% Librarian I01-47ZUp[U"^#^ O(p[bAAA_SYSTEM_CELLSABDDEFLACBDEF;ACMDEFTACMEAGENT_CB_DEFACMEAGENT_CO_DEF@ACMEAGENT_DATA_DEF  ACP_ROUTINES" vADBDEF+ vADPDEFi AIBDEFq ALFDEFy "APECSDEF APLDDEF AQBDEF JARBDEF ARCDEF FAREADEF bASSYMDEF H ASTSTKDEF @BBDDEF BBMDEF! *BBSDEF( BDDEFBKTDEFS BNAMDEF[ rBODDEFm BOOCMDDEF} d BOOPARDEF BOOSTATEDEF0BOO_IO_SUPPORT.t COM_ROUTINESSdo6LEVTDEFw6N LGIINTDEF6LHBDEF! LIB_BIGPAGED LIB_TYPES6LILDEF6pLIRDEF6LKBDEF6<LLBDEF6LMBDEF 7\ LMFITMDEF7Z LNMSTRDEFI LNM_ROUTINESRLOADABLE_IMAGE_SETUP-7LOGDEF97LOOPDEFA7LPBDEFJ7`LSBDEF88zMADEF?8MBADEFW8@MBOXDEFe8 MBR_INFODEFw8ZMBXDEF8MCBDEF8MCBUSDEF`DMGT$C_ROUTINES MGT_MACROS MMG_FUNCTIONSiL MMG_ROUTINES>MPDEV_ROUTINESR MT_ROUTINESOSLVMSBDDEFCCBDEF COM_ROUTINESDCPIDMSG EFIDEF EMBPWRDEF EXEDEF#FMDEFLHD3DEFIA64_ASMIMPDEF" IOHANDLEDEF( KA0902DEF4 LAN_LNMDEF6 LDR_ROUTINESMCBDEF8MSLGDEF <OSLVMS:7PFNDEFCPRIDEFD RAD_MACROSmH S0PAGINGDEFK SCS_ROUTINES SMP_ROUTINESnO SVAPTEDEFQTFDEFNUBMDDEFX VMS_RANDOM[ YMF262_REGeL SDA_CIODEFL SDA_FLAGSDEFLJ SDA_MSGDEF.M SDA_OPTDEF  SDA_ROUTINES;MSDIRDEFDM(SDPDEFMM SECLIBDEF_SECURITY-MACROSTMSGNDEF^MSHADDEFvNSHLDEFN*SHMEMDEFN SHM_CPPDEFN4 SHM_DESCDEFNP SHM_IDDEFNt SHM_REGDEFjSHSBA_ROUTINESN4SLVDEFNSMBDEFOpSMCIDEF SMP_ROUTINESGOSMTDEF[O SNAPFKVECDEF SWIS_ROUTINES SYSAP_MACROSSYSTEM_SERVICE_SETUP SYS_FUNCTIONSjTFDEFMF262_REGej IA64_MCHKDEF IA64_PALDEFNIA64_PAL_ROUTINESZ! IA64_SALDEFn"IA64_SAL_ROUTINES!IAFDEFpIBDTAB!ICAPDEF!ICPDEF!<ICRDDEF!IDBDEF!IDTDEF"IFDDEF"IFSDEF"&IHADEF "RIHDDEF4"IHIDEF<"vIHPDEFD"IHSDEFL"IHVNDEFU"IHXDEF IIC_IOCTL_"IMCBDEF"IMPDEF"IMSEMDEF" INDICTINTDEF" INIRTNDEF@INIT_RTN_SETUP" INTSTKDEF IOC_ROUTINES KA1605DEF` LDR_ROUTINESiCONDEF  CONFIG_TABLE4" COREIODEFDCPBDEF CPUCOMDEFCPUDEFktCQBICDEFuCRABDEFCRAMDEFCRAMHDEFCRBDEFVCRCTXDEFCSBDEF6 CSCHEDDEF5CSDTDEF?CTDDEFO CTLP1FLAGSDEFbCTSIDEFsCWPSDEF"CXBDEF DALDEFPDBRDEFvDCBDEFDCBEDEFDCPIDMSGINESE ERL_ROUTINESO EXE_ROUTINES>FSHWAFSHWA_ROUTINESd GLX_ROUTINES- GPS_ROUTINES8IA64_ASM_; BDLPTRDEFE BKTDEFS BNAMDEF[ rBODDEFm BOOCMDDEF} d BOOPARDEF BOOSTATEDEF0BOO_IO_SUPPORT BPTDEF BRKTDEF (BTADPDEF JBTBDEF BTDDEF- lBUFIODEF8 BUGCHECKDEFI BUGLOGDEF[ h BUSARRAYDEF BUSDEF C2DEF TCADEF CALDEF lCANDEF CBBDEF NCCBDEF CDDBDEF pCDLDEF CDRPDEFt CDTDEF CEBDEF , CHFCTXDEF T CHPCTLDEF & CHPRETDEF.t COM_ROUTINES CDDBDEF pCDLDEF CDRPDEFt CDTDEF CEBDEF , CHFCTXDEF T CHPCTLDEF & CHPRETDEF CIAOLDDEF bCIA_DEF  CIA_MCHKDEFz CIBHANDEF" CIFQDTDEF+CINDEF7\CLASSDEFA CLONEVADEFHCLUBDEFH CLUDCBDEF~CLUDEF CLUEVTIDEF CLUICBDEF CLUOPTDEFRCLUPBDEFP CLURCBDEF CLUSDADEF$ CMNBDLTDEF.t COM_ROUTINESi#DCRDEF0~DDBDEFFjDDTDEF\DEADEFf DEVCFG_CBKDEFqDIAGDEFxNDIDTDEFDIOBDDEFDIOBMDEFDIRDEFtDISPDEFDISPLAY_WILDEFDDJIDEFNDLCDEFDMBDEFNDMPDEF8DPTDEFDQFDEFLDRDEFDSRVDEF#LDTNDEF,*DTSSDEF4DXRDEF>DYNDEFLEFBDEFEFIDEFUTINESE ERL_ROUTINESO EXE_ROUTINES>FSHWAFSHWA_ROUTINESd GLX_ROUTINES- GPS_ROUTINES8IA64_ASM_:z EFI_ROUTINES%zEIAFDEF1EICPDEF:~EIHADEFFEIHDDEF_jEIHIDEFhEIHPDEFrEIHSDEF{.EIHVNDEFb EISABUSDEF[EISDDEFqEMBBCDEF EMBCEHDEFEMBCRDEFEMBDVDEFEMBETDEFtEMBHDDEF EMBINDICTDEFr EMBINFODEFvEMBLMDEFEMBLTDEFEMBMCDEF+ EMBPWRDEFKlEMBSBDEFE ERL_ROUTINESO EXE_ROUTINES>FSHWAFSHWA_ROUTINESd GLX_ROUTINES- GPS_ROUTINES8IA64_ASM]KlEMBSBDEFVEMBSEDEFzEMBSPDEFEMBSSDEF"EMBSUDEFEMBTSDEF4EMBUEDEF4EMBUIDEF:EMBVMDEFrEO1DEFTEO2DEFEO3DEF|EO4DEFERBDEF ERFMBXDEFERLDEF ERLMBXDEFE ERL_ROUTINES EV4DEF>EV5DEF)n EV6MCHKDEFPEVTDEFWB EWDATADEFjEXEDEFO EXE_ROUTINESs\EXTDEF|F11BCDEFF11CDEF>FSHWAFSHWA_ROUTINESd GLX_ROUTINES- GPS_ROUTINES8IA64_ASM .ZU%/* module vms_drivers.h "X-3"*I* Copyright Digital Equipment Corporation, 1993 All Rights Reserved.O* Unpublished rights reserved under the copyright laws of the United States.* L* The software contained on this media is proprietary to and embodies theP* confidential technology of Digital Equipment Corporation. Possession, use,N* duplication or dissemination of the software and media is authorized onlyL* pursuant to a valid written license from Digital Equipment Corporation.* K* RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.G* Government is subject to restrictions as set forth in SubparagraphJ* (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable.* *++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS systemB* routines that begin with the ACP$ and ACP_STD$ prefixes and have* a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits  wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.* * * AUTHOR:* * Leonard S. Szubowicz* * CREATION DATE: 7-Jun-1993* * MODIFICATION HISTORY:* -* X-3 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*1* X-2 JCH703 John C. Hallyburton, Jr. 25-Apr-1995* Add ACP_STD$FASTIO_BLOCK*0* X-1 LSS0279 Leonard S. Szubowicz 7-Jun-1993@* Initial version containing only those routines commonly used* by device drivers.* *--*/#ifndef __ACP_ROUTINES_LOADED#define __ACP_ROUTINES_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define all types that are used in the following function prototypes.*/#include #include #include #include /*P VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/'#define acp_std$access ACP_STD$ACCESS,#define acp_std$accessnet ACP_STD$ACCESSNET*#define acp_std$deaccess ACP_STD$DEACCESS2#define acp_std$fastio_block ACP_STD$FASTIO_BLOCK'#define acp_std$modify ACP_STD$MODIFY%#define acp_std$mount ACP_STD$MOUNT)#define acp_std$readblk ACP_STD$READBLK*#define acp_std$writeblk ACP_STD$WRITEBLK/*N Function prototypes for system routines with the ACP$ and ACP_STD$ prefix.*/>int acp_std$access (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);Aint acp_std$accessnet (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);@int acp_std$deaccess (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);Dint acp_std$fast io_block (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);>int acp_std$modify (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);=int acp_std$mount (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);?int acp_std$readblk (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);@int acp_std$writeblk (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif"#endif /* __ACP_ROUTINES_LOADED */ww|ZUO///////////////////////////////////////////////////////////////////////////////// // FACILITY:// // IPB// // ABSTRACT://D// Header file required to use the routines in boo$io_support.c(// Has all the function prototypes.//// REFERENCE://>// Intel 460GX Chipset System Software Developer's ManualD// Intel IA-64 Architecture Software Debeloper's Manual, Vol. 2// // AUTHOR://// Tony C amuso//// REVISION HISTORY://C// X-10 TLC Tony Camuso 09-Aug-2005>// Add support for PCIe extended config space access.//C// X-9 TLC Tony Camuso 09-Sep-2004C// Add BTADP parameter to boo$read and boo$write routines.//C// X-8 TLC Tony Camuso 17-Apr-2003?// Change the data type in the address argument of theE// boo$in/out routines from int to uint64 . Signed arithmeticB// would scuttle the address space test if the MSB of the(// signed int address were set.//C// X-7 CJ Charles Jaojaroenkul 12-Feb-2003C// Add an address mask for legacy port I/O base addresses.//C// X-6 TLC Tony Camuso 04-Feb-2003C// Compile as 64-bit, require 64-bit for boo$ld*p/boo$st*pA// routines. Set address bit 63 for boo$read*/boo$write*2// routin es for making physical accesses.C// Change address parameters in boo$ld*p/boo$st*p routines// to pointer-to-void.//C// X-5 TLC Tony Camuso 29-Jan-2003-// Add physical load/store routines.//C// X-4 TLC Tony Camuso 27-Jan-2003?// Add constant mask for Port-IO/PCI-IO address space.//(// X-3 PJR Paul Rivera 26-Sep-20025// . Include changes made in X-2 checkin by FAK.*//  . Added memory allocation routines//C// X-2 TLC Tony Camuso 23-Mar-2002L// . Changed read/write pci_config routines to take PCI_NODE_NUMBERE// instead of a raw PCI config address. This abstracts theJ// platform-specific implementation of the structure of the PCI// config address.F// . Added int types while awaiting final version of Compaq C// IA64 x-compiler.L// . Added the PCI_NO DE_NUMBER declaration. Though this is declaredG// in PCIDEF.H, that header file was created with SDL, whichJ// generates macros and pragmas that will gag the gcc compiler.J// But this too shall pass when we do all our compiles with the'// Compaq C IA64 x-compiler.//C// X-1 TLC Tony Camuso 21-Feb-2002// Initial entry.//O/////////////////////////////////////////////////////////////////////////////// #ifndef _BOO$IO_SUPPORT_H_LOADED"#define _BOO$IO_SUPPORT_H_LOADED 1#include #include #include O///////////////////////////////////////////////////////////////////////////////// NODE DATA FUNCTIONSO/////////////////////////////////////////////////////////////////////////////////enum { BOO$K_DDMA_BASE_PA = 1, BOO$K_DDMA_WIN_SIZE, BOO$K_DDMA_BASE_BA, BOO$K_DIRECT_DMA_SIZE, BOO$K_EISA_IO_PORT};O//////////////////////// ///////////////////////////////////////////////////////// IO Address SpacesO/////////////////////////////////////////////////////////////////////////////////enum { BOO$K_IOPORT = 1, BOO$K_IOMEM};M// Offsets into the IO address space will not be great enough to require moreI// than 28 bits. That leaves bits 63:28 for defining the address space in(// either the physical or virtual realm.//1#define IO_ADDR_SPACE_OFFSET_MASK ((1 << 28) - 1)M// Conventional Port IO and !PCI-IO address space is limited to 64 KB of space!// and is partitioned as follows.//// 0xFFFF \// | PCI-IO Space// 0x1000 /// 0x0FFF \$// | Legacy Port IO Space// 0x0000 ///H// The following mask will be used by the read/write and in/out routinesI// to determine which address space is being reference. Addresses greaterL// than this mask value will be referenced as Memory-Mapped IO (MMIO) space.//&#define IO_SPACE_ADDR_MASK 0x0000FFFF"M// When we map I/O port addresses in legacy port I/O memory space, we use the// following memory mask.//#define IO_PORT_MASK 0xFFF4// Legacy PCI and PCIe Extended Config Address flags//"#define PCI_LEGACY_MAX_OFFSET 0xFF#define PCI_LEGACY_ADDR 0#define PCI_EXPRESS_ADDR 1O///////////////////////////////////////////////////////////////////////////////// NODE DATA ROUTINEO/////////////////////////////////////////////////////////////////////////////////@extern int boo$nod #e_data (int iFunctionCode, int *piUserBuffer);O///////////////////////////////////////////////////////////////////////////////'// IO ADDRESS SPACE CONVERSION ROUTINESO/////////////////////////////////////////////////////////////////////////////////;extern uint64 boo$io_va_to_pa( uint64 uqVa, int iIoSpace );;extern uint64 boo$io_pa_to_va( uint64 uqPa, int iIoSpace );O///////////////////////////////////////////////////////////////////////////////// IO SPACE MAPPING ROUTINESO//////// $/////////////////////////////////////////////////////////////////////////<extern uint64 boo$map_io ( uint64 uqPhysAddr, int iSize );<extern void boo$unmap_io ( uint64 uqVirtAddr, int iSize );O///////////////////////////////////////////////////////////////////////////////#// PCI MEMORY SPACE ACCESS ROUTINESO/////////////////////////////////////////////////////////////////////////////////@// The following routines provide access to PCI Memory space and// i460gx CSR space//6// T %here are two prototypes provided for each routine.//>// #define BOO_NEW_PARAMS - the routines require the BTADP arg//M// If the user does not #define BOO_NEW_PARAMS, the routines will not require// the BTADP argument.//#ifdef BOO_NEW_PARAMSSextern uint8 boo$readb ( uint64 uqVirtIoAddr, BTADP* pBtadp ); // Return a byteSextern uint16 boo$readw ( uint64 uqVirtIoAddr, BTADP* pBtadp ); // Return a wordWextern uint32 boo$readl ( uint64 uqVirtIoAddr, BTADP* pBtadp ); // Return& a longwordWextern uint64 boo$readq ( uint64 uqVirtIoAddr, BTADP* pBtadp ); // Return a quadword//bextern void boo$writeb ( uint64 uqVirtIoAddr, uint8 ubData, BTADP* pBtadp ); // Write a bytebextern void boo$writew ( uint64 uqVirtIoAddr, uint16 uwData, BTADP* pBtadp ); // Write a wordfextern void boo$writel ( uint64 uqVirtIoAddr, uint32 ulData, BTADP* pBtadp ); // Write a longwordfextern void boo$writeq ( uint64 uqVirtIoAddr, uint64 uqData, BTADP* pBtadp ); // Write a 'quadword#elseDextern uint8 boo$readb ( uint64 uqVirtIoAddr ); // Return a byteDextern uint16 boo$readw ( uint64 uqVirtIoAddr ); // Return a wordHextern uint32 boo$readl ( uint64 uqVirtIoAddr ); // Return a longwordHextern uint64 boo$readq ( uint64 uqVirtIoAddr ); // Return a quadword//Sextern void boo$writeb ( uint64 uqVirtIoAddr, uint8 ubData ); // Write a byteSextern void boo$writew ( uint64 uqVirtIoAddr, uint16 uwData ); // Write a wordWextern void boo$wr (itel ( uint64 uqVirtIoAddr, uint32 ulData ); // Write a longwordWextern void boo$writeq ( uint64 uqVirtIoAddr, uint64 uqData ); // Write a quadword#endifO///////////////////////////////////////////////////////////////////////////////O/////////////////////////////////////////////////////////////////////////////// // PORT IO SPACE ACCESS ROUTINESO/////////////////////////////////////////////////////////////////////////////////J// NOTE: No need to call boo$map_io(). Just ca )ll the routine with the portK// number. The 64 KB (64 MB swizzled) of port IO space is permanently// mapped once for all.//#// Example: Write 'A' to port 0x3F8//// boo$outb( 0x3f8, 'A' );//Iextern uint8 boo$inb ( uint64 iIoPort ); // Read a byte from a portIextern uint16 boo$inw ( uint64 iIoPort ); // Read a word from a portMextern uint32 boo$inl ( uint64 iIoPort ); // Read a longword from a port//Textern void boo$outb ( uint64 iIoPort, uint8 u *bData ); // Write a byte to a portTextern void boo$outw ( uint64 iIoPort, uint16 uwData ); // Write a word to a portXextern void boo$outl ( uint64 iIoPort, uint32 ulData ); // Write a longword to a portO///////////////////////////////////////////////////////////////////////////////O///////////////////////////////////////////////////////////////////////////////)// PHYSICAL ADDRESS SPACE ACCESS ROUTINESO///////////////////////////////////////////////////////////////////////////////+////&#pragma __required_pointer_size __save"#pragma __required_pointer_size 64)extern uint8 boo$ldbp( void* pubAddr );(extern uint16 boo$ldwp( void* puwAddr );(extern uint32 boo$ldlp( void* pulAddr );(extern uint64 boo$ldqp( void* puqAddr );//6extern void boo$stbp( void* pubAddr, uint8 ubData );5extern void boo$stwp( void* puwAddr, uint16 uwData );5extern void boo$stlp( void* pulAddr, uint32 ulData );5extern void boo$stqp( void* puqAddr, uint64 uqData );)#pragma __required_p,ointer_size __restoreO///////////////////////////////////////////////////////////////////////////////// PCI CONFIG ACCESS FUNCTIONSO/////////////////////////////////////////////////////////////////////////////////// boo$read'x'_pci_config//// boo$write'x'_pci_config//B// Where 'x' is one of b, w, l for 8, 16, and 32-bit accesses// respectively.//O// Access PCI Config space given a pointer to the caller's PCI_NODE_NUMBER// structure.//// BIT -FIELD// =========//#// 2:0 function number!// 7:3 device number// 15:8 bus number#// 31:16 register offset//=extern uint8 boo$readb_pci_config( PCI_NODE_NUMBER *psPnn );=extern uint16 boo$readw_pci_config( PCI_NODE_NUMBER *psPnn );=extern uint32 boo$readl_pci_config( PCI_NODE_NUMBER *psPnn );//Kextern void boo$writeb_pci_config( PCI_NODE_NUMBER *psPnn, uint8 ubData );Kextern void boo$writew_pci_config( PCI_NODE_NUMBER * .psPnn, uint16 uwData );Kextern void boo$writel_pci_config( PCI_NODE_NUMBER *psPnn, uint32 ulData );O///////////////////////////////////////////////////////////////////////////////O///////////////////////////////////////////////////////////////////////////////// MEMORY ALLOCATION ROUTINESO/////////////////////////////////////////////////////////////////////////////////fextern int boo$alloc_contig_mem(int req_size, void **ret_phy_addr, int *ret_size,void **ret_vir_addr);Lextern int boo/$dealloc_contig_mem(void *phy_addr, int size, void *vir_addr);"#endif // _BOO$IO_SUPPORT_H_LOADEDwwZU/**I* Copyright Digital Equipment Corporation, 1993 All Rights Reserved.O* Unpublished rights reserved under the copyright laws of the United States.* L* The software contained on this media is proprietary to and embodies theP* confidential technology of Digital Equipment Corporation. Possession, use,N* duplication or dissemination of the softw0are and media is authorized onlyL* pursuant to a valid written license from Digital Equipment Corporation.* K* RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.G* Government is subject to restrictions as set forth in SubparagraphJ* (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable.* *++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS systemB* routin1es that begin with the COM$ and COM_STD$ prefixes and have* a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is 2used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the type3s defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passe4d by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointe5r to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.* * * AUTHOR:* * Leonard S. Szubowicz* * CREATION DATE: 7-Jun-1993* * MODIFICATION HISTORY:* -* X-2 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*0* X-1 LSS0279 Leonard S. Szubowicz 7-Jun-1993@* Initial version cont6aining only those routines commonly used* by device drivers.* *--*/ #ifndef __COM_ROUTINES_LOADED#define __COM_ROUTINES_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define all types that are used in the following function protot7ypes.*/#include #include #include #include #include #include #include /*P VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/.#define com_std$delattnast COM_STD$DELATTNAST0#define com_std$delattnastp COM_STD$DELATTNASTP.#def 8ine com_std$delctrlast COM_STD$DELCTRLAST0#define com_std$delctrlastp COM_STD$DELCTRLASTP.#define com_std$drvdealmem COM_STD$DRVDEALMEM.#define com_std$flushattns COM_STD$FLUSHATTNS.#define com_std$flushctrls COM_STD$FLUSHCTRLS##define com_std$post COM_STD$POST.#define com_std$post_nocnt COM_STD$POST_NOCNT.#define com_std$setattnast COM_STD$SETATTNAST.#define com_std$setctrlast COM_STD$SETCTRLAST/*N Function prototypes for system routines with the COM$ and COM_STD$ prefix. 9*/2void com_std$delattnast (ACB **acb_lh, UCB *ucb);=void com_std$delattnastp (ACB **acb_lh, UCB *ucb, int ipid);Avoid com_std$delctrlast (ACB **acb_lh, UCB *ucb, int matchchar, - int32 *inclchar_p);Lvoid com_std$delctrlastp (ACB **acb_lh, UCB *ucb, int ipid, int matchchar, . int32 *inclchar_p);%void com_std$drvdealmem (void *ptr);Fint com_std$flushattns (PCB *pcb, UCB *ucb, int chan, ACB **acb_lh);Eint com_std$flushctrls (PC :B *pcb, UCB *ucb, int chan, ACB **acb_lh,) int32 *mask_p);(void com_std$post (IRP *irp, UCB *ucb);$void com_std$post_nocnt (IRP *irp);Pint com_std$setattnast (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb, ACB **acb_lh);Oint com_std$setctrlast (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb, ACB **acb_lh,3 int mask, TAST **tast_p);R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __ ;restore /* Restore the previously-defined required ptr size */#endif"#endif /* __COM_ROUTINES_LOADED */ww@ZU/* module EFI_ROUTINES.H "X-2"*I*************************************************************************I* *I* Copyright 2002 Compaq Computer Corporation *I* *I* COMPAQ Registered in U.S. Pa<tent and Trademark Office. *I* *I* Confidential computer software. Valid license from Compaq or *I* authorized sublicensor required for possession, use or copying. *I* Consistent with FAR 12.211 and 12.212, Commercial Computer Software, *I* Computer Software Documentation, and Technical Data for Commercial *I* Items are licensed to the U.S. Government under vendor's standard *I* co=mmercial license. *I* *I* Compaq shall not be liable for technical or editorial errors or *I* omissions contained herein. The information in this document is *I* subject to change without notice. *I* *I******************************************************>********************++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* B* This module contains the C function prototypes for the IA64 PAL +* routines that begin with the EFI$ prefix.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works ev ?en in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected@ to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used Ainstead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:B** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.*/* 6. Mixed pointer sizes within one argumentF* If a 64-bit pointer is being passed by reference, the reference to ?* the pointer should also be 64 bits wide to avoid confusion. * For example:* * PTE_PPQ va_pte_p;* VOID_PPQ start_va_p;C ** should be used instead of:** PTE_PQ *va_pte_p;* VOID_PQ *start_va_p;* * * AUTHOR:* * Karen L. Noel* * CREATION DATE: 30-Jan-2002* * MODIFICATION HISTORY:*)* X-2 KLN3121 Karen L. Noel 31-Oct-2002%* Remove extra pointer_size pragmas.**--*/#ifndef __EFI__ROUTINES_LOADED #define __EFI__ROUTINES_LOADED 1&#pragma __required_pointer_size __save&#pragma __required_pointer_size __long/*G* Define all types that are uDsed in the following function prototypes.*/#include #include #include typedef struct _efi_fpswa_ret { __int64 status; unsigned __int64 err1; unsigned __int64 err2; unsigned __int64 err3;} EFI_FPSWA_RET;@int exe$call_fpswa (INTSTK * intstk, EFI_FPSWA_RET * fpswa_ret);0typedef EFI_FPSWA_RET (EFI_FPSWA)(int trap_type, unsigned __int64 bundle_p, unsigned __int64 *ipsr_p, unsigned __int64 *fsr_p, unsigned __int64 *isr_Ep, unsigned __int64 *preds_p, unsigned __int64 *ifs_p, FP_STATE *fp_state_p);:#pragma linkage_ia64 fpswa_linkage=(result(r8,r9,r10,r11)).#pragma use_linkage fpswa_linkage (EFI_FPSWA)extern EFI_FPSWA *exe$ar_fpswa;!int efi$set_virtual_address_map ( unsigned __int64 mmap_size, " unsigned __int64 mmap_desc_size,) unsigned int mmap_desc_version, ! EFI_MEMORY_DESCRIPTOR * mmap_p);)#pragma __required_pointer_size __restore'#endif /* __IA64_PAL_ROUTINES_LO FADED */ww`ZU/**I* Copyright Digital Equipment Corporation, 1993 All Rights Reserved.O* Unpublished rights reserved under the copyright laws of the United States.* L* The software contained on this media is proprietary to and embodies theP* confidential technology of Digital Equipment Corporation. Possession, use,N* duplication or dissemination of the software and media is authorized onlyL* pursuant to a valid written license from Digital EquipmenGt Corporation.* K* RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.G* Government is subject to restrictions as set forth in SubparagraphJ* (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable.* *++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS systemB* routines that begin with the ERL$ and ERL_STD$ prefixes and have* a standard call interface.* * H NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is Ithe returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included belJow.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedOK* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* L UCB structure.* * * AUTHOR:* * Leonard S. Szubowicz* * CREATION DATE: 7-Jun-1993* * MODIFICATION HISTORY:*** X-3 RAB053 Robert A. Brooks 03-Mar-2003;* Add optional 3rd parameter (IRP) to erl_std$devicerr and* ioc_std$devicetmo.* -* X-2 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*0* X-1 LSS0279 Leonard S. SzubowiczM 7-Jun-1993@* Initial version containing only those routines commonly used* by device drivers.* *--*/ #ifndef __ERL_ROUTINES_LOADED#define __ERL_ROUTINES_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define all types that areN used in the following function prototypes.*/#include #include #include /*P VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/*#define erl_std$allocemb ERL_STD$ALLOCEMB.#define erl_std$deviceattn ERL_STD$DEVICEATTN*#define erl_std$devicerr ERL_STD$DEVICERR*#define erl_stOd$devictmo ERL_STD$DEVICTMO,#define erl_std$releasemb ERL_STD$RELEASEMB/*N Function prototypes for system routines with the ERL$ and ERL_STD$ prefix.*/3int erl_std$allocemb (int size, EMBDV **embdv_p);8void erl_std$deviceattn (int64 driver_param, UCB *ucb);<void erl_std$devicerr (int64 driver_param, UCB *ucb, ... );<void erl_std$devictmo (int64 driver_param, UCB *ucb, ... );'void erl_std$releasemb (EMBDV *embdv);R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr P size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif"#endif /* __ERL_ROUTINES_LOADED */wwxZU/* module EXE_ROUTINES.H "X-90"*I*************************************************************************I* *I* HPE CONFIDENTIAL. This software is confidential proprietary software *I* licensed by Hewlett Packard Enterprise DQevelopment, LP, and is not *I* authorized to be used, duplicated or disclosed to anyone without the *I* prior written permission of HPE. *I* Copyright 2017 Hewlett Packard Enterprise Development, LP *I* *I* VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *I* proprietary software licensed by VMS Software, Inc., and is not *I* authorized to Rbe used, duplicated or disclosed to anyone without *I* the prior written permission of VMS Software, Inc. *I* Copyright 2017-2023 VMS Software, Inc. *I* *I**************************************************************************++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS sSystemB* routines that begin with the EXE$ and EXE_STD$ prefixes and have* a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generi Tc "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototyUpes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. VParameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlWen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.*/* 6. Mixed pointer sizes within one argumentF* If a 64-bit pointer is being passed by reference, the reference to ?* the pointer should also be 64 bits wide to avoid confusion. * For example:* * PTE_PPQ va_pte_p;* VOID_PPQ start_va_p; ** should be used instead of:** PTE_PQ *va_pte_p;* VOID_PQ *start_va_p;* * * AUXTHOR:* * Leonard S. Szubowicz* * CREATION DATE: 8-Jun-1993*V* NOTE WELL: Structure datatypes defined in STARLET must generally must be specifiedU* as 'struct _xxxx' rather than the typedef form 'XXXX' or 'xxxx'. ThisH* is because there is no guarantee that the module which includesI* this file will have __NEW_STARLET in place. Thus you don't know#* which typedef form to use.** MODIFICATION HISTORY:*$* X-90 DAG Doug Gordo Yn 23-May-20237* Add the long-missing optional status argument to the * EXE$KP_END prototype. BO-1228*(* X-89 CEG0435 Clair Grant 19-Apr-2018;* Include decc$types.h and redefine exe$kvprintf prototype* Verify conditionals.*C* X-88 MLW Michael Winiarski 25-Jan-2018?* Revert exe$kvprintf prototype change from X-87.B* The attempted fix causes collateral build failuresA* in other facilities due to varargs.h vs.Z stdarg.h+* variable argument handling.*C* X-87 MLW Michael Winiarski 19-Jan-2018+* Fix exe$kvprintf prototype.*#* X-86 AHM Drew Mason 22-Dec-20170* Revert declaration of ini$brk to return void.*#* X-85 AHM Drew Mason 15-Nov-2017:* Update copyright. Add return value to ini$brk for x86.*@* X-84 RCL Rick Lord 6-Feb-06*K* a) Delete EXE$KP_SPL_ACQUIREL/RELEASEL/RESTO [REL - we do notJ* store a KPB's current spinlock context anymore, insteadJ* refreshing it when necessary (stall, re/start, end), so9* these routines are no longer necessary*N* b) Add EXE$SPL_CTX_SET, a no-KPB version of EXE$KP_SPL_CTX_SET*O* c) Change the last parameter of EXE$KP_SPL_RE/START and the 2ndL* parameter of EXE$KP_SPL_UPDATE_KPB so it's a set of flagsO* instead o \f a current spinlock context; all we really need toI* know at this boundary is which spinlocks are not to be-* released by the active KPB*L* d) Delete the last parameter to EXE$KP_TQE_WAIT, EXE$KP_FORKL* and EXE$KP_FORK_WAIT - it used to be a requested spinlockK* context, but for sort-of consistency with the stock codeF* the KP will now be restarted with the same spinlock/* ] context with which it stalls*)* X-83 KLN3620 Karen L. Noel 1-Feb-2006"* Add exe$credit_bytcnt_bytlm_id.** X-82 RCL Rick Lord 5-Oct-05* Add EXE$KP_SPL_INIT_KPB* * X-81 RCL Rick Lord 23-Aug-057* a) Add a #include of SPLDEF to resolve references to9* SPL structures in EXE$KP_SPL_* routine prototypes;* b) Add #defines of lower-case exe$kp_spl_* routine names2* c) Add prototypes for new EXE$KP_SPL_* routines*)* X-78,79 WBF Burns Fisher 07-Jun-20044* Put^ in pragma linkage for EXE$REVERT_WHOLE_PGM...*+* X-75,76,77 WBF Burns Fisher 18-Mar-2004,* Add whole program floating point routines*$* X-74 DAG Doug Gordon 15-May-2003B* Add EXE$KP_ALLOC_MEM_STACK_USER, EXE$KP_DEALLOC_MEM_STACK_USER,,* EXE$KP_USER_ALLOC_KPB, EXE$KP_STACK_PEAKS*$* X-73 DAG Doug Gordon 8-Apr-20035* exe$kp_alloc_rse_stack_p2_any is a 64-bit routine.*** X-72 KLN3248 Karen L. Noel 26-Mar-2003* Add exe$setstk_64_int.*0* X-71 KLN3246 Karen L. Noe_l 21-Mar-2003** o Promote exe_std$expandstk to 64-bits.'* o Add exe$kp_alloc_rse_stack_p2_any.*+* X-70 Anne McElearney 14-Feb-2003** Remove stdarg.h due to build conflicts 5* and instead define va_list parameter to be char **+* X-69 Anne McElearney 13-Feb-20032* In addition to the va_list change, also include5* stdarg.h to make sure we get the va_* definitions. * (Eiche)*+* X-68 Anne McElearney 13-Feb-20031* Fix exe$kvprintf prototyp`e. Ghostwriter: Eiche*+* X-67 Anne McElearney 12-Feb-2003** Add exe$kprintf,exe$kvprintf prototypes*)* X-66 KLN3210 Karen L. Noel 5-Feb-2003!* Two more exe$rseregs routines.*** X-65 KLN3190 Karen L. Noel 15-Jan-2003* Add exe$rseregs routines.*$* X-64 DAG Doug Gordon 17-Dec-2002,* Add the new KP stack allocation routines.*$* X-63 DAG Doug Gordon 22-Nov-20028* Promote exe$lal_insert_first and exe$lal_remove_first6* to use long pointers. (And yes, thea listhead can be6* in 64-bit space, the list elements are 32-bit only)*%* X-62 WBF Burns Fisher 11-Nov-20021* Change comment to slash-star for STANDARD=VAXC*%* X-61 WBF Burns Fisher 23-Oct-2002<* Add exe_std$expandstk and for IA64, add the floating save * routines*)* X-60 RAB Richard A. Bishop 31-Oct-2001:* The changes in X-59 give problems with level4 checking.)* Disable NOPARMLIST errors around them.*%* X-59 Anne McElearney 20-Jul-2001B* Remove argument d beclaration from error_rtn in exe_std$readlock,F* exe_std$writelock, and exe_std$modifylock. They were not accountingG* for an optional argument as the last parameter to the error routine.F* The routine still expects the parameters, they are just not definedB* in the prototype. The addition of the last parameter could not@* be added and still allow backward compatability. This fixes * PTR 75-45-194.*%* X-58 JRK Jim Kauffman 12-Jun-2001* Add exe$cbb_zero_range*%* X-57 WBF c Burns Fisher 14-Jul-2000;* Add optional arguments to exe$allocate_pool and friends.6* Happy Bastille Day! Libert, galit, fraternit! *$* X-56 TJP Tom Provost 13-Jul-2000;* Add exe_std$iofork_cpu prototype to provide a C-callable.* interface to iofork_cpu macro in iomar.mar.*)* X-55 JMB218 James M. Blue 9-Mar-2000<* Add exe_std$qioserver_new_unit prototype for activating a8* newly discovered QIOServer capabale unit. Delete the=* exe_std$qsrv_srvr_fdt prototype, itd has been replaced with* a DDT entry at QSRV_HELPER.*0* X-54 LSS0406 Leonard S. Szubowicz 10-Feb-2000?* Part of the fix for CLDs 70-3-2729 and 70-3-2599: MultipathA* internal I/O that was sent to a UCB by calling EXE_STD$INSIOQCC* would increment UCB$L_QLEN but never decrement it on completion.7* Add prototype for new routine EXE_STD$INSIOQ_SIMPLE.*** X-53 KLN2123 Karen L. Noel 14-Jan-2000%* Add exe_std$alophycntg_color[_s2].*&* X-52 RAE Rae Eastland 15-Oct-19996e* Add routine prototypes for exe$lal_insert_first and* exe$lal_remove_first.*&* X-51 JMB James M. Blue 22-Jul-19997* Add routine prototype for a QIOServer server to call.* a FDT routine to fix-up a client's request.*%* X-50 Ruth Goldenberg 06-Jul-19986* Change EXE_STD$WRTMAILBOX to accept variable number7* of arguments so CSP can call it with the EPID to be 7* associated with a termination message for a remotely* created process.*+* X-49 KLN2084 Karen L. Noel 0f5-June-19987* Correct the prototype for exe$register_pool_info to * accept 64-bit pointers.*** X-48 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*** X-47 KLN2077 Karen L. Noel 20-May-1998<* Ignore NOPARMLIST informationals where approriate so that3* level4 checking can be used with the C compiler.*)* X-46 EMB Ellen M. Batbouta 02-Apr-19989* Add prototype g definition for routines, Exe$cbb_insert_8* bitmask and Exe$cbb_boolean_oper. Remove definitions9* for routines, Exe$cbb_set_bits and Exe$cbb_clear_bits.*)* X-45 EMB Ellen M. Batbouta 04-Mar-19986* Add prototype definition for routine, Exe$cbb_zero.*)* X-44 EMB Ellen M. Batbouta 25-Feb-19989* Add a flags input parameter to the following routines::* Exe$cbb_copy, Exe$find_first_set, Exe$find_first_clear,5* Exe$cbb_empty, Exe$cbb_test_bit, Exe$cbb_rebuild, ;* Exe$cbb_extrahct_bitmask, Exe$cbb_set_bit, Exe$cbb_clear_1* bit, Exe$cbb_set_bits, and Exe$cbb_clear_bits.*:* Add prototype definition for routine, Exe$cbb_validate.*)* X-43 EMB Ellen M. Batbouta 13-Feb-19982* Bugfix for X-42 - missing ; (how embarrassing!)*)* X-42 EMB Ellen M. Batbouta 12-Feb-19989* Add prototype definition for routine, Exe$cbb_extract_ * bitmask.*)* X-41 EMB Ellen M. Batbouta 11-Feb-1998:* Add prototype definition for routine, Exe$event_notify.*)* X-40 EMB i Ellen M. Batbouta 16-Jan-19986* Add prototype definition for routine, Exe$cbb_copy.*)* X-39 EMB Ellen M. Batbouta 17-Dec-1997:* Change the prototypes for the routines, Exe$cbb_set_bit?* (remove ccode parameter) and Exe$cbb_test_bit (remove state * parameter).*)* X-38 EMB Ellen M. Batbouta 11-Dec-19979* Change the prototype for the Exe$cbb_allocate routine.7* The output parameter, cbb, should be cast as CBB_PPQ<* rather than CBB_PQ. A level of indirection was missing.j*)* X-37 EMB Ellen M. Batbouta 04-Dec-1997@* Add timeout_value parameter to the routines, exe$cbb_allocate* and exe$cbb_initialize*(* X-36 JRK388 Jim Kauffman 10-Nov-19976* Clean up far_pointer prototype definitions for CBBs*(* X-35 JRK388 Jim Kauffman 6-Nov-1997* Add CBB routine prototypes*!* X-34 Ken Follien 25-Jul-1997** Changed exe$primitive_mcheck prototype.*"* X-33 Andy Kuehnel 17-Jun-1997/* Remove never implemented callback interface.** (kget back in line with VDE)*$* X-30 KJF Ken Follien 21-Apr-19973* Add exe$primitive_mcheck, exe$setup_memtest_env,* and exe$clear_memtest_env.*)* X-28 EMB Ellen M. Batbouta 04-Nov-1996* Add exe$check_for_mem_error.*%* X-27 WBF Burns Fisher 06-Aug-1996/* Add new user param to EXE$REGISTER_POOL_INFO*"* X-27 Andy Kuehnel 9-Jul-1996* Add exe_std$chkflupages.*+* X-26 WBF Burns Fisher 29-May-19969* Update exe$register_pool_info parameters to match slpec*+* X-25 PKW350 Paul K. M. Weiss 14-May-1996(* Add exe$lock_pkta and exe$unlock_pkta*&* X-24 DMB Dave Bernardo 04-May-1996$* Change POOL_TYPE to MMG$POOL_TYPE*%* X-23 WBF Burns Fisher 2-May-19965* Add function protos for exe$allocate_pool routines*-* X-22 NYK538 Nitin Y. Karkhanis 31-Jan-19968* Modify function prototype for EXE_STD$NAM_TO_PCB such<* that the PIDADR and PRCNAM arguments are 64-bit pointers.*-* X-21 NYK455 Nitin Y. Karkhanis 20-Jul-19957* m Add function prototypes for exe$bugchk_remove_va and* exe$bugchk_cancel_remove_va.*** X-20 KLN1458 Karen L. Noel 17-Jul-1995=* Change desciptor pointer types to void pointers and remove?* the include of descrip.h (it causes library version mismatch>* headaches when one library includes a module from another).*** X-19 KLN1457 Karen L. Noel 05-Jun-1995* Add some posix routines.*(* X-18 JRK369 Jim Kauffman 23-May-1995* Add exe$nam_to_pcb*** X-17 KLN1447 Karen nL. Noel 26-Apr-19950* Conditionalize exe_std$probe*_dsc64 protos on* __INITIAL_POINTER_SIZE.*** X-16 KLN1445 Karen L. Noel 25-Apr-19953* Add protos for 64-bit descriptor probe routines.*3* X-15 JCH703b John C. Hallyburton, Jr. 6-Mar-1995* Add EXE_STD$CREDIT_BYTCNT.*0* X-14 LSS0325 Leonard S. Szubowicz 24-Feb-1995;* 64-Bit Virtual Addressing: Add EXE_STD$LOCK_ERR_CLEANUP.*0* X-13 LSS0320 Leonard S. Szubowicz 15-Feb-1995@* 64-Bit Virtual Addressing: Support 64-bit o buffer addresses on@* the EXE_STD$xCHK and EXE_STD$xLOCK prototypes if the compiler* supports them.*0* X-12 LSS0321 Leonard S. Szubowicz 10-Feb-1995-* 64-bit IOSB address on EXE_STD$SYNCH_LOOP.*2* X-11 WDB64B1 Walter D. Blaschuk, Jr. 2-Feb-1995=* 64-bit Virtual Addressing/BUFIO changes: Add 5* exe_std$alloc_bufio_32, exe_std$alloc_bufio_64 and* exe_std$alloc_diagbuf.2* ** X-10 KLN1365 Karen L. Noel 19-Jan-19p95&* Add exe_std$debit_bytcnt_bytlm_alo.*(* X-9 KLN1360 Karen L. Noel 5-Jan-1995,* Add exe_std$alopaged and exe_std$deapaged*2* X-8 JCH703a John C. Hallyburton, Jr. 6-Dec-1994"* Add EXE_STD$CHECK_DEVICE_ACCESS* ,* X-7 NYK143 Nitin Y. Karkhanis 18-Nov-1994* Add exe_std$alophycntg_s2.*1* X-6 JCH703 John C. Hallyburton, Jr. 3-Nov-19944* Add EXE_STD$*P1* memory allocation/dealllocation.*/* X-5 LSS0308 Leonard S. Szubowicz 11-May-1994=* Add function prototype for inqi$brk. Although this routine@* does not begin with the exe prefix, this is probably the best* place for it.*/* X-4 LSS0308 Leonard S. Szubowicz 5-May-1994C* Add function prototypes for exe$kp_find_kpb and exe$kp_tqe_wait.*&* X-3 SDD Steve DiPirro 04-Feb-1994;* Reverse parameter order in exe_std$deanonpgdsiz function* prototype definition.* +* X-2 DEE0198 David E. Eiche 16-Sep-1993=* Add definitions for EXE_STD_PROBEW and EXE_STD$PROBEW_DSC.*0* X-1 LSS0279 rLeonard S. Szubowicz 8-Jun-1993@* Initial version containing only those routines commonly used* by device drivers.* *--*/#ifndef __EXE_ROUTINES_LOADED#define __EXE_ROUTINES_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define sall types that are used in the following function prototypes.*/#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #inclutde /* X-81a */#include #include D#ifdef __ia64 /* Verified for IA64 port - KLN; x86 - Clair Grant */#include #include #endif/*P VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/)#define exe_std$abortio EXE_STD$ABORTIO6#define exe_std$alloc_bu ufio_32 EXE_STD$ALLOC_BUFIO_326#define exe_std$alloc_bufio_64 EXE_STD$ALLOC_BUFIO_644#define exe_std$alloc_diagbuf EXE_STD$ALLOC_DIAGBUF*#define exe_std$allocbuf EXE_STD$ALLOCBUF*#define exe_std$allocceb EXE_STD$ALLOCCEB*#define exe_std$allocirp EXE_STD$ALLOCIRP*#define exe_std$allocjib EXE_STD$ALLOCJIB*#define exe_std$allocpcb EXE_STD$ALLOCPCB*#define exe_std$alloctqe EXE_STD$ALLOCTQE0#define exe_std$alononpaged EXE_STD$ALONONPAGED*#define exe_std$alopaged EXE_STD$ALOPAGED,#defin ve exe_std$alop1imag EXE_STD$ALOP1IMAG,#define exe_std$alop1proc EXE_STD$ALOP1PROC.#define exe_std$alophycntg EXE_STD$ALOPHYCNTG4#define exe_std$alophycntg_s2 EXE_STD$ALOPHYCNTG_S29#define exe_std$alophycntg_color EXE_STD$ALOPHYCNTG_COLOR?#define exe_std$alophycntg_color_s2 EXE_STD$ALOPHYCNTG_COLOR_S2,#define exe_std$altquepkt EXE_STD$ALTQUEPKTC#define exe$bugchk_cancel_remove_va EXE$BUGCHK_CANCEL_REMOVE_VA5#define exe$bugchk_remove_va EXE$BUGCHK_REMOVE_VA(#define exe$bus_ wdelay EXE$BUS_DELAY!#define exe$delay EXE$DELAY*#define exe_std$carriage EXE_STD$CARRIAGE.#define exe$cbb_allocate EXE$CBB_ALLOCATE0#define exe$cbb_clear_bit EXE$CBB_CLEAR_BIT4#define exe$cbb_clear_range EXE$CBB_CLEAR_RANGE(#define exe$cbb_empty EXE$CBB_EMPTY=#define exe$cbb_find_first_clear EXE$CBB_FIND_FIRST_CLEARK#define exe$cbb_find_first_clear_nolock EXE$CBB_FIND_FIRST_CLEAR_NOLOCK9#define exe$cbb_find_first_set EXE$CBB_FIND_FIRST_SETG#define x exe$cbb_find_first_set_nolock EXE$CBB_FIND_FIRST_SET_NOLOCK.#define exe$cbb_get_size EXE$CBB_GET_SIZE2#define exe$cbb_initialize EXE$CBB_INITIALIZE&#define exe$cbb_lock EXE$CBB_LOCK,#define exe$cbb_rebuild EXE$CBB_REBUILD,#define exe$cbb_set_bit EXE$CBB_SET_BIT.#define exe$cbb_test_bit EXE$CBB_TEST_BIT*#define exe$cbb_unlock EXE$CBB_UNLOCK&#define exe$cbb_copy EXE$CBB_COPY?#define exe$cbb_extract_bitmask EXE$CBB_EXTRACT_BITMASK>#define y exe$cbb_insert_bitmask EXE$CBB_INSERT_BITMASK.#define exe$cbb_validate EXE$CBB_VALIDATE&#define exe$cbb_zero EXE$CBB_ZERO5#define exe$cbb_boolean_oper EXE$CBB_BOOLEAN_OPER?#define exe_std$check_device_access EXE_STD$CHECK_DEVICE_ACCESS.#define exe_std$chkpro_int EXE_STD$CHKPRO_INT0#define exe_std$chkcreacces EXE_STD$CHKCREACCES0#define exe_std$chkdelacces EXE_STD$CHKDELACCES0#define exe_std$chkexeacces EXE_STD$CHKEXEACCES0#define exe_std$chklogacces EXE_STD$CHKLOGA zCCES0#define exe_std$chkphyacces EXE_STD$CHKPHYACCES.#define exe_std$chkrdacces EXE_STD$CHKRDACCES0#define exe_std$chkwrtacces EXE_STD$CHKWRTACCES4#define exe_std$credit_bytcnt EXE_STD$CREDIT_BYTCNT?#define exe_std$credit_bytcnt_bytlm EXE_STD$CREDIT_BYTCNT_BYTLME#define exe$credit_bytcnt_bytlm_id EXE$CREDIT_BYTCNT_BYTLM_ID9#define exe_std$cvt_ipid_to_epid EXE_STD$CVT_IPID_TO_EPID8#define exe_std$cvt_ipid_to_pcb EXE_STD$CVT_IPID_TO_PCB*#define exe_std$deapaged EXE_STD$DEAPAGED {0#define exe_std$deanonpaged EXE_STD$DEANONPAGED2#define exe_std$deanonpgdsiz EXE_STD$DEANONPGDSIZ.#define exe_std$deap1block EXE_STD$DEAP1BLOCK%#define exe_std$deap1 EXE_STD$DEAP12#define exe_std$debit_bytcnt EXE_STD$DEBIT_BYTCNT9#define exe_std$debit_bytcnt_alo EXE_STD$DEBIT_BYTCNT_ALOC#define exe_std$debit_bytcnt_bytlm_nw EXE_STD$DEBIT_BYTCNT_BYTLM_NWE#define exe_std$debit_bytcnt_bytlm_alo EXE_STD$DEBIT_BYTCNT_BYTLM_ALO*#define exe_std$finishio EXE_STD$FINISHIO(#define exe$ |illiofunc EXE$ILLIOFUNC.#define exe_std$insert_irp EXE_STD$INSERT_IRP'#define exe_std$insioq EXE_STD$INSIOQ)#define exe_std$insioqc EXE_STD$INSIOQC4#define exe_std$insioq_simple EXE_STD$INSIOQ_SIMPLE)#define exe_std$instimq EXE_STD$INSTIMQ:#define exe_std$iofork_cpu EXE_STD$IOFORK_CPU,#define exe_std$iorsnwait EXE_STD$IORSNWAIT4#define exe$kp_allocate_kpb EXE$KP_ALLOCATE_KPBG#define exe$kp_alloc_rse_stack_p2_any EXE$KP_ALLOC_RSE_STACK_P2_ANY7#define ex }e$kp_deallocate_kpb EXE$KP_DEALLOCATE_KPB##define exe$kp_end EXE$KP_END,#define exe$kp_find_kpb EXE$KP_FIND_KPB%#define exe$kp_fork EXE$KP_FORK.#define exe$kp_fork_wait EXE$KP_FORK_WAIT*#define exe$kp_restart EXE$KP_RESTART5#define exe$kp_stall_general EXE$KP_STALL_GENERAL&#define exe$kp_start EXE$KP_START.#define exe_std$kp_startio EXE_STD$KP_STARTIO,#define exe$kp_tqe_wait EXE$KP_TQE_WAITC#define exe$kp_alloc_mem_stack_user EXE$KP_ALLOC_MEM ~_STACK_USERG#define exe$kp_dealloc_mem_stack_user EXE$KP_DEALLOC_MEM_STACK_USER7#define exe$kp_user_alloc_kpb EXE$KP_USER_ALLOC_KPB2#define exe$kp_stack_peaks EXE$KP_STACK_PEAKSJ#define exe$kp_spl_start EXE$KP_SPL_START /* X-81b Start */:#define exe$kp_spl_restart EXE$KP_SPL_RESTART=#define exe$kp_spl_update_kpb EXE$KP_SPL_UPDATE_KPB:#define exe$kp_spl_ctx_set EXE$KP_SPL_CTX_SET@#define exe$kp_spl_stall_general EXE$KP _SPL_STALL_GENERAL;#define exe$kp_spl_tqe_wait EXE$KP_SPL_TQE_WAIT6#define exe$kp_rmvtimq EXE$KP_RMVTIMQ7#define exe$kp_spl_fork EXE$KP_SPL_FORKL#define exe$kp_spl_fork_wait EXE$KP_SPL_FORK_WAIT /* X-81b End */F#define exe$kp_spl_init_kpb EXE$KP_SPL_INIT_KPB /* X-82 */K#define exe$spl_ctx_set EXE$SPL_CTX_SET /* X-84b */0#define exe_std$lcldskvalid EXE_STD$LCLDSKVALID9#define exe_std$lock_err_clean up EXE_STD$LOCK_ERR_CLEANUP,#define exe_std$maxacmode EXE_STD$MAXACMODE,#define exe_std$mntversio EXE_STD$MNTVERSIO'#define exe_std$modify EXE_STD$MODIFY.#define exe_std$modifylock EXE_STD$MODIFYLOCK,#define exe_std$mount_ver EXE_STD$MOUNT_VER.#define exe_std$nam_to_pcb EXE_STD$NAM_TO_PCB)#define exe_std$oneparm EXE_STD$ONEPARM.#define exe_std$outzstring EXE_STD$OUTZSTRING6#define exe_std$primitive_fork EXE_STD$PRIMITIVE_FORK?#define exe_std$primitive_fork_wait EXE_STD$PRIMITIV E_FORK_WAIT'#define exe_std$prober EXE_STD$PROBER.#define exe_std$prober_dsc EXE_STD$PROBER_DSC2#define exe_std$prober_dsc64 EXE_STD$PROBER_DSC64'#define exe_std$probew EXE_STD$PROBEW.#define exe_std$probew_dsc EXE_STD$PROBEW_DSC2#define exe_std$probew_dsc64 EXE_STD$PROBEW_DSC64?#define exe$psx_resume_and_wait EXE$PSX_RESUME_AND_WAIT?#define exe$psx_set_fork_status EXE$PSX_SET_FORK_STATUS,#define exe_std$qioacppkt EXE_STD$QIOACPPKT,#define exe_std$qiodrvpkt EXE _STD$QIODRVPKT=#define exe_std$qioserver_new_unit EXE_STD$QIOSERVER_NEW_UNIT.#define exe_std$queue_fork EXE_STD$QUEUE_FORK##define exe_std$read EXE_STD$READ)#define exe_std$readchk EXE_STD$READCHK*#define exe_std$readlock EXE_STD$READLOCK)#define exe_std$rmvtimq EXE_STD$RMVTIMQ,#define exe_std$sensemode EXE_STD$SENSEMODE)#define exe_std$setchar EXE_STD$SETCHAR)#define exe_std$setmode EXE_STD$SETMODE*#define exe_std$sndevmsg EXE_STD$SNDEVMSG8#define exe_std$snglequota_lon g EXE_STD$SNGLEQUOTA_LONG.#define exe_std$synch_loop EXE_STD$SYNCH_LOOP9#define exe$timedwait_complete EXE$TIMEDWAIT_COMPLETE4#define exe$timedwait_setup EXE$TIMEDWAIT_SETUP=#define exe$timedwait_setup_10us EXE$TIMEDWAIT_SETUP_10US%#define exe_std$write EXE_STD$WRITE*#define exe_std$writechk EXE_STD$WRITECHK,#define exe_std$writelock EXE_STD$WRITELOCK.#define exe_std$wrtmailbox EXE_STD$WRTMAILBOX*#define exe_std$zeroparm EXE_STD$ZEROPARM#define ini$brk INI$BRK ,#define exe$allocate_pool EXE$ALLOCATE_POOL0#define exe$deallocate_pool EXE$DEALLOCATE_POOL.#define exe$trim_pool_list EXE$TRIM_POOL_LIST6#define exe$register_pool_info EXE$REGISTER_POOL_INFO%#define exe$lock_pkta EXE$LOCK_PKTA)#define exe$unlock_pkta EXE$UNLOCK_PKTA2#define exe$lal_insert_first EXE$LAL_INSERT_FIRST2#define exe$lal_remove_first EXE$LAL_REMOVE_FIRST!#define exe$kprintf EXE$KPRINTF##define exe$kvprintf EXE$KVPRINTFD#ifdef __ia64 /* Verified for IA64 port - KLN; x86 - Clair Grant */*#define exe$save_f12_f15 EXE$SAVE_F12_F156#define exe$save_hfp_registers EXE$SAVE_HFP_REGISTERS0#define exe$restore_f12_f15 EXE$RESTORE_F12_F15;#define exe$restore_hfp_registers EXE$RESTORE_HFP_REGISTERS.#define exe$rseregs_before EXE$RSEREGS_BEFORE0#define exe$rseregs_between EXE$RSEREGS_BETWEEN.#define exe$rseregs_beyond EXE$RSEREGS_BEYOND*#define exe$rseregs_save EXE$RSEREGS_SAVE0#define exe$rseregs_restore EXE$RSEREGS_RESTORE#endif,#define exe$ setstk_64_int EXE$SETSTK_64_INT/*N Function prototypes for system routines with the EXE$ and EXE_STD$ prefix.*/Bint exe_std$abortio (IRP *irp, PCB *pcb, UCB *ucb, int qio_sts);Nint exe_std$alloc_bufio_32 (IRP *irp, PCB *pcb, void *uva32, int pktdatsiz);Pint exe_std$alloc_bufio_64 (IRP *irp, PCB *pcb, VOID_PQ uva64, int pktdatsiz);Eint exe_std$alloc_diagbuf (IRP *irp, VOID_PQ uva64, int pktdatsiz);Hint exe_std$allocbuf (int reqsize, int32 *alosize_p, void **bufptr_p);7int exe_std$allocceb (int32 *alosize_p, CEB **ceb_p);%int exe_std$allocirp (IRP **irp_p);7int exe_std$allocjib (int32 *alosize_p, JIB **jib_p);7int exe_std$allocpcb (int32 *alosize_p, PCB **pcb_p);7int exe_std$alloctqe (int32 *alosize_p, TQE **tqe_p);Iint exe_std$alononpaged (int reqsize, int32 *alosize_p, void **pool_p);Fint exe_std$alopaged (int reqsize, int32 *alosize_p, void **pool_p);Hint exe_std$alop1imag (int reqsize, int32 *alosize_p, void **pool_p);Hint exe_std$alop1proc (int reqsize, int32 *alosize_p, void **pool_p);4int exe_std$alophycntg (int npages, void **sva_p);9int exe_std$alophycntg_s2 (int npages, VOID_PPQ sva_p);Sint exe_std$alophycntg_color (int npages, int rad, int byte_align, void **sva_p);Xint exe_std$alophycntg_color_s2 (int npages, int rad, int byte_align, VOID_PPQ sva_p);-void exe_std$altquepkt (IRP *irp, UCB *ucb);Kint exe$bugchk_cancel_remove_va (VOID_PQ start_va, uint64 size_in_bytes);Dint exe$bugchk_remove_va (VOID_PQ start_va, uint64 size_in_bytes);#int exe$bus_delay (ADP *adp);)int exe$delay (int64 *delay_nanos);"void exe_std$carriage (IRP *irp);kint exe$cbb_allocate (CBB_PPQ cbb, int unitsize, int bits, int ipl, uint64 flags, int timeout_value);Zint exe$cbb_clear_bit (int flags, int bitpos, CBB_PQ src, CBB_PQ dst, INT_PQ ccode);gint exe$cbb_clear_range (int flags, int start, int length, CBB_PQ src, CBB_PQ dst, INT_PQ ccode);>int exe$cbb_empty (CBB_PQ cbb, int flags, INT_PQ state);cint exe$cbb_find_first_clear (CBB_PQ cbb, int start, int flags, INT_PQ bitpos, INT_PQ ccode);aint exe$cbb_find_first_set (CBB_PQ cbb, int start, int flags, INT_PQ bitpos, INT_PQ ccode);Cint exe$cbb_get_size (int unitsize, int bits, INT_PQ resultsize);xint exe$cbb_initialize (CBB_PQ cbb, int blksiz, int unitsize, int bits, int ipl, uint64 flags, int timeout_value);$int exe$cbb_lock (CBB_PQ cbb);2int exe$cbb_rebuild (CBB_PQ cbb, int flags);Jint exe$cbb_set_bit (int flags, int bitpos, CBB_PQ src, CBB_PQ dst);?int exe$cbb_test_bit (CBB_PQ cbb, int bitpos, int flags);&int exe$cbb_unlock (CBB_PQ cbb);Cint exe$cbb_copy( CBB_PQ src, CBB_PQ dst, int length, int flags);cint exe$cbb_extract_bitmask( CBB_PQ src, int start, int length, int flags, VOID_PQ bitmask_addr);bint exe$cbb_insert_bitmask( int start, int length, int flags, VOID_PQ bitmask_addr, CBB_PQ cbb);{int exe$cbb_validate (CBB_PQ cbb, int unitsize, int bits, int ipl, uint64 flags, int timeout_value, UINT64_PQ ret_flags);+int exe$cbb_zero (CBB_PQ cbb, int flags);iint exe$cbb_boolean_oper (int flags, int function, CBB_PQ cbb1, CBB_PQ cbb2, CBB_PQ dst, INT_PQ ccode);@int exe_std$check_device_access(int, int, PCB *pcb, UCB *ucb);!int exe_std$chkflupages (void);Nint exe_std$chkpro_int (ARB *arb, ORB *orb, CHPCTL *chpctl, CHPRET *chpret);Cint exe_std$chkcreacces (ARB *arb, ORB *orb, PCB *pcb, UCB *ucb);Cint exe_std$chkdelacces (ARB *arb, ORB *orb, PCB *pcb, UCB *ucb);Cint exe_std$chkexeacces (ARB *arb, ORB *orb, PCB *pcb, UCB *ucb);Cint exe_std$chklogacces (ARB *arb, ORB *orb, PCB *pcb, UCB *ucb);Cint exe_std$chkphyacces (ARB *arb, ORB *orb, PCB *pcb, UCB *ucb);Bint exe_std$chkrdacces (ARB *arb, ORB *orb, PCB *pcb, UCB *ucb);Cint exe_std$chkwrtacces (ARB *arb, ORB *orb, PCB *pcb, UCB *ucb);3void exe_std$credit_bytcnt (int credit, PCB *pcb);9void exe_std$credit_bytcnt_bytlm (int credit, PCB *pcb);8 int exe$credit_bytcnt_bytlm_id (int credit, int ipid);*int exe_std$cvt_ipid_to_epid (int ipid);)PCB *exe_std$cvt_ipid_to_pcb (int ipid);$void exe_std$deapaged (void *pool);'int exe_std$deanonpaged (void *pool);2int exe_std$deanonpgdsiz (void *pool, int size);+int exe_std$deap1 (void *pool, int size);&int exe_std$deap1block (void *pool);1int exe_std$debit_bytcnt (int debit, PCB *pcb);Fint exe_std$debit_bytcnt_alo (int debit, PCB *pcb, int32 *alosize_p,/ void **pool_p);Lint exe_std$debit_bytcnt_bytlm_alo (int debit, PCB *pcb, int32 *alosize_p,/ void **pool_p);:int exe_std$debit_bytcnt_bytlm_nw (int debit, PCB *pcb);%int exe_std$expandstk (VOID_PQ va);,int exe_std$finishio (IRP *irp, UCB *ucb);Aint exe$illiofunc (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);2int exe_std$insert_irp (IRP **irp_lh, IRP *irp);*void exe_std$insioq (IRP *irp, UCB *ucb);+void exe_std$insioqc (IRP *irp, UCB *ucb);1void exe_std$insioq_simple (IRP *irp, UCB *ucb);?void exe_std$instimq (int duetim_lo, int duetim_hi, TQE *tqe);4void exe_std$iofork_cpu (FKB *fkb, CPU *destcpudb);Aint exe_std$iorsnwait (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb, / int qio_sts, int rsn);Qint exe$kp_allocate_kpb (KPB **kpb_p, int stksiz, int flags, int paramsiz);wint exe$kp_alloc_rse_stack_p2_any (KPB_PQ kpb, const int stack_pages, unsigned int region_prot, unsigned int acmode);+ int exe$kp_deallocate_kpb (KPB *kpb);Tint exe$kp_end (KPB *kpb, ...); /* status = exe$kp_end(kpb[, end_status]); */!KPB *exe$kp_find_kpb (void);+int exe$kp_fork (KPB *kpb, FKB *fkb);0int exe$kp_fork_wait (KPB *kpb, FKB *fkb);4int exe$kp_restart (KPB *kpb, int thread_sts);*int exe$kp_stall_general (KPB *kpb);Iint exe$kp_start (KPB *kpb, void (*rout)(KPB *kpb), int64 regmask);.void exe_std$kp_startio (IRP *irp, UCB *ucb);@int exe$kp_tqe _wait (KPB *kpb, int64 *ticks, int spnlidx);8int exe$kp_alloc_mem_stack(KPB_PQ kpb, int stack_pages);)int exe$kp_dealloc_mem_stack(KPB_PQ kpb);8int exe$kp_alloc_rse_stack(KPB_PQ kpb, int stack_pages);)int exe$kp_dealloc_rse_stack(KPB_PQ kpb);;int exe$kp_alloc_rse_stack_p2(KPB_PQ kpb, int stack_pages);,int exe$kp_dealloc_rse_stack_p2(KPB_PQ kpb);Cint exe$kp_alloc_mem_stack_user(KPB_PQ kpb, const int stack_pages);.int exe$kp_dealloc_mem_stack_user(KPB_PQ kpb);#int exe$kp_stack_peaks(KPB_PQ kpb);Uint exe$kp_user_alloc_kpb(KPB **kpb_p, int flags, int param_size, int (*kpb_alloc)(),0 int mem_stack_bytes, int (*memstk_alloc)(), C int rse_stack_bytes, int (*rsestk_alloc)(), void (*end_rtn)()); /* X-81c Begin */int exe$kp_spl_start3 (KPB *kpb, /* Kernel Process Block address */< void (*rout)(KPB *kpb), /* Routine to execute as KPB */? int64 regmask, /* Register mask (0 to default) */E int64 flags); /* X-84c Not-relea seable flags */int exe$kp_spl_restart3 (KPB *kpb, /* Kernel Process Block address */> int thread_sts, /* Status to pass to restarted thread */E int64 flags); /* X-84c Not-releaseable flags */int exe$kp_spl_update_kpb3 (KPB *kpb, /* Kernel Process Block address */L int64 flags, /* X-84c Not-releaseable flags to add */8 SPL *spl_fork, /* Fork spinlock address */8 SPL *spl_port, /* Port spinlock addres s */; SPL *spl_dyn); /* Dynamic spinlock address */int exe$kp_spl_ctx_set3 (KPB *kpb, /* Kernel Process Block address */5 int64 req_spl_ctx, /* Spinlock control flags */K int64 *prev_spl_ctx); /* Returned previous spinlock context (opt) */ /int exe$spl_ctx_set /* X-84b */S (int64 req_spl_ctx, /* Requested spinlock context & control bits */? SPL *spl_fork, /* Fork spinlock address */? SPL *spl_ port, /* Port spinlock address */B SPL *spl_dyn, /* Dynamic spinlock address */R int64 *prev_spl_ctx); /* Returned previous spinlock context (opt) */int exe$kp_spl_stall_general3 (KPB *kpb, /* Kernel Process Block address */F void (*sch_stall_rtn)()); /* Schedule stall routine (opt) */(int exe$kp_spl_tqe_wait /* X-84d */3 (KPB *kpb, /* Kernel Process Block address */0 int64 *ticks); /* EXE$GQ_SYSTIME ticks */int exe$kp_rmvtimq4 (KPB *kpb); /* Kernel Process Block address */$int exe$kp_spl_fork /* X-84d */3 (KPB *kpb, /* Kernel Process Block address */* FKB *fkb); /* Fork Block address */(int exe$kp_spl_fork_wait /* X-84d */3 (KPB *kpb, /* Kernel Process Block address */* FKB *fkb); /* Fork Block address */ /* X-81c End */'int exe$kp_spl_init_kpb /* X-82 */3 (KPB *kpb, /* Kernel Process Block address */8 SPL *spl_fork, /* Fork spinlock address */8 SPL *spl_port, /* Port spinlock address */; SPL *spl_dyn); /* Dynamic spinlock address */%int exe$kprintf(char *form, ...);:int exe$kvprintf (char *form,__va_list __va_list_arg);Cint exe_std$lcldskvalid (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);*void exe_std$lock_err_cleanup (IRP *irp);%int exe_std$maxacmode (int acmode);?void exe$lal_insert_first(void *packet, VOID_PQ listhead);1void *exe$lal_remove_first(VOID_PQ listhead);#pragma message save "#pragma message disable noparmlist=void exe_std$mntversio (void (*rout)(), IRP *irp, UCB *ucb);#pragma message restore>int exe_std$modify (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);#pragma message save "#pragma message disable noparmlistK#ifdef __INITIAL_POINTER_SIZE /* Defined if support for 64-bit pointers */Bint exe_std$modifylock (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb, 3 VOID_PQ buf, int bufsiz,  void (*err_rout)());#elseBint exe_std$modifylock (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb, 1 void *buf, int bufsiz, - void (*err_rout());##endif /* __INITIAL_POINTER_SIZE */#pragma message restoreCint exe_std$mount_ver (int iost1, int iost2, IRP *irp, UCB *ucb);K#ifdef __INITIAL_POINTER_SIZE /* Defined if support for 64-bit pointers */Kint exe_std$nam_to_pcb(INT_PQ pid_p,VOID_PQ prcnam_p,int nsa_id,PCB *pcb,( int *rpid_p ,KTB **rktb_p,PCB **rpcb_p);#elseGint exe_std$nam_to_pcb(int *pid_p,void *prcnam_p,int nsa_id,PCB *pcb,( int *rpid_p,KTB **rktb_p,PCB **rpcb_p);##endif /* __INITIAL_POINTER_SIZE */?int exe_std$oneparm (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);(void exe_std$outzstring (char *string);>void exe_std$primitive_fork (int64 fr3, int64 fr4, FKB *fkb);Cvoid exe_std$primitive_fork_wait (int64 fr3, int64 fr4, FKB *fkb);;int exe_std$prober (VOID_PQ buf, int bufsiz, int acmode);'int ex e_std$prober_dsc (void *dsc_p);;int exe_std$probew (VOID_PQ buf, int bufsiz, int acmode);'int exe_std$probew_dsc (void *dsc_p);Aint exe_std$prober_dsc64 (VOID_PQ dsc_p, UINT64_PQ ret_length,  CHAR_PPQ ret_bufadr);@int exe_std$probew_dsc64 (VOID_PQ dsc_p, UINT64_PQ ret_length, CHAR_PPQ ret_bufadr);7int exe_std$qioacppkt (IRP *irp, PCB *pcb, UCB *ucb);-int exe_std$qiodrvpkt (IRP *irp, UCB *ucb);,int exe_std$qioserver_new_unit (UCB *ucb);$void exe_std$queue_fork (FKB *fkb);0int exe$psx_resume_and_wait (PCB *child_pcb);<void exe$psx_set_fork_status (PCB *child_pcb, int status);<int exe_std$read (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);K#ifdef __INITIAL_POINTER_SIZE /* Defined if support for 64-bit pointers */Nint exe_std$readchk (IRP *irp, PCB *pcb, UCB *ucb, VOID_PQ buf, int bufsiz);#elseLint exe_std$readchk (IRP *irp, PCB *pcb, UCB *ucb, void *buf, int bufsiz);##endif /* __INITIAL_POINTER_SIZE */#pragma message save "#pragma messag e disable noparmlistK#ifdef __INITIAL_POINTER_SIZE /* Defined if support for 64-bit pointers */@int exe_std$readlock (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb, 3 VOID_PQ buf, int bufsiz,  void (*err_rout)());#else@int exe_std$readlock (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb, 1 void *buf, int bufsiz,  void (*err_rout)());##endif /* __INITIAL_POINTER_SIZE */#pragma message restoreDint exe_std$rmvtimq (int acmode, int reqid, int remval, int ipid);Aint exe_std$sensemode (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);?int exe_std$setchar (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);?int exe_std$setmode (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);>int exe_std$sndevmsg (MB_UCB *mb_ucb, int msgtyp, UCB *ucb);9int exe_std$snglequota_long (int32 *quota_p, PCB *pcb);1int exe_std$synch_loop (int efn, VOID_PQ iosb);2int exe$timedwait_complete (int64 *end_value_p);Cint exe$timedwait_setup (int64 *delay_nanos, int64 *end_value_p);Gint exe$timedwait_setup_10us (int64 *delay_10us, int64 *end_value_p);=int exe_std$write (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);K#ifdef __INITIAL_POINTER_SIZE /* Defined if support for 64-bit pointers */Oint exe_std$writechk (IRP *irp, PCB *pcb, UCB *ucb, VOID_PQ buf, int bufsiz);#elseMint exe_std$writechk (IRP *irp, PCB *pcb, UCB *ucb, void *buf, int bufsiz);##endif /* __INITIAL_POINTER_SIZE */#pragma message save "#pragma message disable noparm listK#ifdef __INITIAL_POINTER_SIZE /* Defined if support for 64-bit pointers */Aint exe_std$writelock (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb, 3 VOID_PQ buf, int bufsiz,  void (*err_rout)());#elseAint exe_std$writelock (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb, 1 void *buf, int bufsiz,  void (*err_rout)());##endif /* __INITIAL_POINTER_SIZE */#pragma message restoreEint exe_std$wrtmailbox (MB_UCB *mb_ucb, int msgs iz, void *msg,...);@int exe_std$zeroparm (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);void ini$brk (void);I/* The definition of these funcs must have their own prototypes. That isE because they have optional parameters, and it works much better toL specify "..." for callers and the actual args for the function itself. */ #if !defined(MEMORYALC_POOL_SRC)K#ifdef __INITIAL_POINTER_SIZE /* Defined if support for 64-bit pointers */Mint exe$allocate_pool(int requestSize, MMG$POOL_TYPE p oolType, int alignment,8 UINT64_PQ allocatedSize, VOID_PPQ returnBlock,...);Tvoid exe$deallocate_pool(VOID_PQ returnBlock, MMG$POOL_TYPE poolType, int size,...);Mint exe$trim_pool_list(int reqSize, MMG$POOL_TYPE poolType, int percent,...);!#ifdef __INITIAL_POINTER_SIZE )#pragma __required_pointer_size __long #endif#pragma message save "#pragma message disable noparmlist}int exe$register_pool_info(int (*need_memory_callback)(), MMG$POOL_TYPE poolType, uint64 userParam, int maxSize, int minSize,0 uint64 extra_param_1,uint64 extra_param_2);#pragma message restore!#ifdef __INITIAL_POINTER_SIZE '#pragma __required_pointer_size __short#endifZ/* Extra_param_n have pool_type-specific semantics. They are PA base and length for BAP*//* No 32-bit only version */#endif#endif /*MEMORYALC_POOL_SRC*/int exe$lock_pkta(void);int exe$unlock_pkta(void);)void exe$check_for_mem_error(CPU *cpudb);"int exe$primitive_mcheck(int vec); int exe$setup_memtest_env(void); int exe$clear_memtest_env(void);+/* Routine for System event notification */)#define exe$event_notify EXE$EVENT_NOTIFY- void exe$event_notify (uint64 event_mask);A#ifdef __ia64 /* Verified for IA64 port BF; x86 - Clair Grant */)#pragma __required_pointer_size __long */* Floating point save/restore routines */'void exe$save_f12_f15(void *save_area);(void exe$save_hfp_registers(void *area);*void exe$restore_f12_f15(void *save_area);+void exe$restore_hfp_regis ters(void *area);?uint64 *exe$rseregs_before (uint64 *baseAddress, uint64 slots);Kuint64 exe$rseregs_between (uint64 *greaterAddress, uint64 *lesserAddress);?uint64 *exe$rseregs_beyond (uint64 *baseAddress, uint64 slots);zint exe$rseregs_save (INTSTK const * const intframe, uint64 regOutput[96], uint64 *addrOutput[96], uint64 natOutput[2],d uint64 * * const endBackingStore, uint64 * * const endLastNaTSlot, RSC * const endSaveRsc);fvoid exe$rseregs_restore (INTSTK const * const intframe, uint64 regOutput[96], uint64 natOutput[2], [ uint64 * const startBackingStore, uint64 * const startLastNaTSlot, RSC const saveRsc);'#pragma __required_pointer_size __short#endif:/* Routine for setting memory and register stack limits */Uint exe$setstk_64_int (VOID_PQ start_va, uint64 length, int acmode, uint64 flags, 2 VOID_PPQ prev_start_va, UINT64_PQ prev_length);B/* Routines for dealing with whole program floating point modes */&#pragma __required_pointer_size __long!typedef struct _return_2quads_t { unsigned __int64 quad0; unsigned __int64 quad1;} RETURN_2QUADS_T;8void exe$set_whole_pgm_fp_mode(struct _ieee *wpfpValue);YRETURN_2QUADS_T exe$revert_whole_pgm_fp_mode(unsigned __int64 newHW, struct _ieee newSW);#pragma message save6#ifdef __ia64 /* Verified for x86 port--Drew Mason */&#pragma message disable showmaplinkage#endif=#pragma linkage exe$$linkage_return_r0_and_r1=(result(r0,r1))P#pragma use_linkage exe$$linkage_return_r0_and_r1 (exe$revert_whole_pgm_fp_mode)#pragma message restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif"#endif /* __EXE_ROUTINES_LOADED */wwZU/* module FSHWA.H "X-1"**J**************************************************************************J**  *J** Copyright 2005 Hewlett-Packard Development Company, L.P. *J** *J** Confidential computer software. *J** Valid license from HP required for possession, use or copying. *J** *J** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, *J** Computer Software Documentation, and Technical Data for Commercial *J** Items are licensed to the U.S. Government under vendor's standard *J** commercial license. *J** *J** Neither HP nor any of its subsidiaries shall be liable for technical *J** or editorial errors or omissions contained herein. The information *J** in this document is provided "as is" without warranty of any kind and *J** is subject to change without notice. The warranties for HP products *J** are set forth in the express limited warranty statements accompanying *J** such products. Nothing herein should be construed as constituting an *J** additional warranty. *J** *J******************************************************************************++** FACILITY: ** ** VMS Executive (LIB_H)**** MODULE DESCRIPTION:**@** Definitions for the fPars Shared Hardware Assist (FSHWA)$** EFI protocol extension interface.** ** AUTHORS:**** Eric Rasmussen**** CREATION DATE: 22-Apr-2005**** SUPPORTING DOCUMENTS:**>** SPPA Firmware EAS Version 1.6 (Draft 0.56) 20-Apr-2005** Appendix E: fPar ExtensionsC** http://arch.cup.hp.com/sppa_platform/doc/sppa-x/hp_sal/fw1_6.pdf**** MODIFICATION HISTORY:**.** X-1 ER Eric Rasmussen 22-Apr-2005** Initial revision.**--*/#ifndef __FSHWA_H_#define __FSHWA_H_ 1&#pragma __required_pointer_size __save&#pragma __required_pointer_size __long///// EFI status codes returned by FSHWA services.//#define EFI_SUCCESS(a) (!a)*#define EFI_FAILURE(a) (((uint64) a) < 0)&#define EFI_ERROR 0x8000000000000000L4#define EFI_INVALID_PARAMETER ( EFI_ERROR | 0x0002 )/#define EFI_UNSUPPORTED ( EFI_ERROR | 0x0003 )3#define EFI_BUFFER_TOO_SMALL ( EFI_ERROR | 0x0005 )/#define EFI_DEVICE_ERROR ( EFI_ERROR | 0x0007 )3#define EFI_OUT_OF_RESOURCES ( EFI_ERROR | 0x0009 )-#define EFI_NOT_FOUND ( EFI_ERROR | 0x000E )0#define EFI_ACCESS_DENIED ( EFI_ERROR | 0x000F )+#define EFI_TIMEOUT ( EFI_ERROR | 0x0012 )struct _FSHWA_INTERFACE;typedef struct _FSHWA_RET { __int64 Status; unsigned __int64 Rsvd1; unsigned __int64 Rsvd2; unsigned __int64 Rsvd3;} FSHWA_RET;>#pragma linkage_ia64 fshwa_linkage=( result( r8,r9,r10,r11 ) )//// FSHWA Shared Register//5#define FSHWA$M_VMASK_ROOT_GPE_BLK 0x00000000000000012#define FSHWA$M_VMASK_RESERVED 0xFFFFFFFFFFFFFFFEtypedef FSHWA_RET$ ( FSHWA_GET_VIRTUALIZED_MASK ) (# struct _FSHWA_INTERFACE *This,( unsigned __int64 *UseVirtualAccess  );?#pragma use_linkage fshwa_linkage( FSHWA_GET_VIRTUALIZED_MASK ) typedef enum { FshwaAccessWidthUint8 = 1, FshwaAccessWidthUint16 = 2, FshwaAccessWidthUint32 = 4,  FshwaAccessWidthUint64 = 8} FSHWA_ACCESS_WIDTH;typedef FSHWA_RET  ( FSHWA_VIRTUAL_READ ) ( struct _FSHWA_INTERFACE *This, FSHWA_ACCESS_WIDTH AccessWidth, unsigned __int64 Address, unsigned __int64 Size, void *Buffer );7#pragma use_linkage fshwa_linkage( FSHWA_VIRTUAL_READ )typedef FSHWA_RET  ( FSHWA_VIRTUAL_WRITE ) ( struct _FSHWA_INTERFACE *This, FSHWA_ACCESS_WIDTH AccessWidth, unsigned __int64 Address, unsigned __int64 Size, void *Buffer );8#pragma use_linkage fshwa_linkage( FSHWA_VIRTUAL_WRITE )//// FSHWA Shared IOSAPIC//typedef FSHWA_RET ( ( FSHWA_GET_SHARED_IOSAPIC_COUNT ) ( struct _FSHWA_INTERFACE *This,( unsigned __int64 *CountOfSharedIoSapics );C#pragma use_linkage fshwa_linkage( FSHWA_GET_SHARED_IOSAPIC_COUNT ))typedef struct _FSHWA_SHARED_IOSAPIC_DESC{% unsigned __int64 PhysicalAddress;# unsigned __int64 AccessMode[4];} FSHWA_SHARED_IOSAPIC_DESC;typedef FSHWA_RET ' ( FSHWA_GET_SHARED_IOSAPIC_LIST ) (# struct _FSHWA_INTERFACE *This,# FSHWA_SHARED_IOSAPIC_DESC *List, unsigned __int64 *Size );B#pragma use_linkage fshwa_linkage( FSHWA_GET_SHARED_IOSAPIC_LIST )typedef FSHWA_RET ' ( FSHWA_GET_SHARED_IOSAPIC_VERS ) ( struct _FSHWA_INTERFACE *This,! unsigned __int64 IoSapicAddress, unsigned __int64 *Version );B#pragma use_linkage fshwa_linkage( FSHWA_GET_SHARED_IOSAPIC_VERS )typedef FSHWA_RET ! ( FSHWA_SET_IOSAPIC_REDIR ) ( struct _FSHWA_INTERFACE *This,! unsigned __int64 IoSapicAddress, unsigned __int64 RedirNumber, unsigned __int64 RedirValue );<#pragma use_linkage fshwa_linkage( FSHWA_SET_IOSAPIC_REDIR )typedef FSHWA_RET ! ( FSHWA_GET_IOSAPIC_REDIR ) ( struct _FSHWA_INTERFACE *This,! unsigned __int64 IoSapicAddress, unsigned __int64 RedirNumber, unsigned __int64 *RedirValue );<#pragma use_linkage fshwa_linkage( FSHWA_GET_IOSAPIC_REDIR )typedef FSHWA_RET  ( FSHWA_CLEAR_INTERRUPT ) ( struct _FSHWA_INTERFACE *This,! unsigned __int64 IoSapicAddress, unsigned __int64 RedirNumber, unsigned __int64 EoiValue );:#pragma use_linkage fshwa_linkage( FSHWA_CLEAR_INTERRUPT )typedef FSHWA_RET ' ( FSHWA_ACQUIRE_EXCLUSIVE_REDIR ) ( struct _FSHWA_INTERFACE *This,! unsigned __int64 IoSapicAddress, unsigned __int64 RedirNumber, unsigned __int64 *WhoHasIt );B#pragma use_linkage fshwa_linkage( FSHWA_ACQUIRE_EXCLUSIVE_REDIR )typedef FSHWA_RET ' ( FSHWA_RELEASE_EXCLUSIVE_REDIR ) ( struct _FSHWA_INTERFACE *This,! unsigned __int64 IoSapicAddress, unsigned __int64 RedirNumber );B#pragma use_linkage fshwa_linkage( FSHWA_RELEASE_EXCLUSIVE_REDIR )//// FSHWA Shared IPMI//typedef FSHWA_RET  ( FSHWA_GET_SEQUENCE ) ( struct _FSHWA_INTERFACE *This, unsigned __int64 *SequenceNum );7#pragma use_linkage fshwa_linkage( FSHWA_GET_SEQUENCE )typedef FSHWA_RET  ( FSHWA_ENQUEUE_MSG ) ( struct _FSHWA_INTERFACE *This, unsigned __int64 SequenceNum, void *BtMessage, unsigned __int64 Size );6#pragma use_linkage fshwa_linkage( FSHWA_ENQUEUE_MSG )typedef FSHWA_RET  ( FSHWA_DEQUEUE_MSG ) ( struct _FSHWA_INTERFACE *This, unsigned __int64 *SequenceNum, void *BtMessage, unsigned __int64 *Size );6#pragma use_linkage fshwa_linkage( FSHWA_DEQUEUE_MSG )//// FSHWA Protocol Interface// typedef struct _FSHWA_INTERFACE {#  unsigned __int64 Revision;//// Shared Register Interface//7 FSHWA_GET_VIRTUALIZED_MASK *GetVirtualizedMask;) FSHWA_VIRTUAL_READ *VirtualRead;+ FSHWA_VIRTUAL_WRITE *VirtualWrite;//// Shared IOSAPIC Interface//; FSHWA_GET_SHARED_IOSAPIC_COUNT *GetSharedIoSapicCount;: FSHWA_GET_SHARED_IOSAPIC_LIST *GetSharedIoSapicList;: FSHWA_GET_SHARED_IOSAPIC_VERS *GetSharedIoSapicVers;1 FSHWA_SET_IOSAPIC_REDIR *SetIoSapicRedir;1 FSHWA_GET_IOSAPIC_REDIR *GetIoSapicRedir;5 FSHWA_CLEAR_INTERRUPT *ClearIoSapicInterrupt;B FSHWA_ACQUIRE_EXCLUSIVE_REDIR *AcquireExclusiveIoSapicRedir;B FSHWA_RELEASE_EXCLUSIVE_REDIR *ReleaseExclusiveIoSapicRedir;//// Shared IPMI BT Interface//( FSHWA_GET_SEQUENCE *GetIpmiSeq;+ FSHWA_ENQUEUE_MSG *EnqueueIpmiMsg;+ FSHWA_DEQUEUE_MSG *DequeueIpmiMsg;} FSHWA_INTERFACE;)#pragma __required_pointer_size __restore#endif /* __FSHWA_H_ */ww ^ZU"/* module FSHWA_ROUTINES.H "X-1"**J**************************************************************************J** *J** Copyright 2005 Hewlett-Packard Development Company, L.P. *J** *J** Confidential computer software. *J** Valid license from HP required for possession, use or copying.  *J** *J** Consistent with FAR 12.211 and 12.212, Commercial Computer Software, *J** Computer Software Documentation, and Technical Data for Commercial *J** Items are licensed to the U.S. Government under vendor's standard *J** commercial license. *J** *J** Neither HP nor any of its subsidiaries shall be liable for technical *J** or editorial errors or omissions contained herein. The information *J** in this document is provided "as is" without warranty of any kind and *J** is subject to change without notice. The warranties for HP products *J** are set forth in the express limited warranty statements accompanying *J** such products. Nothing herein should be construed as constituting an *J** additional warranty. *J**  *J******************************************************************************++** FACILITY: ** ** VMS Executive (LIB_H)**** MODULE DESCRIPTION:**;** This module contains support routines for the fPars5** Shared Hardware Assist (FSHWA) protocol interface.** ** AUTHORS:**** Eric Rasmussen**** CREATION DATE: 22-Apr-2005**** SUPPORTING DOCUMENTS:**>** SPPA Firmware EAS Version 1.6 (Draft 0.56) 20-Apr-2005** Appendix E: fPar ExtensionsC** http://arch.cup.hp.com/sppa_platform/doc/sppa-x/hp_sal/fw1_6.pdf**** MODIFICATION HISTORY:**.** X-1 ER Eric Rasmussen 22-Apr-2005** Initial revision.**--*/#ifndef __FSHWA_ROUTINES_H_#define __FSHWA_ROUTINES_H_ 1&#pragma __required_pointer_size __save&#pragma __required_pointer_size __long#include #include #include #include &extern FSHWA_INTERFACE *exe$gpq_fshwa;/***++** FUNCTIONAL DESCRIPTION:**6** Get the current FSHWA protocol revision level.**** FORMAL PARAMETERS:** ** rev:/** Pointer to returned revision level.**** RETURN VALUE:**-** Status indicating success or failure.**** SS$_NORMAL:4** The revision level was returned successfully.**** SS$_BADPARAM:$** The rev parameter is invalid.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/+static int fshwa$get_version( uint64 *rev ){8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;+ if ( rev == NULL ) return SS$_BADPARAM;# *rev = exe$gpq_fshwa->Revision; return SS$_NORMAL;}//"// FSHWA Shared Register Interface///***++** FUNCTIONAL DESCRIPTION:**O** Get a bit mask that identifies registers, or groups of registers, that J** must be accessed using the FSHWA virtual read/write register functions.**** FORMAL PARAMETERS:** ** mask:7** Returned bit mask of virtualized registers.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:8** The register mask data was returned successfully.**** SS$_BADPARAM:%** The mask parameter is invalid.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/6static int fshwa$get_virtualized_mask ( uint64 *mask ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;H FshwaRet = exe$gpq_fshwa->GetVirtualizedMask( exe$gpq_fshwa, mask );) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}/***++** FUNCTIONAL DESCRIPTION:**6** Read a virtualized (shared) register resource.**** FORMAL PARAMETERS:** ** width:3** The access size in bytes. Valid values are: ** 1 - Byte ** 2 - Word** 4 - Longword** 8 - Quadword**** address:4** The address of the virtualized register. ** ** size:(** The number of bytes to read.** ** data:7** Pointer to where the data will be returned.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:H** The virtualized register was read and data returned successfully.**** SS$_BADPARM:*** One or more parameters are invalid.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/ static int fshwa$virtual_read ( G FSHWA_ACCESS_WIDTH width, uint64 address, uint64 size, void *data ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED; switch ( width ) { case FshwaAccessWidthUint8: FshwaRet =  exe$gpq_fshwa->VirtualRead(  exe$gpq_fshwa, width,  address,  size,  ( uint8 * )data ); break; case FshwaAccessWidthUint16: FshwaRet =  exe$gpq_fshwa->VirtualRead(  exe$gpq_fshwa, width,  address, size,  ( uint16 * )data ); break; case FshwaAccessWidthUint32: FshwaRet =  exe$gpq_fshwa->VirtualRead(  exe$gpq_fshwa, width,  address, size,  ( uint32 * )data ); break; case FshwaAccessWidthUint64: FshwaRet =  exe$gpq_fshwa->VirtualRead(  exe$gpq_fshwa, width,  address, size,  ( uint64 * )data ); break; default: return SS$_BADPARAM; }) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}/***++** FUNCTIONAL DESCRIPTION:**7** Write a virtualized (shared) register resource.**** FORMAL PARAMETERS:** ** width:3** The access size in bytes. Valid values are: ** 1 - Byte ** 2 - Word** 4 - Longword** 8 - Quadword**** address:4** The address of the virtualized register. ** ** size:)** The number of bytes to write.** ** data:7** Pointer from where the data will be copied.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:9** The virtualized register was written successfully.**** SS$_BADPARM:*** One or more parameters are invalid.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/!static int fshwa$virtual_write ( G FSHWA_ACCESS_WIDTH width, uint64 address, uint64 size, void *data ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED; switch ( width ) { case FshwaAccessWidthUint8: FshwaRet =  exe$gpq_fshwa->VirtualWrite(  exe$gpq_fshwa, width,  address, size,  ( uint8 * )data ); break; case FshwaAccessWidthUint16: FshwaRet =  exe$gpq_fshwa->VirtualWrite(  exe$gpq_fshwa, width,  address, size,  ( uint16 * )data ); break; case FshwaAccessWidthUint32: FshwaRet =  exe$gpq_fshwa->VirtualWrite(  exe$gpq_fshwa, width,  address, size,  ( uint32 * )data ); break; case FshwaAccessWidthUint64: FshwaRet =  exe$gpq_fshwa->VirtualWrite(  exe$gpq_fshwa, width,  address, size,  ( uint64 * )data ); break; default: return SS$_BADPARAM; }) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED;  return 0;}//!// FSHWA Shared IOSAPIC Interface///***++** FUNCTIONAL DESCRIPTION:**?** Get the number of virtualized (shared) IOSAPIC devices.**** FORMAL PARAMETERS:**** count:D** Returned number of IOSAPIC devices that must be accessed*** using the FSHWA protocol interface.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:?** The number of shared IOSAPICs was returned successfully.**** SS$_BADPARM:&** The count parameter is invalid.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/;static int fshwa$get_shared_iosapic_count ( uint64 *count ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;L FshwaRet = exe$gpq_fshwa->GetSharedIoSapicCount( exe$gpq_fshwa, count );) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}/***++** FUNCTIONAL DESCRIPTION:**?** Get a list of virtualized (shared) IOSAPIC descriptors.**** FORMAL PARAMETERS:** ** list:G** Buffer to return a list of virtualized IOSAPIC descriptors. ** ** size:,** The size of the buffer in bytes.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:H** The list of shared IOSAPIC descriptors was returned successfully.**** SS$_BADPARM:*** One or more parameters are invalid.**** SS$_IVBUFLEN:'** The size parameter is too small.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/+static int fshwa$get_shared_iosapic_list ( 3 FSHWA_SHARED_IOSAPIC_DESC *list, uint64 *size ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;P FshwaRet = exe$gpq_fshwa->GetSharedIoSapicList( exe$gpq_fshwa, list, size );) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;2 if ( FshwaRet.Status == EFI_BUFFER_TOO_SMALL ) return SS$_IVBUFLEN;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}/***++** FUNCTIONAL DESCRIPTION:**I** Read the contents of the specified virtualized (shared) IOSAPIC's** Version register (VR).**F** VR<23:16> contains the maximum Redirection Table Entry (RTE) numberG** for the specified IOSAPIC. This value is needed for the calculation7** of each RTE's Global System Interrupt Number (GSIN).**** FORMAL PARAMETERS:**** iosapic:8** The base address of the virtualized IOSAPIC. ** ** version:6** The returned contents of the IOSAPIC's VR.**** RETURN VALUE:**** SS$_NORMAL:5** The contents of VR were returned successfully.**** SS$_BADPARM:*** One or more parameters are invalid.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/Lstatic int fshwa$get_shared_iosapic_vers ( uint64 iosapic, uint64 *version ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;4 FshwaRet = exe$gpq_fshwa->GetSharedIoSapicVers( & exe$gpq_fshwa, iosapic, version );) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}/***++** FUNCTIONAL DESCRIPTION:**G** Write a Redirection Table Entry (RTE) register on the specified ** virtualized (shared) IOSAPIC.**** FORMAL PARAMETERS:**** iosapic:4** Base address of the virtualized IOSAPIC. ** ** rte:F** The redirection table entry register number to be written.** ** value:$** The value to be written.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:1** The RTE register was successfully written.**** SS$_BADPARM:*** One or more parameters are invalid.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/Ostatic int fshwa$set_iosapic_redir ( uint64 iosapic, uint64 rte, uint64 value ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;/ FshwaRet = exe$gpq_fshwa->SetIoSapicRedir( ) exe$gpq_fshwa, iosapic, rte, value );) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}/***++** FUNCTIONAL DESCRIPTION:**H** Read a Redirection Table Entry (RTE) register from the specified ** virtualized (shared) IOSAPIC.**** FORMAL PARAMETERS:**** iosapic:4** Base address of the virtualized IOSAPIC. ** ** rte:C** The redirection table entry register number to be read.** ** value:$** The returned data value.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:.** The RTE register was successfully read.**** SS$_BADPARM:*** One or more parameters are invalid.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/Pstatic int fshwa$get_iosapic_redir ( uint64 iosapic, uint64 rte, uint64 *value ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;/ FshwaRet = exe$gpq_fshwa->GetIoSapicRedir( ) exe$gpq_fshwa, iosapic, rte, value ); ) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}/***++** FUNCTIONAL DESCRIPTION:**J** Clear an interrupt from the specified virtualized (shared) IOSAPIC?** to complete the processing of an interrupt received from the4** specified Redirection Table Entry (RTE) register.**** FORMAL PARAMETERS:**** iosapic:4** Base address of the virtualized IOSAPIC. ** ** rte:K** The redirection table entry register number that corresponds to#** the interrupt being cleared.** ** value:F** The value to be written into the virtualized EOI register.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:.** The interrupt was successfully cleared.**** SS$_BADPARAM:*** One or more parameters are invalid.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/+static int fshwa$clear_iosapic_interrupt ( . uint64 iosapic, uint64 rte, uint64 value ){ FSHWA_RET FshwaRet; 8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;5 FshwaRet = exe$gpq_fshwa->ClearIoSapicInterrupt( ) exe$gpq_fshwa, iosapic, rte, value ); ) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}/***++** FUNCTIONAL DESCRIPTION:**J** Acquire exclusive access rights to a Redirection Table Entry (RTE):** register on the specified virtualized (shared) IOSAPIC.**** FORMAL PARAMETERS:**** iosapic:4** Base address of the virtualized IOSAPIC. ** ** rte:G** The redirection table entry register whose exclusive access** is being requested.** ** owner:E** The fPar number of the current owner if access is denied.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:H** Exclusive rights to the specified RTE were successfully acquired.**** SS$_BADPARAM:*** One or more parameters are invalid.**** SS$_LOCKINUSE:2** The RTE is currently owned by another fPar.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/Pstatic int fshwa$acquire_exclusive ( uint64 iosapic, uint64 rte, uint64 *owner ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;< FshwaRet = exe$gpq_fshwa->AcquireExclusiveIoSapicRedir( - exe$gpq_fshwa, iosapic, rte, owner );) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;/ if ( FshwaRet.Status == EFI_ACCESS_DENIED ) return SS$_LOCKINUSE;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}/***++** FUNCTIONAL DESCRIPTION:**J** Release exclusive access rights to a Redirection Table Entry (RTE):** register on the specified virtualized (shared) IOSAPIC.**** FORMAL PARAMETERS:**** iosapic:4** Base address of the virtualized IOSAPIC. ** ** rte:G** The redirection table entry register whose exclusive access** are being released.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:H** Exclusive rights to the specified RTE were successfully released.**** SS$_BADPARAM:*** One or more parameters are invalid.**** SS$_LOCKINUSE:2** The RTE is currently owned by another fPar.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/Astatic int fshwa$release_exclusive ( uint64 iosapic, uint64 rte ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;< FshwaRet = exe$gpq_fshwa->ReleaseExclusiveIoSapicRedir( & exe$gpq_fshwa, iosapic, rte );) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;/ if ( FshwaRet.Status == EFI_ACCESS_DENIED ) return SS$_LOCKINUSE;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}//// FSHWA Shared IPMI Interface///***++** FUNCTIONAL DESCRIPTION:**C** Obtain a virtualized (shared) IPMI message sequence number.**** FORMAL PARAMETERS:**** number:G** The returned sequence number, guaranteed to be unique (i.e.>** not to match that allocated to, or in use by, any other ** fPar).**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:5** The sequence number was successfully returned.**** SS$_BADPARAM:*** One or more parameters are invalid.**** SS$_TIMEOUT:1** The FSHWA protocol lock was held too long.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/5static int fshwa$get_ipmi_sequence ( uint64 *number ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;B FshwaRet = exe$gpq_fshwa->GetIpmiSeq( exe$gpq_fshwa, number );) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;) if ( FshwaRet.Status == EFI_TIMEOUT ) return SS$_TIMEOUT;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}/***++** FUNCTIONAL DESCRIPTION:**J** Queue an IPMI BT message to the virtualized (shared) BT interface.**** FORMAL PARAMETERS:**** sequence:(** The virtual sequence number. ** ** message:A** Pointer to a buffer containing a properly formed IPMI** BT message.** ** size:5** The size of the IPMI BT message in bytes.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:+** The message was successfully queued.**** SS$_BADPARAM:*** One or more parameters are invalid.**** SS$_NOTQUEUED:>** The per-fPar instance limit of outstanding messages has** been reached.**** SS$_DEVREQERR:=** The message could not be queued due to a device error.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/Mstatic int fshwa$enqueue_ipmi ( uint64 sequence, void *message, uint64 size ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;. FshwaRet = exe$gpq_fshwa->EnqueueIpmiMsg( , exe$gpq_fshwa, sequence, message, size );) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;2 if ( FshwaRet.Status == EFI_OUT_OF_RESOURCES ) return SS$_NOTQUEUED;. if ( FshwaRet.Status == EFI_DEVICE_ERROR ) return SS$_DEVREQERR;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;}/***++** FUNCTIONAL DESCRIPTION:**K** Retrieve an IPMI BT response message from the virtualized (shared) ** BT interface.**** FORMAL PARAMETERS:**** sequence:E** The returned virtualized sequence number of the response.?** The actual sequence number for the message is inside the** returned message buffer. ** ** message:B** Pointer to a buffer for the returned IPMI BT response.** ** size:@** On input: the size of the specified message buffer.**B** On output: the size of the returned BT message, or the size@** of the next message to be removed if the specified buffer%** is too small, otherwise, zero.**** RETURN VALUE:**(** Status indicating success or failure.**** SS$_NORMAL:7** The response message was successfully retrieved.**** SS$_BADPARAM:*** One or more parameters are invalid.**** SS$_IVBUFLEN:.** The specified buffer size is too small.**** SS$_INSFRSPID:B** A response message, matching the specified sequence number,** could not be found.**** SS$_UNSUPPORTED:&** This function is not supported.****--*/Ostatic int fshwa$dequeue_ipmi ( uint64 *sequence, void *message, uint64 *size ){ FSHWA_RET FshwaRet;8 if ( exe$gpq_fshwa == NULL ) return SS$_UNSUPPORTED;. FshwaRet = exe$gpq_fshwa->DequeueIpmiMsg( / exe$gpq_fshwa, sequence, message, size );) if ( EFI_SUCCESS( FshwaRet.Status ) ) return SS$_NORMAL;3 if ( FshwaRet.Status == EFI_INVALID_PARAMETER ) return SS$_BADPARAM;2 if ( FshwaRet.Status == EFI_BUFFER_TOO_SMALL ) return SS$_IVBUFLEN;+ if ( FshwaRet.Status == EFI_NOT_FOUND ) return SS$_INSFRSPID;- if ( FshwaRet.Status == EFI_UNSUPPORTED ) return SS$_UNSUPPORTED; return 0;})#pragma __required_pointer_size __restore #endif /* __FSHWA_ROUTINES_H_ */wwZU#ifndef __GLX_ROUTINES_LOADED#define __GLX_ROUTINES_LOADED 1/* module GLX_ROUTINES.H "X-62"*I* Copyright Digital Equipment Corporation, 1998 All Rights Reserved.O* Unpublished rights reserved under the copyright laws of the United States.* L* The software contained on this media is proprietary to and embodies theP* confidential technology of Digital Equipment Corporation. Possession, use,N* duplication or dissemination of the software and media is authorized onlyL* pursuant to a valid written license from Digital Equipment Corporation.* K* RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.G* Government is subject to restrictions as set forth in SubparagraphJ* (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable.* *++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS system+* routines that begin with the GLX$ prefix.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The fu nction prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.* /* 6. Mixed pointer sizes within one argumentF* If a 64-bit pointer is being passed by reference, the reference to ?* the pointer should also be 64 bits wide to avoid confusion. * For example:* * PTE_PPQ va_pte_p;* VOID_PPQ start_va_p; ** should be used instead of:** PTE_PQ *va_pte_p;* VOID_PQ *start_va_p;* * AUTHOR:* F* Karen L. Noel based on header file authored by Leonard S. Szubowicz.* * CREATION DATE: 9-Sep-1997* * MODIFICATION HISTORY:*)* X-62 KLN3450 Karen L. Noel 5-Mar-2004* Use vms$defs.h.*!* X-61 Clair Grant 19-Feb-20048* Replace arch_defs.h with vms$defs.h and add temporary9* definition here until the build mechanism is in place.*3* X-60 Clair Grant Friday the 13th-Feb-2004%* Add new routines for expanded PFNs*(* X-59 JRK393  Jim Kauffman 2-May-2001&* Update hotswap routine declarations*%* X-57 WBF Burns Fisher 21-Apr-2000)* Add optional arg for glx$get_lock_info*(* X-56 JRK393 Jim Kauffman 5-Aug-19994* Update callbacks to support different FRU formats*%* X-55 WBF Burns Fisher 27-Jul-1999* Add glx$cfg_compat*)* X-54 RAB Richard A. Bishop 29-Oct-19985* Remove GLX$MEM_CONFIG_INFO and GLX$MEM_CONFIG_PFN.6* They are now MMG$* and are found in MMG_ROUTINES.H.*(* X-53 JRK390 Jim Kauffman 5-Oct-19985* Add flags parameter to glx$_instance_packet_notify*&* X-52 DMB Dave Bernardo 14-Aug-19986* Add some cruft around GLOCKDEF to get __NEW_STARLET* defined. See comments below.*/* X-51 PKH-G034 Paul K. Harter, Jr. 21-Jul-1998=* Modify prototype for glx$log_message to add message length+* and optional OPC type and FAO arguments.*)* X-50 KLN2091 Karen L. Noel 8-Jul-19982* Add new routines to read shared memory bitmaps.*#* X-49 Dave Bernardo 24-Jun-19980* Add accmode parameter to glx$init_lock_table.*** X-48 KLN2087 Karen L. Noel 24-Jun-19982* Change shm_cpp routines to accept wait context.*(* X-47 JRK390 Jim Kauffman 23-May-19989* Add incarnation parameter to glx$find_instance_primary*#* X-46 Dave Bernardo 14-Apr-19986* Remove galaxy locking system services. They are in * STARLET now.*(* X-45 JRK390 Jim Kauffman 3-Apr-19983* Add several of SMP/Galaxy communication routines*%* X-44 AHM043 Drew Mason 5-Mar-1998.* Change prototype for glx$leave_galaxy. Add* glx$finish_leaving.* * X-43 Tom Benson 24-Feb-19985* Added glx$shm_reg_recover, glx$shm_reg_reset, and * glx$shm_cpp_recover.*&* X-42 DMB Dave Bernardo 25-Feb-1998* Add glx$break_locks.*(* X-41 WBF Burns Fisher 27-Feb-19986* Add wait_context parameter to GLX$SHM_REG_ADD_PAGES*&* X-40 AHM040 Drew Mason 25-Feb-19987* Add glx$shmem_reform_galaxy, glx$reform_rejoin_fork,:* and glx$check_dead_node_fork. Change glx$reform_galaxy* to take an int parameter.*&* X-39 AHM039 Drew Mason 24-Feb-19985* Change prototype for membership callbacks. Remove5* glx$mem_change_wrapper. Add glx$reform_galaxy and* glx$validate_galaxy.*/* X-38 PKH-G013 Paul K. Harter, Jr. 19-Feb-1998&* Add prototype for glx$leave_galaxy.* * X-37 Tom Benson 16-Feb-1998=* Added glx$shm_cpp_galaxy_exit and glx$shm_reg_galaxy_exit.*&* X-36 DMB Dave Bernardo 13-Feb01998/* Another change the the *lock_table routines.9* Add prototypes for $reset_lock and $delete*lock_table.)* Add internal use only get_member_info.*)* X-35 EMB Ellen M. Batbouta 11-Feb-1998* Remove glx$event_notify.*%* X-34 AHM037 Drew Mason 3-Feb-1998* PKH-G010 Paul K. Harter, Jr.,* Add prototypes for glx$remove_node_start,1* glx$remote_crash_fork, glx$reform_galaxy_fork,0* glx$get_member_info, glx$start_validate_fork,1* glx$done_validate_fork, glx$node_leaving_fork.* Include mbr_infodef.h.*)* X-33 EMB Ellen M. Batbouta 03-Feb-1998* Add glx$event_notify.*(* X-32 JRK390 Jim Kauffman 29-Jan-1998=* Add glx$all_instance_bit_notify and glx$find_all_primaries*&* X-31 AHM035 Drew Mason 29-Jan-19982* Add glx$remove_node and glx$mem_change_wrapper.* * X-30 Tom Benson 27-Jan-19989* Added glx$shm_reg_id_to_va and glx$mmap_get_fragments.*(* X-29 JRK390 Jim Kauffman 23-Jan-19989* Resynch glx$get_cpu_handle_owner parameter definitions"* with new console GCT structures*&* X-28 DMB Dave Bernardo 20-Jan-19989* The init_lock_table routines needs two size parameters;* the create_lock_table routines needs one size parameter.*** X-27 KLN2048 Karen L. Noel 21-Jan1-9985* Change glx$shm_reg prototypes again. They weren't * quite right...*&* X-26 AHM033 Drew Mason 15-Jan-1998+* Added prototype for glx$mem_change_fork.*** X-25 KLN2046 Karen L. Noel 14-Jan-1998&* o Add routine glx$shm_reg_va_to_id.-*  o Change prototype for glx$shm_reg_create.-* o Change prototype for glx$shm_reg_delete.*&* X-24 AHM033 Drew Mason 13-Jan-19984* Change prototype for glx$kick_off_join to have no* parameters.*&* X-23 AHM032 Drew Mason 13-Jan-1998$* Added glx$reg_member_callback and* glx$del_member_callback.*&* X-22 AHM031 Drew Mason 12-Jan-1998* Added glx$crash_all_nodes.* * X-21 Tom Benson 08-Jan-1998'* Corrected glx$shm_cpp_get_info args.*#* X-20 Dave Bernardo 07-Jan-1998* More locking prototypes.*(* X-19 JRK390 Jim Kauffman 18-Dec-1997,* Add prototypes for communication routines*&* X-18 AHM029 Drew Mason 18-Dec-19970* Add prototypes for the IP interrupt handlers.*** X-17 KLN2035 Karen L. Noel 17-Dec-1997)* o Add a prototype for glx$log_message.7* o Add proto_pte and return_virt_length arguments to * glx$shm_reg_create.*** X-16 KLN2031 Karen L. Noel 11-Dec-19977* The prototype for glx$shm_cpp_get_info doesn't match6* the declaration. This is okay. It has some optional * arguments.*** X-15 KLN2030 Karen L. Noel 09-Dec-19974* Allow glx$shm_cpp_disconnect to specify gNode id.*/* X-14 PKH-G004 Paul K. Harter, Jr. 05-Dec-19975* Corrected null parameter lists for glocks, cpucom,6* member services and cpuinfo to "(void)" and changed2* shmem_gmdb_init and shmem_gmdb_init to use null* parameter lists.8* Moved member services protos from LONG pointer scope.*** X-13 KLN2026 Karen L. Noel 04-Dec-1997/* Change MMAP prototypes to include region id.*#* X-12 Dave Bernardo 04-Dec-1997<* Fix prototypes for glx$glock_*. Add glx$init_galaxy_lock.6* Add missing glx$glock membership services routines.*%* X-11 AHM025 Drew Mason 3-Dec-19971* Add prototypes for membership services and CPU* communications.*#* X-10 Karen L. Noel 24-Nov-1997* Add change X-8 back.*)* X-9 KLN2021 Karen L. Noel 20-Nov-1997:* Update the glx$shm_cpp_alloc_pages prototype to use the* proper type for flags.*"* X-8 Dave Bernardo 20-Nov-1997* Fix $reset_lock protypes.*)* X-7 KLN2019 Karen L. Noel 13-Nov-1997* Update some prototypes.*.* X-6 KLN2018 Karen L. Noel 7-Nov-1997(* Add prototype for glx$mem_config_pfn.* "* X-5 Dave Bernardo 06-Nov-1997* Add locking prototypes.*)* X-4 KLN2013 Karen L. Noel 23-Oct-19973* Add prototypes for memory config info functions.*)* X-3 KLN2010 Karen L. Noel 22-Oct-1997* Add GMDB definition.*)* X-2 KLN2005 Karen L. Noel 13-Oct-1997"* Add SHM_REG and SHMEM routines.*)* X-1 KLN2003 Karen L. Noel 9-Sep-1997;* Initial version containing primitive GLX shared memory * managment routine interfaces.* *--*/#ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save'#pragma __required_pointer_size __short#endif/*G* Define all types that are used in the following function prototypes.*/#include #include #include #include #include #include #include #include #include 7#include /* MMAP and PFNLST definitions */3#include /* PFN and PMAP definitions */#include #include #include #include #include /* O The following crockery is the result of moving GLOCKDEF from LIB to Starlet.I There is code on the masterpack which includes GLX_ROUTINES but is notF built with __NEW_STARLET defined. Unfortunately, it's required for 4 GLX_ROUTINES and GLOCKDEF to play nice together. */#ifndef __NEW_STARLET,#define __glockdef_defined_new_starlet__ = 1#define __NEW_STARLET = 1#endif#include '#ifdef __glockdef_defined_new_starlet__'#undef __glockdef_defined_new_starlet__#undef __NEW_STARLET #endif/*P VMS system routine entry points are defined externally using uppercase names.H The macro preceding each prototype allows the usage of the lowercase L versions of these names even in the presence of the /NAME=AS_IS compiler switch.*//*( Memory configuration info functions */3#define glx$shmem_config_desc GLX$SHMEM_CONFIG_DESC{ int glx$shmem_config_desc (uint32 max_fragments, UINT64_PQ wildcard_context_p, UINT32_PQ frag_count_p, PMAP_PQ pmap_p);1#define glx$shmem_config_all GLX$SHMEM_CONFIG_ALL int glx$shmem_config_all (uint32 max_mem_desc_nodes, uint32 max_frag_per_node, UINT32_PQ total_frag_count_p, PMAP_PQ pmap_p);#ifdef VMS$PFNBITS_323#define glx$shmem_config_gmdb GLX$SHMEM_CONFIG_GMDBM int glx$shmem_config_gmdb (UINT32_PQ gmdb_pfn_p, UINT32_PQ gmdb_pages_p);#endif/** GMDB mapping and allocation functions */1#define glx$gmdb_map_initial GLX$GMDB_MAP_INITIALR int glx$gmdb_map_initial (uint64 initial_gmdb_length, GMDB_PPQ return_gmdb_p);+#define glx$gmdb_allocate GLX$GMDB_ALLOCATE int glx$gmdb_allocate (GMDB_PQ initial_gmdb_p, uint64 initial_gmdb_length, uint64 total_gmdb_length, GMDB_PPQ return_gmdb_p);3#define glx$gmdb_map_continue GLX$GMDB_MAP_CONTINUEj int glx$gmdb_map_continue (GMDB_PQ inital_gmdb_p, uint64 initial_gmdb_length, GMDB_PPQ return_gmdb_p, ! UINT64_PQ return_gmdb_length_p);%#define glx$gmdb_unmap GLX$GMDB_UNMAP< int glx$gmdb_unmap (GMDB_PQ gmdb_p, uint64 gmdb_length);/* Shared memory CPP functions*/1#define glx$shm_cpp_get_size GLX$SHM_CPP_GET_SIZE7 void glx$shm_cpp_get_size (UINT64_PQ return_size_p);#ifndef __SHM_CPP_SOURCE#ifdef VMS$PFNBITS_321#define glx$shm_cpp_get_info GLX$SHM_CPP_GET_INFO; int glx$shm_cpp_get_info (SHM_CPP_ID shm_cpp_id, ...); #endif/* Optional arguments:G UINT32_PQ free_pages_p, UINT32_PQ total_pgcnt_p, UINT32_PQ min_pfn_p, 4 UINT32_PQ max_pfn_p, SHMEM_FLAGS_PQ shmem_flags_p,  UINT32_PQ bad_pages_p */)#define glx$shm_cpp_init GLX$SHM_CPP_INITt in t glx$shm_cpp_init (SHM_CPP_ID shm_cpp_id, uint32 min_pfn, uint32 max_pfn, PMAP_PQ pmap_p, uint32 flags, ...);#endif3#define glx$shm_cpp_add_pages GLX$SHM_CPP_ADD_PAGESZ int glx$shm_cpp_add_pages (SHM_CPP_ID shm_cpp_id, uint32 first_pfn, uint32 pfn_count);/#define glx$shm_cpp_connect GLX$SHM_CPP_CONNECTK int glx$shm_cpp_connect (SHM_CPP_ID shm_cpp_id, VOID_PQ wait_context_p);5#define glx$shm_cpp_disconnect GLX$SHM_CPP_DISCONNECT` int glx$shm_cpp_disconnect (SHM_CPP_ID shm_cpp _id, uint32 gnode_id, VOID_PQ wait_context_p);;#define glx$shm_cpp_acquire_glock GLX$SHM_CPP_ACQUIRE_GLOCKR int glx$shm_cpp_acquire_glock (SHM_CPP_ID shm_cpp_id, VOID_PQ wait_context_p);;#define glx$shm_cpp_release_glock GLX$SHM_CPP_RELEASE_GLOCK: int glx$shm_cpp_release_glock (SHM_CPP_ID shm_cpp_id);#ifdef VMS$PFNBITS_327#define glx$shm_cpp_alloc_pages GLX$SHM_CPP_ALLOC_PAGESp int glx$shm_cpp_alloc_pages (SHM_CPP_ID shm_cpp_id, uint32 page_count, uint32 list_id, SHM_CPP_ALLOC flags, 3 UINT32_PQ return_pfn_p, UINT32_PQ return_count_p);#endif;#define glx$shm_cpp_dealloc_pages GLX$SHM_CPP_DEALLOC_PAGESi int glx$shm_cpp_dealloc_pages (SHM_CPP_ID shm_cpp_id, uint32 pfn, uint32 page_count, uint32 list_id);8#define glx$shm_cpp_galaxy_exit GLX$SHM_CPP_GALAXY_EXIT ' int glx$shm_cpp_galaxy_exit (void);/#define glx$shm_cpp_recover GLX$SHM_CPP_RECOVER. int glx$shm_cpp_recover (uint32 gnode_id);/* % Memory map manipulation functions*/##def ine glx$mmap_init GLX$MMAP_INITw int glx$mmap_init (MMAP_PQ mmap_p, uint64 virt_size, uint64 phys_size, SHM_CPP_ID shm_cpp_id, VOID_PQ wait_context,+ SHM_ID shm_reg_id, UINT64_PQ phys_size_p);1#define glx$mmap_alloc_pages GLX$MMAP_ALLOC_PAGES int glx$mmap_alloc_pages (MMAP_PQ mmap_p, uint64 virt_offset, uint64 phys_size, SHM_CPP_ID shm_cpp_id, VOID_PQ wait_context,+ SHM_ID shm_reg_id, UINT64_PQ phys_size_p);'#define glx$mmap_delete GLX$MMAP_DELETE? int glx$mmap_delete (MMAP_ PQ mmap_p, VOID_PQ wait_context);/#define glx$mmap_map_object GLX$MMAP_MAP_OBJECTJ int glx$mmap_map_object (MMAP_PQ mmap_p, PTE_PQ pte_p, PTE proto_pte);5#define glx$mmap_get_fragments GLX$MMAP_GET_FRAGMENTS1 int glx$mmap_get_fragments (MMAP_PQ mmap_ptr,D UINT32_PQ fragment_count, uint32 max_pmap_count, PMAP_PQ pmap_ptr);/*" Shared Memory Region Functions*/.#define glx$shm_reg_create GLX$SHM_REG_CREATE #ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __ longs int glx$shm_reg_create (VOID_PQ tag_p, SHMEM_FLAGS flags, uint64 reserved, VOID_PQ sys_va, uint64 virt_length, 5 uint64 phys_length, uint64 context, PTE proto_pte,  int (*callback_routine)(V int reason, uint32 gnode_id, SHM_ID shm_reg_id, VOID_PQ sys_va, uint64 virt_length),1 VOID_PQ wait_context_p, SHM_ID_PQ shm_reg_id_p);'#pragma __required_pointer_size __short#endif-#define glx$shm_reg_delete GLX$SHM_REG_DELETEG int glx$shm_reg_delete (SHM_ID shm_reg_id, VOID_PQ wai t_context_p);4#define glx$shm_reg_add_pages GLX$SHM_REG_ADD_PAGES w int glx$shm_reg_add_pages (SHM_ID shm_reg_id, uint32 flags, uint64 reserverd, uint64 shm_reg_offset, uint64 length, VOID_PQ wait_context_p); 1#define glx$shm_reg_get_info GLX$SHM_REG_GET_INFOn int glx$shm_reg_get_info (VOID_PQ tag_p, SHM_ID shm_reg_id, SHMEM_INFO flags, UINT64_PQ wildcard_context, c SHM_ID_PQ shm_reg_id_p, SHMEM_FLAGS_PQ shmem_flags_p, VOID_PPQ sys_va_p, UINT64_PQ virt_length_p, l UINT64_PQ phy s_length_p, UINT32_PQ fragment_count, SHORT_PQ return_tag_length, UINT64_PQ return_context_p);3#define glx$shm_reg_get_nodes GLX$SHM_REG_GET_NODESg int glx$shm_reg_get_nodes (VOID_PQ tag_p, SHM_ID shm_reg_id, SHMEM_INFO flags, CBB_PQ nodes_cbb_p);1#define glx$shm_reg_get_pmap GLX$SHM_REG_GET_PMAPp int glx$shm_reg_get_pmap (SHM_ID shm_reg_id, uint32 max_pmap_count, PMAP_PQ pmap_p, UINT32_PQ pmap_count_p);)#define glx$shm_reg_size GLX$SHM_REG_SIZE, int glx$shm_reg_size (UINT64_P Q size_p);)#define glx$shm_reg_init GLX$SHM_REG_INIT- int glx$shm_reg_init (SHM_ID shm_reg_id);2#define glx$shm_reg_va_to_id GLX$SHM_REG_VA_TO_ID v int glx$shm_reg_va_to_id (VOID_PQ sys_va, int acmode, SHM_ID_PQ shm_reg_id_p, UINT64_PQ offset_p, INT_PQ valid_p);2#define glx$shm_reg_id_to_va GLX$SHM_REG_ID_TO_VA ] int glx$shm_reg_id_to_va (SHM_ID shm_reg_id, VOID_PPQ sys_va_p, UINT64_PQ virt_length_p);}#define glx$shm_reg_incref GLX$SHM_REG_INCREF  - int glx$shm_reg_incref (PFN_PQ pfndbe_p);-#define glx$shm_reg_decref GLX$SHM_REG_DECREF- int glx$shm_reg_decref (PFN_PQ pfndbe_p);8#define glx$shm_reg_galaxy_exit GLX$SHM_REG_GALAXY_EXIT ' int glx$shm_reg_galaxy_exit (void);/#define glx$shm_reg_recover GLX$SHM_REG_RECOVER. int glx$shm_reg_recover (uint32 gnode_id);+#define glx$shm_reg_reset GLX$SHM_REG_RESET! int glx$shm_reg_reset (void);/*& Shared Memory Management Functions*/#ifndef __SHMEM_SOURCE#ifdef VMS$PFNBITS_32-#define glx$shmem_get_info GLX$SHMEM_GET_INFOr int glx$shmem_get_info (uint32 pfn, SHMEM_INFO flags, UINT64_PQ wildcard_context, SHM_CPP_ID_PQ shm_cpp_id_p, z UINT32_PQ low_pfn_p, UINT32_PQ pfn_count_p, SHMEM_FLAGS_PQ shmem_flags_p, UINT32_PQ free_pages_p, UINT32_PQ bad_pages_p,  ...);#endif#endif /* __SHMEM_SOURCE*/1#define glx$config_new_shmem GLX$CONFIG_NEW_SHMEMC int glx$config_new_shmem (uint32 first_pfn, uint32 page_count);/#define glx$shmem_gmdb_size GLX$SHMEM_GMDB_SIZE/ int glx$shmem_gmdb_size (UINT64_PQ size_p);0#define glx$shmem_gmdb_init GLX$SHMEM_GMDB_INIT # int glx$shmem_gmdb_init (void);/#define glx$shmem_gmdb_join GLX$SHMEM_GMDB_JOIN# int glx$shmem_gmdb_join (void);5#define glx$shmem_recover_gmdb GLX$SHMEM_RECOVER_GMDB1 int glx$shmem_recover_gmdb (uint32 gnode_id);7#define glx$shmem_reform_galaxy GLX$SHMEM_REFORM_GALAXY& int glx$shmem_reform_galaxy(void);3#define glx$shmem_galaxy_exit GLX$SHMEM_GALAXY_EXIT% int glx$shmem_galaxy_exit (void);&/* Galaxy locking internal routines */#ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __long)#define glx$acquire_lock GLX$ACQUIRE_LOCK8 int glx$acquire_lock(uint64 lock_handle, ) uint32 timeout,' uint32 flags,* VOID_PQ context);'#define glx$break_locks GLX$BREAK_LOCKS+ int glx$break_locks(GLCKTBL *lcktbl_va, uint32 lcktbl_handle, uint64 reg_va, int32 gnode, int32 cpu, int32 epid);'#define glx$create_lock GLX$CREATE_LOCK< int glx$create_lock(uint32 lcktbl_handle, ( CHAR_PQ name, ' uint32 size,+ uint32 timeout, ' uint32 ipl, ( uint32 rank, /  UINT64_PQ lock_handle); 5#define glx$create_galaxy_lock GLX$CREATE_GALAXY_LOCK8 int glx$create_galaxy_lock(uint32 lcktbl_handle, / CHAR_PQ name, . uint32 size,2 uint32 timeout, . uint32 ipl, / uint32 rank, 6 UINT64_PQ lock_handle);8  3#define glx$create_lock_table GLX$CREATE_LOCK_TABLE8 int glx$create_lock_table(CHAR_PQ name, 1 uint32 accmode,  uint64 section_size,5 uint32 section_type,. uint32 prot, 3 uint32 lock_size, 7 UINT32_PQ lcktbl_handle);A#define glx$create_galaxy_lock_table GLX$CREATE_GALAXY_LOCK_TABL E8 int glx$create_galaxy_lock_table(CHAR_PQ name, 8 uint32 accmode, uint64 section_size,< uint32 section_type,5 uint32 prot, : uint32 lock_size, > UINT32_PQ lcktbl_handle);'#define glx$delete_lock GLX$DELETE_LOCK8 int glx$delete_lock(uint64 lock_handle); 5#defin e glx$delete_galaxy_lock GLX$DELETE_GALAXY_LOCK? int glx$delete_galaxy_lock(uint64 lock_handle); 3#define glx$delete_lock_table GLX$DELETE_LOCK_TABLE8 int glx$delete_lock_table(uint32 lcktbl_handle); A#define glx$delete_galaxy_lock_table GLX$DELETE_GALAXY_LOCK_TABLE? int glx$delete_galaxy_lock_table(uint32 lcktbl_handle); +#define glx$get_lock_info GLX$GET_LOCK_INFO8 int glx$get_lock_info(uint64 lock_handle, * CHAR_PQ  name, - UINT32_PQ timeout, ) UINT32_PQ size,) UINT32_PQ ipl, * UINT32_PQ rank, + USHORT_PQ flags,5 ...); /* Allow SHORT_PQ to return name length */+#define glx$get_lock_size GLX$GET_LOCK_SIZE8 int glx$get_lock_size(UINT32_PQ min_size, / UINT32_PQ max_size );##define glx$init_lock GLX$INIT_LOCK8 int glx$init_l ock(GLOCK *va, & CHAR_PQ name, % uint32 size,) uint32 timeout, % uint32 ipl, & uint32 rank, - UINT64_PQ lock_handle);1#define glx$init_galaxy_lock GLX$INIT_GALAXY_LOCK? int glx$init_galaxy_lock(GLOCK *va, , CHAR_PQ name, , uint32 size,0  uint32 timeout, , uint32 ipl, - uint32 rank, 4 UINT64_PQ lock_handle);/#define glx$init_lock_table GLX$INIT_LOCK_TABLE0 int glx$init_lock_table(VOID_PQ region_va, uint32 accmode, 4 uint64 reg_phys_size,4 uint64 reg_virt_size,3 uint32 section_type,1  uint32 lock_size, 5 UINT32_PQ lcktbl_handle);=#define glx$init_galaxy_lock_table GLX$INIT_GALAXY_LOCK_TABLE7 int glx$init_galaxy_lock_table(VOID_PQ region_va,9 uint64 reg_phys_size,8 uint64 reg_virt_size,: uint32 section_type,8 uint32 lock_size, < UINT32_PQ lcktbl_handle);)#define glx$release_lock GLX$RELEASE_LOCK9 int glx$release_lock(uint64 lock_handle); %#define glx$reset_lock GLX$RESET_LOCK9 int glx$reset_lock(uint64 lock_handle, - GLOCK **lock_va_ret);4#define glx$reset_galaxy_lock GLX$RESET_GALAXY_LOCK 9 int glx$reset_galaxy_lock(uint64 lock_handle, 4 GLOCK **lock_va_ret);,#define glx$wait_on_glock GLX$WAIT_ON_GLOCK *int glx$wait_on_glock(uint64 lock_handle,  uint32 timeout);:#define glx$notify_glock_waiters GLX$NOTIFY_GLOCK_WAITERS 1int glx$notify_glock_waiters(uint64 lock_handle, uint64 waiters );+#define glx$check_process GLX$CHECK_PROCESSvoid glx$check_process(void);<#define glx$release_glock_waiters GLX$RELEASE_GLOCK_WAITERS %void glx$release_glock_waiters(void);+ 5/* Galaxy membership services routines for locking */3#define glx$glock_galaxy_exit GLX$GLOCK_GALAXY_EXIT1 int glx$glock_galaxy_exit(uint64 time_limit);/#define glx$glock_gmdb_init GLX$GLOCK_GMDB_INIT" int glx$glock_gmdb_init(void);/#define glx$glock_gmdb_join GLX$GLOCK_GMDB_JOIN" int glx$glock_gmdb_join(void);/#define glx$glock_gmdb_size GLX$GLOCK_GMDB_SIZE0 int glx$glock_gmdb_size(UINT64_PQ seq_size);5#define glx$glock_recover_gmdb GLX$GLOCK_RECOVER_GMDB0 int glx$glock_recover_gmdb(uint32 node_id);7#define glx$glock_reform_galaxy GLX$GLOCK_REFORM_GALAXY& int glx$glock_reform_galaxy(void);7#define glx$glock_validate_gmdb GLX$GLOCK_VALIDATE_GMDB. int glx$glock_validate_gmdb(uint32 scope);(/* Galaxy CPU Communications routines */5#define glx$cpucom_galaxy_exit GLX$CPUCOM_GALAXY_EXIT2 int glx$cpucom_galaxy_exit(int time_limit[2]);9#define glx$cpucom_validate_gmdb GLX$CPUCOM_VALIDATE_GMDB, int glx$cpucom_validate_gmdb(int scope);7#define glx$cpucom_recover_gmdb GLX$CPUCOM_RECOVER_GMDB- int glx$cpucom_recover_gmdb(int node_id);1#define glx$cpucom_gmdb_init GLX$CPUCOM_GMDB_INIT# int glx$cpucom_gmdb_init(void);1#define glx$cpucom_gmdb_join GLX$CPUCOM_GMDB_JOIN# int glx$cpucom_gmdb_join(void);1#define glx$cpucom_gmdb_size GLX$CPUCOM_GMDB_SIZE1 int glx$cpucom_gmdb_size(UINT64_PQ seg_size);9#define glx$cpucom_reform_galaxy GLX$CPUCOM_REFORM_GALAXY' int glx$cpucom_reform_galaxy(void);/#define glx$init_node_flags GLX$INIT_NODE_FLAGS6 void glx$init_node_flags  (NODEB_PQ node_block_ptr);%/* Galaxy CPU Information routines */7#define glx$cpuinfo_galaxy_exit GLX$CPUINFO_GALAXY_EXIT3 int glx$cpuinfo_galaxy_exit(int time_limit[2]);;#define glx$cpuinfo_validate_gmdb GLX$CPUINFO_VALIDATE_GMDB- int glx$cpuinfo_validate_gmdb(int scope);9#define glx$cpuinfo_recover_gmdb GLX$CPUINFO_RECOVER_GMDB. int glx$cpuinfo_recover_gmdb(int node_id);3#define glx$cpuinfo_gmdb_init GLX$CPUINFO_GMDB_INIT$ int glx$cpuinfo_gmdb_init(void);3#d!efine glx$cpuinfo_gmdb_join GLX$CPUINFO_GMDB_JOIN$ int glx$cpuinfo_gmdb_join(void);3#define glx$cpuinfo_gmdb_size GLX$CPUINFO_GMDB_SIZE2 int glx$cpuinfo_gmdb_size(UINT64_PQ seg_size);;#define glx$cpuinfo_reform_galaxy GLX$CPUINFO_REFORM_GALAXY( int glx$cpuinfo_reform_galaxy(void);'#pragma __required_pointer_size __short#endif#/* Galaxy Communication routines */7#define glx$instance_bit_notify GLX$INSTANCE_BIT_NOTIFYA int glx$instance_bit_notify(int instance_id, u "int64 bitdefs);?#define glx$all_instance_bit_notify GLX$ALL_INSTANCE_BIT_NOTIFYA int glx$all_instance_bit_notify(uint64 bitdefs,uint64 flags);-#define glx$cpu_bit_notify GLX$CPU_BIT_NOTIFY7 int glx$cpu_bit_notify(int cpu_id, uint64 bitdefs);3#define glx$cpu_packet_notify GLX$CPU_PACKET_NOTIFYK int glx$cpu_packet_notify(int cpu_id, int instance_id, VOID_PQ packet);=#define glx$instance_packet_notify GLX$INSTANCE_PACKET_NOTIFYq int glx$instance_packet_notify(int insta #nce_id, uint32 comp_id, uint32 flags, CHAR_PQ packet, uint64 length);;#define glx$find_instance_primary GLX$FIND_INSTANCE_PRIMARY[ int glx$find_instance_primary(int instance_id, INT_PQ cpuid_ptr, UINT64_PQ incarn_ptr);5#define glx$find_all_primaries GLX$FIND_ALL_PRIMARIESF int glx$find_all_primaries(UINT64_PQ cpumask, UINT64_PQ partmask);9#define glx$get_cpu_handle_owner GLX$GET_CPU_HANDLE_OWNERV int glx$get_cpu_handle_owner(int cpu_id, VOID_PPQ handle_ptr, VOID_PPQ owner_ptr$);;#define glx$validate_partition_id GLX$VALIDATE_PARTITION_IDD int glx$validate_partition_id(int node_id, VOID_PPQ handle_ptr);9#define glx$validate_config_tree GLX$VALIDATE_CONFIG_TREE' int glx$validate_config_tree(void);7#define glx$find_partition_name GLX$FIND_PARTITION_NAMEa int glx$find_partition_name (CHAR_PQ name_string, INT64_PQ part_id_ptr, VOID_PPQ handle_ptr);)/* Galaxy Membership Services routines */!#define acquire_gmdb ACQUIRE_GMDB int acquire_gm%db(void);!#define release_gmdb RELEASE_GMDB' void release_gmdb (unsigned broken);##define glx$init_gmdb GLX$INIT_GMDB void glx$init_gmdb (void);##define glx$join_gmdb GLX$JOIN_GMDB int glx$join_gmdb (void);%#define glx$initialize GLX$INITIALIZEA int glx$initialize (void * image_data_block, INIRTN * flags);+#define glx$kick_off_join GLX$KICK_OFF_JOIN! void glx$kick_off_join (void);'#define glx$join_galaxy GLX$JOIN_GALAXY$ void glx$join_galaxy (KPB * k&pb);)#define glx$leave_galaxy GLX$LEAVE_GALAXY int glx$leave_galaxy (void);-#define glx$finish_leaving GLX$FINISH_LEAVING" void glx$finish_leaving (void);3#define glx$exit_cleanup_done GLX$EXIT_CLEANUP_DONE> void glx$exit_cleanup_done (int subfac, int cleanupstatus);'#define glx$local_crash GLX$LOCAL_CRASH+ void glx$local_crash (int bugcheckcode);/#define glx$crash_all_nodes GLX$CRASH_ALL_NODES. int glx$crash_all_nodes (int reason_code);1#define glx$update_hea'rtbeat GLX$UPDATE_HEARTBEAT$ void glx$update_heartbeat (void);'#define glx$log_message GLX$LOG_MESSAGEF void glx$log_message (char *console_string, int console_len, ... );7#define glx$reg_member_callback GLX$REG_MEMBER_CALLBACKF int glx$reg_member_callback (void routine (uint64 info, int type), uint64 info);7#define glx$del_member_callback GLX$DEL_MEMBER_CALLBACKF int glx$del_member_callback (void routine (uint64 info, int type), uint64 info);/#define glx$mem_(change_fork GLX$MEM_CHANGE_FORKB void glx$mem_change_fork (void * foo1, void * foo2, FKB * fkb);3#define glx$remote_crash_fork GLX$REMOTE_CRASH_FORKD void glx$remote_crash_fork (void * foo1, void * foo2, FKB * fkb);3#define glx$remove_node_start GLX$REMOVE_NODE_START* void glx$remove_node_start (KPB * kpb);'#define glx$remove_node GLX$REMOVE_NODE& int glx$remove_node (int node_id);5#define glx$reform_galaxy_fork GLX$REFORM_GALAXY_FORKE void glx$reform_galaxy_fork (void) * foo1, void * foo2, FKB * fkb);+#define glx$reform_galaxy GLX$REFORM_GALAXY' int glx$reform_galaxy (int reason);7#define glx$start_validate_fork GLX$START_VALIDATE_FORKF void glx$start_validate_fork (void * foo1, void * foo2, FKB * fkb);5#define glx$done_validate_fork GLX$DONE_VALIDATE_FORKE void glx$done_validate_fork (void * foo1, void * foo2, FKB * fkb);/#define glx$validate_galaxy GLX$VALIDATE_GALAXY# int glx$validate_galaxy (void);3#define glx$node_leaving_f *ork GLX$NODE_LEAVING_FORKD void glx$node_leaving_fork (void * foo1, void * foo2, FKB * fkb);/#define glx$get_member_info GLX$GET_MEMBER_INFOG int glx$get_member_info (int request, int node_id, MBR_INFO_PQ buf, int len);5#define glx$reform_rejoin_fork GLX$REFORM_REJOIN_FORKE void glx$reform_rejoin_fork (void * foo1, void * foo2, FKB * fkb);9#define glx$check_dead_node_fork GLX$CHECK_DEAD_NODE_FORKG void glx$check_dead_node_fork (void * foo1, void * foo2, FKB * fkb)+;E/* Galaxy execlet internal use only - only does check for the GMDB */'#define get_member_info GET_MEMBER_INFOC int get_member_info (int request, int node_id, MBR_INFO_PQ buf, int len);"/* Galaxy IP interrupt handlers */7#define glx$hnd_crash_all_nodes GLX$HND_CRASH_ALL_NODES' void glx$hnd_crash_all_nodes (void);3#define glx$hnd_reform_galaxy GLX$HND_REFORM_GALAXY% void glx$hnd_reform_galaxy (void);3#define glx$hnd_reform_rejoin GLX$HND_REFORM_REJOIN% voi,d glx$hnd_reform_rejoin (void);1#define glx$hnd_remote_crash GLX$HND_REMOTE_CRASH$ void glx$hnd_remote_crash (void);9#define glx$hnd_remote_pfn_found GLX$HND_REMOTE_PFN_FOUND( void glx$hnd_remote_pfn_found (void);5#define glx$hnd_start_validate GLX$HND_START_VALIDATE& void glx$hnd_start_validate (void);3#define glx$hnd_done_validate GLX$HND_DONE_VALIDATE% void glx$hnd_done_validate (void);1#define glx$hnd_node_leaving GLX$HND_NODE_LEAVING$ void glx$hnd_node_leaving - (void);;#define glx$hnd_membership_change GLX$HND_MEMBERSHIP_CHANGE) void glx$hnd_membership_change (void);%#define glx$map_bitmap GLX$MAP_BITMAPU int glx$map_bitmap (uint32 start_pfn, uint32 page_count, UINT64_PPQ bitmap_va_p);*#define glx$unmap_bitmap GLX$UNMAP_BITMAP T int glx$unmap_bitmap (uint32 start_pfn, uint32 page_count, UINT64_PQ bitmap_va);8#define glx$good_page_in_bitmap GLX$GOOD_PAGE_IN_BITMAP cint glx$good_page_in_bitmap (uint32 start_pfn, uint32 page_count, .UINT64_PQ bitmap_va, uint32 pfn);#ifdef VMS$PFNBITS_32:#define glx$good_range_in_bitmap GLX$GOOD_RANGE_IN_BITMAP uint glx$good_range_in_bitmap (uint32 start_pfn, uint32 page_count, INT_PQ good_status_p, UINT32_PQ first_bad_page_p);#endif%#define glx$cfg_compat GLX$CFG_COMPATint glx$cfg_compat(void);#ifdef __INITIAL_POINTER_SIZE)#pragma __required_pointer_size __restore#endif"#endif /* __GLX_ROUTINES_LOADED */ww`ZUN/*************************************/****************************************N** *N** HPE CONFIDENTIAL. This software is confidential proprietary software *N** licensed by Hewlett Packard Enterprise Development, LP, and is not *N** authorized to be used, duplicated or disclosed to anyone without the *N** prior written permission of HPE. *N** Copyright 2019 Copyright Hewlett Packard Enterprise Develop0ment, LP *N** *N** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *N** proprietary software licensed by VMS Software, Inc., and is not *N** authorized to be used, duplicated or disclosed to anyone without *N** the prior written permission of VMS Software, Inc. *N** Copyright 2019 Copyright VMS Software, Inc. *N** 1 *N*****************************************************************************/O///////////////////////////////////////////////////////////////////////////////// // FACILITY://// IVMSLOA// // ABSTRACT://E// Function prototypes for System Global Routines defined within// this facility.// // AUTHORS://// Tony Camuso//// MODIFIED BY://'// X-4 AHM Drew Mason 23-May-2019!//2 Added __pointer_size pragmas.//G// X-3 TLC Tony Camuso 22-Jun-2006B// Modified ioc$node_data to take variable arguments.////G// X-2 TLC Tony Camuso 29-Oct-20022// Added test to exclude ALPHA build.//+// X-1 MOVED FROM [LIB] to [LIB_H]%// Version numbers Reset//O// ----------------------------------------------------------------------------//G// X-3 3 TLC Tony Camuso 22-Oct-2002.// Added #include //G// X-2 TLC Tony Camuso 21-Oct-20023// Added proto for ioc$find_boot_adp()//G// X-1 TLC Tony Camuso 18-Oct-2002// Initial entry.//////>#if !defined( __GPS_ROUTINES_LOADED__ ) && !defined( __alpha )#define __GPS_ROUTINES_LOADED__)/*************************************4***** INCLUDE FILES AND LIBRARIES)****************************************///E// Files implicitly included are left // Implicitly Included byE// as comments for reference. // ======================//=//#include // exe_routines.h#include ;//#include // vms_macros.h#include #include #include ;//#include 5 // vms_macros.h#include <//#include // vms_drivers.h=//#include // exe_routines.h#include #include ;//#include // vms_macros.h#include #include &#pragma __required_pointer_size __save'#pragma __required_pointer_size __short)/****************************************** SYSTEM GLOBAL ROUTINES)**6**************************************/)/////////////////////////////////////////// From gps$main.c)/////////////////////////////////////////extern int ini$iomap();)/////////////////////////////////////////// From gps$irq_support.c)/////////////////////////////////////////extern DIDT* ioc$get_didt();)/////////////////////////////////////////// From gps$routines.c)/////////////////////////////////////////'extern int exe$startupadp( ADP* pAdp );'extern int exe$shutdwnad7p( ADP* pAdp );"extern int exe$inibootadp( void );extern int ioc$load_map ( ADP* pAdp, CRCTX* pCrctx, PTE* pSvapte, int boff, void** ppDmaAddr );Aextern int ioc$node_function ( CRB* pCrb, int iFuncCode, ... );Pextern int ioc$node_data ( CRB* pCrb, int iFuncCode, void* pBuffer, ... );3extern int ioc$shutdown_controllers( ADP* pAdpIn );%extern ADP* ioc$tr_to_adp( int iTr );exte8rn int ioc$read_pci_config ( ADP *pAdp, int iNode, int iOffset, int iLength, int *pData );extern int ioc$write_pci_config ( ADP *pAdp, int iNode, int iOffset, int iLength, int iData );extern int ioc$find_boot_adp ( BTADP *pBtadp, ADP **ppAd9p, BUSARRAYENTRY **ppBae,% int *pVectorList,% int *pVectorCount ); extern int ioc$init_io_bridge();)#pragma __required_pointer_size __restore!#endif // __GPS_ROUTINES_LOADED__ww3ZU#ifndef _IA64_ASM_H#define _IA64_ASM_H//++// Module IA64_ASM.H "X-7"//'// IA-64 Assembly Language Include File//N/****************************************************************************/@// Copyright 2002 C :ompaq Information Technologies Group, L.P.//E// Compaq and the Compaq logo are trademarks of Compaq InformationB// Technologies Group, L.P. in the U.S. and/or other countries.//L// Confidential computer software. Valid license from Compaq required forH// possession, use or copying. Consistent with FAR 12.211 and 12.212,H// Commercial Computer Software, Computer Software Documentation, andM// Technical Data for Commercial Items are licensed to the U.S. Government1// un;der vendor's standard commercial license.N/****************************************************************************/// // Module Name: //// ia64_asm.h// // Abstract://I// This module contains generic macros for IA-64 assembly language code.// // Author://// Revision History://)// X-7 GHJ Gregory H. Jordan 24-Aug-2005*// Add TR_PRINT macro for IA64 assembler.//*// X-6 KLN3353 Karen L. Noel 12-Sep-2003// Add EXC_PRINT macro.//*// X-5 KLN3141 Karen L. Noe<l 20-Nov-2002// Put code in $CODE$ psect.//'// X-4 PJB0017 Paul Benoit 14-Oct-2002// Add "bug_check" macro. //#// X-3 DAG Doug Gordon 20-Sep-2002&// Added ias$$label and helper macros////-- #ifndef TRUE#define TRUE 1#endif #ifndef FALSE#define FALSE 0#endifA#define PROCEDURE_ENTRY(name) .section $CODE$, "ax", "progbits";\ .type name, @function;\ .proc name; \name::'#define PROCEDURE_EXIT(name) .endp name/*[ What follows is a bug_c=heck_fatal macro for IA64 assembler programmers which can be usedY to generate a bugcheck. Note that you can not use this macro to generate non-fatal or cold-reboot type bugchecks.3 Example: (note the bugcheck type is upper case)% bug_check_fatal (INCONSTATE);*/$#define bug_check_fatal(code) \# .global BUG$_##code; \ movl r17 = BUG$_##code; \ or r17 = 4,r17; \ break.m BREAK$C_SYS_BUGCHECK;/*U What follows is a bug_check macro> for IA64 assembler programmers which can be used to generate a bugcheck. Example:, bug_check (INCONSTATE, FATAL, WARM);*/#define BUGCHK_FATAL 4#define BUGCHK_NONFATAL 0#define BUGCHK_POWEROFF 2#define BUGCHK_COLD 1#define BUGCHK_WARM 08#define bug_check(code, severity, reboot) \. .global BUG$_##code; \) movl r17 = BUG$_##code; \, or r17 = BUGCHK_##severity, r17; \, or r17 = BUGCHK_##reboot, r17?; \ break.m BREAK$C_SYS_BUGCHECK;/* ? * Macro (and helpers) to generate unique labels within macros.= * This macro will generate a unique set of labels every time; * the calling macro is expanded assuming that the C #line = * directive is not used. Use only inside of other macros. : * It relies on the fact that C macros are always expanded * into one line. ** * NOTE: requires /STANDARD=COMMON to work *; * Many conditions can be predicated within macros to avoid:@ * branching altogether, but one example is code that does7 * a consistency check and bugchecks on failure. Since> * bugcheck is a macro itself, it cannot be easily predicated. *6 * Credit to note 3162.* in the DEC C notes conference * * Usage: * * ias$$label(labid) *= * labid - unique label identifier. ias$$label will generate5 * the same label for the same identifier within the+ * same macro. Labels will have the form:4 * Ln_labid where "n" is line number of the calliAng * macro. * * define VALIDATION_SAMPLE\- * [code that sets P6=1 if everything is OK] * (p6) br ias$$label(1)\ * bug_check(INCONSTATE)\ * ias$$label(1): */#define ias$$xcat(x,y) x ## y$#define ias$$cat(x,y) ias$$xcat(x,y)M#define ias$$label(labid) ias$$cat(ias$$cat(L,__LINE__), ias$$cat(_, labid))/*2 * EXC_PRINT - Exception print to EXC trace buffer *D * This macro adds an informational message to the EXC trace buffer.B * The ctrstr argument has similar synBtax to a "printf" statement. *E * Inputs: prefix - Text string to append to the start of labels used * by this macro. A * ctrstr - The text and optional formatting directives to be : * saved in the trace ring buffer, only the following* * directives are allowed (no width):# * %s - zero-terminated string. * %a - ascii string (pointer and length) * %d - decimal value! * %X - hexadecimal longword! * %L - hexadecimal quadword * * Implied iCnputs:D * out1-out5 The corresponding values to be formatted. For the %s= * directive, this is the address of the zero-terminated@ * string. For the %a directive, this requires 2 arguments,? * first the address of the string buffer, then the length? * of the string (by value). Other directives, are passed  * by value. * Output: none * * Usage Examples: * * mov out1 = 15 * EXC_PRINT(IAS1$, "This is an IAS test, index %d")  * * mov out1 = r3 * m Dov out2 = r5@ * EXC_PRINT(IAS2$, "This is a hex number %X and a quadword %L") * * Notes: H * o If EXC tracing has not been started, no call is made to the tracingA * routine. (This attempts to minimize the performance impact.)F * o SP must be properly aligned for a call when the macro is invoked.H * o GP, R8 and R9 are preserved across the call to the tracing routine. * */)#define EXC_PRINT(prefix, ctrstr) \ .global EXC$GQ_DEBUG ;\+ .pushsectio En $DATA$, "wa", "progbits" ;\Bprefix##string: ;\; stringz ctrstr ;\; .popsection ;\B \7 addl r25 = @ltoff(EXC$GQ_DEBUG), gp ;\% ld8 r25 = [r25] ;\% ld8 r25 = [r25] ;\* tbit.z p6 = r25, 0 ;\?(p6) br.cond.spnt prefix##labe Fl ;\B \# mov r26 = 0xf ;\8 andcm r25 = r25, r26 ;\3 ld4 r25 = [r25] ;\2 sxt4 r25 = r25 ;\B \7 add r12 = -8*8, r12 ;\7 add r26 = 2*8,r12 ;\4 st8 [r26] = gp, G8 ;\8 st8 [r26] = r8,8 ;\2 st8 [r26] = r9 ;\B \5 ld8 r26 = [r25],8 ;\7 ld8 gp = [r25] ;\1 mov b6 = r26 ;\B \0 mov r25 = 6 ;\8 movl Hout0 = prefix##string ;\* br.call.sptk b0 = b6 ;\B \ add r26 = 2*8,r12 ;\ ld8 gp=[r26],8 ;\0 ld8 r8=[r26],8 ;\* ld8 r9=[r26] ;\/ add r12 = 8*8, r12 ;\prefix##label:/*& * TR_PRINT - Print to TR trace buffer *C * This macro adds an informational message to the TR trace buffer.B * T Ihe ctrstr argument has similar syntax to a "printf" statement. *E * Inputs: prefix - Text string to append to the start of labels used * by this macro. A * ctrstr - The text and optional formatting directives to be : * saved in the trace ring buffer, only the following* * directives are allowed (no width):# * %s - zero-terminated string. * %a - ascii string (pointer and length) * %d - decimal value! * %X - hexadecimal longword! * %L - hexadJecimal quadword * * Implied inputs:D * out1-out5 The corresponding values to be formatted. For the %s= * directive, this is the address of the zero-terminated@ * string. For the %a directive, this requires 2 arguments,? * first the address of the string buffer, then the length? * of the string (by value). Other directives, are passed  * by value. * Output: none * * Usage Examples: * * mov out1 = 14 * TR_PRINT(IAS1$, "This is an IAS test, index %Kd")  * * mov out1 = r3 * mov out2 = r5? * TR_PRINT(IAS2$, "This is a hex number %X and a quadword %L") * * Notes: G * o If TR tracing has not been started, no call is made to the tracingA * routine. (This attempts to minimize the performance impact.)F * o SP must be properly aligned for a call when the macro is invoked.H * o GP, R8 and R9 are preserved across the call to the tracing routine. * */(#define TR_PRINT(prefix, ctrstr) \ .global TR$ LGQ_DEBUG ;\+ .pushsection $DATA$, "wa", "progbits" ;\Bprefix##string: ;\; stringz ctrstr ;\; .popsection ;\B \6 addl r25 = @ltoff(TR$GQ_DEBUG), gp ;\% ld8 r25 = [r25] ;\% ld8 r25 = [r25] ;\* tbit.z p6 = r25, 0 ;\?(p M6) br.cond.spnt prefix##label ;\B \# mov r26 = 0xf ;\8 andcm r25 = r25, r26 ;\3 ld4 r25 = [r25] ;\2 sxt4 r25 = r25 ;\B \7 add r12 = -8*8, r12 ;\7 add r26 = 2*8,r12 N ;\4 st8 [r26] = gp,8 ;\8 st8 [r26] = r8,8 ;\2 st8 [r26] = r9 ;\B \5 ld8 r26 = [r25],8 ;\7 ld8 gp = [r25] ;\1 mov b6 = r26 ;\B \0 mov r25 = 6 O ;\8 movl out0 = prefix##string ;\* br.call.sptk b0 = b6 ;\B \ add r26 = 2*8,r12 ;\ ld8 gp=[r26],8 ;\0 ld8 r8=[r26],8 ;\* ld8 r9=[r26] ;\/ add r12 = 8*8, r12 ;\prefix##label:#endif /* _IA64_ASM_H */wwZU$/* module IA64_PAL_ROUTINES.H "X-11"*IP*************************************************************************I* *I* Copyright 2002 Compaq Computer Corporation *I* *I* COMPAQ Registered in U.S. Patent and Trademark Office. *I* *I* Confidential computer software. Valid license frQom Compaq or *I* authorized sublicensor required for possession, use or copying. *I* Consistent with FAR 12.211 and 12.212, Commercial Computer Software, *I* Computer Software Documentation, and Technical Data for Commercial *I* Items are licensed to the U.S. Government under vendor's standard *I* commercial license. *I* *I* Compaq shall not be liRable for technical or editorial errors or *I* omissions contained herein. The information in this document is *I* subject to change without notice. *I* *I**************************************************************************++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* B* This module contains the C function prototypes for the IA64 PAL 0* Sroutines that begin with the IA64_PAL$ prefix.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK T* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* U The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter nameV includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to deWnote that new_ucb_p is a pointer to a pointer to a* UCB structure.*/* 6. Mixed pointer sizes within one argumentF* If a 64-bit pointer is being passed by reference, the reference to ?* the pointer should also be 64 bits wide to avoid confusion. * For example:* * PTE_PPQ va_pte_p;* VOID_PPQ start_va_p; ** should be used instead of:** PTE_PQ *va_pte_p;* VOID_PQ *start_va_p;* * * AUTHOR:* * Karen L. Noel* * CREATION DATE:X 30-Jan-2002* * MODIFICATION HISTORY:*%* X-11 WBF Burns Fisher 21-Oct-20087* Oops...PAL_GET_PSTATE and PAL_SET_PSTATE are stacked* not static pal calls*%* X-10 WBF Burns Fisher 27-Sep-20082* Add PAL_PSTATE_INFO, GET_PSTATE, and SET_PSTATE*$* X-9 WBF Burns Fisher 19-Oct-2006* Add PAL_RSE_INFO*+* X-7,8 KLN3557 Karen L. Noel 17-Feb-2005* Add more PAL routines.*!* X-6 Andy Kuehnel 11-Aug-2003:* - Make ia64_pal$halt_info static to avoid MULDEF Ylinker* warnings.*)* X-5 KLN3266 Karen L. Noel 17-Apr-2003;* Change uint64 to unsigned __int64 for modules that don't* include ints.h.*)* X-4 KLN3264 Karen L. Noel 16-Apr-2003<* Add ia64_pal$call_stacked. Use it for ia64_pal$halt_info.*(* X-3 KLN3128 Karen L. Noel 7-Nov-2002+* Fix constant names to match conventions.*)* X-2 KLN3041 Karen L. Noel 15-Mar-2002#* Add ia64_pal$vm_summary routine.* *--*/##ifndef __IA64_PAL__ROUTINES_LOADED%#define Z__IA64_PAL__ROUTINES_LOADED 1&#pragma __required_pointer_size __save&#pragma __required_pointer_size __long/*G* Define all types that are used in the following function prototypes.*/#include #include /* 1* Function prototype of generic wrapper function */.extern unsigned __int64 ia64_pal$call_static (" PAL_RET * ret,  unsigned __int64 index, unsigned __int64 arg1, unsigned __int64 arg2, unsigned __int64 arg3)[;3extern unsigned __int64 ia64_pal$call_static_phys (" PAL_RET * ret,  unsigned __int64 index, unsigned __int64 arg1, unsigned __int64 arg2, unsigned __int64 arg3);/extern unsigned __int64 ia64_pal$call_stacked (" PAL_RET * ret,  unsigned __int64 index, unsigned __int64 arg1, unsigned __int64 arg2, unsigned __int64 arg3);4extern unsigned __int64 ia64_pal$call_stacked_phys (" PAL_RET * ret,  unsigned __i\nt64 index, unsigned __int64 arg1, unsigned __int64 arg2, unsigned __int64 arg3);/*2 * Functional prototypes of PAL wrapper functions  */%#pragma inline (ia64_pal$cache_flush)Kstatic unsigned __int64 ia64_pal$cache_flush( unsigned __int64 cache_type, unsigned __int64 operation, unsigned __int64 progress, PAL_CFLUSH * cflush){6 return (ia64_pal$call_static ((PAL_RET *)cflush,$ IA64_PAL$K_CACHE_FLUSH, cache_type,  operation,  ] progress));}$#pragma inline (ia64_pal$cache_info)Jstatic unsigned __int64 ia64_pal$cache_info(unsigned __int64 cache_level,! unsigned __int64 cache_type, PAL_CINFO * cinfo){0 return (ia64_pal$call_static ((PAL_RET *)cinfo, IA64_PAL$K_CACHE_INFO, cache_level, cache_type, 0));}$#pragma inline (ia64_pal$cache_init)Jstatic unsigned __int64 ia64_pal$cache_init(unsigned __int64 cache_level, unsigned __int64 cache_type, unsigned __int64 rest){^ PAL_RET ret;* return (ia64_pal$call_static_phys (&ret,  IA64_PAL$K_CACHE_INIT,# cache_level, cache_type, rest));})#pragma inline (ia64_pal$cache_prot_info)Ostatic unsigned __int64 ia64_pal$cache_prot_info(unsigned __int64 cache_level, unsigned __int64 cache_type, PAL_CPINFO * cpinfo){1 return (ia64_pal$call_static ((PAL_RET *)cpinfo, IA64_PAL$K_CACHE_PROT_INFO, cache_level, cache_type, 0));}$#pragma inline (ia64_pal$cache_read)Gstatic un_signed __int64 ia64_pal$cache_read (unsigned __int64 line_id, unsigned __int64 address, unsigned __int64 * data, unsigned __int64 * length, unsigned __int64 * mesi){ PAL_RET ret; unsigned __int64 pal_status;/ pal_status = ia64_pal$call_stacked_phys (&ret,/ IA64_PAL$K_CACHE_READ, line_id, address, 0); *data = ret.pal_ret$q_val1; *length = ret.pal_ret$q_val2; *mesi = ret.pal_ret$q_val3; return (pal_status);}'#pragma inline (ia64_pal$cache_summary)`Fstatic unsigned __int64 ia64_pal$cache_summary(PAL_CSUMM * pal_csumm){4 return (ia64_pal$call_static ((PAL_RET *)pal_csumm, IA64_PAL$K_CACHE_SUMMARY, 0, 0, 0));}%#pragma inline (ia64_pal$cache_write)Hstatic unsigned __int64 ia64_pal$cache_write (unsigned __int64 line_id, unsigned __int64 address,  unsigned __int64 data){ PAL_RET ret;* return (ia64_pal$call_stacked_phys (&ret, IA64_PAL$K_CACHE_WRITE, line_id, address, data));}$#pragma inline (ia64a_pal$debug_info)Jstatic unsigned __int64 ia64_pal$debug_info (PAL_DEBUG_INFO * debug_info){9 return (ia64_pal$call_static ((PAL_RET *)debug_info,$ IA64_PAL$K_DEBUG_INFO, 0, 0, 0));}%#pragma inline (ia64_pal$pstate_info)tstatic unsigned __int64 ia64_pal$pstate_info (PAL_PSTATE_INFO_RETURNS *pstate_return,PAL_PSTATE_INFO * pstate_info){< return (ia64_pal$call_static ((PAL_RET *)pstate_return,A IA64_PAL$K_PSTATE_INFO, (unsigned __int64)pstate_info, 0, 0));}"#prabgma inline (ia64_pal$rse_info)Dstatic unsigned __int64 ia64_pal$rse_info (PAL_RSE_INFO * rse_info){7 return (ia64_pal$call_static ((PAL_RET *)rse_info," IA64_PAL$K_RSE_INFO, 0, 0, 0));}$#pragma inline (ia64_pal$get_pstate)`static unsigned __int64 ia64_pal$get_pstate(unsigned __int64 *addr, unsigned __int64 infoType) { unsigned __int64 pal_status; PAL_RET ret;/ pal_status = ia64_pal$call_stacked (&ret, * IA64_PAL$K_GET_PSTATE, infoType, 0, 0); *addrc = ret.pal_ret$q_val1; return (pal_status);}$#pragma inline (ia64_pal$set_pstate)Sstatic unsigned __int64 ia64_pal$set_pstate(__int64 pstate, __int64 force_pstate) { unsigned __int64 pal_status; PAL_RET ret;/ pal_status = ia64_pal$call_stacked (&ret, 3 IA64_PAL$K_SET_PSTATE, pstate, force_pstate, 0); return (pal_status);}#pragma inline (ia64_pal$halt)Cstatic unsigned __int64 ia64_pal$halt(unsigned __int64 halt_state,* unsigned __indt64 io_detail_ptr,* unsigned __int64 * load_return){ PAL_RET ret; unsigned __int64 pal_status; . pal_status = ia64_pal$call_static_phys (&ret, IA64_PAL$K_HALT,! halt_state, io_detail_ptr, 0); if (load_return)' *load_return = ret.pal_ret$q_val1; return (pal_status);}##pragma inline (ia64_pal$halt_info)@static unsigned __int64 ia64_pal$halt_info(void * power_buffer){ PAL_RET ret;! return (ia64_pal$call_stacked ( &ret," IA6e4_PAL$K_HALT_INFO,& (unsigned __int64)power_buffer, 0, 0));}$#pragma inline (ia64_pal$halt_light)2static unsigned __int64 ia64_pal$halt_light(void){ PAL_RET ret;K return (ia64_pal$call_static (&ret, IA64_PAL$K_HALT_LIGHT, 0, 0, 0));}&#pragma inline (ia64_pal$mc_clear_log)Estatic unsigned __int64 ia64_pal$mc_clear_log(PAL_MC_CLOG * mc_clog){6 return (ia64_pal$call_static((PAL_RET *)mc_clog, & IA64_PAL$K_MC_CLEAR_LOG, 0, 0, 0));}"f#pragma inline (ia64_pal$mc_drain)0static unsigned __int64 ia64_pal$mc_drain(void){ PAL_RET ret;( return (ia64_pal$call_static(&ret, " IA64_PAL$K_MC_DRAIN, 0, 0, 0));}%#pragma inline (ia64_pal$mc_expected)Hstatic unsigned __int64 ia64_pal$mc_expected(unsigned __int64 expected, unsigned __int64 * previous){ PAL_RET ret;! unsigned __int64 pal_status;3 pal_status = ia64_pal$call_static_phys (&ret, + IA64_PAL$K_MC_EXPECTED, expected, 0, 0);$ g *previous = ret.pal_ret$q_val1; return (pal_status);}'#pragma inline (ia64_pal$mc_error_info)Mstatic unsigned __int64 ia64_pal$mc_error_info (unsigned __int64 info_index,& unsigned __int64 level_index,% unsigned __int64 type_index, PAL_MCERR * err){/ return (ia64_pal$call_static ((PAL_RET*) err,  IA64_PAL$K_MC_ERROR_INFO,) info_index, level_index, type_index));}'#pragma inline (ia64_pal$perf_mon_info)Fstatic unsigned __int64 ia64_hpal$perf_mon_info(PAL_PM_INFO *pm_info,  PAL_PM_BUFFER *pmbuf){2 return (ia64_pal$call_static ((PAL_RET *)pm_info, IA64_PAL$K_PERF_MON_INFO,# (unsigned __int64) pmbuf, 0, 0));}+#pragma inline (ia64_pal$proc_get_features)5static unsigned __int64 ia64_pal$proc_get_features (# unsigned __int64 * features_avail,# unsigned __int64 * feature_status,$ unsigned __int64 * feature_control){ PAL_RET ret; unsigned __int64 pal_status;. pal_status = ia64_pal$call_static_phyis (&ret,* IA64_PAL$K_PROC_GET_FEATURES, 0, 0, 0);& *features_avail = ret.pal_ret$q_val1;& *feature_status = ret.pal_ret$q_val2;' *feature_control = ret.pal_ret$q_val3; return (pal_status);} ##pragma inline (ia64_pal$ptce_info)?static unsigned __int64 ia64_pal$ptce_info(PAL_PTCE_INFO *info){ return (ia64_pal$call_static ($ (PAL_RET *)info,  IA64_PAL$K_PTCE_INFO, 0,0,0));}!#pragma inline (ia64_pal$vm_info)*static unsigned __int64 ia64_pal$vmj_info( unsigned __int64 tc_level, unsigned __int64 tc_type, PAL_VM_INFO * vm_info){5 return (ia64_pal$call_static((PAL_RET *)vm_info,. IA64_PAL$K_VM_INFO, tc_level, tc_type, 0));}&#pragma inline (ia64_pal$vm_page_size)Istatic unsigned __int64 ia64_pal$vm_page_size(PAL_VM_PGSIZE * vm_pgsize){8 return (ia64_pal$call_static((PAL_RET *)vm_pgsize, & IA64_PAL$K_VM_PAGE_SIZE, 0, 0, 0));}$#pragma inline (ia64_pal$vm_summary)Bstatic unsigned __int64 ia64_pakl$vm_summary(PAL_VM_SUMMARY *summ){ return (ia64_pal$call_static ( (PAL_RET *)summ, IA64_PAL$K_VM_SUMMARY, 0,0,0));}$#pragma inline (ia64_pal$mem_attrib)Kstatic unsigned __int64 ia64_pal$mem_attrib(unsigned __int64 * mem_attrib){ PAL_RET ret; unsigned __int64 pal_status;( pal_status = ia64_pal$call_static(&ret," IA64_PAL$K_MEM_ATTRIB, 0, 0, 0);" *mem_attrib = ret.pal_ret$q_val1; return (pal_status);}!#pragma inline (ia64_pal$version)+static unsigned __ilnt64 ia64_pal$version (! unsigned __int64 * min_pal_ver,% unsigned __int64 * current_pal_ver){ unsigned __int64 pal_status; PAL_RET ret;J pal_status = ia64_pal$call_static (&ret, IA64_PAL$K_VERSION, 0, 0, 0);* *min_pal_ver = ret.pal_ret$q_val1;* *current_pal_ver = ret.pal_ret$q_val2; return (pal_status);}!#pragma inline (ia64_pal$tr_read)Estatic unsigned __int64 ia64_pal$tr_read(unsigned __int64 which_tr,  unsigned __int64 tr_type,E unsimgned __int64 * return_buffer, /* 32-byte buffer - 4 quads */ PAL_TR_VALID * tr_valid){: unsigned __int64 ptr = __tpa((__int64)return_buffer);! unsigned __int64 pal_status; PAL_RET ret;3 pal_status = ia64_pal$call_stacked_phys (&ret,2 IA64_PAL$K_VM_TR_READ, which_tr, tr_type, ptr);7 tr_valid->pal_tr_valid$q_val = ret.pal_ret$q_val1; return (pal_status);}##pragma inline (ia64_pal$freq_base)Istatic unsigned __int64 ia64_pal$freq_base(unsingned __int64 * base_freq){ PAL_RET ret;! unsigned __int64 pal_status;. pal_status = ia64_pal$call_static (&ret, " IA64_PAL$K_FREQ_BASE, 0, 0, 0);% *base_freq = ret.pal_ret$q_val1; return (pal_status);}%#pragma inline (ia64_pal$freq_ratios)Gstatic unsigned __int64 ia64_pal$freq_ratios (unsigned __int64 * proc,1 unsigned __int64 * bus, unsigned __int64 * itc){ PAL_RET ret;! unsigned __int64 pal_status;. pal_status = ia64_pal$call_ostatic (&ret, $ IA64_PAL$K_FREQ_RATIOS, 0, 0, 0); *proc = ret.pal_ret$q_val1; *bus = ret.pal_ret$q_val2; *itc = ret.pal_ret$q_val3; return (pal_status);})#pragma __required_pointer_size __restore'#endif /* __IA64_PAL_ROUTINES_LOADED */wwZU#/* module IA64_SAL_ROUTINES.H "X-5"*I*************************************************************************I* *I* Copyripght 2002 Compaq Computer Corporation *I* *I* COMPAQ Registered in U.S. Patent and Trademark Office. *I* *I* Confidential computer software. Valid license from Compaq or *I* authorized sublicensor required for possession, use or copying. *I* Consistent with FAR 12.211 and 12.212, Commercial Computqer Software, *I* Computer Software Documentation, and Technical Data for Commercial *I* Items are licensed to the U.S. Government under vendor's standard *I* commercial license. *I* *I* Compaq shall not be liable for technical or editorial errors or *I* omissions contained herein. The information in this document is *I* subject to change without notirce. *I* *I**************************************************************************++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:*A* This module contains the C function prototypes for the IA64 SAL0* routines that begin with the IA64_SAL$ prefix.*** AUTHOR: Andrew Crager** CREATION DATE: 19-Aug-2002** MODIFICATION HISTORY:*Bs* X-5 TLC Tony Camuso 3-Aug-2005B* PCIe Extended Config Space support: add flag param3* for extended config space accesses.*)* X-4 KLN3560 Karen L. Noel 18-Feb-2005#* Add prototype for ESI functions.*(* X-3 KLN3534 Karen L. Noel 1-Sep-2004/* Add jacket for calling SAL physical ID info.*(* X-2 KLN3128 Karen L. Noel 7-Nov-2002* o Call exe$ar_sal_proc./* o Make ia64_sal$cache_flush simpler to call.**"* tX-1 Andrew Crager 19-Aug-2002* Initial version.**--*/##ifndef __IA64_SAL__ROUTINES_LOADED%#define __IA64_SAL__ROUTINES_LOADED 1&#pragma __required_pointer_size __save&#pragma __required_pointer_size __long#include #include 4/*** SAL jacket routine prototype for SAL_PROC. ***/5typedef SAL_RET (SAL_PROC) (unsigned __int64 func_id, unsigned __int64 arg1, unsigned __int64 arg2, unsigned __int64 arg3, unsuigned __int64 arg4, unsigned __int64 arg5, unsigned __int64 arg6, unsigned __int64 arg7);=#pragma linkage_ia64 sal_proc_linkage=(result(r8,r9,r10,r11))0#pragma use_linkage sal_proc_linkage (SAL_PROC)!extern SAL_PROC *exe$ar_sal_proc;=/*** SAL jacket routines for the various SAL_PROC calls. ***/%#pragma inline (ia64_sal$set_vectors)%static __int64 ia64_sal$set_vectors ( SAL_SV_RET *sal_ret_ptr, unsigned __int64 vec_type, unsigned __int64 physv_addr_1, unsigned __int64 gp_1, unsigned __int64 len_cs_1, unsigned __int64 phys_addr_2, unsigned __int64 gp_2, unsigned __int64 len_cs_2){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc ( IA64_SAL$K_SET_VECTORS, vec_type, phys_addr_1, gp_1, len_cs_1, phys_addr_2, gp_2, len_cs_2);5 return (((SAL_RET *)sal_ret_ptr)->sal_ret$q_status);}(#pragma inline (ia64_sal$get_state_info)Bstatic __int64 ia64_sal$get_state_info (SAL_GSI_RET *sal_wret_ptr, unsigned __int64 type, unsigned __int64 memaddr){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc ( IA64_SAL$K_GET_STATE_INFO, type, 0, memaddr, 0, 0, 0, 0);5 return (((SAL_RET *)sal_ret_ptr)->sal_ret$q_status);}-#pragma inline (ia64_sal$get_state_info_size)Hstatic __int64 ia64_sal$get_state_info_size (SAL_GSIS_RET *sal_ret_ptr, unsigned __int64 type){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc (%x IA64_SAL$K_GET_STATE_INFO_SIZE, type, 0, 0, 0, 0, 0, 0);5 return (((SAL_RET *)sal_ret_ptr)->sal_ret$q_status);}*#pragma inline (ia64_sal$clear_state_info)Dstatic __int64 ia64_sal$clear_state_info (SAL_CSI_RET *sal_ret_ptr, unsigned __int64 type){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc (" IA64_SAL$K_CLEAR_STATE_INFO, type, 0, 0, 0, 0, 0, 0);5 return (((SAL_RET *y)sal_ret_ptr)->sal_ret$q_status);}##pragma inline (ia64_sal$mc_rendez)>static __int64 ia64_sal$mc_rendez (SAL_MCR_RET *sal_ret_ptr){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc ( IA64_SAL$K_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);5 return (((SAL_RET *)sal_ret_ptr)->sal_ret$q_status);}'#pragma inline (ia64_sal$mc_set_params)Bstatic __int64 ia64_sal$mc_set_params (SAL_MCSP_RET *sal_ret_ptr," unsigned __int64 param_type,z unsigned __int64 i_or_m," unsigned __int64 i_or_m_val, unsigned __int64 time_out, unsigned __int64 mca_opt){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc ( IA64_SAL$K_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val, time_out, mca_opt, 0, 0);5 return (((SAL_RET *)sal_ret_ptr)->sal_ret$q_status);}'#pragma inline (ia64_sal$reg_phys_addr)Astatic __int64 ia64_sal$reg_phys_addr (SAL_RPA_RET *sal_ret_ptr,{# unsigned __int64 phys_entity, unsigned __int64 p_addr){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc ( IA64_SAL$K_REG_PHYS_ADDR, phys_entity, p_addr, 0, 0, 0, 0, 0);5 return (((SAL_RET *)sal_ret_ptr)->sal_ret$q_status);}%#pragma inline (ia64_sal$cache_flush)=static __int64 ia64_sal$cache_flush (unsigned __int64 i_or_d){ SAL_RET sal_ret; sal_ret = exe$ar_sal_proc ( IA64_SAL$K_CACHE_FLUSH, i_or_d,| 0,0,0,0,0,0);# return (sal_ret.sal_ret$q_status);}$#pragma inline (ia64_sal$cache_init)>static __int64 ia64_sal$cache_init (SAL_CI_RET *sal_ret_ptr){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc ( IA64_SAL$K_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);5 return (((SAL_RET *)sal_ret_ptr)->sal_ret$q_status);}&#pragma inline (ia64_sal$pci_cfg_read)Cstatic __int64 ia64_sal$pci_cfg_read (SAL_PCICR_RET *sal_ret_ptr, unsigned} __int64 addr, unsigned __int64 size,( unsigned __int64 addr_type){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc ( IA64_SAL$K_PCI_CFG_READ, addr, size, addr_type, 0, 0, 0, 0);5 return (((SAL_RET *)sal_ret_ptr)->sal_ret$q_status);}'#pragma inline (ia64_sal$pci_cfg_write)Cstatic __int64 ia64_sal$pci_cfg_write (SAL_PCICW_RET *sal_ret_ptr, unsigned __int64 addr, unsigned __int64 size, unsign~ed __int64 value,( unsigned __int64 addr_type){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc ( IA64_SAL$K_PCI_CFG_WRITE, addr, size, value, addr_type, 0, 0, 0);5 return (((SAL_RET *)sal_ret_ptr)->sal_ret$q_status);}##pragma inline (ia64_sal$freq_base)>static __int64 ia64_sal$freq_base (SAL_FB_RET *sal_ret_ptr," unsigned __int64 clock_type){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc ( IA64_SAL$K_FREQ_BASE, clock_type, 0, 0, 0, 0, 0, 0);5 return (((SAL_RET *)sal_ret_ptr)->sal_ret$q_status);}*#pragma inline (ia64_sal$physical_id_info)=static __int64 ia64_sal$physical_id_info (unsigned int *plid){ SAL_RET sal_ret; sal_ret = exe$ar_sal_proc (" IA64_SAL$K_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0);> *plid = ((SAL_PID_RET *)&sal_ret)->sal_pid_ret$w_plid;# return (sal_ret.sal_ret$q_status);}$#pragma inline (ia64_sal$update_pal)Astatic __int64 ia64_sal$update_pal (SAL_UPAL_RET *sal_ret_ptr,! unsigned __int64 param_buf,# unsigned __int64 scratch_buf,( unsigned __int64 scratch_buf_size){, *(SAL_RET *)sal_ret_ptr = exe$ar_sal_proc ( IA64_SAL$K_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size, 0, 0, 0, 0);5 return (((SAL_RET *)sal_ret_ptr)->sal_ret$q_status);}/* Extended SAL functions */typedef struct _esi_ret {# unsigned __int64 esi_ret$q_status;$ unsigned __int64 esi_ret$q_status2; } ESI_RET;Kint exe$get_esi_entry (EFI_GUID * guid_p, void ** code_va_p, void ** gp_p);ESI_RET exe$call_esi_phys ( void * code_va, void * gp, unsigned __int64 esi_func_id, unsigned __int64 arg1, unsigned __int64 arg2, unsigned __int64 arg3);0#pragma linkage_ia64 esi_linkage=(result(r8,r9))4#pragma use_linkage esi_linkage (exe$call_esi_phys))#pragma __required_pointer_size __restore'#endif /* __IA64_SAL_ROUTINES_LOADED */wwlZU/* * IDENT "X-1" *J *************************************************************************J * *J * Copyright 2002 Compaq Information Technologies Group, L.P. *J * *J * Compaq and the Compaq logo are trademarks of Compaq Information *J * Technologies Group, L.P. in the U.S. and/or other countries. *J * *J * Confidential computer software. *J * Valid license from Compaq required for possession, use or copying. *J * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, *J * Computer Software Documentation, and Technical Data for Commercial *J * Items are licensed to the U.S. Government under vendor's standard *J * commercial license. *J * *J * Compaq shall not be liable for technical or editorial errors or *J * omissions contained herein. The information is provided "as is" *J * without warranty of any kind and is subject to change without notice. *J * The warranties for Compaq products are set forth in the express  *J * warranty statements accompanying such products. Nothing herein *J * should be construed as constituting an additional warranty. *J * *J ************************************************************************* * * * FACILITY: * * [IBOOTDRIVER] IBDTAB.H  * * ABSTRACT: *> * This module contains the boot driver selection support$ * for the Itanium OpenVMS. * * Author: *J * Paul J. Rivera Creation Date: 25-Jul-2002 * * REVISION HISTORY: *G * X-1 PJR102 Paul Rivera 23-OCT-2002! * Initial check-in. * */#ifndef __IBDTAB_LOADED#define __IBDTAB_LOADED 1 !#define IBDTAB$M_SUPPORT_DOSD 0x1#define IBDTAB$M_SUPPORT_VA 0x2 struct ibdtab$r_ibdtab {F void *ibdtab$q_bdtab_base; /* Boot Driver Table Base Entry */N unsigned int ibdtab$q_boot_device; /* Boot device type */Y void *ibdtab$pl_driver_namtbl; /* Ptr to runtime driver name descriptor table */N int ibdtab$q_cpu_list; /* List of supported CPUs */N int (*ibdtab$q_qio) (); /* Driver QIO entry point */N int (*ibdtab$q_unit_init) (); /* Driver unit init entry */N int (*ibdtab$q_unit_disc) (); /* Driver unit disconnect entry */N int (*ibdtab$q_unit_reset) (); /* Driver unit reset */L int *ibdtab$q_node_number; /* Device node number */N unsigned int ibdtab$q_class_driver; /* Class driver device type */N unsigned int ibdtab$q_port_driver; /* Port driver device type */N unsigned int ibdtab$q_btdriver_name;/* PCI ID or name of the device */N unsigned int ibdtab$q_bdtab_size; /* Size of BDTAB */ __union {N unsigned int ibdtab$q_flags; /* Driver flags defined as  follows: */N __struct { /* ... */c unsigned ibdtab$v_support_dosd : 1; /* Driver supports dump file off system disk */` unsigned ibdtab$v_support_va : 1; /* Driver supports virtual addressing mode. */* unsigned ibdtab$v_fill_0_ : 6;# } ibdtab$r_flag_fields;! } ibdtab$r_flags_overlay;N/* */B/* Define the LAN driver transfer vectors. */N/* */\ int ibdtab$a_init_adapter; /* Address of the adapter initialization routine. */^ int ibdtab$a_reinit_adapter; /* Address of the adapter reinitialization routine. */b int ibdtab$a_init_poll; /* Address of the initialization complete poll routine. */W int ibdtab$a_xmt_initiate; /* Address of the transmit initiate routine. */\ int ibdtab$a_xmt_poll; /* Address of the transmit complete poll routine. */[ int ibdtab$a_rcv_poll; /* Address of the receive complete poll routine. */\ int ibdtab$a_rcv_release_buffer; /* Address of the release receive buffer routine. */N/* */B/* Define the LAN adapter characteristics. */N/*  */N unsigned int ibdtab$l_lan_hdr_size; /* Minimum LAN header size. */j unsigned int ibdtab$l_min_xmt_size; /* Minimum transmit size (does not include minimum LAN header). */j unsigned int ibdtab$l_max_xmt_size; /* Maximum transmit size (does not include minimum LAN header). */N/* */B/* Define the device specific characteristics. */N/*  */^ unsigned int ibdtab$l_dma_map_regs_needed; /* Required number of DMA mapping registers. */n unsigned int ibdtab$l_initialization_time; /* Time in seconds required for selftest and initialization. */N/* */B/* Define ATA and ATAPI IDE characteristics. */N/* */U unsigned int ibdtab$l_ata_chan_pri; /* 0: Primary Channel 1: Secondary Channel */P unsigned int ibdtab$l_ata_drive_master; /* 0: Master Drive 1: Slave Drive */N unsigned int ibdtab$l_ata_lun; /* ATA Logical Unit Number */N unsigned int ibdtab$l_ata_pio; /* PIO mode setting */N unsigned int ibdtab$l_ata_dma; /* DMA mode setting */N/* */B/* Define SCSI characteristics.  */N/* */N unsigned int ibdtab$l_scsi_id; /* Target SCSI ID */N unsigned int ibdtab$l_scsi_lun; /* Target SCSI LUN */; int *ibdtab$q_scsiDesc; /* SCSI Descriptor */ N/* */N/* Define Fibre Channel characteristics. */N/*  */N unsigned int ibdtab$l_fc_wwn; /* Target SCSI ID */N unsigned int ibdtab$l_fc_lun; /* Target SCSI LUN */  } ; #if !defined(__VAXC)<#define ibdtab$q_flags ibdtab$r_flags_overlay.ibdtab$q_flags_#define ibdtab$v_support_dosd ibdtab$r_flags_overlay.ibdtab$r_flag_fields.ibdtab$v_support_dosd[#define ibdtab$v_support_va ibdtab$r_flags_overlay.ibdtab$r_flag_fields.ibdtab $v_support_va"#endif /* #if !defined(__VAXC) */  struct namtbl$r_driver_namtbl { __union {N __struct { /* only for bliss32 drivers */g unsigned int namtbl$l_designator_l; /* Counted string. ASCII device designator (eg. DK) */N unsigned int namtbl$l_designator_h; /* */% } namtbl$r_vector_fields;_ char namtbl$t_designator [8]; /* Counted string. ASCII device designator (eg. D K) */& } namtbl$r_designator_overlay;N __union { /* Driver flags */% __int64 namtbl$iq_name_flags;+ unsigned int namtbl$l_name_flags_l;+ unsigned int namtbl$l_name_flags_h;& } namtbl$r_name_flags_overlay; __union {+ __int64 namtbl$iq_driver_name_desc; __struct {4 unsigned short int namtbl$w_desc_length;3 unsigned short int namtbl$w_desc_flags;% vo id *namtbl$pl_desc_ptr;# } namtbl$r_desc_fields;% } namtbl$r_name_desc_overlay; } ; #if !defined(__VAXC)f#define namtbl$l_designator_l namtbl$r_designator_overlay.namtbl$r_vector_fields.namtbl$l_designator_lf#define namtbl$l_designator_h namtbl$r_designator_overlay.namtbl$r_vector_fields.namtbl$l_designator_hK#define namtbl$t_designator namtbl$r_designator_overlay.namtbl$t_designatorM#define namtbl$iq_name_flags namtbl$r_name_flags_overlay.namtbl$iq_name_flagsO#define namtbl$l_name_flags_l namtbl$r_name_flags_overlay.namtbl$l_name_flags_lO#define namtbl$l_name_flags_h namtbl$r_name_flags_overlay.namtbl$l_name_flags_hX#define namtbl$iq_driver_name_desc namtbl$r_name_desc_overlay.namtbl$iq_driver_name_desca#define namtbl$w_desc_length namtbl$r_name_desc_overlay.namtbl$r_desc_fields.namtbl$w_desc_length_#define namtbl$w_desc_flags namtbl$r_name_desc_overlay.namtbl$r_desc_fields.namtbl$w_desc_flags]#define namtbl$pl_desc_ptr namtbl$r_name_desc_overlay.namtbl$r_desc_fields.namtbl$pl_desc_ptr"#endif /* #if !defined(__VAXC) */ !#define NAME_FLAGS$M_HARDWARE 0x1 #define NAME_FLAGS$M_SYS_DEV 0x2#define NAME_FLAGS$M_REMOTE 0x4##define NAME_FLAGS$M_DEF_PREFIX 0x8%#define NAME_FLAGS$M_NO_CTRL_LTR 0x10%#define NAME_FLAGS$M_HW_CTRL_LTR 0x20$#define NAME_FLAGS$M_CTRL_LTR_A 0x40 #define NAME_FLAGS$M_UNIT_0 0x80%#define NAME_FLAGS$M_CREATE_DEV 0x100 struct name_flags$r_name_flags {l unsigned name_flags$v_hardware : 1; /* Device requires CSR, vector and controller letter assignment, */N/* clear => no hardware. */s unsigned name_flags$v_sys_dev : 1; /* This is the driver for the system device, clear => not system device. */k unsigned name_flags$v_remote : 1; /* Use the SCS node name in the BTADP, clear => no node$ prefix. */u unsigned name_flags$v_def_prefix : 1; /* Use default name descriptor prefix, clear => use BTADP driver prefix. */j unsigned name_flags$v_no_ctrl_ltr : 1; /* Add controller letter, clear => ignore controller letter. */w unsigned name_flags$v_hw_ctrl_ltr : 1; /* Copy hardware controller letter to BTADP, clear => ignore HW ctrl ltr. */p unsigned name_flags$v_ctrl_ltr_a : 1; /* Use "A", clear => use (computed) controller letter in the BTADP. */r unsigned name_flags$v_unit_0 : 1; /* Use 0 as the unit number, clear => use the unit number in the BTADP. */l unsigned name_flags$v_create_dev : 1; /* Must create a new device, clear => device can already exist. */& unsigned name_flags$v_fill_1_ : 7; } ; #endif /* __IBDTAB_LOADED */ ww0ZU/* * IDENT X-2A1 * * Copyright (C) 1996 by9 * Digital Equipment Corporation, Maynard, Massachusetts. * All rights reserved. *H * This software is furnished under a license and may be used and copiedH * only in accordance of the terms of such license and with theH * inclusion of the above copyright notice. This software or any otherH * copies thereof may not be provided or otherwise made available to anyH * other person. No title to and ownership of the software is hereby * transferred. *H * The information in this software is subject to change without noticeH * and should not be construed as a commitment by Digital Equipment * Corporation. *H * Digital assumes no responsibility for the use or reliability of its: * software on equipment which is not supplied by Digital. * * * Abstract: *A * This file contains various definitions for use with IIC device * driver (IIDRIVER). * * Authors: * * Paul A. Jacobi, May 1997 *  * Modified by: *4 * X-2A1 PAJ1012 Paul A. Jacobi 01-Sep-1998= * Add definitions for Goldrush server management registers. *2 * X-2 PAJ0942 Paul A. Jacobi 11-Jun-1997' * Define IIC_R_PSR_TEMP_MASK bitmask. * */#ifndef __IIC_IOCTL_LOADED#define __IIC_IOCTL_LOADED 1#endif/*+ * The following IOCTL codes are supported: * */( /* Read functions */##define II_IOCTL_READ_TEMPERATURE 1$#define II_IOCTL_READ_POWER_STATUS 2"#define II_IOCTL_READ_FAN_STATUS 3!#define II_IOCTL_READ_OCP_TEXT 45/* All write function codes must be less than zero */##define II_IOCTL_WRITE_OCP_TEXT -1*/* Define buffer size for each function */%#define II_LENGTH_READ_TEMPERATURE 16&#define II_LENGTH_READ_POWER_STATUS 16$#define II_LENGTH_READ_FAN_STATUS 16##define II_LENGTH_READ_OCP_TEXT 16##define II_LENGTH_WRITE_OCP_TEXT 16%#define IIDRIVER_MAX_BUFFER_SIZE 256/*0 * Known IIC node addresses for Sable and Mikasa */#define IIC_CONT 0xB6#define IIC_OCP0 0x40#define IIC_OCP1 0x42/*J * Known IIC node addresses for Sable. Note CPU3 and MEM1 share the same 5 * physical slot and have the same IIC node address.  */#define IIC_MEM0 0xA0#define IIC_MEM1 0xA2#define IIC_MEM2 0xA4#define IIC_MEM3 0xA6#define IIC_CPU0 0xA8#define IIC_CPU1 0xAA#define IIC_CPU2 0xAE#define IIC_CPU3 0xA2#define IIC_IO 0xAC#define IIC_PSC 0x46$/* IIC node addresses for Rawhide */-#define IIC_R_GCD 0xA0 // GCD module.#define IIC_R_MB 0xA2 // Motherboard(#define IIC_R_CPU0 0xA4 // CPU 0(#define IIC_R_CPU1 0xA6 // CPU 1*#define IIC_R_H0 0xA8 // Horse 0+#define IIC_R_S0 0xAA // Saddle 00#define IIC_R_CPU2 0xAC // CPU 2/Horse 11#define IIC_ R_CPU3 0xAE // CPU 3/Saddle 11#define IIC_R_OCP0 0x40 // OCP controller1#define IIC_R_OCP1 0x42 // OCP controller0#define IIC_R_MEM0 0x48 // Memory pair 00#define IIC_R_MEM1 0x4A // Memory pair 10#define IIC_R_MEM2 0x4C // Memory pair 20#define IIC_R_MEM3 0x4E // Memory pair 3H#define IIC_R_FFR 0x70 // Failing fan and power supply registerJ#define IIC_R_PSR 0x72 // Fan/Temp/Power Sensor function registerE#define II C_R_FFR_PS0_MASK 0x80 /* Power supply 0, 0=present, 1=NA */E#define IIC_R_FFR_PS1_MASK 0x10 /* Power supply 1, 0=present, 1=NA */E#define IIC_R_FFR_PS2_MASK 0x40 /* Power supply 2, 0=present, 1=NA */C#define IIC_R_PSR_PS0_MASK 0x20 /* Power supply 0, 0=good, 1=bad */C#define IIC_R_PSR_PS1_MASK 0x40 /* Power supply 1, 0=good, 1=bad */C#define IIC_R_PSR_PS2_MASK 0x80 /* Power supply 2, 0=good, 1=bad */G#define IIC_R_PSR_TEMP_MASK 0x01 /* Temperature warning status, 1=OK */@#define IIC_ R_PSR_SYSFAN_MASK 0x02 /* System fan status, 1=OK */=#define IIC_R_PSR_CPUFAN_MASK 0x08 /* CPU fan status, 1=OK *//* Define KCSRM addresses */5#define IIC_KCRSM_TEMP 0x9E /* Temperature Sensor */4#define IIC_KCRSM_NVRAM0 0xC0 /* NVRAM location 0 */4#define IIC_KCRSM_NVRAM1 0xC2 /* NVRAM location 1 */4#define IIC_KCRSM_NVRAM2 0xC4 /* NVRAM location 2 */4#define IIC_KCRSM_NVRAM3 0xC6 /* NVRAM location 3 */4#define IIC_KCRSM_NVRAM4 0xC8 /* NVRAM location 4 */4#define IIC_KCRSM_NVRAM5 0xC A /* NVRAM location 5 */4#define IIC_KCRSM_NVRAM6 0xCC /* NVRAM location 6 */4#define IIC_KCRSM_NVRAM7 0xCE /* NVRAM location 7 */"/* IIC node addresses for Goldrush */.#define IIC_G_MB 0xA2 // Motherboard(#define IIC_G_CPU0 0xA4 // CPU 0(#define IIC_G_CPU1 0xA6 // CPU 11#define IIC_G_OCP0 0x40 // OCP controller1#define IIC_G_OCP1 0x42 // OCP controller0#define IIC_G_MEM0 0x48 // Memory pair 00#define IIC_G_MEM1 0x4A // Memory pair 10#define IIC_G_MEM2 0x4C // Memory pair 20#define IIC_G_MEM3 0x4E // Memory pair 3H#define IIC_G_FFR 0x70 // Failing fan and power supply registerJ#define IIC_G_PSR 0x72 // Fan/Temp/Power Sensor function registerE#define IIC_G_FFR_PS0_MASK 0x80 /* Power supply 0, 0=present, 1=NA */H#define IIC_G_FFR_PS1FT_MASK 0x10 /* PS1 or fan tray, 0=present, 1=NA */G#define IIC_G_PSR_TEMP_MASK 0x01 /* Temperature warning status, 1=OK */@#define IIC_G_PSR_SYSFAN _MASK 0x02 /* System fan status, 1=OK */=#define IIC_G_PSR_CPUFAN_MASK 0x08 /* CPU fan status, 1=OK */<#define IIC_G_PSR_FT_MASK 0x10 /* Fan Tray, 0=good, 1=bad */C#define IIC_G_PSR_PS0_MASK 0x20 /* Power supply 0, 0=good, 1=bad */C#define IIC_G_PSR_PS1_MASK 0x40 /* Power supply 1, 0=good, 1=bad */ww@ZUO/* ************************************************************************* */O/* * * */O/* * HPE CONFIDENTIAL. This software is confidential proprietary software * */O/* * licensed by Hewlett Packard Enterprise Development, LP, and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without the * */O/* * prior written permission of HPE. * */O/* * Copyright 2021 Hewlett Packard Enterprise Development, LP * */O/* * * */O/* * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential * */O/* * proprietary software licensed by VMS Software, Inc., and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without * */O/* * the prior written permission of VMS Software, Inc. * */O/* * Copyright 2021 VMS Software, Inc. * */O/* * * */O/* ************************************************************************* *//**++ * FACILITY:** VMS Executive (LIB)* * ABSTRACT:*K* This header file will setup initialization/unload routines for execlets.M* Before including this header file, the programmer needs to #define symbolsL* for those routines to be defined. The good news is that you can setup allL* your initialization and unload routines in one swell foop. You can defineM* multiple symbols and then just #include this file to do the set up. This isM* different from how the setup works from MACRO or BLISS, where a nice macroK* takes care of ALL of the ugly stuff. In C, you need to get ugly yourselfL* (yes, this is supposed to be an improvement - Guess again!). Fortunately,* that's easy for most of us. *K* This include file has been setup so that multiple inclusions won't causeO* problems. It will still work properly. However, the way you use this includeM* file DOES matter. It can ONLY be invoked from the outer most scope of yourL* C module, and that includes outside of main{}. You must also have already0* declared the initialization/unload routines. *N* This include file specifies the following psect option attributes that mustG* not be overridden in your link option file (DECC always sets MOD for* psects with initial data):*'* For EXEC$INIT_000 and EXEC$INIT_001:*0* LONG,PIC,CON,REL,GBL,NOSHR,EXE,NOWRT,NOVEC,MOD*%* For EXEC$UNL_000 and EXEC$UNL_001:*0* OCTA,PIC,CON,REL,GBL,NOSHR,NOEXE,WRT,NOVEC,MOD*K* The following examples show what to do in your C execlet to emulate what%* you used to do in MACRO and BLISS:*I* To setup a single, priority 0 (the MACRO/BLISS default) initialization * routine:** execlet_init_rtn()* { }*+* #define INIT000_ROUTINE execlet_init_rtn* #include * * main()* { }*O* To setup a priority 1 initialization routine and priority 0 (the MACRO/BLISS* default) unload routine:** execlet_init_rtn()* { }* execlet_unload_rtn()* { }*+* #define INIT001_ROUTINE execlet_init_rtn,* #define UNL000_ROUTINE execlet_unload_rtn* #include * * main()* { }* * AUTHOR:** Steve DiPirro*"* CREATION DATE: 07-Jan-1993** MODIFICATION HISTORY:*'* X-8 CEG0982 Clair Grant 19-Apr-2021!* Make exec$init_000, _001 NOEXE*'* X-7 CEG0972 Clair Grant 28-Mar-2021(* Make exec$init_000, _001 RD,WRT,NOEXE*'* X-6 CEG0960 Clair Grant 28-Mar-2021* More psect fixing.*'* X-5 CEG0957 Clair Grant 26-Mar-20210* Fix WRT,EXE psect definitions. VSI copyright.* VDE version sync.*!* X-3 Andy Kuehnel 22-Jul-19985* - Allow multiple modules to specify init routines.6* - Specify the psect options; we are finally using a(* compiler that allows us to do that.*%* X-2 SDD Steve DiPirro 06-May-19967* Make sure required pointer size explicitly declared.**--*/ /*I We want to allow multiple inclusions of this header file. So no need to do the setup more than once.*/#ifndef __INIT_RTN_SETUP#define __INIT_RTN_SETUP 1#ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save'#pragma __required_pointer_size __short#endif/*p Some compilers warn if an array is allocated on too small an alignment. We must allocate on an exact alignmentR for the init processing to work, so we must do it this way. Disable the warning.*/#pragma message saves#pragma message disable UNKMSGID /* This allows the next one to work even on compilers where it is not supported*/##pragma message disable ALIGNNOTSTDtypedef struct{ int (*init_rtn)(); long second_long;} INIT_RTN_VEC;#endif#define ssxconcat(a,b) a##b$#define ssconcat(a,b) ssxconcat(a,b)/*H The setup is complete. For each routine symbol which has been defined,= setup the vector in the appropriate PSECT for that routine.*/#ifdef INIT0 01_ROUTINE#pragma extern_model save ]#pragma extern_model strict_refdef "EXEC$INIT_001" long,pic,con,rel,gbl,noshr,noexe,wrt,novecCINIT_RTN_VEC ssconcat(INIVEC$,INIT001_ROUTINE)={INIT001_ROUTINE,0};#pragma extern_model restore#undef INIT001_ROUTINE#endif#ifdef INIT000_ROUTINE#pragma extern_model save ]#pragma extern_model strict_refdef "EXEC$INIT_000" long,pic,con,rel,gbl,noshr,noexe,wrt,novecCINIT_RTN_VEC ssconcat(INIVEC$,INIT000_ROUTINE)={INIT000_ROUTINE,0};#pragma extern_model restore#undef INIT000_ROUTINE#endif#ifdef UNL001_ROUTINE#pragma extern_model save \#pragma extern_model strict_refdef "EXEC$UNL_001" octa,pic,con,rel,gbl,noshr,noexe,wrt,novecAINIT_RTN_VEC ssconcat(INIVEC$,UNL001_ROUTINE)={UNL001_ROUTINE,0};#pragma extern_model restore#undef UNL001_ROUTINE#endif#ifdef UNL000_ROUTINE#pragma extern_model save \#pragma extern_model strict_refdef "EXEC$UNL_000" octa,pic,con,rel,gbl,noshr,noexe,wrt,novecAINIT_RTN_VEC ssconcat(INIVEC$,UNL000_ROUTINE)={UNL000_ROUTINE,0};#pragma extern_model restore#undef UNL000_ROUTINE#endif#pragma message restore#ifdef __INITIAL_POINTER_SIZE)#pragma __required_pointer_size __restore#endifwwp}ZU/** MODULE: IOC_ROUTINES.H** VERSION: X-41*L// *************************************************************************L// * *L// * HPE CONFIDENTIAL. This software is confidential proprietary software *L// * licensed by Hewlett Packard Enterprise Development, LP, and is not *L// * authorized to be used, duplicated or disclosed to anyone without the *L// * prior written permission of HPE. *L// * Copyright 2016 Hewlett Packard Enterprise Development, LP *L// * *L// * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *L// * proprietary  software licensed by VMS Software, Inc., and is not *L// * authorized to be used, duplicated or disclosed to anyone without *L// * the prior written permission of VMS Software, Inc. *L// * Copyright 2018-2023 VMS Software, Inc. *L// * *L// ****************************************************************************++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:*C* This module contains the C function prototypes for the VMS systemB* routines that begin with the IOC$ and IOC_STD$ prefixes and have* a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the pres ence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofI* most functions and is the type for most integers passed by value.I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesO* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB.=* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.*/* 6. Mixed pointer sizes within one argumentE* If a 64-bit pointer is being passed by reference, the reference to=* the pointer should also be 64 bits wide to avoid confusion.* For example:** PTE_PPQ va_pte_p;* VOID_PPQ start_va_p;** should be used instead of:** PTE_PQ *va_pte_p;* VOID_PQ *start_va_p;** * AUTHOR:** Leonard S. Szubowicz** CREATION DATE: 28-May-1993** MODIFICATION HISTORY:*)* X-41 GHJ Gregory H. Jordan 24-Jul-2023D* Make all DIOBM references occur under the VMS$SVAPTE conditional.*(* X-39 MJM Michael Moroney 10-Jul-2022:* Add routines IOC$xxxx_IOBD as part of conversion of all5* DIOBD references to IOBD. Remove DIOBD references.*"* X-38 RCL Rick Lord  22-OCT-20188* Add IOC$FIRST_EXTENT, IOC$NEXT_SEGMENT, IOC$MOVE_DATA8* prototypes; delete IOC$GET_EXTENT_INFO prototype; add8* #defines for ioc$move_to_user and ioc$move_from_user,9* which invoke IOC$MOVE_DATA with a direction parameter.*"* X-37 RCL Rick Lord 27-Aug-2018&* Add prototype for ioc$fill_iobd_pte*"* X-36 RCL Rick Lord 26-Mar-20181* a) Add #include of diobddef for new prototypes?* b) Add upper case constants and prototypes for the following1* routines, for NOSVAPTE development on IA64:* - ioc$create_diobd* - ioc$fill_diobd* - ioc$release_diobd* - ioc$get_extent_info*(* X-35 MJM Michael Moroney 07-Oct-20168* Make ioc_std$qnxtseg1 vbn parameter uint64 (quadword)*,* X-34 RAB0202 Robert A. Brooks 01-Sep-2016* Add ioc_std$validate_ucb.*,* X-33 RAB0199 Robert A. Brooks 17-Aug-2016#* Add ioc_std$get_freeblock_count.*1* X-32 JJF0379 J. Jeffery Friedrichs 20-Jun-2008* Back out X-31*1* X-31 JJF0361  J. Jeffery Friedrichs 30-Nov-20073* Change the parameter for are_bitmaps_active_ipl0*/* X-30 GHJ Gregory H. Jordan 3-Jan-20079* Remove the temporary definition of VMS$PFNBITS_32 and ?* uncomment the include of VMS$DEFS where the symbol is really * defined.*C* X-29 TLC Tony Camuso 22-Jun-2006<* ioc$nod_data(), changed to variable argument list.*$* X-28 SCS Sue Sommer 23-Sept-2005>* Add 3 new routines in support of Active-Active controllers:;* ioc$get_targ_port_grp_num, ioc$get_asym_access_state and* ioc$reverse_endian.*)* X-27 DP Dave Prizer 14-Oct-2004** Rename ioc_std$fibre_channel_connect to4* ioc_std$fc_global_connect. This was necessary to6* allow older versions (pre-WTID) of the FibreChannel6* drivers to co-exist with newer versions (post-WTID)* of the SYS facility.*+* X-26 JHS0034 John H. Shortt 04-May-2004#* Add ioc_std$ignore_local_bitmaps*+* X-25 RAB089 Robert A. Brooks 02-Mar-2004* Folds from V73-1R-HBMM . . .*5* X-14A30A2 LSS0459 Leonard S. Szubowicz 29-Sep-2003=* HBMM: Avoid including WBMDEF.H and the resultant Catch-22.<* WBMDEF.H requires the __NEW_STARLET versions of LKSBDEF.H>* and ILEDEF.H. But some modules that include IOC_ROUTINES.H<* are written to the "old starlet" versions of LKSBDEF.H or * ILEDEF.H.*0* X-14A30A1 JHS0009 John H. Shortt 24-Sep-2003** Add the following prototypes from HBMM:* ioc_std$are_bitmaps_active#* ioc_std$are_bitmaps_active_ipl0* ioc_std$zero_local_bitmap?* Remove include for iledef.h since it has been added wbmdef.h:* and wbmdef.h is in here. The issue is that new_starlet+* needs to be done for lksbdef and iledef.**(* X-24 Clair Grant 19-Feb-20046* Add vms$defs.h but with a temporary definition here)* until the build mechanism is in place.*3* X-23 Clair Grant Valentine's Day-Feb-20042* Conditionalize ioc_std$ptetopfn for 32-bit PFNs*+* X-22 DEE0871 David E. Eiche 10-Feb-2004#* Add ioc$pte_to_pfn_64 prototype.*+* X-21 DEE0833 David E. Eiche 26-Aug-2003 * Add ioc$unload_map prototype.*'* X-20 ABP Anu Pant 06-May-20032* Change user_param of ioc_std$devconfig_register* from int to int64.*'* X-19 ABP Anu Pant 29-Apr-2003.* Add prototye for ioc_std$devconfig_cbk_iodb*'* X-18 ABP Anu Pant 27-Mar-20033* Add prototype for ioc_std$devconfig_register and * ioc_std$devconfig_deregister.*'* X-17 ABP Anu Pant 24-Jan-20035* Add prototype for quiet mount verification related$* routine, ioc_std$sndopc_mvsupmsg.*'* X-16 ABP Anu Pant 09-Jan-20034* Add prototype for ioc_std$establish_ddt_altstart,>* ioc_std$establish_ddt_cancel, ioc_std$establish_ddt_mntver,<* ioc_std$establish_ddt_start, ioc_std$ddt_start_intercept,#* ioc_std$ddt_mntver_intercept and"* ioc_std$ddt_altstart_intercept.*,* X-14A32 OH0033 Oliver Hellwig 3-May-20 02?* The prototype for ioc_std$fibre_channel_connect=* needs a forward reference for PCTX since this=* def module has not yet been checked into LIB.*-* X-14A31 OH0031 Oliver Hellwig 26-Apr-2002.* Add proto for ioc_std$fibre_channel_connect*.* X-14A30 JEM003 John E. Malmberg 09-Oct-20014* Added prototype for ioc$get_rpt_dev_udid. Parses3* SCSI Report Device Identifier buffer for a UDID.*3* X-14A29 LSS0413 Leonard S. Szubowicz 23-J an-2001* Fold in X-14A22A2.;* Part of the fix for CLD 70-3-4160: Provide a method thatA* allows both Multipath and HSM to intercept the DDT$PS_CANCEL_2=* driver entry point in a compatible fashion. Add prototype0* for the IOC_STD$DDT_CANCEL_INTERCEPT routine.*=* X-14A28 OH Oliver Hellwig 22-Aug-2000=* Add Prototype for ioc_std$binwwid_to_ascwwid.*'* X-14A27 TJP Tom Provost 13-Jul-2000.* Add prototypes for ioc_std$initiate_lck_rel* 3* X-14A26 LSS0406 Leonard S. Szubowicz 10-Feb-2000?* Part of the fix for CLDs 70-3-2729 and 70-3-2599: MultipathA* internal I/O that was sent to a UCB by calling EXE_STD$INSIOQCC* would increment UCB$L_QLEN but never decrement it on completion.5* Add prototype for routine IOC_STD$INITIATE_NEW_IO.*&* X-14A25 SCS Sue Sommer 09-Feb-20006* Add prototypes for ioc_std$update_dev_wwid_list and1* ioc_std$ascwwid_to_binwwid. Update copyright.*%* X-14A24 TGS Tom Speer 05-Aug-1999%* Add prototype for IOC_STD$HWM_END.*C* X-14A23 SSL Steven S. Lim 13-May-19997* Add prototype for IOC_STD$REQCOM_LOCAL.*,* X-14A22 JMB057 James M. Blue 01-Oct-1998,* Add interface to ioc_std$errcnt_value and* ioc_std$opcnt_value.*C* X-14A21 GP Genady Perchenko 29-Jul-19988* Add interface to ioc_std$q_internal_irp.*,* X-14A20 JMB027 James M. Blue 17-Jul-1998** Correct ioc$sndopcfao definition error.*)* X-14A19 JMB James M. Blue 14-Jul-1998?* Add interface routines to generate a dynamic FAO message and* send it to OPCOM.*-* X-14A18 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*(* X-14A17 SCS Sue Sommer 2-Jun-1998"* Fix prototype for ioc$get_udid.*+* X-14A16 RTS092 Bob Silver 21-May-1998C* Fix WWID, SN_WWID references that  only worked for __NEW_STARLET.*+* X-14A15 RTS080 Bob Silver 21-May-1998<* Add prototypes for ioc$get_udid, ioc$get_page80_wwid, and2* ioc$get_page83_wwid routines for fibre channel.*(* X-14A14 SCS Sue Sommer 6-Jan-1998;* Add prototype for SCSI class/port driver connect routine* ioc$scsipath_connect.*+* X-14A13 RTS030 Bob Silver 02-Dec-1997@* - Move macros to lowercase names of routines in READ_CONFIG.H@* from this module into READ_CONFIG.H. This was done as part9* of changes to implement fibre channel configuration.*4* X-14A12 LSS0371 Leonard S. Szubowicz 3-Apr-1997&* Fix prototype for ioc$allocate_ccb.*5* X-14A11 PAJ0918 Paul A. Jacobi 16-Jan-1997=* Define IOC_STD$GETSYI_CPU_SPECIFIC routine to fetch GETSYI+* item codes from system specific routine.*+* X-14A10 FGK Fred Kleinsorge 17-Oct-1996;* Back out the routines for foreign_boot and read_config."* They are not in the base image.*** X-14A9 FGK Fred Kleinsorge 30-Jul-19965* Fix informational by removing reference to private#* routine in foreign_boot_support.*** X-14A8 FGK Fred Kleinsorge 25-Jul-1996'* Add FOREIGN_BOOT_SUPPORT prototypes.*#* X-14A7 Susan Lewis 06-Jun-19961* Modify interface to ioc$node_function to allow4* an optional cpu mask argument. Adjust edit number* to match VDE.*** X-14A5 FGK Fred Kleinsorge 02-Apr-19962* Add read_config prototypes. Fix broken edit by* adding BUSARRAYDEF*/* X-14A3 NYK619 Nitin Y. Karkhanis 22-Mar-19969* Declare descriptor as a long pointer to void (VOID_PQ)<* for IOC_STD$SEARCH, IOC_STD$SEARCHALL, IOC_STD$SEARCHDEV,* and IOC_STD$TRANDEVNAM.*,* X-14A2 DEE0219 David E. Eiche 1-Feb-1996;* Add an optional argument to the IOC_STD$LINK_UCB routine;* so that when an existing UCB is found with the same unit:* number as the formative UCB we're trying to link in, we(* can return its address to the caller.*/* X-14A1 JPJ James P. Janetos 07-Aug-1995A* Add prototypes for PCI configuration space accessF* routines IOC$READ_PCI_CONFIG and IOC$WRITE_PCI_CONFIG.*1* X-14 LSS0348 Leonard S. Szubowicz 13-Jun-1995B* 64-bits: Add resource wait flag parameter to IOC_STD$FILL_DIOBM* and IOC_STD$CREATE_DIOBM.*0* X-13 LSS0320 Leonard S. Szubowicz 15-Feb-1995A* 64-Bit Virtual Addressing: Revise edit X-10 to stick to 32-bitA* pointers if using a compiler that doesn't support 64-bit ones.*3* X-11 WDB64B3 Walter D. Blaschuk, Jr. 9-Feb-1995/* 64-Bit Virtual Addressing/VA2PA changes: Add* IOC_STD$SVAPTE_IN_BUF*0* X-10 LSS0319 Leonard S. Szubowicz 7-Feb-1995:* 64-Bit Virtual Addressing: Add IOC_STD$VA_TO_PA, 64-bit6* pointers on IOC_STD$PTETOPFN and IOC_STD$SIMREQCOM.*/* X-9 LSS0314 Leonard S. Szubowicz 12-Jan-1995@* Add function prototypes for DIOBM routines. See "Chapter 20:?* QIO and Device Drivers" in DOCD$:[EVMS.CMS_64B]DS-64BITS.PS.*1* X-8 JCH703  John C. Hallyburton, Jr. 5-Dec-19940* Add function prototype for IOC_STD$CHECK_HWM.=* Change IOC_STD$MAPVBLK to use unsigned VBN/LBN/bytecounts.*/* X-7 LSS0313 Leonard S. Szubowicz 2-Nov-1994=* Add function prototype for new IOC$SETUP_UCB_DIPL routine.-* See STAR::EVMS_IO note 378.13 for details.*,* X-6 JPJ James P. Janetos 19-Jan-1994C* Change iohandle to pointer to uint64 in ioc$map_io,<* ioc$unmap_io, ioc$read_io, ioc$write_io, andD*  ioc$cram_cmd. Change read and write data to pointer=* to void in both ioc$read_io and ioc$write_io.*,* X-5 JPJ James P. Janetos 22-Dec-1993?* Include ptedef. Add ioc$read_io, ioc$write_io,<* ioc$map_io, ioc$unmap_io, ioc$alloc_cnt_res,A* ioc$init_crctx, ioc$init_cram, ioc$alloc_adp, andB* ioc$add_adp. Fix prototypes for ioc_std$ptetopfn,@* ioc$cram_cmd, ioc$load_map, and ioc$alloc_crctx.*+* X-4 DEE0203 David E. Eiche 01-Nov-19935* Move the driver table initialization prototypes to* vms_drivers.h.*/* X-3 LSS0286 Leonard S. Szubowicz 30-Aug-1993?* Add the definition of DDT, DPT, and FDT types which are used>* by the driver table initialization prototypes added by X-2.*+* X-2 DEE0188 David E. Eiche 19-Aug-19939* Correct CCB parameter in ioc$alloc_ccb prototype. Add.* prototypes for driver table initialization.*0* X-1 LSS0279 Leonard S. Szubowicz 28-May-1993* Initial version.**--*/#ifndef __IOC_ROUTINES_LOADED#define __IOC_ROUTINES_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define all types that are used in the following function prototypes.*/#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include 1struct _wbmh; /* Write BitMap Handle */'struct _wbmb; /* Write Bitmap Block *//*> * When pctxdef is checked in and included above, this forward+ * declaration will no longer be necessary. */typedef struct _pctx PCTX;/*P  VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/3#define ioc$add_adp IOC$ADD_ADP4#define ioc$add_device_type IOC$ADD_DEVICE_TYPE.#define ioc$allocate_ccb IOC$ALLOCATE_CCB0#define ioc$allocate_cram IOC$ALLOCATE_CRAM5#define ioc$alloc_adp IOC$ALLOC_ADP9#define ioc$ alloc_cnt_res IOC$ALLOC_CNT_RES*#define ioc$alloc_crab IOC$ALLOC_CRAB,#define ioc$alloc_crctx IOC$ALLOC_CRCTX,#define ioc_std$altreqcom IOC_STD$ALTREQCOMB#define ioc_std$are_bitmaps_active IOC_STD$ARE_BITMAPS_ACTIVEG#define ioc_std$are_bitmaps_active_ipl0 IOC_STD$ARE_BITMAPS_ACTIVE_IPL0A#define ioc_std$ignore_local_bitmaps IOC_STD$IGNORE_LOCAL_BITMAPS=#define ioc_std$ascwwid_to_binwwid IOC_STD$ASCWWID_TO_BINWWID=#define ioc_std$binwwid_to_ascwwid IOC_STD$BINWWID_T O_ASCWWID;#define ioc_std$fc_global_connect IOC_STD$FC_GLOBAL_CONNECT,#define ioc_std$broadcast IOC_STD$BROADCAST)#define ioc_std$bufpost IOC_STD$BUFPOST*#define ioc_std$cancelio IOC_STD$CANCELIO2#define ioc$cancel_cnt_res IOC$CANCEL_CNT_RES?#define ioc$cancel_cnt_res_nosync IOC$CANCEL_CNT_RES_NOSYNC9#define ioc$change_device_type IOC$CHANGE_DEVICE_TYPE,#define ioc$chan_to_ccb IOC$CHAN_TO_CCB,#define ioc_std$check_hwm IOC_STD$CHECK_HWM0#define ioc_std$chkmbxquota  IOC_STD$CHKMBXQUOTA0#define ioc_std$chkucbquota IOC_STD$CHKUCBQUOTA,#define ioc_std$clone_ucb IOC_STD$CLONE_UCB2#define ioc_std$closebufwind IOC_STD$CLOSEBUFWIND,#define ioc_std$conbrdcst IOC_STD$CONBRDCST*#define ioc_std$copy_ucb IOC_STD$COPY_UCB&#define ioc$cram_cmd IOC$CRAM_CMD%#define ioc$cram_io IOC$CRAM_IO*#define ioc$cram_queue IOC$CRAM_QUEUE(#define ioc$cram_wait IOC$CRAM_WAIT5#define ioc$create_ccb_table IOC$CREATE_CCB_TABLE.#define ioc_std$create_u cb IOC_STD$CREATE_UCB2#define ioc_std$create_diobm IOC_STD$CREATE_DIOBM.#define ioc_std$credit_ucb IOC_STD$CREDIT_UCB(#define ioc$ctrl_init IOC$CTRL_INIT,#define ioc_std$cvtlogphy IOC_STD$CVTLOGPHY.#define ioc_std$cvt_devnam IOC_STD$CVT_DEVNAM.#define ioc_std$dalloc_dev IOC_STD$DALLOC_DEV.#define ioc_std$dalloc_dmt IOC_STD$DALLOC_DMTF#define ioc_std$ddt_altstart_intercept IOC_STD$DDT_ALTSTART_INTERCEPTA#define ioc_std$ddt_cancel_intercept IOC_STD$DDT_CANCEL_INTERCEPTD#define io c_std$ddt_mntver_intercept IOC_STD$DDT_MNTVER_INTERCEPTC#define ioc_std$ddt_start_intercept IOC_STD$DDT_START_INTERCEPT2#define ioc$deallocate_ccb IOC$DEALLOCATE_CCB4#define ioc$deallocate_cram IOC$DEALLOCATE_CRAM4#define ioc$dealloc_cnt_res IOC$DEALLOC_CNT_RESA#define ioc$dealloc_cnt_res_nosync IOC$DEALLOC_CNT_RES_NOSYNC.#define ioc$dealloc_crab IOC$DEALLOC_CRAB0#define ioc$dealloc_crctx IOC$DEALLOC_CRCTX,#define ioc_std$debit_ucb IOC_STD$DEBIT_UCB.#def ine ioc_std$delete_ucb IOC_STD$DELETE_UCBB#define ioc_std$devconfig_cbk_iodb IOC_STD$DEVCONFIG_CBK_IODB=#define ioc_std$devconfig_register IOC_STD$DEVCONFIG_REGISTERA#define ioc_std$devconfig_deregister IOC_STD$DEVCONFIG_DEREGISTER.#define ioc_std$diagbufill IOC_STD$DIAGBUFILL*#define ioc_std$dismount IOC_STD$DISMOUNT2#define ioc_std$errcnt_value IOC_STD$ERRCNT_VALUEE#define ioc_std$establish_ddt_altstart IOC_STD$ESTABLISH_DDT_ALTSTARTB#define ioc_std$establish_ddt_cancel IOC_STD$ ESTABLISH_DDT_CANCELA#define ioc_std$establish_ddt_mntver IOC_STD$ESTABLISH_DDT_MNTVERC#define ioc_std$establish_ddt_start IOC_STD$ESTABLISH_DDT_START0#define ioc$fill_iobd_pte IOC$FILL_IOBD_PTE.#define ioc_std$fill_diobm IOC_STD$FILL_DIOBM'#define ioc_std$filspt IOC_STD$FILSPT.#define ioc$first_extent IOC$FIRST_EXTENT*#define ioc_std$free_ucb IOC_STD$FREE_UCB)#define ioc_std$getbyte IOC_STD$GETBYTE?#define ioc$get_asym_access_state IOC$GET_ASYM_ACCESS_STATE4#def ine ioc$get_device_type IOC$GET_DEVICE_TYPE;#define ioc$get_extent_info IOC$GET_EXTENT_INFO4#define ioc$get_page80_wwid IOC$GET_PAGE80_WWID4#define ioc$get_page83_wwid IOC$GET_PAGE83_WWID5#define ioc$get_rpt_dev_udid IOC$GET_RPT_DEV_UDIDA#define ioc$get_targ_port_grp_num IOC$GET_TARG_PORT_GRP_NUM&#define ioc$get_udid IOC$GET_UDID)#define ioc_std$hwm_end IOC_STD$HWM_END5#define ioc$init_cram IOC$INIT_CRAM6#define ioc$init_c rctx IOC$INIT_CRCTX0#define ioc_std$initbufwind IOC_STD$INITBUFWIND*#define ioc_std$initiate IOC_STD$INITIATE9#define ioc_std$initiate_lck_rel IOC_STD$INITIATE_LCK_REL8#define ioc_std$initiate_new_io IOC_STD$INITIATE_NEW_IO*#define ioc$kp_reqchan IOC$KP_REQCHAN*#define ioc$kp_wfikpch IOC$KP_WFIKPCH*#define ioc$kp_wfirlch IOC$KP_WFIRLCH,#define ioc_std$last_chan IOC_STD$LAST_CHAN6#define ioc_std$last_chan_ambx IOC_STD$LAST_CHAN_AMBX*#define ioc_std$link_ucb IOC_STD$LINK_UCB&#define ioc$load_map IOC$LOAD_MAP*#define ioc$unload_map IOC$UNLOAD_MAP*#define ioc_std$lock_dev IOC_STD$LOCK_DEV2#define ioc$map_io IOC$MAP_IO)#define ioc_std$mapvblk IOC_STD$MAPVBLK'#define ioc_std$mntver IOC_STD$MNTVER(#define ioc$move_data IOC$MOVE_DATA,#define ioc_std$movfruser IOC_STD$MOVFRUSER.#define ioc_std$movfruser1 IOC_STD$MOVFRUSER1.#define ioc_std$movfruser2 IOC_STD$MOVFRUSER2,#define ioc_std$movtouser IOC_STD$MOV TOUSER.#define ioc_std$movtouser1 IOC_STD$MOVTOUSER1.#define ioc_std$movtouser2 IOC_STD$MOVTOUSER2.#define ioc$next_segment IOC$NEXT_SEGMENT(#define ioc$node_data IOC$NODE_DATA0#define ioc$node_function IOC$NODE_FUNCTION0#define ioc_std$opcnt_value IOC_STD$OPCNT_VALUE.#define ioc_std$parsdevnam IOC_STD$PARSDEVNAM*#define ioc_std$post_irp IOC_STD$POST_IRP4#define ioc_std$pre_simreqcom IOC_STD$PRE_SIMREQCOM=#define ioc_std$primitive_reqchanh IOC_STD$PRIMITIVE_REQCHANH=#d efine ioc_std$primitive_reqchanl IOC_STD$PRIMITIVE_REQCHANL;#define ioc_std$primitive_wfikpch IOC_STD$PRIMITIVE_WFIKPCH;#define ioc_std$primitive_wfirlch IOC_STD$PRIMITIVE_WFIRLCH*#define ioc_std$ptetopfn IOC_STD$PTETOPFN,#define ioc$ptetopfn_64 IOC$PTETOPFN_64)#define ioc_std$putbyte IOC_STD$PUTBYTE>#define ioc_std$q_internal_irp IOC_STD$Q_INTERNAL_IRP)#define ioc_std$qnxtseg IOC_STD$QNXTSEG*#define ioc_std$qnxtseg1 IOC_STD$QNXTSEG13#define ioc$read_io  IOC$READ_IO;#define ioc$read_pci_config IOC$READ_PCI_CONFIG2#define ioc$reallocate_ccb IOC$REALLOCATE_CCB)#define ioc_std$relchan IOC_STD$RELCHAN4#define ioc_std$release_diobm IOC_STD$RELEASE_DIOBM9#define ioc$remove_device_type IOC$REMOVE_DEVICE_TYPE'#define ioc_std$reqcom IOC_STD$REQCOM<#define ioc_std$reqcom_local IOC_STD$REQCOM_LOCAL,#define ioc$reserve_scb IOC$RESERVE_SCB##define ioc$return IOC$RETURN2#define ioc$return_suc cess IOC$RETURN_SUCCESS9#define ioc$return_unsupported IOC$RETURN_UNSUPPORTED2#define ioc$reverse_endian IOC$REVERSE_ENDIAN&#define ioc$scan_ccb IOC$SCAN_CCB,#define ioc_std$scan_iodb IOC_STD$SCAN_IODB2#define ioc_std$scan_iodb_2p IOC_STD$SCAN_IODB_2P9#define ioc_std$scan_iodb_usrctx IOC_STD$SCAN_IODB_USRCTX5#define ioc$scsipath_connect IOC$SCSIPATH_CONNECT'#define ioc_std$search IOC_STD$SEARCH,#define ioc_std$searchall IOC_STD$SEARCHALL.#define ioc_std$searchcont  IOC_STD$SEARCHCONT,#define ioc_std$searchdev IOC_STD$SEARCHDEV,#define ioc_std$searchint IOC_STD$SEARCHINT9#define ioc$search_device_type IOC$SEARCH_DEVICE_TYPE,#define ioc_std$sensedisk IOC_STD$SENSEDISK2#define ioc$setup_ucb_dipl IOC$SETUP_UCB_DIPL,#define ioc_std$sever_ucb IOC_STD$SEVER_UCB,#define ioc_std$simreqcom IOC_STD$SIMREQCOM(#define ioc$sndopcfao IOC$SNDOPCFAO8#define ioc_std$sndopc_mvsupmsg IOC_STD$SNDOPC_MVSUPMSG(#define ioc$sva_to_pa IOC$SVA_TO_PA4 #define ioc_std$svapte_in_buf IOC_STD$SVAPTE_IN_BUF.#define ioc$svapte_to_pa IOC$SVAPTE_TO_PA*#define ioc_std$testunit IOC_STD$TESTUNIT,#define ioc_std$threadcrb IOC_STD$THREADCRB.#define ioc_std$trandevnam IOC_STD$TRANDEVNAM(#define ioc$tr_to_adp IOC$TR_TO_ADP(#define ioc$unit_init IOC$UNIT_INIT.#define ioc_std$unlock_dev IOC_STD$UNLOCK_DEV4#define ioc$unmap_io IOC$UNMAP_IO0#define ioc$unreserve_scb IOC$UNRESERVE_SCBA#define ioc_std$update_dev_wwi d_list IOC_STD$UPDATE_DEV_WWID_LIST*#define ioc_std$va_to_pa IOC_STD$VA_TO_PA,#define ioc$verify_chan IOC$VERIFY_CHAN'#define ioc_std$wakacp IOC_STD$WAKACP4#define ioc$write_io IOC$WRITE_IO<#define ioc$write_pci_config IOC$WRITE_PCI_CONFIGC#define ioc_std$getsyi_cpu_specific IOC_STD$GETSYI_CPU_SPECIFICA#define ioc_std$zero_local_bitmap IOC_STD$ZERO_LOCAL_BITMAP?#define ioc_std$get_freeblock_count IOC_STD$GET_FREEBLOCK_COUNT/*N Function prototypes for system routines with the IOC$ and IOC_STD$ prefix.*/Dint ioc$add_adp (ADP *parent_adp, ADP *new_adp, int ba_index);Iint ioc$add_device_type (const char *, const int32, UCB *, DTN **);8int ioc$allocate_ccb (int16 *chan_p, CCB **ccb_p);Jint ioc$allocate_cram (CRAM **cram_p, IDB *idb, UCB *ucb, ADP *adp);Xint ioc$alloc_adp (int64 *adp, int adptype, int hose, int bustype, int nodecount);aint ioc$alloc_cnt_res (CRAB *crab, CRCTX *crctx, int64 cntxt1, int64 cntxt2, int64 cntxt3);@int ioc$alloc_crab (int itemcnt, int gran, CRAB **crab_p);Bint ioc$alloc_crctx (CRAB *crab, CRCTX **crctx_p, int flck);:void ioc_std$altreqcom (int iost1, int iost2, CDRP *cdrp,3 IRP **irp_p, UCB **ucb_p);Gint ioc_std$are_bitmaps_active(MSCP_UCB *vu_ucb, unsigned int flags);Tint ioc_std$are_bitmaps_active_ipl0(unsigned int vu_unit_num, unsigned int flags);aint ioc_std$ignore_local_bitmaps(struct _wbmb *wbmb_p, unsigned int group, unsigned int state);Sint ioc_std$ascwwid_to_binwwid(char *strptr, int len, char *result, int *reslen);\int ioc_std$binwwid_to_ascwwid(WWID *wwid_ptr, char *wwid_string, int inlen, int *retlen);Xint ioc_std$fc_global_connect(int unit, PCTX *pctx, int protocol_id, void(*cmprtn)());<int ioc_std$broadcast (int msglen, void *msg_p, UCB *ucb);+void ioc_std$bufpost (PCB *pcb, IRP *irp);@void ioc_std$cancelio (int chan, IRP *irp, PCB *pcb, UCB *ucb);Dint ioc$cancel_c nt_res (CRAB *crab, CRCTX *crctx, int resume);Kint ioc$cancel_cnt_res_nosync (CRAB *crab, CRCTX *crctx, int resume);Lint ioc$change_device_type (const char *, const int32, UCB *, DTN **);4int ioc$chan_to_ccb (int16 chan, CCB **ccb_p);#int ioc_std$check_hwm (IRP *irp);8int ioc_std$chkmbxquota (PCB *pcb, UCB *ucb, int quo);/int ioc_std$chkucbquota (PCB *pcb, UCB *ucb);7int ioc_std$clone_ucb (UCB *tmpl_ucb, UCB **new_ucb);&void ioc_std$closebufwind (UCB *ucb);2int  ioc_std$conbrdcst (int msglen, void *msg_p);5int ioc_std$copy_ucb (UCB *src_ucb, UCB **new_ucb);Iint ioc$cram_cmd (int cmdidx, int byteoffset, ADP *adp, CRAM *cram,* uint64 *iohandle);#int ioc$cram_io (CRAM *cram);&int ioc$cram_queue (CRAM *cram);%int ioc$cram_wait (CRAM *cram);.int ioc$create_ccb_table (int num_chan);#if VMS$SVAPTEHint ioc_std$create_diobm (const PTE_PQ va_pte, const uint32 pte_count,/  const uint32 flags,= PTE **svapte_p, DIOBM **diobm_p);#endif?int ioc_std$create_ucb (PCB *pcb, UCB *ucb, UCB **new_ucb_p);$void ioc_std$credit_ucb (UCB *ucb);-int ioc$ctrl_init (CRB *crb, DDB *ddb);6void ioc_std$cvtlogphy (int lbn, IRP *irp, UCB *ucb);Dint ioc_std$cvt_devnam (int buflen, char *buf, int form, UCB *ucb,, int32 *outlen_p );.int ioc_std$dalloc_dev (PCB *pcb, UCB *ucb);.int ioc_std$dalloc_dmt (PCB *pcb, UC B *ucb);9void ioc_std$ddt_altstart_intercept(IRP *irp, UCB *ucb);Xvoid ioc_std$ddt_cancel_intercept (int chan, IRP *irp, PCB *pcb, UCB *ucb, int reason);7void ioc_std$ddt_mntver_intercept(IRP *irp, UCB *ucb);6void ioc_std$ddt_start_intercept(IRP *irp, UCB *ucb);(int ioc$deallocate_ccb (CCB *ccb);+int ioc$deallocate_cram (CRAM *cram);9int ioc$dealloc_cnt_res (CRAB *crab, CRCTX *crctx);@int ioc$dealloc_cnt_res_nosync (CRAB *crab, CRCTX *crctx);(int ioc$deal loc_crab (CRAB *crab);+int ioc$dealloc_crctx (CRCTX *crctx);-void ioc_std$debit_ucb (UCB *ucb, PCB *pcb);$void ioc_std$delete_ucb (UCB *ucb);(int ioc_std$devconfig_cbk_iodb (void);Pint ioc_std$devconfig_register (int flags, int devclass, void (*devconfigured)J (UCB *ucb, int64 user_param), int64 user_param, int64 * ret_handle);1int ioc_std$devconfig_deregister(int64 handle);6void ioc_std$diagbufill (int driver_param, UCB *ucb);7int ioc_std$dismount (int flags, PCB *pcb, MTL *mtl);&int ioc_std$errcnt_value (UCB *ucb);oint ioc_std$establish_ddt_altstart (UCB*, int (*altstart_routine) (IRP *irp, UCB *ucb), int level, int flag);vint ioc_std$establish_ddt_cancel (UCB *, int (*cancel_routine) (int chan, IRP *irp, PCB *pcb, UCB *ucb, int reason), int level, int flag);lint ioc_std$establish_ddt_mntver (UCB*, int (*mntver_routine) ( IRP *irp, UCB *ucb), int level, int flag);jint ioc_std$establish_ddt_start (UCB*, int (*start_routine) (IRP *irp, U CB *ucb), int level, int flag);#if VMS$SVAPTEBint ioc_std$fill_diobm (DIOBM *const diobm, const PTE_PQ va_pte,E const uint32 pte_count, const uint32 flags,* PTE **svapte_p);#endif void *ioc_std$filspt (UCB *ucb);"void ioc_std$free_ucb (UCB *ucb);:int ioc_std$getbyte (void *sva, UCB *ucb, void **sva_p);_int ioc$get_asym_access_state (RPT_TPG_DAT *tpg_dat, short requested_grpnum, int *state);.int ioc$get_device_type (UCB * , DTN **);Iint ioc$get_page80_wwid (INQUIRY_DATA *inq_data, PAGE80 *pg80_data, struct _sn_wwid *wwid);Fint ioc$get_page83_wwid (PAGE83 *pg83_data, struct _wwid *wwid);8int ioc$get_rpt_dev_udid(const unsigned int *dev_data,% int data_len, int *udid_p);Eint ioc$get_targ_port_grp_num (PAGE83 *pg83_data, short *tpg_num);8int ioc$get_udid (DEVID *devid_data, int *udid_p);+void ioc_std$hwm_end (PCB *pcb, IRP *irp);%void *ioc_std$initbufwind (UCB *ucb);/int  ioc$init_cram (ADP *adp, CRAM *cram);>int ioc$init_crctx (CRAB *crab, CRCTX *crctx, int flck);,void ioc_std$initiate (IRP *irp, UCB *ucb);4void ioc_std$initiate_lck_rel (IRP *irp, UCB *ucb);3void ioc_std$initiate_new_io (IRP *irp, UCB *ucb);-int ioc$kp_reqchan (KPB *kpb, int pri);9int ioc$kp_wfikpch (KPB *kpb, int tmo, int newipl);9int ioc$kp_wfirlch (KPB *kpb, int tmo, int newipl);7void ioc_std$last_chan (int chan, PCB *pcb, UCB *ucb);2void ioc_std$la st_chan_ambx (PCB *pcb, UCB *ucb);Aint ioc_std$link_ucb (UCB *ucb, ... ); /* [ UCB **outucb_p ] */Fint ioc$load_map (ADP *adp, CRCTX *crctx, PTE *svapte, int boff,+ void **dma_addr_p);2int ioc$unload_map (ADP *adp, CRCTX *crctx);Kint ioc_std$lock_dev (int lockmode, void *lock_val_p, PCB *pcb, UCB *ucb,) int32 *lockid_p);Mint ioc$map_io (ADP *adp, int node, uint64 *phys_offset, int num_bytes,4 int attr, uint64 *iohandle);?int ioc_std$mapvblk (unsigned int vbn, unsigned int numbytes,& WCB *wcb, IRP *irp, UCB *ucb,> uint32 *lbn_p, uint32 *notmapped_p, UCB **new_ucb_p);*void ioc_std$mntver (IRP *irp, UCB *ucb);Pvoid *ioc_std$movfruser (void *sysbuf, int numbytes, UCB *ucb, void **sysbuf_p);\void *ioc_std$movfruser1 (void *sysbuf, int numbytes, UCB *ucb, void *sva, void **sysbuf_p);\void *ioc_std$movfruser2 (void *sysbuf, int numbytes, UCB *ucb, void *sva, void **sysbuf_p);Pvoid *ioc_std$movtouser (void *sysbuf, int numbytes, UCB *ucb, void **sysbuf_p);\void *ioc_std$movtouser1 (void *sysbuf, int numbytes, UCB *ucb, void *sva, void **sysbuf_p);\void *ioc_std$movtouser2 (void *sysbuf, int numbytes, UCB *ucb, void *sva, void **sysbuf_p);?int ioc$node_data (CRB *crb, int func, void *buf_p, ...);6int ioc$node_function (CRB *crb, int func, ...);%int ioc_std$opcnt_value (UCB *ucb);Aint ioc_std$parsdevnam (int devnamlen, char *devnam, int flags,M  int32 *unit_p, int32 *scslen_p, int32 *devnamlen_p,; char **devnam_p, int32 *flags_p);"void ioc_std$post_irp (IRP *irp);9int ioc_std$pre_simreqcom (int pri, int efn, ACB *acb);Cint ioc_std$primitive_reqchanh (IRP *irp, UCB *ucb, IDB **idb_p);Cint ioc_std$primitive_reqchanl (IRP *irp, UCB *ucb, IDB **idb_p);?void ioc_std$primitive_wfikpch (IRP *irp, int64 fr4, UCB *ucb,; int tmo, int restore_ipl);?void ioc_std$primitive_wfirlch (IRP *irp, int64 fr4, UCB *ucb,; int tmo, int restore_ipl);K#ifdef __INITIAL_POINTER_SIZE /* Defined if support for 64-bit pointers */#ifdef VMS$PFNBITS_32$int ioc_std$ptetopfn (PTE_PQ pte);#endif$PFN_T ioc$ptetopfn_64 (PTE_PQ pte);#else"int ioc_std$ptetopfn (PTE *pte);##endif /* __INITIAL_POINTER_SIZE */7void *ioc_std$putbyte (void *sva, char data, UCB *ucb);Lint ioc_std$q_internal_irp(IRP *irp, UCB *ucb,  IOSB_PQ iosb, VOID_PQ mbz);Bvoid ioc_std$qnxtseg (IRP *irp, PCB *pcb, UCB *ucb, UCB **ucb_p);7void ioc_std$qnxtseg1 (uint64 vbn, int bcnt, WCB *wcb,C IRP *irp, PCB *pcb, UCB *ucb, UCB **ucb_p);>int ioc$read_io (ADP *adp, uint64 *iohandle, int offset,2 int length, void *data_p);Bint ioc$read_pci_config (ADP *adp, int pci_node, int offset,1 int length, int *data_p);7int ioc$reallocate_ccb (int16 chan, CCB **ccb_p);!void ioc_std$relchan (UCB *ucb);#if VMS$SVAPTE1int ioc_std$release_diobm (DIOBM *const diobm);#endif,int ioc$remove_device_type (UCB *ucb);6void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);(void ioc_std$reqcom_local (CDRP *cdrp);Jint ioc$reserve_scb (int count, int min_vec, int max_vec, int align,, int32 *resvec_p);void ioc$return (void);$int ioc$return_success (void);(int ioc$return_unsupported (void);;void ioc$reverse_endian(char *buffer, int byte_count);8int ioc$scan_ccb (int32 **context_p, CCB **ccb_p);Gint ioc_std$scan_iodb (UCB *ucb, DDB *ddb, UCB **ucb_p, DDB **ddb_p);9int ioc_std$scan_iodb_2p (int path, UCB *ucb, DDB *ddb,E int32 *path_p, UCB **ucb_p, DDB **ddb_p);Fint ioc_std$scan_iodb_usrctx (int ctx, int unit, UCB *ucb, DDB *ddb,W int32 *ctx_p, int32 *unit_p, UCB **ucb_p, DDB **ddb_p);*int ioc$scsipath_connect (SCQ *scq);Cint ioc_std$search (VOID_PQ descr_p, int flags, void *lock_val_p,; UCB **ucb_p, DDB **ddb_p, SB **sb_p);Oint ioc_std$searchall (VOID_PQ descr_p, UCB **ucb_p, DDB **ddb_p, SB **sb_p);Kint ioc_std$searchcont (int unit, int scslen, UCB *ucb, DDB *ddb, SB *sb,A int devnamlen, char *devnam, int flags,R UCB **ucb_p, DDB **ddb_p, SB **sb_p, void **lock_val_p);Oint ioc_std$searchdev (VOID_PQ descr_p , UCB **ucb_p, DDB **ddb_p, SB **sb_p);Kint ioc_std$searchint (int unit, int scslen, int devnamlen, char *devnam,H int flags, UCB **ucb_p, DDB **ddb_p, SB **sb_p,, void **lock_val_p);Eint ioc$search_device_type (const char *, const int32, DTN **);Aint ioc_std$sensedisk (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);(void ioc$setup_ucb_dipl (UCB *ucb);#void ioc_std$sever_ucb (UCB *ucb);Gint ioc_std$simreqcom (VOID_PQ iosb, int pri , int efn, int32 iost[2],/ ACB *acb, int acmode);Wint ioc$sndopcfao (unsigned int opc_msg_code, unsigned int opc_class_mask, ... );)void ioc_std$sndopc_mvsupmsg (UCB *ucb);Oint64 ioc$sva_to_pa (void *svapte, int64 *pa, int buflen, int32 *retlen_p);Cint ioc_std$svapte_in_buf (IRP *irp, VOID_PQ va, PTE **svapte_p);Jint64 ioc$svapte_to_pa (void *svapte, int boff, int64 *pa, int buflen,@ int32 *retlen_p, void **nxtsvapte_p);C int ioc_std$testunit (int unit, int devtype, UCB *ucb, int flags,G void *lock_val_p, UCB **ucb_p, int32 *flags_p);#void ioc_std$threadcrb (CRB *crb);@int ioc_std$trandevnam (VOID_PQ descr_p, int flags, char *buf,7 int32 *outlen, void **out_p);!ADP *ioc$tr_to_adp (int tr);#int ioc$unit_init (UCB *ucb);$int ioc_std$unlock_dev (UCB *ucb);4int ioc$unmap_io (ADP *adp, uint64 *iohandle);=int ioc$unreserve_scb (int c ount, int32 vector_list[]);Bint ioc_std$update_dev_wwid_list (WWID *wwid_ptr, char *devnam);5VOID_PQ ioc_std$va_to_pa (VOID_PQ va, VOID_PPQ pa_p);4int ioc$verify_chan (int16 chan, CCB **ccb_p);*void ioc_std$wakacp (UCB *ucb, IRP *irp);?int ioc$write_io (ADP *adp, uint64 *iohandle, int offset,3 int length, void *data_p);Cint ioc$write_pci_config (ADP *adp, int pci_node, int offset,/ int length, int wdata);Jint ioc_std$ getsyi_cpu_specific (int getsyi_code, unsigned char *buffer,; int *buffer_length);5int ioc_std$zero_local_bitmap(struct _wbmh handle);gint ioc_std$get_freeblock_count( unsigned int lock_id, unsigned int buffer_size, long long *ret_buff );Jint ioc_std$validate_ucb( UCB *ucb, DDB *old_ddb, unsigned int old_unit );Iint ioc$fill_iobd (IOBD_PQ iobd, VOID_PQ va, int bcnt, uint32 flags);Wint ioc$fill_iobd_pte (IOBD_PQ iobd, PTE_PQ pte, int boff, int bcnt, uint32 flags);(int ioc$release_iobd (IOBD_PQ iobd);Lint ioc$create_iobd (VOID_PQ va, int bcnt, uint32 flags, IOBD_PPQ iobd);Eint ioc$first_extent (IOBD_PQ iobd, EXT_PPQ ppq_extent, int *offset);Dint ioc$next_segment (EXT_PPQ ppq_extent, int *p_offset, int abcnt);#define FROM_USER_BUFFER (0)#define TO_USER_BUFFER (1)@int ioc$move_data (VOID_PQ sysbuf, /* SVA of system buffer */G int bcnt, /* Number of bytes to move */c  EXT_PQ extent, /* Address of first user buffer EXT (extent structure) */` int extent_boff, /* Offset into 1st user buffer EXT of extents array */[ uint64 to, /* To-user-buffer boolean (0 from = 0, 1 = to) */f int *moved); /* Pointer to int in which to return the moved byte count */S#define ioc$move_from_user(sysbuf,bcnt,extent,extent_boff, moved) \Q ioc$move_data  (sysbuf,bcnt,extent,extent_boff,FROM_USER_BUFFER,moved)O#define ioc$move_to_user(sysbuf,bcnt,extent,extent_boff, moved) \M ioc$move_data (sysbuf,bcnt,extent,extent_boff,TO_USER_BUFFER,moved)R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif"#endif /* __IOC_ROUTINES_LOADED */wwZUP/*******************************************************************************P * *P * Copyright Digital Equipment Corporation 1995, 1996 All rights reserved. *P * *P * Restricted Rights: Use, duplication, or disclosure by the U.S. Government *P * is subject to restrictions as set forth *P * in subparagraph (c) (1) (ii) of  *P * DFARS 252.227-7013, or in FAR 52.227-19, or in FAR 52.227-14 Alt. III, as *P * applicable. *P * *P * This software is proprietary to and embodies the confidential technology of *P * Digital Equipment Corporation. Possession, use, or copying of this software *P * and media is authorized only pursuant to a valid written license from *P * Digital or an authorized sublicensor. *P * *Q *******************************************************************************//*++  * FACILITY: CPU1605 * * ABSTRACT: *I * This module contains structure definitions for the different types of P * rawhide addresses and for the individual bits in the MC-PCI bridge CSRs.J * This .h file is not generated by SDL. The structures here are notL * defined with SDL in order to keep their field names simple (i.e. in B * order to have the same field name in multiple structures). * * AUTHORS: *@ * Walter D. Arbo CREATION DATE: 23-May-1995 * * REVISION HISTORY: *6 * X-2 WDA W.D. Arbo 05-Feb-19963 * Add bits for I2C bus to RH_INT_MASK6 * X-1 WDA W.D. Arbo 23-May-1995 * Initial version. *-- */#include #pragma __member_alignment save%#pragma __nomember_alignment quadword/* * * Rawhide Sparse Memory Space CPU Address * I * 63 40 39 38-36 35-33 32 31 7 6 5 4-3 2-0J * +------------+---+-----+-----+---+----------------+--------+-----+---+J * | 0 | 1 | GID | MID | 0 | address info. | offset | len | 0 |J * +------------+---+-----+-----+---+----------------+--------+-----+---+ */typedef union { uint64 q; struct { unsigned mbz : 3; unsigned len : 2; unsigned addr : 27; unsigned type : 1; unsigned mid : 3; unsigned gid : 3; unsigned io : 1; unsigned mbz_2 : 24; } bits;} RH_SPARSE_MEM_ADDR; #define RH_SPARSE_MEM_ADDR_T 0/* ) * Rawhide Dense Memory Space CPU Address * G * 63 40 39 38-36 35-33 32-31 30  0H * +------------+---+-----+-----+-----+-------------------------------+H * | 0 | 1 | GID | MID | 10 | address info. |H * +------------+---+-----+-----+-----+-------------------------------+ */typedef union { uint64 q; struct { unsigned addr : 31; unsigned type : 2; unsigned mid : 3; unsigned gid : 3; unsigned io : 1; unsigned mbz_2 : 24; } bits;} RH_DENSE_MEM_ADDR; #define RH_DENSE_MEM_ADDR_T 2/* ' * Rawhide Sparse I/O Space CPU Address * K * 63 40 39 38-36 35-33 32-30 29 7 6 5 4-3 2-0L * +------------+---+-----+-----+-----+----------------+--------+-----+---+L * | 0 | 1 | GID | MID | 110 | address info. | offset | len | 0 |L * +------------+---+-----+-----+-----+----------------+--------+-----+---+ */typedef union { uint64 q; struct { unsigned mbz   : 3; unsigned len : 2; unsigned addr : 25; unsigned type : 3; unsigned mid : 3; unsigned gid : 3; unsigned io : 1; unsigned mbz_2 : 24; } bits;} RH_SPARSE_IO_ADDR; #define RH_SPARSE_IO_ADDR_T 6/* 9 * Rawhide Sparse Config Space CPU Address (Sparse Space) * ] * 63 40 39 38-36 35-33 32 29 28 21 20 16 15 13 12 7 6 5 4-3 2-0^ * +------------+---+-----+-----+------ -+-------+---------+------+-------+--------+-----+---+^ * | 0 | 1 | GID | MID | 1110 | bus | device | func | reg | offset | len | 0 |^ * +------------+---+-----+-----+-------+-------+---------+------+-------+--------+-----+---+ */typedef union { uint64 q; struct { unsigned mbz : 3; unsigned len : 2; unsigned offset : 2; unsigned reg : 6; unsigned func : 3; unsigned device : 5; unsigned bus   : 8; unsigned type : 4; unsigned mid : 3; unsigned gid : 3; unsigned io : 1; unsigned mbz_2 : 24; } bits;} RH_PCI_CONFIG_ADDR;"#define RH_PCI_CONFIG_ADDR_T 0x0E/* A * Rawhide PCI CSR Space CPU Address Format (Pseudo-Sparse space) * M * 63 40 39 38-36 35-33 32 28 27 7 6 5 4-3 2-0N * +------------+---+-----+-----+-------+----------------+--------+-----+---+N * | 0 | 1 | GID |  MID | 11110 | address info. | offset | len | 0 |N * +------------+---+-----+-----+-------+----------------+--------+-----+---+ */typedef union { uint64 q; struct { unsigned mbz : 3; unsigned len : 2; unsigned addr : 23; unsigned type : 5; unsigned mid : 3; unsigned gid : 3; unsigned io : 1; unsigned mbz_2 : 24; } bits;} RH_PCI_CSR_ADDR; #define RH_PCI_CSR_ADDR_T 0x01E  ./* Definitions for bits in the bridge CSRs. */%#pragma __nomember_alignment longwordtypedef union { uint32 l; struct { unsigned int0_mid : 3; unsigned int0_gid : 3; unsigned int1_mid : 3; unsigned int1_gid : 3; unsigned mbz : 20; } bits0; struct {& unsigned int0_targ_dev_id : 6;& unsigned int1_targ_dev_id : 6; unsigned mbz : 20; } bits1;  } RH_INT_TARG; typedef union {  uint32 l; struct { unsigned mbz_2 : 2; unsigned pci_offset : 4; unsigned mbz : 6;! unsigned int_adr_lo : 20; } bits; } RH_INT_ADR; typedef union { uint32 l; struct {! unsigned int_adr_ext : 7; unsigned mbz : 25; } bits; } RH_INT_ADR_EXT;typedef union { uint32 l; struct { unsigned intr : 16; unsigned eisa_intr : 1; unsigned i2c_ctrl : 1; unsigned i2c : 1; unsigned mbz : 2; unsigned eisa_nmi : 1; unsigned soft_error : 1; unsigned hard_error : 1; unsigned mbzz : 8; } bits; } RH_INT_MASK;typedef union { uint32 l;( struct { unsigned cap_rev : 4;( unsigned horse_rev : 4;( unsigned saddle_rev : 4;( unsigned saddle_type : 3;( unsigned eisa_present : 1;) unsigned pci_cc : 16;  } bits; } RH_PCI_REV;typedef union { uint32 l;! struct { unsigned mid : 3;! unsigned gid : 3;! unsigned cpu : 8;" unsigned mbz : 18; } bits; } RH_WHOAMI;typedef union { uint32 l;! struct { unsigned enable : 1;) unsigned scatter_gather : 1; unsigned mbz : 18; unsigned base : 12; } bits; } RH_W_BASE; typedef union { uint32 l; struct { unsigned mbz : 20; unsigned mask : 12; } bits; } RH_W_MASK;typedef union { uint32 l; struct { unsigned mbz : 2; unsigned base : 30; } bits; } RH_T_BASE; typedef union { uint32 l;" struct { unsigned h_bound : 9; unsigned mbz_0 : 4;! unsigned pc_he1 : 1;! unsigned pc_he2 : 1;! unsigned h_base : 9; unsigned mbz_1 : 8; } bits; } RH_HBASE; "#pragma __member_alignment restoreww@ZU#ifndef __LDR_ROUTINES_LOADED#define __LDR_ROUTINES_LOADED 1/* module LDR_ROUTINES.H "X-12"/*I************************************************************************* * *I* HPE CONFIDENTIAL. This software is confidential proprietary software *I* licensed by Hewlett Packard Enterprise Development, LP, and is not *I* authorized to be used, duplicated or disclosed to anyone without the *I* prior written permission of HPE. *I* Copyright 2017 Hewlett Packard Enterprise Development, LP *I* *I* VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *I* proprietary software licensed by VMS Software, Inc., and is not *I* authorized to be used, duplicated or disclosed to anyone without *I* the prior written permission of VMS Software, Inc. *I* Copyright 2017-2022 VMS Software, Inc. * * *I************************************************************************** *++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS systemB* routines that begin with the LDR$ and LDR_STD$ prefixes and have* a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ*  most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Paramete r namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.* /* 6. Mixed pointer sizes within one argumentJ* If a 64-bit pointer is being passed by reference, the reference toC* the pointer should also be 64 bits wide to avoid confusion.* For example:** PTE_PPQ va_pte_p;* VOID_PPQ start_va_p;*"* should be used instead of:** PTE_PQ *va_pte_p;* VOID_PQ *start_va_p;** * AUTHOR:* * Leonard S. Szubowicz* * CREATION DATE: 8-Jun-1993* * MODIFICATION HISTORY:*#* X-12 AHM Drew Mason 28-Jul-2022<* Change the type of the first parameter to ldr$alloc_slice-* from const uint64 to const int64, x86 only*#* X-11 AHM Drew Mason 20-Nov-20190* Make definitions of ldr_std$alloc_s0s1_va and,* ldr_std$dealloc_s0s1_va apply to x86 too.*#* X-10 AHM Drew Mason 13-Dec-2017:* Change some declarations for x86. Resync edit history.*)* X-8 SAD Stuart A. Davidson 21-Oct-2003>* Allow optional extra arg to LDR$ALLOC_SLICE, for alignment.*)* X-7 SAD Stuart A. Davidson 16-MAY-2002:* Add routines needed in converting the exec loader to C.*,* X-6 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*)* X-5 DFW0291 David F. Wall 29-Jan-1997#* Add ldr_std$alloc_s2_va_aligned.*,* X-4 NYK301 Nitin Y. Karkhanis 6-Mar-1995* Add ldr_std$count_s2_pages.*,* X-3 NYK259 Nitin Y. Karkhanis 7-Feb-19958* Correct formal argument types for system space memory:* allocation routines as per the new rule #6 (see above).*,* X-2 NYK098 Nitin Y. Karkhanis 2-Nov-19947* Define function protoypes for LDR_STD$ALLOC_S0S1_VA,4* LDR_STD$DEALLOC_S0S1_VA, LDR_STD$ALLOC_S2_VA, and* LDR_STD$ALLOC_S2_VA.*0* X-1 LSS0279 Leonard S. Szubowicz 8-Jun-1993@* Initial version containing only those routines commonly used* by device drivers.* *--*/ R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define all types that are used in the following function prototypes.*/#include #include #include /*P VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/5#ifdef __x86_64 // Verified for x86 port--Drew Mason0#define ldr_std$alloc_s0_va LDR_STD$ALLOC_S0_VA4#define ldr_std$dealloc_s0_va LDR_STD$DEALLOC_S0_VA#endif4#define ldr_std$alloc_s0s1_va LDR_STD$ALLOC_S0S1_VA8#define ldr_std$dealloc_s0s1_va LDR_STD$DEALLOC_S0S1_VA*#define ldr_std$alloc_pt LDR_STD$ALLOC_PT.#define ldr_std$dealloc_pt LDR_ST D$DEALLOC_PT0#define ldr_std$alloc_s2_va LDR_STD$ALLOC_S2_VA4#define ldr_std$dealloc_s2_va LDR_STD$DEALLOC_S2_VA6#define ldr_std$count_s2_pages LDR_STD$COUNT_S2_PAGES?#define ldr_std$alloc_s2_va_aligned LDR_STD$ALLOC_S2_VA_ALIGNED)#define ldr$alloc_slice LDR$ALLOC_SLICE,#define ldr$dealloc_slice LDR$DEALLOC_SLICE/*N Function prototypes for system routines with the LDR$ and LDR_STD$ prefix.*/3int ldr_std$alloc_pt (int npte, void **svapte_p);2int ldr_std$dealloc_pt (void * svapte, int npte);5#ifdef __x86_64 // Verified for x86 port--Drew MasonRint ldr_std$alloc_s0_va (const int req_pages, VOID_PPQ sva_p, PTE_PPQ va_pte_p);Fint ldr_std$dealloc_s0_va (const int page_count, const VOID_PQ sva);Gint ldr$alloc_slice (const int64 page_type, const uint64 alloc_size, / INT64_PQ ret_va_ref, const uint64 rq_align);#elseHint ldr$alloc_slice (const uint64 page_type, const uint64 alloc_size, K const uint64 return_length, const uint64 offset, void *ret_va_r !ef, ...);#endifTint ldr_std$alloc_s0s1_va (const int req_pages, VOID_PPQ sva_p, PTE_PPQ va_pte_p);Hint ldr_std$dealloc_s0s1_va (const int page_count, const VOID_PQ sva);Rint ldr_std$alloc_s2_va (const int req_pages, VOID_PPQ sva_p, PTE_PPQ va_pte_p);Fint ldr_std$dealloc_s2_va (const int page_count, const VOID_PQ sva);$int ldr_std$count_s2_pages (void);Fint ldr_std$alloc_s2_va_aligned (const int req_pages, VOID_PPQ sva);\int ldr$dealloc_slice ( const uint64 PAGE_TYPE, uint64" dealloc_size_in_bytes, VOID_PQ VA);R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif"#endif /* __LDR_ROUTINES_LOADED */wwZU/* Version X-18I*************************************************************************I* *I* VMS SOFTWARE, INC. CONFIDENTIAL. This #software is confidential *I* proprietary software licensed by VMS Software, Inc., and is not *I* authorized to be used, duplicated or disclosed to anyone without *I* the prior written permission of VMS Software, Inc. *I* Copyright 2019 VMS Software, Inc. *I* *I************************************************************************* *$//**++ * FACILITY:** Open/VMS AXP (LIB)* * ABSTRACT:*I* This header file will provide big page inline functions equivalent to ;* the LIB big page macros which exist for BLISS and Macro.* * AUTHOR:** Karen Noel*"* CREATION DATE: 12-Sep-1994** MODIFICATION HISTORY:*<* X-18 CEG0915 Clair Grant 25-Sep-20205* Change comment in X-17 *** X-17 CEG0906 Clair Grant 24-Sep-2020** Rep%lace "// comment" style to eliminate+* confusion when compiling /STANDARD=VAXC.*%* X-16 AHM Drew Mason 17-Jun-20196* Bug located and fixed. Revert to contents of X-13.*%* X-15 AHM Drew Mason 13-Jun-20198* Set __required_pointer_size to long in case some code+* using this include file has it as short.*%* X-14 AHM Drew Mason 11-Jun-2019:* Back out X-13 and feed it in piece by piece to identify3* the failing part. Define mmg$gq_shared_va_ptes,6* mmg$gq_bpt_ba&se, and mmg$gq_phymem_window_base_addr0* based on architecture, not on __SYSBOOT flag.*%* X-13 LMN Lisa Nevin 07-Jun-20195* X86 support for $is_process_pte_va, removed source8* conditionals based on the __SYSBOOT flag*%* X-12 LMN Lisa Nevin 15-Mar-2019>* Add x86 bug fix to is_private_va, to check also if equal on* boundary mmg$gq_bpt_base*** X-11 MJM Michael Moroney 13-Sep-2018=* Add X86 specific versions of $is_private_va, $is_shared_va>* and $'is_system_pte_va where mmg$gq_shared_va_ptes is really,* an array of four addresses, one per mode.*%* X-10 AHM Drew Mason 10-Aug-20182* Change BIGPAGE$BWP_WIDTH, BIGPAGE$BWP_MASK, and5* BIGPAGE$PAGE_SIZE on x86 for page allocation size.3* Define BIGPAGE$VA_MASK and BIGPAGE$PT_MASK. Fix-* macros to use the correct revised symbols.*(* X-9 DOF Dave Fairbanks 13-Jun-2018'* Move the following RUNCONST symbols:* - mmg$gq_level_width* - mmg$gq_ptes_per_page* - mmg($gl_bwp_width* - mmg$gl_bwp_mask* - mmg$gl_page_size5* before the #ifdef __x86_64 conditional so they are* also declared for X86.*$* X-8 AHM Drew Mason 15-May-2018?* Fix bug where defined symbols conflict with symbols in other;* modules with the same name. Add BIGPAGE$ to all defined * symbols.*#* X-7 AHM Drew Mason 4-May-2018<* For x86, use compile-time constants for level width, ptes0* per page, bwp width, bwp mask, and page size.*$* X-6 AHM Drew )Mason 12-Apr-2018=* Fix improper declaration of mmg$gq_phymem_window_base_addr * as int64 rather than __int64.*#* X-5 AHM Drew Mason 9-Mar-20182* Resync modification history. Add definition of7* __RUNCONST to allow SYSBOOT to write the "constants"/* used here. Update macros $is_system_pte_va,:* $is_shared_va, and $is_private_va for x86 complexities.*.* X-3A1A3 KLN3058 Karen L. Noel 18-Apr-2002A* o Add more parens in $make_va macro so it works in conditional+* s*tatements and with complex arguments..* o Add $is_valid_address macro.*.* X-3A1A2 KLN3037 Karen L. Noel 13-Mar-20027* We don't trust the compiler anymore. Put the inlines1* back in. It messes up initialization routines.*.* X-3A1A1 KLN3025 Karen L. Noel 26-Feb-2002* o Port PT space to IA64.6* o Remove inline pragmas. We trust the compiler now.*,* X-3A1 KLN2202 Karen L. Noel 27-Nov-20001* Fix $make_va so it properly returns a VOID_PQ.*+* X-3 KLN1+396 Karen L. Noel 24-Feb-1995(* Add $is_shared_va and $is_private_va.*+* X-2 KLN1322 Karen L. Noel 22-Sep-1994'* 64-bit project: Internal programming* Define roundup argument.**--*/#ifndef __LIB_BIGPAGE_LOADED#define __LIB_BIGPAGE_LOADED 1#ifdef __INITIAL_POINTER_SIZE$#pragma __required_pointer_size save$#pragma __required_pointer_size long#endif /* * Included files: * * */#include #include #include ,9#ifdef __x86_64 /* Verified for x86 port--Drew Mason */#include #endif F/* This construct allows SYSBOOT write access to variables that are */F/* run-time constants, but need to be initialized at boot time. */#ifdef __SYSBOOT#define __RUNCONST#else#define __RUNCONST const#endif/* * * External data cells: * */9#ifdef __x86_64 /* Verified for x86 port--Drew Mason */5extern PTE_PQ __RUNCONST mmg$gq_shared_va_ptes [4];/extern PTE_PQ __R-UNCONST mmg$gq_bpt_base [4];;extern __int64 __RUNCONST mmg$gq_phymem_window_base_addr;#else1extern PTE_PQ __RUNCONST mmg$gq_shared_va_ptes;<extern PTE_PQ __RUNCONST mmg$gq_pt_base [VA$C_VRNX_COUNT];#endif8extern VOID_PQ __RUNCONST mmg$gq_system_virtual_base;6extern __RUNCONST unsigned __int64 mmg$gq_non_va_mask;=/* The symbols defined below cannot be UNDEFINED because they> * need to be available in the source file that includes them.> * So prefix them with BIGPAGE$, w.hich is unlikely to conflict * with other symbol names. */6extern __RUNCONST unsigned __int64 mmg$gq_level_width;8extern __RUNCONST unsigned __int64 mmg$gq_ptes_per_page;'extern __RUNCONST int mmg$gl_bwp_width;&extern __RUNCONST int mmg$gl_bwp_mask;'extern __RUNCONST int mmg$gl_page_size;8#ifdef __x86_64 /* Verified for x86 port--Drew Mason */2extern __RUNCONST unsigned __int64 mmg$gq_pt_mask;2extern __RUNCONST unsigned __int64 mmg$gq_va_mask;3#define BIGPAGE$LEVEL_WIDTH MMG$$C_PTE /_SEGMENT_SIZE2#define BIGPAGE$PTES_PER_PAGE MMG$$C_PTES_PER_PAGE&#define BIGPAGE$PT_MASK mmg$gq_pt_mask&#define BIGPAGE$VA_MASK mmg$gq_va_maskM/* These next three are based on the page allocation size of 8 kB, not the */8/* page size defined in the x86 architecture of 4 kB. */*#define BIGPAGE$BWP_WIDTH MMG$$C_BWP_WIDTH,#define BIGPAGE$BWP_MASK MMG$$C_BOFF_MASK_8K/#define BIGPAGE$PAGE_SIZE MMG$$C_BYTES_PER_PAGE#else.#define BIGPAGE$LEVEL_WIDTH mmg$gq_level_width2#define BIGPAGE$PTES_PER0_PAGE mmg$gq_ptes_per_page*#define BIGPAGE$BWP_WIDTH mmg$gl_bwp_width(#define BIGPAGE$BWP_MASK mmg$gl_bwp_mask*#define BIGPAGE$PAGE_SIZE mmg$gl_page_size-#define BIGPAGE$PT_MASK (~mmg$gq_non_pt_mask)-#define BIGPAGE$VA_MASK (~mmg$gq_non_va_mask)#endif /**++B* $sys_start_of_page - Calculate the starting address of the page.* * Inputs:* source_va - source address* * Returns:G* The address of the first byte within the page specified by source_va.*--*/'#define $s1ys_start_of_page(source_va) \N(VOID_PQ)((unsigned __int64)source_va & ~(unsigned __int64)(BIGPAGE$BWP_MASK)) /* *++:* $sys_next_page - Calculate the address of the next page.* * Inputs:* source_va - source address4* clearbwp - If 1, masks the bwp portion of the VA.* * Returns:F* The address of one page after the source address. If clearbwp is 1,E* the address will be rounded down to be the start of the next page.**--*/-#define $sys_next_page(source_va, clea2rbwp) \*(VOID_PQ)(((unsigned __int64)source_va + \3 (unsigned __int64)BIGPAGE$PAGE_SIZE) & \> ~(clearbwp * ((unsigned __int64)BIGPAGE$BWP_MASK)) ) /* *++B* $sys_previous_page - Calculate the address of the previous page.* * Inputs:* source_va - source address4* clearbwp - If 1, masks the bwp portion of the VA.* * Returns:G* The address of one page before the source address. If clearbwp is 1,I* the address will be rounded down to be the start of3 the previous page.**--*/1#define $sys_previous_page(source_va, clearbwp) \*(VOID_PQ)(((unsigned __int64)source_va - \3 (unsigned __int64)BIGPAGE$PAGE_SIZE) & \> ~(clearbwp * ((unsigned __int64)BIGPAGE$BWP_MASK)) ) /* *++.* $sys_pages_to_bytes - Convert pages to bytes* * Inputs:!* page_count - source page count* * Returns:$* The number of bytes in page_count.**--*/I#define $sys_pages_to_bytes(page_count) (page_count << BIGPAGE$BWP_WID4TH) /* *+++* $bytes_to_pages - Convert bytes to pages * * Inputs:* byte_count - Byte countI* roundup = 1 if byte_count is to be rounded up before converted to pages#* = 0 if rounding is not required.* * Returns:$* The number of pages in byte_count.**--*/2#define $sys_bytes_to_pages(byte_count, roundup) \@((byte_count + (roundup*BIGPAGE$BWP_MASK)) >> BIGPAGE$BWP_WIDTH) /**++5* $extract_vpn - Extract page table space vpn from va* * Inputs: 5* addr - source virtual address*'* Extracts a VPN from a virtual address**--*/#define $extract_vpn(addr) \;(unsigned int)(((unsigned __int64)addr & BIGPAGE$VA_MASK) \ >> BIGPAGE$BWP_WIDTH) /* *++ C* $extract_pte_offset - Extract page table space pte offset from va* * Inputs:* addr - source virtual address*/* Extracts a PTE offset from a virtual address**--*/(#define $extract_pte_offset(addr) \1(((unsigned __int64)addr & BIGPAGE$PT_MA6SK) \( >> BIGPAGE$LEVEL_WIDTH) /**++L* $make_va - Make a virtual address from a virtual page number in page table* space* * Input: #* vpn - source virtual page number* * Output: * va - virtual address (VOID_PQ)*2* Makes a virtual address from virtual page number**--*/@/* Shift a VPN into the proper location in a virtual address. */#define $$$non_sext_va(vpn) \.((unsigned __int64)(vpn) << BIGPAGE$BWP_WIDTH)H/* Mask to ext7ract the one bit in a shifted VPN that needs to be sign */9/* extended when crafting a canonical virtual address. */#define $$$sext_bit \)((unsigned __int64)1<<(mmg$gq_va_bits-1))#define $make_va(vpn) \8 ((($$$non_sext_va(vpn) & $$$sext_bit) == 0) ? \, (VOID_PQ)($$$non_sext_va(vpn)) : \; (VOID_PQ)($$$non_sext_va(vpn) | BIGPAGE$VA_MASK)) /**++:* $is_pt_space_va - Test if quadword is a PT space address** Inputs: arg - 64-bit address*&* Output8: 1 if arg is PT space address$* 0 if arg is not PT space address**--*/"#pragma inline ($$$is_pt_space_va)3static int $$$is_pt_space_va (unsigned __int64 arg){8# ifdef __x86_64 /* Verified for x86 port--Drew Mason */G if (arg < (unsigned __int64) mmg$gq_bpt_base [PSL$C_KERNEL]) return 0;H if (arg >= (unsigned __int64) mmg$gq_phymem_window_base_addr) return 0; return 1;# else int vrnx;% unsigned __int64 p,size_of_pt_space;# ifdef __NEW_STARLET VA v; v.va$q_quad = arg9;# else va v; v.va$q_quad[0] = arg; v.va$q_quad[1] = arg>>32;# endif /* __NEW_STARLET */ /* Get VRNX from the VA */ vrnx = v.va$v_vrnx;3 /* If less that pt_base, it's not a PT space VA */< if (arg < (unsigned __int64)mmg$gq_pt_base[vrnx]) return 0;; /* Get size of a PT space given 3 levels of page tables */ p = BIGPAGE$PTES_PER_PAGE;. size_of_pt_space = p*p*p*PTE$C_BYTES_PER_PTE;N /* If greater than or equal to the top of PT space, it's not a PT space VA */P if (a:rg >= (unsigned __int64)mmg$gq_pt_base[vrnx] + size_of_pt_space) return 0; /* It's a PT space VA */ return 1;# endif /* __x86_64 */}G#define $is_pt_space_va(arg) $$$is_pt_space_va((unsigned __int64)(arg)) /**++@* $is_process_pte_va - Test if quadword is a process pte addressX* for X86 page table entries are between Kernel bpt base and < Physical Memory WindowI* since we are checking for only process the max would be shared[USER]** Inputs: arg - 64-bit address;*)* Output: 1 if arg is process pte address'* 0 if arg is not process pte address**--*/%#pragma inline ($$$is_process_pte_va)6static int $$$is_process_pte_va (unsigned __int64 arg){ #ifdef __x86_64N return ( ( (arg >= (unsigned __int64) mmg$gq_bpt_base [PSL$C_KERNEL]) && _ ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_KERNEL]) ) || \U ( ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_bpt_base[PSL$C_EXEC]) && \\ ((unsi <gned __int64)(arg) < (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_EXEC]) ) || \V ( ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_bpt_base[PSL$C_SUPER]) && \] ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_SUPER]) ) || \U ( ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_bpt_base[PSL$C_USER]) && \W ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_USER]) ));#else int vrnx;# unsigned __int64 size_of_pt_space;=#ifdef __NEW_STARLET VA v; v.va$q_quad = arg;#else va v; v.va$q_quad[0] = arg; v.va$q_quad[1] = arg>>32;#endif /* Get VRNX from the VA */ vrnx = v.va$v_vrnx;> /* If VRNX is system space, it's not a process PTE address */( if (vrnx == VA$C_VRNX_SYSTEM) return 0;3 /* Return the results from the PT space VA test */ return ($is_pt_space_va(arg));#endif /* __x86_64 */}N#define $is_process_pte_va(arg) $$$is_process_pte_va ((unsigned __int64)(arg)) /**+>+>* $is_system_pte_va - Test if quadword is a system pte address** Inputs: arg - 64-bit address*(* Output: 1 if arg is system pte address&* 0 if arg is not system pte address**--*/:#ifdef __x86_64 /* Verified for x86 port--Drew Mason */ #define $is_system_pte_va(arg) \\ ( ( ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_KERNEL]) && \U ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_bpt_base[PSL$C_EXEC])) || \Z ( ((unsigned __int64)(a?rg) >= (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_EXEC]) && \V ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_bpt_base[PSL$C_SUPER])) || \[ ( ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_SUPER]) && \U ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_bpt_base[PSL$C_USER])) || \Z ( ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_USER]) && \U ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_phymem_window_base_a@ddr)) )#else #define $is_system_pte_va(arg) \K (((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_shared_va_ptes) && \L ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_system_virtual_base))#endif /* __x86_64 */ /**++1* $is_shared_va - Test if quadword is a shared va** Inputs: arg - 64-bit address*$* Output: 1 if arg is shared address"* 0 if arg is not shared address**--*/:#ifdef __x86_64 /* Verified for x86 port--Drew Mason */#define $is_Ashared_va(arg) \\ ( ( ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_KERNEL]) && \U ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_bpt_base[PSL$C_EXEC])) || \Z ( ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_EXEC]) && \V ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_bpt_base[PSL$C_SUPER])) || \[ ( ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_SUPER]) && \U ((unsigned __int64)(arg) < B (unsigned __int64)mmg$gq_bpt_base[PSL$C_USER])) || \W ( (unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_USER]) )#else#define $is_shared_va(arg) \E ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_shared_va_ptes)#endif /* __x86_64 */ /**++3* $is_private_va - Test if quadword is a private va** Inputs: arg - 64-bit address*%* Output: 1 if arg is private address#* 0 if arg is not private address**--*/:#ifdef __x86_64 /C* Verified for x86 port--Drew Mason */#define $is_private_va(arg) \Z ( ( (unsigned __int64)(arg) < (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_KERNEL]) || \Y ( ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_EXEC]) && \V ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_bpt_base[PSL$C_EXEC])) || \Z ( ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_SUPER]) && \W ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_bpt_base[PSDL$C_SUPER])) || \Y ( ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_shared_va_ptes[PSL$C_USER]) && \S ((unsigned __int64)(arg) >= (unsigned __int64)mmg$gq_bpt_base[PSL$C_USER])) )#else#define $is_private_va(arg) \D ((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_shared_va_ptes)#endif /* __x86_64 */ /**++@* $is_valid_address - Test if quadword is a valid 64-bit address** Inputs: arg - 64-bit address*#* Output: 1 if arg is valid address!* 0 if aErg is not valid address**--*/+extern VOID_PQ __RUNCONST mmg$gq_gap_lo_va;+extern VOID_PQ __RUNCONST mmg$gq_gap_hi_va; #define $is_valid_address(arg) \D(((unsigned __int64)(arg) < (unsigned __int64)mmg$gq_gap_lo_va) || \A ((unsigned __int64)(arg) > (unsigned __int64)mmg$gq_gap_hi_va) )#ifdef __INITIAL_POINTER_SIZE'#pragma __required_pointer_size restore#endif!#endif /* __LIB_BIGPAGE_LOADED */ww0RZU#ifndef __LIB_TYPES_LOADED#define __LIB_TYPES_LOAD FED 1/* Version X-2 */O/* ************************************************************************* */O/* * * */O/* * HPE CONFIDENTIAL. This software is confidential proprietary software * */O/* * licensed by Hewlett Packard Enterprise Development, LP, and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without the * */O/* * prior written permission of HPE. G * */O/* * Copyright 2017 Hewlett Packard Enterprise Development, LP * */O/* * * */O/* * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential * */O/* * proprietary software licensed by VMS Software, Inc., and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without * */O/* * the prior written permission of VMS Software, Inc. H * */O/* * Copyright 2017 VMS Software, Inc. * */O/* * * */O/* ************************************************************************* *//**++ * FACILITY:** Open/VMS AXP (LIB)* * ABSTRACT:*A* This header file will provide type definitions for C programs.* * AUTHOR:** Karen Noel*"* CREATION DATE: 26-Jan-2004** MODIFICATIOIN HISTORY:*'* X-2 CEG0119 Clair Grant 28-Apr-2017&* Verified conditionals for x86 port.* Updated copyright to VSI.*/ /*B** Define the size of a PFN field for Alpha and non-Alpha systems.*/A#if defined (__ALPHA) /* Verified for x86 port - Clair Grant */ typedef unsigned int PFN_T;#else typedef unsigned __int64 PFN_T;#endif#ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save&#pragma __required_pointer_size __longA typedef PFN_T * PFN_T_PQ; J /* 64-bit pointer to a PFN */)#pragma __required_pointer_size __restore#elseC typedef unsigned __int64 PFN_T_PQ; /* 64-bit pointer to a PFN */#endif#endif /* __LIB_TYPES_LOADED */wwPZU/**I* Copyright Digital Equipment Corporation, 1993 All Rights Reserved.O* Unpublished rights reserved under the copyright laws of the United States.* L* The software contained on this media is proprietary to and embodies theP* confidential technoloKgy of Digital Equipment Corporation. Possession, use,N* duplication or dissemination of the software and media is authorized onlyL* pursuant to a valid written license from Digital Equipment Corporation.* K* RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.G* Government is subject to restrictions as set forth in SubparagraphJ* (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable.* *++* * FACILITY:** VMS Executive (LIB_H)L* * ABSTRACT:* C* This module contains the C function prototypes for the VMS systemB* routines that begin with the ERL$ and ERL_STD$ prefixes and have* a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of th Me /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide evenN if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionaOlly equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outPlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.* * * AUTHOR:* * Leonard S. Szubowicz* * CREATION DATE: 9-Jun-1993* * MODIFICATION HISTORY:* -* X-2 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers fQrom the command line.*0* X-1 LSS0279 Leonard S. Szubowicz 9-Jun-1993@* Initial version containing only those routines commonly used* by device drivers.* *--*/ #ifndef __LNM_ROUTINES_LOADED#define __LNM_ROUTINES_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default toR 32-bit pointers */#endif/*G* Define all types that are used in the following function prototypes.*/#include #include #include /*P VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/0#define lnm_std$delete_lnmb LNM_STD$DELETE_LNMB%#define lnm_std$lockw LNM_STD$LOCKSW'#define lnm_std$unlock LNM_STD$UNLOCK/*N Function prototypes for system routines with the LNM$ and LNM_STD$ prefix.*/'int lnm_std$delete_lnmb (LNMB *lnmb);void lnm_std$lockw (PCB *pcb); void lnm_std$unlock (PCB *pcb);R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif"#endif /* __LNM_ROUTINES_LOADED */ww* this PSECT as: PIC,USR,CON,REL,GBL,NOSHR,NOEXE,RD,WRT,NOVEC*J* There are 3 "parameters" to this header file, the latter 2 of which canG* be defaulted (to zero). The following example shows how to setup the'* symbols and invoke this header file:*,* #define LDI_IMAGE_NAME "SYSTEM_DEBUG.EXE"* #define LDI_FLAGS 1* #define LDI_LDR_FYLAGS 1"* #include * * main()* { }* * AUTHOR:** Steve DiPirro*"* CREATION DATE: 18-Feb-1993** MODIFICATION HISTORY:*C* X-2 SDD Steve DiPirro 20-May-1994-* Fix usage of #error directive**--*/ /*I We want to allow multiple inclusions of this header file. So no need to do the setup more than once.*/#ifndef __LOADABLE_IMAGE_SETUP #define __LOADABLE_IMAGE_SETUP 1Ztypedef struct{ int image_name_size; char *image_name; int flags; int ldr_flags;} LOADABLE_IMAGE_VEC;#define lixconcat(a,b) a ## b$#define liconcat(a,b) lixconcat(a,b)#define LIDATA_PREFIX ldi_vec_#define LIDATA_SUFFIX 0#endif/*: If we've been in here one too many times, let's get out.*/#if LIDATA_SUFFIX == 30C#error "Header file currently supports a max of 30 loadable images"#endif/* Setup any defaulted symbols.*/#ifndef LDI_IMAGE_NA[ME-#error "Loadable image name must be supplied"#endif#ifndef LDI_FLAGS#define LDI_FLAGS 0#endif#ifndef LDI_LDR_FLAGS#define LDI_LDR_FLAGS 0#endif/* Now initialize the structure*/#pragma extern_model save @#pragma extern_model strict_refdef "EXEC$NONPAGED_DATA_STATBLKS":LOADABLE_IMAGE_VEC liconcat(LIDATA_PREFIX,LIDATA_SUFFIX)={) sizeof(LDI_IMAGE_NAME)-1,LDI_IMAGE_NAME, LDI_FLAGS,LDI_LDR_FLAGS};#pragma extern_model restore/*4 Now undefine or redefine all\ the temporary symbols*/#undef LDI_IMAGE_NAME#undef LDI_FLAGS#undef LDI_LDR_FLAGS/*E Unfortunately, I could think of no other way to produce unique dataH names for each inclusion of this header file other than the nauseatingD hack below. This header file doesn't get used much...Not that it's any excuse, mind you.*/#if LIDATA_SUFFIX == 29#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 30#endif#if LIDATA_SUFFIX == 28#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 29#e]ndif#if LIDATA_SUFFIX == 27#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 28#endif#if LIDATA_SUFFIX == 26#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 27#endif#if LIDATA_SUFFIX == 25#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 26#endif#if LIDATA_SUFFIX == 24#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 25#endif#if LIDATA_SUFFIX == 23#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 24#endif#if LIDATA_SUFFIX == 22#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 23#end^if#if LIDATA_SUFFIX == 21#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 22#endif#if LIDATA_SUFFIX == 20#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 21#endif#if LIDATA_SUFFIX == 19#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 20#endif#if LIDATA_SUFFIX == 18#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 19#endif#if LIDATA_SUFFIX == 17#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 18#endif#if LIDATA_SUFFIX == 16#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 17#endif_#if LIDATA_SUFFIX == 15#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 16#endif#if LIDATA_SUFFIX == 14#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 15#endif#if LIDATA_SUFFIX == 13#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 14#endif#if LIDATA_SUFFIX == 12#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 13#endif#if LIDATA_SUFFIX == 11#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 12#endif#if LIDATA_SUFFIX == 10#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 11#endif `#if LIDATA_SUFFIX == 9#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 10#endif#if LIDATA_SUFFIX == 8#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 9#endif#if LIDATA_SUFFIX == 7#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 8#endif#if LIDATA_SUFFIX == 6#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 7#endif#if LIDATA_SUFFIX == 5#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 6#endif#if LIDATA_SUFFIX == 4#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 5#endif#if LIDATA_SaUFFIX == 3#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 4#endif#if LIDATA_SUFFIX == 2#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 3#endif#if LIDATA_SUFFIX == 1#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 2#endif#if LIDATA_SUFFIX == 0#undef LIDATA_SUFFIX#define LIDATA_SUFFIX 1#endifwwZU/*L// *************************************************************************L// * *L// * HP bCONFIDENTIAL. This software is confidential proprietary software *L// * licensed by Hewlett-Packard Development Company, L.P., and is not *L// * authorized to be used, duplicated or disclosed to anyone without the *L// * prior written permission of HP. *L// * *K// * 2015 Copyright Hewlett-Packard Development Company, L.P. *L// * c *L// * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *L// * proprietary software licensed by VMS Software, Inc., and is not *L// * authorized to be used, duplicated or disclosed to anyone without the *L// * prior written permission of VMS Software, Inc. *L// * *K// * 2017 Copyright VMS Software, Inc. *L// * d *L// *************************************************************************//L// *************************************************************************// * *E// * c Copyright 2005 Hewlett-Packard Development Company, L.P. *// * *G// * Confidential computer software. Valid license from HP and/or *E// * its subsidiaries required for possession, use, or copying. *// * e*L// * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, *L// * Computer Software Documentation, and Technical Data for Commercial *K// * Items are licensed to the U.S. Government under vendor's standard *"// * commercial license. *// * *L// * Neither HP nor any of its subsidiaries shall be liable for technical *L// * or editorial errors or omissions contained herein. The information *L// * in this document is provided "as is" without warranfty of any kind and *L// * is subject to change without notice. The warranties for HP products *L// * are set forth in the express limited warranty statements accompanying *L// * such products. Nothing herein should be construed as constituting an *#// * additional warranty. *// * *L// *************************************************************************//// // FACILITY://"// Managed Object support routines//// // ABSTRACT://2// This module contains glgobal definitions for the#// Managed Object support routines.//// // AUTHOR://&// Barry Kierstein Hewlett Packard////-// X-2 BK Barry Kierstein 04-Jun-2017+// Updated copyrights to include VSI text.&// Updated conditionals for x86 port.+// Verified for x86 port - Barry Kierstein//-// X-1 BK Barry Kierstein 30-Sep-2005// Initial version.//*//*// Include files*/H#ifndef MGT_DEBUG_SETTINGS /* Verified for x86 port - Barry Kierstein */h#ifndef MGT_NATIVE_INT64#define MGT_NATIVE_INT64#endif#ifndef MGT_CALLS_64_BIT#define MGT_CALLS_64_BIT#endif'#endif /* #ifndef MGT_DEBUG_SETTINGS *//*// Definitions*/ #ifndef NULL#define NULL (void *)0#endif #ifndef FALSE#define FALSE (0==1)#endif #ifndef TRUE#define TRUE (0==0)#endifN#define NUINT unsigned __int64 /* Verified for x86 port - Barry Kierstein */#define NINT __int64/*//A//// Managed Object registration definitions and routines isection//G// This section defines the items needed for the various registrationB// routines needed to register a Managed Object with the system.*//*// Function prototypes*/int MGT$Register_me6 (char *pMO_obj_name, /* MO object name */9 int MO_minor_obj_num, /* MO object minor ver */9 int MO_major_obj_num, /* MO object major ver */; int (*pMO$MGT_action)(), /* MO action routine */; int (**pRM$MGT_action)(), /* RM action rjoutine */8 int *MO_handle_return, /* RM/MO handles */4 NINT MO_context /* MO context value */ );/*//7//// Integer compression definition and routine section//@// This section defines the items needed for the integer-basedC// compression routines. It is basically a subset of the general-// compression routines in another section.*//* Error statuses */0/* These are less or equal to zero to enable */0/* positive numbers to be a number kof bytes. */:#define MGT$ICOMP_STS_SUCCESS 0 /* Success */E#define MGT$ICOMP_STS_INV_PARAM -1 /* Invalid parameter */N#define MGT$ICOMP_STS_INV_BUFFER_ADDR -2 /* Invalid buffer address */O#define MGT$ICOMP_STS_AT_END_OF_BUFFER -3 /* Output buffer overflow */U#define MGT$ICOMP_STS_INV_BUFFER_CONTENTS -4 /* Contents invalid during get *//*// Structure declarations*/ typedef struct _MGT$ICompContext{ NUINT tempBuffer[2]; NUlINT *pInOutBuffer[2]; int readingBuffer[2]; int bufferLen[2]; int atEndOfBuffer[2]; int bytePos[2]; int origBytes[2]; int compBytes[2]; int bufferBytes[2];F int bufferUnitLength; /* Doesn't need a save context */} MGT$ICompContext;/*// Macro definitions*/4#define MGT$ICOMP_GET_COMP_BYTES(MGT$ICompContext) \$ (MGT$ICompContext->compBytes[0])4#define MGT$ICOMP_GET_ORIG_BYTES(MGT$ICompContext) \m$ (MGT$ICompContext->origBytes[0])4#define MGT$ICOMP_GET_BUFFER_POS(MGT$ICompContext) \3 ((char *)(MGT$ICompContext->pInOutBuffer[0])+ \' (MGT$ICompContext->bytePos[0]) \ )=#define MGT$ICOMP_GET_BUFFER_BYTES_USED(MGT$ICompContext) \& (MGT$ICompContext->bufferBytes[0])%#define MGT$ICOMP_SUCCESS(status) \* ((status == MGT$ICOMP_STS_SUCCESS) \ )5 /* List all "success" statuses. Shouldn't */ /* be very many. *//*// Functionnal prototypes*//* MGT$ICompInitAddContext//// FUNCTIONAL DESCRIPTION://3// This routine initializes an integer compression4// context. This is used when starting to compress#// integers into an output buffer.//// ENVIRONMNET://,// Safe for kernel-mode, no C RTL included.// // INPUTS:///// Arg1 Integer compression context address9// Arg2 Output buffer address. This is assumed to be!// on an NUINT/NINT boundary.7// Arg3 Output buffer length. Tohis will be rounded6// down to the size of an integral number of Arg4.:// Arg4 Size of the unit length for the buffer length.6// This must be a multiple of the size of a NUINT.//// IMPLICIT INPUTS:// // OUTPUTS://!// Return MGT$ICOMP_STS_SUCCESS7// MGT$ICOMP_STS_INV_PARAM Invalid bufferUnitLength//// IMPLICIT OUTPUTS://// SIDE EFFECTS:////*/int MGT$ICompInitAddContext ) (MGT$ICompContext *pMGT$ICompContext, void *pOutputBuffer, p int outputBufferLen, int bufferUnitLength );/* MGT$ICompInitGetContext//// FUNCTIONAL DESCRIPTION://3// This routine initializes an integer compression2// context. This is used when retrieving integer // values from an input buffer.//// ENVIRONMNET://,// Safe for kernel-mode, no C RTL included.// // INPUTS:///// Arg1 Integer compression context address9// Arg2 Output buffer address. This is assumed to be!// on an NUINT/NINT boundary.7//q Arg3 Output buffer length. This will be rounded<// up to the size of an integral number of NUINTs/NINTs.//// IMPLICIT INPUTS:// // OUTPUTS://!// Return MGT$ICOMP_STS_SUCCESS;// MGT$ICOMP_STS_INV_PARAM Invalid bufferUnitLengthD// MGT$ICOMP_STS_INV_BUFFER_ADDR Invalid pOutputBuffer address//// IMPLICIT OUTPUTS://// SIDE EFFECTS:////*/int MGT$ICompInitGetContext ) (MGT$ICompContext *pMGT$ICompContext, void *pOutputBuffer, irnt outputBufferLen, int bufferUnitLength );/* MGT$ICompIAddValues//// FUNCTIONAL DESCRIPTION://9// This routine adds signed integer values to the outputA// buffer. This should be called after MGT$ICompInitAddContext.//// ENVIRONMNET://,// Safe for kernel-mode, no C RTL included.// // INPUTS:///// Arg1 Integer compression context address6// Arg2 Address of signed integer value(s) to add.0// Adding multiple integers assumes that the,// int segers are in consecutive addresses5// (e.g. an array or adjacent fields in a struct)'// Arg3 Length of signed integer(s).// Arg4 Number of signed integer(s) to add//// IMPLICIT INPUTS:// // OUTPUTS://M// Return Successful completion Number of bytes used in the output bufferU// Unsuccessful completion MGT$ICOMP_STS_INV_PARAM, invalid unit length parameterA// MGT$ICOMP_STS_INV_BUFFER_ADDR, address not NINT aligned@// MGT$ICOMP_STS_AT_END_OF_BUFFER t, output buffer overflow//5// Note: MGT$ICOMP_STS_AT_END_OF_BUFFER return statusA// This indicates that the output buffer is full and that itC// is possible that the end of the output buffer might containC// a compressed integer that is incomplete. It is recommendedE// that the caller save a "last good known buffer position" thatE// makes sense (e.g. last compressed integer, last good "record"// of data, etc).D// So that the caller doesn't have to cuheck the status at everyC// call, once the buffer is full, the routine will safely keep-// returning the buffer overflow status.//// IMPLICIT OUTPUTS://// SIDE EFFECTS:////*/int MGT$ICompIAddValues) (MGT$ICompContext *pMGT$ICompContext, void *pValueAddr, int unitLen, int numUnits );/* MGT$ICompUIAddValues//// FUNCTIONAL DESCRIPTION://;// This routine adds unsigned integer values to the outputA// buffer. This should be cavlled after MGT$ICompInitAddContext.//// ENVIRONMNET://,// Safe for kernel-mode, no C RTL included.// // INPUTS:///// Arg1 Integer compression context address8// Arg2 Address of unsigned integer value(s) to add.0// Adding multiple integers assumes that the,// integers are in consecutive addresses5// (e.g. an array or adjacent fields in a struct))// Arg3 Length of unsigned integer(s)0// Arg4 Number of unsigned integer(s) to add//// IMPLICIT INPUTS w:// // OUTPUTS://M// Return Successful completion Number of bytes used in the output bufferU// Unsuccessful completion MGT$ICOMP_STS_INV_PARAM, invalid unit length parameterB// MGT$ICOMP_STS_INV_BUFFER_ADDR, address not NUINT aligned@// MGT$ICOMP_STS_AT_END_OF_BUFFER, output buffer overflow//5// Note: MGT$ICOMP_STS_AT_END_OF_BUFFER return statusA// This indicates that the output buffer is full and that itC// is possible that the end of the output bufxfer might containC// a compressed integer that is incomplete. It is recommendedE// that the caller save a "last good known buffer position" thatE// makes sense (e.g. last compressed integer, last good "record"// of data, etc).D// So that the caller doesn't have to check the status at everyC// call, once the buffer is full, the routine will safely keep-// returning the buffer overflow status.//// IMPLICIT OUTPUTS://// SIDE EFFECTS:////*/yint MGT$ICompUIAddValues) (MGT$ICompContext *pMGT$ICompContext, void *pValueAddr, int unitLen, int numUnits );/* MGT$ICompIGetValues//// FUNCTIONAL DESCRIPTION://9// This routine retrieves signed integer values from theG// input buffer. This should be called after MGT$ICompInitGetContext.//// ENVIRONMNET://,// Safe for kernel-mode, no C RTL included.// // INPUTS:///// Arg1 Integer compression context address?// Arg2 Address ofz signed integer value(s) for destination.4// Retrieving multiple integers assumes that the,// integers are in consecutive addresses5// (e.g. an array or adjacent fields in a struct)'// Arg3 Length of signed integer(s)7// Arg4 Number of signed integer(s) for destination//// IMPLICIT INPUTS:// // OUTPUTS://$// Return MGT$ICOMP* return status// MGT$ICOMP_STS_SUCCESS:// MGT$ICOMP_STS_INV_PARAM, invalid unit length parameter<// MGT$ICOMP_STS_INV_BUFFER_ADD{R, address not NUINT aligned:// MGT$ICOMP_STS_AT_END_OF_BUFFER, at end of input bufferI// MGT$ICOMP_STS_INV_BUFFER_CONTENTS, error interpreting buffer contents//// IMPLICIT OUTPUTS://// SIDE EFFECTS:////*/int MGT$ICompIGetValues) (MGT$ICompContext *pMGT$ICompContext, void *pValueAddr, int unitLen, int numUnits );/* MGT$ICompUIGetValues//// FUNCTIONAL DESCRIPTION://;// This routine retrieves unsigned integer values from theG// inpu|t buffer. This should be called after MGT$ICompInitGetContext.//// ENVIRONMNET://,// Safe for kernel-mode, no C RTL included.// // INPUTS:///// Arg1 Integer compression context addressA// Arg2 Address of unsigned integer value(s) for destination.4// Retrieving multiple integers assumes that the,// integers are in consecutive addresses5// (e.g. an array or adjacent fields in a struct))// Arg3 Length of unsigned integer(s)9// Arg4 Number of unsigned} integer(s) for destination//// IMPLICIT INPUTS:// // OUTPUTS://$// Return MGT$ICOMP* return status// MGT$ICOMP_STS_SUCCESS:// MGT$ICOMP_STS_INV_PARAM, invalid unit length parameter<// MGT$ICOMP_STS_INV_BUFFER_ADDR, address not NUINT aligned:// MGT$ICOMP_STS_AT_END_OF_BUFFER, at end of input bufferI// MGT$ICOMP_STS_INV_BUFFER_CONTENTS, error interpreting buffer contents//// IMPLICIT OUTPUTS://// SIDE EFFECTS:////*/int MGT$ICompUIGetValues) (MGT$ICompCo~ntext *pMGT$ICompContext, void *pValueAddr, int unitLen, int numUnits );/* MGT$ICompSaveState//// FUNCTIONAL DESCRIPTION://8// This routine saves the current state of the context.:// This is useful for recording a safe place to roll back7// to if the next operations could overflow the output;// buffer. Use in conjunction with MGT$ICompRestoreState.8// This should be called after MGT$ICompInitAddContext/5// MGT$ICompInitGetContext and MGT$ICompUIAddValues/// MGT$ICompIAddValues.//// ENVIRONMNET://,// Safe for kernel-mode, no C RTL included.// // INPUTS:///// Arg1 Integer compression context address//// IMPLICIT INPUTS:// // OUTPUTS://// IMPLICIT OUTPUTS://// SIDE EFFECTS://*/void MGT$ICompSaveState( (MGT$ICompContext *pMGT$ICompContext );/* MGT$ICompRestoreState//// FUNCTIONAL DESCRIPTION://D// This routine restores the previously saved state of the context.:// This is useful for rolling back to a safe place if the:// output buffer has overflowed. Use in conjunction with// MGT$ICompSaveState.8// This should be called after MGT$ICompInitAddContext/5// MGT$ICompInitGetContext and MGT$ICompUIAddValues/// MGT$ICompIAddValues.//6// Note: When the context is initialized, the saved1// context is set so that any further integer(// compressions done will return the,// MGT$ICOMP_STS_INV_BUFFER_ADDR status.//// ENVIRONMNET://,// Safe for kernel-mode, no C RTL included.// // INPUTS:///// Arg1 Integer compression context address//// IMPLICIT INPUTS:// // OUTPUTS://// IMPLICIT OUTPUTS://// SIDE EFFECTS://*/void MGT$ICompRestoreState( (MGT$ICompContext *pMGT$ICompContext );/* MGT$ICompFinishComp//// FUNCTIONAL DESCRIPTION://8// This routine does whatever is necessary to make sure:// the output buffer has all the compressed data, and any7// other needed cleanup or processing.  This should be@// called after MGT$ICompInitAddContext/MGT$ICompInitGetContext1// and MGT$ICompUIAddValues/MGT$ICompIAddValues.//// ENVIRONMNET://,// Safe for kernel-mode, no C RTL included.// // INPUTS:///// Arg1 Integer compression context address//// IMPLICIT INPUTS:// // OUTPUTS://5// Return Number of bytes used in the output buffer//// IMPLICIT OUTPUTS://5// Output buffer position in the compression context7// is updated to be the first quadword aligned address#// after the last compressed byte.//// SIDE EFFECTS://*/int MGT$ICompFinishComp( (MGT$ICompContext *pMGT$ICompContext );wwNZU/*L// *************************************************************************L// * *L// * HP CONFIDENTIAL. This software is confidential proprietary software *L// * licensed by Hewlett-Packard Development Company, L.P., and is not *L// * authorized to be used, duplicated or disclosed to anyone without the *L// * prior written permission of HP. *L// * *K// * 2015 Copyright Hewlett-Packard Development Company, L.P. *L// * *L// * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *L// * proprietary software licensed by VMS Software, Inc., and is not *L// * authorized to be used, duplicated or disclosed to anyone without the *L// * prior written permission of VMS Software, Inc. *L// * *K// * 2019 Copyright VMS Software, Inc. *L// * *L// *************************************************************************//// // FACILITY://// OpenVMS System C libraries//// // ABSTRACT://D// This module contains definitions used for Managed Objects written// in C.//>// This module assumes that MGTHDR.H has already been included// in the C source module.// // // AUTHOR://&// Barry Kierstein Hewlett Packard////// REVISION HISTORY://-// X-4 bw Bob Wilson 18-Apr-2019+// Make MGT_NATIVE_INT64 for x86_64 = ia64//-// X-3 BK Barry Kierstein 04-Jun-2017+// Updated copyrights to include VSI text.&// Updated conditionals for x86 port.+// Verified for x86 port - Barry Kierstein//-// X-2 BK Barry Kierstein 06-Dec-20058// Correct spelling of MGT$K_STS_CONT_DATA_CTX_NOT_FND.//-// X-1 BK Barry Kierstein 30-Sep-2005// Initial version.//*//*// Macro definitions*/5/* Define this macro if V2 MGT headers are used *//* #define MGTV2_DEFS */</* Define this macro if MGT header V1 behavior is needed */#/* #define MGT_V1_HDR_COMPATIBLE *//*!// Machine architecture settings*/#ifndef MGT_DEBUG_SETTINGS #ifdef __VMS#ifdef __ALPHA#ifndef MGT_NATIVE_INT64I#define MGT_NATIVE_INT64 /* Architecture has native 64 bit integers */#endif#ifndef MGT_CALLS_64_BITF#define MGT_CALLS_64_BIT /* Architecture has native 64 bit calls */#endif#elif __ia64 || __x86_64#ifndef MGT_NATIVE_INT64I#define MGT_NATIVE_INT64 /* Architecture has native 64 bit integers */#endif#ifndef MGT_CALLS_64_BITF#define MGT_CALLS_64_BIT /* Architecture has native 64 bit calls */#endif#else /* VAX */#endif /* #ifdef __ALPHA */#else /* #ifdef __VMS */#ifndef MGT_NATIVE_INT64I#define MGT_NATIVE_INT64 /* Architecture has native 64 bit integers */#endif#ifndef MGT_CALLS_64_BITF#define MGT_CALLS_64_BIT /* Architecture has native 64 bit calls */#endif#endif /* #ifdef __VMS */(#endif /* #ifndef MGT_DEBUG_SETTINGS */#ifdef MGT_VERBOSE_MSG#ifdef MGT_NATIVE_INT64+#pragma message ("MGT_NATIVE_INT64 is set")#else/#pragma message ("MGT_NATIVE_INT64 is not set")#endif#ifdef MGT_CALLS_64_BIT+#pragma message ("MGT_CALLS_64_BIT is set")#else/#pragma message ("MGT_CALLS_64_BIT is not set")#endif%#endif /* #ifdef MGT_VERBOSE_MSG *//*// Type definitions*/typedef int MGT_I32;!typedef unsigned int MGT_U32;#ifdef MGT_NATIVE_INT64typedef __int64 MGT_I64;$typedef unsigned __int64 MGT_U64;#endif/* // OpenVMS status testing macro*/#ifndef VMS_SUCCESS+#define VMS_SUCCESS(status) (status & 0x01)#endif/* // C Macros for Managed Objects*//*4// Note: Since various macros define code blocks,-// all variables local to the code blocks-// must be unique to avoid variable scope/// problems when various macros are nested.*/##define MGT_SUCCESS(status) \, ((status == MGT$K_STS_SUCCESS) || \5 (status == MGT$K_STS_CONT_DATA_CTX_FOUND_W) || \5 (status == MGT$K_STS_CONT_DATA_CTX_FOUND_E) || \5 (status == MGT$K_STS_CONT_DATA_CTX_NOT_FND) \ )5 /* List all "success" statuses. Shouldn't */ /* be very many. *//*(// Copy ASCIZ field to fixed-size field//9// This macro will copy an ASCIZ string to a fixed-sized6// field. If the ASCIZ field length is less than the;// fixed-sized field, the fixed-sized field will be padded7// with '\0' characters. If the ASCIZ field is larger7// than the fixed-sized field, the copy will only copy:// the characters that will fit in the fixed-sized field.//// Parameters://-// src Address of the character field for the// source ASCIZ string..// dest Address of the character field for the*// destination (ASCIZ string, padded with// '\0' characters as needed).*// len Length of the Dest character field.*/0#define MGT_COPY_ASCIZ_TO_FIXED_FIELD(src, \ dest, \ len) \ { \ register int MGTAZindex; \& register int MGTAZslen = len; \& register int MGTAZlen = len; \. register char *MGTAZsrc = (char *)src; \. register char *MGTAZdest = (char *)dest; \ \ /* Copy string */ \ for (MGTAZindex = 0; \# MGTAZindex < MGTAZlen; \ MGTAZindex++) \ { \% MGTAZdest[MGTAZindex] = \ MGTAZsrc[MGTAZindex]; \, if (MGTAZsrc[MGTAZindex] == '\0') \ { \# MGTAZslen = MGTAZindex+1; \ break; \ } \ } \ \$ /* Null out remain space */ \$ for (MGTAZindex = MGTAZslen; \# MGTAZindex < MGTAZlen; \ MGTAZindex++) \ { \* MGTAZdest[MGTAZindex] = '\0'; \ } \ }/*"// Copy Managed Object name macro//7// This macro will make a copy of the Managed Object's // name.//4// The correct fo rmat for the registration database7// is an ASCIZ string, with all the bytes in the field2// after the trailing null set to null. However,3// a previous specification allowed input as ASCIC2// string for V1.1 and V1.2 parameter section of 3// Management Registration Requests. For V2.1 and4// above versions of the parameter section, this is// not supported.1// By default, this macro treats the object name,// as an ASCIZ field, in line with the V2.*// specification.-// To s upport the V1.* specification, define8// MGT_V1_HDR_COMPATIBLE. This will the ASCIC or ASCIZ1// object names. This mode tests the first byte4// of the object name. If it is less than 32, then6// it is treated as the count byte in an ASCIC field.//// Parameters://-// src Address of the character field for the)// source ASCIZ string (ASCIC string for-// legacy Management Registration requests)..// dest Address of the character field for the*// destination (ASCIZ string, padded with*// '\0' characters as needed). Character!// field length must be at least&// MGTRQV2$K_OBJ_NAME_LEN characters.*/#ifdef MGT_V1_HDR_COMPATIBLE/*2// Make a basic assumption that if the first byte0// is unprintable (less than a space), then the// name is in ASCIC format.*/!#if MGTHDR$K_OBJ_NAME_LEN-1 >= 324#error MGTHDR$K_OBJ_NAME_LEN is larger than 32 bytes#endif4#if MGTKRGIN$K_OBJ_NAME_LEN != MGTHDR$K_OBJ_NAME_LEN7#error MGTKRGIN$K_OBJ_NAME_LEN != MGTHDR$K_OBJ_NAME_LEN#endif*#define MGT_COPY_OBJ_NAME(src,dest) \ { \ int MGTclen; \& char *MGTcsrc = (char *)src; \' char *MGTcdest = (char *)dest; \ \. if (MGTcsrc[0] <(MGTHDR$K_OBJ_NAME_LEN-1)) \ { \! MGTclen = MGTcsrc[0]; \ MGTcsrc++; \ } \ else \ { \+ MGTclen = MGTHDR$K_OBJ_NAME_LEN; \ } \ \ /* Copy string */ \% MGT_COPY_ASCIZ_TO_FIXED_FIELD \( (MGTcsrc, MGTcdest, MGTclen); \ }#else*#define MGT_COPY_OBJ_NAME(src,dest) \ { \ /* Copy string */ \% MGT_COPY_ASCIZ_TO_FIXED_FIELD \ (MGTcsrc, MGTcdest, \" MGTHDR$K_OBJ_NAME_LEN \ ); \ }#endif/*.// Return the maximum packet data length that// the packet can describe//// Parameters://(// pMgtHdr Management Header address//*/5#define MGT_GET_MGT_PACKET_DATA_LEN_MAX(pMgtHdr) \5 (((MGTHDR *)pMgtHdr)->mgthdr$b_hdr_major == 1 ? \ 0xF8 : \ 0xFF * sizeof(MGT_U64) \ )/*2// Rounds up the data length to the next quadword//// Parameters://// len Length to align//*/'#define MGT_QW_ALIGN_LENGTH(len) \ ((len + 7) & ~0x07) \/*'// Find length of a Management header.//// Parameters://(// pMgtHdr Management Header address//*/4#define MGT_GET_MGT_PACKET_HEADER_LEN(pMgtHdr) \+ (((MGTHDR *)pMgtHdr)->mgthdr$b_hdr_len)/*1// Find length of a Management packet data area./// This is the data only, and does not include(// the area described by an EOD header.//// Parameters://(// pMgtHdr Management Header address//*/2#define MGT_GET_MGT_PACKET_DATA_LEN(pMgtHdr) \5 (((MGTHDR *)pMgtHdr)->mgthdr$b_hdr_major == 1 ? \. ((MGTHDR *)pMgtHdr)->mgthdr$w_par_len : \. ((MGTHDR *)pMgtHdr)->mgthdr$w_par_len * \ sizeof(MGT_U64) \ )/*'// Find length of a Management packet.//3// This macro will return the length of the header// and its data.//// Parameters://(// pMgtHdr Management Header address//*/.#define MGT_GET_MGT_PACKET_LEN(pMgtHdr) \3 (MGT_GET_MGT_PACKET_HEADER_LEN(pMgtHdr) + \/ MGT_GET_MGT_PACKET_DATA_LEN(pMgtHdr) \ )/*7// Set the length of a Management packet data section.//1// This macro accepts the address of the initial6// packet header and the length of the data in bytes.6// The length will be aligned up to the next quadword // boundary.//// Parameters://(// pMgtHdr Management Header address1// len Management Packet data length in bytes//*/5#define MGT_SET_MGT_PACKET_DATA_LEN(pMgtHdr,len) \ { \, ((MGTHDR *)pMgtHdr)->mgthdr$w_par_len = \" (((MGTHDR *)pMgtHdr)-> \! mgthdr$b_hdr_major == 1 ? \" MGT_QW_ALIGN_LENGTH(len) : \ MGT_QW_ALIGN_LENGTH \# (len) / sizeof(MGT_U64) \ ); \ }/*-// Set the length of a Management packet. A.// packet consists of a Management header and// related data, if any.//6// The length will be aligned up to the next quadword // boundary.//// Parameters://(// pMgtHdr Management Header address,// len Management Packet length in bytes//*/1#define MGT_SET_MGT_PACKET_LEN(pMgtHdr,len) \ { \# MGT_SET_MGT_PACKET_DATA_LEN \ (pMgtHdr, \ (len - \# ((MGTHDR *)pMgtHdr)-> \ mgthdr$b_hdr_len) \ ); \ }/*6// Compute and set the length of a Management packet.0// A packet consists of a Management header and// related data, if any.//1// This macro accepts the address of the initial-// packet header and the address of the next/// available byte after the end of the packet.-// It will compute the length of the packet,.// and set the length of the packet data area// appropriately.//1// The computed length will be aligned up to the// next quadword boundary.//// Parameters://(// pMgtHdr Management header address,// pNextByte Next available byte after the$// end of the Management packet//*/5#define MGT_FIND_AND_SET_MGT_PACKET_LEN(pMgtHdr, \ pNextByte) \ { \ MGT_SET_MGT_PACKET_LEN \ (pMgtHdr, \. ((char *)pNextByte - (char *)pMgtHdr) \ ); \ }/*0// Find address of Management parameter section//-// This macro will return the address of the0// parameter section for the Management packet.//// Parameters://(// pMgtHdr Management Header address//*/.#define MGT_GET_MGT_PARAM_ADDR(pMgtHdr) \ ( \ (char *) \ ((char *)pMgtHdr + \. MGT_GET_MGT_PACKET_HEADER_LEN(pMgtHdr) \ ) \ )/**// Find address of next Management header//3// This macro will return the address of where the$// next Management header would be.*// It assumes that all Management packets // are adjacent to one another.//// Parameters://(// pMgtHdr Management Header address//*/0#define MGT_GET_NEXT_MGT_HDR_ADDR(pMgtHdr) \ ( \ (void *) \ ((char *)pMgtHdr + \+ MGT_GET_MGT_PACKET_LEN(pMgtHdr) \ ) \ )/*-// Find address of the EOD Management header//-// This macro will return the address of the"// EOD Management header or NULL.// *// It assumes that all Management packets // are adjacent to one another.//// Parameters://-// pMgtHdr Management Header address of a// main Management packet//*/-#define MGT_GET_MGT_EOD_ADDR(pMgtHdr) \ ( \6 (((MGTHDR *)pMgtHdr)->mgthdr$b_hdr_major <= 2 ? \ ((void *) \/ (((MGTHDRV2 *)pMgtHdr)->mgthdrv2$v_eod ? \/ MGT_GET_NEXT_MGT_HDR_ADDR(pMgtHdr) : \ NULL \ ) \ ) : \ NULL \ ) \ )/*0// Find the length of the EOD Management packet//,// This macro will return the length of the,// EOD Management packet or 0 if the packet// doesn't exist.// )// It assumes that all Management packet%// sets are adjacent to one another.*/2#define MGT_GET_MGT_EOD_PACKET_LEN(pMgtHdr) \ ( \6 (((MGTHDR *)pMgtHdr)->mgthdr$b_hdr_major <= 2 ? \3 (((MGTHDRV2 *)pMgtHdr)->mgthdrv2$v_eod ? \ MGT_GET_MGT_PACKET_LEN \/ (MGT_GET_NEXT_MGT_HDR_ADDR(pMgtHdr)) : \ 0 \ ) : \ 0 \ ) \ )/*1// Get the length of the parameter buffer of the2// MO header. If there is an EOD record, then the-// parameter buffer length is the sum of the1// parameter data length, the EOD header length,.// and the parameter data length described by// the EOD header.*/3#define MGT_GET_MGT_PACKET_PARAM_LEN(pMgtHdr) \ ( \( MGT_GET_MGT_PACKET_LEN(pMgtHdr) - \. MGT_GET_MGT_PACKET_HEADER_LEN(pMgtHdr) + \* MGT_GET_MGT_EOD_PACKET_LEN(pMgtHdr) \ )/*2// Find address of Management continuation header//:// This macro will return the address of the continuation9// header, else it will return NULL if it doesn't exist.*/.#define MGT_GET_MGT_CONT_ADDR(pMgtHdr) \ ( \ (void *) \6 (((MGTHDR *)pMgtHdr)->mgthdr$v_continuation ? \ MGT_GET_MGT_CONT_ADDR2 \/ (MGT_GET_NEXT_MGT_HDR_ADDR(pMgtHdr) \ ) : \ NULL \ ) \ )/#define MGT_GET_MGT_CONT_ADDR2(pMgtHdr) \ ( \ (void *) \6 (((MGTHDR *)pMgtHdr)->mgthdr$v_continuation ? \, MGT_GET_NEXT_MGT_HDR_ADDR(pMgtHdr) : \ pMgtHdr \ ) \ )/*9// Find the length of the Management continuation packet//9// This macro will return the length of the continuation6// header, else it will return 0 if it doesn't exist.*//#define MGT_GET_MGT_CONT_PACKET_LEN(pMgtHdr) \ ( \0 (((MGTHDR *)pMgtHdr)->mgthdr$v_continuation ? \ MGT_GET_MGT_PACKET_LEN \$ (MGT_GET_MGT_CONT_ADDR(pMgtHdr) \ ) : \ 0 \ ) \ )/*.// Find the length of a Management packet set//6// This macro will return the length of a packet set.2// This macro assumes that the header information// has been validated.*/1#define MGT_GET_MGT_PACKET_SET_LEN(pMgtHdr) \ ( \, MGT_GET_MGT_PACKET_LEN(pMgtHdr) + \, MGT_GET_MGT_EOD_PACKET_LEN(pMgtHdr) + \+ MGT_GET_MGT_CONT_PACKET_LEN(pMgtHdr) \ )/*.// Find address of next Management packet set//3// This macro will return the address of where the(// next Management packet set would be.2// It assumes that all Management header and data%// sets are adjacent to one another.*/5#define MGT_GET_NEXT_MGT_PACKET_SET_ADDR(pMgtHdr) \ ( \ (void *) \ ((char *)pMgtHdr + \. MGT_GET_MGT_PACKET_SET_LEN(pMgtHdr) \ ) \ )/*// Copy quadword block macro//-// This will copy a block of quadwords. For+// machine architectures that are longword1// oriented, this will copy by longword instead.//6// This macro assumes that the source and destination// are quadword aligned.*/#ifdef MGT_NATIVE_INT64/#define MGT_COPY_QW_BLOCK(pSrc,pDest,len) \ { \! register int MGTCQWindex; \% register __int64 *MGTCQWsrc = \ (__int64 *)pSrc; \% register __int64 *MGTCQWdest = \ (__int64 *)pDest; \& register int MGTCQWlen = len; \ \ for (MGTCQWindex = 0; \) MGTCQWindex < (MGTCQWlen>>3); \ MGTCQWindex++) \ { \% MGTCQWdest[MGTCQWindex] =  \ MGTCQWsrc[MGTCQWindex]; \ } \ }#else/#define MGT_COPY_QW_BLOCK(pSrc,pDest,len) \ { \! register int MGTCQWindex; \+ register int *MGTCQWsrc = (int *)pSrc; \+ register int *MGTCQWdest= (int *)pDest; \' register int MGTCQWlen = len; \ \ for (MGTCQWindex = 0; \) MGTCQWindex < (MGTCQWlen>>2); \ MGTCQWindex++) \ { \% MGTCQWdest[MGTCQWindex] = \ MGTCQWsrc[MGTCQWindex]; \ } \ }#endif/*// Copy MO header macro//)// This will copy a Management header to2// a destination. It is basically a memory copy,+// but it is here for a number of reasons://-// 1) It obtains the length to copy from the// packet itself.0// 2) This assumes that the buffers are aligned+// on a quadword boundary, and is optimized // for that.0// 3) Since this code is also used on VAX where+// some of the standard C functions are not+// available, this can be tailored for each&// architecture on which OpenVMS runs.//,// The next available byte parameter is the.// address of the field that will receive the0// address of the next available byte. If this// parameter is equal to NULL,&// then this address is not returned.*/+#define MGT_COPY_MGT_HEADER(pSrcHdr, \ pDestHdr, \ ppNextByte) \ { \" register int MGTCHDlen = \. MGT_GET_MGT_PACKET_HEADER_LEN(pSrcHdr); \  \ MGT_COPY_QW_BLOCK \( (pSrcHdr,pDestHdr,MGTCHDlen); \ \ if (ppNextByte != NULL) \ { \, char **MGTCHDptr = ppNextByte; \ *MGTCHDptr = \' (char *)(pDestHdr) + MGTCHDlen; \ } \ }/*#// Copy MO header macro with check//.// This macro will check to see if the length2// of the MO header will fit in the buffer before+// attempting the copy. The return status0// determines whether the copy happened or not.//,// The next available byte parameter is the.// address of the field that will receive the0// address of the next available byte. If this// parameter is equal to NULL,&// then this address is not returned.*/2#define MGT_COPY_MGT_HEADER_WITH_CHECK(pSrcHdr, \ pDestHdr, \ bufLen, \ retStatus, \ ppNextByte) \ { \0 if (MGT_GET_MGT_PACKET_HEADER_LEN(pSrcHdr) <= \ bufLen) \ { \ MGT_COPY_MGT_HEADER \# (pSrcHdr,pDestHdr,ppNextByte); \& retStatus = MGT$K_STS_SUCCESS; \ } \ else \ { \) retStatus = MGT$K_STS_RSP_NO_ROOM; \ } \ }/*// Copy MO packet macro//)// This will copy a Management packet to2// a destination. It is basically a memory copy,+// but it is here for a number of reasons://-// 1) It obtains the length to copy from the// packet itself.0// 2) This assumes that the buffers are aligned+// on a quadword boundary, and is optimized // for that.0// 3) Since this code is also used on VAX where+// some of the standard C functions are not+// available, this can be tailored for each&// architecture on which OpenVMS runs.//4// The address for the next MGTHDR parameter is the.// address of the field that will receive the0// address for the next MGTHDR header. If this// parameter is equal to NULL,&// then this address is not returned.*/+#define MGT_COPY_MGT_PACKET(pSrcHdr, \ pDestHdr, \ ppNextHdr) \ { \" register int MGTCPKlen = \+ MGT_GET_MGT_PACKET_LEN(pSrcHdr); \ \ MGT_COPY_QW_BLOCK \( (pSrcHdr,pDestHdr,MGTCPKlen); \ \ if (ppNextHdr != NULL) \ { \+ MGTHDR **MGTCPKptr = ppNextHdr; \ *MGTCPKptr = \ (MGTHDR *) \' ((char *)(pDestHdr) +MGTCPKlen); \ } \ }/*#// Copy MO packet macro with check//.// This macro will check to see if the length2// of the MO packet will fit in the buffer before+// attempting the copy. The return status0// determines whether the copy happened or not.//4// The address for the next MGTHDR parameter is the.// address of the field that will receive the0// address for the next MGTHDR header. If this// parameter is equal to NULL,&// then this address is not returned.*/5#define MGT_COPY_MGT_PACKET_WITH_CHECK(pSrcHdr, \ pDestHdr, \ bufLen, \ retStatus, \ ppNextHdr) \ { \- if (MGT_GET_MGT_PACKET_LEN(pSrcHdr) <= \ bufLen) \ { \ MGT_COPY_MGT_PACKET \% (pSrcHdr,pDestHdr,ppNextHdr); \) retStatus = MGT$K_STS_SUCCESS; \ } \ else \ { \, retStatus = MGT$K_STS_RSP_NO_ROOM; \ } \ }/*// Replace MO packet macro//.// This macro will check to see if the length/// of the new MO packet will fit in the buffer/// space of the old one before attempting the .// replacement. The return status determines,// whether the replacement happened or not.//4// The address for the next MGTHDR parameter is the.// address of the field that will receive the0// address for the next MGTHDR header. If this// parameter is equal to NULL,&// then this address is not returned.*/.#define MGT_REPLACE_MGT_PACKET(pSrcHdr, \ pDestHdr, \ retStatus, \ ppNextHdr) \ { \ int srcLen = \+ MGT_GET_MGT_PACKET_LEN(pSrcHdr); \ int destLen = \, MGT_GET_MGT_PACKET_LEN(pDestHdr); \ \ if (srcLen == destLen) \ { \ MGT_COPY_MGT_PACKET \% (pSrcHdr,pDestHdr,ppNextHdr); \) retStatus = MGT$K_STS_SUCCESS; \ } \ else \ { \, retStatus = MGT$K_STS_RSP_NO_ROOM; \ } \ }/*// Copy MO packet set macro//-// This will copy a Management packet set to2// a destination. It is basically a memory copy,+// but it is here for a number of reasons://-// 1) It obtains the length to copy from the// packet set itself.0// 2) This assumes that the buffers are aligned+// on a quadword boundary, and is optimized // for that.0// 3) Since this code is also used on VAX where+// some of the standard C functions are not+// available, this can be tailored for each&// architecture on which OpenVMS runs.//4// The address for the next MGTHDR parameter is the.// address of the field that will receive the0// address for the next MGTHDR header. If this// parameter is equal to NULL,&// then this address is not returned.*/.#define MGT_COPY_MGT_PACKET_SET(pSrcHdr, \ pDestHdr, \ ppNextHdr) \ { \" register int MGTCSTlen = \. MGT_GET_MGT_PACKET_SET_LEN(pSrcHdr);  \ \ MGT_COPY_QW_BLOCK \( (pSrcHdr,pDestHdr,MGTCSTlen); \ \ if (ppNextByte != NULL) \ { \, char **MGTCSTptr = ppNextByte; \ *MGTCSTptr = \' (char *)(pDestHdr) + MGTCSTlen; \ } \ }/*'// Copy MO packet set macro with check//.// This macro will check to see if the length6// of the MO packet set will fit in the buffer before+// attempting the copy. The return status0// determines whether the copy happened or not.//4// The address for the next MGTHDR parameter is the.// address of the field that will receive the0// address for the next MGTHDR header. If this// parameter is equal to NULL,&// then this address is not returned.*/5#define MGT_COPY_MGT_PACKET_SET_WITH_CHECK(pSrcHdr, \ pDestHdr, \ bufLen, \ retStatus, \ ppNextHdr) \ { \- if (MGT_GET_MGT_PACKET_SET_LEN(pSrcHdr) <= \ bufLen) \ { \ MGT_COPY_MGT_PACKET_SET \" (pSrcHdr,pDestHdr,ppNextHdr); \& retStatus = MGT$K_STS_SUCCESS; \ } \ else \ { \) retStatus = MGT$K_STS_RSP_NO_ROOM; \ } \ }/*=// Initialize V1.1 MO response from a V1.1 MO request header//3// This macro will carry over the fields that need8// to be copied from the MO request to the MO response.*/2#define MGT_COPY_V1_1_MGT_REQUEST_INFO(pSrcHdr, \ pDestHdr) \ { \- MGTHDR *pCMRI11SrcHdr = (MGTHDR *)pSrcHdr; \/ MGTHDR *pCMRI11DestHdr = (MGTHDR *)pDestHdr; \ \( pCMRI11DestHdr->mgthdr$l_obj_handle = \+ pCMRI11SrcHdr->mgthdr$l_obj_handle; \, pCMRI11DestHdr->mgthdr$l_src_obj_handle = \. pCMRI11SrcHdr->mgthdr$l_src_obj_handle; \( pCMRI11DestHdr->mgthdr$l_action_seq = \+ pCMRI11SrcHdr->mgthdr$l_action_seq; \% pCMRI11DestHdr->mgthdr$b_action = \' pCMRI11SrcHdr->mgthdr$b_action; \ }/*=// Initialize V2.1 MO response from a V2.1 MO request header//3// This macro will carry over the fields that need8// to be copied from the MO request to the MO response.*/2#define MGT_COPY_V2_1_MGT_REQUEST_INFO(pSrcHdr, \ pDestHdr) \ { \1 MGTHDRV2 *pCMRI21SrcHdr = (MGTHDRV2 *)pSrcHdr; \2 MGTHDRV2 *pCMRI21DestHdr= (MGTHDRV2 *)pDestHdr; \ \. pCMRI21DestHdr->mgthdrv2$l_obj_handle = \, pCMRI21SrcHdr->mgthdrv2$l_obj_handle; \0 pCMRI21DestHdr->mgthdrv2$l_src_obj_handle = \0 pCMRI21SrcHdr->mgthdrv2$l_src_obj_handle; \. pCMRI21DestHdr->mgthdrv2$l_action_seq = \, pCMRI21SrcHdr->mgthdrv2$l_action_seq; \* pCMRI21DestHdr->mgthdrv2$b_action = \) pCMRI21SrcHdr->mgthdrv2$b_action; \ }/*1// Initialize MO response from MO request header//3// This macro will carry over the fields that need8// to be copied from the MO request to the MO response.*/-#define MGT_COPY_MGT_REQUEST_INFO(pSrcHdr, \ pDestHdr) \ { \+ MGTHDR *pCMRISrcHdr = (MGTHDR *)pSrcHdr; \- MGTHDR *pCMRIDestHdr = (MGTHDR *)pDestHdr; \ \, if (pCMRISrcHdr->mgthdr$b_hdr_major <= 2) \ { \& MGT_COPY_V2_1_MGT_REQUEST_INFO \ (pSrcHdr, pDestHdr); \ } \ else \ { \& MGT_COPY_V1_1_MGT_REQUEST_INFO \ (pSrcHdr, pDestHdr); \ } \ }/*%// Create a MO V1.1 compliant header//2// This macro will initialize a MO V1.1 compliant$// header at the address specified.*/#ifdef MGT_NATIVE_INT641#define MGT_CREATE_V1_1_MGT_HEADER(pMgtHdr, \ hdrType, \ destMOID, \ srcMOID, \ actionCode, \ paramMajVer, \ paramMinVer, \ actionCtx, \ ppNextByte) \ { \3 MGT_U64 *pQWV11Hdr = (MGT_U64 *) pMgtHdr; \ \ pQWV11Hdr[0] = \- ((MGT_U64)(MGTHDR$K_ACT_HDR_V1_1_LEN)) + \% ((MGT_U64)(MGTHDR$M_V) << 8) + \ ((MGT_U64)(0x01) << 16) + \ ((MGT_U64)(0x01) << 24) + \" ((MGT_U64)(hdrType) << 32) + \- ((MGT_U64)(MGT$K_STS_RESERVED) << 40); \ pQWV11Hdr[1] = \ ((MGT_U64)(destMOID)) + \# ((MGT_U64)(srcMOID) << 32); \ pQWV11Hdr[2] = \ ((MGT_U64)(actionCode)) + \& ((MGT_U64)(paramMinVer) << 16) + \& ((MGT_U64)(paramMajVer) << 24) + \% ((MGT_U64)(actionCtx) << 32); \ \# if (ppNextByte != NULL) \ { \& char **MGTC11Hptr = ppNextByte; \ *MGTC11Hptr = \$ (char *)&(pQWV11Hdr[3]); \ } \}#else1#define MGT_CREATE_V1_1_MGT_HEADER(pMgtHdr, \ hdrType, \ destMOID, \ srcMOID, \ actionCode, \ paramMajVer, \ paramMinVer, \ actionCtx, \ ppNextByte) \ { \3 MGT_U32 *pLWV11Hdr = (MGT_U32 *) pMgtHdr; \ \ pLWV11Hdr[0] = \% ((MGTHDR$K_ACT_HDR_V1_1_LEN)) + \ ((MGTHDR$M_V) << 8) + \ ((0x01) << 16) + \ ((0x01) << 24); \ pLWV11Hdr[1] = \ ((hdrType)) + \% ((MGT$K_STS_RESERVED) << 8); \ pLWV11Hdr[2] = \ ((destMOID)); \ pLWV11Hdr[3] = \ ((srcMOID)); \ pLWV11Hdr[4] = \ ((actionCode)) + \ ((paramMinVer) << 16) + \ ((paramMajVer) << 24); \ pLWV11Hdr[5] = \ ((actionCtx)); \ \# if (ppNextByte != NULL) \ { \& char **MGTC11Hptr = ppNextByte; \ *MGTC11Hptr = \$ (char *)&(pLWV11Hdr[6]); \ } \}#endif/*%// Create a MO V2.1 compliant header//2// This macro will initialize a MO V2.1 compliant$// header at the address specified.*/#ifdef MGT_NATIVE_INT641#define MGT_CREATE_V2_1_MGT_HEADER(pMgtHdr, \ hdrType, \ destMOID, \ srcMOID, \ actionCode, \ paramMajVer, \ paramMinVer, \ actionCtx, \ ppNextByte) \ { \3 MGT_U64 *pQWV21Hdr = (MGT_U64 *) pMgtHdr; \ \ pQWV21Hdr[0] = \. ((MGT_U64)(MGTHDRV2$K_ACT_HDR_V2_1_LEN))+ \% ((MGT_U64)(MGTHDR$M_V) << 8) + \ ((MGT_U64)(0x01) << 16) + \ ((MGT_U64)(0x02) << 24) + \" ((MGT_U64)(hdrType) << 32) + \- ((MGT_U64)(MGT$K_STS_RESERVED) << 40); \ pQWV21Hdr[1] = \ ((MGT_U64)(destMOID)) + \# ((MGT_U64)(srcMOID) << 32); \ pQWV21Hdr[2] = \ ((MGT_U64)(actionCode)) + \& ((MGT_U64)(paramMinVer) << 16) + \& ((MGT_U64)(paramMajVer) << 24) + \% ((MGT_U64)(actionCtx) << 32); \ \# if (ppNextByte != NULL) \ { \& char **MGTC21Hptr = ppNextByte; \ *MGTC21Hptr = \$ (char *)&(pQWV21Hdr[3]); \ } \}#else1#define MGT_CREATE_V2_1_MGT_HEADER(pMgtHdr, \ hdrType, \ destMOID, \ srcMOID, \ actionCode, \ paramMajVer, \ paramMinVer, \ actionCtx, \ ppNextByte) \ { \3 MGT_U32 *pLWV21Hdr = (MGT_U32 *) pMgtHdr; \ \ pLWV21Hdr[0] = \' ((MGTHDRV2$K_ACT_HDR_V2_1_LEN)) + \ ((MGTHDR$M_V) << 8) + \ ((0x01) << 16) + \ ((0x02) << 24); \ pLWV21Hdr[1] = \ ((hdrType)) + \% ((MGT$K_STS_RESERVED) << 8); \ pLWV21Hdr[2] = \ ((destMOID)); \ pLWV21Hdr[3] = \ ((srcMOID)); \ pLWV21Hdr[4] = \ ((actionCode)) + \ ((paramMinVer) << 16) + \ ((paramMajVer) << 24); \ pLWV21Hdr[5] = \ ((actionCtx)); \ \# if (ppNextByte != NULL) \ { \& char **MGTC21Hptr = ppNextByte; \ *MGTC21Hptr = \$ (char *)&(pLWV21Hdr[6]); \ } \}#endif/*)// Create a MO V2.1 compliant miniheader//2// This macro will initialize a MO V2.1 compliant(// miniheader at the address specified.*/#ifdef MGT_NATIVE_INT645#define MGT_CREATE_V2_1_MGT_MINIHEADER(pMgtHdr, \ hdrType, \ ppNextByte) \ { \4 MGT_U64 *pQWV21MHdr = (MGT_U64 *) pMgtHdr; \ \ pQWV21MHdr[0] = \/ ((MGT_U64)(MGTHDRV2$K_MINI_HDR_V2_1_LENGTH))+\% ((MGT_U64)(MGTHDR$M_V) << 8) + \ ((MGT_U64)(0x01) << 16) + \ ((MGT_U64)(0x02) << 24) + \" ((MGT_U64)(hdrType) << 32) + \- ((MGT_U64)(MGT$K_STS_RESERVED) << 40); \ \# if (ppNextByte != NULL) \ { \& char **MGTC21Hptr = ppNextByte; \ *MGTC21Hptr = \% (char *)&(pQWV21MHdr[1]); \ } \}#else5#define MGT_CREATE_V2_1_MGT_MINIHEADER(pMgtHdr, \ hdrType, \ ppNextByte) \ { \4 MGT_U32 *pLWV21MHdr = (MGT_U32 *) pMgtHdr; \ \ pLWV21MHdr[0] = \* ((MGTHDRV2$K_MINI_HDR_V2_1_LENGTH)) + \ ((MGTHDR$M_V) << 8) + \ ((0x01) << 16) + \ ((0x02) << 24); \ pLWV21MHdr[1] = \ ((hdrType)) + \% ((MGT$K_STS_RESERVED) << 8); \ \# if (ppNextByte != NULL) \ { \& char **MGTC21Hptr = ppNextByte; \ *MGTC21Hptr = \% (char *)&(pLWV21MHdr[2]); \ } \}#endif/*A// Initialize a V1.1 MO security header into the response buffer//6// Create a V1.1 MO security header into the response // buffer.//3// This macro assumes that there is enough room in5// the response buffer for the V1.1 security header.//,// The next available byte parameter is the.// address of the field that will receive the0// address of the next available byte. If this// parameter is equal to NULL,&// then this address is not returned.*/3#define MGT_CREATE_V1_1_MGT_SEC_HDR(pDestHdr, \ ppNextByte)  \ { \" MGT_CREATE_V1_1_MGT_HEADER \ (pDestHdr, \, MGTHDR$K_REC_TYPE_ACCESS_RIGHTS, \ 0x00, \ 0x00, \ 0x00, \ 0x01, \ 0x01, \ 0x00, \ ppNextByte); \ }/*A// Initialize a V2.1 MO security header into the response buffer//6// Create a V2.1 MO security header into the response // buffer.//3// This macro assumes that there is enough room in5// the response buffer for the V2.1 security header.//,// The next available byte parameter is the.// address of the field that will receive the0// address of the next available byte. If this// parameter is equal to NULL,&// then this address is not returned.*/3#define MGT_CREATE_V2_1_MGT_SEC_HDR(pDestHdr, \ ppNextByte) \ { \" MGT_CREATE_V2_1_MGT_HEADER \ (pDestHdr, \, MGTHDR$K_REC_TYPE_ACCESS_RIGHTS, \ 0x00,  \ 0x00, \ 0x00, \ 0x01, \ 0x01, \ 0x00, \ ppNextByte); \ }/*4// Return the length of various MO error responses.*/*#define MGT_V1_1_MGT_ERROR_RESPONSE_LEN \ (MGTHDR$K_RSP_HDR_V1_1_LEN) *#define MGT_V2_1_MGT_ERROR_RESPONSE_LEN \! (MGTHDRV2$K_RSP_HDR_V2_1_LEN) /*5// Initialize a MO response into the response buffer//6// Initialize a MO response from the MO request. The5// header version of the response will be the header// version of the request.//,// The next available byte parameter is the.// address of the field that will receive the0// address of the next available byte. If this// parameter is equal to NULL,&// then this address is not returned.//3// This macro will carry over the fields that need8// to be copied from the MO request to the MO response.///// This macro assumes that for some calls, the6// request buffer is the same as the response buffer,4// and that the two headers might overlap. If this7// is the case, the following context should be saved://1// 1) If the MORE bit is set, the address of the// next request header/// 2) If the CONTINUATION bit is set, the data*// associated with the continuation packet3// 3) If the CONTEXT bit is set, the packet itself$// 4) The parameter length and data5// 5) The number of parameter records, if applicable//*/.#define MGT_INIT_MGT_RESPONSE(pSrcHdr, \ pDestHdr, \ MOErrorStatus, \ paramMajVer, \ paramMinVer, \ ppNextByte) \ { \6 MGT_U64 TmpHdr[(MGTHDR$K_ACT_HDR_LEN/8)+1]; \/ MGTHDR *pTmpHdr = (MGTHDR *) TmpHdr; \4 MGTHDRV2 *pTmpHdrV2 = (MGTHDRV2 *) TmpHdr; \ \6 if (((MGTHDR *)pSrcHdr)->mgthdr$b_hdr_major == 1) \ { \' MGT_CREATE_V1_1_MGT_HEADER \ (pTmpHdr, \$ MGTHDR$K_REC_TYPE_ACT_RSP, \ 0x00, \ 0x00, \ 0x00, \ paramMajVer, \ paramMinVer, \ 0x00, \ NULL); \( pTmpHdr->mgthdr$b_rsp_status \ = MOErrorStatus; \ } \ else \ { \' MGT_CREATE_V2_1_MGT_HEADER \ (pTmpHdrV2, \$ MGTHDR$K_REC_TYPE_ACT_RSP, \ 0x00, \ 0x00, \ 0x00, \ paramMajVer, \ paramMinVer, \ 0x00, \ NULL); \, pTmpHdrV2->mgthdrv2$b_rsp_status \ = MOErrorStatus; \ } \" MGT_COPY_MGT_REQUEST_INFO \ (pSrcHdr,pTmpHdr); \ MGT_COPY_MGT_HEADER \* (pTmpHdr,pDestHdr,ppNextByte); \ }/*;// Initialize a MO error response into the response buffer//0// Create a MO error response into the response;// buffer, and initialize it with data from the MO request;// and set the MO response status with the MO error status6// parameter. The MO response header version is based%// on the MO request header version.//3// This macro assumes that there is enough room in0// the response buffer for the response buffer.1// If a Management is called from RMDRIVER, this// is the case.//,// The next available byte parameter is the.// address of the field that will receive the0// address of the next available byte. If this// parameter is equal to NULL,&// then this address is not returned.//3// This macro will carry over the fields that need8// to be copied from the MO request to the MO response.*/-#define MGT_CREATE_MGT_ERROR_RESPONSE( \ pSrcHdr, \ pDestHdr, \ MOErrorStatus, \ ppNextByte) \ { \ MGT_INIT_MGT_RESPONSE \ (pSrcHdr, \ pDestHdr, \ MOErrorStatus, \ 1, \ 1, \ ppNextByte);  \ }/*/// Convert a MO response back to an MO request//2// For the case where MO request and MO responses4// share a buffer, upon a continuation the response2// header needs to be converted back to a request3// header. This routine does that processing. It4// clears the flags field in preparation for adding// or attaching other headers.*/6#define MGT_CVT_MGT_RESPONSE_TO_REQUEST(pSrcHdr, \ ppNextByte) \ { \3 MGTHDR *pCMRTRSrcHdr = (MGTHDR *)pSrcHdr; \6 MGTHDRV2 *pCMRTRSrcHdrV2 = (MGTHDRV2 *)pSrcHdr; \ \) pCMRTRSrcHdr->mgthdr$b_flags = 0; \% pCMRTRSrcHdr->mgthdr$v_v = 1; \ \1 if (pCMRTRSrcHdr->mgthdr$b_hdr_major <= 2) \ { \, pCMRTRSrcHdr->mgthdr$b_mgt_func = \# MGTHDR$K_REC_TYPE_ACT_REQ; \. pCMRTRSrcHdr->mgthdr$b_rsp_status = \ MGT$K_STS_RESERVED; \+ pCMRTRSrcHdr->mgthdr$w_par_len = \ 0; \0 pCMRTRSrcHdr->mgthdr$b_num_par_recs = \ 0; \ } \ else \ { \4 pCMRTRSrcHdrV2->mgthdrv2$b_mgt_func = \# MGTHDR$K_REC_TYPE_ACT_REQ; \4 pCMRTRSrcHdrV2->mgthdrv2$b_rsp_status = \ MGT$K_STS_RESERVED; \3 pCMRTRSrcHdrV2->mgthdrv2$w_par_len = \ 0; \4 pCMRTRSrcHdrV2->mgthdrv2$b_num_par_recs = \ 0; \ } \ \! if (ppNextByte != NULL) \ { \0 char **MGTCMRTRHptr = ppNextByte; \ *MGTCMRTRHptr = \- MGT_GET_MGT_PARAM_ADDR(pCMRTRSrcHdr); \ } \ }/* // Add quadword block to packet//0// This macro will copy a quadword block to the1// the packet, and adjust the data length of the// packet accordingly.*/5#define MGT_ADD_QW_BLOCK_TO_MGT_PACKET(pMgtHdr, \ pQWSrc, \ len) \ { \ int MGTAQWDest = \ (char *)pMgtHdr +  \' MGT_MGT_PACKET_LEN(pMgtHdr); \ \ MGT_COPY_QW_BLOCK \$ (pQWSrc,MGTAQWDest,len); \ \# MGT_SET_MGT_PACKET_DATA_LEN \ (pMgtHdr, \' MGT_GET_MGT_PACKET_DATA_LEN \ (pMgtHdr) + \ len \ ) \ }/*(// Add a main header to a MO packet set//%// This macro will add a main header0// to a MO packet set at the end of the packet.2// It will set all the fields as needed, and will.// return the address of the data section for.// the added main header. This will also set0// the necessary fields in the MO packet set to-// indicate that another packet set follows.//-// The parMaj parameter is the major version-// number for the data the added main packet-// will contain, and the parMin parameter is// the minor version.//-// The bufLen parameter should be the length,// of the buffer from the pSrcHdr parameter// to the end of the buffer.//+// This routine returns the address of the.// added header as well as the address of the// next available byte.*/,#define MGT_ADD_MAIN_HEADER(pSrcHdr, \ bufLen, \ actionCode, \ parMaj, \ parMin, \ actionContext, \ retStatus, \ ppNextHdr, \ ppNextByte) \ { \1 MGTHDR *MGTAMHSrc = (MGTHDR *)pSrcHdr; \ MGTHDR *MGTAMHDest; \# MGTHDRV2  *MGTAMHDestV2; \ int remBufLen; \ \0 /* Calculate the remaining buffer len */ \ remBufLen = \ bufLen - \/ MGT_GET_MGT_PACKET_SET_LEN(pSrcHdr); \ \* /* Find the address for the new */ \ /* packet set. */ \ MGTAMHDest = \5 MGT_GET_NEXT_MGT_PACKET_SET_ADDR(pSrcHdr); \ \% /* Create the main header */ \- /* Since the headers are currently */ \. /* the same length and have many of */ \1 /* the fields set the same, a straight */ \* /* copy of the header with some */ \* /* adjustments is good for now. */ \/ /* Also, for a packet set chain, all */ \, /* the headers must have the same */ \' /* Management IDs, etc. */ \' MGT_COPY_MGT_HEADER_WITH_CHECK \ (pSrcHdr, \ MGTAMHDest, \ remBufLen, \ retStatus, \ ppNextByte \ );  \ MGTAMHDestV2 = \$ (MGTHDRV2 *)MGTAMHDest; \ \5 /* If this succeeded, fixup the headers */ \5 /* The Management function will be the */ \, /* same as the source header */ \+ if (retStatus == MGT$K_STS_SUCCESS) \ { \- /* Adjust the source header */ \, MGTAMHSrc->mgthdr$v_more = 1; \ \+ /* Adjust the new header */ \+ MGTAMHDest->mgthdr$b_flags = 0; \' MGTAMHDest->mgthdr$v_v = 1; \- MGTAMHDest->mgthdr$b_num_par_recs \ = 0; \/ MGTAMHDest->mgthdr$w_par_len = 0; \3 if (MGTAMHDest->mgthdr$b_hdr_major == 1) \ { \( MGTAMHDest->mgthdr$b_par_major = \ parMaj; \( MGTAMHDest->mgthdr$b_par_minor = \ parMin; \% MGTAMHDest->mgthdr$b_action = \ actionCode; \) MGTAMHDest->mgthdr$l_action_ctx = \ actionContext;  \ } \ else \ { \+ MGTAMHDestV2->mgthdrv2$b_par_major= \ parMaj; \+ MGTAMHDestV2->mgthdrv2$b_par_minor= \ parMin; \) MGTAMHDestV2->mgthdrv2$b_action = \ actionCode; \, MGTAMHDestV2->mgthdrv2$l_action_ctx= \ actionContext; \ } \ \1 /* Set the next header variable */ \# if (ppNextHdr != NULL) \ { \/ if (MGTAMHDest->mgthdr$b_hdr_major == 1) \ { \$ MGTHDR **MGTAMHDestHdr = \ (MGTHDR **)ppNextHdr; \) *MGTAMHDestHdr = MGTAMHDest; \ } \ else \ { \* MGTHDRV2 **MGTAMHDestHdrV2 = \! (MGTHDRV2 **)ppNextHdr; \, *MGTAMHDestHdrV2 = MGTAMHDestV2; \ } \ } \ } \ }/*6// Add an End-of-data (EOD) header to a MO packet set//8// This macro will add an EOD header to a MO packet set=// as determined by the parameter length in the main header.//7// The bufLen parameter is the length of the parameter3// buffer (the parameter length in the main header8// plus the length of the EOD header plus the parameter5// length in the EOD header) minus the length of the// actual data.//2// It will set all the fields as needed, and will/// return the address of just after the end of// the EOD header.//8// If the MO packet set already contains a continuation-// packet, an error status will be returned.*/'#define MGT_ADD_EOD_HEADER(pSrcHdr, \ bufLen, \ retStatus, \ ppNextByte) \ { \" MGTHDRV2 *MGTAEHSrcV2 = \ (MGTHDRV2 *)pSrcHdr; \ int MGTAEHSrcV2Len = \+ MGT_GET_MGT_PACKET_LEN(MGTAEHSrcV2); \ MGTHDRV2 *MGTAEHDestV2; \ \0 if ((MGTAEHSrcV2->mgthdrv2$v_continuation) || \) (MGTAEHSrcV2->mgthdrv2$v_context) \ ) \ { \, retStatus = MGT$K_STS_EOD_INVALIDADD; \ } \ else if (bufLen < \! MGTHDRV2$K_EOD_HDR_V2_1_LEN \ ) \ { \, retStatus = MGT$K_STS_EOD_INSFBUFLEN; \ } \ else \ { \% /* Find the address for the */ \ /* EOD header */ \ MGTAEHDestV2 = \' MGT_GET_NEXT_MGT_HDR_ADDR(pSrcHdr); \ \ /* Create the header */ \& MGT_CREATE_V2_1_MGT_MINIHEADER \ (MGTAEHDestV2, \ MGTHDR$K_REC_TYPE_EOD, \ NULL \ ); \ \) /* Set the length of the header */ \$ MGT_SET_MGT_PACKET_DATA_LEN \ (MGTAEHDestV2, \ bufLen - \# MGT_GET_MGT_PACKET_HEADER_LEN \ (MGTAEHDestV2) \ ); \ \) /* Find the address of the next */ \ /* available byte */ \ if (ppNextByte != NULL) \ { \% char **pTmpNextByte = ppNextByte; \ \ *pTmpNextByte = \" MGT_GET_NEXT_MGT_HDR_ADDR \ (MGTAEHDestV2); \ } \ \% /* Adjust the source header */ \( MGTAEHSrcV2->mgthdrv2$v_eod = 1; \ \& retStatus = MGT$K_STS_SUCCESS; \ } \ }/*0// Add a continuation header to a MO packet set//-// This macro will add a continuation header0// to a MO packet set at the end of the packet.2// It will set all the fields as needed, and will.// return the address of the data section for// the continuation header.//4// If the MO packet set has contains an EOD packet,&// the continuation flag will be set.//-// The parMaj parameter is the major version/// number for the data the continuation packet-// will contain, and the parMin parameter is// the minor version.*/,#define MGT_ADD_CONT_HEADER(pSrcHdr, \ bufLen, \ parMaj, \ parMin, \ actionContext, \ retStatus, \ ppNextHdr, \ ppNextByte) \ { \& MGTHDRV2  *MGTACHSrcV2 = \! (MGTHDRV2 *)pSrcHdr; \" MGTHDRV2 *MGTACHEODV2; \ MGTHDR *MGTACHDest; \# MGTHDRV2 *MGTACHDestV2; \ \ do \ { \4 /* Can't add a continuation header to */ \4 /* a MO packet set that already has a */ \& /* context header. */ \/ if (MGTACHSrcV2->mgthdrv2$v_context) \ { \/ retStatus = MGT$K_STS_CONT_INVALIDADD; \ break; \ } \ \4 /* If there is an EOD header, get to */ \4 /* the end of that header, else just */ \0 /* the end of the main header. */ \ MGTACHEODV2 = \' MGT_GET_MGT_EOD_ADDR(pSrcHdr); \ \- /* Find the address for the */ \) /* continuation header */ \% if (MGTACHEODV2 != NULL) \ { \ MGTACHDest = \/ MGT_GET_NEXT_MGT_HDR_ADDR(MGTACHEODV2); \ } \ else \ { \ MGTACHDest = \/ MGT_GET_NEXT_MGT_HDR_ADDR(pSrcHdr); \ } \ \3 /* Create the continuation header */ \4 /* Since the headers are currently */ \4 /* the same length and have many of */ \4 /* the fields set the same, a straight */ \1 /* copy of the header with some */ \1 /* adjustments is good for now. */ \*  MGT_COPY_MGT_HEADER_WITH_CHECK \ (pSrcHdr, \ MGTACHDest, \ bufLen, \ retStatus, \ ppNextByte \ ); \( if (!MGT_SUCCESS(retStatus)) \ break; \ \ MGTACHDestV2 = \! (MGTHDRV2 *)MGTACHDest; \ \- /* Adjust the source header */ \ MGTACHSrcV2-> \( mgthdrv2$v_continuation = 1; \ \4 /* Adjust the EOD header if needed */ \% if (MGTACHEODV2 != NULL) \ MGTACHEODV2-> \( mgthdrv2$v_continuation = 1; \ \3 /* Adjust the continuation header */ \+ MGTACHDest->mgthdr$b_flags = 0; \' MGTACHDest->mgthdr$v_v = 1; \- MGTACHDest->mgthdr$b_mgt_func = \$ MGTHDR$K_REC_TYPE_ACT_CONT; \- MGTACHDest->mgthdr$b_num_par_recs \ = 0; \/ MGTACHDest->mgthdr$w_par_len = 0; \2 MGTACHDest->mgthdr$b_par_major= parMaj; \2 MGTACHDest->mgthdr$b_par_minor= parMin; \6 MGTACHDest->mgthdr$l_action_ctx=actionContext; \ \1 /* Set the next header variable */ \# if (ppNextHdr != NULL) \ { \/ if (MGTACHDest->mgthdr$b_hdr_major == 1) \ { \$ MGTHDR **MGTACHDestHdr = \ (MGTHDR **)ppNextHdr; \) *MGTACHDestHdr = MGTACHDest; \ } \ else \ { \* MGTHDRV2 **MGTACHDestHdrV2 = \! (MGTHDRV2 **)ppNextHdr; \, *MGTACHDestHdrV2 = MGTACHDestV2; \ } \ } \ \ } while (FALSE); \ }/**// Attach an existing continuation packet// to a MO packet set//0// This macro will attach a continuation header0// to a MO packet set at the end of the packet..// It is assumed that the continuation packet3// already exists and is at the current end of the.// MO packet set. This  macro's purpose is to5// reattach a continuation packet to a MO packet set5// after a response has been converted to a request.2// It will set all the fields as needed, and will4// return the address at the end of the packet set.//4// If the MO packet set has contains an EOD packet,&// the continuation flag will be set.*/#ifdef MGTV2_DEFS>#if MGTHDRV2$K_CONT_HDR_V2_1_LEN != MGTHDR$K_CONT_HDR_V1_1_LENQ#error MGTHDRV2$K_CONT_HDR_V2_1_LEN != MGTHDR$K_CONT_HDR_V1_1_LEN in MGT_MACROS.H#endif#endif/#define MGT_ATTACH_CONT_HEADER(pSrcHdr, \ pContHdr, \ retStatus, \ ppNextByte) \ { \& MGTHDRV2 *MGTTCHSrcV2 = \! (MGTHDRV2 *)pSrcHdr; \" MGTHDRV2 *MGTTCHEODV2; \" char *MGTTCHNextByte; \" MGTHDRV2 *MGTTCHCont = \" (MGTHDRV2 *)pContHdr; \ \ do \ { \4 /* Can't attach a continuation header */ \4  /* to a MO packet set that already has */ \4 /* a continuation header or a context */ \ /* header. */ \6 if ((MGTTCHSrcV2->mgthdrv2$v_continuation) || \) (MGTTCHSrcV2->mgthdrv2$v_context) \ ) \ { \/ retStatus = MGT$K_STS_CONT_INVALIDATT; \ break; \ } \ \4 /* If there is an EOD header, get to */ \4 /* the end of that header, else just */ \0 /* the end of the main header. */ \ MGTTCHEODV2 = \' MGT_GET_MGT_EOD_ADDR(pSrcHdr); \ \- /* Find the address for the */ \) /* continuation header */ \% if (MGTTCHEODV2 != NULL) \ { \ MGTTCHNextByte = \/ MGT_GET_NEXT_MGT_HDR_ADDR(MGTTCHEODV2); \ } \ else \ { \ MGTTCHNextByte = \/ MGT_GET_NEXT_MGT_HDR_ADDR(pSrcHdr); \ } \ \4 /* See if the next byte is the address */ \0 /* of the continuation header. */ \4 if (MGTTCHNextByte != (char *)MGTTCHCont) \ { \/ retStatus = MGT$K_STS_CONT_INVALIDADR; \ break; \ } \ \4 /* Do a sanity check on the address */ \4 /* given for the continuation header */ \1 /* to see if it is still valid. */ \* if (!MGTTCHCont->mgthdrv2$v_v) \ { \/ retStatus = MGT$K_STS_CONT_INVALIDHDR; \ break; \ } \1 if (MGTTCHCont->mgthdrv2$b_mgt_func != \# MGTHDR$K_REC_TYPE_ACT_CONT \ ) \ { \/ retStatus = MGT$K_STS_CONT_INVALIDHDR; \ break; \ } \0 if (MGTTCHCont->mgthdrv2$b_hdr_len != \% MGTHDRV2$K_CONT_HDR_V2_1_LEN \ ) \ { \/ retStatus = MGT$K_STS_CO NT_INVALIDHDR; \ break; \ } \ \4 /* Reset the flags field to reflect */ \4 /* that this is the end of the packet */ \4 /* set. If there is a context header */ \4 /* at the end of this packet, it will */ \4 /* need to be reattached so that the */ \4 /* flag fields of all the headers are */ \2 /* set correctly and consistent. */ \/ MGTTCHCont->mgthdrv2$b_flags = 0; \,  MGTTCHCont->mgthdrv2$v_v = 1; \ \- /* Adjust the source header */ \6 MGTTCHSrcV2->mgthdrv2$v_continuation = 1; \ \4 /* Adjust the EOD header if needed */ \% if (MGTTCHEODV2 != NULL) \ MGTTCHEODV2-> \+ mgthdrv2$v_continuation = 1; \ \0 /* Fill in next byte parameter */ \$ if (ppNextByte != NULL) \ { \' char **MGTTCHDptr = ppNextByte; \ *MGTTCHDptr = \/ MGT_GET_NEXT_MGT_HDR_ADDR(MGTTCHCont); \ } \ \ } while (FALSE); \ }/*5// Copy a continuation packet from one MO packet set// to another MO packet set//3// This macro will copy a continuation packet from4// one MO packet set to another MO packet set. The/// continuation packet will be appended to the6// destination MO packet. If there is a continuation2// packet already associated with the destination8// MO packet set, then the retStatus will reflect this.//5// This macro assumes that the first 6 fields of the#// Management header are the same.*/)#define MGT_COPY_CONT_PACKET(pSrcHdr, \ pDestHdr, \ bufLen, \ retStatus, \ ppNextByte) \ { \+ MGTHDR *MGTCCDSrc = (MGTHDR *)pSrcHdr; \, MGTHDR *MGTCCDDest = (MGTHDR *)pDestHdr; \ \* /* Pick the right routine according */ \* /* to the Management header version */ \* switch (MGTCCDSrc->mgthdr$b_hdr_major) \ { \ case 1: \ \ MGT_COPY_V1_1_CONT_PACKET \ (pSrcHdr, \ pDestHdr, \ bufLen, \ retStatus, \ ppNextByte \ ); \ break; \ \ case 2: \ \ MGT_COPY_V2_1_CONT_PACKET \ (pSrcHdr, \ pDestHdr, \ bufLen, \ retStatus, \ ppNextByte \ ); \ break; \ \ default: \ \) retStatus = MGT$K_STS_HDR_INCOMPAT; \ break; \ \ } \ }-#define MGT_COPY_V1_1_CONT_PACKET(pSrcHdr, \ pDestHdr, \ bufLen, \ retStatus, \ ppNextByte) \ { \+ MGTHDR *MGTCCD11Src = (MGTHDR *)pSrcHdr; \- MGTHDR *MGTCCD11Dest = (MGTHDR *)pDestHdr; \ MGTHDR *MGTCCD11ContSrc; \ MGTHDR *MGTCCD11ContDest; \ \" /* First see if there is a */ \% /* continuation packet in the */ \ /* destination MO packet */ \ retStatus = \0 (MGTCCD11Dest->mgthdr$v_continuation ? \- MGT$K_STS_CONT_DATA_INVALIDCOPY : \ MGT$K_STS_SUCCESS \ ); \ \' /* If there isn't a continuation */ \( /* already, copy the one from the */ \) /* source MO to the destination MO */ \' if (retStatus == MGT$K_STS_SUCCESS) \ { \ MGTCCD11ContSrc = \$ MGT_GET_MGT_CONT_ADDR(pSrcHdr); \ MGTCCD11ContDest = \$ MGT_GET_NEXT_MGT_PACKET_SET_ADDR \ (pDestHdr); \& MGT_COPY_MGT_PACKET_WITH_CHECK \ (MGTCCD11ContSrc, \ MGTCCD11ContDest, \ bufLen, \ retStatus, \ ppNextByte \ ); \ \0 /* If this succeeded, fixup the header */ \+ if (retStatus == MGT$K_STS_SUCCESS) \ { \ MGTCCD11Dest-> \" mgthdr$v_continuation = 1; \ } \ } \ }1#define MGT_COPY_V2_1_CONT_PACKET(pSrcHdr, \ pDestHdr, \ bufLen, \ retStatus, \ ppNextByte) \ { \6 MGTHDRV2 *MGTCCD21Src = (MGTHDRV2 *)pSrcHdr; \6 MGTHDRV2 *MGTCCD21Dest = (MGTHDRV2 *)pDestHdr; \& MGTHDRV2 *MGTCCD21ContSrc; \' MGTHDRV2 *MGTCCD21ContDest; \ \& /* First see if there is a */ \) /* continuation packet in the */ \$ /* destination MO packet */ \ retStatus = \4 (MGTCCD21Dest->mgthdrv2$v_continuation ? \, MGT$K_STS_CONT_DATA_INVALIDCOPY : \ MGT$K_STS_SUCCESS \ ); \ \+ /* If there isn't a continuation */ \, /* already, copy the one from the */ \- /* source MO to the destination MO */ \+ if (retStatus == MGT$K_STS_SUCCESS) \ { \ MGTCCD21ContSrc = \( MGT_GET_MGT_CONT_ADDR(pSrcHdr); \ MGTCCD21ContDest = \( MGT_GET_NEXT_MGT_PACKET_SET_ADDR \ (pDestHdr); \* MGT_COPY_MGT_PACKET_WITH_CHECK \ (MGTCCD21ContSrc, \ MGTCCD21ContDest, \ bufLen, \ retStatus, \ ppNextByte \ ); \ \4 /* If this succeeded, fixup the header */ \/ if (retStatus == MGT$K_STS_SUCCESS) \ { \% MGTHDRV2 *MGTCCDEOD = \+ MGT_GET_MGT_EOD_ADDR(pDestHdr); \ if (MGTCCDEOD != NULL) \ MGTCCDEOD-> \% mgthdrv2$v_continuation = 1; \  \ MGTCCD21Dest-> \( mgthdrv2$v_continuation = 1; \ } \ } \ }/*5// Copy a continuation packet from one MO packet set7// to another MO packet set, replacing the one that is// currently there.//3// This macro will copy a continuation packet from4// one MO packet set to another MO packet set. The7// new continuation packet will replace the old in the9// destination MO packet. If there isn't a continuation2// packet already associated with the destination8// MO packet set, then the retStatus will reflect this.5// Since this is a replacement, and the confinuation5// packet may be in the middle of the MO packet set,7// the new continuation packet should be the same size7// as the old one, and if it isn't, the retStatus will// reflect this.*//#define MGT_REPLACE_CONT_PACKET(pSrcHdr, \ pDestHdr, \ retStatus, \ ppNextByte) \ { \. MGTHDR *MGTRCPSrc = (MGTHDR *)pSrcHdr; \/ MGTHDR *MGTRCPDest = (MGTHDR *)pDestHdr; \ MGTHDR *MGTRCPCSrc; \ MGTHDR *MGTRCPCDest; \ \) retStatus = MGT$K_STS_SUCCESS; \ do \ { \- /* First see if there is a */ \/ /* continuation packet in the */ \4 /* source and destination MO packet */ \5 if ((!MGTRCPSrc->mgthdr$v_continuation) || \, (!MGTRCPDest->mgthdr$v_continuation) \ ) \ { \ retStatus = \, MGT$K_STS_CONT_DATA_INVALIDREPL; \ break; \ } \ \4 /* If there is a continuation already, */ \4 /* replace the one from the source MO */ \+ /* to the destination MO */ \ MGTRCPCSrc = \( MGT_GET_MGT_CONT_ADDR(pSrcHdr); \ MGTRCPCDest = \( MGT_GET_MGT_CONT_ADDR(pDestHdr); \# MGT_REPLACE_MGT_PACKET \ (MGTRCPCSrc, \ MGTRCPCDest, \ retStatus, \ ppNextByte \ ); \ } while (FALSE); \ }/**// Prepare a packet set chain for another2// packet set. It will return the address of the// next packet header.*/3#define MGT_ADD_TO_PACKET_SET_CHAIN(pSrcHdr, \ pNextHdr) \ { \+ pSrcHdr->mgthdrv2$v_more = TRUE; \ pNextHdr = \5 MGT_GET_NEXT_MGT_PACKET_SET_ADDR(pSrcHdr); \ }ww ZU/* IDENT X-44 */I/************************************************************************I* *I* HPE CONFIDENTIAL. This software is confidential proprietary software *I* licensed by Hewlett Packard Enterprise Development, LP, and is not *I* authorized to be used, duplicated or disclosed to anyone without the *I* prior written permission of HPE. *I* Copyright 2018 Hewlett Packard Enterprise Development, LP *I* *I* VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *I* proprietary software licensed by VMS Software, Inc., and is not *I* authorized to be used, duplicated or disclosed to anyone without *I* the prior written permission of VMS Software, Inc. *I* Copyright 2018-2022 VMS Software, Inc.  *I* *I************************************************************************//**++ * FACILITY:** VMS Executive (LIB)* * ABSTRACT:*E* This header file provides the basic set of C inline functions for 2* the 64-bit memory management system services. *M* Note: these functions may only be used from within the sys$vm.exe execlet H* due to references to global routines which are not made available as * system vectors.* * AUTHOR:** Karen L. Noel*"* CREATION DATE: 13-Oct-1994** MODIFICATION HISTORY:*)* X-44 GHJ Gregory H. Jordan 23-Feb-2022:* Update the $is_mapped_shpt so that it will work on X86.*)* X-43 CMOS Christian Moser 16-Jun-2021:* Fix $more_pgflquota and check for negative to see if we** need to call mmg_std$purge_zpts or not.*)* X-42 GHJ Gregory H. Jordan 9-Jun-2021:* For now, always return false of $is_mapped_shpt on X86.*#* X-41 AHM Drew Mason 14-Apr-2020<* Change declaration of phv$gl_pixbas from uint16 to int16.*)* X-40 GHJ Gregory H. Jordan 1-Feb-20197* Revert PT_NO_DELETE symbols back to the prior names.*#* X-39 AHM Drew Mason 16-Mar-20189* Change $pt_no_delete for NOSVAPTE to use different PHD=* symbols instead of PT_NO_DELETE1 and 2. Change references3* to pte$v_pfn to an architecture-specific symbol.*!* X-38 Mark Morris 17-Aug-20075* Add check i n $pt_no_delete for a negative phvindex/* field, which occurs for the Swapper process.*%* X-37 Ruth Goldenberg 17-May-20078* Remove incorrect test in $is_valid_delete_range that8* required the range to be mapped by an integral number7* of shared page tables. It is possible to create such0* a section, and this overly strict requirement;* makes it impossible to delete the section, once created.*?* X-36 Ram Ramachandra C N 26-apr-2007E*  The FREWSLE_ACTIVE bit is stored in volatile variable7* to prevent compiler optimisation when it is sampled.*?* X-35 Ram Ramachandra C N 23-Feb-2007H* On IA64, use __CMP_SWAP_QUAD instead of __CMP_STORE_QUAD-* since the latter is not available on IA64.*?* X-34 Ram Ramachandra C N 22-Feb-20076* Add $atomic_write_keep_in_ws function.4* Also mmg$gl_sysphd is made global extern to avoid+* conflict when t his header is included. *)* X-33 GHJ Gregory H. Jordan 18-Dec-20069* In the $pt_no_delete macro, the synchronization of the9* phd$pq_pt_no_delete* fields is changing from using the-* MMG spinlock to the PCB specific spinlock.*"* X-32 Andy Kuehnel 16-Aug-20049* The macros $is_valid_delete_range and $is_mapped_shpts:* have the implicit assumption that a GH region cannot be:* larger than the VA space mapped by a single level 3 PT.!* That is no longer true on I64.*9*   Also: $is_mapped_shpt was holding MMG when this is not;* necessary. We are at IPL$_ASTDEL where we can take page2* faults but the address space cannot be changed.*"* X-31 Andy Kuehnel 30-Jun-2004=* On IA64, don't try to jump over the gap for more VA space:)* you might not land where you expect...*!* X-30 Clair Grant 08-Mar-2004* Updates for 64b PFNs*'* X-29 MLM Mark L. Morris 26-FEB-20041* Modify $is_last_section_page to expand checks *)* X-28 CMOS Chris tian Moser 10-FEB-2004>* Modify $update_peak_counters to shadow VIRTPEAK and IPAGEFL* in the PHD.*-* X-26,27 KLN3374 Karen L. Noel 17-Oct-2003?* In $start_end_va, fix return_start_va for descending region @* with expreg. This case was only wrong when the length was not;* page size aligned, ie. a partial seciton. PTR 75-101-325*-* X-24A18 KLN3025 Karen L. Noel 26-Feb-2002* o Port PT space to IA64.C* o Remove inline pragmas. We trust the compiler now.* -* X-24A17 KLN2200 Karen L. Noel 15-Nov-2000:* Disable informationals for pointer casting. We know the%* pointer is 32-bits before we cast.*-* X-24A16 KLN2176 Karen L. Noel 17-Apr-2000<* Reference the L1 page table physically in $is_mapped_shpt*-* X-24A15 KLN2171 Karen L. Noel 28-Mar-20004* Move $read_pte and $write_pte to pte_functions.h.*-* X-24A14 KLN2137 Karen L. Noel 11-Feb-2000;* o Make read and write PTE macros static so more than one* module can include them.>* o Clean up interfaces so PTECHECK can use these macros too.*3* X-24A13 KLN2134 Karen L. noel 10-Feb-2000%* Add macros to read and write PTEs.* %* X-24A12 Andy Kuehnel 8-Jul-1998/* Detect SHMGS pages as being memory resident.*%* X-24A11 Andy Kuehnel 18-Jun-19985* - Allow galaxy shared pages as shared page tables.A* - Close minute windows: we must first get MMG, then see if the&* pages we want to touch are valid.*-* X-24A10 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*$* X-24A9 Andy Kuehnel 20-Jan-1998B* Teach $gsd_insque how to deal with SHMGS sections and rename it* to $insque_gsd.*/* X-24A8 NYK668 Nitin Y. Karkhanis 9-Sep-19966* $start_end_va must align VA to PT-page boundary for* shared PT regions.*/* X-24A7 NYK660 Nitin Y. Karkhanis 29-Aug-1996?* Add $is_in_region, $is_mapped_shpts, $is_valid_delete_range,* and $is_last_section_page.*,* X-24A6 KLN1556 Karen L. Noel 19-Jun-1996* Add function $is_mem_res*,* X-24A5 KLN1549 Karen L. Noel 31-May-1996* Add function $stx_to_entry.*,* X-24A4 KLN1533 Karen L. Noel 24-Oct-1995?* Move $probe functions to sys_functions.h, a more appropriate* home.*1* X-24A3 KLN1527 Karen L. Noel 9-Oct-1995A* 1. In $more_pgflquota, purge zero page table pages to release 9* pagefile quota if the process has run out of quota.* 2. Add $keep_in_ws function.* ,* X-24A2 KLN1515 Karen L. Noel 20-Sep-19957* Return error from $in_region_64 if either VA is with** the gap of the the range spans the gap.*,* X-24A1 KLN1503 Karen L. Noel 29-Aug-19955* Allow start_va = 0 and no expreg in $start_end_va.*** X-24 KLN1484 Karen L. Noel 21-Jul-1995&* Check for VA wrap in $start_end_va.*** X-23 KLN1482 Karen L. Noel 20-Jul-1995* Page count -> 64 bits.*** X-22 KLN1481 Karen L. Noel 20-Jul-1995* Only jump over the gap if P2*** X-21 KLN1480 Karen L. Noel 19-Jul-1995>* Make length of P2 header region a natural non-sign-extended * value.*** X-20 KLN1476 Karen L. Noel 17-Jul-19958* Return SS$_VA_IN_USE if $adjust_header_region overlap** created address space in header region.*** X-19 KLN1472 Karen L. Noel 11-Jul-1995* 1. Hop over the gap properly.* 2. Insert GSDs into the GSD queues properly*** X-18 KLN1461 Karen L. Noel 19-Jun-1995* Restore lost check-in.*-* X-17 NYK439 Nitin Y. Karkhanis 19-Jun-19956* Restore lost edit that was X-16. That was "Virtual5* peak calculation in $update_peak_counters does not!* need created_length argument."*** X-16 KLN1458 Karen L. Noel 12-Jun-19952* Charge for page table pages for pagefile quota.*-* X-15 NYK422 Nitin Y. Karkhanis 8-Jun-1995&* Add $update_peak_counters function.*** X-14 KLN1457 Karen L. Noel 05-Jun-19957* Add functions $remove_rde and $adjust_header_region.*+* X-13 KLN1434 Karen L. Noel 18-Apr-1995* Add $pt_no_delete function.*** X-12 KLN1425 Karen L. Noel 30-Mar-19953* Allow default P2 region to start at a higher VA.*** X-11 KLN1383 Karen L. Noel 13-Feb-19952* Fix $start_end_va for P1 block multiple ranges.*+* X-9,10 KLN1379 Karen L. Noel 6-Feb-1995* Add $gsd_insque function.*+* X-7,8 KLN1354 Karen L. Noel 15-Dec-1994?* Fix problems found while debugging process private services.*(* X-6 KLN1347 Karen L. Noel 5-Dec-1994* Add $start_end_va.*)* X-5 KLN1342 Karen L. Noel 30-Nov-1994* Use $get_ps_info*)* X-4 KLN1337 Karen L. Noel 21-Nov-1994* Miscellaneous enhancements.*)* X-3 KLN1333 Karen L. Noel 10-Nov-1994* MMG utility functions.*)* X-2 KLN1327 Karen L. Noel 28-Oct-1994* Improve $lookup_rde_va*--*//*? Include any header files we need to make these functions work*/#ifndef __MMG_FUNCTIONS_LOADED #define __MMG_FUNCTIONS_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include H#define __MAX_PP_REGION_ID VA$C_P2 /* Max process permanent region id */"extern PHD * const mmg$gl_sysphd;6#ifdef __x86_64 // Verified for x86 port--Drew Mason##define PTE$V_ARCH_PFN pte$v_pfn_4k#else #define PTE$V_ARCH_PFN pte$v_pfn#endif /**++H* $lookup_rde_id - Lookup region descriptor entry (RDE) address given a * region id.*+* Input: region_id - Region id of interest.** phd - Address of PHD in P1 space.C* ipl - Current IPL if known, if not known or if 0, ipl will be7* set to IPL$_ASTDEL upon entry and restored upon* completion.*** Output: rde - Address of associated RDE.**--*/Gstatic RDE *$lookup_rde_id (uint64 region_id, PHD * const phd, int ipl){9 extern RDE *ctl$a_region_table[RDE$C_REGION_TABLE_SIZE];8 RDE *pp_rde_array; /* Process permanent RDE array */ RDE *rde; /* Pointer to RDE */4 int saved_ipl; /* Saved ipl for synchronization */1 uint32 index; /* Index into region table */ /* Process permanent regions */# if (region_id < RDE$C_MIN_USER_ID) {1 if (region_id > __MAX_PP_REGION_ID) return (0);4 pp_rde_array = (RDE *)&(phd->phd$q_p0_rde);& return (pp_rde_array + region_id);  } /* Synchronize, if necessary */@ if (ipl < IPL$_ASTDEL) saved_ipl = __PAL_MTPR_IPL(IPL$_ASTDEL); /* User defined regions */9 index = (uint32)region_id & (RDE$C_REGION_TABLE_SIZE-1); ! rde = ctl$a_region_table[index];: while ((rde != 0) && (rde->rde$q_region_id != region_id)) rde = rde->rde$ps_table_link; /* Restore ipl */2 if (ipl < IPL$_ASTDEL) __PAL_MTPR_IPL(saved_ipl);. return (rde); /* return 0 or rde if found */} /**++ ,* $search_rde_va - Search for RDE in VA list*1* Inputs: va - Virtual address of interest.1* head - RDE list header of interest.*$* Output: RDE address if exact match<* *prev - address of previous RDE in list (may be head)<* *next - address of next RDE in list (may be head)*H* Environment: Must be called at IPL$_ASTDEL for proper synchronization.**--*/Jstatic RDE *$search_rde_va (VOID_PQ va, RDE *head, RDE **prev, RDE **next){ /* External variables */" extern const int mmg$gl_va_bits; /* Local variables */ RDE *rde;* /* Header region is ascending (P0, P2) */ if (!head->rde$v_descend) { *prev = 0; rde = head;% *next = head->rde$ps_va_list_flink;# while ((*next != head) && (va >= / $$sext((uint64)rde->rde$pq_start_va + & rde->rde$q_region_size))) { *prev = rde; rde = *next;% *next = rde->rde$ps_va_list_flink; }" /* Figure out what to return */ 0 if (va < $$sext((uint64)rde->rde$pq_start_va +& rde->rde$q_region_size))  {# if (va >= rde->rde$pq_start_va) return (rde); /* Got it */" *next = rde; /* rde is next */$ return(0); /* prev is correct */  } else /* va is above rde */ {" *prev = rde; /* rde is prev */0 return (0); /* next is correct */ } }' /* Header region is descending (P1) */ if (head->rde$v_descend) { *prev = 0; rde = head;% *next = head->rde$ps_va_list_flink;8 while ((*next != head) && (va < rde->rde$pq_start_va)) { *prev = rde; rde = *next;& *next = rde->rde$ps_va_list_flink; }" /* Figure out what to return */ ! if (va >= rde->rde$pq_start_va) {4 if ((uint64)va < ((uint64)rde->rde$pq_start_va + ( rde->rde$q_region_size)) return (rde); /* Got it */" *next = rde; /* rde is next */$ return(0); /* prev is correct */  } else /* va is below rde */ {" *prev = rde; /* rde is prev */0 return (0); /* next is correct */ } }} /**++* $lookup_rde_va: * G* Lookup region descriptor entry (RDE) address given a virtual address.*0* Input: va - Virtual address of interest./* phd - Address of PHD in P1 space.* function - M* __LOOKUP_RDE_EXACT(0) = va must be within a region for an RDE to be * returnedO* __LOOKUP_RDE_HIGHER(1)  = If va is not within a region, the RDE for the 7* region whose starting VA is higher than VA will be * returned.A* ipl - Current IPL if known, if not known or if 0, ipl will be6* set to IPL$_ASTDEL upon entry and restored upon* completion.*** Output: rde - Address of associated RDE.**--*/Ostatic RDE *$lookup_rde_va (VOID_PQ va, PHD * const phd, int function, int ipl){1 extern const VOID_PQ mmg$gq_process_space_limit;6 int saved_ipl; /* Saved ipl f!or synchronization */4 int index; /* Index into RDE array in PHD */ A RDE *rde,*prev,*head,*next; /* RDE pointers for search */& uint64 mo=0; /* Quadword -1 */ mo = ~mo;#pragma message save&#pragma message disable pointerintcast /* Get proper list header */. if ($is_p2_va(va,mmg$gq_process_space_limit)) index = VA$C_P2; else if ($is_p1_va(va))  index = VA$C_P1; else if ($is_p0_va(va))  index = VA$C_P0;4 else /* -1 is wild-card start va, return P"0 RDE */> if (((uint64)va == mo) && (function == __LOOKUP_RDE_HIGHER))- return ((RDE *)&(phd->phd$q_p0_rde));@ else return (0); /* Non-process space addresses is an error */#pragma message restore, head = (RDE *)&(phd->phd$q_p0_rde) + index; /* Synchronize, if necessary */@ if (ipl < IPL$_ASTDEL) saved_ipl = __PAL_MTPR_IPL(IPL$_ASTDEL);4 /* Search list header for RDE associated with VA *// rde = $search_rde_va (va, head, &prev, &next); if (rde != 0)  {3 if (ipl < IP#L$_ASTDEL) __PAL_MTPR_IPL(saved_ipl);$ return (rde); /* Found match */ } /* Did not find exact match */% if (function == __LOOKUP_RDE_EXACT)  {3 if (ipl < IPL$_ASTDEL) __PAL_MTPR_IPL(saved_ipl); return (0); } + /* Function must be __LOOKUP_RDE_HIGHER */& if (function == __LOOKUP_RDE_HIGHER)  {, /* If descending, prev is higher */ if (head->rde$v_descend)  {4 if (ipl < IPL$_ASTDEL) __PAL_MTPR_IPL(saved_ipl); return (prev);$ } /* Ascending:: * If we have left a gap before start of header region,  * return header region */! if (va < head->rde$pq_start_va) {4 if (ipl < IPL$_ASTDEL) __PAL_MTPR_IPL(saved_ipl); return (head); }! /* Otherwise, next is higher */ if (next != head)  {4 if (ipl < IPL$_ASTDEL) __PAL_MTPR_IPL(saved_ipl); return (next); }8 /* Otherwise, off end of list, go look at next list */# if (index == __MAX_PP_REGION_ID)  {4 if (ipl <% IPL$_ASTDEL) __PAL_MTPR_IPL(saved_ipl); return (0);  } head++; , /* If ascending, head is next higher */  if (!head->rde$v_descend)  {4 if (ipl < IPL$_ASTDEL) __PAL_MTPR_IPL(saved_ipl); return (head);  }+ /* If descending, blink is next higher */# rde = head->rde$ps_va_list_blink;3 if (ipl < IPL$_ASTDEL) __PAL_MTPR_IPL(saved_ipl); return (rde); } /* Restore IPL */2 if (ipl < IPL$_ASTDEL) __PAL_MTPR_IPL(saved_ipl);) return (0); /* Inval&id function code */} /* End of $lookup_rde_va */ /**++3* $init_pgflquota - Initialize pagefile quota cache** Input: pcb - PCB address'* pages - page count of pages to map6* pagefile_cache - Address of pagefile cache storage* A* Output: pagefile_cache is updated to reflect any allocation or* deallocation*--*/4static void $init_pgflquota (const PCB * const pcb,  int pages, # int *pagefile_cache){ uint32 min; JIB *jib;'+ /* Do nothing if cached quota is enough */& if (*pagefile_cache >= pages) return; /* Get address of JIB */ jib = pcb->pcb$l_jib;* /* Use min of pages and pagefile quota */ while (1) { min = jib->jib$l_pgflcnt; if (pages < min) min = pages;1 __ADD_ATOMIC_LONG (&jib->jib$l_pgflcnt, -min);  if (jib->jib$l_pgflcnt >= 0) { *pagefile_cache += min; return; }/ __ADD_ATOMIC_LONG (&jib->jib$l_pgflcnt, min); }} /**++1* $more_pgflquota - Ge(t more pagefile quota cache** Input: pcb - PCB address6* pages_1 - page count - 1 of remaining pages to map6* pagefile_cache - Address of pagefile cache storage* A* Output: pagefile_cache is updated to reflect any allocation or* deallocation*--*/4static void $more_pgflquota (const PCB * const pcb,  int pages_1,$ int * pagefile_cache){ /* External routine */C extern void mmg_std$purge_zpts (VOID_PQ start_va, VOID_PQ end_va); /* Ex)ternal variable */1 extern VOID_PQ const mmg$gq_process_space_limit;( /* Try for number of pages requested *// $init_pgflquota(pcb,pages_1+1,pagefile_cache);B /* If we've run out of pagefile quota, try purging page tables */ if (*pagefile_cache < 0) {% /* Purge zero'd page table pages */ mmg_std$purge_zpts (0,4 (VOID_PQ)((uint64)mmg$gq_process_space_limit-1));% /* Now try to get pagefile quota */0 $init_pgflquota(pcb,pages_1+1,pagefile_cache); }} /**++5* $r*et_pgflquota - Return unused pagefile quota cache** Input: pcb - PCB address6* pagefile_cache - Address of pagefile cache storage* =* Output: Unused pagefile quota cache is returned to jib and"* pagefile_cache is reset to zero*--*/Gstatic void $ret_pgflquota (const PCB * const pcb, int *pagefile_cache) { int ipl; JIB *jib;$ /* return cached page file quota */ jib = pcb->pcb$l_jib;: __ADD_ATOMIC_LONG (&jib->jib$l_pgflcnt, *pagefile_cache); *pagefile_c+ache = 0;} /**++K* $is_in_region - Is virtual address between starting address of region and+* starting address plus length of region* * Input: va - virtual address* rde - region descriptor* Output: 1 - is in region* 0 - in not in region**--*/#define $is_in_region(va,rde)\&(((va) >= (rde)->rde$pq_start_va) && \M ((va) < $$sext((uint64)(rde)->rde$pq_start_va + (rde)->rde$q_region_size)))  /**++3* $in_region_64 - check if request is within regio,n** Input: RDE - RDE address* start_va - Starting address* end_va - Ending address* ** Output: *exbytes - # of bytes to expand#* *pages - # of pages in request * status = SS$_NORMAL - success* 0 - failure*--*/&static int $in_region_64 (RDE *rde, VOID_PQ start_va,  VOID_PQ end_va,  uint64 *expbytes, UINT64_PQ pages){ /* External variables */% extern const uint64 mmg$gq_bwp_mask;& extern const int mmg$gl_page_size, - mmg$gl_bwp_width, mmg$gl_va_bits;' extern VOID_PQ const mmg$gq_gap_lo_va, mmg$gq_gap_hi_va;  /* Local variables */ VOID_PQ lo, hi;; /* page align start_va and end_va and get this in order */ if (start_va < end_va) {6 lo = (VOID_PQ)((uint64)start_va & ~mmg$gq_bwp_mask);4 hi = (VOID_PQ)((uint64)end_va & ~mmg$gq_bwp_mask); } else  {6 hi = (VOID_PQ)((uint64)start_va & ~mmg$gq_bwp_mask);4 lo = (VOID_PQ)((uint64)end_va & ~mmg$gq_bwp_mask); }.$ /* compute and return page count */> *pages = (((uint64)hi - (uint64)lo) >> mmg$gl_bwp_width) + 1;1 if (!rde->rde$v_descend) /* ascending region */ {8 /* decide if this is all past current end of region */% if (lo < rde->rde$pq_first_free_va) return (0);% if (hi < rde->rde$pq_first_free_va)# return (0); = /* Also, return error if hi is higher than end of region */2 if (hi >= $$sext((uint64)rde->rde$pq_start_va + 8 / rde->rde$q_region_size)) return (0);/#ifdef __alpha // Verified for IA64 port - ak: /* Also, return error if either VA is within the gap, or * if the range spans the gap */' if (rde->rde$q_region_id == VA$C_P2)  {" if ((lo >= mmg$gq_gap_lo_va) && (lo < mmg$gq_gap_hi_va)) return (0);" if ((hi >= mmg$gq_gap_lo_va) && (hi < mmg$gq_gap_hi_va)) return (0);! if ((lo < mmg$gq_gap_lo_va) && (hi >= mmg$gq_gap_hi_va)) return 0(0); }#endif= /* return # of bytes to expand (watch out for jumping over  * the gap)  */@ *expbytes = $$trunc(hi) - $$trunc(rde->rde$pq_first_free_va) + mmg$gl_page_size; return (SS$_NORMAL); } /* descending region */$ if (hi > rde->rde$pq_first_free_va) return (0);$ if (lo > rde->rde$pq_first_free_va) return (0);< /* Also return error if lo is lower than start of region */ if (lo < rde->rde$pq_start_va) return (0); " /* return # of bytes 1to expand */@ *expbytes = ((uint64)rde->rde$pq_first_free_va - (uint64)lo) +  mmg$gl_page_size; return (SS$_NORMAL);} /* *++/* $service_init - Initialize MMG system service*3* Input: return_va - address of caller's return va6* return_length _ address of caller's return length*?* Output: *callers_mode - mode of system service caller* *ipl - current IPL**--*//static int $service_init (VOID_PPQ return_va,  UINT64_PQ return_length,2 int *callers_mode, int *ipl){ uint64 mo;" /* Create a 64-bit constant -1 */ mo = 0; mo = ~mo; /* Get info from PS */ $get_ps_info(callers_mode,ipl);( /* Probe return_va and return_length */? if ($probew_2q(return_va, return_length, *callers_mode) == 0)  return (SS$_ACCVIO); - /* Initialize return_va and return_length */ *return_va = (VOID_PQ)mo; *return_length = 0;  /* All set */ return (SS$_NORMAL);} /**++2* $service_com 3plete - Complete MMG system service.*+* Input: probe - If 1, probes will be done$* - If 0, probes will not be done-* va - virtual address to return to caller'* length - length to return to caller.* return_va - address of caller's return va6* return_length _ address of caller's return lengthC* callers_mode - mode of system service caller (0 - no probes)5* *pagefile_cache - cached pagefile quota (0 - none)*"* Output: SS$_NORMAL if successful=* SS$_ACCVIO if ret4urn_va or return_length cannot be written*--*/(static int $service_complete (int probe, VOID_PQ va, uint64 length,# VOID_PPQ return_va,( UINT64_PQ return_length,! int callers_mode,$ int *pagefile_cache){ extern PCB * const ctl$gl_pcb;' /* Return any cached pagefile quota */ if (pagefile_cache != 0). $ret_pgflquota (ctl$gl_pcb, pagefile_cache);9 /* If re-probing is required, probe ret5urn parameters */ if ((probe) && @ ($probew_2q (return_va, return_length, callers_mode) == 0)) return (SS$_ACCVIO);3 /* Return va and length to system service caller*/ *return_va = va; *return_length = length; /* All set */ return (SS$_NORMAL);} /**++1* $start_end_va - compute starting and ending vas*A* Inputs: expreg - non-zero if region expansion specified'* rde - Address of region descriptor=* start_va - starting va specified: 0 if none, 6page aligned * if specified* length - length in bytes *2* Outputs: *return_start_va - returned starting va(* *return_end_va - returned ending va**--*/'static void $start_end_va (int expreg, RDE *rde,  VOID_PQ start_va, uint64 length, VOID_PQ *return_start_va, VOID_PQ *return_end_va){ /* External variables */, extern const uint64 mmg$gq_level_width, mmg$gq_page_size;* extern VOID_PQ const mmg$gq_gap_lo_va,7 mmg$gq_gap_hi_va; uint64 bytes_mapped_by_l3pt;2 /* Compute number of bytes mapped by a PT page */? bytes_mapped_by_l3pt = mmg$gq_page_size << mmg$gq_level_width; /* Ascending, expreg */% if ((!rde->rde$v_descend) && expreg) {% /* Calculate start va and end_va *// *return_start_va = rde->rde$pq_first_free_va;4 /* For shared PT regions, make sure start_va is PT page aligned */ if (rde->rde$v_shared_pts)! *return_start_va = $align_va ( *return_start_va8, bytes_mapped_by_l3pt, 1); *return_end_va =6 (VOID_PQ)((uint64)*return_start_va + (length - 1));/#ifdef __alpha // Verified for IA64 port - ak& /* Jump over the gap if necessary */* if ((rde->rde$q_region_id == VA$C_P2) &&, (*return_end_va > mmg$gq_gap_lo_va) &&, (*return_start_va < mmg$gq_gap_lo_va)) {' *return_start_va = mmg$gq_gap_hi_va; *return_end_va = 4 (VOID_PQ)((uint64)*return_start_va + length - 1); }#endif }$ /* Ascending, s9pecified start_va */& if ((!rde->rde$v_descend) && !expreg) { *return_start_va = start_va;> *return_end_va = (VOID_PQ)((uint64)start_va + (length - 1)); }G /* Ascending, if VA wrap has occurred, set end va to largest number */B if ((!rde->rde$v_descend) && (*return_end_va < *return_start_va)) *return_end_va = (VOID_PQ)-1; /* Descending, expreg */$ if ((rde->rde$v_descend) && expreg) { if (rde->rde$v_shared_pts) {! /* Calculate lowest used va */A *return_end_va := (VOID_PQ)((uint64)rde->rde$pq_first_free_va + mmg$gq_page_size);* /* Subtract length and PT-page align */ *return_end_va = $align_va (3 (VOID_PQ) ((uint64) *return_end_va - length), bytes_mapped_by_l3pt, 0); 3 /* Starting address is end_va plus length - 1 */G *return_start_va = (VOID_PQ) ((uint64) *return_end_va + length - 1); } else {! /* Calculate lowest used va */A *return_end_va = (VOID_PQ)((uint64)rde->rde$pq_first_free;_va + mmg$gq_page_size);' /* Subtract length and page align */A *return_end_va = (VOID_PQ)(((uint64)*return_end_va - length) &% ~(mmg$gq_page_size-1)); 6 /* Starting address is first free byte in region */E *return_start_va = (VOID_PQ)((uint64)*return_end_va + length - 1); } }% /* Descending, specified start_va */% if ((rde->rde$v_descend) && !expreg) {@ *return_start_va = (VOID_PQ)((uint64)start_va + (length - 1)); *return_end_va = s<tart_va; }I /* Descending, if VA wrap has occurred, set end va to smallest number */A if ((rde->rde$v_descend) && (*return_end_va > *return_start_va)) *return_end_va = 0;} /**++@* $insque_gsd - Insert GSD into appropriate global section queue*!* Inputs: flags - sections flags&* *gsd - Global section descriptor** Outputs: none** Environment: GSD mutex held**--*/6static void $insque_gsd (SECDEF_FLAGS flags, GSD *gsd){ /* External variables */= extern GSD * exe$gl_gsdsysfl; extern GSD * exe$gl_gsdsysbl; extern GSD * exe$gl_gsdgrpfl; extern GSD * exe$gl_gsdgrpbl; extern GSD * exe$gl_glxsysfl; extern GSD * exe$gl_glxsysbl; extern GSD * exe$gl_glxgrpfl; extern GSD * exe$gl_glxgrpbl; /* Local variables */ GSD **gsd_list_flink; GSD **gsd_list_blink; int type = 0; /* find queue "index" */+ if (flags.secflg$v_shmgs) type = 2;- if (flags.secflg$v_sysgbl) type |= 1;' /* Insert gsd i>nto appropriate list */ switch (type) {# case 0: /* group global */$ gsd_list_flink = &exe$gl_gsdgrpfl;$ gsd_list_blink = &exe$gl_gsdgrpbl; break;$ case 1: /* system global */$ gsd_list_flink = &exe$gl_gsdsysfl;$ gsd_list_blink = &exe$gl_gsdsysbl; break;) case 2: /* SHMGS group global */$ gsd_list_flink = &exe$gl_glxgrpfl;$ gsd_list_blink = &exe$gl_glxgrpbl; break;) case 3: /* SHMGS system global*/$ gsd_list_flink = &exe$gl_glxsysfl;$? gsd_list_blink = &exe$gl_glxsysbl; break; }) (*gsd_list_flink)->gsd$l_gsdbl = gsd;+ gsd->gsd$l_gsdfl = *gsd_list_flink;* gsd->gsd$l_gsdbl = (GSD *)gsd_list_flink; *gsd_list_flink = gsd;} /**++C* $pt_no_delete - Set fields in PHD to synchronize PT create/delete*?* Inputs: l2pte1 - starting l2pte va (0 if clearing PHD fields)* l2pte2 - ending l2pte va * phd - process's PHD address* IPL is at IPL$_ASTDEL*E* Output: SS$_WASSET if l2pte1 and l2pte@2 are already within range of* page tables already created.** SS$_WASCLR if range no already created.*--*/)static int $pt_no_delete (PTE_PQ l2pte1, PTE_PQ l2pte2, PHD *phd){ /* External variables */& extern PCB **sch$gl_pcbvec;9 extern int16 *PHV$GL_PIXBAS; // Must be SIGNED6 extern PCB * const sch$ar_swppcb; /* Swapper's PCB */ /* Local variables */ VOID_PQ pte1, pte2; PCB *pcb; int index;= index = phd-A>phd$l_phvindex; // Get the PHV index- if (index == -1) // Handle Swapper case { pcb = sch$ar_swppcb; } else {C index = PHV$GL_PIXBAS[index]; // Get the process index9 pcb = sch$gl_pcbvec[index]; // Get the PCB }8 /* If range is zero, we want to clear the PHD fields */ if (l2pte1 == 0) { /* Clear PHD fields */L /* Note that phd$pq_pt_no_delete* are synchronized via the PCB spinlock */= device_lock ( pcb->pcb$l_spinlock, RBAISE_IPL, NOSAVE_IPL ); phd->phd$pq_pt_no_delete1 = 0; phd->phd$pq_pt_no_delete2 = 0;B device_unlock ( pcb->pcb$l_spinlock, IPL$_ASTDEL, SMP_RELEASE ); /* Done */ return (SS$_WASCLR); }$ /* Swap PTE pointers if reversed */ pte1 = l2pte1; pte2 = l2pte2; if (pte1 > pte2) { pte1 = l2pte2; pte2 = l2pte1; }G /* If PHD fields are filled in, check range. If in range, all set. */( if ((phd->phd$pq_pt_no_delete1 != 0) &&+ (pte1 >= phd->phd$pq_pt_no_delete1)C &&) (pte2 <= phd->phd$pq_pt_no_delete2)) return (SS$_WASSET);  /* Set PHD fields */< device_lock ( pcb->pcb$l_spinlock, RAISE_IPL, NOSAVE_IPL );" phd->phd$pq_pt_no_delete1 = pte1;" phd->phd$pq_pt_no_delete2 = pte2;A device_unlock ( pcb->pcb$l_spinlock, IPL$_ASTDEL, SMP_RELEASE ); return (SS$_WASCLR); } /*+I* $adjust_header_region - Internal function to adjust header region's RDE*$* Inputs: head - Header region's RDE* next - New next RDE*:* Output: Dstatus - Error code if anything is inconsistent.**/Gstatic int $adjust_header_region (RDE *head, /* Header region's RDE */- RDE *next) /* New next region */{   /* External variables */1 extern VOID_PQ const mmg$gq_process_space_limit;: extern const int mmg$gl_page_size, mmg$gl_bwp_width; % extern const int mmg$gl_va_bits; /* Local constants */( const uint64 size_of_p0 = 0x40000000;1 const VOID_PQ p1_start_va = (VOID_PQ)0x40000000;( const uint64 sizeE_of_p1 = 0x40000000; /* Local variables */ VOID_PQ start_va = 0; uint64 region_size = 0;* /* Initialize start_va and region_size */ if (next != head) {# start_va = next->rde$pq_start_va;( region_size = next->rde$q_region_size; } /* Ascending header region */ if (!head->rde$v_descend) { if (next == head)# /* Header region is now empty */ if (head->rde$v_p0_space) ) head->rde$q_region_size = size_of_p0; else { " /* Must be P2 space *F/  head->rde$q_region_size = ) $$trunc(mmg$gq_process_space_limit); head->rde$q_region_size -=$ $$trunc(head->rde$pq_start_va); } if (next != head) { 8 /* Don't allow if less than header's first free va */. if (start_va < head->rde$pq_first_free_va)  return (SS$_VA_IN_USE);" /* Adjust header region size */1 head->rde$q_region_size = $$trunc(start_va) - % $$trunc(head->rde$pq_start_va); } ' } /* End of ascending header region */ /G* Descending header region */ if (head->rde$v_descend) { if (next == head) { /* Must be P1 region *// head->rde$pq_start_va = p1_start_va;( head->rde$q_region_size = size_of_p1; } if (next != head) {4 /* Don't allow if above header's first free va */* if (((uint64)start_va + region_size) > - ((uint64)head->rde$pq_first_free_va +  mmg$gl_page_size)) return (SS$_VA_IN_USE);, /* Calculate new start_va, region_size */ H head->rde$pq_start_va = / (VOID_PQ)((uint64)start_va + region_size); head->rde$q_region_size = & (uint64)p1_start_va + size_of_p1; head->rde$q_region_size -= # (uint64)head->rde$pq_start_va; } } /* All set */ return (SS$_NORMAL);$} /* End of $adjust_header_region */ /**++>* $remove_rde - Remove RDE from VA list and from region table.* * input: rde - RDE to remove!* head - RDE for VA list header*M* output: none - This routine should nIot fail. RDE passed in must be on the %* VA list and in the region table.*--*/-static void $remove_rde (RDE *rde, RDE *head){ /* External variables */: extern RDE * ctl$a_region_table[RDE$C_REGION_TABLE_SIZE]; /* Local variables */ int index; RDE *prev, *next; /* Remove from region table */> index = rde->rde$q_region_id & (RDE$C_REGION_TABLE_SIZE - 1);+ /* Special case: rde is at head of list */" prev = ctl$a_region_table[index]; if (rde == prev)5 ctl$a_Jregion_table[index] = rde->rde$ps_table_link; else  {$ /* Search for rde */! next = prev->rde$ps_table_link; while (next != rde) { prev = next;) /* Accvio if we run off end of list */# next = next->rde$ps_table_link;  }# /* Found it, take rde off list */4 prev->rde$ps_table_link = next->rde$ps_table_link; } /* Remove from VA list */" prev = rde->rde$ps_va_list_blink;" next = rde->rde$ps_va_list_flink;# prev->rde$ps_va_list_flink = next;K# next->rde$ps_va_list_blink = prev;! /* Adjust header if necessary */5 if (prev == head) $adjust_header_region(head, next);} /* End of $remove_rde */ /**++3* $update_peak_counters - Update CTL$ peak counters* * input: none** implicit inputs:* ctl$gl_pcb* ctl$gl_ipagefl* ctl$gq_virtpeak** output: none ** implicit outputs:* ctl$gl_ipagefl* ctl$gq_virtpeak*--*/(static void $update_peak_counters (void){ /* ExternalL variables */ extern PCB * const ctl$gl_pcb; extern PHD * const ctl$gl_phd;" extern uint32 ctl$gl_ipagefl;# extern uint64 ctl$gq_virtpeak;- extern const uint64 mmg$gq_process_va_pages; /* Local variables */ JIB *jib; uint32 pf_pages_used; uint64 virtual_pages_used;" /* Update peak page file usage */ jib = ctl$gl_pcb->pcb$l_jib;; pf_pages_used = jib->jib$l_pgflquota - jib->jib$l_pgflcnt;/ if (pf_pages_used > ctl$gl_phd->phd$l_ipagefl) {/ ctl$gl_phd->pMhd$l_ipagefl = pf_pages_used;$ ctl$gl_ipagefl = pf_pages_used; }% /* Update peak virtual page usage */Q virtual_pages_used = mmg$gq_process_va_pages - ctl$gl_phd->phd$q_free_pte_count;5 if (virtual_pages_used > ctl$gl_phd->phd$q_virtpeak) {5 ctl$gl_phd->phd$q_virtpeak = virtual_pages_used;* ctl$gq_virtpeak = virtual_pages_used; }$} /* End of $update_peak_counters */ /* $keep_in_ws *@ * Keep range of pages between va1 and va2 in the working set. N * E * Input: va1 - Beginning range of pages to be kept in working set. 4 * -1 if no longer require pages to be kept.< * va2 - Ending range of pages to be kept in working set.& * 0 if only one page to keep.4 * -1 if no longer require pages to be kept. * F * To keep just one page in the working set, $keep_in_ws us called as * follows: * * $keep_in_ws (va, 0); *E * To keep a range of pages in the working set, $keep_in_ws is called * as follows: *"O * $keep_in_ws (start_va, end_va); *N * When done requiring that pages be in working set, $keep_in_ws is called as * follows: * * $keep_in_ws (DONE_KIWS); */)#define DONE_KIWS (VOID_PQ)-1,(VOID_PQ)-13static void $keep_in_ws (VOID_PQ va1, VOID_PQ va2) { /* External variable */ extern PCB * const ctl$gl_pcb;D /* If VAs are both -1, we no longer want to keep pages in the WS */2 if (((__int64)va1 == -1) && ((__int64)va2 == -1)) {- ctl$gl_pcb->pcb$q_keep_in_ws = P-1;- ctl$gl_pcb->pcb$q_keep_in_ws2 = -1; return; }, /* Store VAs in PCB fields for pagefault */ if (va2 != 0)/ ctl$gl_pcb->pcb$q_keep_in_ws2 = (__int64)va2;- ctl$gl_pcb->pcb$q_keep_in_ws = (__int64)va1;F /* Synchronize with pagefault if this process can be multithreaded */' if (ctl$gl_pcb->pcb$l_multithread > 1) {8 sys_lock(MMG,1,0); /* Synch with pagefault */" sys_unlock(MMG,IPL$_ASTDEL,0);  }} /* $stx_to_entry * 5* Convert section tableQ index to section table entry*(* Input: phd - Process or system header* stx - Section table index*&* Output: section table entry address**/1static SECDEF * $stx_to_entry (PHD *phd, int stx){< return ((SECDEF *)((int)phd + phd->phd$l_pst_base_offset 2 - (SEC$C_LENGTH * stx)));} 8/* $is_mem_res - Is page a memory-resident section page ** Input: PTE contents,* if invalid, slave PTE * if valid, slave or master PTE** Output: 0, if Rnot MRES* 1, if MRES *(* Environment: MMG spinlock must be held*/ static int $is_mem_res (PTE pte){  /* External variables */' extern PTE_PQ const mmg$gq_gpt_base; /* Local variables */ PFN_PQ entry; PTE gpte; PFN_T pfn = 0; int gstx; SECDEF * gste;! /* If pte is valid, get pfn */ if (pte.pte$v_valid) pfn = pte.PTE$V_ARCH_PFN; else { /* PTE is invalid */F if (pte.pte$v_typ1) return (0); /* file backed proceSss page */ if (pte.pte$v_typ0) { /* global invalid */ /* Get GPTE */, gpte = mmg$gq_gpt_base[pte.pte$v_gptx];! /* If GPTE valid, get pfn */ if (gpte.pte$v_valid)# pfn = gpte.PTE$V_ARCH_PFN; else {7 /* GPTE not valid, reject types other than section */# if (!gpte.pte$v_typ0) return (0); /* Get gstx from master PTE */ gstx = gpte.pte$v_stx; } } else+ { /* transition or process dzro page */ pfn = pte.PTE$V_ARCH_PFTN;2 if (!pfn) return (0); /* process dzro page */ } } I /* If we have a PFN, check for SHMGS page or get gstx from pfn data */ if (pfn) { /* Get pfn database entry */ entry = pfn_to_entry (pfn);9 /* Reject non global writable section backing storage */5 if (entry->pfn$v_pagtyp != PFN$C_GBLWRT) return (0);; if (entry->pfn$v_shared) /* SHMGS page is resident; */3 return (1); /* no need to check the gste */$ if (!entry->pfn$v_typ0) return (0);% iUf (entry->pfn$v_gblbak) return (0); . /* Get gstx from BAK field in pfn database */ gstx = entry->pfn$v_stx; }6 /* Check the global section table entry for MRES */. gste = $stx_to_entry (mmg$gl_sysphd, gstx);% if (!gste->sec$v_mres) return (0); return (1);} 2/* $is_mapped_shpts - Is page mapped by shared PTs** Input: PTE VA*** Output: 0, if not mapped with shared PTs * 1, if mapped with shared PTs*(* Environment: Assumes IPL = IPL$_ASTDEL*/+staticV int $is_mapped_shpts (PTE_PQ va_pte){ /* External variables */ /* Local variables */ PFN_PQ entry; PTE_PQ l1pte, l2pte; SECDEF * gste; int old_ipl; PTE l1pte_contents;0 /* Get PFN database entry of L3PT/BPT PFN */> l2pte = bpte_va (va_pte, PSL$C_KERNEL); // PD PTE on X86= l1pte = bpte_va (l2pte, PSL$C_KERNEL); // PDPT PTE on X86< /* Verify upper level PTs exist before touching L3PT/BPT */6#ifdef __x86_64 // Verified for x8W6 port--Drew Mason PTE_PQ pml4pte; PTE pml4pte_contents;, pml4pte = bpte_va (l1pte, PSL$C_KERNEL);+ $read_pte (pml4pte, &pml4pte_contents);' if (!pml4pte_contents.pte$v_valid) return (0);#endif' $read_pte (l1pte, &l1pte_contents);? if ((!l1pte_contents.pte$v_valid) || (!l2pte->pte$v_valid)) return (0);1 entry = pfn_to_entry (l2pte->PTE$V_ARCH_PFN);- /* Is this a valid Galaxy shared page? */9 if ((!entry->pfn$v_shared) || (!entry->pfn$v_zXeroed)) {$ /* No: perform additional checks */2 /* If L3PT PFN page type is not global write, the$ PFN cannot be a shared PT PFN */) if (entry->pfn$v_pagtyp != PFN$C_GBLWRT) return (0);6 /* If the type 0 bits and the WRT bits are clear, but= the page type of a L3PT is global write, the entry* is in an inconsistent state. */1 if ((!entry->pfn$v_wrt) && (!entry->pfn$v_typ0))) bug_check (INCONMMGST, FATAL, COLD);4 /* Compute the address of the sYhared PT section and9 verify that the shared PTs bit is set; if it's: clear, the GSTE is in an inconsistent state. */8 gste = $stx_to_entry (mmg$gl_sysphd, entry->pfn$v_stx); if (!gste->sec$v_shared_pts)) bug_check (INCONMMGST, FATAL, COLD); } return (1);} B/* $is_last_section_page - Is the specified page the last page in* section*0* This routine assumes that VA in question/* is part of a global section mapped into* Z a shared PT region.** Input: Virtual Address*%* Output: 0, if not last section page* 1, if last section page*(* Environment: Assumes IPL = IPL$_ASTDEL**/-static int $is_last_section_page (VOID_PQ va){ /* External variables */& extern int const mmg$gl_page_size;( extern PTE_PQ const mmg$gq_gpt_base;4 extern SHM_DESC_PQ const glx$gpq_shm_desc_array; /* Local variables */ PTE_PQ l1pte, l2pte, l3pte; PTE gpte;$ int old_ipl, pa[gelets_per_page;C uint32 gptx, last_gptx, gstx, last_section_page, shm_reg_index; PFN_T pfn, last_section_pfn; PFN_PQ entry; SECDEF * gste;= pagelets_per_page = mmg$gl_page_size / VA$C_PAGELET_SIZE; sys_lock (MMG, 1, &old_ipl);; /* Verify upper level PTs exist before touching L3PT */ l1pte = l1pte_va (va); l2pte = l2pte_va (va); l3pte = pte_va (va);7 if ((!l1pte->pte$v_valid) || (!l2pte->pte$v_valid)) { sys_unlock (MMG, old_ipl, 1\); return (0); } if ((l3pte->pte$v_valid) || L ((!l3pte->pte$v_valid) && (l3pte->PTE$V_ARCH_PFN) && (!l3pte->pte$v_typ0))) {6 /* Valid or transition form: top part of PTE is a PFN */. entry = pfn_to_entry (l3pte->PTE$V_ARCH_PFN); if (entry->pfn$v_shared) { /* Galactic section page:F Find the gstx in the SHM_REG descriptor, then check that "our"- page is the last page in this section */< shm_reg_index = entry->pfn$r_shm_reg_id.shm_i]d$w_index;B gstx = glx$gpq_shm_desc_array[shm_reg_index].shm_desc$l_gstx;0 gste = $stx_to_entry (mmg$gl_sysphd, gstx);+ last_section_page = gste->sec$l_vpx + 3 (gste->sec$l_unit_cnt / pagelets_per_page) - 1;J last_section_pfn = mmg$gq_gpt_base[last_section_page].PTE$V_ARCH_PFN;" sys_unlock (MMG, old_ipl, 1);3 if (last_section_pfn == l3pte->PTE$V_ARCH_PFN) return 1; return 0; } else { /* Normal global page */) gptx = (int) entry->p^fn$q_pte_index; gste = $stx_to_entry ( mmg$gl_sysphd, entry->pfn$v_stx); } } else { gptx = l3pte->pte$v_gptx;% gpte = mmg$gq_gpt_base[gptx]; if (gpte.pte$v_valid) {& pfn = gpte.PTE$V_ARCH_PFN;& entry = pfn_to_entry(pfn);$ gstx = entry->pfn$v_stx; } else {" gstx = gpte.pte$v_stx; } gste = $stx_to_entry (" mmg$gl_s_ysphd, gstx); }? last_gptx = (gste->sec$l_unit_cnt / pagelets_per_page) - 1;! last_gptx += gste->sec$l_vpx;! sys_unlock (MMG, old_ipl, 1); if (gptx != last_gptx) return (0);E /* If we reach this point, the specified page represents the last page of the section */ return (1);} D/* $is_valid_delete_range - Does the specified range of addresses to/* wholly contain mappings using shared PT* sections.*0* ` This routine assumes the specified range1* maps one or more global sections and that3* the range wholly resides within a shared PT* region.** Input: PTE contents,*J* Output: 0, start va or end va do not lie on an even PT page boundary, if!* they are mapped by shared PTs** 1, if the range is "PT page inclusive"*(* Environment: Assumes IPL = IPL$_ASTDEL**/Jstatic int $is_valid_delete_range (VOID_PQ start_va, uint64 delete_length){ /* Extaernal variables */* extern const uint64 mmg$gq_page_size;' extern const int mmg$gl_bwp_width;) extern const int mmg$gl_level_width;+ extern const int *mmg$ar_gh_ps_vector; /* Local variables */ VOID_PQ va, end_va; PTE_PQ end_va_pte;& PTE pte_contents, zero_pte = {0}; uint64 bytes_mapped_by_l3pt;N bytes_mapped_by_l3pt = (uint64)1<<(mmg$gl_bwp_width + mmg$gq_level_width);G /* If the first page to be deleted is mapped by a shared PT bsection8 it must be aligned to the greater of PT of GH. */- if ($is_mapped_shpts (pte_va (start_va))) { PTE l3pte = *pte_va (start_va);& uint64 bytes_mapped_by_gh, min_align; if (l3pte.pte$v_valid) {6#ifdef __x86_64 // Verified for x86 port--Drew MasonK bytes_mapped_by_gh = mmg$gl_page_size; // no granularity hints on x86#elseI bytes_mapped_by_gh = (uint64)1< * Keep range of pages between va1 and va2 in the working set,+ * by atomically updatinfg PCB$Q_KEEP_IN_WS. *C * Input: va1 - Beginning range of pages to be kept in working set. *@ * va2 - Ending range of pages to be kept in working set.+ * 0 if only one page to keep. * * pcb - PCB address. *R * To keep just one page in the working set, $atomic_write_keep_in_ws us called as * follows: *. * $atomic_write_keep_in_ws (va, 0, pcb); *E * To keep a range of pages in the working set, $keep_in_ws is called * as follows: *9 * $atomigc_write_keep_in_ws (start_va, end_va, pcb); * * Output: none * U * Note: To release a range of pages, write -1 into PCB$Q_KEEP_IN_WS2 (must be first)< * followed by memory barrier and -1 into PCB$Q_KEEP_IN_WS. * */Dstatic void $atomic_write_keep_in_ws(int64 va1, int64 va2, PCB *pcb){ PHD *phd;= volatile void *addr = (void *)&pcb->pcb$q_keep_in_ws; int status; volatile unsigned int *frewsl; ' if(pcb->pcb$l_multithread <=h 1) {#ifdef MON_VERSION# if (pcb->pcb$q_keep_in_ws != -1) ' bug_check(INCONMMGST, FATAL, COLD); #endif, pcb->pcb$q_keep_in_ws = va1; if (va2 != 0)5 pcb->pcb$q_keep_in_ws2 = va2; return; }3 /* Store VAs in PCB fields for pagefault */ while(1) {5 while(pcb->pcb$q_keep_in_ws != -1) {}#ifdef __alpha ? status = __CMP_STORE_QiUAD(addr, -1, va1, addr);#else* status = __CMP_SWAP_QUAD(addr, -1, va1);#endif! if(status) break; } if (va2 != 0), pcb->pcb$q_keep_in_ws2 = va2; phd = pcb->pcb$l_phd; frewsl = &phd->phd$l_flags; __MB();) while(*frewsl & PHD$M_FREWSLE_ACTIVE) {}}R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined requjired ptr size */#endif##endif /* __MMG_FUNCTIONS_LOADED */wwZU#ifndef __MMG_ROUTINES_LOADED#define __MMG_ROUTINES_LOADED 1 /* module MMG_ROUTINES.H "X-106"*I*************************************************************************I* *I* HPE CONFIDENTIAL. This software is confidential proprietary software *I* licensed by Hewlett Packard Enterprise Development, LP, and is not *I* authkorized to be used, duplicated or disclosed to anyone without the *I* prior written permission of HPE. *I* Copyright 2017 Hewlett Packard Enterprise Development, LP *I* *I* VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *I* proprietary software licensed by VMS Software, Inc., and is not *I* authorized to be used, duplicated or disclosed to anyolne without *I* the prior written permission of VMS Software, Inc. *I* Copyright 2017-2023 VMS Software, Inc. *I* *I************************************************************************** *++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS systemB* routines that begin with tmhe MMG$ and MMG_STD$ prefixes and have* a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn' nt matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIBo]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* p The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* q integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.* /* 6. Mixed pointer sizes within one argumentF* If a 64-bit pointer is being passed by reference, the reference to ?* the pointer should also be 64 bits wide to avoid confusion. * For example:* * PTE_PPQ va_pte_p;* VOID_PPQ start_va_p; ** should be used instead of:** PTE_PQ *va_pte_p;* VOID_PQ *start_va_p;* * AUTHOR:* * Leonard S. Szubowiczr* * CREATION DATE: 9-Jun-1993* * MODIFICATION HISTORY:*+* X-106 CV Camiel Vanderhoeven 5-May-2023* Add mmg$page_present*+* X-105 GHJ Gregory H. Jordan 21-Mar-2023A* Update the interfaces to mmg$$valid_l3pte and mmg_std$frewsle.9* Add a new X86 specific routine mmg$bufobj_page_tables.*+* X-104 GHJ Gregory H. Jordan 3-Mar-2022** X-103 CMOS Christian Moser 04-Nov-2021&* Remove the VMS$NOSVAPTE conditional*A* X-102 CEG0916 Clair Grant s 25-Sep-2020'* Change comment in X-101*)* X-101 CEG0907 Clair Grant 24-Sep-2020** Replace "// comment" style to eliminate+* confusion when compiling /STANDARD=VAXC.*+* X-100 GHJ Gregory H. Jordan 27-Aug-2020@* Change the protection argument in mmg_std$map_from_lists from.* a uint32 to instead be PROTO_PTE proto_pte.*D* X-99 LMN Lisa Nevin 4-Jun-2020H* Add prototype for mmg$bpte_va - a routine wraptper around6* bpte_va macro (mainly added for bliss)*#* X-98 AHM Drew Mason 7-Jan-2020;* Add prototypes for mmg$$valid_l3pt, mmg_std$frewsle, and* mmg_std$make_wsle_64.*#* X-97 RCL Rick Lord 11-Mar-2019* Add MMG$IOUNLOCK_EXTS*K* X-96 MLW Michael Winiarski 28-Feb-2019E* Fix function prototype for mmg_std$map_pfns_gh() ... >* protection data-type from uint32 to PROTO_PTE.*)* X-95 MJM Michae ul Moroney 22-Jun-2018@* Remove some #ifdef VMS$PFNBITS_32 conditionals that prevented?* prototype definitions of some routines used for Itanium/X86.*** X-94 GHJ Gregory H. Jordan 18-Jun-2018>* Change the protection field in mmg_std$alloc_map_pfns to be<* a PROTO_PTE. Note that this does change the field from aC* uint32 on Alpha and IA64 to now be an int. The only CC callers @* for VMS pass constants so there is no impact but could impact** other callers that pass a uint32 fiveld.* ** X-93 GHJ Gregory H. Jordan 5-Jun-2018>* Change the proto_pte parameter for a number of MMG routines@* to be PROTO_PTE (defined in PTEDEF.SDL). This will be defined5* as an int for Alpha and IA64 and as a PTE for X86.*** X-92 GHJ Gregory H. Jordan 16-May-20182* Add the X86 specific routine mmg$write_pte_x86.* "* X-91 RCL Rick Lord 26-Mar-2018;* Add upper case constant and prototype for mmg$page_size,+* needed on IA64 for NOSVAPTE development.*:* X-90 CEGw0299 Clair Grant 19-Oct-2017&* Verified conditionals for x86 port.)* Updated copyright to VSI.*)* X-89 GHJ Gregory H. Jordan 10-Feb-20094* The routine mmg$create_vhpt no longe has an input * parameter.*)* X-88 RAB Richard A. Bishop 30-Oct-20084* Tweak to previous. The two routines must pass PFN9* back via PFN_T* instead of uint64* so they can be used* transparently on Alpha.*)* X-87 RAB Richard A. Bishop 23-Oct-2008<* Add variants xof MMG$ALLOC_SVA_MAP & MMG$ALLOC_PFN_MAP_SVA8* that will output a 64-bit PFN (MMG$ALLOC_SVA_MAP_64 &5* MMG$ALLOC_PFN_64_MAP_SVA). Fix comments describing6* optional arguments to MMG_STD$ALLOC_SYSTEM_VA_MAP &8* MMG_STD$ALLOC_PFN_MAP_SYSTEM_VA. Remove definition of2* MMG_STD$ALLOC_CTG_PFN_MAP_SVA, it is private to* [SYS]SYSVA_ALLOC.C.*** X-86 KLN3450 Karen L. Noel 5-Mar-2004* Use vms$defs.h.*"* X-85 Andy Kuehnel 1-Mar-2004E* More (final ?) changes to interfaces of new mymg$alloc... routines.*"* X-84 Andy Kuehnel 27-Feb-2004%* Tweak mmg$alloc_pfn_map interface.*"* X-83 Andy Kuehnel 20-Feb-20048* - Add optional page_prot to mmg_std$setsecprotown_64.B* - Change to parameters for mmg$allocate_contig_pfns and friends*!* X-82 Clair Grant 19-Feb-20048* Replace arch_defs.h with vms$defs.h and add temporary9* definition here until the build mechanism is in place.*** X-81 KLN3436 Karen L. Noel 13-Feb-2004 * Fix typo.*3* X-80 Claizr Grant Friday the 13th-Feb-2004&* Add new routines for expanded PFNs.*)* X-79 KLN3420 Karen L. Noel 6-Feb-2004* Use PFN_T type.*** X-78 KLN3410 Karen L. Noel 12-Jan-2004* Promote some PFNs to 64-bit.*** X-77 KLN3351 Karen L. Noel 10-Sep-2003* Add more VHPT routines.*)* X-76 KLN3343 Karen L. Noel 2-Sep-2003%* Add mmg$invalidate_vhpt* routines.*** X-75 KLN3322 Karen L. Noel 28-Jul-2003(* Add mmg$setup_tr and mmg$create_vhpt.*** X-74 KLN3290 {Karen L. Noel 10-Jul-2003/* Add mmg$lkwset_int and mmg$lock_linker_data."* Add mmg$invo_context* routines.*)* X-73 KLN3280 Karen L. Noel 1-May-2003* Add mmg$find_stack_peak.*$* X-72 DAG Doug Gordon 17-Oct-2002"* Add mmg_std$alloc_stack_va_map.*&* X-71 KLN Karen L. Noel 22-May-2002* Fold from Ruby,* X-67A1 KLN3061 Karen L. Noel 10-May-2002* Add mmg$alloc_contig_range.*"* X-70 Andy Kuehnel 7-May-20026* Add prototype for mmg_std$ins_pfnt_64 now that it's|* being used.*** X-69 KLN3060 Karen L. Noel 25-Apr-2002;* Add declarations for mmg_std$alcstx and mmg_std$dalcstx.*** X-68 KLN3031 Karen L. Noel 05-Mar-2002* Add mmg$check_va_access.*** X-67 KLN2213 Karen L. Noel 08-Mar-2001* Add mmg$update_sysptbr.*%* X-66 WBF Burns Fisher 26-Jan-20018* Add ifdef to inhibit new proto in function definition4* (required because of the way we do optional args)*%* X-65 WBF Burns Fisher 26-Jan-2001.* Add proto for mmg_std}$alloc_ctg_pfn_map_sva*** X-64 KLN2172 Karen L. Noel 29-Mar-2000* Add proto for mmg$va_to_rad.*"* X-63 Andy Kuehnel 23-Mar-2000?* Allow optional start_pfn argument in mmg_std$return_res_mem.*** X-62 KLN2118 Karen L. Noel 09-Dec-1999.* NUMA is now RAD (Resource Affinity Domain).*** X-61 KLN2117 Karen L. Noel 24-Nov-19991* Add color PFN allocation routine declarations.*)* X-60 RAB Richard A. Bishop 29-Oct-19982* Add MMG$MEM_CONFIG_INFO and MMG$MEM_CONFIG_PFN. ~+* They used to be GLX$* in GLX_ROUTINES.H.*-* X-59 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*** X-58 KLN2077 Karen L. Noel 20-May-1998:* o Add void to prototypes that have no arguments so that6* level 4 checking can be used with the C compiler.** o Add prototype for mmg$pfncheck_range.*)* X-57 EMB Ellen M. Batbouta 26-Feb-1998!* Add Mmg$ptecheckw_process_ast.*** X-56 KLN2052 Karen L. Noel 12-Feb-1998!* Add PTE/PFN checking routines.*"* X-55 Andy Kuehnel 15-Sep-19973* mmg_std$global_fast_map_64 does return a status.*"* X-54 Andy Kuehnel 20-Jun-19979* Fix a build bug: the struct name for private PFN lists7* conflicts with existing private definitions in other* facilities.*"* X-53 Andy Kuehnel 16-Jun-1997* More XFC infrastructure.9* - The following routines were eliminated after a major* re-design:* mmg_std$fluid_increase* mmg_std$fluid_decrease* mmg_std$alloc_freepte* mmg_std$dealloc_freepte:* - The call interface for mmg_std$establish_freepte_list * changed.'* - The following routines were added:* mmg_std$insque_free_pte* mmg_std$remque_free_pte*"* X-52 Andy Kuehnel 12-Jun-1997?* MMG_STD$MAP_PFNS is MMG_STD$MAP_PFNS_GH to satify the latest* review comments.*"* X-51 Andy Kuehnel 22-May-19979* Replace MMG_STD$UNMAP_PFNS with MMG_STD$ALLOC_MAP_PFNS*"* X-50 Andy Kuehnel 30-Jan-19978* (Don't know what happened to X-49; VDE expects X-50.)1* Allow an additional optional flags argument in7* mmg_std$ref_bufobj to support buffer objects without* associated system space.*)* X-48 EMB Ellen M. Batbouta 21-Oct-1996/* Fix build bug introduced with previous edit.*)* X-47 EMB Ellen M. Batbouta 18-Oct-19968* Add mmg_std$rem_pfnh_64 and mmg$compute_mem_checksum.*)* X-46 EMB Ellen M. Batbouta 06-Sep-1996* Add mmg$test_page.*-* X-45 NYK661 Nitin Y. Karkhanis 29-Aug-1996>* Add mmg_std$create_shpt_mapping_64, mmg_std$delete_pts, and* mmg_std$delete_private_l3pt.*)* X-44 KLN1572 Karen L. Noel 6-Aug-1996.* Add return status to mmg_std$return_res_mem*-* X-43 NYK647 Nitin Y. Karkhanis 30-Jul-1996+* o Add prototype for mmg_std$ins_pfnh_64.7* o Change type of copy_address in mmg_std$copy_rmd to&* RMD * for Dave Wall.*** X-42 DFW0274 David F. Wall 23-Jul-1996&* Add prototype for MMG_STD$COPY_RMD.*** X-41 KLN1570 Karen L. Noel 18-Jul-1996:* Fix protos for TBI_DATA routines. The call entry points* are the _std routines.*** X-40 KLN1553 Karen L. Noel 17-Jun-1996$* Move RES_MEM* flags to mmgdef.sdl*** X-39 KLN1550 Karen L. Noel 29-May-1996** o Add mmg_std$add_pt_win_cnt prototype 5* o Add mmg_flags argument to mmg_std$try_all_64 and* mmg_std$derive_granhint_64*** X-38 KLN1548 Karen L. Noel 24-May-1996;* o One more interface change to reserved memory routines..* o Change name of mmg_std$gpfile_gste_64 to * mmg_std$gdzro_gste_64*)* X-37 KLN1547 Karen L. Noel 7-May-19966* Refine reserved memory routine interfaces based on '* changes to functional specification.*** X-36 KLN1545 Karen L. Noel 22-Apr-19967* Add new reserved memory routines, mmg_std$*_res_mem.:* Add name argument to existing reserved memory routines.*** X-35 KLN1542 Karen L. Noel 27- Mar-1996** o Add new MMG_STD$ALLO_CONTIG routines..* o Add new routine MMG_STD$DALLOC_CONTIG_PFN/* o Add new routine MMG_STD$DALLOC_ZERO_PFN_64* ** X-34 KLN1541 Karen L. Noel 22-Mar-1996"* o Restore lost edits (whoops!).C* o Add prototypes for MMG_STD$ALLO_CONTIG* routines.** o Add prototype for MMG_STD$REM_PFN_64.*** X-33 KLN1531 Karen L. Noel 16-Oct-1995?* Change name of mmg_std$gblsec_privchk to mmg_std$sec_privchk+* because it now handles private sections.*C* X-32 NYK494 Nitin Y. Karkhanis 4-Oct-1995D* Add MMG$ALLOC_PFN_ALGND_64, MMG$ALLOC_ZERO_ALGND_64,** MMG_STD$ALLOC_ZERO_PFN_64.*C* X-31 LSS0353 Leonard S. Szubowicz 21-Jul-1995B* 64-bits: Add prototype for MMG_STD$GET_PTE_FOR_VA.*** X-30 KLN1482 Karen L. Noel 20-Jul-1995* Make page counts 64 bits.*** X-29 KLN1478 Karen L. Noel 18-Jul-1995* Type gs_name as VOID_PQ.*** X-28 KLN1472 Karen L. Noel 11-Jul-19953* For mmg_std$delpag_64, make page count unsigned.*-* X-27 NYK449 Nitin Y. Karkhanis 30-Jun-1995#* Add mmg_std$alloc_system_va_map,I* mmg_std$alloc_pfn_map_system_va, & mmg_std$del_contents_pfn_64.*** X-26 KLN1460 Karen L. Noel 19-Jun-19951* Add WSL address as input to mmg_std$lckulkpag.*** X-25 KLN1452 Karen L. Noel 22-May-1995* Add routine mmg$pteref_64.*** X-23 KLN1443 Karen L. Noel 25-Apr-1995#* Add routine mmg_std$dea lloc_sva.*-* X-22 NYK353 Nitin Y. Karkhanis 11-Apr-1995?* MMG_STD$ALLOC_PFN and MMG_STD$DALLOC_PFN underwent interfaceA* changes in order to support a PFN database in S2 space. "_64"** has been appended to the routine names.*-* X-21 NYK342 Nitin Y. Karkhanis 6-Apr-1995@* Use long PFN database entry pointers (i.e. PFN_PQ and PFN_PPQ * instead of PFN * and PFN **).*0* X-20 LSS0336 Leonard S. Szubowicz 28-Mar-1995C* 64-bits: More appropriate parameter types for mmg_std$s vaptechk.*0* X-19 LSS0330 Leonard S. Szubowicz 9-Mar-1995:* 64-bits: Remove mmg_std$lock_mem and mmg_std$unlock_mem<* which turn out to be inappropriate for their intended use6* as replacements for mmg$iolock in PROCESS_SCAN.MAR.*0* X-18 LSS0328 Leonard S. Szubowicz 7-Mar-19959* 64-bits: Add prototypes for mmg_std$lock_mem, mmg_std$@* unlock_mem; mmg_std$iounlock_buf replaces mmg_std$unlock_buf.@* Remove soon-to-be-obsolete mmg_std$iolock and mmg_std$unlock.*-* X-17 EMB0355 Ellen M. Batbouta 02-Mar-1995?* Add function prototypes for mmg$tbi_single_threads, mmg$tbi_(* data_64, and mmg$tbi_data_64_threads.*)* X-16 KLN1378 Karen L. Noel 3-Feb-19957* Clean up MMG prototypes so they can be used with old:* or new C compiler. Add rule about mixing pointer sizes* within an argument.*)* X-15 KLN1376 Karen L. Noel 1-Feb-1995B* Conditionalize GSD scan routine based on using 64-bit compiler.*** X-14 KLN1365 Karen L. Noel 18-Jan-1995:* Add prototypes for 64-bit working set service routines.*** X-13 KLN1362 Karen L. Noel 12-Jan-1995>* Fix prototype for mmg_std$gsdscan and mmg_std$chkpro_audit.*0* X-12 LSS0314 Leonard S. Szubowicz 10-Jan-1995;* 64-Bits: Add function prototypes for mmg_std$iolock_buf,C* mmg_std$unlock_buf, mmg_std$decptref_pfndb, mmg_std$lockpgtb_64.*)* X-11 KLN1360 Karen L. Noel 5-Jan-1995* Add mmg_std$gblsec_privchk.*)* X-10 KLN1359 Karen L. Noel 3-Jan-1995.* ...more prototypes for 64-bit MMG services.*)* X-9 KLN1355 Karen L. Noel 21-Dec-1994/* Add more prototypes for 64-bit MMG services.*)* X-8 KLN1353 Karen L. Noel 15-Dec-1994<* Fix build bug where SECDEF isn't correct if __NEW_STARLET* is not defined.*(* X-7 KLN1351 Karen L. Noel 9-Dec-1994:* Fix proto for mmg_std$try_all_64 and add more routines.*(* X-6 KLN1347 Karen L. Noel 5-Dec-1994* More 64-bit MMG routines.*)* X-5 KLN1342 Karen L. Noel 28-Nov-1994;* Declare function prototypes for new 64-bit MMG routines.*,* X-4 NYK099 Nitin Y. Karkhanis 3-Nov-19948* Declare function prototypes for mmg_std$alloc_gpt and* mmg_std$dealloc_gpt.* 1* X-3 JCH703 John C. Hallyburton, Jr. 1-Nov-1994(* Add mmg$ref_bufobj, mmg$deref_bufobj.*/* X-2 LSS0308 Leonard S. Szubowicz 5-May-1994>* Add function prototypes for mmg$tbi_all and mmg$tbi_single.*0* X-1 LSS0279 Leonard S. Szubowicz 9-Jun-1993@* Initial version containing only those routines commonly used*  by device drivers.* *--*/R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define all types that are used in the following function prototypes.*/#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /*P VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of t he /NAME=AS_IS compiler switch.*/6#define mmg_std$add_pt_win_cnt MMG_STD$ADD_PT_WIN_CNT2#define mmg_std$alloc_pfn_64 MMG_STD$ALLOC_PFN_64>#define mmg$alloc_pfn_algnd_64 MMG$ALLOC_PFN_ALGND_64@#define mmg$allocate_contig_pfns MMG$ALLOCATE_CONTIG_PFNS8#define mmg$allocate_pfn MMG$ALLOCATE_PFN<#define mmg$allocate_pfn_map MMG$ALLOCATE_PFN_MAPA#define mmg$allocate_sva_and_pfns MMG$ALLOCATE_SVA_AND_PFNSA#define mmg_std$alloc_zero_pfn_64 MMG_STD$ALLOC_ZERO_PFN_64?#define mmg$alloc_zero_algnd_64 MMG$ALLOC_ZERO_ALGND_640#define mmg_std$allo_contig MMG_STD$ALLO_CONTIG5#define mmg_std$allo_contig_a MMG_STD$ALLO_CONTIG_A 8#define mmg_std$allo_contig_pfn MMG_STD$ALLO_CONTIG_PFN<#define mmg_std$allo_contig_pfn_a MMG_STD$ALLO_CONTIG_PFN_A<#define mmg_std$dalloc_contig_pfn MMG_STD$DALLOC_CONTIG_PFN4#define mmg_std$dalloc_pfn_64 MMG_STD$DALLOC_PFN_64>#define mmg_std$dalloc_zero_pfn_64 MMG_STD$DALLOC_ZERO_PFN_64?#defin e mmg_std$del_contents_pfn_64 MMG_STD$DEL_CONTENTS_PFN_64,#define mmg_std$alloc_gpt MMG_STD$ALLOC_GPT0#define mmg_std$dealloc_gpt MMG_STD$DEALLOC_GPT6#define mmg_std$decptref_pfndb MMG_STD$DECPTREF_PFNDB2#define mmg_std$deref_bufobj MMG_STD$DEREF_BUFOBJ0#define mmg_std$lockpgtb_64 MMG_STD$LOCKPGTB_64.#define mmg_std$iolock_buf MMG_STD$IOLOCK_BUF2#define mmg_std$iounlock_buf MMG_STD$IOUNLOCK_BUF0#define mmg$iounlock_exts MMG$IOUNLOCK_EXTS.#define mmg_std$ref_bufobj MMG_STD$REF_BU FOBJ,#define mmg_std$svaptechk MMG_STD$SVAPTECHK%#define mmg$tbi_all MMG$TBI_ALL*#define mmg$tbi_single MMG$TBI_SINGLE9#define mmg$tbi_single_threads MMG$TBI_SINGLE_THREADS0#define mmg_std$tbi_data_64 MMG_STD$TBI_DATA_64?#define mmg_std$tbi_data_64_threads MMG_STD$TBI_DATA_64_THREADS-#define mmg_std$delpag_64 MMG_STD$DELPAG_64.#define mmg_std$delete_pts MMG_STD$DELETE_PTS?#define mmg_std$delete_private_l3pt MMG_STD$DELETE_PRIVATE_L3PT@#define mmg_std$check_contract_6 4_1 MMG_STD$CHECK_CONTRACT_64_1<#define mmg_std$check_contract_64 MMG_STD$CHECK_CONTRACT_64.#define mmg_std$try_all_64 MMG_STD$TRY_ALL_646#define mmg_std$fast_create_64 MMG_STD$FAST_CREATE_64.#define mmg_std$crepag_64 MMG_STD$CREPAG_64 E#define mmg_std$create_shpt_mapping_64 MMG_STD$CREATE_SHPT_MAPPING_648#define mmg_std$check_window_64 MMG_STD$CHECK_WINDOW_64#ifdef __NEW_STARLET4#define mmg_std$init_pste_64 MMG_STD$INIT_PSTE_64 6#define mmg_std$gdzro_gste_64 MMG_STD$GDZRO_GSTE _64 6#define mmg_std$gfile_gste_64 MMG_STD$GFILE_GSTE_64 ;#define mmg_std$setsecprotown_64 MMG_STD$SETSECPROTOWN_64 4#define mmg_std$chkpro_audit MMG_STD$CHKPRO_AUDIT >#define mmg_std$global_fast_map_64 MMG_STD$GLOBAL_FAST_MAP_64 #endif?#define mmg_std$sec_fast_create_64 MMG_STD$SEC_FAST_CREATE_64 E#define mmg_std$set_gh_and_fastmap_64 MMG_STD$SET_GH_AND_FASTMAP_64 ,#define mmg_std$init_orb MMG_STD$INIT_ORB *#define mmg_std$dalcstx MMG_STD$DALCSTX 0#define mmg_std$dalcstxscn  MMG_STD$DALCSTXSCN 0#define mmg_std$subsecrefl MMG_STD$SUBSECREFL ?#define mmg_std$derive_granhint_64 MMG_STD$DERIVE_GRANHINT_64 ?#define mmg_std$fastmap_with_gh_64 MMG_STD$FASTMAP_WITH_GH_64 E#define mmg_std$set_gh_and_fastmap_64 MMG_STD$SET_GH_AND_FASTMAP_64 6#define mmg_std$perform_audit MMG_STD$PERFORM_AUDIT .#define mmg_std$delgblwcb MMG_STD$DELGBLWCB .#define mmg_std$movgsdnam MMG_STD$MOVGSDNAM 8#define mmg_std$gblsec_privchk MMG_STD$GBLSEC_PRIVCHK -#define mmg_std$lc kulkpag MMG_STD$LCKULKPAG4#define mmg_std$purgwspag_64 MMG_STD$PURGWSPAG_64 4#define mmg_std$lckbufobjpag MMG_STD$LCKBUFOBJPAG 8#define mmg_std$delbufobjpages MMG_STD$DELBUFOBJPAGES 4#define mmg_std$setprtpag_64 MMG_STD$SETPRTPAG_64 4#define mmg_std$setfltpag_64 MMG_STD$SETFLTPAG_64 9#define mmg_std$has_priv_pswapm MMG_STD$HAS_PRIV_PSWAPM *#define mmg_std$gsdscan MMG_STD$GSDSCAN 0#define mmg_std$addprcpgfl MMG_STD$ADDPRCPGFL 2#define mmg_std$lock_gpt_64 MMG_STD$LOCK_GPT_6 4 4#define mmg$alloc_sva_map MMG$ALLOC_SVA_MAP9#define mmg$alloc_sva_map_64 MMG$ALLOC_SVA_MAP_64=#define mmg$alloc_pfn_map_sva MMG$ALLOC_PFN_MAP_SVA C#define mmg$alloc_pfn_64_map_sva MMG$ALLOC_PFN_64_MAP_SVA ?#define mmg_std$alloc_system_va_map MMG_STD$ALLOC_SYSTEM_VA_MAP=#define mmg_std$alloc_stack_va_map MMG_STD$ALLOC_STACK_VA_MAPG#define mmg_std$alloc_pfn_map_system_va MMG_STD$ALLOC_PFN_MAP_SYSTEM_VA2#define mmg_std$dealloc_sva MMG_STD$DEALLOC_SVA ,#define mmg$page_size MMG$PAGE_SIZE,#define mmg$pteref_64 MMG$PTEREF_64>#define mmg_std$get_pte_for_va MMG_STD$GET_PTE_FOR_VA2#define mmg_std$rem_pfn_64 MMG_STD$REM_PFN_64 1#define mmg_std$ins_pfnh_64 MMG_STD$INS_PFNH_641#define mmg_std$ins_pfnt_64 MMG_STD$INS_PFNT_640#define mmg_std$use_res_mem MMG_STD$USE_RES_MEM6#define mmg$use_res_mem_64 MMG$USE_RES_MEM_644#define mmg_std$free_res_mem MMG_STD$FREE_RES_MEM 8#define mmg_std$return_res_mem  MMG_STD$RETURN_RES_MEM *#define mmg_std$copy_rmd MMG_STD$COPY_RMD%#define mmg$test_page MMG$TEST_PAGE0#define mmg_std$map_pfns_gh MMG_STD$MAP_PFNS_GH6#define mmg_std$alloc_map_pfns MMG_STD$ALLOC_MAP_PFNSE#define mmg_std$establish_freepte_list MMG_STD$ESTABLISH_FREEPTE_LIST8#define mmg_std$insque_free_pte MMG_STD$INSQUE_FREE_PTE8#define mmg_std$remque_free_pte MMG_STD$REMQUE_FREE_PTEE#define mmg_std$establish_freepfn_list MMG_STD$ESTABLISH_FREEPFN_LIST8#define mmg_std$insque_free_ pfn MMG_STD$INSQUE_FREE_PFN8#define mmg_std$remque_free_pfn MMG_STD$REMQUE_FREE_PFN6#define mmg_std$map_from_lists MMG_STD$MAP_FROM_LISTS6#define mmg_std$unmap_to_lists MMG_STD$UNMAP_TO_LISTS##define mmg$pfncheck MMG$PFNCHECK.#define mmg$pfncheck_range MMG$PFNCHECK_RANGE4#define mmg$ptecheckw_process MMG$PTECHECKW_PROCESS2#define mmg$ptecheckw_system MMG$PTECHECKW_SYSTEM;#define mmg$ptecheckw_process_ast MMG$PTECHECKW_PROCESS_AST6#define mmg$alloc_pfn_color_64 MMG$ALLOC_PFN_CO LOR_648#define mmg$alloc_zero_color_64 MMG$ALLOC_ZERO_COLOR_64:#define mmg$alloc_contig_color_a MMG$ALLOC_CONTIG_COLOR_A 6#define mmg$alloc_contig_range MMG$ALLOC_CONTIG_RANGE.#define mmg$update_sysptbr MMG$UPDATE_SYSPTBR%#define mmg$va_to_rad MMG$VA_TO_RAD'#define mmg_std$alcstx MMG_STD$ALCSTX0#define mmg$find_stack_peak MMG$FIND_STACK_PEAK'#define mmg$lkwset_int MMG$LKWSET_INT2#define mmg$lock_linker_data MMG$LOCK_LINKER_DATA4#define mmg$invo_context_init MMG$INVO_CONTEX T_INIT8#define mmg$invo_context_malloc MMG$INVO_CONTEXT_MALLOC4#define mmg$invo_context_free MMG$INVO_CONTEXT_FREE4#define mmg$invo_context_done MMG$INVO_CONTEXT_DONE<#ifdef __ia64 /* Verified for x86 port - Clair Grant */##define mmg$setup_tr MMG$SETUP_TR'#define mmg$check_vhpt MMG$CHECK_VHPT)#define mmg$create_vhpt MMG$CREATE_VHPT)#define mmg$enable_vhpt MMG$ENABLE_VHPT)#define mmg$insert_vhpt MMG$INSERT_VHPT2#define mmg$invalidate_vhpt MMG$INVALIDATE_VHPT 6#def ine mmg$invalidate_vhpt_p MMG$INVALIDATE_VHPT_P =#define mmg$invalidate_vhpt_entry MMG$INVALIDATE_VHPT_ENTRY #endif/*N Function prototypes for system routines with the MMG$ and MMG_STD$ prefix.*/Ivoid mmg_std$add_pt_win_cnt (VOID_PQ va, PTE_PQ va_pte, int win_count); DPFN_T mmg$allocate_pfn (uint32 flags, int color, uint64 byte_align);}PFN_T mmg$allocate_contig_pfns (uint64 page_count, uint32 flags, int color, uint64 byte_align, PFN_T low_pfn, PFN_T high_pfn, UINT64_PQ la rgest_chunk);int mmg$allocate_sva_and_pfns (uint64 page_count, uint32 flags, int color, int system_region, PROTO_PTE proto_pte, int refcnt,  VOID_PPQ ret_sva);rint mmg$allocate_pfn_map (uint64 page_count, uint32 flags, int color, PFN_T low_pfn, PFN_T high_pfn, VOID_PQ sva, % PROTO_PTE proto_pte, int refcnt);.PFN_T mmg_std$alloc_pfn_64 (PFN_PPQ pfndbe_p);<PFN_T mmg$alloc_pfn_algnd_64 (uint64 vpn, PFN_PPQ pfndbe_p);3PFN_T mmg_std$alloc_zero_pfn_64 (PFN_PPQ pfndbe_p);=PFN_T mmg$allo c_zero_algnd_64 (uint64 vpn, PFN_PPQ pfndbe_p);-PFN_T mmg_std$allo_contig (uint32 pfn_count);@PFN_T mmg_std$allo_contig_pfn (uint32 pfn_count, PFN_T max_pfn);BPFN_T mmg_std$allo_contig_a (uint32 pfn_count, uint64 byte_align);UPFN_T mmg_std$allo_contig_pfn_a (uint32 pfn_count, uint64 byte_align, PFN_T max_pfn);>void mmg_std$dalloc_contig_pfn (PFN_T pfn, uint32 pfn_count);7void mmg_std$dalloc_pfn_64 (PFN_T pfn, PFN_PQ pfndbe);<void mmg_std$dalloc_zero_pfn_64 (PFN_T pfn, PFN_PQ pfndbe);=void mmg_std$del_contents_pfn_64 (PFN_T pfn, PFN_PQ pfndbe);>int mmg_std$alloc_gpt (const int req_pages, PTE_PPQ gpte_p);Dint mmg_std$dealloc_gpt (const int page_count, const PTE_PQ gpte);3void mmg_std$decptref_pfndb (PFN_PQ const pfndbe);Jvoid mmg_std$deref_bufobj (int32 object_handle_1, int32 object_handle_2);?int mmg_std$iolock_buf (VOID_PQ const buf, const int bufsiz, < const int is_read, PCB *const pcb,A PTE_PPQ va_pte_p, VOID_P PQ fault_va_p);Cvoid mmg_std$iounlock_buf (const int npages, PTE_PQ const va_pte);6int mmg$iounlock_exts (const EXT_PQ exts, int bcnt);@void mmg_std$lockpgtb_64 (PTE_PQ const va_pte, PHD *const phd);Ivoid mmg_std$svaptechk (VOID_PQ va, PCB *pcb, PHD *phd, PTE **svapte_p);void mmg$tbi_all (void);dint mmg_std$ref_bufobj (int32 object_handle_1, int32 object_handle_2, ...); /* [ uint32 flags ] */&void mmg$tbi_single (VOID_PQ va);.void mmg$tbi_single_threads (VOID_PQ va); 'void mmg_std$tbi_data_64 (VOID_PQ va);/void mmg_std$tbi_data_64_threads (VOID_PQ va);Iint mmg_std$delpag_64 (RDE *rde, VOID_PPQ start_va_p, uint64 *pages_1,  int acmode, int *mmg_flags);<void mmg_std$delete_pts (VOID_PQ start_va, VOID_PQ end_va);Gvoid mmg_std$delete_private_l3pt (PTE_PQ l3pt_va, PCB *pcb, PHD *phd);Ivoid mmg_std$check_contract_64_1 (RDE *rde, PHD *phd, VOID_PQ start_va);Gvoid mmg_std$check_contract_64 (RDE *rde, PHD *phd, VOID_PQ start_va,  VOID_PQ end _va);Dint mmg_std$try_all_64(RDE *rde, VOID_PQ start_va, VOID_PQ end_va,9 uint64 expbytes, uint64 pages, int *pagefile_cache_p,  int *mmg_flags_p);Hvoid mmg_std$fast_create_64(RDE *rde, VOID_PQ start_va, VOID_PQ end_va, uint64 pages, PTE prot_pte);Oint mmg_std$crepag_64(RDE *rde, VOID_PPQ va_p, uint64 *pages_1, int max_mode,; PTE proto_pte, int *pagefile_cache_p, int *mmg_flags_p);\int mmg_std$create_shpt_mapping_64 (RDE *rde, VOID_PPQ va_p, int64 *pages_1, int max_mode, ) PTE proto_pte, int *mmg_flags_p, ...);Fint mmg_std$check_window_64(int channel, CCB **ccb_p, int *efblk_p);F/* The following prototypes are only defined for __NEW_STARLET because8 * the type SECDEF is not defined in SECDEF.H otherwise. */#ifdef __NEW_STARLETKint mmg_std$init_pste_64(CCB *ccb, uint64 *pagelets_p, int section_flags,F uint64 start_vbn, int pfc_pagelets, int *efblk_p, SECDEF **pste_p,  int *pstx_p);Dint mmg_std$gfile_gste_64(GSD *gsd, CCB *ccb, uint64 *page lets_p, H int section_flags, uint64 start_vbn, int pfc_pagelets, int *efblk_p, * SECDEF **gste_p, unsigned int *gstx_p);Mint mmg_std$gdzro_gste_64(GSD *gsd, uint64 *pagelets_p, int section_flags, * SECDEF **gste_p, unsigned int *gstx_p);Oint mmg_std$setsecprotown_64(PTE *proto_pte_p, int section_flags, int acmode,J SECDEF *section_table_entry_p, GSD *gsd, ...); /* [uint32 page_prot] */Fint mmg_std$chkpro_audit(GSD *gsd, SECDEF *gste, int section_flags, ! int status, int calle rs_mode);Oint mmg_std$global_fast_map_64(VOID_PQ start_va, VOID_PQ end_va, uint64 pages, PTE proto_pte, SECDEF *gste);#endifNint mmg_std$sec_fast_create_64 (RDE *rde, VOID_PQ start_va, VOID_PQ end_va, 2 uint64 pages, PTE proto_pte, int mmg_flags); Gvoid mmg_std$set_gh_and_fastmap_64 (VOID_PQ start_va, VOID_PQ end_va, uint64 pages, PTE proto_pte);5int mmg_std$init_orb(GSD *gsd, CCB *ccb, int prot);)void mmg_std$dalcstx(int stx, PHD *phd);#void mmg_std$dalcstxscn(PHD  *phd);:void mmg_std$subsecrefl(int refcnt, int index, PHD *phd);@int mmg_std$derive_granhint_64(RDE *rde, VOID_PPQ start_va_p, 7 VOID_PPQ end_va_p, uint64 page_count, PTE proto_pte, int *mmg_flags_p);Bvoid mmg_std$fastmap_with_gh_64(VOID_PQ start_va, VOID_PQ end_va,% uint64 page_count, PTE proto_pte);Evoid mmg_std$set_gh_and_fastmap_64(VOID_PQ start_va, VOID_PQ end_va,% uint64 page_count, PTE proto_pte);2void mmg_std$perform_audit(GSD *gsd, int status);"void mmg_std$de lgblwcb(PCB *pcb);Avoid mmg_std$movgsdnam(char *dest_p, char *source_p, GSD *gsd); 8int mmg_std$sec_privchk(char *gs_string_p, int flags);Jint mmg_std$lckulkpag(VOID_PQ start_va, int acmode, int flags, PCB *pcb, PHD *phd, WSL_PQ wsl);Hvoid mmg_std$purgwspag_64(VOID_PQ start_va, int acmode, uint64 pages_1, int page_inc);Gint mmg_std$lckbufobjpag(VOID_PQ start_va, int acmode, int page_inc,  BOD *bod, PTE_PPQ va_pte_p);1void mmg_std$delbufobjpages(BOD *bod, PCB *pcb);Cin t mmg_std$setprtpag_64(RDE *rde, VOID_PQ start_va, int acmode, % int alpha_prot, int *prev_prot_p);Bint mmg_std$setfltpag_64(RDE *rde, VOID_PQ start_va, int acmode, int fault_mask);(int mmg_std$has_priv_pswapm(PCB *pcb);8void mmg_std$addprcpgfl(int pages, PHD *phd); 9void mmg_std$lock_gpt_64(PTE_PQ gpte, PHD *sys_phd,...);+int mmg_std$gsdscan(VOID_PQ input_gsnam, A UINT64_PQ input_ident, int section_flags, char *return_gsnam, $ uint64 *return_ident, GSD **gsd );Hint mmg$alloc_sva_map (PROTO_PTE proto_pte, int page_count, int refcnt, 3 PTE ** ret_svapte, void ** ret_sva, int *ret_pfn);Kint mmg$alloc_pfn_map_sva (PROTO_PTE proto_pte, int page_count, int refcnt,. PTE * svapte, void ** ret_sva, int *ret_pfn);Kint mmg$alloc_sva_map_64 (PROTO_PTE proto_pte, int page_count, int refcnt, 5 PTE ** ret_svapte, void ** ret_sva, PFN_T *ret_pfn);Nint mmg$alloc_pfn_64_map_sva (PROTO_PTE proto_pte, int page_count, int refcnt,0 PTE * svapte, void ** ret_sva, PFN_T *ret_pfn);'#ifndef MMG_STD$ALLOC_SYSTEM_VA_MAP_SRCQint mmg_std$alloc_system_va_map (const PROTO_PTE proto_pte, const int page_count,v const uint32 refcnt, const uint32 system_region, VOID_PPQ sva, ...); /* [VOID_PQ not_used, int rad, int rad_flags] */#endif+#ifndef MMG_STD$ALLOC_PFN_MAP_SYSTEM_VA_SRCUint mmg_std$alloc_pfn_map_system_va (const PROTO_PTE proto_pte, const int page_count,A const uint32 refcnt, VOID_PQ sva, ...); /* [PFN_T_PQ ret_pfn] */#endif6int mmg_std$deallo c_sva (int page_count, VOID_PQ sva);9int mmg$pteref_64 (VOID_PQ va, RDE *rde, PTE_PPQ va_pte);Lint mmg_std$get_pte_for_va (VOID_PQ const va, PHD *const phd, PTE_PQ pte_p);@void mmg_std$rem_pfn_64 (PFN_T pfn, int list, PFN_PQ pfndbe_p);@void mmg_std$ins_pfnh_64 (PFN_T pfn, int list, PFN_PQ pfndbe_p);@void mmg_std$ins_pfnt_64 (PFN_T pfn, int list, PFN_PQ pfndbe_p);6PFN_T mmg_std$rem_pfnh_64(int list, PFN_PPQ pfndbe_p);#ifdef VMS$PFNBITS_32gint mmg_std$use_res_mem (uint32 page_count, uint32 char_count, char *name, uint32 flags, uint32 group, / uint32 *return_pfn, uint32 *reserved_pages);#endif~int mmg$use_res_mem_64 (uint32 page_count, uint32 char_count, CHAR_PQ name, uint32 flags, uint32 group, UINT64_PQ return_pfn,2 UINT64_PQ reserved_pages);jint mmg_std$free_res_mem (uint32 char_count, char *name, uint32 flags, uint32 group, uint32 *freed_pages);int mmg_std$return_res_mem (uint32 page_count, uint32 char_count, char *name, uint32 flags, uint32 gro up, ...); /* uint32 start_pfn] */vint mmg_std$copy_rmd (uint32 rmd_count, uint32 char_count, char *name, uint32 flags, uint32 group, RMD *copy_address);'int mmg$test_page(uint32 *pfn_count_p);S#if defined(__alpha) || defined(__ia64) /* Verified for x86 port - Clair Grant */Jvoid mmg$compute_mem_checksum(PMREG *pmr, int32 bitmap_size, uint32 flag);#endif_int mmg_std$map_pfns_gh (PFN_T first_pfn, uint32 pfn_count, PROTO_PTE protection, VOID_PQ sva);Qint mmg_std$alloc_map_pfns (uint32 pfn_count, PROTO_PTE protection, VOID_PQ sva);Xint mmg_std$establish_freepte_list (PTELIST_PQ pte_list, VOID_PQ sva, uint64 pte_count);Qint mmg_std$insque_free_pte (PTELIST_PQ pte_list, VOID_PQ sva, uint64 pte_count);Dint mmg_std$remque_free_pte (PTELIST_PQ pte_list, uint64 pte_count);int mmg_std$establish_freepfn_list (uint32 count, void (*callback_routine)(PRVPFN_PQ pfn_list), uint32 priority, PRVPFN_PPQ prvpfn, UINT32_PQ return_count);Wint mmg_std$insque_free_pfn (PRVPFN_PQ pfn_list, uint3 2 count, UINT32_PQ return_count);?int mmg_std$remque_free_pfn (PRVPFN_PQ pfn_list, uint32 count);iint mmg_std$map_from_lists (PTELIST_PQ pte_list, PRVPFN_PQ prvpfn, PROTO_PTE proto_pte_in, VOID_PPQ sva);Pint mmg_std$unmap_to_lists (VOID_PQ sva, PTELIST_PQ pte_list, PRVPFN_PQ prvpfn);3int mmg$pfncheck (PFN_T pfn, UINT32_PQ which_list);6int mmg$pfncheck_range (PFN_T pfn, uint32 page_count);!int mmg$ptecheckw_process (void); int mmg$ptecheckw_system (void);3void mmg$ptecheckw_process_ast(P CB *pcb, ACB *acb);/#define mmg$mem_config_info MMG$MEM_CONFIG_INFO\ int mmg$mem_config_info (UINT32_PQ max_mem_desc_nodes_p, UINT32_PQ max_frag_per_node_p);-#define mmg$mem_config_pfn MMG$MEM_CONFIG_PFNe int mmg$mem_config_pfn (PFN_T pfn, INT_PQ page_type_p, UINT64_PQ part_id_p, UINT64_PQ comm_id_p);WPFN_T mmg$alloc_pfn_color_64 (uint32 flags, uint64 vpn, uint32 rad, PFN_PPQ pfndbe_p);YPFN_T mmg$alloc_zero_color_64 (uint32 flags, uint64 vpn, uint32 rad, PFN_PPQ pfndbe_p); { PFN_T mmg$alloc_contig_color_a (uint32 pfn_count, uint32 flags, uint64 byte_align, uint32 rad, UINT32_PQ largest_chunk_p); }PFN_T mmg$alloc_contig_range (PFN_T min_pfn, uint32 pfn_count, PFN_T max_pfn, uint64 byte_align, UINT32_PQ largest_chunk_p); void mmg$update_sysptbr(void);0int mmg$va_to_rad (VOID_PQ va, UINT32_PQ rad_p);.unsigned int mmg$check_va_access (VOID_PQ va);Gint mmg_std$alcstx (PCB * pcb_p, PHD * phd_p, unsigned int * stx_p); Pint mmg_std$alloc_stack_va_map (const PROTO_PTE proto_pte, const int page_count,@ const uint32 refcnt, const uint32 system_region, const int rad,$ const int rad_flags, VOID_PPQ sva);Cunsigned __int64 mmg$find_stack_peak (VOID_PQ base, VOID_PQ limit, % int regstack, int acmode, int type);;int mmg$lkwset_int (VOID_PQ start_va_64, uint64 length_64);+int mmg$lock_linker_data (VOID_PQ code_va);>#ifdef __x86_64 /* Verified for x86 port - Greg Jordan *//int mmg$bufobj_page_tables( VOID_PQ buf_addr );#endifOPFN_PQ mmg$$valid_l3pt (VOID_PQ bpte_addr, PCB_PQ pcb, PHD_PQ phd, WSL_PQ wsl);Lint mmg_std$frewsle (PCB_PQ pcb, PHD_PQ phd, WSL_PQ wsl, UINT64_PQ reswait);ivoid mmg_std$make_wsle_64 (VOID_PQ va, PTE_PQ va_pte, PCB_PQ PCB, PHD_PQ phd, WSL_PQ wsl, PFN_PQ pfndbe);<unsigned __int64 mmg$invo_context_init (int total_length);OVOID_PQ mmg$invo_context_malloc (int length, unsigned __int64 ident);Fvoid mmg$invo_context_free (VOID_PQ ptr, unsigned __int64 ident);Bvoid mmg$invo_context_ done (unsigned __int64 ident);<#ifdef __ia64 /* Verified for x86 port - Clair Grant */Jvoid mmg$purge_tr (VOID_PQ va, unsigned __int64 length, int which_trs);nvoid mmg$setup_tr (VOID_PQ va, unsigned __int64 pa, unsigned __int64 length, int prot, int tr, int which_trs);$int mmg$check_vhpt (VOID_PQ va);void mmg$create_vhpt (void);void mmg$enable_vhpt (void);7void mmg$insert_vhpt (VOID_PQ va, PTE pte_contents);#void mmg$invalidate_vhpt (void);%void mmg$invalidate_vhpt_p (void);/void mmg$invalidate_vhpt_entry (VOID_PQ va);#endif'uint64 mmg$va2pa_64 (VOID_PQ const va);(uint64 mmg$page_size (VOID_PQ const va);>#ifdef __x86_64 /* Verified for x86 port - Greg Jordan */)#define mmg$page_present MMG$PAGE_PRESENT(int mmg$page_present (VOID_PQ const va);+#define mmg$write_pte_x86 MMG$WRITE_PTE_X861void mmg$write_pte_x86( PTE_PQ va_pte, PTE pte );P#define mmg$bpte_va MMG$BPTE_VA /* wrapper around bpte_va macro */0PTE_PQ mmg$bpte_va (uint64 addr, uint32 mode); #endifq#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif"#endif /* __MMG_ROUTINES_LOADED */ww`ZU/* * MODULE: MPDEV_ROUTINES.H** VERSION: X-21*>* Copyright 2002 Compaq Information Technologies Group, L.P.*C* Compaq and the Compaq logo are trademarks of Compaq Information@* Technologies Group, L.P. in the U.S. and/or other countries.*J* Confidential computer software. Valid license from Compaq required forF* possession, use or copying. Consistent with FAR 12.211 and 12.212,F* Commercial Computer Software, Computer Software Documentation, andK* Technical Data for Commercial Items are licensed to the U.S. Government/* under vendor's standard commercial license.* *++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS systemI* routines that begin with the MPDEV$ that use a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS*  compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.*/* 6. Mixed pointer sizes within one argumentF* If a 64-bit pointer is being passed by reference, the reference to ?* the pointer should also be 64 bits wide to avoid confusion. * For example:* * PTE_PPQ va_pte_p;* VOID_PPQ start_va_p; ** should be used instead of:**  PTE_PQ *va_pte_p;* VOID_PQ *start_va_p;* * * AUTHOR:* * David E. Eiche* * CREATION DATE: 11-May-1998* * MODIFICATION HISTORY:*%* X-21 ABP Anu B. Pant 26-Sep-20027* Change mpdev$driver_start prototype to return int. *4* X-20 LSS0435 Leonard S. Szubowicz 16-May-2002B* Part of the fix for PTRs 75-66-975, 75-66-1089, and 75-66-1090.A* Starting and ending path verification to "find an active path"@* is now handled by new routines MPDEV$ PV_START_FIND_ACTIVE and* MPDEV$PV_END_FIND_ACTIVE.?* Also, take this opportunity to add MPDEV$LEAST_USED_LCL_PATH?* which will be used to provide a bias for balancing path use.*,* X-19 RAB016 Robert A. Brooks 10-Jan-2002* Add MPDEV$CANCEL_POLLER_IRP*'* X-18 Anne McElearney 15-Oct-2001:* Change references to routine MPDEV$IS_CURRENT_ONLINE to<* MPDEV$IS_DEVICE_ONLINE. The routine name changed because4* the behavior of the routine changed due to fixing* PTR 75-45-482.*4* X-17 LSS0426 Leonard S. Szubowicz 15-Oct-2001?* Part of the fix for PTR 75-66-346: Add routine prototype for* MPDEV$INIT_CDRP_IN_IRP.*4* X-16 LSS0414 Leonard S. Szubowicz 22-Feb-2001* Fold X-12A3.3* Incorporate comments from code review of X-12A2.A* MPDEV$DISPOSE_IFNOT_FWDABLE replaces MPDEV$IS_IRP_FORWARDABLE.*1* X-15 LSS0413 Leonard S. Szubowicz 23-Jan-2001* Fold X-12A2.;* Part of the fix for CLD 70-3-4160: Provide a method thatA* allows both  Multipath and HSM to intercept the DDT$PS_CANCEL_2C* driver entry point in a compatible fashion. This is facilitatedA* by keeping all Multipath DDT intercepts in place once they areC* established regardless of the current path. Also add prototypes=* for routines mpdev$opcom_msg and mpdev$is_irp_forwardable.* K* X-14 GP Genady Perchenko 21-Aug-2000P* Add definition for mpdev$get_alt_host_ucb and mpdev$get_mscp_ucb*)* X-13  ABP Anu Pant 13-Mar-2000<* Add new routine mpdev$ms_notify and mpdev$ms_notify_kast.*B* Add new parameter (pointer to MPDEV_ACB)to mpdev$manual_switch :* to deliver completion AST for multipath system service.* F* Change parameter of mpdev$manual_switch and mpdev$locate_target_ucb<* to support 64-bits pointer for multipath system services.*1* X-12 LSS0396 Leonard S. Szubowicz 28-Apr-1999=* Part of the fix for PTRs 75-3-4260 and 75-43-393. Add the?* prototype for the  mpdev$mntv_sssc routine used to invoke theA* "mount verification shadow set state change" action routine on* a shadow set.9* Part of the fix for PTR 75-43-571. Add prototypes forA* mpdev$set_valid and mpdev$clear_valid that reflect UCB$V_VALID:* bit changes to the primary path UCB on a multipath set.*** X-11 JMB055 James M. Blue 30-Sep-1998<* Modify mpdev$locate_target_ucb and mpdev$manual_switch to:* add an ASCIZ string parameter to receive the final full* path description string.*** X-10 JMB048 James M. Blue 31-Jul-1998<* Add status return for MPDEV$SET_BITS routine. Needed for'* attempt to disable the current path.*K* X-9 GP Genady Perchenko 21-Jul-19984* Add mpdev$map_status_shdset routine.*)* X-8 JMB032 James M. Blue 17-Jul-1998@* Modify prototypes for MPDEV$ADD_POLLER_PATH to return an int.*K* X-7 GP Genady Perchenko 15-Jul-1998M*  Add support for mpdev$pv_start_manual. Moved mpdev$map_statusG* up to keep all routines in alphabetical order. Renamed C* mpdev$find_online_path to mpdev$is_current_online. *1* X-6 DEE0415 David E. Eiche 08-Jul-19984* Add support for routines mpdev$locate_target_ucb,+* mpdev$manual_switch, and mpdev$set_bits.*K* X-5 GP Genady Perchenko 05-Jun-19989* Make default size of the pointers 32 -bit.*'* X-4 GP Genady Perchenko 02-Jun-1998=* Add support for the new routines mpdev$driver_pending_io. @* Renamed mpdev$is_pv_allowed to mpdev$map_status.*+* X-3 DEE0406 David E. Eiche 28-May-19989* Add support for the new routine mpdev$setup_intercept.*+* X-2 DEE0402 David E. Eiche 16-May-19986* Add prototype and define for mpdev$add_poller_path..* Also, reflect changes to calling sequences:?* 1. Change mpdev$pv_do_io_to_path to mpdev$do_io_to_path;F* 2. Add UCB pointer to calling sequence for mpdev$do_io_to_path;6* 3. Remove UCB pointer from calling sequence for!* mpdev$pv_convert_mvirp.:* Fix call to driver cancel to include reason for cancel.* ,* X-1 DEE0401 David E. Eiche 13-May-1998* Initial check-in.* *--*/#ifndef __MPDEV_ROUTINES_LOADED!#define __MPDEV_ROUTINES_LOADED 1/*H * Define all types that are used in the following function prototypes. */#include #include #include #include #include #include #include #include /*Q * VMS system routine entry points are defined externally using uppercase names.K * The following macros allow the usage of the lowercase versions of theseB * names even in the presence of the /NAME=AS_IS compiler switch. */0#define mpdev$add_mpdev_ddt MPDEV$ADD_MPDEV_DDT4#define mpdev$add_path_to_set MPDEV$ADD_PATH_TO_SET4#defin e mpdev$add_poller_path MPDEV$ADD_POLLER_PATH8#define mpdev$cancel_poller_irp MPDEV$CANCEL_POLLER_IRP,#define mpdev$clear_valid MPDEV$CLEAR_VALID?#define mpdev$dispose_ifnot_fwdable MPDEV$DISPOSE_IFNOT_FWDABLE0#define mpdev$do_io_to_path MPDEV$DO_IO_TO_PATH4#define mpdev$driver_altstart MPDEV$DRIVER_ALTSTART0#define mpdev$driver_cancel MPDEV$DRIVER_CANCEL4#define mpdev$driver_fast_fdt MPDEV$DRIVER_FAST_FDT8#define mpdev$driver_pending_io MPDEV$DRIVER_PENDING_IO.#define mpdev$driver_s tart MPDEV$DRIVER_START;#define mpdev$driver_startio_pvip MPDEV$DRIVER_STARTIO_PVIP>#define mpdev$get_alt_host_ucb MPDEV$GET_ALT_HOST_UCB:#define mpdev$get_mscp_ucb MPDEV$GET_MSCP_UCB6#define mpdev$init_cdrp_in_irp MPDEV$INIT_CDRP_IN_IRP6#define mpdev$is_device_online MPDEV$IS_DEVICE_ONLINE9#define mpdev$is_path_selectable MPDEV$IS_PATH_SELECTABLE<#define mpdev$least_used_lcl_path MPDEV$LEAST_USED_LCL_PATH 8#define mpdev$locate_target_ucb MPDEV$LOCATE_TARGET_UCB0#d efine mpdev$manual_switch MPDEV$MANUAL_SWITCH*#define mpdev$map_status MPDEV$MAP_STATUS8#define mpdev$map_status_shdset MPDEV$MAP_STATUS_SHDSET)#define mpdev$mntv_sssc MPDEV$MNTV_SSSC)#define mpdev$ms_notify MPDEV$MS_NOTIFY<#define mpdev$ms_notify_kast MPDEV$MS_NOTIFY_KAST)#define mpdev$opcom_msg MPDEV$OPCOM_MSG6#define mpdev$pv_convert_mvirp MPDEV$PV_CONVERT_MVIRP##define mpdev$pv_end MPDEV$PV_END@#define mpdev$pv_end_find_active MPDEV$PV_END_FIND_ACTIVE0#d efine mpdev$pv_end_shdset MPDEV$PV_END_SHDSET=#define mpdev$pv_intercept_packack MPDEV$PV_INTERCEPT_PACKACK*#define mpdev$pv_io_done MPDEV$PV_IO_DONE6#define mpdev$pv_restore_mvirp MPDEV$PV_RESTORE_MVIRP.#define mpdev$pv_set_state MPDEV$PV_SET_STATE'#define mpdev$pv_start MPDEV$PV_STARTB#define mpdev$pv_start_find_active MPDEV$PV_START_FIND_ACTIVE=#define mpdev$pv_start_manual MPDEV$PV_START_MANUAL4#define mpdev$pv_start_shdset MPDEV$PV_START_SHDSET'#define mpdev$set_ bits MPDEV$SET_BITS)#define mpdev$set_valid MPDEV$SET_VALID'#define mpdev$special1 MPDEV$SPECIAL1,#define mpdev$switch_path MPDEV$SWITCH_PATH/*D * Function prototypes for system routines with the MPDEV$ prefix. */[#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */]#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32- bit pointers */#endifPint mpdev$add_mpdev_ddt( MPDEV *mpdev, UCB *primary_ucb, UCB *candidate_ucb );Dint mpdev$add_path_to_set( UCB *primary_ucb, UCB *candidate_ucb );2int mpdev$add_poller_path( UCB *candidate_ucb );*void mpdev$cancel_poller_irp( UCB *ucb );$void mpdev$clear_valid( UCB *ucb );Jint mpdev$dispose_ifnot_fwdable( IRP *irp, UCB *src_ucb, UCB *dst_ucb );0void mpdev$do_io_to_path( IRP *irp, UCB *ucb );2void mpdev$driver_altstart( IRP *irp, UCB *ucb );Pint mpdev$dr iver_cancel( int chan, IRP *irp, PCB *pcb, UCB *ucb, int reason );Fint mpdev$driver_fast_fdt( IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb );9int mpdev$driver_pending_io( void *que_hdr, IRP *irp );/int mpdev$driver_start( IRP *irp, UCB *ucb );6int mpdev$driver_startio_pvip( IRP *irp, UCB *ucb );(UCB *mpdev$get_alt_host_ucb(UCB *ucb); #UCB *mpdev$get_mscp_ucb(UCB *ucb);3void mpdev$init_cdrp_in_irp( IRP *irp, UCB *ucb );1int mpdev$is_device_online( UCB *primary_ucb );+int mpdev$is_path_selectable( UCB *ucb );0UCB *mpdev$least_used_lcl_path( MPDEV *mpdev );pint mpdev$locate_target_ucb( UCB *primary_ucb, VOID_PQ target_id, CHAR_PQ target_string, UCB **target_ucb_p );fint mpdev$manual_switch( UCB *primary_ucb, VOID_PQ target_id, CHAR_PQ target_string, MPDEV_ACB * );(int mpdev$map_status( int io_status );@int mpdev$map_status_shdset( int io_status, UCB *shadow_ucb );Evoid mpdev$mntv_sssc( int io_status, IRP *vp_irp, UCB *shadow_ucb );1void mpdev$ms_notify(MPDE V_ACB *, MPDEV *, int);+void mpdev$ms_notify_kast(PCB *, ACB64 *);Bvoid mpdev$opcom_msg( int opc_code, MPDEV *mpdev, UCB *old_ucb );3void mpdev$pv_convert_mvirp( IRP *irp, int func );'void mpdev$pv_end( UCB *primary_ucb );Evoid mpdev$pv_end_find_active( IRP *packack_irp, UCB *primary_ucb );-void mpdev$pv_end_shdset( UCB *shadow_ucb );7void mpdev$pv_intercept_packack( IRP *irp, UCB *ucb );#void mpdev$pv_io_done( IRP *irp );)void mpdev$pv_restore_mvirp( IRP *irp );5void mpdev$pv_set_state( UCB *ucb, int path_state );)void mpdev$pv_start( UCB *primary_ucb );Gvoid mpdev$pv_start_find_active( IRP *packack_irp, UCB *primary_ucb );@void mpdev$pv_start_manual( UCB *primary_ucb, UCB *target_ucb);/void mpdev$pv_start_shdset( UCB *shadow_ucb );iint mpdev$set_bits( UCB *ucb, unsigned int *bit_field, unsigned int bit_mask, unsigned int bit_value );"void mpdev$set_valid( UCB *ucb );lint mpdev$special1( UCB *ucb, int (*cancel_routine)(int chan, IRP *irp, PCB *pcb, UCB *ucb, int reason) );$void mpdev$switch_path( UCB *ucb );l#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ d#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif$#endif /* __MPDEV_ROUTINES_LOADED */wwZU/**I* Copyright Digital Equipment Corporation, 1993 All Rights Reserved.O* Unpublished rights reserved under the copyright laws of the Unite d States.* L* The software contained on this media is proprietary to and embodies theP* confidential technology of Digital Equipment Corporation. Possession, use,N* duplication or dissemination of the software and media is authorized onlyL* pursuant to a valid written license from Digital Equipment Corporation.* K* RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.G* Government is subject to restrictions as set forth in SubparagraphJ* (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable.* *++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS system@* routines that begin with the MT$ and MT_STD$ prefixes and have* a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercas e or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* intege r that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.* * * AUTHOR:* * Leonard S. Szubowicz* * CREATION DATE: 9-Jun-1993* * MODIFICATION HISTORY:* -* X-2 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*0* X-1 LSS0279 Leonard S. Szubowicz 9-Jun-1993@* Initial version containing only those routines commonly used* by device drivers.* *--*/ #ifndef __MT_ROUTINES_LOADED#define __MT_ROUTINES_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define all types that are used in the following function prototypes.*/#include #include #include #include /*P VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/0#define mt_std$check_access MT_STD$CHECK_ACCESS/*L Function prototypes for system routines with the MT$ and MT_STD$ prefix.*/Cint mt_std$check_access (IRP *irp, PCB *pcb, UCB *ucb, CCB *ccb);R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif!#endif /* __MT_ROUTINES_LOADED */ww@ZUO/* ************************************************************************* */O/* * * */O/* * HPE CONFIDENTIAL. This software is confidential proprietary software * */O/* * licensed by Hewlett Packard Enterprise Development, LP, and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without the * */O/* * prior written permission of HPE. * */O/* * Copyright 2017 Hewlett Packard Enterprise Development, LP * */O/* * * */O/* * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential * */O/* * proprietary software licensed by VMS Software, Inc., and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without * */O/* * the prior written permission of VMS Software, Inc. * */O/* * Copyright 2 017-2020 VMS Software, Inc. * */O/* * * */O/* ************************************************************************* */N//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~//N// DESCRIPTION: The ACPI OSL (Operating System Layer) provides the interface L// between OpenVMS EXEC components and the ACPI-CA (Component Architecture) L// subsystem. ACPI exists as an  execlet (SYS$ACPI) loaded during bootstrap.L// When the boot process determines the machine is ACPI-capable (as all IPF M// systems must be), an ACPI-aware SYS$CPU_ROUTINES execlet is loaded. This F// module will initialize and enable ACPI. From that point forth, allK// access to ACPI data structures, devices, and methods must go through theM// acpi$osl routines described herein. If you don't see a routine to do what6// you are trying to do with ACPI, contact the author.//// REVISION HISTORY://%// X-21 GMN G.M.Newsted 09-Apr-20204// Redefine acpi$osl_bib_reset to use arg to select7// Reset or Power-Off functions on x86. The prior use7// of this arg was "cpuid" which was ignored. Behavior// on IA64 is unchanged.//*// X-20 RAB Richard A. Bishop 27-Jan-20203// Use ARCH_DEFS for platform conditionals so that"// cross-platform SDA will build.//C// X-19 MLW Michael Winiarski 22-Oct-2019G// Add function prototypes fo r acpi$osl_intrpt_override().//C// X-18 MLW Michael Winiarski 29-Aug-2019H// Add function prototypes for acpi$osl_ioapic_config() and?// acpi$osl_ioapic_find_rte() for non IA64 builds.//$// X-17 AHM Drew Mason 29-May-2019I// Conditionalized acpi$osl_iosapic_config and acpi$osl_iosapic_find_rteA// to IA64. Add the corresponding I/O APIC definitions for x86.//1// X-16 08-Nov-2018 Michael Winiarski?// Wi th the change in X-15, the acpi.h header fileC// was included. Since ACPI is compiled with uses longE// pointers, bracket the acpi.h header with pointer_sizeH// pragmas -- this ensures ACPI structure sizes are correct// throughout.//1// X-15 19-Oct-2018 Michael Winiarski=// Added definition of VMS-styled jacket routine#// acpi$osl_get_table.//1// X-14 19-Jul-2017 Michael Winiarski ;// * Support for ACPICA.ORG 20170531 code drop//8// X-13 PAJ1533 Paul A. Jacobi 10-Jun-2008<// 1) Fix VGA structure definitions to match specification.-// 2) Define bitfields for PCDP flags field.=// 3) Seperate the flags field from the HCDP function field.'// 4) Reset module Ident to match VDE.///// X13 23-Apr-2008 LSS0541 Leonard S. Szubowicz;// Add definition of VMS-styled constants for various ACPI<// types. These are of use to callers of variou s ACPI$OSL_xB// routines. Add function prototype for ACPI$OSL_GET_OBJECT_TYPE.//(// X12 18-Apr-2008 RAB Richard A. Bishop>// Put the new definitions added in X11 under the conditional>// _ACPI_OSL_EXTENSION_STRUCTURES so that only [ACPI]OSLVMS.C;// and [SDA]SHOWACPI.C pick them up. Without this, several;// modules that use OSLVMS.H now have a dependency on many// other ACPI headers.//(// X11 11-Apr-2008 RAB Richard A. Bishop<// Moved definitions here from OSLVMS.C so SDA can use them///// X10 20-Mar-2008 LSS0539 Leonard S. Szubowicz;// Add function prototypes for ACPI$OSL_WALK_NAMESPACE and:// ACPI$OSL_GET_DEVICES, initially for SYS$GET_WBEM_INFO.//// X9 8-Jan-2008 WDA W.D.ArboL// Add ACPI$OSL_GET_STATISTICS, ACPI$OSL_INSTALL_TABLE_HANDLER #// and ACPI$REMOVE_TABLE_HANDLER. //<// [acpi]oslvms (not this file) will be obsoleted with this // checkin.//5// Port this update from the obsoleted [acpi]oslvms.//$// X7 06-Jul-2005 ER Eric Rasmussen// Add ACPI$OSL_FIXED_CONFIG.////!// X8 8-May-2006 JRK Jim Kauffman// Add acpi$osl_bib_reset//&// X7 5-May-2005 KLN3568 Karen L. NoelA// Fix acpi$osl_execute_method and acpi$osl_exec_numeric_method.//'// X6 25-Apr-2005 KLN3567 Karen L. Noel3// Move funtion prototypes from gpscfgdef to here.//!// X5 06-May-2003 TLC Tony Camuso3// Changed GPSPORTDEV Addr field to unsigned quad.1// Renamed GPSHEADER uqIdString field to uqHwId.//(// X4 22-Apr-2003 GMN Gary M. Newsted ,// Merged gps_configdef.h into this header.//(// X3 18-Apr-2003 GMN Gary M. Newsted 4// Eliminated ACPI-specific datatypes and includes.//(// X2 04-Mar-2003 GMN Gary M. Newsted -// Added HCDP structure defs & HCDP routines//(// X1 15-Jan-2003 GMN Gary M. Newsted // Initial module creationN//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~#ifndef __ACPI_OSLVMS_H__#define __ACPI_OSLVMS_H__ #include +#include // uint64, uint32, etc.#include #pragma __pointer_size __save#pragma __pointer_size __long#include #pragma __pointer_size __restoreN//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~// VMS-styled ACPI constantsN//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~//C// These ACPI constants are useful in conjunction with some of the I// ACPI$OSL_x routines, whose prototypes are defined in this h eader file.// K// Note: Compilation of module [ACPI]OSLVMS.C will validate the equality ofH// these symbols to their corresponding native ACPI constants, which are// defined by [ACPI]ACTYPES.H..#define ACPI$K_TYPE_ANY 0x00P#define ACPI$K_TYPE_INTEGER 0x01 // Byte/Word/Dword/Zero/One/Ones.#define ACPI$K_TYPE_STRING 0x02.#define ACPI$K_TYPE_BUFFER 0x03b#define ACPI$K_TYPE_PACKAGE 0x04 // ByteConst, multiple Dat aTerm/Constant/SuperName.#define ACPI$K_TYPE_FIELD_UNIT 0x05F#define ACPI$K_TYPE_DEVICE 0x06 // Name, multiple Node.#define ACPI$K_TYPE_EVENT 0x07Q#define ACPI$K_TYPE_METHOD 0x08 // Name, ByteConst, multiple Code.#define ACPI$K_TYPE_MUTEX 0x09.#define ACPI$K_TYPE_REGION 0x0AV#define ACPI$K_TYPE_POWER 0x0B // Name,ByteConst,WordConst,multi Node`#define ACPI$K_TYPE_PROCESSOR 0x 0C // Name,ByteConst,DWordConst,ByteConst,multi NmOF#define ACPI$K_TYPE_THERMAL 0x0D // Name, multiple Node.#define ACPI$K_TYPE_BUFFER_FIELD 0x0E]#define ACPI$K_ROOT_OBJECT (uint64)( ~((uint64) 0) ) // Root object handle in ACPI namespaceT#define ACPI$K_UINT32_MAX (uint32)( ~((uint32) 0) ) // Max 32-bit unsigned integerL#define ACPI$K_AE_OK 0x0000 // ACPI_STATUS AE_OK, success[#define ACPI$K_AE_CODE_CONTROL 0x4000 // ACPI_STATUS AE_COD E_CONTROL, control codec#define ACPI$K_AE_CTRL_TERMINATE (0x0003 | ACPI$K_AE_CODE_CONTROL) // ACPI_STATUS, terminate N//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~:// OSL FUNCTION PROTOTYPES - Support for VMS EXEC routinesN//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously- defined required ptr size */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */#endif3#define acpi$osl_init_execlet ACPI$OSL_INIT_EXECLET%int acpi$osl_init_execlet (void);@#if IA64 // Verified for x86 port--Drew Mason & Richard Bishop8#define acpi$osl_iosapic_config ACPI$OSL_IOSAPIC_CONFIG Xint acpi$osl_iosapic_config (void (*pfCB_User)(void), GPSIOSAPICINFO *pIoSapicInfo);;#define acpi$osl_iosapic_find_rte ACPI$OSL_IOSAPIC_FIND_RTE lint acpi$osl_iosapic_find_rte (unsigned int ulGsin, int *iRteOffset, unsigned __int64 *pIoSapicAddress);L#else // Verified for x86 port - Michael Winiarski6#define acpi$osl_ioapic_config ACPI$OSL_IOAPIC_CONFIG Uint acpi$osl_ioapic_config (void (*pfCB_User)(void), GPSIOAPICINFO *pIoApicInfo);9#define acpi$osl_ioapic_find_rte ACPI$OSL_IOAPIC_FIND_RTEjint acpi$osl_ioapic_find_rte (unsigned int ulGsin, int *iRteOffset, unsigned __int64 *pIoApicAddress);#endif// X-199#define acpi$osl_intrpt_override ACPI$OSL_INTRPT_OVERRIDETint acpi$osl_intrpt_override (UINT32 Gsin, UINT32 *newGsin, UINT16 *newPolTrig); // end X-195#define acpi$osl_device_config ACPI$OSL_DEVICE_CONFIGMint acpi$osl_device_config (void (*pfCB_User)(void), GPSCONFIG *pConfig);3#define acpi$osl_hcdp_entries ACPI$OSL_HCDP_ENTRIES$int acpi$osl_hcdp_entries(void);7#define acpi$osl_console_config ACPI$OSL_CONSOLE_CONFIGOint acpi$osl_console_confi g (void (*pfCB_User)(void),GPSHCDPDEV *pHcdpDev);1#define acpi$osl_spmi_config ACPI$OSL_SPMI_CONFIGIint acpi$osl_spmi_config (void (*pfCB_User)(void),GPSSPMI *pRetSpmi);/#define acpi$osl_gpe_config ACPI$OSL_GPE_CONFIGIint acpi$osl_gpe_config (void (*pfCB_User)(void),GPSGPEDEV *pRetGpe);/#define acpi$osl_cpu_config ACPI$OSL_CPU_CONFIGdint acpi$osl_cpu_config ( unsigned __int64 hStart, void ( *pfCB_User )( ), GPSCONFIG *pConfig );:#define acpi$osl_get_system_info ACPI$OSL_GET_SYSTEM_INFO 8int acpi$osl_get_system_info (GPSSYSINFO *pSysInfo);-#define acpi$osl_bib_reset ACPI$OSL_BIB_RESET#if IA64#int acpi$osl_bib_reset (int cpuid);#else'int acpi$osl_bib_reset (int power_off);#endif&#pragma __required_pointer_size __save'#pragma __required_pointer_size __short3#define acpi$osl_get_crs_item ACPI$OSL_GET_CRS_ITEMyint acpi$osl_get_crs_item ( unsigned __int64 uqHwHandle, int iResTag, int iTypeTag, int iAttrTag, void **ppvRetData);)#defin e acpi$osl_get_prt ACPI$OSL_GET_PRTRint acpi$osl_get_prt ( unsigned __int64 uqHwHandle, GPSPRTENTRY **ppvRetData);)#pragma __required_pointer_size __restore$#define acpi$osl_free ACPI$OSL_FREE 'int acpi$osl_free (void *pvBuffer);A#define acpi$osl_exec_numeric_method ACPI$OSL_EXEC_NUMERIC_METHODtint acpi$osl_exec_numeric_method ( unsigned __int64 uqHwHandle, char *pMethodName, unsigned __int64 *pqRetData);>#define acpi$osl_execute_debug_cmd ACPI$OSL_EXECUTE_DEBUG_CMD 0in t acpi$osl_execute_debug_cmd (char * cmd);7#define acpi$osl_execute_method ACPI$OSL_EXECUTE_METHODpint acpi$osl_execute_method (unsigned __int64 uqHwHandle, char *pMethodName, GPSDESCRIPTOR *psInParamArray, J unsigned int uiInParamCnt, unsigned int *pulRetType, void **ppvRetData);G#define acpi$osl_install_notify_handler ACPI$OSL_INSTALL_NOTIFY_HANDLER8int acpi$osl_install_notify_handler (void * Handle,  unsigned int Type, F void (*Handler)(void * Device, unsigned int Va lue, void * Context),  void *Context);E#define acpi$osl_remove_notify_handler ACPI$OSL_REMOVE_NOTIFY_HANDLER7int acpi$osl_remove_notify_handler (void * Handle,  unsigned int Type, F void (*Handler)(void * Device, unsigned int Value, void * Context));B#define acpi$osl_install_gpe_handler ACPI$OSL_INSTALL_GPE_HANDLER 5int acpi$osl_install_gpe_handler (void * Handle,  unsigned int GpeNum,  unsigned int Type, c unsigned int (*Handler)(void * GpeDevice, unsigned int GpeNumber, void * Context),  void *Context);?#define acpi$osl_remove_gpe_handler ACPI$OSL_REMOVE_GPE_HANDLER4int acpi$osl_remove_gpe_handler (void * Handle,  unsigned int GpeNum, c unsigned int (*Handler)(void * GpeDevice, unsigned int GpeNumber, void * context));E#define acpi$osl_install_fixed_handler ACPI$OSL_INSTALL_FIXED_HANDLER<int acpi$osl_install_fixed_handler (unsigned int Event, + unsigned int (*Handler)(void * Context),  void *Co ntext);C#define acpi$osl_remove_fixed_handler ACPI$OSL_REMOVE_FIXED_HANDLER;int acpi$osl_remove_fixed_handler (unsigned int Event, + unsigned int (*Handler)(void * Context));3#define acpi$osl_get_pathname ACPI$OSL_GET_PATHNAMEDint acpi$osl_get_pathname (void * Object, unsigned char **Name);A// Executes a callback for each fixed-feature device in the FADT.//3#define acpi$osl_fixed_config ACPI$OSL_FIXED_CONFIGLint acpi$osl_fixed_config (void (*pfCB_User)(void), GPSCONFIG *pConfig);;// Fetches the SciCount,GpeCount,FixedEventCounts from ACPI//7#define acpi$osl_get_statistics ACPI$OSL_GET_STATISTICS@int acpi$osl_get_statistics (GPSSTATISTICS *statistics_buffer);C// Install a handler to be called when an event occurs for a table.//E#define acpi$osl_install_table_handler ACPI$OSL_INSTALL_TABLE_HANDLERMint acpi$osl_install_table_handler (GPSTABLEHANDLER handler, void * context);B// Remove a handler to be called when an event occurs for a table.//C#define acpi$osl_remove_table_handler ACPI$OSL_REMOVE_TABLE_HANDLER<int acpi$osl_remove_table_handler (GPSTABLEHANDLER handler);G// Walk a portion of the ACPI namespace looking for ACPI objects of theE// specified type. The specified callback routine is invoked for eachE// matching object. The portion can be specified such that the entire// ACPI namespace is traversed.7#define acpi$osl_walk_namespace ACPI$OSL_WALK_NAMESPACEint acpi$osl_walk_namespace ( uint32 obj_type, uint64 start_obj_handle, uint32 max_depth,g int (*call_back_rout)( uint64 obj_handle, uint32 nesting_level, void *context, void **return_value ), void *context, void **return_value );F// Walk the entire ACPI namespace looking for ACPI device objects thatG// match the specified Hardware ID (HID) string. The specified callback6// routine is invoked for each matching device object.1#define acpi$osl_get_devices ACPI$OSL_GET_DEVICESint acpi$osl_get_devices ( char *hid,g int (*call_back_rout)( uint64 obj_handle, uint32 nesting_level, void *context, void **return_value ), void *context, void **return_value );O// Get the ACPI object type (ACPI$K_TYPE_x) of an object in the ACPI namespace.9#define acpi$osl_get_object_type ACPI$OSL_GET_OBJECT_TYPEint acpi$osl_get_object_type ( uint64 obj_handle, uint32 *obj_type_p );-#define acpi$osl_get_table ACPI$OSL_GET_TABLE,int acpi$osl_get_table (char *Signature,, uint32 Ins tance,: ACPI_TABLE_HEADER **OutTable);r#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ a#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif:#endif %#ifdef _ACPI_OSL_EXTENSION_STRUCTURESN//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~L// ACPI-OSL EXTENSION STRUCTURES (some of these may emerge in Intel headers)N//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~//>// Should only be needed by [ACPI]OSLVMS.C and [SDA]SHOWACPI.C//!#pragma __member_alignment __save#pragma __nomember_alignmentA// HCDP - Headless Console & Debug Port Table def from DIG64 spectypedef struct {9 ACPI_TABLE_HEADER TableHeader; // actbl.h - 24 bytes UINT32 NumEntries;, UINT32 Entry; // First entry} OSL_HCDP_HEADER; typedef struct {5 UINT8 Type; // 0 = UART Desc, 1 = DEBUGPORT Desc UINT8 NumDataBits; UINT8 Parity; UINT8 StopBits;5 UINT8 PciSegNum; // If UART is a PCI device5 UINT8 PciBusNum; // If UART is a PCI device8 UINT8 PciDeviceNum; // If UART is a PCI device struct {# unsigned PciFunctionNum : 3; unsigned Rsvd : 3;$ unsigned InterruptFlag : 1;$ unsigned PciDeviceFlag : 1; } PciFunctionFields; UINT64 Baud; UINT8 AddressSpaceID; // 38 UINT8 RegisterBitWidth; UINT8 RegisterBitOffset; UINT8 Fill1; UINT64 BaseAddress; // 3C UINT16 DeviceID; UINT16 VendorID;! UINT32 GlobalSystemInterrupt; UINT32 PseudoClockRate; UINT8 PciClass; UINT8 Fill2[7];} OSL_HCDP_ENTRY;O//=============================================================================// INTERCONNECT STRUCTURES//M// For New Type (PCDP) Device Descriptor Entries, an area is reserved for theH// Interconnect Data for access to the device through MMIO, Port, or PCI// Config space.//D// See "DIG64 Descriptions for Primary Console & Debug Port Devices"// Table 2-4, Offset 6//O//=============================================================================!#define INTERCONNECT_TYPE_ACPI 0!#define INTERCONNECT_TYPE_PCI 1// -------------------// INTERCONNECT_HEADER// -------------------E// Hea der for the Interconnect types is implemented as a macro ratherD// than as a separate data structure. The macro provides fields withA// the same names when declared within other structures, allowingA// access to the header fields common to all types. An additionalB// benefit is that the macro provides more maintainablility, sinceC// changes made to the macro can propagate to other structures that // use it.//D// See "DIG64 Descriptions for Primary Console & Debug Port Devices"*// Tables 2-6 and 2-7, offsets 0, 1, and 22// This header has a 4 byte (32 bit) displacement.//!#define INTERCONNECT_HEADER \! UINT8 InterconnectType; \! UINT8 ICT_Reserved_0; \ UINT16 Length;// ---------------------------// INTERCONNECT_HEADER_OVERLAY// ---------------------------F// The following structure is used in the INTERCONNECT union to access/// the header fields for any INTERCONNECT type.//typedef struct{ INTERCONNECT_HEADER}INTERCONNECT_HEADER_OVERLAY;// ------------------// INTERCONNECT_FLAGS// ------------------@// "DIG64 Descriptions for Primary Console & Debug Port Devices"// Table 2-6, offset 32//typedef struct{: unsigned IrqMode : 1; // 0 = Edge, 1 = Level7 unsigned IrqPolarity : 1; // 0 = Hi, 1 = Lo* unsigned Reserved_0 : 1; // MBZO unsigned SparseXlat : 1; // 1 = Sparse Translation (Port IO swizzle)? unsigned MmioXlat : 1; // Memory-to-IO Translation* unsigned Reserved_1 : 1; // MBZ8 unsigned IrqValid : 1; // 1 = IRQ supported* unsigned Reserved_2 : 1; // MBZ}INTERCONNECT_FLAGS;// ------------------------// INTERCONNECT_XLAT_FIELDS// ------------------------@// "DIG64 Descriptions for Primary Console & Debug Port Devices"// Table 2-6, offset 33//typedef struct{ unsigned MmIoTraValid : 1; unsigned PortIoTraValid : 1; unsigned Reserved : 6;}INTERCONNECT_XLAT;// --------------------// INTERCONNECT_TRAILER// --------------------J// These are fields that are common to the APCI and PCI Interconnect typesD// See "DIG64 Descriptions for Primary Console & Debug Port Devices"// Tables 2-7 and 2-7.//!#define INTERCONNECT_TRAILER \! UINT32 Gsin; \! UINT64 MmIoTra; \! UINT64 PortIoTra; \! INTERCONNECT_FLAGS Flags; \ INTERCONNECT_XLAT Xlat;// -----------------// ACPI_INTERCONNECT// -----------------@// "DIG64 Descriptions for Primary Console & Debug Port Devices" // Table 2-6//typedef struct{# INTERCONNECT_HEADER // 4 Bytes UINT32 AcpiUid; UINT32 AcpiHid; INTERCONNECT_TRAILER}ACPI_INTERCONNECT;// ----------------// PCI_INTERCONNECT// ----------------(// X-58 TLC 20060714 VGA Console SupportO// We must add the PCI Interconnect Specific structure for the PCDP in order toO// properly characterize a possible VGA entry in the PCDP. Note that the fieldsL// are aligned on natural boundaries, as defined in the DIG64 specification.//typedef struct{" INTERCONNECT_HEADER // 4 Bytes UINT8 Segment; UINT8 Bus;2 UINT8 Device; // Only bits 4:0 are valid2 UINT8 Function; // Only bits 2:0 are valid UINT16 DeviceID; UINT16 VendorID; INTERCONNECT_TRAILER}PCI_INTERCONNECT;// ------------// INTERCONNECT// ------------H// This union is basically "An y Interconnect" and provides access to theK// header fields before knowing which type of interconnect was encountered.H// We need to access the header fields first in order to determine which(// type of interconnect was encountered.// typedef union{/ INTERCONNECT_HEADER_OVERLAY InterconnectX;) ACPI_INTERCONNECT AcpiInterconnect;( PCI_INTERCONNECT PciInterconnect;} INTERCONNECT;Q// See Table 2-4 in "DIG64 Descriptions for Primary Console & Debug Port Devices"// #if 0//B// This structure has been deprecated and has been replaced by the@// macro below it. It is left here for historical reference. OneH// reason for deprecating it is that, once the type has been determined,H// the pointer to the entry can be cast as that type to access the otherI// fields. This structure was replaced by the macro immediately below it,D// where other reasons for replacing this structure with a macro are // detailed.//:typedef struct { // PCDP new device t ype template UINT8 Type; UINT8 PrimaryConsole; // <0> UINT16 EntryLength; UINT16 ConDevIndex;} OSL_PCDP_NEWTYPE_ENTRY;#endif // ----------------------------- // OSL_PCDP_NEWTYPE_ENTRY_HEADER // -----------------------------H// See Table 2-4 in "DIG64 Descriptions for Primary Console & Debug Port // Devices"//I// This defines the header fields of the new PCDP descriptor type header.F// It is done as a macro so that the descriptors that use these headerK// fieds  can use the macro rather than redefining the fields. This providesK// more maintainability, because, if changes to the header are ever needed,L// the changes only have to be made to the macro, whereupon the changes will6// propagate to all the structures that use the macro.//'#define OSL_PCDP_NEWTYPE_ENTRY_HEADER \ UINT8 Type; \ UINT8 PrimaryConsole; \ UINT16 EntryLength; \ UINT16 ConDevIndex;(// -------------------------------------(// OSL_PCDP_ NEWTYPE_ENTRY_HEADER_OVERLAY(// -------------------------------------K// This structure is used in union with all the other PCDP descriptor typesL// so that the header fields may be accessed before knowing which descriptorN// type is being examined, most importantly, to access the Type field in order// to determine the type.//typedef struct{! OSL_PCDP_NEWTYPE_ENTRY_HEADER}&OSL_PCDP_NEWTYPE_ENTRY_HEADER_OVERLAY;)typedef struct { // PCDP UART descriptor5 UINT8 Type; // 0 = UART Desc, 1 = DEBUGPORT Desc UINT8 NumDataBits; UINT8 Parity; UINT8 StopBits;5 UINT8 PciSegNum; // If UART is a PCI device5 UINT8 PciBusNum; // If UART is a PCI device8 UINT8 PciDeviceNum; // If UART is a PCI device struct {# unsigned PciFunctionNum : 3; unsigned Rsvd : 5; } PciFunctionFields; UINT64 Baud; UINT8 AddressSpaceID; // 38 UINT8 RegisterBitWidth; UINT8 RegisterBitOffset; UINT8 Fill1; UINT64 BaseAddress; // 3C UINT16 DeviceID; UINT16 VendorID;! UINT32 GlobalSystemInterrupt; UINT32 PseudoClockRate;6 UINT8 PciClass; // Same as HCDP down to this point struct {% unsigned InterruptMode : 1;& unsigned InterruptPolarity : 1; unsigned Primary : 1; unsigned Rsvd : 3;% unsigned InterruptFlag : 1;% unsigned PciDeviceFlag : 1; } Flags; UINT16 ConDevIndex; UINT8 Rsvd[4];} OSL_PCDP_TYPE_0_1_ENTRY;Htypedef struct { // PCDP fPars Virtual Console descriptor! OSL_PCDP_NEWTYPE_ENTRY_HEADER UINT32 MinPollMsec; UINT32 SuggestedPollMsec; char ESITguid[16];} OSL_PCDP_TYPE_130_ENTRY;// ----------------// VGA_EXTADDR_DESC// ----------------(// X-49 TLC 20060804 VGA Console Support//D// See "DIG64 Descriptions for Primary Console & Debug Port Devices"// Tables 2-4 and 2-5//J// The VGA Extended Address Space Descriptor in the PCDP_ENTRY for the VGAH// device consists of 56 bytes as defined in the ACPI 3.0 Specification.I// There can be any number of these in the PCDP_ENTRY for the VGA consoleG// device, so we declare a data type as the first element in a possibleJ// array of these data types in the PCDP_ENTRY for the VGA console device.//typedef struct{ UINT8 VgaExtAddrDesc[56];}VGA_EXTADDR_DESC;// ----------------------// OSL_PCDP_TYPE_10_ENTRY// ----------------------(// X-49 TLC 20060804 VGA Console Support//D// See "DIG64 Descriptions for Primary Console & Debug Port Devices"// Tables 2-4 and 2-5//J// The OSL_PCDP_TYPE_10_ENTRY data structure defined below will be used byO// acpi$osl_console_config() when it discovers a VGA console entry in the PCDP.J// This new structure will be included in the OSL_PCDP_ENTRY union defined// below in this file.//typedef struct{! OSL_PCDP_NEWTYPE_ENTRY_HEADER% INTERCONNECT  Interconnect;< UINT8 DescCount; // Num of descriptors}*OSL_PCDP_TYPE_10_ENTRY; // VGA Entry TypeAtypedef union { // Add any new device descriptors to this union1 OSL_PCDP_NEWTYPE_ENTRY_HEADER_OVERLAY DevX;3 OSL_PCDP_TYPE_0_1_ENTRY Dev0_1;3 OSL_PCDP_TYPE_130_ENTRY Dev130;2 OSL_PCDP_TYPE_10_ENTRY Dev10;} OSL_PCDP_ENTRY; O// SPCR - Serial Port Configuration Register (Console when HCDP is not present)Htypedef struct // Watch for this structure to appear in later code drops{ ACPI_TABLE_HEADER Header; UINT8 InterfaceType; UINT8 Reserved[3]; UINT8 AddressSpaceID; UINT8 RegisterBitWidth; UINT8 RegisterBitOffset; UINT8 Fill1; UINT64 BaseAddress; UINT8 InterruptType; UINT8 IRQ;# UINT8 GlobalSystemInterrupt[4]; UINT8 BaudRate; UINT8 Parity; UINT8 StopBits; UINT8 FlowControl; UINT8 TerminalType; UINT8 Language; UINT16 PCIDeviceID; UINT16 PCIVendorID; UINT8 PCIBusNumber; UINT8 PCIDeviceNumber; UINT8 PCIFunctionNumber; UINT8 PCIFlags[4]; UINT8 PCISegment; UINT8 Reserved2[4]; } OSL_SPCR;$#pragma __member_alignment __restore)#endif // _ACPI_OSL_EXTENSION_STRUCTURESwwhZU&//#pragma module PAGING_MACROS.H "X-9"#ifndef __PAGING_MACROS_LOADED#define __PAGING_MACROS_LOADED/*J ******************* ****************************************************** * *J * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *J * proprietary software licensed by VMS Software, Inc., and is not *J * authorized to be used, duplicated or disclosed to anyone without *J * the prior written permission of VMS Software, Inc. *J * Copyright 2019-2021 VMS Software, Inc. * * *J ************************************************************************* *" * FACILITY: VMS Executive (LIB_H) *I * ABSTRACT: This module contains C macros for accessing and manipulating * PTEs for x86. * * Author: Drew Mason * * Creation Date: 19-Jul-2017 * * Revision History: *) * X-9 GHJ Gregory H. Jordan 23-Aug-2021A * Add a 4k variant of the various pte_va macros for X86. TheseG * macros will return the address of the 4K pte instead of the address * of the PTE pair. *) * X-8 GHJ Gregory H.  Jordan 20-Feb-20199 * Update $$xxpte_va macros to handle a PTEs pointing to/ * the top level page table self map pointers. *# * X-7 AHM Drew Mason 16-Aug-20185 * Change macros BCNT_TO_PAGES and VA_TO_BOFF to use3 * the allocated page size of 8192 rather than the% * hardware page size of 4096 bytes. *- * X-6 GHJ Gregory H. Jordan 11-Jul-20187 * Modify macros that return a VA to alwasy return the6 * PTE Va for an 8K page. Pull out bpte_va as it is  * moving to vms_macros.h *" * X-5 AHM Drew Mason 6-Jun-20185 * Conditionalize the macros that return PTE virtual2 * addresses to use boo$ variables in SYSBOOT and4 * mmg$ variables otherwise. Use the quadword form * of the PTE_LEVELS variables. *# * X-4 AHM Drew Mason 20-Apr-20186 * Fix bug in the mask used in pml4e_va and pdpte_va. *$ * X-3 GHJ Greg Jordan 17-Apr-20184 * Fix use of __SYSBOOT, needs to be in upper case. *$ * X-2 GHJ Greg Jordan 11-Apr-2018: * Switch usage of BOO$GL_PTE_LEVELS to MMG$GL_PTE_LEVELSL * unless __SYSBOOT is defined. Rename pteidx_pt tp pteidx_bpt * and pto_pt to pto_bpt. *# * X-1 AHM Drew Mason 19-Mar-2018/ * Move this .h file from SYSBOOTX86 to LIB_H. *, * --- Resync modification history for LIB_H *" * X-2 AHM Drew Mason 2-Feb-20186 * Change "spt" to "bpt" for bottom page table to use! * a term that has less baggage. *# * X-1 AHM Drew Mason 19-Jul-2017 * Initial entry.*/#ifndef __INITIAL_POINTER_SIZEb #error SYS-F-NOPTRSIZE, x86 memory-management code must compile with the /POINTER_SIZE qualifier#endif&#pragma __required_pointer_size __save&#pragma __required_pointer_size __long#include #include #include C// This construct allows SYSBOOT write access to variables that are?// run-time constants, but need to be initialized at boot time.#ifdef __SYSBOOT#define __RUNCONST#else#define __RUNCONST const#endif'#define BCNT_TO_PAGES( BCNT ) \< (((BCNT) + MMG$$C_BYTES_PER_PAGE - 1) >> MMG$$C_BOFF_SIZE)#define VA_TO_BOFF( VA ) \ (VA & MMG$$C_BOFF_MASK_8K)/*! ! MACROS:! pteidx_pml5 (addr)! pteidx_pml4 (addr)! pteidx_pdpt (addr)! pteidx_pd (addr)! pteidx_bpt (addr)! ! FUNCTION:!Q! These routines and macros accept a virtual address and return the correspondingQ! page-table field. The return value is, equivalently, the index (not offset) inR! the page-table page for the input address. This is an index within the specific3! page, not the index within the entire page table.!J! The purpose of embedding the routine in a #define is so that the routine6! can be passed any type that can be cast as an int64.! ! NOTES:!K! (1) In contrast to previous VMS practice, the order of the page tables isQ! reversed: the L4 or L5 page table is the one farthest from the target page.P! CR3 (the x86 equivalent of PTBR) contains the physical address of the PML4O! or PML5 page table, depending on whether the system is running with 4- or! 5-level pagins.I! (2) These macros are intended to work with either 4- or 5-level paging.P! (3) All that these routines do is mask and shift the appropriate bits from theH! input VA so that they are at the low end of the returned quadword.R! (4) It is the caller's responsibility to locate the appropriate page-table page.M! (5) There is no guarantee that the page-table page is valid or even exis ts.R! (6) If given an address within a 1-GB or 2-MB page, pteidx_bpt will still returnK! the PT index that corresponds to this address. It is likely that theO! BPT page for this address does not exist. The caller must sort this out.T! (7) Similarly, if given an address within a 1-GB page, pteidx_pd will still returnK! the PD index that corresponds to this address. It is likely that theN! PD page for this address does not exist. The caller must sort this out.! ! ARGUM ENTS:!! addr (Passed by value)9! The virtual address whose PT field is to be returned.!! SIDE EFFECTS:!! None.! ! RETURNS:!O! The appropriate field of the VA passed to this routine, returned as an index.!! EXAMPLE CALL:! ! int64 addr;! uint64 levelField;"! levelField = pteidx_pdpt (addr);!! CHANGE HISTORY:*/!//#pragma inline ($$$pteidx_pml5))static uint64 $$$pteidx_pml5 (int64 addr){8 return (addr & MMG$$C_PML5_MASK) >> MMG$$C_PML5_BIT!POS;}7#define pteidx_pml5(addr) $$$pteidx_pml5 ((int64) addr)!//#pragma inline ($$$pteidx_pml4))static uint64 $$$pteidx_pml4 (int64 addr){8 return (addr & MMG$$C_PML4_MASK) >> MMG$$C_PML4_BITPOS;}7#define pteidx_pml4(addr) $$$pteidx_pml4 ((int64) addr)!//#pragma inline ($$$pteidx_pdpt))static uint64 $$$pteidx_pdpt (int64 addr){8 return (addr & MMG$$C_PDPT_MASK) >> MMG$$C_PDPT_BITPOS;}7#define pteidx_pdpt(addr) $$$pteidx_pdpt ((int64) addr)//#pragma inline ("$$$pteidx_pd)'static uint64 $$$pteidx_pd (int64 addr){4 return (addr & MMG$$C_PD_MASK) >> MMG$$C_PD_BITPOS;}3#define pteidx_pd(addr) $$$pteidx_pd ((int64) addr) //#pragma inline ($$$pteidx_bpt)(static uint64 $$$pteidx_bpt (int64 addr){6 return (addr & MMG$$C_BPT_MASK) >> MMG$$C_BPT_BITPOS;}5#define pteidx_bpt(addr) $$$pteidx_bpt ((int64) addr)/*! ! MACROS:! pto_pml5e (addr)! pto_pml4e (addr)! pto_pdpte (addr)! pto_pde (addr)! pto_bpte (addr)#! ! FUNCTION:!Q! These routines and macros accept a virtual address and return the correspondingN! page-table field. The return value is, equivalently, the offset (not index)M! in the page-table page for the input address. This is an offset within the=! specific page, not the offset within the entire page table.!J! The purpose of embedding the routine in a #define is so that the routine6! can be passed any type that can be cast as an int64.! ! NOTES:!K! (1) In contrast to$ previous VMS practice, the order of the page tables isM! reversed: the L1 page table is the one closest to the target 4-kB page.G! The L4 or L5 page table is the one farthest from the target page.K! CR3 (the x86 equivalent of PTBR) contains the physical address of theI! PML4 or PML5 page table, depending on whether the system is running!! with 4- or 5-level paging.I! (2) These macros are intended to work with either 4- or 5-level paging.P! (3) All that these routine%s do is mask and shift the appropriate bits from theH! input VA so that they are at the low end of the returned quadword.R! (4) It is the caller's responsibility to locate the appropriate page-table page.M! (5) There is no guarantee that the page-table page is valid or even exists.P! (6) If given an address within a 1-GB or 2-MB page, pto_bpte will still returnL! the BPT index that corresponds to this address. It is likely that theO! BPT page for this address does not exist. The c&aller must sort this out.R! (7) Similarly, if given an address within a 1-GB page, pto_pde will still returnK! the PD index that corresponds to this address. It is likely that theN! PD page for this address does not exist. The caller must sort this out.! ! ARGUMENTS:!(! addr (Passed by value)?! The virtual address whose PT field is to be returned.!! SIDE EFFECTS:!! None.! ! RETURNS:!T! The appropriate field of the VA passed t'o this routine, returned as an offset.!! EXAMPLE CALL:! ! int64 addr;! uint64 levelField; ! levelField = pto_pdpte (addr);!! CHANGE HISTORY:*///#pragma inline ($$$pto_pml5e)'static uint64 $$$pto_pml5e (int64 addr){; return (addr & MMG$$C_PML5_MASK) >> MMG$$C_PML5_OFFPOS;}3#define pto_pml5e(addr) $$$pto_pml5e ((int64) addr)//#pragma inline ($$$pto_pml4e)'static uint64 $$$pto_pml4e (int64 addr){; return (addr & MMG$$C_PML4_MASK) >> MMG$$C_PML4_OF(FPOS;}3#define pto_pml4e(addr) $$$pto_pml4e ((int64) addr)//#pragma inline ($$$pto_pdpte)'static uint64 $$$pto_pdpte (int64 addr){; return (addr & MMG$$C_PDPT_MASK) >> MMG$$C_PDPT_OFFPOS;}4 #define pto_pdpte(addr) $$$pto_pdpte ((int64) addr)//#pragma inline ($$$pto_pde)%static uint64 $$$pto_pde (int64 addr){7 return (addr & MMG$$C_PD_MASK) >> MMG$$C_PD_OFFPOS;}/#define pto_pde(addr) $$$pto_pde ((int64) addr)//#pragma inline ($$$pto_bpte)&static u)int64 $$$pto_bpte (int64 addr){9 return (addr & MMG$$C_BPT_MASK) >> MMG$$C_BPT_OFFPOS;}1#define pto_bpte(addr) $$$pto_bpte ((int64) addr)/*! ! MACROS:! pml5e_va (addr, mode)! pml4e_va (addr, mode)! pdpte_va (addr, mode)! pde_va (addr, mode)! bpte_va (addr, mode)!! pml5e_va_4k (addr, mode)! pml4e_va_4k (addr, mode)! pdpte_va_4k (addr, mode)! pde_va_4k (addr, mode)! bpte_va_4k (addr, mode)! ! FUNCTION:!@! These routines and macros return the * VA of the PTE that maps a?! given VA. The specific macro identifies which of the several?! mapping PTEs are to be returned. Result depends on execution! mode.!J! The purpose of embedding the routine in a #define is to that the routine6! can be passed any type that can be case as an int64.! ! NOTES:!I! (1) These macros are intended to work with either 4- or 5-level paging.D! But they are not very smart. If you call pml5e_va on a systemF! that does not have 5-level p +aging enabled, the return value willE! be zero. (There are better ways to determine if 5-level paging ! is on.D! (2) All these routines do is mask, shift, and add the value to theE! address of the appropriate page-table base. If you ask for theD! VA of a PDE, the macro does not check whether the PML5 or PML4=! entries are valid. That's the caller's responsibility.G! (3) bpte_va invoked on a 1-GB or 2-MB will still return the VA of theG! BPTE that corresponds to t,hat address. It is likely that the BPTF! page for that address does not exist. The caller must sort thisE! out. A similar note applies to invoking pde_va on a 1-GB page.!E! It is up to the caller to determine if 5-level paging is enabled...! ! ARGUMENTS:! addr (Passed by value):! The virtual address for which a PTE address is desired.! mode (Passed by value)9! Which of the per-mode page table addresses is desired.!! SIDE EFFECTS:!! None!! EXAMPLE CAL-L:!! #include ! #include ! int64 addr;! PTE_PQ pdentry_va;!*! pdentry_va = pde_va (addr, PSL$C_SUPER);*/#if defined __SYSBOOT2#define PAGING_MACROS$PTE_LEVELS boo$gq_pte_levels0#define PAGING_MACROS$BPT_BASE boo$gq_bpt_base/#define PAGING_MACROS$PD_BASE boo$gq_pd_base1#define PAGING_MACROS$PDPT_BASE boo$gq_pdpt_base1#define PAGING_MACROS$PML4_BASE boo$gq_pml4_base1#define PAGING_MACROS$PML5_BASE boo$gq_pml5_base#else2#define PAGING_MACRO .S$PTE_LEVELS mmg$gq_pte_levels0#define PAGING_MACROS$BPT_BASE mmg$gq_bpt_base/#define PAGING_MACROS$PD_BASE mmg$gq_pd_base1#define PAGING_MACROS$PDPT_BASE mmg$gq_pdpt_base1#define PAGING_MACROS$PML4_BASE mmg$gq_pml4_base1#define PAGING_MACROS$PML5_BASE mmg$gq_pml5_base#endif#pragma inline ($$$pml5e_va)3static PTE_PQ $$$pml5e_va (int64 addr, uint32 mode){> extern unsigned __int64 __RUNCONST PAGING_MACROS$PTE_LEVELS;7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML5_BASE [4];/ __int64 offset; __int64 va_pte;$ if (PAGING_MACROS$PTE_LEVELS != 5) { return (PTE_PQ) 0; }; offset = (addr & MMG$$C_PML5_MASK) >> MMG$$C_PML5_OFFPOS;#ifndef __SYSBOOT ) offset &= ~0xF; // Point to PTE pair #endifb va_pte = (__int64) PAGING_MACROS$PML5_BASE [mode] + offset + ((mode % 2) * PTE$C_BYTES_PER_PTE); return ((PTE_PQ) va_pte);} // end $$$pml5e_vaI#define pml5e_va(addr,mode) $$$pml5e_va ((int64) (addr), (uint32) (mode))#pragma inline (0$$$pml4e_va)3static PTE_PQ $$$pml4e_va (int64 addr, uint32 mode){> extern unsigned __int64 __RUNCONST PAGING_MACROS$PTE_LEVELS;7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML4_BASE [4];7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML5_BASE [4]; __int64 mask; __int64 offset; __int64 va_pte;$ if (PAGING_MACROS$PTE_LEVELS == 5)/ mask = MMG$$C_PML5_MASK | MMG$$C_PML4_MASK; else mask = MMG$$C_PML4_MASK;/ offset = (addr & mask) >> MMG$$C_PML4_OFFPOS;#ifndef __SYSBOO 1T ) offset &= ~0xF; // Point to PTE pair #endif= va_pte = (__int64) PAGING_MACROS$PML4_BASE [mode] + offset;T // If va_pte is the self map PTE in the top level page table, fix up based on mode& if (PAGING_MACROS$PTE_LEVELS == 4) {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML4_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))3 va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } else {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML5_BASE[mode]2+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))3 va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } return ((PTE_PQ) va_pte);} // end $$$pml4e_vaI#define pml4e_va(addr,mode) $$$pml4e_va ((int64) (addr), (uint32) (mode))#pragma inline ($$$pdpte_va)3static PTE_PQ $$$pdpte_va (int64 addr, uint32 mode){> extern unsigned __int64 __RUNCONST PAGING_MACROS$PTE_LEVELS;7 extern PTE_PQ __RUNCONST PAGING_MACROS$PDPT_BASE [4];7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML4_BASE3 [4];7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML5_BASE [4]; __int64 mask; __int64 offset; __int64 va_pte;- mask = MMG$$C_PML4_MASK | MMG$$C_PDPT_MASK;> if (PAGING_MACROS$PTE_LEVELS == 5) mask |= MMG$$C_PML5_MASK;/ offset = (addr & mask) >> MMG$$C_PDPT_OFFPOS;#ifndef __SYSBOOT ) offset &= ~0xF; // Point to PTE pair #endif= va_pte = (__int64) PAGING_MACROS$PDPT_BASE [mode] + offset;T // If va_pte is the self map PTE in the top level page table, fix up based on 4mode& if (PAGING_MACROS$PTE_LEVELS == 4) {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML4_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))3 va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } else {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML5_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))3 va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } return ((PTE_PQ) va_pte);} // end $$$pdpte_vaI#define pdpte_va(addr,mode) $$$p5dpte_va ((int64) (addr), (uint32) (mode))#pragma inline ($$$pde_va)1static PTE_PQ $$$pde_va (int64 addr, uint32 mode){> extern unsigned __int64 __RUNCONST PAGING_MACROS$PTE_LEVELS;5 extern PTE_PQ __RUNCONST PAGING_MACROS$PD_BASE [4];7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML4_BASE [4];7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML5_BASE [4]; __int64 mask; __int64 offset; __int64 va_pte;> mask = MMG$$C_PML4_MASK | MMG$$C_PDPT_MASK | MMG$$C_PD_MASK;> if (PAGING_MAC 6ROS$PTE_LEVELS == 5) mask |= MMG$$C_PML5_MASK;- offset = (addr & mask) >> MMG$$C_PD_OFFPOS;#ifndef __SYSBOOT ) offset &= ~0xF; // Point to PTE pair #endif; va_pte = (__int64) PAGING_MACROS$PD_BASE [mode] + offset;T // If va_pte is the self map PTE in the top level page table, fix up based on mode& if (PAGING_MACROS$PTE_LEVELS == 4) {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML4_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))3 va_pte += (mode % 72) * PTE$C_BYTES_PER_PTE; } else {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML5_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))3 va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } return ((PTE_PQ) va_pte);} // end $$$pde_vaE#define pde_va(addr,mode) $$$pde_va ((int64) (addr), (uint32) (mode))#pragma inline ($$$pml5e_va_4k)6static PTE_PQ $$$pml5e_va_4k (int64 addr, uint32 mode){> extern unsigned __int64 __RUNCONST PAGING_MACROS$PTE_LEV8ELS;7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML5_BASE [4]; __int64 offset; __int64 va_pte;$ if (PAGING_MACROS$PTE_LEVELS != 5) { return (PTE_PQ) 0; }; offset = (addr & MMG$$C_PML5_MASK) >> MMG$$C_PML5_OFFPOS;b va_pte = (__int64) PAGING_MACROS$PML5_BASE [mode] + offset + ((mode % 2) * PTE$C_BYTES_PER_PTE); return ((PTE_PQ) va_pte);} // end $$$pml5e_va_4kO#define pml5e_va_4k(addr,mode) $$$pml5e_va_4k ((int64) (addr), (uint32) (mode))#pragma inline9 ($$$pml4e_va_4k)6static PTE_PQ $$$pml4e_va_4k (int64 addr, uint32 mode){> extern unsigned __int64 __RUNCONST PAGING_MACROS$PTE_LEVELS;7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML4_BASE [4];7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML5_BASE [4]; __int64 mask; __int64 offset; __int64 va_pte;$ if (PAGING_MACROS$PTE_LEVELS == 5)/ mask = MMG$$C_PML5_MASK | MMG$$C_PML4_MASK; else mask = MMG$$C_PML4_MASK;/ offset = (addr & mask) >> MMG$$C_PML4_OFFPOS;= va_pte: = (__int64) PAGING_MACROS$PML4_BASE [mode] + offset;T // If va_pte is the self map PTE in the top level page table, fix up based on mode& if (PAGING_MACROS$PTE_LEVELS == 4) {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML4_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))3 va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } else {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML5_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))3 va_pte; += (mode % 2) * PTE$C_BYTES_PER_PTE; } return ((PTE_PQ) va_pte);!} // end $$$pml4e_va_4kO#define pml4e_va_4k(addr,mode) $$$pml4e_va_4k ((int64) (addr), (uint32) (mode))#pragma inline ($$$pdpte_va_4k)6static PTE_PQ $$$pdpte_va_4k (int64 addr, uint32 mode){> extern unsigned __int64 __RUNCONST PAGING_MACROS$PTE_LEVELS;7 extern PTE_PQ __RUNCONST PAGING_MACROS$PDPT_BASE [4];7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML4_BASE [4];7 extern PTE_PQ __RUNCONST PAGIN <G_MACROS$PML5_BASE [4]; __int64 mask; __int64 offset; __int64 va_pte;- mask = MMG$$C_PML4_MASK | MMG$$C_PDPT_MASK;> if (PAGING_MACROS$PTE_LEVELS == 5) mask |= MMG$$C_PML5_MASK;/ offset = (addr & mask) >> MMG$$C_PDPT_OFFPOS;= va_pte = (__int64) PAGING_MACROS$PDPT_BASE [mode] + offset;T // If va_pte is the self map PTE in the top level page table, fix up based on mode& if (PAGING_MACROS$PTE_LEVELS == 4) {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML4_BASE=[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))3 va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } else {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML5_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))3 va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } return ((PTE_PQ) va_pte);!} // end $$$pdpte_va_4kO#define pdpte_va_4k(addr,mode) $$$pdpte_va_4k ((int64) (addr), (uint32) (mode))#pragma inline ($$$pde_va_4k)4static PTE_PQ $$>$pde_va_4k (int64 addr, uint32 mode){> extern unsigned __int64 __RUNCONST PAGING_MACROS$PTE_LEVELS;5 extern PTE_PQ __RUNCONST PAGING_MACROS$PD_BASE [4];7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML4_BASE [4];7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML5_BASE [4]; __int64 mask; __int64 offset; __int64 va_pte;> mask = MMG$$C_PML4_MASK | MMG$$C_PDPT_MASK | MMG$$C_PD_MASK;> if (PAGING_MACROS$PTE_LEVELS == 5) mask |= MMG$$C_PML5_MASK;- offset = (addr & mask) >> MMG$$C_PD_?OFFPOS;; va_pte = (__int64) PAGING_MACROS$PD_BASE [mode] + offset;T // If va_pte is the self map PTE in the top level page table, fix up based on mode& if (PAGING_MACROS$PTE_LEVELS == 4) {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML4_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))3 va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } else {x if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML5_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2)))@3 va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } return ((PTE_PQ) va_pte);} // end $$$pde_va_4kK#define pde_va_4k(addr,mode) $$$pde_va_4k ((int64) (addr), (uint32) (mode))#pragma inline ($$$bpte_va_4k)5static PTE_PQ $$$bpte_va_4k (int64 addr, uint32 mode){6 extern PTE_PQ __RUNCONST PAGING_MACROS$BPT_BASE [4];#ifndef __SYSBOOT 7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML4_BASE [4];7 extern PTE_PQ __RUNCONST PAGING_MACROS$PML5_BASE [4];#endif> Aextern __RUNCONST unsigned __int64 PAGING_MACROS$PTE_LEVELS; __int64 mask; __int64 offset; __int64 va_pte;#if defined(TEST$MMG)$ va_pte = test$mmg_bpte_va( addr );/ if (va_pte != 0) return ((PTE_PQ) va_pte); #endif P mask = MMG$$C_PML4_MASK | MMG$$C_PDPT_MASK | MMG$$C_PD_MASK | MMG$$C_BPT_MASK;> if (PAGING_MACROS$PTE_LEVELS == 5) mask |= MMG$$C_PML5_MASK;. offset = (addr & mask) >> MMG$$C_BPT_OFFPOS;; va_pte = (uint64) PAGING_MACROS$BPT_BASE [mode] + offset;#i Bfndef __SYSBOOT W /* If va_pte is the self map PTE in the top level page table, fix up based on mode */& if (PAGING_MACROS$PTE_LEVELS == 4) {y if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML4_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2))) , va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } else {y if ((va_pte & ~0x10ull) == (__int64) PAGING_MACROS$PML5_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2))) , va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; }C#endif return ((PTE_PQ) va_pte);} /* end $$$bpte_va_4k */M#define bpte_va_4k(addr,mode) $$$bpte_va_4k ((int64) (addr), (uint32) (mode))*# pragma __required_pointer_size __restore"#endif // __PAGING_MACROS_LOADEDwwZU#ifndef __PFN_MACROS_LOADED#define __PFN_MACROS_LOADED 1/* Version X-26 */J/*************************************************************************J * *J * HDPE CONFIDENTIAL. This software is confidential proprietary software *J * licensed by Hewlett Packard Enterprise Development, LP, and is not *J * authorized to be used, duplicated or disclosed to anyone without the *J * prior written permission of HPE. *J * Copyright 2017 Hewlett Packard Enterprise Development, LP *J * *J * VMS SOFTWARE, INC. CONFIDENTIAL. This software is c Eonfidential *J * proprietary software licensed by VMS Software, Inc., and is not *J * authorized to be used, duplicated or disclosed to anyone without *J * the prior written permission of VMS Software, Inc. *J * Copyright 2017-2021 VMS Software, Inc. *J * *J **************************************************************************//**++ * FACILITY:F** VMS Executive (LIB_H)* * ABSTRACT:*=* This header file provides the PFN macros & routines for C.* * AUTHOR:** Nitin Karkhanis*"* CREATION DATE: 17-Oct-1994** MODIFICATION HISTORY:*#* X-26 AHM Drew Mason 20-Jul-2021:* Change shift amounts in valid_pfn_2mb and valid_pfn_1gb*C* X-25 CEG0917 Clair Grant 25-Sep-2020&* Change comment in X-24*(* X-24 CEG0908 Clair Grant 24-Sep-2020** Replace G "// comment" style to eliminate+* confusion when compiling /STANDARD=VAXC.*2* X-23 GHJ Gregory H. Jordan 1-Sep-2020<* Revert back change X-22 so that DECSHR will decrement the1* SHRCNT for outer mode bottom page table pages.*2* X-22 GHJ Gregory H. Jordan 17-Dec-2019H* Update DECSHR to not decrement the SHRCNT for outer mode(* bottom page table pages.*$* X-21 AHM Drew Mason 20-Nov-20199* For x86, add prototypes for mmg$access_Hbackpointer and2* mmg$establish_backpointer to quiet build noise.*2* X-20 GHJ Gregory H. Jordan 29-May-2019:* Change the establish_backpointer and access_backpointer9* macros to call global routines to perform the function * on X86.*2* X-19 GHJ Gregory H. Jordan 10-Dec-20186* Don't inlcude pte_functions.h and remove use of the8* $write_one_pte macro. Do the work by hand. Too many8* conflicts arise due to varying defines of data cells.*2* X-18 IGHJ Gregory H. Jordan 6-Dec-20183* Turn access_backpointer back on for X86 and use /* $insert_pfn to update the mmg$gq_window_pte.*2* X-17 GHJ Gregory H. Jordan 1-Oct-20186* Change valid_pfn for X86 to use the PMAP structure.*2* X-16 GHJ Gregory H. Jordan 25-Apr-2018&* Add additional X86 specific macros:* valid_pfn_2mb* valid_pfn_1g* pfn_to_entry_2mb* pfn_to_entry_1g*=* Make pfn_to_entry architecture specific since X86 needs to7* shift J then pfn right by 1 to obtain the pfndb index.*#* X-15 AHM Drew Mason 29-Nov-2017<* Update copyright. Update for x86. Add an x86 version of<* valid_pfn. Add __RUNCONST to allow SYSBOOT to write intoC* data cells that are runtime constants. Stub out the backpointer2* macros for x86 until we know what goes in them.*** X-14 KLN3502 Karen L. Noel 15-Apr-2004?* Fix access_backpointer macro for slot pages that are mapped.*)* X-13 KLN3448 Karen L. Noel 5-Mar-2004* ForK 50-bit PA project:* o Use PFN$I fields.<* o Use mmg$gq_window_pte instead of mmg$gq_window_pte_pfn.* o Use PFN_T typedef.* o Reference PMM64 structure.*** X-12 KLN3410 Karen L. Noel 12-Jan-2004;* Define mmg window cells non-const for the C module that <* initializes these cells. These definitions are under the * MMG_WINDOW_INIT symbol.*)* X-11 KLN3368 Karen L. Noel 8-Oct-2003#* Avoid informational on decshr().*-* X-9A12 KLN3052 Karen L. Noel 5-April-20026 L* Only define backpointer functions to be called from9* modules that compile with the /pointer_size qualifier.*,* X-9A11 KLN3025 Karen L. Noel 26-Feb-2002:* o Change references to mmg$gq_pt_base, mmg$gq_l1_base, 7* mmg$gq_l2_base and mmg$gl_l1_index for IPF.:* o Include VRNX field in PTE_INDEX field of PFN database * entry.C* o Remove inline pragmas. We trust the compiler now.*$* X-9A10 Andy Kuehnel 25-Jul-2000** Fix pfn_to_entry macro for high mMemory.*-* X-18 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*"* X-17 Andy Kuehnel 7-Jan-1998=* PMM is only defined with __NEW_STARLET. Compile VALID_PFN$* only if __NEW_STARLET is defined.*"* X-16 Andy Kuehnel 30-Dec-1997-* Use SYI PFN memory map in VALID_PFN macro.*"* X-15 Andy Kuehnel 6-Jan-1996:* Add return statements after bug_check in orNder to avoid* CC-W-FALLOFFEND messages.*-* X-14 NYK574 Nitin Y. Karkhanis 8-Mar-1996* Add VALID_PFN.*** X-13 KLN1530 Karen L. Noel 13-Oct-1995B* 1. Fix typo, should include mmg_routines.h, not mmg_functions.h?* 2. Also should include pfndef.h, ptedef.h and far_pointers.h*-* X-12 NYK495 Nitin Y. Karkhanis 4-Oct-1995#* Add ALLOCPFN and ALLOC_ZERO_PFN.*-* X-11 NYK475 Nitin Y. Karkhanis 15-Sep-19957* MMG$GQ_WINDOW_PTE_PFN declared has an uint64 instead* of asO an INT_PQ.*-* X-10 NYK467 Nitin Y. Karkhanis 1-Sep-19958* Make sure short pointers to struct _PTE are passed to'* svapte_to_va_pte conversion routine.*,* X-9 NYK367 Nitin Y. Karkhanis 13-Apr-1995=* Replace instances of PFN$PL_DATABASE with PFN$PQ_DATABASE.*,* X-8 NYK343 Nitin Y. Karkhanis 6-Apr-1995@* Use long PFN database entry pointers (i.e. PFN_PQ and PFN_PPQ * instead of PFN * and PFN **).*,* X-7 NYK333 Nitin Y. Karkhanis 31-Mar-1995;* Compute backpointers foPr RESERVED and UNKNOWN page types6* as long as PT_PFN for corresponding PFN db entry is * non-zero.*,* X-6 NYK327 Nitin Y. Karkhanis 28-Mar-19958* Update macros to reflect their Macro-32 counterparts.*,* X-5 NYK254 Nitin Y. Karkhanis 1-Feb-19954* Modify extern declarations to match VMS_MACROS.H.*,* X-4 NYK173 Nitin Y. Karkhanis 19-Dec-19942* Cast return value from pfn_to_entry to (PFN *).*,* X-3 NYK101 Nitin Y. Karkhanis 10-Nov-19946* Mmg$gq_system_virtual_base was imQproperly declared.7* Cast arguments to pte_va to VOID_PQ since pte_va has8* temporarily (until C compiler properly handles 64-bit!* expressions) become a routine.*,* X-2 NYK095 Nitin Y. Karkhanis 2-Nov-1994* Update backpointer macros.,* Rename is_encumbered to test_backpointer.6* Add __PFN_MACROS_LOADED symbol to determine whether)* this header file was already included.**--*/F/* This construct allows SYSBOOT write access to variables that are */B/* run-time constaRnts, but need to be initialized at boot time. */#ifdef __SYSBOOT#define __RUNCONST#else#define __RUNCONST const#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */##endif /* __INITIAL_POINTER_SIZE *//*** MODULE PFN_MACROS ***//*= Include any header filesS we need to make these macros work.*/#include #include #include #include #include #include #include #include #include #include #include K/* The following code is only available to modules that compile with the */D/* pointer_size qualifier. Short, long, 32, or 64 are all okay. */'#ifdef __INITIAL_POINTER_SIZE #if __INITTIAL_POINTER_SIZE /*N This routine returns the virtual address of a PTE (VA_PTE) that maps the PFNP described by the entry passed in. The VA_PTE is only calculated if the PFN is@ encumbered (i.e. PFN$I_PT_PFN field of the entry is non-zero). Assumptions: MMG is held. Arguments:B entry: the PFN database entry for which a VA_PTE should be calculated.L va_pte: a quadword that is used to return the VA_PTE (page tableD space PTE)U that maps the PFN described by entry.B map: a flag to indicate that the returned VA_PTE should beE calculated using the address in MMG$GQ_WINDOW_VA.*/:#ifdef __x86_64 /* Verified for x86 port--Greg Jordan */Dvoid mmg$access_backpointer (PFN_PQ entry, PTE_PPQ va_pte, int map);0#define access_backpointer(entry,va_pte,map) { \/ mmg$access_backpointer(entry,va_pte,map); }#else##pragma inline (access_backpointer)Fstatic void access_backpointer (VPFN_PQ entry, PTE_PPQ va_pte, int map){ extern PTE_PQ __RUNCONST mmg$gq_gpt_base, mmg$gq_s0s1base_pte_address; extern PTE_PQ __RUNCONST$ mmg$gq_pt_base[VA$C_VRNX_COUNT];#if defined(MMG_WINDOW_INIT) extern VOID_PQ  mmg$gq_window_va; extern PTE_PQ  mmg$gq_window_pte;#else extern VOID_PQ __RUNCONST mmg$gq_window_va; extern PTE_PQ __RUNCONST mmg$gq_window_pte;#endif extern __RUNCONST uint64 mmg$gq_bwp_mask; uint64(W pte_index_mask = 0xffffffffffffffff; PTE_PQ pt_base; int vrnx;' pte_index_mask <<= PFN$S_INDEX_WIDTH;G/* The PTE backpointer can only be calculated if the PFN is encumbered0 (PFN$I_PT_PFN field is not zero). */ if (entry->pfn$i_pt_pfn == 0) { *va_pte = (PTE_PQ) 0; return; } vrnx = entry->pfn$v_vrnx; switch (entry->pfn$v_pagtyp) {F/* PTEs for process pages and process page table pages are determinedJ based upon wheXther the owning process is current. The map flag guidesN the decision on whether to compute a PTE address using the window page. */ case PFN$C_PROCESS : case PFN$C_PPGTBL :5/* Treat slot pages as system space pages. */! if (entry->pfn$v_slot == 1) {' pt_base = mmg$gq_pt_base[vrnx];J *va_pte = &(pt_base [(entry->pfn$q_pte_index & ~pte_index_mask)]); if (map == 1) {5 if (*va_pte >= mmg$gq_s0s1base_pte_addressY)9 *va_pte = va_pte_to_svapte ((PTE *) *va_pte); } return; }C/* Return the PT_space VA_PTE if mapping is not requested. */% pt_base = mmg$gq_pt_base[vrnx]; if (map == 0)J *va_pte = &(pt_base [(entry->pfn$q_pte_index & ~pte_index_mask)]); else {D/* To use the window address simply write the PFN of the page tableD containing the PTE of interest to the PFN field of the VA_PTE of" MMG$GQ_WINDOW_VA. Z */) PTE new_pte = *mmg$gq_window_pte;* $insert_pfn(new_pte,entry->pfn$i_pt_pfn); *mmg$gq_window_pte = new_pte;9 /* For X86, write the second PTE by hand... Pulling in 8 pte_functions.h here causes issues due to differringG definitions of constants... */:#ifdef __x86_64 /* Verified for x86 port--Greg Jordan */ new_pte.pte$v_pfn_4k++;" *(mmg$gq_window_pte+1) = new_pte;#endif> tbi_data_64 (mmg$gq_window_va, THIS_ [CPU_ONLY, NO_PCB);7 *va_pte = (PTE_PQ) ((uint64) mmg$gq_window_va +W (( (entry->pfn$q_pte_index & ~pte_index_mask ) << PTE$C_SHIFT_SIZE) &$ mmg$gq_bwp_mask)); } break;I/* PTEs for system pages and global page table pages can always be foundH in page table space since they are valid for every process. The mapJ flag of the macro guides the decision on whether the corresponding SPTH window address should be calculated (for S\0/S1 space VAs only). GPT( pages are simply system space pages.J Mapping a global page table page through the window makes little senseI since it's valid for every process and always available in page table space. */ case PFN$C_GPGTBL : case PFN$C_SYSTEM :# if (vrnx != VA$C_VRNX_SYSTEM)% bug_check (INCONMMGST, FATAL, COLD);% pt_base = mmg$gq_pt_base[vrnx];H *va_pte = &(pt_base [(entry->pfn$q_pte_index & ~pte_index_mask)]);J/* ]If mapping was requested return the corresponding SVAPTE if the VA_PTE0 maps FFFFFFFF.80000000 or higher. */ if (map == 1) {3 if (*va_pte >= mmg$gq_s0s1base_pte_address)/ *va_pte = va_pte_to_svapte (*va_pte); } break;G/* PTEs for global pages and global writable pages are valid for everyK process since they reside in system space. The map flag is meaningless4 in this case and is therefore ignored. */ case P^FN$C_GLOBAL : case PFN$C_GBLWRT :P *va_pte = &(mmg$gq_gpt_base [(entry->pfn$q_pte_index & ~pte_index_mask)]); break;I/* Compute VA_PTES for these types of pages as long as the a backpointer exists. */ case PFN$C_RESERVED: case PFN$C_UNKNOWN:' pt_base = mmg$gq_pt_base[vrnx]; # if (entry->pfn$i_pt_pfn != 0)J *va_pte = &(pt_base [(entry->pfn$q_pte_index & ~pte_index_mask)]); }} /* end access_backpointer */#endif_ /* ifdef __x86_64 */)#endif /* if __INITIAL_POINTER_SIZE */*#endif /* ifdef __INITIAL_POINTER_SIZE *//*E This routine, PFN_TO_ENTRY, is equivalent to its MACRO counterpart.@ It takes a PFN argument and converts it into an entry address.B For X86 with a 4k page size, the pfn database still describes 8kD pages so the pfn needs to be shifted right by 1 to get the correctF index. Separate macros exist for dealing with 2mb and 1G pages that make the appropriate shift.*/:#i`fdef __x86_64 /* Verified for x86 port--Greg Jordan */&static PFN_PQ pfn_to_entry (PFN_T pfn){ extern PFN_PQ __RUNCONST pfn$pq_database;A return (&(pfn$pq_database [pfn >> MMG$$C_PFN_TO_PFNDBIDX_4K]));}*static PFN_PQ pfn_to_entry_2mb (PFN_T pfn){ extern PFN_PQ __RUNCONST pfn$pq_database;B return (&(pfn$pq_database [pfn << MMG$$C_PFN_TO_PFNDBIDX_2MB]));})static PFN_PQ pfn_to_entry_1g (PFN_T pfn){ extern PFN_PQ __RUNCONST pfn$pq_database;A return (a&(pfn$pq_database [pfn << MMG$$C_PFN_TO_PFNDBIDX_1G]));}#else&static PFN_PQ pfn_to_entry (PFN_T pfn){ extern PFN_PQ __RUNCONST pfn$pq_database;$ return (&(pfn$pq_database [pfn]));}#endif/*I This macro allocates a PFN from the free list. If either the VA or VPNL argument is specified, a PFN of the corresponding color will be allocated.I To allocate a PFN with specifying a page color, both the VA and and VPNO arguments should be zero. This implies that a PFN can bnot be allocated to mapG VA or VPN 0. Any other scheme that enables a PFN color of zero to beO specified complicates the interface and was viewed as unnecessary; especially, since VPN 0 is typically a no access page.L Note that non-zero values for the both VA and VPN arguments will result inJ an INCONMMGST bugcheck. This approach was taken since it's not possible? to check the arguments at compile-time and generate an error.! Assumptions: MMG is held. Arguments:G c Entry: The address of the PFN database entry that corresponds to the PFN allocated.F VA: Virtual address which will map the allocated PFN. When@ this argument is specified, a PFN from the corresponding? color list will be allocated. The VA and VPN arguments> are mutually exclusive. Therefore, if VA if non-zero,& the VPN argument MUST be zero.D VPN: Virtual page number which will map the allocated PFN.7 When this ardgument is specified, A PFN from the? corresponding color list will be allocated. The VA and< VPN arguments are mutually exclusive. Therefore, if6 VPN is non-zero, the VA argument must be zero.D Returns: The PFN returned from the call to MMG$ALLOCATE_PFN.*/=static PFN_T allocpfn (PFN_PPQ entry, VOID_PQ va, uint64 vpn){ PFN_T pfn; uint64 byte_align;9#ifdef __x86_64 /* Verified for x86 port--Drew Mason */"#define BWP_WIDTH MMG$$C_BWP_WIDTH#elsee. extern __RUNCONST uint64 mmg$gq_bwp_width;"#define BWP_WIDTH mmg$gq_bwp_width#endif /* __x86_64 */J /* Determine requested byte alignment (0 = no particular alignment) */7 if (va && vpn) bug_check (INCONMMGST, FATAL, COLD);$ if (!va && !vpn) byte_align = 0;+ if (vpn) byte_align = vpn << BWP_WIDTH;$ if (va) byte_align = (uint64)va;# /* Attempt to allocate a PFN */: pfn = mmg$allocate_pfn (0, MMG$K_NO_RAD, byte_align); ( /* Get PFN database entry addrfess */( if (pfn) *entry = pfn_to_entry(pfn); /* Return PFN if any */ return (pfn);#undef BWP_WIDTH}/*P This macro allocates a PFN from the zeroed page list. If either the VA or VPNL argument is specified, a PFN of the corresponding color will be allocated.I To allocate a PFN with specifying a page color, both the VA and and VPNO arguments should be zero. This implies that a PFN cannot be allocated to mapG VA or VPN 0. Any other scheme that enables a PFN color gof zero to beO specified complicates the interface and was viewed as unnecessary; especially, since VPN 0 is typically a no access page.L Note that non-zero values for both the VA and VPN arguments will result inJ an INCONMMGST bugcheck. This approach was taken since it's not possible? to check the arguments at compile-time and generate an error.! Assumptions: MMG is held. Arguments:G Entry: The address of the PFN database entry that corresponds to t hhe PFN allocated.F VA: Virtual address which will map the allocated PFN. When@ this argument is specified, a PFN from the corresponding? color list will be allocated. The VA and VPN arguments> are mutually exclusive. Therefore, if VA if non-zero,& the VPN argument MUST be zero.D VPN: Virtual page number which will map the allocated PFN.7 When this argument is specified, A PFN from the? corresponding color list will be allociated. The VA and< VPN arguments are mutually exclusive. Therefore, if6 VPN is non-zero, the VA argument must be zero.C Returns: The PFN returned from the call to MMG$ALLOCATE_PFN*/Cstatic PFN_T alloc_zero_pfn (PFN_PPQ entry, VOID_PQ va, uint64 vpn){ PFN_T pfn; uint64 byte_align;9#ifdef __x86_64 /* Verified for x86 port--Drew Mason */"#define BWP_WIDTH MMG$$C_BWP_WIDTH#else. extern __RUNCONST uint64 mmg$gq_bwp_width;"#define BWP_WIDTH mmg$gq_bjwp_width#endif /* __x86_64 */J /* Determine requested byte alignment (0 = no particular alignment) */9 if (va && vpn) bug_check (INCONMMGST, FATAL, COLD);$ if (!va && !vpn) byte_align = 0;1 if (vpn) byte_align = vpn << BWP_WIDTH;- if (va) byte_align = (uint64)va;* /* Attempt to allocate a zero'd PFN */E pfn = mmg$allocate_pfn (MMG$M_ZEROED, MMG$K_NO_RAD, byte_align); ( /* Get PFN database entry address */( if (pfn) *entry = pfn_to_entryk(pfn); /* Return PFN if any */ return (pfn);#undef BWP_WIDTH}/*O This macro decrements the reference count of the specified PFN database entryM and initiates a REFCNTNEG bugcheck if the reference count becomes negative. Arguments:D entry: the PFN database entry whose reference count is to be decremented.*/d#define decref(entry) \d{ l \d if (((entry)->pfn$w_refcnt--) < 0) \d bug_check (REFCNTNEG, FATAL, COLD); \}/*K This macro decrements the share count of the specified PFN database entryC and initiates a SHRCNTNET bugcheck if the count becomes negative. Arguments:D entry: the PFN database entry whose reference count is to be m decremented.*/d#define decshr(entry) \d{ \d if ((int)((entry)->pfn$l_shrcnt--) < 0) \d bug_check (SHRCNTNEG, FATAL, COLD); \}K/* The following code is only available to modules that compile wi nth the */D/* pointer_size qualifier. Short, long, 32, or 64 are all okay. */'#ifdef __INITIAL_POINTER_SIZE #if __INITIAL_POINTER_SIZE /*O This routine establishes or clears the backpointer for the PFN database entryL specified. To establish a backpointer means to compute a PTE index off ofM either MMG$GQ_PT_BASE or MMG$GQ_GPT_BASE, and determine the PFN of the pageG table that maps the PTE to which this PFN database entry corresponds. K To clear a backpointer o means to disassociate a VA_PTE with a PFN databaseI entry. IF the VA_PTE argument is zero, the page table PFN field of the specified entry. Arguments:A entry: the PFN database entry whose backpointer should be established or cleared.K va_pte: the virtual address of a PTE to which this PFN is assigned.> If the argument is zero, the page table PFN field of the& entry specified will be cleared.E svapte: a flag denoting that the address passe pd in the va_pte* argument lies within the SPT window.B gpt: a flag denoting that the address passed in the va_pte> argument is an address within the global page table. IfB this flag is set, the macro uses MMG$GQ_GPT_BASE as the baseB of the page tables for the PTE index calculation. Note that: the gpt and svapte arguments can never both be true.J pt_pfn: PFN of a page table page containing the PTE that maps this? page. This may be supplied if q one wishes to override the5 PT_PFN value that otherwise would be calculated> automatically using the current mapping. This parameter> only has meaning when the gpt and svapte are both false.; It's contents will be ignored if either flag is true.*/:#ifdef __x86_64 /* Verified for x86 port--Greg Jordan */`void mmg$establish_backpointer (PFN_PQ entry, PTE_PQ va_pte, int svapte, int gpt, PFN_T pt_pfn);A#define establish_backpointer(entry,va_pte,svapte,gpt,pt_pfn) r{ \@ mmg$establish_backpointer(entry,va_pte,svapte,gpt,pt_pfn); }#elsebstatic void establish_backpointer (PFN_PQ entry, PTE_PQ va_pte, int svapte, int gpt, PFN_T pt_pfn){ extern PTE_PQN mmg$gq_max_gpte; /* Not declared as const since GPT can be expanded. */ extern PTE_PQ __RUNCONST mmg$gq_gpt_base, mmg$gq_s0s1base_pte_address, mmg$gq_sptbase; extern PTE_PQ __RUNCONST$ mmg$gq_pt_base[VA$C_VRNX_COUNT]; extern __RUNCONST uint64 mmg$gq_pte ss_per_page, mmg$gq_level_width, mmg$gq_non_pt_mask; extern VOID_PQ __RUNCONST mmg$gq_system_virtual_base; PTE_PQ temp; uint64 index,( pte_index_mask = 0xFFFFFFFFFFFFFFFF; int vrnx; uint64 ptes_per_page, size_of_pt_space; PTE_PQ  pt_base, pt_space_hi;#ifdef __NEW_STARLET VA v;#else va v;#endif' pte_index_mask <<= PFN$S_INDEX_WIDTH;A/* The VA_PTE supplied cannot be both a SVAPTE and GPTE. *t/ if (svapte == 1 && gpt == 1)( bug_check (INCONMMGST, FATAL, COLD);6/* Clear the backpointer if va_pte is zero. */ if (va_pte == (PTE_PQ) 0) { entry->pfn$i_pt_pfn = 0; return; }:/* We have a va_pte. Use it to extract the VRNX. */# ifdef __NEW_STARLET v.va$q_quad = (uint64)va_pte;# else( v.va$q_quad[0] = (unsigned int)va_pte;6 v.va$q_quad[1] = (unsigned int)((uint64)va_pte>>32);# endif vrnx = v.va$v_vrnx; entry->pfn$v_vrnux = vrnx; ,/* Check if a GPTE was supplied. */ if (gpt == 1) {>/* Verify that a GPTE address was actually supplied. */# if (va_pte < mmg$gq_gpt_base ||" va_pte >= mmg$gq_max_gpte)* bug_check (INCONMMGST, FATAL, COLD);K/* Establish the backpointer, while preserving the reference count. */M index = ((uint64) va_pte - (uint64) mmg$gq_gpt_base) >> PTE$C_SHIFT_SIZE;O entry->pfn$q_pte_index = (entry->pfn$q_pte_index & pte_index_masvk) | index;% temp = pte_va ((VOID_PQ) va_pte);* entry->pfn$i_pt_pfn = temp->pte$v_pfn; return; }I/* If VA_PTE contains a SVAPTE, compute the corresponding VA_PTE address- and establish the backpointer. */ if (svapte == 1) { PTE_PQ converted_va_pte;9/* Verify that a SVAPTE was actually supplied. */ if (va_pte < mmg$gq_sptbase)* bug_check (INCONMMGST, FATAL, COLD);9 converted_va_pte = svapte_to_va_pte ((PTE *)w va_pte);J/* Establish the backpointer,while preserving the reference count. */\ index = ((uint64) converted_va_pte - (uint64) mmg$gq_pt_base[vrnx]) >> PTE$C_SHIFT_SIZE;O entry->pfn$q_pte_index = (entry->pfn$q_pte_index & pte_index_mask) | index;/ temp = pte_va ((VOID_PQ) converted_va_pte);* entry->pfn$i_pt_pfn = temp->pte$v_pfn; return; }@/* If execution has progressed this far, the following is true: o gpt flag is false. o svapte flag is false x4 o a va_pte was passed in (needs to be verified).J o the contents of pt_pfn must be recorded in the PFN database entry if# it contains a non-zero value.*/A/* Compute the size of PT space given 3 levels of page tables */ ' ptes_per_page = mmg$gq_ptes_per_page;S size_of_pt_space = ptes_per_page*ptes_per_page*ptes_per_page*PTE$C_BYTES_PER_PTE;! pt_base = mmg$gq_pt_base[vrnx];E pt_space_hi = (PTE_PQ)((uint64)pt_base + (uint64)size_of_pt_space);0 if (va_pte < pt_base || yva_pte >= pt_space_hi)( bug_check (INCONMMGST, FATAL, COLD);K/* Establish the backpointer. At this point the gpt and svapte flags mustK be false so consider the value of pt_pfn when updating the PFN database entry. */C index = ((uint64) va_pte - (uint64) pt_base) >> PTE$C_SHIFT_SIZE;M entry->pfn$q_pte_index = (entry->pfn$q_pte_index & pte_index_mask) | index; temp = pte_va (va_pte); if (pt_pfn == 0)* entry->pfn$i_pt_pfn = temp->pte$v_pfn; else!z entry->pfn$i_pt_pfn = pt_pfn;!} /* end establish_backpointer */#endif /* ifdef __x86_64 */)#endif /* if __INITIAL_POINTER_SIZE */*#endif /* ifdef __INITIAL_POINTER_SIZE *//*P This macro increments the reference count of the specified PFN database entry. Arguments:@ entry: PFN database entry whose reference count is to be incremented.*//#define incref(entry) ((entry)->pfn$w_refcnt++)/*N This macro determines if a PFN is encumbered by comparing {the page table PFNN field to zero. A zero in this field indicates that the PFN is available for allocation. Arguments:@ entry: PFN database entry to be checked for encumbrance.*/<#define test_backpointer(entry) ((entry)->pfn$i_pt_pfn != 0)#ifdef __NEW_STARLET/*N This routine determines if a PFN is valid by checking if it is either larger@ than MAX_PFN, or within a hole by checking the PFN memory map. Arguments: pfn: PFN to check.*/8#ifdef __x86_64 | /* Verified for x86 port--Drew Mason */ static int valid_pfn (PFN_T pfn){+ extern __RUNCONST uint64 mmg$gq_maxpfn;+ extern int64 mmg$gq_pfn_memory_map [2]; int64 i; PMAP_PQ memory_map;G/* If the supplied PFN exceeds the highest numbered PFN on the system, it's invalid. */ if (pfn > mmg$gq_maxpfn) return 0;H/* If the first quadword in the memory map is zero, the system containsN contiguous physical memory; therefore there's }nothing more to check. */1 if (mmg$gq_pfn_memory_map [0] == 0) return 1;A/* Fetch the pool packet containing the memory map. For systemsD containing discontiguous physical memory, the second quadword ofD mmg$gq_pfn_memory_map points to a pool packet that describes the) PFN ranges on the system. */5 memory_map = (PMAP_PQ) mmg$gq_pfn_memory_map [1];5 for (i = 0; i < mmg$gq_pfn_memory_map [0]; ++i) {0 if ((pfn >= memory_map[i].pmap$iq_start_pfn) &&~/ (pfn < (memory_map[i].pmap$iq_start_pfn + ) memory_map[i].pmap$iq_pfn_count)) &&C (memory_map[i].pmap$v_console | memory_map[i].pmap$v_openvms)) return 1; } return 0;} /* end valid_pfn */$static int valid_pfn_2mb (PFN_T pfn){L/* ghj - to validate large pfns, convert to a 4k pfn and call valid_pfn. */I/* these will need to be beefed up so that they verify ALL the 4k pfns */&/* do exist - not just the first 1. */> return valid_pfn( pfn << (MMG$$C_PFN_TO_PFNDBIDX_2MB+1) );}#static int valid_pfn_1g (PFN_T pfn){= return valid_pfn( pfn << (MMG$$C_PFN_TO_PFNDBIDX_1G+1) );}#else static int valid_pfn (PFN_T pfn){+ extern __RUNCONST uint64 mmg$gq_maxpfn;* extern int mmg$gl_pfn_memory_map [2];0 extern uint64 *mmg$gl_syi_pfn_memory_map_64; int i; PMM64 *memory_map;G/* If the supplied PFN exceeds the highest numbered PFN on the system, it's invalid. */ if (pfn > mmg$gq_maxpfn) return 0;H/* If the first longword in the memory map is zero, the system containsN contiguous physical memory; therefore there's nothing more to check. */1 if (mmg$gl_pfn_memory_map [0] == 0) return 1;A/* Fetch the pool packet containing the memory map. For systemsB containing discontiguous physical memory, the high longword ofN mmg$gl_pfn_memory_map contains a pool packet that describes the PFN ranges on the system. */; memory_map = (PMM64 *)&mmg$gl_syi_pfn_memory_map_64[1];: for (i = 0; i < mmg$gl_syi_pfn_memory_map_64 [0]; ++i)0 if ((pfn >= memory_map[i].pmm64$q_start_pfn) &&. (pfn < memory_map[i].pmm64$q_start_pfn + ( memory_map[i].pmm64$q_pfn_count) &&E (memory_map[i].pmm64$v_console | memory_map[i].pmm64$v_openvms)) return 1; return 0;} /* end valid_pfn */#endif /* __x86_64 else */#endif /* __NEW_STARLET */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif #endif /* __PFN_MACROS_LOADED */wwyZU /* module PMS_ROUTINES.H "X-2"*I* Copyright Digital Equipment Corporation, 1993 All Rights Reserved.O* Unpublished rights reserved under the copyright laws of the United States.* L* The software contained on this media is proprietary to and embodies theP* confidential technology of Digital Equipment Corporation. Possession, use,N* duplication or dissemination of the software and media is authorized onlyL* pursuant to a valid written license from Digital Equipment Corporation.* K* RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.G* Government is subject to restrictions as set forth in SubparagraphJ* (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable.* *++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS systemB* routines that begin with the PMS$ and PMS_STD$ prefixes and have* a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS * compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;*  UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.* * * AUTHOR:* * Leonard S. Szubowicz* * CREATION DATE: 9-Jun-1993* * MODIFICATION HISTORY:*-* X-3 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*1* X-2 JCH703 John C. Hallyburton, Jr. 12-Jan-1995 * Add the rest of the routines.* 0* X-1 LSS0279 Leonard S. Szubowicz 9-Jun-1993@* Initial version containing only those routines commonly used* by device drivers.* *--*/#ifndef __PMS_ROUTINES_LOADED#define __PMS_ROUTINES_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define all types that are used in the following function prototypes.*/#include /*P VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/*#define pms_std$abort_rq PMS_STD$ABORT_RQ(#define pms_std$end_io PMS_STD$END_IO(#define pms_std$end_rq PMS_STD$END_RQ*#define pms_std$start_io PMS_STD$START_IO*#define pms_std$start_rq PMS_STD$START_RQ/*N Function prototypes for system routines with the PMS$ and PMS_STD$ prefix.*/"void pms_std$abort_rq (IRP *irp); void pms_std$end_io (IRP *irp); void pms_std$end_rq (IRP *irp);"void pms_std$start_io (IRP *irp);"void pms_std$start_rq (IRP *irp);R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif"#endif /* __PMS_ROUTINES_LOADED */wwZU// Module POOL_ZONES.H "X-5"//I// Copyright Digital Equipment Corporation, 1996 All Rights Reserved.O// Unpublished rights reserved under the copyright laws of the United States.//L// The software contained on this media is proprietary to and embodies theP// confidential technology of Digital Equipment Corporation. Possession, use,N// duplication or dissemination of the software and media is authorized onlyL// pursuant to a valid written license from Digital Equipment Corporation.//K// RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.G// Government is subject to restrictions as set forth in SubparagraphJ// (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable.////++// // FACILITY://// OpenVMS Executive (LIB_H)// // ABSTRACT://?// This module contains the C function prototypes and structure0// definitions for the 64-bit poolzone routines.// // AUTHOR://// Christian Moser, June 1997//// MODIFIED BY://(// X-5 MLH Mark L. Hopkins 3-AUG-20066// In the _poolzone structure, change the use of the 3// quadword field, not1stpage, to be the list head3// of a singly linked list of empty poolzone_page.-// This allows poolzone purges to be faster.//+// X-4 MAS0695 Mark A. Stiles 2-Jun-2001:// Pad out the poolzone_page header to 128 bytes, so that4// structures within start on cache line boundaries// (currently 64b).//)// X-3 CMOS Christian Moser 20-NOV-19979// Fix declaration of exe$pool_deallocate to use VOID_PQ7// instead of VOID_PPQ, since we pass a pointer to the;// packet. To generate better code, use quadword alignment// by default.//)// X-2 CMOS Christian Moser 22-SEP-1997;// Define cell for empty_page counter, use a fill cell, in// order to change the size.//)// X-1 CMOS Christian Moser 17-JUN-1997// Initial version.//#ifndef __POOL_ZONES_LOADED#define __POOL_ZONES_LOADED 1C#pragma __nostandard // This file uses non-ANSI-Standard features!#pragma __member_alignment __save'#pragma __nomember_alignment __quadwordM#ifdef __INITIAL_POINTER_SIZE // Defined whenever ptr size pragmas supportedW#pragma __required_pointer_size __save // Save the previously-defined required ptr sizeU#pragma __required_pointer_size __long // And set ptr size default to 64-bit pointers#endif//// Common header files//#include far_pointers #include intsO/////////////////////////////////////////////////////////////////////////////////G// NOTE: PALcode quadword queue instructions (like REMQUEQ or INSQUEQ)H// require octaword alignment, hence it is important to align the'// queue links on such boundary!//O/////////////////////////////////////////////////////////////////////////////////4// Structure definition for the poolzone page header//typedef struct _poolzone_page {' struct _poolzone_page *zonepage_flink;' struct _poolzone_page *zonepage_blink; VOID_PQ freequeue_flink; VOID_PQ freequeue_blink; struct _poolzone *zone; uint64 packet_size; uint64 packet_count; uint64 free_count; uint64 hits; uint64 relinks; uint64 reserved1; uint64 reserved2; uint64 reserved3; uint64 reserved4; uint64 reserved5; uint64 reserved6; uint64 first_packet; } POOLZONE_PAGE;///// Structure definition for the poolzone header//typedef struct _poolzone {' struct _poolzone_page *zonepage_flink;' struct _poolzone_page *zonepage_blink; uint64 packet_size; uint64 pages; uint64 max_pages; uint64 free_count; uint64 hits; uint64 misses; uint64 expansions; uint64 failures; #pragma message save$#pragma message disable(UNSTRUCTMEM) union { uint64 not1stpage;' struct _poolzone_page *empty_list; };#pragma message restore uint64 empty_pages; } POOLZONE;//6// Structure definition for the poolzone region header//!typedef struct _poolzone_region { uint64 fill_1; unsigned short int size; unsigned char type; unsigned char subtype; uint32 fill_2; int (*zonepage_alloc_rtn)();" int (*zonepage_dealloc_rtn)(); uint64 zone_count; uint64 fill_3;  uint64 reserved_1; uint64 reserved_2; uint64 reserved_3; uint64 reserved_4; struct _poolzone zone[1]; } POOLZONE_REGION;//*// Poolzone routine prototype declarations//7int exe$poolzone_create ( POOLZONE_REGION *zone_region, int granularity, int init_pages, int max_pages );7int exe$poolzone_expand ( POOLZONE_REGION *zone_region, POOLZONE *zone );6int exe$poolzone_purge ( POOLZONE_REGION *zone_region, POOLZONE *zone, int num_pages );9int exe$poolzone_allocate ( POOLZONE_REGION *zone_region, POOLZONE *zone, VOID_PPQ return_address );-int exe$poolzone_deallocate ( POOLZONE *zone, VOID_PQ packet );5int exe$pool_allocate ( POOLZONE_REGION *zone_region, int size,! VOID_PPQ return_address );+int exe$pool_deallocate ( VOID_PQ packet );$#pragma __member_alignment __restoreN#ifdef __INITIAL_POINTER_SIZE // Defined whenever ptr size pragmas supported]#pragma __required_pointer_size __restore // Restore the previously-defined required ptr size#endif#pragma __standard #endif // __POOL_ZONES_LOADEDww0ZU/* IDENT X-13 */I/************************************************************************I* *I* HPE CONFIDENTIAL. This software is confidential proprietary software *I* licensed by Hewlett Packard Enterprise Development, LP, and is not *I* authorized to be used, duplicated or disclosed to anyone without the *I* prior written permission of HPE. *I* Copyright 2018 Hewlett Packard Enterprise Development, LP *I* *I* VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *I* proprietary software licensed by VMS Software, Inc., and is not *I* authorized to be used, duplicated or disclosed to anyone without *I* the prior written permission of VMS Software, Inc. *I* Copyright 2018 VMS Software, Inc. *I* *J*************************************************************************//**++ * FACILITY:** VMS Executive (LIB)* * ABSTRACT:*E* This header file provides the basic set of C inline functions for * accessing PTEs.* * AUTHOR:** Karen L. Noel*"* CREATION DATE:  28-Mar-2000** MODIFICATION HISTORY:*<* X-13 CEG0918 Clair Grant 25-Sep-20205* Change comment in X-12 *** X-12 CEG0909 Clair Grant 24-Sep-2020** Replace "// comment" style to eliminate+* confusion when compiling /STANDARD=VAXC.*C* X-11 LMN Lisa Nevin 20-Dec-2019@* verify pfns are even on x86 in write_one_pte when the pte is * valid *+* X-10 GHJ Gregory H. Jordan 10-Dec-2018%* Revert hwrpb def due to conflicts.*** X-9 GHJ Gregory H. Jordan 10-Dec-20189* Update various data cells to use __RUNCONST instead of * const. *)* X-8 MJM Michael Moroney 20-Nov-20188* Add $write_one_pte() macro for X86, writes the kernel* PTE pair only.*** X-7 GHJ Gregory H. Jordan 20-Jun-2018:* Change conditionals to use __alpha to avoid the need to* include arch_defs.h.*** X-6 GHJ Gregory H. Jordan 21-May-2018I* Add the $wrpte_pte macro  back here (it had moved to VMS_MACROS)B* and VMS_MACROS was including this module for Alpha. TheF* definitions of a number of extern symbols (mmg$gq_page_size,<* mmg$gq_bwp_mask, etc... then conflicted with definitions <* in other modules which were defining them as ints and not * uint64.*** X-5 GHJ Gregory H. Jordan 21-May-2018@* Change the $write_pte routine to be Alpha specific andC* rename to $write_pte_alpha. VMS_MACROS.H now has aA*  $write_pte macro that will call this routines for Alpha0* and do teh appropriate work for IA64 and X86.*,* X-4 PAJ1567 Paul A. Jacobi 11-Jan-20189* Limit reference of HWRPB$V_VIRBND to Alpha. The field4* is always 0 on IA64 and does not exist on X86_64.*+* X-3 KLN3025 Karen L. Noel 26-Feb-2002* o Port PT space to IA64.C* o Remove inline pragmas. We trust the compiler now.*+* X-2 KLN2200 Karen L. Noel 15-Nov-2000* Fix nested comments.*--*//*? Include any header files we need to make these functions work*/#ifndef __PTE_FUNCTIONS_LOADED #define __PTE_FUNCTIONS_LOADED 1/*B This construct allows SYSBOOT write access to variables that are> run-time constants, but need to be initialized at boot time.*/#ifdef __SYSBOOT#define __RUNCONST#else#define __RUNCONST const#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif#include #include #include #include #include #include  /* *++ * $read_pte - Read a PTE** This function reads a PTE.*T* With VIRBND and SYSPTBR enabled, the level 1 page table page cannot be referenced M* safely in a virtual manner. This function references the level 1 page table* physically when necessary.*-* Input: pte_address - Address of PTE to read?* Output: contents_p - Address to store the contents of the PTE*--*/=static void $read_pte (PTE_PQ pte_address, PTE_PQ contents_p){0 extern PTE mmg$read_l1pte (PTE_PQ pte_address);; extern PTE_PQ __RUNCONST mmg$gq_l1_base[VA$C_VRNX_COUNT];, extern uint64 __RUNCONST mmg$gq_page_size;, extern uint64 __RUNCONST mmg$gq_bwp_width;* extern uint64 __RUNCONST mmg$gq_bwp_mask; exter n HWRPB * exe$gpq_hwrpb; > /* If this system doesn't support system space page tables */> /* or, if this isn't a L1 PTE address, just read the PTE */> /* Note for IA64, hwprb$v_virbnd == 0. The field does not */E /* exist on X86_64. This make the following test always */F /* TRUE on IA64 and X86_64. */ F#if defined (__alpha) /* Verified for x86 port - Gregory H. Jordan */, if ((exe$gpq_hwrpb->hwrpb$v_virbnd == 0) ||M ((uint64)pte_address < (uint64)mmg$gq_l1_base[VA$C_VRNX_SYSTEM]) || X ((uint64)pte_address >= (uint64)mmg$gq_l1_base[VA$C_VRNX_SYSTEM]+mmg$gq_page_size))#else if (1)#endif { *contents_p = *pte_address; return; }; /* Call a macro-32 routine to read the L1PTE physically */+ *contents_p = mmg$read_l1pte(pte_address); return;}?/* $write_pte() macro - use to write a PTE into the page tables *I * For X86, use the global routine mmg$write_pte_x86 in mmg_routines.c.; * For  IA64, just write the PTE into the provide address.? * For Alpha, use $write_pte_alpha defined in pte_functions.h */#if defined(__x86_64)D #define $write_pte( vapte, pte ) mmg$write_pte_x86( vapte, pte )F#elif defined (__ia64) /* Verified for x86 port - Gregory H. Jordan */0 #define $write_pte( vapte, pte) *vapte = pteH#elif defined (__alpha) /* Verified for x86 port - Gregory H. Jordan */@ #define $write_pte( vapte, pte) $write_pte_alpha(vapte, pte)#else/ #error Need architecture specific work here#endif/*++++* $write_pte_alpha - Write to a PTE (Alpha)*X* This function writes to a PTE on Alpha. The routine is called by the $write_pte macro* defined in VMS_MACROS.H.*T* With VIRBND and SYSPTBR enabled, the level 1 page table page cannot be referenced M* safely in a virtual manner. This function references the level 1 page table* physically when necessary.*.* Input: pte_address - Address of PTE to write7* contents - The contents to write to the PTE**---*/F#if defined (__alpha) /* Verified for x86 port - Gregory H. Jordan */?static void $write_pte_alpha (PTE_PQ pte_address, PTE contents){B extern uint64 mmg$write_l1pte (PTE_PQ pte_address, PTE contents);: extern PTE_PQ __RUNCONST mmg$gq_l1_base[VA$C_VRNX_COUNT];, extern uint64 __RUNCONST mmg$gq_page_size;, extern uint64 __RUNCONST mmg$gq_bwp_width;+ extern uint64 __RUNCONST mmg$gq_bwp_mask; extern HWRPB * exe$gpq_hwrpb; > /* If this system doesn't support system space page tables */> /* or, if this isn't a L1 PTE address, just write the PTE */> /* Note for IA64, hwprb$v_virbnd == 0. The field does not */E /* exist on X86_64. This make the following test always */E /* TRUE on IA64 and X86_64. */, if ((exe$gpq_hwrpb->hwrpb$v_virbnd == 0) ||M ((uint64)pte_address < (uint64)mmg$gq_l1_base[VA$C_VRNX_SYSTEM]) || X ((uint64)pte_address >= (uint64)mmg$gq_l1_base[VA$C_VRNX_SYSTEM]+mmg$gq_page_size)) {" *pte_address = contents; return; }< /* Call a macro-32 routine to write the L1PTE physically */( mmg$write_l1pte(pte_address,contents);  return;}#endifJ/* $write_one_pte() macro - use to write single PTE into kernel page table *C * For X86, write the single PTE pair, incrementing PFN if valid.9 * For IA64 and Alpha, this is identical to $write_pte. */C#if defined(__x86_64) /* Verified for x86 port - Michael Moroney */)#define $wri te_one_pte( vapte, pte ) { \ PTE pte2 = (pte); \ PTE_PQ va2 = (vapte); \ if (pte2.pte$v_valid) { \) if (pte2.pte$v_pfn_4k & 1ull) { \* uint64 ra = __RETURN_ADDRESS(); \ exe$kprintf("\n Expected an even PFN but received odd PFN: %08X.%08X RA: %08X.%08X \n", pte2.pte$v_pfn_4k >> 32, pte2.pte$v_pfn_4k & 0XFFFFFFFF, ra >> 32, ra & 0xFFFFFFFF); \+ bug_check(INCONMMGST, FATAL, COLD); \ } \) *va2++ = pte2;  \) pte2.pte$v_pfn_4k++; \ } \ else { \ *va2++ = pte2; \ } \ *va2 = pte2; \}F#elif defined (__ia64) /* Verified for x86 port - Gregory H. Jordan */4 #define $write_one_pte( vapte, pte) *vapte = pteH#elif defined (__alpha) /* Verified for x86 port - Gregory H. Jordan */D #define $write_one_pte( vapte, pte) $write_pte_alpha(vapte, pte)#else/ #error Need architecture specific work here#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif##endif /* __PTE_FUNCTIONS_LOADED */wwPdZU#ifndef __RAD_MACROS_LOADED#define __RAD_MACROS_LOADED 1O/* ************************************************************************* */O/* * * */O/* * HPE CONFIDENTIAL. This software is confidential proprietary software * */O/* * licensed by Hewlett Packard Enterprise Development, LP, and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without the * */O/* * prior written permission of HPE. * */O/* * Copyright 2018 Hewlett Packard Enterprise Development, LP * */O/* * * */O/* * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential * */O/* * proprietary software licensed by VMS Software, Inc., and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without * */O/* * the prior written permission of VMS Software, Inc. * */O/* * Copyright 2018 VMS Software, Inc. * */O/* * * */O/* ************************************************************************* *//** Version X-16*++ * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:*M* This header file provides the Resource Affinity Domain (RAD) macros for C.* * AUTHOR:** Karen Noel*"* CREATION DATE: 09-Dec-1999** MODIFICATION HISTORY:*(* X-16 CEG0480 Clair Grant 04-May-2018!* Verified conditionals for x86.* Updated copyright to VSI.*)* X-15 GHJ Gregory H. Jordan 14-Oct-20088* Change the parameter passed to both incr_zeroed_count%* and decr_zeroed_count to be PFN_T.* 9* Add code in decr_zero_count for the future possibility3* of setting a bit requesting zeroing assistance -7* the page_zeroing routine in SYS_SCHED for more info.*)* X-14 GHJ Gregory H. Jordan 12-Sep-20088* Add support for per RAD page zeroing. Two new macros8* have been added for incrementing and decrementing the9* zero page counts - as there is now a system wide count* and a RAD specific count.*)* X-13 GHJ Gregory H. Jordan 17-Apr-20085* Change $rad_to_cpu_mask to return a quadword mask.*)* X-12 KLN3448 Karen L. Noel 5-Mar-20043* Use 64-bit PFN data cells for 50-bit PA project.*** X-11 KLN3418 Karen L. Noel 14-Jan-2004;* Include mmgdef.h since MMG$ symbols are referenced here.*** X-10 KLN3415 Karen L. Noel 13-Jan-2004* Add $GET_PAGE_COLOR macro.*(* X-9 CMOS Christian Moser 30-OCT-2001?* For Marvel we cannot simply shift the PFN to find the Rad id=* and for a given RAD there might not be a single PFN range.?* Change relevant macros to call a platform specific routines,* if necessary. *(* X-8 CMOS Christian Moser 5-OCT-2001<* define exe$gl_radid and typecast rad parameter when doing* a comparison.*(* X-7 CMOS Christian Moser 1-OCT-20015* Update $GET_CURRENT_RAD macro to use EXE$GL_RADID.*&* X-5,6 WBF Burns Fisher 06-Mar-2000A* Fix build break and use new mask in RIH instead of calculation*$* X-4 WBF Burns Fisher 01-Mar-2000* Add $rad_to_cpu_mask*)* X-3 KLN2134 Karen L. Noel 10-Feb-2000#* Add $pfn_to_rad and $cpu_to_rad.*)* X-2 KLN2125 Karen L. Noel 13-Jan-2000* Add $get_current_rad macro*--*/R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*** MODULE RAD_MACROS ***//*= Include any header files we need to make these macros work.*/#include #include #include #include #include  /**&* $cpu_to_rad - Convert CPU ID to RAD.*@* This macro returns the RAD corresponding to the specified CPU.** Input: CPU - CPU ID(* Output: RAD - Resource Affinity Domain**--*/#define $cpu_to_rad(cpu,rad)\Y{  \R rad = 0; \R if (exe$gpq_rad_info_header) \ { \B if ( exe$gpq_rad_info_header->rih$l_cpu_shift_value == -1 ) \C rad = exe$gpq_rad_info_header->rih$l_cpu_to_rad ( (cpu) ); \ else \O rad = ((cpu) >> exe$gpq_rad_info_header->rih$l_cpu_shift_value); \ } \} /**#* $pfn_to_rad - Convert PFN to RAD.*@* This macro returns the RAD corresponding to the specified PFN.* * Input: PFN - Page Frame Number(* Output: RAD - Resource Affinity Domain**--*/#define $pfn_to_rad(pfn,rad)\Z{ \/ extern const uint64 mmg$gq_vpn_to_va; \ rad = 0; \- if (exe$gpq_rad_info_header) { \E if ( exe$gpq_rad_info_header->rih$l_pfn_ shift_value == -1 ) \] rad = exe$gpq_rad_info_header->rih$l_pa_to_rad ( (uint64)(pfn) << mmg$gq_vpn_to_va ); \ else \U rad = ((uint64)(pfn) >> exe$gpq_rad_info_header->rih$l_pfn_shift_value); \ } \} /**/* $get_current_rad - Get the current CPU's RAD.*B* Macro to retrieve the current Rad id. In a non-NUMA environment,C* the global cell EXE$GL_RADID is initialized to 0, which is alwaysA* true. In a NUMA environment, the cell is initi alized to -1, andC* only if replication is enabled, the cell will hold the true valueB* which is fetched from per-RAD local memory. If we get a -1 back,@* we need to do it the hard way, by converting the CPU id into a * Rad id.***/Y#define $get_current_rad(rad) \Y{ \!extern int exe$gl_radid; \ rad = exe$gl_radid; \ if ( (int)rad < 0 ) \ { \R rad = 0; \R if (exe$gpq_rad_info_header) \R { \O rad = __PAL_MFPR_WHAMI(); \D if ( exe$gpq_rad_info_header->rih$l_cpu_shift_value == -1 ) \D rad = exe$gpq_rad_info_header->rih$l_cpu_to_rad ( (rad) ); \ else \Q rad = ((rad) >> exe$gpq_rad_info_header->rih$l_cpu_shift_value); \R } \ } \} /**0* $get_next_color - Get the next "random" color.*M* This macro works with either type of page coloring, VPN based or RAD based.D* It will skip those page colors that are not present in the system.*.* Output: color - the next random color to use***/'#define $get_next_color(color) \Y{ \Yextern uint32 mmg$gl_next_color_index; \Yextern uint32 mmg$gl_present_color_mask; \)extern uint32 mmg$gl_color_count; \Y \. if (mmg$gl_present_color_mask == 0) \U color = 0; \Y else \Y { \ color = -1; \R while ((int)color == -1) \ { \K color = mmg$gl_next_color_index; \K if (((1 << color) & mmg$gl_present_color_mask) == 0) \K { \D color = -1; \D mmg$gl_next_color_index++; \H if (mmg$gl_next_color_index >= mmg$gl_color_count) \D mmg$gl_next_color_index = 0; \K } \R }  \R mmg$gl_next_color_index++; \R if (mmg$gl_next_color_index >= mmg$gl_color_count) \H mmg$gl_next_color_index = 0; \ } \} /**5* $get_base_rad - Get the base operating system RAD. *:* This macro will return 0 if there is no RAD info header.*F* Output: rad - Resource Affinity Domain for the base op erating system**--*/##define $get_base_rad(rad) \Y{ \6 extern RIH_PQ const exe$gpq_rad_info_header; \Y \Y if (exe$gpq_rad_info_header == 0) \9 rad=0; \Y else  \R rad = exe$gpq_rad_info_header->rih$l_base_rad; \X}  /**G* $rad_to_pfn_range - Convert the RAD to a range of PFNs within the RAD* (* Input: rad - Resource Affinity Domain%* range_index - request range index*;* Output: low_pfn - the lowest PFN within the specified RAD7* high_pfn - the highest PFN within the specif ied RAD*T* Some RADs may contain multiple PFN ranges. Additional PFN ranges can be obtainedV* by calling by incrementing the range index for the same rad. Should the range_indexU* exceed the number of PFN ranges, then both low_pfn and high_pfn will be returned as* zero.**/"#pragma inline ($rad_to_pfn_range)Zstatic void $rad_to_pfn_range(int rad,uint64 range_index,PFN_T *low_pfn, PFN_T *high_pfn) {/ extern RIH_PQ const exe$gpq_rad_info_header; extern const uint64 mmg$gq_min_node_pfn, mmg$gq_max_node_pfn; *low_pfn = 0; *high_pfn = 0; // U // For non-rad systems, return the nodes min and max pfn values. As there is onlyQ // a single range of pfns, return with the low and high pfn set to zero if the+ // range index is anything other than 0. //$ if (exe$gpq_rad_info_header == 0) { if (range_index != 0) return; *low_pfn = mmg$gq_min_node_pfn;! *high_pfn = mmg$gq_max_node_pfn; return; }< if (exe$gpq_r ad_info_header->rih$l_pfn_shift_value == -1) {& extern const uint64 mmg$gq_vpn_to_va; uint64 low_pa, high_pa;X#pragma __required_pointer_size long /* And set ptr size default to 32-bit pointers */ uint64 *pa_range;[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */A#if ALPHA /* Verified for x86 port - Clair Grant */K if (range_index != 0) return; // never more than 1 range of pfns on AlphaJ exe$gpq_rad_info_header->rih$ l_rad_to_pa_range( rad, &low_pa, &high_pa );' *low_pfn = low_pa >> mmg$gq_vpn_to_va;) *high_pfn = high_pa >> mmg$gq_vpn_to_va;#else//X// On other systems, it is possible to have systems with more than 1 disjoing pfn range.R// The rad_to_pa_range call will return an array of quadwords. The first containsR// a count of the pa ranges and following are pairs of quadwords with the low and "// high PA address for the ranges.//B exe$gpq_rad_info_header->rih$l_rad_to_pa_range( rad, &pa_range );( if (range_index >= pa_range[0]) return;* pa_range = &pa_range[(range_index*2)+1];. *low_pfn = pa_range[0] >> mmg$gq_vpn_to_va;. *high_pfn = pa_range[1] >> mmg$gq_vpn_to_va;#endif } else { if (range_index != 0) return;G *low_pfn = rad << exe$gpq_rad_info_header->rih$l_pfn_shift_value;G *high_pfn = (rad+1) << exe$gpq_rad_info_header->rih$l_pfn_shift_value; *high_pfn--; }} /**O* Macro to get a mask of CPUs from a RAD number. RAD Support has an assumption* of a max CPU id of 63.** Use:* $rad_to_cpu_mask rad,cpu_mask** WHERE:* rad - Specified RAD!* cpu_mask- Returned mask of CPUs*/(#define $rad_to_cpu_mask(rad,cpu_mask) \{ \# extern uint64 smp$gl_cpuconf; \' if (exe$gpq_rad_info_header != 0) \" if (rad <= RIH$C_MAX_RAD_COUNT) \X cpu_mask = exe$gpq_rad_info_header->rih$r_cpu_array[rad].rih$q_cpu_mask_array[0]; \ else \ cpu_mask = 0; \ else \ if (rad==0) \! cpu_mask = smp$gl_cpuconf; \ else \ cpu_mask == 0; \} /**/* Function to convert vpn and rad to page color** Use:,* color = $get_page_color (flags, vpn, rad);** WHERE:2* flags - MMG$M_COLOR_MUST or MMG$M_COLOR_RANDOM* vpn - virtual page number* rad - specified RAD*/Estatic uint32 $get_page_color (uint32 flags, uint64 vpn, uint32 rad) {6 extern RIH_PQ const exe$gpq_rad_info_header; $ extern uint32 mmg$gl_color_mask;- extern uint32 mmg$gl_color_count;  uint32 color=0; RIH_PQ rih; // Get rad info header" rih = exe$gpq_rad_info_header;  // Return a random color( if ((flags & MMG$M_COLOR_RANDOM) || ' (rih && ((int)rad == MMG$K_NO_RAD))) { $get_next_color(color);$ color = color & ~mmg$gl_color_mask; return (color); } // Return a rad based color if (rih) {! if ((int)rad == MMG$K_BASE_RAD) color = rih->rih$l_base_rad;  else color = rad;$ color = color & ~mmg$gl_color_mask; return (color); }  // Return a VPN based color: if (mmg$gl_color_count && ((int)vpn != MMG$K_NO_VPN)) color = vpn;' color = color & ~mmg$gl_color_mask; return (color);}/* DECR_ZEROED_LIST_COUNTP This macro will decrement the appropriate zeroed list count. This maintainsA the count for the overall system and for the appropriate RAD.*/'#pragma inline (decr_zeroed_list_count)1static void decr_zeroed_list_count( PFN_T pfn ) { * extern RAD_PQ exe$gq_rad_data_array[];5 extern volatile uint64 mmg$gq_zeroed_list_count; int rad;  uint32 rad_bit; RAD_PQ rad_data;  int high_limit; 0 extern RIH_PQ const exe$gpq_rad_info_header;' extern int mmg$gl_zero_list_hi_lim; $pfn_to_rad( pfn, rad ); + rad_data = exe$gq_rad_data_array[rad]; ) rad_data->rad$l_zeroed_list_count--; mmg$gq_zeroed_list_count--; #ifdef MMG$ZERO_ASSIST if (exe$gpq_rad_info_header) {2 if (rad_data->rad$l_zero_list_hi_lim != 0)3 high_limit = rad_data->rad$l_zero_list_hi_lim; else* high_limit = mmg$gl_zero_list_hi_lim; rad_bit = 1<rad$l_zeroed_list_count < (high_limit / 2 ))K if ((exe$gpq_rad_info_header->rih$l_page_zero_assist && rad_bit) == 0)> exe$gpq_rad_info_header->rih$l_page_zero_assist |= rad_bit;  }#endif}'#pragma inline (incr_zeroed_list_count)1static void incr_zeroed_list_count( PFN_T pfn ) { * extern RAD_PQ exe$gq_rad_data_array[];5 extern volatile uint64 mmg$gq_zeroed_list_count;0 extern RIH_PQ const exe$gpq_rad_info_header; int rad;  RAD_PQ rad_data;  $pfn_to_rad( pfn, rad ); + rad_data = exe$gq_rad_data_array[rad]; ; if (rad_data != 0) rad_data->rad$l_zeroed_list_count++;" mmg$gq_zeroed_list_count++; } R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif #endif /* __RAD_MACROS_LOADED */wwZU/** MODULE: SCH_ROUTINES.H** VERSION: X-17*I* Copyright Digital Equipment Corporation, 1993 All Rights Reserved.O* Unpublished rights reserved under the copyright laws of the United States.* L* The software contained on this media is proprietary to and embodies theP* confidential technology of Digital Equipment Corporation. Possession, use,N* duplication or dissemination of the software and media is authorized onlyL* pursuant to a valid written license from Digital Equipment Corporation.* K* RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.G* Government is subject to restrictions as set forth in SubparagraphJ* (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable.* *++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS systemB* routines that begin with the SCH$ and SCH_STD$ prefixes and have* a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS _IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;*  UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.*/* 6. Mixed pointer sizes within one argumentF* If a 64-bit pointer is being passed by reference, the reference to ?* the pointer should also be 64 bits wide to avoid confusion. * For example:* * PTE_PPQ va_pte_p;* VOID_PPQ start_va_p; ** should be used instead of:** PTE_PQ *va_pte_p;* VOID_PQ *start_va_p;* * * AUTHOR:* * Leonard S. Szubowicz* * CREATION DATE: 9-Jun-1993* * MODIFICATION HISTORY:*&* X-17 ER Eric Rasmussen 27-Oct-20056* NMSP$CBB - Changed affinity routine interfaces from%* bitmasks to bitmaps (a.k.a. CBBs):* sch$change_affinity()* sch$clear_affinity()* sch$compute_runnable_mask()* sch$set_affinity_bindings() * sch$clear_affinity_bindings()*%* Add sch$update_affinity_bindings()*(* X-16 JRK398 Jim Kauffman 20-Apr-20046* Fix pointer target sizes for hard affinity routines* Add 64-bit affinity routines*** X-15 KLN3257 Karen L. Noel 10-Apr-20032* Declare ASN routines to accept 64-bit pointers.*%* X-14 WBF Burns Fisher 23-Oct-20025* Add sch_std$report_event and sch_std$thread_ravail*+* X-13 KLN3043 Karen L. Noel 20-Mar-20020* Include freddef.h to resolves new references.*** X-12 KLN3040 Karen L. Noel 14-Mar-2002-* Add  sch$save_asn and sch$get_asn for IA64.*%* X-11 WBF Burns Fisher 21-Aug-2001;* Define first arg of sch$wait_proc as a WQH * rather than=* a KTB * to avoid problems of passing the wrong indirection* level from a wait queue.*-* X-10 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*+* X-9 PKMW386 Paul K. M. Weiss 8-Jan-1998:* Fix sch_std$qast to correctly specify the PCB parameter%* as an output pointer to a pointer.*'* X-8 JRK387 Jim Kauffman 4-Sep-1997(* Add SCH$ACQUIRE_IMPLICIT_AFFINITY and * SCH$RELEASE_IMPLICIT_AFFINITY*,* X-7 NYK638 Nitin Y. Karkhanis 17-Jul-19960* Add function prototypes for SCH$WAIT_PROC and* SCH$WAIT_KERNEL_MODE.*0* X-6 LSS0356 Leonard S. Szubowicz 6-Sep-1995=* Include ints.h to define types used by various prototypes.=* Also, fix prototype for SCH_STD$WAKE: PCB pointer returned* by reference.*'* X-5 JRK369 Jim Kauffman 24-May-1995%* Fix SCH$CLEAR_CAPABILITY prototype*0* X-4 LSS0348 Leonard S. Szubowicz 13-Jun-1995>* 64-bits: Add function prototypes for SCH$RESOURCE_WAIT[_PS]*'* X-3 JRK369 Jim Kauffman 23-May-19950* Add assorted affinity and capability routines*)* X-2 KLN1422 Karen L. Noel 27-Mar-1995-* Replace sch_std$clref with sch_std$clrefr.*0* X-1 LSS0279 Leonard S. Szubowicz 9-Jun-1993@* Initial version containing only those routines commonly used* by device drivers.* *--*/ #ifndef __SCH_ROUTINES_LOADED#define __SCH_ROUTINES_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define all types that are used in the following function prototypes.*/#include #include #include #include #include #include #include #include #include /*P VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/)#define sch$add_cpu_cap SCH$ADD_CPU_CAP0#define sch$change_affinity  SCH$CHANGE_AFFINITY4#define sch$change_capability SCH$CHANGE_CAPABILITY;#define sch$change_cpu_capability SCH$CHANGE_CPU_CAPABILITY.#define sch$clear_affinity SCH$CLEAR_AFFINITY?#define sch$clear_affinity_bindings SCH$CLEAR_AFFINITY_BINDINGS;#define sch$compute_runnable_mask SCH$COMPUTE_RUNNABLE_MASK2#define sch$clear_capability SCH$CLEAR_CAPABILITY2#define sch$wait_kernel_mode SCH$WAIT_KERNEL_MODE%#define sch$wait_proc SCH$WAIT_PROC.#define sch$remove_cpu_cap SCH$REMOVE_CPU_CAP, #define sch$resource_wait SCH$RESOURCE_WAIT2#define sch$resource_wait_ps SCH$RESOURCE_WAIT_PS8#define sch$resource_wait_setup SCH$RESOURCE_WAIT_SETUP*#define sch$set_affinity SCH$SET_AFFINITY;#define sch$set_affinity_bindings SCH$SET_AFFINITY_BINDINGS.#define sch$set_capability SCH$SET_CAPABILITYC#define sch$acquire_implicit_affinity SCH$ACQUIRE_IMPLICIT_AFFINITYC#define sch$release_implicit_affinity SCH$RELEASE_IMPLICIT_AFFINITYA#define sch$update_affinity_bindings SCH$UPDATE_AFFINITY _BINDINGS'#define sch_std$clrefr SCH_STD$CLREFR)#define sch_std$iolockr SCH_STD$IOLOCKR)#define sch_std$iolockw SCH_STD$IOLOCKW*#define sch_std$iounlock SCH_STD$IOUNLOCK%#define sch_std$lockr SCH_STD$LOCKR.#define sch_std$lockr_quad SCH_STD$LOCKR_QUAD,#define sch_std$lockrexec SCH_STD$LOCKREXEC6#define sch_std$lockrexec_quad SCH_STD$LOCKREXEC_QUAD%#define sch_std$lockw SCH_STD$LOCKW,#define sch_std$lockwexec SCH_STD$LOCKWEXEC6#define sch_std$lockwexec_quad SCH_STD$LO CKWEXEC_QUAD0#define sch_std$lockwnowait SCH_STD$LOCKWNOWAIT9#define sch_std$lockwnowait_quad SCH_STD$LOCKWNOWAIT_QUAD'#define sch_std$postef SCH_STD$POSTEF##define sch_std$qast SCH_STD$QAST'#define sch_std$ravail SCH_STD$RAVAIL4#define sch_std$thread_ravail SCH_STD$THREAD_RAVAIL'#define sch_std$unlock SCH_STD$UNLOCK.#define sch_std$unlockexec SCH_STD$UNLOCKEXEC8#define sch_std$unlockexec_quad SCH_STD$UNLOCKEXEC_QUAD##define sch_std$wake SCH_STD$WAKE##define sch$save_asn  SCH$SAVE_ASN!#define sch$get_asn SCH$GET_ASN/*N Function prototypes for system routines with the SCH$ and SCH_STD$ prefix.*/Jint sch$add_cpu_cap(uint32 cpu_id, uint32 mask, UINT32_PQ prev_mask_p);hint sch$change_affinity (CBB_PQ aff_bitmap, KTB *ktb, uint64 flags, CBB_PQ old_bitmap, int add_flag);wint sch$change_capability (KTB *ktb, uint64 new_caps, uint32 cpuid, uint64 flags, UINT64_PQ old_mask, int add_flag);cint sch$change_cpu_capability (uint32 cpuid, uint64 cap_mask, UINT64_PQ old_mask, int add_flag);Zint sch$clear_affinity(uint32 cpu_mask, KTB *ktb, uint32 flags, UINT32_PQ prev_mask_p);8void sch$clear_affinity_bindings(CBB_PQ cpuid_bitmap);gint sch$clear_capability(KTB *ktb, uint32 mask, uint32 cpu_id, uint32 flags, UINT32_PQ prev_mask_p);aint sch$compute_runnable_mask (uint64 capabilities, CBB_PQ affinities, CBB_PQ run_bitmap_ptr);#void sch$wait_kernel_mode (void);1void sch$wait_proc (WQH *wait_queue, KTB *ktb);<void sch$resource_wait (KTB *const ktb, const uint32 rsn);Pvoid sch$resource_wait_ps (KTB *const ktb,const uint32 rsn, const uint32 psl);Bint sch$resource_wait_setup (KTB *const ktb, const uint32 rsn);Mint sch$remove_cpu_cap(uint32 cpu_id, uint32 mask, UINT32_PQ prev_mask_p);Xint sch$set_affinity(uint32 cpu_mask, KTB *ktb, uint32 flags, UINT32_PQ prev_mask_p);6void sch$set_affinity_bindings(CBB_PQ cpuid_bitmap);eint sch$set_capability(KTB *ktb, uint32 mask, uint32 cpu_id, uint32 flags, UINT 32_PQ prev_mask_p);Iint sch$acquire_implicit_affinity(KTB *ktb, int obsolete, int cpu_id);/int sch$release_implicit_affinity(KTB *ktb);Qvoid sch$update_affinity_bindings(KTB *ktb, CBB_PQ cur_affs, CBB_PQ perm_affs);*int sch_std$clrefr (int efn, PCB *pcb);"MUTEX *sch_std$iolockr (PCB *pcb);"MUTEX *sch_std$iolockw (PCB *pcb);#void sch_std$iounlock (PCB *pcb);*void sch_std$lockr (MTX *mtx, PCB *pcb);3void sch_std$lockr_quad (MUTEX *mutex, PCB *pcb);$int sch_std$lockr exec (MTX *mtx);-int sch_std$lockrexec_quad (MUTEX *mutex);*void sch_std$lockw (MTX *mtx, PCB *pcb);$int sch_std$lockwexec (MTX *mtx);-int sch_std$lockwexec_quad (MUTEX *mutex);0int sch_std$lockwnowait (MTX *mtx, PCB *pcb);9int sch_std$lockwnowait_quad (MUTEX *mutex, PCB *pcb);Cint sch_std$postef (int ipid, int incpri, int efn, PCB **pcb_p);8int sch_std$qast (int incpri, ACB *acb, PCB **pcb_p); void sch_std$ravail (int rsn);Cvoid sch_std$report_event(int event, int prioIncrClass, KTB *ktb);4void sch_std$thread_ravail (int rsn,int threadno);+void sch_std$unlock (MTX *mtx, PCB *pcb);%void sch_std$unlockexec (MTX *mtx);.void sch_std$unlockexec_quad (MUTEX *mutex);,int sch_std$wake (int ipid, PCB **pcb_p);R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */"#pragma __required_pointer_size 64#endifBvoid sch$save_asn (PCB * old_pcb, FRED * old_fred, CPU * cpudb);bint sch$get_asn (PCB * new_pcb, FRED  * new_fred, CPU * cpudb, PCB * old_pcb, FRED * old_fred);R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif"#endif /* __SCH_ROUTINES_LOADED */ww'ZU/* module SCS_ROUTINES.H "X-6" *K * Copyright Digital Equipment Corporation, 1999; All Rights Reserved.P * Unpublished rights reserved under the copyright laws of the United Sta tes. * M * The software contained on this media is proprietary to and embodies theQ * confidential technology of Digital Equipment Corporation. Possession, use,O * duplication or dissemination of the software and media is authorized onlyM * pursuant to a valid written license from Digital Equipment Corporation. * L * RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.H * Government is subject to restrictions as set forth in SubparagraphK * (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable. *  *++ *  * FACILITY: * * VMS Executive (LIB_H) *  * ABSTRACT: * D * This module contains the C function prototypes for the VMS systemM * routines that begin with the SCS_STD$, and have a standard call interface. * * NOTE: *? * The conventions used in these function prototypes are: * * 1. CaseL * This header file supports invoking the routines by either using allJ * l owercase or all uppercase names for the system routines. EitherH * naming convention works even in the presence of the /NAME=AS_IS * compiler switch. * * 2. Integer sizeK * The generic "int" type is used where it doesn't matter whether theL * integer is 32 or 64 bits wide. Thus "int" is the returned value ofK * most functions and is the type for most integers passed by value. J * However, an unambiguous integer type, e.g. int32, is used for anyJ  * integer that is passed by reference. Also, int64 is used for anyL * integer that is expected to be 64 bits wide even if it is passed by * value. * * 3. TypesQ * The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. > * The definitions of all types used are included below. * * 4. Parameter namesO * Parameter names are used in the prototypes. Although they are ignoredL * by the compiler they do provide useful documentation. For example: *A * void ioc_std$reqcom (int iost1, int iost2, UCB *ucb); *8 * is used instead of the functionally equivalent: *2 * void ioc_std$reqcom (int, int, UCB *); *' * 5. Parameters passed by referenceO * The parameter name includes the "_p" suffix if the parameter is passedP * by reference unless the parameter type implies that it is always passed@ * by reference. For example, there is no "_p" suffix in: * * UCB *ucb; * int32 iosb[2]; *N * since structures and arrays are always passed by reference. However: * * int32 *outlen_p; * UCB **new_ucb_p; *L * include the suffix to denote that outlen_p is a pointer to a 32 bitM * integer, and to denote that new_ucb_p is a pointer to a pointer to a * UCB structure. *0 * 6. Mixed pointer sizes within one argumentG * If a 64-bit pointer is being passed by reference, the reference to @ * the pointer should also be 64 bits wide to avoid confusion.  * For example: *  * PTE_PPQ va_pte_p; * VOID_PPQ start_va_p;  * * should be used instead of: * * PTE_PQ *va_pte_p; * VOID_PQ *start_va_p; *  * * Author: * / * James M. Blue Creation Date: 22-Mar-1999 *  * Modification History: *) * X-6 JMB185 James M. Blue 5-Oct-1999 * Missed a few when doing X-5! *) * X-5 JMB171 James M. Blue 16-Aug-1999B * Remove the CDT argum ent from the SCS_STD$_* send, receive, andA * map routine calls where the CDT used by the underlying SCS$_*B * routine is acquired from a different source, such as the CDRP. *) * X-4 JMB152 James M. Blue 3-Aug-1999= * Modify the SCS_STD$LKP* routines to be void output and to8 * pass the action parameter as void to the void return< * action routine. Eliminated the unnecessary PDT argument? * in the SCS_STD$LKP_MSGWAIT prototype. The PDT is available# * via the CDT argument if needed. *) * X-3 JMB129 James M. Blue 27-Jul-1999G * Correct the argument prototype in SCS$CONNECT for the SYSAP routineB * called by FAST_RECVMSG_REQUEST. The CDRP had not been handledK * correctly between the SYSAP and the caller of SCS$FAST_RECVMSG_REQUEST.? * Add CDT as output argument to SCS_STD$FAST_RECVMSG_REQUEST. *) * X-2 JMB104 James M. Blue 6-Apr-1999B * Add in prototypes for SCS_STD$REQUEST_DATA, SCS_STD$SEND_DATA, * and SCS_STD$SEND_DATA_WMSG. *) * X-1 JMB085 James M. Blue 22-Mar-1999 * Initial version. *-- */#ifndef __SCS_ROUTINES_LOADED#define __SCS_ROUTINES_LOADED 1#ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif/*H * Define all types that are used in the following function prototypes. */#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /*A * VMS system routine entry points are defined externally usingB * uppercase names. The following macros allow the usage of theB * lowercase versions of these names even in the presence of the! * /NAME=AS_IS compiler sw itch. */6#define scs_std$accept SCS_STD$ACCEPT7#define scs_std$allocdg SCS_STD$ALLOCDG<#define scs_std$alloc_msgbuf SCS_STD$ALLOC_MSGBUF;#define scs_std$alloc_rspid SCS_STD$ALLOC_RSPID:#define scs_std$cancel_mbx SCS_STD$CANCEL_MBX;#define scs_std$cancel_wait SCS_STD$CANCEL_WAIT?#define scs_std$change_affinity SCS_STD$CHANGE_AFFINITY<#define scs_std$check_vc_tmo SCS_STD$CHECK_VC_TMO=#d efine scs_std$cleanup_rbuns SCS_STD$CLEANUP_RBUNS:#define scs_std$config_pth SCS_STD$CONFIG_PTH:#define scs_std$config_sys SCS_STD$CONFIG_SYS7#define scs_std$connect SCS_STD$CONNECT<#define scs_std$credit_avail SCS_STD$CREDIT_AVAIL9#define scs_std$deallocdg SCS_STD$DEALLOCDG:#define scs_std$deallocmsg SCS_STD$DEALLOCMSG9#define scs_std$deall_cdt SCS_STD$DEALL_CDT;#define scs_std$deall_rspid SCS_STD$DEALL_RSPID:#define scs_std$disconnect SCS_STD$DISCONNECTD#define scs_std$fast_recvmsg_chk_res SCS_STD$FAST_RECVMSG_CHK_RES?#define scs_std$fast_recvmsg_pm SCS_STD$FAST_RECVMSG_PMD#define scs_std$fast_recvmsg_request SCS_STD$FAST_RECVMSG_REQUESTG#define scs_std$fast_sendmsg_ass_res_pm SCS_STD$FAST_SENDMSG_ASS_RES_PM?#define scs_std$fast_sendmsg_pm SCS_STD$FAST_SENDMSG_PMD#define scs_std$fast_sendmsg_request SCS_STD$FAST_SENDMSG_R EQUEST7#define scs_std$find_bd SCS_STD$FIND_BD9#define scs_std$find_rdte SCS_STD$FIND_RDTE9#define scs_std$init_bdlt SCS_STD$INIT_BDLT>#define scs_std$initialize_pdt SCS_STD$INITIALIZE_PDT6#define scs_std$listen SCS_STD$LISTEN;#define scs_std$lkp_msgwait SCS_STD$LKP_MSGWAIT:#define scs_std$lkp_pb_pdt SCS_STD$LKP_PB_PDT;#define scs_std$lkp_rdtcdrp SCS_STD$LKP_RDTCDRP;#define scs_std$ lkp_rdtwait SCS_STD$LKP_RDTWAIT3#define scs_std$map SCS_STD$MAP6#define scs_std$mreset SCS_STD$MRESET=#define scs_std$msg_buf_avail SCS_STD$MSG_BUF_AVAIL6#define scs_std$mstart SCS_STD$MSTART6#define scs_std$new_pb SCS_STD$NEW_PB6#define scs_std$new_sb SCS_STD$NEW_SB<#define scs_std$notify_sysap SCS_STD$NOTIFY_SYSAP8#define scs_std$poll_mbx SCS_STD$POLL_MBX 9#define scs_std$poll_mode SCS_STD$POLL_MODE9#define scs_std$poll_proc SCS_STD$POLL_PROC>#define scs_std$port_init_done SCS_STD$PORT_INIT_DONE7#define scs_std$queuedg SCS_STD$QUEUEDG9#define scs_std$queuemdgs SCS_STD$QUEUEMDGS9#define scs_std$rchmsgbuf SCS_STD$RCHMSGBUF9#define scs_std$rclmsgbuf SCS_STD$RCLMSGBUF;#define scs_std$recyl_rspid SCS_STD$RECYL_RSPID6#define scs_std$reje ct SCS_STD$REJECT>#define scs_std$repossess_cdrp SCS_STD$REPOSSESS_CDRP7#define scs_std$reqdata SCS_STD$REQDATA<#define scs_std$request_data SCS_STD$REQUEST_DATA>#define scs_std$restore_credit SCS_STD$RESTORE_CREDIT0#define scs_std$resumewaitr SCS_STD$RESUMEWAITR4#define scs_std$resume_thread SCS_STD$RESUME_THREAD8#define scs_std$senddata SCS_STD$SENDDATA=#define scs_std$senddata_wmsg SCS_STD$SENDDATA_WMS G6#define scs_std$senddg SCS_STD$SENDDG7#define scs_std$sendmsg SCS_STD$SENDMSG8#define scs_std$sendrgdg SCS_STD$SENDRGDG9#define scs_std$send_data SCS_STD$SEND_DATA>#define scs_std$send_data_wmsg SCS_STD$SEND_DATA_WMSG?#define scs_std$set_load_rating SCS_STD$SET_LOAD_RATING8#define scs_std$shutdown SCS_STD$SHUTDOWN5#define scs_std$stall SCS_STD$STALL?#define scs_std$start_pwf_ recov SCS_STD$START_PWF_RECOV5#define scs_std$unmap SCS_STD$UNMAP:#define scs_std$unstallucb SCS_STD$UNSTALLUCBG#define scs_std$update_port_load_vector SCS_STD$UPDATE_PORT_LOAD_VECTOR8#define scs_std$vc_flush SCS_STD$VC_FLUSH/*F * Function prototypes for system routines with the SCS_STD$ prefix. */lint scs_std$accept ( void (*msgadr_p)( unsigned int msg_length, void *msg_buf_p, CDT *cdt_p, PDT *pdt_p ), v oid (*dgadr_p)( unsigned int dg_status, unsigned int dg_length, void *dg_buf_p, CDT *cdt_p, PDT *pdt_p ),o void (*erradr_p)( unsigned int err_status, unsigned int reason, CDT *cdt_p, PDT *pdt_p)," int initcr," int minscr," int initdg," int blkpri,& void *condat_p,& void *auxstr_p,< void (*badrsp_p)( __unknown_params ),q void (*movadr_p)( unsigned int status, unsigned int move_status, CDT *cdt_p, PDT *pdt_p ),' int load_rating,t void (*complete_p)( unsigned int accept_status, void *unknown_1, void *unknown_2, CDT *cdt_p,N PDT *pdt_p, int accept_parameter )," CDT *cdt_p,+ int accept_parameter );3int scs_std$allocdg ( PDT *pdt_p, CDRP *cdrp_p );6int scs_std$alloc_msgbuf ( PDT *pdt_p, CDRP *cdrp_p,z void (*ravail_p)( unsigned int stall_return_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );Aint scs_std$alloc_rspid ( CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p,y void (*ravail_p)( unsigned int stall_return_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );(void scs_std$cancel_mbx ( SPPB *sppb );Gint scs_std$cancel_wait ( int rwcptr_upd, PDT *pdt_p, CDRP *cdrp_p );,int  scs_std$change_affinity( UCB *ucb_p );8void scs_std$cleanup_rbuns( int pooltype, PDT *pdt_p );Hint scs_std$config_pth ( void *rmst_lclprt_p, PBO *pbo_p, PB **pb_p );Hint scs_std$config_sys ( void *scssystemid_p, SBO *sbo_p, SB **sb_p );mint scs_std$connect ( void (*msgadr_p)( unsigned int msg_length, void *msg_buf_p, CDT *cdt_p, PDT *pdt_p ), void (*dgadr_p)( unsigned int dg_status, unsigned int dg_length, void *dg_buf_p, CDT *cdt_p, PDT *pdt_p ),p  void (*erradr_p)( unsigned int err_status, unsigned int reason, CDT *cdt_p, PDT *pdt_p),' void *rsysid_p,' void *rstadr_p,' void *rprnam_p,' void *lprnam_p,# int initcr,# int minscr,# int initdg,# int blkpri,' void *condat_p,' void *auxstr_p,=  void (*badrsp_p)( __unknown_params ),r void (*movadr_p)( unsigned int status, unsigned int move_status, CDT *cdt_p, PDT *pdt_p ),( int load_rating,| int (*req_fast_recvmsg_p)( int msg_length, void *msg_buf_p, CDT *cdt_p, PDT *pdt_p, CDRP **cdrp_p ),k void (*fast_recvmsg_pm_p)( void *msg_buf_p, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ),[ void (*change_aff_p)( SB * sb_p, PB *pb_p, CDT *cdt_p, PDT *pdt_p ),u void (*complete_p)( unsigned int connect_status, unsigned int reject_reason, void *msg_buf_p,\ CDT *cdt_p, PDT *pdt_p, int connect_parameter ),- int connect_parameter );5void scs_std$credit_avail( CDT *cdt_p, PDT *pdt_p );4void scs_std$deallocdg ( void *dgbuf, PDT *pdt_p );6void scs_std$deallocmsg ( PDT *pdt_p, CDRP *cdrp_p );'void scs_std$deall_cdt ( CDT *cdt_p );+int scs_std$deall_rspid ( CDRP *cdrp_p );Dvoid scs_std$dealrgmsg ( void *msg_buf_p, CDT *cdt_p, PDT *pdt_p );3int scs_std$disconnect ( int distyp, CDT *cdt_p, void (*complete_p)( unsigned int disconnect_status, void *unknown_1, void *unknown_2, void *unknown_3,X void *unknown_4, int disconnect_parameter ),2 int disconnect_param );Lint scs_std$fast_recvmsg_chk_res ( CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p );Vvoid scs_std$fast_recvmsg_pm( CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p, BUFDESC **bd_p );^int scs_std$fast_recvmsg_request( void *msg_buf_p, PDT *pdt_p, CDT **cdt_p, CDRP **cdrp_p );]void scs_std$fast_sendmsg_ass_res_pm ( void *svapte_boff_bcnt_p, PDT *pdt_p, CDRP *cdrp_p );Vvoid scs_std$fast_sendmsg_pm ( int msg_buf_len, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p,G void (*complete)( __unknown_params ) );Zint scs_std$fast_sendmsg_request ( void *svapte_boff_bcnt_p, PDT *pdt_p, CDRP *cdrp_p );Cint scs_std$find_bd( BDLPTR *bdlt_p, BNAM bnam, BUFDESC **bd_p );7int scs_std$find_rdte ( int rspid, SCS_RD **rdte_p );&int scs_std$init_bdlt( PDT *pdt_p );+int scs_std$initialize_pdt( PDT *pdt_p );Rint scs_std$listen ( void (*msgadr_p)(void *msg_buf_p, CDT *cdt_p, PDT *pdt_p ),o void (*erradr_p)( unsigned int err_status, unsigned int reason, CDT *cdt_p, PDT *pdt_p),&  void *lprnam_p,& void *prinfo_p,% CDT **cdt_p );[void scs_std$lkp_msgwait ( void (*action)( void *action_param, CDT *cdt_p, CDRP *cdrp_p ),= void *action_param, CDT *cdt_p );Zvoid scs_std$lkp_pb_pdt ( void (*action)( SB *sb_p, PB *pb_p, PDT *pdt_p ), PDT *pdt_p );[void scs_std$lkp_rdtcdrp ( void (*action)( void *action_param, CDT *cdt_p, CDRP *cdrp_p ),= void *action_param, CDT *cdt_p );[void scs_std$lkp_rdtwait ( void (*action)( void *action_param, CDT *cdt_p, CDRP *cdrp_p ),= void *action_param, CDT *cdt_p );Gint scs_std$map ( void *svapte_boff_bcnt_p, PDT *pdt_p, CDRP *cdrp_p,q void (*ravail_p)( unsigned int stall_return_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );Eint scs_std$mreset( int force_flag, void *rstation_p, PDT *pdt_p );*void scs_std$msg_buf_avail( PDT *pdt_p );Xint scs_std$mstart( int boot_flag, void *rstation_p, void *boot_address, PDT *pdt_p );!void scs_std$new_pb( PB *pb_p );!void scs_std$new_sb( SB *sb_p );?void scs_std$notify_sysap( int status, PB *pb_p, PDT *pdt_p );Qint scs_std$poll_mbx ( int channel_number, void *sysap_name_p, SPPB **sppb_p );Rint scs_std$poll_mode ( int enable_disable, SPPB *sppb_p, void *scssystemid_p );_int scs_std$poll_proc ( int (*notification_p)( unsigned int context_data, void *sysap_name_p,[  void *scssystemid_p, void *process_info_p,E void *node_name_p ),Y unsigned int context_data, void *sysap_name_p, SPPB **sppb_p );+void scs_std$port_init_done( PDT *pdt_p );Aint scs_std$queuedg ( void *dg_buf_p, CDT *cdt_p, PDT *pdt_p );Zint scs_std$queuemdgs ( int buffer_count, CDT *cdt_p, PDT *pdt_p, int *buffers_added_ );3int scs_std$rchmsgbuf ( PDT *pdt_p, CDRP *cdrp_p,w void (*ravail_p)( unsigned int stall_return_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );3int scs_std$rclmsgbuf ( PDT *pdt_p, CDRP *cdrp_p,w void (*ravail_p)( unsigned int stall_return_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );+void scs_std$recyl_rspid ( CDRP *cdrp_p );.int scs_std$reject ( int rejtyp, CDT *cdt_p,y void (*complete_p)( unsigned int reject_status, void *unknown_1, void *unknown_2, void *unknown_3,S  void *unknown_4, int reject_parameter ),. int reject_parameter );:void scs_std$repossess_cdrp ( PDT *pdt_p, CDRP *cdrp_p );1int scs_std$reqdata ( PDT *pdt_p, CDRP *cdrp_p,s void (*complete)( unsigned int completion_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );6int scs_std$request_data ( PDT *pdt_p, CDRP *cdrp_p,x void (*complete)( unsigned int completion_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );:void scs_std$restore_credit ( PDT *pdt_p, CDRP *cdrp_p );Fvoid scs_std$resumewaitr( unsigned int resume_status, CDRP *cdrp_p );Hvoid scs_std$resume_thread( unsigned int resume_status, CDRP *cdrp_p );2int scs_std$senddata ( PDT *pdt_p, CDRP *cdrp_p,t void (*complete)( unsigned int completion_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );7int scs_std$senddata_wmsg ( PDT *pdt_p, CDRP *cdrp_p,y void (*complete)( unsigned int c ompletion_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );Oint scs_std$senddg ( int disposition_flag, int dg_msg_length, CDRP *cdrp_p );Bint scs_std$sendmsg ( int msg_buf_len, PDT *pdt_p, CDRP *cdrp_p,s void (*complete)( unsigned int completion_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );}int scs_std$sendrgdg ( unsigned int disposition_flag, unsigned int dg_msg_length, void *dg_buf_p, CDT *cdt_p, PDT *pdt_p );3int scs_std$send_data ( PDT *pdt_p, CDRP *cdrp _p,u void (*complete)( unsigned int completion_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );Iint scs_std$send_data_wmsg ( int msg_buf_len, PDT *pdt_p, CDRP *cdrp_p,z void (*complete)( unsigned int completion_status, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p ) );9int scs_std$set_load_rating ( int rating, CDT *cdt_p );void scs_std$shutdown ();Uint scs_std$stall ( int stall_condition_code, CDT *cdt_p, PDT *pdt_p, CDRP *cdrp_p,s   void (*ravail)( unsigned int stall_return_status, void *cdt_p, void *pdt_p, CDRP *cdrp_p ) );6void scs_std$start_pwf_recov( PB *pb_p, PDT *pdt_p );1void scs_std$unmap ( PDT *pdt_p, CDRP *cdrp_p );(void scs_std$unstallucb ( UCB *ucb_p );/void scs_std$vc_flush( PB *pb_p, PDT *pdt_p );#ifdef __cplusplus }#endif"#endif /* __SCS_ROUTINES_LOADED */wwМZU// Module SDA_ROUTINES.H "X-21"//L// ***************************************************** ********************L// * *L// * HPE CONFIDENTIAL. This software is confidential proprietary software *L// * licensed by Hewlett Packard Enterprise Development, LP, and is not *L// * authorized to be used, duplicated or disclosed to anyone without the *L// * prior written permission of HPE. *L// * Copyright 2021 Hewlett Packard Enterprise Development, LP *L// *   *L// * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *L// * proprietary software licensed by VMS Software, Inc., and is not *L// * authorized to be used, duplicated or disclosed to anyone without *L// * the prior written permission of VMS Software, Inc. *L// * Copyright 2021 VMS Software, Inc. *L// *  *L// *************************************************************************////++// // FACILITY://// VMS Executive (LIB_H)// // ABSTRACT://G// This module contains the C function prototypes for the SDA extension// routine entry points.// // AUTHOR:// // Christian Moser, January 1996//// MODIFIED BY://'// X-21 HB Hartmut Becker 5-Jul-2021:// Add SDA$GET_UNWIND_ENTRY_INFO. Use ANSI include style.//*// X-20 RAB Richard A. Bishop 01-Feb-2006// Add SDA$GET_FLAGS//*// X-19 RAB Richard A. Bishop 04-Aug-2005(// Fix prototype for SDA$EXTEND_CBB_FFC//*// X-18 RAB Richard A. Bishop 27-Jul-2005// Add CBB routines//*// X-17 RAB Richard A. Bishop 10-Feb-2005// Add SDA$FID_TO_NAME//#// X-16 RCL Rick Lord 26-Mar-20044// Add #defines and prototype for SDA$DELETE_PREFIX//*// X-15 RAB Richard A. Bishop 04-Feb-20037// Allow for extensions wanting to get at the template!// for IA64 instruction bundles.//*// X-14 RAB Richard A. Bishop 16-Sep-20025// SDA$GET_HEADER now has some additional (optional)8// arguments for access to crash error log entry and/or// trap info data.//*// X-13 RAB Richard A. Bishop 15-Dec-1999// Add SDA$FAO//)// X-12 RAB Richard A. Bishop 7-Dec-1998// Add SDA$GET_DEVICE_NAME//*// X-11 CMOS Christian Moser 30-JUN-1998-// Add new routines SET_PROCESS, SET_CPU and// GET_CURRENT_CPU.//*// X-10 RAB Richard A. Bishop 15-May-19982// Make lowercase and uppercase names equivalent.//)// X-9 RAB Richard A. Bishop 26-Feb-1998<// Use "const char *" instead of "char *" where appropriate//(// X-8 RAB Richard A. Bishop 3-Apr-19975// Fix SDA$SYMBOL_VALUE definition/call. Now returns6// uint64 instead of void. This to ensure users allow// 64-bits for the value. //)// X-7 RAB Richard A. Bishop 21-Mar-19978// Put back in X-5 now everything else is ready. Fix up// a couple more prototypes//)// X-6 RAB Richard A. Bis hop 21-Mar-19979// Back out X-5 - too much fallout from the addition of :// SDAMSG.MSG to LIB until I can get more ducks lined up.//)// X-5 RAB Richard A. Bishop 20-Mar-1997:// Add SDAMSG.MSG, clean up loose ends (eg many routines &// should return void instead of int)//)// X-4 CMOS Christian Moser 13-MAR-1997@// Rename SDA$HANDLER to SDA$COND_HANDLER and define the vector=// table address in this module, so the user doesn't have to*// bother with this in the source module. <// Also fix a bug to include the SDA_xxx include files from9// SYS$LIB_C.TLB instead looking for them in the current// directory.//)// X-3 CMOS Christian Moser 13-JAN-19975// Uppercase CHF$SIGNAL_ARRAY and CHF$MECH_ARRAY for<// __NEW_STARLET to match the CHFDEF declaration for Raven.//)// X-2 CMOS Christian Moser 3-DEC-19966// Add proper routine prototype declarations and more1// comments to make it self explanatory. Add all;// C friendly SDA extension routines and remove unfriendly7// ones. All this in light of the full support for SDA// extensions.//)// X-1 RAB Richard A. Bishop 1-Apr-19964// Moved to LIB_H. Several changes in the light of )// developing the PTHREAD$SDA extension.//+// Prior audit trail is from CLUE$SDA......//)// X-1 CMOS Christian Moser 1-FEB-1996// Initial version.// #ifndef __SDA_ROUTINES_LOADED#define __SDA_ROUTINES_LOADED 1C#pragma __nostandard // This file uses non-ANSI-Standard features!#pragma __member_alignment __save#pragma __nomember_alignmentM#ifdef __INITIAL_POINTER_SIZE // Defined whenever ptr size pragmas supportedW#pragma __required_pointer_size __save // Save the previously-defined required ptr sizeV#pragma __required_pointer_size __short // And set ptr size default to 32-bit pointers#endif#define __unknown_params#define __optional_params ...// Common header files#include #include #include #include #include #include #include #include #include #include *#define sda$vector_table SDA$VECTOR_TABLE6#define SDA$VECTOR_TABLE SDA$EXTEND_VECTOR_TABLE_ADDRB#define sda$extend_vector_table_addr SDA$EXTEND_VECTOR_TABLE_ADDRextern int * sda$vector_table;O/////////////////////////////////////////////////////////////////////////////////F// This routine transfers an area from the memory in t he dump file to @// the callers return buffer. It performs the necessary address 3// translation to locate the data in the dump file.//A// Differences between GETMEM, TRYMEM, and REQMEM are as follows:// B// TRYMEM is called from both GETMEM and REQMEM as the lower levelG// routine that actually does the work. TRYMEM returns success/failure 0// status in R0, but does not signal any errors.//J// GETMEM signals a warning when any error status is returned from TRYMEM.G// Signalling a wa rning will print out a warning message, but does not %// abort the SDA command in progress.//I// REQMEM signals an error when any error status is returned from TRYMEM.F// Signalling an error will print out an error message, abort the SDA H// command in progress and return us to the "SDA>" prompt. It should be H// noted that if the error occurs before we get to the first prompt, an *// error will cause the SDA image to exit.//-// sda$getmem start, dest, length, [physical]-// sda$trymem start, dest, length, [physical]-// sda$reqmem start, dest, length, [physical]//,// start = starting virtual address in dump // dest = return buffer address// length = length of transferA// physical = virtual (=0) or physical (=1) address, default = 0//#define sda$getmem SDA$GETMEM&#define SDA$GETMEM SDA$EXTEND_GETMEM64/#define sda$extend_getmem64 SDA$EXTEND_GETMEM64*int sda$extend_getmem64 ( VOID_PQ start,  void *dest,  int length, __optional_params );#define sda$reqmem SDA$REQMEM&#define SDA$REQMEM SDA$EXTEND_REQMEM64/#define sda$extend_reqmem64 SDA$EXTEND_REQMEM64*int sda$extend_reqmem64 ( VOID_PQ start,  void *dest,  int length, __optional_params );#define sda$trymem SDA$TRYMEM&#define SDA$TRYMEM SDA$EXTEND_TRYMEM64/#define sda$extend_trymem64 SDA$EXTEND_TRYMEM64*int sda$extend_trymem64 ( VOID_PQ start,  void *dest,  int length, __optional_params );O//// /////////////////////////////////////////////////////////////////////////////2// Adds a symbol to SDA's local symbol table.//0// sda$add_symbol symbol_name, symbol_value//E// symbol_name = address of symbol name string (zero-terminated)#// symbol_value = symbol value//%#define sda$add_symbol SDA$ADD_SYMBOL/#define SDA$ADD_SYMBOL SDA$EXTEND_ADD_SYMBOL_CC9#define sda$extend_add_symbol_cc SDA$EXTEND_ADD_SYMBOL_CC8void sda$extend_add_symbol_cc ( const char *symbol_name, uint64 symbol_value );O//////////////////////////////////////////////////////////////////////////////////// Convert a value to a symbol name and offset.E// This routine accepts a value and returns a string which contains a1// symbol and offset corresponding to that value.G// First the value is checked in the value order tree. If no symbol canG// be found, the value is then checked to see if it falls within one of"// the loaded or activated images.//.// sda$symbolize value, symbol_buf, symbol_len//"// value = value to be translated7// symbol_buf = address of buffer to return string into/// symbol_len = maximum length of string buffer//// Status returned is either:%// SS$_NORMAL - successful completion5// SS$_BUFFEROVF - buffer too small, string truncatedF// SS$_NOTRAN - no symbolization for this value (zero string returned)//##define sda$symbolize SDA$SYMBOLIZE-#define SDA$SYMBOLIZE SDA$EXTEND_SYMBOLIZE_CC7#define sda$extend_symbolize_cc SDA$EXTEND_SYMBOLIZE_CC+int sda$extend_symbolize_cc ( uint64 value, char *symbol_buf,! uint32 symbol_len );O/////////////////////////////////////////////////////////////////////////////////'// Get the value of a specified symbol.//)// sda$symbol_value symb_name, symb_value//<// symb_name = zero-terminated string containing symbol name/// symb_value = address to receive symbol value//)#define sda$symbol_value SDA$SYMBOL_VALUE3#define SDA$SYMBOL_VALUE SDA$EXTEND_SYMBOL_VALUE_CC=#define sda$extend_symbol_value_cc SDA$EXTEND_SYMBOL_VALUE_CC8int sda$extend_symbol_value_cc ( const char *symb_name,  uint64 *symb_value );O/////////////////////////////////////////////////////////////////////////////////H// This routine will cause a new page to be written and will output the (// page heading and current sub-heading.//// sda$new_page//!#define sda$new_page SDA$NEW_PAGE)#define SDA$NEW_PAGE SDA$EXTEND_NEW_PAGE 1#defin e sda$extend_new_page SDA$EXTEND_NEW_PAGE void sda$extend_new_page ();O/////////////////////////////////////////////////////////////////////////////////>// This routine will output a specified number of blank lines.//// sda$skip_lines lines//#// lines = number of lines to skip//%#define sda$skip_lines SDA$SKIP_LINES,#define SDA$SKIP_LINES SDA$EXTEND_SKIP_LINES3#define sda$extend_skip_lines SDA$EXTEND_SKIP_LINES,void sda$extend_skip_lines ( uint32 lines );O//////////!///////////////////////////////////////////////////////////////////////B// This routine will check and make sure that the number of lines E// specified will fit on the current page, otherwise it will issue a // page break.//// sda$ensure lines//*// lines = number of lines to fit on page//#define sda$ensure SDA$ENSURE$#define SDA$ENSURE SDA$EXTEND_ENSURE+#define sda$extend_ensure SDA$EXTEND_ENSURE(void sda$extend_ensure ( uint32 lines );O//////////////////////////////////"///////////////////////////////////////////////!// Format a new page sub-heading.//+// sda$format_heading ctrstr, [prmlst, ...]//1// ctrstr = address of control string descriptor/// prmlst = address of quadword FAO parameters//-#define sda$format_heading SDA$FORMAT_HEADING7#define SDA$FORMAT_HEADING SDA$EXTEND_FORMAT_SUBHEAD_CCA#define sda$extend_format_subhead_cc SDA$EXTEND_FORMAT_SUBHEAD_CC8void sda$extend_format_subhead_cc ( const char *ctrstr,  __optional_para#ms );O/////////////////////////////////////////////////////////////////////////////////F// Set the current heading routine to be called after each page break.//'// sda$set_heading_routine heading_rtn//D// heading_rtn = address of routine to be called after each new page//7#define sda$set_heading_routine SDA$SET_HEADING_ROUTINE>#define SDA$SET_HEADING_ROUTINE SDA$EXTEND_SET_HEADING_ROUTINEE#define sda$extend_set_heading_routine SDA$EXTEND_SET_HEADING_ROUTINE?void sda$extend_se$t_heading_routine ( void (*heading_rtn) () );O/////////////////////////////////////////////////////////////////////////////////G// Format and print a single line. This will normally be screen output,G// unless the SDA command SET OUTPUT or SET LOG is used to redirect the// output to a file.//"// sda$print ctrstr, [prmlst, ...]//8// ctrstr = address of a zero-terminated control string#// prmlst = list of FAO parameters//#define sda$print SDA$PRINT%#define SDA$PRINT SDA$EX%TEND_PRINT_CC/#define sda$extend_print_cc SDA$EXTEND_PRINT_CC.int sda$extend_print_cc ( const char *ctrstr,  __optional_params );O/////////////////////////////////////////////////////////////////////////////////.// Format and type a single line to SYS$OUTPUT//!// sda$type ctrstr, [prmlst, ...]//8// ctrstr = address of a zero-terminated control string#// prmlst = list of FAO parameters//#define sda$type SDA$TYPE##define SDA$TYPE SDA$EXTEND_TYPE_CC-#define sda$&extend_type_cc SDA$EXTEND_TYPE_CC-int sda$extend_type_cc ( const char *ctrstr,  __optional_params );O/////////////////////////////////////////////////////////////////////////////////)// Format and return the resultant string//1// sda$fao ctrstr, bufptr, buflen, [prmlst, ...]//8// ctrstr = address of a zero-terminated control string>// bufptr = address of buffer to receive the formatted string,// buflen = the length of the output buffer#// prmlst = list of FAO param'eters//C// The returned value of the routine is a pointer to the end of theC// used portion of the buffer (i.e. a pointer to its trailing zero)//#define sda$fao SDA$FAO!#define SDA$FAO SDA$EXTEND_FAO_CC+#define sda$extend_fao_cc SDA$EXTEND_FAO_CC/char * sda$extend_fao_cc ( const char *ctrstr,  const char *bufptr, const int buflen, __optional_params );O/////////////////////////////////////////////////////////////////////////////////&// Set the current( pages line counter.// // sda$set_line_count line_count//;// line_count = the number of lines printed on current page//-#define sda$set_line_count SDA$SET_LINE_COUNT4#define SDA$SET_LINE_COUNT SDA$EXTEND_SET_LINE_COUNT;#define sda$extend_set_line_count SDA$EXTEND_SET_LINE_COUNT5void sda$extend_set_line_count ( uint32 line_count );O/////////////////////////////////////////////////////////////////////////////////A// Get the number of lines currently printed on the current page.)// // sda$get_line_count line_count//;// line_count = the number of lines printed on current page//-#define sda$get_line_count SDA$GET_LINE_COUNT4#define SDA$GET_LINE_COUNT SDA$EXTEND_GET_LINE_COUNT;#define sda$extend_get_line_count SDA$EXTEND_GET_LINE_COUNT6void sda$extend_get_line_count ( uint32 *line_count );O/////////////////////////////////////////////////////////////////////////////////// Allocate dynamic memory.//// sda$allocate size, ptr_block///// size = siz*e of block to allocate (in bytes)>// ptr_block = address of longword to receive address of block//!#define sda$allocate SDA$ALLOCATE(#define SDA$ALLOCATE SDA$EXTEND_ALLOCATE/#define sda$extend_allocate SDA$EXTEND_ALLOCATE'void sda$extend_allocate ( uint32 size, void **ptr_block );O/////////////////////////////////////////////////////////////////////////////////&// Deallocate and free dynamic memory.//!// sda$deallocate ptr_block, size//4// ptr_block = starting addr+ess of block to be freed1// size = size of block to deallocate (in bytes)//%#define sda$deallocate SDA$DEALLOCATE,#define SDA$DEALLOCATE SDA$EXTEND_DEALLOCATE3#define sda$extend_deallocate SDA$EXTEND_DEALLOCATE-void sda$extend_deallocate ( void *ptr_block, uint32 size );O/////////////////////////////////////////////////////////////////////////////////@// Stores an address value into the current memory address. The <// predefined SDA symbol "." points to the current location.,//// sda$set_address address//?// address = address value to store in current memory location//'#define sda$set_address SDA$SET_ADDRESS0#define SDA$SET_ADDRESS SDA$EXTEND_SET_ADDRESS649#define sda$extend_set_address64 SDA$EXTEND_SET_ADDRESS642void sda$extend_set_address64 ( VOID_PQ address );O/////////////////////////////////////////////////////////////////////////////////9// Gets the address value of the current memory location.//// sda$get_address address//B// a -ddress = pointer on where to store the current memory address//'#define sda$get_address SDA$GET_ADDRESS0#define SDA$GET_ADDRESS SDA$EXTEND_GET_ADDRESS649#define sda$extend_get_address64 SDA$EXTEND_GET_ADDRESS643void sda$extend_get_address64 ( VOID_PQ *address );O/////////////////////////////////////////////////////////////////////////////////F// Validate queue structures. This routine can be used to validate theD// integrity of double-linked, single-linked or self-relative queues* .// either with longword or quadword links.G// If you specify the option SDA_OPT$M_LISTQUEUE the queue elements areF// displayed for debugging purposes. Otherwise a one-line summary willF// tell you how many elements were found and if the queue is intact or// not.//-// sda$validate_queue queue_header [,options]//.// queue_header = address to start search from-// options = flags to indicate type of queue=// none - defaults to double-linked longword queue6// SDA_OPT$M_Q /UEUE_SELF - self-relative queue1// SDA_OPT$M_QUEUE_QUADLINK - quadword queue6// SDA_OPT$M_QUEUE_SINGLINK - single-linked queueG// SDA_OPT$M_QUEUE_LISTQUEUE - display queue elements for debugging//-#define sda$validate_queue SDA$VALIDATE_QUEUE6#define SDA$VALIDATE_QUEUE SDA$EXTEND_VALIDATE_QUEUE64?#define sda$extend_validate_queue64 SDA$EXTEND_VALIDATE_QUEUE648void sda$extend_validate_queue64 ( VOID_PQ queue_header, __optional_params );O////////////////// 0///////////////////////////////////////////////////////////////B// Read symbols from a given file to add symbol definitions to theG// working symbol table by reading GST entries. This is normal a symbol!// file (.STB) or an image (.EXE)//B// sda$read_symfile filespec, options [,relocate_base, symvect_va,&// symvect_size, loaded_image_info]//9// filespec = address of asciz file specification to read<// options = indicate type of symbol file and logging flags,// SDA_OPT$M_READ_FOR 1CE - read/force ,// SDA_OPT$M_READ_IMAGE - read/image ,// SDA_OPT$M_READ_SYMVA - read/symva *// SDA_OPT$M_READ_RELO - read/relo +// SDA_OPT$M_READ_EXEC - read/exec []=// SDA_OPT$M_READ_NOLOG - /nolog, suppress # of symbols read3// SDA_OPT$M_READ_FILESPEC - or given@// SDA_OPT$M_READ_NOSIGNAL - return status, don't signal errors@// relocate_base = base address for symbols (non-sliced symbols)F// symvect_va = symb vector addr (symbols are offs2ets into sym vector)'// symvect_size = size of symbol vectorE// loaded_img_info = addr of $LDRIMG data structure with execlet info//)#define sda$read_symfile SDA$READ_SYMFILE3#define SDA$READ_SYMFILE SDA$EXTEND_READ_SYMFILE_CC=#define sda$extend_read_symfile_cc SDA$EXTEND_READ_SYMFILE_CC7int sda$extend_read_symfile_cc ( const char *filespec,  uint32 options, __optional_params );O///////////////////////////////////////////////////////////////////////////////// 3H// This routine displays the formatted content of a data structure whichG// begins at the address specified. If no symbol prefix is passed, thenI// SDA tries to find the symbols associated with the block type specified0// in the block-type byte of the data structure.//3// sda$format struct_addr [,options, struct_prefix]//>// struct_addr = address of the data structure to be formatted// options = flags1// none - use structure type from xxx$B_TYPEB// SDA_OPT$M_FORMAT_TYPE - 4to be set if structure prefix passedB// SDA_OPT$M_FORMAT_PHYSICAL - marks physical address instead of // virtual address8// struct_prefix = descriptor of structure prefix string//#define sda$format SDA$FORMAT&#define SDA$FORMAT SDA$EXTEND_FORMAT64/#define sda$extend_format64 SDA$EXTEND_FORMAT64/void sda$extend_format64 ( VOID_PQ struct_addr, __optional_params );O/////////////////////////////////////////////////////////////////////////////////// Display onlin5e help.//"// sda$display_help library, topic//)// library = address of library filespec$// topic = address of of topic name//)#define sda$display_help SDA$DISPLAY_HELP,#define sda$display_help( library, topic ) \ { \) $DESCRIPTOR ( library_desc, library ); \% $DESCRIPTOR ( topic_desc, topic ); \+ sda$extend_display_help ( &library_desc, \ &topic_desc ); \ }7#define sda$extend_display_help SDA$EXTEND_DISPLAY_HELPEvoid sda$extend_display_help ( struct dsc$descriptor_s6 *library_desc,, struct dsc$descriptor_s *topic_desc );O/////////////////////////////////////////////////////////////////////////////////D// Parse and execute a SDA command line. Not every SDA command has aD// callable extension interface. For example, to change the process <// context from within SDA you would pass the command stringE// 'SET PROC/IND=xx' to this parse command routine. Abbreviations are // allowed.//(// sda$parse_command cmd_line [,options]//C// cmd_line = 7address of a valid SDA command line (zero-terminated)// options = flags;// none - defaults to 'do not save this command'C// SDA_OPT$K_PARSE_DONT_SAVE - means 'do not save this command'C// SDA_OPT$K_PARSE_SAVE - indicates to 'save this command'(// (can be recalled with KP0)//+#define sda$parse_command SDA$PARSE_COMMAND5#define SDA$PARSE_COMMAND SDA$EXTEND_PARSE_COMMAND_CC?#define sda$extend_parse_command_cc SDA$EXTEND_PARSE_COMMAND_CC8void sda$ext8end_parse_command_cc ( const char *cmd_line, __optional_params );O/////////////////////////////////////////////////////////////////////////////////H// Reads input commands. The command entered will be returned as a zero-G// terminated string. No input, by simply pressing or // will return a null string.//'// sda$get_input prompt, buffer, buflen//-// prompt = address of prompt string (asciz)/// buffer = address of buffer to store command%// buflen 9 = maximum length of buffer//// Status returned is either:%// SS$_NORMAL - successful completion// RMS$_EOF - user hit //##define sda$get_input SDA$GET_INPUT-#define SDA$GET_INPUT SDA$EXTEND_GET_INPUT_CC7#define sda$extend_get_input_cc SDA$EXTEND_GET_INPUT_CC1int sda$extend_get_input_cc ( const char *prompt, char *buffer, uint32 buflen );O/////////////////////////////////////////////////////////////////////////////////F// Given a virtual address, th :is routine finds in which image it fallsF// and returns the image information and offset. The loaded image listH// is traversed first to find this information. If it is not found, thenF// the process activated image list is traversed. If still no success,2// then the resident installed images are checked.//G// The status returned indicate the type of image if a match was found.4// SDA_CIO$V_VALID - set if image offset was found;// SDA_CIO$V_PROCESS - set if image was an activated image1;// SDA_CIO$V_SLICED - set if the image is sliced<// SDA_CIO$V_COMPRESSED - set if activated image containing!// compressed data sections;// SDA_CIO$V_ISD_INDEX - index into ISD_LABELS table (only// for LDRIMG execlets)//<// SDA_CIO$V_xxx flags set: img_info type: subimg_info type:// valid LDRIMG n/a(// valid && sliced LDRIMG ISD_OVERLAY// valid && process IMCB n/a2// valid && process && sliced IMCB KFERES_SECTION////9// sda$get_image_offset va, img_info <, subimg_info, offset//$// va = virtual address to look for<// img_info = pointer to return addr of LDRIMG or IMCB block@// subimg_info = pointer to return addr of ISD_OVERLAY or KFERES;// offset = pointer to address to return offset from image//1#define sda$get_image_offset SDA$GET_IMAGE_OFFSET8#define SDA$GET_IMAGE_OFFSET SDA$EXTEND_GET_IMAGE_OFFSET?#define sda$extend_get_image_offset SDA$EXTEND_GET_IMAGE_OFFSET6COMP_IMG_OFF sda$extend_get_image_offset ( VOID_PQ va, VOID_P=Q img_info, VOID_PQ subimg_info, VOID_PQ offset );O/////////////////////////////////////////////////////////////////////////////////I// Gets the string representing the bugcheck code passed as the argument.F// The bugcheck message string is passed in the buffer (represented as)// a pointer and length) in ASCIZ format.//>// sda$get_bugcheck_msg bugcheck_code, buffer_ptr, buffer_size///// bugcheck_code = the bugcheck code to look up:// buffer_ptr = address of buf>fer to save bugcheck message1// buffer_size = size of buffer to put message in//1#define sda$get_bugcheck_msg SDA$GET_BUGCHECK_MSG5#define SDA$GET_BUGCHECK_MSG SDA$EXTEND_GET_BUGMSG_CC9#define sda$extend_get_bugmsg_cc SDA$EXTEND_GET_BUGMSG_CC5void sda$extend_get_bugmsg_cc ( uint32 bugcheck_code, char *buffer_ptr, uint32 buffer_size );O/////////////////////////////////////////////////////////////////////////////////F// Gets the string representing the curren?t HW name and puts it in the3// buffer passed as the argument (in ASCIZ format).//*// sda$get_hw_name buffer_ptr, buffer_len//1// buffer_ptr = address of buffer to save HW name3// buffer_len = length of buffer to receive HW name//'#define sda$get_hw_name SDA$GET_HW_NAME1#define SDA$GET_HW_NAME SDA$EXTEND_GET_HW_NAME_CC;#define sda$extend_get_hw_name_cc SDA$EXTEND_GET_HW_NAME_CC2void sda$extend_get_hw_name_cc ( char *buffer_ptr, uint32 buffer_len );O////////////////// @///////////////////////////////////////////////////////////////'// Translate block type/subtype to name//G// sda$get_block_name block_type, block_subtype, buffer_ptr, buffer_len//D// block_type = block type (usually extracted from xxx$b_type field)L// block_subtype = block subtype (ignored if the block type has no subtypes)4// buffer_ptr = address of buffer to save block name6// buffer_len = length of buffer to receive block name//-#define sda$get_block_name SDA$GET_BLOCK_NAME4#defAine SDA$GET_BLOCK_NAME SDA$EXTEND_GET_BLOCK_NAME;#define sda$extend_get_block_name SDA$EXTEND_GET_BLOCK_NAME3void sda$extend_get_block_name ( uint32 block_type, uint32 block_subtype, char *buffer_ptr, uint32 buffer_len );O///////////////////////////////////////////////////////////////////////////////// G// Get the PCB address of the "SDA current process" currently selected.//// sda$get_current_pcb pcbadr//>// pcbadr = address of to retrieve a pointeBr to a PCB address///#define sda$get_current_pcb SDA$GET_CURRENT_PCB6#define SDA$GET_CURRENT_PCB SDA$EXTEND_GET_CURRENT_PCB=#define sda$extend_get_current_pcb SDA$EXTEND_GET_CURRENT_PCB1void sda$extend_get_current_pcb ( PCB **pcbadr );O/////////////////////////////////////////////////////////////////////////////////B// Returns pointers to the dumpfile header and the errorlog buffer3// together with the size of those data structures.//0// sda$get_header dmp_header, dmp_header_siCze, "// errlog_buf, errlog_buf_size,&// crasherl_buf, crasherl_buf_size,%// trapinfo_buf, trapinfo_buf_size//@// dmp_header = address in which to store the local copy address// of the dumpfile header>// dmp_header_size = address to return size of dumpfile header@// errlog_buf = address in which to store the local copy address// of the errorlog buffer>// errlog_buf_size = address to return size of errorlog buffer//%// (remaining arguments are optional)//B// crash Derl_buf = address in which to store the local copy address#// of the crash error log entryF// crasherl_buf_size = address to return size of crash error log entryB// trapinfo_buf = address in which to store the local copy address// of the trapinfo data>// trapinfo_buf_size = address to return size of trapinfo data//%#define sda$get_header SDA$GET_HEADER,#define SDA$GET_HEADER SDA$EXTEND_GET_HEADER3#define sda$extend_get_header SDA$EXTEND_GET_HEADER.void sda$extend_get_header ( D EMP **dmp_header, uint32 *dmp_header_size, void **errlog_buf, uint32 *errlog_buf_size, __optional_params );O/////////////////////////////////////////////////////////////////////////////////K// Translates one Alpha machine instruction or IA64 slot into the assemblerJ// string equivalent. Alpha instructions are always 4 bytes long. For IA64K// the entire 128-bit bundle must be available, whose base address is foundJ// by clearing the low 3 bits of the address referenced Fby the istream_ptrL// argument. The instruction stream must first be read into local memory andI// then a pointer to the instruction stream is passed to the routine. ForI// every successful translated instruction, that pointer is automatically4// updated to point to the next instruction or slot.J// The output assembler string is zero-terminated and in case of a failureG// a null string is returned. Likewise, if IA64 and the output templateF// string argument is provided, it is zero-terminate Gd and in case of a%// failure a null string is returned.//L// sda$instruction_decode istream_ptr, buffer, buflen [, template, templen]//D// istream_ptr = address of the pointer which points to the i-stream?// buffer = address of a string buffer into which to store the// output assembler string.// buflen = maximum size of the string buffer@// template = address of a string buffer into which to store the3// output template string (IA64 only, optional)=// templen = maximum si Hze of the template buffer (IA64 only,// optional)//// Status returned is either:%// SS$_NORMAL - successful completionB// SS$_BADPARAM - any of the following failures (output buffer too<// small, invalid register, invalid opcode class/format,'// could not translate instruction)//5#define sda$instruction_decode SDA$INSTRUCTION_DECODE<#define SDA$INSTRUCTION_DECODE SDA$EXTEND_INSTRUCTION_DECODEC#define sda$extend_instruction_decode SDA$EXTEND_INSTRUCTION_DECODE6int sda$Iextend_instruction_decode ( void *istream_ptr, char *buffer, uint32 buflen, __optional_params );O///////////////////////////////////////////////////////////////////////////////// C// Get the CPU database address of the "SDA current CPU" currently // selected.//// sda$get_current_cpu cpudb//?// cpudb = address of to retrieve a pointer to a CPUDB address///#define sda$get_current_cpu SDA$GET_CURRENT_CPU9#define SDA$GET_CURRENT_CPU SDA$EXTEND_GET_CURRENT_CPUJ_CCC#define sda$extend_get_current_cpu_cc SDA$EXTEND_GET_CURRENT_CPU_CC3void sda$extend_get_current_cpu_cc ( CPU **cpudb );O/////////////////////////////////////////////////////////////////////////////////!// Set a new SDA process context.//4// sda$set_process proc_name, proc_index, proc_addr//=// proc_name = zero-terminated string containing process name// proc_index = process index// proc_addr = PCB address///// Note: the parameters are mutually exclusive.//'#definKe sda$set_process SDA$SET_PROCESS1#define SDA$SET_PROCESS SDA$EXTEND_SET_PROCESS_CC;#define sda$extend_set_process_cc SDA$EXTEND_SET_PROCESS_CC7int sda$extend_set_process_cc ( const char *proc_name,  int proc_index, int proc_addr );O/////////////////////////////////////////////////////////////////////////////////// Set a new SDA CPU context.//// sda$set_cpu cpu_id//// cpu_id = CPU Id//#define sda$set_cpu SDA$SET_CPU)#define SDA$SET_CPU SDA$EXTEND_SLET_CPU_CC3#define sda$extend_set_cpu_cc SDA$EXTEND_SET_CPU_CC)int sda$extend_set_cpu_cc ( int cpu_id );O/////////////////////////////////////////////////////////////////////////////////)// Convert a UCB address to a device name//3// sda$get_device_name ucb_addr, name_buf, name_len//(// ucb_addr = system address of the UCB;// name_buf = address of buffer to return device name into3// name_len = maximum length of device name buffer//// Status returned is either:%// SS$ M_NORMAL - successful completion5// SS$_BUFFEROVF - buffer too small, string truncatedF// SS$_NOTRAN - no symbolization for this value (zero string returned)///#define sda$get_device_name SDA$GET_DEVICE_NAME6#define SDA$GET_DEVICE_NAME SDA$EXTEND_GET_DEVICE_NAME=#define sda$extend_get_device_name SDA$EXTEND_GET_DEVICE_NAME2int sda$extend_get_device_name ( VOID_PQ ucb_addr, char *name_buf, int name_len);O//////////////////////////////////////////////////////////////N///////////////////L// Condition handler which can be established using the following statement://&// lib$establish ( sda$cond_handler );//)#define sda$cond_handler SDA$COND_HANDLER0#define SDA$COND_HANDLER SDA$EXTEND_COND_HANDLER7#define sda$extend_cond_handler SDA$EXTEND_COND_HANDLER#ifdef __NEW_STARLET8int sda$extend_cond_handler ( CHF$SIGNAL_ARRAY *sigarr, CHF$MECH_ARRAY *mecharr );#else?int sda$extend_cond_handler ( struct chf$signal_array *sigarr, ' struct chfO$mech_array *mecharr );#endifO/////////////////////////////////////////////////////////////////////////////////H// Displays a list of image activated images together with their virtual(// address range for debugging purposes.//// sda$dbg_image_info//-#define sda$dbg_image_info SDA$DBG_IMAGE_INFO4#define SDA$DBG_IMAGE_INFO SDA$EXTEND_DBG_IMAGE_INFO;#define sda$extend_dbg_image_info SDA$EXTEND_DBG_IMAGE_INFO"void sda$extend_dbg_image_info ();$#pragma __member_alignment __rPestoreN#ifdef __INITIAL_POINTER_SIZE // Defined whenever ptr size pragmas supported]#pragma __required_pointer_size __restore // Restore the previously-defined required ptr size#endif#pragma __standard O/////////////////////////////////////////////////////////////////////////////////M// Delete all symbols with a given prefix from SDA's local symbol tables//!// sda$delete_prefix prefix//=// prefix = address of prefix string (zero-terminated)//+#define sd Qa$delete_prefix SDA$DELETE_PREFIX5#define SDA$DELETE_PREFIX SDA$EXTEND_DELETE_PREFIX_CC?#define sda$extend_delete_prefix_cc SDA$EXTEND_DELETE_PREFIX_CC7void sda$extend_delete_prefix_cc ( const char *prefix);O/////////////////////////////////////////////////////////////////////////////////E// Translate File ID to file name, using LIB$FID_TO_NAME if analyzing?// running system, or using collected file data (if present) if// analyzing a system dump//2// sda$fid_to_name devptr, fiRdptr, bufptr, buflen//?// devptr = address of device name string (ASCIZ) in ALLDEVNAM4// format (leading underscore and trailing colon// are ignored)"// fidptr = address of 3-word FID<// bufptr = address of buffer to receive the ASCIZ filename,// buflen = the length of the output buffer//// Status returned is either:%// SS$_NORMAL - successful completionD// SDA$_NOCOLLECT - no collection available (for entire system, this// disk, or just this file)*// other - asS returned by LIB$FID_TO_NAME//'#define sda$fid_to_name SDA$FID_TO_NAME.#define SDA$FID_TO_NAME SDA$EXTEND_FID_TO_NAME5#define sda$extend_fid_to_name SDA$EXTEND_FID_TO_NAME+int sda$extend_fid_to_name ( char *devptr,  unsigned short *fidptr,  char *bufptr, int buflen );O/////////////////////////////////////////////////////////////////////////////////// CBB handling routines:// SDA$CBB_INIT// SDA$CBB_TEST_BIT// SDA$CBB_CLEAR_BIT// SDA$CBB_SET_BITT// SDA$CBB_COPY// SDA$CBB_BOOLEAN_OPER// SDA$CBB_FFC// SDA$CBB_FFS//O/////////////////////////////////////////////////////////////////////////////////// sda$cbb_init cbb//7// cbb = Address of CBB (of length CBB$K_STATIC_BLOCK)//// Status returned: // None//!#define sda$cbb_init SDA$CBB_INIT(#define SDA$CBB_INIT SDA$EXTEND_CBB_INIT/#define sda$extend_cbb_init SDA$EXTEND_CBB_INIT&void sda$extend_cbb_init (CBB_PQ cbb);O//////////////////////////////U///////////////////////////////////////////////////// sda$cbb_test_bit cbb, bit//&// cbb = Address of local copy of CBB.// bit = bit number to be tested (zero-based)//// Status returned is one of:// SS$_WASSET Bit was set // SS$_WASCLR Bit was clear2// SS$_BADPARAM Bit number outside size of CBB//)#define sda$cbb_test_bit SDA$CBB_TEST_BIT0#define SDA$CBB_TEST_BIT SDA$EXTEND_CBB_TEST_BIT7#define sda$extend_cbb_test_bit SDA$EXTEND_CBB_TEST_BIT(int sda$extend_cbbV_test_bit (CBB_PQ cbb, int bit);O/////////////////////////////////////////////////////////////////////////////////// sda$cbb_clear_bit cbb, bit//&// cbb = Address of local copy of CBB/// bit = bit number to be cleared (zero-based)(// If bit = -1, all bits are cleared//// Status returned is one of:// SS$_NORMAL Success2// SS$_BADPARAM Bit number outside size of CBB//+#define sda$cbb_clear_bit SDA$CBB_CLEAR_BIT2#define SDA$CBB_CLEAR_BIT SDA$EXTEND_CBB_CWLEAR_BIT9#define sda$extend_cbb_clear_bit SDA$EXTEND_CBB_CLEAR_BIT)int sda$extend_cbb_clear_bit (CBB_PQ cbb, int bit);O/////////////////////////////////////////////////////////////////////////////////// sda$cbb_set_bit cbb, bit//&// cbb = Address of local copy of CBB+// bit = bit number to be set (zero-based)$// If bit = -1, all bits are set//// Status returned is one of:// SS$_NORMAL Success2// SS$_BADPARAM Bit number outside size of CBB//'#define Xsda$cbb_set_bit SDA$CBB_SET_BIT.#define SDA$CBB_SET_BIT SDA$EXTEND_CBB_SET_BIT5#define sda$extend_cbb_set_bit SDA$EXTEND_CBB_SET_BIT'int sda$extend_cbb_set_bit (CBB_PQ cbb, int bit);O/////////////////////////////////////////////////////////////////////////////////&// sda$cbb_copy input_cbb, output_cbb//8// input_cbb = Address of local copy of CBB to be copied)// output_cbb = Address of target of copy//// Status returned: // None//!#define sda$cbb_copy SDA$CBB_CYOPY(#define SDA$CBB_COPY SDA$EXTEND_CBB_COPY/#define sda$extend_cbb_copy SDA$EXTEND_CBB_COPY+void sda$extend_cbb_copy (CBB_PQ input_cbb, CBB_PQ output_cbb);O/////////////////////////////////////////////////////////////////////////////////-// sda$cbb_boolean_oper input_cbb, output_cbb//>// input_cbb = Address of local copy of first CBB in operation<// output_cbb = Address of local copy of second CBB (target)=// operation = One of CBB$C_OR or CBB$C_BIC. Others to follow// Z if needed//// Status returned:*// 0 No bits set in resulting bitmask3// 1 At least one bit set in resulting bitmask//1#define sda$cbb_boolean_oper SDA$CBB_BOOLEAN_OPER8#define SDA$CBB_BOOLEAN_OPER SDA$EXTEND_CBB_BOOLEAN_OPER?#define sda$extend_cbb_boolean_oper SDA$EXTEND_CBB_BOOLEAN_OPER2int sda$extend_cbb_boolean_oper (CBB_PQ input_cbb, CBB_PQ output_cbb, int operation);O/////////////////////////////////////////////////////////////////////////////////[// sda$cbb_ffc cbb, start_bit//5// cbb = Address of local copy of CBB to be searched*// start_bit = First bit in CBB for search//// Status returned:"// n < valid bits Bit n is set'// n >= valid bits No bits are set //#define sda$cbb_ffc SDA$CBB_FFC&#define SDA$CBB_FFC SDA$EXTEND_CBB_FFC-#define sda$extend_cbb_ffc SDA$EXTEND_CBB_FFC#int sda$extend_cbb_ffc (CBB_PQ cbb, int start_bit);O////////////////////////////////////////////////////////////////////////////\/////// sda$cbb_ffs cbb, start_bit//5// cbb = Address of local copy of CBB to be searched*// start_bit = First bit in CBB for search//// Status returned:"// n < valid bits Bit n is set'// n >= valid bits No bits are set //#define sda$cbb_ffs SDA$CBB_FFS&#define SDA$CBB_FFS SDA$EXTEND_CBB_FFS-#define sda$extend_cbb_ffs SDA$EXTEND_CBB_FFS#int sda$extend_cbb_ffs (CBB_PQ cbb, int start_bit);O//////////////////////////////////////////////////////////////////]///////////////C// Obtain environment flags that allow an extension to know what isD// being analyzed - system vs dump, type of dump, platform, override // mode, etc.//// sda$get_flags flagaddr//2// flagaddr = address of location to receive flags//// Status returned: // None//##define sda$get_flags SDA$GET_FLAGS*#define SDA$GET_FLAGS SDA$EXTEND_GET_FLAGS1#define sda$extend_get_flags SDA$EXTEND_GET_FLAGS0void sda$extend_get_flags (SDA_FLAGS *flagaddr);K#if defined ^__x86_64 || XCVMS != 0 // Verified for x86 port, Hartmut BeckerO/////////////////////////////////////////////////////////////////////////////////"// Obtain unwind entry information//5// sdaget_unwind_entry_info pc, ue_block, name [,...]// pc = Target PC=// ue_block = Address of a 4-quadword block to be filled inD// name = (Optional) Will be updated with name associated with pc//// Status returned:// SS$_NORMAL Success// SS$_IVADDR Invalid PC.// SS$_NODAT_A No unwind information found//R// Please note, usually the extend name would be sda$extend_get_unwind_entry_info,I// which are 32 characters, one too much; the C compiler will shorten it;S// not a big deal, but it would be a warning in the object module propagated to theS// shareable image; so one would either disable the compiler warning here or changeW// the link completion code to SUCCESS. And even then, when looking at the map, someoneV// may be confused not to find full name as used`, here. So WE shorten the extend name.;#define sda$get_unwind_entry_info SDA$GET_UNWIND_ENTRY_INFO7#define SDA$GET_UNWIND_ENTRY_INFO SDA$EXTEND_GET_UEINFO3#define sda$extend_get_ueinfo SDA$EXTEND_GET_UEINFO%int sda$extend_get_ueinfo (uint64 pc, VOID_PQ ue_block, VOID_PQ name, ...);(#endif // defined __x86_64 || XCVMS != 0#endif // __SDA_ROUTINES_LOADEDww0ZU #ifndef __SECURITY_MACROS_LOADED"#define __SECURITY_MACROS_LOADED 1O/* IDENT X-7 a */N/*****************************************************************************N * *N * COPYRIGHT (c) 1996, 1997 BY *N * DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS. *I * COPYRIGHT (c) 2000 Compaq Computer Corporation *N * ALL RIGHTS RESERVED. b *N * *N * THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED *N * ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE *N * INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER *N * COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY *N * OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY c *N * TRANSFERRED. *N * *N * THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE *N * AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT *N * CORPORATION. *N * *N * DIGITAL ASSUMES NOd RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS *N * SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL. *N * *O *****************************************************************************//* *++ * FACILITY: * * VMS Executive (LIB_H) * * ABSTRACT: *@ * This header file provides macros and functions that are used * for security services. * * AUTHOR: * *e Bill Davenport *# * CREATION DATE: 17-Apr-1996 * * MODIFICATION HISTORY: */ * X-7 JAH0453 John A Harney 12-Nov-2003D * Dereference the privilege pointers in $PSB$ENABLE_PRIVILEGES. *$ * X-2 Douglas Fyfe 28-Feb-2000= * Use new 32-bit defined pointers for persona structures *. * X-1 AJM Andrew J. Moskal 25-Feb-1997? * Add FLAGS parameter to NSA_STD$ASSUME_PERSONA prototype. * * Shuan Lin 24-Jan-1997; * Mainline merge of Per-Thrfead Security support: (gen 4A3) *4 * X-3A7 Shuan Lin 13-Feb-1997" * Simplified GET_CURPSB code. *3 * X-3A6 Shuan Lin 7-Feb-1997! * Remove the paranoid stuff.C * Rewrite macro get_curpsb to use nsa$get_current_psb routine. *4 * X-3A5 Shuan Lin 24-Jan-1997 * Fix the comment problem. *4 * X-3A4 Shuan Lin 23-Jan-1997< * Rewrite GET_CURPSB to support backward compatibility. * g4 * X-3A3 Shuan Lin 31-Oct-1996' * Support backward compatibility.  *= * X-3A2 AJM96060 Andrew J. Moskal 30-Jun-1996D * In GET_CURPSB, don't check mode if persona is already active. *C * X-3A1 WXD Bill Davenport 16-Jul-19960 * Rename min macro to avoid conflicts. *C * X-3 JMM960A7 John M. Molloy 28-May-1996- * Incorporate comments from code review:' * -- Add NEW_ShTARLET support. *C * X-2 WXD Bill Davenport 8-May-1996A * Added additional macros and supporting documentation. *D * X-1 WXD Bill Davenport 17-Apr-1996$ * Created initial version. *-- *//*= * Include any header files we need to make these macros work */#include #include #include #include #include #include #include #include #include #include #include #include #include #include #define ___TRUE___ (0 == 0) #define ___FALSE___ (0 == 1)B#define JIB$K_SIZE_ACCOUNT sizeof(((JIB *) 0)->jib$t_account)C#define JIB$K_SIZE_USERNAME sizeof(((JIB *) 0)->jib$t_username) @#define $_$_$min$_$_$(e1,e2) (((e1) <= (e2)) ? (e1) : (e2))#ifdef __INITIAL_POINTER_SIZE&#pragma __requirjed_pointer_size __save'#pragma __required_pointer_size __short#endif /* global symbol */%extern int ctl$gl_persona_usercount;/*+ * Function prototypes for global functions */?extern int EXE$PERSONA_EXPORT_ARB (int level);?extern int EXE$PERSONA_IMPORT_ARB (int level);<extern int NSA_STD$GET_CURRENT_PSB (KTB *ktb, PSB_ps *Psb);Bextern int NSA_STD$ASSUME_PERSONA (int personaId,< k KTB *ktb,E int previousMode,? ISSSRVCFLG flags);<extern int NSA_STD$CLONE_PSB (PSB_ps psb,= int mode,@ PSB_ps *newPsb);=extern void NSA_STD$DEREFERENCE_PSB (PSB_ps psb);=extern void NSA_STD$FREE_PSB (PSB_ps psb);l=extern int NSA_STD$GET_PSB (int size,= PSB_ps *psb);3extern int NSA_STD$EXPAND_PERSONA_ARRAY (void);Fextern int NSA_STD$INIT_PERSONA_ARRAY (PSB_ps naturalPsb);3extern int NSA_STD$LAZY_PERSONA_ASSUME (void);Bextern int NSA_STD$LOOKUP_PERSONA (int personaId,E int previousMode,= PSB_ps * mpsb);=extern void NSA_STD$REFERENCE_PSB (PSB_ps psb);3extern int NSA_STD$RELEASE_PERSONA_ARRAY (void);=extern int NSA_STD$REMOVE_PERSONA (PSB_ps psb);<extern int NSA_STD$STORE_PERSONA (PSB_ps psb,C int *personaId);?extern int NSA_STD$ADD_RIGHTS_IDENTIFIER (RIGHTS_ps rights,C int identifier,> i nnt flags,B int *prevFlags,F RIGHTS_ps *clonedRights);?extern int NSA_STD$CLONE_RIGHTS_CHAIN (RIGHTS_ps rights,F RIGHTS_ps *clonedRights);@extern void NSA_STD$DEREF_RIGHTS_CHAIN (RIGHTS_ps rights);?extern void NSA_STD$FIND_RIGHTS_IDENTIFIER (RIGHTS_ps rights,C int identifier,D o RIGHTS_ps *foundRights,C int *foundIndex,D RIGHTS_ps *freeRights);@extern void NSA_STD$FREE_RIGHTS_CHAIN (RIGHTS_ps rights);=extern int NSA_STD$GET_RIGHTS_BLOCK (int size,@ RIGHTS_ps *rights);@extern void NSA_STD$REFERENCE_RIGHTS_CHAIN (RIGHTS_ps rights);?extern int NSA_STD$REMOVE_RIGHTS_IDENT p (RIGHTS_ps rights,C int identifier,B int *prevFlags,F RIGHTS_ps *clonedRights);/** * Function prototypes for local functions */Cstatic int get_curpsb (PSB_ps *u_psb, C KTB *const u_ktb, F const int u_acmode); q#ifdef __NEW_STARLET,#pragma inline (___internal___get_ps_prvmod)-static int ___internal___get_ps_prvmod (void){ typedef union { PSLDEF fields; uint64 quad; } PS; PS ps; * /* Read PS and return previous mode */ ps.quad = __PAL_RD_PS();( return (int) ps.fields.psl$v_prvmod;}#endif /* __NEW_STARLET */ &#pragma inline (___memcpy_and_fill___)=static void ___memcpy_and_fill___ (void *d, const int dSize, rC const void *s, const int sSize, 0 const char f){ /* * First copy the data */0 memcpy (d, s, $_$_$min$_$_$ (dSize, sSize)); /*" * Now perform any needed fill */ if (dSize > sSize) {$ char *dc = (char *) d;6 memset (&dc[sSize], (int) f, (dSize - sSize)); }} #define ACMODE_PREVIOUS -1#define CONTEXT_PERSONA 0#define CONTEXT_PROCsESS 13#define ___success___(status) ((status & 0x1) == 1) #pragma inline (___setup_ktb___).static KTB * ___setup_ktb___(KTB *const u_ktb){ /*? * If we didn't receive a ktb address as input then compute9 * our current ktb, otherwise use what was specified. */ if (u_ktb == (void *) 0) return get_curktb (); else return u_ktb;} #pragma inline (___setup_psb___)=static int ___setup_psb___ (PSB_ps *psb, PSB_ps const u_psb, A t KTB *const u_ktb, const int u_acmode){ int status; /*? * If we didn't receive a psb address as input then compute9 * our current psb, otherwise use what was specified. */ if (u_psb == (void *) 0) {7 status = get_curpsb (psb, u_ktb, u_acmode);' if (!___success___(status)) return status; } else *psb = u_psb; return SS$_NORMAL;} /*++ * D E S C R Iu P T I O N * =====================G * Audit control macros. These macros are used to temporarily disable H * and enable security auditing for the current persona. The savedAuditE * parameter can be used to capture the current audit state for laterE * restoration by the $RESTORE_AUDIT macro. These macros are usable  * only from kernel mode. *> * The following is the intended usage style for these macros: * * int savedAudit; * int status; *A * status = $psb$disabvle_audit (&savedAudit, psb, ktb, acmode); * if (status) * { * ...< * $psb$restore_audit (&savedAudit, psb, ktb, acmode); * } * else * persona assume error; * * N O T E S * =========A * These macros operate on the current persona. Failure to take H * appropriate steps to localize this operation (such as first creating I * a cloned persona) will result in leakage of the actions of this macro 7 * to all other execution threads sharing this persona. w *H * Since these macros operate on the current persona, the most efficientA * argument that can be supplied by a caller is the psb argument.@ * If the psb argument is omitted, then the next most efficient  * argument is the ktb address. *D * The acmode argument must be supplied if any lazy assume performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF * context of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PRE xVIOUS (-1) will cause the + * previous mode to be fetched by the code. * * U S A G E * =========< * $psb$restore_audit Enable or restore NOAUDIT count *B * savedAudit longword to restore current NOAUDIT valueB * psb optional PSB (default is current persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *F * $psb$disable_audit Incre yment NOAUDIT count to disable audits *@ * savedAudit longword to store current NOAUDIT valueB * psb optional PSB (default is current persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *E * $psb$enable_audit Decrement NOAUDIT count to enable audits *@ * savedAudit longword to store current NOAUDIT valueB * psb z optional PSB (default is current persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *M * If unknown, the psb and ktb arguments must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */##pragma inline ($psb$restore_audit)Fstatic int $psb$restore_audit (int *u_savedAudit, PSB_ps const u_psb, E { KTB *const u_ktb, const int u_acmode){ PCB *pcb; PSB_ps psb; KTB *ktb; int status; /*7 * Set up our ktb pointer (needed later to get pcb) */" ktb = ___setup_ktb___ (u_ktb); /*< * Set up our psb pointer from user supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return status; /*C * The purpose of the following test is to | allow only an enableC * of auditing to take place if auditing is currently disabled,@ * and to allow a disable of auditing to take place anytime. */; if ((psb->psb$l_noaudit != 0) || (*u_savedAudit == -1)) {D psb->psb$l_noaudit = psb->psb$l_noaudit - *u_savedAudit;, *u_savedAudit = - *u_savedAudit;5 /* update pcb if it is the only user mode psb */+ if ((ctl$gl_persona_usercount <= 1) &&" (psb->psb$l_mode == PSL$C_USER)) { } /* * Pick up PCB address */ pcb = ktb->ktb$l_pcb;+ pcb->pcb$l_noaudit = psb->psb$l_noaudit;  } } else *u_savedAudit = 0; return SS$_NORMAL;} ##pragma inline ($psb$disable_audit)Fstatic int $psb$disable_audit (int *u_savedAudit, PSB_ps const u_psb, D KTB *const u_ktb, const int u_acmode){ PSB_ps psb; int status; /*< * Set up our psb pointer from use~r supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return status;( /* Save direction for restoration */ *u_savedAudit = -1;3 /* Perform the modification to audit counter */1 $psb$restore_audit (u_savedAudit, psb, 0, 0); return SS$_NORMAL;} "#pragma inline ($psb$enable_audit)Dstatic int $psb$enable_audit (int *u_savedAudit, PSB_ps const u_psb,C KTB *const u_ktb, const int u_acmode){ PSB_ps psb; int status; /*< * Set up our psb pointer from user supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return status;( /* Save direction for restoration */ *u_savedAudit = 1;3 /* Perform the modification to audit counter */1 $psb$restore_audit (u_savedAudit, psb, 0, 0); return SS$_NORMAL;} /*++ * D E S C R I P T I O N * =====================E * Audit test macro. This macro is used to test the current state ofE * auditing for the current persona. Using this test for an invalid A * persona is treated as if auditing were enabled. This macro is * usable only from kernel mode. *< * The following is the intended usage style for this macro: */ * if ($psb$audit_enabled (psb, ktb, acmode)) * { * ... * } * * N O T E S * =========/ * These macros operate on the c urrent persona. *G * Since this macro operates on the current persona, the most efficientA * argument that can be supplied by a caller is the psb argument.@ * If the psb argument is omitted, then the next most efficient  * argument is the ktb address. *D * The acmode argument must be supplied if any lazy assume performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF * context of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PREVIOUS (-1) will cause the + * previous mode to be fetched by the code. * * U S A G E * =========6 * $psb$audit_enabled Test for auditing enabled *B * psb optional PSB (default is current persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *M * If unknown, the psb and ktb arguments must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */##pragma inline ($psb$audit_enabled)Xstatic int $psb$audit_enabled (PSB_ps const u_psb, KTB *const u_ktb, const int u_acmode){ PSB_ps psb; int status; /*< * Set up our psb pointer from user supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return ___TRUE___; /*< * Return the current state of auditing for this persona */% return (psb->psb$l_noaudit != 0);} /*++ * D E S C R I P T I O N * =====================B * Privilege control macros. These macros are used for temporary @ * enabling and disabling of privileges for the current persona.1 * These macros are usable only from kernel mode. *> * The following is the intended usage style for these macros: * * PRVDEF savedPrivs; * PRVDEF privMask; * int status; *P * status = $psb$enable_privileges (&privMask, &savedPrivs, psb, ktb, acmode); * if (status) * { * ...A * $psb$restore_privileges (&savedPrivs, psb, ktb, acmode); * } * else * persona assume error; * * N O T E S * =========A * These macros operate on the current persona. Failure to take H * appropriate steps to localize this operation (such as first creating I * a cloned persona) will result in leakage of the actions of this macro 7 * to all other execution threads sh aring this persona. *H * Since these macros operate on the current persona, the most efficientA * argument that can be supplied by a caller is the psb argument.@ * If the psb argument is omitted, then the next most efficient  * argument is the ktb address. *D * The acmode argument must be supplied if any lazy assume performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF * context of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PREVIOUS (-1) will cause the + * previous mode to be fetched by the code. *D * The privMask argument is the address of a quadword privilege mask! * containing bits to be enabled. *B * The savedPriv argument is the address of a quadword in which toA * save the current privilege bit settings for later restoration. * * U S A G E * =========2 * $psb$enable_privileges Enable privileges *3 * privMask address of privileges maskF * savedPriv  address of quadword to store saved privilegesB * psb optional PSB (default is current persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *3 * $psb$restore_privileges Restore privileges *= * savedPriv address of privileges being restoredB * psb optional PSB (default is current persona)H * ktb optio nal KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *M * If unknown, the psb and ktb arguments must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */&#pragma inline ($psb$enable_privilege)Ostatic int $psb$enable_privilege (const PRVDEF *u_privMask, PRVDEF *savedPriv, [ PSB_ps const u_psb, KTB *const u_ktb, const int u_acmode){ PSB_ps psb; PRVDEF *prv; int status; /*< * Set up our psb pointer from user supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return status; prv = &psb->psb$q_workpriv; /* * Save privs (if requested) */ if (savedPriv) *savedPriv = *prv; /* * Enable requested privs */4 prv->prv$l_l1_bits |= u_privMask->prv$l_l1_bits;4 prv->prv$l_l2_bits |= u_privMask->prv$l_l2_bits;7 /* Export ARB if the current PSB is the only one in user node */3 EXE$PERSONA_EXPORT_ARB (ISS$C_ARB_UNSPECIFIED); return SS$_NORMAL;} '#pragma inline ($psb$restore_privilege)Rstatic int $psb$restore_privilege (const PRVDEF *u_savedPriv, PSB_ps const u_psb, H KTB *const u_ktb, const int u_acmode){ PSB_ps psb; PRVDEF *prv; int status; /*< * Set up our psb pointer from user supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return status; /* * Restore privilege mask */ prv = &psb->psb$q_workpriv;4 prv->prv$l_l1_bits = u_savedPriv->prv$l_l1_bits;4 prv->prv$l_l2_bits = u_savedPriv->prv$l_l2_bits;7 /* Export ARB if the current PSB is the only one in user node */3 EXE$PERSONA_EXPORT_ARB (ISS$C_ARB_UNSPECIFIED); return SS$_NORMAL;} /*++ * D E S C R I P T I O N * =====================B * Privilege test macro. This macro is used to test the state of E * privilege bits for the current persona. This macro is usable only * from kernel mode. *D * This privilege testing macro does not perform auditing of the useA * of privilege and should only be used in circumstances where an0 * audit would be inappropriate (which are few). *G * If more than a single privilege bit is being tested, then this macro= * will return TRUE if any of the privilege bits are enabled. *< * The following is the intended usage style for this macro: * * PRVDEF privMask; *> * if ($psb$privilege_enabled (&privMask, psb, ktb, acmode)) * { * ... * } * * N O T E S * =========A * These macros operate on the current persona. Failure to take H * appropriate steps to localize this operation (such as first creating I * a cloned persona)  will result in leakage of the actions of this macro 7 * to all other execution threads sharing this persona. *H * Since these macros operate on the current persona, the most efficientA * argument that can be supplied by a caller is the psb argument.@ * If the psb argument is omitted, then the next most efficient  * argument is the ktb address. *D * The acmode argument must be supplied if any lazy assume performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF  * context of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PREVIOUS (-1) will cause the + * previous mode to be fetched by the code. *D * The privMask argument is the address of a quadword privilege mask * containing bits to be tested. * * U S A G E * =========7 * $psb$privilege_enabled Privilege enabled test *3 * privMask address of privileges maskB * psb optional PSB (default is current pers ona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *M * If unknown, the psb and ktb arguments must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */'#pragma inline ($psb$privilege_enabled)Qstatic int $psb$privilege_enabled (const PRVDEF *u_privMask, PSB_ps const u_psb, H KTB *const u_ktb, const int u_acmode){ PSB_ps psb; PRVDEF privs; PRVDEF *prv1; PRVDEF *prv2; int status; /*< * Set up our psb pointer from user supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return ___FALSE___; /*( * Compute current active privileges */ prv1 = &psb->psb$q_workpriv;& prv2 = &psb->psb$q_image_workpriv;D privs.prv$l_l1_bits = prv1->prv$l_l1_bits | prv2->prv$l_l1_bits;D privs.prv$l_l2_bits = prv1->prv$l_l2_bits | prv2->prv$l_l2_bits; /*0 * And requested privs against computed mask */5 privs.prv$l_l1_bits &= u_privMask->prv$l_l1_bits;5 privs.prv$l_l2_bits &= u_privMask->prv$l_l2_bits; /*8 * If any bits are left in the mask then return true */A if ((privs.prv$l_l1_bits != 0) || (privs.prv$l_l2_bits != 0)) return ___TRUE___; else return ___FALSE___;} /*++B * Account access macros. This macro provides the ability to readB * the account field of the persona block while hiding the overallC * structure of the implementation. This macro is usable only from * kernel mode. *< * The following is the intended usage style for this macro: *- * char account [PSB$K_SIZE_ACCOUNT]; *M * status = $psb$get_account (&account, sizeof(account), psb, ktb, acmode); * if (status) * { * ... * } * else * persona assume error; * * N O T E S * =========. * This macro operates on the current persona. *G * Since this macro operates on the current persona, the most efficientA * argument that can be supplied by a caller is the psb argument.@ * If the psb argument is omitted, then the next most efficient  * argument is the ktb address. *D * The acmode argument must be supplied if any lazy assume performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF * context of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PREVIOUS (-1) will cause the + * previous mode to be fetched by the code. *C * The account argument is the address of the buffer into which the$ * account string should be fetched. *7 * The size argument is the size of the account buffer. * * U S A G E * =========5 * $PSB$GET_ACCOUNT Fetch account string *L * account address of buffer to receive co py of account string: * size size of buffer for account stringB * psb optional PSB (default is current persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *M * If unknown, the psb and ktb arguments must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */!#pragma inline ($psb$get_account)Rstatic int $psb$get_account (char *u_account, const int size, PSB_ps const u_psb, B KTB *const u_ktb, const int u_acmode){ int i; PSB_ps psb; int status; /*< * Set up our psb pointer from user supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return status; /*) * Copy the string into user's buffer */Z ___memcpy_and_fill___ (u_account, size, &psb->psb$t_account, PSB$K_SIZE_ACCOUNT, ' '); return SS$_NORMAL;} /*++C * Account access macros. This macro provides the ability to writeB * the account field of the persona block while hiding the overallC * structure of the implementation. This macro is usable only from * kernel mode. *< * The following is the intended usage style for this macro: *- * char account [PSB$K_SIZE_ACCOUNT]; *V * status = $psb$set_account (&account, sizeof(account), context, psb, ktb, acmode); * if (status) * { * ... * } * else * persona assume error; * * N O T E S * =========@ * This macro operates on the current persona. Failure to take H * appropriate steps to localize this operation (such as first creating I * a cloned persona) will result in leakage of the actions of this macro 7 * to all other execution threads sharing this persona. *G * Since this macro operates on the current persona, the m ost efficientA * argument that can be supplied by a caller is the psb argument.@ * If the psb argument is omitted, then the next most efficient  * argument is the ktb address. *D * The acmode argument must be supplied if any lazy assume performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF * context of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PREVIOUS (-1) will cause the + * previous mode to be fetched by the code. *C * The account argument is the address of the buffer into which the$ * account string should be fetched. *7 * The size argument is the size of the account buffer. *E * The context argument is an indication as to which fields should beE * updated with the account string. If this argument is specified asG * CONTEXT_PERSONA then only the persona block is updated; if specifiedH * as CONTEXT_PROCESS then the JIB and CTL cells are updated in addition * to the persona block.  * * U S A G E * =========3 * $PSB$SET_ACCOUNT Set account string *D * account address of buffer containing account stringA * size size of account string within the bufferB * context context of operation (default is persona)B * psb optional PSB (default is current persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *M * If unknown, the psb and ktb arguments must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */!#pragma inline ($psb$set_account)Wstatic int $psb$set_account (const char *u_account, const int size, const int context, V PSB_ps const u_psb, KTB *const u_ktb, const int u_acmode){ int i; KTB *ktb; PSB_ps psb; int status; /*I * If modifying process level data then make sure we know ktb and psb */# if (context == CONTEXT_PROCESS) { /*; * Set up our ktb pointer (needed later to get jib) */& ktb = ___setup_ktb___ (u_ktb); /*R * Set up our psb pointer from user supplied information (and ktb pointer) */> status = ___setup_psb___ (&psb, u_psb, ktb, u_acmode);# if (!___success___(status)) return status; } /*( * Otherwise just set up psb pointer */ else { /*@ * Set up our psb pointer from user supplied information */@ status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode);# if (!___success___(status)) return status; } /*# * Copy the string into the PSB */Z ___memcpy_and_fill___ (&psb->psb$t_account, PSB$K_SIZE_ACCOUNT, u_account, size, ' '); /*2 * Performing modification for entire process? */# if (context == CONTEXT_PROCESS) { JIB *jib;? extern char ctl$t_account [JIB$K_SIZE_ACCOUNT]; /*& * Pick up current JIB address */ jib = ktb->ktb$l_jib; /*' * Copy the string into the JIB */H ___memcpy_and_fill___ (&jib->jib$t_account, JIB$K_SIZE_ACCOUNT, M &psb->psb$t_account, PSB$K_SIZE_ACCOUNT, ' '); /*. * Copy the string into the CTL region */B ___memcpy_and_fill___ (ctl$t_account, JIB$K_SIZE_ACCOUNT, M &psb->psb$t_account, PSB$K_SIZE_ACCOUNT, ' '); } return SS$_NORMAL;} /*++C * Username access macros. This macro provides the ability to readC * the username field of the persona block while hiding the overallC * structure of the implementation. This macro is usable only from * kernel mode. *< * The following is the intended usage style for this macro: */ * char username [PSB$K_SIZE_USERNAME]; *P * status = $psb$get_username (&username, sizeof(username), psb, ktb, acmode); * if (status) * { * ... * } * else * persona assume error; * * N O T E S * =========. * This macro operates on the current persona. *G * Since this macro operates on the current persona, the most efficientA * argument that can be supplied by a caller is the psb argument.@ *  If the psb argument is omitted, then the next most efficient  * argument is the ktb address. *D * The acmode argument must be supplied if any lazy assume performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF * context of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PREVIOUS (-1) will cause the + * previous mode to be fetched by the code. *D * The username argument is the address of the buffer into which the%  * username string should be fetched. *8 * The size argument is the size of the username buffer. * * U S A G E * =========6 * $PSB$GET_USERNAME Fetch username string *M * username address of buffer to receive copy of username string; * size size of buffer for username stringB * psb optional PSB (default is current persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *M * If unknown, the psb and ktb arguments must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */"#pragma inline ($psb$get_username)@static int $psb$get_username (char *u_username, const int size, W PSB_ps const u_psb, KTB *const u_ktb, const int u_acmode){ int i; PSB_ps psb; int status; /*< * Set up our psb pointer from user supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return status; /*) * Copy the string into user's buffer */] ___memcpy_and_fill___ (u_username, size, &psb->psb$t_username, PSB$K_SIZE_USERNAME, ' '); return SS$_NORMAL;} /*++D * Username access macros. This macro provides the ability to writeC * the username field of the persona block while hiding the overallC * structure of the implementation. This macro is usable only from * kernel mode. *< * The following is the intended usage style for this macro: */ * char username [PSB$K_SIZE_USERNAME]; *P * status = $psb$set_username (&username, sizeof(username), psb, ktb, acmode); * if (status) * { * ... * } * else * persona assume error; * * N O T E S * =========@ * This macro operates on the current persona. Failure to take H * appropr iate steps to localize this operation (such as first creating I * a cloned persona) will result in leakage of the actions of this macro 7 * to all other execution threads sharing this persona. *G * Since this macro operates on the current persona, the most efficientA * argument that can be supplied by a caller is the psb argument.@ * If the psb argument is omitted, then the next most efficient  * argument is the ktb address. *D * The acmode argument must be supplied if any lazy assume  performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF * context of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PREVIOUS (-1) will cause the + * previous mode to be fetched by the code. *D * The username argument is the address of the buffer into which the% * username string should be fetched. *8 * The size argument is the size of the username buffer. *E * The context argument is an indication as to which f ields should beF * updated with the username string. If this argument is specified asG * CONTEXT_PERSONA then only the persona block is updated; if specifiedH * as CONTEXT_PROCESS then the JIB and CTL cells are updated in addition * to the persona block. * * U S A G E * =========4 * $PSB$SET_USERNAME Set username string *E * username address of buffer containing username stringB * size size of username string within the bufferB * con text context of operation (default is persona)B * psb optional PSB (default is current persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *M * If unknown, the psb and ktb arguments must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */"#pragma inline ($psb$set_username)Ystatic int $psb$set_username (const char *u_username, const int size, const int context, W PSB_ps const u_psb, KTB *const u_ktb, const int u_acmode){ int i; KTB *ktb; PSB_ps psb; int status; /*I * If modifying process level data then make sure we know ktb and psb */# if (context == CONTEXT_PROCESS) { /*; * Set up our ktb pointer (needed later to get jib) */& ktb = ___setup_ktb___ (u_ktb); /*R * Set up our psb pointer from user supplied information (and ktb pointer) */> status = ___setup_psb___ (&psb, u_psb, ktb, u_acmode);# if (!___success___(status)) return status; } /*( * Otherwise just set up psb pointer */ else { /*@ * Set up our psb pointer from user supplied information */@ status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode);#  if (!___success___(status)) return status; } /*# * Copy the string into the PSB */] ___memcpy_and_fill___ (&psb->psb$t_username, PSB$K_SIZE_USERNAME, u_username, size, ' '); /*2 * Performing modification for entire process? */# if (context == CONTEXT_PROCESS) { JIB *jib;A extern char ctl$t_username [JIB$K_SIZE_USERNAME]; /*& * Pick up current JIB address */ jib = ktb->ktb$l_jib; /*' * Copy the string into the JIB */J ___memcpy_and_fill___ (&jib->jib$t_username, JIB$K_SIZE_USERNAME, O &psb->psb$t_username, PSB$K_SIZE_USERNAME, ' '); /*. * Copy the string into the CTL region */D ___memcpy_and_fill___ (ctl$t_username, JIB$K_SIZE_USERNAME, O &psb->psb$t_username, PSB$K_SIZE_USERNAME, ' '); } return SS$_NORMAL;} /*++@ * Privs access macros. This macro provides the ability to readB * the current privs of the persona block while hiding the overallC * structure of the implementation. This macro is usable only from * kernel mode. *< * The following is the intended usage style for this macro: * * PRVDEF privMask; * int status; *; * status = $psb$get_privs (&privMask, psb, ktb, acmode); * if (status) * { * ... * } * else *  persona assume error; * * N O T E S * =========. * This macro operates on the current persona. *G * Since this macro operates on the current persona, the most efficientA * argument that can be supplied by a caller is the psb argument.@ * If the psb argument is omitted, then the next most efficient  * argument is the ktb address. *D * The acmode argument must be supplied if any lazy assume performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF * context  of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PREVIOUS (-1) will cause the + * previous mode to be fetched by the code. *D * The privMask argument is the address of a quadword into which the% * privileges mask should be fetched. * * U S A G E * =========1 * $psb$get_privs Fetch privileges *G * privMask address of quadword to receive privileges maskB * psb optional PSB (default is cu rrent persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *M * If unknown, the psb and ktb arguments must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */#pragma inline ($psb$get_privs)Cstatic int $psb$get_privs (PRVDEF *u_privMask, PSB_ps const u_psb, @ KTB *const u_ktb, const int u_acmode){ PSB_ps psb; PRVDEF *prv1; PRVDEF *prv2; int status; /*< * Set up our psb pointer from user supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return status; /*$ * Calculate our privs to return */ prv1 = &psb->psb$q_workpriv;& prv2 = &psb->psb$q_image_workpriv;K u_privMask->prv$l_l1_bits = prv1->prv$l_l1_bits | prv2->prv$l_l1_bits;K u_privMask->prv$l_l2_bits = prv1->prv$l_l2_bits | prv2->prv$l_l2_bits; return SS$_NORMAL;} /*++> * UIC access macros. This macro provides the ability to read> * the UIC field of the persona block while hiding the overall> * structure of the implementation. This macro is usable only * from kernel mode. *< * The following is the intended usage style for this macro: * * int uic; *4 * status = $psb$get_uic (&uic, psb, ktb, acmode); * if (status) * { * ... * } * else * persona assume error; * * N O T E S * =========. * This macro operates on the current persona. *G * Since this macro operates on the current persona, the most efficientA * argument that can be supplied by a caller is the psb argument.@ * If the psb argument is omitted, then the next most efficient  * argument is the ktb address. *D * The acmode argument must be supplied if any lazy assume performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF * context of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PREVIOUS (-1) will cause the + * previous mode to be fetched by the code. *C * The uic argument is the address of a longword into which the uic * is stored. * * U S A G E * =========* * $psb$get_uic Fetch uic *? * uic address of longword to receive the uicB * psb optional PSB (default is current persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *M * If unknown, the psb and ktb arguments must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */#pragma inline ($psb$get_uic)^static int $psb$get_uic (int *u_uic, PSB_ps const u_psb, KTB *const u_ktb, const int u_acmode){ PSB_ps psb; int status; /*< * Set up our psb pointer from user supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return status; /*% * Pick up uic from persona block */ *u_uic = psb->psb$l_uic; return SS$_NORMAL;} /*++? * UIC access macros. This macro provides the ability to write> * the UIC field of the persona block while hiding the overall> * structure of the implementation. This macro is usable only * from kernel mode. *< * The following is the intended usage style for this macro: * * int uic; *3 * status = $psb$set_uic (uic, psb, ktb, acmode); * if (status) * { * ... * } * else * persona assume error; * * N O T E S * =========. * This macro operates on the current persona. *G * Since this macro operates on the current persona, the most efficientA * argument that can be supplied by a caller is the psb argument.@ * If the psb argument is omitted, then the next most efficient  * argument is the ktb address. *D * The acmode argument must be supplied if any lazy assume performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF * context of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PREVIOUS (-1) will cause the + * previous mode to be fetched by the code. *G * The uic argument is the address of a longword which contains the uic * to be set.  * * U S A G E * =========( * $psb$set_uic Set uic *? * uic address of longword containing the uicB * psb optional PSB (default is current persona)H * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *M * If unknown, the psb and ktb arguments must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */#pragma inline ($psb$set_uic)cstatic int $psb$set_uic (const int u_uic, PSB_ps const u_psb, KTB *const u_ktb, const int u_acmode){ PSB_ps psb; int status; /*< * Set up our psb pointer from user supplied information */< status = ___setup_psb___ (&psb, u_psb, u_ktb, u_acmode); if (!___success___(status)) return status; /*! * Store uic in persona block  */ psb->psb$l_uic = u_uic;7 /* Export ARB if the current PSB is the only one in user node */3 EXE$PERSONA_EXPORT_ARB (ISS$C_ARB_UNSPECIFIED); return SS$_NORMAL;} /*++F * Macro to get address of current persona block. This macro handles E * the need to perform a lazy persona assume if the persona id in theG * per-thread kernel area indicates an implicit persona context switch.F * The value returned by the macro is an indication of a successful orF * failed attempt to assume a persona. The invoker of this macro must * be in kernel mode. *< * The following is the intended usage style for this macro: * * PSB *psb; * int status; *- * status = get_curpsb (&psb, ktb, acmode); * if (status) * { * ...; * } * else * persona assume error; * * N O T E S * =========G * The psb argument is the address of a location into which the current3 * persona's persona block address w ill be written. *E * If known, the ktb address should be supplied. Otherwise the macro@ * generates code to determine the current thread's ktb address. *D * The acmode argument must be supplied if any lazy assume performedF * by get_curpsb (used if psb is omitted) needs to be performed in theF * context of a different mode other than the previous execution mode.D * Specifying an access mode of ACMODE_PREVIOUS (-1) will cause the + * previous mode to be fetched by the code. * * U S A G E * =========0 * get_curpsb Get current psb *M * psb address of longword to receive persona block addressH * ktb optional KTB (default is current kernel thread)S * acmode optional access mode for lazy assume (default is PREVIOUS) *D * If unknown, the ktb argument must be specified as NULL (0), andC * the acmode argument must be specified as ACMODE_PREVIOUS (-1). *-- */#pragma inline (get_curpsb)Lstatic int get_curpsb (PSB_ps *u_psb, KTB *const u_ktb, const int u_acmode) { /*? * If we didn't receive a ktb address as input then pass 0,( * otherwise use what was specified. */ if (u_ktb == (void *) 0)/ return NSA_STD$GET_CURRENT_PSB(0, u_psb ); else/ return NSA_STD$GET_CURRENT_PSB(u_ktb, u_psb );}#ifdef __INITIAL_POINTER_SIZE)#pragma __required_pointer_size __restore#endif%#endif /* __SECURITY_MACROS_LOADED */#if 0h $has_priv (pri v, prvmsk, mask = current, message, msgcod, itmlst, altprv, flags, acmode = unknown) =#endifwwJZU /* module SHSBA_ROUTINES.H "X-3"*J *************************************************************************J * *J * Copyright 2004 Hewlett-Packard Development Company, L.P. *J * *J * Confidential computer software. Valid license from HP and/or *J * its subsidiaries required for possession, use, or copying. *J * *J * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, *J * Computer Software Documentation, and Technical Data for Commercial *J * Items are licensed to the U.S. Government under vendor's standard *J * commercial license. *J *  *J * Neither HP nor any of its subsidiaries shall be liable for technical *J * or editorial errors or omissions contained herein. The information *J * in this document is provided "as is" without warranty of any kind and *J * is subject to change without notice. The warranties for HP products *J * are set forth in the express limited warranty statements accompanying *J * such products. Nothing herein should be construed as constituting an *J * additional warranty. *J * *J **************************************************************************++ * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* >* This module contains the C function prototypes for the fPars* shared SBA routines.* * AUTHOR:* * Karen L. Noel* * CREATION DATE: 15-Jan-2004* * MODIFICATION HISTORY:*** X-3 DEE0937 David E. Eiche 18-Jan-20057* Add support for pathname form of shared SBA services.*** X-2 DEE0927 David E. Eiche 03-Nov-2004.* o Add resource ID and status return symbols.8* o KLN: Fix interface for shsba$invalidate_io_ranges().*)* X-1 KLNxxxx Karen L. Noel 15-Jan-2004* Initial checkin.***--*/ #ifndef __SHSBA__ROUTINES_LOADED"#define __SHSBA__ROUTINES_LOADED 1&#pragma __required_pointer_size __save&#pragma __required_pointer_size __long/*G* Define all types that are used in the following function prototypes.*/#include #include /*7* Define symbols used by more than one shared SBA call*/#define SHSBA$K_RSRC_IOPDIR 0#define SHSBA$K_RSRC_IOVA 1!#define SHSBA$K_RSRC_IOTLB_PAGE 2!#define SHSBA$K_RSRC_SEGMENT_CT 3#define SHSBA$K_ALLROPES (-1)/* 1* Declare routines called from within this module*//uint64 exe$call_shsba_service (uint64 func_id,  uint64 arg1,  uint64 arg2,  uint64 arg3,  uint64 arg4,  uint64 * ret1,  uint64 * ret2);/** Static function definitions*/!#define SHSBA$K_GET_IOPDIR_INFO 29static uint64 shsba$get_iopdir_info (uint64 sba_number,  uint64 resource_seg, ! uint64 resource_subseg,  uint64 resource_type, uint64 * ret_base,  uint64 * ret_size){ return (> exe$call_shsba_service (SHSBA$K_GET_IOPDIR_INFO, sba_number, 0 resource_seg, resource_subseg, resource_type,  ret_base, ret_size) );}&#define SHSBA$K_INVALIDATE_IO_RANGES 3=static uint64 shsba$invalidate_io_ranges (uint64 sba_number,  uint64 resource_seg, void * iova_addr,  uint64 size){ return (7 exe$call_shsba_service (SHSBA$K_INVALIDATE_IO_RANGES, ; sba_number, resource_seg, (uint64) iova_addr, size, 0, 0) );}&#define SHSBA$K_GET_HANDLE_FROM_PATH 5=static uint64 shsba$get_handle_from_path( uchar * path_name, uint64 * ret_handle){ return (7 exe$call_shsba_service (SHSBA$K_GET_HANDLE_FROM_PATH, - (uint64) path_name, 0, 0, 0, ret_handle, 0) );})#define SHSBA$K_GET_PDIR_INFO_BY_HANDLE 6=static uint64 shsba$get_pdir_info_by_handle (uint64 handle,! uint64 resource_type, uint64 * ret_base,  uint64 * ret_size){ return (B exe$call_shsba_service (SHSBA$K_GET_PDIR_INFO_BY_HANDLE, handle, * resource_type, 0, 0, ret_base, ret_size) );}-#define SHSBA$K_INVALIDATE_RANGES_BY_HANDLE 7@static uint64 shsba$invalidate_ranges_by_handle (uint64 handle,  void * iova_addr,  uint64 size){ return (> exe$call_shsba_service (SHSBA$K_INVALIDATE_RANGES_BY_HANDLE, , handle, (uint64) iova_addr, size, 0, 0, 0) );})#pragma __required_pointer_size __restore$#endif /* __SHSBA_ROUTINES_LOADED */wwZU/**I*************************************************************************I* *I* HPE CONFIDENTIAL. This software is confidential proprietary software *I* licensed by Hewlett Packard Enterprise Development, LP, and is not *I* authorized to be used, duplicated or disclosed to anyone without the *I* prior written permission of HPE. *I* Copyright 2018 Hewlett Packard Enterprise Development, LP *I*  *I* VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *I* proprietary software licensed by VMS Software, Inc., and is not *I* authorized to be used, duplicated or disclosed to anyone without *I* the prior written permission of VMS Software, Inc. *I* Copyright 2019 VMS Software, Inc. *I*  *I************************************************************************** *++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* C* This module contains the C function prototypes for the VMS systemB* routines that begin with the SMP$ and SMP_STD$ prefixes and have* a standard call interface.* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by eit her using allI* lowercase or all uppercase names for the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by reference. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:**  UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.* * * AUTHOR:* * Leonard S. Szubowicz* * CREATION DATE: 6-Jun-1993* * MODIFICATION HISTORY:* (* X-15 MJM Michael Moroney 20-Mar-20195* Make smp$create_spinlock and smp$name_spinlock use"* variable length argument lists.*** X-14 RAB Richard A. Bishop 31-Oct-2007* Add SMP$REMOVE_SPINLOCK*** X-13 RAB Richard A. Bishop 27-May-20035* Remove local declarations for SPL$S_NAME and _spl,"* as they are included in SPLDEF.* +* X-12 CJ Charles Jaojaroenkul 17-Jul-2002;* Add prototype declarations for new spinlock manipulation;* functions smp$create_spinlock() and smp$name_spinlock().* (* X-11 JRK393 Jim Kauffman 26-Jul-2001* Add support for CPU hot-add*$* X-10 TJP Tom Provost 15-OCT-1999/* Add prototype for allocate portlock routine* (* X-9 CMOS Christian Moser 16-AUG-1999<* Add prototypes for sharelock and nospin locking routines.*'* X-8 JRK390 Jim Kauffman 27-Aug-1998$* Fix naming of IOSBDEF header file*'* X-7 JRK390 Jim Kauffman 22-Jun-19982* Fix parameters to smp$validate_hw_configuration*-* X-6 KLN2082 Karen L. Noel 04-Jun-1998@* Surround this file with short pointer pragmas in case someone=* wants to compile with long pointers from the command line.*'* X-5 JRK390 Jim Kauffman 10-Apr-1998* Remove smp$allocate_ctd*'* X-4 JRK390 Jim Kauffman 3-Apr-1998/* Add CPU migration and communication routines*'* X-3 JRK390 Jim Kauffman 12-Mar-1998(* Add potential set validation routines*'* X-2 JRK390 Jim Kauffman 13-Feb-19981* Extra routines used for config tree and Galaxy*0* X-1 LSS0279 Leonard S. Szubowicz 6-Jun-1993@* Initial version containing only those routines commonly used* by device drivers.* *--*/ #ifndef __SMP_ROUTINES_LOADED#define __SMP_ROUTINES_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define all types that are used in the following function prototypes.*/#include #include #include /*P VMS system routine entry points are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/*#define smp_std$acqnoipl SMP_STD$ACQNOIPL)#define smp_std$acquire SMP_STD$ACQUIRE*#define smp_std$acquir el SMP_STD$ACQUIREL2#define smp_std$acqnoipl_shr SMP_STD$ACQNOIPL_SHR0#define smp_std$acquire_shr SMP_STD$ACQUIRE_SHR2#define smp_std$acquirel_shr SMP_STD$ACQUIREL_SHR8#define smp_std$acqnoipl_nospin SMP_STD$ACQNOIPL_NOSPIN6#define smp_std$acquire_nospin SMP_STD$ACQUIRE_NOSPIN8#define smp_std$acquirel_nospin SMP_STD$ACQUIREL_NOSPIN?#define smp_std$acqnoipl_shr_nospin SMP_STD$ACQNOIPL_SHR_NOSPIN=#define smp_std$acquire_shr_nospin SMP_STD$ACQUIRE_SHR_NOSPIN?#define smp_std$acquirel_shr _nospin SMP_STD$ACQUIREL_SHR_NOSPIN;#define smp_std$allocate_portlock SMP_STD$ALLOCATE_PORTLOCK4#define smp_std$cvt_to_shared SMP_STD$CVT_TO_SHARED,#define smp_std$cvt_to_ex SMP_STD$CVT_TO_EX)#define smp_std$release SMP_STD$RELEASE*#define smp_std$releasel SMP_STD$RELEASEL)#define smp_std$restore SMP_STD$RESTORE*#define smp_std$restorel SMP_STD$RESTOREL0#define smp_std$release_shr SMP_STD$RELEASE_SHR2#define smp_std$releasel_shr SMP_STD$RELEASEL_SHR0#define smp_std$restore_shr  SMP_STD$RESTORE_SHR2#define smp_std$restorel_shr SMP_STD$RESTOREL_SHR,#define smp_std$setup_cpu SMP_STD$SETUP_CPU5#define smp$cpu_orphan_check SMP$CPU_ORPHAN_CHECK=#define smp$request_shutdown_cpu SMP$REQUEST_SHUTDOWN_CPU;#define smp$system_event_notify SMP$SYSTEM_EVENT_NOTIFY%#define smp$timeout SMP$TIMEOUTG#define smp$validate_hw_configuration SMP$VALIDATE_HW_CONFIGURATION/*N Function prototypes for system routines with the SMP$ and SMP_STD$ prefix.*/ "void smp_std$acqnoipl (SPL *spl);&void smp_std$acquire (int spl_index);"void smp_std$acquirel (SPL *spl);)int smp_std$acqnoipl_nospin (SPL *spl);-int smp_std$acquire_nospin (int spl_index);)int smp_std$acquirel_nospin (SPL *spl);&void smp_std$acqnoipl_shr (SPL *spl);*void smp_std$acquire_shr (int spl_index);&void smp_std$acquirel_shr (SPL *spl);-int smp_std$acqnoipl_shr_nospin (SPL *spl);1int smp_std$acquire_shr_nospin (int spl_index);-int smp_std$acquirel_shr_nos pin (SPL *spl);Dint smp_std$allocate_portlock (int spl_index, SPL **portlock_ptr);'void smp_std$cvt_to_shared (SPL *spl);#int smp_std$cvt_to_ex (SPL *spl);&void smp_std$release (int spl_index);"void smp_std$releasel (SPL *spl);&void smp_std$restore (int spl_index);"void smp_std$restorel (SPL *spl);*void smp_std$release_shr (int spl_index);&void smp_std$releasel_shr (SPL *spl);*void smp_std$restore_shr (int spl_index);&void smp_std$restorel_shr (SPL *spl);%int smp_std$setu p_cpu(int, CTD_PQ);.int smp$cpu_orphan_check(int,uint64,uint64);)int smp$request_shutdown_cpu(int, int);9int smp$system_event_notify(CTD_PQ ctd, int event);void smp$timeout (void);;int smp$validate_hw_configuration(int, char **, char **);dint smp$create_spinlock (SPL **spladdr, unsigned int flags, unsigned int ipl, char lockname[], ...);;int smp$name_spinlock (SPL *spladdr, char lockname[], ...);(void smp$remove_spinlock (SPL *spladdr);R#ifdef __INITIAL_POINTER_S IZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif"#endif /* __SMP_ROUTINES_LOADED */wwZU /* module SWIS_ROUTINES.H "X-15"*M*****************************************************************************M* *M* HP CONFIDENTIAL. This software is confidential proprietary software *M* licensed by Hewlett-Packard Development Company, L.P., and is not *M* authorized to be used, duplicated OR disclosed to anyone without the *M* prior written permission of HP. *M* (c) 2017 Copyright Hewlett-Packard Development Company, L.P. *M* *M* VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *M* proprietary software l icensed by VMS Software, Inc., and is not *M* authorized to be used, duplicated or disclosed to anyone without *M* the prior written permission of VMS Software, Inc. *M* (c) 2019 Copyright VMS Software, Inc. *M* *M******************************************************************************++* * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* B* This module contains the C function prototypes for the VMS (IPF)D* SoftWare Interrupt Services (SWIS) routines which begin withA* SWIS$ and thus are not direct replacements for Alpha PAL calls..* (The latter are in [STARLET_H]PAL_SERVICES).* * NOTE:*>* The conventions used in these function prototypes are:* * 1. CaseK* This header file supports invoking the routines by either using allI* lowercase or all uppercase names for  the system routines. EitherG* naming convention works even in the presence of the /NAME=AS_IS* compiler switch.** 2. Integer sizeJ* The generic "int" type is used where it doesn't matter whether theK* integer is 32 or 64 bits wide. Thus "int" is the returned value ofJ* most functions and is the type for most integers passed by value. I* However, an unambiguous integer type, e.g. int32, is used for anyI* integer that is passed by referenc e. Also, int64 is used for anyK* integer that is expected to be 64 bits wide even if it is passed by* value.* * 3. TypesP* The function prototypes use the types defined in [SYSLIB]SYS$LIB_C.TLB. =* The definitions of all types used are included below.** 4. Parameter namesN* Parameter names are used in the prototypes. Although they are ignoredK* by the compiler they do provide useful documentation. For example:*@* void ioc_std$reqcom (int iost1, int iost2, UCB *ucb);*7* is used instead of the functionally equivalent:*1* void ioc_std$reqcom (int, int, UCB *);*&* 5. Parameters passed by referenceN* The parameter name includes the "_p" suffix if the parameter is passedO* by reference unless the parameter type implies that it is always passed?* by reference. For example, there is no "_p" suffix in:** UCB *ucb;* int32 iosb[2];*M* since structures and arrays are always passed by reference. However:** int32 *outlen_p;* UCB **new_ucb_p;*K* include the suffix to denote that outlen_p is a pointer to a 32 bitL* integer, and to denote that new_ucb_p is a pointer to a pointer to a* UCB structure.*/* 6. Mixed pointer sizes within one argumentF* If a 64-bit pointer is being passed by reference, the reference to ?* the pointer should also be 64 bits wide to avoid confusion. * For example:* * PTE_PPQ va_pte_p;* VOID_PPQ start_va_p; ** should be used instead of:** PTE_PQ *va_pte_p;* VOID_PQ *start_va_p;* * * AUTHOR:* 8* Copied from SYS_ROUTINES by Leonard S. Szubowicz* Burns Fisher* * CREATION DATE: 10-Jul-2002* * MODIFICATION HISTORY:*)* X-15 RAB Richard A. Bishop 10-May-2019* Add SWIS_STD$SWPCTX_V()*.* X-14 CV-0225 Camiel Vanderhoeven 7-Aug-2018.* swis$swpctx_v only takes a single argument.*/* X-13 CV-0124 Camiel Vanderhoeven 20-Feb-2018** Include for use of KTB type.*/* X-12 CV-0123 Camiel Vanderhoeven 19-Feb-2018%* Use long pointers for xsave/xrstor*/* X-11 CV-0121 Camiel Vanderhoeven 16-Feb-20189* Provide x86 version of swpctx_v, add xsave and xrstor.*/* X-10 CV-0018 Camiel Vanderhoeven 13-Jun-20171* Provide x86 versions, update copyright to VSI.*+* X-9 WBF Burns Fisher 12-Mar-2004* Promote PFN to quadword*+* X-8 CMOS Christian Moser 04-SEP-20035* Add prototype for SWIS$SET_PSR and SWIS$CLEAR_PSR.*,* X-7 KLN3235 Karen L. Noel 28-Feb-2003* Fix proto for swis$get_bsp.*/* X-6 KLN3189 Karen L. Noel 14-Jan-2003* Add swis$get_rid.*+* X-4 WBF Burns Fisher 03-Dec-20026* Move declarations with pointers to the long pointer * section*+* X-3 WBF Burns Fisher 25-Nov-2002-* Add definition of NEXT_AST_MODE data table*+* X-3 WBF Burns Fisher 10-Jul-2002* Add SWIS$GET_HWPCB*-* X-1,2 WBF Burns Fisher 10-Jul-2002* Initial version* *--*/z#if !defined(__SWIS_ROUTINES_LOADED) && !defined(__alpha) /* Verified for IA64 port WBF; x86 port - Camiel Vanderhoeven */ #define __SWIS_ROUTINES_LOADED 1R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/*G* Define all types that are used in the following function prototypes.*/#include #include #include #include #include D#if defined(__ia64) // Verified for x86 port - Camiel Vanderhoeven#include #endifF#if defined(__x86_64) // Verified for x86 port - Camiel Vanderhoeven#include #endif/*P VMS system routine entry points  are defined externally using uppercase names.J The following macros allow the usage of the lowercase versions of theseA names even in the presence of the /NAME=AS_IS compiler switch.*/$#define swis$set_idt SWIS$SET_IDT $#define swis$get_idt SWIS$GET_IDT 9#define swis$get_astsr_asten SWIS$GET_ASTSR_ASTEN(#define swis$raise_ipl SWIS$RAISE_IPL (#define swis$lower_ipl SWIS$LOWER_IPL 6#define swis$get_current_kt_id SWIS$GET_CURRENT_KT_ID6#define swis$set_current_kt_id SWIS$SET_CURRENT_KT_ID6#define swis$get_current_hwpcb SWIS$GET_CURRENT_HWPCBF#if defined(__x86_64) // Verified for x86 port - Camiel Vanderhoeven)#define swis$get_ptbase SWIS$GET_PTBASE)#define swis$set_ptbase SWIS$SET_PTBASE#endifD#if defined(__ia64) // Verified for x86 port - Camiel Vanderhoeven##define swis$get_rid SWIS$GET_RID%#define swis$set_ptbr SWIS$SET_PTBR&#define swis$get_ptbr SWIS$GET_PTBR $#define swis$set_bsp SWIS$SET_BSP $#define swis$get_bsp SWIS$GET_BSP ##define swis$set_psr SWIS$SET_PSR##define swis$get_psr SWIS$GET_PSR#endif*/* Set current hwpcb is called swpctx ! *//*B Function prototypes for system routines with the SWIS$ prefix.*/int swis$get_astsr_asten(void);"int swis$raise_ipl(int targetIPL);"int swis$lower_ipl(int targetIPL);!int swis$get_current_kt_id(void);&void swis$set_current_kt_id(int ktid);D#if defined(__ia64) // Verified for x86 port - Camiel Vanderhoeven'int swis$get_rid (int virtual_region);+uint64 swis$get_ptbr (int virtual_regionx);4void swis$set_ptbr (uint64 pfn,int virtual_regionx); VOID_PQ swis$get_bsp (int mode);-int swis$set_bsp (int mode, VOID_PQ new_bsp);uint64 swis$set_psr (PSR psr); uint64 swis$clear_psr (PSR psr);#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */#endif$HWPCB *swis$get_current_hwpcb(void);V#if defined(__x86_64) // Verified for x86 port - Camiel Vanderhoeven"uint64 swis$get_ptbase (int mode);/void swis$set_ptbase (uint64 ptbase, int mode);void swis$xsave(char* area);void swis$xrstor(char* area);#endifF#if defined(__x86_64) // Verified for x86 port - Camiel Vanderhoeven KTB* swis$swpctx_v(KTB* newktb);,KTB* swis_std$swpctx_v(KTB* newktb, void *);#elif defined(__ia64)#int swis$swpctx_v(HWPCB *newhwpcb);#else#error Needs architectural work#endif,INTERRUP TION_HANDLER_PQ *swis$get_idt(void);FINTERRUPTION_HANDLER_PQ *swis$set_idt(INTERRUPTION_HANDLER_PQ *table);R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif/*J The following data can be used as the initial value of a 256-long arrayJ which, when indexed by the value gotten with swis$get_astasr_asten willK tell you the mode of the next AST that will be delivered (4 means none).*/#define NEXT_AST_MODE_DATA \" {4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4\" ,4,0,4,0,4,0,4,0,4,0,4,0,4,0,4,0\" ,4,4,1,1,4,4,1,1,4,4,1,1,4,4,1,1\" ,4,0,1,0,4,0,1,0,4,0,1,0,4,0,1,0\" ,4,4,4,4,2,2,2,2,4,4,4,4,2,2,2,2\" ,4,0,4,0,2,0,2,0,4,0,4,0,2,0,2,0\" ,4,4,1,1,2,2,1,1,4,4,1,1,2,2,1,1\" ,4,0,1,0,2,0,1,0,4,0,1,0,2,0,1,0\" ,4,4,4,4,4,4,4,4,3,3,3,3,3,3,3,3\" ,4,0,4,0,4,0,4,0,3,0,3,0,3,0,3,0\" ,4,4,1,1,4,4,1,1,3,3,1,1,3,3,1,1\" ,4,0,1,0,4,0,1,0,3,0,1,0,3,0,1,0\" ,4,4,4,4,2,2,2,2,3,3,3,3,2,2,2,2\" ,4,0,4,0,2,0,2,0,3,0,3,0,2,0,2,0\" ,4,4,1,1,2,2,1,1,3,3,1,1,2,2,1,1\" ,4,0,1,0,2,0,1,0,3,0,1,0,2,0,1,0}##endif /* __SWIS_ROUTINES_LOADED */ww4ZU/* module sysap_macros.h "X-4" *K * Copyright Digital Equipment Corporation, 1998; All Rights Reserved.P * Unpublished rights reserved under the copyright laws of the United States. * M * The software contained on this media is proprietary to and embodies theQ * confidenti al technology of Digital Equipment Corporation. Possession, use,O * duplication or dissemination of the software and media is authorized onlyM * pursuant to a valid written license from Digital Equipment Corporation. * L * RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.H * Government is subject to restrictions as set forth in SubparagraphK * (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable. *  *++ * Facility: * * VMS E xecutive (LIB_H) * * Abstract: *N * These are C macros which parallel the functionality of SYSAP_MACROS.MAR.R * The MACRO-32 interface does not follow the Alpha Calling Standard in severalO * ways. Arguments are passed in general registers, which may or may not beR * saved and restored. Results are also passed in general registers additionalN * to R0. For this reason, these macros require the assistance of MACRO-323 * support in addition to the macros themselves.  *O * These macros define the SYSAP interface to Alpha SCS only. SYSAPs shouldE * use the macros in preference to calling SCS$ routines directly. *Q * There three aspects to the resource allocation macros. The first allocatesN * the resource requested but does not stall on failure. The second is theP * ability to call the resource allocation failure stall directly. The thirdM * is the combination of the first two. However, the combination does itsM * resource all ocation request and stall request in MACRO-32 code vice theS * "C" macro. In the case where multiple resources are requested with potential> * stalls for each, only one callback routine is specified. *N * The SYSAP is free to use the base macro and SCS_STALL separately to have6 * complete control over the stalling control flow. *O * The block transfer and message send macros which fork also are built fromP * base macros usable by the SYSAP to control the forking behavior explicitly, * like their resource allocating cousins * * * Author: */ * James M. Blue Creation Date: 22-Mar-1999 * * Modification History: *) * X-4 JMB186 James M. Blue 5-Oct-1999 * Missed a few when doing X-3! *) * X-3 JMB172 James M. Blue 16-Aug-1999B * Remove the CDT argument from the SCS_STD$_* send, receive, andA * map routine calls where the CDT used by the underlying SCS$_*B * routine is acquired from a different source, such as the CDRP. *) * X-2 JMB154 James M. Blue 6-Aug-1999? * Removed unnecessary PDT argument in SCAN_MSGBUF_WAIT macro. *) * X-1 JMB086 James M. Blue 22-Mar-1999 * Initial version. *-- */#ifndef __SYSAP_MACROS_LOADED#define __SYSAP_MACROS_LOADED 1#ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif/* Include files */#include /* *++'  * *** Resource allocation Macros *** * * Overview: *J * An SCS_STALL macro is provided that stalls the SYSAP for the resourceL * indicated by the condition value in status. Use of these macros allowsI * complete control over the placement of fork routine entry points andK * subroutine returns. In the MACRO-32 version of these macros, there isL * the ability to insert an inline .JSB_ENTRY . For this reason, the codeJ * visually appears to flow linearly, in actuality it may be composed ofG * several routine entries. This capability is not available in "C".F * Additionally, the default use of registers is also not available. * * Example: *G * 1) SYSAP choses to use the VAX/SCS emulation version of the macro: * * void sample_scs_interface() * { * ...E * status = ALLOC_MSG_BUF( cdt_p, pdt_p, cdrp_p, ravail_p );M * ; allocate Send buffer, requestingF *  ; a stall if required. TheI * ; routine for the stall return? * ; must be specified. */ * if ( status == SS$_WASSET ) return; * * ;F * ; This is a bit on the deceiving side of things. This canG * ; flow linearly only if the non-stall path is used. If theG * ; stall path was required then this code path must be endedF * ; at  the time of the stall. The resumption will be at theG * ; routine entry point specified. Because the macro is usedH * ; in a form requiring a status return, the required "return"I * ; statement cannot be included in the macro. Thus the callerJ * ; must do it. Note that because this code is executed at IPL,F * ; the caller must exit in order for the resource to become * ; available. * ; * ... * return; * } *+ * 2) SYSAP choses to use the components. * * void sample_scs_interface() * { * ...2 * status = ALLOCMSGBUF( pdt_p, cdrp_p );M * ; allocate Send buffer, but do not> * ; stall on failure.' * if ( status != SS$_NORMAL )M * ; if the resource wasn't allocated * {M * status = SCS _STALL( status, cdt_p, pdt_p, cdrp_p, ravail_p );I * ; attempt to stall in order toB * ; acquire the resource.3 * if ( status == SS$_WASSET ) return;O * ; If stall activated then exit whileO * ; waiting for the resource to become7 * ; available. * }' * if ( status == SS$_NORMAL )P * ; If the resource was allocated, then * {6 * ravail( status, cdt_p, pdt_p, cdt_p );; * ; go process it. * return; * } * error pathS * ; Otherwise, handle the error condition. * * ... * return; * } * * * NOTE:S *  1. The use of ";" for the comments above is not appropriate to "C",Q * however, this is a "C" module and "C" does not handle imbedded$ * comments. So ...R * 2. The first example could have been used to accomplish the secondQ * as shown in the example. However, the second gives the callerN * control over whether the stall request ever gets activated. *-- */O/********************** SCS Initialization of CDRP **************************** *+ * SCS_INIT_CDRP - *P * This macro initializes SCS cells that must be set to an initial state priorP * to the first call to a SCS service that allocates a resource. The same CDRP? * that is re-used by a SYSAP needs only be initialized once. * * Arguments: * cdrp_p -H * This argument contains a pointer to the CDRP which is being * initialized. * * Return: * None . *- */:#define scs_init_c drp( cdrp_p ) \: ((CDRP *) cdrp_p)->cdrp$q_res_wait_state = 0; \: /* Zero wait state and SCS State */ \: ((CDRP *) cdrp_p)->cdrp$l_bd_addr = 0; \: /* Zero buffer descriptor address */ \: ((CDRP *) cdrp_p)->cdrp$l_rbun = 0; \0 /* Resource bundle pointer */L/**************** Stall of SCS Fork Thread or SYSAP ************************ *+% * SCS_STALL - (non-kernal  process) * M * Stalls a SYSAP or SCS fork thread waiting for a resource. Modeled (veryL * loosely) after FORK, FORK_WAIT and friends. Control is always returnedK * to the caller. The SYSAP's R3, R4, and R5 contents are saved at stallM * entry and restored as arguments along with the status in R0 as arguments * to the RAVAIL_P routine. *K * The overall stall scheme used within the MACRO version of these macrosL * allows for the macro to be executed in-line including  the stall return.O * This is not possible with C. The stall return must be made to an existing * subroutine. *P * The SCS stall linkage is via JSB. A stall condition found in R0 is used toK * determine if a stall will be queued. If the stall is queued, then theQ * contents of R3 (cdt), R4 (pdt), and R5 (cdrp) will be saved in the CDRP forkO * block. It is presumed that R5 will contain a pointer to a CDRP structure.O * Whether a stall is queued or not, a return will be made to the caller. IfN * the returned condition code is SS$_WASSET, then a stall was queued and anQ * immediate return should be made. Note, this macro should only be used after% * an allocation failure situation. * * Arguments * * stall_condition_code -R * This argument contains the status returned by the resource allocation * request. * cdt_p -P * This argument is actually a user defined cell that will be restoredR *  when the user is called at the return entry point. Typically it is a * pointer to the cdt. * pdt_p -P * This argument is actually a user defined cell that will be restoredR * when the user is called at the return entry point. Typically it is a * pointer to the pdt. * cdrp_p -P * This argument contains a pointer to the CDRP for which the resource * is being allocated. * ravail_p -S * This argu ment contains a pointer to the routine to call when the stallS * has completed; if specified as NULL, the routine pointer is assumed to! * be in CDRP$L_FPC(R5) * * Return * * status -Q * The status resulting from the call. Generally, this is a SS$_WASSETO * indicating that the resource wait stall was activated and that theR * caller should unwind and return to it's caller. Otherwise, the inputN * status indicati ng that the resource allocation failed because the3 * error was not due to a wait condition. *P * The arguments for the callback routine (ravail) are the first four argumentO * specified in this macro. If the status continues to be a failure then theQ * resource was not allocated and appropriate action must be taken. Otherwise,Q * the resource is allocated and is indicated by the appropriate cell(s) in the * CDRP being filled. *- */K#define scs_stall( stall _condition_code, cdt_p, pdt_p, cdrp_p, ravail_p ) \Q scs_std$stall( stall_condition_code, cdt_p, pdt_p, cdrp_p, ravail_p )?/************ Stalls During Resource Allocation *************** *H * For purposes of this functionality, stalls refer to those instancesI * where a resource allocation has failed upon initial request and mustH * wait for the resource to become available. The caller may chose to@ * use the stall mechanism to wait or may re-issue the requestI *  periodically. The call is the same whether a stall is authorized orD * not. To authorize a stall action, specify the RAVAIL argument;2 * otherwise, specify it as NULL ( (void *) 0 ). *G * If a stall has been requested and the resource wait is stallable aL * SS$_WASSET will be returned as the status. If this status is returned,7 * the caller must terminate the thread of execution. *? ************ Message Buffer Allocation/Deallocation ********** *+ * ALLOC_MSG_BUF * K * Allocate a sequenced message buffer and the credit to send it, withoutL * stall. If successful (SS$_NORMAL), the application buffer pointer willH * be contained in the CDRP$L_MSGBUF field of the CDRP. Otherwise, anK * error status will be returned. This status will either be a conditionC * resolvable via stall or a fatal error (ie. connection closed). * * Arguments * * pdt_p -Q * This argument contains a pointer to the port descriptor table (PDT).K  * It is required because the buffer allocation is port specific. * cdrp_p -S * This argument contains a pointer to the CDRP for which the resource is@ * being allocated. The following cell must be valid: *1 * CDRP$L_CDT(R5) - Addr of CDT * * ravail_p -S * This argument contains a pointer to the routine to call when the stallO * has completed; if specified as NULL, a stall will not be requestedR *  regardless of allocation request status. A SS$_WASSET status will be= * returned, if a stall was successfully requested. * * Return * * status -Q * The status resulting from the call. Generally, this is a SS$_NORMALN * indicating that the resource was allocated to the caller. If notN * SS$_NORMAL, then it will be either SS$_WASSET indicating that theM * caller should unwind and return to it's caller or a fatal error. * *- */3#define alloc_msg_buf( pdt_p, cdrp_p, ravail_p ) \< scs_std$alloc_msgbuf( pdt_p, cdrp_p, ravail_p )/* *+ * RECYCx_MSG_BUF *H * Recycle a message buffer. This call is used to obtain credit for aH * received message in order to turn it around and send it back to theE * original sender. The two calls wait at high or low priority forG * send credit (if waiting required), where x equals H for high and L * for low. * * Arguments *  * cdt_p -P * This argument is actually a user defined cell that will be restoredR * when the user is called at the return entry point. Typically it is a * pointer to the cdt. * pdt_p -Q * This argument contains a pointer to the port descriptor table (PDT).K * It is required because the buffer allocation is port specific. * cdrp_p -S * This argument contains a pointer to the CDRP for which the resource isB  * being allocated. The following cells must be valid: *1 * CDRP$L_CDT(R5) - Addr of CDT * * ravail_p -S * This argument contains a pointer to the routine to call when the stallO * has completed; if specified as NULL, a stall will not be requestedR * regardless of allocation request status. A SS$_WASSET status will be= * returned, if a stall was successfully requested. * * Return * * status - Q * The status resulting from the call. Generally, this is a SS$_NORMALN * indicating that the resource was allocated to the caller. If notN * SS$_NORMAL, then it will be either SS$_WASSET indicating that theM * caller should unwind and return to it's caller or a fatal error. * *- */3#define recych_msg_buf( pdt_p, cdrp_p, ravail_p ) \9 scs_std$rchmsgbuf( pdt_p, cdrp_p, ravail_p )3#define recycl_msg_buf( pdt_p, cdrp_p, ravail_p ) \9 scs_std$rclmsgbuf( pdt_p, cdrp_p, ravail_p )/* *+ * DEALLOC_MSG_BUF - *E * Deallocates a message buffer and returns associated send credit.B * This will cause any threads waiting for message buffers to be5 * called before control is returned to the caller. * * Arguments * * pdt_p -Q * This argument contains a pointer to the port descriptor table (PDT).K * It is required because the buffer allocation is port specific. * cdrp_p -S * This argument contains a pointer to the CDRP for which the resource is * being deallocated. * * Return * * None. *- */*#define dealloc_msg_buf( pdt_p, cdrp_p ) \0 scs_std$deallocmsg( pdt_p, cdrp_p )/* *+ * DEALLOC_MSG_BUF_REG - *E * Deallocates a message buffer which is not associated with a CDRPE * and returns associated send credit. This will cause any threadsH * waiting for message buffers to be called before control is returned * to the caller. * * Arguments * * msg_buf_p -I * This argument contains a pointer to the message buffer to be * deallocated. * cdt_p -P * This argument contains a pointer to the connection descriptor table * (CDT). * pdt_p -Q * This argument contains a pointer to the port descriptor table (PDT).K * It is required because the buffer allocation is port specific. * * Return * * None. *- */8#define dealloc_msg_buf_reg( msg_buf_p, cdt_p, pdt_p ) \9 scs_std$dealrgmsg( msg_buf_p, cdt_p, pdt_p )/* *+ * RESTORE_CREDIT - *H * Deallocates a send buffer and returns the credit. This is the only= * way to get back send credits without sending the buffer. * * Arguments * * pdt_p -Q * This argument contains a pointer to the port descriptor table (PDT).K *  It is required because the buffer allocation is port specific. * cdrp_p -T * This argument contains a pointer to the CDRP for which the resource was * allocated. * * Return * * None. *- */)#define restore_credit( pdt_p, cdrp_p ) \4 scs_std$restore_credit( pdt_p, cdrp_p )9/************ Datagram Allocation/Deallocation ********** *+ * ALLOC_DG_BUF - *F * Allocates a Datagram buffer, this call does not stall on failure. * * Arguments * * pdt_p -Q * This argument contains a pointer to the port descriptor table (PDT).K * It is required because the buffer allocation is port specific. * cdrp_p -S * This argument contains a pointer to the CDRP for which the resource is * being allocated. * * Return * * status -Q * The status resulting from the call. Generally, this is a SS$_NORMALR * indicating that the datagram was allocated to the caller. Otherwise,S * SS$_INSFMEM, indicating no datagram buffers available and no memory to * make more. *- */'#define alloc_dg_buf( pdt_p, cdrp_p ) \- scs_std$allocdg( pdt_p, cdrp_p )/* *+ * DEALLOC_DG_BUF - *" * Deallocate a datagram buffer. * * Arguments * * dgbuf_p -N * This is a pointer to the application data portion of the datagram& * buffer to be deallocated. * pdt_p -Q * This argument contains a pointer to the port descriptor table (PDT).K * It is required because the buffer allocation is port specific. * * Return * * None. *- */*#define dealloc_dg_buf( dgbuf_p, pdt_p ) \0 scs_std$deallocdg( dgbuf_p, pdt_p )/* *+ * QUEUE_MULT_DGS - *I * Add or subtract datagram buffers from the port's supply of datagrams< * "crediting" the indicated connection for the datagram s. * * Arguments * * buffer_count -P * This argument contains the number of buffers to be added (+ number)# * or removed (- number). * cdt_p -M * This argument contains a pointer the connection descriptor tableO * (CDT). The count of buffers allocated is contained in this table. * pdt_p -Q * This argument contains a pointer to the port descriptor table (PDT).K * It is required because the buffer all ocation is port specific. * buffers_added_p -O * This argument contains a pointer to a cell to receive the count of& * buffers added or removed. * * Return * * status -Q * The status resulting from the call. Generally, this is a SS$_NORMALN * indicating that the resources were added or removed as requested.T * Otherwise, SS$_DGQINCOMP indicating that not all requested buffers were * added or removed. *- */F#define queue_mlt_dgs( buffer_count, cdt_p, pdt_p, buffers_added_p ) \M scs_std$queuemdgs( buffer_count, cdt_p, pdt_p, buffers_added_p )/* *+ * QUEUE_DG_BUF - *= * Add a datagram buffer to the port's supply of datagrams. * * Arguments * * dg_buf_p -O * This argument contains a pointer to the application portion of the* * datagram buffer to be queued. * cdt_p -P * This argument contains a pointer to the connection descriptor tableO * (CDT). The count of buffers allocated is contained in this table. * pdt_p -Q * This argument contains a pointer to the port descriptor table (PDT).K * It is required because the buffer allocation is port specific. * * Return * * status -Q * The status resulting from the call. Generally, this is a SS$_NORMAL@ * indicating that the buffer was queued as requested. *- */0#define  queue_dg_buf( dg_buf_p, cdt_p, pdt_p ) \6 scs_std$queuedg( dg_buf_p, cdt_p, pdt_p )</************ Response ID Allocation/Deallocation ********** *+ * ALLOC_RSPID * * Allocate a RSPID. * * Arguments * * cdt_p -P * This argument is actually a user defined cell that will be restoredP * when the user is called at the return entry point. Typically it is * a pointer to a cdt. * pdt_p -Q * This argument contain !s a pointer to the port descriptor table (PDT).K * It is required because the buffer allocation is port specific. * cdrp_p -P * This argument contains a pointer to the CDRP for which the RSPID is * being allocated. * ravail_p -S * This argument contains a pointer to the routine to call when the stallO * has completed; if specified as NULL, a stall will not be requestedR * regardless of allocation request status. " A SS$_WASSET status will be= * returned, if a stall was successfully requested. * * Return * * status -Q * The status resulting from the call. Generally, this is a SS$_NORMALN * indicating that the resource was allocated to the caller. If notN * SS$_NORMAL, then it will be either SS$_WASSET indicating that theM * caller should unwind and return to it's caller or a fatal error. * *- */7#define alloc_rspid( cdt_p, #pdt_p, cdrp_p, ravail_p ) \B scs_std$alloc_rspid( cdt_p, pdt_p, cdrp_p, ravail_p )/* *+ * RECYCL_RSPID - *Q * "Re-allocates" an existing RSPID (eq. to DEALLOC_RSPID then ALLOC_RSPID, butN * more efficient). This call cannot fail, thus there is no status or stall * capability required. * * Arguments * * cdrp_p -N * This argument contains a pointer to the CDRP containing the RSPID * being recycled. * * Return * *$ None. *- */ #define recycl_rspid( cdrp_p ) \* scs_std$recyl_rspid( cdrp_p ) /* *+ * DEALLOC_RSPID - *A * Deallocate a response id. If there are other RSPID waiters,? * this call will invoke each of their waiting threads before% * returning control to the caller. * * Arguments * * cdrp_p -H * This argument contains a pointer to the CDRP containing the% * RSPID being deallocated. * * Return * * % None. *- */!#define dealloc_rspid( cdrp_p ) \* scs_std$deall_rspid( cdrp_p )G/************ Block transfer mapping Allocation/Deallocation ********** *+ * MAP *N * Allocate mapping registers and map request data. It is presumed that the> * data has already been probed and locked down as required. * * Arguments * * svapte_boff_bcnt_p -M * This argument contains a pointer to a three element array in theO * same order an &d size as CDRP$L_SVAPTE, CDRP$L_BOFF, and CDRP$L_BCNTS * and containing similarly appropriate data for the buffer to be mapped.I * If it is desired to map an IRP, then point to CDRP$L_SVAPTE. * cdt_p -P * This argument is actually a user defined cell that will be restoredR * when the user is called at the return entry point. Typically it is a * pointer to the cdt. * pdt_p -Q * This argument contains a pointer to the ' port descriptor table (PDT).P * It is required because the buffer allocation is port specific. The. * following PDT cell must be valid: *N * PDT$L_BDLT - Address of Buffer Descriptor table for port * * cdrp_p -Q * This argument contains a pointer to the CDRP for which the buffer isC * being mapped. The following CDRP cells must be valid: *. * CDRP$L_CDT - Addr of CDT@ * CDRP$L_LBUFH_ (AD - Addr of SYSAP's buffer handle7 * CDT$L_RCONID - Remote connection ID< * CDRP$L_BD_ADDR - Address of BD if non-zero *I * If input CDRP is an IRP (CDRP$B_TYPE = DYN$C_IRP) then also: *G * CDRP$L_SVAPTE - transfer starting page's PTE address? * CDRP$L_BOFF - transfer byte in page offset9 * CDRP$L_BCNT - transfer size in bytesR * CDRP$B_RMOD - caller's access mode (w/o prote )ction check bit) * * ravail_p -S * This argument contains a pointer to the routine to call when the stallO * has completed; if specified as NULL, a stall will not be requestedR * regardless of allocation request status. A SS$_WASSET status will be= * returned, if a stall was successfully requested. * * Return * * status -Q * The status resulting from the call. Generally, this is a SS$_NORMALN * indicat*ing that the resource was allocated to the caller. If notN * SS$_NORMAL, then it will be either SS$_WASSET indicating that theM * caller should unwind and return to it's caller or a fatal error. * *- */=#define map( svapte_boff_bcnt_p, pdt_p, cdrp_p, ravail_p ) \G scs_std$map( svapte_boff_bcnt_p, pdt_p, cdrp_p, ravail_p )/* *+ * UNMAP - ** * Unmap a buffer for block transfer * * Arguments * * pdt_p -Q * T+his argument contains a pointer to the port descriptor table (PDT).H * It is required because the buffer mapping is port specific. * cdrp_p -P * This argument contains a pointer to the CDRP for which contains the. * buffer handle of the mapped data. * * Return * * None. *- */ #define unmap( pdt_p, cdrp_p ) \+ scs_std$unmap( pdt_p, cdrp_p )>/*************** Connection error cleanup calls ************** *H * Each ,of these macros searchs a resource wait queue (except SCAN_RDTI * which searches the RSPID table) for stalled SYSAP threads associatedG * with the indicated connection (CDT) and calls the specified actionF * routine with the CDRP associated with the stalled thread in CDRP. * * SCAN_MSGBUF_WAIT - *L * Scan message buffer and send credit wait queues for CDRP with given CDT * * Arguments * * action_p -P * This argument contains a pointer to the action ro -utine to be calledP * if a match is found. The action routine is called with the currentL * action_param value, CDT, CDRP. The action routine return is anK * updated or the same action_param value to passed if the action6 * routine is called again during this call. * action_param -O * This argument contains the value to be sent to the action routine. * cdt_p -P * This argument contains a pointer to the connection de.scriptor (CDT) * to be matched. * * Return * * status -7 * The status returned by the action routine. *- */;#define scan_msgbuf_wait( action_p, action_param, cdt_p ) \A scs_std$lkp_msgwait( action_p, action_param, cdt_p )/* *+ * SCAN_RDT - *% * Scan RDT for CDRP with given CDT * * Arguments * * action_p -P * This argument contains a pointer to the action routine to be calledP * i /f a match is found. The action routine is called with the currentL * action_param value, CDT, CDRP. The action routine return is anK * updated or the same action_param value to passed if the action6 * routine is called again during this call. * action_param -O * This argument contains the value to be sent to the action routine. * cdt_p -P * This argument contains a pointer to the connection descriptor (CDT) * to be0 matched. * * Return * * status -7 * The status returned by the action routine. *- */3#define scan_rdt( action_p, action_param, cdt_p ) \A scs_std$lkp_rdtcdrp( action_p, action_param, cdt_p )/* *+ * SCAN_RSPID_WAIT - *2 * Scan RSPID wait queue for CDRP with given CDT * * Arguments * * action_p -P * This argument contains a pointer to the action routine to be calledP * if a match is found. The 1 action routine is called with the currentL * action_param value, CDT, CDRP. The action routine return is anK * updated or the same action_param value to passed if the action6 * routine is called again during this call. * action_param -O * This argument contains the value to be sent to the action routine. * cdt_p -P * This argument contains a pointer to the connection descriptor (CDT) * to be matched. * * Ret2urn * * status -7 * The status returned by the action routine. *- */:#define scan_rspid_wait( action_p, action_param, cdt_p ) \A scs_std$lkp_rdtwait( action_p, action_param, cdt_p )/* *+ * CANCEL_WAIT - *E * Cancel Resource Wait Stall for a CDRP. When a port stalls for aF * resource (message buffer or map registers) some data structure isE * placed on a wait queue. When timeouts fire, a SYSAP may want toC * regain control of t 3he CDRP to cancel the request and retry allC * operations on the controller. The SYSAP invokes this macro toI * cancel the resource wait stall and regain control of the CDRP. ThisJ * replaces the simple REMQUE of the CDRP off the resource wait queue inJ * VAX/VMS. This service is required as it is no longer always the CDRP@ * that is placed on the resource wait queue. This service is/ * synchronous and there is no return status. * * Arguments * * rwcptr_upd - 4K * This argument contains a flag. If set to 1, then any resourceN * wait counters associated with the CDRP amd the cancelled resource. * wait state are to be decremented. * pdt_p -Q * This argument contains a pointer to the port descriptor table (PDT).J * It is required because many resource waits are port specific. * cdrp_p -P * This argument contains a pointer to the CDRP for which contains the. * queue5 for the wait in most cases. * * Return * * status -F * SS$_NORMAL is returned if the cancel was successful. A 0< * indicates no wait state to cancel on this CDRP. *- */2#define cancel_wait( rwcptr_upd, pdt_p, cdrp_p ) \= scs_std$cancel_wait( rwcptr_upd, pdt_p, cdrp_p )./**************** Misc. calls **************** * * FIND_RSPID_RDTE - *9 * Locate and validate the RDTE for a given response ID * * Arguments * * 6 rspid -G * This argument contains the RSPID from the received message1 * for which the RDTE is to be located. * rdte_p -H * This argument is pointer to a pointer to be loaded with theD * found RDTE if the RSPID was valid and the RDTE located. * * Return * * status -F * If set to 1, then RDTE argument contains a pointer to theB * associated RDTE for the RSPID requested, otherwise, 0) * indicat7ing an invalid RSPID. *- */*#define find_rspid_rdte( rspid, rdte_p ) \/ scs_std$find_rdte( rspid, rdte_p )/* *+ * RESUME_RESOURCE_WAITER - *C * Using the data from a CDRP restored using FIND_RSPID_RDTE,B * resume the thread of execution stalled via SCS_STD$STALL. * * Arguments * * resume_status -O * This argument contians the status to be passed the resumed thread. * cdrp_p -P * This argument contains 8a pointer to the CDRP for which contains the" * saved thread context. * * Return * * None. *- */9#define resume_resource_waiter( resume_status, cdrp_p ) \9 scs_std$resumewaitr( resume_status, cdrp_p )/* *+ * RESUME_THREAD - *C * Using the data from a CDRP restored using FIND_RSPID_RDTE,@ * resume the thread of execution stalled as a result of a * data transfer request. * * Arguments * * resume_st9atus -O * This argument contians the status to be passed the resumed thread. * cdrp_p -P * This argument contains a pointer to the CDRP for which contains the" * saved thread context. * * Return * * None. *- */0#define resume_thread( resume_status, cdrp_p ) \; scs_std$resume_thread( resume_status, cdrp_p )0/**************** Configuration Services ******* *+ * CONFIG_PTH - *' * Get path configuration info:rmation * * Arguments * * rmst_lclprt_p -= * This argument contains a pointer to a data blockA * describing the remote station address and local port * name. * pbo_p -C * This argument contains a pointer to a data block to be: * filled with the path block information found. * pb_p -? * This argument contains a pointer to the path block( * containing the information. * * Return *; * status -E * If SS$_NORMAL, then pbo_p contains the path information;E * otherwise, SS$_NOSUCHNODE indicating that no such remote * station exists. *- */2#define config_pth( rmst_lclprt_p, pbo_p, pb_p ) \= scs_std$config_pth( rmst_lclprt_p, pbo_p, pb_p )/* *+ * CONFIG_SYS - *) * Get system configuration information * * Arguments * * scssystemid_p -C * This argument contains a pointer to t<he SCSSYSTEMID to * be located. * sbo_p -C * This argument contains a pointer to a data block to be6 * filled with the system information found. * sb_p -A * This argument contains a pointer to the system block) * containing this information. * * Return * * status -E * If SS$_NORMAL, then sbo_p contains the path information;> * otherwise, SS$_NOSUCHNODE indicating that no such * = SCSSYSTEMID exists. *- */2#define config_sys( scssystemid_p, sbo_p, sb_p ) \= scs_std$config_sys( scssystemid_p, sbo_p, sb_p )/* *+ * POLL_PROC - *0 * Declare a SYSAP name to the process poller. * * Arguments * * notification_p -< * This argument contains a pointer to the routine; * to handle notification when the process poller: * locates the requested SYSAP on a remote node. * context_data_p -< * > This argument contains a caller defined context@ * parameter to be passed to the notification routine. * sysap_name_p -? * This argument contains a pointer to the sysap name' * to be located via polling. * sppb_p -? * This argument contains a pointer that will receive> * a pointer to the SPPB allocated for this process. * * Return * * status -? * SS$_NORMAL indicating that the sysap_name? has been: * decalred to the process poller or SS$_INSFMEMA * indicating that a SCS Process Poller Block could not * be allocated. *- */K#define poll_proc( notification_p, context_data_p, sysap_name_p, sppb_p ) \R scs_std$poll_proc( notification_p, context_data_p, sysap_name_p, sppb_p )/* *+ * POLL_MODE - *4 * Enable process polling for declared SYSAP name. * * Arguments * * enable_disable -G * This argu@ment contains a flag - LBC to disable polling and# * LBS to enable polling. * sppb_p -G * This argument contains a pointer to the SPPB allocated for * this process. * scssystemid_p -A * This argument contains a pointer to the SCSSYSTEMID. * * Return * * status -C * SS$_NORMAL indicating that polling has been enabled or5 * disabled as requested or SS$_NOSUCHNODE. *- */<#define poll_mode(A enable_disable, sppb_p, scssystemid_p ) \C scs_std$poll_mode( enable_disable, sppb_p, scssystemid_p )/* *+ * POLL_MBX - *B * Declare a SYSAP name to the process poller with noticficationG * via mailbox. Note: The IPL cannot be higher than IPL$_ASTDEL (2). * * Arguments * * channel_number -< * This argument contains the channel number of an8 * existing mailbox which is to receive poller * notification. * sysap_nBame_p -? * This argument contains a pointer to the sysap name' * to be located via polling. * sppb_p -? * This argument contains a pointer that will receive> * a pointer to the SPPB allocated for this process. * * Return * * status -? * SS$_NORMAL indicating that the sysap_name has been8 * decalred to the process poller, SS$_INSFMEMA * indicating that a SCS Process Poller Block could not? * C be allocated, or SS$_IVCHAN indicating the mailbox * channel is invalid. *- */:#define poll_mbx( channel_number, sysap_name_p, sppb_p ) \B scs_std$poll_mbx( channel_number, sysap_name_p, sppb_p );/* *+ * CANCEL_MBX - *) * Cancel mailbox polling notification. * * Arguments * * sppb_p -C * This argument contains a pointer to the SPPB allocated * for this process. * * Return * * None. *-D */#define cancel_mbx( sppb_p ) \% scs_std$cancel_mbx( sppb_p )4/*********** Maintenance Functions ***************** *+ * MRESET - *! * Reset remote port and system * * Arguments * * force_flag -D * This argument contains a 0 for do not force reset, 1 to * force a reset. * rstation_p -C * This argument contains a pointer to the remote station- * address of the port to be reset. * pdt_p -ED * This argument contains a pointer to the port descriptor6 * (PDT). This is a port specific function. * * Return * * status -I * SS$_NORMAL to indicate successful request; SS$_NOSUCHNODE to9 * indicate that the remote station is unknown. *- */1#define mreset( force_flag, rstation_p, pdt_p ) \= scs_std$mreset( force_flag, rstation_p, pdt_p );/* *+ * MSTART - *# * Power up remote port and host.F * * Arguments * * boot_flag -G * This argument contains a 0 indicating boot starting at theE * boot address supplied; 1 indicating use the default boot * address. * rstation_p -C * This argument contains a pointer to the remote station1 * address of the port to be restarted. * boot_address -F * This argument contains the boot address to be used if the# * boot flag is set to 0. * G pdt_p -D * This argument contains a pointer to the port descriptor6 * (PDT). This is a port specific function. * * Return * * status -I * SS$_NORMAL to indicate successful request; SS$_NOSUCHNODE to9 * indicate that the remote station is unknown. *- */>#define mstart( boot_flag, rstation_p, boot_address, pdt_p ) \I scs_std$mstart( boot_flag, rstation_p, boot_address, pdt_p )9/************** Connection ManagemenHt Calls ************* *I * These calls are concerned with Establising, Dissolving and obtaining# * information about connections. *K * The SYSAP should check the status following the call and upon entry toJ * the completion routine for errors that prevent sending the connection- * management message at all (Eg. INSFMEM). * *+ * LISTEN - *J * Listen for incoming CONNECT requests. LISTEN returns directly to theD * caller after establishing the listen context orI encountering anL * allocation failure, therefore there is no need of the COMPLETE callback * argument. * * Arguments * * msgadr_p -E * This argument contains a pointer to the routine handling * a connect request. * erradr_p -E * This argument contains a pointer to the routine handling1 * any error conditions that may arise. * lprname_p -G * This argument contains a pointer to the local process name+ J * to be placed in the directory. * prinfo_p -F * This argument contains a pointer to the information about * the local process. * cdt_p -A * This argument contains a pointer to a pointer to the< * connection descriptor assigned to this request. * * Return * * status -F * SS$_NORMAL to indicate successful request, SS$_INSFCDT toF * indicate that the connection descriptor table is full, orKH * SS$_INTERLOCK to indicate that there is no memory available# * for a directory entry. *- */B#define listen( msgadr_p, erradr_p, lprname_p, prinfo_p, cdt_p ) \M scs_std$listen( msgadr_p, erradr_p, lprname_p, prinfo_p, cdt_p )/* *+ * ACCEPT - *! * Accept a connection request. * * Arguments * * msgadr_p -E * This argument contains a pointer to the routine handling% * sequenced message input. * L dgadr_p -E * This argument contains a pointer to the routine handling$ * datagram message input. * erradr_p -E * This argument contains a pointer to the routine handling6 * error conditions such as connection loss. * initcr -I * This argument contains the initial number of receive credits/ * to be extended to the remote node. * minscr -F * This argument contains the minimum number of creditMs by a$ * local process protocol. * initdg -H * This argument contains the number of datagrams to queue for * receive. * blkpri -E * This argument contains the priority for block transfers. * condat_p -E * This argument contains a pointer to the connection data. * auxstr_p -B * This argument contains a pointer to an auxillary data * structure. * badrsp_p -E * This Nargument contains a pointer to the routine handlingE * a bad response message. (Not implemented in SCS at this * time.) * movadr_p -E * This argument contains a pointer to the routine handling7 * a SCS request to move to a different port. * load_rating -D * This argument contains the numeric code for load rating- * associated with this connection. * complete_p -E * This argument contains a poOinter to the routine handlingI * the connection completion. This call is a guaranteed stall. * cdt_p -E * This argument contains a pointer to the CDT passed in by * the Listen request. * cdrp_p -P * This argument is actually a user defined cell that will be restoredR * when the user is called at the return entry point. Typically it is a * pointer to a cdrp. * * Return * * status -C * P SS$_NORMAL to indicate a successful initiation of the K * connect process; NOT completion of the process, SS$_DISCONNECTJ * to indicate that the connection was disconnected, SS$_INSFCDTK * to indicate that no more cdt's could be allocated, SS$_INSFMEMI * to indicate no memory for buffer allocation, SS$_VCBROKEN to8 * indicate that the virtual circuit was lost. * * Note:L * The CDT is specified after the other parameter in order t Qo maintainL * their argument position when the call reaches the MACRO-32 layer ofA * SCS. It is moved to a register for the next layer call. *- */N#define accept( msgadr_p, dgadr_p, erradr_p, initcr, minscr, initdg, blkpri, \F condat_p, auxstr_p, badrsp_p, movadr_p, load_rating, \- complete_p, cdt_p, cdrp_p ) \K scs_std$accept( msgadr_p, dgadr_p, erradr_p, initcr, minscr, \L initdg, blkpri, condat_p, aRuxstr_p, badrsp_p, \T movadr_p, (load_rating ? load_rating : CDT$C_YELLOW), \8 complete_p, cdt_p, cdrp_p )/* *+ * REJECT - *! * Reject a connection request. * * Arguments * * rejtyp -B * This argument contains the reject code to be returned) * to the connection initiator. * cdt_p -F * This argument contains a pointer to the cdt received from * the listen re Squest. * complete_p -E * This argument contains a pointer to the routine handlingD * rejection completion. This call is a guaranteed stall. * cdrp_p -P * This argument is actually a user defined cell that will be restoredP * when the user is called at the return entry point. Typically it is! * a pointer to a cdrp. * * Return * status -C * SS$_NORMAL to indicate a successful initiation of the H * T reject request; NOT completion of the process, SS$_ILLCDTSTG * to indicate that the CDT address is invalid (specifically,D * that it was NULL), or SS$_VCBROKEN to indicate that the& * virtual circuit was lost. *- */5#define reject( rejtyp, cdt_p, complete_p, cdrp_p ) \< scs_std$reject( rejtyp, cdt_p, complete_p, cdrp_p )/* *+ * CONNECT - *@ * Initiate a connect over a virtual circuit to a remote node. * * Arguments * U * msgadr_p -E * This argument contains a pointer to the routine handling% * sequenced message input. * dgadr_p -H * This argument contains a pointer to the routine to handling$ * datagram message input. * erradr_p -H * This argument contains a pointer to the routine to handling6 * error conditions such as connection loss. * rsysid_p -H * This argument contains a pointer to the SCSSYSTEMIDV for the * remote node. * rstadr_p -H * This argument contains a pointer to the station address for * the remote node. *E * (Although both arguments (rsysid_p and rstadr_p) must beJ * specified, only one is required to be non-NULL and valid, the- * other may point to a NULL field. * * rprnam_p -H * This argument contains a pointer to the process name on for * the remote node. * W lprnam_p -H * This argument contains a pointer to the process name on for * the local node. * initcr -I * This argument contains the initial number of receive credits/ * to be extended to the remote node. * minscr -F * This argument contains the minimum number of credits by a$ * local process protocol. * initdg -H * This argument contains the number of datagrams to queue for * recei Xve. * blkpri -E * This argument contains the priority for block transfers. * condat_p -E * This argument contains a pointer to the connection data. * auxstr_p -B * This argument contains a pointer to an auxillary data * structure. * badrsp_p -E * This argument contains a pointer to the routine handlingH * bad response input. (Not implemented in SCS at this time.) * movadr_p -E * Y This argument contains a pointer to the routine handling7 * a SCS request to move to a different port. * load_rating -D * This argument contains the numeric code for load rating- * associated with this connection. * req_fast_recvmsg_p -E * This argument contains a pointer to the routine handlingF * fast path receive message request services. This routineE * returns a int with low bit set indicating that fast p Zath * may proceed. * fast_recvmsg_pm_p -E * This argument contains a pointer to the routine handling0 * the receipt of a fast path message. * change_aff_p -E * This argument contains a pointer to the routine handling * affinity changes. * complete_p -E * This argument contains a pointer to the routine handlingE * connection completion. This call is a guaranteed stall. * connect_param [eter -E * This argument contains an unsigned longword parameter toG * be passed to the connect complete routine. It is not used# * or manipulated by SCS. * * Return * status -C * SS$_NORMAL to indicate a successful initiation of the K * connect process; NOT completion of the process, SS$_DISCONNECTJ * to indicate that the connection was disconnected, SS$_INSFCDTK * to indicate that no more cdt's could be \ allocated, SS$_INSFMEMI * to indicate no memory for buffer allocation, SS$_VCBROKEN to8 * indicate that the virtual circuit was lost. *- */M#define connect( msgadr_p, dgadr_p, erradr_p, rsysid_p, rstadr_p, rprnam_p, \P lprnam_p, initcr, minscr, initdg, blkpri, condat_p, auxstr_p, \G badrsp_p, movadr_p, load_rating, req_fast_recvmsg_p, \S fast_recvmsg_pm_p, change_aff_p, complete_p, connect_parameter ) \L s ]cs_std$connect( msgadr_p, dgadr_p, erradr_p, rsysid_p, rstadr_p, \O rprnam_p, lprnam_p, initcr, minscr, initdg, blkpri, \C condat_p, auxstr_p, badrsp_p, movadr_p, \G (load_rating ? load_rating : CDT$C_YELLOW), \P req_fast_recvmsg_p, fast_recvmsg_pm_p, change_aff_p, \9 complete_p, connect_parameter )/* *+ * DISCONNECT - *A * Remove a connection over a vi^rtual circuit to a remote node. * * Arguments * * distyp -D * This argument contains the disconnect reason code to be) * returned to the remote node. * cdt_p -M * This argument contains a pointer to the CDT for this connection. * complete_p -E * This argument contains a pointer to the routine handlingE * disconnect completion. This call is a guaranteed stall. * disparam -H * This argument _ contains a scalar value to be returned by the+ * disconnect completion routine. * * Return * status -C * SS$_NORMAL to indicate a successful initiation of the ? * disconnect request; NOT completion of the process,C * SS$_ALRDYCLOSED to indicate the connection was alreadyE * closed, SS$_ILLCDTST to indicate that the CDT address isF * invalid (specifically, that it was NULL), or SS$_VCBROKEN; * to indicate` that the virtual circuit was lost. *- */;#define disconnect( distyp, cdt_p, complete_p, disparam ) \B scs_std$disconnect( distyp, cdt_p, complete_p, disparam )/* *+ * SET_LOAD_RATING - *+ * Set a connection's dynamic load rating * * Arguments * * rating -= * This argument contains the new load rating code. * cdt_p -M * This argument contains a pointer to the CDT for this connection. * * Return * * satatus -L * SS$_NORMAL to indicate that rating was changed, SS$_BADPARAM toG * indicate that the rating was out of range, SS$_ILLCDTST to/ * indicate that the CDT was invalid. *- */*#define set_load_rating( rating, cdt_p ) \1 scs_std$set_load_rating( rating, cdt_p )7/************** Block Data Transfer Calls ************* *L * New for Alpha/SCS are three new macros that call the SCS block transferL * routines directly and return to calle br. These macros require the SYSAP1 * already have a CDRP with a MSGBUF and RSPID, *N * Each of the Alpha/SCS block transfer calls include a COMPLETE argument toO * macros for specifying a call back entry when the block transfer completes.M * These macros *Do not* end the current for thread, control is returned to * the caller *J * If the COMPLETE argument is not specified the address of the complete1 * routine must have been stored in CDRP$L_FPC. *L * NOTE: If a CO cMPLETE routine is explicitly specified there is no need toO * check R0 status when called at that routine, it will always be SS$_NORMAL. * *+$ * REQDATA / SENDDATA / SENDDATAWM *O * These Alpha/SCS only macros call the SCS block transfer routines directly,K * the do *not* end the current thread. The SYSAP specifies a completionL * callback routine (COMPLETE argument) if none is specified it is assumed * to be in CDRP$L_FPC. *I * The two block transfer calls differ o dnly in transfer direction. ForL * SENDDATA the contents of the local data buffer (specified by the bufferN * handle @CDRP$L_LBUFH_AD) is transferred to the remote SYSAP's data bufferN * (specified by the buffer handle @CDRP$L_RBUFH_AD, which must be currentlyO * MAP'd by the remote SYSAP) For REQDATA the remote data buffer contents areK * transferred to the local data buffer. It is presumed that a RSPID andA * message buffer have been previously allocated for this CDRP. * * e Arguments * * pdt_p -M * This argument contains a pointer to the PDT for this connection. * cdrp_p -N * This argument contains a pointer to the CDRP for this connection.; * The following cells of the CDRP must be valid: *E * CDRP$L_RSPID - RSPID to use to correlate transferD * completion with initiation threadI * CDRP$L_MSG_BUF - Message buffer to use for xfer command2 * f CDRP$L_XCT_LEN - # bytes to xfer> * CDRP$L_LBUFH_AD - Addr of local buffer handleE * CDRP$L_LBOFF - Local byte offset for segmentation? * CDRP$L_RBUFH_AD - Addr of remote buffer handleF * CDRP$L_RBOFF - Remote byte offset for segmentation *K * In addition, for SENDDATAWM, the following cell must be valid: *L * CDRP$L_CDT - CDT for connection on which the piggyback4 * g message is sent.  * * complete_p -J * This argument contains a pointer to the routine handling send? * data completion. This call is a guaranteed stall. * * Return * * status -@ * Either SS$_NORMAL indicating the request was queued@ * successfully or SS$_ILLCDTST indicating the CDT was * not open. *- */.#define reqdata( pdt_p, cdrp_p, complete_p ) \5 scs_std$reqdata( pdt_p, cdrp_p, comhplete_p )/#define senddata( pdt_p, cdrp_p, complete_p ) \6 scs_std$senddata( pdt_p, cdrp_p, complete_p )1#define senddatawm( pdt_p, cdrp_p, complete_p ) \; scs_std$senddata_wmsg( pdt_p, cdrp_p, complete_p )/* *+. * REQUEST_DATA / SEND_DATA / SEND_DATA_WMSG *C * These macros behave similarly to those above, except that theyC * allocate the necessary RSPID and message buffer as part of the> * call. These requests may result in a stall at any point.D * i However, the caller will only be called at the completion entryB * routine upon final completion either with success or failure. * * Arguments * * msg_buf_len -C * This argument contains the length of the message being; * transmitted. THIS IS FOR SEND_DATA_WMSG ONLY. * pdt_p -M * This argument contains a pointer to the PDT for this connection. * cdrp_p -N * This argument contains a pointer to the CDRP for this connejction. * complete_p -H * This argument contains the address of the routine to handleC * the final completion. This call may generate a stall. * * Return * * status -C * Either SS$_WASSET indicating the request was queued orC * an appropriate error condition for one of the resourceB * allocation routines. See ALLOCMSGBUF, ALLOCRSPID, or/ * RECYCHMSGBUF (for SEND_DATA_WMSG). *- */3#define request_kdata( pdt_p, cdrp_p, complete_p ) \: scs_std$request_data( pdt_p, cdrp_p, complete_p )0#define send_data( pdt_p, cdrp_p, complete_p ) \7 scs_std$send_data( pdt_p, cdrp_p, complete_p )B#define send_data_wmsg( msg_buf_len, pdt_p, cdrp_p, complete_p ) \I scs_std$send_data_wmsg( msg_buf_len, pdt_p, cdrp_p, complete_p )1/************** Datagram Send Calls ************* * * SEND_DG_BUF - * * Send a datagram. * * Arguments * * disposition_f llag -; * This argument indicates the disposition of the< * datagram after it has been sent. SYSAP$C_DISPQ= * indicates return the datagram to the free queue,= * SYSAP$C_DISPRET indicates return the datagram to; * the SYSAP, and SYSAP$C_DISPPO indicates return7 * the datagram to the port for deallocation. * dg_msg_length -< * This argument contains the length of the buffer * to transmit. * cmdrp_p -9 * This argument contains a pointer to the CDRP* * associated with this request. * * Return * * status -: * SS$_NORMAL indicating the request was queued. *- */@#define send_dg_buf( disposition_flag, db_msg_length, cdrp_p ) \B scs_std$senddg( disposition_flag, db_msg_length, cdrp_p )/* *+ * SEND_DG_BUF_REG - *" * Send a datagram without CDRP. * * Arguments * * disposition_flag -; * n This argument indicates the disposition of the< * datagram after it has been sent. SYSAP$C_DISPQ= * indicates return the datagram to the free queue,= * SYSAP$C_DISPRET indicates return the datagram to; * the SYSAP, and SYSAP$C_DISPPO indicates return7 * the datagram to the port for deallocation. * dg_msg_length -< * This argument contains the length of the buffer * to transmit. * dg_buf_p -M * o This argument contains a pointer to the application data portion& * of a datagram to be sent. * cdt_p -M * This argument contains a pointer to the PDT for this connection. * pdt_p -M * This argument contains a pointer to the PDT for this connection. * * Return * * status -: * SS$_NORMAL indicating the request was queued. *- */T#define send_dg_buf_reg( disposition_flag, dg_msg_length, dg_buf_p, cdt_p, pdt_p )p \T scs_std$sendrgdg( disposition_flag, dg_msg_length, dg_buf_p, cdt_p, pdt_p )0/************** Message Send Calls ************* *+ * SENDMSGBUF *M * This macro is used to send a max sized message. If a RSPID is specifiedL * a completion routine entry should be specified in the COMPLETE argumentN * (or be stored in CDRP$L_FPC(R5)). This is a guaranteed stall, if a RSPID= * is specified, thus the caller must terminate the thread. * * Arguments * * p qdt_p -M * This argument contains a pointer to the PDT for this connection. * cdrp_p -N * This argument contains a pointer to the CDRP for this connection./ * The following cells must be valid: *1 * CDRP$L_CDT(R5) - Addr of CDT6 * CDRP$L_MSG_BUF(R5) - Addr of message ; * CDRP$L_RSPID(R5) - RSPID (to set RETFLG) * * complete_p -O * This argument contains a pointer to the routine handlring the finalP * completion. This call is guaranteed stall. This cell will only be+ * used if the RSPID is non-zero. * * Return * * status -C * Either SS$_NORMAL indicating the request was queued or? * SS$_ILLCDTST indicating the connection was closed. *- */1#define sendmsgbuf( pdt_p, cdrp_p, complete_p ) \D scs_std$sendmsg( SCS$GW_MAXMSG, pdt_p, cdrp_p, complete_p )/* *+ * SENDCNTMSGBUF *I * This ma scro is equivelent to SENDMSGBUF except a message size must be? * specified. The jacket for this macro encompasses both theJ * SENDCNTMSGBUF and SEND_CNT_MSG_BUF macros of SYSAP_MACROS.MAR. Thus,J * if there is no RSPID, there is no stall. If no completion routine isJ * specified and one is required, it is anticipated that the address has6 * previously been placed in CDRP$L_FPC of the CDRP. * * Arguments * * buf_size -F * This argument contains the buffer t size to be transmitted. * pdt_p -M * This argument contains a pointer to the PDT for this connection. * cdrp_p -N * This argument contains a pointer to the CDRP for this connection./ * The following cells must be valid: *1 * CDRP$L_CDT(R5) - Addr of CDT6 * CDRP$L_MSG_BUF(R5) - Addr of message ; * CDRP$L_RSPID(R5) - RSPID (to set RETFLG) * * complete_p -O * This argument conutains a pointer to the routine handling the final: * completion. This call is a guaranteed stall. * * Return * * status -C * Either SS$_NORMAL indicating the request was queued or? * SS$_ILLCDTST indicating the connection was closed. *- */>#define sendcntmsgbuf( buf_size, pdt_p, cdrp_p, complete_p ) \? scs_std$sendmsg( buf_size, pdt_p, cdrp_p, complete_p )-/************** Fast Path Calls ************* *9 * Called by a S vYSAP which is attempting Fast Path I/O. * *+ * FAST_SENDMSG_REQUEST - *F * Request a Fast Message Send via Fast Path. This service requestsH * permission from the SCS and port layers to use Fast Path for a fastE * message send. If approval is granted then return status will beH * success and both SCS and the PM spinlock will be held. The SYSAP isH * expected to perform some updates and promptly drop the SCS spinlockH * in favor of the PM spinlock. If permission is de wnied then only theH * SCS spinlock is held and traditional slow path is used for the I/O.1 * A resource bundle is returned on a success.  * * Arguments * * svapte_boff_bcnt_p -M * This is a pointer to a three element array in the same order andO * size as CDRP$L_SVAPTE, CDRP$L_BOFF, and CDRP$L_BCNT and containingN * similarly appropriate data for the buffer to be mapped. If it isN * desired to map an IRP, then point to CDRP$L_SVAPT xE. This is usedI * by the port driver to validate its ability to use fast path. * pdt_p -Y * This argument contains a pointer to the PDT associated with this connection. * cdrp_p -W * This argument contains a pointer to the CDRP containing the mapping buffer * handle to be used. * * Return * * status -Q * If LBS, then SCS and the port can handle this request as a Fast PathM * request and have ma yde the appropriate setup. Else, this requestN * cannot be handled as Fast Path request and must be handled in theN * standard way. If successful (LBS), then both the IPL$_SCS and PMQ * spinlocks are held. The SYSAP should complete any required IPL$_SCSQ * level activity quickly and return the IPL$_SCS spinlock. Otherwise,- * the IPL$_SCS lock is still held. *- */C#define FAST_SENDMSG_REQUEST( svapte_boff_bcnt_p, pdt_p, cdrp_p ) \ zJ scs_std$fast_sendmsg_request( svapte_boff_bcnt_p, pdt_p, cdrp_p )/* *+ * FAST_SENDMSG_ASSOCIATE_PM - *N * Associate RBUN SCS resources to current message. This service associatesN * the RBUN SCS resources to the current request. The RBUN was allocated onO * a previous FAST_SENDMSG_REQUEST call. This service operates entirely underK * port mainline (PM) spinlock synchronization and returns a pointer to a6 * message buffer for the SYSAP to create a message. * { * Arguments * * svapte_boff_bcnt_p -M * This is a pointer to a three element array in the same order andO * size as CDRP$L_SVAPTE, CDRP$L_BOFF, and CDRP$L_BCNT and containingN * similarly appropriate data for the buffer to be mapped. If it isN * desired to map an IRP, then point to CDRP$L_SVAPTE. This is usedI * by the port driver to validate its ability to use fast path. * pdt_p -Y * This argument contains |a pointer to the PDT associated with this connection. * cdrp_p -W * This argument contains a pointer to the CDRP containing the mapping buffer * handle to be used. * * Return * * None. *- */H#define fast_sendmsg_associate_pm( svapte_boff_bcnt_p, pdt_p, cdrp_p ) \M scs_std$fast_sendmsg_ass_res_pm( svapte_boff_bcnt_p, pdt_p, cdrp_p )/* *+ * FAST_SENDMSG_PM *F * Send a message under a port mainline (PM) spinlock. This } serviceC * sends a SYSAP message within Fast Path and executes under a PMH * spinlock instead of the SCS spinlock. The message can for example,H * be a message to a MSCP Server to perform an I/O. On return, the PMF * spinlock has been released so the SYSAP should not do anything on- * return but terminate the current thread. *E * Unlike traditional SENDMSG processing, a SYSAP can only use thisH * service if a response is required (ie. that there is a RSPID in the * CDR~P). * * Arguments * * msg_buf_len -C * This argument contains the length of the message being * transmitted. * cdt_p -P * This argument is actually a user defined cell that will be restoredP * when the user is called at the return entry point. Typically it is * a pointer to a cdt. * pdt_p -Y * This argument contains a pointer to the PDT associated with this connection. * cdrp_p -Y *  This argument contains a pointer to the CDRP containing the RBUN to be used. * complete_p -Q * This argument contains a pointer to the routine handling the request * completion. * * Return * * None. *- */J#define fast_sendmsg_pm( msg_buf_len, cdt_p, pdt_p, cdrp_p, complete_p ) \Q scs_std$fast_sendmsg_pm( msg_buf_len, cdt_p, pdt_p, cdrp_p, complete_p )/* *+ * FAST_RECVMSG_CHECK_RES - *J * Check on RBUN existence  and create one if none. The SYSAP calls thisF * service to check on SCS resources. Currently only the RBUN is ofI * concern here. If the RBUN doesn't exists and a RBUN was wanted thenL * a RBUN is created out of the current I/O's resources. The SCS spinlockK * is held for this routine and if the RBUN cannot be created then use of * Fast Path is denied. * * Arguments * * cdt_p -Y * This argument contains a pointer to the CDT associated with this connection. * pdt_p -Y * This argument contains a pointer to the PDT associated with this connection. * cdrp_p -W * This argument contains a pointer to the CDRP containing the RSPID, message2 * buffer, and buffer handle to be used. * complete_p -Q * This argument contains a pointer to the routine handling the request * completion. * * Return * * Status -L * If LBS, then fast can be used; otherwise the standard path must * used. *- */6#define fast_recvmsg_chk_res( cdt_p, pdt_p, cdrp_p ) \/ ( cdrp_p->cdrp$l_rbun ? SS$_NORMAL : \< ( cdrp_p->cdrp$l_scs_state & cdrp$v_rbun_wanted ? \G scs_std$fast_recvmsg_chk_res( cdt_p, pdt_p, cdrp_p ) : 0 ) )/* *+ * REPO_CDRP - *C * Repossess the CDRP. When a SYSAP sends a message, for which a> * response is expected out over a port, control of the CDRPD * transfers to SCS and the port  driver. However a SYSAP may wishC * to seize control of the CDRP before the response arrives, as aE * result of a connection failure or cancel operation. For a SYSAPF * to regain control of the CDRP before a response comes in for thisD * CDRP, this macro can be invoked on the CDRP. The macro must beE * invoked before any modification or access to and SCS CDRP fieldsB * occur. Only SYSAPs supporting Fast Path need use this macro. * * Arguments * * pdt_p -J *  This argument contains a pointer to the PDT for this request. * cdrp_p -R * This argument contains a pointer to the CDRP that is to be retrieved. * * Return * * None. *- */$#define repo_cdrp( pdt_p, cdrp_p ) \1 scs_std$repossess_cdrp( pdt_p, cdrp_p );#ifdef __cplusplus }#endif"#endif /* __SYSAP_MACROS_LOADED */wwZU)/* Module: SYSTEM_SERVICE_SETUP.H "X-17"*I*************************************************************************I* *I* HPE CONFIDENTIAL. This software is confidential proprietary software *I* licensed by Hewlett Packard Enterprise Development, LP, and is not *I* authorized to be used, duplicated or disclosed to anyone without the *I* prior written permission of HPE. *I* Copyright 2020 Hewlett Packard Enterprise Development, LP *I*  *I* VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *I* proprietary software licensed by VMS Software, Inc., and is not *I* authorized to be used, duplicated or disclosed to anyone without *I* the prior written permission of VMS Software, Inc. *I* Copyright 2020-2021 VMS Software, Inc. *I*  *I***************************************************************************++ * FACILITY:** VMS Executive (LIB)* * ABSTRACT:*L* This header file will do some of the setup necessary for system services.M* It is ONLY for use in setting up change-mode services. If you are creatingL* a mode-of-the-caller system service, it must have a SYS$xxx routine name.M* All callers will use that name. If you are creating a change-mode service,L* then you may have an "internal" name as well as the public, SYS$xxx name.F* You need only create the routine with your internal name and defineN* special symbols (see below) for the name and prefix you're using. Note thatJ* your "internal" routine must be a standard call and should not make anyP* assumptions about where it was called from (like the change-mode dispatcher).*M* Before including this header file, the programmer needs to #define symbolsL* for those routines and how they're called. This is diff erent from how theK* setup works from MACRO or BLISS, where a nice macro takes care of ALL of* the ugly stuff.*J* Multiple inclusions of this header file would introduce padding betweenI* the contributions to the EXEC$INIT_SSTBL_001 PSECT. The system serviceM* loader interprets the padding (a longword of zeroes) as the termination ofN* the system service vector list. To avoid the run-time problems, this headerG* file will generate compile-time errors when included more than once. *K* It is still possible to declare multiple system services from the same CO* module. The symbols must be defined for all such services prior to inclusionM* of this header file so that the initialization can take place all at once.*M* The way you use this include file DOES matter. It can ONLY be invoked fromN* the outer most scope of your C module, and that includes outside of main{}.C* You must also have already declared the system service routines.L* *********************** **************************************************D* This should not be true anymore since we specify these attributesO* (except MOD) in this header file. I left this comment here for posterity soN* you will know why there are all the PSECT_ATTR statements in link commands.* * You mustN* also be sure that the link option file for your image specifies the correctK* PSECT attributes for the EXEC$INIT_SSTBL_001 PSECT. What is generated by6* DECC will NOT be correc t. The attributes should be:*1* LONG,PIC,CON,REL,GBL,NOSHR,EXE,NOWRT,NOVEC,MOD ** L*****************************************************************************H* NOTE: mode-of-caller system services should not use this header file.I* Simply create the SYS$xxx routine in source. If the system service isC* new, it does need a vector in SYS$PUBLIC_VECTORS and an entry in* SYSTEM_SERVICES.M64.*H* The following examples show what to do in your C code to em ulate whatJ* you used to do in MACRO and BLISS (note that the IMASK, FLAGS, and TYPEK* fields are specifying the default values and could be omitted). You mustJ* define several "temporary" symbols prior to including this header file.J* These symbols will be "undefined" by this header file. This header fileD* currently supports up to 5 system service definitions. The symbolM* SYSRVC_NUMBER is defined to be the number of system service vectors needed* (defaults to 1).*0* To setup a single kernel-mode system service:** exe$krnl_sysrvc_rtn()* { }*"* #define SYSRVC_PREFIX_NAME exe$.* #define SYSRVC_ROUTINE_NAME krnl_sysrvc_rtn$* #define SYSRVC_MODE MODE_K_KERNEL* #define SYSRVC_IMASK 129* #define SYSRVC_FLAGS 0$* #define SYSRVC_TYPE TYPE_K_NORMAL"* #include *.* To setup three kernel-mode system services:** exe$krnl_sysrvc_rtn1()* { }* exe$krnl_sysrvc_rtn2()* { }* exe$krnl_sysrvc_rtn3()* { }*"* #define SYSRVC_PREFIX_NAME exe$/* #define SYSRVC_ROUTINE_NAME krnl_sysrvc_rtn1$* #define SYSRVC_MODE MODE_K_KERNEL* #define SYSRVC_IMASK 129* #define SYSRVC_FLAGS 0$* #define SYSRVC_TYPE TYPE_K_NORMAL** #define SYSRVC_NUMBER 2#* #define SYSRVC2_PREFIX_NAME exe$0* #define SYSRVC2_ROUTINE_NAME krnl_sysrvc_rtn2%* #define SYSRVC2_MODE MODE_K_KERNEL* #define SYSRVC2_IMASK 129* #define SYSRVC2_FLAGS 0%* #define SYSRVC2_TYPE TYPE_K_NORMAL** #define SYSRVC_NUMBER 3#* #define SYSRVC3_PREFIX_NAME exe$0* #define SYSRVC3_ROUTINE_NAME krnl_sysrvc_rtn3%* #define SYSRVC3_MODE MODE_K_KERNEL* #define SYSRVC3_IMASK 129* #define SYSRVC3_FLAGS 0%* #define SYSRVC3_TYPE TYPE_K_NORMAL*"* #include *O* This header file includes starlet.h to define the system service prototypes.*P* If a service in the module is in starlet.h, but has a different declaration, M* define __STARLET_LOADED before inluding system_service_setup.h. This will ,* disable all declarations from starlet.h. ** #define __STARLET_LOADED*B* If a service being setup is not in starlet.h or if you defined M* __STARLET_LOADED because of a conflict, declare the service in the source =* module before including system_service_setup.h as follows:*1* int sys$krnl_sysrvc_rtn (proper arguments...);"* #include * * AUTHOR:** Steve DiPirro*"* CREATION DATE: 29-Jan-1993** MODIFICATION HISTORY:*&* X-17 HB Hartmut Becker 7-Dec-20217* Make the system service entries "const" to match the** NOWRT of the exec$init_sstbl_001 PSECT.*(* X-16 CEG0973 Clair Grant 16-Apr-2021#* Make exec$init_sstbl_001 noexe *(* X-15 CEG0963 Clair Grant 28-Mar-2021'* Make exec$init_sstbl_001 nowrt,exe *#* X-14 AHM Drew Mason 13-Jan-20209* Add module IDENT. Update copyright. Add comment that9* this header file should not be used for mode-of-caller * services. *%* X-13 WBF Burns Fisher 8-Jan-2009@* Disable superfluous alignment messages from latest C compiler*)* X-12 GHJ Gregory H. Jordan 9-Apr-2004=* Increase the number of system services that can be defined* to 6.*** X-11 KLN3057 Karen L. Noel 18-Apr-2002<* We can no longer declare sys$ routines without arguments.;* The compiler complains when the declarations don't match<* existing ones. So we define them by including starlet.h. ?* Those services not in starlet.h req uire a definition in the <* source module. Those modules that contain defintions that>* conflict with starlet.h need to define __STARLET_LOADED to $* disable the include of starlet.h.*%* X-10 WBF Burns Fisher 04-Aug-19997* Add psect attributes to the extern psects, since the5* compiler now supports it. That should prevent the4* occasional mysterious system service failures-to-4* load that we see. Problem was that the alignment5* was OCTA if you did not explictly force it to long9* with a PSECT_ATTR statement in the linker. This might:* sometimes cause the linker to insert an extra longword.*)* X-9 KLN2077 Karen L. Noel 21-May-19983* Disable the information about no parameter list.*%* X-8 DMB Dave Bernardo 03-Jan-1996(* Fix bogus characters at end of lines.*%* X-7 DMB Dave Bernardo 20-Dec-19967* Turn the pad longword at the end of a system service4* discriptor into a longword flags field. The FLAGS6* byte still gets the first 8 bits for compatibility.3* The longword field also contains this byte, plus* any new bits above 8.*(* X-6 KLN1400 Karen L. Noel 2-Mar-19958* Change external declarations of sys$ routines to take2* an unknown number of arguments instead of void.*(* X-5 KLN1347 Karen L. Noel 7-Dec-19945* Rename blocks so more than one C module can define+* system services within the same execlet.*C* X-4 SDD Steve DiPirro 20-May-1994-* Fix usage of #error directive*C* X-3 SDD Steve DiPirro 28-Dec-1993F* Use new, modified SSDESCR structure definition in LIB.+* Initialize unused padding field to zero.*C* X-2 SDD Steve DiPirro 15-Sep-1993J* Completed redesigned mechanism for multiple system service<* declarations (since previous one didn't work correctly at,* run-time with the system service loader).**--*/ /*p Some comp ilers warn if an array is allocated on too small an alignment. We must allocate on an exact alignmentR for the init processing to work, so we must do it this way. Disable the warning.*/#pragma message savew#pragma message disable UNKMSGID /* Don't complain about the next line even on compilers without ALIGNNOTSTD message*/##pragma message disable ALIGNNOTSTD/*I We don't want to allow multiple inclusions of this header file since itB will result in run-time problems with the system service loader.*/#ifdef __SYSTEM_SERVICE_SETUP=#error "Cannot include SYSTEM_SERVICE_SETUP.H more than once"#else #define __SYSTEM_SERVICE_SETUP 1#endif#include #define ssxconcat(a,b) a ## b$#define ssconcat(a,b) ssxconcat(a,b)#define SYSRVC_VECTOR_NAME sys$"#define SSDATA_PREFIX sysvec_data_)#define SSDATA_SUFFIX SYSRVC_ROUTINE_NAME/*= Make sure the system service number is something reasonable*/#ifndef SYSRVC_NUMBER#define SYSRVC_NUMBER 1#else#if SYSRVC_NUMBER > 6F#error "Too many system services for this hack header file to support"#endif#endif/*F These are constants which we need defined (and which, luckily, don'tF change much. If they're not defined at this point, we'll define themK here but set a flag to realize we did it and need to undefine them later.*/#ifndef MODE_K_CALLERS_MODE#define __MODE_DEFINED 1#define MODE_K_KERNEL 0#define MODE_K_EXEC 1#define MODE_K_SUPER 2#define MODE_K_USER 3#define MODE_K_CALLERS_MODE 4#endif/*E Setup any defaulted parameters (note that an undefined mode or mode% we don't like will cause an error).*/#ifndef SYSRVC_PREFIX_NAME5#error "System service name prefix must be specified"#endif#if SYSRVC_NUMBER > 1#ifndef SYSRVC2_PREFIX_NAME<#error "Second system service name prefix must be specified"#endif#endif#if SYSRVC_NUMBER > 2#ifndef SYSRVC3_PREFIX_NAME;#error "Third system service name prefix must be specified"#endif#endif#if SYSRVC_NUMBER > 3#ifndef SYSRVC4_PREFIX_NAME<#error "Fourth system service name prefix must be specified"#endif#endif#if SYSRVC_NUMBER > 4#ifndef SYSRVC5_PREFIX_NAME;#error "Fifth system service name prefix must be specified"#endif#endif#if SYSRVC_NUMBER > 5#ifndef SYSRVC6_PREFIX_NAME;#error "Sixth system service name prefix must be specified"#endif#endif#ifndef SYSRVC_ROUTINE_NAME6#error "System service routine name must be specified"#endif#if SYSRVC_NUMBER > 1#ifndef SYSRVC2_ROUTINE_NAME=#error "Second system service routine name must be specified"#endif#endif#if SYSRVC_NUMBER > 2#ifndef SYSRVC3_ROUTINE_NAME<#error "Third system service routine name must be specified"#endif#endif#if SYSRVC_NUMBER > 3#ifndef SYSRVC4_ROUTINE_NAME=#error "Fourth system service routine name must be specified"#endif#endif#if SYSRVC_NUMBER > 4#ifndef SYSRVC5_ROUTINE_NAME<#error "Fifth system service routine name must be specified"#endif#endif#if SYSRVC_NUMBER > 5#ifndef SYSRVC6_ROUTINE_NAME<#error "Sixth system service routine name must be specified"#endif#endif#ifndef SYSRVC_MODE.#error "System service mode must be specified"#elseB#if (SYSRVC_MODE != MODE_K_KERNEL) && (SYSRVC_MODE != MODE_K_EXEC)A#error "System service mode must be MODE_K_KERNEL or MODE_K_EXEC"#endif#endif#if SYSRVC_NUMBER > 1#ifndef SYSRVC2_MODE5#error "Second system service mode must be specified"#elseD#if (SYSRVC2_MODE != MODE_K_KERNEL) && (SYSRVC2_MODE != MODE_K_EXEC)H#error "Second system service mode must be MODE_K_KERNEL or MODE_K_EXEC"#endif#endif#endif#if SYSRVC_NUMBER > 2#ifndef SYSRVC3_MODE4#error "Third system service mode must be specified"#elseD#if (SYSRVC3_MODE != MODE_K_KERNEL) && (SYSRVC3_MODE != MODE_K_EXEC)G#error "Third system service mode must be MODE_K_KERNEL or MODE_K_EXEC"#endif#endif#endif#if SYSRVC_NUMBER > 3#ifndef SYSRVC4_MODE5#error "Fourth system service mode must be specified"#elseD#if (SYSRVC4_MODE != MODE_K_KERNEL) && (SYSRVC4_MODE != MODE_K_EXEC)H#error "Fourth system service mode must be MODE_K_KERNEL or MODE_K_EXEC"#endif#endif#endif#if SYSRVC_NUMBER > 4#ifndef SYSRVC5_MODE4#error "Fifth system service mode must be specified"#elseD#if (SYSRVC5_MODE != MODE_K_KERNEL) && (SYSRVC5_MODE != MODE_K_EXEC)G#error "Fifth system service mode must be MODE_K_KERNEL or MODE_K_EXEC"#endif#endif#endif#if SYSRVC_NUMBER > 5#ifndef SYSRVC6_MODE4#error "Sixth system service mode must be specified"#elseD#if (SYSRVC6_MODE != MODE_K_KERNEL) && (SYSRVC6_MODE != MODE_K_EXEC)G#error "Sixth system service mode must be MODE_K_KERNEL or MODE_K_EXEC"#endif#endif#endif#ifndef SYSRVC_IMASK#define SYSRVC_IMASK 129#endif#if SYSRVC_NUMBER > 1#ifndef SYSRVC2_IMASK#define SYSRVC2_IMASK 129#endif#endif#if SYSRVC_NUMBER > 2#ifndef SYSRVC3_IMASK#define SYSRVC"3_IMASK 129#endif#endif#if SYSRVC_NUMBER > 3#ifndef SYSRVC4_IMASK#define SYSRVC4_IMASK 129#endif#endif#if SYSRVC_NUMBER > 4#ifndef SYSRVC5_IMASK#define SYSRVC5_IMASK 129#endif#endif#if SYSRVC_NUMBER > 5#ifndef SYSRVC6_IMASK#define SYSRVC6_IMASK 129#endif#endif#ifndef SYSRVC_FLAGS#define SYSRVC_FLAGS 0#endif#if SYSRVC_NUMBER > 1#ifndef SYSRVC2_FLAGS#define SYSRVC2_FLAGS 0#endif#endif#if SYSRVC_NUMBER > 2#ifndef SYSRVC3_FLAG#S#define SYSRVC3_FLAGS 0#endif#endif#if SYSRVC_NUMBER > 3#ifndef SYSRVC4_FLAGS#define SYSRVC4_FLAGS 0#endif#endif#if SYSRVC_NUMBER > 4#ifndef SYSRVC5_FLAGS#define SYSRVC5_FLAGS 0#endif#endif#if SYSRVC_NUMBER > 5#ifndef SYSRVC6_FLAGS#define SYSRVC6_FLAGS 0#endif#endif#ifndef SYSRVC_TYPE#define SYSRVC_TYPE 0#endif#if SYSRVC_NUMBER > 1#ifndef SYSRVC2_TYPE#define SYSRVC2_TYPE 0#endif#endif#if SYSRVC_NUMBER > 2#ifndef SYSRVC!3_TYPE#define SYSRVC3_TYPE 0#endif#endif#if SYSRVC_NUMBER > 3#ifndef SYSRVC4_TYPE#define SYSRVC4_TYPE 0#endif#endif#if SYSRVC_NUMBER > 4#ifndef SYSRVC5_TYPE#define SYSRVC5_TYPE 0#endif#endif#if SYSRVC_NUMBER > 5#ifndef SYSRVC6_TYPE#define SYSRVC6_TYPE 0#endif#endif/*  Define system services.*/#include /*8 For exec or kernel mode services, we need to construct= a system service descriptor table entry (or entries) in the, EXEC$INIT_SSTBL_001 PSECT (of all places).*/#pragma extern_model save f#pragma extern_model strict_refdef "EXEC$INIT_SSTBL_001" LONG,PIC,CON,REL,GBL,NOSHR,NOEXE,NOWRT,NOVEC #define SSDESCR SSDESCR const#if SYSRVC_NUMBER == 1/SSDESCR ssconcat(SSDATA_PREFIX,SSDATA_SUFFIX)={2 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC_ROUTINE_NAME),2 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC_ROUTINE_NAME),; SYSRVC_TYPE,(SYSRVC_FLAGS) & 255,SYSRVC_IMASK,SYSRVC_MODE, SYSRVC_FLAGS};#else#if SYSRVC_NUMBER == 22SSDESCR ssconcat(SSDATA_PREFIX,SSDATA_SUFFIX)[2]={2 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC_ROUTINE_NAME),2 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC_ROUTINE_NAME),; SYSRVC_TYPE,(SYSRVC_FLAGS) & 255,SYSRVC_IMASK,SYSRVC_MODE, SYSRVC_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC2_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC2_ROUTINE_NAME),? SYSRVC2_TYPE,(SYSRVC2_FLAGS) & 255,SYSRVC2_IMASK,SYSRVC2_MODE, SYSRVC2_FLAGS};#else#if SYSRVC_NUMBER == 32SSDESCR ssconcat(SSDATA_PREFIX,SSDATA_SUFF IX)[3]={2 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC_ROUTINE_NAME),2 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC_ROUTINE_NAME),; SYSRVC_TYPE,(SYSRVC_FLAGS) & 255,SYSRVC_IMASK,SYSRVC_MODE, SYSRVC_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC2_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC2_ROUTINE_NAME),? SYSRVC2_TYPE,(SYSRVC2_FLAGS) & 255,SYSRVC2_IMASK,SYSRVC2_MODE, SYSRVC2_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC3_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC3_ROUTINE_NAME),? SYSRVC3_TYPE, (SYSRVC3_FLAGS) & 255,SYSRVC3_IMASK,SYSRVC3_MODE, SYSRVC3_FLAGS};#else#if SYSRVC_NUMBER == 42SSDESCR ssconcat(SSDATA_PREFIX,SSDATA_SUFFIX)[4]={2 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC_ROUTINE_NAME),2 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC_ROUTINE_NAME),; SYSRVC_TYPE,(SYSRVC_FLAGS) & 255,SYSRVC_IMASK,SYSRVC_MODE, SYSRVC_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC2_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC2_ROUTINE_NAME),? SYSRVC2_TYPE,(SYSRVC2_FLAGS) & 255,SYSRVC2_IMASK,SYSRVC2_MODE, SYSRVC2_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC3_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC3_ROUTINE_NAME),? SYSRVC3_TYPE,(SYSRVC3_FLAGS) & 255,SYSRVC3_IMASK,SYSRVC3_MODE, SYSRVC3_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC4_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC4_ROUTINE_NAME),? SYSRVC4_TYPE,(SYSRVC4_FLAGS) & 255,SYSRVC4_IMASK,SYSRVC4_MODE, SYSRVC4_FLAGS};#else#if SYSRVC_NUMBER == 52SSDESCR ssconcat(SSDATA_PREFIX,SSDATA_SUFFIX)[5]={2 ssconcat(SY SRVC_VECTOR_NAME,SYSRVC_ROUTINE_NAME),2 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC_ROUTINE_NAME),; SYSRVC_TYPE,(SYSRVC_FLAGS) & 255,SYSRVC_IMASK,SYSRVC_MODE, SYSRVC_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC2_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC2_ROUTINE_NAME),? SYSRVC2_TYPE,(SYSRVC2_FLAGS) & 255,SYSRVC2_IMASK,SYSRVC2_MODE, SYSRVC2_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC3_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC3_ROUTINE_NAME),? SYSRVC3_TYPE,(SYSRVC3_FLAGS) & 255,SYSRVC3_IMASK,SYSRVC3_MODE, SYSRVC3_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC4_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC4_ROUTINE_NAME),? SYSRVC4_TYPE,(SYSRVC4_FLAGS) & 255,SYSRVC4_IMASK,SYSRVC4_MODE, SYSRVC4_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC5_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC5_ROUTINE_NAME),? SYSRVC5_TYPE,(SYSRVC5_FLAGS) & 255,SYSRVC5_IMASK,SYSRVC5_MODE, SYSRVC5_FLAGS};#else#if SYSRVC_NUMBER == 62SSDESCR ssconcat(SSDATA_PREFIX,SSDATA_SU FFIX)[6]={2 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC_ROUTINE_NAME),2 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC_ROUTINE_NAME),; SYSRVC_TYPE,(SYSRVC_FLAGS) & 255,SYSRVC_IMASK,SYSRVC_MODE, SYSRVC_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC2_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC2_ROUTINE_NAME),? SYSRVC2_TYPE,(SYSRVC2_FLAGS) & 255,SYSRVC2_IMASK,SYSRVC2_MODE, SYSRVC2_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC3_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC3_ROUTINE_NAME),? SYSRVC3_TYP E,(SYSRVC3_FLAGS) & 255,SYSRVC3_IMASK,SYSRVC3_MODE, SYSRVC3_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC4_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC4_ROUTINE_NAME),? SYSRVC4_TYPE,(SYSRVC4_FLAGS) & 255,SYSRVC4_IMASK,SYSRVC4_MODE, SYSRVC4_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC5_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC5_ROUTINE_NAME),? SYSRVC5_TYPE,(SYSRVC5_FLAGS) & 255,SYSRVC5_IMASK,SYSRVC5_MODE, SYSRVC5_FLAGS,3 ssconcat(SYSRVC_VECTOR_NAME,SYSRVC6_ROUTINE_NAME),3 ssconcat(SYSRVC_PREFIX_NAME,SYSRVC6_ROUTINE_NAME),? SYSRVC6_TYPE,(SYSRVC6_FLAGS) & 255,SYSRVC6_IMASK,SYSRVC6_MODE, SYSRVC6_FLAGS};#endif#endif#endif#endif#endif#endif#pragma extern_model restore/*$ Undefine all the temporary symbols*/#ifdef __MODE_DEFINED#undef __MODE_DEFINED#undef MODE_K_KERNEL#undef MODE_K_EXEC#undef MODE_K_SUPER#undef MODE_K_USER#undef MODE_K_CALLERS_MODE#endif#undef SYSRVC_PREFIX_NAME#undef SYSRVC_ROUTINE_NAME#undef SYSRVC_TYPE#undef SYSRVC_MODE#undef SYSRVC_IMASK#undef SYSRVC_FLAGS#undef SYSRVC_TYPE#undef SYSRVC2_PREFIX_NAME#undef SYSRVC2_ROUTINE_NAME#undef SYSRVC2_TYPE#undef SYSRVC2_MODE#undef SYSRVC2_IMASK#undef SYSRVC2_FLAGS#undef SYSRVC2_TYPE#undef SYSRVC3_PREFIX_NAME#undef SYSRVC3_ROUTINE_NAME#undef SYSRVC3_TYPE#undef SYSRVC3_MODE#undef SYSRVC3_IMASK#undef SYSRVC3_FLAGS#undef SYSRVC3_TYPE#undef SYSRVC4_PREFIX_NAME#undef SYSRVC4_ROUTINE_NAME#undef SYSRVC4_TYPE#undef SYSRVC4_MODE#undef SYSRVC4_IMASK#undef SYSRVC4_FLAGS#undef SYSRVC4_TYPE#undef SYSRVC5_PREFIX_NAME#undef SYSRVC5_ROUTINE_NAME#undef SYSRVC5_TYPE#undef SYSRVC5_MODE#undef SYSRVC5_IMASK#undef SYSRVC5_FLAGS#undef SYSRVC5_TYPE#undef SYSRVC6_PREFIX_NAME#undef SYSRVC6_ROUTINE_NAME#undef SYSRVC6_TYPE#undef SYSRVC6_MODE#undef SYSRVC6_IMASK#undef SYSRVC6_FLAGS#undef SYSRVC6_TYPE#pragma message restorewwWZU#ifndef __SYS_FUNCTIONS_LOAD ED #define __SYS_FUNCTIONS_LOADED 1/* IDENT X-22 */N//****************************************************************************N// *N// HP CONFIDENTIAL. This software is confidential proprietary software *N// licensed by Hewlett-Packard Development Company, L.P., and is not *N// authorized to be used, duplicated OR disclosed to anyone without the *N// prior written permission of HP. *N// (c) 2017 Copyright Hewlett-Packard Development Company, L.P. *N// *N// VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential *N// proprietary software licensed by VMS Software, Inc., and is not *N// authorized to be used, duplicated or disclosed to anyone without *N// the prior written permission of VMS Software, Inc.  *N// (c) 2017-2019 Copyright VMS Software, Inc. *N// *N//****************************************************************************/**++ * FACILITY:** VMS Executive (LIB)* * ABSTRACT:*F* This header file will provide a basic set of C inline functions for* OpenVMS system services.* * AUTHOR:** Karen L. Noel*"* CREATION DATE:  15-Nov-1994** MODIFICATION HISTORY:$* X-22 DAG Doug Gordon 15-Jul-20197* Have $probew_2q test against the actual page size by4* using a new constant, MMG$C_COMMON_MIN_PAGE_SIZE,8* defined in [STARLET]PAGEDEF.SDL. Belt and suspenders9* by defining it here if for some reason pagedef doesnt.*/* X-21 CV-0335 Camiel Vanderhoeven 15-Apr-2019** Provide x86 version of $priv_instr_trap*/* X-20 CV-0042 Camiel Vanderhoeven 21-Aug-2017* X86 version.* Updated copyright to VSI.*** X-19 KLN3364 Karen L. Noel 29-Sep-2003"* Fix declaration of exe$reflect.*** X-18 KLN3362 Karen L. Noel 25-Sep-2003;* Acces return address as an argument to $priv_instr_trap.*** X-17 KLN3175 Karen L. Noel 19-Dec-2002>* Disable the $$SEXT macro for IA64. Virtual addresses should>* not require extending like on Alpha. On IA64, process space* does not contain a gap.*** X-16 KLN3112 Karen L. Noel 22-Oct-2002;* Add static to $priv_instr_trap to avoid it being defined-* as global in every module that invokes it.*!* X-15 Clair Grant 24-Jul-20026* intstk$l_ipl and intstk$l_pprevmode should be bytes* not longwords.*0* X-14 KLN3065 Karen L. Noel 22-May-2002&* Add $priv_instr_trap for IA64 code.*** X-13 KLN3039 Karen L. Noel 25-Mar-2002'* Add $get_interrupt_ps for IA64 port.*'* X-12 AHM0022 Drew Mason 13-Nov-1997:* Fix bug in $align_va by surrounding the definition with* parentheses.*-* X-11 NYK662 Nitin Y. Karkhanis 1-Aug-1996* Add $align_va.*** X-10 KLN1533 Karen L. Noel 24-Oct-19955* Move $probe functions here from mmg_functions.h so2* they can be used in a more general purpose way.*)* X-9 KLN1530 Karen L. Noel 13-Oct-1995** 1. Include builtins.h for completeness.8* 2. Conditionalize $get_ps_info so header will compile%* with and without __NEW_STARLET.*(* X-8 KLN1471 Karen L. Noel 7-Jul-1995* Add $$trunc macro.*)* X-7 KLN1394 Karen L. Noel 27-Feb-1995%* Fix $make_bigpage_inclusive macro.*/* X-6 KLN1367 Karen L. Noel 20-Jan-1995* Fix cut-and-paste error.*)* X-5 KLN1365 Karen L. Noel 19-Jan-1995(* Add $make_big_page_inclusive function*(* X-4 KLN1350 Karen L. Noel 6-Dec-1994* Fix definition of PS.*)* X-3 KLN1342 Karen L. Noel 30-Nov-1994* Add $get_ps_info*,* X-2 KLN1336 Karen L. Noel 22-Nov-1994(* Take out definitions of SS$_IVACMODE.*--*//*? Include any header files we need to make these functions work*/#include #include #include #include #include #include @#ifdef __ia64 // Verified for x86 port - Camiel Vanderhoeven#include #include #include #endifB#ifdef __x86_64 // Verified for x86 port - Camiel Vanderhoeven#include #endif/**++"* $$sext - sign extend a 64-bit VA** Input: va - 64-bit VA**--*/X#if defined(__alpha) || defined(__x86_64) // Verified for x86 port - Camiel Vanderhoeven1 // Canonical addresses also required on x86#define $$sext(va)\H(VOID_PQ)(((__int64)(va) << (64-mmg$gl_va_bits)) >> (64-mmg$gl_va_bits))#else #define $$sext(va) (VOID_PQ)(va)#endif/**++ * $$trunc - truncate a 64-bit VA** Input: va - 64-bit VA**--*/#define $$trunc(va)\F(uint64)(((uint64)(va) << (64-mmg$gl_va_bits)) >> (64-mmg$gl_va_bits))/**++M* $make_big_page_inclusive - Make start_va and length on even page boundaries*0* Input: start_va - Unaligned starting address%* length - Non-page multiple length*.* Output: return_va - Aligned starting address(* return_length - Page multiple length*J* This function ensures that original start_va and length are covered withI* the returned va and length. If the length was just blindly rounded up,I* the original intended end_va may not get covered by the returned range.*--*/)#pragma inline ($make_big_page_inclusive)6static void $make_big_page_inclusive(VOID_PQ start_va, uint64 length, VOID_PQ *return_va, uint64 *return_length){% extern const uint64 mmg$gq_bwp_mask; uint64 temp_length; VOID_PQ lo_va,hi_va;" /* Round down starting address */8 lo_va = (VOID_PQ)((uint64)start_va & ~mmg$gq_bwp_mask); *return_va = lo_va; /* Compute high address */. hi_va = (VOID_PQ)((uint64)start_va + length);( /* Compute length not yet rounded up *// temp_length = ((uint64)hi_va - (uint64)lo_va); /* Round up return length */E *return_length = (temp_length + mmg$gq_bwp_mask) & ~mmg$gq_bwp_mask;}/**++N* $maximize_access_mode - maximize the acmode argument with the caller's mode.*0* Input: acmode - Access mode provided by caller(* callers_mode - Access mode of caller*J* Output: Returns SS$_IVACMODE status if acmode is greater than PSL$C_USER!* If success, returns SS$_NORMAL.2* max_mode - Maximum of acmode and caller's mode.**--*/&#pragma inline ($maximize_access_mode)Mstatic int $maximize_access_mode(int acmode, int callers_mode, int *max_mode){0 if (acmode > PSL$C_USER) return (SS$_IVACMODE);6 if (acmode <= callers_mode) *max_mode = callers_mode;& else *max_mode = acmode; return (SS$_NORMAL);}/**++0* $is_aligned - check if arg is properly aligned** Input: arg - 64-bit valueE* alignment - alignment factor (page size or block size for example)** Output: returns 1 if aligned* returns 0 if not aligned**--*/##define $is_aligned(arg,alignment)\0(((uint64)(arg) & ((uint64)(alignment)-1)) == 0) /**++5* $align_va - Align va up or down to alignment factor** Input: arg - 64-bit valueE* alignment - alignment factor (page size or block size for example)** up - 1 for round up or 0 for round down** Output: Aligned 64-bit value**--*/$#define $align_va(arg,alignment,up)\( (up)\N? (VOID_PQ)(((uint64)(arg)+(uint64)(alignment)-1) & ~((uint64)(alignment)-1))\7: (VOID_PQ)((uint64)(arg) & ~((uint64)(alignment)-1)) )/**++5* $get_ps_info - Read PS and get IPL and callers_mode** Note:K* This function is only available with __NEW_STARLET due to the differencesG* with PSLDEF. Since there is no current need for $get_ps_info without9* __NEW_STARLET, it will not be implemented at this time.** Inputs: none*1* Outpus: *callers_mode - Previous mode from PS* *ipl - Current IPL*--*/#ifdef __NEW_STARLET#pragma inline ($get_ps_info)5static void $get_ps_info(int *callers_mode, int *ipl){ typedef union { PSLDEF fields; uint64 quad; } PS; PS ps;, /* Read PS and get IPL and caller's mode */ ps.quad = __PAL_RD_PS();# *ipl = (int)(ps.fields.psl$v_ipl);/ *callers_mode = (int)(ps.fields.psl$v_prvmod);}#endif /* __NEW_STARLET *//**++O* $make_interrupt_ps - Construct an interrupt PS from the interrupt stack frame*4* Input: intstk_p - pointer to interrupt stack frame*B* Output: int_ps - PS as if it were in the Alpha interrupt stack**--*/"#pragma inline ($get_interrupt_ps)=static unsigned __int64 $get_interrupt_ps (INTSTK * intstk_p){@#ifdef __alpha // Verified for x86 port - Camiel Vanderhoeven return (intstk_p->intstk$q_ps);#else /* Create a type for the PS */ typedef union { PSLDEF fields; unsigned __int64 quad; } PS; PS int_ps;?#ifdef __ia64 // Verified for x86 port - Camiel Vanderhoeven2 PSR ipsr; // Interrupt processor status register#endif; /* Fill in PS fields from fields in the interrupt stack */ int_ps.quad = 0;2 int_ps.fields.psl$v_ipl = intstk_p->intstk$b_ipl;?#ifdef __ia64 // Verified for x86 port - Camiel Vanderhoeven7 ipsr.psr$q_processor_status = intstk_p->intstk$q_ipsr;- int_ps.fields.psl$v_curmod = ipsr.psr$v_cpl;#else: int_ps.fields.psl$v_curmod = intstk_p->intstk$b_prevmode;#endif; int_ps.fields.psl$v_prvmod = intstk_p->intstk$b_pprevmode; /* Return the results */ return (int_ps.quad);#endif}/**++0* $prober_1q - Probe 1 quadword for readability.*(* Input: va - Address of quadword * callers_mode - Mode of caller*,* Output: Returns 1 if quadword is readable.)* Returns 0 if quadword is not readable.**--*/%#define $prober_1q(va, callers_mode)\8__PAL_PROBER((va), sizeof(uint64)-1, (char)callers_mode)/**++0* $probew_1q - Probe 1 quadword for writability.*(* Input: va  - Address of quadword * callers_mode - Mode of caller*,* Output: Returns 1 if quadword is writable.)* Returns 0 if quadword is not writable.**--*/%#define $probew_1q(va, callers_mode)\8__PAL_PROBEW((va), sizeof(uint64)-1, (char)callers_mode)/**++1* $probew_2q - Probe 2 quadwords for writability.*** Input: va1 - Address of first quadword#* va2 - Address of second quadword * callers_mode - Mode of caller*3* Output: Returns 1 if both quadwords are writable.7* Returns 0 if one or both quadwords are not writable.**--*/#pragma inline ($probew_2q)Bstatic int $probew_2q (VOID_PQ va1, VOID_PQ va2, int callers_mode){#include  VOID_PQ lo, hi; uint64 diff;"#ifndef MMG$C_COMMON_MIN_PAGE_SIZE'#define MMG$C_COMMON_MIN_PAGE_SIZE 8192#endif /* Order addresses */ if (va1 < va2) { lo = va1; hi = va2; } else { lo = va2; hi = va1; }G /* If diff is less than or equal to minimum page size, do one probe */3 diff = ((uint64)hi - (uint64)lo) + sizeof(uint64);( if (diff <= MMG$C_COMMON_MIN_PAGE_SIZE)= return (__PAL_PROBEW(lo, (int)diff-1, (char)callers_mode));+ /* Both probes must succeed to return 1 */A return (__PAL_PROBEW(lo, sizeof(uint64)-1, (char)callers_mode) &A __PAL_PROBEW(hi, sizeof(uint64)-1, (char)callers_mode));} J// If the caller's mode is not kernel, reflect an illegal instruction trap$// AKA - privileged instruction trap// AKA - opcdecI#ifdef __ia64 // Verified for IA64 port - KLN; x86 - Camiel Vanderhoeven!#pragma inline ($priv_instr_trap).static void $priv_instr_trap(__int64 ret_addr){G extern void exe$reflect (int mode, VOID_PQ ret_addr, int sscode, ...); PFS pfs; int mode;& // Get the caller's mode from the PFS: pfs.pfs$iq_prev_func_state = __getReg (_IA64_REG_AR_PFS); mode = pfs.pfs$v_ppl;& // If the caller's mode is not kernel if (mode != PL$C_KERNEL)< // The caller tried to execute a privileged instruction7 exe$reflect (mode, (VOID_PQ)ret_addr, SS$_OPCDEC); return;}#endif?#ifdef __x86_64 // Verified for x86 port - Camiel Vanderhoeven!#pragma inline ($priv_instr_trap).static void $priv_instr_trap(__int64 ret_addr){G extern void exe$reflect (int mode, VOID_PQ ret_addr, int sscode, ...);9 if (__readGsLong(SWIS$K_CURMODE_OFFSET) != PSL$C_KERNEL)< // The caller tried to execute a privileged instructionV exe$reflect (__readGsLong(SWIS$K_CURMODE_OFFSET), (VOID_PQ)ret_addr, SS$_OPCDEC); return;}#endif!#endif /* SYS_FUNCTIONS_LOADED */wwZU// Module TFDEF.H "X-4"//Q// ******************************************************************************Q// * *Q// * Copyright 1976, 2003 Hewlett-Packard Development Company, L.P. *Q// * *Q// * Confidential computer software. Valid license from HP and/or *Q// * its subsidiaries required for possession, use, or copying. *Q// * *Q// * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, *Q// * Computer Software Documentation, and Technical Data for Commercial *Q// * Items are licensed to the U.S. Government under vendor's standard *Q// * commercial license. *Q// * *Q// * Neither HP nor any of its subsidiaries shall be liable for technical *Q// * or editorial errors or omissions contained herein. The information *Q// * in this document is provided "as is" without warranty of any kind and *Q// * is subject to change without notice. The warranties for HP products *Q// * are set forth in the express limited warranty statements accompanying *Q// * such products. Nothing herein should be construed as constituting an *Q// * additional warranty. *Q// * *Q// ******************************************************************************////++// // FACILITY://// OpenVMS Executive (LIB_H)// // ABSTRACT://?// This module contains the C function prototypes and structure=// definitions for the SDA extension trace facility routines.// // AUTHOR://#// Christian Moser, Hewlett-Packard//// MODIFIED BY://)// X-4 CMOS Christian Moser 8-FEB-20067// Add new TF$CVT_TIMESTAMP and TF$CALC_DELTA routines// and remove TF$READ_SCC.//)// X-3 CMOS Christian Moser 27-JAN-20059// Add structures and routine declarations for the PC to,// module, routine and offset translations.//)// X-2 RAB Richard A. Bishop 23-Aug-2004!// Initial CPU namespace changes//)// X-1 CMOS Christian Moser 2-APR-2003// Initial version.//#ifndef __TFDEF_LOADED#define __TFDEF_LOADED 1C#pragma __nostandard // This file uses non-ANSI-Standard features!#pragma __member_alignment __save'#pragma __nomember_alignment __quadwordM#ifdef __INITIAL_POINTER_SIZE // Defined whenever ptr size pragmas supportedW#pragma __required_pointer_size __save // Save the previously-defined required ptr sizeU#pragma __required_pointer_size __long // And set ptr size default to 64-bit pointers#endif//// Common header files//#include far_pointers #include ints// // Constants//"#define TF$TRACE_BUFFER_PAGES 1280// // Define trace header structure//typedef struct _tf_hdr { uint32 idx; uint32 max_idx; unsigned short int mbo;  unsigned char type;  unsigned char subtype; uint32 reserved1; unsigned __int64 size;  VOID_PQ *entry_ptr; } TF_HDR;#typedef struct _tf_hdr * TF_HDR_PQ;typedef struct _image_range { void *left; void *right; int16 reserved; int16 alignment [3]; uint64 start_va; uint64 end_va; uint64 base_va; char name[64]; char devdir[64]; uint64 image_mapped; unsigned char *trace_info; uint64 info_remaining; unsigned char *trace_abbrev; uint64 abbrev_remaining; uint64 abbrev_table; uint64 abbrev_last; unsigned char *trace_aranges; uint64 aranges_remaining; uint64 aranges_table; } IMAGE_RANGE;,typedef struct _image_range *IMAGE_RANGE_PQ;.typedef struct _image_range **IMAGE_RANGE_PPQ;typedef struct _rtn_range { void *left; void *right; int16 reserved; int16 alignment [3]; uint64 rtn_low_pc; uint64 rtn_high_pc; uint64 mod_low_pc; uint64 mod_high_pc; uint64 base_va; char rtn_name[64]; char mod_name[64]; } RTN_RANGE;(typedef struct _rtn_range *RTN_RANGE_PQ;*typedef struct _rtn_range **RTN_RANGE_PPQ;$#pragma __member_alignment __restoreN#ifdef __INITIAL_POINTER_SIZE // Defined whenever ptr size pragmas supported]#pragma __required_pointer_size __restore // Restore the previously-defined required ptr size#endif#pragma __standard//0// Trace facility routine prototype declarations//int tf$load ( char *execlet ); int tf$unload ( char *execlet );@int tf$debug ( char *execlet, uint64 anchor, TF_HDR_PQ tf_hdr );Oint tf$get_execlet_info ( char *execlet, uint64 *exec_base, uint64 *exec_end );Cint tf$get_module_offset ( uint64 va, char *module, char *offset );int tf$build_image_tree ();mint tf$get_mod_rtn ( uint64 pc, uint64 *mod_name, uint64 *rtn_name, uint64 *mod_rel_pc, uint64 *rtn_rel_pc );Qvoid tf$cvt_timestamp ( int64 timestamp, int cpuid, uint64 *time, uint64 *usec );Uint64 tf$calc_delta ( int64 time_end, int cpuid_end, int64 time_beg, int cpuid_beg ); #endif // __TFDEF_LOADEDww`ZU#ifndef __THREAD_MACROS_LOADED #define __THREAD_MACROS_LOADED 1/* IDENT X-18 *//* */O/* ************************************************************************* */O/* * * */O/* * HPE CONFIDENTIAL. This software is confidential proprietary software * */O/* * licensed by Hewlett Packard Enterprise Development, LP, and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without the * */O/* * prior written permission of HPE. * */O/* * Copyright 2017 Hewlett Packard Enterprise Development, LP * */O/* * * */O/* * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential * */O/* * proprietary software licensed by VMS Software, Inc., and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without * */O/* * the prior written permission of VMS Software, Inc. * */O/* * Copyright 2017 VMS Software, Inc. * */O/* * * */O/* ************************************************************************* *//**++ * FACILITY:** VMS Executive (LIB)* * ABSTRACT:*?* This header file provides macros and functions that are used* for kernel thread support. * * AUTHOR:** Ellen M. Batbouta*"* CREATION DATE: 09-Mar-1995** MODIFICATION HISTORY:*C* X-18 CEG0919 Clair Grant 25-Sep-20205* Change comment in X-17 *)* X-17 CEG0910 Clair Grant 24-Sep-2020** Replace "// comment" style to eliminate+* confusion when compiling /STANDARD=VAXC.*.* X-16 CV-0262 Camiel Vanderhoeven 1-Nov-20183* Deal with possibility of null PCB in get_curktb.*#* X-15 AHM Drew Mason 30-Nov-20175* Add definition of __RUNCONST to let SYSBOOT modify3* run-time constants. Use typed PCB_PL and KTB_PL)* pointers instead of the ambiguous "*".*(* X-14 CEG0167 Clair Grant 09-Jun-2017&* Verified conditionals for x86 port.* Updated copyright t0 VSI.*)* X-13 KLN3096 Karen L. Noel 2-Oct-2002* o Port get_curktb to IA64.* o Fix ident.*%* X-11 DJM Dennis Mattoon 20-MAR-02:* Replaced call_pal asm statement with an equivalent call* to the __PAL_LDQP builtin.*** X-10 KLN2085 Karen L. Noel 11-Jun-1998-* Fix some more DEC C level4 informationals.*)* X-9 KLN2075 Karen L. Noel 12-May-19989* The compiler doesn't like upper cased externs compiled7* with lower cased externs of the same name. Most code6* uses lower case, so just switch this case to lower.*"* X-8 Dave Bernardo 07-Mar-1998:* Fix return in get_curktb. Cleanup pointer size madness.*%* X-7 DMB Dave Bernardo 04-Nov-1996* Add new WTAMI algorithm*'* X-6 MAS Mary A. Sullivan 17-May-19965* Use more standard '__int64' rather than 'int64' in9* our casts (from X-3) since we don't explicitly include5* ints.h, and besides it makes the latest C compiler * happy.*** X-5 PKW355 Paul K. M. Weiss 17-May-1996* Define pktadef for PKW353*** X-4 PKW353 Paul K. M. Weiss 15-May-1996(* Add get_curpkta caller's mode routine*'* X-3 MAS Mary A. Sullivan 17-Jan-19964* Declare 'pcbb' as a 64-bit pointer and use 64-bit#* arithmetic on my_id calculation.*1* X-2 JCH703 John C. Hallyburton, Jr. 17-Apr-1995>* Change logical "&&" to bitwise "&" in my_id calculation, so;* the correct KTB pointer will be returned instead of PCB.<* Rework code slightly. Note the compiler could do a little=* better by realizing it was SEXTL-ing pcbb then masking off8* only the low 9 bits, so why SEXTL in the first place?**--*//*A This construct allows SYSBOOT write access to variables that are= run-time constants, but need to be initialized at boot time.*/#ifdef __SYSBOOT#define __RUNCONST#else#define __RUNCONST const#endif/*< Include any header files we need to make these macros work*/#include #include #include #include #include [#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */Z#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */Q/* Define function to get the address of the current kernel thread block (KTB) */#pragma inline (get_curktb)static KTB_PL get_curktb(void) { G#ifndef __ALPHA /* Verified for IA64 port - KLN; x86 - Clair Grant */+ extern int swis$get_current_kt_id(void);( extern PCB_PL __RUNCONST ctl$gl_pcb; int my_id; KTB_PPL ktbvec; G#if !defined(__ia64) /* Verified for x86 port - Camiel Vanderhoeven */ if (ctl$gl_pcb == (PCB_PL)0) return (KTB_PL)0;#endif 7 /* If process has 1 execution context, ktb is pcb */* if (ctl$gl_pcb->pcb$l_kt_count <= 1) % return ((KTB_PL)ctl$gl_pcb); M /* This is a multithreaded process with more than 1 execution context. */$ my_id = swis$get_current_kt_id();% ktbvec = ctl$gl_pcb->pcb$l_ktbvec; return (ktbvec[my_id]);#endif F#ifdef __ALPHA /* Verified for IA64 port - KLN; x86 - Clair Grant */( extern PCB_PL __RUNCONST ctl$gl_pcb; ) extern __RUNCONST int mmg$gl_bwp_mask; VOID_PQ pcbb;  int my_id;  KTB_PPL ktbvec; 6/* Does process have more than 1 execution context? */* if (ctl$gl_pcb->pcb$l_kt_count <= 1) % return ((KTB_PL)ctl$gl_pcb); # else { P /* This is a multithreaded process with more than 1 execution context. */" pcbb = __PAL_MFPR_PCBB(); : if ( (__int64) pcbb & (__int64) (FRED$K_LENGTH - 1))! return ((KTB_PL)ctl$gl_pcb); + if (ctl$gl_pcb->pcb$v_ fredlock == 0) {? /* This is a multithreaded process with 1 FRED page */X my_id = (int) (((__int64) pcbb & (__int64) mmg$gl_bwp_mask) >> FRED$K_SHIFT); + ktbvec = ctl$gl_pcb->pcb$l_ktbvec; return (ktbvec[my_id]); } else {J /* This is a multithreaded process with more than 1 FRED page */Q return (KTB_PL)(__PAL_LDQP((void *)((__int64)pcbb + FRED$C_KTB_KT_ID))); }# }  #endif}#pragma inline (get_curpkta)static PKTA * get_curpkta(void){ int my_id;" extern int sys$get_kt_id(void);! extern int ctl$gl_multithread;" extern PKTA ctl$a_initial_pkta;Y#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ extern PKTA **ctl$gq_pktavec;Z#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ if (ctl$gl_multithread <= 1) return &ctl$a_initial_pkta; else { my_id = sys$get_kt_id();, return ((PKTA *) ctl$gq_pktavec[my_id]); }}b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */##endif /* __THREAD_MACROS_LOADED */wwSZU /* module VCONS_ROUTINES.H "X-1"*J *************************************************************************J * *J * Copyright 2004 Hewlett-Packard Development Company, L.P. *J * *J * Confidential computer software. Valid license from HP and/or *J * its subsidiaries required for possession, use, or copying. *J * *J * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, *J * Computer Software Documentation, and Technical Data for Commercial *J * Items are licensed to the U.S. Government under vendor's standard *J * commercial license. *J * *J * Neither HP nor any of its subsidiaries shall be liable for technical *J * or editorial errors or omissions contained herein. The information *J * in this document is provided "as is" without warranty of any kind and *J * is subject to change without notice. The warranties for HP products  *J * are set forth in the express limited warranty statements accompanying *J * such products. Nothing herein should be construed as constituting an *J * additional warranty. *J * *J **************************************************************************++ * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:* >* This module contains the C function prototypes for the fPars* virtual console routines.* * AUTHOR:* * Karen L. Noel* * CREATION DATE: 15-Jan-2004* * MODIFICATION HISTORY:**--*/ #ifndef __VCONS__ROUTINES_LOADED"#define __VCONS__ROUTINES_LOADED 1&#pragma __required_pointer_size __save&#pragma __required_pointer_size __long/*G* Define all types that are used in the following function prototypes.*/#include /* 1* Declare routines called from within this mdoule*//uint64 exe$call_vcons_service (uint64 func_id,  void * buffer,  uint64 size,  uint64 fpar_id, ! uint64 * return_bytes);/** Static function definitions*/#define VCONS$K_OUTPUT 2/static uint64 vcons$output (void * out_buffer,  uint64 buffer_size, 3 uint64 * bytes_written){ return (E exe$call_vcons_service (VCONS$K_OUTPUT, out_buffer, buffer_size, 0,  bytes_written) );}#define VCONS$K_INPUT 3-static uint64 vcons$input (void * in_buffer,  uint64 buffer_size,  uint64 * bytes_read){ return (C exe$call_vcons_service (VCONS$K_INPUT, in_buffer, buffer_size, 0, bytes_read) );})#pragma __required_pointer_size __restore'#endif /* __IA64_PAL_ROUTINES_LOADED */wwzZU// IDENT "X-1"//O///////////////////////////////////////////////////////////////////////////////H// Copyright (c) 2017,2018 VMS Software, Inc. Bolton, Massachusetts, USA//// HEADER: VMS_CONSOLE.H// FACILITY: VMS_BOOTMGRL// DESCRIPTION: Boot Manager Console IO Services, Callbacks and Structures. //// REVISION HISTORY://%// X-1 AHM Drew Mason 24-Jul-2018<// Checkin this boot manager H file for Gary. Add #define5// for va_list if needed. #define __cdecl as null.+// X-03 GMN Gary M. Newsted 23-Jul-2018)// Cleaned up for use by SYSBOOT et al.*// X-02 GMN Gary M. Newsted 2-Apr-2018E// Added BOOTMGR_ExitBootServices service (service table version 7)*// X-01 GMN Gary M. Newsted 8-Aug-2017// First VSI edition.//O/////////////////////////////////////////////////////////////////////////////////#ifndef __VMS_CONSOLE_LOADED#define __VMS_CONSOLE_LOADED 1#include // A few common UEFI data types #ifndef CHAR8#define CHAR8 char #endif #ifndef INT32#define INT32 __int32#endif#ifndef UINT32 #define UINT32 unsigned __int32 #endif#ifndef UINT64 #define UINT64 unsigned __int64 #endif#ifndef va_list#define va_list __va_list#endif#define __cdecl1// Useful UEFI Colors (Format: 24-bit 0x00RRGGBB)7#define K_COLOR_BLACK 0x00000000 // Default Background1#define K_COLOR_WHITE 0x00FFFFFF // Default Text-#define K_COLOR_BLUE 0x000000FF // Full blue2#define K_COLOR_DKBLUE 0x006060FF // Major Labels2#define K_COLOR_LTBLUE 0x0010FFFF // General Text5#define K_COLOR_REBLUE 0x00AFE1E1 // Robins Egg Blue>#define K_COLOR_GREEN 0x0010C010 //  Progress and Success Text-#define K_COLOR_RED 0x00FF1010 // Error Text9#define K_COLOR_VIOLET 0x00D000D0 // Default Prompt Text2#define K_COLOR_YELLOW 0x00E0E010 // Warning Text8#define K_COLOR_ORANGE 0x00FF8000 // Graphical Outlines8#define K_COLOR_LIGHTSLATE 0x00B9B9B9 // Greyed out Text7#define K_COLOR_DARKSLATE 0x006E6E6E // Greyed out Text3#define K_COLOR_LIGHTBLUE 0x00B2E9FF // General Use2#define K_COLOR_LTGREEN 0x00A7FF86 // General Use2#define K_COLOR_DARKTEAL 0x00004040 // General Use(typedef CHAR8(__cdecl *KEYBOARD_CHAR) ( );,typedef CHAR8* (__cdecl *KEYBOARD_STRING) ( );typedef void(*VOID_FUNCTION) ( ); typedef UINT64(*CONSOLE_PRINT) (W UINT32 color, // A RGB color constant, or any custom color (no Alpha channel byte)O const char *pFmt, // Pointer to a pre-formatted character string to output. ... );!typedef UINT64(*CONSOLE_VPRINT) (W UINT32 color, // A RGB color constant, or any custom color (no Alpha channel byte)O const char *pFmt, // Pointer to a pre-formatted character string to output. va_list argp ); typedef UINT64(*SPECIAL_PRINT) (O const char *pFmt, // Pointer to a pre-formatted character string to output. ... ); typedef void(*STRING_FUNCTION) (J CHAR8 *pString // Passed or returned string pointer (caller allocated) );typedef void(*SET_UINT32) (( UINT32 value // Sets a 32 bit value );%typedef UINT32(__cdecl *GET_UINT32) ( );#define K_CONIO_TABLE_VE RSION 8typedef struct {; UINT64 Version; // *** KEEP TABLE QUADWORD ALIGNED *** // CONIN - Keyboard FunctionsB KEYBOARD_CHAR KB_Getc; // (CHAR8) Keyboard Character Input@ KEYBOARD_STRING KB_Gets; // (CHAR8*) Keyboard String Input: VOID_FUNCTION KB_EOC; // void Issue End-Of-Command // CONOUT - Display Functions S CONSOLE_PRINT PRINT_Console; // (color, fmt, ...) Variable color General PurposeI SPECIAL_PRINT PRINT_Error; // (fmt, ...) Fixed Red ERRORS Not gatedN SPECIAL_PRINT PRINT_Warning; // (fmt, ...) Fixed Yellow WARNINGS Not gatedI SPECIAL_PRINT PRINT_Info; // (fmt, ...) Fixed White INFO Not gateda SPECIAL_PRINT PRINT_Progress; // (fmt, ...) Fixed Green, PROGRESS Gated by boot flag PROGRESS // GRAPHICAL Functions$ STRING_FUNCTION GRAPHICS_SetPrompt;% VOID_FUNCTION GRAPHICS_RedrawPrompt; GET_UINT32 GRAPHICS_GetCursor; SET_UINT32 GRAPHICS_SetCursor;) GET_UINT32 GRAPHICS_GetBackgroundColor;) SET_UINT32 GRAPHICS_SetBackgroundColor;) GET_UINT32 GRAPHICS_GetForegroundColor;) SET_UINT32 GRAPHICS_SetForegroundColor;% VOID_FUNCTION GRAPHICS_ClearDisplay; // DUMP KERNEL Functions( VOID_FUNCTION COMMAND_DumpKernelBoot;, STRING_FUNCTION COMMAND_DumpKernelDevList; // New in V7` SET_UINT32 BOOTMGR_ExitBootServices; // Wraps UEFI service to allow switching keyboard handler // New in V83 CONSOLE_VPRINT PRINT_ConsoleVA; // (fmt, va_list)} BOOTMGR_CONIO_TABLE;#endifwwZU/*  module vms_drivers.h "X-27"*I*************************************************************************I* *I* Copyright 2002 Compaq Computer Corporation *I* *I* COMPAQ Registered in U.S. Patent and Trademark Office. *I* *I* Confidential computer software. Valid license from Compaq or *I* authorized sublicensor required for possession, use or copying. *I* Consistent with FAR 12.211 and 12.212, Commercial Computer Software, *I* Computer Software Documentation, and Technical Data for Commercial *I* Items are licensed to the U.S. Government under vendor's standard *I* commercial license. *I*  *I* Compaq shall not be liable for technical or editorial errors or *I* omissions contained herein. The information in this document is *I* subject to change without notice. *I* *I**************************************************************************++ * FACILITY:** VMS Executive (LIB)* * ABSTRACT:*O* This header file will provide a basic set of C macros for system programmers6* and driver writers to use FDT Completion routines. * * AUTHOR:** Walter D. Blaschuk, Jr.*#* CREATION DATE: 14-June-1993** MODIFICATION HISTORY:*(* X-27 MJM Michael Moroney 30-May-2017:* Add ini_dpt_dsplypath_size and ini_dpt_dsplypath_ucb_of * macros.*)* X-26 CMOS Christian Moser 23-MAR-2004+* Add new DRIVER$INI_DPT_MAX_UNIT routine.*'* X-25 ABP Anu Pant 14-May-2002,* Add support for MPDEV_PATH_SWTCH routine.* * X-24 ABP Anu Pant 1-May-2002* Fix for PTR 75-83-85:,* Set status to NORMAL in the beginning of 8* device_lock_nospin and device_lock_shr_nospin macros.*)* X-23 CMOS Christian Moser 2-OCT-2001:* Add new UCB_LOCK/UCB_UNLOCK macros as a combintation of&* the fork/device lock/unlock macros.*+* X-22 DEE0601 David E. Eiche 29-Jun-2000:* Add support for the USB CONFIGURE and DECONFIGURE entry * points.*)* X-21 JMB219 James M. Blue 9-Mar-2000:* Change the QIOServer helper routine name from QSRV_HLPR* to QSRV_HELPER.*'* X-20 JRC John R. Covert 24-Feb-20000* Add RMdriver Object registration routine defs"* MGT_REGISTER and MGT_DEREGISTER*)* X-19 JMB202 James M. Blue 10-Jan-20003* Rename QSRV_COMPLETION to QSRV_HELPER to be more** representative of its function. Rename2* QSRV_PATH_NOTIFY to QSRV_EVNT_NOTIFY to be more"* representative of its function.*3* Add a new FDT table containing QIOServer control/*  bit masks by function code to be 'OR'ed into7* IRP$L_STS2. These settings will direct the handling'* of a request by QIOServer's KClient.*)* X-18 CMOS Christian Moser 16-AUG-1999=* Add new DEVICE_LOCK and DEVICE_UNLOCK variants to support !* sharelocks and nospin locking.*)* X-17 JMB094 James M. Blue 22-Mar-19997* Add initialization macro for the qsrv_completion and9* qsrv_path_notify cells that has been added to the ddt.*C* X-16 GP Genady P erchenko 06-Jul-1998<* Renames driver$ini_dpt_dsplypath_ucb_ofs to C* driver$ini_dpt_dsplypath_ucb_of in order to fit it %* within 31 characters.*C* X-15 GP Genady Perchenko 23-Jun-1998D* Add ini_dpt_dsplypath_size and ini_dpt_dsplypath_ofs$* function prototypes.*)* X-14 CMOS Christian Moser 20-APR-19987* Add fastpath FDT and upcall routines (SETPRFPATH and* CHANGE_PREFER RED).*C* X-13 GP Genady Perchenko 12-Dec-19979* Fiber Channel Device Naming Project: Add A* ini_dpt_devpath_size, ini_dpt_devpath_ucb_ofs andJ* ini_ddt_make_devpath macros. See DPTDEF.SDL and DDTDEF.SDL5* for information on associated fields.*+* See the design document in J* STAR::DOCD$:[EVMS.PROJECT_DOCUMENTS]FC_NAMING.PS for more * details*+* X-12 DEE0232 David E. Eiche 10-Jan-1996(* Add DDT macros for DDT entry FUNCTAB.*(* X-11 PJH Paul J. Houlihan 26-Jun-1995)* Add DDT macro for pending I/O routine.*2* X-10 JCH703 John C. Hallyburton, Jr. 23-Jan-1995)* Add DDT macros for DDT entry FAST_FDT./* DOCD$:[EVMS.PROJECT_DOCUMENTS]FS-FASTIO.PS;1* Add once-only #include code*/* X-9 LSS0311 Leonard S. Szubowicz 19-Oct-1994B* Add definitions of FDT_x_64 constants that can be used with the?* ini_fdt_act macro to declare functions that support a 64-bitB* $QIO P1 parameter. See "Chapter 20: QIO and Device Drivers" in$* DOCD$:[EVMS.CMS_64B]DS-64BITS.PS.*+* X-8 JPJ James P. Janetos 05-May-1994%* Get rid of form feed.*0* X-7 ROW0843 Ralph O. Weber 20-DEC-1993 13:38:* Add driver initialization support for DPT$IW_IOHANDLES,:* the number of I/O Handles the driver needs to save, and>* DDT$PS_CSR_MAPPING, the pointer to the driver's CSR mapping* initialization routine.*** X-6 DEE0203 David E. Eiche 01-Nov-1993A* Move the device driver table initialization routine prototypes;* into this module from ioc_routines.h. Add one macro perA* initialization routine to invoke the routine, check the status@* returned and exit if the status isn't a success code. Define4* codes for BUFFERED and NOT_BUFFERED (DIRECT) I/O.* ** X-5 DEE0202 David E. Eiche 13-Oct-1993=* Add the dpt_store_isr_vec macro to allow the driver writer@* to store an ISR PD and entry poin t address in any one of whatE* may be several VEC entries in the CRB. Redefine the dpt_store_isr>* macro in terms of dpt_store_isr_vec to fill in the first or* only VEC entry in a CRB.*** X-4 DEE0201 David E. Eiche 08-Oct-1993** Add the dpt_store_isr macro definition.*/* X-3 LSS0285 Leonard S. Szubowicz 27-Aug-1993@* Revised and more complete forms of the device driver synchro->* nization macros as described in EVMS$IO_DOC:HLLDD-FORK.MEM.A* Also, change names of FDT completion macros from $x to CALL_x.*/* X-2 LSS0282 Leonard S. Szubowicz 21-Jul-1993A* Initial versions of some device driver synchronization macros.*5* X-1 WDB:HLL63 Walter D. Blaschuk, Jr. 14 June 1993?* HLLDD Project: C macros for Step 2 FDT Completion routines."* EVMS$IO_DOC:[IO.CMS]FDT_DESIGN.**--*/#ifndef __VMS_DRIVERS_LOADED#define __VMS_DRIVERS_LOADED 1/* Include files */#include #include #include #include #include #include #include #include #include #include #include #include #include /*:Macro to set up and call the Step 2 FDT Completion routineEXE_STD$ABORTIO.&This will always return SS$_FDT_COMPL.*/1#define call_abortio(irp,pcb,ucb,final_status) \ ( \- exe_std$abortio(irp,pcb,ucb,final_status) \ )/*:Macro to set up and call the Step 2 FDT Completion routine9EXE_STD$FINISHIO. This macro fills in but the first and 'second longword of the IOST in the IRP.&This will always return SS$_FDT_COMPL.*/-#define call_finishio(irp,ucb,iost1,iost2) \ ( \ irp->irp$l_iost1 = iost1, \/ irp->irp$l_iost2 = iost2, \ exe_std$finishio(irp,ucb) \ )/*:Macro to set up and call the Step 2 FDT Completion routine<EXE_STD$FINISHIO with status in the first longword and zero 0in the second longword of the IOST in the IRP.. &This will always return SS$_FDT_COMPL.*/)#define call_finishioc(irp,ucb,iost1) \ ( \ irp->irp$l_iost1 = iost1, \, irp->irp$l_iost2 = 0, \ exe_std$finishio(irp,ucb) \ )/*:Macro to set up and call the Step 2 FDT Completion routine;EXE_STD$FINISHIO. The macro does not touch the IOST fields in the IRP.&This will always return SS$_FDT_COMPL.*/)#define call_finishio_noiost(irp,ucb) \  ( \ exe_std$finishio(irp,ucb) \ )/*:Macro to set up and call the Step 2 FDT Completion routineEXE_STD$QIOACPPKT.*/(#define call_qioacppkt(irp,pcb,ucb) \ ( \$ exe_std$qioacppkt(irp,pcb,ucb) \ )/*:Macro to set up and call the Step 2 FDT Completion routine9EXE_STD$QIODRVPKT. This macro zeros the FDT Context ptr.%in the IRP then calls EXE_STD$INSIOQ.&This will always return SS$_FDT_COMPL.*/$#define call_qiodrvpkt(irp,ucb) \  ( \! irp->irp$ps_fdt_context = 0, \ exe_std$insioq(irp,ucb), \ SS$_FDT_COMPL \ )/*:Macro to set up and call the Step 2 FDT Completion routineEXE_STD$IORSNWAIT.&This will always return SS$_FDT_COMPL.*/C#define call_iorsnwait(irp,pcb,ucb,ccb,final_status,resource_num) \ ( \D exe_std$iorsnwait(irp,pcb,ucb,ccb,final_status,resource_num) \ )/*M Define some constants used by the device_lock, device_unlock, fork_lock, and fork_unlock macros*/<#define NOSAVE_IPL ((int *) 0) /* don't save original IPL */7#define NOLOWER_IPL -1 /* don't lower IPL on unlock */4#define NORAISE_IPL 0 /* don't raise IPL on lock *//#define RAISE_IPL 1 /* do raise IPL on lock */=#define SMP_RELEASE 0 /* unconditionally release spinlock */;#define SMP_RESTORE 1 /* conditionally release spinlock *//*I* The device_lock macro is used to acquire a device spinlock and to$* optionally save the original IPL.* ** The f ormat of the device_lock macro is:* 0* device_lock (lockaddr, raise_ipl, savipl_p)* * Inputs:* I* lockaddr is a pointer to the device spinlock structure of* type SPL.* I* raise_ipl is either the integer value RAISE_IPL orI* NORAISE_IPL. The symbol RAISE_IPL is defined to beI* 1 and the symbol NORAISE_IPL is defined to be 0 byI* the vms_drivers.h fi le. If raise_ipl is equal toI* RAISE_IPL, then the IPL is set using the value in-* the spinlock structure.* * Outputs:* I* savipl_p is a 32-bit integer passed by reference in whichI* the original IPL is returned. If the address ofI* this parameter is NOSAVE_IPL, then the current IPLI* is not returned. The symbol NOSAVE_IPL is definedI*  to be a null pointer, i.e. ((int *) 0), by the)* vms_drivers.h file.*F* status is a 32-bit integer passed by reference in whichG* the status of the lock operation is returned. TheG* _NOSPIN variants will return either SS$_NORMAL orI* SS_$INUSE, depending, if the spinlock was locked or* not.* I* For example, in a driver fork routine one could save the current  IPL* and take the device lock by:* ;* device_lock (ucb->ucb$l_dlck, RAISE_IPL, &orig_ipl);* I* However, in an interrupt service routine, where the IPL is alreadyI* known to be at device IPL one could take the device lock and leave the* IPL unchanged by:* >* device_lock (ucb->ucb$l_dlck, NORAISE_IPL, NOSAVE_IPL);*/4#define device_lock(lockaddr, raise_ipl, savipl_p) \ { \( extern SMP smp$gl_flags; \ \* if(s avipl_p != NOSAVE_IPL) \. *savipl_p = __PAL_MFPR_IPL(); \ \- if(raise_ipl == NORAISE_IPL) { \/ if(smp$gl_flags.smp$v_enabled) \0 smp_std$acqnoipl( lockaddr ); \ } \ else { \/ if(smp$gl_flags.smp$v_enabled) \0 smp_std$acquirel( lockaddr ); \ else \8 __PAL_MTPR_IPL( lockaddr->spl$l_ipl ); \ } \  }8#define device_lock_shr(lockaddr, raise_ipl, savipl_p) \ { \( extern SMP smp$gl_flags; \ \* if(savipl_p != NOSAVE_IPL) \. *savipl_p = __PAL_MFPR_IPL(); \ \- if(raise_ipl == NORAISE_IPL) { \/ if(smp$gl_flags.smp$v_enabled) \3 smp_std$acqnoipl_shr( lockaddr ); \ } \ else { \/ if(smp$gl_flags.smp$v_enabled) \3   smp_std$acquirel_shr( lockaddr ); \ else \8 __PAL_MTPR_IPL( lockaddr->spl$l_ipl ); \ } \ }C#define device_lock_nospin(lockaddr, raise_ipl, savipl_p, status) \ { \( extern SMP smp$gl_flags; \$ *(int *)status = SS$_NORMAL; \ \* if(savipl_p != NOSAVE_IPL) \. *savipl_p = __PAL_MFPR_IPL(); \ \- if(raise_ipl == NORAISE_IPL) { \/  if(smp$gl_flags.smp$v_enabled) \G *(int *)status = smp_std$acqnoipl_nospin( lockaddr ); \ } \ else { \/ if(smp$gl_flags.smp$v_enabled) \G *(int *)status = smp_std$acquirel_nospin( lockaddr ); \ else \ { \8 __PAL_MTPR_IPL( lockaddr->spl$l_ipl ); \! *(int *)status = SS$_NORMAL; \ } \ } \ }G#define device_lock_shr_nospin(lockaddr, raise_ipl, savipl_p, status) \ { \( extern SMP smp$gl_flags; \$ *(int *)status = SS$_NORMAL; \ \* if(savipl_p != NOSAVE_IPL) \. *savipl_p = __PAL_MFPR_IPL(); \ \- if(raise_ipl == NORAISE_IPL) { \/ if(smp$gl_flags.smp$v_enabled) \K *(int *)status = smp_std$acqnoipl_shr_nospin( lockaddr ); \ } \ else { \/ if(smp$gl_flags.smp$v_enabled) \K *(int *)status = smp_std$acquirel_shr_nospin( lockaddr ); \ else \ { \8 __PAL_MTPR_IPL( lockaddr->spl$l_ipl ); \! *(int *)status = SS$_NORMAL; \ } \ } \ },#define device_lock_cvt_to_shr(lockaddr ) \ { \( extern SMP smp$gl_flags; \ \- if(smp$gl_flags.smp$v_enabled) \2 smp_std$cvt_to_shared( lockaddr ); \ else \6 __PAL_MTPR_IPL( lockaddr->spl$l_ipl ); \ }2#define device_lock_cvt_to_ex(lockaddr, status ) \ { \( extern SMP smp$gl_flags; \ \- if(smp$gl_flags.smp$v_enabled) \? *(int *)status = smp_std$cvt_to_ex( lockaddr ); \ else \ { \6 __PAL_MTPR_IPL( lockaddr->spl$l_ipl ); \& *(int *)status = SS$_NORMAL; \ } \  }/*I* The device_unlock macro is used to either release or restore (i.e.I* conditionally release) a device spinlock and to optionally set a new* IPL.* ,* The format of the device_unlock macro is:* .* device_unlock (lockaddr, newipl, restore)* * Inputs:* I* lockaddr is a pointer to the device spinlock structure of* type SPL.* I* newipl is the integer value of the desired new IPL or theI*  value NOLOWER_IPL if the IPL should be leftI* unchanged. The symbol NOLOWER_IPL is defined to be3* -1 by the vms_drivers.h file.* I* restore is the either the integer value SMP_RESTORE orI* SMP_RELEASE. If SMP_RELEASE is specified then theI* spinlock is unconditionally released by callingI* SMP_STD$RELEASEL, otherwise the spinlock  isI* conditionally released by calling SMP_STD$RESTOREL.I* The symbol SMP_RESTORE is defined to be 1 and theI* symbol SMP_RELEASE is defined to be 0 by the)* vms_drivers.h file.* I* For example, in a driver fork routine one could release the device2* lock and restore the previously saved IPL by:* @* device_unlock (ucb->ucb$l_dlck, orig_ipl, SMP_RELEASE);* I* However, in an interrupt service routine, one could release the0* device lock and stay at the current IPL by:* C* device_unlock (ucb->ucb$l_dlck, NOLOWER_IPL, SMP_RELEASE);*/2#define device_unlock(lockaddr, newipl, restore) \ { \( extern SMP smp$gl_flags; \ \/ if(smp$gl_flags.smp$v_enabled) { \+ if(restore == SMP_RELEASE) \0 smp_std$releasel( lockaddr ); \ else \0 smp_std$restorel( lockaddr ); \ } \ if(newipl >= 0) \+ __PAL_MTPR_IPL( newipl ); \ }6#define device_unlock_shr(lockaddr, newipl, restore) \ { \( extern SMP smp$gl_flags; \ \/ if(smp$gl_flags.smp$v_enabled) { \+ if(restore == SMP_RELEASE) \3 smp_std$releasel_shr( lockaddr ); \ else \3 smp_std$restorel_shr( lockaddr ); \ } \ if(newipl >= 0) \+ __PAL_MTPR_IPL( newipl ); \ }/*D * The dpt_store_isr and dpt_store_isr_vec macros are used to storeF * the procedure descriptor and entry point addresses of an interruptG * service routine into a VEC entry in a given CRB. The dpt_store_isr< * macro selects the first or only VEC entry in a CRB. TheA * dpt_store_isr_vec macro allows the number of the vector to be * supplied. *" * The formats of the macros are: *) * dpt_store_isr_vec (crb, vecno, isr) * * and * * dpt_store_isr (crb, isr) * * where: *3 * crb is a pointer to the Channel Request BlockH * vecno is the index (0, 1, 2, ...) of the VEC entry to be filled inF * isr is the procedure descriptor of the Interrupt Service Routine * */3#define dpt_store_isr_vec( crb, vecno, isr ) { \6 struct __pd { int :32; int :32; void *entry; } \, *_pdp = ( struct __pd *)(isr); \E  ((VEC *)&((crb)->crb$l_intd) + (vecno))->vec$ps_isr_pd = (isr); \M ((VEC *)&((crb)->crb$l_intd) + (vecno))->vec$ps_isr_code = _pdp->entry; }B#define dpt_store_isr( crb, isr ) dpt_store_isr_vec( crb, 0, isr )/*H* The fork macro is used to queue a specified fork routine withH* specified fork routine parameters. After the fork routine isH* queued, execution continues with the next statement following the* fork macro.* $* The format of the fork macro is:* (* fork (fork_routine, fr3, fr4, fkb)* * Inputs:* H* fork_routine is the procedure value of the routine that is toH* be executed in a fork thread. This value isH* passed to the fork dispatcher via fkb->fkb$l_fpc.* H* fr3 is the 64-bit value to pass to the fork routineH* via fkb->fkb$q_fr3. This parameter is cast as a&* 64-bit integer.* H* fr4  is the 64-bit value to pass to the fork routineH* via fkb->fkb$q_fr4. This parameter is cast as a&* 64-bit integer.* H* fkb is a pointer to the fork block. This parameter6* is cast as a pointer to an FKB.*/,#define fork(fork_routine, fr3, fr4, fkb) \ { \6 ((FKB *) fkb)->fkb$l_fpc = fork_routine; \7 ((FKB *) fkb)->fkb$q_fr3 = (__int64) fr3; \7 ((FKB *) fkb)->fkb$q_fr4 = (__int64) fr4; \1 exe_std$queue_fork( (FKB *) fkb ); \ }/*H* The fork_lock macro is used to acquire a fork spinlock and to%* optionally save the original IPL.* )* The format of the fork_lock macro is:* #* fork_lock (lockidx, savipl_p)* * Inputs:* B* lockidx is the integer value of the spinlock index.* * Outputs:* H* savipl_p is a 32-bit integer passed by reference in w hichH* the original IPL is returned. If the address ofH* this parameter is NOSAVE_IPL, then the originalH* IPL is not returned. The symbol NOSAVE_IPL isH* defined to be a null pointer, i.e. ((int *) 0),1* by the vms_drivers.h file.* H* For example, one can take the UCB fork lock and store the original * IPL by:* /* fork_lock (ucb->ucb$b_flck, &orig_ipl);H* If there is no need to save the original IPL, then one can take the* fork lock by:* 0* fork_lock (ucb->ucb$b_flck, NOSAVE_IPL);*/(#define fork_lock(lockidx, savipl_p) \ { \( extern SMP smp$gl_flags; \+ extern int smp$al_iplvec[]; \ \* if(savipl_p != NOSAVE_IPL) \. *savipl_p = __PAL_MFPR_IPL(); \ \- if(smp$gl_flags.smp$v_enabled) \, smp_std$acquire( lockidx ); \  else \9 __PAL_MTPR_IPL( smp$al_iplvec[lockidx] ); \ }/*H* The fork_unlock macro is used to either release or restore (i.e.H* conditionally release) a fork spinlock and to optionally set a new* IPL.* +* The format of the fork_unlock macro is:* ,* fork_unlock (lockidx, newipl, restore)* * Inputs:* B* lockidx is the integer value of the spinlock index.* H* newipl is the integer value of t he desired new IPL orH* the value NOLOWER_IPL if the IPL should be leftH* unchanged. The symbol NOLOWER_IPL is defined to7* be -1 by the vms_drivers.h file.* H* restore is the either the integer value SMP_RESTORE orH* SMP_RELEASE. If SMP_RELEASE is specified thenH* the spinlock is unconditionally released byH* calling SMP_STD$RELEASE, ! otherwise the spinlockH* is conditionally released by callingH* SMP_STD$RESTORE. The symbol SMP_RESTORE isH* defined to be 1 and the symbol SMP_RELEASE isA* defined to be 0 by the vms_drivers.h file.* H* For example, one can conditionally release the UCB fork lock and set * IPL by:* =* fork_unlock (ucb->ucb$b_flck, orig_ipl, SMP_RESTORE);* H* If there is no need t"o change IPL, then one can conditionally* release the fork lock by:* @* fork_unlock (ucb->ucb$b_flck, NOLOWER_IPL, SMP_RESTORE);*/0#define fork_unlock(lockidx, newipl, restore) \ { \( extern SMP smp$gl_flags; \ \/ if(smp$gl_flags.smp$v_enabled) { \+ if(restore == SMP_RELEASE) \. smp_std$release( lockidx ); \ else \. smp_std$restore( lockidx ); \ # } \ if(newipl >= 0) \+ __PAL_MTPR_IPL( newipl ); \ }/*G* The ucb_lock macro is used to acquire a fork or device spinlock and(* to optionally save the original IPL.* (* The format of the ucb_lock macro is:* )* ucb_lock (ucb, raise_ipl, savipl_p)* * Inputs:* 5* ucb is address of a UCB structure.* J* raise_ipl is either the integer value RAISE_IPL orJ* N $ORAISE_IPL. The symbol RAISE_IPL is defined to beJ* 1 and the symbol NORAISE_IPL is defined to be 0 byJ* the vms_drivers.h file. If raise_ipl is equal toJ* RAISE_IPL, then the IPL is set using the value in.* the spinlock structure.* * Outputs:* H* savipl_p is a 32-bit integer passed by reference in whichH* the original IPL is returned. If the address ofH* % this parameter is NOSAVE_IPL, then the originalH* IPL is not returned. The symbol NOSAVE_IPL isH* defined to be a null pointer, i.e. ((int *) 0),1* by the vms_drivers.h file.* *//#define ucb_lock(ucb, raise_ipl, savipl_p) \ { \* extern SMP smp$gl_flags; \- extern int smp$al_iplvec[]; \) extern SPL_PPL smp$ar_spnlkvec; \ \- & if (savipl_p != NOSAVE_IPL) \0 *savipl_p = __PAL_MFPR_IPL(); \ \/ if (raise_ipl == NORAISE_IPL) \ { \2 if (smp$gl_flags.smp$v_enabled) \ { \2 if (ucb->ucb$b_flck < SPL$_MIN_INDEX) \: smp_std$acqnoipl( ucb->ucb$l_dlck ); \ else \P smp_std$acqnoipl( (SPL *)smp$ar_spnlkvec[ucb->ucb$b_flck] ); \ } \ } \ ' else \ { \2 if (smp$gl_flags.smp$v_enabled) \ { \2 if (ucb->ucb$b_flck < SPL$_MIN_INDEX) \: smp_std$acquirel( ucb->ucb$l_dlck ); \ else \9 smp_std$acquire( ucb->ucb$b_flck ); \ } \ else \C __PAL_MTPR_IPL( smp$al_iplvec[ucb->ucb$b_flck] ); \ } \ }/*C* The ucb_unlock macro is used to eith(er release or restore (i.e.K* conditionally release) a fork or device spinlock and to optionally set * a new IPL.* ** The format of the ucb_unlock macro is:* '* ucb_unlock (ucb, newipl, restore)* * Inputs:* 9* ucb is the address of a UCB structure.* H* newipl is the integer value of the desired new IPL orH* the value NOLOWER_IPL if the IPL should be leftH* unchanged. The symbol NOLOWE )R_IPL is defined to7* be -1 by the vms_drivers.h file.* H* restore is the either the integer value SMP_RESTORE orH* SMP_RELEASE. If SMP_RELEASE is specified thenH* the spinlock is unconditionally released byH* calling SMP_STD$RELEASE, otherwise the spinlockH* is conditionally released by callingH* SMP_STD$RESTORE. The sym*bol SMP_RESTORE isH* defined to be 1 and the symbol SMP_RELEASE isA* defined to be 0 by the vms_drivers.h file.* */-#define ucb_unlock(ucb, newipl, restore) \ { \* extern SMP smp$gl_flags; \- extern int smp$al_iplvec[]; \) extern SPL_PPL smp$ar_spnlkvec; \ \0 if (smp$gl_flags.smp$v_enabled) \ { \/ if (restore == SMP_RELEASE) + \ { \2 if (ucb->ucb$b_flck < SPL$_MIN_INDEX) \: smp_std$releasel( ucb->ucb$l_dlck ); \ else \9 smp_std$release( ucb->ucb$b_flck ); \ } \ else \ { \2 if (ucb->ucb$b_flck < SPL$_MIN_INDEX) \: smp_std$restorel( ucb->ucb$l_dlck ); \ else \9 smp_std$restore( ucb->ucb$b_flck ); \ } \ , } \ \# if (newipl >= 0) \- __PAL_MTPR_IPL( newipl ); \ }/*H* The fork_wait macro is used to queue a specified fork routine withH* specified fork routine parameters for delayed execution. After theH* fork routine is queued, execution continues with the next statement* following the fork macro.* )* The format of the fork_wait macro is:* -* fork_wait (fork_routine, fr3, fr4, fkb)* * Inputs: -* H* fork_routine is the procedure value of the routine that is toH* be executed in a fork thread. This value isH* passed to the fork dispatcher via fkb->fkb$l_fpc.* H* fr3 is the 64-bit value to pass to the fork routineH* via fkb->fkb$q_fr3. This parameter is cast as a&* 64-bit integer.* H* fr4 is the 64-bit value to pass to the fork routineH* . via fkb->fkb$q_fr4. This parameter is cast as a&* 64-bit integer.* H* fkb is a pointer to the fork block. This parameter6* is cast as a pointer to an FKB.*/3#define fork_wait(fork_routine, fr3, fr4, fkb) \ { \8 ((FKB *) fkb)->fkb$l_fpc = fork_routine; \H exe_std$primitive_fork_wait( (__int64) fr3, (__int64) fr4, \; (FKB *) fkb/ ); \ }/*J* The iofork macro is used to queue a fork routine with specified forkJ* routine parameters. This macro is very similar to fork, except thatJ* the fork block is assumed to be a UCB and the ucb$v_tim bit is cleared&* before the fork routine is queued.* &* The format of the iofork macro is:* ** iofork (fork_routine, fr3, fr4, ucb)* * Inputs:* J* fork_routine is the procedure value of the routine that is to beJ* 0 executed in a fork thread. This value is passed to>* the fork dispatcher via ucb->ucb$l_fpc.* J* fr3 is the 64-bit value to pass to the fork routine viaJ* ucb->ucb$q_fr3. This parameter is cast as a 64-bit* integer.* J* fr4 is the 64-bit value to pass to the fork routine viaJ* ucb->ucb$q_fr4. This parameter is cast as a 64-bit* 1 integer.* J* ucb is a pointer to the unit control block. This?* parameter is cast as a pointer to a UCB.*/.#define iofork(fork_routine, fr3, fr4, ucb) \ { \, ((UCB *) ucb)->ucb$v_tim = 0; \2 fork( fork_routine, fr3, fr4, ucb); \ }/*J* The rfi macro can be used in an interrupt service routine to invokeJ* the resume from interrupt routine that has been set up by either theJ2* wfikpch or wfirlch macros. The interface for the resume from2* interrupt routine is described in section 4.7.* #* The format of the rfi macro is:* * rfi (irp, fr4, ucb)* * Inputs:* J* irp is a usually a pointer to an IRP type, but can beJ* any value which is expected as the first parameter<* of the resume from interrupt routine.* J* fr4 is any value which is exp3ected as the secondF* parameter of the resume from interrupt routine.* J* ucb is a pointer to a Unit Control Block and is theJ* third parameter of the resume from interruptJ* routine. This parameter is cast as a pointer to an* UCB.*/ #define rfi(irp, fr4, ucb) \7 ( *((UCB *) ucb)->ucb$l_fpc ) (irp, fr4, ucb)/*J* The wfikpch macro is used to setup 4 an interrupt resume routine and aJ* device interrupt timeout routine without releasing the channel (i.e. * CRB).* '* The format of the wfikpch macro is:* G* wfikpch (resume_rout, tout_rout, irp, fr4, ucb, tmo, restore_ipl)* * Inputs:* J* resume_rout is the procedure value of the resume from interruptJ* routine that is to be called by the interruptJ* service routine. This value is passed to t 5heJ* interrupt service routine via ucb->ucb$l_fpc. ThisJ* routine is discussed in sections 2.3, 4.7, and 5.6.* J* tout_rout is the procedure value of the device interruptJ* timeout routine that may be called by EXE$TIMEOUT.J* This value is passed via ucb->ucb$ps_toutrout.@* This routine is described in section 4.6.* J* irp is a pointer to an IR 6P type which is passed to theJ* interrupt resume or timeout routine via&* ucb->ucb$q_fr3.* J* fr4 is a 64-bit value to pass to the resume fromJ* interrupt or timeout routine via ucb->ucb$q_fr4.B* This parameter is cast as a 64-bit integer.* J* ucb is a pointer to a Unit Control Block. This@* parameter is cast as a po7inter to an UCB.* J* tmo is an integer specifying the timeout value in* seconds.* J* restore_ipl is an integer specifying the IPL to lower to prior$* to returning.* J* For example, a driver start I/O routine might use the wfikpch macro inJ* the following fashion, where start_device_xfer is a device specific&* routine implemented in the driver:* * {>* device_lock (ucb->ucb$l_dl 8ck, RAISE_IPL, &orig_ipl);)* start_device_xfer ( ucb, irp );E* wfikpch (resume_rout, tout_rout, irp, 0, ucb, 3, orig_ipl);* return; * }*/K#define wfikpch(resume_rout, tout_rout, irp, fr4, ucb, tmo, restore_ipl) \ { \7 ((UCB *) ucb)->ucb$l_fpc = resume_rout; \; ((UCB *) ucb)->ucb$ps_toutrout = tout_rout; \I ioc_std$primitive_wfikpch (irp, (__int64) fr4, (UCB *) ucb, \= 9 tmo, restore_ipl ); \ }/*J* The wfirlch macro is used to setup an interrupt resume routine and aJ* device interrupt timeout routine, and to release the channel (i.e. * CRB).* G* wfirlch (resume_rout, tout_rout, irp, fr4, ucb, tmo, restore_ipl)* J* The wfirlch macro works just like the wfikpch macro with the exceptionJ* that wfirlch calls routine IOC_STD$PRIMITIVE_WFIRLCH instead ofJ* IOC_STD$PRIMITIVE_WFIKPCH. In all other r :espects the description ofM* the parameters of the wfikpch macro in applies to the wfirlch macro.*/K#define wfirlch(resume_rout, tout_rout, irp, fr4, ucb, tmo, restore_ipl) \ { \7 ((UCB *) ucb)->ucb$l_fpc = resume_rout; \; ((UCB *) ucb)->ucb$ps_toutrout = tout_rout; \I ioc_std$primitive_wfirlch (irp, (__int64) fr4, (UCB *) ucb, \= tmo, restore_ipl ); \ } %/* Device dr ;iver table initialization1 * Map lower case function names into upper case */<#define driver$ini_ddt_altstart DRIVER$INI_DDT_ALTSTARTB#define driver$ini_ddt_aux_routine DRIVER$INI_DDT_AUX_ROUTINEB#define driver$ini_ddt_aux_storage DRIVER$INI_DDT_AUX_STORAGE8#define driver$ini_ddt_cancel DRIVER$INI_DDT_CANCELL#define driver$ini_ddt_cancel_selective DRIVER$INI_DDT_CANCEL_SELECTIVEK#define driver$ini_ddt_change_preferred DRIVER$INI_DDT_CHANGE_PREFERREDG#define < driver$ini_ddt_channel_assign DRIVER$INI_DDT_CHANNEL_ASSIGN>#define driver$ini_ddt_cloneducb DRIVER$INI_DDT_CLONEDUCB>#define driver$ini_ddt_configure DRIVER$INI_DDT_CONFIGURE<#define driver$ini_ddt_ctrlinit DRIVER$INI_DDT_CTRLINITB#define driver$ini_ddt_csr_mapping DRIVER$INI_DDT_CSR_MAPPINGB#define driver$ini_ddt_deconfigure DRIVER$INI_DDT_DECONFIGURE8#define driver$ini_ddt_diagbf DRIVER$INI_DDT_DIAGBF8#define driver$ini_ddt_erlgbf DRIVER$INI_DDT_ERLGBF=<#define driver$ini_ddt_fast_fdt DRIVER$INI_DDT_FAST_FDT:#define driver$ini_ddt_functab DRIVER$INI_DDT_FUNCTABB#define driver$ini_ddt_kp_reg_mask DRIVER$INI_DDT_KP_REG_MASKE#define driver$ini_ddt_kp_stack_size DRIVER$INI_DDT_KP_STACK_SIZE@#define driver$ini_ddt_kp_startio DRIVER$INI_DDT_KP_STARTIOD#define driver$ini_ddt_make_devpath DRIVER$INI_DDT_MAKE_DEVPATH<#define driver$ini_ddt_mntv_for DRIVER$INI_DDT_MNTV_FOR8#define driver$ini_ddt_mntver DRIVER$IN >I_DDT_MNTVER@#define driver$ini_ddt_pending_io DRIVER$INI_DDT_PENDING_IOB#define driver$ini_ddt_qsrv_helper DRIVER$INI_DDT_QSRV_HELPERK#define driver$ini_ddt_qsrv_evnt_notify DRIVER$INI_DDT_QSRV_EVNT_NOTIFYD#define driver$ini_ddt_mgt_register DRIVER$INI_DDT_MGT_REGISTERG#define driver$ini_ddt_mgt_deregister DRIVER$INI_DDT_MGT_DEREGISTER8#define driver$ini_ddt_regdmp DRIVER$INI_DDT_REGDMP@#define driver$ini_ddt_setprfpath DRIVER$INI_DDT_SETPRFPATH6#define ?driver$ini_ddt_start DRIVER$INI_DDT_START<#define driver$ini_ddt_unitinit DRIVER$INI_DDT_UNITINIT3#define driver$ini_ddt_end DRIVER$INI_DDT_END6#define driver$ini_dpt_adapt DRIVER$INI_DPT_ADAPT<#define driver$ini_dpt_bt_order DRIVER$INI_DPT_BT_ORDER8#define driver$ini_dpt_decode DRIVER$INI_DPT_DECODE<#define driver$ini_dpt_defunits DRIVER$INI_DPT_DEFUNITS:#define driver$ini_dpt_deliver DRIVER$INI_DPT_DELIVERD#define driver$ini_dpt_devpath_size DRIVER$ @INI_DPT_DEVPATH_SIZEI#define driver$ini_dpt_devpath_ucb_ofs DRIVER$INI_DPT_DEVPATH_UCB_OFSG#define driver$ini_dpt_dsplypath_size DRIVER$INI_DPT_DSPLYPATH_SIZEK#define driver$ini_dpt_dsplypath_ucb_of DRIVER$INI_DPT_DSPLYPATH_UCB_OF6#define driver$ini_dpt_flags DRIVER$INI_DPT_FLAGS>#define driver$ini_dpt_idb_crams DRIVER$INI_DPT_IDB_CRAMS>#define driver$ini_dpt_iohandles DRIVER$INI_DPT_IOHANDLES<#define driver$ini_dpt_maxunits DRIVER$INI_DPT_MAXUNITS<#define A driver$ini_dpt_max_unit DRIVER$INI_DPT_MAX_UNITO#define driver$ini_dpt_mpdev_path_swtch DRIVER$INI_DPT_MPDEV_PATH_SWTCH5#define driver$ini_dpt_name DRIVER$INI_DPT_NAME@#define driver$ini_dpt_struc_init DRIVER$INI_DPT_STRUC_INITD#define driver$ini_dpt_struc_reinit DRIVER$INI_DPT_STRUC_REINIT>#define driver$ini_dpt_ucb_crams DRIVER$INI_DPT_UCB_CRAMS:#define driver$ini_dpt_ucbsize DRIVER$INI_DPT_UCBSIZE8#define driver$ini_dpt_unload DRIVER$INI_DPT_UNLOAD B8#define driver$ini_dpt_vector DRIVER$INI_DPT_VECTOR3#define driver$ini_dpt_end DRIVER$INI_DPT_END3#define driver$ini_fdt_act DRIVER$INI_FDT_ACT5#define driver$ini_fdt_qsrv DRIVER$INI_FDT_QSRV3#define driver$ini_fdt_end DRIVER$INI_FDT_END%/* Device driver table initialization. * Declare initialization function prototypes */>int driver$ini_ddt_altstart( DDT *ddt, void (*func)() );Bint driver$ini_ddt_aux_routine( DDT *ddt, int ( *func )() );=Cint driver$ini_ddt_aux_storage( DDT *ddt, void *addr );>int driver$ini_ddt_cancel( DDT *ddt, void ( *func )() );Gint driver$ini_ddt_cancel_selective( DDT *ddt, int ( *func )() );Gint driver$ini_ddt_change_preferred( DDT *ddt, int ( *func )() );Fint driver$ini_ddt_channel_assign( DDT *ddt, void ( *func )() );@int driver$ini_ddt_cloneducb( DDT *ddt, int ( *func )() );@int driver$ini_ddt_configure( DDT *ddt, int ( *func )() );?int driver$ini_ddt_cDtrlinit( DDT *ddt, int ( *func )() );Bint driver$ini_ddt_csr_mapping( DDT *ddt, int ( *func )() );Bint driver$ini_ddt_deconfigure( DDT *ddt, int ( *func )() );Bint driver$ini_ddt_diagbf( DDT *ddt, unsigned short value );Bint driver$ini_ddt_erlgbf( DDT *ddt, unsigned short value );?int driver$ini_ddt_fast_fdt( DDT *ddt, int ( *func )() );7int driver$ini_ddt_functab( DDT *ddt, FDT *fdt );Fint driver$ini_ddt_kp_reg_mask( DDT *ddt, unsigned long value );EHint driver$ini_ddt_kp_stack_size( DDT *ddt, unsigned long value );Bint driver$ini_ddt_kp_startio( DDT *ddt, void ( *func )() );Cint driver$ini_ddt_make_devpath( DDT *ddt, int ( *func )() );?int driver$ini_ddt_mntv_for( DDT *ddt, int ( *func )() );?int driver$ini_ddt_mntver( DDT *ddt, void ( *func )() ); Eint driver$ini_ddt_mpdev_path_swtch( DDT *ddt, int ( *func )() ); Aint driver$ini_ddt_pending_io( DDT *ddt, int ( *func )() );Bint driver$iniF_ddt_qsrv_helper( DDT *ddt, int ( *func )() );Gint driver$ini_ddt_qsrv_evnt_notify( DDT *ddt, int ( *func )() );Cint driver$ini_ddt_mgt_register( DDT *ddt, int ( *func )() );Eint driver$ini_ddt_mgt_deregister( DDT *ddt, int ( *func )() );>int driver$ini_ddt_regdmp( DDT *ddt, void ( *func )() );Aint driver$ini_ddt_setprfpath( DDT *ddt, int ( *func )() );=int driver$ini_ddt_start( DDT *ddt, void ( *func )() );?int driver$ini_ddt_unitinit( DDT *ddt, i Gnt ( *func )() );)int driver$ini_ddt_end( DDT *ddt );@int driver$ini_dpt_adapt( DPT *dpt, unsigned long value );:int driver$ini_dpt_bt_order( DPT *dpt, long value );8int driver$ini_dpt_decode( DPT *dpt, long value );Dint driver$ini_dpt_defunits( DPT *dpt, unsigned short value );>int driver$ini_dpt_deliver( DPT *dpt, int ( *func )() );Gint driver$ini_dpt_devpath_size( DPT *dpt, unsigned long value );Jint driver$ini_dpt_devpath_ucb_ofs( DPT *dptH, unsigned long value );Iint driver$ini_dpt_dsplypath_size( DPT *dpt, unsigned long value );Kint driver$ini_dpt_dsplypath_ucb_of( DPT *dpt, unsigned long value );@int driver$ini_dpt_flags( DPT *dpt, unsigned long value );Eint driver$ini_dpt_idb_crams( DPT *dpt, unsigned short value );Eint driver$ini_dpt_iohandles( DPT *dpt, unsigned short value );Dint driver$ini_dpt_maxunits( DPT *dpt, unsigned short value );Cint driver$ini_dpt_max_unit( DPT *dpt, u Insigned long value );<int driver$ini_dpt_name( DPT *dpt, char *string_ptr );Bint driver$ini_dpt_struc_init( DPT *dpt, void ( *func )() );Dint driver$ini_dpt_struc_reinit( DPT *dpt, void ( *func )() );Eint driver$ini_dpt_ucb_crams( DPT *dpt, unsigned short value );Cint driver$ini_dpt_ucbsize( DPT *dpt, unsigned short value );=int driver$ini_dpt_unload( DPT *dpt, int ( *func )() );>int driver$ini_dpt_vector( DPT *dpt, void( **func )() );)int dr Jiver$ini_dpt_end( DPT *dpt );oint driver$ini_fdt_act( FDT *fdt, unsigned long iofunc, int ( *action )(), unsigned long buf_64_flags );Pint driver$ini_fdt_qsrv( FDT *fdt, unsigned long iofunc, int qsrv_mask );)int driver$ini_fdt_end( FDT *fdt );%/* Device driver table initializationO * Define symbols that should be used for the buf_64_flags parameter passed toI * the driver$ini_fdt_act() macro. The buf_64_flags parameter specifiesM * whether the function is "buffeKred" or "direct" as well as if the function. * supports a 64-bit $QIO P1 parameter value. */#define FDT_BUFFERED 1#define FDT_NOT_BUFFERED 0#define FDT_DIRECT 0#define __FDT_64 29#define FDT_BUFFERED_64 (FDT_BUFFERED | __FDT_64)9#define FDT_NOT_BUFFERED_64 (FDT_NOT_BUFFERED | __FDT_64)9#define FDT_DIRECT_64 (FDT_DIRECT | __FDT_64)%/* Device driver table initialization; * Define macros corresponding to each of the driver tableB * initialization functio Lns that invoke the function and continue@ * if it returns success status; else, return the error status. */)#define ini_ddt_altstart( ddt, func ) { \ int _status; \a if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_altstart( ddt, func ))) return _status; },#define ini_ddt_aux_routine( ddt, func ) { \ int _status; \d if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_aux_routine( ddt, func ))) return _status; },#define ini_ddt_aux_storage( ddt, addr ) { \ in Mt _status; \d if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_aux_storage( ddt, addr ))) return _status; }'#define ini_ddt_cancel( ddt, func ) { \ int _status; \_ if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_cancel( ddt, func ))) return _status; }1#define ini_ddt_cancel_selective( ddt, func ) { \ int _status; \i if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_cancel_selective( ddt, func ))) return _status; }1#define ini_ddt_change_preferred( ddt, N func ) { \ int _status; \i if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_change_preferred( ddt, func ))) return _status; }/#define ini_ddt_channel_assign( ddt, func ) { \ int _status; \g if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_channel_assign( ddt, func ))) return _status; }*#define ini_ddt_cloneducb( ddt, func ) { \ int _status; \b if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_cloneducb( ddt, func ))) return _status; }*#define ini_ Oddt_configure( ddt, func ) { \ int _status; \b if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_configure( ddt, func ))) return _status; })#define ini_ddt_ctrlinit( ddt, func ) { \ int _status; \a if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_ctrlinit( ddt, func ))) return _status; },#define ini_ddt_csr_mapping( ddt, func ) { \ int _status; \d if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_csr_mapping( ddt, func ))) return _status; },#define in Pi_ddt_deconfigure( ddt, func ) { \ int _status; \d if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_deconfigure( ddt, func ))) return _status; })#define ini_ddt_diagbf( ddt, value ) { \ int _status; \a if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_diagbf( ddt, value ))) return _status; })#define ini_ddt_erlgbf( ddt, value ) { \ int _status; \a if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_erlgbf( ddt, value ))) return _status; })#define Qini_ddt_fast_fdt( ddt, func ) { \ int _status; \a if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_fast_fdt( ddt, func ))) return _status; }'#define ini_ddt_functab( ddt, fdt ) { \ int _status; \_ if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_functab( ddt, fdt ))) return _status; }-#define ini_ddt_kp_reg_mask( ddt, value ) { \ int _status; \e if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_kp_reg_mask( ddt, value ))) return _status; }/#defin Re ini_ddt_kp_stack_size( ddt, value ) { \ int _status; \g if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_kp_stack_size( ddt, value ))) return _status; }+#define ini_ddt_kp_startio( ddt, func ) { \ int _status; \c if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_kp_startio( ddt, func ))) return _status; }-#define ini_ddt_make_devpath( ddt, func ) { \ int _status; \e if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_make_devpath( ddt, func ))) return S _status; })#define ini_ddt_mntv_for( ddt, func ) { \ int _status; \a if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_mntv_for( ddt, func ))) return _status; }'#define ini_ddt_mntver( ddt, func ) { \ int _status; \_ if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_mntver( ddt, func ))) return _status; }1#define ini_ddt_mpdev_path_swtch( ddt, func ) { \ int _status; \i if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_mpdev_path_swtch( ddt, func T))) return _status; }+#define ini_ddt_pending_io( ddt, func ) { \ int _status; \c if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_pending_io( ddt, func ))) return _status; },#define ini_ddt_qsrv_helper( ddt, func ) { \ int _status; \d if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_qsrv_helper( ddt, func ))) return _status; }1#define ini_ddt_qsrv_evnt_notify( ddt, func ) { \ int _status; \i if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_qsrv_e Uvnt_notify( ddt, func ))) return _status; }-#define ini_ddt_mgt_register( ddt, func ) { \ int _status; \e if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_mgt_register( ddt, func ))) return _status; }/#define ini_ddt_mgt_deregister( ddt, func ) { \ int _status; \g if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_mgt_deregister( ddt, func ))) return _status; }'#define ini_ddt_regdmp( ddt, func ) { \ int _status; \_ if( !$VMS_STATUS_SUCCESS( _status V= driver$ini_ddt_regdmp( ddt, func ))) return _status; }+#define ini_ddt_setprfpath( ddt, func ) { \ int _status; \c if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_setprfpath( ddt, func ))) return _status; }&#define ini_ddt_start( ddt, func ) { \ int _status; \^ if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_start( ddt, func ))) return _status; })#define ini_ddt_unitinit( ddt, func ) { \ int _status; \a if( !$VMS_STATUS_SUCCESS( _status = drive Wr$ini_ddt_unitinit( ddt, func ))) return _status; }#define ini_ddt_end( ddt ) { \ int _status; \V if( !$VMS_STATUS_SUCCESS( _status = driver$ini_ddt_end( ddt ))) return _status; }'#define ini_dpt_adapt( dpt, value ) { \ int _status; \_ if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_adapt( dpt, value ))) return _status; }*#define ini_dpt_bt_order( dpt, value ) { \ int _status; \b if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_bt_order( dpt, value X ))) return _status; }(#define ini_dpt_decode( dpt, value ) { \ int _status; \` if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_decode( dpt, value ))) return _status; }*#define ini_dpt_defunits( dpt, value ) { \ int _status; \b if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_defunits( dpt, value ))) return _status; }(#define ini_dpt_deliver( dpt, func ) { \ int _status; \` if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_deliver( dpt, func ))) retur Yn _status; }.#define ini_dpt_devpath_size( dpt, value ) { \ int _status; \f if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_devpath_size( dpt, value ))) return _status; }1#define ini_dpt_devpath_ucb_ofs( dpt, value ) { \ int _status; \i if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_devpath_ucb_ofs( dpt, value ))) return _status; }0#define ini_dpt_dsplypath_size( dpt, value ) { \ int _status; \h if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_ds Zplypath_size( dpt, value ))) return _status; }2#define ini_dpt_dsplypath_ucb_of( dpt, value ) { \ int _status; \j if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_dsplypath_ucb_of( dpt, value ))) return _status; }'#define ini_dpt_flags( dpt, value ) { \ int _status; \_ if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_flags( dpt, value ))) return _status; }+#define ini_dpt_idb_crams( dpt, value ) { \ int _status; \c if( !$VMS_STATUS_SUCCESS( _status = [ driver$ini_dpt_idb_crams( dpt, value ))) return _status; }+#define ini_dpt_iohandles( dpt, value ) { \ int _status; \c if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_iohandles( dpt, value ))) return _status; }+#define ini_dpt_maxunits( dpt, value ) { \ int _status; \c if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_maxunits( dpt, value ))) return _status; }+#define ini_dpt_max_unit( dpt, value ) { \ int _status; \c if( !$VMS_STATUS_SUCCESS( \_status = driver$ini_dpt_max_unit( dpt, value ))) return _status; }+#define ini_dpt_name( dpt, string_ptr ) { \ int _status; \c if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_name( dpt, string_ptr ))) return _status; }+#define ini_dpt_struc_init( dpt, func ) { \ int _status; \c if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_struc_init( dpt, func ))) return _status; }-#define ini_dpt_struc_reinit( dpt, func ) { \ int _status; \e if( !$VMS_STAT ]US_SUCCESS( _status = driver$ini_dpt_struc_reinit( dpt, func ))) return _status; },#define ini_dpt_ucb_crams( dpt, value ) { \ int _status; \d if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_ucb_crams( dpt, value ))) return _status; }*#define ini_dpt_ucbsize( dpt, value ) { \ int _status; \b if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_ucbsize( dpt, value ))) return _status; }'#define ini_dpt_unload( dpt, func ) { \ int _status; \_ if( !$VMS_ ^STATUS_SUCCESS( _status = driver$ini_dpt_unload( dpt, func ))) return _status; }'#define ini_dpt_vector( dpt, func ) { \ int _status; \_ if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_vector( dpt, func ))) return _status; }#define ini_dpt_end( dpt ) { \ int _status; \V if( !$VMS_STATUS_SUCCESS( _status = driver$ini_dpt_end( dpt ))) return _status; }:#define ini_fdt_act( fdt, func, action, buf_64_flags ) { \ int _status; \x if( !$VMS_STATUS_SUCCESS( __status = driver$ini_fdt_act( fdt, func, action, FDT_##buf_64_flags ))) return _status; }0#define ini_fdt_qsrv( fdt, func, qsrv_mask ) { \ int _status; \h if( !$VMS_STATUS_SUCCESS( _status = driver$ini_fdt_qsrv( fdt, func, qsrv_mask ))) return _status; }#define ini_fdt_end( fdt ) { \ int _status; \V if( !$VMS_STATUS_SUCCESS( _status = driver$ini_fdt_end( fdt ))) return _status; }!#endif /* __VMS_DRIVERS_LOADED */ww ZU#ifndef __VMS_MACROS_LOADED `#define __VMS_MACROS_LOADED 1*/* module VMS_MACROS.H "X-94" */O/* ************************************************************************* */O/* * * */O/* * HPE CONFIDENTIAL. This software is confidential proprietary software * */O/* * licensed by Hewlett Packard Enterprise Development, LP, and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without the * */O/* * prior wriatten permission of HPE. * */O/* * Copyright 2019 Hewlett Packard Enterprise Development, LP * */O/* * * */O/* * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential * */O/* * proprietary software licensed by VMS Software, Inc., and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without * */O/* * the prior written permibssion of VMS Software, Inc. * */O/* * Copyright 2019-2021 VMS Software, Inc. * */O/* * * */O/* ************************************************************************* *//**++ * FACILITY:** VMS Executive (LIB_H)* * ABSTRACT:*O* This header file will provide a basic set of C macros for system programmersM* to hide some particularly ugly things ocr for commonly used functions whichN* are somewhat performance sensitive. These macros should be very simple (notL* that C would let you get away with anything else). If complex, reconsiderK* creating a new exec routine to perform the function rather than a macro.* * AUTHOR:** Steve DiPirro*"* CREATION DATE: 17-Feb-1993** MODIFICATION HISTORY:*)* X-94 GHJ Gregory H. Jordan 9-Jun-2021>* The lock_cpu_mutex and unlock_cpu_mutex macros incorrectly >* compu dted a signed longword delta time. If bit 31 was set, <* then the call to exe$timedwait_setup computed a end_time :* in the past. If exe$timedwait_complete was called, it 3* would always indicate the end time was exceeded.*C* X-93 CEG0922 Clair Grant 28-Sep-2020<* Change comments in NOT_X86_READY to use "\" *C* X-92 CEG0920 Clair Grant 25-Sep-20205* Change comment in X-91 *)* Xe-91 CEG0911 Clair Grant 24-Sep-2020** Replace "// comment" style to eliminate+* confusion when compiling /STANDARD=VAXC.*(* X-90 CEG0840 Clair Grant 04-Dec-2019* Fix build bug in X-89*(* X-89 CEG0836 Clair Grant 23-Nov-2019 * Add VMS$GET_GR and VMS$SET_GR*"* X-88 AHM Drew Mason 7-Jun-20194* Change the x86 definition of VMS$GET_TIMESTAMP to* read the TSC not the HPET.*/* X-87 CV-0334 Camiel Vanderhoeven 12-Apr-2019 * Fix typo in previous checkin.*.* X-86 f CV-0329 Camiel Vanderhoeven 9-Apr-2019* Use sys$pal_read_unq on x86.*"* X-85 RCL Rick Lord 14-Mar-20192* Add $pa_to_pfn to convert a PA to a PFN. Since :* MMG$$C_PA_TO_PFN_SHIFT is now defined in MMG_CONSTANTS,7* use it and delete local symbol PFN_TO_PA_SHIFT. Move6* #include of mmg_constants to an unconditional block(* to support Alpha and IA64 $pa_to_pfn.*)* X-84 GHJ Gregory H. Jordan 20-Feb-20197* Update $$bpte_va to handle a bottom PTE pointing to .* the top levelg page table self map pointers.*(* X-83 CEG0675 Clair Grant 07-Feb-2019:* Update VMS$PREV_INVO_END and add VMS$INIT_INVO_CONTEXT.*(* X-82 CEG0667 Clair Grant 06-Feb-2019<* Add VMS$GET_CURR_INVO_CONTEXT, VMS$GET_PREV_INVO_CONTEXT,* and VMS$PREV_INVO_END macros*(* X-81 CEG0659 Clair Grant 19-Jan-2019* Add VMS$SET_THREADENV(X)*!* X-80 RCL Rick Lord 7-Jan-2019* Add macro not_x86_ready()*+* X-79 PAJ1681 Paul A. Jacobi 09-Nov-2018:* Fix bug_check macro to genehrate the same code on X86 as>* IA64. The X86 version will probably diverge in the future.* Fix VDE ident.* (* X-77 MJM Michael Moroney 20-Sep-2018=* Define $insert_pfn( pte, pfn ) macro to insert PFN in PTE.*(* X-76 MJM Michael Moroney 13-Sep-20185* Add parenthesis to argument for $extract_pfn() and;* $pfn_to_pa() to prevent syntax error on macro expansion.*)* X-75 GHJ Gregory H. Jordan 21-Aug-2018;* Some code defines mmg$gl_vpn_to_va and a uint32 and some;* as ia uint64... Stop attempting to define in VMS_MACROS.H* and hard code for now.*)* X-74 GHJ Gregory H. Jordan 21-Aug-20186* Define mmg$gl_vpn_to_va in the static routines used* to conert a pfn to a pa.* )* X-73 GHJ Gregory H. Jordan 20-Aug-2018<* Add macros for Extracting a PFN from a PTE, Converting a 9* pfn to a PA, and extracting a PA from a PTE. For X86,9* there are variants to operate on 2mb and 1G ptes/pfns.*)* X-72 GHJ Gregory H. Jordan 1-Aug-2018+* Make ja fix for the TEST$MMG environment.*#* X-71 AHM Drew Mason 16-Jul-20182* Fix bug in bpte_va that caused SYSBOOT to fail.*)* X-70 GHJ Gregory H. Jordan 11-Jul-2018;* Add the bpte_va macro vms_macros as it will be valid for* use in all architectures.* )* X-69 GHJ Gregory H. Jordan 27-Jun-2018* Add VA2PA_64 macro.*)* X-68 GHJ Gregory H. Jordan 11-Jun-20186* Add an include of mmg_constants for the X86 variant* of $$$va_pte_to_va.*)* X-67 GHJ Gregory H. Jordan k 5-Jun-2018* Update VA_PTE_TO_VA for X86.*)* X-66 GHJ Gregory H. Jordan 16-May-20188* The $write_pte macro is moving to PTE_FUNCTIONS.H to <* avoid the need for this module to pull in PTE_FUNCTIONS.H?* for Alpha. That resulted in some conflicting symbol * definitions in the build.*)* X-65 GHJ Gregory H. Jordan 16-May-2018>* Add the $write_pte macro with archiecture specific actions * for X86, IA64, and Alpha.*(* X-64 CEG0416 Clair Grant 13-Apr-2018* Makle PLDEF IA64 only*(* X-63 CEG0414 Clair Grant 12-Apr-2018-* Fix VMS$GET_THREADENV() for Alpha and IA64*/* X-62 CV-0161 Camiel Vanderhoeven 12-Apr-20183* Replace C++ style comments with C style ones for'* modules compiled with /STANDARD=VAXC*(* X-61 CEG0401 Clair Grant 09-Apr-2018"* Added VMS$GET_THREADENV() macro*(* X-60 CEG0384 Clair Grant 28-Mar-2018* Include far_pointers for x86*(* X-59 CEG0383 Clair Grant 26-Mar-2018 * Fix another build bug in X-57m*(* X-58 CEG0382 Clair Grant 26-Mar-2018* Fix build bug in X-57*(* X-57 CEG0375 Clair Grant 26-Mar-2018* Added VMS$GET_TIMESTAMP()*/* X-56 CV-0146 Camiel Vanderhoeven 15-Mar-2018=* Add VMS$GET_PREVMODE() macros for all three architectures.*/* X-55 CV-0108 Camiel Vanderhoeven 13-Feb-20187* Fix use of PSLDEF when __NEW_STARLET is not defined.*/* X-54 CV-0106 Camiel Vanderhoeven 12-Feb-2018<* Add VMS$GET_CURMODE() macros for all three architectures.*(* X-53 CnEG0348 Clair Grant 25-Jan-2018* Verified a conditional*"* X-52 AHM Drew Mason 1-Dec-2017<* Revert changes made in X-51 to mmg$gq_s0base_pte_address.7* Made several VA- and PTE-related macros into dummies+* for x86 because they won't exist on x86.-* One more conditional still to be verified.*"* X-51 AHM Drew Mason 7-Nov-20172* Update copyright. Add definition of __RUNCONST,* to allow SYSBOOT to write the "constants"1* used here. Change mmg$gq_s0s1base_pte_address4 o* to mmg$gq_s0base_pte_address for x86 only. Added9* module IDENT. More conditionals still to be verified.*/* X-50 CV-0053 Camiel Vanderhoeven 03-Oct-20173* kriprdef is ia64 only. Exclude from x86 version.*:* X-49 CEG0288 Clair Grant 13-Sep-2017D* Verified some conditionals for x86 port. More to do.*:* X-48 CEG0234 Clair Grant 18-Jul-2017<* Create a temporary, empty bug_check for x86.*$* X-47 DAG Doug Gorpdon 2-Nov-20161* Noticed that the X-45 changes were outside the6* __VMS_MACROS_LOADED conditional. Move them in. (But9* obviously no one has included this file multiple times* since 2004!)*)* X-46 CMOS Christian Moser 24-FEB-2005@* Rewrite the LOCK_CPU_MUTEX and UNLOCK_CPU_MUTEX to match what?* the Macro32 macro does to acquire and release the CPU mutex.:* Only use a single atomic update operation to avoid some* fairness issues.*!* X-45 Clair Grant 02-Apr-2004q* Add "atomic" macros*)* X-44 CMOS Christian Moser 7-SEP-2003&* Add EXC_PRINT for exception tracing*!* X-43 Clair Grant 01-Nov-2002%* builtins.h must precede kriprdef.h*"* X-42 Burns Fisher 31-Oct-2002 * KRIPRDEF include is IA64-only*"* X-41 Burns Fisher 30-Oct-20029* Use KRs for get_cpu_data and add get_slot_va for IA64.*!* X-40 Clair Grant 23-Jul-20027* We won't be calling a service to bugcheck so replace:* sys$pal_bugchk with the __PAL_BUGCHK buriltin which uses * a break instruction directly.*** X-39 KLN3080 Karen L. Noel 18-Jul-2002 * o Fix lower case conditional.3* o Reset ident numbering to match source control.*3* X-37A1A4 KLN3048 Karen L. Noel 28-Mar-20026* o Avoid assigning a 64-bit pointer to a 32-bit int.(* o Conditionalize Alpha specific code.2* o Require /pointer_size to use 64-bit pointers.*** X-41 KLN3037 Karen L. Noel 13-Mar-20025* Inline static routines so compiler doesn't mess up* inistialization routines.*** X-40 KLN3035 Karen L. Noel 11-Mar-20024* Remove arch_defs.h and change conditionals to use3* __ALPHA and __ia64. Including arch_defs.h breaks4* XFC and perhaps other code that does conditionals* a different way.*** X-39 KLN3025 Karen L. Noel 26-Feb-20020* o Conditionalize MTPR/MFPR macro definitions.0* o Cast new_ipl in sys_unlock macro to get rid* of compiler informational.0* o Make two page table spaces per IA64 region.5* o Call sys$pal_ tbugchk for IA64 in bug_check macro.>* o Fix comment for sys_lock_nospin to indicate SS$_LOCKINUSE* can be returned.C* o Remove inline pragmas. We trust the compiler now.*)* X-38 CMOS Christian Moser 10-JAN-20027* Update comment for TR_PRINT macro to include example+* usage based on popular feedback request.*)* X-37 CMOS Christian Moser 26-JUN-20019* Add new TR_PRINT macro, which can be used as a general=* purpose debug aid in combination with TR$DEBUG uand TR$SDA.*%* X-36 JRK Jim Kauffman 6-Nov-2000* Fix CPU mutex deadlock*)* X-35 CMOS Christian Moser 16-AUG-19996* Add new SYS_LOCK and SYS_UNLOCK variants to support!* sharelocks and nospin locking.*(* X-34 RAB Richard A. Bishop 9-Apr-1999<* Make bug_check macro use some names that aren't so likely&* to clash with customer definitions.*2* X-33 PAJ0988 Paul A. Jacobi 16-Jun-1998?* Define BUGCHK_POWEROFF for use with BUG_CHECK macro. Update@* module vIDENT to match VDE. Fold of X-28A1 from BLIZZARD_FT1.*)* X-30 KLN2084 Karen L. Noel 5-Jun-19984* Protect the sys_lock macro so that it can be used9* properly within a module compiled for 64-bit pointers.*** X-29 KLN2077 Karen L. Noel 20-May-19987* Add "int" to declaration in bug_check macro so the C8* compiler doesn't complain when using level4 checking.*)* X-28 CMOS Christian Moser 27-APR-1998;* Replace bug_check macro to generate inline bugcheck with:* correct PAL wcode instruction, instead of calling routine1* EXE$GEN_BUGCHK to generate an inline bugcheck.*(* X-27 JRK388 Jim Kauffman 4-Nov-1997=* Fix bug_check usage in lock_cpu_mutex and unlock_cpu_mutex*** X-26 KLN1570 Karen L. Noel 18-Jul-19963* Fix calls to TBI_DATA* routines so that the call4* entry points are used instead of the JSB entries.*&* X-25 SDD Steve DiPirro 26-Apr-1996@* Fix exe$gen_bugchk parameter declarations to be more standard"* and to avoid the DECC V5.3 buxg.*-* X-24 NYK521 Nitin Y. Karkhanis 30-Nov-1995:* Add macros to fetch contents of item list entry fields.*-* X-23 EMB0381 Ellen M. Batbouta 03-Oct-1995:* Add NO_PCB symbol to TBI_DATA_64 and TBI_SINGLE macros.*-* X-22 NYK326 Nitin Y. Karkhanis 30-Mar-19956* Cast PTE pointers to integers before performing any;* arithmetic. (In va_pte_to_svapte and svapte_to_va_pte.)*-* X-21 EMB0355 Ellen M. Batbouta 08-Mar-19955* Add TB invalidate macros, TBI_ALL, TBI_SINGLE, andy* TBI_DATA_64.*-* X-20 NYK251 Nitin Y. Karkhanis 1-Feb-19958* Removed 64B_REVISIT for PTE_VA macro since the newest9* generation of the C compiler that's coupled with Theta** correctly evaluates 64-bit expressions.<* Added const to all extern system data cells declarations.*-* X-19 NYK231 Nitin Y. Karkhanis 27-Jan-1995<* Add new routines to convert a VA_PTE to a SVAPTE and vice * versa.=* Replaced instances of __unsigned int64 with uint64 for the* PTE macros only. z*0* X-18 LSS0314 Leonard S. Szubowicz 10-Jan-1995?* Handle multiple inclusions of this header file gracefully by&* doing nothing after the first time.*-* X-17 NYK102 Nitin Y. Karkhanis 10-Nov-1994<* Temporarily make pte_va an inline routine. This was doneA* to work around some compiler problems with 64-bit expressions.*0* X-16 NYK075 Nitin Y. Karkhanis 17-Oct-1994?* The presence of access_backpointer and establish_backpointer8* in this header file resulted in too much {pain for the=* build. Access_backpointer, decref, establish_backpointer,>* incref, is_encumbered, and pfn_to_entry therefore have beenA* moved to [LIB_H]PFN_MACROS.H. The VA_PTE_TO_VA inline routine.* need the static qualifer on its definition.*-* X-15 NYK073 Nitin Y. Karkhanis 14-Oct-19947* MMG$GQ_LEVEL_WIDTH and MMG$GQ_NON_VA_MASK need to be8* declared within inline routine establish_backpointer.*-* X-14 NYK072 Nitin Y. Karkhanis 13-Oct-19947* Safe to include access_ba |ckpointer routine since the8* system data cells it uses have now been defined. The?* inclusion of the routine ended up being a separate edit from<* X-13 since the symbols were defined (in SYSLNK.OPT, etc.)"* after edit X-13 hit the "pack".*-* X-13 NYK071 Nitin Y. Karkhanis 13-Oct-19947* Update PTE macros according to code review comments.* Add PFN macros.*-* X-12 NYK055 Nitin Y. Karkhanis 19-Sep-19944* MMG$GL_PAGE_SIZE in va_pte_to_va should really be* MMG$GQ_PAGE_SIZ }E.*-* X-11 NYK046 Nitin Y. Karkhanis 14-Sep-1994=* Adding paging equation macros (l1pte_va, l2pte_va, pte_va,A* va_pte_to_va- routine). Also changed pfn_to_entry macro since>* the shift is no longer viable. PFN database entry size has3* grown for 64-bits and is no longer a power of 2.*&* X-10 SDD Steve DiPirro 18-Aug-1994@* Some idiot screwed up all the va/vpn conversion macros for P0A* space using a nonexistent (and unneeded) mask symbol. Oh yeah, * that was me. What a~ surprise.*%* X-9 SDD Steve DiPirro 23-May-1994:* Extern declaration of smp$gl_flags should use same type2* as in VMS_DRIVERS.H (type SMP rather than int).*%* X-8 SDD Steve DiPirro 27-Jan-1994=* Function prototypes defined here are obsolete and conflict=* with the actual definitions now available in other include * files.*%* X-7 SDD Steve DiPirro 08-Nov-1993:* Fixed sys_unlock to restore IPL, even when SMP enabled.*%* X-6 SDD Steve DiPirro 08-Sep-19938* Added vms_assert, good_status, and bad_status macros.4* Fixed sys_lock problem accessing spinlock vector.*%* X-5 SDD Steve DiPirro 26-Aug-19938* Fixed sys_lock and sys_unlock references to SPL$C_xxx,* symbols causing new compilation problems.*%* X-4 SDD Steve DiPirro 18-Aug-19936* Fixed (erroneous) extra level of indirection in the* bug_check macro.*%* X-3 SDD Steve DiPirro 09-Jun-1993:* I'm an idiot. Fix the case of constants used by macros.;* Fix sys_lock to allow defaulting of saved_ipl parameter.>* Make bugcheck code references consistent across the macros.*%* X-2 SDD Steve DiPirro 30-Apr-1993* Added new bug_check macro.**--*//*< Include any header files we need to make these macros work*/<#ifdef __ALPHA /* Verified for x86 port - Clair Grant */#include #include #endif#include union _PS { unsigned __int64 quad;#ifdef __NEW_STARLET PSLDEF fields;#else union psldef fields;#endif};D#ifdef __ALPHA /* Verified for x86 port - Camiel Vanderhoeven */ #define PL$C_KERNEL PSL$C_KERNEL#define PL$C_EXEC PSL$C_EXEC#define PL$C_SUPER PSL$C_SUPER#define PL$C_USER PSL$C_USER#endif#include #include ;#ifdef __ia64 /* Verified for x86 port - Clair Grant */#include #include #include #endif=#ifdef __x86_64 /* Verified for x86 port - Clair Grant */#include #include )extern UINT64_PQ exe$gqp_hpet_counter_va;#endifF/* This construct allows SYSBOOT write access to variables that are */F/* run-time constants, but need to be initialized at boot time. */#ifdef __SYSBOOT#define __RUNCONST/#define VMS_MACROS$PTE_LEVELS boo$gq_pte_levels-#define VMS_MACROS$BPT_BASE boo$gq_bpt_base.#define VMS_MACROS$PML4_BASE boo$gq_pml4_base.#define VMS_MACROS$PML5_BASE boo$gq_pml5_base#else#define __RUNCONST const/#define VMS_MACROS$PTE_LEVELS mmg$gq_pte_levels-#define VMS_MACROS$BPT_BASE mmg$gq_bpt_base.#define VMS_MACROS$PML4_BASE mmg$gq_pml4_base.#define VMS_MACROS$PML5_BASE mmg$gq_pml5_base#endif#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /*@ These are macros which facilitate the creation of other macros*/#define concat_sym(a,b) a ## b(#define concat_defs(a,b) concat_sym(a,b)+#define bld_sym1(x,line) concat_sym(x,line)'#define bld_sym(x) bld_sym1(x,__LINE__)/*F Here are some macros which need no explanation (except for, perhaps,8 why we're bothering to define them in the first place)*/%#define mfpr_asten __PAL_MFPR_ASTEN()%#define mfpr_astsr __PAL_MFPR_ASTSR()!#define mfpr_esp __PAL_MFPR_ESP()!#define mfpr_fen __PAL_MFPR_FEN()!#define mfpr_ipl __PAL_MFPR_IPL()##define mfpr_mces __PAL_MFPR_MCES()##define mfpr_pcbb __PAL_MFPR_PCBB()##define mfpr_prbr __PAL_MFPR_PRBR()##define mfpr_sisr __PAL_MFPR_SISR()!#define mfpr_ssp __PAL_MFPR_SSP()9#define mfpr_tbchk(check_adr) __PAL_MFPR_TBCHK(check_adr)!#define mfpr_usp __PAL_MFPR_USP()%#define mfpr_whami __PAL_MFPR_WHAMI()/#define mtpr _asten(mask) __PAL_MTPR_ASTEN(mask)/#define mtpr_astsr(mask) __PAL_MTPR_ASTSR(mask)3#define mtpr_datfx(enable) __PAL_MTPR_DATFX(enable)/#define mtpr_esp(new_sp) __PAL_MTPR_ESP(new_sp)1#define mtpr_fen(new_fen) __PAL_MTPR_FEN(new_fen)7#define mtpr_ipir(ipir_mask) __PAL_MTPR_IPIR(ipir_mask)/#define mtpr_ipl(newipl) __PAL_MTPR_IPL(newipl)3#define mtpr_mces(mck_sum) __PAL_MTPR_MCES(mck_sum)5#define mtpr_prbr(new_prbr) __PAL_MTPR_PRBR(new_prbr)-#define mtpr_sirr(mask) __PAL_MTPR_SIRR(mask)/#define mtpr_ssp(new_sp) __PAL_MTPR_SSP(new_sp)##define mtpr_tbia __PAL_MTPR_TBIA()%#define mtpr_tbiap __PAL_MTPR_TBIAP()1#define mtpr_tbis(tb_adr) __PAL_MTPR_TBIS(tb_adr)3#define mtpr_tbisd(tb_adr) __PAL_MTPR_TBISD(tb_adr)3#define mtpr_tbisi(tb_adr) __PAL_MTPR_TBISI(tb_adr)/#define mtpr_usp(new_sp) __PAL_MTPR_USP(new_sp)/*= The following macros are modelled after macros available to: BLISS and MACRO but are basically just simple PAL calls.*/C#define dsbint(newipl,saved_ipl) saved_ipl = __PAL_MTPR_IPL(newipl)-#define enbint(newipl) __PAL_MTPR_IPL(newipl)-#define setipl(newipl) __PAL_MTPR_IPL(newipl))#define softint(ipl) __PAL_MTPR_SIRR(ipl)A#ifdef __ia64 /* Verified for x86 port - Clair Grant; X-53 */-#define find_cpu_data __getReg(KR$C_CPUDB_VA)*#define get_slot_va __getReg(KR$C_SLOT_VA)#else'#define find_cpu_data __PAL_MFPR_PRBR()#endif/*6 The following MFPR/MTPR calls have no IA64 builtins.*/<#ifdef __ALPHA /* Verified for x86 por t - Clair Grant */%#define mfpr_scbb __PAL_MFPR_SCBB()6#define mtpr_scbb(base_adr) __PAL_MTPR_SCBB(base_adr)%#define mfpr_ptbr __PAL_MFPR_PTBR()%#define mfpr_vptb __PAL_MFPR_VPTB()6#define mtpr_vptb(new_vptb) __PAL_MTPR_VPTB(new_vptb)#endif/*O What follows is a bug_check macro for system C programmers which can be usedM to generate a bugcheck. Included are some #define's of constants which canI be used with the macro invocation. An example of its use is (note, all  parameters are in uppercase):% bug_check (INCONSTATE, FATAL, COLD);*/#define BUGCHK_QUOTE(s) #s%#define BUGCHK_STR(s) BUGCHK_QUOTE(s)#define BUGCHK_FATAL 1#define BUGCHK_NONFATAL 0#define BUGCHK_POWEROFF 2#define BUGCHK_COLD 1#define BUGCHK_WARM 0<#ifdef __ALPHA /* Verified for x86 port - Clair Grant */2#define bug_check(code, severity, reboot) \ { \( extern const int BUG$_##code; \, int bug_code = (int) &BUG$_##code; \F bug_code |= (BUGCHK_##severity) ? ((BUGCHK_##reboot) ? 5 : 4) : 0; \D asm ( "call_pal " BUGCHK_STR(EVX$PAL_BUGCHK) ";", bug_code ); \ }#endif;#ifdef __ia64 /* Verified for x86 port - Clair Grant */2#define bug_check(code, severity, reboot) \ { \( extern const int BUG$_##code; \, int bug_code = (int) &BUG$_##code; \F bug_code |= (BUGCHK_##severity) ? ((BUGCHK_##reboot) ? 5 : 4) : 0; \" __PAL_BUGCHK(bug_code); \ }#endif /* __ia64 */@#ifdef __x86_64 /* Verified for x86 port - Paul A. Jacobi */2#define bug_check(code, severity, reboot) \ { \( extern const int BUG$_##code; \, int bug_code = (int) &BUG$_##code; \F bug_code |= (BUGCHK_##severity) ? ((BUGCHK_##reboot) ? 5 : 4) : 0; \" __PAL_BUGCHK(bug_code); \ }#endif /* __x86_64 */;#ifdef __x86_64 /* Verified for x86 port--Drew Mason */K/* The following code is only available to modules that compile with the */D/* pointer_size qualifier. Short, long, 32, or 64 are all okay. */#ifdef __INITIAL_POINTER_SIZE#if __INITIAL_POINTER_SIZE/*J * The following macros and routines are temporarily defined for x86, but I * return null results. They will be going away in the fullness of time,? * but are left defined to keep the build noise to a dull roar. * l1pte_va * l2pte_va * pte_va * va_pte_to_va * svapte_to_va_pte * va_pte_to_svapte * make_va_s0 * extract_va_s0 * extract_pte_offset * */T/* Call it bpte_va so it doesn't get confused with pte_va used on Alpha and IA64. */#pragma inline ($$$bpte_va)2static PTE_PQ $$$bpte_va (int64 addr, uint32 mode){3 extern PTE_PQ __RUNCONST VMS_MACROS$BPT_BASE [4];#ifndef __SYSBOOT 4 extern PTE_PQ __RUNCONST VMS_MACROS$PML4_BASE [4];4 extern PTE_PQ __RUNCONST VMS_MACROS$PML5_BASE [4];#endif; extern __RUNCONST unsigned __int64 VMS_MACROS$PTE_LEVELS; __int64 mask; __int64 offset; __int64 va_pte;#if defined(TEST$MMG)$ va_pte = test$mmg_bpte_va( addr );/ if (va_pte != 0) return ((PTE_PQ) va_pte); #endif P mask = MMG$$C_PML4_MASK | MMG$$C_PDPT_MASK | MMG$$C_PD_MASK | MMG$$C_BPT_MASK;; if (VMS_MACROS$PTE_LEVELS == 5) mask |= MMG$$C_PML5_MASK;. offset = (addr & mask) >> MMG$$C_BPT_OFFPOS;#ifndef __SYSBOOT 0 offset &= ~0xF; /* Insure PTE for 8K page */#endif8 va_pte = (uint64) VMS_MACROS$BPT_BASE [mode] + offset;#ifndef __SYSBOOT W /* If va_pte is the self map  PTE in the top level page table, fix up based on mode */# if (VMS_MACROS$PTE_LEVELS == 4) {v if ((va_pte & ~0x10ull) == (__int64) VMS_MACROS$PML4_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2))) , va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; } else {v if ((va_pte & ~0x10ull) == (__int64) VMS_MACROS$PML5_BASE[mode]+(PTE$C_BYTES_PER_PTE*(MMG$$C_PTES_PER_PAGE/2))) , va_pte += (mode % 2) * PTE$C_BYTES_PER_PTE; }#endif return ((PTE_PQ) va_pte);} /* end $$$bpte_va */G#define bpte_va(addr,mode) $$$bpte_va ((int64) (addr), (uint32) (mode))<static PTE_PQ $$$dummy1 (uint64 addr) { return (PTE_PQ) 0; }2#define l1pte_va(addr) $$$dummy1 ((uint64) (addr))2#define l2pte_va(addr) $$$dummy1 ((uint64) (addr))0#define pte_va(addr) $$$dummy1 ((uint64) (addr)))#define svapte_to_va_pte (PTE * svapte) \#define $$$SVAPTE_TO_VA 1#if defined($$$SVAPTE_TO_VA)> #error svapte_to_va_pte is only supported on Alpha nd IA64#endifCstatic PTE * va_pte_to_svapte (PTE_PQ va_pte) { return (PTE *) 0; })#define va2pa_64( va ) mmg$va2pa_64( va ))#endif /* if __INITIAL_POINTER_SIZE */*#endif /* ifdef __INITIAL_POINTER_SIZE */#define make_va_s0(vpn) (0)#define extract_va_s0(vpn) (0)"#define extract_pte_offset(va) (0)>#else /* ifdef __x86_64 Verified for x86 port--Drew Mason */K/* The following code is only available to modules that compile with the */D/* pointer_size qualifier. Short, long, 32, or 64 are all okay. */#ifdef __INITIAL_POINTER_SIZE#if __INITIAL_POINTER_SIZE/*E Macro to return the VA of the L1PTE that maps the virtual address passed in.2 L1PTE_VA = MMG$GQ_L1_BASE[VA] + 8*VA*/#pragma inline ($$$l1pte_va)'static PTE_PQ $$$l1pte_va (uint64 addr){; extern PTE_PQ __RUNCONST mmg$gq_l1_base[VA$C_VRNX_COUNT]; int vrnx; unsigned __int64 va_pte;#ifdef __NEW_STARLET VA v; v.va$q_quad = addr;#else va v; v.va$q_quad[0] = addr; v.va$q_quad[1] = addr>>32;#endif vrnx = v.va$v_vrnx;* va_pte = (uint64) mmg$gq_l1_base[vrnx] +_ ((addr & ~mmg$gq_non_va_mask) >> 3*mmg$gq_level_width) & (uint64) ~(PTE$C_BYTES_PER_PTE-1); return ((PTE_PQ) va_pte);}2#define l1pte_va(addr) $$$l1pte_va((uint64)(addr))/*E Macro to return the VA of the L2PTE that maps the virtual address passed in.4 L2PTE_VA = MMG$GQ_L2_BASE[VA] + 8*VA*/#pragma inline ($$$l2pte_va)'static PTE_PQ $$$l2pte_va (uint64 addr){; extern PTE_PQ __RUNCONST mmg$gq_l2_base[VA$C_VRNX_COUNT];. extern __RUNCONST uint64 mmg$gq_non_va_mask;. extern __RUNCONST uint64 mmg$gq_level_width; int vrnx; unsigned __int64 va_pte;#ifdef __NEW_STARLET VA v; v.va$q_quad = addr;#else va v; v.va$q_quad[0] = addr; v.va$q_quad[1] = addr>>32;#endif vrnx = v.va$v_vrnx;c va_pte = (uint64) mmg$gq_l2_base[vrnx] + ((addr & ~mmg$gq_non_va_mask) >> 2*mmg$gq_level_width) &$ (uint64) ~(PTE$C_BYTES_PER_PTE-1); return ((PTE_PQ)va_pte);}2#define l2pte_va(addr) $$$l2pte_va((uint64)(addr))/*C Macro to return the VA of the PTE that maps the virtual address passed in.2 PTE_VA = MMG$GQ_PT_BASE[VA] + 8*VA*/#pragma inline ($$$pte_va)%static PTE_PQ $$$pte_va (uint64 addr){; extern PTE_PQ __RUNCONST mmg$gq_pt_base[VA$C_VRNX_COUNT];. extern __RUNCONST uint64 mmg$gq_non_pt_mask;. extern __RUNCONST uint64 mmg$gq_level_width; int vrnx; unsigned __int64 va_pte;#ifdef __NEW_STARLET VA v; v.va$q_quad = addr;#else va v; v.va$q_quad[0] = addr; v.va$q_quad[1] = addr>>32;#endif vrnx = v.va$v_vrnx;` va_pte = (uint64) mmg$gq_pt_base[vrnx] + ((addr & ~mmg$gq_non_pt_mask) >> mmg$gq_level_width); return ((PTE_PQ)va_pte);}.#define pte_va(addr) $$$pte_va((uint64)(addr))/*J bpte_va has a mode parameterm but the parameter is ignored on Alpha/IA64.*/4#define bpte_va(addr,mode) $$$pte_va((uint64)(addr)))#endif /* if  __INITIAL_POINTER_SIZE */*#endif /* ifdef __INITIAL_POINTER_SIZE */#endif#ifdef __INITIAL_POINTER_SIZE#if __INITIAL_POINTER_SIZE/*< Routine to return the VA mapped by the VA_PTE passed in.C VA = ((VA_PTE - MMG$GQ_PT_BASE[VA])/PTE_SIZE) * PAGE_SIZE*/ #pragma inline ($$$va_pte_to_va).static VOID_PQ $$$va_pte_to_va (PTE_PQ va_pte){<#ifdef __x86_64 /* Verified for x86 port--Greg Jordan */A extern PTE_PQ __RUNCONST mmg$gq_bpt_vrnx_base[VA$C_VRNX_COUNT];#else; extern PTE_PQ __RUNCONST mmg$gq_pt_base[VA$C_VRNX_COUNT];#endif* extern __RUNCONST uint64 mmg$gq_va_bits;. extern __RUNCONST uint64 mmg$gq_level_width; uint64 temp1; int vrnx;#ifdef __NEW_STARLET VA v; VA temp2; v.va$q_quad = (uint64)va_pte;#else va v; va temp2; temp1 = (uint64)va_pte;' v.va$q_quad[0] = (unsigned int)temp1;/ v.va$q_quad[1] = (unsigned int)(temp1 >> 32);#endif vrnx = v.va$v_vrnx;<#ifdef __x86_64 /* Verified fo r x86 port--Greg Jordan */\ temp1 = ((uint64)va_pte - (uint64) mmg$gq_bpt_vrnx_base[vrnx]) << MMG$$C_PTE_SEGMENT_SIZE;#elseQ temp1 = ((uint64)va_pte - (uint64) mmg$gq_pt_base[vrnx]) << mmg$gq_level_width;#endifG/* Since the above statement creates an address that does not have theI bits above the L1 MSB set according to the setting of the L1 MSB, the6 following code handles this contingency. */[#if defined(__alpha) || defined(__x86_64) /* Verified for x86 port - Clair Grant */3 if ((int64) (temp1 << (64 - mmg$gq_va_bits)) < 0)3 temp1 = temp1 | ((int64) -1 << mmg$gq_va_bits);#endif//* IA64 we now have to insert the vrnx bits */8#ifdef __ia64 /* Verified for x86 port--Drew Mason */ if (vrnx&1)3 temp1 = temp1 | ((int64) -1 << mmg$gq_va_bits);# ifdef __NEW_STARLET temp2.va$q_quad = temp1; temp2.va$v_vrnx = vrnx; temp1 = temp2.va$q_quad;# else temp2.va$q_quad[0] = temp1;! temp2.va$q_quad[1] = temp1>>32; temp2.va$v_vrnx = vrnx; temp1 = temp2.va$q_quad[0];* temp1 |= (uint64)temp2.va$q_quad[1]<<32;# endif#endif /* __ia64 */ return ((VOID_PQ) temp1);}>#define va_pte_to_va(va_pte) $$$va_pte_to_va((PTE_PQ)(va_pte)))#endif /* if __INITIAL_POINTER_SIZE */*#endif /* ifdef __INITIAL_POINTER_SIZE */a#if defined(__alpha) || defined(__ia64) /* Verified for x86 port - Clair Grant */#ifdef __INITIAL_POINTER_SIZE#if __INITIAL_POINTER_SIZE0/* Routine to convert a SVAPTE to a VA_PTE. */!#pragma inline (svapte_to_va_pte),static PTE_PQ svapte_to_va_pte (PTE *svapte){) extern PTE * __RUNCONST mmg$gl_sptbase;7 extern PTE_PQ __RUNCONST mmg$gq_s0s1base_pte_address;l return ((PTE_PQ) ((uint64) mmg$gq_s0s1base_pte_address + (uint64) ((int) svapte - (int) mmg$gl_sptbase)));}0/* Routine to convert a VA_PTE to a SVAPTE. */!#pragma inline (va_pte_to_svapte)-static PTE * va_pte_to_svapte (PTE_PQ va_pte){) extern PTE * __RUNCONS T mmg$gl_sptbase;7 extern PTE_PQ __RUNCONST mmg$gq_s0s1base_pte_address;k return ((PTE *) ((int) mmg$gl_sptbase + (int) ((uint64) va_pte - (uint64) mmg$gq_s0s1base_pte_address)));})#endif /* if __INITIAL_POINTER_SIZE */*#endif /* ifdef __INITIAL_POINTER_SIZE *//*O These macros, MAKE_VA_xx, are similar to $MAKE_VA for MACRO and BLISS but notO as sophisticated. They will convert a virtual page number (VPN) to an addressL (the first byte of the page) for the specified add ress space. These macrosL ALWAYS assume page-size-independent code and that the LIB symbols VA$M_xxx8 are defined and you're linking against SYS$BASE_IMAGE.*/A#define make_va_s0(vpn) ((vpn << mmg$gl_vpn_to_va) | VA$M_SYSTEM)/*M These macros, EXTRACT_VA_xx, are similar to $EXTRACT_VA for MACRO and BLISSL but not as sophisticated. They will convert a virtual address to a virtualA page number (VPN) for the specified address space. These macrosL ALWAYS assume page-size-independent co de and that the LIB symbols VA$M_xxx8 are defined and you're linking against SYS$BASE_IMAGE.*/F#define extract_va_s0(va) ((va & (~ VA$M_SYSTEM)) >> mmg$gl_vpn_to_va)/*I These macros, EXTRACT_PTE_OFFSET_xx, are similar to $EXTRACT_PTE_OFFSETK for MACRO and BLISS but not as sophisticated. They will convert a virtualG address to a PTE offset for the specified address space. These macrosL ALWAYS assume page-size-independent code and that the LIB symbols VA$M_xxx8 are defined and you're linking against SYS$BASE_IMAGE.*/##define extract_pte_offset_s0(va) \5 ((va & (~ VA$M_SYSTEM)) >> mmg$gl_pte_offset_to_va) #endif /* ifdef __x86_64 else *//*J These macros and static routines will perform various operations on PTEs and PFNs. 8 Extracting a PFN from a PTE $extract_pfn( PTE pte )@ Inserting a PFN into a PTE $insert_pfn( PTE pte, PFN pfn )6 Converting a PFN to a PA $pfn_to_pa( uint64 pfn )5 Getting the PA for a PTE $extract_pa( PTE pte )6  Converting a PA to a PFN $pa_to_pfn ( uint64 pa )) For X86, _2mb and _1g variants exist.*/@#define $pa_to_pfn( pa ) ((pa) >> MMG$$C_PA_TO_PFN_SHIFT)Y#if defined(__alpha) || defined(__ia64) /* Verified for x86 port - Greg Jordan */.#define $extract_pfn( pte ) (pte).pte$v_pfn:#define $insert_pfn( pte, pfn ) (pte).pte$v_pfn = (pfn)@#define $pfn_to_pa( pfn ) ((pfn) << MMG$$C_PA_TO_PFN_SHIFT)#pragma inline ($extract_pa)#static uint64 $extract_pa (PTE pte){ uint64 pfn; pfn = $extract_pfn( pte ); return $pfn_to_pa( pfn );}#elif defined(__x86_64)2#define $extract_pfn( pte ) (pte).pte$v_pfn_4k:#define $insert_pfn( pte, pfn ) (pte).pte$v_pfn_4k = (pfn)3#define $extract_pfn_2mb( pte ) (pte).pte$v_pfn_2mb2#define $extract_pfn_1g( pte ) (pte).pte$v_pfn_1gA#define $pfn_to_pa( pfn ) ((pfn) << MMG$$C_PFN_TO_PA_SHIFT)E#define $pfn_to_pa_2mb( pfn ) ((pfn) << MMG$$C_PFN_2MB_TO_PA_SHIFT)E#define $pfn_to_pa_1g( pfn ) ((pfn) << MMG$$C_PFN_1GB_TO_PA_SHIFT)#pragma inline ($extract_pa)#static uint64 $extract_pa (PTE pte){ uint64 pfn; pfn = $extract_pfn( pte ); return $pfn_to_pa( pfn );} #pragma inline ($extract_pa_2mb)'static uint64 $extract_pa_2mb (PTE pte){ uint64 pfn;! pfn = $extract_pfn_2mb( pte ); return $pfn_to_pa_2mb( pfn );}#pragma inline ($extract_pa_1g)&static uint64 $extract_pa_1g (PTE pte){ uint64 pfn; pfn = $extract_pfn_1g( pte ); return $pfn_to_pa_1g( pfn );}#else/ #error Need architecture specific work here#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifY/* Guard against anyone using this macro with their module compiled with long pointers */\typedef struct _spl ** SPL_PPL ; /* Short pointer to a short pointer to an SPL structure */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif/*R Define some constants used by the various spinlock acquisition and release macros*/<#define NOSAVE_IPL ((int *) 0) /* don't save original IPL */7#define NOLOWER_IPL -1 /* don't lower IPL on unlock */4#define NORAISE_IPL 0 /* don't ra ise IPL on lock *//#define RAISE_IPL 1 /* do raise IPL on lock */=#define SMP_RELEASE 0 /* unconditionally release spinlock */;#define SMP_RESTORE 1 /* conditionally release spinlock *//*G These macros are similar to the LOCK macro (in MACRO-32) to acquire aC spinlock and/or raise IPL. They do NOT take out a mutex, however. This is a separate function.> lockname = Name of the spinlock in uppercase (IOLOCK8, etc.) change_ipl = 0 => No, 1 => YesM saved_ipl = Address of variable (int) to receive the previous IPL (or zero)P status = address of variable (int) to receive the status of the lock operationJ For example, to take out IOLOCK8, change IPL, and save the previous IPL: int old_ipl; sys_lock(IOLOCK8,1,&old_ipl);2 and if you didn't want to save the previous IPL: sys_lock(IOLOCK8,1,0);M The _NOSPIN variants return a status of either SS$_NORMAL or SS$_LOCKINUSE,. depending if the spinlock was locked or not.*/1#define sys_lock(lockname,change_ipl,saved_ipl) \{ \ extern SMP smp$gl_flags; \# extern SPL_PPL smp$ar_spnlkvec; \\ if (saved_ipl != 0) \# *(int *)saved_ipl = mfpr_ipl; \\ if (change_ipl == 0) \E smp_std$acqnoipl(smp$ar_spnlkvec[concat_sym(SPL$C_,lockname)]); \ else \% if (smp$gl_flags.smp$v_enabled) \5 smp_std$acquire(concat_sym(SPL$C_,lockname)); \ else \- mtpr_ipl(concat_sym(IPL$_,lockname)); \}5#define sys_lock_shr(lockname,change_ipl,saved_ipl) \{ \ extern SMP smp$gl_flags; \# extern SPL_PPL smp$ar_spnlkvec; \\ if (saved_ipl != 0) \# *(int *)saved_ipl = mfpr_ipl; \\ if (change_ipl == 0) \I smp_std$acqnoipl_shr(smp$ar_spnlkvec[concat_sym(SPL$C_,lockname)]); \ else \% if (smp$gl_flags.smp$v_enabled) \9 smp_std$acquire_shr(concat_sym(SPL$C_,lockname)); \ else \- mtpr_ipl(concat_sym(IPL$_,lockname)); \}?#define sys_lock_nospin(lockname,change_ipl,saved_ipl,status) \{ \ extern SMP smp$gl_flags; \# extern SPL_PPL smp$ar_spnlkvec; \\ if (saved_ipl != 0) \# *(int *)saved_ipl = mfpr_ipl; \\ if (change_ipl == 0) \] *(int *)status = smp_std$acqnoipl_nospin(smp$ar_spnlkvec[concat_sym(SPL$C_,lockname)]); \ else \% if (smp$gl_flags.smp$v_enabled) \M *(int *)status = smp_std$acquire_nospin(concat_sym(SPL$C_,lockname)); \ else \ { \- mtpr_ipl(concat_sym(IPL$_,lockname)); \$ *(int *)status = SS$_NORMAL; \ } \}C#define sys_lock_shr_nospin(lockname,change_ipl,saved_ipl,status) \{ \ extern SMP smp$gl_flags; \# extern SPL_PPL smp$ar_spnlkvec; \\ if (saved_ipl != 0) \# *(int *)saved_ipl = mfpr_ipl; \\ if (change_ipl == 0) \a *(int *)status = smp_std$acqnoipl_shr_nospin(smp$ar_spnlkvec[concat_sym(SPL$C_,lockname)]); \ else \% if (smp$gl_flags.smp$v_enabled) \Q *(int *)status = smp_std$acquire_shr_nospin(concat_sym(SPL$C_,lockname)); \ else \ { \- mtpr_ipl(concat_sym(IPL$_,lockname)); \$ *(int *)status = SS$_NORMAL; \ } \}'#define sys_lock_cvt_to_shr(lockname) \{ \ extern SMP smp$gl_flags; \# extern SPL_PPL smp$ar_spnlkvec; \\H smp_std$cvt_to_shared(smp$ar_spnlkvec[concat_sym(SPL$C_,lockname)]); \}-#define sys_lock_cvt_to_ex(lockname,status) \{ \ extern SMP smp$gl_flags; \# extern SPL_PPL smp$ar_spnlkvec; \\U *(int *)status = smp_std$cvt_to_ex(smp$ar_spnlkvec[concat_sym(SPL$C_,lockname)]); \}/*I These macros are similar to the UNLOCK macro (in MACRO-32) to release aB spinlock and/or lower IPL. They do NOT release a mutex, however. This is a separate function.> lockname = Name of the spinlock in uppercase (IOLOCK8, etc.)K new_ipl = if >= 0, then this is to be the new IPL (< 0 implies no change)E restore = if != 0, then use SMP restore function, else use release.*/.#define sys_unlock(lockname,new_ipl,restore) \{ \ extern SMP smp$gl_flags; \\# if (smp$gl_flags.smp$v_enabled) \ if (restore != 0) \5 smp_std$restore(concat_sym(SPL$C_,lockname)); \ else \5 smp_std$release(concat_sym(SPL$C_,lockname)); \ if ((int)(new_ipl) >= 0) \ mtpr_ipl(new_ipl); \}2#define sys_unlock_shr(lockname,new_ipl,restore) \{ \ extern SMP smp$gl_flags; \\# if (smp$gl_flags.smp$v_enabled) \ { \ if (restore != 0) \9 smp_std$restore_shr(concat_sym(SPL$C_,lockname)); \ else \9 smp_std$release_shr(concat_sym(SPL$C_,lockname)); \ } \ if ((int)(new_ipl) >= 0) \ mtpr_ipl(new_ipl); \}P/******************************************************************************* *D * The LOCK_CPU_MUTEX and UNLOCK_CPU_MUTEX macros are similar to theA * Macro32 LOCK and UNLOCK macros for acquiring and releasing the? * CPU mutex, the only mutex ever acquired or released by those * macros. *? * The LOCK_CPU_MUTEX and UNLOCK_CPU_MUTEX macros do not take aC * mutex parameter and instead deal exclusively with the CPU mutex.D * The caller can only specify whether shared or exclusive access is * required. *C * Acquiring the CPU mutex in shared mode will restore the IPL, butC * if the CPU mutex is acquired in exclusive mode, then IPL remainsF * at IPL$_POWER and it is the responsibility of the caller to restore) * the IPL after releasing the CPU mutex. * * Shared Usage: * lock_cpu_mutex (1); * ... * ... * unlock_cpu_mutex (1); * * Exclusive Usage:! * saved_ipl = __PAL_MFPR_IPL(); * lock_cpu_mutex (0); * ... * ... * unlock_cpu_mutex (0); * setipl (saved_ipl); * * */<#ifdef __alpha /* Verified for x86 port - Clair Grant */?#define CMPXCHG8(ptr,old,new) __CMP_STORE_QUAD(ptr,old,new,ptr)#else:#define CMPXCHG8(ptr,old,new) __CMP_SWAP_QUAD(ptr,old,new)#endif%#define lock_cpu_mutex(share) \ { \int status; \int saved_ipl; \int drop_ipl; \int retry;  \int64 delta_time; \int64 end_time; \CPU *cpu; \MUTEX old_mutex; \MUTEX new_mutex; \&extern int sgn$gl_smp_spinwait; \2extern SYS_TIME_CONTROL exe$gl_time_control; \4extern volatile struct _mutex smp$gq_cpu_mutex; \ \ \ /* */ \7 /* Disable interrupts, initialize drop IPL and */ \) /* retrieve CPU database address */ \ /* */ \) saved_ipl = setipl ( IPL$_POWER ); \& if ( saved_ipl >= IPL$_SCHED ) \ drop_ipl = saved_ipl; \ else \ drop_ipl = IPL$_SCHED; \$ cpu = (CPU *) find_cpu_data; \ retry = 0; \ \ /* */ \" /* Compute endtime token */ \ /* */ \/ int64 smp_spinwait = sgn$gl_smp_spinwait; \* delta_time = smp_spinwait << 13ull; \5 exe$timedwait_setup ( &delta_time, &end_time ); \ \ /* */ \8 /* Loop to increment mutex owner count atomically */ \ /* */ \ do \ { \ /* */ \7 /* Issue memory barrier and read current mutex */ \ /* */ \ __MB(); \D old_mutex.mutex$q_quadword = smp$gq_cpu_mutex.mutex$q_quadword; \> new_mutex.mutex$q_quadword = old_mutex.mutex$q_quadword; \ \ /* */ \+ /* check if mutex is free or not */ \ /* */ \+ if ( old_mutex.mutex$v_interlock ) \ { \ /* */ \/ /* Give the IPINT handler a chance */ \ /* */ \ setipl ( drop_ipl ); \" setipl ( IPL$_POWER ); \ \ /* */ \- /* Check for bugcheck requests. */ \ /* */ \D if ( cpu->cpu$v_bugchk ) bug_check ( CPUEXIT, FATAL, COLD ); \ \ /* */ \@ /* If SMP timeouts are not disabled check for timeout, */ \* /* then try another wait loop */ \ /* */ \5 if ( !exe$gl_time_control.exe$v_nospinwait ) \ { \9 status = exe$timedwait_complete ( &end_time ); \/ if ( !$VMS_STATUS_SUCCESS(status) ) \ { \ smp$timeout(); \5 exe$timedwait_setup ( &delta_time, &end_time ); \ } \ } \ } \ else \ { \ /* */ \2 /* Mutex is free (interlock bit clear) */ \? /* For shared access, only increment the owner count. */ \> /* For exclusive access, only set the interlock bit */ \1 /* after making sure it is not owned. */ \ /* */ \ if ( share ) \ { \( new_mutex.mutex$l_owncnt++; \1 retry = CMPXCHG8 ( &smp$gq_cpu_mutex, \* old_mutex.mutex$q_quadword, \+ new_mutex.mutex$q_quadword ); \ } \ else \ { \5 if ( (int)new_mutex.mutex$l_owncnt == -1 ) \ { \. new_mutex.mutex$v_interlock = 1; \3 retry = CMPXCHG8 ( &smp$gq_cpu_mutex, \% old_mutex.mutex$q_quadword, \& new_mutex.mutex$q_quadword ); \ } \ } \ } \ \ } while ( !retry ); \ \ /* */ \7 /* record this mutex held-count and restore IPL */ \ /* shared access */ \ /* */ \ __MB(); \ cpu->cpu$l_cpumtx++; \* if ( share ) setipl ( saved_ipl ); \}'#define unlock_cpu_mutex(share) \ { \int status; \int saved_ipl; \int drop_ipl; \int retry; \int64 delta_time; \int64 end_time; \CPU *cpu; \MUTEX old_mutex; \MUTEX new_mutex; \&extern int sgn$gl_smp_spinwait; \2extern SYS_TIME_CONTROL exe$gl_time_control; \4extern volatile struct _mutex smp$gq_cpu_mutex; \ \ \ if ( share ) \ { \ /*  */ \8 /* Disable interrupts, initialize drop IPL and */ \+ /* retrieve CPU database address */ \ /* */ \+ saved_ipl = setipl ( IPL$_POWER ); \' if ( saved_ipl >= IPL$_SCHED ) \! drop_ipl = saved_ipl; \ else \" drop_ipl = IPL$_SCHED; \& cpu = (CPU *) find_cpu_data; \ retry = 0; \ \ /* */ \$ /* Compute endtime token */ \ /* */ \1 int64 smp_spinwait = sgn$gl_smp_spinwait; \, delta_time = smp_spinwait << 13ull; \6 exe$timedwait_setup ( &delta_time, &end_time ); \ \ /* */ \> /* Loop to decrement CPU mutex owner count atomically */ \ /* */ \ do \ { \ /* */ \= /* Issue memory barrier and read current CPU mutex */ \ /* */ \ __MB(); \F old_mutex.mutex$q_quadword = smp$gq_cpu_mutex.mutex$q_quadword; \@ new_mutex.mutex$q_quadword = old_mutex.mutex$q_quadword; \ \ /* */ \0 /* check if CPU mutex is free or not */ \ /* */ \- if ( old_mutex.mutex$v_interlock ) \ { \ /* */ \0 /* Give the IPINT handler a chance */ \ /* */ \" setipl ( drop_ipl ); \$ setipl ( IPL$_POWER ); \ \ /* */ \/ /* Check for bugcheck requests. */ \ /* */ \F if ( cpu->cpu $v_bugchk ) bug_check ( CPUEXIT, FATAL, COLD ); \ \ /* */ \B /* If SMP timeouts are not disabled check for timeout, */ \, /* then try another wait loop */ \ /* */ \7 if ( !exe$gl_time_control.exe$v_nospinwait ) \ { \; status = exe$timedwait_complete ( &end_time ); \1 if ( !$VMS_STATUS_SUCCESS(status) ) \ { \ smp$timeout(); \6 exe$timedwait_setup ( &delta_time, &end_time ); \ } \ } \ } \ else \ { \ /* */ \( /* Decrement owner count */ \ /* */ \( new_mutex.mutex$l_owncnt--; \1 retry = CMPXCHG8 ( &smp$gq_cpu_mutex, \* old_mutex.mutex$q_quadword, \+ new_mutex.mutex$q_quadword ); \ } \ \ } while ( !retry ); \ \ /* */ \> /* rundown this CPU's mutex held-count and restore IPL */ \ /* */ \ __MB(); \ cpu->cpu$l_cpumtx--; \ setipl ( saved_ipl ); \ } \ else \ { \ /* */ \> /* Interrupts are already disabled, so just retrieve */ \# /* CPU database address */ \ /* */ \& cpu = (CPU *) find_cpu_data; \ \ /* */ \2 /* decrement this CPU's mutex held-count */ \ /* */ \ cpu->cpu$l_cpumtx--; \ \ /* */ \1 /* Clear the interlocked bit atomically */ \ /* */ \5 __ATOMIC_DECREMENT_QUAD ( &smp$gq_cpu_mutex ); \ \ /* */ \? /* Synchronize with any TB invalidates that might have */ \? /* occured in the active set prior to this CPU joining */ \ /* the active set. */ \ /* */ \ mtpr_tbia; \ } \}Q/*******************************************************************************//*E This vms_assert macro is intended to provide C "assert" behavior inJ a twisted, perverted, VMS fashion...That is, if the specified expressionJ turns out to be false (evaluated VMS-style) at run-time, fatal bugcheck.H Otherwise, do nothing. The macro does nothing in a non-debug mode too.*/ #ifdef NDEBUG#define vms_assert(ignore)#else#define vms_assert(expr) \9 { if (!((expr) & 1)) bug_check(ASSERTFAIL,FATAL,COLD) }#endif/*H This macro improves readability of VMS code which checks status returnI values for success/failure based on the low bit of the status value. InI C, the test for this is slightly uglier than in MACRO and BLISS and canJ be hidden inside a macro which makes it clear what the code is trying toG do. This macro takes a single argument, the return status or functionH return value and returns true (1) or false (0) based on the low bit of this value.*/1#define good_status(status) (((status) & 1) == 1)0#define bad_status(status) (((status) & 1) == 0)?/* The following definitions of constants and system data cells> are needed by the TB invalidate routines which follow them.*/#define NO_PCB ((PCB *) 0)#define THIS_CPU_ONLY 1#define ALL_CPUS 2#define ASSUME_PRIVATE 3#define ASSUME_SHARED 4extern SMP smp$gl_flags;/*6 TB Invalidate All Entries (System and Process) TBI_ALL ENVIRONE ENVIRON = "THIS_CPU_ONLY" indicates that this invocation of TBIA is< to be executed strictly within the context of the localA CPU only. Thus, no attempt is made whatsoever to extend8 the TBIA request to any CPU or other 'processor' that! might exist within the system.B = "ALL_CPUS" forces the TBIA to be extended to all components of( the system that may have cached PTEs.*/#define tbi_all(environ) { \\! if (environ == THIS_CPU_ONLY) \ mtpr_tbia; \ else \ mmg$tbi_all(); \}/*  TB Invalidate Data Single 64$ TBI_DATA_64 ADDR, ENVIRON, PCBADDR1 ADDR = 64-bit Virtual Address to be invalidated.F ENVIRON = "THIS_CPU_ONLY" indicates that this invocation of TBISD is< to be executed strictly within the context of the localA CPU only. Thus, no attempt is made whatsoever to extend9 the TBISD request to any CPU or other 'processor' that! might exist within the system.5 = "ASSUME_PRIVATE" indicates that this is a threads5 environment and that the address should be treated3 as a private address and not checked. Therefore,6 in an SMP environment, we need to do the invalidate7 to other CPUs which are running a kernel thread from7 this process. This argument is used for system space6 addresses which should be treated as private to the5 process (e.g. for L2PTE's which are also mapped in "page table space").B = "ASSUME_SHARED" indicates that this invocation of TBISD should9 be broadcast to all other CPUs in the system. ASSUME_1 SHARED is the exact opposite of THIS_CPU_ONLY.= = "ALL_CPUS" forces the TB invalidate to be extended to all6 components of the system that may have cached PTEs.@ PCBADDR = Address of current process control block. The NO_PCB; symbol can be used for this argument if the PCB address; is not required (for example, when using the qualifier,5 ENVIRON=THIS_CPU_ONLY or ENVIRON=ASSUMED_SHARED).*/-#define tbi_data_64(addr,environ,pcbaddr) { \\ switch (environ) \# { \$ case THIS_CPU_ONLY: \ mtpr_tbisd(addr); \ break; \& case ALL_CPUS: \3 if (smp$gl_flags.smp$v_enabled == 0) \/ mtpr_tbisd(addr); \ else \% if ($is_shared_va(addr)) \& mmg_std$tbi_data_64(addr); \' else \( { \, if (pcbaddr->pcb$l _multithread <= 1) \* mtpr_tbisd(addr); \, else \0 mmg_std$tbi_data_64_threads(addr); \ } \ break; \1 case ASSUME_PRIVATE: \6 if (smp$gl_flags.smp$v_enabled == 0) \3 mtpr_tbisd(addr); \ else \. if (pcbaddr->pcb$l_multithread <= 1) \- mtpr_tbisd(addr); \. else  \/ mmg_std$tbi_data_64_threads(addr); \0 break; \8 case ASSUME_SHARED: \3 if (smp$gl_flags.smp$v_enabled == 0) \/ mtpr_tbisd(addr); \/ else \( mmg_std$tbi_data_64(addr); \( break; \6 } \}/* TB Invalid ate Single) TBI_SINGLE ADDR, ENVIRON, PCBADDR* ADDR = Virtual Address to be invalidated.E ENVIRON = "THIS_CPU_ONLY" indicates that this invocation of TBIS is< to be executed strictly within the context of the localA CPU only. Thus, no attempt is made whatsoever to extend8 the TBIS request to any CPU or other 'processor' that! might exist within the system.5 = "ASSUME_PRIVATE" indicates that this is a threads5 environment and that the address should be tr eated3 as a private address and not checked. Therefore,6 in an SMP environment, we need to do the invalidate7 to other CPUs which are running a kernel thread from7 this process. This argument is used for system space6 addresses which should be treated as private to the5 process (e.g. for L2PTE's which are also mapped in "page table space").A = "ASSUME_SHARED" indicates that this invocation of TBIS should9 be broadcast to all other CPUs in the system. ASSUME_1 SHARED is the exact opposite of THIS_CPU_ONLY.= = "ALL_CPUS" forces the TB invalidate to be extended to all6 components of the system that may have cached PTEs.A PCBADDR = Address of current process control block. The NO_PCB; symbol can be used for this argument if the PCB address; is not required (for example, when using the qualifier, ENVIRON=THIS_CPU_ONLY).*/,#define tbi_single(addr,environ,pcbaddr) { \\ switch (environ) \# { \$  case THIS_CPU_ONLY: \ mtpr_tbis(addr); \ break; \& case ALL_CPUS: \3 if (smp$gl_flags.smp$v_enabled == 0) \) mtpr_tbis(addr); \ else \$ if ($is_shared_va(addr)) \% mmg$tbi_single(addr); \( else \) { \. if (pcbaddr->pcb$l_multithread <= 1) \+ mtpr_tbis(addr);  \, else \, mmg$tbi_single_threads(addr); \ } \ break; \/ case ASSUME_PRIVATE: \4 if (smp$gl_flags.smp$v_enabled == 0) \1 mtpr_tbis(addr); \ else \* if (pcbaddr->pcb$l_multithread <= 1) \' mtpr_tbis(addr); \* else \) mmg$tbi_single_threads(addr); \* break;  \2 case ASSUME_SHARED: \7 if (smp$gl_flags.smp$v_enabled == 0) \4 mtpr_tbis(addr); \5 else \/ mmg$tbi_single(addr); \0 break; \? } \}/*L * Convert bitmask to bit number. I.e., the xxx$V_yyy version of xxx$M_yyy.M * The name is uppercase to reflect the fact that the input is a compile-time! * constant, such as IRP$M_ERASE. *! * Input (mask) Output (position) * 0x0001 0 * 0x0002 1 * 0x0004 2 * ... * 0x4000 14 * etc. *5 * Currently limited to 32 bit wide single-bit masks. */#define MASK_TO_POSITION(m) \8 (m>>24 ? (m>>31?31:m>>30?30:m>>29?29:m>>28?28: \4 m>>27?27:m>>26?26:m>>25?25:24) : \9 m>>16 ? (m>>23?23:m>>22?22:m>>21?21:m>>20?20: \4  m>>19?19:m>>18?18:m>>17?17:16) : \8 m>>8 ? (m>>15?15:m>>14?14:m>>13?13:m>>12?12: \4 m>>11?11:m>>10?10:m>> 9? 9: 8) : \8 (m>> 7? 7:m>> 6? 6:m>> 5? 5:m>> 4? 4: \2 m>> 3? 3:m>> 2? 2:m>> 1? 1: 0) )/* $get_item_codeI This macro fetches the contents of the item code field from an item listJ entry. Note that the item code field is in the same place for 32-bit and 64-bit item list entries. ARGUMENTS:B item_list: Specifies the item list entry from which the item code is extracted. USAGE:( item_code = $get_item_code (item_list);*/'#define $get_item_code(item_list) \0 ( ((ILEA_64_PQ)item_list)->ilea_64$w_code )/* $GET_LENGTHF This macro fetches the contents of the length field from an item list entry. ARGUMENTS:= flag: A flag denoting the type of item list specified. Low: bit set denotes a 64-bit item list, while low bit clear denotes a 32-bit item list.> itemlist: Specifies the item list entry from which the length is extracted. USAGE:- item_length = $get_length (flag, item_list);*/)#define $get_length(flag,item_list) \d ( flag == 1 ? ((ILEA_64_PQ)item_list)->ilea_64$q_length : ((ILE2_PQ)item_list)->ile2$w_length )/* $GET_BUFADDRN This macro fetches the contents of the buffer address field from an item list entry. ARGUMENTS:= flag: A flag denoting the type of item list specified. Low: bit set denotes a 64-bit item list, while low bit clear denotes a 32-bit item list.? item_list: Specifies the item list entry from which the buffer address is extracted. USAGE:/ item_bufaddr = $get_bufaddr (flag, item_list);*/*#define $get_bufaddr(flag,item_list) \h ( flag == 1 ? ((ILEA_64_PQ)item_list)->ilea_64$pq_bufaddr : ((ILE2_PQ)item_list)->ile2$ps_bufaddr )/* $GET_RETLEN_ADDRK This macro fetches the contents of the return length address field from anN item list entry. The return length address field only exists for item_list_3$ and item_list_64_b item list types. ARGUMENTS:= flag: A flag denoting the type of item list specified. Low: bit set denotes a 64-bit item list, while low bit clear denotes a 32-bit item list.? item_list: Specifies the item list entry from which the return length address is extracted. USAGE:7 item_retlen_addr = $get_retlen_addr (flag, item_list);*/.#define $get_retlen_addr(flag,item_list) \p ( flag == 1 ? ((ILEB_64_PQ)item_list)->ileb_64$pq_retlen_addr : ((ILE3_PQ)item_list)->ile3$ps_retlen_addr )/* $GET_ILE_FIELDSI This macro fetches the contents of the item list entry fields and writes% them to the user-supplied registers. ARGUMENTS:= flag: A flag denoting the type of item list entry specified4 in the item list argument. Low bit set denotes a9 64-bit item list, while low bit clear denotes a 32-bit item list.B item_list: An item list entry from which to fetch the contents of the various fields.> item_code: Contents of the item code field are recorded here.9 length: Contents of the length field are recorded here.A bufaddr: Contents of the buffer address field are recorded here.= retlen_addr: Contents of the return length address field are recorded here. USAGE:L $get_ile_fields (flag, item_list, item_code, length, bufaddr, retlen_addr);*/W#define $get_ile_fields(flag, item_list, item_code, length, bufaddr, retlen_addr) \{ \ if (flag == 1 ) \ { \7 item_code = ((ILEB_64_PQ)item_list)->ileb_64$w_code; \6 length = ((ILEB_64_PQ)item_list)->ileb_64$q_length; \9 bufaddr = ((ILEB_64_PQ)item_list)->ileb_64$pq_bufaddr; \A retlen_addr = ((ILEB_64_PQ)item_list)->ileb_64$pq_retlen_addr; \ } \ else \ { \1 item_code = ((ILE3_PQ)item_list)->ile3$w_code; \0 length = ((ILE3_PQ)item_list)->ile3$w_length; \3 bufaddr = ((ILE3_PQ)item_list)->ile3$ps_bufaddr; \; retlen_addr = ((ILE3_PQ)item_list)->ile3$ps_retlen_addr; \ } \} /* TR_PRINT - Debug print * *C * This macro adds an informational message to the TR trace buffer.G * The ctrstr argument has similar syntax to a "printf" statement. * * Inputs: *C * ctrstr - The text and optional formatting directives to beD * saved in the trace ring buffer, only the following3 * directives are allowed, no width:3 * %s - zero- terminated string< * %a - ascii string (pointer & length)* * %d - decimal value1 * %X - hexadecimal longword1 * %L - hexadecimal quadwordF * p1-p5 - The corresponding values to be formatted. For the %sG * directive, this is the address of the zero-terminatedJ * string. For the %a directive, this requires 2 arguments,I * first the address of the string buff er, then the lengthJ * of the string (by value). For the other directives, this% * is passed by value. * * Usage Examples: * Macro32:< * tr_print ctrstr=,p1=r4C * tr_print ctrstr=,p1=r3,p2=r5 * C: * #include vms_macrosQ * tr_print (("this is a C test and needs double-parentheses, index %d", idx ));W * tr_print (("a hex number %X and a quadword %L", irp->irp$l_func, irp->irp$q_fr3 )); * Bliss:7 * tr_print ('this is a Bliss test, index %d', .idx );@ * tr_print ('a hex number %X and a quadword %L', .irp, .ucb ); */extern uint64 tr$gq_debug;$#define tr_print(_printf_args) \ if ( tr$gq_debug & 1 ) \ { \4 int *tr_print_rtn = (int *) (tr$gq_debug & ~1); \1 ((void (*)()) *tr_print_rtn) _printf_args ; \ }+/* EXC_PRINT - Exception trace print * *D * This macro adds an informational message to the EXC trace buffer.G *  The ctrstr argument has similar syntax to a "printf" statement. * * Inputs: *C * ctrstr - The text and optional formatting directives to beD * saved in the trace ring buffer, only the following3 * directives are allowed, no width:3 * %s - zero-terminated string< * %a - ascii string (pointer & length)* * %d - decimal value1 * %X - hexadecimal longword1 *  %L - hexadecimal quadwordF * p1-p5 - The corresponding values to be formatted. For the %sG * directive, this is the address of the zero-terminatedJ * string. For the %a directive, this requires 2 arguments,I * first the address of the string buffer, then the lengthJ * of the string (by value). For the other directives, this% * is passed by value. * * Usage Examples: * Macro32:= * exc_pr int ctrstr=,p1=r4D * exc_print ctrstr=,p1=r3,p2=r5 * C: * #include vms_macrosR * exc_print (("this is a C test and needs double-parentheses, index %d", idx ));X * exc_print (("a hex number %X and a quadword %L", irp->irp$l_func, irp->irp$q_fr3 )); * Bliss:8 * exc_print ('this is a Bliss test, index %d', .idx );A * exc_print ('a hex number %X and a quadword %L', .irp, .ucb ); */extern uint64 exc$gq_debug;% #define exc_print(_printf_args) \ if ( exc$gq_debug & 1 ) \ { \6 int *exc_print_rtn = (int *) (exc$gq_debug & ~1); \2 ((void (*)()) *exc_print_rtn) _printf_args ; \ }L/* __ADD_ATOMIC_LONG, and QUAD, generate memory barriers on Alpha and memoryO * fences on IPF around the atomic instruction sequence. __ATOMIC_ADD_LONG, andM * QUAD, do not. This is a little-known fact and __ADD_ATOMIC_LONG, and QUAD,P * are frequently used when the memory barriers are not needed. These macros areM * intended to help code writers and readers with this distinction. Every bit$ * of performance improvement helps. *//#define $ADD_ATOMIC_LONG_BARRIER(data,count){ \1 __ADD_ATOMIC_LONG(data,count); \}1#define $ADD_ATOMIC_LONG_NO_BARRIER(data,count){\1 __ATOMIC_ADD_LONG(data,count); \}/#define $ADD_ATOMIC_QUAD_BARRIER(data,count){ \1 __ADD_ATOMIC_QUAD(data,count); \}1#define $ADD_ATOMIC_QUAD_NO_BARRIER( data,count){\1 __ATOMIC_ADD_QUAD(data,count); \}./* VMS$GET_CURMODE() and VMS$GET_PREVMODE() */B#if defined (__ALPHA) /* Verified for x86 port - Clair Grant */O /* On Alpha, we get the current mode from the Processor Status Longword. */V #define VMS$GET_CURMODE() (((union _PS){.quad=__PAL_RD_PS()}).fields.psl$v_curmod)W #define VMS$GET_PREVMODE() (((union _PS){.quad=__PAL_RD_PS()}).fields.psl$v_prvmod)#elif defined(__ia64)L /* On IA64, we get the current mode from the Previous Function State, asO we can't directly read the cpl part of the Processor Status Register. */e #define VMS$GET_CURMODE() (((PFS){.pfs$iq_prev_func_state=__getReg(_IA64_REG_AR_PFS)}).pfs$v_ppl)W #define VMS$GET_PREVMODE() (((union _PS){.quad=__PAL_RD_PS()}).fields.psl$v_prvmod)#elif defined(__x86_64)G /* On X86, we get the current mode from the SWIS data structure. */C #define VMS$GET_CURMODE() (__readGsWord(SWIS$K_CURMODE_OFFSET))E #define VMS$GET_PREVMODE() (__readGsWord(SWIS$K_PREVMODE_OFFSET))#else/ #error Need architecture specific work here#endif /* VMS$GET_TIMESTAMP() */B#if defined (__ALPHA) /* Verified for x86 port - Clair Grant */K #define VMS$GET_TIMESTAMP() (asm ( "call_pal " STR(EVX$PAL_RSCC) ";" ))#elif defined(__ia64)< #define VMS$GET_TIMESTAMP() (__getReg(_IA64_REG_AR_ITC))#elif defined(__x86_64)8 #define VMS$GET_TIMESTAMP() (__getReg(_X86_REG_TSC))#else/ #error Need architecture specific work here#endif=/* VMS$GET_THREADENV() - get pointer to thread environment */B#if defined (__alpha) /* Verified for x86 port - Clair Grant */6 #define VMS$GET_THREADENV() (asm("call_pal 0x9E"))#elif defined (__ia64)8 #define VMS$GET_THREADENV() (__getReg(_IA64_REG_TP))#elif defined(__x86_64)2 #define VMS$GET_THREADENV() sys$pal_read_unq()#else/ #error Need architecture specific work here#endif>/* VMS$SET_THREADENV(x) - set pointer to thread environment */B#if defined (__alpha) /* Verified for x86 port - Clair Grant */: #define VMS$SET_THREADENV(x) (asm("call_pal 0x9F", x))#elif defined (__ia64)P #define VMS$SET_THREADENV(x) (__setReg(_IA64_REG_TP, (unsigned __int64)(x)))#elif defined(__x86_64)5 #define VMS$SET_THREADENV(x) sys$pal_write_unq(x)#else/ #error Need architecture specific work here#endifB/* VMS$GET_CURR_INVO_CONTEXT() - get current invocation context */B#if defined (__alpha) /* Verified for x86 port - Clair Grant */? #define VMS$GET_CURR_INVO_CONTEXT lib$get_curr_invo_context#elif defined (__ia64)C #define VMS$GET_CURR_INVO_CONTEXT lib$i64_get_curr_invo_context#elif defined(__x86_64)C #define VMS$GET_CURR_INVO_CONTEXT lib$x86_get_curr_invo_context#else/ #error Need architecture specific work here#endifC/* VMS$GET_PREV_INVO_CONTEXT() - get previous invocation context */B#if defined (__alpha) /* Verified for x86 port - Clair Grant */? #define VMS$GET_PREV_INVO_CONTEXT lib$get_prev_invo_context#elif defined (__ia64)C #define VMS$GET_PREV_INVO_CONTEXT lib$i64_get_prev_invo_context#elif defined(__x86_64)C #define VMS$GET_PREV_INVO_CONTEXT lib$x86_get_prev_invo_context#else/ #error Need architecture specific work here#endif3/* VMS$PREV_INVO_END() - previous invocation end */B#if defined (__alpha) /* Verified for x86 port - Clair Grant */& #define VMS$PREV_INVO_END(_ctx_) 1#elif defined (__ia64)A #define VMS$PREV_INVO_END(_ctx_) lib$i64_prev_invo_end(_ctx_)#elif defined(__x86_64)A #define VMS$PREV_INVO_END(_ctx_) lib$x86_prev_invo_end(_ctx_)#else/ #error Need architecture specific work here#endif7/* VMS$INIT_INVO_CONTEXT() - init invocation context */B#if defined (__alpha) /* Verified for x86 port - Clair Grant */* #define VMS$INIT_INVO_CONTEXT(_ctx_) 1#elif defined (__ia64)I #define VMS$INIT_INVO_CONTEXT(_ctx_) lib$i64_init_invo_context(_ctx_)#elif defined(__x86_64)I #define VMS$INIT_INVO_CONTEXT(_ctx_) lib$x86_init_invo_context(_ctx_)#else/ #error Need architecture specific work here#endif'/* VMS$GET_GR - get general register */A#if defined (__ia64) /* Verified for x86 port - Clair Grant */% #define VMS$GET_GR lib$i64_get_gr#elif defined(__x86_64)% #define VMS$GET_GR lib$x86_get_gr#endif'/* VMS$SET_GR - set general register */A#if defined (__ia64) /* Verified for x86 port - Clair Grant */% #define VMS$SET_GR lib$i64_set_gr#elif defined(__x86_64)% #define VMS$SET_GR lib$x86_set_gr#endif/*;+; NOT_X86_READY;K; This macro is intended to act as a marker for sections of code thatI; have not been modified to run on X86 - usually such sections willM; contain SVAPTE, PTE or other references that keep the modules they'reM; in from compiling, or that keep any image containing the modules from; linking.;M; If these sections are not immediately needed (such as for first boot)M; then we can defer work on them and get the modules containing them to>; compile and link cleanly by conditionalizing them out.;O; Besides making it easy to find these sections later on, this macro willN; bugcheck (on X86 only) to prevent any of these sections from executing; without our knowledge.;L; Code should never be conditionalized out like this w/o being guardedN; by this macro, because that would allow it to be silently skipped, and@; would likely lead to hard-to-diagnose run time problems.;K; A common sequence would be (note: in the example below, replace allB; backslash characters "\" with forward slash "/" in actual code):; ;>; not_x86_ready(); \* Code is not ready to run on X86 *\;D; #if !VMS$NOSVAPTE \* Compile if platform supports SVAPTEs *\;0; << ... code that is not X86-ready ... >>;;; #endif \* Compile if platform supports SVAPTEs *\;;-*/#if defined(__x86_64) #define not_x86_ready() \ { \W exe$kprintf("***** %s:%s:%d not_x86_ready() *****\n",__FILE__,__func__,__LINE__); \' bug_check(INCONSTATE,FATAL,COLD); \ }#else#define not_x86_ready()#endif #endif /* __VMS_MACROS_LOADED */wwZU/* * VMS_RANDOM.H *E * VMS-specific definitions for the FreeBSD random number support via * Fortuna. *H * The major purpose of this module is to bridge the set of bits definedI * in RNDBITDEF.SDL (which are the useful bits controlling the collectorsG * in VMS terms) and the enum random_entropy_source which the FreeBSD C * code expects. * * Author: Doug Gordon * * Edit History: *$ * X-2 DAG Doug Gordon 31-Mar-2023: * Add ACCOUNT bit. Remove workaround for RNDBITDEF typo.2 * Use ENVIRONMENTAL_END constant from RNDBITDEF. *% * X-1 DAG Doug Gordon 1-Feb-2022 * Original. */#ifndef _VMS_RANDOM_H_#define _VMS_RANDOM_H_/*G * We want the __NEW_STARLET flavors of our VMS include files but don't< * want to chance disrupting code that includes this header. */#ifndef __NEW_STARLET#define __NEW_STARLET#define __UNDEF_NEW_STARLET#endif#include #include 4extern volatile uint64 EXE$GL_ACTIVE_RANDOM_SOURCES;/*4 * Time between entropy roll-ups from the harvesters2 * One tenth of a second as delta time, in decimal */#define ONE_TENTH_SEC 1000000LL/*J * e num of the various source. Some symbols are retained from the FreeBSDL * flavor for things that *might* get support. NI indicates Not Implemented * at this point. */enum random_entropy_source { RANDOM_START = 0,! RANDOM_CACHED = RANDOM$K_CACHED, /* Environmental sources */> RANDOM_ATTACH = RANDOM$K_ATTACH, /* Device attachment - NI */8 RANDOM_PERCPU = RANDOM$K_PERCPU, /* Per-CPU counters */4 RANDOM_LCKMGR = RANDOM$K_LCKMGR, /* Lock Manager */7 RANDOM_CLUSTER = RANDOM$K_CLUSTER, /* Cluster hooks */> RANDOM_NET_TUN = RANDOM$K_NET_TUN, /* Write to tunnel - NI */C RANDOM_NET_ETHER = RANDOM$K_NET_ETHER, /* Write ethernet packet */? RANDOM_INTERRUPT = RANDOM$K_INTERRUPT, /* Device Interrupts */6 RANDOM_SWI = RANDOM$K_SWI, /* Software Interrupts */7 RANDOM_FS_ATIME = RANDOM$K_FS_ATIME, /* File System */; RANDOM_NPP = RANDOM$K_NPP, /* Pool Packet deallocation */> RANDOM_UMA = RANDOM_NPP, /* Special!! UMA/SLAB Allocator */L RANDOM_ACCOUNT = RANDOM$K_ACCOUNT, /* Accou nting data at job termination */7 RANDOM_ENVIRONMENTAL_END = RANDOM$K_ENVIRONMENTAL_END,8 /* Fast hardware random-number sources from here on. */0 RANDOM_PURE_START = RANDOM$K_RANDOM_PURE_START,H RANDOM_PURE_RDRAND = RANDOM$K_PURE_RDRAND, /* X86 RDRAND instruction */L RANDOM_PURE_VIRTIO = RANDOM$K_PURE_VIRTIO, /* VIRTIO Entropy driver - NI */ ENTROPYSOURCE};R#define RANDOM_HARVEST_EVERYTHING_MASK ((1 << (RANDOM_ENVIRONMENTAL_END + 1)) - 1)[#define RANDOM_HARVEST_PURE_MASK (((1 << ENTROPYSOURCE) - 1) & (-1UL << RANDOM_PURE_START))/*$ * Random harvest routine prototypes */*/* Queued entropy - most common routine */bvoid exe$random_harvest_queue(const void *entropy, u_int size, enum random_entropy_source origin);+/* Fast harvest - high data rate sources */>void exe$random_harvest_fast(const void *entropy, u_int size);:/* Direct entropy harvesting - copy straight to Fortuna */cvoid exe$random_harvest_direct(const void *entropy, u_int size, enum random_entropy_source origin);/** * Macros to ease some of the common calls */Q#define RANDOM_SOURCE(BIT) ((EXE$GL_ACTIVE_RANDOM_SOURCES & RNDBIT$M_##BIT) != 0)g#define NPP_ENTROPY_HARVEST(packet, size) if (RANDOM_SOURCE(NPP)) exe$random_harvest_fast(packet, size)#ifdef __UNDEF_NEW_STARLET#undef __NEW_STARLET#undef __UNDEF_NEW_STARLET#endif#endif /* _VMS_RANDOM_H_ */ww9ZUO/* ************************************************************************* */O/* *  * */O/* * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential * */O/* * proprietary software licensed by VMS Software, Inc., and is not * */O/* * authorized to be used, duplicated or disclosed to anyone without * */O/* * the prior written permission of VMS Software, Inc. * */O/* * Copyright 2019-2022 VMS Software, Inc. * */O/* *  * */O/* ************************************************************************* *//* *++ * FACILITY: * * VMS Library (LIB_H) * * ABSTRACT: *S * This header file contains the x86_cpuid structure definition and associated * inline functions. * * AUTHOR: * * Camiel Vanderhoeven * * CREATION DATE: * * 10-Jun-2019 * * MODIFICATION HISTORY: ** * X-9 CV Camiel Vanderhoeven 29-May-2024: * Fix buffer length issue in x86_cpuid_get_brand_string. ** * X-8 CV Camiel Vanderhoeven 23-Feb-20247 * Include tests for SYSTEM_PRIMITIVES routine variant * selection. */ * X-7 CV-0696 Camiel Vanderhoeven 31-May-2022# * Fix test for AMD vendor string. *# * X-6 DAG Doug Gordon 2-Feb-2022) * Test for support of RDRAND and RDSEED *C * X-5 CEG0921 Clair Grant 25-Sep-2020% * Change comment in X-4 *) * X-4 CEG0912 Clair Grant 24-Sep-2020+ * Replace "// comment" style to eliminate, * confusion when compiling /STANDARD=VAXC. */ * X-3 CV-0435 Camiel Vanderhoeven 26-Aug-2019( * Add functions to detect MCE and MCA. *. * X-2 CV-0417 Camiel Vanderhoeven 3-Jul-2019# * Fix family and model functions. *8 * X-1 CV-0393 Camiel Vanderhoeven 10-Jun-2019 * Initial version. * *-- */#ifndef __X86_CPUID_INFO_H__#define __X86_CPUID_INFO_H__9#include /* C Compiler builtins */#include #include extern SWRPB* exe$gpq_swrpb;"typedef struct x86_cpuid_subleaf { unsigned __int32 eax; unsigned __int32 ebx; unsigned __int32 ecx; unsigned __int32 edx;} X86_CPUID_SUBLEAF;typedef struct x86_cpuid_leaf {" X86_CPUID_SUBLEAF subleaf[64];} X86_CPUID_LEAF;typedef struct x86_cpuid_info {" X86_CPUID_LEAF basic_leaf[64];( X86_CPUID_SUBLEAF extended_leaf[64];} X86_CPUID_INFO;I#defin e _THE_INFO ((X86_CPUID_INFO*)(exe$gpq_swrpb->swrpb$pq_cpuid_info))(#pragma inline(x86_cpuid_max_basic_leaf)4static unsigned int x86_cpuid_max_basic_leaf(void) {3 return _THE_INFO->basic_leaf[0].subleaf[0].eax;}1#pragma inline(x86_cpuid_get_manufacturer_string)Bstatic int x86_cpuid_get_manufacturer_string(int len, char* buf) { if (len<13) return SS$_INVARG;F *(unsigned int*)&buf[0] = _THE_INFO->basic_leaf[0].subleaf[0].ebx;F *(unsigned int*)&buf[4] = _THE_INFO->basic_leaf[0].subleaf[0].edx;F *(unsigned int*)&buf[8] = _THE_INFO->basic_leaf[0].subleaf[0].ecx; buf[12] = '\0'; return SS$_NORMAL;}"#pragma inline(x86_cpuid_is_intel)%static int x86_cpuid_is_intel(void) {< if (_THE_INFO->basic_leaf[0].subleaf[0].ebx == 0x756E6547? && _THE_INFO->basic_leaf[0].subleaf[0].edx == 0x49656E69@ && _THE_INFO->basic_leaf[0].subleaf[0].ecx == 0x6C65746E) return 1; else return 0;} #pragma inline(x86_cpuid_is_amd)#static int x86_cpuid_is_amd(void) {< if (_THE_INFO->basic_leaf[0].subleaf[0].ebx == 0x68747541? && _THE_INFO->basic_leaf[0].subleaf[0].edx == 0x69746E65@ && _THE_INFO->basic_leaf[0].subleaf[0].ecx == 0x444D4163) return 1; else return 0;}%#pragma inline(x86_cpuid_stepping_id)1static unsigned int x86_cpuid_stepping_id(void) {9 return _THE_INFO->basic_leaf[1].subleaf[0].eax & 0xf;}"#pragma inline(x86_cpuid_model_id).static unsigned int x86_cpuid_model_id(void) {B return ((_THE_INFO->basic_leaf[1].subleaf[0].eax & 0xf0) >> 4)@ | ((_THE_INFO->basic_leaf[1].subleaf[0].eax & 0xf0000) >> 12);}##pragma inline(x86_cpuid_family_id)/static unsigned int x86_cpuid_family_id(void) {C return ((_THE_INFO->basic_leaf[1].subleaf[0].eax & 0xf00) >> 8)B | ((_THE_INFO->basic_leaf[1].subleaf[0].eax & 0xff00000) >> 16);}(#pragma inline(x86_cpuid_processor_type)4static unsigned int x86_cpuid_processor_type(void) {D return (_THE_INFO->basic_leaf[1].subleaf[0].eax & 0xf000) >> 12;}"#pragma inline(x86_cpuid_md_clear)%static int x86_cpuid_md_clear(void) {8 if (_THE_INFO->basic_leaf[7].subleaf[0].edx & 0x400) return 1; else return 0;}#pragma inline(x86_cpuid_mce) static int x86_cpuid_mce(void) {7 if (_THE_INFO->basic_leaf[1].subleaf[0].edx & 0x80) return 1; else return 0;}#pragma inline(x86_cpuid_mca) static int x86_cpuid_mca(void) {9 if (_THE_INFO->basic_leaf[1].subleaf[0].edx & 0x4000) return 1; else return 0;}+#pragma inline(x86_cpuid_max_extended_leaf).static int x86_cpuid_max_extended_leaf(void) {8 if (!(_THE_INFO->extended_leaf[0].eax & 0x80000000)) return -1; else5 return _THE_INFO->extended_leaf[0].eax - 0x80000000;}*#pragma inline(x86_cpuid_get_brand_string);static int x86_cpuid_get_brand_string(int len, char* buf) { if (len < 49) return SS$_INVARG;> *(unsigned int*)&buf[0] = _THE_INFO->extended_leaf[2].eax;> *(unsigned int*)&buf [4] = _THE_INFO->extended_leaf[2].ebx;> *(unsigned int*)&buf[8] = _THE_INFO->extended_leaf[2].ecx;? *(unsigned int*)&buf[12] = _THE_INFO->extended_leaf[2].edx;? *(unsigned int*)&buf[16] = _THE_INFO->extended_leaf[3].eax;? *(unsigned int*)&buf[20] = _THE_INFO->extended_leaf[3].ebx;? *(unsigned int*)&buf[24] = _THE_INFO->extended_leaf[3].ecx;? *(unsigned int*)&buf[28] = _THE_INFO->extended_leaf[3].edx;? *(unsigned int*)&buf[32] = _THE_INFO->extended_leaf[4].eax;? *(unsigned int*)&buf[36] = _THE_INFO->extended_leaf[4].ebx;? *(unsigned int*)&buf[40] = _THE_INFO->extended_leaf[4].ecx;? *(unsigned int*)&buf[44] = _THE_INFO->extended_leaf[4].edx; buf[48] = '\0'; return SS$_NORMAL;}/* * Leaf Subleaf Reg Bit * RDRAND 1 0 ECX 30 * RDSEED 7 0 EBX 18 */ #pragma inline(x86_cpuid_rdrand)#static int x86_cpuid_rdrand(void) {= if (_THE_INFO->basic_leaf[1].subleaf[0].ecx & 0x40000000) return 1; else return 0;} #pragma inline(x86_cpuid_rdseed)#static int x86_cpuid_rdseed(void) {: if (_THE_INFO->basic_leaf[7].subleaf[0].ebx & 0x40000) return 1; else return 0;}"#pragma inline(x86_cpuid_fsgsbase)%static int x86_cpuid_fsgsbase(void) {4 if (_THE_INFO->basic_leaf[7].subleaf[0].ebx & 1) return 1; else return 0;}"#pragma inline(x86_cpuid_xsaveopt)%static int x86_cpuid_xsaveopt(void) {6 if (_THE_INFO->basic_leaf[0xd].subleaf[1].eax & 1) return 1; else return 0;}+#pragma inline(x86_cpuid_arch_capabilities).static int x86_cpuid_arch_capabilities(void) {= if (_THE_INFO->basic_leaf[7].subleaf[0].edx & 0x20000000) return 1; else return 0;}#undef _THE_INFO!#endif /* __X86_CPUID_INFO_H__ */wwZU/* * YMF262_REG.H *J * Copyright Digital Equipment Corporation, 1994 All Rights Reserved.P * Unpublished rights reserved under the copyright laws of the United States. * M * The software contained on this media is proprietary to and embodies theQ * confidential technology of Digital Equipment Corporation. Possession, use,O * duplication or dissemination of the software and media is authorized onlyM * pursuant to a valid written license from Digital Equipment Corporation. * L * RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S.H * Government is subject to restrictions as set forth in SubparagraphK * (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable. * M * ----------------------------------------------------------------------- * * ABSTRACT: ** * Yamaha MIDI Chip register definitions. * * AUTHOR: *# * This file was taken from OSF/1. * * MODIFIED BY: * * X-1 WDA W.D.Arbo 8-Mar-1994' * Original VMS version.  * */#ifndef YMF262_REG_H#define YMF262_REG_H$#define YMF_LsiTest 0x01$#define YMF_Timer1 0x02$#define YMF_Timer2   0x03$#define YMF_TimerControl 0x04$#define YMF_NTS 0x08$#define YMF_KeyScaleRate00 0x20$#define YMF_KeyScaleRate01 0x21$#define YMF_KeyScaleRate02 0x22$#define YMF_KeyScaleRate03 0x23$#define YMF_KeyScaleRate04 0x24$#define YMF_KeyScaleRate05 0x25$#define YMF_KeyScaleRate06 0x26$#define YMF_KeyScaleRate07 0x27$#define YMF_KeyScaleRate08 0x28$#define YMF_KeyScaleRate09 0x29$#define YMF_KeyScaleRate0a 0x 2a$#define YMF_KeyScaleRate0b 0x2b$#define YMF_KeyScaleRate0c 0x2c$#define YMF_KeyScaleRate0d 0x2d$#define YMF_KeyScaleRate0e 0x2e$#define YMF_KeyScaleRate0f 0x2f$#define YMF_KeyScaleRate10 0x30$#define YMF_KeyScaleRate11 0x31$#define YMF_KeyScaleRate12 0x32$#define YMF_KeyScaleRate13 0x33$#define YMF_KeyScaleRate14 0x34$#define YMF_KeyScaleRate15 0x35$#define YMF_KSL_TL00 0x40$#define YMF_KSL_TL01 0x41$#defin e YMF_KSL_TL02 0x42$#define YMF_KSL_TL03 0x43$#define YMF_KSL_TL04 0x44$#define YMF_KSL_TL05 0x45$#define YMF_KSL_TL06 0x46$#define YMF_KSL_TL07 0x47$#define YMF_KSL_TL08 0x48$#define YMF_KSL_TL09 0x49$#define YMF_KSL_TL0a 0x4a$#define YMF_KSL_TL0b 0x4b$#define YMF_KSL_TL0c 0x4c$#define YMF_KSL_TL0d 0x4d$#define YMF_KSL_TL0e 0x4e$#define YMF_KSL_TL 0f 0x4f$#define YMF_KSL_TL10 0x50$#define YMF_KSL_TL11 0x51$#define YMF_KSL_TL12 0x52$#define YMF_KSL_TL13 0x53$#define YMF_KSL_TL14 0x54$#define YMF_KSL_TL15 0x55$#define YMF_AR_DR00 0x60$#define YMF_AR_DR01 0x61$#define YMF_AR_DR02 0x62$#define YMF_AR_DR03 0x63$#define YMF_AR_DR04 0x64$#define YMF_AR_DR05 0x65$#define YMF_AR_DR06   0x66$#define YMF_AR_DR07 0x67$#define YMF_AR_DR08 0x68$#define YMF_AR_DR09 0x69$#define YMF_AR_DR0a 0x6a$#define YMF_AR_DR0b 0x6b$#define YMF_AR_DR0c 0x6c$#define YMF_AR_DR0d 0x6d$#define YMF_AR_DR0e 0x6e$#define YMF_AR_DR0f 0x6f$#define YMF_AR_DR10 0x70$#define YMF_AR_DR11 0x71$#define YMF_AR_DR12 0x72$#define YMF_AR_DR13 0x73$#define YMF_AR_DR14 0x74$#define YMF_AR_DR15 0x75$#define YMF_SL_RR00 0x80$#define YMF_SL_RR01 0x81$#define YMF_SL_RR02 0x82$#define YMF_SL_RR03 0x83$#define YMF_SL_RR04 0x84$#define YMF_SL_RR05 0x85$#define YMF_SL_RR06 0x86$#define YMF_SL_RR07 0x87$#define YMF_SL_RR08 0x88$#define YMF_SL_RR09 0x89$#define YMF_SL_RR0a 0x8a$#define YMF_SL_RR0b 0x8b$#define YMF_SL_RR0c 0x8c$#define YMF_SL_RR0d 0x8d$#define YMF_SL_RR0e 0x8e$#define YMF_SL_RR0f 0x8f$#define YMF_SL_RR10 0x90$#define YMF_SL_RR11 0x91$#define YMF_SL_RR12 0x92$#define YMF_SL_RR13 0x93$#define YMF_SL_RR14 0x94$#define YMF_SL_RR15 0x95##define YMF_AttackRate00 0x0#endif /* YMF262_REG_H */wwZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc.  **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 16-MAR-1993 10:47:10 $1$DGA8345:[LIB_H.SRC]ABDDEF.SDL;1 *//******************************************************* *************************************************************************//*** MODULE $ABDDEF ***/#ifndef __ABDDEF_LOADED#define __ABDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define ABD$K_LENGTH 8 /* SIZE OF DESCRIPTOR */N#define ABD$C_LENGTH 8 /* SIZE OF DESCRIPTOR */R#define ABD$S_ABDDEF 8 /* OLD SIZE NAME, SYNONYM FOR ABD$S_ABD */N#define ABD$C_WINDOW 0 /* DESCRIPTOR FOR WINDOW ADDRESS */N#define ABD$C_FIB 1 /* DESCRIPTOR FOR FIB */N#define ABD$C_NAME 2 /* DESCRIPTOR FOR NAME STRING */N#define ABD$C_RESL 3  /* DESCRIPTOR FOR RESULT LENGTH */N#define ABD$C_RES 4 /* DESCRIPTOR FOR RESULT STRING */N#define ABD$C_ATTRIB 5 /* FIRST ATTRIBUTE DESCRIPTOR */ typedef struct _abd {N unsigned short int abd$w_text; /* WORD OFFSET TO DATA TEXT */N unsigned short int abd$w_count; /* BYTE COUNT OF TEXT */N void *abd$l_userva; /* USER VIRTUAL ADDRESS OF TEXT */ } ABD; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ABDDEF_LOADED */ wwZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 05-OCT-2018 17:36:33 $1$DGA8345:[LIB_H.SRC]ACBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ACBDEF ***/#ifndef __ACBDEF_LOADED#define __ACBDEF_LOADED 1  G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* AST CONTROL BLOCK DEFINITIONS  */N/* */N/* AST CONTROL BLOCKS EXIST AS SEPARATE STRUCTURES AND AS SUBSTRUCTURES */N/* WITHIN LARGER CONTROL BLOCKS SUCH AS I/O REQUEST PACKETS AND TIMER */N/* QUEUE ENTRIES. */N/* */N/*- */ #define ACB$M_FLAGS_VALID 0x4#define ACB$M_POSIX_ACB 0x8#define ACB$M_PKAST 0x10#define ACB$M_NODELETE 0x20#define ACB$M_QUOTA 0x40#define ACB$M_KAST 0x80#define ACB$M_THREAD_SAFE 0x1"#define ACB$M_THREAD_PID_VALID 0x2#define ACB$M_UPCALL 0x4#define ACB$M_FASTIO 0x8#define ACB$M_64BITS 0x10#define ACB$M_NOFLOAT 0x20#define ACB$M_KAST_NOFLOAT 0x40'#define ACB$M_USER_THREAD_ID_VALID 0x80#define ACB$M_EXCLUSIVE 0x100#define ACB$M_TOLERANT 0x200#define ACB$M_NODUP 0x400"#define ACB$M_FIRST_IN_QUEUE 0x800 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _acb {#pragma __nomember_alignmentN struct _acb *acb$l_astqfl; /*AST QUEUE FORWARD LINK */N struct _acb *acb$l_astqbl; /*AST QUEUE BACKWARD LINK */N unsigned short int acb$w_size; /*STRUCTURE SIZE IN BYTES  */N unsigned char acb$b_type; /*STRUCTURE TYPE CODE */ __union {N unsigned char acb$b_rmod; /*REQUEST ACCESS MODE */ __struct {N unsigned acb$v_mode : 2; /*MODE FOR FINAL DELIVERY */N unsigned acb$v_flags_valid : 1; /*FLAGS IN FLAG_ID ARE VALID */Q unsigned acb$v_posix_acb : 1; /*USED FOR DELIVERING SIGNALS/EVENTS */N unsigned acb$v_pkast : 1; /*PIGGY BACK S !PECIAL KERNEL AST */N unsigned acb$v_nodelete : 1; /*DON'T DELETE ACB ON DELIVERY */N unsigned acb$v_quota : 1; /*ACCOUNT FOR QUOTA */N unsigned acb$v_kast : 1; /*SPECIAL KERNEL AST */ } acb$r_rmod_bits; } acb$r_rmod_overlay;N unsigned int acb$l_pid; /*PROCESS ID OF REQUEST */ __union {N void (*acb$l_ast)(); /*AST ROUTINE ADDRESS */N " unsigned int acb$l_acb64x; /*OFFSET TO ACB64X STRUCTURE */ } acb$r_ast_overlay;N unsigned int acb$l_astprm; /*AST PARAMETER */ __union {N unsigned int acb$l_flags; /*AST CONTROL FLAGS */ __struct {U unsigned acb$v_thread_safe : 1; /*AST DOES NOT REQUIRE SYNCHRONIZATION */b unsigned acb$v_thread_pid_valid : 1; /*THREAD_PID FIELD CONTAINS A VALID THREAD PID */N # unsigned acb$v_upcall : 1; /*THIS AST IS ALREADY AN UPCALL */N unsigned acb$v_fastio : 1; /* This ACB is really a Fast-IO IRP */R unsigned acb$v_64bits : 1; /* This ACB has a 64-bit AST and ASTPRM */W unsigned acb$v_nofloat : 1; /* The AST routine will not use FP registers */k unsigned acb$v_kast_nofloat : 1; /* The special kernel AST routine will not use FP registers */k unsigned acb$v_user_thread_id_valid : 1; /* USER_THREAD_ID f$ield contains a valid identifier */N/* Only valid in conjunction with '64BITS' */Z unsigned acb$v_exclusive : 1; /*AST REQUIRES EXCLUSIVE ACCESS TO INNER MODE */i unsigned acb$v_tolerant : 1; /*THREAD SAFE AST WHICH BLOCKS EXCLUSIVE ACCESS TO INNER MODE */i unsigned acb$v_nodup : 1; /* Do not queue the ACB if ASTADR/ASTPRM match ACB at the tail */u unsigned acb$v_first_in_queue : 1; /* Should be queued first. Don't % put (e.g.) stalled ACBs in front. */' unsigned acb$v_fill_0_ : 4; } acb$r_flag_bits; } acb$r_flags_overlay;N unsigned int acb$l_thread_pid; /*PID of actual target KTB */O void (*acb$l_kast)(); /*INTERNAL KERNEL MODE XFER ADDRESS */ } ACB; #if !defined(__VAXC)0#define acb$b_rmod acb$r_rmod_overlay.acb$b_rmod@#define acb$v_mode acb$r_rmod_overlay.acb$r_rmod_bits.acb$v_modeN#define acb$v_flags_valid acb$r_rmod_overlay &.acb$r_rmod_bits.acb$v_flags_validJ#define acb$v_posix_acb acb$r_rmod_overlay.acb$r_rmod_bits.acb$v_posix_acbB#define acb$v_pkast acb$r_rmod_overlay.acb$r_rmod_bits.acb$v_pkastH#define acb$v_nodelete acb$r_rmod_overlay.acb$r_rmod_bits.acb$v_nodeleteB#define acb$v_quota acb$r_rmod_overlay.acb$r_rmod_bits.acb$v_quota@#define acb$v_kast acb$r_rmod_overlay.acb$r_rmod_bits.acb$v_kast-#define acb$l_ast acb$r_ast_overlay.acb$l_ast3#define acb$l_acb64x acb$r_ast_overlay.acb$l_acb64x3#define acb$l_fl'ags acb$r_flags_overlay.acb$l_flagsO#define acb$v_thread_safe acb$r_flags_overlay.acb$r_flag_bits.acb$v_thread_safeY#define acb$v_thread_pid_valid acb$r_flags_overlay.acb$r_flag_bits.acb$v_thread_pid_validE#define acb$v_upcall acb$r_flags_overlay.acb$r_flag_bits.acb$v_upcallE#define acb$v_fastio acb$r_flags_overlay.acb$r_flag_bits.acb$v_fastioE#define acb$v_64bits acb$r_flags_overlay.acb$r_flag_bits.acb$v_64bitsG#define acb$v_nofloat acb$r_flags_overlay.acb$r_flag_bits.acb$v_nofloatQ#def(ine acb$v_kast_nofloat acb$r_flags_overlay.acb$r_flag_bits.acb$v_kast_nofloata#define acb$v_user_thread_id_valid acb$r_flags_overlay.acb$r_flag_bits.acb$v_user_thread_id_validK#define acb$v_exclusive acb$r_flags_overlay.acb$r_flag_bits.acb$v_exclusiveI#define acb$v_tolerant acb$r_flags_overlay.acb$r_flag_bits.acb$v_tolerantC#define acb$v_nodup acb$r_flags_overlay.acb$r_flag_bits.acb$v_nodupU#define acb$v_first_in_queue acb$r_flags_overlay.acb$r_flag_bits.acb$v_first_in_queue"#endif /* #if ) !defined(__VAXC) */ N#define ACB$K_LENGTH 36 /* Length of block. */N#define ACB$C_LENGTH 36 /* Length of block. */R#define ACB$S_ACBDEF 36 /* Old size name, synonym for ACB$S_ACB */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _acb64x {#pragma __nomemb *er_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void (*acb64x$pq_ast)(); /*64-BIT AST ROUTINE ADDRESS */#else unsigned __int64 acb64x$pq_ast;#endifN unsigned __int64 acb64x$q_astprm; /*64-BIT AST PARAMETER */P unsigned __int64 acb64x$q_user_thread_id; /*Unique user thread identifier */ } ACB64X;N#define +ACB64X$K_LENGTH 24 /* Length of block. */N#define ACB64X$C_LENGTH 24 /* Length of block. */#define ACB64$M_FLAGS_VALID 0x4#define ACB64$M_POSIX_ACB 0x8#define ACB64$M_PKAST 0x10#define ACB64$M_NODELETE 0x20#define ACB64$M_QUOTA 0x40#define ACB64$M_KAST 0x80#define ACB64$M_THREAD_SAFE 0x1$#define ACB64$M_THREAD_PID_VALID 0x2#define ACB64$M_UPCALL 0x4#define ACB64$M_FASTIO 0x8#define ACB64$M_64BITS 0x10#define ACB64$,M_NOFLOAT 0x20!#define ACB64$M_KAST_NOFLOAT 0x40)#define ACB64$M_USER_THREAD_ID_VALID 0x80#define ACB64$M_EXCLUSIVE 0x100#define ACB64$M_TOLERANT 0x200 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _acb64 {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __-required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _acb *acb64$l_astqfl; /*AST QUEUE FORWARD LINK */N struct _acb *acb64$l_astqbl; /*AST QUEUE BACKWARD LINK */N unsigned short int acb64$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char acb64$b_type; /*STRUCTURE TYPE CODE */ __union {N unsigned char acb64$b_rmod; /*REQUEST ACCESS MODE */. __struct {N unsigned acb64$v_mode : 2; /*MODE FOR FINAL DELIVERY */c unsigned acb64$v_flags_valid : 1; /*FLAGS IN FLAG_ID ARE VALID (always set in ACB64) */S unsigned acb64$v_posix_acb : 1; /*USED FOR DELIVERING SIGNALS/EVENTS */N unsigned acb64$v_pkast : 1; /*PIGGY BACK SPECIAL KERNEL AST */N unsigned acb64$v_nodelete : 1; /*DON'T DELETE ACB ON DELIVERY */N unsigned acb64$v_quota : 1; /*ACCOUNT FOR /QUOTA */N unsigned acb64$v_kast : 1; /*SPECIAL KERNEL AST */ } acb64$r_rmod_bits; } acb64$r_rmod_overlay;N unsigned int acb64$l_pid; /*PROCESS ID OF REQUEST */l unsigned int acb64$l_acb64x; /*OFFSET TO ACB64X STRUCTURE (Always equals ACB64$Q_AST in ACB64) */N int acb64$l_fill_1; /*Not used in ACB64 (ASTPRM in ACB) */ __union {N unsigned int acb64$l_flags; /*AST 0CONTROL FLAGS */ __struct {W unsigned acb64$v_thread_safe : 1; /*AST DOES NOT REQUIRE SYNCHRONIZATION */d unsigned acb64$v_thread_pid_valid : 1; /*THREAD_PID FIELD CONTAINS A VALID THREAD PID */N unsigned acb64$v_upcall : 1; /*THIS AST IS ALREADY AN UPCALL */O unsigned acb64$v_fastio : 1; /* This ACB is really a Fast-IO IRP */i unsigned acb64$v_64bits : 1; /* This ACB has a 64-bit AST and ASTPRM (always set in 1ACB64) */Y unsigned acb64$v_nofloat : 1; /* The AST routine will not use FP registers */m unsigned acb64$v_kast_nofloat : 1; /* The special kernel AST routine will not use FP registers */m unsigned acb64$v_user_thread_id_valid : 1; /* USER_THREAD_ID field contains a valid identifier */\ unsigned acb64$v_exclusive : 1; /*AST REQUIRES EXCLUSIVE ACCESS TO INNER MODE */k unsigned acb64$v_tolerant : 1; /*THREAD SAFE AST WHICH BLOCKS EXCLUSIVE 2ACCESS TO INNER MODE */) unsigned acb64$v_fill_1_ : 6; } acb64$r_flag_bits; } acb64$r_flags_overlay;N unsigned int acb64$l_thread_pid; /*PID of actual target KTB */O void (*acb64$l_kast)(); /*INTERNAL KERNEL MODE XFER ADDRESS */N int acb64$l_fill_2; /*FILL TO QUADWORD ALIGN ACB64X */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long / 3* And set ptr size default to 64-bit pointers */N void (*acb64$pq_ast)(); /*64-BIT AST ROUTINE ADDRESS */#else unsigned __int64 acb64$pq_ast;#endifN unsigned __int64 acb64$q_astprm; /*64-BIT AST PARAMETER */O unsigned __int64 acb64$q_user_thread_id; /*Unique user thread identifier */ } ACB64; #if !defined(__VAXC)6#define acb64$b_rmod acb64$r_rmod_overlay.acb64$b_rmodH#define acb64$v_mode acb64$r_rmod_overlay.acb64$r_rmod_bits.acb64$v_4modeV#define acb64$v_flags_valid acb64$r_rmod_overlay.acb64$r_rmod_bits.acb64$v_flags_validR#define acb64$v_posix_acb acb64$r_rmod_overlay.acb64$r_rmod_bits.acb64$v_posix_acbJ#define acb64$v_pkast acb64$r_rmod_overlay.acb64$r_rmod_bits.acb64$v_pkastP#define acb64$v_nodelete acb64$r_rmod_overlay.acb64$r_rmod_bits.acb64$v_nodeleteJ#define acb64$v_quota acb64$r_rmod_overlay.acb64$r_rmod_bits.acb64$v_quotaH#define acb64$v_kast acb64$r_rmod_overlay.acb64$r_rmod_bits.acb64$v_kast9#define acb64$l_flag5s acb64$r_flags_overlay.acb64$l_flagsW#define acb64$v_thread_safe acb64$r_flags_overlay.acb64$r_flag_bits.acb64$v_thread_safea#define acb64$v_thread_pid_valid acb64$r_flags_overlay.acb64$r_flag_bits.acb64$v_thread_pid_validM#define acb64$v_upcall acb64$r_flags_overlay.acb64$r_flag_bits.acb64$v_upcallM#define acb64$v_fastio acb64$r_flags_overlay.acb64$r_flag_bits.acb64$v_fastioM#define acb64$v_64bits acb64$r_flags_overlay.acb64$r_flag_bits.acb64$v_64bitsO#define acb64$v_nofloat acb64$r_flag6s_overlay.acb64$r_flag_bits.acb64$v_nofloatY#define acb64$v_kast_nofloat acb64$r_flags_overlay.acb64$r_flag_bits.acb64$v_kast_nofloati#define acb64$v_user_thread_id_valid acb64$r_flags_overlay.acb64$r_flag_bits.acb64$v_user_thread_id_validS#define acb64$v_exclusive acb64$r_flags_overlay.acb64$r_flag_bits.acb64$v_exclusiveQ#define acb64$v_tolerant acb64$r_flags_overlay.acb64$r_flag_bits.acb64$v_tolerant"#endif /* #if !defined(__VAXC) */ N#define ACB64$K_LENGTH 64 /* Length 7of block. */N#define ACB64$C_LENGTH 64 /* Length of block. */  #ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save&#pragma __required_pointer_size __longDtypedef struct _acb * ACB_PQ; /* pointer to an ACB structure */Otypedef struct _acb ** ACB_PPQ; /* pointer a pointer to an ACB structure */Jtypedef struct _acb64x * ACB64X_PQ; /* pointer to an ACB64X structure */Utypedef struct _acb64x ** ACB64X_PPQ; /* pointe 8r a pointer to an ACB64X structure */'#pragma __required_pointer_size __shortDtypedef struct _acb * ACB_PL; /* pointer to an ACB structure */Otypedef struct _acb ** ACB_PPL; /* pointer a pointer to an ACB structure */Jtypedef struct _acb64x * ACB64X_PL; /* pointer to an ACB64X structure */Utypedef struct _acb64x ** ACB64X_PPL; /* pointer a pointer to an ACB64X structure */)#pragma __required_pointer_size __restore#elsetypedef __int64 ACB_PQ;typedef __int64 ACB_PPQ;type 9def __int64 ACB64X_PQ;typedef __int64 ACB64X_PPQ;typedef __int32 ACB_PL;typedef __int32 ACB_PPL;typedef __int32 ACB64X_PL;typedef __int32 ACB64X_PPL;#endifN/* */N/* In order to make the inner mode semaphore history trace in SDA readable, */N/* the following symbols are defined. These are the values that are stored */P/* in the second longword of the semaphore history record. SDA automatically */O/* tries to :symbolize these values. By creating named values, the semaphore */N/* history can be effectively read like prose. */N/* */N/* Note that __RELEASE_KERNEL_AST is defined by hand in ASTDEL_STACK.M64 */N/* */"#define ACQUIRE_SCH$QAST 180355072$#define ACQUIRE_KERNEL_AST 178257920"#define ACQUIRE_EXEC_AST 178323456 #defin ;e ACQUIRE_SPKAST 178388992##define ACQUIRE_PIGGYBACK 178454528&#define __RELEASE_KERNEL_AST 183500800$#define __RELEASE_EXEC_AST 183566336"#define __RELEASE_SPKAST 183631872%#define __RELEASE_PIGGYBACK 183697408%#define __RELEASE_AST_ERROR 183369728$#define __RELEASE_ASTFAULT 183435264 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined requ<ired ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ACBDEF_LOADED */ ww0KZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR d=isclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without> **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVM ?S SDL V3.7 */F/* Source: 07-MAY-2001 13:54:39 $1$DGA8345:[LIB_H.SRC]ACMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ACMDEF ***/#ifndef __ACMDEF_LOADED#define __ACMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr@ size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_sAtruct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* ACMDEF - ACCOUNTING MANAGER DEFINITIONS */N/*- */N#define ACM$S_ACMDEF 2 /* Old size name, synonym */ typedef struct _acm { __Bstruct {N unsigned acm$v_process : 1; /* PROCESS ACCOUNTING ENABLED */N unsigned acm$v_image : 1; /* IMAGE ACCOUNTING ENABLED */N unsigned acm$v_interactive : 1; /* INTERACTIVE ACCOUNTING ENABLED */O unsigned acm$v_logfail : 1; /* LOGIN FAILURE ACCOUNTING ENABLED */N unsigned acm$v_subprocess : 1; /* SUBPROCESS ACCOUNTING ENABLED */R unsigned acm$v_detached : 1; /* DETACHED PROCESS ACCOUNTING ENABLED */N Cunsigned acm$v_batch : 1; /* BATCH ACCOUNTING ENABLED */Q unsigned acm$v_network : 1; /* NETWORK PROCESS ACCOUNTING ENABLED */N unsigned acm$v_print : 1; /* PRINT JOB ACCOUNTING ENABLED */N unsigned acm$v_user_data : 1; /* USER_DATA ACCOUNTING ENABLED */N unsigned acm$v_acm_func : 1; /* ACM FUNCTION ACCOUNTING ENABLED */Q unsigned acm$v_sys_func : 1; /* SYSTEM FUNCTION ACCOUNTING ENABLED */N unsigned acm$v_cca Denab : 1; /* CHARGE CODE ACCOUNTING ENABLED */N unsigned acm$v_ccvenab : 1; /* CHARGE CODE VALIDATION ENABLED */# unsigned acm$v_fill_0_ : 2; } acm$r_acmdef_bits; } ACM; #if !defined(__VAXC)5#define acm$v_process acm$r_acmdef_bits.acm$v_process1#define acm$v_image acm$r_acmdef_bits.acm$v_image=#define acm$v_interactive acm$r_acmdef_bits.acm$v_interactive5#define acm$v_logfail acm$r_acmdef_bits.acm$v_logfail;#define acm$v_subprocess acm$r_acmdef_ Ebits.acm$v_subprocess7#define acm$v_detached acm$r_acmdef_bits.acm$v_detached1#define acm$v_batch acm$r_acmdef_bits.acm$v_batch5#define acm$v_network acm$r_acmdef_bits.acm$v_network1#define acm$v_print acm$r_acmdef_bits.acm$v_print9#define acm$v_user_data acm$r_acmdef_bits.acm$v_user_data7#define acm$v_acm_func acm$r_acmdef_bits.acm$v_acm_func7#define acm$v_sys_func acm$r_acmdef_bits.acm$v_sys_func5#define acm$v_ccaenab acm$r_acmdef_bits.acm$v_ccaenab5#define acm$v_ccvenab acm$r_acmdFef_bits.acm$v_ccvenab"#endif /* #if !defined(__VAXC) */   9#ifdef __cplusplus /* Define structure prototypes */ struct _psb; #endif /* #ifdef __cplusplus */ typedef struct _acmhdr {N unsigned short int acm$w_type; /* MESSAGE TYPE */N unsigned short int acm$w_mailbox; /* MAILBOX UNIT NUMBER */N __union { /* SECURITY PROFILES */N __struct { /* PRIMARY SECUR GITY PROFILE */N unsigned __int64 acm$q_prvmsk; /* PROCESS PRIVILEGE MASK */ __union {N unsigned int acm$l_uic; /* PROCESS UIC */ __struct {N unsigned short int acm$w_mem; /* MEMBER UIC */N unsigned short int acm$w_grp; /* GROUP UIC */' } acm$r_uic_fields;$ } acm$r_uic_overlay; } acm$r_security H_1;N __struct { /* ALTERNATE SECURITY PROFILE */N struct _psb *acm$l_psb_address; /* ADDRESS OF CLONED PERSONA */" char acm$$_fill_1 [8]; } acm$r_security_2;! } acm$r_security_profile;N char acm$t_username [12]; /* USERNAME */N char acm$t_account [8]; /* ACCOUNT NAME */N unsigned char acm$b_procpri; /* PROCESS BASE PRIORITY I */N unsigned char acm$b_rmod; /* REQUESTOR'S ACCESS MODE */O char acm$$_fill_1 [2]; /* SPARE BYTES (LONGWORD ALIGNMENT) */N unsigned int acm$l_pid; /* PROCESS ID */N unsigned int acm$l_sts; /* PROCESS STATUS */N unsigned int acm$l_owner; /* OWNER PROCESS ID (0 => NONE) */S char acm$t_terminal [8]; /* TERMINAL NAME (COUNTED ASCII STRING) */N unsigned J __int64 acm$q_systime; /* CURRENT SYSTEM TIME */ } ACMHDR; #if !defined(__VAXC)I#define acm$q_prvmsk acm$r_security_profile.acm$r_security_1.acm$q_prvmskU#define acm$l_uic acm$r_security_profile.acm$r_security_1.acm$r_uic_overlay.acm$l_uicf#define acm$w_mem acm$r_security_profile.acm$r_security_1.acm$r_uic_overlay.acm$r_uic_fields.acm$w_memf#define acm$w_grp acm$r_security_profile.acm$r_security_1.acm$r_uic_overlay.acm$r_uic_fields.acm$w_grpS#define acm$l_psb_addres Ks acm$r_security_profile.acm$r_security_2.acm$l_psb_address"#endif /* #if !defined(__VAXC) */ N#define ACM$S_ACMDEF1 76 /* Old size name - synonym */ @typedef struct _acm1 { /* WARNING: aggregate has origin of -8 */; /* WARNING: aggregate element "acm$w_msgsts" ignored */; /* WARNING: aggregate element "acm$w_msglen" ignored */; /* WARNING: aggregate element "acm$l_procid" ignored */ ACMHDR acm$r_acmhdr;N/* L */N/* SEND TO ACCOUNTING MANAGER FIELDS */N/* */ } ACM1;N#define ACM$S_ACMDEF2 326 /* Old size name - synonym */ typedef struct _acm2 { ACMHDR acm$r_acmhdr;N unsigned short int acm$w_userreq; /* USER REQUEST TYPE */N char acm$t_data [256]; /* USER DATA */NM/* */N/* PROCESS/IMAGE DELETE/PURGE FIELDS */N/* */ } ACM2;#define ACM$M_UIDGID 0x1\#define ACM$K_PROCLEN 144 /* MIN. PROCESS/IMAGE TERMINATION MESSAGE LENGTH */\#define ACM$C_PROCLEN 144 /* MIN. PROCESS/IMAGE TERMINATION MESSAGE LENGTH */N#define ACM$S_ACMDEF3 160 N /* Old size name - synonym */ typedef struct _acm3 { ACMHDR acm$r_acmhdr;N unsigned __int64 acm$q_login; /* PROCESS/IMAGE START TIME */N unsigned int acm$l_finalsts; /* PROCESS FINAL STATUS */N unsigned int acm$l_imgcnt; /* IMAGE EXECUTION COUNT */N unsigned int acm$l_cputime; /* CPU USAGE */N unsigned int acm$l_pageflts; /* PAGEFAULT COUNT */N unsignOed int acm$l_pgfltio; /* PAGEFAULT I/O */N unsigned int acm$l_wspeak; /* WORKING SET PEAK */N unsigned int acm$l_pgflpeak; /* PAGE FILE PEAK */N unsigned int acm$l_diocnt; /* DIRECT I/O COUNT */N unsigned int acm$l_biocnt; /* BUFFERED I/O COUNT */N unsigned int acm$l_volumes; /* VOLUME MOUNT COUNT */N unsigned int acm$l_vp_cputime; P /* VECTOR CPU TIME */T unsigned short int acm$w_nodeaddr; /* MESSAGE OFFSET TO REMOTE NODE ADDRESS */Q unsigned short int acm$w_nodename; /* MESSAGE OFFSET TO REMOTE NODE NAME */N unsigned short int acm$w_remoteid; /* MESSAGE OFFSET TO REMOTE ID */N unsigned short int acm$w_imagename; /* MESSAGE OFFSET TO IMAGE NAME */U unsigned short int acm$w_fulladdr; /* MESSAGE OFFSET to remote PhaseV address */O unsigned short int acm$w_fullname; /* M QESSAGE OFFSET to remote Fullname */ __union {N int acm$l_flags; /* FLAGS */ __struct {N unsigned acm$v_uidgid : 1; /* (0) NOT PRESENT/(1) = PRESENT */' unsigned acm$v_fill_3_ : 7; } acm$r_fill_2_; } acm$r_fill_1_;N unsigned int acm$l_posix_uid; /* POSIX UID */N unsigned int acm$l_posix_gid; /* POSIX GID */Z int acm$ Rl_qmgrs_used [4]; /* BITMAP OF QUEUE MANAGERS ACCESSED BY PROCESS */N/* */N/* SNDJBC MESSAGE FIELDS */N/* */ } ACM3; #if !defined(__VAXC)-#define acm$l_flags acm$r_fill_1_.acm$l_flags=#define acm$v_uidgid acm$r_fill_1_.acm$r_fill_2_.acm$v_uidgid"#endif /* #if !defined(__VAXC) */S #define ACM$S_SNDJBCDEF 90N#define ACM$S_ACMDEF4 90 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _iosb; #endif /* #ifdef __cplusplus */ typedef struct _acm4 { ACMHDR acm$r_acmhdr;N unsigned int acm$l_imagecnt; /* IMAGE COUNT FOR PROCESS */N unsigned int acm$l_efn; /* COMPLETION EVENT FLAG */N struct _iosb *acm$l_iosb; /* COMPLETION IOSB A TDDRESS */N void (*acm$l_astadr)(); /* COMPLETION AST ADRESS */N unsigned int acm$l_astprm; /* COMPLETION AST PARAMETER */N unsigned short int acm$w_func; /* SNDJBC/GETQUI FUNCTION CODE */#if defined(__VAXC) char acm$t_itmlst[];#elseS/* Warning: empty char[] member for acm$t_itmlst at end of structure not created */"#endif /* #if defined(__VAXC) */ } ACM4; $#pragma __member_alignment __restoreR#ifdef __INIUTIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ACMDEF_LOADED */ wwPZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidentVial proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential W**/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*******************X*************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:39 by OpenVMS SDL V3.7 */P/* Source: 11-FEB-2004 12:47:04 $1$DGA8345:[LIB_H.SRC]ACMEAGENT_CB_DEF.SDL;1 *//********************************************************************************************************************************/,/*** MODULE $ACMEAGENT_CB_DEF IDENT X-1 ***/!#ifndef __ACMEAGENT_CB_DEF_LOADED##define __ACMEAGENT_CB_DEF_LOADED Y1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#definZe __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* [ */N/* ACM Kernel Callback Routines Protypes */N/* */N/*- */N/* */N/* Acquire ACME Resource */N/* */I/* acme$cb_acqui\re_resource wqe, resource_type, resource_value */N/* */>/* wqe = address of ACM Work Queue Entry */G/* resource_type = type of (ACME defined) resource to allocate */U/* resource_value = address of quadword to receive the value of resource allocated */N/* */;#define acme$cb_acquire_resource ACME$CB_ACQUIRE_RESOURCE ] /int acme$cb_acquire_resource(__unknown_params);N/* */N/* Acquire ACME AST Context */N/* */I/* acme$cb_acquire_acme_ast wqe, ast_handler, ast_context, */&/* ast_routine, ast_parameter */N/* */>/* wqe = addr^ess of ACM Work Queue Entry */E/* ast_handler = address of 64-bit pointer to receive AST handler */;/* (interceptor procedure) address */F/* ast_context = address of quadword to receive AST parameter value */H/* ast_routine = address of ACME's AST service routine to invoke upon */;/* AST delivery */K/* ast_parameter = address of quadword containing ACME specific value to */B/* pass to the ACME's AST servic _e routine upon AST delivery */N/* */;#define acme$cb_acquire_acme_ast ACME$CB_ACQUIRE_ACME_AST /int acme$cb_acquire_acme_ast(__unknown_params);N/* */N/* Acquire ACME RMS AST Context */N/* */I/* acme$cb_acquire_acme_rmsast wqe, a `st_handler, ast_context */&/* ast_routine, ast_parameter */N/* */>/* wqe = address of ACM Work Queue Entry */E/* ast_handler = address of 64-bit pointer to receive AST handler */;/* (interceptor procedure) address */F/* ast_context = address of quadword to receive AST parameter value */H/* ast_routine = address of ACME's AST service routine to invoke upon */;/* a AST delivery */K/* ast_parameter = address of longword containing ACME specific value to */B/* pass to the ACME's AST service routine upon AST delivery */N/* */A#define acme$cb_acquire_acme_rmsast ACME$CB_ACQUIRE_ACME_RMSAST 2int acme$cb_acquire_acme_rmsast(__unknown_params);N/* */N/* Acquire WQE ASbT Context */N/* */I/* acme$cb_acquire_wqe_ast wqe, ast_handler, ast_context, */&/* ast_routine, ast_parameter */N/* */>/* wqe = address of ACM Work Queue Entry */E/* ast_handler = address of 64-bit pointer to receive AST handler */;/* (interceptor procedure) acddress */F/* ast_context = address of quadword to receive AST parameter value */H/* ast_routine = address of ACME's AST service routine to invoke upon */;/* AST delivery */K/* ast_parameter = address of quadword containing ACME specific value to */B/* pass to the ACME's AST service routine upon AST delivery */N/* */9#define acme$cb_acquire_wqe_ast ACME$CB_ dACQUIRE_WQE_AST .int acme$cb_acquire_wqe_ast(__unknown_params);N/* */N/* Acquire WQE RMS AST Context */N/* */I/* acme$cb_acquire_wqe_rmsast wqe, ast_handler, ast_context */&/* ast_routine, ast_parameter */N/* */>e/* wqe = address of ACM Work Queue Entry */E/* ast_handler = address of 64-bit pointer to receive AST handler */;/* (interceptor procedure) address */F/* ast_context = address of quadword to receive AST parameter value */H/* ast_routine = address of ACME's AST service routine to invoke upon */;/* AST delivery */K/* ast_parameter = address of longword containing ACME specific value to */B/* pass to the ACM fE's AST service routine upon AST delivery */N/* */?#define acme$cb_acquire_wqe_rmsast ACME$CB_ACQUIRE_WQE_RMSAST 1int acme$cb_acquire_wqe_rmsast(__unknown_params);N/* */N/* Allocate ACME VM */N/* */I/* acme$cb_allocat ge_acme_vm wqe, segment_size, segment_address */N/* */>/* wqe = address of ACM Work Queue Entry */F/* segment_size = number of bytes to allocated */I/* segment_address = address of first byte allocated */N/* */;#define acme$cb_allocate_acme_vm ACME$CB_ALLOCATE_ACME_VM /int acme$chb_allocate_acme_vm(__unknown_params);N/* */N/* Allocate WQE VM */N/* */I/* acme$cb_allocate_wqe_vm wqe, segment_size, segment_address */N/* */>/* wqe = address of ACM Work Queue Entry */F/* seg iment_size = number of bytes to allocated */I/* segment_address = address of first byte allocated */N/* */9#define acme$cb_allocate_wqe_vm ACME$CB_ALLOCATE_WQE_VM .int acme$cb_allocate_wqe_vm(__unknown_params);N/* */N/* Cancel Dialogue */N/* j */I/* acme$cb_cancel_dialogue wqe */N/* */>/* wqe = address of ACM Work Queue Entry */N/* */9#define acme$cb_cancel_dialogue ACME$CB_CANCEL_DIALOGUE .int acme$cb_cancel_dialogue(__unknown_params);N/* k */N/* Deallocate ACME VM */N/* */I/* acme$cb_deallocate_acme_vm wqe, segment_size, segment_address */N/* */>/* wqe = address of ACM Work Queue Entry */F/* segment_size = number of bytes to deallocate */Il/* segment_address = address of first byte to deallocate */N/* */?#define acme$cb_deallocate_acme_vm ACME$CB_DEALLOCATE_ACME_VM 1int acme$cb_deallocate_acme_vm(__unknown_params);N/* */N/* Deallocate WQE VM */N/* m */I/* acme$cb_deallocate_wqe_vm wqe, segment_size, segment_address */N/* */>/* wqe = address of ACM Work Queue Entry */F/* segment_size = number of bytes to deallocate */I/* segment_address = address of first byte to deallocate */N/* */=#define acme$cb_deallocate_wqe_vm ACME$CB_DE nALLOCATE_WQE_VM 0int acme$cb_deallocate_wqe_vm(__unknown_params);N/* */N/* Format Date and Time */N/* */I/* acme$cb_format_date_time wqe, dt_value, dt_string, dt_len, flags */N/* */>/* wqe = address of ACM Work Queue En otry */B/* dt_value = address of UTC date/time value */C/* dt_string = address of descriptor describing buffer to */;/* receive the formatted date/time string */A/* dt_len = address of word to receive the length (in bytes) */;/* of the formatted date/time string */@/* flags = formatting control flags */N/* */;#defpine acme$cb_format_date_time ACME$CB_FORMAT_DATE_TIME /int acme$cb_format_date_time(__unknown_params);N/* */N/* Issue Credentials */N/* */I/* acme$cb_issue_credentials wqe, type, credentials */N/* */ q>/* wqe = address of ACM Work Queue Entry */?/* type = type of security credentials */I/* credentials = address of descriptor describing security credentials */N/* */=#define acme$cb_issue_credentials ACME$CB_ISSUE_CREDENTIALS 0int acme$cb_issue_credentials(__unknown_params);N/* */N/* Convert a Latin1r string to a UCS string */N/* */I/* acme$cb_latin1_to_ucs wqe, latin1_string, ucs_string, ucs_bytes */N/* */>/* wqe = address of ACM Work Queue Entry */G/* latin1_string = address of descriptor for buffer */N/* holding the Latin-1 encoded string s */D/* ucs_string = address of descriptor for buffer */;/* to receive the UCS encoded string */C/* ucs_bytes = length of ucs string (in bytes) */N/* */5#define acme$cb_latin1_to_ucs ACME$CB_LATIN1_TO_UCS ,int acme$cb_latin1_to_ucs(__unknown_params);N/* */N/* Queue Dialogue t */N/* */I/* acme$cb_queue_dialogue wqe, flags, item_code, max_length, */-/* data_1, data_2 */N/* */>/* wqe = address of ACM Work Queue Entry */@/* flags = dialogue control flags */C/* item_code = item code to use to tag res uponse */D/* max_length = maximum length of response data */A/* data_1 = prompt/message text */A/* data_2 = prompt/response/message text */N/* */7#define acme$cb_queue_dialogue ACME$CB_QUEUE_DIALOGUE -int acme$cb_queue_dialogue(__unknown_params);N/* */N/*v Release ACME AST Context */N/* */I/* acme$cb_release_acme_ast wqe, ast_context */N/* */>/* wqe = address of ACM Work Queue Entry */E/* ast_context = AST parameter value */N/* w */;#define acme$cb_release_acme_ast ACME$CB_RELEASE_ACME_AST /int acme$cb_release_acme_ast(__unknown_params);N/* */N/* Release ACME RMS AST Context */N/* */I/* acme$cb_release_acme_rmsast wqe, ast_context */N/* x */>/* wqe = address of ACM Work Queue Entry */E/* ast_context = AST parameter value */N/* */A#define acme$cb_release_acme_rmsast ACME$CB_RELEASE_ACME_RMSAST 2int acme$cb_release_acme_rmsast(__unknown_params);N/* */N/* Release ACME Resource y */N/* */I/* acme$cb_release_resource wqe, resource_type, resource_value */N/* */>/* wqe = address of ACM Work Queue Entry */G/* resource_type = type of (ACME defined) resource to allocate */U/* resource_value = address of quadword to receive the value of resource allocated */N/* z */;#define acme$cb_release_resource ACME$CB_RELEASE_RESOURCE /int acme$cb_release_resource(__unknown_params);N/* */N/* Release WQE AST Context */N/* */I/* acme$cb_release_wqe_ast wqe, ast_context */N/* { */>/* wqe = address of ACM Work Queue Entry */E/* ast_context = AST parameter value */N/* */9#define acme$cb_release_wqe_ast ACME$CB_RELEASE_WQE_AST .int acme$cb_release_wqe_ast(__unknown_params);N/* */N/* Release WQE RMS AST Context | */N/* */I/* acme$cb_release_wqe_rmsast wqe, ast_context */N/* */>/* wqe = address of ACM Work Queue Entry */E/* ast_context = AST parameter value */N/* */?#defin}e acme$cb_release_wqe_rmsast ACME$CB_RELEASE_WQE_RMSAST 1int acme$cb_release_wqe_rmsast(__unknown_params);N/* */N/* Report ACME Activity */N/* */I/* acme$cb_report_activity wqe, activity */N/* ~ */>/* wqe = address of ACM Work Queue Entry */E/* activity = address of ACME activity (status information) string */N/* */9#define acme$cb_report_activity ACME$CB_REPORT_ACTIVITY .int acme$cb_report_activity(__unknown_params);N/* */N/* Report ACME Attributes */N/*  */I/* acme$cb_report_attributes wqe, ident, resource_req */N/* */>/* wqe = address of ACM Work Queue Entry */@/* ident = address of descriptor describing ident string */F/* resource_req = address of ACME resource requirements structure */N/* */=#define acme$cb_report_attributes ACME$CB_REPORT_ATTRIBUTES 0int acme$cb_report_attributes(__unknown_params);N/* */N/* Send to Log File */N/* */I/* acme$cb_send_logfile wqe, msgvec */N/*  */>/* wqe = address of ACM Work Queue Entry */A/* msgvec = address of $PUTMSG style message vector */A/* actrtn = address of action routine */A/* actprm = parameter to pass to action routine */N/* */3#define acme$cb_send_logfile ACME$CB_SEND_LOGFILE +int acme$cb_send_logfile(__unknown_params);N/*  */N/* Send to Operator */N/* */I/* acme$cb_send_operator wqe, msgtxt */N/* */>/* wqe = address of ACM Work Queue Entry */A/* msgtxt = address of descriptor describing message text */N/*  */5#define acme$cb_send_operator ACME$CB_SEND_OPERATOR ,int acme$cb_send_operator(__unknown_params);N/* */N/* Set Secondary (Proctected) Status */N/* */I/* acme$cb_set_2nd_status wqe, status_value */N/*  */>/* wqe = address of ACM Work Queue Entry */F/* status_value = specific status value/condition code */N/* */7#define acme$cb_set_2nd_status ACME$CB_SET_2ND_STATUS -int acme$cb_set_2nd_status(__unknown_params);N/* */N/* Set ACME Status  */N/* */I/* acme$cb_set_acme_status wqe, status_value */N/* */>/* wqe = address of ACM Work Queue Entry */F/* status_value = ACME specific status value/condition code */N/* */9#define acme$cb_set_a cme_status ACME$CB_SET_ACME_STATUS .int acme$cb_set_acme_status(__unknown_params);N/* */N/* Set Designated DOI (Accept Request) */N/* */I/* acme$cb_set_designated_doi wqe */N/* */>/* wqe = address of  ACM Work Queue Entry */N/* */?#define acme$cb_set_designated_doi ACME$CB_SET_DESIGNATED_DOI 1int acme$cb_set_designated_doi(__unknown_params);N/* */N/* Set Logon Flag */N/* */I/* acme$cb_set_logon _flag wqe, flag */N/* */>/* wqe = address of ACM Work Queue Entry */?/* flag = flag number to set */N/* */7#define acme$cb_set_logon_flag ACME$CB_SET_LOGON_FLAG -int acme$cb_set_logon_flag(__unknown_params);N/*  */N/* Set Non-Native (non-OpenVMS) Logon Statistics */N/* */I/* acme$cb_set_logon_stats_doi wqe, logon_data */N/* */>/* wqe = address of ACM Work Queue Entry */D/* logon_data = address of OpenVMS logon statistics buffer */N/*  */A#define acme$cb_set_logon_stats_doi ACME$CB_SET_LOGON_STATS_DOI 2int acme$cb_set_logon_stats_doi(__unknown_params);N/* */N/* Set Native (OpenVMS) Logon Statistics */N/* */I/* acme$cb_set_logon_stats_vms wqe, logon_data */N/*  */>/* wqe = address of ACM Work Queue Entry */D/* logon_data = address of OpenVMS logon statistics buffer */N/* */A#define acme$cb_set_logon_stats_vms ACME$CB_SET_LOGON_STATS_VMS 2int acme$cb_set_logon_stats_vms(__unknown_params);N/* */N/* Set Output Item  */N/* */I/* acme$cb_set_output_item wqe, entry, data */N/* */>/* wqe = address of ACM Work Queue Entry */@/* entry = address of the item list entry to set */?/* data = address of descriptor describing data for field */N/*  */9#define acme$cb_set_output_item ACME$CB_SET_OUTPUT_ITEM .int acme$cb_set_output_item(__unknown_params);N/* */N/* Set Phase Notification Event */N/* */I/* acme$cb_set_phase_event wqe, event_data */N/*  */>/* wqe = address of ACM Work Queue Entry */D/* event_data = prompt/message text */N/* */9#define acme$cb_set_phase_event ACME$CB_SET_PHASE_EVENT .int acme$cb_set_phase_event(__unknown_params);N/* */N/* Set WQE Flag  */N/* */I/* acme$cb_set_wqe_flag wqe, flag */N/* */>/* wqe = address of ACM Work Queue Entry */?/* flag = flag number to set */N/* */3#define acm e$cb_set_wqe_flag ACME$CB_SET_WQE_FLAG +int acme$cb_set_wqe_flag(__unknown_params);N/* */N/* Set WQE Parameter (Item) */N/* */I/* acme$cb_set_wqe_parameter wqe, id, data */N/* */>/* wqe = address of ACM Work Queue Entry */=/* id = id number of parameter (item) field to set */?/* data = address of descriptor describing data for field */N/* */=#define acme$cb_set_wqe_parameter ACME$CB_SET_WQE_PARAMETER 0int acme$cb_set_wqe_parameter(__unknown_params);N/* */N/* Convert a UCS string to a Latin1 string  */N/* */I/* acme$cb_ucs_to_latin1 wqe, ucs_string, latin1_string, latin1_bytes */N/* */>/* wqe = address of ACM Work Queue Entry */D/* ucs_string = address of descriptor for buffer */N/* holding the UCS encoded string */G/* latin1_string = address o f descriptor for buffer */;/* to receive the Latin-1 encoded string */F/* latin1_bytes = length of latin1 string (in bytes) */N/* */5#define acme$cb_ucs_to_latin1 ACME$CB_UCS_TO_LATIN1 ,int acme$cb_ucs_to_latin1(__unknown_params);N/* */N/* Set New Password Flags  */N/* */I/* acme$cb_set_new_pwd_flags wqe, flag */N/* */>/* wqe = address of ACM Work Queue Entry */?/* flag = flag number to set */N/* */=#define acme$cb_set_new_pwd_flags ACME$CB_SET_NEW_PWD_FLAGS 0int acme$cb_set_new_pwd_flags(__unknown_params); $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard &#endif /* __ACMEAGENT_CB_DEF_LOADED */ wwpZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:39 by OpenVMS SDL V3.7 */P/* Source: 29-AUG-2000 09:54:48 $1$DGA8345:[LIB_H.SRC]ACMEAGENT_CO_DEF.SDL;1 *//********************************************************************************************************* ***********************/,/*** MODULE $ACMEAGENT_CO_DEF IDENT X-1 ***/!#ifndef __ACMEAGENT_CO_DEF_LOADED##define __ACMEAGENT_CO_DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+  */N/* */N/* ACME Agent Callout Routines Prototypes */N/* */N/*- */N/* */I/* acme$ast_routine kcb_vector, acme_context, wqe, wqe_context, */4/* ast_context, ast_parameter */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */E/* ast_context = address of quadword containing the AST context id */;/* (parameter) returned to the agent when acquiring */;/* the AST context */H/* ast_parameter = addesss of quadword containing ACME specific value */?/* specified by the agent when acquiring the AST context */N/* */+#define acme$ast_routine ACME$AST_ROUTINE (void acme$ast_routine(__unknown_params);N/*  */I/* acme$ast_routine kcb_vector, acme_context, wqe, wqe_context, */4/* ast_context, rms_parameter */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context  */E/* ast_context = address of longword containing the AST context id */;/* (parameter) returned to the agent when acquiring */;/* the AST context */E/* rms_context = addesss of RMS structure associated with this AST */;/* (the ...$L_CTX field contains the AST parameter */@/* specified by the agent when acquiring the AST context) */N/* */1#define acme$rmsa st_routine ACME$RMSAST_ROUTINE +void acme$rmsast_routine(__unknown_params);N/* */N/* Agent Initialize */N/* */I/* acme$co_agent_initialize kcb_vector, acme_context, wqe */N/* */D/* kcb_vector = address of  ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */N/* */;#define acme$co_agent_initialize ACME$CO_AGENT_INITIALIZE /int acme$co_agent_initialize(__unknown_params);N/* */N/* Agent Shutdown  */N/* */I/* acme$co_agent_shutdown kcb_vector, acme_context, wqe */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */N/*  */7#define acme$co_agent_shutdown ACME$CO_AGENT_SHUTDOWN -int acme$co_agent_shutdown(__unknown_params);N/* */N/* Agent Standby */N/* */I/* acme$co_agent_standby kcb_vector, acme_context, wqe */N/*  */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */N/* */5#define acme$co_agent_standby ACME$CO_AGENT_STANDBY ,int acme$co_agent_standby(__unknown_params);N/*  */N/* Agent Startup */N/* */I/* acme$co_agent_startup kcb_vector, acme_context, wqe */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */D/* concurrency_factor = number indicating extent of parallelism */N/* */5#define acme$co_agent_startup ACME$CO_AGENT_STARTUP ,int acme$co_agent_startup(__unknown_params);N/* */N/* EVENT function */N/*  */I/* acme$co_event kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C /* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */%#define acme$co_event ACME$CO_EVENT $int acme$co_event(__unknown_params);N/* */N/* QUERY function */N/*  */I/* acme$co_query kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request  context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */%#define acme$co_query ACME$CO_QUERY $int acme$co_query(__unknown_params);N/* */O/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ACCEPT_PASSWORDS phase processing */N/*  */K/* acme$co_accept_passwords kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of ag ent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */;#define acme$co_accept_passwords ACME$CO_ACCEPT_PASSWORDS /int acme$co_accept_passwords(__unknown_params);N/* */O/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ACCEPT_PRINCIPAL phase processing */N/* */K/* acme$co_accept_principal kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entr y */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */;#define acme$co_accept_principal ACME$CO_ACCEPT_PRINCIPAL /int acme$co_accept_principal(__unknown_params);N/*  */O/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ANCILLARY_MECH_1 phase processing */N/* */K/* acme$co_ancillary_mech_1 kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context  */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */;#define acme$co_ancillary_mech_1 ACME$CO_ANCILLARY_MECH_1 /int acme$co_ancillary_mech_1(__unknown_params);N/*  */O/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ANCILLARY_MECH_2 phase processing */N/* */K/* acme$co_ancillary_mech_2 kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* a cme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */;#define acme$co_ancillary_mech_2 ACME$CO_ANCILLARY_MECH_2 /int acme$co_ancillary_mech_2(__unknown_params);N/* */O/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ANCILLARY_MECH_3 phase processing */N/* */K/* acme$co_ancillary_mech_3 kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */;#define acme$co_ancilla ry_mech_3 ACME$CO_ANCILLARY_MECH_3 /int acme$co_ancillary_mech_3(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ANNOUNCE phase processing */N/* */I/* acme$co_announce kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/*  */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/*  */+#define acme$co_announce ACME$CO_ANNOUNCE 'int acme$co_announce(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD AUTHENTICATE phase processing */N/* */I/* acme$co_authenticate kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/*  */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/*  */3#define acme$co_authenticate ACME$CO_AUTHENTICATE +int acme$co_authenticate(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD AUTHORIZE phase processing */N/* */I/* acme$co_authorize kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */-#define acme$co_authorize ACME$CO_AUTHORIZE (int acme$co_authorize(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD AUTOLOGON phase processing */N/* */I/* acme$co_autologon kcb_vector, acme_context, wqe, wqe_context , */4/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item _list = address of agent specific item list */N/* */-#define acme$co_autologon ACME$CO_AUTOLOGON (int acme$co_autologon(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD CREDENTIALS phase processing */N/* */I/* acme$co_credentials kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item  list */H/* acme_item_list = address of agent specific item list */N/* */1#define acme$co_credentials ACME$CO_CREDENTIALS *int acme$co_credentials(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD FINISH phase processing */N/*  */I/* acme$co_finish kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_ list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */'#define acme$co_finish ACME$CO_FINISH %int acme$co_finish(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD INITIALIZE phase processing */N/*  */I/* acme$co_initialize kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request con text */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* *//#define acme$co_initialize ACME$CO_INITIALIZE )int acme$co_initialize(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD MAP_PRINCIPAL phase processing */N/*  */I/* acme$co_map_principal kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context =  address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */5#define acme$co_map_principal ACME$CO_MAP_PRINCIPAL ,int acme$co_map_principal(__unknown_params);N/* */P/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD LOGON_INFORMATION phase processing */N/* */L/* acme$co_logon_information kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */=#define acme$co_logon_information ACME$CO_LOGON_INFORMATION 0int acme$co_logon_information(__unknown_params);N/*  */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD MESSAGES phase processing */N/* */I/* acme$co_messages kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific contex t */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */+#define acme$co_messages ACME$CO_MESSAGES 'int acme$co_messages(__unknown_params);N/*  */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD NEW_PASSWORD_1 phase processing */N/* */I/* acme$co_new_password_1 kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = addres s of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */7#define acme$co_new_password_1 ACME$CO_NEW_PASSWORD_1 -int acme$co_new_password_1(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD NEW_PASSWORD_2 phase processing */N/* */I/* acme$co_new_password_2 kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */7#define acme$co_new_password_2 ACME$CO_NEW_PASSWORD_ 2 -int acme$co_new_password_2(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD NOTICES phase processing */N/* */I/* acme$co_notices kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */)#def ine acme$co_notices ACME$CO_NOTICES &int acme$co_notices(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD PASSWORD_1 phase processing */N/* */I/* acme$co_password_1 kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/*  */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/*  *//#define acme$co_password_1 ACME$CO_PASSWORD_1 )int acme$co_password_1(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD PASSWORD_2 phase processing */N/* */I/* acme$co_password_2 kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/*  */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/*  *//#define acme$co_password_2 ACME$CO_PASSWORD_2 )int acme$co_password_2(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD PRINCIPAL_NAME phase processing */N/* */I/* acme$co_principal_name kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list  */N/* */7#define acme$co_principal_name ACME$CO_PRINCIPAL_NAME -int acme$co_principal_name(__unknown_params);N/* */Q/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD QUALIFY_PASSWORD_1 phase processing */N/* */M/* acme$co_qualify_password_1 kcb_vector, acme_context, w qe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */?#define acme$co_qualify_password_1 ACME$CO_QUALIFY_PASSWORD_1 1int acme$co_qualify_password_1(__unknown_params);N/* */Q/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD QUALIFY_PASSWORD_2 phase processing */N/*  */M/* acme$co_qualify_password_2 kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list =  address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */?#define acme$co_qualify_password_2 ACME$CO_QUALIFY_PASSWORD_2 1int acme$co_qualify_password_2(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD SET_PASSWORDS phase processing */N/*  */I/* acme$co_set_passwords kcb_vector, acme_context, wqe, wqe_context, */4/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address  of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */5#define acme$co_set_passwords ACME$CO_SET_PASSWORDS ,int acme$co_set_passwords(__unknown_params);N/* */N/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD SYSTEM_PASSWORD phase processing */N/* */J/* acme$co_system_password kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */>/* wqe = address of ACM Work Queue Entry  */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */9#define acme$co_system_password ACME$CO_SYSTEM_PASSWORD .int acme$co_system_password(__unknown_params);N/* */O/* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD VALIDATE_MAPPING phase processing */N/* */K/* acme$co_validate_mapping kcb_vector, acme_context, wqe, wqe_context, */-/* item_list, acme_item_list */N/* */D/* kcb_vector = address of ACM Kernel Callback Vector */F/* acme_context = address of agent specific context */ >/* wqe = address of ACM Work Queue Entry */E/* wqe_context = address of agent specific request context */C/* item_list = address of agent independent item list */H/* acme_item_list = address of agent specific item list */N/* */;#define acme$co_validate_mapping ACME$CO_VALIDATE_MAPPING /int acme$co_validate_mapping(__unknown_params); $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard &#endif /* __ACMEAGENT_CO_DEF_LOADED */ ww\ZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:38 by OpenVMS SDL V3.7 */R/* Source: 11-FEB-2004 12:48:29 $1$DGA8345:[LIB_H.SRC]ACMEAGENT_DATA_DEF.SDL;1 *//********************************************************************************************************************************/./*** MODULE $ACMEAGENT_DATA_DEF IDENT X-1 ***/##ifndef __ACMEAGENT_DATA_DEF_L OADED%#define __ACMEAGENT_DATA_DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/*  */N/* Miscellaneous constants */N/* */N/*- */O#define ACME$K_MAXCHAR_ACME_IDENT 64 /* Maximum length (in characters) of */N/* ACME ident */O#define ACME$K_MAXCHAR_ACME_ACTIVITY 64 /* Maximum length (in characters) of */N/* ACME activity (status) information */N/*+ */N/* */N/* ACMEWQE - ACM Work Queue Entry. */N/* */N/*-  */ !#pragma __member_alignment __save#pragma __nomember_alignment$#define ACMEWQEFLG$K_MIN_ACME_FLAG 0&#define ACMEWQEFLG$M_ACME_FLAGS 0xFFFF%#define ACMEWQEFLG$K_MAX_ACME_FLAG 150#define ACMEWQEFLG$M_DISPATCHER_FLAGS 0xFFFF0000.#define ACMEWQEFLG$M_DIALOGUE_POSSIBLE 0x10000)#define ACMEWQEFLG$M_AST_RECEIVED 0x20000/#define ACMEWQEFLG$M_REPORT_PHASE_EVENT 0x40000(#define ACMEWQEFLG$M_MASK_STATUS 0x80000+#define ACMEWQEFLG$M_TRACE_ENABLED 0x100000-#define ACMEWQEFLG$M_ABORT_REQUEST 0x40000000.#define ACMEWQEFLG$M_FAILED_REQUEST 0x80000000"#define ACMEWQEFLG$K_MIN_FI_FLAG 0!#define ACMEWQEFLG$K_PHASE_DONE 0##define ACMEWQEFLG$M_PHASE_DONE 0x1#define ACMEWQEFLG$K_NO_RETRY 1!#define ACMEWQEFLG$M_NO_RETRY 0x2"#define ACMEWQEFLG$K_MAX_FI_FLAG 1%#define ACMEWQEFLG$K_MIN_AUTH_FLAG 12(#define ACMEWQEFLG$K_PREAUTHENTICATED 12,#define ACMEWQEFLG$M_PREAUTHENTICATED 0x1000(#define ACMEWQEFLG$K_NO_EXTERNAL_AUTH 13,#define ACMEWQEFLG$M_NO_EXTERNAL_AUTH 0x2000)#define AC MEWQEFLG$K_SKIP_NEW_PASSWORD 14-#define ACMEWQEFLG$M_SKIP_NEW_PASSWORD 0x4000%#define ACMEWQEFLG$K_NULL_NET_USER 15)#define ACMEWQEFLG$M_NULL_NET_USER 0x8000%#define ACMEWQEFLG$K_MAX_AUTH_FLAG 15 typedef struct _acmewqeflg { __union {N/* */N/* Overall flags structure */N/* */ __ union {N unsigned int acmewqeflg$l_flags_struct; /* Composite field */ __struct {N/* */N/* Bits [15:0] = ACME settable */B/* Function independent flags are assigned upward. */B/* Function dependent flags are assigned downward. */N/* */6  unsigned acmewqeflg$v_acme_flags : 16;N/* */N/* Bits [31:16] = ACM Dispatcher controlled */N/* */< unsigned acmewqeflg$v_dispatcher_flags : 16;' } acmewqeflg$r_fill_1_;# } acmewqeflg$r_fill_0_;N/* */N/*  ACM Dispatcher controlled flags */N/* */ __union {1 unsigned int acmewqeflg$l_dispatcher; __struct {< unsigned acmewqeflg$v_disp_flgs_fill_1 : 16;T unsigned acmewqeflg$v_dialogue_possible : 1; /* Dialogue possible */N unsigned acmewqeflg$v_ast_received : 1; /* AST recieved */[ unsigned acmewqeflg$v_report_phase_event : 1; /* Phase transition event */N/* processing has already been */N/* requested for this WQE. */` unsigned acmewqeflg$v_mask_status : 1; /* Indicates $ACM[W] service will mask */N/* the reporting of privileged status */X unsigned acmewqeflg$v_trace_enabled : 1; /* Server tracing is enabled */;  unsigned acmewqeflg$v_disp_flgs_fill_2 : 9;N unsigned acmewqeflg$v_abort_request : 1; /* Abort request */e unsigned acmewqeflg$v_failed_request : 1; /* An ACME returned a non-success status */N/* (failed request processing should occur) */' } acmewqeflg$r_fill_3_;# } acmewqeflg$r_fill_2_;N/* */N/* ACME setable, function independent flags */N/* */ __union {7 unsigned int acmewqeflg$l_func_independent; __struct {N unsigned acmewqeflg$v_phase_done : 1; /* Phase completed */N unsigned acmewqeflg$v_no_retry : 1; /* Retry not possible */? unsigned acmewqeflg$v_acme_fi_flgs_fill_1 : 16;2 unsigned acmewqeflg$v_fill _8_ : 6;' } acmewqeflg$r_fill_5_;# } acmewqeflg$r_fill_4_;N/* */N/* Flags applicable to AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD */N/* */ __union {1 unsigned int acmewqeflg$l_auth_flags; __struct {; unsigned acmewqeflg$v_auth_flgs_fill_1 : 2;< unsigned acmewqeflg$v_auth_flgs_fill_2 : 10;S unsigned acmewqeflg$v_preauthenticated : 1; /* Pre-authenticated */W unsigned acmewqeflg$v_no_external_auth : 1; /* Authenticate natively */_ unsigned acmewqeflg$v_skip_new_password : 1; /* Skip new password processing */Z unsigned acmewqeflg$v_null_net_user : 1; /* Special no-username request */< unsigned acmewqeflg$v_auth_flgs_fill_3 : 16;' } acmewqeflg$r_f ill_7_;# } acmewqeflg$r_fill_6_; } acmewqeflg$r_overlay; } ACMEWQEFLG; #if !defined(__VAXC)e#define acmewqeflg$l_flags_struct acmewqeflg$r_overlay.acmewqeflg$r_fill_0_.acmewqeflg$l_flags_structv#define acmewqeflg$v_acme_flags acmewqeflg$r_overlay.acmewqeflg$r_fill_0_.acmewqeflg$r_fill_1_.acmewqeflg$v_acme_flags#define acmewqeflg$v_dispatcher_flags acmewqeflg$r_overlay.acmewqeflg$r_fill_0_.acmewqeflg$r_fill_1_.acmewqeflg$v_dispatcher_flags#define acmewqeflg$v_dialogue_possible acmewqeflg$r_overlay.acmewqeflg$r_fill_2_.acmewqeflg$r_fill_3_.acmewqeflg$v_dialogue_possiblez#define acmewqeflg$v_ast_received acmewqeflg$r_overlay.acmewqeflg$r_fill_2_.acmewqeflg$r_fill_3_.acmewqeflg$v_ast_received#define acmewqeflg$v_report_phase_event acmewqeflg$r_overlay.acmewqeflg$r_fill_2_.acmewqeflg$r_fill_3_.acmewqeflg$v_report_phase_ev\entx#define acmewqeflg$v_mask_status acmewqeflg$r_overlay.acmewqeflg$r_fill_2_.acmewqeflg$r_fill_3_.acmewqeflg$v_mask_status|#define acmewqeflg$v_trace_enabled acmewqeflg$r_overlay.acmewqeflg$r_fill_2_.acmewqeflg$r_fill_3_.acmewqeflg$v_trace_enabled|#define acmewqeflg$v_abort_request acmewqeflg$r_overlay.acmewqeflg$r_fill_2_.acmewqeflg$r_fill_3_.acmewqeflg$v_abort_request~#define acmewqeflg$v_failed_request acmewqeflg$r_overlay.acmewqeflg$r_fill_2_.acmewqeflg$r_fill_3_.acmewqeflg$v_failed_requestv#define acmewqeflg$v_phase_done acmewqeflg$r_overlay.acmewqeflg$r_fill_4_.acmewqeflg$r_fill_5_.acmewqeflg$v_phase_doner#define acmewqeflg$v_no_retry acmewqeflg$r_overlay.acmewqeflg$r_fill_4_.acmewqeflg$r_fill_5_.acmewqeflg$v_no_retry#define acmewqeflg$v_preauthenticated acmewqeflg$r_overlay.acmewqeflg$r_fill_6_.acmewqeflg$r_fill_7_.acmewqeflg$v_preauthenticated#define acmewqeflg$v_no_external_auth acmewqeflg$r_overlay.acmewqeflg$r_fill_6_.acmewqeflg$r_fill_7_.acmewqeflg$v_no_external_auth#define acmewqeflg$v_skip_new_password acmewqeflg$r_overlay.acmewqeflg$r_fill_6_.acmewqeflg$r_fill_7_.acmewqeflg$v_skip_new_password|#defin e acmewqeflg$v_null_net_user acmewqeflg$r_overlay.acmewqeflg$r_fill_6_.acmewqeflg$r_fill_7_.acmewqeflg$v_null_net_user"#endif /* #if !defined(__VAXC) */ #define ACMEWQEFLG$K_LENGTH 4 $#pragma __member_alignment __restore  #pragma __member_alignmenttypedef struct _acmewqeval {N ACMEID acmewqeval$l_acme_id; /* ID of ACME which set the value */N unsigned int acmewqeval$l_phase; /* Phase during which value was set */N unsigned int acmewqeval$l_value; /* Val ue */ } ACMEWQEVAL;#define ACMEWQEVAL$K_LENGTH 12 typedef struct _acmewqeitm {N ACMEID acmewqeitm$l_acme_id; /* ID of ACME which set the item */N unsigned int acmewqeitm$l_phase; /* Phase during which item was set */N unsigned int acmewqeitm$l_length; /* Size, in bytes, of data */N void *acmewqeitm$ps_pointer; /* Address of data */ } ACMEWQEITM;#define ACMEWQEITM$K_LENGTH 16N/*  */N/* Function independent WQE extension */N/* */N/* Note: */N/* */I/* The function independent WQE extension contains no fields */I/* at present, the structure declaration is specified simply */I/* to declare the applicable datatype. */N/* */#define ACMEWQEFIX$K_LENGTH 0 typedef struct _acmewqefix { __union {N unsigned int acmewqefix$l_reserved []; /* Null structure */ } acmewqefix$r_overlay; } ACMEWQEFIX; #if !defined(__VAXC)"#endif /* #if !defined(__VAXC) */ N/*  */N/* WQE extension applicable to AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD */N/* */$#define ACMEWQE$K_MIN_AUTH_PARAM 256%#define ACMEWQE$K_SYSTEM_PASSWORD 256$#define ACMEWQE$K_PRINCIPAL_NAME 257(#define ACMEWQE$K_PRINCIPAL_NAME_OUT 258"#define ACMEWQE$K_VMS_USERNAME 259 #define ACMEWQE$K_PASSWORD_1 260 #define ACMEWQE$K_PASSWORD_2 261$#define ACMEWQE$K_NEW_PASSWORD_1 262$#d efine ACMEWQE$K_NEW_PASSWORD_2 263$#define ACMEWQE$K_MAX_AUTH_PARAM 263 typedef struct _acmewqeax {R ACMEPWDFLG acmewqeax$l_new_password_flags; /* Password change request flags */N ACMELGIFLG acmewqeax$l_logon_flags; /* Logon flags */R ACMELIVMS acmewqeax$r_logon_stats_vms; /* Native (OpenVMS) logon statistics */Z ACMELIDOI acmewqeax$r_logon_stats_doi; /* Non-native (non-OpenVMS) logon statistics */N ACMEWQEITM acmewqeax$r_system_password; /* System password */Q ACMEWQEITM acmewqeax$r_principal_name; /* Raw (unprocessed) principal name */N ACMEWQEITM acmewqeax$r_principal_name_out; /* Principal name */N ACMEWQEITM acmewqeax$r_vms_username; /* Mapped OpenVMS username */N ACMEWQEITM acmewqeax$r_password_1; /* Password 1 */N ACMEWQEITM acmewqeax$r_password_2; /* Password 2 */N ACMEWQEITM acmewqeax$r_new_password_1; /* New password 1 */N  ACMEWQEITM acmewqeax$r_new_password_2; /* New password 2 */ } ACMEWQEAX;#define ACMEWQEAX$K_LENGTH 296N/* */N/* WQE extension applicable to Agent Initialization */N/* */  9#ifdef __cplusplus /* Define structure prototypes */struct _descriptor; #endif /* #ifdef __cplusplus */ typedef struct _acmewqeaix {T struct _descriptor *acmewqeaix$ps_agent_name; /* address of string descriptor */ } ACMEWQEAIX;#define ACMEWQEAIX$K_LENGTH 4N/* */N/* WQE extension applicable to Agent startup (Enabling) */N/* */ #pragma __member_alignmenttypedef struct _acmewqeaex {N unsigned int acmewqeaex$l_concurrent_req  uests; /* maximum at a time */ } ACMEWQEAEX;#define ACMEWQEAEX$K_LENGTH 4N/* */N/* WQE extension applicable to Agent shutdown (Disabling) */N/* */ typedef struct _acmewqeadx {N unsigned int acmewqeadx$l_reserved []; /* Null structure */ } ACMEWQEADX;#define ACMEWQEADX$K_LENGTH 4N/*  */N/* WQE extension applicable to Agent Standby */N/* */ typedef struct _acmewqeasx {N unsigned int acmewqeasx$l_reserved []; /* Null structure */ } ACMEWQEASX;#define ACMEWQEASX$K_LENGTH 4N/* */N/* Function dependent WQE extens ion */N/* */ typedef struct _acmewqefdx { __union {U ACMEWQEAX acmewqefdx$r_auth_pwd; /* AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD */ } acmewqefdx$r_overlay; } ACMEWQEFDX; #if !defined(__VAXC)H#define acmewqefdx$r_auth_pwd acmewqefdx$r_overlay.acmewqefdx$r_auth_pwd"#endif /* #if !defined(__VAXC) */ #define ACMEWQEFDX$K_LENGTH 296 U#define  ACMEWQE$K_MINOR_ID_000 0 /* original V7.2-1 WQE supporting only COM */N#define ACMEWQE$K_MINOR_ID_001 1 /* subsequent extension of the WQE */#define ACMEWQE$K_MINOR_ID 0 #define ACMEWQE$K_MAJOR_ID_001 1#define ACMEWQE$K_MAJOR_ID 1#define ACMEWQE$K_REVISION 256 typedef struct _acmewqe {N struct _acmewqe *acmewqe$ps_flink; /* WQE list forward link */#pragma __member_alignmentN struct _acmewqe *acmewqe$ps_blink; /* WQE list backward link */N /* */N/* ACME visible fields */N/* */#pragma __member_alignmentN unsigned short int acmewqe$w_size; /* Structure size, in bytes */N ACMEREVLVL acmewqe$w_revision_level; /* Structure revision level */N/* */ N/* WQE Data Structure minor versions */N/* */N ACMEWQEFLG acmewqe$l_flags; /* Status/control flags */N ACMEFC acmewqe$l_function; /* Function code/modifiers */N ACMEDLOGFLG acmewqe$l_dialogue_flags; /* Dialogue support flags */P unsigned int acmewqe$l_requestor_profile; /* Requestor's security profile */N/* (Persona ID)  */N unsigned int acmewqe$l_requestor_mode; /* Requestor's mode */N unsigned int acmewqe$l_requestor_pid; /* Requestor's PID */N ACMEID acmewqe$l_target_acme_id; /* Agent id of ACME at which */N/* this request is directed */N ACMEID acmewqe$l_designated_acme_id; /* Agent id of ACME that */N/* assumed processing control  */P unsigned int acmewqe$l_designated_cred; /* Type of credentials associated */N/* with the designated ACME */N ACMEID acmewqe$l_current_acme_id; /* Agent id of current ACME */Z ACMEWQEVAL acmewqe$r_status; /* First non-success status returned by an ACME */N ACMEWQEVAL acmewqe$r_secondary_status; /* Secondary (protected) status */N ACMEWQEVAL acmewqe$r_acme_status; /* ACME specific sta tus */X struct _acmewqefix *acmewqe$ps_func_ind_params; /* Function independent extension */#pragma __member_alignmentV struct _acmewqefdx *acmewqe$ps_func_dep_params; /* Function dependent extension */#pragma __member_alignmentN struct _ile3 *acmewqe$ps_itemlist; /* ACME independent item list */#pragma __member_alignmentN struct _ile3 *acmewqe$ps_acme_itemlist; /* ACME specific item list */#pragma __member_alignmentN unsigned __int64 acmewqe$q_ast_c ontext; /* AST context for which the */N/* AST has been recieved */N ACMEWQEITM acmewqe$r_locale; /* Locale specifier */N ACMEWQEITM acmewqe$r_service_name; /* Service (client) specifier */N unsigned int acmewqe$l_timeout_seconds; /* seconds since system boot */N/* at which this request can */N/* be timed out. */ char acmewqe$b_fill_9_ [4]; } ACMEWQE;N#define ACMEWQE$K_LENGTH 152 /* Length of fixed portion */  N/*+ */N/* */N/* ACMEOUTITM - Item list output item data buffer */N/* */N/*- */N#define ACMEOUTITM$K_LENGTH 16 /* Length of fixed portion */ typedef struct _acmeoutitm {Q ACMEID acmeoutitm$l_acme_id; /* ID of ACME which set the item entry */N unsigned int acmeoutitm$l_phase; /* Phase during which item was set */N unsigned short int acmeoutitm$w_size; /* Structure size, in bytes */+ unsigned short int acmeoutitm$w_rsvd_1;P unsigned short int acmeoutitm$w_length; /* Actua l size, in bytes, of data */T unsigned short int acmeoutitm$w_max_length; /* Size, in bytes, of data buffer */N unsigned char acmeoutitm$b_data []; /* Data */# char acmeoutitm$b_fill_11_ [3]; } ACMEOUTITM;N/*+ */N/* */N/* ACMERSRC - ACME Agent Resource Requirements Block */N/*  */N/*- */ Ntypedef struct _acmepq { /* Process quota requirements */N unsigned int acmepq$l_memory; /* Virtual address space use */N unsigned int acmepq$l_channel; /* I/O channels */N unsigned int acmepq$l_direct_io; /* Direct I/O count */N unsigned int acmepq$l_buffer_i  o; /* Buffered I/O count */N unsigned int acmepq$l_buffer_io_mem; /* Buffered I/O memory usage */N unsigned int acmepq$l_ast; /* AST count */N unsigned int acmepq$l_tqe; /* TQE count */N unsigned int acmepq$l_lock; /* Lock count */ } ACMEPQ;!#define ACMERSRC$K_MINOR_ID_000 0#define ACMERSRC$K_MINOR_ID 0N#define ACMERSRC$K_MAJOR_ID_001 1 /* VMS V7.2-1  */#define ACMERSRC$K_MAJOR_ID 1#define ACMERSRC$K_REVISION 256 typedef struct _acmersrc {N/* */N/* General resource requirements */N/* */N unsigned __int64 acmersrc$q_privileges; /* Operating privilege */N unsigned short int acmersrc$w_size; /* Structure size, in by tes */N ACMEREVLVL acmersrc$w_revision_level; /* Structure revision level */N unsigned int acmersrc$l_stack_size; /* Maximum operating stack */N ACMEPQ acmersrc$r_agent_quotas; /* General process quotas */N/* */N/* Per-request resource requirements */N/* */N ACMEPQ  acmersrc$r_request_quotas; /* Per-request process quotas */ } ACMERSRC;#define ACMERSRC$K_LENGTH 80 N/*+ */N/* */P/* ACMEDTFLG - Formatting control flags for ACME$CB_FORMAT_DATE_TIME callback */N/* */N/*-  */ !#pragma __member_alignment __save#pragma __nomember_alignment##define ACMEDTFLG$M_TIME_FIELDS 0x1##define ACMEDTFLG$M_DATE_FIELDS 0x2$#define ACMEDTFLG$M_LOCAL 0x40000000"#define ACMEDTFLG$M_UCS 0x80000000 typedef struct _acmedtflg { __union {N unsigned int acmedtflg$l_control_flags; /* Composite field */ __struct {N unsigned acmedtflg$v_time_fields : 1; /* Include time fields */N unsigned acmedtflg$v_dat  e_fields : 1; /* Include date fields */4 unsigned acmedtflg$v_dt_flg_fill_1 : 28;R unsigned acmedtflg$v_local : 1; /* Use default locale for the local */N/* system in lieu of WQE locale */N unsigned acmedtflg$v_ucs : 1; /* Convert to UCS-4 encoding */# } acmedtflg$r_fill_13_; } acmedtflg$r_fill_12_; } ACMEDTFLG; #if !defined(__VAXC)P#define acmedtflg$l_control_flags acmedtflg$r_fi  ll_12_.acmedtflg$l_control_flagsa#define acmedtflg$v_time_fields acmedtflg$r_fill_12_.acmedtflg$r_fill_13_.acmedtflg$v_time_fieldsa#define acmedtflg$v_date_fields acmedtflg$r_fill_12_.acmedtflg$r_fill_13_.acmedtflg$v_date_fieldsU#define acmedtflg$v_local acmedtflg$r_fill_12_.acmedtflg$r_fill_13_.acmedtflg$v_localQ#define acmedtflg$v_ucs acmedtflg$r_fill_12_.acmedtflg$r_fill_13_.acmedtflg$v_ucs"#endif /* #if !defined(__VAXC) */ #define ACMEDTFLG$K_LENGTH 4 $#pragma __member_alignment  __restore N/*+ */N/* */N/* ACMEKCV - ACM Kernel Callback Vector */N/* */N/*- */#define ACME$K_MINOR_ID_000 0#define ACME$K_MINOR_ID_001 0N#define ACME$K_MINOR_ID 0  /* The default is still 000 */#define ACME$K_MAJOR_ID_001 1#define ACME$K_MAJOR_ID 1#define ACME$K_REVISION 256N#define ACMEKCV$K_MINOR_ID_000 0 /* original V7.2-1 callback list */P#define ACMEKCV$K_MINOR_ID_001 1 /* supporting Latin1<->UCS conversion */#define ACMEKCV$K_MINOR_ID 1 #define ACMEKCV$K_MAJOR_ID_001 1#define ACMEKCV$K_MAJOR_ID 1#define ACMEKCV$K_REVISION 257"#define ACME$K_REPORT_ATTRIBUTES 0#define ACME$K_SEND_OPERATOR 1#defin e ACME$K_SEND_LOGFILE 2!#define ACME$K_ALLOCATE_ACME_VM 3##define ACME$K_DEALLOCATE_ACME_VM 4 #define ACME$K_ALLOCATE_WQE_VM 5"#define ACME$K_DEALLOCATE_WQE_VM 6##define ACME$K_SET_DESIGNATED_DOI 7#define ACME$K_SET_2ND_STATUS 8 #define ACME$K_SET_ACME_STATUS 9#define ACME$K_SET_WQE_FLAG 10##define ACME$K_SET_WQE_PARAMETER 11!#define ACME$K_SET_OUTPUT_ITEM 12 #define ACME$K_SET_LOGON_FLAG 13%#define ACME$K_SET_LOGON_STATS_VMS 14%#define ACME$K_SET_LOGON_STATS_DOI 15!#define AC ME$K_SET_PHASE_EVENT 16 #define ACME$K_QUEUE_DIALOGUE 17!#define ACME$K_CANCEL_DIALOGUE 18"#define ACME$K_ACQUIRE_ACME_AST 19"#define ACME$K_RELEASE_ACME_AST 20!#define ACME$K_ACQUIRE_WQE_AST 21!#define ACME$K_RELEASE_WQE_AST 22%#define ACME$K_ACQUIRE_ACME_RMSAST 23%#define ACME$K_RELEASE_ACME_RMSAST 24$#define ACME$K_ACQUIRE_WQE_RMSAST 25$#define ACME$K_RELEASE_WQE_RMSAST 26"#define ACME$K_ACQUIRE_RESOURCE 27"#define ACME$K_RELEASE_RESOURCE 28##define ACME$K_ISSUE_CREDENTIALS 29"  #define ACME$K_FORMAT_DATE_TIME 30!#define ACME$K_REPORT_ACTIVITY 31#define ACME$K_UCS_TO_LATIN1 32#define ACME$K_LATIN1_TO_UCS 33##define ACME$K_SET_NEW_PWD_FLAGS 34#define ACME$K_KCV_COUNT 35 typedef struct _acmekcv {N ACMEREVLVL acmekcv$w_acm_revision_level; /* ACM kernel revision level */N ACMEREVLVL acmekcv$w_revision_level; /* Structure revision level */N int (*acmekcv$cb_report_attributes)(); /* Report resource requirements */#pragma __member_alignment  N int (*acmekcv$cb_send_operator)(); /* Send a message to the operator */#pragma __member_alignmentN int (*acmekcv$cb_send_logfile)(); /* Write a message in the log file */#pragma __member_alignmentN int (*acmekcv$cb_allocate_acme_vm)(); /* Allocate a block of memory */#pragma __member_alignmentN int (*acmekcv$cb_deallocate_acme_vm)(); /* Deallocate a block of memory */#pragma __member_alignmentN int (*acmekcv$cb_allocate_wqe_vm)(); /* Allocate a block of memory  */#pragma __member_alignmentN int (*acmekcv$cb_deallocate_wqe_vm)(); /* Deallocate a block of memory */#pragma __member_alignmentO int (*acmekcv$cb_set_designated_doi)(); /* Declare DOI accepting request */#pragma __member_alignmentQ int (*acmekcv$cb_set_2nd_status)(); /* Report secondary (protected) status */#pragma __member_alignmentN int (*acmekcv$cb_set_acme_status)(); /* Report ACME specific status */#pragma __member_alignmentN int (*acmekcv$cb_set_wqe_fla  g)(); /* Set WQE status/control flag */#pragma __member_alignmentN int (*acmekcv$cb_set_wqe_parameter)(); /* Set WQE data item */#pragma __member_alignmentN int (*acmekcv$cb_set_output_item)(); /* Set output item */#pragma __member_alignmentN int (*acmekcv$cb_set_logon_flag)(); /* Set logon status flag */#pragma __member_alignment[ int (*acmekcv$cb_set_logon_stats_vms)(); /* Report native (OpenVMS) logon statistics */#pragma __me  mber_alignmentc int (*acmekcv$cb_set_logon_stats_doi)(); /* Reprot non-native (non-OpenVMS) logon statistics */#pragma __member_alignmentP int (*acmekcv$cb_set_phase_event)(); /* Set phase transition notification */#pragma __member_alignmentN int (*acmekcv$cb_queue_dialogue)(); /* Queue a dialogue item set */#pragma __member_alignmentN int (*acmekcv$cb_cancel_dialogue)(); /* Dismiss pending dialogue */#pragma __member_alignmentO int (*acmekcv$cb_acquire_acme_  ast)(); /* Establish a non-RMS AST context */#pragma __member_alignmentN int (*acmekcv$cb_release_acme_ast)(); /* Dismiss non-RMS AST context */#pragma __member_alignmentN int (*acmekcv$cb_acquire_wqe_ast)(); /* Establish a non-RMS AST context */#pragma __member_alignmentN int (*acmekcv$cb_release_wqe_ast)(); /* Dismiss non-RMS AST context */#pragma __member_alignmentO int (*acmekcv$cb_acquire_acme_rmsast)(); /* Establish an RMS AST context */#pragma __member_alignme ntN int (*acmekcv$cb_release_acme_rmsast)(); /* Dismiss RMS AST context */#pragma __member_alignmentN int (*acmekcv$cb_acquire_wqe_rmsast)(); /* Establish an RMS AST context */#pragma __member_alignmentN int (*acmekcv$cb_release_wqe_rmsast)(); /* Dismiss RMS AST context */#pragma __member_alignmentQ int (*acmekcv$cb_acquire_resource)(); /* Acquire an ACME specific resource */#pragma __member_alignmentQ int (*acmekcv$cb_release_resource)(); /* Release an ACME speci ! fic resource */#pragma __member_alignmentN int (*acmekcv$cb_issue_credentials)(); /* Issue security credentials */#pragma __member_alignmentN int (*acmekcv$cb_format_date_time)(); /* Format date and time */#pragma __member_alignmentN int (*acmekcv$cb_report_activity)(); /* Report resource requirements */N/* */N/* The following cells are only meaningful if ACMEKCV$W_REVISION_LEVEL */N/* c " ontains ACMEKCV$K_MAJOR_ID_001/ACMEKCV$K_MINOR_ID_001 or higher. */N/* */#pragma __member_alignmentN int (*acmekcv$cb_ucs_to_latin1)(); /* Convert UCS2_4 to Latin1 */#pragma __member_alignmentN int (*acmekcv$cb_latin1_to_ucs)(); /* Convert Latin1 to UCS2_4 */#pragma __member_alignmentN int (*acmekcv$cb_set_new_pwd_flags)(); /* Set new password flag */ } ACMEKCV;#define AC# MEKCV$K_LENGTH 144  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard (#endif /* __ACMEAGENT_DATA_DEF_LOADED */ wwZUM/***************************************************************************/M/** $ **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** % **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********& ******************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JUL-2003 07:53:09 $1$DGA8345:[LIB_H.SRC]ADBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ADBDEF ***/#ifndef __ ' ADBDEF_LOADED#define __ADBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C"( {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pra ) gma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _adb {N/* Defined in the form of a standard structure header */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void (*adb$q_ast_proc)(); /*AST ROUTINE ADDRESS */#else! unsigned __int64 adb$q_ * ast_proc;#endif" unsigned short int adb$w_size;$ unsigned char adb$b_struct_type;' unsigned char adb$b_struct_subtype; __union { int adb$l_flags; } adb$r_flags_union; __int64 adb$q_ast_parm;f __int64 adb$q_saved_ip; /* For the 0.0001% of ASTs that care about the undocumented */` __int64 adb$q_saved_ps; /* Alpha "Saved PC/Saved PS", we have to build these. */a unsigned int adb$l_ast_target_pid; /* Where an AST was queued + -- we may have delivered it */N/* elsewhere because of IMSEM ownership */N unsigned int adb$l_ast_spare_long; /* Currently unused */_ __int64 adb$q_tie_ast_proc; /* Target AST address if AST to be delivered via TIE */[ unsigned __int64 adb$q_ast_spare_quad; /* Unused, round out size to an even 40 bytes */ } ADB; #if !defined(__VAXC)1#define adb$l_flags adb$r_flags_union.adb$l_flags"#endif /* #if !defined(__VAXC, ) */ #define ADB$K_LENGTH 64 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ADBDEF_LOADED */ ww ZUM/***************************************************************************/M/** - **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** . **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********/ ******************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:29 by OpenVMS SDL V3.7 */F/* Source: 18-APR-2017 14:56:23 $1$DGA8345:[LIB_H.SRC]ADPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ADPDEF ***/#ifndef __ 0 ADPDEF_LOADED#define __ADPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C"1 {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* ADAPTER CONTROL BLOCK DEFIN2 ITIONS */N/* */N/* There is one ADP for each adapter on the system, where an adapter */N/* is defined as an interconnect between two busses or a multichannel */N/* device. ADPs are now arranged in a hierarchical structure reflecting */N/* the physical topology of the system and I/O buses. A special system ADP */N/* is placed at the root of the tree to represent a "vir3 tual adapter" */N/* to the system bus. ADPs now contain a pointer to an array of */N/* information for each node on the remote bus to which the adapter */N/* connects. For example, the ADP for an XMI to BI adapter points to */N/* a 16-entry array for the 16 node BI bus. Each array entry contains */N/* several items including a hardware ID field, the base address of */N/* the node's CSR space, pointer(s) to data structure(s), a node */N/*4 number, and a bus-specific field. */N/* */Q/* The ADP sometimes contains a pointer to a bus command table, which contains */O/* bit patterns representing commands on the target bus. These bit patterns */N/* are copied to the command field in the hardware mailbox for remote I/O */N/* bus register access on SRM-mailbox machines. */N/*- 5 */  #include !#define ADP$M_INDIRECT_VECTOR 0x1#define ADP$M_ONLINE 0x2#define ADP$M_BOOT_ADP 0x4 #define ADP$M_PCI_PCI_BRIDGE 0x8#define ADP$M_EISA_PARENT 0x10#define ADP$M_DEEP 0x20#define ADP$M_PCI_MULTI 0x40#define ADP$M_HCDP 0x80#define ADP$M_MULTI_CHAN 0x100#define ADP$M_SHUTDOWN 0x1#define ADP$M_PORTONLY 0x2"#define ADP$M_STRUCT_ALLOCATED 0x4#define ADP$M_DDMA64 0x1#define ADP$M_DDMA_MONSTER 0x26 #define ADP$M_DDMA32 0x4#define ADP$M_MAP_REGISTERS 0x8!#define ADP$M_BUFFER_COPYING 0x10&#define ADP$M_ALLOC_MAP_REGISTERS 0x20  9#ifdef __cplusplus /* Define structure prototypes */ struct _crb;struct _busarray_header; struct _spl; struct _crab;struct _iohandle; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_a 7 lignment#endiftypedef struct _adp {#pragma __nomember_alignmentQ __int64 adp$q_csr; /* Adapter control and status register */N unsigned short int adp$w_size; /* Structure size in bytes */N unsigned char adp$b_type; /* Structure type code */N unsigned char adp$b_number; /* Ordinal adapter number */S struct _adp *adp$l_link; /* Address of next adapter control block */N unsigned int adp$l_t8 r; /* Configuration TR number */N unsigned int adp$l_adptype; /* Software adapter type */[ int (*adp$ps_node_data)(); /* Address of adapter specific node data routine */N void *adp$l_vector; /* Address of vector jump table */N struct _crb *adp$l_crb; /* Address of channel request block */Q void *adp$ps_mbpr; /* Address of mailbox pointer register */c#if !defined(__NOBASEALIGN_SUPPO 9 RT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifZ unsigned __int64 adp$q_queue_time; /* Timeout value for mailbox queueing operation */#pragma __nomember_alignment` unsigned __int64 adp$q_wait_time; /* Timeout value for mailbox completion (DON bit set) */_ struct _adp *adp$ps_parent_adp; /* Address of parent ADP (0 if this is the root ADP) */N struct _adp *adp$ps_peer_a: dp; /* Address of next ADP in peer list */N struct _adp *adp$ps_child_adp; /* Address of first child ADP */P unsigned int adp$l_probe_cmd; /* Command index used for probing bus */N struct _busarray_header *adp$ps_bus_array; /* Address of bus array */S void *adp$ps_command_tbl; /* Address of bus specific command table */N struct _spl *adp$ps_spinlock; /* Address of spinlock structure */N/* For a bus-to-bus adapter, the node_num is the; node number of the adapter */N/* on the primary bus. The sec_node_num is the node number of the adapter */N/* on the remote bus. Whether these fields are used or not depends on how */N/* the bus and adapter hardware are designed. Examples: for xmi, the lamb */N/* xmi node number is stored in sec_node_num. For the other XMI */N/* adapters, the xmi node number is stored in node_num and sec_node_num is */N/* not used. < */ __union {* unsigned short int adp$w_node_num;N unsigned short int adp$w_prim_node_num; /* Primary node number */! } adp$r_node_num_overlay;N unsigned short int adp$w_sec_node_num; /* Secondary node number */N unsigned short int adp$w_fill2 [1]; /* Keep alignment */N unsigned char adp$b_hose_num; /* I/O adapter hose number */N unsigned char adp$b_fill3 [1]; /* Keep alignment */N = __union { /* ADP specific cell */# void *adp$ps_adp_specific2;) unsigned int adp$l_adp_specific2;N unsigned int adp$l_hw_location; /* Geographic locator */N unsigned int adp$l_a32_free_items; /* Fbus specific usage */& } adp$r_adp_specific2_overlay;N __union { /* ADP specific cell */# void *adp$ps_adp_specific3;) unsigned int adp$l_adp > _specific3;N unsigned int adp$l_a64_item_num; /* Fbus specific usage */& } adp$r_adp_specific3_overlay;S struct _crab *adp$l_crab; /* Address of map register control block */ __union {) unsigned int adp$l_adapter_flags;N __struct { /* Adapter flags field */R unsigned adp$v_indirect_vector : 1; /* Indirect vectored interrupts */N unsigned adp$v_online : 1; /* Adapter is online ? */N unsigned adp$v_boot_adp : 1; /* Adapter is boot adapter */X unsigned adp$v_pci_pci_bridge : 1; /* Adapter represents a PCI/PCI bridge */N unsigned adp$v_eisa_parent : 1; /* EISA ADP is this adp's child */N unsigned adp$v_deep : 1; /* Multiple IRQs per SCB */N unsigned adp$v_pci_multi : 1; /* ADP represents a */I/* multifunction device */N @ unsigned adp$v_hcdp : 1; /* ADP for HCDP console devices */N unsigned adp$v_multi_chan : 1; /* ADP for multi-channel device */' unsigned adp$v_fill_4_ : 7;& } adp$r_adapter_flag_bits;& } adp$r_adapter_flags_overlay;N unsigned int adp$l_reserved1; /* Reserved for future expansion */ __union {N __int64 adp$q_hw_id_mask; /* Hardware ID mask 64-bits */ __struct {N int adp$l_hw_id_ A mask_lo; /* Hardware ID mask low 32-bits */N int adp$l_hw_id_mask_hi; /* Hardware ID mask high 32-bits */( } adp$r_adp_hw_id_mask_ints;' } adp$r_adp_hw_id_mask_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB adp$r_cbb_cpu_affinity; /* Embedded CB B B block */N __struct { /* Compatability offset cells */) __int64 adp$q_cbb_fill_1 [6]; __union {d unsigned int adp$l_cpu_affinity; /* Records CPUs which devices have affinity with */h unsigned __int64 adp$q_cpu_affinity; /* Records CPUs which devices have affinity with */0 } adp$r_cbb_cpuaff_data_overlay;* __int64 adp$q_cbb_fill_2 [15];. } adp$r_cbb_cpuaff C _compat_overlay;# } adp$r_cbb_cpuaff_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif_ int (*adp$ps_node_function)(); /* Address of adapter-specific node function routine */#pragma __nomember_alignment __union {N unsigned int adp$l_vportsts; /* CI - Vax port status bits */ __struct {P un D signed adp$v_shutdown : 1; /* CI - adapter microcode is stopped */[ unsigned adp$v_portonly : 1; /* CI - port restart only -- no adapter restart */b unsigned adp$v_struct_allocated : 1; /* CI/SCSI - adapter-wide structures allocated */' unsigned adp$v_fill_5_ : 5;" } adp$r_vportsts_bits;! } adp$r_vportsts_overlay;U void *adp$l_avector; /* Addr of 1ST SCB vector for this adaptor */ char adp$b_fill_6_ [4];c#if !defined E (__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif* unsigned __int64 adp$q_scratch_buf_pa;#pragma __nomember_alignmentP void *adp$ps_scratch_buf_va; /* VA, PA, and length of a physically */N unsigned int adp$l_scratch_buf_len; /* contiguous memory block */N void *adp$l_lsdump; /* Address of physical contiguous */N/* memory foF r the adapter memory dump. */[ int (*adp$ps_probe_csr)(); /* Address of adapter-specific probe CSR routine */c int (*adp$ps_probe_csr_cleanup)(); /* Address of adapter-specific probe CSR cleanup routine */c int (*adp$ps_load_map_reg)(); /* Address of adapter-specific load map register routine */Z int (*adp$ps_shutdown)(); /* Address of adapter-specific shutdown routine */P void *adp$ps_config_table; /* Point G er to autoconfiguration table */[ void *adp$ps_map_reg_base; /* Base virtual address of adapter map registers */ __union {N void *adp$ps_adp_specific; /* ADP specific cell */# void *adp$ps_adp_specific1;) unsigned int adp$l_adp_specific1;N unsigned int adp$l_a32_item_num; /* Fbus specific usage */N void *adp$ps_ablk; /* PNDRIVER specific usage */N void *adp$ps_ioc_base_va; H /* IPF - SVA of IOC register base */& } adp$r_adp_specific1_overlay;d int (*adp$ps_disable_interrupts)(); /* Address of adapter-specific disable interrupts routine */Y int (*adp$ps_startup)(); /* Address of adapter-specific startup routine */` int (*adp$ps_init)(); /* Address of adapter-specific initialization routine */N __union { /* ADP specific cell */# void *adp$ps_adp_specific4;) unsigned I int adp$l_adp_specific4;N unsigned int adp$l_a64_free_items; /* Fbus specific usage */] unsigned int adp$l_total_sg_entries; /* For PCI specific usage with memory channel */& } adp$r_adp_specific4_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifU __int64 adp$q_hardware_type; /* Saved hardware device type anJ d revision */#pragma __nomember_alignmentW __int64 adp$q_hardware_rev; /* info. Interpretation in adapter-specific. */[ int (*adp$ps_cram_cmd)(); /* Address of adapter-specific cram init routine */a int (*adp$ps_read_pci_config)(); /* Address of adapter-specific read pci config routine */b int (*adp$ps_write_pci_config)(); /* Address of adapter-specific write pci config routine */c int (*adp$ps_map_io)(); /* Address of adapter-specific I/O sK pace mapping routine */` int (*adp$ps_read_io)(); /* Address of adapter-specific read I/O space routine */a int (*adp$ps_write_io)(); /* Address of adapter-specific write I/O space routine */j struct _iohandle *adp$ps_iohandle_flink; /* Pointer to IOHANDLE structures associated with this bus */j struct _iohandle *adp$ps_iohandle_blink; /* Pointer to IOHANDLE structures associated with this bus */N/* Make sure that INTD has quadword alignment L */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned int adp$l_intd [4]; /* Interrupt transfer vector */#pragma __nomember_alignment[ unsigned int adp$l_bus_num; /* Bus number. Used for systems with remote PCI */N/* buses for Type1 config space address generation. */N unsigned short M int adp$w_fpars_sba_uid; /* SBA UID as short integer */N unsigned char adp$b_fpars_ioc_no; /* IOC number from low byte of UID */O unsigned char adp$b_fpars_rope_no; /* Rope number from ACPI _SUN method */ __union {W __int64 adp$q_pci_node_num; /* PCI node number of PCI/PCI bridge adapter */ __struct { __struct { __union {- int adp$l_pci_node_num_l; __struct {N/* Verified for X8 N 6, Dave Fairbanks */W int adp$l_pci_node_num; /* Signed on IA64, unsigned on alpha */( } adp$r_fill_3_;$ } adp$r_fill_2_;) int adp$l_pci_node_num_h;( } adp$r_pnn_long_struct; } adp$r_fill_1_; } adp$r_fill_0_;N/* Make sure that SINTD has quadword alignment */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__c O plusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned int adp$l_sintd [4]; /* Shared Interrupt transfer vector */#pragma __nomember_alignmente unsigned __int64 adp$q_hw_handle; /* An opaque hw_handle to match this ADP with its hardware */S unsigned __int64 adp$q_parent_hh; /* Hardware Handle of this ADP's parent. */N void *adp$ps_prt; /* Pointer to the PCI RoutinP g Table */e int (*adp$ps_unload_map_reg)(); /* Address of adapter-specific unload map register routine */N __int64 adp$q_iotlb_ibase; /* IOTLB IOVA base */P __int64 adp$q_iotlb_imask; /* IOTLB IOVA mask; defines IOVA size */N __int64 adp$q_iotlb_pa; /* Physical address of IOTLB */S unsigned __int64 adp$q_ioc_base_pa; /* IPF Physical address of IOC registers */N/* Q */N/* The TRA_OFFSET identifier is being deprecated in favor of */N/* the TRA_MMIO identifier, since we need a TRA for Port IO */N/* space as well. */N/* */ __union {( unsigned __int64 adp$q_tra_mmio;\ unsigned __int64 adp$q_tra_offset; /* Offset between I/O and system views of MMIO */! } adp$r_R tra_mmio_overlay;N unsigned __int64 adp$q_hid; /* ACPI Object Hardware ID field */N unsigned __int64 adp$q_uid; /* ACPI Object Unique ID field */W __union { /* This provides a cell for the ADP-specific */T __int64 adp$q_init_io_bridge; /* init_io_bridge routine, if one exists. */' int (*adp$ps_init_io_bridge)();' } adp$r_init_io_bridge_overlay;R unsigned __int64 adp$q_sal_handle; /* Identify shared FPars rS esouce to SAL */O void *adp$ps_config; /* Short pointer to GPSCONFIG struct */W/* These flags describe the types of DMA that are supported by the PLATFORM. Putting */U/* the flags at the ADP level allows additional flexibility on platforms where DMA */N/* capabilities vary by, for example, I/O controller. */N/* */U/* Device drivers use the same set of flag values to describe the DM T A capabilities */S/* supported by the driver. Note that capabilities may not be uniform across all */W/* driver functions; for example, command/response rings may be constrained to exist */[/* below 4GB at the same time that the driver/adapter support 64-bit transfer addresses. */N/* */ __union {) unsigned int adp$l_mapping_flags; __struct {N unsigned adp$v_ddma64 : 1; /* 64-bit DDMAU available */N unsigned adp$v_ddma_monster : 1; /* DDMA Monster window */N unsigned adp$v_ddma32 : 1; /* 32-bit DDMA available */N unsigned adp$v_map_registers : 1; /* Map registers available */S unsigned adp$v_buffer_copying : 1; /* Copying to/from system buffers */W unsigned adp$v_alloc_map_registers : 1; /* Allocate map regs before load */' unsigned adp$v_fill_7_ : 2;& } adp$r_ma V pping_flag_bits;- } adp$r_mapping_capabilities_overlay; __union {N unsigned __int64 adp$q_reserved14; /* Reserved for future expansion */ __struct {N void *adp$ps_devslots; /* Short Pointer to SLOT Objects */N int adp$l_devslot_count; /* Number of Device SLOT Objects */# } adp$r_devslot_struct; } adp$r_rsvd14;N/* Cells that describe the 32-bit Direct DMA window */N/* W */N unsigned __int64 adp$q_dma_base_pa; /* Base physical address of window */N unsigned __int64 adp$q_dma_size; /* Size of window */N unsigned __int64 adp$q_dma_paba_32; /* PA to bus address offset */N/* Cells that describe the 64-bit Direct DMA window */N/* */N unsigned __int64 adp$q_dma_paba_64; /* PX A to bus address offset */N/* Verified for X86, Dave Fairbanks */N/* */N/* */N/* This cell contains a pointer to the System Vector Map */N/* and is initialized by GPS$IRQ_SUPPPORT.C::irq$$init(). */N/* Y */ __union {+ unsigned __int64 adp$q_sys_vec_map; int *adp$ps_sys_vec_map; } adp$r_sys_vec_map;N/* */N/* */N/* This cell contains a pointer to an IO Access Data block */N/* defined in [IVMSLOA]LOCALDEFS.H as IORW_DATA. The cell */N/* is used in GPS$IO_SUPPORT to record salient det Z ails of */N/* the most recent IO Read attempt. */N/* */ __union {, unsigned __int64 adp$q_last_io_read;! int *adp$ps_last_io_read; } adp$r_last_io_read;N/* */N/* */N/* This cell contains a po [ inter to an IO Access Data block */N/* defined in [IVMSLOA]LOCALDEFS.H as IORW_DATA. The cell */N/* is used in GPS$IO_SUPPORT to record salient details of */N/* the most recent IO Write attempt. */N/* */ __union {- unsigned __int64 adp$q_last_io_write;" int *adp$ps_last_io_write; } adp$r_last_io_write;N \ /* */N/* */N/* This cell contains a pointer to the Vital Product Data (VPD). */N/* This is used by each device driver that supports VPD. */N/* */ __union {# unsigned __int64 adp$q_vpd; int *adp$ps_vpd; } adp$r_vpd;N ] unsigned __int64 adp$q_tra_portio; /* TRA for Port IO space. */ __union {N unsigned __int64 adp$q_cid_list; /* Pointer to the CID list */N char *adp$ps_cid_list; /* copied from ACPI */ } adp$r_cid;N unsigned __int64 adp$q_reserved24; /* Reserved for future expansion */ } ADP; #if !defined(__VAXC)<#define adp$w_node_num adp$r_node_num_overlay.adp$w_node_numF#define adp$w_prim_node_num adp$r_node_num_overlay.a^ dp$w_prim_node_numM#define adp$ps_adp_specific2 adp$r_adp_specific2_overlay.adp$ps_adp_specific2K#define adp$l_adp_specific2 adp$r_adp_specific2_overlay.adp$l_adp_specific2G#define adp$l_hw_location adp$r_adp_specific2_overlay.adp$l_hw_locationM#define adp$l_a32_free_items adp$r_adp_specific2_overlay.adp$l_a32_free_itemsM#define adp$ps_adp_specific3 adp$r_adp_specific3_overlay.adp$ps_adp_specific3K#define adp$l_adp_specific3 adp$r_adp_specific3_overlay.adp$l_adp_specific3I#define adp$l_a6_ 4_item_num adp$r_adp_specific3_overlay.adp$l_a64_item_numK#define adp$l_adapter_flags adp$r_adapter_flags_overlay.adp$l_adapter_flagsg#define adp$v_indirect_vector adp$r_adapter_flags_overlay.adp$r_adapter_flag_bits.adp$v_indirect_vectorU#define adp$v_online adp$r_adapter_flags_overlay.adp$r_adapter_flag_bits.adp$v_onlineY#define adp$v_boot_adp adp$r_adapter_flags_overlay.adp$r_adapter_flag_bits.adp$v_boot_adpe#define adp$v_pci_pci_bridge adp$r_adapter_flags_overlay.adp$r_adapter_flag_bits.a` dp$v_pci_pci_bridge_#define adp$v_eisa_parent adp$r_adapter_flags_overlay.adp$r_adapter_flag_bits.adp$v_eisa_parentQ#define adp$v_deep adp$r_adapter_flags_overlay.adp$r_adapter_flag_bits.adp$v_deep[#define adp$v_pci_multi adp$r_adapter_flags_overlay.adp$r_adapter_flag_bits.adp$v_pci_multiQ#define adp$v_hcdp adp$r_adapter_flags_overlay.adp$r_adapter_flag_bits.adp$v_hcdp]#define adp$v_multi_chan adp$r_adapter_flags_overlay.adp$r_adapter_flag_bits.adp$v_multi_chanF#define adp$q_hw_id_mask adpa $r_adp_hw_id_mask_overlay.adp$q_hw_id_maskf#define adp$l_hw_id_mask_lo adp$r_adp_hw_id_mask_overlay.adp$r_adp_hw_id_mask_ints.adp$l_hw_id_mask_lof#define adp$l_hw_id_mask_hi adp$r_adp_hw_id_mask_overlay.adp$r_adp_hw_id_mask_ints.adp$l_hw_id_mask_hiN#define adp$r_cbb_cpu_affinity adp$r_cbb_cpuaff_overlay.adp$r_cbb_cpu_affinity#define adp$l_cpu_affinity adp$r_cbb_cpuaff_overlay.adp$r_cbb_cpuaff_compat_overlay.adp$r_cbb_cpuaff_data_overlay.adp$l_cpu_affinity#define adp$q_cpu_affinity adp$r_cbb_cpub aff_overlay.adp$r_cbb_cpuaff_compat_overlay.adp$r_cbb_cpuaff_data_overlay.adp$q_cpu_affinity<#define adp$l_vportsts adp$r_vportsts_overlay.adp$l_vportstsP#define adp$v_shutdown adp$r_vportsts_overlay.adp$r_vportsts_bits.adp$v_shutdownP#define adp$v_portonly adp$r_vportsts_overlay.adp$r_vportsts_bits.adp$v_portonly`#define adp$v_struct_allocated adp$r_vportsts_overlay.adp$r_vportsts_bits.adp$v_struct_allocatedK#define adp$ps_adp_specific adp$r_adp_specific1_overlay.adp$ps_adp_specificM#define adc p$ps_adp_specific1 adp$r_adp_specific1_overlay.adp$ps_adp_specific1K#define adp$l_adp_specific1 adp$r_adp_specific1_overlay.adp$l_adp_specific1I#define adp$l_a32_item_num adp$r_adp_specific1_overlay.adp$l_a32_item_num;#define adp$ps_ablk adp$r_adp_specific1_overlay.adp$ps_ablkI#define adp$ps_ioc_base_va adp$r_adp_specific1_overlay.adp$ps_ioc_base_vaM#define adp$ps_adp_specific4 adp$r_adp_specific4_overlay.adp$ps_adp_specific4K#define adp$l_adp_specific4 adp$r_adp_specific4_overlay.adp$l_add p_specific4M#define adp$l_a64_free_items adp$r_adp_specific4_overlay.adp$l_a64_free_itemsQ#define adp$l_total_sg_entries adp$r_adp_specific4_overlay.adp$l_total_sg_entries;#define adp$q_pci_node_num adp$r_fill_0_.adp$q_pci_node_numq#define adp$l_pci_node_num_l adp$r_fill_0_.adp$r_fill_1_.adp$r_pnn_long_struct.adp$r_fill_2_.adp$l_pci_node_num_l{#define adp$l_pci_node_num adp$r_fill_0_.adp$r_fill_1_.adp$r_pnn_long_struct.adp$r_fill_2_.adp$r_fill_3_.adp$l_pci_node_numc#define adp$l_pci_node_ne um_h adp$r_fill_0_.adp$r_fill_1_.adp$r_pnn_long_struct.adp$l_pci_node_num_h<#define adp$q_tra_mmio adp$r_tra_mmio_overlay.adp$q_tra_mmio@#define adp$q_tra_offset adp$r_tra_mmio_overlay.adp$q_tra_offsetN#define adp$q_init_io_bridge adp$r_init_io_bridge_overlay.adp$q_init_io_bridgeP#define adp$ps_init_io_bridge adp$r_init_io_bridge_overlay.adp$ps_init_io_bridgeR#define adp$l_mapping_flags adp$r_mapping_capabilities_overlay.adp$l_mapping_flags\#define adp$v_ddma64 adp$r_mapping_capabilities_overlaf y.adp$r_mapping_flag_bits.adp$v_ddma64h#define adp$v_ddma_monster adp$r_mapping_capabilities_overlay.adp$r_mapping_flag_bits.adp$v_ddma_monster\#define adp$v_ddma32 adp$r_mapping_capabilities_overlay.adp$r_mapping_flag_bits.adp$v_ddma32j#define adp$v_map_registers adp$r_mapping_capabilities_overlay.adp$r_mapping_flag_bits.adp$v_map_registersl#define adp$v_buffer_copying adp$r_mapping_capabilities_overlay.adp$r_mapping_flag_bits.adp$v_buffer_copyingv#define adp$v_alloc_map_registers adp$r_mapping_g capabilities_overlay.adp$r_mapping_flag_bits.adp$v_alloc_map_registers6#define adp$q_reserved14 adp$r_rsvd14.adp$q_reserved14I#define adp$ps_devslots adp$r_rsvd14.adp$r_devslot_struct.adp$ps_devslotsQ#define adp$l_devslot_count adp$r_rsvd14.adp$r_devslot_struct.adp$l_devslot_count=#define adp$q_sys_vec_map adp$r_sys_vec_map.adp$q_sys_vec_map?#define adp$ps_sys_vec_map adp$r_sys_vec_map.adp$ps_sys_vec_map@#define adp$q_last_io_read adp$r_last_io_read.adp$q_last_io_readB#define adp$ps_last_io h _read adp$r_last_io_read.adp$ps_last_io_readC#define adp$q_last_io_write adp$r_last_io_write.adp$q_last_io_writeE#define adp$ps_last_io_write adp$r_last_io_write.adp$ps_last_io_write%#define adp$q_vpd adp$r_vpd.adp$q_vpd'#define adp$ps_vpd adp$r_vpd.adp$ps_vpd/#define adp$q_cid_list adp$r_cid.adp$q_cid_list1#define adp$ps_cid_list adp$r_cid.adp$ps_cid_list"#endif /* #if !defined(__VAXC) */ N#define ADP$K_CIADPLEN 672 /* Length of ADP for CI */N#define ADP$C_i CIADPLEN 672 /* Length of ADP for CI */N#define ADP$K_NIADPLEN 672 /* Length of ADP for NI */N#define ADP$C_NIADPLEN 672 /* Length of ADP for NI */Q#define ADP$K_GBIADPLEN 672 /* Length of ADP for Generic BI device */Q#define ADP$C_GBIADPLEN 672 /* Length of ADP for Generic BI device */N#define ADP$K_MINADPLEN 672 /* Length of smallest available ADP */N#define ADP$C_MINADPLEN 672 j /* Length of smallest available ADP */Q#define ADP$S_ADPDEF 672 /* Old ADP size field for compatiblity */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ADPDEF_LOADED */ ww@ZUM/*****************k **********************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprl ise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. m **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 16-MAR-1993 10:47:48 $1$DGA8345:[LIB_H.SRC]AIBDEF.SDL;1 *//******************************************************************* n *************************************************************//*** MODULE $AIBDEF ***/#ifndef __AIBDEF_LOADED#define __AIBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short o /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ p */N/* FORMAT OF ACP I/O BUFFER PACKET. THIS PACKET CONTAINS ALL THE DATA */N/* TRANSMITTED FROM THE USER TO THE ACP AND BACK FOR AN ACP FUNCTION. */N/* NOTE THAT THE DESCRIPTORS IN THE PACKET ARE TREATED BY BLISS CODE */N/* AS A BLOCKVECTOR. */N/*- */ N#define AIB$K_LENGTH 12 q /* LENGTH OF PACKET HEADER */N#define AIB$C_LENGTH 12 /* LENGTH OF PACKET HEADER */R#define AIB$S_AIBDEF 12 /* OLD SIZE NAME, SYNONYM FOR AIB$S_AIB */ typedef struct _aib {N void *aib$l_descript; /* ADDRESS OF START OF DESCRIPTORS */N int aibdef$$_fill_1; /* SPARE LONGWORD */N unsigned short int aib$w_size; /* SIZE OF PACKET */N unsigned char aib$b_tyr pe; /* PACKET TYPE CODE */N char aibdef$$_fill_2; /* SPARE */ } AIB; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __AIBDEF_LOADED */ ww`1ZUM/*******s ********************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packat rd Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. u **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */F/* Source: 19-APR-1993 13:46:59 $1$DGA8345:[LIB_H.SRC]ALFDEF.SDL;1 *//********************************************************* v ***********************************************************************//*** MODULE $ALFDEF ***/#ifndef __ALFDEF_LOADED#define __ALFDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_sizw e __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N x /*+ */N/* */N/* $ALFDEF - structure for auto-login file. */N/* */N/*- */#define ALF$C_LENGTH 128#define ALF$K_LENGTH 128#define ALF$S_ALFDEF 128 typedef struct _alf {Ny char alf$t_devname [63]; /* Terminal device name */N char alf$t_username [32]; /* Associated username */ char alf$b_fill_1 [33]; } ALF; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* z __ALFDEF_LOADED */ wwpXZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. { **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** | 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */H/* Source: 14-OCT-1994 16:13:32 $1$DGA8345:[LIB_H.SRC]APECSDEF.SDL;1 */ } /********************************************************************************************************************************//*** MODULE $APECSDEF ***/#ifndef __APECSDEF_LOADED#define __APECSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previou~ sly-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union unio n#else#define __union variant_union#endif#endif )#define APECS$Q_D21071CA_BASE -2147483648!#define APECS$Q_D21071CA_BASE_H 1)#define APECS$Q_D21071DA_BASE -1610612736!#define APECS$Q_D21071DA_BASE_H 1##define APECS$Q_PCI_SCS -1342177280#define APECS$Q_PCI_SCS_H 1)#define APECS$Q_PCI_SPARSE_IO -1073741824!#define APECS$Q_PCI_SPARSE_IO_H 1%#define APECS$Q_PCI_CONFIG -536870912#define APECS$Q_PCI_CONFIG_H 1 #define APECS$Q_PCI_SPARSE_MEM 0"#define APECS$Q_PCI_SPARSE_M EM_H 2#define APECS$Q_PCI_DENSE_MEM 0!#define APECS$Q_PCI_DENSE_MEM_H 3#define APECS_PCI_NODE_COUNT 13#define APECS$K_MEMORY_BANKS 9'#define APECS$M_TBASE1_32_10 0xFFFFFE00'#define APECS$M_TBASE2_32_10 0xFFFFFE00&#define APECS$M_PCIBASE1_SG_EN 0x40000$#define APECS$M_PCIBASE1_WEN 0x80000&#define APECS$M_PCIBASE2_SG_EN 0x40000$#define APECS$M_PCIBASE2_WEN 0x80000)#define APECS$M_PCIMASK1_31_20 0xFFF00000)#define APECS$M_PCIMASK2_31_20 0xFFF00000*#define APECS$M_HAXR1_PCI_31_27 0x F8000000!#define APECS$M_HAXR2_PCI_1_0 0x3*#define APECS$M_HAXR2_PCI_31_24 0xFF000000#define APECS$M_PMLC 0xFF#define APECS$K_LENGTH 16384 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _apecs {#pragma __nomember_alignment __union { int apecs$l_gcsr; __struct {- unsigned apecs$v_gcsr_fill1 :  32;" } apecs$r_gcsr_fields; } apecs$r_gcsr; char apecs$b_fill10 [2044]; __struct { __struct {' short int apecs$w_base_csr;- short int apecs$w_fill_base [15];' } apecs$r_bankset_base [9];+ char apecs$b_fill_base_array [224]; } apecs$r_bankset_bases; __struct { __struct { __union {- short int apecs$w_config_csr; __struct {/ unsigned apecs$v_valid : 1;1 unsigned apecs$v_fill_0_ : 7;# } apecs$r_bits;- } apecs$r_bankset_config_reg;/ short int apecs$w_fill_config [15];) } apecs$r_bankset_config [9];- char apecs$b_fill_config_array [224];" } apecs$r_bankset_configs; __struct { __struct {+ short int apecs$w_timing_a_csr;1 short int apecs$w_fill_timing_a [15];+  } apecs$r_bankset_timing_a [9];/ char apecs$b_fill_timing_a_array [224];$ } apecs$r_bankset_timing_as; __struct { __struct {+ short int apecs$w_timing_b_csr;1 short int apecs$w_fill_timing_b [15];+ } apecs$r_bankset_timing_b [9];/ char apecs$b_fill_timing_b_array [224];$ } apecs$r_bankset_timing_bs; char apecs$b_fill20 [4096]; __union { int apecs$l_dcsr; __struct {-  unsigned apecs$v_dcsr_fill1 : 32;" } apecs$r_dcsr_fields; } apecs$r_dcsr; char apecs$b_fill30 [28]; __union { int apecs$l_pear; __struct {- unsigned apecs$v_pear_fill1 : 32;" } apecs$r_pear_fields; } apecs$r_pear; char apecs$b_fill40 [28]; __union { int apecs$l_sear; __struct {- unsigned apecs$v_sear_fill1 : 32;" } apecs$r_sear_fields; } apecs$r_ sear; char apecs$b_fill50 [28]; __union { int apecs$l_dr1; __struct {, unsigned apecs$v_dr1_fill1 : 32;! } apecs$r_dr1_fields; } apecs$r_dr1; char apecs$b_fill60 [28]; __union { int apecs$l_dr2; __struct {, unsigned apecs$v_dr2_fill1 : 32;! } apecs$r_dr2_fields; } apecs$r_dr2; char apecs$b_fill70 [28]; __union { int apecs$l_dr3; __struct { , unsigned apecs$v_dr3_fill1 : 32;! } apecs$r_dr3_fields; } apecs$r_dr3; char apecs$b_fill80 [28]; __union { int apecs$l_tbase1; __struct {. unsigned apecs$v_tbase1_fill1 : 9;/ unsigned apecs$v_tbase1_32_10 : 23;$ } apecs$r_tbase1_fields; } apecs$r_tbase1; char apecs$b_fill90 [28]; __union { int apecs$l_tbase2; __struct {. unsigned apecs$v_tbase 2_fill1 : 9;/ unsigned apecs$v_tbase2_32_10 : 23;$ } apecs$r_tbase2_fields; } apecs$r_tbase2; char apecs$b_filla0 [28]; __union { int apecs$l_pcibase1; __struct {1 unsigned apecs$v_pcibase1_fill1 : 18;0 unsigned apecs$v_pcibase1_sg_en : 1;. unsigned apecs$v_pcibase1_wen : 1;1 unsigned apecs$v_pcibase1_31_20 : 12;& } apecs$r_pcibase1_fields; } apecs$r_pcibase1;  char apecs$b_fillb0 [28]; __union { int apecs$l_pcibase2; __struct {1 unsigned apecs$v_pcibase2_fill1 : 18;0 unsigned apecs$v_pcibase2_sg_en : 1;. unsigned apecs$v_pcibase2_wen : 1;1 unsigned apecs$v_pcibase2_31_20 : 12;& } apecs$r_pcibase2_fields; } apecs$r_pcibase2; char apecs$b_fillc0 [28]; __union { int apecs$l_pcimask1; __struct {1 unsigned apecs$v_pci mask1_fill1 : 20;1 unsigned apecs$v_pcimask1_31_20 : 12;& } apecs$r_pcimask1_fields; } apecs$r_pcimask1; char apecs$b_filld0 [28]; __union { int apecs$l_pcimask2; __struct {1 unsigned apecs$v_pcimask2_fill1 : 20;1 unsigned apecs$v_pcimask2_31_20 : 12;& } apecs$r_pcimask2_fields; } apecs$r_pcimask2; char apecs$b_fille0 [28]; __union { int apecs$l_haxr0; __st ruct {. unsigned apecs$v_haxr0_fill1 : 32;# } apecs$r_haxr0_fields; } apecs$r_haxr0; char apecs$b_fillf0 [28]; __union { int apecs$l_haxr1; __struct {. unsigned apecs$v_haxr1_fill1 : 27;1 unsigned apecs$v_haxr1_pci_31_27 : 5;# } apecs$r_haxr1_fields; } apecs$r_haxr1; char apecs$b_fill100 [28]; __union { int apecs$l_haxr2; __struct {/ unsigned ape cs$v_haxr2_pci_1_0 : 2;. unsigned apecs$v_haxr2_fill1 : 22;1 unsigned apecs$v_haxr2_pci_31_24 : 8;# } apecs$r_haxr2_fields; } apecs$r_haxr2; char apecs$b_fill110 [28]; __union { int apecs$l_pmlt; __struct {& unsigned apecs$v_pmlc : 8;- unsigned apecs$v_pmlt_fill1 : 24;" } apecs$r_pmlt_fields; } apecs$r_pmlt; char apecs$b_fill120 [28]; __union { int apecs$l_ tlb_tag0; __struct {1 unsigned apecs$v_tlb_tag0_fill1 : 32;& } apecs$r_tlb_tag0_fields; } apecs$r_tlb_tag0; char apecs$b_fill130 [28]; __union { int apecs$l_tlb_tag1; __struct {1 unsigned apecs$v_tlb_tag1_fill1 : 32;& } apecs$r_tlb_tag1_fields; } apecs$r_tlb_tag1; char apecs$b_fill140 [28]; __union { int apecs$l_tlb_tag2; __struct {1 unsigned ape cs$v_tlb_tag2_fill1 : 32;& } apecs$r_tlb_tag2_fields; } apecs$r_tlb_tag2; char apecs$b_fill150 [28]; __union { int apecs$l_tlb_tag3; __struct {1 unsigned apecs$v_tlb_tag3_fill1 : 32;& } apecs$r_tlb_tag3_fields; } apecs$r_tlb_tag3; char apecs$b_fill160 [28]; __union { int apecs$l_tlb_tag4; __struct {1 unsigned apecs$v_tlb_tag4_fill1 : 32;& } apecs$r_tlb_tag4 _fields; } apecs$r_tlb_tag4; char apecs$b_fill170 [28]; __union { int apecs$l_tlb_tag5; __struct {1 unsigned apecs$v_tlb_tag5_fill1 : 32;& } apecs$r_tlb_tag5_fields; } apecs$r_tlb_tag5; char apecs$b_fill180 [28]; __union { int apecs$l_tlb_tag6; __struct {1 unsigned apecs$v_tlb_tag6_fill1 : 32;& } apecs$r_tlb_tag6_fields; } apecs$r_tlb_tag6; char apecs$b_f ill190 [28]; __union { int apecs$l_tlb_tag7; __struct {1 unsigned apecs$v_tlb_tag7_fill1 : 32;& } apecs$r_tlb_tag7_fields; } apecs$r_tlb_tag7; char apecs$b_fill1a0 [28]; __union { int apecs$l_tlb_data0; __struct {2 unsigned apecs$v_tlb_data0_fill1 : 32;' } apecs$r_tlb_data0_fields; } apecs$r_tlb_data0; char apecs$b_fill1b0 [28]; __union { int apecs$l_tlb_da ta1; __struct {2 unsigned apecs$v_tlb_data1_fill1 : 32;' } apecs$r_tlb_data1_fields; } apecs$r_tlb_data1; char apecs$b_fill1c0 [28]; __union { int apecs$l_tlb_data2; __struct {2 unsigned apecs$v_tlb_data2_fill1 : 32;' } apecs$r_tlb_data2_fields; } apecs$r_tlb_data2; char apecs$b_fill1d0 [28]; __union { int apecs$l_tlb_data3; __struct {2 unsigned apecs $v_tlb_data3_fill1 : 32;' } apecs$r_tlb_data3_fields; } apecs$r_tlb_data3; char apecs$b_fill1e0 [28]; __union { int apecs$l_tlb_data4; __struct {2 unsigned apecs$v_tlb_data4_fill1 : 32;' } apecs$r_tlb_data4_fields; } apecs$r_tlb_data4; char apecs$b_fill1f0 [28]; __union { int apecs$l_tlb_data5; __struct {2 unsigned apecs$v_tlb_data5_fill1 : 32;' } apecs$r_tlb_da ta5_fields; } apecs$r_tlb_data5; char apecs$b_fill200 [28]; __union { int apecs$l_tlb_data6; __struct {2 unsigned apecs$v_tlb_data6_fill1 : 32;' } apecs$r_tlb_data6_fields; } apecs$r_tlb_data6; char apecs$b_fill210 [28]; __union { int apecs$l_tlb_data7; __struct {2 unsigned apecs$v_tlb_data7_fill1 : 32;' } apecs$r_tlb_data7_fields; } apecs$r_tlb_data7; char a pecs$b_fill220 [28]; __union { int apecs$l_tbia; __struct {- unsigned apecs$v_tbia_fill1 : 32;" } apecs$r_tbia_fields; } apecs$r_tbia; char apecs$b_fill230 [7164]; } APECS; #if !defined(__VAXC).#define apecs$l_gcsr apecs$r_gcsr.apecs$l_gcsrG#define apecs$r_bankset_base apecs$r_bankset_bases.apecs$r_bankset_base)#define apecs$w_base_csr apecs$w_base_csr+#define apecs$w_fill_base apecs$w_fill_baseM#define apecs$b_fill_b ase_array apecs$r_bankset_bases.apecs$b_fill_base_arrayM#define apecs$r_bankset_config apecs$r_bankset_configs.apecs$r_bankset_config=#define apecs$r_bankset_config_reg apecs$r_bankset_config_regH#define apecs$w_config_csr apecs$r_bankset_config_reg.apecs$w_config_csr<#define apecs$r_bits apecs$r_bankset_config_reg.apecs$r_bits0#define apecs$v_valid apecs$r_bits.apecs$v_validS#define apecs$r_bankset_timing_a apecs$r_bankset_timing_as.apecs$r_bankset_timing_a1#define apecs$w_timing_a_csr ape cs$w_timing_a_csrS#define apecs$r_bankset_timing_b apecs$r_bankset_timing_bs.apecs$r_bankset_timing_b1#define apecs$w_timing_b_csr apecs$w_timing_b_csr.#define apecs$l_dcsr apecs$r_dcsr.apecs$l_dcsr.#define apecs$l_pear apecs$r_pear.apecs$l_pear.#define apecs$l_sear apecs$r_sear.apecs$l_sear+#define apecs$l_dr1 apecs$r_dr1.apecs$l_dr1+#define apecs$l_dr2 apecs$r_dr2.apecs$l_dr2+#define apecs$l_dr3 apecs$r_dr3.apecs$l_dr34#define apecs$l_tbase1 apecs$r_tbase1.apecs$l_tbase1V#define apec s$v_tbase1_32_10 apecs$r_tbase1.apecs$r_tbase1_fields.apecs$v_tbase1_32_104#define apecs$l_tbase2 apecs$r_tbase2.apecs$l_tbase2V#define apecs$v_tbase2_32_10 apecs$r_tbase2.apecs$r_tbase2_fields.apecs$v_tbase2_32_10:#define apecs$l_pcibase1 apecs$r_pcibase1.apecs$l_pcibase1^#define apecs$v_pcibase1_sg_en apecs$r_pcibase1.apecs$r_pcibase1_fields.apecs$v_pcibase1_sg_enZ#define apecs$v_pcibase1_wen apecs$r_pcibase1.apecs$r_pcibase1_fields.apecs$v_pcibase1_wen:#define apecs$l_pcibase2 apecs$r_pcibase 2.apecs$l_pcibase2^#define apecs$v_pcibase2_sg_en apecs$r_pcibase2.apecs$r_pcibase2_fields.apecs$v_pcibase2_sg_enZ#define apecs$v_pcibase2_wen apecs$r_pcibase2.apecs$r_pcibase2_fields.apecs$v_pcibase2_wen:#define apecs$l_pcimask1 apecs$r_pcimask1.apecs$l_pcimask1^#define apecs$v_pcimask1_31_20 apecs$r_pcimask1.apecs$r_pcimask1_fields.apecs$v_pcimask1_31_20:#define apecs$l_pcimask2 apecs$r_pcimask2.apecs$l_pcimask2^#define apecs$v_pcimask2_31_20 apecs$r_pcimask2.apecs$r_pcimask2_fields.apecs$v_pc imask2_31_201#define apecs$l_haxr0 apecs$r_haxr0.apecs$l_haxr01#define apecs$l_haxr1 apecs$r_haxr1.apecs$l_haxr1Z#define apecs$v_haxr1_pci_31_27 apecs$r_haxr1.apecs$r_haxr1_fields.apecs$v_haxr1_pci_31_271#define apecs$l_haxr2 apecs$r_haxr2.apecs$l_haxr2V#define apecs$v_haxr2_pci_1_0 apecs$r_haxr2.apecs$r_haxr2_fields.apecs$v_haxr2_pci_1_0Z#define apecs$v_haxr2_pci_31_24 apecs$r_haxr2.apecs$r_haxr2_fields.apecs$v_haxr2_pci_31_24.#define apecs$l_pmlt apecs$r_pmlt.apecs$l_pmltB#define apecs$v_ pmlc apecs$r_pmlt.apecs$r_pmlt_fields.apecs$v_pmlc:#define apecs$l_tlb_tag0 apecs$r_tlb_tag0.apecs$l_tlb_tag0:#define apecs$l_tlb_tag1 apecs$r_tlb_tag1.apecs$l_tlb_tag1:#define apecs$l_tlb_tag2 apecs$r_tlb_tag2.apecs$l_tlb_tag2:#define apecs$l_tlb_tag3 apecs$r_tlb_tag3.apecs$l_tlb_tag3:#define apecs$l_tlb_tag4 apecs$r_tlb_tag4.apecs$l_tlb_tag4:#define apecs$l_tlb_tag5 apecs$r_tlb_tag5.apecs$l_tlb_tag5:#define apecs$l_tlb_tag6 apecs$r_tlb_tag6.apecs$l_tlb_tag6:#define apecs$l_tlb_tag7 apecs$r_t lb_tag7.apecs$l_tlb_tag7=#define apecs$l_tlb_data0 apecs$r_tlb_data0.apecs$l_tlb_data0=#define apecs$l_tlb_data1 apecs$r_tlb_data1.apecs$l_tlb_data1=#define apecs$l_tlb_data2 apecs$r_tlb_data2.apecs$l_tlb_data2=#define apecs$l_tlb_data3 apecs$r_tlb_data3.apecs$l_tlb_data3=#define apecs$l_tlb_data4 apecs$r_tlb_data4.apecs$l_tlb_data4=#define apecs$l_tlb_data5 apecs$r_tlb_data5.apecs$l_tlb_data5=#define apecs$l_tlb_data6 apecs$r_tlb_data6.apecs$l_tlb_data6=#define apecs$l_tlb_data7 apecs$ r_tlb_data7.apecs$l_tlb_data7.#define apecs$l_tbia apecs$r_tbia.apecs$l_tbia"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __APECSDEF_LOADED */ wwZUM/******************************* ********************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Developmen t, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */G/* Source: 27-APR-1993 16:42:30 $1$DGA8345:[LIB_H.SRC]APLDDEF.SDL;1 *//******************************************************************************* *************************************************//*** MODULE $APLDDEF ***/#ifndef __APLDDEF_LOADED#define __APLDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And s et ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define APLD$C_LENGT H 20 /* Length of APLD */N#define APLD$S_APLD$DEF 20 /* Old size name - synonym */ typedef struct _apld {N __union { /* base address of cmod table */N struct _apld *apld$l_base; /* Used as base of APLD struct */! void *apld$ps_cmod_table; } apld$r_cmod_table;N void *apld$ps_cmod_table_end; /* end of cmod table */N void *apld$ps_plv_list; /* base address of routine list */N void *apld$ps_plv_flags_list; /* base address of routine flags */N unsigned int apld$l_maxcode; /* max cmod code assigned */ } APLD; #if !defined(__VAXC)1#define apld$l_base apld$r_cmod_table.apld$l_base?#define apld$ps_cmod_table apld$r_cmod_table.apld$ps_cmod_table"#endif /* #if !defined(__VAXC) */ #define APLD$C_VECTOR_ENTRIES 42%#define APLD$C_MSG_VECTOR_ENTRIES 128!#define APLD$C_VECTOR_LENG TH 2584##define APLD$S_APLD$VECTOR_DEF 2584 typedef struct _apld$vector {N unsigned int apld$l_exec_apld_index; /* # of EXEC aplds entries */N unsigned int apld$l_kern_apld_index; /* # of KERN aplds entries */N unsigned int apld$l_exec_rundown_index; /* # of EXEC rndown entries */N unsigned int apld$l_kern_rundown_index; /* # of KERN rndown entries */N unsigned int apld$l_exec_apld_count; /* # EXEC aplds relocated */N unsigned int apld$ l_kern_apld_count; /* # KERN aplds relocated */N unsigned int apld$l_exec_rundown_count; /* # EXEC rndown relocated */N unsigned int apld$l_kern_rundown_count; /* # KERN rndown relocated */N unsigned int apld$l_exec_apld_perm; /* # of EXEC aplds process perm */N unsigned int apld$l_kern_apld_perm; /* # of KERN aplds process perm */N unsigned int apld$l_exec_rundown_perm; /* # of EXEC rndown proc perm */N unsigned int apld$l_kern_rundown_perm; /* # of KERN rndown proc perm */N unsigned int apld$l_message_count; /* # of message entries */N unsigned int apld$l_message_perm; /* # proc perm message entries */N __struct { /* base of EXEC apld structures */ APLD apld$r_filler;' } apld$r_exec_apld_vector [42];N __struct { /* base of KERN apld structures */ APLD apld$r_filler;' } apld$r_kern_apld_vector [42];N void * apld$ps_exec_rundown_vector [42]; /* base of EXEC rundown vector */N void *apld$ps_kern_rundown_vector [42]; /* base of KERN rundown vector */N unsigned int apld$l_message_vector [128]; /* base of message vector */ } APLD$VECTOR; #if !defined(__VAXC)"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previ ously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __APLDDEF_LOADED */ wwZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be u sed, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclos ed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-202 4 15:22:22 by OpenVMS SDL V3.7 */F/* Source: 30-MAR-2018 12:15:13 $1$DGA8345:[LIB_H.SRC]AQBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $AQBDEF ***/#ifndef __AQBDEF_LOADED#define __AQBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /*  Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#defin e __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DEFINITION OF ACP QUEUE HEADER */N/*- */ #define AQB$M_UNIQUE 0x1#define AQB$M_DEFCLASS 0x2#define AQB$M_DEFSYS 0x4#define AQ B$M_CREATING 0x8#define AQB$M_XQIOPROC 0x10N#define AQB$K_UNDEFINED 0 /* UNDEFINED ACP */N#define AQB$K_F11V1 1 /* FILES-11 STRUCTURE LEVEL 1 */N#define AQB$K_F11V2 2 /* FILES-11 STRUCTURE LEVEL 2 */N#define AQB$K_MTA 3 /* MAGTAPE */N#define AQB$K_NET 4 /* NETWORKS */N#define AQB$K_REM 5 /* REMOTE I/O  */N#define AQB$K_HBS 6 /* HOST BASED SHADOWING */O#define AQB$K_F11V3 7 /* Files-11 presentation of ISO 9660 */R#define AQB$K_F11V4 8 /* Files-11 presentation of High Sierra */N#define AQB$K_F64 9 /* Dollar ACP type */Q#define AQB$K_UCX 10 /* ACP for TCP/IP Services for OpenVMS */N#define AQB$K_F11V5 11 /* FILES-11 STRUCTURE LEVEL 5 */N#define AQB$K_F11V6 12 /* FILES-11 STRUCTURE LEVEL 6 */N#define AQB$K_LD 13 /* Logical Disk/Tape ACP */N#define AQB$C_MAXACP 13 /* maximum AQB supported */N#define AQB$K_LENGTH 40 /* SIZE OF AQB */N#define AQB$C_LENGTH 40 /* SIZE OF AQB */R#define AQB$S_AQBDEF 40 /* OLD SIZE NAME, SYNONYM FOR AQB$S_AQB */  9#ifdef _ _cplusplus /* Define structure prototypes */ struct _irp; struct _vcb; #endif /* #ifdef __cplusplus */ typedef struct _aqb { __union {N unsigned __int64 aqb$q_acpiq; /* INTERLOCKED QUEUE */ __struct {N struct _irp *aqb$l_acpqfl; /* QUEUE FORWARD LINK */N struct _irp *aqb$l_acpqbl; /* QUEUE BACK LINK */$ } aqb$r_acp_q_structure; } aqb$r_acpq_overlay;N unsigned sho rt int aqb$w_size; /* CONTROL BLOCK SIZE IN BYTES */N unsigned char aqb$b_type; /* BLOCK TYPE CODE */N unsigned char aqb$b_mntcnt; /* THIS FIELD IS NOW OBSOLETE */N/* AND HAS BEEN REPLACED BY */N/* AQB$L_MOUNT_COUNT */N unsigned int aqb$l_acppid; /* ACP PROCESS PID */N struct _aqb *aqb$l_link; /* AQB LIST LINKAGE */ __union {N unsigned char aqb$b_status; /* STATUS BYTE */ __struct {N unsigned aqb$v_unique : 1; /* ACP IS UNIQUE TO THIS DEVICE */N unsigned aqb$v_defclass : 1; /* ACP IS DEFAULT FOR THIS CLASS */N unsigned aqb$v_defsys : 1; /* ACP IS DEFAULT FOR THE SYSTEM */N unsigned aqb$v_creating : 1; /* ACP IS CURRENTLY BEING CREATED */T unsigned aqb$v_xqi oproc : 1; /* eXtended QIO PROCessor is being used. */' unsigned aqb$v_fill_0_ : 3; } aqb$r_status_bits; } aqb$r_status_overlay;N unsigned char aqb$b_acptype; /* ACP TYPE CODE */N/* */N/* ***** The following ACP type codes are now a user visible interface */N/* ***** and the values may not be changed. There are parallel definitions */N/* ***** in the $DVI DEF macro that define symbols of the form: */N/* ***** */N/* ***** DVI$C_ACP_F11V1 */N/* ***** DVI$C_ACP_F11V2 */N/* ***** DVI$C_ACP_MTA */N/* ***** ... */N/* *****  */N/* ***** All new ACP type values must be added at the end and the names */N/* ***** must be 5 characters or less to keep the DVI form of the name */N/* ***** 15 characters or less. Any additions must also be made in $DVIDEF */N/* ***** and in the list of ASSUMES in the module SYSGETDEV in [SYS.SRC] */N/* */N unsigned char aqb$b_class; /* ACP CLASS CODE  */N char aqbdef$$_fill_1; /* RESERVED */N void *aqb$l_bufcache; /* POINTER TO BUFFER CACHE */U unsigned int aqb$l_mount_count; /* ACP MOUNT COUNT (REPLACES AQB$B_MNTCNT) */N struct _vcb *aqb$l_orphaned_vcb; /* Pointer to Orphaned VCB */P void (*aqb$l_astadr)(); /* AST address used for XQP-type file */N/* system processing */ } AQ B; #if !defined(__VAXC)2#define aqb$q_acpiq aqb$r_acpq_overlay.aqb$q_acpiqF#define aqb$r_acp_q_structure aqb$r_acpq_overlay.aqb$r_acp_q_structure7#define aqb$l_acpqfl aqb$r_acp_q_structure.aqb$l_acpqfl7#define aqb$l_acpqbl aqb$r_acp_q_structure.aqb$l_acpqbl6#define aqb$b_status aqb$r_status_overlay.aqb$b_statusH#define aqb$v_unique aqb$r_status_overlay.aqb$r_status_bits.aqb$v_uniqueL#define aqb$v_defclass aqb$r_status_overlay.aqb$r_status_bits.aqb$v_defclassH#define aqb$v_defsys aqb$r_s tatus_overlay.aqb$r_status_bits.aqb$v_defsysL#define aqb$v_creating aqb$r_status_overlay.aqb$r_status_bits.aqb$v_creatingL#define aqb$v_xqioproc aqb$r_status_overlay.aqb$r_status_bits.aqb$v_xqioproc"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#e ndif#pragma __standard #endif /* __AQBDEF_LOADED */ wwZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written  permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Soft ware, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */F/* Source: 17-MAR-1995 07:57:57 $ 1$DGA8345:[LIB_H.SRC]ARBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ARBDEF ***/#ifndef __ARBDEF_LOADED#define __ARBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_s ize __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defin ed(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Access Rights Block - structure defining process access rights and */N/* privileges. Currently part of the PCB (meaning that the size of the */N/* ARB declared here must track in the PCB). */N/* */N/*- */ N#define ARB$C_HEADER 52 /* Length of header */N#define ARB$K_HEADER 52 /* Length of header */N#define ARB$K_LENGTH 124 /* Structure length */N#define ARB$C_LENGTH 124 /* Structure length */#define ARB$S_ARBDEF 124 ty pedef struct _arb {N unsigned __int64 arb$q_priv; /* Privilege mask */N unsigned short int arb$w_size; /* Structure size */N unsigned char arb$b_type; /* Structure type */N unsigned char arb$b_flags; /* ARB flags (unused) */N __struct { /* Security classification mask */ int arb$$$_fill_2 [5]; } arb$r_class; __union {N int  arb$l_rightslist [5]; /* Rights list descriptors */ __struct {N void *arb$l_process; /* process rights */N void *arb$l_system; /* system rights */N void *arb$l_extended; /* extended process rights */N void *arb$l_image; /* image rights */N void *arb$l_reserved; /* reserved */ } ar b$r_fill_1_; } arb$r_fill_0_;N __struct { /* Descriptor for local rights list */ int arb$$$_fill_3 [2]; } arb$r_rightsdesc;N __struct { /* Process local rights list */ __union {N unsigned int arb$l_uic; /* Process UID */ __struct {N unsigned short int arb$w_mem; /* Member number */N unsigned short int arb $w_grp; /* Group number */ } arb$r_fill_3_; } arb$r_fill_2_; int arb$$$_fill_4 [15]; } arb$r_localrights; } ARB; #if !defined(__VAXC)7#define arb$l_rightslist arb$r_fill_0_.arb$l_rightslist?#define arb$l_process arb$r_fill_0_.arb$r_fill_1_.arb$l_process=#define arb$l_system arb$r_fill_0_.arb$r_fill_1_.arb$l_systemA#define arb$l_extended arb$r_fill_0_.arb$r_fill_1_.arb$l_extended;#define arb$l_image arb$r_fill_0_.arb$r_fi ll_1_.arb$l_imageA#define arb$l_reserved arb$r_fill_0_.arb$r_fill_1_.arb$l_reserved;#define arb$l_uic arb$r_localrights.arb$r_fill_2_.arb$l_uicI#define arb$w_mem arb$r_localrights.arb$r_fill_2_.arb$r_fill_3_.arb$w_memI#define arb$w_grp arb$r_localrights.arb$r_fill_2_.arb$r_fill_3_.arb$w_grp"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __rest ore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ARBDEF_LOADED */ wwiZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/ M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be use d, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/ =/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */F/* Source: 18-OCT-2017 15:32:36 $1$DGA8345:[LIB_H.SRC]ARCDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ARCDEF ***/#ifndef __ARCDEF_LOADED#define __ARCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INI TIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */R/* Bit definitions for EXE$GL_ARCHFLAG - flags for VAX architecture differences */N/*  */N/*- */#define ARC$M_CHAR_EMUL 0x10#define ARC$M_DCML_EMUL 0x20#define ARC$M_EDPC_EMUL 0x40#define ARC$M_CRC_EMUL 0x80#define ARC$M_DFLT_EMUL 0x100#define ARC$M_FFLT_EMUL 0x200#define ARC$M_GFLT_EMUL 0x400#define ARC$M_HFLT_EMUL 0x800#define ARC$M_EMOD_EMUL 0x1000#define ARC$M_POLY_EMUL 0x2000#define ARC$M_VIRT_SCB 0x4000#define ARC$M_VIRT_SPT 0x8000#define ARC$M_VIRT_PCB 0x10000#def ine ARC$M_LOAD_SMP 0x20000#define ARC$S_ARCDEF 4 typedef struct _arc { __struct {N unsigned arcdef$$_fill_1 : 4; /* */N unsigned arc$v_char_emul : 1; /* Char Str Ins Emul */N unsigned arc$v_dcml_emul : 1; /* Decimal String Emul */N unsigned arc$v_edpc_emul : 1; /* EDITPC Instr Emul */N unsigned arc$v_crc_emul : 1; /* CRC Instr Emul */N  unsigned arc$v_dflt_emul : 1; /* D-flt Data Type Emul */N unsigned arc$v_fflt_emul : 1; /* F-flt Data Type Emul */N unsigned arc$v_gflt_emul : 1; /* G-flt Data Type Emul */N unsigned arc$v_hflt_emul : 1; /* H-flt Data Type Emul */N unsigned arc$v_emod_emul : 1; /* EMOD Instr Emul */N unsigned arc$v_poly_emul : 1; /* POLY Instr Emul */N unsigned arc$v_virt_scb : 1; /* SCB located in virtual memory */N unsigned arc$v_virt_spt : 1; /* SPT located in virtual memory */N unsigned arc$v_virt_pcb : 1; /* HWPCB located in virtual memory */N unsigned arc$v_load_smp : 1; /* Load SMP uncoditionally */N unsigned arcdef$$_fill_2 : 14; /* */ } arc$r_arcdef_bits; } ARC; #if !defined(__VAXC)9#define arc$v_char_emul arc$r_arcdef_bits.arc$v_char_emul9#define arc$ v_dcml_emul arc$r_arcdef_bits.arc$v_dcml_emul9#define arc$v_edpc_emul arc$r_arcdef_bits.arc$v_edpc_emul7#define arc$v_crc_emul arc$r_arcdef_bits.arc$v_crc_emul9#define arc$v_dflt_emul arc$r_arcdef_bits.arc$v_dflt_emul9#define arc$v_fflt_emul arc$r_arcdef_bits.arc$v_fflt_emul9#define arc$v_gflt_emul arc$r_arcdef_bits.arc$v_gflt_emul9#define arc$v_hflt_emul arc$r_arcdef_bits.arc$v_hflt_emul9#define arc$v_emod_emul arc$r_arcdef_bits.arc$v_emod_emul9#define arc$v_poly_emul arc$r_arcdef_bit s.arc$v_poly_emul7#define arc$v_virt_scb arc$r_arcdef_bits.arc$v_virt_scb7#define arc$v_virt_spt arc$r_arcdef_bits.arc$v_virt_spt7#define arc$v_virt_pcb arc$r_arcdef_bits.arc$v_virt_pcb7#define arc$v_load_smp arc$r_arcdef_bits.arc$v_load_smp"#endif /* #if !defined(__VAXC) */  "#pragma required_pointer_size save"#pragma required_pointer_size longtypedef ARC * ARC_PQ;##pragma required_pointer_size shorttypedef ARC * ARC_PL;%#pragma required_pointer_size restore $#pragma  __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ARCDEF_LOADED */ wwZUM/***************************************************************************/M/** **/M/** HP E CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENT IAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/********************************************************* ******************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */I/* Source: 09-JUN-1993 15:42:57 $1$DGA8345:[LIB_H.SRC]RMSFILSTR.SDL;1 *//********************************************************************************************************************************//*** MODULE $AREADEF ***/#ifndef __AREADEF_LOADED#define __AREADEF_LOADED 1  G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define  __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/*  */N/* definitions for the area descriptor in the prologue */N/* */N/* */N#define AREA$C_CYL 1 /* cylinded alignment */N#define AREA$C_LBN 2 /* logical block alignment */N#define AREA$C_VBN 3 /* virtual block alignment */T#define AREA$C_RFI 4 /* allocate close to related file by fid */#define AREA$M_HARD 0x1#define AREA$M_ONC 0x2#define AREA$M_CBT 0x20#define AREA$M_CTG 0x80X#define AREA$K_BLN 64 /* length of area descriptor in the prologue */X#define AREA$C_BLN 64 /* length of area descriptor in the prologue */N#define AREA$S_AREADEF 64 /* Old size name - synonym */ typedef struct _prologue_area {N char area$$_fill_1;  /* spare */N unsigned char area$b_flags; /* not currently used */N unsigned char area$b_areaid; /* area id */N unsigned char area$b_arbktsz; /* bucket size for area */N unsigned short int area$w_volume; /* relative volume number */N unsigned char area$b_aln; /* extend allocation alignment */ __union {N unsigned char area$b_aop; /* align ment options */ __struct {N unsigned area$v_hard : 1; /* absolute alignment or nothing */N unsigned area$v_onc : 1; /* locate on cylinder */' unsigned area$$_fill_2 : 3;N unsigned area$v_cbt : 1; /* contiguous best try */' unsigned area$$_fill_3 : 1;N unsigned area$v_ctg : 1; /* contiguous */ } area$r_aop_bits; } area$r _aop_overlay;N unsigned int area$l_avail; /* available (returned) buckets */N unsigned int area$l_cvbn; /* start vbn for current extent */Q unsigned int area$l_cnblk; /* number of blocks in current extent */N unsigned int area$l_used; /* number of blocks used */N unsigned int area$l_nxtvbn; /* next vbn to use */N unsigned int area$l_nxt; /* start vbn for next extent */N un signed int area$l_nxblk; /* number of blocks in next extent */N unsigned short int area$w_deq; /* default extend quantity */N char area$$_fill_4 [2]; /* spare */N unsigned int area$l_loc; /* start lbn on volume */N unsigned short int area$w_rfi [3]; /* related file id */N unsigned int area$l_total_alloc; /* total block allocation */N char area$$_fill_5 [8]; /* spare */N unsigned short int area$w_check; /* checksum */ } PROLOGUE_AREA; #if !defined(__VAXC)0#define area$b_aop area$r_aop_overlay.area$b_aop:#define area$r_aop_bits area$r_aop_overlay.area$r_aop_bits/#define area$v_hard area$r_aop_bits.area$v_hard-#define area$v_onc area$r_aop_bits.area$v_onc-#define area$v_cbt area$r_aop_bits.area$v_cbt-#define area$v_ctg area$r_aop_bits.area$v_ctg"#endif /* #if !defined(__ VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __AREADEF_LOADED */ wwZUM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/**  VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************** **********************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JAN-2004 07:50:02 $1$DGA8345:[LIB_H.SRC]TTYDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE ASSYMDEF ***/#ifndef __ASSYMDEF_LOADED #define __ASSYMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __ unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define AS$M_MD_ODLPARSE 0x1#define AS$M_MD_EDIT 0x2#define AS$M_MD_NOUPCASE 0x4#define AS$M_MD_INPUT 0x8#define AS $M_MD_1978 0x10#define AS$M_MD_PRELOAD 0x20#define AS$M_MD_4BYTE 0x40V#define AS$S_MODEDEF 1 /* Old size name, synonym for AS$S_AS_MODE */ typedef struct _as_mode {N unsigned as$v_md_odlparse : 1; /* Parse ODL request sequence */N unsigned as$v_md_edit : 1; /* MOC line editing */N unsigned as$v_md_noupcase : 1; /* Disable MOC upcasing */N unsigned as$v_md_input : 1; /* Input (Kana or Kanji)  */N unsigned as$v_md_1978 : 1; /* JIS 1978 code conversion */N unsigned as$v_md_preload : 1; /* Dynamic glyph preloading */N unsigned as$v_md_4byte : 1; /* 4-byte capability */ unsigned as$v_fill_5_ : 1; } AS_MODE;#define AS$M_ST_XPORT 0x1#define AS$M_ST_NOTTYGET 0x2#define AS$M_ST_GLOAD 0x4#define AS$M_ST_GLOAD2 0x8#define AS$M_ST_NOJOBC 0x10#define AS$M_ST_NOECHO 0x20#define AS$M_ST_TIM 0x40X#define  AS$S_ODLLOADDEF 1 /* Old size name; synonym for AS$S_AS_ODLLOAD */ typedef struct _as_odlload {N unsigned as$v_st_xport : 1; /* Extended Port */N unsigned as$v_st_nottyget : 1; /* No TTYGET */N unsigned as$v_st_gload : 1; /* Glyph Load */N unsigned as$v_st_gload2 : 1; /* Glyph Load 2 */N unsigned as$v_st_nojobc : 1; /* No JOBCONT */N unsigned as$v_st_noecho : 1; /* No Echo */N unsigned as$v_st_tim : 1; /* Timer Active */ unsigned as$v_fill_6_ : 1; } AS_ODLLOAD;#define AS$M_PR_REQUEST 0xF#define AS$M_PR_XAREA 0x10#define AS$M_PR_XSEQ 0x20#define AS$M_PR_SKIP 0x40Y#define AS$S_ODLPARSEDEF 1 /* Old size name; synonym for AS$S_AS_ODLPARSE */ typedef struct _as_odlparse {N unsigned as$v_pr_request : 4; /* Req. seq. stat */N unsigned as$v_pr_xarea : 1; /* Extend Area */N unsigned as$v_pr_xseq : 1; /* Extended request sequence */N unsigned as$v_pr_skip : 1; /* Skip parsing in downloading */ unsigned as$v_fill_7_ : 1; } AS_ODLPARSE;#define AS$M_TR_ESCSEEN 0x1#define AS$M_TR_1STOF2B 0x2#define AS$M_TR_WAS_XA8 0x4#define AS$M_TR_KANAMODE 0x8#define AS$M_TR_UPCASE 0x10#define AS$M_TR_SS2 0x20 #define AS$M_TR_SS3 0x40Y#define AS$S_JISTRANSDEF 1 /* Old size name; synonym for AS$S_AS_JISTRANS */ typedef struct _as_jistrans {N unsigned as$v_tr_escseen : 1; /* ESC seen */N unsigned as$v_tr_1stof2b : 1; /* 1st of 2Byte */N unsigned as$v_tr_was_xa8 : 1; /* it was x'A8' */N unsigned as$v_tr_kanamode : 1; /* Kana mode */N unsigned as$v_tr_upcase : 1; /* Upper-case ASCII code */N unsigned as$v_tr_ss2 : 1; /* SS2 seen */N unsigned as$v_tr_ss3 : 1; /* SS3 seen */ unsigned as$v_fill_8_ : 1; } AS_JISTRANS;#define AS$M_ED_EDIT 0x1#define AS$M_ED_NOUPCASE 0x2#define AS$M_ED_RETBYTE 0x4#define AS$M_ED_GOTMOC 0x8#define AS$M_ED_GOTMULTI 0x10#define AS$M_ED_EXPNEXT 0x20#define AS$M_ED_ECHOMOC 0x40#define AS$M_ED_EDITMOC 0x80U#define AS $S_ASEDITDEF 1 /* Old size name; synonym for AS$S_AS_EDIT */ typedef struct _as_edit {N unsigned as$v_ed_edit : 1; /* MOC editing required */N unsigned as$v_ed_noupcase : 1; /* Disable MOC upcasing */N unsigned as$v_ed_retbyte : 1; /* Can return incomplete MOC */N unsigned as$v_ed_gotmoc : 1; /* Got a MOC */N unsigned as$v_ed_gotmulti : 1; /* Remove whole MOC from TA buffer */N unsigned as$v_ed_expnext : 1; /* Expecting next byte of MOC */N unsigned as$v_ed_echomoc : 1; /* MOC echo in pregress */N unsigned as$v_ed_editmoc : 1; /* MOC edit (e.g. del) */ } AS_EDIT;#define AS$M_XE_EXP2ND 0x1#define AS$M_XE_EXP3RD 0x2#define AS$M_XE_EXP4TH 0x4T#define AS$S_ASXEDDEF 1 /* Old size name; synonym for AS$S_AS_XED */ typedef struct _as_xed {N unsigned as$v_xe_exp2nd : 1; /* Exp ecting MOC 2nd byte */N unsigned as$v_xe_exp3rd : 1; /* Expecting MOC 3rd byte */N unsigned as$v_xe_exp4th : 1; /* Expecting MOC 4th byte */ unsigned as$v_fill_9_ : 5; } AS_XED;N/*++ */N/* VMS/Japanaese Multi Code Set Support bit */N/*-- */#define AS$M_MCE_SS2 0x1 #define AS$M_MCE_SS3 0x2#define AS$M_MCE_EXP2ND 0x4#define AS$M_MCE_EXP3RD 0x8#define AS$M_MCE_EXPSS2NXT 0x10 struct mcedef {N unsigned as$v_mce_ss2 : 1; /* Handling SS2 bit */N unsigned as$v_mce_ss3 : 1; /* Handling SS3 bit */N unsigned as$v_mce_exp2nd : 1; /* Expect 2nd byte of SS3 */N unsigned as$v_mce_exp3rd : 1; /* Expect 3rd byte of SS3 */N unsigned as$v_mce_expss2nxt : 1; /* Expect 2nd byte of SS2 */ unsigned as$v_fill_10_ : 3; } ;N/*++ */N/* VMS/Japanaese Output Character State bit */N/*-- */#define AS$M_OCS_MBCHAR 0x8000 struct ocsdef {N unsigned as$v_ocs_fill : 15; /* (reserved) */N unsigned as$v_ocs_mbchar : 1; /* Expect  a next byte of MB Char */ } ;N/*++ */N/* ODL parse State */N/*-- */N#define AS$C_PR_DONE 0 /* Whole sequence is parsed */N#define AS$C_PR_DCS 1 /* Parsed DCS, expect 1st P1 */Q#define AS$C_PR_PAR11 2 /* Parsed 1st P1 parameter , expect 2nd */R#define AS$C_PR_PARA 3 /* Parsed all P1 parameters, expect 'x' */Q#define AS$C_PR_TERM 4 /* Parsed 'x', expect 1st byte of code */Q#define AS$C_PR_1STB 5 /* Parsed 1st byte of code, expect 2nd */P#define AS$C_PR_2NDB 6 /* Parsed 2nd byte of code, expect ST */N/*++ */N/* VMS/Japanaese Multi Code Set Support SS handling state */N/*-- */#define AS$C_SS2 142#define AS$C_SS3 143N/*++ */N/* Dispatch code returned by AS$MOVEREADATA */N/*-- */N#define AS$C_GD_DISMISS 0 /* 0 - DISMISS */N#define AS$C_GD_GETNXT 1 /* 1 - TTY$GETN EXTCHAR */N#define AS$C_GD_FORMAT_CHAR 2 /* 2 - FORMAT_CHAR */N#define AS$C_GD_FORMAT_LOCAL 3 /* 3 - FORMAT_LOCAL */N#define AS$C_GD_STRTMULTI 4 /* 4 - STRTMULTI */N#define AS$C_GD_STRTMULTI_1 5 /* 5 - STRTMULTI_1 */N#define AS$C_GD_EOLSEEN 6 /* 6 - EOLSEEN */N#define AS$C_GD_XON 7 /* 7 - XON */N#d efine AS$C_GD_MOVE_BOL 8 /* 8 - MOVE_BOL */N#define AS$C_GD_MOVE_EOL 9 /* 9 - MOVE_EOL */N#define AS$C_GD_BACKSPACING 10 /* 10 - BACKSPACING */N#define AS$C_GD_EDITREAD 11 /* 11 - EDITREAD */N#define AS$C_GD_UPDATE_CURSOR 12 /* 12 - UPDATE_CURSOR */N#define AS$C_GD_OUTPUTANDWAIT 13 /* 13 - OUTPUTANDWAIT */N/*++ */N/* Miscellaneous symbols */N/*-- */#define AS$C_MOC_MIN 161 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif #pragma __standard #endif /* __ASSYMDEF_LOADED */ ww0-ZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written pe rmission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Softwa re, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */I/* Source: 13-MAR-1996 14:11:05 $1$ DGA8345:[LIB_H.SRC]ASTSTKDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ASTSTKDEF ***/#ifndef __ASTSTKDEF_LOADED#define __ASTSTKDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required _pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union #if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* AST stack - this defines the architected stack contents during */N/* an AST. */N/* */N/* This also contains a definition of the stack frame for SCH$ASTDEL(_K). */Q /* Offsets are defined both as positive from the base of the stack frame, and */N/* as negative from the base of the ASTSTK$ structure. */N/* */N/* It would be nice if ORIGIN could be used to let SDL do this, but the C */N/* backend doesn't know what to do with ORIGIN. */N/* */#define ASTSTK$M_FEN 0 x1$#define ASTSTK$M_FP_SAVE_DELAYED 0x2##define ASTSTK$M_FP_SAVE_ENABLE 0x4##define ASTSTK$M_FP_RECLEAR_FEN 0x8##define ASTSTK$ASTDEL_FRAME$Q_FP -8%#define ASTSTK$ASTDEL_FRAME$Q_R14 -16%#define ASTSTK$ASTDEL_FRAME$Q_R13 -24(#define ASTSTK$ASTDEL_FRAME$Q_RET_PC -32)#define ASTSTK$ASTDEL_FRAME$Q_HANDLER -40$#define ASTSTK$ASTDEL_FRAME$Q_PV -48#define ASTDEL_FRAME$K_SIZE 48#define ASTDEL_FRAME$C_SIZE 48"#define ASTSTK$K_NO_FEN_LENGTH 144"#define ASTSTK$C_NO_FEN_LENGTH 144#define AS TSTK$K_FEN_LENGTH 336#define ASTSTK$C_FEN_LENGTH 336#define ASTSTK$S_ASTSTKDEF 336 typedef struct _aststk { __union { __union {, unsigned __int64 aststk$q_flags; __struct {N unsigned aststk$v_fen : 1; /* Floating point enabled */U unsigned aststk$v_fp_save_delayed : 1; /* FP register save delayed */[ unsigned aststk$v_fp_save_enable : 1; /* Don't save without this bit set */W unsigned aststk$v_fp_reclear_fen : 1; /* If set, clear FEN after ast */. unsigned aststk$v_fill_2_ : 4;# } aststk$r_fill_1_; } aststk$r_fill_0_;+ unsigned __int64 astdel_frame$q_pv; } aststk$r_base_overlay; __union {, unsigned __int64 aststk$q_no_fen_r0;% unsigned __int64 aststk$q_f0;0 unsigned __int64 astdel_frame$q_handler; } aststk$r_f0_overlay; __union {, unsigned __int64 aststk$ q_no_fen_r1;% unsigned __int64 aststk$q_f1;/ unsigned __int64 astdel_frame$q_ret_pc; } aststk$r_f1_overlay; __union {- unsigned __int64 aststk$q_no_fen_r16;& unsigned __int64 aststk$q_f10;, unsigned __int64 astdel_frame$q_r13; } aststk$r_f10_overlay; __union {- unsigned __int64 aststk$q_no_fen_r17;& unsigned __int64 aststk$q_f11;, unsigned __int64 astdel_frame$q_r14; } aststk$r_f11_overlay;  __union {- unsigned __int64 aststk$q_no_fen_r18;& unsigned __int64 aststk$q_f12;+ unsigned __int64 astdel_frame$q_fp; } aststk$r_f12_overlay; __union {- unsigned __int64 aststk$q_no_fen_r19;& unsigned __int64 aststk$q_f13; } aststk$r_f13_overlay; __union {- unsigned __int64 aststk$q_no_fen_r20;& unsigned __int64 aststk$q_f14; } aststk$r_f14_overlay; __union {- unsigned __int64 aststk$ q_no_fen_r21;& unsigned __int64 aststk$q_f15; } aststk$r_f15_overlay; __union {- unsigned __int64 aststk$q_no_fen_r22;& unsigned __int64 aststk$q_f16; } aststk$r_f16_overlay; __union {- unsigned __int64 aststk$q_no_fen_r23;& unsigned __int64 aststk$q_f17; } aststk$r_f17_overlay; __union {- unsigned __int64 aststk$q_no_fen_r24;& unsigned __int64 aststk$q_f18; } aststk$r_f18_overlay;  __union {- unsigned __int64 aststk$q_no_fen_r25;& unsigned __int64 aststk$q_f19; } aststk$r_f19_overlay; __union {- unsigned __int64 aststk$q_no_fen_r26;& unsigned __int64 aststk$q_f20; } aststk$r_f20_overlay; __union {- unsigned __int64 aststk$q_no_fen_r27;& unsigned __int64 aststk$q_f21; } aststk$r_f21_overlay; __union {- unsigned __int64 aststk$q_no_fen_r28;& unsigned __int64 astst k$q_f22; } aststk$r_f22_overlay; __union {- unsigned __int64 aststk$q_no_fen_r29;& unsigned __int64 aststk$q_f23; } aststk$r_f23_overlay; __union {V unsigned __int64 aststk$q_no_fen_fill; /* Fill to ensure octaword alignment */& unsigned __int64 aststk$q_f24; } aststk$r_f24_overlay;" unsigned __int64 aststk$q_f25;" unsigned __int64 aststk$q_f26;" unsigned __int64 aststk$q_f27;" unsigned __int64 aststk$q_f28;"  unsigned __int64 aststk$q_f29;" unsigned __int64 aststk$q_f30;O unsigned __int64 aststk$q_f31; /* Placeholder for octword alignment */% unsigned __int64 aststk$q_fen_r0;% unsigned __int64 aststk$q_fen_r1;& unsigned __int64 aststk$q_fen_r16;& unsigned __int64 aststk$q_fen_r17;& unsigned __int64 aststk$q_fen_r18;& unsigned __int64 aststk$q_fen_r19;& unsigned __int64 aststk$q_fen_r20;& unsigned __int64 aststk$q_fen_r21;& unsigned __int64 aststk$q_fen_ r22;& unsigned __int64 aststk$q_fen_r23;& unsigned __int64 aststk$q_fen_r24;& unsigned __int64 aststk$q_fen_r25;& unsigned __int64 aststk$q_fen_r26;& unsigned __int64 aststk$q_fen_r27;& unsigned __int64 aststk$q_fen_r28;& unsigned __int64 aststk$q_fen_r29;O unsigned __int64 aststk$q_fen_fill; /* Fill to ensure octaword alignment */ } ASTSTK; #if !defined(__VAXC)L#define aststk$q_flags aststk$r_base_overlay.aststk$r_fill_0_.aststk$q_flagsY#define aststk$v_f en aststk$r_base_overlay.aststk$r_fill_0_.aststk$r_fill_1_.aststk$v_fenq#define aststk$v_fp_save_delayed aststk$r_base_overlay.aststk$r_fill_0_.aststk$r_fill_1_.aststk$v_fp_save_delayedo#define aststk$v_fp_save_enable aststk$r_base_overlay.aststk$r_fill_0_.aststk$r_fill_1_.aststk$v_fp_save_enableo#define aststk$v_fp_reclear_fen aststk$r_base_overlay.aststk$r_fill_0_.aststk$r_fill_1_.aststk$v_fp_reclear_fenA#define astdel_frame$q_pv aststk$r_base_overlay.astdel_frame$q_pvA#define aststk$q_no_ fen_r0 aststk$r_f0_overlay.aststk$q_no_fen_r03#define aststk$q_f0 aststk$r_f0_overlay.aststk$q_f0I#define astdel_frame$q_handler aststk$r_f0_overlay.astdel_frame$q_handlerA#define aststk$q_no_fen_r1 aststk$r_f1_overlay.aststk$q_no_fen_r13#define aststk$q_f1 aststk$r_f1_overlay.aststk$q_f1G#define astdel_frame$q_ret_pc aststk$r_f1_overlay.astdel_frame$q_ret_pcD#define aststk$q_no_fen_r16 aststk$r_f10_overlay.aststk$q_no_fen_r166#define aststk$q_f10 aststk$r_f10_overlay.aststk$q_f10B#defin e astdel_frame$q_r13 aststk$r_f10_overlay.astdel_frame$q_r13D#define aststk$q_no_fen_r17 aststk$r_f11_overlay.aststk$q_no_fen_r176#define aststk$q_f11 aststk$r_f11_overlay.aststk$q_f11B#define astdel_frame$q_r14 aststk$r_f11_overlay.astdel_frame$q_r14D#define aststk$q_no_fen_r18 aststk$r_f12_overlay.aststk$q_no_fen_r186#define aststk$q_f12 aststk$r_f12_overlay.aststk$q_f12@#define astdel_frame$q_fp aststk$r_f12_overlay.astdel_frame$q_fpD#define aststk$q_no_fen_r19 aststk$r_f13_overlay.aststk$q_ no_fen_r196#define aststk$q_f13 aststk$r_f13_overlay.aststk$q_f13D#define aststk$q_no_fen_r20 aststk$r_f14_overlay.aststk$q_no_fen_r206#define aststk$q_f14 aststk$r_f14_overlay.aststk$q_f14D#define aststk$q_no_fen_r21 aststk$r_f15_overlay.aststk$q_no_fen_r216#define aststk$q_f15 aststk$r_f15_overlay.aststk$q_f15D#define aststk$q_no_fen_r22 aststk$r_f16_overlay.aststk$q_no_fen_r226#define aststk$q_f16 aststk$r_f16_overlay.aststk$q_f16D#define aststk$q_no_fen_r23 aststk$r_f17_overlay.aststk$q_no _fen_r236#define aststk$q_f17 aststk$r_f17_overlay.aststk$q_f17D#define aststk$q_no_fen_r24 aststk$r_f18_overlay.aststk$q_no_fen_r246#define aststk$q_f18 aststk$r_f18_overlay.aststk$q_f18D#define aststk$q_no_fen_r25 aststk$r_f19_overlay.aststk$q_no_fen_r256#define aststk$q_f19 aststk$r_f19_overlay.aststk$q_f19D#define aststk$q_no_fen_r26 aststk$r_f20_overlay.aststk$q_no_fen_r266#define aststk$q_f20 aststk$r_f20_overlay.aststk$q_f20D#define aststk$q_no_fen_r27 aststk$r_f21_overlay.aststk$q_no_f en_r276#define aststk$q_f21 aststk$r_f21_overlay.aststk$q_f21D#define aststk$q_no_fen_r28 aststk$r_f22_overlay.aststk$q_no_fen_r286#define aststk$q_f22 aststk$r_f22_overlay.aststk$q_f22D#define aststk$q_no_fen_r29 aststk$r_f23_overlay.aststk$q_no_fen_r296#define aststk$q_f23 aststk$r_f23_overlay.aststk$q_f23F#define aststk$q_no_fen_fill aststk$r_f24_overlay.aststk$q_no_fen_fill6#define aststk$q_f24 aststk$r_f24_overlay.aststk$q_f24"#endif /* #if !defined(__VAXC) */  $#pragma __member_a lignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ASTSTKDEF_LOADED */ wwP{ZUM/***************************************************************************/M/** **/M/** HPE CONF IDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. T his software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************  ************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BBDDEF ***/#ifndef __BBDDEF_LOADED#define __BBDDEF_LOADED 1 G#pragm  a __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_p arams ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* B  ad block descriptor (generated by formatters for RK06, RM03, et al) */N/* */N/*- */ N#define BBD$K_DESCRIPT 8 /* start of bad block descriptors */N#define BBD$C_DESCRIPT 8 /* start of bad block descriptors */N#define BBD$S_BBDDEF 512 /* Old size name - synonym */ typedef struct _bbd {  N unsigned int bbd$l_serial; /* pack serial number */N unsigned short int bbd$w_reserved; /* reserved area (MBZ) */V unsigned short int bbd$w_flags; /* pack status flags (zero for normal use) */ char bbddef$$_fill_1 [500];N unsigned int bbd$l_lastword; /* last longword of block */ } BBD;#define BBD$K_ENTRY 4#define BBD$C_ENTRY 4N#define BBD$S_BBDDEF1 4 /* Old size name - synonym */  typedef struct _bbd1 { __union {N unsigned int bbd$l_badblock; /* individual bad block entry */ __struct {N unsigned bbd$v_cylinder : 15; /* cylinder number of bad block */) unsigned bbddef$$_fill_2 : 1;N unsigned bbd$v_sector : 8; /* sector number of bad block */N unsigned bbd$v_track : 7; /* track number of bad block */( unsigned bbd$v_fill_11_ : 1;" } bbd$r_badblock_bits; } bbd$r_bbd1_overlay; } BBD1; #if !defined(__VAXC)8#define bbd$l_badblock bbd$r_bbd1_overlay.bbd$l_badblockL#define bbd$v_cylinder bbd$r_bbd1_overlay.bbd$r_badblock_bits.bbd$v_cylinderH#define bbd$v_sector bbd$r_bbd1_overlay.bbd$r_badblock_bits.bbd$v_sectorF#define bbd$v_track bbd$r_bbd1_overlay.bbd$r_badblock_bits.bbd$v_track"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size prag mas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BBDDEF_LOADED */ wwpZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlet t-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Softwar e, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************  *******************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BBMDEF ***/#ifndef __BBMDEF_LOADED#define __BBMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_align ment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif  #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Bad block map (generated by bad block scan program) */N/*  */N/*- */ N#define BBM$K_POINTERS 4 /* start of retrieval pointers */N#define BBM$C_POINTERS 4 /* start of retrieval pointers */#define BBM$S_BBMDEF 512 /* Old size name - synonym /* retrieval pointer forma\t */ typedef struct _bbm {Q unsigned char bbm$b_coun tsize; /* retrieval pointer count field size */O unsigned char bbm$b_lbnsize; /* retrieval pointer LBN field size */O unsigned char bbm$b_inuse; /* number of retrieval words in use */R unsigned char bbm$b_avail; /* number of retrieval words available */N char bbm$$_fill_1 [506]; /* pointer space */N unsigned short int bbm$w_checksum; /* block checksum */ } BBM;N#define BBM$S_BBMDEF1 4 /* Old size name - synonym */ typedef struct _bbm1 {N unsigned char bbm$b_highlbn; /* high order LBN */N unsigned char bbm$b_count; /* block count */N unsigned short int bbm$w_lowlbn; /* low order LBN */ } BBM1;N#define BBM$S_BBMDEF2 5 /* Old size name - synonym */ @typedef struct _bbm2 { /* WARNING: aggregate has origin of -4 */= /* WARNING: aggregat! e element "bbm$b_prevhlbn" ignored */> /* WARNING: aggregate element "bbm$b_prevcount" ignored */= /* WARNING: aggregate element "bbm$w_prevllbn" ignored */ char bbm$$_fill_2; } BBM2;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #e " ndif /* __BBMDEF_LOADED */ ww>ZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. # **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **$ /M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */F/* Source: 20-APR-1993 10:15:39 $1$DGA8345:[LIB_H.SRC]BBSDEF.SDL; % 1 *//********************************************************************************************************************************//*** MODULE $BBSDEF ***/#ifndef __BBSDEF_LOADED#define __BBSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previou& sly-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union unio' n#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Structure of message from disk ACP to bad block scan utility. */N/* */N/*- */ #define BBS$K_LENGTH 18#define BBS$( C_LENGTH 18#define BBS$S_BBSDEF 18  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; #endif /* #ifdef __cplusplus */ typedef struct _bbs {P unsigned char bbs$b_msgtype; /* message type code (MSG$C_SCANBAD) */N char bbsdef$$_fill_1 [3]; /* unused */N unsigned short int bbs$w_sequence; /* message sequence number */N short int bbsdef$$_fill_2; /* unused */N) struct _ucb *bbs$l_ucb; /* UCB address of device */N unsigned short int bbs$w_fid [3]; /* file ID of file */ } BBS; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BBSDEF_LOADED */ ww* eZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 20+ 24 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software,, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */E/* Source: 12-SEP-2020 01:52:06 $1$DGA8345:[LIB_H.SRC]BDDEF.SDL;1 *//******************************* - *************************************************************************************************//*** MODULE $BDDEF ***/#ifndef __BDDEF_LOADED#define __BDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma . __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union / #endif#endif N/*+ */N/* BD - Buffer Descriptor format in Buffer Descriptor Leaf table */N/*- */ #define BD$M_VALID 0x1#define BD$M_RO 0x2N#define BD$K_LENGTH 64 /* Length of a Buffer Descriptor */N#define BD$C_LENGTH 64 /* Length of a Buffer Descriptor */N#define BD$C_PORT_PAGE_SZ 8192 0 /* 8K Port Page Size */N#define BD$C_BD_IN_BDL 128 /* Number of BDs in a BDL */q#define BD$S_SHIFT_SIZE 5 /* Factor for shift left of a BDL index to get BD address within a BDL */S/* Note this shift size must reflect the NPort requirement that the BDL_INDEX be */P#define BD$S_BDDEF 64 /* Old size name, synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _cdrp;struct _crct 1 x; #endif /* #ifdef __cplusplus */ typedef struct _bufdesc {t unsigned __int64 bd$q_fill_1; /* Fill for hex alignement. If possible keep bit 16 of this field zero so */N/* the even number descriptor is never treated as a valid BD. */N unsigned short int bd$w_size; /* Structure size in bytes */N unsigned char bd$b_type; /* Structure Type */N unsigned char bd$b_subtype; /* Structure Subtype for BD */ 2  __union {N struct _cdrp *bd$l_cdrp; /* Addr of associated CDRP */O void *bd$l_link; /* or addr of next free descriptor */ } bd$r_cdrp_overlay;I unsigned __int64 bd$q_root_ptr0_vir; /* Virtual Root Pointer 0 */N unsigned __int64 bd$q_root_ptr1_vir; /* Virtual Root Pointer 1 */N unsigned short int bd$w_page_offset; /* Byte offset of start of buffer */ __union {N unsigned short int bd$w_flags; /* F 3 lags word */ __struct {N unsigned bd$v_valid : 1; /* Valid bit */Y unsigned bd$v_ro : 1; /* Read-Only access mode check enabled if set */N/* - Currently not supported */& unsigned bd$v_fill_0_ : 6; } bd$r_flags_bits; } bd$r_flags_overlay; __union {N unsigned int bd$l_bname; /* Buffer Name 4 */ __struct {N unsigned bd$v_bdl_index : 8; /* BDL Index */N unsigned bd$v_bdlt_index : 12; /* BDLT Index */N unsigned bd$v_key : 12; /* Sequence Number */! } bd$r_bname_bit_fld; } bd$r_bname_overlay;N unsigned int bd$l_buf_len; /* Length of mapped buffer */N unsigned int bd$l_sbz1; /* Should be zero */ __union 5 {~ __struct { /* Field serves as 1) input to MAP routine and 2) as default CI-like buffer pointer */N/* used by ports with no MAP routine (like PEDRIVER). */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *bd$pq_svapte_sva; /* NOSVAPTE_V9.0 cmos */#else# unsigned __int64 bd$pq_svapte 6 _sva;#endif) } bd$r_port_default_buff_ptr;N __struct { /* NPORT Overlay */ __union {S unsigned __int64 bd$q_root_ptr0_phy; /* Physical Root Pointer 0 */ __struct {N unsigned bd$v_ptr0_type : 2; /* Type */. unsigned bd$v_fill_1_ : 6;) } bd$r_root_ptr0_fld;) } bd$r_root_ptr0_overlay; 7 __union {R unsigned __int64 bd$q_root_ptr1_phy; /* Physical Root Pointer 1 */ __struct {N unsigned bd$v_ptr1_type : 2; /* Type */. unsigned bd$v_fill_2_ : 6;) } bd$r_root_ptr1_fld;) } bd$r_root_ptr1_overlay;" } bd$r_nport_root_ptr;N __struct { /* SSP Port Overlay */R#ifdef __INITIAL_POINTER_SIZE /* Defined wh 8 enever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifZ void *bd$l_fill_2; /* Skip over "First SVAPTE of User Data Buffer" */_ struct _crctx *bd$l_crctx; /* Address of CRCTX assoicated with this I/O request */ } bd$r_ssp_overlay;% } bd$r_port_specific_overlay;N/* based on a buffer descriptor size of 32. */ } BUFDESC; #i 9 f !defined(__VAXC)-#define bd$l_cdrp bd$r_cdrp_overlay.bd$l_cdrp-#define bd$l_link bd$r_cdrp_overlay.bd$l_link0#define bd$w_flags bd$r_flags_overlay.bd$w_flags@#define bd$v_valid bd$r_flags_overlay.bd$r_flags_bits.bd$v_valid:#define bd$v_ro bd$r_flags_overlay.bd$r_flags_bits.bd$v_ro0#define bd$l_bname bd$r_bname_overlay.bd$l_bnameK#define bd$v_bdl_index bd$r_bname_overlay.bd$r_bname_bit_fld.bd$v_bdl_indexM#define bd$v_bdlt_index bd$r_bname_overlay.bd$r_bname_bit_fld.bd$v_bdlt_index?#defin: e bd$v_key bd$r_bname_overlay.bd$r_bname_bit_fld.bd$v_key_#define bd$pq_svapte_sva bd$r_port_specific_overlay.bd$r_port_default_buff_ptr.bd$pq_svapte_svas#define bd$q_root_ptr0_phy bd$r_port_specific_overlay.bd$r_nport_root_ptr.bd$r_root_ptr0_overlay.bd$q_root_ptr0_phy~#define bd$v_ptr0_type bd$r_port_specific_overlay.bd$r_nport_root_ptr.bd$r_root_ptr0_overlay.bd$r_root_ptr0_fld.bd$v_ptr0_types#define bd$q_root_ptr1_phy bd$r_port_specific_overlay.bd$r_nport_root_ptr.bd$r_root_ptr1_overlay.bd$q_ ; root_ptr1_phy~#define bd$v_ptr1_type bd$r_port_specific_overlay.bd$r_nport_root_ptr.bd$r_root_ptr1_overlay.bd$r_root_ptr1_fld.bd$v_ptr1_typeK#define bd$l_fill_2 bd$r_port_specific_overlay.bd$r_ssp_overlay.bd$l_fill_2I#define bd$l_crctx bd$r_port_specific_overlay.bd$r_ssp_overlay.bd$l_crctx"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore < /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BDDEF_LOADED */ wwZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/*= * authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, d> uplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* ? Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */I/* Source: 22-APR-1993 10:11:31 $1$DGA8345:[LIB_H.SRC]BDLPTRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BDLPTRDEF ***/#ifndef __BDLPTRDEF_LOADED#define __BDLPTRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifd@ ef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define A __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* BDLPTR - NPORT Buffer Descriptor Leaf pointer */N/* */N/* This table is sharable among all SCS ports using the NPORT B architectured */N/* named buffer convention. buffer descriptors (BD's) are allocated for SCS */Q/* block transfers. the BDLT must be aligned on a an 8K boundary. The BDLT can */N/* support up to 4096 BDL pointers but in this implementation will only */R/* support up to 32 BDL pointers for a maximum of 8148 buffer descriptors. This */N/* definition only defines a single BDL pointer, each BDL pointer has the */P/* identical structure. The VMS implementation uses the first few pointers as */C N/* defined in CMNBDLTDEF. */N/* */N/* 63 1 0 */N/* ----------------------------------------------------- */E/* | BDL_PTR_PHY |V| V=valid */N/* ----------------------------------------------------- */F/* | BDL_PTR_VIR D | */N/* ----------------------------------------------------- */N/*- */ #define BDLPTR$M_VALID 0x1N#define BDLPTR$C_LENGTH 16 /* Length of structure */d#define BDLPTR$S_SHIFT_SIZE 4 /* Factor for shift left of BDLT index to get BDL address */#define BDLPTR$S_BDLPTRDEF 16 typedef struct _bdlptr { __union {[ unsign E ed __int64 bdlptr$q_phy_addr; /* Buffer Descriptor 0 Leaf Physical Pointer */ __struct {N unsigned bdlptr$v_valid : 1; /* Valid Bit */* unsigned bdlptr$v_fill_0_ : 7;" } bdlptr$r_flags_bits; } bdlptr$r_phy_overlay;V unsigned __int64 bdlptr$q_vir_addr; /* Buffer Descriptor 0 Leaf Virtual Pointer */ } BDLPTR; #if !defined(__VAXC)@#define bdlptr$q_phy_addr bdlptr$r_phy_overlay.bdlptr$q_phy_addrN#define bdlptrF $v_valid bdlptr$r_phy_overlay.bdlptr$r_flags_bits.bdlptr$v_valid"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BDLPTRDEF_LOADED */ ww)ZUM/*******************************************G ********************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP H **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** I **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */I/* Source: 09-JUN-1993 15:42:57 $1$DGA8345:[LIB_H.SRC]RMSFILSTR.SDL;1 *//***************************************************************************************** J ***************************************//*** MODULE $BKTDEF ***/#ifndef __BKTDEF_LOADED#define __BKTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size K default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* L */N/* index bucket definition */N/* */N/* this is the bucket format for RMS-11/RMS-32 index files. */N/* */N#define BKT$K_OVERHDSZ 14 /* length of bucket overhead */N#define BKT$C_OVERHDSZ 14 /* length of bucke M t overhead */#define BKT$M_LASTBKT 0x1#define BKT$M_ROOTBKT 0x2#define BKT$M_PTR_SZ 0x18N#define BKT$C_ENDOVHD 4 /* end of bucket overhead */V#define BKT$C_DATBKTOVH 2 /* end of bucket overhead for data buckets */U#define BKT$C_DUPBKTOVH 4 /* additional end of data bucket overhead */N/* when duplicates are allowed (LCB pointer */N#define BKT$C_MAXBKTSIZ 63 /* maximum bucket size N */N#define BKT$S_BKTDEF 14 /* Old size name - synonym */ typedef struct _bkt {N unsigned char bkt$b_checkchar; /* bucket check character */ __union {Z unsigned char bkt$b_areano; /* area number form which bucket was allocated */Y unsigned char bkt$b_indexno; /* index to which this bucket belongs (plg 3) */ } bkt$r_areano_overlay;b unsigned short int bkt$w_adrsample; /* address sample - low 16 b O its of first vbn in bucket */ __union {\ unsigned short int bkt$w_freespace; /* displacement in bucket of first free byte */V unsigned short int bkt$w_keyfrespc; /* pointer to key's free space (plg 3) */" } bkt$r_freespace_overlay; __union {W unsigned short int bkt$w_nxtrecid; /* next available word record id (plg 3) */ __struct {N unsigned char bkt$b_nxtrecid; /* next available record id */N unsigned char bkt$b_ P lstrecid; /* last id in range */$ } bkt$r_nxtrecid_fields;! } bkt$r_nxtrecid_overlay;N unsigned int bkt$l_nxtbkt; /* vbn of next bucket */N unsigned char bkt$b_level; /* bucket level number */ __union {N unsigned char bkt$b_bktcb; /* bucket control bits */ __struct {N unsigned bkt$v_lastbkt : 1; /* last bucket in horizontal chain */N unsigned bkt$v Q _rootbkt : 1; /* root bucket */N unsigned bkt$$_fill_1 : 1; /* spare */R unsigned bkt$v_ptr_sz : 2; /* size of vbn pointers in this bucket */' unsigned bkt$v_fill_4_ : 3; } bkt$r_bktcb_bits; } bkt$r_bktcb_overlay; } BKT; #if !defined(__VAXC)6#define bkt$b_areano bkt$r_areano_overlay.bkt$b_areano8#define bkt$b_indexno bkt$r_areano_overlay.bkt$b_indexno?#define bkt$w_freespace bkt$ R r_freespace_overlay.bkt$w_freespace?#define bkt$w_keyfrespc bkt$r_freespace_overlay.bkt$w_keyfrespc<#define bkt$w_nxtrecid bkt$r_nxtrecid_overlay.bkt$w_nxtrecidJ#define bkt$r_nxtrecid_fields bkt$r_nxtrecid_overlay.bkt$r_nxtrecid_fields;#define bkt$b_nxtrecid bkt$r_nxtrecid_fields.bkt$b_nxtrecid;#define bkt$b_lstrecid bkt$r_nxtrecid_fields.bkt$b_lstrecid3#define bkt$b_bktcb bkt$r_bktcb_overlay.bkt$b_bktcb=#define bkt$r_bktcb_bits bkt$r_bktcb_overlay.bkt$r_bktcb_bits4#define bkt$v_lastbkt S bkt$r_bktcb_bits.bkt$v_lastbkt4#define bkt$v_rootbkt bkt$r_bktcb_bits.bkt$v_rootbkt2#define bkt$v_ptr_sz bkt$r_bktcb_bits.bkt$v_ptr_sz"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BKTDEF_LOADED */  T ww wZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/*U * 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS SofV tware, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */G/* Source: 22-APR-1993 10:15:57 $1$DGA8345:[LIB_H.SRC]BNAMDEF.SDL;1 *//*********************** W *********************************************************************************************************//*** MODULE $BNAMDEF ***/#ifndef __BNAMDEF_LOADED#define __BNAMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr sizX e */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union Y variant_union#endif#endif N/*+ */N/* BNAM - NPORT Buffer Name Descriptor */N/* */N/*- */ N#define BNAM$C_LENGTH 4 /* Length of structure */N#define BNAM$M_BDLT_MASK -1048321 /* Mask to use extract BDL Z T index */N#define BNAM$M_BDL_MASK -256 /* Mask to use extract BDL index */N#define BNAM$M_KEY_MASK 1048575 /* Mask to use extract KEY */#define BNAM$S_BNAMDEF 4 typedef struct _bnam { __union {N void *bnam$l_bname; /* Buffer NAME */ __struct {N unsigned bnam$v_bdl_index : 8; /* BDL Index */N unsigned bnam$v_bdlt_index : 12; /* BDLT Index */N [ unsigned bnam$v_key : 12; /* Sequence Number */# } bnam$r_bname_bit_fld; } bnam$r_bname_overlay; } BNAM; #if !defined(__VAXC)6#define bnam$l_bname bnam$r_bname_overlay.bnam$l_bnameS#define bnam$v_bdl_index bnam$r_bname_overlay.bnam$r_bname_bit_fld.bnam$v_bdl_indexU#define bnam$v_bdlt_index bnam$r_bname_overlay.bnam$r_bname_bit_fld.bnam$v_bdlt_indexG#define bnam$v_key bnam$r_bname_overlay.bnam$r_bname_bit_fld.bnam$v_key"#endif /*\ #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BNAMDEF_LOADED */ ww@ZUM/***************************************************************************/M/** ] **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** ^ **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************_ **************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */F/* Source: 05-JAN-2019 16:33:14 $1$DGA8345:[LIB_H.SRC]BODDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BODDEF ***/#ifndef __BODD` EF_LOADED#define __BODDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {a #define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* BOD - Buffer Object Descriptor b */N/* */N/* A buffer object descriptor defines a buffer object used */N/* by the I/O subsystem. */N/*- */ #define BOD$M_DELPEN 0x1#define BOD$M_NOQUOTA 0x2#define BOD$M_S2_WINDOW 0x4#define BOD$M_NOSVA 0x8#define BOD$M_SYSBUFOBJ 0xc 10  9#ifdef __cplusplus /* Define structure prototypes */ struct _pte; struct _ext; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _bod {#pragma __nomember_alignmentN struct _bod *bod$l_flink; /* FLINK into PCB list */N struct _bod *bod$l_blink; /* d BLINK into PCB list */O unsigned short int bod$w_size; /* Size of fixed portion of BOOTCB */N unsigned char bod$b_type; /* Type of control block */ unsigned char bod$b_align_1;N unsigned int bod$l_acmode; /* Owner access mode */N unsigned int bod$l_seqnum; /* Sequence # at object creation */N unsigned int bod$l_refcnt; /* No. of references to this BOD */ __union {N unsigned ie nt bod$l_flags; /* Flags longword */ __struct {N unsigned bod$v_delpen : 1; /* Delete pending */N unsigned bod$v_noquota : 1; /* No quota charge for S0 window */S unsigned bod$v_s2_window : 1; /* Buffer object mapped into S2 space */R unsigned bod$v_nosva : 1; /* BO without associated system space */] unsigned bod$v_sysbufobj : 1; /* System buffer object (no process space ties) * f /' unsigned bod$v_fill_0_ : 3; } bod$r_flags_bits; } bod$r_flags_overlay;N unsigned int bod$l_pid; /* PID of creating process */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long g /* And set ptr size default to 64-bit pointers */T void *bod$pq_basepva; /* Base process address of buffer object */#else! unsigned __int64 bod$pq_basepva;#endif __union {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Z void *bod$pq_basesva; /* Base S2 address (valid iff BOD$V_S2_WINDOW) */#e h lse! unsigned __int64 bod$pq_basesva;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifS void *bod$l_basesva; /* Base system address of buffer object */ } bod$r_basesva_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else i #pragma __nomember_alignment#endifN __union { /* X-20a */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */T struct _pte *bod$pq_va_pte; /* S2 VA_PTE (valid iff BOD$V_S2_WINDOW) */#else unsigned __int64 bod$pq_va_pte;#endif } bod$r_svapte_overlay;N unsign j ed int bod$l_pagcnt; /* No. of pages in buffer object */N/* X-20b EXTENT fields are valid iff EXTENT is non-0 */ char bod$b_fill_1_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set k ptr size default to 64-bit pointers */W struct _ext *bod$pq_extent; /* Pointer to 1st buffer extent to reference */#else unsigned __int64 bod$pq_extent;#endif#pragma __nomember_alignmentP int bod$l_extent_boff; /* Byte offset into 1st buffer extent */ char bod$b_fill_2_ [4]; } BOD; #if !defined(__VAXC)3#define bod$l_flags bod$r_flags_overlay.bod$l_flagsF#define bod$v_delpen bod$r_flags_overlay.bod$r_flags_bits.bod$v_delpenH#define bod$v_noquot l a bod$r_flags_overlay.bod$r_flags_bits.bod$v_noquotaL#define bod$v_s2_window bod$r_flags_overlay.bod$r_flags_bits.bod$v_s2_windowD#define bod$v_nosva bod$r_flags_overlay.bod$r_flags_bits.bod$v_nosvaL#define bod$v_sysbufobj bod$r_flags_overlay.bod$r_flags_bits.bod$v_sysbufobj;#define bod$pq_basesva bod$r_basesva_overlay.bod$pq_basesva9#define bod$l_basesva bod$r_basesva_overlay.bod$l_basesva8#define bod$pq_va_pte bod$r_svapte_overlay.bod$pq_va_pte"#endif /* #if !defined(__VAXC) */ N#definm e BOD$K_LENGTH 80 /* LENGTH OF STRUCTURE */N#define BOD$C_LENGTH 80 /* LENGTH OF STRUCTURE */#define BOD$S_BODDEF 80 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BODDEF_LOADED */ n wwPZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/Mo /** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Sp oftware, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */I/* Source: 01-AUG-2016 16:01:48 $1$DGA8345:[LIB_H.SRC]BOOCMDDEF.SDL;1 *//******************* q *************************************************************************************************************//*** MODULE $boocmddef ***/#ifndef __BOOCMDDEF_LOADED#define __BOOCMDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined requirr ed ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#defins e __union variant_union#endif#endif N/*+ */I/* Definitions for SYSGEN/SYSBOOT command options flags */N/*- */#define BOOCMD$M_NOCHECK 0x1#define BOOCMD$M_NORESET 0x2#define BOOCMD$M_SAVE 0x4#define BOOCMD$M_USER 0x8#define BOOCMD$M_PAGEFILE 0x10#define BOOCMD$M_NONCONTIG 0x20#define BOOCMD$M_SELECT 0x40#define BOOCt MD$M_EXCLUDE 0x80#define BOOCMD$M_CONT 0x100#define BOOCMD$M_DEFAULT 0x200#define BOOCMD$M_USEFILE 0x400#define BOOCMD$M_DISHEX 0x800#define BOOCMD$M_AUTOLOG 0x1000#define BOOCMD$M_OUTPUT 0x2000#define BOOCMD$M_INPUT 0x4000!#define BOOCMD$M_SETOUTPUT 0x8000!#define BOOCMD$M_TERMINAL 0x10000#define BOOCMD$M_CONTIG 0x20000!#define BOOCMD$M_NOCHKPNT 0x40000#define BOOCMD$M_REMOTE 0x80000!#define BOOCMD$M_LOGICAL 0x100000#define BOOCMD$M_UART1 0x200000#define BOOCMD$Mu _UART2 0x400000#define BOOCMD$M_UART3 0x800000#define BOOCMD$M_NI 0x1000000"#define BOOCMD$M_NL_USER 0x2000000##define BOOCMD$M_DINS_ALL 0x4000000##define BOOCMD$M_DINS_IDX 0x8000000"#define BOOCMD$M_SETCMD 0x10000000&#define BOOCMD$M_CLR_MODIFY 0x20000000(#define BOOCMD$M_DYNAMIC_ONLY 0x40000000#define BOOCMD$S_BOOCMDDEF 4 typedef struct _boocmd { __struct {& unsigned boocmd$v_nocheck : 1;& unsigned boocmd$v_noreset : 1;# unsigned boocmd$v_save : 1v ;# unsigned boocmd$v_user : 1;' unsigned boocmd$v_pagefile : 1;( unsigned boocmd$v_noncontig : 1;% unsigned boocmd$v_select : 1;& unsigned boocmd$v_exclude : 1;# unsigned boocmd$v_cont : 1;& unsigned boocmd$v_default : 1;& unsigned boocmd$v_usefile : 1;% unsigned boocmd$v_dishex : 1;& unsigned boocmd$v_autolog : 1;% unsigned boocmd$v_output : 1;$ unsigned boocmd$v_input : 1;( unsigned boocmd$w v_setoutput : 1;' unsigned boocmd$v_terminal : 1;% unsigned boocmd$v_contig : 1;' unsigned boocmd$v_nochkpnt : 1;% unsigned boocmd$v_remote : 1;& unsigned boocmd$v_logical : 1;$ unsigned boocmd$v_uart1 : 1;$ unsigned boocmd$v_uart2 : 1;$ unsigned boocmd$v_uart3 : 1;! unsigned boocmd$v_ni : 1;& unsigned boocmd$v_nl_user : 1;' unsigned boocmd$v_dins_all : 1;' unsigned boocmd$v_dins_idx : 1;% un x signed boocmd$v_setcmd : 1;) unsigned boocmd$v_clr_modify : 1;+ unsigned boocmd$v_dynamic_only : 1;& unsigned boocmd$v_fill_0_ : 1; } boocmd$r_cmdopt_bits; } BOOCMD; #if !defined(__VAXC)>#define boocmd$v_nocheck boocmd$r_cmdopt_bits.boocmd$v_nocheck>#define boocmd$v_noreset boocmd$r_cmdopt_bits.boocmd$v_noreset8#define boocmd$v_save boocmd$r_cmdopt_bits.boocmd$v_save8#define boocmd$v_user boocmd$r_cmdopt_bits.boocmd$v_user@#define boocmd$v_pagefile y boocmd$r_cmdopt_bits.boocmd$v_pagefileB#define boocmd$v_noncontig boocmd$r_cmdopt_bits.boocmd$v_noncontig<#define boocmd$v_select boocmd$r_cmdopt_bits.boocmd$v_select>#define boocmd$v_exclude boocmd$r_cmdopt_bits.boocmd$v_exclude8#define boocmd$v_cont boocmd$r_cmdopt_bits.boocmd$v_cont>#define boocmd$v_default boocmd$r_cmdopt_bits.boocmd$v_default>#define boocmd$v_usefile boocmd$r_cmdopt_bits.boocmd$v_usefile<#define boocmd$v_dishex boocmd$r_cmdopt_bits.boocmd$v_dishex>#define boocmd$v_autolog z boocmd$r_cmdopt_bits.boocmd$v_autolog<#define boocmd$v_output boocmd$r_cmdopt_bits.boocmd$v_output:#define boocmd$v_input boocmd$r_cmdopt_bits.boocmd$v_inputB#define boocmd$v_setoutput boocmd$r_cmdopt_bits.boocmd$v_setoutput@#define boocmd$v_terminal boocmd$r_cmdopt_bits.boocmd$v_terminal<#define boocmd$v_contig boocmd$r_cmdopt_bits.boocmd$v_contig@#define boocmd$v_nochkpnt boocmd$r_cmdopt_bits.boocmd$v_nochkpnt<#define boocmd$v_remote boocmd$r_cmdopt_bits.boocmd$v_remote>#define boocmd$v_log { ical boocmd$r_cmdopt_bits.boocmd$v_logical:#define boocmd$v_uart1 boocmd$r_cmdopt_bits.boocmd$v_uart1:#define boocmd$v_uart2 boocmd$r_cmdopt_bits.boocmd$v_uart2:#define boocmd$v_uart3 boocmd$r_cmdopt_bits.boocmd$v_uart34#define boocmd$v_ni boocmd$r_cmdopt_bits.boocmd$v_ni>#define boocmd$v_nl_user boocmd$r_cmdopt_bits.boocmd$v_nl_user@#define boocmd$v_dins_all boocmd$r_cmdopt_bits.boocmd$v_dins_all@#define boocmd$v_dins_idx boocmd$r_cmdopt_bits.boocmd$v_dins_idx<#define boocmd$v_setcmd boocmd$r| _cmdopt_bits.boocmd$v_setcmdD#define boocmd$v_clr_modify boocmd$r_cmdopt_bits.boocmd$v_clr_modifyH#define boocmd$v_dynamic_only boocmd$r_cmdopt_bits.boocmd$v_dynamic_only"#endif /* #if !defined(__VAXC) */ #define BOOLAST$M_DEFAULT 0x1#define BOOLAST$M_ACTIVE 0x2#define BOOLAST$M_CURRENT 0x4#define BOOLAST$M_FILESPEC 0x8#define BOOLAST$S_BOOLASTDEF 1 typedef struct _boolastuse { __struct {' unsigned boolast$v_default : 1;& unsigned boolast$v_active : 1;' } unsigned boolast$v_current : 1;( unsigned boolast$v_filespec : 1;' unsigned boolast$v_fill_1_ : 4;! } boolast$r_lastuse_bits; } BOOLASTUSE; #if !defined(__VAXC)B#define boolast$v_default boolast$r_lastuse_bits.boolast$v_default@#define boolast$v_active boolast$r_lastuse_bits.boolast$v_activeB#define boolast$v_current boolast$r_lastuse_bits.boolast$v_currentD#define boolast$v_filespec boolast$r_lastuse_bits.boolast$v_filespec"#endif /* #if !defined(__~ VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BOOCMDDEF_LOADED */ wwp:ZUM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/* * VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************** ************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */I/* Source: 25-AUG-2005 12:49:26 $1$DGA8345:[LIB_H.SRC]BOOPARDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $boopardef ***/#ifndef __BOOPARDEF_ LOADED#define __BOOPARDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#d efine __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define BOOPAR$K_LENGTH 360 /* Length of argument list */  9#ifdef __cplusplus /* D efine structure prototypes */ struct _scb; struct _idt; #endif /* #ifdef __cplusplus */ typedef struct _booparam {N unsigned int boopar$l_arg_revision; /* Argument list revision */N void *boopar$l_pfn_map; /* Address of allocation bitmap */N unsigned int boopar$l_state; /* exe$gl_state */N unsigned int boopar$l_va_to_vpn; /* Negated vpn_to_va */N unsigned int boopar$l_vpn_to_va; /* Size of byte with in page field */N unsigned int boopar$l_bwp_mask; /* Byte within a page mask */N void *boopar$l_file_cache; /* addr of file cache */N unsigned int boopar$l_cache_size; /* file cache size */N void *boopar$l_sptbase; /* SPT base */N struct _scb *boopar$l_scb; /* SCB address */N void *boopar$l_hpdesc; /* ldr huge page structure */N st ruct _scb *boopar$l_xdtscb; /* Xdelta's SCB address */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */V void *boopar$pq_l1_base; /* VA of L1PT in PT_space for process space */#else$ unsigned __int64 boopar$pq_l1_base;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_siz e __long /* And set ptr size default to 64-bit pointers */W void *boopar$pq_l2_base; /* VA of L2PTs in PT_space for process space */#else$ unsigned __int64 boopar$pq_l2_base;#endifN __int64 boopar$q_non_va_mask; /* Mask for bits above L1 MSB */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */S void *boopar$pq_pt_base; /* V A of PT_space base for process space */#else$ unsigned __int64 boopar$pq_pt_base;#endifN unsigned int boopar$l_system_l1_index; /* L1 index of S0/S1 L1PTE */b unsigned int boopar$l_pt_space_l1_index; /* L1 index of self-mapped L1PTE for process space */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *boopar$pq_gap_lo; /* Low address end of gap */#else# unsigned __int64 boopar$pq_gap_lo;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *boopar$pq_gap_hi; /* High address end of gap */#else# unsigned __int64 boopar$pq_gap_hi;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *boopar$pq_proc_space_lim; /* Highest process space address */#else+ unsigned __int64 boopar$pq_proc_space_lim;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Z void *boopar$pq_s0s1base_pte_addr; /* Address of PTE that maps base of S0/S1 space */#else. unsigned __int64 boopar$pq_ s0s1base_pte_addr;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */V void *boopar$pq_shared_va_ptes; /* Boundary between process and system ptes */#else+ unsigned __int64 boopar$pq_shared_va_ptes;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */^ void *boopar$pq_sys_virt_base; /* Base address of system space (lowest addr in S2) */#else* unsigned __int64 boopar$pq_sys_virt_base;#endifX unsigned int boopar$l_va_bits; /* Number of bits in 3 level fields plus byte */N/* within page field */N int boopar$l_spare_1; /* */N __int64 boopar$q_virbnd; /* VIRBND register contents */N __int64 boopar$q_sysptbr; /* System Page Table Base Register */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */U void *boopar$pq_l1_basesys; /* VA of L1PT in PT_space for system space */#else' unsigned __int64 boopar$pq_l1_basesys;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __requir ed_pointer_size __long /* And set ptr size default to 64-bit pointers */V void *boopar$pq_l2_basesys; /* VA of L2PTs in PT_space for system space */#else' unsigned __int64 boopar$pq_l2_basesys;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */R void *boopar$pq_pt_basesys; /* VA of PT_space base for system space */#else' unsigned __int6 4 boopar$pq_pt_basesys;#endifd unsigned int boopar$l_pt_space_l1_indexsys; /* L1 index of self-mapped L1PTE for system space */N int boopar$l_spare_2; /* */\ __int64 boopar$q_pal_proc; /* Address of IA64 PAL code procedure entry point */N __int64 boopar$q_non_pt_mask; /* Mask for bits not in segments */a __int64 boopar$q_level_width; /* size of each segment field in VA; aka "level width" */Y __int64 boop ar$q_non_pa_mask; /* mask for bits not in physical address range */N __int64 boopar$q_ptes_per_page; /* how many PTEs fit into a page */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _idt *boopar$gpq_idt; /* pointer to IDT table */#else! unsigned __int64 boopar$gpq_idt;#endifR#ifdef __INITIAL_POINTER_SIZE /* Define d whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *boopar$pq_sal_plabel0; /* Code address of SAL */#else( unsigned __int64 boopar$pq_sal_plabel0;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *boopar$pq_sal_plabel1; /* GP for SAL */#else( unsigned __int64 boopar$pq_sal_plabel1;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *boopar$pq_fpswa; /* Address of FPSWA routine */#else" unsigned __int64 boopar$pq_fpswa;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __ long /* And set ptr size default to 64-bit pointers */W void *boopar$pq_efi_runtime_services; /* Address of EFI runtime service routines */#else1 unsigned __int64 boopar$pq_efi_runtime_services;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *boopar$pq_efi_system_table; /* Address of EFI system table */#else- unsigned __int64 boopar$p q_efi_system_table;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *boopar$pq_vcons_plabel0; /* Code address of vcons service */#else* unsigned __int64 boopar$pq_vcons_plabel0;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-b it pointers */N void *boopar$pq_vcons_plabel1; /* GP for vcons service */#else* unsigned __int64 boopar$pq_vcons_plabel1;#endifa __int64 boopar$q_min_bitmap_pfn; /* Lowest PFN described by the first allocation bitmap */b __int64 boopar$q_max_bitmap_pfn; /* Highest PFN described by the first allocation bitmap */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size defau lt to 64-bit pointers */N void *boopar$pq_shsba_plabel0; /* Code address of shsba service */#else* unsigned __int64 boopar$pq_shsba_plabel0;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *boopar$pq_shsba_plabel1; /* GP for shsba service */#else* unsigned __int64 boopar$pq_shsba_plabel1;#endifR#ifdef __INITIAL_POINTER _SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *boopar$pq_esi_table; /* Extensible SAL interface table */#else& unsigned __int64 boopar$pq_esi_table;#endifb __int64 boopar$q_min_bitmap_pfn2; /* Lowest PFN described by the second allocation bitmap */c __int64 boopar$q_max_bitmap_pfn2; /* Highest PFN described by the second allocation bitmap */R#ifdef __INITIAL _POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifQ void *boopar$l_pfn_map2; /* Address of second allocation bitmap */N int boopar$l_spare_3; /* */ } BOOPARAM; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_s ize __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BOOPARDEF_LOADED */ wwZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and  is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** author ized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************************************************* *************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */K/* Source: 16-APR-2022 21:52:51 $1$DGA8345:[LIB_H.SRC]BOOSTATEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE BOOSTATEDEF ***/#ifndef __BOOSTATEDEF_LOADED#define __BOOSTATEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __ nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !d efined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define BOOSTATE$M_SYSBOOT 0x1#define BOOSTATE$M_INIT 0x2#define BOOSTATE$M_SWAPPER 0x4#define BOOSTATE$M_SYSINIT 0x8#define BOOSTATE$M_STARTUP 0x10 #define BOOSTATE$M_PFN_INIT 0x20!#define BOOSTATE$M_POOL_INIT 0x40#define BOOSTATE$M_XQP 0x80#define BOOSTATE$M _RMS 0x100 #define BOOSTATE$M_CONSOLE 0x200%#define BOOSTATE$M_SPNLCK_AVAIL 0x400!#define BOOSTATE$M_NORDONLY 0x800&#define BOOSTATE$M_EXEC_SLICING 0x1000 #define BOOSTATE$M_OBJREG 0x2000"#define BOOSTATE$M_AUDITING 0x4000(#define BOOSTATE$M_OBJECT_SERVICE 0x8000'#define BOOSTATE$M_FOREIGN_BOOT 0x10000!#define BOOSTATE$M_LANACP 0x20000"#define BOOSTATE$M_SPARE_1 0x40000'#define BOOSTATE$M_STACONFIG_IP 0x80000&#define BOOSTATE$M_POOL_AVAIL 0x100000'#define BOOSTATE$M_SYSMUT_INIT 0x200 000)#define BOOSTATE$M_BUGCHECK_INIT 0x400000+#define BOOSTATE$M_JOINING_CLUSTER 0x800000,#define BOOSTATE$M_ENTROPY_RUNNING 0x1000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _boostate {#pragma __nomember_alignment __union { int boostate$l_bits; __struct {N unsigned boostate$v_sysboot : 1; /* SYSBOOT is executing */N unsigned boostate$v_init : 1; /* INIT is executing */S unsigned boostate$v_swapper : 1; /* The SWAPPER process is executing */S unsigned boostate$v_sysinit : 1; /* The SYSINIT process is executing */S unsigned boostate$v_startup : 1; /* The STARTUP process is executing */S unsigned boostate$v_pfn_init : 1; /* The PFN database is initialized */` unsigned boostate$v_pool_init : 1; /* Nonpaged pool - (only low level interfaces) */N unsigned boostate$v_xqp : 1; /* The XQP has been mapped */N unsigned boostate$v_rms : 1; /* RMS has been loaded */Q unsigned boostate$v_console : 1; /* Console routines are connected */S unsigned boostate$v_spnlck_avail : 1; /* Spinlock database available */N unsigned boostate$v_nordonly : 1; /* If set, EXEC should not be */N/* made read only.  */S unsigned boostate$v_exec_slicing : 1; /* If set, execlets should not */N/* sliced during load. */V unsigned boostate$v_objreg : 1; /* Security Object Registration enabled */[ unsigned boostate$v_auditing : 1; /* Security auditing subsystem initialized */] unsigned boostate$v_object_service : 1; /* Security object service initialized */] unsigned boost ate$v_foreign_boot : 1; /* If set, system disk is foreign to VMS */N unsigned boostate$v_lanacp : 1; /* If set, LANACP is started */N unsigned boostate$v_spare_1 : 1; /* was used for QIOserver */` unsigned boostate$v_staconfig_ip : 1; /* If set, STACONFIG Process is in progress */V unsigned boostate$v_pool_avail : 1; /* Nonpaged pool is fully available */b unsigned boostate$v_sysmut_init : 1; /* (IA64 only) System MUT has been initia lized */g unsigned boostate$v_bugcheck_init : 1; /* BUGCHECK has been initialized (can take dumps) */X unsigned boostate$v_joining_cluster : 1; /* In process of joining cluster */Y unsigned boostate$v_entropy_running : 1; /* Entropy service init complete. */, unsigned boostate$v_fill_0_ : 7;( } boostate$r_bits_structure; } boostate$r_bits_union; } BOOSTATE; #if !defined(__VAXC)=#define boostate$l_bits boostate$r_bits_un ion.boostate$l_bits]#define boostate$v_sysboot boostate$r_bits_union.boostate$r_bits_structure.boostate$v_sysbootW#define boostate$v_init boostate$r_bits_union.boostate$r_bits_structure.boostate$v_init]#define boostate$v_swapper boostate$r_bits_union.boostate$r_bits_structure.boostate$v_swapper]#define boostate$v_sysinit boostate$r_bits_union.boostate$r_bits_structure.boostate$v_sysinit]#define boostate$v_startup boostate$r_bits_union.boostate$r_bits_structure.boostate$v_startup_#define bo ostate$v_pfn_init boostate$r_bits_union.boostate$r_bits_structure.boostate$v_pfn_inita#define boostate$v_pool_init boostate$r_bits_union.boostate$r_bits_structure.boostate$v_pool_initU#define boostate$v_xqp boostate$r_bits_union.boostate$r_bits_structure.boostate$v_xqpU#define boostate$v_rms boostate$r_bits_union.boostate$r_bits_structure.boostate$v_rms]#define boostate$v_console boostate$r_bits_union.boostate$r_bits_structure.boostate$v_consoleg#define boostate$v_spnlck_avail boostate$r_bit s_union.boostate$r_bits_structure.boostate$v_spnlck_avail_#define boostate$v_nordonly boostate$r_bits_union.boostate$r_bits_structure.boostate$v_nordonlyg#define boostate$v_exec_slicing boostate$r_bits_union.boostate$r_bits_structure.boostate$v_exec_slicing[#define boostate$v_objreg boostate$r_bits_union.boostate$r_bits_structure.boostate$v_objreg_#define boostate$v_auditing boostate$r_bits_union.boostate$r_bits_structure.boostate$v_auditingk#define boostate$v_object_service boostate$r_bits_ union.boostate$r_bits_structure.boostate$v_object_serviceg#define boostate$v_foreign_boot boostate$r_bits_union.boostate$r_bits_structure.boostate$v_foreign_boot[#define boostate$v_lanacp boostate$r_bits_union.boostate$r_bits_structure.boostate$v_lanacp]#define boostate$v_spare_1 boostate$r_bits_union.boostate$r_bits_structure.boostate$v_spare_1g#define boostate$v_staconfig_ip boostate$r_bits_union.boostate$r_bits_structure.boostate$v_staconfig_ipc#define boostate$v_pool_avail boostate$r_bit s_union.boostate$r_bits_structure.boostate$v_pool_availe#define boostate$v_sysmut_init boostate$r_bits_union.boostate$r_bits_structure.boostate$v_sysmut_initi#define boostate$v_bugcheck_init boostate$r_bits_union.boostate$r_bits_structure.boostate$v_bugcheck_initm#define boostate$v_joining_cluster boostate$r_bits_union.boostate$r_bits_structure.boostate$v_joining_clusterm#define boostate$v_entropy_running boostate$r_bits_union.boostate$r_bits_structure.boostate$v_entropy_running"#endif /* # if !defined(__VAXC) */ #define BOOSTATE$S_BOOSTATEDEF 4 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __BOOSTATEDEF_LOADED */ wwZUM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */F/* Source: 20-DEC-2005 17:17:54 $1$DGA8345:[LIB_H.SRC]BPTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BPTDEF ***/#ifndef __BPTDEF_LOADED#define __BPTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #i fdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* + */ N/* */S/* Define bits which control which hardcoded calls to INI$BRK (the initial BPT) */N/* will be executed as a system is being booted. */N/* */N/* - */#define BPT$M_INITBEGIN 0x1#define BPT$M_INITEND 0x2#define BPT$M_SMPSTART 0x4#define BPT$ M_ANYMODE 0x8#define BPT$M_LDR_INIT 0x10#define BPT$M_PROCDUMP 0x20N#define BPT$S_BPTDEF 4 /* Old size name, synonym */ typedef struct _bpt { __union {N unsigned int bpt$l_bptmsk; /* Initial BPT enable mask */ __struct {N unsigned bpt$v_initbegin : 1; /* BRK at start of INIT */N unsigned bpt$v_initend : 1; /* BRK at end of INIT */N unsigned bpt$v_smpstart : 1; /* BRK at INIT call to setup SMP */N unsigned bpt$v_anymode : 1; /* Trap to XDELTA in any mode */O unsigned bpt$v_ldr_init : 1; /* BRK before calling init routines */S unsigned bpt$v_procdump : 1; /* Trap to XDELTA before a process dump */N/* is written (requires ANYMODE be set too) */' unsigned bpt$v_fill_2_ : 2; } bpt$r_fill_1_; } bpt$r_fill_0_; } BPT; #if !defined(__VAXC)C#defin e bpt$v_initbegin bpt$r_fill_0_.bpt$r_fill_1_.bpt$v_initbegin?#define bpt$v_initend bpt$r_fill_0_.bpt$r_fill_1_.bpt$v_initendA#define bpt$v_smpstart bpt$r_fill_0_.bpt$r_fill_1_.bpt$v_smpstart?#define bpt$v_anymode bpt$r_fill_0_.bpt$r_fill_1_.bpt$v_anymodeA#define bpt$v_ldr_init bpt$r_fill_0_.bpt$r_fill_1_.bpt$v_ldr_initA#define bpt$v_procdump bpt$r_fill_0_.bpt$r_fill_1_.bpt$v_procdump"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER _SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BPTDEF_LOADED */ ww$ZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential propriet ary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** pr oprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************* *************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */G/* Source: 19-DEC-1996 15:57:54 $1$DGA8345:[LIB_H.SRC]BRKTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BRKTDEF ***/#ifndef __BRKTDEF_LOADED#define __BRKTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI -Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params #define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* + */N/* */N/* Structure of breakthru message descriptor block. */N/* */N/* - */ #define BRK$M_LOCKED 0x1#define BRK$M_DONE 0x2#define BRK$M_CHKPRIV 0x4#define BRK$M_CHKUIC 0x8#define BRK$C_LENGTH 146`#define BRK$S_BRKTHRU_1 146 /* Old size field (when aggregate had different name) */  9#ifdef __cplusplus /* Define structure prototypes */ struct _pcb; struct _ucb; struct _ddb; #endif /* #ifdef __cplusplus */ typedef struct _brk {N/* */N/* Common Storage */N/* */N unsigned int brk$l_locpsbid; /* local PSB ID */N unsigned int brk$l_savpsbid; /* saved PSB ID */N unsigned short int brk$w_size; /* block size */N unsigned short int brk$w_outcnt; /* outstanding I/O count */N char brk$t_devname [16]; /* device name for $ASSIGN */N unsigned int brk$l_devuic; /* UIC of the terminal's owner */N struct _pcb *brk$l_pcb; /* Address of PCB */N void *brk$l_iosb; /* Address of return IOSB */N void (*brk$l_astadr)(); /* Address of AST routine */N unsigned int brk$l_astprm; /* Value of AST parameter */N unsigned __int64 brk$q_timeout; /* Timeout value */N unsigned int brk$l_carcon; /* carriage control */N unsigned int brk$l_flags; /* flags */N char brk$t_sendname [16]; /* username/terminal name  */N unsigned short int brk$w_sendtype; /* send descriptor type */N unsigned short int brk$w_seconds; /* Timeout in seconds */N unsigned int brk$l_reqid; /* send requestor ID */N/* */N/* miscellaneous context */N/* */N unsigned i nt brk$l_pidctx; /* Last PID in user search */N struct _ucb *brk$l_ucbctx; /* Last UCB in TTY search */N struct _ddb *brk$l_ddbctx; /* Last DDB in TTY search */N void *brk$l_qioctx; /* per QIO context address */N unsigned short int brk$w_efn; /* user event flag *BYTE***? */ __union {N unsigned char brk$b_sts; /* status flags */N __struct { /* status flags bit definition */N unsigned brk$v_locked : 1; /* I/O dataabse locked */N unsigned brk$v_done : 1; /* done looking for terminals */N unsigned brk$v_chkpriv : 1; /* check privilege */N unsigned brk$v_chkuic : 1; /* check UIC of terminal owner */' unsigned brk$v_fill_0_ : 4; } brk$r_sts_bits; } brk$r_sts_overlay;N unsigned char brk$b_pr vmode; /* previous mode */N unsigned int brk$l_scrmsglen; /* screen message length */N unsigned int brk$l_scrmsg; /* screen message address */N/* */N/* status block */N/* */N unsigned short int brk$w_status; /* status  */N unsigned short int brk$w_successcnt; /* Success count */N unsigned short int brk$w_timeoutcnt; /* Timeout count */N unsigned short int brk$w_refusedcnt; /* Refused count */N/* */N/* start of mailbox message */N/* */ N unsigned short int brk$w_trmmsg; /* mailbox message code */N unsigned short int brk$w_trmunit; /* tty unit number */N char brk$t_trmname [16]; /* terminal name */N/* */N/* real message starts here */N/* */N unsigned short int b rk$w_msglen; /* length of msgbuf */N/* */N/* Length */N/* */i char brk$t_msgbuf; /* start of message (Do not include in the length. This field */N/* marks the begining of the variable length buffer. It has a */N/* real size for C)  */ } BRK; #if !defined(__VAXC)-#define brk$b_sts brk$r_sts_overlay.brk$b_stsB#define brk$v_locked brk$r_sts_overlay.brk$r_sts_bits.brk$v_locked>#define brk$v_done brk$r_sts_overlay.brk$r_sts_bits.brk$v_doneD#define brk$v_chkpriv brk$r_sts_overlay.brk$r_sts_bits.brk$v_chkprivB#define brk$v_chkuic brk$r_sts_overlay.brk$r_sts_bits.brk$v_chkuic"#endif /* #if !defined(__VAXC) */   c#if !defined(__NOBASEALIGN_SUPPORT) && !def ined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _brk2 {N/* */N/* Per QIO storage */N/* */#pragma __nomember_alignmentN struct _brk *brk2$l_common; /* address of common area */N unsigned __int64 brk2$q_iosb; /* iosb for QIO */N unsigned short int brk2$w_chan; /* channel */N unsigned short int brk2$w_fill_1; /* For longword alignment of... */N/* subsequent & adjacent BRK2. */N/* */N/* Length of Per QIO context */N/*  */ } BRK2;#define BRK2$C_LENGTH 16`#define BRKTHRU_2$S_LENGTH 16 /* Old size field (when aggregate had different name) */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BRKTDEF_LOADED */ wwKZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE.  **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/ M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */H/* Source: 29-NOV-2017 12:37:47 $1$DGA8345:[LIB_H.SRC]BTADPDEF.SDL; 1 *//********************************************************************************************************************************//*** MODULE $btadpdef ***/#ifndef __BTADPDEF_LOADED#define __BTADPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the p reviously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __unio n union#else#define __union variant_union#endif#endif !#define BTADP$M_BOOTED_DEVICE 0x1#define BTADP$M_VALID 0x2#define BTADP$M_FOREIGN 0x4 #define BTADP$M_FOREIGN_PORT 0x8 #define BTADP$M_NO_HARDWARE 0x10#define BTADP$M_SKIP_DUMP 0x20##define BTADP$M_SECONDARY_BOOT 0x40 #define BTADP$M_HCDP_DEVICE 0x80%#define BTADP$M_HARDWARE_DEVICE 0x100 #define BTADP$M_MEMORYDISK 0x200 #define BTADP$M_UNIT_KNOWN 0x400 #define BTADP$M_SAS_DEVICE 0x800%#define BTADP$M_SAS_EXT_DEVI CE 0x1000##define BTADP$M_CISS_EXT_LUN 0x2000##define BTADP$M_CISS_INT_LUN 0x4000"#define BTADP$M_CONSOLE_OUT 0x8000"#define BTADP$M_CONSOLE_IN 0x10000##define BTADP$M_HW_BOOT_DEV 0x20000U#define BTADP$K_COMPARE_LEN 328 /* Length of that part of the BTADP to use */N/* when comparing against the Booted Device */N#define BTADP$K_IDE_CHAN_PRI 0 /* Primary Channel */N#define BTADP$K_IDE_CHAN_SEC 1 /* Secondary Channel */N#define BTADP$K_IDE_DRIVE_MASTER 0 /* Master Drive */N#define BTADP$K_IDE_DRIVE_SLAVE 1 /* Slave Driver */N#define BTADP$C_LENGTH 464 /* Length Of Btadp */N#define BTADP$K_LENGTH 464 /* Length Of Btadp */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DE CC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _btadp {#pragma __nomember_alignment __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *btadp$pq_flink; /* BTADP forward link */#else! unsigned __int64 btadp$pq_flink;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif# void *btadp$pl_flink_l;* unsigned int btadp$il_flink_h;# } btadp$r_flink_fields; } btadp$r_flink_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size d efault to 64-bit pointers */N void *btadp$pq_blink; /* BTADP backward link */#else! unsigned __int64 btadp$pq_blink;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif# void *btadp$pl_blink_l;* unsigned int btadp$il_blink_h;# } btadp$r_blink_fields; } btadp$ r_blink_overlay; __union {N unsigned __int64 btadp$iq_devtype; /* Bootstrap Device Type */ __struct {, unsigned int btadp$il_devtype_l;, unsigned int btadp$il_devtype_h;% } btadp$r_devtype_fields;" } btadp$r_devtype_overlay; __union {N unsigned __int64 btadp$iq_unit; /* Boot Device Unit Number */ __struct {) unsigned int btadp$il_unit_l;) unsigned int btadp$il_unit_h ;" } btadp$r_unit_fields; } btadp$r_unit_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *btadp$pq_csrphy; /* Phys. Csr Addr. Of Boot Dev */#else" unsigned __int64 btadp$pq_csrphy;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#p ragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif$ void *btadp$pl_csrphy_l;+ unsigned int btadp$il_csrphy_h;$ } btadp$r_csrphy_fields;! } btadp$r_csrphy_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *btadp$pq_csrvir; /* Virtual Csr A ddr. Of Boot Dev */#else" unsigned __int64 btadp$pq_csrvir;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif$ void *btadp$pl_csrvir_l;+ unsigned int btadp$il_csrvir_h;$ } btadp$r_csrvir_fields;! } btadp$r_csrvir_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined when ever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *btadp$pq_adpphy; /* Phys. Csr Addr. Of Boot Adp */#else" unsigned __int64 btadp$pq_adpphy;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif$ void *btadp$pl_adpphy_l;+ unsigned int btadp$il_adpphy_h;$ } btadp$r_adpphy_fields;! } btadp$r_adpphy_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *btadp$pq_adpvir; /* Virtual Csr Addr. Of Boot Adp */#else" unsigned __int64 btadp$pq_adpvir;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defi ned whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif$ void *btadp$pl_adpvir_l;+ unsigned int btadp$il_adpvir_h;$ } btadp$r_adpvir_fields;! } btadp$r_adpvir_overlay; __union {N unsigned __int64 btadp$iq_bootndt; /* Nexus Device Type Of Boot */N __struct { /* Device */, unsigned int b tadp$il_bootndt_l;, unsigned int btadp$il_bootndt_h;% } btadp$r_bootndt_fields;" } btadp$r_bootndt_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *btadp$pq_node_space_addr; /* SVA of node space */#else+ unsigned __int64 btadp$pq_node_space_addr;#endif __struct {R#ifdef _ _INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif- void *btadp$pl_node_space_addr_l;4 unsigned int btadp$il_node_space_addr_h;- } btadp$r_node_space_addr_fields;* } btadp$r_node_space_addr_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __ long /* And set ptr size default to 64-bit pointers */N void *btadp$pq_bdtab; /* Pointer to BDTAB */#else! unsigned __int64 btadp$pq_bdtab;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif# void *btadp$pl_bdtab_l;* unsigned int btadp$il_bdtab_h;# } btadp$r_bdta b_fields; } btadp$r_bdtab_overlay; __union {N __int64 btadp$iq_protocol; /* */ __struct {- unsigned int btadp$il_protocol_l;- unsigned int btadp$il_protocol_h;& } btadp$r_protocol_fields;# } btadp$r_protocol_overlay; __union {N __int64 btadp$iq_hose; /* */ __struct {) unsigned int btadp$il_hose_l;) unsigned int btadp$il_hose_h;" } btadp$r_hose_fields; } btadp$r_hose_overlay; __union {N __int64 btadp$iq_slot; /* XMI/FBUS slot */ __struct {) unsigned int btadp$il_slot_l;) unsigned int btadp$il_slot_h;" } btadp$r_slot_fields; } btadp$r_slot_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_poi nter_size __long /* And set ptr size default to 64-bit pointers */N void *btadp$pq_remote_addr; /* remote addr (eg. XZA) */#else' unsigned __int64 btadp$pq_remote_addr;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif) void *btadp$pl_remote_addr_l;0 unsigned int btadp$il_remote_addr_ h;) } btadp$r_remote_addr_fields;& } btadp$r_remote_addr_overlay; __union {N __int64 btadp$iq_chan; /* Channel */ __struct {) unsigned int btadp$il_chan_l;) unsigned int btadp$il_chan_h;" } btadp$r_chan_fields; } btadp$r_chan_overlay; __union {N __int64 btadp$iq_bus_type; /* Bus type value */ __struct {- unsigned int btadp$il_bus_type_l;- unsigned int btadp$il_bus_type_h;& } btadp$r_bus_type_fields;# } btadp$r_bus_type_overlay; __union {N __int64 btadp$iq_dma_map_register; /* Base DMA mapping register */ __struct {5 unsigned int btadp$il_dma_map_register_l;5 unsigned int btadp$il_dma_map_register_h;. } btadp$r_dma_map_register_fields;+ } btadp$r_dma_map_register_overlay;N/*  */B/* Define the fields used to control the device name. */N/* */N/* */I/* NOTE: There is code within the boot path that is dependent on the */J/* order of the fields from MSCP_SLUN through RSRVD. If you */I/* need to add fields, please do so after the RSRVD field. */N/* */O unsigned __int64 btadp$iq_mscp_slun; /* TMSCP/MSCP SLUN for this device. */p char btadp$t_device_name [32]; /* Counted string. Remote device name. Used for NISCA booting only. */] char btadp$t_node_name [16]; /* Counted string. Remote system's SCS node name. */S unsigned __int64 btadp$iq_scssystemid; /* Remote system's SCSSYSTEMID value. */a char btadp$t_controller_prefix [8]; /* Counted string. Remote device's controller prefix. */^ unsigned char btadp$b_controller_letter; /* Remote device's controller letter in ASCII. */ char btadp$b_rsrvd1 [7];a unsigned int btadp$il_dumpdev_order; /* The placement of this device in the DUMP_DEV list. */N/* ie. (first (1), second (2), etc. */p char btadp$t_pseudo_devnam [4]; /* Counted string. Pseudo driver prefix. Used for MOP devices only. */N/* This should NOT exceed 1 char for count and 3 for DEVNAM */ __union {N __int64 btadp$iq_flags; /* Flags */ __struct {* unsigned int btadp$il_flags_l;* unsigned int btadp$il_flags_h;% } btadp$r_flag_longwords; __struct {_ unsigned btadp$v_booted_device : 1; /* is this the boot device (See note below) */N unsigned btadp$v_valid : 1; /* BTADP validity */O unsi gned btadp$v_foreign : 1; /* this device is a foreign class */S unsigned btadp$v_foreign_port : 1; /* this device is a foreign port */` unsigned btadp$v_no_hardware : 1; /* this device is not associated with hardware */\ unsigned btadp$v_skip_dump : 1; /* the device should not be used for dumping */` unsigned btadp$v_secondary_boot : 1; /* this device is the secondary boot device */W unsigned btadp$v_hcdp_device : 1; /* Headless Conso le Debug Port device */h unsigned btadp$v_hardware_device : 1; /* Actual hardware device when booting memory disk */N/* (See note below) */a unsigned btadp$v_memorydisk : 1; /* this device is a memory disk (See note below) */[ unsigned btadp$v_unit_known : 1; /* BUGCHECK has determined the unit number */O unsigned btadp$v_sas_device : 1; /* this device is a SAS device */\ unsign ed btadp$v_sas_ext_device : 1; /* this device is a SAS external device */W unsigned btadp$v_ciss_ext_lun : 1; /* CISS external Raid controller LUN */j unsigned btadp$v_ciss_int_lun : 1; /* CISS internal Raid controller LUN for RAW (HBA) mode */O unsigned btadp$v_console_out : 1; /* boot console output device */N unsigned btadp$v_console_in : 1; /* boot console input device */f unsigned btadp$v_hw_boot_dev : 1; /* The actual HW device when booting via memory disk */N/* (used by EXEC_INIT to track which device is which) */N/* (See note below) */) unsigned btadp$v_fill_0_ : 6;# } btadp$r_flags_fields; } btadp$r_flags_overlay;T int btadp$il_alloclass; /* port allocation class for SCSI devices */d unsigned int btadp$il_dumpdev_skipped; /* The number of dump devices which are not valid dump */N/* devic es before we found this device. */O int btadp$l_pathname_len; /* length of console pathname string */U char btadp$t_pathname [76]; /* console pathname string for this device */N/* Block within the Select Bootdriver routine. */I/* Define fibre channel world-wide identifier (WWID) index. */I/* This is obtained from the console in a BOOT_DEV or BOOTED_DEV */I/* string in the format: @WWIDn, where n is the WWID index. */I/* If there is no @WWIDn specifier in the string, then APB */I/* stores -1 in this field. */N int btadp$l_wwid_index; /* World-wide identifier index */I/* Define fibre channel Target ID and LUN. If unavailable from the */I/* console, then set them to -1. They are both quadword fields but */J/* are split into _L and _H longwords so that BLISS-32 can handle them. */  char btadp$b_fill_1_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentb __int64 btadp$q_target_id; /* 24-bit fibre channel destination ID, including AL-PA */ __struct {$ int btadp$l_target_id_l;$ int btadp$l_target_id_h;' } btadp$r_target_id_fields;$ } btadp$r_target_id_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 btadp$q_lun; /* SCSI Logical Unit Number */ __struct { int btadp$l_lun_l; int btadp$l_lun_h;! } btadp$r_lun_fields; } btadp$r_lun_overlay; T __int64 btadp$q_hw_channel; /* Channel number assigned to boot device */N int btadp$l_hsz_alloclass; /* Allocation class from HSZ70/80 */ int btadp$l_rsrvd2;N/* */N/* QIOSERVER booting */N/* */O unsigned __int64 btadp$q_qslun; /* QIOSERVER QSLUN for remote de vice */O unsigned int btadp$l_rtdriver_class_len; /* length of driver name string */N char btadp$t_rtdriver_class [16]; /* length of driver name string */N/* Verified for X86, Dave Fairbanks */N/* */N/* */B/* Define ATA/ATAPI IDE fields */N/*  */V unsigned int btadp$l_ide_chan_pri; /* 0:Primary Channel 1: Secondary Channel */T unsigned int btadp$l_ide_drive_master; /* 0: Master Drive 1: Slave Drive */R unsigned int btadp$l_ide_lun; /* ATA Logical Unit Number (Serial ATA) */N unsigned int btadp$l_ide_pio; /* PIO mode setting */N unsigned int btadp$l_ide_dma; /* DMA mode setting */ __union {R#ifdef __INITIAL_P OINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *btadp$pq_port_chan; /* port boot driver */#else% unsigned __int64 btadp$pq_port_chan;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif' void *btadp$pl_port_chan_l;. unsigned int btadp$il_port_chan_h;' } btadp$r_port_chan_fields;$ } btadp$r_port_chan_overlay;N/* */N/* */F/* Define Fields required for Cell-Based Boot/Crash Driver Support */N/* */ __union {N __in t64 btadp$iq_hid; /* ACPI Hardware ID */ __struct {( unsigned int btadp$il_hid_l;( unsigned int btadp$il_hid_h;! } btadp$r_hid_fields; } btadp$r_hid_overlay; __union {N __int64 btadp$iq_uid; /* ACPI Unique ID */ __struct {( unsigned int btadp$il_uid_l;( unsigned int btadp$il_uid_h;! } btadp$r_uid_fields; } btadp$r_uid_over lay; __union {N/* */N/* The TRA_OFFSET identifier is being deprecated in favor of */N/* the TRA_MMIO identifier, since we need a TRA for Port IO */N/* space as well. */N/* */N unsigned __int64 btadp$iq_tra_mmio; /* New Name */N unsigned __int64 btadp$iq_tra_offset; /* TRanslation Addreess */# } btadp$r_tra_mmio_overlay; __union {& __int64 btadp$iq_pci_cfg_data;$ void *btadp$pl_pci_cfg_data; } btadp$r_bus_specific;N/* */N/* This field will contain the TRA for Port IO addresses. */N/* */) unsigned __int64 bta dp$iq_tra_portio;N/* */B/* Define the minimum BTADP data structure length. */N/* */B/* Define the LAN boot driver fields. */N/* */B/* Transmit and receive control variables. */N/* */ } BTADP; #if !defined(__VAXC);#define btadp$pq_flink btadp$r_flink_overlay.btadp$pq_flinkT#define btadp$pl_flink_l btadp$r_flink_overlay.btadp$r_flink_fields.btadp$pl_flink_lT#define btadp$il_flink_h btadp$r_flink_overlay.btadp$r_flink_fields.btadp$il_flink_h;#define btadp$pq_blink btadp$r_blink_overlay.btadp$pq_blinkT#define btadp$pl_blink_l btadp$r_blink_overlay.btadp$r_blink_fields.btadp$pl_blink_lT#define btadp$il_blink_h btadp$r_blink_overlay .btadp$r_blink_fields.btadp$il_blink_hA#define btadp$iq_devtype btadp$r_devtype_overlay.btadp$iq_devtype\#define btadp$il_devtype_l btadp$r_devtype_overlay.btadp$r_devtype_fields.btadp$il_devtype_l\#define btadp$il_devtype_h btadp$r_devtype_overlay.btadp$r_devtype_fields.btadp$il_devtype_h8#define btadp$iq_unit btadp$r_unit_overlay.btadp$iq_unitP#define btadp$il_unit_l btadp$r_unit_overlay.btadp$r_unit_fields.btadp$il_unit_lP#define btadp$il_unit_h btadp$r_unit_overlay.btadp$r_unit_fields.btadp $il_unit_h>#define btadp$pq_csrphy btadp$r_csrphy_overlay.btadp$pq_csrphyX#define btadp$pl_csrphy_l btadp$r_csrphy_overlay.btadp$r_csrphy_fields.btadp$pl_csrphy_lX#define btadp$il_csrphy_h btadp$r_csrphy_overlay.btadp$r_csrphy_fields.btadp$il_csrphy_h>#define btadp$pq_csrvir btadp$r_csrvir_overlay.btadp$pq_csrvirX#define btadp$pl_csrvir_l btadp$r_csrvir_overlay.btadp$r_csrvir_fields.btadp$pl_csrvir_lX#define btadp$il_csrvir_h btadp$r_csrvir_overlay.btadp$r_csrvir_fields.btadp$il_csrvir_h>#defin e btadp$pq_adpphy btadp$r_adpphy_overlay.btadp$pq_adpphyX#define btadp$pl_adpphy_l btadp$r_adpphy_overlay.btadp$r_adpphy_fields.btadp$pl_adpphy_lX#define btadp$il_adpphy_h btadp$r_adpphy_overlay.btadp$r_adpphy_fields.btadp$il_adpphy_h>#define btadp$pq_adpvir btadp$r_adpvir_overlay.btadp$pq_adpvirX#define btadp$pl_adpvir_l btadp$r_adpvir_overlay.btadp$r_adpvir_fields.btadp$pl_adpvir_lX#define btadp$il_adpvir_h btadp$r_adpvir_overlay.btadp$r_adpvir_fields.btadp$il_adpvir_hA#define btadp$iq_bootndt btadp$r_bootndt_overlay.btadp$iq_bootndt\#define btadp$il_bootndt_l btadp$r_bootndt_overlay.btadp$r_bootndt_fields.btadp$il_bootndt_l\#define btadp$il_bootndt_h btadp$r_bootndt_overlay.btadp$r_bootndt_fields.btadp$il_bootndt_hY#define btadp$pq_node_space_addr btadp$r_node_space_addr_overlay.btadp$pq_node_space_addr|#define btadp$pl_node_space_addr_l btadp$r_node_space_addr_overlay.btadp$r_node_space_addr_fields.btadp$pl_node_space_addr_l|#define btadp$il_node_space_addr_h btadp$r_node_space_ad dr_overlay.btadp$r_node_space_addr_fields.btadp$il_node_space_addr_h;#define btadp$pq_bdtab btadp$r_bdtab_overlay.btadp$pq_bdtabT#define btadp$pl_bdtab_l btadp$r_bdtab_overlay.btadp$r_bdtab_fields.btadp$pl_bdtab_lT#define btadp$il_bdtab_h btadp$r_bdtab_overlay.btadp$r_bdtab_fields.btadp$il_bdtab_hD#define btadp$iq_protocol btadp$r_protocol_overlay.btadp$iq_protocol`#define btadp$il_protocol_l btadp$r_protocol_overlay.btadp$r_protocol_fields.btadp$il_protocol_l`#define btadp$il_protocol_h btadp$ r_protocol_overlay.btadp$r_protocol_fields.btadp$il_protocol_h8#define btadp$iq_hose btadp$r_hose_overlay.btadp$iq_hoseP#define btadp$il_hose_l btadp$r_hose_overlay.btadp$r_hose_fields.btadp$il_hose_lP#define btadp$il_hose_h btadp$r_hose_overlay.btadp$r_hose_fields.btadp$il_hose_h8#define btadp$iq_slot btadp$r_slot_overlay.btadp$iq_slotP#define btadp$il_slot_l btadp$r_slot_overlay.btadp$r_slot_fields.btadp$il_slot_lP#define btadp$il_slot_h btadp$r_slot_overlay.btadp$r_slot_fields.btadp$il_slot_h M#define btadp$pq_remote_addr btadp$r_remote_addr_overlay.btadp$pq_remote_addrl#define btadp$pl_remote_addr_l btadp$r_remote_addr_overlay.btadp$r_remote_addr_fields.btadp$pl_remote_addr_ll#define btadp$il_remote_addr_h btadp$r_remote_addr_overlay.btadp$r_remote_addr_fields.btadp$il_remote_addr_h8#define btadp$iq_chan btadp$r_chan_overlay.btadp$iq_chanP#define btadp$il_chan_l btadp$r_chan_overlay.btadp$r_chan_fields.btadp$il_chan_lP#define btadp$il_chan_h btadp$r_chan_overlay.btadp$r_chan_fields .btadp$il_chan_hD#define btadp$iq_bus_type btadp$r_bus_type_overlay.btadp$iq_bus_type`#define btadp$il_bus_type_l btadp$r_bus_type_overlay.btadp$r_bus_type_fields.btadp$il_bus_type_l`#define btadp$il_bus_type_h btadp$r_bus_type_overlay.btadp$r_bus_type_fields.btadp$il_bus_type_h\#define btadp$iq_dma_map_register btadp$r_dma_map_register_overlay.btadp$iq_dma_map_register#define btadp$il_dma_map_register_l btadp$r_dma_map_register_overlay.btadp$r_dma_map_register_fields.btadp$il_dma_map_register_l #define btadp$il_dma_map_register_h btadp$r_dma_map_register_overlay.btadp$r_dma_map_register_fields.btadp$il_dma_map_register_h;#define btadp$iq_flags btadp$r_flags_overlay.btadp$iq_flagsV#define btadp$il_flags_l btadp$r_flags_overlay.btadp$r_flag_longwords.btadp$il_flags_lV#define btadp$il_flags_h btadp$r_flags_overlay.btadp$r_flag_longwords.btadp$il_flags_h^#define btadp$v_booted_device btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_booted_deviceN#define btadp$v_valid btadp$r_flags_over lay.btadp$r_flags_fields.btadp$v_validR#define btadp$v_foreign btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_foreign\#define btadp$v_foreign_port btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_foreign_portZ#define btadp$v_no_hardware btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_no_hardwareV#define btadp$v_skip_dump btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_skip_dump`#define btadp$v_secondary_boot btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_secondary_bootZ#define bt adp$v_hcdp_device btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_hcdp_deviceb#define btadp$v_hardware_device btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_hardware_deviceX#define btadp$v_memorydisk btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_memorydiskX#define btadp$v_unit_known btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_unit_knownX#define btadp$v_sas_device btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_sas_device`#define btadp$v_sas_ext_device btadp$r_flags_overlay.b tadp$r_flags_fields.btadp$v_sas_ext_device\#define btadp$v_ciss_ext_lun btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_ciss_ext_lun\#define btadp$v_ciss_int_lun btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_ciss_int_lunZ#define btadp$v_console_out btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_console_outX#define btadp$v_console_in btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_console_inZ#define btadp$v_hw_boot_dev btadp$r_flags_overlay.btadp$r_flags_fields.btadp$v_hw_boot_devE #define btadp$q_target_id btadp$r_target_id_overlay.btadp$q_target_idb#define btadp$l_target_id_l btadp$r_target_id_overlay.btadp$r_target_id_fields.btadp$l_target_id_lb#define btadp$l_target_id_h btadp$r_target_id_overlay.btadp$r_target_id_fields.btadp$l_target_id_h3#define btadp$q_lun btadp$r_lun_overlay.btadp$q_lunJ#define btadp$l_lun_l btadp$r_lun_overlay.btadp$r_lun_fields.btadp$l_lun_lJ#define btadp$l_lun_h btadp$r_lun_overlay.btadp$r_lun_fields.btadp$l_lun_hG#define btadp$pq_port_chan b tadp$r_port_chan_overlay.btadp$pq_port_chand#define btadp$pl_port_chan_l btadp$r_port_chan_overlay.btadp$r_port_chan_fields.btadp$pl_port_chan_ld#define btadp$il_port_chan_h btadp$r_port_chan_overlay.btadp$r_port_chan_fields.btadp$il_port_chan_h5#define btadp$iq_hid btadp$r_hid_overlay.btadp$iq_hidL#define btadp$il_hid_l btadp$r_hid_overlay.btadp$r_hid_fields.btadp$il_hid_lL#define btadp$il_hid_h btadp$r_hid_overlay.btadp$r_hid_fields.btadp$il_hid_h5#define btadp$iq_uid btadp$r_uid_overlay.bta  dp$iq_uidL#define btadp$il_uid_l btadp$r_uid_overlay.btadp$r_uid_fields.btadp$il_uid_lL#define btadp$il_uid_h btadp$r_uid_overlay.btadp$r_uid_fields.btadp$il_uid_hD#define btadp$iq_tra_mmio btadp$r_tra_mmio_overlay.btadp$iq_tra_mmioH#define btadp$iq_tra_offset btadp$r_tra_mmio_overlay.btadp$iq_tra_offsetH#define btadp$iq_pci_cfg_data btadp$r_bus_specific.btadp$iq_pci_cfg_dataH#define btadp$pl_pci_cfg_data btadp$r_bus_specific.btadp$pl_pci_cfg_data"#endif /* #if !defined(__VAXC) */ N/* */N/* Define the minimum BTADP data structure length required for LAN devices. */N/* */#define BTADP$S_BTADPDEF 464#define BTADP$K_LAN_LENGTH 464#define BTADP$C_LAN_LENGTH 464N/* Verified for x86 port--Drew Mason */ #ifdef __INITIAL_POINTER_SIZE$#pragma __required_pointer_size save$#pragma __required_point er_size longtypedef BTADP * BTADP_PQ;%#pragma __required_pointer_size shorttypedef BTADP * BTADP_PL;'#pragma __required_pointer_size restore#else"typedef unsigned __int64 BTADP_PQ;"typedef unsigned __int32 BTADP_PL;#endif $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#end if#pragma __standard #endif /* __BTADPDEF_LOADED */ wwZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written  permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Soft ware, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */F/* Source: 18-SEP-2003 16:34:16 $  1$DGA8345:[LIB_H.SRC]BTBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BTBDEF ***/#ifndef __BTBDEF_LOADED#define __BTBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_s ize __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defin  ed(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define BTB$K_VAX_SECTOR 0 /* address of VAX bootblock LBN */N#define BTB$K_ALPHA_SECTOR 0 /* address of Alpha bootblock LBN */N#define BTB$K_LENGTH_PART1 480 /* Length of 1st part of boot block */#define BTB$M_NOTCONTIG 0x1N#define BTB$K_LENGTH 512 /* Length of a boot block */N#define BTB$S_BTBDEF 512 /* Old size name, sy  nonym */ typedef struct _btb {N unsigned char btb$b_nop1; /* Contains NOP opcode */N unsigned char btb$b_brb; /* Contains BRB opcode */S unsigned char btb$b_brb_offset; /* Contains PC relative offset of branch */N unsigned char btb$b_nop2; /* Contains NOP opcode */ __union {N int btb$l_lbn1; /* Starting LBN of 1st boot file */ __struct {N un signed short int btb$w_high_lbn; /* High 32-bits of LBN */N unsigned short int btb$w_low_lbn; /* Low 32-bits of LBN */ } btb$r_lbn1_fields; } btb$r_lbn1_overlay;N int btb$l_fill1; /* Filler */N unsigned char btb$b_vax_brb; /* Contains BRB opcode (VAX) */S unsigned char btb$b_vax_offset; /* Contains PC relative offset of branch */N char btb$b_fill2; /* Fille r */N unsigned char btb$b_pdp_brb; /* Contain BRB opcode (PDP) */S unsigned char btb$b_pdp_offset; /* Contains PC relative offset of branch */N char btb$b_fill3; /* Filler */N int btb$l_fill4; /* Filler */N short int btb$w_fill5; /* Filler */N unsigned char btb$b_inst_set; /* Instruction set code (%x1 8=VAX) */N unsigned char btb$b_ctrl_type; /* Controller type */N unsigned char btb$b_file_str; /* File structure (ODS-II =2) */S unsigned char btb$b_comp3; /* Complement of sum of previous 3 bytes */N char btb$b_fill6; /* Filler */N unsigned char btb$b_version; /* Boot block version=1 */N short int btb$w_fill7; /* Filler */N unsi gned int btb$l_size; /* Size in LBNs of image */N unsigned int btb$l_load_offset; /* Load offset into good memory */N unsigned int btb$l_start_offset; /* Offset to begin execution */R unsigned int btb$l_checksum; /* Checksum of three previous longwords */ __union {N char btb$b_vax_code [92]; /* VAX boot block code */ __struct {N int btb$l_stuff; /*  */N int btb$l_more_stuff; /* */N char btb$t_comment [20]; /* */ } btb$r_code_fields; } btb$r_code_overlay;N char btb$b_fill8 [340]; /* Reserved for future use */ __union {N __int64 btb$q_size2; /* Size of 2nd boot file */ __struct {N int btb$l_low_size2; /* Low 32-bits of size  */N int btb$l_high_size2; /* High 32-bits of size */! } btb$r_size2_fields; } btb$r_size2_overlay; __union {N __int64 btb$q_lbn2; /* Starting LBN of 2nd boot file */ __struct {N int btb$l_low_lbn2; /* Low 32-bits of LBN */N int btb$l_high_lbn2; /* High 32-bits of LBN */ } btb$r_lbn2_fields; } btb$r_lbn2_overlay; __un  ion {N unsigned __int64 btb$q_flags; /* Boot block flags */ __struct {N unsigned int btb$l_low_flags; /* Low longword of flags */N unsigned int btb$l_high_flags; /* High longword of flags */! } btb$r_flag_fields1; __struct {N unsigned btb$v_notcontig : 1; /* Bootstrap is not contiguous */' unsigned btb$v_fill_0_ : 7; } btb$r_flag_fields; } btb$r_flags_  overlay; __union {N __int64 btb$q_checksum2; /* Checksum of entire block */ __struct {N int btb$l_low_check2; /* Low 32-bits of checksum */N int btb$l_high_check2; /* High 32-bits of checksum */% } btb$r_checksum2_fields;" } btb$r_checksum2_overlay; } BTB; #if !defined(__VAXC)0#define btb$l_lbn1 btb$r_lbn1_overlay.btb$l_lbn1J#define btb$w_high_lbn btb$r_lbn1_overlay.btb$r_lbn1_f ields.btb$w_high_lbnH#define btb$w_low_lbn btb$r_lbn1_overlay.btb$r_lbn1_fields.btb$w_low_lbn8#define btb$b_vax_code btb$r_code_overlay.btb$b_vax_codeD#define btb$l_stuff btb$r_code_overlay.btb$r_code_fields.btb$l_stuffN#define btb$l_more_stuff btb$r_code_overlay.btb$r_code_fields.btb$l_more_stuffH#define btb$t_comment btb$r_code_overlay.btb$r_code_fields.btb$t_comment3#define btb$q_size2 btb$r_size2_overlay.btb$q_size2N#define btb$l_low_size2 btb$r_size2_overlay.btb$r_size2_fields.btb$l_low_s ize2P#define btb$l_high_size2 btb$r_size2_overlay.btb$r_size2_fields.btb$l_high_size20#define btb$q_lbn2 btb$r_lbn2_overlay.btb$q_lbn2J#define btb$l_low_lbn2 btb$r_lbn2_overlay.btb$r_lbn2_fields.btb$l_low_lbn2L#define btb$l_high_lbn2 btb$r_lbn2_overlay.btb$r_lbn2_fields.btb$l_high_lbn23#define btb$q_flags btb$r_flags_overlay.btb$q_flagsN#define btb$l_low_flags btb$r_flags_overlay.btb$r_flag_fields1.btb$l_low_flagsP#define btb$l_high_flags btb$r_flags_overlay.btb$r_flag_fields1.btb$l_high_flags  M#define btb$v_notcontig btb$r_flags_overlay.btb$r_flag_fields.btb$v_notcontig?#define btb$q_checksum2 btb$r_checksum2_overlay.btb$q_checksum2X#define btb$l_low_check2 btb$r_checksum2_overlay.btb$r_checksum2_fields.btb$l_low_check2Z#define btb$l_high_check2 btb$r_checksum2_overlay.btb$r_checksum2_fields.btb$l_high_check2"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __ required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BTBDEF_LOADED */ ww0ZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Develop ment, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not ** /M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************************************** ***************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 20-JAN-1992 09:25:06 $1$DGA8345:[LIB_H.SRC]BTDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BTDDEF ***/#ifndef __BTDDEF_LOADED#define __BTDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nome! mber_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defin" ed(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Boot device codes */N/* # */N/*- */N/* "$K_" added, 8/30/79, CHP */N#define BTD$K_MB 0 /* Massbus device */N/* Types 1-31. reserved for */N/* Unibus(Qbus) devices */N#define BTD$K_DM 1 /* RK06/7 $ */N#define BTD$K_DL 2 /* RL02 */N#define BTD$K_DQ 3 /* RB02/RB80 */N#define BTD$K_PROM 8 /* PROM (not copied) */N#define BTD$K_PROM_COPY 9 /* PROM copied (Mayflower) */N#define BTD$K_UDA 17 /* UDA */N#define BTD$K_TK50 18 /* TK50 (MAYA) */N#define BTD$K_% KFQSA 19 /* KFQSA */N#define BTD$K_QBUS_SCSI 20 /* Qbus SCSI adapter */N/* End of Unibus(Qbus) devices */N#define BTD$K_HSCCI 32 /* HSC on CI */N#define BTD$K_BDA 33 /* BI disk adapter */N#define BTD$K_BVPSSP 34 /* BVP Storage Systems ports */N#define BTD$K_AIE_TK50 35 & /* AIE/TK50 port */N#define BTD$K_ST506_DISK 36 /* ST506 disk (PVAX/VAXstar) */N#define BTD$K_KA410_DISK 36 /* VAXstar ST506 disk */N#define BTD$K_KA420_DISK 36 /* PVAX ST506 disk */O#define BTD$K_SCSI_5380_TAPE 37 /* NCR 5380 SCSI tape (PVAX/VAXstar) */N#define BTD$K_KA410_TAPE 37 /* VAXstar SCSI tape */N#define BTD$K_KA420_TAPE 37 /* PVAX SCSI tape ' */N#define BTD$K_DISK9 38 /* Disk on 009 */N#define BTD$K_SII 39 /* Embedded DSSI controller */N#define BTD$K_SHAC 41 /* Single chip DSSI adapter. */N#define BTD$K_SCSI_5380_DISK 42 /* NCR 5380 SCSI disk (PVAX) */#define BTD$K_HSX 43#define BTD$K_KDM70 43#define BTD$K_HSXTAPE 44#define BTD$K_KDM70TAPE 44U#define BTD$K_SWIFT 45 /* Another embedded DSSI contr ( oller-CIRRUS */ #define BTD$K_SCSI_53C94_DISK 46 #define BTD$K_SCSI_53C94_TAPE 47N#define BTD$K_CONSOLE 64 /* Console block storage device */N/* Network boot devices (96-103) */N#define BTD$K_NET_DLL 96 /* Start of network boot devices */N/* Codes 96-127 reserved */N#define BTD$K_QNA 96 /* DEQNA */N#define BTD$K_UNA 97) /* DEUNA */N#define BTD$K_AIE_NI 98 /* AIE/NI */N#define BTD$K_LANCE 99 /* LANCE NI chip */N#define BTD$K_KA410_NI 99 /* VAXstar NI (LANCE chip) */N#define BTD$K_KA420_NI 99 /* PVAX NI (LANCE chip) */N#define BTD$K_SGEC 100 /* SGEC chip */N#define BTD$K_SERVER_DEBNA 101 /* NI-* CDROM server */N#define BTD$K_SERVER_DEBNI 102 /* NI-CDROM server */N#define BTD$K_SERVER_XNA 103 /* NI-CDROM server */N#define BTD$K_DEBNI 104 /* DEBNI */N#define BTD$K_DEMNA 105 /* DEMNA */N#define BTD$K_KA520_NI 106 /* CIRRUS NI */N#define BTD$K_SERVER_QNA 107 /* NI-CDROM server + */N#define BTD$K_SERVER_AIE_NI 108 /* NI-CDROM server */N#define BTD$K_SERVER_LANCE 109 /* NI-CDROM server */N#define BTD$K_SERVER_SGEC 110 /* NI-CDROM server */N#define BTD$K_SERVER_KA520_NI 111 /* NI-CDROM server */N#define BTD$K_DEMFA 112 /* DEMFA */N#define BTD$K_SERVER_DEMFA 113 /* NI-CDROM server */N#define BTD$K_DEFZ, A 114 /* DEFZA */N#define BTD$K_SERVER_DEFZA 115 /* NI-CDROM server */N#define BTD$K_PMAD 116 /* PMAD */N#define BTD$K_SERVER_PMAD 117 /* NI-CDROM server */N#define BDT$K_TGEC 118 /* TGEC ethernet chip */N#define BTD$K_SERVER_TGEC 119 /* NI-CDROM server */N#define BDT$K_DEANA 120 /* F - uturebus to Ethernet */N#define BTD$K_SERVER_DEANA 121 /* NI-CDROM server */N#define BTD$K_NETWORK_BOOT 128 /* Generic boot over NI */N#define BTD$K_NISCS 128 /* SCS disk over NI */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#end. if#ifdef __cplusplus }#endif#pragma __standard #endif /* __BTDDEF_LOADED */ ww@6ZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone wit/ hout the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the pr0 ior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */H 1 /* Source: 25-OCT-1994 08:33:10 $1$DGA8345:[LIB_H.SRC]BUFIODEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BUFIODEF ***/#ifndef __BUFIODEF_LOADED#define __BUFIODEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas 2 supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif3 #endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* BUFIO - Buffered I/O Packet Header */N/* */N/* There are two alternative formats for the packet header of a simple */N/* buffered I/O packet. The first is the "tradi4 tional" 12 byte header */N/* (symbolic constant BUFIO$K_HDRLEN32) that contains room for a 32-bit */N/* user buffer address. The second alternative format, with size */N/* BUFIO$K_HDRLEN64, that contains room for a 64-bit user buffer address. */N/* */N/* These two types of simple buffered I/O packets are "self identifying." */N/* That is, it is possible to distinguish a 32-bit from a 64-bit format 5 */N/* packet from the 32-bit user buffer address cell. A -1 value (symbolic */P/* constant BUFIO$K_64) in this cell indicates that this is a 64-bit buffered */P/* I/O packet and that the user buffer address is in the BUFIO$PQ_UVA64 cell. */N/* This is very similar to the method used to identify a 64-bit descriptor. */N/*- */ N#define BUFIO$K_64 -1 /* BUFIO$K_64, see BUFIO$PQ_UVA64 */P#define BUFI 6 O$K_HDRLEN32 12 /* Size of 32-bit BUFIO packet header */P#define BUFIO$K_HDRLEN64 24 /* Size of 64-bit BUFIO packet header */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _bufio {#pragma __nomember_alignment\ void *bufio$ps_pktdata; /* Pointer to the buffered data within the packet */a void * 7 bufio$ps_uva32; /* 32-bit pointer to user's buffer, or BUFIO$K_64 (-1) */N unsigned short int bufio$w_size; /* Total packet size */N unsigned char bufio$b_type; /* Structure type, DYN$C_BUFIO */ char bufio$b_fill_1; int bufio$l_fill_2;#pragma __member_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N 8 void *bufio$pq_uva64; /* 64-bit pointer to user's buffer */#else! unsigned __int64 bufio$pq_uva64;#endifN/* Valid if and only if BUFIO$PS_UVA32 contains */N/* the value BUFIO$K_64 (-1). */ } BUFIO; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defi9 ned required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BUFIODEF_LOADED */ ww`ZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, dupli: cated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyo; ne without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:38 < by OpenVMS SDL V3.7 */K/* Source: 31-MAY-2022 17:00:19 $1$DGA8345:[LIB_H.SRC]BUGCHECKDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BUGCHECKDEF ***/#ifndef __BUGCHECKDEF_LOADED#define __BUGCHECKDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_S= IZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#els> e#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define BUGDATA$M_NEW_DIAGS 0x1!#define BUGDATA$M_NEW_DUMPDEV 0x2##define BUGDATA$M_NEW_DUMPFLAGS 0x4!#define BUGDATA$M_NEW_MAXCPUS 0x8 #define BUGDATA$M_PAC_ENABLE 0x1N#define BUGDATA$C_LENGTH 408 /* Length of structure */S/* Allocate a 4K HW page (must be second half of the 8K used by th? e Kernel Base) */N#define BUGDATA$C_TOP_OF_STACK 24576 /* Offset to top of stack */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _bugcheck_data {#pragma __nomember_alignment) unsigned __int64 bugdata$q_uefi_ptbr;( unsigned __int64 bugdata$q_uefi_idt;3 unsigned __int64 bugdata$q_pa_dk_initial_stack;2 unsi@ gned __int64 bugdata$q_pa_dk_xfer_address;d unsigned int bugdata$l_pk_bap_offset; /* Offset from base of this structure (multiple of 8KB) */c unsigned int bugdata$l_pk_bap_size; /* Size in bytes of Primary Kernel BAP (multiple of 8KB) */d unsigned int bugdata$l_dk_bap_offset; /* Offset from base of this structure (multiple of 8KB) */` unsigned int bugdata$l_dk_bap_size; /* Size in bytes of Dump Kernel BAP (multiple of 8KB) */" char bugdata$t_fill_area [80];3 unsigned __int64 b A ugdata$q_base_image_linktime;* unsigned __int64 bugdata$q_crash_time;+ unsigned __int64 bugdata$q_system_ptbr;0 unsigned __int64 bugdata$q_process_ptbr [4];R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */. struct _intstk *bugdata$q_exception_frame;#else, unsigned __int64 bugdata$q_exception_frame;#endif int bugdata$l_bugcheck_code; int bugdat B a$l_dump_style; int bugdata$l_primary_cpudb; int bugdata$l_pte_levels; int bugdata$l_sys_symvec;! int bugdata$l_sys_symvec_end; __union {5 unsigned short int bugdata$w_new_config_data; __struct {- unsigned bugdata$v_new_diags : 1;/ unsigned bugdata$v_new_dumpdev : 1;1 unsigned bugdata$v_new_dumpflags : 1;/ unsigned bugdata$v_new_maxcpus : 1;n unsigned bugdata$v_config_fill : 12 /** WARNING: C bitfield array has been reduced to a string **/ ;% } bugdata$r_config_struc;! } bugdata$r_config_union; __union {+ unsigned short int bugdata$w_flags; __struct {. unsigned bugdata$v_pac_enable : 1;m unsigned bugdata$v_flags_fill : 15 /** WARNING: bitfield array has been reduced to a string **/ ;$ } bugdata$r_flags_struc; } bugdata$r_flags_union;% unsigned int bugdata$l_dump_mask;& unsigned int bugdaD ta$l_exec_flags;d unsigned int bugdata$l_dumpflags; /* Updated Dump Kernel boot flags (if NEW_DUMPFLAGS != 0) */' unsigned __int64 bugdata$q_max_pfn;a unsigned __int64 bugdata$q_diags; /* Updated Dump Kernel diagnostics (if NEW_DIAGS != 0) */f unsigned int bugdata$l_dumpdev_offset; /* Offset within this page of updated dump device string */e unsigned int bugdata$l_dumpdev_length; /* and length of string (both zero if NEW_DUMPDEV == 0) */N/* (Filled in by SET DUMP). E */g unsigned int bugdata$l_paclist_offset; /* Offset within this page of PACLIST_B data from SYSBOOT */h unsigned int bugdata$l_paclist_length; /* and length of list (both zero if no SYSBOOT> SET/CLASS) */N/* (Filled in by BUGCHECK's INIT code). */ char bugdata$t_nodename [8];h unsigned int bugdata$l_alloclass; /* Allows Dump Kernel to use same alloclass as Primary Kernel */i unsigned int bugdata$l_maxF cpus; /* Updated Dump Kernel Maximum CPU Count (if NEW_MAXCPUS != 0) */N/* If necessary, add a spare cell here so we always have pairs of longwords */I/* and allow quadwords to align. Uncomment the next line if needed: */9/* SPARE longword fill; */d/* 64 bytes chosen for these two fields to match the code in SR$UNIT_INIT ([OPDRIVER]SRDRIVER.C), */^/* in EXE$FILL_HWNAME ([SYS]C_UTILS.C), and in routines EXE$GET_MANUFACTURER_FRM_SMBIOS and */I/* EXE$GET_PROG DUCT_NAME_FRM_SMBIOS ([SYS]SYSGETSYI_SMBIOS.C). */N char bugdata$t_manufacturer [64]; /* SMBIOS manufacturer string */N char bugdata$t_product_name [64]; /* SMBIOS product name string */Q/* for the trampoline code that is copied there by the BUGCHECK_X86 init code. */I/* Allocate 4 x 4K pages for stack space for the trampoline. */L/* (All this fits well inside the megabyte reserved by the boot manager). */) char bugdata$t_data_page_fill [3688];- H char bugdata$t_embedded_code_page [4096];* char bugdata$t_embedded_stack [16384]; } BUGCHECK_DATA; #if !defined(__VAXC)R#define bugdata$w_new_config_data bugdata$r_config_union.bugdata$w_new_config_data]#define bugdata$v_new_diags bugdata$r_config_union.bugdata$r_config_struc.bugdata$v_new_diagsa#define bugdata$v_new_dumpdev bugdata$r_config_union.bugdata$r_config_struc.bugdata$v_new_dumpdeve#define bugdata$v_new_dumpflags bugdata$r_config_union.bugdata$r_config_struc.bugdata$v_ I new_dumpflagsa#define bugdata$v_new_maxcpus bugdata$r_config_union.bugdata$r_config_struc.bugdata$v_new_maxcpus=#define bugdata$w_flags bugdata$r_flags_union.bugdata$w_flags]#define bugdata$v_pac_enable bugdata$r_flags_union.bugdata$r_flags_struc.bugdata$v_pac_enable"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previJ ously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __BUGCHECKDEF_LOADED */ wwGZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to K be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disL closed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct M -2024 15:22:25 by OpenVMS SDL V3.7 */I/* Source: 12-MAY-2006 21:23:30 $1$DGA8345:[LIB_H.SRC]BUGLOGDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BUGLOGDEF ***/#ifndef __BUGLOGDEF_LOADED#define __BUGLOGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POIN NTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct structO #else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* BUGLOG - BUGcheck LOG buffer */N/* */N/* A BUGLOG buffer is a per-CPU data area that may contain */ P N/* additional information for use in analyzing a crash dump. */N/*- */ !#define BUGLOG$M_DATA_PRESENT 0x1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _buglog {#pragma __nomember_alignmentr __int64 buglog$q_timestamp; /* System timeQ when SYS$GET_BUGLOG was called to reserve this structure */V unsigned short int buglog$w_size; /* Size of entire BUGLOG structure in bytes */N unsigned char buglog$b_type; /* Structure type (DYN$C_MISC) */N unsigned char buglog$b_subtype; /* Structure subtype (DYN$C_BUGLOG) */ __union {N unsigned short int buglog$w_flags; /* BUGLOG flags */ __struct {n unsigned buglog$v_data_present : 1; /* Buffer has been reserved fo R r use, data should be present */* unsigned buglog$v_fill_0_ : 7;" } buglog$r_flags_bits;! } buglog$r_flags_overlay;i unsigned short int buglog$w_data_len; /* Number of bytes starting at DATASTART that caller may use */N unsigned __int64 buglog$q_caller_pc; /* Caller's return address */N unsigned __int64 buglog$q_saved_r0; /* Caller's R0 */N unsigned __int64 buglog$q_saved_r1; /* Caller's R1 */N unsi S gned __int64 buglog$q_reserved; /* Reserved */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment __struct {N __int64 buglog$q_qw01; /* User data area as quadwords */" __int64 buglog$q_qw02;" __int64 buglog$q_qw03;" __int64 buglT og$q_qw04;" __int64 buglog$q_qw05;" __int64 buglog$q_qw06;" __int64 buglog$q_qw07;" __int64 buglog$q_qw08;" __int64 buglog$q_qw09;" __int64 buglog$q_qw10;" __int64 buglog$q_qw11;" __int64 buglog$q_qw12;" __int64 buglog$q_qw13;" __int64 buglog$q_qw14;" __int64 buglog$q_qw15;" __int64 buglog$q_qw16;" __int64 buglog$q_qw17;" __int64 buglogU $q_qw18;" __int64 buglog$q_qw19;" __int64 buglog$q_qw20;" __int64 buglog$q_qw21;" __int64 buglog$q_qw22;" __int64 buglog$q_qw23;" __int64 buglog$q_qw24;" __int64 buglog$q_qw25;" __int64 buglog$q_qw26;% } buglog$r_datastart_qws;N char buglog$t_datastart [208]; /* User data area as byte block */% } buglog$r_datastart_overlay; } BUGLOG; #if !defined(__VAXC)<#definV e buglog$w_flags buglog$r_flags_overlay.buglog$w_flags^#define buglog$v_data_present buglog$r_flags_overlay.buglog$r_flags_bits.buglog$v_data_presentU#define buglog$q_qw01 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw01U#define buglog$q_qw02 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw02U#define buglog$q_qw03 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw03U#define buglog$q_qw04 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw04U#dW efine buglog$q_qw05 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw05U#define buglog$q_qw06 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw06U#define buglog$q_qw07 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw07U#define buglog$q_qw08 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw08U#define buglog$q_qw09 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw09U#define buglog$q_qw10 buglog$r_datastart_overlay.buglog$r_datastart_X qws.buglog$q_qw10U#define buglog$q_qw11 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw11U#define buglog$q_qw12 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw12U#define buglog$q_qw13 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw13U#define buglog$q_qw14 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw14U#define buglog$q_qw15 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw15U#define buglog$q_qw16 buglog$r_datastart_overlY ay.buglog$r_datastart_qws.buglog$q_qw16U#define buglog$q_qw17 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw17U#define buglog$q_qw18 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw18U#define buglog$q_qw19 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw19U#define buglog$q_qw20 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw20U#define buglog$q_qw21 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw21U#define buglog$q_qw22 buZ glog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw22U#define buglog$q_qw23 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw23U#define buglog$q_qw24 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw24U#define buglog$q_qw25 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw25U#define buglog$q_qw26 buglog$r_datastart_overlay.buglog$r_datastart_qws.buglog$q_qw26H#define buglog$t_datastart buglog$r_datastart_overlay.buglog$t_datastart"#endif /* #if ! [ defined(__VAXC) */ Q#define BUGLOG$K_LENGTH 256 /* Standard length of BUGLOG structure */N#define BUGLOG$C_LENGTH 256 /* Ditto */N#define BUGLOG$S_BUGLOGDEF 256 /* Another size name synonym */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifd\ ef __cplusplus }#endif#pragma __standard #endif /* __BUGLOGDEF_LOADED */ wwЕZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without] the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior ^ written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:30 by OpenVMS SDL V3.7 */K/* S _ ource: 14-JUN-2019 15:55:49 $1$DGA8345:[LIB_H.SRC]BUSARRAYDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BUSARRAYDEF ***/#ifndef __BUSARRAYDEF_LOADED#define __BUSARRAYDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size ` pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_structa #endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include #include N/*+ */Q/* Bus Array -- each node on a bus has an entry in the Bus Array for that bus. */N/* */N/* A Bus Array is pointed to by a field in the ADP. A Bus Array cb onsists */P/* of a header and a number of entries (one for each node on the bus or one */N/* for each channel on an adapter). */N/* Each entry contains info on the node, such as hardware id, base CSR */N/* address, a pointer to a data structure, and node number. */N/* */N/*- */N/* Define Buc s Array Entry */ N/* ================================================================ */N/* BUSARRAYENTRY */N/* ================================================================ */N/* Characterizes hardware connected to the bus adapter represented */N/* by the ADP. The Bus Array is comprised of a number of these */N/* BUSARRAYENTRYs, one for each no d de on the bus. */N/* */##define BUSARRAY$M_NO_RECONNECT 0x1#define BUSARRAY$M_MSI 0x2"#define BUSARRAY$M_INVALID_BAE 0x4!#define BUSARRAY$M_SPAREBIT03 0x8#define BUSARRAY$M_MULTI 0x10#define BUSARRAY$M_CHANNEL 0x20"#define BUSARRAY$M_PCI_BRIDGE 0x40!#define BUSARRAY$M_NO_DRIVER 0x80$#define BUSARRAY$M_INT_ENABLED 0x100 #define BUSARRAY$M_DELMODE 0xE00"#define BUSARRAY$M_POLARITY 0x10e 00"#define BUSARRAY$M_TRIGMODE 0x2000#define BUSARRAY$M_MSIX 0x4000!#define BUSARRAY$M_CONSOLE 0x8000##define BUSARRAY$M_DESTMODE 0x10000  9#ifdef __cplusplus /* Define structure prototypes */ struct _crb; struct _adp; struct _bax; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _busarr f ayentry { __union {#pragma __nomember_alignmentN unsigned __int64 busarray$q_hw_id; /* Hardware ID. */ __struct {N unsigned short int busarray$w_pci_vend_id; /* Vendor ID */N unsigned short int busarray$w_pci_dev_id; /* Device ID */R unsigned short int busarray$w_pci_subvend_id; /* Subsytem Vendor ID */T unsigned short int busarray$w_pci_subsys_id; /* Subsystem (Device) ID */, } bu g sarray$r_pci_hw_word_fields; __struct {N unsigned int busarray$l_pci_dev_vend_id; /* Device & Vendor ID */Z unsigned int busarray$l_pci_subsys_vend_id; /* Subsystem Vendor & subsys ID */- } busarray$r_pci_hw_lword_fields;# } busarray$r_hw_id_overlay;N unsigned __int64 busarray$q_csr; /* Base CSR address */N __union { /* Node or channel number */' __int64 busarray$q_node_numbh er; __struct { __union {- int busarray$l_node_number_l;+ int busarray$l_node_number;1 } busarray$r_nn_low_long_overlay;) int busarray$l_node_number_h;( } busarray$r_nn_long_struct; } busarray$r_nn_overlay; __union {N unsigned int busarray$l_flags; /* Flags */ __struct {1 unsigned busarray$v_no_reconnect : 1;Z unsigni ed busarray$v_msi : 1; /* PCI 2.2 & PCIX message signaled interrupts. */N unsigned busarray$v_invalid_bae : 1; /* Invalid BAE - ignore. */S unsigned busarray$v_sparebit03 : 1; /* A named bit for future needs. */W unsigned busarray$v_multi : 1; /* multi-function or multi-channel device */R unsigned busarray$v_channel : 1; /* This BUSARRAYENTRY is a channel */N unsigned busarray$v_pci_bridge : 1; /* PCI-PCI Bridge device */O j unsigned busarray$v_no_driver : 1; /* No entry in SYS$CONFIG.DAT */0 unsigned busarray$v_int_enabled : 1;N/* Verified for X86, Dave Fairbanks */O unsigned busarray$v_delmode : 3; /* IOAPIC/IOSAPIC delivery mode */N unsigned busarray$v_polarity : 1; /* 0=Active-hi, 1=Active-lo */N unsigned busarray$v_trigmode : 1; /* 0=Edge, 1=Level */N unsigned busarray$v_msix : 1; /* MSI-X interrupt dei k very */R unsigned busarray$v_console : 1; /* The one and only console device */N/* Verified for x86--Drew Mason */N unsigned busarray$v_destmode : 1; /* 0=Physical, 1=Logical */, unsigned busarray$v_fill_0_ : 7;# } busarray$r_flag_bits;# } busarray$r_flags_overlay;N struct _crb *busarray$ps_crb; /* Pointer to Channel Request Block */N struct _adp *busarray$ps_adp; /* P l ointer to subordinate ADP */ __union {N unsigned int busarray$l_autoconfig; /* Reserved for Autoconfigure */N void *busarray$ps_autoconfig; /* Reserved for Autoconfigure */( } busarray$r_autoconfig_overlay; __union {( unsigned int busarray$l_ctrlltr;) unsigned char busarray$b_ctrlltr;% } busarray$r_ctrlltr_overlay;N/* Make sure the following quadword stays aligned properly */ char busarray$b_fill_1_ [4m ];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment1 unsigned __int64 busarray$q_bus_specific; __struct { __union {7 unsigned int busarray$l_bus_specific_l;1 void *busarray$ps_bus_specific_l;V unsigned int busarray$l_int_vec; /* Offset n into SCB or vector table */c unsigned int busarray$l_sys_irq; /* System IRQ (4*SYS_IRQ = vector table offset) */N unsigned int busarray$l_scb_offset; /* Offset into the SCB */4 } busarray$r_bus_specific_l_overlay; __union {7 unsigned int busarray$l_bus_specific_h;1 void *busarray$ps_bus_specific_h;7 unsigned int busarray$l_bus_specific_1;1 void *busarray$ps_bus_specific_1 o ;4 } busarray$r_bus_specific_h_overlay;- } busarray$r_bus_specific_fields;* } busarray$r_bus_specific_overlay;N __union { /* Quadword aligns the structure *// unsigned int busarray$l_bus_specific_2;) void *busarray$ps_bus_specific_2;% struct _bax *busarray$ps_bax;, } busarray$r_bus_specific_2_overlay;N/* Verified for X86, Dave Fairbanks */ char busarra p y$b_fill_2_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifh unsigned __int64 busarray$q_hw_handle; /* An opaque handle used to map this entry to its hardware */#pragma __nomember_alignmentW unsigned __int64 busarray$q_parent_hh; /* Hardware handle of this entry's parent */N int busarray$l_gsin; /* Global System Interrupt Numbe q r */n int busarray$l_ivec; /* Assigned Interrupt vector (see DIDTDEF, SAPICDEF, and IOAPICDEF) */N/* Verified for x86--Drew Mason */` void *busarray$ps_ioapic; /* System address of the IOAPIC for this device (x86) */ char busarray$b_fill_3_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_ali r gnment#endif __union {#pragma __nomember_alignmentN CBB busarray$r_cbb_cpu_affinity; /* Embedded CBB block */N __struct { /* Compatability offset cells */. __int64 busarray$q_cbb_fill_1 [6]; __union {h unsigned int busarray$l_cpu_affinity; /* Identifies CPU the device is interrupting on */l unsigned __int64 busarray$q_cpu_affinity; /* Identifies CPU the device is interrupting on s */5 } busarray$r_cbb_cpu_affinity_data_o;/ __int64 busarray$q_cbb_fill_2 [15];1 } busarray$r_cbb_cpu_affinity_compat;- } busarray$r_cbb_cpu_affinity_overla; } BUSARRAYENTRY; #if !defined(__VAXC)B#define busarray$q_hw_id busarray$r_hw_id_overlay.busarray$q_hw_idl#define busarray$w_pci_vend_id busarray$r_hw_id_overlay.busarray$r_pci_hw_word_fields.busarray$w_pci_vend_idj#define busarray$w_pci_dev_id busarray$r_hw_id_overlay.busarray$r_pci_t hw_word_fields.busarray$w_pci_dev_idr#define busarray$w_pci_subvend_id busarray$r_hw_id_overlay.busarray$r_pci_hw_word_fields.busarray$w_pci_subvend_idp#define busarray$w_pci_subsys_id busarray$r_hw_id_overlay.busarray$r_pci_hw_word_fields.busarray$w_pci_subsys_idu#define busarray$l_pci_dev_vend_id busarray$r_hw_id_overlay.busarray$r_pci_hw_lword_fields.busarray$l_pci_dev_vend_id{#define busarray$l_pci_subsys_vend_id busarray$r_hw_id_overlay.busarray$r_pci_hw_lword_fields.busarray$l_pci_subsys_veu nd_idK#define busarray$q_node_number busarray$r_nn_overlay.busarray$q_node_number#define busarray$l_node_number_l busarray$r_nn_overlay.busarray$r_nn_long_struct.busarray$r_nn_low_long_overlay.busarray$l_node_num\ber_l#define busarray$l_node_number busarray$r_nn_overlay.busarray$r_nn_long_struct.busarray$r_nn_low_long_overlay.busarray$l_node_numberi#define busarray$l_node_number_h busarray$r_nn_overlay.busarray$r_nn_long_struct.busarray$l_node_number_hB#define busarray$l_flags busarray$r_v flags_overlay.busarray$l_flagse#define busarray$v_no_reconnect busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_no_reconnectS#define busarray$v_msi busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_msic#define busarray$v_invalid_bae busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_invalid_baea#define busarray$v_sparebit03 busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_sparebit03W#define busarray$v_multi busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_w multi[#define busarray$v_channel busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_channela#define busarray$v_pci_bridge busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_pci_bridge_#define busarray$v_no_driver busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_no_driverc#define busarray$v_int_enabled busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_int_enabled[#define busarray$v_delmode busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_delmode]#define bux sarray$v_polarity busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_polarity]#define busarray$v_trigmode busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_trigmodeU#define busarray$v_msix busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_msix[#define busarray$v_console busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_console]#define busarray$v_destmode busarray$r_flags_overlay.busarray$r_flag_bits.busarray$v_destmodeQ#define busarray$l_autoconfig busarray$r_autocy onfig_overlay.busarray$l_autoconfigS#define busarray$ps_autoconfig busarray$r_autoconfig_overlay.busarray$ps_autoconfigH#define busarray$l_ctrlltr busarray$r_ctrlltr_overlay.busarray$l_ctrlltrH#define busarray$b_ctrlltr busarray$r_ctrlltr_overlay.busarray$b_ctrlltrW#define busarray$q_bus_specific busarray$r_bus_specific_overlay.busarray$q_bus_specific#define busarray$l_bus_specific_l busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_l_overlay.\busarray$lz _bus_specific_l#define busarray$ps_bus_specific_l busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_l_overlay\.busarray$ps_bus_specific_l#define busarray$l_int_vec busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_l_overlay.busarra\ y$l_int_vec#define busarray$l_sys_irq busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_l_overlay.busarra\ y$l_sys_irq#define busarray$l_scb_offse{ t busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_l_overlay.busa\rray$l_scb_offset#define busarray$l_bus_specific_h busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_h_overlay.\busarray$l_bus_specific_h#define busarray$ps_bus_specific_h busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_h_overlay\.busarray$ps_bus_specific_h#define busarray$l_bus_specific_1 busarray$r_bus_speci| fic_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_h_overlay.\busarray$l_bus_specific_1#define busarray$ps_bus_specific_1 busarray$r_bus_specific_overlay.busarray$r_bus_specific_fields.busarray$r_bus_specific_h_overlay\.busarray$ps_bus_specific_1]#define busarray$l_bus_specific_2 busarray$r_bus_specific_2_overlay.busarray$l_bus_specific_2_#define busarray$ps_bus_specific_2 busarray$r_bus_specific_2_overlay.busarray$ps_bus_specific_2I#define busarray$ps_bax busarray$r_bus_s} pecific_2_overlay.busarray$ps_baxb#define busarray$r_cbb_cpu_affinity busarray$r_cbb_cpu_affinity_overla.busarray$r_cbb_cpu_affinity#define busarray$l_cpu_affinity busarray$r_cbb_cpu_affinity_overla.busarray$r_cbb_cpu_affinity_compat.busarray$r_cbb_cpu_affinity_d\ata_o.busarray$l_cpu_affinity#define busarray$q_cpu_affinity busarray$r_cbb_cpu_affinity_overla.busarray$r_cbb_cpu_affinity_compat.busarray$r_cbb_cpu_affinity_d\ata_o.busarray$q_cpu_affinity"#endif /* #if !defined(__VAXC) */ ~ "#define BUSARRAYENTRY$K_LENGTH 272N/* ================================================================ */N/* BUSARRAY_HEADER */N/* ================================================================ */N/* Descriptor for the Bus Array hanging off the ADP. */N/* */^#define BUSARRAYHEADER$K_LENGTH 24 /* Keep length before ENTRY_ LIST, which has no real */N/* length */N#define BUSARRAY$S_BUSARRAYHEADER 24 /* Old size name */  9#ifdef __cplusplus /* Define structure prototypes */ struct _adp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif!typedef  struct _busarray_header {#pragma __nomember_alignmentN struct _adp *busarray$ps_parent_adp; /* Point back to ADP */N unsigned int busarray$l_fill1; /* */N unsigned short int busarray$w_size; /* Structure size in bytes */N unsigned char busarray$b_type; /* Structure type */N unsigned char busarray$b_subtype; /* Structure subtype */N unsigned int busarray$l_bus_type; /* Bus T ype code */N unsigned int busarray$l_bus_node_cnt; /* Number of entries in Bus Array */N unsigned int busarray$l_fill2; /* Fill to quadword boundary */ __union {N __int64 busarray$q_entry_list [1]; /* Bus Array entries start */N/* at entry_list */S BUSARRAYENTRY busarray$r_bus_array_entry; /* First bus array in the list */! } busarray$r_bae_overlay; } BUSARRAY_H EADER; #if !defined(__VAXC)J#define busarray$q_entry_list busarray$r_bae_overlay.busarray$q_entry_listT#define busarray$r_bus_array_entry busarray$r_bae_overlay.busarray$r_bus_array_entry"#endif /* #if !defined(__VAXC) */ N/* ================================================================ */N/* BAX - BUSARRAYENTRY EXTENSION */N/* ================================================================ */N/* This structure is the BusAr ray eXtension and provides more */N/* detail for the characterization of the hardware represented */N/* by the BUSARRAYENTRY. */N/* */#define BAX$K_LENGTH 112  9#ifdef __cplusplus /* Define structure prototypes */ struct _adp;struct _vec_list;struct _mvi_data; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUP PORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _bax {N/* */N/* */N/* The following field points back to the ADP on which this BAX */N/* resides. */N/* */#pragma __nomember_alignmentN struct _adp *bax$ps_parent_adp; /* Mother ADP */N/* */N/* */N/* This field points back to the BUSARRAYENTRY that "owns" this BAX */N/* instance. */ N/* */- struct _busarrayentry *bax$ps_parent_bae;N/* */N/* */N/*-------------------------------------------------------------- */N/* General Data */N/*------------------------------------------------------ -------- */N/* */N unsigned int bax$l_channel; /* Channel number */O struct _vec_list *bax$ps_vec_list; /* Interrupt Vectors List see IOCDEF */N unsigned int bax$l_int_mech; /* Interrupt delivery mechanism */N/* */N/* */N /*-------------------------------------------------------------- */N/* Descriptor for Bus-specific data buffer. */N/*-------------------------------------------------------------- */N/* For PCI busses, this is a snapshot of the Config Header. */N/* */ char bax$b_fill_4_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using  pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __struct {#pragma __nomember_alignment __union {, __int64 bax$q_bus_data_area [4]; __struct {1 unsigned int bax$l_bus_data_size;1 unsigned int bax$l_bus_data_type;& void *bax$ps_bus_data;, } bax$r_bus_data_descriptor;% } bax$r_bus_data_overlay; } bax$r_bus_da ta;N/* */N/* */N/*-------------------------------------------------------------- */N/* Interrupt Routine Pointers */N/*-------------------------------------------------------------- */N/* Since PCI-X, it has been possible for devices on the same bus */N/* to use different  interrupt technologies. These fields provide */N/* long (64-bit) and short (32-bit) pointers to the device-specific */N/* Interrupt Init, Enable, Disable, and Redirection routines. These */N/* fields are initialized with the appropriate routine pointer when */N/* the interrupt technology is determined (IOSAPIC, IOAPIC, MSI, MSI-X...), */N/* during device configuration. The IRQ init and node_function */N/* routines will call through these pointers t o the correct routine */N/* for the device. */N/* */ void *bax$ps_msiabs;# int (*bax$ps_init_interrupt)();% int (*bax$ps_enable_interrupt)();& int (*bax$ps_disable_interrupt)();' int (*bax$ps_redirect_interrupt)();N/* */N/* */N/*-------------------------------------------------------------- */N/* Multiple Vector Interrupt Routines and Data */N/*-------------------------------------------------------------- */& struct _mvi_data *bax$ps_mvi_data;( int (*bax$ps_mvi_request_vectors)();# int (*bax$ps_mvi_map_vector)();N int (*bax$ps_mvi_dispatch_vte)(); /* MSIX only */( int (*bax$ps_mvi_dispatch_un ique)();( int (*bax$ps_mvi_dispatch_vector)();$ int (*bax$ps_mvi_mask_vector)();& int (*bax$ps_mvi_unmask_vector)();' int (*bax$ps_mvi_pending_vector)();N/* */N/* */N/* Fill to quadword boundary */N/* */ } BAX; #if !defined(__VAXC)U#define bax$q_bus_data_area bax$r_bus_data.bax$r_bus_data_overlay.bax$q_bus_data_areao#define bax$l_bus_data_size bax$r_bus_data.bax$r_bus_data_overlay.bax$r_bus_data_descriptor.bax$l_bus_data_sizeo#define bax$l_bus_data_type bax$r_bus_data.bax$r_bus_data_overlay.bax$r_bus_data_descriptor.bax$l_bus_data_typeg#define bax$ps_bus_data bax$r_bus_data.bax$r_bus_data_overlay.bax$r_bus_data_descriptor.bax$ps_bus_data"#endif /* #if !defined(__VAXC) */   &#pragma __re quired_pointer_size __save&#pragma __required_pointer_size __long-typedef BUSARRAY_HEADER * BUSARRAY_HEADER_PQ;)typedef BUSARRAYENTRY * BUSARRAYENTRY_PQ;'#pragma __required_pointer_size __short-typedef BUSARRAY_HEADER * BUSARRAY_HEADER_PL;)typedef BUSARRAYENTRY * BUSARRAYENTRY_PL;)#pragma __required_pointer_size __restore $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore  /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __BUSARRAYDEF_LOADED */ wwpZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not ** /M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be u sed, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************************************************************* */=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 05-AUG-2022 10:30:00 $1$DGA8345:[LIB_H.SRC]BUSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $BUSDEF ***/#ifndef __BUSDEF_LOADED#define __BUSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __I NITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __stru ct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Bus Type definitions. */N/* */N/* DEFINE Bus Types -- used in BUSARRAY$L_BUS_TYPE and  */N/* CMDTABLE$L_BUS_TYPE */N/* */N/* DEFINE BUS TYPES */N/* */#define BUS$_FBUS 1#define BUS$_XMI 2#define BUS$_LBUS 3#define BUS$_TURBO 4#define BUS$_CBUS 5#define BUS$_LSB 6#define BUS$_NI 7#define BUS$_CI 8#defin e BUS$_FDDI 9#define BUS$_SCSI 10#define BUS$_DSSI 11#define BUS$_KDM70 12#define BUS$_GENXMI 13#define BUS$_BUSLESS_SYSTEM 14#define BUS$_COREIO 15#define BUS$_EISA 16#define BUS$_VTI_COMBO 17#define BUS$_VME 18#define BUS$_PCI 19#define BUS$_ISA 20#define BUS$_XBUS 21#define BUS$_THIRDPARTY0 22#define BUS$_THIRDPARTY1 23#define BUS$_THIRDPARTY2 24#define BUS$_THIRDPARTY3 25#define BUS$_THIRDPARTY4 26#define BUS$_THIRDPARTY5 27#define BUS$_THIRDPARTY6 28#define BUS$_THIRDPARTY7 29#define BUS$_TLSB 30#define BUS$_TIOP 31#define BUS$_ITIOP 32#define BUS$_PCMCIA 33#define BUS$_GLOBAL_BUS 34#define BUS$_MC_BUS 35#define BUS$_WF_BUS 36#define BUS$_IA64_BUS 37#define BUS$_NULL 38#define BUS$_PCIE 39#define BUS$_VMBUS 40 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined requ ired ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __BUSDEF_LOADED */ ww`fZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR d isclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVM S SDL V3.7 */E/* Source: 28-MAR-2005 09:55:56 $1$DGA8345:[LIB_H.SRC]C2DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $C2DEF ***/#ifndef __C2DEF_LOADED#define __C2DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr siz e pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struc t#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* C2 - C2 Subset Definitions */N/* */P/* This structures maps the bits in the SECURITY_POLICY SYSGEN parameter that */Q/* are used to enable or remove feat ures that have not been formally evaluated */N/* by the NCSC under our C2/B1 VMS/SEVMS evaluation. */N/* */N/*- */)#define C2$M_ALLOW_DISPLAY_POSTSCRIPT 0x1*#define C2$M_ALLOW_MULTIPLE_DECW_USERS 0x2+#define C2$M_ALLOW_ALTERNATE_TRANSPORTS 0x4%#define C2$M_ALLOW_SPAN_JOB_TREES 0x8#define C2$M_LOCAL_UPDATE 0x10#define C2$M _LOCAL_PROFILE 0x20%#define C2$M_ALLOW_CAPTIVE_SPAWN 0x40&#define C2$M_COMPRESS_MAC_STRINGS 0x80"#define C2$M_UPPERCASE_INPUT 0x100"#define C2$M_GUARD_PASSWORDS 0x200)#define C2$M_DOI_AUTHORIZATION_ONLY 0x400!#define C2$M_IGNORE_EXTAUTH 0x800(#define C2$M_INTRUSIONS_ARE_LOCAL 0x1000$#define C2$M_USE_POSIX_UIDGID 0x2000(#define C2$M_ALLOW_SYMLINK_ACCESS 0x4000#define C2$S_SECPOLDEF 4 typedef struct _secpol { __union {* unsigned int c2$l_security_policy; __stru ct {a unsigned c2$v_allow_display_postscript : 1; /* allow display postscript extensions */p unsigned c2$v_allow_multiple_decw_users : 1; /* allow multiple username to connect to DECW$SERVER */\ unsigned c2$v_allow_alternate_transports : 1; /* allow unevaluated transports */Y unsigned c2$v_allow_span_job_trees : 1; /* allow $SIGPRC to span job trees */N/* The following bits control profile management for cluster object */N/* when the object server is unavailable. Setting these bits will */N/* allow these objects to have inconsistent profiles within a security */N/* domain (cluster). */N unsigned c2$v_local_update : 1; /* allow local profile changes */N unsigned c2$v_local_profile : 1; /* allow local object creation */e unsigned c2$v_allow_captive_spawn : 1; /* allow SPAWN or LIB$SPAWN in CAPTIVE accounts */_ unsigned c2$v_compress_mac_strings : 1; /* compress MAC category strings (SEVMS) */N unsigned c2$v_uppercase_input : 1; /* as prior to VMS V7.1 */N unsigned c2$v_guard_passwords : 1; /* ACMEs shall not share */R unsigned c2$v_doi_authorization_only : 1; /* prevent feature mixing */i unsigned c2$v_ignore_extauth : 1; /* ignore user-specific EXTAUTH and VMSAUTH restrictions */a unsigned c2$v_intrusions_are_local : 1; /* consider local intrus ions only when set */d unsigned c2$v_use_posix_uidgid : 1; /* perform UID/GID lookup in tcpip proxy database */v unsigned c2$v_allow_symlink_access : 1; /* execute access permits read-attributes on FN and/or backlink */& unsigned c2$v_fill_2_ : 1; } c2$r_fill_1_; } c2$r_fill_0_; } SECPOL; #if !defined(__VAXC)>#define c2$l_security_policy c2$r_fill_0_.c2$l_security_policy]#define c2$v_allow_display_postscript c2$r_fill_0_.c2$r_fi ll_1_.c2$v_allow_display_postscript_#define c2$v_allow_multiple_decw_users c2$r_fill_0_.c2$r_fill_1_.c2$v_allow_multiple_decw_usersa#define c2$v_allow_alternate_transports c2$r_fill_0_.c2$r_fill_1_.c2$v_allow_alternate_transportsU#define c2$v_allow_span_job_trees c2$r_fill_0_.c2$r_fill_1_.c2$v_allow_span_job_treesE#define c2$v_local_update c2$r_fill_0_.c2$r_fill_1_.c2$v_local_updateG#define c2$v_local_profile c2$r_fill_0_.c2$r_fill_1_.c2$v_local_profileS#define c2$v_allow_captive_spawn c2$ r_fill_0_.c2$r_fill_1_.c2$v_allow_captive_spawnU#define c2$v_compress_mac_strings c2$r_fill_0_.c2$r_fill_1_.c2$v_compress_mac_stringsK#define c2$v_uppercase_input c2$r_fill_0_.c2$r_fill_1_.c2$v_uppercase_inputK#define c2$v_guard_passwords c2$r_fill_0_.c2$r_fill_1_.c2$v_guard_passwordsY#define c2$v_doi_authorization_only c2$r_fill_0_.c2$r_fill_1_.c2$v_doi_authorization_onlyI#define c2$v_ignore_extauth c2$r_fill_0_.c2$r_fill_1_.c2$v_ignore_extauthU#define c2$v_intrusions_are_local c2$r_fill_ 0_.c2$r_fill_1_.c2$v_intrusions_are_localM#define c2$v_use_posix_uidgid c2$r_fill_0_.c2$r_fill_1_.c2$v_use_posix_uidgidU#define c2$v_allow_symlink_access c2$r_fill_0_.c2$r_fill_1_.c2$v_allow_symlink_access"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __C2DEF_LOADED */ wwPZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prio r written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission o f VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */E/* Source: 16-OCT-1998 15:07:58 $1$DGA8345:[LIB_H.SRC]CADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CADEF ***/#ifndef __CADEF_LOADED#define __CADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_poi nter_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CONDITIONAL ASSEMBLY PARAMETER DEFINITIONS */N/* */N/* A NONZERO PARAMETER VALUE INDICATES PRESENCE OF THE FEATURE. */N/* A ZERO PARAMETER VALUE INDICATES ABSENCE OF THE FEATURE */N/*  */N/* ALL PARAMETERS MUST BE DEFINED */N/*- */N#define CA$_SIMULATOR 1 /*INCLUDE SIMULATOR SUPPORT CODE */S#define CA$_MEASURE 2 /*INCLUDE PERFORMANCE MEASUREMENT HOOKS */U#define CA$_MEASURE_IOT 4 /*INCLUDE I/O TRANSACTION DATA COLLECTION */N#define CA$_LNM_ MEASURE 0 /*Exclude new logical name counters */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CADEF_LOADED */ ww RZUM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 09-FEB-2006 04:43:44 $1$DGA8345:[LIB_H.SRC]CALDEF.SDL;1 *//********************************************************************************************************************************//*** MOD ULE $CALDEF ***/#ifndef __CALDEF_LOADED#define __CALDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* CAL - Calibration information */N/* */N#define CAL$K_LENGTH 96 /* Structure size */N#define CAL$C_LENGTH 96 /* Structure size */  9#ifdef __cplusplus /* Define structure prototypes */ struct _spl;struct _cache_line; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defin ed(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cal {#pragma __nomember_alignmentP unsigned __int64 cal$q_last_calibration; /* timestamp of last calibration */N unsigned short int cal$w_mbo; /* must-be-one field */N unsigned char cal$b_type; /* Structure type (DYN$C_CAL) */N unsigned char cal$b_subtype; /* Structure subtype */ __union {N unsigned int cal$l_flags; /* flags */ __struct {N unsigned cal$v_ip : 1; /* calibration in-progress */' unsigned cal$v_fill_0_ : 7; } cal$r_flag_bits; } cal$r_flags_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif N __int64 cal$q_size; /* total size in bytes */#pragma __nomember_alignmentN unsigned int cal$l_max_cpus; /* maximum number of CPUs */N unsigned int cal$l_pages; /* total size in pages */S struct _spl *cal$l_spinlock; /* pointer to dynamic spinlock structure */ char cal$b_fill_1_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomemb er_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 cal$q_count; /* count number of calibrations */#pragma __nomember_alignmentN unsigned __int64 cal$q_divisor; /* divisor for timestamp conversion */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _cache_line *cal$q_scc_ref; /* pointer to array of cache lines */#else unsigned __int64 cal$q_scc_ref;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */_ __int64 *cal$q_scc; /* pointer to array of cycle counts per possible CPU */#else unsigned __int64 cal$q_scc;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long  /* And set ptr size default to 64-bit pointers */_ __int64 *cal$q_systime; /* pointer to array of systime info per possible CPU */#else unsigned __int64 cal$q_systime;#endif% unsigned __int64 cal$q_reserved1;% unsigned __int64 cal$q_reserved2; } CAL; #if !defined(__VAXC)3#define cal$l_flags cal$r_flags_overlay.cal$l_flags=#define cal$v_ip cal$r_flags_overlay.cal$r_flag_bits.cal$v_ip"#endif /* #if !defined(__VAXC) */  J#pragma __required_pointer _size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Dtypedef struct _cal * CAL_PQ; /* Pointer to a CAL structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#end if#ifdef __cplusplus }#endif#pragma __standard #endif /* __CALDEF_LOADED */ ww@ZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone wit hout the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the pr ior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */F /* Source: 10-MAR-1995 13:52:08 $1$DGA8345:[LIB_H.SRC]CANDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CANDEF ***/#ifndef __CANDEF_LOADED#define __CANDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporte d */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif  #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CAN - DEFINE DRIVER CANCEL ROUTINE REASON CODES */N/* */N/* THESE CODES ARE PASSED TO THE CANCEL ROUTINE OF A DRIVER SO THAT */N/* THE ROUTINE CAN DISTINGUISH BETWEEN CALLS FROM $DASSG N AND $CANCEL. */N/* */N/*- */S#define CAN$C_CANCEL 0 /*CANCEL INVOKED DUE TO $CANCEL SERVICE */S#define CAN$C_DASSGN 1 /*CANCEL INVOKED DUE TO $DASSGN SERVICE */T#define CAN$C_AMBXDGN 2 /*CANCEL INVOKED DUE TO MB DISASSOCIATION */Q#define CAN$C_MSCPSERVER 3 /*CANCEL INVOKED BY MSCP SERVER DUE TO */N/* CONNECTION LOSS TO CLIENT NODE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CANDEF_LOADED */ wwPZUM/***************************************************** **********************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M /** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */F/* Source: 13-JAN-2021 12:16:02 $1$DGA8345:[LIB_H.SRC]CBBDEF.SDL;1 *//******************************************************************************************************* *************************//*** MODULE $CBBDEF ***/#ifndef __CBBDEF_LOADED#define __CBBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32- bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define CBB$M_OVERRIDE_LOCK 1#define CBB$M_ ZERO 2#define CBB$M_DUPLICATE_COPY 4N/*+ */N/* */N/* Common bitmask block definition. The purpose of this data structure */N/* is to represent a variable, potentially unlimited number of CPUs in */N/* bitmask format. The CBB is intended to be a generic construct as well; */N/* flexible enough for other applications that require bitmask sup port. */N/*- */#define CBB$M_LOCK_BIT 0x1#define CBB$M_AUTO_LOCK 0x2#define CBB$M_TIMEOUT_CRASH 0x4#define CBB$M_SUMMARY_BITS 0x8#define CBB$M_SET_COUNT 0x10 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cbb {#pragma __nomember_alignmentN unsign ed int cbb$l_data_offset; /* Offset to start of bit data */N unsigned short int cbb$w_unit_count; /* Valid data units within block */N unsigned char cbb$b_unit_size; /* Size of data units in bytes */N unsigned char cbb$b_lock_ipl; /* Synchronization IPL for CBB */N unsigned short int cbb$w_size; /* Structure size */N unsigned char cbb$b_type; /* Structure type */N unsigned char cbb$b_subtype; /* Structure subtype */N unsigned int cbb$l_bit_count; /* Number of data bits set in block */ __union {N unsigned __int64 cbb$q_interlock; /* Alias for locking */ __union {N unsigned __int64 cbb$q_state; /* State bitmask */ __struct {N unsigned cbb$v_lock_bit : 1; /* Atomic locking bit */N unsigned cbb$v_auto_lock : 1; /* Automatic locking state */Q unsigned cbb$v_timeout_crash : 1; /* Crash if timeout exceeded */R unsigned cbb$v_summary_bits : 1; /* Summary masks to be updated */N unsigned cbb$v_set_count : 1; /* Count of bits set kept */+ unsigned cbb$v_fill_2_ : 3; } cbb$r_fill_1_; } cbb$r_fill_0_; } cbb$r_flags_overlay;N unsigned int cbb$l_timeout_count; /* Timeout interval in 10usec */N unsigned int cbb$l_saved_ipl;  /* Caller's IPL upon entrance to */N/* Exe$cbb_lock */N unsigned int cbb$l_valid_bits; /* # of bits (specified by the user */N/* on input to allocate, get_size, and */N/* initialize) represented by this Cbb */P char cbb$b_cbb_padding_0 [4]; /* To preserve quadword alignment */N/* */Y/* All new fields must be added before the SUMMARY_BITMASK field. The SUMMARY_BITMASK */N/* field below may be the 1st summary bitmask field of many. */N/* */U unsigned __int64 cbb$q_summary_bitmask; /* Summary bitmask of 64 unit bitmasks */ } CBB; #if !defined(__VAXC);#define cbb$q_interlock cbb$r_flags_overlay.cbb$q_interlockA#define cbb$q_state cbb$r_flags_overlay.cbb$r_ fill_0_.cbb$q_stateU#define cbb$v_lock_bit cbb$r_flags_overlay.cbb$r_fill_0_.cbb$r_fill_1_.cbb$v_lock_bitW#define cbb$v_auto_lock cbb$r_flags_overlay.cbb$r_fill_0_.cbb$r_fill_1_.cbb$v_auto_lock_#define cbb$v_timeout_crash cbb$r_flags_overlay.cbb$r_fill_0_.cbb$r_fill_1_.cbb$v_timeout_crash]#define cbb$v_summary_bits cbb$r_flags_overlay.cbb$r_fill_0_.cbb$r_fill_1_.cbb$v_summary_bitsW#define cbb$v_set_count cbb$r_flags_overlay.cbb$r_fill_0_.cbb$r_fill_1_.cbb$v_set_count"#endif /* #if !define d(__VAXC) */ N#define CBB$K_LENGTH 48 /* Length of CBB */N#define CBB$C_LENGTH 48 /* Length of CBB */N/* Function code values for the function input parameter to the routine, */N/* Exe$cbb_boolean_oper. */N/* */N#define CBB$C_OR 0 /* Logical Sum */N#define  CBB$C_AND 1 /* Logical Product */N#define CBB$C_XOR 2 /* Logical Difference */N#define CBB$C_BIC 3 /* Logical Product with Complement */N#define CBB$C_ORNOT 4 /* Logical Sum with Complement */N#define CBB$C_EQV 5 /* Logical Equivalence (XORNOT) */P#define CBB$C_COMP 6 /* Logical ones complement of source */#define CBB$C_MAX_FUNCTION 6N/* Verified for x86 Port - Clair Grant */##define CBB$K_STATIC_CPU_COUNT 1024#define CBB$K_STATIC_BLOCK 192 # ifdef __INITIAL_POINTER_SIZEM# pragma __required_pointer_size __save /* Save current pointer size */G# pragma __required_pointer_size 64 /* Pointers are 64-bits */G typedef struct _cbb * CBB_PQ; /* 64-bit pointer to a CBB */M typedef struct _cbb ** CBB_PPQ; /* 64-bit ptr to a ptr to a CBB */O# pragma __required_pointer_size __restore /* Return to previous ptr size */# elseH typedef unsigned __int64 CBB_PQ; /* Size = 64-bit ptr to a CBB */O typedef unsigned __int64 CBB_PPQ; /* Size = 64-bit ptr to a ptr to CBB */# endif $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus } #endif#pragma __standard #endif /* __CBBDEF_LOADED */ wwpZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior writ ten permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS  Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */F/* Source: 24-OCT-1994 14:54: 28 $1$DGA8345:[LIB_H.SRC]CCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CCBDEF ***/#ifndef __CCBDEF_LOADED#define __CCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_point er_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !d efined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CCB - CHANNEL CONTROL BLOCK */N/* */N/* THERE IS ONE CHANNEL CONTROL BLOCK FOR EACH SOFTWARE CHANNEL THAT A */N/* PROCESS MAY INITIATE I/O REQUESTS ON. THE NUMBER OF SUCH I/O CHANNELS */N/* IS DETERMINED BY THE FIXED NUMBER ASSIGNED TO A PROCESS PLUS ANY */N/* ADDITIONAL CHANNELS REQUIRED BY THE IMAGE CURRENTLY BEING EXECUTED */N/* BY THE PROCESS. */N/* */N/*- */ #define CCB$M_AMB 0x1#define CCB$M_IMGTMP 0x2#define CCB$M_RDCHKDON 0x4#define CCB$M_WRTCHKDON 0x8 #define CCB$M_LOGCHKDON 0x10#define CCB$M_PHYCHKDON 0x20#define CCB$M_NOREADACC 0x40#define CCB$M_NOWRITEACC 0x80#define CCB$M_CLONE 0x100  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; struct _irp; struct _wcb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cc b {#pragma __nomember_alignmentN struct _ucb *ccb$l_ucb; /*ADDRESS OF ASSIGNED DEVICE UCB */ __union {N unsigned int ccb$l_sts; /*CHANNEL STATUS */ __struct {N unsigned ccb$v_amb : 1; /* MAILBOX ASSOCIATED WITH CHANNEL */N unsigned ccb$v_imgtmp : 1; /* IMAGE TEMPORARY */N unsigned ccb$v_rdchkdon : 1; /* READ PROTECTION CHECK COMPLETED */P unsigned ccb$v_wrtch kdon : 1; /* WRITE PROTECTION CHECK COMPLETED */N unsigned ccb$v_logchkdon : 1; /* LOGICAL I/O ACCESS CHECK DONE */N unsigned ccb$v_phychkdon : 1; /* PHYSICAL I/O ACCESS CHECK DONE */N unsigned ccb$v_noreadacc : 1; /* READ ACCESS TO DEVICE DISABLED */P unsigned ccb$v_nowriteacc : 1; /* WRITE ACCESS TO DEVICE DISABLED */N unsigned ccb$v_clone : 1; /* Clone channel after Posix fork() */' unsigned ccb$v_fill_0_ : 7; } ccb$r_sts_bits; } ccb$r_sts_overlay;\ unsigned int ccb$l_ioc; /* Number of outstanding I/O requests on channel */Q struct _irp *ccb$l_dirp; /*DEACCESS I/O REQUEST PACKET ADDRESS */O char ccb$b_amod; /*ACCESS MODE THAT ASSIGNED CHANNEL */ unsigned char ccb$b_spare_1;% unsigned short int ccb$w_spare_2;N struct _wcb *ccb$l_wind; /* Address of Window Control Block */ __union {N int ccb$l_chan; /* associated channel number */& unsigned short int ccb$w_chan; } ccb$r_chan_overlay; int ccb$l_reserved; } CCB; #if !defined(__VAXC)-#define ccb$l_sts ccb$r_sts_overlay.ccb$l_sts<#define ccb$v_amb ccb$r_sts_overlay.ccb$r_sts_bits.ccb$v_ambB#define ccb$v_imgtmp ccb$r_sts_overlay.ccb$r_sts_bits.ccb$v_imgtmpF#define ccb$v_rdchkdon ccb$r_sts_overlay.ccb$r_sts_bits.ccb$v_rdchkdonH#define ccb$v_wrtchkdon ccb$r_sts_overlay.ccb$r_sts_bits.ccb$v_wrt chkdonH#define ccb$v_logchkdon ccb$r_sts_overlay.ccb$r_sts_bits.ccb$v_logchkdonH#define ccb$v_phychkdon ccb$r_sts_overlay.ccb$r_sts_bits.ccb$v_phychkdonH#define ccb$v_noreadacc ccb$r_sts_overlay.ccb$r_sts_bits.ccb$v_noreadaccJ#define ccb$v_nowriteacc ccb$r_sts_overlay.ccb$r_sts_bits.ccb$v_nowriteacc@#define ccb$v_clone ccb$r_sts_overlay.ccb$r_sts_bits.ccb$v_clone0#define ccb$l_chan ccb$r_chan_overlay.ccb$l_chan0#define ccb$w_chan ccb$r_chan_overlay.ccb$w_chan"#endif /* #if !defined(__VAXC) */  N#define CCB$K_LENGTH 32 /*LENGTH OF CCB */Q#define CCB$S_CCBDEF 32 /*OLD SIZE NAME, SYNONYM FOR CCB$S_CCB */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CCBDEF_LOADED */ ww  /* WARNING: aggregate element "cdl$w_maxconidx" ignored */> /* WARNING: aggregate element "cdldef$$_fill_1" ignored */< /* WARNING: aggregate element "cdl$l_freecdt" ignored */9 /* WARNING: aggregate element "cdl$w_size" ignored */9 /* WARNING: aggregate element "cdl$b_type" ignored */; /* WARNING: aggregate element "cdl$b _subtyp" ignored */> /* WARNING: aggregate element "cdl$l_nocdt_cnt" ignored */N void *cdl$l_base; /*BASE OF THE TABLE */ } CDL; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CDLDEF_LOADED */   wwZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/* * 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Sof tware, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:17 by OpenVMS SDL V3.7 */G/* Source: 24-JUL-2023 11:46:14 $1$DGA8345:[LIB_H.SRC]CDRPDEF.SDL;1 *//*********************** *********************************************************************************************************//*** MODULE $CDRPDEF ***/#ifndef __CDRPDEF_LOADED#define __CDRPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr siz e */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CDRP - CLASS DRIVER I/O REQUEST PACKET */N/* */N/* This structure contains within it, at negative offsets, a full IRP. */N/* For this reason all IRP fields must be at the same relative offsets */N/* as the corresponding fields in the IRP. */N/* */O/* NOTE: The equivalency of these IRP and CDRP offsets is verified by ASSUME */P/* statements in the [LIB]VFY_IRP_A_LIKES.MAR module. These ASSUMEs may need */P/* to be altered as well whenever an CDRP or IRP field is removed or altered. */N/*- */  Y#include /* Define the IOBD type; IRP contains an embedded  IOBD */#define CDRP$M_WLE_REUSE 0x1#define CDRP$M_WLE_SUPWL 0x2#define CDRP$K_CDRPBASE 0#define CDRP$C_CDRPBASE 0N#define CDRP$C_RSPID_WAIT 1 /* Waiting for Rspid Resource */N#define CDRP$C_POOL_WAIT 2 /* Waiting for Pool Resource */N#define CDRP$C_CREDIT_WAIT 3 /* Waiting for Credit Resource */U#define CDRP$C_BD_WAIT 4 /* Waiting for Buffer Descriptor Resource */ #define CDRP$M_SYSAP_STALLED 0x1#define CDRP$M_RBU N_WANTED 0x2#define CDRP$K_LENGTH 80#define CDRP$C_LENGTH 80I/* CDRP extensions */#define CDRP$K_BT_LEN 96#define CDRP$C_BT_LEN 96#define CDRP$M_CAND 0x1#define CDRP$M_CANIO 0x2#define CDRP$M_ERLIP 0x4#define CDRP$M_PERM 0x8#define CDRP$M_HIRT 0x10#define CDRP$M_DENSCK 0x20#define CDRP$M_CONNWALK 0x40#define CDRP$M_COPYSHAD 0x80#define CDRP$M_IVCMD 0x100#define CDRP$M_WALK_2P 0x200#define CDRP$M_LOC_ONLY 0x400#def  ine CDRP$M_LOADBAL 0x800#define CDRP$M_NORETRY 0x1000#define CDRP$M_INTERNAL 0x2000#define CDRP$M_DRAIN 0x4000#define CDRP$K_CD_LEN 144#define CDRP$C_CD_LEN 144[#define CDRP$K_NORMAL 0 /* The standard case (particulary no block xfer) */N#define CDRP$K_REQUESTOR 1 /* Block transfer requestor */N#define CDRP$K_PARTNER 2 /* Block transfer partner, active */N#define CDRP$K_PART_IDLE 3 /* Block transfer partner, idle  */a#define CDRP$K_REQ_MAP 4 /* Block transfer requestor, waiting for buffer handle */_#define CDRP$K_PART_MAP 5 /* Block transfer partner, waiting for buffer handle */X#define CDRP$K_PART_FORK_WAIT 6 /* Block transfer partner, on fork_wait queue */N#define CDRP$K_CNX_MSG 0 /* Send message */N#define CDRP$K_CNX_BLKRD 1 /* Block read */N#define CDRP$K_CNX_BLKWRT 2 /* Block write  */N#define CDRP$K_CNX_REQ 3 /* Request block xfer */#define CDRP$M_HAVE_SYNCH 0x1#define CDRP$M_MSGBLD_SYNCH 0x2#define CDRP$M_CPL_SYNCH 0x4#define CDRP$M_STALL_SYNCH 0x8!#define CDRP$M_RM_BLKRD_DONE 0x10##define CDRP$M_RM_XFRPROC_DONE 0x20#define CDRP$K_CM_LENGTH 232[#define CDRP$K_VCNX_NORMAL 0 /* The standard case (particulary no block xfer) */N#define CDRP$K_VCNX_REQUESTOR 1 /* Block transfer requestor  */N#define CDRP$K_VCNX_PARTNER 2 /* Block transfer partner, active */N#define CDRP$K_VCNX_PART_IDLE 3 /* Block transfer partner, idle */a#define CDRP$K_VCNX_REQ_MAP 4 /* Block transfer requestor, waiting for buffer handle */_#define CDRP$K_VCNX_PART_MAP 5 /* Block transfer partner, waiting for buffer handle */%#define CDRP$M_CDRP_PARTNER_VALID 0x1"#define CDRP$M_XMT_CDRP_BLKXFR 0x2"#define CDRP$M_XMT_REQ_SUCCESS 0x4 #define CDRP$M_XMT_XFER_DONE 0  x8!#define CDRP$M_PARTNER_ABORT 0x10 #define CDRP$M_XMT_NOTIFIED 0x20#define CDRP$M_XMT_SEGMENT 0x40#define CDRP$M_XMT_MUX_MSG 0x80N#define CDRP$K_VCNX_MSG 0 /* Normal messages */N#define CDRP$K_VCNX_BLKRD 1 /* Block transfer read */N#define CDRP$K_VCNX_BLKWRT 2 /* Block transfer write */N#define CDRP$K_VCNX_REQ 3 /* Requestor */#define CDRP$K_SCATP_LENGTH 176N#define CD RP$K_IDLE 0 /* CDRP is idle */N#define CDRP$K_ALLOC_MSG_BUF 1 /* Allocate message in progress */N#define CDRP$K_RECYCLE_MSG_BUF 2 /* Message is being recycled */N#define CDRP$K_MAP 3 /* Map wait is in progress */N#define CDRP$K_SEND_DATA 4 /* Block transfer is in progress */N#define CDRP$K_SEND_MSG 5 /* Message sending in progress */N#define CDRP$K_ALLOC_RSPID 6  /* Allocate rspid in progress */#define CDRP$K_SDA_LEN 168#define CDRP$C_SDA_LEN 168  9#ifdef __cplusplus /* Define structure prototypes */ struct _irp; struct _wcb; struct _ucb; struct _shad; struct _hrb;struct _bufio; struct _irpe;struct _fdt_context; struct _arb; struct _kpb; struct _ccb; struct _cdt; struct _vcrp; struct _tlcb;struct _rcvreq; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* I  f using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifBtypedef struct _cdrp { /* WARNING: aggregate has origin of -616 */; /* WARNING: aggregate element "cdrp$l_ioqfl" ignored */; /* WARNING: aggregate element "cdrp$l_ioqbl" ignored */> /* WARNING: aggregate element "cdrp$w_irp_size" ignored */> /* WARNING: aggregate element "cdrp$b_irp_type" ignored */: /* WARNING: aggregate element "cdrp$b_rmod" ignored */9  /* WARNING: aggregate element "cdrp$l_pid" ignored */C /* WARNING: aggregate element "cdrp$l_acb64x_offset" ignored */B /* WARNING: aggregate element "cdrp$l_param_0_fill" ignored */? /* WARNING: aggregate element "cdrp$l_acb_flags" ignored */@ /* WARNING: aggregate element "cdrp$l_thread_pid" ignored */B /* WARNING: aggregate element "cdrp$r_wind_overlay" ignored */9 /* WARNING: aggregate element "cdrp$l_ucb" ignored */G /* WARNING: aggregate element "cdrp$r_acb64_ast_  overlay" ignored */J /* WARNING: aggregate element "cdrp$r_acb64_astprm_overlay" ignored */D /* WARNING: aggregate element "cdrp$q_user_thread_id" ignored */9 /* WARNING: aggregate element "cdrp$b_efn" ignored */9 /* WARNING: aggregate element "cdrp$b_pri" ignored */> /* WARNING: aggregate element "cdrp$b_cln_indx" ignored */G /* WARNING: aggregate element "cdrp$r_wlg_flags_overlay" ignored *// /* WARNING: aggregate element "" ignored */: /* WARNING: aggregate elem  ent "cdrp$l_chan" ignored */= /* WARNING: aggregate element "cdrp$r_fill_0_" ignored */= /* WARNING: aggregate element "cdrp$r_fill_2_" ignored */= /* WARNING: aggregate element "cdrp$pq_va_pte" ignored */D /* WARNING: aggregate element "cdrp$r_svapte_overlay" ignored */: /* WARNING: aggregate element "cdrp$l_bcnt" ignored */: /* WARNING: aggregate element "cdrp$l_boff" ignored */; /* WARNING: aggregate element "cdrp$l_oboff" ignored */< /* WARNING: aggregate elemen  t "cdrp$l_extend" ignored */B /* WARNING: aggregate element "cdrp$ps_fdt_context" ignored */> /* WARNING: aggregate element "cdrp$b_fill_25_" ignored */@ /* WARNING: aggregate element "cdrp$q_fill_diobm" ignored *// /* WARNING: aggregate element "" ignored */: /* WARNING: aggregate element "cdrp$r_iobd" ignored */= /* WARNING: aggregate element "cdrp$pq_extent" ignored */B /* WARNING: aggregate element "cdrp$pq_orig_extent" ignored */A /* WARNING: aggregate element "c drp$l_extent_boff" ignored */F /* WARNING: aggregate element "cdrp$l_orig_extent_boff" ignored */= /* WARNING: aggregate element "cdrp$r_fill_4_" ignored */G /* WARNING: aggregate element "cdrp$r_nt_prvmsk_overlay" ignored */B /* WARNING: aggregate element "cdrp$r_func_overlay" ignored */= /* WARNING: aggregate element "cdrp$r_fill_6_" ignored */D /* WARNING: aggregate element "cdrp$r_segvbn_overlay" ignored */E /* WARNING: aggregate element "cdrp$r_diagbuf_overlay" ign  ored */D /* WARNING: aggregate element "cdrp$r_seqnum_overlay" ignored */9 /* WARNING: aggregate element "cdrp$l_arb" ignored */E /* WARNING: aggregate element "cdrp$r_keydesc_overlay" ignored */: /* WARNING: aggregate element "cdrp$ps_kpb" ignored */: /* WARNING: aggregate element "cdrp$ps_ccb" ignored */= /* WARNING: aggregate element "cdrp$r_fill_8_" ignored */> /* WARNING: aggregate element "cdrp$r_fill_10_" ignored */> /* WARNING: aggregate element "cdrp$r_fill  _12_" ignored */> /* WARNING: aggregate element "cdrp$r_fill_14_" ignored */> /* WARNING: aggregate element "cdrp$r_fill_16_" ignored */> /* WARNING: aggregate element "cdrp$r_fill_18_" ignored */< /* WARNING: aggregate element "cdrp$q_lbn_64" ignored */N/* ALL FIELDS INSERTED ABOVE THIS POINT IN THE CDRP */N/* MUST BE CHANGED IN THE IRPDEF.SDL FILE. */ N/*  */N/* */#pragma __nomember_alignmentN struct _cdrp *cdrp$l_fqfl; /* Fork Queue FLINK */N struct _cdrp *cdrp$l_fqbl; /* Fork Queue Blink */S unsigned short int cdrp$w_cdrpsize; /* Size field for positive section only */N unsigned char cdrp$b_cd_type; /* Type, always of interest */N unsigned char cdrp$b_flck; /* Fork lock  */N void (*cdrp$l_fpc)(); /* Fork PC */N __int64 cdrp$q_fr3; /* Fork R3 */N __int64 cdrp$q_fr4; /* Fork R4 */T void (*cdrp$l_savd_rtn)(); /* Saved return address from level 1 JSB */O void *cdrp$l_msg_buf; /* Address of allocated MSCP buffer */N unsigned int cdrp$l_rspid; /* Allocated Request ID */! U struct _cdt *cdrp$l_cdt; /* Address of Connection Descriptor Table */ __union {Y unsigned __int64 cdrp$q_res_wait_state; /* SCS Resource Wait State Information */ __struct {q unsigned int cdrp$l_wait_state; /* SCS Resource Wait State: >0 = SCS Wait, <0 = Port-specific Wait */N/* Possible SCS states: */ __union {N unsigned int cdrp$l_scs_state; /* SCS State bits: " */ __struct {m unsigned cdrp$v_sysap_stalled : 1; /* SYSAP context has been saved in CDRP fork block */\ unsigned cdrp$v_rbun_wanted : 1; /* RBUN was wanted but none existed */1 unsigned cdrp$v_fill_26_ : 6;& } cdrp$r_fill_21_;" } cdrp$r_fill_20_;) } cdrp$r_scs_resource_fields;& } cdrp$r_scs_resource_overlay;] int cdrp$l_scs_stall_data; /* D # ata cell used by SCS to save data over a stall */N short int *cdrp$l_rwcptr; /* RWAITCNT pointer */_ void *cdrp$l_bd_addr; /* Address of Buffer Descriptor that maps I/O buffer */N void *cdrp$l_rbun; /* Address of Resource Bundle */N void *cdrp$l_lbufh_ad; /* Local BUFfer Handle ADress */ char cdrp$b_fill_27_ [4];  __union {I/* Block Transfer Extension $ */ __struct {N unsigned int cdrp$l_lboff; /* Local Byte OFFset */N void *cdrp$l_rbufh_ad; /* Remote BUFfer Handle ADress */N unsigned int cdrp$l_rboff; /* Remote Byte OFFset */N unsigned int cdrp$l_xct_len; /* Transfer length in bytes */( } cdrp$r_blk_xfer_extension;I/* Class Driver Extension */ __struct {N % char cdrp$t_lbufhndl [12]; /* Local buffer handle */] unsigned int cdrp$l_ubarsrce; /* Scratch Cell used for DU/TUDRIVER convenience */ __union {O unsigned int cdrp$l_dutuflags; /* Class driver status flags: */ __struct {N unsigned cdrp$v_cand : 1; /* canceled I/O request */R unsigned cdrp$v_canio : 1; /* cancel operation I/O request */N unsigned cdrp$v_erlip & : 1; /* error log in progress */N unsigned cdrp$v_perm : 1; /* CDDB permanent IRP/CDRP */N unsigned cdrp$v_hirt : 1; /* HIRT permanent IRP/CDRP */R unsigned cdrp$v_densck : 1; /* Tape density check required */S unsigned cdrp$v_connwalk : 1; /* Thread walking connections */_ unsigned cdrp$v_copyshad : 1; /* CDRP represents an active IO$_COPYSHAD */\ unsigned cdrp$v_ivcm' d : 1; /* Invalid command processing in progress */u unsigned cdrp$v_walk_2p : 1; /* Thread trying secondary path before walking other connections */v unsigned cdrp$v_loc_only : 1; /* VMS MSCPservers are to be ignored during this connection walk */m unsigned cdrp$v_loadbal : 1; /* A load balancing pass of connection walking is active */s unsigned cdrp$v_noretry : 1; /* Don't retry this cdrp if connection fails, post( it instead. */O unsigned cdrp$v_internal : 1; /* Internal tempory CDRP. */g unsigned cdrp$v_drain : 1; /* This CDRP set UCB's MSCP_LOCAL_DRAIN_WAITBMP bit. */1 unsigned cdrp$v_fill_28_ : 1;& } cdrp$r_fill_23_;" } cdrp$r_fill_22_;N unsigned short int cdrp$w_dutucntr; /* General purpose counter */[ unsigned short int cdrp$w_endmsgsiz; /* Size of most recent MSCP end message */) N unsigned int cdrp$l_pdt; /* PDT for this CDRP */N unsigned int cdrp$l_cddb; /* Current CDDB */N unsigned int cdrp$l_walk_state; /* State for connection walking */f unsigned int cdrp$l_walk_svpc; /* Return address for resumption from connection walking */N unsigned int cdrp$l_lb_cddb; /* Load balancing CDDB */% char cdrp$b_fill_29_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && * !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif+ unsigned int cdrp$l_dutu_rsvd1;#pragma __nomember_alignment+ unsigned int cdrp$l_dutu_rsvd2;+ unsigned int cdrp$l_dutu_rsvd3;+ unsigned int cdrp$l_dutu_rsvd4;' } cdrp$r_cls_drv_extension;I/* Connection management extension */ __struct { + __union { __struct { __union {N unsigned int cdrp$l_val1; /* data value 1 */N unsigned __int64 cdrp$q_val1; /* data value 1 */. } cdrp$r_val1_overlay; __union {N unsigned int cdrp$l_val2; /* data value 2 */N unsigned __int64 cdrp$q_val2; /* data value 2 */. , } cdrp$r_val2_overlay;N unsigned int cdrp$l_val3; /* data value 3 */N unsigned int cdrp$l_val4; /* data value 4 */N unsigned int cdrp$l_val5; /* data value 5 */- char cdrp$b_fill_30_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif - __union {N unsigned __int64 cdrp$q_val6; /* data value 6 */#pragma __nomember_alignmentN unsigned int cdrp$l_val6; /* data value 6 */. } cdrp$r_val6_overlay;N unsigned int cdrp$l_val7; /* data value 7 */N unsigned int cdrp$l_val8; /* data value 8 */N unsigned int cdrp$l_val9; /* data value 9 */. N unsigned int cdrp$l_val10; /* data value 10 */N unsigned int cdrp$l_val11; /* data value 11 */N unsigned int cdrp$l_val12; /* data value 12 */- } cdrp$r_cnx_client_data; __struct {, int cdrp$l_fill_val [7];- char cdrp$b_fill_31_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or / C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cdrp$pq_cnxsvapte_sva; /* NOSVAPTE_V9.0 cmos */#else( unsigned __int64 cdrp$pq_cnxsvapte_sva;#endif#pragma __nomember_alignmentN unsigned int cdrp$l_cnxbcnt; /* Block xfer l0 ength */P unsigned short int cdrp$w_cnxboff; /* Block buffer offset */N unsigned char cdrp$b_cnxrmod; /* Block access mode */N unsigned char cdrp$b_cltsts; /* A client's status field */, } cdrp$r_cnx_block_xfer;' } cdrp$r_cnx_work_area;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32- 1 bit pointers */#endifN int (*cdrp$l_msgbld)(); /* Address of MSG BUILD routine */N int (*cdrp$l_savepc)(); /* Caller's saved PC */N unsigned short int cdrp$w_sendseqnm; /* Message sequence number */N unsigned char cdrp$b_cnxstate; /* CNX message state */N/* Possible states: */N unsigned char cdrp$b_cnx_function; /* Function code */N2 /* Possible states: */N unsigned int cdrp$l_retrspid; /* RSPID to return */N __union { /* Lock Manager flags overlay */N unsigned int cdrp$l_lckmgr_flags; /* Lock Manager flags */N __struct { /* Lock Manager Bits */` unsigned cdrp$v_have_synch : 1; /* This thread has LCKMGR Synchronization */g 3 unsigned cdrp$v_msgbld_synch : 1; /* MSGBLD Routine needs LCKMGR Synchronization */j unsigned cdrp$v_cpl_synch : 1; /* Completion call back needs LCKMGR Synchronziation */k unsigned cdrp$v_stall_synch : 1; /* CDRP is stalled to obtain LCKMGR Synchronization */c unsigned cdrp$v_rm_blkrd_done : 1; /* Remaster block xfer read has completed */n unsigned cdrp$v_rm_xfrproc_done : 1; /* Remaster processing on block 4 xfer has completed */1 unsigned cdrp$v_fill_32_ : 2;. } cdrp$r_lckmgr_flag_bits;N/* */. } cdrp$r_lckmgr_flags_overlay;N/* */% char cdrp$b_fill_33_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __q5 uadword#else#pragma __nomember_alignment#endifN __union { /* data value 13 */. unsigned __int64 cdrp$q_val13;#pragma __nomember_alignment* unsigned int cdrp$l_val13;' } cdrp$r_val13_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __un 6 ion { /* data value 14 */* unsigned int cdrp$l_val14;#pragma __nomember_alignment. unsigned __int64 cdrp$q_val14;' } cdrp$r_val14_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __union { /* data value 15 */* 7 unsigned int cdrp$l_val15;#pragma __nomember_alignment. unsigned __int64 cdrp$q_val15;' } cdrp$r_val15_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __union { /* data value 16 */* unsigned int cdrp$l_val16;#pragma __nomember_alignment. 8 unsigned __int64 cdrp$q_val16;' } cdrp$r_val16_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __union { /* data value 17 */* unsigned int cdrp$l_val17;#pragma __nomember_alignment. unsigned __int64 cdrp$q_val17;' } cdrp$r_val17 9 _overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __union { /* data value 18 */* unsigned int cdrp$l_val18;#pragma __nomember_alignment. unsigned __int64 cdrp$q_val18;' } cdrp$r_val18_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus : ) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __union { /* data value 19 */* unsigned int cdrp$l_val19;#pragma __nomember_alignment. unsigned __int64 cdrp$q_val19;' } cdrp$r_val19_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment _; _quadword#else#pragma __nomember_alignment#endifN __union { /* data value 20 */* unsigned int cdrp$l_val20;#pragma __nomember_alignment. unsigned __int64 cdrp$q_val20;' } cdrp$r_val20_overlay;' } cdrp$r_con_mgt_extension;I/* IPC SCA Transport extension */ __struct { __union { __struct {N < unsigned int cdrp$l_scatp_val1; /* data value 1 */N unsigned int cdrp$l_scatp_val2; /* data value 2 */N unsigned int cdrp$l_scatp_val3; /* data value 3 */N unsigned int cdrp$l_scatp_val4; /* data value 4 */N unsigned int cdrp$l_scatp_val5; /* data value 5 */N unsigned int cdrp$l_scatp_val6; /* data value 6 */N unsigned int cdr = p$l_scatp_val7; /* data value 7 */N unsigned int cdrp$l_scatp_val8; /* data value 8 */. } cdrp$r_vcnx_client_data; __struct {0 int cdrp$l_vcnxfill_val [5];- char cdrp$b_fill_34_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL > _POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cdrp$pq_vcnxsvapte_sva; /* NOSVAPTE_V9.0 cmos */#else) unsigned __int64 cdrp$pq_vcnxsvapte_sva;#endif#pragma __nomember_alignmentg unsigned int cdrp$l_vcnxbcnt; /* Block xfer length NOTE these two fields are the */n unsigned short int cdrp$w_vcnxboff; /* Block buffe ? r offset NOTE other way round on VAX */N unsigned char cdrp$b_vcnxrmod; /* Block access mode */T unsigned char cdrp$b_scatp_cltsts; /* A client's status field */- } cdrp$r_vcnx_block_xfer;( } cdrp$r_vcnx_work_area;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN int (*cdrp@ $l_scatp_msgbld)(); /* Address of MSG BUILD routine */* void (*cdrp$l_scatp_savepc)();N/* Caller's saved PC */T unsigned short int cdrp$w_scatp_sendseqnm; /* Message sequence number */N unsigned char cdrp$b_vcnxstate; /* VCNX message state */N/* Possible states: */N __union { /* */A N unsigned char cdrp$b_scatp_flags; /* FLAGS byte */N __struct { /* */\ unsigned cdrp$v_cdrp_partner_valid : 1; /* The CDRP_PARTNER has valid */N/* data. */Z unsigned cdrp$v_xmt_cdrp_blkxfr : 1; /* This is block transfer CDRP */T unsigned cdrp$v_xmt_req_success : 1; /* The transmit requeB st */N/* processing is done */N/* successfully for this CDRP. */S unsigned cdrp$v_xmt_xfer_done : 1; /* The data transfer is */N/* completed for this CDRP. */Q unsigned cdrp$v_partner_abort : 1; /* This block transfer */N/* request is aborted by */N/* partnC er node. */Y unsigned cdrp$v_xmt_notified : 1; /* Indicates that the associated */N/* VCRP has been returned to */N/* the user */Q unsigned cdrp$v_xmt_segment : 1; /* Indicates this is part */N/* of a larger message */Q D unsigned cdrp$v_xmt_mux_msg : 1; /* Indicates this message */N/* has Session multiplexed */N/* link protocol header */- } cdrp$r_scatp_flag_bits;N/* */+ } cdrp$r_scatp_flags_union;N/* */N unsigned int cE drp$l_scatp_retrspid; /* RSPID to return */N struct _cdrp *cdrp$l_cdrp_partner; /* Partner's CDRP/RCVREQ */N struct _vcrp *cdrp$l_vcrp; /* VCRP addr */N struct _tlcb *cdrp$l_tlcb; /* TLCB address */N struct _rcvreq *cdrp$l_rcvreq; /* RCVREQ address */N int (*cdrp$l_save_ret)(); /* Saved caller's */N/* return PC. F */N struct _tlcb *cdrp$l_tlcbfqfl; /* Fork queue (in TLCB) flink */N struct _tlcb *cdrp$l_tlcbfqbl; /* Fork queue (in TLCB) blink */N unsigned int cdrp$l_disc_reason; /* Disconnect reason */N/* for DI msg. */P unsigned int cdrp$l_saved_status; /* Save the status for the VCRP */N unsigned char cdrp$b_vcnx_function; /* VCNX function G */N/* Possible functions: */N char cdrp$t_align [3]; /* QUADWORD ALIGN */% } cdrp$r_scatp_extension;I/* Remote SDA Extension */ __struct {N/* Reserve space for block transfer extension */$ char cdrp$t_bt_ext [16];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V H 4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cdrp$pq_mysvapte_sva; /* NOSVAPTE_V9.0 cmos */#else' unsigned __int64 cdrp$pq_mysvapte_sva;#endif#pragma __nomember_alignmentN unsigned int cdrp$l_mybcnt; /* Byte Count I */N unsigned int cdrp$l_myboff; /* Byte Offset */N char cdrp$t_mybufhdl [12]; /* Buffer handle */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *cdrp$l_savd_msg_buf; /* Saved message buffer address */N/* during a BLOCK Transfer J */N unsigned int cdrp$l_savd_msg_siz; /* Saved message size */% char cdrp$b_fill_35_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ K N void *cdrp$pq_virt_addr; /* 64-bit Virtual Address */#else$ unsigned __int64 cdrp$pq_virt_addr;#endif#pragma __nomember_alignmentN unsigned int cdrp$l_sda_bcnt; /* Byte Count */N unsigned int cdrp$l_sda_pid; /* Process ID */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment L #endifN unsigned __int64 cdrp$q_pte; /* Target PTE */#pragma __nomember_alignmentN unsigned int cdrp$l_cpu; /* Target CPU */N unsigned short int cdrp$w_state; /* CDRP state */N/* Possible states: */N unsigned short int cdrp$w_blk_status; /* Block transfer status */# } cdrp$r_sda_extension;! } cdrp$r_cdrp_extens M ions; } CDRP; #if !defined(__VAXC)3#define cdrp$l_wind cdrp$r_wind_overlay.cdrp$l_wind3#define cdrp$l_mirp cdrp$r_wind_overlay.cdrp$l_mirp3#define cdrp$l_kast cdrp$r_wind_overlay.cdrp$l_kastD#define cdrp$pq_acb64_ast cdrp$r_acb64_ast_overlay.cdrp$pq_acb64_ast@#define cdrp$l_shd_iofl cdrp$r_acb64_ast_overlay.cdrp$l_shd_iofl>#define cdrp$l_iirp_p0 cdrp$r_acb64_ast_overlay.cdrp$l_iirp_p0K#define cdrp$q_acb64_astprm cdrp$r_acb64_astprm_overlay.cdrp$q_acb64_astprm;#define cdrp$l_shaN d cdrp$r_acb64_astprm_overlay.cdrp$l_shad9#define cdrp$l_hrb cdrp$r_acb64_astprm_overlay.cdrp$l_hrb?#define cdrp$l_mv_tmo cdrp$r_acb64_astprm_overlay.cdrp$l_mv_tmoA#define cdrp$l_iirp_p1 cdrp$r_acb64_astprm_overlay.cdrp$l_iirp_p1B#define cdrp$b_wlg_flags cdrp$r_wlg_flags_overlay.cdrp$b_wlg_flagsW#define cdrp$v_wle_reuse cdrp$r_wlg_flags_overlay.cdrp$r_wlg_flag_bits.cdrp$v_wle_reuseW#define cdrp$v_wle_supwl cdrp$r_wlg_flags_overlay.cdrp$r_wlg_flag_bits.cdrp$v_wle_supwl0#define cdrp$pq_iosbO cdrp$r_fill_0_.cdrp$pq_iosbW#define cdrp$l_cln_wle cdrp$r_fill_0_.cdrp$r_fill_1_.cdrp$r_iosb_overlay.cdrp$l_cln_wleW#define cdrp$l_iirp_p2 cdrp$r_fill_0_.cdrp$r_fill_1_.cdrp$r_iosb_overlay.cdrp$l_iirp_p22#define cdrp$q_status cdrp$r_fill_2_.cdrp$q_status;#define cdrp$l_sts cdrp$r_fill_2_.cdrp$r_fill_3_.cdrp$l_sts=#define cdrp$l_sts2 cdrp$r_fill_2_.cdrp$r_fill_3_.cdrp$l_sts2C#define cdrp$pq_svapte_sva cdrp$r_svapte_overlay.cdrp$pq_svapte_svaA#define cdrp$pq_bufio_pkt cdrp$r_svapte_overlay.P cdrp$pq_bufio_pkt7#define cdrp$ps_void cdrp$r_svapte_overlay.cdrp$ps_voidA#define cdrp$ps_bufio_pkt cdrp$r_svapte_overlay.cdrp$ps_bufio_pkt0#define cdrp$q_media cdrp$r_fill_4_.cdrp$q_mediaT#define cdrp$l_iost1 cdrp$r_fill_4_.cdrp$r_fill_5_.cdrp$r_iost1_overlay.cdrp$l_iost1T#define cdrp$l_media cdrp$r_fill_4_.cdrp$r_fill_5_.cdrp$r_iost1_overlay.cdrp$l_mediaT#define cdrp$l_iost2 cdrp$r_fill_4_.cdrp$r_fill_5_.cdrp$r_iost2_overlay.cdrp$l_iost2o#define cdrp$l_tt_term cdrp$r_fill_4_.cdrp$r_fill_5_Q .cdrp$r_iost2_overlay.cdrp$r_tt_term_overlay.cdrp$l_tt_termm#define cdrp$b_carcon cdrp$r_fill_4_.cdrp$r_fill_5_.cdrp$r_iost2_overlay.cdrp$r_tt_term_overlay.cdrp$b_carconB#define cdrp$q_nt_prvmsk cdrp$r_nt_prvmsk_overlay.cdrp$q_nt_prvmsk>#define cdrp$q_station cdrp$r_nt_prvmsk_overlay.cdrp$q_stationX#define cdrp$q_tt_state cdrp$r_nt_prvmsk_overlay.cdrp$r_tt_state_overlay.cdrp$q_tt_statei#define cdrp$l_abcnt cdrp$r_nt_prvmsk_overlay.cdrp$r_tt_state_overlay.cdrp$r_tt_state_fields.cdrp$l_abcnti#dR efine cdrp$l_obcnt cdrp$r_nt_prvmsk_overlay.cdrp$r_tt_state_overlay.cdrp$r_tt_state_fields.cdrp$l_obcnt3#define cdrp$l_func cdrp$r_func_overlay.cdrp$l_func8#define cdrp$l_dt_modifs cdrp$r_fill_6_.cdrp$l_dt_modifs`#define cdrp$w_dt_modifs cdrp$r_fill_6_.cdrp$r_fill_7_.cdrp$r_dt_modifs_overlay.cdrp$w_dt_modifsz#define cdrp$w_shd_mscp_disk_modifier cdrp$r_fill_6_.cdrp$r_fill_7_.cdrp$r_dt_modifs_overlay.cdrp$w_shd_mscp_disk_modifier9#define cdrp$q_segvbn cdrp$r_segvbn_overlay.cdrp$q_segvbn9#defin S e cdrp$l_segvbn cdrp$r_segvbn_overlay.cdrp$l_segvbn<#define cdrp$l_diagbuf cdrp$r_diagbuf_overlay.cdrp$l_diagbuf<#define cdrp$l_scb_buf cdrp$r_diagbuf_overlay.cdrp$l_scb_buf>#define cdrp$w_tt_prmpt cdrp$r_diagbuf_overlay.cdrp$w_tt_prmpt9#define cdrp$l_seqnum cdrp$r_seqnum_overlay.cdrp$l_seqnumC#define cdrp$l_dcd_src_ucb cdrp$r_seqnum_overlay.cdrp$l_dcd_src_ucb<#define cdrp$l_keydesc cdrp$r_keydesc_overlay.cdrp$l_keydesc<#define cdrp$l_wle_ptr cdrp$r_keydesc_overlay.cdrp$l_wle_ptr>#define cd T rp$b_cpy_mode cdrp$r_keydesc_overlay.cdrp$b_cpy_mode2#define cdrp$q_qio_p1 cdrp$r_fill_8_.cdrp$q_qio_p1A#define cdrp$l_qio_p1 cdrp$r_fill_8_.cdrp$r_fill_9_.cdrp$l_qio_p13#define cdrp$q_qio_p2 cdrp$r_fill_10_.cdrp$q_qio_p2C#define cdrp$l_qio_p2 cdrp$r_fill_10_.cdrp$r_fill_11_.cdrp$l_qio_p23#define cdrp$q_qio_p3 cdrp$r_fill_12_.cdrp$q_qio_p3C#define cdrp$l_qio_p3 cdrp$r_fill_12_.cdrp$r_fill_13_.cdrp$l_qio_p33#define cdrp$q_qio_p4 cdrp$r_fill_14_.cdrp$q_qio_p4C#define cdrp$l_qio_p4 cdrp$r_fU ill_14_.cdrp$r_fill_15_.cdrp$l_qio_p43#define cdrp$q_qio_p5 cdrp$r_fill_16_.cdrp$q_qio_p5C#define cdrp$l_qio_p5 cdrp$r_fill_16_.cdrp$r_fill_17_.cdrp$l_qio_p53#define cdrp$q_qio_p6 cdrp$r_fill_18_.cdrp$q_qio_p6C#define cdrp$l_qio_p6 cdrp$r_fill_18_.cdrp$r_fill_19_.cdrp$l_qio_p6O#define cdrp$q_res_wait_state cdrp$r_scs_resource_overlay.cdrp$q_res_wait_stateb#define cdrp$l_wait_state cdrp$r_scs_resource_overlay.cdrp$r_scs_resource_fields.cdrp$l_wait_statep#define cdrp$l_scs_state cdrp$r_scs_V resource_overlay.cdrp$r_scs_resource_fields.cdrp$r_fill_20_.cdrp$l_scs_state#define cdrp$v_sysap_stalled cdrp$r_scs_resource_overlay.cdrp$r_scs_resource_fields.cdrp$r_fill_20_.cdrp$r_fill_21_.cdrp$v_sysap_st\alled#define cdrp$v_rbun_wanted cdrp$r_scs_resource_overlay.cdrp$r_scs_resource_fields.cdrp$r_fill_20_.cdrp$r_fill_21_.cdrp$v_rbun_wantedR#define cdrp$l_lboff cdrp$r_cdrp_extensions.cdrp$r_blk_xfer_extension.cdrp$l_lboffX#define cdrp$l_rbufh_ad cdrp$r_cdrp_extensions.cdrp$r_blk_xfer_extenW sion.cdrp$l_rbufh_adR#define cdrp$l_rboff cdrp$r_cdrp_extensions.cdrp$r_blk_xfer_extension.cdrp$l_rboffV#define cdrp$l_xct_len cdrp$r_cdrp_extensions.cdrp$r_blk_xfer_extension.cdrp$l_xct_lenW#define cdrp$t_lbufhndl cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$t_lbufhndlW#define cdrp$l_ubarsrce cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$l_ubarsrcei#define cdrp$l_dutuflags cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$l_dutuflagso#define cdrp$v_cand cdrpX $r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_candq#define cdrp$v_canio cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_canioq#define cdrp$v_erlip cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_erlipo#define cdrp$v_perm cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_permo#define cdrp$v_hirt cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdY rp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_hirts#define cdrp$v_densck cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_densckw#define cdrp$v_connwalk cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_connwalkw#define cdrp$v_copyshad cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_copyshadq#define cdrp$v_ivcmd cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_Z .cdrp$v_ivcmdu#define cdrp$v_walk_2p cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_walk_2pw#define cdrp$v_loc_only cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_loc_onlyu#define cdrp$v_loadbal cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_loadbalu#define cdrp$v_noretry cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_noretryw#define [ cdrp$v_internal cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_internalq#define cdrp$v_drain cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$r_fill_22_.cdrp$r_fill_23_.cdrp$v_drainW#define cdrp$w_dutucntr cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$w_dutucntrY#define cdrp$w_endmsgsiz cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$w_endmsgsizM#define cdrp$l_pdt cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$l_pdtO#define cdrp$l\ _cddb cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$l_cddb[#define cdrp$l_walk_state cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$l_walk_stateY#define cdrp$l_walk_svpc cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$l_walk_svpcU#define cdrp$l_lb_cddb cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$l_lb_cddb[#define cdrp$l_dutu_rsvd1 cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$l_dutu_rsvd1[#define cdrp$l_dutu_rsvd2 cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extens] ion.cdrp$l_dutu_rsvd2[#define cdrp$l_dutu_rsvd3 cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$l_dutu_rsvd3[#define cdrp$l_dutu_rsvd4 cdrp$r_cdrp_extensions.cdrp$r_cls_drv_extension.cdrp$l_dutu_rsvd4#define cdrp$l_val1 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$r_val1_overlay\ .cdrp$l_val1#define cdrp$q_val1 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$r_val1_overlay\ .cdrp$q_val1^ #define cdrp$l_val2 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$r_val2_overlay\ .cdrp$l_val2#define cdrp$q_val2 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$r_val2_overlay\ .cdrp$q_val2{#define cdrp$l_val3 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$l_val3{#define cdrp$l_val4 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_wor_ k_area.cdrp$r_cnx_client_data.cdrp$l_val4{#define cdrp$l_val5 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$l_val5#define cdrp$q_val6 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$r_val6_overlay\ .cdrp$q_val6#define cdrp$l_val6 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$r_val6_overlay\ .cdrp$l_val6{#define cdrp$l_val7 cdrp$r_cdrp_extensio` ns.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$l_val7{#define cdrp$l_val8 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$l_val8{#define cdrp$l_val9 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$l_val9}#define cdrp$l_val10 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$l_val10}#define cdrp$l_val11 cdrp$r_cdrp_extensia ons.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$l_val11}#define cdrp$l_val12 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_client_data.cdrp$l_val12#define cdrp$l_fill_val cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_block_xfer.cdrp$l_fill_val#define cdrp$pq_cnxsvapte_sva cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_block_xfer.cdrp$pq_cn\ xsvapte_sva#define cdb rp$l_cnxbcnt cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_block_xfer.cdrp$l_cnxbcnt#define cdrp$w_cnxboff cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_block_xfer.cdrp$w_cnxboff#define cdrp$b_cnxrmod cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_block_xfer.cdrp$b_cnxrmod~#define cdrp$b_cltsts cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_cnx_work_area.cdrp$r_cnx_block_xfer.cdrp$b_cltstsc S#define cdrp$l_msgbld cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$l_msgbldS#define cdrp$l_savepc cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$l_savepcY#define cdrp$w_sendseqnm cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$w_sendseqnmW#define cdrp$b_cnxstate cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$b_cnxstate_#define cdrp$b_cnx_function cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$b_cnx_functionW#define cdrp$l_retrspid cdrp$r_cdrp_extensions.cdrp$d r_con_mgt_extension.cdrp$l_retrspid{#define cdrp$l_lckmgr_flags cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_lckmgr_flags_overlay.cdrp$l_lckmgr_flags#define cdrp$v_have_synch cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_lckmgr_flags_overlay.cdrp$r_lckmgr_flag_bits.cdrp$\ v_have_synch#define cdrp$v_msgbld_synch cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_lckmgr_flags_overlay.cdrp$r_lckmgr_flag_bits.cdr\p$v_msgbld_synch#define cdrp$v_cpl_synch cdrp$r_cdrp_extene sions.cdrp$r_con_mgt_extension.cdrp$r_lckmgr_flags_overlay.cdrp$r_lckmgr_flag_bits.cdrp$v\ _cpl_synch#define cdrp$v_stall_synch cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_lckmgr_flags_overlay.cdrp$r_lckmgr_flag_bits.cdrp\$v_stall_synch#define cdrp$v_rm_blkrd_done cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_lckmgr_flags_overlay.cdrp$r_lckmgr_flag_bits.cd\rp$v_rm_blkrd_done#define cdrp$v_rm_xfrproc_done cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_lckmgr_flagsf _overlay.cdrp$r_lckmgr_flag_bits.\cdrp$v_rm_xfrproc_donef#define cdrp$q_val13 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val13_overlay.cdrp$q_val13f#define cdrp$l_val13 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val13_overlay.cdrp$l_val13f#define cdrp$l_val14 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val14_overlay.cdrp$l_val14f#define cdrp$q_val14 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val14_overlay.cdrp$q_val14f#define cdrp$l_val15 cdrp$r_cdg rp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val15_overlay.cdrp$l_val15f#define cdrp$q_val15 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val15_overlay.cdrp$q_val15f#define cdrp$l_val16 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val16_overlay.cdrp$l_val16f#define cdrp$q_val16 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val16_overlay.cdrp$q_val16f#define cdrp$l_val17 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val17_overlay.cdrp$l_val17f#define cdrp$q_vh al17 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val17_overlay.cdrp$q_val17f#define cdrp$l_val18 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val18_overlay.cdrp$l_val18f#define cdrp$q_val18 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val18_overlay.cdrp$q_val18f#define cdrp$l_val19 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val19_overlay.cdrp$l_val19f#define cdrp$q_val19 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val19_overlay.cdrp$q_val19f#di efine cdrp$l_val20 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val20_overlay.cdrp$l_val20f#define cdrp$q_val20 cdrp$r_cdrp_extensions.cdrp$r_con_mgt_extension.cdrp$r_val20_overlay.cdrp$q_val20#define cdrp$l_scatp_val1 cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_client_data.cdrp$l_scatp_\val1#define cdrp$l_scatp_val2 cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_client_data.cdrp$l_scatp_\val2#define cdrp$l_scatpj _val3 cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_client_data.cdrp$l_scatp_\val3#define cdrp$l_scatp_val4 cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_client_data.cdrp$l_scatp_\val4#define cdrp$l_scatp_val5 cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_client_data.cdrp$l_scatp_\val5#define cdrp$l_scatp_val6 cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_ k client_data.cdrp$l_scatp_\val6#define cdrp$l_scatp_val7 cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_client_data.cdrp$l_scatp_\val7#define cdrp$l_scatp_val8 cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_client_data.cdrp$l_scatp_\val8#define cdrp$pq_vcnxsvapte_sva cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_block_xfer.cdrp$pq_v\ cnxsvapte_sva#define cdrp$l_vcnxbcnt cdrp$r_cdrp_extensl ions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_block_xfer.cdrp$l_vcnxbcnt#define cdrp$w_vcnxboff cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_block_xfer.cdrp$w_vcnxboff#define cdrp$b_vcnxrmod cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_block_xfer.cdrp$b_vcnxrmod#define cdrp$b_scatp_cltsts cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_vcnx_work_area.cdrp$r_vcnx_block_xfer.cdrp$b_scatp\_cltsts]#define m cdrp$l_scatp_msgbld cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$l_scatp_msgbld]#define cdrp$l_scatp_savepc cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$l_scatp_savepcc#define cdrp$w_scatp_sendseqnm cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$w_scatp_sendseqnmW#define cdrp$b_vcnxstate cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$b_vcnxstatet#define cdrp$b_scatp_flags cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_scatp_flags_union.cdrp$b_scatp_flags#define cdrpn $v_cdrp_partner_valid cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_scatp_flags_union.cdrp$r_scatp_flag_bits.cdr\p$v_cdrp_partner_valid#define cdrp$v_xmt_cdrp_blkxfr cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_scatp_flags_union.cdrp$r_scatp_flag_bits.cdrp$v\_xmt_cdrp_blkxfr#define cdrp$v_xmt_req_success cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_scatp_flags_union.cdrp$r_scatp_flag_bits.cdrp$v\_xmt_req_success#define cdrp$v_xmt_xfer_done cdrp$r_cdrp_extensions.cdrpo $r_scatp_extension.cdrp$r_scatp_flags_union.cdrp$r_scatp_flag_bits.cdrp$v_x\ mt_xfer_done#define cdrp$v_partner_abort cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_scatp_flags_union.cdrp$r_scatp_flag_bits.cdrp$v_p\ artner_abort#define cdrp$v_xmt_notified cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_scatp_flags_union.cdrp$r_scatp_flag_bits.cdrp$v_xm\ t_notified#define cdrp$v_xmt_segment cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_scatp_flags_union.cdrp$r_scatp_flag_bitsp .cdrp$v_xmt\_segment#define cdrp$v_xmt_mux_msg cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$r_scatp_flags_union.cdrp$r_scatp_flag_bits.cdrp$v_xmt\_mux_msga#define cdrp$l_scatp_retrspid cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$l_scatp_retrspid]#define cdrp$l_cdrp_partner cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$l_cdrp_partnerM#define cdrp$l_vcrp cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$l_vcrpM#define cdrp$l_tlcb cdrp$r_cdrp_extensions.cdrp$r_scatp_extensq ion.cdrp$l_tlcbQ#define cdrp$l_rcvreq cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$l_rcvreqU#define cdrp$l_save_ret cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$l_save_retU#define cdrp$l_tlcbfqfl cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$l_tlcbfqflU#define cdrp$l_tlcbfqbl cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$l_tlcbfqbl[#define cdrp$l_disc_reason cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$l_disc_reason]#define cdrp$l_saved_status cdrp$r_cdrp_extensr ions.cdrp$r_scatp_extension.cdrp$l_saved_status_#define cdrp$b_vcnx_function cdrp$r_cdrp_extensions.cdrp$r_scatp_extension.cdrp$b_vcnx_function]#define cdrp$pq_mysvapte_sva cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$pq_mysvapte_svaO#define cdrp$l_mybcnt cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$l_mybcntO#define cdrp$l_myboff cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$l_myboffS#define cdrp$t_mybufhdl cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$t_mybufhdl[#define cdrps $l_savd_msg_buf cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$l_savd_msg_buf[#define cdrp$l_savd_msg_siz cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$l_savd_msg_sizW#define cdrp$pq_virt_addr cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$pq_virt_addrS#define cdrp$l_sda_bcnt cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$l_sda_bcntQ#define cdrp$l_sda_pid cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$l_sda_pidI#define cdrp$q_pte cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$q_ t pteI#define cdrp$l_cpu cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$l_cpuM#define cdrp$w_state cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$w_stateW#define cdrp$w_blk_status cdrp$r_cdrp_extensions.cdrp$r_sda_extension.cdrp$w_blk_status"#endif /* #if !defined(__VAXC) */ T#define CDRP$S_CDRPDEF 848 /* Old size name, synonym for CDRP$S_CDRP */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */u b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CDRPDEF_LOADED */ wwMZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Entev rprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and iw s not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************************** x *****************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */F/* Source: 18-FEB-1995 12:27:23 $1$DGA8345:[LIB_H.SRC]CDTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CDTDEF ***/#ifndef __CDTDEF_LOADED#define __CDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __savey #pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struz ct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CDT - SCS CONNECTION DESCRIPTOR TABLE */N/* */N/* THESE DESCRIPTORS ARE POI{ NTED TO BY THE SYSTEM WIDE CONNECTION */N/* DESCRIPTOR LIST (CDL). ONE CDT IS USED PER SCS VIRTUAL CIRCUIT */N/* OR LISTENING CONNECTION. */N/*- */ N#define CDT$C_CLOSED 0 /* CLOSED */N#define CDT$C_LISTEN 1 /* LISTENING FOR CONNX REQUESTS */N#define CDT$C_OPEN 2 /* OPEN | */N#define CDT$C_DISC_ACK 3 /* DISCONNECT ACKNOWLEDGED */N#define CDT$C_DISC_REC 4 /* DISCONNECT REQ RECEIVED */N#define CDT$C_DISC_SENT 5 /* DISCONNECT SENT */N#define CDT$C_DISC_MTCH 6 /* DISCONNECT MATCH */N#define CDT$C_CON_SENT 7 /* CONNECT REQ SENT */N#define CDT$C_CON_ACK 8 /* CONNECT REQ SENT AND ACK'ED } */N#define CDT$C_CON_REC 9 /* CONNECT REQ RECEIVED */N#define CDT$C_ACCP_SENT 10 /* ACCEPT REQ SENT */N#define CDT$C_REJ_SENT 11 /* REJECT SENT */V#define CDT$C_DISC_MTCH_RSPQ 12 /* MATCHING DISCONNECT RESPONSE IN PROGRESS */N#define CDT$C_DISC_RSPQ 13 /* DISCONNECT RESPONSE IN PROGRESS */N#define CDT$C_VC_FAIL 14 /* VIRTUAL CIRCUIT FAILED */N/* ~ */N#define CDT$C_CON_PEND 1 /* WAITING TO SEND CONNECT REQ */N#define CDT$C_ACCP_PEND 2 /* WAITING TO SEND ACCEPT REQ */N#define CDT$C_REJ_PEND 3 /* WAITING TO SEND REJECT REQ */N#define CDT$C_DISC_PEND 4 /* WAITING TO SEND DISCONNECT REQ */N#define CDT$C_CR_PEND 5 /* WAITING TO SEND CREDIT */N#define CDT$C_DCR_PEND 6  /* WAITING TO SEND CREDIT IN */N/* PREPARATION FOR DISCONNECT */Z#define CDT$C_RATING0 0 /* (TYC 4-JAN-89) Undefined yet but valid value */Z#define CDT$C_RATING1 1 /* (TYC 4-JAN-89) Undefined yet but valid value */Z#define CDT$C_RATING2 2 /* (TYC 4-JAN-89) Undefined yet but valid value */Z#define CDT$C_RATING3 3 /* (TYC 4-JAN-89) Undefined yet but valid value */N/* MOVE SUGGESTED  FOR AN EQUAL PATH (I.E. CI->CI) */S#define CDT$C_YELLOW 4 /* (TYC 4-JAN-89) port is in YELLOW zone */Z#define CDT$C_RATING5 5 /* (TYC 4-JAN-89) Undefined yet but valid value */Z#define CDT$C_RED 6 /* port is in RED zone (i.e. port is saturated) */^#define CDT$C_UNEQUAL_PATH 7 /* MOVE SUGGESTED FOR AN UNEQUAL PATH (I.E. NI->CI) */N#define CDT$C_LOAD_SHARE_DISABLE 8 /* load sharing disabled */ N/* */S#define CDT$C_BAD_RATING -2147483648 /* (TYC 4-JAN-89) Bad load rating marker */$#define CDT$K_BAD_RATING -2147483648P#define CDT$C_LOADSHARE 0 /* (TYC 21-Jun-89) Load sharing SYSAP */T#define CDT$C_PRE_LOADSHARE 1 /* (TYC 21-Jun-89) Pre-load sharing SYSAP */N/* */N#define CDT$K_LENGTH 400 /*LENGTH OF  CDT */N#define CDT$C_LENGTH 400 /*LENGTH OF CDT */N#define CDT$S_CDTDEF 400 /*Old size name, synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _pdt; struct _pb; struct _sb; #endif /* #ifdef __cplusplus */ typedef struct _cdt { __union {T void *cdt$l_msginput; /* SYSAP Message Input Dispatcher routine */N struct _cdt *cdt$l_link; /* O R LINK TO NEXT FREE CDT */! } cdt$r_msginput_overlay;N int (*cdt$l_dginput)(); /* SYSAP Datagram Received Routine */N unsigned short int cdt$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char cdt$b_type; /*SCS STRUCTURE TYPE */N unsigned char cdt$b_subtyp; /*SCS STRUCT SUBTYPE FOR CDT */N int (*cdt$l_erraddr)(); /* SYSAP Error Notification routine */s int (*cdt$l_fast_recvmsg_reque st)(); /* SYSAP routine to see if Fast Path can be used for a received message */f int (*cdt$l_fast_recvmsg_pm)(); /* SYSAP routine to process received message via Fast Path */m int (*cdt$l_change_affinity)(); /* SYSAP routine to process changes in Fast Path port CPU affinity */N struct _pdt *cdt$l_pdt; /*ADDR OF ASSOC PORT DESC TABLE */N unsigned int cdt$l_rconid; /*REMOTE CONNECTION ID */N unsigned int cdt$l_lconid; /*LOCA L CONNECTION ID */N struct _pb *cdt$l_pb; /*ADDR OF ASSOC PATH BLOCK */N unsigned char cdt$b_rstation [6]; /*REMOTE STATION ADDR */N unsigned short int cdt$w_reason; /*REJECT/DISCONNECT REASON */N unsigned short int cdt$w_state; /*CONNECTION STATE */N/*STATE VALUES: */N/* 0 ORIGIN, INCREMENTS OF 1:  */N unsigned short int cdt$w_blkstate; /*SCS SEND BLOCKED STATE */N/*STATE VALUES: */N/* 1 ORIGIN, INCREMENTS OF 1: */N/* */N void *cdt$l_scsmsg; /*ADDR OF SCS RECEIVE BUFFER */N void *cdt$l_waitqfl; /*SEND SCS MSG WAIT QUEUE FLINK */N void *cdt$l_wa itqbl; /*SEND SCS MSG WAIT QUEUE BLINK */N void *cdt$l_crwaitqfl; /*SEND CREDIT WAIT QUEUE FLINK */N void *cdt$l_crwaitqbl; /*SEND CREDIT WAIT QUEUE BLINK */N unsigned short int cdt$w_send; /*CURRENT SEND CREDIT */N unsigned short int cdt$w_rec; /*RECEIVE CREDIT (SEND CREDIT */N/* HELD BY REMOTE) */N unsigned short int cdt$w_minrec; /*MI NIMUM RECEIVE CREDIT (MIN */N/* SEND REQUIRED BY REMOTE) */N unsigned short int cdt$w_pendrec; /*RECEIVE CREDIT NOT YET EXTENDED */N/* TO REMOTE */N unsigned short int cdt$w_initlrec; /*INITIAL RECEIVE CREDIT */N unsigned short int cdt$w_minsend; /*MINIMUM SEND CREDIT */N unsigned short int cdt$w_dgrec; /*DATAGRAMS QUEUED FOR RECEIVE */N unsigned char cdt$b_priority; /*BLOCK TRANSFER PRIORIY */N char cdtdef$$_fill_1; /*RESERVED */N void *cdt$l_rprocnam; /*ADDR OF REMOTE PROCESS NAME */N void *cdt$l_lprocnam; /*ADDR OF LOCAL PROCESS NAME */N void *cdt$l_condat; /*ADDR OF CONNECT DATA */N void *cdt$l_auxstruc; /*ADDR OF AUXILARY DATA STRUCTURE */N int (*cdt$l_ badrsp)(); /*ADDR IN SYSAP TO CALL WITH */N/* BAD RESPONSE(UNIMPLEMENTED) */N unsigned int cdt$l_fpc; /*SAVED FORK PROCESS PC */N unsigned int cdt$l_fr5; /*SAVED FORK PROCESS R5 */N void *cdt$l_cdtlst; /*LINK FOR CDT LIST FROM PB */N unsigned int cdt$l_dgsent; /*# APPLICATION DGS SENT */N unsigned int cdt$l_dgrcvd; /* # APPLICATION DGS REC'D */N unsigned int cdt$l_dgdiscard; /*# DGS DISCARDED BY DRIVER */N unsigned int cdt$l_msgsent; /*# APPLICATION MSGS SENT */N unsigned int cdt$l_msgrcvd; /*# APPLICATION MSGS REC'D */^ unsigned int cdt$l_non_fp_sendmsgs; /* Counter of number of non-Fast Path send messages */a unsigned int cdt$l_non_fp_rcvdmsgs; /* Counter of number of non-Fast Path receive messages */N unsigned int cdt$l_snddats;  /*# SEND DATAS INITIATED */N unsigned int cdt$l_bytsent; /*# BYTES SENT VIA SEND DATAS */N unsigned int cdt$l_reqdats; /*#REQ DATAS INITIATED */N unsigned int cdt$l_bytreqd; /*BYTES REC'D VIA REQ DATAS */N unsigned int cdt$l_bytmapd; /*TOTAL BYTES MAPPED */N unsigned short int cdt$w_qcr_cnt; /*# TIMES QUEUED FOR SEND CREDIT */N unsigned short int cdt$w_qbdlt_cnt; /*# TIMES QUEUED F OR BDLT */N/* (TYC 14-FEB-89) LOAD SHARING FIELDS */N void *cdt$l_move_path_addr; /* CONNECTION MOVE ADDRESS */N/* 1 ORIGIN, INCREMENTS OF 1: */Q void *cdt$l_share_flink; /*DYNAMIC LOAD SHARING CDT QUEUE FLINK */Q void *cdt$l_share_blink; /*DYNAMIC LOAD SHARING CDT QUEUE BLINK */N struct _sb *cdt$l_sb; /*SYSTEM BLOCK ADDRESS  */N/* R1 load rating on entry (TYC 4-JAN-89) */V unsigned int cdt$l_con_req_ctr; /* (TYC 25-Apr-89) # of times CONN REQ sent */Q unsigned int cdt$l_load_rating; /* LOAD RATING (TYC 4-JAN-89 now used) */` unsigned int cdt$l_time_stamp; /* TIME STAMP (EXE$GL_ABSTIM) OF CONNECTION FORMATION */` unsigned int cdt$l_queue_time_stamp; /* (TYC 15-Feb-89) TIME STAMP OF MOVING CDT TO QUEUE */] unsigned int cdt$l_discon_counter; /* (TYC 15-Feb -89) LOAD SHARING DISCONNECT COUNTER */N/* used with conditional assembly */^ void *cdt$l_optimal_path; /* (TYC 15-Feb-89) PATH ADDRESS OF THE OPTIMAL PORT */c unsigned int cdt$l_bytes_xfer; /* (TYC 15-Feb-89) TOTAL BYTES XFERRED (BOTH XMIT & RCV) */U unsigned int cdt$l_bytes_dg_xmt; /* (TYC 15-Feb-89) TOTAL DG BYTES XMITTED */U unsigned int cdt$l_bytes_dg_rcv; /* (TYC 15-Feb-89) TOTAL DG BYTES RECEIVED */U unsign ed int cdt$l_bytes_msg_xmt; /* (TYC 15-Feb-89) TOTAL MSG BYTES XMITTED */V unsigned int cdt$l_bytes_msg_rcv; /* (TYC 15-Feb-89) TOTAL MSG BYTES RECEIVED */R unsigned int cdt$l_bytes_xfer_last; /* (TYC 31-Aug-89) TOTAL BYTES XFERRED */N/* UP TO LAST LOAD SHARING INTERVAL */V unsigned int cdt$l_bytes_dg_xmt_last; /* (TYC 31-Aug-89) TOTAL DG BYTES XMITTED */N/* UP TO LAST LOAD SHARING INTERVAL */X unsi gned int cdt$l_bytes_dg_rcv_last; /* (TYC 31-Aug-89) TOTAL DG BYTES RECEIVED */N/* UP TO LAST LOAD SHARING INTERVAL */Y unsigned int cdt$l_bytes_msg_xmt_last; /* (TYC 31-Aug-89) TOTAL MSG BYTES XMITTED */N/* UP TO LAST LOAD SHARING INTERVAL */Y unsigned int cdt$l_bytes_msg_rcv_last; /* (TYC 31-Aug-89) TOTAL MSG BYTES RECEIVED */N/* UP TO LAST LOAD SHARING INTERVAL */Q unsigned int cdt$l_bytmapd_last; /* (TYC 31-Aug-89) TOTAL BYTES MAPPED */N/* UP TO LAST LOAD SHARING INTERVAL */P unsigned int cdt$l_dgsent_last; /* (TYC 31-Aug-89) TOTAL DGS XMITTED */N/* UP TO LAST LOAD SHARING INTERVAL */P unsigned int cdt$l_dgrcvd_last; /* (TYC 31-Aug-89) TOTAL DGS RECEIVED */N/* UP TO LAST LOAD SHARING INTERVAL */P unsigned int c dt$l_msgsent_last; /* (TYC 31-Aug-89) TOTAL MSGS XMITTED */N/* UP TO LAST LOAD SHARING INTERVAL */R unsigned int cdt$l_msgrcvd_last; /* (TYC 31-Aug-89) TOTAL MSGS RECEIVED */N/* UP TO LAST LOAD SHARING INTERVAL */N/* (TYC 17-Feb-89) peak counters used with conditional assembly */P unsigned int cdt$l_bytes_xfer_peak; /* PEAK VALUE OF TOTAL BYTES XFERRED */U unsigned int cdt$l_bytes_dg_xmt_ peak; /* PEAK VALUE OF TOTAL DG BYTES XMITTED */V unsigned int cdt$l_bytes_dg_rcv_peak; /* PEAK VALUE OF TOTAL DG BYTES RECEIVED */W unsigned int cdt$l_bytes_msg_xmt_peak; /* PEAK VALUE OF TOTAL MSG BYTES XMITTED */W unsigned int cdt$l_bytes_msg_rcv_peak; /* PEAK VALUE OF TOTAL MSG BYTES RECEIVED */O unsigned int cdt$l_bytmapd_peak; /* PEAK VALUE OF TOTAL BYTES MAPPED */N unsigned int cdt$l_dgsent_peak; /* PEAK VALUE OF TOTAL DGS XMITTED */N unsigned int cdt$l_d grcvd_peak; /* PEAK VALUE OF TOTAL DGS RECEIVED */N unsigned int cdt$l_msgsent_peak; /* PEAK VALUE OF TOTAL MSGS XMITTED */P unsigned int cdt$l_msgrcvd_peak; /* PEAK VALUE OF TOTAL MSGS RECEIVED */N/* (TYC 17-Feb-89) average counters used with conditional assembly */S unsigned int cdt$l_bytes_xfer_avg; /* AVERAGE VALUE OF TOTAL BYTES XFERRED */W unsigned int cdt$l_bytes_dg_xmt_avg; /* AVERAGE VALUE OF TOTAL DG BYTES XMITTED */X unsigned int cdt$l_bytes_dg_ rcv_avg; /* AVERAGE VALUE OF TOTAL DG BYTES RECEIVED */Y unsigned int cdt$l_bytes_msg_xmt_avg; /* AVERAGE VALUE OF TOTAL MSG BYTES XMITTED */Y unsigned int cdt$l_bytes_msg_rcv_avg; /* AVERAGE VALUE OF TOTAL MSG BYTES RECEIVED */R unsigned int cdt$l_bytmapd_avg; /* AVERAGE VALUE OF TOTAL BYTES MAPPED */Q unsigned int cdt$l_dgsent_avg; /* AVERAGE VALUE OF TOTAL DGS XMITTED */Q unsigned int cdt$l_dgrcvd_avg; /* AVERAGE VALUE OF TOTAL DGS RECEIVED */Q unsigned int cdt$l_msgsent_avg; /* AVERAGE VALUE OF TOTAL MSGS XMITTED */S unsigned int cdt$l_msgrcvd_avg; /* AVERAGE VALUE OF TOTAL MSGS RECEIVED */Q unsigned int cdt$l_bytes_xfer_int; /* (TYC 31-AUG-89) TOTAL BYTES XFERRED */N/* DURING LAST LOAD SHARING INTERVAL */N/* (TYC 21-Jun-89) Moved fields */N unsigned short int cdt$w_local_index; /* LOCAL PROCESS NAME INDEX */Y unsigned char cdt$b_ ls_flag; /* (TYC 15-Feb-89) LOAD SHARING FLAG. IF SET, */N/* THE CONNECTION IS REQUESTED TO DISCONNECT */T unsigned char cdt$b_sysap_version; /* (TYC 21-Jun-89) Flag for SYSAP version */N/* (TYC 21-Jun-89) SYSAP version constants */N char cdt$b_quad_fill1 [4]; /* Following Maintenance block must */N/* be quadword aligned: */U unsigned char cdt$b_scs_main t_block [16]; /*Add a Maintenance block to the CDT */N/* which must be quadword aligned */a unsigned int cdt$l_fp_scs_nosend; /* Counter of number of times SCS votes no on Send Msg */d unsigned int cdt$l_fp_scs_norecv; /* Counter of number of times SCS votes no on Receive Msg */N unsigned int cdt$l_reserved3; /*RESERVED */N unsigned int cdt$l_reserved4; /*RESERVED */ } CD T; #if !defined(__VAXC)<#define cdt$l_msginput cdt$r_msginput_overlay.cdt$l_msginput4#define cdt$l_link cdt$r_msginput_overlay.cdt$l_link"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CDTDEF_LOADED */ ww0ZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE.  **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */F/* Source: 20-JAN-2004 10:45:49 $1$DGA8345:[LIB_H.SRC]CEBDEF.SDL;1 *//***************** ***************************************************************************************************************//*** MODULE $CEBDEF ***/#ifndef __CEBDEF_LOADED#define __CEBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __un ion variant_union#endif#endif N/*+ */N/* COMMON EVENT BLOCK */N/*- */ #define CEB$M_NOQUOTA 0x1#define CEB$M_PERM 0x2##define CEB$M_RSRVD_2_31 0xFFFFFFFCN#define CEB$K_LENGTH 72 /*LENGTH OF COMMON EVENT BLOCK */N#define CEB$C_LENGTH 72 /*LENGTH OF COMMON EVENT BLOCK */#define CEB$S_CEBDEF 72  9#ifdef __cplusplus /* Define structure prototypes */ struct _orb; #endif /* #ifdef __cplusplus */ typedef struct _ceb {P struct _ceb *ceb$l_cebfl; /*POINTER TO NEXT COMMON EVENT BLOCK */T struct _ceb *ceb$l_cebbl; /*POINTER TO PREVIOUS COMMON EVENT BLOCK */Q unsigned short int ceb$w_size; /*SIZE OF COMMON EVENT BLOCK IN BYTES */N unsigned char ceb$b_type; /*STRUCTURE TYPE CODE FOR CEB */ char ceb$b_subtype; __union {N unsigned int ceb$l_sts; /*STATUS FLAGS FOR CEB */ __struct {N unsigned ceb$v_noquota : 1; /*NO QUOTA UPDATE */N unsigned ceb$v_perm : 1; /*PERMANENT CLUSTER */+ unsigned ceb$v_rsrvd_2_31 : 30; } ceb$r_sts_bits; } ceb$r_sts_overlay;N unsigned int ceb$l_pid; /*PID OF CREATOR */N unsigned int ceb$l_efc; /*EVENT FLAGS (32 BIT VECTOR) */N void *ceb$l_wqfl; /*HEAD OF WAIT QUEUE */N void *ceb$l_wqbl; /*TAIL OF WAIT QUEUE */N unsigned int ceb$l_wqcnt; /*WAIT QUEUE COUNT(LENGTH) */N unsigned int ceb$l_state; /*CEF WAIT STATE NUMBER */N struct _orb *ceb$l_orb; /*POINTER TO THE ORB */ __union {N unsigned int ceb$l_uic; /*USER IDENT OF CEB CREATOR */ __struct {% char cebdef$$_fill_2 [2];N unsigned short int ceb$w_grp; /*GROUP NUMBER OF OWNER */ } ceb$r_uic_fields; } ceb$r_uic_overlay;N unsigned int ceb$l_prot; /*PROTECTION MASK */N unsigned int ceb$l_refc; /*REFERENCE COUNT FOR CEB */N char ceb$t_efcnam [16]; /*EVENT CLUSTER TEXT NAME */ } CEB; #if !defined(__VAXC)-#define ceb$l_sts ceb$r_sts_overlay.ceb$l_stsD#define ceb$v_noquota ceb$r_sts_overlay.ceb$r_sts_bits.ceb$v_noquota>#define ceb$v_perm ceb$r_sts_overlay.ceb$r_sts_bits.ceb$v_permJ#define ceb$v_rsrvd_2_31 ceb$r_sts_overlay.ceb$r_sts_bits.ceb$v_rsrvd_2_31-#define ceb$l_uic ceb$r_uic_overlay.ceb$l_uic>#define ceb$w_grp ceb$r_uic_overlay.ceb$r_uic_fields.ceb$w_grp"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __resto reR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CEBDEF_LOADED */ wwP8ZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This softw are is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is conf idential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*** *****************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */I/* Source: 16-MAY-2017 13:01:50 $1$DGA8345:[LIB_H.SRC]CHFCTXDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CHFCTXDEF ***/#ifndef __CHFCTXDEF_LOADED#define __CHFCTXDEF_LOADED 1 G#pragma __nost andard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params .. .#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* CONDITION HANDLING FACILITY INTERNAL CONTEXT OFFSETS */N/*  */N/* This module defines the layout of the Condition Handling Facility */N/* internal context on the stack (in the mode of the exception). */N/* This context is created by the VMS hardware exception handling */N/* facility and the RTL LIB$SIGNAL/LIB$STOP routines. This context */N/* is used by the Condition Handling Facility as well as DEBUG. */N/*  */N/* Note that this structure definition only provides offsets for a */N/* small portion of the whole exception context. The whole exception */N/* context contains: */N/* */K/* Internal context area (structure defined here) */I/* ALPHA mechanism array  */I/* Signal array (which includes the ALPHA exception record) */I/* Exception frame generated by PAL */N/* */N/* The mechanism array can't be embedded here because it is subject to */N/* change, and there is no easy way to "include" the mechanism array */N/* definition into this module. */N/* */N/* The signal array is variable length, depending on the exception. */N/* */#define CHFCTX$M_SIGNAL 0x1#define CHFCTX$M_STOP 0x2!#define CHFCTX$M_FPREGS_VALID 0x4#define CHFCTX$M_UNWIND_AST 0x8!#define CHFCTX$M_REINVOKABLE 0x10"#define CHFCTX$M_FPREGS_READY 0x20 #define CHFCTX$M_SYS_UNWIND 0x40!#define CHFCTX$M_GOTO_UNWIND 0x80"#define CHFCTX$M_EXI T_UNWIND 0x100$#define CHFCTX$M_RECALL_TARGET 0x200$#define CHFCTX$M_REENABLE_ASTS 0x400"#define CHFCTX$M_CALL_CLRAST 0x800#define CHFCTX$M_SIG64 0x1000*#define CHFCTX$M_TARGET_IS_REGFRAME 0x2000)#define CHFCTX$M_SET_STACK_TO_BASE 0x4000*#define CHFCTX$M_SOFTWARE_GENERATED 0x8000!#define CHFCTX$M_BADSTACK 0x10000 #define CHFCTX$M_REBUILT 0x20000N#define CHFCTX$K_LENGTH 112 /* Length of CHFCTX */N#define CHFCTX$C_LENGTH 112 /* Length of CHFCTX */N#define CHFCTX$C_LENGTH_V731 80 /* Length of V7.3-1 CHFCTX */#define CHFCTX$S_CHFCTXDEF 112 typedef struct _chfctx {N unsigned __int64 chfctx$q_linkage_ptr; /* Linkage section pointer */N unsigned __int64 chfctx$q_sigarglst; /* Address of Signal array */N unsigned __int64 chfctx$q_mcharglst; /* Address of mechanism array */N unsigned __int64 chfctx$q_expt_addr; /* Address of exception frame */N unsigned __int64 chfctx$ q_expt_fp; /* Exception FP */N unsigned __int64 chfctx$q_unwind_sp; /* SP during unwind */P unsigned __int64 chfctx$q_reinvokable_fp; /* End of reinvokable algorithm */N unsigned __int64 chfctx$q_unwind_target; /* Unwind target (FP) */N unsigned __int64 chfctx$q_unwind_target_pc; /* Unwind target PC */N unsigned __int64 chfctx$q_unwind_target_invo; /* Unwind target INVO */N unsigned int chfctx$l_bytecnt; /* Byte coun t of exception context */N unsigned int chfctx$l_sig_args; /* Original signal array count */ __union { __union {N unsigned int chfctx$l_flags; /* Internal flags */ __struct {N unsigned chfctx$v_signal : 1; /* Signal flag */N unsigned chfctx$v_stop : 1; /* Stop flag */X unsigned chfctx$v_fpregs_valid : 1; /* Floating Point Registers valid */N  unsigned chfctx$v_unwind_ast : 1; /* Unwinding from AST */Z unsigned chfctx$v_reinvokable : 1; /* Reinvokable algorithm in progress */X unsigned chfctx$v_fpregs_ready : 1; /* Floating Point Registers ready */N unsigned chfctx$v_sys_unwind : 1; /* Unwind by depth */P unsigned chfctx$v_goto_unwind : 1; /* GOTO unwind in progress */P unsigned chfctx$v_exit_unwind : 1; /* Exit unwind in progress */^  unsigned chfctx$v_recall_target : 1; /* Re-call target invocation's handler */[ unsigned chfctx$v_reenable_asts : 1; /* ASTs were disabled during unwind */X unsigned chfctx$v_call_clrast : 1; /* Call CLRAST in CHF_RESTORE_REGS */N unsigned chfctx$v_sig64 : 1; /* This is a 64-bit signal */h unsigned chfctx$v_target_is_regframe : 1; /* Target frame of Unwind is register frame */] unsigned chfctx$v_set_stack_to _base : 1; /* Reset inner mode stack to base */\ unsigned chfctx$v_software_generated : 1; /* Software Generated exception */W unsigned chfctx$v_badstack : 1; /* Resumed in outer mode at BADSTACK */c unsigned chfctx$v_rebuilt : 1; /* This CHFCTX was converted from pre-V7.3-2 size */. unsigned chfctx$v_fill_2_ : 6;# } chfctx$r_fill_1_; } chfctx$r_fill_0_;N unsigned int chfctx$l_finalsts; /* Final s tatus */ } chfctx$r_flags_desc;N void *chfctx$l_msgptr; /* Address of $EXCMSG error msg */N/* Verified for x86 port - Clair Grant */N unsigned __int64 chfctx$q_unwind_depth; /* IA64 unwind depth */] unsigned __int64 chfctx$q_spare1; /* Structure length must be a multiple of 16 bytes */ } CHFCTX; #if !defined(__VAXC)J#define chfctx$l_flags chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx $l_flags]#define chfctx$v_signal chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_signalY#define chfctx$v_stop chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_stopi#define chfctx$v_fpregs_valid chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_fpregs_valide#define chfctx$v_unwind_ast chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_unwind_astg#define chfctx$v_reinvokable chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_rein vokablei#define chfctx$v_fpregs_ready chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_fpregs_readye#define chfctx$v_sys_unwind chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_sys_unwindg#define chfctx$v_goto_unwind chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_goto_unwindg#define chfctx$v_exit_unwind chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_exit_unwindk#define chfctx$v_recall_target chfctx$r_flags_desc.chfctx$r_fill_0_.chfc tx$r_fill_1_.chfctx$v_recall_targetk#define chfctx$v_reenable_asts chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_reenable_astsg#define chfctx$v_call_clrast chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_call_clrast[#define chfctx$v_sig64 chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_sig64u#define chfctx$v_target_is_regframe chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_target_is_regframes#define chfctx$v_set_stack_to_base chf ctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_set_stack_to_baseu#define chfctx$v_software_generated chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_software_generateda#define chfctx$v_badstack chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_badstack_#define chfctx$v_rebuilt chfctx$r_flags_desc.chfctx$r_fill_0_.chfctx$r_fill_1_.chfctx$v_rebuilt?#define chfctx$l_finalsts chfctx$r_flags_desc.chfctx$l_finalsts"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CHFCTXDEF_LOADED */ ww`_ZUM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE,  INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/******************************************* ********************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */I/* Source: 20-DEC-1996 06:37:06 $1$DGA8345:[LIB_H.SRC]CHPCTLDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CHPCTLDEF ***/#ifndef __CHPCTLDEF_LOADED#define __CHPCTLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_ params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* CHeck Protection ConTroL block definition. This  block contains the */N/* information concerning the type of access check being made. */N/* */#define CHPCTL$M_READ 0x1#define CHPCTL$M_WRITE 0x2#define CHPCTL$M_USEREADALL 0x4#define CHPCTL$M_NOAUDIT 0x8#define CHPCTL$M_NOFAILAUD 0x10#define CHPCTL$M_NOSUCCAUD 0x20#define CHPCTL$M_DELETE 0x40#define CHPCTL$M_MANDATORY 0x80#define CHPCTL$M_FLUSH 0x100#define CHPCTL$M_CREATE 0x200#def ine CHPCTL$M_INTERNAL 0x400#define CHPCTL$M_SERVER 0x800#define CHPCTL$K_LENGTH 32#define CHPCTL$C_LENGTH 32  9#ifdef __cplusplus /* Define structure prototypes */ struct _arb; struct _psb; struct _orb; #endif /* #ifdef __cplusplus */ typedef struct _chpctl {N unsigned int chpctl$l_access; /* type of access desired */ __union {N unsigned int chpctl$l_flags; /* control flags */ __struct {N unsi gned chpctl$v_read : 1; /* READ access */N unsigned chpctl$v_write : 1; /* WRITE access */S unsigned chpctl$v_usereadall : 1; /* try for READ access via READALL */N unsigned chpctl$v_noaudit : 1; /* do not perform any auditing */U unsigned chpctl$v_nofailaud : 1; /* do not perform failed access audit */Y unsigned chpctl$v_nosuccaud : 1; /* do not perform successful access audit */N unsi gned chpctl$v_delete : 1; /* perform audit as DELETE event */N unsigned chpctl$v_mandatory : 1; /* perform mandatory audit */Q unsigned chpctl$v_flush : 1; /* force buffer flush in audit server */N unsigned chpctl$v_create : 1; /* perform audit as CREATE event */N unsigned chpctl$v_internal : 1; /* audit on behalf of VMS TCB */V unsigned chpctl$v_server : 1; /* audit originates in TCB server process */* unsigned chpctl$v_ fill_2_ : 4; } chpctl$r_fill_1_; } chpctl$r_fill_0_;N unsigned int chpctl$l_mode; /* access mode of request */V void *chpctl$l_audit_list; /* address of associated auditing item list */N int chpctl$l_deaccess_key; /* deaccess audit object handle */N unsigned int chpctl$l_message; /* associated auditing message code */\ __union { /* Use same storage for either ARB or PSB address */N struct _arb *chpctl$l_arb; /* corresponding ARB */N struct _psb *chpctl$l_psb; /* corresponding PSB */$ } chpctl$r_access_structure;N struct _orb *chpctl$l_orb; /* corresponding ORB */ } CHPCTL; #if !defined(__VAXC)6#define chpctl$l_flags chpctl$r_fill_0_.chpctl$l_flagsE#define chpctl$v_read chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$v_readG#define chpctl$v_write chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$ v_writeQ#define chpctl$v_usereadall chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$v_usereadallK#define chpctl$v_noaudit chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$v_noauditO#define chpctl$v_nofailaud chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$v_nofailaudO#define chpctl$v_nosuccaud chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$v_nosuccaudI#define chpctl$v_delete chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$v_deleteO#define chpctl$v_mandatory chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$v_mandatoryG#define chpc tl$v_flush chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$v_flushI#define chpctl$v_create chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$v_createM#define chpctl$v_internal chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$v_internalI#define chpctl$v_server chpctl$r_fill_0_.chpctl$r_fill_1_.chpctl$v_server;#define chpctl$l_arb chpctl$r_access_structure.chpctl$l_arb;#define chpctl$l_psb chpctl$r_access_structure.chpctl$l_psb"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CHPCTLDEF_LOADED */ wwZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidenti al **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********* ***********************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */I/* Source: 22-NOV-1993 09:46:27 $1$DGA8345:[LIB_H.SRC]CHPRETDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CHPRETDEF ***/#ifndef __CHPRETDEF_LOADED#define __CHPRETDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#e lse#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* CHeck Protectio n ConTroL RETurn argument block. This block contains */N/* the information needed to return arguments from the protection check. */N/* */N/*- */#define CHPRET$M_ACMODE 0x1#define CHPRET$M_MAC 0x2#define CHPRET$M_DAC 0x4 #define CHPRET$M_MATCHED_ACE 0x8#define CHPRET$M_SOGW 0x10#define CHPRET$M_ACL_KEYID 0x20#define CHPRET$M_IVBUFLEN 0x40#define CHPRET$K_LENGTH 44#define CHPRET$C_LENGTH 44 typedef struct _chpret {N unsigned int chpret$l_auditlen; /* Size of the audit ACE buffer */N void *chpret$l_audit; /* Address of the audit ACE buffer */O void *chpret$l_auditret; /* Address of word to get ACE length */N unsigned int chpret$l_alarmlen; /* Size of the alarm ACE buffer */N void *chpret$l_alarm; /* Address of the alarm ACE buffer */O void *ch pret$l_alarmret; /* Address of word to get ACE length */N unsigned int chpret$l_matched_acelen; /* Size of the matched ACE buffer */O void *chpret$l_matched_ace; /* Address of the matched ACE buffer */O void *chpret$l_matched_aceret; /* Address of word to get ACE length */X void *chpret$l_privs_used; /* Address of longword to get privileges used */ __union {N unsigned int chpret$l_progress; /* Protection check progress fl */  __struct {N unsigned chpret$v_acmode : 1; /* Access mode check failed */N unsigned chpret$v_mac : 1; /* MAC check failed */N unsigned chpret$v_dac : 1; /* DAC check failed */N unsigned chpret$v_matched_ace : 1; /* matching ACE was located */N unsigned chpret$v_sogw : 1; /* SOGW check was performed */Y unsigned chpret$v_acl_keyid : 1; /* An identifier ACE was found in the ACL */ X unsigned chpret$v_ivbuflen : 1; /* CHPRET info for auditing is incomplete */* unsigned chpret$v_fill_2_ : 1; } chpret$r_fill_1_; } chpret$r_fill_0_; } CHPRET; #if !defined(__VAXC)<#define chpret$l_progress chpret$r_fill_0_.chpret$l_progressI#define chpret$v_acmode chpret$r_fill_0_.chpret$r_fill_1_.chpret$v_acmodeC#define chpret$v_mac chpret$r_fill_0_.chpret$r_fill_1_.chpret$v_macC#define chpret$v_dac chpret$r_fill_0_.chpret$r_fill_1_.c hpret$v_dacS#define chpret$v_matched_ace chpret$r_fill_0_.chpret$r_fill_1_.chpret$v_matched_aceE#define chpret$v_sogw chpret$r_fill_0_.chpret$r_fill_1_.chpret$v_sogwO#define chpret$v_acl_keyid chpret$r_fill_0_.chpret$r_fill_1_.chpret$v_acl_keyidM#define chpret$v_ivbuflen chpret$r_fill_0_.chpret$r_fill_1_.chpret$v_ivbuflen"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragm a __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CHPRETDEF_LOADED */ wwZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not  **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************* ***********************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */I/* Source: 24-FEB-1994 09:46:18 $1$DGA8345:[LIB_H.SRC]CIAOLDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CIAOLDDEF ***/#ifndef __CIAOLDDEF_LOADED#define __CIAOLDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __s ave#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef  __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CIAOLD - Compound Intrusion Analysis block */N/* */N/* Contains informatio n about suspected and known intruders */N/*- */N#define CIAOLD$K_TERMINAL 1 /* Unknown user at terminal */N#define CIAOLD$K_TERM_USER 2 /* Known username at terminal */N#define CIAOLD$K_NETWORK 3 /* Network source */N#define CIAOLD$K_USERNAME 4 /* Username of parent process */#define CIAOLD$M_INTRUDER 0x1N#define CIAOLD$K _LENGTH 160 /* Length of CIAOLD block */N#define CIAOLD$C_LENGTH 160 /* Length of CIAOLD block */#define CIAOLD$S_CIAOLDDEF 160 typedef struct _ciaold {N struct _ciaold *ciaold$l_flink; /* Forward link to next block */N struct _ciaold *ciaold$l_blink; /* Backward link to previous block */N unsigned short int ciaold$w_size; /* Size of block */N unsigned char ciaold$b_type; /* Structure type */N unsigned char ciaold$b_subtype; /* Structure subtype */N/* Source of breakin attempt */ __union {N unsigned int ciaold$l_flags; /* Breakin type flags */ __struct {N unsigned ciaold$v_intruder : 1; /* Entry is an intruder */* unsigned ciaold$v_fill_2_ : 7; } ciaold$r_fill_1_; } ciaold$r_fill_0_;N unsigned int cia old$l_count; /* Count of attempts */N unsigned int ciaold$l_fill_1; /* Make TIME naturally aligned */N unsigned __int64 ciaold$q_time; /* Expiration time of entry */N char ciaold$t_data [128]; /* Data area */ } CIAOLD; #if !defined(__VAXC)6#define ciaold$l_flags ciaold$r_fill_0_.ciaold$l_flagsM#define ciaold$v_intruder ciaold$r_fill_0_.ciaold$r_fill_1_.ciaold$v_intruder"#endif /* #if !defined(__VA XC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CIAOLDDEF_LOADED */ ww"ZUM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/**  VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************** **********************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */G/* Source: 23-JAN-1996 10:41:54 $1$DGA8345:[LIB_H.SRC]CIA_DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CIA_DEF ***/#ifndef __CIA_DEF_LOADED #define __CIA_DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __un known_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define CIA$L_NODE_PA_H 135 /* High order word */&#define CIA$L_CIA_GENERAL_L 1073741824%#defin e CIA$L_CIA_MEMORY_L 1342177280'#define CIA$L_CIA_PCI_ADDR_L 1610612736)#define CIA$L_FLASH_AND_GRU_L -2147483648N#define CIA$L_PCI_REV_L 128 /*PCI revision */N#define CIA$L_PCI_LAT_L 192 /*PCI Latency */N#define CIA$L_CIA_CTRL_L 256 /*CIA COntrol */N#define CIA$L_HAE_MEM_L 1024 /*HAE memory */N#define CIA$L_HAE_IO_L 1088 /*HAE I/O  */N#define CIA$L_HAE_CFG_L 1152 /*COnfig */N#define CIA$L_CIA_CACK_EN_L 1536 /*Ack control */N#define CIA$L_CIA_DIAG_L 8192 /*Diag control */N#define CIA$L_CIA_CHECK_L 12288 /*Diag check */N#define CIA$L_PERF_MON_L 16384 /*Perf monitor */N#define CIA$L_PERF_CNTR_L 16448 /*Perf control */N#define CIA$ L_CPU_ERR0_L 32768 /*Cpu err info 0 */N#define CIA$L_CPU_ERR1_L 32832 /*Cpu err info 1 */N#define CIA$L_CIA_ERR_L 33280 /*CIA err */N#define CIA$L_CIA_STAT_L 33344 /*CIA status */N#define CIA$L_CIA_ERR_MSK_L 33408 /*CIA err mask */N#define CIA$L_CIA_SYN_L 33536 /*CIA syndrome */N#define CIA$L_CPU_MPSR0_L 33792  /*Memport stat0 */N#define CIA$L_CPU_MPSR1_L 33856 /*Memport stat1 */N#define CIA$L_PCI_ERR0_L 34816 /*PCI Err 0 */N#define CIA$L_PCI_ERR1_L 34880 /*PCI Err 1 */N#define CIA$L_PCI_ERR2_L 34944 /*PCI Err 1 */N#define CIA$L_MEM_CNFG_L 0 /*Memory config */N#define CIA$L_MEM_BA0_L 1536 /*Mem base addr0  */N#define CIA$L_MEM_BA2_L 1664 /*Mem base addr2 */N#define CIA$L_MEM_BA4_L 1792 /*Mem base addr4 */N#define CIA$L_MEM_BA6_L 1920 /*Mem base addr6 */N#define CIA$L_MEM_BA8_L 2048 /*Mem base addr8 */N#define CIA$L_MEM_BAA_L 2176 /*Mem base addrA */N#define CIA$L_MEM_BAC_L 2304 /*Mem base addrC */N#define CI A$L_MEM_BAE_L 2432 /*Mem base addrE */N#define CIA$L_MEM_TMG0_L 2816 /*Mem timing 0 */N#define CIA$L_MEM_TMG1_L 2880 /*Mem timing 1 */N#define CIA$L_MEM_TMG2_L 2944 /*Mem timing 2 */N#define CIA$L_PCI_TBIA_L 256 /*SG TB inval */N#define CIA$L_PCI_W0_BASE_L 1024 /*Window base0 */N#define CIA$L_PCI_W0_MASK_L 1088  /*Window mask0 */N#define CIA$L_PCI_T0_BASE_L 1152 /*Trans base0 */N#define CIA$L_PCI_W1_BASE_L 1280 /*Window base1 */N#define CIA$L_PCI_W1_MASK_L 1344 /*Window mask1 */N#define CIA$L_PCI_T1_BASE_L 1408 /*Trans base1 */N#define CIA$L_PCI_W2_BASE_L 1536 /*Window base2 */N#define CIA$L_PCI_W2_MASK_L 1600 /*Window mask2  */N#define CIA$L_PCI_T2_BASE_L 1664 /*Trans base2 */N#define CIA$L_PCI_W3_BASE_L 1792 /*Window base3 */N#define CIA$L_PCI_W3_MASK_L 1856 /*Window mask3 */N#define CIA$L_PCI_T3_BASE_L 1920 /*Trans base3 */N#define CIA$L_PCI_DAC_BASE_L 1984 /*DAC Base */N#define CIA$L_PCI_LTB_TAG0_L 2048 /*Lock TB tag0 */N#define  CIA$L_PCI_LTB_TAG1_L 2112 /*Lock TB tag1 */N#define CIA$L_PCI_LTB_TAG2_L 2176 /*Lock TB tag2 */N#define CIA$L_PCI_LTB_TAG3_L 2240 /*Lock TB tag3 */N#define CIA$L_PCI_TB_TAG0_L 2304 /* TB tag0 */N#define CIA$L_PCI_TB_TAG1_L 2368 /* TB tag1 */N#define CIA$L_PCI_TB_TAG2_L 2432 /* TB tag2 */N#define CIA$L_PCI_TB_TAG3_L 2496  /* TB tag3 */N#define CIA$L_PCI_TB0_PAGE0_L 4096 /* TB0 page0 */N#define CIA$L_PCI_TB0_PAGE1_L 4160 /* TB0 page1 */N#define CIA$L_PCI_TB0_PAGE2_L 4224 /* TB0 page2 */N#define CIA$L_PCI_TB0_PAGE3_L 4288 /* TB0 page3 */N#define CIA$L_PCI_TB1_PAGE0_L 4352 /* TB1 page0 */N#define CIA$L_PCI_TB1_PAGE1_L 4416 /* TB1 page1  */N#define CIA$L_PCI_TB1_PAGE2_L 4480 /* TB1 page2 */N#define CIA$L_PCI_TB1_PAGE3_L 4544 /* TB1 page3 */N#define CIA$L_PCI_TB2_PAGE0_L 4608 /* TB2 page0 */N#define CIA$L_PCI_TB2_PAGE1_L 4672 /* TB2 page1 */N#define CIA$L_PCI_TB2_PAGE2_L 4736 /* TB2 page2 */N#define CIA$L_PCI_TB2_PAGE3_L 4800 /* TB2 page3 */N#defin e CIA$L_PCI_TB3_PAGE0_L 4864 /* TB3 page0 */N#define CIA$L_PCI_TB3_PAGE1_L 4928 /* TB3 page1 */N#define CIA$L_PCI_TB3_PAGE2_L 4992 /* TB3 page2 */N#define CIA$L_PCI_TB3_PAGE3_L 5056 /* TB3 page3 */N#define CIA$L_PCI_TB4_PAGE0_L 5120 /* TB4 page0 */N#define CIA$L_PCI_TB4_PAGE1_L 5184 /* TB4 page1 */N#define CIA$L_PCI_TB4_PAGE2_L 52 48 /* TB4 page2 */N#define CIA$L_PCI_TB4_PAGE3_L 5312 /* TB4 page3 */N#define CIA$L_PCI_TB5_PAGE0_L 5376 /* TB5 page0 */N#define CIA$L_PCI_TB5_PAGE1_L 5440 /* TB5 page1 */N#define CIA$L_PCI_TB5_PAGE2_L 5504 /* TB5 page2 */N#define CIA$L_PCI_TB5_PAGE3_L 5568 /* TB5 page3 */N#define CIA$L_PCI_TB6_PAGE0_L 5632 /* TB6 page0  */N#define CIA$L_PCI_TB6_PAGE1_L 5696 /* TB6 page1 */N#define CIA$L_PCI_TB6_PAGE2_L 5760 /* TB6 page2 */N#define CIA$L_PCI_TB6_PAGE3_L 5824 /* TB6 page3 */N#define CIA$L_PCI_TB7_PAGE0_L 5888 /* TB7 page0 */N#define CIA$L_PCI_TB7_PAGE1_L 5952 /* TB7 page1 */N#define CIA$L_PCI_TB7_PAGE2_L 6016 /* TB7 page2 */N#def ine CIA$L_PCI_TB7_PAGE3_L 6080 /* TB7 page3 */!#define CIA$M_CIA_CTRL_PCI_EN 0x1&#define CIA$M_CIA_CTRL_PCI_LOCK_EN 0x2&#define CIA$M_CIA_CTRL_PCI_LOOP_EN 0x4$#define CIA$M_CIA_CTRL_FST_BB_EN 0x8"#define CIA$M_CIA_CTRL_MST_EN 0x10"#define CIA$M_CIA_CTRL_MEM_EN 0x20$#define CIA$M_CIA_CTRL_REQ64_EN 0x40$#define CIA$M_CIA_CTRL_ACK64_EN 0x80'#define CIA$M_CIA_CTRL_ADDR_PE_EN 0x100$#define CIA$M_CIA_CTRL_PERR_EN 0x200(#define CIA$M_CIA_CTRL_FILL_ERR_EN 0x400(#defin e CIA$M_CIA_CTRL_ECC_CHK_EN 0x1000(#define CIA$M_CIA_CTRL_CACK_EN_PE 0x2000)#define CIA$M_CIA_CTRL_CON_IDLE_BC 0x4000)#define CIA$M_CIA_CTRL_CSR_IOA_BYP 0x8000+#define CIA$M_CIA_CTRL_IO_FLUSH_REQ 0x10000,#define CIA$M_CIA_CTRL_CPU_FLUSH_REQ 0x20000)#define CIA$M_CIA_CTRL_ARB_EV5_EN 0x40000*#define CIA$M_CIA_CTRL_EN_ARB_LINK 0x80000&#define CIA$M_CIA_CTRL_RD_TYP 0x300000'#define CIA$M_CIA_CTRL_RL_TYP 0x3000000(#define CIA$M_CIA_CTRL_RM_TYP 0x30000000&#define CIA$M_CIA_CNFG_PCI_WIDTH 0x1 00(#define CIA$M_CIA_CNFG_IOD_WIDTH 0x10000 #define CIA$M_HAE_MEM_REG_3 0xFC"#define CIA$M_HAE_MEM_REG_2 0xF800&#define CIA$M_HAE_MEM_REG_1 0xE0000000#define CIA$M_HAE_IO 0xFE000000#define CIA$M_FROM_EN 0x1#define CIA$M_USE_CHECK 0x2 #define CIA$M_FPE_PCI 0x30000000##define CIA$M_FPE_TO_EV5 0x80000000&#define CIA$M_CPU_ERR0_ADDR 0xFFFFFFF0#define CIA$M_CPU_ERR1_3432 0x7#define CIA$M_CPU_ERR1_39 0x80 #define CIA$M_CPU_ERR1_CMD 0xF00(#define CIA$M_CPU_ERR1_INT4_VALID 0xF000&#def ine CIA$M_CPU_ERR1_AC_PAR 0x200000%#define CIA$M_CPU_ERR1_FPE 0x40000000$#define CIA$M_CPU_ERR1_PE 0x80000000#define CIA$M_ERR_CORR_ECC 0x1#define CIA$M_ERR_UNC_ECC 0x2#define CIA$M_ERR_CPU_PE 0x4#define CIA$M_ERR_MEM_NEM 0x8#define CIA$M_ERR_PCI_SERR 0x10#define CIA$M_ERR_PCI_PERR 0x20!#define CIA$M_ERR_PCI_ADR_PE 0x40#define CIA$M_ERR_M_ABORT 0x80#define CIA$M_ERR_T_ABORT 0x100"#define CIA$M_ERR_PA_PTE_INV 0x200$#define CIA$M_ERR_FROM_WRT_ERR 0x400##define CIA$M_ERR_IOA_ TIMEOUT 0x800'#define CIA$M_ERR_LOST_CORR_ECC 0x10000&#define CIA$M_ERR_LOST_UNC_ECC 0x20000%#define CIA$M_ERR_LOST_CPU_PE 0x40000&#define CIA$M_ERR_LOST_MEM_NEM 0x80000(#define CIA$M_ERR_LOST_PCI_SERR 0x100000(#define CIA$M_ERR_LOST_PCI_PERR 0x200000*#define CIA$M_ERR_LOST_PCI_ADR_PE 0x400000'#define CIA$M_ERR_LOST_M_ABORT 0x800000(#define CIA$M_ERR_LOST_T_ABORT 0x1000000+#define CIA$M_ERR_LOST_PA_PTE_INV 0x2000000-#define CIA$M_ERR_LOST_FROM_WRT_ERR 0x4000000,#define CIA$M_ERR_LOST _IOA_TIMEOUT 0x8000000"#define CIA$M_ERR_VALID 0x80000000#define DM_K_IDLE 0#define DM_K_RESTART 4096#define DM_K_IOW_64 8192#define DM_K_IOW_32 12288#define DM_K_R_4 16384#define DM_K_NONE 20480#define DM_K_DMA_RD 24576#define DM_K_DMA_WR 28672#define DM_K_GRU_WR 32768#define DM_K_GRU_RD 36864#define DM_K_CSR_RD 40960#define DM_K_PCI_RD 45056!#define CIA$M_STAT_PCI_STATUS 0x3!#define CIA$M_STAT_MEM_SOURCE 0x8 #define CIA$M_STAT_IO_QUEUE 0xF0"#define CIA$M_STAT _CPU_QUEUE 0x700!#define CIA$M_STAT_TLB_MISS 0x800!#define CIA$M_STAT_DM_STAT 0xF000%#define CIA$M_STAT_PA_CPU_RES 0x30000##define CIA$M_MASK_CORR_ECC_ERR 0x1"#define CIA$M_MASK_UNC_ECC_ERR 0x2#define CIA$M_MASK_CPU_PE 0x4#define CIA$M_MASK_MEM_NEM 0x8 #define CIA$M_MASK_PCI_SERR 0x10 #define CIA$M_MASK_PCI_PERR 0x20"#define CIA$M_MASK_PCI_ADR_PE 0x40#define CIA$M_MASK_M_ABORT 0x80 #define CIA$M_MASK_T_ABORT 0x100##define CIA$M_MASK_PA_PTE_INV 0x200%#define CIA$M_MASK_FROM_WRT_ ERR 0x400$#define CIA$M_MASK_IOA_TIMEOUT 0x800#define CIA$M_CIA_SYNDROME 0xFF%#define CIA$M_MPSR0_ADDR_H 0xFFFFFFF0#define CIA$M_MPSR1_ADDR_H 0x3 #define CIA$M_MPSR1_ADDR_39 0x80#define CIA$M_MPSR1_CMD_H 0xF00$#define CIA$M_MPSR1_PORT_MASK 0xF000"#define CIA$M_MPSR1_SEQ_ST 0xF0000%#define CIA$M_MPSR1_PORT_SRC 0x100000&#define CIA$M_MPSR1_SET_SEL 0x1F000000#define CIA$M_PCIE_CMD 0xF"#define CIA$M_PCIE_LOCK_STATE 0x10!#define CIA$M_PCIE_DAC_CYCLE 0x20#define CIA$M_PCIE_WINDOW 0x F00%#define CIA$M_PCIE_MSTR_STATE 0xF0000&#define CIA$M_PCIE_TRGT_STATE 0x700000#define CIA$M_MCR_MEM_SIZE 0x1!#define CIA$M_MCR_CACHE_SIZE 0x70"#define CIA$M_MCR_REF_RATE 0x3FF00##define CIA$M_MCR_REF_BURST 0xC0000!#define CIA$M_MCR_TMG_R0 0x300000'#define CIA$M_MCR_LONG_CBR_CAS 0x400000'#define CIA$M_MCR_DLY_IDLE_BC 0xC000000*#define CIA$M_MCR_EARLY_IDLE_BC 0x20000000#define CIA$M_MBA0_S0_VALID 0x1#define CIA$M_MBA0_ROW_TYPE 0x6#define CIA$M_MBA0_MASK 0x1F0"#define CIA$M_ MBA0_S1_VALID 0x8000$#define CIA$M_MBA0_PATTERN 0x3FF0000$#define CIA$M_MBA0_TIMING 0x30000000(#define CIA$M_MBA0_RESERVED_5 0xC0000000#define CIA$M_MBA2_S0_VALID 0x1#define CIA$M_MBA2_ROW_TYPE 0x6#define CIA$M_MBA2_MASK 0x1F0"#define CIA$M_MBA2_S1_VALID 0x8000$#define CIA$M_MBA2_PATTERN 0x3FF0000$#define CIA$M_MBA2_TIMING 0x30000000#define CIA$M_MBA4_S0_VALID 0x1#define CIA$M_MBA4_ROW_TYPE 0x6#define CIA$M_MBA4_MASK 0x1F0"#define CIA$M_MBA4_S1_VALID 0x8000$#define CIA$M_MBA4 _PATTERN 0x3FF0000$#define CIA$M_MBA4_TIMING 0x30000000#define CIA$M_MBA6_S0_VALID 0x1#define CIA$M_MBA6_ROW_TYPE 0x6#define CIA$M_MBA6_MASK 0x1F0"#define CIA$M_MBA6_S1_VALID 0x8000$#define CIA$M_MBA6_PATTERN 0x3FF0000$#define CIA$M_MBA6_TIMING 0x30000000#define CIA$M_MBA8_S0_VALID 0x1#define CIA$M_MBA8_ROW_TYPE 0x6#define CIA$M_MBA8_MASK 0x1F0"#define CIA$M_MBA8_S1_VALID 0x8000$#define CIA$M_MBA8_PATTERN 0x3FF0000$#define CIA$M_MBA8_TIMING 0x30000000#define CIA$M_MBAA_S0_VA LID 0x1#define CIA$M_MBAA_ROW_TYPE 0x6#define CIA$M_MBAA_MASK 0x1F0"#define CIA$M_MBAA_S1_VALID 0x8000$#define CIA$M_MBAA_PATTERN 0x3FF0000$#define CIA$M_MBAA_TIMING 0x30000000#define CIA$M_MBAC_S0_VALID 0x1#define CIA$M_MBAC_ROW_TYPE 0x6#define CIA$M_MBAC_MASK 0x1F0"#define CIA$M_MBAC_S1_VALID 0x8000$#define CIA$M_MBAC_PATTERN 0x3FF0000$#define CIA$M_MBAC_TIMING 0x30000000#define CIA$M_MBAE_S0_VALID 0x1#define CIA$M_MBAE_ROW_TYPE 0x6#define CIA$M_MBAE_MASK 0x1F0"#defin e CIA$M_MBAE_S1_VALID 0x8000$#define CIA$M_MBAE_PATTERN 0x3FF0000$#define CIA$M_MBAE_TIMING 0x30000000#define CIA$M_TMG0_R1 0x3#define CIA$M_TMG0_R2 0xC#define CIA$M_TMG0_R3 0x30#define CIA$M_TMG0_R4 0xC0#define CIA$M_TMG0_R5 0x300#define CIA$M_TMG0_R6 0xC00#define CIA$M_TMG0_W1 0x7000#define CIA$M_TMG0_W4 0x38000#define CIA$M_TMG0_PRE 0x40000#define CIA$M_TMG0_V3 0x180000#define CIA$M_TMG0_V4 0x600000#define CIA$M_TMG0_V5 0x3000000#define CIA$M_TMG0_V6 0xC000000 #d efine CIA$M_TMG0_RV 0x30000000$#define CIA$M_TMG0_RD_DLY 0xC0000000#define CIA$M_TMG1_R1 0x3#define CIA$M_TMG1_R2 0xC#define CIA$M_TMG1_R3 0x30#define CIA$M_TMG1_R4 0xC0#define CIA$M_TMG1_R5 0x300#define CIA$M_TMG1_R6 0xC00#define CIA$M_TMG1_W1 0x7000#define CIA$M_TMG1_W4 0x38000#define CIA$M_TMG1_PRE 0x40000#define CIA$M_TMG1_V3 0x180000#define CIA$M_TMG1_V4 0x600000#define CIA$M_TMG1_V5 0x3000000#define CIA$M_TMG1_V6 0xC000000 #define CIA$M_TMG1_RV 0x30000000$#def ine CIA$M_TMG1_RD_DLY 0xC0000000#define CIA$M_TMG2_R1 0x3#define CIA$M_TMG2_R2 0xC#define CIA$M_TMG2_R3 0x30#define CIA$M_TMG2_R4 0xC0#define CIA$M_TMG2_R5 0x300#define CIA$M_TMG2_R6 0xC00#define CIA$M_TMG2_W1 0x7000#define CIA$M_TMG2_W4 0x38000#define CIA$M_TMG2_PRE 0x40000#define CIA$M_TMG2_V3 0x180000#define CIA$M_TMG2_V4 0x600000#define CIA$M_TMG2_V5 0x3000000#define CIA$M_TMG2_V6 0xC000000 #define CIA$M_TMG2_RV 0x30000000$#define CIA$M_TMG2_RD_DLY 0xC0000000"#d efine CIA$M_TBIA_CSR_WR_DATA 0x3#define CIA$M_WBASE0_W_EN 0x1#define CIA$M_WBASE0_SG_EN 0x2!#define CIA$M_WBASE0_MEMCS_EN 0x4#define CIA$M_WBASE0_DAC_EN 0x8$#define CIA$M_WBASE0_BASE 0xFFF00000$#define CIA$M_WMASK0_MASK 0xFFF00000$#define CIA$M_TBASE0_BASE 0xFFFFFF00#define CIA$M_WBASE1_W_EN 0x1#define CIA$M_WBASE1_SG_EN 0x2!#define CIA$M_WBASE1_MEMCS_EN 0x4#define CIA$M_WBASE1_DAC_EN 0x8$#define CIA$M_WBASE1_BASE 0xFFF00000$#define CIA$M_WMASK1_MASK 0xFFF00000$#define CIA$M_ TBASE1_BASE 0xFFFFFF00#define CIA$M_WBASE2_W_EN 0x1#define CIA$M_WBASE2_SG_EN 0x2!#define CIA$M_WBASE2_MEMCS_EN 0x4#define CIA$M_WBASE2_DAC_EN 0x8$#define CIA$M_WBASE2_BASE 0xFFF00000$#define CIA$M_WMASK2_MASK 0xFFF00000$#define CIA$M_TBASE2_BASE 0xFFFFFF00#define CIA$M_WBASE3_W_EN 0x1#define CIA$M_WBASE3_SG_EN 0x2!#define CIA$M_WBASE3_MEMCS_EN 0x4#define CIA$M_WBASE3_DAC_EN 0x8$#define CIA$M_WBASE3_BASE 0xFFF00000$#define CIA$M_WMASK3_MASK 0xFFF00000$#define CIA$M_TBASE3_BAS E 0xFFFFFF00#define CIA$M_DAC_BASE 0xFF#define CIA$M_LTB0_VALID 0x1#define CIA$M_LTB0_LOCKED 0x2#define CIA$M_LTB0_DAC 0x4!#define CIA$M_LTB0_TAG 0xFFFF8000#define CIA$M_LTB1_VALID 0x1#define CIA$M_LTB1_LOCKED 0x2#define CIA$M_LTB1_DAC 0x4!#define CIA$M_LTB1_TAG 0xFFFF8000#define CIA$M_LTB2_VALID 0x1#define CIA$M_LTB2_LOCKED 0x2#define CIA$M_LTB2_DAC 0x4!#define CIA$M_LTB2_TAG 0xFFFF8000#define CIA$M_LTB3_VALID 0x1#define CIA$M_LTB3_LOCKED 0x2#define CIA$M_LTB3_DAC 0x4!#define CIA$M_LTB3_TAG 0xFFFF8000#define CIA$M_TB0_VALID 0x1#define CIA$M_TB0_DAC 0x4 #define CIA$M_TB0_TAG 0xFFFF8000#define CIA$M_TB1_VALID 0x1#define CIA$M_TB1_DAC 0x4 #define CIA$M_TB1_TAG 0xFFFF8000#define CIA$M_TB2_VALID 0x1#define CIA$M_TB2_DAC 0x4 #define CIA$M_TB2_TAG 0xFFFF8000#define CIA$M_TB3_VALID 0x1#define CIA$M_TB3_DAC 0x4 #define CIA$M_TB3_TAG 0xFFFF8000!#define CIA$M_TB0_PAGE0_VALID 0x1%#define CIA$M_TB0_PAGE0_ADDR 0x3FFFFE!#define CIA$M_TB0_PA GE1_VALID 0x1%#define CIA$M_TB0_PAGE1_ADDR 0x3FFFFE!#define CIA$M_TB0_PAGE2_VALID 0x1%#define CIA$M_TB0_PAGE2_ADDR 0x3FFFFE!#define CIA$M_TB0_PAGE3_VALID 0x1%#define CIA$M_TB0_PAGE3_ADDR 0x3FFFFE!#define CIA$M_TB1_PAGE0_VALID 0x1%#define CIA$M_TB1_PAGE0_ADDR 0x3FFFFE!#define CIA$M_TB1_PAGE1_VALID 0x1%#define CIA$M_TB1_PAGE1_ADDR 0x3FFFFE!#define CIA$M_TB1_PAGE2_VALID 0x1%#define CIA$M_TB1_PAGE2_ADDR 0x3FFFFE!#define CIA$M_TB1_PAGE3_VALID 0x1%#define CIA$M_TB1_PAGE3_ADDR 0x3FF FFE!#define CIA$M_TB2_PAGE0_VALID 0x1%#define CIA$M_TB2_PAGE0_ADDR 0x3FFFFE!#define CIA$M_TB2_PAGE1_VALID 0x1%#define CIA$M_TB2_PAGE1_ADDR 0x3FFFFE!#define CIA$M_TB2_PAGE2_VALID 0x1%#define CIA$M_TB2_PAGE2_ADDR 0x3FFFFE!#define CIA$M_TB2_PAGE3_VALID 0x1%#define CIA$M_TB2_PAGE3_ADDR 0x3FFFFE!#define CIA$M_TB3_PAGE0_VALID 0x1%#define CIA$M_TB3_PAGE0_ADDR 0x3FFFFE!#define CIA$M_TB3_PAGE1_VALID 0x1%#define CIA$M_TB3_PAGE1_ADDR 0x3FFFFE!#define CIA$M_TB3_PAGE2_VALID 0x1%#define  CIA$M_TB3_PAGE2_ADDR 0x3FFFFE!#define CIA$M_TB3_PAGE3_VALID 0x1%#define CIA$M_TB3_PAGE3_ADDR 0x3FFFFE!#define CIA$M_TB4_PAGE0_VALID 0x1%#define CIA$M_TB4_PAGE0_ADDR 0x3FFFFE!#define CIA$M_TB4_PAGE1_VALID 0x1%#define CIA$M_TB4_PAGE1_ADDR 0x3FFFFE!#define CIA$M_TB4_PAGE2_VALID 0x1%#define CIA$M_TB4_PAGE2_ADDR 0x3FFFFE!#define CIA$M_TB4_PAGE3_VALID 0x1%#define CIA$M_TB4_PAGE3_ADDR 0x3FFFFE!#define CIA$M_TB5_PAGE0_VALID 0x1%#define CIA$M_TB5_PAGE0_ADDR 0x3FFFFE!#define CIA$M_TB5_ PAGE1_VALID 0x1%#define CIA$M_TB5_PAGE1_ADDR 0x3FFFFE!#define CIA$M_TB5_PAGE2_VALID 0x1%#define CIA$M_TB5_PAGE2_ADDR 0x3FFFFE!#define CIA$M_TB5_PAGE3_VALID 0x1%#define CIA$M_TB5_PAGE3_ADDR 0x3FFFFE!#define CIA$M_TB6_PAGE0_VALID 0x1%#define CIA$M_TB6_PAGE0_ADDR 0x3FFFFE!#define CIA$M_TB6_PAGE1_VALID 0x1%#define CIA$M_TB6_PAGE1_ADDR 0x3FFFFE!#define CIA$M_TB6_PAGE2_VALID 0x1%#define CIA$M_TB6_PAGE2_ADDR 0x3FFFFE!#define CIA$M_TB6_PAGE3_VALID 0x1%#define CIA$M_TB6_PAGE3_ADDR 0x3 FFFFE!#define CIA$M_TB7_PAGE0_VALID 0x1%#define CIA$M_TB7_PAGE0_ADDR 0x3FFFFE!#define CIA$M_TB7_PAGE1_VALID 0x1%#define CIA$M_TB7_PAGE1_ADDR 0x3FFFFE!#define CIA$M_TB7_PAGE2_VALID 0x1%#define CIA$M_TB7_PAGE2_ADDR 0x3FFFFE!#define CIA$M_TB7_PAGE3_VALID 0x1%#define CIA$M_TB7_PAGE3_ADDR 0x3FFFFE c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _cia {N/* CIA ASIC revision 8740000080 */#pragma __nomember_alignment% unsigned char cia$b_fill00 [128]; __union { int cia$l_pci_cia_rev; __struct {N char cia$b_cia_rev; /* CIA revision */' unsigned cia$v_fill01 : 24; } cia$r_rev_bits;! } cia$r_pci_cia_revision;$ unsigned char cia$b_fill02 [60];N/* PCI master latency timeout 874 00000C0 */ __union { int cia$l_pci_lat; __struct { char cia$b_fill10;N char cia$b_pci_latency; /* CIA revision */' unsigned cia$v_fill11 : 16;! } cia$r_latency_bits; } cia$r_pci_latency;$ unsigned char cia$b_fill20 [60];N/* CIA Control register 8740000100 */ __union { int cia$l_cia_ctl; __st ruct {V unsigned cia$v_cia_ctrl_pci_en : 1; /*CIA disable/enable resets to PCI */S unsigned cia$v_cia_ctrl_pci_lock_en : 1; /*CIA locks from PCI enable */N unsigned cia$v_cia_ctrl_pci_loop_en : 1; /*CIA loopback enable */U unsigned cia$v_cia_ctrl_fst_bb_en : 1; /*CIA fast back-to-back enable */P unsigned cia$v_cia_ctrl_mst_en : 1; /*CIA is a PCI master enable */O unsigned cia$v_cia_ctrl_mem_en : 1; /*CIA is a PCI target en able */[ unsigned cia$v_cia_ctrl_req64_en : 1; /*CIA will request 64bit PCI txactions */[ unsigned cia$v_cia_ctrl_ack64_en : 1; /*CIA will accept 64bit PCI txactions */] unsigned cia$v_cia_ctrl_addr_pe_en : 1; /*CIA will check address parity enable */T unsigned cia$v_cia_ctrl_perr_en : 1; /*CIA will check PCI data enable */Y unsigned cia$v_cia_ctrl_fill_err_en : 1; /*CIA will assert fill_err enable */& unsigned cia$v_fill20  : 1;S unsigned cia$v_cia_ctrl_ecc_chk_en : 1; /*CIA checks IOD data enable */V unsigned cia$v_cia_ctrl_cack_en_pe : 1; /*CIA checks c/a parity on CACK */W unsigned cia$v_cia_ctrl_con_idle_bc : 1; /*CIA generated contig. IDLE_BC */U unsigned cia$v_cia_ctrl_csr_ioa_byp : 1; /*CIA bypasses I/O addr queue */] unsigned cia$v_cia_ctrl_io_flush_req : 1; /*Controls response to PCI FLUSH_REQ */^ unsigned cia$v_cia_ctrl_cpu_flush_req :  1; /*Controls response to PCI FLUSH_REQ */Y unsigned cia$v_cia_ctrl_arb_ev5_en : 1; /*Enable bypass path ev5 to mem/io */4 unsigned cia$v_cia_ctrl_en_arb_link : 1;R unsigned cia$v_cia_ctrl_rd_typ : 2; /*Control prefetch algorithm RD */& unsigned cia$v_fill21 : 2;R unsigned cia$v_cia_ctrl_rl_typ : 2; /*Control prefetch algorithm RL */& unsigned cia$v_fill22 : 2;R unsigned cia$v_cia_ctrl_rm_typ : 2; /*Control prefetch a  lgorithm RM */& unsigned cia$v_fill23 : 2;% } cia$r_cia_control_bits; } cia$r_cia_control;% unsigned char cia$b_fill30 [252];N/* CIA Config => Size information of the two busses 8740000200 */ __union { int cia$l_cia_config; __struct { char cia$b_fill30a;P unsigned cia$v_cia_cnfg_pci_width : 1; /* Bit is set -> 64bit PCI */& unsigned cia$v_fill31 : 7;P unsigned cia$v_cia_cnf  g_iod_width : 1; /* Bit is set -> 64bit IOD */' unsigned cia$v_fill32 : 15;$ } cia$r_cia_config_bits;# } cia$r_cia_config_overlay;% unsigned char cia$b_fill40 [508];N/* HAE MEM => Extends sparse space addr to full 32 bits 8740000400 */ __union { int cia$l_hae_mem; __struct {' unsigned cia$v_fill40a : 2;N unsigned cia$v_hae_mem_reg_3 : 6; /* High order sparse bits */& unsigned cia$v_fill4  1 : 3;N unsigned cia$v_hae_mem_reg_2 : 5; /* High order sparse bits */' unsigned cia$v_fill42 : 13;N unsigned cia$v_hae_mem_reg_1 : 3; /* High order sparse bits */! } cia$r_hae_mem_bits; } cia$r_hae_mem_overlay;$ unsigned char cia$b_fill50 [60];N/* HAE IO => Extends sparse space addr to full 32 bits 8740000440 */ __union { int cia$l_hae_io; __struct {' unsigned cia$v_fill51 : 25;N  unsigned cia$v_hae_io : 7; /* High order sparse bits */ } cia$r_hae_io_bits; } cia$r_hae_io_overlay;$ unsigned char cia$b_fill60 [60];N/* CFG => Low two address bits during access to PCI COnfig space 8740000480 */ __union { int cia$l_cfg; __struct {Q unsigned cia$v_cfg_bits : 2; /* Low order bits of config space ref */' unsigned cia$v_fill61 : 29;' unsigned cia$v_fill_0_ : 1;%  } cia$r_cgf_bits_overlay; } cia$r_cfg_overlay;% unsigned char cia$b_fill70 [380];N/* CACK_EN Enable CIA's response to EV5 commands 840000600 */ __union { int cia$l_cack_en; __struct {P unsigned cia$v_cack_en_bits : 4; /* Control CIA's response to EV5 */' unsigned cia$v_fill71 : 28;! } cia$r_cack_en_bits; } cia$r_cack_en_overlay;& unsigned char cia$b_fill80 [6652];N/* CIA_DIAG Diagnostic co  ntrol enable 840002000 */ __union { int cia$l_cia_diag; __struct {N unsigned cia$v_from_en : 1; /* FROM write enable */S unsigned cia$v_use_check : 1; /* USed with DIA_CHECK for ECC testing */' unsigned cia$v_fill81 : 26;N unsigned cia$v_fpe_pci : 2; /* Force bad parity on PCI */& unsigned cia$v_fill82 : 1;N unsigned cia$v_fpe_to_ev5 : 1; /* Force pari  ty error */" } cia$r_cia_diag_bits;! } cia$r_cia_diag_overlay;& unsigned char cia$b_fill90 [4092];N/* DIAG_CHECK Diagnostic used to write a known ECC pattern 840003000 */ __union { int cia$l_diag_check; __struct {N char cia$b_diag_check_ecc; /* ECC to be used */' unsigned cia$v_fill91 : 24;$ } cia$r_diag_check_bits;# } cia$r_diag_check_overlay;' unsigned char cia$  b_fill100 [4092];N/* Perf Monitor counts 8740004000 */ __union { int cia$l_perf_monitor;% } cia$r_perf_monitor_overlay;% unsigned char cia$b_fill110 [60];N/* Perf Monitor control 8740004040 */ __union { int cia$l_perf_control;% } cia$r_perf_control_overlay;( unsigned char cia$b_fill120 [16316];N/* CPU Error reigster 0 8740008000  */ __union { int cia$l_cpu_err0; __struct {& unsigned cia$v_fillc0 : 4;T unsigned cia$v_cpu_err0_addr : 28; /* Bad addr on EV5 interface error */" } cia$r_cpu_err0_bits;! } cia$r_cpu_err0_overlay;% unsigned char cia$b_fill130 [60];N/* CPU error register 1 8740008040 */ __union { int cia$l_cpu_err1; __struct {N unsigned cia$v_cpu_err1_  3432 : 3; /* CPU addr <34:32> on error */& unsigned cia$v_filld0 : 4;N unsigned cia$v_cpu_err1_39 : 1; /* CPU addr <39> on error */N unsigned cia$v_cpu_err1_cmd : 4; /* CPU command */N unsigned cia$v_cpu_err1_int4_valid : 4; /* INT4 valid bits */& unsigned cia$v_filld1 : 5;R unsigned cia$v_cpu_err1_ac_par : 1; /* Parity bit from CPU Addr/cmd */& unsigned cia$v_filld2 : 8;U unsign  ed cia$v_cpu_err1_fpe : 1; /*Copy of csr bit to force bad parity */N unsigned cia$v_cpu_err1_pe : 1; /*IF set, CPU detected PE. */" } cia$r_cpu_err1_bits;! } cia$r_cpu_err1_overlay;& unsigned char cia$b_fill140 [444];N/* CIA Error reigster 8740008200 */ __union { int cia$l_cia_err; __struct {N unsigned cia$v_err_corr_ecc : 1; /* [0] */N unsign ed cia$v_err_unc_ecc : 1; /* [1] */N unsigned cia$v_err_cpu_pe : 1; /* [2] */N unsigned cia$v_err_mem_nem : 1; /* [3] */N unsigned cia$v_err_pci_serr : 1; /* [4] */N unsigned cia$v_err_pci_perr : 1; /* [5] */N unsigned cia$v_err_pci_adr_pe : 1; /* [6] */N unsigned cia$v_err_m_abort : 1;  /* [7] */N unsigned cia$v_err_t_abort : 1; /* [8] */N unsigned cia$v_err_pa_pte_inv : 1; /* [9] */N unsigned cia$v_err_from_wrt_err : 1; /* [10] */N unsigned cia$v_err_ioa_timeout : 1; /* [11] */N unsigned cia$v_err_ioa_reserved_0 : 4; /* [15:12] */1 unsigned cia$v_err_lost_corr_ecc : 1;0 unsign  ed cia$v_err_lost_unc_ecc : 1;/ unsigned cia$v_err_lost_cpu_pe : 1;0 unsigned cia$v_err_lost_mem_nem : 1;1 unsigned cia$v_err_lost_pci_serr : 1;1 unsigned cia$v_err_lost_pci_perr : 1;3 unsigned cia$v_err_lost_pci_adr_pe : 1;0 unsigned cia$v_err_lost_m_abort : 1;0 unsigned cia$v_err_lost_t_abort : 1;3 unsigned cia$v_err_lost_pa_pte_inv : 1;5 unsigned cia$v_err_lost_from_wrt_err : 1;4 unsigned cia$v_err_lost_ioa_timeout : 1;N unsigned cia$v_err_lost_reserved_1 : 3; /* */) unsigned cia$v_err_valid : 1;! } cia$r_cia_err_bits; } cia$r_cia_err_overlay;% unsigned char cia$b_fill150 [60];N/* */N/* CIA Error status register - 0x8740008240 */N/* ! */ __union { int cia$l_cia_stat; __struct {N unsigned cia$v_stat_pci_status : 2; /* [1:0] */N unsigned cia$v_stat_fill1 : 1; /* [2] */N unsigned cia$v_stat_mem_source : 1; /* [3] */N unsigned cia$v_stat_io_queue : 4; /* [7:4] */N unsigned cia$v_stat_cpu_queue : 3; /* [10:8] */N unsigned c " ia$v_stat_tlb_miss : 1; /* [11] */N unsigned cia$v_stat_dm_stat : 4; /* [15:12] */N unsigned cia$v_stat_pa_cpu_res : 2; /* [17:16] */N unsigned cia$v_stat_reserved_0 : 14; /* [31:18] */" } cia$r_cia_stat_bits;! } cia$r_cia_stat_overlay;% unsigned char cia$b_fill160 [60];N/* */N/* # */N/* CIA Error mask register - 0x8740008280 */N/* */ __union {! int cia$l_cia_error_mask; __struct {N unsigned cia$v_mask_corr_ecc_err : 1; /* [0] */N unsigned cia$v_mask_unc_ecc_err : 1; /* [1] */N unsigned cia$v_mask_cpu_pe : 1; /* [$ 2] */N unsigned cia$v_mask_mem_nem : 1; /* [3] */N unsigned cia$v_mask_pci_serr : 1; /* [4] */N unsigned cia$v_mask_pci_perr : 1; /* [5] */N unsigned cia$v_mask_pci_adr_pe : 1; /* [6] */N unsigned cia$v_mask_m_abort : 1; /* [7] */N unsigned cia$v_mask_t_abort : 1; /* [8] % */N unsigned cia$v_mask_pa_pte_inv : 1; /* [9] */N unsigned cia$v_mask_from_wrt_err : 1; /* [10] */N unsigned cia$v_mask_ioa_timeout : 1; /* [11] */N unsigned cia$v_mask_reserved_1 : 20; /* [30:12] */( } cia$r_cia_error_mask_bits;' } cia$r_cia_error_mask_overlay;& unsigned char cia$b_fill170 [124];N/* & */N/* CIA Error Syndrome register - 0x8740008300 */N/* */ __union { int cia$l_cia_synd; __struct {, unsigned cia$v_cia_syndrome : 8;% unsigned cia$v_fill : 24;" } cia$r_cia_synd_bits; } cia$r_cia_syndrome;& unsigned char cia$b_fill180 [252];N/* ' */N/* CIA Memory Port status register 0 - 0x8740008400 */N/* */ __union { int cia$l_cia_mpsr0; __struct {( unsigned cia$v_unused_0 : 4;- unsigned cia$v_mpsr0_addr_h : 28;# } cia$r_cia_mpsr0_bits;" } cia$r_cia_mpsr0_overlay;% unsigned char cia$b_fill190 [60];N/* ( */N/* CIA Memory Port status register 1 - 0x8740008440 */N/* */ __union { int cia$l_cia_mpsr1; __struct {N unsigned cia$v_mpsr1_addr_h : 2; /* [1:0] */N unsigned cia$v_mpsr1_reserved : 5; /* [6:2] */N unsigned cia$v_mpsr1_addr_39 : 1; /* [7] */N ) unsigned cia$v_mpsr1_cmd_h : 4; /* [11:8] */N unsigned cia$v_mpsr1_port_mask : 4; /* [15:12] */N unsigned cia$v_mpsr1_seq_st : 4; /* [19:16] */N unsigned cia$v_mpsr1_port_src : 1; /* [20] */N unsigned cia$v_mpsr1_reserved_2 : 3; /* [23:21] */N unsigned cia$v_mpsr1_set_sel : 5; /* [28:24] */N unsigned cia$v_mpsr1_reser * ved_3 : 3; /* [31:29] */# } cia$r_cia_mpsr1_bits;" } cia$r_cia_mpsr1_overlay;& unsigned char cia$b_fill200 [956];N/* */N/* PCI Error register 0 - 0x8740008800 */N/* */ __union { int cia$l_cia_pcie0; __struct {N unsigned cia$v_pcie_cmd : 4; /+ * [3:0] */N unsigned cia$v_pcie_lock_state : 1; /* [4] */N unsigned cia$v_pcie_dac_cycle : 1; /* [5] */N unsigned cia$v_pcie_reserved : 2; /* [7:6] */N unsigned cia$v_pcie_window : 4; /* [11:8] */N unsigned cia$v_pcie_reserved_2 : 4; /* [15:12] */N unsigned cia$v_pcie_mstr_state : 4; /* [19:16] , */N unsigned cia$v_pcie_trgt_state : 3; /* [22:20] */N unsigned cia$v_pcie_unused_2 : 9; /* [31:23] */" } cia$r_cia_pcie_bits;" } cia$r_cia_pcie0_overlay;% unsigned char cia$b_fill210 [60];N/* */N/* CIA PCI error register 1 - 0x8740008840 */N/* - */ __union {# int cia$l_pcie1_mem_addr_h;" } cia$r_cia_pcie1_overlay;' unsigned char cia$b_fill220 [6076];N/* */N/* Memory Configuration Register - 0x8750000000 */N/* */ __union { int cia$l_mem_mcr; __struct {N unsigned cia$v_mcr_mem_size : 1; /* . */N unsigned cia$v_mcr_reserved : 3; /* */N unsigned cia$v_mcr_cache_size : 3; /* */N unsigned cia$v_mcr_reserved_2 : 1; /* */N unsigned cia$v_mcr_ref_rate : 10; /* */N unsigned cia$v_mcr_ref_burst : 2; /* */N unsigned cia$v_mcr_tmg_r0 : 2; /* / */N unsigned cia$v_mcr_long_cbr_cas : 1; /* */N unsigned cia$v_mcr_reserved_3 : 3; /* */N unsigned cia$v_mcr_dly_idle_bc : 2; /* */N unsigned cia$v_mcr_unused_4 : 1; /* */N unsigned cia$v_mcr_early_idle_bc : 1; /* */N unsigned cia$v_mcr_unused_5 : 2; /* */! } cia$r_me 0 m_mcr_bits; } cia$r_mem_mcr_overlay;' unsigned char cia$b_fill230 [1532];N/* */N/* Memory Base Address 0 Register - 0x8750000600 */N/* */ __union { int cia$l_mem_mba0; __struct {N unsigned cia$v_mba0_s0_valid : 1; /* */N unsigned cia$v_m1 ba0_row_type : 2; /* */N unsigned cia$v_mba0_reserved : 1; /* */N unsigned cia$v_mba0_mask : 5; /* */N unsigned cia$v_mba0_reserved_2 : 6; /* */N unsigned cia$v_mba0_s1_valid : 1; /* */N unsigned cia$v_mba0_pattern : 10; /* */N unsigned cia$v_mba0_reserved_3 : 2; /* 2 */N unsigned cia$v_mba0_timing : 2; /* */N unsigned cia$v_mba0_reserved_5 : 2; /* */" } cia$r_mem_mba0_bits;! } cia$r_mem_mba0_overlay;& unsigned char cia$b_fill240 [124];N/* */N/* Memory Base Address 2 Register - 0x8750000680 */N/* 3 */ __union { int cia$l_mem_mba2; __struct {N unsigned cia$v_mba2_s0_valid : 1; /* */N unsigned cia$v_mba2_row_type : 2; /* */N unsigned cia$v_mba2_reserved : 1; /* */N unsigned cia$v_mba2_mask : 5; /* */N unsigned cia$v_mba2_reserved_2 : 6; /* */N 4 unsigned cia$v_mba2_s1_valid : 1; /* */N unsigned cia$v_mba2_pattern : 10; /* */N unsigned cia$v_mba2_reserved_3 : 2; /* */N unsigned cia$v_mba2_timing : 2; /* */N unsigned cia$v_mba2_reserved_5 : 2; /* */" } cia$r_mem_mba2_bits;! } cia$r_mem_mba2_overlay;& unsigned char cia$b_fill250 [124];N 5 /* */N/* Memory Base Address 4 Register - 0x8750000700 */N/* */ __union { int cia$l_mem_mba4; __struct {N unsigned cia$v_mba4_s0_valid : 1; /* */N unsigned cia$v_mba4_row_type : 2; /* */N unsigned cia$v_mba4_reserv6 ed : 1; /* */N unsigned cia$v_mba4_mask : 5; /* */N unsigned cia$v_mba4_reserved_2 : 6; /* */N unsigned cia$v_mba4_s1_valid : 1; /* */N unsigned cia$v_mba4_pattern : 10; /* */N unsigned cia$v_mba4_reserved_3 : 2; /* */N unsigned cia$v_mba4_timing : 2; /* 7 */N unsigned cia$v_mba4_reserved_5 : 2; /* */" } cia$r_mem_mba4_bits;! } cia$r_mem_mba4_overlay;& unsigned char cia$b_fill260 [124];N/* */N/* Memory Base Address 6 Register - 0x8750000780 */N/* */ __union { int cia$l_mem_mba6; __st8 ruct {N unsigned cia$v_mba6_s0_valid : 1; /* */N unsigned cia$v_mba6_row_type : 2; /* */N unsigned cia$v_mba6_reserved : 1; /* */N unsigned cia$v_mba6_mask : 5; /* */N unsigned cia$v_mba6_reserved_2 : 6; /* */N unsigned cia$v_mba6_s1_valid : 1; /* */N unsi 9 gned cia$v_mba6_pattern : 10; /* */N unsigned cia$v_mba6_reserved_3 : 2; /* */N unsigned cia$v_mba6_timing : 2; /* */N unsigned cia$v_mba6_reserved_5 : 2; /* */" } cia$r_mem_mba6_bits;! } cia$r_mem_mba6_overlay;& unsigned char cia$b_fill270 [124];N/* */N/* Memory : Base Address 8 Register - 0x8750000800 */N/* */ __union { int cia$l_mem_mba8; __struct {N unsigned cia$v_mba8_s0_valid : 1; /* */N unsigned cia$v_mba8_row_type : 2; /* */N unsigned cia$v_mba8_reserved : 1; /* */N unsigned cia$v_mba8_mask : 5; /* ; */N unsigned cia$v_mba8_reserved_2 : 6; /* */N unsigned cia$v_mba8_s1_valid : 1; /* */N unsigned cia$v_mba8_pattern : 10; /* */N unsigned cia$v_mba8_reserved_3 : 2; /* */N unsigned cia$v_mba8_timing : 2; /* */N unsigned cia$v_mba8_reserved_5 : 2; /* < */" } cia$r_mem_mba8_bits;! } cia$r_mem_mba8_overlay;& unsigned char cia$b_fill280 [124];N/* */N/* Memory Base Address 10 Register - 0x8750000880 */N/* */ __union { int cia$l_mem_mbaa; __struct {N unsigned cia$v_mbaa_s0_valid : 1; /* */N= unsigned cia$v_mbaa_row_type : 2; /* */N unsigned cia$v_mbaa_reserved : 1; /* */N unsigned cia$v_mbaa_mask : 5; /* */N unsigned cia$v_mbaa_reserved_2 : 6; /* */N unsigned cia$v_mbaa_s1_valid : 1; /* */N unsigned cia$v_mbaa_pattern : 10; /* */N unsigned cia$v > _mbaa_reserved_3 : 2; /* */N unsigned cia$v_mbaa_timing : 2; /* */N unsigned cia$v_mbaa_reserved_5 : 2; /* */" } cia$r_mem_mbaa_bits;! } cia$r_mem_mbaa_overlay;& unsigned char cia$b_fill290 [124];N/* */N/* Memory Base Address C Register - 0x8750000900 */N/* ? */ __union { int cia$l_mem_mbac; __struct {N unsigned cia$v_mbac_s0_valid : 1; /* */N unsigned cia$v_mbac_row_type : 2; /* */N unsigned cia$v_mbac_reserved : 1; /* */N unsigned cia$v_mbac_mask : 5; /* */N unsigned cia$v_mbac_reserved_2 : 6; /* @ */N unsigned cia$v_mbac_s1_valid : 1; /* */N unsigned cia$v_mbac_pattern : 10; /* */N unsigned cia$v_mbac_reserved_3 : 2; /* */N unsigned cia$v_mbac_timing : 2; /* */N unsigned cia$v_mbac_reserved_5 : 2; /* */" } cia$r_mem_mbac_bits;! } cia$r_mem_mbac_overlay;& unsigned A char cia$b_fill300 [124];N/* */N/* Memory Base Address E Register - 0x8750000980 */N/* */ __union { int cia$l_mem_mbae; __struct {N unsigned cia$v_mbae_s0_valid : 1; /* */N unsigned cia$v_mbae_row_type : 2; /* */N B unsigned cia$v_mbae_reserved : 1; /* */N unsigned cia$v_mbae_mask : 5; /* */N unsigned cia$v_mbae_reserved_2 : 6; /* */N unsigned cia$v_mbae_s1_valid : 1; /* */N unsigned cia$v_mbae_pattern : 10; /* */N unsigned cia$v_mbae_reserved_3 : 2; /* */N unsigned cia$v_mbae_timi C ng : 2; /* */N unsigned cia$v_mbae_reserved_5 : 2; /* */" } cia$r_mem_mbae_bits;! } cia$r_mem_mbae_overlay;& unsigned char cia$b_fill310 [380];N/* */N/* Memory Timing Register 0 - 0x8750000B00 */N/* */ __union { int ciD a$l_mem_tmg0; __struct {N unsigned cia$v_tmg0_r1 : 2; /* */N unsigned cia$v_tmg0_r2 : 2; /* */N unsigned cia$v_tmg0_r3 : 2; /* */N unsigned cia$v_tmg0_r4 : 2; /* */N unsigned cia$v_tmg0_r5 : 2; /* */N unsigned cia$v_tmg0_r6 : 2; /* E */N unsigned cia$v_tmg0_w1 : 3; /* */N unsigned cia$v_tmg0_w4 : 3; /* */N unsigned cia$v_tmg0_pre : 1; /* */N unsigned cia$v_tmg0_v3 : 2; /* */N unsigned cia$v_tmg0_v4 : 2; /* */N unsigned cia$v_tmg0_reserved : 1; /* */N un F signed cia$v_tmg0_v5 : 2; /* */N unsigned cia$v_tmg0_v6 : 2; /* */N unsigned cia$v_tmg0_rv : 2; /* */N unsigned cia$v_tmg0_rd_dly : 2; /* */" } cia$r_mem_tmg0_bits;! } cia$r_mem_tmg0_overlay;% unsigned char cia$b_fill320 [60];N/* */N/* Memor G y Timing Register 1 - 0x8750000B40 */N/* */ __union { int cia$l_mem_tmg1; __struct {N unsigned cia$v_tmg1_r1 : 2; /* */N unsigned cia$v_tmg1_r2 : 2; /* */N unsigned cia$v_tmg1_r3 : 2; /* */N unsigned cia$v_tmg1_r4 : 2; /* H */N unsigned cia$v_tmg1_r5 : 2; /* */N unsigned cia$v_tmg1_r6 : 2; /* */N unsigned cia$v_tmg1_w1 : 3; /* */N unsigned cia$v_tmg1_w4 : 3; /* */N unsigned cia$v_tmg1_pre : 1; /* */N unsigned cia$v_tmg1_v3 : 2; /* I */N unsigned cia$v_tmg1_v4 : 2; /* */N unsigned cia$v_tmg1_reserved : 1; /* */N unsigned cia$v_tmg1_v5 : 2; /* */N unsigned cia$v_tmg1_v6 : 2; /* */N unsigned cia$v_tmg1_rv : 2; /* */N unsigned cia$v_tmg1_rd_dly : 2; /* */" } cia$ J r_mem_tmg1_bits;! } cia$r_mem_tmg1_overlay;% unsigned char cia$b_fill330 [60];N/* */N/* Memory Timing Register 2 - 0x8750000B80 */N/* */ __union { int cia$l_mem_tmg2; __struct {N unsigned cia$v_tmg2_r1 : 2; /* */N unsigned ciaK $v_tmg2_r2 : 2; /* */N unsigned cia$v_tmg2_r3 : 2; /* */N unsigned cia$v_tmg2_r4 : 2; /* */N unsigned cia$v_tmg2_r5 : 2; /* */N unsigned cia$v_tmg2_r6 : 2; /* */N unsigned cia$v_tmg2_w1 : 3; /* */N unsigned cia$v_tmg2_w4 : 3; /* L */N unsigned cia$v_tmg2_pre : 1; /* */N unsigned cia$v_tmg2_v3 : 2; /* */N unsigned cia$v_tmg2_v4 : 2; /* */N unsigned cia$v_tmg2_reserved : 1; /* */N unsigned cia$v_tmg2_v5 : 2; /* */N unsigned cia$v_tmg2_v6 : 2; /* M */N unsigned cia$v_tmg2_rv : 2; /* */N unsigned cia$v_tmg2_rd_dly : 2; /* */" } cia$r_mem_tmg2_bits;! } cia$r_mem_tmg2_overlay;' unsigned char cia$b_fill340 [5244];N/* */N/* PCI Scatter/Gather TBIA - 0x8760000100 */N/* N */& unsigned char cia$b_fill345 [256]; __union { int cia$l_pci_tbia; __struct {N unsigned cia$v_tbia_csr_wr_data : 2; /* */N unsigned cia$v_tbia_reserved : 30; /* */" } cia$r_pci_tbia_bits;! } cia$r_pci_tbia_overlay;& unsigned char cia$b_fill350 [764];N/* */N/* PCI Window Base 0 - 0x8760000 O 400 */N/* */ __union { int cia$l_pci_wbase0; __struct {N unsigned cia$v_wbase0_w_en : 1; /* */N unsigned cia$v_wbase0_sg_en : 1; /* enable scatter/gather */N unsigned cia$v_wbase0_memcs_en : 1; /* enable MEMCS */N unsigned cia$v_wbase0_dac_en : 1; /* enable 64BIT PCI P */N unsigned cia$v_wbase0_reserved : 16; /* */, unsigned cia$v_wbase0_base : 12;$ } cia$r_pci_wbase0_bits;# } cia$r_pci_wbase0_overlay;% unsigned char cia$b_fill360 [60];N/* */N/* PCI Window Mask 0 - 0x8760000440 */N/* */ __union { Q  int cia$l_pci_wmask0; __struct {N unsigned cia$v_wmask0_reserved : 20; /* */, unsigned cia$v_wmask0_mask : 12;$ } cia$r_pci_wmask0_bits;# } cia$r_pci_wmask0_overlay;% unsigned char cia$b_fill370 [60];N/* */N/* PCI Window Translated Base 0 - 0x8760000480 */N/* R */ __union { int cia$l_pci_tbase0; __struct {N unsigned cia$v_tbase0_reserved : 8; /* */, unsigned cia$v_tbase0_base : 24;$ } cia$r_pci_tbase0_bits;# } cia$r_pci_tbase0_overlay;& unsigned char cia$b_fill380 [124];N/****** */N/* */N/* S PCI Window Base 1 - 0x8760000500 */N/* */ __union { int cia$l_pci_wbase1; __struct {N unsigned cia$v_wbase1_w_en : 1; /* */N unsigned cia$v_wbase1_sg_en : 1; /* enable scatter/gather */N unsigned cia$v_wbase1_memcs_en : 1; /* enable MEMCS */N unsigned cia$v_wbase1_dac_ T en : 1; /* enable 64BIT PCI */N unsigned cia$v_wbase1_reserved : 16; /* */, unsigned cia$v_wbase1_base : 12;$ } cia$r_pci_wbase1_bits;# } cia$r_pci_wbase1_overlay;% unsigned char cia$b_fill390 [60];N/* */N/* PCI Window Mask 1 - 0x8760000540 */N/* U */ __union { int cia$l_pci_wmask1; __struct {N unsigned cia$v_wmask1_reserved : 20; /* */, unsigned cia$v_wmask1_mask : 12;$ } cia$r_pci_wmask1_bits;# } cia$r_pci_wmask1_overlay;% unsigned char cia$b_fill400 [60];N/* */N/* PCI Window Translated Base 1 - 0x8760000580 */N/* V */ __union { int cia$l_pci_tbase1; __struct {N unsigned cia$v_tbase1_reserved : 8; /* */, unsigned cia$v_tbase1_base : 24;$ } cia$r_pci_tbase1_bits;# } cia$r_pci_tbase1_overlay;& unsigned char cia$b_fill410 [124];N/* */N/* PCI Window Base 2 - 0x8760000600 W */N/* */ __union { int cia$l_pci_wbase2; __struct {N unsigned cia$v_wbase2_w_en : 1; /* */N unsigned cia$v_wbase2_sg_en : 1; /* enable scatter/gather */N unsigned cia$v_wbase2_memcs_en : 1; /* enable MEMCS */N unsigned cia$v_wbase2_dac_en : 1; /* enable 64BIT PCI */N X unsigned cia$v_wbase2_reserved : 16; /* */, unsigned cia$v_wbase2_base : 12;$ } cia$r_pci_wbase2_bits;# } cia$r_pci_wbase2_overlay;% unsigned char cia$b_fill420 [60];N/* */N/* PCI Window Mask 2 - 0x8760000640 */N/* */ __union { int ci Y a$l_pci_wmask2; __struct {N unsigned cia$v_wmask2_reserved : 20; /* */, unsigned cia$v_wmask2_mask : 12;$ } cia$r_pci_wmask2_bits;# } cia$r_pci_wmask2_overlay;% unsigned char cia$b_fill430 [60];N/* */N/* PCI Window Translated Base 2 - 0x8760000680 */N/* Z */ __union { int cia$l_pci_tbase2; __struct {N unsigned cia$v_tbase2_reserved : 8; /* */, unsigned cia$v_tbase2_base : 24;$ } cia$r_pci_tbase2_bits;# } cia$r_pci_tbase2_overlay;& unsigned char cia$b_fill440 [124];N/* */N/* PCI Window Base 3 - 0x8760000700 */N/* [ */ __union { int cia$l_pci_wbase3; __struct {N unsigned cia$v_wbase3_w_en : 1; /* */N unsigned cia$v_wbase3_sg_en : 1; /* enable scatter/gather */N unsigned cia$v_wbase3_memcs_en : 1; /* enable MEMCS */N unsigned cia$v_wbase3_dac_en : 1; /* enable 64BIT PCI */N unsigned cia$v_wbase3_reserved : 16; /* \ */, unsigned cia$v_wbase3_base : 12;$ } cia$r_pci_wbase3_bits;# } cia$r_pci_wbase3_overlay;% unsigned char cia$b_fill450 [60];N/* */N/* PCI Window Mask 3 - 0x8760000740 */N/* */ __union { int cia$l_pci_wmask3; __struct {N ] unsigned cia$v_wmask3_reserved : 20; /* */, unsigned cia$v_wmask3_mask : 12;$ } cia$r_pci_wmask3_bits;# } cia$r_pci_wmask3_overlay;% unsigned char cia$b_fill460 [60];N/* */N/* PCI Window Translated Base 3 - 0x8760000780 */N/* */ __union { int cia$ ^ l_pci_tbase3; __struct {N unsigned cia$v_tbase3_reserved : 8; /* */, unsigned cia$v_tbase3_base : 24;$ } cia$r_pci_tbase3_bits;# } cia$r_pci_tbase3_overlay;% unsigned char cia$b_fill470 [60];N/* */N/* PCI DAC Base Register - 0x87600007C0 */N/* _ */ __union { int cia$l_pci_dac; __struct {( unsigned cia$v_dac_base : 8;N unsigned cia$v_dac_reserved : 24; /* */! } cia$r_pci_dac_bits; } cia$r_pci_dac_overlay;% unsigned char cia$b_fill480 [60];N/* */N/* PCI Lockable TB Tag 0- 0x8760000800 */N/* ` */ __union { int cia$l_pci_ltb0; __struct {N unsigned cia$v_ltb0_valid : 1; /* */N unsigned cia$v_ltb0_locked : 1; /* enable scatter/gather */N unsigned cia$v_ltb0_dac : 1; /* enable 64BIT PCI */N unsigned cia$v_ltb0_reserved : 12; /* */) unsigned cia$v_ltb0_tag : 17;" } cia$r_pci_ltb0 a _bits;! } cia$r_pci_ltb0_overlay;% unsigned char cia$b_fill490 [60];N/* */N/* PCI Lockable TB Tag 1- 0x8760000840 */N/* */ __union { int cia$l_pci_ltb1; __struct {N unsigned cia$v_ltb1_valid : 1; /* */N unsigned cia$v_ltb1_lo b cked : 1; /* enable scatter/gather */N unsigned cia$v_ltb1_dac : 1; /* enable 64BIT PCI */N unsigned cia$v_ltb1_reserved : 12; /* */) unsigned cia$v_ltb1_tag : 17;" } cia$r_pci_ltb1_bits;! } cia$r_pci_ltb1_overlay;% unsigned char cia$b_fill500 [60];N/* */N/* PCI Lockable TB Tag 2- 0x8760000880 c */N/* */ __union { int cia$l_pci_ltb2; __struct {N unsigned cia$v_ltb2_valid : 1; /* */N unsigned cia$v_ltb2_locked : 1; /* enable scatter/gather */N unsigned cia$v_ltb2_dac : 1; /* enable 64BIT PCI */N unsigned cia$v_ltb2_reserved : 12; /* */) unsigned c d ia$v_ltb2_tag : 17;" } cia$r_pci_ltb2_bits;! } cia$r_pci_ltb2_overlay;% unsigned char cia$b_fill510 [60];N/* */N/* PCI Lockable TB Tag 3- 0x87600008C0 */N/* */ __union { int cia$l_pci_ltb3; __struct {N unsigned cia$v_ltb3_valid : 1; /* e */N unsigned cia$v_ltb3_locked : 1; /* enable scatter/gather */N unsigned cia$v_ltb3_dac : 1; /* enable 64BIT PCI */N unsigned cia$v_ltb3_reserved : 12; /* */) unsigned cia$v_ltb3_tag : 17;" } cia$r_pci_ltb3_bits;! } cia$r_pci_ltb3_overlay;% unsigned char cia$b_fill520 [60];N/* */N/* PCI TB Tag f 0- 0x8760000900 */N/* */ __union { int cia$l_pci_tb0; __struct {N unsigned cia$v_tb0_valid : 1; /* */N unsigned cia$v_reserved : 1; /* */N unsigned cia$v_tb0_dac : 1; /* enable 64BIT PCI */N unsigned cia$v_tb0_reserved2 : 12; /* g */( unsigned cia$v_tb0_tag : 17;! } cia$r_pci_tb0_bits; } cia$r_pci_tb0_overlay;% unsigned char cia$b_fill530 [60];N/* */N/* PCI TB Tag 1 - 0x8760000940 */N/* */ __union { int cia$l_pci_tb1; __struct {N unsigned c h ia$v_tb1_valid : 1; /* */N unsigned cia$v_tb1_reserved : 1; /* */N unsigned cia$v_tb1_dac : 1; /* enable 64BIT PCI */N unsigned cia$v_tb1_reserved2 : 12; /* */( unsigned cia$v_tb1_tag : 17;! } cia$r_pci_tb1_bits; } cia$r_pci_tb1_overlay;% unsigned char cia$b_fill540 [60];N/* i */N/* PCI TB Tag 2 - 0x8760000980 */N/* */ __union { int cia$l_pci_tb2; __struct {N unsigned cia$v_tb2_valid : 1; /* */N unsigned cia$v_tb2_reserved : 1; /* */N unsigned cia$v_tb2_dac : 1; /* enable 64BIT PCI */N unsi j gned cia$v_tb2_reserved2 : 12; /* */( unsigned cia$v_tb2_tag : 17;! } cia$r_pci_tb2_bits; } cia$r_pci_tb2_overlay;% unsigned char cia$b_fill550 [60];N/* */N/* PCI TB Tag 3- 0x87600009C0 */N/* */ __union { int cia$l_pci_tb3; k __struct {N unsigned cia$v_tb3_valid : 1; /* */N unsigned cia$v_tb3_reserved : 1; /* */N unsigned cia$v_tb3_dac : 1; /* enable 64BIT PCI */N unsigned cia$v_tb3_reserved2 : 12; /* */( unsigned cia$v_tb3_tag : 17;! } cia$r_pci_tb3_bits; } cia$r_pci_tb3_overlay;' unsigned char cia$b_fill560 [1596];N/* l */N/* PCI TB0 Page 0- 0x8760001000 */N/* */ __union { int cia$l_pci_tb0_page0; __struct {N unsigned cia$v_tb0_page0_valid : 1; /* *// unsigned cia$v_tb0_page0_addr : 21;N unsigned cia$v_fill : 10; /* */' m } cia$r_pci_tb0_page0_bits;& } cia$r_pci_tb0_page0_overlay;% unsigned char cia$b_fill570 [60];N/* */N/* PCI TB0 Page 1 - 0x8760001040 */N/* */ __union { int cia$l_pci_tb0_page1; __struct {N unsigned cia$v_tb0_page1_valid : 1; /* n *// unsigned cia$v_tb0_page1_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb0_page1_bits;& } cia$r_pci_tb0_page1_overlay;% unsigned char cia$b_fill580 [60];N/* */N/* PCI TB0 Page 2 - 0x8760001080 */N/* */ __ o union { int cia$l_pci_tb0_page2; __struct {N unsigned cia$v_tb0_page2_valid : 1; /* *// unsigned cia$v_tb0_page2_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb0_page2_bits;& } cia$r_pci_tb0_page2_overlay;% unsigned char cia$b_fill590 [60];N/* */N/* PCI TB0 Page 3- 0x8760001 p 0C0 */N/* */ __union { int cia$l_pci_tb0_page3; __struct {N unsigned cia$v_tb0_page3_valid : 1; /* *// unsigned cia$v_tb0_page3_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb0_page3_bits;& } cia$r_pci_tb0_page3_overlay;% unsign q ed char cia$b_fill600 [60];N/* */N/* PCI TB1 Page 0- 0x8760001100 */N/* */ __union { int cia$l_pci_tb1_page0; __struct {N unsigned cia$v_tb1_page0_valid : 1; /* *// unsigned cia$v_tb1_page0_addr : 21;N unsigned cia$v_fill : r 10; /* */' } cia$r_pci_tb1_page0_bits;& } cia$r_pci_tb1_page0_overlay;% unsigned char cia$b_fill610 [60];N/* */N/* PCI TB1 Page 1 - 0x8760001140 */N/* */ __union { int cia$l_pci_tb1_page1; __struct {N unsigned cia$v s _tb1_page1_valid : 1; /* *// unsigned cia$v_tb1_page1_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb1_page1_bits;& } cia$r_pci_tb1_page1_overlay;% unsigned char cia$b_fill620 [60];N/* */N/* PCI TB1 Page 2 - 0x8760001180 */N/* t */ __union { int cia$l_pci_tb1_page2; __struct {N unsigned cia$v_tb1_page2_valid : 1; /* *// unsigned cia$v_tb1_page2_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb1_page2_bits;& } cia$r_pci_tb1_page2_overlay;% unsigned char cia$b_fill630 [60];N/* u */N/* PCI TB1 Page 3- 0x87600011C0 */N/* */ __union { int cia$l_pci_tb1_page3; __struct {N unsigned cia$v_tb1_page3_valid : 1; /* *// unsigned cia$v_tb1_page3_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb1_page3_bits;& v } cia$r_pci_tb1_page3_overlay;% unsigned char cia$b_fill640 [60];N/* */N/* PCI TB2 Page 0- 0x8760001200 */N/* */ __union { int cia$l_pci_tb2_page0; __struct {N unsigned cia$v_tb2_page0_valid : 1; /* *// unsigned cia$v_tb2_page0_a w ddr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb2_page0_bits;& } cia$r_pci_tb2_page0_overlay;% unsigned char cia$b_fill650 [60];N/* */N/* PCI TB2 Page 1 - 0x8760001240 */N/* */ __union { int cia$l_pci_tb2_page1; x __struct {N unsigned cia$v_tb2_page1_valid : 1; /* *// unsigned cia$v_tb2_page1_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb2_page1_bits;& } cia$r_pci_tb2_page1_overlay;% unsigned char cia$b_fill660 [60];N/* */N/* PCI TB2 Page 2 - 0x8760001280 y */N/* */ __union { int cia$l_pci_tb2_page2; __struct {N unsigned cia$v_tb2_page2_valid : 1; /* *// unsigned cia$v_tb2_page2_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb2_page2_bits;& } cia$r_pci_tb2_page2_overlay;% unsigned char cia$b_fill670 [60];N/* z */N/* PCI TB2 Page 3- 0x87600012C0 */N/* */ __union { int cia$l_pci_tb2_page3; __struct {N unsigned cia$v_tb2_page3_valid : 1; /* *// unsigned cia$v_tb2_page3_addr : 21;N unsigned cia$v_fill : 10; /* */' { } cia$r_pci_tb2_page3_bits;& } cia$r_pci_tb2_page3_overlay;% unsigned char cia$b_fill680 [60];N/* */N/* PCI TB3 Page 0- 0x8760001300 */N/* */ __union { int cia$l_pci_tb3_page0; __struct {N unsigned cia$v_tb3_page0_valid : 1; /* | *// unsigned cia$v_tb3_page0_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb3_page0_bits;& } cia$r_pci_tb3_page0_overlay;% unsigned char cia$b_fill690 [60];N/* */N/* PCI TB3 Page 1 - 0x8760001340 */N/* */ __ } union { int cia$l_pci_tb3_page1; __struct {N unsigned cia$v_tb3_page1_valid : 1; /* *// unsigned cia$v_tb3_page1_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb3_page1_bits;& } cia$r_pci_tb3_page1_overlay;% unsigned char cia$b_fill700 [60];N/* */N/* PCI TB3 Page 2 - 0x876000 ~ 1380 */N/* */ __union { int cia$l_pci_tb3_page2; __struct {N unsigned cia$v_tb3_page2_valid : 1; /* *// unsigned cia$v_tb3_page2_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb3_page2_bits;& } cia$r_pci_tb3_page2_overlay;% unsign  ed char cia$b_fill710 [60];N/* */N/* PCI TB3 Page 3- 0x87600013C0 */N/* */ __union { int cia$l_pci_tb3_page3; __struct {N unsigned cia$v_tb3_page3_valid : 1; /* *// unsigned cia$v_tb3_page3_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb3_page3_bits;& } cia$r_pci_tb3_page3_overlay;% unsigned char cia$b_fill720 [60];N/* */N/* PCI TB4 Page 0- 0x8760001400 */N/* */ __union { int cia$l_pci_tb4_page0; __struct {N unsigned cia$v _tb4_page0_valid : 1; /* *// unsigned cia$v_tb4_page0_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb4_page0_bits;& } cia$r_pci_tb4_page0_overlay;% unsigned char cia$b_fill730 [60];N/* */N/* PCI TB4 Page 1 - 0x8760001440 */N/* */ __union { int cia$l_pci_tb4_page1; __struct {N unsigned cia$v_tb4_page1_valid : 1; /* *// unsigned cia$v_tb4_page1_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb4_page1_bits;& } cia$r_pci_tb4_page1_overlay;% unsigned char cia$b_fill740 [60];N/* */N/* PCI TB4 Page 2 - 0x8760001480 */N/* */ __union { int cia$l_pci_tb4_page2; __struct {N unsigned cia$v_tb4_page2_valid : 1; /* *// unsigned cia$v_tb4_page2_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb4_page2_bits;& } cia$r_pci_tb4_page2_overlay;% unsigned char cia$b_fill750 [60];N/* */N/* PCI TB4 Page 3- 0x87600014C0 */N/* */ __union { int cia$l_pci_tb4_page3; __struct {N unsigned cia$v_tb4_page3_valid : 1; /* *// unsigned cia$v_tb4_page3_a ddr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb4_page3_bits;& } cia$r_pci_tb4_page3_overlay;% unsigned char cia$b_fill760 [60];N/* */N/* PCI TB5 Page 0- 0x8760001500 */N/* */ __union { int cia$l_pci_tb5_page0; __struct {N unsigned cia$v_tb5_page0_valid : 1; /* *// unsigned cia$v_tb5_page0_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb5_page0_bits;& } cia$r_pci_tb5_page0_overlay;% unsigned char cia$b_fill770 [60];N/* */N/* PCI TB5 Page 1 - 0x8760001540 */N/* */ __union { int cia$l_pci_tb5_page1; __struct {N unsigned cia$v_tb5_page1_valid : 1; /* *// unsigned cia$v_tb5_page1_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb5_page1_bits;& } cia$r_pci_tb5_page1_overlay;% unsigned char cia$b_fill780 [60];N/* */N/* PCI TB5 Page 2 - 0x8760001580 */N/* */ __union { int cia$l_pci_tb5_page2; __struct {N unsigned cia$v_tb5_page2_valid : 1; /* *// unsigned cia$v_tb5_page2_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb5_page2_bits;& } cia$r_pci_tb5_page2_overlay;% unsigned char cia$b_fill790 [60];N/* */N/* PCI TB5 Page 3- 0x87600015C0 */N/* */ __union { int cia$l_pci_tb5_page3; __struct {N unsigned cia$v_tb5_page3_valid : 1; /* *// unsigned cia$v_tb5_page3_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb5_page3_bits;& } cia$r_pci_tb5_page3_overlay;% unsigned char cia$b_fill800 [60];N/* */N/* PCI TB6 Page 0- 0x8760001600 */N/* */ __ union { int cia$l_pci_tb6_page0; __struct {N unsigned cia$v_tb6_page0_valid : 1; /* *// unsigned cia$v_tb6_page0_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb6_page0_bits;& } cia$r_pci_tb6_page0_overlay;% unsigned char cia$b_fill810 [60];N/* */N/* PCI TB6 Page 1 - 0x876000 1640 */N/* */ __union { int cia$l_pci_tb6_page1; __struct {N unsigned cia$v_tb6_page1_valid : 1; /* *// unsigned cia$v_tb6_page1_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb6_page1_bits;& } cia$r_pci_tb6_page1_overlay;% unsign ed char cia$b_fill820 [60];N/* */N/* PCI TB6 Page 2 - 0x8760001680 */N/* */ __union { int cia$l_pci_tb6_page2; __struct {N unsigned cia$v_tb6_page2_valid : 1; /* *// unsigned cia$v_tb6_page2_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb6_page2_bits;& } cia$r_pci_tb6_page2_overlay;% unsigned char cia$b_fill830 [60];N/* */N/* PCI TB6 Page 3- 0x87600016C0 */N/* */ __union { int cia$l_pci_tb6_page3; __struct {N unsigned cia$v _tb6_page3_valid : 1; /* *// unsigned cia$v_tb6_page3_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb6_page3_bits;& } cia$r_pci_tb6_page3_overlay;% unsigned char cia$b_fill840 [60];N/* */N/* PCI TB7 Page 0- 0x8760001700 */N/* */ __union { int cia$l_pci_tb7_page0; __struct {N unsigned cia$v_tb7_page0_valid : 1; /* *// unsigned cia$v_tb7_page0_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb7_page0_bits;& } cia$r_pci_tb7_page0_overlay;% unsigned char cia$b_fill850 [60];N/* */N/* PCI TB7 Page 1 - 0x8760001740 */N/* */ __union { int cia$l_pci_tb7_page1; __struct {N unsigned cia$v_tb7_page1_valid : 1; /* *// unsigned cia$v_tb7_page1_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb7_page1_bits;& } cia$r_pci_tb7_page1_overlay;% unsigned char cia$b_fill860 [60];N/* */N/* PCI TB7 Page 2 - 0x8760001780 */N/* */ __union { int cia$l_pci_tb7_page2; __struct {N unsigned cia$v_tb7_page2_valid : 1; /* *// unsigned cia$v_tb7_page2_a ddr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb7_page2_bits;& } cia$r_pci_tb7_page2_overlay;% unsigned char cia$b_fill870 [60];N/* */N/* PCI TB7 Page 3- 0x87600017C0 */N/* */ __union { int cia$l_pci_tb7_page3; __struct {N unsigned cia$v_tb7_page3_valid : 1; /* *// unsigned cia$v_tb7_page3_addr : 21;N unsigned cia$v_fill : 10; /* */' } cia$r_pci_tb7_page3_bits;& } cia$r_pci_tb7_page3_overlay;' unsigned char cia$b_fill880 [2108]; } CIA; #if !defined(__VAXC)B#define cia$l_pci_cia_rev cia$r_pci_cia_revision.cia$l_pci_cia_revI#define cia$b_cia_rev cia$r_pci_cia_revision.c ia$r_rev_bits.cia$b_cia_rev5#define cia$l_pci_lat cia$r_pci_latency.cia$l_pci_latP#define cia$b_pci_latency cia$r_pci_latency.cia$r_latency_bits.cia$b_pci_latency5#define cia$l_cia_ctl cia$r_cia_control.cia$l_cia_ctl\#define cia$v_cia_ctrl_pci_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_pci_enf#define cia$v_cia_ctrl_pci_lock_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_pci_lock_enf#define cia$v_cia_ctrl_pci_loop_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_ci a_ctrl_pci_loop_enb#define cia$v_cia_ctrl_fst_bb_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_fst_bb_en\#define cia$v_cia_ctrl_mst_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_mst_en\#define cia$v_cia_ctrl_mem_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_mem_en`#define cia$v_cia_ctrl_req64_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_req64_en`#define cia$v_cia_ctrl_ack64_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_ack64_end#d efine cia$v_cia_ctrl_addr_pe_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_addr_pe_en^#define cia$v_cia_ctrl_perr_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_perr_enf#define cia$v_cia_ctrl_fill_err_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_fill_err_end#define cia$v_cia_ctrl_ecc_chk_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_ecc_chk_end#define cia$v_cia_ctrl_cack_en_pe cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_cack_en_pef#d efine cia$v_cia_ctrl_con_idle_bc cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_con_idle_bcf#define cia$v_cia_ctrl_csr_ioa_byp cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_csr_ioa_byph#define cia$v_cia_ctrl_io_flush_req cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_io_flush_reqj#define cia$v_cia_ctrl_cpu_flush_req cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_cpu_flush_reqd#define cia$v_cia_ctrl_arb_ev5_en cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_c trl_arb_ev5_enf#define cia$v_cia_ctrl_en_arb_link cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_en_arb_link\#define cia$v_cia_ctrl_rd_typ cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_rd_typ\#define cia$v_cia_ctrl_rl_typ cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_rl_typ\#define cia$v_cia_ctrl_rm_typ cia$r_cia_control.cia$r_cia_control_bits.cia$v_cia_ctrl_rm_typB#define cia$l_cia_config cia$r_cia_config_overlay.cia$l_cia_configh#define cia$v_cia_cnfg_pci_width cia $r_cia_config_overlay.cia$r_cia_config_bits.cia$v_cia_cnfg_pci_widthh#define cia$v_cia_cnfg_iod_width cia$r_cia_config_overlay.cia$r_cia_config_bits.cia$v_cia_cnfg_iod_width9#define cia$l_hae_mem cia$r_hae_mem_overlay.cia$l_hae_memX#define cia$v_hae_mem_reg_3 cia$r_hae_mem_overlay.cia$r_hae_mem_bits.cia$v_hae_mem_reg_3X#define cia$v_hae_mem_reg_2 cia$r_hae_mem_overlay.cia$r_hae_mem_bits.cia$v_hae_mem_reg_2X#define cia$v_hae_mem_reg_1 cia$r_hae_mem_overlay.cia$r_hae_mem_bits.cia$v_hae_mem_reg_16 #define cia$l_hae_io cia$r_hae_io_overlay.cia$l_hae_ioH#define cia$v_hae_io cia$r_hae_io_overlay.cia$r_hae_io_bits.cia$v_hae_io-#define cia$l_cfg cia$r_cfg_overlay.cia$l_cfgN#define cia$v_cfg_bits cia$r_cfg_overlay.cia$r_cgf_bits_overlay.cia$v_cfg_bits9#define cia$l_cack_en cia$r_cack_en_overlay.cia$l_cack_enV#define cia$v_cack_en_bits cia$r_cack_en_overlay.cia$r_cack_en_bits.cia$v_cack_en_bits<#define cia$l_cia_diag cia$r_cia_diag_overlay.cia$l_cia_diagN#define cia$v_from_en cia$r_cia_diag_o verlay.cia$r_cia_diag_bits.cia$v_from_enR#define cia$v_use_check cia$r_cia_diag_overlay.cia$r_cia_diag_bits.cia$v_use_checkN#define cia$v_fpe_pci cia$r_cia_diag_overlay.cia$r_cia_diag_bits.cia$v_fpe_pciT#define cia$v_fpe_to_ev5 cia$r_cia_diag_overlay.cia$r_cia_diag_bits.cia$v_fpe_to_ev5B#define cia$l_diag_check cia$r_diag_check_overlay.cia$l_diag_check`#define cia$b_diag_check_ecc cia$r_diag_check_overlay.cia$r_diag_check_bits.cia$b_diag_check_eccH#define cia$l_perf_monitor cia$r_perf_monitor_ov erlay.cia$l_perf_monitorH#define cia$l_perf_control cia$r_perf_control_overlay.cia$l_perf_control<#define cia$l_cpu_err0 cia$r_cpu_err0_overlay.cia$l_cpu_err0Z#define cia$v_cpu_err0_addr cia$r_cpu_err0_overlay.cia$r_cpu_err0_bits.cia$v_cpu_err0_addr<#define cia$l_cpu_err1 cia$r_cpu_err1_overlay.cia$l_cpu_err1Z#define cia$v_cpu_err1_3432 cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_3432V#define cia$v_cpu_err1_39 cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_39X#define ci a$v_cpu_err1_cmd cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_cmdf#define cia$v_cpu_err1_int4_valid cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_int4_valid^#define cia$v_cpu_err1_ac_par cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_ac_parX#define cia$v_cpu_err1_fpe cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_fpeV#define cia$v_cpu_err1_pe cia$r_cpu_err1_overlay.cia$r_cpu_err1_bits.cia$v_cpu_err1_pe9#define cia$l_cia_err cia$r_cia_err_overlay.cia$ l_cia_errV#define cia$v_err_corr_ecc cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_corr_eccT#define cia$v_err_unc_ecc cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_unc_eccR#define cia$v_err_cpu_pe cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_cpu_peT#define cia$v_err_mem_nem cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_mem_nemV#define cia$v_err_pci_serr cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_pci_serrV#define cia$v_err_pci_perr cia$r_cia_err_overlay.cia$r_cia_err _bits.cia$v_err_pci_perrZ#define cia$v_err_pci_adr_pe cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_pci_adr_peT#define cia$v_err_m_abort cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_m_abortT#define cia$v_err_t_abort cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_t_abortZ#define cia$v_err_pa_pte_inv cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_pa_pte_inv^#define cia$v_err_from_wrt_err cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_from_wrt_err\#define cia$v_err_ioa_timeou t cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_ioa_timeout`#define cia$v_err_lost_corr_ecc cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_corr_ecc^#define cia$v_err_lost_unc_ecc cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_unc_ecc\#define cia$v_err_lost_cpu_pe cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_cpu_pe^#define cia$v_err_lost_mem_nem cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_mem_nem`#define cia$v_err_lost_pci_serr cia$r_cia_err_overlay.ci a$r_cia_err_bits.cia$v_err_lost_pci_serr`#define cia$v_err_lost_pci_perr cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_pci_perrd#define cia$v_err_lost_pci_adr_pe cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_pci_adr_pe^#define cia$v_err_lost_m_abort cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_m_abort^#define cia$v_err_lost_t_abort cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_t_abortd#define cia$v_err_lost_pa_pte_inv cia$r_cia_err_overlay.cia$r_cia_err_bi ts.cia$v_err_lost_pa_pte_invh#define cia$v_err_lost_from_wrt_err cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_from_wrt_errf#define cia$v_err_lost_ioa_timeout cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_lost_ioa_timeoutP#define cia$v_err_valid cia$r_cia_err_overlay.cia$r_cia_err_bits.cia$v_err_valid<#define cia$l_cia_stat cia$r_cia_stat_overlay.cia$l_cia_stat^#define cia$v_stat_pci_status cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_pci_status^#define cia$v_stat_mem_sou rce cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_mem_sourceZ#define cia$v_stat_io_queue cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_io_queue\#define cia$v_stat_cpu_queue cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_cpu_queueZ#define cia$v_stat_tlb_miss cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_tlb_missX#define cia$v_stat_dm_stat cia$r_cia_stat_overlay.cia$r_cia_stat_bits.cia$v_stat_dm_stat^#define cia$v_stat_pa_cpu_res cia$r_cia_stat_overlay.cia$r_cia_stat_ bits.cia$v_stat_pa_cpu_resN#define cia$l_cia_error_mask cia$r_cia_error_mask_overlay.cia$l_cia_error_maskn#define cia$v_mask_corr_ecc_err cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_corr_ecc_errl#define cia$v_mask_unc_ecc_err cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_unc_ecc_errb#define cia$v_mask_cpu_pe cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_cpu_ped#define cia$v_mask_mem_nem cia$r_cia_error_mask_overlay.cia$r_cia_error_mask _bits.cia$v_mask_mem_nemf#define cia$v_mask_pci_serr cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_pci_serrf#define cia$v_mask_pci_perr cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_pci_perrj#define cia$v_mask_pci_adr_pe cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_pci_adr_ped#define cia$v_mask_m_abort cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_m_abortd#define cia$v_mask_t_abort cia$r_cia_error_mask_overlay.cia$r_ cia_error_mask_bits.cia$v_mask_t_abortj#define cia$v_mask_pa_pte_inv cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_pa_pte_invn#define cia$v_mask_from_wrt_err cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_from_wrt_errl#define cia$v_mask_ioa_timeout cia$r_cia_error_mask_overlay.cia$r_cia_error_mask_bits.cia$v_mask_ioa_timeout8#define cia$l_cia_synd cia$r_cia_syndrome.cia$l_cia_syndB#define cia$r_cia_synd_bits cia$r_cia_syndrome.cia$r_cia_synd_bitsA#define ci a$v_cia_syndrome cia$r_cia_synd_bits.cia$v_cia_syndrome?#define cia$l_cia_mpsr0 cia$r_cia_mpsr0_overlay.cia$l_cia_mpsr0Z#define cia$v_mpsr0_addr_h cia$r_cia_mpsr0_overlay.cia$r_cia_mpsr0_bits.cia$v_mpsr0_addr_h?#define cia$l_cia_mpsr1 cia$r_cia_mpsr1_overlay.cia$l_cia_mpsr1Z#define cia$v_mpsr1_addr_h cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_addr_h\#define cia$v_mpsr1_addr_39 cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_addr_39X#define cia$v_mpsr1_cmd_h cia$r_cia_mp sr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_cmd_h`#define cia$v_mpsr1_port_mask cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_port_maskZ#define cia$v_mpsr1_seq_st cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_seq_st^#define cia$v_mpsr1_port_src cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_port_src\#define cia$v_mpsr1_set_sel cia$r_cia_mpsr1_overlay.cia$r_cia_mpsr1_bits.cia$v_mpsr1_set_sel?#define cia$l_cia_pcie0 cia$r_cia_pcie0_overlay.cia$l_cia_pcie0Q#define  cia$v_pcie_cmd cia$r_cia_pcie0_overlay.cia$r_cia_pcie_bits.cia$v_pcie_cmd_#define cia$v_pcie_lock_state cia$r_cia_pcie0_overlay.cia$r_cia_pcie_bits.cia$v_pcie_lock_state]#define cia$v_pcie_dac_cycle cia$r_cia_pcie0_overlay.cia$r_cia_pcie_bits.cia$v_pcie_dac_cycleW#define cia$v_pcie_window cia$r_cia_pcie0_overlay.cia$r_cia_pcie_bits.cia$v_pcie_window_#define cia$v_pcie_mstr_state cia$r_cia_pcie0_overlay.cia$r_cia_pcie_bits.cia$v_pcie_mstr_state_#define cia$v_pcie_trgt_state cia$r_cia_pcie0_ov erlay.cia$r_cia_pcie_bits.cia$v_pcie_trgt_stateM#define cia$l_pcie1_mem_addr_h cia$r_cia_pcie1_overlay.cia$l_pcie1_mem_addr_h9#define cia$l_mem_mcr cia$r_mem_mcr_overlay.cia$l_mem_mcrV#define cia$v_mcr_mem_size cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_mem_sizeZ#define cia$v_mcr_cache_size cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_cache_sizeV#define cia$v_mcr_ref_rate cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_ref_rateX#define cia$v_mcr_ref_burst cia$r_mem_mcr_overla y.cia$r_mem_mcr_bits.cia$v_mcr_ref_burstR#define cia$v_mcr_tmg_r0 cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_tmg_r0^#define cia$v_mcr_long_cbr_cas cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_long_cbr_cas\#define cia$v_mcr_dly_idle_bc cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_dly_idle_bc`#define cia$v_mcr_early_idle_bc cia$r_mem_mcr_overlay.cia$r_mem_mcr_bits.cia$v_mcr_early_idle_bc<#define cia$l_mem_mba0 cia$r_mem_mba0_overlay.cia$l_mem_mba0Z#define cia$v_mba0_s0_valid ci a$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_s0_validZ#define cia$v_mba0_row_type cia$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_row_typeR#define cia$v_mba0_mask cia$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_maskZ#define cia$v_mba0_s1_valid cia$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_s1_validX#define cia$v_mba0_pattern cia$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_patternV#define cia$v_mba0_timing cia$r_mem_mba0_overlay.cia$r_mem_mba0_bits.cia$v_mba0_timing <#define cia$l_mem_mba2 cia$r_mem_mba2_overlay.cia$l_mem_mba2Z#define cia$v_mba2_s0_valid cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_s0_validZ#define cia$v_mba2_row_type cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_row_typeR#define cia$v_mba2_mask cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_maskZ#define cia$v_mba2_s1_valid cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_s1_validX#define cia$v_mba2_pattern cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_p atternV#define cia$v_mba2_timing cia$r_mem_mba2_overlay.cia$r_mem_mba2_bits.cia$v_mba2_timing<#define cia$l_mem_mba4 cia$r_mem_mba4_overlay.cia$l_mem_mba4Z#define cia$v_mba4_s0_valid cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba4_s0_validZ#define cia$v_mba4_row_type cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba4_row_typeR#define cia$v_mba4_mask cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba4_maskZ#define cia$v_mba4_s1_valid cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba 4_s1_validX#define cia$v_mba4_pattern cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba4_patternV#define cia$v_mba4_timing cia$r_mem_mba4_overlay.cia$r_mem_mba4_bits.cia$v_mba4_timing<#define cia$l_mem_mba6 cia$r_mem_mba6_overlay.cia$l_mem_mba6Z#define cia$v_mba6_s0_valid cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia$v_mba6_s0_validZ#define cia$v_mba6_row_type cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia$v_mba6_row_typeR#define cia$v_mba6_mask cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia $v_mba6_maskZ#define cia$v_mba6_s1_valid cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia$v_mba6_s1_validX#define cia$v_mba6_pattern cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia$v_mba6_patternV#define cia$v_mba6_timing cia$r_mem_mba6_overlay.cia$r_mem_mba6_bits.cia$v_mba6_timing<#define cia$l_mem_mba8 cia$r_mem_mba8_overlay.cia$l_mem_mba8Z#define cia$v_mba8_s0_valid cia$r_mem_mba8_overlay.cia$r_mem_mba8_bits.cia$v_mba8_s0_validZ#define cia$v_mba8_row_type cia$r_mem_mba8_overlay.cia$r_mem_mba8_bi ts.cia$v_mba8_row_typeR#define cia$v_mba8_mask cia$r_mem_mba8_overlay.cia$r_mem_mba8_bits.cia$v_mba8_maskZ#define cia$v_mba8_s1_valid cia$r_mem_mba8_overlay.cia$r_mem_mba8_bits.cia$v_mba8_s1_validX#define cia$v_mba8_pattern cia$r_mem_mba8_overlay.cia$r_mem_mba8_bits.cia$v_mba8_patternV#define cia$v_mba8_timing cia$r_mem_mba8_overlay.cia$r_mem_mba8_bits.cia$v_mba8_timing<#define cia$l_mem_mbaa cia$r_mem_mbaa_overlay.cia$l_mem_mbaaZ#define cia$v_mbaa_s0_valid cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_ bits.cia$v_mbaa_s0_validZ#define cia$v_mbaa_row_type cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_bits.cia$v_mbaa_row_typeR#define cia$v_mbaa_mask cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_bits.cia$v_mbaa_maskZ#define cia$v_mbaa_s1_valid cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_bits.cia$v_mbaa_s1_validX#define cia$v_mbaa_pattern cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_bits.cia$v_mbaa_patternV#define cia$v_mbaa_timing cia$r_mem_mbaa_overlay.cia$r_mem_mbaa_bits.cia$v_mbaa_timing<#define cia$l_mem_mbac cia$r_mem_m bac_overlay.cia$l_mem_mbacZ#define cia$v_mbac_s0_valid cia$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_s0_validZ#define cia$v_mbac_row_type cia$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_row_typeR#define cia$v_mbac_mask cia$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_maskZ#define cia$v_mbac_s1_valid cia$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_s1_validX#define cia$v_mbac_pattern cia$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_patternV#define cia$v_mbac_timing ci a$r_mem_mbac_overlay.cia$r_mem_mbac_bits.cia$v_mbac_timing<#define cia$l_mem_mbae cia$r_mem_mbae_overlay.cia$l_mem_mbaeZ#define cia$v_mbae_s0_valid cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_s0_validZ#define cia$v_mbae_row_type cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_row_typeR#define cia$v_mbae_mask cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_maskZ#define cia$v_mbae_s1_valid cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_s1_validX#define cia$v_mbae_patte rn cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_pattern^#define cia$v_mbae_reserved_3 cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_reserved_3V#define cia$v_mbae_timing cia$r_mem_mbae_overlay.cia$r_mem_mbae_bits.cia$v_mbae_timing<#define cia$l_mem_tmg0 cia$r_mem_tmg0_overlay.cia$l_mem_tmg0N#define cia$v_tmg0_r1 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r1N#define cia$v_tmg0_r2 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r2N#define cia$v_tmg0_r3 cia$r_mem_tm g0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r3N#define cia$v_tmg0_r4 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r4N#define cia$v_tmg0_r5 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r5N#define cia$v_tmg0_r6 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_r6N#define cia$v_tmg0_w1 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_w1N#define cia$v_tmg0_w4 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_w4P#define cia$v_tmg0_pre cia$r_mem_tmg0_overlay.cia$r_mem_tmg0 _bits.cia$v_tmg0_preN#define cia$v_tmg0_v3 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_v3N#define cia$v_tmg0_v4 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_v4N#define cia$v_tmg0_v5 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_v5N#define cia$v_tmg0_v6 cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_v6N#define cia$v_tmg0_rv cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_rvV#define cia$v_tmg0_rd_dly cia$r_mem_tmg0_overlay.cia$r_mem_tmg0_bits.cia$v_tmg0_rd_d ly<#define cia$l_mem_tmg1 cia$r_mem_tmg1_overlay.cia$l_mem_tmg1N#define cia$v_tmg1_r1 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r1N#define cia$v_tmg1_r2 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r2N#define cia$v_tmg1_r3 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r3N#define cia$v_tmg1_r4 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r4N#define cia$v_tmg1_r5 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r5N#define cia$v_tmg1_r6 cia$r_mem_tmg1_ove rlay.cia$r_mem_tmg1_bits.cia$v_tmg1_r6N#define cia$v_tmg1_w1 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_w1N#define cia$v_tmg1_w4 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_w4P#define cia$v_tmg1_pre cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_preN#define cia$v_tmg1_v3 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_v3N#define cia$v_tmg1_v4 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_v4N#define cia$v_tmg1_v5 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits .cia$v_tmg1_v5N#define cia$v_tmg1_v6 cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_v6N#define cia$v_tmg1_rv cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_rvV#define cia$v_tmg1_rd_dly cia$r_mem_tmg1_overlay.cia$r_mem_tmg1_bits.cia$v_tmg1_rd_dly<#define cia$l_mem_tmg2 cia$r_mem_tmg2_overlay.cia$l_mem_tmg2N#define cia$v_tmg2_r1 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r1N#define cia$v_tmg2_r2 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r2N#define cia$v_tmg2_r 3 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r3N#define cia$v_tmg2_r4 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r4N#define cia$v_tmg2_r5 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r5N#define cia$v_tmg2_r6 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_r6N#define cia$v_tmg2_w1 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_w1N#define cia$v_tmg2_w4 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_w4P#define cia$v_tmg2_pre cia$r_mem_tmg2_overlay. cia$r_mem_tmg2_bits.cia$v_tmg2_preN#define cia$v_tmg2_v3 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_v3N#define cia$v_tmg2_v4 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_v4N#define cia$v_tmg2_v5 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_v5N#define cia$v_tmg2_v6 cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_v6N#define cia$v_tmg2_rv cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.cia$v_tmg2_rvV#define cia$v_tmg2_rd_dly cia$r_mem_tmg2_overlay.cia$r_mem_tmg2_bits.c ia$v_tmg2_rd_dly<#define cia$l_pci_tbia cia$r_pci_tbia_overlay.cia$l_pci_tbia`#define cia$v_tbia_csr_wr_data cia$r_pci_tbia_overlay.cia$r_pci_tbia_bits.cia$v_tbia_csr_wr_dataB#define cia$l_pci_wbase0 cia$r_pci_wbase0_overlay.cia$l_pci_wbase0Z#define cia$v_wbase0_w_en cia$r_pci_wbase0_overlay.cia$r_pci_wbase0_bits.cia$v_wbase0_w_en\#define cia$v_wbase0_sg_en cia$r_pci_wbase0_overlay.cia$r_pci_wbase0_bits.cia$v_wbase0_sg_enb#define cia$v_wbase0_memcs_en cia$r_pci_wbase0_overlay.cia$r_pci_wbase0_bi ts.cia$v_wbase0_memcs_en^#define cia$v_wbase0_dac_en cia$r_pci_wbase0_overlay.cia$r_pci_wbase0_bits.cia$v_wbase0_dac_enZ#define cia$v_wbase0_base cia$r_pci_wbase0_overlay.cia$r_pci_wbase0_bits.cia$v_wbase0_baseB#define cia$l_pci_wmask0 cia$r_pci_wmask0_overlay.cia$l_pci_wmask0Z#define cia$v_wmask0_mask cia$r_pci_wmask0_overlay.cia$r_pci_wmask0_bits.cia$v_wmask0_maskB#define cia$l_pci_tbase0 cia$r_pci_tbase0_overlay.cia$l_pci_tbase0Z#define cia$v_tbase0_base cia$r_pci_tbase0_overlay.cia$r_pci_tba se0_bits.cia$v_tbase0_baseB#define cia$l_pci_wbase1 cia$r_pci_wbase1_overlay.cia$l_pci_wbase1Z#define cia$v_wbase1_w_en cia$r_pci_wbase1_overlay.cia$r_pci_wbase1_bits.cia$v_wbase1_w_en\#define cia$v_wbase1_sg_en cia$r_pci_wbase1_overlay.cia$r_pci_wbase1_bits.cia$v_wbase1_sg_enb#define cia$v_wbase1_memcs_en cia$r_pci_wbase1_overlay.cia$r_pci_wbase1_bits.cia$v_wbase1_memcs_en^#define cia$v_wbase1_dac_en cia$r_pci_wbase1_overlay.cia$r_pci_wbase1_bits.cia$v_wbase1_dac_enZ#define cia$v_wbase1_base ci a$r_pci_wbase1_overlay.cia$r_pci_wbase1_bits.cia$v_wbase1_baseB#define cia$l_pci_wmask1 cia$r_pci_wmask1_overlay.cia$l_pci_wmask1Z#define cia$v_wmask1_mask cia$r_pci_wmask1_overlay.cia$r_pci_wmask1_bits.cia$v_wmask1_maskB#define cia$l_pci_tbase1 cia$r_pci_tbase1_overlay.cia$l_pci_tbase1Z#define cia$v_tbase1_base cia$r_pci_tbase1_overlay.cia$r_pci_tbase1_bits.cia$v_tbase1_baseB#define cia$l_pci_wbase2 cia$r_pci_wbase2_overlay.cia$l_pci_wbase2Z#define cia$v_wbase2_w_en cia$r_pci_wbase2_overlay.cia $r_pci_wbase2_bits.cia$v_wbase2_w_en\#define cia$v_wbase2_sg_en cia$r_pci_wbase2_overlay.cia$r_pci_wbase2_bits.cia$v_wbase2_sg_enb#define cia$v_wbase2_memcs_en cia$r_pci_wbase2_overlay.cia$r_pci_wbase2_bits.cia$v_wbase2_memcs_en^#define cia$v_wbase2_dac_en cia$r_pci_wbase2_overlay.cia$r_pci_wbase2_bits.cia$v_wbase2_dac_enZ#define cia$v_wbase2_base cia$r_pci_wbase2_overlay.cia$r_pci_wbase2_bits.cia$v_wbase2_baseB#define cia$l_pci_wmask2 cia$r_pci_wmask2_overlay.cia$l_pci_wmask2Z#define cia$v_wmas k2_mask cia$r_pci_wmask2_overlay.cia$r_pci_wmask2_bits.cia$v_wmask2_maskB#define cia$l_pci_tbase2 cia$r_pci_tbase2_overlay.cia$l_pci_tbase2Z#define cia$v_tbase2_base cia$r_pci_tbase2_overlay.cia$r_pci_tbase2_bits.cia$v_tbase2_baseB#define cia$l_pci_wbase3 cia$r_pci_wbase3_overlay.cia$l_pci_wbase3Z#define cia$v_wbase3_w_en cia$r_pci_wbase3_overlay.cia$r_pci_wbase3_bits.cia$v_wbase3_w_en\#define cia$v_wbase3_sg_en cia$r_pci_wbase3_overlay.cia$r_pci_wbase3_bits.cia$v_wbase3_sg_enb#define cia$v_wbas e3_memcs_en cia$r_pci_wbase3_overlay.cia$r_pci_wbase3_bits.cia$v_wbase3_memcs_en^#define cia$v_wbase3_dac_en cia$r_pci_wbase3_overlay.cia$r_pci_wbase3_bits.cia$v_wbase3_dac_enZ#define cia$v_wbase3_base cia$r_pci_wbase3_overlay.cia$r_pci_wbase3_bits.cia$v_wbase3_baseB#define cia$l_pci_wmask3 cia$r_pci_wmask3_overlay.cia$l_pci_wmask3Z#define cia$v_wmask3_mask cia$r_pci_wmask3_overlay.cia$r_pci_wmask3_bits.cia$v_wmask3_maskB#define cia$l_pci_tbase3 cia$r_pci_tbase3_overlay.cia$l_pci_tbase3Z#define  cia$v_tbase3_base cia$r_pci_tbase3_overlay.cia$r_pci_tbase3_bits.cia$v_tbase3_base9#define cia$l_pci_dac cia$r_pci_dac_overlay.cia$l_pci_dacN#define cia$v_dac_base cia$r_pci_dac_overlay.cia$r_pci_dac_bits.cia$v_dac_base<#define cia$l_pci_ltb0 cia$r_pci_ltb0_overlay.cia$l_pci_ltb0T#define cia$v_ltb0_valid cia$r_pci_ltb0_overlay.cia$r_pci_ltb0_bits.cia$v_ltb0_validV#define cia$v_ltb0_locked cia$r_pci_ltb0_overlay.cia$r_pci_ltb0_bits.cia$v_ltb0_lockedP#define cia$v_ltb0_dac cia$r_pci_ltb0_overlay. cia$r_pci_ltb0_bits.cia$v_ltb0_dacP#define cia$v_ltb0_tag cia$r_pci_ltb0_overlay.cia$r_pci_ltb0_bits.cia$v_ltb0_tag<#define cia$l_pci_ltb1 cia$r_pci_ltb1_overlay.cia$l_pci_ltb1T#define cia$v_ltb1_valid cia$r_pci_ltb1_overlay.cia$r_pci_ltb1_bits.cia$v_ltb1_validV#define cia$v_ltb1_locked cia$r_pci_ltb1_overlay.cia$r_pci_ltb1_bits.cia$v_ltb1_lockedP#define cia$v_ltb1_dac cia$r_pci_ltb1_overlay.cia$r_pci_ltb1_bits.cia$v_ltb1_dacP#define cia$v_ltb1_tag cia$r_pci_ltb1_overlay.cia$r_pci_ltb1_bits.cia$ v_ltb1_tag<#define cia$l_pci_ltb2 cia$r_pci_ltb2_overlay.cia$l_pci_ltb2T#define cia$v_ltb2_valid cia$r_pci_ltb2_overlay.cia$r_pci_ltb2_bits.cia$v_ltb2_validV#define cia$v_ltb2_locked cia$r_pci_ltb2_overlay.cia$r_pci_ltb2_bits.cia$v_ltb2_lockedP#define cia$v_ltb2_dac cia$r_pci_ltb2_overlay.cia$r_pci_ltb2_bits.cia$v_ltb2_dacP#define cia$v_ltb2_tag cia$r_pci_ltb2_overlay.cia$r_pci_ltb2_bits.cia$v_ltb2_tag<#define cia$l_pci_ltb3 cia$r_pci_ltb3_overlay.cia$l_pci_ltb3T#define cia$v_ltb3_valid cia$r_p ci_ltb3_overlay.cia$r_pci_ltb3_bits.cia$v_ltb3_validV#define cia$v_ltb3_locked cia$r_pci_ltb3_overlay.cia$r_pci_ltb3_bits.cia$v_ltb3_lockedP#define cia$v_ltb3_dac cia$r_pci_ltb3_overlay.cia$r_pci_ltb3_bits.cia$v_ltb3_dacP#define cia$v_ltb3_tag cia$r_pci_ltb3_overlay.cia$r_pci_ltb3_bits.cia$v_ltb3_tag9#define cia$l_pci_tb0 cia$r_pci_tb0_overlay.cia$l_pci_tb0P#define cia$v_tb0_valid cia$r_pci_tb0_overlay.cia$r_pci_tb0_bits.cia$v_tb0_validL#define cia$v_tb0_dac cia$r_pci_tb0_overlay.cia$r_pci_tb0_ bits.cia$v_tb0_dacL#define cia$v_tb0_tag cia$r_pci_tb0_overlay.cia$r_pci_tb0_bits.cia$v_tb0_tag9#define cia$l_pci_tb1 cia$r_pci_tb1_overlay.cia$l_pci_tb1P#define cia$v_tb1_valid cia$r_pci_tb1_overlay.cia$r_pci_tb1_bits.cia$v_tb1_validL#define cia$v_tb1_dac cia$r_pci_tb1_overlay.cia$r_pci_tb1_bits.cia$v_tb1_dacL#define cia$v_tb1_tag cia$r_pci_tb1_overlay.cia$r_pci_tb1_bits.cia$v_tb1_tag9#define cia$l_pci_tb2 cia$r_pci_tb2_overlay.cia$l_pci_tb2P#define cia$v_tb2_valid cia$r_pci_tb2_overlay.cia$ r_pci_tb2_bits.cia$v_tb2_validL#define cia$v_tb2_dac cia$r_pci_tb2_overlay.cia$r_pci_tb2_bits.cia$v_tb2_dacL#define cia$v_tb2_tag cia$r_pci_tb2_overlay.cia$r_pci_tb2_bits.cia$v_tb2_tag9#define cia$l_pci_tb3 cia$r_pci_tb3_overlay.cia$l_pci_tb3P#define cia$v_tb3_valid cia$r_pci_tb3_overlay.cia$r_pci_tb3_bits.cia$v_tb3_validL#define cia$v_tb3_dac cia$r_pci_tb3_overlay.cia$r_pci_tb3_bits.cia$v_tb3_dacL#define cia$v_tb3_tag cia$r_pci_tb3_overlay.cia$r_pci_tb3_bits.cia$v_tb3_tagK#define cia$l_pci_tb 0_page0 cia$r_pci_tb0_page0_overlay.cia$l_pci_tb0_page0h#define cia$v_tb0_page0_valid cia$r_pci_tb0_page0_overlay.cia$r_pci_tb0_page0_bits.cia$v_tb0_page0_validf#define cia$v_tb0_page0_addr cia$r_pci_tb0_page0_overlay.cia$r_pci_tb0_page0_bits.cia$v_tb0_page0_addrK#define cia$l_pci_tb0_page1 cia$r_pci_tb0_page1_overlay.cia$l_pci_tb0_page1h#define cia$v_tb0_page1_valid cia$r_pci_tb0_page1_overlay.cia$r_pci_tb0_page1_bits.cia$v_tb0_page1_validf#define cia$v_tb0_page1_addr cia$r_pci_tb0_page1_overl ay.cia$r_pci_tb0_page1_bits.cia$v_tb0_page1_addrK#define cia$l_pci_tb0_page2 cia$r_pci_tb0_page2_overlay.cia$l_pci_tb0_page2h#define cia$v_tb0_page2_valid cia$r_pci_tb0_page2_overlay.cia$r_pci_tb0_page2_bits.cia$v_tb0_page2_validf#define cia$v_tb0_page2_addr cia$r_pci_tb0_page2_overlay.cia$r_pci_tb0_page2_bits.cia$v_tb0_page2_addrK#define cia$l_pci_tb0_page3 cia$r_pci_tb0_page3_overlay.cia$l_pci_tb0_page3h#define cia$v_tb0_page3_valid cia$r_pci_tb0_page3_overlay.cia$r_pci_tb0_page3_bits.cia$v_t b0_page3_validf#define cia$v_tb0_page3_addr cia$r_pci_tb0_page3_overlay.cia$r_pci_tb0_page3_bits.cia$v_tb0_page3_addrK#define cia$l_pci_tb1_page0 cia$r_pci_tb1_page0_overlay.cia$l_pci_tb1_page0h#define cia$v_tb1_page0_valid cia$r_pci_tb1_page0_overlay.cia$r_pci_tb1_page0_bits.cia$v_tb1_page0_validf#define cia$v_tb1_page0_addr cia$r_pci_tb1_page0_overlay.cia$r_pci_tb1_page0_bits.cia$v_tb1_page0_addrK#define cia$l_pci_tb1_page1 cia$r_pci_tb1_page1_overlay.cia$l_pci_tb1_page1h#define cia$v_tb1_pa ge1_valid cia$r_pci_tb1_page1_overlay.cia$r_pci_tb1_page1_bits.cia$v_tb1_page1_validf#define cia$v_tb1_page1_addr cia$r_pci_tb1_page1_overlay.cia$r_pci_tb1_page1_bits.cia$v_tb1_page1_addrK#define cia$l_pci_tb1_page2 cia$r_pci_tb1_page2_overlay.cia$l_pci_tb1_page2h#define cia$v_tb1_page2_valid cia$r_pci_tb1_page2_overlay.cia$r_pci_tb1_page2_bits.cia$v_tb1_page2_validf#define cia$v_tb1_page2_addr cia$r_pci_tb1_page2_overlay.cia$r_pci_tb1_page2_bits.cia$v_tb1_page2_addrK#define cia$l_pci_tb1_page3  cia$r_pci_tb1_page3_overlay.cia$l_pci_tb1_page3h#define cia$v_tb1_page3_valid cia$r_pci_tb1_page3_overlay.cia$r_pci_tb1_page3_bits.cia$v_tb1_page3_validf#define cia$v_tb1_page3_addr cia$r_pci_tb1_page3_overlay.cia$r_pci_tb1_page3_bits.cia$v_tb1_page3_addrK#define cia$l_pci_tb2_page0 cia$r_pci_tb2_page0_overlay.cia$l_pci_tb2_page0h#define cia$v_tb2_page0_valid cia$r_pci_tb2_page0_overlay.cia$r_pci_tb2_page0_bits.cia$v_tb2_page0_validf#define cia$v_tb2_page0_addr cia$r_pci_tb2_page0_overlay.cia$r _pci_tb2_page0_bits.cia$v_tb2_page0_addrK#define cia$l_pci_tb2_page1 cia$r_pci_tb2_page1_overlay.cia$l_pci_tb2_page1h#define cia$v_tb2_page1_valid cia$r_pci_tb2_page1_overlay.cia$r_pci_tb2_page1_bits.cia$v_tb2_page1_validf#define cia$v_tb2_page1_addr cia$r_pci_tb2_page1_overlay.cia$r_pci_tb2_page1_bits.cia$v_tb2_page1_addrK#define cia$l_pci_tb2_page2 cia$r_pci_tb2_page2_overlay.cia$l_pci_tb2_page2h#define cia$v_tb2_page2_valid cia$r_pci_tb2_page2_overlay.cia$r_pci_tb2_page2_bits.cia$v_tb2_page2 _validf#define cia$v_tb2_page2_addr cia$r_pci_tb2_page2_overlay.cia$r_pci_tb2_page2_bits.cia$v_tb2_page2_addrK#define cia$l_pci_tb2_page3 cia$r_pci_tb2_page3_overlay.cia$l_pci_tb2_page3h#define cia$v_tb2_page3_valid cia$r_pci_tb2_page3_overlay.cia$r_pci_tb2_page3_bits.cia$v_tb2_page3_validf#define cia$v_tb2_page3_addr cia$r_pci_tb2_page3_overlay.cia$r_pci_tb2_page3_bits.cia$v_tb2_page3_addrK#define cia$l_pci_tb3_page0 cia$r_pci_tb3_page0_overlay.cia$l_pci_tb3_page0h#define cia$v_tb3_page0_vali d cia$r_pci_tb3_page0_overlay.cia$r_pci_tb3_page0_bits.cia$v_tb3_page0_validf#define cia$v_tb3_page0_addr cia$r_pci_tb3_page0_overlay.cia$r_pci_tb3_page0_bits.cia$v_tb3_page0_addrK#define cia$l_pci_tb3_page1 cia$r_pci_tb3_page1_overlay.cia$l_pci_tb3_page1h#define cia$v_tb3_page1_valid cia$r_pci_tb3_page1_overlay.cia$r_pci_tb3_page1_bits.cia$v_tb3_page1_validf#define cia$v_tb3_page1_addr cia$r_pci_tb3_page1_overlay.cia$r_pci_tb3_page1_bits.cia$v_tb3_page1_addrK#define cia$l_pci_tb3_page2 cia$r_pc i_tb3_page2_overlay.cia$l_pci_tb3_page2h#define cia$v_tb3_page2_valid cia$r_pci_tb3_page2_overlay.cia$r_pci_tb3_page2_bits.cia$v_tb3_page2_validf#define cia$v_tb3_page2_addr cia$r_pci_tb3_page2_overlay.cia$r_pci_tb3_page2_bits.cia$v_tb3_page2_addrK#define cia$l_pci_tb3_page3 cia$r_pci_tb3_page3_overlay.cia$l_pci_tb3_page3h#define cia$v_tb3_page3_valid cia$r_pci_tb3_page3_overlay.cia$r_pci_tb3_page3_bits.cia$v_tb3_page3_validf#define cia$v_tb3_page3_addr cia$r_pci_tb3_page3_overlay.cia$r_pci_tb3 _page3_bits.cia$v_tb3_page3_addrK#define cia$l_pci_tb4_page0 cia$r_pci_tb4_page0_overlay.cia$l_pci_tb4_page0h#define cia$v_tb4_page0_valid cia$r_pci_tb4_page0_overlay.cia$r_pci_tb4_page0_bits.cia$v_tb4_page0_validf#define cia$v_tb4_page0_addr cia$r_pci_tb4_page0_overlay.cia$r_pci_tb4_page0_bits.cia$v_tb4_page0_addrK#define cia$l_pci_tb4_page1 cia$r_pci_tb4_page1_overlay.cia$l_pci_tb4_page1h#define cia$v_tb4_page1_valid cia$r_pci_tb4_page1_overlay.cia$r_pci_tb4_page1_bits.cia$v_tb4_page1_validf #define cia$v_tb4_page1_addr cia$r_pci_tb4_page1_overlay.cia$r_pci_tb4_page1_bits.cia$v_tb4_page1_addrK#define cia$l_pci_tb4_page2 cia$r_pci_tb4_page2_overlay.cia$l_pci_tb4_page2h#define cia$v_tb4_page2_valid cia$r_pci_tb4_page2_overlay.cia$r_pci_tb4_page2_bits.cia$v_tb4_page2_validf#define cia$v_tb4_page2_addr cia$r_pci_tb4_page2_overlay.cia$r_pci_tb4_page2_bits.cia$v_tb4_page2_addrK#define cia$l_pci_tb4_page3 cia$r_pci_tb4_page3_overlay.cia$l_pci_tb4_page3h#define cia$v_tb4_page3_valid cia$r_ pci_tb4_page3_overlay.cia$r_pci_tb4_page3_bits.cia$v_tb4_page3_validf#define cia$v_tb4_page3_addr cia$r_pci_tb4_page3_overlay.cia$r_pci_tb4_page3_bits.cia$v_tb4_page3_addrK#define cia$l_pci_tb5_page0 cia$r_pci_tb5_page0_overlay.cia$l_pci_tb5_page0h#define cia$v_tb5_page0_valid cia$r_pci_tb5_page0_overlay.cia$r_pci_tb5_page0_bits.cia$v_tb5_page0_validf#define cia$v_tb5_page0_addr cia$r_pci_tb5_page0_overlay.cia$r_pci_tb5_page0_bits.cia$v_tb5_page0_addrK#define cia$l_pci_tb5_page1 cia$r_pci_tb5_pa ge1_overlay.cia$l_pci_tb5_page1h#define cia$v_tb5_page1_valid cia$r_pci_tb5_page1_overlay.cia$r_pci_tb5_page1_bits.cia$v_tb5_page1_validf#define cia$v_tb5_page1_addr cia$r_pci_tb5_page1_overlay.cia$r_pci_tb5_page1_bits.cia$v_tb5_page1_addrK#define cia$l_pci_tb5_page2 cia$r_pci_tb5_page2_overlay.cia$l_pci_tb5_page2h#define cia$v_tb5_page2_valid cia$r_pci_tb5_page2_overlay.cia$r_pci_tb5_page2_bits.cia$v_tb5_page2_validf#define cia$v_tb5_page2_addr cia$r_pci_tb5_page2_overlay.cia$r_pci_tb5_page2_b its.cia$v_tb5_page2_addrK#define cia$l_pci_tb5_page3 cia$r_pci_tb5_page3_overlay.cia$l_pci_tb5_page3h#define cia$v_tb5_page3_valid cia$r_pci_tb5_page3_overlay.cia$r_pci_tb5_page3_bits.cia$v_tb5_page3_validf#define cia$v_tb5_page3_addr cia$r_pci_tb5_page3_overlay.cia$r_pci_tb5_page3_bits.cia$v_tb5_page3_addrK#define cia$l_pci_tb6_page0 cia$r_pci_tb6_page0_overlay.cia$l_pci_tb6_page0h#define cia$v_tb6_page0_valid cia$r_pci_tb6_page0_overlay.cia$r_pci_tb6_page0_bits.cia$v_tb6_page0_validf#define  cia$v_tb6_page0_addr cia$r_pci_tb6_page0_overlay.cia$r_pci_tb6_page0_bits.cia$v_tb6_page0_addrK#define cia$l_pci_tb6_page1 cia$r_pci_tb6_page1_overlay.cia$l_pci_tb6_page1h#define cia$v_tb6_page1_valid cia$r_pci_tb6_page1_overlay.cia$r_pci_tb6_page1_bits.cia$v_tb6_page1_validf#define cia$v_tb6_page1_addr cia$r_pci_tb6_page1_overlay.cia$r_pci_tb6_page1_bits.cia$v_tb6_page1_addrK#define cia$l_pci_tb6_page2 cia$r_pci_tb6_page2_overlay.cia$l_pci_tb6_page2h#define cia$v_tb6_page2_valid cia$r_pci_tb6_ page2_overlay.cia$r_pci_tb6_page2_bits.cia$v_tb6_page2_validf#define cia$v_tb6_page2_addr cia$r_pci_tb6_page2_overlay.cia$r_pci_tb6_page2_bits.cia$v_tb6_page2_addrK#define cia$l_pci_tb6_page3 cia$r_pci_tb6_page3_overlay.cia$l_pci_tb6_page3h#define cia$v_tb6_page3_valid cia$r_pci_tb6_page3_overlay.cia$r_pci_tb6_page3_bits.cia$v_tb6_page3_validf#define cia$v_tb6_page3_addr cia$r_pci_tb6_page3_overlay.cia$r_pci_tb6_page3_bits.cia$v_tb6_page3_addrK#define cia$l_pci_tb7_page0 cia$r_pci_tb7_page0_over lay.cia$l_pci_tb7_page0h#define cia$v_tb7_page0_valid cia$r_pci_tb7_page0_overlay.cia$r_pci_tb7_page0_bits.cia$v_tb7_page0_validf#define cia$v_tb7_page0_addr cia$r_pci_tb7_page0_overlay.cia$r_pci_tb7_page0_bits.cia$v_tb7_page0_addrK#define cia$l_pci_tb7_page1 cia$r_pci_tb7_page1_overlay.cia$l_pci_tb7_page1h#define cia$v_tb7_page1_valid cia$r_pci_tb7_page1_overlay.cia$r_pci_tb7_page1_bits.cia$v_tb7_page1_validf#define cia$v_tb7_page1_addr cia$r_pci_tb7_page1_overlay.cia$r_pci_tb7_page1_bits.cia$ v_tb7_page1_addrK#define cia$l_pci_tb7_page2 cia$r_pci_tb7_page2_overlay.cia$l_pci_tb7_page2h#define cia$v_tb7_page2_valid cia$r_pci_tb7_page2_overlay.cia$r_pci_tb7_page2_bits.cia$v_tb7_page2_validf#define cia$v_tb7_page2_addr cia$r_pci_tb7_page2_overlay.cia$r_pci_tb7_page2_bits.cia$v_tb7_page2_addrK#define cia$l_pci_tb7_page3 cia$r_pci_tb7_page3_overlay.cia$l_pci_tb7_page3h#define cia$v_tb7_page3_valid cia$r_pci_tb7_page3_overlay.cia$r_pci_tb7_page3_bits.cia$v_tb7_page3_validf#define cia$v_tb 7_page3_addr cia$r_pci_tb7_page3_overlay.cia$r_pci_tb7_page3_bits.cia$v_tb7_page3_addr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CIA_DEF_LOADED */ ww 4ZUM/*********************** ****************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise De velopment, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. ** /M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */K/* Source: 03-APR-1997 09:22:00 $1$DGA8345:[LIB_H.SRC]CIA_MCHKDEF.SDL;1 *//******************************************************************* *************************************************************/(/*** MODULE CIA_MCHKDEF IDENT X-1A2 ***/#ifndef __CIA_MCHKDEF_LOADED#define __CIA_MCHKDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __requir ed_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif #endif c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mck {N/* */N/* Define the field offsets for the machine check abort logout area */N/* */#pragma __nomember_alignment __un ion {N unsigned int mck$l_byte_count; /* Size of logout frame in bytes */ __union {$ __int64 mck$q_retry_str; __struct {- unsigned mck$v_fill_1_1 : 32;k unsigned mck$v_fill_1_2 : 30 /** WARNING: bitfield array has been reduced to a string **/ ;N unsigned mck$v_second_error : 1; /* Second error occurred */N unsigned mck$v_retry : 1; /* Retry bit */ } mck$r_fill_1_; } mck$r_fill_0_; } mck$r_count_overlay;O unsigned int mck$l_proc_offset; /* Offset to processor specific info */N unsigned int mck$l_system_offset; /* Offset to system specific info */N unsigned __int64 mck$q_mcheck_type; /* PAL-determined cause for mchk */N/* */N/* */N/* Processor specific se gment of logout frame */N/* */N unsigned __int64 mck$q_shadow8; /* Shadow registers */# unsigned __int64 mck$q_shadow9;$ unsigned __int64 mck$q_shadow10;$ unsigned __int64 mck$q_shadow11;$ unsigned __int64 mck$q_shadow12;$ unsigned __int64 mck$q_shadow13;$ unsigned __int64 mck$q_shadow14;$ unsigned __int64 mck$q_shadow25;R unsigned __int64 mck $q_paltemp0; /* PALTEMPs: 23 PAL temporary registers */$ unsigned __int64 mck$q_paltemp1;$ unsigned __int64 mck$q_paltemp2;$ unsigned __int64 mck$q_paltemp3;$ unsigned __int64 mck$q_paltemp4;$ unsigned __int64 mck$q_paltemp5;$ unsigned __int64 mck$q_paltemp6;$ unsigned __int64 mck$q_paltemp7;$ unsigned __int64 mck$q_paltemp8;$ unsigned __int64 mck$q_paltemp9;% unsigned __int64 mck$q_paltemp10;% unsigned __int64 mck$q_paltemp11;% unsigned __int64 mck $q_paltemp12;% unsigned __int64 mck$q_paltemp13;% unsigned __int64 mck$q_paltemp14;% unsigned __int64 mck$q_paltemp15;% unsigned __int64 mck$q_paltemp16;% unsigned __int64 mck$q_paltemp17;% unsigned __int64 mck$q_paltemp18;% unsigned __int64 mck$q_paltemp19;% unsigned __int64 mck$q_paltemp20;% unsigned __int64 mck$q_paltemp21;% unsigned __int64 mck$q_paltemp22;% unsigned __int64 mck$q_paltemp23;N unsigned __int64 mck$q_exc_address; /* Excepti on address register */N unsigned __int64 mck$q_exc_summ; /* Exception summary register */N unsigned __int64 mck$q_exc_mask; /* Exception mask register */R unsigned __int64 mck$q_pal_base; /* Contains the base address of Palcode */P unsigned __int64 mck$q_isr; /* Hardware Interrupt Enable Register */Q unsigned __int64 mck$q_icsr; /* Hardware Interrupt Request Register */N unsigned __int64 mck$q_ic_perr_stat; /* Icache parity error st atus */N unsigned __int64 mck$q_dc_perr_stat; /* Dcache parity error status */N unsigned __int64 mck$q_proc_va; /* Processor mcheck VA */Q unsigned __int64 mck$q_mm_stat; /* Info on memory management error or */N/* DTB miss */N unsigned __int64 mck$q_sc_addr; /* S-cache address register */N unsigned __int64 mck$q_sc_stat; /* S-cache status register */N unsi gned __int64 mck$q_bc_tag_addr; /* B cache TAG register */N unsigned __int64 mck$q_ei_addr; /* */R unsigned __int64 mck$q_fill_syndrome; /* Contains syndromes for single bit */N/* errors */N unsigned __int64 mck$q_ei_stat; /* */N unsigned __int64 mck$q_ld_lock; /* */N/*  */# unsigned __int64 mck$q_cpu_ei0;# unsigned __int64 mck$q_cpu_ei1;# unsigned __int64 mck$q_cia_err;( unsigned __int64 mck$q_cia_err_stat;( unsigned __int64 mck$q_cia_err_mask;# unsigned __int64 mck$q_cia_syn;$ unsigned __int64 mck$q_mem_err0;$ unsigned __int64 mck$q_mem_err1;$ unsigned __int64 mck$q_pci_err0;$ unsigned __int64 mck$q_pci_err1;$ unsigned __int64 mck$q_nmi_info; } MCK; #if !defined(_ _VAXC)=#define mck$l_byte_count mck$r_count_overlay.mck$l_byte_count]#define mck$v_second_error mck$r_count_overlay.mck$r_fill_0_.mck$r_fill_1_.mck$v_second_errorO#define mck$v_retry mck$r_count_overlay.mck$r_fill_0_.mck$r_fill_1_.mck$v_retry"#endif /* #if !defined(__VAXC) */ #define MCK$CIA_LOGOUT_SIZE 504Q/* This portion of the sdl file describes each of the Alcor specific registers */N/* individually. They must be referenced as if from offset 0 */N/* Alcor specific segment of the logout frame */N/* */N/* CPU Error Information 0 - 0x8740008000 */N/* */)#define MCHECK$M_CPU_ERR0_ADDR 0xFFFFFFF0 union cpu_ei0 { __int64 mcheck$q_cpu_err0; __struct {% unsigned mcheck$v_fillc0 : 4;S unsigned mcheck$v_cpu_err0_addr : 28; /* Bad addr on EV5 interface error */# int mcheck$l_cpu_err0_fill;! } mcheck$r_cpu_err0_bits; } ; #if !defined(__VAXC)>#define mcheck$v_fillc0 mcheck$r_cpu_err0_bits.mcheck$v_fillc0L#define mcheck$v_cpu_err0_addr mcheck$r_cpu_err0_bits.mcheck$v_cpu_err0_addrL#define mcheck$l_cpu_err0_fill mcheck$r_cpu_err0_bits.mcheck$l_cpu_err0_fill"#endif /* #if !defined(__VAXC) */ N/* */N/* CPU Error Infor mation 1 - 0x8740008040 */N/* */"#define MCHECK$M_CPU_ERR1_3432 0x7!#define MCHECK$M_CPU_ERR1_39 0x80##define MCHECK$M_CPU_ERR1_CMD 0xF00+#define MCHECK$M_CPU_ERR1_INT4_VALID 0xF000)#define MCHECK$M_CPU_ERR1_AC_PAR 0x200000(#define MCHECK$M_CPU_ERR1_FPE 0x40000000'#define MCHECK$M_CPU_ERR1_PE 0x80000000 union cpu_ei1 { __int64 mcheck$q_cpu_err1; __struct {N  unsigned mcheck$v_cpu_err1_3432 : 3; /* CPU addr <34:32> on error */% unsigned mcheck$v_filld0 : 4;N unsigned mcheck$v_cpu_err1_39 : 1; /* CPU addr <39> on error */N unsigned mcheck$v_cpu_err1_cmd : 4; /* CPU command */N unsigned mcheck$v_cpu_err1_int4_valid : 4; /* INT4 valid bits */% unsigned mcheck$v_filld1 : 5;Q unsigned mcheck$v_cpu_err1_ac_par : 1; /* Parity bit from CPU Addr/cmd */% unsigned mcheck$v_fill d2 : 8;T unsigned mcheck$v_cpu_err1_fpe : 1; /*Copy of csr bit to force bad parity */N unsigned mcheck$v_cpu_err1_pe : 1; /*IF set, CPU detected PE. */# int mcheck$l_cpu_err1_fill;! } mcheck$r_cpu_err1_bits; } ; #if !defined(__VAXC)L#define mcheck$v_cpu_err1_3432 mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_3432>#define mcheck$v_filld0 mcheck$r_cpu_err1_bits.mcheck$v_filld0H#define mcheck$v_cpu_err1_39 mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_39J#def ine mcheck$v_cpu_err1_cmd mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_cmdX#define mcheck$v_cpu_err1_int4_valid mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_int4_valid>#define mcheck$v_filld1 mcheck$r_cpu_err1_bits.mcheck$v_filld1P#define mcheck$v_cpu_err1_ac_par mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_ac_par>#define mcheck$v_filld2 mcheck$r_cpu_err1_bits.mcheck$v_filld2J#define mcheck$v_cpu_err1_fpe mcheck$r_cpu_err1_bits.mcheck$v_cpu_err1_fpeH#define mcheck$v_cpu_err1_pe mcheck$r_cpu_err1_bits.mcheck $v_cpu_err1_peL#define mcheck$l_cpu_err1_fill mcheck$r_cpu_err1_bits.mcheck$l_cpu_err1_fill"#endif /* #if !defined(__VAXC) */ N/* */N/* CIA Error register - 0x8740008200 */N/* */!#define MCHECK$M_ERR_CORR_ECC 0x1 #define MCHECK$M_ERR_UNC_ECC 0x2#define MCHECK$M_ERR_CPU_PE 0x4 #define MCHECK$M_ERR_MEM_NEM 0x8"#define MCHECK$M_ERR_PCI_SERR 0x10"#define MCHECK$M_ERR_PCI_PERR 0x20$#define MCHECK$M_ERR_PCI_ADR_PE 0x40!#define MCHECK$M_ERR_M_ABORT 0x80"#define MCHECK$M_ERR_T_ABORT 0x100%#define MCHECK$M_ERR_PA_PTE_INV 0x200'#define MCHECK$M_ERR_FROM_WRT_ERR 0x400&#define MCHECK$M_ERR_IOA_TIMEOUT 0x800&#define MCHECK$M_ERR_RESERVED_0 0xF000*#define MCHECK$M_ERR_LOST_CORR_ECC 0x10000)#define MCHECK$M_ERR_LOST_UNC_ECC 0x20000(#define MCHECK$M_ERR_LOST_CPU_PE 0x40000)#define MCHECK$M_ERR_LOST_ MEM_NEM 0x80000+#define MCHECK$M_ERR_LOST_PCI_SERR 0x100000+#define MCHECK$M_ERR_LOST_PCI_PERR 0x200000-#define MCHECK$M_ERR_LOST_PCI_ADR_PE 0x400000*#define MCHECK$M_ERR_LOST_M_ABORT 0x800000+#define MCHECK$M_ERR_LOST_T_ABORT 0x1000000.#define MCHECK$M_ERR_LOST_PA_PTE_INV 0x20000000#define MCHECK$M_ERR_LOST_FROM_WRT_ERR 0x4000000/#define MCHECK$M_ERR_LOST_IOA_TIMEOUT 0x8000000*#define MCHECK$M_ERR_RESERVED_1 0x70000000%#define MCHECK$M_ERR_VALID 0x80000000 union cia_err {  __int64 mcheck$q_cia_err; __struct {N unsigned mcheck$v_err_corr_ecc : 1; /* [0] */N unsigned mcheck$v_err_unc_ecc : 1; /* [1] */N unsigned mcheck$v_err_cpu_pe : 1; /* [2] */N unsigned mcheck$v_err_mem_nem : 1; /* [3] */N unsigned mcheck$v_err_pci_serr : 1; /* [4] */N unsigned mcheck$v_err_pci_perr : 1; /* [5]  */N unsigned mcheck$v_err_pci_adr_pe : 1; /* [6] */N unsigned mcheck$v_err_m_abort : 1; /* [7] */N unsigned mcheck$v_err_t_abort : 1; /* [8] */N unsigned mcheck$v_err_pa_pte_inv : 1; /* [9] */N unsigned mcheck$v_err_from_wrt_err : 1; /* [10] */N unsigned mcheck$v_err_ioa_timeout : 1; /* [11] */N unsigned mcheck$v_err_reserved_0 : 4; /* [15:12] */0 unsigned mcheck$v_err_lost_corr_ecc : 1;/ unsigned mcheck$v_err_lost_unc_ecc : 1;. unsigned mcheck$v_err_lost_cpu_pe : 1;/ unsigned mcheck$v_err_lost_mem_nem : 1;0 unsigned mcheck$v_err_lost_pci_serr : 1;0 unsigned mcheck$v_err_lost_pci_perr : 1;2 unsigned mcheck$v_err_lost_pci_adr_pe : 1;/ unsigned mcheck$v_err_lost_m_abort : 1;/ unsigned mcheck$v_err_lo st_t_abort : 1;2 unsigned mcheck$v_err_lost_pa_pte_inv : 1;4 unsigned mcheck$v_err_lost_from_wrt_err : 1;3 unsigned mcheck$v_err_lost_ioa_timeout : 1;N unsigned mcheck$v_err_reserved_1 : 3; /* */( unsigned mcheck$v_err_valid : 1;" int mcheck$l_cia_err_fill; } mcheck$r_cia_err_bits; } ; #if !defined(__VAXC)I#define mcheck$v_err_corr_ecc mcheck$r_cia_err_bits.mcheck$v_err_corr_eccG#define mcheck$v_err_unc _ecc mcheck$r_cia_err_bits.mcheck$v_err_unc_eccE#define mcheck$v_err_cpu_pe mcheck$r_cia_err_bits.mcheck$v_err_cpu_peG#define mcheck$v_err_mem_nem mcheck$r_cia_err_bits.mcheck$v_err_mem_nemI#define mcheck$v_err_pci_serr mcheck$r_cia_err_bits.mcheck$v_err_pci_serrI#define mcheck$v_err_pci_perr mcheck$r_cia_err_bits.mcheck$v_err_pci_perrM#define mcheck$v_err_pci_adr_pe mcheck$r_cia_err_bits.mcheck$v_err_pci_adr_peG#define mcheck$v_err_m_abort mcheck$r_cia_err_bits.mcheck$v_err_m_abortG#def ine mcheck$v_err_t_abort mcheck$r_cia_err_bits.mcheck$v_err_t_abortM#define mcheck$v_err_pa_pte_inv mcheck$r_cia_err_bits.mcheck$v_err_pa_pte_invQ#define mcheck$v_err_from_wrt_err mcheck$r_cia_err_bits.mcheck$v_err_from_wrt_errO#define mcheck$v_err_ioa_timeout mcheck$r_cia_err_bits.mcheck$v_err_ioa_timeoutM#define mcheck$v_err_reserved_0 mcheck$r_cia_err_bits.mcheck$v_err_reserved_0S#define mcheck$v_err_lost_corr_ecc mcheck$r_cia_err_bits.mcheck$v_err_lost_corr_eccQ#define mcheck$v_err_los t_unc_ecc mcheck$r_cia_err_bits.mcheck$v_err_lost_unc_eccO#define mcheck$v_err_lost_cpu_pe mcheck$r_cia_err_bits.mcheck$v_err_lost_cpu_peQ#define mcheck$v_err_lost_mem_nem mcheck$r_cia_err_bits.mcheck$v_err_lost_mem_nemS#define mcheck$v_err_lost_pci_serr mcheck$r_cia_err_bits.mcheck$v_err_lost_pci_serrS#define mcheck$v_err_lost_pci_perr mcheck$r_cia_err_bits.mcheck$v_err_lost_pci_perrW#define mcheck$v_err_lost_pci_adr_pe mcheck$r_cia_err_bits.mcheck$v_err_lost_pci_adr_peQ#define mcheck$v_e rr_lost_m_abort mcheck$r_cia_err_bits.mcheck$v_err_lost_m_abortQ#define mcheck$v_err_lost_t_abort mcheck$r_cia_err_bits.mcheck$v_err_lost_t_abortW#define mcheck$v_err_lost_pa_pte_inv mcheck$r_cia_err_bits.mcheck$v_err_lost_pa_pte_inv[#define mcheck$v_err_lost_from_wrt_err mcheck$r_cia_err_bits.mcheck$v_err_lost_from_wrt_errY#define mcheck$v_err_lost_ioa_timeout mcheck$r_cia_err_bits.mcheck$v_err_lost_ioa_timeoutM#define mcheck$v_err_reserved_1 mcheck$r_cia_err_bits.mcheck$v_err_reserved_1C #define mcheck$v_err_valid mcheck$r_cia_err_bits.mcheck$v_err_validI#define mcheck$l_cia_err_fill mcheck$r_cia_err_bits.mcheck$l_cia_err_fill"#endif /* #if !defined(__VAXC) */ N/* */N/* CIA Error status register - 0x8740008240 */N/* */#define DM_K_IDLE 0#define DM_K_RESTART 4096#define DM_K_IOW_64 8192#define DM_K_IOW_32 12288#define DM_K_R_4 16384#define DM_K_NONE 20480#define DM_K_DMA_RD 24576#define DM_K_DMA_WR 28672#define DM_K_GRU_WR 32768#define DM_K_GRU_RD 36864#define DM_K_CSR_RD 40960#define DM_K_PCI_RD 45056#define MCHECK$M_FILL1 0x1$#define MCHECK$M_STAT_MEM_SOURCE 0x2##define MCHECK$M_STAT_IO_QUEUE 0x3C%#define MCHECK$M_STAT_CPU_QUEUE 0x1C0$#define MCHECK$M_STAT_TLB_MISS 0x200$#define MCHECK$M_STAT_DM_STAT 0x3C00'#define MCHECK$M_STAT_PA_CPU_RES 0xC000&#d efine MCHECK$M_RESERVED_0 0x3FFF0000 union cia_error_stat { __int64 mcheck$q_cia_stat; __struct {N unsigned mcheck$v_fill1 : 1; /* [2] */N unsigned mcheck$v_stat_mem_source : 1; /* [3] */N unsigned mcheck$v_stat_io_queue : 4; /* [7:4] */N unsigned mcheck$v_stat_cpu_queue : 3; /* [10:8] */N unsigned mcheck$v_stat_tlb_miss : 1; /* [11]  */N unsigned mcheck$v_stat_dm_stat : 4; /* [15:12] */N unsigned mcheck$v_stat_pa_cpu_res : 2; /* [17:16] */N unsigned mcheck$v_reserved_0 : 14; /* [31:18] */& unsigned mcheck$v_fill_2_ : 2;# int mcheck$l_cia_stat_fill;! } mcheck$r_cia_stat_bits; } ; #if !defined(__VAXC)<#define mcheck$v_fill1 mcheck$r_cia_stat_bits.mcheck$v_fill1P#define mcheck$v_stat_mem_source mcheck$r_cia_stat_bits.mcheck$v_stat_mem_sourceL#define mcheck$v_stat_io_queue mcheck$r_cia_stat_bits.mcheck$v_stat_io_queueN#define mcheck$v_stat_cpu_queue mcheck$r_cia_stat_bits.mcheck$v_stat_cpu_queueL#define mcheck$v_stat_tlb_miss mcheck$r_cia_stat_bits.mcheck$v_stat_tlb_missJ#define mcheck$v_stat_dm_stat mcheck$r_cia_stat_bits.mcheck$v_stat_dm_statP#define mcheck$v_stat_pa_cpu_res mcheck$r_cia_stat_bits.mcheck$v_stat_pa_cpu_resF#define mcheck$v_reserved_0 mcheck$r_cia_stat_bits.mcheck$v_reserved_0L#d efine mcheck$l_cia_stat_fill mcheck$r_cia_stat_bits.mcheck$l_cia_stat_fill"#endif /* #if !defined(__VAXC) */ N/* */N/* CIA Error mask register - 0x8740008280 */N/* */&#define MCHECK$M_MASK_CORR_ECC_ERR 0x1%#define MCHECK$M_MASK_UNC_ECC_ERR 0x2 #define MCHECK$M_MASK_CPU_PE 0x4!#define MCHECK$M_MASK_MEM_NEM 0x8##define MCHECK$M_MASK_PCI_SERR 0x10##define MCHECK$M_MASK_PCI_PERR 0x20%#define MCHECK$M_MASK_PCI_ADR_PE 0x40"#define MCHECK$M_MASK_M_ABORT 0x80##define MCHECK$M_MASK_T_ABORT 0x100&#define MCHECK$M_MASK_PA_PTE_INV 0x200(#define MCHECK$M_MASK_FROM_WRT_ERR 0x400'#define MCHECK$M_MASK_IOA_TIMEOUT 0x800&#define MCHECK$M_RESERVED_1 0xFFFFF000 union cia_error_mask {$ __int64 mcheck$q_cia_error_mask; __struct {N unsigned mcheck$v_mask_corr_ecc_err : 1; /* [0]  */N unsigned mcheck$v_mask_unc_ecc_err : 1; /* [1] */N unsigned mcheck$v_mask_cpu_pe : 1; /* [2] */N unsigned mcheck$v_mask_mem_nem : 1; /* [3] */N unsigned mcheck$v_mask_pci_serr : 1; /* [4] */N unsigned mcheck$v_mask_pci_perr : 1; /* [5] */N unsigned mcheck$v_mask_pci_adr_pe : 1; /* [6] */N unsigned mcheck$v_mask_m_abort : 1; /* [7] */N unsigned mcheck$v_mask_t_abort : 1; /* [8] */N unsigned mcheck$v_mask_pa_pte_inv : 1; /* [9] */N unsigned mcheck$v_mask_from_wrt_err : 1; /* [10] */N unsigned mcheck$v_mask_ioa_timeout : 1; /* [11] */N unsigned mcheck$v_reserved_1 : 20; /* [30:12] */# int mcheck$l_cia_mask_fill;'  } mcheck$r_cia_error_mask_bits; } ; #if !defined(__VAXC)Z#define mcheck$v_mask_corr_ecc_err mcheck$r_cia_error_mask_bits.mcheck$v_mask_corr_ecc_errX#define mcheck$v_mask_unc_ecc_err mcheck$r_cia_error_mask_bits.mcheck$v_mask_unc_ecc_errN#define mcheck$v_mask_cpu_pe mcheck$r_cia_error_mask_bits.mcheck$v_mask_cpu_peP#define mcheck$v_mask_mem_nem mcheck$r_cia_error_mask_bits.mcheck$v_mask_mem_nemR#define mcheck$v_mask_pci_serr mcheck$r_cia_error_mask_bits.mcheck$v_mask_pci_serrR#d efine mcheck$v_mask_pci_perr mcheck$r_cia_error_mask_bits.mcheck$v_mask_pci_perrV#define mcheck$v_mask_pci_adr_pe mcheck$r_cia_error_mask_bits.mcheck$v_mask_pci_adr_peP#define mcheck$v_mask_m_abort mcheck$r_cia_error_mask_bits.mcheck$v_mask_m_abortP#define mcheck$v_mask_t_abort mcheck$r_cia_error_mask_bits.mcheck$v_mask_t_abortV#define mcheck$v_mask_pa_pte_inv mcheck$r_cia_error_mask_bits.mcheck$v_mask_pa_pte_invZ#define mcheck$v_mask_from_wrt_err mcheck$r_cia_error_mask_bits.mcheck$v_mask_from_w rt_errX#define mcheck$v_mask_ioa_timeout mcheck$r_cia_error_mask_bits.mcheck$v_mask_ioa_timeoutL#define mcheck$v_reserved_1 mcheck$r_cia_error_mask_bits.mcheck$v_reserved_1R#define mcheck$l_cia_mask_fill mcheck$r_cia_error_mask_bits.mcheck$l_cia_mask_fill"#endif /* #if !defined(__VAXC) */ N/* */N/* CIA Error Syndrome register - 0x8740008300 */N/*   */"#define MCHECK$M_CIA_SYNDROME 0xFF-#define MCHECK$M_CIA_SYND_UNUSED_0 0xFFFFFF00 union cia_syndrome { __int64 mcheck$q_cia_synd; __struct {+ unsigned mcheck$v_cia_syndrome : 8;1 unsigned mcheck$v_cia_synd_unused_0 : 24;# int mcheck$l_cia_synd_fill;! } mcheck$r_cia_synd_bits; } ; #if !defined(__VAXC)J#define mcheck$v_cia_syndrome mcheck$r_cia_synd_bits.mcheck$v_cia_syndromeT#define mcheck$v_cia_synd_un used_0 mcheck$r_cia_synd_bits.mcheck$v_cia_synd_unused_0L#define mcheck$l_cia_synd_fill mcheck$r_cia_synd_bits.mcheck$l_cia_synd_fill"#endif /* #if !defined(__VAXC) */ N/* */N/* CIA Memory Port status register 0 - 0x8740008400 */N/* */(#define MCHECK$M_MPSR0_ADDR_H 0xFFFFFFF0 union cia_mpsr0 { __int64 mcheck$q_cia _mpsr0; __struct {' unsigned mcheck$v_unused_0 : 4;, unsigned mcheck$v_mpsr0_addr_h : 28; int mcheck$l_mpsr0_fill;" } mcheck$r_cia_mpsr0_bits; } ; #if !defined(__VAXC)C#define mcheck$v_unused_0 mcheck$r_cia_mpsr0_bits.mcheck$v_unused_0K#define mcheck$v_mpsr0_addr_h mcheck$r_cia_mpsr0_bits.mcheck$v_mpsr0_addr_hG#define mcheck$l_mpsr0_fill mcheck$r_cia_mpsr0_bits.mcheck$l_mpsr0_fill"#endif /* #if !defined(__VAXC) */ N/*  */N/* CIA Memory Port status register 1 - 0x8740008440 */N/* */!#define MCHECK$M_MPSR1_ADDR_H 0x3##define MCHECK$M_MPSR1_ADDR_39 0x80"#define MCHECK$M_MPSR1_CMD_H 0xF00'#define MCHECK$M_MPSR1_PORT_MASK 0xF000%#define MCHECK$M_MPSR1_SEQ_ST 0xF0000(#define MCHECK$M_MPSR1_PORT_SRC 0x100000)#define MCHECK$M_MPSR1_SET_SEL 0x1F000000,#define MC HECK$M_MPSR3_RESERVED_3 0xE0000000 union cia_mpsr1 { __int64 mcheck$q_cia_mpsr1; __struct {N unsigned mcheck$v_mpsr1_addr_h : 2; /* [1:0] */N unsigned mcheck$v_mpsr1_reserved : 5; /* [6:2] */N unsigned mcheck$v_mpsr1_addr_39 : 1; /* [7] */N unsigned mcheck$v_mpsr1_cmd_h : 4; /* [11:8] */N unsigned mcheck$v_mpsr1_port_mask : 4; /* [15:12]  */N unsigned mcheck$v_mpsr1_seq_st : 4; /* [19:16] */N unsigned mcheck$v_mpsr1_port_src : 1; /* [20] */N unsigned mcheck$v_mpsr2_reserved_2 : 3; /* [23:21] */N unsigned mcheck$v_mpsr1_set_sel : 5; /* [28:24] */N unsigned mcheck$v_mpsr3_reserved_3 : 3; /* [31:29] */ int mcheck$l_mpsr1_fill;" } mcheck$r_cia_mpsr1_bits; } ; #if !defined(__VAXC)K#define mcheck$v_mpsr1_addr_h mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_addr_hO#define mcheck$v_mpsr1_reserved mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_reservedM#define mcheck$v_mpsr1_addr_39 mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_addr_39I#define mcheck$v_mpsr1_cmd_h mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_cmd_hQ#define mcheck$v_mpsr1_port_mask mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_port_maskK#define mcheck$v_mpsr1_seq_st mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_seq_stO#define mcheck$v_mpsr1 _port_src mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_port_srcS#define mcheck$v_mpsr2_reserved_2 mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr2_reserved_2M#define mcheck$v_mpsr1_set_sel mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr1_set_selS#define mcheck$v_mpsr3_reserved_3 mcheck$r_cia_mpsr1_bits.mcheck$v_mpsr3_reserved_3G#define mcheck$l_mpsr1_fill mcheck$r_cia_mpsr1_bits.mcheck$l_mpsr1_fill"#endif /* #if !defined(__VAXC) */ N/* */N/* PCI Error register 0 - 0x8740008800 */N/* */#define MCHECK$M_PCIE_CMD 0xF%#define MCHECK$M_PCIE_LOCK_STATE 0x10$#define MCHECK$M_PCIE_DAC_CYCLE 0x20"#define MCHECK$M_PCIE_WINDOW 0xF00(#define MCHECK$M_PCIE_MSTR_STATE 0xF0000)#define MCHECK$M_PCIE_TRGT_STATE 0x700000$#define MCHECK$M_UNUSED_2 0xFF800000 union cia_pcie0 { __int64 mcheck$q_cia_pcie0; __struct {N unsigned mcheck$v_pcie_cmd : 4; /* [3:0] */N unsigned mcheck$v_pcie_lock_state : 1; /* [4] */N unsigned mcheck$v_pcie_dac_cycle : 1; /* [5] */N unsigned mcheck$v_reserved : 2; /* [7:6] */N unsigned mcheck$v_pcie_window : 4; /* [11:8] */N unsigned mcheck$v_reserved_2 : 4; /* [15:12] */N unsigned mcheck$v_ pcie_mstr_state : 4; /* [19:16] */N unsigned mcheck$v_pcie_trgt_state : 3; /* [22:20] */N unsigned mcheck$v_unused_2 : 9; /* [31:23] */ int mcheck$l_pcie0_fill;! } mcheck$r_cia_pcie_bits; } ; #if !defined(__VAXC)B#define mcheck$v_pcie_cmd mcheck$r_cia_pcie_bits.mcheck$v_pcie_cmdP#define mcheck$v_pcie_lock_state mcheck$r_cia_pcie_bits.mcheck$v_pcie_lock_stateN#define mcheck$v_pcie_dac_cycle mcheck$r_cia_pcie_bits.mcheck$v_pcie_dac_cycleB#define mcheck$v_reserved mcheck$r_cia_pcie_bits.mcheck$v_reservedH#define mcheck$v_pcie_window mcheck$r_cia_pcie_bits.mcheck$v_pcie_windowF#define mcheck$v_reserved_2 mcheck$r_cia_pcie_bits.mcheck$v_reserved_2P#define mcheck$v_pcie_mstr_state mcheck$r_cia_pcie_bits.mcheck$v_pcie_mstr_stateP#define mcheck$v_pcie_trgt_state mcheck$r_cia_pcie_bits.mcheck$v_pcie_trgt_stateB#define mcheck$v_unused_2 mcheck$r_cia_pcie_bits.mcheck$v_unused_2F#define mcheck$l_pcie0_fill mcheck$r_cia_pcie_bits.mcheck$l_pcie0_fill"#endif /* #if !defined(__VAXC) */ N/* */N/* CIA PCI error register 1 - 0x8740008840 */N/* */ struct cia_pcie1 { int mcheck$l_pcie1_addr_h; int mcheck$l_pcie1_fill; } ; struct nmi_info {N int mcheck$l_nmi_info_l; /* TBD  */ int mcheck$l_nmi_info_h; } ;N/* Processor detected error types */#define MCK_PROC$K_TAG_PE 128"#define MCK_PROC$K_TAG_CTRL_PE 130!#define MCK_PROC$K_HARD_ERROR 132$#define MCK_PROC$K_PROC_CORR_ECC 134&#define MCK_PROC$K_PROC_UNCORR_ECC 136!#define MCK_PROC$K_OS_PAL_BUG 138 #define MCK_PROC$K_RESERVED2 140 #define MCK_PROC$K_RESERVED3 142#define MCK_PROC$K_PAL_BUG 144 #define MCK_PROC$K_RESERVED4 146 #define MCK_PROC$K_RESERVED5 148(#define MCK_PROC$K_ICACHE_READ_RETRY 150&#define MCK_PROC$K_PROC_HARD_ERROR 152N/* System detected error types */N/* Hex */N#define MCK_SYS$K_SYS_CORR_ECC 513 /* 201 */N#define MCK_SYS$K_SYS_UNCORR_ECC 515 /* 203 */N#define MCK_SYS$K_CIA_PE 517 /* 205  */N#define MCK_SYS$K_NXM 519 /* 207 */N#define MCK_SYS$K_PCI_SERR 521 /* 209 */N#define MCK_SYS$K_PCI_D_PE 523 /* 20b */N#define MCK_SYS$K_PCI_A_PE 525 /* 20d */N#define MCK_SYS$K_PCI_MASTER_AB 527 /* 20f */N#define MCK_SYS$K_PCI_TARG_AB 529 /* 211 */N#define MCK_SYS$K_SG_INV_PTE 531 /* 213 */N#define MCK_SYS$K_FLASH_WR_ERR 533 /* 215 */N#define MCK_SYS$K_IOA_TIMEOUT 535 /* 217 */N#define MCK_SYS$K_IOCHK 537 /* 219 */N#define MCK_SYS$K_EISA_FS_TO 539 /* 21b */N#define MCK_SYS$K_EISA_BUS_TO 541 /* 21d */N#define MCK_SYS$K_EISA_SW_NMI 543 /* 21f */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __CIA_MCHKDEF_LOADED */ wwPZUM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */I/* Source: 19-APR-1993 13:52:56 $1$DGA8345:[LIB_H.SRC]CIBHANDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CIBHANDEF ***/ #ifndef __CIBHANDEF_LOADED#define __CIBHANDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus! extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CIBHAN - CI " BUFFER HANDLE FORMAT */N/*- */ N#define CIBHAN$K_LENGTH 12 /*LENGTH OF CI BUFFER HANDLE */N#define CIBHAN$C_LENGTH 12 /*LENGTH OF CI BUFFER HANDLE */#define CIBHAN$S_CIBHANDEF 12 typedef struct _cibhan {N unsigned int cibhan$l_boff; /*BYTE OFFSET IN LOCAL BUFFER */N unsigned int cibhan$l_bname; /*NAME OF LOCA#L BUFFER */N unsigned int cibhan$l_rconid; /*REMOTE CONNECTION ID */ } CIBHAN; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CIBHANDEF_LOADED */ ww`ZUM/***************************$************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Develo%pment, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M&/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */I/* Source: 21-APR-1993 10:29:48 $1$DGA8345:[LIB_H.SRC]CIFQDTDEF.SDL;1 *//************************************************************************* '*******************************************************//*** MODULE $CIFQDTDEF ***/#ifndef __CIFQDTDEF_LOADED#define __CIFQDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __shor(t /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ ) */N/* CIFQDT - CI FREE MESSAGE/DATAGRAM QUEUE DESCRIPTOR TABLE */N/* */N/* THIS DATA STRUCTURE AND THE QUEUES IT HAS HEADERS FOR MAY BE */N/* SHARED AMONG ALL CI'S ON THE SYSTEM. */N/*- */N#define CIFQDT$K_LENGTH 32 * /*LENGTH OF CI FQDT */N#define CIFQDT$C_LENGTH 32 /*LENGTH OF CI FQDT */#define CIFQDT$S_CIFQDTDEF 32 typedef struct _cifqdt {N unsigned short int cifqdt$w_dgsiz; /*DATAGRAM SIZE (INCL PORT HEADER) */N unsigned short int cifqdt$w_msgsiz; /*MESSAGE SIZE (INCL PORT HEADER) */N int cifqdtdef$$_fill_1; /*RESERVED LONGWORD */N unsigned short int cifqdt$w_size; /*STRUCTURE SIZE IN BYTES */+N unsigned char cifqdt$b_type; /*CI STRUCTURE TYPE */N unsigned char cifqdt$b_subtyp; /*CI STRUCT SUBTYPE FOR CI FQDT */S unsigned short int cifqdt$w_dgcnt; /*SUM OF INITL DG CREDITS FOR ALL CONNX */T unsigned short int cifqdt$w_msgcnt; /*SUM OF INITL MSG CREDITS FOR ALL CONNX */N void *cifqdt$l_dgfl; /*DG FREE QUEUE FWD LINK */N void *cifqdt$l_dgbl; /*DG FREE QUEUE BACK LINK */N void *ci,fqdt$l_msgfl; /*MSG FREE QUEUE FWD LINK */N void *cifqdt$l_msgbl; /*MSG FREE QUEUE BACK LINK */ } CIFQDT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CIFQDTDEF_LOADED */ ww-ZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 C.opyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc/. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */F/* Source: 09-JUN-1993 15:26:35 $1$DGA8345:[LIB_H.SRC]CINDEF.SDL;1 *//*********************************** 0*********************************************************************************************//*** MODULE $CINDEF ***/#ifndef __CINDEF_LOADED#define __CINDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma 1__required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union 2#endif#endif N/*+ */N/* */N/* Connect to interrupt definitions for QIO parameters */N/* */N/*- */#define CIN$M_EFN 0x1#define CIN$M_USECAL 0x2#define CIN$M_REPEAT 0x4#define 3CIN$M_AST 0x8#define CIN$M_INIDEV 0x10#define CIN$M_START 0x20#define CIN$M_ISR 0x40#define CIN$M_CANCEL 0x80#define CIN$M_EFNUM 0xFFFF0000#define CIN$S_CINDEF 4 typedef struct _cin { __struct {N unsigned cin$v_efn : 1; /* Set event flag on interrupt. */N unsigned cin$v_usecal : 1; /* Use CALL interface. */N unsigned cin$v_repeat : 1; /* Do repeated interrupt service. */N unsigned cin$v_ast : 1; /*4 Queue AST on interrupt. */N unsigned cin$v_inidev : 1; /* Device initialization to do. */N unsigned cin$v_start : 1; /* Start I/O routine. */N unsigned cin$v_isr : 1; /* ISR to execute. */N unsigned cin$v_cancel : 1; /* Cancel I/O routine. */N unsigned cindef$$_fill_1 : 8; /* Spare bits. */N unsigned cin$v_efnum : 16; /* Event flag number. 5 */ } cin$r_cindef_bits; } CIN; #if !defined(__VAXC)-#define cin$v_efn cin$r_cindef_bits.cin$v_efn3#define cin$v_usecal cin$r_cindef_bits.cin$v_usecal3#define cin$v_repeat cin$r_cindef_bits.cin$v_repeat-#define cin$v_ast cin$r_cindef_bits.cin$v_ast3#define cin$v_inidev cin$r_cindef_bits.cin$v_inidev1#define cin$v_start cin$r_cindef_bits.cin$v_start-#define cin$v_isr cin$r_cindef_bits.cin$v_isr3#define cin$v_cancel cin$r_cindef_bits.cin$v_cancel1#define cin$v_6efnum cin$r_cindef_bits.cin$v_efnum"#endif /* #if !defined(__VAXC) */ #define CIN$S_CINDEF1 16 typedef struct _cin1 {N unsigned int cin$l_inidev; /* Offset to device init routine. */N unsigned int cin$l_start; /* Offset to start device routine. */S unsigned int cin$l_isr; /* Offset to interrupt service routine. */N unsigned int cin$l_cancel; /* Offset to cancel I/O routine. */ } CIN1;#define CIN$S_CINDEF2 8 type 7def struct _cin2 {N unsigned int cin$l_sptcount; /* Number of SPTs allocated. */ __union {N unsigned int cin$l_startvpn; /* Starting VPN allocated. */N unsigned int cin$l_startbit; /* Starting bit in bitmap. */! } cin$r_startvpn_overlay; } CIN2; #if !defined(__VAXC)<#define cin$l_startvpn cin$r_startvpn_overlay.cin$l_startvpn<#define cin$l_startbit cin$r_startvpn_overlay.cin$l_startbit"#endif /* #if !defined(__VAXC8) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CINDEF_LOADED */ wwEZUM/***************************************************************************/M/** 9 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SO:FTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************************;****************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */H/* Source: 20-DEC-1996 08:48:24 $1$DGA8345:[LIB_H.SRC]CLASSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CLASSDEF ***/#ifndef __CLASSDEF_LOADED#def <ine __CLASSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unkn=own_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* CLASSification data block definitions > */N/* */   9#ifdef __cplusplus /* Define structure prototypes */ struct _cls; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _class {#pragma __nomember_alignmentN struct _class *class?$l_flink; /* Standard listhead forward link */N struct _class *class$l_blink; /* Standard listhead backward link */O unsigned short int class$w_size; /* Standard structure size, in bytes */_ unsigned char class$b_type; /* Standard type code for CLASS (DYN$C_SECURITY) */^ unsigned char class$b_subtype; /* Standard subtype code (DYN$C_SECURITY_CLASS) */N struct _class *class$l_debug_flink; /* Forward link to CLASS (DEBUG) */N struct _cl@ass *class$l_debug_blink; /* Backward link to CLASS (DEBUG) */^ unsigned int class$l_debug_pid; /* PID of process that allocated this CLASS (DEBUG) */a unsigned int class$l_refcount; /* Number of attached execution contexts to this CLASS */T struct _cls *class$ar_minclass; /* Pointer to minimum classification data */T struct _cls *class$ar_maxclass; /* Pointer to maximum classification data */S struct _cls *class$ar_class; /* Pointer to active classificat Aion data */N/* */V/* The CLS classification data structures are appended to this data block as needed */N/* */ } CLASS;N#define CLASS$K_LENGTH 40 /* Length of CLASS$ structure */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointBer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CLASSDEF_LOADED */ wwlZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, anCd is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authDorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************************************************** E***************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */J/* Source: 10-APR-1992 12:20:32 $1$DGA8345:[LIB_H.SRC]CLONEVADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CLONEVADEF ***/#ifndef __CLONEVADEF_LOADED#define __CLONEVADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __Fnomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !dGefined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* Copy characteristic definitions */N/*- */N#define CLONEVA$C_COPY 0 H /* Copy */N#define CLONEVA$C_NOCOPY 1 /* No copy */N#define CLONEVA$C_DZRO 2 /* Demand zero */N#define CLONEVA$C_CW 3 /* Copy on write */N#define CLONEVA$C_MAX_CHAR 3 /* Maximum value */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __requiredI_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CLONEVADEF_LOADED */ wwZUM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise DevelopmentJ, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/MK/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************* L***********************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */G/* Source: 16-MAR-2004 13:39:08 $1$DGA8345:[LIB_H.SRC]CLUBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CLUBDEF ***/#ifndef __CLUBDEF_LOADED#define __CLUBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomeMmber_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !definNed(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CLUB - CLUSTER BLOCK. */N/* */I/* THERE IS ONE CLUB IN A VMS SYSTEM THAT OIS PART OF A CLUSTER. */I/* THE CLUB DEFINES THE STATE OF THE THE CLUSTER AS KNOWN TO */I/* THE LOCAL SYSTEM. */N/*- */N/* */I/* THE CLUB FORK BLOCK (CLUBFKB) IS A SUBBLOCK OF THE CLUB THAT IS */I/* USED WHEN IT NECESSARY TO WAIT IN ORDER TO ALLOCATE MEMORY OR */I/* WHEN PIT IS DESIRABLE TO FORK TO ALLOW OTHER FORK PROCESSES A */I/* CHANCE TO RUN. */ #include  #define CLUBFKB$M_FKB_BUSY 0x1#define CLUBFKB$M_FORKQ 0x2N#define CLUBFKB$C_LENGTH 56 /* LENGTH OF CLUBFKB */N#define CLUBFKB$K_LENGTH 56 /* LENGTH OF CLUBFKB */N#define CLUBFKB$S_CLUBFKBDEF 56 /* Old size name, synonym */ typedef struct _clubfkb { QN char clubfkb$b_fork_block [48]; /* FORK BLOCK TO WAIT IN */N unsigned int clubfkb$l_pc2; /* SAVED PC */ __union {N unsigned int clubfkb$l_status; /* CLUSTER FAILOVER STATUS FLAGS */ __struct {N unsigned clubfkb$v_fkb_busy : 1; /* FORK BLOCK IN USE FLAG */N unsigned clubfkb$v_forkq : 1; /* FORK BLOCK ON FORK QUEUE */+ unsigned clubfkb$v_fill_2_ : 6; } clubfk Rb$r_fill_1_; } clubfkb$r_fill_0_; } CLUBFKB; #if !defined(__VAXC);#define clubfkb$l_status clubfkb$r_fill_0_.clubfkb$l_statusQ#define clubfkb$v_fkb_busy clubfkb$r_fill_0_.clubfkb$r_fill_1_.clubfkb$v_fkb_busyK#define clubfkb$v_forkq clubfkb$r_fill_0_.clubfkb$r_fill_1_.clubfkb$v_forkq"#endif /* #if !defined(__VAXC) */ N/* */I/* THE CLUB POWERFAIL FORK BLOCK (CLUBPWF) IS A SUBBLOCK OF THE CLUB */I S/* THAT IS USED TO FORK FROM IPL 31 TO IPL SCS DURING POWER RECOVERY. */#define CLUBPWF$M_BUSY 0x1N#define CLUBPWF$C_LENGTH 56 /* LENGTH OF CLUBPWF */N#define CLUBPWF$K_LENGTH 56 /* LENGTH OF CLUBPWF */N#define CLUBPWF$S_CLUBPWFDEF 56 /* Old size name, synonym */ typedef struct _clubpwf {N char clubpwf$b_fork_block [48]; /* FORK BLOCK TO WAIT IN */N/* Place STATUS in aligned quadword for interlockeTd instructions */  __union {N unsigned int clubpwf$l_status; /* BLOCK STATUS FLAGS */ __struct {N unsigned clubpwf$v_busy : 1; /* FORK BLOCK IN USE FLAG */+ unsigned clubpwf$v_fill_5_ : 7; } clubpwf$r_fill_4_; } clubpwf$r_fill_3_;N char clubpwf$t_align [4]; /* QUADWORD ALIGN */ } CLUBPWF; #if !defined(__VAXC);#define clubpwf$l_status clubpwf$r_fill_3_ U.clubpwf$l_statusI#define clubpwf$v_busy clubpwf$r_fill_3_.clubpwf$r_fill_4_.clubpwf$v_busy"#endif /* #if !defined(__VAXC) */ N/* */I/* THE CLUSTER FAILOVER CONTROL BLOCK (CLUFCB) IS A SUBBLOCK OF */I/* THE CLUB THAT IS USED TO SEQUENCE FAILOVER ACTIONS IN A CLUSTER. */N/* */#define CLUFCB$M_ACTIVE 0x1#define CLUFCB$M_PENDING 0x2 V#define CLUFCB$M_SYNC_NODE 0x4#define CLUFCB$M_FKB_BUSY 0x8#define CLUFCB$M_WAITING 0x10#define CLUFCB$M_AUX 0x20 #define CLUFCB$M_RB_SUSPEND 0x40N#define CLUFCB$C_LENGTH 136 /* LENGTH OF CLUFCB */N#define CLUFCB$K_LENGTH 136 /* LENGTH OF CLUFCB */N#define CLUFCB$S_CLUFCBDEF 136 /* Old size name, synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _csb; #endif /* #ifdef __cplu Wsplus */ typedef struct _clufcb {N char clufcb$b_fork_block [48]; /* FORK BLOCK TO WAIT IN */N unsigned int clufcb$l_step; /* CURRENT FAILOVER STEP INDEX */N unsigned int clufcb$l_id; /* FAILOVER INSTANCE IDENTIFICATION */ __union {N unsigned int clufcb$l_status; /* CLUSTER FAILOVER STATUS FLAGS */ __struct {N unsigned clufcb$v_active : 1; /* FAILOVER ROUTINE ACTIVE */N unsigned clufcb$Xv_pending : 1; /* FAILOVER PENDING */N unsigned clufcb$v_sync_node : 1; /* LOCAL NODE IS SYNCHRONIZER */N unsigned clufcb$v_fkb_busy : 1; /* FORK BLOCK IN USE FLAG */N unsigned clufcb$v_waiting : 1; /* WAITING FOR NODES TO RESPOND */N unsigned clufcb$v_aux : 1; /* AUXILIARY FORK BLOCK ALLOCATED */N unsigned clufcb$v_rb_suspend : 1; /* REBUILD SUSPENDED */* unsigned clufcb$v_fill_8_ : 1; Y } clufcb$r_fill_7_; } clufcb$r_fill_6_;T struct _csb *clufcb$l_sync_csb; /* ADDRESS OF CSB OF SYNCHRONIZING SYSTEM */N char clufcb$b_nodemap [32]; /* BITMAP OF ALL INVOLVED NODES */N char clufcb$b_respmap [32]; /* BITMAP OF NODES READY FOR A STEP */N unsigned int clufcb$l_index; /* STORAGE FOR BIT MAP INDEX */N struct _fkb *clufcb$l_aux_fkb; /* ADDRESS OF AUXILIARY FORK BLOCK */ } CLUFCB; #if !defined(__VAXC)8#defZine clufcb$l_status clufcb$r_fill_6_.clufcb$l_statusI#define clufcb$v_active clufcb$r_fill_6_.clufcb$r_fill_7_.clufcb$v_activeK#define clufcb$v_pending clufcb$r_fill_6_.clufcb$r_fill_7_.clufcb$v_pendingO#define clufcb$v_sync_node clufcb$r_fill_6_.clufcb$r_fill_7_.clufcb$v_sync_nodeM#define clufcb$v_fkb_busy clufcb$r_fill_6_.clufcb$r_fill_7_.clufcb$v_fkb_busyK#define clufcb$v_waiting clufcb$r_fill_6_.clufcb$r_fill_7_.clufcb$v_waitingC#define clufcb$v_aux clufcb$r_fill_6_.clufcb$r_fill_7_.clu [fcb$v_auxQ#define clufcb$v_rb_suspend clufcb$r_fill_6_.clufcb$r_fill_7_.clufcb$v_rb_suspend"#endif /* #if !defined(__VAXC) */ N/* Cluster Page Cache (CLUPGC) - buffer cache of S0/S1 (Alpha sized) pages. */T/* An array of these structures is kept in the CLUB at the CLUB$L_PGCLIST offset. */W/* Each structure corresponds to the appropriate index for buffer size of 1-9 pages. */N/* Index level 0 is used for statistics across all buffer sizes. */ c#if !defined(__NOBASEALIGN_SUP \PORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endiftypedef struct _clupgc {#pragma __nomember_alignmentN unsigned int clupgc$l_link; /* First cached entry or zero */N unsigned int clupgc$l_cur_cached; /* # cached entries of this size */N unsigned int clupgc$l_cur_in_use; /* # active buffers of this size */O unsigned int clupgc$l_max_in_use; /* Max # a ]ctive buffers of this size */O unsigned int clupgc$l_max_cached; /* Max # cached entries of this size */N unsigned int clupgc$l_cache_lim; /* Limit value for this size */N unsigned int clupgc$l_last_alloc; /* ABSTIM of last allocation */N unsigned int clupgc$l_last_dealloc; /* ABSTIM of last deallocation */ } CLUPGC;#define CLUB$M_CLUSTER 0x1#define CLUB$M_QF_ACTIVE 0x2#define CLUB$M_QF_DYNVOTE 0x4#define CLUB$M_QF_WATCHER 0x8#define CLUB$M^_SHUTDOWN 0x10"#define CLUB$M_QF_REFRESH_REQ 0x20#define CLUB$M_LNM_RESYNCH 0x40#define CLUB$M_STS_PPHASE 0x100#define CLUB$M_STS_PH0 0x200#define CLUB$M_STS_PH1B 0x400#define CLUB$M_STS_PH1 0x800#define CLUB$M_STS_PH2 0x1000#define CLUB$M_TDF_VALID 0x2000#define CLUB$M_FKB_BUSY 0x10000#define CLUB$M_UNLOCK 0x20000#define CLUB$M_NO_FORM 0x40000#define CLUB$M_INIT 0x80000#define CLUB$M_BACKOUT 0x100000&#define CLUB$M_PRIOR_PROTOCOL 0x200000#define CLUB$M_VERBOSE 0x4_00000 #define CLUB$M_LOST_CNX 0x800000'#define CLUB$M_QF_FAILED_NODE 0x1000000 #define CLUB$M_QF_VOTE 0x2000000##define CLUB$M_QF_NEWVOTE 0x4000000##define CLUB$M_ADJ_QUORUM 0x8000000 #define CLUB$M_QUORUM 0x10000000$#define CLUB$M_TRANSITION 0x20000000##define CLUB$M_RESLOCKIP 0x40000000!#define CLUB$M_QTQEBSY 0x80000000#define CLUB$M_LK_MERGEIP 0x4#define CLUB$M_LK_DO_FULL 0x8#define CLUB$M_LK_FULL 0x10#define CLUB$M_LK_DO_DIR 0x20#define CLUB$M_LK_DIR 0x40 #define CLUB`$M_LK_NO_RMVDIR 0x80!#define CLUB$M_LK_INIT_RBLD 0x100#define CLUB$M_LK_NO_RM 0x200!#define CLUB$M_LK_TABLE_V51 0x400!#define CLUB$M_LK_SPECIAL_1 0x800 #define CLUB$M_LK_RM_DSBL 0x1000 #define CLUB$M_LK_TABLE_1 0x2000!#define CLUB$M_LK_SHUTDOWN 0x4000 #define CLUB$M_LK_SHUT_IP 0x8000#define CLUB$M_NO_FQUORUM 0x1#define CLUB$M_NO_DQUORUM 0x2#define CLUB$M_IFW_REQ 0x4#define CLUB$M_RNS_REQ 0x8#define CLUB$M_CLUGEN_VALID 0x1N#define CLUB$C_LENGTH 1056 /* LENGTH OFa CLUB */N#define CLUB$K_LENGTH 1056 /* LENGTH OF CLUB */N#define CLUB$S_CLUBDEF 1056 /* Old size name, synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _csb; struct _acb; struct _tqe;struct _cludcb;struct _cluicb;struct _clurcb; #endif /* #ifdef __cplusplus */ typedef struct _club {N struct _csb *club$l_csbqfl; /* CSB QUEUE FORWARD LINK */N struct _bcsb *club$l_csbqbl; /* CSB QUEUE BACKWARD LINK */N unsigned short int club$w_size; /* SIZE OF CLUB IN BYTES */N unsigned char club$b_type; /* STRUCTURE TYPE */N unsigned char club$b_subtype; /* STRUCTURE SUBTYPE */N unsigned int club$l_poll_ctx; /* SCS POLLER CONTEXT */Q struct _csb *club$l_local_csb; /* ADDRESS OF THE CSB FOR LOCAL SYSTEM */N struct _acb *club$l_astqfl; c /* AST QUEUE FORWARD LINK */N struct _acb *club$l_astqbl; /* AST QUEUE BACKWARD LINK */ __union {N unsigned int club$l_flags; /* CLUSTER STATUS FLAGS */ __struct {N unsigned club$v_cluster : 1; /* THIS NODE IS MEMBER OF CLUSTER */f unsigned club$v_qf_active : 1; /* QUORUM FILE IS READABLE, CONTRIBUTE TO STATIC QUORUM */_ unsigned club$v_qf_dynvote : 1; /* QUORUM FILE CAN CONTRIBUTE TO dDYNAMIC QUORUM */N unsigned club$v_qf_watcher : 1; /* NODE IS QUORUM FILE WATCHER */P unsigned club$v_shutdown : 1; /* NODE READY FOR CLUSTER SHUTDOWN */T unsigned club$v_qf_refresh_req : 1; /* QUORUM FILE REFRESH REQUESTED */b unsigned club$v_lnm_resynch : 1; /* CLUSTERWIDE LOGICAL NAME RESYNCH THREAD ACTIVE */N unsigned club$v_fill_0 : 1; /* PAD TO BYTE BOUNDARY */P unsigned club$v_sts_pphase : 1; /* STATUS ANAeLYZER POLLING PHASE */N unsigned club$v_sts_ph0 : 1; /* STATUS ANALYZER, PHASE 0 SEEN */a unsigned club$v_sts_ph1b : 1; /* STATUS ANALYZER, PHASE 1 (COORD CNX BROKEN) SEEN */\ unsigned club$v_sts_ph1 : 1; /* STATUS ANALYZER, PHASE 1 (COORD CNX OK) SEEN */N unsigned club$v_sts_ph2 : 1; /* STATUS ANALYZER, PHASE 2 SEEN */] unsigned club$v_tdf_valid : 1; /* Indicates that TDF in club has been written */N unsigned club$v_fillf_01 : 2; /* PAD TO BYTE BOUNDARY */N unsigned club$v_fkb_busy : 1; /* FORK BLOCK IN USE */N unsigned club$v_unlock : 1; /* UNLOCK REQUESTED */X unsigned club$v_no_form : 1; /* PROHIBIT NODE FROM FORMING A NEW CLUSTER */O unsigned club$v_init : 1; /* READY FOR CLUSTER JOIN/FORMATION */S unsigned club$v_backout : 1; /* MUST EVENTUALLY BACK-OUT TRANSITION */X unsigned club$v_prior_protocgol : 1; /* Earlier version protocol present */N unsigned club$v_verbose : 1; /* VERBOSE MODE */[ unsigned club$v_lost_cnx : 1; /* CONNECTION TO CLUSTER MEMBER HAS BEEN LOST */Q unsigned club$v_qf_failed_node : 1; /* A NODE HAS BEEN FAILED OUT */[ unsigned club$v_qf_vote : 1; /* QUORUM DISK IS CONTRIBUTING A (STATIC) VOTE */N unsigned club$v_qf_newvote : 1; /* STAGING FOR QF_VOTE */N unsigned clu hb$v_adj_quorum : 1; /* QUORUM ADJUSTMENT REQUESTED */N unsigned club$v_quorum : 1; /* CLUSTER IS IN QUORUM */O unsigned club$v_transition : 1; /* STATE TRANSITION IN PROGRESS */N unsigned club$v_reslockip : 1; /* RESERVATION LOCK IN PROGRESS */N unsigned club$v_qtqebsy : 1; /* QUORUM TQE IS ALREADY IN QUE */ } club$r_fill_10_; } club$r_fill_9_; __union {% unsigned int club$l_lk_flags; __stiruct {N unsigned club$v_fill_10 : 1; /* RESERVED */N unsigned club$v_fill_11 : 1; /* RESERVED */N unsigned club$v_lk_mergeip : 1; /* MERGE IN PROGRESS (LOCAL) */N unsigned club$v_lk_do_full : 1; /* DO A FULL REBUILD */N unsigned club$v_lk_full : 1; /* FULL REBUILD */N unsigned club$v_lk_do_dir : 1; /* DO A DIRECTORY REBUILD */N unsijgned club$v_lk_dir : 1; /* DIRECTORY REBUILD */N unsigned club$v_lk_no_rmvdir : 1; /* INHIBIT RMVDIRS */N unsigned club$v_lk_init_rbld : 1; /* INITIAL REBUILD FLAG */N unsigned club$v_lk_no_rm : 1; /* (obsolete) */N unsigned club$v_lk_table_v51 : 1; /* (obsolete) */N unsigned club$v_lk_special_1 : 1; /* (obsolete) */S unsigned club$v_lk_rm_dsbl : 1 k; /* REMASTER DISABLED DUE TO REBUILD */N unsigned club$v_lk_table_1 : 1; /* FAILOVER TABLE 1 IN USE */N unsigned club$v_lk_shutdown : 1; /* SHUTDOWN REQUESTED */N unsigned club$v_lk_shut_ip : 1; /* SHUTDOWN IN PROGRESS */ } club$r_fill_12_; } club$r_fill_11_;N unsigned short int club$w_rseqnum; /* FULL REBUILD SEQUENCE NUMBER */N unsigned short int club$w_dirseqnum; /* DIRECTORY REBUILD SEQ */ l __union {N unsigned char club$b_qstatus; /* QUORUM STATUS FLAGS */ __struct {N unsigned club$v_no_fquorum : 1; /* NO FORMAL QUORUM */N unsigned club$v_no_dquorum : 1; /* NO DYNAMIC QUORUM */O unsigned club$v_ifw_req : 1; /* INCARNATION FILE WRITE REQUIRED */N unsigned club$v_rns_req : 1; /* REMOVED NODE STATUS REQUIRED */N unsigned club$v_fill_03 : 4; /* PAD TO BYTE BOUNDARY m */ } club$r_fill_14_; } club$r_fill_13_;N char club$b_fill_2; /* Maintain alignment */N unsigned short int club$w_qdvotes; /* VOTES HELD BY QUORUM DISK */N unsigned short int club$w_quorum; /* CLUSTER QUORUM */N unsigned short int club$w_votes; /* CLUSTER VOTES */N unsigned short int club$w_cevotes; /* UNIVERSE OF VOTES */] unsigned short int club$w_adj_ ncevotes; /* UNIVERSE OF VOTES ADJUSTMENT REQUESTED VALUE */N unsigned short int club$w_nodes; /* NODES IN CLUSTER */N char club$b_fsysid [6]; /* FOUNDING NODE'S SYSID */ char club$b_fill_21_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 club$q_ftime; /* FOUNDING TIME o */#pragma __nomember_alignmentO unsigned int club$l_lst_xtn; /* LAST COMPLETED TRANSACTION NUMBER */Y unsigned int club$l_lst_coord; /* LAST COMPLETED TRANSACTION COORDINATOR CSID */S __int64 club$q_lst_time; /* LAST COMPLETED TRANSACTION TIME-STAMP */N unsigned char club$b_lst_code; /* LAST COMPLETED TRANSACTION CODE */N unsigned char club$b_lst_phase; /* LAST COMPLETED TRANSACTION CODE */N unsigned short int club$w_newqdvot pes; /* STAGING FOR QDVOTES */N unsigned int club$l_cur_xtn; /* CURRENT TRANSACTION NUMBER */R unsigned int club$l_cur_coord; /* CURRENT TRANSACTION COORDINATOR CSID */ char club$b_fill_22_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 club$q_cur_time; /* CURRENT TRANSACTION TIME-STAMP */ q#pragma __nomember_alignmentN unsigned char club$b_cur_code; /* TRANSACTION CODE */N unsigned char club$b_cur_phase; /* TRANSACTION PHASE */O unsigned short int club$w_msgcnt; /* OUTSTANDING/WAITING MESSAGE COUNT */N struct _csb *club$l_coord; /* COORDINATOR'S CSB ADDRESS */ __union {N unsigned int club$l_local_csid; /* LOCAL SYSTEM CSID */ __struct {N unsigned short int clurb$w_local_csid_idx; /* SLOT INDEX */N unsigned short int club$w_local_csid_seq; /* SEQUENCE NUMBER */ } club$r_fill_16_; } club$r_fill_15_;N unsigned short int club$w_next_csid; /* INDEX OF NEXT CSID TO ASSIGN */N unsigned short int club$w_first_index; /* INDEX OF FIRST CSID ASSIGNED */N unsigned int club$l_max_xtn; /* LARGEST TRANSACTION ID SEEN */S unsigned int club$l_retrycnt; /* RESOURCE ALLOCATION RETRIES AVAILABLEs */N unsigned int club$l_ctx0; /* LEVEL 0 CONTEXT AREA */N unsigned int club$l_ret1; /* LEVEL 1 SUBROUTINE RETURN */N unsigned int club$l_ctx1; /* LEVEL 1 CONTEXT AREA */N unsigned int club$l_ret2; /* LEVEL 2 SUBROUTINE RETURN */N unsigned int club$l_ctx2; /* LEVEL 2 CONTEXT AREA */N struct _tqe *club$l_tqe; /* ADDRESS OF TIMER ENTRY */R unsigned int clu tb$l_cspipid; /* PID OF CLUSTER SERVER (FOR SCH$WAKE) */ char club$b_fill_23_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 club$q_newtime; /* NEW VALUE OF TIME */#pragma __nomember_alignmentN unsigned __int64 club$q_newtime_ref; /* LOCAL REFERENCE FOR NEW TIME */N unsigned short int club$w_ unewquorum; /* NEW VALUE FOR QUORUM */N unsigned short int club$w_newcevotes; /* NEW UNIVERSE OF VOTES */Q unsigned int club$l_fmerit; /* FIGURE OF MERIT FOR OPTIMAL CLUSTER */ __union {W unsigned int club$l_e_memseq; /* EXTENDED MEMBERSHIP STATE SEQUENCE NUMBER */ __struct {T unsigned short int club$w_memseq; /* MEMBERSHIP STATE SEQUENCE NUMBER */$ short int club$w_fill_1; } club$r_fill_18_; v} club$r_fill_17_;N unsigned int club$l_random; /* RANDOM NUMBER GENERATOR CONTEXT */R struct _cludcb *club$l_cludcb; /* ADDRESS OF QUORUM DISK CONTROL BLOCK */N char club$t_qdname [16]; /* QUORUM DISK FULLDEVNAM */W struct _cluicb *club$l_cluicb; /* ADDRESS OF INCARNATION FILE CONTROL BLOCK */] unsigned int club$l_foreign_cluster; /* SHIFT REGISTER INDICATING FOREIGN CLUSTER SEEN */N unsigned int club$l_enbl_verbose; /* TIME TO ENABL wE VERBOSE MODE */Q unsigned int club$l_qlost_clugen; /* CLUSTER GENERATION WHEN QUORUM LOST */R unsigned int club$l_stg_join_clugen; /* STAGING AREA FOR CLUSTER GENERATION */[ unsigned int club$l_join_clugen; /* JOINING NODE'S LAST CLUSTER GENERATION NUMBER */O unsigned short int club$w_stg_join_flags; /* STAGING AREA FOR JOIN FLAGS */ __union {N unsigned short int club$w_join_flags; /* JOINING NODE'S FLAGS */ __struct {Q unsigned x club$v_clugen_valid : 1; /* GENERATION DATA FIELDS VALID */N unsigned club$v_fill_04 : 15; /* PAD TO BYTE BOUNDARY */ } club$r_fill_20_; } club$r_fill_19_;N unsigned int club$l_rm_quota; /* REMASTERING QUOTA */ char club$b_fill_24_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN y unsigned __int64 club$q_cspq; /* QUEUE FOR COMMUNICATION WITH CSP */[ char club$b_fork_block [56]; /* FORK BLOCK TO WAIT IN (CLUBFKB SUB-STRUCTURE) */#pragma __nomember_alignmentN char club$b_nodemap [32]; /* BITMAP OF ALL POSSIBLE NODES */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN char club$b_clufcb [136]; z /* CLUSTER FAILOVER CONTROL BLOCK */a FKB club$r_pgc_fkb; /* Fork Block for Cluster Page Cache Trimming/Recovery */U char club$b_clubpwf [56]; /* FORK BLOCK TO USE DURING POWER RECOVERY */O/* New cells located at end to minimize rebuiding. Should be moved someday. */#pragma __nomember_alignmentN unsigned int club$l_reslocktmo; /* RESERVATION EXPIRATION TIME */N unsigned int club$l_reslockcsid; /* CSID OF RESERVATION HOLDER */{N unsigned int club$l_locktime; /* TIME LOCKED */N unsigned short int club$w_merge_cnt; /* MERGE COUNTER */N unsigned short int club$w_parseqnum; /* PARTIAL REBUILD SEQUENCE NUMBER */N unsigned char club$b_newrbld_req; /* PROPOSED REBUILD REQUEST */N unsigned char club$b_rbld_clu; /* REBUILD IN PROGRESS IN CLUSTER */O unsigned char club$b_rbld_loc; /* REBUILD IN PROGRESS ON LOCAL NODE */N char club$b_fill_2|1; /* ALIGN */N struct _clurcb *club$l_clurcbfl; /* ACTIVE RCBs */N struct _clurcb *club$l_clurcbbl; /* */Q unsigned short int club$w_rbld_inhib; /* REASONS TO INHIBIT A LOCK REBUILD */ short int club$w_fill_22;N unsigned short int club$w_ncnid; /* NEXT CLUSTER NODE ID */N unsigned short int club$w_newncnid; /* NEW NEXT CLUSTER NODE ID */N unsigned} int club$l_toff; /* LOCKING OFF */N unsigned int club$l_ton; /* LOCKING ON */N void *club$l_tbls; /* TABLE START */N struct _tqe *club$l_qtqe; /* POINTER TO QUORUM LOSS TQE */N unsigned int club$l_sync_step; /* SYNC STEP COUNT (move to clurcb) */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomemb ~er_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 club$q_tdf; /* DTS TDF */N unsigned __int64 club$q_block_seq; /* Fast Re-master Block */N/* Transfer Sequence # */O char club$b_lckmgr_fork_block [56]; /* Fork block to fork down to LCKMGR */S unsigned int club$l_rmbuf_link; /* Pointer to first free Remaster buffer */c#if !defined(__NOBASEALIGN _SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifO unsigned int club$l_max_rmbufs; /* Maximum concurrent remaster xfers */N unsigned int club$l_cached_rmbufs; /* Number of cached rm xfer buffers */U unsigned int club$l_tot_rmbufs; /* Total rm xfer buffers (cached + active) */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or  C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifN __union { /* Cluster Page Cache Structures */ __struct {#pragma __nomember_alignment! int club$l_link_fill;S unsigned int club$l_cur_cached; /* # cached entries across all sizes */S unsigned int club$l_cur_in_use; /* # active buffers across all sizes */W unsigned int club$l_max_in_use; /* Max # active buffers across all sizes */W unsigned int club$l_max_cached; /* Max # cached entries across all sizes */& int club$l_cache_lim_fill;V unsigned int club$l_last_alloc; /* ABSTIM of last allocation (any size) */Z unsigned int club$l_last_dealloc; /* ABSTIM of last deallocation (any size) */. char club$b_entry_list_fill [288]; } club$r_pgc_totals;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endif\ CLUPGC club$r_pgclist [10]; /* Cluster Page Cache List Array, Totals + [1..9] */ } club$r_pgc_overlay; } CLUB; #if !defined(__VAXC)0#define club$l_flags club$r_fill_9_.club$l_flagsD#define club$v_cluster club$r_fill_9_.club$r_fill_10_.club$v_clusterH#define club$v_qf_active club$r_fill_9_.club$r_fill_10_.club$v_qf_activeJ#define club$v_qf_dynvote club$r_fill_9_.club$r_fill_10_.club$v_qf_dynvoteJ#define club$v_qf_watcher club$r_fill_9_.club$r_fill_10_.club$v_qf_watcherF#define club$v_shutdown club$r_fill_9_.club$r_fill_10_.club$v_shutdownR#define club$v_qf_refresh_req club$r_fill_9_.club$r_fill_10_.club$v_qf_refresh_reqL#define club$v_lnm_resynch club$r_fill_9_.club$r_fill_10_.club$v_lnm_resynchJ#define club$v_sts_pphase club$r_fill_9_.club$r_fill_10_.club$v_sts_pphaseD#define club$v_sts_ph0 club$r_fill_9_.club$r_fill_10_.club$v_sts_ph0F#define club$v_sts_ph1b club$r_fill_9_.club$r_fill_10_.club$v_sts_ph1bD#define club$v_sts_ph1 club$r_fill_9_.club$r_fill_10_.club$v_sts_ph1D#define club$v_sts_ph2 club$r_fill_9_.club$r_fill_10_.club$v_sts_ph2H#define club$v_tdf_valid club$r_fill_9_.club$r_fill_10_.club$v_tdf_validF#define club$v_fkb_busy club$r_fill_9_.club$r_fill_10_.club$v_fkb_busyB#define club$v_unlock club$r_fill_9_.club$r_fill_10_.club$v_unlockD#define club$v_no_form club$r_fill_9_.club$r_fill_10_.club$v_no_form>#define club$v_init club$r_fill_9_.club$r_fill_10_.club$v_initD#define club$v_backout club$r_fill_9_.club$r_fill_10_.club$v_backoutR#define club$v_prior_protocol club$r_fill_9_.club$r_fill_10_.club$v_prior_protocolD#define club$v_verbose club$r_fill_9_.club$r_fill_10_.club$v_verboseF#define club$v_lost_cnx club$r_fill_9_.club$r_fill_10_.club$v_lost_cnxR#define club$v_qf_failed_node club$r_fill_9_.club$r_fill_10_.club$v_qf_failed_nodeD#define club$v_qf_vote club$r_fill_9_.club$r_fill_10_.club$v_qf_voteJ#define club$v_qf_newvote club$r_fill_9_.club$r_fill_10_.club$v_qf_newvoteJ#define club$v_adj_quorum club$r_fill_9_.club$r_fill_10_.club$v_adj_quorumB#define club$v_quorum club$r_fill_9_.club$r_fill_10_.club$v_quorumJ#define club$v_transition club$r_fill_9_.club$r_fill_10_.club$v_transitionH#define club$v_reslockip club$r_fill_9_.club$r_fill_10_.club$v_reslockipD#define club$v_qtqebsy club$r_fill_9_.club$r_fill_10_.club$v_qtqebsy7#define club$l_lk_flags club$r_fill_11_.club$l_lk_flagsK#define club$v_lk_mergeip club$r_fill_11_.club$r_fill_12_.club$v_lk_mergeipK#define club$v_lk_do_full club$r_fill_11_.club$r_fill_12_.club$v_lk_do_fullE#define club$v_lk_full club$r_fill_11_.club$r_fill_12_.club$v_lk_fullI#define club$v_lk_do_dir club$r_fill_11_.club$r_fill_12_.club$v_lk_do_dirC#define club$v_lk_dir club$r_fill_11_.club$r_fill_12_.club$v_lk_dirO#define club$v_lk_no_rmvdir club$r_fill_11_.club$r_fill_12_.club$v_lk_no_rmvdirO#define club$v_lk_init_rbld club$r_fill_11_.club$r_fill_12_.club$v_lk_init_rbldG#define club$v_lk_no_rm club$r_fill_11_.club$r_fill_12_.club$v_lk_no_rmO#define club$v_lk_table_v51 club$r_fill_11_.club$r_fill_12_.club$v_lk_table_v51O#define club$v_lk_special_1 club$r_fill_11_.club$r_fill_12_.club$v_lk_special_1K#define club$v_lk_rm_dsbl club$r_fill_11_.club$r_fill_12_.club$v_lk_rm_dsblK#define club$v_lk_table_1 club$r_fill_11_.club$r_fill_12_.club$v_lk_table_1M#define club$v_lk_shutdown club$r_fill_11_.club$r_fill_12_.club$v_lk_shutdownK#define club$v_lk_shut_ip club$r_fill_11_.club$r_fill_12_.club$v_lk_shut_ip5#define club$b_qstatus club$r_fill_13_.club$b_qstatusK#define club$v_no_fquorum club$r_fill_13_.club$r_fill_14_.club$v_no_fquorumK#define club$v_no_dquorum club$r_fill_13_.club$r_fill_14_.club$v_no_dquorumE#define club$v_ifw_req club$r_fill_13_.club$r_fill_14_.club$v_ifw_reqE#define club$v_rns_req club$r_fill_13_.club$r_fill_14_.club$v_rns_req;#define club$l_local_csid club$r_fill_15_.club$l_local_csidS#define club$w_local_csid_idx club$r_fill_15_.club$r_fill_16_.club$w_local_csid_idxS#define club$w_local_csid_seq club$r_fill_15_.club$r_fill_16_.club$w_local_csid_seq7#define club$l_e_memseq club$r_fill_17_.club$l_e_memseqC#define club$w_memseq club$r_fill_17_.club$r_fill_18_.club$w_memseq;#define club$w_join_flags club$r_fill_19_.club$w_join_flagsO#define club$v_clugen_valid club$r_fill_19_.club$r_fill_20_.club$v_clugen_validP#define club$l_cur_cached club$r_pgc_overlay.club$r_pgc_totals.club$l_cur_cachedP#define club$l_cur_in_ use club$r_pgc_overlay.club$r_pgc_totals.club$l_cur_in_useP#define club$l_max_in_use club$r_pgc_overlay.club$r_pgc_totals.club$l_max_in_useP#define club$l_max_cached club$r_pgc_overlay.club$r_pgc_totals.club$l_max_cachedP#define club$l_last_alloc club$r_pgc_overlay.club$r_pgc_totals.club$l_last_allocT#define club$l_last_dealloc club$r_pgc_overlay.club$r_pgc_totals.club$l_last_dealloc8#define club$r_pgclist club$r_pgc_overlay.club$r_pgclist"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CLUBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 28-APR-1993 14:08:54 $1$DGA8345:[LIB_H.SRC]CLUDCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CLUDCBDEF ***/#ifndef __CLUDCBDEF_LOADED#define __CLUDCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CLUDCB - Cluster Quorum Disk Control Block  */N/*- */ #define CLUDCB$M_QS_REM_INA 0x1#define CLUDCB$M_QS_REM_ACT 0x2!#define CLUDCB$M_QS_NOT_READY 0x4#define CLUDCB$M_QS_READY 0x8#define CLUDCB$M_QS_ACTIVE 0x10 #define CLUDCB$M_QS_CLUSTER 0x20#define CLUDCB$M_QS_VOTE 0x40#define CLUDCB$M_QF_INQTMO 0x1#define CLUDCB$M_QF_INQIP 0x2#define CLUDCB$M_QF_TIM 0x4#define CLUDCB$M_QF_RIP 0x8#define CLUDCB$M_QF_WIP 0x10#define CLUDCB$M _QF_ERROR 0x20"#define CLUDCB$M_QF_FIRST_ERR 0x40 #define CLUDCB$M_QF_WRL_ERR 0x80"#define CLUDCB$M_QF_NOACCESS 0x100#define CLUDCB$M_CSP_ACK 0x1"#define CLUDCB$M_CSP_LBN_VALID 0x2#define CLUDCB$M_CSP_MVHELP 0x4O#define CLUDCB$K_F_LENGTH 64 /* Length of fixed portion of CLUDCB */O#define CLUDCB$C_F_LENGTH 64 /* Length of fixed portion of CLUDCB */N#define CLUDCB$K_LENGTH 580 /* Length of CLUDCB */N#define CLUDCB$C_LENGTH 580 /* Length of CLUDCB */N/* The quorum disk is specified with 4 sysgen parameters. DISK_QUORUM1 */#define CLUDCB$S_DISK_QUORUM 16  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; struct _irp; struct _tqe; #endif /* #ifdef __cplusplus */ typedef struct _cludcb {N struct _cludcb *cludcb$l_cludcbfl; /* Forward Link (not used) */N struct _cludcb *cludcb$l_cludcbbl; /* Backward Link (not used) */N unsigned short int cludcb$w_size; /* Size of CLUDCB (bytes) */N unsigned char cludcb$b_type; /* Structure type */N unsigned char cludcb$b_subtype; /* Structure subtype */N struct _ucb *cludcb$l_ucb; /* Address of quorum disk UCB */N struct _irp *cludcb$l_irp; /* Address of IRP */N struct _tqe *cludcb$l_tqe; /* Address of timer queue entry */N unsigned int cludcb$l_watcher_csid; /* C SID of quorum file watcher */N unsigned int cludcb$l_act_count; /* Saved activity counter */ N unsigned int cludcb$l_qflbn; /* Quorum file logical block number */N char cludcb$t_align2 [4]; /* QUADWORD ALIGN BEFORE */ __union {N unsigned short int cludcb$w_state; /* Quorum disk state bits */ __struct {N unsigned cludcb$v_qs_rem_ina : 1; /* Remote inactive */N unsigned cludcb$v_qs_rem_act : 1; /* Remote active */N unsigned cludcb$v_qs_not_ready : 1; /* Not ready */N unsigned cludcb$v_qs_ready : 1; /* Ready */N unsigned cludcb$v_qs_active : 1; /* Active */\ unsigned cludcb$v_qs_cluster : 1; /* Active and this node is a cluster member */N unsigned cludcb$v_qs_vote : 1; /* Potential vote */* unsigned cludcb$v_fill_6_ : 1; } cludcb$r_fill_1_; } cludcb$r_fill_0_;N short int cludcb$w_fill_1; /* Fill to next longword */ __union {N unsigned short int cludcb$w_flags; /* CLUDCB status bits */ __struct {N unsigned cludcb$v_qf_inqtmo : 1; /* Status inquiry timed out */N unsigned cludcb$v_qf_inqip : 1; /* Remote inquiry in progress */N unsigned cludcb$v_qf_tim : 1; /* Read or write timed out */N unsigned cludcb$v_qf_rip : 1; /* Read in progress */N unsigned cludcb$v_qf_wip : 1; /* Write in progress */U unsigned cludcb$v_qf_error : 1; /* Quorum disk error has been reported */W unsigned cludcb$v_qf_first_err : 1; /* First error has already been seen */O unsigned cludcb$v_qf_wrl_err : 1; /* Quorum disk is write-locked */Z unsigned cludcb$v_qf_noaccess : 1; /* Never access the quorum disk directl y */* unsigned cludcb$v_fill_7_ : 7; } cludcb$r_fill_3_; } cludcb$r_fill_2_;N short int cludcb$w_fill_2; /* Fill to next longword */N/* The interlocked flags field is in its own quadword for granulary reasons */  __union {a unsigned short int cludcb$w_csp_flags; /* Flags for interlocked communication with CSP */ __struct {R unsigned cludcb$v_csp_ack : 1; /* CSP request has been acknowledged */R  unsigned cludcb$v_csp_lbn_valid : 1; /* CSP has found a quorum file */O unsigned cludcb$v_csp_mvhelp : 1; /* Restart mount verification */* unsigned cludcb$v_fill_8_ : 5; } cludcb$r_fill_5_; } cludcb$r_fill_4_;N char cludcb$t_align4 [6]; /* QUADWORD ALIGN AFTER */N unsigned char cludcb$b_counter; /* Iteration counter */N char cludcb$b_fill_3 [3]; /* Fill to next longword */ N char cludcb$t_align5 [4]; /* QUADWORD ALIGN */ N char cludcb$t_buffer [516]; /* Quorum file buffer */N/* to DISK_QUORUM4. Each parameter can specify 4 bytes. */ } CLUDCB; #if !defined(__VAXC)6#define cludcb$w_state cludcb$r_fill_0_.cludcb$w_stateQ#define cludcb$v_qs_rem_ina cludcb$r_fill_0_.cludcb$r_fill_1_.cludcb$v_qs_rem_inaQ#define cludcb$v_qs_rem_act cludcb$r_fill_0_.cludcb$r_fill_1_.cludcb$v_qs_rem_actU#define cludcb$v_qs_not_ready cludcb$r_fill_0_.cludcb$r_fill_1_.cludcb$v_qs_not_readyM#define cludcb$v_qs_ready cludcb$r_fill_0_.cludcb$r_fill_1_.cludcb$v_qs_readyO#define cludcb$v_qs_active cludcb$r_fill_0_.cludcb$r_fill_1_.cludcb$v_qs_activeQ#define cludcb$v_qs_cluster cludcb$r_fill_0_.cludcb$r_fill_1_.cludcb$v_qs_clusterK#define cludcb$v_qs_vote cludcb$r_fill_0_.cludcb$r_fill_1_.cludcb$v_qs_vote6#define cludcb$w_flags cludcb$r_fill_2_.cludcb$w_flagsO#define cludcb$v_qf_inqtmo cludcb$r_fill_2_.cludcb$r_fill_3_.cludcb$v_qf_inqtmoM#define cludcb$v_qf_inqip cludcb$r_fill_2_.cludcb$r_fill_3_.cludcb$v_qf_inqipI#define cludcb$v_qf_tim cludcb$r_fill_2_.cludcb$r_fill_3_.cludcb$v_qf_timI#define cludcb$v_qf_rip cludcb$r_fill_2_.cludcb$r_fill_3_.cludcb$v_qf_ripI#define cludcb$v_qf_wip cludcb$r_fill_2_.cludcb$r_fill_3_.cludcb$v_qf_wipM#define cludcb$v_qf_error cludcb$r_fill_2_.cludcb$r_fill_3_.cludcb$v_qf_errorU#define cludcb$v_qf_first_err cludcb$r_fill_2_.cludcb$r_fill_3_.cludcb$v_qf_first_errQ#define cludcb$v_qf_wrl_err cludcb$r_fill_2_.cludcb$r_fill_3_.cludcb$v_qf_wrl_errS#define cludcb$v_qf_noaccess cludcb$r_fill_2_.cludcb$r_fill_3_.cludcb$v_qf_noaccess>#define cludcb$w_csp_flags cludcb$r_fill_4_.cludcb$w_csp_flagsK#define cludcb$v_csp_ack cludcb$r_fill_4_.cludcb$r_fill_5_.cludcb$v_csp_ackW#define cludcb$v_csp_lbn_valid cludcb$r_fill_4_.cludcb$r_fill_5_.cludcb$v_csp_lbn_validQ#define cludcb$v_csp_mvhelp cludcb$r_fill_4_.cludcb$r_fill_5_.cludcb$v_csp_mvhelp"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CLUDCBDEF_LOADED */ wwW[UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */F/* Source: 02-SEP-1989 10:36:16 $1$DGA8345:[LIB_H.SRC]CLUDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CLUDEF ***/#i fndef __CLUDEF_LOADED#define __CLUDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CLUDEF - CLUSTER DEFINITIONS */N/*- */N#define CLU$C_MAX_NODES 256 /* MAX CLUSTER NODES */N#define CLU$K_MAX_NODES 256 /* MAX CLUSTER NODES */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CLUDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVM S SDL V3.7 */J/* Source: 16-DEC-1993 14:32:41 $1$DGA8345:[LIB_H.SRC]CLUEVTIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CLUEVTIDEF ***/#ifndef __CLUEVTIDEF_LOADED#define __CLUEVTIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* get the ACB def */N/* get the CLUEVTHNDL def */ #include #include N#define CLUACB$K_LENGTH 52 /* Length of block. */N#define CLUACB$C_LENGTH 52 /* Lengt h of block. */ typedef struct _cluacb { ACB cluacb$r_generic_acb;X CLUEVTHNDL cluacb$r_handle; /* unique handle id (in case of cancellation) */N unsigned int cluacb$l_event; /* event type value */Z int cluacb$l_local_queue; /* set indicates CLUACB on CLUEVT private queue */ } CLUACB;N#define CLUEVT$K_LENGTH 64 /* Length of block. */N#define CLUEVT$C_LENGTH 64 /* Length of block. */  9#ifdef __cplusplus /* Define structure prototypes */struct _cluacb; #endif /* #ifdef __cplusplus */ typedef struct _cluevt {N unsigned int cluevt$l_reserved_1; /* set up default header */% unsigned int cluevt$l_reserved_2;% unsigned short int cluevt$w_size; unsigned char cluevt$b_type;# unsigned char cluevt$b_subtype;N unsigned int cluevt$l_seq_num; /* ever increasing counter */N struct _cluacb  *cluevt$l_add_qfl; /* queued CLUACBs */% struct _cluacb *cluevt$l_add_qbl;% struct _cluacb *cluevt$l_rem_qfl;% struct _cluacb *cluevt$l_rem_qbl;N unsigned int cluevt$l_reserved_3; /* reserved for future use */% unsigned int cluevt$l_reserved_4;% unsigned int cluevt$l_reserved_5;% unsigned int cluevt$l_reserved_6;% unsigned int cluevt$l_reserved_7;% unsigned int cluevt$l_reserved_8;% unsigned int cluevt$l_reserved_9;% unsigned int cluevt$l_reserved_0; } CLUEVT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CLUEVTIDEF_LOADED */ ww0[UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 22-APR-1993 10:35:40 $1$DGA8345:[LIB_H.SRC]CLUICBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CLUICBDEF ***/#ifndef __CLUICBDEF_LOADED#define __CLUICBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */ N/* CLUICB - Incarnation File Control Block */N/*- */ #define CLUICB$M_WIP 0x1#define CLUICB$M_WREQ 0x2N#define CLUICB$K_F_LENGTH 32 /* Length of fixed portion */N#define CLUICB$C_F_LENGTH 32 /* Length of fixed portion */N/* End of fixed portion of the block */N#define CLUICB$T_BUFFER 32 /* Sta rt of incarnation */N/* file buffer area */  9#ifdef __cplusplus /* Define structure prototypes */ struct _irp; #endif /* #ifdef __cplusplus */ typedef struct _cluicb {N/* Fixed portion */N struct _cluicb *cluicb$l_fl; /* Forward Link */N struct _cluicb *cluicb$l_bl; /* Backward Link */N unsigned short int cluicb$w_size; /* Size of block */N unsigned char cluicb$b_type; /* Structure type */N unsigned char cluicb$b_subtype; /* Structure subtype */N struct _irp *cluicb$l_irp; /* Address of IRP */S unsigned int cluicb$l_lbn; /* Incarnation file logical block number */N unsigned short int cluicb$w_wip_cnt; /* Write-in-progress counter */N short int cluicb$w_fil l_1; /* Align */ __union {N unsigned short int cluicb$w_flags; /* Flags */ __struct {N unsigned cluicb$v_wip : 1; /* Write-in-progress bit */N unsigned cluicb$v_wreq : 1; /* Write requested bit */* unsigned cluicb$v_fill_2_ : 6; } cluicb$r_fill_1_; } cluicb$r_fill_0_;N short int cluicb$w_fill_2; /* Align  */N char cluicb$t_align [4]; /* QUADWORD ALIGN */ } CLUICB; #if !defined(__VAXC)6#define cluicb$w_flags cluicb$r_fill_0_.cluicb$w_flagsC#define cluicb$v_wip cluicb$r_fill_0_.cluicb$r_fill_1_.cluicb$v_wipE#define cluicb$v_wreq cluicb$r_fill_0_.cluicb$r_fill_1_.cluicb$v_wreq"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CLUICBDEF_LOADED */ ww@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not  **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************* ***********************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 20-APR-1993 10:52:59 $1$DGA8345:[LIB_H.SRC]CLUOPTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CLUOPTDEF ***/#ifndef __CLUOPTDEF_LOADED#define __CLUOPTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CLUOPT - Cluster Optimal ReConfiguration Context Block */N/*- */ N#define CLUOPT$K_L ENGTH 116 /* Length of CLUOPT */N#define CLUOPT$C_LENGTH 116 /* Length of CLUOPT */ typedef struct _cluopt {N struct _cluopt *cluopt$l_prev; /* Link to previous CLUOPT block */P struct _cluopt *cluopt$l_best; /* Link to best attained CLUOPT block */N unsigned short int cluopt$w_size; /* Size of CLUOPT (bytes) */N unsigned char cluopt$b_type; /* Structure type */N unsigned  char cluopt$b_subtype; /* Structure subtype */N unsigned int cluopt$l_cmerit; /* Figure of merit of nodes in CMAP */U unsigned int cluopt$l_acmerit; /* Figure of merit of nodes in AMAP + CMAP */N char cluopt$b_cmap [32]; /* Map of nodes in proposed cluster */P char cluopt$b_amap [32]; /* Map of nodes available for cluster */V char cluopt$b_rmap [32]; /* Map of nodes remaining for consideration */ } CLUOPT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CLUOPTDEF_LOADED */ ww`A[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */H/* Source: 16-AUG-2000 15:14:46 $1$DGA8345:[LIB_H.SRC]CLUPBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CLUPBDEF ***/#ifndef __CLUPBDEF_LOADED#define __CLUP BDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CLUPB - PARALLEL CONTEXT BLOCK  */N/* */N/*- */ #define CLUPB$M_BUSY 0x1#define CLUPB$K_FIX_LENGTH 52N/* Optional extensions for user's of the service */#define CLUPB$K_RBLD_LENGTH 88N#define CLUPB$K_LENGTH 88 /*LENGTH */N#define CLUPB$C_LENGTH 88 /*LENGTH  */#define CLUPB$S_CLUPBDEF 88  9#ifdef __cplusplus /* Define structure prototypes */ struct _rsb; struct _lkb; #endif /* #ifdef __cplusplus */ typedef struct _clupb {N/* This section reserved for the service itself */N char clupb$b_fork_block [32]; /* FORK BLOCK */ __union {N unsigned short int clupb$w_flags; /* STATUS FLAGS */N __struct { /* FORK BLOCK IN USE */& unsigned clupb$v_busy : 1;) unsigned clupb$v_fill_0_ : 7;! } clupb$r_flags_bits; } clupb$r_flags_overlay;N unsigned char clupb$b_threads; /* ACTIVE THREADS */N unsigned char clupb$b_max_threads; /* MAX ACTIVE THREADS */N unsigned int clupb$l_parent; /* PARENT CONTEXT BLOCK */N/* This section filled in by user of service */N  int (*clupb$l_action)(); /* ACTION ROUTINE */N int (*clupb$l_cplrtn)(); /* COMPLETION ROUTINE */N unsigned int clupb$l_cplprm; /* COMPLETION PARAMETER */ char clupb$b_fill_1_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {N/* Lock rebuild extensions  */#pragma __nomember_alignment __struct {N unsigned int clupb$l_rtn1; /* SAVED RETURN ADDRESS */N unsigned char clupb$b_qcnt; /* QUEUE COUNTER */N char clupb$b_fill_1 [3]; /* FILL */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __no member_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _rsb *clupb$q_rtrsb; /* ROOT RSB */#else unsigned __int64 clupb$q_rtrsb;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ N struct _rsb *clupb$q_rsb_list; /* RSB LIST ADDRESS */#else# unsigned __int64 clupb$q_rsb_list;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _lkb *clupb$q_lkb_list; /* LKB LIST ADDRESS */#else# unsigned __int64 clupb$q_lkb_list;#endif% } clupb$r_rbld_structure;N/* Other extensions  can go here */# } clupb$r_clubr_extensions; } CLUPB; #if !defined(__VAXC)9#define clupb$w_flags clupb$r_flags_overlay.clupb$w_flagsJ#define clupb$v_busy clupb$r_flags_overlay.clupb$r_flags_bits.clupb$v_busyQ#define clupb$l_rtn1 clupb$r_clubr_extensions.clupb$r_rbld_structure.clupb$l_rtn1Q#define clupb$b_qcnt clupb$r_clubr_extensions.clupb$r_rbld_structure.clupb$b_qcntS#define clupb$q_rtrsb clupb$r_clubr_extensions.clupb$r_rbld_stru cture.clupb$q_rtrsbY#define clupb$q_rsb_list clupb$r_clubr_extensions.clupb$r_rbld_structure.clupb$q_rsb_listY#define clupb$q_lkb_list clupb$r_clubr_extensions.clupb$r_rbld_structure.clupb$q_lkb_list"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus } #endif#pragma __standard #endif /* __CLUPBDEF_LOADED */ wwph[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */I/* Source: 07-OCT-1999 11:2 7:53 $1$DGA8345:[LIB_H.SRC]CLURCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CLURCBDEF ***/#ifndef __CLURCBDEF_LOADED#define __CLURCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CLURCB - REMASTER CONTROL BLOCK */N/* */N/*- */ #define CLURCB$M_BUSY 0x1#define CLURCB$M_FQ 0x2!#define CLURCB $M_EXP_DONE_VLD 0x4#define CLURCB$M_QUOTA 0x8#define CLURCB$M_OLDMST 0x10#define CLURCB$M_EXPMSG 0x20#define CLURCB$M_TQE 0x40#define CLURCB$M_CANCEL 0x80#define CLURCB$M_BXFR 0x100 #define CLURCB$M_BXFR_LAST 0x200 #define CLURCB$M_WVB_ABORT 0x400N#define CLURCB$K_LENGTH 1384 /*LENGTH OF CLURCB */N#define CLURCB$C_LENGTH 1384 /*LENGTH OF CLURCB */N#define CLURCB$S_CLURCBDEF 1384 /*Old size name synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _lkb; struct _rsb; struct _club; struct _cdrp; #endif /* #ifdef __cplusplus */ typedef struct _clurcb {N struct _clurcb *clurcb$l_clurcbfl; /* FORWARD LINK */N struct _clurcb *clurcb$l_clurcbbl; /* BACKWARD LINK */N unsigned short int clurcb$w_size; /* SIZE IN BYTES */N unsigned char clurcb$b_type; /* STRUCTURE TYPE  */N unsigned char clurcb$b_subtype; /* STRUCTURE SUBTYPE */N unsigned short int clurcb$w_rseqnum; /* FULL REBUILD SEQ NUM */N unsigned short int clurcb$w_parseqnum; /* PARTIAL REBUILD SEQ NUM */N/* Align the fork block */ N char clurcb$b_fork_block [64]; /* FORK BLOCK / TQE TO WAIT IN */ __union {N unsigned int clurcb$l_flags; /* STATUS FLAGS */ __struct {N unsigned clurcb$v_busy : 1; /* Fork block in use */N unsigned clurcb$v_fq : 1; /* On fork queue */O unsigned clurcb$v_exp_done_vld : 1; /* Expected done count valid */N unsigned clurcb$v_quota : 1; /* Quota charged */N unsigned clurcb$v_oldmst : 1; /* Old master */N unsigned clurcb$v_expmsg : 1; /* Message expected */N  unsigned clurcb$v_tqe : 1; /* Queued as TQE */N unsigned clurcb$v_cancel : 1; /* Cancel TQE thread */N unsigned clurcb$v_bxfr : 1; /* can use block transfer */N unsigned clurcb$v_bxfr_last : 1; /* bxfer - last buffer */N unsigned clurcb$v_wvb_abort : 1; /* Block WVB needs to clean up */* unsigned clurcb$v_fill_2_ : 5; } clurcb$r_fill_1_; } clurcb$r_fill_0_;N  unsigned char clurcb$b_qcnt; /* LOCK QUEUE COUNTER */N char clurcb$b_fill_1 [3]; /* ALIGN */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _lkb *clurcb$q_lkb_list; /* ADDRESS OF LKB LIST */#else$ unsigned __int64 clurcb$q_lkb_list;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _rsb *clurcb$q_rsb_list; /* ADDRESS OF RSB LIST */#else$ unsigned __int64 clurcb$q_rsb_list;#endif#pragma __nomember_alignmentN unsigned __int64 clurcb$q_cntx1; /* CONTEXT STORAGE */N unsigned __int64 clurcb$q_cntx2; /* CONTEXT STORAGE */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN int (*clurcb$l_waitret)(); /* RETURN PC STORAGE */N int (*clurcb$l_errret)(); /* RETURN PC ON ERROR */N unsigned int clurcb$l_exptime; /* Expiration time */N unsigned short int clurcb$w_exp_done; /* RBLD_DONES expected */N unsigned short int clurcb$w_rcv_done; /* RBLD_DONES received */N unsigned int clurcb$l_newmaster; /* NEW MASTER'S CSID */N unsigned int clurcb$l_oldmaster; /* OLD MASTER'S CSID */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomemb er_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _rsb *clurcb$q_rsb; /* ADDRESS OF ROOT RSB */#else unsigned __int64 clurcb$q_rsb;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _club *clurcb$l_club; /* ADDRESS OF CLUB */N unsigned short int clurcb$w_respcnt; /* EXPECTED RESPONSE COUNT */N unsigned short int clurcb$w_index; /* MAP INDEX */N int (*clurcb$l_savrtn)(); /* SAVED RETURN ADDRESS */N int (*clurcb$l_msgbld)(); /* MESSAGE BUILD ROUTINE */N char clurcb$b_nodemap [32]; /* NODES TO REBUILD */N char clurcb$b_shutmap [32]; /* NODES WITH TRAFFIC SHUTDOWN */N char clurcb$b_ackmap [32]; /* NODES RETURNING ACKS */N char clurcb$b_resmap [32]; /* NODES NEEDING RESUMPTION */N void *clurcb$l_bptr; /* Bxfer buffer pointer */N unsigned int clurcb$l_bsize; /* Bxfer buffer allocated size */N unsigned int clurcb$l_boff; /* c urrent Offset in buffer */N struct _cdrp *clurcb$l_bxfr_cdrp; /* block transfer CDRP */N int clurcb$l_nrsb; /* number of RSBs written to buffer */N int clurcb$l_nlkb; /* number of LKBs written to buffer */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defi ned whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _rsb *clurcb$q_currsb; /* current RSB during Block XFER */#else" unsigned __int64 clurcb$q_currsb;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _lkb *clurcb$q_curlkb; /* current LKB during Block XFER */#else" unsigned __int64 clurcb$q_curlkb;#endifN __int64 clurcb$q_rmstart; /* timing extensions */#pragma __nomember_alignmentN int clurcb$l_totrsb; /* timing extensions */N int clurcb$l_totlkb; /* timing extensions */N int clurcb$l_wvbsent; /* WVB bufs in flight */ char clurcb$b_fill_3_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cpl usplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN int clurcb$l_wvbbuf [256]; /* Write value block buf pointers */ } CLURCB; #if !defined(__VAXC)6#define clurcb$l_flags clurcb$r_fill_0_.clurcb$l_flagsE#define clurcb$v_busy clurcb$r_fill_0_.clurcb$r_fill_1_.clurcb$v_busyA#define clurcb$v_fq clurcb$r_fill_0_.clurcb$r_fill_1_.clurcb$v_fqU#define clurcb$v_exp_done_vld clurcb$r_fill_0_.clurcb$r_fill_1_.clurcb$v_exp_done_vldG#define clurcb$v_quota clurcb$r_fill_0_.clurcb$r_fill_1_.clurcb$v_quotaI#define clurcb$v_oldmst clurcb$r_fill_0_.clurcb$r_fill_1_.clurcb$v_oldmstI#define clurcb$v_expmsg clurcb$r_fill_0_.clurcb$r_fill_1_.clurcb$v_expmsgC#define clurcb$v_tqe clurcb$r_fill_0_.clurcb$r_fill_1_.clurcb$v_tqeI#define clurcb$v_cancel clurcb$r_fill_0_.clurcb$r_fill_1_.clurcb$v_cancelE#define clurcb$v_bxfr clurcb$r_fill_0_.clurcb$r_fill_1_.clurcb$v_bxfrO#define clurcb$v_bxfr_last clurcb$r_fill_0_.clurcb$r_fill_1_.clurcb$v_bxfr_lastO#define clurcb$v_wvb_abort clurcb$r_fill_0_.clurcb$r_fill_1_.clurcb$v_wvb_abort"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CLURCBDEF_LOADED */  ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */I/* Source: 31-JAN-2008 14:10:08 $1$DGA8345:[LIB_H.SRC]CLUSDADEF.SDL;1 *//***************** ***************************************************************************************************************//*** MODULE $CLUSDADEF ***/#ifndef __CLUSDADEF_LOADED#define __CLUSDADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#def ine __union variant_union#endif#endif N/*+ */I/* $CLUSDADEF - define an incoming connect block. This block handles */I/* all of the activity for one connection. Since only one command */I/* can be active at any time, a permanent CDRP is allocated with */I/* this block. */N/*-  */ N#define CLUSDA$C_BUGCHK 1 /* Cluster bugcheck protocol */O#define CLUSDA$C_PRTLEV 2 /* 32-bit Remote SDA Protocol level */O#define CLUSDA$C_PRTLEV_64 3 /* 64-bit Remote SDA Protocol level */N#define CLUSDA$C_IDLE 0 /* Idle */N#define CLUSDA$C_ACTIVE 1 /* CDRP is in use */N#define CLUSDA$C_LENGTH 24 /* LENGTH OF FIXED PART */N#define CLUSDA$K_LENGTH 24 /* LENGTH OF FIXED PART */  9#ifdef __cplusplus /* Define structure prototypes */ struct _cdt; struct _pdt; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _clusda {N/* */#pragma __nomember_alignmentN struct _clusda *clusda$l_flink; /* Queue forward link */N struct _clusda *clusda$l_blink; /* Queue backward link */N unsigned short int clusda$w_size; /* Structure size */N unsigned short int clusda$w_type; /* Structure type */N struct _cdt *clusda$l_cdt; /* CDT address */N struct _pdt *clusda$l_pdt; /* PDT address */N unsigned short int clusda$w_state; /* Connect state */N/* State values */N unsigned short int clusda$w_fill_1; /* Unused */ N char clusda$b_cdrp [1]; /* Start of permanent CDRP */ char clusda$b_fill_0_ [7]; } CLUSDA;#define CLUSDA$S_CLUSDADEF 32N/* */N/* Data structure built in  NPP by CLUSTER_CRASH */N/* */N#define SCSSDA$K_LENGTH 144 /* Length of the structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _scssda {#pragma __nomember_alignmentN unsigned int scssda$l_ref_count; /* Reference count for this block */N unsigned int scssda$l_cluster_flag; /* =1 if crashing all nodes */N unsigned short int scssda$w_size; /* Structure size */N unsigned char scssda$b_type; /* Structure type */N unsigned char scssda$b_subtype; /* Structure subtype */V unsigned int scssda$l_attempts; /* Number of nodes we've attempted to crash */N unsigned char scssda$t_target_node [8]; /* Name of targe t node */N unsigned char scssda$t_message_1 [16]; /* First part of coroner message */N unsigned short int scssda$w_connect; /* The connect code */O unsigned char scssda$t_message_2 [14]; /* Second part of coroner message */S unsigned __int64 scssda$q_system_id; /* The target system's ID (from the SB) */U SBO scssda$t_system_data; /* The SBO data returned by SCS$CONFIG_SYS */ } SCSSDA;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CLUSDADEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********** *********************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */J/* Source: 28-APR-1993 17:14:04 $1$DGA8345:[LIB_H.SRC]CMNBDLTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CMNBDLTDEF ***/#ifndef __CMNBDLTDEF_LOADED#define __CMNBDLTDEF_LOADED 1 G#pragma __nostanda rd /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define CMNBDLT$K_RESERVED_LENGTH 80 /* Length of Reserved area */N#define CMNBDLT$K_LENGTH 128 /* Length of Header */N#define CMNBDLT$ C_LENGTH 128 /* Length of Header */N#define CMNBDLT$C_LEAF_ENTRY_SZ 16 /* Length of one leaf pointer entry */##define CMNBDLT$C_INIT_BDLT_INDEX 7S/* Initial BDLT LAST_INDEX, used to show space occupied by BDLT header is in use */N#define CMNBDLT$S_CMNBDLTDEF 144 /* Old size name - synonym */ typedef struct _cmnbdlt {N unsigned __int64 cmnbdlt$q_phy_addr; /* BDLT physical address */N unsigned short int cmnbdlt$w_size; /* Structure size in bytes */N unsigned char cmnbdlt$b_type; /* Structure Type */N unsigned char cmnbdlt$b_subtype; /* Structure Subtype for BDLT */N unsigned int cmnbdlt$l_bd_cnt; /* Current number of assigned BDs */N unsigned int cmnbdlt$l_fill; /* Unused for alignment */N unsigned int cmnbdlt$l_qbdlt_cnt; /* Count of BDLT waits */N unsigned int cmnbdlt$l_last_index; /* Highest current BDLT Index  */N unsigned int cmnbdlt$l_max_index; /* Maximum allowed BDLT Index */N void *cmnbdlt$l_free_bd; /* Free BD list */S void *cmnbdlt$l_port_ptr; /* reserved for port/port driver pointer */N void *cmnbdlt$l_waitfl; /* BD Wait Queue FLINK */N void *cmnbdlt$l_waitbl; /* BD Wait Queue BLINK */N unsigned __int64 cmnbdlt$q_reserved_1; /* Reserved quadword */N unsigned __int64 cmnbdlt$q_reserved_2; /* Reserved quadword */N unsigned __int64 cmnbdlt$q_reserved_3; /* Reserved quadword */N unsigned __int64 cmnbdlt$q_reserved_4; /* Reserved quadword */N unsigned __int64 cmnbdlt$q_reserved_5; /* Reserved quadword */N unsigned __int64 cmnbdlt$q_reserved_6; /* Reserved quadword */N unsigned __int64 cmnbdlt$q_reserved_7; /* Reserved quadword */N unsigned __int64 cmnbdlt$q_reserve d_8; /* Reserved quadword */N unsigned __int64 cmnbdlt$q_reserved_9; /* Reserved quadword */N unsigned __int64 cmnbdlt$q_reserved_10; /* Reserved quadword */\ unsigned __int64 cmnbdlt$q_bdl_ptr0_phy; /* Buffer Descriptor 0 Leaf Physical Pointer */[ unsigned __int64 cmnbdlt$q_bdl_ptr0_vir; /* Buffer Descriptor 0 Leaf Virtual Pointer */ } CMNBDLT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CMNBDLTDEF_LOADED */ ww+[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************* *******************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */F/* Source: 23-APR-1993 13:51:11 $1$DGA8345:[LIB_H.SRC]CONDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CONDEF ***/#ifndef __CONDEF_LOADED#define __CONDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Console function codes (defined in SRM). */N/* */N/*- */N#define CON$C_SWDONE 1 /* Software done */N#define CON$C_BOOTCPU 2 /* Boot function code */N#define CON$C_CLRWARM 3 /* Clear warm start flag */N#define CON$C_CLRCOLD 4 /* Clear cold start flag */N/*+   */N/* */N/* Routine specifier codes used when calling CON$ASSIST_PSWITCH */N/* */N/*- */N#define CON$C_START_SWITCH 1 /* Start primary switch operation */N#define CON$C_ABORT_SWITCH 2 /* Abort prima ry switch operation */N#define CON$C_FINISH_SWITCH 3 /* Finish primary switch operation */#define RXCST$M_IE 0x40#define RXCST$M_RDY 0x80 typedef struct _rxcst { __struct {$ unsigned rxcst$v_fill_1 : 6;N unsigned rxcst$v_ie : 1; /* Receiver Interrupt Enable */N unsigned rxcst$v_rdy : 1; /* Receiver Data Ready */ } rxcst$r_rxcst_fields; } RXCST; #if !defined(__VAXC)2#define rxcst$v_ie rxcst$r_r xcst_fields.rxcst$v_ie4#define rxcst$v_rdy rxcst$r_rxcst_fields.rxcst$v_rdy"#endif /* #if !defined(__VAXC) */ #define TXCST$M_IE 0x40#define TXCST$M_RDY 0x80#define TXCST$M_ERR 0x8000 typedef struct _txcst { __struct {$ unsigned txcst$v_fill_1 : 6;N unsigned txcst$v_ie : 1; /* Transmitter Interrupt Enable */N unsigned txcst$v_rdy : 1; /* Transmitter Ready for Input */$ unsigned txcst$v_fill_2 : 7;N unsigned txcst$v _err : 1; /* Error sending, pls re-transmit */ } txcst$r_txcst_fields; } TXCST; #if !defined(__VAXC)2#define txcst$v_ie txcst$r_txcst_fields.txcst$v_ie4#define txcst$v_rdy txcst$r_txcst_fields.txcst$v_rdy4#define txcst$v_err txcst$r_txcst_fields.txcst$v_err"#endif /* #if !defined(__VAXC) */ #define RXTX$M_ERR 0x8000 typedef struct _rxtx { __struct {N unsigned rxtx$v_data : 8; /* Data field of RXDB/TXDB */N unsigned rxtx$ v_id : 4; /* ID field of RXDB/TXDB */# unsigned rxtx$v_fill_1 : 3;N unsigned rxtx$v_err : 1; /* Error bit, RXDB only */ } rxtx$r_rxtx_fields; } RXTX; #if !defined(__VAXC)2#define rxtx$v_data rxtx$r_rxtx_fields.rxtx$v_data.#define rxtx$v_id rxtx$r_rxtx_fields.rxtx$v_id0#define rxtx$v_err rxtx$r_rxtx_fields.rxtx$v_err"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CONDEF_LOADED */ wwR[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************* ***********************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */L/* Source: 09-JUN-2015 15:54:10 $1$DGA8345:[LIB_H.SRC]CONFIG_TABLE.SDL;1 *//********************************************************************************************************************************//*** MODULE CONFIG_TABLE ***/#ifndef __CONFIG_TABLE_LOADED#define __CONFIG_TABLE_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* The configuration table has a 64-bit mask prefix. This mask is used to */N/* strip the HW ID in the bus array prior to matching against the ID in the */N/* configuration entry array. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _config_header {#pragma __nomember_alignmentN __union {  /* HW ID mask union */N __struct { /* HW ID mask as longwords */T unsigned int iogen_cfg_tbl$l_hw_id_mask_lo; /* HW ID mask low 32-bits */U unsigned int iogen_cfg_tbl$l_hw_id_mask_hi; /* HW ID mask high 32-bits */+ } iogen_cfg_tbl$r_hw_id_mask_i;N unsigned __int64 iogen_cfg_tbl$q_hw_id_mask; /* HW ID mask 64-bits */( } iogen_cfg_tbl$r_id_mask_union; } CONFIG_HEADER; #if !defined(__VAXC)~#define iogen_cfg_tbl$l_hw_id_mask_lo iogen_cfg_tbl$r_id_mask_union.iogen_cfg_tbl$r_hw_id_mask_i.iogen_cfg_tbl$l_hw_id_mask_lo~#define iogen_cfg_tbl$l_hw_id_mask_hi iogen_cfg_tbl$r_id_mask_union.iogen_cfg_tbl$r_hw_id_mask_i.iogen_cfg_tbl$l_hw_id_mask_hi[#define iogen_cfg_tbl$q_hw_id_mask iogen_cfg_tbl$r_id_mask_union.iogen_cfg_tbl$q_hw_id_mask"#endif /* #if !defined(__VAXC) */ N#define IOGEN_CFG_TBL$K_HEADER_LEN 8 /* Length of the entry */N/*  */N/* This structure provides a layout of the memory used by the */N/* config table. It is prepended to the config_table structure */N/* and is typically used only for creation and deletion of the */N/* table. */N/* */N/* The table is created from a single pool allocation.  This pool */N/* fragment is then managed by the table creation routines as a */N/* private pool. This minimizes fragmentation of pool, and allows */N/* the entire table to be deleted by a single call. */N/* */N/* The definition has been worked to be the same size as a "normal" */N/* block header for VMS. The first two longword are not a flink */N/*  and blink - since this is not part of a queue. But the size, */N/* type and subtype fields are all in the right places. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _config_memdsc {#pragma __nomember_alignmentT char *config_memdsc$ps_fragment; /* Pointer to free memory in the fragment */S short int config_memdsc$w_free; /* Amount of memory left in the fragment */R char config_memdsc$b_refcnt; /* Number of references to the fragment */N char config_memdsc$b_fill; /* Spare byte */U short int config_memdsc$w_size; /* Total size of the pool fragment or FFFF */N char config_memdsc$b_type; /* Block type */N char config_memdsc$b_subtype; /* Subtype */O int config_memdsc$l_actual_size; /* Actual block size if size is FFFF */ } CONFIG_MEMDSC;N/* */P/* This structure describes an array entry in the config table. It uses the */R/* iogen_cfg_tbl prefix for historical reasons. The first 32 bytes (up to the */P/* flags) is identical in format to a hand-defined BLISS definition that was */X/* replaced in IOGEN_MACROS.REQ. The second 32 bytes provide additional information */N/* to allow boot configuration, and make the configuration extensible. */N/* */N/* If you touch this structure size, or order of the fields, you must edit */W/* IOGEN_MACROS.REQ as well as any *_SUPPORT.C bus modules to ensure that the dummy */N/* records are properly initialized. */N/*  */ #define IOGEN_CFG_TBL$M_MSCP 0x1 #define IOGEN_CFG_TBL$M_SCSI 0x2$#define IOGEN_CFG_TBL$M_NOVECTOR 0x4 #define IOGEN_CFG_TBL$M_DISK 0x8$#define IOGEN_CFG_TBL$M_NETWORK 0x10!#define IOGEN_CFG_TBL$M_PORT 0x20"#define IOGEN_CFG_TBL$M_CLASS 0x40##define IOGEN_CFG_TBL$M_PSEUDO 0x80"#define IOGEN_CFG_TBL$M_BOOT 0x100(#define IOGEN_CFG_TBL$M_CASE_BLIND 0x200&#define IOGEN_CFG_TBL$M_NO_TABLE 0x400)#define IOGEN_CFG_TBL$M_EXTENDED_ID 0x800&#define IOGEN_CFG_TBL$M_FOREIGN 0x1000$#define IOGEN_CFG_TBL$M_FIBRE 0x2000"#define IOGEN_CFG_TBL$M_ULP 0x4000-#define IOGEN_CFG_TBL$M_LOAD_DRV_CLASS 0x8000%#define IOGEN_CFG_TBL$M_NISCA 0x10000+#define IOGEN_CFG_TBL$M_ISA_ON_EISA 0x20000$#define IOGEN_CFG_TBL$M_CISS 0x40000##define IOGEN_CFG_TBL$M_SAS 0x80000##define IOGEN_CFG_TBL$M_SYS_DEV 0x1"#define IOGEN_CFG_TBL$M_REMOTE 0x2&#define IOGEN_CFG_TBL$M_ALT_PREFIX 0x4'#define IOGEN_CFG_TBL$M_NO_CTRL_LTR 0x8(#define IOGEN_CFG_TBL$M_HW_CTRL_LTR 0x10##define IOGEN_CFG_TBL$M_UNIT_0 0x20'#define IOGEN_CFG_TBL$M_CTRL_LTR_A 0x40'#define IOGEN_CFG_TBL$M_CREATE_DEV 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _iogen_cfg_tbl {#pragma __nomember_alignmentN __union { /* HW ID union */N __struct  { /* HW ID as longwords */N unsigned int iogen_cfg_tbl$l_hw_id_lo; /* HW ID low 32-bits */N unsigned int iogen_cfg_tbl$l_hw_id_hi; /* HW ID high 32-bits */$ } iogen_cfg_tbl$r_hw_id;N unsigned __int64 iogen_cfg_tbl$q_hw_id; /* HW ID as 64-bits */N char iogen_cfg_tbl$b_hw_id_string [8]; /* HW ID as a string */# } iogen_cfg_tbl$r_id_union;\ void *iogen_cfg_tbl$ps_driver_name; /* Point!er to the device driver name (descriptor) */P char *iogen_cfg_tbl$ps_devnam; /* Pointer to the device name (ASCIZ) */N unsigned int iogen_cfg_tbl$l_vector_cnt; /* Number of interrupt vectors */N unsigned int iogen_cfg_tbl$l_vector_align; /* Alignment for SCB vectors */N unsigned int iogen_cfg_tbl$l_num_units; /* Number of units */ __union {N unsigned int iogen_cfg_tbl$l_flags; /* Device flag word */N __struct { /*" Device flag bits */N unsigned iogen_cfg_tbl$v_mscp : 1; /* MSCP device */N unsigned iogen_cfg_tbl$v_scsi : 1; /* SCSI device */N unsigned iogen_cfg_tbl$v_novector : 1; /* No Vector */N unsigned iogen_cfg_tbl$v_disk : 1; /* Disk */N unsigned iogen_cfg_tbl$v_network : 1; /* Network */N unsigned iogen_cfg_tbl$v_port : 1; /* Port driver # */N unsigned iogen_cfg_tbl$v_class : 1; /* Class driver */N unsigned iogen_cfg_tbl$v_pseudo : 1; /* Psuedo driver */N unsigned iogen_cfg_tbl$v_boot : 1; /* Bootable device */N unsigned iogen_cfg_tbl$v_case_blind : 1; /* Match case blind */P unsigned iogen_cfg_tbl$v_no_table : 1; /* This is the dummy table */_ unsigned iogen_cfg_tbl$v_extended_id : 1; /* ID check should not use the HW_MASK$ */N unsigned iogen_cfg_tbl$v_foreign : 1; /* Entry is from TPB file */N unsigned iogen_cfg_tbl$v_fibre : 1; /* Fibre Channel */N unsigned iogen_cfg_tbl$v_ulp : 1; /* Upper-Level Protocol */d unsigned iogen_cfg_tbl$v_load_drv_class : 1; /* Load driver class when loading driver */R unsigned iogen_cfg_tbl$v_nisca : 1; /* Identifies NISCA port driver */a unsigned iogen_cfg_tbl$v_isa_on_eisa : 1; /* Device is a ISA d %evice on an EISA bus */N unsigned iogen_cfg_tbl$v_ciss : 1; /* CISS controller */N unsigned iogen_cfg_tbl$v_sas : 1; /* SAS controller */1 unsigned iogen_cfg_tbl$v_fill_0_ : 4;* } iogen_cfg_tbl$r_c_flag_bits;" } iogen_cfg_tbl$r_c_flags;N char *iogen_cfg_tbl$ps_description; /* Description of device (ASCIZ) */N unsigned int iogen_cfg_tbl$l_adp_type; /* Adapter type */N char *iogen_cfg_tbl$ps_a&ssoc_drv; /* Associated driver (ASCIZ) */N char *iogen_cfg_tbl$ps_addl_names; /* Additional names (ASCIZ) */N char *iogen_cfg_tbl$ps_dtype; /* Pointer to TYPE string (ASCIZ) */N char *iogen_cfg_tbl$ps_boot_class; /* Boot class name (ASCIZ) */ __union {N unsigned int iogen_cfg_tbl$l_boot_flags; /* Boot flag word */N __struct { /* Boot flag bits */S unsigned iogen_cfg_tbl$v_s'ys_dev : 1; /* Device can be a system disk */N unsigned iogen_cfg_tbl$v_remote : 1; /* Remote */N unsigned iogen_cfg_tbl$v_alt_prefix : 1; /* Alternate prefix */Z unsigned iogen_cfg_tbl$v_no_ctrl_ltr : 1; /* Don't assign controller letter */X unsigned iogen_cfg_tbl$v_hw_ctrl_ltr : 1; /* Needs same controller letter */N unsigned iogen_cfg_tbl$v_unit_0 : 1; /* Unit 0 */P unsigned iogen_cfg_tbl$v(_ctrl_ltr_a : 1; /* Device must be unique */Q unsigned iogen_cfg_tbl$v_create_dev : 1; /* Must create new device */* } iogen_cfg_tbl$r_b_flag_bits;" } iogen_cfg_tbl$r_b_flags;N char *iogen_cfg_tbl$ps_private; /* For extensions (ASCIZ) */X char *iogen_cfg_tbl$ps_curr_name; /* Pointer to the current device name (ASCIZ) */N int iogen_cfg_tbl$l_index; /* Index into additional names */N int iogen_cfg_tbl$l_avail; /* Ava )ilable for extensions */N int iogen_cfg_tbl$l_avail2; /* Available for extensions */ } IOGEN_CFG_TBL; #if !defined(__VAXC)h#define iogen_cfg_tbl$l_hw_id_lo iogen_cfg_tbl$r_id_union.iogen_cfg_tbl$r_hw_id.iogen_cfg_tbl$l_hw_id_loh#define iogen_cfg_tbl$l_hw_id_hi iogen_cfg_tbl$r_id_union.iogen_cfg_tbl$r_hw_id.iogen_cfg_tbl$l_hw_id_hiL#define iogen_cfg_tbl$q_hw_id iogen_cfg_tbl$r_id_union.iogen_cfg_tbl$q_hw_idZ#define iogen_cfg_tbl$b_hw_id_string iogen_cfg_tbl$r_i*d_union.iogen_cfg_tbl$b_hw_id_stringK#define iogen_cfg_tbl$l_flags iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$l_flagse#define iogen_cfg_tbl$v_mscp iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_mscpe#define iogen_cfg_tbl$v_scsi iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_scsim#define iogen_cfg_tbl$v_novector iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_novectore#define iogen_cfg_tbl$v_disk iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c+_flag_bits.iogen_cfg_tbl$v_diskk#define iogen_cfg_tbl$v_network iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_networke#define iogen_cfg_tbl$v_port iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_portg#define iogen_cfg_tbl$v_class iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_classi#define iogen_cfg_tbl$v_pseudo iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_pseudoe#define iogen_cfg_tbl$v_boot iogen_cfg_tbl$r,_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_bootq#define iogen_cfg_tbl$v_case_blind iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_case_blindm#define iogen_cfg_tbl$v_no_table iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_no_tables#define iogen_cfg_tbl$v_extended_id iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_extended_idk#define iogen_cfg_tbl$v_foreign iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_-foreigng#define iogen_cfg_tbl$v_fibre iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_fibrec#define iogen_cfg_tbl$v_ulp iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_ulpy#define iogen_cfg_tbl$v_load_drv_class iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_load_drv_classg#define iogen_cfg_tbl$v_nisca iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_niscas#define iogen_cfg_tbl$v_isa_on_eisa iogen_cfg_tbl$r_c_flag.s.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_isa_on_eisae#define iogen_cfg_tbl$v_ciss iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_cissc#define iogen_cfg_tbl$v_sas iogen_cfg_tbl$r_c_flags.iogen_cfg_tbl$r_c_flag_bits.iogen_cfg_tbl$v_sasU#define iogen_cfg_tbl$l_boot_flags iogen_cfg_tbl$r_b_flags.iogen_cfg_tbl$l_boot_flagsk#define iogen_cfg_tbl$v_sys_dev iogen_cfg_tbl$r_b_flags.iogen_cfg_tbl$r_b_flag_bits.iogen_cfg_tbl$v_sys_devi#define iogen_cfg_tbl$v_remote iogen_cfg_t/bl$r_b_flags.iogen_cfg_tbl$r_b_flag_bits.iogen_cfg_tbl$v_remoteq#define iogen_cfg_tbl$v_alt_prefix iogen_cfg_tbl$r_b_flags.iogen_cfg_tbl$r_b_flag_bits.iogen_cfg_tbl$v_alt_prefixs#define iogen_cfg_tbl$v_no_ctrl_ltr iogen_cfg_tbl$r_b_flags.iogen_cfg_tbl$r_b_flag_bits.iogen_cfg_tbl$v_no_ctrl_ltrs#define iogen_cfg_tbl$v_hw_ctrl_ltr iogen_cfg_tbl$r_b_flags.iogen_cfg_tbl$r_b_flag_bits.iogen_cfg_tbl$v_hw_ctrl_ltri#define iogen_cfg_tbl$v_unit_0 iogen_cfg_tbl$r_b_flags.iogen_cfg_tbl$r_b_flag_bits.iogen0_cfg_tbl$v_unit_0q#define iogen_cfg_tbl$v_ctrl_ltr_a iogen_cfg_tbl$r_b_flags.iogen_cfg_tbl$r_b_flag_bits.iogen_cfg_tbl$v_ctrl_ltr_aq#define iogen_cfg_tbl$v_create_dev iogen_cfg_tbl$r_b_flags.iogen_cfg_tbl$r_b_flag_bits.iogen_cfg_tbl$v_create_dev"#endif /* #if !defined(__VAXC) */ N#define IOGEN_CFG_TBL$K_ENTRY_SIZE 80 /* Length of the entry */N/* */N/* The config_table structure is the union of both th 1e hw id mask, */N/* and the config table (iogen_cfg_tbl). This structure is pointed */N/* to by ADP$PS_CONFIG_TABLE. A memory descriptor for it exists at */N/* a negative offset. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pra 2gma __nomember_alignment#endiftypedef struct _config_table {#pragma __nomember_alignmentN CONFIG_HEADER config_table$r_header; /* Hardware ID mask header */U IOGEN_CFG_TBL config_table$r_entries; /* Configuration entry array starts here */ } CONFIG_TABLE;N/* */Q/* The config_mem structure contains the memory prefix description. Normally */R/* this is only use by the allocation and deallocation 3routines, and the table */N/* consumers see only the config_table or iogen_cfg_tbl structures. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _config_mem {#pragma __nomember_alignmentN CONFIG_MEMDSC config_mem$r_memdsc; /* Memory descriptor 4 */N CONFIG_HEADER config_mem$r_header; /* Hardware ID mask prefix */N IOGEN_CFG_TBL config_mem$r_entries; /* Configuration array */ } CONFIG_MEM; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard "#endif /* __CONF 5IG_TABLE_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. 6 **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 7 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */I/* Source: 21-JUL-1993 13:29:52 $1$DGA8345:[LIB_H.SRC]COREIODEF.SDL;1 */ 8/********************************************************************************************************************************//*** MODULE $COREIODEF ***/#ifndef __COREIODEF_LOADED#define __COREIODEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the pre9viously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union :union#else#define __union variant_union#endif#endif &#define COREIO$M_LDP_DMA_PA_LO 0xFFFE0)#define COREIO$M_LDP_DMA_PA_HI 0xFFF00000+#define COREIO$M_SCOMM_TR_DMA_PA 0xFFFFFFE0+#define COREIO$M_SCOMM_RC_DMA_PA 0xFFFFFFE0-#define COREIO$M_PRINTER_TR_DMA_PA 0xFFFFFFE0-#define COREIO$M_PRINTER_RC_DMA_PA 0xFFFFFFE0*#define COREIO$M_ISDN_TR_DMA_PA 0xFFFFFFE0.#define COREIO$M_ISDN_TR_BUF_DMA_PA 0xFFFFFFE0*#define COREIO$M_ISDN_RC_DMA_PA 0xFFFFFFE0.#define COREIO$M_ISDN_RC_BUF_D;MA_PA 0xFFFFFFE0#define COREIO$M_SSR_GPO_0 0x1#define COREIO$M_SSR_GPO_1 0x2#define COREIO$M_SSR_GPO_2 0x4#define COREIO$M_SSR_GPO_3 0x8#define COREIO$M_SSR_GPO_4 0x10#define COREIO$M_SSR_GPO_5 0x20#define COREIO$M_SSR_GPO_6 0x40#define COREIO$M_SSR_GPO_7 0x80 #define COREIO$M_SSR_GPO_8 0x100 #define COREIO$M_SSR_GPO_9 0x200!#define COREIO$M_SSR_GPO_10 0x400!#define COREIO$M_SSR_GPO_11 0x800"#define COREIO$M_SSR_GPO_12 0x1000"#define COREIO$M_SSR_GPO_13 0x2000"#define CORE <IO$M_SSR_GPO_14 0x4000"#define COREIO$M_SSR_GPO_15 0x8000)#define COREIO$M_SSR_LANCE_DMA_EN 0x10000(#define COREIO$M_SSR_SCSI_DMA_EN 0x20000)#define COREIO$M_SSR_SCSI_DMA_DIR 0x40000(#define COREIO$M_SSR_ISDN_RCV_EN 0x80000(#define COREIO$M_SSR_ISDN_TR_EN 0x100000+#define COREIO$M_SSR_FLOPPY_DMA_EN 0x200000,#define COREIO$M_SSR_FLOPPY_DMA_DIR 0x400000.#define COREIO$M_SSR_SCC1_RC_DMA_EN 0x10000000.#define COREIO$M_SSR_SCC1_TR_DMA_EN 0x20000000.#define COREIO$M_SSR_SCC0_RC_DMA_EN 0x400000=00.#define COREIO$M_SSR_SCC0_TR_DMA_EN 0x80000000#define COREIO$M_SSR_LEDS 0xFF&#define COREIO$M_SSR_LANCE_RESET 0x100$#define COREIO$M_SSR_RTC_RESET 0x400$#define COREIO$M_SSR_SSC_RESET 0x800&#define COREIO$M_SSR_ISDN_RESET 0x1000'#define COREIO$M_SSR_10BASET_SEL 0x2000'#define COREIO$M_SSR_NI_LOOPBACK 0x4000!#define COREIO$M_SSR_TXDIS 0x8000+#define COREIO$M_SSR_ISDN_RC_DMA_EN 0x80000,#define COREIO$M_SSR_ISDN_TR_DMA_EN 0x1000001#define COREIO$M_SSR_PRINTER_RC_DMA_EN 0x100000001#d >efine COREIO$M_SSR_PRINTER_TR_DMA_EN 0x20000000.#define COREIO$M_SSR_COMM_RC_DMA_EN 0x40000000.#define COREIO$M_SSR_COMM_TR_DMA_EN 0x80000000 #define COREIO$M_SSR_IO_MASK 0xF$#define COREIO$M_SSR_IO_MASK_EN 0x10#define COREIO$M_SSR_FPE 0x80##define COREIO$M_SSR_SMR0 0x1000000##define COREIO$M_SSR_SMR1 0x2000000##define COREIO$M_SSR_SMRA 0x4000000(#define COREIO$M_SSR_FAST_MODE 0x8000000-#define COREIO$M_SSR_KBD_RC_DMA_EN 0x10000000-#define COREIO$M_SSR_KBD_TR_DMA_EN 0x20000000l#def ?ine COREIO$C_SIR 544 /* A constant for C programmers - defines offset of SIR structure */!#define COREIO$M_SIR_GP_INT_0 0x1!#define COREIO$M_SIR_GP_INT_1 0x2!#define COREIO$M_SIR_GP_INT_2 0x4!#define COREIO$M_SIR_GP_INT_3 0x8"#define COREIO$M_SIR_GP_INT_4 0x10"#define COREIO$M_SIR_GP_INT_5 0x20"#define COREIO$M_SIR_GP_INT_6 0x40"#define COREIO$M_SIR_GP_INT_7 0x80##define COREIO$M_SIR_GP_INT_8 0x100##define COREIO$M_SIR_GP_INT_9 0x200$#define COREIO$M_SIR_GP_INT_10 0x400 @$#define COREIO$M_SIR_GP_INT_11 0x800%#define COREIO$M_SIR_GP_INT_12 0x1000%#define COREIO$M_SIR_GP_INT_13 0x2000%#define COREIO$M_SIR_GP_INT_14 0x4000%#define COREIO$M_SIR_GP_INT_15 0x8000)#define COREIO$M_SIR_LANCE_DMA_ER 0x10000)#define COREIO$M_SIR_SCSI_DMA_MRE 0x20000(#define COREIO$M_SIR_SCSI_DMA_OV 0x40000)#define COREIO$M_SIR_SCSI_DMA_PTR 0x80000*#define COREIO$M_SIR_ISDN_DMA_MRE 0x100000.#define COREIO$M_SIR_ISDN_DMA_RC_INTR 0x200000.#define COREIO$M_SIR_ISDN_DMA_TR_INTR 0x A400000,#define COREIO$M_SIR_FLOPPY_DMA_INT 0x800000*#define COREIO$M_SIR_SCC1_DMA_OV 0x1000000+#define COREIO$M_SIR_SCC1_RCV_INT 0x2000000-#define COREIO$M_SIR_SCC1_TR_DMA_ME 0x4000000*#define COREIO$M_SIR_SCC1_TR_INT 0x8000000+#define COREIO$M_SIR_SCC0_DMA_OV 0x10000000,#define COREIO$M_SIR_SCC0_RCV_INT 0x20000000.#define COREIO$M_SIR_SCC0_TR_DMA_ME 0x40000000+#define COREIO$M_SIR_SCC0_TR_INT 0x80000000#define COREIO$M_SIR_HALT0 0x1#define COREIO$M_SIR_HALT1 0x2$#define COREIO$M_SIR B_ALT_CONSOLE 0x8!#define COREIO$M_SIR_SCC0_SI 0x40!#define COREIO$M_SIR_SCC1_SI 0x80"#define COREIO$M_SIR_NI_INTR 0x100%#define COREIO$M_SIR_ISDN_INTR 0x2000)#define COREIO$M_SIR_LANCE_DMA_RE 0x10000,#define COREIO$M_SIR_PP_RC_DMA_OVR 0x1000000,#define COREIO$M_SIR_PP_RC_HP_INTR 0x2000000,#define COREIO$M_SIR_PP_TR_DMA_MRE 0x4000000,#define COREIO$M_SIR_PP_TR_PE_INTR 0x8000000/#define COREIO$M_SIR_COMM_RC_DMA_OVR 0x10000000/#define COREIO$M_SIR_COMM_RC_HP_INTR 0x20000000/#define CORE CIO$M_SIR_COMM_TR_DMA_MRE 0x40000000/#define COREIO$M_SIR_COMM_TR_PE_INTR 0x80000000!#define COREIO$M_SIR_TC_SLOT0 0x4!#define COREIO$M_SIR_TC_SLOT1 0x8"#define COREIO$M_SIR_SCC0_INT 0x40"#define COREIO$M_SIR_SCC1_INT 0x80$#define COREIO$M_SIR_LANCE_INT 0x100$#define COREIO$M_SIR_ISDN_INT 0x2000$#define COREIO$M_SIR_CONS_SEL 0x8000m#define COREIO$C_SIMR 576 /* A constant for C programmers - defines offset of SIMR structure */"#define COREIO$M_SIMR_GP_INT_0 0x1"#define COREDIO$M_SIMR_GP_INT_1 0x2"#define COREIO$M_SIMR_GP_INT_2 0x4"#define COREIO$M_SIMR_GP_INT_3 0x8##define COREIO$M_SIMR_GP_INT_4 0x10##define COREIO$M_SIMR_GP_INT_5 0x20##define COREIO$M_SIMR_GP_INT_6 0x40##define COREIO$M_SIMR_GP_INT_7 0x80$#define COREIO$M_SIMR_GP_INT_8 0x100$#define COREIO$M_SIMR_GP_INT_9 0x200%#define COREIO$M_SIMR_GP_INT_10 0x400%#define COREIO$M_SIMR_GP_INT_11 0x800&#define COREIO$M_SIMR_GP_INT_12 0x1000&#define COREIO$M_SIMR_GP_INT_13 0x2000&#define COREIO$M_SIMR_ EGP_INT_14 0x4000&#define COREIO$M_SIMR_GP_INT_15 0x8000*#define COREIO$M_SIMR_LANCE_DMA_ER 0x10000*#define COREIO$M_SIMR_SCSI_DMA_MRE 0x20000)#define COREIO$M_SIMR_SCSI_DMA_OV 0x40000*#define COREIO$M_SIMR_SCSI_DMA_PTR 0x80000+#define COREIO$M_SIMR_ISDN_DMA_MRE 0x100000/#define COREIO$M_SIMR_ISDN_DMA_RC_INTR 0x200000/#define COREIO$M_SIMR_ISDN_DMA_TR_INTR 0x400000-#define COREIO$M_SIMR_FLOPPY_DMA_INT 0x800000+#define COREIO$M_SIMR_SCC1_DMA_OV 0x1000000,#define COREIO$M_SIMR_SCC1_RCV_I FNT 0x2000000.#define COREIO$M_SIMR_SCC1_TR_DMA_ME 0x4000000+#define COREIO$M_SIMR_SCC1_TR_INT 0x8000000,#define COREIO$M_SIMR_SCC0_DMA_OV 0x10000000-#define COREIO$M_SIMR_SCC0_RCV_INT 0x20000000/#define COREIO$M_SIMR_SCC0_TR_DMA_ME 0x40000000,#define COREIO$M_SIMR_SCC0_TR_INT 0x80000000#define COREIO$M_SIMR_HALT0 0x1#define COREIO$M_SIMR_HALT1 0x2%#define COREIO$M_SIMR_ALT_CONSOLE 0x8"#define COREIO$M_SIMR_SCC0_SI 0x40"#define COREIO$M_SIMR_SCC1_SI 0x80##define COREIO$M_SIMR_NI_INT GR 0x100&#define COREIO$M_SIMR_ISDN_INTR 0x2000*#define COREIO$M_SIMR_LANCE_DMA_RE 0x10000-#define COREIO$M_SIMR_PP_RC_DMA_OVR 0x1000000-#define COREIO$M_SIMR_PP_RC_HP_INTR 0x2000000-#define COREIO$M_SIMR_PP_TR_DMA_MRE 0x4000000-#define COREIO$M_SIMR_PP_TR_PE_INTR 0x80000000#define COREIO$M_SIMR_COMM_RC_DMA_OVR 0x100000000#define COREIO$M_SIMR_COMM_RC_HP_INTR 0x200000000#define COREIO$M_SIMR_COMM_TR_DMA_MRE 0x400000000#define COREIO$M_SIMR_COMM_TR_PE_INTR 0x80000000"#define COREIO$M_SIMHR_TC_SLOT0 0x4"#define COREIO$M_SIMR_TC_SLOT1 0x8##define COREIO$M_SIMR_SCC0_INT 0x40##define COREIO$M_SIMR_SCC1_INT 0x80%#define COREIO$M_SIMR_LANCE_INT 0x100%#define COREIO$M_SIMR_ISDN_INT 0x2000%#define COREIO$M_SIMR_CONS_SEL 0x8000'#define COREIO$M_SADR_TC_ADDR 0x1FFFFE0+#define COREIO$M_ISDN_DATA_TR_DATA 0xFFFFFF+#define COREIO$M_ISDN_DATA_RC_DATA 0xFFFFFF"#define COREIO$M_LANCE_SLOT_CS 0xF)#define COREIO$M_LANCE_SLOT_HW_ADDR 0x3F0!#define COREIO$M_SCC0_SLOT_CS 0xF(#define ICOREIO$M_SCC0_SLOT_HW_ADDR 0x3F0!#define COREIO$M_SCC1_SLOT_CS 0xF(#define COREIO$M_SCC1_SLOT_HW_ADDR 0x3F0g#define COREIO$C_ISDN_AUDIO 49152 /* A constant for C programmers - defines offset of ISDN CSR */N#define COREIO$Q_TC_NUMBER 1 /* High nibble of addr */N#define COREIO$Q_SLOT0_DENSE_BASE 0 /* base PA of TC slot 0 */N#define COREIO$Q_SLOT1_DENSE_BASE 536870912 /* base PA of TC slot 1 */N#define COREIO$Q_SLOT2_DENSE_BASE 1073741824 /* Jbase PA of TC slot 2 */N#define COREIO$Q_SLOT3_DENSE_BASE 1610612736 /* base PA of TC slot 3 */N#define COREIO$Q_SLOT4_DENSE_BASE -2147483648 /* base PA of TC slot 4 */N#define COREIO$Q_SLOT5_DENSE_BASE -1610612736 /* base PA of TC slot 5 */N#define COREIO$Q_LANCE_RAP 1572872 /* PA of LANCE RAP reg */N#define COREIO$Q_LANCE_RDP_DENSE 786432 /* PA of LANCE RDP reg */N#define COREIO$Q_NI_ADR_ROM_DENSE 524288 /* PA of NI ADR ROM K */N#define COREIO$Q_LDP_DENSE 262176 /* PA of LDP reg */N#define COREIO$Q_LANCE_SLOT 524992 /* PA of lance slot */N#define COREIO$Q_SSR 524800 /* SSR reg */N#define COREIO$Q_SIR 524832 /* SIR reg */N#define COREIO$Q_SIMR 524848 /* SIMR reg */U#define COREIO$S_COREIODEF 57344 /* Old COREIO size field for compatibility */ typedef Lstruct _coreio {N void *coreio$l_ioctl_csr; /* Core I/O base CSR address */( unsigned char coreio$b_fill560 [60]; __union {N unsigned int coreio$l_ldp; /* Ethernet Lance DMA pointer */ __struct {, unsigned coreio$v_ldp_fill1 : 5;1 unsigned coreio$v_ldp_dma_pa_lo : 15;1 unsigned coreio$v_ldp_dma_pa_hi : 12; } coreio$r_ldp_bits; } coreio$r_ldp_overlay;( unsigned char coreio$b_fil Ml570 [28]; __union {U unsigned int coreio$l_scomm_tr; /* Serial comm transmit port 1 DMA pointer */ __struct {1 unsigned coreio$v_scomm_tr_fill1 : 5;3 unsigned coreio$v_scomm_tr_dma_pa : 27;% } coreio$r_scomm_tr_bits;$ } coreio$r_scomm_tr_overlay;( unsigned char coreio$b_fill580 [28]; __union {T unsigned int coreio$l_scomm_rc; /* Serial comm receive port 1 DMA pointer */ __struct {1 unsign Ned coreio$v_scomm_rc_fill1 : 5;3 unsigned coreio$v_scomm_rc_dma_pa : 27;% } coreio$r_scomm_rc_bits;$ } coreio$r_scomm_rc_overlay;( unsigned char coreio$b_fill590 [28]; __union {Q unsigned int coreio$l_printer_tr; /* Printer transmit port DMA pointer */ __struct {3 unsigned coreio$v_printer_tr_fill1 : 5;5 unsigned coreio$v_printer_tr_dma_pa : 27;' } coreio$r_printer_tr_bits;& } coreio$r_print Oer_tr_overlay;( unsigned char coreio$b_fill600 [28]; __union {P unsigned int coreio$l_printer_rc; /* Printer receive port DMA pointer */ __struct {3 unsigned coreio$v_printer_rc_fill1 : 5;5 unsigned coreio$v_printer_rc_dma_pa : 27;' } coreio$r_printer_rc_bits;& } coreio$r_printer_rc_overlay;( unsigned char coreio$b_fill610 [60]; __union {N unsigned int coreio$l_isdn_tr; /* ISDN transmit DMA pointer */ P __struct {0 unsigned coreio$v_isdn_tr_fill1 : 5;2 unsigned coreio$v_isdn_tr_dma_pa : 27;$ } coreio$r_isdn_tr_bits;# } coreio$r_isdn_tr_overlay;( unsigned char coreio$b_fill620 [28]; __union {Q unsigned int coreio$l_isdn_tr_buf; /* ISDN transmit DMA buffer pointer */ __struct {4 unsigned coreio$v_isdn_tr_buf_fill1 : 5;6 unsigned coreio$v_isdn_tr_buf_dma_pa : 27;( } coreio$r_isdn_tr Q_buf_bits;' } coreio$r_isdn_tr_buf_overlay;( unsigned char coreio$b_fill630 [28]; __union {N unsigned int coreio$l_isdn_rc; /* ISDN receive DMA pointer */ __struct {0 unsigned coreio$v_isdn_rc_fill1 : 5;2 unsigned coreio$v_isdn_rc_dma_pa : 27;$ } coreio$r_isdn_rc_bits;# } coreio$r_isdn_rc_overlay;( unsigned char coreio$b_fill640 [28]; __union {Q unsigned int coreio$l_isdn_rc_buf; /* ISDN recei Rve DMA buffer pointer */ __struct {4 unsigned coreio$v_isdn_rc_buf_fill1 : 5;6 unsigned coreio$v_isdn_rc_buf_dma_pa : 27;( } coreio$r_isdn_rc_buf_bits;' } coreio$r_isdn_rc_buf_overlay;( unsigned char coreio$b_fill650 [28];N unsigned int coreio$l_data0; /* System Data Buffer 0 */( unsigned char coreio$b_fill660 [28];N unsigned int coreio$l_data1; /* System Data Buffer 1 */( unsigned char Scoreio$b_fill670 [28];N unsigned int coreio$l_data2; /* System Data Buffer 2 */( unsigned char coreio$b_fill680 [28];N unsigned int coreio$l_data3; /* System Data Buffer 3 */( unsigned char coreio$b_fill690 [28]; __union {N unsigned int coreio$l_ssr; /* System support register */ __struct {, unsigned coreio$v_ssr_gpo_0 : 1;, unsigned coreio$v_ssr_gpo_1 : 1;, unsigned coreio$ Tv_ssr_gpo_2 : 1;, unsigned coreio$v_ssr_gpo_3 : 1;, unsigned coreio$v_ssr_gpo_4 : 1;, unsigned coreio$v_ssr_gpo_5 : 1;, unsigned coreio$v_ssr_gpo_6 : 1;, unsigned coreio$v_ssr_gpo_7 : 1;, unsigned coreio$v_ssr_gpo_8 : 1;, unsigned coreio$v_ssr_gpo_9 : 1;- unsigned coreio$v_ssr_gpo_10 : 1;- unsigned coreio$v_ssr_gpo_11 : 1;- unsigned coreio$v_ssr_gpo_12 : 1;- unsigned c Uoreio$v_ssr_gpo_13 : 1;- unsigned coreio$v_ssr_gpo_14 : 1;- unsigned coreio$v_ssr_gpo_15 : 1;3 unsigned coreio$v_ssr_lance_dma_en : 1;2 unsigned coreio$v_ssr_scsi_dma_en : 1;3 unsigned coreio$v_ssr_scsi_dma_dir : 1;2 unsigned coreio$v_ssr_isdn_rcv_en : 1;1 unsigned coreio$v_ssr_isdn_tr_en : 1;4 unsigned coreio$v_ssr_floppy_dma_en : 1;5 unsigned coreio$v_ssr_floppy_dma_dir : 1;, V unsigned coreio$v_ssr_fill5 : 5;5 unsigned coreio$v_ssr_scc1_rc_dma_en : 1;5 unsigned coreio$v_ssr_scc1_tr_dma_en : 1;5 unsigned coreio$v_ssr_scc0_rc_dma_en : 1;5 unsigned coreio$v_ssr_scc0_tr_dma_en : 1; } coreio$r_ssr_bits;N __struct { /* Flamingo specific bits */+ unsigned coreio$v_ssr_leds : 8;2 unsigned coreio$v_ssr_lance_reset : 1;0 unsigned coreio$v_ssr_ Wfill_04_1 : 1;0 unsigned coreio$v_ssr_rtc_reset : 1;0 unsigned coreio$v_ssr_ssc_reset : 1;1 unsigned coreio$v_ssr_isdn_reset : 1;2 unsigned coreio$v_ssr_10baset_sel : 1;2 unsigned coreio$v_ssr_ni_loopback : 1;, unsigned coreio$v_ssr_txdis : 1;0 unsigned coreio$v_ssr_fill_04_3 : 3;5 unsigned coreio$v_ssr_isdn_rc_dma_en : 1;5 unsigned coreio$v_ssr_isdn_tr_dma_en : 1;0 unsigned corei Xo$v_ssr_fill_04_4 : 2;0 unsigned coreio$v_ssr_fill_04_5 : 5;8 unsigned coreio$v_ssr_printer_rc_dma_en : 1;8 unsigned coreio$v_ssr_printer_tr_dma_en : 1;5 unsigned coreio$v_ssr_comm_rc_dma_en : 1;5 unsigned coreio$v_ssr_comm_tr_dma_en : 1;# } coreio$r_ssr_04_bits;N __struct { /* Pelican specific bits */. unsigned coreio$v_ssr_io_mask : 4;1 unsigned coreio$v_ssr_io_m Yask_en : 1;1 unsigned coreio$v_ssr_sys_ok_led : 1;0 unsigned coreio$v_ssr_fill_07_1 : 1;* unsigned coreio$v_ssr_fpe : 1;1 unsigned coreio$v_ssr_fill_07_3 : 16;+ unsigned coreio$v_ssr_smr0 : 1;+ unsigned coreio$v_ssr_smr1 : 1;+ unsigned coreio$v_ssr_smra : 1;0 unsigned coreio$v_ssr_fast_mode : 1;4 unsigned coreio$v_ssr_kbd_rc_dma_en : 1;4 unsigned coreio$v_ssr_kbd_tr_dma_en : 1; Z0 unsigned coreio$v_ssr_fill_07_4 : 2;# } coreio$r_ssr_07_bits; } coreio$r_ssr_overlay;( unsigned char coreio$b_fill700 [28]; __union {N unsigned int coreio$l_sir; /* System interrupt register */ __struct {/ unsigned coreio$v_sir_gp_int_0 : 1;/ unsigned coreio$v_sir_gp_int_1 : 1;/ unsigned coreio$v_sir_gp_int_2 : 1;/ unsigned coreio$v_sir_gp_int_3 : 1;/ unsigned c [oreio$v_sir_gp_int_4 : 1;/ unsigned coreio$v_sir_gp_int_5 : 1;/ unsigned coreio$v_sir_gp_int_6 : 1;/ unsigned coreio$v_sir_gp_int_7 : 1;/ unsigned coreio$v_sir_gp_int_8 : 1;/ unsigned coreio$v_sir_gp_int_9 : 1;0 unsigned coreio$v_sir_gp_int_10 : 1;0 unsigned coreio$v_sir_gp_int_11 : 1;0 unsigned coreio$v_sir_gp_int_12 : 1;0 unsigned coreio$v_sir_gp_int_13 : 1;0 unsigned coreio$ \v_sir_gp_int_14 : 1;0 unsigned coreio$v_sir_gp_int_15 : 1;3 unsigned coreio$v_sir_lance_dma_er : 1;3 unsigned coreio$v_sir_scsi_dma_mre : 1;2 unsigned coreio$v_sir_scsi_dma_ov : 1;3 unsigned coreio$v_sir_scsi_dma_ptr : 1;3 unsigned coreio$v_sir_isdn_dma_mre : 1;7 unsigned coreio$v_sir_isdn_dma_rc_intr : 1;7 unsigned coreio$v_sir_isdn_dma_tr_intr : 1;5 unsigned coreio$v_sir_floppy_dma_int : ] 1;2 unsigned coreio$v_sir_scc1_dma_ov : 1;3 unsigned coreio$v_sir_scc1_rcv_int : 1;5 unsigned coreio$v_sir_scc1_tr_dma_me : 1;2 unsigned coreio$v_sir_scc1_tr_int : 1;2 unsigned coreio$v_sir_scc0_dma_ov : 1;3 unsigned coreio$v_sir_scc0_rcv_int : 1;5 unsigned coreio$v_sir_scc0_tr_dma_me : 1;2 unsigned coreio$v_sir_scc0_tr_int : 1; } coreio$r_sir_bits;N __struct { ^ /* Flamingo specific bits */, unsigned coreio$v_sir_halt0 : 1;, unsigned coreio$v_sir_halt1 : 1;0 unsigned coreio$v_sir_fill_04_1 : 1;2 unsigned coreio$v_sir_alt_console : 1;0 unsigned coreio$v_sir_fill_04_2 : 2;. unsigned coreio$v_sir_scc0_si : 1;. unsigned coreio$v_sir_scc1_si : 1;. unsigned coreio$v_sir_ni_intr : 1;0 unsigned coreio$v_sir_fill_04_3 : 4;0 unsigned corei _o$v_sir_isdn_intr : 1;0 unsigned coreio$v_sir_fill_04_4 : 2;3 unsigned coreio$v_sir_lance_dma_re : 1;0 unsigned coreio$v_sir_fill_04_5 : 7;4 unsigned coreio$v_sir_pp_rc_dma_ovr : 1;4 unsigned coreio$v_sir_pp_rc_hp_intr : 1;4 unsigned coreio$v_sir_pp_tr_dma_mre : 1;4 unsigned coreio$v_sir_pp_tr_pe_intr : 1;6 unsigned coreio$v_sir_comm_rc_dma_ovr : 1;6 unsigned coreio$v_sir_comm_rc_hp_intr : 1;6 ` unsigned coreio$v_sir_comm_tr_dma_mre : 1;6 unsigned coreio$v_sir_comm_tr_pe_intr : 1;# } coreio$r_sir_04_bits;N __struct { /* Pelican specific bits */0 unsigned coreio$v_sir_fill_07_1 : 2;/ unsigned coreio$v_sir_tc_slot0 : 1;/ unsigned coreio$v_sir_tc_slot1 : 1;1 unsigned coreio$v_sir_fill_07_1a : 2;/ unsigned coreio$v_sir_scc0_int : 1;/ unsigned cor aeio$v_sir_scc1_int : 1;0 unsigned coreio$v_sir_lance_int : 1;0 unsigned coreio$v_sir_fill_07_2 : 4;/ unsigned coreio$v_sir_isdn_int : 1;0 unsigned coreio$v_sir_fill_07_3 : 1;/ unsigned coreio$v_sir_cons_sel : 1;1 unsigned coreio$v_sir_fill_07_4 : 16;$ } coreio$r_sir_07__bits; } coreio$r_sir_overlay;( unsigned char coreio$b_fill710 [28]; __union {N unsigned int coreio$l_simr; /* Syste bm interrupt mask register */ __struct {0 unsigned coreio$v_simr_gp_int_0 : 1;0 unsigned coreio$v_simr_gp_int_1 : 1;0 unsigned coreio$v_simr_gp_int_2 : 1;0 unsigned coreio$v_simr_gp_int_3 : 1;0 unsigned coreio$v_simr_gp_int_4 : 1;0 unsigned coreio$v_simr_gp_int_5 : 1;0 unsigned coreio$v_simr_gp_int_6 : 1;0 unsigned coreio$v_simr_gp_int_7 : 1;0 unsigned coreio$v_simr_gp_int_8 : 1;0 c unsigned coreio$v_simr_gp_int_9 : 1;1 unsigned coreio$v_simr_gp_int_10 : 1;1 unsigned coreio$v_simr_gp_int_11 : 1;1 unsigned coreio$v_simr_gp_int_12 : 1;1 unsigned coreio$v_simr_gp_int_13 : 1;1 unsigned coreio$v_simr_gp_int_14 : 1;1 unsigned coreio$v_simr_gp_int_15 : 1;4 unsigned coreio$v_simr_lance_dma_er : 1;4 unsigned coreio$v_simr_scsi_dma_mre : 1;3 unsigned coreio$v_simr_scs di_dma_ov : 1;4 unsigned coreio$v_simr_scsi_dma_ptr : 1;4 unsigned coreio$v_simr_isdn_dma_mre : 1;8 unsigned coreio$v_simr_isdn_dma_rc_intr : 1;8 unsigned coreio$v_simr_isdn_dma_tr_intr : 1;6 unsigned coreio$v_simr_floppy_dma_int : 1;3 unsigned coreio$v_simr_scc1_dma_ov : 1;4 unsigned coreio$v_simr_scc1_rcv_int : 1;6 unsigned coreio$v_simr_scc1_tr_dma_me : 1;3 unsigned coreio$v_simr_scc1_tr_int e : 1;3 unsigned coreio$v_simr_scc0_dma_ov : 1;4 unsigned coreio$v_simr_scc0_rcv_int : 1;6 unsigned coreio$v_simr_scc0_tr_dma_me : 1;3 unsigned coreio$v_simr_scc0_tr_int : 1;! } coreio$r_simr_bits;N __struct { /* Flamingo specific bits */- unsigned coreio$v_simr_halt0 : 1;- unsigned coreio$v_simr_halt1 : 1;1 unsigned coreio$v_simr_fill_04_1 : 1;3 unsi fgned coreio$v_simr_alt_console : 1;1 unsigned coreio$v_simr_fill_04_2 : 2;/ unsigned coreio$v_simr_scc0_si : 1;/ unsigned coreio$v_simr_scc1_si : 1;/ unsigned coreio$v_simr_ni_intr : 1;1 unsigned coreio$v_simr_fill_04_3 : 4;1 unsigned coreio$v_simr_isdn_intr : 1;1 unsigned coreio$v_simr_fill_04_4 : 2;4 unsigned coreio$v_simr_lance_dma_re : 1;1 unsigned coreio$v_simr_fill_04_5 : 7;5 g unsigned coreio$v_simr_pp_rc_dma_ovr : 1;5 unsigned coreio$v_simr_pp_rc_hp_intr : 1;5 unsigned coreio$v_simr_pp_tr_dma_mre : 1;5 unsigned coreio$v_simr_pp_tr_pe_intr : 1;7 unsigned coreio$v_simr_comm_rc_dma_ovr : 1;7 unsigned coreio$v_simr_comm_rc_hp_intr : 1;7 unsigned coreio$v_simr_comm_tr_dma_mre : 1;7 unsigned coreio$v_simr_comm_tr_pe_intr : 1;$ } coreio$r_simr_04_bits;N __struct h { /* Pelican specific bits */1 unsigned coreio$v_simr_fill_07_1 : 2;0 unsigned coreio$v_simr_tc_slot0 : 1;0 unsigned coreio$v_simr_tc_slot1 : 1;2 unsigned coreio$v_simr_fill_07_1a : 2;0 unsigned coreio$v_simr_scc0_int : 1;0 unsigned coreio$v_simr_scc1_int : 1;1 unsigned coreio$v_simr_lance_int : 1;1 unsigned coreio$v_simr_fill_07_2 : 4;0 unsigned coreio$v_simr i_isdn_int : 1;1 unsigned coreio$v_simr_fill_07_3 : 1;0 unsigned coreio$v_simr_cons_sel : 1;2 unsigned coreio$v_simr_fill_07_4 : 16;% } coreio$r_simr_07__bits; } coreio$r_simr_overlay;( unsigned char coreio$b_fill720 [28]; __union {N unsigned int coreio$l_sadr; /* System address register */ __struct {- unsigned coreio$v_sadr_fill1 : 5;0 unsigned coreio$v_sadr_tc_addr : 20;- j unsigned coreio$v_sadr_fill2 : 7;! } coreio$r_sadr_bits; } coreio$r_sadr_overlay;( unsigned char coreio$b_fill730 [28]; __union {N unsigned int coreio$l_isdn_data_tr; /* ISDN Data Transmit */ __struct {5 unsigned coreio$v_isdn_data_tr_data : 24;4 unsigned coreio$v_isdn_data_tr_fill : 8;) } coreio$r_isdn_data_tr_bits;( } coreio$r_isdn_data_tr_overlay;( unsigned char coreio$b_fill740 [ k28]; __union {N unsigned int coreio$l_isdn_data_rc; /* ISDN Data Receive */ __struct {5 unsigned coreio$v_isdn_data_rc_data : 24;4 unsigned coreio$v_isdn_data_rc_fill : 8;) } coreio$r_isdn_data_rc_bits;( } coreio$r_isdn_data_rc_overlay;( unsigned char coreio$b_fill750 [28]; __union {N unsigned int coreio$l_lance_slot; /* Lance slot register */ __struct {0 unsigned corei lo$v_lance_slot_cs : 4;5 unsigned coreio$v_lance_slot_hw_addr : 6;3 unsigned coreio$v_lance_slot_fill : 22;' } coreio$r_lance_slot_bits;& } coreio$r_lance_slot_overlay;( unsigned char coreio$b_fill760 [60]; __union {N unsigned int coreio$l_scc0_slot; /* SCC0 slot register */ __struct {/ unsigned coreio$v_scc0_slot_cs : 4;4 unsigned coreio$v_scc0_slot_hw_addr : 6;2 unsigned corei mo$v_scc0_slot_fill : 22;& } coreio$r_scc0_slot_bits;% } coreio$r_scc0_slot_overlay;( unsigned char coreio$b_fill770 [28]; __union {N unsigned int coreio$l_scc1_slot; /* SCC1 slot register */ __struct {/ unsigned coreio$v_scc1_slot_cs : 4;4 unsigned coreio$v_scc1_slot_hw_addr : 6;2 unsigned coreio$v_scc1_slot_fill : 22;& } coreio$r_scc1_slot_bits;% } coreio$r_scc1_slot_overlay;* nunsigned char coreio$b_fill780 [7388];N unsigned int coreio$l_ni_adr_rom; /* Ethernet address ROM */* unsigned char coreio$b_fill790 [8188];N unsigned int coreio$l_lance_rdp; /* Lance ethernet CSR */R unsigned char coreio$b_fill800 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_lance_rap; /* Lance ethernet CSR */* unsigned char coreio$b_fill810 [8180];N unsigned int coreio$l_scc0b_comm_rap; /* Comm Porto 1 RAP */R unsigned char coreio$b_fill820 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_scc0b_comm_data; /* Comm Port 1 data */R unsigned char coreio$b_fill830 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_scc0a_mouse_rap; /* Mouse RAP */R unsigned char coreio$b_fill840 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_scc0a_mouse_data; /* Mouse port data regispter */* unsigned char coreio$b_fill850 [8164];N unsigned int coreio$l_scc1b_print_rap; /* Printer Port 2 RAP */R unsigned char coreio$b_fill860 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_scc1b_print_data; /* Printer Port 2 data */R unsigned char coreio$b_fill870 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_scc1a_key_rap; /* Keyboard RAP */R unsigned char coreio$b_fill880 [4]; /*q Fill to allow sparse space byte mask */N unsigned int coreio$l_scc1a_key_data; /* Keyboard port data register */* unsigned char coreio$b_fill890 [8164];N unsigned int coreio$l_rtc_sec; /* TOY clock CSR--seconds */R unsigned char coreio$b_fill900 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_alms; /* TOY clock CSR--seconds alarm */R unsigned char coreio$b_fill910 [4]; /* Fill to allow sparse space byte mask */N unsignedr int coreio$l_rtc_min; /* TOY clock CSR--minutes */R unsigned char coreio$b_fill920 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_almn; /* TOY clock CSR--minutes alarm */R unsigned char coreio$b_fill930 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_hour; /* TOY clock CSR--hours */R unsigned char coreio$b_fill940 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_srtc_almh; /* TOY clock CSR--hours alarm */R unsigned char coreio$b_fill950 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_dow; /* TOY clock CSR--day of week */R unsigned char coreio$b_fill960 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_day; /* TOY clock CSR--date of month */R unsigned char coreio$b_fill970 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_mon; t/* TOY clock CSR--month */R unsigned char coreio$b_fill980 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_year; /* TOY clock CSR--year */R unsigned char coreio$b_fill990 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_rega; /* TOY clock CSR--register A */S unsigned char coreio$b_fill1000 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_regb; /* TOY clocku CSR--register B */S unsigned char coreio$b_fill1010 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_regc; /* TOY clock CSR--register C */S unsigned char coreio$b_fill1020 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_regd; /* TOY clock CSR--register D */S unsigned char coreio$b_fill1030 [4]; /* Fill to allow sparse space byte mask */N unsigned int coreio$l_rtc_ram; /* TOY clock CSR--ba vse of BBU RAM */+ unsigned char coreio$b_fill1040 [8076];N unsigned int coreio$l_isdn_audio; /* ISDN audio chip CSR */+ unsigned char coreio$b_fill1050 [8188]; } COREIO; #if !defined(__VAXC)6#define coreio$l_ldp coreio$r_ldp_overlay.coreio$l_ldp\#define coreio$v_ldp_dma_pa_lo coreio$r_ldp_overlay.coreio$r_ldp_bits.coreio$v_ldp_dma_pa_lo\#define coreio$v_ldp_dma_pa_hi coreio$r_ldp_overlay.coreio$r_ldp_bits.coreio$v_ldp_dma_pa_hiE#define coreio$l_scomm_tr cowreio$r_scomm_tr_overlay.coreio$l_scomm_trj#define coreio$v_scomm_tr_dma_pa coreio$r_scomm_tr_overlay.coreio$r_scomm_tr_bits.coreio$v_scomm_tr_dma_paE#define coreio$l_scomm_rc coreio$r_scomm_rc_overlay.coreio$l_scomm_rcj#define coreio$v_scomm_rc_dma_pa coreio$r_scomm_rc_overlay.coreio$r_scomm_rc_bits.coreio$v_scomm_rc_dma_paK#define coreio$l_printer_tr coreio$r_printer_tr_overlay.coreio$l_printer_trr#define coreio$v_printer_tr_dma_pa coreio$r_printer_tr_overlay.coreio$r_printer_tr_bits.coreio$vx_printer_tr_dma_paK#define coreio$l_printer_rc coreio$r_printer_rc_overlay.coreio$l_printer_rcr#define coreio$v_printer_rc_dma_pa coreio$r_printer_rc_overlay.coreio$r_printer_rc_bits.coreio$v_printer_rc_dma_paB#define coreio$l_isdn_tr coreio$r_isdn_tr_overlay.coreio$l_isdn_trf#define coreio$v_isdn_tr_dma_pa coreio$r_isdn_tr_overlay.coreio$r_isdn_tr_bits.coreio$v_isdn_tr_dma_paN#define coreio$l_isdn_tr_buf coreio$r_isdn_tr_buf_overlay.coreio$l_isdn_tr_bufv#define coreio$v_isdn_tr_buf_dma_pa coreyio$r_isdn_tr_buf_overlay.coreio$r_isdn_tr_buf_bits.coreio$v_isdn_tr_buf_dma_paB#define coreio$l_isdn_rc coreio$r_isdn_rc_overlay.coreio$l_isdn_rcf#define coreio$v_isdn_rc_dma_pa coreio$r_isdn_rc_overlay.coreio$r_isdn_rc_bits.coreio$v_isdn_rc_dma_paN#define coreio$l_isdn_rc_buf coreio$r_isdn_rc_buf_overlay.coreio$l_isdn_rc_bufv#define coreio$v_isdn_rc_buf_dma_pa coreio$r_isdn_rc_buf_overlay.coreio$r_isdn_rc_buf_bits.coreio$v_isdn_rc_buf_dma_pa6#define coreio$l_ssr coreio$r_ssr_overlay.coreio$l_ssrzT#define coreio$v_ssr_gpo_0 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_0T#define coreio$v_ssr_gpo_1 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_1T#define coreio$v_ssr_gpo_2 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_2T#define coreio$v_ssr_gpo_3 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_3T#define coreio$v_ssr_gpo_4 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_4T#define coreio$v_ssr_gpo_5 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v{_ssr_gpo_5T#define coreio$v_ssr_gpo_6 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_6T#define coreio$v_ssr_gpo_7 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_7T#define coreio$v_ssr_gpo_8 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_8T#define coreio$v_ssr_gpo_9 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_9V#define coreio$v_ssr_gpo_10 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_10V#define coreio$v_ssr_gpo_11 coreio$r_ssr_overlay.coreio$r_ssr_|bits.coreio$v_ssr_gpo_11V#define coreio$v_ssr_gpo_12 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_12V#define coreio$v_ssr_gpo_13 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_13V#define coreio$v_ssr_gpo_14 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_14V#define coreio$v_ssr_gpo_15 coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_gpo_15b#define coreio$v_ssr_lance_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_lance_dma_en`#define coreio$v_ssr_scsi_dm}a_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scsi_dma_enb#define coreio$v_ssr_scsi_dma_dir coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scsi_dma_dir`#define coreio$v_ssr_isdn_rcv_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_isdn_rcv_en^#define coreio$v_ssr_isdn_tr_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_isdn_tr_end#define coreio$v_ssr_floppy_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_floppy_dma_enf#define coreio$v_ssr_floppy_dma_dir core~io$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_floppy_dma_dirf#define coreio$v_ssr_scc1_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scc1_rc_dma_enf#define coreio$v_ssr_scc1_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scc1_tr_dma_enf#define coreio$v_ssr_scc0_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scc0_rc_dma_enf#define coreio$v_ssr_scc0_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_bits.coreio$v_ssr_scc0_tr_dma_enU#define coreio$v_ssr_leds coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_ledsc#define coreio$v_ssr_lance_reset coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_lance_reset_#define coreio$v_ssr_rtc_reset coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_rtc_reset_#define coreio$v_ssr_ssc_reset coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_ssc_reseta#define coreio$v_ssr_isdn_reset coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_isdn_resetc#define coreio$v_ssr_10baset_sel coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_10baset_selc#define coreio$v_ssr_ni_loopback coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_ni_loopbackW#define coreio$v_ssr_txdis coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_txdisi#define coreio$v_ssr_isdn_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_isdn_rc_dma_eni#define coreio$v_ssr_isdn_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_isdn_tr_dma_eno#define coreio$v_ssr_printer_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_printer_rc_dma_eno#define coreio$v_ssr_printer_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_printer_tr_dma_eni#define coreio$v_ssr_comm_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_comm_rc_dma_eni#define coreio$v_ssr_comm_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_04_bits.coreio$v_ssr_comm_tr_dma_en[#define coreio$v_ssr_io_mask coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_io_maska#define coreio$v_ssr_io_mask_en coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_io_mask_enS#define coreio$v_ssr_fpe coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_fpeU#define coreio$v_ssr_smr0 coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_smr0U#define coreio$v_ssr_smr1 coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_smr1U#define coreio$v_ssr_smra coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_smra_#define coreio$v_ssr_fast_mode coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_fast_modeg#define coreio$v_ssr_kbd_rc_dma_en coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_kbd_rc_dma_eng#define coreio$v_ssr_kbd_tr_dma_en coreio$r_ssr_overlay.coreio$r_ssr_07_bits.coreio$v_ssr_kbd_tr_dma_en6#define coreio$l_sir coreio$r_sir_overlay.coreio$l_sirZ#define coreio$v_sir_gp_int_0 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_0Z#define coreio$v_sir_gp_int_1 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_1Z#define coreio$v_sir_gp_int_2 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_2Z#define coreio$v_sir_gp_int_3 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_3Z#define coreio$v_sir_gp_int_4 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_4Z#define coreio$v_sir_gp_int_5 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_5Z#define coreio$v_sir_gp_int_6 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_6Z#define coreio$v_sir_gp_int_7 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_7Z#define coreio$v_sir_gp_int_8 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_8Z#define coreio$v_sir_gp_int_9 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_9\#define coreio$v_sir_gp_int_10 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_10\#define coreio$v_sir_gp_int_11 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_11\#define coreio$v_sir_gp_int_12 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_12\#define coreio$v_sir_gp_int_13 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_13\#define coreio$v_sir_gp_int_14 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_14\#define coreio$v_sir_gp_int_15 coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_gp_int_15b#define coreio$v_sir_lance_dma_er coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_lance_dma_erb#define coreio$v_sir_scsi_dma_mre coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scsi_dma_mre`#define coreio$v_sir_scsi_dma_ov coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scsi_dma_ovb#define coreio$v_sir_scsi_dma_ptr coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scsi_dma_ptrb#define coreio$v_sir_isdn_dma_mre coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_isdn_dma_mrej#define coreio$v_sir_isdn_dma_rc_intr coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_isdn_dma_rc_intrj#define coreio$v_sir_isdn_dma_tr_intr coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_isdn_dma_tr_intrf#define coreio$v_sir_floppy_dma_int coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_floppy_dma_int`#define coreio$v_sir_scc1_dma_ov coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc1_dma_ovb#define coreio$v_sir_scc1_rcv_int coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc1_rcv_intf#define coreio$v_sir_scc1_tr_dma_me coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc1_tr_dma_me`#define coreio$v_sir_scc1_tr_int coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc1_tr_int`#define coreio$v_sir_scc0_dma_ov coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc0_dma_ovb#define coreio$v_sir_scc0_rcv_int coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc0_rcv_intf#define coreio$v_sir_scc0_tr_dma_me coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc0_tr_dma_me`#define coreio$v_sir_scc0_tr_int coreio$r_sir_overlay.coreio$r_sir_bits.coreio$v_sir_scc0_tr_intW#define coreio$v_sir_halt0 coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_halt0W#define coreio$v_sir_halt1 coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_halt1c#define coreio$v_sir_alt_console coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_alt_console[#define coreio$v_sir_scc0_si coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_scc0_si[#define coreio$v_sir_scc1_si coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_scc1_si[#define coreio$v_sir_ni_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_ni_intr_#define coreio$v_sir_isdn_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_isdn_intre#define coreio$v_sir_lance_dma_re coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_lance_dma_reg#define coreio$v_sir_pp_rc_dma_ovr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_pp_rc_dma_ovrg#define coreio$v_sir_pp_rc_hp_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_pp_rc_hp_intrg#define coreio$v_sir_pp_tr_dma_mre coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_pp_tr_dma_mreg#define coreio$v_sir_pp_tr_pe_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_pp_tr_pe_intrk#define coreio$v_sir_comm_rc_dma_ovr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_comm_rc_dma_ovrk#define coreio$v_sir_comm_rc_hp_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_comm_rc_hp_intrk#define coreio$v_sir_comm_tr_dma_mre coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_comm_tr_dma_mrek#define coreio$v_sir_comm_tr_pe_intr coreio$r_sir_overlay.coreio$r_sir_04_bits.coreio$v_sir_comm_tr_pe_intr^#define coreio$v_sir_tc_slot0 coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_tc_slot0^#define coreio$v_sir_tc_slot1 coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_tc_slot1^#define coreio$v_sir_scc0_int coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_scc0_int^#define coreio$v_sir_scc1_int coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_scc1_int`#define coreio$v_sir_lance_int coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_lance_int^#define coreio$v_sir_isdn_int coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_isdn_int^#define coreio$v_sir_cons_sel coreio$r_sir_overlay.coreio$r_sir_07__bits.coreio$v_sir_cons_sel9#define coreio$l_simr coreio$r_simr_overlay.coreio$l_simr^#define coreio$v_simr_gp_int_0 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_0^#define coreio$v_simr_gp_int_1 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_1^#define coreio$v_simr_gp_int_2 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_2^#define coreio$v_simr_gp_int_3 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_3^#define coreio$v_simr_gp_int_4 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_4^#define coreio$v_simr_gp_int_5 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_5^#define coreio$v_simr_gp_int_6 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_6^#define coreio$v_simr_gp_int_7 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_7^#define coreio$v_simr_gp_int_8 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_8^#define coreio$v_simr_gp_int_9 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_9`#define coreio$v_simr_gp_int_10 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_10`#define coreio$v_simr_gp_int_11 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_11`#define coreio$v_simr_gp_int_12 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_12`#define coreio$v_simr_gp_int_13 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_13`#define coreio$v_simr_gp_int_14 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_14`#define coreio$v_simr_gp_int_15 coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_gp_int_15f#define coreio$v_simr_lance_dma_er coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_lance_dma_erf#define coreio$v_simr_scsi_dma_mre coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scsi_dma_mred#define coreio$v_simr_scsi_dma_ov coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scsi_dma_ovf#define coreio$v_simr_scsi_dma_ptr coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scsi_dma_ptrf#define coreio$v_simr_isdn_dma_mre coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_isdn_dma_mren#define coreio$v_simr_isdn_dma_rc_intr coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_isdn_dma_rc_intrn#define coreio$v_simr_isdn_dma_tr_intr coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_isdn_dma_tr_intrj#define coreio$v_simr_floppy_dma_int coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_floppy_dma_intd#define coreio$v_simr_scc1_dma_ov coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc1_dma_ovf#define coreio$v_simr_scc1_rcv_int coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc1_rcv_intj#define coreio$v_simr_scc1_tr_dma_me coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc1_tr_dma_med#define coreio$v_simr_scc1_tr_int coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc1_tr_intd#define coreio$v_simr_scc0_dma_ov coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc0_dma_ovf#define coreio$v_simr_scc0_rcv_int coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc0_rcv_intj#define coreio$v_simr_scc0_tr_dma_me coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc0_tr_dma_med#define coreio$v_simr_scc0_tr_int coreio$r_simr_overlay.coreio$r_simr_bits.coreio$v_simr_scc0_tr_int[#define coreio$v_simr_halt0 coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_halt0[#define coreio$v_simr_halt1 coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_halt1g#define coreio$v_simr_alt_console coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_alt_console_#define coreio$v_simr_scc0_si coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_scc0_si_#define coreio$v_simr_scc1_si coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_scc1_si_#define coreio$v_simr_ni_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_ni_intrc#define coreio$v_simr_isdn_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_isdn_intri#define coreio$v_simr_lance_dma_re coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_lance_dma_rek#define coreio$v_simr_pp_rc_dma_ovr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_pp_rc_dma_ovrk#define coreio$v_simr_pp_rc_hp_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_pp_rc_hp_intrk#define coreio$v_simr_pp_tr_dma_mre coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_pp_tr_dma_mrek#define coreio$v_simr_pp_tr_pe_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_pp_tr_pe_intro#define coreio$v_simr_comm_rc_dma_ovr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_comm_rc_dma_ovro#define coreio$v_simr_comm_rc_hp_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_comm_rc_hp_intro#define coreio$v_simr_comm_tr_dma_mre coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_comm_tr_dma_mreo#define coreio$v_simr_comm_tr_pe_intr coreio$r_simr_overlay.coreio$r_simr_04_bits.coreio$v_simr_comm_tr_pe_intrb#define coreio$v_simr_tc_slot0 coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_tc_slot0b#define coreio$v_simr_tc_slot1 coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_tc_slot1b#define coreio$v_simr_scc0_int coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_scc0_intb#define coreio$v_simr_scc1_int coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_scc1_intd#define coreio$v_simr_lance_int coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_lance_intb#define coreio$v_simr_isdn_int coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_isdn_intb#define coreio$v_simr_cons_sel coreio$r_simr_overlay.coreio$r_simr_07__bits.coreio$v_simr_cons_sel9#define coreio$l_sadr coreio$r_sadr_overlay.coreio$l_sadr\#define coreio$v_sadr_tc_addr coreio$r_sadr_overlay.coreio$r_sadr_bits.coreio$v_sadr_tc_addrQ#define coreio$l_isdn_data_tr coreio$r_isdn_data_tr_overlay.coreio$l_isdn_data_trv#define coreio$v_isdn_data_tr_data coreio$r_isdn_data_tr_overlay.coreio$r_isdn_data_tr_bits.coreio$v_isdn_data_tr_dataQ#define coreio$l_isdn_data_rc coreio$r_isdn_data_rc_overlay.coreio$l_isdn_data_rcv#define coreio$v_isdn_data_rc_data coreio$r_isdn_data_rc_overlay.coreio$r_isdn_data_rc_bits.coreio$v_isdn_data_rc_dataK#define coreio$l_lance_slot coreio$r_lance_slot_overlay.coreio$l_lance_slotj#define coreio$v_lance_slot_cs coreio$r_lance_slot_overlay.coreio$r_lance_slot_bits.coreio$v_lance_slot_cst#define coreio$v_lance_slot_hw_addr coreio$r_lance_slot_overlay.coreio$r_lance_slot_bits.coreio$v_lance_slot_hw_addrH#define coreio$l_scc0_slot coreio$r_scc0_slot_overlay.coreio$l_scc0_slotf#define coreio$v_scc0_slot_cs coreio$r_scc0_slot_overlay.coreio$r_scc0_slot_bits.coreio$v_scc0_slot_csp#define coreio$v_scc0_slot_hw_addr coreio$r_scc0_slot_overlay.coreio$r_scc0_slot_bits.coreio$v_scc0_slot_hw_addrH#define coreio$l_scc1_slot coreio$r_scc1_slot_overlay.coreio$l_scc1_slotf#define coreio$v_scc1_slot _cs coreio$r_scc1_slot_overlay.coreio$r_scc1_slot_bits.coreio$v_scc1_slot_csp#define coreio$v_scc1_slot_hw_addr coreio$r_scc1_slot_overlay.coreio$r_scc1_slot_bits.coreio$v_scc1_slot_hw_addr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pra gma __standard #endif /* __COREIODEF_LOADED */ ww0=[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */F/* Source: 11-AUG-2005 14:45:38 $1$DGA8 345:[LIB_H.SRC]CPBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CPBDEF ***/#ifndef __CPBDEF_LOADED#define __CPBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__V AXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Constants defining CPU capability numbers and flags for routines */N/* */N#define CPB$C_PRIMARY 0 /* Primary CPU (aka TIMEKEEPER) */N#define CPB$C_NS  1 /* future */N#define CPB$C_QUORUM 2 /* Cluster quorum required */N#define CPB$C_RUN 3 /* Run capability */N#define CPB$C_IMPLICIT_AFFINITY 4 /* Implicit affinity */a#define CPB$C_SOFT_RAD_AFFINITY 5 /* If set, need to check further for soft RAD affinity */#define CPB$C_RAD_0 6#define CPB$C_RAD_1 7#define CPB$C_RAD_2 8#define CPB$C_RAD_3 9#define CPB$C_RAD_4 10#define CPB$C_RAD_5 11#define CPB$C_RAD_6 12#define CPB$C_RAD_7 13#define CPB$C_MAX 32 #define CPB$C_MAX_SYSTEM_BITS 16#define CPB$C_MAX_USER_BITS 16N#define CPB$C_VECTOR 1 /* equate NS with VECTOR */#define CPB$M_PRIMARY 0x1#define CPB$M_VECTOR 0x2#define CPB$M_QUORUM 0x4#define CPB$M_RUN 0x8$#define CPB$M_IMPLICIT_AFFINITY 0x10$#define CPB$M_SOFT_RAD_AFFINITY 0x20#define CPB$M_RAD_0 0x40#define CPB$M_RAD_1 0x80#define CPB$M_RAD_2 0x100#define CPB$M_RAD_3 0x200#define CPB$M_RAD_4 0x400#define CPB$M_RAD_5 0x800#define CPB$M_RAD_6 0x1000#define CPB$M_RAD_7 0x2000#define CPB$M_THDS_IDLE 0x4000#define CPB$S_CPBDEF 4 typedef struct _cpb { __union { unsigned int cpb$l_cpb; __struct {N unsigned cpb$v_primary : 1; /* Primary (timekeeper) */N unsigned cpb$v_vector : 1; /* Vector processor */N unsigned cpb$v_quorum : 1; /* Cluster quorum required */N unsigned cpb$v_run : 1; /* CPU can run processes */S unsigned cpb$v_implicit_affinity : 1; /* Extended cap - implicit aff */X unsigned cpb$v_soft_rad_affinity : 1; /* Extended cap - Soft RAD affinity */^ unsigned cpb$v_rad_0 : 1; /* RAD in which a CPU resides. MUST REMAIN IN ORDER */% unsigned cpb$v_rad_1 : 1;% unsigned cpb$v_rad_2 : 1;% unsigned cpb$v_rad_3 : 1;% unsigned cpb$v_rad_4 : 1;% unsigned cpb$v_rad_5 : 1;% unsigned cpb$v_rad_6 : 1;% unsigned cpb$v_rad_7 : 1;j unsigned cpb$v_thds_idle : 1; /* KTB must be alone on a core. Other CPU thds must be idle. */' unsigned cpb$v_fill_1 : 17; } cpb$r_fill_1_; } cpb$r_fill_0_; } CPB; #if !defined(__VAXC)?#define cpb$v_primary cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_primary=#define cpb$v_vector cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_vector=#define cpb$v_quorum cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_quorum7#define cpb$v_run cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_runS#define cpb$v_implicit_affinity cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_implicit_affinityS#define cpb$v_soft_rad_affinity cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_soft_rad_affinity;#define cpb$v_rad_0 cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_rad_0;#define cpb$v_rad_1 cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_rad_1;#define cpb$v_rad_2 cpb$r_fill_0_.cpb$r_fill_1_.cpb$ v_rad_2;#define cpb$v_rad_3 cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_rad_3;#define cpb$v_rad_4 cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_rad_4;#define cpb$v_rad_5 cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_rad_5;#define cpb$v_rad_6 cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_rad_6;#define cpb$v_rad_7 cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_rad_7C#define cpb$v_thds_idle cpb$r_fill_0_.cpb$r_fill_1_.cpb$v_thds_idle"#endif /* #if !defined(__VAXC) */ #define CPB$M_FLAG_CHECK_CPU 0x1 #define CPB$M_FLAG_PERMANENT 0x2#define CPB$M_FLAG_PRIMARY 0x4'#define CPB$M_FLAG_CHECK_CPU_ACTIVE 0x8#define CPB$S_CPB_FLAGSDEF 1 typedef struct _cpb_flags { __struct {N unsigned cpb$v_flag_check_cpu : 1; /* Check that process can run */N unsigned cpb$v_flag_permanent : 1; /* Affect process permanent mask */N unsigned cpb$v_flag_primary : 1; /* Request to run on primary cpu */V unsigned cpb$v_flag_check_cpu_active : 1; /* Check all selected CPUs active */_ unsigned cpb$v_flag_fi ller : 4; /**** ADD ALL NEW BITFIELDS BEFORE THIS DECLARATION */N/**** THIS FIELD IS USED TO ASSURE MASKS ARE WITHIN RANGE */ } cpb$r_cpb_flags; } CPB_FLAGS; #if !defined(__VAXC)A#define cpb$v_flag_check_cpu cpb$r_cpb_flags.cpb$v_flag_check_cpuA#define cpb$v_flag_permanent cpb$r_cpb_flags.cpb$v_flag_permanent=#define cpb$v_flag_primary cpb$r_cpb_flags.cpb$v_flag_primaryO#define cpb$v_flag_check_cpu_active cpb$r_cpb_flags.cpb$v_flag_check_cpu_active;#define cpb$v_flag_filler cpb$r_cpb_flags.cpb$v_flag_filler"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CPBDEF_LOADED */ ww@d[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */I/* Source: 09-JUN-2017 14:50:16 $1$DGA8345:[LIB_H.SRC]CPUCOMDEF.SDL;1 *//***************************************************************************************************** ***************************//*** MODULE $CPUCOMDEF ***/#ifndef __CPUCOMDEF_LOADED#define __CPUCOMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define STRLCK$M_LOCKED 0x1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _structure_lock { __union {#pragma __nomember_alignment' unsigned __int64 strlck$q_lock; __struct { __union {N unsigned int strlck$l_state; /* State flags longword */ __struct {Z unsigned strlck$v_lo cked : 1; /* Last untested page is being tested */4 unsigned strlck$v_reserved : 31;* } strlck$r_state_bits;* } strlck$r_fields_overlay;N unsigned int strlck$l_owner; /* Partition ID of owning instance */ } strlck$r_fill_1_; } strlck$r_fill_0_;V unsigned __int64 strlck$q_owner_incarnation; /* Instance life - from node block */N unsigned int strlck$l_spares_1 [12]; /* pad to next 64-byte boundary */  } STRUCTURE_LOCK; #if !defined(__VAXC)4#define strlck$q_lock strlck$r_fill_0_.strlck$q_lock_#define strlck$l_state strlck$r_fill_0_.strlck$r_fill_1_.strlck$r_fields_overlay.strlck$l_stateu#define strlck$v_locked strlck$r_fill_0_.strlck$r_fill_1_.strlck$r_fields_overlay.strlck$r_state_bits.strlck$v_lockedG#define strlck$l_owner strlck$r_fill_0_.strlck$r_fill_1_.strlck$l_owner"#endif /* #if !defined(__VAXC) */ #define STRLCK$C_LENGTH 64#define STRLCK$K_LENGTH 64 c#if !defin ed(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _link_header {#pragma __nomember_alignmentN unsigned __int64 lnkhdr$q_flink_offset; /* Forward offset link */N unsigned __int64 lnkhdr$q_blink_offset; /* Backward offset link */N unsigned __int64 lnkhdr$q_size; /* Size of associated structure */ } LINK_HEADER;#def ine LNKHDR$C_LENGTH 24#define LNKHDR$K_LENGTH 24 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _glxcomhdr {#pragma __nomember_alignmentP unsigned __int64 glxcomhdr$q_joiners; /* Count of members who have joined */Q unsigned short int glxcomhdr$w_mbo; /* Must be 1 - implies quad size field */N unsigned char glxcomhdr$b_type ; /* Dynamic structure type */N unsigned char glxcomhdr$b_subtype; /* Dynamic structure subtype */! char glxcomhdr$b_fill_2_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR unsigned __int64 glxcomhdr$q_size; /* Size of communication segment header */ __union {#pragma __nomember_alignmentN unsigned __int64  glxcomhdr$q_state; /* State flags quadword */ __struct {1 unsigned glxcomhdr$v_reserved_1 : 32;1 unsigned glxcomhdr$v_reserved_2 : 32;% } glxcomhdr$r_state_bits;$ } glxcomhdr$r_state_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 glxcomhdr$q_gmd_array_offset; /* Of fset to GMD array */N unsigned __int64 glxcomhdr$q_gcb_array_offset; /* Offset to GCB array */R unsigned __int64 glxcomhdr$q_active_set_offset; /* Offset to active set CBB */#pragma __nomember_alignmentN unsigned int glxcomhdr$l_spares_1 [2]; /* pad to next 64-byte boundary */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifY STRUCTURE_LOCK glxcomhdr$r_segment_lock; /* Lock structure on cache block boundary */ V STRUCTURE_LOCK glxcomhdr$r_pool_lock; /* Lock structure on cache block boundary */T LINK_HEADER glxcomhdr$r_free_pool; /* Listhead for self-relative free blocks */#pragma __nomember_alignmentX unsigned __int64 glxcomhdr$q_allocated_pool; /* Bytes of pool currently allocated */N unsigned __int64 glxcomhdr$q_max_pool; /* Total shmem pool space */T unsigned __int64 glxcomhdr$q_max_dynamic_pool; /* Maximum shmem to be managed */ } GLXCOMHDR; #if !defined(__VAXC)E#define glxcomhdr$q_state glxcomhdr$r_state_overlay.glxcomhdr$q_state"#endif /* #if !defined(__VAXC) */ #define GLXCOMHDR$C_LENGTH 240#define GLXCOMHDR$K_LENGTH 240N/*+ */N/* */N/* Galaxy CPU block definition. This block is allocated */N/* and initial ized when a CPU undergoes a state transition to a sharing */N/* node in a Galaxy configuration. */N/*- */##define CPU_GCB$M_NOTIFY_PACKET 0x1'#define CPU_GCB$M_CPU_IN_TRANSITION 0x1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypede f struct _cpu_gcb {#pragma __nomember_alignment __union {N unsigned __int64 cpu_gcb$q_event_bits; /* CPU notification bits */ __struct {T unsigned cpu_gcb$v_notify_packet : 1; /* GMP listhead contains packet */+ unsigned cpu_gcb$v_fill_7_ : 7; } cpu_gcb$r_fill_4_; } cpu_gcb$r_fill_3_;N unsigned short int cpu_gcb$w_size; /* Structure size */N unsigned char cpu_gcb$b_type; /* Structure type  */N unsigned char cpu_gcb$b_subtype; /* Structure subtype */N unsigned int cpu_gcb$l_owner_id; /* Owner node ID */ __union {N unsigned int cpu_gcb$l_state; /* State bitmask */ __struct {N unsigned cpu_gcb$v_cpu_in_transition : 1; /* Restricted access */- unsigned cpu_gcb$v_reserved : 31; } cpu_gcb$r_fill_6_; } cpu_gcb$r_fill_5_;N unsigned int  cpu_gcb$l_spares_1 [27]; /* pad to next 128-byte boundary */N LINK_HEADER cpu_gcb$r_gmp_listhead; /* Listhead for message packets */ } CPU_GCB; #if !defined(__VAXC)C#define cpu_gcb$q_event_bits cpu_gcb$r_fill_3_.cpu_gcb$q_event_bits[#define cpu_gcb$v_notify_packet cpu_gcb$r_fill_3_.cpu_gcb$r_fill_4_.cpu_gcb$v_notify_packet9#define cpu_gcb$l_state cpu_gcb$r_fill_5_.cpu_gcb$l_statec#define cpu_gcb$v_cpu_in_transition cpu_gcb$r_fill_5_.cpu_gcb$r_fill_6_.cpu_gcb$v_cpu_in_transit ion"#endif /* #if !defined(__VAXC) */ #define CPU_GCB$C_LENGTH 152#define CPU_GCB$K_LENGTH 152N/*+ */N/* */N/* Galaxy Member Data block definition. This block is allocated */N/* and initialized when a node joins a Galaxy community */N/*- */#define CPU_GMD$M_ACTIVE 0x1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cpu_gmd {#pragma __nomember_alignment __union {N unsigned int cpu_gmd$l_state; /* State flags quadword */ __struct {N unsigned cpu_gmd$v_active : 1; /* Segment is in use */- unsigned cpu_g md$v_reserved : 31;# } cpu_gmd$r_state_bits;" } cpu_gmd$r_state_overlay;N unsigned int cpu_gmd$l_primary_cpuid; /* CPU ID for this node */N unsigned short int cpu_gmd$w_size; /* Structure size */N unsigned char cpu_gmd$b_type; /* Structure type */N unsigned char cpu_gmd$b_subtype; /* Structure subtype */ char cpu_gmd$b_fill_8_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplus plus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 cpu_gmd$q_gpd_offset; /* Offset to GPD structure */#pragma __nomember_alignmentN unsigned int cpu_gmd$l_spares_1 [26]; /* pad to next 128-byte boundary */N LINK_HEADER cpu_gmd$r_gmp_listhead; /* Listhead for message packets */ } CPU_GMD; #if !defined(__VAXC)?#define cpu_gmd$l_state cpu_gmd$r_state_overlay.cpu_gmd$l_st ateV#define cpu_gmd$v_active cpu_gmd$r_state_overlay.cpu_gmd$r_state_bits.cpu_gmd$v_active"#endif /* #if !defined(__VAXC) */ #define CPU_GMD$C_LENGTH 152#define CPU_GMD$K_LENGTH 152N/*+ */N/* */N/* Galaxy Message Packet block definition. */N/*-  */##define CPU_GMP$M_NO_LOCAL_COPY 0x1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cpu_gmp {#pragma __nomember_alignmentN LINK_HEADER cpu_gmp$r_gmp_queue; /* Listhead for message packets */ __union {N unsigned int cpu_gmp$l_state; /* State bitmask */ __struct {Z  unsigned cpu_gmp$v_no_local_copy : 1; /* Don't copy packet to nonpaged pool */+ unsigned cpu_gmp$v_fill_1 : 31;! } cpu_gmp$r_fill_10_; } cpu_gmp$r_fill_9_;N unsigned int cpu_gmp$l_component_id; /* CPU ID for this node */N unsigned int cpu_gmp$l_source_id; /* Partition ID of source */N unsigned int cpu_gmp$l_target_id; /* Partition ID of target */P unsigned __int64 cpu_gmp$q_incarnation; /* Instance incarnation of t arget */N unsigned __int64 cpu_gmp$q_data_length; /* Size of data in this GMP */N unsigned __int64 cpu_gmp$q_data_offset; /* Size of data in this GMP */N unsigned __int64 cpu_gmp$a_data; /* Beginning of block data */ } CPU_GMP; #if !defined(__VAXC)9#define cpu_gmp$l_state cpu_gmp$r_fill_9_.cpu_gmp$l_state\#define cpu_gmp$v_no_local_copy cpu_gmp$r_fill_9_.cpu_gmp$r_fill_10_.cpu_gmp$v_no_local_copy"#endif /* #if !defined(__VAXC) */ #define CPU_GMP$C_LE NGTH 72#define CPU_GMP$K_LENGTH 72N/*+ */N/* */N/* Galaxy Packet Dispatch block definition. */N/*- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword #else#pragma __nomember_alignment#endiftypedef struct _cpu_gpd {#pragma __nomember_alignmentN unsigned int cpu_gpd$l_max_slots; /* maximum dispatch slots in struct */N unsigned int cpu_gpd$l_size; /* structure size */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 cpu_gpd$a_routines; /* Array of quad routines */ } CPU_GPD;#define CPU_GPD$C_LENGTH 16#define CPU_GPD$K_LENGTH 16 #ifdef __INITIAL_POINTER_SIZEM# pragma __required_pointer_size __save /* Save current pointer size */G# pragma __required_pointer_size 64 /* Pointers are 64-bits */M typedef struct _cpu_gcb * CPU_GCB_PQ; /* 64-bit pointer to struct */Q typedef struct _cpu_gcb ** CPU_GCB_PPQ; /* 64-bit ptr to a ptr to struct */M typedef struct _cpu_gmd * CPU_GMD_PQ;  /* 64-bit pointer to struct */Q typedef struct _cpu_gmd ** CPU_GMD_PPQ; /* 64-bit ptr to a ptr to struct */M typedef struct _cpu_gmp * CPU_GMP_PQ; /* 64-bit pointer to struct */Q typedef struct _cpu_gmp ** CPU_GMP_PPQ; /* 64-bit ptr to a ptr to struct */M typedef struct _cpu_gpd * CPU_GPD_PQ; /* 64-bit pointer to struct */Q typedef struct _cpu_gpd ** CPU_GPD_PPQ; /* 64-bit ptr to a ptr to struct */U typedef struct _link_header * LINK_HEADER_PQ; /* 64-bit pointer to struct */Y typedef struct _link_header ** LINK_HEADER_PPQ; /* 64-bit ptr to a ptr to struct */[ typedef struct _structure_lock * STRUCTURE_LOCK_PQ; /* 64-bit pointer to struct */_ typedef struct _structure_lock ** STRUCTURE_LOCK_PPQ; /* 64-bit ptr to a ptr to struct */Q typedef struct _glxcomhdr * GLXCOMHDR_PQ; /* 64-bit pointer to struct */U typedef struct _glxcomhdr ** GLXCOMHDR_PPQ; /* 64-bit ptr to a ptr to struct */O# pragma __required_pointer_size __restore /* Return to previous ptr size */#elseC typedef unsigned __int64 CPU_GCB_PQ; /* Size = 64-bit ptr */L typedef unsigned __int64 CPU_GCB_PPQ; /* Size = 64-bit ptr to a ptr */C typedef unsigned __int64 CPU_GMD_PQ; /* Size = 64-bit ptr */L typedef unsigned __int64 CPU_GMD_PPQ; /* Size = 64-bit ptr to a ptr */C typedef unsigned __int64 CPU_GMP_PQ; /* Size = 64-bit ptr */L typedef unsigned __int64 CPU_GMP_PPQ; /* Size = 64-bit ptr to a ptr */C typedef unsigned __int64 CPU_GPD_PQ; /* Size = 64-bit ptr */L typedef unsigned __int64 CPU_GPD_PPQ; /* Size = 64-bit ptr to a ptr */P typedef unsigned __int64 LINK_HEADER_PQ; /* 64-bit pointer to struct */T typedef unsigned __int64 LINK_HEADER_PPQ; /* 64-bit ptr to a ptr to struct */S typedef unsigned __int64 STRUCTURE_LOCK_PQ; /* 64-bit pointer to struct */W typedef unsigned __int64 STRUCTURE_LOCK_PPQ; /* 64-bit ptr to a ptr to struct */N typedef unsigned __int64 GLXCOMHDR_PQ; /* 64-bit pointer to struct */R typedef unsigned __int64 GLXCOMHDR_PPQ; /* 64-bit ptr to a ptr to struct */#endif $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CPUCOMDEF_LOADED */ ww`[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:29 by OpenVMS SDL V3.7 */F/* Source: 31-MAY-2022 08:15:56 $1$DGA8345:[LIB_H.SRC]CPUDEF.SDL;1 *//*********************************** *********************************************************************************************//*** MODULE $CPUDEF ***/#ifndef __CPUDEF_LOADED#define __CPUDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union #endif#endif  M#include /* Define the FKB type; CPU$ contains an embedded FKB */#include #include N/*+ */N/* */N/* Per-CPU Database definitions. One of these structures exists for */N/* each CPU that is participating in symmetric multiprocessing. */N/*  */N/* The per-CPU database consists of 2 parts. A fixed portion that exists */N/* for any CPU type is defined first. A variable portion is also defined as */N/* necessary for various CPU types. The contents of the variable portion */N/* are CPU-specific. */N/* */N/* When creating a per-CPU database, one must allocate space to include */N/* both the fixed portion and a variable portion that is specific to the */N/* CPU type for which the database is being created. */N/* */N/*- */N#define CPU$C_RESERVED 0 /* Zero is reserved */N#define CPU$C_INIT 1 /* CPU is being INITialized */N#define CPU$C_RUN 2 /* CPU is RUNning */N#define CPU$C_STOPPING 3 /* CPU is STOPping */N#define CPU$C_STOPPED 4 /* CPU is STOPPED */N#define CPU$C_TIMOUT 5 /* Boot of CPU timed out */N#define CPU$C_BOOT_REJECTED 6 /* CPU refuses to join SMP */N#define CPU$C_BOOTED 7 /* CPU booted - waiting for "go" */R#define CPU$C_NOT_CONFIGURED 8  /* CPU exists, but not in configure set */T#define CPU$C_POWERED_DOWN 9 /* CPU in configure set, but powered down */N#define CPU$C_DEALLOCATED 10 /* CPU has been deallocated */#define CPU$M_INV_TBS 0x1#define CPU$M_INV_TBA 0x2#define CPU$M_BUGCHK 0x4#define CPU$M_BUGCHKACK 0x8#define CPU$M_RECALSCHD 0x10#define CPU$M_UPDASTSR 0x20!#define CPU$M_UPDATE_HWCLOCK 0x40#define CPU$M_WORK_FQP 0x80#define CPU$M_QLOST 0x100#define CPU$M_RESCHED 0x200#define CPU$M_VIRTCONS 0x400#define CPU$M_IOPOST 0x800 #define CPU$M_INV_ISTREAM 0x1000#define CPU$M_INV_TBSD 0x2000 #define CPU$M_INV_TBS_MMG 0x4000!#define CPU$M_INV_TBSD_MMG 0x8000 #define CPU$M_IO_INT_AFF 0x10000"#define CPU$M_IO_START_AFF 0x20000$#define CPU$M_UPDATE_SYSPTBR 0x40000#define CPU$M_PERFMON 0x80000#define CPU$M_READ_SCC 0x100000!#define CPU$M_CPUFILL_1 0xFFFFFFF!#define CPU$M_CPUSPEC1 0x10000000!#define CPU$M_CPUSPEC2 0x20000000!#define CPU$M_CPUSPEC3  0x40000000!#define CPU$M_CPUSPEC4 0x80000000Q#define CPU$K_NUM_SWIQS 6 /* Number of software interrupt queues */#define CPU$M_SYS_ASTEN 0xF#define CPU$M_SYS_ASTSR 0xF0N#define CPU$C_HWPCBLEN 256 /* Length of HWPCB in 128 bytes */N#define CPU$K_HWPCBLEN 256 /* Length of HWPCB in 128 bytes */#define CPU$M_TERM_ASTEN 0xF#define CPU$M_TERM_ASTSR 0xF0#define CPU$M_BC_AST_CALLED 0x1#define CPU$M_BC_ASTDEL 0x2 #define CPU$M_BC_XSAVE_SAVED 0x4"#define CPU$M_BC_FAULTY_TOWERS 0x8#define CPU$M_BC_IMSEM 0x10$#define CPU$M_BC_ALPHAREG_SAVED 0x20"#define CPU$K_BC_INTSTK_LENGTH 480u/**** End of X86_64 symbols that match $CRASHDEF in [SDA]EVAX_SDADEF.SDL and $INTSTKDEF in [LIB]INTSTKDEF.SDL **** */#define CPU$M_SCHED 0x1#define CPU$M_FOREVER 0x2#define CPU$M_NEWPRIM 0x4#define CPU$M_PSWITCH 0x8#define CPU$M_BC_STACK 0x10#define CPU$M_BC_CONTEXT 0x20(#define CPU$M_USER_CAPABILITIES_SET 0x40"#define CPU$M_RESET_LOW_POWER 0x80#define CPU$M_STOPPING 0x1#define CPU$M_RESCHEDULING 0x2!#define CPU$M_PCSAMPLE_ACTIVE 0x1"#define CPU$M_IO_AFF_FKB_INUSE 0x1#define CPU$M_PORT_ASSIGNED 0x2"#define CPU$M_DISTRIBUTED_INTS 0x4(#define CPU$M_LASTPAGE_TESTED 0x20000000#define CPU$M_MCHECK 0x40000000%#define CPU$M_MEMORY_WRITE 0x80000000#define CPU$M_AUTO_START 0x1#define CPU$M_NOBINDINGS 0x2  9#ifdef __cplusplus /* Define structure prototypes */ struct _pcb; struct _ktb; struct _irp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cpu {#pragma __nomember_alignment __union {N struct _pcb *cpu$l_curpcb; /* Address of CPU's current PCB */N struct _ktb *cpu$l_curktb; /* Address of CPU's current KTB */ } cpu$r_curpcb_overlay;N void *cpu$l_slot_va; /* Address of CPU's HWRPB slot */N unsigned short int cpu$w_size; /* Structure size */N unsigned char cpu$b_type; /* Structure type */N unsigned char cpu$b_subtype; /* Structure subtype */N unsigned int cpu$l_state; /* State of this processor */N unsigned int cpu$l_cpumtx; /* Count of CPUMTX acquires */N unsigned int cpu$l_cur_pri; /* Cur rent Process Priority */N/* */N/* CPU type independent work request bits */N/* */ __union { __union {N unsigned int cpu$l_work_req; /* Work request bitmask */ __struct {N unsigned cpu$v_inv_tbs : 1; /* Invalidate TB single */N  unsigned cpu$v_inv_tba : 1; /* Invalidate TB all */N unsigned cpu$v_bugchk : 1; /* BUG_CHECK requested */N unsigned cpu$v_bugchkack : 1; /* BUG_CHECK acked */W unsigned cpu$v_recalschd : 1; /* Recalculate per cpu mask,reschedule */N unsigned cpu$v_updastsr : 1; /* Update ASTSR register */U unsigned cpu$v_update_hwclock : 1; /* Update local hardware clocks */N unsigned cpu$v_work_fqp : 1; /* Process work queue */N unsigned cpu$v_qlost : 1; /* Stall until quorum regained */N unsigned cpu$v_resched : 1; /* Issue IPL 3 SOFTINT */W unsigned cpu$v_virtcons : 1; /* Enter virtual console mode (primary) */N unsigned cpu$v_iopost : 1; /* Issue IPL 4 SOFTINT */Z unsigned cpu$v_inv_istream : 1; /* Invalidate cached instruction stream */N unsigned cpu$v_inv_tbsd : 1; /* Invalidate data TB single */[ unsigned cpu$v_inv_tbs_mmg : 1; /* Invalidate TB single MMG synchronized */\ unsigned cpu$v_inv_tbsd_mmg : 1; /* Invalidate TB single MMG synchronized */S unsigned cpu$v_io_int_aff : 1; /* Fast Path I/O completion event */P unsigned cpu$v_io_start_aff : 1; /* Fast Path I/O start event */P unsigned cpu$v_update_sysptbr : 1; /* Update SYSPTBR register */N  unsigned cpu$v_perfmon : 1; /* Performance Monitoring */N unsigned cpu$v_read_scc : 1; /* Read SCC */, unsigned cpu$v_fill_16_ : 3; } cpu$r_fill_1_; } cpu$r_fill_0_;N/* */N/* Define 4 CPU type specific work request bits as bit #s 28-31. */N/* */N  __union { /* CPU specific work requests */ __union {H unsigned int cpu$l_cpuspec; /* generic definition */ __struct {Z unsigned cpu$v_cpufill_1 : 28; /* pad bit definitions into position */N unsigned cpu$v_cpuspec1 : 1; /* CPU specific */N unsigned cpu$v_cpuspec2 : 1; /* CPU specific */N unsigned cpu$v_cpuspec3 : 1; /* CPU specific */N unsigned cpu$v_cpuspec4 : 1; /* CPU specific */$ } cpu$r_fill_3_; } cpu$r_fill_2_;$ } cpu$r_cpuspec_overlay;! } cpu$r_work_req_overlay;N/* */N unsigned int cpu$l_phy_cpuid; /* CPU ID number */N int cpu$l_cbb_reserved_1; /* $l_cpuid_mask moves to bottom */N unsigned  int cpu$l_busywait; /* <>0 = Spinning for lock */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 cpu$q_swiqfl [6]; /* Software interrupt queues */#pragma __nomember_alignmentN struct _irp *cpu$l_psfl; /* POST QUEUE forward link */N struct _irp *cpu$l_psbl; /* POST QUEUE backward link */N __union { /* Work queue overlay */N unsigned __int64 cpu$q_work_fqfl; /* Work packet queue */N unsigned __int64 cpu$q_work_ifq; /* Work packet queue */ } cpu$r_ifq_overlay;N/* */N int cpu$l_zeroed_page_spte_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */N void *cpu$l_zeroed_page_va; /* VA for zeroed page filling */N __int64 cpu$q_zeroed_page_state; /* State for interrupted filling */N/******************************************************************* */I/* HWPCB for this CPU's dedicated System Process */N/* */O/* This Hardware Privileged Context Block provides the context for when this */N/* CPU has no other process to run. */N/* */N/* NOTE WELL: This HWPCB must be aligned to a 128 byte boundary, the */I/* architected natural alignment of a HWPCB. */N/* */R/* NOTE WELL: There are bit symbols defined here for accessing the saved ASTEN, */U/* ASTSR, FEN and DATFX values in the HWPCB. These symbols are NOT to be used when */Z/* interfacing to the ASTEN, ASTSR, FEN or DATFX internal processor registers directly. */O/* See the specific internal register definitions for bitmasks and constants */I/* to be used when interfacing to the IPRs directly. */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nome mber_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 cpu$q_phy_sys_hwpcb; /* Physical address of HWPCB */N/* Start of aligned section */#pragma __nomember_alignment __union {N unsigned __int64 cpu$q_sys_hwpcb; /* Base of HWPCB */N unsigned __int64 cpu$q_sys_ksp; /* Kernel stack pointer */ } cpu$r_hwpcb_overlay;N unsigned __int64 cpu$q_sys_esp ; /* Executive stack pointer */N unsigned __int64 cpu$q_sys_ssp; /* Supervisor stack pointer */N unsigned __int64 cpu$q_sys_usp; /* User stack pointer */N unsigned __int64 cpu$q_sys_ptbr [4]; /* Page Table base for each mode */U unsigned __int64 cpu$q_sys_asn; /* ASN (to be combined with mode for PCID) */ __union {N unsigned __int64 cpu$q_sys_astsr_asten; /* ASTSR / ASTEN quadword */ __struct {N un signed cpu$v_sys_asten : 4; /* AST Enable Register */N unsigned cpu$v_sys_astsr : 4; /* AST Pending Summary Register */ } cpu$r_ast_bits0; } cpu$r_ast_overlay;N unsigned __int64 cpu$q_sys_perf_ctrl; /* Perfomance monitoring control */N unsigned __int64 cpu$q_sys_cc; /* Cycle Counter */ unsigned __int64 cpu$q_unq;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_p ointer_size __long /* And set ptr size default to 64-bit pointers */` void *cpu$pq_sys_alphareg [4]; /* Pointers to emulated Alpha registers for each mode */#else* unsigned __int64 cpu$pq_sys_alphareg [4];#endifN unsigned char cpu$b_sys_pmod; /* Previous mode */T unsigned char cpu$b_sys_was_scheduled; /* Process was scheduled at least once */" char cpu$b_sys_reserved_1 [6];N unsigned int cpu$l_sys_interrupt_depth; /* Interrupt depth  */N int cpu$l_sys_cur_frame_mode; /* Mode of currently active frame */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_sys_cur_frame; /* Currently active frame */#else' unsigned __int64 cpu$pq_sys_cur_frame;#endif* unsigned __int64 cpu$q_sys_kstack_top;- unsigned __int64 cpu$q_sys_kstack_bottom;N __int64 cpu$q_sys_pal_rsvd [5]; /* Reserved for PAL Scratch */N char cpu$t_align2 [40]; /* Assure 128 byte alignment */N/* */N/* End of Hardware Privileged Context Block (HWPCB) for the system process */N/* */N/******************************************************************* */N/******************************************************************* */I/* HWPCB for this CPU's Terminating Process. */N/* */O/* This Hardware Privileged Context Block provides the context for when this */N/* CPU needs a place to run when a powerfail may, unexpectedly, happen. */N/* */Q/* Remember, when a process's HWPCB is loaded (active on the CPU) the contents */N/* of the HWPCB are undefined since the processor may use that area as */S/* scratch space. All code paths that execute higher than IPL IPL$_POWER-2 (29) */O/* for an extended period of time may need to execute in the context of this */O/* process. Currently this includes most code surrounding powerfail/restart */N/* and parts of SMP$START_SECONDARY. */N/* */N/* NOTE WELL: This HWPCB must be aligned to a 128 byte boundary, the */I/* architected natural alignment of a HWPCB. */N/* */R/* NOTE WELL: There are bit symbols defined here for accessing the saved ASTEN, */V/* ASTSR, FEN and DATFX values in the HWPCB. These symbols are NOT to be used when */Z/* interfacing to the ASTEN, ASTSR, FEN or DATFX internal processor registers directly. */O/* See the specific internal register definitions for bitmasks and constants */I/* to be used when interfacing to the IPRs directly. */N/* */N/* Start of aligned section */ __union {N unsigned __int64 cpu$q_term_hwpcb; /* Base of HWPCB */N unsigned __int64 cpu$q_term_ksp; /* Kernel stack pointer */# } cpu$r_term_hwpcb_overlay;N unsigned __int64 cpu$q_term_esp; /* Executive stack pointer */N unsigned __int64 cpu$q_term_ssp; /* Supervisor stack pointer */N unsigned __int64 cpu$q_term_usp; /* User stack pointer */N unsigned __int64 cpu$q_term_ptbr [4]; /* Page Table base for each mode */U unsigned __int64 cpu$q_term_asn; /* ASN (to be combined with mode for PCID) */ __union {N unsigned __int64 cpu$q_term_astsr_asten; /* ASTSR / AS TEN quadword */ __struct {N unsigned cpu$v_term_asten : 4; /* AST Enable Register */N unsigned cpu$v_term_astsr : 4; /* AST Pending Summary Register */# } cpu$r_term_ast_bits0;! } cpu$r_term_ast_overlay;N unsigned __int64 cpu$q_term_perf_ctrl; /* Perfomance monitoring control */N unsigned __int64 cpu$q_term_cc; /* Cycle Counter */N unsigned __int64 cpu$q_term_unq; /* Process Unique Value  */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */` void *cpu$pq_term_alphareg [4]; /* Pointers to emulated Alpha registers for each mode */#else+ unsigned __int64 cpu$pq_term_alphareg [4];#endifN unsigned char cpu$b_term_pmod; /* Previous mode */U unsigned char cpu$b_term_was_scheduled; /* Process was scheduled at least once  */# char cpu$b_term_reserved_1 [6];N unsigned int cpu$l_term_interrupt_depth; /* Interrupt depth */N int cpu$l_term_cur_frame_mode; /* Mode of currently active frame */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_term_cur_frame; /* Currently active frame */#else( unsigned __int64 cpu$pq_term_cur_fram e;#endif+ unsigned __int64 cpu$q_term_kstack_top;. unsigned __int64 cpu$q_term_kstack_bottom;N __int64 cpu$q_term_pal_rsvd [5]; /* Reserved for PAL Scratch */N char cpu$t_align3 [40]; /* Assure 128 byte alignment */N/* */S/* End of aligned portion of HWPCB. Next quadword is used so we don't need to */X/* convert a virtual address to a physical address every time we use the terminating */N/* process. */N/* */N unsigned __int64 cpu$q_phy_term_hwpcb; /* Physical address of HWPCB */N/* */R/* End of Hardware Privileged Context Block (HWPCB) for the terminating process */N/* */N/******************************************************************* */N/* */N/* Per-CPU state saved during powerfail interrupt processing. The state */N/* that is saved here is process independent, yet specific to this CPU. */N/* */N unsigned __int64 cpu$q_saved_pcbb; /* PCBB from powerdown (non-zero */N/* if state successfully saved) */N unsigned __int64 cpu$q_scbb; /* SCBB from powerdown */N unsigned __int64 cpu$q_sisr; /* SISR from powerdown */N/******************************************************************* */N/* The following storage is used by BUGCHECK code. The order must be */N/* preserved since it is assumed by a table within SDA (see $CRASHDEF */N/* in [SDA]EVAX_SDADEF.SDL). The cells from BC_FLAGS to BC_SS must */N/* also match the layout of $INTSTKDEF in [LIB]INTSTKDEF.SDL. */N/* */N unsigned __int64 cpu$q_bc_ksp; /* Stored KSP */N unsigned __int64 cpu$q_bc_esp; /* Stored ESP */N unsigned __int64 cpu$q_bc_ssp; /* Stored SSP */N unsigned __int64 cpu$q_bc_usp; /* Stored USP */N unsigned __int64 cpu$q_bc_ptbr [4]; /* Stored PTBR for each mode */N unsigned __int64 cpu$q_bc_asn; /* Stored ASN */N unsigned __int64 cpu$q_bc_astsr_asten; /* Stored AST SR and EN */T unsigned __int64 cpu$q_bc_perf_ctrl; /* Stored performance monitoring control */N unsigned __int64 cpu$q_bc_cc; /* Stored CC */N unsigned __int64 cpu$q_bc_unq; /* Thread pointer */R#ifdef __INITIAL_POINTER _SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */T void *cpu$pq_bc_alphareg_ptr [4]; /* Emulated Alpha registers for each mode */#else- unsigned __int64 cpu$pq_bc_alphareg_ptr [4];#endifN unsigned char cpu$b_bc_pmod; /* Previous mode */S unsigned char cpu$b_bc_was_scheduled; /* Process was scheduled at least once */N char cpu$b_bc_reserved_1 [6];  /* alignment */N unsigned int cpu$l_bc_interrupt_depth; /* Interrupt depth */N int cpu$l_bc_cur_frame_mode; /* Mode of currently active frame */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_bc_cur_frame; /* Currently active frame */#else& unsigned __int64 cpu$pq_bc_cur_frame; #endif) unsigned __int64 cpu$q_bc_kstack_top;, unsigned __int64 cpu$q_bc_kstack_bottom;Q/* **** The next group of cells match $INTSTKDEF (from BC_FLAGS to BC_SS) **** */ __union { char cpu$b_bc_flags; __struct {h unsigned cpu$v_bc_ast_called : 1; /* ASTDEL has been called at least once with this frame */S unsigned cpu$v_bc_astdel : 1; /* Performing outer-mode AST delivery */\ unsigned cpu$v_bc_xsave_saved : 1; /* XSAVE state sa ved prior to AST delivery */P unsigned cpu$v_bc_faulty_towers : 1; /* Re-execute system service */X unsigned cpu$v_bc_imsem : 1; /* Inner-mode semaphore needs to be released */[ unsigned cpu$v_bc_alphareg_saved : 1; /* Alpha registers saved in this frame */( unsigned cpu$v_fill_17_ : 2;! } cpu$r_bc_flag_bits; } cpu$r_bc_flags_union;Q unsigned char cpu$b_bc_pprevmode; /* Save interrupted context's PREVMODE */ __union {Q unsigned char cpu$b_bc_prevmode; /* Save interrupted context's CURMODE */j unsigned char cpu$b_bc_prevstack; /* What mode of stack (register and memory) do we return to? */" } cpu$r_bc_prevmode_union;N unsigned char cpu$b_bc_ipl; /* SWIS IPL state */n unsigned int cpu$l_bc_stkalign; /* How much allocated on this stack for int frame? Guaranteed that */N/* STKALIGN & 0XFFF0 is the actual length of the structure. In other */N/* words, the structure is always allocated on a 16-byte boundary and */N/* is a multiple of 16-bytes long. */N unsigned char cpu$b_bc_astmode; /* Mode of current AST delivery */+ unsigned char cpu$b_bc_interrupt_depth;d unsigned char cpu$b_bc_type; /* Make this structure look like a standard VMS structure */# unsigned char cpu$b_bc_subtype;N unsigned int cpu$l_bc_trap_type; /* Trap type */N unsigned __int64 cpu$q_bc_fsbase; /* Saved base of FS segment */N unsigned __int64 cpu$q_bc_rax; /* Saved x86 registers */" unsigned __int64 cpu$q_bc_rdi;" unsigned __int64 cpu$q_bc_rsi;" unsigned __int64 cpu$q_bc_rdx;" unsigned __int64 cpu$q_bc_rcx;! unsigned __int64 cpu$q_bc_r8;! unsigned __int64 cpu$q_bc_r9;" unsigned __int64 cpu$q_bc_rbx;" unsigned __int64 cpu$q_bc_rbp;" unsigned __int64 cpu$q_bc_r10;" unsigned __int64 cpu$q_bc_r11;" unsigned __int64 cpu$q_bc_r12;" unsigned __int64 cpu$q_bc_r13;" unsigned __int64 cpu$q_bc_r14;" unsigned __int64 cpu$q_bc_r15;, unsigned __int64 cpu$q_bc_alphareg [32];R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *cpu$pq_bc_prev_frame;#else' unsigned __int64 cpu$pq_bc_prev_frame;#endif! int cpu$l_bc_prev_frame_mode;%  unsigned int cpu$l_bc_filler_pfm;( unsigned short int cpu$w_bc_cpu_num;- unsigned short int cpu$w_bc_filler_2 [3];N unsigned __int64 cpu$q_bc_vector; /* Interrupt vector we came in on */Z unsigned __int64 cpu$q_bc_error_code; /* From here on this is the CPU-defined frame */" unsigned __int64 cpu$q_bc_rip;! unsigned __int64 cpu$q_bc_cs;% unsigned __int64 cpu$q_bc_rflags;" unsigned __int64 cpu$q_bc_rsp;! unsigned __int64 cpu$q_bc_ss;N unsigned __int64 c pu$q_bc_pcbb; /* Stored PCBB */N unsigned __int64 cpu$q_bc_prbr; /* Stored PRBR */N unsigned __int64 cpu$q_bc_scbb; /* Stored SCBB */N unsigned __int64 cpu$q_bc_sisr; /* Stored SISR */P/**** End of X86_64 symbols that match $CRASHDEF in [SDA]EVAX_SDADEF.SDL **** */X unsigned __int64 cpu$q_bc_bugstk; /*new BUGSTK pointer following context switch */X unsigned __int64 cpu$q_bc_intstk ; /*new INTSTK pointer following context switch */* unsigned __int64 cpu$q_bc_orig_intstk;N/* */N/* */N/* */N/* End of storage used by BUGCHECK code. */N/******************************************************************* */N unsi gned int cpu$l_bugcode; /* BUGCHECK code */N unsigned int cpu$l_capability; /* Bitmask of CPU's capabilities */N unsigned __int64 cpu$q_boot_time; /* System time this cpu booted */N unsigned __int64 cpu$q_asn; /* Last ASN assigned for this CPU */N unsigned __int64 cpu$q_asnseq; /* Current ASN sequence number */N/* */N/* Time counters defined as follow s: */N/* (Also applies to UKERNEL and UNULLCPU cells) */N/* */N/* KERNEL mode in process context, no spinlock busywait active */N/* EXECUTIVE mode */N/* SUPERVISOR mode */N/* USER mode   */X/* KERNEL mode in system context (PS = 1), no spinlock busywait active */O/* KERNEL mode in process or system context, spinlock busywait is active */N/* */N/* NULL time counter */N/* */ __union {N unsigned __int64 cpu$q_kernel [6]; /* Clock ticks in each mode */ __struct {X __int64 cpu$q_fill_1 [4]; /* non-busywait counters for 4 process modes */V unsigned __int64 cpu$q_system_context; /* Clock ticks in interrupt mode */S unsigned __int64 cpu$q_mpsynch; /* Clock ticks in MP synchronization */ } cpu$r_fill_5_; } cpu$r_fill_4_;Z unsigned __int64 cpu$q_nullcpu; /* Clock ticks in per-CPU system process (null) */N unsigned int cpu$l_hardaff; /* Count of processes with */N/* hard affinity for this CPU */N/* */N/* Spinlock acquisition/release tracking and verification data */N/* */O unsigned int cpu$l_rank_vec; /* Ranks of spinlocks currently held */N unsigned int cpu$l_ipl_vec; /* IPL vector of held spinlocks  */N int cpu$l_ipl_array [32]; /* IPL counts of held spinlocks */N/* */N/* Cells for CPU sanity timer */N/* */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *cpu$l_tpointer; /* Address of SANITY_TIMER of */N/* CPU being watched */Z unsigned int cpu$l_sanity_timer; /* # of sanity cycles before this CPU times out */P unsigned int cpu$l_sanity_ticks; /* # of ticks until next sanity cycle */N/* */N/* CPU flags */N/*  */ __union {N unsigned int cpu$l_flags; /* Various CPU flags */ __struct {N unsigned cpu$v_sched : 1; /* Idle loop vying for SCHED */N unsigned cpu$v_forever : 1; /* STOP/CPU with /FOREVER qualifier */N unsigned cpu$v_newprim : 1; /* Primary-to-be CPU */Z unsigned cpu$v_pswitch : 1; /* Live primary switch requested by primary CPU */d unsigned cpu$v_bc_stack : 1; /* Set if we swapped process context to write crash dump */_ unsigned cpu$v_bc_context : 1; /* Set if database contains context from bugcheck */h unsigned cpu$v_user_capabilities_set : 1; /* Set if user capabilities already initialized */q unsigned cpu$v_reset_low_power : 1; /* Tell the next clock soft-tick to reset the low power switch */ } cpu$r_fill_7_; } cpu$r_fill_6_;N/*  */N/* The following field, INTFLAGS, must be longword aligned since */N/* interlocked instructions are used to access the bitfields. */N/* */ __union {N unsigned int cpu$l_intflags; /* Interlocked CPU flags */ __struct {N unsigned cpu$v_stopping : 1; /* CPU stopping flag */ N unsigned cpu$v_rescheduling : 1; /* CPU rescheduling flag */( unsigned cpu$v_fill_18_ : 6; } cpu$r_fill_9_; } cpu$r_fill_8_;N/* */N/* System stack base and limit */N/* */ void *cpu$l_sys_stack_base; void *cpu$l_sys_stack_limit;N/*  */N/* Descriptor used to locate the variable portion of the per-CPU database. */N/* This approach allows the fixed portion of the database to more easily */N/* grow over time. The offset represents a byte offset from the start of */P/* the fixed portion of the per-CPU database to a variable portion containing */N/* CPU-specific data. The variable portion is located adjacent to the fixed */N/* portion of the database.  */N/* */T unsigned int cpu$l_variable_offset; /* Offset to variable portion of database */Q unsigned int cpu$l_variable_length; /* Length in bytes of variable portion */N/* */N/* Define cells for machine check recovery block. These two longwords */N/* are assumed to be adjacent.  */N/* */V unsigned int cpu$l_mchk_mask; /* Function mask for current recovery block */Q void *cpu$l_mchk_sp; /* Saved SP for return at end of block */N/* 0 (zero) if no current recovery block */N/* */O/* Define a cell to point to a machine check crashes save area. This poi nter */N/* is used by SDA to display the machine check information after a crash. */N/* */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_mchk_crash_area_va; /* VA of mcheck crash area */#else, unsigned __int64 cpu$pq_mchk_crash_area_va;#endif  __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif. void *cpu$pl_mchk_crash_area_va_l;5 unsigned int cpu$il_mchk_crash_area_va_h;. } cpu$r_mchk_crash_area_va_fields;+ } cpu$r_mchk_crash_area_va_overlay;N/* */P/* Define cells for processor_corrected_error_svapte and processor_mchk_abort */N/* _svapte. */N/* */N int cpu$l_proc_corrected_error_svap_fi; /* NOSVAPTE_V9.0 Dave Fairbanks */N int cpu$l_proc_mchk_abort_svapte_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer _size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_logout_area_va; /* VA of mcheck logout area */#else( unsigned __int64 cpu$pq_logout_area_va;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif* void *cpu$pl_logout_area_va_l;1 unsigned int cpu$il_logout_area_va_h; * } cpu$r_logout_area_va_fields;' } cpu$r_logout_area_va_overlay;N/* */N/* Soft tick dynamic timing offsets to determine when a 10ms "soft" tick */N/* occurs for each CPU. */N/* */! unsigned int cpu$l_soft_tick; int cpu$l_time_deviation;N/*  */O/* The following fields support PC sampling. They must be longword aligned. */N/* */ void *cpu$l_pcsample_buffer; __union {* unsigned int cpu$l_pcsample_flags; __struct {N unsigned cpu$v_pcsample_active : 1; /* Sample being collected. */( unsigned cpu$v_fill_19_ : 7; } cpu$r_fill_11_; } cpu$r_fill_10_;N/* */P/* Performance monitoring cells to replace global roll-up cells in idle loop. */N/* These cells MUST remain on quadword boundaries since they are updated by */O/* system quadword builtins. Any changes above these offsets must take this */N/* into account. */N/* */N unsigned __int 64 cpu$q_idle_loop_count; /* Count of idle code loops */N unsigned __int64 cpu$q_zeroed_page_count; /* Count of free pages zeroed */N/* */N/* Rank counter cells for keeping track of the number of acquisitions */N/* in effect for a given ranking. This is primarily for portlock support, */N/* but is integrated into all static ranks for simplicity */N/* ! */N int cpu$l_rank_array [32]; /* Counts of acquisitions by rank */N/* */N/* Inline fork block for port-affinitized I/O activity */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else "#pragma __nomember_alignment#endif char cpu$l_io_aff_fkb [48];N/* */N/* Flags field for Fast Path I/O - this field is clumped with the FKB above */N/* and the queue below to get the best cache block behavior */N/* */#pragma __nomember_alignment __union {N unsigned int cpu$l_io_aff_flags; /* Fast Path I/O bits # */ __struct {N unsigned cpu$v_io_aff_fkb_inuse : 1; /* CPUDB FKB in use */N unsigned cpu$v_port_assigned : 1; /* CPU has port affinity */] unsigned cpu$v_distributed_ints : 1; /* CPU has hw interrupt port(s) assigned. */( unsigned cpu$v_fill_20_ : 5; } cpu$r_fill_13_; } cpu$r_fill_12_;N/* */N/* Absolute queue header for por $t-affinitized Fast Path I/O - must be */N/* quadword aligned */N/* */ char cpu$b_fill_21_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN void *cpu$ps_io_start_aff_qfl; /* UCB listhead */%#pragma __nomember_alignment" void *cpu$ps_io_start_aff_qbl;N/* */N/* The following space doubles as debugging space as well as providing */N/* 64-byte cache alignment for the following listhead. If the structure */N/* above changes this must reflected in this count. If this space gets */N/* filled in at some point, it is critical that the new cells not be */N/* highly accessed, otherwise we have &potential hangs from overlapping */N/* memory lock interactions. */ int cpu$l_fill_6 [12];N/* */N/* Absolute interlocked queue for fastpath hardware interrupt ports */N/* assigned to this cpu */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) ' && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN void *cpu$ps_io_int_aff_qfl; /* Fastpath HW interrupt */#pragma __nomember_alignmentN void *cpu$ps_io_int_aff_qbl; /* : ports UCB listhead */N/* */N/* Holder cell for CPU capabilities. This replaces the old CAPABILITY that */P/*( existed further up the structure. The lower longword holds the system and */P/* user capabilities for this CPU. The upper longword is an affinity bitmask */N/* containing a single bit set in the CPUID position of this CPU. */N/* */ __union {N unsigned __int64 cpu$q_capabilities; /* Caps and affinity */N unsigned int cpu$l_capabilities; /* Just system and user caps */% )} cpu$r_capabilities_overlay;T/* Cell to hold a counter for emulated instructions. This counter is incremented */P/* when an instruction that is not available on this CPU (e.g. LDBU, LDWU) is */N/* executed in system context and is emulated. */ int cpu$l_emulate_count; __union {W unsigned int cpu$l_untested_page_state; /* State for interrupted memory test */ __struct {z unsigned short int cpu$w_untested_chunks; /* Count of 32 *-byte chunks remaining to be tested in current page */' unsigned cpu$v_fill_7 : 13;X unsigned cpu$v_lastpage_tested : 1; /* Last untested page is being tested */P unsigned cpu$v_mcheck : 1; /* Mcheck occurred during memory test */V unsigned cpu$v_memory_write : 1; /* Memory test is in the write process */" } cpu$r_untested_bits;! } cpu$r_untested_overlay;, unsigned __int64 cpu$q_untested_pattern;N int cpu$l_untested_page_sp +te_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */N void *cpu$l_untested_page_va; /* VA for testing memory */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif" __int64 cpu$q_sched_data [85];N/* scheduling data based on process */N/* priority level (5 quadwords for each , */N/* priority level). See SCHED_DS structure */N/* below for more details. */N/* */N __int64 cpu$q_scc_delta; /* Offset from primary SCC value */#pragma __nomember_alignment __union {O unsigned int cpu$l_transition_flags; /* Various CPU transition flags */ __struct {Q unsigned cpu$v -_auto_start : 1; /* CPU is automatically made active */Z unsigned cpu$v_nobindings : 1; /* Minimize features that prevent transition */( unsigned cpu$v_fill_22_ : 6; } cpu$r_fill_15_; } cpu$r_fill_14_; char cpu$b_fill_23_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE / .* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_ctd_listhead; /* Offset to CPU transition block */#else& unsigned __int64 cpu$pq_ctd_listhead;#endif#pragma __nomember_alignmentN int cpu$l_failover_node; /* Node ID to fail this CPU over to */ char cpu$b_fill_24_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4. /0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_gmp_listhead; /* Address of listhead for GMPs */#else& unsigned __int64 cpu$pq_gmp_listhead;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size 0pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_extension_block; /* Pointer to extension of CPUDB */#else) unsigned __int64 cpu$pq_extension_block;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Y void *cpu$pq_lckcpu; /* pointer to per-CPU lckmgr counter 1 structure */#else unsigned __int64 cpu$pq_lckcpu;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *cpu$l_fp_asgn_ports_fl; /* queue links to fastpa 2th ports */#pragma __nomember_alignmentN void *cpu$l_fp_asgn_ports_bl; /* : */[ int cpu$l_fp_num_ports; /* number of fastpath ports assigned to this CPU */^ int cpu$l_fp_num_user_ports; /* number of user preferred fastpath ports assigned */ int cpu$l_fp_spare1; int cpu$l_fp_spare2; int cpu$l_fp_spare3; int cpu$l_fp_spare4;h int cpu$l_rad; /* This cell initialized to the RAD number the3 CPU belongs to */ int cpu$l_rad_spare1;g unsigned __int64 cpu$q_bc_scc; /* System Cycle Counter recorded by BUGCHECK (all platforms) */N/* */U/* TIMEDWAIT cells to support mixed-speed CPUs in heterogeneous SMP configurations */N/* */N unsigned __int64 cpu$q_tmwt_scaler; /* Scaler value for SCC conversions */P unsigned __int64 cpu4$q_tmwt_divisor; /* Divisor value for SCC conversions */U unsigned __int64 cpu$q_tmwt_shift; /* Divisor shift count for SCC conversions */N/* */N/* Fastpath hardware interrupt ports housekeeping */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember 5_alignment __quadword#else#pragma __nomember_alignment#endifN void *cpu$l_fp_asgn_hwint_ports_fl; /* queue links to hwint ports */#pragma __nomember_alignmentN void *cpu$l_fp_asgn_hwint_ports_bl; /* : */N int cpu$l_num_hwint_ports; /* number HW int ports */X int cpu$l_num_usrprf_hwint_ports; /* number user-assigned fastpath HW int ports */P unsigned __int64 cpu$q_xfc_vab_pointer; /* Link to XFC per RAD structure6s */N/* Keep track of CPU load */d unsigned int cpu$l_load_factor; /* This is the fixed point fraction of time CPU is usable */N unsigned int cpu$l_bin_5sec; /* Which of 5 bins are we using */O unsigned int cpu$l_usable_ticks [5]; /* 5 bins counting the usable ticks */S unsigned int cpu$l_total_ticks; /* Total number of ticks during a second */T unsigned int cpu$l_counter_10ms; /* Count 10ms intervals to get7 one second */N int cpu$l_filler_1; /* Make quadwords even */N/* Per-CPU queues */N int cpu$aq_com_queues [128]; /* 64 queue heads for this CPU */Z unsigned __int64 cpu$q_com_queue_summary; /* Bits to show which CPU queues are used */N/* Per-RAD database pointer */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporte 8d */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */e void *cpu$pq_rad_database; /* Pointer to the RAD database for RAD this CPU belongs to */#else& unsigned __int64 cpu$pq_rad_database;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr s 9ize pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_cflush_va_pte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else+ unsigned __int64 cpu$pq_cflush_va_pte_sva;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */S void *cpu$pq_cflush_va; :/* Pointer to S2 space VA used by cflush */#else# unsigned __int64 cpu$pq_cflush_va;#endifN/* Per-CPU timing cells to be filled in when CPU joins the active set */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR __int64 cpu$q_itm_width; /* Width of clock tick in IPF ITM units */#pragma __nomember_alignment int cpu$l_max_devi ;ation;% unsigned int cpu$l_minimum_ticks; int cpu$l_over_delta; int cpu$l_under_delta;N/* */N/* System register stack base and limit */N/* */N/* */N/* Termination and slot stack bases */N/* < */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *cpu$q_slot_stack_base;#else( unsigned __int64 cpu$q_slot_stack_base;#endifN/* */N/* VHPT virtual address and setup info */N=/* */N/* */N/* More BUGCHECK cells: the contents of the CR.PTA register; data from SWIS */O/* (SWIS$L_GH_PS thru SWIS$Q_DTNVFLT without the fill); the region registers */N/* */N/* */N/* Virtual addresses of >the physical buffers that hold the SAL-built error */N/* records for the four hardware interrupt types */N/* */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */O void *cpu$pq_init_error_record_va; /* VA of INIT error record buffer */#else. unsigne ?d __int64 cpu$pq_init_error_record_va;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif0 void *cpu$pl_init_error_record_va_l;7 unsigned int cpu$il_init_error_record_va_h;0 } cpu$r_init_error_record_va_fields;- } cpu$r_init_error_record_va_overlay; __union {R#ifdef __INITIAL_POINTER_SIZ @E /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_mca_error_record_va; /* VA of MCA error record buffer */#else- unsigned __int64 cpu$pq_mca_error_record_va;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/ A void *cpu$pl_mca_error_record_va_l;6 unsigned int cpu$il_mca_error_record_va_h;/ } cpu$r_mca_error_record_va_fields;, } cpu$r_mca_error_record_va_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_cmc_error_record_va; /* VA of CMC error record buffer */#else- unsigned __int64 cpu$pq_cmc_e Brror_record_va;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/ void *cpu$pl_cmc_error_record_va_l;6 unsigned int cpu$il_cmc_error_record_va_h;/ } cpu$r_cmc_error_record_va_fields;, } cpu$r_cmc_error_record_va_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever p Ctr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_cpe_error_record_va; /* VA of CPE error record buffer */#else- unsigned __int64 cpu$pq_cpe_error_record_va;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif/ void *cpu$pl_cpe_err Dor_record_va_l;6 unsigned int cpu$il_cpe_error_record_va_h;/ } cpu$r_cpe_error_record_va_fields;, } cpu$r_cpe_error_record_va_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB cpu$r_cbb_cpuid_mask; /* Embedded CBB block */N __struct { E /* Compatability offset cells */) __int64 cpu$q_cbb_fill_1 [6]; __union {T unsigned int cpu$l_cpuid_mask; /* CPU ID in longword bitmask form */X unsigned __int64 cpu$q_cpuid_mask; /* CPU ID in quadword bitmask form */1 } cpu$r_cbb_cpumask_data_overlay;* __int64 cpu$q_cbb_fill_2 [15];/ } cpu$r_cbb_cpumask_compat_overlay;$ } cpu$r_cbb_cpumask_overlay;N/* F */N/* Itanium power management data cells. */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifQ int cpu$l_low_power; /* Indicates if power management is on */#pragma __Gnomember_alignmentO int cpu$l_pwr_mgmt_on; /* Incremented when Power Mgmt is on */N __int64 cpu$q_prev_nullcpu; /* Previous NULLCPU value */[ __int64 cpu$q_low_power_entered; /* Number of times a low power state was entered */N/* */N/* CPU Thread data */N/* H */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB cpu$r_cbb_cothread_mask; /* Embedded CBB block */N __struct { /* Compatability offset cells */, __int64 cpu$q_cbbthd_fill_1 [6];^ unsigned __int64 cpu$q_cothread_mask; /* CIPU cothreads in quadword bitmask form */- __int64 cpu$q_cbbthd_fill_2 [15];/ } cpu$r_cbb_thdmask_compat_overlay;$ } cpu$r_cbb_thdmask_overlay;b unsigned __int64 cpu$q_cothreadd_db_qfl; /* Quadword queue to CPUDB which is another thread */N unsigned __int64 cpu$q_cothreadd_db_qbl; /* (Back link) */g unsigned int cpu$l_max_cur_cothd_priority; /* The maximum priority of the cothreads on this core */c unsigned int cpu$l_num_cothreads; /*J How many threads are in the same core with this CPU? */N/* */N/* More processor registers to be saved at system crash */N/* */N/* */N/* BUGcheck LOG buffer area for dump hints/info prior to bugcheck */N/* K */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif char cpu$r_buglog [256];N/* */\/* Data cells to keep track of owner and sequence number of floating point register banks */N/* */ L#pragma __nomember_alignment) unsigned int cpu$l_fp_high_owner_pid;( unsigned int cpu$l_fp_low_owner_pid;3 unsigned __int64 cpu$q_fp_high_sequence_number;2 unsigned __int64 cpu$q_fp_low_sequence_number;N/* */N/* Cells to hold the values in the first two protection key registers */N/* when the system crashes (only the first two are used, for FOE/iCache) */N/* M */# unsigned __int64 cpu$q_bc_pkr0;# unsigned __int64 cpu$q_bc_pkr1;N/* */N/* Keep track of the current power/performance state in this CPU */N/* */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default N to 64-bit pointers */w void *cpu$pq_power_accounting; /* Pointer to (possibly variable length) data to account for CPU pstate time */#else* unsigned __int64 cpu$pq_power_accounting;#endif& unsigned int cpu$l_current_pstate;& unsigned int cpu$l_spare_pstate_l;* unsigned __int64 cpu$q_spare_pstate_q;s int cpu$l_idle_exits; /* Decrement each time we exit idle. If <=0, stop saving power in idle. */% unsigned int cpu$l_spare_counter;, unsigned __int O64 cpu$q_idle_phl_stopped;2 unsigned __int64 cpu$q_idle_phl_restart_abort;N/* */N/* Keep track of AR.RUC and related fields of this CPU */N/* */% unsigned int cpu$l_ruc_soft_tick;" unsigned int cpu$l_ruc_spare1;$ unsigned __int64 cpu$q_ruc_base;h unsigned __int64 cpu$q_ruc_in_use_by_host_mode; /* Used to store theP "CPU unavailable" time on VM */N/* */N/* Add new cells to hold the ITC and RUC values at every timer interrupt */N/* Also add new cells to hold the ITC and RUC values at the time of crash */N/* */b unsigned __int64 cpu$q_last_timer_int_itc; /* ITC value at the time of last timer interrupt */b unsigned __int64 cpu$q_last_timer_int_ruc; /* RU QC value at the time of last timer interrupt */N unsigned __int64 cpu$q_bc_itc; /* ITC value at the time of crash */N unsigned __int64 cpu$q_bc_ruc; /* RUC value at the time of crash */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_point Rer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_zeroed_page_spte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else. unsigned __int64 cpu$pq_zeroed_page_spte_sva;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_proc_correrr_svap_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else/ S unsigned __int64 cpu$pq_proc_correrr_svap_sva;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cpu$pq_proc_mchkabt_svap_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else/ unsigned __int64 cpu$pq_proc_mchkabt_svap_sva;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long / T* And set ptr size default to 64-bit pointers */N void *cpu$pq_untested_page_spte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else0 unsigned __int64 cpu$pq_untested_page_spte_sva;#endifZ unsigned __int64 cpu$iq_lapic_total; /* Track total time accumulated by LAPIC timer */N/* */N/* New cells should be added before this comment */N/* U */b __int64 cpu$q_bc_expansion [8]; /* Make sure there's space at the end for new registers */N/* */V/* End of fixed portion of the per-CPU database. A variable portion may be required */N/* by this CPU type. */N/* */N/* V */N/* Beginning of quadword aligned, variable portion of the per-CPU database. */N/* Access to this is via the VARIABLE_OFFSET and VARIABLE_LENGTH data cells */N/* in the fixed portion of the database. */N/* */ } CPU; #if !defined(__VAXC)6#define cpu$l_curpcb cpu$r_curpcb_overlay.cpu$l_curpcb6#define cpu$l_curktb cpu$r_curpcb_overlay.cpu$l_curktbJ#define cpu$Wl_work_req cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$l_work_reqV#define cpu$v_inv_tbs cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_inv_tbsV#define cpu$v_inv_tba cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_inv_tbaT#define cpu$v_bugchk cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_bugchkZ#define cpu$v_bugchkack cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_bugchkackZ#define cpu$v_recalschd cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_recalscXhdX#define cpu$v_updastsr cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_updastsrd#define cpu$v_update_hwclock cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_update_hwclockX#define cpu$v_work_fqp cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_work_fqpR#define cpu$v_qlost cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_qlostV#define cpu$v_resched cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_reschedX#define cpu$v_virtcons cpu$r_work_req_overlay.cpYu$r_fill_0_.cpu$r_fill_1_.cpu$v_virtconsT#define cpu$v_iopost cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_iopost^#define cpu$v_inv_istream cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_inv_istreamX#define cpu$v_inv_tbsd cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_inv_tbsd^#define cpu$v_inv_tbs_mmg cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_inv_tbs_mmg`#define cpu$v_inv_tbsd_mmg cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_inv_tbsd_mmgZ\#define cpu$v_io_int_aff cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_io_int_aff`#define cpu$v_io_start_aff cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_io_start_affd#define cpu$v_update_sysptbr cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_update_sysptbrV#define cpu$v_perfmon cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_perfmonX#define cpu$v_read_scc cpu$r_work_req_overlay.cpu$r_fill_0_.cpu$r_fill_1_.cpu$v_read_sccn#define cpu$v_cpuspec1 cpu$r_wor[k_req_overlay.cpu$r_cpuspec_overlay.cpu$r_fill_2_.cpu$r_fill_3_.cpu$v_cpuspec1n#define cpu$v_cpuspec2 cpu$r_work_req_overlay.cpu$r_cpuspec_overlay.cpu$r_fill_2_.cpu$r_fill_3_.cpu$v_cpuspec2n#define cpu$v_cpuspec3 cpu$r_work_req_overlay.cpu$r_cpuspec_overlay.cpu$r_fill_2_.cpu$r_fill_3_.cpu$v_cpuspec3n#define cpu$v_cpuspec4 cpu$r_work_req_overlay.cpu$r_cpuspec_overlay.cpu$r_fill_2_.cpu$r_fill_3_.cpu$v_cpuspec49#define cpu$q_work_fqfl cpu$r_ifq_overlay.cpu$q_work_fqfl7#define cpu$q_work_ifq cpu$r_i \fq_overlay.cpu$q_work_ifq;#define cpu$q_sys_hwpcb cpu$r_hwpcb_overlay.cpu$q_sys_hwpcb7#define cpu$q_sys_ksp cpu$r_hwpcb_overlay.cpu$q_sys_kspE#define cpu$q_sys_astsr_asten cpu$r_ast_overlay.cpu$q_sys_astsr_astenI#define cpu$v_sys_asten cpu$r_ast_overlay.cpu$r_ast_bits0.cpu$v_sys_astenI#define cpu$v_sys_astsr cpu$r_ast_overlay.cpu$r_ast_bits0.cpu$v_sys_astsrB#define cpu$q_term_hwpcb cpu$r_term_hwpcb_overlay.cpu$q_term_hwpcb>#define cpu$q_term_ksp cpu$r_term_hwpcb_overlay.cpu$q_term_kspL#d]efine cpu$q_term_astsr_asten cpu$r_term_ast_overlay.cpu$q_term_astsr_astenU#define cpu$v_term_asten cpu$r_term_ast_overlay.cpu$r_term_ast_bits0.cpu$v_term_astenU#define cpu$v_term_astsr cpu$r_term_ast_overlay.cpu$r_term_ast_bits0.cpu$v_term_astsr:#define cpu$b_bc_flags cpu$r_bc_flags_union.cpu$b_bc_flagsB#define cpu$r_bc_flag_bits cpu$r_bc_flags_union.cpu$r_bc_flag_bitsB#define cpu$v_bc_ast_called cpu$r_bc_flag_bits.cpu$v_bc_ast_called:#define cpu$v_bc_astdel cpu$r_bc_flag_bits.cpu$v_bc_astdel^D#define cpu$v_bc_xsave_saved cpu$r_bc_flag_bits.cpu$v_bc_xsave_savedH#define cpu$v_bc_faulty_towers cpu$r_bc_flag_bits.cpu$v_bc_faulty_towers8#define cpu$v_bc_imsem cpu$r_bc_flag_bits.cpu$v_bc_imsemJ#define cpu$v_bc_alphareg_saved cpu$r_bc_flag_bits.cpu$v_bc_alphareg_savedC#define cpu$b_bc_prevmode cpu$r_bc_prevmode_union.cpu$b_bc_prevmodeE#define cpu$b_bc_prevstack cpu$r_bc_prevmode_union.cpu$b_bc_prevstack/#define cpu$q_kernel cpu$r_fill_4_.cpu$q_kernelM#define cpu$q_system_context cpu$r __fill_4_.cpu$r_fill_5_.cpu$q_system_context?#define cpu$q_mpsynch cpu$r_fill_4_.cpu$r_fill_5_.cpu$q_mpsynch-#define cpu$l_flags cpu$r_fill_6_.cpu$l_flags;#define cpu$v_sched cpu$r_fill_6_.cpu$r_fill_7_.cpu$v_sched?#define cpu$v_forever cpu$r_fill_6_.cpu$r_fill_7_.cpu$v_forever?#define cpu$v_newprim cpu$r_fill_6_.cpu$r_fill_7_.cpu$v_newprim?#define cpu$v_pswitch cpu$r_fill_6_.cpu$r_fill_7_.cpu$v_pswitchA#define cpu$v_bc_stack cpu$r_fill_6_.cpu$r_fill_7_.cpu$v_bc_stackE#define cpu$v_bc_c`ontext cpu$r_fill_6_.cpu$r_fill_7_.cpu$v_bc_context[#define cpu$v_user_capabilities_set cpu$r_fill_6_.cpu$r_fill_7_.cpu$v_user_capabilities_setO#define cpu$v_reset_low_power cpu$r_fill_6_.cpu$r_fill_7_.cpu$v_reset_low_power3#define cpu$l_intflags cpu$r_fill_8_.cpu$l_intflagsA#define cpu$v_stopping cpu$r_fill_8_.cpu$r_fill_9_.cpu$v_stoppingI#define cpu$v_rescheduling cpu$r_fill_8_.cpu$r_fill_9_.cpu$v_rescheduling\#define cpu$pq_mchk_crash_area_va cpu$r_mchk_crash_area_va_overlay.cpu$pq_mchka_crash_area_va#define cpu$pl_mchk_crash_area_va_l cpu$r_mchk_crash_area_va_overlay.cpu$r_mchk_crash_area_va_fields.cpu$pl_mchk_crash_area_va_l#define cpu$il_mchk_crash_area_va_h cpu$r_mchk_crash_area_va_overlay.cpu$r_mchk_crash_area_va_fields.cpu$il_mchk_crash_area_va_hP#define cpu$pq_logout_area_va cpu$r_logout_area_va_overlay.cpu$pq_logout_area_vap#define cpu$pl_logout_area_va_l cpu$r_logout_area_va_overlay.cpu$r_logout_area_va_fields.cpu$pl_logout_area_va_lp#define cpu$il_logout_area_va_h cpbu$r_logout_area_va_overlay.cpu$r_logout_area_va_fields.cpu$il_logout_area_va_h@#define cpu$l_pcsample_flags cpu$r_fill_10_.cpu$l_pcsample_flagsQ#define cpu$v_pcsample_active cpu$r_fill_10_.cpu$r_fill_11_.cpu$v_pcsample_active<#define cpu$l_io_aff_flags cpu$r_fill_12_.cpu$l_io_aff_flagsS#define cpu$v_io_aff_fkb_inuse cpu$r_fill_12_.cpu$r_fill_13_.cpu$v_io_aff_fkb_inuseM#define cpu$v_port_assigned cpu$r_fill_12_.cpu$r_fill_13_.cpu$v_port_assignedS#define cpu$v_distributed_ints cpu$r_fill_12_.cpcu$r_fill_13_.cpu$v_distributed_intsH#define cpu$q_capabilities cpu$r_capabilities_overlay.cpu$q_capabilitiesH#define cpu$l_capabilities cpu$r_capabilities_overlay.cpu$l_capabilitiesR#define cpu$l_untested_page_state cpu$r_untested_overlay.cpu$l_untested_page_state^#define cpu$w_untested_chunks cpu$r_untested_overlay.cpu$r_untested_bits.cpu$w_untested_chunks^#define cpu$v_lastpage_tested cpu$r_untested_overlay.cpu$r_untested_bits.cpu$v_lastpage_testedL#define cpu$v_mcheck cpu$r_untested_overlay.dcpu$r_untested_bits.cpu$v_mcheckX#define cpu$v_memory_write cpu$r_untested_overlay.cpu$r_untested_bits.cpu$v_memory_writeD#define cpu$l_transition_flags cpu$r_fill_14_.cpu$l_transition_flagsG#define cpu$v_auto_start cpu$r_fill_14_.cpu$r_fill_15_.cpu$v_auto_startG#define cpu$v_nobindings cpu$r_fill_14_.cpu$r_fill_15_.cpu$v_nobindingsb#define cpu$pq_init_error_record_va cpu$r_init_error_record_va_overlay.cpu$pq_init_error_record_va#define cpu$pl_init_error_record_va_l cpu$r_init_error_record_vae_overlay.cpu$r_init_error_record_va_fields.cpu$pl_init_error_record\_va_l#define cpu$il_init_error_record_va_h cpu$r_init_error_record_va_overlay.cpu$r_init_error_record_va_fields.cpu$il_init_error_record\_va_h_#define cpu$pq_mca_error_record_va cpu$r_mca_error_record_va_overlay.cpu$pq_mca_error_record_va#define cpu$pl_mca_error_record_va_l cpu$r_mca_error_record_va_overlay.cpu$r_mca_error_record_va_fields.cpu$pl_mca_error_record_va_l#define cpu$il_mca_error_record_va_h cpu$r_mca_error_rfecord_va_overlay.cpu$r_mca_error_record_va_fields.cpu$il_mca_error_record_va_h_#define cpu$pq_cmc_error_record_va cpu$r_cmc_error_record_va_overlay.cpu$pq_cmc_error_record_va#define cpu$pl_cmc_error_record_va_l cpu$r_cmc_error_record_va_overlay.cpu$r_cmc_error_record_va_fields.cpu$pl_cmc_error_record_va_l#define cpu$il_cmc_error_record_va_h cpu$r_cmc_error_record_va_overlay.cpu$r_cmc_error_record_va_fields.cpu$il_cmc_error_record_va_h_#define cpu$pq_cpe_error_record_va cpu$r_cpe_error_record_vag_overlay.cpu$pq_cpe_error_record_va#define cpu$pl_cpe_error_record_va_l cpu$r_cpe_error_record_va_overlay.cpu$r_cpe_error_record_va_fields.cpu$pl_cpe_error_record_va_l#define cpu$il_cpe_error_record_va_h cpu$r_cpe_error_record_va_overlay.cpu$r_cpe_error_record_va_fields.cpu$il_cpe_error_record_va_hK#define cpu$r_cbb_cpuid_mask cpu$r_cbb_cpumask_overlay.cpu$r_cbb_cpuid_mask#define cpu$l_cpuid_mask cpu$r_cbb_cpumask_overlay.cpu$r_cbb_cpumask_compat_overlay.cpu$r_cbb_cpumask_data_overlay.cpu$l_chpuid_mask#define cpu$q_cpuid_mask cpu$r_cbb_cpumask_overlay.cpu$r_cbb_cpumask_compat_overlay.cpu$r_cbb_cpumask_data_overlay.cpu$q_cpuid_maskQ#define cpu$r_cbb_cothread_mask cpu$r_cbb_thdmask_overlay.cpu$r_cbb_cothread_maskj#define cpu$q_cothread_mask cpu$r_cbb_thdmask_overlay.cpu$r_cbb_thdmask_compat_overlay.cpu$q_cothread_mask"#endif /* #if !defined(__VAXC) */ N#define CPU$K_LENGTH 4376 /* Total fixed structure size */N#define CPU$C_LENGTH 4376 /* Total i fixed structure size */#define CPU$M_AGE_DATA 0x1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sched_ds {#pragma __nomember_alignmentN unsigned __int64 cpu$q_acc_run; /* accumulated runtime */U unsigned __int64 cpu$q_proc_count; /* # of process run at this priority level */N unsigned __int64 cpu$q j_acc_interrupt; /* accumulated interrupt time */N unsigned __int64 cpu$q_acc_waitime; /* accumulated wait time */ __union {N unsigned __int64 cpu$q_sched_flags; /* Scheduling flags */ __struct {N unsigned cpu$v_age_data : 1; /* Indicates data needs to be aged */( unsigned cpu$v_fill_27_ : 7; } cpu$r_fill_26_; } cpu$r_fill_25_; } SCHED_DS; #if !defined(__VAXC):#define cpu$q_sched_flags cpku$r_fill_25_.cpu$q_sched_flagsC#define cpu$v_age_data cpu$r_fill_25_.cpu$r_fill_26_.cpu$v_age_data"#endif /* #if !defined(__VAXC) */ #define CPU$K_SCHED_LENGTH 40N/* byte length of each per-priority entry */N/* in the SCHED_DATA data structure */ "#pragma required_pointer_size save"#pragma required_pointer_size longtypedef CPU * CPU_PQ;##pragma required_pointer_size shorttypedef CPU * CPU_PL;%#pragma relquired_pointer_size restore  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CPUDEF_LOADED */ ww`[UM/***************************************************************************/M/** m **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** n **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********o****************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */H/* Source: 22-APR-1993 10:44:40 $1$DGA8345:[LIB_H.SRC]CQBICDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CQBICDEF ***/#ifndef p__CQBICDEF_LOADED#define __CQBICDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus exteqrn "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */I/* CQBIC definitions r */N/*-- */N/* Offsets within page containing interprocessor doorbell registers */N#define CQBIC$W_INTPR0 320 /*Arbiter doorbell */N#define CQBIC$W_INTPR1 322 /*Auxiliary #1 doorbell */N#define CQBIC$W_INTPR2 324 /*Auxiliary #2 doorbell */N#define CQBIC$W_INTPR3 326 /*Auxiliary #3s doorbell */N#define CQBIC$W_INTPR4 328 /*Auxiliary #4 doorbell */N#define CQBIC$W_INTPR5 330 /*Auxiliary #5 doorbell */N#define CQBIC$W_INTPR6 332 /*Auxiliary #6 doorbell */N#define CQBIC$W_INTPR7 334 /*Auxiliary #7 doorbell */N/* Offsets within page containing SCR, memory and map registers */N#define CQBIC$L_SCR 0 /*System configuration */N t#define CQBIC$L_DSER 4 /*DMA system error */N#define CQBIC$L_MEAR 8 /*DMA master error */N#define CQBIC$L_SEAR 12 /*DMA slave error */N#define CQBIC$L_MAP_BASE 16 /*Scatter/gather map base */#define CQBIC$M_INTPR_DBIRQ 0x1 #define CQBIC$M_INTPR_LMEAE 0x20 #define CQBIC$M_INTPR_DBIIE 0x40"#define CQBIC$M_INTPR_AUXHLT 0x100!#define CQBIC$M_INTPR_TBIA 0x4000##define CQBI uC$M_INTPR_DMAQME 0x8000 typedef struct _intpr {N unsigned cqbic$v_intpr_dbirq : 1; /* Doorbell interrupt request */% unsigned cqbic$v_intpr_mbz_1 : 4;N unsigned cqbic$v_intpr_lmeae : 1; /* Local memory enable */N unsigned cqbic$v_intpr_dbiie : 1; /* Doorbell interrupt enable */% unsigned cqbic$v_intpr_mbz_2 : 1;N unsigned cqbic$v_intpr_auxhlt : 1; /* Auxiliary halt */% unsigned cqbic$v_intpr_mbz_3 : 5;N unsignved cqbic$v_intpr_tbia : 1; /* Xlate buffer invalidate all */N unsigned cqbic$v_intpr_dmaqme : 1; /* DMA memory space error */ } INTPR; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CQBICDEF_LOADED */ www [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copxyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. y **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:37 by OpenVMS SDL V3.7 */G/* Source: 06-AUG-2007 11:18:24 $1$DGA8345:[LIB_H.SRC]CRABDEF.SDL;1 *//*********************************** z*********************************************************************************************//*** MODULE $CRABDEF ***/#ifndef __CRABDEF_LOADED#define __CRABDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragm{a __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_unio|n#endif#endif  #include  g#define CRAB$K_LENGTH 112 /* Length of base structure (not including allocation array) */  9#ifdef __cplusplus /* Define structure prototypes */ struct _spl; struct _adp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _crab {}#pragma __nomember_alignmentN struct _crab *crab$l_flink; /* Forward link */N struct _crab *crab$l_blink; /* Backward link */N unsigned short int crab$w_size; /* Structure size in bytes */N unsigned char crab$b_type; /* Structure type */N unsigned char crab$b_subtype; /* Structure subtype */N struct _spl *crab$l_spinlock; /* Address of dynamic spinlock ~ */X void *crab$l_wqfl; /* Wait queue flink--points to links in CRCTX */N void *crab$l_wqbl; /* Wait queue blink */N struct _adp *crab$ps_adp; /* Address of ADP */N unsigned int crab$l_total_items; /* Total number of items */N unsigned int crab$l_alloc_gran_mask; /* Allocation granularity mask */N struct _spl *crab$l_nosync_spinlock; /* Address of dynamic spinlock */l void (*crab$ps_dealloc_cb)(); /* Points to a callback routine for dealloc_cnt_Res */R void *crab$ps_ringbuffer; /* Pointer to a CRCTX debug ring buffer */N/* base item number managed by */N unsigned int crab$l_base_item; /* this crab */N unsigned int crab$l_valid_desc_cnt; /* Count of valid descriptors */U unsigned int crab$l_insfmapreg_cnt; /* X-13a Number of SS$_INSFMAPREG failures */N __union { /* X-13b Spare field for debug */ void *crab$ps_spare; int crab$l_spare; } crab$r_spare_union;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment* unsigned char crab$b_ucb_fkb [48]; __struct {N struct _fkb *crab$l_fqfl; /*FORK QUEUE FORWARD LINK */N struct _fkb *crab$l_fqbl; /*FORK QUEUE BACKWARD LINK */N unsigned short int crab$w_fsize; /*SIZE OF FKB IN BYTES */N unsigned char crab$b_ftype; /*STRUCTURE TYPE OF FKB */N unsigned char crab$b_flck; /*FORK LOCK NUMBER */N void (*crab$l_fpc)(); /*FORK PC */N __int64 crab$q_fr3; /*FORK R3  */N __int64 crab$q_fr4; /*FORK R4 */$ } crab$r_ucb_fkb_struct; } crab$r_crab_fkb_union;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned int crab$l_alloc_array; /* Start of Allocation array */#pragma __nomember_alignment char crab$b_fill_0_ [4];  } CRAB; #if !defined(__VAXC)6#define crab$ps_spare crab$r_spare_union.crab$ps_spare4#define crab$l_spare crab$r_spare_union.crab$l_spareK#define crab$l_fqfl crab$r_crab_fkb_union.crab$r_ucb_fkb_struct.crab$l_fqflK#define crab$l_fqbl crab$r_crab_fkb_union.crab$r_ucb_fkb_struct.crab$l_fqblM#define crab$w_fsize crab$r_crab_fkb_union.crab$r_ucb_fkb_struct.crab$w_fsizeM#define crab$b_ftype crab$r_crab_fkb_union.crab$r_ucb_fkb_struct.crab$b_ftypeK#define crab$b_flck crab$r_crab_fkb_union.crab$r_ucb_fkb_struct.crab$b_flckI#define crab$l_fpc crab$r_crab_fkb_union.crab$r_ucb_fkb_struct.crab$l_fpcI#define crab$q_fr3 crab$r_crab_fkb_union.crab$r_ucb_fkb_struct.crab$q_fr3I#define crab$q_fr4 crab$r_crab_fkb_union.crab$r_ucb_fkb_struct.crab$q_fr4"#endif /* #if !defined(__VAXC) */   c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _crab_array {#pragma __nomember_alignmentN unsigned int crab_array$l_num; /* Starting item number */N unsigned int crab_array$l_cnt; /* Item count */ } CRAB_ARRAY;N#define CRAB_ARRAY$K_LENGTH 8 /* Length of CRAB array entry */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CRABDEF_LOADED */ ww0[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7 -Oct-2024 15:22:31 by OpenVMS SDL V3.7 */G/* Source: 18-MAY-1994 14:53:01 $1$DGA8345:[LIB_H.SRC]CRAMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CRAMDEF ***/#ifndef __CRAMDEF_LOADED#define __CRAMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CRAM - CSR Register Access Mailbox */N/* */O/* The CSR register access mailbox describes the remote I/O CSR access to be */N /* performed. */N/* */N/*- */ #define CRAM$M_IN_USE 0x1#define CRAM$M_DER 0x2!#define CRAM$M_CMD_VAL 0x3FFFFFFF$#define CRAM$M_CMD_BRIDGE 0x40000000##define CRAM$M_CMD_WRITE 0x80000000#define CRAM$M_MBX_DONE 0x1#define CRAM$M_MBX_ERROR 0x2N#define CRAM$K_LENGTH 128  /* Length of structure */S#define CRAM$S_CRAMDEF 128 /* Old CRAM size field for compatibility */N/* Define common command indices */N#define CRAMCMD$K_RDQUAD32 1 /* Quadword read in 32 bit space */N#define CRAMCMD$K_RDLONG32 2 /* Longword " " " " " */N#define CRAMCMD$K_RDWORD32 3 /* Word " " " " " */N#define CRAMCMD$K_RDBYTE32 4 /* Byte " " " " " */N#define CRAMCMD$K_WTQUAD32 5 /* Quadword write " " " " */N#define CRAMCMD$K_WTLONG32 6 /* Longword " " " " " */N#define CRAMCMD$K_WTWORD32 7 /* Word " " " " " */N#define CRAMCMD$K_WTBYTE32 8 /* Byte " " " " " */N#define CRAMCMD$K_RDQUAD64 9 /* Quadword read in 64 bit space */N#define CRAMCMD$K_RDLONG64 10 /* Longword " " " " " */N#define CRAMCMD$K_RDWORD64 11 /* Word " " " " " */N#define CRAMCMD$K_RDBYTE64 12 /* Byte " " " " " */N#define CRAMCMD$K_WTQUAD64 13 /* Quadword write " " " " */N#define CRAMCMD$K_WTLONG64 14 /* Longword " " " " " */N#define CRAMCMD$K_WTWORD64 15 /* Word " " " " " */N#define CRAMCMD$K_WTBYTE64 16 /* Byte " " " " " */N#define CRAMCMD$K_RDTRIBYTE32 17 /* Tribyte read " 32 " " */N#define CRAMCMD$K_WTTRIBYTE32 18 /* Tribyte write " 32 " " */N#define CRAMCMD$K_RDTRIBYTE64 19 /* Tribyte read " 64 " " */N#define CRAMCMD$K_WTTRIBYTE64 20 /* Tribyte write " 64 " " */#define CRAMCMD$K_MININDEX 1#define CRAMCMD$K_MAXINDEX 20  9#ifdef __cplusplus /* Define structure prototypes */ struct _idb; struct _ucb; struct _adp; #endif /* #ifdef __cplusplus */ c#if !d efined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cram {#pragma __nomember_alignmentN struct _cram *cram$l_flink; /* Forward link */N struct _cram *cram$l_blink; /* Backward link */N unsigned short int cram$w_size; /* Structure size in bytes */N unsigned char cram$b_type; /* Structure type */N unsigned char cram$b_subtype; /* Structure subtype */N void *cram$l_mbpr; /* Address of MBPR */N unsigned __int64 cram$q_hw_mbx; /* PA of hardward mailbox */N unsigned __int64 cram$q_queue_time; /* Queue timeout time */N unsigned __int64 cram$q_wait_time; /* Wait timeout */N unsigned int cram$l_driver; /* Spare longw ord for driver */N struct _idb *cram$l_idb; /* Pointer to IDB */N struct _ucb *cram$l_ucb; /* Pointer to UCB */ __union { __union {N unsigned int cram$l_cram_flags; /* Flags bitmask */ __struct {N unsigned cram$v_in_use : 1; /* CRAM is valid */N unsigned cram$v_der : 1; /* Disable-error-reporting */, un signed cram$v_fill_6_ : 6;! } cram$r_fill_1_; } cram$r_fill_0_;$ } cram$r_cram_flags_overlay;N struct _adp *cram$l_adp; /* Pointer to ADP */ char cram$b_filler1 [4];N/* This piece must be 64 byte aligned - this is the hardware mailbox */ __union {N unsigned int cram$l_command; /* Bus command */ __union {) unsigned int cram$l_cmd_bits; __struct {N unsigned cram$v_cmd_val : 30; /* Remote bus command bits */N unsigned cram$v_cmd_bridge : 1; /* BRIDGE bit */N unsigned cram$v_cmd_write : 1; /* WRITE bit */! } cram$r_fill_3_; } cram$r_fill_2_; } cram$r_cmd_overlay;N unsigned char cram$b_byte_mask; /* Active byte mask */N unsigned char cram$b_filler2; /* SBZ */N  unsigned char cram$b_hose; /* I/O bus number */N unsigned char cram$b_filler3; /* SBZ */N unsigned __int64 cram$q_rbadr; /* Remote bus address */ __union {N unsigned __int64 cram$q_wdata; /* Data to be written */N unsigned int cram$l_wdata; /* Data to be written */N unsigned short int cram$w_wdata; /* Data to be written */N unsi gned char cram$b_wdata; /* Data to be written */ } cram$r_wdata_overlay;N unsigned __int64 cram$q_filler4; /* SBZ */ __union {N unsigned __int64 cram$q_rdata; /* Returned read data */" unsigned int cram$l_rdata;( unsigned short int cram$w_rdata;# unsigned char cram$b_rdata; } cram$r_rdata_overlay; __union { __union {N unsigned short int cram$w_mbx_ flags; /* Flags bitmask */ __struct {O unsigned cram$v_mbx_done : 1; /* Mailbox operation completed */N unsigned cram$v_mbx_error : 1; /* Error in operation */, unsigned cram$v_fill_7_ : 6;! } cram$r_fill_5_; } cram$r_fill_4_;# } cram$r_mbx_flags_overlay;N unsigned short int cram$w_error_bits [3]; /* Device specific error bits */N unsigned __int64 cram$q_filler5 [2]; /* SBZ  */ } CRAM; #if !defined(__VAXC)T#define cram$l_cram_flags cram$r_cram_flags_overlay.cram$r_fill_0_.cram$l_cram_flags[#define cram$v_in_use cram$r_cram_flags_overlay.cram$r_fill_0_.cram$r_fill_1_.cram$v_in_useU#define cram$v_der cram$r_cram_flags_overlay.cram$r_fill_0_.cram$r_fill_1_.cram$v_der8#define cram$l_command cram$r_cmd_overlay.cram$l_commandI#define cram$l_cmd_bits cram$r_cmd_overlay.cram$r_fill_2_.cram$l_cmd_bitsV#define cram$v_cmd_val cram$r_cmd_overlay.cram$r_fill_2_.cram$r_fill_3_.cram$v_cmd_val\#define cram$v_cmd_bridge cram$r_cmd_overlay.cram$r_fill_2_.cram$r_fill_3_.cram$v_cmd_bridgeZ#define cram$v_cmd_write cram$r_cmd_overlay.cram$r_fill_2_.cram$r_fill_3_.cram$v_cmd_write6#define cram$q_wdata cram$r_wdata_overlay.cram$q_wdata6#define cram$l_wdata cram$r_wdata_overlay.cram$l_wdata6#define cram$w_wdata cram$r_wdata_overlay.cram$w_wdata6#define cram$b_wdata cram$r_wdata_overlay.cram$b_wdata6#define cram$q_rdata cram$r_rdata_overla y.cram$q_rdata6#define cram$l_rdata cram$r_rdata_overlay.cram$l_rdata6#define cram$w_rdata cram$r_rdata_overlay.cram$w_rdata6#define cram$b_rdata cram$r_rdata_overlay.cram$b_rdataQ#define cram$w_mbx_flags cram$r_mbx_flags_overlay.cram$r_fill_4_.cram$w_mbx_flags^#define cram$v_mbx_done cram$r_mbx_flags_overlay.cram$r_fill_4_.cram$r_fill_5_.cram$v_mbx_done`#define cram$v_mbx_error cram$r_mbx_flags_overlay.cram$r_fill_4_.cram$r_fill_5_.cram$v_mbx_error"#endif /* #if !defined(__VAXC) */ N/* M ailbox data structure used by hardware and bootstrap code */#define HW_CRAM$M_MBX_DONE 0x1#define HW_CRAM$M_MBX_ERROR 0x2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _hw_cram {#pragma __nomember_alignmentN unsigned int hw_cram$l_command; /* Bus command */N unsigned char hw_cram$b_byte_mask; /* Active byte mask */N unsigned char hw_cram$b_filler6; /* SBZ */N unsigned char hw_cram$b_hose; /* I/O bus number */N unsigned char hw_cram$b_filler7; /* SBZ */N unsigned __int64 hw_cram$q_rbadr; /* Remote bus address */N unsigned __int64 hw_cram$q_wdata; /* Data to be written */N unsigned __int64 hw_cram$q_filler8; /* SBZ  */N unsigned __int64 hw_cram$q_rdata; /* Returned read data */ __union { __union {N unsigned short int hw_cram$w_mbx_flags; /* Flags bitmask */ __struct {R unsigned hw_cram$v_mbx_done : 1; /* Mailbox operation completed */N unsigned hw_cram$v_mbx_error : 1; /* Error in operation */0 unsigned hw_cram$v_fill_10_ : 6;$ } hw_cram$r_fill_9_;  } hw_cram$r_fill_8_;& } hw_cram$r_mbx_flags_overlay;Q unsigned short int hw_cram$w_error_bits [3]; /* Device specific error bits */N unsigned __int64 hw_cram$q_filler9 [2]; /* SBZ */ } HW_CRAM; #if !defined(__VAXC)]#define hw_cram$w_mbx_flags hw_cram$r_mbx_flags_overlay.hw_cram$r_fill_8_.hw_cram$w_mbx_flagsm#define hw_cram$v_mbx_done hw_cram$r_mbx_flags_overlay.hw_cram$r_fill_8_.hw_cram$r_fill_9_.hw_cram$v_mbx_doneo#define hw_cram$v_mbx_error hw_cram$r_mbx_flags_overlay.hw_cram$r_fill_8_.hw_cram$r_fill_9_.hw_cram$v_mbx_error"#endif /* #if !defined(__VAXC) */ N#define HW_CRAM$K_LENGTH 64 /* Length of structure */V#define HW_CRAM$S_HW_CRAMDEF 64 /* Old HW_CRAM size field for compatibility */N/* Command table definition. Note -- the order of the longwords in the */N/* CMDARRAY vector must be the same as the order of the constant command */N/* indices defined above.  */N/* */ "#define CMDTABLEHEADER$K_LENGTH 12  9#ifdef __cplusplus /* Define structure prototypes */ struct _adp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cmdtable {#pragma __nomember_a lignment! struct _adp *cmdtable$ps_adp;N unsigned int cmdtable$l_bus_type; /* Bus Type */N unsigned short int cmdtable$w_size; /* Structure size in bytes */N unsigned char cmdtable$b_type; /* Structure type */N unsigned char cmdtable$b_subtype; /* Structure subtype */#if defined(__VAXC)! char cmdtable$l_cmd_vector[];#else1#define cmdtable$l_cmd_vector cmdtable$r_cmdarray"#endif /* #if defined(__VAXC) */ __struct {Z unsigned int cramcmd$l_fill2; /* needed because command indices are one based */N unsigned int cramcmd$l_rdquad32; /* Quadword read in 32 bit space */N unsigned int cramcmd$l_rdlong32; /* Longword " " " " " */N unsigned int cramcmd$l_rdword32; /* Word " " " " " */N unsigned int cramcmd$l_rdbyte32; /* Byte " " " " " */N unsigned int cramcmd$l_wtquad32; /* Quadword write " " " " */N unsigned int cramcmd$l_wtlong32; /* Longword " " " " " */N unsigned int cramcmd$l_wtword32; /* Word " " " " " */N unsigned int cramcmd$l_wtbyte32; /* Byte " " " " " */N unsigned int cramcmd$l_rdquad64; /* Quadword read in 64 bit space */N unsigned int cramcmd$l_rdlong64; /* Longword " " " " " */N unsigned int cramcmd$l_rdword64; /* Word " " " " " */N unsigned int cramcmd$l_rdbyte64; /* Byte " " " " " */N unsigned int cramcmd$l_wtquad64; /* Quadword write " " " " */N unsigned int cramcmd$l_wtlong64; /* Longword " " " " " */N unsigned int cramcmd$l_wtword64; /* Word " " " " " */N unsigned int cramcmd$l_wtbyte64; /* Byte " " " " " */N unsigned int cramcmd$l_rdtribyte32; /* Tribyte read " 32 " " */N unsigned int cramcmd$l_wtt ribyte32; /* Tribyte write " 32 " " */N unsigned int cramcmd$l_rdtribyte64; /* Tribyte read " 64 " " */N unsigned int cramcmd$l_wttribyte64; /* Tribyte write " 64 " " */ } cmdtable$r_cmdarray; } CMDTABLE; #if !defined(__VAXC)A#define cramcmd$l_rdquad32 cmdtable$r_cmdarray.cramcmd$l_rdquad32A#define cramcmd$l_rdlong32 cmdtable$r_cmdarray.cramcmd$l_rdlong32A#define cramcmd$l_rdword32 cmdtable$r_cmdarray.cramcmd$l_rdword32A#define cramcmd$l_rdbyte32 cmdtable$r_cmdarray.cramcmd$l_rdbyte32A#define cramcmd$l_wtquad32 cmdtable$r_cmdarray.cramcmd$l_wtquad32A#define cramcmd$l_wtlong32 cmdtable$r_cmdarray.cramcmd$l_wtlong32A#define cramcmd$l_wtword32 cmdtable$r_cmdarray.cramcmd$l_wtword32A#define cramcmd$l_wtbyte32 cmdtable$r_cmdarray.cramcmd$l_wtbyte32A#define cramcmd$l_rdquad64 cmdtable$r_cmdarray.cramcmd$l_rdquad64A#define cramcmd$l_rdlong64 cmdtable$r_cmdarray.cramcmd$l_rdlong64A#define cramcmd$l_rdword64 cmdtable$r_cmdarray.cra mcmd$l_rdword64A#define cramcmd$l_rdbyte64 cmdtable$r_cmdarray.cramcmd$l_rdbyte64A#define cramcmd$l_wtquad64 cmdtable$r_cmdarray.cramcmd$l_wtquad64A#define cramcmd$l_wtlong64 cmdtable$r_cmdarray.cramcmd$l_wtlong64A#define cramcmd$l_wtword64 cmdtable$r_cmdarray.cramcmd$l_wtword64A#define cramcmd$l_wtbyte64 cmdtable$r_cmdarray.cramcmd$l_wtbyte64G#define cramcmd$l_rdtribyte32 cmdtable$r_cmdarray.cramcmd$l_rdtribyte32G#define cramcmd$l_wttribyte32 cmdtable$r_cmdarray.cramcmd$l_wttribyte32G #define cramcmd$l_rdtribyte64 cmdtable$r_cmdarray.cramcmd$l_rdtribyte64G#define cramcmd$l_wttribyte64 cmdtable$r_cmdarray.cramcmd$l_wttribyte64"#endif /* #if !defined(__VAXC) */ N#define CMDTABLE$K_LENGTH 96 /* Length of structure */W#define CMDTABLE$S_CMDTABLEDEF 96 /* Old CMDTABLE size field for compatibility */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CRAMDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************************************************** *****************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */H/* Source: 18-MAY-1994 14:32:07 $1$DGA8345:[LIB_H.SRC]CRAMHDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CRAMHDEF ***/#ifndef __CRAMHDEF_LOADED#define __CRAMHDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CRAMH - CSR Regsiter Access Mailbox Header */N/* */N/* The CSR register access mailbox header de scribes the page of mailboxes */N/* */N/*- */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cramh {#pragma __nomember_alignmentN struct _cramh *cramh$l_flink; /* Forward link  */N struct _cramh *cramh$l_blink; /* Backward link */N unsigned short int cramh$w_size; /* Structure size in bytes */N unsigned char cramh$b_type; /* Structure type */N unsigned char cramh$b_subtype; /* Structure subtype */N unsigned int cramh$l_max; /* Mailbox max index */N unsigned __int64 cramh$q_pa_base; /* Base PA of page */N  unsigned int cramh$l_avail; /* Mailboxes available */N unsigned char cramh$b_map [64]; /* Usage bitmap */N/* Sized for 64KB page max */N char cramh$b_filler [36]; /* SBZ */ } CRAMH;N#define CRAMH$K_LENGTH 128 /* Length of structure */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CRAMHDEF_LOADED */ wwpJ[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************* ***********************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */F/* Source: 18-APR-2017 14:46:54 $1$DGA8345:[LIB_H.SRC]CRBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CRBDEF ***/#ifndef __CRBDEF_LOADED#define __CRBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CRB - CHANNEL REQUEST BLOCK */N/* */ N/* THERE IS ONE CHANNEL REQUEST BLOCK FOR EACH SET OF DEVICES WHOSE */N/* ACCESS TO A SET OF CONTROLLERS MUST BE SYNCHRONIZED. EACH CHANNEL */N/* CONTROL BLOCK ALLOWS UP TO FOUR CONTROLLERS TO WHICH THE INDIVIDUAL */N/* DEVICES CAN BE ATTACHED. */N/*- */#define CRB$M_XZA_CHAN0 0x1#define CRB$M_XZA_CHAN1 0x2#define CRB$M_XZA_ADPERR 0x4#define CRB$M_ BSY 0x1#define CRB$M_UNINIT 0x2N#define CRB$K_VEC1_OFFSET 112 /*Offset to first interrupt block */N#define CRB$K_LENGTH 128 /*LENGTH OF STANDARD CRB */N#define CRB$C_LENGTH 128 /*LENGTH OF STANDARD CRB */"#define CRB$K_SHR_FLINK_OFFSET 144"#define CRB$K_SHR_BLINK_OFFSET 148#define CRB$M_SHARED_INT 0x1#define CRB$M_DISABLE_INT 0x2#define CRB$M_SHARED_QUEUE 0x4  9#ifdef __cplusplus /* Define structure prototypes */ struct _fkb; struct _spl; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _crb {#pragma __nomember_alignmentN struct _fkb *crb$l_fqfl; /*FORK QUEUE FORWARD LINK */N struct _fkb *crb$l_fqbl; /*FORK QUEUE BACKWARD LINK */N unsigned short int crb$w_size; /*SIZE OF CRB IN BYTES */N unsigned char crb$b_type; /*STRUCTURE TYPE FOR CRB */N unsigned char crb$b_flck; /*FORK LOCK NUMBER */N void (*crb$l_fpc)(); /*FORK PC */N __int64 crb$q_fr3; /*FORK R3 */N __int64 crb$q_fr4; /*FORK R4 */N struct _fkb *crb$l_wqfl; /*WAIT QUEUE FORWA RD LINK */N struct _fkb *crb$l_wqbl; /*WAIT QUEUE BACKWARD LINK */ __union { __union {( unsigned char crb$b_tt_type;N unsigned int crb$l_tt_type; /*controler type (DZ11, DZ32) */$ } crb$r_tt_type_overlay;N unsigned int crb$l_xza_sts; /*Coordination for XZA driver */ __struct {N unsigned crb$v_xza_chan0 : 1; /*Channel 0 reinit flag */N unsigned crb$v _xza_chan1 : 1; /*Channel 1 reinit flag */N unsigned crb$v_xza_adperr : 1; /*XZA error/reset flag */' unsigned crb$v_fill_0_ : 5; } crb$r_xza_flags; } crb$r_tt_xza_sts; __union {N unsigned int crb$l_refc; /*REFERENCE COUNT OF UCB'S */& unsigned short int crb$w_refc; } crb$r_refc_overlay; __union {! unsigned char crb$b_mask;N unsigned int crb$l_mask; /*CHANNE L ALLOCATION MASK */ __struct {N unsigned crb$v_bsy : 1; /* CHANNEL IS BUSY (1=YES) */R unsigned crb$v_uninit : 1; /* GENBI CRB is uninitialized. (1=YES) */' unsigned crb$v_fill_1_ : 6; } crb$r_mask_bits; } crb$r_mask_overlay;N void *crb$ps_busarray; /* Bus array for SCSI ports */ __union {N __int64 crb$q_auxstruc; /*Auxiliary structure addr */$  unsigned int crb$l_auxstruc; void *crb$ps_auxstruc;! } crb$r_auxstruc_overlay; __union {N __int64 crb$q_lan_struc; /*Auxiliary pointer for LAN drivers */% unsigned int crb$l_lan_struc; void *crb$ps_lan_struc;" } crb$r_lan_struc_overlay;N __union { /*Auxiliary pointer for SCS drivers */ __int64 crb$q_scs_struc;% unsigned int crb$l_scs_struc; void *crb$ps_scs_struc;" } cr b$r_scs_struc_overlay; __union {P struct _crb *crb$l_timelink; /*Thread of CRB's for periodic wakeup */N void *crb$l_tt_modem; /*modem control timer thread */! } crb$r_timelink_overlay;N unsigned int crb$l_node; /*node number on bus */ __union {N unsigned int crb$l_duetime; /*Due time for periodic wakeup */U void *crb$ps_sysg_dblk; /*workstation SLU port driver/DW interface */  } crb$r_duetime_overlay; __union {O void (*crb$l_toutrout)(); /*Address of periodic wakeup routine */N unsigned int crb$l_tt_timrefc; /*lines with active modem timers */! } crb$r_toutrout_overlay;N struct _spl *crb$ps_dlck; /*ADDRESS OF DEVICE SPINLOCK */N struct _crb *crb$ps_crb_link; /*pointer to next CRB on ADP */ __union {S __int64 crb$q_ctrlr_shutdown; /*Address of controller shutdown routine */' int (*crb$ps_ctrlr_shutdown)();' } crb$r_ctrlr_shutdown_overlay;N unsigned int crb$l_intd [4]; /*DEFAULT TRANSFER VECTOR START */N unsigned int crb$l_intd2 [4]; /*2ND DEFAULT TRANSFER VECTOR START */N/* Verified for X86, Dave Fairbanks */N/* */N/* **** NOTE **** */N/* The following field MUST BE quadword aligned. Any modifications to the */N/* fields above this point must not move this field out of quad alingment. */N/* This is a queue entry that will be managed using the interlocked queue */N/* instructions (see sys$pal_insqtil) which require the flink of the queue */N/* to be qud aligned. */N/* */N/* For Shared Interrupt support, CRBs whose devices must share an interrupt */N/* will be queued using the following fields. The interrupt dispatcher */N/* will walk the queue of CRBs, unpackaging each VEC to call each ISR. */N/* */N/* The offset constants are used to calculate the pointer to the top of */N/* the CRB structure to gain access to its other fields, since the FLINK */N/* and BLINK queue fields will only point to other FLINK and BLINK fields  */N/* in the queue. */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment int crb$l_shr_flink;U void *crb$ps_shr_flink; /* Forward Queue of Shared Interru pt CRBs. */" } crb$r_shr_flink_overlay; __union { int crb$l_shr_blink;V void *crb$ps_shr_blink; /* Backward Queue of Shared Interrupt CRBs. */" } crb$r_shr_blink_overlay; __union {% unsigned __int64 crb$q_flags; __struct {R unsigned crb$v_shared_int : 1; /* Driver supports shared interrupts */] unsigned crb$v_disable_int : 1; /* Device Driver does not want to be disturbed */U unsigned crb$v_s hared_queue : 1; /* CRB is in a shared interrupt queue */' unsigned crb$v_fill_2_ : 5; } crb$r_flag_bits; } crb$r_flags_overlay; } CRB; #if !defined(__VAXC)J#define crb$b_tt_type crb$r_tt_xza_sts.crb$r_tt_type_overlay.crb$b_tt_typeJ#define crb$l_tt_type crb$r_tt_xza_sts.crb$r_tt_type_overlay.crb$l_tt_type4#define crb$l_xza_sts crb$r_tt_xza_sts.crb$l_xza_stsH#define crb$v_xza_chan0 crb$r_tt_xza_sts.crb$r_xza_flags.crb$v_xza_chan0H#define crb$v_xza_chan 1 crb$r_tt_xza_sts.crb$r_xza_flags.crb$v_xza_chan1J#define crb$v_xza_adperr crb$r_tt_xza_sts.crb$r_xza_flags.crb$v_xza_adperr0#define crb$l_refc crb$r_refc_overlay.crb$l_refc0#define crb$w_refc crb$r_refc_overlay.crb$w_refc0#define crb$b_mask crb$r_mask_overlay.crb$b_mask0#define crb$l_mask crb$r_mask_overlay.crb$l_mask>#define crb$v_bsy crb$r_mask_overlay.crb$r_mask_bits.crb$v_bsyD#define crb$v_uninit crb$r_mask_overlay.crb$r_mask_bits.crb$v_uninit<#define crb$q_auxstruc crb$r_auxstruc_overla y.crb$q_auxstruc<#define crb$l_auxstruc crb$r_auxstruc_overlay.crb$l_auxstruc>#define crb$ps_auxstruc crb$r_auxstruc_overlay.crb$ps_auxstruc?#define crb$q_lan_struc crb$r_lan_struc_overlay.crb$q_lan_struc?#define crb$l_lan_struc crb$r_lan_struc_overlay.crb$l_lan_strucA#define crb$ps_lan_struc crb$r_lan_struc_overlay.crb$ps_lan_struc?#define crb$q_scs_struc crb$r_scs_struc_overlay.crb$q_scs_struc?#define crb$l_scs_struc crb$r_scs_struc_overlay.crb$l_scs_strucA#define crb$ps_scs_struc crb$r _scs_struc_overlay.crb$ps_scs_struc<#define crb$l_timelink crb$r_timelink_overlay.crb$l_timelink<#define crb$l_tt_modem crb$r_timelink_overlay.crb$l_tt_modem9#define crb$l_duetime crb$r_duetime_overlay.crb$l_duetime?#define crb$ps_sysg_dblk crb$r_duetime_overlay.crb$ps_sysg_dblk<#define crb$l_toutrout crb$r_toutrout_overlay.crb$l_toutrout@#define crb$l_tt_timrefc crb$r_toutrout_overlay.crb$l_tt_timrefcN#define crb$q_ctrlr_shutdown crb$r_ctrlr_shutdown_overlay.crb$q_ctrlr_shutdownP#define crb$ps_ctrlr_shutdown crb$r_ctrlr_shutdown_overlay.crb$ps_ctrlr_shutdown?#define crb$l_shr_flink crb$r_shr_flink_overlay.crb$l_shr_flinkA#define crb$ps_shr_flink crb$r_shr_flink_overlay.crb$ps_shr_flink?#define crb$l_shr_blink crb$r_shr_blink_overlay.crb$l_shr_blinkA#define crb$ps_shr_blink crb$r_shr_blink_overlay.crb$ps_shr_blink3#define crb$q_flags crb$r_flags_overlay.crb$q_flagsM#define crb$v_shared_int crb$r_flags_overlay.crb$r_flag_bits.crb$v_shared_intO#define crb$v_disable_int crb$r_ flags_overlay.crb$r_flag_bits.crb$v_disable_intQ#define crb$v_shared_queue crb$r_flags_overlay.crb$r_flag_bits.crb$v_shared_queue"#endif /* #if !defined(__VAXC) */ N#define CRB$S_CRBDEF 160 /*OLD CRB SIZE FOR COMPATIBILITY */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CRBDEF_LOADED */ wwq[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */H/* Source: 28-MAY-199 8 13:51:14 $1$DGA8345:[LIB_H.SRC]CRCTXDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CRCTXDEF ***/#ifndef __CRCTXDEF_LOADED#define __CRCTXDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define CRCTX$M_HIGH_PRIO 0x1#define CRCTX$M_ITEM_VALID 0x2  9#ifdef __cplusplus /* Define structure prototypes */ struct _crab; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _crctx {#pragma __nomember_alignmentN struct _crctx *crctx$l_flink; /* Forward link */N struct _crctx *crctx$l_blink; /* Backward link */N unsigned short int crctx$w_size; /* Structure size in bytes */N unsigned char crctx$b_type; /* Structure type */N unsigned char crctx$b_subtype; /* Structure subtype */N struct _crab *crctx$l_crab; /* Address of CRAB  */ __union {N unsigned char crctx$b_flck; /*FORK LOCK NUMBER */N unsigned int crctx$l_flck; /*FORK LOCK NUMBER */ } crctx$r_flck_overlay;N __union { /* Flags */N int crctx$l_flags; /* */N __struct { /* */S unsigned crctx$v_high_prio : 1; /* High priority request, attempt to */N/* allocate resource immediately, */N/* without regard for whether there */N/* are other threads waiting. */Q unsigned crctx$v_item_valid : 1; /* Flag to indicate that the item */N/* number and count fields are valid. */N/* Used for sanity check by DEALLOC_CNT_RES.  */) unsigned crctx$v_fill_0_ : 6; } crctx$r_flag_bits;N/* */ } crctx$r_flags_overlay;N/* */N void *crctx$l_wqfl; /* Stalled requests are queued */Q void *crctx$l_wqbl; /* to CRAB wait queue with these links */ __union { int crctx$l_context1; ! __int64 crctx$q_context1;# } crctx$r_context1_overlay; __union { int crctx$l_context2;! __int64 crctx$q_context2;# } crctx$r_context2_overlay; __union { int crctx$l_context3;! __int64 crctx$q_context3;# } crctx$r_context3_overlay;N int crctx$l_item_cnt; /* Count of allocated items */N int crctx$l_item_num; /* First allocated item num */N int crctx$l_up_bound;  /* Allocation upper bound */N int crctx$l_low_bound; /* Allocation lower bound */N int (*crctx$l_callback)(); /* Callback address */N int (*crctx$l_saved_callback)(); /* Saved callback address */N void *crctx$l_aux_context; /* Auxiliary context longword */N int crctx$l_reserved1; /* Reserved longword */S int crctx$l_dma_adr; /* VMS-only - DMA adr. ret'd by LOAD_MAP */O void *crctx$ps_caller_pc; /* PC of caller of (DE)ALLOC_CNT_RES */ } CRCTX; #if !defined(__VAXC)6#define crctx$b_flck crctx$r_flck_overlay.crctx$b_flck6#define crctx$l_flck crctx$r_flck_overlay.crctx$l_flck9#define crctx$l_flags crctx$r_flags_overlay.crctx$l_flagsS#define crctx$v_high_prio crctx$r_flags_overlay.crctx$r_flag_bits.crctx$v_high_prioU#define crctx$v_item_valid crctx$r_flags_overlay.crctx$r_flag_bits.crctx$v_item_validB#def ine crctx$l_context1 crctx$r_context1_overlay.crctx$l_context1B#define crctx$q_context1 crctx$r_context1_overlay.crctx$q_context1B#define crctx$l_context2 crctx$r_context2_overlay.crctx$l_context2B#define crctx$q_context2 crctx$r_context2_overlay.crctx$q_context2B#define crctx$l_context3 crctx$r_context3_overlay.crctx$l_context3B#define crctx$q_context3 crctx$r_context3_overlay.crctx$q_context3"#endif /* #if !defined(__VAXC) */ N#define CRCTX$K_LENGTH 96 /* Length of structure  */N#define CRCTX$S_CRCTXDEF 96 /* Old size name, synonym */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _crctx_buf {#pragma __nomember_alignmentN unsigned int crctx_buf$l_xaction; /* Contains ALLO or DEAL */N unsigned int crctx_buf$l_item_num; /* Contains CRCTX$L_ITEM_NUM  */N unsigned int crctx_buf$l_item_cnt; /* Contains CRCTX$L_ITEM_CNT */^ struct _crctx *crctx_buf$ps_crctx; /* Address of CRCTX which made called ALLOC/DEALLOC */\ void *crctx_buf$ps_caller_pc; /* Caller's PC, comes from CRCTX CALLER_PC field. */P unsigned int crctx_buf$l_status; /* Status ret'd by (DE)ALLOC_CNT_RES. */N unsigned int crctx_buf$l_dma_addr; /* DMA-able address */N unsigned int crctx_buf$l_count; /* The number of this entry  */ } CRCTX_BUF;#define CRCTX_BUF$K_LENGTH 32 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _crctx_buf_h {#pragma __nomember_alignmentN __int64 crctx_buf_h$q_free; /* Address of the next free entry */N unsigned int crctx_buf_h$l_size; /* Size of the buffer */ int crctx_buf_h$l_reserved;T int crctx_buf_h$l_count; /* Number of the next entry to be written */ int crctx_buf_h$l_reserved2; } CRCTX_BUF_H; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CRCTXDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc.  **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Source: 30-OCT-2008 13:05:23 $1$DGA8345:[LIB_H.SRC]CSBDEF.SDL;1 *//******************************************************* *************************************************************************//*** MODULE $CSBDEF ***/#ifndef __CSBDEF_LOADED#define __CSBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CSB - Cluster System Block */N/* */N/* There is one CSB for each system in the cluster. */I/* It is used by the connection manager to synchronize */I/* cluster communications and configuration. Access */I/* to the CSB is synchronized with the SCS spinlock. */N/*- */ #include  #define CSB$M_CAP_VCC 0x2 #define CSB$M_CAP_EXT_STATUS 0x8#define CSB$M_CAP_CWCREPRC 0x10#define CSB$M_CAP_THREADS 0x20!#define CSB$M_CAP_CWLOGICALS 0x40&#define CSB$M_CAP_IPC_DEMULT_CONN 0x80#define CSB$M_CAP_RMBXFR 0x100"#define CSB$M_CAP_WBM_SHADOW 0x200#define CSB$M_CAP_WBM_ALL 0x400##define CSB$M_CAP_SCHED_CLASS 0x800"#define CSB$M_CAP_WBM_AMCVP 0x1000!#define CSB$M_CAP_WBM_TYPE 0x2000#define CSB$M_LONG_BREAK 0x1#define CSB$M_MEMBER 0x2#define CSB$M_REMOVED 0x4#define CSB$M_QF_SAME 0x8#define CSB$M_QF_WATCHER 0x10#define CSB$M_QF_NOACCESS 0x20#define CSB$M_CLUSTER 0x100#define CSB$M_QF_ACTIVE 0x200#define CSB$M_SHUTDOWN 0x400#define CSB$M_GONE 0x800$#define CSB$M_RESYNCH_FKB_BSY 0x1000##define CSB$M_RESEND_FKB_BSY 0x2000"#define CSB$M_RCVMSG_FRK_IP 0x4000##define CSB$M_RCVMSG_FKB_BSY 0x8000#define CSB$M_LOCKED 0x10000#define CSB$M_SELECTED 0x20000#define CSB$M_RESERVED1 0x40000%#define CSB$M_SEND_EXT_STATUS 0x80000##define CSB$M_FORCED_STALL 0x100000#define CSB$M_LOCAL 0x1000000##define CSB$M_STATUS_RCVD 0x2000000##define CSB$M_SEND_STATUS 0x4000000$#define CSB$M_QF_RFRSH_RQD 0x8000000$#define CSB$M_QF_RFRSH_IP 0x10000000##define CSB$M_QF_IOSYNCH 0x20000000##define CSB$M_ACT_LSHARE 0x40000000$#define CSB$M_PASS_LSHARE 0x80000000N#define CSB$K_OPEN 1  /* Open (normal) */N#define CSB$K_STATUS 2 /* Sending/waiting for status */N#define CSB$K_RECONNECT 3 /* Attempting to reconnect */N#define CSB$K_NEW 4 /* Brand new block */N#define CSB$K_CONNECT 5 /* Attempting initial connection */N#define CSB$K_ACCEPT 6 /* Accepting initial connection */N#define CSB$K_DISCONNECT 7 /* Disconnect in progress */N#define CSB$K_REACCEPT 8 /* Accepting reconnect request */N#define CSB$K_WAIT 9 /* Time-out in progress */N#define CSB$K_DEAD 10 /* No connection possible */N#define CSB$K_LOCAL 11 /* Local system CSB */N#define CSB$C_LENGTH 520 /* Length of fixed portion of CSB */N#define CSB$K_LENGTH 520 /* Length of fixed portion of CSB */^#define CSB$S_CSBDEF 520 /* Old size name - synonym for fixed portion of CSB */  9#ifdef __cplusplus /* Define structure prototypes */ struct _cdt; struct _pdt; struct _club; struct _sb; struct _tqe; struct _cdrp; #endif /* #ifdef __cplusplus */ typedef struct _csb {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN void *csb$l_sysqfl; /* System Queue Forward Link */#pragma __nomember_alignmentN void *csb$l_sysqbl; /* System Queue Backward Link */N unsigned short int csb$w_size; /* Size of CSB in bytes */N unsigned char csb$b_type; /* Structure Type (DYN$C_CLU) */O unsigned char csb$b_subtype; /* Structure Subtype (DYN$C_CLU_CSB) */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment$ unsigned int csb$bil_cluver; __struct {N unsigned char csb$b_cluver; /* Cluster version number */ } csb$r_fill_1_; } csb$r_fill_0_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#p ragma __nomember_alignment#endif __union {#pragma __nomember_alignment& unsigned int csb$wil_protocol; __struct {N unsigned char csb$b_ecolvl; /* Protocol ECO level */N unsigned char csb$b_vernum; /* Protocol Version number */ } csb$r_fill_3_; } csb$r_fill_2_;N unsigned int csb$l_cache_protocol_ver; /* Cache protocol version */W unsigned short int csb$w_lckdirwt; /* Lock Manager distribute d directory weight */N unsigned short int csb$w_lckrmwt; /* Lock Manager remaster weight */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment# unsigned int csb$wil_votes; __struct {N unsigned short int csb$w_votes; /* Votes held by node */ } csb$r_fill_5_; } csb$r_fill_4_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment$ unsigned int csb$wil_evotes; __struct {O unsigned short int csb$w_evotes; /* Remote node's Expected Votes */ } csb$r_fill_7_; } csb$r_fill_6_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment% unsigned int csb$wil_qdvotes; __struct {Q unsigned short int csb$w_qdvotes; /* Votes assigned to quorum disk */ } csb$r_fill_9_; } csb$r_fill_8_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment$ unsigned int csb$wil_quorum; __struct {N unsigned short int csb$w_quorum; /* Quorum set in node */ } csb$r_fill_11_; } csb$r_fill_10_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment# unsigned int csb$wil_nodes; __struct {S unsigned short int csb$w_nodes; /* Number of nodes in remote cluster */ } csb$r_fill_13_; } csb$r_fill_12_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifN char csb$b_cnct [16]; /* SCS CONNECT /ACCEPT Data Area */N char csb$b_nodemap [32]; /* Bitmap of node connectivity */N char csb$b_hwname [61]; /* Hardware Model Name */#pragma __nomember_alignmentN char csb$b_hwname_pad [3]; /* Explicitly pad to next quadword */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN char csb$t_sw_version [8]; /* VMS Software Version */P unsigned __int64 csb$q_swincarn; /* Remote Software Incarnation Number */N unsigned __int64 csb$q_reftime; /* Creation/Addition/Removal time */R unsigned __int64 csb$q_lnm_seqnum; /* Clusterwide Logicals Sequence Number */Z unsigned __int64 csb$q_lckrm_bxfrseq; /* LCKMGR Remaster Block XFER Sequence Number */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment( unsigned int csb$wil_cnx_sts_r0; __struct {S unsigned short int csb$w_cnx_sts_r0; /* Connection request R0 status */ } csb$r_fill_15_; } csb$r_fill_14_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment( unsigned int csb$wil_cnx_sts_r1; __struct {S unsigned short int csb$w_cnx_sts_r1; /* Connection request R1 status */ } csb$r_fill_17_; } csb$r_fill_16_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN FKB csb$r_resynch_fkb;  /* Message Build Resynch Fork Block */N FKB csb$r_resend_msgs_fkb; /* Resend Messages Fork Block */N FKB csb$r_scs2lckmgr_fkb; /* Received Messages Fork Block */N struct _cdt *csb$l_cdt; /* Address of CDT */#pragma __nomember_alignmentN struct _pdt *csb$l_pdt; /* Address of PDT */N struct _club *csb$l_club; /* Address of CLUB */W struct _sb *csb$l_sb;  /* Address of System Block for remote system */N struct _tqe *csb$l_tqe; /* Address of Timer Queue Entry */N unsigned int csb$l_timeout; /* Time to give up reCONNECTing */] unsigned int csb$l_rmax_vctmo; /* Maximum Remote Virtual Circuit Timeout Interval */S int csb$l_abstim_offset; /* Offset to obtain remote node's ABSTIM */ __union {N unsigned int csb$l_csid; /* Cluster System ID: */ __struct {N unsigned short int csb$w_csid_idx; /* Slot index */N unsigned short int csb$w_csid_seq; /* Sequence number */ } csb$r_fill_19_; } csb$r_fill_18_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment" unsigned int csb$wil_cnid;  __struct {N unsigned short int csb$w_cnid; /* Cluster Node ID */ } csb$r_fill_21_; } csb$r_fill_20_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment __int64 csb$q_partnerq; __struct {W void *csb$l_partnerqfl; /* Block XFER PARTNER BTX Queue Forward Link */X void *csb$l_partnerqbl; /* Block XFER PARTNER BTX Queue Backward Link */ } csb$r_fill_23_; } csb$r_fill_22_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment __int64 csb$q_warmcdrpq; __struct {O struct _cdrp *csb$ l_warmcdrpqfl; /* Warm CDRP Queue Forward Link */P struct _cdrp *csb$l_warmcdrpqbl; /* Warm CDRP Queue Backward Link */ } csb$r_fill_25_; } csb$r_fill_24_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment __union {O unsigned __int64 csb$q_rm_ctxq; /* Remaster Context Block Queue: */ __struct {N unsigned int csb$l_rm_ctxqfl; /* CTXQ Forward Link */N unsigned int csb$l_rm_ctxqbl; /* CTXQ Backward Link */! } csb$r_fill_27_; } csb$r_fill_26_; } csb$r_rm_ctx;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifT void * csb$l_sentqfl; /* SENT Messages List Forward Link (Head) */#pragma __nomember_alignmentU void *csb$l_sentqbl; /* SENT Messages List Backward Link (Tail) */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifV void *csb$l_resendqfl; /* RESEND Messages List Forward Link (Head) */#pragma __nomember_alignmentW void *csb$l_resendqbl; /* RESEND Messages List Backward Link (Tail) */ __union {N unsigned int csb$l_capability; /* Node capabilities */ __struct {N unsigned csb$v_cap_fill_1 : 1; /* obsoleted CAP_RM8SEC */N unsigned csb$v_cap_vcc : 1; /* VCC Enabled */N unsigned csb$v_cap_fill_3 : 1; /* obsoleted CAP_DTS */N unsigned csb$v_cap_ext_status : 1; /* Extended status message */N unsigned csb$v_cap_cwcreprc : 1; /* Clusterwide $CREPRC support */N unsigned csb$v_cap_threads : 1; /* Kernel threads support */Q unsigned csb$v_cap_cwlogicals : 1; /* Clusterwide Logicals support */a unsigned csb$v_cap_ipc_demult_conn : 1; /* IPC supports de-multiplexed connections */Q unsigned csb$v_cap_rmbxfr : 1; /* Can send/receive block remasters */l unsigned csb$v_cap_wbm_shadow : 1; /* Supports Write BitMap for shadow member copy operations */U unsigned csb$v_cap_wbm_all : 1; /* Supports Write BitMap for all disks */q unsigned csb$v_cap_sched_class : 1; /* Supports class scheduling via class scheduler database file */O unsigned csb$v_cap_wbm_amcvp : 1; /* Supports AMCVP enhancements */X unsigned csb$v_cap_wbm_type : 1; /* Supports WBM bitmap TYPE enhancements */( unsigned csb$v_fill_46_ : 2; } csb$r_fill_29_;  } csb$r_fill_28_; __union {N unsigned int csb$l_status; /* Status of node in cluster */ __struct {N unsigned csb$v_long_break : 1; /* Long break in connection */N unsigned csb$v_member : 1; /* Node is member of local cluster */N unsigned csb$v_removed : 1; /* Node removed from cluster */T unsigned csb$v_qf_same : 1; /* Remote quorum disk matches local disk */W unsigned csb$v_qf_watcher : 1; /* Remote node is watching a quorum file */U unsigned csb$v_qf_noaccess : 1; /* Node will never access quorum disk */N unsigned csb$v_sts_fill_1 : 2; /* Pad to next byte boundary */N unsigned csb$v_cluster : 1; /* Remote node is cluster member */V unsigned csb$v_qf_active : 1; /* Remote node's quorum file is readable */V unsigned csb$v_shutdown : 1; /* Remote node ready for cluster shutdown */N unsigned csb$v_gone : 1; /* Known to have shutdown */U unsigned csb$v_resynch_fkb_bsy : 1; /* MSGBLD Resynch Fork Block busy */Q unsigned csb$v_resend_fkb_bsy : 1; /* Resend_Msgs Fork Block busy */U unsigned csb$v_rcvmsg_frk_ip : 1; /* SCS2LCKMGR fork thread is active */v unsigned csb$v_rcvmsg_fkb_bsy : 1; /* SCS2LCKMGR fork block is queued, thread may or may not be active */N unsigned csb$v_locked : 1; /* Node locked by coordinator */N unsigned csb$v_selected : 1; /* Node selected by coordinator */O unsigned csb$v_reserved1 : 1; /* Bit was used for a VAX release */S unsigned csb$v_send_ext_status : 1; /* Need to send extended status */d unsigned csb$v_forced_stall : 1; /* Waiting for remote acks to avoid remote overload */N unsigned csb$v_sts_fill_2 : 3; /* Pad to next byte boundary */N unsigned csb$v_local : 1; /* This CSB is the local system  */U unsigned csb$v_status_rcvd : 1; /* Status received from remote system */W unsigned csb$v_send_status : 1; /* Need to send status to remote system */N unsigned csb$v_qf_rfrsh_rqd : 1; /* Need Quorum File refresh */R unsigned csb$v_qf_rfrsh_ip : 1; /* Quorum File refresh in progress */N unsigned csb$v_qf_iosynch : 1; /* Quorum File I/O synch done */N unsigned csb$v_act_lshare : 1; /* Active side to load sharing */O unsigned csb$v_pass_lshare : 1; /* Passive side to load sharing */ } csb$r_fill_31_; } csb$r_fill_30_;N unsigned int csb$l_state; /* State of connection */Q struct _cdrp *csb$l_currcdrp; /* Address of CDRP in critical section */N unsigned int csb$l_refcnt; /* Reference count */N unsigned int csb$l_unackedmsgs; /* Number of unacked messages */N unsigned int csb$l_remacklim;  /* Remote side's ACK Limit */N unsigned int csb$l_warmcdrps; /* Number of CDRPs on free queue */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment' unsigned int csb$wil_sendseqnm; __struct {R unsigned short int csb$w_sendseqnm; /* Next sequence number to send */  } csb$r_fill_33_; } csb$r_fill_32_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment' unsigned int csb$wil_rcvdseqnm; __struct {S unsigned short int csb$w_rcvdseqnm; /* Last Sequence Number received */ } csb$r_fill_35_; } csb$r_fill_34_;c #if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment' unsigned int csb$wil_ackrseqnm; __struct {Y unsigned short int csb$w_ackrseqnm; /* Last ACK'd received Sequence Number */ } csb$r_fill_37_; } csb$r_fill_36_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cpl usplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment& unsigned int csb$wil_lastsent; __struct {Y unsigned short int csb$w_lastsent; /* Sequence Number of message last sent */ } csb$r_fill_39_; } csb$r_fill_38_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma  __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment' unsigned int csb$wil_pass_cntr; __struct {X unsigned short int csb$w_pass_cntr; /* Total passive loadshare operations */ } csb$r_fill_41_; } csb$r_fill_40_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment& unsigned int csb$wil_act_cntr; __struct {V unsigned short int csb$w_act_cntr; /* Total active loadshare operations */ } csb$r_fill_43_; } csb$r_fill_42_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_a lignment& unsigned int csb$wil_err_cntr; __struct {O unsigned short int csb$w_err_cntr; /* Total errors on connection */ } csb$r_fill_45_; } csb$r_fill_44_;Q unsigned int csb$l_scs2lckmgr_maxidx; /* Max index for SCS2LCKMGR_MSGARRAY */[ unsigned int csb$l_maxmsgsiz; /* Max message size allowed to send to this node */! unsigned int csb$l_spare_lw1;% unsigned __int64 csb$q_spare_qw2;c#if !defined(__NOBASEALIGN_SUPPORT) & & !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment unsigned int csb$l_scs2lckmgr_msgcnt; /* Number of received msgbufs waiting for LCKMGR spinlock (at element 0 of array) */{ int csb$l_scs2lckmgr_msgarray; /* Array of msgbuf addresses waiting for LCKMGR spinlock (starting at element 1) */Y __int64 csb$q_scs2lckmgr_pad; /* Pad uni on to match quadword alignment for C */$ } csb$r_lckmgr_fork_overlay;Z/* N.B. -- Do not add any symbols beyond the lckmgr_fork_overlay -- it must be the last */U/* entry in the CSB as the SCS2LCKMGR_MSGARRAY is dynamically sized based on the */I/* CLUSTER_CREDITS SYSGEN parameter. */ } CSB; #if !defined(__VAXC)3#define csb$bil_cluver csb$r_fill_0_.csb$bil_cluver=#define csb$b_cluver csb$r_fill_0_.csb$r_fill_1_.csb$b_cluver7#define csb$wi l_protocol csb$r_fill_2_.csb$wil_protocol=#define csb$b_ecolvl csb$r_fill_2_.csb$r_fill_3_.csb$b_ecolvl=#define csb$b_vernum csb$r_fill_2_.csb$r_fill_3_.csb$b_vernum1#define csb$wil_votes csb$r_fill_4_.csb$wil_votes;#define csb$w_votes csb$r_fill_4_.csb$r_fill_5_.csb$w_votes3#define csb$wil_evotes csb$r_fill_6_.csb$wil_evotes=#define csb$w_evotes csb$r_fill_6_.csb$r_fill_7_.csb$w_evotes5#define csb$wil_qdvotes csb$r_fill_8_.csb$wil_qdvotes?#define csb$w_qdvotes csb$r_fill_8_.csb$r_fill _9_.csb$w_qdvotes4#define csb$wil_quorum csb$r_fill_10_.csb$wil_quorum?#define csb$w_quorum csb$r_fill_10_.csb$r_fill_11_.csb$w_quorum2#define csb$wil_nodes csb$r_fill_12_.csb$wil_nodes=#define csb$w_nodes csb$r_fill_12_.csb$r_fill_13_.csb$w_nodes<#define csb$wil_cnx_sts_r0 csb$r_fill_14_.csb$wil_cnx_sts_r0G#define csb$w_cnx_sts_r0 csb$r_fill_14_.csb$r_fill_15_.csb$w_cnx_sts_r0<#define csb$wil_cnx_sts_r1 csb$r_fill_16_.csb$wil_cnx_sts_r1G#define csb$w_cnx_sts_r1 csb$r_fill_16_.csb$r_fill_1 7_.csb$w_cnx_sts_r1,#define csb$l_csid csb$r_fill_18_.csb$l_csidC#define csb$w_csid_idx csb$r_fill_18_.csb$r_fill_19_.csb$w_csid_idxC#define csb$w_csid_seq csb$r_fill_18_.csb$r_fill_19_.csb$w_csid_seq0#define csb$wil_cnid csb$r_fill_20_.csb$wil_cnid;#define csb$w_cnid csb$r_fill_20_.csb$r_fill_21_.csb$w_cnidG#define csb$l_partnerqfl csb$r_fill_22_.csb$r_fill_23_.csb$l_partnerqflG#define csb$l_partnerqbl csb$r_fill_22_.csb$r_fill_23_.csb$l_partnerqblI#define csb$l_warmcdrpqfl csb$r_fill_24_.csb$r_fill_25_.csb$l_warmcdrpqflI#define csb$l_warmcdrpqbl csb$r_fill_24_.csb$r_fill_25_.csb$l_warmcdrpqbl?#define csb$q_rm_ctxq csb$r_rm_ctx.csb$r_fill_26_.csb$q_rm_ctxqR#define csb$l_rm_ctxqfl csb$r_rm_ctx.csb$r_fill_26_.csb$r_fill_27_.csb$l_rm_ctxqflR#define csb$l_rm_ctxqbl csb$r_rm_ctx.csb$r_fill_26_.csb$r_fill_27_.csb$l_rm_ctxqbl8#define csb$l_capability csb$r_fill_28_.csb$l_capabilityA#define csb$v_cap_vcc csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_vccO#define csb$v_cap_ext_status csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_ext_statusK#define csb$v_cap_cwcreprc csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_cwcreprcI#define csb$v_cap_threads csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_threadsO#define csb$v_cap_cwlogicals csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_cwlogicalsY#define csb$v_cap_ipc_demult_conn csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_ipc_demult_connG#define csb$v_cap_rmbxfr csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_rmbxfrO#define csb$v_cap_wbm_shadow csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_wbm_shadowI#define csb$v_cap_wbm_all csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_wbm_allQ#define csb$v_cap_sched_class csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_sched_classM#define csb$v_cap_wbm_amcvp csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_wbm_amcvpK#define csb$v_cap_wbm_type csb$r_fill_28_.csb$r_fill_29_.csb$v_cap_wbm_type0#define csb$l_status csb$r_fill_30_.csb$l_statusG#define csb$v_long_break csb$r_fill_30_.csb$r_fill_31_.csb$v_long_break?#define csb$v_member csb$r_fill_30_.csb$r_fill_31_.csb$v_memberA#define csb$v_removed csb$r_fill_30_.csb$r_fill_31_.csb$v_removedA#define csb$v_qf_same csb$r_fill_30_.csb$r_fill_31_.csb$v_qf_sameG#define csb$v_qf_watcher csb$r_fill_30_.csb$r_fill_31_.csb$v_qf_watcherI#define csb$v_qf_noaccess csb$r_fill_30_.csb$r_fill_31_.csb$v_qf_noaccessA#define csb$v_cluster csb$r_fill_30_.csb$r_fill_31_.csb$v_clusterE#define csb$v_qf_active csb$r_fill_30_.csb$r_fill_31_.csb$v_qf_activeC#define csb$v_shutdown csb$r_fill_30_.csb$r_fill_31_.csb$v_shutdown;#define csb$v_gone csb$r_fill_30_.csb$r_fill_31_.csb$v_goneQ#define csb$v_resynch_fkb_bsy csb$r_fill_30_.csb$r_fill_31_.csb$v_resynch_fkb_bsyO#define csb$v_resend_fkb_bsy csb$r_fill_30_.csb$r_fill_31_.csb$v_resend_fkb_bsyM#define csb$v_rcvmsg_frk_ip csb$r_fill_30_.csb$r_fill_31_.csb$v_rcvmsg_frk_ipO#define csb$v_rcvmsg_fkb_bsy csb$r_fill_30_.csb$r_fill_31_.csb$v_rcvmsg_fkb_bsy?#define csb$v_locked csb$r_fill_30_.csb$r_fill_31_.csb$v_lockedC#define csb$v_selected csb$r_fill_30_.csb$r_fill_31_.csb$v_selectedE#define csb$v_reserved1 csb$r_fill_30_.csb$r_fill_31_.csb$v_reserved1Q#define csb$v_send_ext_status csb$r_fill_30_.csb$r_fill_31_.csb$v_send_ext_statusK#define csb$v_forced_stall csb$r_fill_30_.csb$r_fill_31_.csb$v_forced_stall=#define csb$v_local csb$r_fill_30_.csb$r_fill_31_.csb$v_localI#define csb$v_status_rcvd csb$r_fill_30_.csb$r_fill_31_.csb$v_status_rcvdI#define csb$v_send_status csb$r_fill_30_.csb$r_fill_31_.csb$v_send_statusK#define csb$v_qf_rfrsh_rqd csb$r_fill_30_.csb$r_fill_31_.csb$v_qf_rfrsh_rqdI#define csb$v_qf_rfrsh_ip csb$r_fill_30_.csb$r_fill_31_.csb$v_qf_rfrsh_ipG#define csb$v_qf_iosynch csb$r_fill_30_.csb$r_fill_31_.csb$v_qf_iosynchG#define csb$v_act_lshare csb$r_fill_30_.csb$r_fill_31_.csb$v_act_lshareI#define csb$v_pass_lshare csb$r_fill_30_.csb$r_fill_31_.csb$v_pass_lshare:#define csb$wil_sendseqnm csb$r_fill_32_.csb$wil_sendseqnmE#define csb$w_sendseqnm csb$r_fill_32_.csb$r_fill_33_.csb$w_sendseqnm:#define csb$wil_rcvdseqnm csb$r_fill_34_.csb$wil_rcvdseqnmE#define csb$w_rcvdseqnm csb$r_fill_34_.csb$r_fill_35_.csb$w_rcvdseqnm:#define csb$wil_ackrseqnm csb$r_fill_36_.csb$wil_ackrseqnmE#define csb$w_ackrseqnm csb$r_fill_36_.csb$r_fill_37_.csb$w_ackrseqnm8#define csb$wil_lastsent csb$r_fill_38_.csb$wil_lastsentC#define csb$w_lastsent csb$r_fill_38_.csb$r_fill_39_.csb$w_lastsent:#define csb$wil_pass_cntr csb$r_fill_40_.csb$wil_pass_cntrE#define csb$w_pass_cntr csb$r_fill_40_.csb$r_fill_41_.csb$w_pass_c ntr8#define csb$wil_act_cntr csb$r_fill_42_.csb$wil_act_cntrC#define csb$w_act_cntr csb$r_fill_42_.csb$r_fill_43_.csb$w_act_cntr8#define csb$wil_err_cntr csb$r_fill_44_.csb$wil_err_cntrC#define csb$w_err_cntr csb$r_fill_44_.csb$r_fill_45_.csb$w_err_cntrQ#define csb$l_scs2lckmgr_msgcnt csb$r_lckmgr_fork_overlay.csb$l_scs2lckmgr_msgcntU#define csb$l_scs2lckmgr_msgarray csb$r_lckmgr_fork_overlay.csb$l_scs2lckmgr_msgarray"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CSBDEF_LOADED */ ww4[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This softwa re is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/************************************************************************* !**//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */I/* Source: 12-APR-2006 13:17:31 $1$DGA8345:[LIB_H.SRC]CSCHEDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CSCHEDDEF ***/#ifndef __CSCHEDDEF_LOADED#define __CSCHEDDEF_LOADED 1 G#pra "gma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional#_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* The following structure is the format of the records in the class */N/* $ scheduler database file. The class record is the largest record. */N/* The qualifying records (username, account name, and UIC) are subsets */N/* of the class record. */N/*-- */##define CSCHED$K_CLASS_NUMBER_POS 2 #define CSCHED$K_CLASS_NUMSIZE 2 #define CSCHED$K_NODE_NAME_POS 4N#define CSCHED$K_NODE_RECORD 20 /* End of Node record */!#d %efine CSCHED$K_USER_NAME_POS 20N#define CSCHED$K_USERNAME_RECORD 52 /* End of User name record */$#define CSCHED$K_ACCOUNT_NAME_POS 52N#define CSCHED$K_ACCOUNT_RECORD 84 /* End of Account record */#define CSCHED$K_UIC_POS 84#define CSCHED$K_UIC_GRP_POS 86#define CSCHED$K_UIC_SIZE 4N#define CSCHED$K_UIC_RECORD 88 /* End of UIC record */#define CSCHED$M_WINDFALL 0x1#define CSCHED$M_CLUSTER 0x2#define CSCHED$M_DELPND 0x4#define &CSCHED$M_MONDAY 0x1#define CSCHED$M_TUESDAY 0x2#define CSCHED$M_WEDNESDAY 0x4#define CSCHED$M_THURSDAY 0x8#define CSCHED$M_FRIDAY 0x10#define CSCHED$M_SATURDAY 0x20#define CSCHED$M_SUNDAY 0x40##define CSCHED$K_CLASS_NAME_POS 144N#define CSCHED$K_CLASS_RECORD 160 /* End of class record */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_align 'ment#endiftypedef struct _csched {#pragma __nomember_alignment] unsigned short int csched$w_record_type; /* Record type (class, user, account, or UIC) */[ unsigned short int csched$w_class_number; /* Class number (values between 0 - 8191) */N char csched$t_node_name [16]; /* Node name */N char csched$t_user_name [32]; /* User name */T char csched$t_account [32]; /* Account name (same as in the UAF file) */ ( __union {N unsigned int csched$l_uic; /* User's UIC value */ __struct {N unsigned short int csched$w_mem; /* Member number in UIC */N unsigned short int csched$w_grp; /* Group number in UIC */ } csched$r_fill_1_; } csched$r_fill_0_;] unsigned char csched$b_primeday_cpulimit [24]; /* Cpu limits per hour for primary days */_ unsigned char csched$b_seconday_cpulimit [24]; /* Cpu limits per ) hour for secondary days */ __union {N unsigned int csched$l_flags; /* Flags field */ __struct {T unsigned csched$v_windfall : 1; /* Enable windfall if this bit is set */N unsigned csched$v_cluster : 1; /* Class is valid cluster-wide */N unsigned csched$v_delpnd : 1; /* Class is being deleted */* unsigned csched$v_fill_6_ : 5; } csched$r_fill_3_; } csched$r_fill_2_; *__union {V unsigned char csched$b_days; /* Days of the week that the class is valid */ __struct {V unsigned csched$v_monday : 1; /* If bit is clear, day is a primary day. */Q unsigned csched$v_tuesday : 1; /* Otherwise, it's a secondary day. */, unsigned csched$v_wednesday : 1;+ unsigned csched$v_thursday : 1;) unsigned csched$v_friday : 1;+ unsigned csched$v_saturday : 1;) unsigned csched$v_ +sunday : 1;* unsigned csched$v_fill_7_ : 1; } csched$r_fill_5_; } csched$r_fill_4_;N unsigned char csched$$$_fill_2 [3]; /* Get alignment back */N char csched$t_class_name [16]; /* Name of scheduling class */ } CSCHED; #if !defined(__VAXC)2#define csched$l_uic csched$r_fill_0_.csched$l_uicC#define csched$w_mem csched$r_fill_0_.csched$r_fill_1_.csched$w_memC#define csched$w_grp csched$r_fill_0_.csched$r_fill_1_.csche,d$w_grp6#define csched$l_flags csched$r_fill_2_.csched$l_flagsM#define csched$v_windfall csched$r_fill_2_.csched$r_fill_3_.csched$v_windfallK#define csched$v_cluster csched$r_fill_2_.csched$r_fill_3_.csched$v_clusterI#define csched$v_delpnd csched$r_fill_2_.csched$r_fill_3_.csched$v_delpnd4#define csched$b_days csched$r_fill_4_.csched$b_daysI#define csched$v_monday csched$r_fill_4_.csched$r_fill_5_.csched$v_mondayK#define csched$v_tuesday csched$r_fill_4_.csched$r_fill_5_.csched$v_tuesday -O#define csched$v_wednesday csched$r_fill_4_.csched$r_fill_5_.csched$v_wednesdayM#define csched$v_thursday csched$r_fill_4_.csched$r_fill_5_.csched$v_thursdayI#define csched$v_friday csched$r_fill_4_.csched$r_fill_5_.csched$v_fridayM#define csched$v_saturday csched$r_fill_4_.csched$r_fill_5_.csched$v_saturdayI#define csched$v_sunday csched$r_fill_4_.csched$r_fill_5_.csched$v_sunday"#endif /* #if !defined(__VAXC) */  #define CSCHED$S_CLASS_NAME 16N#define CSCHED$K_LENGTH 160 . /* Length of structure */N/* Values for each Record type are: */#define CSCHED$K_CLASS 1#define CSCHED$K_USERNAME 2#define CSCHED$K_UIC 3#define CSCHED$K_ACCOUNT 4#define CSCHED$K_NODE 5O/* Define a maximum number of classes. The class scheduler database file is */O/* designed to support an unlimited number of classes. However, we place a */P/* limit of the number of classes so that we can easily determine the size of */N//* the in-memory class scheduler arrays. */N/* */&#define CSCHED$K_MAX_SCHED_CLASSES 256N/* */S/* The following 2 constants define the actual size of the user name and account */N/* name fields. The size of these fields is tied to the size of these same */O/* fields in the sysuaf.dat file. The Authorize image limit 0s these names to */N/* 12 and 8 bytes respectively despite the fact that uafdef.sdl reserves 32 */O/* bytes for each of these fields in the sysuaf.dat file. If Authorize ever */R/* increases the limit on these fields, then these constants should be adjusted */N/* to match the new limits. */N/* */&#define CSCHED$K_USERNAME_REAL_SIZE 12$#define CSCHED$K_ACCOUNT_REAL_SIZE 8N1/* */N/* This is the class scheduler's work area. The memory for this work */N/* area is allocated/deallocated by the SMIserver and will be used by */N/* the SMI object routines. This work area holds the RMS data structures */N/* used when reading/writing to the class scheduler database file. */N/* */#define SCHEDWA$K_LENGTH 1 2232 struct schedwa {N unsigned char schedwa$b_fab [80]; /* FAB for database file */N unsigned char schedwa$b_rab [144]; /* RAB for database file */T unsigned char schedwa$b_class_key0 [100]; /* 6 XAB's to represent 6 different */R unsigned char schedwa$b_class_key1 [100]; /* index keys into database file. */- unsigned char schedwa$b_class_key2 [100];- unsigned char schedwa$b_class_key3 [100];- unsigned char schedwa$b_class_key4 [100];- 3unsigned char schedwa$b_class_key5 [100];N unsigned char schedwa$b_xabpro [88]; /* Protection XAB */N unsigned char schedwa$b_input_buf [160]; /* Input buffer */N unsigned char schedwa$b_output_buf [160]; /* Output buffer */ } ;Q/* Bit definitions for the flags field passed between SYSMAN and the SMIserver */T/* for the ADD, DELETE, and SHOW commands. Since both these images include this */N/* file, it is an appropriate place to inc4lude them. */N#define CSCHED$K_ALL 0 /* flags for the SHOW command */#define CSCHED$K_FULL 1\#define CSCHED$K_WINDFALL 0 /* flags for the ADD command and the cluster flag */R#define CSCHED$K_CLUSTER 1 /* is also valid for the DELETE command */N/* Values below represent the item codes for the item list which */T/* contains the user data for a scheduling class. These item codes are used for */T/* the ADD and MOD 5IFY functions. The item list is passed from SYSMAN to the SMI */N/* class scheduler object routine. */#define CSCHED$K_ADD_USER 1#define CSCHED$K_ADD_ACCOUNT 2#define CSCHED$K_ADD_UIC 3#define CSCHED$K_REMOVE_USER 4!#define CSCHED$K_REMOVE_ACCOUNT 5#define CSCHED$K_REMOVE_UIC 6&#define CSCHED$K_NUMBER_OF_ITEMCODES 7 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#p6ragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CSCHEDDEF_LOADED */ ww[[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterp7rise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is 8not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************************** 9***************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */G/* Source: 22-APR-1993 10:46:47 $1$DGA8345:[LIB_H.SRC]CSDTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CSDTDEF ***/#ifndef __CSDTDEF_LOADED#define __CSDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save:#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __st;ruct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CSDT - CLUSTER SERVER DISPATCH TABLE */N/* */N/*- < */N/* */I/* CSDTE - CLUSTER SERVER DISPATCH TABLE ENTRY */N/* */ N/* */N#define CSDTE$C_LENGTH 64 /* LENGTH */N#define CSDTE$K_LENGTH 64 /* LENGTH = */#define CSDTE$S_CSDTEDEF 64 typedef struct _csdte {N unsigned __int64 csdte$q_req_iq; /* INTERLOCKED REQUEST QUEUE */N unsigned __int64 csdte$q_waitq; /* WAIT QUEUE */N unsigned int csdte$l_ipid; /* SERVER IPID */N unsigned int csdte$l_queued; /* NUMBER OF WAITS */N unsigned int csdte$l_requests; /* TOTAL REQUESTS MADE */N unsigned int c>sdte$l_waitcnt; /* ENTRIES IN WAIT QUEUE */N unsigned int csdte$l_maxactive; /* MAXIMUM ACTIVE REQUESTS ALLOWED */N unsigned int csdte$l_active; /* NUMBER ACTIVE REQUESTS */N char csdte$t_fill_4 [24]; /* Make table size a power of 2 */ } CSDTE;N#define CSDT$C_LENGTH 16 /* LENGTH OF FIXED PART */N#define CSDT$K_LENGTH 16 /* LENGTH OF FIXED PART */N#define CSDT$T_CSDTEVEC 16 ? /* START OF VARIABLE PART */#define CSDT$S_CSDTDEF 16 typedef struct _csdt {N int csdt$l_fill_1; /* RESERVED */N int csdt$l_fill_2; /* RESERVED */N unsigned short int csdt$w_size; /* SIZE OF IN BYTES */N unsigned char csdt$b_type; /* STRUCTURE TYPE */N unsigned char csdt$b_subtype; /* STRUCTURE SUBTYPE */N@ char csdt$t_align [4]; /* QUADWORD ALIGN */ } CSDT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CSDTDEF_LOADED */ ww[UM/*********************************************************A******************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** B **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** C **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Source: 09-JUN-2017 14:54:38 $1$DGA8345:[LIB_H.SRC]CTDDEF.SDL;1 *//*********************************************************************************************************** D*********************//*** MODULE $CTDDEF ***/#ifndef __CTDDEF_LOADED#define __CTDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit Epointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ F */N/* */N/* CPU transition block definition. This block is allocated */N/* and initialized when a CPU undergoes a state transition and the final */N/* completion code is to be returned to the issuer. */N/*- */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ Gtqe; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ctd {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _ctd *ctd$pq_qlink; /* H Forward link to next CTD */#else unsigned __int64 ctd$pq_qlink;#endifN unsigned short int ctd$w_size; /* Structure size */N unsigned char ctd$b_type; /* Structure type */N unsigned char ctd$b_rmod; /* Duplicate of ACB RMOD */N unsigned int ctd$l_pid; /* PID of owner process */N unsigned int ctd$l_acb64x; /* Offset to ACB extension */N unsigned int cItd$l_flags; /* CTD behavioral flags */N unsigned int ctd$l_acb_flags; /* ACB64X behavioral flags */N unsigned int ctd$l_thread_pid; /* PID of initiating thread */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void (*ctd$l_kast)(); /* Internal Kernel mode xfer */N unsigned int c Jtd$l_imgcnt; /* PHD IMGCNT value at issue */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void (*ctd$pq_ast)(); /* 64-bit AST address */#else unsigned __int64 ctd$pq_ast;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadwor Kd#else#pragma __nomember_alignment#endifN unsigned __int64 ctd$q_astprm; /* 64-bit ASTPRM value */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ctd$pq_iosb; /* Quadword IOSB pointer */#else unsigned __int64 ctd$pq_iosb;#endifN __int64 ctd$q_source_node; /* Node ID of source system L */N __int64 ctd$q_target_node; /* Node ID of target system */#pragma __nomember_alignmentN int ctd$l_primary_tran_code; /* Transition type in progress */N int ctd$l_current_tran_code; /* Transition type in progress */N unsigned int ctd$l_transition_mask; /* Bitmask of requested transitions */N int ctd$l_cpu_id; /* ID of CPU under transition */N unsigned int ctd$l_status; /* Final completion code M */N unsigned int ctd$l_efn; /* Event flag to set on finish */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _tqe *ctd$l_timeout_tqe; /* Pointer to TQE for timeout */ char ctd$b_fill_0_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomemb Ner_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 ctd$q_cpu_handle; /* Config tree pointer */N unsigned __int64 ctd$q_target_handle; /* Config tree pointer */N unsigned __int64 ctd$q_start_time; /* Smithsonian initiation time */N unsigned __int64 ctd$q_interim_time; /* Smithsonian completion time */ } CTD;N#define CTD$K_LENGTH 144 /* Total fixed structure size */ #ifdef __INITIAL_POOINTER_SIZEM# pragma __required_pointer_size __save /* Save current pointer size */G# pragma __required_pointer_size 64 /* Pointers are 64-bits */H typedef struct _ctd * CTD_PQ; /* 64-bit pointer to an CTD */V typedef struct _ctd ** CTD_PPQ; /* 64-bit pointer to a pointer to an CTD */S# pragma __required_pointer_size __restore /* Return to previous pointer size */#elseU typedef unsigned __int64 CTD_PQ; /* Same size as a 64-bit pointer to an CTDP */b typedef unsigned __int64 CTD_PPQ; /* Same size as a 64-bit pointer to a pointer to an CTD */#endif $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CTDDEF_LOADED */ ww[UM/***************************************Q************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP R **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** S **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */M/* Source: 25-FEB-2008 18:27:21 $1$DGA8345:[LIB_H.SRC]CTLP1FLAGSDEF.SDL;1 *//********************************************************************************* T***********************************************//*** MODULE $CTLP1FLAGSDEF ***/#ifndef __CTLP1FLAGSDEF_LOADED #define __CTLP1FLAGSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __Ushort /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* +V */N/* CTL P1 flags */N/* */N/* These are flags in the CTL p1 region to define miscellaneous things. */P/* There are also some definitions relating to the instruction emulator here. */N/* - */N/* W */N/* These reside in the cell CTL$GQ_MISC_P1_FLAGS, defined in SHELL.MAR. */N/* The byte alignment fillers are present for historical reasons. When */N/* the adjacent fields were added, $GETJPI was not capable of fetching */N/* bitfields in CTL structures, so these fields were byte aligned and */N/* fetched as byte items. Of course, this practice couldn't last and we */N/* ran out of available bits in the quadword. $GETJPI Xhas been fixed and */N/* the space in the fillers is available for use. The fillers remain so */N/* that existing bits do not move. */N/* */"#define CTLP1FLAGS$M_GSD_CLEAN 0x1"#define CTLP1FLAGS$M_IPC_CLEAN 0x2 #define CTLP1FLAGS$M_PSX_PML 0x4"#define CTLP1FLAGS$M_MKTHREADS 0x8!#define CTLP1FLAGS$M_UPCALLS 0x10!#define CTLP1FLAGS$M_PTHREAD 0x20'#define CTLP1FLAGS$M_MEDDL YE_ENABLE 0x40 #define CTLP1FLAGS$M_MEDDLE 0x80+#define CTLP1FLAGS$M_PARSE_STYLE_PERM 0x700-#define CTLP1FLAGS$M_SRCH_SYMLINK_PERM 0x1800.#define CTLP1FLAGS$M_PARSE_STYLE_IMAGE 0x70000/#define CTLP1FLAGS$M_SRCH_SYMLINK_TEMP 0x180000/#define CTLP1FLAGS$M_CASE_LOOKUP_PERM 0x70000002#define CTLP1FLAGS$M_CASE_LOOKUP_IMAGE 0x700000000(#define CTLP1FLAGS$M_UNITS 0x10000000000*#define CTLP1FLAGS$M_TOKEN 0x1000000000000N#define CTLP1FLAGS$S_CTLP1DEF 8 /* Old size name - synonym Z*/ typedef struct _ctlp1 {N unsigned ctlp1flags$v_gsd_clean : 1; /* GSD clean-up is in progress */W unsigned ctlp1flags$v_ipc_clean : 1; /* $IPC association clean-up is in progress */T unsigned ctlp1flags$v_psx_pml : 1; /* POSIX user stack locked in working set */N unsigned ctlp1flags$v_mkthreads : 1; /* Multiple kernel threads enabled */N unsigned ctlp1flags$v_upcalls : 1; /* Upcalls enabled */R unsigned ctlp1flags$v_pthread : 1; /* PTHREAD$RTL h[as been image activated */k unsigned ctlp1flags$v_meddle_enable : 1; /* Record fact of process logical name & symbol alterations */` unsigned ctlp1flags$v_meddle : 1; /* Process logical names or symbols have been altered */S unsigned ctlp1flags$v_parse_style_perm : 3; /* Process-permanent parse_style */\ unsigned ctlp1flags$v_srch_symlink_perm : 2; /* Process-permanent symlink search mode */O unsigned ctlp1flags$v_filler_2 : 3; /* Byte align for historical reasons */P unsi\gned ctlp1flags$v_parse_style_image : 3; /* Life-of-image parse_style */X unsigned ctlp1flags$v_srch_symlink_temp : 2; /* Life-of-image symlink search mode */O unsigned ctlp1flags$v_filler_3 : 3; /* Byte align for historical reasons */S unsigned ctlp1flags$v_case_lookup_perm : 3; /* Process-permanent case_lookup */O unsigned ctlp1flags$v_filler_4 : 5; /* Byte align for historical reasons */P unsigned ctlp1flags$v_case_lookup_image : 3; /* Life-of-image case_lookup */O unsign]ed ctlp1flags$v_filler_5 : 5; /* Byte align for historical reasons */N unsigned ctlp1flags$v_units : 1; /* Use bytes or blocks */O unsigned ctlp1flags$v_filler_6 : 7; /* Byte align for historical reasons */N unsigned ctlp1flags$v_token : 1; /* Use small or large tokens */N unsigned ctlp1flags$v_filler_7 : 15; /* Available space */ } CTLP1;N/* */N/* The following a ^re the flags that reside in CTL$GQ_EMULATOR_FLAGS */N/* */#define CTLEMFLAGS$M_REINIT 0x1&#define CTLEMFLAGS$M_GET_SIG_COUNT 0x2+#define CTLEMFLAGS$M_NO_NEW_IMAGE_RESET 0x4*#define CTLEMFLAGS$M_SIGNAL_INNER_MODE 0x8&#define CTLEMFLAGS$M_NO_MASK_INIT 0x10,#define CTLEMFLAGS$M_NO_SIGNAL_MAX_INIT 0x20)#define CTLEMFLAGS$M_NO_PC_RING_INIT 0x40'#define CTLEMFLAGS$M_NO_COUNT_INIT 0x80 c#if !defined(__NOBASEALI _GN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ctlemflags {#pragma __nomember_alignmentX unsigned ctlemflags$v_reinit : 1; /* A new image started: reinitialize P1 cells */V unsigned ctlemflags$v_get_sig_count : 1; /* Get the sig count from EMULATE_DATA */N unsigned ctlemflags$v_no_new_image_reset : 1; /* Inhibit initialization */h unsigned ctlemflag `s$v_signal_inner_mode : 1; /* Signal SS$_EMULATED even for inner mode emulation */N/* ...(you need a condition handler else SSERVEXC bugcheck) */f unsigned ctlemflags$v_no_mask_init : 1; /* Run init in emulator, but don't init these fields... */1 unsigned ctlemflags$v_no_signal_max_init : 1;. unsigned ctlemflags$v_no_pc_ring_init : 1;N unsigned ctlemflags$v_no_count_init : 1; /* ...End of "init but" bits */" char ctlemflags$b_fill_0_ [7]; } CTLEMFLAGS;N/* a */N/* The following are the flags that reside in the CTL$GQ_EXCEPTION_FLAGS */N/* */'#define CTLEXCFLAGS$M_SIGNAL_ACTIVE 0x1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ctlexcflags { b#pragma __nomember_alignmentN unsigned ctlexcflags$v_signal_active : 1; /* Signal processing is in */N/* progress */* unsigned ctlexcflags$v_fill_1__1 : 32;* unsigned ctlexcflags$v_fill_1__2 : 31; } CTLEXCFLAGS;N/* */N/* These constants relate to CTL$GQ_EMULATE_PC_RING */N/* c */!#define CTL$C_EMULATE_RING_SIZE 8O#define CTL$M_EMULATE_RING_SIZE 7 /* Mask for valid bits to index ring */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard ##endif /* __CTLP1FLAGSDEF_LOADED */ ww0[UdM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Heewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. f **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */G/* Source: 29-APR-1993 16:32:31 $1$DGA8345:[LIB_H.SRC]CTSIDEF.SDL;1 *//******************************************* g*************************************************************************************//*** MODULE $CTSIDEF ***/#ifndef __CTSIDEF_LOADED#define __CTSIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __requhired_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#end iif#endif N#define CTSI$K_REVISION 1 /* CTSI Revision 1 only. */#define CTSI$C_REVISION 1N#define CTMD$K_SIZE 8 /* Size */N#define CTMD$C_SIZE 8 /* Size */ Ntypedef struct _ctmd { /* Module descriptor in the CTSIA. */N unsigned short int ctmd$w_pgcount; /* Module length in pages */N short int ctmd$w_spare_1; /* Padding j */N void *ctmd$l_baseaddr; /* Base physical addr. */ } CTMD;N#define CTCB$K_SIZE 28 /* Length of channel block */N#define CTCB$C_SIZE 28 /* Length of channel block */ Ntypedef struct _ctcb { /* Channel block in the CTSIA. */N unsigned char ctcb$b_dvatr; /* Device attributes */N unsigned char ctcb$b_chatr; /* Channel attributes k */N unsigned short int ctcb$w_statesz; /* State size */N int (*ctcb$l_phy_entry)(); /* Physical entry point */N int (*ctcb$l_vir_entry)(); /* Virtual entry point */N void *ctcb$l_phy_segment; /* IO segment physical addr */N void *ctcb$l_vir_segment; /* IO segment virtual addr */N void *ctcb$l_phy_extend; /* Extended state phys. addr */N void *ct lcb$l_vir_extend; /* Extended state virt. addr */ } CTCB;N#define CTIOS$K_SIZE 8 /* Descriptor length */N#define CTIOS$C_SIZE 8 /* Descriptor length */ typedef struct _ctios {N/* Console I/O segment array and descriptors */ __union { __struct {O unsigned short int ctios$w_sgmt_count; /* # segments for channel */& short int ctios$w_spar me_1;R unsigned char ctios$b_base_segment; /* Offset for first segment dx. */$ } ctios$r_segment_count; __struct {N unsigned short int ctios$w_pgcount; /* Pages in this segment */& short int ctios$w_spare_2;N void *ctios$l_segment; /* Physical Segment address */) } ctios$r_segment_descriptor; } ctios$r_counted_array; } CTIOS; #if !defined(__VAXC)Y#define ctios$w_sgmt_count ctios$r_cou nnted_array.ctios$r_segment_count.ctios$w_sgmt_count]#define ctios$b_base_segment ctios$r_counted_array.ctios$r_segment_count.ctios$b_base_segmentX#define ctios$w_pgcount ctios$r_counted_array.ctios$r_segment_descriptor.ctios$w_pgcountX#define ctios$l_segment ctios$r_counted_array.ctios$r_segment_descriptor.ctios$l_segment"#endif /* #if !defined(__VAXC) */ #define CTSI$K_MODULE_COUNT 6#define CTSI$C_MODULE_COUNT 6#define CTSI$K_CHN_COUNT 6#define CTSI$C_CHN_COUNT 6#define CTSI$M_C oMUSE 0x3#define CTSI$M_INUSE 0x4#define CTSI$M_CM 0x10N#define CTSI$S_CTSIDEF 316 /* Old size name - synonym */ typedef struct _ctsi {N struct _ctsi *ctsi$l_base; /* Physical base address of CTSI */N unsigned short int ctsi$w_size; /* Size in bytes of CTSI */N unsigned short int ctsi$w_ident; /* Indent string "CT" */ unsigned char ctsi$b_spare0;N unsigned char ctsi$b_chksum; /* Checksum of first byt pes */ __union {N unsigned char ctsi$b_flags; /* Flags */ __struct {& unsigned ctsi$v_cmuse : 2;N unsigned ctsi$v_inuse : 1; /* Routine in use */' unsigned ctsi$v_spare0 : 1;N unsigned ctsi$v_cm : 1; /* Console mode */( unsigned ctsi$v_fill_0_ : 3; } ctsi$r_flags_bits; } ctsi$r_flags_overlay;N unsigned char ctqsi$b_revisn; /* Console revision */N unsigned __int64 ctsi$q_module_desc [6]; /* Module descriptors */P unsigned int ctsi$l_chnblk [42]; /* Channel blocks of size = (7 longs) */N unsigned __int64 ctsi$q_save; /* Save ptrs */N unsigned __int64 ctsi$q_restore; /* Restore pointers */N unsigned __int64 ctsi$q_trans; /* Translate ptrs */N unsigned __int64 ctsi$q_getchr; /* G rET CHAR ptrs */N unsigned int ctsi$l_getchr_state [4]; /* GET CHAR state */N unsigned __int64 ctsi$q_putchr; /* PUT CHAR ptrs */N unsigned int ctsi$l_putchr_state [4]; /* PUT CHAR state */N unsigned __int64 ctsi$q_putmsg; /* Put message routine */N unsigned __int64 ctsi$q_readprompt; /* Read with prompt routine */ } CTSI; #if !defined(__VAXC)6#define ctsi$b_flags ctsi$r_fl sags_overlay.ctsi$b_flagsH#define ctsi$v_cmuse ctsi$r_flags_overlay.ctsi$r_flags_bits.ctsi$v_cmuseH#define ctsi$v_inuse ctsi$r_flags_overlay.ctsi$r_flags_bits.ctsi$v_inuseJ#define ctsi$v_spare0 ctsi$r_flags_overlay.ctsi$r_flags_bits.ctsi$v_spare0B#define ctsi$v_cm ctsi$r_flags_overlay.ctsi$r_flags_bits.ctsi$v_cm"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_poitnter_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CTSIDEF_LOADED */ ww@F[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, uand is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** auvthorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************************************************** w*****************/=/* Created: 7-Oct-2024 15:23:37 by OpenVMS SDL V3.7 */G/* Source: 16-MAR-2004 13:41:34 $1$DGA8345:[LIB_H.SRC]CWPSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CWPSDEF ***/#ifndef __CWPSDEF_LOADED#define __CWPSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_axlignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VyAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* cwpssrv - Common service structure header */N/* */N/* All cwpsxxx$ packets contain the following h zeader information. */N/* */N/* Fields marked with ++ must be filled/zeroed by service-specific */N/* routines (at least for pcntrl services) */N/* */N/*- */ #include N/* { */Q/* The CWPSSRV$ structure is exchanged with remote nodes. Any updates to this */N/* structure must take mixed-version operation into account. */N/* */ #define CWPSSRV$M_BTX_DONE 0x1#define CWPSSRV$M_SEC_CLASS 0x1#define CWPSSRV$M_JPIBUF 0x2#define CWPSSRV$M_NOQUOTA 0x4 #define CWPSSRV$M_GROUP_PRIV 0x8!#define CWPSSRV$M_WORLD_PRIV 0x10#define CWPSSRV$M_SECAUDIT 0 |x20#define CWPSSRV$M_NOAUDIT 0x40 #define CWPSSRV$M_OPER_PRIV 0x80N#define CWPSSRV$K_RETRY_CNT 5 /* five retries is about */N/* 4 seconds */N#define CWPSSRV$K_LENGTH 112 /* length of data structure common */N#define CWPSSRV$K_SRVCODE_BEGIN 0 /* - marker for beginning of codes */N#define CWPSSRV$K_CANWAK 1 /* $CANWAK service */N#define CWPSSRV$K_DELPRC 2 } /* $DELPRC service */N#define CWPSSRV$K_FORCEX 3 /* $FORCEX service */N#define CWPSSRV$K_RESUME 4 /* $RESUME service */N#define CWPSSRV$K_SCHDWK 5 /* $SCHDWK service */N#define CWPSSRV$K_SETPRI 6 /* $SETPRI service */N#define CWPSSRV$K_SUSPND 7 /* $SUSPND service */N#define CWPSSRV$K_WAKE 8 /* $WAKE service ~ */N#define CWPSSRV$K_SRVCODE_END 9 /* - marker for end of SRV codes */N/* CWPS subtypes for other services */N#define CWPSSRV$K_GETJPI 20 /* $GETJPI service */N#define CWPSSRV$K_CREPRC 21 /* $CREPRC service */N#define CWPSSRV$K_TERMIN 22 /* process termination message */N/* CWPS subtypes for security service codes */N#defin e CWPSSRV$K_GRANTID 28 /* $GRANTID service */N#define CWPSSRV$K_REVOKID 29 /* $WAKE service */N#define CWPSSRV$K_VERSION_1 1 /* initial version */#define CWPSSRV$K_VERSION_2 2#define CWPSSRV$K_VERSION_3 3#define CWPSSRV$K_VERSION_4 4#define CWPSSRV$K_VERSION_5 5#define CWPSSRV$K_VERSION_6 6#define CWPSSRV$K_VERSION_7 7#define CWPSSRV$K_VERSION_8 8#define CWPSSRV$K_VERSION_9 9#define CWPSSRV$ K_VERSION_10 10#define CWPSSRV$K_VERSION_11 11#define CWPSSRV$K_VERSION_12 12$#define CWPSSRV$K_INITIAL_MAJ_VERS 1$#define CWPSSRV$K_INITIAL_MIN_VERS 1!#define CWPSSRV$S_$CWPSSRVDEF 112 typedef struct _cwpssrv {N unsigned int cwpssrv$l_send_length; /* length sent to partner */N unsigned int cwpssrv$l_return_length; /* length returned from partner */K unsigned short int cwpssrv$w_size; /* size of structure ++ */M unsigned char cwpssrv$b_type;  /* structure type code ++ */T unsigned char cwpssrv$b_subtype; /* structure subtype and service code ++ */S unsigned short int cwpssrv$w_btx_status; /* status of block transfer request */ __union {N unsigned char cwpssrv$b_btx_flags; /* state of block transfer */ __struct {N unsigned cwpssrv$v_btx_done : 1; /* block transfer is complete */+ unsigned cwpssrv$v_fill_4_ : 7; } cwpssrv$r_fill_1_; } cwpssrv$r_fill_0_;N unsigned char cwpssrv$b_func; /* CLSMSG request function code */Q unsigned short int cwpssrv$w_srv_maj_vers; /* incompatible version formats */R unsigned short int cwpssrv$w_srv_min_vers; /* upwards compatible extensions */Q unsigned short int cwpssrv$w_ext_maj_vers; /* incompatible version formats */R unsigned short int cwpssrv$w_ext_min_vers; /* upwards compatible extensions */N unsigned int cwpssrv$l_status; /* status from remote service  */N unsigned int cwpssrv$l_bxfr_status; /* status from block transfer */O unsigned int cwpssrv$l_maximum_length; /* maximum possible return length */ __union {N unsigned int cwpssrv$l_flags; /* longword of flags */ __struct {N unsigned cwpssrv$v_sec_class : 1; /* sec class present... */N unsigned cwpssrv$v_jpibuf : 1; /* jpi requests buffered */N unsigned cwpssrv$v_noquota : 1; /* quota has not been charged */a unsigned cwpssrv$v_group_priv : 1; /* requestor running image with GROUP privilege */a unsigned cwpssrv$v_world_priv : 1; /* requestor running image with WORLD privilege */d unsigned cwpssrv$v_secaudit : 1; /* requestor running with mandatory process auditing */N unsigned cwpssrv$v_noaudit : 1; /* requestor is part of TCB */P unsigned cwpssrv$v_oper_priv : 1; /* requestor has OPER privilege */ } cwpssrv$r_fill_3_; } cwpssrv$r_fill_2_;R unsigned int cwpssrv$l_ext_offset; /* offset to service-specific extension */T void *cwpssrv$a_post_routine; /* address of post-processing routine ++ */N unsigned int cwpssrv$l_rqstr_csid; /* CSID of the requestor's node */N unsigned int cwpssrv$l_rqstr_pid; /* IPID of the requestor */N unsigned int cwpssrv$l_rqstr_epid; /* EPID of the requestor */N unsigned int cwpssrv$l_rqstr_imgcnt; /* image count of requestor */O unsigned int cwpssrv$l_rqstr_rightslen; /* length of process rights info */P unsigned int cwpssrv$l_rqstr_rightsoff; /* offset to start of rights info */N void *cwpssrv$l_rqstr_pidadr; /* original pid address from user */N unsigned int cwpssrv$l_partner_csid; /* CSID of the partner node */N unsigned int cwpssrv$l_sought_epid; /* epid for target process */N unsigned int cwpssrv$l_return_epid; /* actual epid from target process */O unsigned short int cwpssrv$w_prcnamlen; /* length of target process name */X unsigned short int cwpssrv$w_prcnamoff; /* offset to start of target process name */N unsigned int cwpssrv$l_free_offset; /* offset to free data area */N unsigned int cwpssrv$l_spare1; /* zero if unused */N unsigned short int cwpssrv$w_spare2; /* zero if unused */N unsigned char cwpssrv$b_spare3; /* zero if unused */N unsign ed char cwpssrv$b_retries_left; /* number of retries remaining */N unsigned __int64 cwpssrv$q_time; /* time structure allocated */ } CWPSSRV; #if !defined(__VAXC)A#define cwpssrv$b_btx_flags cwpssrv$r_fill_0_.cwpssrv$b_btx_flagsQ#define cwpssrv$v_btx_done cwpssrv$r_fill_0_.cwpssrv$r_fill_1_.cwpssrv$v_btx_done9#define cwpssrv$l_flags cwpssrv$r_fill_2_.cwpssrv$l_flagsS#define cwpssrv$v_sec_class cwpssrv$r_fill_2_.cwpssrv$r_fill_3_.cwpssrv$v_sec_classM#define cwpssrv$v_jpibuf cwpssrv$r_fill_2_.cwpssrv$r_fill_3_.cwpssrv$v_jpibufO#define cwpssrv$v_noquota cwpssrv$r_fill_2_.cwpssrv$r_fill_3_.cwpssrv$v_noquotaU#define cwpssrv$v_group_priv cwpssrv$r_fill_2_.cwpssrv$r_fill_3_.cwpssrv$v_group_privU#define cwpssrv$v_world_priv cwpssrv$r_fill_2_.cwpssrv$r_fill_3_.cwpssrv$v_world_privQ#define cwpssrv$v_secaudit cwpssrv$r_fill_2_.cwpssrv$r_fill_3_.cwpssrv$v_secauditO#define cwpssrv$v_noaudit cwpssrv$r_fill_2_.cwpssrv$r_fill_3_.cwpssrv$v_noauditS#define cwpssrv$v_ oper_priv cwpssrv$r_fill_2_.cwpssrv$r_fill_3_.cwpssrv$v_oper_priv"#endif /* #if !defined(__VAXC) */  N#define CWPS$_ENABLED 1 /* assemble the code */N#define CWPS$_NERVOUS 0 /* do reasonable checking */N#define CWPS$_SCARED 0 /* do a lot of consistency checking */N#define CWPS$_PARANOID 0 /* do excessive checking */N#define CWPS$_STATISTICS 1 /* collect statistics  */N#define CWPSCAN$K_LENGTH 0 /* length of $CANWAK */N#define CWPSRES$K_LENGTH 0 /* length of $RESUME */N#define CWPSSUS$K_LENGTH 0 /* length of $SUSPND */N#define CWPSWAK$K_LENGTH 0 /* length of $WAKE */N/* */N/* The CWPSDEL$ structure is exchanged with remote nodes. Any updates */N/* to this structure  must take mixed-version operation into account. */N/* Sender stores delprc flags argument (longword) in flags extension. */N#define CWPSDEL$K_LENGTH 4 /* length of data structure */N#define CWPSDEL$S_$CWPSDELDEF 4 /* Old size name - synonym */ typedef struct _cwpsdel {N unsigned int cwpsdel$l_flags; /* flags to pass to remote */ } CWPSDEL;'#define CWPSSRV$K_DELPRC_EXT_MIN_VERS 2N/*  */Q/* The CWPSFEX$ structure is exchanged with remote nodes. Any updates to this */N/* structure must take mixed-version operation into account. */N/* */N#define CWPSFEX$K_LENGTH 4 /* length of data structure */N#define CWPSFEX$S_$CWPSFEXDEF 4 /* Old size name - synonym */ typedef struct _cwpsfex {N unsigned int cwpsfex$l_code; /* code to pass to remote */ } CWPSFEX;N/* Version # of 6-cell SETPRI extension */$#define CWPSSRV$K_SETPRI_MIN_VERS2 2N/* */Q/* The CWPSPRI$ structure is exchanged with remote nodes. Any updates to this */N/* structure must take mixed-version operation into account. */N/*  */N#define CWPSPRI$K_LENGTH 24 /* length of data structure */N#define CWPSPRI$S_$CWPSPRIDEF 24 /* Old size name - synonym */ typedef struct _cwpspri {N void *cwpspri$l_user_prvpri; /* address of user's prvpri cell */N unsigned int cwpspri$l_pri; /* priority we send to remote */N unsigned int cwpspri$l_prvpri; /* priority we receive from remote */N void *cwpspri$l_user_prvpol; /* address of user's prvpol cell */N unsigned int cwpspri$l_pol; /* policy we send to remote (or -1) */P unsigned int cwpspri$l_prvpol; /* prev policy we receive from remote */ } CWPSPRI;N/* */Q/* The CWPSSWK$ structure is exchanged with remote nodes. Any updates to this */N/* structure must take mixed-version operation into account. */N/*  */N#define CWPSSWK$K_LENGTH 16 /* length of data structure */N#define CWPSSWK$S_$CWPSSWKDEF 16 /* Old size name - synonym */ typedef struct _cwpsswk {N unsigned __int64 cwpsswk$q_daytim; /* time to wake up */N unsigned __int64 cwpsswk$q_reptim; /* time to repeat wake up */ } CWPSSWK;N/* */Q/* The CWPSJPI$ structure is exchanged with remote  nodes. Any updates to this */N/* structure must take mixed-version operation into account. */N/* */N#define CWPSJPI$K_LENGTH 60 /* length of data structure */N#define CWPSJPI$S_$CWPSJPIDEF 60 /* Old size name - synonym */ typedef struct _cwpsjpi {N unsigned int cwpsjpi$l_pscan_off; /* offset to start of pscanctx */N unsigned int cwpsjpi$l_itmoff; /* offset to item list in structure */N unsigned int cwpsjpi$l_bufoff; /* offset to return buffer */N unsigned int cwpsjpi$l_vecoff; /* offset to vector for item addr */N unsigned int cwpsjpi$l_acboff; /* offset to acb structure */N void *cwpsjpi$l_itmlst; /* address of original item list */N unsigned int cwpsjpi$l_buflen; /* length of user's buffers */N void *cwpsjpi$l_iosbadr; /* user's I/O status address */N unsigned __int64 cwpsjpi$q_iosb; /* return iosb contents */N void (*cwpsjpi$l_astadr)(); /* AST address */N unsigned int cwpsjpi$l_astprm; /* AST parameter */N void *cwpsjpi$l_pscanctx_addr; /* PSCANCTX record address */P unsigned short int cwpsjpi$w_pscan_seqnum; /* sequence number of PSCANCTX */N unsigned char cwpsjpi$b_efn; /* event flag to set */N unsign ed char cwpsjpi$b_acmode; /* access mode of original call */O unsigned short int cwpsjpi$w_ctlflags; /* JPI$_GETJPI_CONTROL_FLAGS bits */N unsigned short int cwpsjpi$w_spare0; /* spare, align */ } CWPSJPI;N#define CWPSJPI_64$K_LENGTH 40 /* length of data structure */ typedef struct _cwpsjpi_64 {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */{ void *cwpsjpi_64$pq_rqstr_pidadr; /* user's address for PID argument: cwpssrv$l_rqstr_pid for $GETJPI will be -1. */#else- unsigned __int64 cwpsjpi_64$pq_rqstr_pidadr;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */q void *cwpsjpi_64$pq_itmlst; /* user's item list address: cwpsjpi$l_itmlst for $GETJPI will be - 1. */#else' unsigned __int64 cwpsjpi_64$pq_itmlst;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */m void *cwpsjpi_64$pq_iosbadr; /* user's IOSB address: cwpsjpi$l_iosbadr for $GETJPI will be -1. */#else( unsigned __int64 cwpsjpi_64$pq_iosbadr;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */_ void *cwpsjpi_64$pq_astadr; /* user's AST address: cwpsjpi$l_astadr will be -1. */#else' unsigned __int64 cwpsjpi_64$pq_astadr;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */a void *cwpsjpi_64$pq_astprm; /* user's AST parameter: cwpsjpi$l_astprm will be -1. */#else' unsigned __int64 cwpsjpi_64$pq_astprm;#endif } CWPSJPI_64;N/* */Q/* The CWPSCRE$ structure is exchanged with remote nodes. Any updates to this */N/* structure must take mixed-version operation into account. */N/* */ #define CWPSCRE$M_IMGDMP 0x1#define CWPSCRE$M_DEBUG 0x2#define CWPSCRE$M_DBGTRU 0x4$#d efine CWPSCRE$M_PARSE_EXTENDED 0x8%#define CWPSCRE$M_CASE_SENSITIVE 0x10N#define CWPSCRE$K_LENGTH 2100 /* length of data structure */N#define CWPSCRE$S_$CWPSCREDEF 2100 /* Old size name - synonym */ typedef struct _cwpscreprc {Q unsigned int cwpscre$l_base_offset; /* Offset of CWPSCRE from CWPSSRV base */Q unsigned int cwpscre$l_acboff; /* Offset of embedded ACB from CWPSCRE */N unsigned __int64 cwpscre$q_prvmsk; /* Privileges of new process */N unsigned __int64 cwpscre$q_iosb; /* Transaction status block */N unsigned int cwpscre$l_priority; /* Priority of new process */N unsigned int cwpscre$l_uic; /* UIC of new process */O unsigned int cwpscre$l_defprot; /* Default protection of new process */S unsigned int cwpscre$l_tmbu; /* Termination MB unit number of creator */N unsigned int cwpscre$l_spare1; /* zero if unused */N unsigned int cwpscre$l_spare2; /* zero if unused */N unsigned short int cwpscre$w_maxjobs; /* Maximum jobs limit */N unsigned short int cwpscre$w_maxdetach; /* Maximum detached jobs limit */N unsigned int cwpscre$l_astlm; /* AST LIMIT */N unsigned int cwpscre$l_biolm; /* BUFFERED I/O LIMIT */N unsigned int cwpscre$l_bytlm; /* BUFFERED I/O LIMIT */N unsigned int cwpscre$l_cpulm; /* CPU TIME LIMIT */N unsigned int cwpscre$l_diolm; /* DIRECT I/O LIMIT */N unsigned int cwpscre$l_fillm; /* OPEN FILE LIMIT */N unsigned int cwpscre$l_pgflquota; /* PAGING FILE QUOTA */N unsigned int cwpscre$l_prclm; /* SUB-PROCESS LIMIT */N unsigned int cwpscre$l_tqelm; /* TIMER QUEUE ENTRY LIMIT */N unsigned int cwpscre$l_wsquota; /* WORKING SET QUOTA */N unsigned int cwpscre$l_wsdefault; /* WORKING SET DEFAULT */N unsigned int cwpscre$l_enqlm; /* ENQUEUE LIMIT */N unsigned int cwpscre$l_wsextent; /* MAXIMUM WORKING SET SIZE */X unsigned int cwpscre$l_jtquota; /* JOB-WIDE LOGICAL NAME TABLE CREATION QUOTA */W unsigned int cwpscre$l_spare_quota1; /* Spare field in case a new quota is added */W unsigned int cwpscre$l_spare_quota2; /* Spare field in case a new quota is added */N unsigned int cwpscre$l_input_att; /* SYS$INPUT attributes */N unsigned int cwpscre$l_output_att; /* SYS$OUTPUT attributes */N unsigned int cwpscre$l_error_att; /* SYS$ERROR attributes */N unsigned int cwpscre$l_msgmask; /* MESSAGE FLAGS */N unsigned int cwpscre$l_uaf_flags; /* FLAGS FROM UAF RECORD */N unsigned int cwpscre$l_creprc_flags; /* Copy of $CREPRC status flags */ __union {N unsigned int cwpscre$l_flags; /* Miscellaneous flags for PQB */ __struct {Q unsigned cwpscre$v_imgdmp : 1; /* TAKE IMAGE DUMP ON SERIOUS ERROR */N unsigned cwpscre$v_debug : 1; /* /DEBUG startup desired */N unsigned cwpscre$v_dbgtru : 1; /* debugger present */S unsigned cwpscre$v_parse_extended : 1; /* Use PARSE_STYLE = EXTENDED */T unsigned cwpscre$v_case_sensitive : 1; /* Use CASE_LOOKUP = SENSITIVE */+ unsigned cwpscre$v_fill_7_ : 3; } cwpscre$r_fill_6_; } cwpscre$r_fill_5_;N char cwpscre$t_input [256]; /* LOGICAL NAME FOR INPUT */N char cwpscre$t_output [256]; /* LOGICAL NAME FOR OUTPUT */N char cwpscre$t_error [256]; /* LOGICAL NAME FOR ERROR OUTPUT */N char cwpscre$t_disk [256]; /* LOGICAL NAME FOR SYS$DISK */N char cwpscre$t_image [256]; /* IMAGE NAME FOR NEW PROCESS */N char cwpscre$t_ddstring [256]; /* DEFAULT DIRECTORY STRING */N char cwpscre$t_username [12]; /* User name of new process for JIB */Q char cwpscre$t_account [8]; /* Account name of new process for JIB */R char cwpscre$t_pqb_account [8]; /* Account name for new process for PQB */S __struct { /* MINIMUM AUTHORIZED SECURITY CLEARANCE */- unsigned char cwpscre$$$_fill_2 [20]; } cw pscre$r_min_class;S __struct { /* MAXIMUM AUTHORIZED SECURITY CLEARANCE */- unsigned char cwpscre$$$_fill_3 [20]; } cwpscre$r_max_class;N char cwpscre$t_cli_name [32]; /* CLI name */N char cwpscre$t_cli_table [32]; /* CLI table name */N char cwpscre$t_spawn_cli [32]; /* Spawn CLI name */N char cwpscre$t_spawn_table [256]; /* Spawn CLI table name */  } CWPSCREPRC; #if !defined(__VAXC)9#define cwpscre$l_flags cwpscre$r_fill_5_.cwpscre$l_flagsM#define cwpscre$v_imgdmp cwpscre$r_fill_5_.cwpscre$r_fill_6_.cwpscre$v_imgdmpK#define cwpscre$v_debug cwpscre$r_fill_5_.cwpscre$r_fill_6_.cwpscre$v_debugM#define cwpscre$v_dbgtru cwpscre$r_fill_5_.cwpscre$r_fill_6_.cwpscre$v_dbgtru]#define cwpscre$v_parse_extended cwpscre$r_fill_5_.cwpscre$r_fill_6_.cwpscre$v_parse_extended]#define cwpscre$v_case_sensitive cwpscre$r_fill_5_.cwpscre$r_fill_ 6_.cwpscre$v_case_sensitive"#endif /* #if !defined(__VAXC) */  N/* */R/* The CWPSTERM$ structure is exchanged with remote nodes. Any updates to this */N/* structure must take mixed-version operation into account. */N/* */ N#define CWPSTERM$K_LENGTH 108 /* length of data structure */N#define CWPSTERM$S_$CWPSTERMDEF 108 /* Old size name - synonym */ typedef struct _cwpsterm {S unsigned int cwpsterm$l_base_offset; /* Offset of CWPSTERM from CWPSSRV base */R unsigned int cwpsterm$l_acboff; /* Offset of embedded ACB from CWPSTERM */N unsigned __int64 cwpsterm$q_iosb; /* Transaction status block */f unsigned int cwpsterm$l_deleted_proc_epid; /* EPID of process whose termination message this is */N unsigned int cwpsterm$l_spare; /* Spare field  */N char cwpsterm$t_term_msg [84]; /* termination message */ } CWPSTERM; N/* */P/* The CWPSVEC$ structure is a local structure. If modified, you do not need */Q/* to take mixed-version operation into account, however you must be sure that */P/* all modules and images which reference the structure are updated together. */P/* Code that utilizes this structure assumes it resides at a  quadword-aligned */N/* VA. The structure must always contain an integral number of quadwords. */N/* */ #define CWPSVEC$M_64_BIT_ILE 0x1N#define CWPSVEC$K_LENGTH 24 /* length of data structure */N#define CWPSVEC$S_$CWPSVECDEF 24 /* Old size name - synonym */ typedef struct _cwpsvec {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __requ ired_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cwpsvec$pq_usr_bufadr; /* user's address for buffer items */#else( unsigned __int64 cwpsvec$pq_usr_bufadr;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */P void *cwpsvec$pq_usr_lenadr; /* user's address for returned length */#else( unsigned __int64 cwpsvec$pq_usr_lenadr;#endif __union {% unsigned int cwpsvec$l_flags; __struct {. unsigned cwpsvec$v_64_bit_ile : 1;, unsigned cwpsvec$v_fill_10_ : 7; } cwpsvec$r_fill_9_; } cwpsvec$r_fill_8_;N int cwpsvec$l_fill_1; /* Keep structure QW-aligned */ } CWPSVEC; #if !defined(__VAXC)9#define cwpsvec$l_flags cwpsvec$r_fill_8_.cwpsvec$l_flagsU#define cwpsvec$v_64_bit_ile cwpsvec$r_fill_8_.cwpsvec$r_fill_ 9_.cwpsvec$v_64_bit_ile"#endif /* #if !defined(__VAXC) */ N/* */P/* The CWPSACB$ structure is a local structure. If modified, you do not need */Q/* to take mixed-version operation into account, however you must be sure that */P/* all modules and images which reference the structure are updated together. */N/* */N#define CWPSACB$K_ACB_LENGTH 36  /* length of embedded block */Q#define CWPSACB$K_LENGTH 92 /* length of data structure (less PCB) */N#define CWPSACB$S_$CWPSACBDEF 97 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _acb; struct _csb; struct _cdrp; struct _psb; #endif /* #ifdef __cplusplus */ typedef struct _cwpsacb { __union {( char cwpsacb$b_cwpsacb_fkb [48]; __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _acb *cwpsacb$l_astqfl; /* ast queue forward link */N struct _acb *cwpsacb$l_astqbl; /* ast queue backward link */N unsigned short int cwpsacb$w_size; /* structure size in bytes */N unsigned char cwpsacb$b_type; /* structure type code */N unsigned c har cwpsacb$b_rmod; /* request access mode */N unsigned int cwpsacb$l_pid; /* process id of request */N void (*cwpsacb$l_ast)(); /* ast routine address */N unsigned int cwpsacb$l_astprm; /* ast parameter */' int cwpsacb$l_acb_fill [2];P void (*cwpsacb$l_kast)(); /* internal kernel mode xfer address */! } cwpsacb$r_fill_12_; } cwpsacb$r_fill_11_;N void *cwpsacb$l_bufadr; /* address of buffer */N unsigned int cwpsacb$l_buflen; /* length of the buffer */N void *cwpsacb$l_msgbuf; /* message buffer address */N struct _csb *cwpsacb$l_csb; /* csb address */N struct _cdrp *cwpsacb$l_cdrp; /* cdrp address */N unsigned int cwpsacb$l_read_length; /* length of bxfr read request */N unsigned int cwpsacb$l_write_length; / * length of bxfr write request */N unsigned int cwpsacb$l_rightsdesc [2]; /* descriptor for rightslist */N unsigned char cwpsacb$b_func; /* function code from message */# unsigned char cwpsacb$b_spare0;( unsigned short int cwpsacb$w_spare1;X struct _psb *cwpsacb$ar_remote_psb; /* address of remote process security profile */N/* trojan PCB should be octaword aligned */ char cwpsacb$b_fill_13_ [4];c#if !defined(__NOBASEALI GN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifN unsigned char cwpsacb$b_trojan_pcb; /* start of false PCB */ } CWPSACB; #if !defined(__VAXC)F#define cwpsacb$b_cwpsacb_fkb cwpsacb$r_fill_11_.cwpsacb$b_cwpsacb_fkbO#define cwpsacb$l_astqfl cwpsacb$r_fill_11_.cwpsacb$r_fill_12_.cwpsacb$l_astqflO#define cwpsacb$l_astqbl cwpsacb$r_fill_11_.cwpsacb$r_fill_12_.cwpsacb$l_astqblK#define cwpsacb$w_size cwpsacb$r_fill_11_.cwpsacb$r_fill_12_.cwpsacb$w_sizeK#define cwpsacb$b_type cwpsacb$r_fill_11_.cwpsacb$r_fill_12_.cwpsacb$b_typeK#define cwpsacb$b_rmod cwpsacb$r_fill_11_.cwpsacb$r_fill_12_.cwpsacb$b_rmodI#define cwpsacb$l_pid cwpsacb$r_fill_11_.cwpsacb$r_fill_12_.cwpsacb$l_pidI#define cwpsacb$l_ast cwpsacb$r_fill_11_.cwpsacb$r_fill_12_.cwpsacb$l_astO#define cwpsacb$l_astprm cwpsacb$r_fill_11_.cwpsacb$r_fill_12_.cwpsacb$l_astprmK#define cwpsacb$l_ka st cwpsacb$r_fill_11_.cwpsacb$r_fill_12_.cwpsacb$l_kast"#endif /* #if !defined(__VAXC) */ N/* */P/* The CWPSSQH$ structure is a local structure. If modified, you do not need */Q/* to take mixed-version operation into account, however you must be sure that */P/* all modules and images which reference the structure are updated together. */N/* */N #define CWPSSQH$K_LENGTH 32 /* length of data structure */N#define CWPSSQH$S_$CWPSSQHDEF 32 /* Old size name - synonym */ #pragma __nomember_alignmenttypedef struct _cwpssqh {N struct _cwpssqh *cwpssqh$l_flink; /* forward link */N struct _cwpssqh *cwpssqh$l_blink; /* back link */N unsigned short int cwpssqh$w_size; /* size of structure (SQH only) */N unsigned char cwpssqh$b_type; /* s tructure type code */N unsigned char cwpssqh$b_subtype; /* structure subtype */N unsigned int cwpssqh$l_alloc_length; /* actual length of allocation */N unsigned int cwpssqh$l_mpid; /* master pid */N unsigned int cwpssqh$l_spare0; /* enough to make it octaword */N unsigned int cwpssqh$l_spare1; /* aligned... */" unsigned int cwpssqh$l_spare3; } CWPSSQH;N/*  */S/* The CWPSNODI*$ structures are local structures. If modified, you do not need */Q/* to take mixed-version operation into account, however you must be sure that */Q/* all modules and images which reference the structures are updated together. */N/* */N#define CWPSNODIH$K_HEADER 16 /* length of data structure */N#define CWPSNODIH$S_$CWPSNODIH DEF 17 /* Old size name - synonym */ typedef struct _cwpsnodih {N struct _cwpsnodih *cwpsnodih$l_flink; /* forward link */N struct _cwpsnodih *cwpsnodih$l_blink; /* back link */N unsigned short int cwpsnodih$w_size; /* size of structure */N unsigned char cwpsnodih$b_type; /* structure type code */N unsigned char cwpsnodih$b_subtype; /* structure subtype */N unsigned int cwpsn odih$l_count; /* count of nodes */N unsigned char cwpsnodih$b_node_list; /* start of list of node blocks */ } CWPSNODIH;N#define CWPSNODI$K_LENGTH 32 /* length of data structure */N#define CWPSNODI$S_$CWPSNODIDEF 32 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _sb; #endif /* #ifdef __cplusplus */ typedef struct _cwpsnodi {N unsigned int cwpsnodi$l_hwtype; /*  hardware type (and flink) */N unsigned short int cwpsnodi$w_hw_model; /* integer model code */N unsigned short int cwpsnodi$w_sparew; /* spare */N unsigned int cwpsnodi$l_csid; /* node's csid */N unsigned char cwpsnodi$b_name [16]; /* node's name (ASCIC) */N struct _sb *cwpsnodi$l_sb; /* sb address */ } CWPSNODI; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CWPSDEF_LOADED */ wwp[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential  **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************* *******************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */F/* Source: 05-MAR-1996 18:11:49 $1$DGA8345:[LIB_H.SRC]CXBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $CXBDEF ***/#ifndef __CXBDEF_LOADED#define __CXBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* + */N/* CXB - COMPLEX CHAINED BUFFER */N/*  */N/* THESE OFFSETS ARE USED IN THE HEADER OF DISJOINT SEGMENTS */N/* WHICH ARE TO BE PRESENTED TO THE USER AS A UNIT. */N/* */N/* - */ #define CXB$M_RESP 0x1N#define CXB$L_NI_ALTXMT 28 /* ALTSTART XMT parameters */"#define CXB$C_AGENT_SCRATCH_LEN 52N/* This marks the length of the standard CXB. */#define CXB$K_LENGTH 92#define CXB$C_LENGTH 92N/* Data link layer scratch space */#define CXB$M_FLTR_MCA 0x1#define CXB$M_FLTR_CTL 0x2#define CXB$M_FLTR_SRC 0x4#define CXB$M_FLTR_STARTUP 0x1#define CXB$M_FLTR_INTXMIT 0x2N#define CXB$T_R_DATA 128 /* Start of RCV data */N#define CXB$W_R_LEN_802 140 /* 802 length field  */N#define CXB$T_R_USER_ETH 142 /* Start of user ETH data */N#define CXB$W_R_SIZE 142 /* Size of message if padded */N#define CXB$X_R_CTL 144 /* 802 CTL field */N#define CXB$G_R_PID 145 /* 5-byte Protocol Identifier */N#define CXB$T_R_USER_802E 150 /* Start of user 802E data */N#define CXB$C_DLL 52 /* Size of CXB$T_DLL */N#define CXB$C_DLL_SCRATCH_LEN 52 /* Size of CXB$T_DLL */N/* ** This field must be quadword aligned for CNDRIVER. */N#define CXB$K_HEADER 144 /* CXB size up to this point */N#define CXB$C_HEADER 144 /* CXB size up to this point */P#define CXB$C_TRAILER 4 /* Space after CXB data for CRC code */N#define CXB$K_OVERHEAD 148 /* CXB$C_HEADER + CXB$C_TRAILER */N#define CXB$C_OVERHEAD 148  /* CXB$C_HEADER + CXB$C_TRAILER */  9#ifdef __cplusplus /* Define structure prototypes */ struct _irp; struct _dcb; struct _ucb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cxb {#pragma __nomember_alignment __union {N __struct { /* CXB can be in a queue... */N struct _cxb *cxb$l_fl; /* Forward queue link */N struct _cxb *cxb$l_bl; /* Backward queue link */ } cxb$r_qlinks;N/* ...or... */N __struct { /* CXB for IRP sent to I/O Post */P void *cxb$ps_pktdata; /* Pointer to buffered data in packet */a void *cxb$ps_uva32; /* 3 2-bit pointer to user's buffer, or BUFIO$K_64 (-1) */ } cxb$r_iopost; } cxb$r_qlinks_overlay;N unsigned short int cxb$w_size; /* Block size */N unsigned char cxb$b_type; /* Block type */ __union {N unsigned char cxb$b_flag; /* Flag byte */ __struct {N unsigned cxb$v_resp : 1; /* Command/Response indicator */( unsigned cxb$v_f ill_16_ : 7; } cxb$r_fill_1_; } cxb$r_fill_0_;N unsigned short int cxb$w_boff; /* Offset to data link data */N unsigned short int cxb$w_bcnt; /* Size of data link data */U void *cxb$l_data_chain; /* Pointer to data chain buffer descriptor */\ unsigned __int64 cxb$q_station; /* Contains destination address or source address */W unsigned short int cxb$w_ctl; /* 802.2 ctl field either byte or word value */N unsigned char cxb$b_ctl_size; /* 802.2 ctl field value size */N unsigned char cxb$b_dsap; /* 802.2 ALT/FFI XMT dest sap */N unsigned __int64 cxb$q_reserved; /* Reserved for future use */N/* Agent specific scratch space. */ __union {& char cxb$t_agent_scratch [52];N/* DECnet-VAX agent specific fields. */ __union {2 unsigned char cxb$t_agent_decnet [52]; __struct {N unsigned short int cxb$w_length; /* Length of data */V unsigned short int cxb$w_offset; /* Offset to start of nsp message */N unsigned char cxb$b_code; /* Buffer code */N unsigned char cxb$b_sts; /* Status fields */U unsigned short int cxb$w_channel; /* Store channel number for AST */Q void *cxb$l_link; /* Link word for chained data message */N struct _irp *cxb$l_irp; /* IRP address for transmits */N int (*cxb$l_end_action)(); /* Pointer to I/O done routine */Q/* The following fields contain the context that NSP needs to process a packet */N/* which has been received out of order. */N void *cxb$l_r_nsp_msg; /* This is the address of the next */N/* byte in the NSP message after  */N/* the segment number field (R1) */R unsigned int cxb$l_r_data_size; /* This is the number of as yet */N/* unaccounted bytes in message (R2) */b unsigned short int cxb$w_r_seg_num; /* This is the messages segment number (R3) */N short int cxb$w_filler_1; /* Filler to longword align */P/* Backlink pointer for NSP to associate the CXB with the user's originating */P/* IRP. The non-agent specific field, CXB$L_IRP, cannot be used because the */O/* datalink drivers use this field for the same purpose, but different IRP. */N/* The datalink's IRP is the DECnet routing supplied IRP queued to the */N/* altstart interface. */N struct _irp *cxb$l_user_irp; /* link to user's IRP */N struct _dcb *cxb$l_last_dcb; /* pointer to last DCB */N/* 64 -bit pointer to user buffer address that's valid if and only if */N/* CXB$PS_UVA32 contains the value BUFIO$K_64 (-1). */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *cxb$pq_uva64; /* 64-bit pointer to user's buffer */#else unsigned __int64 cxb$pq_uva64;#endif } cxb$r_fill_3_; } cxb$r_fill_2_; } cxb$r_agent_overlay;N/* Size of the agent scratch area */#pragma __nomember_alignment __union { char cxb$t_dll [52];N/* The following three structures define the fields used by the */N/* Ethernet/802 datalink drive rs. */ __union {/ unsigned char cxb$t_dll_ni802 [52]; __struct {N unsigned char cxb$b_ni_func; /* Internal function code */N unsigned char cxb$b_r_flags; /* Flags */ __union {N unsigned short int cxb$w_ni_rid; /* Request ID */ __struct {N unsigned char cxb$b_ni_slot; /* Ma pping slot number */N unsigned char cxb$b_ni_ring; /* Ring Entry number */( } cxb$r_fill_7_;$ } cxb$r_fill_6_;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _irp *cxb$l_t_irp; /* User IRP address */S unsigned short int cxb$w_r_nchain; /* Number of buffers in chain */T unsigned short int cxb$w_r_lenerr; /* Length and Rcv error status */N struct _ucb *cxb$l_r_ucb; /* UCB address of receiver */O unsigned short int cxb$w_hdr_size; /* Size of receive header */N unsigned char cxb$b_r_fmt; /* Receive packet format */ __union { __union {[ unsigned char cxb$b_r_filter; /* Receive CXB filtering mask word * /# __struct {_ unsigned cxb$v_fltr_mca : 1; /* MCA filtering has been performed */_ unsigned cxb$v_fltr_ctl : 1; /* CTL filtering has been performed */_ unsigned cxb$v_fltr_src : 1; /* SRC filtering has been performed */8 unsigned cxb$v_fill_17_ : 5;, } cxb$r_fill_9_;( } cxb$r_fill_8_; __un ion {\ unsigned char cxb$b_t_filter; /* Transmit CXB filtering mask word */# __struct {[ unsigned cxb$v_fltr_startup : 1; /* Delete CXB, complete IRP */Z unsigned cxb$v_fltr_intxmit : 1; /* Add CXB to Receive list */8 unsigned cxb$v_fill_18_ : 6;- } cxb$r_fill_11_;) } cxb$r_fill_10_;# } cxb$r_filter; } cxb$r_fill_5_; } cxb$r_fill_4_; __union {2 unsigned char cxb$t_dll_ni802xmt [52]; __struct {. char cxbdef$$_nixmt_fill [38];N unsigned char cxb$t_t_data [14]; /* Start of standard XMT */! } cxb$r_fill_13_; } cxb$r_fill_12_; __union {2 unsigned char cxb$t_dll_ni802rcv [52]; __struct {/ char cxbdef$$_nircv_fill1 [36];N unsigned short int cxb$g_r_dest [3]; /* Destination address */N unsigned short int cxb$g_r_src [3]; /* Source address */N unsigned short int cxb$w_r_ptype; /* Protocol type */N unsigned char cxb$b_r_dsap; /* 802 DSAP field */N unsigned char cxb$b_r_ssap; /* 802 SSAP field */! } cxb$r_fill_15_; } cxb$r_fill_14_; } cxb$r_dll_overlay;R  int cxbdef$$_fill_1; /* This represents the space taken for */N/* the CRC trailer */ char cxb$b_fill_19_ [4]; } CXB; #if !defined(__VAXC);#define cxb$l_fl cxb$r_qlinks_overlay.cxb$r_qlinks.cxb$l_fl;#define cxb$l_bl cxb$r_qlinks_overlay.cxb$r_qlinks.cxb$l_blG#define cxb$ps_pktdata cxb$r_qlinks_overlay.cxb$r_iopost.cxb$ps_pktdataC#define cxb$ps_uva32 cxb$r_qlinks_overlay.cxb$r_iopost.cxb$ps_uva32+#define cxb$b_flag cxb$r_fill_0_.cxb$b_flag9#define cxb$v_resp cxb$r_fill_0_.cxb$r_fill_1_.cxb$v_respC#define cxb$t_agent_scratch cxb$r_agent_overlay.cxb$t_agent_scratchO#define cxb$t_agent_decnet cxb$r_agent_overlay.cxb$r_fill_2_.cxb$t_agent_decnetQ#define cxb$w_length cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$w_lengthQ#define cxb$w_offset cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$w_offsetM#define cxb$b_code cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$b_codeK#define cxb$b_sts cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$b_stsS#define cxb$w_channel cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$w_channelM#define cxb$l_link cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$l_linkK#define cxb$l_irp cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$l_irpY#define cxb$l_end_action cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$l_end_actionW#define cxb$l_r_nsp_msg cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$l_r_nsp_msg[#define cxb$l_r_data_size cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$l_r_data_sizeW#define cxb$w_r_seg_num cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$w_r_seg_numU#define cxb$l_user_irp cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$l_user_irpU#define cxb$l_last_dcb cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$l_last_dcbQ#define cxb$pq_uva64 cxb$r_agent_overlay.cxb$r_fill_2_.cxb$r_fill_3_.cxb$pq_uva64-#define cxb$t_dll cxb$r_dll_overlay.cxb$t_dllG#define cxb$t_dll_ni802 cxb$r_dll_overlay.cxb$r_fill_4_.cxb$t_dll_ni802Q#define cxb$b_ni_func cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$b_ni_funcQ#define cxb$b_r_flags cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$b_r_flags]#define cxb$w_ni_rid cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$r_fill_6_.cxb$w_ni_ridm#define cxb$b_ni_slot cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$r_fill_6_.cxb$r_fill_7_.cxb$b_ni_slotm#define cxb$b_ni_ring cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$r_fill_6_.cxb$r_fill_7_.cxb$b_ni_ringM#define cxb$l_t_irp cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$l_t_irpS#define cxb$w_r_nchain cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$w_r_nchainS#define cxb$w_r_lenerr cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$w_r_lenerrM#define cxb$l_r_ucb cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$l_r_ucbS#define cxb$w_hdr_size cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$w_hdr_sizeM#define cxb$b_r_fmt cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$b_r_fmtO#define cxb$r_filter cxb$r_dll_overlay.cxb$r_fill_4_.cxb$r_fill_5_.cxb$r_filter@#define cxb$b_r_filter cxb$r_filter.cxb$r_fill_8_.cxb$b_r_filterN#define cxb$v_fltr_mca cxb$r_filter.cxb$r_fill_8_.cxb$r_fill_9_.cxb$v_fltr_mcaN#define cxb$v_fltr_ctl cxb$r_filter.cxb$r_fill_8_.cxb$r_fill_9_.cxb$v_fltr_ctlN#define cxb$v_fltr_src cxb$r_filter.cxb$r_fill_8_.cxb$r_fill_9_.cxb$v_fltr_srcA#define cxb$b_t_filter cxb$r_filter.cxb$r_fill_10_.cxb$b_t_filterX#define cxb$v_fltr_startup cxb$r_filter.cxb$r_fill_10_.cxb$r_fill_11_.cxb$v_fltr_startupX#define cxb$v_fltr_intxmit cxb$r_filter.cxb$r_fill_10_.cxb$r_fill_11_.cxb$v_fltr_intxmitN#define cxb$t_dll_ni802xmt cxb$r_dll_overlay.cxb$r_fill_12_.cxb$t_dll_ni802xmtQ#define cxb$t_t_data cxb$r_dll_overlay.cxb$r_fill_12_.cxb$r_fill_13_.cxb$t_t_dataN#define cxb$t_dll_ni802rcv cxb$r_dll_overlay.cxb$r_fill_14_.cxb$t_dll_ni802rcvQ#define cxb$g_r_dest cxb$r_dll_overlay.cxb$r_fill_14_.cxb$r_fill_15_.cxb$g_r_destO#define cxb$g_r_src cx b$r_dll_overlay.cxb$r_fill_14_.cxb$r_fill_15_.cxb$g_r_srcS#define cxb$w_r_ptype cxb$r_dll_overlay.cxb$r_fill_14_.cxb$r_fill_15_.cxb$w_r_ptypeQ#define cxb$b_r_dsap cxb$r_dll_overlay.cxb$r_fill_14_.cxb$r_fill_15_.cxb$b_r_dsapQ#define cxb$b_r_ssap cxb$r_dll_overlay.cxb$r_fill_14_.cxb$r_fill_15_.cxb$b_r_ssap"#endif /* #if !defined(__VAXC) */ N#define CXB$S_CXBDEF 152 /* Old size name - synonym */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE  /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __CXBDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************* *******************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */F/* Source: 06-FEB-1997 09:29:18 $1$DGA8345:[LIB_H.SRC]DALDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DALDEF ***/#ifndef __DALDEF_LOADED#define __DALDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DAL - Device Allocation Lock (value block contents) */N/*  */N/* This structure defines the contents of the lock value block for a */N/* device allocation lock. */N/*- */#define DAL$M_NOTFIRST_MNT 0x1#define DAL$M_FOREIGN 0x2#define DAL$M_GROUP 0x4#define DAL$M_SYSTEM 0x8#define DAL$M_WRITE 0x10#define DAL$M_NOQUOTA 0x20#define DAL$M_OVR_PROT 0x40#define DAL$M_OVR_OWNUIC 0x80#define DAL$M_NO INTERLOCK 0x100#define DAL$M_SHADOW_MBR 0x200#define DAL$M_POOL_MBR 0x400#define DAL$S_DALDEF 16 typedef struct _dal { __union {N unsigned short int dal$w_flags; /* Device usage flags: */ __struct {S unsigned dal$v_notfirst_mnt : 1; /* not first time device mounted. */N unsigned dal$v_foreign : 1; /* device mounted /FOREIGN */N unsigned dal$v_group : 1; /* device mounted /GROUP */N  unsigned dal$v_system : 1; /* device mounted /SYSTEM */N unsigned dal$v_write : 1; /* write access allowed */N unsigned dal$v_noquota : 1; /* quota checking disabled */N unsigned dal$v_ovr_prot : 1; /* override protection */N unsigned dal$v_ovr_ownuic : 1; /* override volume ownership */U unsigned dal$v_nointerlock : 1; /* access NOT VAXcluster interlocked */N unsigned dal$v _shadow_mbr : 1; /* shadow set member */R unsigned dal$v_pool_mbr : 1; /* snapshot-capable disk pool member */' unsigned dal$v_fill_2_ : 5; } dal$r_fill_1_; } dal$r_fill_0_;N unsigned short int dal$w_protection; /* Volume protection */N unsigned int dal$l_owner_uic; /* Volume owner UIC */R unsigned short int dal$w_first_mounter_group; /* UIC group of first mounter */N unsigned short int dal $w_fill_1; /* Not used */N unsigned int dal$l_volid; /* Volume identifier hash */ } DAL; #if !defined(__VAXC)-#define dal$w_flags dal$r_fill_0_.dal$w_flagsI#define dal$v_notfirst_mnt dal$r_fill_0_.dal$r_fill_1_.dal$v_notfirst_mnt?#define dal$v_foreign dal$r_fill_0_.dal$r_fill_1_.dal$v_foreign;#define dal$v_group dal$r_fill_0_.dal$r_fill_1_.dal$v_group=#define dal$v_system dal$r_fill_0_.dal$r_fill_1_.dal$v_system;#define dal$v_writ e dal$r_fill_0_.dal$r_fill_1_.dal$v_write?#define dal$v_noquota dal$r_fill_0_.dal$r_fill_1_.dal$v_noquotaA#define dal$v_ovr_prot dal$r_fill_0_.dal$r_fill_1_.dal$v_ovr_protE#define dal$v_ovr_ownuic dal$r_fill_0_.dal$r_fill_1_.dal$v_ovr_ownuicG#define dal$v_nointerlock dal$r_fill_0_.dal$r_fill_1_.dal$v_nointerlockE#define dal$v_shadow_mbr dal$r_fill_0_.dal$r_fill_1_.dal$v_shadow_mbrA#define dal$v_pool_mbr dal$r_fill_0_.dal$r_fill_1_.dal$v_pool_mbr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DALDEF_LOADED */ ww0 [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */F/* Source: 06-MAY-2005 13:11:06 $1$DGA8345:[LIB_H.SRC]DBRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DBRDEF ***/#ifndef __DBRDEF_LOADED#define __DBRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Definitions for Data Breakpoint Registers (DBR)  */N/* */##define DBR$M_MASK 0xFFFFFFFFFFFFFF##define DBR$M_PLM 0xF00000000000000##define DBR$M_IG 0x3000000000000000##define DBR$M_RW 0xC000000000000000"#define DBR$M_W 0x4000000000000000"#define DBR$M_R 0x8000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#end iftypedef struct _dbr {#pragma __nomember_alignment __union {[ unsigned __int64 dbr$q_register; /* Use this for even-numbered DBR registers too */U __struct { /* This defines odd-numbered DBR registers */#if defined(__VAXC)' unsigned dbr$v_mask_1 : 32;' unsigned dbr$v_mask_2 : 24;#elseN unsigned __int64 dbr$v_mask : 56; /* Valid address bits mask */#endifN unsigned dbr$v_plm : 4; /* Privi lege level mask */N unsigned dbr$v_ig : 2; /* Ignored */N unsigned dbr$v_rw : 2; /* Read or write match enable */ } dbr$r_dbrdef_bits;X __struct { /* This defines odd-numbered DBR registers... */#if defined(__VAXC)) unsigned dbr$v_fill_1_1 : 32;) unsigned dbr$v_fill_1_2 : 30;#elsec unsigned __int64 dbr$v_fill_1 : 62; /* ...if we want read an d write as separate bits */#endifN unsigned dbr$v_w : 1; /* Write match enable */N unsigned dbr$v_r : 1; /* Read match enable */! } dbr$r_dbrdef2_bits; } dbr$r_dbr_union; } DBR; #if !defined(__VAXC)5#define dbr$q_register dbr$r_dbr_union.dbr$q_register?#define dbr$v_mask dbr$r_dbr_union.dbr$r_dbrdef_bits.dbr$v_mask=#define dbr$v_plm dbr$r_dbr_union.dbr$r_dbrdef_bits.dbr$v_plm;#define dbr$v_ig dbr $r_dbr_union.dbr$r_dbrdef_bits.dbr$v_ig;#define dbr$v_rw dbr$r_dbr_union.dbr$r_dbrdef_bits.dbr$v_rwD#define dbr$v_fill_1 dbr$r_dbr_union.dbr$r_dbrdef2_bits.dbr$v_fill_1:#define dbr$v_w dbr$r_dbr_union.dbr$r_dbrdef2_bits.dbr$v_w:#define dbr$v_r dbr$r_dbr_union.dbr$r_dbrdef2_bits.dbr$v_r"#endif /* #if !defined(__VAXC) */ N/* */N/* Definitions for Instruction Breakpoint Registers (IBR) */N/*  */##define IBR$M_MASK 0xFFFFFFFFFFFFFF##define IBR$M_PLM 0xF00000000000000##define IBR$M_IG 0x7000000000000000"#define IBR$M_X 0x8000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ibr {#pragma __nomember_alignment __union {[ unsigned __int64  ibr$q_register; /* Use this for even-numbered DBR registers too */U __struct { /* This defines odd-numbered DBR registers */#if defined(__VAXC)' unsigned ibr$v_mask_1 : 32;' unsigned ibr$v_mask_2 : 24;#elseN unsigned __int64 ibr$v_mask : 56; /* Valid address bits mask */#endifN unsigned ibr$v_plm : 4; /* Privilege level mask */N unsigned ibr$v_ig : 3; /* Ignored  */N unsigned ibr$v_x : 1; /* Execute match enable */ } ibr$r_ibrdef_bits; } ibr$r_ibr_union; } IBR; #if !defined(__VAXC)5#define ibr$q_register ibr$r_ibr_union.ibr$q_register?#define ibr$v_mask ibr$r_ibr_union.ibr$r_ibrdef_bits.ibr$v_mask=#define ibr$v_plm ibr$r_ibr_union.ibr$r_ibrdef_bits.ibr$v_plm;#define ibr$v_ig ibr$r_ibr_union.ibr$r_ibrdef_bits.ibr$v_ig9#define ibr$v_x ibr$r_ibr_union.ibr$r_ibrdef_bits.ibr$v_x"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DBRDEF_LOADED */ ww~ [UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */F/* Source: 04-AUG-2020 15:29:12 $1$DGA8345:[LIB_H.SRC]DCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DCBDEF ***/#ifndef __ DCBDEF_LOADED#define __DCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* + */N/* DCB - Data link layer chained buffer descriptor */N/* */N/* This descriptor may be used in one of two ways. The first way is to */N/* use this descriptor to describe a direct I/O transfer. The second */N/* is to use this descriptor to describe a chain of buffers to transmit */N/* or a chain of buffers which have been received. */N/*  */N/* - */#define DCB$M_TYPE_IO 0x1N#define DCB$K_HEADER 48 /* DCB size up to this point */N#define DCB$C_HEADER 48 /* DCB size up to this point */#define DCB$S_DCBDEF 48  9#ifdef __cplusplus /* Define structure prototypes */struct _bufio; #endif /* #ifdef __cplusplus */ typedef struct _dcb {N struct _dcb *dcb$l_flink; /* Forward link */N struct _dcb *dcb$l_blink; /* Backward link */N unsigned short int dcb$w_size; /* Size of block */N unsigned char dcb$b_type; /* Type of block */N unsigned char dcb$b_mode; /* Access mode of agent */N void *dcb$l_link; /* Link to next buffer in chain */N __union { /* Describe I/O  */N unsigned short int dcb$w_sts; /* Old word width STS field */ __union {# unsigned int dcb$l_sts; __struct {Q unsigned dcb$v_type_io : 1; /* If set DIRECT if clear buffered */+ unsigned dcb$v_fill_2_ : 7; } dcb$r_fill_1_; } dcb$r_fill_0_; } dcb$r_sts_overlay; char dcb$b_fill_3_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifO __union { /* X-6, NOSVAPTE_V9.0 Dave Fairbanks */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *dcb$pq_void; /* Untyped 64b pointer */#else unsigned __int6 4 dcb$pq_void;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */T struct _bufio *dcb$pq_bufio_pkt; /* 64-bit pointer to buffered I/O packet */#else# unsigned __int64 dcb$pq_bufio_pkt;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit po inters */#endifN void *dcb$ps_void; /* Untyped 32b pointer */T struct _bufio *dcb$ps_bufio_pkt; /* 32-bit pointer to buffered I/O packet */ } dcb$r_svapte_overlay; __union {N unsigned short int dcb$w_boff; /* Offset to start of data. Data */N unsigned int dcb$l_boff; /* link headers must be back built */ } dcb$r_boff_overlay;N/* from this offset. */Q __union { /* For transmits size in bytes of this */O unsigned short int dcb$w_bcnt; /* segment of the data. For receives */N unsigned int dcb$l_bcnt; /* contains the size of the segment */ } dcb$r_bcnt_overlay;N/* of data contained in this buffer. */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *dcb$pq_svapte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else$ unsigned __int64 dcb$pq_svapte_sva;#endif } DCB; #if !defined(__VAXC)-#define dcb$w_sts dcb$r_sts_overlay.dcb$w_sts;#define dcb$l_sts dcb$r_sts_overlay.dcb$r_fill_0_.dcb$l_stsQ#def ine dcb$v_type_io dcb$r_sts_overlay.dcb$r_fill_0_.dcb$r_fill_1_.dcb$v_type_io4#define dcb$pq_void dcb$r_svapte_overlay.dcb$pq_void>#define dcb$pq_bufio_pkt dcb$r_svapte_overlay.dcb$pq_bufio_pkt4#define dcb$ps_void dcb$r_svapte_overlay.dcb$ps_void>#define dcb$ps_bufio_pkt dcb$r_svapte_overlay.dcb$ps_bufio_pkt0#define dcb$w_boff dcb$r_boff_overlay.dcb$w_boff0#define dcb$l_boff dcb$r_boff_overlay.dcb$l_boff0#define dcb$w_bcnt dcb$r_bcnt_overlay.dcb$w_bcnt0#define dcb$l_bcnt dcb$r_bcnt_overlay.dc b$l_bcnt"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DCBDEF_LOADED */ wwХ [UM/***************************************************************************/M/**   **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**   **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** ** /M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:18 by OpenVMS SDL V3.7 */G/* Source: 24-JUL-2023 11:46:15 $1$DGA8345:[LIB_H.SRC]DCBEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DCBEDEF  ***/#ifndef __DCBEDEF_LOADED#define __DCBEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DCBE - Data Chain Block */N/* */N/* The DCBE is the data structure used to chain data packets together. A */N/* chain may consist of on buffer or may buffers each pointed to by a DCBE. */N/* the format of the DCBE is the same as a VCRP data request, so that a */N/* VCRP may be the first DCBE in the chain, and describe the entire */N/* data request.  */N/* */O/* THE FORMAT OF THIS PACKET SHOULD NOT CHANGE WITHOUT CORRESPONDING CHANGES */N/* BEING MAY TO A VCRP DATA REQUEST PACKET. */N/*- */N#define DCBE$G_SCRATCH 40 /* Start of DCBE scratch area */N#define DCBE$S_SCRATCH 4 /* Length of scratch area */#define DCBE$M_CMN_LOCKED 0x1#define DCBE$M_CMN_RETBUF 0x2#define DCBE$M_CMN_CACHE 0x4U#define DCBE$S_DCB_HEADER_PE 104 /* Length of PEDRIVER-specific DCBE header */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _dcbe {#pragma __nomember_alignmentN struct _dcbe *dcbe$l_flink; /* Forward Queue link */N struct _dcbe *dcbe$l_blink; /* Backward Queue link */N unsigned short int dcbe$w_size; /* Size of structure */N unsigned char dcbe$b_type; /* Type of structure - DYN$C_NET */R unsigned char dcbe$b_sub_type; /* Subtype of structure - DYN$C_VCI_DCB */N int dcbe$l_reserved [13]; /* Reserved to ensure that VCRP and */N/* DCB look the same up to DCB_HEADER */\/* The DCBE scratch area is 4 bytes long, overlaying the spare longword at VCRP$L_FILLER2 */R/* which is the 7th longword of this reserved area, so 24 bytes back from here. */ __union {\ unsigned short int dcbe$w_common_flags; /* Common flags used by all users of DCBs */ __struct {` unsigned dcbe$v_cmn_locked : 1; /* Indicates buffer is locked down for direct I/O */f unsigned dcbe$v_cmn_retbuf : 1; /* Indicates buffer must be return to owner immediatel y */[ unsigned dcbe$v_cmn_cache : 1; /* Indicates buffer came from creator's cache */( unsigned dcbe$v_fill_0_ : 5;& } dcbe$r_common_flags_bit;& } dcbe$r_common_flags_overlay;N unsigned char dcbe$b_flags; /* User controlled DCB flags */N unsigned char dcbe$b_mode; /* */S void *dcbe$a_dealloc_rtn; /* Address of routine to deallocate VCRP */c#if !defined(__NOBASEALIGN_SUPPORT) & & !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Z void *dcbe$pq_buffer_addr64; /* 64-bit buffer address (upper-level VCM only) */#else( unsigned __int64 dcbe$pq_buffer_addr64;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifV void *dcbe$l_buffer_address; /* VM Address of buffer specified in SVAPTE */N void *dcbe$a_dcb_link; /* Address of next DCB in chain */O unsigned int dcbe$l_boff; /* Offset to start of data in buffer */N unsigned int dcbe$l_bcnt; /* Byte count of data in buf fer */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Q void *dcbe$pq_svapte_sva; /* Address of list of extents (EXT_PQ) */#else% unsigned __int64 dcbe$pq_svapte_sva;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignme nt#endif# __int64 dcbe$q_fill_diobm [11]; } DCBE; #if !defined(__VAXC)K#define dcbe$w_common_flags dcbe$r_common_flags_overlay.dcbe$w_common_flags_#define dcbe$v_cmn_locked dcbe$r_common_flags_overlay.dcbe$r_common_flags_bit.dcbe$v_cmn_locked_#define dcbe$v_cmn_retbuf dcbe$r_common_flags_overlay.dcbe$r_common_flags_bit.dcbe$v_cmn_retbuf]#define dcbe$v_cmn_cache dcbe$r_common_flags_overlay.dcbe$r_common_flags_bit.dcbe$v_cmn_cache"#endif /* #if !defined(__VAXC) */ N#define DCBE$K_DCB_HEADER 192 /* Length of DCB header */#define DCBE$S_DCBEDEF 192 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DCBEDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */H/* Source: 10-AUG-2000 09:27:58 $1$DGA8345:[LIB_H.SRC]DCPIDMSG.SDL;1 *//************************************************************************************************* *******************************//*** MODULE $DCPIDMSG ***/#ifndef __DCPIDMSG_LOADED#define __DCPIDMSG_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif   9#ifdef __cplusplus /*  Define structure prototypes */ struct _kfe; struct _imcb;struct _ldrimg; #endif /* #ifdef __cplusplus */ typedef struct _dcpid_msg {N unsigned short int dcpi$w_type; /* message type */N unsigned short int dcpi$w_reserved; /* reserved - unused */N unsigned int dcpi$l_pid; /* process id */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __requir ed_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _kfe *dcpi$pq_kfe_ptr; /* address of KFE */#else" unsigned __int64 dcpi$pq_kfe_ptr;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _imcb *dcpi$pq_imcb_ptr; /* address of IMCB */#else# unsigned __int64 dcpi$pq_imcb_ptr!;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _ldrimg *dcpi$pq_ldrimp_ptr; /* address of LDRIMG */#else% unsigned __int64 dcpi$pq_ldrimp_ptr;#endif$ } dcpi$r_struct_ptr_overlay; } DCPID_MSG; #if !defined(__VAXC)A#define dcpi$pq_kfe_ptr dcpi$r_struct_ptr_overlay.dcpi$pq_kfe_ptrC#define dcpi$pq_imcb_ptr dcpi$r_ "struct_ptr_overlay.dcpi$pq_imcb_ptrG#define dcpi$pq_ldrimp_ptr dcpi$r_struct_ptr_overlay.dcpi$pq_ldrimp_ptr"#endif /* #if !defined(__VAXC) */ N#define DCPI$C_LENGTH 16 /* length of DCPID_MSG */N#define DCPI$K_LENGTH 16 /* length of DCPID_MSG */N#define DCPI$C_PROC_SCAN 1 /* process scan message type */N#define DCPI$C_PROC_RUNDOWN 2 /* process rundown message type */S#define DCPI$C_PROC_IMGACT 3 # /* process image activation message type */N#define DCPI$C_SYS_INSTALL 4 /* system install message type */N#define DCPI$C_SYS_DEINSTALL 5 /* system uninstall message type */N#define DCPI$C_SYS_LOAD 6 /* system load message type */N#define DCPI$C_SYS_UNLOAD 7 /* system unload message type */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma $__required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DCPIDMSG_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Dev%elopment, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not & **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************************* '*******************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */F/* Source: 06-FEB-2002 10:11:28 $1$DGA8345:[LIB_H.SRC]DCRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DCRDEF ***/#ifndef __DCRDEF_LOADED#define __DCRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __(nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !d)efined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Definitions for Default Control Register (DCR - CR0) */N/* */#define DCR$M_PP 0x1#define DCR$M_BE* 0x2#define DCR$M_IC 0x4#define DCR$M_MBZ0 0xF8#define DCR$M_DM 0x100#define DCR$M_DP 0x200#define DCR$M_DK 0x400#define DCR$M_DX 0x800#define DCR$M_DR 0x1000#define DCR$M_DA 0x2000#define DCR$M_DD 0x4000N#define DCR$M_DEFER_ALL 32512 /* Defer all faults */#define DCR$M_MBZ1 0xFFFF8000%#define DCR$M_MBZ2 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_a +lignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _dcr {#pragma __nomember_alignment __union {/ unsigned __int64 dcr$q_default_control; __struct {T unsigned dcr$v_pp : 1; /* Privileged Performance monitor default */N unsigned dcr$v_be : 1; /* Big-Endian default */N unsigned dcr$v_ic : 1; /* IA-32 Lock Check enable */N unsigned dcr$v_mbz0 : 5; /* Reserve,d DCR{7:3} (MBZ) */N unsigned dcr$v_dm : 1; /* Defer TLB Miss faults only */O unsigned dcr$v_dp : 1; /* Defer Page no Present faults only */N unsigned dcr$v_dk : 1; /* Defer Key Miss faults only */N unsigned dcr$v_dx : 1; /* Defer Key Permission faults only */N unsigned dcr$v_dr : 1; /* Defer Access Rights faults only */N unsigned dcr$v_da : 1; /* Defer Access Bit faults only - */N unsigned dcr$v_dd : 1; /* Defer Debug faults */N unsigned dcr$v_mbz1 : 17; /* Reserved DCR{31:15} */N unsigned dcr$v_mbz2 : 32; /* Reserved DCR{63:32} */ } dcr$r_dcrdef_bits; } dcr$r_dcr_union; } DCR; #if !defined(__VAXC)C#define dcr$q_default_control dcr$r_dcr_union.dcr$q_default_control;#define dcr$v_pp dcr$r_dcr_union.dcr$r_dcrdef_bits.dcr$v_pp;#define dcr$v_be dcr$r_dcr_u .nion.dcr$r_dcrdef_bits.dcr$v_be;#define dcr$v_ic dcr$r_dcr_union.dcr$r_dcrdef_bits.dcr$v_ic?#define dcr$v_mbz0 dcr$r_dcr_union.dcr$r_dcrdef_bits.dcr$v_mbz0;#define dcr$v_dm dcr$r_dcr_union.dcr$r_dcrdef_bits.dcr$v_dm;#define dcr$v_dp dcr$r_dcr_union.dcr$r_dcrdef_bits.dcr$v_dp;#define dcr$v_dk dcr$r_dcr_union.dcr$r_dcrdef_bits.dcr$v_dk;#define dcr$v_dx dcr$r_dcr_union.dcr$r_dcrdef_bits.dcr$v_dx;#define dcr$v_dr dcr$r_dcr_union.dcr$r_dcrdef_bits.dcr$v_dr;#define dcr$v_da dcr$r_dcr_union.d /cr$r_dcrdef_bits.dcr$v_da;#define dcr$v_dd dcr$r_dcr_union.dcr$r_dcrdef_bits.dcr$v_dd?#define dcr$v_mbz1 dcr$r_dcr_union.dcr$r_dcrdef_bits.dcr$v_mbz1?#define dcr$v_mbz2 dcr$r_dcr_union.dcr$r_dcrdef_bits.dcr$v_mbz2"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Dtypedef struct _dcr * DCR_PQ; /* Pointer to a DCR structur 0e. */Qtypedef struct _dcr ** DCR_PPQ; /* Pointer to a pointer to a DCR structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 DCR_PQ;!typedef unsigned __int64 DCR_PPQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required1 ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DCRDEF_LOADED */ ww i [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR discl2osed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without 3 **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SD 4L V3.7 */F/* Source: 03-MAR-2005 16:07:07 $1$DGA8345:[LIB_H.SRC]DDBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DDBDEF ***/#ifndef __DDBDEF_LOADED#define __DDBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr siz5e pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struc6t#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DDB - DEVICE DATA BLOCK */N/* */N/* THERE IS ONE DEVICE DATA BLOCK FOR EACH CONTROLLER IN A SYSTEM. */N/*+ 7 */ #define DDB$M_NO_TIMEOUT 0x1#define DDB$M_PAC 0x2N#define DDB$K_PACK 1 /*LARGE DISK PACKS */N#define DDB$K_CART 2 /*DISK CARTRIDGES */O#define DDB$K_SLOW 3 /*SLOW (CHEAP) DISKS (E.G., FLOPPY) */P#define DDB$K_TAPE 4 /*BLOCK STRUCTURED TAPE (E.G., TU58) */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; 8struct _ddt; struct _dpt; struct _sb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ddb {#pragma __nomember_alignment __union {R int ddb$l_link; /*ADDRESS OF NEXT DDB IN LIST (0=LAST) */ __struct {R struct _ddb *ddb$ps_link; /*ADDRESS OF NEXT DD 9B IN LIST (0=LAST) */ } ddb$r_fill_1_; } ddb$r_fill_0_; __union {O int ddb$l_ucb; /*ADDRESS OF FIRST UCB FOR THIS DDB */ __struct {O struct _ucb *ddb$ps_ucb; /*ADDRESS OF FIRST UCB FOR THIS DDB */ } ddb$r_fill_3_; } ddb$r_fill_2_; __union {N unsigned short int ddb$w_size; /*SIZE OF DDB IN BYTES */ __struct {N unsigned short int ddb$iw_size; /*SIZE : OF DDB IN BYTES */ } ddb$r_fill_5_; } ddb$r_fill_4_; __union {N unsigned char ddb$b_type; /*TYPE OF DATA STRUCTURE FOR DDB */ __struct {N unsigned char ddb$ib_type; /*TYPE OF DATA STRUCTURE FOR DDB */ } ddb$r_fill_7_; } ddb$r_fill_6_;N __union { /* Flags */" unsigned char ddb$b_flags; __struct {N unsigned ddb$v_n ;o_timeout : 1; /* No TIMEOUT handling */N unsigned ddb$v_pac : 1; /* Using port allocation class */( unsigned ddb$v_fill_22_ : 6; } ddb$r_flags_bits; } ddb$r_flags_overlay; __union {R int ddb$l_ddt; /*ADDRESS OF THE DRIVER DISPATCH TABLE */ __struct {R struct _ddt *ddb$ps_ddt; /*ADDRESS OF THE DRIVER DISPATCH TABLE */ } ddb$r_fill_9_; } ddb$r_fill_8_; <__union {Q unsigned int ddb$l_acpd; /*NAME OF DEFAULT ACP FOR DEVICE UNITS */Q unsigned int ddb$il_acpd; /*NAME OF DEFAULT ACP FOR DEVICE UNITS */ __struct {% char ddbdef$$_fill_4 [3]; __union {N unsigned char ddb$b_acpclass; /*CLASS CODE OF DEFAULT ACP */ __struct {R unsigned char ddb$ib_acpclass; /*CLASS CODE OF DEFAULT ACP */% } ddb$r_fill_11_;! = } ddb$r_fill_10_; } ddb$r_acpd_fields; } ddb$r_acpd_union; __union {N char ddb$t_name [16]; /*GENERIC PATH NAME OF DEVICE */ __struct { __union {H unsigned char ddb$b_name_len; /* CHARACTER COUNT */ __struct {M unsigned char ddb$ib_name_len; /* CHARACTER COUNT */% } ddb$r_fill_13_;! } ddb$r_fill_12_;J > char ddb$t_name_str [15]; /* CHARACTER STRING */ } ddb$r_name_ascic; } ddb$r_name_overlay;N struct _dpt *ddb$ps_dpt; /*ADDR OF DRIVER DPT */N struct _ddb *ddb$ps_drvlink; /*ADDR OF NEXT DDB FOR THIS DRIVER */ __union {N int ddb$l_sb; /*ADDR OF SYSTEMBLOCK */ __struct {N struct _sb *ddb$ps_sb; /*ADDR OF SYSTEMBLOCK */ } dd ?b$r_fill_15_; } ddb$r_fill_14_; __union {N int ddb$l_conlink; /*NEXT DDB IN CONNECTION SUB-CHAIN */ __struct {N struct _ddb *ddb$ps_conlink; /*NEXT DDB IN CONNECTION SUB-CHAIN */ } ddb$r_fill_17_; } ddb$r_fill_16_; __union {N unsigned int ddb$l_allocls; /*DEVICE ALLOCATION CLASS */ __struct {N unsigned int ddb$il_allocls; /*DEVICE ALLOCATION CLASS */ @ } ddb$r_fill_19_; } ddb$r_fill_18_; __union {S struct _ucb *ddb$l_2p_ucb; /*ADDRESS OF FIRST UCB ON SECONDARY PATH */S struct _ucb *ddb$ps_2p_ucb; /*ADDRESS OF FIRST UCB ON SECONDARY PATH */N struct _ucb *ddb$l_dp_ucb; /*OLD STYLE SYNONYM FOR ABOVE */ } ddb$r_union_2p_ucb; __union {N unsigned int ddb$l_port_id; /* Reserved */ __struct {N char ddb$t_port_id [1] A; /* Reserved */ } ddb$r_fill_21_; } ddb$r_fill_20_;N unsigned int ddb$l_class_lkid; /* Reserved */N void *ddb$ps_2p_ddb; /* Reserved */N unsigned int ddb$l_seed_unit; /* Seed unit */N struct _ucb *ddb$l_seed_ptr; /* Seed pointer */N int ddb$l_spare_1 [8]; /* Reserved */ B } DDB; #if !defined(__VAXC)+#define ddb$l_link ddb$r_fill_0_.ddb$l_link;#define ddb$ps_link ddb$r_fill_0_.ddb$r_fill_1_.ddb$ps_link)#define ddb$l_ucb ddb$r_fill_2_.ddb$l_ucb9#define ddb$ps_ucb ddb$r_fill_2_.ddb$r_fill_3_.ddb$ps_ucb+#define ddb$w_size ddb$r_fill_4_.ddb$w_size;#define ddb$iw_size ddb$r_fill_4_.ddb$r_fill_5_.ddb$iw_size+#define ddb$b_type ddb$r_fill_6_.ddb$b_type;#define ddb$ib_type ddb$r_fill_6_.ddb$r_fill_7_.ddb$ib_type3#define ddb$b_flags ddb$r_flags_overlay. Cddb$b_flagsN#define ddb$v_no_timeout ddb$r_flags_overlay.ddb$r_flags_bits.ddb$v_no_timeout@#define ddb$v_pac ddb$r_flags_overlay.ddb$r_flags_bits.ddb$v_pac)#define ddb$l_ddt ddb$r_fill_8_.ddb$l_ddt9#define ddb$ps_ddt ddb$r_fill_8_.ddb$r_fill_9_.ddb$ps_ddt.#define ddb$l_acpd ddb$r_acpd_union.ddb$l_acpd0#define ddb$il_acpd ddb$r_acpd_union.ddb$il_acpdW#define ddb$b_acpclass ddb$r_acpd_union.ddb$r_acpd_fields.ddb$r_fill_10_.ddb$b_acpclassh#define ddb$ib_acpclass ddb$r_acpd_union.ddb$r_acpd_fiDelds.ddb$r_fill_10_.ddb$r_fill_11_.ddb$ib_acpclass0#define ddb$t_name ddb$r_name_overlay.ddb$t_nameX#define ddb$b_name_len ddb$r_name_overlay.ddb$r_name_ascic.ddb$r_fill_12_.ddb$b_name_leni#define ddb$ib_name_len ddb$r_name_overlay.ddb$r_name_ascic.ddb$r_fill_12_.ddb$r_fill_13_.ddb$ib_name_lenI#define ddb$t_name_str ddb$r_name_overlay.ddb$r_name_ascic.ddb$t_name_str(#define ddb$l_sb ddb$r_fill_14_.ddb$l_sb9#define ddb$ps_sb ddb$r_fill_14_.ddb$r_fill_15_.ddb$ps_sb2#define ddb$l_conlink ddb$r_ Efill_16_.ddb$l_conlinkC#define ddb$ps_conlink ddb$r_fill_16_.ddb$r_fill_17_.ddb$ps_conlink2#define ddb$l_allocls ddb$r_fill_18_.ddb$l_alloclsC#define ddb$il_allocls ddb$r_fill_18_.ddb$r_fill_19_.ddb$il_allocls4#define ddb$l_2p_ucb ddb$r_union_2p_ucb.ddb$l_2p_ucb6#define ddb$ps_2p_ucb ddb$r_union_2p_ucb.ddb$ps_2p_ucb4#define ddb$l_dp_ucb ddb$r_union_2p_ucb.ddb$l_dp_ucb2#define ddb$l_port_id ddb$r_fill_20_.ddb$l_port_idA#define ddb$t_port_id ddb$r_fill_20_.ddb$r_fill_21_.ddb$t_port_id"#endif F /* #if !defined(__VAXC) */ N#define DDB$K_LENGTH 112 /*LENGTH OF STANDARD DDB */N#define DDB$C_LENGTH 112 /*LENGTH OF STANDARD DDB */N#define DDB$S_DDBDEF 112 /*OLD DDB SIZE FOR COMPATIBILITY */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endifG#ifdef __cplusplus }#endif#pragma __standard #endif /* __DDBDEF_LOADED */ ww0 [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone withoHut the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prioIr written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */F/* J Source: 02-APR-2003 12:24:36 $1$DGA8345:[LIB_H.SRC]DDTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DDTDEF ***/#ifndef __DDTDEF_LOADED#define __DDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported K*/\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endifL #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DDT - DRIVER DISPATCH TABLE */N/* */N/* EACH DEVICE DRIVER HAS A DRIVER DISPATCH TABLE. */N/*- M */ e#define DDT$M_DIAGBUF64 32768 /*Use 64-bit BUFIO for diag buffer if set in DDT$W_DIAGBUF */N#define DDT$K_ITCLVL_DRVR 0 /* "Native" Driver */N#define DDT$K_ITCLVL_MPDEV 4096 /* Multipath */N#define DDT$K_ITCLVL_HSM 24576 /* Hierarchical Storage Manager */N#define DDT$K_ITCLVL_TOP 32767 /* Top, with intercepts in place */N#define DDT$K_LENGTH_MIN 120 /*Minimum DDT leNngth since V7.0 */  9#ifdef __cplusplus /* Define structure prototypes */ struct _fdt; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ddt {#pragma __nomember_alignmentN struct _ddt *ddt$ps_next_intercept_ddt; /*Pointer to next intercept DDT */ int ddt$l_reserved_lw2; __un Oion {N unsigned short int ddt$w_size; /*Structure size */ __struct {N unsigned short int ddt$iw_size; /*Structure size */ } ddt$r_fill_1_; } ddt$r_fill_0_;S unsigned char ddt$b_type; /* Nonpaged pool packet type, DYN$C_MISC */[ unsigned char ddt$b_subtype; /* Nonpaged pool packet subtype, DYN$C_DDT */ __union {_ unsigned short int ddt$w_diagbuf; /*Size of diagnostic b Puffer in bytes (low 15-bits) */ __struct {d unsigned short int ddt$iw_diagbuf; /*Size of diagnostic buffer in bytes (low 15-bits) */ } ddt$r_fill_3_; } ddt$r_fill_2_; __union {R unsigned short int ddt$w_errorbuf; /*SIZE OF ERROR LOG BUFFER IN BYTES */ __struct {W unsigned short int ddt$iw_errorbuf; /*SIZE OF ERROR LOG BUFFER IN BYTES */ } ddt$r_fill_5_; } ddt$r_fill_4_; __union {N Qunsigned short int ddt$w_fdtsize; /*SIZE OF FDT IN BYTES */ __struct {N unsigned short int ddt$iw_fdtsize; /*SIZE OF FDT IN BYTES */ } ddt$r_fill_7_; } ddt$r_fill_6_;N short int ddt$w_intercept_level; /*Intercept level */N void (*ddt$ps_start_2)(); /*STEP 2 DRIVER START I/O ROUTINE */Q void (*ddt$ps_start_jsb)(); /*STEP 2 DRIVER JSB_START I/O ROUTINE */U int (*ddt$ps_ctrlinit_2)(); R /*STEP 2 CONTROLLER INITIALIZATION ROUTINE */O int (*ddt$ps_unitinit_2)(); /*STEP 2 UNIT INITIALIZATION ROUTINE */N int (*ddt$ps_cloneducb_2)(); /*STEP 2 CLONED UCB ROUTINE */S struct _fdt *ddt$ps_fdt_2; /*ADDR OF STEP 2 FUNCTION DECISION TABLE */N void (*ddt$ps_cancel_2)(); /*STEP 2 CANCEL I/O ROUTINE */P void (*ddt$ps_regdump_2)(); /*STEP 2 DEVICE REGISTER DUMP ROUTINE */O void (*ddt$ps_altstart_2)(); S/*STEP 2 ALTERNATE START I/O ROUTINE */S void (*ddt$ps_altstart_jsb)(); /*STEP 2 JSB ALTERNATE START I/O ROUTINE */N void (*ddt$ps_mntver_2)(); /*STEP 2 MOUNT VERIFICATION ROUTINE */ __union {X int ddt$l_mntv_sssc; /*ADDRESS OF SHADOW SET STATE CHANGE MV ENTRY */ __struct {X int (*ddt$ps_mntv_sssc)(); /*ADDRESS OF SHADOW SET STATE CHANGE MV ENTRY */ } ddt$r_fill_9_; } ddt$r_fill_8_; __union {O Tint ddt$l_mntv_for; /*ADDRESS OF FOREIGN DEVICE MV ENTRY */ __struct {O int (*ddt$ps_mntv_for)(); /*ADDRESS OF FOREIGN DEVICE MV ENTRY */ } ddt$r_fill_11_; } ddt$r_fill_10_; __union {R int ddt$l_mntv_sqd; /*ADDRESS OF SEQUENTIAL DEVICE MV ENTRY */ __struct {R int (*ddt$ps_mntv_sqd)(); /*ADDRESS OF SEQUENTIAL DEVICE MV ENTRY */ } ddt$r_fill_13_; } ddt$r_fill_12_; U __union {N int ddt$l_aux_storage; /*ADDRESS OF AUXILIARY STORAGE AREA */ __struct {N void *ddt$ps_aux_storage; /*ADDRESS OF AUXILIARY STORAGE AREA */ } ddt$r_fill_15_; } ddt$r_fill_14_; __union {N int ddt$l_aux_routine; /*ADDRESS OF AUXILIARY ROUTINE */ __struct {N int (*ddt$ps_aux_routine)(); /*ADDRESS OF AUXILIARY ROUTINE */ } ddt$r_fill_17_; } ddt$r_fillV_16_;P void (*ddt$ps_channel_assign_2)(); /*STEP 2 ROUTINE TO CALL FROM $ASSIGN */P int (*ddt$ps_cancel_selective_2)(); /*STEP 2 SELECTIVE CANCEL I/O ROUTINE */N unsigned int ddt$is_stack_bcnt; /*BYTES OF KP STACK REQUIRED */N unsigned int ddt$is_reg_mask; /*KP REGISTER SAVE MASK */X void (*ddt$ps_kp_startio)(); /*ADDRESS OF KERNEL PROCESS START I/O ROUTINE */N int (*ddt$ps_csr_mapping)(); /*ADDRESS OF CSR MAPPING ROUTINE */Q Wint (*ddt$ps_fast_fdt)(); /* Address of Fast-IO fast-FDT routine */N int (*ddt$ps_pending_io)(); /*Address of Pending I/O routine */N void *ddt$ps_customer; /*Reserved_to_customer pointer */R int (*ddt$ps_make_devpath)(); /*Address of create path infor. routine */N int (*ddt$ps_setprfpath)(); /* Address of fastpath FDT routine */P int (*ddt$ps_change_preferred)(); /* Address of fastpath upcall routine */N unsigned int ddtX$l_mpdev_spare_1; /* Old QIOserver cell */N unsigned int ddt$l_mpdev_spare_2; /* Old QIOserver cell */` __union { /* USB entry point overlays AMDS registration routine */] int (*ddt$ps_mgt_register)(); /* Address of RMdriver Object registration routine */N int (*ddt$ps_configure)(); /* Address of USB configure routine */ } ddt$r_config_overlay;b __union { /* USB entry point Y overlays AMDS deregistration routine */_ int (*ddt$ps_mgt_deregister)(); /* Address of RMdriver Object deregistration routine */P int (*ddt$ps_deconfigure)(); /* Address of USB deconfigure routine */! } ddt$r_deconfig_overlay;Q int (*ddt$ps_mpdev_path_swtch)(); /* Address of mpdev_path_swtch routine */ } DDT; #if !defined(__VAXC)+#define ddt$w_size ddt$r_fill_0_.ddt$w_size;#define ddt$iw_size ddt$r_fill_0_.ddt$r_fill_1_.ddt$iw_size1#define ddt$w_diag Zbuf ddt$r_fill_2_.ddt$w_diagbufA#define ddt$iw_diagbuf ddt$r_fill_2_.ddt$r_fill_3_.ddt$iw_diagbuf3#define ddt$w_errorbuf ddt$r_fill_4_.ddt$w_errorbufC#define ddt$iw_errorbuf ddt$r_fill_4_.ddt$r_fill_5_.ddt$iw_errorbuf1#define ddt$w_fdtsize ddt$r_fill_6_.ddt$w_fdtsizeA#define ddt$iw_fdtsize ddt$r_fill_6_.ddt$r_fill_7_.ddt$iw_fdtsize5#define ddt$l_mntv_sssc ddt$r_fill_8_.ddt$l_mntv_ssscE#define ddt$ps_mntv_sssc ddt$r_fill_8_.ddt$r_fill_9_.ddt$ps_mntv_sssc4#define ddt$l_mntv_for ddt$r_fil [l_10_.ddt$l_mntv_forE#define ddt$ps_mntv_for ddt$r_fill_10_.ddt$r_fill_11_.ddt$ps_mntv_for4#define ddt$l_mntv_sqd ddt$r_fill_12_.ddt$l_mntv_sqdE#define ddt$ps_mntv_sqd ddt$r_fill_12_.ddt$r_fill_13_.ddt$ps_mntv_sqd:#define ddt$l_aux_storage ddt$r_fill_14_.ddt$l_aux_storageK#define ddt$ps_aux_storage ddt$r_fill_14_.ddt$r_fill_15_.ddt$ps_aux_storage:#define ddt$l_aux_routine ddt$r_fill_16_.ddt$l_aux_routineK#define ddt$ps_aux_routine ddt$r_fill_16_.ddt$r_fill_17_.ddt$ps_aux_routineD#define dd \t$ps_mgt_register ddt$r_config_overlay.ddt$ps_mgt_register>#define ddt$ps_configure ddt$r_config_overlay.ddt$ps_configureJ#define ddt$ps_mgt_deregister ddt$r_deconfig_overlay.ddt$ps_mgt_deregisterD#define ddt$ps_deconfigure ddt$r_deconfig_overlay.ddt$ps_deconfigure"#endif /* #if !defined(__VAXC) */ N#define DDT$K_LENGTH 152 /*LENGTH OF DDT */N#define DDT$C_LENGTH 152 /*LENGTH OF DDT */R#define DDT$S_DDTDEF 152 ] /*OLD DDT LENGTH NAME FOR COMPATIBILITY */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DDTDEF_LOADED */ wwP [UM/***************************************************************************/M/** ^ **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** _ **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/`M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */F/* Source: 22-APR-1993 10:49:45 $1$DGA8345:[LIB_H.SRC]DEADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DEADEF ***/ a#ifndef __DEADEF_LOADED#define __DEADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus b extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Define the layocut of the Deaccess Audit Pending block. This record is */N/* used to store the information necessary to write a deaccess audit event */N/* upon object deaccess. These records are queued off a per-process queue */N/* (NSA$GQ_DEACCESS_AUDIT) and managed by NSA$QUEUE_DEACCESS_AUDIT, */N/* NSA$DEACCESS_AUDIT, and $DELPRC. */N/* */#define DEA$K_LENGTH 48N/* Define flags us ded by the NSA$DEACCESS_AUDIT routine. */N#define DEA$K_FLUSH_ALL 1 /* flush all DEAs */N#define DEA$K_FLUSH_BY_OCB 2 /* flush all DEAs by object class */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ocb; #endif /* #ifdef __cplusplus */ typedef struct _dea {N struct _dea *dea$l_flink; /* FLINK */N struct _dea *dea$l_blink; /* BLINK e */N unsigned int dea$l_size; /* size of DEA record */N unsigned int dea$l_type; /* type of structure (DYN$C_DEA) */N unsigned int dea$l_flags; /* flags (unused) */N unsigned int dea$l_deaccess_key; /* deaccess audit key */N unsigned int dea$l_audit_mask; /* alarm/audit mask */N struct _ocb *dea$l_ocb; /* OCB address */N un fsigned int dea$l_alarm_size; /* size of alarm string */N unsigned int dea$l_audit_size; /* size of audit string */N void *dea$l_alarm; /* alarm string address */N void *dea$l_audit; /* audit string address */ } DEA; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restoreg the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DEADEF_LOADED */ wwp, [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorizedh to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated ori disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7 j-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */M/* Source: 06-MAY-2003 07:55:07 $1$DGA8345:[LIB_H.SRC]DEVCFG_CBKDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DEVCFG_CBKDEF ***/#ifndef __DEVCFG_CBKDEF_LOADED #define __DEVCFG_CBKDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentRk#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#defline __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DEVCFG_CBK - Devconfig call back */N/* */O/* The routines ioc_std$devconfig_register and ioc_std$devmconfig_deregister */N/* maintain a singly-linked list of device configure call back structure */N/* (DEVCFG_CBK structures). */O/* A new entry is added by a successful call to the registration routine and */O/* an existing entry can be removed by calling the deregistration routine. */N/* The registration routine would minimally specify a device class */N/* and a callback routine address. Subsequently, when a new device */ nN/* is configured of that class, the specified callback routine would be */N/* called. */N/* The head of the list is stored at IOC$GL_DEVCFG_CBK. */N/*- */   9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus o) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _devcfg_cbk {#pragma __nomember_alignmentN struct _devcfg_cbk *devcfg_cbk$ps_flink; /* Forward pointer */N unsigned int devcfg_cbk$l_reserved1; /* Reserved longword */N unsigned short int devcfg_cbk$w_size; /* Structure size */N unsigned char devcfg_cbk$b_type; /* Structure type, DYN$C_MISC p*/Q unsigned char devcfg_cbk$b_subtype; /* Structure subtype, DYN$C_DEVCFG_CBK */[ unsigned int devcfg_cbk$l_flags; /* Validated flag specified in registration call */N/* may contain another flag in the future */Y unsigned int devcfg_cbk$l_devclass; /* Device class specified in registration call */N void (*devcfg_cbk$ps_devconfigured)(); /* Callback routine specified */N/* in registration call q */\ unsigned __int64 devcfg_cbk$q_user_param; /* Parameter specified in registration call */a unsigned int devcfg_cbk$l_num_calls; /* Number of times this call back invoked (diagnosis) */g struct _ucb *devcfg_cbk$ps_last_ucb; /* Last UCB address for which call back invoked (diagnosis) */ } DEVCFG_CBK;N#define DEVCFG_CBK$K_LENGTH 40 /* Size of fixed size DEVCFG_CBK */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptrr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard ##endif /* __DEVCFG_CBKDEF_LOADED */ wwS [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** slicensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licentsed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************* u*************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */G/* Source: 02-SEP-1989 10:38:13 $1$DGA8345:[LIB_H.SRC]DIAGDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DIAGDEF ***/#ifndef __DIAGDEF_LOADED#define __DIAGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!v#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_parwams ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/** */N/* */N/* Constants defining literals used in $DIAGNOSE system service x */N/* */T#define DIAG$C_SETAFF 1 /* request to set affinity -- Set/Release */N/* explicit process affinity to any CPU. */P#define DIAG$C_ACTVCPUS 2 /* request to read SMP$GL_ACTIVE_CPUS */P#define DIAG$C_DISABLAFF 0 /* disable explicit affinity to a CPU */O#define DIAG$C_ENABLAFF 1 /* enable explicit affinity to a CPU */ $#pyragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DIAGDEF_LOADED */ ww [UM/***************************************************************************/M/** **/zM/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. C{ONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************************|**************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */G/* Source: 18-JUN-2005 15:16:57 $1$DGA8345:[LIB_H.SRC]DIDTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE didtdef ***/#ifndef __DIDTDEF_LOADED#define __DIDTDEF_LOAD}ED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#def~ine __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define DIDT$K_SPURIOUS_IRQ 15#define DIDT$K_MAX_ENTRIES 256#define DIDT$K_MIN_DEV_VEC 32#define DIDT$K_MAX_DEV_VEC 223N/* Historically, the first quad in an SCB entry was a pointer to the entry */N/* point of IOC$INTDISP() in [SYS]IOCINDISP.MAR. The second quad consisted */N/* of a 32-bit pointer to a VEC struct in the low longword and the SCB */N/* offset in the high longword. In the Alpha, PAL code would jump to the */P/* entry point stored int the first quadword, IOC$INTDISP(), and that routine */O/* would unpackage the VEC structure to get the procedure descriptor for the */N/* ISR of the interrupts.  */N/* */N/* For IA64, though we retain the historical names of these fields, the */N/* first quadword is vacant. The second quadword still has the VEC in the */N/* low longword and the SCB vector in the high longword. */N/* */R/* In IA64, the irq$$dispatcher() routine called by SWIS when there is a device */P/* interrupt will unpackage the VEC structure to find the function descriptor */O/* of the ISR for the interrupting device. It will then call the ISR through */N/* its function descriptor. */N/* */N/* */#define DIDT$K_SIZE 16 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endiftypedef struct _didt {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 didt$q_isr; /* historical SCB name of this quad */c#if !defined(__NOBASEALIGN_SUPPORT ) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __struct {#pragma __nomember_alignmentN int didt$l_crb_sqfl; /* Shr Intr queue FLINK */N int didt$l_crb_sqbl; /* Shr Intr queue BLINK */ } didt$r_qhdr; } didt$r_qw0;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 didt$q_arg; /* historical SCB name of this quad */ __struct {N int didt$l_vec; /* must be cast as (VEC*) in C */N int didt$l_scb_offset; /* SCB offset of this entry */ } didt$r_fields; } didt$r_qw1; } DIDT; #if !defined(__VAXC)( #define didt$q_isr didt$r_qw0.didt$q_isr>#define didt$l_crb_sqfl didt$r_qw0.didt$r_qhdr.didt$l_crb_sqfl>#define didt$l_crb_sqbl didt$r_qw0.didt$r_qhdr.didt$l_crb_sqbl(#define didt$q_arg didt$r_qw1.didt$q_arg.#define didt$r_fields didt$r_qw1.didt$r_fields+#define didt$l_vec didt$r_fields.didt$l_vec9#define didt$l_scb_offset didt$r_fields.didt$l_scb_offset"#endif /* #if !defined(__VAXC) */ N/* */N/*  */O/* These constants enumerate the Interrupt Delievery Technologies considered */N/* by the routines that handle interrupt configuration and dispatch. */N/* */#define INTDEL$K_IOSAPIC 0#define INTDEL$K_MSI 1#define INTDEL$K_MSIX 2 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DIDTDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************************** ***************************************/=/* Created: 7-Oct-2024 15:22:14 by OpenVMS SDL V3.7 */H/* Source: 13-APR-2022 12:56:44 $1$DGA8345:[LIB_H.SRC]DIOBDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DIOBDDEF ***/#ifndef __DIOBDDEF_LOADED#define __DIOBDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* IOBD--Direct I/O Buffer Descriptor */N/* */N/* The IOBD structure is used to describe the physical address(es) of all */N/* buffers used in direct I/O. For the I/O to succeed, the buffer must be */N/* locked in memory. */N/* */N/* There are two variants of the IOBD structure. The first is the primary */N/* IOBD structure, which may be embedded in an IRP. It contains room for */N/* exactly DIOBD$K_FIXED_EXTENT_CNT extents. If more extents are needed */N/* to describe the physical address range of the buffer, the IOBD will be */N/* given a larger auxiliary extent list. */N/* */N/* An IOBD can also be created by calling IOC$CREATE_IOBD - in this case, */N/* since the IOBD has to be allocated from pool anyway, its extent list */N/* is sized to hold as many extents as are needed for the specified buffer  */N/* and no auxiliary extent list is needed. */N/* */N/* The IRP, IRPE, VCRP, and DCBE structures all contain an embedded fixed- */N/* size IOBD structure. */N/*- */  #include #ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save&#pragma __required_pointer_size __long!typedef struct _diobd * DIOBD_PQ;#typedef struct _diobd ** DIOBD_PPQ;)#pragma __required_pointer_size __restore#else"typedef unsigned __int64 DIOBD_PQ;#typedef unsigned __int64 DIOBD_PPQ;#endif#define DIOBD$M_INUSE 0x4 #define DIOBD$M_AUX_EXTENTS 0x10#define DIOBD$M_AUX_INUSE 0x20 #define DIOBD$M_REL_DEALLOC 0x80#define DIOBD$M_BY_PTE 0x400#define DIOBD$M_AUX_DIOBD 0x800'#define DIOBD$M_VALID_STORED_FLAGS 1172O#define DIOBD$K_HDRLEN 48 /* DIOBD header length (w/o extents) */\#define DIOBD$K_FIXED_EXTENT_CNT 4 /* Number of extents in the fixed-size IOBD. This */N/* value must keep the IOBD the same size as the DIOBM */b#define DIOBD$K_LENGTH 264 /* Size of fixed size DIOBD including the fixed extents */N/* */X#define DIOBD$M_NORESWAIT 1 /* No resource wait - return an error instead */X#define DIOBD$M_EXT_IOBD 2 /* This is an external IOBD, not one which is */N/* embedded in an IRP. This flag is ignored on */U#define DIOBD$M_INIT_IOBD 4 /* Initialize, do not validate, this IOBD. */N/* When using a stack IOBD it's possible for */Z#define DIOBD$M_PTE_STRIDE_1 8 /* When building the EXT list, step through the */N/* list of passed-in PTEs one by one no matter */ $#define DIOBD$M_VALID_PARAM_FLAGS 15 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _diobd { __union {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */T struct _ext *dio bd$pq_extents; /* If the IOBD is INUSE, this pointer can */#else# unsigned __int64 diobd$pq_extents;#endifN/* be used to find the extents mapped by */N/* this IOBD, whether they are embedded */N/* or auxiliary */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size defau lt to 64-bit pointers */V struct _diobd *diobd$pq_aux_diobd; /* Pointer to a secondary IOBD structure */#else% unsigned __int64 diobd$pq_aux_diobd;#endifN/* Valid if and only if IOBD$V_AUX_INUSE set */$ } diobd$r_extents_aux_union;N unsigned short int diobd$w_size; /* IOBD size in bytes */N unsigned char diobd$b_type; /* IOBD type, DYN$C_MISC */N unsigned char diobd$b_subtype; /* IOBD subtype, DYN$C_IOBD */S unsigned int diobd$il_byte_offset; /* This field may be made obsolete soon, */N/* but it has been useful debugging IOBD */N/* problems. A buffer's byte offset is */N/* always included in the physical */N/* address in the 1st extent, but on */N/* architectures where PTEs are not used */N/* to describe a buffer and on which page */N/* size can vary, it's not very useful. */P unsigned int diobd$il_byte_count; /* Total number of bytes described by */N/* the extents. */N unsigned int diobd$il_max_extent_count; /* Maximum number of extents */N unsigned int diobd$il_extent_count; /* Number of valid extents */Y unsigned int diobd$il_extents_alloc_size; /* Number of bytes of pool allocated for */N/* the extents list - only valid if */N/* DIOBD$IL_FLAGS.DIOBD$M_AUX_EXTENTS */N/* is set. */ __union {N unsigned int diobd$il_flags; /* Flag bits: */ __struct {V unsigned diobd$v_fill_0 : 2; /* 01:00 Avoid common fill pattern bits */N unsigned diobd$v_inuse : 1; /* 02 This IOBD is in use */V unsigned diobd$v_fill_3 : 1; /* 03 Avoid common fill pattern bits */p unsigned diobd$v_aux_extents : 1; /* 04 IOBD$PQ_EXTENTS points to an auxiliary extents list */_ unsigned diobd$v_aux_inuse : 1; /* ** IOBD$PS_AUX_IOBD points to secondary IOBD */V unsigned diobd$v_fill_5 : 1; /* 06:05 Avoid common fill pattern bits */\ unsigned diobd$v_rel_dealloc : 1; /* 07 Deallocate this IOBD on release */V unsigned diobd$v_fill_8 : 2; /* 09:08 Avoid common fill pattern bits */i unsigned diobd$v_by_pte : 1; /* 10 DIOBD was filled by PTE, not VA (BOFF is valid) */P unsigned diobd$v_aux_diobd : 1; /* ** This is an auxiliary DIOBD */) unsigned diobd$v_fill_2_ : 4; } diobd$r_fill_1_; } diobd$r_fill_0_;r/* These flags are valid in IOBD$IL_FLAGS - they are not t he same flags used in the FLAGS parameter (see below) */N unsigned int diobd$il_abcnt; /* Accumulated byte count */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *diobd$pq_va; /* VA mapped by the extents */#else unsigned __int64 diobd$pq_va;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pte *diobd$pq_pte; /* PTE used to map */#else unsigned __int64 diobd$pq_pte;#endif } diobd$r_va_pte_union;N/* Number of extents in the fixed-size IOBD. */N/* There's no reason for this constant to be */N/* used outside of this module - code should */N/* use the DIOBD extent count and maximum */N/* extent count fields, or use the DIOBD size */N/* and HDRLEN to calculate a maximum extent */N/* count, but the management of guard extents */N/* makes extent management best left to the */N/* code in DIOBD.C. */N/* (or smaller), to avoids changes to the offsets of */N/* IRP fields which follow it. */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {N EXT diobd$r_fixed_extents [9]; /* + 1 for a guard extent */#pragma __nomember_alignment __struct {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 diobd$iq_base_pa_vector [4]; /* Vector of PAs */c#if !defined(__NOBASEALI GN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifQ unsigned int diobd$il_base_length_vector [4]; /* Vector of lengths */# } diobd$r_base_extents;#pragma __nomember_alignment __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */5 unsigned __int64 *diobd$pq_aux_pa_vector;#else) unsigned __int64 diobd$pq_aux_pa_vector;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */5 unsigned int *diobd$pq_aux_length_vector;#else- unsigned __int64 diobd$pq_aux_length_vector;#endif" } diobd$r_aux_extents;" } diobd$r_extents_overlay;N/* Bits defined in the flags parameter to routines which take one */N/* */N/* NOSVAPTE platforms such as X86, and the IOBD */N/* will be filled regardless of its location - */N/* this bit is used to bypass sanity checks */N/* performed on SVAPTE platforms such as IA64 */N/* when filling a non-IRP-embedded IOBD. */N/* it to be reused as the routine which declares */N/* it is called repeatedly - the IOBD may retain */N/* enough context (type, subtype, size) to pass */N/* validation but still have been corrupted as */N/* other fields on the stack were used, maybe */N/* for a call to a different routine.  */N/* what the value of the architecture-specific */N/* constant PTE$C_PAGE_INCR is set to. This is */N/* to support unusual PTE lists such as those */N/* built by the Modified Page Writer. */X/* These flags are valid when used in the flags parameter supported by some routines. */ } DIOBD; #if !defined(__VAXC)C#define diobd$pq_extents diobd$r_extents_aux_union.diobd$pq_extentsG#define diobd$pq_aux_diobd diobd$r_extents_aux_union.diobd$pq_aux_diobd5#define diobd$il_flags diobd$r_fill_0_.diobd$il_flagsC#define diobd$v_inuse diobd$r_fill_0_.diobd$r_fill_1_.diobd$v_inuseO#define diobd$v_aux_extents diobd$r_fill_0_.diobd$r_fill_1_.diobd$v_aux_extentsK#define diobd$v_aux_inuse diobd$r_fill_0_.diobd$r_fill_1_.diobd$v_aux_inuseO#define diobd$v_rel_dealloc diobd$r_fill_0_.diobd$r_fill_1_.diobd$v_rel_deallocE#define diobd$v_by_pte diobd$r_fill_0_.diobd$r_fill_1_.diobd$v_by_pteK#define diobd$v_aux_diobd diobd$r_fill_0_.diobd$r_fill_1_.diobd$v_aux_diobd4#define diobd$pq_va diobd$r_va_pte_union.diobd$pq_va6#define diobd$pq_pte diobd$r_va_pte_union.diobd$pq_pteK#define diobd$r_fixed_extents diobd$r_extents_overlay.diobd$r_fixed_extentsI#define diobd$r_base_extents diobd$r_extents_overlay.diobd$r_base_extentsL#define diobd$iq_base_pa_vector diobd$r_base_extents.diobd$iq_base_pa_vectorT#define diobd$il_base_length_vector diobd$r_base _extents.diobd$il_base_length_vectorG#define diobd$r_aux_extents diobd$r_extents_overlay.diobd$r_aux_extentsI#define diobd$pq_aux_pa_vector diobd$r_aux_extents.diobd$pq_aux_pa_vectorQ#define diobd$pq_aux_length_vector diobd$r_aux_extents.diobd$pq_aux_length_vector"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DIOBDDEF_LOADED */ ww= [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-202 4 15:22:17 by OpenVMS SDL V3.7 */H/* Source: 26-JUL-2023 08:28:00 $1$DGA8345:[LIB_H.SRC]DIOBMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DIOBMDEF ***/#ifndef __DIOBMDEF_LOADED#define __DIOBMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DIOBMDEF_LOADED */  ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************* ***********************************************************************************************************//*** MODULE $DIRDEF ***/#ifndef __DIRDEF_LOADED#define __DIRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Directory entry structure for Files-11 Structure Level 2 */N/* */N/*- */ N#define DIR$C_FID 0 /* normal file ID  */P#define DIR$C_LINKNAME 1 /* symbolic name (obsolete, not used) */N/* Filename encoding codes. */N#define DIR$C_ODS2 0 /* ODS-2 legal ASCII */P#define DIR$C_ISL1 1 /* ODS-2 illegal ASCII or ISO LATIN-1 */#define DIR$$_TYPE_RESERVED 2O#define DIR$C_UCS2 3 /* Unicode USC-2 (16 bit characters) */R/* NOTE - The values of DIR$C_ODS2 et al. must be the same as the corresponding */Q#define DIR$K_LENGTH 6 /* length of directory entry overhead */Q#define DIR$C_LENGTH 6 /* length of directory entry overhead */N#define DIR$S_NAME 80 /* maximum length of name string */S#define DIR$S_ODS5_NAME 236 /* maximum length of name string (ODS-5) */N#define DIR$S_DIRDEF 6 /* Old size name - synonym */ typedef struct _dir {P unsigned short int dir$w_size;  /* size of directory record in bytes */N unsigned short int dir$w_verlimit; /* maximum number of versions */ __union {N unsigned char dir$b_flags; /* status flags */ __struct {N unsigned dir$v_type : 3; /* directory entry type */N unsigned dir$v_nametype : 3; /* Filename encoding type */V unsigned dir$v_special : 1; /* directory entry points to a special file */' unsigned dir$v_fill_8_ : 1; } dir$r_flags_bits;m __struct { /* the following two flags are obsolete and were never implemented */& unsigned dir$v_fill_1 : 6;Y unsigned dir$v_nextrec : 1; /* another record of same name & type follows */Z unsigned dir$v_prevrec : 1; /* another record of same name & type precedes */# } dir$r_flags_obsolete;N/* directory entry type codes  */N/* values for name encoding in FI5DEF and FIBDEF. */ } dir$r_flags_overlay; __union {N unsigned char dir$b_namecount; /* byte count of name string */ __struct { char dir$$_fill_2;#if defined(__VAXC) char dir$t_name[];#elseQ/* Warning: empty char[] member for dir$t_name at end of structure not created */"#endif /* #if defined(__VAXC) */N/* the version numbers and file ID's follow the  */N/* variable length name area in the form of a */N/* blockvector. Each entry is as follows: */% } dir$r_namecount_fields;" } dir$r_namecount_overlay; } DIR; #if !defined(__VAXC)3#define dir$b_flags dir$r_flags_overlay.dir$b_flagsB#define dir$v_type dir$r_flags_overlay.dir$r_flags_bits.dir$v_typeJ#define dir$v_nametype dir$r_flags_overlay.dir$r_flags_bits.dir$v_nametypeH#def ine dir$v_special dir$r_flags_overlay.dir$r_flags_bits.dir$v_specialL#define dir$v_nextrec dir$r_flags_overlay.dir$r_flags_obsolete.dir$v_nextrecL#define dir$v_prevrec dir$r_flags_overlay.dir$r_flags_obsolete.dir$v_prevrec?#define dir$b_namecount dir$r_namecount_overlay.dir$b_namecountL#define dir$t_name dir$r_namecount_overlay.dir$r_namecount_fields.dir$t_name"#endif /* #if !defined(__VAXC) */ N#define DIR$K_VERSION 8 /* size of each version entry */N#define DIR$C_VE RSION 8 /* size of each version entry */N#define DIR$S_DIRDEF1 8 /* Old size name - synonym */ typedef struct _dir1 {N short int dir$w_version; /* version number */ __union {N unsigned short int dir$w_fid [3]; /* file ID */ __struct {N unsigned short int dir$w_fid_num; /* file number */N unsigned short int dir$w_fid_seq; /* file se quence number */ __union {O unsigned short int dir$w_fid_rvn; /* relative volume number */ __struct {N unsigned char dir$b_fid_rvn; /* alternate format RVN */^ unsigned char dir$b_fid_nmx; /* alternate format file number extension */+ } dir$r_fid_rvn_fields;( } dir$r_fid_rvn_overlay; } dir$r_fid_fields; } dir$r_fid_overlay; } DIR1; #if !defined(__VAXC)-#define dir$w_fid dir$r_fid_overlay.dir$w_fidF#define dir$w_fid_num dir$r_fid_overlay.dir$r_fid_fields.dir$w_fid_numF#define dir$w_fid_seq dir$r_fid_overlay.dir$r_fid_fields.dir$w_fid_seq\#define dir$w_fid_rvn dir$r_fid_overlay.dir$r_fid_fields.dir$r_fid_rvn_overlay.dir$w_fid_rvnq#define dir$b_fid_rvn dir$r_fid_overlay.dir$r_fid_fields.dir$r_fid_rvn_overlay.dir$r_fid_rvn_fields.dir$b_fid_rvnq#define dir$b_fid_nmx dir$r_fid_overlay.dir$r_fid_fields.dir$r_fid_rvn_overlay.dir $r_fid_rvn_fields.dir$b_fid_nmx"#endif /* #if !defined(__VAXC) */ N#define DIR$S_DIRDEF2 1 /* Old size name - synonym */ typedef struct _dir2 {R char dir$t_linkname; /* symbolic link name (counted string) */ } DIR2;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DIRDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7  */G/* Source: 05-MAR-2003 17:04:52 $1$DGA8345:[LIB_H.SRC]VECTORS.SDL;1 *//********************************************************************************************************************************//*** MODULE DISPDEF ***/#ifndef __DISPDEF_LOADED#define __DISPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define DISP_K_LENGTH 16 /* Size of list element */N#define DISP_S_DISPDEF 16 /* Old size name - synonym */ typedef struct _disp {N void *disp_a_service_routine; /* Address of first instruction of */N/* service-specific procedure */N void *disp_a_e ntry_point; /* Actual code address */R unsigned char disp_b_flags; /* Flags (first byte for compatibility) */R char disp_b_fillerb; /* N.B. The system service dispatcher */N short int disp_w_fillerw; /* treats this as a longword */N short int disp_w_vector_index; /* Index into SYS$PUBLIC_VECTORS */ short int disp_w_fillerl; } DISP;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DISPDEF_LOADED */ ww0 [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************** ***************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */I/* Source: 23-JUN-2004 13:16:13 $1$DGA8345:[LIB_H.SRC]RMSPUBSTR.SDL;1 *//********************************************************************************************************************************/ /*** MODULE $DISPLAY_WILDEF ***/#ifndef __DISPLAY_WILDEF_LOADED!#define __DISPLAY_WILDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* $DISPLAY_WILD */N/*  */N/* Display File */N/* */N/* $DISPLAY_WILD fab, [err], [suc], ctx */N/* */N/* fab_rab = address of fab or rab */N/*  */E/* err = address of user error completion routine */N/* */E/* suc = address of user success completion routine */E/* ctx = address of a longword used to hold the next ifi. */N/* */!#define sys$display SYS$DISPLAY "int sys$display(__unknown_params); $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard $#endif /* __DISPLAY_WILDEF_LOADED */ wwPO [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********************************************************** ****************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */F/* Source: 17-DEC-1993 12:37:45 $1$DGA8345:[LIB_H.SRC]DJIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DJIDEF ***/#ifndef __DJIDEF_LOADED#define __DJIDEF_LOADED 1 G#p ragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Item codes for interface from job controller to LOGINOUT. */N/* */R#define DJI$K_CPU_MAXIMUM 1 /* (longword) CPU maximum (10 ms units) */[#define DJI$K_FILE_IDENTIFICATION 2 /* (28 bytes) DVI, FID, DID of command procedure */L#define DJI$K_FLAGS 3 /* (longword) flags */J#define DJI$K_JOB_NAME 4 /* (string) job name */J#define DJI$K_LOG_QUEUE 5 /* (string) log file queue */M#define DJI$K_LOG_SPECIFICATION 6 /* (string) log file specification */J#define DJI$K_PARAMETER_1 7 /* (string) value of P1 */J#define DJI$K_PARAMETER_2 8 /* (string) value of P2 */J#define DJI$K_PARAMETER_3 9 /* (string) value of P3 */J#define DJI$K_PARAMETER_4 10 /* (string) value of P4 */J#define DJI$K_PARAMETER_5 11 /* (string) value of P5 */J#define DJI$K_PARAMETER_6 12 /* (string) value of P6  */J#define DJI$K_PARAMETER_7 13 /* (string) value of P7 */J#define DJI$K_PARAMETER_8 14 /* (string) value of P8 */M#define DJI$K_RESTART 15 /* (string) value of BATCH$RESTART */J#define DJI$K_USERNAME 16 /* (string) username */L#define DJI$K_WSDEFAULT 17 /* (longword) working set default */L#define DJI$K_WSEXTENT 18 /* (longword) working set extent */L#define DJI$K_WSQUOTA 19  /* (longword) working set quota */N#define DJI$K_ADJUST_PRIORITY 20 /* (longword) adjusted priority */J#define DJI$K_CLI 21 /* (string) CLI name */O#define DJI$K_CLASS 22 /* (20 bytes) process classification */J#define DJI$K_NOTE 23 /* (string) the job's note */R#define DJI$K_CHARGE_CODE_NAME 24 /* (string) account or charge code name */L#define DJI$K_INPUT_FLAGS 32769 /* (longword) flags  */Q#define DJI$K_CONDITION_VECTOR 32770 /* (1 to 3 longwords) error conditions */Q#define DJI$K_FILE_SPECIFICATION 32771 /* (string) filespec of failed logfile */ !typedef struct _dji_item_header {N unsigned short int dji$w_item_size; /* Item size */N unsigned short int dji$w_item_code; /* Item code */ } DJI_ITEM_HEADER;O#define DJI$S_ITEM_HEADER 4 /* Size (using prior aggregate name) */N/*  */N/* Structure of FLAGS item. */N/* */#define DJI$M_DELETE_FILE 0x1#define DJI$M_LOG_DELETE 0x2#define DJI$M_LOG_NULL 0x4#define DJI$M_LOG_SPOOL 0x8#define DJI$M_NOTIFY 0x10#define DJI$M_RESTARTING 0x20#define DJI$M_TERMINATE 0x40"#define DJI$M_USE_CPU_MAXIMUM 0x80!#define DJI$M_USE_WSDEFAULT 0x100  #define DJI$M_USE_WSEXTENT 0x200#define DJI$M_USE_WSQUOTA 0x400N#define DJI$S_FLAGS 4 /* Old size name synonym */ typedef struct _dji_flags { __union {! unsigned int dji$l_flags; __struct {N unsigned dji$v_delete_file : 1; /* delete command procedure */N unsigned dji$v_log_delete : 1; /* delete log file */N unsigned dji$v_log_null : 1; /* log specification is NLA0: */N  unsigned dji$v_log_spool : 1; /* spool log file */N unsigned dji$v_notify : 1; /* spool log file with /NOTIFY */N unsigned dji$v_restarting : 1; /* job is restarting */N unsigned dji$v_terminate : 1; /* job should terminate */O unsigned dji$v_use_cpu_maximum : 1; /* use specified CPU_MAXIMUM */N unsigned dji$v_use_wsdefault : 1; /* use specified WSDEFAULT */N unsigned dji$v_use_w sextent : 1; /* use specified WSEXTENT */N unsigned dji$v_use_wsquota : 1; /* use specified WSQUOTA */' unsigned dji$v_fill_2_ : 5; } dji$r_fill_1_; } dji$r_fill_0_; } DJI_FLAGS; #if !defined(__VAXC)-#define dji$l_flags dji$r_fill_0_.dji$l_flagsG#define dji$v_delete_file dji$r_fill_0_.dji$r_fill_1_.dji$v_delete_fileE#define dji$v_log_delete dji$r_fill_0_.dji$r_fill_1_.dji$v_log_deleteA#define dji$v_log_null dji$r_fill_0_.dji$r_fill_1_.dji$v_log_nullC#define dji$v_log_spool dji$r_fill_0_.dji$r_fill_1_.dji$v_log_spool=#define dji$v_notify dji$r_fill_0_.dji$r_fill_1_.dji$v_notifyE#define dji$v_restarting dji$r_fill_0_.dji$r_fill_1_.dji$v_restartingC#define dji$v_terminate dji$r_fill_0_.dji$r_fill_1_.dji$v_terminateO#define dji$v_use_cpu_maximum dji$r_fill_0_.dji$r_fill_1_.dji$v_use_cpu_maximumK#define dji$v_use_wsdefault dji$r_fill_0_.dji$r_fill_1_.dji$v_use_wsdefaultI#define dji$v_use_wsextent dji$r_fill_0_.dji $r_fill_1_.dji$v_use_wsextentG#define dji$v_use_wsquota dji$r_fill_0_.dji$r_fill_1_.dji$v_use_wsquota"#endif /* #if !defined(__VAXC) */ N/* */N/* Structure of INPUT_FLAGS item. */N/* */#define DJI$M_NO_FILE 0x1N#define DJI$S_INPUT_FLAGS 4 /* Old size name synonym */ !typedef struct _dji_input_flags { __union {' unsigned int dji$l_input_flags; __struct {N unsigned dji$v_no_file : 1; /* do not return a file */' unsigned dji$v_fill_5_ : 7; } dji$r_fill_4_; } dji$r_fill_3_; } DJI_INPUT_FLAGS; #if !defined(__VAXC)9#define dji$l_input_flags dji$r_fill_3_.dji$l_input_flags?#define dji$v_no_file dji$r_fill_3_.dji$r_fill_4_.dji$v_no_file"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DJIDEF_LOADED */ ww`v [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */I/* Source: 09-JUN-1993 15:42:57 $1$DGA8345:[LIB_H.SRC]RMSFILSTR.SDL;1 *//********************************************************************************************************************************//*** MODULE $DLCDEF ***/#ifndef __DLCDEF_LOADED#define __DLCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/*  */N/* relative file deletion control byte bit definitions */N/* */#define DLC$M_DELETED 0x4#define DLC$M_REC 0x8N#define DLC$S_DLCDEF 1 /* Old size name - synonym */ typedef struct _dlc { __struct {N unsigned dlc$$_fill_1 : 2; /* (start with bit 2) */N unsigned dlc$v_deleted : 1; /* record deleted  */X unsigned dlc$v_rec : 1; /* record exists (but may have been deleted) */# unsigned dlc$v_fill_3_ : 4; } dlc$r_dlcdef_bits; } DLC; #if !defined(__VAXC)5#define dlc$v_deleted dlc$r_dlcdef_bits.dlc$v_deleted-#define dlc$v_rec dlc$r_dlcdef_bits.dlc$v_rec"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DLCDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************************************************************** ***/=/* Created: 7-Oct-2024 15:22:35 by OpenVMS SDL V3.7 */F/* Source: 03-MAY-1993 10:31:57 $1$DGA8345:[LIB_H.SRC]DMBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DMBDEF ***/#ifndef __DMBDEF_LOADED#define __DMBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DMB32 (BICOMBO) specific register definitions */N/*- */#define DMB$M_FORCE_FAIL 0x1#define DMB$M_PROGRAM_RESET 0x2#define DMB$M_PTE_VALID 0x4#define DMB$M_SKIP_SELFTEST 0x8#define DMB$M_MAINT_LEVEL1 0x10#define DMB$M_MAINT_LEVEL2 0x20#define DMB$M_SYNC 0x100#define DMB$M_ASYNC 0x200#define DMB$M_PRINT 0x400#define DMB$M_DIAG_FAIL 0x800 #define DMB$M_X21_SUPPORT 0x1000#define DMB$M_CABLE_KEY 0x2000#define DMB$M_TURN_CONN 0x4000#define DMB$M_MANF_CONN 0x8000#define DMB$M_RX_I_E 0x100#define DMB$M_TX_I_E 0x200#define DMB$M_SYNC_I_E 0x800#define DMB$M_PR_I_E 0x800$#define DMB$M_PR_DAVFU_READY 0x10000'#define DMB$M_PR_CONNECT_VERIFY 0x20000 #define DMB$M_PR_OFFLINE 0x40000#define DMB$M_ASYNC_RESET 0x400#define DMB$M_SYNC_RESET 0x400!#define DMB$M_PRINTER_RESET 0x400#define DMB$M_PR_DMA_START 0x1#define DMB$M_PR_DMA_PTE 0x2#define DMB$M_PR_DMA_PHYS 0x4 #define DMB$M_PR_DMA_ABORT 0x100#define DMB$M_PR_FORMAT 0x200#define DMB$M_PR_TAB 0x1000000 #define DMB$M_PR_TRUNC 0x2000000&#define DMB$M_PR_AUTO_RETURN 0x4000000$#define DMB$M_PR_AUTO_FORM 0x8000000%#define DMB$M_PR_NON_PRINT 0x10000000!#define DMB$M_PR_DAVFU 0x20000000 #define DMB$M_PR_WRAP 0x40000000!#define DMB$M_PR_UPPER 0x80000000#define DMB$M_TX1_DMA_START 0x1#define DMB$M_TX1_DMA_PTE 0x2#define DMB$M_TX1_DMA_PHYS 0x4#define DMB$M_TX1_X21 0x8#define DMB$M_TX1_PAR 0x10!#define DMB$M_TX1_DMA_ABORT 0x100#define DMB$M_RX1_DMA_START 0x1#define DMB$M_RX1_DMA_PTE 0x2#define DMB$M_RX1_DMA_PHYS 0x4#define DMB$M_RX1_X21 0x8!#define DMB$M_RX1_DMA_ABORT 0x100#define DMB$M_RX_ENABLE 0x1#define DMB$M_RX_MATCH_ENA 0x4#define DMB$M_RX_PRIMARY 0x8#define DMB$M_X21ENABLE 0x10 #define DMB$M_CLOCK_CONTROL 0x40#define DMB$M_CODING_TYPE 0x80#define DMB$M_BAUD_RATE 0xF00#define DMB$M_LOOP 0x1000#define DMB$M_V35_SELECT 0x2000#define DMB$M_V10_SELECT 0x4000##define DMB$M_MODEM_SUPPRESS 0x8000##define DMB$M_LINE_RESET 0x80000000#define DMB$M_SYNC_ML1 0x1#define DMB$M_SYNC_DTR 0x2#define DMB$M_SYNC_DRS 0x4#define DMB$M_SYNC_ML2 0x8#define DMB$M_SYNC_RTS 0x10#define DMB$M_SPARE_MODEM 0xE0 #define DMB$M_SYNC_RXCLOCK 0x100 #define DMB$M_SYNC_TXCLOCK 0x200#define DMB$M_SYNC_TI 0x400#define DMB$M_SYNC_CTS 0x1000#define DMB$M_SYNC_DCD 0x2000#define DMB$M_SYNC_RI 0x4000#define DMB$M_SYNC_DSR 0x8000#define DMB$M_PROTOCOL 0x70000#define DMB$C_PRO_DDCMP 0#define DMB$C_PRO_SDLC 1#define DMB$C_PRO_HDLC 2#define DMB$C_PRO_BISYNC 3#define DMB$C_PRO_GENBYTE 7!#define DMB$M_ERROR_TYPE 0x380000#define DMB$C_ERR_CRC1 0#define DMB$C_ERR_CRC0 1#define DMB$C_ERR_LVE 2#define DMB$C_ERR_CRC16 3#define DMB$C_ERR_LRC0 4#define DMB$C_ERR_LRCE 5#define DMB$C_ERR_LVO 6#define DMB$C_NOCON 7#define DMB$M_RX_BPC 0x1C00000#define DMB$M_TX_BPC 0xE000000##define DMB$M_STRIP_SYNC 0x10000000$#define DMB$M_EBCDIC_CODE 0x20000000"#define DMB$M_IDLE_SYNC 0x40000000'#define DMB$M_MODEM_OVERRIDE 0x80000000#define DMB$M_TX2_DMA_START 0x1#define DMB$M_TX2_DMA_PTE 0x2#define DMB$M_TX2_DMA_PHYS 0x4#define DMB$M_TX2_X21 0x8#define DMB$M_TX2_PAR 0x10!#define DMB$M_TX2_DMA_ABORT 0x100#define DMB$M_RX2_DMA_START 0x1#define DMB$M_RX2_DMA_PTE 0x2#define DMB$M_RX2_DMA_PHYS 0x4#define DMB$M_RX2_X21 0x8!#define DMB$M_RX2_DMA_ABORT 0x100"#define DMB$M_SYNC_CABLE 0xF000000"#define DMB$M_SYNC_LOOP 0x20000000##define DMB$M_SYNC_VALID 0x40000000!#define DMB$M_SYNC_X21 0x80000000#define DMB$M_PREEMPT_GO 0x8000#define DMB$M_ML 0x1#define DMB$M_DTR 0x2#define DMB$M_DRS 0x4#define DMB$M_RTS 0x10 #define DMB$M_TX_INT_DELAY 0x200#define DMB$M_RX_ENA 0x400#define DMB$M_BREAK 0x800#define DMB$M_MAINT 0x3000!#define DMB$M_REPORT_MODEM 0x4000!#define DMB$M_DISCARD_FLOW 0x8000!#define DMB$M_CHAR_LENGTH 0x30000!#define DMB$M_PARITY_ENAB 0x40000!#define DMB$M_EVEN_PARITY 0x80000 #define DMB$M_STOP_CODE 0x100000#define DMB$M_USE_CTS 0x200000!#define DMB$M_IAUTO_FLOW 0x400000!#define DMB$M_OAUTO_FLOW 0x800000 #define DMB$M_RX_SPEED 0xF000000!#define DMB$M_TX_SPEED 0xF0000000#define DMB$M_TX_DMA_START 0x1#define DMB$M_TX_DMA_PTE 0x2#define DMB$M_TX_DMA_PHYS 0x4 #define DMB$M_TX_OUT_ABORT 0x100#define DMB$M_ML2 0x400#define DMB$M_CTS 0x1000#define DMB$M_DCD 0x2000#define DMB$M_RI 0x4000#define DMB$M_DSR 0x8000#define DMB$M_SNDOFF 0x800000#define DMB$M_TX_ENA 0x80000000#define DMB$M_TX_PREEMPT 0x100 #define DMB$M_TX_FIFO_DONE 0x200#define DMB$M_TX_ACT 0x80000000#define DMB$M_SYNC_MODEM 0x100#define DMB$M_SYNC_TX_ACT 0x200&#define DMB$M_SYNC_SECOND_BUFFER 0x400#define DMB$M_PARITY_ERR 0x1000#define DMB$M_FRAME_ERR 0x2000 #define DMB$M_OVERRUN_ERR 0x4000#define DMB$M_NON_CHAR 0x8000##define DMB$M_DATA_VALID 0x80000000#define DMB$C_NO_ERROR 0#define DMB$C_DMA_ERROR 1#define DMB$C_MSG_ERROR 2#define DMB$C_LAST_CHAR_ERROR 3#define DMB$C_BUFFER_ERROR 4#define DMB$C_MODEM_ERROR 5#define DMB$C_ABORT_ERROR 6#define DMB$C_X21_ERROR 7#define DMB$C_OFFLINE_ERROR 8#define DMB$C_INTERNAL_ERROR 9 #define DMB$C_HEADER_CRC_ERROR 1#define DMB$C_DATA_CRC_ERROR 2#define DMB$C_LENGTH_ERROR 3$#define DMB$C_LENGTH_AND_CRC_ERROR 4%#define DMB$C_ABORT_CHARACTER_ERROR 5'#define DMB$C_INVALID_CHARACTER_ERROR 6 #define DMB$C_HOST_ABORT_ERROR 1#define DMB$C_DMB_ABORT_ERROR 2 #define DMB$C_RX_OVERRUN_ERROR 1!#define DMB$C_TX_UNDERRUN_ERROR 2N#define DMB$S_DMBDEF 528 /* Old size name - synonym */ typedef struct _dmb { char dmbdef$$_fill_1 [256]; __union  {N unsigned int dmb$l_maint; /*Maintenance register */ __struct {N unsigned dmb$v_force_fail : 1; /*Force failure */N unsigned dmb$v_program_reset : 1; /*Programmed reset */N unsigned dmb$v_pte_valid : 1; /*Page tables valid */N unsigned dmb$v_skip_selftest : 1; /*Skip self test */N unsigned dmb$v_maint_level1 : 1; /*Maintenance level 1 */N unsigned dmb$v_maint_level2 : 1; /*Maintenance level 2 */) unsigned dmbdef$$_fill_2 : 2;N unsigned dmb$v_sync : 1; /*Sync lines present */N unsigned dmb$v_async : 1; /*Async lines present */N unsigned dmb$v_print : 1; /*Printer present */N unsigned dmb$v_diag_fail : 1; /*Diagnostic error */N unsigned dmb$v_x21_support : 1; /*X21 firmware sup port present */N unsigned dmb$v_cable_key : 1; /*Cable key signal present */N unsigned dmb$v_turn_conn : 1; /*stag. loopback conn. present */N unsigned dmb$v_manf_conn : 1; /*Mfg. loopback conn. present */ } dmb$r_maint_bits; } dmb$r_maint_overlay;N/* */N/* The following 3 registers are the Control Status Registers (CSRs) for */N/* the Async, Sync, an d Printer ports in that order. */N/* */ __union {N unsigned int dmb$l_acsr; /*Async Control Status Register */ __struct {N char dmb$b_async_ind_add; /*Indirect Addr. Register Ptr. */N unsigned dmb$v_rx_i_e : 1; /*Receive Interrupt Enable */N unsigned dmb$v_tx_i_e : 1; /*Transmit Interrupt Enable */'  unsigned dmb$v_fill_0_ : 6; } dmb$r_acsr_bits; } dmb$r_acsr_overlay; __union {N unsigned int dmb$l_scsr; /*Sync Control Status Register */ __struct {N char dmb$b_sync_ind_add; /*Indirect Addr. Register Ptr. */) unsigned dmbdef$$_fill_4 : 3;N unsigned dmb$v_sync_i_e : 1; /*Sync Interrupt Enable */' unsigned dmb$v_fill_1_ : 4; } dmb$r_scsr_bits; } dmb$ r_scsr_overlay; __union {N unsigned int dmb$l_pcsr; /*Printer Control Status Register */ __struct {* unsigned dmbdef$$_fill_5 : 11;N unsigned dmb$v_pr_i_e : 1; /*Printer Interrupt Enable */) unsigned dmbdef$$_fill_6 : 4;N unsigned dmb$v_pr_davfu_ready : 1; /*DAVFU ready */N unsigned dmb$v_pr_connect_verify : 1; /*Connect verify */N unsigned dmb$v_pr_offline : 1;  /*Line printer error */' unsigned dmb$v_fill_2_ : 5; } dmb$r_pcsr_bits; } dmb$r_pcsr_overlay;N int dmb$l_fill_7; /*Unused */N/* */N/* Configuration of devices on DMB32. */N/* */ __union {N unsigned int dmb$l _config; /*Device Configuration */ __struct {N char dmb$b_async_lines; /*Number of async lines */N char dmb$b_sync_lines; /*Number of sync lines */N char dmb$b_printer_lines; /*Number of printer ports */" } dmb$r_config_fields; } dmb$r_config_overlay;N/* */N/* The following 3 registers are the 2nd  Control Status Registers for */N/* each of the ports on the DMB32 (Async, Sync, and Printer). */K/* */ __union {N int dmb$l_acsr2; /*2ND Async Control Status Register */ __struct {* unsigned dmbdef$$_fill_7 : 10;N unsigned dmb$v_async_reset : 1; /*Async Port reset */) unsigned dmbdef$$_fill_8 : 5;N char dmb$b _rx_timer; /*Rcv Interrupt delay timer */ } dmb$r_acsr2_bits; } dmb$r_acsr2_overlay; __union {N int dmb$l_scsr2; /*2ND Sync Control Status Register */ __struct {* unsigned dmbdef$$_fill_9 : 10;N unsigned dmb$v_sync_reset : 1; /*Sync Port reset */' unsigned dmb$v_fill_3_ : 5; } dmb$r_scsr2_bits; } dmb$r_scsr2_overlay; __union {P unsigned  int dmb$l_pcsr2; /*2ND Printer Control Status Register */ __struct {+ unsigned dmbdef$$_fill_10 : 10;N unsigned dmb$v_printer_reset : 1; /*Printer Port reset */' unsigned dmb$v_fill_4_ : 5; } dmb$r_pcsr2_bits; } dmb$r_pcsr2_overlay; int dmbdef$$_fill_11 [11];N unsigned int dmb$l_spte; /*SPTE system page table register */N unsigned int dmb$l_spts; /*System page table size registe r */N unsigned int dmb$l_gpte; /*Global page table register */N unsigned int dmb$l_gpts; /*Global page table size register */N/* */N/* The following 6 registers are specific to the printer port on the */N/* DMB32. */N/* */ __union {N  unsigned int dmb$l_pfix; /*Printer prefix/suffix control */ __struct {N char dmb$b_prefix_count; /*Prefix count */N char dmb$b_prefix_char; /*Prefix character */N char dmb$b_suffix_count; /*Suffix count */N char dmb$b_suffix_char; /*Suffix character */ } dmb$r_pfix_fields; } dmb$r_pfix_overlay;O void *dmb$l_pbuf ad; /*Printer Buffer Address */ __union {N unsigned int dmb$l_pbufct; /*Printer Buffer count/offset */ __struct {N short int dmb$w_pr_buff_off; /*printer buffer offset */N short int dmb$w_pr_buff_ct; /*transmit DMA char. count */" } dmb$r_pbufct_fields; } dmb$r_pbufct_overlay; __union {N unsigned int dmb$l_pctrl; /*Printer Control Register */ __struct {N unsigned dmb$v_pr_dma_start : 1; /*Start a DMA transfer */N unsigned dmb$v_pr_dma_pte : 1; /*PTE address */N unsigned dmb$v_pr_dma_phys : 1; /*Physical address */* unsigned dmbdef$$_fill_12 : 5;N unsigned dmb$v_pr_dma_abort : 1; /*Abort a DMA transfer */N unsigned dmb$v_pr_format : 1; /*Format control */* unsigned dmbdef$$_fill_13 : 6;N char dmb$b_pr_error; /*Error code */N unsigned dmb$v_pr_tab : 1; /*Tab expansion */N unsigned dmb$v_pr_trunc : 1; /*Truncation of Data */N unsigned dmb$v_pr_auto_return : 1; /*Auto CR insert */N unsigned dmb$v_pr_auto_form : 1; /*Auto FF to LF convert */N unsigned dmb$v_pr_non_print : 1; /*Non printing char. accept */N unsigned d mb$v_pr_davfu : 1; /*DAVFU */N unsigned dmb$v_pr_wrap : 1; /*Line Wrap */N unsigned dmb$v_pr_upper : 1; /*Convert to upper case */ } dmb$r_pctrl_bits; } dmb$r_pctrl_overlay; __union {N unsigned int dmb$l_pcar; /*Printer Carriage Counter */ __struct {N short int dmb$w_pr_line; /*Lines printed */N short int dm b$w_pr_char; /*Characters transmitted */ } dmb$r_pcar_fields; } dmb$r_pcar_overlay; __union {N unsigned int dmb$l_psize; /*Printer page size */ __struct {N short int dmb$w_pr_width; /*Line Width */N short int dmb$w_pr_page; /*Page size */! } dmb$r_psize_fields; } dmb$r_psize_overlay; int dmbdef$$_fill_14 [2];N/*   */N/* The next 16 registers are specific to the SYNC port on the DMB32. */N/* */N void *dmb$l_tbuffad1; /*Transmit Buffer Address 1 */ __union {N unsigned int dmb$l_tbuffct1; /*Transmit Buffer Count/offset 1 */ __struct {N short int dmb$w_tx_buff_off1; /*Transmit buffer offset  */N short int dmb$w_tx_char_ct1; /*Transmit DMA character count */$ } dmb$r_tbuffct1_fields;! } dmb$r_tbuffct1_overlay;N void *dmb$l_rbuffad1; /*Receive Buffer Address 1 */ __union {N unsigned int dmb$l_rbuffct1; /*Receive Buffer Count/offset 1 */ __struct {N short int dmb$w_rx_buff_off1; /*Receive buffer offset */N short int dmb$w_rx_char_ct1; /*Receive DMA character cou nt */$ } dmb$r_rbuffct1_fields;! } dmb$r_rbuffct1_overlay; __union {N unsigned int dmb$l_tlnctrl1; /*Buffer 1 Transmit Control */ __struct {N unsigned dmb$v_tx1_dma_start : 1; /*Start a DMA transfer */N unsigned dmb$v_tx1_dma_pte : 1; /*PTE address */N unsigned dmb$v_tx1_dma_phys : 1; /*Physical address */N unsigned dmb$v_tx1_x21 : 1; /*X.21 mode  */N unsigned dmb$v_tx1_par : 1; /*Parameter change */* unsigned dmbdef$$_fill_15 : 3;N unsigned dmb$v_tx1_dma_abort : 1; /*Transmitter DMA abort */+ unsigned dmbdef$$_fill_16 : 15;N char dmb$b_tx1_error; /*Transmitter Error bits */" } dmb$r_tlnctrl1_bits;! } dmb$r_tlnctrl1_overlay; __union {N unsigned int dmb$l_rlnctrl1; /*Buffer 1 Receive Control  */ __struct {N unsigned dmb$v_rx1_dma_start : 1; /*Start a DMA transfer */N unsigned dmb$v_rx1_dma_pte : 1; /*PTE address */N unsigned dmb$v_rx1_dma_phys : 1; /*Physical address */N unsigned dmb$v_rx1_x21 : 1; /*X.21 mode */* unsigned dmbdef$$_fill_17 : 4;N unsigned dmb$v_rx1_dma_abort : 1; /*Receiver DMA abort */+ unsigned dmbdef$$_ fill_18 : 15;N char dmb$b_rx1_error; /*Receiver error bits */" } dmb$r_rlnctrl1_bits;! } dmb$r_rlnctrl1_overlay; __union {N unsigned int dmb$l_lpr1; /*Sync line parameters 1 */ __struct {N unsigned dmb$v_rx_enable : 1; /*Receiver Enable */* unsigned dmbdef$$_fill_19 : 1;Q unsigned dmb$v_rx_match_ena : 1; /*Receiver Match character enable */N unsigned dmb$v_rx_primary : 1; /*Primary-Secondary Station */N unsigned dmb$v_x21enable : 1; /*X21 Protocol Enable */* unsigned dmbdef$$_fill_20 : 1;N unsigned dmb$v_clock_control : 1; /*Clock control bit */N unsigned dmb$v_coding_type : 1; /*Data coding type */N unsigned dmb$v_baud_rate : 4; /*Internal B.R. Generator speed */N unsigned dmb$v_loop : 1; /*Maintenance Loop back  */N unsigned dmb$v_v35_select : 1; /*V.35 select */N unsigned dmb$v_v10_select : 1; /*V.10 select */N unsigned dmb$v_modem_suppress : 1; /*Supress modem change ints */N char dmb$b_number_sync; /*Number of sync characters */* unsigned dmbdef$$_fill_22 : 7;N unsigned dmb$v_line_reset : 1; /*Line reset request */ } dmb$r_lpr1_bits; } dmb$r_lpr1_ove rlay; __union {N unsigned int dmb$l_lpr2; /*Sync line parameters 2 */ __struct {N unsigned dmb$v_sync_ml1 : 1; /*Modem loop output */N unsigned dmb$v_sync_dtr : 1; /*Data terminal ready output */N unsigned dmb$v_sync_drs : 1; /*Data rate select output */N unsigned dmb$v_sync_ml2 : 1; /*2nd modem loop output */N unsigned dmb$v_sync_rts : 1; /*Request to send output */N unsigned dmb$v_spare_modem : 3; /* */N unsigned dmb$v_sync_rxclock : 1; /*Receive clock running */N unsigned dmb$v_sync_txclock : 1; /*Transmit clock running */N unsigned dmb$v_sync_ti : 1; /*Test indicator */* unsigned dmbdef$$_fill_23 : 1;N unsigned dmb$v_sync_cts : 1; /*Clear to send input */N unsigned dmb$v_sync_dcd : 1; /*Data carrier detect input */N unsigned dmb$v_sync_ri : 1; /*Ring indicator input */N unsigned dmb$v_sync_dsr : 1; /*Data set ready input */N unsigned dmb$v_protocol : 3; /*Protocol type */* unsigned dmb$v_error_type : 3;N unsigned dmb$v_rx_bpc : 3; /*#of receive bits per char. */N unsigned dmb$v_tx_bpc : 3; /*# of transmit bits per char. */N unsigned dmb $v_strip_sync : 1; /*Strip Sync */N unsigned dmb$v_ebcdic_code : 1; /*Character code */N unsigned dmb$v_idle_sync : 1; /*Idle Sync */N unsigned dmb$v_modem_override : 1; /*Modem control override */ } dmb$r_lpr2_bits; } dmb$r_lpr2_overlay;N void *dmb$l_tbuffad2; /*Transmit Buffer Address 2 */ __union {N unsigned int dmb$l_tbuffct2; /*Transmit  Buffer count/offset 1 */ __struct {N short int dmb$w_tx_buff_off2; /*Transmit buffer offset */N short int dmb$w_tx_char_ct2; /*Transmit DMA character count */$ } dmb$r_tbuffct2_fields;! } dmb$r_tbuffct2_overlay;N void *dmb$l_rbuffad2; /*Receive Buffer Address 2 */ __union {N unsigned int dmb$l_rbuffct2; /*Receive Buffer count/offset 2 */ __struct {N short int dmb$w_rx_buff_off2; /*Receive buffer offset */N short int dmb$w_rx_char_ct2; /*Receive DMA character count */$ } dmb$r_rbuffct2_fields;! } dmb$r_rbuffct2_overlay; __union {N unsigned int dmb$l_tlnctrl2; /*Buffer 2 Transmit Control */ __struct {N unsigned dmb$v_tx2_dma_start : 1; /*Start a DMA transfer */N unsigned dmb$v_tx2_dma_pte : 1; /*PTE address */N unsigned dmb$v_tx2_dma_phys : 1; /*Physical address */N unsigned dmb$v_tx2_x21 : 1; /*X.21 mode */N unsigned dmb$v_tx2_par : 1; /*Parameter change */* unsigned dmbdef$$_fill_24 : 3;N unsigned dmb$v_tx2_dma_abort : 1; /*Transmitter DMA abort */+ unsigned dmbdef$$_fill_25 : 15;N char dmb$b_tx2_error; /*Transmitter error bits */" } dmb$r_tlnctrl2_bit s;! } dmb$r_tlnctrl2_overlay; __union {N unsigned int dmb$l_rlnctrl2; /*Buffer 2 Receive control */ __struct {N unsigned dmb$v_rx2_dma_start : 1; /*Start a DMA transfer */N unsigned dmb$v_rx2_dma_pte : 1; /*PTE address */N unsigned dmb$v_rx2_dma_phys : 1; /*Physical address */N unsigned dmb$v_rx2_x21 : 1; /*X.21 mode */* unsigned dmbdef$ $_fill_26 : 4;N unsigned dmb$v_rx2_dma_abort : 1; /*Receiver DMA abort */+ unsigned dmbdef$$_fill_27 : 15;N char dmb$b_rx2_error; /*Receiver error bits */" } dmb$r_rlnctrl2_bits;! } dmb$r_rlnctrl2_overlay; __union {N unsigned int dmb$l_lpr3; /*Sync Line parameters 3 */ __struct {N char dmb$b_sync_char; /*Sync character */N ch ar dmb$b_rx_match; /*Receive match character */N char dmb$b_address1; /*First address character */N char dmb$b_address2; /*Second address character */ } dmb$r_lpr3_fields; } dmb$r_lpr3_overlay; __union {N unsigned int dmb$l_bufctrl; /*Sync Buffer Control Bits */ __struct {N char dmb$b_tx_buff_prio; /*Transmitter Buf. Priority */N char dmb$b_rx_buff_prio; /*Receiver Buffer Priority */N char dmb$b_sync_test_input; /*Test inputs */N unsigned dmb$v_sync_cable : 4; /*Electrical Configuration */* unsigned dmbdef$$_fill_28 : 1;N unsigned dmb$v_sync_loop : 1; /*Loopback present */N unsigned dmb$v_sync_valid : 1; /*Valid cable */N unsigned dmb$v_sync_x21 : 1; /*X.21 Mode */ ! } dmb$r_bufctrl_bits; } dmb$r_bufctrl_overlay;N/* */N/* The next 10 registers are for the async port on the DMB32 */N/* */ __union {N unsigned int dmb$l_preempt; /*Preempt Buffer */ __struct {N char dmb$b_preempt_char; /*Character to Transmit */* unsigned dmbdef$$_fill_29 : 7;N unsigned dmb$v_preempt_go : 1; /*Start Preempt */! } dmb$r_preempt_bits; } dmb$r_preempt_overlay;N void *dmb$l_tbuffad; /*Transmit Buffer Address */ __union {N unsigned int dmb$l_tbuffct; /*Transmit Buffer Count-Offset */ __struct {N short int dmb$w_tx_buff_off; /*Transmit Buffer Offset */N short int dmb$w_tx _char_ct; /*Transmit Buffer Count */# } dmb$r_tbuffct_fields; } dmb$r_tbuffct_overlay; __union {N unsigned int dmb$l_lpr; /*Line parameter register */ __struct {N unsigned dmb$v_ml : 1; /*Modem Loop */N unsigned dmb$v_dtr : 1; /*Data Terminal Ready */N unsigned dmb$v_drs : 1; /*Data Rate Select */* unsigned dmbde!f$$_fill_30 : 1;N unsigned dmb$v_rts : 1; /*Request to Send */* unsigned dmbdef$$_fill_31 : 4;N unsigned dmb$v_tx_int_delay : 1; /*Transmit Interrupt Control */N unsigned dmb$v_rx_ena : 1; /*Receiver Enable */N unsigned dmb$v_break : 1; /*Break control */N unsigned dmb$v_maint : 2; /*Maintenance Mode */N unsigned dmb$v_report_modem : 1;" /*Report Modem changes */P unsigned dmb$v_discard_flow : 1; /*Discard flow contr. characters */N unsigned dmb$v_char_length : 2; /*character length */N unsigned dmb$v_parity_enab : 1; /*Parity enable */N unsigned dmb$v_even_parity : 1; /*Even parity */N unsigned dmb$v_stop_code : 1; /*Stop code */N unsigned dmb$v_use_cts : 1; /*CTS controls output # */N unsigned dmb$v_iauto_flow : 1; /*Auto f.c. of incoming data */N unsigned dmb$v_oauto_flow : 1; /*Auto f.c. of outgoing data */N unsigned dmb$v_rx_speed : 4; /*Received data speed */N unsigned dmb$v_tx_speed : 4; /*Transmitted data rate */ } dmb$r_lpr_bits; } dmb$r_lpr_overlay; __union {N unsigned int dmb$l_lnctrl; /*Line Control */ __struct $ {N unsigned dmb$v_tx_dma_start : 1; /*Start a DMA transfer */N unsigned dmb$v_tx_dma_pte : 1; /*PTE address */N unsigned dmb$v_tx_dma_phys : 1; /*Physical address */* unsigned dmbdef$$_fill_32 : 5;N unsigned dmb$v_tx_out_abort : 1; /*Transmitter output abort */* unsigned dmbdef$$_fill_33 : 7;N char dmb$b_tx_error; /*Transmitter error bits */* %unsigned dmbdef$$_fill_34 : 1;' unsigned dmb$v_fill_5_ : 7; } dmb$r_lnctrl_bits; } dmb$r_lnctrl_overlay; __union {N unsigned int dmb$l_lstat; /*Line status register */ __struct {+ unsigned dmbdef$$_fill_35 : 10;N unsigned dmb$v_ml2 : 1; /*Spare modem control lead */* unsigned dmbdef$$_fill_36 : 1;N unsigned dmb$v_cts : 1; /*Clear to send &*/N unsigned dmb$v_dcd : 1; /*Data carrier detected */N unsigned dmb$v_ri : 1; /*Ring indicator */N unsigned dmb$v_dsr : 1; /*Data set ready */* unsigned dmbdef$$_fill_37 : 7;N unsigned dmb$v_sndoff : 1; /*Send XOFF */* unsigned dmbdef$$_fill_38 : 7;N unsigned dmb$v_tx_ena : 1; /*Transmitter enable */ } 'dmb$r_lstat_bits; } dmb$r_lstat_overlay; __union {N unsigned int dmb$l_flowc; /*Flow control characters */ __struct {N char dmb$b_sent_xoff; /*Transmitted XOFF */N char dmb$b_sent_xon; /*Transmitted XON */N char dmb$b_received_xoff; /*Received XOFF */N char dmb$b_received_xon; /*Received XON */! } dm (b$r_flowc_fields; } dmb$r_flowc_overlay; int dmbdef$$_fill_39 [10]; __union {N unsigned int dmb$l_tbuf; /*Transmit completion fifo */ __struct {N char dmb$b_tx_line; /*Transmit line number */N unsigned dmb$v_tx_preempt : 1; /*Preempt completed */N unsigned dmb$v_tx_fifo_done : 1; /*fifo empty */* unsigned dmbdef$$_fill_40 : 6;N char dmb )$b_tx_dma_error; /*Transmit error code */* unsigned dmbdef$$_fill_41 : 7;N unsigned dmb$v_tx_act : 1; /*Transmitter action */ } dmb$r_tbuf_bits; } dmb$r_tbuf_overlay; __union {N unsigned int dmb$l_sbuf; /*Sync line completion fifo */ __struct {N char dmb$b_sync_line; /*Sync line number */N unsigned dmb$v_sync_modem : 1; /*Modem change * */N unsigned dmb$v_sync_tx_act : 1; /*Sync Transmit complete */N unsigned dmb$v_sync_second_buffer : 1; /*buffer number */N unsigned dmb$v_sbuf_spare : 5; /* */N __union { /* */N char dmb$b_sync_modem_status; /*Sync line new modem status */N char dmb$b_sync_error; /*Sync line error code */ + } dmb$r_sbuf_x; } dmb$r_sbuf_bits; } dmb$r_sbuf_overlay; __union {N unsigned int dmb$l_rbuf; /*Async Receiver Buffer */ __struct {N char dmb$b_rxchar; /*Received character */* unsigned dmbdef$$_fill_42 : 4;N unsigned dmb$v_parity_err : 1; /*Parity error */N unsigned dmb$v_frame_err : 1; /*Framing error */N ,unsigned dmb$v_overrun_err : 1; /*Overrun error */N unsigned dmb$v_non_char : 1; /*non character data */N char dmb$b_rx_line; /*Receive line number */* unsigned dmbdef$$_fill_43 : 7;N unsigned dmb$v_data_valid : 1; /*Data valid */ } dmb$r_rbuf_bits; } dmb$r_rbuf_overlay; } DMB; #if !defined(__VAXC)3#define dmb$l_maint dmb$r_maint_overlay.dmb$l_maint-N#define dmb$v_force_fail dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_force_failT#define dmb$v_program_reset dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_program_resetL#define dmb$v_pte_valid dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_pte_validT#define dmb$v_skip_selftest dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_skip_selftestR#define dmb$v_maint_level1 dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_maint_level1R#define dmb$v_maint_level2 dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_maint_level2B#defin.e dmb$v_sync dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_syncD#define dmb$v_async dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_asyncD#define dmb$v_print dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_printL#define dmb$v_diag_fail dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_diag_failP#define dmb$v_x21_support dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_x21_supportL#define dmb$v_cable_key dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_cable_keyL#define dmb$v_turn_conn dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v /_turn_connL#define dmb$v_manf_conn dmb$r_maint_overlay.dmb$r_maint_bits.dmb$v_manf_conn0#define dmb$l_acsr dmb$r_acsr_overlay.dmb$l_acsrR#define dmb$b_async_ind_add dmb$r_acsr_overlay.dmb$r_acsr_bits.dmb$b_async_ind_addD#define dmb$v_rx_i_e dmb$r_acsr_overlay.dmb$r_acsr_bits.dmb$v_rx_i_eD#define dmb$v_tx_i_e dmb$r_acsr_overlay.dmb$r_acsr_bits.dmb$v_tx_i_e0#define dmb$l_scsr dmb$r_scsr_overlay.dmb$l_scsrP#define dmb$b_sync_ind_add dmb$r_scsr_overlay.dmb$r_scsr_bits.dmb$b_sync_ind_addH#define dm0b$v_sync_i_e dmb$r_scsr_overlay.dmb$r_scsr_bits.dmb$v_sync_i_e0#define dmb$l_pcsr dmb$r_pcsr_overlay.dmb$l_pcsrD#define dmb$v_pr_i_e dmb$r_pcsr_overlay.dmb$r_pcsr_bits.dmb$v_pr_i_eT#define dmb$v_pr_davfu_ready dmb$r_pcsr_overlay.dmb$r_pcsr_bits.dmb$v_pr_davfu_readyZ#define dmb$v_pr_connect_verify dmb$r_pcsr_overlay.dmb$r_pcsr_bits.dmb$v_pr_connect_verifyL#define dmb$v_pr_offline dmb$r_pcsr_overlay.dmb$r_pcsr_bits.dmb$v_pr_offline6#define dmb$l_config dmb$r_config_overlay.dmb$l_configT#define dm1b$b_async_lines dmb$r_config_overlay.dmb$r_config_fields.dmb$b_async_linesR#define dmb$b_sync_lines dmb$r_config_overlay.dmb$r_config_fields.dmb$b_sync_linesX#define dmb$b_printer_lines dmb$r_config_overlay.dmb$r_config_fields.dmb$b_printer_lines3#define dmb$l_acsr2 dmb$r_acsr2_overlay.dmb$l_acsr2P#define dmb$v_async_reset dmb$r_acsr2_overlay.dmb$r_acsr2_bits.dmb$v_async_resetJ#define dmb$b_rx_timer dmb$r_acsr2_overlay.dmb$r_acsr2_bits.dmb$b_rx_timer3#define dmb$l_scsr2 dmb$r_scsr2_overlay.dmb$2l_scsr2N#define dmb$v_sync_reset dmb$r_scsr2_overlay.dmb$r_scsr2_bits.dmb$v_sync_reset3#define dmb$l_pcsr2 dmb$r_pcsr2_overlay.dmb$l_pcsr2T#define dmb$v_printer_reset dmb$r_pcsr2_overlay.dmb$r_pcsr2_bits.dmb$v_printer_reset0#define dmb$l_pfix dmb$r_pfix_overlay.dmb$l_pfixR#define dmb$b_prefix_count dmb$r_pfix_overlay.dmb$r_pfix_fields.dmb$b_prefix_countP#define dmb$b_prefix_char dmb$r_pfix_overlay.dmb$r_pfix_fields.dmb$b_prefix_charR#define dmb$b_suffix_count dmb$r_pfix_overlay.dmb$r_pfix_fie3lds.dmb$b_suffix_countP#define dmb$b_suffix_char dmb$r_pfix_overlay.dmb$r_pfix_fields.dmb$b_suffix_char6#define dmb$l_pbufct dmb$r_pbufct_overlay.dmb$l_pbufctT#define dmb$w_pr_buff_off dmb$r_pbufct_overlay.dmb$r_pbufct_fields.dmb$w_pr_buff_offR#define dmb$w_pr_buff_ct dmb$r_pbufct_overlay.dmb$r_pbufct_fields.dmb$w_pr_buff_ct3#define dmb$l_pctrl dmb$r_pctrl_overlay.dmb$l_pctrlR#define dmb$v_pr_dma_start dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_dma_startN#define dmb$v_pr_dma_pte dmb$r_pctrl4_overlay.dmb$r_pctrl_bits.dmb$v_pr_dma_pteP#define dmb$v_pr_dma_phys dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_dma_physR#define dmb$v_pr_dma_abort dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_dma_abortL#define dmb$v_pr_format dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_formatJ#define dmb$b_pr_error dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$b_pr_errorF#define dmb$v_pr_tab dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_tabJ#define dmb$v_pr_trunc dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_t5runcV#define dmb$v_pr_auto_return dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_auto_returnR#define dmb$v_pr_auto_form dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_auto_formR#define dmb$v_pr_non_print dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_non_printJ#define dmb$v_pr_davfu dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_davfuH#define dmb$v_pr_wrap dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_wrapJ#define dmb$v_pr_upper dmb$r_pctrl_overlay.dmb$r_pctrl_bits.dmb$v_pr_upper0#define dmb$l_pcar6 dmb$r_pcar_overlay.dmb$l_pcarH#define dmb$w_pr_line dmb$r_pcar_overlay.dmb$r_pcar_fields.dmb$w_pr_lineH#define dmb$w_pr_char dmb$r_pcar_overlay.dmb$r_pcar_fields.dmb$w_pr_char3#define dmb$l_psize dmb$r_psize_overlay.dmb$l_psizeL#define dmb$w_pr_width dmb$r_psize_overlay.dmb$r_psize_fields.dmb$w_pr_widthJ#define dmb$w_pr_page dmb$r_psize_overlay.dmb$r_psize_fields.dmb$w_pr_page<#define dmb$l_tbuffct1 dmb$r_tbuffct1_overlay.dmb$l_tbuffct1Z#define dmb$w_tx_buff_off1 dmb$r_tbuffct1_overlay.dmb$r_7tbuffct1_fields.dmb$w_tx_buff_off1X#define dmb$w_tx_char_ct1 dmb$r_tbuffct1_overlay.dmb$r_tbuffct1_fields.dmb$w_tx_char_ct1<#define dmb$l_rbuffct1 dmb$r_rbuffct1_overlay.dmb$l_rbuffct1Z#define dmb$w_rx_buff_off1 dmb$r_rbuffct1_overlay.dmb$r_rbuffct1_fields.dmb$w_rx_buff_off1X#define dmb$w_rx_char_ct1 dmb$r_rbuffct1_overlay.dmb$r_rbuffct1_fields.dmb$w_rx_char_ct1<#define dmb$l_tlnctrl1 dmb$r_tlnctrl1_overlay.dmb$l_tlnctrl1Z#define dmb$v_tx1_dma_start dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb8$v_tx1_dma_startV#define dmb$v_tx1_dma_pte dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$v_tx1_dma_pteX#define dmb$v_tx1_dma_phys dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$v_tx1_dma_physN#define dmb$v_tx1_x21 dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$v_tx1_x21N#define dmb$v_tx1_par dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$v_tx1_parZ#define dmb$v_tx1_dma_abort dmb$r_tlnctrl1_overlay.dmb$r_tlnctrl1_bits.dmb$v_tx1_dma_abortR#define dmb$b_tx1_error dmb$r_tlnctrl1_overlay.dmb$r_tlnct9rl1_bits.dmb$b_tx1_error<#define dmb$l_rlnctrl1 dmb$r_rlnctrl1_overlay.dmb$l_rlnctrl1Z#define dmb$v_rx1_dma_start dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bits.dmb$v_rx1_dma_startV#define dmb$v_rx1_dma_pte dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bits.dmb$v_rx1_dma_pteX#define dmb$v_rx1_dma_phys dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bits.dmb$v_rx1_dma_physN#define dmb$v_rx1_x21 dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bits.dmb$v_rx1_x21Z#define dmb$v_rx1_dma_abort dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bi:ts.dmb$v_rx1_dma_abortR#define dmb$b_rx1_error dmb$r_rlnctrl1_overlay.dmb$r_rlnctrl1_bits.dmb$b_rx1_error0#define dmb$l_lpr1 dmb$r_lpr1_overlay.dmb$l_lpr1J#define dmb$v_rx_enable dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_rx_enableP#define dmb$v_rx_match_ena dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_rx_match_enaL#define dmb$v_rx_primary dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_rx_primaryJ#define dmb$v_x21enable dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_x21enableR#define dmb$v_clock_control dmb$r_lp;r1_overlay.dmb$r_lpr1_bits.dmb$v_clock_controlN#define dmb$v_coding_type dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_coding_typeJ#define dmb$v_baud_rate dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_baud_rate@#define dmb$v_loop dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_loopL#define dmb$v_v35_select dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_v35_selectL#define dmb$v_v10_select dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_v10_selectT#define dmb$v_modem_suppress dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_modem_supp<ressN#define dmb$b_number_sync dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$b_number_syncL#define dmb$v_line_reset dmb$r_lpr1_overlay.dmb$r_lpr1_bits.dmb$v_line_reset0#define dmb$l_lpr2 dmb$r_lpr2_overlay.dmb$l_lpr2H#define dmb$v_sync_ml1 dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_ml1H#define dmb$v_sync_dtr dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_dtrH#define dmb$v_sync_drs dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_drsH#define dmb$v_sync_ml2 dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_m=l2H#define dmb$v_sync_rts dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_rtsN#define dmb$v_spare_modem dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_spare_modemP#define dmb$v_sync_rxclock dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_rxclockP#define dmb$v_sync_txclock dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_txclockF#define dmb$v_sync_ti dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_tiH#define dmb$v_sync_cts dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_ctsH#define dmb$v_sync_dcd dmb$r_lpr2_over>lay.dmb$r_lpr2_bits.dmb$v_sync_dcdF#define dmb$v_sync_ri dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_riH#define dmb$v_sync_dsr dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_sync_dsrH#define dmb$v_protocol dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_protocolL#define dmb$v_error_type dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_error_typeD#define dmb$v_rx_bpc dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_rx_bpcD#define dmb$v_tx_bpc dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_tx_bpcL#define dmb$v_strip_sync dmb$r_l?pr2_overlay.dmb$r_lpr2_bits.dmb$v_strip_syncN#define dmb$v_ebcdic_code dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_ebcdic_codeJ#define dmb$v_idle_sync dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_idle_syncT#define dmb$v_modem_override dmb$r_lpr2_overlay.dmb$r_lpr2_bits.dmb$v_modem_override<#define dmb$l_tbuffct2 dmb$r_tbuffct2_overlay.dmb$l_tbuffct2Z#define dmb$w_tx_buff_off2 dmb$r_tbuffct2_overlay.dmb$r_tbuffct2_fields.dmb$w_tx_buff_off2X#define dmb$w_tx_char_ct2 dmb$r_tbuffct2_overlay.dmb$r_tbuffct2_@fields.dmb$w_tx_char_ct2<#define dmb$l_rbuffct2 dmb$r_rbuffct2_overlay.dmb$l_rbuffct2Z#define dmb$w_rx_buff_off2 dmb$r_rbuffct2_overlay.dmb$r_rbuffct2_fields.dmb$w_rx_buff_off2X#define dmb$w_rx_char_ct2 dmb$r_rbuffct2_overlay.dmb$r_rbuffct2_fields.dmb$w_rx_char_ct2<#define dmb$l_tlnctrl2 dmb$r_tlnctrl2_overlay.dmb$l_tlnctrl2Z#define dmb$v_tx2_dma_start dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_dma_startV#define dmb$v_tx2_dma_pte dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_dmaA_pteX#define dmb$v_tx2_dma_phys dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_dma_physN#define dmb$v_tx2_x21 dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_x21N#define dmb$v_tx2_par dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_parZ#define dmb$v_tx2_dma_abort dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$v_tx2_dma_abortR#define dmb$b_tx2_error dmb$r_tlnctrl2_overlay.dmb$r_tlnctrl2_bits.dmb$b_tx2_error<#define dmb$l_rlnctrl2 dmb$r_rlnctrl2_overlay.dmb$l_rlnctrl2Z#define dmb$Bv_rx2_dma_start dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$v_rx2_dma_startV#define dmb$v_rx2_dma_pte dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$v_rx2_dma_pteX#define dmb$v_rx2_dma_phys dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$v_rx2_dma_physN#define dmb$v_rx2_x21 dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$v_rx2_x21Z#define dmb$v_rx2_dma_abort dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$v_rx2_dma_abortR#define dmb$b_rx2_error dmb$r_rlnctrl2_overlay.dmb$r_rlnctrl2_bits.dmb$b_rx2C_error0#define dmb$l_lpr3 dmb$r_lpr3_overlay.dmb$l_lpr3L#define dmb$b_sync_char dmb$r_lpr3_overlay.dmb$r_lpr3_fields.dmb$b_sync_charJ#define dmb$b_rx_match dmb$r_lpr3_overlay.dmb$r_lpr3_fields.dmb$b_rx_matchJ#define dmb$b_address1 dmb$r_lpr3_overlay.dmb$r_lpr3_fields.dmb$b_address1J#define dmb$b_address2 dmb$r_lpr3_overlay.dmb$r_lpr3_fields.dmb$b_address29#define dmb$l_bufctrl dmb$r_bufctrl_overlay.dmb$l_bufctrlV#define dmb$b_tx_buff_prio dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$b_tx_buff_DprioV#define dmb$b_rx_buff_prio dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$b_rx_buff_prio\#define dmb$b_sync_test_input dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$b_sync_test_inputR#define dmb$v_sync_cable dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$v_sync_cableP#define dmb$v_sync_loop dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$v_sync_loopR#define dmb$v_sync_valid dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$v_sync_validN#define dmb$v_sync_x21 dmb$r_bufctrl_overlay.dmb$r_bufctrl_bits.dmb$Ev_sync_x219#define dmb$l_preempt dmb$r_preempt_overlay.dmb$l_preemptV#define dmb$b_preempt_char dmb$r_preempt_overlay.dmb$r_preempt_bits.dmb$b_preempt_charR#define dmb$v_preempt_go dmb$r_preempt_overlay.dmb$r_preempt_bits.dmb$v_preempt_go9#define dmb$l_tbuffct dmb$r_tbuffct_overlay.dmb$l_tbuffctV#define dmb$w_tx_buff_off dmb$r_tbuffct_overlay.dmb$r_tbuffct_fields.dmb$w_tx_buff_offT#define dmb$w_tx_char_ct dmb$r_tbuffct_overlay.dmb$r_tbuffct_fields.dmb$w_tx_char_ct-#define dmb$l_lpr dmb$r_lpr_ Foverlay.dmb$l_lpr:#define dmb$v_ml dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_ml<#define dmb$v_dtr dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_dtr<#define dmb$v_drs dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_drs<#define dmb$v_rts dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_rtsN#define dmb$v_tx_int_delay dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_tx_int_delayB#define dmb$v_rx_ena dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_rx_ena@#define dmb$v_break dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_break@#define dmb$v_maint dmb$r_Glpr_overlay.dmb$r_lpr_bits.dmb$v_maintN#define dmb$v_report_modem dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_report_modemN#define dmb$v_discard_flow dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_discard_flowL#define dmb$v_char_length dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_char_lengthL#define dmb$v_parity_enab dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_parity_enabL#define dmb$v_even_parity dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_even_parityH#define dmb$v_stop_code dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_stop_codeHD#define dmb$v_use_cts dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_use_ctsJ#define dmb$v_iauto_flow dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_iauto_flowJ#define dmb$v_oauto_flow dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_oauto_flowF#define dmb$v_rx_speed dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_rx_speedF#define dmb$v_tx_speed dmb$r_lpr_overlay.dmb$r_lpr_bits.dmb$v_tx_speed6#define dmb$l_lnctrl dmb$r_lnctrl_overlay.dmb$l_lnctrlT#define dmb$v_tx_dma_start dmb$r_lnctrl_overlay.dmb$r_lnctrl_bits.dmb$v_tx_dma_staIrtP#define dmb$v_tx_dma_pte dmb$r_lnctrl_overlay.dmb$r_lnctrl_bits.dmb$v_tx_dma_pteR#define dmb$v_tx_dma_phys dmb$r_lnctrl_overlay.dmb$r_lnctrl_bits.dmb$v_tx_dma_physT#define dmb$v_tx_out_abort dmb$r_lnctrl_overlay.dmb$r_lnctrl_bits.dmb$v_tx_out_abortL#define dmb$b_tx_error dmb$r_lnctrl_overlay.dmb$r_lnctrl_bits.dmb$b_tx_error3#define dmb$l_lstat dmb$r_lstat_overlay.dmb$l_lstat@#define dmb$v_ml2 dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_ml2@#define dmb$v_cts dmb$r_lstat_overlay.dmb$r_lstat_bi Jts.dmb$v_cts@#define dmb$v_dcd dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_dcd>#define dmb$v_ri dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_ri@#define dmb$v_dsr dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_dsrF#define dmb$v_sndoff dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_sndoffF#define dmb$v_tx_ena dmb$r_lstat_overlay.dmb$r_lstat_bits.dmb$v_tx_ena3#define dmb$l_flowc dmb$r_flowc_overlay.dmb$l_flowcN#define dmb$b_sent_xoff dmb$r_flowc_overlay.dmb$r_flowc_fields.dmb$b_sent_xoffL#define dmb$b_sentK_xon dmb$r_flowc_overlay.dmb$r_flowc_fields.dmb$b_sent_xonV#define dmb$b_received_xoff dmb$r_flowc_overlay.dmb$r_flowc_fields.dmb$b_received_xoffT#define dmb$b_received_xon dmb$r_flowc_overlay.dmb$r_flowc_fields.dmb$b_received_xon0#define dmb$l_tbuf dmb$r_tbuf_overlay.dmb$l_tbufF#define dmb$b_tx_line dmb$r_tbuf_overlay.dmb$r_tbuf_bits.dmb$b_tx_lineL#define dmb$v_tx_preempt dmb$r_tbuf_overlay.dmb$r_tbuf_bits.dmb$v_tx_preemptP#define dmb$v_tx_fifo_done dmb$r_tbuf_overlay.dmb$r_tbuf_bits.dmb$v_tx_fLifo_doneP#define dmb$b_tx_dma_error dmb$r_tbuf_overlay.dmb$r_tbuf_bits.dmb$b_tx_dma_errorD#define dmb$v_tx_act dmb$r_tbuf_overlay.dmb$r_tbuf_bits.dmb$v_tx_act0#define dmb$l_sbuf dmb$r_sbuf_overlay.dmb$l_sbufJ#define dmb$b_sync_line dmb$r_sbuf_overlay.dmb$r_sbuf_bits.dmb$b_sync_lineL#define dmb$v_sync_modem dmb$r_sbuf_overlay.dmb$r_sbuf_bits.dmb$v_sync_modemN#define dmb$v_sync_tx_act dmb$r_sbuf_overlay.dmb$r_sbuf_bits.dmb$v_sync_tx_act\#define dmb$v_sync_second_buffer dmb$r_sbuf_overlay.dmb$r_sb Muf_bits.dmb$v_sync_second_bufferL#define dmb$v_sbuf_spare dmb$r_sbuf_overlay.dmb$r_sbuf_bits.dmb$v_sbuf_spareD#define dmb$r_sbuf_x dmb$r_sbuf_overlay.dmb$r_sbuf_bits.dmb$r_sbuf_xD#define dmb$b_sync_modem_status dmb$r_sbuf_x.dmb$b_sync_modem_status6#define dmb$b_sync_error dmb$r_sbuf_x.dmb$b_sync_error0#define dmb$l_rbuf dmb$r_rbuf_overlay.dmb$l_rbufD#define dmb$b_rxchar dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$b_rxcharL#define dmb$v_parity_err dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$v_parity_errJ N#define dmb$v_frame_err dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$v_frame_errN#define dmb$v_overrun_err dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$v_overrun_errH#define dmb$v_non_char dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$v_non_charF#define dmb$b_rx_line dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$b_rx_lineL#define dmb$v_data_valid dmb$r_rbuf_overlay.dmb$r_rbuf_bits.dmb$v_data_valid"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined Owhenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DMBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/MP/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software lQicensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************** R*****************************************************************************/=/* Created: 7-Oct-2024 15:23:33 by OpenVMS SDL V3.7 */F/* Source: 29-JUN-2022 19:45:28 $1$DGA8345:[LIB_H.SRC]DMPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DMPDEF ***/#ifndef __DMPDEF_LOADED#define __DMPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!S#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_parTams ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include P/* */P/* The invocation context block is defined in STARLET, and may materialize */P/* as a typedef or as a struct, dependinUg on whether or not the user of this */P/* module has defined __NEW_STARLET. However, the DMP_IMGDMP_ICB structure */P/* in which it is embedded is declared here as a typedef, meaning that SDL */P/* will generate a reference to the typedef name INVO_CONTEXT_BLK. If */P/* __NEW_STARLET is not enabled, we define the missing INVO_CONTEXT_BLK */P/* to be the equivalent struct reference. */P/* V */#include #ifndef __NEW_STARLET1typedef struct invo_context_blk INVO_CONTEXT_BLK;#endifN/* */N/* LAYOUT OF THE HEADER BLOCK OF THE SYSTEM DUMP FILE */N/* (WHICH IS THE FIRST TWO DISK BLOCKS OF SYS$SYSTEM:SYSDUMP.DMP) */N/* */#define DMP$M_OLDDUMP 0x1#define DMP$M_EMPTY 0x2W#define DMP$M_HDRBLK 0x4#define DMP$M_ERRLOG 0x8#define DMP$M_MEMORY 0x10#define DMP$M_STUB 0x20#define DMP$M_WRITECOMP 0x40#define DMP$M_ERRLOGCOMP 0x80#define DMP$M_TRAP_VALID 0x100#define DMP$M_ORIGINAL 0x200#define DMP$M_COLLECT 0x400#define DMP$M_PARTIAL 0x800#define DMP$M_X86_64DUMP 0x1000#define DMP$M_BITS_13_14 0x6000#define DMP$M_I64DUMP 0x8000 #define DMP$M_COMPRESSED 0x10000#define DMP$M_NOTSAVED 0x20000#define DMP$M_VAXDUMP 0x40000#define DMP$M_ALPHXADUMP 0x80000!#define DMP$M_BAD4GBDUMP 0x100000#define DMP$M_MODIFIED 0x200000 #define DMP$M_SHMEMDUMP 0x400000#define DMP$M_PROCDUMP 0x800000##define DMP$M_BITS_24_28 0x1F000000!#define DMP$M_EXCLDATA 0x20000000#define DMP$M_FEN 0xC0000000#define DMP$M_FEN_MFL 1#define DMP$M_FEN_MFH 2#define DMP$M_DUMPSTYLE 0x1#define DMP$M_FULL_MESSAGES 0x2#define DMP$M_DO_DOSD 0x4#define DMP$M_COMPRESS 0x8#define DMP$M_SKIP_SHARED 0x10#define DMP$M_KEY_ONLY 0x20#define DMP$M_YSKIP_S2 0x40#define DMP$M_INTERLEAVED 0x80#define DMP$M_BITS_8_9 0x300!#define DMP$M_SUPER_VERBOSE 0x400 #define DMP$M_SKIP_SYSDISK 0x800 #define DMP$M_DO_GLXFATAL 0x1000&#define DMP$M_DISABLE_GLXRMTPFN 0x2000'#define DMP$M_ALLOW_HBVS_DUMPDEV 0x4000#define DMP$M_DATACHECK 0x8000#define DMP$M_SKIP_INIT 0x10000#define DMP$M_TR_BUFFER 0x20000 #define DMP$M_SPL_BUFFER 0x40000!#define DMP$M_BITS_19_23 0xF80000'#define DMP$M_MEM_STACK_PAGES 0xF000000(#define DMP$M_REG_STACK_PAGES 0x ZF0000000O#define DMP$K_DEFAULT_MEM_STACK_PAGES 1 /* Default memory stack size for x86 */N/* (enough to get the dump kernel started) */N#define DMP$K_DUMPVER 2561 /* DUMP FILE VERSION NUMBER */N#define DMP$K_PROCVER 769 /* PROCESS DUMP FILE VERSION NUMBER */T#define DMP$K_SHMEMVER 769 /* SHARED MEMORY DUMP FILE VERSION NUMBER */N#define DMP$K_LENGTH 1024 /* Length of dump header */ type [def struct _dmp {N unsigned int dmp$l_errseq; /* LAST ERROR LOG SEQ. NUMBER */ __union {Z unsigned int dmp$l_flags; /* DUMP FILE FLAGS **** KEEP AT OFFSET 4. **** */ __struct {N unsigned dmp$v_olddump : 1; /* SET IF DUMP ALREADY ANALYZED */N unsigned dmp$v_empty : 1; /* SET IF DUMP HAS NO DATA BLOCKS */N unsigned dmp$v_hdrblk : 1; /* SET IF ERROR WRITING DUMP HEADER */Z unsigned dmp$v_errlog : \1; /* SET IF ERROR WRITING ERROR LOGS TO DUMP FILE */_ unsigned dmp$v_memory : 1; /* SET IF ERROR WRITING MEMORY CONTENTS TO DUMP FILE */Q unsigned dmp$v_stub : 1; /* SET IF SYS$ERRLOG.DMP BEING WRITTEN */O unsigned dmp$v_writecomp : 1; /* SET IF DUMP WRITE WAS COMPLETED */] unsigned dmp$v_errlogcomp : 1; /* SET IF HEADER/ERROR LOGS WRITE WAS COMPLETED */N unsigned dmp$v_trap_valid : 1; /* Set if a trap happened */S ] unsigned dmp$v_original : 1; /* Set by BUGCHECK, cleared by SDA COPY */N unsigned dmp$v_collect : 1; /* Set if a COLLECT/SAVE file */l unsigned dmp$v_partial : 1; /* Set if a partial dump not including error logs, PT space, etc, */` unsigned dmp$v_x86_64dump : 1; /* Set for X86-64 dumps **** KEEP AT BIT 12. **** */g unsigned dmp$v_bits_13_14 : 2; /* Spare to keep bits in old FLAGS2 in matching positions */[ unsigned dmp$v_i64dump :^ 1; /* Set for IA64 dumps **** KEEP AT BIT 15. **** */^ unsigned dmp$v_compressed : 1; /* SET IF DUMP DATA IS COMPRESSED (in this copy) */j unsigned dmp$v_notsaved : 1; /* Set by SYSINIT if SAVEDUMP not set and dump in PAGEFILE.SYS */S unsigned dmp$v_vaxdump : 1; /* Never set **** KEEP AT BIT 18. **** */^ unsigned dmp$v_alphadump : 1; /* Set for Alpha dumps **** KEEP AT BIT 19. **** */u unsigned dmp$v_bad4gbdump : 1; /* Set if memory ab_ove 4GB written directly (no buffer pages available) */T unsigned dmp$v_modified : 1; /* Dump has been modified with /OVERRIDE */c unsigned dmp$v_shmemdump : 1; /* Galaxy Shared Memory Dump **** KEEP AT BIT 22. **** */W unsigned dmp$v_procdump : 1; /* Process dump **** KEEP AT BIT 23. **** */N unsigned dmp$v_bits_24_28 : 5; /* Spare */N/* Remaining bits are specific to process dumps */i ` unsigned dmp$v_excldata : 1; /* Set if data wasn't saved because of insufficient privilege */O unsigned dmp$v_fen : 2; /* Set if FEN was set in the process */N/* (1 bit used on Alpha, both on IPF. Not used on X86, MBZ) */ } dmp$r_flags_bits; } dmp$r_flags_overlay; __union {e unsigned int dmp$l_dumpstyle; /* Setting of SYSGEN parameter DUMPSTYLE when dump written */S __struct { /* (handcrafted valuae for process dumps) */r unsigned dmp$v_dumpstyle : 1; /* Full vs. Selective (ignored on X86: Selective or Interleaved only) */V unsigned dmp$v_full_messages : 1; /* Minimal console output vs. Verbose */X unsigned dmp$v_do_dosd : 1; /* System disk vs. DOSD disk (ignored on X86) */r unsigned dmp$v_compress : 1; /* Raw vs. Compressed (for the original dump, ignored for Interleaved) */k unsigned dmp$v_skip_shared : 1; /* Dump shared memory vs. bdon't dump. (Not used on X86, MBZ) */f unsigned dmp$v_key_only : 1; /* Only dump system space, key processes, key global pages */Y unsigned dmp$v_skip_s2 : 1; /* Don't dump S2 space. (Not used on X86, MBZ) */_ unsigned dmp$v_interleaved : 1; /* Interleaved Dump (Only on X86, otherwise MBZ) */X unsigned dmp$v_bits_8_9 : 2; /* Spare bits for future documented features */N unsigned dmp$v_super_verbose : 1; /* Diagnostics */N c unsigned dmp$v_skip_sysdisk : 1; /* Don't touch system disk */N unsigned dmp$v_do_glxfatal : 1; /* Force Galaxy-wide crash */X unsigned dmp$v_disable_glxrmtpfn : 1; /* Disable Galaxy remote PFN checks */[ unsigned dmp$v_allow_hbvs_dumpdev : 1; /* Allow DOSD to be shadow set member */X unsigned dmp$v_datacheck : 1; /* Do a datacheck read after each write I/O */l unsigned dmp$v_skip_init : 1; /* Don't fill in the SCB/IDT (i.de. primitive exception display) */N/* **** Note: SKIP_INIT is not dynamic in SYSGEN!!!! **** */V unsigned dmp$v_tr_buffer : 1; /* Bit 17 = %x20000: Dump TR_PRINT buffer */R unsigned dmp$v_spl_buffer : 1; /* Bit 18 = %x40000: Dump SPL buffer */\ unsigned dmp$v_bits_19_23 : 5; /* Spare bits for future undocumented features */[ unsigned dmp$v_mem_stack_pages : 4; /* Additional pages for BUGCHECK's stack */q unsigned dmp$v_rege_stack_pages : 4; /* Additional pages for BUGCHECK's stack (only useful on IA64) */N/* Verified for x86 port - Richard Bishop */ } dmp$r_style_bits; } dmp$r_style_overlay;T unsigned short int dmp$w_memmap_entries; /* Entries in memory map (full dump) */P unsigned short int dmp$w_erlbufpages; /* # pagelets / S0 error log buffer */i unsigned __int64 dmp$q_ptbr; /* PAGE TABLE BASE REGISTER (SYSPTBR if VIRBND or IA64 or x86) */fN unsigned __int64 dmp$q_ksp; /* KERNEL STACK POINTER */N unsigned __int64 dmp$q_esp; /* EXECUTIVE STACK POINTER */N unsigned __int64 dmp$q_ssp; /* SUPERVISOR STACK POINTER */N unsigned __int64 dmp$q_usp; /* USER STACK POINTER */b unsigned __int64 dmp$q_sysident; /* TEXT ident for SYS.EXE **** KEEP AT OFFSET 56. **** */N void *dmp$l_erlbufadr; /* Address of S0 error log buffers */b gunsigned short int dmp$w_pagebits; /* Number of bits in page index. (Not used on X86, MBZ) */g unsigned short int dmp$w_va_bits; /* Number of bits in virtual address. (Not used on X86, MBZ) */a void *dmp$l_symvect_va; /* ABSOLUTE VIRTUAL ADDRESS OF SYMBOL VECTOR IN MEMORY */h void *dmp$l_symvect_end; /* ABSOLUTE VIRTUAL ADDRESS OF END OF SYMBOL VECTOR IN MEMORY */\ unsigned int dmp$l_dumpblockcnt; /* COUNT OF BLOCKS DUMPED (not interleaved dumps) */i hunsigned int dmp$l_nocompblockcnt; /* As DUMPBLOCKCNT with no compression (not interleaved dumps) */a unsigned int dmp$l_sysver; /* SYSTEM VERSION NUMBER **** KEEP AT OFFSET 88. **** */e unsigned int dmp$l_check; /* ONES COMPLEMENT OF SYSVER **** KEEP AT OFFSET 92. **** */d unsigned short int dmp$w_dumpver; /* DUMP FILE VERSION NUMBER **** KEEP AT OFFSET 96. **** */N unsigned short int dmp$w_erlbufcnt; /* # S0 error log buffers */f unsigned shoirt int dmp$w_erlbufhead; /* Index of next S0 error log buffer to be written to file */Z unsigned short int dmp$w_erlbuftail; /* Index of next available S0 error log buffer */ __union { __struct {W unsigned __int64 dmp$q_l2_base; /* Crash-time contents of mmg$gq_l2_base */W unsigned __int64 dmp$q_l1_base; /* Crash-time contents of mmg$gq_l1_base */W unsigned __int64 dmp$q_pt_base; /* Crash-time contents of mmg$gq_pt_base */' } dmp$ jr_platform_struct_1a; __struct {Y unsigned __int64 dmp$q_pte_levels; /* Number of page table levels (4 or 5) */N unsigned __int64 dmp$q_max_pfn; /* Contents of MMG$GQ_MAXPFN */m unsigned int dmp$l_lmb_count; /* The number of LMBs in the dump (X86: interleaved only or MBZ) */N unsigned int dmp$l_x86_spare_1; /* Not used on x86 (MBZ) */' } dmp$r_platform_struct_1b;# } dmp$r_platform_overlay_1;N unsigned __iknt64 dmp$q_crashtime; /* Crash date/time */[ unsigned __int64 dmp$q_linktime; /* Link date/time of base image in system dumped */Z void *dmp$l_chfctxadr; /* Base address of CHFCTX block (process dumps) */Z void *dmp$l_call_handl; /* Address of SYS$GL_CALL_HANDL (process dumps) */V void *dmp$l_astdel; /* Address of SYS$GL_ASTDEL (process dumps) */X void *dmp$l_astdel_k; /* Address of SYS$GL_ASTDEL_K (procelss dumps) */O unsigned int dmp$l_errstatus; /* LAST ERROR STATUS FROM DUMP WRITE */O unsigned int dmp$l_dumperrs; /* COUNT OF ERRORS DURING DUMP WRITE */i unsigned int dmp$l_maxcompentries; /* Worst case count of compression map entries in dump */f unsigned int dmp$l_shortblockcnt; /* THE NUMBER OF ADDITIONAL BLOCKS NEEDED FOR COMPLETE DUMP */` unsigned int dmp$l_compentrypages; /* Max # pages mapped by a data compression map entry */T unsigned int dmmp$l_saveprccnt; /* Count of saved processes (subset dump) */S unsigned short int dmp$w_saveradcnt; /* Count of saved RADs (selective dump) */U unsigned short int dmp$w_regioncnt; /* Count of regions dumped (shared memory) */S void *dmp$l_pcbvec; /* Pointer to PCB vector (Process dumps) */a int dmp$l_teb_addr; /* Address of thread environment block (Process dumps) */S unsigned int dmp$l_maxpix; /* Highest process index (Process dumpns) */ unsigned int dmp$l_l1_index; __union {S unsigned int dmp$l_level_width; /* Width of a page table level (not X86) */] unsigned int dmp$l_perf_blocks; /* Number of blocks of performance data (X86 only) */# } dmp$r_platform_overlay_2; void *dmp$l_npagedyn; void *dmp$l_balbase; void *dmp$l_bal_end; unsigned int dmp$l_bslotsz; void *dmp$l_pixbas; void *dmp$l_ktb_address; void *dmp$l_sysphd; void *dmp$l_hpdesc;) unosigned __int64 dmp$q_sys_virt_base;g unsigned __int64 dmp$q_shared_va_ptes; /* Not used on x86 (MBZ). Derived from page table ranges. */$ unsigned __int64 dmp$q_gpt_base;$ unsigned __int64 dmp$q_max_gpte;( unsigned __int64 dmp$q_pfn_database;k unsigned char dmp$b_astsr_asten; /* AST summary register and AST enable bits (process dumps only) */N unsigned char dmp$b_trapinfo_blks; /* # blocks set aside for trap data */P unsigned char dmp$b_crasherl_blks; /* # blocks fopr crash error log entry */h unsigned char dmp$b_imgdmp_icb_blks; /* # blocks used for invocation context (process dumps only) */h unsigned char dmp$b_imgdmp_reg_blks; /* # blocks used for internal registers (process dumps only) */ char dmp$t_spare_bytes [2];N char dmp$t_nodename [9]; /* ASCIC node name */N char dmp$t_procname [16]; /* ASCIC process name */N char dmp$t_modelname [32]; /* ASCIC model name q */N unsigned int dmp$l_bugcode; /* The bugcheck code */\ void *dmp$l_mch_array; /* Address of the mechanism array (process dumps) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *dmp$q_erlbufadr_s2; /* Address of S2 error log buffers */#else% unsigned __int64 dmp$q_erlbufadr_s2;#endifN unsignedr int dmp$l_erlbufpages_s2; /* # pagelets / S2 error log buffer */N unsigned int dmp$l_erlbufcnt_s2; /* # S2 error log buffers */e unsigned int dmp$l_erlbufhead_s2; /* Index of next S2 error log buffer to be written to file */Y unsigned int dmp$l_erlbuftail_s2; /* Index of next available S2 error log buffer */d unsigned int dmp$l_collect_total; /* The total size of the file-ID + unwind-data collection */\ unsigned int dmp$l_collect_disk; /* The size of the dsisk portion of the collection */N/* (a subset of and the final blocks of COLLECT_TOTAL) */q unsigned int dmp$l_keyblockcnt; /* Count of blocks dumped for system space, key processes, key globals */P unsigned int dmp$l_nocompkeycnt; /* As KEYBLOCKCNT with no compression */o unsigned int dmp$l_compentries; /* Count of compression map entries in this (partial copy of a) dump */m unsigned int dmp$l_fragblocks; /* Number of blocks BUGCHECK could use btecause file too fragmented */] int dmp$l_add_pcb_astcnt; /* ASTCNT adjustment required to take process dump */] int dmp$l_add_pcb_biocnt; /* BIOCNT adjustment required to take process dump */] int dmp$l_add_pcb_diocnt; /* DIOCNT adjustment required to take process dump */] int dmp$l_add_jib_bytcnt; /* BYTCNT adjustment required to take process dump */] int dmp$l_add_jib_filcnt; /* FILCNT adjustment required to take process dumpu */\ int dmp$l_add_jib_tqcnt; /* TQCNT adjustment required to take process dump */^ int dmp$l_add_jib_pgflcnt; /* PGFLCNT adjustment required to take process dump */] int dmp$l_add_jib_enqcnt; /* ENQCNT adjustment required to take process dump */` unsigned __int64 dmp$q_add_phd_cpulim; /* CPULIM adjustment required to take process dump */N/* (not yet used, but would be recorded as a delta time) */k unsigned __int64 dmp$q_wslbase; v /* Base address of working set pages in S2 space (process dumps) */j unsigned __int64 dmp$q_wsl_end; /* End address of working set pages in S2 space (process dumps) */b unsigned __int64 dmp$q_process_ptbr [4]; /* PTBRs for process (if one active) at crash time */Y unsigned __int64 dmp$q_dumpblockcnt; /* COUNT OF BLOCKS DUMPED (interleaved dumps) */h unsigned __int64 dmp$q_nocompblockcnt; /* As DUMPBLOCKCNT with no compression (interleaved dumps) */i unsigned __int64 dmp$qw_lost_vbn_list; /* First VBN in a chain of compression map VBNs that weren't */N/* used (one per actor process when its final LMB has its */N/* compression map embedded). First quadword in block is VBN */N/* of next in chain. */q unsigned __int64 dmp$q_keyblockcnt; /* Count of blocks dumped for system space, key processes, key globals */Q unsigned __int64 dmp$q_nocompkeycnt; /* As KEYBLOCKCNT with no c xompression */! char dmp$t_extra_space [492];l unsigned int dmp$l_checksum; /* Last longword of 2-block header **** KEEP AT OFFSET 1020. **** */ } DMP; #if !defined(__VAXC)3#define dmp$l_flags dmp$r_flags_overlay.dmp$l_flagsH#define dmp$v_olddump dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_olddumpD#define dmp$v_empty dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_emptyF#define dmp$v_hdrblk dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_hdrblkF#define dmp$v_errlog dmp$r_flags_oveyrlay.dmp$r_flags_bits.dmp$v_errlogF#define dmp$v_memory dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_memoryB#define dmp$v_stub dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_stubL#define dmp$v_writecomp dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_writecompN#define dmp$v_errlogcomp dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_errlogcompN#define dmp$v_trap_valid dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_trap_validJ#define dmp$v_original dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_originalH#define dmp$v_cozllect dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_collectH#define dmp$v_partial dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_partialN#define dmp$v_x86_64dump dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_x86_64dumpN#define dmp$v_bits_13_14 dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_bits_13_14H#define dmp$v_i64dump dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_i64dumpN#define dmp$v_compressed dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_compressedJ#define dmp$v_notsaved dmp$r_flags_overlay.dmp$r_flags_bits.{dmp$v_notsavedH#define dmp$v_vaxdump dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_vaxdumpL#define dmp$v_alphadump dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_alphadumpN#define dmp$v_bad4gbdump dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_bad4gbdumpJ#define dmp$v_modified dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_modifiedL#define dmp$v_shmemdump dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_shmemdumpJ#define dmp$v_procdump dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_procdumpN#define dmp$v_bits_24_28 dmp|$r_flags_overlay.dmp$r_flags_bits.dmp$v_bits_24_28J#define dmp$v_excldata dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_excldata@#define dmp$v_fen dmp$r_flags_overlay.dmp$r_flags_bits.dmp$v_fen;#define dmp$l_dumpstyle dmp$r_style_overlay.dmp$l_dumpstyleL#define dmp$v_dumpstyle dmp$r_style_overlay.dmp$r_style_bits.dmp$v_dumpstyleT#define dmp$v_full_messages dmp$r_style_overlay.dmp$r_style_bits.dmp$v_full_messagesH#define dmp$v_do_dosd dmp$r_style_overlay.dmp$r_style_bits.dmp$v_do_dosdJ#define dmp$}v_compress dmp$r_style_overlay.dmp$r_style_bits.dmp$v_compressP#define dmp$v_skip_shared dmp$r_style_overlay.dmp$r_style_bits.dmp$v_skip_sharedJ#define dmp$v_key_only dmp$r_style_overlay.dmp$r_style_bits.dmp$v_key_onlyH#define dmp$v_skip_s2 dmp$r_style_overlay.dmp$r_style_bits.dmp$v_skip_s2P#define dmp$v_interleaved dmp$r_style_overlay.dmp$r_style_bits.dmp$v_interleavedJ#define dmp$v_bits_8_9 dmp$r_style_overlay.dmp$r_style_bits.dmp$v_bits_8_9T#define dmp$v_super_verbose dmp$r_style_overlay.dmp$~r_style_bits.dmp$v_super_verboseR#define dmp$v_skip_sysdisk dmp$r_style_overlay.dmp$r_style_bits.dmp$v_skip_sysdiskP#define dmp$v_do_glxfatal dmp$r_style_overlay.dmp$r_style_bits.dmp$v_do_glxfatal\#define dmp$v_disable_glxrmtpfn dmp$r_style_overlay.dmp$r_style_bits.dmp$v_disable_glxrmtpfn^#define dmp$v_allow_hbvs_dumpdev dmp$r_style_overlay.dmp$r_style_bits.dmp$v_allow_hbvs_dumpdevL#define dmp$v_datacheck dmp$r_style_overlay.dmp$r_style_bits.dmp$v_datacheckL#define dmp$v_skip_init dmp$r_style_overlay.dmp$r_style_bits.dmp$v_skip_initL#define dmp$v_tr_buffer dmp$r_style_overlay.dmp$r_style_bits.dmp$v_tr_bufferN#define dmp$v_spl_buffer dmp$r_style_overlay.dmp$r_style_bits.dmp$v_spl_bufferN#define dmp$v_bits_19_23 dmp$r_style_overlay.dmp$r_style_bits.dmp$v_bits_19_23X#define dmp$v_mem_stack_pages dmp$r_style_overlay.dmp$r_style_bits.dmp$v_mem_stack_pagesX#define dmp$v_reg_stack_pages dmp$r_style_overlay.dmp$r_style_bits.dmp$v_reg_stack_pagesU#define dmp$q_l2_base dmp$r_platform_overlay_1.dmp$r_platform_struct_1a.dmp$q_l2_baseU#define dmp$q_l1_base dmp$r_platform_overlay_1.dmp$r_platform_struct_1a.dmp$q_l1_baseU#define dmp$q_pt_base dmp$r_platform_overlay_1.dmp$r_platform_struct_1a.dmp$q_pt_base[#define dmp$q_pte_levels dmp$r_platform_overlay_1.dmp$r_platform_struct_1b.dmp$q_pte_levelsU#define dmp$q_max_pfn dmp$r_platform_overlay_1.dmp$r_platform_struct_1b.dmp$q_max_pfnY#define dmp$l_lmb_count dmp$r_platform_overlay_1.dmp$r_platform_struct_1b.dmp$l_lmb_count]#define dmp$l_x8 6_spare_1 dmp$r_platform_overlay_1.dmp$r_platform_struct_1b.dmp$l_x86_spare_1D#define dmp$l_level_width dmp$r_platform_overlay_2.dmp$l_level_widthD#define dmp$l_perf_blocks dmp$r_platform_overlay_2.dmp$l_perf_blocks"#endif /* #if !defined(__VAXC) */ N#define DMP$K_VAX_EMB_LENGTH 12 /* Length of EMB header on VAX */ typedef struct _dmp_compat {" char dmp$t_compat_fill_1 [48]; __union {h unsigned __int64 dmp$q_v731_sysident; /* TEXT ident for SYS.EXE **** KEEP AT OFFSET 48. **** */x unsigned __int64 dmp$q_vax_embcr_swvers; /* SOFTWARE VERSION IN VAX CRASH ERRLOG **** KEEP AT OFFSET 48. **** */! } dmp$r_compat_overlay_1;" char dmp$t_compat_fill_2 [12];a unsigned int dmp$l_pre_v731_sysver; /* SYSTEM VERSION NUMBER **** KEEP AT OFFSET 68. **** */e unsigned int dmp$l_pre_v731_check; /* ONES COMPLEMENT OF SYSVER **** KEEP AT OFFSET 72. **** */k unsigned short int dmp$w_pre_v731_dumpver; /* DUMP FILE VERSION NUMBER **** K EEP AT OFFSET 76. **** */" char dmp$t_compat_fill_3 [26]; __union {m unsigned __int64 dmp$q_pre_v731_sysident; /* TEXT ident for SYS.EXE **** KEEP AT OFFSET 104. **** */ __struct {- unsigned int dmp$l_compat_fill_4;u unsigned short int dmp$w_vax_dumpver; /* DUMP FILE VERSION NUMBER ON VAX **** KEEP AT OFFSET 108. **** */3 unsigned short int dmp$w_compat_fill_5;$ } dmp$r_compat_struct_1;! } dmp$r_compat_overlay_2 ;" char dmp$t_compat_fill_4 [20];m unsigned int dmp$l_vax_crasherl; /* SYSTEM CRASH ERR LOG ENTRY ON VAX **** KEEP AT OFFSET 132. **** */ } DMP_COMPAT; #if !defined(__VAXC)F#define dmp$q_v731_sysident dmp$r_compat_overlay_1.dmp$q_v731_sysidentL#define dmp$q_vax_embcr_swvers dmp$r_compat_overlay_1.dmp$q_vax_embcr_swversN#define dmp$q_pre_v731_sysident dmp$r_compat_overlay_2.dmp$q_pre_v731_sysident\#define dmp$l_compat_fill_4 dmp$r_compat_overlay_2.dmp$r_compat_struct_1.dmp$l _compat_fill_4X#define dmp$w_vax_dumpver dmp$r_compat_overlay_2.dmp$r_compat_struct_1.dmp$w_vax_dumpver\#define dmp$w_compat_fill_5 dmp$r_compat_overlay_2.dmp$r_compat_struct_1.dmp$w_compat_fill_5"#endif /* #if !defined(__VAXC) */ N#define DMP$K_TRAPINFO_LENGTH 512 /* Length of trap entry buffer */ $typedef struct _dmp_trapinfo_entry { INTSTK dmp$t_trapinfo;N/* Verified for x86 port - Richard Bishop */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _intstk *dmp$pq_trap_intstk; /* address of INTSTK structure */#else% unsigned __int64 dmp$pq_trap_intstk;#endif" char dmp$t_trapinfo_fill [24]; } DMP_TRAPINFO_ENTRY;N#define DMP$K_CRASHERL_LENGTH 1024 /* Length of crash error log buffer */ $typedef struct _dmp_crasherl_entry {) char dmp$t_crasherl_header_fill [16];)  char dmp$t_crasherl_crash_fill [600];) char dmp$t_crasherl_entry_fill [408]; } DMP_CRASHERL_ENTRY;N#define DMP$K_IMGDMP_ICB_LENGTH 2048 /* Length of invo context block */ typedef struct _dmp_imgdmp_icb {& INVO_CONTEXT_BLK dmp$r_imgdmp_icb;N char dmp$t_spare_icb [304]; /* filler to end of block */ } DMP_IMGDMP_ICB; #ifdef __INITIAL_POINTER_SIZEI#pragma __required_pointer_size __save /* Save current pointer size */D#pragma __requir ed_pointer_size __long /* Pointers are 64-bit */Vtypedef struct _dmp_imgdmp_icb * DMP_IMGDMP_ICB_PQ; /* Pointer to a ICB structure. */P#pragma __required_pointer_size __restore /* Return to previous pointer size */#else+typedef unsigned __int64 DMP_IMGDMP_ICB_PQ;##endif /* __INITIAL_POINTER_SIZE */N#define DMP$K_IMGDMP_REGS_LENGTH 512 /* Length of general registers */ !typedef struct _dmp_imgdmp_regs {N/* Verified for x86 port - Richard Bishop  */N unsigned char dmp$b_imgdmp_prevmode; /* Not in the ICB structure */P char dmp$t_imgdmp_spare [7]; /* Keep things on quadword boundaries */N char dmp$t_spare_regs [504]; /* filler to end of block */ } DMP_IMGDMP_REGS;#define DMP$M_NODUMP 0x1#define DMP$M_POWEROFF 0x2#define DMP$M_BADMEMORY 0x4#define DMP$M_BIB_STATE 0x8"#define DMP$M_LONG_FILL 0xFFFFFFF0 typedef struct _dumpmask {N unsigned dmp$v_nodump : 1; /* Do no t write dumpfile */N unsigned dmp$v_poweroff : 1; /* Request power off of system */T unsigned dmp$v_badmemory : 1; /* Memory is too broken to try dumping it */N unsigned dmp$v_bib_state : 1; /* Request shutdown to BIB state */N unsigned dmp$v_long_fill : 28; /* Longword filler */ } DUMPMASK;O#define DMP$C_FRAG_GCT -1 /* if all bits set then GCT fragment */ #define DMP$K_FRAG_MAP_LENGTH 32 #define DMP$C_ FRAG_MAP_LENGTH 32 typedef struct _dmp_memmap {N int dmp$l_frag_map_length; /* Size of structure */O unsigned int dmp$l_frag_flags; /* See [STARLET]PMMDEF.SDL for these */N unsigned __int64 dmp$q_frag_start_pfn; /* Start PFN of fragment */T unsigned __int64 dmp$q_frag_length; /* Actual block count for memory fragment */W unsigned __int64 dmp$q_frag_nocomp_length; /* As FRAG_LENGTH without compression */ } DMP_MEMMAP;#define DMP$M_ BLOCK_BITS 0x7FF#define DMP$M_LMBHDR 0x800#define DMP$M_UNCOMP 0x1000#define DMP$M_OVERRUN 0x2000#define DMP$M_IO_ERROR 0x4000#define DMP$M_NOCOMP 0x8000N#define DMP$K_REPEAT 0 /* Repeated character sequence */N#define DMP$K_REENCODE_1 1 /* 1-bit re-encoding */N#define DMP$K_REENCODE_2 2 /* 2-bit re-encoding */N#define DMP$K_REENCODE_3 3 /* 3-bit re-encoding */N#define DMP$K_REENCODE_4 4 /* 4-bit re-encoding */N#define DMP$K_REENCODE_5 5 /* 5-bit re-encoding */N#define DMP$K_REENCODE_6 6 /* 6-bit re-encoding */N#define DMP$K_BITMAP_1 7 /* Bitmap (one dominant character) */N#define DMP$K_BITMAP_3 8 /* Bitmap (2-3 dominant characters) */N#define DMP$K_BITMAP_7 9 /* Bitmap (4-7 dominant characters) */N#define DMP$K_INCREMENT 10 /* Incrementing character sequence */N#define DMP$K_DECREMENT 11 /* Decrementing character sequence */N#define DMP$K_NOCOMP 12 /* No compression */N#define DMP$K_COMPRESSION_TYPES 13 /* Number of types */N#define DMP$M_RECOMP 32 /* Recompressed section */N#define DMP$M_FINAL 64 /* Final section to restore */N#define DMP$M_FIRST 128 /* Section is first in a "raw"  read */ typedef struct _dmp_cblock { __union { __struct {N unsigned __int64 dmp$q_comp_entry; /* An entire entry */" } dmp$r_comp_fields_1; __struct {^ unsigned int dmp$l_comp_ending_vbn; /* Final uncompressed VBN from this section */f unsigned short int dmp$w_comp_blocks; /* The count of compressed blocks in this section */ __union { __struct {U unsigned short int dmp$w_comp_flags; /* Flags for this section */* } dmp$r_comp_fields_3; __struct {e unsigned dmp$v_block_bits : 11; /* ILV only: block count & flags share a word. */t unsigned dmp$v_lmbhdr : 1; /* Not ILV: LMB header (to distinguish from map entries for holes) */Y unsigned dmp$v_uncomp : 1; /* All types: Uncompressed data section */k unsigned dmp$v_overrun : 1; /* All types: Dumpfile filled while writing this section */m unsigned dmp$v_io_error : 1; /* Not ILV: I/O error occurred while writing this section */h unsigned dmp$v_nocomp : 1; /* Not ILV: Non-compressed section (LMB header, holes) */* } dmp$r_comp_fields_4;' } dmp$r_comp_overlay_2;" } dmp$r_comp_fields_2; } dmp$r_comp_overlay_1;N/* Compression types */ } DMP_CBLOCK; #if !defined(__VAXC)R#define dmp$q_comp_entry dmp$r_comp_overlay_1.dmp$r_comp_fields_1.dmp$q_comp_entry\#define dmp$l_comp_ending_vbn dmp$r_comp_overlay_1.dmp$r_comp_fields_2.dmp$l_comp_ending_vbnT#define dmp$w_comp_blocks dmp$r_comp_overlay_1.dmp$r_comp_fields_2.dmp$w_comp_blocks{#define dmp$w_comp_flags dmp$r_comp_overlay_1.dmp$r_comp_fields_2.dmp$r_comp_overlay_2.dmp$r_comp_fields_3.dmp$w_comp_flags{#define dmp$v_block_bits dmp$r_comp_overlay_1.dmp$r_comp_fields_2.dmp$r_comp_overlay_2.dmp$r_comp_fields_4.dmp$v_block_bitss#define dmp$v_lmbhdr dmp$r_comp_overlay_1.dmp$r_comp_fields_2.dmp$r_comp_overlay_2.dmp$r_comp_fields_4.dmp$v_lmbhdrs#define dmp$v_uncomp dmp$r_comp_overlay_1.dmp$r_comp_fields_2.dmp$r_comp_overlay_2.dmp$r_comp_fields_4.dmp$v_uncompu#define dmp$v_overrun dmp$r_comp_overlay_1.dmp$r_comp_fields_2.dmp$r_comp_overlay_2.dmp$r_comp_fields_4.dmp$v_overrunw#define dmp$v_io_error dmp$r_comp_overlay_1.dmp$r_comp_fields_2.dmp$r_comp_overlay_2.dmp$r_comp_fi elds_4.dmp$v_io_errors#define dmp$v_nocomp dmp$r_comp_overlay_1.dmp$r_comp_fields_2.dmp$r_comp_overlay_2.dmp$r_comp_fields_4.dmp$v_nocomp"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */\typedef struct _dmp_cblock * DMP_CBLOCK_PQ; /* Pointer to a compression block structure. */Q#pragma __required_pointer_size __restore /* R eturn to previous pointer size */#else'typedef unsigned __int64 DMP_CBLOCK_PQ;##endif /* __INITIAL_POINTER_SIZE */#define DMP$K_SQUEEZE_LENGTH 72 #define DMP$K_MAX_COMPRESSIONS 4#define DMP$K_MAX_IO_RAW 32768N#define DMP$K_MAX_IO_112 57344 /* max full-page I/O without split */W#define DMP$K_MAX_IO_124 63488 /* max raw data when no compression possible */N#define DMP$K_MAX_IO_127 65024 /* max regular I/O without split */#define DMP$K_MAX_IO 65536#d efine DMP$K_COMP_LENGTH 2048#define DMP$K_MIN_REPEAT 16#define DMP$K_ERROR_COUNT 156#define DMP$K_OVERRUN_COUNT 159#define DMP$K_STATS_ENTRIES 162#define DMP$K_SHORT_STATS 39 typedef struct _dmp_squeeze {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N char *dmp$pq_output_start; /* The output buffer being filled */#else& unsigned __int6 4 dmp$pq_output_start;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */n char *dmp$pq_squeeze_work; /* Address of the work area into which data is initially compressed */#else& unsigned __int64 dmp$pq_squeeze_work;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* An d set ptr size default to 64-bit pointers */\ int *dmp$pq_byte_table; /* Address of array where byte values are counted */#else$ unsigned __int64 dmp$pq_byte_table;#endifY int dmp$l_output_used; /* How much of the output buffer has been used */c int dmp$l_prior_uncomp; /* Length of prior uncompressed section in output buffer */n int dmp$l_current_uncomp; /* Offset to start of current uncompressed section in output buffer */u in t dmp$l_squeeze_flags; /* DMP$M_UNCOMP gets set in here when an uncompressible section is created */` __int64 dmp$q_base_vbn; /* Raw VBN of base of LMB (always zero in full dumps) */ R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */, int (*dmp$pq_write_compressed_blocks)();#else1 unsigned __int64 dmp$pq_write_compressed_blocks;#endifN /* Callback routine to write buffer contents */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */+ unsigned __int64 *dmp$pq_squeeze_stats;#else' unsigned __int64 dmp$pq_squeeze_stats;#endifN/* Pointer to statistics array - 3 quadwords for each compression type */N/* for each compression attempt  */, unsigned int dmp$l_squeeze_uncomp_count;+ unsigned int dmp$l_squeeze_merge_count; } DMP_SQUEEZE;#define DMP$K_EXPLODE_LENGTH 40 typedef struct _dmp_explode {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN char *dmp$ps_input_start; /* The input buffer being processed */p char *dmp$ps_explode_work; /* Address of the work area into which data is initially decompressed */X int dmp$l_input_used; /* How much of the input buffer has been used */w int dmp$l_explode_flags; /* DMP$M_UNCOMP gets set in here when an uncompressible section is processed */[ int dmp$l_lowest_vbn; /* Lowest VBN exploded left in the output buffer */\ int dmp$l_highest_vbn; /* Highest VBN exploded left in the output buffer */+ int (*dmp$ps_read_compressed_blo cks)();N/* Callback routine to read more compressed data into the input buffer */+ unsigned __int64 *dmp$ps_explode_stats;N/* Pointer to statistics array - 3 quadwords for each compression type */N/* for each decompression pass */, unsigned int dmp$l_explode_uncomp_count;m char *dmp$ps_explode_filedata; /* Pointer to the file_data structure for the file being processed */ } DMP_EXPLODE; #define DMP_DISK$M_NO_ACCESS 0x1 #define DMP_DISK$M_SEPARATE 0x2!#define DMP_DISK$M_UNCOMBINED 0x4N#define DMP_DISK$K_LENGTH 45 /* Base length of DMP_DISK_DATA */  9#ifdef __cplusplus /* Define structure prototypes */struct _dmp_file_data; #endif /* #ifdef __cplusplus */ typedef struct _dmp_disk_data {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Z struct _dm p_disk_data *dmp_disk$pq_next; /* Pointer to next DMP_DISK_DATA structure */#else# unsigned __int64 dmp_disk$pq_next;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */_ struct _dmp_file_data *dmp_disk$pq_file; /* Pointer to first DMP_FILE_DATA for this disk */#else# unsigned __int64 dmp_disk$pq_file;#endifk unsigned int dmp_disk$l_vbn; /* Relative VBN in collection for this disk's file/code/etc data */` unsigned int dmp_disk$l_blocks; /* Count of blocks for this disk's file/code/etc data */U __int64 dmp_disk$q_disk_data_length; /* Length of this DMP_DISK_DATA structure */f __int64 dmp_disk$q_disk_data_total; /* Total length of all this disk's file/code/etc structures */ __union {, unsigned short int dmp_disk$w_flags; __struct {N unsigned dmp_disk$v_no_access : 1; /* Unable to access the disk */k unsigned dmp_disk$v_separate : 1; /* This DMP_DISK_DATA was allocated separately (pre-reorg) */j unsigned dmp_disk$v_uncombined : 1; /* The attached file/code/etc were allocated separately */, unsigned dmp_disk$v_fill_0_ : 5;$ } dmp_disk$r_flags_bits;# } dmp_disk$r_flags_overlay;N unsigned short int dmp_disk$w_name_length; /* Length of the disk name */N char dmp_disk$t_name [1]; /* Start of the disk name  */ } DMP_DISK_DATA; #if !defined(__VAXC)B#define dmp_disk$w_flags dmp_disk$r_flags_overlay.dmp_disk$w_flags`#define dmp_disk$v_no_access dmp_disk$r_flags_overlay.dmp_disk$r_flags_bits.dmp_disk$v_no_access^#define dmp_disk$v_separate dmp_disk$r_flags_overlay.dmp_disk$r_flags_bits.dmp_disk$v_separateb#define dmp_disk$v_uncombined dmp_disk$r_flags_overlay.dmp_disk$r_flags_bits.dmp_disk$v_uncombined"#endif /* #if !defined(__VAXC) */ #define DMP_FILE$M_NO_ACCESS 0x1 #define DMP_FILE$M_NO_UNWIND 0x2#define DMP_FILE$M_SEPARATE 0x4#define DMP_FILE$M_COUNTED 0x8N#define DMP_FILE$K_LENGTH 53 /* Base length of DMP_FILE_DATA */  9#ifdef __cplusplus /* Define structure prototypes */struct _dmp_code_data;struct _dmp_unwind_data; #endif /* #ifdef __cplusplus */ typedef struct _dmp_file_data {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default  to 64-bit pointers */^ struct _dmp_file_data *dmp_file$pq_next; /* Pointer to next DMP_FILE_DATA for this disk */#else# unsigned __int64 dmp_file$pq_next;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */_ struct _dmp_code_data *dmp_file$pq_code; /* Pointer to first DMP_CODE_DATA for this file */#else# unsigned __int64 dmp_file$pq_code;#endifR#ifd ef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */e struct _dmp_unwind_data *dmp_file$pq_unwind; /* Pointer to first DMP_UNWIND_DATA for this file */#else% unsigned __int64 dmp_file$pq_unwind;#endifN unsigned short int dmp_file$w_fid_num; /* File number */N unsigned short int dmp_file$w_fid_seq; /* File sequence number */O unsigned c har dmp_file$b_fid_rvn; /* Short form relative volume number */N unsigned char dmp_file$b_fid_nmx; /* File number extension */ short int dmp_file$w_filler;U __int64 dmp_file$q_file_data_length; /* Length of this DMP_FILE_DATA structure */S unsigned int dmp_file$l_status; /* Status when we tried to open the file */N unsigned int dmp_file$l_stv; /* Corresponding STV if relevant */ __union {' unsigned char dmp_file$b_flags; __struct {N unsigned dmp_file$v_no_access : 1; /* Unable to access the file */i unsigned dmp_file$v_no_unwind : 1; /* An image file but no unwind data (e.g. message file) */k unsigned dmp_file$v_separate : 1; /* This DMP_FILE_DATA was allocated separately (pre-reorg) */g unsigned dmp_file$v_counted : 1; /* Any DMP_UNWIND_DATAs for this file have been counted */, unsigned dmp_file$v_fill_1_ : 4;$ } dmp_file$r_flags_bits;# } dmp_file$r_flags_overlay;N unsigned char dmp_file$b_spare [1]; /* For alignment and/or reuse */N unsigned short int dmp_file$w_name_length; /* Length of the file name */N char dmp_file$t_name [1]; /* Start of the file name */ } DMP_FILE_DATA; #if !defined(__VAXC)B#define dmp_file$b_flags dmp_file$r_flags_overlay.dmp_file$b_flags`#define dmp_file$v_no_access dmp_file$r_flags_overlay.dmp_file$r_flags_bits.dmp_file$v_no_access`#define dmp_file$v_no_ unwind dmp_file$r_flags_overlay.dmp_file$r_flags_bits.dmp_file$v_no_unwind^#define dmp_file$v_separate dmp_file$r_flags_overlay.dmp_file$r_flags_bits.dmp_file$v_separate\#define dmp_file$v_counted dmp_file$r_flags_overlay.dmp_file$r_flags_bits.dmp_file$v_counted"#endif /* #if !defined(__VAXC) */ #define DMP_CODE$M_SEPARATE 0x1N#define DMP_CODE$K_LENGTH 64 /* Length of DMP_CODE_DATA */  9#ifdef __cplusplus /* Define structure prototypes */struct _dmp_unwind _data; #endif /* #ifdef __cplusplus */ typedef struct _dmp_code_data {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */^ struct _dmp_code_data *dmp_code$pq_next; /* Pointer to next DMP_CODE_DATA for this file */#else# unsigned __int64 dmp_code$pq_next;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __requir ed_pointer_size __long /* And set ptr size default to 64-bit pointers */g struct _dmp_unwind_data *dmp_code$pq_unwind; /* Pointer to DMP_UNWIND_DATA for this code segment */#else% unsigned __int64 dmp_code$pq_unwind;#endifN __int64 dmp_code$q_segnum; /* Code segment number */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */` void *dm p_code$pq_code_offset; /* Start offset of this code segment within the image */#else* unsigned __int64 dmp_code$pq_code_offset;#endifN __int64 dmp_code$q_code_size; /* Size of this code segment */m __int64 dmp_code$q_info_offset; /* Start offset within unwind segment for this code segment (IA64) */^ __int64 dmp_code$q_info_size; /* Size of unwind data for this code segment (IA64) */ __union {' unsigned char dmp_code$b_flags; __stru ct {k unsigned dmp_code$v_separate : 1; /* This DMP_CODE_DATA was allocated separately (pre-reorg) */, unsigned dmp_code$v_fill_2_ : 7;$ } dmp_code$r_flags_bits;# } dmp_code$r_flags_overlay;N unsigned char dmp_code$b_spare [7]; /* For alignment and/or reuse */ } DMP_CODE_DATA; #if !defined(__VAXC)B#define dmp_code$b_flags dmp_code$r_flags_overlay.dmp_code$b_flags^#define dmp_code$v_separate dmp_code$r_flags_overlay.dmp_code$r_flags_ bits.dmp_code$v_separate"#endif /* #if !defined(__VAXC) */ !#define DMP_UNWIND$M_NOT_HERE 0x1!#define DMP_UNWIND$M_SEPARATE 0x2N#define DMP_UNWIND$K_LENGTH 112 /* Length of DMP_UNWIND_DATA */ !typedef struct _dmp_unwind_data {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */d struct _dmp_unwind_data *dmp_unwind$pq_next; /* Pointer to next DMP_ UNWIND_DATA for this file */#else% unsigned __int64 dmp_unwind$pq_next;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */` void *dmp_unwind$pq_segment; /* Address of in-memory copy of actual unwind segment */#else( unsigned __int64 dmp_unwind$pq_segment;#endif\ __int64 dmp_unwind$q_seglen; /* Length of in-memory copy of the unwind segment */N unsigned __int64 dmp_unwind$q_segnum; /* Unwind segment number */j unsigned __int64 dmp_unwind$q_image_offset; /* Start offset of this unwind segment within the image */R __int64 dmp_unwind$q_image_seglen; /* Size of unwind segment in image file */u unsigned __int64 dmp_unwind$q_unwtab_length; /* Size (in bytes) of unwind table portion of this segment (IA64) */d unsigned int dmp_unwind$l_codeseg_count; /* Number of code segments described by this segment */` unsigned int dmp_unwind$l_vbn; /* Relative VBN in collection for this unwind segment */U unsigned int dmp_unwind$l_blocks; /* Count of blocks for this unwind segment */ __union {) unsigned char dmp_unwind$b_flags; __struct {o unsigned dmp_unwind$v_not_here : 1; /* The unwind segment wasn't kept in memory during dump copy */o unsigned dmp_unwind$v_separate : 1; /* This DMP_UNWIND_DATA was allocated separately (pre-reorg) */. unsigned dmp_unwind$v_fill_3_ : 6;& } dmp_unwind$r_flags_bits;% } dmp_unwind$r_flags_overlay;` unsigned char dmp_unwind$b_table_enc; /* Encoding for unwind table entries (only for X86) */l unsigned char dmp_unwind$b_ute_offset; /* Offset to first UTE (aka binary search table, only for X86) */d unsigned char dmp_unwind$b_ute_size; /* Size of a UTE (aka binary search table, only for X86) */s unsigned __int64 dmp_unwind$q_info_offset; /* Start offset within unwind segment for this code segment (X86) */] __int64 dmp_unwind$q_info_size; /* Size of unwind data for this code segment (X86) */Z unsigned __int64 dmp_unwind$q_fde_count; /* Count of FDEs in the lookup table (X86) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */o struct _dmp_code_data *dmp_unwind$pq_code; /* Pointer to the DMP_CODE_DATA for this unwind segment (X86)  */#else% unsigned __int64 dmp_unwind$pq_code;#endifa unsigned __int64 dmp_unwind$q_mem_address; /* Theoretical memory address of unwind segment */ } DMP_UNWIND_DATA; #if !defined(__VAXC)H#define dmp_unwind$b_flags dmp_unwind$r_flags_overlay.dmp_unwind$b_flagsf#define dmp_unwind$v_not_here dmp_unwind$r_flags_overlay.dmp_unwind$r_flags_bits.dmp_unwind$v_not_heref#define dmp_unwind$v_separate dmp_unwind$r_flags_overlay.dmp_unwind$r_flags_bits.dmp_unwind$v_separate"#endif /* #if !defined(__VAXC) */  &#pragma __required_pointer_size __save&#pragma __required_pointer_size __long)typedef DMP_DISK_DATA * DMP_DISK_DATA_PQ;+typedef DMP_DISK_DATA ** DMP_DISK_DATA_PPQ;)typedef DMP_FILE_DATA * DMP_FILE_DATA_PQ;+typedef DMP_FILE_DATA ** DMP_FILE_DATA_PPQ;)typedef DMP_CODE_DATA * DMP_CODE_DATA_PQ;+typedef DMP_CODE_DATA ** DMP_CODE_DATA_PPQ;-typedef DMP_UNWIND_DATA * DMP_UNWIND_DATA_PQ;/typedef DMP_UNWIND_DATA ** DMP_UNWIND_DATA_PPQ;)#pragma __required_pointer_size __restoreN/* Verified for x86 port - Richard Bishop */O#define DMP$K_PT_MODE 0 /* Page table mode (-1 if not PT VA) */P#define DMP$K_PT_LEVEL 1 /* Page table level (-1 if not PT VA) */N#define DMP$K_IS_VALID_VA 2 /* Valid VA? (not in the gap) */U#define DMP$K_IS_PROCESS_VA 3 /* Process VA? (includes private PT pages) */V#define DMP$K_IS_PT_VA 4 /* Page table VA? (regardless of own ership) */S#define DMP$K_IS_SYSTEM_VA 5 /* System VA? (includes shared PT pages) */N#define DMP$K_IS_SELFMAP_VA 6 /* VA in the top-level PTE? */X#define DMP$K_IS_SELFMAP_PAIR 7 /* Is VA in one of the selfmap pair of pages? */`#define DMP$K_IS_SELFMAP_PTE 8 /* Is VA below/in/above the selfmap PTE for its mode? */(#define DMP_PERF$K_PERF_HEADER_LENGTH 24 !typedef struct _dmp_perf_header {_ unsigned short int dmp_perf$w_elapsed_start; /* Offset to the DMP_PERF_ELAPSED structure */` unsigned short int dmp_perf$w_elapsed_length; /* Length of the DMP_PERF_ELAPSED structure */] unsigned short int dmp_perf$w_system_start; /* Offset to the DMP_PERF_SYSTEM structure */^ unsigned short int dmp_perf$w_system_length; /* Length of the DMP_PERF_SYSTEM structure */w unsigned short int dmp_perf$w_system_count; /* Count of DMP_PERF_SYSTEM structures (should be 2 = initial+final) */Y unsigned short int dmp_perf$w_cpu_start; /* Offset to first DMP_PERF_CPU structure */V unsigned short int dmp_perf$w_cpu_length; /* Length of a DMP_PERF_CPU structure */S unsigned short int dmp_perf$w_cpu_count; /* Count of DMP_PERF_CPU structures */a unsigned short int dmp_perf$w_process_start; /* Offset to first DMP_PERF_PROCESS structure */^ unsigned short int dmp_perf$w_process_length; /* Length of a DMP_PERF_PROCESS structure */[ unsigned short int dmp_perf$w_process_count; /* Count of DMP_PERF_PROCESS structures */N char dmp_perf$t_perf_header_align [2]; /* filler to quadword */ } DMP_PERF_HEADER;)#define DMP_PERF$K_PERF_ELAPSED_LENGTH 32 "typedef struct _dmp_perf_elapsed {h __int64 dmp_perf$q_init_time; /* Negative delta time between crash and start of memory dump */b __int64 dmp_perf$q_dump_time; /* Negative delta time actually writing the memory dump */p/* CONFIG_TIME (ILV only) is not recorded... It can be derived using (DUMP_TIME - STAGE1_TIME - STAGE2_TIME). */f/* CONFIG_TIME is the time taken to determine the available CPUs and the list of LMBs to be dumped. */i __int64 dmp_perf$q_stage1_time; /* (ILV only) Time taken to determine page ranges to be dumped */i __int64 dmp_perf$q_stage2_time; /* (ILV only) Time taken to compress and write memory contents */ } DMP_PERF_ELAPSED;(#define DMP_PERF$K_PERF_SYSTEM_LENGTH 32 !typedef struct _dmp_perf_system {^ __int64 dmp_perf$q_system_uptime; /* Negative delta time since boot (100ns  intervals) */` unsigned int dmp_perf$l_total_memory; /* Memory data returned by $GETSYI/SYI$_MAIN_MEMORY */( unsigned int dmp_perf$l_free_memory;( unsigned int dmp_perf$l_used_memory;, unsigned int dmp_perf$l_modified_memory;N unsigned int dmp_perf$l_peak_npagedyn; /* Peak usage of NPAGEDYN */N unsigned int dmp_perf$l_peak_locks; /* Peak number of locks */ } DMP_PERF_SYSTEM;%#define DMP_PERF$K_PERF_CPU_LENGTH 64 typedef struct _dmp_perf_cpu {N  unsigned int dmp_perf$l_cpu_id; /* CPU ID */ __union {a __int64 dmp_perf$q_cpu_mode_times [7]; /* Per-mode CPU times collected from each CPUdb */\ __struct { /* Saved as negative delta time (100ns intervals) */* __int64 dmp_perf$q_cpu_kernel;( __int64 dmp_perf$q_cpu_exec;) __int64 dmp_perf$q_cpu_super;( __int64 dmp_perf$q_cpu_user;- __int64 dmp_perf$q_cpu_interrupt; + __int64 dmp_perf$q_cpu_mpsynch;( __int64 dmp_perf$q_cpu_idle;* } dmp_perf$r_cpu_times_struct;% } dmp_perf$r_cpu_times_union;N char dmp_perf$t_perf_cpu_align [4]; /* filler to quadword */ } DMP_PERF_CPU; #if !defined(__VAXC)V#define dmp_perf$q_cpu_mode_times dmp_perf$r_cpu_times_union.dmp_perf$q_cpu_mode_timesj#define dmp_perf$q_cpu_kernel dmp_perf$r_cpu_times_union.dmp_perf$r_cpu_times_struct.dmp_perf$q_cpu_kernelf#define dmp_perf$q_cpu_exec dmp_perf$r_cpu_times_union.dmp_perf$r_cpu_times_struct.dmp_perf$q_cpu_exech#define dmp_perf$q_cpu_super dmp_perf$r_cpu_times_union.dmp_perf$r_cpu_times_struct.dmp_perf$q_cpu_superf#define dmp_perf$q_cpu_user dmp_perf$r_cpu_times_union.dmp_perf$r_cpu_times_struct.dmp_perf$q_cpu_userp#define dmp_perf$q_cpu_interrupt dmp_perf$r_cpu_times_union.dmp_perf$r_cpu_times_struct.dmp_perf$q_cpu_interruptl#define dmp_perf$q_cpu_mpsynch dmp_perf$r_cpu_times_union.dmp_perf$r_cpu_times_struct. dmp_perf$q_cpu_mpsynchf#define dmp_perf$q_cpu_idle dmp_perf$r_cpu_times_union.dmp_perf$r_cpu_times_struct.dmp_perf$q_cpu_idle"#endif /* #if !defined(__VAXC) */ )#define DMP_PERF$K_PERF_PROCESS_LENGTH 64 "typedef struct _dmp_perf_process {N char dmp_perf$t_proc_name [16]; /* Process name (ASCIZ) */S __int64 dmp_perf$q_proc_elapsed; /* Negative delta time (100ns intervals) */S __int64 dmp_perf$q_proc_cputime; /* Negative delta time (100ns intervals) */'  unsigned int dmp_perf$l_proc_bufio;' unsigned int dmp_perf$l_proc_dirio;( unsigned int dmp_perf$l_proc_pgflts;Y unsigned int dmp_perf$l_proc_ppgcnt; /* Not available from term mailbox, set to -1 */Y unsigned int dmp_perf$l_proc_gpgcnt; /* Not available from term mailbox, set to -1 */( unsigned int dmp_perf$l_proc_wspeak;_ unsigned __int64 dmp_perf$q_proc_virtpeak; /* Not available from term mailbox, set to -1 */ } DMP_PERF_PROCESS; &#pragma __required_pointer_s ize __save&#pragma __required_pointer_size __long-typedef DMP_PERF_HEADER * DMP_PERF_HEADER_PQ;/typedef DMP_PERF_HEADER ** DMP_PERF_HEADER_PPQ;-typedef DMP_PERF_SYSTEM * DMP_PERF_SYSTEM_PQ;/typedef DMP_PERF_SYSTEM ** DMP_PERF_SYSTEM_PPQ;'typedef DMP_PERF_CPU * DMP_PERF_CPU_PQ;)typedef DMP_PERF_CPU ** DMP_PERF_CPU_PPQ;/typedef DMP_PERF_PROCESS * DMP_PERF_PROCESS_PQ;1typedef DMP_PERF_PROCESS ** DMP_PERF_PROCESS_PPQ;)#pragma __required_pointer_size __restore $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DMPDEF_LOADED */ ww0r[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********************************************************************** ****//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:35 by OpenVMS SDL V3.7 */F/* Source: 06-JUL-2018 09:01:53 $1$DGA8345:[LIB_H.SRC]DPTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DPTDEF ***/#ifndef __DPTDEF_LOADED#define __DPTDEF_LOADED 1 G#pragma __nost andard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DPT - DRIVER PROLOGUE TABLE */N/*  */N/* EACH DEVICE DRIVER HAS A DRIVER PROLOGUE TABLE. */N/*- */ N#define DPT$K_STEP_1 1 /*A STEP 1 DRIVER */N#define DPT$K_STEP_2 2 /*A STEP 2 DRIVER */N#define DPT$K_STEP1_V1 1 /*STEP 1 VERSION 1 */N#define DPT$K_STEP1_V2 2  /*STEP 1 VERSION 2 */N#define DPT$K_STEP2_V1 1 /*STEP 2 VERSION 1 */N#define DPT$K_STEP2_V2 2 /*STEP 2 VERSION 2 (CSR mapping) */T#define DPT$K_STEP2_V3 3 /*STEP 2 VERSION 3 (early Theta, pre-IFT) */\#define DPT$K_STEP2_V4 4 /*STEP 2 VERSION 4 (Theta IFT: 64-bits, Fast I/O) */[#define DPT$K_STEP2_V5 5 /*STEP 2 VERSION 5 (Theta EFT: DDT, UCB changes) */"#define DPT$K_IOGEN_REQ_STEP2VER 5#define DPT$M_SUBCNTRL 0x1#define DPT$M_SVP 0x2#define DPT$M_NOUNLOAD 0x4#define DPT$M_SCS 0x8#define DPT$M_DUSHADOW 0x10#define DPT$M_SCSCI 0x20#define DPT$M_BVPSUBS 0x40#define DPT$M_UCODE 0x80#define DPT$M_SMPMOD 0x100#define DPT$M_DECW_DECODE 0x200#define DPT$M_TPALLOC 0x400#define DPT$M_SNAPSHOT 0x800$#define DPT$M_NO_IDB_DISPATCH 0x1000#define DPT$M_SCSI_PORT 0x2000#define DPT$M_ATM 0x4000#define DPT$M_CSMACD 0x8000#define DPT$M_FDDI 0x10000#defin e DPT$M_TR 0x20000 #define DPT$M_SHARED_INT 0x40000!#define DPT$M_DEVPATH_SUP 0x80000$#define DPT$M_MULTIPATH_SUP 0x100000#define DPT$M_ATM_FORE 0x400000#define DPT$M_USB_SUP 0x800000##define DPT$M_HOTSWAP_SUP 0x1000000 #define DPT$M_MAX_UNIT 0x2000000U#define DPT$K_BASE_LEN 168 /*LENGTH OF PRE IMAGE NAME DRIVER PROLOGUE */U#define DPT$C_BASE_LEN 168 /*LENGTH OF PRE IMAGE NAME DRIVER PROLOGUE */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ddt; struct _ddb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _dpt {#pragma __nomember_alignment __union {N int dpt$l_flink; /*FORWARD LINK TO NEXT DPT */ __struct {N struct _dpt *dpt$ps_flink; /*FORWARD LINK TO NEXT DPT  */ } dpt$r_fill_1_; } dpt$r_fill_0_; __union {N int dpt$l_blink; /*BACKWARD LINK TO PREVIOUS DPT */ __struct {N struct _dpt *dpt$ps_blink; /*BACKWARD LINK TO PREVIOUS DPT */ } dpt$r_fill_3_; } dpt$r_fill_2_; __union {N unsigned short int dpt$w_size; /*SIZE OF DRIVER */ __struct {N unsigned short int dpt$iw_size; /*SIZE OF DRIVER  */ } dpt$r_fill_5_; } dpt$r_fill_4_; __union {N unsigned char dpt$b_type; /*STRUCTURE TYPE */ __struct {N unsigned char dpt$ib_type; /*STRUCTURE TYPE */ } dpt$r_fill_7_; } dpt$r_fill_6_; char dptdef$$_fill_1;N unsigned short int dpt$iw_step; /*DRIVER STEP NUMBER */N unsigned short int dpt$iw_stepver; /*VERSION WITHIN A DRIVER STEP */  __union {N unsigned short int dpt$w_defunits; /*DEFAULT NUMBER OF UNITS */ __struct {N unsigned short int dpt$iw_defunits; /*DEFAULT NUMBER OF UNITS */ } dpt$r_fill_9_; } dpt$r_fill_8_; __union {T unsigned short int dpt$w_maxunits; /*MAXIMUM UNITS THAT CAN BE CONNECTED */ __struct {Y unsigned short int dpt$iw_maxunits; /*MAXIMUM UNITS THAT CAN BE CONNECTED */ } dpt$r_fill_11_;  } dpt$r_fill_10_; __union {N unsigned short int dpt$w_ucbsize; /*SIZE OF UCB */ __struct {N unsigned short int dpt$iw_ucbsize; /*SIZE OF UCB */ } dpt$r_fill_13_; } dpt$r_fill_12_;S unsigned short int dpt$iw_iohandles; /*Number of IOHANDLES that driver needs */U unsigned short int dpt$iw_idb_crams; /*Number of CRAMS to allocate for the IDB */U unsigned short int dpt$iw_ucb_crams; /*Number of CRAMS to allocate for the UCB */ __union {N unsigned int dpt$l_flags; /*DRIVER LOADER FLAGS */N unsigned int dpt$il_flags; /*DRIVER LOADER FLAGS */O unsigned char dpt$b_flags; /*an old-world synonym for the above */ __struct {N unsigned dpt$v_subcntrl : 1; /*DEVICE IS A SUB-CONTROLLER */N unsigned dpt$v_svp : 1; /*DEVICE REQUIRES A SYSTEM PAGE */N unsigned dpt$v_nounload : 1; /*DRIVER IS NOT TO BE UNLOADED */N unsigned dpt$v_scs : 1; /*Load common SCS code with driver */N unsigned dpt$v_dushadow : 1; /*SHADOWING DISK CLASS DRIVER */W unsigned dpt$v_scsci : 1; /*Load common SCS/CI subroutines with driver */T unsigned dpt$v_bvpsubs : 1; /*Load common BVP subroutines with driver */R unsigned dpt$v_ucode : 1; /*Driver has associated microcode image */N unsigned dpt$v_smpmod : 1; /*Driver has been modified for SMP */R unsigned dpt$v_decw_decode : 1; /*DECwindows decoder (class) driver */P unsigned dpt$v_tpalloc : 1; /*Use tape allocation class parameter */[ unsigned dpt$v_snapshot : 1; /*Driver has been certified for system snapshot */[ unsigned dpt$v_no_idb_dispatch : 1; /*Don't use IDB$L_UCBLST for UCB vectors */N unsigned dpt$v_scsi_port : 1; /*Driver is an SCSI port driver */N unsigned dpt$v_atm : 1; /*Driver is an LAN ATM port driver */O unsigned dpt$v_csmacd : 1; /*Driver is an LAN CSMAD port driver */N unsigned dpt$v_fddi : 1; /*Driver is an LAN FDDI port driver */N unsigned dpt$v_tr : 1; /*Driver is an LAN TR port driver */Q unsigned dpt$v_shared_int : 1; /*Driver supports Shared Interrupts */X unsigned dpt$v_devpath_sup : 1; /*Driver supports device path information */N unsigned dpt$v_multipath_sup : 1; /*Driver supports multipath */N unsigned dpt$v_filler_21 : 1; /*Preserve alignment */R unsigned dpt$v_atm_fore : 1; /*Driver is a LAN FORE ATM port driver */N unsigned dpt$v_usb_sup : 1; /*Driver supports USB */P unsigned dpt$v_hotswap_sup : 1; /*Driver supports PCI I/O hotswap */S unsigned dpt$v_max_unit : 1; /*Driver has specified a MAX_UNIT value */( unsigned dpt$v_fill_22_ : 6;  } dpt$r_flags_bits; } dpt$r_flags_overlay;N unsigned int dpt$il_adptype; /*ADAPTER TYPE CODE */R unsigned int dpt$il_refc; /*COUNT OF DDB'S THAT REFERENCE DRIVER */P void (*dpt$ps_init_pd)(); /*STRUCTURE INIT ROUTINE DESC ADDRESS */S void (*dpt$ps_reinit_pd)(); /*STRUCTURE RE-INIT ROUTINE DESC ADDRESS */V int (*dpt$ps_deliver_2)(); /*STEP 2 UNIT DELIVERY ROUTINE DESC ADDRESS */N int (*dpt$ps_unload)();  /*UNLOAD ROUTINE DESC ADDRESS */N struct _ddt *dpt$ps_ddt; /*POINTER TO DRIVER'S DDT ADDRESS */Y struct _ddb *dpt$ps_ddb_list; /*POINTER TO FIRST DDB IN LIST FOR THIS DRIVER */O int dpt$is_btorder; /*BOOTTIME INIT CALL ORDERING NUMBER */ __union {S int dpt$l_vector; /*POINTER TO VECTOR TABLE (IN TTDRIVER) */ __struct {S void *dpt$ps_vector; /*POINTER TO VECTOR TABLE (IN TTDRIV ER) */ } dpt$r_fill_15_; } dpt$r_fill_14_; __union {N char dpt$t_name [16]; /*AUTHOR'S NAME FOR THE DRIVER */ __struct { __union {H unsigned char dpt$b_name_len; /* CHARACTER COUNT */ __struct {M unsigned char dpt$ib_name_len; /* CHARACTER COUNT */% } dpt$r_fill_17_;! } dpt$r_fill_16_;J char dpt$t_name_str [1 5]; /* CHARACTER STRING */ } dpt$r_name_ascic; } dpt$r_name_overlay; __union {N unsigned int dpt$l_ecolevel; /*ECO LEVEL FROM IMAGE HEADER */ __struct {N unsigned int dpt$il_ecolevel; /*ECO LEVEL FROM IMAGE HEADER */ } dpt$r_fill_19_; } dpt$r_fill_18_;N unsigned int dpt$l_ucode; /*ASSOCIATED MICROCODE IMAGE */R unsigned __int64 dpt$q_linktime; /*LINK DATE AND TIME  FROM IMAGE HEADER */ __union {Z unsigned __int64 dpt$iq_image_name; /*STRING DESCRIPTOR FOR DRIVER'S IMAGE NAME */ __struct {N unsigned short int dpt$iw_iname_len; /*-- IMAGE NAME LENGTH */N unsigned char dpt$ib_iname_type; /*-- IMAGE NAME DESC TYPE */N unsigned char dpt$ib_iname_class; /*-- IMAGE NAME DESC TYPE */N void *dpt$ps_iname_ptr; /*-- IMAGE NAME DESC POINTER */ } dpt$r_iname_stuff; ! } dpt$r_image_name_stuff;N unsigned int dpt$il_loader_handle [6]; /*EXECLET LOADER HANDLE */ __union {N int dpt$l_decw_sname; /*POINTER TO COUNTED ASCII STRING */ __struct {N void *dpt$ps_decw_sname; /*POINTER TO COUNTED ASCII STRING */ } dpt$r_fill_21_; } dpt$r_fill_20_;N void *dpt$ps_customer; /*Reserved_to_customer */Z unsigned int dpt$il_devpath_size; /*SIZE OF THE PATH INFORMATION BLOCK WITHIN UCB */] unsigned int dpt$il_devpath_ucb_ofs; /*OFFSET OF THE PATH INFORMATION BLOCK WITHIN UCB */\ unsigned int dpt$il_dsplypath_size; /*MAX. SIZE OF THE DISPLAY PATH STRING WITHIN UCB */\ unsigned int dpt$il_dsplypath_ucb_ofs; /*OFFSET OF THE DISPLAY PATH STRING WITHIN UCB */N unsigned int dpt$l_max_unit; /*Number of maximum device units */ unsigned int dpt$l_spare_1;# unsigned char dpt$t_image_name; char dpt$b_fill_23_ [7];  } DPT; #if !defined(__VAXC)-#define dpt$l_flink dpt$r_fill_0_.dpt$l_flink=#define dpt$ps_flink dpt$r_fill_0_.dpt$r_fill_1_.dpt$ps_flink-#define dpt$l_blink dpt$r_fill_2_.dpt$l_blink=#define dpt$ps_blink dpt$r_fill_2_.dpt$r_fill_3_.dpt$ps_blink+#define dpt$w_size dpt$r_fill_4_.dpt$w_size;#define dpt$iw_size dpt$r_fill_4_.dpt$r_fill_5_.dpt$iw_size+#define dpt$b_type dpt$r_fill_6_.dpt$b_type;#define dpt$ib_type dpt$r_fill_6_.dpt$r_fill_7_.dpt$ib_type3#define dpt$w_defunits dpt $r_fill_8_.dpt$w_defunitsC#define dpt$iw_defunits dpt$r_fill_8_.dpt$r_fill_9_.dpt$iw_defunits4#define dpt$w_maxunits dpt$r_fill_10_.dpt$w_maxunitsE#define dpt$iw_maxunits dpt$r_fill_10_.dpt$r_fill_11_.dpt$iw_maxunits2#define dpt$w_ucbsize dpt$r_fill_12_.dpt$w_ucbsizeC#define dpt$iw_ucbsize dpt$r_fill_12_.dpt$r_fill_13_.dpt$iw_ucbsize3#define dpt$l_flags dpt$r_flags_overlay.dpt$l_flags5#define dpt$il_flags dpt$r_flags_overlay.dpt$il_flags3#define dpt$b_flags dpt$r_flags_overlay.dpt$b_flagsJ#define dpt$v_subcntrl dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_subcntrl@#define dpt$v_svp dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_svpJ#define dpt$v_nounload dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_nounload@#define dpt$v_scs dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_scsJ#define dpt$v_dushadow dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_dushadowD#define dpt$v_scsci dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_scsciH#define dpt$v_bvpsubs dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_bvpsubsD#define dpt$v_ucode dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_ucodeF#define dpt$v_smpmod dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_smpmodP#define dpt$v_decw_decode dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_decw_decodeH#define dpt$v_tpalloc dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_tpallocJ#define dpt$v_snapshot dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_snapshotX#define dpt$v_no_idb_dispatch dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_no_idb_dispatchL#define dpt$v_scsi_port dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_scsi_port@#define dpt$v_atm dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_atmF#define dpt$v_csmacd dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_csmacdB#define dpt$v_fddi dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_fddi>#define dpt$v_tr dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_trN#define dpt$v_shared_int dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_shared_intP#define dpt$v_devpath_sup dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_devpath_supT#define dpt$v_multipath_sup dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_multipath_supJ#define dpt$v_atm_fore dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_atm_foreH#define dpt$v_usb_sup dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_usb_supP#define dpt$v_hotswap_sup dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_hotswap_supJ#define dpt$v_max_unit dpt$r_flags_overlay.dpt$r_flags_bits.dpt$v_max_unit0#define dpt$l_vector dpt$r_fill_14_.dpt$l_vectorA#define dpt$ps_vector dpt$r_fill_14_.dpt$r_fill_15_.dpt$ps_vector0#define dpt$t_name dpt$r_name_overlay.dpt$t_nameX#define dpt$b_name_len dpt$r_name_overlay.dpt$r_name_ascic.dpt$r_fill_16_.dpt$b_name_leni#define dpt$ib_name_len dpt$r_name_overlay.dpt$r_name_ascic.dpt$r_fill_16_.dpt$r_fill_17_.dpt$ib_name_lenI#define dpt$t_name_str dpt$r_name_overlay.dpt$r_name_ascic.dpt$t_name_str4#define dpt$l_ecolevel dpt$r_fill_18_.dpt$l_ecolevelE#define dpt$il_ecolevel dpt$r_fill_18_.dpt$r_fill_19_.dpt$il_ecolevelB#define dpt$iq_image_name dpt$r_image_name_stuff.dpt$iq_image_nameR#define dpt$iw_ina me_len dpt$r_image_name_stuff.dpt$r_iname_stuff.dpt$iw_iname_lenT#define dpt$ib_iname_type dpt$r_image_name_stuff.dpt$r_iname_stuff.dpt$ib_iname_typeV#define dpt$ib_iname_class dpt$r_image_name_stuff.dpt$r_iname_stuff.dpt$ib_iname_classR#define dpt$ps_iname_ptr dpt$r_image_name_stuff.dpt$r_iname_stuff.dpt$ps_iname_ptr8#define dpt$l_decw_sname dpt$r_fill_20_.dpt$l_decw_snameI#define dpt$ps_decw_sname dpt$r_fill_20_.dpt$r_fill_21_.dpt$ps_decw_sname"#endif /* #if !defined(__VAXC) */ P#define DPT$S_DPTDEF 176 /*OLD DPT SIZE NAME FOR COMPATIBILITY */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DPTDEF_LOADED */ ww5[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************/ /*** MODULE $DQFDEF ***/#ifndef __DQFDEF_LOADED#define __DQFDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+  */N/* */Q/* Structure of disk quota file record. Each record contains the authorization */N/* and usage of a particular UIC for this volume set. */N/* */N/*- */ #define DQF$M_ACTIVE 0x1#define DQF$K_LENGTH 32#define DQF$C_LENGTH 32N#define DQF$ S_DQFDEF 32 /* Old size name - synonym */ typedef struct _dqf { __union {N unsigned int dqf$l_flags; /* flags longword, containing... */ __struct {N unsigned dqf$v_active : 1; /* record contains an active entry */( unsigned dqf$v_fill_13_ : 7; } dqf$r_flags_bits; } dqf$r_flags_overlay;N unsigned int dqf$l_uic; /* UIC of this record */N unsigned int dqf$l_u sage; /* number of blocks in use */N unsigned int dqf$l_permquota; /* permanent disk quota */N unsigned int dqf$l_overdraft; /* overdraft limit */N int dqf$$_fill_1 [3]; /* reserved */ } DQF; #if !defined(__VAXC)3#define dqf$l_flags dqf$r_flags_overlay.dqf$l_flagsF#define dqf$v_active dqf$r_flags_overlay.dqf$r_flags_bits.dqf$v_active"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DQFDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************************** ************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 15-JUN-2005 11:31:28 $1$DGA8345:[LIB_H.SRC]NETUSR.SDL;1 *//********************************************************************************************************************************//*** MODULE $DRDEF ***/#ifndef __DRDEF_LOADED#define __DRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* DISCONNECT REASONS */N/* */N#define NET$C_DR_NORMAL 0 /* NO ERROR (SYNCH DISCONNECT) */N#define NET$C_DR_RSU 1 /* COULDN'T ALLOCATE UCB ADDRESS */N#define NET$C_DR_NONODE 2 /* Unrecognized node name */N#define NET$C_DR_SHUT 3 /* NODE OR LINE SHUTTING DOWN */N#define NET$C_DR_NOBJ 4 /* UNKNOWN OBJECT TYPE OR PROCESS */N#define NET$C_DR_FMT 5 /* ILLEGAL PROCESS NAME FIELD */N#define NET$C_DR_BUSY 6 /* Object too busy */N#define NET$C_DR_PROTCL 7 /* GENERAL PROTOCOL ERROR */N#define NET$C_DR_THIRD 8 /* THIRD PARTY DISCONNECT */N#define NET$C_DR_ABORT 9 /* DISCONNECT ABORT */N#define NET$C_DR_IVNODE 2 /* Invalid node name format */N#define NET$C_DR_NONZ 21 /* NON-ZERO DST ADDRESS */N#define NET$C_DR_BADLNK 22 /* INCONSISTENT DSTLNK */N#define NET$C_DR_ZERO 23 /* ZERO SOURCE ADDRESS */N#define NET$C_DR_BADFC 24 /* FCVAL ILLEGAL */N#define NET$C_DR_NOCON 32 /* NO CONNECT SLOTS AVAILABLE */N#define NET$C_DR_ACCESS 34 /* INVALID ACCESS CONTROL */N#define NET$C_DR_BADSRV 35 /* LOGICAL LINK SERVICES MISMATCH  */N#define NET$C_DR_ACCNT 36 /* INVALID ACCOUNT INFORMATION */N#define NET$C_DR_SEGSIZ 37 /* SEGSIZE TOO SMALL */N#define NET$C_DR_EXIT 38 /* USER EXIT OR TIMEOUT */N#define NET$C_DR_NOPATH 39 /* NO PATH TO DESTINATION NODE */N#define NET$C_DR_LOSS 40 /* LOSS OF DATA HAS OCCURRED */P#define NET$C_DR_NOLINK 41 /* ILLEGAL MSG FOR LINK NOLINK STATE */N#define NET$C_DR_CONF 42 /* REAL DISCONNECT CONFIRM */N#define NET$C_DR_IMLONG 43 /* IMAGE DATA FIELD TOO LONG */N#define NET$C_DR_MISLSCV 50 /* MISSING CRYPTOGRAPHIC KEY */N#define NET$C_DR_EXPSCV 51 /* EXPIRED CRYPTOGRAPHIC KEY */N#define NET$C_DR_MACFAIL 53 /* INTEGRITY CHECK FAILED */N#define NET$C_DR_SRVMMAT 54 /* CRYPTOGRAPHIC SERVICE MISMATCH */X#define NET$C_DR_VERFAIL 55 /* C RYPTOGRAPHIC CONNECT VERIFICATION FAILURE */S#define NET$C_DR_CSWRAP 56 /* CRYPTOGRAPHIC SEQUENCE SPACE EXHAUSED */N/* The following two are NOT valid disconnect reason codes. They are */N/* used locally. These were previously hardcoded in NETDRVSES. */N#define NET$C_DR_INVALID 100 /* Link is IO$_DEACCESS'ed */N#define NET$C_DR_DEACC 102 /* Reason field never setup */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DRDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************* *************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:35 by OpenVMS SDL V3.7 */G/* Source: 28-NOV-2016 15:13:21 $1$DGA8345:[LIB_H.SRC]DSRVDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DSRVDEF ***/#ifndef __DSRVDEF_LOADED#define __DSRVDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DSRV ( ) Definitions */N/*  */I/* This module defines the main data structure of the MSCP */I/* server. This structure contains the values specified in */I/* the start up qualifiers when the server was loaded, the */I/* UQB vector table, and statistics that are kept for server */I/* performance measurements. */N/* */N/* <<== !NOTICE! ==>> */N/* */I/* DO NOT change offsets of the top part of the data structure. */J/* If new fields have to be added please add them to the */I/* end of the structure. */N/*- */ N/*Max number of served units  */#define DSRV$M_LOG_ENABLD 0x1#define DSRV$M_LOG_PRESENT 0x2#define DSRV$M_PKT_LOGGED 0x4#define DSRV$M_PKT_LOST 0x8#define DSRV$M_LBSTEP1 0x10#define DSRV$M_LBSTEP2 0x20#define DSRV$M_LBEVENT 0x40#define DSRV$M_HULB_DEL 0x80#define DSRV$M_MON_ACTIVE 0x100#define DSRV$M_LB_REQ 0x200 #define DSRV$M_CONFIG_WAIT 0x400#define DSRV$C_LENGTH 41452#define DSRV$K_LENGTH 41452N#define DSRV$K_AR_ADD 2 /* Action routine code */#define DSRV$K_MAX_UNITS 9999N#define DSRV$S_DSRVDEF 41452 /* Old size name synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _fkb; #endif /* #ifdef __cplusplus */ typedef struct _dsrv {N void *dsrv$l_flink; /* Field maintained for */N void *dsrv$l_blink; /* compatability */N unsigned short int dsrv$w_size; /* Structure size in bytes  */N unsigned char dsrv$b_type; /* MSCP type structure */N unsigned char dsrv$b_subtype; /* with a DSRV subtype (1) */ __union {N unsigned short int dsrv$w_state; /* Current state of the server */ __struct {N unsigned dsrv$v_log_enabld : 1; /* Logging is enabled */N unsigned dsrv$v_log_present : 1; /* Logging code is present */N unsigned dsrv$v_pkt_logged : 1; /* A packet has been logged */N unsigned dsrv$v_pkt_lost : 1; /* One or more packets over- */N/* written since last read */N unsigned dsrv$v_lbstep1 : 1; /* Load balancing step1 active */N unsigned dsrv$v_lbstep2 : 1; /* Load balancing step2 active */N unsigned dsrv$v_lbevent : 1; /* An event of interest to LB has */N/* occured while STEP1 was active */O  unsigned dsrv$v_hulb_del : 1; /* One or more HULBs to be deleted */S unsigned dsrv$v_mon_active : 1; /* The load monitor thread is active */R unsigned dsrv$v_lb_req : 1; /* A load balance request has been sent */T unsigned dsrv$v_config_wait : 1; /* Waiting for STACONFIG to complete */( unsigned dsrv$v_fill_2_ : 5; } dsrv$r_fill_1_; } dsrv$r_fill_0_;N unsigned short int dsrv$w_bufwait; /*I/Os that had to wait  */N void *dsrv$l_log_buf_start; /* Address of start of buffer */N void *dsrv$l_log_buf_end; /* Address of end of buffer */N void *dsrv$l_next_read; /* Adrs of next packet to read */N void *dsrv$l_next_write; /* Adrs of next packet to write */N unsigned short int dsrv$w_inc_lolim; /* Low unit number to log */N unsigned short int dsrv$w_inc_hilim; /* High unit number to log */N unsigned s hort int dsrv$w_exc_lolim; /* Low unit number not to log */N unsigned short int dsrv$w_exc_hilim; /* High unit number not to log */N void *dsrv$l_srvbuf; /* Address of preallocated pool */N void *dsrv$l_free_list; /* Pointer to head of free pool */N unsigned int dsrv$l_avail; /* Sum of bytes available in buffer */N unsigned int dsrv$l_buffer_min; /* Min xfer size based on buffer */N unsigned int dsrv$l_splitxfer;  /* Fragmented I/O count */N __struct { /* Info returned in GCI cmd */N unsigned short int dsrv$w_version; /* Server software version */N unsigned short int dsrv$w_cflags; /* Controller flags */N unsigned short int dsrv$w_ctimo; /* Controller timeout */N unsigned short int dsrv$w_reserved; /* Reserved for alignment */ } dsrv$r_ctrl_info;N unsigned __int64 dsrv$q_ctrl_id;  /* Unique MSCP device identifier */N unsigned int dsrv$l_memw_tot; /* Number of I/Os that had to wait */N unsigned short int dsrv$w_memw_cnt; /* Requests in memory wait queue */N unsigned short int dsrv$w_memw_max; /* Most requests ever in MEMWAIT */N void *dsrv$l_memw_fl; /* Queue listhead for requests */N void *dsrv$l_memw_bl; /* in memory wait state */N unsigned short int dsrv$w_num_host; /* Count of hosts bein g served */N unsigned short int dsrv$w_num_unit; /* Count of disks being served */N void *dsrv$l_hqb_fl; /* Host queue block list head */N void *dsrv$l_hqb_bl; /* */N void *dsrv$l_uqb_fl; /* Unit queue block list head */N void *dsrv$l_uqb_bl; /* */N/* */I/* Serve r Load Balancing fields */N/* */I/* The following fields containing working information and statistics */I/* for the server load balancing function. Load balancing status bits */I/* are defined in DSRV$STATE above. Time fields are in EXE$GL_ABSTIM */I/* format. */N/*  */N unsigned short int dsrv$w_load_avail; /* Current load available */N unsigned short int dsrv$w_load_capacity; /* Server load capacity */N unsigned short int dsrv$w_lbload; /* Target load for LB request */N unsigned short int dsrv$w_lbresp; /* Load available from other server */N unsigned short int dsrv$w_lm_load1; /* previous interval load 1 */N unsigned short int dsrv$w_lm_load2; /* previous interval load 2 */N unsigned short int dsrv$w_lm_load3; /* previous interval load 3 */N unsigned short int dsrv$w_lm_load4; /* previous interval load 4 */Q unsigned short int dsrv$w_lbinit_cnt; /* Count of LB requests we have sent */P unsigned short int dsrv$w_lbfail_cnt; /* Count of LB requests that failed */V unsigned short int dsrv$w_lbreq_cnt; /* Count of LB requests from other servers */] unsigned short int dsrv$w_lbresp_cnt; /* Count of LB requests we to which we responded */N unsigned int dsrv$l_lbreq_time; /* Time last LB request was sent */N unsigned int dsrv$l_lbmon_time; /* Time of last LB monitor pass */P struct _fkb *dsrv$l_lm_fkb; /* Address of load monitor thread FKB */P struct _fkb *dsrv$l_lb_fkb; /* Address of load balance thread FKB */N unsigned short int dsrv$w_lm_interval; /* Load monitoring interval */O unsigned char dsrv$b_lb_count1; /* Counter for load balancing thread */O unsigned cha r dsrv$b_lb_count2; /* Counter for load balancing thread */N void *dsrv$l_hulb_fl; /* HULB queue listhead */N void *dsrv$l_hulb_bl; /* */N unsigned char dsrv$b_hosts [32]; /* Bit array of hosts served */ char dsrv$b_fill_3_ [12];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomemb er_alignment#endifN void *dsrv$l_units [9999]; /* Table of UQB addresses */N/* */I/* Statistics gathering fields */N/* */I/* Two tables are maintained below. The first table is made up of the */I/* frequency count for each of the opcodes received since the server */J/* was loaded. T he opcode is used as an index into the table to its own */I/* frequency count (the zeroeth element contains a total count). The */I/* second table is made up of the frequency counters for all the */I/* different sized block transfers. For this table, the size of the */I/* transfer is the index into the table. */N/* */#pragma __nomember_alignment char dsrv$b_fill_4_ [4];c#i f !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __struct { /* Op-code counters */#pragma __nomember_alignmentN unsigned int dsrv$l_opcount; /* Total operations count */N unsigned int dsrv$l_abort_cnt; /* - 1 - */N unsigned int dsrv$l_get_cmd_cnt; /* - 2 - */N unsigned int dsrv$l_get_unt_cnt; /* - 3 - */N unsigned int dsrv$l_set_con_cnt; /* - 4 - */N unsigned int dsrv$l_acc_nvm_cnt; /* - 5 - */N unsigned int dsrv$l_display_cnt; /* - 6 - */N unsigned int dsrv$l_get_unn_cnt; /* - 7 - */N unsigned int dsrv$l_avail_cnt; /* - 8 -  */N unsigned int dsrv$l_onlin_cnt; /* - 9 - */N unsigned int dsrv$l_set_unt_cnt; /* - 10 - */N unsigned int dsrv$l_det_acc_cnt; /* - 11 - */N unsigned int dsrv$l_move_cnt; /* - 12 - */N unsigned int dsrv$l_dcd_cnt; /* - 13 - */N unsigned int dsrv$l_reserved14; /* - 14 - */N unsigned int dsrv$l_reserved15; /* - 15 - */N unsigned int dsrv$l_acces_cnt; /* - 16 - */N unsigned int dsrv$l_cmp_con_cnt; /* - 17 - */N unsigned int dsrv$l_erase_cnt; /* - 18 - */N unsigned int dsrv$l_flush_cnt; /* - 19 - */N unsigned int dsrv$l_replc_cnt; /* - 20 - */N unsigned int dsrv$l_reserved21; /* - 21 - */N unsigned int dsrv$l_eraseg_cnt; /* - 22 - */N unsigned int dsrv$l_erase_64_cnt; /* - 23 - */N unsigned int dsrv$l_format_cnt; /* - 24 - */N unsigned int dsrv$l_wri_his_cnt; /* - 25 - */N unsigned int dsrv$l_reserved26; /* - 26 - */N unsigned int dsrv$l_reserved27; /* - 27 -  */N unsigned int dsrv$l_reserved28; /* - 28 - */N unsigned int dsrv$l_reserved29; /* - 29 - */N unsigned int dsrv$l_reserved30; /* - 30 - */N unsigned int dsrv$l_reserved31; /* - 31 - */N unsigned int dsrv$l_cmp_hst_cnt; /* - 32 - */N unsigned int dsrv$l_read_cnt; /* - 33 - */N unsigned int dsrv$l_write_cnt; /* - 34 - */N unsigned int dsrv$l_rea_ced_cnt; /* - 35 - */N unsigned int dsrv$l_cmp_hst_64_cnt; /* - 36 - */N unsigned int dsrv$l_read_64_cnt; /* - 37 - */N unsigned int dsrv$l_write_64_cnt; /* - 38 - */N unsigned int dsrv$l_reserved39; /* - 39 - */N unsigned int dsrv$l_reserved40; /*  - 40 - */N unsigned int dsrv$l_reserved41; /* - 41 - */N unsigned int dsrv$l_reserved42; /* - 42 - */N unsigned int dsrv$l_reserved43; /* - 43 - */N unsigned int dsrv$l_reserved44; /* - 44 - */N unsigned int dsrv$l_reserved45; /* - 45 - */N unsigned int dsrv$l_reserved46; /* - 46 -  */N unsigned int dsrv$l_reserved47; /* - 47 - */N unsigned int dsrv$l_terco_cnt; /* - 48 - */ char dsrv$b_fill_5_ [4]; } dsrv$r_opcode_cntrs;N unsigned int dsrv$l_vcfail_cnt; /* Count of VC failures */N unsigned int dsrv$l_blkcount [257]; /* Counters for block xfer reqs */N unsigned int dsrv$l_pcb; /* Pointer to simulated PCB */N unsigned int dsrv$l_hrb_tm o_cntr; /* Counter for timed out HRB's */N unsigned int dsrv$l_seed; /* Seed for next host number. */ } DSRV; #if !defined(__VAXC)0#define dsrv$w_state dsrv$r_fill_0_.dsrv$w_stateI#define dsrv$v_log_enabld dsrv$r_fill_0_.dsrv$r_fill_1_.dsrv$v_log_enabldK#define dsrv$v_log_present dsrv$r_fill_0_.dsrv$r_fill_1_.dsrv$v_log_presentI#define dsrv$v_pkt_logged dsrv$r_fill_0_.dsrv$r_fill_1_.dsrv$v_pkt_loggedE#define dsrv$v_pkt_lost dsrv$r_fill_0_.dsrv$r_fill_1_.dsrv$v_pkt_lostC#define dsrv$v_lbstep1 dsrv$r_fill_0_.dsrv$r_fill_1_.dsrv$v_lbstep1C#define dsrv$v_lbstep2 dsrv$r_fill_0_.dsrv$r_fill_1_.dsrv$v_lbstep2C#define dsrv$v_lbevent dsrv$r_fill_0_.dsrv$r_fill_1_.dsrv$v_lbeventE#define dsrv$v_hulb_del dsrv$r_fill_0_.dsrv$r_fill_1_.dsrv$v_hulb_delI#define dsrv$v_mon_active dsrv$r_fill_0_.dsrv$r_fill_1_.dsrv$v_mon_activeA#define dsrv$v_lb_req dsrv$r_fill_0_.dsrv$r_fill_1_.dsrv$v_lb_reqK#define dsrv$v_config_wait dsrv$r_fill_0_.dsrv$r_fill_1_.dsrv$v_ config_wait6#define dsrv$w_version dsrv$r_ctrl_info.dsrv$w_version4#define dsrv$w_cflags dsrv$r_ctrl_info.dsrv$w_cflags2#define dsrv$w_ctimo dsrv$r_ctrl_info.dsrv$w_ctimo9#define dsrv$l_opcount dsrv$r_opcode_cntrs.dsrv$l_opcount=#define dsrv$l_abort_cnt dsrv$r_opcode_cntrs.dsrv$l_abort_cntA#define dsrv$l_get_cmd_cnt dsrv$r_opcode_cntrs.dsrv$l_get_cmd_cntA#define dsrv$l_get_unt_cnt dsrv$r_opcode_cntrs.dsrv$l_get_unt_cntA#define dsrv$l_set_con_cnt dsrv$r_opcode_cntrs.dsrv$l_set_con_cntA#d efine dsrv$l_acc_nvm_cnt dsrv$r_opcode_cntrs.dsrv$l_acc_nvm_cntA#define dsrv$l_display_cnt dsrv$r_opcode_cntrs.dsrv$l_display_cntA#define dsrv$l_get_unn_cnt dsrv$r_opcode_cntrs.dsrv$l_get_unn_cnt=#define dsrv$l_avail_cnt dsrv$r_opcode_cntrs.dsrv$l_avail_cnt=#define dsrv$l_onlin_cnt dsrv$r_opcode_cntrs.dsrv$l_onlin_cntA#define dsrv$l_set_unt_cnt dsrv$r_opcode_cntrs.dsrv$l_set_unt_cntA#define dsrv$l_det_acc_cnt dsrv$r_opcode_cntrs.dsrv$l_det_acc_cnt;#define dsrv$l_move_cnt dsrv$r_opcode_cn !trs.dsrv$l_move_cnt9#define dsrv$l_dcd_cnt dsrv$r_opcode_cntrs.dsrv$l_dcd_cnt=#define dsrv$l_acces_cnt dsrv$r_opcode_cntrs.dsrv$l_acces_cntA#define dsrv$l_cmp_con_cnt dsrv$r_opcode_cntrs.dsrv$l_cmp_con_cnt=#define dsrv$l_erase_cnt dsrv$r_opcode_cntrs.dsrv$l_erase_cnt=#define dsrv$l_flush_cnt dsrv$r_opcode_cntrs.dsrv$l_flush_cnt=#define dsrv$l_replc_cnt dsrv$r_opcode_cntrs.dsrv$l_replc_cnt?#define dsrv$l_eraseg_cnt dsrv$r_opcode_cntrs.dsrv$l_eraseg_cntC#define dsrv$l_erase_64_cnt dsrv$r "_opcode_cntrs.dsrv$l_erase_64_cnt?#define dsrv$l_format_cnt dsrv$r_opcode_cntrs.dsrv$l_format_cntA#define dsrv$l_wri_his_cnt dsrv$r_opcode_cntrs.dsrv$l_wri_his_cntA#define dsrv$l_cmp_hst_cnt dsrv$r_opcode_cntrs.dsrv$l_cmp_hst_cnt;#define dsrv$l_read_cnt dsrv$r_opcode_cntrs.dsrv$l_read_cnt=#define dsrv$l_write_cnt dsrv$r_opcode_cntrs.dsrv$l_write_cntA#define dsrv$l_rea_ced_cnt dsrv$r_opcode_cntrs.dsrv$l_rea_ced_cntG#define dsrv$l_cmp_hst_64_cnt dsrv$r_opcode_cntrs.dsrv$l_cmp_hst_64_cntA ##define dsrv$l_read_64_cnt dsrv$r_opcode_cntrs.dsrv$l_read_64_cntC#define dsrv$l_write_64_cnt dsrv$r_opcode_cntrs.dsrv$l_write_64_cnt=#define dsrv$l_terco_cnt dsrv$r_opcode_cntrs.dsrv$l_terco_cnt"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#e $ndif#pragma __standard #endif /* __DSRVDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior writte%n permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS So&ftware, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:35 by OpenVMS SDL V3.7 */F/* Source: 24-MAR-1993 16:36:04 ' $1$DGA8345:[LIB_H.SRC]DTNDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DTNDEF ***/#ifndef __DTNDEF_LOADED#define __DTNDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer(_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !def)ined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define DTN$K_BASE_LENGTH 24 /* length of fixed portion of DTN */N#define DTN$K_LENGTH 52 /* standard length of DTN */N#define DTN$K_NAMELEN_MAX 27 /* max length of name string */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; #endif /* #ifdef __cplusplus */ typedef struct _dtn {N struct _dtn *dtn$ps_*flink; /* flink to next DTN */N struct _dtn *dtn$ps_blink; /* blink to previous DTN */N unsigned short int dtn$w_size; /* size of DTN in bytes */N unsigned char dtn$b_type; /* structure type of DTN */N unsigned char dtn$b_subtype; /* structure subtype */N unsigned int dtn$l_flags; /* various flag bits */N unsigned char dtn$b_devtype; /* copy of+ UCB$B_DEVTYPE */N unsigned char dtn$b_devclass; /* copy of UCB$B_DEVCLASS */N short int dtn$w_spare1; /* pad for longword alignment */N struct _ucb *dtn$ps_ucblist; /* pointer to list of UCBs */N __union { /* name string */N char dtn$t_dtname [28]; /* name stored in ASCIC format */ __struct {N unsigned char dtn$ib_dtname_len; /* length, of the device name */N char dtn$t_dtname_str [27]; /* actual string */ } dtn$r_ascic_name; } dtn$r_name_overlay; } DTN; #if !defined(__VAXC)4#define dtn$t_dtname dtn$r_name_overlay.dtn$t_dtnameO#define dtn$ib_dtname_len dtn$r_name_overlay.dtn$r_ascic_name.dtn$ib_dtname_lenM#define dtn$t_dtname_str dtn$r_name_overlay.dtn$r_ascic_name.dtn$t_dtname_str"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restore-R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DTNDEF_LOADED */ wwF[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This softwar.e is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confid/ential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***** 0***************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:35 by OpenVMS SDL V3.7 */G/* Source: 09-JUN-1993 15:27:18 $1$DGA8345:[LIB_H.SRC]DTSSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DTSSDEF ***/#ifndef __DTSSDEF_LOADED#define __DTSSDEF_LOADED 1 G#pragma __nostandard 1/* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else2#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */O/* Bit definitions for 3 EXE$GL_DTSSFLAGS - flags for Distributed Time Service */N/* */N/*- */#define DTSS$M_ACTIVE 0x1"#define DTSS$M_CALCULATE_CLOCK 0x2#define DTSS$S_DTSSDEF 1 typedef struct _dtss { __struct {N unsigned dtss$v_active : 1; /* Time service active */O unsigned dtss$v_calculate_clock : 1; /* Service wants to synch4 clock */$ unsigned dtss$v_fill_0_ : 6; } dtss$r_dtssdef_bits; } DTSS; #if !defined(__VAXC)7#define dtss$v_active dtss$r_dtssdef_bits.dtss$v_activeI#define dtss$v_calculate_clock dtss$r_dtssdef_bits.dtss$v_calculate_clock"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined requir5ed ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DTSSDEF_LOADED */ wwn[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR d6isclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without7 **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:35 by OpenVM 8S SDL V3.7 */F/* Source: 15-NOV-2017 12:05:56 $1$DGA8345:[LIB_H.SRC]DXRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DXRDEF ***/#ifndef __DXRDEF_LOADED#define __DXRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr9 size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_s:truct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* This defines a DXR -- a Dump eXclusion Region. */N/* DXRs are elements in a singly-linked list. */N/* Each DXR describes a region of virtual address space */N/* that is to be excluded from sel ;ective crash dumps. */N/* */#define DXR$K_LENGTH 40#define DXR$C_LENGTH 40 typedef struct _dxr {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Y void *dxr$pq_link; /* Link to next element -- 0 means end of list */#else unsigned __int64 dxr$pq<_link;#endifN/* DXR only has flinks, so make room for a quadword */N/* pointer. */N unsigned short int dxr$w_size; /* Size of DXR in bytes */f unsigned char dxr$b_type; /* Structure type for DXR (to be filled in with DYN$C_MISC) */h unsigned char dxr$b_subtype; /* Structure subtype for DXR (to be filled in with DYN$C_DXR) */N unsigned int dxr$l_checksum; =/* Checksum */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */P void *dxr$pq_start_va; /* Start System VA of Excluded Region */#else" unsigned __int64 dxr$pq_start_va;#endifN unsigned __int64 dxr$q_bytecount; /* Size of Excluded Region in Bytes */N __int64 dxr$q_callers_pc; /* Caller's PC >*/ } DXR; #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Htypedef struct _dxr * DXR_PQ; /* Long pointer to a DXR structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 DXR_PQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_S?IZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __DXRDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietar@y software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** propArietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************* B***********************************************************************************************/=/* Created: 7-Oct-2024 15:22:35 by OpenVMS SDL V3.7 */F/* Source: 22-NOV-2023 04:31:41 $1$DGA8345:[LIB_H.SRC]DYNDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $DYNDEF ***/#ifndef __DYNDEF_LOADED#define __DYNDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-StandCard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#defDine __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DATA STRUCTURE TYPE DEFINITIONS */N/* E */N/* EACH DATA STRUCTURE THAT IS ALLOCATED FROM THE DYNAMIC MEMORY */N/* POOL SHOULD HAVE A VALID TYPE IN ITS 11TH BYTE. */N/*- */N/*BASE AND OFFSET OF 1 */N#define DYN$C_ADP 1 /*UNIBUS ADAPTER CONTROL BLOCK */N#define DYN$C_ACB 2 /*AST CONTROL BLOCK */NF#define DYN$C_AQB 3 /*ACP QUEUE BLOCK */N#define DYN$C_CEB 4 /*COMMON EVENT BLOCK */N#define DYN$C_CRB 5 /*CHANNEL REQUEST BLOCK */N#define DYN$C_DDB 6 /*DEVICE DESCRIPTOR BLOCK */N#define DYN$C_FCB 7 /*FILE CONTROL BLOCK */N#define DYN$C_FRK 8 /*FORK BLOCK */N#define DYN$C_IDB 9 G /*INTERRUPT DISPATCH BLOCK */N#define DYN$C_IRP 10 /*I/O REQUEST PACKET */N#define DYN$C_LOG 11 /*LOGICAL NAME BLOCK */N#define DYN$C_PCB 12 /*PROCESS CONTROL BLOCK */N#define DYN$C_PQB 13 /*PROCESS QUOTA BLOCK */N#define DYN$C_RVT 14 /*RELATIVE VOLUME TABLE */N#define DYN$C_TQE 15 /*TIMER QUEUHE ENTRY */N#define DYN$C_UCB 16 /*UNIT CONTROL BLOCK */N#define DYN$C_VCB 17 /*VOLUME CONTROL BLOCK */N#define DYN$C_WCB 18 /*WINDOW CONTROL BLOCK */N#define DYN$C_BUFIO 19 /*BUFFERED I/O BLOCK */N#define DYN$C_TYPAHD 20 /*TERMINAL TYPEAHEAD BUFFER */N#define DYN$C_GSD 21 /*GLOBAL SECTION DESCRIPTOR BLOCK */IN#define DYN$C_MVL 22 /*MAGNETIC TAPE VOLUME LIST */N#define DYN$C_NET 23 /*NETWORK MESSAGE BLOCK */N#define DYN$C_KFE 24 /*KNOWN FILE ENTRY */N#define DYN$C_MTL 25 /*MOUNTED VOLUME LIST ENTRY */N#define DYN$C_BRDCST 26 /*BROADCAST MESSAGE BLOCK */N#define DYN$C_CXB 27 /*COMPLEX CHAINED BUFFER */N#define DYN$C_NDB 28 J /* NETWORK NODE DESCRIPTOR BLOCK */S#define DYN$C_SSB 29 /* LOGICAL LINK SUBCHANNEL STATUS BLOCK */N#define DYN$C_DPT 30 /* DRIVER PROLOGUE TABLE */N#define DYN$C_JPB 31 /* JOB PARAMETER BLOCK */N#define DYN$C_PBH 32 /* PERFORMANCE BUFFER HEADER */N#define DYN$C_PDB 33 /* PERFORMANCE DATA BLOCK */N#define DYN$C_PIB 34 /* PKERFORMANCE INFORMATION BLOCK */N#define DYN$C_PFL 35 /* PAGE FILE CONTROL BLOCK */N#define DYN$C_PFLMAP 36 /* Page file mapping window */N#define DYN$C_PTR 37 /* POINTER CONTROL BLOCK */N#define DYN$C_KFRH 38 /* KNOWN FILE IMAGE HEADER */N#define DYN$C_DCCB 39 /* Data Cache Control Block */P#define DYN$C_EXTGSD 40 /*EXTENDED GLOBAL SECTION DESCLRIPTOR */U#define DYN$C_SHMGSD 41 /*SHARED MEMORY GLOBAL SECTION DESCRIPTOR */N#define DYN$C_SHB 42 /*SHARED MEMORY CONTROL BLOCK */N#define DYN$C_MBX 43 /*MAILBOX CONTROL BLOCK */N#define DYN$C_IRPE 44 /*I/O REQUEST PACKET EXTENSION */N#define DYN$C_SLAVCEB 45 /*SLAVE COMMON EVENT BLOCK */U#define DYN$C_SHMCEB 46 /*SHARED MEMORY MASTER COMMON EVENT BLOCK */MN#define DYN$C_JIB 47 /*JOB INFORMATION BLOCK */N#define DYN$C_TWP 48 /* Terminal driver write packet */N#define DYN$C_RBM 49 /* Realtime SPT bit map */N#define DYN$C_VCA 50 /* Disk volume cache block */N#define DYN$C_CDB 51 /*X25 LES CHANNEL DATA BLOCK */N#define DYN$C_LPD 52 /*X25 LES PROCESS DESCRIPTOR */N#define DYN$C_LKB 53 N /*LOCK BLOCK */N#define DYN$C_RSB 54 /*RESOURCE BLOCK */N#define DYN$C_LCKRQ 55 /*Lock Manager Request Block */N#define DYN$C_RSHT 56 /*RESOURCE HASH TABLE */N#define DYN$C_CDRP 57 /*CLASS DRIVER REQUEST PACKET */N#define DYN$C_ERP 58 /* ERRORLOG PACKET */N#define DYN$C_CIDG 59 /*DATAGRAMO BUFFER FOR CI PORT */N#define DYN$C_CIMSG 60 /*MESSAGE BUFFER FOR CI PORT */O#define DYN$C_XWB 61 /*DECNET LOGICAL LINK CONTEXT BLOCK */N/* (REPLACES "NDB" BLOCK) */N#define DYN$C_WQE 62 /*DECNET WORK QUEUE BLOCK */N/* (REPLACES "NET" BLOCK) */N#define DYN$C_ACL 63 /*ACCESS CONTROL LIST QUEUE ENTRY P */N#define DYN$C_LNM 64 /*LOGICAL NAME BLOCK */N#define DYN$C_FLK 65 /* Fork Lock Request Block */N#define DYN$C_RIGHTSLIST 66 /*RIGHTS LIST */O#define DYN$C_KFD 67 /* Known File Device Directory block */N#define DYN$C_KFPB 68 /* Known File list Pointer Block */O#define DYN$C_CIA 69 /* Compound Intrusion Analysis block */N#define DYN$C_PMQB 70 /* Page Fault Monitor Control Block */N#define DYN$C_PFB 71 /* Page Fault Monitor Buffer */N#define DYN$C_CHIP 72 /* Internal CHKPRO block */N#define DYN$C_ORB 73 /* Objects Rights Block */N#define DYN$C_FKB 74 /* Fork block */N#define DYN$C_MVWB 75 /* Mount Verification work buffer */N#define DYN$C_UNC 76 /*R Universal Context Block */N#define DYN$C_DCB 77 /* DCB, for DECnet chained I/O */N#define DYN$C_VCRP 78 /* VAX Communication Request Packet */N#define DYN$C_SPL 79 /* Spinlock control block */N#define DYN$C_ARB 80 /* Access Rights Block */N#define DYN$C_LCKCTX 81 /* Lock context block */N#define DYN$C_BOD 82 /* Buffer object descriptor S */N#define DYN$C_FTRD 83 /* FTDRIVER read request packet */N#define DYN$C_DDTM_EVENT 84 /* DDTM Event Notification block */N#define DYN$C_DFLB 85 /* Dump File Locator Block */N#define DYN$C_PTC 86 /* Posix Terminal Control */N#define DYN$C_OCB 87 /* Object Class Block (Security) */N#define DYN$C_CPCB 88 /* Common Process Control Block */N#define DYN$C_THWPCB 89 /* Hardware Process Control Block */N#define DYN$C_GCB 90 /* Glyph Control Block */N#define DYN$C_RDPB 91 /* Resource Domain Pointer Block */N#define DYN$C_RDDB 92 /* Resource Domain Data Block */N#define DYN$C_SCDRP 93 /* SCSI Class Driver Request Packet */N#define DYN$C_TQE_ACB 94 /* TQE-ACB block */N#define DYN$C_NSAB 95 U/* Security Audit Block */N#define DYN$C_DEA 96 /* DEaccess Audit pending block */N/* This first region is full, do not add more types. */N/* */N/* */O/* THE FOLLOWING CODES ARE SUBTYPABLE, THAT IS EACH CODE REFERS TO A GENERIC */N/* FUNCTION AND WITHIN THAT FUNCTION THERE MAY BE MANY DIFFERENTV SUB-TYPES */N/* OF BLOCKS. THIS SCHEME WAS ADOPTED TO PRESERVE TYPES. THE SUB-TYPE IS */N/* IN THE 12TH BYTE. */N/* */N#define DYN$C_SUBTYPE 96 /* START OF SUBTYPABLES */N#define DYN$C_SCS 96 /* SYSTEM COMMUNICATION SERVICES */N#define DYN$C_SCS_CDL 1 /* CONNECT DISPATCH LIST */N#define DYWN$C_SCS_CDT 2 /* CONNECT DISPATCH TABLE */N#define DYN$C_SCS_DIR 3 /* DIRECTORY BLOCK */N#define DYN$C_SCS_PB 4 /* PATH BLOCK */N#define DYN$C_SCS_PDT 5 /* PORT DESCRIPTOR TABLE */N#define DYN$C_SCS_RDT 6 /* REQUEST DESCRIPTOR TABLE */N#define DYN$C_SCS_SB 7 /* SYSTEM BLOCK */N#define DYN$C_SCS_SPPB 8 X /* SCA POLLER PROCESS BLOCK */N#define DYN$C_SCS_SPNB 9 /* SCA POLLER NAME BLOCK */N#define DYN$C_SCS_SBNB 10 /* SCS LOAD SHARE NAME BLOCK */N#define DYN$C_SCS_PLVEC 11 /* SCS PORT LOAD VECTOR */N#define DYN$C_SCS_PDTLIST 12 /* (TYC 14-Feb-89) SCS PDT LIST */N#define DYN$C_SCS_BD 13 /* Buffer Descriptor Entry */N#define DYN$C_SCS_CMNBDLT 14 /* Buffer Descriptor LYeaf Table */N#define DYN$C_SCS_RBUN 15 /* Resource bundle */N#define DYN$C_SCS_CRRR 16 /* Carrier for Nport adapters */N#define DYN$C_SCS_TYP1 17 /* TYP1 mapping structure */N#define DYN$C_SCS_SDA 18 /* CLUSTER_CRASH structure */K#define DYN$C_SCS_IPCI_CFG 19 /* IPCI early load structure */N#define DYN$C_SCS_IPCI_IPINTERFACE 20 /* IPCI SCS enabled IP interface */N#define DYZN$C_SCS_IPCI_UNICAST 21 /* IPCI unicast address */N#define DYN$C_CI 97 /* CI PORT SPECIFIC */N#define DYN$C_CI_BDT 1 /* BUFFER DESCRIPTOR TABLE */N#define DYN$C_CI_FQDT 2 /* FREE QUE DESCRIPTOR TABLE */N#define DYN$C_CI_CRRR 3 /* Carrier for Nport adapters */N#define DYN$C_LOADCODE 98 /* LOADABLE CODE */N#define DYN$C_NON_PAGED 1 [ /* NON PAGED CODE */N#define DYN$C_PAGED 2 /* PAGED CODE */N#define DYN$C_LC_MP 3 /* MULTIPROCESSOR CODE */N#define DYN$C_LC_SCS 4 /* SCS CODE */N#define DYN$C_LC_CLS 5 /* CLUSTER CODE */N#define DYN$C_LC_CHREML 6 /* CHAR/DECIMAL INS EMUL */N#define DYN$C_LC_FPEMUL 7 /* FLOAT PNT EMULATOR \ */N#define DYN$C_LC_MSCP 8 /* MSCP SERVER */N#define DYN$C_LC_SYSL 9 /* SYSLOA */N#define DYN$C_LDRIMG 10 /* Execlet data structure */Z#define DYN$C_INIT 99 /* STRUCTURES SET UP BY INIT OR INIT'N ROUTINES */N#define DYN$C_PCBVEC 1 /* PROCESS CONTROL BLOCK VECTOR */N#define DYN$C_PHVEC 2 /* PROCESS HEADER VECTOR ]*/N#define DYN$C_SWPMAP 3 /* SWAPPER MAP */N#define DYN$C_MPWMAP 4 /* MODIFIED PAGE WRITER MAP */N#define DYN$C_PRCMAP 5 /* PROCESS BITMAP */N#define DYN$C_BOOTCB 6 /* BOOT CONTROL BLOCK */N#define DYN$C_CONF 7 /* CONFIGURATION ARRAYS */N#define DYN$C_CST 8 /* CLUSTER SYSTEM TABLE */N#define DYN$C_COLOR_AR^RAYS 9 /* PFN COLOR ARRAYS */N#define DYN$C_PHREFC 10 /* PROCESS HEADER REF COUNT ARRAY */_#define DYN$C_POOL_STATS 11 /* POOL STATS ARRAYS (ALLOCS, FAILS, DEALLOCS, ETC.) */N#define DYN$C_RING_BUFFER 12 /* HISTORY RING BUFFER */N#define DYN$C_POOL_MAP 13 /* POOL_MAP created during INIT */P#define DYN$C_LSTHDS 14 /* LSTHDS pointer created during INIT */U#define DYN$C_CLASSDRV 100 _ /* CLASS DRIVER MAJOR STRUCTURE TYPE CODE */N#define DYN$C_CD_CDDB 1 /* CLASS DRIVER DATA BLOCK */N#define DYN$C_CD_BBRPG 2 /* BAD BLOCK REPLACEMENT PAGE */N#define DYN$C_CD_SHDW_WRK 3 /* SHADOW SET WORK BUFFER */N#define DYN$C_CD_LDB 4 /* LOAD DRIVER DATA BLOCK */O#define DYN$C_CLU 101 /* CLUSTER MAJOR STRUCTURE TYPE CODE */N#define DYN$C_CLU_CSB 1 /* C`ONNECTION STATUS BLOCK */N#define DYN$C_CLU_CLUVEC 2 /* CLUSTER SYSTEM VECTOR */N#define DYN$C_CLU_CLUB 3 /* CLUSTER BLOCK */N#define DYN$C_CLU_BTX 4 /* CLUSTER BLOCK TRANSFER EXTENSION */O#define DYN$C_CLU_CLUDCB 5 /* CLUSTER DISK QUORUM CONTROL BLOCK */[#define DYN$C_CLU_CLUOPT 6 /* CLUSTER OPTIMAL RECONFIGURATION CONTEXT BLOCK */W#define DYN$C_CLU_LCKDIR 7 /* LOCK MANAGEaR DISTRIBUTED DIRECTORY VECTOR */N#define DYN$C_CLU_ICB 8 /* INCARNATION FILE CONTROL BLOCK */N#define DYN$C_CLU_CLURCB 9 /* REMASTER CONTROL BLOCK */N#define DYN$C_CLU_NTE 10 /* NOTIFICATION TABLE ENTRY */N#define DYN$C_CLU_CSDT 11 /* SERVER DISPATCH TABLE */U#define DYN$C_CLU_CWLNM 12 /* CLUSTERWIDE LOGICAL NAME MESSAGE BUFFER */N#define DYN$C_CLU_CLUEVT 13 /* CLUSTER EVENT BLOCKb */N#define DYN$C_PGD 102 /* PAGED DYNAMIC MEMORY */N#define DYN$C_PGD_F11BC 1 /* F11BXQP BUFFER CACHE. */N#define DYN$C_KFERES 2 /* KFE resident sections */V#define DYN$C_IMRE 3 /* track imgreg_pages VA allcation [INSTAL] */N#define DYN$C_KFERES64 4 /* KFERES64 resident sections */N#define DYN$C_P0_POOL 5 /* P0 Pool allocation header */Nc#define DYN$C_IMCB 6 /* Image control block */S#define DYN$C_FREE_IMCB 7 /* Image control block on lookaside list */W#define DYN$C_IMGACT_POOL 8 /* process pool page used by image activator */W#define DYN$C_IMGDMP 9 /* process pool reserved for image dump work */N#define DYN$C_DECW 103 /* DECWINDOWS */N#define DYN$C_DECW_GPB 1 /* GPX Packet Buffer */Nd#define DYN$C_DECW_GPD 2 /* GPX Physical Data */N#define DYN$C_DECW_INB 3 /* Input Buffer descriptor */N#define DYN$C_DECW_DVI 4 /* Device Info block */N#define DYN$C_VWS 104 /* UIS Structure */N/* UIS subtypes */N#define DYN$C_UIS_ARD 1 /* Allocation region */N#define DYN$C_UIS_VDB 2 e /* Virtual display control block */N#define DYN$C_UIS_WDB 3 /* Display window control block */N#define DYN$C_UIS_SEG 4 /* Segment control block */N#define DYN$C_UIS_ATB 5 /* Attribute block */N#define DYN$C_UIS_OTP 6 /* Output primitive */N#define DYN$C_UIS_APD 7 /* Application-specific data */W#define DYN$C_UIS_SEGEND 8 /* Segment "fend" marker (really part of SEG) */N#define DYN$C_UIS_URG 9 /* User region AST request block */N#define DYN$C_UIS_VDT 10 /* Display transformation */O#define DYN$C_UIS_MENU 11 /* Window options menu or menu items */N#define DYN$C_UIS_KBB 12 /* Virtual keyboard control block */N#define DYN$C_UIS_RES 13 /* Resize/rescale information block */N#define DYN$C_UIS_VCMD 14 /* Virtual color map descrgiptor */N#define DYN$C_UIS_VCMS 15 /* Virtual color map section */N#define DYN$C_UIS_CMSD 16 /* Color map segment descriptor */X#define DYN$C_UIS_CMSB 17 /* Color map segment allocation control block */N#define DYN$C_UIS_CMS 18 /* Color map segment */N#define DYN$C_UIS_FNT 19 /* Font block */[#define DYN$C_UIS_FNTH 20 /* Font header -- extra memory at head of ha font */N#define DYN$C_UIS_VPD 21 /* Viewport descriptor block */N#define DYN$C_UIS_VRD 22 /* Viewport region descriptor */N#define DYN$C_UIS_BMD 23 /* */N#define DYN$C_UIS_OFF_MEM 24 /* Offscreen memory descriptor */N#define DYN$C_UIS_USB 25 /* UIS system-wide storage */N#define DYN$C_UIS_QBE 26 /* QVSS block extension */N#define DYN$C_iUIS_MEM 27 /* Video scanline allocation block */N#define DYN$C_UIS_VSL_MEM 28 /* VAX scanline storage */N#define DYN$C_UIS_SL_TEMP 29 /* Scanline temporary storage */N#define DYN$C_UIS_ERROR 30 /* Error handler "spare" memory */N/* VPS subtypes */N#define DYN$C_VPS_FM 86 /* */N#define DYN$C_VPS_CTX 87 j/* */N#define DYN$C_VPS_PPD 88 /* Per-process data structure */N#define DYN$C_VPS_SDB 89 /* Scan descriptor block */N#define DYN$C_VPS_BTD 90 /* Bitmap descriptor */N/* VWS subtypes */N#define DYN$C_VWS_REGIS 170 /* ReGIS buffer */N#define DYN$C_VWS_VT200 171 /* VT200 emulator buffer k */N#define DYN$C_VWS_CHR_ARR 172 /* Character array */N#define DYN$C_VWS_CLIP 173 /* Clipping region desc */N#define DYN$C_VWS_CUR 174 /* */N#define DYN$C_VWS_FNTD 175 /* Font descriptor */N#define DYN$C_VWS_SCR 176 /* */N#define DYN$C_VWS_UPD 177 /* */N#define DYN$lC_VWS_UPDE 178 /* UPD extension */N#define DYN$C_VWS_VIEW 179 /* Driver Viewport control block */N#define DYN$C_VWS_DOP 180 /* Device output primative packet */N#define DYN$C_VWS_GLYB 181 /* Glyph storage block */N#define DYN$C_DSRV 105 /* Disk Server structure type */N/* Server subtypes */N#define DYN$C_DSRV_DSRV 1 m /* Disk server structure */N#define DYN$C_DSRV_HQB 2 /* Host Queue Block */N#define DYN$C_DSRV_HRB 3 /* Host Request Block */N#define DYN$C_DSRV_IOBUF 4 /* Server local I/O Buffer */N#define DYN$C_DSRV_UQB 5 /* Unit Queue Block */N#define DYN$C_DSRV_HULB 6 /* Host-Unit Load Block */N#define DYN$C_MP 106 /* MP related structure n */N/* MP subtypes */N#define DYN$C_MP_MPB 1 /* Logical Console Block */N#define DYN$C_MP_CPU 2 /* Per-CPU database */N#define DYN$C_NSA 107 /* Non-discretionary Security Audit */N#define DYN$C_NSA_EVENT 1 /* Event enable vectors */N#define DYN$C_NSA_FAILURE 2 /* Failure mode vectors */N#define DYoN$C_NSA_ALARM 3 /* Security alarm packet list */N#define DYN$C_CWPS 108 /* Cluster-Wide Process Services */N/* CWPS subtypes for process control service codes */N#define DYN$C_CWPS_CANWAK 1 /* $CANWAK service */N#define DYN$C_CWPS_DELPRC 2 /* $DELPRC service */N#define DYN$C_CWPS_FORCEX 3 /* $FORCEX service */N#define DYN$C_CWPS_RESUME 4 p /* $RESUME service */N#define DYN$C_CWPS_SCHDWK 5 /* $SCHDWK service */N#define DYN$C_CWPS_SETPRI 6 /* $SETPRI service */N#define DYN$C_CWPS_SUSPND 7 /* $SUSPND service */N#define DYN$C_CWPS_WAKE 8 /* $WAKE service */N/* CWPS subtypes for other services */N#define DYN$C_CWPS_GETJPI 20 /* $GETJPI service q */N#define DYN$C_CWPS_CREPRC 21 /* $CREPRC service */N#define DYN$C_CWPS_TERMIN 22 /* process termination message */N/* CWPS subtypes for security service codes */N#define DYN$C_CWPS_GRANTID 28 /* $GRANTID service */N#define DYN$C_CWPS_REVOKID 29 /* $WAKE service */N/* CWPS subtypes for miscellaneous structures */N#define rDYN$C_CWPSACB 64 /* CWPSACB$ structure */N#define DYN$C_CWPSNODI 65 /* CWPSNODI$ structure */N#define DYN$C_CWPSSQH 66 /* CWPSSQH$ structure */N#define DYN$C_PSCANBUF 67 /* PSCAN JPI buffer */N#define DYN$C_PSCANCTX 68 /* PSCAN context */N#define DYN$C_PSCANITM 69 /* PSCAN JPI itemlist */N#define DYN$C_VP 109 s /* Vector processing support */N/* Vector processing subtypes */N#define DYN$C_VP_VCTX 1 /* Vector context block */N#define DYN$C_VP_VEXC 2 /* Vector saved exception block */N#define DYN$C_SHAD 110 /* Volume Shadowing structure type */N#define DYN$C_VCC 111 /* VAXcluster cache */N/* VCC subtypes t */N#define DYN$C_VCC_CL 1 /* Cache Line */N#define DYN$C_VCC_CPT 2 /* Cache Page Table */N#define DYN$C_VCC_HT 3 /* Hash Table */N/* for VCC_CFCB SUBTYPE and RMOD overlap so force correct RMOD bits */N#define DYN$C_VCC_CFCB 32 /* Cache FCB */N/* XFC Data structures are subtypes of VCC. */N#definue DYN$C_VCC_CFB 64 /* Cache File Block */N#define DYN$C_VCC_CVB 65 /* Cache Volume Block */N#define DYN$C_VCC_PECB 66 /* Primary Extent Cache Block */N#define DYN$C_VCC_SECB 67 /* Secondary Extent Cache Block */N#define DYN$C_VCC_EFB 68 /* Extent File Block */N#define DYN$C_VCC_FHT 69 /* File Hash Table */N#define DYN$C_VCC_EHT 70 v /* Extent Hash Table */N#define DYN$C_VCC_ANCHOR 71 /* Anchor data structure */N#define DYN$C_VCC_SFBAR 72 /* Single File Barrier */N#define DYN$C_VCC_IFBAR 73 /* Interfile barrier */P#define DYN$C_VCC_DIRBAR 74 /* Directed side of interfile barrier */Q#define DYN$C_VCC_DEPBAR 75 /* Dependent side of interfile barrier */N#define DYN$C_VCC_FLUSHBAR 76 /* Flush Barwrier */N#define DYN$C_VCC_WTB 77 /* Writer-thread control block */N#define DYN$C_VCC_CTX 78 /* I/O Context */N#define DYN$C_VCC_MTX 79 /* Mutex structure */N#define DYN$C_VCC_CVS 80 /* Cache Volume Statistics */T#define DYN$C_VCC_HWMBAR 81 /* Deferred highwater mark update barrier */N#define DYN$C_VCC_VHT 82 /* Volume Hash Table x */N#define DYN$C_VCC_LCKCTX 83 /* Lock Context */N#define DYN$C_VCC_CFS 84 /* Cache File Statistics */N#define DYN$C_VCC_SPRM 85 /* SSIO Parameters */N#define DYN$C_VCC_SSC 86 /* SSIO Stream Context */G#define DYN$C_VCC_SCTX 87 /* SSIO Context */N#define DYN$C_OVRS 112 /* Open VMS NT Registry Server */N/* OVRS subtypes y */N/* Subtypes for the Registry Client */N#define DYN$C_OVRS_RCB 1 /* Registry Control Block */N#define DYN$C_OVRS_RRB 2 /* Registry Request Block */N#define DYN$C_OVRS_OKH 3 /* Open Key Header */N#define DYN$C_OVRS_OKE 4 /* Open Key Entry */N#define DYN$C_OVRS_PKE 5 /* Predefizned Key Entry */N#define DYN$C_OVRS_CRED 6 /* Credentials Block */N#define DYN$C_OVRS_RTB 7 /* Rights Block */N/* Subtypes for the Registry Server */N#define DYN$C_OVRS_SSB 8 /* Server Status Block */N#define DYN$C_OVRS_LSB 9 /* Lock Status Block */N#define DYN$C_OVRS_TCB 10 /* Thread Control Block {*/N#define DYN$C_OVRS_TRB 11 /* Thread Request Block */N#define DYN$C_OVRS_WIT 12 /* Work Item */N/* Subtypes for Communication */N#define DYN$C_OVRS_CDS 13 /* Connection Descriptor */P#define DYN$C_OVRS_ICCB 14 /* Inter-Cluster Communications Block */N#define DYN$C_OVRS_NP 15 /* Network Packet */N#define DYN$C_OVRS_N|PH 16 /* Network Packet Header */N#define DYN$C_OVRS_RPH 17 /* Request Packet Header */N#define DYN$C_OVRS_SIB 18 /* Security Information Block */N/* Subtypes for the Registry Database */N#define DYN$C_OVRS_RRT 19 /* Registry Root Table */N#define DYN$C_OVRS_FLE 20 /* File List Entry */N#define DYN$C_OVRS_FTH 21 /* Fil}e Table Header */N#define DYN$C_OVRS_FTB 22 /* File Table Block */N#define DYN$C_OVRS_FTE 23 /* File Table Entry */N#define DYN$C_OVRS_LTB 24 /* Logical File Table */N#define DYN$C_OVRS_LTE 25 /* Logical file Table Entry */N#define DYN$C_OVRS_DFH 26 /* Database File Header */N#define DYN$C_OVRS_SGH 27 /* Segment Header ~ */N#define DYN$C_OVRS_STH 28 /* Segment Table Header */N#define DYN$C_OVRS_STE 29 /* Segment Table Entry */N#define DYN$C_OVRS_FSO 30 /* File/Segment/Offset */N#define DYN$C_OVRS_CTE 31 /* Category Table Entry */N#define DYN$C_OVRS_KEY 32 /* Key */N#define DYN$C_OVRS_VAL 33 /* Value */N#define DYN$C_OVRS_STR 34 /* String */N#define DYN$C_OVRS_DAT 35 /* Data */N#define DYN$C_OVRS_SEC 36 /* Security Descriptor */N#define DYN$C_OVRS_KCN 37 /* Key Change Notification */N#define DYN$C_OVRS_SLS 38 /* Shared Library Structure */N#define DYN$C_OVRS_TKE 39 /* To be clean Key Entry */N#define DYN$C_OVRS_SPA 40 /* Search path structure */N#define DYN$C_OVRS_OUT 41 /* Output Parameters */N/* Subtypes for the Logging */N#define DYN$C_OVRS_WPK 42 /* Write Packet */N#define DYN$C_OVRS_WUN 43 /* Write Unit */N#define DYN$C_OVRS_RBQ 44 /* Rollback structure */N#define DYN$C_OVRS_CTESAV 45 /* CTE Structure Save  */N#define DYN$C_OVRS_LOCKSAV 46 /* Lock Structure Save */N#define DYN$C_OVRS_DLH 47 /* Database Log File Header */N#define DYN$C_OVRS_MLH 48 /* Master Log File Header */N#define DYN$C_OVRS_RLH 49 /* Reply Log File Header */N#define DYN$C_OVRS_LRH 50 /* Log Record Header */N#define DYN$C_OVRS_LGR 51 /* Log Record */N#define DYN$C_OVRS_RPR 52 /* Reply Log Record */N#define DYN$C_OVRS_CMR 53 /* Commit Record */N#define DYN$C_OVRS_MCR 54 /* Master Commit Record */N/* Add new types here so as not to create database incompatibilities */N#define DYN$C_OVRS_CNX 55 /* Connection Block */N#define DYN$C_OVRS_CSB 56 /* Connection Status Block */N#define DYN$C_OVRS_WCB 57 /* Work Context Block */Q#define DYN$C_DDTM 113 /* Digital Distributed Transaction Mgr */N/* DDTM subtypes */N#define DYN$C_DDTM_XCB 1 /* Transaction Control Block */O#define DYN$C_DDTM_XSCB 2 /* Transaction Segment Control Block */S#define DYN$C_DDTM_XPCB 3 /* Transaction Participant Control Block */N#define DYN$C_DDTM_CDCB 4 /* Commit Domain Control Block */T#define DYN$C_DDTM_CMDB 5 /* Communication Manager Definition Block */Q#define DYN$C_DDTM_CMCB 6 /* Communication Manager Control Block */N#define DYN$C_DDTM_RMCB 7 /* Resource Manager Control Block */Q#define DYN$C_DDTM_NDCB 8 /* V1 DDTM Communication Manager Block */N#define DYN$C_DDTM_DGCB 9 /* TPCom Dialogue Control Block */N#define DYN$C_DDTM_LGCB 10 /* Log Control Block  */N#define DYN$C_DDTM_NNCB 11 /* Node Name Cache Block */N#define DYN$C_DDTM_DDTMTXT 12 /* DECdtm text block */N/* Subtypes for the Log Manager (LM) */N#define DYN$C_LM_LBDB 13 /* Log Buffer Descriptor Block */N#define DYN$C_LM_LMLINK 14 /* Log Server Link Message */N#define DYN$C_LM_LMOPCB 15 /* Parameter Block for LM$OPEN call */N#define DYN$C_LM_LMRCB 16 /* Read Control Block */N#define DYN$C_LM_LMTRCB 17 /* Transition Control Block */N#define DYN$C_LM_LMREAD 18 /* Read Return */N#define DYN$C_LM_LCB 19 /* Log Control Block */N#define DYN$C_LM_LMTREE 20 /* TID Tree Entry */N#define DYN$C_LM_LMHT 21 /* Hash Table */N#define DYN$C_LM_LMTE 22 /* Hash Table Entry */N/* Additional subtypes for DECdtm (DDTM) */N#define DYN$C_DDTM_XTCB 23 /* Thread Control Block */P#define DYN$C_DDTM_XTCBLW 24 /* "Lightweight" Thread Control Block */N#define DYN$C_DDTM_STACK 25 /* Thread Stack Control Block */P#define DYN$C_DDTM_XBID 26 /* Transaction Brand Id Control Block */#define DYN$C_DDTM_XSBID 27O#define DYN$C_DDTM_XDCB 28  /* Default Transaction Control Block */Q#define DYN$C_DDTM_XCBX 29 /* Transaction Control Block Extension */]#define DYN$C_DDTM_XPCBX 30 /* Transaction Participant Control Block Extension */N/* Additional subtypes for the Log Manager (LM) extended structures */N#define DYN$C_LM_LMOPCBX 31 /* Open Control Block */N#define DYN$C_LM_LMRCBX 32 /* Read Control Block */N#define DYN$C_LM_LMTRCBX 33  /* Transition Control Block */N#define DYN$C_SMI 114 /* System Management Integrator */N/* SMI subtypes */Q#define DYN$C_SMI_CSCB 1 /* Cluster/System Communications Block */N#define DYN$C_SMI_CTX 2 /* Internal context block */N#define DYN$C_SMI_SUPB 3 /* Server User Profile Block */N#define DYN$C_SMI_RTTB 4 /* RouTine Table Block */N#define DYN$C_TSRV 115 /* Tape Server structure type */N/* Server subtypes */N#define DYN$C_TSRV_TSRV 1 /* Tape server structure */N#define DYN$C_TSRV_HQB 2 /* Host Queue Block */N#define DYN$C_TSRV_HRB 3 /* Host Request Block */N#define DYN$C_TSRV_UQB 4 /* Unit Queue Block */N#define DYN$C_TSRV_TBUFF 5 /* Tape local Buffer */P#define DYN$C_LAVC 116 /* Local Area VAX Cluster structures. */N/* LAVC subtypes */N#define DYN$C_LAVC_ROOT 1 /* ROOT block data structure. */N#define DYN$C_LAVC_PORT 2 /* PORT block data structure. */N#define DYN$C_LAVC_VC 3 /* Virtual Circuit data structure. */N#define DYN$C_LAVC_CH 4  /* Channel Block data structure. */N#define DYN$C_LAVC_BUS 5 /* BUS block data structure. */[#define DYN$C_LAVC_COMP 6 /* Network component description data structure. */T#define DYN$C_LAVC_CLST 7 /* Network component list data structure. */S#define DYN$C_LAVC_ID_TABLE 8 /* Network component ID table structure. */N#define DYN$C_LAVC_NIT 9 /* NIsca Timer structure */N#define DYN$C_LAVC_TRACE_CONTEXT 10 /* PEDRIVER trace context structure */N#define DYN$C_LAVC_TRACE 11 /* PEDRIVER trace buffer */N#define DYN$C_DECNET 117 /* DECNET structures */N/* */N/* DECNET subtype definitions. Each component gets a multiple of 8 */N/* entries; except the first (which gets 7 because we wanted 0 to be */N/* the unknown entry).  */N/* */N/* Note that the DECNET subtypes break the SUBTYPE NAME RESTRICTIONS */N/* and the format code in SDA special cases for */N/* this occurance. */N/* */N#define DYN$C_NET_UNK 0 /* Unknown subtype of zero */N/* */N/* Base image vectors (2-8) */I/* */N#define DYN$C_NET_NBI_NDVEC 2 /* Network Data Vectors */N#define DYN$C_NET_NBI_NBIRV 3 /* Global Routine Vectors */O#define DYN$C_NET_NBI_GRVH 4 /* Global routine init vector header */N#define DYN$C_NET_NBI_GRVE 5 /* Global routine init vector entry */N/* */N/* Common trace support data structures (9-16) */I/* */N#define DYN$C_NET_CTF_TB 9 /* Trace block */N#define DYN$C_NET_CTF_TR 10 /* Trace record */N#define DYN$C_NET_CTF_MH 11 /* Module header  */N#define DYN$C_NET_CTF_REQ 12 /* Trace requests */N/* */N/* EMAA support structures (17-24) */N/* */O#define DYN$C_NET_EMAA_MRCP 17 /* Management request control packet */N#define DYN$C_NET_EMAA_IVK 18 /* Invoke block */N#define DYN$C_NET_EMAA_EMAA 19 /* Misc dynamic EMAA structures */N#define DYN$C_NET_EMAA_EIB 20 /* Entity information block */N#define DYN$C_NET_EMAA_EISDB 21 /* Entity semantic block */N#define DYN$C_NET_EMAA_EAB 22 /* Entity access block */N#define DYN$C_NET_EMAA_IVKIDTBL 23 /* Invoke Block ID Table */N#define DYN$C_NET_EMAA_ERTTBL 24 /* Entity Registration Table */N/*  */N/* Loader support data structures (25-32) */I/* */N#define DYN$C_NET_LDR_LIE 25 /* Loaded Image Entry block */N/* */N/* Task support data structures (33-40) */I/*  */N#define DYN$C_NET_TSK_NTK 33 /* Network task scheduler database */N#define DYN$C_NET_TSK_TCX 34 /* Task context block */N#define DYN$C_NET_TSK_TPB 35 /* Task parameter block */N#define DYN$C_NET_TSK_SQX 36 /* Scheduler queue block */N#define DYN$C_NET_TSK_SCX 37 /* Scheduler control block */N/* */N/* Timer support data structures (41-48) */I/* */N#define DYN$C_NET_TIM_NTM 41 /* Network timer database */N#define DYN$C_NET_TIM_NTEB 42 /* Network timer element block */N/* */N/* VCI support data structures (49-56) */I/*  */N#define DYN$C_NET_VCI_VRT 49 /* VCI Registration Table */N#define DYN$C_NET_VCI_VID 50 /* VCI Identification Table */N#define DYN$C_NET_VCI_VCIB 51 /* VCI Communication Info Block */N#define DYN$C_NET_VCI_DCBE 52 /* Data Chain Block (Extension) */N/* */N/* EVL support data structures (57-64)  */I/* */N#define DYN$C_NET_EVL_EVT 57 /* EVL Event Report */N/* */I/* Itemlist support structure (65-72) */N/* */N#define DYN$C_NET_ITEM 65 /* Network Itemlist */N/*  */I/* Session control support structure (73-88 = 16 entries) */N/* */N#define DYN$C_NET_SCL_SESSID 73 /* Session Connection Id Table */N#define DYN$C_NET_SCL_SPB 74 /* Session Port Block */N#define DYN$C_NET_SCL_SCLSVP 75 /* Session VCI Port data block */N#define DYN$C_NET_SCL_SCLATTR 76 /* Session VCI port attribute block */N#define DYN$C_NET_SCL_BUFFER 77 /* Generic session buffer */N#define DYN$C_NET_SCL_CRPROC 78 /* Create process block */N#define DYN$C_NET_SCL_CRPROCNCB 79 /* Create process NCB block */N#define DYN$C_NET_SCL_USER_CRPROC 80 /* Create process usermode block */N/* */N/* NSP support data structures (89-96) */I/* */N#define DYN$C_NET_NSP_ATB 89 /* NSP Association Table */N#define DYN$C_NET_NSP_TCTB 90 /* NSP Transport Connection Table */N#define DYN$C_NET_NSP_NSP 91 /* NSP service blk subtype */N#define DYN$C_NET_NSP_LSP 92 /* LSP service blk subtype */N#define DYN$C_NET_NSP_RSP 93 /* RSP service blk subtype */N#define DYN$C_NET_NSP_PORT 94 /* PORT service blk subtype */N/* */N/* LAN support data structures (97-104) */I/* */N#define DYN$C_NET_LAN_LAN 97 /* LAN LAN Entity Block */N#define DYN$C_NET_LAN_LSB 98 /* LAN Station Block */N#define DYN$C_NET_LAN_LPB 99 /* LAN Port Block  */N/* */N/* Thread support data structures (105-112) */I/* */N#define DYN$C_NET_THREAD 105 /* Thread Block */N/* */I/* Network Routing Layer data structures (113-144 = 32 entries) */N/*  */N#define DYN$C_NET_NRL_NRD 113 /* Global database */N#define DYN$C_NET_NRL_HTB 114 /* Hash table header */N#define DYN$C_NET_NRL_CKT 115 /* Circuit database entry */N#define DYN$C_NET_NRL_ADJ 116 /* Adjacency database entry */N#define DYN$C_NET_NRL_PSB 117 /* Protocol service block */N#define DYN$C_NET_NRL_TP 118  /* Transport database entry */N#define DYN$C_NET_NRL_CKTEVT 119 /* Circuit event block */N/* */N/* Node agent data structures (145-152) */N/* */N#define DYN$C_NET_NODE_IDS 145 /* ID table header */N#define DYN$C_NET_NODE_DATABASE 146 /* Permanent database  */N/* */N/* OSITP support data structures (153-168 = 16 Entries) */N/* */N#define DYN$C_NET_OSITP_ATB 153 /* OSI Association Table */N#define DYN$C_NET_OSITP_TCTB 154 /* OSI Transport Connection Table */N#define DYN$C_NET_OSITP_NCCB 155 /* OSI Transport */N/* Network Connection Block */N#define DYN$C_NET_OSITP_ILB 156 /* OSI Transport */N/* Itemlist Block */N#define DYN$C_NET_OSITP_TLB 157 /* OSI Transport */N/* Timer List Block */N#define DYN$C_NET_OSITP_TMP 158 /* OSI Transport */N/* Template Name Block  */N#define DYN$C_NET_OSITP_OSI 159 /* OSI Transport */N/* OSI Block */N#define DYN$C_NET_OSITP_PORT 160 /* OSI Transport */N/* port Block */N#define DYN$C_NET_OSITP_LSP 161 /* OSI Transport */N/* LSP Block  */N#define DYN$C_NET_OSITP_RSP 162 /* OSI Transport */N/* RSP Block */N#define DYN$C_NET_OSITP_ITM 163 /* OSITP Allocated Item list */#define DYN$C_NET_OSITP_TLQ 164N/* */N/* QIO support data structures (169-176) */N/*  */N#define DYN$C_NET_QIO_DAB 169 /* Declared Application Block */N#define DYN$C_NET_QIO_QLB 170 /* QIO Link Block */N/* */N/* MOP data structures (177-192) */N/* */N#define DYN$C_NET_MOP_MRCPIN 177 /* MRCP Inbound from management */N#define DYN$C_NET_MOP_MRCPOUT 178 /* MRCP Outbound to management */N#define DYN$C_NET_MOP_MANAGEMENTABORT 179 /* Management Abort Block */P#define DYN$C_NET_MOP_CPRPIN 180 /* Create Port Request Packet Inbound */Q#define DYN$C_NET_MOP_CPRPOUT 181 /* Create Port Request Packet Outbound */P#define DYN$C_NET_MOP_DPRPIN 182 /* Delete Port Request Packet Inbound */Q#define DYN$C_NET_MOP_DPRPOUT 183 /* Delete Port Request Packet Outbound */N#define DYN$C_NET_MOP_VCRPIN 184 /* VCRP Inbound from Datalink */N#define DYN$C_NET_MOP_VCRPOUT 185 /* VCRP Outbound to Datalink */O#define DYN$C_NET_MOP_ENPIN 186 /* Event Notification Packet Inbound */P#define DYN$C_NET_MOP_ENPOUT 187 /* Event Notification Packet Outbound */N#define DYN$C_NET_MOP_PDUOUT 188 /* PDU Outbound to Datalink */N#define DYN$C_NET_MOP_SUBPDU 189 /* Sub PDU */U#define DYN$C_NET_MOP_CPB 190  /* Console Carrier Connect Parameter Block */N#define DYN$C_NET_MOP_WORK 191 /* Thread Work BLock */N#define DYN$C_NET_MOP_TRC 192 /* Tracepoint substructure */N#define DYN$C_NET_MOP_TIMER 193 /* Timer block */N/* */N/* TPCONS support data structures (201-209 = 9 Entries) */N/*  */#define DYN$C_NET_TPCONS 201!#define DYN$C_NET_TPCONS_TPCB 202 #define DYN$C_NET_TPCONS_ATB 203 #define DYN$C_NET_TPCONS_ITM 204#define DYN$C_NET_TPCONS_MD 205 #define DYN$C_NET_TPCONS_BUF 206 #define DYN$C_NET_TPCONS_TLB 207N/* */N/* OSVCM support data structures (210-214 = 5 Entries) */N/* */N#define DYN$C_NET_OSVCM_OCB 210 /* OSVCM Context Block */N#define DYN$C_NET_OSVCM_LAB 211 /* OSVCM Local Address Block */N/* */N/* End of DECNET subtype definitions */N/* */T#define DYN$C_PSX 118 /* Generic type code for Posix structures */N#define DYN$C_PSX_XCTX 1 /* System Service Context Area */N#define DYN$C_PSX_XPCB 2 /* Extended PCB */N#define DYN$C_PSX_XSIG 3 /* Signal Block */N#define DYN$C_PSX_PXSB 4 /* Session Block */N#define DYN$C_PSX_PXPG 5 /* Process Group Block */N#define DYN$C_PSX_SHSH 6 /* Semaphore hash table */N#define DYN$C_PSX_SIDT 7 /* Semaphore Id table */N#define DYN$C_PSX_SOB 8 /* semaphore Operation block */N#define DYN$C_PSX_SMB 9 /* semaphore block */N#define DYN$C_PSX_FCCB 10 /* fork_callbacks control block */N#define DYN$C_PSX_FCDB 11 /* fork_callbacks dispatch block */N#define DYN$C_PSX_PSXHDR 12 /* POSIX SID/PGID header structure */X#define DYN$C_PSX_PSXMEM 13 /* POSIX SID/PGID individual member structure */\#define DYN$C_QMAN 119 /* Generic type code for Queue Manager structures */N#define DYN$C_QMAN_QDB 1 /* Queue Data block */N#define DYN$C_QMAN_QMANMSG 2 /* Queue manager message header */P#define DYN$C_QMAN_GQC 3 /* Queue manager GETQUI context block */N#define DYN$C_SM 120 /* Storage Management Subtypes */N#define DYN$C_SM_MMECB 1 /* MME control block */N#define DYN$C_SM_MCB 2 /* Mount context block */N#define DYN$C_MISC 121 /* Miscellaneous types */N/* Miscellaneous data structures */P#define DYN$C_CRAM 1 /* Controller Register Access Mailbox */N#define DYN$C_CRAMH 2 /* Page header for CRAM */N#define DYN$C_KPB 3 /* Kernel Process Block */N#define DYN$C_CRAB 4 /* Counted resouce allocation block */N#define DYN$C_CRCTX 5 /* Counted resouce context block */N#define DYN$C_BUSARRAY 6 /* Bus Array */N#define DYN$C_VLE 7 /* Vector List Extension */N#define DYN$C_CMDTABLE 8 /* Bus Command Table */N#define DYN$C_CAR 9 /* XZA/SCSI Carrier structure */N#define DYN$C_QBUF 10 /* XZA/SCSI Q_Buffer structure */N#define DYN$C_PADBLK 11 /* XZA/SCSI Pad Buffer structure */Q#define DYN$C_SGMAP 12 /* XZA/SCSI Scatter-Gather Map struct. */N#define DYN$C_C710S 13 /* Cobra NCR 53C710 SCSI Port */N#define DYN$C_SPDT 14 /* SCSI Port Descriptor Table */N#define DYN$C_SCDT 15 /* SCSI Connection Descriptor Table */N#define DYN$C_PRCEVT 16 /* Process event block  */N#define DYN$C_PRCSTR 17 /* Alternate procstrt */W#define DYN$C_ECB 18 /* A1742A/SCSI Enhanced Control Block struct */P#define DYN$C_ASB 19 /* A1742A/SCSI Status Block structure */T#define DYN$C_SGL 20 /* A1742A/SCSI Scatter/Gather List Struct */X#define DYN$C_ICDB 21 /* A1742A/SCSI Init. Configuration Data Block */N#define DYN$C_FDT_CONTEXT 22 /* FDT Context Structure  */N#define DYN$C_DTN 23 /* Dynamic Type Name structure */T#define DYN$C_SSI_BLOCK 24 /* System Service Intercept Control block */a#define DYN$C_IOHANDLE 25 /* IOHANDLE structure for platform independent mapping */R#define DYN$C_STDT 26 /* SCSI Target Descriptor Table RCL0001 */P#define DYN$C_MCJ 27 /* Magic Cookie Jar to hold IOHANDLEs */N#define DYN$C_ISACFG 28 /* ISA Config Data Blocks */R#define DYN$C_SCSICLS 29 /* SCSI Class driver random data blocks */N#define DYN$C_RDE 30 /* Region descriptor entry */N#define DYN$C_DIOBM 31 /* Direct I/O Buffer Map */N#define DYN$C_FANDLEVEC 32 /* Fandle vector */R#define DYN$C_MC_PDT 33 /* Memory Channel Port Descriptor Table */N#define DYN$C_CONFIG_TABLE 34 /* Adapter Configuration table */N#define DYN$C_RMD 35 /* Reserved Memory Descriptor */Q#define DYN$C_TTSTR 36 /* Site-specific terminal text strings */N#define DYN$C_PRVPFN 37 /* Private PFN list head */N#define DYN$C_MMAP 38 /* Memory map data structure */N#define DYN$C_GBL_MAP 39 /* Global section mapping structure */N#define DYN$C_SUD 40 /* Supplemental UCB Data structure */N#define DYN$C_CBB 41 /* Common Bitmask Block */N#define DYN$C_DXR 42 /* Dump eXclusion Record (Bugcheck) */N#define DYN$C_MPDEV 43 /* Multipath data structure */N#define DYN$C_FP 44 /* Fastpath data structure */N/* */N/* [X-78] Subtypes defined for FibreChannel */N/*  */N#define DYN$C_ACTX 45 /* Adapter Context */T#define DYN$C_CHS 46 /* PCI Configuration Header Space CSRs */X#define DYN$C_FCCD 47 /* Fibre Channel Command Descriptor [X-79] */N#define DYN$C_CSR 48 /* Other CSRs */N#define DYN$C_CTR 49 /* Counter Set */N#define DYN$C_LSDB 50 /* Link State Data Block */N#define DYN$C_MBD 51 /* Mapped Buffer Descriptor */N#define DYN$C_PCTX 52 /* Protocol Context */N#define DYN$C_RBD 53 /* Ring Buffer Descriptor */N#define DYN$C_RCTX 54 /* Emulex Ring Context */N#define DYN$C_SCTX 55 /* Shell Context */N#define DYN$C_UCTX 56 /* Unit Context */N/* */N/* [X-78] End */N/* */N#define DYN$C_DDT 57 /* Driver Dispatch Table */N#define DYN$C_MPDEV_PPB 58 /* Multipath poller block */N#define DYN$C_RIH 59 /* RAD Info Header */N#define DYN$C_DEV_WWID_DUPLE 60 /* Fibre Channel device/WWID data */N#define DYN$C_AMDS_REG_SEG 61 /* AM/DECamds registration segment */R#define DYN$C_SDP 62 /* System dump priority data structure. */N#define DYN$C_IOCNT 63 /* IOCNT data */N#define DYN$C_RAD 64 /* Per-RAD data structure */N#define DYN$C_TQEIDX 65 /* TQE index block */N#define DYN$C_SSENTRY 66 /* IPF system service entry frame */N#define DYN$C_INTSTK 67 /* IPF interrupt frame */N#define DYN$C_ADB 68 /* IPF Ast Dispatch Block */Z#define DYN$C_OCLA 69 /* Marvel On-Chip Logic Analyzer data structure */O#define DYN$C_INDICTREQ 70 /* Indictment data request structure */N#define DYN$C_INDICTDEF 71 /* Indictment data head structure */R#define DYN$C_DEVCFG_CBK 72 /* Device configure call back structure */N#define DYN$C_ICRD 73 /* Invo context region descriptor */R#define DYN$C_STALE_SSENTRY 74 /* Stale IPF system service entry frame */N#define DYN$C_STALE_INTSTK 75 /* Stale IPF interrupt frame */N#define DYN$C_KPSTACK 76 /* IPF KP Stack context */N#define DYN$C_HBMM_EP 77 /* HBMM evaluate policy structure */V#define DYN$C_WTID 78 /* FibreChannel WWID Throttle IO Descriptor */T#define DYN$C_FCPROT 79 /* FibreChannel protocol connection block */N#define DYN$C_PSXROO 80 /* Posix ROOT definition structure */\#define DYN$C_DBGIBR 81 /* Debug inst break register array (hung off PCB) */\#define DYN$C_DBGDBR 82 /* Debug data break register array (hung off PCB) */T#define DYN$C_MBOX_MSG 83 /* Mailbox Driver message packet (writes) */R#define DYN$C_MBOX_BUF 84 /* Mailbox Driver system buffer (reads) */Z#define DYN$C_BUGLOG 85 /* Bugcheck Log additional crash info structure */_#define DYN$C_RHA 86 /* RAD Hint Array for global sections (hung off RIH) */^#define DYN$C_SYSMD 87 /* Memory disk boot data block (deleted by SYSINIT) */R#define DYN$C_DIOBD 88 /* [X-141] Direct I/O Buffer Descriptor */N#define DYN$C_IOBD 89 /* [X-142] I/O Buffer Descriptor */[#define DYN$C_RC 122  /* Generic type code for RAID control structures */R#define DYN$C_IPC 123 /* Generic type code for IPC structures */N/* System Service Data Structure Subtypes */N#define DYN$C_IPC_AB 1 /* Association Block */N#define DYN$C_IPC_CB 2 /* Connection Block */N#define DYN$C_IPC_IPCBUF 3 /* Buffer Descriptor */N/* SYSIPC Data Structure Subtypes  */N#define DYN$C_IPC_NT 4 /* Name Table */N#define DYN$C_IPC_TDB 5 /* Transport Descriptor Block */N#define DYN$C_IPC_TPCB 6 /* Transport Control Block */N#define DYN$C_IPC_LCB 7 /* Link Control Block */N#define DYN$C_IPC_LIST 8 /* List (generic table) Header */N#define DYN$C_IPC_PHL 9 /* Physical Link Block  */N/* Local Transport data structure subtypes */N#define DYN$C_IPC_LCCB 10 /* Local Copy Control Block */N/* DECnet NSP Transport data structure subtypes */N#define DYN$C_IPC_IPC_CCB 11 /* ACP Channel Control Block */N#define DYN$C_IPC_IPC_ACP 12 /* Global ACP Data Cell Block */N/* SCA Transport data structure subtypes */N#define DYN$C_IPC_TLTB 13 /* Transport Logical Link Table */R#define DYN$C_IPC_TLCB 14 /* Transport Logical Link Control Block */N#define DYN$C_IPC_TVCB 15 /* Transport Virtual Circuit Block */N#define DYN$C_IPC_TCB 16 /* Transport Control Block */Y#define DYN$C_IPC_TPBTX 17 /* SCA Transport Block Transfer CDRP Extension */N/* Shared data structure subtypes */N#define DYN$C_IPC_IPST 18 /* IPST */N#define DYN$C_IPC_IPLK 19 /* IPLK */N#define DYN$C_IPC_IPB 20 /* IPB */N#define DYN$C_IPC_IPC 21 /* ACP Work Block */N#define DYN$C_IPC_POOL 22 /* Pool header - structure follows */N#define DYN$C_FILE_SYSTEM 124 /* File system structures */N#define DYN$C_SQE 1 /* XQP  serialization queue entry */N/* */N/* Dollar File system types */N/* */W#define DYN$C_F64 125 /* Generic type code for Files-64 structures */#define DYN$C_F64_XQPDATA 1#define DYN$C_F64_FDB 2#define DYN$C_F64_CDESC 3#define DYN$C_F64_MCB 4#define DYN$C_F64_DIRENTRY 5#d efine DYN$C_F64_F64VPI_PATH 6##define DYN$C_F64_F64VPI_PATHCOMP 7#define DYN$C_F64_F64VPI_MCB 8#define DYN$C_F64_F64VPI_FDB 9#define DYN$C_F64_RES1 10#define DYN$C_F64_RES2 11#define DYN$C_F64_RES3 12N/* */N/* Types for Snapshot-capable disk */N/* */#define DYN$C_F64_SDANCHOR 13#define DYN$C_F64_SDCB 14#define DYN$C_F64_SDMB 15#define DYN$C_F64_MIRP 16#define DYN$C_F64_SLE 17#define DYN$C_F64_SL 18#define DYN$C_F64_CRASH 19#define DYN$C_F64_FAMTAB 20#define DYN$C_F64_FAMTABSUM 21#define DYN$C_F64_FREEMAP 22#define DYN$C_F64_FREEMAPSUM 23#define DYN$C_F64_HASH 24#define DYN$C_F64_HASHSUM 25#define DYN$C_F64_HOWF 26#define DYN$C_F64_HOWFSUM 27#define DYN$C_F64_NAMTAB 28#define DYN$C_F64_NAMTABSUM 29#define DYN$C_F64_ROOTMAP 30#define DYN$C_F64_ROOTMA PSUM 31#define DYN$C_F64_SEGBASE 32#define DYN$C_F64_SEGBASESUM 33#define DYN$C_F64_SEGMAP 34#define DYN$C_F64_SEGMAPSUM 35#define DYN$C_F64_NAMETABLE 36Y#define DYN$C_FILES_64 126 /* Generic type code for all Dollar facilities */ #define DYN$C_FILES_64_F64DATA 1N/* KERNEL DOLLAR THREADS */N#define DYN$C_FILES_64_THD_GL_DATA 2 /* Global Data */N#define DYN$C_FILES_64_THD_DTCB 3 /* Thread Control Block */N#define DYN$C_FILES_64_THD_SEMA 4 /* Semaphore structure */N#define DYN$C_FILES_64_THD_STACKDSC 5 /* Stack Descriptor */N#define DYN$C_FILES_64_THD_RES1 6 /* Reserved */N#define DYN$C_FILES_64_THD_RES2 7 /* Reserved */N/* KERNEL DOLLAR LOCK MANAGER */N#define DYN$C_FILES_64_LCK_HANDLE 8 /* Lock Handle */N#define DYN$C_FILES_64_LCK_EVQ 9 /* Lock Event Queue */N#define DYN$C_FILES_64_LCK_ACC_EVT 10 /* Lock Request Acceptance Event */N#define DYN$C_FILES_64_LCK_QUED_EVT 11 /* Lock Queued Event */N#define DYN$C_FILES_64_LCK_BLK_EVT 12 /* Lock Blocking Event */N#define DYN$C_FILES_64_LCK_RES1 13 /* Reserved */N#define DYN$C_FILES_64_LCK_RES2 14 /* Reserved */N/* KERNEL CONTAINER MANAGER */N#define DYN$C_FILES_64_CM_IRPX 15 /* IRP extension */N#define DYN$C_FILES_64_CM_AICB 16 /* Asynchronous IO control block */N#define DYN$C_FILES_64_CM_GL_DATA 17 /* Global Data */N#define DYN$C_FILES_64_CM_RES2 18 /* Reserved */N#define DYN$C_FILES_64_CM_RES3 19 /* Reserved */N#define DYN$C_SECURITY 127 /* Security data block type */N/* and its subtypes ... */N#define DYN$C_SECURITY_CLASS 1 /* Classification block ($CLASSDEF) */N#define DYN$C_SECURITY_PSB 2 /* Persona Security Block ($PSBDEF) */H#define DYN$C_SECURITY_RIGHTS 3 /* RightsBlock ($RIGHTSDEF) */e#define DYN$C_SECURITY_PXRB 4 /* Persona Security Extension registration Block ($PXBDEF) */[#define DYN$C_SECURITY_PXBNT 5 /* Persona Security Extension NT Block ($PXBDEF) */c#define DYN$C_SECURITY_DELEGATE_BLOCK 6 /* Persona Security Extension Delegation Block ($PXBDEF) */X#define DYN$C_SECURITY_PXB_ARRAY 7 /* Persona Security Extension Array ($PXBDEF) */e#define DYN$C_SECURITY_RESERVE_BLOCK 8 /* Persona Security Delegation Reservation Block ($PSBDEF) */T#define DYN$C_SECURITY_PSB_ARRAY 9 /* Persona Security Block Array ($PSBDEF) */T#define DYN$C_SECURITY_PSB_RINGBUFFER 10 /* Persona Security Ringbuffer ($PSBDEF) */h#define DYN$C_SECURITY_PXB_GENERIC 11 /* Persona Security Extension Block (not VMS or NT) ($PXBDEF) */N#define DYN$C_SECURITY_ACMESDB 12 /* ACME server data block */N#define DYN$C_SECURITY_ACMEADB 13 /* ACME agent data block */N#define DYN$C_SECURITY_ACMECH 14 /* ACME configuration header */N#define DYN$C_SECURITY_ACMERM 15 /* ACME request/response message */N/* */N/* Special dynamic memory type. On VAX, this used to be mark the start of */N/* the types handled specially by EXE$DALONONPAGED. Now we don't use them */N/* and we do need more non-special types, so this is just a type code with */N/* no additional significance. */N/* */N#define DYN$C_SPECIAL 128 /* SPECIAL TYPE = 128 */N#define DYN$C_SHRBUFIO 128  /* SHARED MEMORY BUFFERED I/O */N#define DYN$C_LNMC 129 /* Logical-name cache block */N/* */N/* ICC data types */N/* */N#define DYN$C_ICC 130 /* ICC structure typ cd */N#define DYN$C_ICCPDB 1 /* ICC Process Data Blk */N#define DYN$C_ICCP1B 2 /* P1-space data */N#define DYN$C_ICCPAB 3 /* Association Data Blk */N#define DYN$C_ICCPCB 4 /* Connection Data Blk */N#define DYN$C_ICCPSB 5 /* Send Data Block */N#define DYN$C_ICCPRB 6 /* Receive Data Block */N/* */N/* Galaxy specific data types */N/* */N#define DYN$C_GLX 131 /* GLX structure type */N#define DYN$C_GMDB 1 /* Galaxy management database */U#define DYN$C_SHM_CPP 2 /* Shared memory common property partition */N#define DYN$C_SHM_REG 3 /* Shared memory region structure */N#define DYN$C_SHM_DESC 4 /* Shared memory descriptor */P#define DYN$C_SHMEM 5 /* Shared memory management structure */N#define DYN$C_CPU_GCB 6 /* Galaxy CPU Block */N#define DYN$C_CPU_GMD 7 /* Galaxy Member Data Block */N#define DYN$C_GMP 8 /* Galaxy Message Packet */N#define DYN$C_GLOCK 9 /* Galaxy lock */N#define DYN$C_MEMCBK 10 /* Galaxy member callback */S#define DYN$C_NODEB 11 /* Galaxy management database node block */N/* */N/* Galaxy data type that requires compatibility with ACB64 structure */N/* */N#define DYN$C_CTD 132 /* Type code for for CTD structure */N/*  */N/* Lock Manager specific data types */N/* */N#define DYN$C_LCK 133 /* Lock manager structure type */N#define DYN$C_LCKCPU 1 /* per-CPU counter block */N#define DYN$C_LCK_POOLZONE 2 /* poolzone header block */N#define DYN$C_LCKSTR 3 /* lock manager struct block */N#define DYN$C_LCK_TRACE 4 /* lock manager debug and trace */Q#define DYN$C_RMCTX 5 /* fast remastering block xfer context */N/* */N/* QIOServer specific structure types */N/* */N#define DYN$C_QSRVR 134 /* QIOserver structure type UNUSED */N/*  */N/* System event data structure type */N/* */N#define DYN$C_SYS_EVENT 135 /* System event structure type */N/* */N/* Shared Memory Cluster Interconnect */N/*  */P#define DYN$C_SMCI 136 /* Shared Memory Cluster Interconnect */N#define DYN$C_SMCH 1 /* SMCI Channel structure */N#define DYN$C_SMND 2 /* SMCI Node structure */N#define DYN$C_SMH 3 /* SMCI Handle */N#define DYN$C_NB 4 /* SMCI Negotiation Block */N#define DYN$C_PBFKB 5 /* SMCI IPint FKB */N#define DYN$C_SMWE 6 /* SMCI Work Entry */N/* */N/* Spinlock Share Array Element */N/* */N#define DYN$C_SPLX 137 /* Spinlock Extensions */N#define DYN$C_SPL_SHR 1 /* Spinlock Share Array Element */N#define DYN$C_SPL_TRACE 2  /* Spinlock Trace */N#define DYN$C_SPLDBG 3 /* Spinlock debug structure */N#define DYN$C_SPLTRH 4 /* spinlock trace header */Q#define DYN$C_SPLPTR 5 /* Array of spinlock addresses for SDA */N/* */N/* Write bitmap */N/*  */N#define DYN$C_WBM 138 /* Write Bitmap */a#define DYN$C_WBM_WBMB 1 /* Write Bitmap Block - basic tracking struct for WBM */U#define DYN$C_WBM_BITMAP 2 /* Actual bitmap header and bits structure */V#define DYN$C_WBM_DATA 3 /* Global data for tracking WBM information */N#define DYN$C_WBM_WBMH_ARRAY 4 /* Bitmap handle array */P#define DYN$C_WBM_WBMCD_ARRAY 5  /* Bitmap connection descriptor array */j#define DYN$C_WBM_CTX 6 /* To store the context during Asynchronous "setbit" operation */N/* */N/* Universal Serial Bus */N/* */N#define DYN$C_USB 139 /* Universal Serial Bus */N#define DYN$C_USB_BUS 1  /* Bus structure */N#define DYN$C_USB_DEVICE 2 /* Device structure */N#define DYN$C_USB_INTERFACE 3 /* Interface structure */N#define DYN$C_USB_PIPE 4 /* Pipe structure */N#define DYN$C_USB_REQUEST 5 /* Request structure */N#define DYN$C_USB_ENDPOINT 6 /* Endpoint structure */N#define DYN$C_USB_HUB 7 /* Hub structure  */N#define DYN$C_USB_FUNCTION 8 /* Function structure */N#define DYN$C_USB_BUFFER 9 /* I/O buffer */N/* */N/* LAN facility specific structure types */N/* */N#define DYN$C_LAN 140 /* LAN structure type */N#define DYN$C_LAN_LSB 1 /* The LSB Structure */N#define DYN$C_LAN_FCRB 2 /* Fibre Channel Request Block */T#define DYN$C_LAN_FCARP 3 /* Fibre Channel Address Resolution Table */N/* */N/* TCPip facility specific structure types */N/* */N#define DYN$C_TCPIP 141  /* TCPIP structure type */N/* */N/* ACPI facility specific structure types */N/* */N#define DYN$C_ACPI 142 /* ACPI structure type */N/* */N/* Pshared specific data types  */N/* */N#define DYN$C_PSH 143 /* Pshared structure type */N#define DYN$C_PSH_ARY 1 /* pshared array structure type */N#define DYN$C_PSH_MAS 2 /* pshared master structure type */N#define DYN$C_PSH_OBJ 3 /* pshared object structure type */N#define DYN$C_PSH_TIM 4 /* pshared timeout structure type */N#define DYN$C_PSH_WT 5 /* pshared wait structure type */N#define DYN$C_PSH_GBL 6 /* pshared global structure type */N#define DYN$C_PSH_OWN 7 /* pshared owner structure type */N#define DYN$C_PSH_STA 8 /* pshared state structure type */N#define DYN$C_PSH_LCK 9 /* pshared lock structure type */N#define DYN$C_PSH_DAT 10 /* pshared data tag structure type */N/*  */N/* Poolzones specific data types */N/* */N#define DYN$C_PZ 144 /* Poolzones structure type */N#define DYN$C_PZ_PSH 1 /* pshared poolzone */N#define DYN$C_PZ_LCK 2 /* lock manager poolzone */N#define DYN$C_PZ_XFC 3 /* XFC poolzone */N/* */N/* Calibration specific data types */N/* */N#define DYN$C_CAL 145 /* CAL structure type */N/* */N/* Memory Mgt Structures */N/* */N#define DYN$C_MMG 146 /* Memory Management Structure */N#define DYN$C_MMG_DEL 1 /* DELPAG Control Structure */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus } #endif#pragma __standard #endif /* __DYNDEF_LOADED */ wwP1[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40  $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EFBDEF ***/#ifndef __EFBDEF_LOADED#define __EFBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* This structure represents an extended fork block. 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This structure is used in the definition of the */N/* LSB. */N/*-- */ N#d efine EFB$K_LENGTH 64 /* Size of the extended fork block */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _efb {N/* First get to the end of the VMS fork block. */#pragma __nomember_alignment char efb$b_filler [48];N unsigned int efb$l_inuse; /* LBS = fork block in use  */N/* LBC = fork block not in use */N unsigned int efb$l_count; /* Number of times block was used */N unsigned int efb$l_lstfrksch; /* Time fork was last scheduled */N unsigned int efb$l_lstfrktim; /* Time fork was last entered */ } EFB;   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EFBDEF_LOADED */ wwp[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************************************************* *******/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SDL V3.7 */F/* Source: 15-NOV-2017 12:10:41 $1$DGA8345:[LIB_H.SRC]EFIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EFIDEF ***/#ifndef __EFIDEF_LOADED#define __EFIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* A GUID */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _efi_guid {#pragma __nomember_alignment unsigned int efi$l_data1;# unsigned short int efi$w_data2;# unsigned short int efi$w_data3;" unsigned char efi$b_data4 [8]; } EFI_GUID;N/*++ */N/* EFI table header  */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif"typedef struct _efi_table_header {#pragma __nomember_alignment= unsigned __int64 efi$q_signature; /* Signature */N unsigned int efi$l_revision; /* Revision */N unsigned int  efi$l_headersize; /* Size of header in bytes */N unsigned int efi$l_crc32; /* CRC */N unsigned int efi$l_reserved_1; /* Reserved */ } EFI_TABLE_HEADER; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif&typedef struct _efi_runtime_services {#pragma __nomember_ali gnmentN EFI_TABLE_HEADER efi$r_runtime_services_hdr; /* Table header */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *efi$pq_get_time; /* Get time */#else" unsigned __int64 efi$pq_get_time;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer _size __long /* And set ptr size default to 64-bit pointers */N void *efi$pq_set_time; /* Set time */#else" unsigned __int64 efi$pq_set_time;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *efi$pq_get_wakeup_time; /* Get wakeup time */#else) unsigned __int64 efi$pq_get_wakeup_time; #endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *efi$pq_set_wakeup_time; /* Set wakeup time */#else) unsigned __int64 efi$pq_set_wakeup_time;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N vo id *efi$pq_set_virtual_address_map; /* Set virtual address map */#else1 unsigned __int64 efi$pq_set_virtual_address_map;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *efi$pq_convert_pointer; /* Convert pointer */#else) unsigned __int64 efi$pq_convert_pointer;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined when ever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *efi$pq_get_variable; /* Get variable */#else& unsigned __int64 efi$pq_get_variable;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *efi$pq_get_next_variable_name; /* Get next variable name  */#else0 unsigned __int64 efi$pq_get_next_variable_name;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *efi$pq_set_variable; /* Set variable */#else& unsigned __int64 efi$pq_set_variable;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_siz e __long /* And set ptr size default to 64-bit pointers */) void *efi$pq_get_next_high_mon_count;#else1 unsigned __int64 efi$pq_get_next_high_mon_count;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_reset_system;#else& unsigned __int64 efi$pq_reset_system;#endif } EFI_RUNTIME_SERVICES;N/*++  */N/* EFI Boot Services */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif#typedef struct _efi_boot_services {#pragma __nomember_alignmentN EFI_TABLE_HEADER efi$r_boot_services_h dr; /* Table header */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_raise_tpl;#else# unsigned __int64 efi$pq_raise_tpl;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_restore_tpl; #else% unsigned __int64 efi$pq_restore_tpl;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_allocate_pages;#else( unsigned __int64 efi$pq_allocate_pages;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ vo id *efi$pq_free_pages;#else$ unsigned __int64 efi$pq_free_pages;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_get_memory_map;#else( unsigned __int64 efi$pq_get_memory_map;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-b it pointers */ void *efi$pq_allocate_pool;#else' unsigned __int64 efi$pq_allocate_pool;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_free_pool;#else# unsigned __int64 efi$pq_free_pool;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set pt r size default to 64-bit pointers */ void *efi$pq_create_event;#else& unsigned __int64 efi$pq_create_event;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_set_timer;#else# unsigned __int64 efi$pq_set_timer;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __lo ng /* And set ptr size default to 64-bit pointers */ void *efi$pq_wait_for_event;#else( unsigned __int64 efi$pq_wait_for_event;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_signal_event;#else& unsigned __int64 efi$pq_signal_event;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __ required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_close_event;#else% unsigned __int64 efi$pq_close_event;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_check_event;#else% unsigned __int64 efi$pq_check_event;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas su pported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */) void *efi$pq_install_proto_interface;#else1 unsigned __int64 efi$pq_install_proto_interface;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */( void *efi$pq_reinst_proto_interface;#else0 unsigned __int64 efi$pq_reinst_proto_interface;#endifR#ifdef  __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */( void *efi$pq_uninst_proto_interface;#else0 unsigned __int64 efi$pq_uninst_proto_interface;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */! void *efi$pq_handle_protocol;#else) unsigne d __int64 efi$pq_handle_protocol;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */$ void *efi$pq_pc_handle_protocol;#else, unsigned __int64 efi$pq_pc_handle_protocol;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */* void * efi$pq_register_protocol_notify;#else2 unsigned __int64 efi$pq_register_protocol_notify;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_locate_handle;#else' unsigned __int64 efi$pq_locate_handle;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */$ void *efi$pq_locate_device_path;#else, unsigned __int64 efi$pq_locate_device_path;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */& void *efi$pq_install_config_table;#else. unsigned __int64 efi$pq_install_config_table;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#p ragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_image_load;#else$ unsigned __int64 efi$pq_image_load;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_image_start;#else% unsigned __int64 efi$pq_image_start;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragma s supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_exit;#else unsigned __int64 efi$pq_exit;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_image_unload;#else& unsigned __int64 efi$pq_image_unload;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */$ void *efi$pq_exit_boot_services;#else, unsigned __int64 efi$pq_exit_boot_services;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */* void *efi$pq_get_next_monotonic_count;#else2 unsigned __int64 efi$pq_get_next_monotonic_count;#endifR#ifd ef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_stall;#else unsigned __int64 efi$pq_stall;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */$ void *efi$pq_set_watchdog_timer;#else, unsigned __int64 efi$pq_set_watchdo g_timer;#endif } EFI_BOOT_SERVICES;N/*++ */N/* EFI Configuration Table */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif)typedef struct _efi_configur ation_table {#pragma __nomember_alignment EFI_GUID efi$r_vendor_guid;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_vendor_table;#else& unsigned __int64 efi$pq_vendor_table;#endif } EFI_CONFIGURATION_TABLE;N/*++ */N/* EFI system table   */N/*-- */  9#ifdef __cplusplus /* Define structure prototypes */struct _simple_input_interface;%struct _simple_text_output_interface;)struct _efi_simple_text_output_interface; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif"typedef struct _efi_system_table {#pragma __nomember_alignment, EFI_TABLE_HEADER efi$r_system_table_hdr;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */& short int *efi$pq_firmware_vendor;#else) unsigned __int64 efi$pq_firmware_vendor;#endif int efi$l_firmware_revision; int efi$l_reserved_2;R#ifdef __INITIAL_POINTER_SIZE /* De fined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */# void *efi$pq_console_in_handle;#else+ unsigned __int64 efi$pq_console_in_handle;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */2 struct _simple_input_interface *efi$pq_con_in;#else unsigned __int64 efi$pq_con_in; #endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */$ void *efi$pq_console_out_handle;#else, unsigned __int64 efi$pq_console_out_handle;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */9 struct _simple_text_output_interface *ef i$pq_con_out;#else! unsigned __int64 efi$pq_con_out;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */' void *efi$pq_standard_error_handle;#else/ unsigned __int64 efi$pq_standard_error_handle;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default t o 64-bit pointers */= struct _efi_simple_text_output_interface *efi$pq_std_err;#else! unsigned __int64 efi$pq_std_err;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */: struct _efi_runtime_services *efi$pq_runtime_services;#else* unsigned __int64 efi$pq_runtime_services;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas su pported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */4 struct _efi_boot_services *efi$pq_boot_services;#else' unsigned __int64 efi$pq_boot_services;#endif* __int64 efi$q_number_of_table_entries;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */@ struct _efi_configuration_table *efi$pq_configuration_table;#els e- unsigned __int64 efi$pq_configuration_table;#endif } EFI_SYSTEM_TABLE;N/*++ */N/* ESI (Estensible SAL Interface) entry pointer descriptor */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_align ment#endiftypedef struct _esi_entry {#pragma __nomember_alignmentN unsigned char efi$b_esi_entry_type; /* type == 0 */N char efi$b_esi_entry_reserved0 [7]; /* reserved */N __int64 efi$q_esi_entry_reserved1; /* reserved */N unsigned __int64 efi$q_esi_entry_proc_addr; /* Procedure code address */N unsigned __int64 efi$q_esi_entry_global_ptr; /* Procedure gp */N EFI_GUID efi$r_esi_entry_gui d; /* GUID */ } ESI_ENTRY;N/*++ */N/* ESI (Extensible SAL Interface) table */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _esi_table {#pragma __nomember_alignment= unsigned int efi$l_esi_signature; /* Signature */N unsigned int efi$l_esi_length; /* Length of entire structure */N unsigned short int efi$w_esi_revision; /* Revision */N unsigned short int efi$w_esi_entry_count; /* Number of array entries */N unsigned char efi$b_esi_check_sum; /* CRC */N char efi$b_esi_reserved_1 [7]; /* Reserved  */N unsigned short int efi$w_esi_sal_a_ver; /* SAL_A version */N unsigned short int efi$w_esi_sal_b_ver; /* SAL_B version */N char efi$t_esi_oem_id [32]; /* OEM ID */N char efi$t_esi_product_id [32]; /* Product ID */N char efi$b_esi_reserved_2 [8]; /* Reserved */N ESI_ENTRY efi$r_esi_entries [1]; /* Array of ESI entries */ } ESI_TABL E;N/*++ */N/* EFI memory descriptor */N/*-- */#define EFI$M_MEMORY_UC 0x1#define EFI$M_MEMORY_WC 0x2#define EFI$M_MEMORY_WT 0x4#define EFI$M_MEMORY_WB 0x8#define EFI$M_MEMORY_UCE 0x10*#define EFI$M_UNDEFINED 0x7FFFFFFFFFFFFFE0/#define EFI$M_MEMORY_RUNTIME 0x8000000000000000 c#if !defined (__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif'typedef struct _efi_memory_descriptor {#pragma __nomember_alignment unsigned int efi$l_type;" unsigned int efi$l_reserved_3;* unsigned __int64 efi$q_physical_start;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *efi$pq_virtual_start;#else' unsigned __int64 efi$pq_virtual_start;#endif+ unsigned __int64 efi$q_number_of_pages; __union {) unsigned __int64 efi$q_attribute; __struct {) unsigned efi$v_memory_uc : 1;) unsigned efi$v_memory_wc : 1;) unsigned efi$v_memory_wt : 1;) unsigned efi$v_memory_wb : 1;* unsigned efi$v_memory_uce : 1;, unsigned efi$v_undefined _1 : 32;, unsigned efi$v_undefined_2 : 26;. unsigned efi$v_memory_runtime : 1; } efi$r_attr_bits; } efi$r_attr_union;& unsigned __int64 efi$q_reserved_4; } EFI_MEMORY_DESCRIPTOR; #if !defined(__VAXC)8#define efi$q_attribute efi$r_attr_union.efi$q_attributeH#define efi$v_memory_uc efi$r_attr_union.efi$r_attr_bits.efi$v_memory_ucH#define efi$v_memory_wc efi$r_attr_union.efi$r_attr_bits.efi$v_memory_wcH#define efi$v_memory_wt efi$r_attr_uni on.efi$r_attr_bits.efi$v_memory_wtH#define efi$v_memory_wb efi$r_attr_union.efi$r_attr_bits.efi$v_memory_wbJ#define efi$v_memory_uce efi$r_attr_union.efi$r_attr_bits.efi$v_memory_uceR#define efi$v_memory_runtime efi$r_attr_union.efi$r_attr_bits.efi$v_memory_runtime"#endif /* #if !defined(__VAXC) */ $#define EFI$C_RESERVED_MEMORY_TYPE 0#define EFI$C_LOADER_CODE 1#define EFI$C_LOADER_DATA 2"#define EFI$C_BOOT_SERVICES_CODE 3"#define EFI$C_BOOT_SERVICES_DATA 4%#define EFI$C_RUNTIME_SERV ICES_CODE 5%#define EFI$C_RUNTIME_SERVICES_DATA 6##define EFI$C_CONVENTIONAL_MEMORY 7#define EFI$C_UNUSABLE_MEMORY 8##define EFI$C_ACPI_RECLAIM_MEMORY 9 #define EFI$C_ACPI_MEMORY_NVS 10!#define EFI$C_MEMORY_MAPPED_IO 11&#define EFI$C_MEM_MAP_IO_PORT_SPACE 12#define EFI$C_PAL_CODE 13 #define EFI$C_MAX_MEMORY_TYPE 14N/*++ */N/* Time */N/*--  */&#define EFI$M_TIME_ADJUST_DAYLIGHT 0x1"#define EFI$M_TIME_IN_DAYLIGHT 0x2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _efi_time {#pragma __nomember_alignmentN unsigned short int efi$w_year; /* 1998 - 20XX */N unsigned char efi$b_mont h; /* 1-12 */N unsigned char efi$b_day; /* 1-31 */N unsigned char efi$b_hour; /* 0-23 */N unsigned char efi$b_minute; /* 0-59 */N unsigned char efi$b_second; /* 0-59 */N char efi$b_reserved_5; /* */N unsigned int efi$l_nanosecond; /* 0-999,999,9!99 */N short int efi$w_time_zone; /* -1440 to 1440 or 2047 */ __union {& unsigned char efi$b_day_light; __struct {4 unsigned efi$v_time_adjust_daylight : 1;0 unsigned efi$v_time_in_daylight : 1;' unsigned efi$v_fill_0_ : 6; } efi$r_dl_struct; } efi$r_dl_union; char efi$b_reserved_6; } EFI_TIME; #if !defined(__VAXC)6#define efi$b_day_light efi$r_dl_union.efi$b "_day_light\#define efi$v_time_adjust_daylight efi$r_dl_union.efi$r_dl_struct.efi$v_time_adjust_daylightT#define efi$v_time_in_daylight efi$r_dl_union.efi$r_dl_struct.efi$v_time_in_daylight"#endif /* #if !defined(__VAXC) */ '#define EFI$C_UNSPECIFIED_TIMEZONE 2047#define EFI$C_ALL_HANDLES 0"#define EFI$C_BY_REGISTER_NOTIFY 1#define EFI$C_BY_PROTOCOL 2N/*++ */N/* Generic return status used by EFI calls # */N/*-- */#define EFI$C_SUCCESS 0#define EFI$C_LOAD_ERROR 1!#define EFI$C_INVALID_PARAMETER 2#define EFI$C_UNSUPPORTED 3#define EFI$C_BAD_BUFFER_SIZE 4 #define EFI$C_BUFFER_TOO_SMALL 5#define EFI$C_NOT_READY 6#define EFI$C_DEVICE_ERROR 7#define EFI$C_WRITE_PROTECTED 8 #define EFI$C_OUT_OF_RESOURCES 9!#define EFI$C_VOLUME_CORRUPTED 10#define EFI$C_VOLUME_FULL 11#define EFI$C_NO_MEDIA$ 12#define EFI$C_MEDIA_CHANGED 13#define EFI$C_NOT_FOUND 14#define EFI$C_ACCESS_DENIED 15#define EFI$C_NO_RESPONSE 16#define EFI$C_NO_MAPPING 17#define EFI$C_TIMEOUT 18#define EFI$C_NOT_STARTED 19 #define EFI$C_ALREADY_STARTED 20#define EFI$C_ABORTED 21#define EFI$C_ICMP_ERROR 22#define EFI$C_TFTP_ERROR 23#define EFI$C_PROTOCOL_ERROR 24%#define EFI$C_INCOMPATIBLE_VERSION 25##define EFI$C_SECURITY_VIOLATION 26#define EFI$C_CRC_ERROR 27#define EFI$C_END_OF_MEDIA 28 %#define EFI$C_END_OF_FILE 29!#define EFI$C_INVALID_LANGUAGE 30!#define EFI$C_COMPROMISED_DATA 31##define EFI$C_WARN_UNKNOWN_GLYPH 32$#define EFI$C_WARN_DELETE_FAILURE 33##define EFI$C_WARN_WRITE_FAILURE 34&#define EFI$C_WARN_BUFFER_TOO_SMALL 35 #define EFI$C_WARN_STALE_DATA 36 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr& size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EFIDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed' to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **(/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SDL V3 ).7 */G/* Source: 21-APR-1993 15:56:50 $1$DGA8345:[LIB_H.SRC]EIAFDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EIAFDEF ***/#ifndef __EIAFDEF_LOADED#define __EIAFDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr siz*e pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struc+t#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* EIAF - EXTENDED IMAGE ACTIVATOR FIXUP SECTION */N/* */N/* THE IMAGE ACTIVATOR FIXUP SECTION IS AN IMAGE SECTION THAT IS CREATED */N/* BY THE LINKER AND USED BY THE IMAGE , ACTIVATOR TO MODIFY THE IMAGE AS */N/* IT IS ACTIVATED. THIS IS DONE TO MAINTAIN THE POSITION INDEPENDENCE */N/* OF EXTERNAL REFERENCES. */N/*- */_#define EIAF$K_LENGTH 84 /* Length of fixed area (should be quadword aligned) */N#define EIAF$C_LENGTH 84 /* Length of fixed area */#define EIAF$S_EIAFDEF 84 typedef struct - _eiaf {N __struct { /* Version of this EIAF */N unsigned int eiaf$l_majorid; /* Major ID */N unsigned int eiaf$l_minorid; /* Minor ID */ } eiaf$r_version;N __union { /* Link for image activator use */ int eiaf$l_iaflink; __int64 eiaf$q_iaflink; } eiaf$r_iaflink;N __union { /* Link for shar .able image fixups */ int eiaf$l_fixuplnk; __int64 eiaf$q_fixuplnk; } eiaf$r_fixuplnk;N int eiaf$l_size; /* Size of fixed part of EIAF */ __union {N unsigned int eiaf$l_flags; /* Flags */ __struct {N unsigned eiaf$v_shr : 1; /* This is in a shareable image */( unsigned eiaf$v_fill_0_ : 7; } eiaf$r_flags_bits; } eiaf$r_flags_overlay;V / int eiaf$l_qrelfixoff; /* Offset to quadword relocation fixup data */V int eiaf$l_lrelfixoff; /* Offset to longword relocation fixup data */T int eiaf$l_qdotadroff; /* Offset to quadword .address fixup data */T int eiaf$l_ldotadroff; /* Offset to longword .address fixup data */O int eiaf$l_codeadroff; /* Offset to code address fixup data */O int eiaf$l_lpfixoff; /* Offset to linkage pair fixup data *0/P int eiaf$l_chgprtoff; /* Offset to isect change prot. data */N int eiaf$l_shlstoff; /* Offset to shareable image list */R int eiaf$l_shrimgcnt; /* Number of shareable images in shlst */W int eiaf$l_shlextra; /* Number of extra shareable images allowed */O int eiaf$l_permctx; /* Permanent sharable image context */N void *eiaf$l_base_va; /* Base address of the image itself */f 1int eiaf$l_lppsbfixoff; /* Offset to "linkage pair with procedure signature" fixups */ } EIAF; #if !defined(__VAXC)4#define eiaf$l_majorid eiaf$r_version.eiaf$l_majorid4#define eiaf$l_minorid eiaf$r_version.eiaf$l_minorid4#define eiaf$l_iaflink eiaf$r_iaflink.eiaf$l_iaflink4#define eiaf$q_iaflink eiaf$r_iaflink.eiaf$q_iaflink7#define eiaf$l_fixuplnk eiaf$r_fixuplnk.eiaf$l_fixuplnk7#define eiaf$q_fixuplnk eiaf$r_fixuplnk.eiaf$q_fixuplnk6#define eiaf$l_flags eiaf$r_flags_2overlay.eiaf$l_flagsD#define eiaf$v_shr eiaf$r_flags_overlay.eiaf$r_flags_bits.eiaf$v_shr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EIAFDEF_LOADED */ ww[UM/*******************3********************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterpris4e Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. 5 **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SDL V3.7 */G/* Source: 19-APR-1993 13:58:44 $1$DGA8345:[LIB_H.SRC]EICPDEF.SDL;1 *//******************************************************************* 6*************************************************************//*** MODULE $EICPDEF ***/#ifndef __EICPDEF_LOADED#define __EICPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __shor7t /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ 8 */N/* EICP - EXTENDED CHANGE IMAGE SECTION PROTECTION DATA */N/* */N/* THIS STRUCTURE IS USED IN THE IMAGE FIXUP SECTION BY THE LINKER */N/* TO INFORM THE IMAGE ACTIVATOR OF THE IMAGE SECTIONS THAT NEED */N/* THEIR PROTECTION CHANGED. */N/*- 9 */N#define EICP$K_LENGTH 16 /* size of one section's data */N#define EICP$C_LENGTH 16 /* size of one section's data */#define EICP$S_EICPDEF 16 typedef struct _eicp {Q __union { /* Virtual address of start of section */# unsigned int eicp$l_baseva;' unsigned __int64 eicp$q_baseva; } eicp$r_baseva;P unsigned int eicp$l_size; /* size in byt :es of the image section */N unsigned int eicp$l_newprt; /* new protection */ } EICP; #if !defined(__VAXC)1#define eicp$l_baseva eicp$r_baseva.eicp$l_baseva1#define eicp$q_baseva eicp$r_baseva.eicp$q_baseva"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required p;tr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EICPDEF_LOADED */ wwi[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR discl<osed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without = **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SD >L V3.7 */G/* Source: 22-APR-1993 10:52:45 $1$DGA8345:[LIB_H.SRC]EIHADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EIHADEF ***/#ifndef __EIHADEF_LOADED#define __EIHADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr? size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_s@truct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* EXTENDED IMAGE HEADER ACTIVATION SECTION OFFSETS */N/*- */N#define EIHA$K_LENGTH 48 /*SIZE OF ACTIVATION SECTION */N#define EIHA$C_LENGTH 48 A /*SIZE OF ACTIVATION SECTION */#define EIHA$S_EIHADEF 48 typedef struct _eiha {X unsigned int eiha$l_size; /* Size in bytes of EIHA(#transfers = size/8) */N unsigned int eiha$l_spare; /* Spare */N __union { /*FIRST TRANSFER ADDRESS */( unsigned __int64 eiha$q_tfradr1; __struct {( unsigned int eiha$l_tfradr1;* unsigned int eiha$l_tfradr1_h;$ B } eiha$r_tfradr1_fields;! } eiha$r_tfradr1_overlay;N __union { /*SECOND TRANSFER ADDRESS */( unsigned __int64 eiha$q_tfradr2; __struct {( unsigned int eiha$l_tfradr2;* unsigned int eiha$l_tfradr2_h;$ } eiha$r_tfradr2_fields;! } eiha$r_tfradr2_overlay;N __union { /*THIRD TRANSFER ADDRESS */( unsigned __int64 eiha$q_tfradr3; __ Cstruct {( unsigned int eiha$l_tfradr3;* unsigned int eiha$l_tfradr3_h;$ } eiha$r_tfradr3_fields;! } eiha$r_tfradr3_overlay;Q __union { /*FOURTH TRANSFER ADDRESS: Always ZERO */( unsigned __int64 eiha$q_tfradr4; __struct {( unsigned int eiha$l_tfradr4;* unsigned int eiha$l_tfradr4_h;$ } eiha$r_tfradr4_fields;! } eiha$r_tfradr4_overlay;N __union { D /*SHARED IMAGE INITIALIZATION */N unsigned int eiha$l_inishr; /*(valid if IHD$V_INISHR set) */' unsigned __int64 eiha$q_inishr; } eiha$r_inishr; } EIHA; #if !defined(__VAXC)<#define eiha$q_tfradr1 eiha$r_tfradr1_overlay.eiha$q_tfradr1R#define eiha$l_tfradr1 eiha$r_tfradr1_overlay.eiha$r_tfradr1_fields.eiha$l_tfradr1V#define eiha$l_tfradr1_h eiha$r_tfradr1_overlay.eiha$r_tfradr1_fields.eiha$l_tfradr1_h<#define eiha$q_tfradr2 eiha$r_Etfradr2_overlay.eiha$q_tfradr2R#define eiha$l_tfradr2 eiha$r_tfradr2_overlay.eiha$r_tfradr2_fields.eiha$l_tfradr2V#define eiha$l_tfradr2_h eiha$r_tfradr2_overlay.eiha$r_tfradr2_fields.eiha$l_tfradr2_h<#define eiha$q_tfradr3 eiha$r_tfradr3_overlay.eiha$q_tfradr3R#define eiha$l_tfradr3 eiha$r_tfradr3_overlay.eiha$r_tfradr3_fields.eiha$l_tfradr3V#define eiha$l_tfradr3_h eiha$r_tfradr3_overlay.eiha$r_tfradr3_fields.eiha$l_tfradr3_h<#define eiha$q_tfradr4 eiha$r_tfradr4_overlay.eiha$q_tfradr4R#defin Fe eiha$l_tfradr4 eiha$r_tfradr4_overlay.eiha$r_tfradr4_fields.eiha$l_tfradr4V#define eiha$l_tfradr4_h eiha$r_tfradr4_overlay.eiha$r_tfradr4_fields.eiha$l_tfradr4_h1#define eiha$l_inishr eiha$r_inishr.eiha$l_inishr1#define eiha$q_inishr eiha$r_inishr.eiha$q_inishr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-Gdefined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EIHADEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, dHuplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to Ianyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:2 J2:36 by OpenVMS SDL V3.7 */G/* Source: 27-MAR-1998 15:38:59 $1$DGA8345:[LIB_H.SRC]EIHDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EIHDDEF ***/#ifndef __EIHDDEF_LOADED#define __EIHDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* DeKfined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define L__struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */Z/* EXTENDED IMAGE HEADER RECORD DEFINITIONS - FIRST RECORD OF THE EXTENDED IMAGE HEADER */N/*- */N#define EIHD$K_MAJORID 3 /* Major id constant */N#defMine EIHD$K_MINORID 0 /* Minor id constant */N#define EIHD$K_MINORID_64 1 /* Alt Minor id constant */N#define EIHD$K_EXE 1 /* Executable image */N#define EIHD$K_LIM 2 /* Linkable image */N#define EIHD$C_MINCODE 0 /* Low bound of ALIAS values */N#define EIHD$C_NATIVE 0 /* Alpha native mode image */N#define EIHD$C_CLI 1 N /* Image is a CLI, run LOGINOUT */N#define EIHD$C_MAXCODE 1 /* High bound of ALIAS values */#define EIHD$M_LNKDEBUG 0x1#define EIHD$M_LNKNOTFR 0x2#define EIHD$M_NOP0BUFS 0x4#define EIHD$M_PICIMG 0x8#define EIHD$M_P0IMAGE 0x10#define EIHD$M_DBGDMT 0x20#define EIHD$M_INISHR 0x40#define EIHD$M_XLATED 0x80"#define EIHD$M_BIND_CODE_SEC 0x100"#define EIHD$M_BIND_DATA_SEC 0x200#define EIHD$M_MKTHREADS 0x400#define EIHD$M_UPCALLS 0x800#define EIOHD$M_OMV_READY 0x1000##define EIHD$M_EXT_BIND_SECT 0x2000N#define EIHD$K_LENGTH 104 /* Length of fixed area */N#define EIHD$C_LENGTH 104 /* Length of fixed area */N#define EIHD$K_LENGTH_97 112 /* Length of fixed area */N#define EIHD$K_ALIAS_MINCODE -1 /* Low bound of ALIAS values */N/* Following are reserved but not used by the Alpha linker */N#define EIHD$K_VAX -1 /* NPative mode image */N#define EIHD$K_RSX 0 /* RSX image produced by TKB */N#define EIHD$K_BPA 1 /* BASIC plus analog */`#define EIHD$K_ALIAS 2 /* Last 126 bytes contains ASCIC of image to activate */N#define EIHD$K_VAX_CLI 3 /* Image is a CLI, run LOGINOUT */N#define EIHD$K_PMAX 4 /* PMAX system image */_/* Alpha linker writes this value into last word of Q 1st header block for system images only */#define EIHD$K_ALPHA 5N#define EIHD$K_ALIAS_MAXCODE 5 /* High bound of ALIAS values */N#define EIHD$S_EIHDDEF 512 /* Old size name - synonym */ typedef struct _eihd {N __struct { /* Version of this EIHD */N unsigned int eihd$l_majorid; /* Major id */N unsigned int eihd$l_minorid; /* Minor id */ R} eihd$r_version;N unsigned int eihd$l_size; /* Size in bytes of image header */N unsigned int eihd$l_isdoff; /* Byte offset to ISD list */N unsigned int eihd$l_activoff; /* Byte offset to activation data */Y unsigned int eihd$l_symdbgoff; /* Byte offset to symbol table and debug data */N unsigned int eihd$l_imgidoff; /* Byte offset to image ident data */N unsigned int eihd$l_patchoff; /* Byte offset to patch data S */U __union { /* Relative virtual address of fixup info */ void *eihd$l_iafva; __int64 eihd$q_iafva; } eihd$r_iafva;X __union { /* Relative virtual address of symbol vector */ void *eihd$l_symvva; __int64 eihd$q_symvva; } eihd$r_symvva;T unsigned int eihd$l_version_array_off; /* Byte offset to version number array */N unsigned int eihd$l_imgtype; /* Image type T */N/* */N/* IMAGE TYPE CODES */N/* */N unsigned int eihd$l_subtype; /* Code to use secondary image name */N/****************************************** */N/* */N/* DeUfine legal range of SUBTYPE constants. MINCODE must be equal to the */I/* lowest value and MAXCODE must be equal to the highest value. */N/* */[ unsigned int eihd$l_imgiocnt; /* size in bytes of image i/o section requested */N/*0 if default */N unsigned int eihd$l_iochancnt; /* # channels requested */N unsigned __int64 e Vihd$q_privreqs; /* requested privelege mask */N unsigned int eihd$l_hdrblkcnt; /* # header diskblocks */ __union {N unsigned int eihd$l_lnkflags; /* Linker produced image flags */ __struct {N unsigned eihd$v_lnkdebug : 1; /* Full debugging requested */O unsigned eihd$v_lnknotfr : 1; /* First transfer address missing */U unsigned eihd$v_nop0bufs : 1; /* RMS use of P0 for image i/o disabled */NW unsigned eihd$v_picimg : 1; /* Image is position independent */N unsigned eihd$v_p0image : 1; /* Image is in P0 space only */N unsigned eihd$v_dbgdmt : 1; /* Image header has dmt fields */X unsigned eihd$v_inishr : 1; /* Transfer array contains valid IHA$L_INISHR */N unsigned eihd$v_xlated : 1; /* Translated image */a unsigned eihd$v_bind_code_sec : 1; /* EXE image sections can be put into S0 if set *X/b unsigned eihd$v_bind_data_sec : 1; /* DATA image sections can be put into S0 if set */P unsigned eihd$v_mkthreads : 1; /* Multiple kernel threads enabled */N unsigned eihd$v_upcalls : 1; /* Upcalls enabled */X unsigned eihd$v_omv_ready : 1; /* image may be correctly processed by OMV */e unsigned eihd$v_ext_bind_sect : 1; /* isects may be moved, if extended fixups applied. */N/* this applies to both code and data section Ys. */( unsigned eihd$v_fill_0_ : 2;# } eihd$r_lnkflags_bits;" } eihd$r_lnkflags_overlay;U unsigned int eihd$l_ident; /* GBL SEC ident value for linkable image */Y unsigned int eihd$l_sysver; /* SYS$K_VERSION or 0 if not linked with exec */N __struct { /* Linker control fields */N unsigned char eihd$b_matchctl; /* Linker match control */N unsignedZ char eihd$b_fill_1; /* Spares */N unsigned char eihd$b_fill_2; /* Spares */N unsigned char eihd$b_fill_3; /* Spares */R unsigned int eihd$l_symvect_size; /* Size of the symbol vector in bytes */{ unsigned int eihd$l_virt_mem_block_size; /* Virtual memory size used for link (value given to /BPAGE, power of 2 */ } eihd$r_control;N/* from 9[ to 16) */P unsigned int eihd$l_ext_fixup_off; /* Byte offset to extended fixup data */U unsigned int eihd$l_noopt_psect_off; /* Byte offset to no_optimize psect table */b char eihd$t_skip [398]; /* ALIAS is last word in 512 byte block of system image */O unsigned short int eihd$w_alias; /* CODE identifies image type to MOM */N/****************************************** */N/* \ */P/* Define legal range of ALIAS constants. ALIAS_MINCODE must be equal to the */I/* lowest value and ALIAS_MAXCODE must be equal to the highest value. */N/* */ } EIHD; #if !defined(__VAXC)4#define eihd$l_majorid eihd$r_version.eihd$l_majorid4#define eihd$l_minorid eihd$r_version.eihd$l_minorid.#define eihd$l_iafva eihd$r_iafva.eihd$l_iafva.#define eihd$q_iafva eihd$r_ia ]fva.eihd$q_iafva1#define eihd$l_symvva eihd$r_symvva.eihd$l_symvva1#define eihd$q_symvva eihd$r_symvva.eihd$q_symvva?#define eihd$l_lnkflags eihd$r_lnkflags_overlay.eihd$l_lnkflagsI#define eihd$r_lnkflags_bits eihd$r_lnkflags_overlay.eihd$r_lnkflags_bits<#define eihd$v_lnkdebug eihd$r_lnkflags_bits.eihd$v_lnkdebug<#define eihd$v_lnknotfr eihd$r_lnkflags_bits.eihd$v_lnknotfr<#define eihd$v_nop0bufs eihd$r_lnkflags_bits.eihd$v_nop0bufs8#define eihd$v_picimg eihd$r_lnkflags_bits.eihd$v_picimg ^:#define eihd$v_p0image eihd$r_lnkflags_bits.eihd$v_p0image8#define eihd$v_dbgdmt eihd$r_lnkflags_bits.eihd$v_dbgdmt8#define eihd$v_inishr eihd$r_lnkflags_bits.eihd$v_inishr8#define eihd$v_xlated eihd$r_lnkflags_bits.eihd$v_xlatedF#define eihd$v_bind_code_sec eihd$r_lnkflags_bits.eihd$v_bind_code_secF#define eihd$v_bind_data_sec eihd$r_lnkflags_bits.eihd$v_bind_data_sec>#define eihd$v_mkthreads eihd$r_lnkflags_bits.eihd$v_mkthreads:#define eihd$v_upcalls eihd$r_lnkflags_bits.eihd$v_upcalls>#d _efine eihd$v_omv_ready eihd$r_lnkflags_bits.eihd$v_omv_readyF#define eihd$v_ext_bind_sect eihd$r_lnkflags_bits.eihd$v_ext_bind_sect6#define eihd$b_matchctl eihd$r_control.eihd$b_matchctl2#define eihd$b_fill_1 eihd$r_control.eihd$b_fill_12#define eihd$b_fill_2 eihd$r_control.eihd$b_fill_22#define eihd$b_fill_3 eihd$r_control.eihd$b_fill_3>#define eihd$l_symvect_size eihd$r_control.eihd$l_symvect_sizeL#define eihd$l_virt_mem_block_size eihd$r_control.eihd$l_virt_mem_block_size"#endif /* #if !de`fined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EIHDDEF_LOADED */ ww[UM/***************************************************************************/M/** a **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **b/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********************c******************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SDL V3.7 */G/* Source: 03-MAY-1993 13:36:54 $1$DGA8345:[LIB_H.SRC]EIHIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EIHIDEF ***/#ifndef __EIHIDEF_dLOADED#define __EIHIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#defeine __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* EXTENDED IMAGE HEADER IDENTIFICATIO fN SECTION OFFSETS */N/*- */#define EIHI$K_MAJORID 1#define EIHI$K_MINORID 2R#define EIHI$K_LENGTH 104 /*LENGTH OF IMAGE HEADER IDENT SECTION */R#define EIHI$C_LENGTH 104 /*LENGTH OF IMAGE HEADER IDENT SECTION */N#define EIHI$S_EIHIDEF 104 /* Old size name - synonym */ typedef struct _eihi {N __struct { /* Version of thgis EIHP */N unsigned int eihi$l_majorid; /* Major ID */N unsigned int eihi$l_minorid; /* Minor ID */ } eihi$r_version;Q unsigned __int64 eihi$q_linktime; /*DATE AND TIME THIS IMAGE WAS LINKED */N/*STANDARD SYSTEM QUADWORD FORMAT */N char eihi$t_imgnam [40]; /*IMAGE NAME STRING */N char eihi$t_imgid [16]; /*IMAGE IDhENT STRING */N char eihi$t_linkid [16]; /*LINKER IDENT STRING */N char eihi$t_imgbid [16]; /*IMAGE BUILD IDENT STRING */ } EIHI; #if !defined(__VAXC)4#define eihi$l_majorid eihi$r_version.eihi$l_majorid4#define eihi$l_minorid eihi$r_version.eihi$l_minorid"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#piragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EIHIDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprijse Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is nokt **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************************* l*************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */G/* Source: 20-APR-1993 11:10:52 $1$DGA8345:[LIB_H.SRC]EIHPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EIHPDEF ***/#ifndef __EIHPDEF_LOADED#define __EIHPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __savem#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __strunct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* EXTENDED IMAGE HEADER PATCH SECTION OFFSETS */N/*- */N#define EIHP$K_LENGTH 60 o /*LENGTH OF PATCH HEADER SECTION */N#define EIHP$C_LENGTH 60 /*LENGTH OF PATCH HEADER SECTION */#define EIHP$S_EIHPDEF 60 typedef struct _eihp {N __struct { /* Version of this EIHP */N unsigned int eihp$l_majorid; /* Major ID */N unsigned int eihp$l_minorid; /* Minor ID */ } eihp$r_version;N unsigned int eihp$l_eco1; /*DEC ECO pLEVELS 1-32 */N unsigned int eihp$l_eco2; /*DEC ECO LEVELS 33-64 */N unsigned int eihp$l_eco3; /*DEC ECO LEVELS 65-98 */N unsigned int eihp$l_eco4; /*USER ECO LEVELS 99-132 */U unsigned int eihp$l_patcomtxt; /*PATCH COMMAND TEXT VIRTUAL BLOCK NUMBER */N unsigned int eihp$l_rw_patsiz; /*SIZE OF FREE RW PATCH AREA */Q __union { /*VIR ADDR OF NEXT FREE RW P qATCH AREA */& unsigned int eihp$l_rw_patadr;* unsigned __int64 eihp$q_rw_patadr; } eihp$r_rw_patadr;N unsigned int eihp$l_ro_patsiz; /*SIZE OF FREE RO PATCH AREA */Q __union { /*VIR ADDR OF NEXT FREE RO PATCH AREA */& unsigned int eihp$l_ro_patadr;* unsigned __int64 eihp$q_ro_patadr; } eihp$r_ro_patadr;N unsigned __int64 eihp$q_patdate; /*DATE OF MOST RECENT PATCH */ } EIHP;  r#if !defined(__VAXC)4#define eihp$l_majorid eihp$r_version.eihp$l_majorid4#define eihp$l_minorid eihp$r_version.eihp$l_minorid:#define eihp$l_rw_patadr eihp$r_rw_patadr.eihp$l_rw_patadr:#define eihp$q_rw_patadr eihp$r_rw_patadr.eihp$q_rw_patadr:#define eihp$l_ro_patadr eihp$r_ro_patadr.eihp$l_ro_patadr:#define eihp$q_ro_patadr eihp$r_ro_patadr.eihp$q_ro_patadr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever pstr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EIHPDEF_LOADED */ ww -[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licetnsed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed uby VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************** v*********************************************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */G/* Source: 19-APR-1993 14:03:10 $1$DGA8345:[LIB_H.SRC]EIHSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EIHSDEF ***/#ifndef __EIHSDEF_LOADED#define __EIHSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#prawgma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params x...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* IMAGE HEADER SYMBOL TABLE AND DEBUG SECTION OFFSETS */N/*- y*/#define EIHS$K_MAJORID 1#define EIHS$K_MINORID 1N#define EIHS$K_LENGTH 32 /*LENGTH OF SYMBOL TABLE SECTION */N#define EIHS$C_LENGTH 32 /*LENGTH OF SYMBOL TABLE SECTION */#define EIHS$S_EIHSDEF 32 typedef struct _eihs {N __struct { /* Version of this EIHP */N unsigned int eihs$l_majorid; /* Major ID */N unsigned int eihs$l_minorid; /* Minor ID z */ } eihs$r_version;U unsigned int eihs$l_dstvbn; /*DEBUG SYMBOL TABLE VIRTUAL BLOCK NUMBER */N unsigned int eihs$l_dstsize; /*DEBUG SYMBOL SIZE IN BYTES */V unsigned int eihs$l_gstvbn; /*GLOBAL SYMBOL TABLE VIRTUAL BLOCK NUMBER */N unsigned int eihs$l_gstsize; /*GLOBAL SYMBOL TABLE RECORD COUNT */N unsigned int eihs$l_dmtvbn; /*VBN OF DMT INFORMATION */N unsigned int eihs$l_dmtbytes; /*LENGTH OF DMT {INFO */ } EIHS; #if !defined(__VAXC)4#define eihs$l_majorid eihs$r_version.eihs$l_majorid4#define eihs$l_minorid eihs$r_version.eihs$l_minorid"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard  |#endif /* __EIHSDEF_LOADED */ ww@{[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. } **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. ~ **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */H/* Source: 16-DEC-1993 14:32:49 $1$DGA8345:[LIB_H.SRC]EIHVNDE F.SDL;1 *//********************************************************************************************************************************//*** MODULE $EIHVNDEF ***/#ifndef __EIHVNDEF_LOADED#define __EIHVNDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif *#define EIHVN$M_SUBVERSION_MINOR_ID 0xFFFF.#define EIHVN$M_SUBVERSION_MAJOR_ID 0xFFFF0000 $typedef struct _eimg_version_array {R unsigned int eihvn$l_subsystem_mask; /* Bit mask of nonzero version numbers */ __union {N unsigned int eihvn$l_subversion_array; /* First array element */ __struct {X unsigned eihvn$v_subversion_minor_id : 16; /* Minor ID for each component */X  unsigned eihvn$v_subversion_major_id : 16; /* Major ID for each component */ } eihvn$r_fill_1_; } eihvn$r_fill_0_; } EIMG_VERSION_ARRAY; #if !defined(__VAXC)I#define eihvn$l_subversion_array eihvn$r_fill_0_.eihvn$l_subversion_array_#define eihvn$v_subversion_minor_id eihvn$r_fill_0_.eihvn$r_fill_1_.eihvn$v_subversion_minor_id_#define eihvn$v_subversion_major_id eihvn$r_fill_0_.eihvn$r_fill_1_.eihvn$v_subversion_major_id"#endif /* #if !defined(__VAXC) */ )#define EIHVN$M_VERSION_MINOR_ID 0xFFFFFF+#define EIHVN$M_VERSION_MAJOR_ID 0xFF000000 &typedef struct _eimg_overall_version { __union {! int eihvn$l_version_bits; __struct {N unsigned eihvn$v_version_minor_id : 24; /* Minor ID of SYS.STB */N unsigned eihvn$v_version_major_id : 8; /* Major ID of SYS.STB */ } eihvn$r_fill_3_; } eihvn$r_fill_2_; } EIMG_OVERALL_VERSION; #if !defined(__VAXC)Y#define eihvn$v_ version_minor_id eihvn$r_fill_2_.eihvn$r_fill_3_.eihvn$v_version_minor_idY#define eihvn$v_version_major_id eihvn$r_fill_2_.eihvn$r_fill_3_.eihvn$v_version_major_id"#endif /* #if !defined(__VAXC) */ #define EIHVN$K_LENGTH 132#define EIHVN$C_LENGTH 132 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EIHVNDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */J/* Source:  13-APR-1996 16:32:46 $1$DGA8345:[LIB_H.SRC]EISABUSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EISABUSDEF ***/#ifndef __EISABUSDEF_LOADED#define __EISABUSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* This file describes the layout of EISA CSR space. It is based */N/* on the EISA spec, V3.10 BCPR Service, INC. */N/* */"#define EISA$M_PIC_L_ICW1_ICW4 0x1"#define EISA$M_PIC_L_ICW1_SNGL 0x2 #define EISA$M_PIC_L_OCW2_L0 0x1 #define EISA$M_PIC_L_OCW2_L1 0x2 #define EISA$M_PIC_L_OCW2_L2 0x4"#define EISA$M_PIC_L_OCW2_EOI 0x20!#define EISA$M_PIC_L_OCW2_SL 0x40 #define EISA$M_PIC_L_OCW2_R 0x80!#define EISA$M_PIC_L_OCW3_RIS 0x1 #define EISA$M_PIC_L_OCW3_RR 0x2#define EISA$M_PIC_L_OCW3_P 0x4"#define EISA$M_PIC_L_OCW3_SMM 0x20##define EISA$M_PIC_L_OCW3_ESMM 0x40$#define EISA$M_PIC_L_ICW2_ZEROES 0x7"#define EISA$M_PIC_L_ICW2_VEC 0xF8(#define EISA$M_PIC_L_ICW3_IRQ0_SLAVE 0x1(#define EISA$M_PIC_L_ICW3_IRQ1_SLAVE 0x2(#define EISA$M_PIC_L_ICW3_IRQ2_SLAVE 0x4(#define EISA$M_PIC_L_ICW3_IRQ3_SLAVE 0x8)#define EISA$M_PIC_L_ICW3_IRQ4_SLAVE 0x10)#define EISA$M_PIC_L_ICW3_IRQ5_SLAVE 0x20)#define EISA$M_PIC_L_ICW3_IRQ6_SLAVE 0x40)#define EISA$M_PIC_L_ICW3_IRQ7_SLAVE 0x80"#define EISA$M_PIC_L_ICW4_MODE 0x1"#define EISA$M_PIC_L_ICW4_AEOI 0x2##define EISA$M_PIC_L_ICW4_BUFF 0x18##define EISA$M_PIC_L_ICW4_NEST 0x20##define EISA$M_PIC_L_OCW1_MASK 0xFF& #define EISA$M_PIC_L_T1_SYSTIM_BCD 0x1'#define EISA$M_PIC_L_T1_SYSTIM_MODE 0xE&#define EISA$M_PIC_L_T1_SYSTIM_RW 0x30(#define EISA$M_PIC_L_T1_SYSTIM_STAT 0x40'#define EISA$M_PIC_L_T1_SYSTIM_OUT 0x80##define EISA$M_PIC_L_T1_REF_BCD 0x1$#define EISA$M_PIC_L_T1_REF_MODE 0xE##define EISA$M_PIC_L_T1_REF_RW 0x30%#define EISA$M_PIC_L_T1_REF_STAT 0x40$#define EISA$M_PIC_L_T1_REF_OUT 0x80$#define EISA$M_PIC_L_T1_SPKR_BCD 0x1%#define EISA$M_PIC_L_T1_SPKR_MODE 0xE$#define EISA$M_PIC_L_T1_SPKR_RW 0x30&#define EISA$M_PIC_L_T1_SPKR_STAT 0x40%#define EISA$M_PIC_L_T1_SPKR_OUT 0x80$#define EISA$M_PIC_L_T1_CTRL_BCD 0x1%#define EISA$M_PIC_L_T1_CTRL_MODE 0xE(#define EISA$M_PIC_L_T1_CTRL_CNTLAT 0x30(#define EISA$M_PIC_L_T1_CTRL_CNTSEL 0xC0$#define EISA$M_PIC_L_T2_FLSF_BCD 0x1%#define EISA$M_PIC_L_T2_FLSF_MODE 0xE$#define EISA$M_PIC_L_T2_FLSF_RW 0x30&#define EISA$M_PIC_L_T2_FLSF_STAT 0x40%#define EISA$M_PIC_L_T2_FLSF_OUT 0x80&#define EISA$M_PIC_L_T2_CPUSPD_BCD 0x1'#define EISA$M_PIC_L_T2_CPUSPD_MODE 0xE&#define EISA$M_PIC_L_T2_CPUSPD_RW 0x30(#define EISA$M_PIC_L_T2_CPUSPD_STAT 0x40'#define EISA$M_PIC_L_T2_CPUSPD_OUT 0x80$#define EISA$M_PIC_L_T2_CTRL_BCD 0x1%#define EISA$M_PIC_L_T2_CTRL_MODE 0xE(#define EISA$M_PIC_L_T2_CTRL_CNTLAT 0x30(#define EISA$M_PIC_L_T2_CTRL_CNTSEL 0xC0"#define EISA$M_PIC_L_NMICSR_T1 0x1$#define EISA$M_PIC_L_NMICSR_SPKR 0x2"#define EISA$M_PIC_L_NMICSR_PE 0x4%#define EISA$M_PIC_L_NMICSR_IOCHK 0x8$#define EISA$M_PIC_L_NMICSR_REF 0x10&#define EISA$M_PIC_L_NMICSR_INTM1 0x20'#define EISA$M_PIC_L_NMICSR_NMIINT 0x40$#define EISA$M_PIC_L_NMICSR_PAR 0x80'#define EISA$M_PIC_L_NMIRTC_CLKADR 0x7F&#define EISA$M_PIC_L_NMIRTC_ENDIS 0x80"#define EISA$M_PIC_H_ICW1_ICW4 0x1"#define EISA$M_PIC_H_ICW1_SNGL 0x2 #define EISA$M_PIC_H_OCW2_L0 0x1 #define EISA$M_PIC_H_OCW2_L1 0x2 #define EISA$M_PIC_H_OCW2_L2 0x4"#define EISA$M_PIC_H_OCW2_EOI 0x20!#define EISA$M_PIC_H_OCW2_SL 0x40 #define EISA$M_PIC_H_OCW2_R 0x80!#define EISA$M_PIC_H_OCW3_RIS 0x1  #define EISA$M_PIC_H_OCW3_RR 0x2#define EISA$M_PIC_H_OCW3_P 0x4"#define EISA$M_PIC_H_OCW3_SMM 0x20##define EISA$M_PIC_H_OCW3_ESMM 0x40$#define EISA$M_PIC_H_ICW2_ZEROES 0x7"#define EISA$M_PIC_H_ICW2_VEC 0xF8(#define EISA$M_PIC_H_ICW3_IRQ0_SLAVE 0x1(#define EISA$M_PIC_H_ICW3_IRQ1_SLAVE 0x2(#define EISA$M_PIC_H_ICW3_IRQ2_SLAVE 0x4(#define EISA$M_PIC_H_ICW3_IRQ3_SLAVE 0x8)#define EISA$M_PIC_H_ICW3_IRQ4_SLAVE 0x10)#define EISA$M_PIC_H_ICW3_IRQ5_SLAVE 0x20)#define EISA$M_PIC_H_ICW3_IRQ6_SLAVE 0x40)#define EISA$M_PIC_H_ICW3_IRQ7_SLAVE 0x80"#define EISA$M_PIC_H_ICW4_MODE 0x1"#define EISA$M_PIC_H_ICW4_AEOI 0x2##define EISA$M_PIC_H_ICW4_BUFF 0x18##define EISA$M_PIC_H_ICW4_NEST 0x20##define EISA$M_PIC_H_OCW1_MASK 0xFF&#define EISA$M_PIC_EXNMICSR_BUSRST 0x1$#define EISA$M_PIC_EXNMICSR_ENIO 0x2$#define EISA$M_PIC_EXNMICSR_FSEN 0x4$#define EISA$M_PIC_EXNMICSR_TOEN 0x8$#define EISA$M_PIC_EXNMICSR_IOP 0x20##define EISA$M_PIC_EXNMICSR_BT 0x40&#define EISA$M_PIC_EXNMICSR_FSINT 0x80&#define EISA$M_PIC_EISA_BUSMAS_SL1 0x1&#define EISA$M_PIC_EISA_BUSMAS_SL2 0x2&#define EISA$M_PIC_EISA_BUSMAS_SL3 0x4&#define EISA$M_PIC_EISA_BUSMAS_SL4 0x8'#define EISA$M_PIC_EISA_BUSMAS_SL5 0x10'#define EISA$M_PIC_EISA_BUSMAS_SL6 0x20'#define EISA$M_PIC_EISA_BUSMAS_SL7 0x40&#define EISA$M_PIC_CTRL1_EDGE_INT3 0x8'#define EISA$M_PIC_CTRL1_EDGE_INT4 0x10'#define EISA$M_PIC_CTRL1_EDGE_INT5 0x20'#define EISA$M_PIC_CTRL1_EDGE_INT6 0x40'#define EISA$M_PIC_CTRL1_EDGE_INT7 0x80&#defin e EISA$M_PIC_CTRL2_EDGE_INT9 0x2'#define EISA$M_PIC_CTRL2_EDGE_INT10 0x4'#define EISA$M_PIC_CTRL2_EDGE_INT11 0x8(#define EISA$M_PIC_CTRL2_EDGE_INT12 0x10(#define EISA$M_PIC_CTRL2_EDGE_INT14 0x40(#define EISA$M_PIC_CTRL2_EDGE_INT15 0x80"#define EISA$M_SLOT1_PID_CHAR2 0x3##define EISA$M_SLOT1_PID_CHAR1 0x7C%#define EISA$M_SLOT1_PID_CHAR3 0x1F00*#define EISA$M_SLOT1_PID_CHAR2_CONT 0xE000*#define EISA$M_SLOT1_PID_PROD_NUM1 0xF0000+#define EISA$M_SLOT1_PID_PROD_NUM2 0xF00000+#define EISA$M _SLOT1_PID_REV_NUM1 0xF000000-#define EISA$M_SLOT1_PID_PROD_NUM3 0xF0000000"#define EISA$M_SLOT2_PID_CHAR2 0x3##define EISA$M_SLOT2_PID_CHAR1 0x7C%#define EISA$M_SLOT2_PID_CHAR3 0x1F00*#define EISA$M_SLOT2_PID_CHAR2_CONT 0xE000*#define EISA$M_SLOT2_PID_PROD_NUM1 0xF0000+#define EISA$M_SLOT2_PID_PROD_NUM2 0xF00000+#define EISA$M_SLOT2_PID_REV_NUM1 0xF000000-#define EISA$M_SLOT2_PID_PROD_NUM3 0xF0000000"#define EISA$M_SLOT3_PID_CHAR2 0x3##define EISA$M_SLOT3_PID_CHAR1 0x7C%#define EI SA$M_SLOT3_PID_CHAR3 0x1F00*#define EISA$M_SLOT3_PID_CHAR2_CONT 0xE000*#define EISA$M_SLOT3_PID_PROD_NUM1 0xF0000+#define EISA$M_SLOT3_PID_PROD_NUM2 0xF00000+#define EISA$M_SLOT3_PID_REV_NUM1 0xF000000-#define EISA$M_SLOT3_PID_PROD_NUM3 0xF0000000"#define EISA$M_SLOT4_PID_CHAR2 0x3##define EISA$M_SLOT4_PID_CHAR1 0x7C%#define EISA$M_SLOT4_PID_CHAR3 0x1F00*#define EISA$M_SLOT4_PID_CHAR2_CONT 0xE000*#define EISA$M_SLOT4_PID_PROD_NUM1 0xF0000+#define EISA$M_SLOT4_PID_PROD_NUM2 0xF00000+ #define EISA$M_SLOT4_PID_REV_NUM1 0xF000000-#define EISA$M_SLOT4_PID_PROD_NUM3 0xF0000000"#define EISA$M_SLOT5_PID_CHAR2 0x3##define EISA$M_SLOT5_PID_CHAR1 0x7C%#define EISA$M_SLOT5_PID_CHAR3 0x1F00*#define EISA$M_SLOT5_PID_CHAR2_CONT 0xE000*#define EISA$M_SLOT5_PID_PROD_NUM1 0xF0000+#define EISA$M_SLOT5_PID_PROD_NUM2 0xF00000+#define EISA$M_SLOT5_PID_REV_NUM1 0xF000000-#define EISA$M_SLOT5_PID_PROD_NUM3 0xF0000000"#define EISA$M_SLOT6_PID_CHAR2 0x3##define EISA$M_SLOT6_PID_CHAR1 0x7 C%#define EISA$M_SLOT6_PID_CHAR3 0x1F00*#define EISA$M_SLOT6_PID_CHAR2_CONT 0xE000*#define EISA$M_SLOT6_PID_PROD_NUM1 0xF0000+#define EISA$M_SLOT6_PID_PROD_NUM2 0xF00000+#define EISA$M_SLOT6_PID_REV_NUM1 0xF000000-#define EISA$M_SLOT6_PID_PROD_NUM3 0xF0000000"#define EISA$M_SLOT7_PID_CHAR2 0x3##define EISA$M_SLOT7_PID_CHAR1 0x7C%#define EISA$M_SLOT7_PID_CHAR3 0x1F00*#define EISA$M_SLOT7_PID_CHAR2_CONT 0xE000*#define EISA$M_SLOT7_PID_PROD_NUM1 0xF0000+#define EISA$M_SLOT7_PID_PROD_NU M2 0xF00000+#define EISA$M_SLOT7_PID_REV_NUM1 0xF000000-#define EISA$M_SLOT7_PID_PROD_NUM3 0xF0000000"#define EISA$M_SLOT8_PID_CHAR2 0x3##define EISA$M_SLOT8_PID_CHAR1 0x7C%#define EISA$M_SLOT8_PID_CHAR3 0x1F00*#define EISA$M_SLOT8_PID_CHAR2_CONT 0xE000*#define EISA$M_SLOT8_PID_PROD_NUM1 0xF0000+#define EISA$M_SLOT8_PID_PROD_NUM2 0xF00000+#define EISA$M_SLOT8_PID_REV_NUM1 0xF000000-#define EISA$M_SLOT8_PID_PROD_NUM3 0xF0000000"#define EISA$M_SLOT9_PID_CHAR2 0x3##define EISA$M_SLOT9 _PID_CHAR1 0x7C%#define EISA$M_SLOT9_PID_CHAR3 0x1F00*#define EISA$M_SLOT9_PID_CHAR2_CONT 0xE000*#define EISA$M_SLOT9_PID_PROD_NUM1 0xF0000+#define EISA$M_SLOT9_PID_PROD_NUM2 0xF00000+#define EISA$M_SLOT9_PID_REV_NUM1 0xF000000-#define EISA$M_SLOT9_PID_PROD_NUM3 0xF0000000##define EISA$M_SLOT10_PID_CHAR2 0x3$#define EISA$M_SLOT10_PID_CHAR1 0x7C&#define EISA$M_SLOT10_PID_CHAR3 0x1F00+#define EISA$M_SLOT10_PID_CHAR2_CONT 0xE000+#define EISA$M_SLOT10_PID_PROD_NUM1 0xF0000,#define EISA $M_SLOT10_PID_PROD_NUM2 0xF00000,#define EISA$M_SLOT10_PID_REV_NUM1 0xF000000.#define EISA$M_SLOT10_PID_PROD_NUM3 0xF0000000##define EISA$M_SLOT11_PID_CHAR2 0x3$#define EISA$M_SLOT11_PID_CHAR1 0x7C&#define EISA$M_SLOT11_PID_CHAR3 0x1F00+#define EISA$M_SLOT11_PID_CHAR2_CONT 0xE000+#define EISA$M_SLOT11_PID_PROD_NUM1 0xF0000,#define EISA$M_SLOT11_PID_PROD_NUM2 0xF00000,#define EISA$M_SLOT11_PID_REV_NUM1 0xF000000.#define EISA$M_SLOT11_PID_PROD_NUM3 0xF0000000##define EISA$M_SLOT12_PID_CHAR 2 0x3$#define EISA$M_SLOT12_PID_CHAR1 0x7C&#define EISA$M_SLOT12_PID_CHAR3 0x1F00+#define EISA$M_SLOT12_PID_CHAR2_CONT 0xE000+#define EISA$M_SLOT12_PID_PROD_NUM1 0xF0000,#define EISA$M_SLOT12_PID_PROD_NUM2 0xF00000,#define EISA$M_SLOT12_PID_REV_NUM1 0xF000000.#define EISA$M_SLOT12_PID_PROD_NUM3 0xF0000000##define EISA$M_SLOT13_PID_CHAR2 0x3$#define EISA$M_SLOT13_PID_CHAR1 0x7C&#define EISA$M_SLOT13_PID_CHAR3 0x1F00+#define EISA$M_SLOT13_PID_CHAR2_CONT 0xE000+#define EISA$M_SLOT13_PID_ PROD_NUM1 0xF0000,#define EISA$M_SLOT13_PID_PROD_NUM2 0xF00000,#define EISA$M_SLOT13_PID_REV_NUM1 0xF000000.#define EISA$M_SLOT13_PID_PROD_NUM3 0xF0000000##define EISA$M_SLOT14_PID_CHAR2 0x3$#define EISA$M_SLOT14_PID_CHAR1 0x7C&#define EISA$M_SLOT14_PID_CHAR3 0x1F00+#define EISA$M_SLOT14_PID_CHAR2_CONT 0xE000+#define EISA$M_SLOT14_PID_PROD_NUM1 0xF0000,#define EISA$M_SLOT14_PID_PROD_NUM2 0xF00000,#define EISA$M_SLOT14_PID_REV_NUM1 0xF000000.#define EISA$M_SLOT14_PID_PROD_NUM3 0xF0000000 ##define EISA$M_SLOT15_PID_CHAR2 0x3$#define EISA$M_SLOT15_PID_CHAR1 0x7C&#define EISA$M_SLOT15_PID_CHAR3 0x1F00+#define EISA$M_SLOT15_PID_CHAR2_CONT 0xE000+#define EISA$M_SLOT15_PID_PROD_NUM1 0xF0000,#define EISA$M_SLOT15_PID_PROD_NUM2 0xF00000,#define EISA$M_SLOT15_PID_REV_NUM1 0xF000000.#define EISA$M_SLOT15_PID_PROD_NUM3 0xF0000000'#define EISA$K_NODE_SPACE_LENGTH 131072N#define EISA$S_EISABUSDEF 131072 /* Old size name - synonym */ typedef struct _eisabus {  __union {0 unsigned char eisa$b_dma1_ch0_base_addr;, } eisa$r_dma1_ch0_base_addr_overlay; __union {/ unsigned char eisa$b_dma1_ch0_base_cnt;+ } eisa$r_dma1_ch0_base_cnt_overlay; __union {0 unsigned char eisa$b_dma1_ch1_base_addr;, } eisa$r_dma1_ch1_base_addr_overlay; __union {/ unsigned char eisa$b_dma1_ch1_base_cnt;+ } eisa$r_dma1_ch1_base_cnt_overlay; __union {0 unsigned char eisa$b_dma1_ch2_base_addr;, } eisa$r_dma1_ch2_base_addr_overlay; __union {/ unsigned char eisa$b_dma1_ch2_base_cnt;+ } eisa$r_dma1_ch2_base_cnt_overlay; __union {0 unsigned char eisa$b_dma1_ch3_base_addr;, } eisa$r_dma1_ch3_base_addr_overlay; __union {/ unsigned char eisa$b_dma1_ch3_base_cnt;+ } eisa$r_dma1_ch3_base_cnt_overlay; __union {+ unsigned char eisa$b_dma1_stat_cmd;' } eisa$r_dma1_stat_cmd_overlay; __union {( unsigned char eisa$b_dma1_wrreq;$ } eisa$r_dma1_wrreq_overlay; __union {) unsigned char eisa$b_dma1_wrmask;% } eisa$r_dma1_wrmask_overlay; __union {) unsigned char eisa$b_dma1_wrmode;% } eisa$r_dma1_wrmode_overlay; __union {) unsigned char eisa$b_dma1_clrbyt;% } eisa$r_dma1_clrbyt_overlay; __union {- unsigned char eisa$b_dma1_master_clr;) } eisa$r_dma1_master_clr_overlay; __union {+ unsigned char eisa$b_dma1_clr_mask;' } eisa$r_dma1_clr_mask_overlay; __union {+ unsigned char eisa$b_dma1_mask_reg;' } eisa$r_dma1_mask_reg_overlay; char eisa$b_fill4 [16]; __union {( unsigned char eisa$b_pic_l_icw1; __struct {0 unsigned eisa$v_pic_l_icw1_icw4 : 1;0 unsigned eisa$v_pic_l_icw1_sngl : 1;1 unsigned eisa$v_pic_l_icw1_fill1 : 6;% } eisa$r_pic_l_icw1_bits; __st ruct {. unsigned eisa$v_pic_l_ocw2_l0 : 1;. unsigned eisa$v_pic_l_ocw2_l1 : 1;. unsigned eisa$v_pic_l_ocw2_l2 : 1;1 unsigned eisa$v_pic_l_ocw2_fill1 : 2;/ unsigned eisa$v_pic_l_ocw2_eoi : 1;. unsigned eisa$v_pic_l_ocw2_sl : 1;- unsigned eisa$v_pic_l_ocw2_r : 1;% } eisa$r_pic_l_ocw2_bits; __struct {/ unsigned eisa$v_pic_l_ocw3_ris : 1;. unsigned eisa$v_pic_l_ocw3_rr : 1;- unsigned eisa$v_pic_l_ocw3_p : 1;1 unsigned eisa$v_pic_l_ocw3_fill1 : 2;/ unsigned eisa$v_pic_l_ocw3_smm : 1;0 unsigned eisa$v_pic_l_ocw3_esmm : 1;1 unsigned eisa$v_pic_l_ocw3_fill2 : 1;% } eisa$r_pic_l_ocw3_bits;* } eisa$r_pic_l_icw1_ocw23_overlay; __union {( unsigned char eisa$b_pic_l_icw2; __struct {2 unsigned eisa$v_pic_l_icw2_zeroes : 3;/ unsigned eisa$v_pic_ l_icw2_vec : 5;% } eisa$r_pic_l_icw2_bits; __struct {6 unsigned eisa$v_pic_l_icw3_irq0_slave : 1;6 unsigned eisa$v_pic_l_icw3_irq1_slave : 1;6 unsigned eisa$v_pic_l_icw3_irq2_slave : 1;6 unsigned eisa$v_pic_l_icw3_irq3_slave : 1;6 unsigned eisa$v_pic_l_icw3_irq4_slave : 1;6 unsigned eisa$v_pic_l_icw3_irq5_slave : 1;6 unsigned eisa$v_pic_l_icw3_irq6_slave : 1;6 unsigned eisa$v_pic_l_ icw3_irq7_slave : 1;% } eisa$r_pic_l_icw3_bits; __struct {0 unsigned eisa$v_pic_l_icw4_mode : 1;0 unsigned eisa$v_pic_l_icw4_aeoi : 1;1 unsigned eisa$v_pic_l_icw4_fill1 : 1;0 unsigned eisa$v_pic_l_icw4_buff : 2;0 unsigned eisa$v_pic_l_icw4_nest : 1;1 unsigned eisa$v_pic_l_icw4_fill2 : 3;( unsigned eisa$v_fill_0_ : 7;% } eisa$r_pic_l_icw4_bits; __struct {0 un signed eisa$v_pic_l_ocw1_mask : 8;% } eisa$r_pic_l_ocw1_bits;+ } eisa$r_pic_l_icw234_ocw1_overlay; char eisa$b_fill5 [29]; __union {- unsigned char eisa$b_pic_l_t1_systim; __struct {4 unsigned eisa$v_pic_l_t1_systim_bcd : 1;5 unsigned eisa$v_pic_l_t1_systim_mode : 3;3 unsigned eisa$v_pic_l_t1_systim_rw : 2;5 unsigned eisa$v_pic_l_t1_systim_stat : 1;4 unsigned eisa$v_pic_l_t1_systim_out : 1;* } eisa$r_pic_l_t1_systim_bits;) } eisa$r_pic_l_t1_systim_overlay; __union {* unsigned char eisa$b_pic_l_t1_ref; __struct {1 unsigned eisa$v_pic_l_t1_ref_bcd : 1;2 unsigned eisa$v_pic_l_t1_ref_mode : 3;0 unsigned eisa$v_pic_l_t1_ref_rw : 2;2 unsigned eisa$v_pic_l_t1_ref_stat : 1;1 unsigned eisa$v_pic_l_t1_ref_out : 1;' } eisa$r_pic_l_t1_ref_bits;& } eisa$r_pic_l_t1_ref_overlay; __union {+ unsigned char eisa$b_pic_l_t1_spkr; __struct {2 unsigned eisa$v_pic_l_t1_spkr_bcd : 1;3 unsigned eisa$v_pic_l_t1_spkr_mode : 3;1 unsigned eisa$v_pic_l_t1_spkr_rw : 2;3 unsigned eisa$v_pic_l_t1_spkr_stat : 1;2 unsigned eisa$v_pic_l_t1_spkr_out : 1;( } eisa$r_pic_l_t1_spkr_bits;' } eisa$r_pic_l_t1_spkr_overlay; __union {+ unsigned char eisa$b_pic_l_t1_ctrl;  __struct {2 unsigned eisa$v_pic_l_t1_ctrl_bcd : 1;3 unsigned eisa$v_pic_l_t1_ctrl_mode : 3;5 unsigned eisa$v_pic_l_t1_ctrl_cntlat : 2;5 unsigned eisa$v_pic_l_t1_ctrl_cntsel : 2;( } eisa$r_pic_l_t1_ctrl_bits;' } eisa$r_pic_l_t1_ctrl_overlay; char eisa$b_fill6 [4]; __union {+ unsigned char eisa$b_pic_l_t2_flsf; __struct {2 unsigned eisa$v_pic_l_t2_flsf_bcd : 1;3 unsigned  eisa$v_pic_l_t2_flsf_mode : 3;1 unsigned eisa$v_pic_l_t2_flsf_rw : 2;3 unsigned eisa$v_pic_l_t2_flsf_stat : 1;2 unsigned eisa$v_pic_l_t2_flsf_out : 1;( } eisa$r_pic_l_t2_flsf_bits;' } eisa$r_pic_l_t2_flsf_overlay; char eisa$b_fill7 [1]; __union {- unsigned char eisa$b_pic_l_t2_cpuspd; __struct {4 unsigned eisa$v_pic_l_t2_cpuspd_bcd : 1;5 unsigned eisa$v_pic_l_t2_cpuspd_mode : 3;3  unsigned eisa$v_pic_l_t2_cpuspd_rw : 2;5 unsigned eisa$v_pic_l_t2_cpuspd_stat : 1;4 unsigned eisa$v_pic_l_t2_cpuspd_out : 1;* } eisa$r_pic_l_t2_cpuspd_bits;) } eisa$r_pic_l_t2_cpuspd_overlay; __union {+ unsigned char eisa$b_pic_l_t2_ctrl; __struct {2 unsigned eisa$v_pic_l_t2_ctrl_bcd : 1;3 unsigned eisa$v_pic_l_t2_ctrl_mode : 3;5 unsigned eisa$v_pic_l_t2_ctrl_cntlat : 2;5 un signed eisa$v_pic_l_t2_ctrl_cntsel : 2;( } eisa$r_pic_l_t2_ctrl_bits;' } eisa$r_pic_l_t2_ctrl_overlay; char eisa$b_fill8 [21]; __union {* unsigned char eisa$b_pic_l_nmicsr; __struct {0 unsigned eisa$v_pic_l_nmicsr_t1 : 1;2 unsigned eisa$v_pic_l_nmicsr_spkr : 1;0 unsigned eisa$v_pic_l_nmicsr_pe : 1;3 unsigned eisa$v_pic_l_nmicsr_iochk : 1;1 unsigned eisa$v_pic_l_nmicsr_ref : 1;3  unsigned eisa$v_pic_l_nmicsr_intm1 : 1;4 unsigned eisa$v_pic_l_nmicsr_nmiint : 1;1 unsigned eisa$v_pic_l_nmicsr_par : 1;' } eisa$r_pic_l_nmicsr_bits;& } eisa$r_pic_l_nmicsr_overlay; char eisa$b_fill9 [14]; __union {* unsigned char eisa$b_pic_l_nmirtc; __struct {4 unsigned eisa$v_pic_l_nmirtc_clkadr : 7;3 unsigned eisa$v_pic_l_nmirtc_endis : 1;' } eisa$r_pic_l_nmirtc_bits;& } eisa$r_pic_l_nmirtc_overlay; char eisa$b_fill10 [16]; __union {* unsigned char eisa$b_dma_page_ch2;& } eisa$r_dma_page_ch2_overlay; __union {* unsigned char eisa$b_dma_page_ch3;& } eisa$r_dma_page_ch3_overlay; __union {* unsigned char eisa$b_dma_page_ch1;& } eisa$r_dma_page_ch1_overlay; char eisa$b_fill10a [3]; __union {* unsigned char eisa$b_dma_page_ch0;& } eisa$r_dma_page_ch0_overlay; char eisa$b_fill10b [1]; __union {* unsigned char eisa$b_dma_page_ch6;& } eisa$r_dma_page_ch6_overlay; __union {* unsigned char eisa$b_dma_page_ch7;& } eisa$r_dma_page_ch7_overlay; __union {* unsigned char eisa$b_dma_page_ch5;& } eisa$r_dma_page_ch5_overlay; char eisa$b_fill10c [3]; __union {* unsigned char eisa$b_dma_page_ref;& } eisa$r_dma_page_ref_overlay; char eisa$b_fill10d [16]; __union {( unsigned  char eisa$b_pic_h_icw1; __struct {0 unsigned eisa$v_pic_h_icw1_icw4 : 1;0 unsigned eisa$v_pic_h_icw1_sngl : 1;1 unsigned eisa$v_pic_h_icw1_fill1 : 5;( unsigned eisa$v_fill_1_ : 1;% } eisa$r_pic_h_icw1_bits; __struct {. unsigned eisa$v_pic_h_ocw2_l0 : 1;. unsigned eisa$v_pic_h_ocw2_l1 : 1;. unsigned eisa$v_pic_h_ocw2_l2 : 1;1 unsigned eisa$v_pic_h_ocw2_fill1 : 2;/  unsigned eisa$v_pic_h_ocw2_eoi : 1;. unsigned eisa$v_pic_h_ocw2_sl : 1;- unsigned eisa$v_pic_h_ocw2_r : 1;% } eisa$r_pic_h_ocw2_bits; __struct {/ unsigned eisa$v_pic_h_ocw3_ris : 1;. unsigned eisa$v_pic_h_ocw3_rr : 1;- unsigned eisa$v_pic_h_ocw3_p : 1;1 unsigned eisa$v_pic_h_ocw3_fill1 : 2;/ unsigned eisa$v_pic_h_ocw3_smm : 1;0 unsigned eisa$v_pic_h_ocw3_esmm : 1;1  unsigned eisa$v_pic_h_ocw3_fill2 : 1;% } eisa$r_pic_h_ocw3_bits;* } eisa$r_pic_h_icw1_ocw23_overlay; __union {( unsigned char eisa$b_pic_h_icw2; __struct {2 unsigned eisa$v_pic_h_icw2_zeroes : 3;/ unsigned eisa$v_pic_h_icw2_vec : 5;% } eisa$r_pic_h_icw2_bits; __struct {6 unsigned eisa$v_pic_h_icw3_irq0_slave : 1;6 unsigned eisa$v_pic_h_icw3_irq1_slave : 1;6 unsigned  eisa$v_pic_h_icw3_irq2_slave : 1;6 unsigned eisa$v_pic_h_icw3_irq3_slave : 1;6 unsigned eisa$v_pic_h_icw3_irq4_slave : 1;6 unsigned eisa$v_pic_h_icw3_irq5_slave : 1;6 unsigned eisa$v_pic_h_icw3_irq6_slave : 1;6 unsigned eisa$v_pic_h_icw3_irq7_slave : 1;% } eisa$r_pic_h_icw3_bits; __struct {0 unsigned eisa$v_pic_h_icw4_mode : 1;0 unsigned eisa$v_pic_h_icw4_aeoi : 1;1 unsigned eisa$v_ pic_h_icw4_fill1 : 1;0 unsigned eisa$v_pic_h_icw4_buff : 2;0 unsigned eisa$v_pic_h_icw4_nest : 1;1 unsigned eisa$v_pic_h_icw4_fill2 : 2;% } eisa$r_pic_h_icw4_bits; __struct {0 unsigned eisa$v_pic_h_ocw1_mask : 8;% } eisa$r_pic_h_ocw1_bits;+ } eisa$r_pic_h_icw234_ocw1_overlay; char eisa$b_fill10e [30]; __union {0 unsigned char eisa$b_dma2_ch0_base_addr;, } eisa$r_dma2_ch0_base_addr_overlay; char eisa$b_fill010 [1]; __union {/ unsigned char eisa$b_dma2_ch0_base_cnt;+ } eisa$r_dma2_ch0_base_cnt_overlay; char eisa$b_fill010a [1]; __union {0 unsigned char eisa$b_dma2_ch1_base_addr;, } eisa$r_dma2_ch1_base_addr_overlay; char eisa$b_fill010b [1]; __union {/ unsigned char eisa$b_dma2_ch1_base_cnt;+ } eisa$r_dma2_ch1_base_cnt_overlay; char eisa$b_fill110 [1]; __union {0 unsigned char eisa$b_dma2_ch2_base_addr;, } eisa$r_dma2_ch2_base_addr_overlay; char eisa$b_fill210 [1]; __union {/ unsigned char eisa$b_dma2_ch2_base_cnt;+ } eisa$r_dma2_ch2_base_cnt_overlay; char eisa$b_fill210a [1]; __union {0 unsigned char eisa$b_dma2_ch3_base_addr;, } eisa$r_dma2_ch3_base_addr_overlay; char eisa$b_fill310 [1]; __union {/ unsigned char eisa$b_dma2_ch3_base_cnt;+ } eisa$r_dma2_ch3_base_cnt_overlay; char eisa$b_fill310a [1]; __union {* unsigned char eisa$b_dma2_stat_wr;& } eisa$r_dma2_stat_wr_overlay; char eisa$b_fill410 [1]; __union {) unsigned char eisa$b_dma2_wr_req;% } eisa$r_dma2_wr_req_overlay; char eisa$b_fill410a [1]; __union {( unsigned char eisa$b_dma2_smask;' } eisa$r_dma2_wr_smask_overlay; char eisa$b_fill410b [1]; __union {) unsigned char eisa$b_dma2_wrmode;% } eisa$r_dma2_wrmode_overlay; char eisa$b_fill510 [1]; __union {) unsigned char eisa$b_dma2_clrbyt;% } eisa$r_dma2_clrbyt_overlay; char eisa$b_fill610 [1]; __union {- unsigned char eisa$b_dma2_master_clr;) } eisa$r_dma2_master_clr_overlay; char eisa$b_fill710 [1]; __union {+ unsigned char eisa$b_dma2_clr_mask;' } eisa$r_dma2_clr_mask_overlay; char eisa$b_fill810 [1]; __union {+ unsigned char eisa$b_dma2_mask_reg;' } eisa$r_dma2_mask_reg_overlay; char eisa$b_fill910 [802]; __union {* unsigned char eisa$b_dma1_ch0_cnt;& } eisa$r_dma1_ch0_cnt_overlay; char eisa$b_fillabc [1]; __union {* unsigned char eisa$b_dma1_ch1_cnt;& } eisa$r_dma1_ch1_cnt_overlay; char eisa$b_fillabc1 [1]; __union {* unsigned char eisa$b_dma1_ch2_cnt;& } eisa$r_dma1_ch2_cnt_overlay; char eisa$b_fillabc2 [1]; __union {* unsigned char eisa$b_dma1_ch3_cnt;& } eisa$r_dma1_ch3_cnt_overlay; char eisa$b_fillabc21 [2]; __union {+ unsigned char eisa$b_dma1_chn_mode;' } eisa$r_dma1_chn_mode_overlay; __union {+ unsigned char eisa$b_dma1_wrt_mode;' } eisa$r_dma1_wrt_mode_overlay; __union {+ unsigned char eisa$b_dma1_buf_ctrl;' } eisa$r_dma1_buf_ctrl_overlay; __union {* unsigned char eisa$b_dma1_stp_lvl;& } eisa$r_dma1_stp_lvl_ov erlay; char eisa$b_fillabc3 [83]; __union {* unsigned char eisa$b_pic_exnmicsr; __struct {4 unsigned eisa$v_pic_exnmicsr_busrst : 1;2 unsigned eisa$v_pic_exnmicsr_enio : 1;2 unsigned eisa$v_pic_exnmicsr_fsen : 1;2 unsigned eisa$v_pic_exnmicsr_toen : 1;* unsigned eisa$v_pic_fill1 : 1;1 unsigned eisa$v_pic_exnmicsr_iop : 1;0 unsigned eisa$v_pic_exnmicsr_bt : 1;3 unsigned eisa$v_pic_exnmicsr_fsint : 1;' } eisa$r_pic_exnmicsr_bits;& } eisa$r_pic_exnmicsr_overlay; __union {( unsigned char eisa$b_pic_nmigen;$ } eisa$r_pic_nmigen_overlay; char eisa$b_fill11 [1]; __union {- unsigned char eisa$b_pic_eisa_busmas; __struct {4 unsigned eisa$v_pic_eisa_busmas_sl1 : 1;4 unsigned eisa$v_pic_eisa_busmas_sl2 : 1;4 unsigned eisa$v_pic_eisa_busmas_sl3 : 1;4 unsigned eis a$v_pic_eisa_busmas_sl4 : 1;4 unsigned eisa$v_pic_eisa_busmas_sl5 : 1;4 unsigned eisa$v_pic_eisa_busmas_sl6 : 1;4 unsigned eisa$v_pic_eisa_busmas_sl7 : 1;( unsigned eisa$v_fill_2_ : 1;* } eisa$r_pic_eisa_busmas_bits;) } eisa$r_pic_eisa_busmas_overlay; char eisa$b_fill12 [28]; __union {/ unsigned char eisa$b_dma_ch2_page_high;+ } eisa$r_dma_ch2_page_high_overlay; __union {/ unsigned char eisa$b_dma_ch3_page_high;+ } eisa$r_dma_ch3_page_high_overlay; __union {/ unsigned char eisa$b_dma_ch1_page_high;+ } eisa$r_dma_ch1_page_high_overlay; char eisa$b_fill12a [3]; __union {/ unsigned char eisa$b_dma_ch0_page_high;+ } eisa$r_dma_ch0_page_high_overlay; char eisa$b_fill12b [1]; __union {/ unsigned char eisa$b_dma_ch6_page_high;+ } eisa$r_dma_ch6_page_high_overlay; __union {/ unsigned char eisa$b_dma_ch7_page_high;+ } eisa$r_dma_ch7_page_high_overlay; __union {/ unsigned char eisa$b_dma_ch5_page_high;+ } eisa$r_dma_ch5_page_high_overlay; char eisa$b_fill12c [3]; __union {. unsigned char eisa$b_dma_reg_ref_high;* } eisa$r_dma_reg_ref_high_overlay; char eisa$b_fill12d [54]; __union {* unsigned char eisa$b_dma2_ch5_cnt;& } eisa$r_dma2_ch5_cnt_overlay; char eisa$b_fill12e [3]; __union {*  unsigned char eisa$b_dma2_ch6_cnt;& } eisa$r_dma2_ch6_cnt_overlay; char eisa$b_fill12e1 [3]; __union {* unsigned char eisa$b_dma2_ch7_cnt;& } eisa$r_dma2_ch7_cnt_overlay; char eisa$b_fill12f [1]; __union {, unsigned char eisa$b_pic_ctrl1_edge; __struct {5 unsigned eisa$v_pic_ctrl1_edge_fill1 : 3;4 unsigned eisa$v_pic_ctrl1_edge_int3 : 1;4 unsigned eisa$v_pic_ctrl1_edge_int4 : 1;4 unsign ed eisa$v_pic_ctrl1_edge_int5 : 1;4 unsigned eisa$v_pic_ctrl1_edge_int6 : 1;4 unsigned eisa$v_pic_ctrl1_edge_int7 : 1;) } eisa$r_pic_ctrl1_edge_bits;( } eisa$r_pic_ctrl1_edge_overlay; __union {, unsigned char eisa$b_pic_ctrl2_edge; __struct {5 unsigned eisa$v_pic_ctrl2_edge_fill1 : 1;4 unsigned eisa$v_pic_ctrl2_edge_int9 : 1;5 unsigned eisa$v_pic_ctrl2_edge_int10 : 1;5 unsigned eisa$ v_pic_ctrl2_edge_int11 : 1;5 unsigned eisa$v_pic_ctrl2_edge_int12 : 1;5 unsigned eisa$v_pic_ctrl2_edge_fill2 : 1;5 unsigned eisa$v_pic_ctrl2_edge_int14 : 1;5 unsigned eisa$v_pic_ctrl2_edge_int15 : 1;) } eisa$r_pic_ctrl2_edge_bits;( } eisa$r_pic_ctrl2_edge_overlay; char eisa$b_fill13 [2]; __union {+ unsigned char eisa$b_dma2_chn_mode;' } eisa$r_dma2_chn_mode_overlay; char eisa$b_fill13a [1];  __union {+ unsigned char eisa$b_dma2_wrt_mode;' } eisa$r_dma2_wrt_mode_overlay; char eisa$b_fill13b [9]; __union {, unsigned char eisa$b_dma_ch0_srb7_2;( } eisa$r_dma_ch0_srb7_2_overlay; __union {- unsigned char eisa$b_dma_ch0_srb15_8;) } eisa$r_dma_ch0_srb15_8_overlay; __union {. unsigned char eisa$b_dma_ch0_srb23_16;* } eisa$r_dma_ch0_srb23_16_overlay; char eisa$b_fill13c [1]; __union {, unsigned char eisa$b_dma_ch1_srb7_2;( } eisa$r_dma_ch1_srb7_2_overlay; __union {- unsigned char eisa$b_dma_ch1_srb15_8;) } eisa$r_dma_ch1_srb15_8_overlay; __union {. unsigned char eisa$b_dma_ch1_srb23_16;* } eisa$r_dma_ch1_srb23_16_overlay; char eisa$b_fill13d [1]; __union {, unsigned char eisa$b_dma_ch2_srb7_2;( } eisa$r_dma_ch2_srb7_2_overlay; __union {- unsigned char eisa$b_dma_ch2_srb15_8;) } eisa$r_dma_ch2_srb15_8_overlay; __union {. unsigned char eisa$b_dma_ch2_srb23_16;* } eisa$r_dma_ch2_srb23_16_overlay; char eisa$b_fill13e [1]; __union {, unsigned char eisa$b_dma_ch3_srb7_2;( } eisa$r_dma_ch3_srb7_2_overlay; __union {- unsigned char eisa$b_dma_ch3_srb15_8;) } eisa$r_dma_ch3_srb15_8_overlay; __union {. unsigned char eisa$b_dma_ch3_srb23_16;* } eisa$r_dma_ch3_srb23_16_overlay; char eisa$b_fill13f [5]; __union {, unsigned char eisa$b_dma_ch5_srb7_2;( } eisa$r_dma_ch5_srb7_2_overlay; __union {- unsigned char eisa$b_dma_ch5_srb15_8;) } eisa$r_dma_ch5_srb15_8_overlay; __union {. unsigned char eisa$b_dma_ch5_srb23_16;* } eisa$r_dma_ch5_srb23_16_overlay; char eisa$b_fill13f1 [1]; __union {, unsigned char eisa$b_dma_ch6_srb7_2;( } eisa$r_dma_ch6_srb7_2_overlay; __union {- unsigned char eisa$b_dma_ch6_srb15_8;) } eisa$r_dma_ch6_srb15_8_overlay; __union {. unsigned char eisa$b_dma_ch6_srb23_16;* } eisa$r_dma_ch6_srb23_16_overlay; char eisa$b_fill13f2 [1]; __union {, unsigned char eisa$b_dma_ch7_srb7_2;( } eisa$r_dma_ch7_srb7_2_overlay; __union {- unsigned char eisa$b_dma_ch7_srb15_8;) } eisa$r_dma_ch7_srb15_8_overlay; __union {. unsigned char eisa$b_dma_ch7_srb23_16;* } eisa$r_d ma_ch7_srb23_16_overlay; char eisa$b_fill13g [6913];$ unsigned char eisa$b_slot1_base; char eisa$b_fill14 [3199]; __union {& unsigned int eisa$l_slot1_pid; __struct {0 unsigned eisa$v_slot1_pid_char2 : 2;0 unsigned eisa$v_slot1_pid_char1 : 5;0 unsigned eisa$v_slot1_pid_fill1 : 1;0 unsigned eisa$v_slot1_pid_char3 : 5;5 unsigned eisa$v_slot1_pid_char2_cont : 3;4 unsigned eisa$v_slot1_pid_prod_num1 : 4;4 unsigned eisa$v_slot1_pid_prod_num2 : 4;3 unsigned eisa$v_slot1_pid_rev_num1 : 4;4 unsigned eisa$v_slot1_pid_prod_num3 : 4;$ } eisa$r_slot1_pid_bits;# } eisa$r_slot1_pid_overlay; char eisa$b_fill14a [4988];$ unsigned char eisa$b_slot2_base; char eisa$b_fill15 [3199]; __union {& unsigned int eisa$l_slot2_pid; __struct {0 unsigned eisa$v_slot2_pid_char2 : 2;0 unsigned eis a$v_slot2_pid_char1 : 5;0 unsigned eisa$v_slot2_pid_fill1 : 1;0 unsigned eisa$v_slot2_pid_char3 : 5;5 unsigned eisa$v_slot2_pid_char2_cont : 3;4 unsigned eisa$v_slot2_pid_prod_num1 : 4;4 unsigned eisa$v_slot2_pid_prod_num2 : 4;3 unsigned eisa$v_slot2_pid_rev_num1 : 4;4 unsigned eisa$v_slot2_pid_prod_num3 : 4;$ } eisa$r_slot2_pid_bits;# } eisa$r_slot2_pid_overlay; char eisa$b_fill15a [4988]; $ unsigned char eisa$b_slot3_base; char eisa$b_fill16 [3199]; __union {& unsigned int eisa$l_slot3_pid; __struct {0 unsigned eisa$v_slot3_pid_char2 : 2;0 unsigned eisa$v_slot3_pid_char1 : 5;0 unsigned eisa$v_slot3_pid_fill1 : 1;0 unsigned eisa$v_slot3_pid_char3 : 5;5 unsigned eisa$v_slot3_pid_char2_cont : 3;4 unsigned eisa$v_slot3_pid_prod_num1 : 4;4 unsigned eisa$v_slot3_pid_prod_num2 : 4;3 unsigned eisa$v_slot3_pid_rev_num1 : 4;4 unsigned eisa$v_slot3_pid_prod_num3 : 4;$ } eisa$r_slot3_pid_bits;# } eisa$r_slot3_pid_overlay; char eisa$b_fill16a [4988];$ unsigned char eisa$b_slot4_base; char eisa$b_fill17 [3199]; __union {& unsigned int eisa$l_slot4_pid; __struct {0 unsigned eisa$v_slot4_pid_char2 : 2;0 unsigned eisa$v_slot4_pid_char1 : 5;0 unsigned eisa$v_slot 4_pid_fill1 : 1;0 unsigned eisa$v_slot4_pid_char3 : 5;5 unsigned eisa$v_slot4_pid_char2_cont : 3;4 unsigned eisa$v_slot4_pid_prod_num1 : 4;4 unsigned eisa$v_slot4_pid_prod_num2 : 4;3 unsigned eisa$v_slot4_pid_rev_num1 : 4;4 unsigned eisa$v_slot4_pid_prod_num3 : 4;$ } eisa$r_slot4_pid_bits;# } eisa$r_slot4_pid_overlay; char eisa$b_fill17a [4988];$ unsigned char eisa$b_slot5_base; char eisa$b_fi ll18 [3199]; __union {& unsigned int eisa$l_slot5_pid; __struct {0 unsigned eisa$v_slot5_pid_char2 : 2;0 unsigned eisa$v_slot5_pid_char1 : 5;0 unsigned eisa$v_slot5_pid_fill1 : 1;0 unsigned eisa$v_slot5_pid_char3 : 5;5 unsigned eisa$v_slot5_pid_char2_cont : 3;4 unsigned eisa$v_slot5_pid_prod_num1 : 4;4 unsigned eisa$v_slot5_pid_prod_num2 : 4;3 unsigned eisa$v_slot5_pid_rev_num1 : 4;4 unsigned eisa$v_slot5_pid_prod_num3 : 4;$ } eisa$r_slot5_pid_bits;# } eisa$r_slot5_pid_overlay; char eisa$b_fill18a [4988];$ unsigned char eisa$b_slot6_base; char eisa$b_fill19 [3199]; __union {& unsigned int eisa$l_slot6_pid; __struct {0 unsigned eisa$v_slot6_pid_char2 : 2;0 unsigned eisa$v_slot6_pid_char1 : 5;0 unsigned eisa$v_slot6_pid_fill1 : 1;0 unsigned eisa$v_slot6_pid_ch ar3 : 5;5 unsigned eisa$v_slot6_pid_char2_cont : 3;4 unsigned eisa$v_slot6_pid_prod_num1 : 4;4 unsigned eisa$v_slot6_pid_prod_num2 : 4;3 unsigned eisa$v_slot6_pid_rev_num1 : 4;4 unsigned eisa$v_slot6_pid_prod_num3 : 4;$ } eisa$r_slot6_pid_bits;# } eisa$r_slot6_pid_overlay; char eisa$b_fill19a [4988];$ unsigned char eisa$b_slot7_base;! char eisa$b_fill19a01 [3199]; __union {& unsigned int eis a$l_slot7_pid; __struct {0 unsigned eisa$v_slot7_pid_char2 : 2;0 unsigned eisa$v_slot7_pid_char1 : 5;0 unsigned eisa$v_slot7_pid_fill1 : 1;0 unsigned eisa$v_slot7_pid_char3 : 5;5 unsigned eisa$v_slot7_pid_char2_cont : 3;4 unsigned eisa$v_slot7_pid_prod_num1 : 4;4 unsigned eisa$v_slot7_pid_prod_num2 : 4;3 unsigned eisa$v_slot7_pid_rev_num1 : 4;4 unsigned eisa$v_slot7_pid_prod_num3 : 4;$ } eisa$r_slot7_pid_bits;# } eisa$r_slot7_pid_overlay; char eisa$b_fill19a1 [4988];$ unsigned char eisa$b_slot8_base; char eisa$b_fill19b [3199]; __union {& unsigned int eisa$l_slot8_pid; __struct {0 unsigned eisa$v_slot8_pid_char2 : 2;0 unsigned eisa$v_slot8_pid_char1 : 5;0 unsigned eisa$v_slot8_pid_fill1 : 1;0 unsigned eisa$v_slot8_pid_char3 : 5;5 unsigned eisa$v_slot8_pid_char2_cont : 3;4 unsigned eisa$v_slot8_pid_prod_num1 : 4;4 unsigned eisa$v_slot8_pid_prod_num2 : 4;3 unsigned eisa$v_slot8_pid_rev_num1 : 4;4 unsigned eisa$v_slot8_pid_prod_num3 : 4;$ } eisa$r_slot8_pid_bits;# } eisa$r_slot8_pid_overlay; char eisa$b_fill19b1 [4988];$ unsigned char eisa$b_slot9_base; char eisa$b_fill19c [3199]; __union {& unsigned int eisa$l_slot9_pid; __struct {0 unsi gned eisa$v_slot9_pid_char2 : 2;0 unsigned eisa$v_slot9_pid_char1 : 5;0 unsigned eisa$v_slot9_pid_fill1 : 1;0 unsigned eisa$v_slot9_pid_char3 : 5;5 unsigned eisa$v_slot9_pid_char2_cont : 3;4 unsigned eisa$v_slot9_pid_prod_num1 : 4;4 unsigned eisa$v_slot9_pid_prod_num2 : 4;3 unsigned eisa$v_slot9_pid_rev_num1 : 4;4 unsigned eisa$v_slot9_pid_prod_num3 : 4;$ } eisa$r_slot9_pid_bits;# } ei sa$r_slot9_pid_overlay; char eisa$b_fill19c1 [4988];% unsigned char eisa$b_slot10_base; char eisa$b_fill19d [3199]; __union {' unsigned int eisa$l_slot10_pid; __struct {1 unsigned eisa$v_slot10_pid_char2 : 2;1 unsigned eisa$v_slot10_pid_char1 : 5;1 unsigned eisa$v_slot10_pid_fill1 : 1;1 unsigned eisa$v_slot10_pid_char3 : 5;6 unsigned eisa$v_slot10_pid_char2_cont : 3;5 unsigned eisa$v_ slot10_pid_prod_num1 : 4;5 unsigned eisa$v_slot10_pid_prod_num2 : 4;4 unsigned eisa$v_slot10_pid_rev_num1 : 4;5 unsigned eisa$v_slot10_pid_prod_num3 : 4;% } eisa$r_slot10_pid_bits;$ } eisa$r_slot10_pid_overlay; char eisa$b_fill19d1 [4988];% unsigned char eisa$b_slot11_base; char eisa$b_fill19e [3199]; __union {' unsigned int eisa$l_slot11_pid; __struct {1 unsigned eisa$v_slot11_pid_char2 :  2;1 unsigned eisa$v_slot11_pid_char1 : 5;1 unsigned eisa$v_slot11_pid_fill1 : 1;1 unsigned eisa$v_slot11_pid_char3 : 5;6 unsigned eisa$v_slot11_pid_char2_cont : 3;5 unsigned eisa$v_slot11_pid_prod_num1 : 4;5 unsigned eisa$v_slot11_pid_prod_num2 : 4;4 unsigned eisa$v_slot11_pid_rev_num1 : 4;5 unsigned eisa$v_slot11_pid_prod_num3 : 4;% } eisa$r_slot11_pid_bits;$ } eisa$r_slot11_pi d_overlay; char eisa$b_fill19e1 [4988];% unsigned char eisa$b_slot12_base; char eisa$b_fill19f [3199]; __union {' unsigned int eisa$l_slot12_pid; __struct {1 unsigned eisa$v_slot12_pid_char2 : 2;1 unsigned eisa$v_slot12_pid_char1 : 5;1 unsigned eisa$v_slot12_pid_fill1 : 1;1 unsigned eisa$v_slot12_pid_char3 : 5;6 unsigned eisa$v_slot12_pid_char2_cont : 3;5 unsigned eisa$v_slot12_pid_prod_num1 : 4;5 unsigned eisa$v_slot12_pid_prod_num2 : 4;4 unsigned eisa$v_slot12_pid_rev_num1 : 4;5 unsigned eisa$v_slot12_pid_prod_num3 : 4;% } eisa$r_slot12_pid_bits;$ } eisa$r_slot12_pid_overlay; char eisa$b_fill19f1 [4988];% unsigned char eisa$b_slot13_base; char eisa$b_fill19aa [3199]; __union {' unsigned int eisa$l_slot13_pid; __struct {1 unsigned eisa$v_slot13_pid_char2 : 2;1  unsigned eisa$v_slot13_pid_char1 : 5;1 unsigned eisa$v_slot13_pid_fill1 : 1;1 unsigned eisa$v_slot13_pid_char3 : 5;6 unsigned eisa$v_slot13_pid_char2_cont : 3;5 unsigned eisa$v_slot13_pid_prod_num1 : 4;5 unsigned eisa$v_slot13_pid_prod_num2 : 4;4 unsigned eisa$v_slot13_pid_rev_num1 : 4;5 unsigned eisa$v_slot13_pid_prod_num3 : 4;% } eisa$r_slot13_pid_bits;$ } eisa$r_slot13_pid_overlay;!  char eisa$b_fill19aa1 [4988];% unsigned char eisa$b_slot14_base; char eisa$b_fill19ab [3199]; __union {' unsigned int eisa$l_slot14_pid; __struct {1 unsigned eisa$v_slot14_pid_char2 : 2;1 unsigned eisa$v_slot14_pid_char1 : 5;1 unsigned eisa$v_slot14_pid_fill1 : 1;1 unsigned eisa$v_slot14_pid_char3 : 5;6 unsigned eisa$v_slot14_pid_char2_cont : 3;5 unsigned eisa$v_slot14_pid_prod_num1 : 4; 5 unsigned eisa$v_slot14_pid_prod_num2 : 4;4 unsigned eisa$v_slot14_pid_rev_num1 : 4;5 unsigned eisa$v_slot14_pid_prod_num3 : 4;% } eisa$r_slot14_pid_bits;$ } eisa$r_slot14_pid_overlay;! char eisa$b_fill19ab1 [4988];% unsigned char eisa$b_slot15_base; char eisa$b_fill19ac [3199]; __union {' unsigned int eisa$l_slot15_pid; __struct {1 unsigned eisa$v_slot15_pid_char2 : 2;1 unsign ed eisa$v_slot15_pid_char1 : 5;1 unsigned eisa$v_slot15_pid_fill1 : 1;1 unsigned eisa$v_slot15_pid_char3 : 5;6 unsigned eisa$v_slot15_pid_char2_cont : 3;5 unsigned eisa$v_slot15_pid_prod_num1 : 4;5 unsigned eisa$v_slot15_pid_prod_num2 : 4;4 unsigned eisa$v_slot15_pid_rev_num1 : 4;5 unsigned eisa$v_slot15_pid_prod_num3 : 4;% } eisa$r_slot15_pid_bits;$ } eisa$r_slot15_pid_overlay;! char eis a$b_fill19ac1 [4988]; } EISABUS; #if !defined(__VAXC)]#define eisa$b_dma1_ch0_base_addr eisa$r_dma1_ch0_base_addr_overlay.eisa$b_dma1_ch0_base_addrZ#define eisa$b_dma1_ch0_base_cnt eisa$r_dma1_ch0_base_cnt_overlay.eisa$b_dma1_ch0_base_cnt]#define eisa$b_dma1_ch1_base_addr eisa$r_dma1_ch1_base_addr_overlay.eisa$b_dma1_ch1_base_addrZ#define eisa$b_dma1_ch1_base_cnt eisa$r_dma1_ch1_base_cnt_overlay.eisa$b_dma1_ch1_base_cnt]#define eisa$b_dma1_ch2_base_addr eisa$r_dma1_ch2_base_addr_overlay.eisa$b_dma1_ch2_base_addrZ#define eisa$b_dma1_ch2_base_cnt eisa$r_dma1_ch2_base_cnt_overlay.eisa$b_dma1_ch2_base_cnt]#define eisa$b_dma1_ch3_base_addr eisa$r_dma1_ch3_base_addr_overlay.eisa$b_dma1_ch3_base_addrZ#define eisa$b_dma1_ch3_base_cnt eisa$r_dma1_ch3_base_cnt_overlay.eisa$b_dma1_ch3_base_cntN#define eisa$b_dma1_stat_cmd eisa$r_dma1_stat_cmd_overlay.eisa$b_dma1_stat_cmdE#define eisa$b_dma1_wrreq eisa$r_dma1_wrreq_overlay.eisa$b_dma1_wrreqH#define eisa$b_dma1_wrmask eisa$r_dma1_wrmask_overlay.eisa$b_dma1_wrmaskH#define eisa$b_dma1_wrmode eisa$r_dma1_wrmode_overlay.eisa$b_dma1_wrmodeH#define eisa$b_dma1_clrbyt eisa$r_dma1_clrbyt_overlay.eisa$b_dma1_clrbytT#define eisa$b_dma1_master_clr eisa$r_dma1_master_clr_overlay.eisa$b_dma1_master_clrN#define eisa$b_dma1_clr_mask eisa$r_dma1_clr_mask_overlay.eisa$b_dma1_clr_maskN#define eisa$b_dma1_mask_reg eisa$r_dma1_mask_reg_overlay.eisa$b_dma1_mask_regK#define eisa$b_pic_l_icw1 eisa$r_pic_l_icw1_ocw23_overlay.eisa$b_pic_l_icw1l#define eisa$v_pic_l_icw1_icw4 eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_icw1_bits.eisa$v_pic_l_icw1_icw4l#define eisa$v_pic_l_icw1_sngl eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_icw1_bits.eisa$v_pic_l_icw1_snglh#define eisa$v_pic_l_ocw2_l0 eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_l0h#define eisa$v_pic_l_ocw2_l1 eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_l1h#define eisa$v_pic_l_ocw2_l2 eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_l2j#define eisa$v_pic_l_ocw2_eoi eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_eoih#define eisa$v_pic_l_ocw2_sl eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_slf#define eisa$v_pic_l_ocw2_r eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw2_bits.eisa$v_pic_l_ocw2_rj#define eisa$v_pic_l_ocw3_ris eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw3_bits.eisa$v_pic_l_ocw3_rish#define eisa$v_pic_l_ocw3_rr eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw3_bits.eisa$v_pic_l_ocw3_rrf#define eisa$v_pic_l_ocw3_p eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw3_bits.eisa$v_pic_l_ocw3_pj#define eisa$v_pic_l_ocw3_smm eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw3_bits.eisa$v_pic_l_ocw3_smml#define eisa$v_pic_l_ocw3_esmm eisa$r_pic_l_icw1_ocw23_overlay.eisa$r_pic_l_ocw3_bits.eisa$v_pic_l_ocw3_esmmL#define eisa$b_pic_l_icw2 eisa$r_pic_l_icw234_ocw1_overlay.eisa$b_pic_l_icw2q#define eisa$v_pic_l_icw2_zeroes eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw2_bits.eisa$v_pic_l_icw2_zeroesk#define eisa$v_pic_l_icw2_vec eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw2_bits.eisa$v_pic_l_icw2_vecy#define eisa$v_pic_l_icw3_irq0_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq0_slavey#define eisa$v_pic_l_icw3_irq1_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq1_slavey#define eisa$v_pic_l_icw3_irq2_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq2_slavey#define eisa$v_pic_l_icw3_irq3_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq3_slavey#define eisa$v_pic_l_icw3_irq4_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq4_slavey#define eisa$v_pic_l_icw3_irq5_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq5_slavey#define eisa$v_pic_l_icw3_irq6_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq6_slavey#define eisa$v_pic_l_icw3_irq7_slave eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw3_bits.eisa$v_pic_l_icw3_irq7_slavem#define eisa$v_pic_l_icw4_mode eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw4_bits.eisa$v_pic_l_icw4_modem#define eisa$v_pic_l_icw4_aeoi eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw4_bits.eisa$v_pic_l_icw4_aeoim#define eisa$v_pic_l_icw4_buff eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw4_bits.eisa$v_pic_l_icw4_buffm#define eisa$v_pic_l_icw4_nest eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_icw4_bits.eisa$v_pic_l_icw4_nestm#define eisa$v_pic_l_ocw1_mask eisa$r_pic_l_icw234_ocw1_overlay.eisa$r_pic_l_ocw1_bits.eisa$v_pic_l_ocw1_maskT#define eisa$b_pic_l_t1_systim eisa$r_pic_l_t1_systim_overlay.eisa$b_pic_l_t1_systimx#define eisa$v_pic_l_t1_systim_bcd eisa$r_pic_l_t1_systim_overlay.eisa$r_pic_l_t1_systim_bits.eisa$v_pic_l_t1_systim_bcdz#define eisa$v_pic_l_t1_systim_mode eisa$r_pic_l_t1_systim_overlay.eisa$r_pic_l_t1_systim_bits.eisa$v_pic_l_t1_systim_modev#define eisa$v_pic_l_t1_systim_rw eisa$r_pic_l_t1_systim_overlay.eisa$r_pic_l_t1_systim_bits.eisa$v_pic_l_t1_systim_rwz#define eisa$v_pic_l_t1_systim_stat eisa$r_pic_l_t1_systim_overlay.eisa$r_pic_l_t1_systim_bits.eisa$v_pic_l_t1_systim_statx#define eisa$v_pic_l_t1_systim_out eisa$r_pic_l_t1_systim_overlay.eisa$r_pic_l_t1_systim_bits.eisa$v_pic_l_t1_systim_outK#define eisa$b_pic_l_t1_ref eisa$r_pic_l_t1_ref_overlay.eisa$b_pic_l_t1_refl#define eisa$v_pic_l_t1_ref_bcd eisa$r_pic_l_t1_ref_overlay.eisa$r_pic_l_t1_ref_bits.eisa$v_pic_l_t1_ref_bcdn#define eisa$v_pic_l_t1_ref_mode eisa$r_pic_l_t1_ref_overlay.eisa$r_pic_l_t1_ref_bits.eisa$v_pic_l_t1_ref_modej#define eisa$v_pic_l_t1_ref_rw eisa$r_pic_l_t1_ref_overlay.eisa$r_pic_l_t1_ref_bits.eisa$v_pic_l_t1_ref_rwn#define eisa$v_pic_l_t1_ref_stat eisa$r_pic_l_t1_ref_overlay.eisa$r_pic_l_t1_ref_bits.eisa$v_pic_l_t1_ref_statl#define eisa$v_pic_l_t1_ref_out eisa$r_pic_l_t1_ref_overlay.eisa$r_pic_l_t1_ref_bits.eisa$v_pic_l_t1_ref_outN#define eisa$b_pic_l_t1_spkr eisa$r_pic_l_t1_spkr_overlay.eisa$b_pic_l_t1_spkrp#define eisa$v_pic_l_t1_spkr_bcd eisa$r_pic_l_t1_spkr_overlay.eisa$r_pic_l_t1_spkr_bits.eisa$v_pic_l_t1_spkr_bcdr#define eisa$v_pic_l_t1_spkr_mode eisa$r_pic_l_t1_spkr_overlay.eisa$r_pic_l_t1_spkr_bits.eisa$v_pic_l_t1_spkr_moden#define eisa$v_pic_l_t1_spkr_rw eisa$r_pic_l_t1_spkr_overlay.eisa$r_pic_l_t1_spkr_bits.eisa$v_pic_l_t1_spkr_rwr#define eisa$v_pic_l_t1_spkr_stat eisa$r_pic_l_t1_spkr_overlay.eisa$r_pic_l_t1_spkr_bits.eisa$v_pic_l_t1_spkr_statp#define eisa$v_pic_l_t1_spkr_out eisa$r_pic_l_t1_spkr_overlay.eisa$r_pic_l_t1_spkr_bits.eisa$v_pic_l_t1_spkr_outN#define eisa$b_pic_l_t1_ctrl eisa$r_pic_l_t1_ctrl_overlay.eisa$b_pic_l_t1_ctrlp#define eisa$v_pic_l_t1_ctrl_bcd eisa$r_pic_l_t1_ctrl_overlay.eisa$r_pic_l_t1_ctrl_bits.eisa$v_pic_l_t1_ctrl_bcdr#define eisa$v_pic_l_t1_ctrl_mode eisa$r_pic_l_t1_ctrl_overlay.eisa$r_pic_l_t1_ctrl_bits.eisa$v_pic_l_t1_ctrl_modev#define eisa$v_pic_l_t1_ctrl_cntlat eisa$r_pic_l_t1_ctrl_overlay.eisa$r_pic_l_t1_ctrl_bits.eisa$v_pic_l_t1_ctrl_cntlatv#define eisa$v_pic_l_t1_ctrl_cntsel eisa$r_pic_l_t1_ctrl_overlay.eisa$r_pic_l_t1_ctrl_bits.eisa$v_pic_l_t1_ctrl_cntselN#define eisa$b_pic_l_t2_flsf eisa$r_pic_l_t2_flsf_overlay.eisa$b_pic_l_t2_flsfp#define eisa$v_pic_l_t2_flsf_bcd eisa$r_pic_l_t2_flsf_overlay.eisa$r_pic_l_t2_flsf_bits.eisa$v_pic_l_t2_flsf_bcdr#define eisa$v_pic_l_t2_flsf_mode eisa$r_pic_l_t2_flsf_overlay.eisa$r_pic_l_t2_flsf_bits.eisa$v_pic_l_t2_flsf_moden#define eisa$v_pic_l_t2_flsf_rw eisa$r_pic_l_t2_flsf_overlay.eisa$r_pic_l_t2_flsf_bits.eisa$v_pic_l_t2_flsf_rwr#define eisa$v_pic_l_t2_flsf_stat eisa$r_pic_l_t2_flsf_overlay.eisa$r_pic_l_t2_flsf_bits.eisa$v_pic_l_t2_flsf_statp#define eisa$v_pic_l_t2_flsf_out eisa$r_pic_l_t2_flsf_overlay.eisa$r_pic_l_t2_flsf_bits.eisa$v_pic_l_t2_flsf_outT#define eisa$b_pic_l_t2_cpuspd eisa$r_pic_l_t2_cpuspd_overlay.eisa$b_pic_l_t2_cpuspdx#define eisa$v_pic_l_t2_cpuspd_bcd eisa$r_pic_l_t2_cpuspd_overlay.eisa$r_pic_l_t2_cpuspd_bits.eisa$v_pic_l_t2_cpuspd_bcdz#define eisa$v_pic_l_t2_cpuspd_mode eisa$r_pic_l_t2_cpuspd_overlay.eisa$r_pic_l_t2_cpuspd_bits.eisa$v_pic_l_t2_cpuspd_modev#define eisa$v_pic_l_t2_cpuspd_rw eisa$r_pic_l_t2_cpuspd_overlay.eisa$r_pic_l_t2_cpuspd_bits.eisa$v_pic_l_t2_cpuspd_rwz#define eisa$v_pic_l_t2_cpuspd_stat eisa$r_pic_l_t2_cpuspd_overlay.eisa$r_pic_l_t2_cpuspd_bits.eisa$v_pic_l_t2_cpuspd_statx#define eisa$v_pic_l_t2_cpuspd_out eisa$r_pic_l_t2_cpuspd_overlay.eisa$r_pic_l_t2_cpuspd_bits.eisa$v_pic_l_t2_cpuspd_outN#define eisa$b_pic_l_t2_ctrl eisa$r_pic_l_t2_ctrl_overlay.eisa$b_pic_l_t2_ctrlp#define eisa$v_pic_l_t2_ctrl_bcd eisa$r_pic_l_t2_ctrl_overlay.eisa$r_pic_l_t2_ctrl_bits.eisa$v_pic_l_t2_ctrl_bcdr#define eisa$v_pic_l_t2_ctrl_mode eisa$r_pic_l_t2_ctrl_overlay.eisa$r_pic_l_t2_ctrl_bits.eisa$v_pic_l_t2_ctrl_modev#define eisa$v_pic_l_t2_ctrl_cntlat eisa$r_pic_l_t2_ctrl_overlay.eisa$r_pic_l_t2_ctrl_bits.eisa$v_pic_l_t2_ctrl_cntlatv#define eisa$v_pic_l_t2_ctrl_cntsel eisa$r_pic_l_t2_ctrl_overlay.eisa$r_pic_l_t2_ctrl_bits.eisa$v_pic_l_t2_ctrl_cntselK#define eisa$b_pic_l_nmicsr eisa$r_pic_l_nmicsr_overlay.eisa$b_pic_l_nmicsrj#define eisa$v_pic_l_nmicsr_t1 eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_t1n#define eisa$v_pic_l_nmicsr_spkr eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_spkrj#define eisa$v_pic_l_nmicsr_pe eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_pep#define eisa$v_pic_l_nmicsr_iochk eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_iochkl#define eisa$v_pic_l_nmicsr_ref eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_refp#define eisa$v_pic_l_nmicsr_intm1 eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_intm1r#define eisa$v_pic_l_nmicsr_nmiint eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_nmiintl#define eisa$v_pic_l_nmicsr_par eisa$r_pic_l_nmicsr_overlay.eisa$r_pic_l_nmicsr_bits.eisa$v_pic_l_nmicsr_parK#define eisa$b_pic_l_nmirtc eisa$r_pic_l_nmirtc_overlay.eisa$b_pic_l_nmirtcr#define eisa$v_pic_l_nmirtc_clkadr eisa$r_pic_l_nmirtc_overlay.eisa$r_pic_l_nmirtc_bits.eisa$v_pic_l_nmirtc_clkadrp#define eisa$v_pic_l_nmirtc_endis eisa$r_pic_l_nmirtc_overlay.eisa$r_pic_l_nmirtc_bits.eisa$v_pic_l_nmirtc_endisK#define eisa$b_dma_page_ch2 eisa$r_dma_page_ch2_overlay.eisa$b_dma_page_ch2K#define eisa$b_dma_page_ch3 eisa$r_dma_page_ch3_overlay.eisa$b_dma_page_ch3K#define eisa$b_dma_page_ch1 eisa$r_dma_page_ch1_overlay.eisa$b_dma_page_ch1K#define eisa$b_dma_page_ch0 eisa$r_dma_page_ch0_overlay.eisa$b_dma_page_ch0K#define eisa$b_dma_page_ch6 eisa$r_dma_page_ch6_overlay.eisa$b_dma_page_ch6K#define eisa$b_dma_page_ch7 eisa$r_dma_page_ch7_overlay.eisa$b_dma_page_ch7K#define eisa$b_dma_page_ch5 eisa$r_dma_page_ch5_overlay.eisa$b_dma_page_ch5K#define eisa$b_dma_page_ref eisa$r_dma_page_ref_overlay.eisa$b_dma_page_refK#define eisa$b_pic_h_icw1 eisa$r_pic_h_icw1_ocw23_overlay.eisa$b_pic_h_icw1l#define eisa$v_pic_h_icw1_icw4 eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_icw1_bits.eisa$v_pic_h_icw1_icw4l#define eisa$v_pic_h_icw1_sngl eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_icw1_bits.eisa$v_pic_h_icw1_snglh#define eisa$v_pic_h_ocw2_l0 eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_l0h#define eisa$v_pic_h_ocw2_l1 eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_l1h#define eisa$v_pic_h_ocw2_l2 eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_l2j#define eisa$v_pic_h_ocw2_eoi eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_eoih#define eisa$v_pic_h_ocw2_sl eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_slf#define eisa$v_pic_h_ocw2_r eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw2_bits.eisa$v_pic_h_ocw2_rj#define eisa$v_pic_h_ocw3_ris eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw3_bits.eisa$v_pic_h_ocw3_rish#define eisa$v_pic_h_ocw3_rr eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw3_bits.eisa$v_pic_h_ocw3_rrf#define eisa$v_pic_h_ocw3_p eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw3_bits.eisa$v_pic_h_ocw3_pj#define eisa$v_pic_h_ocw3_smm eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw3_bits.eisa$v_pic_h_ocw3_smml#define eisa$v_pic_h_ocw3_esmm eisa$r_pic_h_icw1_ocw23_overlay.eisa$r_pic_h_ocw3_bits.eisa$v_pic_h_ocw3_esmmL#define eisa$b_pic_h_icw2 eisa$r_pic_h_icw234_ocw1_overlay.eisa$b_pic_h_icw2q#define eisa$v_pic_h_icw2_zeroes eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw2_bits.eisa$v_pic_h_icw2_zeroesk#define eisa$v_pic_h_icw2_vec eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw2_bits.eisa$v_pic_h_icw2_vecy#define eisa$v_pic_h_icw3_irq0_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq0_slavey#define eisa$v_pic_h_icw3_irq1_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq1_slavey#define eisa$v_pic_h_icw3_irq2_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq2_slavey#define eisa$v_pic_h_icw3_irq3_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq3_slavey#define eisa$v_pic_h_icw3_irq4_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq4_slavey#define eisa$v_pic_h_icw3_irq5_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq5_slavey#define eisa$v_pic_h_icw3_irq6_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq6_slavey#define eisa$v_pic_h_icw3_irq7_slave eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw3_bits.eisa$v_pic_h_icw3_irq7_slavem#define eisa$v_pic_h_icw4_mode eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw4_bits.eisa$v_pic_h_icw4_modem#define eisa$v_pic_h_icw4_aeoi eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw4_bits.eisa$v_pic_h_icw4_aeoim#define eisa$v_pic_h_icw4_buff eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw4_bits.eisa$v_pic_h_icw4_buffm#define eisa$v_pic_h_icw4_nest eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_icw4_bits.eisa$v_pic_h_icw4_nestm#define eisa$v_pic_h_ocw1_mask eisa$r_pic_h_icw234_ocw1_overlay.eisa$r_pic_h_ocw1_bits.eisa$v_pic_h_ocw1_mask]#define eisa$b_dma2_ch0_base_addr eisa$r_dma2_ch0_base_addr_overlay.eisa$b_dma2_ch0_base_addrZ#define eisa$b_dma2_ch0_base_cnt eisa$r_dma2_ch0_base_cnt_overlay.eisa$b_dma2_ch0_base_cnt]#define eisa$b_dma2_ch1_base_addr eisa$r_dma2_ch1_base_addr_overlay.eisa$b_dma2_ch1_base_addrZ#define eisa$b_dma2_ch1_base_cnt eisa$r_dma2_ch1_base_cnt_overlay.eisa$b_dma2_ch1_base_cnt]#define eisa$b_dma2_ch2_base_addr eisa$r_dma2_ch2_base_addr_overlay.eisa$b_dma2_ch2_base_addrZ#define eisa$b_dma2_ch2_base_cnt eisa$r_dma2_ch2_base_cnt_overlay.eisa$b_dma2_ch2_base_cnt]#define eisa$b_dma2_ch3_base_addr eisa$r_dma2_ch3_base_addr_overlay.eisa$b_dma2_ch3_base_addrZ#define eisa$b_dma2_ch3_base_cnt eisa$r_dma2_ch3_base_cnt_overlay.eisa$b_dma2_ch3_base_cntK#define eisa$b_dma2_stat_wr eisa$r_dma2_stat_wr_overlay.eisa$b_dma2_stat_wrH#define eisa$b_dma2_wr_req eisa$r_dma2_wr_req_overlay.eisa$b_dma2_wr_reqH#define eisa$b_dma2_smask eisa$r_dma2_wr_smask_overlay.eisa$b_dma2_smaskH#define eisa$b_dma2_wrmode eisa$r_dma2_wrmode_overlay.eisa$b_dma2_wrmodeH#define eisa$b_dma2_clrbyt eisa$r_dma2_clrbyt_overlay.eisa$b_dma2_clrbytT#define eisa$b_dma2_master_clr eisa$r_dma2_master_clr_overlay.eisa$b_dma2_master_clrN#define eisa$b_dma2_clr_mask eisa$r_dma2_clr_mask_overlay.eisa$b_dma2_clr_maskN#define eisa$b_dma2_mask_reg eisa$r_dma2_mask_reg_overlay.eisa$b_dma2_mask_regK#define eisa$b_dma1_ch0_cnt eisa$r_dma1_ch0_cnt_overlay.eisa$b_dma1_ch0_cntK#define eisa$b_dma1_ch1_cnt eisa$r_dma1_ch1_cnt_overlay.eisa$b_dma1_ch1_cntK#define eisa$b_dma1_ch2_cnt eisa$r_dma1_ch2_cnt_overlay.eisa$b_dma1_ch2_cntK#define eisa$b_dma1_ch3_cnt eisa$r_dma1_ch3_cnt_overlay.eisa$b_dma1_ch3_cntN#define eisa$b_dma1_chn_mode eisa$r_dma1_chn_mode_overlay.eisa$b_dma1_chn_modeN#define eisa$b_dma1_wrt_mode eisa$r_dma1_wrt_mode_overlay.eisa$b_dma1_wrt_modeN#define eisa$b_dma1_buf_ctrl eisa$r_dma1_buf_ctrl_overlay.eisa$b_dma1_buf_ctrlK#define eisa$b_dma1_stp_lvl eisa$r_dma1_stp_lvl_overlay.eisa$b_dma1_stp_lvlK#define eisa$b_pic_exnmicsr eisa$r_pic_exnmicsr_overlay.eisa$b_pic_exnmicsrr#define eisa$v_pic_exnmicsr_busrst eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_busrstn#define eisa$v_pic_exnmicsr_enio eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_enion#define eisa$v_pic_exnmicsr_fsen eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_fsenn#define eisa$v_pic_exnmicsr_toen eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_toenl#define eisa$v_pic_exnmicsr_iop eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_iopj#define eisa$v_pic_exnmicsr_bt eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_btp#define eisa$v_pic_exnmicsr_fsint eisa$r_pic_exnmicsr_overlay.eisa$r_pic_exnmicsr_bits.eisa$v_pic_exnmicsr_fsintE#define eisa$b_pic_nmigen eisa$r_pic_nmigen_overlay.eisa$b_pic_nmigenT#define eisa$b_pic_eisa_busmas eisa$r_pic_eisa_busmas_overlay.eisa$b_pic_eisa_busmasx#define eisa$v_pic_eisa_busmas_sl1 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl1x#define eisa$v_pic_eisa_busmas_sl2 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl2x#define eisa$v_pic_eisa_busmas_sl3 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl3x#define eisa$v_pic_eisa_busmas_sl4 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl4x#define eisa$v_pic_eisa_busmas_sl5 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl5x#define eisa$v_pic_eisa_busmas_sl6 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl6x#define eisa$v_pic_eisa_busmas_sl7 eisa$r_pic_eisa_busmas_overlay.eisa$r_pic_eisa_busmas_bits.eisa$v_pic_eisa_busmas_sl7Z#define eisa$b_dma_ch2_page_high eisa$r_dma_ch2_page_high_overlay.eisa$b_dma_ch2_page_highZ#define eisa$b_dma_ch3_page_high eisa$r_dma_ch3_page_high_overlay.eisa$b_dma_ch3_page_highZ#define eisa$b_dma_ch1_page_high eisa$r_dma_ch1_page_high_overlay.eisa$b_dma_ch1_page_highZ#define eisa$b_dma_ch0_page_high eisa$r_dma_ch0_page_high_overlay.eisa$b_dma_ch0_page_highZ#define eisa$b_dma_ch6_page_high eisa$r_dma_ch6_page_high_overlay.eisa$b_dma_ch6_page_highZ#define eisa$b_dma_ch7_page_high eisa$r_dma_ch7_page_high_overlay.eisa$b_dma_ch7_page_highZ#define eisa$b_dma_ch5_page_high eisa$r_dma_ch5_page_high_overlay.eisa$b_dma_ch5_page_highW#define eisa$b_dma_reg_ref_high eisa$r_dma_reg_ref_high_overlay.eisa$b_dma_reg_ref_highK#define eisa$b_dma2_ch5_cnt eisa$r_dma2_ch5_cnt_overlay.eisa$b_dma2_ch5_cntK#define eisa$b_dma2_ch6_cnt eisa$r_dma2_ch6_cnt_overlay.eisa$b_dma2_ch6_cntK#define eisa$b_dma2_ch7_cnt eisa$r_dma2_ch7_cnt_overlay.eisa$b_dma2_ch7_cntQ#define eisa$b_pic_ctrl1_edge eisa$r_pic_ctrl1_edge_overlay.eisa$b_pic_ctrl1_edgev#define eisa$v_pic_ctrl1_edge_int3 eisa$r_pic_ctrl1_edge_overlay.eisa$r_pic_ctrl1_edge_bits.eisa$v_pic_ctrl1_edge_int3v#define eisa$v_pic_ctrl1_edge_int4 eisa$r_pic_ctrl1_edge_overlay.eisa$r_pic_ctrl1_edge_bits.eisa$v_pic_ctrl1_edge_int4v#define eisa$v_pic_ctrl1_edge_int5 eisa$r_pic_ctrl1_edge_overlay.eisa$r_pic_ctrl1_edge_bits.eisa$v_pic_ctrl1_edge_int5v#define eisa$v_pic_ctrl1_edge_int6 eisa$r_pic_ctrl1_edge_overlay.eisa$r_pic_ctrl1_edge_bits.eisa$v_pic_ctrl1_edge_int6v#define eisa$v_pic_ctrl1_edge_int7 eisa$r_pic_ctrl1_edge_overlay.eisa$r_pic_ctrl1_edge_bits.eisa$v_pic_ctrl1_edge_int7Q#define eisa$b_pic_ctrl2_edge eisa$r_pic_ctrl2_edge_overlay.eisa$b_pic_ctrl2_edgev#define eisa$v_pic_ctrl2_edge_int9 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int9x#define eisa$v_pic_ctrl2_edge_int10 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int10x#define eisa$v_pic_ctrl2_edge_int11 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int11x#define eisa$v_pic_ctrl2_edge_int12 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int12x#define eisa$v_pic_ctrl2_edge_int14 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int14x#define eisa$v_pic_ctrl2_edge_int15 eisa$r_pic_ctrl2_edge_overlay.eisa$r_pic_ctrl2_edge_bits.eisa$v_pic_ctrl2_edge_int15N#define eisa$b_dma2_chn_mode eisa$r_dma2_chn_mode_overlay.eisa$b_dma2_chn_modeN#define eisa$b_dma2_wrt_mode eisa$r_dma2_wrt_mode_overlay.eisa$b_dma2_wrt_modeQ#define eisa$b_dma_ch0_srb7_2 eisa$r_dma_ch0_srb7_2_overlay.eisa$b_dma_ch0_srb7_2T#define eisa$b_dma_ch0_srb15_8 eisa$r_dma_ch0_srb15_8_overlay.eisa$b_dma_ch0_srb15_8W#define eisa$b_dma_ch0_srb23_16 eisa$r_dma_ch0_srb23_16_overlay.eisa$b_dma_ch0_srb23_16Q#define eisa$b_dma_ch1_srb7_2 eisa$r_dma_ch1_srb7_2_overlay.eisa$b_d ma_ch1_srb7_2T#define eisa$b_dma_ch1_srb15_8 eisa$r_dma_ch1_srb15_8_overlay.eisa$b_dma_ch1_srb15_8W#define eisa$b_dma_ch1_srb23_16 eisa$r_dma_ch1_srb23_16_overlay.eisa$b_dma_ch1_srb23_16Q#define eisa$b_dma_ch2_srb7_2 eisa$r_dma_ch2_srb7_2_overlay.eisa$b_dma_ch2_srb7_2T#define eisa$b_dma_ch2_srb15_8 eisa$r_dma_ch2_srb15_8_overlay.eisa$b_dma_ch2_srb15_8W#define eisa$b_dma_ch2_srb23_16 eisa$r_dma_ch2_srb23_16_overlay.eisa$b_dma_ch2_srb23_16Q#define eisa$b_dma_ch3_srb7_2 eisa$r_dma_ch3_srb7_2_ov erlay.eisa$b_dma_ch3_srb7_2T#define eisa$b_dma_ch3_srb15_8 eisa$r_dma_ch3_srb15_8_overlay.eisa$b_dma_ch3_srb15_8W#define eisa$b_dma_ch3_srb23_16 eisa$r_dma_ch3_srb23_16_overlay.eisa$b_dma_ch3_srb23_16Q#define eisa$b_dma_ch5_srb7_2 eisa$r_dma_ch5_srb7_2_overlay.eisa$b_dma_ch5_srb7_2T#define eisa$b_dma_ch5_srb15_8 eisa$r_dma_ch5_srb15_8_overlay.eisa$b_dma_ch5_srb15_8W#define eisa$b_dma_ch5_srb23_16 eisa$r_dma_ch5_srb23_16_overlay.eisa$b_dma_ch5_srb23_16Q#define eisa$b_dma_ch6_srb7_2 eisa$r_dma _ch6_srb7_2_overlay.eisa$b_dma_ch6_srb7_2T#define eisa$b_dma_ch6_srb15_8 eisa$r_dma_ch6_srb15_8_overlay.eisa$b_dma_ch6_srb15_8W#define eisa$b_dma_ch6_srb23_16 eisa$r_dma_ch6_srb23_16_overlay.eisa$b_dma_ch6_srb23_16Q#define eisa$b_dma_ch7_srb7_2 eisa$r_dma_ch7_srb7_2_overlay.eisa$b_dma_ch7_srb7_2T#define eisa$b_dma_ch7_srb15_8 eisa$r_dma_ch7_srb15_8_overlay.eisa$b_dma_ch7_srb15_8W#define eisa$b_dma_ch7_srb23_16 eisa$r_dma_ch7_srb23_16_overlay.eisa$b_dma_ch7_srb23_16B#define eisa$l_slot1_pid e isa$r_slot1_pid_overlay.eisa$l_slot1_pidd#define eisa$v_slot1_pid_char2 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_char2d#define eisa$v_slot1_pid_char1 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_char1d#define eisa$v_slot1_pid_char3 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_char3n#define eisa$v_slot1_pid_char2_cont eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_char2_contl#define eisa$v_slot1_pid_prod_num1 eisa$r_slot 1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_prod_num1l#define eisa$v_slot1_pid_prod_num2 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_prod_num2j#define eisa$v_slot1_pid_rev_num1 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_rev_num1l#define eisa$v_slot1_pid_prod_num3 eisa$r_slot1_pid_overlay.eisa$r_slot1_pid_bits.eisa$v_slot1_pid_prod_num3B#define eisa$l_slot2_pid eisa$r_slot2_pid_overlay.eisa$l_slot2_pidd#define eisa$v_slot2_pid_char2 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_char2d#define eisa$v_slot2_pid_char1 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_char1d#define eisa$v_slot2_pid_char3 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_char3n#define eisa$v_slot2_pid_char2_cont eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_char2_contl#define eisa$v_slot2_pid_prod_num1 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_prod_num1l#define eisa$v_slot2_pid_prod_num2 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_prod_num2j#define eisa$v_slot2_pid_rev_num1 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_rev_num1l#define eisa$v_slot2_pid_prod_num3 eisa$r_slot2_pid_overlay.eisa$r_slot2_pid_bits.eisa$v_slot2_pid_prod_num3B#define eisa$l_slot3_pid eisa$r_slot3_pid_overlay.eisa$l_slot3_pidd#define eisa$v_slot3_pid_char2 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_char2d#define eisa$v_slot3_pid_char1 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_char1d#define eisa$v_slot3_pid_char3 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_char3n#define eisa$v_slot3_pid_char2_cont eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_char2_contl#define eisa$v_slot3_pid_prod_num1 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_prod_num1l#define eisa$v_slot3_pid_prod_num2 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_prod_num2j#define eisa$v_slot3_pid_rev_num1 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_rev_num1l#define eisa$v_slot3_pid_prod_num3 eisa$r_slot3_pid_overlay.eisa$r_slot3_pid_bits.eisa$v_slot3_pid_prod_num3B#define eisa$l_slot4_pid eisa$r_slot4_pid_overlay.eisa$l_slot4_pidd#define eisa$v_slot4_pid_char2 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_char2d#define eisa$v_slot4_pid_char1 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_char1d#define eisa$v_slot4_pid_char3 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_char3n#define eisa$v_slot4_pid_char2_cont eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_char2_contl#define eisa$v_slot4_pid_prod_num1 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_prod_num1l#define eisa$v_slot4_pid_prod_num2 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_prod_num2j#define eisa$v_slot4_pid_rev_num1 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_rev_num1l#define eisa$v_slot4_pid_prod_num3 eisa$r_slot4_pid_overlay.eisa$r_slot4_pid_bits.eisa$v_slot4_pid_prod_num3B#define eisa$l_slot5_pid eisa$r_slot5_pid_overlay.eisa$l_slot5_pidd#define eisa$v_slot5_pid_char2 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_char2d#define eisa$v_slot5_pid_char1 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_char1d#define eisa$v_slot5_pid_char3 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_char3n#define eisa$v_slot5_pid_char2_cont eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_char2_contl#define eisa$v_slot5_pid_prod_num1 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_prod_num1l#define eisa$v_slot5_pid_prod_num2 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_prod_num2j#define eisa$v_slot5_pid_rev_num1 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_rev_num1l#define eisa$v_slot5_pid_prod_num3 eisa$r_slot5_pid_overlay.eisa$r_slot5_pid_bits.eisa$v_slot5_pid_prod_num3B#define eisa$l_slot6_pid eisa$r_slot6_pid_overlay.eisa$l_slot6_pidd#define eisa$v_slot6_pid_char2 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_char2d#define eisa$v_slot6_pid_char1 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_char1d#define eisa$v_slot6_pid_char3 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_char3n#define eisa$v_slot6_pid_char2_cont eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_char2_contl#define eisa$v_slot6_pid_prod_num1 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_prod_num1l#define eisa$v_slot6_pid_prod_num2 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_prod_num2j#define eisa$v_slot6_pid_rev_num1 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_rev_num1l#define eisa$v_slot6_pid_prod_num3 eisa$r_slot6_pid_overlay.eisa$r_slot6_pid_bits.eisa$v_slot6_pid_prod_num3B#define eisa$l_slot7_pid eisa$r_slot7_pid_overlay.eisa$l_slot7_pidd#define eisa$v_slot7_pid_char2 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_char2d#define eisa$v_slot7_pid_char1 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_char1d#define eisa$v_slot7_pid_char3 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_char3n#define eisa$v_slot7_pid_char2_cont eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_char2_contl#define eisa$v_slot7_pid_prod_num1 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_prod_num1l#define eisa$v_slot7_pid_prod_num2 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_prod_num2j#define eisa$v_slot7_pid_rev_num1 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_rev_num1l#define eisa$v_slot7_pid_prod_num3 eisa$r_slot7_pid_overlay.eisa$r_slot7_pid_bits.eisa$v_slot7_pid_prod_num3B#define eisa$l_slot8_pid eisa$r_slot8_pid_overlay.eisa$l_slot8_pidd#define eisa$v_slot8_pid_char2 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_char2d#define eisa$v_slot8_pid_char1 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_char1d#define eisa$v_slot8_pid_char3 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_char3n#define eisa$v_slot8_pid_char2_cont eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_char2_contl#define eisa$v_slot8_pid_prod_num1 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_prod_num1l#define eisa$v_slot8_pid_prod_num2 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_prod_num2j#define eisa$v_slot8_pid_rev_num1 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_rev_num1l#define eisa$v_slot8_pid_prod_num3 eisa$r_slot8_pid_overlay.eisa$r_slot8_pid_bits.eisa$v_slot8_pid_prod_num3B#define eisa$l_slot9_pid eisa$r_slot9_pid_overlay.eisa$l_slot9_pidd#define eisa$v_slot9_pid_char2 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_char2d#define eisa$v_slot9_pid_char1 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_char1d#define eisa$v_slot9_pid_char3 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_char3n#define eisa$v_slot9_pid_char2_cont eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_char2_contl#define eisa$v_slot9_pid_prod_num1 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_prod_num1l#define eisa$v_slot9_pid_prod_num2 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_prod_num2j#define eisa$v_slot9_pid_rev_num1 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_rev_num1l#define eisa$v_slot9_pid_prod_num3 eisa$r_slot9_pid_overlay.eisa$r_slot9_pid_bits.eisa$v_slot9_pid_prod_num3E#define eisa$l_slot10_pid eisa$r_slot10_pid_overlay.eisa$l_slot10_pidh#define eisa$v_slot10_pid_char2 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_char2h#define eisa$v_slot10_pid_char1 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_char1h#define eisa$v_slot10_pid_char3 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_char3r#define eisa$v_slot10_pid_char2_cont eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_char2_contp#define eisa$v_slot10_pid_prod_num1 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_prod_num1p#define eisa$v_slot10_pid_prod_num2 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_prod_num2n#define eisa$v_slot10_pid_rev_num1 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_rev_num1p#define eisa$v_slot10_pid_prod_num3 eisa$r_slot10_pid_overlay.eisa$r_slot10_pid_bits.eisa$v_slot10_pid_prod_num3E#define eisa$l_slot11_pid eisa$r_slot11_pid_overlay.eisa$l_slot11_pidh#define eisa$v_slot11_pid_char2 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_char2h#define eisa$v_slot11_pid_char1 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_char1h#define eisa$v_slot11_pid_char3 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_char3r#define eisa$v_slot11_pid_char2_cont eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_char2_contp#define eisa$v_slot11_pid_prod_num1 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_prod_num1p#define eisa$v_slot11_pid_prod_num2 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_prod_num2n#define eisa$v_slot11_pid_rev_num1 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_rev_num1p#define eisa$v_slot11_pi d_prod_num3 eisa$r_slot11_pid_overlay.eisa$r_slot11_pid_bits.eisa$v_slot11_pid_prod_num3E#define eisa$l_slot12_pid eisa$r_slot12_pid_overlay.eisa$l_slot12_pidh#define eisa$v_slot12_pid_char2 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_char2h#define eisa$v_slot12_pid_char1 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_char1h#define eisa$v_slot12_pid_char3 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_char3r#define eisa$v_slot12_pid_!char2_cont eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_char2_contp#define eisa$v_slot12_pid_prod_num1 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_prod_num1p#define eisa$v_slot12_pid_prod_num2 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_prod_num2n#define eisa$v_slot12_pid_rev_num1 eisa$r_slot12_pid_overlay.eisa$r_slot12_pid_bits.eisa$v_slot12_pid_rev_num1p#define eisa$v_slot12_pid_prod_num3 eisa$r_slot12_pid_overlay.eisa$r_slot12_"pid_bits.eisa$v_slot12_pid_prod_num3E#define eisa$l_slot13_pid eisa$r_slot13_pid_overlay.eisa$l_slot13_pidh#define eisa$v_slot13_pid_char2 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_char2h#define eisa$v_slot13_pid_char1 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_char1h#define eisa$v_slot13_pid_char3 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_char3r#define eisa$v_slot13_pid_char2_cont eisa$r_slot13_pid_overlay.eisa$r_slot13_p#id_bits.eisa$v_slot13_pid_char2_contp#define eisa$v_slot13_pid_prod_num1 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_prod_num1p#define eisa$v_slot13_pid_prod_num2 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_prod_num2n#define eisa$v_slot13_pid_rev_num1 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_rev_num1p#define eisa$v_slot13_pid_prod_num3 eisa$r_slot13_pid_overlay.eisa$r_slot13_pid_bits.eisa$v_slot13_pid_prod_num3E#define eisa$l$_slot14_pid eisa$r_slot14_pid_overlay.eisa$l_slot14_pidh#define eisa$v_slot14_pid_char2 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_char2h#define eisa$v_slot14_pid_char1 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_char1h#define eisa$v_slot14_pid_char3 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_char3r#define eisa$v_slot14_pid_char2_cont eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_char2_contp#define eisa$v%_slot14_pid_prod_num1 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_prod_num1p#define eisa$v_slot14_pid_prod_num2 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_prod_num2n#define eisa$v_slot14_pid_rev_num1 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_rev_num1p#define eisa$v_slot14_pid_prod_num3 eisa$r_slot14_pid_overlay.eisa$r_slot14_pid_bits.eisa$v_slot14_pid_prod_num3E#define eisa$l_slot15_pid eisa$r_slot15_pid_overlay.eisa$l_slot15_&pidh#define eisa$v_slot15_pid_char2 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_char2h#define eisa$v_slot15_pid_char1 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_char1h#define eisa$v_slot15_pid_char3 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_char3r#define eisa$v_slot15_pid_char2_cont eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_char2_contp#define eisa$v_slot15_pid_prod_num1 eisa$r_slot15_pid_overlay.eisa'$r_slot15_pid_bits.eisa$v_slot15_pid_prod_num1p#define eisa$v_slot15_pid_prod_num2 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_prod_num2n#define eisa$v_slot15_pid_rev_num1 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_rev_num1p#define eisa$v_slot15_pid_prod_num3 eisa$r_slot15_pid_overlay.eisa$r_slot15_pid_bits.eisa$v_slot15_pid_prod_num3"#endif /* #if !defined(__VAXC) */ N/* the following constants are useful for bus probing. */(N#define EISA$K_NODE0_BASE_CSR 0 /* this is the system */N/* board slot. */N#define EISA$K_NODE1_BASE_CSR 4096 /* this is slot 1 */N#define EISA$K_NODE2_BASE_CSR 8192 /* this is slot 2 */N#define EISA$K_NODE3_BASE_CSR 12288 /* this is slot 3 */N#define EISA$K_NODE4_BASE_CSR 16384 /* this is slot 4 */N#define EISA$K_NODE5_BAS)E_CSR 20480 /* this is slot 5 */N#define EISA$K_NODE6_BASE_CSR 24576 /* this is slot 6 */N#define EISA$K_NODE7_BASE_CSR 28672 /* this is slot 7 */N#define EISA$K_NODE8_BASE_CSR 32768 /* this is slot 8 */N#define EISA$K_NODE9_BASE_CSR 36864 /* this is slot 9 */N#define EISA$K_NODE10_BASE_CSR 40960 /* this is slot 10 */N#define EISA$K_NODE11_BASE_CSR 45056 /* this is* slot 11 */N#define EISA$K_NODE12_BASE_CSR 49152 /* this is slot 12 */N#define EISA$K_NODE13_BASE_CSR 53248 /* this is slot 13 */N#define EISA$K_NODE14_BASE_CSR 57344 /* this is slot 14 */N#define EISA$K_NODE15_BASE_CSR 61440 /* this is slot 15 */N#define EISA$K_PRODUCT_ID_REG_OFFSET 3200 /* offset from the slot base */N/* to the PID reg +*/N#define EISA$K_MAX_NODE_NUMBER 15 /* max slots is 15 */N#define EISA$K_DIGITAL_VENDOR_ID 524331 /* enet prefix */ "typedef struct _configdataheader { __union {0 unsigned short int eisacfghdr$w_version;' } eisacfghdr$r_version_overlay; __union {1 unsigned short int eisacfghdr$w_revision;( } eisacfghdr$r_revision_overlay; __union { int eisacfghdr$l_ptype;% } eisacfghdr$r_ptype_overl,ay; __union {! int eisacfghdr$l_pvendor;' } eisacfghdr$r_pvendor_overlay; __union { int eisacfghdr$l_pname;% } eisacfghdr$r_pname_overlay; __union {% int eisacfghdr$l_pserial_num;' } eisacfghdr$r_pserial_overlay; } CONFIGDATAHEADER; #if !defined(__VAXC)N#define eisacfghdr$w_version eisacfghdr$r_version_overlay.eisacfghdr$w_versionQ#define eisacfghdr$w_revision eisacfghdr$r_revision_overlay.eisacfghdr$w_revisionH#d -efine eisacfghdr$l_ptype eisacfghdr$r_ptype_overlay.eisacfghdr$l_ptypeN#define eisacfghdr$l_pvendor eisacfghdr$r_pvendor_overlay.eisacfghdr$l_pvendorH#define eisacfghdr$l_pname eisacfghdr$r_pname_overlay.eisacfghdr$l_pnameV#define eisacfghdr$l_pserial_num eisacfghdr$r_pserial_overlay.eisacfghdr$l_pserial_num"#endif /* #if !defined(__VAXC) */ "#define EISASLOTINFO$M_CFG_REV 0xF%#define EISASLOTINFO$M_SLOT_TYPE 0x30##define EISASLOTINFO$M_READ_ID 0x40"#define EISASLOTINFO$M_DUP_ID 0x80%#d.efine EISASLOTINFO$M_TYPE_ENTRY 0x1$#define EISASLOTINFO$M_MEM_ENTRY 0x2$#define EISASLOTINFO$M_IRQ_ENTRY 0x4$#define EISASLOTINFO$M_DMA_ENTRY 0x8,#define EISASLOTINFO$M_PORT_RANGE_ENTRY 0x10+#define EISASLOTINFO$M_PORT_INIT_ENTRY 0x20%#define EISASLOTINFO$M_CHAR_2_MSB 0x3"#define EISASLOTINFO$M_CHAR_1 0x7C&#define EISASLOTINFO$M_CHAR_3_MSB 0x1F&#define EISASLOTINFO$M_CHAR_2_LSB 0xE0 #define EISASLOTINFO$M_HEX_2 0xF!#define EISASLOTINFO$M_HEX_1 0xF0 #define EISASLOTINFO$M_HEX_4 0xF!#d/efine EISASLOTINFO$M_HEX_3 0xF0 typedef struct _eisaslotinfo { __union {, unsigned char eisaslotinfo$b_slotid; __struct {0 unsigned eisaslotinfo$v_cfg_rev : 4;2 unsigned eisaslotinfo$v_slot_type : 2;0 unsigned eisaslotinfo$v_read_id : 1;/ unsigned eisaslotinfo$v_dup_id : 1;) } eisaslotinfo$r_slotid_bits;( } eisaslotinfo$r_slotid_overlay;/ unsigned char eisaslotinfo$b_major_cfg_rev;/ unsigned c 0har eisaslotinfo$b_minor_cfg_rev;. unsigned char eisaslotinfo$b_cfg_chksum_1;. unsigned char eisaslotinfo$b_cfg_chksum_2;. unsigned char eisaslotinfo$b_num_dev_func; __union {/ unsigned char eisaslotinfo$b_func_info; __struct {3 unsigned eisaslotinfo$v_type_entry : 1;2 unsigned eisaslotinfo$v_mem_entry : 1;2 unsigned eisaslotinfo$v_irq_entry : 1;2 unsigned eisaslotinfo$v_dma_entry : 1;9 unsigned eisaslo 1tinfo$v_port_range_entry : 1;8 unsigned eisaslotinfo$v_port_init_entry : 1;/ unsigned eisaslotinfo$v_fillit : 2;, } eisaslotinfo$r_func_info_bits;+ } eisaslotinfo$r_func_info_overlay; __union {. unsigned char eisaslotinfo$b_pid_byte; __struct {N unsigned eisaslotinfo$v_char_2_msb : 2; /* bits <1:0> (2 msb's) */N unsigned eisaslotinfo$v_char_1 : 5; /* bits <6:2> */N unsigned eisaslo 2tinfo$v_rsvd1 : 1; /* bit <7> */, } eisaslotinfo$r_pid_byte0_bits;& } eisaslotinfo$r_pid0_overlay; __union {/ unsigned char eisaslotinfo$b_pid_byte1; __struct {N unsigned eisaslotinfo$v_char_3_msb : 5; /* bits <4:0> */N unsigned eisaslotinfo$v_char_2_lsb : 3; /* bits <7:5> */, } eisaslotinfo$r_pid_byte1_bits;& } eisaslotinfo$r_pid1_overlay; __union {/ unsigned c3har eisaslotinfo$b_pid_byte2; __struct {. unsigned eisaslotinfo$v_hex_2 : 4;. unsigned eisaslotinfo$v_hex_1 : 4;, } eisaslotinfo$r_pid_byte2_bits;& } eisaslotinfo$r_pid2_overlay; __union {/ unsigned char eisaslotinfo$b_pid_byte3; __struct {. unsigned eisaslotinfo$v_hex_4 : 4;. unsigned eisaslotinfo$v_hex_3 : 4;, } eisaslotinfo$r_pid_byte3_bits;& } eisaslotinfo$r_pid3_overlay;4 } EISASLOTINFO; #if !defined(__VAXC)Q#define eisaslotinfo$b_slotid eisaslotinfo$r_slotid_overlay.eisaslotinfo$b_slotidn#define eisaslotinfo$v_cfg_rev eisaslotinfo$r_slotid_overlay.eisaslotinfo$r_slotid_bits.eisaslotinfo$v_cfg_revr#define eisaslotinfo$v_slot_type eisaslotinfo$r_slotid_overlay.eisaslotinfo$r_slotid_bits.eisaslotinfo$v_slot_typen#define eisaslotinfo$v_read_id eisaslotinfo$r_slotid_overlay.eisaslotinfo$r_slotid_bits.eisaslotinfo$v_read_idl#define eisaslotinfo$v_dup_id eisa5slotinfo$r_slotid_overlay.eisaslotinfo$r_slotid_bits.eisaslotinfo$v_dup_idZ#define eisaslotinfo$b_func_info eisaslotinfo$r_func_info_overlay.eisaslotinfo$b_func_infoz#define eisaslotinfo$v_type_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_bits.eisaslotinfo$v_type_entryx#define eisaslotinfo$v_mem_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_bits.eisaslotinfo$v_mem_entryx#define eisaslotinfo$v_irq_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_b6its.eisaslotinfo$v_irq_entryx#define eisaslotinfo$v_dma_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_bits.eisaslotinfo$v_dma_entry#define eisaslotinfo$v_port_range_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_bits.eisaslotinfo$v_port_range_en\try#define eisaslotinfo$v_port_init_entry eisaslotinfo$r_func_info_overlay.eisaslotinfo$r_func_info_bits.eisaslotinfo$v_port_init_entryS#define eisaslotinfo$b_pid_byte eisaslotinfo$r_pid0_overlay.eisaslotinfo$b_pid_b7yteu#define eisaslotinfo$v_char_2_msb eisaslotinfo$r_pid0_overlay.eisaslotinfo$r_pid_byte0_bits.eisaslotinfo$v_char_2_msbm#define eisaslotinfo$v_char_1 eisaslotinfo$r_pid0_overlay.eisaslotinfo$r_pid_byte0_bits.eisaslotinfo$v_char_1U#define eisaslotinfo$b_pid_byte1 eisaslotinfo$r_pid1_overlay.eisaslotinfo$b_pid_byte1u#define eisaslotinfo$v_char_3_msb eisaslotinfo$r_pid1_overlay.eisaslotinfo$r_pid_byte1_bits.eisaslotinfo$v_char_3_msbu#define eisaslotinfo$v_char_2_lsb eisaslotinfo$r_pid1_overla8y.eisaslotinfo$r_pid_byte1_bits.eisaslotinfo$v_char_2_lsbU#define eisaslotinfo$b_pid_byte2 eisaslotinfo$r_pid2_overlay.eisaslotinfo$b_pid_byte2k#define eisaslotinfo$v_hex_2 eisaslotinfo$r_pid2_overlay.eisaslotinfo$r_pid_byte2_bits.eisaslotinfo$v_hex_2k#define eisaslotinfo$v_hex_1 eisaslotinfo$r_pid2_overlay.eisaslotinfo$r_pid_byte2_bits.eisaslotinfo$v_hex_1U#define eisaslotinfo$b_pid_byte3 eisaslotinfo$r_pid3_overlay.eisaslotinfo$b_pid_byte3k#define eisaslotinfo$v_hex_4 eisaslotinfo$r_pid3_o 9verlay.eisaslotinfo$r_pid_byte3_bits.eisaslotinfo$v_hex_4k#define eisaslotinfo$v_hex_3 eisaslotinfo$r_pid3_overlay.eisaslotinfo$r_pid_byte3_bits.eisaslotinfo$v_hex_3"#endif /* #if !defined(__VAXC) */ ##define EISACONFIG$M_CHAR_2_MSB 0x3 #define EISACONFIG$M_CHAR_1 0x7C$#define EISACONFIG$M_CHAR_3_MSB 0x1F$#define EISACONFIG$M_CHAR_2_LSB 0xE0#define EISACONFIG$M_HEX_2 0xF#define EISACONFIG$M_HEX_1 0xF0#define EISACONFIG$M_HEX_4 0xF#define EISACONFIG$M_HEX_3 0xF0 #define EISACONF:IG$M_CFG_REV 0xF##define EISACONFIG$M_SLOT_TYPE 0x30!#define EISACONFIG$M_READ_ID 0x40 #define EISACONFIG$M_DUP_ID 0x80$#define EISACONFIG$M_EISA_ENABLE 0x1!#define EISACONFIG$M_IOCHKERR 0x2"#define EISACONFIG$M_CFG_DONE 0x80##define EISACONFIG$M_TYPE_ENTRY 0x1"#define EISACONFIG$M_MEM_ENTRY 0x2"#define EISACONFIG$M_IRQ_ENTRY 0x4"#define EISACONFIG$M_DMA_ENTRY 0x8*#define EISACONFIG$M_PORT_RANGE_ENTRY 0x10)#define EISACONFIG$M_PORT_INIT_ENTRY 0x20'#define EISACONFIG$M_CFG_FREE_FORM 0;x40"#define EISACONFIG$M_FUNC_ENB 0x80 #define EISACONFIG$M_ROM_RAM 0x1##define EISACONFIG$M_MEM_CACHED 0x2"#define EISACONFIG$M_MEM_TYPE 0x18$#define EISACONFIG$M_SHARED_MEM 0x20*#define EISACONFIG$M_MORE_MEM_ENTRIES 0x80(#define EISACONFIG$M_MEM_ACCESS_SIZE 0x3(#define EISACONFIG$M_MEM_DECODE_SIZE 0xC #define EISACONFIG$M_INT_0_F 0xF&#define EISACONFIG$M_INT_EDGE_LVL 0x20$#define EISACONFIG$M_INT_SHARED 0x40(#define EISACONFIG$M_INT_LAST_ENTRY 0x80'#define EISACONFIG$M_DMA_LAST_ENTRY <0x1##define EISACONFIG$M_DMA_SHARED 0x2"#define EISACONFIG$M_DMA_CHAN 0xE0##define EISACONFIG$M_DMA_TIMING 0xC'#define EISACONFIG$M_DMA_XFER_SIZE 0x30+#define EISACONFIG$M_PORT_IO_LAST_ENTRY 0x1'#define EISACONFIG$M_PORT_IO_SHARED 0x2+#define EISACONFIG$M_NUM_IO_PORT_BYTES 0xF8 typedef struct _eisaconfigdef { __union {, unsigned char eisaconfig$b_pid_byte; __struct {N unsigned eisaconfig$v_char_2_msb : 2; /* bits <1:0> (2 msb's) */N = unsigned eisaconfig$v_char_1 : 5; /* bits <6:2> */N unsigned eisaconfig$v_rsvd1 : 1; /* bit <7> */* } eisaconfig$r_pid_byte0_bits;$ } eisaconfig$r_pid0_overlay; __union {- unsigned char eisaconfig$b_pid_byte1; __struct {N unsigned eisaconfig$v_char_3_msb : 5; /* bits <4:0> */N unsigned eisaconfig$v_char_2_lsb : 3; /* bits <7:5> */* } eisaconfig$r_p>id_byte1_bits;$ } eisaconfig$r_pid1_overlay; __union {- unsigned char eisaconfig$b_pid_byte2; __struct {, unsigned eisaconfig$v_hex_2 : 4;, unsigned eisaconfig$v_hex_1 : 4;* } eisaconfig$r_pid_byte2_bits;$ } eisaconfig$r_pid2_overlay; __union {- unsigned char eisaconfig$b_pid_byte3; __struct {, unsigned eisaconfig$v_hex_4 : 4;, unsigned eisaconfig$v_hex_3 : 4;* } ?eisaconfig$r_pid_byte3_bits;$ } eisaconfig$r_pid3_overlay; __union {* unsigned char eisaconfig$b_slotid; __struct {. unsigned eisaconfig$v_cfg_rev : 4;0 unsigned eisaconfig$v_slot_type : 2;. unsigned eisaconfig$v_read_id : 1;- unsigned eisaconfig$v_dup_id : 1;' } eisaconfig$r_slotid_bits;' } eisaconfig$r_slot_id_overlay; __union {. unsigned char eisaconfig$b_config_err; __stru @ct {2 unsigned eisaconfig$v_eisa_enable : 1;/ unsigned eisaconfig$v_iochkerr : 1;, unsigned eisaconfig$v_fill3 : 5;/ unsigned eisaconfig$v_cfg_done : 1;+ } eisaconfig$r_config_err_bits;* } eisaconfig$r_config_err_overlay;- unsigned char eisaconfig$b_minor_cfg_rev;- unsigned char eisaconfig$b_major_cfg_rev;+ char eisaconfig$b_selection_field [26]; __union {- unsigned char eisaconfig$b_func_info; A __struct {1 unsigned eisaconfig$v_type_entry : 1;0 unsigned eisaconfig$v_mem_entry : 1;0 unsigned eisaconfig$v_irq_entry : 1;0 unsigned eisaconfig$v_dma_entry : 1;7 unsigned eisaconfig$v_port_range_entry : 1;6 unsigned eisaconfig$v_port_init_entry : 1;4 unsigned eisaconfig$v_cfg_free_form : 1;/ unsigned eisaconfig$v_func_enb : 1;* } eisaconfig$r_func_info_bits;) } eisaconfig$r_fBunc_info_overlay;6 unsigned char eisaconfig$b_type_stype_string [80];N/* the memory config region can contain up to 9 7 byte descriptions of */N/* assigned memory regions. In general, only */N/* one of the regions is used, but, for instance, some VGA cards require */P/* 4 buffers. These buffers would be specified in the first 4 7-byte blocks. */O/* Only one of the 7 byte regions has offsets defined here, the remaining 56 */U/* bytes of memory config Cinformation should be accessed using the defined offsets */W/* plus an offset of 7*#mem_config_block_being_returned. ie, to access the 1st byte */T/* of the ith config block being returned for this card, the bliss code would be */g/* mem_config_byte = .ptr_to_1st_mem_config_block[$byteoffset(eisaconfig$b_mem_config)+(i*7),0,8,0]; */c/* In order to reference the interior bits of these bytes, use the $bitposition macro similarly. */N/* these macros are all defined in starlet. D */N/* */ __union {. unsigned char eisaconfig$b_mem_config; __struct {. unsigned eisaconfig$v_rom_ram : 1;1 unsigned eisaconfig$v_mem_cached : 1;- unsigned eisaconfig$v_fill2a : 1;/ unsigned eisaconfig$v_mem_type : 2;1 unsigned eisaconfig$v_shared_mem : 1;. unsigned eisaconfig$v_fill2a1 : 1;7 unsigned e Eisaconfig$v_more_mem_entries : 1;+ } eisaconfig$r_mem_config_bits;* } eisaconfig$r_mem_config_overlay; __union {1 unsigned char eisaconfig$b_mem_data_size; __struct {6 unsigned eisaconfig$v_mem_access_size : 2;6 unsigned eisaconfig$v_mem_decode_size : 2;- unsigned eisaconfig$v_fill2a : 4;. } eisaconfig$r_mem_data_size_bits;- } eisaconfig$r_mem_data_size_overlay;[ unsigned char eisaconfig$b_memF_addr_byte1; /*this 3 byte field should be multiplied */\ unsigned char eisaconfig$b_mem_addr_byte2; /*by 100h to get the true starting address */. unsigned char eisaconfig$b_mem_addr_byte3;] unsigned char eisaconfig$b_mem_size_byte1; /*this field needs to be multiplied by 400h */a unsigned char eisaconfig$b_mem_size_byte2; /* to get the true size, if byte1=0, size = 64M */W/* now we need the fill to leave space for the remaining 56 bytes of mem config data */" char eisaconfiGg$b_fill3a [56];Y/* the following byte specifies the interrupt request information needed by the device */]/* each block is 2 bytes long, and there can be up to 7 blocks. Apparently some cards can */Q/* have a function which needs several irq's. Again, the offsets for a single */_/* interrupt definition are defined here, to access multiple interrupt definitions, use the */]/* starlet macros $byteoffset, $bitposition, $fieldwidth, $extension and an index into the */N/* interrupt definitio Hn blocks. See the mem config block example above. */ __union {* unsigned char eisaconfig$b_interr; __struct {. unsigned eisaconfig$v_int_0_f : 4;, unsigned eisaconfig$v_fill3 : 1;3 unsigned eisaconfig$v_int_edge_lvl : 1;1 unsigned eisaconfig$v_int_shared : 1;5 unsigned eisaconfig$v_int_last_entry : 1;' } eisaconfig$r_interr_bits;- } eisaconfig$r_interr_config_overlay;N/* now leave the spaIce for the remaining 13 potential blocks of IRQ info. */" char eisaconfig$b_fill3b [13];S/* the following byte specifies the dma channel information needed by the device */]/* each block is 2 bytes long, and there can be up to 4 blocks. Apparently some cards can */X/* have a function which needs several dma channels. Again, the offsets for a single */N/* block definition are defined here, to access multiple blocks, use the */]/* starlet macros $byteoffset, $bitposition, $fieldwidth, J$extension and an index into the */N/* definition blocks. See the mem config block example above. */ __union {- unsigned char eisaconfig$b_dma_byte0; __struct {5 unsigned eisaconfig$v_dma_last_entry : 1;1 unsigned eisaconfig$v_dma_shared : 1;, unsigned eisaconfig$v_fill4 : 3;/ unsigned eisaconfig$v_dma_chan : 3;* } eisaconfig$r_dma_byte0_bits;- } eisaconfig$r_dma_chan_config_overl; __ Kunion {- unsigned char eisaconfig$b_dma_byte1; __struct {- unsigned eisaconfig$v_fill4a : 2;1 unsigned eisaconfig$v_dma_timing : 2;4 unsigned eisaconfig$v_dma_xfer_size : 2;, unsigned eisaconfig$v_fill4 : 2;* } eisaconfig$r_dma_byte1_bits;- } eisaconfig$r_dma_chan_config1_over; char eisaconfig$b_fill6 [6];V/* the following block contains the necessary information specifying which IO ports */Y/* a board hLas been assigned to use. Each entry consists of 3 bytes, and there can be */]/* as many as 20 entries, for a total size of 60 bytes. The first byte specifies if there */a/* are more entries to follow, and the number of ports-1 defined.(ie how many sequential bytes */N/* has the board been reserved) */b/* the second and third bytes specify the starting address. As per the above blocks, there are */c/* not 60 entries defined here. Instead a single Mentry is defined and the user needs to use the */b/* starlett macros $byteoffset, $bitposition, etc. and an index into the IO port config data to */N/* reference IO port block definitions 2-20. See mem config example above. */ __union {1 unsigned char eisaconfig$b_port_io_byte0; __struct {9 unsigned eisaconfig$v_port_io_last_entry : 1;5 unsigned eisaconfig$v_port_io_shared : 1;- unsigned eisaconfig$v_fill5a : 1;8 unsignedN eisaconfig$v_num_io_port_bytes : 5;. } eisaconfig$r_port_io_byte0_bits;, } eisaconfig$r_port_io_info_overlay;. unsigned char eisaconfig$b_port_io_addr_l;. unsigned char eisaconfig$b_port_io_addr_h;^ char eisaconfig$b_fill7 [57]; /* now leave space for the remaining port io blocks */]/* a major contribution of the ECU is it's ability to initialize board CSR with predefined */a/* information. This aspect of the ECU is utilized before boot, and the following inf Oormation */e/* is not of importance to the VMS Bus Support code, so nothing is defined for it, space is simply */N/* reserved. */% char eisaconfig$b_init_data [60]; } EISACONFIGDEF; #if !defined(__VAXC)M#define eisaconfig$b_pid_byte eisaconfig$r_pid0_overlay.eisaconfig$b_pid_bytem#define eisaconfig$v_char_2_msb eisaconfig$r_pid0_overlay.eisaconfig$r_pid_byte0_bits.eisaconfig$v_char_2_msbe#define eisaconfig$v_char_1 Peisaconfig$r_pid0_overlay.eisaconfig$r_pid_byte0_bits.eisaconfig$v_char_1O#define eisaconfig$b_pid_byte1 eisaconfig$r_pid1_overlay.eisaconfig$b_pid_byte1m#define eisaconfig$v_char_3_msb eisaconfig$r_pid1_overlay.eisaconfig$r_pid_byte1_bits.eisaconfig$v_char_3_msbm#define eisaconfig$v_char_2_lsb eisaconfig$r_pid1_overlay.eisaconfig$r_pid_byte1_bits.eisaconfig$v_char_2_lsbO#define eisaconfig$b_pid_byte2 eisaconfig$r_pid2_overlay.eisaconfig$b_pid_byte2c#define eisaconfig$v_hex_2 eisaconfig$r_piQd2_overlay.eisaconfig$r_pid_byte2_bits.eisaconfig$v_hex_2c#define eisaconfig$v_hex_1 eisaconfig$r_pid2_overlay.eisaconfig$r_pid_byte2_bits.eisaconfig$v_hex_1O#define eisaconfig$b_pid_byte3 eisaconfig$r_pid3_overlay.eisaconfig$b_pid_byte3c#define eisaconfig$v_hex_4 eisaconfig$r_pid3_overlay.eisaconfig$r_pid_byte3_bits.eisaconfig$v_hex_4c#define eisaconfig$v_hex_3 eisaconfig$r_pid3_overlay.eisaconfig$r_pid_byte3_bits.eisaconfig$v_hex_3L#define eisaconfig$b_slotid eisaconfig$r_slot_id_overlay.eRisaconfig$b_slotidg#define eisaconfig$v_cfg_rev eisaconfig$r_slot_id_overlay.eisaconfig$r_slotid_bits.eisaconfig$v_cfg_revk#define eisaconfig$v_slot_type eisaconfig$r_slot_id_overlay.eisaconfig$r_slotid_bits.eisaconfig$v_slot_typeg#define eisaconfig$v_read_id eisaconfig$r_slot_id_overlay.eisaconfig$r_slotid_bits.eisaconfig$v_read_ide#define eisaconfig$v_dup_id eisaconfig$r_slot_id_overlay.eisaconfig$r_slotid_bits.eisaconfig$v_dup_idW#define eisaconfig$b_config_err eisaconfig$r_config_err_overSlay.eisaconfig$b_config_errv#define eisaconfig$v_eisa_enable eisaconfig$r_config_err_overlay.eisaconfig$r_config_err_bits.eisaconfig$v_eisa_enablep#define eisaconfig$v_iochkerr eisaconfig$r_config_err_overlay.eisaconfig$r_config_err_bits.eisaconfig$v_iochkerrp#define eisaconfig$v_cfg_done eisaconfig$r_config_err_overlay.eisaconfig$r_config_err_bits.eisaconfig$v_cfg_doneT#define eisaconfig$b_func_info eisaconfig$r_func_info_overlay.eisaconfig$b_func_infor#define eisaconfig$v_type_entry eisaconfigT$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_type_entryp#define eisaconfig$v_mem_entry eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_mem_entryp#define eisaconfig$v_irq_entry eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_irq_entryp#define eisaconfig$v_dma_entry eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_dma_entry~#define eisaconfig$v_port_range_entry eisaconfig$r_func_info_overlay.eisaconfig$r_func_infUo_bits.eisaconfig$v_port_range_entry|#define eisaconfig$v_port_init_entry eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_port_init_entryx#define eisaconfig$v_cfg_free_form eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_cfg_free_formn#define eisaconfig$v_func_enb eisaconfig$r_func_info_overlay.eisaconfig$r_func_info_bits.eisaconfig$v_func_enbW#define eisaconfig$b_mem_config eisaconfig$r_mem_config_overlay.eisaconfig$b_mem_confign#define eisaconfigV$v_rom_ram eisaconfig$r_mem_config_overlay.eisaconfig$r_mem_config_bits.eisaconfig$v_rom_ramt#define eisaconfig$v_mem_cached eisaconfig$r_mem_config_overlay.eisaconfig$r_mem_config_bits.eisaconfig$v_mem_cachedp#define eisaconfig$v_mem_type eisaconfig$r_mem_config_overlay.eisaconfig$r_mem_config_bits.eisaconfig$v_mem_typet#define eisaconfig$v_shared_mem eisaconfig$r_mem_config_overlay.eisaconfig$r_mem_config_bits.eisaconfig$v_shared_mem#define eisaconfig$v_more_mem_entries eisaconfig$r_mem_config_Woverlay.eisaconfig$r_mem_config_bits.eisaconfig$v_more_mem_entries`#define eisaconfig$b_mem_data_size eisaconfig$r_mem_data_size_overlay.eisaconfig$b_mem_data_size#define eisaconfig$v_mem_access_size eisaconfig$r_mem_data_size_overlay.eisaconfig$r_mem_data_size_bits.eisaconfig$v_mem_access_size#define eisaconfig$v_mem_decode_size eisaconfig$r_mem_data_size_overlay.eisaconfig$r_mem_data_size_bits.eisaconfig$v_mem_decode_sizeR#define eisaconfig$b_interr eisaconfig$r_interr_config_overlay.eisaconfiXg$b_interrm#define eisaconfig$v_int_0_f eisaconfig$r_interr_config_overlay.eisaconfig$r_interr_bits.eisaconfig$v_int_0_fw#define eisaconfig$v_int_edge_lvl eisaconfig$r_interr_config_overlay.eisaconfig$r_interr_bits.eisaconfig$v_int_edge_lvls#define eisaconfig$v_int_shared eisaconfig$r_interr_config_overlay.eisaconfig$r_interr_bits.eisaconfig$v_int_shared{#define eisaconfig$v_int_last_entry eisaconfig$r_interr_config_overlay.eisaconfig$r_interr_bits.eisaconfig$v_int_last_entryX#define eisaconfYig$b_dma_byte0 eisaconfig$r_dma_chan_config_overl.eisaconfig$b_dma_byte0~#define eisaconfig$v_dma_last_entry eisaconfig$r_dma_chan_config_overl.eisaconfig$r_dma_byte0_bits.eisaconfig$v_dma_last_entryv#define eisaconfig$v_dma_shared eisaconfig$r_dma_chan_config_overl.eisaconfig$r_dma_byte0_bits.eisaconfig$v_dma_sharedr#define eisaconfig$v_dma_chan eisaconfig$r_dma_chan_config_overl.eisaconfig$r_dma_byte0_bits.eisaconfig$v_dma_chanX#define eisaconfig$b_dma_byte1 eisaconfig$r_dma_chan_config1_over.eiZsaconfig$b_dma_byte1v#define eisaconfig$v_dma_timing eisaconfig$r_dma_chan_config1_over.eisaconfig$r_dma_byte1_bits.eisaconfig$v_dma_timing|#define eisaconfig$v_dma_xfer_size eisaconfig$r_dma_chan_config1_over.eisaconfig$r_dma_byte1_bits.eisaconfig$v_dma_xfer_size_#define eisaconfig$b_port_io_byte0 eisaconfig$r_port_io_info_overlay.eisaconfig$b_port_io_byte0#define eisaconfig$v_port_io_last_entry eisaconfig$r_port_io_info_overlay.eisaconfig$r_port_io_byte0_bits.eisaconfig$v_port_io_last\_entry [#define eisaconfig$v_port_io_shared eisaconfig$r_port_io_info_overlay.eisaconfig$r_port_io_byte0_bits.eisaconfig$v_port_io_shared#define eisaconfig$v_num_io_port_bytes eisaconfig$r_port_io_info_overlay.eisaconfig$r_port_io_byte0_bits.eisaconfig$v_num_io_port_b\ytes"#endif /* #if !defined(__VAXC) */ #define EISA_HW_ID_MASK_LO -1#define EISA_HW_ID_MASK_HI -1 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#p\ragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EISABUSDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterp]rise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is ^not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************************** _***************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */G/* Source: 16-APR-1998 16:19:46 $1$DGA8345:[LIB_H.SRC]EISDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EISDDEF ***/#ifndef __EISDDEF_LOADED#define __EISDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save`#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __staruct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* EXTENDED IMAGE SECTION DESCRIPTOR DEFINITIONS */N/*- */#define EISD$K_MAJORID 1b#define EISD$K_MINORID 1#define EISD$M_GBL 0x1#define EISD$M_CRF 0x2#define EISD$M_DZRO 0x4#define EISD$M_WRT 0x8#define EISD$M_INITALCODE 0x10#define EISD$M_BASED 0x20#define EISD$M_FIXUPVEC 0x40#define EISD$M_RESIDENT 0x80#define EISD$M_VECTOR 0x100#define EISD$M_PROTECT 0x200#define EISD$M_LASTCLU 0x400#define EISD$M_EXE 0x800#define EISD$M_NONSHRADR 0x1000!#define EISD$M_QUAD_LENGTH 0x2000!#define EISD$M_ALLOC_64BIT 0x4000U#define EISD$K_LENDZRO 36 c/*LENGTH OF DEMAND ZERO ISD (OR STACK ISD) */U#define EISD$C_LENDZRO 36 /*LENGTH OF DEMAND ZERO ISD (OR STACK ISD) */N#define EISD$K_LENPRIV 36 /*LENGTH OF PRIVATE ISD */N#define EISD$C_LENPRIV 36 /*LENGTH OF PRIVATE ISD */N#define EISD$K_LENGLBL 56 /*LENGTH OF OLD GLOBAL ISD */N#define EISD$C_LENGLBL 56 /*LENGTH OF OLD GLOBAL ISD */N#define EISD$K_MAXLENGLBL 84 /*MAX LENGdTH OF NEW GLOBAL ISD */N#define EISD$C_MAXLENGLBL 84 /*MAX LENGTH OF NEW GLOBAL ISD */N/*+ */N#define EISD$K_MATALL 0 /*MATCH ALWAYS, USE GLOBAL SECTION */N#define EISD$K_MATEQU 1 /*MATCH IF ISD$L_IDENT EQU GBL ID */N#define EISD$K_MATLEQ 2 /*MATCH IF ISD$L_IDENT LEQ GBL ID */N#define EISD$K_MATNEV 3 /*MATCH NEVER, USE PRIVATE COPY e*/N/*+ */N#define EISD$K_NORMAL 0 /*NORMAL PROGRAM IMAGE SECTION */N/*NO SPECIAL ACTION REQUIRED */N#define EISD$K_SHRFXD 1 /*SHAREABLE FIXED SECTION */N#define EISD$K_PRVFXD 2 /*PRIVATE FIXED SECTION */N#define EISD$K_SHRPIC 3 /*SHAREABLE PIC SECTION */N#define EISD$K_PRVPIC f4 /*PRIVATE PIC SECTION */N#define EISD$K_USRSTACK 253 /*USER STACK SECTION */N#define EISD$S_EISDDEF 84 /* Old size name - synonym */ typedef struct _eisd {N __struct { /* Version of this EISD */N unsigned int eisd$l_majorid; /* Major ID */N unsigned int eisd$l_minorid; /* Minor ID */ } eisd$r_ver gsion;N unsigned int eisd$l_eisdsize; /*SIZE IN BYTES OF THIS EISD */\ unsigned int eisd$l_secsize; /*SIZE OF SECTION IN BYTES DESCRIBED BY THIS ISD */ __union {N unsigned __int64 eisd$q_virt_addr; /* Virtual address of section */N void *eisd$l_virt_addr; /* low 32 bits of virtual address */ __struct {N unsigned eisd$v_vaddr : 30; /* Virtual address in region */N unsigned eisd$v_p1 : 1; /* P1 hSPACE */N unsigned eisd$v_system : 1; /* SYSTEM SPACE */ } eisd$r_va_bits;! } eisd$r_address_overlay; __union {N unsigned int eisd$l_flags; /*FLAGS AND ISD TYPE */ __struct {N unsigned eisd$v_gbl : 1; /* GLOBAL */N unsigned eisd$v_crf : 1; /* COPY ON REFERENCE */N unsigned eisd$v_dzro : 1; /* DEMiAND ZERO PAGE */N unsigned eisd$v_wrt : 1; /* WRITABLE */T unsigned eisd$v_initalcode : 1; /* ISD IS PART OF INITIALIZATION CODE */N unsigned eisd$v_based : 1; /* ISECT IS BASED */N unsigned eisd$v_fixupvec : 1; /* ISECT IS FIXUP SECTION */N unsigned eisd$v_resident : 1; /* ISECT IS MEMORY-RESIDENT */P unsigned eisd$v_vector : 1; /* VECTOR CONTAINED IN IMAjGE SECTION */N unsigned eisd$v_protect : 1; /* IMAGE SECTION IS PROTECTED */N unsigned eisd$v_lastclu : 1; /* LAST CLUSTER */R unsigned eisd$v_exe : 1; /* IF SET, THIS IS A CODE IMAGE SECTION */d unsigned eisd$v_nonshradr : 1; /* IF SET, SECTION CONTAINS NON-SHAREABLE ADDRESS DATA */f unsigned eisd$v_quad_length : 1; /* If set, quad length field (eisd$q_secsize) is valid */S unsigned eisd$v_alloc_64bit k: 1; /* If set, allocate in 64-bit space */( unsigned eisd$v_fill_0_ : 1; } eisd$r_flags_bits; } eisd$r_flags_overlay;N unsigned int eisd$l_vbn; /*BASE VIRTUAL BLOCK NUMBER */N __struct { /*Conrtol fields */N unsigned char eisd$b_pfc; /*Page faule cluster */N unsigned char eisd$b_matchctl; /*Linker match control */N unsigned char eisd$b_t lype; /*Section type */N unsigned char eisd$b_fill_1; /*filler */ } eisd$r_control;N unsigned int eisd$l_ident; /*IDENT FOR GLOBAL SECTION */ __union {N char eisd$t_gblnam [44]; /*GLOBAL NAME COUNTED STRING */O unsigned __int64 eisd$q_secsize; /*Quadword size for 64-bit sections */ } eisd$r_gblnam_overlay;N/* MATCH CONTROL VIELD VALUES m */N/*- */N/*BASE OF ZERO , INCR 1 */N/* ISD TYPE FIELD DEFINITIONS */N/*- */ } EISD; #if !defined(__VAXC)4#define eisd$l_majorid eisd$r_version.eisd$l_majorid4#define eisd$l_minorid eisd$r_version.eisd$l_minorid@#define eisd$qn_virt_addr eisd$r_address_overlay.eisd$q_virt_addr@#define eisd$l_virt_addr eisd$r_address_overlay.eisd$l_virt_addrG#define eisd$v_vaddr eisd$r_address_overlay.eisd$r_va_bits.eisd$v_vaddrA#define eisd$v_p1 eisd$r_address_overlay.eisd$r_va_bits.eisd$v_p1I#define eisd$v_system eisd$r_address_overlay.eisd$r_va_bits.eisd$v_system6#define eisd$l_flags eisd$r_flags_overlay.eisd$l_flagsD#define eisd$v_gbl eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_gblD#define eisd$v_crf eisd$r_flags_overlay.eisdo$r_flags_bits.eisd$v_crfF#define eisd$v_dzro eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_dzroD#define eisd$v_wrt eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_wrtR#define eisd$v_initalcode eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_initalcodeH#define eisd$v_based eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_basedN#define eisd$v_fixupvec eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_fixupvecN#define eisd$v_resident eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_residentJ#define eisd$v_vectopr eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_vectorL#define eisd$v_protect eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_protectL#define eisd$v_lastclu eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_lastcluD#define eisd$v_exe eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_exeP#define eisd$v_nonshradr eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_nonshradrT#define eisd$v_quad_length eisd$r_flags_overlay.eisd$r_flags_bits.eisd$v_quad_lengthT#define eisd$v_alloc_64bit eisd$r_flags_overlay.eisd$r_f qlags_bits.eisd$v_alloc_64bit,#define eisd$b_pfc eisd$r_control.eisd$b_pfc6#define eisd$b_matchctl eisd$r_control.eisd$b_matchctl.#define eisd$b_type eisd$r_control.eisd$b_type2#define eisd$b_fill_1 eisd$r_control.eisd$b_fill_19#define eisd$t_gblnam eisd$r_gblnam_overlay.eisd$t_gblnam;#define eisd$q_secsize eisd$r_gblnam_overlay.eisd$q_secsize"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas rsupported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EISDDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-sPackard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software,t Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************** u*****************************************************/=/* Created: 7-Oct-2024 15:23:30 by OpenVMS SDL V3.7 */H/* Source: 27-AUG-1993 10:48:13 $1$DGA8345:[LIB_H.SRC]EMBBCDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBBCDEF ***/#ifndef __EMBBCDEF_LOADED#define __EMBBCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __memberv_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endifw #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* BUGCHECK ERROR MESSAGE BUFFER FORMAT (SYSTEM AND USER) */N/* */ #inc xlude T#define EMB$K_BC_LENGTH 416 /*SIZE OF FIXED PART OF BUGCHECK MESSAGE */T#define EMB$C_BC_LENGTH 416 /*SIZE OF FIXED PART OF BUGCHECK MESSAGE */N#define EMB$S_EMBBCDEF 416 /*Old size name - synonym */ typedef struct _embbc {N unsigned int emb$l_bc_sid; /*SYSTEM ID */N unsigned short int emb$w_bc_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_bc_xsid; /* SyYS_TYPE REGISTER */N unsigned int emb$l_bc_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_bc_dev_class; /* DEVICE CLASS */N unsigned char emb$b_bc_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$r_bc_scs_name; /* SCS node name ASCIC */N unsigned short int emb$w_bc_flags; /* MISC. FLAGS */N unsigned char emb$b_bc_os_id; /* LOGGING OS ID z */N unsigned char emb$b_bc_hdrsz; /* HEADER SIZE */N unsigned short int emb$w_bc_entry; /*ENTRY TYPE */N unsigned __int64 emb$q_bc_time; /*TIME IN 64 BITS */N unsigned short int emb$w_bc_errseq; /*ERROR SEQUENCE NUMBER */N unsigned __int64 emb$q_bc_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_bc_errmsk; /* ERROR MASK */N unsigned int{ emb$l_bc_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_bc_hw_name_len; /* Length of marketing name of this system */N char emb$t_bc_hw_name [31]; /* marketing name of this system */N unsigned __int64 emb$q_bc_ksp; /*KERNEL STACK POINTER */N unsigned __int64 emb$q_bc_esp; /*EXECUTIVE STACK POINTER */N unsigned __int64 emb$q_bc_ssp; /*SUPERVISOR STACK POINTER */N unsigned __int64 emb$q_bc_usp;| /*USER STACK POINTER */N unsigned __int64 emb$q_bc_r0; /*REGISTER R0 */N unsigned __int64 emb$q_bc_r1; /*REGISTER R1 */N unsigned __int64 emb$q_bc_r2; /*REGISTER R2 */N unsigned __int64 emb$q_bc_r3; /*REGISTER R3 */N unsigned __int64 emb$q_bc_r4; /*REGISTER R4 */N unsigned __int64 emb$q_bc_r5; /*REGISTER R5 } */N unsigned __int64 emb$q_bc_r6; /*REGISTER R6 */N unsigned __int64 emb$q_bc_r7; /*REGISTER R7 */N unsigned __int64 emb$q_bc_r8; /*REGISTER R8 */N unsigned __int64 emb$q_bc_r9; /*REGISTER R9 */N unsigned __int64 emb$q_bc_r10; /*REGISTER R10 */N unsigned __int64 emb$q_bc_r11; /*REGISTER R11 */N un~signed __int64 emb$q_bc_r12; /*REGISTER R12 */N unsigned __int64 emb$q_bc_r13; /*REGISTER R13 */N unsigned __int64 emb$q_bc_r14; /*REGISTER R14 */N unsigned __int64 emb$q_bc_r15; /*REGISTER R15 */N unsigned __int64 emb$q_bc_r16; /*REGISTER R16 */N unsigned __int64 emb$q_bc_r17; /*REGISTER R17 */N unsigned __int64 emb$q_bc_r18; /*REGISTER R18 */N unsigned __int64 emb$q_bc_r19; /*REGISTER R19 */N unsigned __int64 emb$q_bc_r20; /*REGISTER R20 */N unsigned __int64 emb$q_bc_r21; /*REGISTER R21 */N unsigned __int64 emb$q_bc_r22; /*REGISTER R22 */N unsigned __int64 emb$q_bc_r23; /*REGISTER R23 */N unsigned __int64 emb$q_bc_r24; /*REGISTER R24  */N unsigned __int64 emb$q_bc_r25; /*REGISTER R25 */N unsigned __int64 emb$q_bc_r26; /*REGISTER R26 */N unsigned __int64 emb$q_bc_r27; /*REGISTER R27 */N unsigned __int64 emb$q_bc_r28; /*REGISTER R28 */N unsigned __int64 emb$q_bc_fp; /*FRAME POINTER */N unsigned __int64 emb$q_bc_sp; /*CURRENT STACK POINTER */N unsigned __int64 emb$q_bc_pc; /*PROGRAM COUNTER */N unsigned __int64 emb$q_bc_psl; /*PROCESSOR STATUS */N unsigned int emb$l_bc_code; /*BUGCHECK CODE */N unsigned int emb$l_bc_pid; /*CURRENT PROCESS ID */N char emb$t_bc_lname [16]; /*CURRENT PROCESS NAME */ } EMBBC; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBBCDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************** *********************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */I/* Source: 08-AUG-2003 10:53:48 $1$DGA8345:[LIB_H.SRC]EMBCEHDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBCEHDEF ***/#ifndef __EMBCEHDEF_LOADED#define __EMBCEHDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* Define some constants that are useful. */N/* Major HDR REVISIONS */N#define EMB$K_HD_REV_V2 2 /* First rev of new header  */N/* Major HDR REVISIONS */#define EMB$C_HD_REV_V2 2N/* Minor HDR REVISIONS */N#define EMB$K_HD_MINOR_REV_V1 1 /* First minor rev of new header */#define EMB$K_OS_ALPHA_VMS 2N/* Hardware type */#define EMB$K_HW_PDP11 1#define EMB$K_HW_VAX 2#define EMB$K_HW_MIPS 3#define EMB$K_HW_ALPHA 4#define EMB$K_HW_X86 5#define EMB$K_HW_IA64 6#define EMB$K_EMB_IDENT -2#define EMB$K_TLV_UNNAMED 1#define EMB$K_TLV_UNUSED 33#define EMB$K_TLV_TIME 65#define EMB$K_TLV_DSR 97#define EMB$K_TLV_OSV 129#define EMB$K_TLV_OSB 161#define EMB$K_TLV_SSN 193#define EMB$K_TLV_DDR 225#define EMB$K_TLV_PATCH 257#define EMB$K_TLV_SCSNAME 289#define EMB$K_TLV_RBS 321#define EMB$K_TLV_DEV_SN 1025"#define EMB$K_TLV_DEV_PROD_ID 1057##define EMB$K_TLV_DEV_PROD_REV 1089 #define EMB$K_TLV_SC SI_CHAN 1121S#define EMB$K_CEH_LENGTH 284 /*LENGTH OF PART COMMON TO ALL MESSAGES */S#define EMB$C_CEH_LENGTH 284 /*LENGTH OF PART COMMON TO ALL MESSAGES */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _embceh {N/* */N/*  */N/* */#pragma __nomember_alignmentN int emb$l_ceh_ident; /* New header ident */N int emb$l_ceh_header_length; /* distance to event */N/* body */N int emb$l_ceh_event_length; /* total length of record */N unsigned short int emb$w_ceh_hdr_rev; /* Major header rev */N unsigned short int emb$w_ceh_hdr_minor; /* Minor header rev */N unsigned short int emb$w_ceh_os_id; /* Id of OS */N unsigned short int emb$w_ceh_hw_arch; /* Hardware architecture */N unsigned int emb$l_ceh_vendor; /* Hardware vendor */N unsigned int emb$l_ceh_systype; /* SYSTEM TYPE REGISTER */N unsigned int emb$l_ceh_systype_h; /* */N unsigned int emb$l_ceh_log_cpu; /* ID of reporting CPU */N unsigned int emb$l_ceh_total_cpus; /* total Active CPUS */N unsigned short int emb$w_ceh_entry; /* ERROR MESSAGE ENTRY TYPE */N unsigned short int emb$w_ceh_devcls; /* Device class */N unsigned int emb$l_ceh_smm; /* SMM number */N unsigned short int emb$w_ceh_devtyp; /* Device type  */N unsigned short int emb$w_ceh_flags; /* MISC. FLAGS */N unsigned int emb$l_ceh_errmsk; /* ERROR MASK */N unsigned int emb$l_ceh_abstim; /* LOGGED CONTENTS OF EXE$GL_ABSTIM */N unsigned int emb$l_ceh_cpuid; /* UNIQUE CPU ID */N unsigned int emb$l_ceh_deviceid0; /* Used by unix */N unsigned int emb$l_ceh_deviceid1; /* Used by unix */N unsigned i nt emb$l_ceh_deviceid2; /* Used by unix */ __union {N unsigned int emb$l_ceh_group; /* Use sequence number */ __struct {R unsigned short int emb$w_ceh_errseq; /* ERROR SEQUENCE FOR MESSAGE */N unsigned short int emb$w_ceh_uuid; /* Universal Unique ID */# } emb$r_ceh_grp_fields; } emb$r_ceh_group_id;N int emb$l_ceh_event_body_length; /* exact length of the event body */N char emb$t_ceh_reserved [36]; /* reserved for expansion */N unsigned int emb$l_ceh_num_tlv; /* Number of TLV strings. */N unsigned short int emb$w_ceh_dsr_tag; /* String type of DSR */N unsigned short int emb$w_ceh_dsr_length; /* String length of DSR */N char emb$t_ceh_dsr_string [32]; /* marketing name of this system */N unsigned short int emb$w_ceh_ddr_tag; /* String type of ddr string */W unsigned short int emb$w_ceh_ddr_length; /* String length of dynamic device name */O char emb$t_ceh_ddr_string [32]; /* Dynamic device recognition string */S unsigned short int emb$w_ceh_ssn_tag; /* String type of system serial number */X unsigned short int emb$w_ceh_ssn_length; /* String length of system serial number */N char emb$t_ceh_ssn_string [20]; /* System serial number */N unsigned short int emb$w_ceh_time_tag; /* String type time */N unsigned short int emb$w_ceh_time_length; /* String length of time */N char emb$t_ceh_time_string [24]; /* time */N unsigned short int emb$w_ceh_osv_tag; /* String type of os version */O unsigned short int emb$w_ceh_osv_length; /* String length of os version */N unsigned __int64 emb$q_ceh_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_ceh_swvers_fill; /* For nulls. */N unsigned short int emb$w_ceh_scs_tag; /* Computer na me */R unsigned short int emb$w_ceh_scs_length; /* String length of computer name */N char emb$t_ceh_scs_name [16]; /* SCS Node name ASCIC */ } EMBCEH; #if !defined(__VAXC):#define emb$l_ceh_group emb$r_ceh_group_id.emb$l_ceh_groupQ#define emb$w_ceh_errseq emb$r_ceh_group_id.emb$r_ceh_grp_fields.emb$w_ceh_errseqM#define emb$w_ceh_uuid emb$r_ceh_group_id.emb$r_ceh_grp_fields.emb$w_ceh_uuid"#endif /* #if !defined(__VAXC) */ N#define EMB$K_TRAIL_LENGTH 8 /*LENGTH OF TRAILER */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif typedef struct _trailer_fields {#pragma __nomember_alignment int emb$l_trailing_length; int emb$l_event_trailer; } TRAILER_FIELDS; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBCEHDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************* *************************************************************************/=/* Created: 7-Oct-2024 15:23:30 by OpenVMS SDL V3.7 */H/* Source: 27-AUG-1993 10:48:31 $1$DGA8345:[LIB_H.SRC]EMBCRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBCRDEF ***/#ifndef __EMBCRDEF_LOADED#define __EMBCRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/* */N/* CRASH-RESTART ERROR MESSAGE BUFFER FORMAT */N/*  */#define EMB$K_CR_LENGTH 480#define EMB$C_CR_LENGTH 480 typedef struct _embcrbuf {N unsigned int emb$l_cr_sid; /*SYSTEM ID */N unsigned short int emb$w_cr_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_cr_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_cr_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_cr_dev_class; /* DEVICE CLASS */N unsigned char emb$b_cr_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_cr_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_cr_flags; /* MISC. FLAGS */N unsigned char emb$b_cr_os_id; /* LOGGING OS ID */N unsigned char emb$b_cr_hdrsz; /* HEADER SIZE */N unsigned short int emb$w_cr_entry; /*ENTRY TYPE */N unsigned __int64 emb$q_cr_time; /*TIME IN 64 BITS */N unsigned short int emb$w_cr_errseq; /*ERROR SEQUENCE NUMBER */N unsigned __int64 emb$q_cr_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_cr_errmsk; /* ERROR MASK */N unsigned int emb$l_cr_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_cr_hw_name_len; /* Length of marketing name of this system */N char emb$t_cr_hw_name [31]; /* marketing name of this system */N unsigned __int64 emb$q_cr_ksp; /*KERNEL STACK POINTER */N unsigned __int64 emb$q_cr_esp; /*EXECUTIVE STACK POINTER */N unsigned __int64 emb$q_cr_ssp; /*SUPERVISOR STACK POINTER */N unsigned __int64 emb$q_cr_usp; /*USER STACK POINTER */N unsigned __int64 emb$q_cr_r0; /*REGISTER R0 */N unsigned __int64 emb$q_cr_r1; /*REGISTER R1 */N unsigned __int64 emb$q_cr_r2; /*REGISTER R2 */N unsigned __int64 emb$q_cr_r3; /*REGISTER R3 */N unsigned __int64 emb$q_cr_r4; /*REGISTER R4 */N unsigned __int64 emb$q_cr_r5; /*REGISTER R5 */N unsigned __int64 emb$q_cr_r6; /*REGISTER R6 */N unsigned __int64 emb$q_cr_r7; /*REGISTER R7  */N unsigned __int64 emb$q_cr_r8; /*REGISTER R8 */N unsigned __int64 emb$q_cr_r9; /*REGISTER R9 */N unsigned __int64 emb$q_cr_r10; /*REGISTER R10 */N unsigned __int64 emb$q_cr_r11; /*REGISTER R11 */N unsigned __int64 emb$q_cr_r12; /*REGISTER R12 */N unsigned __int64 emb$q_cr_r13; /*REGISTER R13 */N unsigned __int64 emb$q_cr_r14; /*REGISTER R14 */N unsigned __int64 emb$q_cr_r15; /*REGISTER R15 */N unsigned __int64 emb$q_cr_r16; /*REGISTER R16 */N unsigned __int64 emb$q_cr_r17; /*REGISTER R17 */N unsigned __int64 emb$q_cr_r18; /*REGISTER R18 */N unsigned __int64 emb$q_cr_r19; /*REGISTER R19 */N unsigned __int64 emb$q_cr_r20; /*REGISTER R20 */N unsigned __int64 emb$q_cr_r21; /*REGISTER R21 */N unsigned __int64 emb$q_cr_r22; /*REGISTER R22 */N unsigned __int64 emb$q_cr_r23; /*REGISTER R23 */N unsigned __int64 emb$q_cr_r24; /*REGISTER R24 */N unsigned __int64 emb$q_cr_r25; /*REGISTER R25 */N unsigned __int64 emb$q_cr_r26; /*REGISTER R26  */N unsigned __int64 emb$q_cr_r27; /*REGISTER R27 */N unsigned __int64 emb$q_cr_r28; /*REGISTER R28 */N unsigned __int64 emb$q_cr_fp; /*FRAME POINTER */N unsigned __int64 emb$q_cr_sp; /*CURRENT STACK POINTER */N unsigned __int64 emb$q_cr_pc; /*PROGRAM COUNTER */N unsigned __int64 emb$q_cr_psl; /*PROCESSOR STATUS */N unsigned __int64 emb$q_cr_ptbr; /*PAGE TABLE BASE REGISTER */N unsigned __int64 emb$q_cr_pcbb; /*PRIVILEGED CONTEXT BLOCK BASE */N unsigned __int64 emb$q_cr_prbr; /*PROCESSOR BASE REGISTER */N unsigned __int64 emb$q_cr_vptb; /*VIRTUAL PAGE TABLE BASE REGISTER */N unsigned __int64 emb$q_cr_scbb; /*SYSTEM CONTROL BLOCK BASE */N unsigned __int64 emb$q_cr_sisr; /*SOFTWARE INTERRUPT SUMMARY REG */N unsigned __int64 emb$q_cr_asn; /*ADDRESS SPACE NUMBER */N unsigned __int64 emb$q_cr_astsr_asten; /*AST SUMMARY AND ENABLE REGS */N unsigned __int64 emb$q_cr_fen; /*FLOATING ENABLE */N unsigned __int64 emb$q_cr_ipl; /*INTERRUPT PRIORITY LEVEL */N unsigned __int64 emb$q_cr_mces; /*MACHINE CHECK ERROR SUMMARY REG */N/* Remember start of CPU-dependent info */ } EMBCRBUF;N#define EMB$S_EMBCRDEF 484 /* Old size name - synonym */ typedef struct _embcr { EMBCRBUF emb$r_embcr;N unsigned int emb$l_cr_cpureg; /*START OF CPU-SPECIFIC IPR'S */ } EMBCR;N/* CPU-specific registers for the 11/780: */#define EMB$K_CR1_LENGTH 576#define EMB$C_CR1_LENGTH 576N#define EMB$S_EMBCRDEF1 576 /* Old size name - synonym */ typedef struct _embcr1 { EMBCRBUF emb$r_embcr;N unsigned int emb$l_cr_icr; /*INTERVAL COUNT REGISTER */N unsigned int emb$l_cr_todr; /*TIME OF DAY REGISTER */N unsigned int emb$l_cr_accs; /*ACCELERATOR CONTROL REGISTER */N unsigned int emb$l_cr_sbifs; /* SBI FAULT STATUS */N unsigned int emb$l_cr_sbisc; /* SBI COMPARATOR REGISTER */N unsigned int emb$l_cr_sbimt; /* SBI MAINT REGISTER */N unsigned int emb$l_cr_sbier; /* SBI ERROR REGISTER  */N void *emb$l_cr_sbita; /* SBI TIMEOUT ADDR REGISTER */N unsigned int emb$l_cr_sbis [16]; /* SBI SILO */ } EMBCR1;N/* CPU-specific registers for the 11/750: */#define EMB$K_CR2_LENGTH 512#define EMB$C_CR2_LENGTH 512N#define EMB$S_EMBCRDEF2 512 /* Old size name - synonym */ typedef struct _embcr2 { EMBCRBUF emb$r_embcr;h char embcr$$_fill_4 [12]; /*Allow room for ICR,TODR,ACCS without causing name conflicts */N unsigned int emb$l_cr_tbdr; /* TB DISABLE REGISTER */N unsigned int emb$l_cr_cadr; /* CACHE DISABLE REGISTER */N unsigned int emb$l_cr_mcesr; /* MACHINE CHECK ERROR SUMMARY */N unsigned int emb$l_cr_caer; /* CACHE ERROR REGISTER */N unsigned int emb$l_cr_cmierr; /* CMI ERROR SUMMARY REGISTER */N/* 16 UNUSED LONGWDS IN EMB  */ } EMBCR2;T#define EMB$K_CR3_LENGTH 600 /*SIZE OF FIXED PART OF BUGCHECK MESSAGE */T#define EMB$C_CR3_LENGTH 600 /*SIZE OF FIXED PART OF BUGCHECK MESSAGE */N#define EMB$S_EMBCRDEF3 600 /* Old size name - synonym */ typedef struct _embcr3 { __union {N char emb$b_fill_3_1 [576]; /* MAKE THIS AFTER ALL OF THE IPRS */" char emb$b_fill_3_2 [512]; } emb$r_fill_3;N unsigned  int emb$l_cr_code; /*BUGCHECK/CRASH CODE */N unsigned int emb$l_cr_pid; /*CURRENT PROCESS ID */N char emb$t_cr_lname [16]; /*CURRENT PROCESS NAME */ } EMBCR3; #if !defined(__VAXC)"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBCRDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:2 3:31 by OpenVMS SDL V3.7 */H/* Source: 15-OCT-1993 09:56:28 $1$DGA8345:[LIB_H.SRC]EMBDVDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBDVDEF ***/#ifndef __EMBDVDEF_LOADED#define __EMBDVDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* DEVICE ERROR MESSAGE BUFFER FORMAT (ERROR AND TIMEOUT) */N/* */ #include #define EMB$K_DV_LENGTH 222#define EMB$C_DV_LENGTH 222N#def ine EMB$S_EMBDVDEF 222 /*Old size name - synonym */ typedef struct _embdv {N unsigned int emb$l_dv_sid; /*SYSTEM ID */N unsigned short int emb$w_dv_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_dv_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_dv_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_dv_dev_class; /* DEVICE CLASS */N unsigned char emb$b_dv_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_dv_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_dv_flags; /* MISC. FLAGS */N unsigned char emb$b_dv_os_id; /* LOGGING OS ID */N unsigned char emb$b_dv_hdrsz; /* HEADER SIZE */N unsigned short int emb$w_dv_entry; /*ENTRY TYPE (1=ERROR, 96=TIMEOUT) */N unsigned __int64 emb$q_dv_time; /*TIME OF ERROR */N unsigned short int emb$w_dv_errseq; /*ERROR SEQUENCE NUMBER */N unsigned __int64 emb$q_dv_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_dv_errmsk; /* ERROR MASK */N unsigned int emb$l_dv_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_dv_hw_name_len; /* Length of marketing name of this system */N char emb$t_dv_hw_name [31]; /* marketing name of this system */O unsigned int emb$l_dv_ertcnt; /*REMAINING NUMBER OF ERROR RETRIES */N unsigned int emb$l_dv_ertmax; /*MAXIMUM NUMBER OF ERROR RETRIES */N unsigned __int64 emb$q_dv_iosb; /*FINAL I/O STATUS */N unsigned int emb$l_dv_sts; /*FINAL DEVICE STATUS */N unsigned char emb$b_dv_class; /*DEVICE CLASS */N unsigned char emb$b_dv_type; /*DEVICE TYPE  */N unsigned int emb$l_dv_rqpid; /*REQUESTER PROCESS ID */N unsigned int emb$l_dv_boff; /*BYTE OFFSET IN PAGE */N unsigned int emb$l_dv_bcnt; /*TRANSFER BYTE COUNT */N void *emb$l_dv_media; /*STARTING MEDIA ADDRESS */N unsigned short int emb$w_dv_unit; /*PHYSICAL UNIT NUMBER */N unsigned int emb$l_dv_errcnt; /*UNIT ERROR COUNT */N unsigned int emb$l_dv_opcnt; /*UNIT OPERATION COUNT */N unsigned int emb$l_dv_ownuic; /*VOLUME OWNER UIC */N unsigned int emb$l_dv_char; /*DEVICE CHARACTERISTICS */N unsigned char emb$b_dv_slave; /*SLAVE CONTROLLER NUMBER */N char embdv$$_fill_1; /*SPARE UNUSED BYTES */N unsigned int emb$l_dv_func; /*I/O FUNCTION VALUE */N char emb$t_dv_name [32]; /*DEVICE NAME */N char emb$t_dv_dtname [28]; /*Device type name */N/*counted string */N void *emb$l_dv_regsav; /*START OF REGISTER SAVE AREA */ } EMBDV; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBDVDEF_LOADED */ ww0[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without  **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */H/* Source: 30-MAY-2017 13:10:42 $1$DGA8345:[LIB_H.SRC]EMBETDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBETDEF ***/#ifndef __EMBETDEF_LOADED#define __EMBETDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* ERROR MESSAGE ENTRY TYPE DEFINITIONS */N/* */G#define EMB$C_DE 1 /* I/A/V Device Error */G#define EMB$K_DE 1  /* I/A/V Device Error */T#define EMB$C_MC 2 /* A/V Machine Check 670 - Processor UCE */T#define EMB$K_MC 2 /* A/V Machine Check 670 - Processor UCE */R#define EMB$C_MCHECK_670 2 /* A Machine Check 670 - Processor UCE */R#define EMB$K_MCHECK_670 2 /* A Machine Check 670 - Processor UCE */N/* Temporary for xbuild, needs x86 review - Clair Grant */P#define EMB$C_MCA_CPU 2 /* I Machine Check Abort - Processor */P#define EMB$K_MCA_CPU 2 /* I Machine Check Abort - Processor */D#define EMB$C_SYNERR 3 /* V Syndrome Error */D#define EMB$K_SYNERR 3 /* V Syndrome Error */D#define EMB$C_BE 4 /* V Bus Error */D#define EMB$K_BE 4 /* V Bus Error */D#define EMB$C_SA 5 /* V SBI Alert */D#define EMB$K_SA 5  /* V SBI Alert */F#define EMB$C_SE 6 /* A/V Soft ECC Error */F#define EMB$K_SE 6 /* A/V Soft ECC Error */N#define EMB$C_MCHECK_620 6 /* A Machine Check 620 - System CE */N#define EMB$K_MCHECK_620 6 /* A Machine Check 620 - System CE */N/* Temporary for xbuild, needs x86 review - Clair Grant */I#define EMB$C_CPE 6 /* I Corrected Platform Error */I#define EMB$K_CPE 6 /* I Corrected Platform Error */I#define EMB$C_AW 7 /* V Asynchronous Write Error */I#define EMB$K_AW 7 /* V Asynchronous Write Error */F#define EMB$C_HE 8 /* A/V Hard ECC Error */F#define EMB$K_HE 8 /* A/V Hard ECC Error */L#define EMB$C_UBA 9 /* V 11/780 Unibus Adapter Error */L#define EMB$K_UBA 9 /* V 11/780 Unibus Adapter Error */P#define EMB$C_SI 10 /* V 11/750 Fault through SBI Vector */P#define EMB$K_SI 10 /* V 11/750 Fault through SBI Vector */D#define EMB$C_UE 11 /* V 11/730 Unibus Error */D#define EMB$K_UE 11 /* V 11/730 Unibus Error */M#define EMB$C_MBA 12 /* V 11/780 Massbus Adapter Error */M#define EMB$K_MBA 12 /* V 11/780 Massbus Adapter Error */D#define EMB$C_SBIA 13  /* V 11/790 SBIA Error */D#define EMB$K_SBIA 13 /* V 11/790 SBIA Error */F#define EMB$C_CRD 14 /* A/V 11/790 CRD Log */F#define EMB$K_CRD 14 /* A/V 11/790 CRD Log */M#define EMB$C_EMM 15 /* V 11/790 Environmental Monitor */M#define EMB$K_EMM 15 /* V 11/790 Environmental Monitor */N#define EMB$C_HLT 16 /* A/V 11/790 Processor Error Halt */N#define EMB$K_HLT 16 /* A/V 11/790 Processor Error Halt */F#define EMB$C_CRBT 17 /* V 11/790 Console Reboot */F#define EMB$K_CRBT 17 /* V 11/790 Console Reboot */D#define EMB$C_BIADPERR 18 /* V BI Adapter Error */D#define EMB$K_BIADPERR 18 /* V BI Adapter Error */D#define EMB$C_BIBUSERR 19 /* V BI Bus Error */D#define EMB$K_BIBUSERR 19 /* V BI Bus Error */D#define EMB$C_NMIFLT 20 /* V NMI Fault */D#define EMB$K_NMIFLT 20 /* V NMI Fault */D#define EMB$C_CTO 21 /* V Console Timeout */D#define EMB$K_CTO 21 /* V Console Timeout */D#define EMB$C_NBW 22 /* V NBW */D#define EMB$K_NBW 22 /* V NBW */F#define EMB$C_CACHERR 23 /* A/V Cache Error */F#define EMB$K_CACHERR 23  /* A/V Cache Error */E#define EMB$C_CVAX_CB 24 /* V CVAX Cache/Bus Error */E#define EMB$K_CVAX_CB 24 /* V CVAX Cache/Bus Error */Q#define EMB$C_MEMSCAN 25 /* V Calypso Memory Error by scanning */Q#define EMB$K_MEMSCAN 25 /* V Calypso Memory Error by scanning */G#define EMB$C_INT54 26 /* A/V Calypso SCB 54 Error */G#define EMB$K_INT54 26 /* A/V Calypso SCB 54 Error */Q#define EMB$C_MCHECK_630 26 /* A Machine Check 630 - Processor CE */Q#define EMB$K_MCHECK_630 26 /* A Machine Check 630 - Processor CE */N/* Temporary for xbuild, needs x86 review - Clair Grant */H#define EMB$C_CMC 26 /* I Corrected Machine Check */H#define EMB$K_CMC 26 /* I Corrected Machine Check */G#define EMB$C_INT60 27 /* A/V Calypso SCB 60 Error */G#define EMB$K_INT60 27 /* A/V Calypso SCB 60 Error */O#define EMB$C_MCHECK_660 27 /* A Machine Check 660 - System UCE */O#define EMB$K_MCHECK_660 27 /* A Machine Check 660 - System UCE */N/* Temporary for xbuild, needs x86 review - Clair Grant */O#define EMB$C_MCA_SYS 27 /* I Machine Check Abort - Platform */O#define EMB$K_MCA_SYS 27 /* I Machine Check Abort - Platform */F#define EMB$C_ADPERR 28 /* A/V Adapter Error  */F#define EMB$K_ADPERR 28 /* A/V Adapter Error */D#define EMB$C_LASTFAIL 29 /* V Calypso Lastfail */D#define EMB$K_LASTFAIL 29 /* V Calypso Lastfail */D#define EMB$C_CONSOLE 30 /* V Console Entry */D#define EMB$K_CONSOLE 30 /* V Console Entry */F#define EMB$C_INFO 31 /* V Informational Message */F#define EMB$K_INFO 31 /* V Informational Message */G#define EMB$C_CS 32 /* I/A/V Cold Start */G#define EMB$K_CS 32 /* I/A/V Cold Start */D#define EMB$C_CLKERR 33 /* V Clock Module Error */D#define EMB$K_CLKERR 33 /* V Clock Module Error */D#define EMB$C_SCAN 34 /* V Scan Error */D#define EMB$K_SCAN 34 /* V Scan Error */G#define EMB$K_NF 35 /* I/A/V New File Created */G#define EMB$C_NF 35 /* I/A/V New File Created */G#define EMB$C_WS 36 /* I/A/V Warm Start */G#define EMB$K_WS 36 /* I/A/V Warm Start */G#define EMB$C_CR 37 /* I/A/V Crash Restart */G#define EMB$K_CR 37 /* I/A/V Crash Restart */G#define EMB$C_TS 38 /* I/A/V Time Stamp */G#define EMB$K_TS 38 /* I/A/V Time Stamp */J#define EMB$C_SS 39 /* I/A/V System Service Message */J#define EMB$K_SS 39 /* I/A/V System Service Message */G#define EMB$C_SBC 40 /* I/A/V System Bugcheck */G#define EMB$K_SBC 40 /* I/A/V System Bugcheck */G#define EMB$C_OM 41 /* I/A/V Operator Message */G#define EMB$K_OM 41 /* I/A/V Operator Message */G#define EMB$C_NM 42 /* I/A/V Network Message */G#define EMB$K_NM 42 /* I/A/V Network Message */E#define EMB$C_CONFIG 43 /* A System Configuration */E#define EMB$K_CONFIG 43 /* A System Configuration */D#define EMB$C_POLL_ERR 44 /* V Polled Error */D#define EMB$K_POLL_ERR 44 /* V Polled Error */G#define EMB$C_VM 64 /* I/A/V Volume Mount */G#define EMB$K_VM 64 /* I/A/V Volume Mount */G#define EMB$C_VD 65 /* I/A/V Volume Dismount */G#define EMB$K_VD 65 /* I/A/V Volume Dismount */G#define EMB$C_DT 96 /* I/A/V Device Timeout */G#define EMB$K_DT 96 /* I/A/V Device Timeout */D#define EMB$C_UI 97 /* V Undefined Interrupt */E#define EMB$K_UI 97 /* V Undefined Interrupt */Q#define EMB$C_DA 98 /* I/A/V Asynchronous Device Attention */Q#define EMB$K_DA 98 /* I/A/V Asynchronous Device Attention */G#define EMB$C_SP 99 /* I/A/V Software Parameters */G#define EMB$K_SP 99 /* I/A/V Software Parameters */G#define EMB$C_LM 100 /* I/A/V Logged Message */G#define EMB$K_LM 100 /* I/A/V Logged Message */G#define EMB$C_LOGMSCP 101 /* I/A/V Logged MSCP Message */G#define EMB$K_LOGMSCP 101 /* I/A/V Logged MSCP Message */D#define EMB$C_PWR 102 /* A Laser Power Event */D#define EMB$K_PWR 102 /* A Laser Power Event */G#define EMB$C_UBC 112 /* I/A/V User Bugcheck */G#define EMB$K_UBC 112 /* I/A/V User Bugcheck */F#define EMB$C_HALT_FRAME 113 /* I/A Console Data Log */F#define EMB$K_HALT_FRAME 113 /* I/A Console Data Log */N/* Temporary for xbuild, needs x86 review - Clair Grant */D#define EMB$C_INIT 114 /* I Processor INIT */D#define EMB$K_INIT 114 /* I Processor INIT */Q#define EMB$C_MCHECK_680 115 /* A Machine Check 680 - System Event */Q#define EMB$K_MCHECK_680 115 /* A Machine Check 680 - System Event */L#define EMB$C_MCHECK_RUE 116 /* A Machine Check 6A0/6B0 - RUE */L#define EMB$K_MCHECK_RUE 116 /* A Machine Check 6A0/6B0 - RUE */M#define EMB$C_THROTTLE_CRD 120 /* I/A CE Throttling Notification */M#define EMB$K_THROTTLE_CRD 120 /* I/A CE Throttling Notification */F#define EMB$C_INDICT 124 /* I/A Indictment Event */F#define EMB$K_INDICT 124 /* I/A Indictment Event */D#define EMB$C_SEL 126 /* I System Event Log */D#define EMB$K_SEL 126 /* I System Event Log */W/* The following are minor class (DEVCLS) codes for the MCHECK_680 major class code. */N#define EMB$C_MCHECK_680_CORRECTABLE 6 /* Correctable */N#define EMB$K_MCHECK_680_CORRECTABLE 6 /* Correctable */N#define EMB$C_MCHECK_680_UNCORRECTABLE 2 /* Uncorrectable */N#define EMB$K_MCHECK_680_UNCORRECTABLE 2 /* Uncorrectable */W/* The following are minor class (DEVCLS) codes for the MCHECK_RUE major class code. */N#define EMB$C_MCHECK_RUE_6A0 1 /* System */N#define EMB$K_MCHECK_RUE_6A0 1 /* System */N#define EMB$C_MCHECK_RUE_6B0 2 /* Processor */N#define EMB$K_MCHECK_RUE_6B0 2 /* Processor */S/* The following are minor class (DEVCLS) codes for the CONFIG major class code. */F#define EMB$C_CONFIG_ORIG 0 /* A/V Original FRU config */F#define EMB$K_CONFIG_ORIG 0 /* A/V Original FRU config */F#define EMB$C_CONFIG_SDR_FRU 1 /* I SDR FRU eeprom config */F#define EMB$K_CONFIG_SDR_FRU 1 /* I SDR FRU eeprom config */D#define EMB$C_CONFIG_PCI 2 /* I PCI config */D#define EMB$K_CONFIG_PCI 2 /* I PCI config */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBETDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:30 by OpenVMS SDL V3.7  */H/* Source: 29-JUL-2004 17:27:37 $1$DGA8345:[LIB_H.SRC]EMBHDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBHDDEF ***/#ifndef __EMBHDDEF_LOADED#define __EMBHDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* ERROR MESSAGE BUFFER HEADER */N/* */N/* Header revisions */#define EMB$K_HD_REV_V50 2#define EMB$K_HD_REV_V51 3#define EMB$K_HD_REV_HICKORY 4#define EMB$K_HD_REV_V10 5#define EMB$K_HD_REV_V20 6#define EMB$K_HD_REV_V30 7N/* Header revisions */#define EMB$C_HD_REV_V50 2#define EMB$C_HD_REV_V51 3#define EMB$C_HD_REV_HICKORY 4#define EMB$C_HD_REV_V10 5#define EMB$C_HD_REV_V20 6#define EMB$C_HD_REV_V30 7N/* OS ID's */#define EMB$C_OS_RESERVED 0#define EMB$ C_OS_VAXVMS 1#define EMB$C_OS_VAXELN 2#define EMB$C_OS_ALPHAVMS 3N/* OS ID's */#define EMB$K_OS_RESERVED 0#define EMB$K_OS_VAXVMS 1#define EMB$K_OS_VAXELN 2#define EMB$K_OS_ALPHAVMS 3N/* This determines the SCS node name buffer size */^typedef char SCS_NAME_LEN [16]; /* Define type so other EMBxxxDEF files can use it. */N#define EMB$C_SCS_NAME_LENGTH 16 /* Buffer size for S CS name */N#define EMB$K_SCS_NAME_LENGTH 16 /* Buffer size for SCS name */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _embhd_nonfixed {N/* */N/* Starting with HD_SID, this aggregate is common to all EMBxxxDEF modules, */P/* so a change here requires a corresponding change to those modules, as well */N/* as an increase to the header revision. */N/* */#pragma __nomember_alignmentN unsigned int emb$l_hd_sid; /* System ID */R unsigned short int emb$w_hd_hdr_rev; /* Header revision (in 1's complement) */N __union { /* Unique CPU type */N unsigned int emb$l_hd_systype; /* System type register */ __struct {X unsigned short int emb$w_hd_xsid_rsv; /* Reserved for type-dependent info */N unsigned char emb$b_hd_xsid_rev; /* Revision level of CPU */N unsigned char emb$b_hd_xsid_typ; /* Sys type, CPU type */# } emb$r_hd_xsid_fields; } emb$r_hd_xsid;N unsigned int emb$l_cpuid; /* Unique CPU ID */N unsigned char emb$b_dev_class; /* Device class */N unsigned char emb$b_dev_type; /* Device type */N SCS_NAME_LEN emb$t_scs_name; /* SCS node name ASCIC */N unsigned short int emb$w_flags; /* Misc. flags */N unsigned char emb$b_os_id; /* Logging OS ID */N unsigned char emb$b_hdrsz; /* Size of this header */ __union {N unsigned short int e mb$w_hd_entry; /* Entry type */ __struct {N unsigned char emb$b_devtyp; /* Device type */N unsigned char emb$b_devcls; /* Device class */$ } emb$r_hd_entry_fields;! } emb$r_hd_entry_overlay;N unsigned __int64 emb$q_hd_time; /* Time of entry */N unsigned short int emb$w_hd_errseq; /* Error sequence number */N unsigned __int64 emb$q_hd_swvers;  /* Software version */N unsigned int emb$l_hd_errmsk; /* Error mask */N unsigned int emb$l_hd_abstim; /* Contents of exe$gl_abstim */U unsigned char emb$b_hd_hw_name_len; /* Length of marketing name of this system */N char emb$t_hd_hw_name [31]; /* Marketing name of this system */ } EMBHD_NONFIXED; #if !defined(__VAXC)7#define emb$l_hd_systype emb$r_hd_xsid.emb$l_hd_systypeN#define emb$w_hd_xsid_rsv em b$r_hd_xsid.emb$r_hd_xsid_fields.emb$w_hd_xsid_rsvN#define emb$b_hd_xsid_rev emb$r_hd_xsid.emb$r_hd_xsid_fields.emb$b_hd_xsid_revN#define emb$b_hd_xsid_typ emb$r_hd_xsid.emb$r_hd_xsid_fields.emb$b_hd_xsid_typ<#define emb$w_hd_entry emb$r_hd_entry_overlay.emb$w_hd_entryN#define emb$b_devtyp emb$r_hd_entry_overlay.emb$r_hd_entry_fields.emb$b_devtypN#define emb$b_devcls emb$r_hd_entry_overlay.emb$r_hd_entry_fields.emb$b_devcls"#endif /* #if !defined(__VAXC) */ ]#define EMB$K_HD_LENGTH 96  /* Length of header that is common to all messages */]#define EMB$C_HD_LENGTH 96 /* Length of header that is common to all messages */U#define EMB$C_LENGTH 16 /* LENGTH OF FIXED PART OF MESSAGE HEADER */U#define EMB$K_LENGTH 16 /* LENGTH OF FIXED PART OF MESSAGE HEADER */N#define EMB$S_EMBHDDEF 112 /* Old size name - synonym */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _embhd {#pragma __nomember_alignment unsigned int emb$l_spare0; __union {_ unsigned int emb$l_size; /* Size of error message in bytes - new style record */ __struct {b unsigned short int emb$w_size; /* Size of error message in bytes - old style record */. unsigned short int emb$w_reserved; } emb$r_size_field s; } emb$r_size_overlay;N unsigned int emb$l_bufind; /* Buffer index */N unsigned char emb$b_valid; /* Error message valid indicator */# unsigned char emb$b_spare1 [3];O EMBHD_NONFIXED emb$r_embhd_nonfixed; /* Non-fixed part of message header */ } EMBHD; #if !defined(__VAXC)0#define emb$l_size emb$r_size_overlay.emb$l_sizeB#define emb$w_size emb$r_size_overlay.emb$r_size_fields.emb$w_size"#endif /* #if !defined(__VAXC) */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _embtrailer {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *emb$q_tr_s2_buf_addr;#else' unsigned __int64 emb$q_tr_s2_buf_addr;#endif int emb$l_tr_spare; int emb$l_tr_actual_size;& unsigned int emb$l_tr_active_cpus;& unsigned int emb$l_tr_logging_cpu;" unsigned __int64 emb$q_tr_tdf; } EMBTRAILER;N#define EMB$C_TR_LENGTH 32 /* Length of EMB trailer */N#define EMB$K_TR_LENGTH 32 /* Length of EMB trailer */#define EMB$M_EM_BUS 0x1#define EMB$M_EM_CPU 0x2#define EMB$M_EM_MEMORY 0x4#define EMB$M_EM_ADAPTER 0x8#define EMB$M_EM _CACHE 0x10#define EMB$M_EM_VECTOR 0x20#define EMB$M_RSRVD1 0x40 typedef union _errmsk_fields { int emb$l_errmsk; __struct {N unsigned emb$v_em_bus : 1; /* Bus error */N unsigned emb$v_em_cpu : 1; /* CPU error */N unsigned emb$v_em_memory : 1; /* Memory error */N unsigned emb$v_em_adapter : 1; /* Adapter error */N unsigned emb$v_em_cache : 1;  /* Cache error */N unsigned emb$v_em_vector : 1; /* Vector error */N unsigned emb$v_rsrvd1 : 1; /* Reserved */" unsigned emb$v_rsrvd : 25; } emb$r_errmsk_bits; } ERRMSK_FIELDS; #if !defined(__VAXC)3#define emb$v_em_bus emb$r_errmsk_bits.emb$v_em_bus3#define emb$v_em_cpu emb$r_errmsk_bits.emb$v_em_cpu9#define emb$v_em_memory emb$r_errmsk_bits.emb$v_em_memory;#define emb$v_em_adapter emb$r_errmsk_bits.emb$v_em_adapter7#define emb$v_em_cache emb$r_errmsk_bits.emb$v_em_cache9#define emb$v_em_vector emb$r_errmsk_bits.emb$v_em_vector3#define emb$v_rsrvd1 emb$r_errmsk_bits.emb$v_rsrvd1"#endif /* #if !defined(__VAXC) */ #define EMB$M_FL_DDR 0x1#define EMB$M_FL_OVWRT 0x2 typedef union _flags_fields { int emb$l_flags; __struct {N unsigned emb$v_fl_ddr : 1; /* DDR packet flag */N unsigned emb$v_fl_ovwrt : 1; /* Overwrite detected */" unsigned emb$v_rsrvd : 14; } emb$r_flags_bits; } FLAGS_FIELDS; #if !defined(__VAXC)2#define emb$v_fl_ddr emb$r_flags_bits.emb$v_fl_ddr6#define emb$v_fl_ovwrt emb$r_flags_bits.emb$v_fl_ovwrt"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBHDDEF_LOADED */ ww`:[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:31 by Op enVMS SDL V3.7 */L/* Source: 23-JUN-2003 16:38:55 $1$DGA8345:[LIB_H.SRC]EMBINDICTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBINDICTDEF ***/#ifndef __EMBINDICTDEF_LOADED#define __EMBINDICTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/* */N/* INDICTMENT BUFFER FORMAT */N/* */N#define EMB$K_INDICT_ISUB_CLASS 9 /* INDICT ISUB class */N#define EMB$C_INDICT_ISUB_CLASS 9 /* INDICT ISUB class */N#define EMB$K_INDICT_ISUB_TYPE 3 /* INDICT ISUB type */N#define EMB$C_INDICT_ISUB_TYPE 3 /* INDICT ISUB type */N#define EMB$K_INDICT_ISUB_REV 1 /* INDICT ISUB revision */N#define EMB$C_INDICT_ISUB_REV 1 /* INDICT ISUB revision */N#define EMB$K_INDICT_ISUB_LENGTH 536 /* INDICT ISUB size */N#define EMB$C_INDICT_ISUB_LENGTH 536 /* INDICT ISUB size */N#define EMB$K_INDICT_TSUB_LENGTH 8 /* INDICT TSUB class */N#define EMB$C_INDICT_TSUB_LENGTH 8 /* INDICT TSUB class */N#define EMB$K_INDICT_TSUB_CLASS 0 /* INDICT TSUB class */N#define EMB$C_INDICT_TSUB_CLASS 0 /* INDICT TSUB class */N#define EMB$K_INDICT_TSUB_TYPE 0 /* INDICT TSUB type */N#define EMB$C_INDICT_TSUB_TYPE  0 /* INDICT TSUB type */N#define EMB$K_INDICT_TSUB_REV 1 /* INDICT TSUB revision */N#define EMB$C_INDICT_TSUB_REV 1 /* INDICT TSUB revision */N#define EMB$K_INDICT_ERL_LENGTH 640 /* INDICT ERL size */N#define EMB$C_INDICT_ERL_LENGTH 640 /* INDICT ERL size */N#define EMB$S_EMBINDICTDEF 640 /* Old size name - synonym */ typedef struct _embindict {N unsigned int emb$l_indt_sid; /*SYSTEM ID */N unsigned short int emb$w_indt_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_indt_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_indt_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_indt_dev_class; /* DEVICE CLASS */N unsigned char emb$b_indt_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_indt_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_indt_flags; /* MISC. FLAGS */N unsigned char emb$b_indt_os_id; /* LOGGING OS ID */N unsigned char emb$b_indt_hdrsz; /* HEADER SIZE */N unsigned short int emb$w_indt_entry; /* ENTRY TYPE */N unsigned __int64 emb$q_indt_time; /*TIME IN 64 BIT FORMAT */N unsigned short int emb$w_indt_errseq; /*ERROR SEQUENCE NUMBER  */N unsigned __int64 emb$q_indt_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_indt_errmsk; /* ERROR MASK */N unsigned int emb$l_indt_abstim; /* CONTENTS OF EXE$GL_ABSTIM */W unsigned char emb$b_indt_hw_name_len; /* Length of marketing name of this system */N char emb$t_indt_hw_name [31]; /* marketing name of this system */N unsigned short int emb$w_indict_isub_len; /* Indictment subpak length */N unsigned short int emb$w_indict_isub_class; /* Indictment subpak class */N unsigned short int emb$w_indict_isub_type; /* Indictment subpak type */N unsigned short int emb$w_indict_isub_rev; /* Indictment subpak rev */N unsigned int emb$l_indict_status; /* Status of this entry */N unsigned int emb$l_indict_object_type; /* Type: Component/PFN/OS */O unsigned __int64 emb$q_indict_pfn_os_handle; /* Failing PFN or OS HWR ID */N unsigned __int64 emb$iq_indict_comp_id; /* Component Handle ID */N unsigned char emb$b_indict_comp_type; /* Component Handle Type */N unsigned char emb$b_indict_comp_subtype; /* Component Handle Subtype */( unsigned char emb$b_indict_pad1 [6];N unsigned __int64 emb$iq_indict_module_id; /* Module Handle ID */N unsigned char emb$b_indict_module_type; /* Module Handle Type */N unsigned char emb$b_indict_module_subtype; /* Module Handle Subtype */( unsigned char emb$b_indict_pad2 [6];N unsigned int emb$l_indict_urgency; /* Urgency of indictment request */N unsigned int emb$l_indict_probability; /* Probability of correct fault */N unsigned int emb$l_total_indictments; /* Total number to be indicted */N unsigned int emb$l_indict_descrip_size; /* Size of descriptor string */N unsigned int emb$l_indict_initiator_size; /* Size of initiator string */N unsigned int emb$l_indict_report_size; /* Size of report handle string */N  char emb$b_indict_description [256]; /* Readable descr. of problem */( unsigned char emb$b_indoct_pad3 [8];N char emb$b_indict_initiator [32]; /* Who called us */( unsigned char emb$b_indict_pad4 [8];N char emb$b_indict_report_handle [128]; /* report handle program name */( unsigned char emb$b_indict_pad5 [8];N unsigned char emb$b_indict_spare [16]; /* future expansion */N unsigned short int emb$w_indict_tsub_len; /* Termination s ubpak length */N unsigned short int emb$w_indict_tsub_class; /* Termination subpak class */N unsigned short int emb$w_indict_tsub_type; /* Termination subpak type */N unsigned short int emb$w_indict_tsub_rev; /* Termination subpak rev */ } EMBINDICT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard "#endif /* __EMBINDICTDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:31 by OpenVMS SDL V3.7  */J/* Source: 27-MAY-1993 10:30:57 $1$DGA8345:[LIB_H.SRC]EMBINFODEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBINFODEF ***/#ifndef __EMBINFODEF_LOADED#define __EMBINFODEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/* */N/* INFORMATIONAL MESSAGE BUFFER FORMAT */N/* */N#define EMB$S_EMBINFODEF 101 /* Old size name - synonym */ ty pedef struct _embinfo {N EMBHD_NONFIXED emb$b_info_hdr; /* */N unsigned int emb$l_info_msg_type; /* Informational msg type */N unsigned char emb$b_info_msg_data; /* Device dependent data */ } EMBINFO; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBINFODEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M /** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:31 by OpenVMS SDL V3.7  */H/* Source: 15-OCT-1993 09:59:11 $1$DGA8345:[LIB_H.SRC]EMBLMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBLMDEF ***/#ifndef __EMBLMDEF_LOADED#define __EMBLMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr siz e pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struc t#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/* */N/* LOGGED MESSAGE (DEVICE DEPENDENT CONTENTS). DRIVER LOGS MESSAGE */N/* WHICH MAY COME DIRECT FROM INTELLIGENT MASS STORAGE CONTROLLER. */N/* */#define EM B$K_LM_LENGTH 162#define EMB$C_LM_LENGTH 162N#define EMB$S_EMBLMDEF 162 /* Old size name - synonym */ typedef struct _emblm {N unsigned int emb$l_lm_sid; /* System ID */N unsigned short int emb$w_lm_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_lm_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_lm_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_lm_dev_class; /* DEVICE CLASS */N unsigned char emb$b_lm_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_lm_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_lm_flags; /* MISC. FLAGS */N unsigned char emb$b_lm_os_id; /* LOGGING OS ID */N unsigned char emb$b_lm_hdrsz; /* HEADER SIZE */O unsigned short int emb$w_lm_entry; /* Entry type (i.e. Logged Message) */N unsigned __int64 emb$q_lm_time; /* Time this entry created */N unsigned short int emb$w_lm_errseq; /* Error sequence number */N unsigned __int64 emb$q_lm_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_lm_errmsk; /* ERROR MASK */N unsigned int emb$l_lm_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_lm_hw_name_len; /* Length of marketing name of this system */N char emb$t_lm_hw_name [31]; /* marketing name of this system */N unsigned char emb$b_lm_class; /* Device Class */N unsigned char emb$b_lm_type; /* Device Type */N unsigned short int emb$w_lm_unit; /* Device unit number */N char emb$t_lm_devnam [32]; /* Device name */N unsigned short int emb$w_lm_msgtyp; /* Type of logged message */N char emb$t_lm_dtname [28]; /* Device type name */N/* counted string */ } EMBLM; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBLMDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc.  **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */H/* Source: 02-SEP-1989 10:39:49 $1$DGA8345:[LIB_H.SRC]EMBLTDEF.SDL;1 *//*************************************** *****************************************************************************************//*** MODULE $EMBLTDEF ***/#ifndef __EMBLTDEF_LOADED#define __EMBLTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_unio n#endif#endif N/* */N/* LOGGED MESSAGE MESSAGE TYPES */N/* */N#define EMB$C_DM 1 /* Disk MSCP message */N#define EMB$K_DM 1 /* Disk MSCP message */N#define EMB$C_TM 2 /* Tape MSCP message */N#define EMB$K_TM 2 /* Tape MSCP message */N#define EMB$C_PM 3 /* Port (CI) message */N#define EMB$K_PM 3 /* Port (CI) message */N#define EMB$C_UM 4 /* Port (UDA) message */N#define EMB$K_UM 4 /* Port (UDA) message */N#define EMB$C_AVATN 5 /* Available Attention Message */N#define EMB$K_AVATN 5  /* Available Attention Message */Q#define EMB$C_DUPUN 6 /* Duplicate Unit ! Attention Message */Q#define EMB$K_DUPUN 6 /* Duplicate Unit ! Attention Message */N#define EMB$C_IVCMD 7 /* Invalid Command Log message. */N#define EMB$K_IVCMD 7 /* Invalid Command Log message. */N#define EMB$C_ACPTH 8 /* Access Path Attention Message */N#define EMB$K_ACPTH 8 /* Access Path Attention Message */N#define EMB$C_INVSTS 9 /* Invalid Status in End Message */N#define EMB$K_INVSTS 9 /* Invalid Status in End Message */N#define EMB$C_INVATT 10 /* Invalid Attention Message */N#define EMB$K_INVATT 10 /* Invalid Attention Message */N#define EMB$C_NOUNIT_DG 11 /* No unit in Datagram */N#define EMB$K_NOUNIT_DG 11 /* No unit in Datagram  */N#define EMB$C_SSTFAIL 12 /* Self test failed. */N#define EMB$K_SSTFAIL 12 /* Self test failed. */N#define EMB$C_KDB50 13 /* KDB50 error detected. */N#define EMB$K_KDB50 13 /* KDB50 error detected. */N/* */N/* The CTLRES_x fields below indicate that an MSCP controller was */N/* told to reset itself by a class driver because the controller */N/* is broken or confused. (To an HSC, this will cause a reboot.) */N/* The first three (INIT, INVMSG and IMTMO) do not have an MSCP end */N/* message logged with them. */N/* */s#define EMB$C_CTLRES_INIT 14 /* An error occurred during or the connection vanished before completing */\#define EMB$K_CTLRES_INIT 14 /* the initial handshake with the class driver. */q#define EMB$C_CTLRES_INVMSG 15 /* An invalid message was received from the controller. The offending */g#define EMB$K_CTLRES_INVMSG 15 /* message has been previously logged as INVATT or INVSTS. */q#define EMB$C_CTLRES_IMTMO 16 /* An immediate mode command has failed to complete within the timeout */a#define EMB$K_CTLRES_IMTMO 16 /* period, indicating a broken or wedged controller. */t#define EMB$C_CTLRES_TMO 17 /* No progress was made on a command during the timeout period. The MSCP */q#define EMB$K_CTLRES_TMO 17 /* GET COMMAND STATUS end message which determined this is included. */N/* */o#define EMB$C_BADRSPID 18 /* A message with an invalid RSPID was received by the class driver. */W#define EMB$K_BADRSPID 18 /* The offending MSCP message is included. */N/* */W#define EMB$C_BVPSSP 19 /* Port message for BVP Storage Systems Port */W#define EMB$K_BVPSSP 19 /* Port message for BVP Storage Systems Port */N#define EMB$C_NIPM 20 /* Port (NI) message */N#define EMB$K_NIPM 20 /* Port (NI) message */N#define EMB$C_LDR_ERR 21 /* Media Loade r error message */N#define EMB$K_LDR_ERR 21 /* Media Loader error message */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBLTDEF_LOADED */ ww$[UM/*********************************************!******************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP " **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** # **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:31 by OpenVMS SDL V3.7 */H/* Source: 27-AUG-1993 10:52:39 $1$DGA8345:[LIB_H.SRC]EMBMCDEF.SDL;1 *//********************************************************************************************* $***********************************//*** MODULE $EMBMCDEF ***/#ifndef __EMBMCDEF_LOADED#define __EMBMCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr siz%e default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/*& */N/* MACHINE CHECK LOG BUFFER FORMAT */N/* */N#define EMB$K_MC_LENGTH 144 /*LENGTH OF MACHINE CHECK FRAME */N#define EMB$C_MC_LENGTH 144 /*LENGTH OF MACHINE CHECK FRAME */N#define EMB$S_EMBMCDEF 144 /* Old size name - synonym */ typedef struct _embmc {'N unsigned int emb$l_mc_sid; /*SYSTEM ID */N unsigned short int emb$w_mc_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_mc_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_mc_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_mc_dev_class; /* DEVICE CLASS */N unsigned char emb$b_mc_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_m(c_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_mc_flags; /* MISC. FLAGS */N unsigned char emb$b_mc_os_id; /* LOGGING OS ID */N unsigned char emb$b_mc_hdrsz; /* HEADER SIZE */N unsigned short int emb$w_mc_entry; /*ENTRY TYPE */N unsigned __int64 emb$q_mc_time; /*TIME IN 64 BITS */N unsigned short int emb$w_mc_errseq; /*ERROR SE)QUENCE NUMBER */N unsigned __int64 emb$q_mc_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_mc_errmsk; /* ERROR MASK */N unsigned int emb$l_mc_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_mc_hw_name_len; /* Length of marketing name of this system */N char emb$t_mc_hw_name [31]; /* marketing name of this system */N unsigned char emb$b_mc_sumcod; /*SUMMARY CODE * */N unsigned char emb$b_mc_topf; /*TIME OUT PENDING FLAG */Q unsigned char emb$b_mc_opcode; /*OPCODE OF INSTRUCTION CAUSING CHECK */R unsigned char emb$b_mc_cachef; /*CACHE DISABLE FLAG, 1=GROUP 0, 2=G 1 */N unsigned int emb$l_mc_ces; /*CPU ERROR STATUS */N void *emb$l_mc_upc; /*MICRO-PC AT FAULT TIME */N void *emb$l_mc_va; /*VIRTUAL ADDRESS AT FAULT TIME */N un+signed int emb$l_mc_d; /*CPU D REGISTER AT FAULT TIME */N unsigned int emb$l_mc_tber0; /*TRANSLATION BUFFER STATUS REG 0 */N unsigned int emb$l_mc_tber1; /*TRANSLATION BUFFER STATUS REG 1 */R void *emb$l_mc_timoad; /*PHYSICAL ADDRESS CAUSING SBI TIMEOUT */N unsigned int emb$l_mc_parity; /*CACHE STATUS REGISTER */N unsigned int emb$l_mc_sbierr; /*SBI ERROR REGISTER */N void *emb$l_mc_pc; , /*PC OF INSTRUCTION CAUSING CHECK */N unsigned int emb$l_mc_psl; /*PSL OF MACHINE AT FAULT TIME */ } EMBMC; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBMCDEF_LOADED */ wwK[UM/*****-**********************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Pac.kard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. / **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:31 by OpenVMS SDL V3.7 */I/* Source: 27-AUG-1993 10:50:03 $1$DGA8345:[LIB_H.SRC]EMBPWRDEF.SDL;1 *//*************************************************** 0*****************************************************************************//*** MODULE $EMBPWRDEF ***/#ifndef __EMBPWRDEF_LOADED#define __EMBPWRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __requir1ed_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif2#endif  #include N/* */N/* Power event message */N/* */"#define EMB$K_PWR_STATE_LENGTH 354"#define EMB$C_PWR_STATE_LENGTH 354$#define EMB$K_PWR_HISTORY_LENGTH 616$#define EMB$C_PWR_HISTORY_LENGTH 616 #define EMB$K_PWR_BAD_LENGTH 133 #define EMB$C_PWR_BAD_LENGTH 133!#define 3EMB$K_PWR_GBUS_LENGTH 120!#define EMB$C_PWR_GBUS_LENGTH 120N#define EMB$S_EMBPWRDEF 616 /* Old size name - synonym */ typedef struct _embpwr {N unsigned int emb$l_pwr_sid; /*SYSTEM ID */N unsigned short int emb$w_pwr_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_pwr_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_pwr_cpuid; /* UNIQUE CPU ID */N unsigned4 char emb$b_pwr_dev_class; /* DEVICE CLASS */N unsigned char emb$b_pwr_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_pwr_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_pwr_flags; /* MISC. FLAGS */N unsigned char emb$b_pwr_os_id; /* LOGGING OS ID */N unsigned char emb$b_pwr_hdrsz; /* HEADER SIZE */N unsigned short int emb$w_pwr_entry5; /* ENTRY TYPE */N unsigned __int64 emb$q_pwr_time; /* TIME IN 64 BITS */N unsigned short int emb$w_pwr_errseq; /* ERROR SEQ ! */N unsigned __int64 emb$q_pwr_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_pwr_errmsk; /* ERROR MASK */N unsigned int emb$l_pwr_abstim; /* CONTENTS OF EXE$GL_ABSTIM */V unsigned char emb$b_pwr_hw_name_len; /* Length of marketing 6name of this system */N char emb$t_pwr_hw_name [31]; /* marketing name of this system */N/* */N/* Header common to all power events */N/* */N unsigned int emb$l_pwr_summary; /* Summary of regulators found */N unsigned __int64 emb$q_pwr_version; /* The version of laser_power.bli */N 7 unsigned int emb$l_pwr_type; /* Type of power event */N/* */N/* 4 possible sub typers in the union */N/* */ __union {N/* */N/* This is the type EMB$K_pwr_state_event specific layout */N/* 8 */ __struct {f unsigned __int64 emb$q_pwr_state_time_center_a; /* Timestamp regulator A center cabinet */f unsigned __int64 emb$q_pwr_state_time_center_b; /* Timestamp regulator B center cabinet */f unsigned __int64 emb$q_pwr_state_time_center_c; /* Timestamp regulator C center cabinet */b unsigned __int64 emb$q_pwr_state_time_left_a; /* Timestamp regulator A left cabinet */b 9 unsigned __int64 emb$q_pwr_state_time_left_b; /* Timestamp regulator B left cabinet */b unsigned __int64 emb$q_pwr_state_time_left_c; /* Timestamp regulator C left cabinet */d unsigned __int64 emb$q_pwr_state_time_right_a; /* Timestamp regulator A right cabinet */d unsigned __int64 emb$q_pwr_state_time_right_b; /* Timestamp regulator B right cabinet */d unsigned __int64 emb$q_pwr_state_time_right_c; /* Timestamp regulator C right cabinet */^ : char emb$t_pwr_state_bmsg_center_a [9]; /* B message regulator A center cabinet */N char emb$t_pwr_state_fill_center_a [3]; /* Long align */^ char emb$t_pwr_state_bmsg_center_b [9]; /* B message regulator B center cabinet */N char emb$t_pwr_state_fill_center_b [3]; /* Long align */^ char emb$t_pwr_state_bmsg_center_c [9]; /* B message regulator C center cabinet */N char emb$t_pwr_state_fill_center_c [3]; /* Long al;ign */Z char emb$t_pwr_state_bmsg_left_a [9]; /* B message regulator A left cabinet */N char emb$t_pwr_state_fill_left_a [3]; /* Long align */Z char emb$t_pwr_state_bmsg_left_b [9]; /* B message regulator B left cabinet */N char emb$t_pwr_state_fill_left_b [3]; /* Long align */Z char emb$t_pwr_state_bmsg_left_c [9]; /* B message regulator C left cabinet */N char emb$t_pwr_state_fill_left_c [3]; /*< Long align */\ char emb$t_pwr_state_bmsg_right_a [9]; /* B message regulator A right cabinet */N char emb$t_pwr_state_fill_right_a [3]; /* Long align */\ char emb$t_pwr_state_bmsg_right_b [9]; /* B message regulator B right cabinet */N char emb$t_pwr_state_fill_right_b [3]; /* Long align */\ char emb$t_pwr_state_bmsg_right_c [9]; /* B message regulator C right cabinet */N char emb$t_pwr_state_fil =l_right_c [3]; /* Long align */ __struct {O unsigned int emb$l_pwr_state_id_cabinet; /* Event cabinet id */S unsigned int emb$l_pwr_state_id_regulator; /* Event regulator id */% } emb$r_pwr_state_id;P char emb$t_pwr_state_smsg [54]; /* S message from event regulator */ } emb$r_state;N/* */N/* This is the type EMB$K_pwr_history>_event specific layout */N/* */ __struct {a char emb$t_pwr_history_hmsg_center_a [54]; /* H message regulator A center cabinet */N char emb$t_pwr_history_fill_center_a [2]; /* Long align */a char emb$t_pwr_history_hmsg_center_b [54]; /* H message regulator B center cabinet */N char emb$t_pwr_history_fill_center_b [2]; /* Long align */a ? char emb$t_pwr_history_hmsg_center_c [54]; /* H message regulator C center cabinet */N char emb$t_pwr_history_fill_center_c [2]; /* Long align */] char emb$t_pwr_history_hmsg_left_a [54]; /* H message regulator A left cabinet */N char emb$t_pwr_history_fill_left_a [2]; /* Long align */] char emb$t_pwr_history_hmsg_left_b [54]; /* H message regulator B left cabinet */N char emb$t_pwr_history_fill_left_b [2]; /* L@ong align */] char emb$t_pwr_history_hmsg_left_c [54]; /* H message regulator C left cabinet */N char emb$t_pwr_history_fill_left_c [2]; /* Long align */_ char emb$t_pwr_history_hmsg_right_a [54]; /* H message regulator A right cabinet */N char emb$t_pwr_history_fill_right_a [2]; /* Long align */_ char emb$t_pwr_history_hmsg_right_b [54]; /* H message regulator B right cabinet */N char emb$t_pwr_hisAtory_fill_right_b [2]; /* Long align */_ char emb$t_pwr_history_hmsg_right_c [54]; /* H message regulator C right cabinet */N char emb$t_pwr_history_fill_right_c [2]; /* Long align */ } emb$r_history;N/* */N/* This is the type EMB$K_pwr_bad_event specific layout */N/* */ B__struct { __struct {N unsigned int emb$l_pwr_bad_id_cabinet; /* Event cabinet id */Q unsigned int emb$l_pwr_bad_id_regulator; /* Event regulator id */# } emb$r_pwr_bad_id;N unsigned int emb$l_pwr_bad_type; /* Bad event type */N char emb$t_pwr_bad_bmsg [9]; /* B message from event regulator */ } emb$r_bad;N/* */ CN/* This is the type EMB$K_gbus specific layout */N/* */ __struct {N unsigned int emb$l_pwr_gbus_halt; /* current GBUS$HALT register */O unsigned int emb$l_pwr_last_gbus; /* previous GBUS$HALT register */ } emb$r_gbus; } emb$r_pwr; } EMBPWR; #if !defined(__VAXC)Y#define emb$q_pwr_state_time_center_a emb$r_pwr.emb$r_state.emb$q_pwDr_state_time_center_aY#define emb$q_pwr_state_time_center_b emb$r_pwr.emb$r_state.emb$q_pwr_state_time_center_bY#define emb$q_pwr_state_time_center_c emb$r_pwr.emb$r_state.emb$q_pwr_state_time_center_cU#define emb$q_pwr_state_time_left_a emb$r_pwr.emb$r_state.emb$q_pwr_state_time_left_aU#define emb$q_pwr_state_time_left_b emb$r_pwr.emb$r_state.emb$q_pwr_state_time_left_bU#define emb$q_pwr_state_time_left_c emb$r_pwr.emb$r_state.emb$q_pwr_state_time_left_cW#define emb$q_pwr_state_time_rightE_a emb$r_pwr.emb$r_state.emb$q_pwr_state_time_right_aW#define emb$q_pwr_state_time_right_b emb$r_pwr.emb$r_state.emb$q_pwr_state_time_right_bW#define emb$q_pwr_state_time_right_c emb$r_pwr.emb$r_state.emb$q_pwr_state_time_right_cY#define emb$t_pwr_state_bmsg_center_a emb$r_pwr.emb$r_state.emb$t_pwr_state_bmsg_center_aY#define emb$t_pwr_state_bmsg_center_b emb$r_pwr.emb$r_state.emb$t_pwr_state_bmsg_center_bY#define emb$t_pwr_state_bmsg_center_c emb$r_pwr.emb$r_state.emb$t_pwr_state_bmsg_centeFr_cU#define emb$t_pwr_state_bmsg_left_a emb$r_pwr.emb$r_state.emb$t_pwr_state_bmsg_left_aU#define emb$t_pwr_state_bmsg_left_b emb$r_pwr.emb$r_state.emb$t_pwr_state_bmsg_left_bU#define emb$t_pwr_state_bmsg_left_c emb$r_pwr.emb$r_state.emb$t_pwr_state_bmsg_left_cW#define emb$t_pwr_state_bmsg_right_a emb$r_pwr.emb$r_state.emb$t_pwr_state_bmsg_right_aW#define emb$t_pwr_state_bmsg_right_b emb$r_pwr.emb$r_state.emb$t_pwr_state_bmsg_right_bW#define emb$t_pwr_state_bmsg_right_c emb$r_pwr.emb$r_staGte.emb$t_pwr_state_bmsg_right_cC#define emb$r_pwr_state_id emb$r_pwr.emb$r_state.emb$r_pwr_state_idP#define emb$l_pwr_state_id_cabinet emb$r_pwr_state_id.emb$l_pwr_state_id_cabinetT#define emb$l_pwr_state_id_regulator emb$r_pwr_state_id.emb$l_pwr_state_id_regulatorG#define emb$t_pwr_state_smsg emb$r_pwr.emb$r_state.emb$t_pwr_state_smsg-#define emb$r_history emb$r_pwr.emb$r_historyU#define emb$t_pwr_history_hmsg_center_a emb$r_history.emb$t_pwr_history_hmsg_center_aU#define emb$t_pwr_historHy_hmsg_center_b emb$r_history.emb$t_pwr_history_hmsg_center_bU#define emb$t_pwr_history_hmsg_center_c emb$r_history.emb$t_pwr_history_hmsg_center_cQ#define emb$t_pwr_history_hmsg_left_a emb$r_history.emb$t_pwr_history_hmsg_left_aQ#define emb$t_pwr_history_hmsg_left_b emb$r_history.emb$t_pwr_history_hmsg_left_bQ#define emb$t_pwr_history_hmsg_left_c emb$r_history.emb$t_pwr_history_hmsg_left_cS#define emb$t_pwr_history_hmsg_right_a emb$r_history.emb$t_pwr_history_hmsg_right_aS#define emb$t_pwIr_history_hmsg_right_b emb$r_history.emb$t_pwr_history_hmsg_right_bS#define emb$t_pwr_history_hmsg_right_c emb$r_history.emb$t_pwr_history_hmsg_right_c%#define emb$r_bad emb$r_pwr.emb$r_bad3#define emb$r_pwr_bad_id emb$r_bad.emb$r_pwr_bad_idJ#define emb$l_pwr_bad_id_cabinet emb$r_pwr_bad_id.emb$l_pwr_bad_id_cabinetN#define emb$l_pwr_bad_id_regulator emb$r_pwr_bad_id.emb$l_pwr_bad_id_regulator7#define emb$l_pwr_bad_type emb$r_bad.emb$l_pwr_bad_type7#define emb$t_pwr_bad_bmsg emb$r_bad.emb$t J_pwr_bad_bmsg'#define emb$r_gbus emb$r_pwr.emb$r_gbus:#define emb$l_pwr_gbus_halt emb$r_gbus.emb$l_pwr_gbus_halt:#define emb$l_pwr_last_gbus emb$r_gbus.emb$l_pwr_last_gbus"#endif /* #if !defined(__VAXC) */ N/* */N/* Values in PWR_TYPE. */N/* */N#define EMB$K_PWR_STATE_EVENT 1 /* State K change event */N#define EMB$K_PWR_HISTORY_EVENT 2 /* Initial history event */N#define EMB$K_PWR_BAD_EVENT 3 /* Bad checksum or no ans */N#define EMB$K_PWR_GBUS_EVENT 4 /* GBUS had some bits set */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endifL#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBPWRDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone witMhout the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prNior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:32 by OpenVMS SDL V3.7 */H O/* Source: 27-AUG-1993 10:52:58 $1$DGA8345:[LIB_H.SRC]EMBSBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBSBDEF ***/#ifndef __EMBSBDEF_LOADED#define __EMBSBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas Psupported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endifQ#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/* */N/* SBI FAULT BUFFER FORMAT AND ASYNCHRONOUS WRITE ERROR FORMAT */N/* */N#define EMB$K_SB_LENGTH 252 /*LENGTH OF SBI ERROR BUFFER */N#define EMB$C_SB_LEN RGTH 252 /*LENGTH OF SBI ERROR BUFFER */N#define EMB$S_EMBSBDEF 252 /* Old size name - synonym */ typedef struct _embsb {N unsigned int emb$l_sb_sid; /*SYSTEM ID */N unsigned short int emb$w_sb_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_sb_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_sb_cpuid; /* UNIQUE CPU ID */N unsigned chaSr emb$b_sb_dev_class; /* DEVICE CLASS */N unsigned char emb$b_sb_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_sb_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_sb_flags; /* MISC. FLAGS */N unsigned char emb$b_sb_os_id; /* LOGGING OS ID */N unsigned char emb$b_sb_hdrsz; /* HEADER SIZE */N unsigned short int emb$w_sb_entry; /*TENTRY TYPE */N unsigned __int64 emb$q_sb_time; /*TIME IN 64 BITS */N unsigned short int emb$w_sb_errseq; /*ERROR SEQUENCE NUMBER */N unsigned __int64 emb$q_sb_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_sb_errmsk; /* ERROR MASK */N unsigned int emb$l_sb_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_sb_hw_name_len; /* Length of marketing name Uof this system */N char emb$t_sb_hw_name [31]; /* marketing name of this system */N unsigned int emb$l_sb_fault; /*SBI FAULT/STATUS REGISTER */N unsigned int emb$l_sb_silcmp; /*SBI SILO COMPARATOR */N unsigned int emb$l_sb_maint; /*SBI MAINTENANCE */N unsigned int emb$l_sb_error; /*SBI ERROR REG */N unsigned int emb$l_sb_timout; /*SBI TIMEOUT REG */N un Vsigned int emb$l_sb_silo [16]; /*SBI SILO REG */N unsigned int emb$l_sb_sbirgs [16]; /*REGISTER A'S ON BUS (OR 0) */N void *emb$l_sb_pc; /*PC OF INSTRUCTION AT FAULT TIME */N unsigned int emb$l_sb_psl; /*PSL OF MACHINE AT FAULT TIME */ } EMBSB; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* RestoWre the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBSBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorXized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicateYd or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created Z: 7-Oct-2024 15:23:32 by OpenVMS SDL V3.7 */H/* Source: 11-AUG-2004 16:46:46 $1$DGA8345:[LIB_H.SRC]EMBSEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBSEDEF ***/#ifndef __EMBSEDEF_LOADED#define __EMBSEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL[_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct str\uct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/* */N/* SOFT ECC DETECTED ERRORS */N/* */N#define EMB$K_SE_REVISION 3 /* Rev ]ision field */N#define EMB$C_SE_REVISION 3 /* Revision field */%#define EMB$M_SE_CRD_FLG_DISABLED 0x1&#define EMB$M_SE_CRD_FLG_LOST_INFO 0x2!#define EMB$M_SE_RSN_INIT_ERR 0x1%#define EMB$M_SE_RSN_FPRINTS_FULL 0x2!#define EMB$M_SE_RSN_SHUTDOWN 0x4$#define EMB$M_SE_RSN_DOMAIN_GREW 0x8 #define EMB$M_SE_RSN_BADPGS 0x10N#define EMB$K_SE_FIXED_HD_LENGTH 128 /* Size of FIXED ERL HEADER */N#define EMB$C_SE_FIXED_HD_LENGTH 128 /* Size ^of FIXED ERL HEADER */N#define EMB$S_EMBSEDEF 128 /* Old size name - synonym */N/*++ */ typedef struct _embse {N unsigned int emb$l_se_sid; /*SYSTEM ID */N unsigned short int emb$w_se_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_se_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_se_cpuid; /* U_NIQUE CPU ID */N unsigned char emb$b_se_dev_class; /* DEVICE CLASS */N unsigned char emb$b_se_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_se_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_se_flags; /* MISC. FLAGS */N unsigned char emb$b_se_os_id; /* LOGGING OS ID */N unsigned char emb$b_se_hdrsz; /* HEADER SIZE ` */N unsigned short int emb$w_se_entry; /*ENTRY TYPE */N unsigned __int64 emb$q_se_time; /*TIME IN 64 BITS */N unsigned short int emb$w_se_errseq; /*ERROR SEQUENCE NUMBER */N unsigned __int64 emb$q_se_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_se_errmsk; /* ERROR MASK */N unsigned int emb$l_se_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned chaar emb$b_se_hw_name_len; /* Length of marketing name of this system */N char emb$t_se_hw_name [31]; /* marketing name of this system */N/* */N/* Start of CRD info */N/* */N unsigned short int emb$w_se_revision; /* ERL revision field */ __union {N unsigned s bhort int emb$w_se_crd_flags; /* ERL flags */ __struct {h unsigned emb$v_se_crd_flg_disabled : 1; /* Indicates CRD init processing is not complete. */N/* No scrubbing/replacement til flag is cleared */N unsigned emb$v_se_crd_flg_lost_info : 1; /* Lost information */& unsigned emb$v_fill1 : 14;' } emb$r_se_crd_flags_field;% } emb$r_se_crd_flags_overlay;N/* c */N/* LOG_REASON corresponds to the field CRD_FOOT$W_LOG_REASON defined in */N/* $CRD_FOOT. If this field is ever changed, appropriate action must */N/* be taken in CRD_FOOT as well. */N/* */ __union {O unsigned short int emb$w_se_log_reason; /* Reason for this ERL entry */ __struct {a unsignedd emb$v_se_rsn_init_err : 1; /* Error occurred during CRDERR initialization */f unsigned emb$v_se_rsn_fprints_full : 1; /* Entries logged because all footprints in use */P unsigned emb$v_se_rsn_shutdown : 1; /* Entries logged at shutdown */d unsigned emb$v_se_rsn_domain_grew : 1; /* Set when ADDR_CUM in a fprint goes non-zero */[ unsigned emb$v_se_rsn_badpgs : 1; /* Indicates a non-zero RPB bad page count */& unsigned emb$v_fill1 : 11;) e } emb$r_se_log_reason_field1;& } emb$r_se_log_reason_overlay;U unsigned short int emb$w_se_n_of_m; /* "N of M" field. Ie., packet "1" of "3" */N unsigned int emb$l_se_hwrpb_badpgs; /* RPB bad page count */N unsigned int emb$l_se_memdsc_size; /* variable SYSLOA memdsc size */Y unsigned int emb$l_se_memdsc_offset; /* Offset from beg. of EMB to start of memdsc */N unsigned int emb$l_se_num_fprints; /* Number of footprints in this EMB */N un fsigned int emb$l_se_fprint_size; /* Size, in bytes, of each fprint */Z unsigned int emb$l_se_fprint_offset; /* Offset from beg. of EMB to start of fprints */N/* End of *Fixed portion* of the SE$ header */N/*-- */ } EMBSE; #if !defined(__VAXC)H#define emb$w_se_crd_flags emb$r_se_crd_flags_overlay.emb$w_se_crd_flagso#define emb$v_se_crd_flg_disabled emb$r_se_crd_flags_overlay.emb$rg_se_crd_flags_field.emb$v_se_crd_flg_disabledq#define emb$v_se_crd_flg_lost_info emb$r_se_crd_flags_overlay.emb$r_se_crd_flags_field.emb$v_se_crd_flg_lost_infoK#define emb$w_se_log_reason emb$r_se_log_reason_overlay.emb$w_se_log_reasonj#define emb$v_se_rsn_init_err emb$r_se_log_reason_overlay.emb$r_se_log_reason_field1.emb$v_se_rsn_init_errr#define emb$v_se_rsn_fprints_full emb$r_se_log_reason_overlay.emb$r_se_log_reason_field1.emb$v_se_rsn_fprints_fullj#define emb$v_se_rsn_shutdown emb$r_se_l hog_reason_overlay.emb$r_se_log_reason_field1.emb$v_se_rsn_shutdownp#define emb$v_se_rsn_domain_grew emb$r_se_log_reason_overlay.emb$r_se_log_reason_field1.emb$v_se_rsn_domain_grewf#define emb$v_se_rsn_badpgs emb$r_se_log_reason_overlay.emb$r_se_log_reason_field1.emb$v_se_rsn_badpgs"#endif /* #if !defined(__VAXC) */ N#define CRD_FOOT$K_MAX_FOOTPRINTS 16 /* Max # of fprints */"#define CRD_FOOT$M_SFLAGS_BUSY 0x1)#define CRD_FOOT$M_SFLAGS_SW_SCRUBBED 0x2%#define CRD_FOOT$M_C iALLER_NOSCRUB 0x1'#define CRD_FOOT$M_CALLER_NOREPLACE 0x2"#define CRD_FOOT$M_CALLER_MULE 0x4'#define CRD_FOOT$M_SCRMSK_PFNTOOBIG 0x1"#define CRD_FOOT$M_SCRMSK_MCHK 0x2'#define CRD_FOOT$M_SCRMSK_MAPFAILED 0x4)#define CRD_FOOT$M_SCRMSK_UNMAPFAILED 0x8+#define CRD_FOOT$M_SCRMSK_TOOMANYRETRY 0x10N#define CRD_FOOT$K_LENGTH 80 /* Length of argument area */N#define CRD_FOOT$C_LENGTH 80 /* Length of argument area */N#define CRD_FOOT$S_CRD_FOOTDEF 80 j /* Old size name - synonym */ typedef struct _crd_foot {N unsigned __int64 crd_foot$q_footprint; /* 64-bits of error syndrome */N unsigned __int64 crd_foot$q_systime; /* System time of the CRD */^ unsigned __int64 crd_foot$q_addr_low; /* 64-bit lowest address associated with this CRD */` unsigned __int64 crd_foot$q_addr_high; /* 64-bit highest address associated with this CRD */x unsigned __int64 crd_foot$q_addr_cum; /* 64-bit bitmask of lowest address kXORed, then ORed with all new addresses */P unsigned int crd_foot$l_scrub_blksiz; /* Size, in bytes, of area to scrub */ __union {N unsigned short int crd_foot$w_static_flags; /* Footprint flags */ __struct {U unsigned crd_foot$v_sflags_busy : 1; /* Indicates this CRD_FOOT in use */N unsigned crd_foot$v_sflags_sw_scrubbed : 1; /* CRD scrubbed */+ unsigned crd_foot$v_fill1 : 14;- } crd_foot$r_static_flags_field1;*l } crd_foot$r_static_flags_overlay;N/* The CRD_FOOT$W_LOG_REASON contains a bitmask of reasons for logging a */N/* particular footprint. These bit definitions must line up with those in */N/* $CRD_EMBDEF. In particular, the field CRD_EMB$W_LOG_REASON defines the */O/* acceptable log reason bits. [LIB]CRD_EMBDEF.SDL should be updated if new */N/* reasons need to be defined. */N/* m */S unsigned short int crd_foot$w_log_reason; /* Reasons for logging this fprint */ __union {O unsigned int crd_foot$l_caller_flags; /* Status bits for this CALLER */ __struct {o unsigned crd_foot$v_caller_noscrub : 1; /* Only update the footprint info - do not attempt scrub */s unsigned crd_foot$v_caller_noreplace : 1; /* Only update the footprint info - do not attempt replace */N unsigned crd_foot$v_caller_mule : 1; n /* multiple error found */+ unsigned crd_foot$v_fill1 : 29;- } crd_foot$r_caller_flags_field1;* } crd_foot$r_caller_flags_overlay; __union {n unsigned int crd_foot$l_scrub_failmsk; /* Contains collective reasons why page couldn't be scrubbed */ __struct {n unsigned crd_foot$v_scrmsk_pfntoobig : 1; /* Footprint PFN was greater than the system maximum. */Z unsigned crd_foot$v_scrmsk_mchk : 1; /* Machine check occurredo during scrub */\ unsigned crd_foot$v_scrmsk_mapfailed : 1; /* Mapping the physical addr failed */` unsigned crd_foot$v_scrmsk_unmapfailed : 1; /* Unmapping the physical addr failed */O unsigned crd_foot$v_scrmsk_toomanyretry : 1; /* Too many retries */+ unsigned crd_foot$v_fill1 : 27;+ } crd_foot$r_scrfailmsk_field1;( } crd_foot$r_scrfailmsk_overlay;S unsigned int crd_foot$l_match_cnt; /* Total CRDs which match this footprint p */Q unsigned int crd_foot$l_scrub_cnt; /* Number of times a page was scrubbed */i unsigned __int64 crd_foot$q_firstscrub_time; /* Time at which first scrubbed CRD matched footprint */n unsigned __int64 crd_foot$q_lastscrub_time; /* Time at which last CRD matched footprint after scrubbing */ } CRD_FOOT; #if !defined(__VAXC)W#define crd_foot$w_static_flags crd_foot$r_static_flags_overlay.crd_foot$w_static_flagst#define crd_foot$v_sflags_busy crd_foot$r_static_flags_overlayq.crd_foot$r_static_flags_field1.crd_foot$v_sflags_busy#define crd_foot$v_sflags_sw_scrubbed crd_foot$r_static_flags_overlay.crd_foot$r_static_flags_field1.crd_foot$v_sflags_sw_scrubbedW#define crd_foot$l_caller_flags crd_foot$r_caller_flags_overlay.crd_foot$l_caller_flagsz#define crd_foot$v_caller_noscrub crd_foot$r_caller_flags_overlay.crd_foot$r_caller_flags_field1.crd_foot$v_caller_noscrub~#define crd_foot$v_caller_noreplace crd_foot$r_caller_flags_overlay.crd_foot$r_caller_flags_field1.crd_froot$v_caller_noreplacet#define crd_foot$v_caller_mule crd_foot$r_caller_flags_overlay.crd_foot$r_caller_flags_field1.crd_foot$v_caller_muleW#define crd_foot$l_scrub_failmsk crd_foot$r_scrfailmsk_overlay.crd_foot$l_scrub_failmskz#define crd_foot$v_scrmsk_pfntoobig crd_foot$r_scrfailmsk_overlay.crd_foot$r_scrfailmsk_field1.crd_foot$v_scrmsk_pfntoobigp#define crd_foot$v_scrmsk_mchk crd_foot$r_scrfailmsk_overlay.crd_foot$r_scrfailmsk_field1.crd_foot$v_scrmsk_mchkz#define crd_foot$v_scrmsk_mapfailed scrd_foot$r_scrfailmsk_overlay.crd_foot$r_scrfailmsk_field1.crd_foot$v_scrmsk_mapfailed~#define crd_foot$v_scrmsk_unmapfailed crd_foot$r_scrfailmsk_overlay.crd_foot$r_scrfailmsk_field1.crd_foot$v_scrmsk_unmapfailed#define crd_foot$v_scrmsk_toomanyretry crd_foot$r_scrfailmsk_overlay.crd_foot$r_scrfailmsk_field1.crd_foot$v_scrmsk_toomanyretry"#endif /* #if !defined(__VAXC) */ #define CRD_ARG$K_LENGTH 32#define CRD_ARG$C_LENGTH 32N#define CRD_ARG$S_CRD_ARGDEF 32 /* Old size name - s tynonym */ typedef struct _crd_arg {N unsigned __int64 crd_arg$q_footprint; /* 64-bits of error syndrome */N unsigned __int64 crd_arg$q_systime; /* System time of the CRD */N unsigned __int64 crd_arg$q_address; /* 64-bit address */N unsigned int crd_arg$l_flags; /* flags */O unsigned int crd_arg$l_scrub_blksiz; /* Size, in bytes, of area to scrub */ } CRD_ARG;N#define CRD$K_SCRUB_RETRY 3 u /* Number of retries */N/* Define fields in EXE$GL_CRD_CONTROL */$#define CRD_CONTROL$M_CRD_ENABLE 0x1&#define CRD_CONTROL$M_SCRUB_ENABLE 0x2-#define CRD_CONTROL$M_PAGE_REPLACE_ENABLE 0x4)#define CRD_CONTROL$M_FORCE_ALL_PFNDB 0x8'#define CRD_CONTROL$M_EXT_CRD_ONLY 0x10(#define CRD_CONTROL$M_LOAD_SMDRIVER 0x20+#define CRD_CONTROL$M_THROTTLE_DISABLE 0x40&#define CRD_CONTROL$M_SEL_DISABLE 0x80 typedef struct _crd_control { __ vunion {& int crd_control$l_crd_control; __struct {N unsigned crd_control$v_crd_enable : 1; /* Enable CRD processing */P unsigned crd_control$v_scrub_enable : 1; /* CRD scrubbing enabled */] unsigned crd_control$v_page_replace_enable : 1; /* Enable bad page replacement */W unsigned crd_control$v_force_all_pfndb : 1; /* Force all pages in PFN db */Q unsigned crd_control$v_ext_crd_only : 1; /* Log only Extended CRDs */N w unsigned crd_control$v_load_smdriver : 1; /* Load SMDRIVER */^ unsigned crd_control$v_throttle_disable : 1; /* Disable CRD throttling when set */V unsigned crd_control$v_sel_disable : 1; /* Disable SEL Polling when set */0 unsigned crd_control$v_reserved : 8;b unsigned short int crd_control$w_sys_specific; /* Reserved for system-specific bits *// } crd_control$r_crd_control_fields;, } crd_control$r_crd_control_overlay;x } CRD_CONTROL; #if !defined(__VAXC)]#define crd_control$l_crd_control crd_control$r_crd_control_overlay.crd_control$l_crd_control|#define crd_control$v_crd_enable crd_control$r_crd_control_overlay.crd_control$r_crd_control_fields.crd_control$v_crd_enable#define crd_control$v_scrub_enable crd_control$r_crd_control_overlay.crd_control$r_crd_control_fields.crd_control$v_scrub_enable#define crd_control$v_page_replace_enable crd_control$r_crd_control_overlay.crd_control$r_crd_control_fielyds.crd_control$v_page_rep\ lace_enable#define crd_control$v_force_all_pfndb crd_control$r_crd_control_overlay.crd_control$r_crd_control_fields.crd_control$v_force_all_pf\ndb#define crd_control$v_ext_crd_only crd_control$r_crd_control_overlay.crd_control$r_crd_control_fields.crd_control$v_ext_crd_only#define crd_control$v_load_smdriver crd_control$r_crd_control_overlay.crd_control$r_crd_control_fields.crd_control$v_load_smdriver#define crd_control$v_throttle_disable crd_control$r_crd_contr zol_overlay.crd_control$r_crd_control_fields.crd_control$v_throttle_di\sable~#define crd_control$v_sel_disable crd_control$r_crd_control_overlay.crd_control$r_crd_control_fields.crd_control$v_sel_disable#define crd_control$w_sys_specific crd_control$r_crd_control_overlay.crd_control$r_crd_control_fields.crd_control$w_sys_specific"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#p{ragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBSEDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterpri|se Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is no}t **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************************* ~*************************************/=/* Created: 7-Oct-2024 15:23:32 by OpenVMS SDL V3.7 */H/* Source: 27-AUG-1993 10:53:30 $1$DGA8345:[LIB_H.SRC]EMBSPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBSPDEF ***/#ifndef __EMBSPDEF_LOADED#define __EMBSPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/* */N/* ERROR BUFFER FORMAT FOR SAVING SOFTWARE PARAMETERS FOR CLASS DRIVER THAT */N/* CORRESPOND TO A LOGGED MESSAGE (SEE EMBLMDEF BELOW) ORIGINATING */N/* IN AN INTELLIGENT MASS STORAGE CONTROLLER. */N/* */#define EMB$K_SP_LENGTH 184#define EMB$C_SP_LENGTH 184N#define EMB$S_EMBSPDEF 184 /* Old size name - synonym */ typedef struct _embsp {N unsigned int emb$l_sp_sid; /* System ID */N unsigned short int emb$w_sp_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_sp_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_sp_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_sp_dev_class; /* DEVICE CLASS */N unsigned char emb$b_sp_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_sp_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_sp_flags; /* MISC. FLAGS */N unsigned char emb$b_sp_os_id;  /* LOGGING OS ID */N unsigned char emb$b_sp_hdrsz; /* HEADER SIZE */S unsigned short int emb$w_sp_entry; /* Entry type (of this errorlog buffer) */N unsigned __int64 emb$q_sp_time; /* Time this entry created */N unsigned short int emb$w_sp_errseq; /* Error Sequence Number */N unsigned __int64 emb$q_sp_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_sp_errmsk; /* ERROR MASK  */N unsigned int emb$l_sp_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_sp_hw_name_len; /* Length of marketing name of this system */N char emb$t_sp_hw_name [31]; /* marketing name of this system */N unsigned char emb$b_sp_class; /* Device Class */N unsigned char emb$b_sp_type; /* Device Type */N unsigned int emb$l_sp_boff; /* Byte OFFset of data transfer */N unsigned int emb$l_sp_bcnt; /* Byte Count of data transfer */S unsigned int emb$l_sp_media; /* Media address (LBN) of data transfer */N unsigned int emb$l_sp_rqpid; /* Requesting PID */N unsigned __int64 emb$q_sp_iosb; /* Final I/O status */N unsigned int emb$l_sp_func; /* I/O function code */N unsigned short int emb$w_sp_unit; /* Unit number of drive */T unsigned int emb$l_sp_opcnt; /* Cummulative operation count this unit */T unsigned int emb$l_sp_errcnt; /* Cummulative error count for this unit */N unsigned int emb$l_sp_ucbsts; /* Copy of UCB$W_STS field */N unsigned int emb$l_sp_ownuic; /* Unit's owner's UIC */N unsigned int emb$l_sp_char; /* Device Characteristics */O unsigned int emb$l_sp_cmdref; /* Command Reference number (RSPID) */N char emb$t_sp_devnam [32]; /* Device name */ } EMBSP; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBSPDEF_LOADED */ ww`[UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:32 by OpenVMS SDL V3.7 */H/* Source: 27-AUG-1993 10:54:02 $1$DGA8345:[LIB_H.SRC]EMBSSDEF.SDL;1 *//********************************************************************************************************************************//* ** MODULE $EMBSSDEF ***/#ifndef __EMBSSDEF_LOADED#define __EMBSSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/*  */N/* SYSTEM SERVICE MESSAGE */N/* */N/* NOTE: SYSTEM SERVICE MESSAGE COVERS: */N/* */N/* 1) THE MESSAGES FROM THE SERVICE */N/* 2) OPERATOR MESSAGES  */N/* 3) NETWORK MESSAGES */N/* */N/* ONLY THE TYPE FIELD IS DIFERENT */N/* */N#define EMB$K_SS_LENGTH 98 /*LENGTH OF CONSTANT PART */N#define EMB$C_SS_LENGTH 98 /*LENGTH OF CONSTANT PART */N#define EMB$S_ EMBSSDEF 99 /* Old size name - synonym */ typedef struct _embss {N unsigned int emb$l_ss_sid; /*SYSTEM ID */N unsigned short int emb$w_ss_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_ss_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_ss_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_ss_dev_class; /* DEVICE CLASS */N unsigned char emb$b_ss_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_ss_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_ss_flags; /* MISC. FLAGS */N unsigned char emb$b_ss_os_id; /* LOGGING OS ID */N unsigned char emb$b_ss_hdrsz; /* HEADER SIZE */N unsigned short int emb$w_ss_entry; /*ENTRY TYPE */N unsigned __int64 emb$q_ss_time;  /*TIME IN 64 BITS */N unsigned short int emb$w_ss_errseq; /*ERROR SEQUENCE NUMBER */N unsigned __int64 emb$q_ss_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_ss_errmsk; /* ERROR MASK */N unsigned int emb$l_ss_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_ss_hw_name_len; /* Length of marketing name of this system */N char emb$t_ss_hw_name [31]; /* marketing name of this system */N unsigned short int emb$w_ss_msgsz; /*MESSAGE TEXT SIZE IN BYTES */N unsigned char emb$b_ss_msgtxt; /*FIRST BYTE OF MESSAGE TEXT */ } EMBSS; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ EMBSSDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE.  **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/**  2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:32 by OpenVMS SDL V3.7 */H/* Source: 27-AUG-1993 10:54:15 $1$DGA8345:[LIB_H.SRC]EMBSUDEF.SDL;1 */ /********************************************************************************************************************************//*** MODULE $EMBSUDEF ***/#ifndef __EMBSUDEF_LOADED#define __EMBSUDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/* */N/* SYSTEM STARTUP MESSAGE */N/* */N#define EMB$K_SU_LENGTH 100 /*LENGTH OF MESSAGE */N#define EMB$C_SU_LENGTH 100 /*LENGTH OF MESSAGE */N#define EMB$S_ EMBSUDEF 100 /* Old size name - synonym */ typedef struct _embsu {N unsigned int emb$l_su_sid; /*SYSTEM ID */N unsigned short int emb$w_su_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_su_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_su_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_su_dev_class; /* DEVICE CLASS */N unsigned char emb$b_su_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_su_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_su_flags; /* MISC. FLAGS */N unsigned char emb$b_su_os_id; /* LOGGING OS ID */N unsigned char emb$b_su_hdrsz; /* HEADER SIZE */U unsigned short int emb$w_su_entry; /*ENTRY TYPE (IE: BOOT OR POWER RECOVERY) */N unsigned __int64 emb$q_su_time; /*CONTENTS OF SYSTEM TIME QUADWORD */N unsigned short int emb$w_su_errseq; /*ERROR SEQUENCE NUMBER */N unsigned __int64 emb$q_su_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_su_errmsk; /* ERROR MASK */N unsigned int emb$l_su_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_su_hw_name_len; /* Length of marketing name of this system */N char emb$t_su_hw_name [31]; /* marketing name of this system */N unsigned int emb$l_su_daytim; /*CONTENTS OF TIME OF DAY CLOCK */ } EMBSU; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBSUDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:32 by OpenVMS SDL V3.7 */H/* Source: 27-AUG-1993 10:50:00 $1$DGA8345:[LIB_H.SRC]EMBTSDEF.SDL;1 *//*********************************************************************** *********************************************************//*** MODULE $EMBTSDEF ***/#ifndef __EMBTSDEF_LOADED#define __EMBTSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #inc lude N/* */N/* TIME STAMP MSG FORMAT */N/* */N#define EMB$K_TS_LENGTH 96 /*LENGTH OF TIME STAMP MSG */N#define EMB$C_TS_LENGTH 96 /*LENGTH OF TIME STAMP MSG */N#define EMB$S_EMBTSDEF 96 /* Old size name - synonym */ typedef struct _embts {N unsigned int emb$l_ts_sid; /*SYSTEM ID */N unsigned short int emb$w_ts_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_ts_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_ts_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_ts_dev_class; /* DEVICE CLASS */N unsigned char emb$b_ts_dev_type; /* DEVICE TYPE */N  SCS_NAME_LEN emb$b_ts_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_ts_flags; /* MISC. FLAGS */N unsigned char emb$b_ts_os_id; /* LOGGING OS ID */N unsigned char emb$b_ts_hdrsz; /* HEADER SIZE */N unsigned short int emb$w_ts_entry; /*ENTRY TYPE */N unsigned __int64 emb$q_ts_time; /*TIME IN 64 BITS */N unsigned short int emb$w _ts_errseq; /*ERROR SEQ ! */N unsigned __int64 emb$q_ts_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_ts_errmsk; /* ERROR MASK */N unsigned int emb$l_ts_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_ts_hw_name_len; /* Length of marketing name of this system */N char emb$t_ts_hw_name [31]; /* marketing name of this system */ } EMBTS; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBTSDEF_LOADED */ wwG[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************************************************** //********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:32 by OpenVMS SDL V3.7 */H/* Source: 27-AUG-1993 10:54:31 $1$DGA8345:[LIB_H.SRC]EMBUEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBUEDEF ***/#ifndef __EMBUEDEF_LOADED#define __EMBUEDEF_LOADED 1 G#pragma __ nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/* */N/* ERROR BUFFER FORMAT FOR UNIBUS ERROR SUMMARY REGISTER  */N/* ***** USED ONLY BY 11/730 **** */N/* */N#define EMB$K_UE_LENGTH 100 /*LENGTH OF MESSAGE */N#define EMB$C_UE_LENGTH 100 /*LENGTH OF MESSAGE */N#define EMB$S_EMBUEDEF 100 /* Old size name - synonym */ typedef struct _embue {N unsigned int emb$l_ue_sid; /*SYSTEM ID  */N unsigned short int emb$w_ue_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_ue_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_ue_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_ue_dev_class; /* DEVICE CLASS */N unsigned char emb$b_ue_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_ue_scs_name; /* SCS node name in ASCIC */N  unsigned short int emb$w_ue_flags; /* MISC. FLAGS */N unsigned char emb$b_ue_os_id; /* LOGGING OS ID */N unsigned char emb$b_ue_hdrsz; /* HEADER SIZE */N unsigned short int emb$w_ue_entry; /*ENTRY TYPE */N unsigned __int64 emb$q_ue_time; /*TIME IN 64 BITS */N unsigned short int emb$w_ue_errseq; /*ERROR SEQUENCE NUMBER */N unsigned __int64 emb$q_u e_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_ue_errmsk; /* ERROR MASK */N unsigned int emb$l_ue_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_ue_hw_name_len; /* Length of marketing name of this system */N char emb$t_ue_hw_name [31]; /* marketing name of this system */N unsigned int emb$l_ue_uberr; /*UNIBUS ERROR REGISTER */ } EMBUE; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBUEDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************************************************** //********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:33 by OpenVMS SDL V3.7 */H/* Source: 27-AUG-1993 10:54:52 $1$DGA8345:[LIB_H.SRC]EMBUIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBUIDEF ***/#ifndef __EMBUIDEF_LOADED#define __EMBUIDEF_LOADED 1 G#pragma __ nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/* */N/* UNDEFINED ADAPTER INTERRUPT BUFFER FORMAT  */N/* */N#define EMB$K_UI_LENGTH 104 /*LENGTH OF MESSAGE */N#define EMB$C_UI_LENGTH 104 /*LENGTH OF MESSAGE */N#define EMB$S_EMBUIDEF 104 /* Old size name - synonym */ typedef struct _embui {N unsigned int emb$l_ui_sid; /*SYSTEM ID */N unsigned short int emb$w_ui_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_ui_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_ui_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_ui_dev_class; /* DEVICE CLASS */N unsigned char emb$b_ui_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_ui_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_ui_flags; /* MISC. FLAGS */N  unsigned char emb$b_ui_os_id; /* LOGGING OS ID */N unsigned char emb$b_ui_hdrsz; /* HEADER SIZE */N unsigned short int emb$w_ui_entry; /*ENTRY TYPE */N unsigned __int64 emb$q_ui_time; /*TIME IN 64 BITS */N unsigned short int emb$w_ui_errseq; /*ERROR SEQUENCE NUMBER */N unsigned __int64 emb$q_ui_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_ui_er rmsk; /* ERROR MASK */N unsigned int emb$l_ui_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_ui_hw_name_len; /* Length of marketing name of this system */N char emb$t_ui_hw_name [31]; /* marketing name of this system */N unsigned int emb$l_ui_tr; /*ADAPTER TR NUMBER */S unsigned int emb$l_ui_csr; /*ADAPTER CONGIGURATION STATUS REGISTER */ } EMBUI; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBUIDEF_LOADED */ wwм[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/********************************************************************* ******//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:33 by OpenVMS SDL V3.7 */H/* Source: 27-AUG-1993 10:55:08 $1$DGA8345:[LIB_H.SRC]EMBVMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EMBVMDEF ***/#ifndef __EMBVMDEF_LOADED#define __EMBVMDEF_LOADED 1 G#pra gma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include N/* */N/* VOLUME MOUNT/DISMOUNT MESSAGE TYPE  */N/* */N#define EMB$K_VM_LENGTH 158 /*LENGTH OF BUFFER */N#define EMB$C_VM_LENGTH 158 /*LENGTH OF BUFFER */N#define EMB$S_EMBVMDEF 158 /* Old size name - synonym */ typedef struct _embvm {N unsigned int emb$l_vm_sid; /*SYSTEM ID */N unsigned short int emb$w_vm_hdr_rev; /* HEADER REV LEVEL */N unsigned int emb$l_vm_xsid; /* SYS_TYPE REGISTER */N unsigned int emb$l_vm_cpuid; /* UNIQUE CPU ID */N unsigned char emb$b_vm_dev_class; /* DEVICE CLASS */N unsigned char emb$b_vm_dev_type; /* DEVICE TYPE */N SCS_NAME_LEN emb$b_vm_scs_name; /* SCS node name in ASCIC */N unsigned short int emb$w_vm_flags; /* MISC. FLAGS */N unsigned char emb$b_vm_os_id; /* LOGGING OS ID */N unsigned char emb$b_vm_hdrsz; /* HEADER SIZE */O unsigned short int emb$w_vm_entry; /*ENTRY TYPE = EMB$K_VM OR EMB$K_VD */N unsigned __int64 emb$q_vm_time; /*TIME IN 64 BIT FORMAT */N unsigned short int emb$w_vm_errseq; /*ERROR SEQUENCE NUMBER */N unsigned __int64 emb$q_vm_swvers; /* SOFTWARE VERSION */N unsigned int emb$l_vm_errmsk; /* ERROR MASK */N unsigned int emb$l_vm_abstim; /* CONTENTS OF EXE$GL_ABSTIM */U unsigned char emb$b_vm_hw_name_len; /* Length of marketing name of this system */N char emb$t_vm_hw_name [31]; /* marketing name of this system */N unsigned int emb$l_vm_ownuic; /*OWNER UIC OF THE VOLUME */N unsigned int emb$l_vm_errcnt; /*UNIT ERROR COUNT FROM UCB */N unsigned int emb$l_vm_oprcnt;  /*UNIT OPERATION COUNT FROM UCB */N unsigned short int emb$w_vm_unit; /*DEVICE UNIT NUMBER */N unsigned char emb$b_vm_namlng; /*LENGTH OF DEVICE GENERIC NAME */N char emb$t_vm_namtxt [31]; /*DEVICE GENERIC NAME */N unsigned short int emb$w_vm_volnum; /*VOLUME NUMBER WITHIN SET */N unsigned short int emb$w_vm_numset; /*NUMBER OF VOLUMES WITHIN SET */N char emb$t_vm_label [12]; /*VOLUME LABEL  */ } EMBVM; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EMBVMDEF_LOADED */ ww[UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */F/* Source: 02-AUG-2007 11:35:39 $1$DGA8345:[LIB_H.SRC]EO1DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EO1DEF ***/#ifndef __EO1DEF_LOADED#define __EO1DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* EOF1 ANSI MAGNETIC TAPE LABEL  */N/* THIS IS THE FIRST LABEL IN FILE TRAILER LABEL SET. IT IS EQUIVALENT TO */N/* HDR1 EXCEPT FOR THE FOLLOWING FIELDS. */N/*- */#define EO1$S_EO1DEF 80 typedef struct _eo1 {P unsigned int eo1$l_eo1lid; /*LABEL IDENTIFIER AND NUMBER 'EOF1' */N char eo1def$$_fill_1 [50]; /*SAME AS HDR1 */N char eo1$t_blockcnt [6]; /*BLOCK COUNT */N char eo1def$$_fill_2 [16]; /*SAME AS HDR1 */Q char eo1$t_hiblockcnt [4]; /* HIGH BLOCK COUNT */ } EO1; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EO1DEF_LOADED */ ww2M/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */F/* Source: 09-JUN-1993 15:28:03 $1$DGA8345:[LIB_H.SRC]EO2DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EO2DEF ***/#ifndef __EO2DEF_LOADED#define __EO2DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union #if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* EOF2 ANSI MAGNETIC TAPE LABEL */O/* THIS IS THE SECOND LABEL IN THE FILE TRAILER LABEL SET. IT IS EQUIVALENT */N/* TO HDR2 EXCEPT FOR THE FOLLOWING FIELDS. */N/*- */#define EO2$S_EO2DEF 4 typedef struct _eo2 {P unsigned int eo2$l_eo2lid; /*LABEL IDENTIFIER AND NUMBER 'EOF2' */ } EO2; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EO2DEF_LOADED */ ww M/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc.  **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */F/* Source: 09-JUN-1993 15:29:03 $1$DGA8345:[LIB_H.SRC]EO3DEF.SDL;1 *//******************************************************* *************************************************************************//*** MODULE $EO3DEF ***/#ifndef __EO3DEF_LOADED#define __EO3DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* EOF3 ANSI MAGNETIC TAPE LABEL */N/* THIS IS THE THIRD LABEL IN THE FILE TRAILER LABEL SET. IT IS EQUIVALENT */N/* TO HDR3 EXCEPT FOR THE FOLLOWING FIELDS. */N/*- */#define EO3$S_EO3DEF 4 typedef struct _eo3 {P unsigned int eo3$l_eo3lid; /*LABEL IDENTIFIER AND NUMBER 'EOF3' */ } EO3; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EO3DEF_LOADED */ ww0M/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */F/* Source: 09-JUN-1993 15:29:38 $1$DGA8345:[LIB_H.SRC]EO4DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EO4DEF ***/#ifn def __EO4DEF_LOADED#define __EO4DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* EOF4 ANSI MAGNETIC TA PE LABEL */O/* THIS IS THE FOURTH LABEL IN THE FILE TRAILER LABEL SET. IT IS EQUIVALENT */N/* TO HDR4 EXCEPT FOR THE FOLLOWING FIELDS. */N/*- */#define EO4$S_EO4DEF 4 typedef struct _eo4 {P unsigned int eo4$l_eo4lid; /*LABEL IDENTIFIER AND NUMBER 'EOF4' */ } EO4; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EO4DEF_LOADED */ ww@M/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************** *****************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */F/* Source: 29-JUL-2004 17:28:34 $1$DGA8345:[LIB_H.SRC]ERBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ERBDEF ***/#ifndef __ERBDEF_LOADED#define __ERBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Error Log Recovery Block Header */N/*  */ typedef struct _erb {N unsigned int erb$l_bufpages; /* V5.1 and + : pages / buffer */N unsigned int erb$l_bufcnt; /* # buffers, not incl crash buf */N unsigned int erb$l_block_size; /* Returned by allocation */N unsigned int erb$l_allocated; /* Bytes alloc'd for this block */N unsigned int erb$l_head; /* Ring head index at crash */N unsigned int erb$l_tail; /* Ring tail index at crash */ } ERB;#define ERB$C_LENGTH 24#define ERB$K_LENGTH 24#define S_ERBDEF 24 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ERBDEF_LOADED */ ww`[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by OpenVMS SDL V3.7 */I/* Source: 29-JUL-2005 10:29:41 $1$DGA8345:[LIB_H.SRC]ERFMBXDEF.SDL;1 *//******************************************************************************* *************************************************//*** MODULE $ERFMBXDEF ***/#ifndef __ERFMBXDEF_LOADED#define __ERFMBXDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*  */N/* COMPLEMENTARY STRUCTURES FOR ERRFMT DIAGNOSTIC MAILBOX CONTROL */N/* */N#define ERF$K_MBX_LENGTH 8 /* LENGTH OF STRUCTURE */N#define ERF$C_MBX_LENGTH 8 /* LENGTH OF STRUCTURE */ typedef struct _erfmbx {N unsigned short int erf$w_mbx_channel; /* MBX CHANNEL NUMBER */N unsigned short int erf$w_mbx_size; /* MBX SIZE */N unsigned int erf$l_mbx_unit; /* MBX UNIT NUMBER */ } ERFMBX; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ERFMBXDEF_LOADED */ wwpC[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by OpenVMS SDL V3.7 */F/* Source: 30-JUL-2004 08:47:53 $1$DGA8345:[LIB_H.SRC]ERLDEF.SDL;1 *//********************************* ***********************************************************************************************//*** MODULE $ERLDEF ***/#ifndef __ERLDEF_LOADED#define __ERLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Error Log Buffer Header */N/* */#define ERL$M_LOCK 0x1#define ERL$M_TIMER 0x2 typedef struct _erl {N unsigned char erl$b_busy; /* For compatibility purposes */N unsigned char erl$b_msgcnt; /* For compatibility purposes */N unsigned char erl$b_bufind; /* For compatibility purposes */ __union {N unsigned char erl$b_flags; /* Buffer control flags */ __struct {N unsigned erl$v_lock : 1; /* Buffer allocation interlock */N unsigned erl$v_timer : 1; /* Timer active */' unsigned erl$v_fill_0_ : 6; } erl$r_flags_bits; } erl$r_flags_overlay; __union {N void *erl$l_next;  /* For compatibility purposes */R unsigned int erl$l_compat; /* Used for compatibility determination */ } erl$r_next_overlay;N void *erl$l_end; /* For compatibility purposes */O unsigned int erl$l_busy; /* Number of busy messages in buffer */T unsigned int erl$l_msgcnt; /* Number of completed messages in buffer */S unsigned int erl$l_bufind; /* Buffer indicator of respective buffer */R#ifd ef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */W void *erl$q_next; /* Address of next available space in buffer */#else unsigned __int64 erl$q_next;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *erl$q_end; /* Address of end of buffer + 1 */#else unsigned __int64 erl$q_end;#endif } ERL; #if !defined(__VAXC)3#define erl$b_flags erl$r_flags_overlay.erl$b_flagsB#define erl$v_lock erl$r_flags_overlay.erl$r_flags_bits.erl$v_lockD#define erl$v_timer erl$r_flags_overlay.erl$r_flags_bits.erl$v_timer0#define erl$l_next erl$r_next_overlay.erl$l_next4#define erl$l_compat erl$r_next_overlay.erl$l_compat"#endif /* #if !defined(__VAXC) */ #define ERL$C_LENGTH 40#define ERL$K_LENGTH 40#define S_ERLDEF 40 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ERLDEF_LOADED */ wwj[UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by OpenVMS SDL V3.7 */I/* Source: 31-JUL-2005 02:50:42 $1$DGA8345:[LIB_H.SRC]ERLMBXDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ERLMBXD EF ***/#ifndef __ERLMBXDEF_LOADED#define __ERLMBXDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* ERR OR LOG MAILBOX SYSTEM DATA CELL STRUCTURE AND MAILBOX COUNT */N/* */N#define ERL$K_MAILBOX_COUNT 5 /* NUMBER OF MAILBOXES */N#define ERL$C_MAILBOX_COUNT 5 /* NUMBER OF MAILBOXES */N#define ERL$K_MBX_LENGTH 8 /* LENGTH OF STRUCTURE */N#define ERL$C_MBX_LENGTH 8 /* LENGTH OF STRUCTURE */ typedef struct _erlmbx {N  unsigned int erl$l_mbx_unt; /* MAILBOX UNIT NUMBER */N unsigned int erl$l_mbx_pid; /* MBX OWNER PID */ } ERLMBX; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ERLMBXDEF_LOADED */  ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by OpenVMS SDL V3.7 */F/* Source: 11-MAY-1994 16:51:24 $1$DGA8345:[LIB_H.SRC]EV4DEF.SDL;1 *//************************* *******************************************************************************************************//*** MODULE $EV4DEF ***/#ifndef __EV4DEF_LOADED#define __EV4DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define EV4$M_SWC 0x4#define EV4$M_INV 0x8#define EV4$M_DZE 0x10#define EV4$M_FOV 0x20#define EV4$M_UNF 0x40#define EV4$M_INE 0x80#define EV4$M_IOV 0x100#define EV4$M_MSK 0x200000000#define EV4$M_WR 0x1#define EV4$M_ACV 0x2#define EV4$M_FOR 0x4#define EV4$M_FOW 0x8#define EV4$M_RA_OPERAND 0x1F0#define EV4$M_OPCODE 0x7E00#define EV4$M_BIU_HERR 0x1#define EV4$M_BIU_SERR 0x2#define EV4$M_BC_TPERR 0x4#define EV4$M_BC_TCPERR 0x8#define EV4$M_BIU_CMD 0x70#define EV4$M_BIU_SEO 0x80#define EV4$M_FILL_ECC 0x100#define EV4$M_BIU_DPERR 0x400#define EV4$M_FILL_IRD 0x800#define EV4$M_FILL_QW 0x3000#define EV4$M_FILL_SEO 0x4000#define EV4$M_DC_HIT 0x8#define EV4$M_DC_ERR 0x10#define EV4$M_IC_ERR 0x20N#define EV4$S_EV4DEF 8 /* Old size name - synonym */ typedef struct _ev4 { __union { __union {+ unsigned __int64 ev4$q_exc_sum; __struct {*  unsigned ev4$v_fill_1 : 2;' unsigned ev4$v_swc : 1;' unsigned ev4$v_inv : 1;' unsigned ev4$v_dze : 1;' unsigned ev4$v_fov : 1;' unsigned ev4$v_unf : 1;' unsigned ev4$v_ine : 1;' unsigned ev4$v_iov : 1;+ unsigned ev4$v_fill_2 : 24;' unsigned ev4$v_msk : 1;+ unsigned ev4$v_fill_3 : 30;% } ev4$r_exc_sum_bi ts;$ } ev4$r_exc_sum_overlay; __union {* unsigned __int64 ev4$q_mm_csr; __struct {& unsigned ev4$v_wr : 1;' unsigned ev4$v_acv : 1;' unsigned ev4$v_for : 1;' unsigned ev4$v_fow : 1;. unsigned ev4$v_ra_operand : 5;* unsigned ev4$v_opcode : 6;- unsigned ev4$v_fill_4_1 : 32;- unsigned ev4$v_fill_4_2 : 17;$ } ev4$r_mm_csr_bits;# } ev4$r_mm_csr_overlay; __union {, unsigned __int64 ev4$q_biu_stat; __struct {, unsigned ev4$v_biu_herr : 1;, unsigned ev4$v_biu_serr : 1;, unsigned ev4$v_bc_tperr : 1;- unsigned ev4$v_bc_tcperr : 1;+ unsigned ev4$v_biu_cmd : 3;+ unsigned ev4$v_biu_seo : 1;, unsigned ev4$v_fill_ecc : 1;* unsigned ev4$v_f ill_5 : 1;- unsigned ev4$v_biu_dperr : 1;, unsigned ev4$v_fill_ird : 1;+ unsigned ev4$v_fill_qw : 2;, unsigned ev4$v_fill_seo : 1;- unsigned ev4$v_fill_6_1 : 32;- unsigned ev4$v_fill_6_2 : 17;& } ev4$r_biu_stat_bits;% } ev4$r_biu_stat_overlay; __union {+ unsigned __int64 ev4$q_dc_stat; __struct {+ unsigned ev4$v_chip_id :  3;* unsigned ev4$v_dc_hit : 1;* unsigned ev4$v_dc_err : 1;* unsigned ev4$v_ic_err : 1;+ unsigned ev4$v_fill_0_ : 2;% } ev4$r_dc_stat_bits;$ } ev4$r_dc_stat_overlay; } ev4$r_ev4_overlay; } EV4; #if !defined(__VAXC)K#define ev4$q_exc_sum ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$q_exc_sum\#define ev4$v_fill_1 ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$r_exc_sum_bits.ev4$v_fill_1V#define ev4$v_swc ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$r_exc_sum_bits.ev4$v_swcV#define ev4$v_inv ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$r_exc_sum_bits.ev4$v_invV#define ev4$v_dze ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$r_exc_sum_bits.ev4$v_dzeV#define ev4$v_fov ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$r_exc_sum_bits.ev4$v_fovV#define ev4$v_unf ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$r_exc_sum_bits.ev4$v_unfV#define ev4$v_ine ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$r_exc_sum_bits.ev4$v_ineV#define ev4$v_iov ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$r_exc_sum_bits.ev4$v_iov\#define ev4$v_fill_2 ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$r_exc_sum_bits.ev4$v_fill_2V#define ev4$v_msk ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$r_exc_sum_bits.ev4$v_msk\#define ev4$v_fill_3 ev4$r_ev4_overlay.ev4$r_exc_sum_overlay.ev4$r_exc_sum_bits.ev4$v_fill_3H#define ev4$q_mm_csr ev4$r_ev4_overlay.ev4$r_mm_csr_overlay.ev4$q_mm_csrR#define ev4$v_wr ev4$r_ev4_overlay.ev4$r_mm_csr_overlay.ev4$r_mm_csr_bits.ev4$v_wrT#define ev4$v_acv ev4$r_ev4_overlay.ev4$r_mm_csr_overlay.ev4$r_mm_csr_bits.ev4$v_acvT#define ev4$v_for ev4$r_ev4_overlay.ev4$r_mm_csr_overlay.ev4$r_mm_csr_bits.ev4$v_forT#define ev4$v_fow ev4$r_ev4_overlay.ev4$r_mm_csr_overlay.ev4$r_mm_csr_bits.ev4$v_fowb#define ev4$v_ra_operand ev4$r_ev4_overlay.ev4$r_mm_csr_overlay.ev4$r_mm_csr_bits.ev4$v_ra_operandZ#define ev4$v_opcode ev4$r_ev4_overlay.ev4$r_mm_csr_overlay.ev4$r_mm_csr_bits.ev4$v_opcodeN#define ev4$q_biu_stat ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$q_biu_statb#define ev4$v_biu_herr ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_biu_herrb#define ev4$v_biu_serr ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_biu_serrb#define ev4$v_bc_tperr ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_bc_tperrd#define ev4$v_bc_tcperr ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_bc_tcperr`#define ev4$v_biu_cmd ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_biu_cmd`#define ev4$v_biu_seo ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_biu_seob#define ev4$v_fill_ecc ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_fill_ecc^#define ev4$v_fill_5 ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_fill_5d#define ev4$v_biu_dperr ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_biu_dperrb#define ev4$v_fill_ird ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_fill_ird`#define ev4$v_fill_qw ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_fill_qwb#define ev4$v_fill_seo ev4$r_ev4_overlay.ev4$r_biu_stat_overlay.ev4$r_biu_stat_bits.ev4$v_fill_seoK#define ev4$q_dc_stat ev4$r_ev4_overlay.ev4$r_dc_stat_overlay.ev4$q_dc_stat^#define ev4$v_chip_id ev4$r_ev4_overlay.ev4$r_dc_stat_overlay.ev4$r_dc_stat_bits.ev4$v_chip_id\#define ev4$v_dc_hit ev4$r_ev4_overlay.ev4$r_dc_stat_overlay.ev4$r_dc_stat_bits.ev4$v_dc_hit \#define ev4$v_dc_err ev4$r_ev4_overlay.ev4$r_dc_stat_overlay.ev4$r_dc_stat_bits.ev4$v_dc_err\#define ev4$v_ic_err ev4$r_ev4_overlay.ev4$r_dc_stat_overlay.ev4$r_dc_stat_bits.ev4$v_ic_err"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragm a __standard #endif /* __EV4DEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc.  **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by OpenVMS SDL V3.7 */F/* Source: 09-OCT-1994 20:08:51 $1$DGA8345:[L IB_H.SRC]EV5DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EV5DEF ***/#ifndef __EV5DEF_LOADED#define __EV5DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save  /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define EV5$M_SWC 0x400#define EV5$M_INV 0x800#define EV5$M_DZE 0x1000#define EV5$M_FOV 0x2000#define EV5$M_UNF 0x4000#define EV5$M_INE 0x8000#define EV5$M_IOV 0x10000#define EV5$M_WR 0x1#define EV5$M_ACV 0x2#define EV5$M_FOR 0x4#define EV5$M_FOW 0x8#define EV5$M_DTB_MISS 0x10#define EV5$M_BAD_VA 0x20#define EV5$M_RA_OPERAND 0x7C0#define EV5$M_OPCODE 0x1F800#define EV5$M_CHIP_ID 0xF000000!#define EV5$M_BC_TPERR 0x10000000##define EV5$M_BC_TC_PERR 0x20000000#define EV5$M_EI_ES 0x40000000$#define EV5$M_COR_ECC_ERR 0x80000000#define EV5$M_UNC_ECC_ERR 0x1#define EV5$M_EI_PAR_ERR 0x2#define EV5$M_FIL_IRD 0x4#define EV5$M_SEO_HRD_ERR 0x8#define EV5$M_DPE 0x800#define EV5$M_TPE 0x1000#define EV5$M_TMR 0x2000#define EV5$M_SEO 0x1#define EV5$M_LOCK 0x2#define EV5$M_DP0 0x4#define EV5$M_DP1 0x8#define EV5$M_TP0 0x10#define EV5$M_TP1 0x20N#define EV5$S_EV5DEF 8 /* Old size name - synonym */ typedef struct _ev5 { __union { __union {+ unsigned __int64 ev5$q_exc_sum; __struct {1 unsigned ev5$v_exc_sum_fill : 10;' unsigned ev5$v_swc : 1;' unsigned ev5$v_inv : 1;' unsigned ev5$v_dze : 1;' unsigned ev5$v_fov : 1;' unsigned ev5$v_unf : 1;' unsigned ev5$v_ine : 1;' unsigned ev5$v_iov : 1;+ unsigned ev5$v_fill_8_ : 7;% } ev5$r_exc_sum_bits;$ } ev5$r_exc_sum_overlay; __union {+ unsigned __int64 ev5$q_mm_stat; __struct {& unsigned ev5$v_wr : 1;' unsigned ev5$v_acv : 1;' unsigned ev5$v_for : 1;' unsigned ev5$v_fow : 1;, unsigned ev5$v_dtb_miss : 1;* unsigned ev5$v_bad_va : 1;. unsigned ev5$v_ra_operand : 5;* unsigned ev5$v_opcode : 6;+ unsigned ev5$v_fill_9_ : 7;% } ev5$r_mm_stat_bits;$ } ev5$r_mm_stat_overlay; __union {+ unsigned __int64 ev5$q_ei_stat; __struct { __union { int ev5$l_l; __struct {9 unsigned ev5$v_ei_stat_fill : 24;3 unsi gned ev5$v_chip_id : 4;4 unsigned ev5$v_bc_tperr : 1;6 unsigned ev5$v_bc_tc_perr : 1;1 unsigned ev5$v_ei_es : 1;7 unsigned ev5$v_cor_ecc_err : 1;( } ev5$r_fill_1_;$ } ev5$r_fill_0_; __union { int ev5$l_h; __struct {7 unsigned ev5$v_unc_ecc_err : 1;6 un signed ev5$v_ei_par_err : 1;3 unsigned ev5$v_fil_ird : 1;7 unsigned ev5$v_seo_hrd_err : 1;4 unsigned ev5$v_fill_10_ : 4;( } ev5$r_fill_3_;$ } ev5$r_fill_2_;' } ev5$r_ei_stat_halves;$ } ev5$r_ei_stat_overlay; __union {& __int64 ev5$q_icperr_stat; __struct {5 unsigned ev5$v_icperr_stat_fill : 11;' ! unsigned ev5$v_dpe : 1;' unsigned ev5$v_tpe : 1;' unsigned ev5$v_tmr : 1;, unsigned ev5$v_fill_11_ : 2; } ev5$r_fill_5_; } ev5$r_fill_4_; __union {& __int64 ev5$q_dcperr_stat; __struct {' unsigned ev5$v_seo : 1;( unsigned ev5$v_lock : 1;' unsigned ev5$v_dp0 : 1;' unsigned ev5$v_dp1 : 1;' unsigned " ev5$v_tp0 : 1;' unsigned ev5$v_tp1 : 1;, unsigned ev5$v_fill_12_ : 2; } ev5$r_fill_7_; } ev5$r_fill_6_; } ev5$r_ev5_overlay; } EV5; #if !defined(__VAXC)K#define ev5$q_exc_sum ev5$r_ev5_overlay.ev5$r_exc_sum_overlay.ev5$q_exc_sumV#define ev5$v_swc ev5$r_ev5_overlay.ev5$r_exc_sum_overlay.ev5$r_exc_sum_bits.ev5$v_swcV#define ev5$v_inv ev5$r_ev5_overlay.ev5$r_exc_sum_overlay.ev5$r_exc_sum_bits.ev5$v_invV#define ev5$v_#dze ev5$r_ev5_overlay.ev5$r_exc_sum_overlay.ev5$r_exc_sum_bits.ev5$v_dzeV#define ev5$v_fov ev5$r_ev5_overlay.ev5$r_exc_sum_overlay.ev5$r_exc_sum_bits.ev5$v_fovV#define ev5$v_unf ev5$r_ev5_overlay.ev5$r_exc_sum_overlay.ev5$r_exc_sum_bits.ev5$v_unfV#define ev5$v_ine ev5$r_ev5_overlay.ev5$r_exc_sum_overlay.ev5$r_exc_sum_bits.ev5$v_ineV#define ev5$v_iov ev5$r_ev5_overlay.ev5$r_exc_sum_overlay.ev5$r_exc_sum_bits.ev5$v_iovK#define ev5$q_mm_stat ev5$r_ev5_overlay.ev5$r_mm_stat_overlay.ev5$q_mm_statT#d$efine ev5$v_wr ev5$r_ev5_overlay.ev5$r_mm_stat_overlay.ev5$r_mm_stat_bits.ev5$v_wrV#define ev5$v_acv ev5$r_ev5_overlay.ev5$r_mm_stat_overlay.ev5$r_mm_stat_bits.ev5$v_acvV#define ev5$v_for ev5$r_ev5_overlay.ev5$r_mm_stat_overlay.ev5$r_mm_stat_bits.ev5$v_forV#define ev5$v_fow ev5$r_ev5_overlay.ev5$r_mm_stat_overlay.ev5$r_mm_stat_bits.ev5$v_fow`#define ev5$v_dtb_miss ev5$r_ev5_overlay.ev5$r_mm_stat_overlay.ev5$r_mm_stat_bits.ev5$v_dtb_miss\#define ev5$v_bad_va ev5$r_ev5_overlay.ev5$r_mm_stat_overlay%.ev5$r_mm_stat_bits.ev5$v_bad_vad#define ev5$v_ra_operand ev5$r_ev5_overlay.ev5$r_mm_stat_overlay.ev5$r_mm_stat_bits.ev5$v_ra_operand\#define ev5$v_opcode ev5$r_ev5_overlay.ev5$r_mm_stat_overlay.ev5$r_mm_stat_bits.ev5$v_opcodeK#define ev5$q_ei_stat ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$q_ei_statb#define ev5$l_l ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$r_ei_stat_halves.ev5$r_fill_0_.ev5$l_l|#define ev5$v_chip_id ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$r_ei_stat_halves.ev5$r_fill_0_.e&v5$r_fill_1_.ev5$v_chip_id~#define ev5$v_bc_tperr ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$r_ei_stat_halves.ev5$r_fill_0_.ev5$r_fill_1_.ev5$v_bc_tperr#define ev5$v_bc_tc_perr ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$r_ei_stat_halves.ev5$r_fill_0_.ev5$r_fill_1_.ev5$v_bc_tc_perrx#define ev5$v_ei_es ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$r_ei_stat_halves.ev5$r_fill_0_.ev5$r_fill_1_.ev5$v_ei_es#define ev5$v_cor_ecc_err ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$r_ei_stat_halves.ev5$r_fil'l_0_.ev5$r_fill_1_.ev5$v_cor_ecc_errb#define ev5$l_h ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$r_ei_stat_halves.ev5$r_fill_2_.ev5$l_h#define ev5$v_unc_ecc_err ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$r_ei_stat_halves.ev5$r_fill_2_.ev5$r_fill_3_.ev5$v_unc_ecc_err#define ev5$v_ei_par_err ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$r_ei_stat_halves.ev5$r_fill_2_.ev5$r_fill_3_.ev5$v_ei_par_err|#define ev5$v_fil_ird ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$r_ei_stat_halves.ev5$r_fill_2_.ev5$r(_fill_3_.ev5$v_fil_ird#define ev5$v_seo_hrd_err ev5$r_ev5_overlay.ev5$r_ei_stat_overlay.ev5$r_ei_stat_halves.ev5$r_fill_2_.ev5$r_fill_3_.ev5$v_seo_hrd_errK#define ev5$q_icperr_stat ev5$r_ev5_overlay.ev5$r_fill_4_.ev5$q_icperr_statI#define ev5$v_dpe ev5$r_ev5_overlay.ev5$r_fill_4_.ev5$r_fill_5_.ev5$v_dpeI#define ev5$v_tpe ev5$r_ev5_overlay.ev5$r_fill_4_.ev5$r_fill_5_.ev5$v_tpeI#define ev5$v_tmr ev5$r_ev5_overlay.ev5$r_fill_4_.ev5$r_fill_5_.ev5$v_tmrK#define ev5$q_dcperr_stat ev5$r_ev5_overla)y.ev5$r_fill_6_.ev5$q_dcperr_statI#define ev5$v_seo ev5$r_ev5_overlay.ev5$r_fill_6_.ev5$r_fill_7_.ev5$v_seoK#define ev5$v_lock ev5$r_ev5_overlay.ev5$r_fill_6_.ev5$r_fill_7_.ev5$v_lockI#define ev5$v_dp0 ev5$r_ev5_overlay.ev5$r_fill_6_.ev5$r_fill_7_.ev5$v_dp0I#define ev5$v_dp1 ev5$r_ev5_overlay.ev5$r_fill_6_.ev5$r_fill_7_.ev5$v_dp1I#define ev5$v_tp0 ev5$r_ev5_overlay.ev5$r_fill_6_.ev5$r_fill_7_.ev5$v_tp0I#define ev5$v_tp1 ev5$r_ev5_overlay.ev5$r_fill_6_.ev5$r_fill_7_.ev5$v_tp1"#endif /* #*if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EV5DEF_LOADED */ ww-[UM/***************************************************************************/M/** + **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** , **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*****************-**********************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by OpenVMS SDL V3.7 */J/* Source: 30-MAR-1998 16:28:31 $1$DGA8345:[LIB_H.SRC]EV6MCHKDEF.SDL;1 *//********************************************************************************************************************************/%/*** MODULE ev6mchkdef IDENT X-2 ***/ .#ifndef __EV6MCHKDEF_LOADED#define __EV6MCHKDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cpluspl/us extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Define th0e field offsets for the machine check logout area */N/* */N/* NOTE: */N/* *********** */N/* Do not add the contents of the "cpu_offset" field in the header to the */R/* base pointer of the logout area in order to access the cpu data. This is one */N/* contiguous structure, not a uni1on, so the offset to the cpu data is not */N/* necessary. The base pointer typecast to (MCK *) will be able to directly */N/* access the cpu data. */N/* */N/* For example: */N/* */U/* The following is the correct way to access data in the cp2u-specific area of the */N/* logout. */N/* */I/* MCK *mck; */I/* uint64 dc_stat; */I/* : */I/* mck = (MCK *)logout_va; */I/* dc_stat = m3ck->mck$q_dc_stat; */N/* */S/* The following is the WRONG way to access data in the cpu-specific area of the */N/* logout. */N/* */I/* MCK *mck; */I/* MCK *cpu_data; 4 */I/* uint64 dc_stat; */I/* : */I/* mck = (MCK *)logout_va; */I/* cpu_data = (MCK *)((int)logout_va + mck->mck$l_cpu_offset); */I/* dc_stat = cpu_data->mck$q_dc_stat; */N/* */N/* 5 */N#define MCK$K_CORRECTABLE_CPU_FRAME_SIZE 88 /* 0x58 */N/* */N#define MCK$K_UNCORRECTABLE_CPU_FRAME_SIZE 160 /* 0xA0 */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftype 6def struct _mck {N __struct { /* offset 0x0 */#pragma __nomember_alignment __union {N/* */N/* frame_base can be used as explicit qw pointer to base of mchk frame */N/* */N unsigned __int64 mck$q_frame_base; /* 0x0 */ __union {- 7 unsigned __int64 mck$q_frame; __struct {Z unsigned int mck$l_frame_size; /* 0x0 Size of logout frame in bytes */ __union {N int mck$l_frame_flags; /* 0x4 */# __struct {> unsigned mck$v_ff_reserved_0 : 28;8 unsigned mck$v_scrubbed : 1;: unsigned mck$v_diagnostic : 1;X 8 unsigned mck$v_second_error : 1; /* Second error occurred */N unsigned mck$v_retry : 1; /* Retry bit */, } mck$r_fill_3_;( } mck$r_fill_2_;$ } mck$r_fill_1_; } mck$r_fill_0_;" } mck$r_frame_overlay;N unsigned int mck$l_cpu_offset; /* 0x08 Offset to cpu specific info */P unsigned int mck$l_system_offset; /* 0x0c Offset to sys specific inf9o */O unsigned int mck$l_code; /* 0x10 PAL-determined cause for mck */N unsigned int mck$l_frame_rev; /* 0x14 Mchk frame revision */ } mck$r_header;N/* */N/* */N/* Processor specific segment of logout frame */N/* : */N/* Because the correctable and uncorrectable frames have the same first 8 */N/* quadwords of information in common, the uncorrectable frame is built as */N/* an extension to, rather than in union with, the correctable frame. */N/* */N/* The reason for providing both quadword and longword abstracts of each */N/* register is to allow power-on debug print routines to access each */N/* longword separa ;tely, as I don't think that 64-bit format support has */N/* been extended to our kprintf() routine. */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __struct {#pragma __nomember_alignment __union {N unsigned __int <64 mck$q_i_stat; /* 0x18 */ __struct {, unsigned int mck$l_i_stat_0;, unsigned int mck$l_i_stat_1; } mck$r_fill_5_; } mck$r_fill_4_; __union {N unsigned __int64 mck$q_dc_stat; /* 0x20 */ __struct {- unsigned int mck$l_dc_stat_0;- unsigned int mck$l_dc_stat_1; } mck$r_fill_7_; } =mck$r_fill_6_; __union {N unsigned __int64 mck$q_c_addr; /* 0x28 */ __struct {, unsigned int mck$l_c_addr_0;, unsigned int mck$l_c_addr_1; } mck$r_fill_9_; } mck$r_fill_8_; __union {N unsigned __int64 mck$q_dc1_syndrome; /* 0x30 */ __struct {2 unsigned int mck$l_dc1_syndrome_0;2 unsigned int m >ck$l_dc1_syndrome_1;! } mck$r_fill_11_; } mck$r_fill_10_; __union {N unsigned __int64 mck$q_dc0_syndrome; /* 0x38 */ __struct {2 unsigned int mck$l_dc0_syndrome_0;2 unsigned int mck$l_dc0_syndrome_1;! } mck$r_fill_13_; } mck$r_fill_12_; __union {N unsigned __int64 mck$q_c_stat; /* 0x40 */ __stru?ct {, unsigned int mck$l_c_stat_0;, unsigned int mck$l_c_stat_1;! } mck$r_fill_15_; } mck$r_fill_14_; __union {N unsigned __int64 mck$q_c_sts; /* 0x48 */ __struct {+ unsigned int mck$l_c_sts_0;+ unsigned int mck$l_c_sts_1;! } mck$r_fill_17_; } mck$r_fill_16_; __union {N unsigned __int64 mck @$q_mm_stat; /* 0x50 */ __struct {- unsigned int mck$l_mm_stat_0;- unsigned int mck$l_mm_stat_1;! } mck$r_fill_19_; } mck$r_fill_18_; } mck$r_correctable;N/* */N/* This is the uncorrectable processor-specific part of the logout frame. */N/* For EV6, it simply picks up where the correctable frame leaves off. */ AN/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __struct { /* 0x58 */#pragma __nomember_alignment __union {N unsigned __int64 mck$q_exc_addr; /* 0x58 */ __struct { B. unsigned int mck$l_exc_addr_0;. unsigned int mck$l_exc_addr_1;! } mck$r_fill_21_; } mck$r_fill_20_; __union {N unsigned __int64 mck$q_ier_cm; /* 0x60 */ __struct {, unsigned int mck$l_ier_cm_0;, unsigned int mck$l_ier_cm_1;! } mck$r_fill_23_; } mck$r_fill_22_; __union {N unsigned __int64 mck$q C_isum; /* 0x68 */ __struct {* unsigned int mck$l_isum_0;* unsigned int mck$l_isum_1;! } mck$r_fill_25_; } mck$r_fill_24_;N unsigned __int64 mck$q_u_reserved_0; /* 0x70 */ __union {N unsigned __int64 mck$q_pal_base; /* 0x78 */ __struct {. unsigned int mck$l_pal_base_0;. unsignedD int mck$l_pal_base_1;! } mck$r_fill_27_; } mck$r_fill_26_; __union {N unsigned __int64 mck$q_i_ctl; /* 0x80 */ __struct {+ unsigned int mck$l_i_ctl_0;+ unsigned int mck$l_i_ctl_1;! } mck$r_fill_29_; } mck$r_fill_28_; __union {N unsigned __int64 mck$q_pctx; /* 0x88 */ __struct {* E unsigned int mck$l_pctx_0;* unsigned int mck$l_pctx_1;! } mck$r_fill_31_; } mck$r_fill_30_;N unsigned __int64 mck$q_u_reserved_1; /* 0x90 */N unsigned __int64 mck$q_u_reserved_2; /* 0x98 */ } mck$r_uncorrectable; } MCK; #if !defined(__VAXC)J#define mck$q_frame_base mck$r_header.mck$r_frame_overlay.mck$q_frame_basef#define mck$l_frame_size mck$r_header.mck$r_frFame_overlay.mck$r_fill_0_.mck$r_fill_1_.mck$l_frame_sizev#define mck$l_frame_flags mck$r_header.mck$r_frame_overlay.mck$r_fill_0_.mck$r_fill_1_.mck$r_fill_2_.mck$l_frame_flags~#define mck$v_scrubbed mck$r_header.mck$r_frame_overlay.mck$r_fill_0_.mck$r_fill_1_.mck$r_fill_2_.mck$r_fill_3_.mck$v_scrubbed#define mck$v_diagnostic mck$r_header.mck$r_frame_overlay.mck$r_fill_0_.mck$r_fill_1_.mck$r_fill_2_.mck$r_fill_3_.mck$v_diagnostic#define mck$v_second_error mck$r_header.mck$r_frame_overlay.mck$r_fi Gll_0_.mck$r_fill_1_.mck$r_fill_2_.mck$r_fill_3_.mck$v_second_er\rorx#define mck$v_retry mck$r_header.mck$r_frame_overlay.mck$r_fill_0_.mck$r_fill_1_.mck$r_fill_2_.mck$r_fill_3_.mck$v_retry6#define mck$l_cpu_offset mck$r_header.mck$l_cpu_offset<#define mck$l_system_offset mck$r_header.mck$l_system_offset*#define mck$l_code mck$r_header.mck$l_code4#define mck$l_frame_rev mck$r_header.mck$l_frame_revA#define mck$q_i_stat mck$r_correctable.mck$r_fill_4_.mck$q_i_statS#define mck$l_i_stat_0 mck$rH_correctable.mck$r_fill_4_.mck$r_fill_5_.mck$l_i_stat_0S#define mck$l_i_stat_1 mck$r_correctable.mck$r_fill_4_.mck$r_fill_5_.mck$l_i_stat_1C#define mck$q_dc_stat mck$r_correctable.mck$r_fill_6_.mck$q_dc_statU#define mck$l_dc_stat_0 mck$r_correctable.mck$r_fill_6_.mck$r_fill_7_.mck$l_dc_stat_0U#define mck$l_dc_stat_1 mck$r_correctable.mck$r_fill_6_.mck$r_fill_7_.mck$l_dc_stat_1A#define mck$q_c_addr mck$r_correctable.mck$r_fill_8_.mck$q_c_addrS#define mck$l_c_addr_0 mck$r_correctable.mck$r_fIill_8_.mck$r_fill_9_.mck$l_c_addr_0S#define mck$l_c_addr_1 mck$r_correctable.mck$r_fill_8_.mck$r_fill_9_.mck$l_c_addr_1N#define mck$q_dc1_syndrome mck$r_correctable.mck$r_fill_10_.mck$q_dc1_syndromea#define mck$l_dc1_syndrome_0 mck$r_correctable.mck$r_fill_10_.mck$r_fill_11_.mck$l_dc1_syndrome_0a#define mck$l_dc1_syndrome_1 mck$r_correctable.mck$r_fill_10_.mck$r_fill_11_.mck$l_dc1_syndrome_1N#define mck$q_dc0_syndrome mck$r_correctable.mck$r_fill_12_.mck$q_dc0_syndromea#define mck$l_dc0_syndJrome_0 mck$r_correctable.mck$r_fill_12_.mck$r_fill_13_.mck$l_dc0_syndrome_0a#define mck$l_dc0_syndrome_1 mck$r_correctable.mck$r_fill_12_.mck$r_fill_13_.mck$l_dc0_syndrome_1B#define mck$q_c_stat mck$r_correctable.mck$r_fill_14_.mck$q_c_statU#define mck$l_c_stat_0 mck$r_correctable.mck$r_fill_14_.mck$r_fill_15_.mck$l_c_stat_0U#define mck$l_c_stat_1 mck$r_correctable.mck$r_fill_14_.mck$r_fill_15_.mck$l_c_stat_1@#define mck$q_c_sts mck$r_correctable.mck$r_fill_16_.mck$q_c_stsS#define mck$l_c_stKs_0 mck$r_correctable.mck$r_fill_16_.mck$r_fill_17_.mck$l_c_sts_0S#define mck$l_c_sts_1 mck$r_correctable.mck$r_fill_16_.mck$r_fill_17_.mck$l_c_sts_1D#define mck$q_mm_stat mck$r_correctable.mck$r_fill_18_.mck$q_mm_statW#define mck$l_mm_stat_0 mck$r_correctable.mck$r_fill_18_.mck$r_fill_19_.mck$l_mm_stat_0W#define mck$l_mm_stat_1 mck$r_correctable.mck$r_fill_18_.mck$r_fill_19_.mck$l_mm_stat_1H#define mck$q_exc_addr mck$r_uncorrectable.mck$r_fill_20_.mck$q_exc_addr[#define mck$l_exc_addr_0 mckL$r_uncorrectable.mck$r_fill_20_.mck$r_fill_21_.mck$l_exc_addr_0[#define mck$l_exc_addr_1 mck$r_uncorrectable.mck$r_fill_20_.mck$r_fill_21_.mck$l_exc_addr_1D#define mck$q_ier_cm mck$r_uncorrectable.mck$r_fill_22_.mck$q_ier_cmW#define mck$l_ier_cm_0 mck$r_uncorrectable.mck$r_fill_22_.mck$r_fill_23_.mck$l_ier_cm_0W#define mck$l_ier_cm_1 mck$r_uncorrectable.mck$r_fill_22_.mck$r_fill_23_.mck$l_ier_cm_1@#define mck$q_isum mck$r_uncorrectable.mck$r_fill_24_.mck$q_isumS#define mck$l_isum_0 mck$r_uncMorrectable.mck$r_fill_24_.mck$r_fill_25_.mck$l_isum_0S#define mck$l_isum_1 mck$r_uncorrectable.mck$r_fill_24_.mck$r_fill_25_.mck$l_isum_1H#define mck$q_pal_base mck$r_uncorrectable.mck$r_fill_26_.mck$q_pal_base[#define mck$l_pal_base_0 mck$r_uncorrectable.mck$r_fill_26_.mck$r_fill_27_.mck$l_pal_base_0[#define mck$l_pal_base_1 mck$r_uncorrectable.mck$r_fill_26_.mck$r_fill_27_.mck$l_pal_base_1B#define mck$q_i_ctl mck$r_uncorrectable.mck$r_fill_28_.mck$q_i_ctlU#define mck$l_i_ctl_0 mck$r_uncorr Nectable.mck$r_fill_28_.mck$r_fill_29_.mck$l_i_ctl_0U#define mck$l_i_ctl_1 mck$r_uncorrectable.mck$r_fill_28_.mck$r_fill_29_.mck$l_i_ctl_1@#define mck$q_pctx mck$r_uncorrectable.mck$r_fill_30_.mck$q_pctxS#define mck$l_pctx_0 mck$r_uncorrectable.mck$r_fill_30_.mck$r_fill_31_.mck$l_pctx_0S#define mck$l_pctx_1 mck$r_uncorrectable.mck$r_fill_30_.mck$r_fill_31_.mck$l_pctx_1"#endif /* #if !defined(__VAXC) */ N/* */N/* O */R/* Platform-specific data in the logout frame below this point Should be placed */N/* in a separate MCHKxxyyDEF.SDL module, where xx is the hex value of the */N/* system type and yy is the hex value of the cpu generation. */N/* */N/* Processor detected error types */N/* P */#define MCK_PROC$K_CORR_ECC 67#define MCK_PROC$K_BUGCHECK 71!#define MCK_PROC$K_OS_BUGCHECK 72##define MCK_PROC$K_RETRYABLE_IRD 75"#define MCK_PROC$K_PROC_HRD_ERR 76!#define MCK_PROC$K_DC_TAG_PERR 79"#define MCK_PROC$K_SYS_HRD_ERR 257 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined requQired ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EV6MCHKDEF_LOADED */ ww{[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated ROR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone witShout **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by Op TenVMS SDL V3.7 */F/* Source: 08-DEC-1994 12:33:07 $1$DGA8345:[LIB_H.SRC]EVTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EVTDEF ***/#ifndef __EVTDEF_LOADED#define __EVTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined wheneverU ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variaVnt_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* EVENT CODE DEFINITIONS */N/* */#define EVT$_AST 0#define EVT$_COLPGA 0#define EVT$_EVENT 1#define EVT$_CEF 2#define EVT$_LEFO 3#dWefine EVT$_FPGA 4#define EVT$_WAKE 5#define EVT$_RESUME 6#define EVT$_PFCOM 7#define EVT$_SETPRI 8#define EVT$_SWPOUT 9#define EVT$_SWPOUTE 10#define EVT$_SWPIN 11#define EVT$_SWPINC 12#define EVT$_MAXEVT 13 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#p Xragma __standard #endif /* __EVTDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permissiYon of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, InZc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:40 by OpenVMS SDL V3.7 */I/* Source: 05-MAY-1993 16:24:16 $1$DGA834 [5:[LIB_H.SRC]EWDATADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EWDATADEF ***/#ifndef __EWDATADEF_LOADED#define __EWDATADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_point\er_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !d ]efined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* $EWDATADEF - Symbolic offsets within the exec-writable page */N/* */N/* An exec-writable page is allocated when the system is bootstrapped. */N/* The fields within this page are being defined below. These data cells */N/* wer^e originally defined in the system (i.e. in SYS.EXE) with the form: */N/* */I/* PMS$xL_cellname. */N/* */N/* Now that this cell resides in a seperate exec-writable page that is */N/* pointed by a cell in the system's base image, the symbolic offset from */N/* the base of the exec-writable pag_e to this cell has the form: */N/* */I/* EW_PMS$xL_cellname. */N/* */N/* */Q/* NOTE: The PMS Arrays (COUNT, MCNT, WRITE, CACHE, CPU, PFA) must immediately */N/* follow FCP and FCP2 fields. ` */N/* */N/*- */#define EW$K_LENGTH 378#define EW$C_LENGTH 378N#define EW$S_EWDATADEF 378 /* Old size name - synonym */ typedef struct _ewdata { __struct {#if defined(__VAXC) char ew_pms$gl_fcp[];#else$#define ew_pms$gl_fcp ew_pms$gl_fcp2"#endif /* #if defined(__VAXC) */#if defined( a__VAXC) char ew_pms$gl_fcp2[];#else&#define ew_pms$gl_fcp2 ew_pms$al_count"#endif /* #if defined(__VAXC) */N unsigned int ew_pms$al_count [10]; /* number of operations */N unsigned int ew_pms$al_mcnt [10]; /* number of modifiers */N unsigned int ew_pms$al_read [10]; /* number of disk reads */N unsigned int ew_pms$al_write [10]; /* number of disk writes */N unsigned int ew_pms$al_cache [10]; /* number of cachbe hits */N unsigned int ew_pms$al_cpu [10]; /* accumulated cpu times */N unsigned int ew_pms$al_pfa [10]; /* accumulated page faults */N unsigned int ew_pms$gl_turn; /* number of window turns */N unsigned int ew_pms$gl_dirhit; /* count of directory LRU hits */N unsigned int ew_pms$gl_dirmiss; /* count of directory LRU misses */N unsigned int ew_pms$gl_quohit; /* count of quota cache hits */N c unsigned int ew_pms$gl_quomiss; /* count of quota cache misses */N unsigned int ew_pms$gl_fidhit; /* count of file ID cache hits */N unsigned int ew_pms$gl_fidmiss; /* count of file ID cache misses */N unsigned int ew_pms$gl_exthit; /* count of extent cache hits */N unsigned int ew_pms$gl_extmiss; /* count of extent cache misses */P unsigned int ew_pms$gl_filhdr_hit; /* count of file header cache hits */S unsigned int ew_pms$gld_filhdr_miss; /* count of file header cache misses */T unsigned int ew_pms$gl_dirdata_hit; /* count of directory data block hits */W unsigned int ew_pms$gl_dirdata_miss; /* count of directory data block misses */W unsigned int ew_pms$gl_storagmap_hit; /* count of storage bit map cache hits */Z unsigned int ew_pms$gl_storagmap_miss; /* count of storage bit map cache misses */N unsigned int ew_pms$gl_open; /* number of currently open files */N unsiegned int ew_pms$gl_opens; /* total count of opens */O unsigned int ew_pms$gl_eraseio; /* total count of erase QIO's issued */N unsigned int ew_pms$gl_vollck; /* count of XQP volume synch locks */O unsigned int ew_pms$gl_volwait; /* # of times XQP had to wait for a */N/* volume synch lock */N unsigned int ew_pms$gl_synchlck; /* count of XQP directory and */N/* file synch locks f */Q unsigned int ew_pms$gl_synchwait; /* # of times XQP had to wait for a */N/* directory or file synch lock */N unsigned int ew_pms$gl_acclck; /* count of XQP access locks */V unsigned int ew_pms$gl_xqpcachewait; /* # of times XQP had to wait for free */N/* space in a cache */ } ew$r_pmsewdata; __struct {[ g unsigned short int ew_rms$gw_gblbufquo; /* current global buffer quota remaining */ } ew$r_rmsewdata; } EWDATA; #if !defined(__VAXC)6#define ew_pms$al_count ew$r_pmsewdata.ew_pms$al_count4#define ew_pms$al_mcnt ew$r_pmsewdata.ew_pms$al_mcnt4#define ew_pms$al_read ew$r_pmsewdata.ew_pms$al_read6#define ew_pms$al_write ew$r_pmsewdata.ew_pms$al_write6#define ew_pms$al_cache ew$r_pmsewdata.ew_pms$al_cache2#define ew_pms$al_cpu ew$r_pmsewdata.ew_pms$al_cpu2#define ew_pms$a hl_pfa ew$r_pmsewdata.ew_pms$al_pfa4#define ew_pms$gl_turn ew$r_pmsewdata.ew_pms$gl_turn8#define ew_pms$gl_dirhit ew$r_pmsewdata.ew_pms$gl_dirhit:#define ew_pms$gl_dirmiss ew$r_pmsewdata.ew_pms$gl_dirmiss8#define ew_pms$gl_quohit ew$r_pmsewdata.ew_pms$gl_quohit:#define ew_pms$gl_quomiss ew$r_pmsewdata.ew_pms$gl_quomiss8#define ew_pms$gl_fidhit ew$r_pmsewdata.ew_pms$gl_fidhit:#define ew_pms$gl_fidmiss ew$r_pmsewdata.ew_pms$gl_fidmiss8#define ew_pms$gl_exthit ew$r_pmsewdata.ew_pms$gl_exthit:#defiine ew_pms$gl_extmiss ew$r_pmsewdata.ew_pms$gl_extmiss@#define ew_pms$gl_filhdr_hit ew$r_pmsewdata.ew_pms$gl_filhdr_hitB#define ew_pms$gl_filhdr_miss ew$r_pmsewdata.ew_pms$gl_filhdr_missB#define ew_pms$gl_dirdata_hit ew$r_pmsewdata.ew_pms$gl_dirdata_hitD#define ew_pms$gl_dirdata_miss ew$r_pmsewdata.ew_pms$gl_dirdata_missF#define ew_pms$gl_storagmap_hit ew$r_pmsewdata.ew_pms$gl_storagmap_hitH#define ew_pms$gl_storagmap_miss ew$r_pmsewdata.ew_pms$gl_storagmap_miss4#define ew_pms$gl_open ew$r_pmse jwdata.ew_pms$gl_open6#define ew_pms$gl_opens ew$r_pmsewdata.ew_pms$gl_opens:#define ew_pms$gl_eraseio ew$r_pmsewdata.ew_pms$gl_eraseio8#define ew_pms$gl_vollck ew$r_pmsewdata.ew_pms$gl_vollck:#define ew_pms$gl_volwait ew$r_pmsewdata.ew_pms$gl_volwait<#define ew_pms$gl_synchlck ew$r_pmsewdata.ew_pms$gl_synchlck>#define ew_pms$gl_synchwait ew$r_pmsewdata.ew_pms$gl_synchwait8#define ew_pms$gl_acclck ew$r_pmsewdata.ew_pms$gl_acclckD#define ew_pms$gl_xqpcachewait ew$r_pmsewdata.ew_pms$gl_xqpcachewakit>#define ew_rms$gw_gblbufquo ew$r_rmsewdata.ew_rms$gw_gblbufquo"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EWDATADEF_LOADED */ ww [UM/*****************************************l**********************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP m **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** n **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:40 by OpenVMS SDL V3.7 */F/* Source: 29-APR-2021 17:28:39 $1$DGA8345:[LIB_H.SRC]EXEDEF.SDL;1 *//******************************************************************************************* o*************************************//*** MODULE $EXEDEF ***/#ifndef __EXEDEF_LOADED#define __EXEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size depfault to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define EXE$C_SYSEFN 31 q /* Common system event flag */X#define EXE$C_CMSTKSZ 20 /* Number of longwords in dispatch call frame */[#define EXE$M_NPAGGRNMSK 63 /* Allocation granularity mask for nonpaged pool */X#define EXE$M_PAGGRNMSK 15 /* Allocation granularity mask for paged pool */W#define EXE$M_P1GRNMSK 15 /* Allocation granularity mask for P1 region */Q#define EXE$M_DEFGRNMSK 15 /* Allocation granularity mask default */T#define EXE$ rM_NPAGGRNMSK_256 255 /* Allocation granularity mask for S2 NPP */N/* MMG FLAGS */ #define EXE$M_MMG_FLAG_ZDONE 0x1 #define EXE$M_MMG_FLAG_UDONE 0x2 typedef struct _mmg_flags { __union {N unsigned int exe$l_mmg_flags; /* Reserved memory flags */ __struct {e unsigned exe$v_mmg_flag_zdone : 1; /* Page zeroing in reserved memory registry is done */T unsigned exe$v_m smg_flag_udone : 1; /* Testing untested memory is done */' unsigned exe$v_fill_0_ : 6;# } exe$r_mmg_flags_bits;" } exe$r_mmg_flags_overlay; } MMG_FLAGS; #if !defined(__VAXC)?#define exe$l_mmg_flags exe$r_mmg_flags_overlay.exe$l_mmg_flags^#define exe$v_mmg_flag_zdone exe$r_mmg_flags_overlay.exe$r_mmg_flags_bits.exe$v_mmg_flag_zdone^#define exe$v_mmg_flag_udone exe$r_mmg_flags_overlay.exe$r_mmg_flags_bits.exe$v_mmg_flag_udone"#endif /* #if !defined(__VAXCt) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EXEDEF_LOADED */ ww0[UM/***************************************************************************/M/** u **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOvFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************************w****************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:12 by OpenVMS SDL V3.7 */F/* Source: 26-FEB-2019 10:37:30 $1$DGA8345:[LIB_H.SRC]EXTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $EXTDEF ***/#ifndef __EXTDEF_LOADED#define __ xEXTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_parayms ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include #ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save&#pragma __required_pointer_size __longztypedef struct _ext * EXT_PQ;typedef struct _ext ** EXT_PPQ;)#pragma __required_pointer_size __restore#else typedef unsigned __int64 EXT_PQ;!typedef unsigned __int64 EXT_PPQ;#endif c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ext {#pragma __nomember_alignment __union {' unsigned __int64 ext$q_address; { __struct {+ unsigned int ext$l_address_low;, unsigned int ext$l_address_high;# } ext$r_addr_longwords; } ext$r_address_union;N __union { /* X-3 */ __struct { int ext$l_length; int ext$l_mbz;" } ext$r_length_struct;& unsigned __int64 ext$q_length; } ext$r_length_union;U PTE ext$r_common_pte; /* X-4 PTE bits |common to all pages in EXT */ } EXT; #if !defined(__VAXC)7#define ext$q_address ext$r_address_union.ext$q_addressE#define ext$r_addr_longwords ext$r_address_union.ext$r_addr_longwords@#define ext$l_address_low ext$r_addr_longwords.ext$l_address_lowB#define ext$l_address_high ext$r_addr_longwords.ext$l_address_highB#define ext$r_length_struct ext$r_length_union.ext$r_length_struct5#define ext$l_length ext$r_length_struct.ext$l_length/#define ext$l_mbz ext$r_length_struct.ext$l_mbz}4#define ext$q_length ext$r_length_union.ext$q_length"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __EXTDEF_LOADED */ wwPf[UM/*****************************************************~**********************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:10 by OpenVMS SDL V3.7 */H/* Source: 04-NOV-1999 15:48:23 $1$DGA8345:[LIB_H.SRC]F11BCDEF.SDL;1 *//***************************************************************************************************** ***************************//*** MODULE $F11BCDEF ***/#ifndef __F11BCDEF_LOADED#define __F11BCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+  */N/* F11BC - Files 11 Block Cache */N/* */N/* Header area which describes block cache used by F11BXQP. */N/* */N/*- */ N/*  */V/* The next four constants are to do with minimum cache allowances for XQP activity */N/* per process. These minima control not ionly minimum cache size but also */N/* stalling for XQP activity. */N/* */N#define F11BC$K_MAPCACHE_MIN 1 /* Bitmap.sys buffers per process */N#define F11BC$K_HDRCACHE_MIN 4 /* Indexf.sys buffers per process */N#define F11BC$K_DIRCACHE_MIN 2 /* Dir/quota buffers per process */S#define F11BC$K_DINDXCACHE_MIN 1 /* Directory index `buffers' per process */R/* The next four constants are to control the minimum number of fluid buffers a */`/* process can hold in the XQP cache. (Fluid buffers == buffers that are not pinned in cache) */N/* */N#define F11BC$K_MAPCACHE_FLUIDMIN 1 /* Bitmap.sys buffers per process */N#define F11BC$K_HDRCACHE_FLUIDMIN 3 /* Indexf.sys buffers per process */N#define F11BC$K_DIRCACHE_FLUIDMIN 2 /* Dir/quota buffers per process */S#define F11BC$K_DINDXCACHE_FLUIDMIN 1 /* Directory index `buffers' per process */N#define F11BC$K_NUM_POOLS 4 /* Number of buffer pools. */N#define F11BC$S_F11BCDEF 240 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _bfrd; struct _bfrl ; #endif /* #ifdef __cplusplus */ typedef struct _f11bc {N void *f11bc$l_bufbase; /* Base address of buffer area. */N unsigned int f11bc$l_bufsize; /* Size of buffer area in bytes. */N unsigned short int f11bc$w_size; /* Standard size field. */N unsigned char f11bc$b_type; /* Standard type field. */N unsigned char f11bc$b_subtype; /* Standard subtype field. */W int f11bc$l_fill1;  /* Position of old size field (Now Reserved) */ __union {O unsigned __int64 f11bc$q_qrealsize; /* Structure size as a quadword. */N unsigned int f11bc$l_realsize; /* Structure size as a longword. */# } f11bc$r_realsize_overlay;N void *f11bc$l_lbnhshbas; /* Base of LBN hash table. */O unsigned int f11bc$l_lbnhshcnt; /* Count of entries in LBN hash tbl. */N unsigned int f11bc$l_bfrcnt; /* Total buffer count. */N struct _bfrd *f11bc$l_bfrdbas; /* Buffer descriptor base address. */O struct _bfrl *f11bc$l_bfrldbas; /* Buffer lock descriptor base addr. */P void *f11bc$l_blhshbas; /* Base addr of buffer lock hash tbl. */P unsigned int f11bc$l_blhshcnt; /* Num entries in buff lock hash tbl. */V void *f11bc$a_freebfrl; /* Address of first free buffer lock block. */N __int64 f11bc$q_pool_lru [4]; /* Per pool LRU listhead. */N __int64 f11bc$q_pool_waitq [4]; /* Per pool cache wait listhead. */N int f11bc$l_waitcnt [4]; /* Count of waiters per pool. */N int f11bc$l_poolavail [4]; /* Available buffers per pool. */N int f11bc$l_poolcnt [4]; /* Count of buffers per pool. */N void *f11bc$l_ambigqfl; /* Ambiguity queue forward link. */N void *f11bc$l_ambigqbl; /* Ambiguity queue back link. */N/*  */N/* Cache performance counters. */N/* */N unsigned int f11bc$l_process_hits; /* In-process buffer hits. */N unsigned int f11bc$l_valid_hits; /* Valid buffer cache hits. */P unsigned int f11bc$l_invalid_hits; /* Buffer found but invalid contents. */N unsigned int f11bc$l_misses; /* Buffer not in cache at all. */N unsigned int f11bc$l_disk_reads; /* Buffer reads from disk. */N unsigned int f11bc$l_disk_writes; /* Buffer writes to disk. */N unsigned int f11bc$l_cache_serial; /* Cache serialization calls. */N unsigned int f11bc$l_cache_stalls; /* Cache serialization stalls. */N unsigned int f11bc$l_buffer_stalls; /* Stalls for lack of buffers. */P char f11bc$t_cachename [24]; /* Name of this cache (display only). */N  void *f11bc$l_log_buffer; /* Pointer to activity log buffer */ } F11BC; #if !defined(__VAXC)D#define f11bc$q_qrealsize f11bc$r_realsize_overlay.f11bc$q_qrealsizeB#define f11bc$l_realsize f11bc$r_realsize_overlay.f11bc$l_realsize"#endif /* #if !defined(__VAXC) */ N/* */N/* Buffer descriptors. */N/*  */#define BFRD$M_DIRTY 0x4#define BFRD$M_VALID 0x8#define BFRD$M_NOPURGE 0x10"#define BFRD$M_ASYNCH_IN_PROG 0x20#define BFRD$M_PINNED 0x40N#define BFRD$S_BFRDDEF 48 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _vfrd; struct _ucb; #endif /* #ifdef __cplusplus */ typedef struct _bfrd {N struct _bfrd *bfrd$l_qfl; /* Queue forward link. */N struct _vfrd *bfrd$l_qbl; /* Queue back link. */N unsigned int bfrd$l_lbn; /* LBN of buffer. */N struct _ucb *bfrd$l_ucb; /* UCB of buffer. */N unsigned int bfrd$l_lockbasis; /* Unique file identifier. */P unsigned int bfrd$l_seqnum; /* Buffer validation sequence number. */ __union {N unsigned char bfrd$b_flags; /* Status flags. */ __struct {N unsigned bfrd$v_pool : 2; /* Pool number of this buffer. */N unsigned bfrd$v_dirty : 1; /* Buffer has been modified. */N unsigned bfrd$v_valid : 1; /* Buffer has been read from disk. */O unsigned bfrd$v_nopurge : 1; /* Do not purge from process cache */c unsigned bfrd$v_asynch_in_prog : 1; /* This buffer has an outstanding deferred write */N unsigned bfrd$v_pinned : 1; /* Buffer is pinned in cache */ ( unsigned bfrd$v_fill_0_ : 1; } bfrd$r_flags_bits; } bfrd$r_flags_overlay;N unsigned char bfrd$b_btype; /* Buffer type. */ short int bfrd$w_fill_1;N unsigned int bfrd$l_curpid; /* Index of current process. */N unsigned int bfrd$l_nxtbfrd; /* Index of next BFRD (hash chain). */P void *bfrd$a_bfrl; /* Address of buffer lock descriptor. */P unsigned int bfrd$l_same_bfrl; /*  Index to next BFRD under same BFRL */N unsigned int bfrd$l_thread; /* Thread number */ } BFRD; #if !defined(__VAXC)6#define bfrd$b_flags bfrd$r_flags_overlay.bfrd$b_flagsF#define bfrd$v_pool bfrd$r_flags_overlay.bfrd$r_flags_bits.bfrd$v_poolH#define bfrd$v_dirty bfrd$r_flags_overlay.bfrd$r_flags_bits.bfrd$v_dirtyH#define bfrd$v_valid bfrd$r_flags_overlay.bfrd$r_flags_bits.bfrd$v_validL#define bfrd$v_nopurge bfrd$r_flags_overlay.bfrd$r_flags_bits.bfrd$v_n opurgeZ#define bfrd$v_asynch_in_prog bfrd$r_flags_overlay.bfrd$r_flags_bits.bfrd$v_asynch_in_progJ#define bfrd$v_pinned bfrd$r_flags_overlay.bfrd$r_flags_bits.bfrd$v_pinned"#endif /* #if !defined(__VAXC) */ N/* */N/* Buffer lock descriptor blocks. */N/* */N#define BFRL$S_BFRLDEF 24 /* Old siz e name - synonym */ typedef struct _bfrl {Q void *bfrl$a_nxtbfrl; /* Address of next BFRL in hash chain. */Q unsigned int bfrl$l_bfrd; /* Index to first BFRD under this lock */T unsigned int bfrl$l_refcnt; /* Number of buffers backed by this lock. */N unsigned int bfrl$l_lkid; /* Lock ID of buffer lock. */N unsigned int bfrl$l_lckbasis; /* Unique file identifier. */N unsigned int bfrl$l_parlkid;  /* Unique volume set identifier. */ } BFRL; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __F11BCDEF_LOADED */ wwP[UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:10 by OpenVMS SDL V3.7 */G/* Source: 13-MAY-1993 14:02:07 $1$DGA8345:[LIB_H.SRC]F11CDEF.SDL;1 *//********************************************************************************************************************************/#/*** MOD ULE $F11CDEF IDENT X-3 ***/#ifndef __F11CDEF_LOADED#define __F11CDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*  */N/* File sections shall be recorded in the Data Area. The following types of */N/* descriptors shall be record in the data area of a volume. */N/* */I/* o Volume Descriptors */I/* o Boot Record (BOOT) */I/* o Volume Descriptor Set Terminator (VDST) */I/* o Primary Volume Descriptor (PVD) */I/* o Supplementary Volume Descriptor (SVD) */I/* o Volume Partition Descriptor (VPD) */I/* o File Descriptors */I/* o Directory Descriptors */I/* o Path Tables */N/* */N/* */N/* ISO 9660 standard constants */N/* */R#define ISO$K_LOGICAL_BLOCK_SIZE 2048 /* Current Volume Descriptor Block Size */Q#define ISO$K_SYSTEM_AREA 0 /* Logical Block number of System Area */O#define ISO$K_DATA_AREA 16 /* Logical Block number of Data Area */]#define ISO$K_ISO_9660_VERSION_1988 1 /* Volume Descriptor Version # for ISO 9660 (1988) */N/* */N/* Character set coding */N/* */N#define ISO$K_SPACE 32 /* ' ' fill character */N#define ISO$K_SEPARATOR_1 46 /* '.'-filename.extension break */N#define ISO$K_SEPARATOR_2 59 /* ';'-extension;version break */N#define ISO$K_FILE_ID 95 /* '_' file identifier character */N#define ISO$K_ROOT_DIRECTORY_ID 0 /* Root Directory Identifier */N#define ISO$K_PARENT_DIRECTORY_ID 1 /* Parent Directory Identifier */N/*+ */N/* FILE_ID */N/*  */N/* A File Identifier consist of the following sequence: */I/* - File name : A sequence of 0 -> 30 'D' or 'D1' characters */I/* - SEPARATOR_1 */I/* - Extension : A sequence of 0 -> 30 'D' or 'D1' characters */I/* - SEPARATOR_2 */I/* - Version # : A sequence of 1 to 5 digits; up to "32767" */N/* If 'File Nam e' length equals 0, then Extension must be 1 or greater */N/* If 'Extension' length equals 0, then File Name must be 1 or greater */N/* The length of 'File Name' + 'Extension' must not exceed 30. */N/*- */N#define ISO$FNAME$S_FILE_ID 37 /* Old size name- synonym */ typedef struct _f11c_file_id {N char iso$fname$t_file_name_ext [37]; /* filename.ext;version */ } F11C_FILE_ID;N/*+ */N/* Identifier */N/* */N/* This descriptor shall specify an identifier. If the first byte is equal */N/* to a %X05F, the remaining bytes of this field shall specific an */N/* identifier for a file containing the identification text. This file */N/* shall be described in the Root Directory. The File Name shall not */N/* contain more than 8 D_CHARACTERS and the File Extension shall not */N/* contain more than 3 D_CHARACTERS. If all bytes in this field are set to */N/* %X20, it shall mean that no such identifier is defined. */N/*- */N#define ISO$ID$S_IDENTIFIER 128 /* Old size name - synonym */ typedef union _f11c_identifier {  __struct {N unsigned char iso$id$b_flag; /* File specific flag */V char iso$id$t_file_name_ext [37]; /* File Identifier (filename.ext;version) */ } iso$id$r_encoded_id;N char iso$id$b_data [128]; /* Text Identifier */ } F11C_IDENTIFIER; #if !defined(__VAXC)7#define iso$id$b_flag iso$id$r_encoded_id.iso$id$b_flagI#define iso$id$t_file_name_ext iso$id$r_encoded_id.iso$id$t_file_name_ext"#endif /* #if !define d(__VAXC) */ N/*+ */N/* ASCII_DATE_TIME */N/* */N/* The date and time shall be represented by a 17-byte field. */N/* If Byte positions 1-16 are the digit '0', and BP 17 equals 0, then */N/* it shall mean that date and time are not specified. */N/*-  */N#define ISO$AUTC$S_ASCII_DATE_TIME 17 /* Old size name - synonym */ !typedef struct _f11c_ascii_date {N char iso$autc$t_year [4]; /* year (1-9999) */N char iso$autc$t_month [2]; /* month (1-12) */N char iso$autc$t_day [2]; /* day (1-31) */N char iso$autc$t_hour [2]; /* hour (0-23)  */N char iso$autc$t_minute [2]; /* minute (0-59) */N char iso$autc$t_second [2]; /* second (0-59) */N char iso$autc$t_hundredth [2]; /* hundredth (0-99) */N char iso$autc$b_offset_gmt; /* hr. intervals (-48:+52)) */ } F11C_ASCII_DATE;N/*+ */N/* BINARY_DATE_TIME */N/* */N/* The data and time shall be represented by seven 8-bit numbers */N/*- */N#define ISO$BUTC$S_BINARY_DATE_TIME 7 /* Old size name - synonym */ "typedef struct _f11c_binary_date {N unsigned char iso$butc$b_year; /* year since 1900 (1-99) */N unsigned char iso$butc$b_month; /* month (1-12)  */N unsigned char iso$butc$b_day; /* day (1-31) */N unsigned char iso$butc$b_hour; /* hour (0-23) */N unsigned char iso$butc$b_minute; /* minute (0-59) */N unsigned char iso$butc$b_second; /* second (0-59) */Y char iso$butc$b_offset_gmt; /* hr. intervals from -48(west) to +52(east) */ } F11C_BINARY_DATE;N/*+  */N/* PATH_TABLE_RECORD */N/* */N/* A Path Table contain a set of records describing a directory hierarchy */N/* for those volume of a Volume Set the sequence numbers of which are less */N/* than, or equal to, the assigned Volume Set size of the volume. */N/* */N/* For each directory in the directory hierarchy other then the Root */N/* Directory, the Path Table shall contain a record which identifies */N/* the directory, its Parent Directory and its location. The records */N/* in a Path Table shall be number starting at 1. The first record in */N/* the Path Table shall identify the Root Directory and it location. */N/* */N/*-  */N#define ISO$PTBL$S_PATH_TABLE_RECORD 45 /* Old size name - synonym */ %typedef struct _f11c_path_table_rec {V unsigned char iso$ptbl$b_directory_id_length; /* Length of directory Identifier */O unsigned char iso$ptbl$b_xar_length; /* Extended Attribute Record length */N unsigned int iso$ptbl$l_extent_location; /* Location of Extent */Q unsigned short int iso$ptbl$w_parent_directory; /* Parent Directory Number */N char iso$ptbl$t_directory_id [37]; /* Directory Identifier (dirname) */ } F11C_PATH_TABLE_REC;N/*+ */N/* DIRECTORY */N/* This descriptor shall define a directory record. A directory record */N/* contains information to locate a File Section; an Extended Attribute */N/* Record associated with a File Section; the identification of a f ile; */N/* attributes of a file and file section. */N/*- */ #define ISO$DREC$M_EXISTENCE 0x1 #define ISO$DREC$M_DIRECTORY 0x2!#define ISO$DREC$M_ASSOCIATED 0x4#define ISO$DREC$M_RECORD 0x8"#define ISO$DREC$M_PROTECTION 0x10 #define ISO$DREC$M_RESERVED 0x60$#define ISO$DREC$M_MULTI_EXTENT 0x80N#define ISO$DREC$A_PADDING 34 /* Pad byte */N#define ISO$DREC$A_SYSTEM_USE 34 /* System use */N#define ISO$DREC$S_DIRECTORY 512 /* Old size name - synonym */ typedef struct _f11c_directory {O unsigned char iso$drec$b_directory_length; /* Length of directory record */N unsigned char iso$drec$b_xar_length; /* Extended Attribute Length */N unsigned int iso$drec$l_extent_location; /* Location of Extent (LBN) */N unsigned int iso$drec$l_extent_location_m; /* Location of Extent (LBN) */N unsigned int iso$drec$l_data_length; /* Data Length of File Section */N unsigned int iso$drec$l_data_length_m; /* Data Length of File Section */N char iso$drec$b_file_recording [7]; /* Recording Date/Time of extent */ __union {N unsigned char iso$drec$b_file_flags; /* File characteristics */ __struct {N unsigned iso$drec$v_existence : 1; /* If set; nonexistent */N unsigned iso$drec$v_directory : 1; /* If set; directory record */N unsigned iso$drec$v_associated : 1; /* If set; associated file */S unsigned iso$drec$v_record : 1; /* If set; record format via XAR.RFM */P unsigned iso$drec$v_protection : 1; /* If set; enforce protection */N unsigned iso$drec$v_reserved : 2; /* Reserved */N unsigned iso$drec$v_multi_extent : 1; /* If set; extend record */) } iso$drec$r_file_flags_bits;( } iso$drec$r_file_flags_overlay;N unsigned char iso$drec$b_file_unit_size; /* Interleave File Unit size */N unsigned char iso$drec$b_interleave_gap; /* Interleave Gap size */R unsigned short int iso$drec$w_volume_number; /* Volume Sequence # of extent */T unsigned short int iso$drec$w_volume_number_m; /* Volume Sequence # of extent */O unsigned char iso$drec$b_file_id_length; /* File Identifier Field Length */N char iso$drec$b_file_id; /* File Identifier */N char iso$drec$b_ [478]; /* Fill out to maximum size */ } F11C_DIRECTORY; #if !defined(__VAXC)Q#define iso$drec$b_file_flags iso$drec$r_file_flags_overlay.iso$drec$b_file_flagsj#define iso$drec$v_existence iso$drec$r_file_flags_overlay.iso$drec$r_file_flags_bits.iso$drec$v_existencej#define iso$drec$v_directory iso$drec$r_file_flags_overlay.iso$drec$r_file_flags_bits.iso$drec$v_directoryl#define iso$drec$v_associated iso$drec$r_file_flags_overlay.iso$drec$r_file_flags_bits.iso$drec$v_associatedd#define iso$drec$v_record iso$drec$r_file_flags_overlay.iso$drec$r_file_flags_bits.iso$drec$v_recordl#define iso$drec$v_protection iso$drec$r_file_flags_overlay.iso$drec$r_file_flags_bits.iso$drec$v_protectionp#define iso$drec$v_multi_extent iso$drec$r_file_flags_overlay.iso$drec$r_file_flags_bits.iso$drec$v_multi_extent"#endif /* #if !defined(__VAXC) */ N/*+ */N/* XAR_RECORD  */N/* This descriptor shall define an Extended Attribute Record. An */N/* extended attribute record contains addition information which */N/* is associated to a File Section. */N/* */N/*- */!#define ISO$XAR$M_SYS_NO_READ 0x1#define ISO$XAR$M_FILL_1 0x2$#define ISO$XAR$M_SYS_NO_EXECUTE 0x4#define ISO$XAR$M_FILL_2 0x8"#define ISO$XAR$M_OWN_NO_READ 0x10#define ISO$XAR$M_FILL_3 0x20%#define ISO$XAR$M_OWN_NO_EXECUTE 0x40#define ISO$XAR$M_FILL_4 0x80##define ISO$XAR$M_GRP_NO_READ 0x100#define ISO$XAR$M_FILL_5 0x200&#define ISO$XAR$M_GRP_NO_EXECUTE 0x400#define ISO$XAR$M_FILL_6 0x800$#define ISO$XAR$M_WLD_NO_READ 0x1000#define ISO$XAR$M_FILL_7 0x2000'#define ISO$XAR$M_WLD_NO_EXECUTE 0x4000#define ISO$XAR$M_FILL_8 0x8000!#define ISO$XAR$RFM$K_UNDEFINED 0#define ISO$XAR$RFM$K_FIXED 1$#define ISO$XAR$RFM$K_LSB_VARIABLE 2$#define ISO$XAR$RFM$K_MSB_VARIABLE 3'#define ISO$XAR$RFM$SYS$K_UNDEFINED 128##define ISO$XAR$RFM$SYS$K_FIXED 129&#define ISO$XAR$RFM$SYS$K_VARIABLE 130!#define ISO$XAR$RFM$SYS$K_VFC 131$#define ISO$XAR$RFM$SYS$K_STREAM 132&#define ISO$XAR$RFM$SYS$K_STREAMLF 133&#define ISO$XAR$RFM$SYS$K_STREAMCR 134#define ISO$XAR$ATR$K_CRLF 0#define ISO$XAR$ATR$K_FTN 1#define ISO$XAR$ATR$K_STM 2N#define ISO$XAR$A_ESCAPE_SEQUENCE 250 /* Escape Sequences */N#define ISO$XAR$S_XAR_RECORD 512 /* Old size name - synonym */ !typedef struct _f11c_xar_record {N unsigned short int iso$xar$w_owner_id; /* Owner Identification */N unsigned short int iso$xar$w_owner_id_m; /* Owner Identification */N unsigned short int iso$xar$w_group_id; /* Group Identification */N unsigned short int iso$xar$w_group_id_m; /* Group Identification  */ __union {^ unsigned short int iso$xar$w_permissions; /* Access permission for classes of users */ __struct {N unsigned iso$xar$v_sys_no_read : 1; /* If set; ~(S:R) */N unsigned iso$xar$v_fill_1 : 1; /* Must be set to 1 */N unsigned iso$xar$v_sys_no_execute : 1; /* If set; ~(S:E) */N unsigned iso$xar$v_fill_2 : 1; /* Must be set to 1 */N unsigned iso$xar$v_own_no_read : 1; /* If set; ~(O:R) */N unsigned iso$xar$v_fill_3 : 1; /* Must be set to 1 */N unsigned iso$xar$v_own_no_execute : 1; /* If set; ~(O:E) */N unsigned iso$xar$v_fill_4 : 1; /* Must be set to 1 */N unsigned iso$xar$v_grp_no_read : 1; /* If set; ~(G:R) */N unsigned iso$xar$v_fill_5 : 1; /* Must be set to 1 */N unsigned iso$xar$v_grp_no_execute : 1; /* If set; ~(G: E) */N unsigned iso$xar$v_fill_6 : 1; /* Must be set to 1 */N unsigned iso$xar$v_wld_no_read : 1; /* If set; ~(W:R) */N unsigned iso$xar$v_fill_7 : 1; /* Must be set to 1 */N unsigned iso$xar$v_wld_no_execute : 1; /* If set; ~(W:E) */N unsigned iso$xar$v_fill_8 : 1; /* Must be set to 1 */) } iso$xar$r_permissions_bits;( } iso$xar$r_permissions_overlay;N char iso$xar$b_file_creation [17]; /* File Creation Date/Time */N char iso$xar$b_file_modification [17]; /* File Modification Date/Time */N char iso$xar$b_file_expiration [17]; /* File Expiration Date/Time */N char iso$xar$b_file_effective [17]; /* File Effective Date/Time */N unsigned char iso$xar$b_record_format; /* Record Format */N unsigned char iso$xar$b_record_attributes; /* Record Attributes */N unsigned short int iso$xar$w_record_length; /* Record Length */N unsigned short int iso$xar$w_record_length_m; /* Record Length */N char iso$xar$t_system_id [32]; /* System Identifier */N char iso$xar$b_system_use [64]; /* System Used */N unsigned char iso$xar$b_xar_version; /* Extended Attribute Version */R unsigned char iso$xar$b_escape_seq_length; /* Escape Sequence record length */N char iso$xar$b_reserved [64]; /* Reserved  */N unsigned short int iso$xar$w_application_use; /* Application Use Length */P unsigned short int iso$xar$w_application_use_m; /* Application Use Length */N char iso$xar$b_application_use [262]; /* Application Use */ } F11C_XAR_RECORD; #if !defined(__VAXC)Q#define iso$xar$w_permissions iso$xar$r_permissions_overlay.iso$xar$w_permissionsl#define iso$xar$v_sys_no_read iso$xar$r_permissions_overlay.iso$xar$r_permissions_bits.iso$xar$v_sys_no_readr#define iso$xar$v_sys_no_execute iso$xar$r_permissions_overlay.iso$xar$r_permissions_bits.iso$xar$v_sys_no_executel#define iso$xar$v_own_no_read iso$xar$r_permissions_overlay.iso$xar$r_permissions_bits.iso$xar$v_own_no_readr#define iso$xar$v_own_no_execute iso$xar$r_permissions_overlay.iso$xar$r_permissions_bits.iso$xar$v_own_no_executel#define iso$xar$v_grp_no_read iso$xar$r_permissions_overlay.iso$xar$r_permissions_bits.iso$xar$v_grp_no_readr#define iso$xar$v_grp_no_execute iso$xar$r_permissions_overlay.iso$xar$r_permissions_bits.iso$xar$v_grp_no_executel#define iso$xar$v_wld_no_read iso$xar$r_permissions_overlay.iso$xar$r_permissions_bits.iso$xar$v_wld_no_readr#define iso$xar$v_wld_no_execute iso$xar$r_permissions_overlay.iso$xar$r_permissions_bits.iso$xar$v_wld_no_execute"#endif /* #if !defined(__VAXC) */ N/*+ */N/* Volume Descriptor */N/*  */O/* The Volume Descriptor shall Identify the volume, the partitions recorded */O/* on the volume, the volume creator(s), certain attributes of the volume, */N/* the location of other recorded descriptors and the version of the */N/* standard which applies to the volume descriptor. */N/* */N/*-  */I#define ISO$VD$K_BOOT 0 /* Boot Record Descriptor */I#define ISO$VD$K_PVD 1 /* Primary Volume Descriptor */M#define ISO$VD$K_SVD 2 /* Supplementary Volume Descriptor */I#define ISO$VD$K_VPD 3 /* Volume Partition Descriptor */)/* (Values 4 to 254 are reserved) */N#define ISO$VD$K_VDST 255 /* Volume Descriptor Set Terminator */N#define ISO$VD$S_VD 2048  /* Old size name - synonym */ typedef struct _f11c_vd {O unsigned char iso$vd$b_volume_descriptor_type; /* Volume Descriptor Type */S char iso$vd$t_standard_identifier [5]; /* International Standard Id. (CD001) */R unsigned char iso$vd$b_volume_descriptor_vers; /* Volume Descriptor Version */N char iso$vd$b_volume_data [2041]; /* Volume Descriptor Data */ } F11C_VD;N/*+  */N/* Boot Record (BOOT) */N/* */O/* The Boot Record shall Identify a system which can recognize and act upon */N/* the content of the field reserved for boot system use in the Boot */N/* Record, and shall contain information which is used to achieve a */N/* specific state for a system or for an application. */N/*  */N/*- */N#define ISO$BOOT$S_BOOT 2048 /* Old size name - synonym */ typedef struct _f11c_boot {N char iso$boot$b_boot_volume [7]; /* Boot Volume Descriptor */N char iso$boot$t_system_identifier [32]; /* Boot System Identifier */N char iso$boot$t_identifier [32]; /* Boot Identifier */N char iso$boot$b_system_use [1977]; /* Boot System Use */ } F11C_BOOT;N/*+ */N/* Volume Descriptor Set Terminator */N/* */O/* The recorded set of Volume Descriptors shall be terminated by a sequence */N/* of one or more Volume Descriptor Set Terminators */N/*  */N/*- */N#define ISO$VDST$S_VDST 2048 /* Old size name - synonym */ typedef struct _f11c_vdst {N char iso$vdst$b_terminator_volume [7]; /* Volume Descriptor Set */N char iso$vdst$b_reserved [2041]; /* Reserved */ } F11C_VDST;N/*+  */N/* Primary Volume Descriptor */N/* */N/* The Primary Volume Descriptor shall Identify the volume, a system which */N/* can recognize and act upon the content of the Logical Sectors with */O/* Logical Sector Number 0 to 15, the size of the Volume Space, the version */N/* of the standard which applies to the Volume Descriptor, the version of */N/* the specif ication which applies to the Directory Records and the Path */N/* Table Records and certain attributes of the volume. */N/* */N/*- */N#define ISO$PVD$S_PVD 2048 /* Old size name - synonym */ typedef struct _f11c_pvd {N char iso$pvd$b_primary_volume [7]; /* Primary Volume Descriptor */N char iso$pvd$b_unused_field1; /* Unused field */N char iso$pvd$t_system_identifier [32]; /* System Identifier */N char iso$pvd$t_volume_identifier [32]; /* Volume Identifier */N char iso$pvd$b_unused_field2 [8]; /* Unused field */N unsigned int iso$pvd$l_volume_space_size; /* Volume Space Size */N unsigned int iso$pvd$l_volume_space_size_m; /* Volume Space Size */N char iso$pvd$b_unused_field3 [32]; /* Unused field */N unsigned short int iso$pvd$w_volume_set_size; /* Volume Set Size */N unsigned short int iso$pvd$w_volume_set_size_m; /* Volume Set Size */N unsigned short int iso$pvd$w_volume_number; /* Volume Sequence Number */N unsigned short int iso$pvd$w_volume_number_m; /* Volume Sequence Number */N unsigned short int iso$pvd$w_logical_block_size; /* Logical Block Size */O unsigned short int iso$pvd$w_logical_block_size_m; /* Logical Block Size */N unsigned int iso$pvd$l_path_table_size; /* Path Table Size */N unsigned int iso$pvd$l_path_table_size_m; /* Path Table Size */N unsigned int iso$pvd$l_path_table; /* Path Table Logical Block # */T unsigned int iso$pvd$l_opt_path_table; /* Optional Path Table Logical Block # */N unsigned int iso$pvd$l_path_table_m; /* Path Table Logical Block # */V unsigned int iso$pvd$l_opt_path_table_m; /* Optional Path Table Logical Block # */N char iso$pvd$b_root_directory [34]; /* Root Directory Record */N char iso$pvd$t_volume_set_identifier [128]; /* Volume Set Identifier */N char iso$pvd$b_publisher_id [128]; /* Publisher Identifier */N char iso$pvd$b_data_preparer_id [128]; /* Data Preparer Identifier */N char iso$pvd$b_application_id [128]; /* Application Identifier */N char iso$pvd$b_copyright_file_id [37]; /* Copyright File Identifier */N char iso$pvd$b_abstract_file_id [37]; /* Abstract File Identifier */N char iso$pvd$b_bibliographic_id [37]; /* Bibliographic File Identifier */N char iso$pvd$b_volume_creation [17]; /* Volume Creation Date/Time */N char iso$pvd$b_volume_modifiy [17]; /* Volume Modification Date/Time */N char iso$pvd$b_volume_expiration [17]; /* Volume Expiration Date/Time */N char iso$pvd$b_volume_effective [17]; /* Volume Effective Date/Time */N unsigned char iso$pvd$b_file_structure_vers; /* File Structure Version */N char iso$pvd$b_reserved1; /* Reserved */N char iso$pvd$b_application_use [512]; /* Application Use field */N char iso$pvd$b_reserved2 [653]; /* Reserved */ } F11C_PVD;N/*+ */N/* Supplementary Volume Descriptor */N/*  */N/* The Supplementary Volume Descriptor shall Identify the volume, a system */O/* which can recognize and act upon the content of the Logical Sectors with */O/* Logical Sector Number 0 to 15, the size of the Volume Space, the version */N/* of the standard which applies to the Volume Descriptor, the version of */N/* the specification which applies to the Directory Records and the Path */N/* Table Records, certain attributes of the volume and the coded graphi c */N/* character sets used to interpret descriptor fields that contain */N/* characters. */N/* */N/*- */"#define ISO$SVD$M_NON_ISO_2375 0x1N#define ISO$SVD$S_SVD 2048 /* Old size name - synonym */ typedef struct _f11c_svd {R char iso$svd$b_supplementa ry_volume [7]; /* Supplementary Volume Descriptor */ __union {N unsigned char iso$svd$b_volume_flags; /* Volume characteristics */ __struct {h unsigned iso$svd$v_non_iso_2375 : 1; /* If set; Escape Sequence is non ISO-2375 compliant */+ unsigned iso$svd$v_fill_0_ : 7;* } iso$svd$r_volume_flags_bits;) } iso$svd$r_volume_flags_overlay;N char iso$svd$t_system_identifier [32]; /* System Identifier */N char iso$svd$t_volume_identifier [32]; /* Volume Identifier */N char iso$svd$b_unused [8]; /* Unused Field */N unsigned int iso$svd$l_volume_space_size; /* Volume Space Size */N unsigned int iso$svd$l_volume_space_size_m; /* Volume Space Size */T char iso$svd$b_escape_sequences [32]; /* Escape Sequences ISO 2022 for G0, G1 */N unsigned short int iso$svd$w_volume_set_size; /* Volume Set Size */N unsigned short int iso$svd$w_volume_set_size_m; /* Volume Set Size */N unsigned short int iso$svd$w_volume_number; /* Volume Sequence Number */N unsigned short int iso$svd$w_volume_number_m; /* Volume Sequence Number */N unsigned short int iso$svd$w_logical_block_size; /* Logical Block Size */O unsigned short int iso$svd$w_logical_block_size_m; /* Logical Block Size */N unsigned int iso$svd$l_path_table_size; /* Path Table Size */N unsigned int iso$svd$l_path_table_size_m; /* Path Table Size */N unsigned int iso$svd$l_path_table; /* Path Table Logical Block # */T unsigned int iso$svd$l_opt_path_table; /* Optional Path Table Logical Block # */N unsigned int iso$svd$l_path_table_m; /* Path Table Logical Block # */V unsigned int iso$svd$l_opt_path_table_m; /* Optional Path Table Logical Block # */N char iso$svd$b_root_directory [34]; /* Root Directory Record */N char iso$svd$t_volume_set_identifier [128]; /* Volume Set Identifier */N char iso$svd$b_publisher_id [128]; /* Publisher Identifier */N char iso$svd$b_data_preparer_id [128]; /* Data Preparer Identifier */N char iso$svd$b_application_id [128]; /* Application Identifier */N char iso$svd$b_copyright_file_id [37]; /* Copyright File Identifier */N char iso$svd$b_abstract_file_id [37]; /* Abstract File Identifier */N char iso$svd$b_bibliographic_id [37]; /* Bibliographic File Identifier */N char iso$svd$b_volume_creation [17]; /* Volume Creation Date/Time */N char iso$svd$b_volume_modifiy [17]; /* Volume Modification Date/Time */N char iso$svd$b_volume_expiration [17]; /* Volume Expiration Date/Time */N char iso$svd$b_volume_effective [17]; /* Volume Effective Date/Time */N unsigned char iso$svd$b_file_structure_vers; /* File Structure Version */N char iso$svd$b_reserved1; /* Reserved */N char iso$svd$b_application_use [512]; /* Application Use field */N char iso$svd$b_reserved2 [653]; /* Reserved */ } F11C_SVD; #if !defined(__VAXC)T#define iso$svd$b_volume_flags iso$svd$r_volume_flags_overlay.iso$svd$b_volume_flagsp#define iso$svd$v_non_iso_2375 iso$svd$r_volume_flags_overlay.iso$svd$r_volume_flags_bits.iso$svd$v_non_iso_2375"#endif /* #if !defined(__VAXC) */ N/*+ */N/* Volume Partition Descriptor */N/* */N/* The Volume Partition Descriptor shall identify a volume partition with */N/* the Volume Space, a system which can recognize and act upon the content */O/* of fields reserved for system use in the Volume Descriptor, the position */N/* and size of the volume partition, the version of the standard which */N/* applies to the Volume Descriptor.  */N/* */N/*- */N#define ISO$VPD$S_VPD 2048 /* Old size name - synonym */ typedef struct _f11c_vpd {N char iso$vpd$b_volume_partition [7]; /* Volume Partition Descriptor */N char iso$vpd$b_unused; /* Unused field */N char iso$vpd$t_system_identifier [32]; /* System Identifier */O char iso$vpd$t_partition_identifier [32]; /* Volume Partition Identifier */P unsigned int iso$vpd$l_partition_location; /* Location of Partition (LBN) */R unsigned int iso$vpd$l_partition_location_m; /* Location of Partition (LBN) */N unsigned int iso$vpd$l_partition_size; /* Volume Partition Size */N unsigned int iso$vpd$l_partition_size_m; /* Volume Partition Size */N char iso$vpd$b_system_use [1960]; /* System Used  */ } F11C_VPD; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __F11CDEF_LOADED */ ww[UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */G/* Source: 13-MAY-1993 10:46:37 $1$DGA8345:[LIB_H.SRC]F11DDEF.SDL;1 *//********************************************************************************************************************************/#/*** MODULE $F11DDEF IDENT X-3  ***/#ifndef __F11DDEF_LOADED#define __F11DDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* File sections shall be recorded in the Data Area. The following types of */N/* descriptors shall be record in the data area of a volume. */N/* */I/* o Volume Descriptors */I/* o Boot Record (BOOT) */I/* o Volume Descriptor Set Terminator (VDST) */I/* o Primary Volume Descriptor (PVD)  */I/* o Supplementary Volume Descriptor (SVD) */I/* o Volume Partition Descriptor (VPD) */I/* o File Descriptors */I/* o Directory Descriptors */I/* o Path Tables */N/* */N/*  */N/* ISO 9660 standard constants */N/* */R#define HS$K_LOGICAL_BLOCK_SIZE 2048 /* Current Volume Descriptor Block Size */Q#define HS$K_SYSTEM_AREA 0 /* Logical Block number of System Area */O#define HS$K_DATA_AREA 16 /* Logical Block number of Data Area */]#define HS$K_ISO_9660_VERSION_1988 1 /* Volume Descriptor Version # for ISO 9660 (1988) */N/* */N/* Character set coding */N/* */N#define HS$K_SPACE 32 /* ' ' fill character */N#define HS$K_FULL_STOP 46 /* '.'-filename.extension break */N#define HS$K_SEMICOLON 59 /* ';'-extension;version break */N#define HS$K_ROOT_DIRECTORY_ID 0 /* Root Directory Identifier */N#define HS$K_PARENT_DIRECTORY_ID 1 /* Parent Directory Identifier */N/*+ */N/* FILE_ID */N/* */N/* A File Identifier consist of the following sequence:  */I/* - File name : A sequence of 0 -> 30 'D' or 'D1' characters */I/* - FULL_STOP */I/* - Extension : A sequence of 0 -> 30 'D' or 'D1' characters */I/* - SEMICOLON */I/* - Version # : A sequence of 1 to 5 digits; up to "32767" */N/* If 'File Name' length equals 0, then Extension must be 1 or greater */N/* If 'Extension' length equals 0, th en File Name must be 1 or greater */N/* if 'Version' length equals 0, then Version is assumed to be 1 */N/* The length of 'File Name' + 'Extension' must not exceed 30. */N/*- */N#define HS$FNAME$S_FILE_ID 32 /* Old size name - synonym */ typedef struct _f11d_file_id {N char hs$fname$t_file_name_ext [32]; /* filename.ext;version */ } F11D_FILE_ID;N/*+  */N/* Identifier */N/* */N/* This descriptor shall specify an identifier. If all bytes in this */O/* field are set to %X20, it shall mean that no such identifier is defined. */N/*- */N#define HS$ID$S_IDENTIFIER 128  /* Old size name - synonym */ typedef union _f11d_identifier {N char hs$id$b_data [128]; /* Text Identifier */ } F11D_IDENTIFIER;N/*+ */N/* ASCII_DATE_TIME */N/* */N/* The date and time shall be represented by a 16-byte field.  */N/* If Byte positions 1-16 are the digit '0' then */N/* it shall mean that date and time are not specified. */N/*- */N#define HS$AUTC$S_ASCII_DATE_TIME 16 /* Old size name - synonym */ !typedef struct _f11d_ascii_date {N char hs$autc$t_year [4]; /* year (1-9999) */N char hs$autc$t_month [2]; /* month (1-12)  */N char hs$autc$t_day [2]; /* day (1-31) */N char hs$autc$t_hour [2]; /* hour (0-23) */N char hs$autc$t_minute [2]; /* minute (0-59) */N char hs$autc$t_second [2]; /* second (0-59) */N char hs$autc$t_hundredth [2]; /* hundredth (0-99) */ } F11D_ASCII_DATE;N/*+  */N/* BINARY_DATE_TIME */N/* */N/* The data and time shall be represented by six 8-bit numbers */N/*- */N#define HS$BUTC$S_BINARY_DATE_TIME 6 /* Old size name - synonym */ "typedef struct _f11d_binary_date {N unsigned char hs$butc$b_year; /* year since 1900 (1-99) */N unsigned char hs$butc$b_month; /* month (1-12) */N unsigned char hs$butc$b_day; /* day (1-31) */N unsigned char hs$butc$b_hour; /* hour (0-23) */N unsigned char hs$butc$b_minute; /* minute (0-59) */N unsigned char hs$butc$b_second; /* second (0-59) */ } F11D_BINARY_DATE;N/*+  */N/* PATH_TABLE_RECORD */N/* */N/* A Path Table contain a set of records describing a directory hierarchy */N/* for those volume of a Volume Set the sequence numbers of which are less */N/* than, or equal to, the assigned Volume Set size of the volume. */N/*  */N/* For each directory in the directory hierarchy other then the Root */N/* Directory, the Path Table shall contain a record which identifies */N/* the directory, its Parent Directory and its location. The records */N/* in a Path Table shall be number starting at 1. The first record in */N/* the Path Table shall identify the Root Directory and it location. */N/* */N/*-  */N#define HS$PTBL$S_PATH_TABLE_RECORD 40 /* Old size name - synonym */ %typedef struct _f11d_path_table_rec {N unsigned int hs$ptbl$l_extent_location; /* Location of Extent */N unsigned char hs$ptbl$b_xar_length; /* Extended Attribute Record length */U unsigned char hs$ptbl$b_directory_id_length; /* Length of directory Identifier */P unsigned short int hs$ptbl$w_parent_directory; /* Parent Directory Number */N char hs$ptbl$t_directory_id [32]; /* Directory Identifier (dirname) */ } F11D_PATH_TABLE_REC;N/*+ */N/* DIRECTORY */N/* This descriptor shall define a directory record. A directory record */N/* contains information to locate a File Section; an Extended Attribute */N/* Record associated with a File Section; the identification of a fil e; */N/* attributes of a file and file section. */N/*- */#define HS$DREC$M_EXISTENCE 0x1#define HS$DREC$M_DIRECTORY 0x2 #define HS$DREC$M_ASSOCIATED 0x4#define HS$DREC$M_RECORD 0x8!#define HS$DREC$M_PROTECTION 0x10#define HS$DREC$M_RESERVED 0x60##define HS$DREC$M_MULTI_EXTENT 0x80N#define HS$DREC$A_PADDING 34 /* Pad byte */N#define HS$DREC$ A_SYSTEM_USE 34 /* System use */N#define HS$DREC$S_DIRECTORY 512 /* Old size name - synonym */ typedef struct _f11d_directory {N unsigned char hs$drec$b_directory_length; /* Length of directory record */N unsigned char hs$drec$b_xar_length; /* Extended Attribute Length */N unsigned int hs$drec$l_extent_location; /* Location of Extent (LBN) */N unsigned int hs$drec$l_extent_location_m; /* Location of Extent (LBN) */N unsigned int hs$drec$l_data_length; /* Data Length of File Section */N unsigned int hs$drec$l_data_length_m; /* Data Length of File Section */N char hs$drec$b_file_recording [6]; /* Recording Date/Time of extent */ __union {N unsigned char hs$drec$b_file_flags; /* File characteristics */ __struct {N unsigned hs$drec$v_existence : 1; /* If set; nonexistent */N unsigned hs$drec$v_directory : 1; /* If set; directory recor d */N unsigned hs$drec$v_associated : 1; /* If set; associated file */R unsigned hs$drec$v_record : 1; /* If set; record format via XAR.RFM */O unsigned hs$drec$v_protection : 1; /* If set; enforce protection */N unsigned hs$drec$v_reserved : 2; /* Reserved */N unsigned hs$drec$v_multi_extent : 1; /* If set; extend record */# } hs$drec$r_file_flags;' } hs$drec$r_file_flags_overlay;N char hs$drec$b_reserved; /* Reserved */N unsigned char hs$drec$b_file_unit_size; /* Interleave File Unit Size */N unsigned char hs$drec$b_interleave_gap; /* Interleave gap size */Q unsigned short int hs$drec$w_volume_number; /* Volume Sequence # of extent */S unsigned short int hs$drec$w_volume_number_m; /* Volume Sequence # of extent */N unsigned char hs$drec$b_file_id_length; /* File Identifier Field Length */N char hs$drec$b_file_id;  /* File Identifier */N char hs$drec$b_ [478]; /* Fill out to maximum size */ } F11D_DIRECTORY; #if !defined(__VAXC)N#define hs$drec$b_file_flags hs$drec$r_file_flags_overlay.hs$drec$b_file_flagsa#define hs$drec$v_existence hs$drec$r_file_flags_overlay.hs$drec$r_file_flags.hs$drec$v_existencea#define hs$drec$v_directory hs$drec$r_file_flags_overlay.hs$drec$r_file_flags.hs$drec$v_directoryc#define hs$drec$v_associated hs$drec$r_file_flags_overlay.hs$drec$r_file_flags.hs$drec$v_associated[#define hs$drec$v_record hs$drec$r_file_flags_overlay.hs$drec$r_file_flags.hs$drec$v_recordc#define hs$drec$v_protection hs$drec$r_file_flags_overlay.hs$drec$r_file_flags.hs$drec$v_protectiong#define hs$drec$v_multi_extent hs$drec$r_file_flags_overlay.hs$drec$r_file_flags.hs$drec$v_multi_extent"#endif /* #if !defined(__VAXC) */ N/*+ */N/* XAR_RECORD  */N/* This descriptor shall define an Extended Attribute Record. An */N/* extended attribute record contains addition information which */N/* is associated to a File Section. */N/* */N/*- */ #define HS$XAR$M_SYS_NO_READ 0x1#define HS$XAR$M_FILL_1 0x2##define HS$XAR$M_SYS_NO_EXECUTE 0x4#define HS$XAR$M_FILL_2 0x8!#define HS$XAR$M_OWN_NO_READ 0x10#define HS$XAR$M_FILL_3 0x20$#define HS$XAR$M_OWN_NO_EXECUTE 0x40#define HS$XAR$M_FILL_4 0x80"#define HS$XAR$M_GRP_NO_READ 0x100#define HS$XAR$M_FILL_5 0x200%#define HS$XAR$M_GRP_NO_EXECUTE 0x400#define HS$XAR$M_FILL_6 0x800##define HS$XAR$M_WLD_NO_READ 0x1000#define HS$XAR$M_FILL_7 0x2000&#define HS$XAR$M_WLD_NO_EXECUTE 0x4000#define HS$XAR$M_FILL_8 0x8000 #define HS$XAR$RFM$K_UNDEFINED 0#define HS$XAR$RFM$K_FIXED 1##define HS$XAR$RFM$K_LSB_VARIABLE 2##define HS$XAR$RFM$K_MSB_VARIABLE 3&#define HS$XAR$RFM$SYS$K_UNDEFINED 128"#define HS$XAR$RFM$SYS$K_FIXED 129%#define HS$XAR$RFM$SYS$K_VARIABLE 130 #define HS$XAR$RFM$SYS$K_VFC 131##define HS$XAR$RFM$SYS$K_STREAM 132%#define HS$XAR$RFM$SYS$K_STREAMLF 133%#define HS$XAR$RFM$SYS$K_STREAMCR 134#define HS$XAR$ATR$K_CRLF 0#define HS$XAR$ATR$K_FTN 1#define HS$XAR$ATR$K_STM 2N#define HS$XAR$S_XAR_R ECORD 512 /* Old size name - synonym */ !typedef struct _f11d_xar_record {N unsigned short int hs$xar$w_owner_id; /* Owner Identification */N unsigned short int hs$xar$w_owner_id_m; /* Owner Identification */N unsigned short int hs$xar$w_group_id; /* Group Identification */N unsigned short int hs$xar$w_group_id_m; /* Group Identification */ __union {] unsigned short int hs$xar$w_permissions; /* Access permission for classes of users */ __struct {N unsigned hs$xar$v_sys_no_read : 1; /* If set; ~(S:R) */N unsigned hs$xar$v_fill_1 : 1; /* Must be set to 1 */N unsigned hs$xar$v_sys_no_execute : 1; /* If set; ~(S:E) */N unsigned hs$xar$v_fill_2 : 1; /* Must be set to 1 */N unsigned hs$xar$v_own_no_read : 1; /* If set; ~(O:R) */N unsigned hs$xar$v_fill_3 : 1; /* Must be set to 1 */N unsigned hs$xar$v_own_no_execute : 1; /* If set; ~(O:E) */N unsigned hs$xar$v_fill_4 : 1; /* Must be set to 1 */N unsigned hs$xar$v_grp_no_read : 1; /* If set; ~(G:R) */N unsigned hs$xar$v_fill_5 : 1; /* Must be set to 1 */N unsigned hs$xar$v_grp_no_execute : 1; /* If set; ~(G:E) */N unsigned hs$xar$v_fill_6 : 1; /* Must be set to 1 */N  unsigned hs$xar$v_wld_no_read : 1; /* If set; ~(W:R) */N unsigned hs$xar$v_fill_7 : 1; /* Must be set to 1 */N unsigned hs$xar$v_wld_no_execute : 1; /* If set; ~(W:E) */N unsigned hs$xar$v_fill_8 : 1; /* Must be set to 1 */( } hs$xar$r_permissions_bits;' } hs$xar$r_permissions_overlay;N char hs$xar$b_file_creation [16]; /* File Creation Date/Time */N char hs$xar$b_file_modification [16]; /* File Modification Date/Time */N char hs$xar$b_file_expiration [16]; /* File Expiration Date/Time */N char hs$xar$b_file_effective [16]; /* File Effective Date/Time */N unsigned char hs$xar$b_record_format; /* Record Format */N unsigned char hs$xar$b_record_attributes; /* Record Attributes */N unsigned short int hs$xar$w_record_length; /* Record Length */N unsigned short int hs$xar$w_record_length_m; /* Record Length */N char hs$xar$t_system_id [32]; /* System Identifier */N char hs$xar$b_system_use [64]; /* System Used */N unsigned char hs$xar$b_xar_version; /* Extended Attribute Version */N char hs$xar$b_reserved [64]; /* Reserved */O unsigned short int hs$xar$w_parent_directory; /* Parent Directory Number */Q unsigned short int hs$xar$w_parent_directory_m; /* Parent Directory Number  */P unsigned short int hs$xar$w_application_length; /* Application Use Length */R unsigned short int hs$xar$w_application_length_m; /* Application Use Length */N char hs$xar$b_root_directory [34]; /* Root Directory Record */N char hs$xar$b_application_use [229]; /* Application Use */ } F11D_XAR_RECORD; #if !defined(__VAXC)N#define hs$xar$w_permissions hs$xar$r_permissions_overlay.hs$xar$w_permissionsh#define hs$xar$v_sys_no_read hs$xar$r_permissions_overlay.hs$xar$r_permissions_bits.hs$xar$v_sys_no_readn#define hs$xar$v_sys_no_execute hs$xar$r_permissions_overlay.hs$xar$r_permissions_bits.hs$xar$v_sys_no_executeh#define hs$xar$v_own_no_read hs$xar$r_permissions_overlay.hs$xar$r_permissions_bits.hs$xar$v_own_no_readn#define hs$xar$v_own_no_execute hs$xar$r_permissions_overlay.hs$xar$r_permissions_bits.hs$xar$v_own_no_executeh#define hs$xar$v_grp_no_read hs$xar$r_permissions_overlay.hs$xar$r_permissions_bits.hs$xar$v_grp_no_readn#define hs$xar$v_grp_no_execute hs$xar$r_permissions_overlay.hs$xar$r_permissions_bits.hs$xar$v_grp_no_executeh#define hs$xar$v_wld_no_read hs$xar$r_permissions_overlay.hs$xar$r_permissions_bits.hs$xar$v_wld_no_readn#define hs$xar$v_wld_no_execute hs$xar$r_permissions_overlay.hs$xar$r_permissions_bits.hs$xar$v_wld_no_execute"#endif /* #if !defined(__VAXC) */ N/*+ */N/* Volume Descriptor  */N/* */O/* The Volume Descriptor shall Identify the volume, the partitions recorded */O/* on the volume, the volume creator(s), certain attributes of the volume, */N/* the location of other recorded descriptors and the version of the */N/* standard which applies to the volume descriptor. */N/* */N/*-  */I#define HS$VD$K_BOOT 0 /* Boot Record Descriptor */I#define HS$VD$K_PVD 1 /* Primary Volume Descriptor */M#define HS$VD$K_SVD 2 /* Supplementary Volume Descriptor */I#define HS$VD$K_VPD 3 /* Volume Partition Descriptor */)/* (Values 4 to 254 are reserved) */N#define HS$VD$K_VDST 255 /* Volume Descriptor Set Terminator */N#define HS$VD$S_VD 2048 /* Old size name - synonym */ typedef struct _f11d_vd {N unsigned int hs$vd$l_descriptor_lbn; /* LBN of first logical block */N unsigned int hs$vd$l_descriptor_lbn_m; /* LBN of first logical block */N unsigned char hs$vd$b_volume_descriptor_type; /* Volume Descriptor Type */R char hs$vd$t_standard_identifier [5]; /* International Standard Id. (CDROM) */Q unsigned char hs$vd$b_volume_descriptor_vers; /* Volume Descriptor  Version */N char hs$vd$b_volume_data [2033]; /* Volume Descriptor Data */ } F11D_VD;N/*+ */N/* Boot Record */N/* */O/* The Boot Record shall Identify a system which can recognize and act upon */N/* the content of the field reserved for boot system use in the Boot  */N/* Record, and shall contain information which is used to achieve a */N/* specific state for a system or for an application. */N/* */N/*- */N#define HS$BOOT$S_BOOT 2048 /* Old size name - synonym */ typedef struct _f11d_boot {N char hs$boot$b_boot_volume [15]; /* Boot Volume Descriptor   */N char hs$boot$t_system_identifier [32]; /* Boot System Identifier */N char hs$boot$t_identifier [32]; /* Boot Identifier */N char hs$boot$b_system_use [1969]; /* Boot System Use */ } F11D_BOOT;N/*+ */N/* Volume Descriptor Sequence Terminator */N/*  */O/* The recorded set of Volume Descriptors shall be terminated by a sequence */N/* of one or more Volume Descriptor Set Terminators */N/* */N/*- */N#define HS$VDST$S_VDST 2048 /* Old size name - synonym */ typedef struct _f11d_vdst {N char hs$vdst$b_terminator_volume [15]; /* Volume Descriptor  Set */N char hs$vdst$b_reserved [2033]; /* Reserved */ } F11D_VDST;N/*+ */N/* Standard File Structure Volume Descriptor */N/* */^/* The Standard File Structure Volume Descriptor shall Identify the volume, a system which */N/* can recognize and act upon the content of the Logical Sectors with */O/* Logical Sector Number 0 to 15, the size of the Volume Space, the version */N/* of the standard which applies to the Volume Descriptor, the version of */N/* the specification which applies to the Directory Records and the Path */N/* Table Records and certain attributes of the volume. */N/* */N/*- */N#define HS$PVD$S_PVD 2048 /* Old size name - synonym */ typedef struct _f11d_pvd {W char hs$pvd$b_primary_volume [15]; /* Standard File Structure Volume Descriptor */N char hs$pvd$b_unused_field1; /* Unused field */N char hs$pvd$t_system_identifier [32]; /* System Identifier */N char hs$pvd$t_volume_identifier [32]; /* Volume Identifier */N char hs$pvd$b_unused_field2 [8]; /* Unused field  */N unsigned int hs$pvd$l_volume_space_size; /* Volume Space Size */N unsigned int hs$pvd$l_volume_space_size_m; /* Volume Space Size */N char hs$pvd$b_unused_field3 [32]; /* Unused field */N unsigned short int hs$pvd$w_volume_set_size; /* Volume Set Size */N unsigned short int hs$pvd$w_volume_set_size_m; /* Volume Set Size */N unsigned short int hs$pvd$w_volume_number; /* Volume Sequence Number */N unsigned short int hs$pvd$w_volume_number_m; /* Volume Sequence Number */N unsigned short int hs$pvd$w_logical_block_size; /* Logical Block Size */N unsigned short int hs$pvd$w_logical_block_size_m; /* Logical Block Size */N unsigned int hs$pvd$l_path_table_size; /* Path Table Size */N unsigned int hs$pvd$l_path_table_size_m; /* Path Table Size */N unsigned int hs$pvd$l_path_table; /* Path Table Logical Block # */S unsigned int hs$pvd$l_opt_path_table; /* Optional Path Table Logical Block # */U unsigned int hs$pvd$l_opt_path_table_1; /* Optional Path Table Logical Block # */U unsigned int hs$pvd$l_opt_path_table_2; /* Optional Path Table Logical Block # */N unsigned int hs$pvd$l_path_table_m; /* Path Table Logical Block # */U unsigned int hs$pvd$l_opt_path_table_m; /* Optional Path Table Logical Block # */V unsigned int hs$pvd$l_opt_path_table_m1; /* Optional Path Table Logical Block # */V unsigned int hs$pvd$l_opt_path_table_m2; /* Optional Path Table Logical Block # */N char hs$pvd$b_root_directory [34]; /* Root Directory Record */N char hs$pvd$t_volume_set_identifier [128]; /* Volume Set Identifier */N char hs$pvd$b_publisher_id [128]; /* Publisher Identifier */N char hs$pvd$b_data_preparer_id [128]; /* Data Preparer Identifier */N char hs$pvd$b_application_id [128]; /* Application Identifier */N char hs$pvd$b_copyright_file_id [32]; /* Copyright File Identifier */N char hs$pvd$b_abstract_file_id [32]; /* Abstract File Identifier */N char hs$pvd$b_volume_creation [16]; /* Volume Creation Date/Time */N char hs$pvd$b_volume_modifiy [16]; /* Volume Modification Date/Time */N char hs$pvd$b_volume_expiration [16]; /* Volume Expiration Date/Time */N char hs$pvd$b_volume_effective [16]; /* Volume Effective Date/Time */N unsigned char hs$pvd$b_file_structure_vers; /* File Structure Version */N char hs$pvd$b_reserved1; /* Reserved */N char hs$pvd$b_application_use [512]; /* Application Use field */N char hs$pvd$b_reserved2 [680]; /* Reserved */ } F11D_PVD;N/*+ */N/* Coded Character Set File Structure Volume Descriptor */N/* */R/* The Coded Character Set File Structure Volume Descriptor Supplementary shall */S/* Identify the volume, a system which can recognize and act upon the content of */N/* the Logical Sectors with Logical Sector Number 0 to 15, the size of the */N/* Volume Space, the version of the standard which applies to the Volume */Q/* Descriptor, the version of the specification which applies to the Directory */R/* Records and the Path Table Records, certain attributes of the volume and the */S/* c oded graphic character sets used to interpret descriptor fields that contain */N/* characters. */N/* */N/*- */!#define HS$SVD$M_NON_ISO_2375 0x1N#define HS$SVD$S_SVD 2048 /* Old size name - synonym */ typedef struct _f11d_svd {g char hs$svd$b_supplementary_volu me [15]; /* Coded Character Set File Structure Volume Descriptor */ __union {N unsigned char hs$svd$b_volume_flags; /* Volume characteristics */ __struct {g unsigned hs$svd$v_non_iso_2375 : 1; /* If set; Escape Sequence is non ISO-2375 compliant */* unsigned hs$svd$v_fill_0_ : 7;) } hs$svd$r_volume_flags_bits;( } hs$svd$r_volume_flags_overlay;N char hs$svd$t_system_identifier [32]; /* System Identifier */N  char hs$svd$t_volume_identifier [32]; /* Volume Identifier */N char hs$svd$b_unused [8]; /* Unused Field */N unsigned int hs$svd$l_volume_space_size; /* Volume Space Size */N unsigned int hs$svd$l_volume_space_size_m; /* Volume Space Size */T char hs$svd$b_escape_sequences [32]; /* Coded Character Set for Descriptor Id */N unsigned short int hs$svd$w_volume_set_size; /* Volume Set Size */N unsigned short int hs$svd$w_volume_set_size_m; /* Volume Set Size */N unsigned short int hs$svd$w_volume_number; /* Volume Sequence Number */N unsigned short int hs$svd$w_volume_number_m; /* Volume Sequence Number */N unsigned short int hs$svd$w_logical_block_size; /* Logical Block Size */N unsigned short int hs$svd$w_logical_block_size_m; /* Logical Block Size */N unsigned int hs$svd$l_path_table_size; /* Path Table Size */N unsigned int hs$svd$l_path_table_size_m; /* Path Table Size */N unsigned int hs$svd$l_path_table; /* Path Table Logical Block # */S unsigned int hs$svd$l_opt_path_table; /* Optional Path Table Logical Block # */U unsigned int hs$svd$l_opt_path_table_1; /* Optional Path Table Logical Block # */U unsigned int hs$svd$l_opt_path_table_2; /* Optional Path Table Logical Block # */N unsigned int hs$svd$l_path_table_m; /* Path Table Logical Block # */U unsigned int hs$svd$l_opt_path_table_m; /* Optional Path Table Logical Block # */V unsigned int hs$svd$l_opt_path_table_m1; /* Optional Path Table Logical Block # */V unsigned int hs$svd$l_opt_path_table_m2; /* Optional Path Table Logical Block # */N char hs$svd$b_root_directory [34]; /* Root Directory Record */N char hs$svd$t_volume_set_identifier [128]; /* Volume Set Identifier */N char hs$svd$b_publisher_id [128]; /* Publisher Identifier */N char hs$svd$b_data_preparer_id [128]; /* Data Preparer Identifier */N char hs$svd$b_application_id [128]; /* Application Identifier */N char hs$svd$b_copyright_file_id [32]; /* Copyright File Identifier */N char hs$svd$b_abstract_file_id [32]; /* Abstract File Identifier */N char hs$svd$b_volume_creation [16]; /* Volume Creation Date/Time */N char hs$svd$b_volume_modifiy [16]; /* Volume Modification Date/Time */N char hs$svd$b_volume_expiration [16]; /* Volume Expiration Date/Time */N  char hs$svd$b_volume_effective [16]; /* Volume Effective Date/Time */N unsigned char hs$svd$b_file_structure_vers; /* File Structure Version */N char hs$svd$b_reserved1; /* Reserved */N char hs$svd$b_application_use [512]; /* Application Use field */N char hs$svd$b_reserved2 [680]; /* Reserved */ } F11D_SVD; #if !defined(__VAXC)Q#define hs$svd$b_volume_flags hs$svd$r_volume_flags_overlay.hs $svd$b_volume_flagsl#define hs$svd$v_non_iso_2375 hs$svd$r_volume_flags_overlay.hs$svd$r_volume_flags_bits.hs$svd$v_non_iso_2375"#endif /* #if !defined(__VAXC) */ N/*+ */N/* Unspecified Partition Descriptor */N/* */Y/* The Unspecified Volume Partition Descriptor shall identify a volume partition with */N/*  the Volume Space, a system which can recognize and act upon the content */O/* of fields reserved for system use in the Volume Descriptor, the position */N/* and size of the volume partition, the version of the standard which */N/* applies to the Volume Descriptor. */N/* */N/*- */N#define HS$VPD$S_VPD 2048 ! /* Old size name - synonym */ typedef struct _f11d_vpd {V char hs$vpd$b_volume_partition [15]; /* Unspecified Volume Partition Descriptor */N char hs$vpd$b_unused; /* Unused field */N char hs$vpd$t_system_identifier [32]; /* System Identifier */N char hs$vpd$t_partition_identifier [32]; /* Volume Partition Identifier */O unsigned int hs$vpd$l_partition_location; /* Location of Partition (LBN) */Q unsign "ed int hs$vpd$l_partition_location_m; /* Location of Partition (LBN) */N unsigned int hs$vpd$l_partition_size; /* Volume Partition Size */N unsigned int hs$vpd$l_partition_size_m; /* Volume Partition Size */N char hs$vpd$b_system_use [1952]; /* System Use */ } F11D_VPD; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* R$estore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __F11DDEF_LOADED */ wwp%![UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** au]O EXE_ROUTINESs\EXTDEF|F11BCDEFF11CDEFzF11DDEF"FATDEF7FBICDEFW^FBUSDEFFCBDEFFCHDEFFCPDEF#BFCPHDEF FCP_QIODEFOFDTDEFWpFDT_CONTEXTDEF`^FH1DEFrNFH2DEFFI1DEF>FI2DEFZFI5DEFFJNDEFFKBDEFFM1DEFFM2DEFtFMDEFFPDEFFPSRDEF FP_STATEDEF* FQAMDEF>FSHWAFSHWA_ROUTINESd GLX_ROUTINES- GPS_ROUTINES8IA64_ASM%thorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, dupli&cated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Cre 'ated: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FATDEF ***/#ifndef __FATDEF_LOADED#define __FATDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POI(NTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct)#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Record attributes area as used by FCS and RMS. */N/* */*N/*- */ N#define FAT$C_UNDEFINED 0 /* undefined record type */N#define FAT$C_FIXED 1 /* fixed record type */N#define FAT$C_VARIABLE 2 /* variable length */N#define FAT$C_VFC 3 /* variable + fixed control */U#define FAT$C_STREAM 4 /* RMS-11 (DEC traditional) stream format */N#define FAT$+C_STREAMLF 5 /* LF-terminated stream format */N#define FAT$C_STREAMCR 6 /* CR-terminated stream format */N#define FAT$C_SEQUENTIAL 0 /* sequential organization */N#define FAT$C_RELATIVE 1 /* relative organization */N#define FAT$C_INDEXED 2 /* indexed organization */N#define FAT$C_DIRECT 3 /* direct organization */N#define FAT$C_SPECIAL 4 , /* Special file organization */#define FAT$M_FORTRANCC 0x1#define FAT$M_IMPLIEDCC 0x2#define FAT$M_PRINTCC 0x4#define FAT$M_NOSPAN 0x8#define FAT$M_MSBRCW 0x10N#define FAT$C_FIFO 1 /* FIFO special file */N#define FAT$C_CHAR_SPECIAL 2 /* character special file */N#define FAT$C_BLOCK_SPECIAL 3 /* block special file */U#define FAT$C_SYMLINK 4 /* symbolic link special file for pre-V8.2 - */\#define FAT$C_SYMBOLIC_LINK 5 /* symbolic link special file for V8.2 and beyond */#define FAT$M_GBC_PERCENT 0x1#define FAT$M_GBC_DEFAULT 0x2#define FAT$K_LENGTH 32#define FAT$C_LENGTH 32N#define FAT$S_FATDEF 32 /* Old size name - synonym */ typedef struct _fat { __union {N unsigned char fat$b_rtype; /* record type */ __struct {N unsigned fat$v_rtype : 4; /* record type subfield . */N unsigned fat$v_fileorg : 4; /* file organization */ } fat$r_rtype_bits; } fat$r_rtype_overlay; __union {N unsigned char fat$b_rattrib; /* record attributes */ __struct {N unsigned fat$v_fortrancc : 1; /* Fortran carriage control */N unsigned fat$v_impliedcc : 1; /* implied carriage control */N unsigned fat$v_printcc : 1; /* print file carriage con/trol */N unsigned fat$v_nospan : 1; /* no spanned records */N unsigned fat$v_msbrcw : 1; /* Format of RCW (0=LSB, 1=MSB) */N unsigned fat$v_fill_1 : 3; /* MBZ (or should be zero) */! } fat$r_rattrib_bits;N unsigned char fat$b_special_type; /* type of special file */N/* (record attributes are */N/* meaningless for special files) 0 */ } fat$r_rattrib_overlay;N unsigned short int fat$w_rsize; /* record size in bytes */ __union {N unsigned int fat$l_hiblk; /* highest allocated VBN */ __struct {N unsigned short int fat$w_hiblkh; /* high order word */N unsigned short int fat$w_hiblkl; /* low order word */! } fat$r_hiblk_fields; } fat$r_hiblk_overlay; __union {N 1 unsigned int fat$l_efblk; /* end of file VBN */ __struct {N unsigned short int fat$w_efblkh; /* high order word */N unsigned short int fat$w_efblkl; /* low order word */! } fat$r_efblk_fields; } fat$r_efblk_overlay;N unsigned short int fat$w_ffbyte; /* first free byte in EFBLK */N unsigned char fat$b_bktsize; /* bucket size in blocks */d unsigned char fat$ 2b_vfcsize; /* size in bytes of fixed length control for VFC records */N unsigned short int fat$w_maxrec; /* maximum record size in bytes */N unsigned short int fat$w_defext; /* default extend quantity */ __union {Q unsigned short int fat$w_gbc; /* global buffer count (original word) */N unsigned short int fat$w_gbc16; /* Alias */ } fat$r_gbc16_overlay; __union {P unsigned char fat$b_recattr_fl3ags; /* flags for record attribute area */ __struct {f unsigned fat$v_gbc_percent : 1; /* Interpret value in GBC32 as percent instead of count */f unsigned fat$v_gbc_default : 1; /* RMS should set default for GBC at runtime and ignore */N/* any values in GBC16 or GBC32 */N unsigned fat$$_fill_4 : 6; /* Reserved for future use */' } fat$r_recattr_flags_bits;& } fat$r_recattr_flags_ 4overlay;a char fat$$_fill_2; /* reserved for future use (possible flags word union) */\ unsigned int fat$l_gbc32; /* longword implementation of global buffer count */Z short int fat$$_fill_3; /* spare space documented as unused in I/O REF */W unsigned short int fat$w_versions; /* default version limit for directory file */ } FAT; #if !defined(__VAXC)3#define fat$b_rtype fat$r_rtype_overlay.fat$b_rtypeD#define fat$v_rtype fat$r_rt5ype_overlay.fat$r_rtype_bits.fat$v_rtypeH#define fat$v_fileorg fat$r_rtype_overlay.fat$r_rtype_bits.fat$v_fileorg9#define fat$b_rattrib fat$r_rattrib_overlay.fat$b_rattribP#define fat$v_fortrancc fat$r_rattrib_overlay.fat$r_rattrib_bits.fat$v_fortranccP#define fat$v_impliedcc fat$r_rattrib_overlay.fat$r_rattrib_bits.fat$v_impliedccL#define fat$v_printcc fat$r_rattrib_overlay.fat$r_rattrib_bits.fat$v_printccJ#define fat$v_nospan fat$r_rattrib_overlay.fat$r_rattrib_bits.fat$v_nospanJ#define fat$6v_msbrcw fat$r_rattrib_overlay.fat$r_rattrib_bits.fat$v_msbrcwC#define fat$b_special_type fat$r_rattrib_overlay.fat$b_special_type3#define fat$l_hiblk fat$r_hiblk_overlay.fat$l_hiblkH#define fat$w_hiblkh fat$r_hiblk_overlay.fat$r_hiblk_fields.fat$w_hiblkhH#define fat$w_hiblkl fat$r_hiblk_overlay.fat$r_hiblk_fields.fat$w_hiblkl3#define fat$l_efblk fat$r_efblk_overlay.fat$l_efblkH#define fat$w_efblkh fat$r_efblk_overlay.fat$r_efblk_fields.fat$w_efblkhH#define fat$w_efblkl fat$r_efblk_overlay.f 7at$r_efblk_fields.fat$w_efblkl/#define fat$w_gbc fat$r_gbc16_overlay.fat$w_gbc3#define fat$w_gbc16 fat$r_gbc16_overlay.fat$w_gbc16K#define fat$b_recattr_flags fat$r_recattr_flags_overlay.fat$b_recattr_flags`#define fat$v_gbc_percent fat$r_recattr_flags_overlay.fat$r_recattr_flags_bits.fat$v_gbc_percent`#define fat$v_gbc_default fat$r_recattr_flags_overlay.fat$r_recattr_flags_bits.fat$v_gbc_default"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __I8NITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FATDEF_LOADED */ ww![UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confide9ntial proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential : **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************** ;***************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:13 by OpenVMS SDL V3.7 */G/* Source: 11-MAY-1993 13:18:10 $1$DGA8345:[LIB_H.SRC]FBICDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FBICDEF ***/#ifndef __FBICDEF_LOADED#define __FBICDEF_LOADED 1 G#pragma __nostandard /* This file< uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __=unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */I/* Define FBIC offsets and registers for Firefox systems */N/*-- > */N#define FBIC$L_MODTYPE 508 /*Module type */N#define FBIC$L_BUSCSR 504 /*MBUS error status */N#define FBIC$L_BUSCTL 500 /*MBUS error control signal log */N#define FBIC$L_BUSADR 496 /*MBUS error address signal log */N#define FBIC$L_BUSDAT 492 /*MBUS error data signal log */N#define FBIC$L_FBICSR 488 /*FBIC CSR ? */N#define FBIC$L_RANGE 484 /*I/O Space range deco=e */N#define FBIC$L_IPDVINT 480 /*IP/Device interrupt */N#define FBIC$L_WHAMI 476 /*Unique software ID */N#define FBIC$L_CPUID 472 /*Unique hardware ID */N#define FBIC$L_IADR1 468 /*Interlock 1 address */N#define FBIC$L_IADR2 464 /*Interlock 2 address */N#define FB@IC$L_SAVGPR 452 /*Scratch register */N#define FMDC$L_FMDCSR 488 /*FMDC CSR */N#define FMDC$L_BASEADDR 484 /*Memory space base address */N#define FMDC$L_ECCADDR0 480 /*ECC error address (QW0) */N#define FMDC$L_ECCADDR1 476 /*ECC error address (QW1) */N#define FMDC$L_ECCSYND0 472 /*ECC error status (QW0) */N#define FMDC$L_ECCSYND1 468 A /*ECC error status (QW1) */N#define FMDC$L_MSECTERR 464 /*Memory section */N#define FMDC$L_MBUSSIG 460 /*MBUS control signature */N#define FMDC$L_DRAMSIG 456 /*DRAM control signature */N#define FMDC$L_SELFSIG 452 /*Self test signature */N#define FMDC$L_LEDLATCH 448 /*Diagnostic LED latch */ typedef struct _modtype {N unsigned fbic$v_modtype_cl Bass : 8; /* Class of module */N unsigned fbic$v_modtype_subclass : 8; /* Low bit echoes TYPDUAL */N unsigned fbic$v_modtype_interface : 8; /* FBIC interface == 1 */N unsigned fbic$v_modtype_revision : 8; /* FBIC hardware revision */ } MODTYPE;N#define KA60$K_MODTYPE_FBIC 1 /* 1 FBIC interface */N#define KA60$K_MODTYPE_FMDC 2 /* 2 FMDC interface */#define KA60$K_MODTYPE_FMCM 254"#definCe FBIC$M_BUSCSR_DBLE 0x10000"#define FBIC$M_BUSCSR_SERR 0x20000"#define FBIC$M_BUSCSR_CTPE 0x40000"#define FBIC$M_BUSCSR_CDPE 0x80000"#define FBIC$M_BUSCSR_CTO 0x100000"#define FBIC$M_BUSCSR_NOS 0x200000"#define FBIC$M_BUSCSR_MTO 0x400000##define FBIC$M_BUSCSR_ILCK 0x800000$#define FBIC$M_BUSCSR_MCPE 0x1000000$#define FBIC$M_BUSCSR_MSPE 0x2000000$#define FBIC$M_BUSCSR_MDPE 0x4000000$#define FBIC$M_BUSCSR_MTPE 0x8000000%#define FBIC$M_BUSCSR_IDAT 0x10000000%#define FBIC$M_BUSCSR_ICMD 0x2 D0000000$#define FBIC$M_BUSCSR_ARB 0x40000000%#define FBIC$M_BUSCSR_FRZN 0x80000000 typedef struct _buscsr {$ unsigned fbic$v_buscsr_mbz : 16;N unsigned fbic$v_buscsr_dble : 1; /*MBUS double error bit */N unsigned fbic$v_buscsr_serr : 1; /*SERR */N unsigned fbic$v_buscsr_ctpe : 1; /*CDAL tag store parity error */N unsigned fbic$v_buscsr_cdpe : 1; /*CDAL parity error */N unsigned fbic$v_buscsr_ctoE : 1; /*CDAL timeout */N unsigned fbic$v_buscsr_nos : 1; /*MBUS no slave response */N unsigned fbic$v_buscsr_mto : 1; /*MBUS slave timeout */N unsigned fbic$v_buscsr_ilck : 1; /*MBUS interlock violation */N unsigned fbic$v_buscsr_mcpe : 1; /*MBUS MCMD parity error */N unsigned fbic$v_buscsr_mspe : 1; /*MBUS MSTATUS parity error */N unsigned fbic$v_buscsr_mdpe : 1; /*MBUS MDAL pari Fty error */N unsigned fbic$v_buscsr_mtpe : 1; /*MBUS tag parity error */N unsigned fbic$v_buscsr_idat : 1; /*MBUS invalid data supplied */N unsigned fbic$v_buscsr_icmd : 1; /*MBUS invalid MCMD encoding */N unsigned fbic$v_buscsr_arb : 1; /*MBUS arbitration error */N unsigned fbic$v_buscsr_frzn : 1; /*MBUS error logging frozen */ } BUSCSR;#define FBIC$M_BUSCTL_MBRM 0x7F#define FBIC$M_BUSCTL_MBRP 0x80G #define FBIC$M_BUSCTL_MBRQ 0x100!#define FBIC$M_BUSCTL_MCMD 0x1E00"#define FBIC$M_BUSCTL_MCPAR 0x2000$#define FBIC$M_BUSCTL_MSTATUS 0xC000##define FBIC$M_BUSCTL_MSPAR 0x10000##define FBIC$M_BUSCTL_MDPAR 0x20000##define FBIC$M_BUSCTL_MBUSY 0x40000%#define FBIC$M_BUSCTL_MSHARED 0x80000&#define FBIC$M_BUSCTL_MDATINV 0x100000%#define FBIC$M_BUSCTL_MABORT 0x200000$#define FBIC$M_BUSCTL_MHALT 0x400000%#define FBIC$M_BUSCTL_PHASE 0x3800000%#define FBIC$M_BUSCTL_SLAVE 0x4000000&#define HFBIC$M_BUSCTL_MASTER 0x8000000(#define FBIC$M_BUSCTL_SVDMCMD 0xF0000000 typedef struct _busctl {N unsigned fbic$v_busctl_mbrm : 7; /* MBRM signals */N unsigned fbic$v_busctl_mbrp : 1; /* MBRP signal */N unsigned fbic$v_busctl_mbrq : 1; /* MBRQ signal */N unsigned fbic$v_busctl_mcmd : 4; /* MCMD signals */N unsigned fbic$v_busctl_mcpar : 1; /* MCPAR signal */N I unsigned fbic$v_busctl_mstatus : 2; /* MSTATUS signal */N unsigned fbic$v_busctl_mspar : 1; /* MSPAR */N unsigned fbic$v_busctl_mdpar : 1; /* MDPAR */N unsigned fbic$v_busctl_mbusy : 1; /* MBUSY */N unsigned fbic$v_busctl_mshared : 1; /* MSHARED */N unsigned fbic$v_busctl_mdatinv : 1; /* MDATINV */N unsigned fbic$v_busctl_m Jabort : 1; /* MABORT */N unsigned fbic$v_busctl_mhalt : 1; /* MHALT */N unsigned fbic$v_busctl_phase : 3; /* BUS PHASE */N unsigned fbic$v_busctl_slave : 1; /* SLAVE */N unsigned fbic$v_busctl_master : 1; /* MASTER */N unsigned fbic$v_busctl_svdmcmd : 4; /* MCMD signal */ } BUSCTL;#define FBIC$M_FBICSR_CDPE 0x1!#definKe FBIC$M_FBICSR_TSTFNC 0x3E!#define FBIC$M_FBICSR_HALTEN 0x80!#define FBIC$M_FBICSR_LEDS 0x3F00$#define FBIC$M_FBICSR_IRQC2M 0xF0000$#define FBIC$M_FBICSR_IRQEN 0xF00000%#define FBIC$M_FBICSR_RESET 0x1000000'#define FBIC$M_FBICSR_HALTCPU 0x2000000&#define FBIC$M_FBICSR_EXCAEN 0x4000000%#define FBIC$M_FBICSR_CMISS 0x8000000%#define FBIC$M_FBICSR_MFMD 0xC0000000 typedef struct _fbicsr {N unsigned fbic$v_fbicsr_cdpe : 1; /*CBUS parity check enable */N unsigned fbiLc$v_fbicsr_tstfnc : 5; /*Diagnostic test function */N unsigned fbic$v_fbicsr_mbz0 : 1; /* Must be zero */N unsigned fbic$v_fbicsr_halten : 1; /*Enable CPU halts */N unsigned fbic$v_fbicsr_leds : 6; /*FBIC LED output */N unsigned fbic$v_fbicsr_mbz1 : 2; /* Must be zero */N unsigned fbic$v_fbicsr_irqc2m : 4; /*Interrupt request direction */N unsigned fbic$v_fbicsr_irqen : 4; /*MInterrupt request enable */N unsigned fbic$v_fbicsr_reset : 1; /*CBUS RESET */N unsigned fbic$v_fbicsr_haltcpu : 1; /*CBUS halt control */N unsigned fbic$v_fbicsr_excaen : 1; /*External cache enable */N unsigned fbic$v_fbicsr_cmiss : 1; /*CBUS cache miss occurred */N unsigned fbic$v_fbicsr_mbz2 : 2; /* Must be zero */N unsigned fbic$v_fbicsr_mfmd : 2; /*Manufacturing mode N */ } FBICSR; #define FBIC$M_RANGE_MASK 0x7FFF"#define FBIC$M_RANGE_ENABLE 0x8000%#define FBIC$M_RANGE_MATCH 0xFFFF0000 typedef struct _range {N unsigned fbic$v_range_mask : 15; /*I/O space address range mask */N unsigned fbic$v_range_enable : 1; /*I/O space address range enable */N unsigned fbic$v_range_match : 16; /*I/O space address range match */ } RANGE;$#define FBIC$M_IPDVINT_VECTOR 0xFFFF&#define FBIC$M_IPDVINT_DEVUNIT 0x10000%#defin Oe FBIC$M_IPDVINT_IPUNIT 0x20000&#define FBIC$M_IPDVINT_IPL14 0x1000000&#define FBIC$M_IPDVINT_IPL15 0x2000000&#define FBIC$M_IPDVINT_IPL16 0x4000000&#define FBIC$M_IPDVINT_IPL17 0x8000000 typedef struct _ipdvint {N unsigned fbic$v_ipdvint_vector : 16; /*Interrupt vector */N unsigned fbic$v_ipdvint_devunit : 1; /*Device interrupt unit */N unsigned fbic$v_ipdvint_ipunit : 1; /*I/P interrupt unit */$ unsigned fbic$v_ipdvint_mbz : 6;N P unsigned fbic$v_ipdvint_ipl14 : 1; /*Generate IPL 14 interrupt */N unsigned fbic$v_ipdvint_ipl15 : 1; /*Generate IPL 15 interrupt */N unsigned fbic$v_ipdvint_ipl16 : 1; /*Generate IPL 16 interrupt */N unsigned fbic$v_ipdvint_ipl17 : 1; /*Generate IPL 17 interrupt */ unsigned fbic$v_fill_0_ : 4; } IPDVINT;#define FBIC$M_CPUID_PROC 0x3#define FBIC$M_CPUID_MID 0xC typedef struct _cpuid {N unsigned fbic$v_cpuid_proc : 2; /*ProcQessor identifier */N unsigned fbic$v_cpuid_mid : 2; /*Module slot identifier */ unsigned fbic$v_fill_1_ : 4; } CPUID;"#define FMDC$M_FMDCSR_RAS_CNT 0xFF$#define FMDC$M_FMDCSR_ST_START 0x100##define FMDC$M_FMDCSR_ST_DONE 0x200 #define FMDC$M_FMDCSR_DTCB 0x400(#define FMDC$M_FMDCSR_DIS_REFRESH 0x1000 #define FMDC$M_FMDCSR_RPS 0x2000 #define FMDC$M_FMDCSR_DRS 0x4000!#define FMDC$M_FMDCSR_EDM 0x18000"#define FMDC$M_FMDCSR_FESC 0x60000"#define FMDC$M_F RMDCSR_FEC 0x380000"#define FMDC$M_FMDCSR_ISR 0x400000##define FMDC$M_FMDCSR_ISML 0x800000$#define FMDC$M_FMDCSR_MOL 0x40000000$#define FMDC$M_FMDCSR_EFS 0x80000000 typedef struct _fmdcsr {N unsigned fmdc$v_fmdcsr_ras_cnt : 8; /* Refresh counter */N unsigned fmdc$v_fmdcsr_st_start : 1; /* Self test start */N unsigned fmdc$v_fmdcsr_st_done : 1; /* Self test complete */N unsigned fmdc$v_fmdcsr_dtcb : 1; /* Data to check bits S */$ unsigned fmdc$v_fmdcsr_mbz1 : 1;N unsigned fmdc$v_fmdcsr_dis_refresh : 1; /* Disable refresh */N unsigned fmdc$v_fmdcsr_rps : 1; /* Refresh period select */N unsigned fmdc$v_fmdcsr_drs : 1; /* Diagnostic refresh start */N unsigned fmdc$v_fmdcsr_edm : 2; /* ECC diagnostic mode */N unsigned fmdc$v_fmdcsr_fesc : 2; /* Force error sub category */N unsigned fmdc$v_fmdcsr_fec : 3; /* Force error T category */N unsigned fmdc$v_fmdcsr_isr : 1; /* Inhibit SBE reporting */N unsigned fmdc$v_fmdcsr_isml : 1; /* Inhibit SBE MSECTERR log */$ unsigned fmdc$v_fmdcsr_mbz2 : 6;N unsigned fmdc$v_fmdcsr_mol : 1; /* Module on-line */N unsigned fmdc$v_fmdcsr_efs : 1; /* Error flag summary */ } FMDCSR;,#define FMDC$M_BASEADDR_STARTADDR 0x7FF00000*#define FMDC$M_BASEADDR_MEMSPEN 0x80000000 typedef stru Uct _baseaddr {& unsigned fmdc$v_baseaddr_mbz : 20;N unsigned fmdc$v_baseaddr_startaddr : 11; /* Starting memory address */N unsigned fmdc$v_baseaddr_memspen : 1; /* Memory space enable */ } BASEADDR;,#define FMDC$M_ECCADDR_RAMERRADDR0 0x7FFFFF0 typedef struct _eccaddr {$ unsigned fmdc$v_eccaddr_mbz : 4;N unsigned fmdc$v_eccaddr_ramerraddr0 : 23; /* ECC Error address */ unsigned fmdc$v_fill_2_ : 5; } ECCADDR;!#define FMDC$M_ECCSYND_SYN VD0 0xFF #define FMDC$M_ECCSYND_SBE 0x100 #define FMDC$M_ECCSYND_MBE 0x200%#define FMDC$M_ECCSYND_ERROVFL 0x1C00%#define FMDC$M_ECCSYND_SUBCB 0xFF0000(#define FMDC$M_ECCSYND_READCB 0xFF000000 typedef struct _eccsynd {N unsigned fmdc$v_eccsynd_synd0 : 8; /* ECC syndronme */N unsigned fmdc$v_eccsynd_sbe : 1; /* Single bit error */N unsigned fmdc$v_eccsynd_mbe : 1; /* Multiple bit error */N unsigned fmdc$v_eccsynd_errovf Wl : 3; /* Error overflow field */$ unsigned fmdc$v_eccsynd_mbz : 3;N unsigned fmdc$v_eccsynd_subcb : 8; /* Substitute check bits */N unsigned fmdc$v_eccsynd_readcb : 8; /* Read check bits */ } ECCSYND; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplXusplus }#endif#pragma __standard #endif /* __FBICDEF_LOADED */ ww"[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/YM/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written peZrmission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:14 by OpenVMS SDL V3.7 */G/* Source: 22 [-MAR-1993 14:38:24 $1$DGA8345:[LIB_H.SRC]FBUSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FBUSDEF ***/#ifndef __FBUSDEF_LOADED#define __FBUSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pra\gma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifn ]def __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */P/* This file describes the layout of Futurebus CSR space. The information is */O/* based on the IEEE Futurebus specification 896.2 and IEEE CSR Architecture */N/* specification P1212. */N/*- ^ */%#define FBUS$M_TEST_STATUS_FAILED 0x1&#define FBUS$M_TEST_STATUS_TIMEOUT 0x2*#define FBUS$M_TEST_STATUS_IMPLEMENTED 0x4&#define FBUS$M_TEST_STATUS_LOOPING 0x8&#define FBUS$M_TEST_STATUS_ACTIVE 0x10(#define FBUS$M_TEST_STATUS_RESERVED 0x20(#define FBUS$M_TEST_STATUS_STEP 0x3FFFC0(#define FBUS$M_TEST_STATUS_FRU 0xFC00000)#define FBUS$M_TEST_STATUS_CAT 0xF0000000(#define FBUS$M_ROM_BASE_CRC_VALUE 0xFFFF+#define FBUS$M_ROM_BASE_CRC_LENGTH 0xFF00002#define FBUS$M_ROM_BASE_BU _S_INFO_LENGTH 0xFF000000'#define FBUS$M_ROOT_DIR_BASE_CRC 0xFFFF.#define FBUS$M_ROOT_DIR_BASE_LENGTH 0xFFFF0000%#define FBUS$K_NODE_SPACE_LENGTH 4096U#define FBUS$S_FBUSDEF 4096 /* Old size name, synonym for FBUS$S_FBUS */ typedef struct _fbus {S/* The following definitions are for CORE CSR space, required by a all Futurebus */N/* nodes. */#if defined(__VAXC) char fbus$l_csr_core[];#else2#define `fbus$l_csr_core fbus$r_state_clear_overlay"#endif /* #if defined(__VAXC) */N __union { /* State Clear register */( unsigned int fbus$l_state_clear; __struct {2 unsigned fbus$v_state_clear_fill : 32;( } fbus$r_state_clear_fields;% } fbus$r_state_clear_overlay;N __union { /* State Set register */& unsigned int fbus$l_state_set; __struct {0 a unsigned fbus$v_state_set_fill : 32;& } fbus$r_state_set_fields;# } fbus$r_state_set_overlay;N __union { /* Node IDs register */% unsigned int fbus$l_node_ids; __struct {/ unsigned fbus$v_node_ids_fill : 32;% } fbus$r_node_ids_fields;" } fbus$r_node_ids_overlay;N __union { /* Reset Start register */( unsigned int fbus$l_reset_st bart; __struct {2 unsigned fbus$v_reset_start_fill : 32;( } fbus$r_reset_start_fields;% } fbus$r_reset_start_overlay;N __union { /* Indirect Address register */- unsigned int fbus$l_indirect_address; __struct {7 unsigned fbus$v_indirect_address_fill : 32;- } fbus$r_indirect_address_fields;* } fbus$r_indirect_address_overlay;N __union { /* I cndirect Data register */* unsigned int fbus$l_indirect_data; __struct {4 unsigned fbus$v_indirect_data_fill : 32;* } fbus$r_indirect_data_fields;' } fbus$r_indirect_data_overlay;N __union { /* Split Timeout Hi register */- unsigned int fbus$l_split_timeout_hi; __struct {7 unsigned fbus$v_split_timeout_hi_fill : 32;- } fbus$r_split_timeout_hi_fields;* d} fbus$r_split_timeout_hi_overlay;N __union { /* Split Timeout Lo register */- unsigned int fbus$l_split_timeout_lo; __struct {7 unsigned fbus$v_split_timeout_lo_fill : 32;- } fbus$r_split_timeout_lo_fields;* } fbus$r_split_timeout_lo_overlay;N __union { /* Argument Hi register */( unsigned int fbus$l_argument_hi; __struct {2 unsigned fbus$ ev_argument_hi_fill : 32;( } fbus$r_argument_hi_fields;% } fbus$r_argument_hi_overlay;N __union { /* Argument Lo register */( unsigned int fbus$l_argument_lo; __struct {2 unsigned fbus$v_argument_lo_fill : 32;( } fbus$r_argument_lo_fields;% } fbus$r_argument_lo_overlay;N __union { /* Test Start register */' unsigned int fbus$l_test_start; f __struct {1 unsigned fbus$v_test_start_fill : 32;' } fbus$r_test_start_fields;$ } fbus$r_test_start_overlay;N __union { /* Test Status register */( unsigned int fbus$l_test_status; __struct {3 unsigned fbus$v_test_status_failed : 1;4 unsigned fbus$v_test_status_timeout : 1;8 unsigned fbus$v_test_status_implemented : 1;4 unsigned fbus$v_test_status_ glooping : 1;3 unsigned fbus$v_test_status_active : 1;5 unsigned fbus$v_test_status_reserved : 1;2 unsigned fbus$v_test_status_step : 16;0 unsigned fbus$v_test_status_fru : 6;0 unsigned fbus$v_test_status_cat : 4;( } fbus$r_test_status_fields;% } fbus$r_test_status_overlay;N __union { /* Units Base Hi register */* unsigned int fbus$l_units_base_hi; __struct {4 h unsigned fbus$v_units_base_hi_fill : 32;* } fbus$r_units_base_hi_fields;' } fbus$r_units_base_hi_overlay;N __union { /* Units Base Lo register */* unsigned int fbus$l_units_base_lo; __struct {4 unsigned fbus$v_units_base_lo_fill : 32;* } fbus$r_units_base_lo_fields;' } fbus$r_units_base_lo_overlay;N __union { /* Units Bound Hi register */+ i unsigned int fbus$l_units_bound_hi; __struct {5 unsigned fbus$v_units_bound_hi_fill : 32;+ } fbus$r_units_bound_hi_fields;( } fbus$r_units_bound_hi_overlay;N __union { /* Units Bound Lo register */+ unsigned int fbus$l_units_bound_lo; __struct {5 unsigned fbus$v_units_bound_lo_fill : 32;+ } fbus$r_units_bound_lo_fields;( } fbus$r_units_bound_lo_overlay;N j__union { /* Memory Base Hi register */+ unsigned int fbus$l_memory_base_hi; __struct {5 unsigned fbus$v_memory_base_hi_fill : 32;+ } fbus$r_memory_base_hi_fields;( } fbus$r_memory_base_hi_overlay;N __union { /* Memory Base Lo register */+ unsigned int fbus$l_memory_base_lo; __struct {5 unsigned fbus$v_memory_base_lo_fill : 32;+ } kfbus$r_memory_base_lo_fields;( } fbus$r_memory_base_lo_overlay;N __union { /* Memory Bound Hi register */, unsigned int fbus$l_memory_bound_hi; __struct {6 unsigned fbus$v_memory_bound_hi_fill : 32;, } fbus$r_memory_bound_hi_fields;) } fbus$r_memory_bound_hi_overlay;N __union { /* Memory Bound Lo register */, unsigned int fbus$l_memory_bound_lo; __st lruct {6 unsigned fbus$v_memory_bound_lo_fill : 32;, } fbus$r_memory_bound_lo_fields;) } fbus$r_memory_bound_lo_overlay;N __union { /* Interrupt Target register */- unsigned int fbus$l_interrupt_target; __struct {7 unsigned fbus$v_interrupt_target_fill : 32;- } fbus$r_interrupt_target_fields;* } fbus$r_interrupt_target_overlay;N __union { /* Interru mpt Mask register */+ unsigned int fbus$l_interrupt_mask; __struct {5 unsigned fbus$v_interrupt_mask_fill : 32;+ } fbus$r_interrupt_mask_fields;( } fbus$r_interrupt_mask_overlay;N __union { /* Clock Value Hi register */+ unsigned int fbus$l_clock_value_hi; __struct {5 unsigned fbus$v_clock_value_hi_fill : 32;+ } fbus$r_clock_value_hi_fields;( } fbus n$r_clock_value_hi_overlay;N __union { /* Clock Value Mid register */, unsigned int fbus$l_clock_value_mid; __struct {6 unsigned fbus$v_clock_value_mid_fill : 32;, } fbus$r_clock_value_mid_fields;) } fbus$r_clock_value_mid_overlay;N __union { /* Clock Tick Period Mid register */2 unsigned int fbus$l_clock_tick_period_mid; __struct {< unsigned fbus$v_cl oock_tick_period_mid_fill : 32;1 } fbus$r_clock_tick_period_mid_field;- } fbus$r_clock_tick_period_mid_overl;N __union { /* Clock Tick Period Lo register */1 unsigned int fbus$l_clock_tick_period_lo; __struct {; unsigned fbus$v_clock_tick_period_lo_fill : 32;1 } fbus$r_clock_tick_period_lo_fields;- } fbus$r_clock_tick_period_lo_overla;N __union { /* Clock Strobe Ar prived Hi register */4 unsigned int fbus$l_clock_strobe_arrived_hi; __struct {= unsigned fbus$v_clock_strobe_arrived_hi_fil : 32;1 } fbus$r_clock_strobe_arrived_hi_fie;- } fbus$r_clock_strobe_arrived_hi_ove;O __union { /* Clock Strobe Arrived Mid register */5 unsigned int fbus$l_clock_strobe_arrived_mid; __struct {= unsigned fbus$v_clock_strobe_arrived_mid_fi : 32;1 } fbus$r q_clock_strobe_arrived_mid_fi;- } fbus$r_clock_strobe_arrived_mid_ov;N __union { /* Clock Strobe register */) unsigned int fbus$l_clock_strobe; __struct {3 unsigned fbus$v_clock_strobe_fill : 32;) } fbus$r_clock_strobe_fields;& } fbus$r_clock_strobe_overlay;N __union { /* Clock Info1 register */( unsigned int fbus$l_clock_info1; __struct { r2 unsigned fbus$v_clock_info1_fill : 32;( } fbus$r_clock_info1_fields;% } fbus$r_clock_info1_overlay;N __union { /* Clock Reference register */, unsigned int fbus$l_clock_reference; __struct {6 unsigned fbus$v_clock_reference_fill : 32;, } fbus$r_clock_reference_fields;) } fbus$r_clock_reference_overlay;N __union { /* Clock Info 3 register s*/( unsigned int fbus$l_clock_info3; __struct {2 unsigned fbus$v_clock_info3_fill : 32;( } fbus$r_clock_info3_fields;% } fbus$r_clock_info3_overlay;N unsigned int fbus$l_message_request [16]; /* Message Request area */N unsigned int fbus$l_message_response [16]; /* Message Response area */N unsigned int fbus$l_p1212_reserved [32]; /* Reserved by P1212 */ __union {% unsigned int fbus$l_error_hi; t__struct {/ unsigned fbus$v_error_hi_fill : 32;% } fbus$r_error_hi_fields;" } fbus$r_error_hi_overlay; __union {% unsigned int fbus$l_error_lo; __struct {/ unsigned fbus$v_error_lo_fill : 32;% } fbus$r_error_lo_fields;" } fbus$r_error_lo_overlay; __union {$ unsigned int fbus$l_fadr_hi; __struct {. unsigned fbus$v_fadr_hi_fill : 32;$ } fbus$r_fadr_hi_fields;!u } fbus$r_fadr_hi_overlay; __union {$ unsigned int fbus$l_fadr_lo; __struct {. unsigned fbus$v_fadr_lo_fill : 32;$ } fbus$r_fadr_lo_fields;! } fbus$r_fadr_lo_overlay;. unsigned int fbus$l_error_log_buffer [28];N/* The following definitions describe the Futurebus dependent CSR area */#if defined(__VAXC) char fbus$l_bus_dependent[];#else?#define fbus$l_bus_dependent fbus$r_logical_common_control_over"#endif /* #if v defined(__VAXC) */N __union { /* Logical Common Control register */3 unsigned int fbus$l_logical_common_control; __struct {= unsigned fbus$v_logical_common_control_fill : 32;1 } fbus$r_logical_common_control_fiel;- } fbus$r_logical_common_control_over;N __union { /* Logical Module Control register */3 unsigned int fbus$l_logical_module_control; __struct {= w unsigned fbus$v_logical_module_control_fill : 32;1 } fbus$r_logical_module_control_fiel;- } fbus$r_logical_module_control_over;N __union { /* Bus Propagation Delay register */+ unsigned int fbus$l_bus_prop_delay; __struct {5 unsigned fbus$v_bus_prop_delay_fill : 32;+ } fbus$r_bus_prop_delay_fields;( } fbus$r_bus_prop_delay_overlay;P __union { /* Competition Set xtling Time register *// unsigned int fbus$l_comp_settling_time; __struct {9 unsigned fbus$v_comp_settling_time_fill : 32;/ } fbus$r_comp_settling_time_fields;, } fbus$r_comp_settling_time_overlay;N __union { /* Transaction Timeout register */0 unsigned int fbus$l_transaction_timeout; __struct {: unsigned fbus$v_transaction_timeout_fill : 32;0 } fbus$r_transaction_timeout_f yields;- } fbus$r_transaction_timeout_overlay;N __union { /* Message Passing Select Mask *// unsigned int fbus$l_msg_select_mask_hi; __struct {9 unsigned fbus$v_msg_select_mask_hi_fill : 32;/ } fbus$r_msg_select_mask_hi_fields;, } fbus$r_msg_select_mask_overlay_hi; __union {/ unsigned int fbus$l_msg_select_mask_lo; __struct {9 unsigned fbus$v_msg_select_mask_lo_fill : z32;/ } fbus$r_msg_select_mask_lo_fields;, } fbus$r_msg_select_mask_overlay_lo;N __union { /* Busy Retry Counter */- unsigned int fbus$l_bsy_rtry_counter; __struct {7 unsigned fbus$v_bsy_rtry_counter_fill : 32;- } fbus$r_bsy_rtry_counter_fields;* } fbus$r_bsy_rtry_counter_overlay;N __union { /* Busy Retry Delay */+ unsigned int fbu {s$l_bsy_rtry_delay; __struct {5 unsigned fbus$v_bsy_rtry_delay_fill : 32;+ } fbus$r_bsy_rtry_delay_fields;( } fbus$r_bsy_rtry_delay_overlay;N __union { /* Error Retry Counter */- unsigned int fbus$l_err_rtry_counter; __struct {7 unsigned fbus$v_err_rtry_counter_fill : 32;- } fbus$r_err_rtry_counter_fields;* } fbus$r_err_rtry_counter_overlay;N __union { | /* Error Retry Delay */+ unsigned int fbus$l_err_rtry_delay; __struct {5 unsigned fbus$v_err_rtry_delay_fill : 32;+ } fbus$r_err_rtry_delay_fields;( } fbus$r_err_rtry_delay_overlay;4 unsigned int fbus$l_bus_dependent_reserved [53];. unsigned int fbus$l_vendor_dependent [64];N/* The following definitions describe the Futurebus ROM area. */N __union { /* ROM Bas }e starting location */% unsigned int fbus$l_rom_base; __struct {4 unsigned fbus$v_rom_base_crc_value : 16;4 unsigned fbus$v_rom_base_crc_length : 8;9 unsigned fbus$v_rom_base_bus_info_length : 8;% } fbus$r_rom_base_fields;" } fbus$r_rom_base_overlay;N __union { /* Bus Id location */# unsigned int fbus$l_bus_id; __struct {- unsigned fbus$v_bu ~s_id_fill : 32;# } fbus$r_bus_id_fields; } fbus$r_bus_id_overlay;N __union { /* Profile ID */* unsigned int fbus$l_profile_id_hi; __struct {4 unsigned fbus$v_profile_id_hi_fill : 32;* } fbus$r_profile_id_hi_fields;' } fbus$r_profile_id_hi_overlay; __union {* unsigned int fbus$l_profile_id_lo; __struct {4 unsigned fbus$v_profile_id_lo_fill :  32;* } fbus$r_profile_id_lo_fields;' } fbus$r_profile_id_lo_overlay;N __union { /* Module Logical Capability */( unsigned int fbus$l_mod_log_cap; __struct {2 unsigned fbus$v_mod_log_cap_fill : 32;( } fbus$r_mod_log_cap_fields;% } fbus$r_mod_log_cap_overlay;N __union { /* Node Capabilities Ext */) unsigned int fbus$l_node_cap_ext; __st ruct {3 unsigned fbus$v_node_cap_ext_fill : 32;) } fbus$r_node_cap_ext_fields;& } fbus$r_node_cap_ext_overlay;N __union { /* Competition Internal Delay */+ unsigned int fbus$l_comp_int_delay; __struct {5 unsigned fbus$v_comp_int_delay_fill : 32;+ } fbus$r_comp_int_delay_fields;( } fbus$r_comp_int_delay_overlay;N __union { /* Packet Speed register  */) unsigned int fbus$l_packet_speed; __struct {3 unsigned fbus$v_packet_speed_fill : 32;) } fbus$r_packet_speed_fields;& } fbus$r_packet_speed_overlay;N __union { /* Message Frame Size */+ unsigned int fbus$l_msg_frame_size; __struct {5 unsigned fbus$v_msg_frame_size_fill : 32;+ } fbus$r_msg_frame_size_fields;( } fbus$r_msg_frame_size_overla y;N __union { /* Busy Retry Counter Capability */1 unsigned int fbus$l_bsy_rtry_counter_cap; __struct {; unsigned fbus$v_bsy_rtry_counter_cap_fill : 32;1 } fbus$r_bsy_rtry_counter_cap_fields;- } fbus$r_bsy_rtry_counter_cap_overla;N __union { /* Busy Retry Delay Capability *// unsigned int fbus$l_bsy_rtry_delay_cap; __struct {9 unsigned fbus$v_bsy_rt ry_delay_cap_fill : 32;/ } fbus$r_bsy_rtry_delay_cap_fields;, } fbus$r_bsy_rtry_delay_cap_overlay;N __union { /* Error Retry Counter Capability */1 unsigned int fbus$l_err_rtry_counter_cap; __struct {; unsigned fbus$v_err_rtry_counter_cap_fill : 32;1 } fbus$r_err_rtry_counter_cap_fields;- } fbus$r_err_rtry_counter_cap_overla;N __union { /* Error Retry Delay Capabil ity *// unsigned int fbus$l_err_rtry_delay_cap; __struct {9 unsigned fbus$v_err_rtry_delay_cap_fill : 32;/ } fbus$r_err_rtry_delay_cap_fields;, } fbus$r_err_rtry_delay_cap_overlay;. unsigned int fbus$l_bus_info_reserved [3];N __union { /* Root Directory base */* unsigned int fbus$l_root_dir_base; __struct {3 unsigned fbus$v_root_dir_base_crc : 16;6 unsigned fbus$v_root_dir_base_length : 16;* } fbus$r_root_dir_base_fields;' } fbus$r_root_dir_base_overlay;- unsigned int fbus$l_rom_space_fill [239];#if defined(__VAXC)+ char fbus$l_initial_units_space_base[];#elseG#define fbus$l_initial_units_space_base fbus$l_initial_units_space_fill"#endif /* #if defined(__VAXC) */7 unsigned int fbus$l_initial_units_space_fill [512]; } FBUS; #if !defined(__VAXC)H#define fbus$l_state_clear fbus$r_state_clear_overlay.fbus$l_state_clearB#define fbus$l_state_set fbus$r_state_set_overlay.fbus$l_state_set?#define fbus$l_node_ids fbus$r_node_ids_overlay.fbus$l_node_idsH#define fbus$l_reset_start fbus$r_reset_start_overlay.fbus$l_reset_startW#define fbus$l_indirect_address fbus$r_indirect_address_overlay.fbus$l_indirect_addressN#define fbus$l_indirect_data fbus$r_indirect_data_overlay.fbus$l_indirect_dataW#define fbus$l_split_timeout_hi fbus$r_split_timeout_hi_overlay.fbus$l_split_timeout_hiW#define fbus$l_split_timeout_lo fbus$r_split_timeout_lo_overlay.fbus$l_split_timeout_loH#define fbus$l_argument_hi fbus$r_argument_hi_overlay.fbus$l_argument_hiH#define fbus$l_argument_lo fbus$r_argument_lo_overlay.fbus$l_argument_loE#define fbus$l_test_start fbus$r_test_start_overlay.fbus$l_test_startH#define fbus$l_test_status fbus$r_test_status_overlay.fbus$l_test_statusp#define fbus$v_test_status_failed fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_failedr#define fbus$v_test_status_timeout fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_timeoutz#define fbus$v_test_status_implemented fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_implementedr#define fbus$v_test_status_looping fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_loopingp#define fbus$v_test_status_active fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_activet#define fbus$v_test_status_reserved fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_reservedl#define fbus$v_test_status_step fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_stepj#define fbus$v_test_status_fru fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_fruj#define fbus$v_test_status_cat fbus$r_test_status_overlay.fbus$r_test_status_fields.fbus$v_test_status_catN#define fbus$l_units_base_hi fbus$r_units_base_hi_overlay.fbus$l_units_base_hiN#define fbus$l_units_base_lo fbus$r_units_base_lo_overlay.fbus$l_units_base_loQ#define fbus$l_units_bound_hi fbus$r_units_bound_hi_overlay.fbus$l_units_bound_hiQ#define fbus$l_units_bound_lo fbus$r_units_bound_lo_overlay.fbus$l_units_bound_loQ#define fbus$l_memory_base_hi fbus$r_memory_base_hi_overlay.fbus$l_memory_base_hiQ#define fbus$l_memory_base_lo fbus$r_memory_base_lo_overlay.fbus$l_memory_base_loT#define fbus$l_memory_bound_hi fbus$r_memory_bound_hi_overlay.fbus$l_memory_bound_hiT#define fbus$l_memory_bound_lo fbus$r_memory_bound_lo_overlay.fbus$l_memory_bound_loW#define fbus$l_interrupt_target fbus$r_interrupt_target_overlay.fbus$l_interrupt_targetQ#define fbus$l_interrupt_mask fbus$r_interrupt_mask_overlay.fbus$l_interrupt_maskQ#define fbus$l_clock_value_hi fbus$r_clock_value_hi_overlay.fbus$l_clock_value_hiT#define fbus$l_clock_value_mid fbus$r_clock_value_mid_overlay.fbus$l_clock_value_midd#define fbus$l_clock_tick_period_mid fbus$r_clock_tick_period_mid_overl.fbus$l_clock_tick_period_midb#define fbus$l_clock_tick_period_lo fbus$r_clock_tick_period_lo_overla.fbus$l_clock_tick_period_loh#define fbus$l_clock_strobe_arrived_hi fbus$r_clock_strobe_arrived_hi_ove.fbus$l_clock_strobe_arrived_hij#define fbus$l_clock_strobe_arrived_mid fbus$r_clock_strobe_arrived_mid_ov.fbus$l_clock_strobe_arrived_midK#define fbus$l_clock_strobe fbus$r_clock_strobe_overlay.fbus$l_clock_strobeH#define fbus$l_clock_info1 fbus$r_clock_info1_overlay.fbus$l_clock_info1T#define fbus$l_clock_reference fbus$r_clock_reference_overlay.fbus$l_clock_referenceH#define fbus$l_clock_info3 fbus$r_clock_info3_overlay.fbus$l_clock_info3?#define fbus$l_error_hi fbus$r_error_hi_overlay.fbus$l_error_hi?#define fbus$l_error_lo fbus$r_error_lo_overlay.fbus$l_error_lo<#define fbus$l_fadr_hi fbus$r_fadr_hi_overlay.fbus$l_fadr_hi<#define fbus$l_fadr_lo fbus$r_fadr_lo_overlay.fbus$l_fadr_lof#define fbus$l_logical_common_control fbus$r_logical_common_control_over.fbus$l_logical_common_controlf#define fbus$l_logical_module_control fbus$r_logical_module_control_over.fbus$l_logical_module_controlQ#define fbus$l_bus_prop_delay fbus$r_bus_prop_delay_overlay.fbus$l_bus_prop_delay]#define fbus$l_comp_settling_time fbus$r_comp_settling_time_overlay.fbus$l_comp_settling_time`#define fbus$l_transaction_timeout fbus$r_transaction_timeout_overlay.fbus$l_transaction_timeout]#define fbus$l_msg_select_mask_hi fbus$r_msg_select_mask_overlay_hi.fbus$l_msg_select_mask_hi]#define fbus$l_msg_select_mask_lo fbus$r_msg_select_mask_overlay_lo.fbus$l_msg_select_mask_loW#define fbus$l_bsy_rtry_counter fbus$r_bsy_rtry_counter_overlay.fbus$l_bsy_rtry_counterQ#define fbus$l_bsy_rtry_delay fbus$r_bsy_rtry_delay_overlay.fbus$l_bsy_rtry_delayW#define fbus$l_err_rtry_counter fbus$r_err_rtry_counter_overlay.fbus$l_err_rtry_counterQ#define fbus$l_err_rtry_delay fbus$r_err_rtry_delay_overlay.fbus$l_err_rtry_delay?#define fbus$l_rom_base fbus$r_rom_base_overlay.fbus$l_rom_basej#define fbus$v_rom_base_crc_value fbus$r_rom_base_overlay.fbus$r_rom_base_fields.fbus$v_rom_base_crc_valuel#define fbus$v_rom_base_crc_length fbus$r_rom_base_overlay.fbus$r_rom_base_fields.fbus$v_rom_base_crc_lengthv#define fbus$v_rom_base_bus_info_length fbus$r_rom_base_overlay.fbus$r_rom_base_fields.fbus$v_rom_base_bus_info_length9#define fbus$l_bus_id fbus$r_bus_id_overlay.fbus$l_bus_idN#define fbus$l_profile_id_hi fbus$r_profile_id_hi_overlay.fbus$l_profile_id_hiN#define fbus$l_profile_id_lo fbus$r_profile_id_lo_overlay.fbus$l_profile_id_loH#define fbus$l_mod_log_cap fbus$r_mod_log_cap_overlay.fbus$l_mod_log_capK#define fbus$l_node_cap_ext fbus$r_node_cap_ext_overlay.fbus$l_node_cap_extQ#define fbus$l_comp_int_delay fbus$r_comp_int_delay_overlay.fbus$l_comp_int_delayK#define fbus$l_packet_speed fbus$r_packet_speed_overlay.fbus$l_packet_speedQ#define fbus$l_msg_frame_size fbus$r_msg_frame_size_overlay.fbus$l_msg_frame_sizeb#define fbus$l_bsy_rtry_counter_cap fbus$r_bsy_rtry_counter_cap_overla.fbus$l_bsy_rtry_counter_cap]#define fbus$l_bsy_rtry_delay_cap fbus$r_bsy_rtry_delay_cap_overlay.fbus$l_bsy_rtry_delay_capb#define fbus$l_err_rtry_counter_cap fbus$r_err_rtry_counter_cap_overla.fbus$l_err_rtry_counter_cap]#define fbus$l_err_rtry_delay_cap fbus$r_err_rtry_delay_cap_overlay.fbus$l_err_rtry_delay_capN#define fbus$l_root_dir_base fbus$r_root_dir_base_overlay.fbus$l_root_dir_baser#define fbus$v_root_dir_base_crc fbus$r_root_dir_base_overlay.fbus$r_root_dir_base_fields.fbus$v_root_dir_base_crcx#define fbus$v_root_dir_base_length fbus$r_root_dir_base_overlay.fbus$r_root_dir_base_fields.fbus$v_root_dir_base_length"#endif /* #if !defined(__VAXC) */ S/* The following definitions describe the format of entries in root directories, */S/* subdirectories, and leaves. Root directories, subdirectories, and leaves are */Q/* basically all the same thing -- an area of ROM space containing information */Y/* about the module, node, or unit. See P1212 for the gory details on directory entry */U/* specification. Briefly, each type of directory contains an initial entry which */N/* indicates the size of the directory followed by one or more entries. */N/* All entries in a directory contain a key in byte 0, which identifies */O/* the type of entry, and a value in bytes 1, 2, and 3. The value can be an */N/* immediate value or a pointer, depending on the key value. */N/* Directory base entry format */"#define FBUS$M_DIR_BASE_CRC 0xFFFF)#define FBUS$M_DIR_BASE_LENGTH 0xFFFF0000Y#define FBUS$S_DIR_BASE_DEF 4 /* Old size name, synonym for FBUS$S_DIR_BASE */ typedef struct _dir_base { __union {% unsigned int fbus$l_dir_base; __struct {. unsigned fbus$v_dir_base_crc : 16;1 unsigned fbus$v_dir_base_length : 16;% } fbus$r_dir_base_fields;" } fbus$r_dir_base_overlay; } DIR_BASE; #if !defined(__VAXC)?#define fbus$l_dir_base fbus$r_dir_base_overlay.fbus$l_dir _base^#define fbus$v_dir_base_crc fbus$r_dir_base_overlay.fbus$r_dir_base_fields.fbus$v_dir_base_crcd#define fbus$v_dir_base_length fbus$r_dir_base_overlay.fbus$r_dir_base_fields.fbus$v_dir_base_length"#endif /* #if !defined(__VAXC) */ '#define FBUS$M_DIR_ENTRY_VALUE 0xFFFFFF'#define FBUS$M_DIR_ENTRY_KEY 0xFF000000Z#define FBUS$S_DIR_ENTRY_DEF 4 /* Old size name, synonym for FBUS$S_DIR_ENTRY */ Ntypedef struct _dir_entry { /* Directory entry format */  __union {& unsigned int fbus$l_dir_entry; __struct {1 unsigned fbus$v_dir_entry_value : 24;. unsigned fbus$v_dir_entry_key : 8;& } fbus$r_dir_entry_fields;# } fbus$r_dir_entry_overlay; } DIR_ENTRY; #if !defined(__VAXC)B#define fbus$l_dir_entry fbus$r_dir_entry_overlay.fbus$l_dir_entryf#define fbus$v_dir_entry_value fbus$r_dir_entry_overlay.fbus$r_dir_entry_fields.fbus$v_dir_entry_valueb#define fbus$v_dir_entry_key fbus$ r_dir_entry_overlay.fbus$r_dir_entry_fields.fbus$v_dir_entry_key"#endif /* #if !defined(__VAXC) */ N/* The following definition describes the Digital implementation of ROM */N/* directory entry MODULE_SW_VERSION */*#define FBUS$M_DIGITAL_SW_VERSION_NODE 0x1+#define FBUS$M_DIGITAL_SW_VERSION_UNIT 0x3E,#define FBUS$M_DIGITAL_SW_VERSION_VAR 0x3FC0.#define FBUS$M_DIGITAL_SW_VERSION_NUM 0xFFC0000#define FBUS$M_DIGITAL_SW_VERSION_KEY 0xFF000000c#defin e FBUS$S_DIGITAL_SW_VERSION_DEF 4 /* Old size name, synonym for FBUS$S_DIGITAL_SW_VERSION */ $typedef struct _digital_sw_version { __union {/ unsigned int fbus$l_digital_sw_version; __struct {8 unsigned fbus$v_digital_sw_version_node : 1;8 unsigned fbus$v_digital_sw_version_unit : 5;7 unsigned fbus$v_digital_sw_version_var : 8;8 unsigned fbus$v_digital_sw_version_num : 10;7 unsigned fbus$v_digital_sw_version_k ey : 8;/ } fbus$r_digital_sw_version_fields;, } fbus$r_digital_sw_version_overlay; } DIGITAL_SW_VERSION; #if !defined(__VAXC)]#define fbus$l_digital_sw_version fbus$r_digital_sw_version_overlay.fbus$l_digital_sw_version#define fbus$v_digital_sw_version_node fbus$r_digital_sw_version_overlay.fbus$r_digital_sw_version_fields.fbus$v_digital_sw_version\_node#define fbus$v_digital_sw_version_unit fbus$r_digital_sw_version_overlay.fbus$r_digital_sw_version_fields.fb us$v_digital_sw_version\_unit#define fbus$v_digital_sw_version_var fbus$r_digital_sw_version_overlay.fbus$r_digital_sw_version_fields.fbus$v_digital_sw_version_\var#define fbus$v_digital_sw_version_num fbus$r_digital_sw_version_overlay.fbus$r_digital_sw_version_fields.fbus$v_digital_sw_version_\num#define fbus$v_digital_sw_version_key fbus$r_digital_sw_version_overlay.fbus$r_digital_sw_version_fields.fbus$v_digital_sw_version_\key"#endif /* #if !defined(__VAXC) */ N/* Format of Bus Array entry hardware_id quadword. When we probe the */P/* Futurebus, we concatenate the vendor_id and the sw_version (which are both */S/* read from the Fbus ROM area) and store the resulting quadword in a bus array */N/* entry. The following structure defines the format of the hardware id */N/* quadword in the bus array entry. */Z#define DEC_FBUS$S_HW_ID_DEF 8 /* Old size name, synonym for DEC_FBUS$S_HW_ID */ typedef struct  _fbus_hw_id { __union {* unsigned __int64 dec_fbus$q_hw_id; __struct {5 unsigned int dec_fbus$l_hw_id_sw_version;4 unsigned int dec_fbus$l_hw_id_vendor_id;& } dec_fbus$r_hw_id_fields;# } dec_fbus$r_hw_id_overlay; } FBUS_HW_ID; #if !defined(__VAXC)B#define dec_fbus$q_hw_id dec_fbus$r_hw_id_overlay.dec_fbus$q_hw_idp#define dec_fbus$l_hw_id_sw_version dec_fbus$r_hw_id_overlay.dec_fbus$r_hw_id_fields.dec_fbus$l_hw_id_sw_v ersionn#define dec_fbus$l_hw_id_vendor_id dec_fbus$r_hw_id_overlay.dec_fbus$r_hw_id_fields.dec_fbus$l_hw_id_vendor_id"#endif /* #if !defined(__VAXC) */ N/* The following key types are defined by IEEE 1212. */#define FBUS_KEY$K_TEX_LEAF 129#define FBUS_KEY$K_TEX_SUBD 193(#define FBUS_KEY$K_BUS_DEP_INFO_LEAF 130(#define FBUS_KEY$K_BUS_DEP_INFO_SUBD 194%#define FBUS_KEY$K_MODULE_VENDOR_ID 3&#define FBUS_KEY$K_MODULE_HW_VERSION 4##define FBUS_KEY$K_MODULE_SPEC_ID 5&#define FBUS_KEY$K_MODULE_SW_VERSION 6+#define FBUS_KEY$K_MODULE_DEP_INFO_LEAF 135+#define FBUS_KEY$K_MODULE_DEP_INFO_SUBD 199##define FBUS_KEY$K_NODE_VENDOR_ID 8$#define FBUS_KEY$K_NODE_HW_VERSION 9"#define FBUS_KEY$K_NODE_SPEC_ID 10%#define FBUS_KEY$K_NODE_SW_VERSION 11'#define FBUS_KEY$K_NODE_CAPABILITIES 12*#define FBUS_KEY$K_NODE_UNIQUE_ID_LEAF 141'#define FBUS_KEY$K_NODE_UNITS_EXTENT 14*#define FBUS_KEY$K_NODE_UNITS_EXTENT_OF 78%#define FBUS_KEY$K_NODE_MEM_EXTENT 15(#defin e FBUS_KEY$K_NODE_MEM_EXTENT_OF 79)#define FBUS_KEY$K_NODE_DEP_INFO_LEAF 144)#define FBUS_KEY$K_NODE_DEP_INFO_SUBD 208#define FBUS_KEY$K_UNIT_SUB 209"#define FBUS_KEY$K_UNIT_SPEC_ID 18%#define FBUS_KEY$K_UNIT_SW_VERSION 19)#define FBUS_KEY$K_UNIT_DEP_INFO_LEAF 148)#define FBUS_KEY$K_UNIT_DEP_INFO_SUBD 212$#define FBUS_KEY$K_UNIT_LOCATION 149%#define FBUS_KEY$K_UNIT_POLL_MASK 149N/* The following constants are useful for bus probing */%#define FBUS$K_NODE0_BASE_ CSR -262144!#define FBUS$K_MAX_NODE_NUMBER 63'#define FBUS$K_DIGITAL_VENDOR_ID 524331N/* Create constants to represent Futurebus commands. These are the */N/* values that will be copied to the command field of the hardware mailbox */N/* for Futurebus register access. */N/* */N/* The following encodings for the Futurebus command field are taken */N/* from the Cobra I/O Module spec. These encodings should be the same */N/* for a Futurebus on any platform. */N/* */N/* 7 6 5 4 3 2 1 0 */N/* +---+---+---+---+---+---+---+---+ */N/* |AW | 0 |DW |WR | transaction | */N/* +---+---+---+---+---+---+---+---+  */N/* */N/* Bit Meaning */N/* --- ------- */N/* AW = 0 32 bit addressing */N/* AW = 1 64 bit addressing */N/* DW = 0 32 bit data width  */N/* DW = 1 64 bit data width */N/* WR = 0 read transaction */N/* WR = 1 write transaction */N/* transaction = 0 unlocked transaction */N/* transaction = 2 partial (masked) transaction */N/* */N/* Bit 31 of the mailbox command field is defined by the Alpha SRM to */N/* mean that the command is a write. This bit is not passed onto the */N/* Futurebus--it is intended as a performance assist for a local side */N/* module. */N/* */N#define FBUS$K_RDQUAD32 32 /* Read, unlocked, AW=32, DW=64 */N#define FBUS$K_RDLONG32 0  /* Read, unlocked, AW=32, DW=32 */N#define FBUS$K_RDWORD32 2 /* Read, partial, AW=32, DW=32 */N#define FBUS$K_RDBYTE32 2 /* Read, partial, AW=32, DW=32 */N#define FBUS$K_WTQUAD32 48 /* write, unlocked, AW=32, DW=64 */N#define FBUS$K_WTLONG32 16 /* write, unlocked, AW=32, DW=32 */N#define FBUS$K_WTWORD32 18 /* write, partial, AW=32, DW=32 */N#define FBUS$K_WTBYTE32 18 /* write, partial, AW=32, DW=32 */N#define FBUS$K_RDQUAD64 160 /* Read, unlocked, AW=64, DW=64 */N#define FBUS$K_RDLONG64 128 /* Read, unlocked, AW=64, DW=32 */N#define FBUS$K_RDWORD64 130 /* Read, partial, AW=64, DW=32 */N#define FBUS$K_RDBYTE64 130 /* Read, partial, AW=64, DW=32 */N#define FBUS$K_WTQUAD64 176 /* Write, unlocked, AW=64, DW=64 */N#define FBUS$K_WTLONG64 144 /* Write, unlocked, AW=64, DW=32 */N#define FBUS$K_WTWORD64 146 /* Write, partial, AW=64, DW=32 */N#define FBUS$K_WTBYTE64 146 /* Write, partial , AW=64, DW=32 */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FBUSDEF_LOADED */ ww.&[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc.  **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:15 by OpenVMS SDL V3.7 */F/* Source: 15-JAN-2022 10:48:28 $1$DGA8345:[LIB_H.SRC]FCBDEF.SDL;1 *//*************************************************** *****************************************************************************//*** MODULE $FCBDEF ***/#ifndef __FCBDEF_LOADED#define __FCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* FCB - FILE CONTROL BLOCK */N/* */N/* THERE IS ONE FILE CONTROL BLOCK FOR EACH UNIQUELY ACCESSED FILE ON A */N/* VOLUME. THE FILE CONTROL BLOCK PROVIDES THE VEHICLE WHEREBY SHARED */N/* ACCESS TO A FILE MAY BE CONTROLLED. */N/* Note LBN and volu me size related fields have been promoted to quadwords. */N/* ODS-II/V will never support volumes larger than 1TB; the promotions are */N/* in anticipation of a new file system that will use the FCB in common. */N/*- */ !#define FCB$M_FILE_ATTRIBUTES 0xF #define FCB$M_FILE_CONTENTS 0xF0"#define FCB$M_FLUSH_ON_CLOSE 0xF00,#define FCB$M_CACHING_OPTIONS_MBZ 0xFFFFF000N#define FCB$C_DEFAULT 0 /* Use default caching policy */N#define FCB$C_WRITETHROUGH 1 /* Use writethrough caching */N#define FCB$C_WRITEBEHIND 2 /* Use writebehind caching */N#define FCB$C_NOCACHING 3 /* Do not cache file */T#define FCB$C_FLUSH 1 /* Flush file from cache when file closed */S#define FCB$C_NOFLUSH 2 /* Retain file in cache when file closed */#define FCB$M_VCC_STATE 0x7N#define FCB$K_LENGTH 392  /* LENGTH OF STANDARD FCB */N#define FCB$C_LENGTH 392 /* LENGTH OF STANDARD FCB */N#define FCB$S_FCBDEF 392 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _orb; struct _wcb; struct _ocb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else #pragma __nomember_alignment#endiftypedef struct _fcb {#pragma __nomember_alignmentN struct _fcb *fcb$l_fcbfl; /* FCB LIST FORWARD LINK */N struct _fcb *fcb$l_fcbbl; /* FCB LIST BACKWARD LINK */N unsigned short int fcb$w_size; /* SIZE OF FCB IN BYTES */N unsigned char fcb$b_type; /* STRUCTURE TYPE OF FCB */N unsigned char fcb$b_acclkmode; /* Access lock mode. */N void *fcb$l_exfcb; /* ADDRESS OF EXTENSION FCB */N struct _fcb *fcb$l_primfcb; /* Pointer to Primary FCB if */N/* this is an extension FCB */N/* else zero */N struct _orb *fcb$l_orb; /* Address of file ORB */N struct _wcb *fcb$l_wlfl; /* WINDOW LISTHEAD FORWARD LINK */N struct _wcb *fcb$l_wlbl; /* WINDOW LISTHEAD BACKWARD LINK */N unsigned int fcb$l_refcnt; /* Total references to this FCB. */N unsigned int fcb$l_acnt; /* FILE ACCESS COUNT */N unsigned int fcb$l_wcnt; /* FILE WRITER COUNT */N unsigned int fcb$l_lcnt; /* FILE LOCK COUNT */N unsigned int fcb$l_tcnt; /* COUNT OF TRUNCATE LOCKS */ __union {N unsigned int fcb$l_status; /* FILE STATUS */ __struct {N unsigned fcb$v_dir : 1; /* FCB IS A DIRECTORY LRU ENTRY */N unsigned fcb$v_markdel : 1; /* FILE IS MARKED FOR DELETE */N unsigned fcb$v_badblk : 1; /* BAD BLOCK ENCOUNTERED IN FILE */N unsigned fcb$v_excl : 1; /* FILE IS EXCLUSIVELY ACCESSED */Q unsigned fcb$v_spool : 1; /* FILE IS AN INTERMEDIATE SPOOL FILE */S unsigned fcb$v_rmslock : 1; /* FILE IS OPEN WITH RMS RECORD LOCKING */V unsigned fcb$v_erase : 1; /* ERASE DATA WHEN BLOCKS REMOVED FROM FILE */N unsigned fcb$v_badacl : 1; /* ACL IS CORRUPT */N unsigned fcb$v_stale : 1; /* Reconstruct FCB from header. */N unsigned fcb$v_delaytrnc : 1; /* Delay truncation. */P unsigned fcb$v_limbo : 1; /* FCB is linked into the LIMBO queue */N unsigned fcb$v_isdir : 1; /* This FCB is a directory FCB */P unsigned fcb$v_nomove : 1; /* This file is NOT to be MOVEFILE'ed */N unsigned fcb$v_shelved : 1; /* This file is shelved */S unsigned fcb$v_noshelvable : 1; /* This file is NOT to be SHELVED'ed */P unsigned fcb$v_preshelved : 1; /* This file has been shelved, but */N/* the data has not been erased from disk */N unsigned fcb$v_fill_1 : 14; /* Unused */N unsigned fcb$v_trunc_eof : 1; /* Truncate file to EOF on close */' unsigned fcb$v_fill_4_ : 1; } fcb$r_status_bits; } fcb$r_status_overlay;N unsigned __int64 fcb$q_opentime; /* Creation time of FCB */N unsigned int fcb$l_reads; /* Total count of read I/Os */N unsigned int fcb$l_writes; /* Total count of write I/Os */N unsigned __int64 fcb$q_readbytes; /* Count of read bytes for I/Os  */N unsigned __int64 fcb$q_writebytes; /* Count of write bytes for I/Os */N unsigned int fcb$l_split_io; /* Total count of split I/Os */V unsigned int fcb$l_assist_io; /* Total count of file system assisted I/Os */ __union {N unsigned short int fcb$w_fid [3]; /* FILE IDENTIFICATION */ __struct {N unsigned short int fcb$w_fid_num; /* FILE NUMBER */N unsigned short int fcb$w_fid_seq; /* FIL E SEQUENCE NUMBER */ __union {O unsigned short int fcb$w_fid_rvn; /* RELATIVE VOLUME NUMBER */ __struct {N unsigned char fcb$b_fid_rvn; /* SHORT FORM RVN */N unsigned char fcb$b_fid_nmx; /* EXTENDED FILE NUMBER */+ } fcb$r_fid_rvn_fields;( } fcb$r_fid_rvn_overlay; } fcb$r_fid_fields;N __struct { /* File ID fields fo r ISO 9660 */W unsigned short int fcb$w_fid_dirnum; /* Directory number of File-Id */N unsigned int fcb$l_fid_recnum; /* Record number of File-ID */( } fcb$r_fid_iso_9660_fields; } fcb$r_fid_overlay;N unsigned short int fcb$w_segn; /* FILE SEGMENT NUMBER */N __union { /* STARTING VIRTUAL BLOCK NUMBER */! unsigned int fcb$l_stvbn;% unsigned __int64 fcb$q_stvbn; } fcb$r_stvbn_overlay;N __union { /* STARTING LOGICAL BLOCK NUMBER */! unsigned int fcb$l_stlbn;% unsigned __int64 fcb$q_stlbn; } fcb$r_stlbn_overlay;N __union { /* LBN OF FILE HEADER */! unsigned int fcb$l_hdlbn;% unsigned __int64 fcb$q_hdlbn; } fcb$r_hdlbn_overlay;N __union { /* FILE SIZE IN BLOCKS */$ unsigned int fcb$l _filesize;( unsigned __int64 fcb$q_filesize;! } fcb$r_filesize_overlay;N __union { /* END OF FILE VBN */! unsigned int fcb$l_efblk;% unsigned __int64 fcb$q_efblk; } fcb$r_efblk_overlay;V unsigned int fcb$l_versions; /* MAXIMUM NUMBER OF VERSIONS IN DIRECTORY */N unsigned int fcb$l_dirseq; /* DIRECTORY USE SEQUENCE NUMBER */N unsigned int fcb$l_dirindx; /* Directory index pointer */N unsigned int fcb$l_acclkid; /* Access lock ID. */N unsigned int fcb$l_lockbasis; /* Lock basis for this FCB. */N __union { /* (mutually exclusive usage) */V unsigned int fcb$l_truncvbn; /* VBN for delayed truncation. (Files-11 B) */X unsigned int fcb$l_numextents; /* Number of extents recorded (Files-11 C/D) */ } fcb$r_fcb1_overlay;N unsigned int fcb$l_cachelkid;  /* Cache interlock lock ID */V unsigned int fcb$l_dirlckid; /* Support for directory cache invalidation */N __union { /* HIGH WATER MARK IN FILE */% unsigned int fcb$l_highwater;) unsigned __int64 fcb$q_highwater;" } fcb$r_highwater_overlay;N __union { /* Highwater mark of pending writes */( unsigned int fcb$l_newhighwater;, unsigned __int64 fcb$q_newhighwater;%  } fcb$r_newhighwater_overlay;Q unsigned int fcb$l_hwm_update; /* Count of writes past highwater mark */Z unsigned int fcb$l_hwm_erase; /* Count of writes starting past highwater mark */[ unsigned int fcb$l_hwm_partial; /* Count of partially validated erase operations */N unsigned int fcb$l_revision; /* File revision */ __union {N __struct { /* High water mark queue header */N void *fcb$l_hw m_waitfl; /* Highwater mark update queue */N void *fcb$l_hwm_waitbl; /* Highwater mark update queue */ } fcb$q_hwmqhd;N __struct { /* LIMBO queue header */N void *fcb$l_limbofl; /* Highwater mark update queue */N void *fcb$l_limbobl; /* Highwater mark update queue */ } fcb$q_limboqhd; } fcb$r_queue_overlay;N/*  */N/* NOTA BENE: */N/* */R/* The following is an embedded ORB. This structure should only be referenced */R/* through the FCB$L_ORB pointer (using ORB$ field names). The existing (FCB) */N/* fields are left for source code and binary compatibility in privileged */N/* software that thinks it knows what an FCB and its ORB look like. */N/* */O/* Third-party developers would be well advised to remove all references to */N/* these FCB symbols as soon as possible. You have been warned! */N/* */N __struct { /* Object's Rights Block */ __union {N unsigned int fcb$l_fileowner; /* FILE OWNER UIC  */ __struct {N unsigned short int fcb$w_uicmember; /* MEMBER NUMBER */N unsigned short int fcb$w_uicgroup; /* GROUP NUMBER */ } fcb$r_fill_1_; } fcb$r_fill_0_;N unsigned int fcb$l_fill_5; /* ACL mutex */N unsigned int fcb$l_fill_3; /* Structure size & type */N unsigned int fcb$l_fill_6; /* Spare + ref count */N unsigned __int64 fcb$q_acmode; /* Access mode protection vector */ __union {N unsigned int fcb$l_sys_prot; /* Protection word/vector */ __struct {N unsigned short int fcb$w_fileprot; /* FILE PROTECTION MASK */0 unsigned short int fcb$w_fill_4; } fcb$r_fill_3_; } fcb$r_fill_2_;N unsigned int fcb$l_own_prot; /* Owner protection */N unsigned int fcb$l_grp_prot; /* Group protection */N unsigned int fcb$l_wor_prot; /* World protection */O void *fcb$l_aclfl; /* ACCESS CONTROL LIST FORWARD LINK */P void *fcb$l_aclbl; /* ACCESS CONTROL LIST BACKWARD LINK */R __struct { /* Minimum security classification mask */N char fcb$b_fill_1 [20]; /* see structure $CLSDEF */# } fcb$r_min_class_prot;R  __struct { /* Maximum security classification mask */N char fcb$b_fill_2 [20]; /* see structure $CLSDEF */# } fcb$r_max_class_prot;- unsigned short int fcb$w_name_length; short int fcb$w_fill_7;! void *fcb$l_name_pointer; struct _ocb *fcb$l_ocb;( struct _orb *fcb$l_template_orb;+ unsigned int fcb$l_object_specific;( struct _orb *fcb$l_original_orb;" unsigned int fcb $l_updseq;N void *fcb$l_mutex_address; /* Address of mutex for CHKPRO */$ unsigned int fcb$l_reserve1; } fcb$r_orb;N unsigned int fcb$l_reserve2; /* Pad to quadword */N __int64 fcb$q_orb_reserved; /* Reserved for ORB expansion */N/* */N/* End of embedded ORB */N/*  */N/* */N/* Define fields and constant values for FCB$L_CACHING_OPTIONS */N/* longword. These must match [STARLET]FIBDEF.SDL exactly. */N/* */ __union {+ unsigned int fcb$l_caching_options; __struct {S unsigned fcb$v_file_attributes : 4; /* File attributes caching field */O unsigned fcb$v_file_contents : 4; /* File contents caching field */N unsigned fcb$v_flush_on_close : 4; /* Flush file on close field */N unsigned fcb$v_caching_options_mbz : 20; /* Must be zero */) } fcb$r_caching_options_bits;( } fcb$r_caching_options_overlay; __union {N unsigned int fcb$l_status2; /* Additional file status */ __struct {Y unsigned fcb$v_vcc _state : 3; /* Replicated caching attribute (see FH2DEF) */' unsigned fcb$v_fill_5_ : 5;! } fcb$r_status2_bits; } fcb$r_status2_overlay; unsigned __int64 fcb$q_cfb;N void *fcb$l_cfcb; /* VBN Cache pointer */N int fcb$l_fill_8; /* Pad to quadword */N unsigned __int64 fcb$q_accdate; /* access date */N unsigned __int64 fcb$q_moddate; /* modification da te */ } FCB; #if !defined(__VAXC)6#define fcb$l_status fcb$r_status_overlay.fcb$l_statusB#define fcb$v_dir fcb$r_status_overlay.fcb$r_status_bits.fcb$v_dirJ#define fcb$v_markdel fcb$r_status_overlay.fcb$r_status_bits.fcb$v_markdelH#define fcb$v_badblk fcb$r_status_overlay.fcb$r_status_bits.fcb$v_badblkD#define fcb$v_excl fcb$r_status_overlay.fcb$r_status_bits.fcb$v_exclF#define fcb$v_spool fcb$r_status_overlay.fcb$r_status_bits.fcb$v_spoolJ#define fcb$v_rmslock fcb$r_status_overlay.fcb$r_status_bits.fcb$v_rmslockF#define fcb$v_erase fcb$r_status_overlay.fcb$r_status_bits.fcb$v_eraseH#define fcb$v_badacl fcb$r_status_overlay.fcb$r_status_bits.fcb$v_badaclF#define fcb$v_stale fcb$r_status_overlay.fcb$r_status_bits.fcb$v_staleN#define fcb$v_delaytrnc fcb$r_status_overlay.fcb$r_status_bits.fcb$v_delaytrncF#define fcb$v_limbo fcb$r_status_overlay.fcb$r_status_bits.fcb$v_limboF#define fcb$v_isdir fcb$r_status_overlay.fcb$r_status_bits.fcb$v_isdirH#define fcb$v_nomove fcb$r_status_overlay.fcb$r_status_bits.fcb$v_nomoveJ#define fcb$v_shelved fcb$r_status_overlay.fcb$r_status_bits.fcb$v_shelvedR#define fcb$v_noshelvable fcb$r_status_overlay.fcb$r_status_bits.fcb$v_noshelvableP#define fcb$v_preshelved fcb$r_status_overlay.fcb$r_status_bits.fcb$v_preshelvedN#define fcb$v_trunc_eof fcb$r_status_overlay.fcb$r_status_bits.fcb$v_trunc_eof-#define fcb$w_fid fcb$r_fid_overlay.fcb$w_fidF#define fcb$w_fid_num fcb$r_fid_overlay.fcb$r_fid_fields.fcb$w_fid_numF#define fcb$w_fid_seq fcb$r_fid_overlay.fcb$r_fid_fields.fcb$w_fid_seq\#define fcb$w_fid_rvn fcb$r_fid_overlay.fcb$r_fid_fields.fcb$r_fid_rvn_overlay.fcb$w_fid_rvnq#define fcb$b_fid_rvn fcb$r_fid_overlay.fcb$r_fid_fields.fcb$r_fid_rvn_overlay.fcb$r_fid_rvn_fields.fcb$b_fid_rvnq#define fcb$b_fid_nmx fcb$r_fid_overlay.fcb$r_fid_fields.fcb$r_fid_rvn_overlay.fcb$r_fid_rvn_fields.fcb$b_fid_nmxU#define fcb$w_fid_dirnum fcb$r_fid_overlay.fcb$r_fid_iso_9660_fields.fcb$w_fid_dirnumU#define fcb$l_fid_recnum fcb $r_fid_overlay.fcb$r_fid_iso_9660_fields.fcb$l_fid_recnum3#define fcb$l_stvbn fcb$r_stvbn_overlay.fcb$l_stvbn3#define fcb$q_stvbn fcb$r_stvbn_overlay.fcb$q_stvbn3#define fcb$l_stlbn fcb$r_stlbn_overlay.fcb$l_stlbn3#define fcb$q_stlbn fcb$r_stlbn_overlay.fcb$q_stlbn3#define fcb$l_hdlbn fcb$r_hdlbn_overlay.fcb$l_hdlbn3#define fcb$q_hdlbn fcb$r_hdlbn_overlay.fcb$q_hdlbn<#define fcb$l_filesize fcb$r_filesize_overlay.fcb$l_filesize<#define fcb$q_filesize fcb$r_filesize_overlay.fcb$q_filesize3#define fcb$l_efblk fcb$r_efblk_overlay.fcb$l_efblk3#define fcb$q_efblk fcb$r_efblk_overlay.fcb$q_efblk8#define fcb$l_truncvbn fcb$r_fcb1_overlay.fcb$l_truncvbn<#define fcb$l_numextents fcb$r_fcb1_overlay.fcb$l_numextents?#define fcb$l_highwater fcb$r_highwater_overlay.fcb$l_highwater?#define fcb$q_highwater fcb$r_highwater_overlay.fcb$q_highwaterH#define fcb$l_newhighwater fcb$r_newhighwater_overlay.fcb$l_newhighwaterH#define fcb$q_newhighwater fcb$r_newhighwater_overlay.fcb$q_newhighwat er5#define fcb$q_hwmqhd fcb$r_queue_overlay.fcb$q_hwmqhd6#define fcb$l_hwm_waitfl fcb$q_hwmqhd.fcb$l_hwm_waitfl6#define fcb$l_hwm_waitbl fcb$q_hwmqhd.fcb$l_hwm_waitbl9#define fcb$q_limboqhd fcb$r_queue_overlay.fcb$q_limboqhd2#define fcb$l_limbofl fcb$q_limboqhd.fcb$l_limbofl2#define fcb$l_limbobl fcb$q_limboqhd.fcb$l_limbobl?#define fcb$l_fileowner fcb$r_orb.fcb$r_fill_0_.fcb$l_fileownerM#define fcb$w_uicmember fcb$r_orb.fcb$r_fill_0_.fcb$r_fill_1_.fcb$w_uicmemberK#define fcb$w_uicgroup f cb$r_orb.fcb$r_fill_0_.fcb$r_fill_1_.fcb$w_uicgroup+#define fcb$q_acmode fcb$r_orb.fcb$q_acmode=#define fcb$l_sys_prot fcb$r_orb.fcb$r_fill_2_.fcb$l_sys_protK#define fcb$w_fileprot fcb$r_orb.fcb$r_fill_2_.fcb$r_fill_3_.fcb$w_fileprot/#define fcb$l_own_prot fcb$r_orb.fcb$l_own_prot/#define fcb$l_grp_prot fcb$r_orb.fcb$l_grp_prot/#define fcb$l_wor_prot fcb$r_orb.fcb$l_wor_prot)#define fcb$l_aclfl fcb$r_orb.fcb$l_aclfl)#define fcb$l_aclbl fcb$r_orb.fcb$l_aclbl;#define fcb$r_min_class_prot fcb$r_orb.fcb$r_min_class_prot;#define fcb$r_max_class_prot fcb$r_orb.fcb$r_max_class_protQ#define fcb$l_caching_options fcb$r_caching_options_overlay.fcb$l_caching_optionsl#define fcb$v_file_attributes fcb$r_caching_options_overlay.fcb$r_caching_options_bits.fcb$v_file_attributesh#define fcb$v_file_contents fcb$r_caching_options_overlay.fcb$r_caching_options_bits.fcb$v_file_contentsj#define fcb$v_flush_on_close fcb$r_caching_options_overlay.fcb$r_caching_options_bits.fcb$v_flush_on_closet #define fcb$v_caching_options_mbz fcb$r_caching_options_overlay.fcb$r_caching_options_bits.fcb$v_caching_options_mbz9#define fcb$l_status2 fcb$r_status2_overlay.fcb$l_status2P#define fcb$v_vcc_state fcb$r_status2_overlay.fcb$r_status2_bits.fcb$v_vcc_state"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FCBDEF_LOADED */ ww|&[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by Open VMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FCHDEF ***/#ifndef __FCHDEF_LOADED#define __FCHDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* File characteristics bit definitions. These are identical to, and must */N/* track, the bits in FILECHAR above, but are defined relative to the file */N/* characteristics longword instead of relative to the file header. */N/* */N/*- */ #define FCH$M_VCC_STATE 0x700!#define FCH$M_ASSOCIATED 0x100000 #define FCH$M_EXISTENCE 0x200000#define FCH$M_WASCONTIG 0x1#define FCH$M_NOBACKUP 0x2#define FCH$M_WRITEBACK 0x4#define FCH$M_READCHECK 0x8#define FCH$M_WRITCHECK 0x10#define FCH$M_CONTIGB 0x20#define FCH$M_LOCKED 0x40#define FCH$M_CONTIG 0x80#define FCH$M_BADACL 0x800#define FCH$M_SPOOL 0x1000#define FCH$M_DIRECTORY 0x2000#define FCH$M_BADBLOCK 0x4000#define FCH$M_MARKDEL 0x8000#define FCH$M_NOCHARGE 0x10000#define FCH$M_ERASE 0x20000#define FCH$M_SHELVED 0x80000#define FCH$M_SCRATCH 0x100000#define FCH$M_NOMOVE 0x200000"#define FCH$M_NOSHELVABLE 0x400000!#define FCH$M_PRESHELVED 0x800000N#define FCH$S_FCHDEF 4 /* Old size name - synonym */ ty pedef struct _fch { __union { int fch$$_fill_1; __struct {N unsigned fch$$_fill_31 : 8; /* reserved */N unsigned fch$v_vcc_state : 3; /* VCC state bits */N unsigned fch$$_fill_32 : 7; /* reserved */N/***********The following line is different from FH2 */N unsigned fch$$_alm_state : 2; /* ALM state bits removed */N unsign ed fch$v_associated : 1; /* ISO 9660 Associated file */N unsigned fch$v_existence : 1; /* ISO 9660 Existence file */' unsigned fch$v_fill_6_ : 2;" } fch$r_fill_1_chunks; __struct {S unsigned fch$v_wascontig : 1; /* file was (and should be) contiguous */N unsigned fch$v_nobackup : 1; /* file is not to be backed up */N unsigned fch$v_writeback : 1; /* file may be write-back cached */N unsigned fch$v_readcheck : 1; /* verify all read operations */N unsigned fch$v_writcheck : 1; /* verify all write operations */R unsigned fch$v_contigb : 1; /* keep file as contiguous as possible */N unsigned fch$v_locked : 1; /* file is deaccess locked */N unsigned fch$v_contig : 1; /* file is contiguous */N unsigned fch$$_fill_3 : 3; /* reserved */N unsigned fch$v_badacl : 1; /* ACL is invalid */N unsigned fch$v_spool : 1; /* intermediate spool file */N unsigned fch$v_directory : 1; /* file is a directory */N unsigned fch$v_badblock : 1; /* file contains bad blocks */N unsigned fch$v_markdel : 1; /* file is marked for delete */O unsigned fch$v_nocharge : 1; /* file space is not to be charged */R unsigned fch$v_erase : 1; /* erase file contents before deletion */N/***********The following line is different from FH2 */N unsigned fch$$_fill_4 : 1; /* Place holder for ALM bit in FH2 */N unsigned fch$v_shelved : 1; /* File shelved */N unsigned fch$v_scratch : 1; /* Scratch Header used by movefile */N unsigned fch$v_nomove : 1; /* Disable movefile on this file */S unsigned fch$v_noshelvable : 1; /* File is not allowed to be shelved */U  unsigned fch$v_preshelved : 1; /* File is shelved but also kept online */N/* Note: The high 8 bits of this longword */N/* are reserved for user and CSS use. */ } fch$r_fill_1_bits; } fch$r_fch_union; } FCH; #if !defined(__VAXC)K#define fch$v_vcc_state fch$r_fch_union.fch$r_fill_1_chunks.fch$v_vcc_stateM#define fch$v_associated fch$r_fch_union.fch$r_fill_1_chunks.fch$v_associatedK#define fch$v_existence fch$r_fch_union.fch$r_fill_1_chunks.fch$v_existenceI#define fch$v_wascontig fch$r_fch_union.fch$r_fill_1_bits.fch$v_wascontigG#define fch$v_nobackup fch$r_fch_union.fch$r_fill_1_bits.fch$v_nobackupI#define fch$v_writeback fch$r_fch_union.fch$r_fill_1_bits.fch$v_writebackI#define fch$v_readcheck fch$r_fch_union.fch$r_fill_1_bits.fch$v_readcheckI#define fch$v_writcheck fch$r_fch_union.fch$r_fill_1_bits.fch$v_writcheckE#define fch$v_contigb fch$r_fch_union.fch$r_fill_1_bits.fch$v_contigbC#define fch$v_locked fch$r_fch_union.fch$r_fill_1_bits.fch$v_lockedC#define fch$v_contig fch$r_fch_union.fch$r_fill_1_bits.fch$v_contigC#define fch$v_badacl fch$r_fch_union.fch$r_fill_1_bits.fch$v_badaclA#define fch$v_spool fch$r_fch_union.fch$r_fill_1_bits.fch$v_spoolI#define fch$v_directory fch$r_fch_union.fch$r_fill_1_bits.fch$v_directoryG#define fch$v_badblock fch$r_fch_union.fch$r_fill_1_bits.fch$v_badblockE#define fch$v_markdel fch$r_fch_union.fch$r_fill_1_bits.fch$v_markdelG#define fch$v_nocharge fch$r_fch_union.fch$r_fill_1_bits.fch$v_nochargeA#define fch$v_erase fch$r_fch_union.fch$r_fill_1_bits.fch$v_eraseE#define fch$v_shelved fch$r_fch_union.fch$r_fill_1_bits.fch$v_shelvedE#define fch$v_scratch fch$r_fch_union.fch$r_fill_1_bits.fch$v_scratchC#define fch$v_nomove fch$r_fch_union.fch$r_fill_1_bits.fch$v_nomoveM#define fch$v_noshelvable fch$r_fch_union.fch$r_fill_1_bits.fch$v_noshelvableK#define fch$v_preshelved fch$r_fch_union.fch$r_fill_1_bits.fch$v_preshelved"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FCHDEF_LOADED */ ww&[UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:17 by OpenVMS SDL V3.7 */F/* Source: 24-MAR-2004 10:54:46 $1$DGA8345:[LIB_H.SRC]FCPDEF.SDL;1 *//********************************************************************************************************************************/"/***  MODULE $FCPDEF IDENT X-1 ***/#ifndef __FCPDEF_LOADED#define __FCPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #ifndef _FCPDEF_LOADED#define _FCPDEF_LOADED !#define FCP_CNTL $M_WRITE_DATA 0x1 #define FCP_CNTL$M_READ_DATA 0x2 #define FCP_CNTL$M_RESERVED1 0x1%#define FCP_CNTL$M_ABORT_TASK_SET 0x2%#define FCP_CNTL$M_CLEAR_TASK_SET 0x4!#define FCP_CNTL$M_RESERVED2 0x18$#define FCP_CNTL$M_TARGET_RESET 0x20!#define FCP_CNTL$M_CLEAR_ACA 0x40&#define FCP_CNTL$M_TERMINATE_TASK 0x80%#define FCP_CNTL$M_TASK_ATTRIBUTE 0x7N#define FCP_CNTL$K_SIMPLE 0 /* Simple tag */N#define FCP_CNTL$K_HEAD 1 /* Head of Queue tag  */N#define FCP_CNTL$K_ORDERED 2 /* Ordered Queue tag */N#define FCP_CNTL$K_ACA 4 /* ACA tag */N#define FCP_CNTL$K_UNTAGGED 5 /* Untagged */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _fcp_cntl_t {#pragma __nomember_alignment  __union {% int fcp_cntl$l_fcp_cntl_bits; __struct {N __union { /* Execution management codes */6 unsigned char fcp_cntl$b_exe_mgt_code; __union {6 char fcp_cntl$b_exe_mgt_code_bits; __struct {V unsigned fcp_cntl$v_write_data : 1; /* SCSI write operation */T unsigned fcp_cntl$v_read_data : 1; /* SCSI read operation */8  unsigned fcp_cntl$v_fill_8_ : 6;- } fcp_cntl$r_fill_3_;) } fcp_cntl$r_fill_2_;2 } fcp_cntl$r_exe_mgt_code_overlay;N __union { /* Task management flags */8 unsigned char fcp_cntl$b_task_mgt_flags; __union {8 char fcp_cntl$b_task_mgt_flags_bits; __struct {N unsigned fcp_cntl$v_reserved1 : 1; /* Reserved */\ unsigned fcp_cntl$v_abort_task_set : 1; /* ABORT TASK SET request */\ unsigned fcp_cntl$v_clear_task_set : 1; /* CLEAR TASK SET request */N unsigned fcp_cntl$v_reserved2 : 2; /* Reserved */X unsigned fcp_cntl$v_target_reset : 1; /* TARGET RESET request */R unsigned fcp_cntl$v_clear_aca : 1; /* CLEAR ACA request */\ unsign ed fcp_cntl$v_terminate_task : 1; /* TERMINATE TASK request */- } fcp_cntl$r_fill_5_;) } fcp_cntl$r_fill_4_;4 } fcp_cntl$r_task_mgt_flags_overlay;N/* Task codes */ __union {3 unsigned char fcp_cntl$b_task_code; __union {3 char fcp_cntl$b_task_code_bits; __struct {\  unsigned fcp_cntl$v_task_attribute : 3; /* Task attribute values: */8 unsigned fcp_cntl$v_fill_9_ : 5;- } fcp_cntl$r_fill_7_;) } fcp_cntl$r_fill_6_;/ } fcp_cntl$r_task_code_overlay;N unsigned char fcp_cntl$b_reserved4; /* Reserved */! } fcp_cntl$r_fill_1_; } fcp_cntl$r_fill_0_; } FCP_CNTL_T; #if !defined(__VAXC)L#define fcp_cntl$l_fcp_cntl_bits fcp_cntl$r_fill_0_.fcp_cntl$l_fcp_cntl_bitsm#define fcp_cntl$r_exe_mgt_code_overlay fcp_cntl$r_fill_0_.fcp_cntl$r_fill_1_.fcp_cntl$r_exe_mgt_code_overlayW#define fcp_cntl$b_exe_mgt_code fcp_cntl$r_exe_mgt_code_overlay.fcp_cntl$b_exe_mgt_codet#define fcp_cntl$b_exe_mgt_code_bits fcp_cntl$r_exe_mgt_code_overlay.fcp_cntl$r_fill_2_.fcp_cntl$b_exe_mgt_code_bitsy#define fcp_cntl$v_write_data fcp_cntl$r_exe_mgt_code_overlay.fcp_cntl$r_fill_2_.fcp_cntl$r_fill_3_.fcp_cntl$v_write_dataw#define fcp_cntl$v_read_data fcp_cntl$r_exe_mgt_code_overlay.fcp_cntl$r_fill_2_.fcp_cntl$r_fill_3_.fcp_cntl$v_read_dataq#define fcp_cntl$r_task_mgt_flags_overlay fcp_cntl$r_fill_0_.fcp_cntl$r_fill_1_.fcp_cntl$r_task_mgt_flags_overlay]#define fcp_cntl$b_task_mgt_flags fcp_cntl$r_task_mgt_flags_overlay.fcp_cntl$b_task_mgt_flagsz#define fcp_cntl$b_task_mgt_flags_bits fcp_cntl$r_task_mgt_flags_overlay.fcp_cntl$r_fill_4_.fcp_cntl$b_task_mgt_flags_bitsy#define fcp_cntl$v_reserved1 fcp_cntl$r_task_mgt_flags_overlay.fcp_cntl$r_fill_4_.fcp_cntl$r_fill_5_.fcp_cntl$v_reserved1#define fcp_cntl$v_abort_task_set fcp_cntl$r_task_mgt_flags_overlay.fcp_cntl$r_fill_4_.fcp_cntl$r_fill_5_.fcp_cntl$v_abort_task_set#define fcp_cntl$v_clear_task_set fcp_cntl$r_task_mgt_flags_overlay.fcp_cntl$r_fill_4_.fcp_cntl$r_fill_5_.fcp_cntl$v_clear_task_sety#define fcp_cntl$v_reserved2 fcp_cntl$r_task_mgt_flags_overlay.fcp_cntl$r_fill_4_.fcp_cntl$r_fill_5_.fcp_cntl$v_reserved2#define fcp_cntl$v_target_reset fcp_cntl$r_task_mgt_flags_overlay.fcp_cntl$r_fill_4_.fcp_cntl$r_fill_5_.fcp_cntl$v_target_resety#define fcp_cntl$v_clear_aca fcp_cntl$r_task_mgt_flags_overlay.fcp_cntl$r_fill_4_.fcp_cntl$r_fill_5_.fcp_cntl$v_clear_aca#define fcp_cntl$v_terminate_task fcp_cntl$r_task_mgt_flags_overlay.fcp_cntl$r_fill_4_.fcp_cntl$r_fill_5_.fcp_cntl$v_terminate_taskg#define fcp_cntl$r_task_code_overlay fcp_cntl$r_fill_0_.fcp_cntl$r_fill_1_.fcp_cntl$r_task_code_overlayN#define fcp_cntl$b_task_code fcp_cntl$r_task_code_overlay.fcp_cntl$b_task_ codek#define fcp_cntl$b_task_code_bits fcp_cntl$r_task_code_overlay.fcp_cntl$r_fill_6_.fcp_cntl$b_task_code_bits~#define fcp_cntl$v_task_attribute fcp_cntl$r_task_code_overlay.fcp_cntl$r_fill_6_.fcp_cntl$r_fill_7_.fcp_cntl$v_task_attributeW#define fcp_cntl$b_reserved4 fcp_cntl$r_fill_0_.fcp_cntl$r_fill_1_.fcp_cntl$b_reserved4"#endif /* #if !defined(__VAXC) */ N/* X-4 Define CDB length consistently */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fcp_cmnd {#pragma __nomember_alignment( unsigned __int64 fcp_cmnd$q_fcp_lun;# FCP_CNTL_T fcp_cmnd$r_fcp_cntl;* unsigned char fcp_cmnd$b_fcp_cdb [16];# unsigned int fcp_cmnd$l_fcp_dl;N/* X-4 Define an SDA-accessible symbol for the size of this structure */ } FCP_CMND;*#define FCP_STATUS$M_FCP_RSP_LEN_VALID 0x1*#define FCP_STATUS$M_FCP_SNS_LEN_VALID 0x2'#define FCP_STATUS$M_FCP_RESID_OVER 0x4(#define FCP_STATUS$M_FCP_RESID_UNDER 0x8##define FCP_STATUS$M_RESERVED1 0xF0 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _fcp_status_t {#pragma __nomember_alignmentN unsigned char fcp_status$b_scsi_status; /* SCSI status byte */ __ union {0 unsigned char fcp_status$b_status_flags; __union {0 char fcp_status$b_status_flags_bits; __struct {W unsigned fcp_status$v_fcp_rsp_len_valid : 1; /* FCP_RSP_LEN is valid */W unsigned fcp_status$v_fcp_sns_len_valid : 1; /* FCP_SNS_LEN is valid */Q unsigned fcp_status$v_fcp_resid_over : 1; /* Overflow occurred */S unsigned fcp_status$v_fcp_resid_under : 1; /* Underflow occurred */4  unsigned fcp_status$v_reserved1 : 4;( } fcp_status$r_fill_11_;$ } fcp_status$r_fill_10_;, } fcp_status$r_status_flags_overlay;N unsigned char fcp_status$b_reserved2; /* Reserved */N unsigned char fcp_status$b_reserved3; /* Reserved */ } FCP_STATUS_T; #if !defined(__VAXC)]#define fcp_status$b_status_flags fcp_status$r_status_flags_overlay.fcp_status$b_status_flags}#define fcp_status$b_status_flags_bits fcp_status$r_status_flags_overlay.fcp_status$r_fill_10_.fcp_status$b_status_flags_bits#define fcp_status$v_fcp_rsp_len_valid fcp_status$r_status_flags_overlay.fcp_status$r_fill_10_.fcp_status$r_fill_11_.fcp_status$v_f\cp_rsp_len_valid#define fcp_status$v_fcp_sns_len_valid fcp_status$r_status_flags_overlay.fcp_status$r_fill_10_.fcp_status$r_fill_11_.fcp_status$v_f\cp_sns_len_valid#define fcp_status$v_fcp_resid_over fcp_status$r_status_flags_overlay.fcp_status$r_fill_10_.fcp_ status$r_fill_11_.fcp_status$v_fcp_\ resid_over#define fcp_status$v_fcp_resid_under fcp_status$r_status_flags_overlay.fcp_status$r_fill_10_.fcp_status$r_fill_11_.fcp_status$v_fcp\ _resid_under#define fcp_status$v_reserved1 fcp_status$r_status_flags_overlay.fcp_status$r_fill_10_.fcp_status$r_fill_11_.fcp_status$v_reserved1"#endif /* #if !defined(__VAXC) */ N#define FCP_RSP_INFO$K_SUCCESS 0 /* Function complete */N#define FCP_RSP_INFO$K_DATA_LEN_MISMATCH 1 /* FCP_DATA  <> BURST_LEN */N#define FCP_RSP_INFO$K_INVALID_CMD 2 /* FCP_CMND fields invalid */S#define FCP_RSP_INFO$K_DATA_RO_MISMATCH 3 /* FCP_DATA RO <> FCP_XFER_RDY DATA_RO */N#define FCP_RSP_INFO$K_UNSUPPORTED_FUNC 4 /* Tsk mgt function not supported */I#define FCP_RSP_INFO$K_FUNC_FAILED 5 /* Tsk mgt function failed */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#p ragma __nomember_alignment#endif typedef struct _fcp_rsp_info_t {#pragma __nomember_alignment/ unsigned char fcp_rsp_info$b_reserved1 [4];N unsigned char fcp_rsp_info$b_rsp_code; /* Response codes (p. 34) */N unsigned char fcp_rsp_info$b_reserved2 [3]; /* Reserved */ } FCP_RSP_INFO_T; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomemb er_alignment#endiftypedef struct _fcp_rsp {#pragma __nomember_alignmentN unsigned char fcp_rsp$b_reserved1 [8]; /* Reserved */N FCP_STATUS_T fcp_rsp$r_fcp_status; /* FCP status */N unsigned int fcp_rsp$l_fcp_resid; /* Residual count */N unsigned int fcp_rsp$l_fcp_sns_len; /* No. of valid FCP_SNS_INFO bytes */N unsigned int fcp_rsp$l_fcp_rsp_len; /* No. of valid FCP_RSP_INFO btyes */O FCP_RSP_INFO_T fcp_rsp $r_scsi_rsp_info; /* Info on FCP protocol failures */b/* X-4 Define an SDA-accessible symbol for the size of this structure up to the SCSI Sense Info */_ unsigned char fcp_rsp$b_scsi_sns_info [256]; /* Sense data (following a Check Condition) */ } FCP_RSP;0#define FCP_LPP$M_RSPNDR_PROC_ASSOC_VALID 0x4000.#define FCP_LPP$M_ORIG_PROC_ASSOC_VALID 0x8000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif%typedef struct _logout_param_page_t {N/* Longword 0 */#pragma __nomember_alignment __union { int fcp_lpp$l_lpp_flags; __struct {- unsigned fcp_lpp$v_reserved1 : 8;, unsigned fcp_lpp$v_rsp_code : 4;- unsigned fcp_lpp$v_reserved2 : 2;; unsigned fcp_lpp$v_rspndr_proc_assoc_valid : 1;9 unsigned fcp _lpp$v_orig_proc_assoc_valid : 1;. unsigned fcp_lpp$v_reserved3 : 16;! } fcp_lpp$r_fill_13_; } fcp_lpp$r_fill_12_;N/* Longword 1 */" int fcp_lpp$l_orig_proc_assoc;N/* Longword 2 */$ int fcp_lpp$l_rspndr_proc_assoc;N/* Longword 3 */ int fcp_lpp$l_reserved4; } LOGO UT_PARAM_PAGE_T; #if !defined(__VAXC)B#define fcp_lpp$l_lpp_flags fcp_lpp$r_fill_12_.fcp_lpp$l_lpp_flagsU#define fcp_lpp$v_reserved1 fcp_lpp$r_fill_12_.fcp_lpp$r_fill_13_.fcp_lpp$v_reserved1S#define fcp_lpp$v_rsp_code fcp_lpp$r_fill_12_.fcp_lpp$r_fill_13_.fcp_lpp$v_rsp_codeU#define fcp_lpp$v_reserved2 fcp_lpp$r_fill_12_.fcp_lpp$r_fill_13_.fcp_lpp$v_reserved2q#define fcp_lpp$v_rspndr_proc_assoc_valid fcp_lpp$r_fill_12_.fcp_lpp$r_fill_13_.fcp_lpp$v_rspndr_proc_assoc_validm#define fcp_lpp$ v_orig_proc_assoc_valid fcp_lpp$r_fill_12_.fcp_lpp$r_fill_13_.fcp_lpp$v_orig_proc_assoc_validU#define fcp_lpp$v_reserved3 fcp_lpp$r_fill_12_.fcp_lpp$r_fill_13_.fcp_lpp$v_reserved3"#endif /* #if !defined(__VAXC) */ #define FCP_SPP$M_RESERVED1 0xFF$#define FCP_SPP$M_ACC_RSP_CODE 0xF00N#define FCP_SPP$K_SUCCESS 1 /* Request executed */[#define FCP_SPP$K_INSUFF_RESOURCES 2 /* Target has no resources to establish img pair */X#define FCP_SPP$K_INIT_INCOMPLETE 3  /* Initialization incomplete for target image */W#define FCP_SPP$K_NONEXISTENT_TARGET 4 /* The specified target image does not exist */d#define FCP_SPP$K_CONFIG_RESTRICTION 5 /* Target image's predefined config precluded this img pr */]#define FCP_SPP$K_CONDITIONAL_SUCCESS 6 /* Some requested service parameters were not set */c#define FCP_SPP$K_MULTIPAGE_DISALLOWED 7 /* Destination N_Port cannot process multipage requests */"#define FCP_SPP$M_RESERVED2 0x1000/#define FCP_SPP$M_ESTABLIS HED_IMAGE_PAIR 0x20000#define FCP_SPP$M_RSPNDR_PROC_ASSOC_VALID 0x4000.#define FCP_SPP$M_ORIG_PROC_ASSOC_VALID 0x8000-#define FCP_SPP$M_WRITE_XFER_RDY_DISABLED 0x1,#define FCP_SPP$M_READ_XFER_RDY_DISABLED 0x2*#define FCP_SPP$M_DATA_RSP_MIX_ALLOWED 0x4*#define FCP_SPP$M_CMD_DATA_MIX_ALLOWED 0x8&#define FCP_SPP$M_TARGET_FUNCTION 0x10)#define FCP_SPP$M_INITIATOR_FUNCTION 0x20+#define FCP_SPP$M_DATA_OVERLAY_ALLOWED 0x40&#define FCP_SPP$M_RESERVED3 0xFFFFFF80 c#if !defined(__NOBASEALIGN_S UPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif&typedef struct _service_param_page_t {#pragma __nomember_alignment __union {+ int fcp_spp$l_spp_associator_flags; __struct {N unsigned fcp_spp$v_reserved1 : 8; /* Reserved */g unsigned fcp_spp$v_acc_rsp_code : 4; /* Accept response codes (PRLI: p. 43, PRLO: p. 49) */N   unsigned fcp_spp$v_reserved2 : 1; /* Reserved */W unsigned fcp_spp$v_established_image_pair : 1; /* Image pair established */d unsigned fcp_spp$v_rspndr_proc_assoc_valid : 1; /* Responder process associator valid */c unsigned fcp_spp$v_orig_proc_assoc_valid : 1; /* Originator process associator valid */N char fcp_spp$b_type_code_extension; /* Type code extension */N char fcp_spp$b_type_code; /* Type code (eg ., SCSI FCP = 08) */! } fcp_spp$r_fill_15_; } fcp_spp$r_fill_14_;N int fcp_spp$l_orig_proc_assoc; /* Originator process associator */N int fcp_spp$l_rspndr_proc_assoc; /* Responder process associator */ __union {/ int fcp_spp$l_common_service_parameter; __union {N int fcp_spp$l_spp_function_flags; /* Service parameters (p. 17) */ __struct {f unsigned fcp_spp$v_write_xfer_rdy_disabled : 1 ; /* FCP_XFER_RDY disallowed on write */d unsigned fcp_spp$v_read_xfer_rdy_disabled : 1; /* FCP_XFER_RDY disallowed on read */r unsigned fcp_spp$v_data_rsp_mix_allowed : 1; /* FCP_DATA and FCP_RSP may be combined in one IU */r unsigned fcp_spp$v_cmd_data_mix_allowed : 1; /* FCP_CMND and FCP_DATA may be combined in one IU */U unsigned fcp_spp$v_target_function : 1; /* Functioning as a target */\ unsigned fcp_spp$v_initiat or_function : 1; /* Functioning as an initiator */X unsigned fcp_spp$v_data_overlay_allowed : 1; /* Data overlays allowed */N unsigned fcp_spp$v_reserved3 : 25; /* Reserved */% } fcp_spp$r_fill_17_;! } fcp_spp$r_fill_16_;# } fcp_spp$r_spp_longword_3; } SERVICE_PARAM_PAGE_T; #if !defined(__VAXC)X#define fcp_spp$l_spp_associator_flags fcp_spp$r_fill_14_.fcp_spp$l_spp_associator_flagsU#define fcp_spp$v_reserved1 fcp_spp$r_fill_14_.fcp_spp$r_fill_15_.fcp_spp$v_reserved1[#define fcp_spp$v_acc_rsp_code fcp_spp$r_fill_14_.fcp_spp$r_fill_15_.fcp_spp$v_acc_rsp_codeU#define fcp_spp$v_reserved2 fcp_spp$r_fill_14_.fcp_spp$r_fill_15_.fcp_spp$v_reserved2o#define fcp_spp$v_established_image_pair fcp_spp$r_fill_14_.fcp_spp$r_fill_15_.fcp_spp$v_established_image_pairq#define fcp_spp$v_rspndr_proc_assoc_valid fcp_spp$r_fill_14_.fcp_spp$r_fill_15_.fcp_spp$v_rspndr_proc_assoc_validm#define fcp_spp$v_orig_proc_assoc_valid fcp_spp$r_fill_14_.fcp_spp$r_fill_15_.fcp_spp$v_orig_proc_assoc_validi#define fcp_spp$b_type_code_extension fcp_spp$r_fill_14_.fcp_spp$r_fill_15_.fcp_spp$b_type_code_extensionU#define fcp_spp$b_type_code fcp_spp$r_fill_14_.fcp_spp$r_fill_15_.fcp_spp$b_type_codef#define fcp_spp$l_common_service_parameter fcp_spp$r_spp_longword_3.fcp_spp$l_common_service_parameterm#define fcp_spp$l_spp_function_flags fcp_spp$r_spp_longword_3.fcp_spp$r_fill_16_.fcp_spp$l_spp_function_flags#define fcp_spp$v_write_xfer_rdy_disabled fcp_spp$r_spp_longword_3.fcp_spp$r_fill_16_.fcp_spp$r_fill_17_.fcp_spp$v_write_xfer_rdy_d\isabled#define fcp_spp$v_read_xfer_rdy_disabled fcp_spp$r_spp_longword_3.fcp_spp$r_fill_16_.fcp_spp$r_fill_17_.fcp_spp$v_read_xfer_rdy_dis\abled#define fcp_spp$v_data_rsp_mix_allowed fcp_spp$r_spp_longword_3.fcp_spp$r_fill_16_.fcp_spp$r_fill_17_.fcp_spp$v_data_rsp_mix_allowed#define fcp_spp$v_cmd_data_mix_allowed fcp_spp$r_spp_longword_3.fcp_spp$r_fill_16_.fcp_spp$r_fill_17_.fcp_spp$v_cmd_data_mix_allowedz#define fcp_spp$v_target_function fcp_spp$r_spp_longword_3.fcp_spp$r_fill_16_.fcp_spp$r_fill_17_.fcp_spp$v_target_function#define fcp_spp$v_initiator_function fcp_spp$r_spp_longword_3.fcp_spp$r_fill_16_.fcp_spp$r_fill_17_.fcp_spp$v_initiator_function#define fcp_spp$v_data_overlay_allowed fcp_spp$r_spp_longword_3.fcp_spp$r_fill_16_.fcp_spp$r_fill_17_.fcp_spp$v_data_overlay_allowedn#define fcp_spp$v_reserved3 fcp_spp$r_spp_longword_3.fcp_spp$r_fill_16_.fcp_spp$r_ fill_17_.fcp_spp$v_reserved3"#endif /* #if !defined(__VAXC) */ N/* This structure was added in revision X-4 */#define FER$K_FCP_CDB_LENGTH 16N/* Calculate the number of quadwords in the array */#define FER$K_FCP_CMND_QUADS 4N/* Create a quadword-aligned array of quadwords */%#define FER$K_SCSI_SNS_INFO_LENGTH 16N/* Calculate the number of quadwords in the array */#define FER$K_FCP_RSP_QUADS 6N/* Create a quadword-aligned array of quadwords */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; struct _scdt; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif"typedef struct _fcp_event_record {N/* --------------------  */N/* I/O Request Section */N/* -------------------- */N/* System time of request completion */#pragma __nomember_alignment# unsigned __int64 fer$q_systime;N/* Restart sequence number */" unsigned int fer$l_fer_seqnum;N/* Class driver UCB address from SCDT  */" struct _ucb *fer$ps_class_ucb;N/* Requested Byte Count */& unsigned int fer$l_requested_bcnt;N/* IRP sequence number (identifies I/O request) */ unsigned int fer$l_seqnum;N/* --------------------------- */N/* I/O Request Status Section */N/* ---------------------------  */N/* KPB or fork thread restart (by FC-AD) status */& unsigned int fer$l_restart_status;N/* FC-AD status mapped to an OpenVMS status - this will usually be the */N/* same as the RESTART_STATUS, but there are cases (at least one: when */N/* a request times out) when a KPB is restarted by the FC-AD with a */N/* special status which will differ from PORT_STATUS */# unsigned int fer$l_port_ status;N/* Additional data (if any) associated with the FC-AD status */' unsigned int fer$l_extended_status;N/* VMS status returned by protocol driver */' unsigned int fer$l_protocol_status;N/* Returned Byte Count */% unsigned int fer$l_returned_bcnt;N/* -------------------- */N/* FCP Command Section  */N/* -------------------- */N/* */N/* This array will be loaded with quadword copies. When an SDA */N/* extension references it for output it can copy the array */N/* address to an FCP_CMND structure and use FCP_CMND$ symbols */N/* */ N/* Define language-specific symbols for the CDB length */N/* Define language-specific symbols for the number of quadwords */ char fer$b_fill_18_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif- unsigned __int64 fer$q_fcp_cmnd_quad [4];N/* --------------------- */N/* FCP Response Section */N/* --------------------- */N/* */N/* This array will be loaded with quadword copies. When an SDA */N/* extension references it for output it can copy the array */N/* address to an FCP_RSP structure and use FCP_RSP$ symbols */N/*  */N/* Define the number of bytes of sense data we want in this array */N/* Define language-specific symbols for sense info length */N/* Define language-specific symbols for the number of quadwords */, unsigned __int64 fer$q_fcp_rsp_quad [6];N/* SCSI Connection Descriptor Table address */#pragma __nomember_alignment struct _scdt *fer$ps_scdt;N/* FibreChannel Logi cal Address (FC-LA) */ int fer$l_fc_la; } FCP_EVENT_RECORD;N/* Current FC_PROT version */$#define FCPROT$C_STRUCTURE_VERSION 1N/* Supported protocol count */+#define FCPROT$C_SUPPORTED_PROTOCOL_COUNT 3N/* Supported devices-per-protocol protocol count */(#define FCPROT$C_DEVICES_PER_PROTOCOL 26N/* FC protcol connection vectors */#define FCPROT$C_LENGTH 40  9#ifdef __cplusplus /* Define structure prototypes */struct _fcprot_vectab; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fc_prot {N/* Pointer to next FCPROT */#p ragma __nomember_alignment, struct _fc_prot *fcprot$ps_fcprot_flink;N/* Pointer to previous FCPROT */, struct _fc_prot *fcprot$ps_fcprot_blink;N/* Structure size */% unsigned short int fcprot$w_size;N/* Structure type (DYN$C_MISC) */ unsigned char fcprot$b_type;N/* Structure sub-type (DYN$C_FCPROT)  */# unsigned char fcprot$b_subtype;N/* Version of this structure */, unsigned int fcprot$l_structure_version;N/* Protocol count */- unsigned __int64 fcprot$q_protocol_count;N/* Pointers to protocol vector blocks */3 struct _fcprot_vectab *fcprot$ps_protocols [3];N/******************************************  */I/* Define the length of the structure. */N/****************************************** */N/* Quadword align the length */- char fcprot$t_length_quad_align_fill [4];N/* FCPROT length */ } FC_PROT;N/* FC protcol connection vectors */  9#ifdef __cplusplus /* Def!ine structure prototypes */struct _fcprot_descrip; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fcprot_vectab {N/* Pointers to protocol descriptors */#pragma __nomember_alignment: struct _fcprot_descrip *fcprot_vectab$ps_descrip [26]; } FCPROT_VECTA"B;N/* FC protcol descriptors */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _fcprot_descrip {N/* Pointer to UCB of driver associated with protocol */##pragma __nomember_alignment' struct _ucb *fcprot_descrip$ps_ucb;N/* Pointers to protocol vector */& int (*fcprot_descrip$ps_vector)(); } FCPROT_DESCRIP;  #endif $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#p $ragma __standard #endif /* __FCPDEF_LOADED */ ww'[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permissi%on of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, In&c. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:18 by OpenVMS SDL V3.7 */G/* Source: 15-JAN-2009 14:14:37 $1$DGA834 '5:[LIB_H.SRC]FCPHDEF.SDL;1 *//********************************************************************************************************************************/"/*** MODULE FCPHDEF IDENT X-6 ***/#ifndef __FCPHDEF_LOADED#define __FCPHDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_point(er_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !d)efined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* FCPHDEF - */N/*- */ #ifndef _FCPHDEF_LOADED#define _FCPHDEF_LOADED#include  N/*+ */N/* * */I/* Extended Link Service codes */N/* */I/* If the code represents an Extended Link Service request, and not */I/* a response (what the documents above call a reply), then it will */I/* appear in bits 31:24 of word 0 of the payload sent with the */I/* following frame header control bits: + */N/* */I/* * Routing, Word 0, bits 31:28 = 0x02 (R_CTL) */M/* * Information Category, Word 0, bits 27:24 = 0x02 (Unsolicited Control) */I/* * Type, Word 1, bits 31:24 = 0x01 */N/* */I/* If the code represents a response, the following values appear: */N/* , */I/* * Routing, Word 0 (R_CTL), bits 31:28 = 0x02 */K/* * Information Category, Word 0, bits 27:24 = 0x02 (Solicited Control) */I/* * Type, Word 1, bits 31:24 = 0x01 */N/* */K/* Ref: Fibre Channel Physical & Signaling Interface-2 (FC-PH-2) Rev 7.3 */I/* Working draft of 5-January-1996 - */N/* Page 36, table 61 */N/* */N/*- */Q#define ELS$K_LS_RJT 1 /* 0x01 Link Service Reject (response) */N#define ELS$K_ACC 2 /* 0x02 Accept (response) */N#define ELS$K_PLOGI 3 /* 0x03 N_Port Login . */N#define ELS$K_FLOGI 4 /* 0x04 F_Port Login */N#define ELS$K_LOGO 5 /* 0x05 Logout */N#define ELS$K_ABTX 6 /* 0x06 Abort Exchange */N#define ELS$K_RSC 7 /* 0x07 Read Connection Status */N#define ELS$K_RES 8 /* 0x08 Read Exchange Status Block */N#define ELS$K_RSS 9 /* 0x09 Read Sequence Status Block */N#define ELS$K_RSI 10/ /* 0x0A Request Sequence Initiative */N#define ELS$K_ESTS 11 /* 0x0B Establish Streaming */N#define ELS$K_ESTC 12 /* 0x0C Estimate Credit */N#define ELS$K_ADVC 13 /* 0x0D Advise Credit */N#define ELS$K_RTV 14 /* 0x0E Read Time-Out Value */N#define ELS$K_RLS 15 /* 0x0F Read Link Status */N#define ELS$K_ECHO 16 /* 0x100 Echo */N#define ELS$K_TEST 17 /* 0x11 Test */O#define ELS$K_RRQ 18 /* 0x12 Reinstate Recovery Qualifier */#define ELS$K_ELP 16N#define ELS$K_PRLI 32 /* 0x20 Process Login */N#define ELS$K_PRLO 33 /* 0x21 Process Logout */N#define ELS$K_SCN 34 /* 0x22 State Change Notification */N#define ELS$K_TPLS 35 /* 0x23 1Test Process Login State */N#define ELS$K_TPRLO 36 /* 0x24 Third Party Logout State */N#define ELS$K_GAID 48 /* 0x30 Get Alias_ID */N#define ELS$K_FACT 49 /* 0x31 Fabric Activate Alias_ID */N#define ELS$K_FDACT 50 /* 0x32 Fabric Deactivate Alias_ID */N#define ELS$K_NACT 51 /* 0x33 N_Port Activate Alias_ID */N#define ELS$K_NDACT 52 /* 0x34 N_Port Deactivate Alias_ID2 */N#define ELS$K_QOSR 64 /* 0x40 Quality of Service Request */N#define ELS$K_RVCS 65 /* 0x41 Read Virtual Circuit Status */U#define ELS$K_PDISC 80 /* 0x50 Discover N_Port Service Parameters */U#define ELS$K_FDISC 81 /* 0x51 Discover F_Port Service Parameters */N#define ELS$K_ADISC 82 /* 0x52 Discover Address */N#define ELS$K_RNC 83 /* 0x53 Report Node Capability */Y#def3ine ELS$K_FARP_REQ 84 /* 0X54 Fibre Channel Addr resolution proto rq */\#define ELS$K_FARP_REPLY 85 /* 0x55 Fibre Channel Addr resolution proto reply */N#define ELS$K_RPS 86 /* 0x56 Read Port Status Block */N#define ELS$K_RPL 87 /* 0X57 Read Port List */N#define ELS$K_FAN 96 /* 0x60 Fabric Address Notification */W#define ELS$K_RSCN 97 /* 0x61 Registered State Change Notification4 */N#define ELS$K_SCR 98 /* 0x62 State Change Request */N#define ELS$K_RNFT 99 /* 0x63 Report node FC-4 types */S#define ELS$K_RNID 120 /* 0x78 Request Node Identification data */R#define ELS$K_RLIR 121 /* 0x79 Registered Link Incident Report */T#define ELS$K_LIRR 122 /* 0x7A Link Incident Record Registration */N#define ELS$K_SRL 123 /* 0x7B Scan Remote Loop */N/*+ 5 */N/* */N/* Frame Header type codes for when routing bits are set to */N/* FC-4 Device Data or FC-4 Link Data. */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of June 1, 16994 */N/* Page 100 table 36 */N/* */N/*- */N#define FCPH$K_ISO_8802_2_LLC 4 /* 0x04 ISO/IEC 8802-2 LLC */N#define FCPH$K_ISO_8802_2_LLC_SNAP 5 /* 0x05 ISO/IEC 8802-2 LLC/SNAP */N#define FCPH$K_RESERVED_1 6 /* 0x06 Reserved 7 */N#define FCPH$K_RESERVED_2 7 /* 0x07 Reserved */N#define FCPH$K_SCSI_FCP 8 /* 0x08 SCSI FCP */N#define FCPH$K_SCSI_GPP 9 /* 0x09 SCSI GPP */#define FCPH$K_IPI_3 16#define FCPH$K_IPI_MASTER 17#define FCPH$K_IPI_SLAVE 18#define FCPH$K_IPI_PEER 19#define FCPH$K_CP_IPI_MASTER 21#define FCPH$K_CP_IPI_SLAVE 22#define FCPH$K_CP_IPI_PEER 23#define FCPH$K_SBCCS_CHANNEL 25$#def8ine FCPH$K_SBCCS_CONTROL_UNIT 26(#define FCPH$K_FIBRE_CHANNEL_SERVICES 32N/*+ */N/* */N/* Frame Header type codes for when routing bits are set to */N/* Basic or Extended Link Data. */N/* */I/* Ref: Fibre Channel Physical 9 & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of June 1, 1994 */N/* Page 100 table 34 */N/* */N/*- */%#define FCPH$K_BASIC_LINK_SRVC_TYPE 0(#define FCPH$K_EXTENDED_LINK_SRVC_TYPE 1 #define FCPH$K_ALL_ONES_MASK 255N/*+ : */N/* */N/* Information Categories used in the R_CTL frame header */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of June 1, 1994 */N/* Page 98 table 29 ; */N/* */N/*- */N#define FCPH$K_UNCAT_INFO 0 /* Uncategorized information */#define FCPH$K_SOLICITED_DATA 1$#define FCPH$K_UNSOLICITED_CONTROL 2"#define FCPH$K_SOLICITED_CONTROL 3!#define FCPH$K_UNSOLICITED_DATA 4 #define FCPH$K_DATA_DESCRIPTOR 5$#define FCPH$K_UNSOLICITED_COMMAND 6#define FCPH$K_COMMAND_STATUS 7<N/*+ */N/* */N/* Routing Bits used in the R_CTL frame header field */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of June 1, 1994 */N/* Page 97 table 28 = */N/* */N/*- */N#define FCPH$K_DEVICE_DATA 0 /* 0x00 FC-4 Device data frame */N#define FCPH$K_RESERVED_3 1 /* 0x01 */N#define FCPH$K_EXTENDED_LINK_SRVC 2 /* 0x02 */N#define FCPH$K_LINK_DATA 3 /* 0x03 FC-4 Link >Data */N#define FCPH$K_VIDEO_DATA 4 /* 0x04 */N#define FCPH$K_RESERVED_4 5 /* 0x05 */N#define FCPH$K_RESERVED_5 6 /* 0x06 */N#define FCPH$K_RESERVED_6 7 /* 0x07 */N#define FCPH$K_BASIC_LINK_SRVC 8 /* 0x08 */N#define FCPH$K_RESERVED_7 9 /* 0x09 */N#def?ine FCPH$K_RESERVED_8 10 /* 0x0A */N#define FCPH$K_RESERVED_9 11 /* 0x0B */N#define FCPH$K_LINK_CONTROL 12 /* 0x0C */ #define FCPH$K_FC4_DEVICE_DATA 0N/*+ */N/* */I/* BA_RJT (Basic Reject) Reason Codes */N@/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */N/* Page 140, table 59 */N/* */N/*- */N#define BA_RJT$K_INVALID 1 A /* 0x01 Invalid Command Code */N#define BA_RJT$K_LOGICAL_ERR 3 /* 0x03 Logical Error */N#define BA_RJT$K_LOGICAL_BSY 5 /* 0x05 Logical Busy */N#define BA_RJT$K_PROTOCOL_ERR 7 /* 0x07 Protocol Error */T#define BA_RJT$K_UNABLE 9 /* 0x09 Unable to Perform Command Request */N/*+ */N/* B */I/* BA_RJT Type */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-January-1996 */N/* Page 139, figure 57 */N/* */N/*- C */ typedef struct _ba_rjt_t { char ba_rjt$b_vendor_unique; char ba_rjt$b_reason_exp; char ba_rjt$b_reason; char ba_rjt$b_reserved; } BA_RJT_T;N/*+ */N/* */I/* BA_RJT (Basic Reject) Reason Code Explanations */N/* D */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */N/* Page 140, table 60 */N/* */N/*- */N#define BA_RJT_EXP$K_NO_MORE_INFO 0 /* 0x00 No AdditioEnal Explanation */T#define BA_RJT_EXP$K_INVALID_ID_COMBO 3 /* 0x03 Invalid OX_ID - RX_ID Combination */e#define BA_RJT_EXP$K_SEQUENCE_ABORTED 5 /* 0x05 Sequence Aborted, No Sequence Information Provided */N/*+ */N/* */I/* LS_RJT_RSN Type */N/* F */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-January-1996 */N/* Page 156, figure 58 */N/* */N/*- */ typedef struct _ls_rjt_rsn_t {$ char ls_rjt_rsn$b_vendor_unique;! char ls_rj Gt_rsn$b_reason_exp; char ls_rjt_rsn$b_reason; char ls_rjt_rsn$b_reserved; } LS_RJT_RSN_T;N/*+ */N/* */I/* LS_RJT Type */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* H Working draft of 5-January-1996 */N/* Page 155, section 21.5.2 */N/* */N/*- */##define LS_RJT$M_RESERVED1 0xFFFFFF typedef struct _ls_rjt {N/* ELS command code field */ __struct {) unsigned ls_rjt$ Iv_reserved1 : 24;0 unsigned char ls_rjt$b_els_command_code;' } ls_rjt$r_els_command_overlay;N/* Reason the request is being rejected */! LS_RJT_RSN_T ls_rjt$r_reason; } LS_RJT; #if !defined(__VAXC)J#define ls_rjt$v_reserved1 ls_rjt$r_els_command_overlay.ls_rjt$v_reserved1X#define ls_rjt$b_els_command_code ls_rjt$r_els_command_overlay.ls_rjt$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ J */N/* */I/* LS_RJT (Link Service Reject) Reason Codes */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */N/* Page 156, table 90 K */N/* */N/*- */N#define LS_RJT$K_INVALID_LA 1 /* 0x01 Invalid LA Command Code */N#define LS_RJT$K_LOGICAL_ERR 3 /* 0x03 Logical Error */N#define LS_RJT$K_LOGICAL_BSY 5 /* 0x05 Logical Busy */N#define LS_RJT$K_PROTOCOL_ERR 7 /* 0x07 Protocol Error */T#define LS_RJTL$K_UNABLE 9 /* 0x09 Unable to Perform Command Request */N#define LS_RJT$K_CMD_UNSUPPORTED 11 /* 0x0B Command Not Supported */N/*+ */N/* */I/* LS_RJT (Link Service Reject) Reason Code Explanations */N/* */I/* Ref: Fibre Channel Physical & SignaMling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */N/* Page 157, table 91 */N/* */N/*- */N#define LS_RJT_EXP$K_NO_MORE_INFO 0 /* 0x00 No Additional Explanation */T#define LS_RJT_EXP$K_SPARM_OPTS 1 /* 0x01 Service Parameter Error N- Options */^#define LS_RJT_EXP$K_SPARM_INI_CTL 3 /* 0x03 Service Parameter Error - Initiator Control */^#define LS_RJT_EXP$K_SPARM_REC_CTL 5 /* 0x05 Service Parameter Error - Recipient Control */e#define LS_RJT_EXP$K_SPARM_RDAT_FLD_SZ 7 /* 0x07 Service Parameter Error - Receive Data Field Size */a#define LS_RJT_EXP$K_SPARM_CONCUR_SEQ 9 /* 0x09 Service Parameter Error - Concurrent Sequences */S#define LS_RJT_EXP$K_SPARM_CREDIT 11 /* 0x0B Service Parameter Error - Credit */P#define LSO_RJT_EXP$K_INV_PORT_NAME 13 /* 0x0D Invalid N-Port or F-Port Name */N#define LS_RJT_EXP$K_INV_NAME 14 /* 0x0E Invalid Node or Fabric Name */V#define LS_RJT_EXP$K_INV_COMMON_SPARMS 15 /* 0x0F Invalid Common Service Parameters */N#define LS_RJT_EXP$K_INV_ASSOC_HDR 17 /* 0x11 Invalid Association Header */N#define LS_RJT_EXP$K_ASSOC_HDR_REQ 19 /* 0x13 Association Header Required */N#define LS_RJT_EXP$K_INV_ORIG_S_ID 21 /* 0x15 Invalid Originator S_ID */T#define LS_RJT_EXP$K_INV_IPD_COMBO 23 /* 0x17 Invalid OX_ID + RX_ID Combination */Y#define LS_RJT_EXP$K_CMD_REQ_IN_PROG 25 /* 0x19 Command or Request Already in Progress */N#define LS_RJT_EXP$K_INV_N_PORT_ID 31 /* 0x1F Invalid N-Port Identifier */W#define LS_RJT_EXP$K_INV_SEQ_ID 33 /* 0x21 Invalid Sequence Identifier (SEQ_ID) */W#define LS_RJT_EXP$K_INV_EXC_ABORT 35 /* 0x23 Attempt to Abort an Invalid Exchange */X#define LS_RJT_EXP$K_INACT_EXC_ABORT 37 /* 0x25 Attempt to Abort an Inactive Exchange */N#defQine LS_RJT_EXP$K_REC_QUAL_REQ 39 /* 0x27 Recovery Qualifier Required */\#define LS_RJT_EXP$K_INSF_RES_FOR_LOGIN 41 /* 0x29 Insufficent Resources to Support Login */R#define LS_RJT_EXP$K_UNABLE_REQ_DAT 42 /* 0x2A Unable to Supply Requested Data */N#define LS_RJT_EXP$K_REQ_UNSUP 44 /* 0x2C Request Not Supported */N/*+ */N/* */I/* F_BSY TypRe */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */I/* Page 126, figure 54 */N/* */N/*- S */#define F_BSY$M_REASON 0xF!#define F_BSY$M_LINK_CONTROL 0xF0 typedef struct _f_bsy_t { unsigned f_bsy$v_reason : 4;& unsigned f_bsy$v_link_control : 4; } F_BSY_T;N/*+ */N/* */I/* F_BSY Reason codes */N/* T */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-January-1996 */N/* Page 126, table 51 */N/* */N/*- */ #define F_BSY_RSN$K_FABRIC_BSY 1 #define F_BSY_RSN$K_N_PORT_BSY 3N/*+ U */N/* */I/* P_BSY Type */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-January-1996 */N/* Page 127, figure 55 V */N/* */N/*- */ typedef struct _p_bsy_t { char p_bsy$b_vendor_unique; char p_bsy$b_reserved1; char p_bsy$b_reason; char p_bsy$b_action; } P_BSY_T;N/*+ */N/* W*/I/* P_BSY Action codes */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-January-1996 */N/* Page 127, table 52 */N/* */N/*- X */!#define P_BSY_ACTION$K_SEQ_TERM 1 #define P_BSY_ACTION$K_SEQ_ACT 2N/*+ */N/* */I/* P_BSY Reason codes */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 Y */N/* Working draft of 5-January-1996 */N/* Page 128, table 53 */N/* */N/*- */%#define P_BSY_RSN$K_PHYS_N_PORT_BSY 1$#define P_BSY_RSN$K_N_PORT_RES_BSY 3)#define P_BSY_RSN$K_VENDOR_UNIQUE_BSY 255N/*+ Z */N/* */I/* P_BSY Type */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-January-1996 */N/* Page 128, figure 56 */N/* [ */N/*- */ typedef struct _rjt_t { char rjt$b_vendor_unique; char rjt$b_reserved1; char rjt$b_reason; char rjt$b_action; } RJT_T;N/*+ */N/* */I/* Reject Action codes \ */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */N/* Page 129, table 54 */N/* */N/*- */$#def]ine RJT_ACTION$K_RETRYABLE_ERR 1(#define RJT_ACTION$K_NON_RETRYABLE_ERR 2N/*+ */N/* */I/* Reject Reason codes */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-Januar^y-1996 */N/* Pages 129-130, table 55 */N/* */N/*- */N#define RJT_RSN$K_INV_D_ID 1 /* 0x01 Invalid D_ID */N#define RJT_RSN$K_INV_S_ID 2 /* 0x02 Invalid S_ID */R#define RJT_RSN$K_PORT_UNAVAIL_TEMP 3 /* 0x03 N-Port Not Avail_able, Temporary */R#define RJT_RSN$K_PORT_UNAVAIL_PERM 4 /* 0x04 N-Port Not Available, Permanent */N#define RJT_RSN$K_CLASS_UNSUP 5 /* 0x05 Class Not Supported */N#define RJT_RSN$K_DELIM_USE_ERR 6 /* 0x06 Delimiter Usage Error */N#define RJT_RSN$K_TYPE_UNSUP 7 /* 0x07 TYPE Not Supported */N#define RJT_RSN$K_INV_LINK_CTL 8 /* 0x08 Invalid Link Control */N#define RJT_RSN$K_INV_R_CTL 9 /* 0x09 Invalid R_CTL Field */N#d`efine RJT_RSN$K_INV_F_CTL 10 /* 0x0A Invalid F_CTL Field */N#define RJT_RSN$K_INV_OX_ID 11 /* 0x0B Invalid OX_ID */N#define RJT_RSN$K_INV_RX_ID 12 /* 0x0C Invalid RX_ID */N#define RJT_RSN$K_INV_SEQ_ID 13 /* 0x0D Invalid SEQ_ID */N#define RJT_RSN$K_INV_DF_CTL 14 /* 0x0E Invalid DF_CTL */N#define RJT_RSN$K_INV_SEQ_CNT 15 /* 0x0F Invalid SEQ_CNT */N#define RJT_RSN$K_INV_PARM_FaLD 16 /* 0x10 Invalid Parameter Field */N#define RJT_RSN$K_EXC_ERR 17 /* 0x11 Exchange Error */N#define RJT_RSN$K_PROTOCOL_ERR 18 /* 0x12 Protocol Error */N#define RJT_RSN$K_INCORRECT_LEN 19 /* 0x13 Incorrect Length */N#define RJT_RSN$K_UNEXPECTED_ACK 20 /* 0x14 Unexpected ACK */N#define RJT_RSN$K_RESERVED_0X15 21 /* 0x15 Reserved */N#define RJT_RSN$K_LOGIN_REQUIRED 22 /* 0x16 Login bRequired */P#define RJT_RSN$K_EXCESS_SEQ_ATTEMPT 23 /* 0x17 Excessive Sequences Attempted */O#define RJT_RSN$K_UNABLE_EST_EXC 24 /* 0x18 Unable to Establish Exchange */[#define RJT_RSN$K_EXP_SEC_HDR_UNSUP 25 /* 0x19 Expiration Security Header Not Supported */N#define RJT_RSN$K_FABRIC_PATH_UNAVAIL 26 /* 0x1A Fabric Path Not Available */N#define RJT_RSN$K_VENDOR_UNIQUE_ERR 255 /* 0xFF Vendor Unique Error */N/*+ c */N/* */I/* A single structure is used to define Service Parameters for each of */I/* the classes of service, with the understanding that some parameters */L/* are meaningless for some classes. The following data structure defines */J/* the format of the Service Parameters. Note that this is not the same */I/* as the Common Service Parameters structure which is used to define */I/* values which do apply tdo a N-Port or F-Port Login regardless of the */I/* class of service used to perform any particular Exchange. */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-January-1996 */N/* Page 185, figure 62 */N/* e */I/* Table 101 on page 186 of the same reference is used to determine */I/* which Service Parameter fields are valid for a particular class */I/* of service for both N-Port and F-Port Logins. */N/* */N/*- */$#define SPR$M_INI_CTL_RESERVED 0x3FF'#define SPR$M_INI_ACK_N_SUPPORTED 0x400'#define SPR$M_INI_ACK_f0_SUPPORTED 0x800&#define SPR$M_INI_RSP_PRC_ASSOC 0x3000(#define SPR$M_INI_X_ID_REASGN_REQ 0xC000$#define SPR$M_SRV_OPT_RESERVED 0x7FF #define SPR$M_SEQ_DELIVERY 0x800$#define SPR$M_STACKED_CON_REQ 0x3000"#define SPR$M_INTERMIX_MODE 0x4000 #define SPR$M_CLASS_VALID 0x8000+#define SPR$M_RECEIVE_DATA_FIELD_SIZE 0xFFF%#define SPR$M_RESERVED_FOR_FABRIC 0xF#define SPR$M_RESERVED1 0xF0-#define SPR$M_R_CATEGORIES_PER_SEQUENCE 0x300#define SPR$M_RESERVED2 0x400/#define SPR$M_R_ERROR_POLICIgES_SUPPORTED 0x1800%#define SPR$M_R_X_ID_INTERLOCK 0x2000&#define SPR$M_R_ACK_N_SUPPORTED 0x4000&#define SPR$M_R_ACK_0_SUPPORTED 0x8000-#define SPR$M_N_PORT_END_TO_END_CREDIT 0x7FFF#define SPR$M_RESERVED3 0x8000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif$typedef struct _service_parameters {#pragma __nomember_alignment __union {% h int spr$l_longword_0_overlay; __struct {N/* */N/* Initiator Control Flags */N/* */N/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-January-1996 */N/* Page 190, figure 65 i */N/* */ __union {= short int spr$w_initiator_control_flags_over; __struct {9 unsigned spr$v_ini_ctl_reserved : 10;; unsigned spr$v_ini_ack_n_supported : 1;; unsigned spr$v_ini_ack_0_supported : 1;9 unsigned spr$v_ini_rsp_prc_assoc : 2;; unsigned spr$v j_ini_x_id_reasgn_req : 2;$ } spr$r_fill_3_; } spr$r_fill_2_;N/* */N/* Service Options */N/* */N/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-January-1996 */N/* k Page 190, figure 64 */N/* */N/* The Class Valid bit is not shown in this figure but is */I/* described in the section in which the table appears. */N/* Note that at least in this revision of the standard */N/* the options defined for N-Port Login (figure 64) are */N/* the same as those defined fo lr F-Port Login (figure 63) */N/* */ __union {8 short int spr$w_service_options_overlay; __struct {9 unsigned spr$v_srv_opt_reserved : 11;4 unsigned spr$v_seq_delivery : 1;7 unsigned spr$v_stacked_con_req : 2;5 unsigned spr$v_intermix_mode : 1;3 unsigned spr$v_class_vmalid : 1;$ } spr$r_fill_5_; } spr$r_fill_4_; } spr$r_fill_1_; } spr$r_fill_0_; __union {% int spr$l_longword_1_overlay; __struct {N/* Receive Data Field Size */ __union {= short int spr$w_receive_data_field_size_over; __struct {@ unsigned spr$v_receive_data_field_size : 12;0 unsi ngned spr$v_fill_16_ : 4;$ } spr$r_fill_9_; } spr$r_fill_8_;N/* */N/* Recipient Control */N/* */N/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-January-1996 */N/* oPage 193, figure 66 */N/* */ __union {: short int spr$w_recipient_control_overlay; __struct {; unsigned spr$v_reserved_for_fabric : 4;1 unsigned spr$v_reserved1 : 4;A unsigned spr$v_r_categories_per_sequence : 2;1 unsigned spr$v_reserved2 : 1;B p unsigned spr$v_r_error_policies_supported : 2;8 unsigned spr$v_r_x_id_interlock : 1;9 unsigned spr$v_r_ack_n_supported : 1;9 unsigned spr$v_r_ack_0_supported : 1;% } spr$r_fill_11_;! } spr$r_fill_10_; } spr$r_fill_7_; } spr$r_fill_6_; __union {% int spr$l_longword_2_overlay; __struct {9 unsigned spr$v_n_port_end_to_end_credit : 15q;) unsigned spr$v_reserved3 : 1;1 short int spr$w_concurrent_sequences; } spr$r_fill_13_; } spr$r_fill_12_; __union {% int spr$l_longword_3_overlay; __struct {& short int spr$w_reserved4;3 char spr$b_open_sequences_per_exchange;! char spr$b_reserved5; } spr$r_fill_15_; } spr$r_fill_14_; } SERVICE_PARAMETERS; #if !defined(__VAXC)G#define spr$l_longword_0r_overlay spr$r_fill_0_.spr$l_longword_0_overlayw#define spr$w_initiator_control_flags_over spr$r_fill_0_.spr$r_fill_1_.spr$r_fill_2_.spr$w_initiator_control_flags_overm#define spr$v_ini_ctl_reserved spr$r_fill_0_.spr$r_fill_1_.spr$r_fill_2_.spr$r_fill_3_.spr$v_ini_ctl_reserveds#define spr$v_ini_ack_n_supported spr$r_fill_0_.spr$r_fill_1_.spr$r_fill_2_.spr$r_fill_3_.spr$v_ini_ack_n_supporteds#define spr$v_ini_ack_0_supported spr$r_fill_0_.spr$r_fill_1_.spr$r_fill_2_.spr$r_fill_3_.spr$v_ini_ack_s0_supportedo#define spr$v_ini_rsp_prc_assoc spr$r_fill_0_.spr$r_fill_1_.spr$r_fill_2_.spr$r_fill_3_.spr$v_ini_rsp_prc_assocs#define spr$v_ini_x_id_reasgn_req spr$r_fill_0_.spr$r_fill_1_.spr$r_fill_2_.spr$r_fill_3_.spr$v_ini_x_id_reasgn_reqm#define spr$w_service_options_overlay spr$r_fill_0_.spr$r_fill_1_.spr$r_fill_4_.spr$w_service_options_overlaym#define spr$v_srv_opt_reserved spr$r_fill_0_.spr$r_fill_1_.spr$r_fill_4_.spr$r_fill_5_.spr$v_srv_opt_reservede#define spr$v_seq_delivery spr$r_filtl_0_.spr$r_fill_1_.spr$r_fill_4_.spr$r_fill_5_.spr$v_seq_deliveryk#define spr$v_stacked_con_req spr$r_fill_0_.spr$r_fill_1_.spr$r_fill_4_.spr$r_fill_5_.spr$v_stacked_con_reqg#define spr$v_intermix_mode spr$r_fill_0_.spr$r_fill_1_.spr$r_fill_4_.spr$r_fill_5_.spr$v_intermix_modec#define spr$v_class_valid spr$r_fill_0_.spr$r_fill_1_.spr$r_fill_4_.spr$r_fill_5_.spr$v_class_validG#define spr$l_longword_1_overlay spr$r_fill_6_.spr$l_longword_1_overlayw#define spr$w_receive_data_field_size_over spru$r_fill_6_.spr$r_fill_7_.spr$r_fill_8_.spr$w_receive_data_field_size_over{#define spr$v_receive_data_field_size spr$r_fill_6_.spr$r_fill_7_.spr$r_fill_8_.spr$r_fill_9_.spr$v_receive_data_field_sizer#define spr$w_recipient_control_overlay spr$r_fill_6_.spr$r_fill_7_.spr$r_fill_10_.spr$w_recipient_control_overlayu#define spr$v_reserved_for_fabric spr$r_fill_6_.spr$r_fill_7_.spr$r_fill_10_.spr$r_fill_11_.spr$v_reserved_for_fabrica#define spr$v_reserved1 spr$r_fill_6_.spr$r_fill_7_.spr$r_fill_10_.svpr$r_fill_11_.spr$v_reserved1#define spr$v_r_categories_per_sequence spr$r_fill_6_.spr$r_fill_7_.spr$r_fill_10_.spr$r_fill_11_.spr$v_r_categories_per_sequencea#define spr$v_reserved2 spr$r_fill_6_.spr$r_fill_7_.spr$r_fill_10_.spr$r_fill_11_.spr$v_reserved2#define spr$v_r_error_policies_supported spr$r_fill_6_.spr$r_fill_7_.spr$r_fill_10_.spr$r_fill_11_.spr$v_r_error_policies_supportedo#define spr$v_r_x_id_interlock spr$r_fill_6_.spr$r_fill_7_.spr$r_fill_10_.spr$r_fill_11_.spr$v_r_x_id_interlwockq#define spr$v_r_ack_n_supported spr$r_fill_6_.spr$r_fill_7_.spr$r_fill_10_.spr$r_fill_11_.spr$v_r_ack_n_supportedq#define spr$v_r_ack_0_supported spr$r_fill_6_.spr$r_fill_7_.spr$r_fill_10_.spr$r_fill_11_.spr$v_r_ack_0_supportedH#define spr$l_longword_2_overlay spr$r_fill_12_.spr$l_longword_2_overlayc#define spr$v_n_port_end_to_end_credit spr$r_fill_12_.spr$r_fill_13_.spr$v_n_port_end_to_end_creditE#define spr$v_reserved3 spr$r_fill_12_.spr$r_fill_13_.spr$v_reserved3[#define spr$w_concurxrent_sequences spr$r_fill_12_.spr$r_fill_13_.spr$w_concurrent_sequencesH#define spr$l_longword_3_overlay spr$r_fill_14_.spr$l_longword_3_overlayE#define spr$w_reserved4 spr$r_fill_14_.spr$r_fill_15_.spr$w_reserved4i#define spr$b_open_sequences_per_exchange spr$r_fill_14_.spr$r_fill_15_.spr$b_open_sequences_per_exchangeE#define spr$b_reserved5 spr$r_fill_14_.spr$r_fill_15_.spr$b_reserved5"#endif /* #if !defined(__VAXC) */ N/*+ y */N/* */I/* Common Service Parameters used in N-Port and F-Port Login */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */N/* Working draft of 5-January-1996 */N/* Page 181, table 98 */N/* z */I/* NOTE: The Alternate Credit Model bit below is not described in the */I/* referenced document, it was taken from a booklet which came */I/* with a Seagate FC disk */I/* */N/*- */)#define CSP$M_BB_RCV_DATA_FLD_SIZE 0xFFFF!#define CSP$M_RESE{RVED1 0x3FF0000"#define CSP$M_E_D_TOV_NS 0x4000000(#define CSP$M_ALT_CREDIT_MODEL 0x8000000%#define CSP$M_F_PORT_LOGIN 0x10000000'#define CSP$M_VENDOR_VERSION 0x20000000/#define CSP$M_RANDOM_RELATIVE_OFFSET 0x400000000#define CSP$M_CONTINUOUSLY_INCREASING 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif+typedef struct _common_service_par |ameters {#pragma __nomember_alignment' unsigned short int csp$w_bb_credit;& unsigned char csp$b_low_fc_ph_rev;' unsigned char csp$b_high_fc_ph_rev; __struct {N unsigned csp$v_bb_rcv_data_fld_size : 16; /* Bits 00 to 15 */N unsigned csp$v_reserved1 : 10; /* Bits 16 to 25 */N unsigned csp$v_e_d_tov_ns : 1; /* Bit 26 */N unsigned csp$v_alt_credit_model : 1; /* Bit 27 */N } unsigned csp$v_f_port_login : 1; /* Bit 28 */N unsigned csp$v_vendor_version : 1; /* Bit 29 */N unsigned csp$v_random_relative_offset : 1; /* Bit 30 */N unsigned csp$v_continuously_increasing : 1; /* Bit 31 */ } csp$r_common_features; __union { __struct {' unsigned int csp$l_r_a_tov;" } csp$r_f_port_fields; __struct {4 unsi ~gned short int csp$w_offset_by_info;5 unsigned short int csp$w_total_sequences;" } csp$r_n_port_fields;! } csp$r_n_f_port_overlay; unsigned int csp$l_e_d_tov; } COMMON_SERVICE_PARAMETERS; #if !defined(__VAXC)S#define csp$v_bb_rcv_data_fld_size csp$r_common_features.csp$v_bb_rcv_data_fld_size=#define csp$v_reserved1 csp$r_common_features.csp$v_reserved1?#define csp$v_e_d_tov_ns csp$r_common_features.csp$v_e_d_tov_nsK#define csp$v_alt_credit_model csp$r_common_features.csp$v_alt_credit_modelC#define csp$v_f_port_login csp$r_common_features.csp$v_f_port_loginG#define csp$v_vendor_version csp$r_common_features.csp$v_vendor_versionW#define csp$v_random_relative_offset csp$r_common_features.csp$v_random_relative_offsetY#define csp$v_continuously_increasing csp$r_common_features.csp$v_continuously_increasingF#define csp$r_f_port_fields csp$r_n_f_port_overlay.csp$r_f_port_fields7#define csp$l_r_a_tov csp$r_f_port_fields.csp$l_r_a_tovF#d efine csp$r_n_port_fields csp$r_n_f_port_overlay.csp$r_n_port_fieldsE#define csp$w_offset_by_info csp$r_n_port_fields.csp$w_offset_by_infoG#define csp$w_total_sequences csp$r_n_port_fields.csp$w_total_sequences"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */J/* Placeholder definition for an IEEE address */N/*  */N/*- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _ieee_address_t {#pragma __nomember_alignment% unsigned char ieee$b_address [8]; } IEEE_ADDRESS_T;N#define IEEE$SZ_LENGTH 8  /*length of structure */N/*+ */N/* */J/* This structure is used to simplify reference to the block of data */I/* which is passed in several ELS requests. It is not used in the */I/* ELS request structures themselves because that would complicate */I/* referencing individual fields in it */N /* */N/*- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _port_data {#pragma __nomember_alignment7 COMMON_SERVICE_PARAMETERS port_data$r_common_sparm;) IEEE_ADDRESS_T port_data$r_por t_name;0 IEEE_ADDRESS_T port_data$r_node_fabric_name;1 SERVICE_PARAMETERS port_data$r_class_1_sparm;1 SERVICE_PARAMETERS port_data$r_class_2_sparm;1 SERVICE_PARAMETERS port_data$r_class_3_sparm;- unsigned char port_data$b_reserved2 [16];8 unsigned char port_data$b_vendor_version_level [16]; } PORT_DATA;N/* */N/* Network Address Authority identifiers */N/*  */#define NAA$K_IGNORED 0#define NAA$K_IEEE 1#define NAA$K_IEEE_EXTENDED 2 #define NAA$K_LOCALLY_ASSIGNED 3#define NAA$K_IP 4)#define NAA$K_CCITT_INDIVIDUAL_ADDRESS 12$#define NAA$K_CCITT_GROUP_ADDRESS 14N/*+ */N/* */J/* N Port Login Request  */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */I/* Page 148, table 71 */N/* */N/*- */&#define PLOGI_REQ$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _plogi_req_t {#pragma __nomember_alignment __struct {, unsigned plogi_req$v_reserved1 : 24;3 unsigned char plogi_req$b_els_command_code;* } plogi_req$r_els_command_overlay;7 COMMON_SERVICE_PARAMETERS plogi_req$r_common_sparm;) IEEE _ADDRESS_T plogi_req$r_port_name;0 IEEE_ADDRESS_T plogi_req$r_node_fabric_name;1 SERVICE_PARAMETERS plogi_req$r_class_1_sparm;1 SERVICE_PARAMETERS plogi_req$r_class_2_sparm;1 SERVICE_PARAMETERS plogi_req$r_class_3_sparm;- unsigned char plogi_req$b_reserved2 [16];8 unsigned char plogi_req$b_vendor_version_level [16]; } PLOGI_REQ_T; #if !defined(__VAXC)S#define plogi_req$v_reserved1 plogi_req$r_els_command_overlay.plogi_req$v_reserved1a#define plogi_req$b_els_co mmand_code plogi_req$r_els_command_overlay.plogi_req$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */J/* N Port Login Response */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I /* Working draft of 5-January-1996 */I/* Page 148, table 72 */N/* */N/*- */&#define PLOGI_RSP$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else #pragma __nomember_alignment#endiftypedef struct _plogi_rsp_t {#pragma __nomember_alignment __struct {, unsigned plogi_rsp$v_reserved1 : 24;3 unsigned char plogi_rsp$b_els_command_code;* } plogi_rsp$r_els_command_overlay;7 COMMON_SERVICE_PARAMETERS plogi_rsp$r_common_sparm;) IEEE_ADDRESS_T plogi_rsp$r_port_name;0 IEEE_ADDRESS_T plogi_rsp$r_node_fabric_name;1 SERVICE_PARAMETERS plogi_rsp$r_class_1_sparm;1 SERVICE_PARAMETERS plogi_rsp$r_cla ss_2_sparm;1 SERVICE_PARAMETERS plogi_rsp$r_class_3_sparm;- unsigned char plogi_rsp$b_reserved2 [16];8 unsigned char plogi_rsp$b_vendor_version_level [16]; } PLOGI_RSP_T; #if !defined(__VAXC)S#define plogi_rsp$v_reserved1 plogi_rsp$r_els_command_overlay.plogi_rsp$v_reserved1a#define plogi_rsp$b_els_command_code plogi_rsp$r_els_command_overlay.plogi_rsp$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+  */N/* */J/* Discover N-Port Parameters Request */N/* */K/* Ref: Fibre Channel Physical & Signaling Interface 2 (FC-PH-2) Rev 7.3 */I/* Working draft of 5-January-1996 */I/* Section 21.19.1 */N/*  */N/*- */&#define PDISC_REQ$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _pdisc_req_t {#pragma __nomember_alignment __struct {, unsigned pdisc_req$v_reserved1 : 24;3 unsigned char pdisc_req$b_els_command_code;* } pdisc_req$r_els_command_overlay;7 COMMON_SERVICE_PARAMETERS pdisc_req$r_common_sparm;) IEEE_ADDRESS_T pdisc_req$r_port_name;0 IEEE_ADDRESS_T pdisc_req$r_node_fabric_name;1 SERVICE_PARAMETERS pdisc_req$r_class_1_sparm;1 SERVICE_PARAMETERS pdisc_req$r_class_2_sparm;1 SERVICE_PARAMETERS pdisc_req$r_class_3_sparm;- unsigned char pdisc_req$b_reserved2 [16];8 unsigned char pdisc_req$b_vendor_version_level [16];  } PDISC_REQ_T; #if !defined(__VAXC)S#define pdisc_req$v_reserved1 pdisc_req$r_els_command_overlay.pdisc_req$v_reserved1a#define pdisc_req$b_els_command_code pdisc_req$r_els_command_overlay.pdisc_req$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */J/* Discover N-Port Parameters Response */N/* */K/* Ref: Fibre Channel Physical & Signaling Interface 2 (FC-PH-2) Rev 7.3 */I/* Working draft of 5-January-1996 */I/* Section 21.19.1 */N/* */N/*- */&#define PDISC_RSP$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _pdisc_rsp_t {#pragma __nomember_alignment __struct {, unsigned pdisc_rsp$v_reserved1 : 24;3 unsigned char pdisc_rsp$b_els_command_code;* } pdisc_rsp$r_els_command_overlay;7 COMMON_SERVICE_PARAMETERS pdisc_rsp$r_common_sparm;) IEEE_ADDRESS_T pdisc_r sp$r_port_name;0 IEEE_ADDRESS_T pdisc_rsp$r_node_fabric_name;1 SERVICE_PARAMETERS pdisc_rsp$r_class_1_sparm;1 SERVICE_PARAMETERS pdisc_rsp$r_class_2_sparm;1 SERVICE_PARAMETERS pdisc_rsp$r_class_3_sparm;- unsigned char pdisc_rsp$b_reserved2 [16];8 unsigned char pdisc_rsp$b_vendor_version_level [16]; } PDISC_RSP_T; #if !defined(__VAXC)S#define pdisc_rsp$v_reserved1 pdisc_rsp$r_els_command_overlay.pdisc_rsp$v_reserved1a#define pdisc_rsp$b_els_command_code pdisc_r sp$r_els_command_overlay.pdisc_rsp$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */J/* Abort Exchange Request */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working dr aft of 5-January-1996 */I/* Page 144, table 62 */N/* */N/*- */%#define ABTX_REQ$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _abtx_req_t {#pragma __nomember_alignment __struct {+ unsigned abtx_req$v_reserved1 : 24;2 unsigned char abtx_req$b_els_command_code;) } abtx_req$r_els_command_overlay; } ABTX_REQ_T; #if !defined(__VAXC)P#define abtx_req$v_reserved1 abtx_req$r_els_command_overlay.abtx_req$v_reserved1^#define abtx_req$b_els_command_code abtx_req$r_els_command_overlay.abtx_req$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */J/* Abort Exchange Response */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */I/* Page 145, table 63  */N/* */N/*- */%#define ABTX_RSP$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _abtx_rsp_t {#pragma __nomember_alignment __struct {+ unsigned abtx_rsp$v_reserved1 : 24;2 unsigned char abtx_rsp$b_els_command_code;) } abtx_rsp$r_els_command_overlay; } ABTX_RSP_T; #if !defined(__VAXC)P#define abtx_rsp$v_reserved1 abtx_rsp$r_els_command_overlay.abtx_rsp$v_reserved1^#define abtx_rsp$b_els_command_code abtx_rsp$r_els_command_overlay.abtx_rsp$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/*  */J/* Advise Credit Request */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */I/* Page 145, table 64 */N/*  */N/*- */%#define ADVC_REQ$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _advc_req_t {#pragma __nomember_alignment __struct {+ unsigned advc_req$v_reserved1 : 24;2 unsigned char advc_req$b_els_command_c ode;) } advc_req$r_els_command_overlay; } ADVC_REQ_T; #if !defined(__VAXC)P#define advc_req$v_reserved1 advc_req$r_els_command_overlay.advc_req$v_reserved1^#define advc_req$b_els_command_code advc_req$r_els_command_overlay.advc_req$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */J/* Advise Credit Response  */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */I/* Page 146, table 65 */N/* */N/*-  */%#define ADVC_RSP$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _advc_rsp_t {#pragma __nomember_alignment __struct {+ unsigned advc_rsp$v_reserved1 : 24;2 unsigned char advc_rsp$b_els_command_code;) } advc_rsp$r_els_command_overlay; } ADVC_RSP_T; #if !defined(__VAXC)P#define advc_rsp$v_reserved1 advc_rsp$r_els_command_overlay.advc_rsp$v_reserved1^#define advc_rsp$b_els_command_code advc_rsp$r_els_command_overlay.advc_rsp$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */J/* Logout Request */N/*  */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */I/* Page 149, table 73 */N/* */N/*- */%#define LOGO_REQ$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _logo_req_t {#pragma __nomember_alignment __struct {+ unsigned logo_req$v_reserved1 : 24;2 unsigned char logo_req$b_els_command_code;) } logo_req$r_els_command_overlay; __struct {& unsigned logo_req$v_d_id : 24;% unsigned logo_req$v_rsvd : 8;) } logo_req$r_n_port_id_structure;N /* Port Name */( IEEE_ADDRESS_T logo_req$r_port_name; } LOGO_REQ_T; #if !defined(__VAXC)P#define logo_req$v_reserved1 logo_req$r_els_command_overlay.logo_req$v_reserved1^#define logo_req$b_els_command_code logo_req$r_els_command_overlay.logo_req$b_els_command_codeF#define logo_req$v_d_id logo_req$r_n_port_id_structure.logo_req$v_d_idF#define logo_req$v_rsvd logo_req$r_n_port_id_structure.logo_req$v_rsvd"#endif /* #if ! defined(__VAXC) */ N/*+ */N/* */J/* Logout Response */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */I/* Page 1 49, table 74 */N/* */N/*- */%#define LOGO_RSP$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _logo_rsp_t {#pragma __nomember_a lignment __struct {+ unsigned logo_rsp$v_reserved1 : 24;2 unsigned char logo_rsp$b_els_command_code;) } logo_rsp$r_els_command_overlay; } LOGO_RSP_T; #if !defined(__VAXC)P#define logo_rsp$v_reserved1 logo_rsp$r_els_command_overlay.logo_rsp$v_reserved1^#define logo_rsp$b_els_command_code logo_rsp$r_els_command_overlay.logo_rsp$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+  */N/* */J/* Generic ACC */N/* */N/*- */##define LS_ACC$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _ls_acc {#pragma __nomember_alignment __struct {) unsigned ls_acc$v_reserved1 : 24;0 unsigned char ls_acc$b_els_command_code;' } ls_acc$r_els_command_overlay; } LS_ACC; #if !defined(__VAXC)J#define ls_acc$v_reserved1 ls_acc$r_els_command_overlay.ls_acc$v_reserved1X#define ls_acc$b_els_command_code ls_acc$r_els_command_overlay.ls_acc$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */J/* Read Link Error Status Block Request */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */I/* Page 151, table 79  */N/* */N/*- */$#define RLS_REQ$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rls_req_t {#pragma __nomember_alignment __struct {* unsigned rls_req$v_reserved1 : 24;1 unsigned char rls_req$b_els_command_code;( } rls_req$r_els_command_overlay; } RLS_REQ_T; #if !defined(__VAXC)M#define rls_req$v_reserved1 rls_req$r_els_command_overlay.rls_req$v_reserved1[#define rls_req$b_els_command_code rls_req$r_els_command_overlay.rls_req$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/*  */J/* Read Link Error Status Block Response */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */I/* Page 151, table 80 */N/*  */N/*- */$#define RLS_RSP$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rls_rsp_t {#pragma __nomember_alignment __struct {* unsigned rls_rsp$v_reserved1 : 24;1 unsigned char rls_rsp$b_els_command_code;( } rls_rsp$r_els_command_overlay; } RLS_RSP_T; #if !defined(__VAXC)M#define rls_rsp$v_reserved1 rls_rsp$r_els_command_overlay.rls_rsp$v_reserved1[#define rls_rsp$b_els_command_code rls_rsp$r_els_command_overlay.rls_rsp$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */L/* An Extended Link Service request or response is built by appending the */I/* appropriate payload to a longword which contains an Extended Link */J/* Service code. The structure being defined here can be used to create */I/* a buffer of a size which will contain any of the Basic or Extended */I/* Link Service payloads defined above. It can also be used as a */I/* type-independent pointer to a structure so the command code can be */I/* interpreted. */N/*  */N/*- */ #define ELS$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef union _els_t {#pragma __nomember_alignment __struct {& unsigned els$v_reserved1 : 24;- unsigned char els$b_els_command_code;+ } els$r_els_command_code_structure; __union {) PLOGI_REQ_T els$r_plogi_req_data;( PLOGI_RSP_T els$r_logi_rsp_data;' ABTX_REQ_T els$r_abtx_req_data;' ABTX_RSP_T els$r_abtx_rsp_data;' ADVC_REQ_T els$r_advc_req_data;' ADVC_RSP_T els$r_advc_rsp_data;' LOGO_REQ_T els$r_logo_req_data;' LOGO_RSP_T els$r_logo_rsp_data;% RLS_REQ_T els$r_rls_req_data;% RLS_RSP_T els$r_rls_rsp_data;" } els$r_els_command_union; } ELS_T; #if !defined(__VAXC)H#define els$v_reserved1 els$r_els_command_code_structure.els$v_reserved1V#define els$b_els_command_code els$r_els_command_code_structure.els$b_els_command_codeI#define els$r_plogi_req_data els$r_els_command_union.els$r_plogi_req_dataG#define els$r_logi_rsp_data els$r_els_command_union.els$r_logi_rsp_dataG#define els$r_abtx_req_data els$r_els_command_union.els$r_abtx_req_dataG#define els$r_abtx_rsp_data els$r_els_command_union.el s$r_abtx_rsp_dataG#define els$r_advc_req_data els$r_els_command_union.els$r_advc_req_dataG#define els$r_advc_rsp_data els$r_els_command_union.els$r_advc_rsp_dataG#define els$r_logo_req_data els$r_els_command_union.els$r_logo_req_dataG#define els$r_logo_rsp_data els$r_els_command_union.els$r_logo_rsp_dataE#define els$r_rls_req_data els$r_els_command_union.els$r_rls_req_dataE#define els$r_rls_rsp_data els$r_els_command_union.els$r_rls_rsp_data"#endif /* #if !defined(__VAXC) */  #endifN/*+ */N/* */J/* Maximum Number of Participating NL-Ports on an Arbitrated Loop */N/* */I/* Ref: Fibre Channel Arbitrated Loop (FC-AL-2) Rev 6.1 */I/* Working draft of 16-Feb-1998 */I/* Page 13, section 5.1.1  */N/* */I/* Note that this is a count of NL-Ports, and does not include */I/* the special AL-PA of 00, which is reserved for the single */I/* FL-Port which may or may not be present on the Arbitrated */I/* Loop */N/* */N/*- */#define FCAL$K_AL_PA_COUNT 126N/* */I/* PRLI Request Payload */N/* */I/* Ref: Fibre Channel Protocol for SCSI (SCSI-FCP) Rev 12 */I/* Draft proposal of 4-Dec-1995 */I/*  Table A.3, page 39 */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _prli_req {#pragma __nomember_alignmentV short int prli_req$w_payload_length; /* Total length of payload (typically 20.) */R char prli_req$b_page_length; /* Length of each service paramter page */Y unsigned char prli_req$b_els_command_code; /* Extended Link service command code */X SERVICE_PARAM_PAGE_T prli_req$r_service_parameter_page; /* Service parameter page */ } PRLI_REQ;N/* */I/* PRLI ACC Payload */N/* */I /* Ref: Fibre Channel Protocol for SCSI (SCSI-FCP) Rev 12 */I/* Draft proposal of 4-Dec-1995 */I/* Table A.5, page 41 */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftype def struct _prli_acc {#pragma __nomember_alignmentV short int prli_acc$w_payload_length; /* Total length of payload (typically 20.) */R char prli_acc$b_page_length; /* Length of each service paramter page */Y unsigned char prli_acc$b_els_command_code; /* Extended Link service command code */X SERVICE_PARAM_PAGE_T prli_acc$r_service_parameter_page; /* Service parameter page */ } PRLI_ACC;N/* */I/* PRLO Request Payload */N/* */I/* Ref: Fibre Channel Protocol for SCSI (SCSI-FCP) Rev 12 */I/* Draft proposal of 4-Dec-1995 */I/* Table A.8, page 46 */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) & & !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _prlo_req {#pragma __nomember_alignmentV short int prlo_req$w_payload_length; /* Total length of payload (typically 20.) */R char prlo_req$b_page_length; /* Length of each service paramter page */Y unsigned char prlo_req$b_els_command_code; /* Extended Link service command code */U LOGOUT_PARAM_PAGE_T prlo_req$r_logout_parameter_page; /* Logout parameter page */ } PRLO_REQ;N/* */I/* PRLO ACC Payload */N/* */I/* Ref: Fibre Channel Protocol for SCSI (SCSI-FCP) Rev 12 */I/* Draft proposal of 4-Dec-1995 */I/* Table A.10, page 48  */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _prlo_acc {#pragma __nomember_alignmentV short int prlo_acc$w_payload_length; /* Total length of payload (typically 20.) */R char prlo_acc$b_page_length; /* Length of each service paramter page */Y unsigned char prlo_acc$b_els_command_code; /* Extended Link service command code */X SERVICE_PARAM_PAGE_T prlo_acc$r_service_parameter_page; /* Service parameter page */ } PRLO_ACC;N/* */I/* Common Transport Information Unit (IU) */I/* FC-GS-2 R5.1 - Tables 1-3, 6 */N/*  */#define CTIU$M_RESERVED2 0x7F!#define CTIU$M_XBIT_EXCHANGE 0x80#define CTIU$K_BIDIRECT 0#define CTIU$K_MULTIPLE 1N#define CTIU$K_ALIAS_SERVER 248 /* F8: Alias server application */N#define CTIU$K_RESERVED1 249 /* F9: (reserved) */P#define CTIU$K_MGMT_SERVER 250 /* FA: Management service application */N#define CTIU$K_TIME_SERVER 251 /* FB: Time service application */O#define CTIU$K_DIRECTORY _SERVER 252 /* FC: Directory service application */Q#define CTIU$K_FABRIC 253 /* FD: Fabric controller service appl. */N/* Longword 2 */#define CTIU$K_NON_FC_IU 0#define CTIU$K_FS_RJT_IU 32769#define CTIU$K_FS_ACC_IU 32770N/* Longowrd 3 */N#define CTIU$K_NS_NO_ADDITIONAL_EXPL 0 /* 00: No additional explanation */P#define CTIU$K_NS_PORT_ID_NOT_REG 1 /* 01: Port identifier not registered */N#define CTIU$K_NS_PORT_NAME_NOT_REG 2 /* 02: Port name not registered */N#define CTIU$K_NS_NODE_NAME_NOT_REG 3 /* 03: Node name not registered */Q#define CTIU$K_NS_CLASS_SRV_NOT_REG 4 /* 04: Class of service not registered */S#define CTIU$K_NS_IP_ADDR_NODE_NOT_REG 5 /* 05: IP address (node) not registered */[#define CTIU$K_NS_IPA_NOT_REG 6 /* 06: Initial Process Associator not registered */N#define CTIU$K_NS_FC4_NOT_REG 7  /* 07: FC-4 Types not registered */U#define CTIU$K_NS_SYM_PORT_NAME_NOT_REG 8 /* 08: Symbolic port name not registered */U#define CTIU$K_NS_SYM_NODE_NAME_NOT_REG 9 /* 09: Symbolic node name not registered */N#define CTIU$K_NS_PORT_TYPE_NOT_REG 10 /* 0A: Port type not registered */T#define CTIU$K_NS_IP_ADDR_PORT_NOT_REG 11 /* 0B: IP address (port) not registered */T#define CTIU$K_NS_FAB_PORT_NAME_NOT_REG 12 /* 0C: Fabric port name not registered */N#define CTIU$K_NS_HARD_ADDR_NOT_REG 13 /* 0D: Hard address not registered */N#define CTIU$K_NS_RESERVED1 14 /* 0E: (reserved) */N#define CTIU$K_NS_RESERVED2 15 /* 0F: (reserved) */N#define CTIU$K_NS_ACCESS_DENIED 16 /* 10: Access denied */P#define CTIU$K_NS_UNACCEPTABLE_PORT_ID 17 /* 11: Unacceptable port identifier */N#define CTIU$K_NS_DATA_BASE_EMPTY 18 /* 12: Data base empty */Z#define CTIU$K_NS_NO_OBJ_REG_IN_SCOPE 19 /* 13: No object registered in specified scope */N#define CTIU$K_INVALID_COMMAND 1 /* 01: Invalid command code */N#define CTIU$K_INVALID_VERSION 2 /* 02: Invalid version level */N#define CTIU$K_LOGICAL_ERROR 3 /* 03: Logical error */N#define CTIU$K_INVALID_IU_SIZE 4 /* 04: Invalid IU size */N#define CTIU$K_LOGICAL_BUSY 5 /* 05: Logical busy */N#define CTIU$K_RESERVED5 6 /* 06: (reserved)  */N#define CTIU$K_PROTOCOL_ERROR 7 /* 07: Protocol error */N#define CTIU$K_RESERVED6 8 /* 08: (reserved) */N#define CTIU$K_CANT_DO_IT 9 /* 09: Unable to perform request */N#define CTIU$K_RESERVED7 10 /* 0A: (reserved) */N#define CTIU$K_NOT_SUPPORTED 11 /* 0B: Command not supported */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _ctiu {#pragma __nomember_alignment __struct {N/* Longword 0 */ char ctiu$b_in_id [3]; char ctiu$b_revision;N/* Longword 1 */ char ctiu$b_reserved; char ctiu$b_options; __union {# char ctiu$b_fs_s ubtype; __struct {. unsigned ctiu$v_reserved2 : 7;2 unsigned ctiu$v_xbit_exchange : 1;) } ctiu$r_fs_subtype_bits; } ctiu$r_fs_subtype; char ctiu$b_fcs_type;N/* - Service types - */1 unsigned short int ctiu$w_max_resid_size;T unsigned short int ctiu$w_command_response; /* - Command/Response codes - */" char ctiu$b_vendor_unique;$  char ctiu$b_rjt_explanation;N/* Reject explanation constants added with revision X-6 */N/* FS_RJT name server reason code explanations */ char ctiu$b_rjt_reason;N/* - FS_RJT reason codes - */ char ctiu$b_reserved4; } ctiu$r_ct_hdr; } CTIU; #if !defined(__VAXC)/#define ctiu$b_in_id ctiu$r_ct_hdr.ctiu$b_in_id5#define ctiu$b_revision ctiu$r_ct_hdr.ctiu$b_revisio n5#define ctiu$b_reserved ctiu$r_ct_hdr.ctiu$b_reserved3#define ctiu$b_options ctiu$r_ct_hdr.ctiu$b_options9#define ctiu$r_fs_subtype ctiu$r_ct_hdr.ctiu$r_fs_subtype=#define ctiu$b_fs_subtype ctiu$r_fs_subtype.ctiu$b_fs_subtypeG#define ctiu$r_fs_subtype_bits ctiu$r_fs_subtype.ctiu$r_fs_subtype_bits@#define ctiu$v_reserved2 ctiu$r_fs_subtype_bits.ctiu$v_reserved2H#define ctiu$v_xbit_exchange ctiu$r_fs_subtype_bits.ctiu$v_xbit_exchange5#define ctiu$b_fcs_type ctiu$r_ct_hdr.ctiu$b_fcs_type A#define ctiu$w_max_resid_size ctiu$r_ct_hdr.ctiu$w_max_resid_sizeE#define ctiu$w_command_response ctiu$r_ct_hdr.ctiu$w_command_response?#define ctiu$b_vendor_unique ctiu$r_ct_hdr.ctiu$b_vendor_uniqueC#define ctiu$b_rjt_explanation ctiu$r_ct_hdr.ctiu$b_rjt_explanation9#define ctiu$b_rjt_reason ctiu$r_ct_hdr.ctiu$b_rjt_reason7#define ctiu$b_reserved4 ctiu$r_ct_hdr.ctiu$b_reserved4"#endif /* #if !defined(__VAXC) */ N/*  */N/* Directory Service Subtypes */I/* FC-GS-2 R5.1, Table 7 */N/* */#define DIR$K_RESERVED1 1#define DIR$K_NAME_SERVICE 2N/* */I/* Name Server Request Command Codes */I/* FC-GS-2 R5.1, Table 10  */N/* */N#define NSREQ$K_GA_NXT 256 /* Get all next */N#define NSREQ$K_GPN_ID 274 /* Get port name */N#define NSREQ$K_GNN_ID 275 /* Get node name using port ID */N#define NSREQ$K_GCS_ID 276 /* Get class of service */N#define NSREQ$K_GFT_ID 279 /* Get FC-4 TYPEs */N#define NSREQ$K_GSPN_ID 280 /* Get symbolic port name */N#define NSREQ$K_GPT_ID 282 /* Get port type */N#define NSREQ$K_GID_PN 289 /* Get port ID using port name */N#define NSREQ$K_GID_NN 305 /* Get port ID using node name */N#define NSREQ$K_GIP_NN 309 /* Get IP address */R#define NSREQ$K_GIPA_NN 310 /* Get proc. associator using node name */N#define NSREQ$K_GSNN_NN 313 /* Get symbolic node name */N#define NSREQ$K_GNN_IP 339 /* Get node name using IP address */S#define NSREQ$K_GIPA_IP 342 /* Get proc. associator using IP address */N#define NSREQ$K_GID_FT 369 /* Get port IDs using FC-4 TYPE */N#define NSREQ$K_GID_PT 417 /* Get port IDs using port type */N#define NSREQ$K_RPN_ID 530 /* Register port name */N#define NSREQ$K_RNN_ID 531  /* Register node name */N#define NSREQ$K_RCS_ID 532 /* Register class of service */N#define NSREQ$K_RFT_ID 535 /* Register FC-4 TYPEs */N#define NSREQ$K_RSPN_ID 536 /* Register symbolic port name */N#define NSREQ$K_RPT_ID 538 /* Register port type */N#define NSREQ$K_RIP_NN 565 /* Register IP address */N#define NSREQ$K_RIPA_NN 566 /* Register proc. associ ator */N#define NSREQ$K_RSNN_NN 569 /* Register symbolic node name */N#define NSREQ$K_DA_ID 768 /* Deregister all */N/* */I/* GID_PN (Get port identifier for specified port) Request Payload */I/* FC-GS-2 R5.1 - Table 28 */N/* */ c#if !defined(_ _NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef union _gid_pn_req {#pragma __nomember_alignmentN char gid_pn_req$b_port_name [8]; /* X-9a */# __int64 gid_pn_req$q_port_name; } GID_PN_REQ; N/* */I/* GID_PN (Get port identifier for specified por t) Reply */I/* FC-GS-2 R5.1 - Table 29 */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef union _gid_pn_acc {#pragma __nomember_alignmentN unsigned int gid_pn_acc$l_port_ident; /* X-9a  */ __struct {$ char gid_pn_acc$b_reserved1;) char gid_pn_acc$b_port_ident [3]; } gid_pn_acc$r_rsvd0; } GID_PN_ACC; #if !defined(__VAXC)H#define gid_pn_acc$b_reserved1 gid_pn_acc$r_rsvd0.gid_pn_acc$b_reserved1J#define gid_pn_acc$b_port_ident gid_pn_acc$r_rsvd0.gid_pn_acc$b_port_ident"#endif /* #if !defined(__VAXC) */ N/* */I/* GID_NN (Get port identifiers for specified node) Request Payload */I/* FC-GS-2 R5.1 - Table 30 */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _gid_nn_req {#pragma __nomember_alignment$ char gid_nn_req$b_node_name [8]; } GID_NN_REQ;N/*  */I/* GID_NN (Get port identifiers for specified node) Reply */I/* FC-GS-2 R5.1 - Table 31 */N/* */$#define GID_NN_ACC$M_RESERVED 0x7F00&#define GID_NN_ACC$M_LAST_IDENT 0x8000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _gid_nn_acc {#pragma __nomember_alignment char gid_nn_acc$b_control;' unsigned gid_nn_acc$v_reserved : 7;) unsigned gid_nn_acc$v_last_ident : 1;% char gid_nn_acc$b_port_ident [3];# char gid_nn_acc$b_fill_17_ [3]; } GID_NN_ACC;N/* */K/* GID_FT (Get port identifiers for specified FC-4 type) Request Payload */I/*  FC-GS-2 R5.1 - Table 42 */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _gid_ft_req {#pragma __nomember_alignment( unsigned char gid_ft_req$b_fc4_type;N unsigned char gid_ft_req$b_area; /* X-9b  */N unsigned char gid_ft_req$b_domain; /* X-9b */( unsigned char gid_ft_req$b_reserved; } GID_FT_REQ;N/* */I/* GID_FT (Get port identifiers for specified FC-4 type) Reply */I/* FC-GS-2 R5.1 - Table 43 */N/* */"#define GID_FT_ACC$M_RESERVED 0x7F$#define GID_FT_ACC$M_LAST_IDENT 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _gid_ft_acc {#pragma __nomember_alignment% char gid_ft_acc$b_port_ident [3]; __struct {+ unsigned gid_ft_acc$v_reserved : 7;- unsigned gid_ft_acc$v_last_ident : 1;) } gid_ft_acc$r_control_structure; } GID_ FT_ACC; #if !defined(__VAXC)R#define gid_ft_acc$v_reserved gid_ft_acc$r_control_structure.gid_ft_acc$v_reservedV#define gid_ft_acc$v_last_ident gid_ft_acc$r_control_structure.gid_ft_acc$v_last_ident"#endif /* #if !defined(__VAXC) */ N/* */I/* GID_PT (Get Port Identifiers) Request Payload */I/* FC-GS-2 R5.1 - Table 44 */N/*  */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _gid_pt_req {#pragma __nomember_alignment char gid_pt_req$b_reserved;N char gid_pt_req$b_area_id_scope; /* X-6 */N char gid_pt_req$b_domain_id_scope; /* X-6 */ char gid_pt_req$b_port_type; } GID_PT_REQ;N/* */I/* GID_PT (Get Port Identifiers) Reply */I/* FC-GS-2 R5.1 - Table 45 */N/* */(#define GID_PT_ACC$M_PORT_IDENT 0xFFFFFF"#define GID_PT_ACC$M_RESERVED 0x7F$#define GID_PT_ACC$M_LAST_IDENT 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _gid_pt_acc {#pragma __nomember_alignment __struct {. unsigned gid_pt_acc$v_port_ident : 24; __struct {/ unsigned gid_pt_acc$v_reserved : 7;1 unsigned gid_pt_acc$v_last_ident : 1;- } gid_pt_acc$r_control_structure;* } gid_pt_acc$r_port_structure [1];  } GID_PT_ACC; #if !defined(__VAXC)7#define gid_pt_acc$v_port_ident gid_pt_acc$v_port_identE#define gid_pt_acc$r_control_structure gid_pt_acc$r_control_structureR#define gid_pt_acc$v_reserved gid_pt_acc$r_control_structure.gid_pt_acc$v_reservedV#define gid_pt_acc$v_last_ident gid_pt_acc$r_control_structure.gid_pt_acc$v_last_ident"#endif /* #if !defined(__VAXC) */ N/* */N/* GPN_ID - Get Port Name by (P ort) ID request */N/* FC-GS-4 5.2.5.4 Table 34 */N/* */%#define GPN_ID_REQ$M_PORT_ID 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _gpn_id_req {#pragma __nomember_alignment' unsi gned gpn_id_req$v_port_id : 24; char gpn_id_req$b_rsvd0; } GPN_ID_REQ;N/* */N/* GPN_ID - Get Port Name by (Port) ID response */N/* FC-GS-4 5.2.5.4 Table 35 */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _gpn_id_acc {#pragma __nomember_alignment- unsigned char gpn_id_acc$b_port_name [8]; } GPN_ID_ACC;%#define NS_GID_PT$K_PT_UNIDENTIFIED 0#define NS_GID_PT$K_PT_N_PORT 1 #define NS_GID_PT$K_PT_NL_PORT 2"#define NS_GID_PT$K_PT_F_NL_PORT 3"#define NS_GID_PT$K_PT_NX_PORT 127!#define NS_GID_PT$K_PT_F_PORT 129"#define NS_GID_PT$K_PT_FL_PORT 130!#define NS_GID_PT$K_PT_E_PORT 132 N/* */I/* Well-known addresses for Fibre Channel Services */I/* FC-FLA R2.7 - Table 28 */N/* */(#define WLKN_ADR$K_SYNCH_SERVER 16777206+#define WLKN_ADR$K_SECURITY_SERVER 16777207(#define WLKN_ADR$K_ALIAS_SERVER 16777208%#define WLKN_ADR$K_QOS_FACIL 16777209'#define WLKN_ADR$K_MGM T_SERVER 16777210'#define WLKN_ADR$K_TIME_SERVER 16777211,#define WLKN_ADR$K_DIRECTORY_SERVER 16777212(#define WLKN_ADR$K_FABRIC_CTRLR 16777213(#define WLKN_ADR$K_FABRIC_FPORT 16777214%#define WLKN_ADR$K_BROADCAST 16777215N/* */I/* RSCN (Registered State Change Notification) Payload */I/* FC-FLA R2.7 - Tables A.14-A.19 */N/*  */!#define RSCN_REQ$K_PORT_ADDRESS 0'#define RSCN_REQ$K_AREA_ADDRESS_GROUP 1)#define RSCN_REQ$K_DOMAIN_ADDRESS_GROUP 2N#define RSCN_REQ$K_FABRIC_ADDRESS_GROUP 3 /* X-6 */##define RSCN_REQ$M_ADDRESS 0xFFFFFF*#define RSCN_REQ$M_ADDRESS_FORMAT_BITS 0x3,#define RSCN_REQ$M_EVENT_QUALIFIER_BITS 0x3C%#define RSCN_REQ$M_RESERVED_BITS 0xC0 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rscn_req {N/* Longword 0 */#pragma __nomember_alignment( short int rscn_req$w_payload_length; char rscn_req$b_page_length;% char rscn_req$b_els_command_code;N/* Longword 1 */ __struct { __union {- unsigned rscn_req$v_addres s : 24; __struct {% char rscn_req$b_port;% char rscn_req$b_area;' char rscn_req$b_domain;/ } rscn_req$r_address_structure;' } rscn_req$r_address_union;N __union { /* X-14 */N __struct { /* X-14 */< unsigned rscn_req$v_address_format_bits : 2;= unsigned rscn_req$ v_event_qualifier_bits : 4;6 unsigned rscn_req$v_reserved_bits : 2;0 } rscn_req$r_addr_fmt_structure;+ char rscn_req$b_address_format;( } rscn_req$r_addr_fmt_union;' } rscn_req$r_affected_page [1]; } RSCN_REQ; #if !defined(__VAXC)9#define rscn_req$r_address_union rscn_req$r_address_unionF#define rscn_req$v_address rscn_req$r_address_union.rscn_req$v_addressZ#define rscn_req$r_address_structure rscn_req$r_address_union.rscn_req$r_address_structureD#define rscn_req$b_port rscn_req$r_address_structure.rscn_req$b_portD#define rscn_req$b_area rscn_req$r_address_structure.rscn_req$b_areaH#define rscn_req$b_domain rscn_req$r_address_structure.rscn_req$b_domain;#define rscn_req$r_addr_fmt_union rscn_req$r_addr_fmt_union]#define rscn_req$r_addr_fmt_structure rscn_req$r_addr_fmt_union.rscn_req$r_addr_fmt_structurec#define rscn_req$v_address_format_bits rscn_req$r_addr_fmt_structure.rscn_req$v_address_format_bitse#define rscn_req$v_event_qualifier_bits rscn_req$r_addr_fmt_structure.rscn_req$v_event_qualifier_bitsW#define rscn_req$v_reserved_bits rscn_req$r_addr_fmt_structure.rscn_req$v_reserved_bitsU#define rscn_req$b_address_format rscn_req$r_addr_fmt_union.rscn_req$b_address_format"#endif /* #if !defined(__VAXC) */ N/* */I/* RSCN (Registered State Change Notification) Accept Reply */I/* FC-FLA R2.7 - Table A.20  */N/* */%#define RSCN_ACC$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rscn_acc {#pragma __nomember_alignment __struct {+ unsigned rscn_acc$v_reserved1 : 24;2 unsigned char rscn _acc$b_els_command_code;) } rscn_acc$r_els_command_overlay; } RSCN_ACC; #if !defined(__VAXC)P#define rscn_acc$v_reserved1 rscn_acc$r_els_command_overlay.rscn_acc$v_reserved1^#define rscn_acc$b_els_command_code rscn_acc$r_els_command_overlay.rscn_acc$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/* */N/* Affected N_Port ID Page - Port Address Format */N/*  */#define IDPAGE$K_PORT_ADDRESS 0 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _portpg {#pragma __nomember_alignment char portpg$b_format; char portpg$b_port_id [3]; } PORTPG;N/* */N/* Affected N_Port ID Page - Area Address Format */N/* */#define IDPAGE$K_AREA_ADDRESS 1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _areapg {#pragma __nomember_alignment char areapg$b_format; char areapg$b_port_domain;  char areapg$b_port_area; char areapg$b_reserved1; } AREAPG;N/* */N/* Affected N_Port ID Page - Domain Address Format */N/* */#define IDPAGE$K_DOMN_ADDRESS 2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#p ragma __nomember_alignment#endiftypedef struct _domnpg {#pragma __nomember_alignment char domnpg$b_format; char domnpg$b_port_domain;! short int domnpg$w_reserved1; } DOMNPG;N/* */I/* FAN (Fabric Address Notification) Payload */I/* FC-FLA R2.7 - Table A.1 */N/*  */ #define FAN$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _fan {#pragma __nomember_alignment __struct {& unsigned fan$v_reserved1 : 24;- unsigned char fan$b_els_command_code;$ } fan$r_els_command_overlay; char fan$b_reserved1; char fan$b_fabric_adrs [3]; char  fan$b_port_name [8]; char fan$b_fabric_name [8]; } FAN; #if !defined(__VAXC)A#define fan$v_reserved1 fan$r_els_command_overlay.fan$v_reserved1O#define fan$b_els_command_code fan$r_els_command_overlay.fan$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/* */I/* SCR (State Change Request) Payload */I/* FC-FLA R2.7 - Tables A.21, A.22  */N/* */$#define SCR_REQ$M_RESERVED1 0xFFFFFF#define SCR_RF$K_RESERVED 0#define SCR_RF$K_FABRIC 1#define SCR_RF$K_N_PORT 2#define SCR_RF$K_FULL 3#define SCR_RF$K_CLEAR_REG 255 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _scr_req {#pragma __nomember_alignment __struct {* unsigned scr_req$v_reserved1 : 24;1 unsigned char scr_req$b_els_command_code;( } scr_req$r_els_command_overlay; char scr_req$b_reg_function;! char scr_req$b_reserved2 [3]; } SCR_REQ; #if !defined(__VAXC)M#define scr_req$v_reserved1 scr_req$r_els_command_overlay.scr_req$v_reserved1[#define scr_req$b_els_command_code scr_req$r_els_command_overlay.scr_req$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*  */I/* SCR (State Change Request) Accept Reply */I/* FC-FLA R2.7 - Table A.23 */N/* */$#define SCR_ACC$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _scr_acc {#pragma __nomember_alignment __struct {* unsigned scr_acc$v_reserved1 : 24;1 unsigned char scr_acc$b_els_command_code;( } scr_acc$r_els_command_overlay; } SCR_ACC; #if !defined(__VAXC)M#define scr_acc$v_reserved1 scr_acc$r_els_command_overlay.scr_acc$v_reserved1[#define scr_acc$b_els_command_code scr_acc$r_els_command_overlay.scr_acc$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*  */I/* ELP (Exchange Link Parameters) Payload */I/* FC-SW R3.3 - Table 6 */N/* */ #define ELP$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _elp {#pragma __nomember_alignment __struct {& unsigned elp$v_reserved1 : 24;- unsigned char elp$b_els_command_code;$ } elp$r_els_command_overlay; } ELP; #if !defined(__VAXC)A#define elp$v_reserved1 elp$r_els_command_overlay.elp$v_reserved1O#define elp$b_els_command_code elp$r_els_command_overlay.elp$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+  */N/* */J/* Fabric Login Request */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */I/* Page 148, table 71 */N/*  */N/*- */&#define FLOGI_REQ$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _flogi_req_t {#pragma __nomember_alignment __struct {, unsigned flogi_req$v_reserved1 : 2 4;3 unsigned char flogi_req$b_els_command_code;* } flogi_req$r_els_command_overlay;7 COMMON_SERVICE_PARAMETERS flogi_req$r_common_sparm;) IEEE_ADDRESS_T flogi_req$r_port_name;0 IEEE_ADDRESS_T flogi_req$r_node_fabric_name;1 SERVICE_PARAMETERS flogi_req$r_class_1_sparm;1 SERVICE_PARAMETERS flogi_req$r_class_2_sparm;1 SERVICE_PARAMETERS flogi_req$r_class_3_sparm;- unsigned char flogi_req$b_reserved2 [16];8 unsigned char flogi_req$b_vendor_version_lev el [16]; } FLOGI_REQ_T; #if !defined(__VAXC)S#define flogi_req$v_reserved1 flogi_req$r_els_command_overlay.flogi_req$v_reserved1a#define flogi_req$b_els_command_code flogi_req$r_els_command_overlay.flogi_req$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */J/* Fabric Login Response  */N/* */I/* Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 */I/* Working draft of 5-January-1996 */I/* Page 148, table 72 */N/* */N/*- */&#define FLOGI_RSP$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _flogi_rsp_t {#pragma __nomember_alignment __union {- int flogi_rsp$l_els_command_longword; __struct {0 unsigned flogi_rsp$v_reserved1 : 24;7 unsigned char flogi_rsp$b_els_command_code;. } flogi_rsp$r_els_command_over lay;( } flogi_rsp$r_els_command_union;7 COMMON_SERVICE_PARAMETERS flogi_rsp$r_common_sparm;) IEEE_ADDRESS_T flogi_rsp$r_port_name;0 IEEE_ADDRESS_T flogi_rsp$r_node_fabric_name;1 SERVICE_PARAMETERS flogi_rsp$r_class_1_sparm;1 SERVICE_PARAMETERS flogi_rsp$r_class_2_sparm;1 SERVICE_PARAMETERS flogi_rsp$r_class_3_sparm;- unsigned char flogi_rsp$b_reserved2 [16];8 unsigned char flogi_rsp$b_vendor_version_level [16]; } FLOGI_RSP_T; #if !defined(__VAXC)g#define flogi_rsp$l_els_command_longword flogi_rsp$r_els_command_union.flogi_rsp$l_els_command_longworde#define flogi_rsp$r_els_command_overlay flogi_rsp$r_els_command_union.flogi_rsp$r_els_command_overlayS#define flogi_rsp$v_reserved1 flogi_rsp$r_els_command_overlay.flogi_rsp$v_reserved1a#define flogi_rsp$b_els_command_code flogi_rsp$r_els_command_overlay.flogi_rsp$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+  */N/* */J/* Discover F-Port Parameters Request */N/* */K/* Ref: Fibre Channel Physical & Signaling Interface 2 (FC-PH-2) Rev 7.3 */I/* Working draft of 5-January-1996 */I/* Section 21.19.1 */N/*  */N/*- */&#define FDISC_REQ$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _fdisc_req_t {#pragma __nomember_alignment __struct {, unsigned fdisc_req$v_reserved1 : 24;3 unsign ed char fdisc_req$b_els_command_code;* } fdisc_req$r_els_command_overlay;7 COMMON_SERVICE_PARAMETERS fdisc_req$r_common_sparm;) IEEE_ADDRESS_T fdisc_req$r_port_name;0 IEEE_ADDRESS_T fdisc_req$r_node_fabric_name;1 SERVICE_PARAMETERS fdisc_req$r_class_1_sparm;1 SERVICE_PARAMETERS fdisc_req$r_class_2_sparm;1 SERVICE_PARAMETERS fdisc_req$r_class_3_sparm;- unsigned char fdisc_req$b_reserved2 [16];8 unsigned char fdisc_req$b_vendor_version_level [16]; } FD ISC_REQ_T; #if !defined(__VAXC)S#define fdisc_req$v_reserved1 fdisc_req$r_els_command_overlay.fdisc_req$v_reserved1a#define fdisc_req$b_els_command_code fdisc_req$r_els_command_overlay.fdisc_req$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */J/* Discover F-Port Parameters Response */N/*  */K/* Ref: Fibre Channel Physical & Signaling Interface 2 (FC-PH-2) Rev 7.3 */I/* Working draft of 5-January-1996 */I/* Section 21.19.1 */N/* */N/*- */&#define FDISC_RSP$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _fdisc_rsp_t {#pragma __nomember_alignment __struct {, unsigned fdisc_rsp$v_reserved1 : 24;3 unsigned char fdisc_rsp$b_els_command_code;* } fdisc_rsp$r_els_command_overlay;7 COMMON_SERVICE_PARAMETERS fdisc_rsp$r_common_sparm;) IEEE_ADDRESS_T fdisc_rsp$r_p ort_name;0 IEEE_ADDRESS_T fdisc_rsp$r_node_fabric_name;1 SERVICE_PARAMETERS fdisc_rsp$r_class_1_sparm;1 SERVICE_PARAMETERS fdisc_rsp$r_class_2_sparm;1 SERVICE_PARAMETERS fdisc_rsp$r_class_3_sparm;- unsigned char fdisc_rsp$b_reserved2 [16];8 unsigned char fdisc_rsp$b_vendor_version_level [16]; } FDISC_RSP_T; #if !defined(__VAXC)S#define fdisc_rsp$v_reserved1 fdisc_rsp$r_els_command_overlay.fdisc_rsp$v_reserved1a#define fdisc_rsp$b_els_command_code fdisc_rsp$r_e ls_command_overlay.fdisc_rsp$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/* */I/* ADISC (Discover Address) Payload */I/* FC-PH-2 R7.4 - Table 147 */N/* */&#define ADISC_REQ$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _adisc_req {#pragma __nomember_alignment __struct {, unsigned adisc_req$v_reserved1 : 24;3 unsigned char adisc_req$b_els_command_code;* } adisc_req$r_els_command_overlay; char adisc_req$b_reserved1;# char adisc_req$b_orig_adrs [3]; int adisc_req$l_orig_port; int adisc_req$l_orig_node; char adisc_req $b_reserved2;& char adisc_req$b_orig_port_id [3]; } ADISC_REQ; #if !defined(__VAXC)S#define adisc_req$v_reserved1 adisc_req$r_els_command_overlay.adisc_req$v_reserved1a#define adisc_req$b_els_command_code adisc_req$r_els_command_overlay.adisc_req$b_els_command_code"#endif /* #if !defined(__VAXC) */ N/* */I/* ADISC (Discover Address) Reply */I/* FC-PH-2 R7.4 - Table  148 */N/* */&#define ADISC_ACC$M_RESERVED1 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _adisc_acc {#pragma __nomember_alignment __struct {, unsigned adisc_acc$v_reserved1 : 24;3 unsigned  char adisc_acc$b_els_command_code;* } adisc_acc$r_els_command_overlay; char adisc_acc$b_reserved1;# char adisc_acc$b_resp_adrs [3]; int adisc_acc$l_resp_port; int adisc_acc$l_resp_node; char adisc_acc$b_reserved2;& char adisc_acc$b_resp_port_id [3]; } ADISC_ACC; #if !defined(__VAXC)S#define adisc_acc$v_reserved1 adisc_acc$r_els_command_overlay.adisc_acc$v_reserved1a#define adisc_acc$b_els_command_code adisc_acc$r_els_command_overlay.adisc_acc$b_els _command_code"#endif /* #if !defined(__VAXC) */ N/* */I/* RSPN_ID (Register Symbolic Port Name) Request Payload */I/* FC-GS-2 ANSI NCITS 288-1999 - Table 68 */N/* */I/* Note: This command has no command-specific objects in */I/* its accept payload.  */N/* */I/* Added with revision X-6 */N/* */)#define RSPN_ID_REQ$M_PORT_IDENT 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rs pn_id_req {#pragma __nomember_alignment+ unsigned rspn_id_req$v_port_ident : 24;$ char rspn_id_req$b_reserved [1];% char rspn_id_req$b_string_length;' char rspn_id_req$b_port_name [255]; } RSPN_ID_REQ;N/* */I/* FC4_ENTRY (List of FC4 entries returned by RNFT) */I/* Ref: Fibre Channel Framing and Signaling (FC-FS) REV 1.90 */I/* Draft proposal of 09-APR-2003  */I/* Table 194, page 303 */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _fc4_entry_t {#pragma __nomember_alignment# char fc4_entry$b_qualifier [3]; char fc4_entry$b_typ e; } FC4_ENTRY_T;N/* */I/* RNFT Request Payload */N/* */I/* Ref: Fibre Channel Framing and Signaling (FC-FS) REV 1.90 */I/* Draft proposal of 09-APR-2003 */I/* Table 192, page 302 */N/*  */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rnft_req {#pragma __nomember_alignmentV short int rnft_req$w_payload_length; /* Total length of payload (typically 20.) */N unsigned char rnft_req$b_reserved; /* Unused */Y unsigned char rnft_req$b_els_command_code; /* Extended Link service command code */N unsigned char rnft_req$b_index; /* First FC-4 Entry to be returned */! char rnft_req$b_fill_18_ [3]; } RNFT_REQ;N/* */I/* RNFT ACC Payload */N/* */I/* Ref: Fibre Channel Framing and Signaling (FC-FS) REV 1.90  */I/* Draft proposal of 09-APR-2003 */I/* Table 193, page 303 */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rnft_acc {#pragma __nomember_alignmentV short int rnft_acc$w_payload_length; /* Total length of payload (typically 20.) */N unsigned char rnft_acc$b_reserved; /* reserved */Y unsigned char rnft_acc$b_els_command_code; /* Extended Link service command code */N FC4_ENTRY_T rnft_acc$r_fc4_entry [255]; /* List of FC4 protocols */ } RNFT_ACC;N/*+ */N/* X-7 Define topology constants */N/* - */N/* Tell whether a switch is present (1) or not (0) */#define FC$M_TOPOLOGY_FABRIC 1N/* Tell whether the topology is Arbitrated Loop (1) or not (0) */#define FC$M_TOPOLOGY_FC_AL 2N/* There are 2 bits in the topology mask */#define FC$V_TOPOLOGY 0#define FC$S_TOPOLOGY 2#define FC$M_TOPOLOGY 3N/* Each topology gets it's own constant based on the bits defined above */#define FC$C_TOPOLOGY_P2P 0#define FC$C_TOPOLOGY_FABRIC 1$#define FC$C_TOPOLOGY_PRIVATE_LOOP 2##define FC$C_TOPOLOGY_PUBLIC_LOOP 3N/* */I/* RFT_ID (Register FC-4 Types) Request Payload */I/* FC-GS-4 Rev 7.6 19-Dec-02 - Table 98 */N/* */I/* 1) Start with a zero'd 8-LW (32-byte) map */I/* 2) Each legal FC-4 type value fits into 8 bits: */I/* LW = high 3 bits (0 to 7) of FC-4 type value */I/* bit# = low 5 bits (0 to 31) of FC-4 type value */I/* 3) Using C notation, for each supported FC-4 type: */I/* map [LW] |= (1 << bit#) */I/* */I/* See Table 25 for a formal description of the FC-4 Types map format */N/* */ (#define RFT_ID_REQ$M_PORT_IDENT 0xFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rft_id_req {#pragma __nomember_alignment* unsigned rft_id_req$v_port_ident : 24;#  char rft_id_req$b_reserved [1]; __union {0 unsigned int rft_id_req$l_fc4_types [8];2 unsigned char rft_id_req$b_fc4_types [32];' } rft_id_req$r_fc4_types_union; } RFT_ID_REQ; #if !defined(__VAXC)R#define rft_id_req$l_fc4_types rft_id_req$r_fc4_types_union.rft_id_req$l_fc4_typesR#define rft_id_req$b_fc4_types rft_id_req$r_fc4_types_union.rft_id_req$b_fc4_types"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FCPHDEF_LOADED */ ww([UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************* *************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:18 by OpenVMS SDL V3.7 */J/* Source: 22-SEP-2016 16:18:08 $1$DGA8345:[LIB_H.SRC]FCP_QIODEF.SDL;1 *//********************************************************************************************************************************/&/*** MODULE $FCP_QIODEF IDENT X-5 ***/#ifndef __FCP_QIODEF_LOADED#define __FCP_QIODEF_LOADED 1 G#pragma __nostan dard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #ifndef _FCP_QIODEF_LOADED#define _FCP_QIODEF_LOADED N/* IO$ACCESS command codes for FibreChannel drivers */N/* Maximum number of filter parame ters allowed */N/* (maximum value of the counts defined below) */N/* Make SDL-local constant public */##define FC$K_EV_FLTR_MAXIMUM_CNT 32N/* Maximum number of FCP status filter bytes */##define FC$K_EV_FLTR_FCP_STAT_CNT 8N/* Maximum number of extended status filter bytes */ #define FC$K_EV_FLTR_ESTAT_CNT 8N/* Maximum number of SCSI comm !and filter bytes */$#define FC$K_EV_FLTR_SCSI_COMM_CNT 8N/* Maximum number of ASC filter bytes */#define FC$K_EV_FLTR_ASC_CNT 8N/* Maximum number of WWID filter bytes */ #define FC$K_EV_FLTR_WWID_CNT 32N/* */N/* QIO Function Codes */N/* " */#define FC$C_QIO_QFULL 0#define FC$C_QIO_FC_LA_DATA 1#define FC$C_QIO_FLTR_WRITE 2#define FC$C_QIO_FLTR_READ 3 #define FC$C_QIO_FCP_RING_SIZE 4#define FC$C_QIO_SET_WTID 5#define FC$C_QIO_IC 6#define FC$C_QIO_RING_SIZE 7%#define FC$C_QIO_FASTPATH_RING_SIZE 8!#define FC$C_QIO_SLOW_RING_SIZE 9##define FC$C_QIO_ERROR_RING_SIZE 10(#define FC$C_QIO_INTERRUPTS_RING_SIZE 11!#define FC$C_QIO_MBX_RING_SIZE 12"#define FC$C_QIO_IOCB_RING_S #IZE 13#define FC$C_QIO_PM_CLEAR 14#define FC$C_QIO_PM_READ_ALL 15#define FC$C_QIO_PM_RSCC 16#define FC$C_QIO_PM_SYSTIME 17!#define FC$C_QIO_SET_ERL_ENTRY 18$#define FC$C_QIO_PM_READ_COUNTERS 19 #define FC$C_QIO_SNIA_REQUEST 20N#define FC$C_QIO_NS_GID_PT 21 /* Get Port IDs using the port type */N#define FC$C_QIO_NS_GPN_ID 22 /* Get Port Name */N#define FC$C_QIO_NS_GSPN_ID 23 /* Get Symbolic Port Name */N#define FC$C_QIO_PM_ALLO$C 24 /* X-8a Allocate performance data */N#define FC$C_QIO_PM_DEALLOC 26 /* X-8a Deallocate performance data */N#define FC$C_QIO_GET_WWIDS 27 /* X-9a Select WWIDs by wildcard */N#define FC$C_QIO_GET_WTID 28 /* X-9a Read a WWID_TID structure */[#define FC$C_QIO_SET_WTIDS 29 /* X-9a Modify selected WWID_TID characteristics */X#define FC$C_QIO_PEEK 30 /* X-11 Read driver-accessible address spaces */%#define FC$C_QIO_SUB_FLTR_%SCSI_COMM 0&#define FC$C_QIO_SUB_FLTR_FCP_STATUS 1##define FC$C_QIO_SUB_FLTR_ESTATUS 2#define FC$C_QIO_SUB_FLTR_ASC 3 #define FC$C_QIO_SUB_FLTR_WWID 4!#define FC$C_QIO_SUB_FLTR_MATCH 5 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _qfull {#pragma __nomember_alignmentN __int64 qfull$q_command_code; /* FC$C_QFULL & */S __int64 qfull$q_qw_count; /* QW parameters (not counting this one) */N __int64 qfull$q_fc_la; /* FibreChannel Logical Address */Q __int64 qfull$q_step_divisor; /* Step size based on Queue Full depth */N __int64 qfull$q_drain_multiplier; /* Drain count based on step size */X __int64 qfull$q_probation_factor; /* Probation period based on Queue Full depth */ } QFULL; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined '(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fc_la_data {#pragma __nomember_alignmentN __int64 fc_la_data$q_command_code; /* FC$C_FC_LA_DATA */S __int64 fc_la_data$q_qw_count; /* QW parameters (not counting this one) */N __int64 fc_la_data$q_fc_la; /* FibreChannel Logical Address */N __int64 fc_la_data$q_fc_address; /* Current FibreCh (annel address */N __int64 fc_la_data$q_port_name; /* FC-LA's port name */N __int64 fc_la_data$q_node_name; /* FC-LA's node name */N __int64 fc_la_data$q_state; /* FC-LA's state as ELS code */ } FC_LA_DATA;#define FC$C_NO_APPEND 0#define FC$C_APPEND 1#define FC$C_OR 0#define FC$C_AND 1#define FC$C_NOR 2#define FC$C_NO_CHANGE 3 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC ) V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif#typedef struct _filter_data_write {#pragma __nomember_alignmentN __int64 filter_data_write$q_command_code; /* FC$C_QIO_FLTR_WRITE */U __int64 filter_data_write$q_qw_count; /* QW parameters (not counting this one) */R __int64 filter_data_write$q_sub_command; /* Sub-command FC$C_QIO_SUB_FLTR_* */N __int64 filter_data_write$q_append; /* Append flag (0=no, 1=yes) */S * __int64 filter_data_write$q_match; /* Match flag (0=or, 1=and, 2=no change) */* __int64 filter_data_write$q_data [32];N/* Data for specified filter function */ } FILTER_DATA_WRITE; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif"typedef struct _filter_data_read {#pragma __nomember_alignmentN __int6 +4 filter_data_read$q_command_code; /* FC$C_QIO_FLTR_READ */T __int64 filter_data_read$q_qw_count; /* QW parameters (not counting this one) */Q __int64 filter_data_read$q_sub_command; /* Sub-command FC$C_QIO_SUB_FLTR_* */ } FILTER_DATA_READ; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif!typedef struct _filter_data_rsp {#pragma __ ,nomember_alignmentS __int64 filter_data_rsp$q_qw_count; /* QW parameters (not counting this one) */( __int64 filter_data_rsp$q_data [32];N/* Data for specified filter function */ } FILTER_DATA_RSP;&#define FLTR_IOSB$M_ALREADY_EXISTS 0x1'#define FLTR_IOSB$M_TOO_MANY_VALUES 0x2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomemb-er_alignment#endiftypedef struct _fltr_iosb {#pragma __nomember_alignment* unsigned short int fltr_iosb$w_status;$ short int fltr_iosb$w_reserved0;$ short int fltr_iosb$w_reserved1;N/* Error word */ __union {2 unsigned short int fltr_iosb$w_error_word; __struct {4 unsigned fltr_iosb$v_already_exists : 1;5 unsigned fltr_iosb$v_too_many_values : 1;0 unsigned flt .r_iosb$v_reserved0 : 14;* } fltr_iosb$r_error_word_bits;) } fltr_iosb$r_error_word_overlay; } FLTR_IOSB; #if !defined(__VAXC)T#define fltr_iosb$w_error_word fltr_iosb$r_error_word_overlay.fltr_iosb$w_error_wordx#define fltr_iosb$v_already_exists fltr_iosb$r_error_word_overlay.fltr_iosb$r_error_word_bits.fltr_iosb$v_already_existsz#define fltr_iosb$v_too_many_values fltr_iosb$r_error_word_overlay.fltr_iosb$r_error_word_bits.fltr_iosb$v_too_many_values"#endif /* #if ! /defined(__VAXC) */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _ring_size_data {#pragma __nomember_alignmentN __int64 ring_size_data$q_command_code; /* FC$C_QIO_RING_SIZE */S __int64 ring_size_data$q_qw_count; /* QW parameters (not counting this one) */N __int64 ring_size_data$q_ring_size; /* Number of ring 0entries requested */ } RING_SIZE_DATA; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ic {#pragma __nomember_alignmentN __int64 ic$q_command_code; /* FC$C_QIO_IC */S __int64 ic$q_qw_count; /* QW parameters (not counting this one) */ __int64 ic$q_rsp_int; __int64 ic$q_del 1ay_ms; __int64 ic$q_rsp_cnt; } IC;#define FC$C_MAX_QFULL_WAIT 1N/* Minimum allowed user-specified IO cap */#define FC$C_USER_IO_CAP_MIN 8N/* Minimum allowed user-specified IO cap */"#define FC$C_USER_IO_CAP_MAX 65535N/* Queue Full processing types */#define FC$C_QFULL_LOAD 0#define FC$C_QFULL_TIMED 1N/* Default Queue Full delay time (for Timed processing) 2 */&#define FC$C_QFULL_TIMED_DELAY_DEF 500N/* Minimum Queue Full delay time (for Timed processing) */$#define FC$C_QFULL_TIMED_DELAY_MIN 1N/* Maximum Queue Full delay time (for Timed processing) */'#define FC$C_QFULL_TIMED_DELAY_MAX 6000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct3 _set_wtid {#pragma __nomember_alignmentN __int64 set_wtid$q_command_code; /* FC$C_QIO_SET_WTID */U __int64 set_wtid$q_byte_count; /* Number of bytes following this quadword */N __int64 set_wtid$q_io_cap; /* IO cap value */P __int64 set_wtid$q_qfull_wait; /* Initiate cap after queue full seen */N __int64 set_wtid$q_qfull_type; /* Queue-full processing type */_ __int64 set_wtid$q_qfull_time; /* Queue-ful 4l delay time (for time-based processing) */N __int64 set_wtid$q_wwid; /* WWID */ } SET_WTID; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _set_erl_entry {#pragma __nomember_alignmentN __int64 set_erl_entry$q_command_code; /* FC$C_SET_ERL_ENTRY */S __int64 set_erl_entr 5y$q_qw_count; /* QW parameters (not counting this one) */] unsigned __int64 set_erl_entry$q_entry_count; /* Number of error log entries requested */ } SET_ERL_ENTRY; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pm_qio {#pragma __nomember_alignmentN __int64 pm_qio$q_command_code; /* FC$C_PM_* commands 6*/N __int64 pm_qio$q_device_class; /* X-7 DC$_TAPE, DC$_DISK, etc. */S __int64 pm_qio$q_device_id; /* X-7 Unit number, or 0 for all devices */ } PM_QIO; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pm_counters {#pragma __nomember_alignmentN unsigned __int64 pm_counters$q_read_time_acc; /* Accumulated7 read time */O unsigned __int64 pm_counters$q_write_time_acc; /* Accumulated write time */N unsigned int pm_counters$l_reads; /* Number of reads */N unsigned int pm_counters$l_writes; /* Number of writes */S unsigned int pm_counters$l_blocks_read; /* Accumulated number of blocks read */Y unsigned int pm_counters$l_blocks_written; /* Accumulated number of blocks written */ } PM_COUNTERS;N/* Nameserver Support 8 */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ns_qio {#pragma __nomember_alignmentN __int64 ns_qio$q_command_code; /* FC$C_NS_* commands */N __int64 ns_qio$q_port; /* Port ID */ } NS_QIO;N/* SNIA support 9 */$#define FC$C_QIO_SUB_SNIA_ADP_ATTR 0%#define FC$C_QIO_SUB_SNIA_PORT_ATTR 1$#define FC$C_QIO_SUB_SNIA_PORTSTAT 2(#define FC$C_QIO_SUB_SNIA_DISCPORTATTR 3$#define FC$C_QIO_SUB_SNIA_RNIDMGMT 4(#define FC$C_QIO_SUB_SNIA_DISCWWPNATTR 5##define FC$C_QIO_SUB_SNIA_FCPSTAT 6N/* Put this header on a specific SNIA structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nome :mber_alignment __quadword#else#pragma __nomember_alignment#endif%typedef struct _snia_request_header {#pragma __nomember_alignmentN __int64 snia_rq_hdr$q_command_code; /* FGE$C_QIO_SNIA_REQUEST */S __int64 snia_rq_hdr$q_qw_count; /* QW parameters (not counting this one) */N __int64 snia_rq_hdr$q_sub_command; /* Specific SNIA command */T __int64 snia_rq_hdr$q_port_id; /* Specific PORT identifier WWID or index */N __int64 snia_rq_hdr$q_data ;; /* Parameter for command */ } SNIA_REQUEST_HEADER;#define SNIA$K_MAX_CDB_SIZE 12 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _path_cdb {#pragma __nomember_alignmentN __int64 snia_path$q_lun; /* LUN */N int snia_path$is_target; /* Target FC_LA < */N unsigned int snia_path$l_length; /* True length of CDB. */N unsigned char snia_path$b_cdb [12]; /* CDB bytes */! char snia_path$b_fill_0_ [4]; } PATH_CDB;G /* X-10 */N/* */N/* X-9b Set characteristics for a potentially wildcarded WWID */N/* = */S#define SET_WTIDS$M_NODE 1 /* Constant for use outside of structure */#define SET_WTIDS$M_NODE 0x1S#define SET_WTIDS$M_OR 2 /* Constant for use outside of structure */#define SET_WTIDS$M_OR 0x2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _set_wtids {#pragma __nome>mber_alignmentN __int64 set_wtids$q_command_code; /* FC$C_QIO_SET_WTID */U __int64 set_wtids$q_byte_count; /* Number of bytes following this quadword */n __int64 set_wtids$q_wwid; /* WWID - port WWID by default, node WWID if SET_WTID$V_NODE is set */U __int64 set_wtids$q_match; /* Wildcarded nibbles are 0'd in this mask */N char set_wtids$b_product_id [16]; /* ASCIZ product ID string to match */ __union {N unsigned __int64 s ?et_wtids$q_flags; /* Control flags */ __struct {P unsigned set_wtids$v_node : 1; /* WWID is a node WWID (else port) */Y unsigned set_wtids$v_or : 1; /* Match either WWID or Product ID (else AND) */- unsigned set_wtids$v_fill_3_ : 6;" } set_wtids$r_fill_2_; } set_wtids$r_fill_1_;N/* End control flags */N __int64 set_wtids$q_io_cap; /* IO cap value @ */P __int64 set_wtids$q_qfull_wait; /* Initiate cap after queue full seen */N __int64 set_wtids$q_qfull_type; /* Queue-full processing type */_ __int64 set_wtids$q_qfull_time; /* Queue-full delay time (for time-based processing) */ } SET_WTIDS; #if !defined(__VAXC)?#define set_wtids$q_flags set_wtids$r_fill_1_.set_wtids$q_flagsQ#define set_wtids$v_node set_wtids$r_fill_1_.set_wtids$r_fill_2_.set_wtids$v_nodeM#define set_wtids$v_or set_wtids A$r_fill_1_.set_wtids$r_fill_2_.set_wtids$v_or"#endif /* #if !defined(__VAXC) */ N/* */W/* X-9c Get the port WWIDs selected by a wildcarded WWID and/or a partial product ID */N/* */S#define GET_WWIDS$M_NODE 1 /* Constant for use outside of structure */#define GET_WWIDS$M_NODE 0x1S#define GET_WWIDS$M_OR 2 /* Constant Bfor use outside of structure */#define GET_WWIDS$M_OR 0x2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _get_wwids {#pragma __nomember_alignmentN __int64 get_wwids$q_command_code; /* FC$C_QIO_GET_WWID */U __int64 get_wwids$q_byte_count; /* Number of bytes following this quadword */ __union {N C unsigned __int64 get_wwids$q_flags; /* Control flags */ __struct {P unsigned get_wwids$v_node : 1; /* WWID is a node WWID (else port) */Y unsigned get_wwids$v_or : 1; /* Match either WWID or Product ID (else AND) */- unsigned get_wwids$v_fill_6_ : 6;" } get_wwids$r_fill_5_; } get_wwids$r_fill_4_;N/* End control flags */N __int64 get_wwids$q_wwid; D/* Base WWID to match */N char get_wwids$b_product_id [16]; /* ASCIZ product ID string to match */U __int64 get_wwids$q_match; /* Wildcarded nibbles are 0'd in this mask */ } GET_WWIDS; #if !defined(__VAXC)?#define get_wwids$q_flags get_wwids$r_fill_4_.get_wwids$q_flagsQ#define get_wwids$v_node get_wwids$r_fill_4_.get_wwids$r_fill_5_.get_wwids$v_nodeM#define get_wwids$v_or get_wwids$r_fill_4_.get_wwids$r_fill_5_.get_wwids$v_or"#endif /* #if !defined( E__VAXC) */ N/* */N/* X-9d Structure returned by a successful FC$C_QIO_GET_WWID */N/* */S#define WWIDS$M_NODE 1 /* Constant for use outside of structure */#define WWIDS$M_NODE 0x1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __q Fuadword#else#pragma __nomember_alignment#endiftypedef struct _wwids {#pragma __nomember_alignmentN __int64 wwids$q_matched; /* Number of WWIDs which matched */N __int64 wwids$q_count; /* Number of WWIDs which follow */ __union {N unsigned __int64 wwids$q_flags; /* Control flags */ __struct {N unsigned wwids$v_node : 1; /* WWIDs are node WWIDs (else port) */) unsigned wwids$v_fill_9_ G : 7; } wwids$r_fill_8_; } wwids$r_fill_7_;N/* End control flags */U __int64 wwids$q_wwids [1]; /* Port or node WWIDS (keep as last field) */ } WWIDS; #if !defined(__VAXC)3#define wwids$q_flags wwids$r_fill_7_.wwids$q_flagsA#define wwids$v_node wwids$r_fill_7_.wwids$r_fill_8_.wwids$v_node"#endif /* #if !defined(__VAXC) */ N/* H */N/* X-9e Return the WWID_TID selected by the specified port WWID */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _get_wtid {#pragma __nomember_alignmentN __int64 get_wtid$q_command_code; /* FC$C_QIO_GET_WTID */U I __int64 get_wtid$q_byte_count; /* Number of bytes following this quadword */N __int64 get_wtid$q_wwid; /* Port WWID */ } GET_WTID;N#define PEEK$M_PCI 1 /* Read PCI CSRs */#define PEEK$M_PCI 0x1N#define PEEK$M_FLASH 2 /* Read flash memory */#define PEEK$M_FLASH 0x2N#define PEEK$M_CSR 4 /* Read controller CSRs */#define PEEK$M_CSR 0x4S#define JPEEK$M_MQIO 8 /* Read controller Multi-Queue I/O space */#define PEEK$M_MQIO 0x8N#define PEEK$M_MSIX 16 /* Read controller MSI-X space */#define PEEK$M_MSIX 0x10 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _peek {#pragma __nomember_alignmentN unsigned __int64 peek$q_command_code; /* FC$KC_QIO_PEEK */ __union {& unsigned __int64 peek$q_flags; __struct {$ unsigned peek$v_pci : 1;& unsigned peek$v_flash : 1;$ unsigned peek$v_csr : 1;% unsigned peek$v_mqio : 1;% unsigned peek$v_msix : 1;) unsigned peek$v_fill_12_ : 3; } peek$r_fill_11_; } peek$r_fill_10_;N __union { /* Offset of starting DWORD */O unsigned L __int64 peek$q_offset; /* For flash, this is a DWORD index, */N unsigned int peek$l_offset; /* but for CSRs it is a byte offset */ } peek$r_offset_overlay;N __union { /* Number of DWORDs to read */, unsigned __int64 peek$q_dword_count;( unsigned int peek$l_dword_count;% } peek$r_dword_count_overlay;V __union { /* Starting location - for flash reads this */X unsigned __int64 peek$ Mq_location; /* allows the caller to calculate the base */X unsigned int peek$l_location; /* of flash memory (subtract starting OFFSET) */" } peek$r_location_overlay;R unsigned int peek$l_dwords [1]; /* Returned DWORDs - leave as the last */N/* field so the structure can be */N/* extended when allocated */ char peek$b_fill_13_ [4]; } PEEK; #if !defined(__VAXC)1#def Nine peek$q_flags peek$r_fill_10_.peek$q_flags=#define peek$v_pci peek$r_fill_10_.peek$r_fill_11_.peek$v_pciA#define peek$v_flash peek$r_fill_10_.peek$r_fill_11_.peek$v_flash=#define peek$v_csr peek$r_fill_10_.peek$r_fill_11_.peek$v_csr?#define peek$v_mqio peek$r_fill_10_.peek$r_fill_11_.peek$v_mqio?#define peek$v_msix peek$r_fill_10_.peek$r_fill_11_.peek$v_msix9#define peek$q_offset peek$r_offset_overlay.peek$q_offset9#define peek$l_offset peek$r_offset_overlay.peek$l_offsetH#define pe Oek$q_dword_count peek$r_dword_count_overlay.peek$q_dword_countH#define peek$l_dword_count peek$r_dword_count_overlay.peek$l_dword_count?#define peek$q_location peek$r_location_overlay.peek$q_location?#define peek$l_location peek$r_location_overlay.peek$l_location"#endif /* #if !defined(__VAXC) */ N/* X-10 */  #endif $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr sPize pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FCP_QIODEF_LOADED */ ww;)[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensQed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed byR VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************* S*******************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */F/* Source: 02-APR-2003 13:35:28 $1$DGA8345:[LIB_H.SRC]FDTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FDTDEF ***/#ifndef __FDTDEF_LOADED#define __FDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __Tmember_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...U#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* FDT - FUNCTION DECISION TABLE FOR STEP 2 I/O DEVICE DRIVERS */N/* */N/* V EACH I/O DEVICE DRIVER HAS A FUNCTION DECISION TABLE. */N/*- */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fdt {#pragma __nomember_alignment\ __int64 fdt$q_buffered; /* 64 bit map set for buffered I/O function codes */R W int (*fdt$ps_func_rtn [64])(); /* Pointers to upper level FDT routines */h __int64 fdt$q_ok64bit; /* Corresponding bit set if function supports 64-bit $QIO P1 */ } FDT;N#define FDT$K_LENGTH 272 /* Length constant */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */X#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FDTDEF_LOADED */ wwp*[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyoneY without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** thZe prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 * [/N/* Source: 15-FEB-1995 10:44:18 $1$DGA8345:[LIB_H.SRC]FDT_CONTEXTDEF.SDL;1 *//********************************************************************************************************************************/ /*** MODULE $FDT_CONTEXTDEF ***/#ifndef __FDT_CONTEXTDEF_LOADED!#define __FDT_CONTEXTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Define\d whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __st]ruct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* FDT_CONTEXT - FUNCTION DECISION TABLE CONTEXT STRUCTURE FOR STEP 2 I/O */N/* DEVICE DRIVERS */N/* */N/* EACH $QIO INVOCAT ^ION HAS A FUNCTION DECISION TABLE CONTEXT STRUCTURE */N/* THAT IS ALLOCATED ON THE STACK. */N/*- */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fdt_context {#pragma __nomember_alignmentU __int64 fdt_context$q__qio_r1_value; /* VA of faulting page if SS$QIO_CROCK set */N unsigned short int fdt_context$w_size; /* FDT_CONTEXT$K_LENGTH */N unsigned char fdt_context$b_type; /* DYN$C_MISC */N unsigned char fdt_context$b_subtype; /* DYN$C_FDT_CONTEXT */Q unsigned int fdt_context$l_qio_status; /* Final $QIO system service status */N/* Pad size to quadword multiple so */N/* EXE$QIO stack is QW aligned. This ` */N/* structure is the first to be */N/* allocated on the $QIO stack. */ } FDT_CONTEXT;#define FDT_CONTEXT$K_LENGTH 16 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus a }#endif#pragma __standard $#endif /* __FDT_CONTEXTDEF_LOADED */ ww^+[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/bM/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written pecrmission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14 d-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FH1DEF ***/#ifndef __FH1DEF_LOADED#define __FH1DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma e__required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef f__union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define FH1$C_LEVEL1 257 /* 401 octal = structure level 1 */N#define FH1$K_LENGTH 46 /* length of header area */N#define FH1$C_LENGTH 46 /* length of header area */N#define FH1$S_FH1DEF 512 /* Old size name - synonym */ typedef struct _fh1 {N unsigned char fh1$b_idoffset; /* g ident area offset in words */N unsigned char fh1$b_mpoffset; /* map area offset in words */ __union {N unsigned short int fh1$w_fid [2]; /* file ID */ __struct {N unsigned short int fh1$w_fid_num; /* file number */N unsigned short int fh1$w_fid_seq; /* file sequence number */ } fh1$r_fid_fields; } fh1$r_fid_overlay;N unsigned short int fh1$w_struclev; /* fil he structure level */ __union {N unsigned short int fh1$w_fileowner; /* file owner UIC */ __struct {N unsigned char fh1$b_uicmember; /* UIC member number */N unsigned char fh1$b_uicgroup; /* UIC group number */% } fh1$r_fileowner_fields;" } fh1$r_fileowner_overlay; __union {N unsigned short int fh1$w_fileprot; /* file protection */ __struct {N i unsigned fh1$v_syspro : 4; /* system protection */N unsigned fh1$v_ownpro : 4; /* owner protection */N unsigned fh1$v_grouppro : 4; /* group protection */N unsigned fh1$v_worldpro : 4; /* world protection */" } fh1$r_fileprot_bits;! } fh1$r_fileprot_overlay; __union {N unsigned short int fh1$w_filechar; /* file characteristics */ __struct j{ __union {T unsigned char fh1$b_userchar; /* user controlled characteristics */ __struct {[ unsigned fh1$v_wascontig : 1; /* file was (and should be) contiguous */S unsigned fh1$v_nobackup : 1; /* file is not to be backed up */N unsigned fh1$$_fill_2 : 1; /* reserved */S unsigned fh1$v_readcheck : 1; /* verify all read operations */T k unsigned fh1$v_writcheck : 1; /* verify all write operations */Z unsigned fh1$v_contigb : 1; /* keep file as contiguous as possible */N unsigned fh1$v_locked : 1; /* file is deaccess locked */N unsigned fh1$v_contig : 1; /* file is contiguous */* } fh1$r_userchar_bits;) } fh1$r_userchar_overlay; __union {U unsigned char fh1$b_syschar; /* system controlled charac lteristics */ __struct {N unsigned fh1$$_fill_3 : 4; /* reserved */N unsigned fh1$v_spool : 1; /* intermediate spool file */N unsigned fh1$$_fill_4 : 1; /* reserved */P unsigned fh1$v_badblock : 1; /* file contains bad blocks */P unsigned fh1$v_markdel : 1; /* file is marked for delete */) } fh1$r_syschar_bits;( m } fh1$r_syschar_overlay;$ } fh1$r_filechar_fields;! } fh1$r_filechar_overlay;N unsigned short int fh1$w_recattr [16]; /* file record attributes */N short int fh1$$_fill_5 [232]; /* rest of file header */N unsigned short int fh1$w_checksum; /* file header checksum */ } FH1; #if !defined(__VAXC)-#define fh1$w_fid fh1$r_fid_overlay.fh1$w_fidF#define fh1$w_fid_num fh1$r_fid_overlay.fh1$r_fid_fields.fh1$w_fid_numF#defnine fh1$w_fid_seq fh1$r_fid_overlay.fh1$r_fid_fields.fh1$w_fid_seq?#define fh1$w_fileowner fh1$r_fileowner_overlay.fh1$w_fileownerV#define fh1$b_uicmember fh1$r_fileowner_overlay.fh1$r_fileowner_fields.fh1$b_uicmemberT#define fh1$b_uicgroup fh1$r_fileowner_overlay.fh1$r_fileowner_fields.fh1$b_uicgroup<#define fh1$w_fileprot fh1$r_fileprot_overlay.fh1$w_fileprotL#define fh1$v_syspro fh1$r_fileprot_overlay.fh1$r_fileprot_bits.fh1$v_sysproL#define fh1$v_ownpro fh1$r_fileprot_overlay.fh1$r_fileproto_bits.fh1$v_ownproP#define fh1$v_grouppro fh1$r_fileprot_overlay.fh1$r_fileprot_bits.fh1$v_groupproP#define fh1$v_worldpro fh1$r_fileprot_overlay.fh1$r_fileprot_bits.fh1$v_worldpro<#define fh1$w_filechar fh1$r_filechar_overlay.fh1$w_filechari#define fh1$b_userchar fh1$r_filechar_overlay.fh1$r_filechar_fields.fh1$r_userchar_overlay.fh1$b_userchar#define fh1$v_wascontig fh1$r_filechar_overlay.fh1$r_filechar_fields.fh1$r_userchar_overlay.fh1$r_userchar_bits.fh1$v_wascontig}#define fh1$v_nobackupp fh1$r_filechar_overlay.fh1$r_filechar_fields.fh1$r_userchar_overlay.fh1$r_userchar_bits.fh1$v_nobackup#define fh1$v_readcheck fh1$r_filechar_overlay.fh1$r_filechar_fields.fh1$r_userchar_overlay.fh1$r_userchar_bits.fh1$v_readcheck#define fh1$v_writcheck fh1$r_filechar_overlay.fh1$r_filechar_fields.fh1$r_userchar_overlay.fh1$r_userchar_bits.fh1$v_writcheck{#define fh1$v_contigb fh1$r_filechar_overlay.fh1$r_filechar_fields.fh1$r_userchar_overlay.fh1$r_userchar_bits.fh1$v_contigby#define fh1$v_qlocked fh1$r_filechar_overlay.fh1$r_filechar_fields.fh1$r_userchar_overlay.fh1$r_userchar_bits.fh1$v_lockedy#define fh1$v_contig fh1$r_filechar_overlay.fh1$r_filechar_fields.fh1$r_userchar_overlay.fh1$r_userchar_bits.fh1$v_contigf#define fh1$b_syschar fh1$r_filechar_overlay.fh1$r_filechar_fields.fh1$r_syschar_overlay.fh1$b_syscharu#define fh1$v_spool fh1$r_filechar_overlay.fh1$r_filechar_fields.fh1$r_syschar_overlay.fh1$r_syschar_bits.fh1$v_spool{#define fh1$v_badblock fh1$r_filechar_overlay.fh r1$r_filechar_fields.fh1$r_syschar_overlay.fh1$r_syschar_bits.fh1$v_badblocky#define fh1$v_markdel fh1$r_filechar_overlay.fh1$r_filechar_fields.fh1$r_syschar_overlay.fh1$r_syschar_bits.fh1$v_markdel"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus } s#endif#pragma __standard #endif /* __FH1DEF_LOADED */ ww+[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior writtten permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS uSoftware, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48: v53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FH2DEF ***/#ifndef __FH2DEF_LOADED#define __FH2DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointwer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !dxefined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* File header definitions for Files-11 Structure Level 2 */N/* */N/*- */ N#d yefine FH2$C_LEVEL1 257 /* 401 octal = structure level 1 */N#define FH2$C_LEVEL2 512 /* 1000 octal = structure level 2 */N#define FH2$C_LEVEL5 1280 /* 2400 octal = structure level 5 */#define FH2$M_VCC_STATE 0x700#define FH2$M_ALM_STATE 0xC0000#define FH2$M_WASCONTIG 0x1#define FH2$M_NOBACKUP 0x2#define FH2$M_WRITEBACK 0x4#define FH2$M_READCHECK 0x8#define FH2$M_WRITCHECK 0x10#define FH2$M_CONTIGB 0x20#define FH2$M_LOCKED 0x40z#define FH2$M_CONTIG 0x80#define FH2$M_BADACL 0x800#define FH2$M_SPOOL 0x1000#define FH2$M_DIRECTORY 0x2000#define FH2$M_BADBLOCK 0x4000#define FH2$M_MARKDEL 0x8000#define FH2$M_NOCHARGE 0x10000#define FH2$M_ERASE 0x20000#define FH2$M_ALM_AIP 0x40000#define FH2$M_SHELVED 0x80000#define FH2$M_SCRATCH 0x100000#define FH2$M_NOMOVE 0x200000"#define FH2$M_NOSHELVABLE 0x400000!#define FH2$M_PRESHELVED 0x800000"#define FH2$M_ALM_ARCHIVED 0x80000(#define FH2$M_SHELVING_RESER {VED 0x800000#define FH2$M_ONLY_RU 0x1#define FH2$M_RUJNL 0x2#define FH2$M_BIJNL 0x4#define FH2$M_AIJNL 0x8#define FH2$M_ATJNL 0x10#define FH2$M_NEVER_RU 0x20#define FH2$M_JOURNAL_FILE 0x40N#define FH2$C_RU_FACILITY_RMS 1 /* RMS */N#define FH2$C_RU_FACILITY_DBMS 2 /* DBMS */N#define FH2$C_RU_FACILITY_RDB 3 /* Rdb/VMS */N#define FH2$C_RU_FACILITY_CHKPNT 4 /* Checkpoint/Re|start */N#define FH2$C_MAX_LINKS 32760 /* maximum link count */N#define FH2$K_LENGTH 80 /* length of header area */N#define FH2$C_LENGTH 80 /* length of header area */N#define FH2$K_SUBSET0_LENGTH 88 /* length of header area */N#define FH2$C_SUBSET0_LENGTH 88 /* length of header area */N#define FH2$K_FULL_LENGTH 108 /* length of full header */N#d}efine FH2$C_FULL_LENGTH 108 /* length of full header */N#define FH2$S_FH2DEF 512 /* Old size name - synonym */ typedef struct _fh2 {N unsigned char fh2$b_idoffset; /* ident area offset in words */N unsigned char fh2$b_mpoffset; /* map area offset in words */R unsigned char fh2$b_acoffset; /* access control list offset in words */N unsigned char fh2$b_rsoffset; /* reserved area offset in words ~*/N unsigned short int fh2$w_seg_num; /* file segment number */ __union {N unsigned short int fh2$w_struclev; /* file structure level */ __struct {N unsigned char fh2$b_strucver; /* file structure version */O unsigned char fh2$b_struclev; /* principal file structure level */$ } fh2$r_struclev_fields;! } fh2$r_struclev_overlay; __union {N unsigned short int fh2$w_fid [3]; /* file ID  */ __struct {N unsigned short int fh2$w_fid_num; /* file number */N unsigned short int fh2$w_fid_seq; /* file sequence number */ __union {O unsigned short int fh2$w_fid_rvn; /* relative volume number */ __struct {N unsigned char fh2$b_fid_rvn; /* alternate format RVN */^ unsigned char fh2$b_fid_nmx; /* alternate format file number  extension */+ } fh2$r_fid_rvn_fields;( } fh2$r_fid_rvn_overlay; } fh2$r_fid_fields; } fh2$r_fid_overlay; __union {N unsigned short int fh2$w_ext_fid [3]; /* extension file ID */ __struct {N unsigned short int fh2$w_ex_fidnum; /* extension file number */U unsigned short int fh2$w_ex_fidseq; /* extension file sequence number */ __union {[ unsigned sho rt int fh2$w_ex_fidrvn; /* extension relative volume number */ __struct {X unsigned char fh2$b_ex_fidrvn; /* alternate format extension RVN */j unsigned char fh2$b_ex_fidnmx; /* alternate format extension file number extension */- } fh2$r_ex_fidrvn_fields;* } fh2$r_ex_fidrvn_overlay;# } fh2$r_ext_fid_fields; } fh2$r_ext_fid_overlay;N unsigned short int fh2$w_recattr [16]; /* fi le record attributes */ __union {N unsigned int fh2$l_filechar; /* file characteristics */ __struct {N unsigned fh2$$_fill_21 : 8; /* reserved */N unsigned fh2$v_vcc_state : 3; /* VCC state bits */N unsigned fh2$$_fill_22 : 7; /* reserved */N/***********The following line is different from FH2 */N unsigned fh2$v_alm_state  : 2; /* ALM state bits */' unsigned fh2$v_fill_0_ : 4;$ } fh2$r_filechar_chunks; __struct {S unsigned fh2$v_wascontig : 1; /* file was (and should be) contiguous */N unsigned fh2$v_nobackup : 1; /* file is not to be backed up */N unsigned fh2$v_writeback : 1; /* file may be write-back cached */N unsigned fh2$v_readcheck : 1; /* verify all read operations */N unsigned fh2$v_writcheck : 1; /* verify all write operations */R unsigned fh2$v_contigb : 1; /* keep file as contiguous as possible */N unsigned fh2$v_locked : 1; /* file is deaccess locked */N unsigned fh2$v_contig : 1; /* file is contiguous */N unsigned fh2$$_fill_23 : 3; /* reserved */N unsigned fh2$v_badacl : 1; /* ACL is invalid */N unsigned fh2$v_spool : 1; /* intermediate spool file */N unsigned fh2$v_directory : 1; /* file is a directory */N unsigned fh2$v_badblock : 1; /* file contains bad blocks */N unsigned fh2$v_markdel : 1; /* file is marked for delete */O unsigned fh2$v_nocharge : 1; /* file space is not to be charged */R unsigned fh2$v_erase : 1; /* erase file contents before deletion */N/***********The following two lines are different from FCH */V unsigned fh2$v_alm_aip : 1; /* Archive in progress - ALM proj cancelled */N unsigned fh2$v_shelved : 1; /* File is shelved */N unsigned fh2$v_scratch : 1; /* Scratch Header used by movefile */N unsigned fh2$v_nomove : 1; /* Disable movefile on this file */S unsigned fh2$v_noshelvable : 1; /* File is not allowed to be shelved */U unsigned fh2$v_preshelved : 1; /* File is shelved but also kept online */N/* Note: The high 8 bits of this longword */N/* are reserved for user and CSS use. */" } fh2$r_filechar_bits;N __struct { /* Overlay SHELVED bit */N unsigned fh2$$_fill_1 : 19; /* Padding */U unsigned fh2$v_alm_archived : 1; /* File archived - ALM proj cancelled */N unsigned fh2$$_fill_2 : 3; /* Padding  */` unsigned fh2$v_shelving_reserved : 1; /* Original placeholder name for PRESHELVED */& } fh2$r_filechar_archived;! } fh2$r_filechar_overlay;N unsigned short int fh2$w_recprot; /* record protection */N unsigned char fh2$b_map_inuse; /* number of map area words in use */N unsigned char fh2$b_acc_mode; /* least privileged access mode */ __union {N unsigned int fh2$l_fileowner; /* file owner UIC  */ __struct {N unsigned short int fh2$w_uicmember; /* UIC member number */N unsigned short int fh2$w_uicgroup; /* UIC group number */% } fh2$r_fileowner_fields;" } fh2$r_fileowner_overlay;N unsigned short int fh2$w_fileprot; /* file protection */ __union {N unsigned short int fh2$w_backlink [3]; /* back link pointer */ __struct {N unsigned short int fh2$w_bk_fidnum; /* back link file number */U unsigned short int fh2$w_bk_fidseq; /* back link file sequence number */ __union {[ unsigned short int fh2$w_bk_fidrvn; /* back link relative volume number */ __struct {X unsigned char fh2$b_bk_fidrvn; /* alternate format back link RVN */j unsigned char fh2$b_bk_fidnmx; /* alternate format back link file number extension */- } fh2$r_bk_fidrvn_fields;* } fh2$r_bk_fidrvn_overlay;$ } fh2$r_backlink_fields;! } fh2$r_backlink_overlay; __union {N unsigned char fh2$b_journal; /* journal control flags */ __struct {W unsigned fh2$v_only_ru : 1; /* file is accessible only in recovery unit */N unsigned fh2$v_rujnl : 1; /* enable recovery unit journal */N unsigned fh2$v_bijnl : 1; /* enable before image journal  */N unsigned fh2$v_aijnl : 1; /* enable after image journal */N unsigned fh2$v_atjnl : 1; /* enable audit trail journal */X unsigned fh2$v_never_ru : 1; /* file is never accessible in recovery unit */N unsigned fh2$v_journal_file : 1; /* this is a journal file */' unsigned fh2$v_fill_1_ : 1;! } fh2$r_journal_bits; } fh2$r_journal_overlay;Y unsigned char fh2$b_ru_active; /* If non-zero, file has active recovery units */N/* (value is recoverable facility id number) */N/* 1-99 reserved to DEC, 100-127 reserved for */N/* CSS, 128-255 reserved for customers. */N short int fh2$w_linkcount; /* (count of links) */N unsigned int fh2$l_highwater; /* high-water mark in file */N int fh2$l_fill_6 [2]; /* reserved  */N __struct { /* security classification mask */N char fh2$b_fill_5 [20]; /* see structure in $CLSDEF */ } fh2$r_class_prot;N char fh2$$_fill_4 [402]; /* rest of file header */N unsigned short int fh2$w_checksum; /* file header checksum */ } FH2; #if !defined(__VAXC)<#define fh2$w_struclev fh2$r_struclev_overlay.fh2$w_struclevR#define fh2$b_strucver fh2$r_struclev_overlay.fh2$r_struclev_fields.fh2$b_strucverR#define fh2$b_struclev fh2$r_struclev_overlay.fh2$r_struclev_fields.fh2$b_struclev-#define fh2$w_fid fh2$r_fid_overlay.fh2$w_fidF#define fh2$w_fid_num fh2$r_fid_overlay.fh2$r_fid_fields.fh2$w_fid_numF#define fh2$w_fid_seq fh2$r_fid_overlay.fh2$r_fid_fields.fh2$w_fid_seq\#define fh2$w_fid_rvn fh2$r_fid_overlay.fh2$r_fid_fields.fh2$r_fid_rvn_overlay.fh2$w_fid_rvnq#define fh2$b_fid_rvn fh2$r_fid_overlay.fh2$r_fid_fields.fh2$r_fid_rvn_overlay.fh2$r_fid_rvn_fields.fh2$b_fid_rvnq#define fh2$b_fid_nmx fh2$r_fid_overlay.fh2$r_fid_fields.fh2$r_fid_rvn_overlay.fh2$r_fid_rvn_fields.fh2$b_fid_nmx9#define fh2$w_ext_fid fh2$r_ext_fid_overlay.fh2$w_ext_fidR#define fh2$w_ex_fidnum fh2$r_ext_fid_overlay.fh2$r_ext_fid_fields.fh2$w_ex_fidnumR#define fh2$w_ex_fidseq fh2$r_ext_fid_overlay.fh2$r_ext_fid_fields.fh2$w_ex_fidseqj#define fh2$w_ex_fidrvn fh2$r_ext_fid_overlay.fh2$r_ext_fid_fields.fh2$r_ex_fidrvn_overlay.fh2$w_ex_fidrvn#define fh2$b_ex_fidrvn fh2$r_ext_fid_overlay.fh2$r_ext_fid_fields.fh2$r_ex_fidrvn_overlay.fh2$r_ex_fidrvn_fields.fh2$b_ex_fidrvn#define fh2$b_ex_fidnmx fh2$r_ext_fid_overlay.fh2$r_ext_fid_fields.fh2$r_ex_fidrvn_overlay.fh2$r_ex_fidrvn_fields.fh2$b_ex_fidnmx<#define fh2$l_filechar fh2$r_filechar_overlay.fh2$l_filecharT#define fh2$v_vcc_state fh2$r_filechar_overlay.fh2$r_filechar_chunks.fh2$v_vcc_stateT#define fh2$v_alm_state fh2$r_filechar_overlay.fh2$r_filechar_chunks.fh2$v_alm_stateR#define fh2$v_wascontig fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_wascontigP#define fh2$v_nobackup fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_nobackupR#define fh2$v_writeback fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_writebackR#define fh2$v_readcheck fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_readcheckR#define fh2$v_writcheck fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_writcheckN#define fh2$v_contigb fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_contigbL#define fh2$v_locked fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_lockedL#define fh2$v_contig fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_contigL#define fh2$v_badacl fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_badaclJ#define fh2$v_spool fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_spoolR#define fh2$v_directory fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_directoryP#define fh2$v_badblock fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_badblockN#define fh2$v_markdel fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_markdelP#define fh2$v_nocharge fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_nochargeJ#define fh2$v_erase fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_eraseN#define fh2$v_alm_aip fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_alm_aipN#define fh2$v_shelved fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_shelvedN#define fh2$v_scratch fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_scratchL#define fh2$v_nomove fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_nomoveV#define fh2$v_noshelvable fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_noshelvableT#define fh2$v_preshelved fh2$r_filechar_overlay.fh2$r_filechar_bits.fh2$v_preshelved\#define fh2$v_alm_archived fh2$r_filechar_overlay.fh2$r_filechar_archived.fh2$v_alm_archivedf#define fh2$v_shelving_reserved fh2$r_filechar_overlay.fh2$r_filechar_archived.fh2$v_shelving_reserved?#define fh2$l_fileowner fh2$r_fileowner_overlay.fh2$l_fileownerV#define fh2$w_uicmember fh2$r_fileowner_overlay.fh2$r_fileowner_fields.fh2$w_uicmemberT#define fh2$w_uicgroup fh2$r_fileowner_overlay.fh2$r_fileowner_fields.fh2$w_uicgroup<#define fh2$w_backlink fh2$r_backlink_overlay.fh2$w_backlinkT#define fh2$w_bk_fidnum fh2$r_backlink_overlay.fh2$r_backlink_fields.fh2$w_bk_fidnumT#define fh2$w_bk_fidseq fh2$r_backlink_overlay.fh2$r_backlink_fields.fh2$w_bk_fidseql#define fh2$w_bk_fidrvn fh2$r_backlink_overlay.fh2$r_backlink_fields.fh2$r_bk_fidrvn_overlay.fh2$w_bk_fidrvn#define fh2$b_bk_fidrvn fh2$r_backlink_overlay.fh2$r_backlink_fields.fh2$r_bk_fidrvn_overlay.fh2$r_bk_fidrvn_fields.fh2$b_bk_fidrvn#define fh2$b_bk_fidnmx fh2$r_backlink_overlay.fh2$r_backlink_fields.fh2$r_bk_fidrvn_overlay.fh2$r_bk_fidrvn_fields.fh2$b_bk_fidnmx9#define fh2$b_journal fh2$r_journal_overlay.fh2$b_journalL#define fh2$v_only_ru fh2$r_journal_overlay.fh2$r_journal_bits.fh2$v_only_ruH#define fh2$v_rujnl fh2$r_journal_overlay.fh2$r_journal_bits.fh2$v_rujnlH#define fh2$v_bijnl fh2$r_journal_overlay.fh2$r_journal_bits.fh2$v_bijnlH#define fh2$v_aijnl fh2$r_journal_overla y.fh2$r_journal_bits.fh2$v_aijnlH#define fh2$v_atjnl fh2$r_journal_overlay.fh2$r_journal_bits.fh2$v_atjnlN#define fh2$v_never_ru fh2$r_journal_overlay.fh2$r_journal_bits.fh2$v_never_ruV#define fh2$v_journal_file fh2$r_journal_overlay.fh2$r_journal_bits.fh2$v_journal_file"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FH2DEF_LOADED */ ww+[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2 024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FI1DEF ***/#ifndef __FI1DEF_LOADED#define __FI1DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define FI1$K_LENGTH 46 /* length of ident area */N#define FI1$C_LENGTH 46 /* length of ident area */N#define FI1$S_FI1DEF 286 /* Old size name - synonym */ typedef struct _fi1 {N unsigned short int fi1$w_filename [3]; /* file name (RAD-50) */N unsigned short int fi1$w_filetype; /* file type (RAD-50) */N unsigned short int fi1$w_version; /* version number (binary) */N unsigned short int fi1$w_revision; /* revision number (binary) */N char fi1$t_revdate [7]; /* revision date (ASCII DDMMMYY) */N char fi1$t_revtime [6]; /* revision time (ASCII HHMMSS) */N char fi1$t_credate [7]; /* creation date (ASCII DDMMMYY) */N char f i1$t_cretime [6]; /* creation time (ASCII HHMMSS) */N char fi1$t_expdate [7]; /* expiration date (ASCII DDMMMYY) */N char fi1$$_fill_1; /* dummy byte to round up */N char fi1$t_mthdr1 [80]; /* HDR1 of ANSI magnetic tape file */N char fi1$t_mthdr2 [80]; /* HDR2 of ANSI magnetic tape file */N char fi1$t_mthdr3 [80]; /* HDR3 of ANSI magnetic tape file */ } FI1;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FI1DEF_LOADED */ wwI,[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************** **********//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FI2DEF ***/#ifndef __FI2DEF_LOADED#define __FI2DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define FI2$K_LENGTH 120 /* length of ident area */N#define FI2$C_LENGTH 120 /* length of ident area */N#define FI2$S_FI2DEF 200 /* Old size name - synonym */ typedef struct _fi2 {S char fi2$t_filename [20]; /* file name, type, and version (ASCII) */N unsigned short int fi2$w_revision; /* revision number (binary) */N unsigned __int64 fi2$q_credate; /* creation date and time */N unsigned __int64 fi2$q_revdate; /* revision date and time */N unsigned __int64 fi2$q_expdate; /* expiration date and time */ N unsigned __int64 fi2$q_bakdate; /* backup date and time */N char fi2$t_filenamext [66]; /* extension file name area */N char fi2$t_userlabel [80]; /* optional user file label */ } FI2;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FI2DEF_LOADED */ wwp,[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV -2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FI5DEF ***/#ifndef __FI5DEF_LOADED#define __FI5DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* ODS-5 format ident area. This is the only structural */N/* difference between ODS-2 and ODS-5. */N/* */ N#define FI5$C_ODS2 0 /* ODS-2 legal ASCII  */P#define FI5$C_ISL1 1 /* ODS-2 illegal ASCII or ISO LATIN-1 */#define FI5$$_TYPE_RESERVED 2O#define FI5$C_UCS2 3 /* Unicode USC-2 (16 bit characters) */#define FI5$M_FIXED_LENGTH 0x10N#define FI5$C_MIN_LENGTH 120 /* Minimum length of ident area */N#define FI5$C_MAX_LENGTH 324 /* Maximum length of ident area */N#define FI5$S_FI5DEF 324 /* Old size name - synonym */ typedef struct _fi5 { __union {N unsigned char fi5$b_control; /* Control flags and name encoding */ __struct {N unsigned fi5$v_nametype : 2; /* Encoding of the filename */O unsigned fi5$$_fill_1 : 2; /* reserved for nametype expansion; */ unsigned fi5$v_fixed_length : 1; /* If set, ident area may not be contracted \/ /* when the name is changed */' unsigned fi5$v_fill_2_ : 3;# } fi5$r_control_fields; } fi5$r_control_overlay;R/* NOTE - The values of FI5$C_ODS2 et al. must be the same as the corresponding */P/* values for name encoding in DIRDEF and FIBDEF. All undefined fields */N/* in FI5$B_CONTROL are REQUIRED to be zero. */N unsigned char fi5$b_namelen; /* Length of name in bytes */N unsigned short int fi5$w_revision; /* revision number (binary) */N unsigned __int64 fi5$q_credate; /* creation date and time */N unsigned __int64 fi5$q_revdate; /* revision date and time */N unsigned __int64 fi5$q_expdate; /* expiration date and time */N unsigned __int64 fi5$q_bakdate; /* backup date and time */N unsigned __int64 fi5$q_accdate; /* last accessed time */N unsigned __int64 fi5$q_attdate; /* last attribute modification time */N unsigned __int64 fi5$q_ex_recattr; /* extended RMS attributes */N __struct { /* File length & record count hint */* unsigned __int64 fi5$q_hint_lo_qw;* unsigned __int64 fi5$q_hint_hi_qw; } fi5$r_length_hint;N char fi5$t_filename [44]; /* file name text */N char fi5$t_filenamext [204]; /* extension file name area */ } FI5; #if !defined(__VAXC)9#define fi5$b_control fi5$r_control_overlay.fi5$b_controlP#define fi5$v_nametype  fi5$r_control_overlay.fi5$r_control_fields.fi5$v_nametypeX#define fi5$v_fixed_length fi5$r_control_overlay.fi5$r_control_fields.fi5$v_fixed_length;#define fi5$q_hint_lo_qw fi5$r_length_hint.fi5$q_hint_lo_qw;#define fi5$q_hint_hi_qw fi5$r_length_hint.fi5$q_hint_hi_qw"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FI5DEF_LOADED */ ww`3-[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-202 4 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FJNDEF ***/#ifndef __FJNDEF_LOADED#define __FJNDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* File journal control bit definitions. These are identical to, and must */O/* track, the bits in JOURNAL above, but are defined relative to the journal */N/* control b yte instead of relative to the file header. */N/* */N/*- */ #define FJN$M_ONLY_RU 0x1#define FJN$M_RUJNL 0x2#define FJN$M_BIJNL 0x4#define FJN$M_AIJNL 0x8#define FJN$M_ATJNL 0x10#define FJN$M_NEVER_RU 0x20#define FJN$M_JOURNAL_FILE 0x40N#define FJN$S_FJNDEF 1 /* Old size name - synonym */  typedef struct _fjn { __union { char fjndef$$_fill_1; __struct {W unsigned fjn$v_only_ru : 1; /* file is accessible only in recovery unit */N unsigned fjn$v_rujnl : 1; /* enable recovery unit journal */N unsigned fjn$v_bijnl : 1; /* enable before image journal */N unsigned fjn$v_aijnl : 1; /* enable after image journal */N unsigned fjn$v_atjnl : 1; /* enable audit trail journal */X unsigned fjn$v_never_ru : 1; /* file is never accessible in recovery unit */N unsigned fjn$v_journal_file : 1; /* this is a journal file */' unsigned fjn$v_fill_7_ : 1; } fjn$r_fill_1_bits; } fjn$r_fjn_overlay; } FJN; #if !defined(__VAXC)G#define fjn$v_only_ru fjn$r_fjn_overlay.fjn$r_fill_1_bits.fjn$v_only_ruC#define fjn$v_rujnl fjn$r_fjn_overlay.fjn$r_fill_1_bits.fjn$v_rujnlC#define fjn$v_bijnl fjn$r_fjn_overlay.fjn$r_ fill_1_bits.fjn$v_bijnlC#define fjn$v_aijnl fjn$r_fjn_overlay.fjn$r_fill_1_bits.fjn$v_aijnlC#define fjn$v_atjnl fjn$r_fjn_overlay.fjn$r_fill_1_bits.fjn$v_atjnlI#define fjn$v_never_ru fjn$r_fjn_overlay.fjn$r_fill_1_bits.fjn$v_never_ruQ#define fjn$v_journal_file fjn$r_fjn_overlay.fjn$r_fill_1_bits.fjn$v_journal_file"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FJNDEF_LOADED */ ww.[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************************************** ***************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */F/* Source: 18-MAR-2004 09:00:52 $1$DGA8345:[LIB_H.SRC]FKBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FKBDEF ***/#ifndef __FKBDEF_LOADED#define __FKBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* FKB - FORK BLOCK */N/* */N/* A FORK BLOCK DESCRIBES THE CONTEXT OF A  FORK PROCESS. EACH UNIT CONTROL */N/* BLOCK CONTAINS A FORK BLOCK AS ITS FIRST SIX LONGWORDS. */N/*- */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fkb {#pragma __nomember_alignmentN struct _fkb *fkb$l_fqfl; /*FORK QUEUE FORWARD LINK */N struct _fkb *fkb$l_fqbl; /*FORK QUEUE BACKWARD LINK */N unsigned short int fkb$w_size; /*SIZE OF FKB IN BYTES */N unsigned char fkb$b_type; /*STRUCTURE TYPE OF FKB */N unsigned char fkb$b_flck; /*FORK LOCK NUMBER */N void (*fkb$l_fpc)(); /*FORK PC */N __int64 fkb$q_fr3; /*FORK R3 */N  __int64 fkb$q_fr4; /*FORK R4 */a void *fkb$l_spinlock; /*Spinlock address (only used if FLCK is SPL$_DYNAMIC) */N int fkb$l_spare_1; /* Spare longword */N __int64 fkb$q_spare_2; /* Spare quadword */ } FKB;N#define FKB$K_LENGTH 48 /*STANDARD LENGTH OF FKB */N#define FKB$C_LENGTH 48 /*STANDARD LENGTH OF FKB */R#define FKB$S_FKBDEF 48 /* Old size name, synonym for FKB$S_FKB */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FKBDEF_LOADED */ wwD.[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//******************************************************************************************************************* *************//*** MODULE $FM1DEF ***/#ifndef __FM1DEF_LOADED#define __FM1DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define FM1$K_POINTERS 10 /* start of retrie val pointers */N#define FM1$C_POINTERS 10 /* start of retrieval pointers */N#define FM1$K_LENGTH 10 /* length of map area */N#define FM1$C_LENGTH 10 /* length of map area */N/* retrieval pointer format */N#define FM1$S_FM1DEF 10 /* Old size name - synonym */ typedef struct _fm1 {V unsigned char fm1$b_ex_segnum; /* extension segment number of this header */O unsigned char fm1$b_ex_rvn; /* extension relative volume number */N unsigned short int fm1$w_ex_filnum; /* extension file number */N unsigned short int fm1$w_ex_filseq; /* extension file sequence number */Q unsigned char fm1$b_countsize; /* retrieval pointer count field size */O unsigned char fm1$b_lbnsize; /* retrieval pointer LBN field size */O unsigned char fm1$b_inuse; /* number of retrieval wor ds in use */R unsigned char fm1$b_avail; /* number of retrieval words available */ } FM1;N#define FM1$S_FM1DEF1 4 /* Old size name - synonym */ typedef struct _fm1_1 {N unsigned char fm1$b_highlbn; /* high order LBN */N unsigned char fm1$b_count; /* block count */N unsigned short int fm1$w_lowlbn; /* low order LBN */ } FM1_1;N#define FM1$S_FM1DEF2 5  /* Old size name - synonym */ Atypedef struct _fm1_2 { /* WARNING: aggregate has origin of -4 */= /* WARNING: aggregate element "fm1$b_prevhlbn" ignored */> /* WARNING: aggregate element "fm1$b_prevcount" ignored */= /* WARNING: aggregate element "fm1$w_prevllbn" ignored */ char fm1def$$_fill_1; } FM1_2;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FM1DEF_LOADED */ ww.[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************************************************** *****************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FM2DEF ***/#ifndef __FM2DEF_LOADED#define __FM2DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* retrieval pointer type codes */N#define FM2$C_PLACEMENT 0 /* 00 = placement control data */N#define FM2$C_FORMAT1 1 /* 01 = format 1 */N#define FM2$C_FORMAT2 2 /* 10 = format 2 */N#define FM2$C_FORMAT3 3 /* 11 = format 3 */N/* format of retrieval pointer */N#define FM2$K_LENGTH0 2 /* length of format 0 (placement) */N#define FM2$C_LENGTH0 2 /* length of format 0 (placement) */N#define FM2$K_LENGTH1 4 /* length of format 1 */N#define FM2$C_LENGTH1 4 /* length of format 1 */ N#define FM2$S_FM2DEF 4 /* Old size name - synonym */ typedef struct _fm2 { __union {N unsigned short int fm2$w_word0; /* first word, of many uses */ __struct {N unsigned fm2$$_fill_1 : 14; /* type specific data */N unsigned fm2$v_format : 2; /* format type code */ } fm2$r_word0_bits0; __struct {N unsigned fm2$v_exact : 1; /* exact placement spe cified */N unsigned fm2$v_oncyl : 1; /* on cylinder allocation desired */' unsigned fm2$$_fill_2 : 10;N unsigned fm2$v_lbn : 1; /* use LBN of next map pointer */N unsigned fm2$v_rvn : 1; /* place on specified RVN */' unsigned fm2$v_fill_3_ : 2; } fm2$r_word0_bits1; __struct {N unsigned fm2$$_fill_3 : 8; /* low byte described below */N unsigned fm2$v_h ighlbn : 6; /* high order LBN */' unsigned fm2$v_fill_4_ : 2; } fm2$r_word0_bits2; __struct {N unsigned fm2$v_count2 : 14; /* format 2 & 3 count field */' unsigned fm2$v_fill_5_ : 2; } fm2$r_word0_bits3;N unsigned char fm2$b_count1; /* format 1 count field */ } fm2$r_word0_overlay;N unsigned short int fm2$w_lowlbn; /* format 1 low order LBN */ } FM 2; #if !defined(__VAXC)3#define fm2$w_word0 fm2$r_word0_overlay.fm2$w_word0G#define fm2$v_format fm2$r_word0_overlay.fm2$r_word0_bits0.fm2$v_formatE#define fm2$v_exact fm2$r_word0_overlay.fm2$r_word0_bits1.fm2$v_exactE#define fm2$v_oncyl fm2$r_word0_overlay.fm2$r_word0_bits1.fm2$v_oncylA#define fm2$v_lbn fm2$r_word0_overlay.fm2$r_word0_bits1.fm2$v_lbnA#define fm2$v_rvn fm2$r_word0_overlay.fm2$r_word0_bits1.fm2$v_rvnI#define fm2$v_highlbn fm2$r_word0_overlay.fm2$r_word0_bits2.fm2$v_hi ghlbnG#define fm2$v_count2 fm2$r_word0_overlay.fm2$r_word0_bits3.fm2$v_count25#define fm2$b_count1 fm2$r_word0_overlay.fm2$b_count1"#endif /* #if !defined(__VAXC) */ N#define FM2$K_LENGTH2 6 /* length of format 2 */N#define FM2$C_LENGTH2 6 /* length of format 2 */N#define FM2$S_FM2DEF1 6 /* Old size name - synonym */ typedef struct _fm2_1 { char fm2$$_fill_4 [2];N unsigned int fm2$l_lbn2;  /* format 2 LBN (longword) */ } FM2_1;N#define FM2$K_LENGTH3 8 /* length of format 3 */N#define FM2$C_LENGTH3 8 /* length of format 3 */N#define FM2$S_FM2DEF2 8 /* Old size name - synonym */ typedef struct _fm2_2 { char fm2$$_fill_5 [2];N unsigned short int fm2$w_lowcount; /* format 3 low order count */N unsigned int fm2$l_lbn3; /* format 3 LBN (longword) */ } FM2_2;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FM2DEF_LOADED */ ww.[UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */E/* Source: 08-AUG-2002 14:06:44 $1$DGA8345:[LIB_H.SRC]FMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FMDEF ***/#ifndef __FMDEF_LOADED#define __FMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define FM$M_SOF 0x7F#define FM$M_SOL 0x3F80#define FM$M_SOR 0x3C000#define FM$M_RRBFR 0xFE000000#define FM$M_RRBPR 0x3F00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fm {N/* */N/* Previous Function State Register */N/**************************************** */#pragma __nomember_align ment __union {, unsigned __int64 fm$iq_frame_marker; __struct {N unsigned fm$v_sof : 7; /* Size of frame */N unsigned fm$v_sol : 7; /* Size of locals */Q unsigned fm$v_sor : 4; /* Size of rotating (# regs = SOR * 8) */S unsigned fm$v_rrbgr : 7; /* Register rename base for general regs */N unsigned fm$v_rrbfr : 7; /* Register Rename Base for FP regs */U  unsigned fm$v_rrbpr : 6; /* Register Rename Base for predicate regs */& unsigned fm$v_fill_0_ : 2; } fm$r_fields; } fm$r_fm_overlay; } FM; #if !defined(__VAXC)=#define fm$iq_frame_marker fm$r_fm_overlay.fm$iq_frame_marker5#define fm$v_sof fm$r_fm_overlay.fm$r_fields.fm$v_sof5#define fm$v_sol fm$r_fm_overlay.fm$r_fields.fm$v_sol5#define fm$v_sor fm$r_fm_overlay.fm$r_fields.fm$v_sor9#define fm$v_rrbgr fm$r_fm_overlay.fm$r_fields.fm$v_rrbgr9#define fm$v_rrbfr fm$r_fm_overlay.fm$r_fields.fm$v_rrbfr9#define fm$v_rrbpr fm$r_fm_overlay.fm$r_fields.fm$v_rrbpr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FMDEF_LOADED */ ww /[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc.  **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */E/* Source: 20-AUG-2001 06:43:08 $1$DGA8345:[LIB_H.SRC]FPDEF.SDL;1 *//***************************************** ***************************************************************************************//*** MODULE $FPDEF ***/#ifndef __FPDEF_LOADED#define __FPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif #endif N/* */N/* Define the I/O Fastpath Function codes */N/* */#define FP$K_BALANCE_PORTS 1#define FP$K_CPU_CONFIGURED 2#define FP$K_CPU_STARTING 3#define FP$K_CPU_STOPPING 4#define FP$K_CPU_STOP_FAILED 5N/* */N/* Define flags for call to exe$fp_select_hwint() */N/* */ #define HWINT$M_CPU_SELECTED 0x1"#define HWINT$M_CPU_NOT_IN_RAD 0x2#define HWINT$M_PRIMARY 0x4 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _hwint_flags {#pragma __nomember_alignment __union { __struct {' unsigned int hwint$l_flags; } hwint$r_fields; __struct {. unsigned hwint$v_cpu_selected : 1;0 unsigned hwint$v_cpu_not_in_rad : 1;) unsigned hwint$v_primary : 1;* unsigned hwint$v_reserved : 1;) unsigned hwint$v_fill_0_ : 4; } hwint$r_bits; } hwint$r_overlay; char hwint$b_fill_1_ [4]; } HWINT_FLAGS; #if !defined(__VAXC)B#define hwint$l_ flags hwint$r_overlay.hwint$r_fields.hwint$l_flagsN#define hwint$v_cpu_selected hwint$r_overlay.hwint$r_bits.hwint$v_cpu_selectedR#define hwint$v_cpu_not_in_rad hwint$r_overlay.hwint$r_bits.hwint$v_cpu_not_in_radD#define hwint$v_primary hwint$r_overlay.hwint$r_bits.hwint$v_primary"#endif /* #if !defined(__VAXC) */ N/* */N/* This structure maintains parameters required for each RAD (Resource */N/* Affinity Domain). The FP struct maintains a pointer to an array of */N/* this structure and the number of these structures in the array. */N/* An array of this structure will be allocated at FP init time */N/* for the number of RADs in the system. The minimum number of RADs */N/* in any system is 1. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fprad {#pragma __nomember_alignment int fprad$l_current_fp_cpu;" int fprad$l_current_hwint_cpu; int fprad$l_radmask; char fprad$b_fill_2_ [4]; } FPRAD;N/* */N/* FP - I/O Fastpath block */N /* */#define FP$M_SPL_HOLD 0x1N#define FP$K_LENGTH 96 /* Length of FP_BLK */N#define FP$C_LENGTH 96 /* Length of FP_BLK */  9#ifdef __cplusplus /* Define structure prototypes */ struct _spl; struct _cbb; struct _sud; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fp {#pragma __nomember_alignmentN struct _spl *fp$l_dlck; /* pointer to spinlock */N int fp$l_dipl; /* device ipl */N unsigned short int fp$w_mbo; /* must-be-one field */N unsigned char fp$b_type; /* structure type */N unsigned char fp$b_subtype;  /* structure sub-type */ __union { __struct {$ unsigned int fp$l_flags; } fp$r_flags_fields; __struct {P unsigned fp$v_spl_hold : 1; /* set if already holding FP SPinLock */' unsigned fp$v_reserved : 1;& unsigned fp$v_fill_3_ : 6; } fp$r_flags_bits; } fp$r_flags_overlay;N unsigned __int64 fp$q_size; /* structure size */N/* pointer to mask o f available CPUs */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */# struct _cbb *fp$q_useable_cpus;#else$ unsigned __int64 fp$q_useable_cpus;#endifN/* Pointer to mask which tries as much as possible to favor */N/* the CPUs in the RAD in which the IO port lives. */R#ifdef __INITIAL_P OINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */# struct _cbb *fp$q_favored_cpus;#else$ unsigned __int64 fp$q_favored_cpus;#endifN/* cells to support assignable ports: */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _sud *fp$l_ports_link; /* link to SUD */N int fp$l_num_ports; /* total number of assignable ports */Q int fp$l_num_user_ports; /* total number of user-assigned ports */N/* cells to support distributed hardware interrupts: */N struct _sud *fp$l_hwint_ports_link; /* link to SUD */N/* Total number of distributed hardware interrupt ports. */ int fp$l _num_hwint_ports;N/* Total number of distributed hardware interrupt ports with */N/* user-assigned interrupt CPU targets. */" int fp$l_num_user_hwint_ports;N/* Last hardware interrupt CPU assigned, absolute number, not a mask. */% int fp$l_last_hwint_cpu_assigned;N/* Pointer to array of FPRAD structures for RAD housekeeping */ struct _fprad *fp$ps_fprad;N/* The number of RADs in this system, which determines the size of the */N/* array of FPRAD structures. The minimum is 1. */ int fp$l_rad_count;N/* Unique Identifier of FP spinlock owner. This field is used to prevent */N/* any routine other than the spinlock owner from clearing the lock. */ int fp$l_spl_owner;N/* Contingency/debug cells: */ int fp$l_spare1; int fp$l_spare2; int fp$l_spare3; int fp$l_spare4; } FP; #if !defined(__VAXC)B#define fp$l_flags fp$r_flags_overlay.fp$r_flags_fields.fp$l_flagsF#define fp$v_spl_hold fp$r_flags_overlay.fp$r_flags_bits.fp$v_spl_hold"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FPDE F_LOADED */ ww@V/[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE.  **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */G/* Source: 19-SEP-2003 11:43:04 $1$DGA8345:[LIB_H.SRC]FPSRDEF.SDL;1 *//***** ***************************************************************************************************************************//*** MODULE $FPSRDEF ***/#ifndef __FPSRDEF_LOADED#define __FPSRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else #define __union variant_union#endif#endif N/* */N/* Floating Point Status Field */N/* */\/* This structure defines the contents of the SF0, SF1, SF2, SF3 fields in the FPSR below */N/**************************************** */#define FPSF$M_FTZ 0x1#define FPSF$M_WRE 0x2#define FPSF$M_PC 0xC#define FPSF$M_RC 0x30#define FPSF$M_TD 0x40#define FPSF$M_V 0x80#define FPSF$M_D 0x100#define FPSF$M_Z 0x200#define FPSF$M_O 0x400#define FPSF$M_U 0x800#define FPSF$M_I 0x1000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fpsf {N/* Control fields  */#pragma __nomember_alignment unsigned fpsf$v_ftz : 1; unsigned fpsf$v_wre : 1; unsigned fpsf$v_pc : 2; unsigned fpsf$v_rc : 2; unsigned fpsf$v_td : 1;N/* Flags fields */ unsigned fpsf$v_v : 1; unsigned fpsf$v_d : 1; unsigned fpsf$v_z : 1; unsigned fpsf$v_o : 1; unsigned fpsf$v_u : 1; unsigned fpsf$v_i : 1;# unsigned fpsf$v_fill_0__1 : 32;# unsigned fpsf$v_fill_0__2 : 19; } FPSF;#define FPSR$M_VD 0x1#define FPSR$M_DD 0x2#define FPSR$M_ZD 0x4#define FPSR$M_OD 0x8#define FPSR$M_UD 0x10#define FPSR$M_ID 0x20#define FPSR$M_TRAPS 0x3F#define FPSR$M_SF0 0x7FFC0#define FPSR$M_SF1 0xFFF80000!#define FPSR$M_SF2 0x1FFF00000000$#define FPSR$M_SF3 0x3FFE00000000000#define FPSR$M_TRAPS_0_6 0x3F#define FPSR$M_SF0_FTZ 0x40#define FPSR$M_SF0_WRE 0x80#define FPSR$M_SF0_PC 0x300#define FPSR$M_SF0_RC 0xC00#define FPSR$M_SF0_TD 0x1000#define FPSR$M_SF0_V 0x2000#define FPSR$M_SF0_D 0x4000#define FPSR$M_SF0_Z 0x8000#define FPSR$M_SF0_O 0x10000#define FPSR$M_SF0_U 0x20000#define FPSR$M_SF0_I 0x40000#define FPSR$M_SF1_FTZ 0x80000#define FPSR$M_SF1_WRE 0x100000#define FPSR$M_SF1_PC 0x600000#define FPSR$M_SF1_RC 0x1800000#define FPSR$M_SF1_TD 0x2000000#define FPSR$M_SF1_V 0x4000000#define FPSR$M_SF1_D 0x8000000#define FPSR$M_SF1_Z 0x10000000#define FPSR$M_SF1_O 0x20000000#define FPSR$M_SF1_U 0x40000000#define FPSR$M_SF1_I 0x80000000"#define FPSR$M_SF2_FTZ 0x100000000"#define FPSR$M_SF2_WRE 0x200000000!#define FPSR$M_SF2_PC 0xC00000000"#define FPSR$M_SF2_RC 0x3000000000"#define FPSR$M_SF2_TD 0x4000000000!#define FPSR$M_SF2_V 0x8000000000"#define FPSR$M_SF2_D 0x10000000000"#define FPSR$M_SF2_Z 0x20000000000"#define FPSR$M_SF2_O 0x40000000000"#define FPSR$M_SF2_U 0x80000000000##define FPSR$M_SF2_I 0x100000000000%#define FPSR$M_SF3_FTZ 0x200000000000%#define FPSR$M _SF3_WRE 0x400000000000%#define FPSR$M_SF3_PC 0x1800000000000%#define FPSR$M_SF3_RC 0x6000000000000%#define FPSR$M_SF3_TD 0x8000000000000%#define FPSR$M_SF3_V 0x10000000000000%#define FPSR$M_SF3_D 0x20000000000000%#define FPSR$M_SF3_Z 0x40000000000000%#define FPSR$M_SF3_O 0x80000000000000&#define FPSR$M_SF3_U 0x100000000000000&#define FPSR$M_SF3_I 0x200000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nome mber_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fpsr {N/* */N/* Floating Point Control and Status Register */N/**************************************** */#pragma __nomember_alignment __union {. unsigned __int64 fpsr$iq_float_status; __struct {# unsigned fpsr$v_vd : 1;# un signed fpsr$v_dd : 1;# unsigned fpsr$v_zd : 1;# unsigned fpsr$v_od : 1;# unsigned fpsr$v_ud : 1;# unsigned fpsr$v_id : 1;( unsigned fpsr$v_fill_1_ : 2; } fpsr$r_trap; __union { __struct {* unsigned fpsr$v_traps : 6;) unsigned fpsr$v_sf0 : 13;) unsigned fpsr$v_sf1 : 13;) unsigned fpsr$v_sf2 : 13;) unsigned fpsr$v_sf3 : 13; unsigned fpsr$v_rv2 : 6; /* Reserved field above SF3. (Do not change location or name. Used by SWIS_EXCEPTION) */% } fpsr$r_fpsr_fields; __struct {. unsigned fpsr$v_traps_0_6 : 6;, unsigned fpsr$v_sf0_ftz : 1;, unsigned fpsr$v_sf0_wre : 1;+ unsigned fpsr$v_sf0_pc : 2;+ unsigned fpsr$v_sf0_rc : 2;+ unsigned fpsr$v_sf0_td : 1;* unsign ed fpsr$v_sf0_v : 1;* unsigned fpsr$v_sf0_d : 1;* unsigned fpsr$v_sf0_z : 1;* unsigned fpsr$v_sf0_o : 1;* unsigned fpsr$v_sf0_u : 1;* unsigned fpsr$v_sf0_i : 1;, unsigned fpsr$v_sf1_ftz : 1;, unsigned fpsr$v_sf1_wre : 1;+ unsigned fpsr$v_sf1_pc : 2;+ unsigned fpsr$v_sf1_rc : 2;+ unsigned fpsr$v_sf1_td : 1;* unsigned fpsr$v_sf 1_v : 1;* unsigned fpsr$v_sf1_d : 1;* unsigned fpsr$v_sf1_z : 1;* unsigned fpsr$v_sf1_o : 1;* unsigned fpsr$v_sf1_u : 1;* unsigned fpsr$v_sf1_i : 1;, unsigned fpsr$v_sf2_ftz : 1;, unsigned fpsr$v_sf2_wre : 1;+ unsigned fpsr$v_sf2_pc : 2;+ unsigned fpsr$v_sf2_rc : 2;+ unsigned fpsr$v_sf2_td : 1;* unsigned fpsr$v_sf2_v : 1;*  unsigned fpsr$v_sf2_d : 1;* unsigned fpsr$v_sf2_z : 1;* unsigned fpsr$v_sf2_o : 1;* unsigned fpsr$v_sf2_u : 1;* unsigned fpsr$v_sf2_i : 1;, unsigned fpsr$v_sf3_ftz : 1;, unsigned fpsr$v_sf3_wre : 1;+ unsigned fpsr$v_sf3_pc : 2;+ unsigned fpsr$v_sf3_rc : 2;+ unsigned fpsr$v_sf3_td : 1;* unsigned fpsr$v_sf3_v : 1;*  unsigned fpsr$v_sf3_d : 1;* unsigned fpsr$v_sf3_z : 1;* unsigned fpsr$v_sf3_o : 1;* unsigned fpsr$v_sf3_u : 1;* unsigned fpsr$v_sf3_i : 1;, unsigned fpsr$v_fill_2_ : 6;& } fpsr$r_fpsr_sf_bits;" } fpsr$r_fpsf_overlay; } fpsr$r_fpsr_overlay; } FPSR; #if !defined(__VAXC)E#define fpsr$iq_float_status fpsr$r_fpsr_overlay.fpsr$iq_float_status;#define fpsr$v_vd fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_vd;#define fpsr$v_dd fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_dd;#define fpsr$v_zd fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_zd;#define fpsr$v_od fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_od;#define fpsr$v_ud fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_ud;#define fpsr$v_id fpsr$r_fpsr_overlay.fpsr$r_trap.fpsr$v_id\#define fpsr$v_traps fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_trapsX#define fpsr$v_sf0 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_sf0X#define fpsr$v_sf1 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_sf1X#define fpsr$v_sf2 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_sf2X#define fpsr$v_sf3 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_sf3X#define fpsr$v_rv2 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_fields.fpsr$v_rv2e#define fpsr$v_traps_0_6 fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_traps_0_6a#define fpsr$v_sf0_ftz fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_ftza#define fpsr$v_sf0_wre fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_wre_#define fpsr$v_sf0_pc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_pc_#define fpsr$v_sf0_rc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_rc_#define fpsr$v_sf0_td fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_td]#define fpsr$v_sf0_v fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_v]#define fpsr$v_sf0_d fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_d]#define fpsr$v_sf0_z fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_z]#define fpsr$v_sf0_o fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_o]#define fpsr$v_sf0_u fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_u]#define fpsr$v_sf0_i fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf0_ia#define fpsr$v_sf1_ftz fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_ftza#define fpsr$v_sf1_wre fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_wre_#define fpsr$v_sf1_pc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_pc_#define fpsr$v_sf1_rc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_rc_#define fpsr$v_sf1_td fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_td]#define fpsr$v_sf1_v fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_v]#define fpsr$v_sf1_d fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_d]#define fpsr$v_sf1_z fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_z]#define fpsr$v_sf1_o fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_o]#define fpsr$v_sf1_u fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_u]#define fpsr$v_sf1_i fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf1_ia#define fpsr$v_sf2_ftz fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_ftza#define fpsr$v_sf2_wre fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_wre_#define fpsr$v_sf2_pc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_pc_#define fpsr$v_sf2_rc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_rc_#define fpsr$v_sf2_td fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_td]#define fpsr$v_sf2_v fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_v]#define fpsr$v_sf2_d fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_d]#define fpsr$v_sf2_z fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_z]#define fpsr$v_sf2_o fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_o]#define fpsr$v_sf2_u fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_u]#define fpsr$v_sf2_i fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf2_ia#define fpsr$v_sf3_ftz fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_ftza#define fpsr$v_sf3_wre fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_wre_#define fpsr$v_sf3_pc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_pc_#define fpsr$v_sf3_rc fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_rc_#define fpsr$v_sf3_td fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_td]#define fpsr$v_sf3_v fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_v]#define fpsr$v_sf3_d fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_d]#define fpsr$v_sf3_z fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_z]#define fpsr$v_sf3_o fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.f psr$v_sf3_o]#define fpsr$v_sf3_u fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_u]#define fpsr$v_sf3_i fpsr$r_fpsr_overlay.fpsr$r_fpsf_overlay.fpsr$r_fpsr_sf_bits.fpsr$v_sf3_i"#endif /* #if !defined(__VAXC) */ f#define FPSR$K_INITIAL_VALUE_L 40895295 /* Low half: sf0=0x0c sf1=0x4e,sf2=sf3=4c traps set to 0x3f */N#define FPSR$K_INITIAL_VALUE_H 622668 /* Upper half */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FPSRDEF_LOADED */ ww`/[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************** *****************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */K/* Source: 17-OCT-2002 12:46:38 $1$DGA8345:[LIB_H.SRC]FP_STATEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FP_STATEDEF ***/#ifndef __FP_STATEDEF_LOADED#define __FP_STATEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknow n_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* Floating Point State */N/*-- ! */  9#ifdef __cplusplus /* Define structure prototypes */struct _fp_state_low_preserved;struct _fp_state_low_volatile; struct _fp_state_high_preserved;struct _fp_state_high_volatile; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fp_state {#pragma "__nomember_alignmentY unsigned __int64 fp_state$q_bitmask_low64; /* Bitmask of low 64 FP registers saved */[ unsigned __int64 fp_state$q_bitmask_high64; /* Bitmask of high 64 FP registers saved */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */> struct _fp_state_low_preserved *fp_state$pq_low_preserved;#else, unsigned __int64 fp_state$pq_low_preserved;#end #ifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */< struct _fp_state_low_volatile *fp_state$pq_low_volatile;#else+ unsigned __int64 fp_state$pq_low_volatile;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */@ struct _fp_state_high_ $preserved *fp_state$pq_high_preserved;#else- unsigned __int64 fp_state$pq_high_preserved;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */> struct _fp_state_high_volatile *fp_state$pq_high_volatile;#else, unsigned __int64 fp_state$pq_high_volatile;#endif } FP_STATE;N/*++ */N/* % 128 bit integer type */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _int128 {#pragma __nomember_alignment' unsigned __int64 int128$q_low_quad;( unsigned __int64 int128$q_high_quad; } INT128; &N/*++ */N/* Floating Point State - low preserved registers */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif(typedef struct _fp_state_low_preserved {#pragma __nomember_alignment 'N INT128 fp_state$r_lp [4]; /* FP registers F2-F5 */ } FP_STATE_LOW_PRESERVED;N/*++ */N/* Floating Point State - low volatile registers */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#els (e#pragma __nomember_alignment#endif'typedef struct _fp_state_low_volatile {#pragma __nomember_alignmentN INT128 fp_state$r_lv [10]; /* FP registers F6-F15 */ } FP_STATE_LOW_VOLATILE;N/*++ */N/* Floating Point State - high preserved registers */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) & )& !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif)typedef struct _fp_state_high_preserved {#pragma __nomember_alignmentN INT128 fp_state$r_hp [16]; /* FP registers F16-F31 */ } FP_STATE_HIGH_PRESERVED;N/*++ */N/* Floating Point State - high volatile registers */N/*-- * */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif(typedef struct _fp_state_high_volatile {#pragma __nomember_alignmentN INT128 fp_state$r_hv [96]; /* FP registers F32 - F127 */ } FP_STATE_HIGH_VOLATILE; $#pragma __member_alignment __restoreR#ifdef __INITI+AL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __FP_STATEDEF_LOADED */ ww/[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confi,dential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential - **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************** .*****************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */G/* Source: 19-APR-1993 14:22:38 $1$DGA8345:[LIB_H.SRC]FQAMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FQAMDEF ***/#ifndef __FQAMDEF_LOADED#define __FQAMDEF_LOADED 1 G#pragma __nostandard /* This fi/le uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define 0__unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */I/* Define FQAM CSR offsets and registers for Firefox systems */N/*-- 1 */N#define FQAM$L_CSR 0 /*FQAM II CSR */#define FQAM$M_CSR_QBUSARB 0x1 #define FQAM$M_CSR_DUMPERROR 0x2#define FQAM$M_CSR_TESTMODE 0x4 typedef struct _csr {N unsigned fqam$v_csr_qbusarb : 1; /*QBUS arbitration enable */N unsigned fqam$v_csr_dumperror : 1; /*Dump error */N unsigned fqam$v_csr_testmode : 1; /*Test mode enable diags */! unsigned f2qam$v_csr_mbz : 28; unsigned fqam$v_fill_0_ : 1; } CSR; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FQAMDEF_LOADED */ ww@0[UM/***************************************************************************/M/** 3 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** 4 **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 5 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */G/* Source: 31-MAY-2022 08:14:26 $1$DGA8345:[LIB_H.SRC]FREDDEF.SDL;1 *//********************************************************************************************************************************/ 6/*** MODULE $FREDDEF ***/#ifndef __FREDDEF_LOADED#define __FREDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif7 #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define FRED$M_ASTEN 0xF#define FRED$M_ASTSR 0xF0#define FRED$M_AST 8EN_KEN 0x1#define FRED$M_ASTEN_EEN 0x2#define FRED$M_ASTEN_SEN 0x4#define FRED$M_ASTEN_UEN 0x8#define FRED$M_ASTSR_KPD 0x10#define FRED$M_ASTSR_EPD 0x20#define FRED$M_ASTSR_SPD 0x40#define FRED$M_ASTSR_UPD 0x80N#define FRED$C_HWPCBLEN 216 /* Length of HWPCB */N#define FRED$K_HWPCBLEN 216 /* Length of HWPCB */N/* */#define FRED$M_SW_FEN 0x1##define 9FRED$M_BORROWED_QUANTUM 0x2"#define FRED$M_PREEMPT_AVOIDED 0x4%#define FRED$M_AST_PENDING 0x80000000N#define FRED$C_KTB_KT_ID 240 /* integer offset to this field */N#define FRED$C_KTB 240 /* integer offset to this field */N#define FRED$C_KT_ID 248 /* integer offset to this field */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ktb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && :!defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fred {N/* */S/* Hardware Privileged Context Block (HWPCB) - This structure must be aligned to */S/* a 128 byte boundary. Natural alignment prevents the structure from crossing a */N/* page boundary. */N;/* */R/* NOTE WELL: There are bit symbols defined here for accessing the saved ASTEN, */X/* ASTSR, FEN and DATFX/AC values in the HWPCB. These symbols are NOT to be used when */]/* interfacing to the ASTEN, ASTSR, FEN or DATFX/AC internal processor registers directly. */O/* See the specific internal register definitions for bitmasks and constants */I/* to be used when interfacing to the IPRs directly. */ <N/* */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *fred$q_ksp; /* Kernel stack pointer */#else unsigned __int64 fred$q_ksp;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragm =a __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *fred$q_esp; /* Executive stack pointer */#else unsigned __int64 fred$q_esp;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *fred$q_ssp; /* Supervisor stack pointer */#else unsigned __int64 fred$q_ssp >;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *fred$q_usp; /* User stack pointer */#else unsigned __int64 fred$q_usp;#endifN unsigned __int64 fred$q_ptbr [4]; /* Page table base for each mode */U unsigned __int64 fred$q_asn; /* ASN (to be combined with mode for PCID) */ __union {N ? unsigned __int64 fred$q_astsr_asten; /* ASTSR / ASTEN quadword */ __struct {N unsigned fred$v_asten : 4; /* AST Enable Register */N unsigned fred$v_astsr : 4; /* AST Pending Summary Register */ } fred$r_ast_bits0; __struct {N unsigned fred$v_asten_ken : 1; /* Kernel AST Enable = 1 */N unsigned fred$v_asten_een : 1; /* Executive AST Enable = 1 */N unsigned fred$v_asten_@sen : 1; /* Supervisor AST Enable = 1 */N unsigned fred$v_asten_uen : 1; /* User AST Enable = 1 */N unsigned fred$v_astsr_kpd : 1; /* Kernel AST Pending = 1 */N unsigned fred$v_astsr_epd : 1; /* Executive AST Pending = 1 */N unsigned fred$v_astsr_spd : 1; /* Supervisor AST Pending = 1 */N unsigned fred$v_astsr_upd : 1; /* User AST Pending = 1 */ } fred$r_ast_bits1; } fred$r_ast_overlAay;N unsigned __int64 fred$q_perf_ctrl; /* Perfomance monitoring control */N unsigned __int64 fred$q_cc; /* Cycle Counter */[ unsigned __int64 fred$q_unq; /* Thread unique value (X86_64 FSBASE, IA64 R13) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */` void *fred$pq_alphareg [4]; /* Pointers to emulated Alpha Bregisters for each mode */#else' unsigned __int64 fred$pq_alphareg [4];#endifN unsigned char fred$b_pmod; /* Previous mode */Q unsigned char fred$b_was_scheduled; /* Process was scheduled at least once */ char fred$b_reserved_1 [6];N unsigned int fred$l_interrupt_depth; /* Intterrupt depth */N int fred$l_cur_frame_mode; /* Mode of currently active frame */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size Cpragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *fred$pq_cur_frame; /* Currently active frame */#else$ unsigned __int64 fred$pq_cur_frame;#endif' unsigned __int64 fred$q_kstack_top;* unsigned __int64 fred$q_kstack_bottom;N __int64 fred$q_pal_rsvd [5]; /* Reserved for PAL Scratch */N/* End of Hardware Privileged Context Block (HWPCB). */N/* D */N/* */N/* XSAVE area for X86 processor context */N/* */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *fred$pq_xsav Ee_area; /* Pointer to XSAVE area */#else% unsigned __int64 fred$pq_xsave_area;#endifN/* */N/* Note: The Alpha architecture defines that the FEN bit in HWPCB cannot */N/* be read, so a separate software FEN bit must be kept. For performance */N/* reasons, we make this bit the low-bit. */N/* F */ __union {N unsigned int fred$l_flags; /* Flags longword */ __struct {N unsigned fred$v_sw_fen : 1; /* Software FEN bit */U unsigned fred$v_borrowed_quantum : 1; /* The next quantum was borrowed */S unsigned fred$v_preempt_avoided : 1; /* Prio raised to avoid preempt */- unsigned fred$v_fill_flags2 : 28;N unsigned fred$v_ast_pending : 1; /* AST pending optimization */G } fred$r_flags_bits; } fred$r_flags_overlay;N unsigned int fred$l_fill_1; /* Pad to correctly align next */N/* quadword field and overlays */N/* PHD$L_EXTRACPU, so don't */N/* use it for anything. */N unsigned __int64 fred$q_asnseq; /* Current ASN/RID Sequence Number */R#ifdef __INITIAL_POINTER_SIZE /* HDefined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _ktb *fred$q_ktb; /* kernel thread block address */#else unsigned __int64 fred$q_ktb;#endifN unsigned __int64 fred$q_kt_id; /* kernel thread id */N char fred$b_reserved [3840]; /* unused, pad to 4096 bytes */ } FRED; #if !defined(__VAXC)@#define fred$q_astsr_asten fred$r_ast_Ioverlay.fred$q_astsr_astenE#define fred$v_asten fred$r_ast_overlay.fred$r_ast_bits0.fred$v_astenE#define fred$v_astsr fred$r_ast_overlay.fred$r_ast_bits0.fred$v_astsrM#define fred$v_asten_ken fred$r_ast_overlay.fred$r_ast_bits1.fred$v_asten_kenM#define fred$v_asten_een fred$r_ast_overlay.fred$r_ast_bits1.fred$v_asten_eenM#define fred$v_asten_sen fred$r_ast_overlay.fred$r_ast_bits1.fred$v_asten_senM#define fred$v_asten_uen fred$r_ast_overlay.fred$r_ast_bits1.fred$v_asten_uenM#define fred$vJ_astsr_kpd fred$r_ast_overlay.fred$r_ast_bits1.fred$v_astsr_kpdM#define fred$v_astsr_epd fred$r_ast_overlay.fred$r_ast_bits1.fred$v_astsr_epdM#define fred$v_astsr_spd fred$r_ast_overlay.fred$r_ast_bits1.fred$v_astsr_spdM#define fred$v_astsr_upd fred$r_ast_overlay.fred$r_ast_bits1.fred$v_astsr_upd6#define fred$l_flags fred$r_flags_overlay.fred$l_flagsJ#define fred$v_sw_fen fred$r_flags_overlay.fred$r_flags_bits.fred$v_sw_fen^#define fred$v_borrowed_quantum fred$r_flags_overlay.fred$r_flags_bi Kts.fred$v_borrowed_quantum\#define fred$v_preempt_avoided fred$r_flags_overlay.fred$r_flags_bits.fred$v_preempt_avoidedT#define fred$v_ast_pending fred$r_flags_overlay.fred$r_flags_bits.fred$v_ast_pending"#endif /* #if !defined(__VAXC) */ N#define FRED$C_LENGTH 4096 /* Length of Fred block */N#define FRED$K_LENGTH 4096 /* Length of Fred block */N#define FRED$S_FREDDEF 4096 /* Old size name - synonym */N#define FRED$K_SHIMFT 12 /* Shift value for FRED size */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FREDDEF_LOADED */ ww0[UM/***************************************************************************/M/** _FPDEFFPSRDEF FP_STATEDEF* FQAMDEF1FREDDEFKFSBDEF>FSHWAFSHWA_ROUTINESiFTRDDEFrhFTUCBDEFFTVECDEFFVEDEFLFVHDEFFWDDEF GCONOUTDEFjGESDEFd GLX_ROUTINESGMDBDEF9 GPSCFGDEF- GPS_ROUTINESGSDDEFvHD1DEFHD2DEFHD3DEFDHD4DEF~HM1DEFHM2DEFHPCDEFzHPETDEF>HQBDEFMzHRBDEFdHULBDEFoHWPRTDEF8IA64_ASMN **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** O **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** P **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */I/* Source: 23-JUN-2004 13:16:13 $1$DGA8345:[LIB_H.SRC]RMSPUBSTR.SDL;1 *//********************************************************************************************************************************//*** Q MODULE $FSBDEF ***/#ifndef __FSBDEF_LOADED#define __FSBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #iRfdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */SN/* FSB field definitions */N/* */N/* File statistics block (fsb) */N/* */I/* An FSB is associated with a file when the ACE$V_STATISTICS */I/* bit is set in the RMS attributes ACE. It is used to keep track */I/* of RMS file statistics. T */N/* */#define FSB$M_PRIVATE 0x1#define FSB$M_RMSDEV 0x2N#define FSB$C_BID 25 /* fsb id code */c#define FSB$K_STANDARD_BLN 276 /* Length of FSB without RMS development specific fields */c#define FSB$C_STANDARD_BLN 276 /* Length of FSB without RMS development specific fields */N/* Reserved for RMS development private moni Utoring */n#define FSBFLG$_GET 0 /* Flags used for keeping track of relative file statistics updates */#define FSBFLG$_FIND 1#define FSBFLG$_PUT 2#define FSBFLG$_UPDATE 3#define FSBFLG$_DELETE 4#define FSBFLG$_MAX 5N#define FSB$K_VERSION 1 /* Current version of FSB */N#define FSB$C_VERSION 1 /* Current version of FSB */#define FSB$C_SEQ 1#define FSB$C_REL 2N#define FSB$C_IDX 3 V /* File organization constants */N#define FSB$K_BLN 384 /* Length of FSB */N#define FSB$C_BLN 384 /* Length of FSB */N#define FSB$S_FSBDEF 384 /* Old size name - synonym */ typedef struct _fsb {N char fsb$b_fill_1 [6]; /* first three longwords unused */ __union {N unsigned short int fsb$w_flags; /* fsb flags */ __st Wruct {N unsigned fsb$v_private : 1; /* FSB is for only one stream */N unsigned fsb$v_rmsdev : 1; /* Reserved RMS fields being used */' unsigned fsb$v_fill_2_ : 6; } fsb$r_fill_1_; } fsb$r_fill_0_;N unsigned char fsb$b_bid; /* block id */N unsigned char fsb$b_bln; /* block length in longwords */N unsigned char fsb$b_org; /* file organization */XN unsigned char fsb$b_version; /* current version of FSB */N unsigned int fsb$l_seqgets; /* # of sequential gets to file */N unsigned int fsb$l_keygets; /* # of keyed gets to file */N unsigned int fsb$l_rfagets; /* # of gets by RFA to file */N unsigned __int64 fsb$q_getbytes; /* Total size of all gets in bytes */N unsigned int fsb$l_seqputs; /* # of sequential puts */N unsigned int fsb$l_kYeyputs; /* # of puts by key */N unsigned __int64 fsb$q_putbytes; /* Total size of all puts in bytes */N unsigned int fsb$l_updates; /* # of updates */P unsigned __int64 fsb$q_updatebytes; /* Total size of all updates in bytes */N unsigned int fsb$l_deletes; /* # of deletes */N unsigned int fsb$l_truncates; /* # of truncates */S unsigned int fsb$l_truncblks; /* TotalZ size in blocks of all truncates */N unsigned int fsb$l_seqfinds; /* # of sequential finds */N unsigned int fsb$l_keyfinds; /* # of keyed finds */N unsigned int fsb$l_rfafinds; /* # of finds by RFA */N unsigned int fsb$l_reads; /* # of $READs to file */N unsigned __int64 fsb$q_readbytes; /* # of bytes of all $READs */N unsigned int fsb$l_connects; /* # of connects to this fil[e */N unsigned int fsb$l_disconnects; /* # of disconnects from file */N unsigned int fsb$l_extends; /* # of extends of file */P unsigned int fsb$l_extblocks; /* # of blocks file has been extended */N unsigned int fsb$l_flushes; /* # of flushes of file */N unsigned int fsb$l_rewinds; /* # of rewinds of file */N unsigned int fsb$l_writes; /* # of $WRITEs to file */O unsigned\ __int64 fsb$q_writebytes; /* # of bytes of all $WRITEs to file */N unsigned int fsb$l_flckenqs; /* # of file lock ENQ's */N unsigned int fsb$l_flckdeqs; /* # of file lock DEQ's */N unsigned int fsb$l_flckcnvs; /* # of file lock conversions */N unsigned int fsb$l_lblckenqs; /* # of local buffer lock ENQ's */N unsigned int fsb$l_lblckdeqs; /* # of local buffer lock DEQ's */P unsigned int fsb$l_lblckcnvs; ] /* # of local buffer lock conversions */N unsigned int fsb$l_gblckenqs; /* # of global buffer lock ENQ's */N unsigned int fsb$l_gblckdeqs; /* # of global buffer lock DEQ's */Q unsigned int fsb$l_gblckcnvs; /* # of global buffer lock conversions */N unsigned int fsb$l_gslckenqs; /* # of global section lock ENQ's */N unsigned int fsb$l_gslckdeqs; /* # of global section lock DEQ's */R unsigned int fsb$l_gslckcnvs; /* # of global s^ection lock conversions */N unsigned int fsb$l_rlckenqs; /* # of record lock ENQ's */N unsigned int fsb$l_rlckdeqs; /* # of record lock DEQ's */N unsigned int fsb$l_rlckcnvs; /* # of record lock conversions */N unsigned int fsb$l_applckenqs; /* # of append lock ENQ's */N unsigned int fsb$l_applckdeqs; /* # of append lock DEQ's */N unsigned int fsb$l_applckcnvs; /* # of append lock conversions */_Q unsigned int fsb$l_flblkasts; /* # of file lock blocking ASTs queued */Y unsigned int fsb$l_lblblkasts; /* # of local buffer lock blocking ASTs queued */Z unsigned int fsb$l_gblblkasts; /* # of global buffer lock blocking ASTs queued */Z unsigned int fsb$l_appblkasts; /* # of shared append lock blocking ASTs queued */N unsigned int fsb$l_lcachehits; /* # of cache hits on local buffers */Y unsigned int fsb$l_lcache_attempts; /* # of attempts to use `the local buffer cache */O unsigned int fsb$l_gcachehits; /* # of cache hits on global buffers */Z unsigned int fsb$l_gcache_attempts; /* # of attempts to use the global buffer cache */Y unsigned int fsb$l_gbrdirios; /* # of direct io's due to global buffer reads */Z unsigned int fsb$l_gbwdirios; /* # of direct io's due to global buffer writes */X unsigned int fsb$l_lbrdirios; /* # of direct io's due to local buffer reads */Y unsigned int fsb$l_lbwdiriaos; /* # of direct io's due to local buffer writes */N unsigned int fsb$l_bktsplt; /* # of 2 bucket splits */N unsigned int fsb$l_mbktsplt; /* # of multi-bucket splits */N unsigned int fsb$l_opens; /* # of times the file is opened */N unsigned int fsb$l_closes; /* # of times the file is closed */[ unsigned int fsb$l_gsblkasts; /* # of global section lock blocking ASTs queued */P unsigned int fsb$l_xqpqiosb; /* Count of XQP QIOs requested by RMS */X unsigned int fsb$l_flwaits; /* # of waits forced by getting the file lock */] unsigned int fsb$l_lbwaits; /* # of waits forced by getting local buffer locks */^ unsigned int fsb$l_gbwaits; /* # of waits forced by getting global buffer locks */b unsigned int fsb$l_gswaits; /* # of waits forced by getting the global section lock */W unsigned int fsb$l_rlwaits; /* # of waits forced by getting crecord locks */Z unsigned int fsb$l_apwaits; /* # of waits forced by getting the Append lock */] unsigned int fsb$l_totwaits; /* Total # of waits (or stalls) performed by RMS. */g unsigned int fsb$l_outbufquo; /* Number of times a process runs out of global buffer quota */] unsigned int fsb$l_rmsdev1; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdev2; /* Reserved for RMS development private monitoring */] d unsigned int fsb$l_rmsdev3; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdev4; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdev5; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdev6; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdev7; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdeev8; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdev9; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdev10; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdev11; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdev12; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdev13; /* Reserved fofr RMS development private monitoring */] unsigned int fsb$l_rmsdev14; /* Reserved for RMS development private monitoring */] unsigned int fsb$l_rmsdev15; /* Reserved for RMS development private monitoring */ __union {^ unsigned int fsb$l_intcol_gbhsh; /* Interlock collision on global buffer hash table */P unsigned int fsb$l_intcol_hshtbl; /* Old field name for compatibility */ } fsb$r_intcol_overlay;Y unsigned int fsb$l_intcol_gbh; /* I gnterlock Collision on global buffer header */ __union {Y unsigned int fsb$l_intrndwn_gbhsh; /* Interlock still held at rundown on GBHSH */P unsigned int fsb$l_intres_setimr; /* Old field name for compatibility */& } fsb$r_intrndwngbhsh_overlay; __union {U unsigned int fsb$l_intrndwn_gbh; /* Interlock still held at rundown on GBH */N unsigned int fsb$l_intnotres; /* Old field name for compatibility */$ } fsb$r_intrndwngbh_overlay; } hFSB; #if !defined(__VAXC)-#define fsb$w_flags fsb$r_fill_0_.fsb$w_flags?#define fsb$v_private fsb$r_fill_0_.fsb$r_fill_1_.fsb$v_private=#define fsb$v_rmsdev fsb$r_fill_0_.fsb$r_fill_1_.fsb$v_rmsdevB#define fsb$l_intcol_gbhsh fsb$r_intcol_overlay.fsb$l_intcol_gbhshD#define fsb$l_intcol_hshtbl fsb$r_intcol_overlay.fsb$l_intcol_hshtblM#define fsb$l_intrndwn_gbhsh fsb$r_intrndwngbhsh_overlay.fsb$l_intrndwn_gbhshK#define fsb$l_intres_setimr fsb$r_intrndwngbhsh_overlay.fsb$l_intres_setimrGi#define fsb$l_intrndwn_gbh fsb$r_intrndwngbh_overlay.fsb$l_intrndwn_gbhA#define fsb$l_intnotres fsb$r_intrndwngbh_overlay.fsb$l_intnotres"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FSBDEF_LOADED */ j ww0[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/kM/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMSl Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */G/* Source: 21-APR-1993 10:34:26 $1$DGA8345:[LIB_H.SRC]FTRDDEF.SDL;1 *//******************* m*************************************************************************************************************//*** MODULE $FTRDDEF ***/#ifndef __FTRDDEF_LOADED#define __FTRDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptrn size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __un oion variant_union#endif#endif N/*+ */N/* */N/* FTRD - Read request packet for FTDRIVER */N/* */N/* The FTRD packet is very similar to an IRP but much smaller. It has an */N/* ACB at the front, the EFN, and some information about the read pbuffer. */N/* */N/*- */N#define FTRD$K_LENGTH 40 /* Size of read packet */N#define FTRD$C_LENGTH 40 /* */#define FTRD$S_FTRDDEF 40 typedef struct _ftrd {N void *ftrd$l_astqfl; /* Read and AST queue forward link */N void *ftrd$l_astqbl; q /* Read and AST queue backward link */N unsigned short int ftrd$w_size; /* Size of structure */N unsigned char ftrd$b_type; /* Type of structure */Q unsigned char ftrd$b_rmod; /* RMOD bits used by AST delivery code */T unsigned int ftrd$l_pid; /* Internal PID of process to receive AST */N int (*ftrd$l_ast)(); /* AST routine address */N unsigned int ftrd$l_astprm; /* AST paramreter */N unsigned char ftrd$b_efn; /* EFN to be set */N unsigned char ftrd$b_unused; /* Spare byte */N unsigned short int ftrd$w_read_size; /* Size of read request in bytes */N void *ftrd$l_buff_addr; /* Address of I/O buffer */N void *ftrd$l_char_addr; /* Address of next character */Q unsigned int ftrd$l_chars_read; /* Number of characters in read buffers */ } FTRD; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FTRDDEF_LOADED */ ww1[UM/***************************************************************************/M/** t **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/uM/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************v****************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */H/* Source: 23-MAY-2008 15:01:19 $1$DGA8345:[LIB_H.SRC]FTUCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FTUCBDEF ***/#ifndef __FTUCBDEF_LwOADED#define __FTUCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#dxefine __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */I/* $FTUCBDEF follows here only becauyse there is no way to get the the */N/* UCB$K_TT_LENGTH into another module. */N/* */I/* Pseudo Terminal Driver definitions */N/* */O/* These definitions define the device dependent extenstions of the TTYUCB. */N/* Certain portions of the UCB are assumed to be contigious and must z not be */N/* split. The AST list heads are order and must remain in order $PTDDEF in */N/* STARDEFMP.SDL is in the same order. */N/* */  #include #include #define UCB$M_FT_BSY 0x1#define UCB$M_FT_DELPEND 0x2#define UCB$M_FT_DELETE_ACT 0x4#define UCB$M_FT_INPUT_CRIT 0x8N#define UCB$C_FT_LENGTH 928 /* Size of FT UCB {*/N#define UCB$K_FT_LENGTH 928 /* " " " " */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ftrd;struct _ucb$r_fr3_overlay; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ft_ucb {#pragma __nomember_alignment TTY_UCB ucb$r_ttyucb;|P unsigned int ucb$l_ft_ipid; /* Interal PID of UCB control process */W void *ucb$l_ft_1st_page; /* P0/P1 address of first page of I/O buffer */T void *ucb$l_ft_lst_page; /* P0/P1 address of end of the I/O buffer */[ void *ucb$l_ft_s0_page; /* S0 address of first page that maps I/O buffer */f unsigned __int64 ucb$q_ft_buffer_handle; /* Pointer to buffer handle used by buffer object code */N/* } */N/* Driver private state information */N/* */ __union {N unsigned short int ucb$w_ft_sts; /* Driver private status word */ __struct {N unsigned ucb$v_ft_bsy : 1; /* Read request pending */R unsigned ucb$v_ft_delpend : 1; /* It is safe to queue deletion fork */N unsigned ucb$v_ft_de ~lete_act : 1; /* Deletion fork queued */a unsigned ucb$v_ft_input_crit : 1; /* Type ahead buffer running out or out of space */' unsigned ucb$v_fill_0_ : 4; } ucb$r_ft_sts_bits; } ucb$r_ft_sts_overlay;Q unsigned short int ucb$w_ft_chan; /* Control applications channel number */N struct _ftrd *ucb$l_ft_readqfl; /* Read requests queue forward link */O struct _ftrd *ucb$l_ft_readqbl; /* Read requests queue backward link */Q  struct _ftrd *ucb$l_ft_curr_read; /* Currend read request packet address */N/* */N/* AST list head this must remain in order and should not be changed. */N/* */Q/* The AST list head is overlaid and becomes the fork block used to delete the */S/* UCB when the control connection deassigns it's channel. This is safe becuase */S/* once the co ntrol connection channel is deleted it is impossible to enable one */N/* of these ASTs. */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment) unsigned char ucb$b_ucb_fkb [48]; __struct {R struct _acb *ucb$l_ft_hangup_ast; /* Address of hangup template ACB */N struct _acb *ucb$l_ft_xon_ast; /* Address of XON template ACB */N struct _acb *ucb$l_ft_bell_ast; /* Address of BELL template ACB */N struct _acb *ucb$l_ft_dc3_ast; /* Address of DC3 template ACB */U struct _acb *ucb$l_ft_stop_ast; /* Address of stop output template ACB */Y struct _acb *ucb$l_ft_resume_ast; /* Address of resume output template ACB */` struct _acb *ucb$l_ft_set_ast; /* Address of changed characteristics template ACB */W struct _acb *ucb$l_ft_abort_ast; /* Address of abort output template ACB */Z struct _acb *ucb$l_ft_start_read_ast; /* Address of start read template ACB */\ struct _acb *ucb$l_ft_middle_read_ast; /* Address of middle read template ACB */V struct _acb *ucb$l_ft_end_read_ast; /* Address of end read template ACB */ } ucb$r_ftucb; __struct {N struct _fkb *ucb$l_ft_fqfl; /* Fork queue forward link */N struct _fkb *ucb$l_ft_fqbl; /* Fork queue backward link */N unsigned short int ucb$w_ft_frksize; /* Size of the fork block */N unsigned char ucb$b_ft_frk_type; /* Type of structure */N unsigned char ucb$b_ft_flck; /* Fork lock index */Y void (*ucb$l_ft_fpc)(); /* Fork PC this points device dele tion routine */N __int64 ucb$q_ft_fr3; /* R3 will be 0 */N __int64 ucb$q_ft_fr4; /* UCB address */$ } ucb$r_ft_fork_overlay; } ucb$r_ft_delete_fork;N/* End Union */N/* */N/* Add 64 bytes of storage for Access Port Name. The string is of the */N/* form first by te is length followed by 63 ASCII characters. */N/* */0 unsigned char ucb$b_ft_portname_string [64]; } FT_UCB; #if !defined(__VAXC)6#define ucb$w_ft_sts ucb$r_ft_sts_overlay.ucb$w_ft_stsH#define ucb$v_ft_bsy ucb$r_ft_sts_overlay.ucb$r_ft_sts_bits.ucb$v_ft_bsyP#define ucb$v_ft_delpend ucb$r_ft_sts_overlay.ucb$r_ft_sts_bits.ucb$v_ft_delpendV#define ucb$v_ft_delete_act ucb$r_ft_sts_overlay.ucb$r_ft_ sts_bits.ucb$v_ft_delete_actV#define ucb$v_ft_input_crit ucb$r_ft_sts_overlay.ucb$r_ft_sts_bits.ucb$v_ft_input_crit4#define ucb$r_ftucb ucb$r_ft_delete_fork.ucb$r_ftucb;#define ucb$l_ft_hangup_ast ucb$r_ftucb.ucb$l_ft_hangup_ast5#define ucb$l_ft_xon_ast ucb$r_ftucb.ucb$l_ft_xon_ast7#define ucb$l_ft_bell_ast ucb$r_ftucb.ucb$l_ft_bell_ast5#define ucb$l_ft_dc3_ast ucb$r_ftucb.ucb$l_ft_dc3_ast7#define ucb$l_ft_stop_ast ucb$r_ftucb.ucb$l_ft_stop_ast;#define ucb$l_ft_resume_ast ucb$r_ftucb.ucb$ l_ft_resume_ast5#define ucb$l_ft_set_ast ucb$r_ftucb.ucb$l_ft_set_ast9#define ucb$l_ft_abort_ast ucb$r_ftucb.ucb$l_ft_abort_astC#define ucb$l_ft_start_read_ast ucb$r_ftucb.ucb$l_ft_start_read_astE#define ucb$l_ft_middle_read_ast ucb$r_ftucb.ucb$l_ft_middle_read_ast?#define ucb$l_ft_end_read_ast ucb$r_ftucb.ucb$l_ft_end_read_astH#define ucb$r_ft_fork_overlay ucb$r_ft_delete_fork.ucb$r_ft_fork_overlay9#define ucb$l_ft_fqfl ucb$r_ft_fork_overlay.ucb$l_ft_fqfl9#define ucb$l_ft_fqbl ucb$r_ft _fork_overlay.ucb$l_ft_fqbl?#define ucb$w_ft_frksize ucb$r_ft_fork_overlay.ucb$w_ft_frksizeA#define ucb$b_ft_frk_type ucb$r_ft_fork_overlay.ucb$b_ft_frk_type9#define ucb$b_ft_flck ucb$r_ft_fork_overlay.ucb$b_ft_flck7#define ucb$l_ft_fpc ucb$r_ft_fork_overlay.ucb$l_ft_fpc7#define ucb$q_ft_fr3 ucb$r_ft_fork_overlay.ucb$q_ft_fr37#define ucb$q_ft_fr4 ucb$r_ft_fork_overlay.ucb$q_ft_fr4"#endif /* #if !defined(__VAXC) */ V#define UCB$S_FTUCBDEF 928 /* Old size name, synonym for UCB$S_FT_UCB */ :#define ucb$r_ft_ucb ucb$r_ttyucb.ucb$r_ltrmucb.ucb$r_ucb-#define ucb$r_ft_ltrm ucb$r_ttyucb.ucb$r_ltrm"#define ucb$r_ft_tty ucb$r_ttyucb  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FTUCBDEF_LOADED */ wwR1[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JAN-2004 07:50:02 $1$DGA8345:[LIB_H.SRC]TTYDEF.SDL;1 *//***************************** ***************************************************************************************************//*** MODULE $FTVECDEF ***/#ifndef __FTVECDEF_LOADED#define __FTVECDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include #define PORT_FT_LENGTH 100#define PORTS_FTVECDEF 100 typedef struct _ft_vec { TT_PORT portr_ft_tt_port; int (*port_ft_create)(); int (*port_ft_read)(); int (*port_ft_write)(); int (*port_ft_set_event)(); int (*port_ft_cancel)();! int (*port_ft_decterm_set)(); } FT_VEC;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FTVECDEF_LOADED */ ww y1[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************* ***********************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */F/* Source: 10-FEB-2004 16:16:29 $1$DGA8345:[LIB_H.SRC]FVEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FVEDEF ***/#ifndef __FVEDEF_LOADED#define __FVEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* Define Fandle Vector Entry */N/*- */N#define FVE$K_LENGTH 3 2 /* Length of FVE */N#define FVE$C_LENGTH 32 /* Length of FVE */N#define FVE$S_FVEDEF 32 /* Size of FVE */  9#ifdef __cplusplus /* Define structure prototypes */ struct _irp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fve {#pragma __nomember_alignmentN struct _irp *fve$l_irpptr; /* Address of associated IRP */N unsigned int fve$l_orgfun; /* Original value of IRP$L_FUNC */N unsigned int fve$l_datob1; /* Data buffer object handle */ unsigned int fve$l_datob2;N unsigned int fve$l_iosob1; /* IOSA buffer object handle */ unsigned int fve$l_iosob2; __int64 fve$q_dbylen; } FVE; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FVEDEF_LOADED */ ww@1[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */F/* Source: 10-FEB-2004 16:16:29 $1$DGA8345:[LIB_H.SRC]FVEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FVHDEF ***/#ifndef __FVHDEF_LOADED#define __FVHDEF_LOADED 1  G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* Define Fandle Vector Header  */N/*- */N#define FVH$K_LENGTH 32 /* Length of FVH */N#define FVH$C_LENGTH 32 /* Length of FVH */N#define FVH$S_FVEDEF 32 /* Size of FVH */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fvh {#pragma __nomember_alignment int fvh$l_flink; int fvh$l_blink; short int fvh$w_size; char fvh$b_type; char fvh$b_subtype;N int fvh$l_real_size; /* Actual size might be > 16 bits */N unsigned int fvh$l_ccbobj [2]; /* Process CCB buffer object handle */ int fvh$l_fill1; int fvh$l_fill2; } FVH; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FVHDEF_LOADED */ wwP1[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************** ***************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $FWDDEF ***/#ifndef __FWDDEF_LOADED#define __FWDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* Forward message field definitions */N/*--- */N#def ine FWD$C_SIZE 8 /* Size of the forward part of */N/* the message */ typedef struct _fwddef {N unsigned short int fwd$w_function; /* Function code */$ unsigned char fwd$g_fwdaddr [6];N/* Address to forward packet to */ } FWDDEF; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __FWDDEF_LOADED */ wwp<2[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************************** *********************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */J/* Source: 05-OCT-2006 13:32:18 $1$DGA8345:[LIB_H.SRC]GCONOUTDEF.SDL;1 *//********************************************************************************************************************************/%/*** MODULE gconoutdef IDENT X-2 ***/#ifndef __GCONOUTDEF_LOADED#define __GCONOUTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Copyright 2006 Hewlett-Packard Development Company, L.P. */N/*  */N/* Confidential computer software. Valid license from HP and/or */N/* its subsidiaries required for possession, use, or copying. */N/* */N/* Consistent with FAR 12.211 and 12.212, Commercial Computer Software, */N/* Computer Software Documentation, and Technical Data for Commercial */N/* Items are licensed to the U.S. Government under vendor's standard */N/* commercial license. */N/* */N/* Neither HP nor any of its subsidiaries shall be liable for technical */N/* or editorial errors or omissions contained herein. The information */N/* in this document is provided "as is" without warranty of any kind and */N/* is subject to change without notice. The warranties for HP products */N/* are set forth in the express limited warranty statements accompanying */N/* such products. Nothing herein should be construed as constituting an */N/* additional warranty. */N/* */N/* ABSTRACT: */N/* */I/* This module describes the data structure for the generic  */I/* graphics console for IA64 */N/* */N/* AUTHOR: */N/* */I/* Fred Kleinsorge, May 2006 */N/* */N/* MODIFIED BY:  */N/* */9/* X-2 FGK0929-01 Fred Kleinsorge 29-Sep-2006 */B/* Add busy indication, and get rid of VISIBLE bit - it isn't */B/* being used on IA64 (HW_READY is always set/cleared at the */B/* same time). */N/* */3/* X-1 FGK Fred Kleinso rge 28-Sep-2006 */B/* Initial entry. */N/* */ N#define GCON$K_MAGIC 136911190 /* Magic number */N#define GCON$K_NO_DRIVER 0 /* No driver init */N#define GCON$K_BOOT_DRIVER 1 /* Boot driver */N#define GCON$K_EXEC_DRIVER 2 /* Exec driver */N#def ine GCON$K_GRAPHICS_DRIVER 3 /* Graphics driver */#define GCON$M_INHIBIT 0x1#define GCON$M_HW_READY 0x2!#define GCON$M_CURSOR_ENABLED 0x4##define GCON$M_CURSOR_DISPLAYED 0x8#define GCON$M_STATUS_LINE 0x10$#define GCON$M_STATUS_WS_SELECT 0x20!#define GCON$M_VT52_GRAPHICS 0x40#define GCON$M_VT52_MODE 0x80##define GCON$M_VT100_GRAPHICS 0x100#define GCON$M_VT100_MODE 0x200N#define GCON$K_NO_STATUS 0 /* No status line */N#defin e GCON$K_BOOT_STATUS 1 /* Boot driver status line */N#define GCON$K_WINDOW_STATUS 2 /* Graphics driver status line */N#define GCON$K_EXEC_STATUS 3 /* Execlet status line */#define GCON$K_LENGTH 25480#define GCON$K_DEF_WIDTH 80#define GCON$K_DEF_HEIGHT 24#define GCON$K_MAX_WIDTH 132#define GCON$K_MAX_HEIGHT 44#define GCON$K_MINOR_VERSION 1#define GCON$K_MAJOR_VERSION 1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cpl usplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gcon {#pragma __nomember_alignmentN unsigned int gcon$l_version; /* Block version # */N int gcon$l_length; /* Block length */Q int gcon$l_valid; /* Structure valid when equal to MAGIC */N int gcon$l_error; /* Error  */X int gcon$l_driver; /* Which driver last initialized address data */ __union {N int gcon$l_flags; /* Flags word */ __struct {N unsigned gcon$v_inhibit : 1; /* Inhibit HW output to console */N unsigned gcon$v_hw_ready : 1; /* HW ready */N unsigned gcon$v_cursor_enabled : 1; /* Cursor enabled */N unsigned gcon$v_cursor_displayed : 1; /* Cursor is displayed */N unsigned gcon$v_status_line : 1; /* Status line enabled */X unsigned gcon$v_status_ws_select : 1; /* Select Window System status line */R unsigned gcon$v_vt52_graphics : 1; /* VT52 graphic character set... */P unsigned gcon$v_vt52_mode : 1; /* Recognize VT52 escape sequences */T unsigned gcon$v_vt100_graphics : 1; /* VT100 graphic character set... */R unsigned gcon$v_vt100_mode : 1; /* Recogni ze VT100 escape sequences */( unsigned gcon$v_fill_0_ : 6;" } gcon$r_flags_struct; } gcon$r_flags_union;N int gcon$l_column; /* Console X position */N int gcon$l_row; /* Console Y position */N int gcon$l_width; /* Console width (chars) */N int gcon$l_height; /* Console height (chars) */N unsigned int gcon$l_vt52_escape; /* VT52 Escape sequence type */N/* */N/* Video text attributes */N/* */N unsigned int gcon$l_attributes; /* Video attributes */N unsigned int gcon$l_attr_normal; /* Normal text */N unsigned int gcon$l_attr_current; /* Current attributes  */N unsigned int gcon$l_text; /* Normal Text Color (0xBBGGRR00) */R unsigned int gcon$l_back; /* Normal Background Color (0xBBGGRR00) */O int gcon$l_text_color; /* Text color in ANSI format (30-37) */Z int gcon$l_text_back; /* Text background color in ANSI format (40-47) */N/* */N/* */N/* */N int gcon$l_error_char; /* Error character */N/* */N/* Force quadword alignment! */N/* */N char gcon$t_align_1 [4]; /* Quadword Alignment */N/*  */N/* */N/* */ __union {( __int64 gcon$q_device_dependent;S void *gcon$a_device_dependent; /* Pointer to device dependent extension */ } gcon$r_dd_union;N/* */N/*  */N/* */ __union {# __int64 gcon$q_window_data;O void *gcon$a_window_data; /* Pointer to runtime window context */ } gcon$r_wd_union;N/* */N/* Public entry for OPDRIVER style call */N/*  */K/* PUTC(char *string, int length, UCB* pUCB, int *ret_len) */N/* */ __union { __int64 gcon$q_conout;N int (*gcon$a_conout)(); /* Output a string */ } gcon$r_conout_union;N/* */N/* This is the GCON version... */N/*  */K/* PUT_STRING(GCON, char *string, int length) */N/* */ __union {" __int64 gcon$q_put_string;N int (*gcon$a_put_string)(); /* Output a string */ } gcon$r_puts_union;N/* */N/* Device dependent action routines  for drawing to the graphics device. */N/* */ __union {# __int64 gcon$q_draw_string;N void (*gcon$a_draw_string)(); /* Draw string routine */ } gcon$r_ds_union; __union {( __int64 gcon$q_draw_dev_segment;N void (*gcon$a_draw_dev_segment)(); /* Draw string routine */ } gcon$r_dds_union; __union {) __int64 gcon$q_erase_dev_segment;N void (*gcon$a_erase_dev_segment)(); /* Draw string routine */ } gcon$r_eds_union; __union {! __int64 gcon$q_draw_char;N void (*gcon$a_draw_char)(); /* Draw a character */ } gcon$r_dc_union; __union {! __int64 gcon$q_read_char;N void (*gcon$a_read_char)(); /* Read a char from the display */ } gcon$r_rc_union; __union {( __int64 gcon$q_clear_background;N vo id (*gcon$a_clear_background)(); /* Clear the entire console */ } gcon$r_cb_union; __union {% __int64 gcon$q_redraw_screen;N void (*gcon$a_redraw_screen)(); /* Redraw screen from backing store */ } gcon$r_rs_union; __union {& __int64 gcon$q_select_console;N void (*gcon$a_select_console)(); /* Device select */ } gcon$r_sc_union; __union {( __int64 gcon$q_deselect_console;N void (*gcon$a_ deselect_console)(); /* Device unselect */ } gcon$r_dsc_union; __union {& __int64 gcon$q_enable_console;N void (*gcon$a_enable_console)(); /* Device enable */ } gcon$r_ec_union; __union {' __int64 gcon$q_disable_console;N int (*gcon$a_disable_console)(); /* Device disable */ } gcon$r_dic_union; __union {! __int64 gcon$q_erase_row;N void (*gcon$a_erase_row)() ; /* Clear a character row */ } gcon$r_er_union; __union {! __int64 gcon$q_scroll_up;N void (*gcon$a_scroll_up)(); /* Up scroll (linefeed) */ } gcon$r_su_union; __union {# __int64 gcon$q_scroll_down;N void (*gcon$a_scroll_down)(); /* Down scroll (reverse index) */ } gcon$r_sd_union; __union {# __int64 gcon$q_draw_cursor;N void (*gcon$a_draw_cursor)(); /* Draw cursor  */ } gcon$r_drc_union; __union {' __int64 gcon$q_read_cursor_pos;N void (*gcon$a_read_cursor_pos)(); /* Read the cursor position */ } gcon$r_rcp_union; __union {$ __int64 gcon$q_erase_cursor;N void (*gcon$a_erase_cursor)(); /* Erase Cursor */ } gcon$r_ecr_union; __union {$ __int64 gcon$q_scroll_bs_up;N void (*gcon$a_scroll_bs_up)(); /* Up scroll (linefeed)  */ } gcon$r_sbu_union; __union {& __int64 gcon$q_scroll_bs_down;N void (*gcon$a_scroll_bs_down)(); /* Down scroll (reverse index) */ } gcon$r_sbd_union; __union {) __int64 gcon$q_draw_string_to_bs;N void (*gcon$a_draw_string_to_bs)(); /* Draw string routine */ } gcon$r_dsbs_union; __union {) __int64 gcon$q_save_screen_to_bs;N void (*gcon$a_save_screen_to_bs)(); /* Save screen to BS  */ } gcon$r_ssbs_union; __union {! __int64 gcon$q_init_font;N void (*gcon$a_init_font)(); /* Initialize font */ } gcon$r_ldf_union; __union {" __int64 gcon$q_load_glyph;N void (*gcon$a_load_glyph)(); /* Load a single glyph */ } gcon$r_ldg_union; __union {$ __int64 gcon$q_save_console;N void (*gcon$a_save_console)(); /* Save console state */  } gcon$r_save_union; __union {' __int64 gcon$q_restore_console;N void (*gcon$a_restore_console)(); /* Restore console state */ } gcon$r_rest_union; __union {& __int64 gcon$q_reinit_console;N void (*gcon$a_reinit_console)(); /* Do re-init sequence */ } gcon$r_rint_union; __union {' __int64 gcon$q_set_status_line;N void (*gcon$a_set_status_line)(); /* Set status line */ } gcon$r_ssl_union; __union {" __int64 gcon$q_send_input;N void (*gcon$a_send_input)(); /* Emulate input from terminal */ } gcon$r_skb_union; __union {% __int64 gcon$q_set_text_attr;N void (*gcon$a_set_text_attr)(); /* Set color/bold/blink/etc */ } gcon$r_sta_union;N unsigned int gcon$l_reserved [32]; /* Extra's */P int gcon$l_busy; /* Set/Cleared on entry to PUT_STRING */N/* */N/* Status line defaults */N/* */N int gcon$l_status_line_len; /* Status line length */N char gcon$b_status_line [132]; /* Status line (0) */N int gcon$l_status_line_ws_len; /* Status line length */N char gcon$b_status_line_ws [132]; /* Status line (1) */N int gcon$l_status_line_row; /* Status line row number */N unsigned int gcon$l_attr_status_line; /* Status line attributes */N int gcon$l_line_offsets [48]; /* Offsets to line starts */N char gcon$b_line_lengths [48]; /* Length of each line */N/* */N/* Force quadword alignment!  */N/* */N char gcon$t_align_2 [4]; /* Quadword Alignment */N/* */V/* Each character position has space for the character attribute and the character */N/* */N int gcon$l_line_data [6120]; /* Character array  */ } GCON; #if !defined(__VAXC)4#define gcon$l_flags gcon$r_flags_union.gcon$l_flagsL#define gcon$v_inhibit gcon$r_flags_union.gcon$r_flags_struct.gcon$v_inhibitN#define gcon$v_hw_ready gcon$r_flags_union.gcon$r_flags_struct.gcon$v_hw_readyZ#define gcon$v_cursor_enabled gcon$r_flags_union.gcon$r_flags_struct.gcon$v_cursor_enabled^#define gcon$v_cursor_displayed gcon$r_flags_union.gcon$r_flags_struct.gcon$v_cursor_displayedT#define gcon$v_status_line gcon$r_flags_union.gcon$r_flags_struct.gcon$v_status_line^#define gcon$v_status_ws_select gcon$r_flags_union.gcon$r_flags_struct.gcon$v_status_ws_selectX#define gcon$v_vt52_graphics gcon$r_flags_union.gcon$r_flags_struct.gcon$v_vt52_graphicsP#define gcon$v_vt52_mode gcon$r_flags_union.gcon$r_flags_struct.gcon$v_vt52_modeZ#define gcon$v_vt100_graphics gcon$r_flags_union.gcon$r_flags_struct.gcon$v_vt100_graphicsR#define gcon$v_vt100_mode gcon$r_flags_union.gcon$r_flags_struct.gcon$v_vt100_modeG#define gcon$q_device_depe ndent gcon$r_dd_union.gcon$q_device_dependentG#define gcon$a_device_dependent gcon$r_dd_union.gcon$a_device_dependent=#define gcon$q_window_data gcon$r_wd_union.gcon$q_window_data=#define gcon$a_window_data gcon$r_wd_union.gcon$a_window_data7#define gcon$q_conout gcon$r_conout_union.gcon$q_conout7#define gcon$a_conout gcon$r_conout_union.gcon$a_conout=#define gcon$q_put_string gcon$r_puts_union.gcon$q_put_string=#define gcon$a_put_string gcon$r_puts_union.gcon$a_put_string=#define gcon$q_draw_string gcon$r_ds_union.gcon$q_draw_string=#define gcon$a_draw_string gcon$r_ds_union.gcon$a_draw_stringH#define gcon$q_draw_dev_segment gcon$r_dds_union.gcon$q_draw_dev_segmentH#define gcon$a_draw_dev_segment gcon$r_dds_union.gcon$a_draw_dev_segmentJ#define gcon$q_erase_dev_segment gcon$r_eds_union.gcon$q_erase_dev_segmentJ#define gcon$a_erase_dev_segment gcon$r_eds_union.gcon$a_erase_dev_segment9#define gcon$q_draw_char gcon$r_dc_union.gcon$q_draw_char9#define gcon$a_draw_char gcon$ r_dc_union.gcon$a_draw_char9#define gcon$q_read_char gcon$r_rc_union.gcon$q_read_char9#define gcon$a_read_char gcon$r_rc_union.gcon$a_read_charG#define gcon$q_clear_background gcon$r_cb_union.gcon$q_clear_backgroundG#define gcon$a_clear_background gcon$r_cb_union.gcon$a_clear_backgroundA#define gcon$q_redraw_screen gcon$r_rs_union.gcon$q_redraw_screenA#define gcon$a_redraw_screen gcon$r_rs_union.gcon$a_redraw_screenC#define gcon$q_select_console gcon$r_sc_union.gcon$q_select_consoleC#define gcon$a_select_console gcon$r_sc_union.gcon$a_select_consoleH#define gcon$q_deselect_console gcon$r_dsc_union.gcon$q_deselect_consoleH#define gcon$a_deselect_console gcon$r_dsc_union.gcon$a_deselect_consoleC#define gcon$q_enable_console gcon$r_ec_union.gcon$q_enable_consoleC#define gcon$a_enable_console gcon$r_ec_union.gcon$a_enable_consoleF#define gcon$q_disable_console gcon$r_dic_union.gcon$q_disable_consoleF#define gcon$a_disable_console gcon$r_dic_union.gcon$a_disable_console9#defin e gcon$q_erase_row gcon$r_er_union.gcon$q_erase_row9#define gcon$a_erase_row gcon$r_er_union.gcon$a_erase_row9#define gcon$q_scroll_up gcon$r_su_union.gcon$q_scroll_up9#define gcon$a_scroll_up gcon$r_su_union.gcon$a_scroll_up=#define gcon$q_scroll_down gcon$r_sd_union.gcon$q_scroll_down=#define gcon$a_scroll_down gcon$r_sd_union.gcon$a_scroll_down>#define gcon$q_draw_cursor gcon$r_drc_union.gcon$q_draw_cursor>#define gcon$a_draw_cursor gcon$r_drc_union.gcon$a_draw_cursorF#define gcon$q_read_cursor_pos gcon$r_rcp_union.gcon$q_read_cursor_posF#define gcon$a_read_cursor_pos gcon$r_rcp_union.gcon$a_read_cursor_pos@#define gcon$q_erase_cursor gcon$r_ecr_union.gcon$q_erase_cursor@#define gcon$a_erase_cursor gcon$r_ecr_union.gcon$a_erase_cursor@#define gcon$q_scroll_bs_up gcon$r_sbu_union.gcon$q_scroll_bs_up@#define gcon$a_scroll_bs_up gcon$r_sbu_union.gcon$a_scroll_bs_upD#define gcon$q_scroll_bs_down gcon$r_sbd_union.gcon$q_scroll_bs_downD#define gcon$a_scroll_bs_down gcon$r_sbd_union.gcon$a_scroll_bs_downK#define gcon$q_draw_string_to_bs gcon$r_dsbs_union.gcon$q_draw_string_to_bsK#define gcon$a_draw_string_to_bs gcon$r_dsbs_union.gcon$a_draw_string_to_bsK#define gcon$q_save_screen_to_bs gcon$r_ssbs_union.gcon$q_save_screen_to_bsK#define gcon$a_save_screen_to_bs gcon$r_ssbs_union.gcon$a_save_screen_to_bs:#define gcon$q_init_font gcon$r_ldf_union.gcon$q_init_font:#define gcon$a_init_font gcon$r_ldf_union.gcon$a_init_font<#define gcon$q_load_glyph gcon$r_ldg_union.gcon$ q_load_glyph<#define gcon$a_load_glyph gcon$r_ldg_union.gcon$a_load_glyphA#define gcon$q_save_console gcon$r_save_union.gcon$q_save_consoleA#define gcon$a_save_console gcon$r_save_union.gcon$a_save_consoleG#define gcon$q_restore_console gcon$r_rest_union.gcon$q_restore_consoleG#define gcon$a_restore_console gcon$r_rest_union.gcon$a_restore_consoleE#define gcon$q_reinit_console gcon$r_rint_union.gcon$q_reinit_consoleE#define gcon$a_reinit_console gcon$r_rint_union.gcon$a_reinit_consoleF#d efine gcon$q_set_status_line gcon$r_ssl_union.gcon$q_set_status_lineF#define gcon$a_set_status_line gcon$r_ssl_union.gcon$a_set_status_line<#define gcon$q_send_input gcon$r_skb_union.gcon$q_send_input<#define gcon$a_send_input gcon$r_skb_union.gcon$a_send_inputB#define gcon$q_set_text_attr gcon$r_sta_union.gcon$q_set_text_attrB#define gcon$a_set_text_attr gcon$r_sta_union.gcon$a_set_text_attr"#endif /* #if !defined(__VAXC) */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus ) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gfont {#pragma __nomember_alignmentN int gfont$l_width; /* Glyph width */N int gfont$l_height; /* Glyph height */N int gfont$l_byte_count; /* Byte count */N int gfont$l_byte_width; /* Byte width */N int gfont$l_fill_count; /* fill count */N int gfont$l_fill_data; /* fill data */N int gfont$l_char_count; /* Number of characters */N int gfont$l_first_char; /* First Character */N int gfont$l_error_character; /* Error glyph index */N char *gfont$ps_char_directory [260]; /* Array of glyph pointers */ char gfont$b_fill_1_ [4]; } GFONT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __GCONOUTDEF_LOADED */ ww2[UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 16-DEC-2002 21:47:01 $1$DGA8345:[LIB_H.SRC]GESDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $GESDEF ***/#ifndef __GESDEF_LOADED#define __GESDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* Types of sensor data.  */N/*-- */#define GES$K_TEMP 0#define GES$K_POWER 1#define GES$K_FAN 2#define GES$K_TABLE_SIZE 3N/*++ */N/* An array of these data structures will be created to store information */N/* about the sensors. There will be one array for each of the sensor types, */N/* and in each array there will be one of these structures for each */N/* individual sensor. */N/* */N/* 63 55 47 39 31 23 15 7 0 */N/* +---------------------------------------------------------------+ */N/* | FRU Node ID from cfg$iq_cfg_id64 in CFGDEF.H | */N/* +---------------------------------------------------------------+ */N/* | Node Flags from cfg$iq_node_flags in CFGDEF.H | */N/* +-------------------------------+-------------------------------+ */N/* | Bitfield | Offset | */N/* +-------+-------+-------+-------+-------------------------------+ */N/* | Node Change | Sub- | Type | Sensor Properties | */N/* | Counter | type | | | */N/* +-------+-------+-------+-------+-------------------------------+ */N/* | Node Handle | */N/* +---------------------------------------------------------------+ */N/* | Subpacket Handle | */N/* +---------------------------------------------------------------+ */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defin ed(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sensor_fru {N/* */N/* The byte fields in this 8-byte structure are declared in CFGDEF.H as */N/* struct cfg$_cfg_node_id_fru_desc in the CFG_NODE structure. */#pragma __nomember_alignment' unsigned __int64 ges$q_fru_node_id;N/*  */N/* The following quadword is the cfg$iq_node_flags field of the FRU */N/* CFG_NODE. This provides a lot of salient information about the FRU. */& unsigned __int64 ges$q_node_flags;N/* */N/* The following two fields comprise the 64-bit cfg$iq_sensor_console_id */N/* declared in CFGDEF.H. The console_id field provides unique */N/* identifier for each FRU node in the tree. */N/* */N/* <31:0> Offset to the data in the hardware's environmental storage */N/* medium. */ unsigned int ges$l_offset;N/* */N/* <63:32> Can be bitfield or offset to Value. */  unsigned int ges$l_bitfield;N/* */N/* Property of the data (status or value or both). */N/* See Config Tree Spec, pp 9-105 */ unsigned int ges$l_prop;N/* */N/* Config Tree FRU Node Type. */ unsigned char ges$b_type;N/*  */N/* Config Tree FRU Node Subtype. */ unsigned char ges$b_subtype;N/* */N/* Config Tree Node Change Counter. */1 unsigned short int ges$w_node_change_counter;N/* */N/* Config Tree Node Handle.  */ __int64 ges$q_node_handle;N/* */N/* Config Tree Subpacket Handle. */ __int64 ges$q_subpkt_handle; } SENSOR_FRU;"#define GES$K_SENSOR_FRU_LENGTH 48N/*++ */P/* This struct will be used to build a table of pointers to SENSOR_FRU arrays */N/* for each of the sensor types, and the corresponding information required */N/* to access and maintain each of the arrays. */N/* */N/* 63 31 15 0 */N/* +-------------------------------+-------------------------------+ */N/* | pointer to SENSOR_FRU array | Item Code | */N/* +-------------------------------+---------------+---------------+ */N/* | Required Buffer Size | Sensor Count | Array Valid | */N/* +-------------------------------+---------------+---------------+ */N/* | Last Init Time | */N/* +---------------------------------------------------------------+ */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus ) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _env_sensor {N/* */N/* This element will be used by code to lookup the correct */N/* entry in the table of ENV_SENSOR structs. */#pragma __nomember_alignment int ges$l_item_code;N/*  */N/* Array of SENSOR_FRU structs for all sensors of this type. */* struct _sensor_fru *ges$ps_sensor_fru;N/* */N/* This boolean will be used to determine if the SENSOR_FRU */N/* array is inited and valid. */* unsigned short int ges$w_array_inited;N/*  */N/* Count of sensors of this type. */! short int ges$w_sensor_count;N/* */N/* Size of buffer required to contain all data, formatted as an array */N/* of ESFITEM, from all sensors of this type (see esfdef.h). */ int ges$l_req_buff_size;N/* */N/* The system time of the last init of the SENSOR_FRU array. */* unsigned __int64 ges$q_last_init_time; } ENV_SENSOR;"#define GES$K_ENV_SENSOR_LENGTH 24 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __GESDEF_LOADED */ ww2[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc.  **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:34 by OpenVMS SDL V3.7 */G/* Source: 20-MAR-2000 08:55:58 $1$DGA8345:[LIB_H.SRC]GMDBDEF.SDL;1 *//************************************************* *******************************************************************************//*** MODULE $gmdbdef ***/#ifndef __GMDBDEF_LOADED#define __GMDBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#e ndif N/* */N/* Ident X-24 */N/* */I/* GMDBDEF.SDL -- Galaxy GMDB definitions */N/* */I/* Copyright Digital Equipment Corporation, 1997 - 1998. */I/* All rights reserved.  */N/* */I/* The software contained on this media is proprietary to and */I/* embodies the confidential technology of Digital Equipment */I/* Corporation. Possession, use, duplication, or dissemination */I/* of the software and media is authorized only pursuant to a */I/* valid written license from Digital Equipment Corporation.  */N/* */I/* RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure */I/* by the U.S. Government is subject to restrictions as set */I/* forth in Subparagraph (c) (1) (ii) of DFARS 252.227-7013, */I/* or in FAR 52.227-19, as applicable. */N/* */O/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */N/* */N/* */P/* Description: This file contains the definitions for values and structures */B/* needed contained in the Galaxy Management Database (GMDB) */N/* */N/* Environment: OpenVMS Operating System, privileged kernel-mode  */N/* */I/* Author: Paul Harter */N/* */N/* Modifications: */I/* */8/* X-24 Susan M. Lewis 20-Mar-2000 */N/* Add a glxint$ code for Galaxy machine check handling. */N/* */5/* X-23 CMOS Christian Moser 26-OCT-1998 */B/* Obsolete old version fields in GMDB and NODEB. */N/* */5/* X-22 CMOS Christian Moser 22-SEP-1998 */B/* Remove the semi-colon of the quadword constant definitions, */B/* otherwise they cannot be used within an IF statement. */B/* Add crash timestamp field to nodeblock, so we know when the */B/* crash reason field was written. */N/* */5/* X-21 RAB Richard A. Bishop 8-Sep-1998 */B/* Change names of reserved fields so that as changes */B/* are made over time, SDA can see them */I/* */5/* X-20 CMOS Christian Moser 7-SEP-1998 */B/* Remove duplicate constants GLX_ST$_xxx instroduced in X-19, */B/* Bliss doesn't like them. */N/* */5/* X-19 CMOS Christian Moser 17-AUG-1998 */B/* Add Revision and version fields, move important and static */B/* fields (offset/length pairs) to the beginning and add */B/* padding. This is needed for possible future changes to t he */B/* GMDB without forcing the whole Galaxy to be shut off for */B/* a version upgrade. */N/* */5/* X-18 RAB Richard A. Bishop 6-Jul-1998 */B/* Fix up reserved field name */I/* */4/* X-17 JRK390 Jim Kauffman 23-Jun-1998 */B/* Add glxint$ code for packet passing */N/* */4/* X-16 LGD Linda G. Duffell 26-May-1998 */B/* Add a GLXINT$ code for Shared Memory LAN. */N/* */;/* X-15 PKH-G026 Paul K. Harter, Jr. 2-Apr-1998 */B/* Change last_heartbeat field in node block to a quadword. */N/*  */2/* X-14 AHM044 Drew Mason 2-Apr-1998 */B/* Add crash status code field to the node block. */N/* */;/* X-13 PKH-G019 Paul K. Harter, Jr. 10-Mar-1998 */B/* Add node timeout field to gmdb and some tracking fields */B/* to the node block. */N/* */5/* X-12 GHJ Gregory H. Jordan 5-Mar-1998 */B/* Add a glxint$ code for Shared Memory CI. */N/* */2/* X-11 AHM043 Drew Mason 5-Mar-1998 */B/* Add gmdb$q_died_time and gmdb$l_last_node. */N/* */2/* X-10 AHM043 Drew Mason 4-Mar-1998 */B/* Add nodeb$q_leaving_time.  */N/* */5/* X-9 KLN2058 Karen L. Noel 3-Mar-1998 */B/* Add glxint$ codes for nodes attaching and detaching */B/* to and from shared memory regions. */N/* */4/* X-8 RAB Richard A. Bishop 26-Feb-1998 */B/* Add changes to enhance SDA support: word for gmdbl flags, */B/* some reserved fields, type/subtype for node block. */N/* */1/* X-7 AHM039 Drew Mason 18-Feb-1998 */B/* Add fields for node being removed and removal start time. */N/* */1/* X-6 AHM031 Drew Mason 12-Jan-1998 */B/* Add crash reason to the node block. */N/*  */3/* X-5 JRK390 Jim Kauffman 8-Jan-1998 */B/* Locking communication bit definitions */N/* */:/* X-4 PKH-G005 Paul K. Harter, Jr. 18-Dec-1997 */B/* Added upper-bound values to galaxy and node state. */N/* */:/* X-3 PKH-G003 Paul K. Harter, Jr. 2-Dec-1997 */B/* Made fields in gmdb_lock naturally aligned. Added */B/* last_joiner to gmdb, and made incarnations into */B/* quadwords. Fixed typo in "to_remove_off" */N/* */:/* X-2 PKH-G001 Paul K. Harter, Jr. 19-Nov-1997 */B/* Added GMDB and NODEB fields and comments. Inserted */B/* alignment and padding. Added "broken" to gmdb lock. */N/*  */5/* X-1 KLN2010 Karen L. Noel 23-Oct-1997 */B/* Initial entry */N/* */  U#include /* Define the MMAP type; GMDB contains an embedded MMAP type */N/* values for galaxy state. */#define GLX_ST$_ALL_DEAD 0#define GLX_ST$_CREATING 1#define GLX_ST$_NODE_JOINING 2#define GLX_ST$_NODE_LEAVING 3#define GLX_ST$_OPERATIONAL 4#define GLX_ST$_RECOVERING 5#define GLX_ST$_VALIDATING 6#define GLX_ST$_REFORMING 7#define GLX_ST$_REFORM_PEND 8#define GLX_ST$_CRASHING 9#define GLX_ST$_CRASH_PEND 10#define GLX_ST$_TOO_BIG 11#define NB_ST$_DEAD 0#define NB_ST$_BOOTING 1#define NB_ST$_CREATING 2#define NB_ST$_JOINING 3#define NB_ST$_LEAVING 4#define NB_ST$_MEMBER 5#define NB_ST$_TOO_BIG 6#define GMDBL$M_LOCKED 0x1#define GMDBL$M_BROKEN 0x2$#define GMDBL$M_RESERVED_2_15 0xFFFC c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _gmdb_lock {#pragma __nomember_alignment" unsigned __int64 gmdbl$q_quad; __struct { __union {- unsigned short int gmdbl$w_flags; __struct {N unsigned gmdbl$v_locked : 1; /* lock is currently held */P unsigned gmdbl$v_broken : 1; /* lock was taken from dead node */4 unsigned gmdbl$v_reserved_2_15 : 14;% } gmdbl$r_flags_bits;$ } gmdbl$r_flags_overlay;) unsigned short int gmdbl$w_extra;N unsigned int gmdbl$l_owner; /* if held, current owner */ } gmdbl$r_fields; } GMDB_LOCK; #if !defined(__VAXC)H#define gmdbl$w_flags gmdbl$r_fields.gmdbl$r_flags_overlay.gmdbl$w_flags ]#define gmdbl$v_locked gmdbl$r_fields.gmdbl$r_flags_overlay.gmdbl$r_flags_bits.gmdbl$v_locked]#define gmdbl$v_broken gmdbl$r_fields.gmdbl$r_flags_overlay.gmdbl$r_flags_bits.gmdbl$v_brokenk#define gmdbl$v_reserved_2_15 gmdbl$r_fields.gmdbl$r_flags_overlay.gmdbl$r_flags_bits.gmdbl$v_reserved_2_152#define gmdbl$w_extra gmdbl$r_fields.gmdbl$w_extra2#define gmdbl$l_owner gmdbl$r_fields.gmdbl$l_owner"#endif /* #if !defined(__VAXC) */ N/* GMDB revision and Galaxy version   */N/* */R/* The Galaxy creator will fill in the GMDB revision field with GMDB$K_REVISION */Q/* and any joining instances will verify their GMDB$K_MIN_REV against the GMDB */Q/* revision. Any compatible change to the GMDB will bump the revision, and any */N/* incompatible change will also bump the minimum revision. */N/* Each Galaxy instance has a major and minor version, which will be use d */N/* during the join decision. */N/* */N#define GMDB$K_PATTERN_L 1481393956 /* string "$GLX" */N#define GMDB$K_PATTERN_H 1111772487 /* string "GMDB" */I/* GMDB Revision Matrix: */I/* --------------------- */?/* Current Rev: Compatible  with: Comment: */./* 1.0 1.0 Initial Galaxy Implementation */N/* */N#define GMDB$K_REV_MAJ 1 /* major GMDB revision */N#define GMDB$K_REV_MIN 0 /* minor GMDB revision */N#define GMDB$K_REV1 1 /* initial Galaxy V1.0 */I/* Galaxy Version Matrix: */I/* ------------------- --- */@/* Current Vers: Compatible with: Comment: */./* 1.0 1.0 Initial Galaxy Implementation */N/* */N#define GLX$K_VERS_MAJ 1 /* Major Galaxy version */N#define GLX$K_VERS_MIN 0 /* Minor Galaxy version */N#define GLX$K_MIN_ALLOWED_MAJ 1 /* minimum Galaxy version allowed */N#define GLX$K_MIN_ ALLOWED_MIN 0 /* minimum Galaxy version allowed */#define GMDB$M_GLOCK 0x1#define GMDB$M_SHMEM 0x2#define GMDB$M_CPUCOM 0x4#define GMDB$M_CPUINFO 0x8#define GMDB$M_MEMBER 0x10'#define GMDB$M_RESERVED_5_31 0xFFFFFFE0R#define GMDB$C_LENGTH 8192 /* length of fixed-size portion of GMDB */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignme nt#endiftypedef struct _gmdb {N/* Galaxy Management Database Header */N/* */N/* This is the fixed-length portion of the GMDB header. The rest */N/* of the header (the variable-length portion) is allocated immediately */N/* following this portion from a single PFN allocation. */N/*  */N/* The total size of the header is the sum of the following rounded up */N/* to the nearest full page: */N/* */4/* GMDB$C_LENGTH - fixed length portion */G/* MAX_NODES * NODEB$C_LENGTH - node block array */M/* 1 * padTo128(exe$cbb_get_size(MAX_NODES)) - membership bit mask CBB */N/*  */N/* */#pragma __nomember_alignmentN unsigned __int64 gmdb$q_pattern; /* GMDB Pattern */N/* New Standard VMS type/subtype word at offset 8 */R unsigned short int gmdb$w_mbo; /* Must be one: implies quad size field */N unsigned char gmdb$b_type; /* Dynamic structure type */N unsigned char gmdb$b_subtype; /* Dynamic structure subtype */ char gmdb$b_fill_0_ [4]; N unsigned __int64 gmdb$q_base_size; /* size of gmdb base section */N unsigned __int64 gmdb$q_total_size; /* size of entire gmdb */N/* GMDB lock quadword - synchronize access to GMDB - uses special acquire */;/* and release that verify node heartbeat to break */;/* lock held by a crashed node. */N/*  */ GMDB_LOCK gmdb$r_lock;N unsigned int gmdb$l_spares_0 [6]; /* pad to next 64-byte boundary */ __union {N unsigned __int64 gmdb$q_revision; /* GMDB Revision */ __struct {/ unsigned int gmdb$l_revision_minor;/ unsigned int gmdb$l_revision_major;% } gmdb$r_revision_fields;" } gmdb$r_revision_overlay;N/* The following operational version fields are filled in by looking at the */Q/* Galaxy version field of all members. The lowest version becomes the current */R/* minimum operational version, and the highest the maximum operational version */N/* The minimum version allowed is needed during the join decision to figure */N/* out if an instance can join an existing Galaxy or not. */N/* */ __union {N unsigned __int64 gmdb$q_min_vers_operational; /* min Galaxy version */ __stru ct {2 unsigned int gmdb$l_min_vers_op_minor;2 unsigned int gmdb$l_min_vers_op_major;( } gmdb$r_min_vers_op_fields;% } gmdb$r_min_vers_op_overlay; __union {N unsigned __int64 gmdb$q_max_vers_operational; /* max Galaxy version */ __struct {2 unsigned int gmdb$l_max_vers_op_minor;2 unsigned int gmdb$l_max_vers_op_major;( } gmdb$r_max_vers_op_fields;% } gmdb$r_max_vers_op_overlay; __un ion {R unsigned __int64 gmdb$q_min_vers_allowed; /* min Galaxy version allowed */ __struct {7 unsigned int gmdb$l_min_vers_allowed_minor;7 unsigned int gmdb$l_min_vers_allowed_major;- } gmdb$r_min_vers_allowed_fields;* } gmdb$r_min_vers_allowed_overlay;N/* */N/* Offset-length pairs for sub-facility specific segments */N/*  */N unsigned __int64 gmdb$q_nodeb_off; /* offset to node block array */N unsigned __int64 gmdb$q_nodeb_size; /* nodeblock size */T unsigned __int64 gmdb$q_mmask_off; /* offset to galaxy membership mask (CBB) */N unsigned __int64 gmdb$q_mmask_len; /* membership mask length */N unsigned __int64 gmdb$q_glock_off; /* offset to galaxy locks segment */N unsigned __int64 gmdb$q_glock_len; /* galaxy locks segment length */N unsigned __int64 gmdb$q_shmem_off; /* offset to shared memory segment */N unsigned __int64 gmdb$q_shmem_len; /* shared memory segment length */R unsigned __int64 gmdb$q_cpucom_off; /* offset to cpu communications segment */O unsigned __int64 gmdb$q_cpucom_len; /* cpu communications segment length */P unsigned __int64 gmdb$q_cpuinfo_off; /* offset to cpu information segment */N unsigned __int64 gmdb$q_cpuinfo_len; /* cpu information segment length */U unsigned __int64 gmdb$q_member_off; /* (reserved) offset to membership segment */R unsigned __int64 gmdb$q_member_len; /* (reserved) membership segment length */N unsigned int gmdb$l_spares_1 [76]; /* pad to next 512-byte boundary */N/* */N MMAP gmdb$r_mmap; /* MMAP for the rest of the GMDB */ N unsigned int gmdb$l_fill_1; /* unused field  */N unsigned int gmdb$l_max_node_id; /* maximum node_id this platform */S unsigned int gmdb$l_break_owner; /* node holding lock while it was broken */N unsigned int gmdb$l_breaker_id; /* node breaking lock */N __int64 gmdb$q_incarnation; /* galaxy incarnation count */N unsigned __int64 gmdb$q_time; /* galaxy creation time (systime) */N unsigned __int64 gmdb$q_died_time; /* systime galaxy died */N unsigned int gmdb$l_state; /* galaxy state */Q unsigned int gmdb$l_node_timeout; /* time in msecs. to call a node dead. */O unsigned int gmdb$l_creator_node; /* creator node for this incarnation */S unsigned int gmdb$l_remover_node; /* node_id of node removing dead members */R unsigned int gmdb$l_last_joiner; /* node_id of last node to join galaxy. */S unsigned int gmdb$l_last_leaver; /* node_id of last node to leave galaxy. */ V unsigned __int64 gmdb$q_to_remove_off; /* offset to list of nodes to be removed */N unsigned int gmdb$l_crash_node; /* node_id of node requesting crash */N unsigned int gmdb$l_crash_reason; /* reason for crash_all_nodes */O unsigned int gmdb$l_reform_node; /* node_id of node requesting reform */N unsigned int gmdb$l_reform_reason; /* reason for reform */Q unsigned int gmdb$l_valid_node; /* node_id of node requesting validate */N unsigned int gmdb$l_ valid_reason; /* reason for validate */P unsigned __int64 gmdb$q_remove_time; /* start time of most recent removal */U unsigned int gmdb$l_being_removed; /* node_id of node currently being removed */O unsigned int gmdb$l_last_member; /* node_id of last node out when the */N/* galaxy died */ __union {% unsigned int gmdb$l_subvlong; __struct {& unsigned gmdb$v_glock : 1;&  unsigned gmdb$v_shmem : 1;' unsigned gmdb$v_cpucom : 1;( unsigned gmdb$v_cpuinfo : 1;' unsigned gmdb$v_member : 1;/ unsigned gmdb$v_reserved_5_31 : 27; } gmdb$r_subvdone; } gmdb$r_subfac_valid;N/* */N/* This is the end of the fixed-length portion of the gmdb header. */N/* Following this are structures whose size depends on the  */N/* maximum number of galaxy nodes allowed for a particular platform. */N/* */N/* Offsets to these (from the base of the fixed length portion) are */N/* stored in the fixed length portion. */N/* */A/* nodeb array of node blocks */N/*   */B/* members galaxy members */D/* crash_ack members who've confirmed crash (or in node block) */I/* validate_done members who've finished validate (or in node block) */N/* */N/* The sub-facility specific portions comprising the rest of the GMDB are */N/* allocated in segments of page granularity and have offsets stored in !*/N/* the gmdb */N/* */N/* */N/* The fixed-length portion of the header ends on a page boundary */N/* */N unsigned int gmdb$l_spares_3 [1875]; /* pad to next page boundary */ } GMDB; #if "!defined(__VAXC)?#define gmdb$q_revision gmdb$r_revision_overlay.gmdb$q_revisionb#define gmdb$l_revision_minor gmdb$r_revision_overlay.gmdb$r_revision_fields.gmdb$l_revision_minorb#define gmdb$l_revision_major gmdb$r_revision_overlay.gmdb$r_revision_fields.gmdb$l_revision_majorZ#define gmdb$q_min_vers_operational gmdb$r_min_vers_op_overlay.gmdb$q_min_vers_operationaln#define gmdb$l_min_vers_op_minor gmdb$r_min_vers_op_overlay.gmdb$r_min_vers_op_fields.gmdb$l_min_vers_op_minorn#define gmdb$l_min#_vers_op_major gmdb$r_min_vers_op_overlay.gmdb$r_min_vers_op_fields.gmdb$l_min_vers_op_majorZ#define gmdb$q_max_vers_operational gmdb$r_max_vers_op_overlay.gmdb$q_max_vers_operationaln#define gmdb$l_max_vers_op_minor gmdb$r_max_vers_op_overlay.gmdb$r_max_vers_op_fields.gmdb$l_max_vers_op_minorn#define gmdb$l_max_vers_op_major gmdb$r_max_vers_op_overlay.gmdb$r_max_vers_op_fields.gmdb$l_max_vers_op_majorW#define gmdb$q_min_vers_allowed gmdb$r_min_vers_allowed_overlay.gmdb$q_min_vers_allowed#defin$e gmdb$l_min_vers_allowed_minor gmdb$r_min_vers_allowed_overlay.gmdb$r_min_vers_allowed_fields.gmdb$l_min_vers_allowed_minor#define gmdb$l_min_vers_allowed_major gmdb$r_min_vers_allowed_overlay.gmdb$r_min_vers_allowed_fields.gmdb$l_min_vers_allowed_major;#define gmdb$l_subvlong gmdb$r_subfac_valid.gmdb$l_subvlongE#define gmdb$v_glock gmdb$r_subfac_valid.gmdb$r_subvdone.gmdb$v_glockE#define gmdb$v_shmem gmdb$r_subfac_valid.gmdb$r_subvdone.gmdb$v_shmemG#define gmdb$v_cpucom gmdb$r_subfac_valid. %gmdb$r_subvdone.gmdb$v_cpucomI#define gmdb$v_cpuinfo gmdb$r_subfac_valid.gmdb$r_subvdone.gmdb$v_cpuinfoG#define gmdb$v_member gmdb$r_subfac_valid.gmdb$r_subvdone.gmdb$v_memberU#define gmdb$v_reserved_5_31 gmdb$r_subfac_valid.gmdb$r_subvdone.gmdb$v_reserved_5_31"#endif /* #if !defined(__VAXC) */ #define GLXINT$M_BUGCHECK 0x1"#define GLXINT$M_MEMBER_CHANGE 0x2"#define GLXINT$M_NODE_CRASHING 0x4$#define GLXINT$M_CRASH_ALL_NODES 0x8"#define GLXINT$M_NODE_LEAVING 0x10$#define GLXINT$M_V&ALIDATE_START 0x20##define GLXINT$M_VALIDATE_DONE 0x40##define GLXINT$M_REFORM_GALAXY 0x80$#define GLXINT$M_REFORM_REJOIN 0x100##define GLXINT$M_WRITABLE_PFN 0x200$#define GLXINT$M_CHECK_PROCESS 0x400&#define GLXINT$M_RELEASE_WAITERS 0x800&#define GLXINT$M_SHM_REG_ATTACH 0x1000&#define GLXINT$M_SHM_REG_DETACH 0x2000"#define GLXINT$M_SMCI_WORKQ 0x4000!#define GLXINT$M_SMLAN_INT 0x8000##define GLXINT$M_MCHECK_REQ 0x10000*#define GLXINT$M_RESERVED_17_31 0xFFFE0000(#define GLXINT$M_PACKE 'T_SENT 0x1000000002#define GLXINT$M_RESERVED_33_63 0xFFFFFFFE00000000P#define NODEB$C_MAX_WATCH_INDEX 4 /* watch heartbeat of at most 5 nodes */N#define NODEB$C_LENGTH 512 /* node block size */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endiftypedef struct _nodeb {#pragma __nomember_alignmentN unsigned __int64 n(odeb$q_heartbeat; /* this node's heartbeat */N/* New Standard VMS type/subtype word at offset 8 */R unsigned short int nodeb$w_mbo; /* Must be one: implies quad size field */N unsigned char nodeb$b_type; /* Dynamic structure type */N unsigned char nodeb$b_subtype; /* Dynamic structure subtype */N unsigned int nodeb$l_state; /* node's current state */N unsigned __int64 nodeb$q_size; /* s )ize of nodeblock */ __union {N unsigned __int64 nodeb$q_version; /* instance version */ __struct {/ unsigned int nodeb$l_version_minor;/ unsigned int nodeb$l_version_major;% } nodeb$r_version_fields;" } nodeb$r_version_overlay; __union {S unsigned __int64 nodeb$q_min_vers_allowed; /* min Galaxy version allowed */ __struct {8 unsigned int nodeb$l_min_vers_allowed_mi *nor;8 unsigned int nodeb$l_min_vers_allowed_major;. } nodeb$r_min_vers_allowed_fields;+ } nodeb$r_min_vers_allowed_overlay; P __union { /* galaxy primitive IP-interrupt mask */- unsigned __int64 glxint$q_whole_mask; __struct {N unsigned glxint$v_bugcheck : 1; /* immediate bugcheck - 0 */N unsigned glxint$v_member_change : 1; /* membership changed - 1 */O unsigned glxint$v_no+de_crashing : 1; /* sender node crashing - 2 */S unsigned glxint$v_crash_all_nodes : 1; /* crash all galaxy nodes - 3 */N unsigned glxint$v_node_leaving : 1; /* node leaving galaxy - 4 */S unsigned glxint$v_validate_start : 1; /* start galaxy validation - 5 */O unsigned glxint$v_validate_done : 1; /* validation completed - 6 */V unsigned glxint$v_reform_galaxy : 1; /* initiate galaxy reformation - 7 */Y unsigned glxint$v_refo,rm_rejoin : 1; /* reform: nodes down, rejoin now - 8 */X unsigned glxint$v_writable_pfn : 1; /* sender has writable remote PFN - 9 */S unsigned glxint$v_check_process : 1; /* check process existence - 10 */S unsigned glxint$v_release_waiters : 1; /* release glock waiters - 11 */Z unsigned glxint$v_shm_reg_attach : 1; /* node is attaching to a region - 12 */\ unsigned glxint$v_shm_reg_detach : 1; /* node is detaching from a region - 13 */Q - unsigned glxint$v_smci_workq : 1; /* process SMCI Work Queues - 14 */P unsigned glxint$v_smlan_int : 1; /* process SMLAN interrupts - 15 */V unsigned glxint$v_mcheck_req : 1; /* process machine check request - 16 */2 unsigned glxint$v_reserved_17_31 : 15;T unsigned glxint$v_packet_sent : 1; /* packet queued notification - 32 */2 unsigned glxint$v_reserved_33_63 : 31; } nodeb$r_bits; } nodeb$r_prim_int_u;O. unsigned __int64 nodeb$q_time; /* time node joined galaxy (systime) */P unsigned __int64 nodeb$q_leaving_time; /* time node left galaxy (systime) */N unsigned __int64 nodeb$q_name; /* node's SCS node name */N __int64 nodeb$q_incarnation; /* node joined galaxy count */N unsigned int nodeb$l_was_creator; /* TRUE if this node created galaxy */N unsigned int nodeb$l_nval_done; /* node validation done */N unsigned int nodeb/$l_crash_ack; /* node crash_all acknowledge */O unsigned int nodeb$l_reform_done; /* node reform done; ready to rejoin */N int nodeb$l_crash_reason; /* bugcheck code for local crash */N int nodeb$l_crash_status; /* system status code that caused */N/* Galaxy code to decide to crash */N/* with GLXFATAL */N unsigned int nodeb$l_fill_2; /* unu0sed field */S unsigned int nodeb$l_lbrother; /* little brother (watched by this node) */Q unsigned int nodeb$l_bbrother; /* big brother (who watches this node) */O unsigned int nodeb$l_last_watched; /* last valid entry in watched_nodes */ __struct {N unsigned int nodeb$l_node_id; /* node_id of node to watch */S unsigned int nodeb$l_miss_count; /* consecutive no-increase observations */Q unsigned __int64 nodeb$q_las 1t_heartbeat; /* heartbeat last observation */$ } nodeb$r_watched_nodes [5];N unsigned int nodeb$l_spares_0 [14]; /* pad to next 128-byte boundary */W unsigned __int64 nodeb$q_crash_time; /* timestamp, when crash reason was written */N unsigned int nodeb$l_spares [62]; /* pad to next 512-byte boundary */ } NODEB; #if !defined(__VAXC)?#define nodeb$q_version nodeb$r_version_overlay.nodeb$q_versionb#define nodeb$l_version_minor nodeb$r_version_overlay.nodeb$r_ve2rsion_fields.nodeb$l_version_minorb#define nodeb$l_version_major nodeb$r_version_overlay.nodeb$r_version_fields.nodeb$l_version_majorZ#define nodeb$q_min_vers_allowed nodeb$r_min_vers_allowed_overlay.nodeb$q_min_vers_allowed#define nodeb$l_min_vers_allowed_minor nodeb$r_min_vers_allowed_overlay.nodeb$r_min_vers_allowed_fields.nodeb$l_min_vers_allowed_mi\nor#define nodeb$l_min_vers_allowed_major nodeb$r_min_vers_allowed_overlay.nodeb$r_min_vers_allowed_fields.nodeb$l_min_vers_allowed_ma\jor3B#define glxint$q_whole_mask nodeb$r_prim_int_u.glxint$q_whole_maskK#define glxint$v_bugcheck nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_bugcheckU#define glxint$v_member_change nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_member_changeU#define glxint$v_node_crashing nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_node_crashingY#define glxint$v_crash_all_nodes nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_crash_all_nodesS#define glxint$v_node_leaving nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_node_leavingW#def4ine glxint$v_validate_start nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_validate_startU#define glxint$v_validate_done nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_validate_doneU#define glxint$v_reform_galaxy nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_reform_galaxyU#define glxint$v_reform_rejoin nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_reform_rejoinS#define glxint$v_writable_pfn nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_writable_pfnU#define glxint$v_check_process nodeb$r_prim_int_u.nodeb$r_bits.glxint$5v_check_processY#define glxint$v_release_waiters nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_release_waitersW#define glxint$v_shm_reg_attach nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_shm_reg_attachW#define glxint$v_shm_reg_detach nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_shm_reg_detachO#define glxint$v_smci_workq nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_smci_workqM#define glxint$v_smlan_int nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_smlan_intO#define glxint$v_mcheck_req nodeb$r_prim_int_u.nodeb$r 6_bits.glxint$v_mcheck_reqW#define glxint$v_reserved_17_31 nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_reserved_17_31Q#define glxint$v_packet_sent nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_packet_sentW#define glxint$v_reserved_33_63 nodeb$r_prim_int_u.nodeb$r_bits.glxint$v_reserved_33_63'#define nodeb$l_node_id nodeb$l_node_id-#define nodeb$l_miss_count nodeb$l_miss_count5#define nodeb$q_last_heartbeat nodeb$q_last_heartbeat"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER7_SIZEL #pragma __required_pointer_size __save /* Save current pointer size */G #pragma __required_pointer_size __long /* Pointers are 64-bit */E typedef GMDB *GMDB_PQ; /* Long pointer to a GMDB structure. */W typedef GMDB **GMDB_PPQ; /* Long pointer to a long pointer to a GMDB structure. */L typedef NODEB *NODEB_PQ; /* Long pointer to a node block structure. */T typedef NODEB **NODEB_PPQ; /* Long pointer to a long pointer to a node block. */K typedef GMDB_LOCK 8 *GMDB_LOCK_PQ; /* Long pointer to the gmdb_lock. */T #pragma __required_pointer_size __restore /* Return to previous pointer size */#else$ typedef unsigned __int64 GMDB_PQ;% typedef unsigned __int64 GMDB_PPQ;% typedef unsigned __int64 NODEB_PQ;& typedef unsigned __int64 NODEB_PPQ;) typedef unsigned __int64 GMDB_LOCK_PQ;##endif /* __INITIAL_POINTER_SIZE */J#define GMDB$K_PATTERN ((GMDB$K_PATTERN_H*0x100000000) + GMDB$K_PATTERN_L)H#define GMDB$K_REVISION ((GMDB$K_REV_ 9MAJ*0x100000000) + GMDB$K_REV_MIN)F#define GLX$K_VERSION ((GLX$K_VERS_MAJ*0x100000000) + GLX$K_VERS_MIN)]#define GLX$K_MIN_VERS_ALLOWED ((GLX$K_MIN_ALLOWED_MAJ*0x100000000) + GLX$K_MIN_ALLOWED_MIN)#if MMAP$C_LENGTH > 64G#error "MMAP$C_LENGTH greater than 64, exceeds embedded space in GMDB!"#endif  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previou:sly-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __GMDBDEF_LOADED */ wwM3[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be use;d, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed< to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 =15:22:21 by OpenVMS SDL V3.7 */I/* Source: 24-AUG-2022 15:00:57 $1$DGA8345:[LIB_H.SRC]GPSCFGDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $GPSCFGDEF ***/#ifndef __GPSCFGDEF_LOADED#define __GPSCFGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_S>IZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#els?e#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/************************************************ */N/* CONSTANTS AND ENUMERATIONS */N/************************************************ */N/* */N/* D @iscoverable SBA Objects */N/* ------------------------ */N/* */#define GPS$K_OBJ_GENERIC 0#define GPS$K_OBJ_SYSBUS 17#define GPS$K_OBJ_PCIHOST 18#define GPS$K_OBJ_PCIDEV 19#define GPS$K_OBJ_IOPORT 20#define GPS$K_OBJ_IOPORTDEV 21#define GPS$K_OBJ_HCDPDEV 22#define GPS$K_OBJ_EMBEDDED 23#define GPS$K_OBJ_IOC 24 A#define GPS$K_OBJ_SYSBUSLESS 25#define GPS$K_OBJ_ROOT 26#define GPS$K_OBJ_CONTAINER 27#define GPS$K_OBJ_GPEDEV 28#define GPS$K_OBJ_VMBUSHOST 29N/* */N/* Address Spaces */N/* -------------- */N/* See Generic Address Specification (GAS) in ACPI 2.0a Spec. */N/* B */#define GPS$K_SPACE_SYSMEM 0#define GPS$K_SPACE_SYSIO 1#define GPS$K_SPACE_PCICFG 2#define GPS$K_SPACE_EMBEDDED 3#define GPS$K_SPACE_SMB 4#define GPS$K_SPACE_FIXEDHW 127N/* */N/* */N/************************************************ */N/* DATA STRUCTURES C */N/************************************************ */N/* */N/* PRT - PCI Routing Table */N/* ----------------------- */N/* The PRT provides the information required to locate the interrupt */N/* wire for the corresponding PCI device. D */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpsprtentry {#pragma __nomember_alignment( unsigned int gps_prt$l_entry_length; unsigned int gps_prt$l_pin;' unsigned __int64 gps_prt$q_address;( unsigned int gps_prt$l_sou Erce_index; char gps_prt$b_fill_0_ [4]; } GPSPRTENTRY;#define GPS$K_PRT_LENGTH 24N/* */N/* */N/* GPS DESCRIPTOR */N/* -------------- */N/* */ c#if !d Fefined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpsdescriptor {#pragma __nomember_alignmentN unsigned int gps_dsc$l_type; /* See ACPI OBJECT Types above */N unsigned int gps_dsc$l_size; /* Size in bytes of the data object */ __union {N unsigned __int64 gps_dsc$q_data; /* for GPS$K_OBJ_TYPE_INTEGER */N G char *gps_dsc$ps_data; /* for types other than INTEGER */! } gps_dsc$r_data_overlay; } GPSDESCRIPTOR; #if !defined(__VAXC)<#define gps_dsc$q_data gps_dsc$r_data_overlay.gps_dsc$q_data>#define gps_dsc$ps_data gps_dsc$r_data_overlay.gps_dsc$ps_data"#endif /* #if !defined(__VAXC) */ N/* */N/* GPS Header */N/* ---------- H */N/* This structure is common to all GPSCONFIG type structures and */N/* contains the fields necessary to extract more information about */N/* the object from ACPI. Also contains fields that are common to */N/* most hardware objects. */N/* */#define GPS_HDR$M_VALID_STA 0x1#define GPIS_HDR$M_VALID_ADR 0x2#define GPS_HDR$M_VALID_HID 0x4#define GPS_HDR$M_VALID_UID 0x8#define GPS_HDR$M_RESRV_0 0x10 #define GPS_HDR$M_VALID_CID 0x20 #define GPS_HDR$M_VALID_CLS 0x40#define GPS_HDR$M_RESRV_1 0x80"#define GPS_HDR$M_VALID_SXDS 0x100"#define GPS_HDR$M_VALID_SXWS 0x200!#define GPS_HDR$M_VALID_BBN 0x400!#define GPS_HDR$M_VALID_SEG 0x800 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __q Juadword#else#pragma __nomember_alignment#endiftypedef struct _gpsheader {#pragma __nomember_alignmentN int gps_hdr$l_status; /* Callback Status */N __union { /* Mask identifying valid fields */% unsigned int gps_hdr$l_valid; __struct {N unsigned gps_hdr$v_valid_sta : 1; /* These masks track the */N unsigned gps_hdr$v_valid_adr : 1; /* : corresponding ones in */N K unsigned gps_hdr$v_valid_hid : 1; /* : [ACPI]ACTYPES.H */- unsigned gps_hdr$v_valid_uid : 1;+ unsigned gps_hdr$v_resrv_0 : 1;- unsigned gps_hdr$v_valid_cid : 1;- unsigned gps_hdr$v_valid_cls : 1;+ unsigned gps_hdr$v_resrv_1 : 1;. unsigned gps_hdr$v_valid_sxds : 1;. unsigned gps_hdr$v_valid_sxws : 1;- unsigned gps_hdr$v_valid_bbn : 1;- unsigned gps_hdr$v_valid_seg : 1;+ L unsigned gps_hdr$v_fill_1_ : 4; } gps_hdr$r_bits;" } gps_hdr$r_valid_overlay;N unsigned __int64 gps_hdr$q_type; /* Object type */N unsigned __int64 gps_hdr$q_hw_handle; /* Object's hardware handle */N unsigned __int64 gps_hdr$q_parent; /* hw_handle of object's parent */N/* */N/* ACPI 2.0a spec section */MN/* ---------------------- */N unsigned __int64 gps_hdr$q_adr; /* _ADR 6.1.1 */N GPSDESCRIPTOR gps_hdr$r_cid; /* _CID 6.1.2 */N GPSDESCRIPTOR gps_hdr$r_hid; /* _HID 6.1.4 */N GPSDESCRIPTOR gps_hdr$r_uid; /* _UID 6.1.7 */N unsigned __int64 gps_hdr$q_sta; /* _STA 6.3.6, 7.1.4 */N unsigned __int64 gps N_hdr$q_bbn; /* _BBN 6.5.6 (Base Bus Number) */N unsigned __int64 gps_hdr$q_seg; /* _SEG 6.5.6 */ } GPSHEADER; #if !defined(__VAXC)?#define gps_hdr$l_valid gps_hdr$r_valid_overlay.gps_hdr$l_validV#define gps_hdr$v_valid_sta gps_hdr$r_valid_overlay.gps_hdr$r_bits.gps_hdr$v_valid_staV#define gps_hdr$v_valid_adr gps_hdr$r_valid_overlay.gps_hdr$r_bits.gps_hdr$v_valid_adrV#define gps_hdr$v_valid_hid gps_hdr$r_valid_overlay.gps_hdr$r_bits.gps_hdr$v_valid_hOidV#define gps_hdr$v_valid_uid gps_hdr$r_valid_overlay.gps_hdr$r_bits.gps_hdr$v_valid_uidR#define gps_hdr$v_resrv_0 gps_hdr$r_valid_overlay.gps_hdr$r_bits.gps_hdr$v_resrv_0V#define gps_hdr$v_valid_cid gps_hdr$r_valid_overlay.gps_hdr$r_bits.gps_hdr$v_valid_cidV#define gps_hdr$v_valid_cls gps_hdr$r_valid_overlay.gps_hdr$r_bits.gps_hdr$v_valid_clsR#define gps_hdr$v_resrv_1 gps_hdr$r_valid_overlay.gps_hdr$r_bits.gps_hdr$v_resrv_1X#define gps_hdr$v_valid_sxds gps_hdr$r_valid_overlay.gps_hdr$r_bits.gp Ps_hdr$v_valid_sxdsX#define gps_hdr$v_valid_sxws gps_hdr$r_valid_overlay.gps_hdr$r_bits.gps_hdr$v_valid_sxwsV#define gps_hdr$v_valid_bbn gps_hdr$r_valid_overlay.gps_hdr$r_bits.gps_hdr$v_valid_bbnV#define gps_hdr$v_valid_seg gps_hdr$r_valid_overlay.gps_hdr$r_bits.gps_hdr$v_valid_seg"#endif /* #if !defined(__VAXC) */ #define GPS$K_HDR_LENGTH 112N/* */N/* GPS System Bus Object Q */N/* --------------------- */N/* Information reported upon the discovery of a system-level bus. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpssysbus {#pragma __nomember_alignmentO R unsigned __int64 gps_sb$q_dma_base; /* Base Address of system DMA window */N unsigned __int64 gps_sb$q_dma_max; /* Max Address of system DMA window */N int gps_sb$l_node_count; /* Number of child nodes */N int gps_sb$l_reserved; /* Pad */N unsigned __int64 gps_sb$q_ioc_base; /* Base Phys addr of IOC registers */S unsigned __int64 gps_sb$q_tra_offset; /* System access translation PA offset */ } GPSSYSBUS;#dSefine GPS$K_SB_LENGTH 40N/* */N/* GPS PCI Host Object */N/* ------------------- */N/* Information reported upon the discovery of a PCI bus host. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using Tpre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpspcihost {#pragma __nomember_alignmentN unsigned __int64 gps_pci$q_base_pa; /* Base Phys addr of this PCI space */N unsigned __int64 gps_pci$q_max_pa; /* Max Phys addr of this PCI space */P unsigned __int64 gps_pci$q_prt_addr; /* VMS System VA of PRT for this bus */N unsigned __int64 gps_pci$q_prt_length; /* Length of the whole PRT */N int gpUs_pci$l_bus; /* Bus Number of this PCI host bus */R int gps_pci$l_seg; /* Segment in which the PCI bus resides */^ unsigned __int64 gps_pci$q_tra_offset; /* System access translation PA offset (per bus) */b unsigned __int64 gps_pci$q_tra_portio; /* Translation PA offset to port I/O space (per bus) */ } GPSPCIHOST;#define GPS$K_PCI_LENGTH 56N/* */N/* GPS PCI Device Object V */N/* --------------------- */N/* Information reported upon the discovery of a PCI device. */N/* */N/* NOTE: ACPI does not report PCI devices, since there is an Industry */N/* Standard probing algorithm for PCI device discovery. This */N/* structure is more for informational purpose Ws or for the unlikely */N/* case of non-ACPI device discovery and reporting mechanisms. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpspcidev {#pragma __nomember_alignmentS unsigned __int64 gps_pcidev$q_ioapic; /* VMS System VA of ACXPI IOAPIC struct */N unsigned __int64 gps_pcidev$q_address; /* PCI config address */P int gps_pcidev$l_bus; /* Bus upon which this device appears */N int gps_pcidev$l_seg; /* Segment of device's bus */N unsigned int gps_pcidev$l_gsin; /* Global System Interrupt Number */N int gps_pcidev$l_polarity; /* Interrupt Polarity */N int gps_pcidev$l_trig_mode; /* Interrupt Trigger Mode */" Y char gps_pcidev$b_fill_2_ [4]; } GPSPCIDEV;#define GPS$K_PCIDEV_LENGTH 40N/* */N/* GPS IO Port Object */N/* ------------------ */N/* Information reported upon the discovery of an IO Port Space. */N/* */ c#if !defined(__NOB ZASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpsioport {#pragma __nomember_alignmentN unsigned __int64 gps_iop$q_base_pa; /* Base Phys Addr of Port IO Space */N int gps_iop$l_swizzle; /* Number of bits to shift */N int gps_iop$l_stride; /* "Sparseness" of Port IO Space */ } GPSIOPORT;#define GPS$K_IO[P_LENGTH 16N/* */N/* GPS IO Port Device */N/* ------------------ */N/* Information reported upon the discovery of an IO Port Device. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4. \0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpsportdev {#pragma __nomember_alignmentS unsigned __int64 gps_iopdev$q_ioapic; /* VMS System VA of ACPI IOAPIC struct */N unsigned __int64 gps_iopdev$q_csr_pa; /* CSR Physical Address */N unsigned int gps_iopdev$l_gsin; /* Global System Interrupt Number */N int gps_iopdev$l_polarity; /* Interrupt Polarity */N int gps_iopdev ]$l_trig_mode; /* Interrupt Trigger Mode */" char gps_iopdev$b_fill_3_ [4]; } GPSPORTDEV;#define GPS$K_IOPDEV_LENGTH 32N/* */N/* GPS IO Embedded Device */N/* ---------------------- */N/* Information reported upon the discovery of an Embedded Device. */N/* ^ */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpsembdev {#pragma __nomember_alignmentQ unsigned __int64 gps_emb$q_ioapic; /* VMS System VA of ACPI IOAPIC struct */N unsigned __int64 gps_emb$q_csr_pa; /* CSR Physical Address */N int gps_emb$l_space; /* T _ype of Address Space */N unsigned int gps_emb$l_gsin; /* Global System Interrupt Number */N int gps_emb$l_polarity; /* Interrupt Polarity */N int gps_emb$l_trig_mode; /* Interrupt Trigger Mode */ } GPSEMBDEV;#define GPS$K_EMB_LENGTH 32N/* */N/* GPS IOC Object */N/* ------------------- `-- */N/* Information reported upon the discovery of an IOC which is separate */N/* from its system bus. HWP0004 for example. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct a _gpsioc {#pragma __nomember_alignmentN unsigned __int64 gps_ioc$q_ioc_base; /* Base Phys addr of IOC registers */T unsigned __int64 gps_ioc$q_tra_offset; /* System access translation PA offset */ } GPSIOC;#define GPS$K_IOC_LENGTH 16N/* */N/* GPS ROOT Object */N/* --------------------- */N/* Informati bon reported upon the discovery of the root node. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpsroot {#pragma __nomember_alignmentN unsigned __int64 gps_root$q_reserved_1; /* Reserved */N unsigned __int64 gps_r coot$q_reserved_2; /* Reserved */ } GPSROOT;#define GPS$K_ROOT_LENGTH 16N/* */N/* GPS CONTAIN Object */N/* --------------------- */N/* Information reported upon the discovery of a container node. */N/* */ c#i df !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpscontain {#pragma __nomember_alignmentN unsigned __int64 gps_contain$q_reserved_1; /* Reserved */N unsigned __int64 gps_contain$q_reserved_2; /* Reserved */ } GPSCONTAIN;#define GPS$K_CONTAIN_LENGTH 16N/* e */N/* GPS SPCR Object */N/* --------------------- */N/* Information reported upon the discovery of a SPCR table */N/* Defined as DIG64 Rev 5 Table, backwards compatible with Rev 4. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* f If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _gpsspmi {#pragma __nomember_alignmentN unsigned char gps_spmi$b_interface_type; /* Interface type */N unsigned char gps_spmi$b_ipmi; /* Indicates IPMI enabled */N unsigned short int gps_spmi$w_spec_revision; /* Rev of pertinent spec */N unsigned char gps_spmi$b_interrupt_type; /* Interrupt type */N gunsigned char gps_spmi$b_gpe; /* GPE block number */N unsigned char gps_spmi$b_reserved_0; /* reserved */N unsigned char gps_spmi$b_pci_device_flag; /* PCI Device Flag */N unsigned int gps_spmi$l_gsin; /* Global System Interrupt */N unsigned char gps_spmi$b_address_space_id; /* Part of ACPI GAS struct */N unsigned char gps_spmi$b_register_bit_width; /* Part of ACPI GAS struct */O unsigned char gps_spmi$b_rhegister_bit_offset; /* Part of ACPI GAS struct */N unsigned char gps_spmi$b_address_size; /* Part of ACPI GAS struct */N unsigned __int64 gps_spmi$q_base_address; /* Part of ACPI GAS struct */N unsigned char gps_spmi$b_pci_seg; /* PCI ident */N unsigned char gps_spmi$b_pci_bus; /* PCI ident */N unsigned char gps_spmi$b_pci_device; /* PCI ident */N unsigned char gps_spmi$b_pci_function; /* PCI iden it */N unsigned char gps_spmi$b_reserved_1; /* Reserved for compatibility */ char gps_spmi$b_fill_4_ [3]; } GPSSPMI;#define GPS$K_SPMI_LENGTH 32N/* */N/* GPS CPU Object */N/* --------------------- */N/* Information reported upon the discovery of a processor object. */N j/* */#define GPS_CPU$M_ENABLED 0x1#define GPS_CPU$M_RESERVED 0xFE c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpscpudev {#pragma __nomember_alignmentN unsigned __int64 gps_cpu$q_lid; /* Local ID */N unsigned int gps_cpu$lk_procid; /* ACPI Processor ID */N __union { /* Processor flags */& unsigned char gps_cpu$b_flags; __struct {+ unsigned gps_cpu$v_enabled : 1;, unsigned gps_cpu$v_reserved : 7; } gps_cpu$r_bits;" } gps_cpu$r_flags_overlay;' unsigned char gps_cpu$b_reserved_0;, unsigned short int gps_cpu$w_reserved_1; } GPSCPUDEV; #if !defined(__VAXC)?#define gps_cpu$b_ lflags gps_cpu$r_flags_overlay.gps_cpu$b_flagsR#define gps_cpu$v_enabled gps_cpu$r_flags_overlay.gps_cpu$r_bits.gps_cpu$v_enabledT#define gps_cpu$v_reserved gps_cpu$r_flags_overlay.gps_cpu$r_bits.gps_cpu$v_reserved"#endif /* #if !defined(__VAXC) */ #define GPS$K_CPUDEV_LENGTH 16N/* */N/* GPS GPE Block Device */N/* -------------------- m */N/* Information reported upon the discovery of a GPE Block device */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpsgpedev {#pragma __nomember_alignmentN unsigned __int64 gps_gpe$q_hw_id; /* PNP ID string equivalent n */N unsigned __int64 gps_gpe$q_mbz; /* quadword of zeroes */N unsigned __int64 gps_gpe$q_hw_handle; /* Object's hardware handle */N unsigned __int64 gps_gpe$q_parent; /* hw_handle of object's parent */N unsigned int gps_gpe$l_gsin; /* Global System Interrupt Number */N int gps_gpe$l_int_type; /* Interrupt Type */N int gps_gpe$l_polarity; /* Interrupt Polarity */N int gps_gpoe$l_trig_mode; /* Interrupt Trigger Mode */N unsigned char gps_gpe$b_address_space_id; /* Part of ACPI GAS struct */N unsigned char gps_gpe$b_register_bit_width; /* Part of ACPI GAS struct */N unsigned char gps_gpe$b_register_bit_offset; /* Part of ACPI GAS struct */N unsigned char gps_gpe$b_access_size; /* Part of ACPI GAS struct */N unsigned __int64 gps_gpe$q_base_address; /* Part of ACPI GAS struct */ char gps_gpe$b_fill_5_ [4]; } pGPSGPEDEV;#define GPS$K_GPEDEV_LENGTH 64N/* */N/* GPS Data */N/* -------- */N/* Combine the discoverable bus objects into one union. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplqus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _gpsdata {#pragma __nomember_alignmentO GPSSYSBUS gps$r_sysbus; /* GPSSYSBUSLESS uses same structure */ GPSPCIHOST gps$r_pci_host; GPSPCIDEV gps$r_pci_dev; GPSIOPORT gps$r_io_port; GPSPORTDEV gps$r_port_dev; GPSEMBDEV gps$r_emb_dev; GPSIOC gps$r_ioc; GPSROOT gps$r_root; GPSCONTAIN gps$r_container; r GPSCPUDEV gps$r_cpu_dev; GPSGPEDEV gps$r_gpe_dev; } GPSDATA;#define GPS$K_DATA_LENGTH 64N/* */N/* GPS Config Information */N/* ---------------------- */N/* Combine the GPS Header and Data structures into one structure to be */N/* inited by ACPI calls and used by VMS IO mapping and configuring code. */sN/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpsconfig {#pragma __nomember_alignment GPSHEADER gps$r_header; GPSDATA gps$r_data; } GPSCONFIG;#define GPS$K_CONFIG_LENGTH 176N/* t */N/* GPS I/O APIC Information (x86 only) */N/* ----------------------------------- */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpsioapicinfo {#pragma __nomember_a ulignment, unsigned __int64 gps_ioapic$q_base_addr;( unsigned int gps_ioapic$l_base_gsin;" unsigned char gps_ioapic$b_id;" char gps_ioapic$b_fill_6_ [3]; } GPSIOAPICINFO;#define GPS$K_IOAPIC_LENGTH 16N/* */N/* GPS HCDP Information */N/* -------------------- */O/* This structure provides information on vthe Headless Console & Debug Port, */N/* if there is one. */N/* */#define GPS_HCDP$M_FUNCTION 0x7 #define GPS_HCDP$M_RESERVED 0x38!#define GPS_HCDP$M_INTR_FLAG 0x40"#define GPS_HCDP$M_PCI_DEVICE 0x80#define GPS_HCDP$M_CONSOLE 0x1&#define GPS_HCDP$K_TYPE_GENERIC_UART 0$#define GPS_HCDP$K_TYPE_DEBUG_PORT 1#define GPS_HCDP$K_TYPE_VGA 10&#define GPS_HCDP$K_TYPE_wFPARS_VCON 130!#define GPS_HCDP$K_VERSION_PCDP 3 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpshcdpdev {#pragma __nomember_alignment, unsigned short int gps_hcdp$w_vendor_id;, unsigned short int gps_hcdp$w_device_id;N int gps_hcdp$l_space_id; /* Type of address space */N unsigned __int64 gps_hcdxp$q_address; /* Address of the device */N unsigned int gps_hcdp$l_gsin; /* Global System Interrupt Number */N int gps_hcdp$l_polarity; /* Interrupt Polarity */N int gps_hcdp$l_trig_mode; /* Interrupt Trigger Mode */N/* */N/* X-21 20070302 TLC */N/* Changed seg field from byte to word to comply with yPCI_NODE_NUMBER */N/* and SAL. */N/* */N unsigned char gps_hcdp$b_seg; /* These fields are valid when the */N unsigned char gps_hcdp$b_bus; /* | pci_device flag bit is set */N unsigned char gps_hcdp$b_device; /* | (see function_bits below) */N/* */Nz/* X-21 20070302 TLC - Clarification */N/* The PCI Function byte in the HCDP/PCDP is overloaded with flag bits, */N/* so we break them out here so they can be easily accessed by parsing */N/* code. */N/* */ __union {N unsigned char gps_hcdp$b_function; /* whole word */ __ {struct {N unsigned gps_hcdp$v_function : 3; /* function number */- unsigned gps_hcdp$v_reserved : 3;N unsigned gps_hcdp$v_intr_flag : 1; /* supports intr if 1 */N unsigned gps_hcdp$v_pci_device : 1; /* pci_device if 1 */' } gps_hcdp$r_function_bits;& } gps_hcdp$r_function_overlay;N/* */N/* X-21 20070302 TLC | */N/* Flags */N/* */ __union {' unsigned char gps_hcdp$b_flags; __struct {N unsigned gps_hcdp$v_console : 1; /* system console flag */, unsigned gps_hcdp$v_fill_7_ : 7;# } gps_hcdp$r_flag_bits;# } gps_hcdp$r_flags_overlay;N/* } */N/* X-21 20070302 TLC */N/* Add version field to enable PLATFORM_SUPPORT to understand data */N/* in terms of whether coming from HCDP or PCDP. */N/* */P char gps_hcdp$b_version; /* Version number: HCDP = 2, PCDP = 3 */N/* ~ */N/* X-21 20070302 TLC */N/* Add type field to enable PLATFORM_SUPPORT to sort out the various */N/* console and com port device types. */N/* */N char gps_hcdp$b_type; /* HCDP/PCDP device type */N/* */N/* X-21 20070302 TLC */N/* Pad out to next quadword. */N/* */" char gps_hcdp$b_quad_fill [5];N/* */N/* X-21 20070302 TLC */N/* HCDP/PCDP Console and Debug Port type constants.  */N/* */ } GPSHCDPDEV; #if !defined(__VAXC)K#define gps_hcdp$b_function gps_hcdp$r_function_overlay.gps_hcdp$b_functiond#define gps_hcdp$v_function gps_hcdp$r_function_overlay.gps_hcdp$r_function_bits.gps_hcdp$v_functiond#define gps_hcdp$v_reserved gps_hcdp$r_function_overlay.gps_hcdp$r_function_bits.gps_hcdp$v_reservedf#define gps_hcdp$v_intr_flag gps_hcdp$r_function_overlay.gps_hcdp$r_function_bits.gps_ hcdp$v_intr_flagh#define gps_hcdp$v_pci_device gps_hcdp$r_function_overlay.gps_hcdp$r_function_bits.gps_hcdp$v_pci_deviceB#define gps_hcdp$b_flags gps_hcdp$r_flags_overlay.gps_hcdp$b_flags[#define gps_hcdp$v_console gps_hcdp$r_flags_overlay.gps_hcdp$r_flag_bits.gps_hcdp$v_console"#endif /* #if !defined(__VAXC) */ #define GPS$K_HCDP_LENGTH 40N/* */N/* GPS System Information  */N/* ---------------------- */N/* Provides information on the ACPI System. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpssysinfo {#pragma __nomember_alignment#  char gps_syi$t_vendor_name [8];) char gps_syi$t_vendor_model_name [8];0 unsigned __int64 gps_syi$q_acpi_ca_revision;/ unsigned int gps_syi$l_acpi_major_revision; char gps_syi$b_fill_8_ [4]; } GPSSYSINFO;#define GPS$K_SYSINFO_LENGTH 32N/* */N/* Generic ACPI Buffer */N/* ------------------- */ N/* For calls to acpi$osl_execute_method() that return with data type of */N/* ACPI_TYPE_BUFFER. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gpsbuffer {#pragma __nomember_alignmentN int gp s_buf$l_length; /* Length of data in bytes */N int gps_buf$l_spare1_mbz; /* Must be zeroed when created */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit poi nters */N void *gps_buf$pq_pointer; /* Pointer to data */#else% unsigned __int64 gps_buf$pq_pointer;#endif } GPSBUFFER;N/* */N/* System statistics returned by acpi$osl_get_statistics */N/* To get the entries in FixedEventCounts, */N/* acpi$osl_get_statistics fetches them via callback routines */N/* registered by prev ious calls to acpi$osl_install_fixed_handler. */N/* */ typedef struct _gpsstatistics {#pragma __nomember_alignment% unsigned int gps_sta$l_sci_count;% unsigned int gps_sta$l_gpe_count;] unsigned int gps_sta$l_fixed_event_count [5]; /* equal to acpi ACPI_NUM_FIXED_EVENTS */( unsigned int gps_sta$l_method_count; } GPSSTATISTICS;"#define GPS$K_STATISTICS_LENGTH 32N/*  */N/* Table Event handler used by acpi$osl_install_table_handler and */N/* acpi$os_remove_table_handler */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif!typedef struct _ gpstablehandler {#pragma __nomember_alignment" unsigned int gps_thdl$l_event;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif void *gps_thdl$ps_table; void *gps_thdl$ps_context; char gps_thdl$b_fill_9_ [4]; } GPSTABLEHANDLER;#define GPS$K_THDL_LENGTH 16N/* */R/* ============================================================================ */N/* SLOT OBJECT DEFINITION */R/* ============================================================================ */N/* */N/* A SLOT OBJECT is a physical connector on a backplane or motherboard into */N/* which a hardware device or adapter may be inserted. Slot Objects are */O/* tracked because it is possible for a device to be inserted into a slot in */P/* one hardware partition, while being "owned" by another hardware partition. */N/* */N/* This allows more flexibility in allocation of IO adapter resources in */N/* systems that have been partitioned. However, it is important to be able */P/* to determine whether an adapter or IO function in a slot can be configured */P/* into the current system. If the adapter or IO function is owned by another */P/* hardware partition, then the corresponding BUSARRAYENTRY in the non-owning */N/* partition must be invalidated. */N/* */N/* It is possible for a SLOT object to have another SLOT as its parent. */N/* */N/* EBA (Express Bus Agent)  */N/* HID A */N/* ADP ----+------------------+ */N/* | | */N/* SLOT SLOT */N/* HID B HID C */N/* Parent HID A Parent HID A */N/*  | | */N/* SLOT SLOT */N/* HID B1 HID C1 */N/* Parent HID B Parent HID C */N/* */N/* Since SLOT objects do not have their own ADPs, a problem ensues when */N/* trying to find the parent ADP of SLOT objects descendent from other */O/* SLOT objects, since the Parent Hardware Handle of descendent SLOT objects */R/* is that of their parent SLOT, rather than that of their ancestral Bus Agent. */R/* It is the Parent Hardware Handle of the ancestral Bus Agent that is required */N/* to locate the ADP for any given SLOT object. */N/* */N/* The following structure maps the ADP of the first-level SLOT objects */N/* of a Bus Agent (LBA, EBA, etc) with SLOT objects on descendent levels. */N/* An array of these structures is dynamicaly allocated by Bus Agents that */R/* require them. The pointer to the array will be placed in the adp$ps_devslots */N/* field of the ADP. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _devslot {#pragma __nomember_alignment) unsigned __int64 devslot$q_hw_handle;) unsigned __int64 devslot$q_parent_hh;! __int64 devslot$q_reserved_0;! __int64 devslot$q_reserved_1; } DEVSLOT;R/****************************************************************************** */N/* ACPI DATA TYPES, CONSTANTS AND ENUMERATIONS  */R/****************************************************************************** */N/* */N/* This section contains copies of the ACPI data types and definitions */N/* that must be exposed for other facilities, particularly PLATFORM_SUPPORT */N/* (aka IVMS), to use for calls into the ACPI. */N/* */N/* This section must be reviewed whenever there is a new ACPI code drop to */N/* assure proper synchronization with ACPI data types and definitions. */N/* */N/* NOTE: These definitions have been removed to prevent future backward */N/* compatibility issues with ACPI-CA updates from Intel. The file */N/* LOCALDEFS.H now imports ACPI data type definitions directly */N/* from the ACPI facility by including ACPI.H. ER - 12/16/2005 */N/* */N/* */N/* The following constant can be used to clue acpi$osl_get_crs_item that */N/* the parameter is unused or not required to fetch the item. */N/* */#define GPS$K_IGNORE -1N/*  */R/* ============================================================================ */N/* ACPI RESOURCE DEFINITIONS */R/* ============================================================================ */N/* */N/* The ACPI Resource Hierarchy can be represented as follows. */N/*  */N/* RESOURCE */N/* | */N/* +---------> ACPI_RESOURCE_TYPE */N/* | */N/* +-----------> ATTRIBUTE_ATTRIBUTE */N/* */N/* In a call to acpi$osl_get_crs_item, the top level parameter is required. */N/* The others may or may not be required, depending on the type of resource */N/* and the ways in which it can be characterized. */N/* */N/* */N/* Structures used to describe device-specific resources. */N/*  */ 'typedef struct _gps_resource_vendccsr {. unsigned short int gps_vend$w_ccsr_length;/ unsigned char gps_vend$b_ccsr_guid_subtype;, unsigned char gps_vend$b_ccsr_guid [16];. unsigned char gps_vend$b_cec_csr_base [8]; } GPS_RESOURCE_VENDCCSR; 'typedef struct _gps_resource_vendpcih {. unsigned short int gps_vend$w_pcih_length;/ unsigned char gps_vend$b_pcih_guid_subtype;, unsigned char gps_vend$b_pcih_guid [16];* unsigned char gps_vend$b_pci_hint [2]; } GPS_RESOURCE_VENDPCIH; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __GPSCFGDEF_LOADED */ wwP_4[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 13-APR-2020 16:28:32 $1$DGA8345:[LIB_H.SRC]GSDDEF.SDL;1 *//*********************************************************************************************************************** *********//*** MODULE $GSDDEF ***/#ifndef __GSDDEF_LOADED#define __GSDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+  */N/* Global Section Descriptor Block */N/*- */N#define GSD$K_LENGTH 49 /*LENGTH OF LOCAL MEMORY GSD */N#define GSD$C_LENGTH 49 /*LENGTH OF LOCAL MEMORY GSD */N#define GSD$K_EXTGSDLNG 73 /*MINIMUM EXTENDED GSD LENGTH */N#define GSD$C_EXTGSDLNG 73 /*MINIMUM EXTENDED GSD LENGTH */#define GSD$S_GSDDEF 73o#define GSD$C_MAXNAMLEN 43 /*Maximum length of a global section name (not including count byte) */N/*The size reflects 39-byte filenames and a 4-character prefix */  9#ifdef __cplusplus /* Define structure prototypes */ struct _orb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_ali gnment#endiftypedef struct _gsd {#pragma __nomember_alignmentN struct _gsd *gsd$l_gsdfl; /*POINTER TO NEXT GSD */N struct _gsd *gsd$l_gsdbl; /*POINTER TO PREVIOUS GSD */N unsigned short int gsd$w_size; /*SIZE OF GSD IN BYTES */N unsigned char gsd$b_type; /*STRUCTURE TYPE CODE FOR GSD */ unsigned char gsd$b_fill_1;N unsigned int gsd$l_hash; /*HASH FOR GSD NAME */  __union {Q unsigned int gsd$l_pcbuic; /*UIC OF CREATOR OF SECTION, FROM PCB */ __struct {% char gsddef$$_fill_6 [2];X unsigned short int gsd$w_pcbgrp; /*GROUP OF CREATOR OF SECTION, FROM PCB */" } gsd$r_pcbuic_fields; } gsd$r_pcbuic_overlay;N unsigned int gsd$l_filuic; /*OWNER OF FILE, UIC FROM FCB */N unsigned int gsd$l_prot; /*PROTECTION MASK */N unsigned int gsd$l_gstx; /*GLOBAL SECTION TABLE INDEX */N unsigned int gsd$l_ident; /*IDENTIFICATION OF GLOBAL SECTION */N struct _orb *gsd$l_orb; /*OBJECT RIGHTS BLOCK LOCATOR */ __union {m unsigned int gsd$l_ipid; /*IPID of nominal owner -- only defined while GSD is being deleted */` unsigned int gsd$l_related_gstx; /*GSTE index of another section related to this one. */N/* e.g. an MRES section with associated shared PTs  */ } gsd$r_ipid_overlay;N unsigned int gsd$l_flags; /*SECTION FLAGS */ __union { __struct {N char gsd$t_gsdnam; /*LOCAL MEMORY SECTION NAME */" char gsd$b_fill_2 [3];( } gsd$r_local_end_structure;N/* */N/* The following fields are only found in extended GSDs. These are used */N/* whenever a GSD is needed without a section table entry, i.e., for pages */N/* mapped by PFN. */N/* */N/* Verified for x86 port - Clair Grant */N unsigned __int64 gsd$i_basepfn; /*FIRST RELATIVE BASE PFN */ } gsd$r_gsd_overlay;N/* Verified for x86 port - Clair Grant */N unsigned __int64  gsd$i_pages; /*COUNT OF PAGES AT FIRST BASE PFN */N unsigned __int64 gsd$i_refcnt; /*FIRST PROCESSOR PTE REF COUNT */N char gsd$t_pfngsdnam; /*PFN-MAPPED SECTION NAME */N/*from MA780 days. */ char gsd$b_fill_0_ [7]; } GSD; #if !defined(__VAXC)6#define gsd$l_pcbuic gsd$r_pcbuic_overlay.gsd$l_pcbuicJ#define gsd$w_pcbgrp gsd$r_pcbuic_overlay.gsd$r_pcbuic_fields.gsd$w_pcbgrp0#defin e gsd$l_ipid gsd$r_ipid_overlay.gsd$l_ipid@#define gsd$l_related_gstx gsd$r_ipid_overlay.gsd$l_related_gstxM#define gsd$t_gsdnam gsd$r_gsd_overlay.gsd$r_local_end_structure.gsd$t_gsdnam5#define gsd$i_basepfn gsd$r_gsd_overlay.gsd$i_basepfn"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __GSDDEF_LOADED */ wwp4[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7  */F/* Source: 02-AUG-2007 11:42:18 $1$DGA8345:[LIB_H.SRC]HD1DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $HD1DEF ***/#ifndef __HD1DEF_LOADED#define __HD1DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* HDR1 ANDSI MAGNETIC TAPE LABEL */T/* THIS IS THE FIRST LABEL IN THE FILE LABEL HEADER SET. IF IDENTIFIES THE FILE. */N/*- */#define HD1$S_HD1DEF 80 typedef struct _hd1 {P unsigned int hd1$l_hd1lid; /*LABEL IDENTIFIER AND NUMBER 'HDR1' */N char hd1$t_fileid [17]; /*FILE IDENTIFIER */N char hd1$t_filesetid [6]; /*FILE SET IDENTIFIER */N char hd1$t_filesecno [4]; /*FILE SECTION NUMBER */N char hd1$t_fileseqno [4]; /*FILE SEQUENCE NUMBER */N char hd1$t_genno [4]; /*FILE GENERATION NUMBER */N char hd1$t_genver [2]; /*FILE GENERATION VERSION NUMBER */N char hd1$t_createdt [6]; /*CREATION DATE ( YYDDD) */N char hd1$t_expiredt [6]; /*EXPIRATION DATE */N unsigned char hd1$b_filaccess; /*FILE ACCESS */N char hd1$t_blockcnt [6]; /*BLOCK COUNT */N char hd1$t_syscode [13]; /*SYSTEM CODE */N char hd1def$$_fill_1 [3];  /*SPACES */N char hd1$t_hiblockcnt [4]; /* HIGH BLOCK COUNT */ } HD1; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HD1DEF_LOADED */ ww4[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc.  **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 20-APR-1993 13:46:44 $1$DGA8345:[LIB_H.SRC]HD2DEF.SDL;1 *//******************************************************************* *************************************************************//*** MODULE $HD2DEF ***/#ifndef __HD2DEF_LOADED#define __HD2DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short  /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+  */N/* HDR2 ANSI MAGNETIC TAPE LABEL */N/* THIS IS THE SECOND LABEL IN FILE LABEL HEADER SET. */N/* THE FILE ATTRIBUTES HAVE BEEN REMOVED FROM HDR2, AND PLACED IN HDR3. */N/* THE FIELDS REMAIN IN THE DEFINITION TO SUPPORT OLD TAPES. */N/*- */#define HD2$S_HD2DEF 72 typedef struct _hd2 {P unsigned int hd2$l_hd2lid; /*LABEL IDENTIFIER AND NUMBER 'HDR2' */N unsigned char hd2$b_recformat; /*RECORD FORMAT */N char hd2$t_blocklen [5]; /*BLOCK LENGTH */N char hd2$t_reclen [5]; /*RECORD LENGTH */Z char hd2$t_recatr1 [20]; /*FIRST 20 BYTES OF FILES-11 RECORD ATTRIBUTES */N char hd2def$$_fill_1; /*SPACES  */N unsigned char hd2$b_formcntrl; /*FORMS CONTROL */Y char hd2$t_recatr2 [12]; /*LAST 12 BYTES OF FILES-11 RECORD ATTRIBUTES */N char hd2def$$_fill_2; /*SPACES */N char hd2$t_bufoff [2]; /*BUFFER OFFSET */N char hd2def$$_fill_3 [20]; /*SPACES */ } HD2; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HD2DEF_LOADED */ ww"5[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************** ***************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */F/* Source: 19-APR-1993 14:24:38 $1$DGA8345:[LIB_H.SRC]HD3DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $HD3DEF ***/#ifndef __HD3DEF_LOADED#define __HD3DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* HDR3 ANSI MAGNETIC TAPE LABEL */N/* THIS IS THE THIRD LABEL IN FILE LABEL HEADER SET.  */N/* IT IDENTIFIES THE FILE ATTRIBUTES. */N/*- */#define HD3$S_HD3DEF 80 typedef struct _hd3 {P unsigned int hd3$l_hd3lid; /*LABEL IDENTIFIES AND NUMBER 'HDR3' */T char hd3$t_recatr [64]; /*64 BYTES OF FILES-11 RECORD ATTRIBUTES */N char hd3def$$_fill_1 [12]; /*SPACES */ } HD3; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HD3DEF_LOADED */ wwp5[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********************************************************** ****************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */F/* Source: 19-APR-1993 14:26:17 $1$DGA8345:[LIB_H.SRC]HD4DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $HD4DEF ***/#ifndef __HD4DEF_LOADED#define __HD4DEF_LOADED 1 G#p ragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* HDR4 ANSI MAGNETIC TAPE LABEL */N /* THIS IS THE FOURTH LABEL IN FILE LABEL HEADER SET. */N/* IT CONTAINS THE LONG FILENAME EXTENSION TO THE HDR1 FILE IDENTIFIER */N/* FOR VMS LONG FILE NAMES */N/*- */#define HD4$S_HD4DEF 82 typedef struct _hd4 {P unsigned int hd4$l_hd4lid; /*LABEL IDENTIFIER AND NUMBER 'HDR4' */T unsigned char hd4$b_fileid_ext_size; /*SIZE OF  FILE ID EXT FOR ANSI 4 VOLUMES */N char hd4$t_fileid_ext [62]; /*EXTENSION OF HDR1 FILEID */S char hd4$t_fileid_ext_v3 [2]; /*SIZE OF FILE ID EXT FOR ANSI 3 VOLUMES */N char hd4def$$_fill_1 [13]; /*SPACES */ } HD4; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HD4DEF_LOADED */ ww5[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without  **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SD L V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $HM1DEF ***/#ifndef __HM1DEF_LOADED#define __HM1DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Home block definitions for Files-11 Structure Level 1 */N/* */N/*-  */ N#define HM1$C_LEVEL1 257 /* 401 octal = structure level 1 */W#define HM1$C_LEVEL2 258 /* 402 octal = structure level 1, version 2 */N#define HM1$S_HM1DEF 512 /* Old size name - synonym */ typedef struct _hm1 {N unsigned short int hm1$w_ibmapsize; /* index file bitmap size, blocks */N unsigned int hm1$l_ibmaplbn; /* index file bitmap starting LBN */N unsigned short int hm1$w_maxfiles; /* maximum ! files on volume */N unsigned short int hm1$w_cluster; /* storage bitmap cluster factor */N unsigned short int hm1$w_devtype; /* disk device type */N unsigned short int hm1$w_struclev; /* volume structure level */N char hm1$t_volname [12]; /* volume name (ASCII) */N char hm1$$_fill_1 [4]; /* spare */N unsigned short int hm1$w_volowner; /* volum e owner UIC */ __union {N unsigned short int hm1$w_protect; /* volume protection */ __struct {N unsigned hm1$v_syspro : 4; /* system protection */N unsigned hm1$v_ownpro : 4; /* owner protection */N unsigned hm1$v_grouppro : 4; /* group protection */N unsigned hm1$v_worldpro : 4; /* world protection */! } hm1$r_protect_bits;  } hm1$r_protect_overlay;N unsigned short int hm1$w_volchar; /* volume characteristics */N unsigned short int hm1$w_fileprot; /* default file protection */N char hm1$$_fill_2 [6]; /* spare */N unsigned char hm1$b_window; /* default window size */N unsigned char hm1$b_extend; /* default file extend */N unsigned char hm1$b_lru_lim; /* default LRU limit  */N char hm1$$_fill_3 [11]; /* spare */N unsigned short int hm1$w_checksum1; /* first checksum */N char hm1$t_credate [14]; /* volume creation date */N char hm1$$_fill_4 [382]; /* spare */N unsigned int hm1$l_serialnum; /* pack serial number */N char hm1$$_fill_5 [12]; /* reserved */N char hm1$t_vol name2 [12]; /* 2nd copy of volume name */N char hm1$t_ownername [12]; /* volume owner name */N char hm1$t_format [12]; /* volume format type */N char hm1$$_fill_6 [2]; /* spare */N unsigned short int hm1$w_checksum2; /* second checksum */ } HM1; #if !defined(__VAXC)9#define hm1$w_protect hm1$r_protect_overlay.hm1$w_protectJ#define hm1$v_syspro hm1$r _protect_overlay.hm1$r_protect_bits.hm1$v_sysproJ#define hm1$v_ownpro hm1$r_protect_overlay.hm1$r_protect_bits.hm1$v_ownproN#define hm1$v_grouppro hm1$r_protect_overlay.hm1$r_protect_bits.hm1$v_groupproN#define hm1$v_worldpro hm1$r_protect_overlay.hm1$r_protect_bits.hm1$v_worldpro"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HM1DEF_LOADED */ ww5[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created : 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $HM2DEF ***/#ifndef __HM2DEF_LOADED#define __HM2DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Home block definitions for Files-11 Structure Level 2 */N/* */N/* - */ N#define HM2$C_LEVEL1 257 /* 401 octal = structure level 1 */N#define HM2$C_LEVEL2 512 /* 1000 octal = structure level 2 */N#define HM2$C_LEVEL5 1280 /* 2400 octal = structure level 5 */N#define HM2$C_LEVEL6 1536 /* 3000 octal = structure level 6 */#define HM2$M_READCHECK 0x1#define HM2$M_WRITCHECK 0x2#define HM2$M_ERASE 0x4#define HM2$M_NOHI GHWATER 0x8#define HM2$M_CLASS_PROT 0x10#define HM2$M_ACCESSTIMES 0x20#define HM2$M_HARDLINKS 0x40##define HM2$M_NO_SPECIAL_FILES 0x80N#define HM2$S_HM2DEF 512 /* Old size name - synonym */ typedef struct _hm2 {N unsigned int hm2$l_homelbn; /* LBN of home (i.e., this) block */N unsigned int hm2$l_alhomelbn; /* LBN of alternate home block */Q unsigned int hm2$l_altidxlbn; /* LBN of alternate index file header */ __un ion {N unsigned short int hm2$w_struclev; /* volume structure level */ __struct {N unsigned char hm2$b_strucver; /* structure version number */N unsigned char hm2$b_struclev; /* main structure level */$ } hm2$r_struclev_fields;! } hm2$r_struclev_overlay;N unsigned short int hm2$w_cluster; /* storage bitmap cluster factor */N unsigned short int hm2$w_homevbn; /* VBN of home (i.e., this) block */N  unsigned short int hm2$w_alhomevbn; /* VBN of alternate home block */Q unsigned short int hm2$w_altidxvbn; /* VBN of alternate index file header */N unsigned short int hm2$w_ibmapvbn; /* VBN of index file bitmap */N unsigned int hm2$l_ibmaplbn; /* LBN of index file bitmap */N unsigned int hm2$l_maxfiles; /* maximum ! files on volume */N unsigned short int hm2$w_ibmapsize; /* index file bitmap size, blocks */N unsigned short int h m2$w_resfiles; /* ! reserved files on volume */N unsigned short int hm2$w_devtype; /* disk device type */T unsigned short int hm2$w_rvn; /* relative volume number of this volume */N unsigned short int hm2$w_setcount; /* count of volumes in set */ __union {N unsigned short int hm2$w_volchar; /* volume characteristics */ __struct {N unsigned hm2$v_readcheck : 1; /* verify all read operations */N  unsigned hm2$v_writcheck : 1; /* verify all write operations */N unsigned hm2$v_erase : 1; /* erase all files on delete */N unsigned hm2$v_nohighwater : 1; /* turn off high-water marking */[ unsigned hm2$v_class_prot : 1; /* enable classification checks on the volume */N unsigned hm2$v_accesstimes : 1; /* enable access time */N unsigned hm2$v_hardlinks : 1; /* enable hardlinks */N unsigned hm2$v_no_special_files : 1; /* disable special files */! } hm2$r_volchar_bits; } hm2$r_volchar_overlay;N unsigned int hm2$l_volowner; /* volume owner UIC */N unsigned int hm2$l_sec_mask; /* volume security mask */N unsigned short int hm2$w_protect; /* volume protection */N unsigned short int hm2$w_fileprot; /* default file protection */N unsigned short int hm2$w_recprot; /* default file record protection */N unsigned short int hm2$w_checksum1; /* first checksum */N unsigned __int64 hm2$q_credate; /* volume creation date */N unsigned char hm2$b_window; /* default window size */N unsigned char hm2$b_lru_lim; /* default LRU limit */N unsigned short int hm2$w_extend; /* default file extend */N unsigned __int64 hm2$q_retainmin; /* minimum file retention period */N  unsigned __int64 hm2$q_retainmax; /* maximum file retention period */N unsigned __int64 hm2$q_revdate; /* volume revision date */N __struct { /* volume minimum security class */ char hm2$b_fill_2 [20]; } hm2$r_min_class;N __struct { /* volume maximum security class */ char hm2$b_fill_3 [20]; } hm2$r_max_class;N unsigned short int hm2$w_filetab_fid [3]; /* file lookup t able FID */ __union {N unsigned short int hm2$w_lowstruclev; /* lowest struclev on volume */ __struct {N unsigned char hm2$b_lowstrucver; /* structure version number */N unsigned char hm2$b_lowstruclev; /* main structure level */' } hm2$r_lowstruclev_fields;$ } hm2$r_lowstruclev_overlay; __union {O unsigned short int hm2$w_highstruclev; /* highest struclev on volume */ __struct {N  unsigned char hm2$b_highstrucver; /* structure version number */N unsigned char hm2$b_highstruclev; /* main structure level */( } hm2$r_highstruclev_fields;% } hm2$r_highstruclev_overlay;N unsigned __int64 hm2$q_copydate; /* volume copy date */N unsigned __int64 hm2$q_accessdelta; /* granularity for access time */d unsigned short int hm2$w_viboffset; /* Offset in bytes to VIB (ODS6 Volume Information Block) */N unsigned short int hm2$w_vibsize; /* Size in bytes of VIB */N char hm2$b_fill_0 [2]; /* Filler to reestablish alignment */N char hm2def$$_fill_1 [288]; /* spare */N unsigned int hm2$l_serialnum; /* pack serial number */N char hm2$t_strucname [12]; /* structure (volume set name) */N char hm2$t_volname [12]; /* volume name */N char hm2$t_ownername [12];  /* volume owner name */N char hm2$t_format [12]; /* volume format type */N char hm2$$_fill_2 [2]; /* spare */N unsigned short int hm2$w_checksum2; /* second checksum */ } HM2; #if !defined(__VAXC)<#define hm2$w_struclev hm2$r_struclev_overlay.hm2$w_struclevR#define hm2$b_strucver hm2$r_struclev_overlay.hm2$r_struclev_fields.hm2$b_strucverR#define hm2$b_struclev hm2$r_struclev_overlay.hm2$r_struclev_fields.hm2$b_struclev9#define hm2$w_volchar hm2$r_volchar_overlay.hm2$w_volcharP#define hm2$v_readcheck hm2$r_volchar_overlay.hm2$r_volchar_bits.hm2$v_readcheckP#define hm2$v_writcheck hm2$r_volchar_overlay.hm2$r_volchar_bits.hm2$v_writcheckH#define hm2$v_erase hm2$r_volchar_overlay.hm2$r_volchar_bits.hm2$v_eraseT#define hm2$v_nohighwater hm2$r_volchar_overlay.hm2$r_volchar_bits.hm2$v_nohighwaterR#define hm2$v_class_prot hm2$r_volchar_overlay.hm2$r_volchar_bits.hm2$v_class_protT#define hm2$v_accesstimes hm2$r_volchar_overlay.hm2$r_volchar_bits.hm2$v_accesstimesP#define hm2$v_hardlinks hm2$r_volchar_overlay.hm2$r_volchar_bits.hm2$v_hardlinks^#define hm2$v_no_special_files hm2$r_volchar_overlay.hm2$r_volchar_bits.hm2$v_no_special_filesE#define hm2$w_lowstruclev hm2$r_lowstruclev_overlay.hm2$w_lowstruclev^#define hm2$b_lowstrucver hm2$r_lowstruclev_overlay.hm2$r_lowstruclev_fields.hm2$b_lowstrucver^#define hm2$b_lowstruclev hm2$r_lowstruclev_overlay.hm2$r_lowstrucle v_fields.hm2$b_lowstruclevH#define hm2$w_highstruclev hm2$r_highstruclev_overlay.hm2$w_highstruclevb#define hm2$b_highstrucver hm2$r_highstruclev_overlay.hm2$r_highstruclev_fields.hm2$b_highstrucverb#define hm2$b_highstruclev hm2$r_highstruclev_overlay.hm2$r_highstruclev_fields.hm2$b_highstruclev"#endif /* #if !defined(__VAXC) */  N/* Type of homeblock placement deltas. */N/* Code assumes these are zero-based and increase monotonically */N/* */N#define HM2$C_REQ_DELTA_GEOM_DEPEND 0 /* dependent on disk geometry */N#define HM2$C_REQ_DELTA_GEOM_INDEPEND 1 /* independent of disk geometry */]#define HM2$C_REQ_DELTA_FIXED_CONTIG 2 /* fixed so index file will be contig (for Dollar) */O#define HM2$C_GEOM_INDEPEND_DELTA 1033 /* actual geometry independent delta */N/* this is a prime > 1000 */S#define HM2$C_FIXED_CONTIG_DELTA 1 /* fixed delta for contiguous index file */[#define HM2$C_LIMITED_SEARCH_LENGTH 255 /* number of blocks to check in a limited search */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HM2DEF_LOADED */ ww46[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */F/* Source: 09-OCT-1995 13:44:01 $1$DGA8345:[LIB_H.SRC]HPCDEF.SDL;1 *//******************************* *************************************************************************************************//*** MODULE $HPCDEF ***/#ifndef __HPCDEF_LOADED#define __HPCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _hpc {#pragma __nomember_alignment! unsigned char hpc$b_f00 [24]; unsigned int hpc$l_ctl;" unsigned char hpc$b_f10 [124]; unsigned int hpc$l_mretry;" unsigned char hpc$b_f20 [124]; unsigned int hpc$l_gpr;" unsigned char hpc$b_f30 [124]; unsigned int hpc$l_err;" unsigned char hpc$b_f40 [124]; unsigned int hpc$l_fadr;" unsigned char hpc$b_f50 [124]; unsigned int hpc$l_imask;" unsigned char hpc$b_f60 [124]; unsigned int hpc$l_diag;" unsigned char hpc$b_f70 [124]; unsigned int hpc$l_ipend;" unsigned char hpc$b_f80 [124]; unsigned int hpc$l_iprog;" unsigned char hpc$b_f90 [124]; unsigned int hpc$l_wmask_a;# unsigned char hpc$b_f100 [124]; unsigned int hpc$l_wbase_a;# unsigned char hpc$b_f110 [124]; unsigned int hpc$l_tbase_a;# unsigned char hpc$b_f120 [124]; unsigned int hpc$l_wmask_b;# unsigned char hpc$b_f130 [124]; unsigned int hpc$l_wbase_b;# unsigned char hpc$b_f140 [124]; unsigned int hpc$l_tbase_b;# unsigned char hpc$b_f150 [124]; unsigned int hpc$l_wmask_c;# unsigned char hpc$b_f160 [124]; unsigned int hpc$l_wbase_c;# unsigned char hpc$b_f170 [124]; unsigned int hpc$l_tbase_c;# unsigned char hpc$b_f180 [124]; unsigned int hpc$l_errvec;$ unsigned char hpc$b_f190 [1788]; __struct {" unsigned int hpc$l_d_inta;, unsigned int hpc$l_d_int_fill1 [31];" unsigned int hpc$l_d_intb;, unsigned int hpc$l_d_int_fill2 [31];" unsigned int hpc$l_d_intc;, unsigned int hpc$l_d_int_fill3 [31];" unsigned int hpc$l_d_intd;, unsigned int hpc$l_d_int_fill4 [31]; } hpc$r_devvec [4]; } HPC; #if !defined(__VAXC)!#define hpc$l_d_inta hpc$l_d_inta+#define hpc$l_d_int_fill1 hpc$l_d_int_fill1!#define hpc$l_d_intb hpc$l_d_intb+#define hpc$l_d_int_fill2 hpc$l_d_int_fill2!#define hpc$l_d_intc hpc$l_d_intc+#define hpc$l_d_int_fill3 hpc$l_d_int_fill3!#define hpc$l_d_intd hpc$l_d_intd+#define hpc$l_d_int_fill4 hpc$l_d_int_fill4"#endif /* #if !defined(__VAXC) */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _iack {#pragma __nomember_alignment# unsigned char iack$b_f210 [24]; __union {! unsigned int iack$l_iack; __struct {6 unsigned iack$v_placeholder_bitfield : 10;( unsigned iack$v_fill_0_ : 6; } iack$r_iack_bits; } iack$r_iack_overlay; } IACK; #if !defined(__VAXC)3#define iack$l_iack iack$r_iack_overlay.iack$l_iack"#endif /* #if !defined(__VAXC) */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _hpc_ctl {#pragma __nomember_alignment __union {# unsigned int hpc$l_reg_ctl; __struct {1 unsigned hpc$v_config_cycle_type : 2;1 unsigned hpc$v_memory_block_size : 1;) unsigned hpc$v_pci_reset : 1;0  unsigned hpc$v_pci_ct_threshold : 4;- unsigned hpc$v_pci_ct_enable : 1;& unsigned hpc$v_io_hae : 5;* unsigned hpc$v_memory_hae : 5;+ unsigned hpc$v_hae_disable : 1;' unsigned hpc$v_mrm_arb : 1;* unsigned hpc$v_mrm_enable : 1;1 unsigned hpc$v_mrm_prefetch_size : 1;. unsigned hpc$v_io_uphose_buff : 2;, unsigned hpc$v_sgm_ram_size : 2;/ unsigned hpc$v_pci_arb_control : 2 ;' unsigned hpc$v_fill_1_ : 3; } hpc$r_ctl_bits; } hpc$r_ctl_overlay; } HPC_CTL; #if !defined(__VAXC)5#define hpc$l_reg_ctl hpc$r_ctl_overlay.hpc$l_reg_ctlX#define hpc$v_config_cycle_type hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_config_cycle_typeX#define hpc$v_memory_block_size hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_memory_block_sizeH#define hpc$v_pci_reset hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_pci_resetV#define hpc$v_pci_ct_threshold hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_pci_ct_thresholdP#define hpc$v_pci_ct_enable hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_pci_ct_enableB#define hpc$v_io_hae hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_io_haeJ#define hpc$v_memory_hae hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_memory_haeL#define hpc$v_hae_disable hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_hae_disableD#define hpc$v_mrm_arb hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_mrm_arbJ#define hpc$v_mrm_enable hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_mrm_enableX#define hpc$v_ mrm_prefetch_size hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_mrm_prefetch_sizeR#define hpc$v_io_uphose_buff hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_io_uphose_buffN#define hpc$v_sgm_ram_size hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_sgm_ram_sizeT#define hpc$v_pci_arb_control hpc$r_ctl_overlay.hpc$r_ctl_bits.hpc$v_pci_arb_control"#endif /* #if !defined(__VAXC) */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _hpc_imask {#pragma __nomember_alignment __union {% unsigned int hpc$l_reg_imask; __struct {) unsigned short int hpc$w_int;- unsigned hpc$v_enable_errint : 1;/ unsigned hpc$v_device_priority : 4;. unsigned hpc$v_error_priority : 4;# unsigned hpc$v_mbz : 7; } hpc$r_imask_bits; } hpc$r_imask_overlay; } HPC_IMASK; #if !defined(__VAXC);#define hpc$l_reg_imask hpc$r_imask_overlay.hpc$l_reg_imask@#define hpc$w_int hpc$r_imask_overlay.hpc$r_imask_bits.hpc$w_intT#define hpc$v_enable_errint hpc$r_imask_overlay.hpc$r_imask_bits.hpc$v_enable_errintX#define hpc$v_device_priority hpc$r_imask_overlay.hpc$r_imask_bits.hpc$v_device_priorityV#define hpc$v_error_priority hpc$r_imask_overlay.hpc$r_imask_bits.hpc$v_error_priority@#define hpc$v_mbz hpc$r_imask_overlay.hpc$r_imask_bits.hpc$v_mbz"#endif /* #if !defined(__VAXC) */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _hpc_present {#pragma __nomember_alignment __union {' unsigned int hpc$l_reg_present; __struct {, unsigned hpc$v_pci_0_slot_0 : 2;, unsigned hpc$v_pci_0_slot_1 : 2;, unsigned hpc$v_pci_0_slot_2 : 2;, unsi gned hpc$v_pci_0_slot_3 : 2;, unsigned hpc$v_pci_1_slot_0 : 2;, unsigned hpc$v_pci_1_slot_1 : 2;, unsigned hpc$v_pci_1_slot_2 : 2;, unsigned hpc$v_pci_1_slot_3 : 2;, unsigned hpc$v_pci_2_slot_0 : 2;, unsigned hpc$v_pci_2_slot_1 : 2;, unsigned hpc$v_pci_2_slot_2 : 2;, unsigned hpc$v_pci_2_slot_3 : 2;+ unsigned hpc$v_standard_io : 1;( unsigned hpc$v_revision : 4;+ unsigned  hpc$v_present_mbz : 3;! } hpc$r_present_bits; } hpc$r_present_overlay; } HPC_PRESENT; #if !defined(__VAXC)A#define hpc$l_reg_present hpc$r_present_overlay.hpc$l_reg_presentV#define hpc$v_pci_0_slot_0 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_0_slot_0V#define hpc$v_pci_0_slot_1 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_0_slot_1V#define hpc$v_pci_0_slot_2 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_0_slot_2V#define hpc$v_pci_0_slot_3 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_0_slot_3V#define hpc$v_pci_1_slot_0 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_1_slot_0V#define hpc$v_pci_1_slot_1 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_1_slot_1V#define hpc$v_pci_1_slot_2 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_1_slot_2V#define hpc$v_pci_1_slot_3 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_1_slot_3V#define hpc$v_pci_2_slot_0 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_2_slot_0V#define hpc$v_pci_2_slot_1 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_2_slot_1V#define hpc$v_pci_2_slot_2 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_2_slot_2V#define hpc$v_pci_2_slot_3 hpc$r_present_overlay.hpc$r_present_bits.hpc$v_pci_2_slot_3T#define hpc$v_standard_io hpc$r_present_overlay.hpc$r_present_bits.hpc$v_standard_ioN#define hpc$v_revision hpc$r_present_overlay.hpc$r_present_bits.hpc$v_revisionT#define hpc$v_present_mbz hpc$r_present_overlay.hpc$r_present_bits.hpc$v_present_mbz"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HPCDEF_LOADED */ ww06[UM/***************************************************************************/M/**  **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */G/* Source: 22-SEP-2020 13:10:01 $1$DGA8345:[LIB_H.SRC]HPETDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $HPETDEF ***/#i fndef __HPETDEF_LOADED#define __HPETDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus ex tern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* Notation: */G/* RW read/write   */G/* RO read only */I/* RW1C write a 1 to clear the bit; writes of 0 have no effect */H/* RW0 field should always be written with a zero */H/* RMW field should always be written with whatever value was */B/* previously read */N/* */N/* This  structure defines hardware registers. The individual fields are */N/* intentionally not defined because these registers can only be accessed */N/* with longword or quadword references. To look at individual fields */N/* copy the entire quadword to a local and then examine the contents. */N/* Similarly, write an entire quadword from a memory copy, not individual */N/* fields. The exceptions to this rule are for the comparator values and */N/* the FSB interrupt value and add ress. Since these fields are entire */N/* quadwords or longwords, they can be directly accessed. */N/* All fields in this structure are read/write. */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _hpet_timer {#pragma __nomember_alignmentN unsigned __int64 hpet_timer$iq_config_and_ caps; /* RW */ __union {e unsigned __int64 hpet_timer$iq_comparator_value64; /* RW Comparator value for 64-bit timer */a unsigned int hpet_timer$il_comparator_value32; /* RW Comparator value for 32-bit timer */" } hpet_timer$r_comp_union; __union {N unsigned __int64 hpet_timer$iq_fsb_interrupt_route; /* RW */ __struct {d unsigned int hpet_timer$il_fsb_int_val; /* RW Value included in FSB interrupt message */o unsigned int hpet_timer$il_fsb_int_addr; /* RW Address to which FSB interrupt message is written */$ } hpet_timer$r_fsb_ints;! } hpet_timer$r_fsb_union;, unsigned __int64 hpet_timer$iq_reserved; } HPET_TIMER; #if !defined(__VAXC)a#define hpet_timer$iq_comparator_value64 hpet_timer$r_comp_union.hpet_timer$iq_comparator_value64a#define hpet_timer$il_comparator_value32 hpet_timer$r_comp_union.hpet_timer$il_comparator_value32b#define hpet_timer$iq_fsb_interrupt_route hpet_timer$r_fsb_union.hpet_timer$iq_fsb_interrupt_routeh#define hpet_timer$il_fsb_int_val hpet_timer$r_fsb_union.hpet_timer$r_fsb_ints.hpet_timer$il_fsb_int_valj#define hpet_timer$il_fsb_int_addr hpet_timer$r_fsb_union.hpet_timer$r_fsb_ints.hpet_timer$il_fsb_int_addr"#endif /* #if !defined(__VAXC) */ N/* Fields of the HPET_TIMER CONFIGS_AND_CAPS register. */N/* All fields in this register are read/write. */ #define HTIMCFG$M_RESERVED_1 0x1"#define HTIMCFG$M_INT_TYPE_CNF 0x2!#define HTIMCFG$M_INT_ENB_CNF 0x4#define HTIMCFG$M_TYPE_CNF 0x8"#define HTIMCFG$M_PER_INT_CAP 0x10#define HTIMCFG$M_SIZE_CAP 0x20"#define HTIMCFG$M_VAL_SET_CNF 0x40!#define HTIMCFG$M_RESERVED_2 0x80"#define HTIMCFG$M_CNF_32MODE 0x100&#define HTIMCFG$M_INT_ROUTE_CNF 0x3E00##define HTIMCFG$M_FSB_EN_CNF 0x4000(#define HTIMCFG$M_FSB_INT_DEL_CAP 0x8000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _htim_config {#pragma __nomember_alignment __union {1 unsigned __int64 htimcfg$iq_cfg_register; __struct {N unsigned htimcfg$v_reserved_1 : 1; /* RW0 [0] */T unsigned htimcfg$v_int_type_cnf : 1; /* RW [1] 0 => edge, 1 => level */N unsigned htimcfg$v_int_enb_cnf : 1; /* RW [2] interrupt enable */T unsigned htimcfg$v_type_cnf : 1; /* RW [3] periodic interrupt enable */b unsigned htimcfg$v_per_int_cap : 1; /* RO [4] timer capable of periodic interrupts */U unsigned htimcfg$v_size_cap : 1; /* RO [5] 1 => 64 bits, 0 => 32 bits */_ unsigned htimcfg$v_val_set_cnf : 1; /* RW [6] periodic accumulator write enable */N unsigned htimcfg$v_reserved_2 : 1; /* RW0 [7] */X unsigned htimcfg$v_cnf_32mode : 1; /* RW [8] force 32-bit timer behavior */] unsigned htimcfg$v_int_route_cnf : 5; /* RW [9-13] I/O APIC interrupt routing */W unsigned htimcfg$v_fsb_en_cnf : 1; /* RW [14] deliver interrupts to FSB */b unsigned htimcfg$v_fsb_int_del_cap : 1; /* RO [15] timer capable of FSB interrupts */N unsigned short int htimcfg$iw_reserved_3; /* RW0 [16-31] */\ unsigned int htimcfg$il_int_route_cap; /* RO [32-63] I/O APIC routes allowed */  } htimcfg$r_cfg;" } htimcfg$r_htimcfg_union; } HTIM_CONFIG; #if !defined(__VAXC)O#define htimcfg$iq_cfg_register htimcfg$r_htimcfg_union.htimcfg$iq_cfg_register[#define htimcfg$v_int_type_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_int_type_cnfY#define htimcfg$v_int_enb_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_int_enb_cnfS#define htimcfg$v_type_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_type_cnfY#define htimcfg$v_per_int_cap htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_per_int_capS#define htimcfg$v_size_cap htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_size_capY#define htimcfg$v_val_set_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_val_set_cnfW#define htimcfg$v_cnf_32mode htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_cnf_32mode]#define htimcfg$v_int_route_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_int_route_cnfW#define htimcfg$v_fsb_en_cnf htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_fsb_en_cnfa#define htimcfg$v_fsb_int_del_cap htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$v_fsb_int_del_capY#define htimcfg$iw_reserved_3 htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$iw_reserved_3_#define htimcfg$il_int_route_cap htimcfg$r_htimcfg_union.htimcfg$r_cfg.htimcfg$il_int_route_cap"#endif /* #if !defined(__VAXC) */ #define HTCFG_INT_TYPE$K_EDGE 0 #define HTCFG_INT_TYPE$K_LEVEL 1!#define HTCFG_INT_ENB$K_DISABLE 0 #define HTCFG_INT_ENB$K_ENABLE 1##define HTCFG_INT_TYPE$K_ONE_SHOT 0##define HTCFG_INT_TYPE$K_PERIODIC 1#define HTCFG_SIZE$K_SIZE_32 0#define HTCFG_SIZE$K_SIZE_64 1T#define HTCFG_VAL_SET$K_ENABLE 1 /* Bit automatically clears after a write */ #define HTCFG_32MODE$K_MODE_64 0 #define HTCFG_32MODE$K_MODE_32 1#define HTCFG_FSB_EN$K_IOAPIC 0#define HTCFG_FSB_EN$K_FSB 1N/* The HPET_TIMER FSB_INTERRUPT_ROUTE register defines the MSI */N/* (Message Signaled Interrupt) address and data to be used if the */N/* timer is configured to use FSB (Front Side Bus) interrupts. The */N/* MSI message format is defined in section 10.11 of Volume 3 of */N/* the Intel 64 and IA-32 Architectures Software Developer's Manual. */N/* The address determines which CPU(s) receive the message, and the */N/* data indicates which IDT vector to use. */#define HTIMFSB$M_VECTOR 0xFF#define HTIMFSB$M_DELMODE 0x700##define HTIMFSB$M_RESERVED_1 0x3800#define HTIMFSB$M_LEVEL 0x4000!#def ine HTIMFSB$M_TRIGMODE 0x8000'#define HTIMFSB$M_RESERVED_2 0xFFFF0000(#define HTIMFSB$M_RESERVED_3 0x300000000&#define HTIMFSB$M_DESTMODE 0x400000000'#define HTIMFSB$M_REDIRHINT 0x800000000*#define HTIMFSB$M_RESERVED_4 0xFF000000000)#define HTIMFSB$M_DEST_ID 0xFF00000000000,#define HTIMFSB$M_FEE_TAG 0xFFF0000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember _alignment#endiftypedef struct _htim_fsb {#pragma __nomember_alignment __union {1 unsigned __int64 htimfsb$iq_fsb_register; __struct {Q unsigned htimfsb$v_vector : 8; /* RW [0-7] destination IDT vector */Y unsigned htimfsb$v_delmode : 3; /* RW [8-10] delivery mode to destination */N unsigned htimfsb$v_reserved_1 : 3; /* RW0 [11-13] */i unsigned htimfsb$v_level : 1; /* RW [14] for level interrupts, 0 => deassert, 1 => assert */Q unsigned htimfsb$v_trigmode : 1; /* RW [15] 0 => edge, 1 => level */N unsigned htimfsb$v_reserved_2 : 16; /* RW0 [16-31] */N unsigned htimfsb$v_reserved_3 : 2; /* RW0 [32-33] */n unsigned htimfsb$v_destmode : 1; /* RW [34] 0 => physical, 1 => logical, but see documentation */N unsigned htimfsb$v_redirhint : 1; /* RW [35] see documentation */N unsigned htimfsb$v_reserved_4 : 8; /* RW0 [36-43] */_ unsigned htimfsb$v_dest_id : 8; /* RW [44-51] destination xAPIC ID or x2APIC ID */Q unsigned htimfsb$v_fee_tag : 12; /* RW [52-63] must contain 0xFEE */ } htimfsb$r_fsb;" } htimfsb$r_htimfsb_union; } HTIM_FSB; #if !defined(__VAXC)O#define htimfsb$iq_fsb_register htimfsb$r_htimfsb_union.htimfsb$iq_fsb_registerO#define htimfsb$v_vector htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_vectorQ#define htimfsb$v_delmode htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_delmodeM#define htimfsb$v_level htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_levelS#define htimfsb$v_trigmode htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_trigmodeS#define htimfsb$v_destmode htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_destmodeU#define htimfsb$v_redirhint htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_redirhintQ#define htimfsb$v_dest_id htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_dest_idQ#define htimfsb$v_fee_tag htimfsb$r_htimfsb_union.htimfsb$r_fsb.htimfsb$v_fee_tag"#endif /* #if !defined(__VAXC) */ #define FSBMSG_DELMODE$K_FIXED 0!#define FSBMSG_DELMODE$K_LOWPRI 1#define FSBMSG_DELMODE$K_SMI 2!#define FSBMSG_DELMODE$K_RESV_1 3#define FSBMSG_DELMODE$K_NMI 4#define FSBMSG_DELMODE$K_INIT 5!#define FSBMSG_DELMODE$K_RESV_2 6!#define FSBMSG_DELMODE$K_EXTINT 7$#define FSBMSG_DESTMODE$K_PHYSICAL 0##define FSBMSG_DESTMODE$K_LOGICAL 1!#define FSBMSG_FEE_TAG$K_FEE 4078!#defin e FSBMSG_LEVEL$K_DEASSERT 0#define FSBMSG_LEVEL$K_ASSERT 1#define FSBMSG_HINT$K_NONE 0#define FSBMSG_HINT$K_HINT 1 #define FSBMSG_TRIGMODE$K_EDGE 0!#define FSBMSG_TRIGMODE$K_LEVEL 1N/* This structure defines hardware registers. The individual fields are */N/* intentionally not defined because these registers can only be accessed */N/* with longword or quadword references. To look at individual fields */N/* copy the entire quadword to a local and then examine the contents.  */N/* Similarly, write an entire quadword from a memory copy, not individual */N/* fields. */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _hpet {#pragma __nomember_alignmentN unsigned __int64 hpet$iq_capabilities_and_id; /* RO */N unsign!ed __int64 hpet$iq_reserved_1; /* RO */N unsigned __int64 hpet$iq_configuration; /* See field descriptions */N unsigned __int64 hpet$iq_reserved_2; /* RO */N unsigned __int64 hpet$iq_interrupt_status; /* See field descriptions */N unsigned __int64 hpet$iq_reserved_3 [25]; /* RO */e unsigned __int64 hpet$iq_main_counter; /* RW Timer value, writable only when counter is halted */N unsigned " __int64 hpet$iq_reserved_4; /* RO */N HPET_TIMER hpet$t_timer [3]; /* See HPET_TIMER description above */ } HPET;N/* Fields of the HPET CAPABILITIES_AND_ID register. */N/* RO indicates read only. */$#define HPETCAP$M_NUM_TIM_CAP 0x1F00&#define HPETCAP$M_COUNT_SIZ_CAP 0x2000$#define HPETCAP$M_RESERVED_14 0x4000&#define HPETCAP$M_LEG_ROUTE_CAP 0x8000 c#if !defined(__NOBASEALI #GN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _hpet_caps {#pragma __nomember_alignment __union {1 unsigned __int64 hpetcap$iq_cap_register; __struct {N unsigned char hpetcap$b_rev_id; /* RO [0-7] Hardware revision */Y unsigned hpetcap$v_num_tim_cap : 5; /* RO [8-12] Number of timers provided */m unsign$ed hpetcap$v_count_siz_cap : 1; /* RO [13] Main counter size, 1 => 64 bits, 0 => 32 bits */N unsigned hpetcap$v_reserved_14 : 1; /* RO [14] */ unsigned hpetcap$v_leg_route_cap : 1; /* RO [15] If set, HPET supports legacy replacement interrupt route option */X unsigned short int hpetcap$iw_vendor_id; /* RO [16-31] 0x8086 means Intel */~ unsigned int hpetcap$il_counter_clk_period; /* RO [32-63] Main counter increment period in femtoseco %nds (1E-15) */ } hpetcap$r_caps; } hpetcap$r_cap_union; } HPET_CAPS; #if !defined(__VAXC)K#define hpetcap$iq_cap_register hpetcap$r_cap_union.hpetcap$iq_cap_registerL#define hpetcap$b_rev_id hpetcap$r_cap_union.hpetcap$r_caps.hpetcap$b_rev_idV#define hpetcap$v_num_tim_cap hpetcap$r_cap_union.hpetcap$r_caps.hpetcap$v_num_tim_capZ#define hpetcap$v_count_siz_cap hpetcap$r_cap_union.hpetcap$r_caps.hpetcap$v_count_siz_capZ#define hpetcap$v_leg_route_cap hpetcap$r_cap_ &union.hpetcap$r_caps.hpetcap$v_leg_route_capT#define hpetcap$iw_vendor_id hpetcap$r_cap_union.hpetcap$r_caps.hpetcap$iw_vendor_idf#define hpetcap$il_counter_clk_period hpetcap$r_cap_union.hpetcap$r_caps.hpetcap$il_counter_clk_period"#endif /* #if !defined(__VAXC) */ #define HCAP_SIZE$K_SIZE_32 0#define HCAP_SIZE$K_SIZE_64 1#define HCAP_LEG$K_IOAPIC 0#define HCAP_LEG$K_LEG_ROUTE 1N/* Fields of the HPET CONFIGURATION register. */N/* Only bit 0, ENABLE_CN 'F is meaningfully writable. For all other bits, */N/* while technically writable, the value written back should be the same */N/* as the value read. */ #define HPETCFG$M_ENABLE_CNF 0x1 #define HPETCFG$M_LEG_RT_CNF 0x2!#define HPETCFG$M_RESERVED_1 0xFC##define HPETCFG$M_RESERVED_2 0xFF00'#define HPETCFG$M_RESERVED_3 0xFFFF0000/#define HPETCFG$M_RESERVED_4 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__c (plusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _hpet_config {#pragma __nomember_alignment __union {1 unsigned __int64 hpetcfg$iq_cfg_register; __struct {X unsigned hpetcfg$v_enable_cnf : 1; /* RW [0] Master interrupt enable bit */^ unsigned hpetcfg$v_leg_rt_cnf : 1; /* RMW [1] Supports legacy replacement route */O unsigned hpetcfg$v )_reserved_1 : 6; /* RMW [2-7] pad out the byte */P unsigned hpetcfg$v_reserved_2 : 8; /* RMW [8-15] pad out the word */V unsigned hpetcfg$v_reserved_3 : 16; /* RMW [16-31] pad out the longword */V unsigned hpetcfg$v_reserved_4 : 32; /* RMW [32-63] pad out the quadword */ } hpetcfg$r_cfg; } hpetcfg$r_cfg_union; } HPET_CONFIG; #if !defined(__VAXC)K#define hpetcfg$iq_cfg_register hpetcfg$r_cfg_union.hpetcfg$iq_cfg_registerS#define hp *etcfg$v_enable_cnf hpetcfg$r_cfg_union.hpetcfg$r_cfg.hpetcfg$v_enable_cnfS#define hpetcfg$v_leg_rt_cnf hpetcfg$r_cfg_union.hpetcfg$r_cfg.hpetcfg$v_leg_rt_cnf"#endif /* #if !defined(__VAXC) */ #define HCFG_ENB$K_DISABLE 0#define HCFG_ENB$K_ENABLE 1N/* Fields of the HPET INTERRUPT_STATUS register. */N/* All fields in this structure are read/write with caveats. */V/* The interrupt status bits are cleared by writing a 1 to them. Writing a zero to +*/N/* them has no effect. */ #define HPETSTS$M_T0_INT_STS 0x1 #define HPETSTS$M_T1_INT_STS 0x2 #define HPETSTS$M_T2_INT_STS 0x4 #define HPETSTS$M_T3_INT_STS 0x8!#define HPETSTS$M_T4_INT_STS 0x10!#define HPETSTS$M_T5_INT_STS 0x20!#define HPETSTS$M_T6_INT_STS 0x40!#define HPETSTS$M_T7_INT_STS 0x80"#define HPETSTS$M_T8_INT_STS 0x100"#define HPETSTS$M_T9_INT_STS 0x200##define HPETSTS$M_T10_INT_STS 0x400##define HPETSTS$M_T11_INT_STS 0x,800$#define HPETSTS$M_T12_INT_STS 0x1000$#define HPETSTS$M_T13_INT_STS 0x2000$#define HPETSTS$M_T14_INT_STS 0x4000$#define HPETSTS$M_T15_INT_STS 0x8000%#define HPETSTS$M_T16_INT_STS 0x10000%#define HPETSTS$M_T17_INT_STS 0x20000%#define HPETSTS$M_T18_INT_STS 0x40000%#define HPETSTS$M_T19_INT_STS 0x80000&#define HPETSTS$M_T20_INT_STS 0x100000&#define HPETSTS$M_T21_INT_STS 0x200000&#define HPETSTS$M_T22_INT_STS 0x400000&#define HPETSTS$M_T23_INT_STS 0x800000'#define HPETSTS$M_T24_INT_ST-S 0x1000000'#define HPETSTS$M_T25_INT_STS 0x2000000'#define HPETSTS$M_T26_INT_STS 0x4000000'#define HPETSTS$M_T27_INT_STS 0x8000000(#define HPETSTS$M_T28_INT_STS 0x10000000(#define HPETSTS$M_T29_INT_STS 0x20000000(#define HPETSTS$M_T30_INT_STS 0x40000000(#define HPETSTS$M_T31_INT_STS 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif!type .def struct _hpet_int_status {#pragma __nomember_alignment __union {1 unsigned __int64 hpetsts$iq_sts_register; __struct { __union {c unsigned int hpetsts$il_tn_int_sts; /* Bit N set if interrupt active for timer N */ __struct {i unsigned hpetsts$v_t0_int_sts : 1; /* RW1C [0] Set if interrupt active for timer 0 */i unsigned hpetsts$v_t1_int_sts : 1; /* RW1C [1] Set if interrupt active/ for timer 1 */i unsigned hpetsts$v_t2_int_sts : 1; /* RW1C [2] Set if interrupt active for timer 2 */i unsigned hpetsts$v_t3_int_sts : 1; /* RW1C [3] Set if interrupt active for timer 3 */i unsigned hpetsts$v_t4_int_sts : 1; /* RW1C [4] Set if interrupt active for timer 4 */i unsigned hpetsts$v_t5_int_sts : 1; /* RW1C [5] Set if interrupt active for timer 5 */i unsigned hpetsts$v_t6_int_sts : 1; /0* RW1C [6] Set if interrupt active for timer 6 */i unsigned hpetsts$v_t7_int_sts : 1; /* RW1C [7] Set if interrupt active for timer 7 */i unsigned hpetsts$v_t8_int_sts : 1; /* RW1C [8] Set if interrupt active for timer 8 */i unsigned hpetsts$v_t9_int_sts : 1; /* RW1C [9] Set if interrupt active for timer 9 */l unsigned hpetsts$v_t10_int_sts : 1; /* RW1C [10] Set if interrupt active for timer 10 */l 1unsigned hpetsts$v_t11_int_sts : 1; /* RW1C [11] Set if interrupt active for timer 11 */l unsigned hpetsts$v_t12_int_sts : 1; /* RW1C [12] Set if interrupt active for timer 12 */l unsigned hpetsts$v_t13_int_sts : 1; /* RW1C [13] Set if interrupt active for timer 13 */l unsigned hpetsts$v_t14_int_sts : 1; /* RW1C [14] Set if interrupt active for timer 14 */l unsigned hpetsts$v_t15_int_sts : 1; /* RW1C [15] Set if interrupt 2active for timer 15 */l unsigned hpetsts$v_t16_int_sts : 1; /* RW1C [16] Set if interrupt active for timer 16 */l unsigned hpetsts$v_t17_int_sts : 1; /* RW1C [17] Set if interrupt active for timer 17 */l unsigned hpetsts$v_t18_int_sts : 1; /* RW1C [18] Set if interrupt active for timer 18 */l unsigned hpetsts$v_t19_int_sts : 1; /* RW1C [19] Set if interrupt active for timer 19 */l unsigned hpetsts$v_t203_int_sts : 1; /* RW1C [20] Set if interrupt active for timer 20 */l unsigned hpetsts$v_t21_int_sts : 1; /* RW1C [21] Set if interrupt active for timer 21 */l unsigned hpetsts$v_t22_int_sts : 1; /* RW1C [22] Set if interrupt active for timer 22 */l unsigned hpetsts$v_t23_int_sts : 1; /* RW1C [23] Set if interrupt active for timer 23 */l unsigned hpetsts$v_t24_int_sts : 1; /* RW1C [24] Set if interrupt active for timer 24 */4l unsigned hpetsts$v_t25_int_sts : 1; /* RW1C [25] Set if interrupt active for timer 25 */l unsigned hpetsts$v_t26_int_sts : 1; /* RW1C [26] Set if interrupt active for timer 26 */l unsigned hpetsts$v_t27_int_sts : 1; /* RW1C [27] Set if interrupt active for timer 27 */l unsigned hpetsts$v_t28_int_sts : 1; /* RW1C [28] Set if interrupt active for timer 28 */l unsigned hpetsts$v_t29_int_sts : 1; /* RW1C 5[29] Set if interrupt active for timer 29 */l unsigned hpetsts$v_t30_int_sts : 1; /* RW1C [30] Set if interrupt active for timer 30 */l unsigned hpetsts$v_t31_int_sts : 1; /* RW1C [31] Set if interrupt active for timer 31 */$ } hpetsts$r_int;& } hpetsts$r_int_union;N unsigned int hpetsts$il_reserved; /* RW0 [32-63] */ } hpetsts$r_sts; } hpetsts$r_sts_union; } HPET_INT_STATU6S; #if !defined(__VAXC)K#define hpetsts$iq_sts_register hpetsts$r_sts_union.hpetsts$iq_sts_registeri#define hpetsts$il_tn_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$il_tn_int_stsu#define hpetsts$v_t0_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t0_int_stsu#define hpetsts$v_t1_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t1_int_stsu#define hpetsts$v_t2_int_sts hpetsts$r_sts_union.h7petsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t2_int_stsu#define hpetsts$v_t3_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t3_int_stsu#define hpetsts$v_t4_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t4_int_stsu#define hpetsts$v_t5_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t5_int_stsu#define hpetsts$v_t6_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int8_union.hpetsts$r_int.hpetsts$v_t6_int_stsu#define hpetsts$v_t7_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t7_int_stsu#define hpetsts$v_t8_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t8_int_stsu#define hpetsts$v_t9_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t9_int_stsw#define hpetsts$v_t10_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpet9sts$v_t10_int_stsw#define hpetsts$v_t11_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t11_int_stsw#define hpetsts$v_t12_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t12_int_stsw#define hpetsts$v_t13_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t13_int_stsw#define hpetsts$v_t14_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t14_int_sts:w#define hpetsts$v_t15_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t15_int_stsw#define hpetsts$v_t16_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t16_int_stsw#define hpetsts$v_t17_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t17_int_stsw#define hpetsts$v_t18_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t18_int_stsw#define hpetsts$;v_t19_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t19_int_stsw#define hpetsts$v_t20_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t20_int_stsw#define hpetsts$v_t21_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t21_int_stsw#define hpetsts$v_t22_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t22_int_stsw#define hpetsts$v_t23_int_sts hpet<sts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t23_int_stsw#define hpetsts$v_t24_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t24_int_stsw#define hpetsts$v_t25_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t25_int_stsw#define hpetsts$v_t26_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t26_int_stsw#define hpetsts$v_t27_int_sts hpetsts$r_sts_union.hp=etsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t27_int_stsw#define hpetsts$v_t28_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t28_int_stsw#define hpetsts$v_t29_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t29_int_stsw#define hpetsts$v_t30_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetsts$r_int_union.hpetsts$r_int.hpetsts$v_t30_int_stsw#define hpetsts$v_t31_int_sts hpetsts$r_sts_union.hpetsts$r_sts.hpetst >s$r_int_union.hpetsts$r_int.hpetsts$v_t31_int_sts"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEG#pragma __required_pointer_size __save /* Save current pointer size */A#pragma __required_pointer_size __long /* Pointers are 64-bit */=typedef HPET * HPET_PQ; /* Pointer to an HPET structure */Mtypedef HPET_TIMER * HPET_TIMER_PQ; /* Pointer to an HPET_TIMER structure */O#pragma __required_pointer_size __restore /* Return to previous pointer size */#else!ty?pedef unsigned __int64 HPET_PQ;'typedef unsigned __int64 HPET_TIMER_PQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HPETDEF_LOADED */ ww`6[UM/*************************************@**************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP A **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** B **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */F/* Source: 17-AUG-2016 13:23:20 $1$DGA8345:[LIB_H.SRC]HQBDEF.SDL;1 *//*************************************************************************************** C*****************************************//*** MODULE $HQBDEF ***/#ifndef __HQBDEF_LOADED#define __HQBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr sizDe default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ E */N/* HQB (Host Queue Block) Definitions */N/* */I/* This data structure contains information pertaining */I/* to a host that has established a connection to the */I/* server. */N/*- F */ #define HQB$M_VC_FAILED 0x1#define HQB$M_DISCON_INIT 0x2#define HQB$M_PATHMOVE 0x4#define HQB$M_UNIT_ONLINE 0x1#define HQB$M_V5CL 0x2#define HQB$M_HUNN 0x4#define HQB$M_64LBN 0x8#define HQB$K_LENGTH 72#define HQB$S_HQBDEF 72  9#ifdef __cplusplus /* Define structure prototypes */ struct _hrb; struct _cdt; struct _dsrv; struct _tsrv; #endif /* #ifdef __cplusplus */ typedef struct _hqb {N struct _hqb *hqb$l_flink; /* Used to lGink together all */N struct _hqb *hqb$l_blink; /* host HQBs using the server */N unsigned short int hqb$w_size; /* Structure size in bytes */N unsigned char hqb$b_type; /* MSCP type structure */N unsigned char hqb$b_subtype; /* with a HQB subtype (2) */N unsigned char hqb$b_hostno; /* Assigned host number */ __union {N unsigned char hqb$b_state; /* State of this host H */ __struct {O unsigned hqb$v_vc_failed : 1; /* The VC to this host has failed */N unsigned hqb$v_discon_init : 1; /* Disconnect being processed */Z unsigned hqb$v_pathmove : 1; /* Closing connection for port load balancing */' unsigned hqb$v_fill_4_ : 5; } hqb$r_fill_1_; } hqb$r_fill_0_;N unsigned short int hqb$w_cnt_flgs; /* Host settable controller flags */N unsigned short int hqb$w_htimo I; /* Host access timeout interval */ __union {' unsigned short int hqb$w_flags; __struct {N unsigned hqb$v_unit_online : 1; /* This host had units online */N unsigned hqb$v_v5cl : 1; /* This is the V5 class driver */N unsigned hqb$v_hunn : 1; /* Class driver knows new naming */N unsigned hqb$v_64lbn : 1; /* Class driver knows 64 bit LBNs */' unsigned hqb$v_fill_5_ : 4; } hqb$Jr_fill_3_; } hqb$r_fill_2_;N/* when the link was broken */N unsigned __int64 hqb$q_time; /* Time host issued set-ctrl-chr */N unsigned short int hqb$w_num_que; /* Requests outstanding */N unsigned short int hqb$w_max_que; /* Most requests ever out */N struct _hrb *hqb$l_hrb_fl; /* HRB queue listhead for */N struct _hrb *hqb$l_hrb_bl; /* this host K */N struct _cdt *hqb$l_cdt; /* Connection Desc Table addr */N struct _dsrv *hqb$l_dsrv; /* DSRV address */N unsigned char hqb$b_systemid [6]; /* SCS system ID of host */N unsigned short int hqb$w_max_hulb; /* Size of HULB vector */N void *hqb$l_hulb_vector; /* HULB vector address */N struct _tsrv *hqb$l_tsrv; /* TSRV address */Q unsigned i Lnt hqb$l_ack_time; /* Time stamp form last remote request */Q unsigned int hqb$l_arr_time; /* Round trip time from server to host */ } HQB; #if !defined(__VAXC)-#define hqb$b_state hqb$r_fill_0_.hqb$b_stateC#define hqb$v_vc_failed hqb$r_fill_0_.hqb$r_fill_1_.hqb$v_vc_failedG#define hqb$v_discon_init hqb$r_fill_0_.hqb$r_fill_1_.hqb$v_discon_initA#define hqb$v_pathmove hqb$r_fill_0_.hqb$r_fill_1_.hqb$v_pathmove-#define hqb$w_flags hqb$r_fill_2_.hqb$w_flagsG#defin Me hqb$v_unit_online hqb$r_fill_2_.hqb$r_fill_3_.hqb$v_unit_online9#define hqb$v_v5cl hqb$r_fill_2_.hqb$r_fill_3_.hqb$v_v5cl9#define hqb$v_hunn hqb$r_fill_2_.hqb$r_fill_3_.hqb$v_hunn;#define hqb$v_64lbn hqb$r_fill_2_.hqb$r_fill_3_.hqb$v_64lbn"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptrN size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HQBDEF_LOADED */ wwE7[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosedO to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **P/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3 Q.7 */F/* Source: 20-SEP-2020 01:34:37 $1$DGA8345:[LIB_H.SRC]HRBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $HRBDEF ***/#ifndef __HRBDEF_LOADED#define __HRBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size prRagmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_structS#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* HRB (Host Request Block) Definitions */N/* */I/* These definitions describe the format of a data structure */I/* that is used in the MSCP server to represenTt the context */I/* of a request from one of the served hosts. */N/*- */ "#define HRB$M_STATE_INVALID 0x8000#define HRB$M_ABORT 0x1#define HRB$M_ABORTWS 0x2#define HRB$M_DEQUEUED 0x4#define HRB$M_ENDMSG 0x8#define HRB$M_MAP 0x10#define HRB$M_UNBLOCK 0x20#define HRB$M_VCFAILED 0x40#define HRB$M_OLDBUF 0x80#define HRB$M_WBC_IMMED 0x100#define HRB$M_FIRST 0x200#d Uefine HRB$M_FLUSH 0x400#define HRB$M_CMD_TMO 0x800#define HRB$K_LENGTH 148N/* request state definitions */N#define HRB$K_ST_MSG_WAIT 1 /* Atn msg buffer/credit wait */N#define HRB$K_ST_SEQ_WAIT 2 /* Waiting for sequential cmd */N#define HRB$K_ST_BUF_WAIT 3 /* Waiting for server buffer */N#define HRB$K_ST_SNDAT_WAIT 4 /* Sending or receiving data */N#define HRB$K_ST_DRV_WAIVT 5 /* Driver queue */N#define HRB$K_ST_MAP_WAIT 6 /* Mapping a data buffer */N#define HRB$K_ST_UNMAP_WAIT 7 /* Returning mapping resources */N#define HRB$K_ST_SNDMS_WAIT 8 /* Sending message */N#define HRB$K_ST_MEM_WAIT 9 /* Local buffer wait */N#define HRB$K_ST_FLUSHED 10 /* Flushed from cache */N#define HRB$K_ST_CACHED 11 /* In locaWl host cache */N#define HRB$S_HRBDEF 148 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _mscp; struct _cdrp; struct _hqb; struct _uqb; struct _pdt; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endiftypedef struct _hrb {#pXragma __nomember_alignmentN void *hrb$l_flink; /* Used to link this request */N void *hrb$l_blink; /* into the HQB data styructure */N unsigned short int hrb$w_size; /* Data structure size in bytes */N unsigned char hrb$b_type; /* This is an MSCP type struct */N unsigned char hrb$b_subtype; /* with a HRB subtype (3) */N int (*hrb$l_respc)(); /* PC to resume on restart */ YN int (*hrb$l_savd_rtn)(); /* Saved address of caller */ __union {N unsigned short int hrb$w_state; /* State of the request */ __struct {N unsigned hrb$v_filler : 15; /* Filled by constant below */Q unsigned hrb$v_state_invalid : 1; /* State is current but previous */ } hrb$r_fill_1_; } hrb$r_fill_0_;N/* state was (bits 0-15) */ __Zunion {N unsigned short int hrb$w_flags; /* Status flags */ __struct {N unsigned hrb$v_abort : 1; /* Abort */N unsigned hrb$v_abortws : 1; /* Abort with status */N unsigned hrb$v_dequeued : 1; /* Removed from resource queues */N unsigned hrb$v_endmsg : 1; /* End message needs to be sent */N unsigned hrb$v_map : 1; /* Map resources allocated [ */N unsigned hrb$v_unblock : 1; /* Unblock needs to be called */N unsigned hrb$v_vcfailed : 1; /* The VC for this host failed */N unsigned hrb$v_oldbuf : 1; /* The buffer allocated for this */N/* rqst is out of the old buffer */N unsigned hrb$v_wbc_immed : 1; /* Write-back caching command */O unsigned hrb$v_first : 1; /* First in burst sequence for tapes */N unsign \ed hrb$v_flush : 1; /* This is a flush type command */N unsigned hrb$v_cmd_tmo : 1; /* This command has "timed out" */' unsigned hrb$v_fill_6_ : 4; } hrb$r_fill_3_; } hrb$r_fill_2_;N struct _mscp *hrb$l_msgbuf; /* Addr of MSCP request packet */N struct _cdrp *hrb$l_irp_cdrp; /* CDRP for I/O requests */N unsigned char hrb$b_lbuff [12]; /* Local buffer descriptor */N void *hrb$l_bd_addr; ] /* Buffer Descriptor Address */N unsigned int hrb$l_buflen; /* Length of buffer allocated */N void *hrb$l_bufadr; /* Buffer starting address */ __union {N unsigned __int64 hrb$q_lbn; /* LBN place holder for xfr */ __struct {# unsigned int hrb$l_lbn; } hrb$r_fill_5_; } hrb$r_fill_4_;N unsigned int hrb$l_obcnt; /* Original request byte count */N ^ unsigned int hrb$l_abcnt; /* Number of bytes already sent */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *hrb$pq_svapte_sva; /* NOSVAPTE_V9.0 cmo _s */#else$ unsigned __int64 hrb$pq_svapte_sva;#endif#pragma __nomember_alignmentN unsigned int hrb$l_bcnt; /* Temp storage for current xfr */N unsigned short int hrb$w_boff; /* Offset within page of sob */N unsigned short int hrb$w_reserved; /* */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bi `t pointers */#endifN void *hrb$l_wait_fl; /* Pointers to link HRB into */N void *hrb$l_wait_bl; /* wait queues in UQB */N struct _hqb *hrb$l_hqb; /* Host Queue Block address */N struct _uqb *hrb$l_uqb; /* Unit Queue Block address */N struct _pdt *hrb$l_pdt; /* Port Desc Table for requestor */N unsigned int hrb$l_cmd_sts; /* Measure of work to be done */N a unsigned int hrb$l_object_skip; /* Objects requested for skipfile */N unsigned int hrb$l_current_skip; /* Placemarker during REPOS */N unsigned int hrb$l_io_time; /* Time for I/O to go from */N/* server to tape and back */N void *hrb$l_cache_fl; /* Cache queue */N void *hrb$l_cache_bl; /* */N void *hrb$l_memw_fl; b /* Waiting on more memory */N void *hrb$l_memw_bl; /* */N unsigned int hrb$l_record; /* Record position on tape */N unsigned int hrb$l_cmd_time; /* Record timestamp */ char hrb$b_fill_7_ [12]; } HRB; #if !defined(__VAXC)-#define hrb$w_state hrb$r_fill_0_.hrb$w_stateK#define hrb$v_state_invalid hrb$r_fill_0_.hrb$r_fill_1_.hrb$v_state_invalid-#define hrb$w_flags chrb$r_fill_2_.hrb$w_flags;#define hrb$v_abort hrb$r_fill_2_.hrb$r_fill_3_.hrb$v_abort?#define hrb$v_abortws hrb$r_fill_2_.hrb$r_fill_3_.hrb$v_abortwsA#define hrb$v_dequeued hrb$r_fill_2_.hrb$r_fill_3_.hrb$v_dequeued=#define hrb$v_endmsg hrb$r_fill_2_.hrb$r_fill_3_.hrb$v_endmsg7#define hrb$v_map hrb$r_fill_2_.hrb$r_fill_3_.hrb$v_map?#define hrb$v_unblock hrb$r_fill_2_.hrb$r_fill_3_.hrb$v_unblockA#define hrb$v_vcfailed hrb$r_fill_2_.hrb$r_fill_3_.hrb$v_vcfailed=#define hrb$v_oldbuf hrb$r d_fill_2_.hrb$r_fill_3_.hrb$v_oldbufC#define hrb$v_wbc_immed hrb$r_fill_2_.hrb$r_fill_3_.hrb$v_wbc_immed;#define hrb$v_first hrb$r_fill_2_.hrb$r_fill_3_.hrb$v_first;#define hrb$v_flush hrb$r_fill_2_.hrb$r_fill_3_.hrb$v_flush?#define hrb$v_cmd_tmo hrb$r_fill_2_.hrb$r_fill_3_.hrb$v_cmd_tmo)#define hrb$q_lbn hrb$r_fill_4_.hrb$q_lbn7#define hrb$l_lbn hrb$r_fill_4_.hrb$r_fill_5_.hrb$l_lbn"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTERe_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HRBDEF_LOADED */ ww7[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietfary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** prgoprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************* h*************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */G/* Source: 22-APR-1993 11:03:44 $1$DGA8345:[LIB_H.SRC]HULBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $HULBDEF ***/#ifndef __HULBDEF_LOADED#define __HULBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSIi-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_paramsj#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* HULB (Host/Unit Load Block) Definitions */N/* k */I/* These definitions describe the format of a data structure */I/* that is used in the MSCP server to record traffic and status */I/* information used by server load balancing. Time fields are in */I/* EXE$GL_ABSTIM format. */N/*- */ #define HULB$M_LB_REQ 0x1#define HULB$M_DELETE 0x2#define HULB$M_LB_DISABLED 0x4 l#define HULB$K_LENGTH 28#define HULB$K_VECLEN 256#define HULB$S_HULBDEF 28 typedef struct _hulb {N void *hulb$l_flink; /* Used to link this request */N void *hulb$l_blink; /* into the DSRV data styructure */N unsigned short int hulb$w_size; /* Data structure size in bytes */N unsigned char hulb$b_type; /* This is an MSCP type struct */N unsigned char hulb$b_subtype; /* with a HULB subtype (4) m */N unsigned short int hulb$w_hostno; /* Assigned host number */N unsigned short int hulb$w_unitno; /* Assigned unit number */N unsigned short int hulb$w_opcount; /* Current operation count */O unsigned short int hulb$w_prev_opc; /* Operation count for prev interval */N unsigned int hulb$l_time; /* Time of last LB request */ __union {N unsigned short int hulb$w_status; /* LB status bits */ n __struct {N unsigned hulb$v_lb_req : 1; /* This unit has been asked to LB */^ unsigned hulb$v_delete : 1; /* This unit is offline and the HULB can be deleted */` unsigned hulb$v_lb_disabled : 1; /* This unit is not available for load balancing */( unsigned hulb$v_fill_2_ : 5; } hulb$r_fill_1_; } hulb$r_fill_0_;N unsigned short int hulb$w_reserved; /* Reserved for alignment */ } HULB; #if !defined o(__VAXC)2#define hulb$w_status hulb$r_fill_0_.hulb$w_statusA#define hulb$v_lb_req hulb$r_fill_0_.hulb$r_fill_1_.hulb$v_lb_reqA#define hulb$v_delete hulb$r_fill_0_.hulb$r_fill_1_.hulb$v_deleteK#define hulb$v_lb_disabled hulb$r_fill_0_.hulb$r_fill_1_.hulb$v_lb_disabled"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previpously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HULBDEF_LOADED */ ww7[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be uqsed, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosred to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-202 s4 15:22:23 by OpenVMS SDL V3.7 */H/* Source: 13-DEC-2020 08:21:02 $1$DGA8345:[LIB_H.SRC]HWPRTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $HWPRTDEF ***/#ifndef __HWPRTDEF_LOADED#define __HWPRTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZtE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#elseu#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* Protection field definitions. These encodings are specific */N/* to the architecture and should only be used for privileged */N/* interfaces. */N/* v */N/* The definitions here specify the contents of the PROT field */N/* in a PTE, and as it says just above, are architecture */N/* specific. */N/* */N/* For protection encodings available at the system-service */N/* interface, see PRTDEF in STARwLET. */N/* */N/* For protection codes ready to OR directly into a zeroed PTE */N/* (rather than assign to the PROT field), see PTEDEF. */N/* */N/* For X86, the HWPRT$C_NA protection of No Access is not a */N/* protection that can be specified within a valid PTE. Ax */N/* request for a No Access protection will result in the */N/* page being marked as invalid. */N/*- */`#define HWPRT$C_HWPRT -2147483648 /* Identify protection argument as HW protection form */`#define HWPRT$M_HWPRT -2147483648 /* Identify protection argument as HW protection form */N/* Verified for x86 port--Drew Mason y */N#define HWPRT$C_NA 0 /* No Access */N#define HWPRT$C_KR 3 /* Kernel Read only (execute) */N#define HWPRT$C_ER 7 /* Exec Read only (execute) */N#define HWPRT$C_SR 11 /* Super Read only (execute) */N#define HWPRT$C_UR 15 /* User Read only (execute) */N#define HWPRT$C_KW 18 /* Kernel Write (no execute) z */N#define HWPRT$C_EW 21 /* Exec Write (no execute) */N#define HWPRT$C_SW 24 /* Super Write (no execute) */N#define HWPRT$C_UW 20 /* User Write (no execute) */N/* */\/* SRKW and URKW differ from IA64 in that they are no execute; see SRKWX and URKWX, below */N/* */Q#defin{e HWPRT$C_ERKW 22 /* Exec Read Kernel Write (no execute) */R#define HWPRT$C_SRKW 26 /* Super Read Kernel Write (no execute) */P#define HWPRT$C_SREW 25 /* Super Read Exec Write (no execute) */Q#define HWPRT$C_URKW 30 /* User Read Kernel Write (no execute) */O#define HWPRT$C_UREW 29 /* User Read Exec Write (no execute) */P#define HWPRT$C_URSW 28 /* User Read Super Write (no execute) */N/* | */N/* These protection encodings are not VAX / Alpha compatible: */N/* */N#define HWPRT$C_KRO 19 /* Kernel Read only (no execute) */N#define HWPRT$C_ERO 23 /* Exec Read only (no execute) */N#define HWPRT$C_SRO 27 /* Super Read only (no execute) */N#define HWPRT$C_URO 31 }/* User Read only (no execute) */N#define HWPRT$C_KWX 2 /* Kernel Write (execute) */N#define HWPRT$C_EWX 5 /* Exec Write (execute) */N#define HWPRT$C_SWX 8 /* Super Write (execute) */N#define HWPRT$C_UWX 4 /* User Write (execute) */N/* */N/* These protection encodings are not VAX / Alpha / IA64 compatibl~e: */N/* */N#define HWPRT$C_ERKWX 6 /* Exec Read Kernel Write (execute) */O#define HWPRT$C_SRKWX 10 /* Super Read Kernel Write (execute) */N#define HWPRT$C_SREWX 9 /* Super Read Exec Write (execute) */N#define HWPRT$C_URKWX 14 /* User Read Kernel Write (execute) */N#define HWPRT$C_UREWX 13 /* User Read Exec Write (execute) */N#define HWPRT$C_URSWX 12 /* User Read Super Write (execute) */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HWPRTDEF_LOADED */ ww/8[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/**  **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/**  **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */H/* Source: 15-MAY-2024 10:40:00 $1$DGA8345:[LIB_H.SRC]HWRPBDEF.SDL;1 *//********************************************************************************************************************************/ /*** MODULE $HWRPBDEF ***/#ifndef __HWRPBDEF_LOADED#define __HWRPBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#e ndif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #ifdef EFI64#pragma pack(push,hwrpbdef)#pragma pack(8) #pragma warning(disable:4068)#endifN/********** X86_64 SECTION ************************************************ */N/* Verified for X86_64 port - GM Newsted */N/********** CONSTANTS ***************************************************** */(#define HWRPB_BOOT_FLAGS$M_SYSPROMPT 0x1%#define HWRPB_BOOT_FLAGS$M_XDELTA 0x2)#define HWRPB_BOOT_FLAGS$M_BREAKPOINT 0x4%#define HWRPB_BOOT_FLAGS$M_DK_SDA 0x8(#define HWRPB_BOOT_FLAGS$M_PROGRESS 0x10'#define HWRPB_BOOT _FLAGS$M_SYSBOOT 0x20(#define HWRPB_BOOT_FLAGS$M_EXECINIT 0x40'#define HWRPB_BOOT_FLAGS$M_SYSINIT 0x80'#define HWRPB_BOOT_FLAGS$M_DRIVER 0x100'#define HWRPB_BOOT_FLAGS$M_SHADOW 0x200(#define HWRPB_BOOT_FLAGS$M_NETBOOT 0x400)#define HWRPB_BOOT_FLAGS$M_SYSDEBUG 0x800&#define HWRPB_BOOT_FLAGS$M_ACPI 0x1000+#define HWRPB_BOOT_FLAGS$M_HW_CONFIG 0x2000-#define HWRPB_BOOT_FLAGS$M_PAGE_FAULTS 0x4000&#define HWRPB_BOOT_FLAGS$M_HALT 0x8000,#define HWRPB_BOOT_FLAGS$M_DK_NOSYSD 0x10000)#define HWRPB_BOOT_FLAGS$M_X20000 0x20000)#define HWRPB_BOOT_FLAGS$M_X40000 0x40000)#define HWRPB_BOOT_FLAGS$M_X80000 0x80000+#define HWRPB_BOOT_FLAGS$M_X100000 0x100000+#define HWRPB_BOOT_FLAGS$M_X200000 0x200000+#define HWRPB_BOOT_FLAGS$M_X400000 0x400000-#define HWRPB_BOOT_FLAGS$M_OPDISPLAY 0x800000,#define HWRPB_BOOT_FLAGS$M_BOOTMGR 0x1000000-#define HWRPB_BOOT_FLAGS$M_MEMCHECK 0x2000000-#define HWRPB_BOOT_FLAGS$M_DEVCHECK 0x4000000.#define HWRPB_BOOT_FLAGS$M_DEVELOPER 0x8000000-#defin e HWRPB_BOOT_FLAGS$M_MDCHECK 0x10000000.#define HWRPB_BOOT_FLAGS$M_CPUCHECK 0x20000000/#define HWRPB_BOOT_FLAGS$M_X40000000 0x40000000-#define HWRPB_BOOT_FLAGS$M_VERBOSE 0x80000000*#define HWRPB_BOOT_FLAGS$M_ROOT 0xFFFF0000"#define HWRPB_SYSTYPE$K_GENERIC 64'#define HWRPB_SYSTYPE$K_X86_GENERIC 128%#define HWRPB_SYSTYPE$K_X86_INTEL 129##define HWRPB_SYSTYPE$K_X86_AMD 130'#define HWRPB_SYSTYPE$K_MAX_SYSTYPE 130 #define HWRPB_SYSVAR$M_MPCAP 0x1!#define HWRPB_SYSVAR$M_CNSLE 0x1E$#defin e HWRPB_SYSVAR$M_KEYBOARD 0xE0%#define HWRPB_SYSVAR$M_DUMPBOOT 0x100%#define HWRPB_SYSVAR$M_GRAPHICS 0x200'#define HWRPB_SYSVAR$M_MEMBER_ID 0xFC00 #define HWRPB_SYSVAR$M_FILL1 0x1&#define HWRPB_SYSVAR$M_RXTX_EXTENT 0x2 #define HWRPB_VM_CONFIG$K_NONE 0##define HWRPB_VM_CONFIG$K_HD_BOOT 1(#define HWRPB_VM_CONFIG$K_DVD_ISO_BOOT 2'#define HWRPB_VM_CONFIG$K_HD_ISO_BOOT 3(#define HWRPB_VM_CONFIG$K_NET_ISO_BOOT 4(#define HWRPB_VM_CONFIG$K_NET_IMG_BOOT 5'#define HWRPB_VM_CONFIG$K_NET_MD_BOOT 6#define HWRPB_KEYBOARD$K_NONE 0#define HWRPB_KEYBOARD$K_PS2 1#define HWRPB_KEYBOARD$K_USB 2!#define HWRPB_KEYBOARD$K_SERIAL 3#define HWRPB_VM_TYPE$K_NONE 0 #define HWRPB_VM_TYPE$K_VMWARE 1#define HWRPB_VM_TYPE$K_KVM 2$#define HWRPB_VM_TYPE$K_VIRTUALBOX 3#define HWRPB_VM_TYPE$K_XEN 4!#define HWRPB_VM_TYPE$K_HYPER_V 5!#define HWRPB_MEMBER_ID$K_INTEL 1#define HWRPB_MEMBER_ID$K_AMD 2N/************************************************************************** */'#define HWRPB_TXRDY$M_TXRDY_SUMMARY 0x1!#define HWRPB_BOOTDEV$M_FUNCT 0x7##define HWRPB_BOOTDEV$M_DEVICE 0xF8"#define HWRPB_BOOTDEV$M_BUS 0xFF00%#define HWRPB_BOOTDEV$M_HOSE 0xFF00000#define HWRPB_BOOTDEV$M_PCINODE_FILL1 0xFF000000 #define HWRPB_ALTDEV$M_FUNCT 0x7"#define HWRPB_ALTDEV$M_DEVICE 0xF8!#define HWRPB_ALTDEV$M_BUS 0xFF00$#define HWRPB_ALTDEV$M_HOSE 0xFF0000/#define HWRPB_ALTDEV$M_ALTNODE_FILL1 0xFF000000(#define HWRPB_UART_PCICFG$M_FUNCTION 0x7'#define HWRPB_UART_PCICFG$M_DEVICE 0xF8& #define HWRPB_UART_PCICFG$M_BUS 0xFF00-#define HWRPB_UART_PCICFG$M_OFFSET 0xFFFF0000'#define HWRPB_VGA_PCICFG$M_FUNCTION 0x7&#define HWRPB_VGA_PCICFG$M_DEVICE 0xF8%#define HWRPB_VGA_PCICFG$M_BUS 0xFF00,#define HWRPB_VGA_PCICFG$M_OFFSET 0xFFFF0000$#define HWRPB_VGA_FLAG$M_CONSOLE 0x1'#define HWRPB_VGA_FLAG$M_GC_CONSOLE 0x2'#define HWRPB_VGA_FLAG$M_GC_BIGFONT 0x4 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_ali gnment __octaword#else#pragma __nomember_alignment#endiftypedef struct _hwrpb {N/************************************************************************** */N/* [X86-64] HWRPB-Related Items */N/************************************************************************** */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size  default to 64-bit pointers */I void *hwrpb$pq_base; /* Booted HWRPB PA */#else unsigned __int64 hwrpb$pq_base;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */I void *hwrpb$pq_vbase; /* Booted HWRPB VA */#else! unsigned __int64 hwrpb$pq_vbase;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *hwrpb$pq_alt_hwrpb; /* Alt kernel HWRPB */#else% unsigned __int64 hwrpb$pq_alt_hwrpb;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *hwrpb$pq_swrpb; /* Ptr to SWRPB  */#else! unsigned __int64 hwrpb$pq_swrpb;#endifN unsigned __int64 hwrpb$iq_size; /* Size of HWRPB */B unsigned __int64 hwrpb$iq_ident; /* Sig "X86_RPB\0" */F unsigned __int64 hwrpb$iq_revision; /* 1 for VMS9.1 X86_64 */N/************************************************************************** */N/* [X86-64] MACHINE DETAILS */N/************************************************************************** */F unsigned __int64 hwrpb$iq_primary; /* Primary CPU ID/Slot */N unsigned __int64 hwrpb$iq_nproc; /* Number of Per-CPU slots */G unsigned __int64 hwrpb$iq_clock_int_freq; /* Clock intr freq */N unsigned __int64 hwrpb$iq_itc_freq; /* TSC update intr freq */L unsigned __int64 hwrpb$iq_cycle_count_freq; /* Cycle Counter freq */N unsigned __int64 hwrpb$iq_com_port_number; /* Selected COM Port */N unsigned __int64 hwrpb$iq_com_port_reg; /* Selected COM Port Reg */N unsigned int hwrpb$il_horiz_rez; /* Display Width or zero */N unsigned int hwrpb$il_vert_rez; /* Display Height or zero */N/************************************************************************** */N/* [X86-64] ADDRESSES AND APPLICABLE SIZES */N/************************************************************************** */N unsigned __int64 hwrpb$iq_framebuffer_pa; /* PA of Framebuffer or NULL */Q unsigned __int64 hwrpb$iq_framebuffer_size; /* Size of Framebuffer or zero */P unsigned __int64 hwrpb$iq_conio_base_pa; /* PA of Console Service Table */N unsigned __int64 hwrpb$iq_st_base_pa; /* PA of UEFI Service Table */C unsigned __int64 hwrpb$iq_sysboot_pa; /* PA of SYSBOOT */M unsigned __int64 hwrpb$iq_sysboot_size; /* Size of SYSBOOT */J unsigned __int64 hwrpb$iq_memdisk_pa; /* PA of MEMDISK */N unsigned __int64 hwrpb$iq_memdisk_size; /* Size of MEMDISK */E unsigned __int64 hwrpb$iq_mmap_pa; /* PA of UEFI Memory Map */N unsigned __int64 hwrpb$iq_mmap_size; /* Size of Memory Map */N unsigned __int64 hwrpb$iq_mmap_entry_size; /* Size of Memory Map Entry */H unsigned __int64 hwrpb$iq_mmap_key; /* Memory Map Key */L unsigned int hwrpb$il_mmap_version; /* Memory Map Version */N unsigned int hwrpb$il_mmap_rsvd; /* For alignment */K unsigned __int64 hwrpb$iq_acpi_rsdp_pa; /* PA of ACPI RSDP Table */G unsigned __int64 hwrpb$iq_restart; /* VA of Restart Routine */Q unsigned __int64 hwrpb$iq_dump_transfer_pa; /* PA of Dump Kernel Transfer */N unsigned __int64 hwrpb$iq_hpet_base_pa; /* PA of Clock Registers */N/************************************************************************** */N/* [X86-64] BOOT FLAGS & BOOT RELATED ITEMS  */N/************************************************************************** */ __union {- unsigned __int64 hwrpb$iq_boot_flags; __struct { __union {3 unsigned int hwrpb$il_boot_flags_l; __struct {_ unsigned hwrpb_boot_flags$v_sysprompt : 1; /* <0>1 SYSBOOT> Conversation */Z unsigned hwrpb_boot_flags$v_xdelta : 1; /* <1>2 Load XDELTA execlet */b unsigned hwrpb_boot_flags$v_breakpoint : 1; /* <2>4 Breakpoint in X(L)DELTA */e unsigned hwrpb_boot_flags$v_dk_sda : 1; /* <3>8 Dump Kernel only: activate SDA */` unsigned hwrpb_boot_flags$v_progress : 1; /* <4>10 Boot Progress Messages */Y unsigned hwrpb_boot_flags$v_sysboot : 1; /* <5>20 SYSBOOT Messages */[ unsigned hwrpb_boot_flags$v_execinit : 1; /* <6>40 EXECINIT Messages */\ unsigned hwrpb_boot_flags$v_sysinit : 1; /* <7>80 SYSINIT Messages */X unsigned hwrpb_boot_flags$v_driver : 1; /* <8>100 DRIVER Messages */] unsigned hwrpb_boot_flags$v_shadow : 1; /* <9>200 Boot from shadow set */c unsigned hwrpb_boot_flags$v_netboot : 1; /* <10>400 Boot from network device */i unsigned hwrpb_boot_flags$v_sysdebug : 1; /* <11>800 Load the System Code Debugger */] unsigned hwrpb_boot_flags$v_acpi : 1; /* <12>1000 ACPI Config Messages */` unsigned hwrpb_boot_flags$v_hw_config : 1; /* <13>2000 HW Config Messages */o unsigned hwrpb_boot_flags$v_page_faults : 1; /* <14>4000 issue TR_PRINTs for page faults */h unsigned hwrpb_boot_flags$v_halt : 1; /* <15>8000 Halt before transfer to SYSBOOT */r unsigned hwrpb_boot_flags$v_dk_nosysd : 1; /* <16>10000 Dump Kernel only: avoid System Disk */Q unsigned hwrpb_boot_flags$v_x20000 : 1; /* <17>20000 Spare */Q unsigned hwrpb_boot_flags$v_x40000 : 1; /* <18>40000 Spare */Q unsigned hwrpb_boot_flags$v_x80000 : 1; /* <19>80000 Spare */S unsigned hwrpb_boot_flags$v_x100000 : 1; /* <20>100000 Spare */S unsigned hwrpb_boot_flags$v_x200000 : 1; /* <21>200000 Spare */S unsigned hwrpb_boot_flags$v_x400000 : 1; /* <22>400000 Spare */p unsigned hwrpb_boot_flags$v_opdisplay : 1; /* <23>800000 Display OPA0 messages after boot */d unsigned hwrpb_boot_flags$v_bootmgr : 1; /* <24>1000000 BOOTMGR> Conversation */c unsigned hwrpb_boot_flags$v_memcheck : 1; /* <25>2000000 BootMgr Memory Info */c unsigned hwrpb_boot_flags$v_devcheck : 1; /* <26>4000000 BootMgr Device Info */d unsigned hwrpb_boot_flags$v_developer : 1; /* <27>8000000 Developer Functions */e unsigned hwrpb_boot_flags$v_mdcheck : 1; /* <28>10000000 MemoryDisk Diagnostic */d unsigned hwrpb_boot_flags$v_cpucheck : 1; /* <29>20000000 CPU Init Diagnostic */W unsigned hwrpb_boot_flags$v_x40000000 : 1; /* <30>40000000 Spare */` unsigned hwrpb_boot_flags$v_verbose : 1; /* <31>80000000 Verbose Messages */1 } hwrpb$r_boot_flags_field_l;/ } hwrpb$r_boot_flags_overlay_l; __union {3  unsigned int hwrpb$il_boot_flags_h; __struct {E unsigned hwrpb_boot_flags$v_boot_flags_fill : 16;N unsigned hwrpb_boot_flags$v_root : 16; /* System Root */1 } hwrpb$r_boot_flags_field_h;/ } hwrpb$r_boot_flags_overlay_h;( } hwrpb$r_boot_flags_fields;% } hwrpb$r_boot_flags_overlay;N __union { /* USB Boot Device */, unsign ed __int64 hwrpb$iq_usb_flags; __struct {5 unsigned short int hwrpb_usb$w_vendor_id;6 unsigned short int hwrpb_usb$w_product_id;6 unsigned char hwrpb_usb$b_interface_class;9 unsigned char hwrpb_usb$b_interface_subclass;9 unsigned char hwrpb_usb$b_interface_protocol;4 unsigned char hwrpb_usb$b_serialnum_len; } hwrpb$r_usb_bits;& } hwrpb$r_usb_bootdev_overlay;. unsigned char hwrpb$b_usb_serialnum [256];N char hwrpb$t_device_name [32]; /* Network BootDev Name */N unsigned char hwrpb$b_service_name [256]; /* Network Boot Service */N/************************************************************************** */N/* [X86-64] SYSTEM IDENTIFICATION */N/************************************************************************** */N unsigned __int64 hwrpb$iq_system_revision; /* System Rev */N unsigned c har hwrpb$b_sys_phys_serialnum [16]; /* Physical S/N */N unsigned char hwrpb$b_sys_serialnum [16]; /* Virtual S/N */F unsigned __int64 hwrpb$iq_systype; /* System Type */N __union { /* System Variation */) unsigned __int64 hwrpb$iq_sysvar; __struct { __union {/ unsigned int hwrpb$il_sysvar_l; __struct {N unsigned hwrpb_sysvar$v_mpcap : 1; /* Capable of SMP */N unsigned hwrpb_sysvar$v_cnsle : 4; /* Console Type */R unsigned hwrpb_sysvar$v_keyboard : 3; /* Boot Keyboard Type */R unsigned hwrpb_sysvar$v_dumpboot : 1; /* Dump Kernel booted */Q unsigned hwrpb_sysvar$v_graphics : 1; /* Embedded graphics */P unsigned hwrpb_sysvar$v_member_id : 6; /* Member ID field */W signed hwrpb_sysvar$ib_vm_type  : 8; /* Virtual Machine Host Type */V signed hwrpb_sysvar$ib_vm_config : 8; /* Virtual Machine Config */, } hwrpb$r_sysvar_field1;0 } hwrpb$r_sysvar_fields_overlay; __union {/ unsigned int hwrpb$il_sysvar_h; __struct {6 unsigned hwrpb_sysvar$v_fill1 : 1;Y unsigned hwrpb_sysvar$v_rxtx_extent : 1; /* ECO-123 >64 CPU enable */7 unsigned h wrpb_sysvar$v_fill2 : 30;, } hwrpb$r_sysvar_field3;2 } hwrpb$r_sysvar_h_fields_overlay;$ } hwrpb$r_sysvar_fields;! } hwrpb$r_sysvar_overlay;N/* [X86-64] OFFSET & SIZES FOR MAJOR BOOT STRUCTURES */N/************************************************************************** */L __int64 hwrpb$iq_kernel_base_offset; /* External Negative *// unsigned __int64 hwrpb$iq_kernel_base_size;K __int64 hwrpb$ iq_whami_offset; /* External Negative */) unsigned __int64 hwrpb$iq_whami_size;B unsigned __int64 hwrpb$iq_mcd_list_offset; /* Internal */- unsigned __int64 hwrpb$iq_mcd_entry_size;B unsigned __int64 hwrpb$iq_conindev_offset; /* Internal */, unsigned __int64 hwrpb$iq_conindev_size;C unsigned __int64 hwrpb$iq_conoutdev_offset; /* Internal */- unsigned __int64 hwrpb$iq_conoutdev_size;C unsigned __int64 hwrpb$iq_conerrdev_offset; /* Int ernal */- unsigned __int64 hwrpb$iq_conerrdev_size;A unsigned __int64 hwrpb$iq_bootdev_offset; /* Internal */+ unsigned __int64 hwrpb$iq_bootdev_size;@ unsigned __int64 hwrpb$iq_altdev_offset; /* Internal */* unsigned __int64 hwrpb$iq_altdev_size;F unsigned __int64 hwrpb$iq_slot_offset; /* Internal */. unsigned __int64 hwrpb$iq_slot_entry_size;M unsigned __int64 hwrpb$iq_swis_offset; /* Internal */. unsigned __int64 hwrpb$iq_swis_entry_size;L unsigned __int64 hwrpb$iq_crb_offset; /* Internal */' unsigned __int64 hwrpb$iq_crb_size;N unsigned __int64 hwrpb$iq_cmd_buf_offset; /* Internal */+ unsigned __int64 hwrpb$iq_cmd_buf_size;N/* */N/* ECO-123 pertains to support of >64 processors. When enabled, the */N/* RXRDY_OFFSET field points to a CBB (Common Bit Block) structure  */N/* containing bits for additional processors. Each of the traditional */N/* 64 CPU_ID bits then indexes quadword bitmasks within the CBB, each */N/* representing another 64 processors. */N/* */N __union { /* Internal */N unsigned __int64 hwrpb$iq_rxrdy; /* Intercom RXRDY bitmask */N unsigned  __int64 hwrpb$iq_rxrdy_offset; /* CBB bitmask offset */ } hwrpb$r_rxrdy_overlay;N __union { /* Internal */N unsigned __int64 hwrpb$iq_txrdy; /* Intercom TXRDY bitmask */ __struct { __union {. unsigned int hwrpb$il_txrdy_l; __struct {g unsigned hwrpb_txrdy$v_txrdy_summary : 1; /* CBB - At least 1 bitmask is nonzero */<  unsigned hwrpb_txrdy$v_txrdy_fill1 : 31;+ } hwrpb$r_txrdy_field1;/ } hwrpb$r_txrdy_fields_overlay;* unsigned int hwrpb$il_txrdy_h;# } hwrpb$r_txrdy_fields; } hwrpb$r_txrdy_overlay;N/************************************************************************** */N/* [X86-64] OFFSET BOOT STRUCTURES (Internal to HWRPB memory allocation) */N/************************************************************************** */N __unio n { /* BOOT DEVICE */2 unsigned __int64 hwrpb$iq_bootdev_pcinode; __struct { __union {8 unsigned int hwrpb$il_bootdev_pcinode_l; __struct {7 unsigned hwrpb_bootdev$v_funct : 3;8 unsigned hwrpb_bootdev$v_device : 5;5 unsigned hwrpb_bootdev$v_bus : 8;6 unsigned hwrpb_bootdev$v_hose : 8;? un signed hwrpb_bootdev$v_pcinode_fill1 : 8;7 } hwrpb$r_bootdev_pcinode_l_fields;4 } hwrpb$r_bootdev_pcinode_l_overlay; __union {8 unsigned int hwrpb$il_bootdev_pcinode_h;3 unsigned int hwrpb$il_sysdisk_unit;4 } hwrpb$r_bootdev_pcinode_h_overlay;- } hwrpb$r_bootdev_pcinode_fields;* } hwrpb$r_bootdev_pcinode_overlay;N __union { /* ALTERNATE BOOT DEVICE  */1 unsigned __int64 hwrpb$iq_altdev_pcinode; __struct { __union {7 unsigned int hwrpb$il_altdev_pcinode_l; __struct {6 unsigned hwrpb_altdev$v_funct : 3;7 unsigned hwrpb_altdev$v_device : 5;4 unsigned hwrpb_altdev$v_bus : 8;5 unsigned hwrpb_altdev$v_hose : 8;> unsigned hwrpb_altdev$v_altnode_fill1 : 8;6 } hwrpb$r_altdev_pcinode_l_fields;3 } hwrpb$r_altdev_pcinode_l_overlay;3 unsigned int hwrpb$il_altdev_pcinode_h;, } hwrpb$r_altdev_pcinode_fields;) } hwrpb$r_altdev_pcinode_overlay;N/************************************************************************** */N/* [X86-64] CONSOLE & MCA ERROR BUFFERS (NOT YET USED ON X86) */N/************************************************************************** */N unsigned __int64 hwrpb$iq_cd l_pa; /* PA Console Data Log */ __union {1 unsigned __int64 hwrpb$iq_cdl_size_count; __struct {+ unsigned int hwrpb$il_cdl_size;, unsigned int hwrpb$il_cdl_count;, } hwrpb$r_cdl_size_count_fields;) } hwrpb$r_cdl_size_count_overlay;N unsigned __int64 hwrpb$iq_mca_error_record; /* PA MCA err rec buffer */ __union {8 unsigned __int64 hwrpb$iq_mca_record_size_count; __struct {2  unsigned int hwrpb$il_mca_record_size;3 unsigned int hwrpb$il_mca_record_count;, } hwrpb$r_mca_size_count_fields;) } hwrpb$r_mca_size_count_overlay;N unsigned __int64 hwrpb$iq_init_error_record; /* PA INIT err rec buffer */ __union {9 unsigned __int64 hwrpb$iq_init_record_size_count; __struct {3 unsigned int hwrpb$il_init_record_size;4 unsigned int hwrpb$il_init_record_count;- } hwrpb$r_init_size_co unt_fields;* } hwrpb$r_init_size_count_overlay;N unsigned __int64 hwrpb$iq_cmc_error_record; /* PA CMC err rec buffer */ __union {8 unsigned __int64 hwrpb$iq_cmc_record_size_count; __struct {2 unsigned int hwrpb$il_cmc_record_size;3 unsigned int hwrpb$il_cmc_record_count;, } hwrpb$r_cmc_size_count_fields;) } hwrpb$r_cmc_size_count_overlay;N unsigned __int64 hwrpb$iq_cpe_error_record; /* PA CPE err rec buffer */ __union {8 unsigned __int64 hwrpb$iq_cpe_record_size_count; __struct {2 unsigned int hwrpb$il_cpe_record_size;3 unsigned int hwrpb$il_cpe_record_count;, } hwrpb$r_cpe_size_count_fields;) } hwrpb$r_cpe_size_count_overlay;N unsigned __int64 hwrpb$iq_decon_error_record; /* PA Deconfigured buffer */ __union {8 unsigned __int64 hwrpb$iq_decon_record_size_cnt; __struct {4 unsigned int hwrpb$il_ decon_record_size;5 unsigned int hwrpb$il_decon_record_count;. } hwrpb$r_decon_size_count_fields;+ } hwrpb$r_decon_size_count_overlay;N/************************************************************************** */N/* [X86-64] SERIAL CONSOLE SUPPORT */N/************************************************************************** */F unsigned __int64 hwrpb$iq_uart_address; /* Console UART PA */N unsigned __int64 hwrpb$iq_debug_uart_pa; /* Debug UART PA */I/* */N/* This next field is valid only when the console is a PCI device */N/* with a PCI Config Header. The overlaid structure has the advantage */N/* of being cast as a PCI_NODE_NUMBER (see PCIDEF.SDL), since its */N/* bitfields are congruent to those in PCI_NODE_NUMBER. */N/*  */N __union { /* UART PCI CONFIG */6 unsigned __int64 hwrpb$iq_uart_pcicfg_address; __struct {6 unsigned hwrpb_uart_pcicfg$v_function : 3;4 unsigned hwrpb_uart_pcicfg$v_device : 5;1 unsigned hwrpb_uart_pcicfg$v_bus : 8;5 unsigned hwrpb_uart_pcicfg$v_offset : 16;5 unsigned hwrpb_uart_pcicfg$v_segment : 8;7 unsigned hwrpb_uart_pcicfg$v_reserve d : 24;/ } hwrpb$r_uart_pcicfg_address_bits;- } hwrpb$r_uart_pcicfg_address_overla;N/************************************************************************** */N/* [X86-64] VGA SUPPORT (Ref: GPS$ACPI_SUPPORT) */N/************************************************************************** */N/* This structure can be cast as a PCI_NODE_NUMBER (see PCIDEF.SDL) */ __union {5 unsigned __int64 hwrpb$iq_vga_pcicfg_address;  __struct {5 unsigned hwrpb_vga_pcicfg$v_function : 3;3 unsigned hwrpb_vga_pcicfg$v_device : 5;0 unsigned hwrpb_vga_pcicfg$v_bus : 8;4 unsigned hwrpb_vga_pcicfg$v_offset : 16;4 unsigned hwrpb_vga_pcicfg$v_segment : 8;6 unsigned hwrpb_vga_pcicfg$v_reserved : 24;) } hwrpb$r_vga_pcicfg_address;- } hwrpb$r_vga_pcicfg_address_overlay;N unsigned __int64 hwrpb$iq_vga_tra_offset; /* MMIO TRA  */N __union { /* VGA Console Flag */, unsigned __int64 hwrpb$iq_vga_flags; __struct {2 unsigned hwrpb_vga_flag$v_console : 1;5 unsigned hwrpb_vga_flag$v_gc_console : 1;5 unsigned hwrpb_vga_flag$v_gc_bigfont : 1;7 unsigned hwrpb_vga_flag$v_rsvd_flags1 : 29;7 unsigned hwrpb_vga_flag$v_rsvd_flags2 : 32;$ } hwrpb$r_vga_flag_bits;$ } hwrpb$r_vga_flags_overlay;N/* */N/* Virtual address of a data structure containing VGA state and data */N/* used to preserve screen contents when moving to SYSBOOT. */0 unsigned __int64 hwrpb$iq_vga_state_pointer;N/* */N/* Size of the VGA State data structure. The size of the structure is */N/* needed by SYSBOOT for fixup of the VGA_STATE_POINTER when moving */N/* to SYSBOOT. */- unsigned __int64 hwrpb$iq_vga_state_size;N/************************************************************************** */N/* [X86-64] ISO INSTALLATION KIT BOOT SUPPORT */N/* */O/* When booting an ISO DVD Installation Kit Image, the entire ISO DVD Image */N/* is transferred from a web server or loaded into memory by the Boot */N/* Manager and becomes memory-resident DMM1 "System Disk" for the duration */N/* of the installation procedure. In order to mount this memory-resident */N/* disk image, its PA and Size are required. */N/************************************************************************** */N/* */N/* Physical address of the ISO Kit Disk Image or ZERO if not used. */N/* */0 unsigned __int64 hwrpb$iq_system_memdisk_pa;N/* */N/* Size in bytes of the ISO Kit Disk Image or ZERO if not used. */N/* */2 unsigned __int64 hwrpb$iq_system_memdisk_size;N/************************************************************************** */N/* [X86_64] Fibrechannel and SAS boot device support. */N/* */N/* These values are filled in by the X86 Boot Manager when booting from a */N/* Fibre or SAS system disk. For other disk types, the WWID and WWN fields */N/* will contain ZERO. WWID is typically 16 bytes, but could be larger. */N/************************************************************************** */N/*  */N unsigned __int64 hwrpb$iq_bootdev_target_id; /* SCSI Target ID */N unsigned __int64 hwrpb$iq_bootdev_lun; /* Logical Unit Number */N unsigned __int64 hwrpb$iq_bootdev_port_wwn; /* HBA PortID little endian */N unsigned int hwrpb$il_bootdev_wwid_len; /* WWID Length in bytes */N unsigned int hwrpb$il_bootdev_wwid_type; /* WWID Type per WWIDDEF */N/*  */N unsigned char hwrpb$b_bootdev_wwid [64]; /* Disk WWID little endian */N/* */N/* Checksum calculated by the Boot Manager and checked by SYSBOOT */N/* */% unsigned __int64 hwrpb$iq_chksum; } HWRPB; #if !defined(__VAXC)J#define hwrpb$iq_boot_flags hwrpb$r_boot_flags_overlay.hwrpb$iq_boot_flags#define hwrpb$il_boot_flags_l hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$il_boot_flags\_l#define hwrpb_boot_flags$v_sysprompt hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\+_flags_field_l.hwrpb_boot_flags$v_sysprompt#define hwrpb_boot_flags$v_xdelta hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\%ags_field_l.hwrpb_boot_flags$v_xdelta#define hwrpb_boot_flags$v_breakpoint hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boo\-t_flags_field_l.hwrpb_boot_flags$v_breakpoint#define hwrpb_boot_flags$v_dk_sda hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\%ags_field_l.hwrpb_boot_flags$v_dk_sda#define hwrpb_boot_flags$v_progress hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\)flags_field_l.hwrpb_boot_flags$v_progress#define hwrpb_boot_flags$v_sysboot hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\'lags_field_l.hwrpb_boot_flags$v_sysboot#define hwrpb_boot_flags$v_execinit hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\)flags_field_l.hwrpb_boot_flags$v_execinit#define hwrpb_boot_flags$v_sysinit hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\'lags_field_l.hwrpb_boot_flags$v_sysinit#define hwrpb_boot_flags$v_driver hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\%ags_field_l.hwrpb_boot_flags$v_driver#define hwrpb_boot_flags$v_shadow hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\%ags_field_l.hwrpb_boot_flags$v_shadow#define hwrpb_boot_flags$v_netboot hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\'lags_field_l.hwrpb_boot_flags$v_netboot#define hwrpb_boot_flags$v_sysdebug hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\)flags_field_l.hwrpb_boot_flags$v_sysdebug#define hwrpb_boot_flags$v_acpi hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_flag\!s_field_l.hwrpb_boot_flags$v_acpi#define hwrpb_boot_flags$v_hw_config hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\+_flags_field_l.hwrpb_boot_flags$v_hw_config#define hwrpb_boot_flags$v_page_faults hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_bo\/ot_flags_field_l.hwrpb_boot_flags$v_page_faults#define hwrpb_boot_flags$v_halt hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_flag\!s_field_l.hwrpb_boot_flags$v_halt#define hwrpb_boot_flags$v_dk_nosysd hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\+_flags_field_l.hwrpb_boot_flags$v_dk_nosysd#define hwrpb_boot_flags$v_x20000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\%ags_field_l.hwrpb_boot_flags$v_x20000#define hwrpb_boot_flags$v_x40000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\%ags_field_l.hwrpb_boot_flags$v_x40000#define hwrpb_boot_flags$v_x80000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_fl\%ags_field_l.hwrpb_boot_flags$v_x80000#define hwrpb_boot_flags$v_x100000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\'lags_field_l.hwrpb_boot_flags$v_x100000#define hwrpb_boot_flags$v_x200000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\'lags_field_l.hwrpb_boot_flags$v_x200000#define hwrpb_boot_flags$v_x400000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\'lags_field_l.hwrpb_boot_flags$v_x400000#define hwrpb_boot_flags$v_opdisplay hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\+_flags_field_l.hwrpb_boot_flags$v_opdisplay#define hwrpb_boot_flags$v_bootmgr hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\'lags_field_l.hwrpb_boot_flags$v_bootmgr#define hwrpb_boot_flags$v_memcheck hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\)flags_field_l.hwrpb_boot_flags$v_memcheck#define hwrpb_boot_flags$v_devcheck hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\)flags_field_l.hwrpb_boot_flags$v_devcheck#define hwrpb_boot_flags$v_developer hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\+_flags_field_l.hwrpb_boot_flags$v_developer#define hwrpb_boot_flags$v_mdcheck hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\'lags_field_l.hwrpb_boot_flags$v_mdcheck#define hwrpb_boot_flags$v_cpucheck hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_\)flags_field_l.hwrpb_boot_flags$v_cpucheck#define hwrpb_boot_flags$v_x40000000 hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot\+_flags_field_l.hwrpb_boot_flags$v_x40000000#define hwrpb_boot_flags$v_verbose hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_l.hwrpb$r_boot_f\'lags_field_l.hwrpb_boot_flags$v_verbose#define hwrpb$il_boot_flags_h hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_h.hwrpb$il_boot_flags\_h#define hwrpb_boot_flags$v_root hwrpb$r_boot_flags_overlay.hwrpb$r_boot_flags_fields.hwrpb$r_boot_flags_overlay_h.hwrpb$r_boot_flag\!s_field_h.hwrpb_boot_flags$v_rootI#define hwrpb$iq_usb_flags hwrpb$r_usb_bootdev_overlay.hwrpb$iq_usb_flags`#define hwrpb_usb$w_vendor_id hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$w_vendor_idb#define hwrpb_usb$w_product_id hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$w_product_idl#define hwrpb_usb$b_interface_class hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$b_interface_classr#define hwrpb_usb$b_interface_subclass hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$b_interface_subclassr#define hwrpb_usb$b_interface_protocol hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$b_interface_protocolh#define hwrpb_usb$b_serialnum_len hwrpb$r_usb_bootdev_overlay.hwrpb$r_usb_bits.hwrpb_usb$b_serialnum_len>#define hwrpb$iq_sysvar hwrpb$r_sysvar_overlay.hwrpb$iq_sysvarv#define hwrpb$il_sysvar_l hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$il_sysvar_l#define hwrpb_sysvar$v_mpcap hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hwrpb\_sysvar$v_mpcap#define hwrpb_sysvar$v_cnsle hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hwrpb\_sysvar$v_cnsle#define hwrpb_sysvar$v_keyboard hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hw\rpb_sysvar$v_keyboard#define hwrpb_sysvar$v_dumpboot hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hw\rpb_sysvar$v_dumpboot#define hwrpb_sysvar$v_graphics hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hw\rpb_sysvar$v_graphics#define hwrpb_sysvar$v_member_id hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.h\wrpb_sysvar$v_member_id#define hwrpb_sysvar$ib_vm_type hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.hw\rpb_sysvar$ib_vm_type#define hwrpb_sysvar$ib_vm_config hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_fields_overlay.hwrpb$r_sysvar_field1.\hwrpb_sysvar$ib_vm_configx#define hwrpb$il_sysvar_h hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_h_fields_overlay.hwrpb$il_sysvar_h#define hwrpb_sysvar$v_fill1 hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_h_fields_overlay.hwrpb$r_sysvar_field3.hwr\pb_sysvar$v_fill1#define hwrpb_sysvar$v_rxtx_extent hwrpb$r_sysvar_overlay.hwrpb$r_sysvar_fields.hwrpb$r_sysvar_h_fields_overlay.hwrpb$r_sysvar_fiel\d3.hwrpb_sysvar$v_rxtx_extent;#define hwrpb$iq_rxrdy hwrpb$r_rxrdy_overlay.hwrpb$iq_rxrdyI#define hwrpb$iq_rxrdy_offset hwrpb$r_rxrdy_overlay.hwrpb$iq_rxrdy_offset;#define hwrpb$iq_txrdy hwrpb$r_txrdy_overlay.hwrpb$iq_txrdyq#define hwrpb$il_txrdy_l hwrpb$r_txrdy_overlay.hwrpb$r_txrdy_fields.hwrpb$r_txrdy_fields_overlay.hwrpb$il_txrdy_l#define hwrpb_txrdy$v_txrdy_summary hwrpb$r_txrdy_overlay.hwrpb$r_txrdy_fields.hwrpb$r_txrdy_fields_overlay.hwrpb$r_txrdy_field1.hw\rpb_txrdy$v_txrdy_summaryT#define hwrpb$il_txrdy_h hwrpb$r_txrdy_overlay.hwrpb$r_txrdy_fields.hwrpb$il_txrdy_hY#define hwrpb$iq_bootdev_pcinode hwrpb$r_bootdev_pcinode_overlay.hwrpb$iq_bootdev_pcinode#define hwrpb$il_bootdev_pcinode_l hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_l_overlay\.hwrpb$il_bootdev_pcinode_l#define hwrpb_bootdev$v_funct hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_l_overlay.hwrp\2b$r_bootdev_pcinode_l_fields.hwrpb_bootdev$v_funct#define hwrpb_bootdev$v_device hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_l_overlay.hwr\4pb$r_bootdev_pcinode_l_fields.hwrpb_bootdev$v_device#define hwrpb_bootdev$v_bus hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_l_overlay.hwrpb$\.r_bootdev_pcinode_l_fields.hwrpb_bootdev$v_bus#define hwrpb_bootdev$v_hose hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_l_overlay.hwrpb\0$r_bootdev_pcinode_l_fields.hwrpb_bootdev$v_hose#define hwrpb$il_bootdev_pcinode_h hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_h_overlay\.hwrpb$il_bootdev_pcinode_h#define hwrpb$il_sysdisk_unit hwrpb$r_bootdev_pcinode_overlay.hwrpb$r_bootdev_pcinode_fields.hwrpb$r_bootdev_pcinode_h_overlay.hwrp\b$il_sysdisk_unitV#define hwrpb$iq_altdev_pcinode hwrpb$r_altdev_pcinode_overlay.hwrpb$iq_altdev_pcinode#define hwrpb$il_altdev_pcinode_l hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$r_altdev_pcinode_l_overlay.hwr\pb$il_altdev_pcinode_l#define hwrpb_altdev$v_funct hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$r_altdev_pcinode_l_overlay.hwrpb$r_\,altdev_pcinode_l_fields.hwrpb_altdev$v_funct#define hwrpb_altdev$v_device hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$r_altdev_pcinode_l_overlay.hwrpb$r\._altdev_pcinode_l_fields.hwrpb_altdev$v_device#define hwrpb_altdev$v_bus hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$r_altdev_pcinode_l_overlay.hwrpb$r_al\(tdev_pcinode_l_fields.hwrpb_altdev$v_bus#define hwrpb_altdev$v_hose hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$r_altdev_pcinode_l_overlay.hwrpb$r_a\*ltdev_pcinode_l_fields.hwrpb_altdev$v_hosex#define hwrpb$il_altdev_pcinode_h hwrpb$r_altdev_pcinode_overlay.hwrpb$r_altdev_pcinode_fields.hwrpb$il_altdev_pcinode_hV#define hwrpb$iq_cdl_size_count hwrpb$r_cdl_size_count_overlay.hwrpb$iq_cdl_size_counth#define hwrpb$il_cdl_size hwrpb$r_cdl_size_count_overlay.hwrpb$r_cdl_size_count_fields.hwrpb$il_cdl_sizej#define hwrpb$il_cdl_count hwrpb$r_cdl_size_count_overlay.hwrpb$r_cdl_size_count_fields.hwrpb$il_cdl_countd#define hwrpb$iq_mca_record_size_count hwrpb$r_mca_size_count_overlay.hwrpb$iq_mca_record_size_countv#define hwrpb$il_mca_record_size hwrpb$r_mca_size_count_overlay.hwrpb$r_mca_size_count_fields.hwrpb$il_mca_record_sizex#define hwrpb$il_mca_record_count hwrpb$r_mca_size_count_overlay.hwrpb$r_mca_size_count_fields.hwrpb$il_mca_record_countg#define hwrpb$iq_init_record_size_count hwrpb$r_init_size_count_overlay.hwrpb$iq_init_record_size_countz#define hwrpb$il_init_record_size hwrpb$r_init_size_count_overlay.hwrpb$r_init_size_count_fields.hwrpb$il_init_record_size|#define hwrpb$il_init_record_count hwrpb$r_init_size_count_overlay.hwrpb$r_init_size_count_fields.hwrpb$il_init_record_countd#define hwrpb$iq_cmc_record_size_count hwrpb$r_cmc_size_count_overlay.hwrpb$iq_cmc_record_size_countv#define hwrpb$il_cmc_record_size hwrpb$r_cmc_size_count_overlay.hwrpb$r_cmc_size_count_fields.hwrpb$il_cmc_record_sizex#define hwrpb$il_cmc_record_count hwrpb$r_cmc_size_count_overlay.hwrpb$r_cmc_size_count_fields.hwrpb$il_cmc_record_countd#define hwrpb$iq_cpe_record_size_count hwrpb$r_cpe_size_count_overlay.hwrpb$iq_cpe_record_size_countv#define hwrpb$il_cpe_record_size hwrpb$r_cpe_size_count_overlay.hwrpb$r_cpe_size_count_fields.hwrpb$il_cpe_record_sizex#define hwrpb$il_cpe_record_count hwrpb$r_cpe_size_count_overlay.hwrpb$r_cpe_size_count_fields.hwrpb$il_cpe_record_countf#define hwrpb$iq_decon_record_size_cnt hwrpb$r_decon_size_count_overlay.hwrpb$iq_decon_record_size_cnt~#define hwrpb$il_decon_record_size hwrpb$r_decon_size_count_overlay.hwrpb$r_decon_size_count_fields.hwrpb$il_decon_record_size#define hwrpb$il_decon_record_count hwrpb$r_decon_size_count_overlay.hwrpb$r_decon_size_count_fields.hwrpb$il_decon_record_countd#define hwrpb$iq_uart_pcicfg_address hwrpb$r_uart_pcicfg_address_overla.hwrpb$iq_uart_pcicfg_address#define hwrpb_uart_pcicfg$v_function hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_functi\on#define hwrpb_uart_pcicfg$v_device hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_device{#define hwrpb_uart_pcicfg$v_bus hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_bus#define hwrpb_uart_pcicfg$v_offset hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_offset#define hwrpb_uart_pcicfg$v_segment hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_segment#define hwrpb_uart_pcicfg$v_reserved hwrpb$r_uart_pcicfg_address_overla.hwrpb$r_uart_pcicfg_address_bits.hwrpb_uart_pcicfg$v_reserv\edb#define hwrpb$iq_vga_pcicfg_address hwrpb$r_vga_pcicfg_address_overlay.hwrpb$iq_vga_pcicfg_address}#define hwrpb_vga_pcicfg$v_function hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_functiony#define hwrpb_vga_pcicfg$v_device hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_devices#define hwrpb_vga_pcicfg$v_bus hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_busy#define hwrpb_vga_pcicfg$v_offset hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_offset{#define hwrpb_vga_pcicfg$v_segment hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_segment}#define hwrpb_vga_pcicfg$v_reserved hwrpb$r_vga_pcicfg_address_overlay.hwrpb$r_vga_pcicfg_address.hwrpb_vga_pcicfg$v_reservedG#define hwrpb$iq_vga_flags hwrpb$r_vga_flags_overlay.hwrpb$iq_vga_flagsi#define hwrpb_vga_flag$v_console hwrpb$r_vga_flags_overlay.hwrpb$r_vga_flag_bits.hwrpb_vga_flag$v_consoleo#define hwrpb_vga_flag$v_gc_console hwrpb$r_vga_flags_overlay.hwrpb$r_vga_flag_bits.hwrpb_vga_flag$v_gc_consoleo#define hwrpb_vga_flag$v_gc_bigfont hwrpb$r_vga_flags_overlay.hwrpb$r_vga_flag_bits.hwrpb_vga_flag$v_gc_bigfontq#define hwrpb_vga_flag$v_rsvd_flags1 hwrpb$r_vga_flags_overlay.hwrpb$r_vga_flag_bits.hwrpb_vga_flag$v_rsvd_flags1q#define hwrpb_vga_flag$v_rsvd_flags2 hwrpb$r_vga_flags_overlay.hwrpb$r_vga_flag_bits.hwrpb_vga_flag$v_rsvd_flags2"#endif /* #if !defined(__VAXC) */ N/************ END OF X86_64 HWRPB STRUCTURE ***************************** */N#define HWRPB$C_LENGTH 1376 /* Length of HWRPB */N#define HWRPB$K_LENGTH 1376 /* Length of HWRPB */N#define HWRPB$S_HWRPBDEF 1376 /* Old size name - synonym */N/************************************************************************ */N/* HWPCB structure in Per-CPU slot definitions - zero relative */N/************************************************************************ */#define HWPCB$M_ASTEN 0xF#define HWPCB$M_ASTSR 0xF0#define HWPCB$M_ASTEN_KEN 0x1#define HWPCB$M_ASTEN_EEN 0x2#define HWPCB$M_ASTEN_SEN 0x4#define HWPCB$M_ASTEN_UEN 0x8#define HWPCB$M_ASTSR_KPD 0x10#define HWPCB$M_ASTSR_EPD 0x20#define HWPCB$M_ASTSR_SPD 0x40#define HWPCB$M_ASTSR_UPD 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#p ragma __nomember_alignment#endiftypedef struct _hwpcb {N/*************** */N/* Base of HWPCB */N/*************** */#pragma __nomember_alignment __union {- unsigned __int64 hwpcb$iq_hwpcb_base;N/********************** */N/* Kernel Stack Pointer  */N/********************** */ __union {* unsigned __int64 hwpcb$iq_ksp; __struct {, unsigned int hwpcb$il_ksp_l;, unsigned int hwpcb$il_ksp_h;% } hwpcb$r_ksp_fields;" } hwpcb$r_ksp_overlay; } hwpcb$r_hwpcb_overlay;N/************************* */N/* E xecutive Stack Pointer */N/************************* */ __union {& unsigned __int64 hwpcb$iq_esp; __struct {( unsigned int hwpcb$il_esp_l;( unsigned int hwpcb$il_esp_h;! } hwpcb$r_esp_fields; } hwpcb$r_esp_overlay;N/************************** */N/* Supervisor Stack Pointer  */N/************************** */ __union {& unsigned __int64 hwpcb$iq_ssp; __struct {( unsigned int hwpcb$il_ssp_l;( unsigned int hwpcb$il_ssp_h;! } hwpcb$r_ssp_fields; } hwpcb$r_ssp_overlay;N/******************** */N/* User Stack Pointer */N/******************** */ __union {& unsigned __int64 hwpcb$iq_usp; __struct {( unsigned int hwpcb$il_usp_l;( unsigned int hwpcb$il_usp_h;! } hwpcb$r_usp_fields; } hwpcb$r_usp_overlay;N/***************** */N/* Page Table Base */N/*****************  */N unsigned __int64 hwpcb$iq_ptbr [4]; /* One per mode */N/***** */N/* ASN */N/***** */" unsigned __int64 hwpcb$iq_asn;N/**************************************************** */N/* AST Enable and Summ ary Registers (ASTSR and ASTEN) */N/**************************************************** */ __union {. unsigned __int64 hwpcb$iq_astsr_asten; __struct {( unsigned int hwpcb$il_ast_l;( unsigned int hwpcb$il_ast_h;! } hwpcb$r_ast_fields; __struct {N unsigned hwpcb$v_asten : 4; /* AST Enable Register */N unsigned hwpcb$v_astsr : 4; /* AST Pending Summa ry Register */ } hwpcb$r_ast_bits0; __struct {N unsigned hwpcb$v_asten_ken : 1; /* Kernel AST Enable = 1 */N unsigned hwpcb$v_asten_een : 1; /* Executive AST Enable = 1 */N unsigned hwpcb$v_asten_sen : 1; /* Supervisor AST Enable = 1 */N unsigned hwpcb$v_asten_uen : 1; /* User AST Enable = 1 */N unsigned hwpcb$v_astsr_kpd : 1; /* Kernel AST Pending = 1 */N unsigned hwpcb$v_astsr_epd : 1; /* Executive AST Pending = 1 */N unsigned hwpcb$v_astsr_spd : 1; /* Supervisor AST Pending = 1 */N unsigned hwpcb$v_astsr_upd : 1; /* User AST Pending = 1 */ } hwpcb$r_ast_bits1; } hwpcb$r_ast_overlay;N/**************************** */N/* Process Attributes Section */N/****************************  */+ unsigned __int64 hwpcb$iq_perf_control;N/*************** */N/* Cycle Counter */N/*************** */ __union {% unsigned __int64 hwpcb$iq_cc; __struct {' unsigned int hwpcb$il_cc_l;' unsigned int hwpcb$il_cc_h; } hwpcb$r_cc_fields; } hwpc b$r_cc_overlay;N/********************** */N/* Process Unique Value - IA64 Thread Pointer (R13) */N/********************** */ __union {N unsigned __int64 hwpcb$iq_unq; /* Process Unique Value */ __struct {( unsigned int hwpcb$il_unq_l;( unsigned int hwpcb$il_unq_h;! } hwpcb$r_unq_fields; } hwpcb$r_unq_overlay;N/*********************** */N/* Alpha register blocks */N/*********************** */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *hwpcb$pq_alphareg [4];#else( unsigned __int64 hwpcb$pq _alphareg [4];#endifN/*************** */N/* Previous mode */N/*************** */N unsigned char hwpcb$b_pmod; /* Previous mode */( unsigned char hwpcb$b_was_scheduled;N char hwpcb$b_reserved_1 [6]; /* Reserved for future use */N/*****************  */N/* Interrupt depth */N/***************** */N unsigned int hwpcb$il_interrupt_depth; /* Interrupt depth */N/*************** */N/* Current frame */N/***************  */N int hwpcb$l_cur_frame_mode; /* Mode of currently active frame */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *hwpcb$pq_cur_frame; /* Currently active frame */#else% unsigned __int64 hwpcb$pq_cur_frame;#endifN/********************* */N/* Kernel Stack Limits */N/********************* */( unsigned __int64 hwpcb$q_kstack_top;+ unsigned __int64 hwpcb$q_kstack_bottom;N/****************************** */N/* Reserved for PALcode scratch */N/****************************** */N __int64 hwpcb$iq_pal_rsvd [5];  /* Reserved for PAL scratch */ } HWPCB; #if !defined(__VAXC)E#define hwpcb$iq_hwpcb_base hwpcb$r_hwpcb_overlay.hwpcb$iq_hwpcb_baseK#define hwpcb$iq_ksp hwpcb$r_hwpcb_overlay.hwpcb$r_ksp_overlay.hwpcb$iq_kspb#define hwpcb$il_ksp_l hwpcb$r_hwpcb_overlay.hwpcb$r_ksp_overlay.hwpcb$r_ksp_fields.hwpcb$il_ksp_lb#define hwpcb$il_ksp_h hwpcb$r_hwpcb_overlay.hwpcb$r_ksp_overlay.hwpcb$r_ksp_fields.hwpcb$il_ksp_h5#define hwpcb$iq_esp hwpcb$r_esp_overlay.hwpcb$iq_espL#define hwpcb$il_esp_l hwpcb$r_esp_overlay.hwpcb$r_esp_fields.hwpcb$il_esp_lL#define hwpcb$il_esp_h hwpcb$r_esp_overlay.hwpcb$r_esp_fields.hwpcb$il_esp_h5#define hwpcb$iq_ssp hwpcb$r_ssp_overlay.hwpcb$iq_sspL#define hwpcb$il_ssp_l hwpcb$r_ssp_overlay.hwpcb$r_ssp_fields.hwpcb$il_ssp_lL#define hwpcb$il_ssp_h hwpcb$r_ssp_overlay.hwpcb$r_ssp_fields.hwpcb$il_ssp_h5#define hwpcb$iq_usp hwpcb$r_usp_overlay.hwpcb$iq_uspL#define hwpcb$il_usp_l hwpcb$r_usp_overlay.hwpcb$r_usp_fields.hwpcb$il_usp_lL#define hwpcb$il_usp_h hwpcb$r_usp_overlay.hwpcb$r_usp_fields.hwpcb$il_usp_hE#define hwpcb$iq_astsr_asten hwpcb$r_ast_overlay.hwpcb$iq_astsr_astenL#define hwpcb$il_ast_l hwpcb$r_ast_overlay.hwpcb$r_ast_fields.hwpcb$il_ast_lL#define hwpcb$il_ast_h hwpcb$r_ast_overlay.hwpcb$r_ast_fields.hwpcb$il_ast_hI#define hwpcb$v_asten hwpcb$r_ast_overlay.hwpcb$r_ast_bits0.hwpcb$v_astenI#define hwpcb$v_astsr hwpcb$r_ast_overlay.hwpcb$r_ast_bits0.hwpcb$v_astsrQ#define hwpcb$v_asten_ken hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_kenQ#define hwpcb$v_asten_een hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_eenQ#define hwpcb$v_asten_sen hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_senQ#define hwpcb$v_asten_uen hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_asten_uenQ#define hwpcb$v_astsr_kpd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_kpdQ#define hwpcb$v_astsr_epd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_epdQ#define hwpcb$v_astsr_spd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_spdQ#define hwpcb$v_astsr_upd hwpcb$r_ast_overlay.hwpcb$r_ast_bits1.hwpcb$v_astsr_upd2#define hwpcb$iq_cc hwpcb$r_cc_overlay.hwpcb$iq_ccH#define hwpcb$il_cc_l hwpcb$r_cc_overlay.hwpcb$r_cc_fields.hwpcb$il_cc_lH#define hwpcb$il_cc_h hwpcb$r_cc_overlay.hwpcb$r_cc_fields.hwpcb$il_cc_h5#define hwpcb$iq_unq hwpcb$r_unq_overlay.hwpcb$iq_unqL#define hwpcb$il_unq_l hwpcb$r_unq_overlay.hwpcb$r_unq_fields.hwpcb$il_unq_lL#define hwpcb$il_unq_h hwpcb$r_unq_overlay.hwpcb$r_unq_fields.hwpcb$il_unq_h"#endif /* #if !defined(__VAXC) */ N/* */N#define HWPCB$C_LENGTH 216 /* Full length of HWPCB$ */N#define HWPCB$K_LENGTH 216 /* Full length of HWPCB$ */N#define HWPCB$S_HWPCBDEF 216 /* Old size name - synonym */N/************************************************************************** */N/* Per-CPU slot definitions  */N/************************************************************************** */#define SLOT$M_BIP 0x1#define SLOT$M_RC 0x2#define SLOT$M_PA 0x4#define SLOT$M_PP 0x8#define SLOT$M_OH 0x10#define SLOT$M_CV 0x20#define SLOT$M_PV 0x40#define SLOT$M_PMV 0x80#define SLOT$M_PL 0x100#define SLOT$M_RIP 0x200#define SLOT$M_HLTREQ 0xFF0000N#define HWRPB_HALT$K_NO_ACTION 0 /* Just Halt */N#define HWRPB_HALT$K_SAVE_RESTORE_TERM 1 /* Save or restore term */N#define HWRPB_HALT$K_COLD_REBOOT 2 /* Cold bootstrap request */N#define HWRPB_HALT$K_WARM_REBOOT 3 /* Warm bootstrap request */N#define HWRPB_HALT$K_REMAIN_HALTED 4 /* Don't restart */N#define HWRPB_HALT$K_POWEROFF 5 /* Power-off system */N/* reserved */N#define HWRPB_HALT$K_MIGRATE 7 /* Galaxy CPU migration */ N/* reserved */N#define HWRPB_HALT$K_BIB_STATE 9 /* Invoke ACPI state for BIB state */#define SLOT$M_PARTID 0xFFFFN#define HWRPB_PAL_REV$K_IPF 32 /* Standard PAL code */N/**************** */!#define HWRPB_CPU_TYPE$K_MERCED 7$#define HWRPB_CPU_TYPE$K_MCKINLEY 31N/********************* */ #define SLOT$M_VAX_FP 0x1#define SLOT$M_IEEE_FP 0x2#define SLOT$M_PE 0x4N#define HWRPB$K_RESTART 0 /* Btstrap,procr strt, or pwrfl. */N#define HWRPB$K_CRASH_CMD 1 /* Crash via cosole request */N#define HWRPB$K_KSP_NOT_VALID 2 /* Kernel stack not valid halt */N#define HWRPB$K_INVALID_SCBB 3 /* Invalid SCB Base register */N#define HWRPB$K_INVALID_PTBR 4 /* Invalid Page Table Base Reg. */N#define HWRPB$K_CALL_PAL_H ALT 5 /* Processor executed in ker. mode */N#define HWRPB$K_DOUBLE_ERROR 6 /* Double error abort */N#define HWRPB$K_MCHECK_IN_PAL 7 /* Mcheck in PAL environment */"#define HWRPB$K_LAST_HALT_REASON 7N/*********************** */#define SLOT$M_MCES_MCA 0x1#define SLOT$M_MCES_CPE 0x2#define SLOT$M_MCES_CMC 0x4#define SLOT$M_MCES_CPE_DIS 0x8 #define SLOT$M_MCES_CMC_DIS 0x10#define SLOT$M_MCE S_INIT 0x20 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cpu_slot {N/******************** */N/* Restart/Boot HWPCB */N/******************** */#pragma __nomember_alignmentO unsigned __int64 slot$iq_hwpcb [32]; /* HWPCB rounded to multiple of 128 */N/************************************ */N/* Physical offset from slot to HWRPB */N/************************************ */N unsigned __int64 slot$iq_hwrpb_offset; /* Offset to HWRPB Negative */N/******************** */N/* Per-CPU state bits  */N/******************** */ __union {' unsigned __int64 slot$iq_state; __struct { __union {+ unsigned int slot$il_state; __struct {N unsigned slot$v_bip : 1; /* Bootstrap in progress */N unsigned slot$v_rc : 1; /* Restart capable */N unsigned slot$v_pa : 1; /* Processor available */N unsigned slot$v_pp : 1; /* Processor present */N unsigned slot$v_oh : 1; /* Operator halted */N unsigned slot$v_cv : 1; /* Context valid */N unsigned slot$v_pv : 1; /* PAL code valid */N unsigned slot$v_pmv : 1; /* PAL code memory valid */N unsigned slot$v_pl : 1; /* PAL code loaded */N unsigned slot$v_rip : 1; /* Rendezvous in progress */r unsigned slot$v_state_fill1 : 6 /** WARNING: bitfield array has been reduced to a string **/ ;/ unsigned slot$v_hltreq : 8;l unsigned slot$v_fill2 : 8 /** WARNING: bitfield array has been reduced to a string **/ ;* } slot$r_state_field1;. } slot$r_state_fields_overlay; __union {-  unsigned int slot$il_state_h; __struct {0 unsigned slot$v_partid : 16;m unsigned slot$v_fill3 : 16 /** WARNING: bitfield array has been reduced to a string **/ ;* } slot$r_state_field2;/ } slot$r_state_fields2_overlay;" } slot$r_state_fields; } slot$r_state_overlay;N/************************************** */N/* Physical Address of SAL memor y space */N/************************************** */ __union {, unsigned __int64 slot$iq_sal_mem_pa; __struct {. unsigned int slot$il_sal_mem_pa_l;. unsigned int slot$il_sal_mem_pa_h;' } slot$r_sal_mem_pa_fields;$ } slot$r_sal_mem_pa_overlay;N/************************************** */N/* Physical Address of PAL memory spac e */N/************************************** */ __union {, unsigned __int64 slot$iq_pal_mem_pa; __struct {. unsigned int slot$il_pal_mem_pa_l;. unsigned int slot$il_pal_mem_pa_h;' } slot$r_pal_mem_pa_fields;$ } slot$r_pal_mem_pa_overlay;N/**************************************** */N/* PALcode revision required by processor  */N/**************************************** */ __union {) unsigned __int64 slot$iq_pal_rev; __struct { __union {/ unsigned int slot$il_pal_rev_l; __struct {S unsigned char slot$b_pal_min_rev; /* PAL code minor revision */S unsigned char slot$b_pal_maj_rev; /* PAL code major revision */N unsigned cha r slot$b_pal_var; /* PAL code variation */1 char slot$b_palrev_fill1 [1];. } slot$r_pal_rev_l_fields;1 } slot$r_pal_rev_fields1_overlay; __union {/ unsigned int slot$il_pal_rev_h; __struct {V unsigned short int slot$iw_pal_compt; /* PAL code compatibility */X unsigned short int slot$iw_max_share; /* Max number CPUs to share */. } sl ot$r_pal_rev_h_fields;2 } slot$r_pal_rev_fields_h_overlay;$ } slot$r_pal_rev_fields;! } slot$r_pal_rev_overlay;N/* Processor Type */N/**************** */ __union {* unsigned __int64 slot$iq_cpu_type; __struct {, unsigned int slot$il_cpu_type_l;, unsigned int slot$il_cpu_type_h;% } slot$r_c pu_type_fields;" } slot$r_cpu_type_overlay;N/* Processor Variation */N/********************* */ __union {) unsigned __int64 slot$iq_cpu_var; __struct { __union {/ unsigned int slot$il_cpu_var_l; __struct {N unsigned slot$v_vax_fp : 1; /* VAX floating point */N unsign ed slot$v_ieee_fp : 1; /* IEEE floating point */N unsigned slot$v_pe : 1; /* Processor Eligibility */t unsigned slot$v_cpuvar_fill1 : 29 /** WARNING: bitfield array has been reduced to a string **/ ;, } slot$r_cpu_var_field1;0 } slot$r_cpu_var_fields_overlay;+ unsigned int slot$il_cpu_var_h;$ } slot$r_cpu_var_fields;! } slot$r_cpu_var_overlay;N/*****************************  */N/* Processor Stepping Revision */N/***************************** */ __union {) unsigned __int64 slot$iq_cpu_rev; __struct {+ unsigned int slot$il_cpu_rev_l;+ unsigned int slot$il_cpu_rev_h;$ } slot$r_cpu_rev_fields;! } slot$r_cpu_rev_overlay;N/*******************  */N/* CPU serial number */N/******************* */, unsigned char slot$b_cpu_serialnum [16];N/********************************* */N/* Physical Address of logout area */N/********************************* */ __union {+ unsigned __i nt64 slot$iq_logout_pa; __struct {- unsigned int slot$il_logout_pa_l;- unsigned int slot$il_logout_pa_h;& } slot$r_logout_pa_fields;# } slot$r_logout_pa_overlay;N/********************* */N/* Size of logout area */N/********************* */ __union {, unsigned __int64 slo t$iq_logout_len; __struct {. unsigned int slot$il_logout_len_l;. unsigned int slot$il_logout_len_h;' } slot$r_logout_len_fields;$ } slot$r_logout_len_overlay;N/*********** */N/* Halt PCBB */N/*********** */ __union {+ unsigned __int64 slot$iq_h alt_pcbb; __struct {- unsigned int slot$il_halt_pcbb_l;- unsigned int slot$il_halt_pcbb_h;& } slot$r_halt_pcbb_fields;# } slot$r_halt_pcbb_overlay;N/********* */N/* Halt PC */N/********* */ __union {) unsigned __int64 slot$iq_halt_pc;  __struct {+ unsigned int slot$il_halt_pc_l;+ unsigned int slot$il_halt_pc_h;$ } slot$r_halt_pc_fields;! } slot$r_halt_pc_overlay;N/********* */N/* Halt PS */N/********* */ __union {) unsigned __int64 slot$iq_halt_ps; __struct  {+ unsigned int slot$il_halt_ps_l;+ unsigned int slot$il_halt_ps_h;$ } slot$r_halt_ps_fields;! } slot$r_halt_ps_overlay;N/******************** */N/* Halt Argument List */N/******************** */ __union {* unsigned __int64 slot$iq_halt_arg; __struct {, unsigned int slot$il_halt_arg_l;, unsigned int slot$il_halt_arg_h;% } slot$r_halt_arg_fields;" } slot$r_halt_arg_overlay;N/********************* */N/* Halt Return Address */N/********************* */ __union {* unsigned __int64 slot$iq_halt_ret; __struct {, unsigned int slo t$il_halt_ret_l;, unsigned int slot$il_halt_ret_h;% } slot$r_halt_ret_fields;" } slot$r_halt_ret_overlay;N/********************** */N/* Halt Procedure Value */N/********************** */ __union {) unsigned __int64 slot$iq_halt_pv; __struct {+ unsigned int slot$il_halt_pv_l; + unsigned int slot$il_halt_pv_h;$ } slot$r_halt_pv_fields;! } slot$r_halt_pv_overlay;N/*********** */N/* Halt Code */N/*********** */ __union {* unsigned __int64 slot$iq_haltcode; __struct {, unsigned int slot$il_haltcode_l;, unsi gned int slot$il_haltcode_h;% } slot$r_haltcode_fields;" } slot$r_haltcode_overlay;N/* Reserved for Software */N/*********************** */ __union {N unsigned __int64 slot$iq_soft_flags; /* Reserved to software */ __struct {. unsigned int slot$il_soft_flags_l;. unsigned int slot$il_soft_flags_h;' } slot$r_soft_ flags_fields;$ } slot$r_soft_flags_overlay;N/************************************ */N/* Interprocessor Console Buffer Area */N/************************************ */ __union {N unsigned char slot$b_incon_buf_area [168]; /* SMP Console Buf Area */ __struct {' unsigned int slot$il_rxlen;' unsigned int slot$il_txlen;/  unsigned char slot$b_rxbuffer [80];/ unsigned char slot$b_txbuffer [80];& } slot$r_incon_buf_fields;# } slot$r_incon_buf_overlay;N/*********************************************** */N/* The next 16 quadwords are reserved for the */N/* "PALcode Revisions Available Block". */N/* The format of the first quadword is platform specific. */N/* The format of each subsequent quadword follows the */N/* PALcode revision field (SLOT[168]) */N/*********************************************** */W unsigned __int64 slot$q_pal_rev_avail [16]; /* PALcode Revisions Available Block */N/********************************** */N/* Processor Software Compatibility */N/********************************* * */ __union {- unsigned __int64 slot$iq_cpu_sw_comp; __struct {/ unsigned int slot$il_cpu_sw_comp_l;/ unsigned int slot$il_cpu_sw_comp_h;( } slot$r_cpu_sw_comp_fields;% } slot$r_cpu_sw_comp_overlay;N/*************************** */N/* Console Frame Data Buffer */N/***************************  */ __union {1 unsigned __int64 slot$iq_console_data_pa; __struct {3 unsigned int slot$il_console_data_pa_l;3 unsigned int slot$il_console_data_pa_h;, } slot$r_console_data_pa_fields;) } slot$r_console_data_pa_overlay;N/******************************** */N/* Console Frame Data Buffer Size */N/********* *********************** */ __union {3 unsigned __int64 slot$iq_console_data_size; __struct {5 unsigned int slot$il_console_data_size_l;5 unsigned int slot$il_console_data_size_h;. } slot$r_console_data_size_fields;+ } slot$r_console_data_size_overlay;N/******************* */N/* Cache Information  */N/******************* */ __union {+ unsigned __int64 slot$iq_cpu_cache; __struct { __union {1 unsigned int slot$il_cpu_cache_l;N/* CPU_CACHE_FIELD1 structure fill; */]/* CPU_CACHE_ASSOC_DEGREE byte unsigned; /* Degree of set associativity */N/* CPU_CACHE_FIELD2 structure fill;  */_/* CPU_CACHE_WRITE_BACK bitfield mask; /* Write-back or Write-through */N/* CPU_CACHE_FILL1 bitfield dimension 7 fill; */N/* end CPU_CACHE_FIELD2; */f/* CPU_CACHE_BLOCK_SIZE integer_word unsigned; /* Size of individual cache block */N/* end CPU_CACHE_FIELD1; */2 } slot$r_cpu_cache_fields_overlay;N  unsigned int slot$il_cpu_cache_h; /* Total size of cache in kb */& } slot$r_cpu_cache_fields;# } slot$r_cpu_cache_overlay;N/************************* */N/* Cycle Counter Frequency */N/************************* */ __union {2 unsigned __int64 slot$iq_cycle_count_freq; __struct {4 unsign ed int slot$il_cycle_count_freq_l;4 unsigned int slot$il_cycle_count_freq_h;- } slot$r_cycle_count_freq_fields;* } slot$r_cycle_count_freq_overlay;N/*************************** */N/* Clock Interrupt Frequency */N/*************************** */ __union {0 unsigned __int64 slot$iq_clock_int_freq; __struct {2 unsigned int slot$il_clock_int_freq_l;2 unsigned int slot$il_clock_int_freq_h;+ } slot$r_clock_int_freq_fields;( } slot$r_clock_int_freq_overlay;N/*************** */N/* ITC Frequency */N/*************** */& unsigned __int64 slot$iq_itc_freq;N/*****************  */N/* ITC Drift value */N/***************** */Q unsigned __int64 slot$iq_itc_drift; /* Hardware drift in ppm clock ticks */N/************************ */N/* LID - IPF CPU Local ID */N/************************   */S unsigned __int64 slot$iq_lid; /* CPU Local ID used for intr generation */N/****************************** */N/* Translation buffer registers */N/****************************** */^ unsigned __int64 slot$q_tbreg_init [8]; /* Values to stuff into TB registers (0=unused) */N/************************************* ! */N/* Kernel Register Values for this CPU */N/************************************* */a unsigned __int64 slot$q_kreg_init [8]; /* Values to stuff into kernel registers (0=unused) */N/******************************** */N/* Interrupt Vector Table Address */N/******************************** " */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */[ void *slot$pq_ivt_init; /* VA of the interrupt vector table for this CPU */#else# unsigned __int64 slot$pq_ivt_init;#endifN/************************************** */N/* Virtual Hash Page Table for this CPU */N/***#*********************************** */b unsigned __int64 slot$iq_swis_offset; /* VA of VHPT for this CPU (0 means VHPT is disabled) */N/*********************** */N/* Interrupt Stack Bases */N/*********************** */N unsigned __int64 slot$q_isp_base; /* The interrupt stack pointer base */` unsign$ed __int64 slot$q_ibsp_base; /* The interrupt stack RSE backing store pointer base */N/********************************************** */N/* Stack pointers for hardware interrupt events */N/********************************************** */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N % void *slot$pq_mca_ksp; /* MCA Kernel Stack */#else" unsigned __int64 slot$pq_mca_ksp;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *slot$pq_init_ksp; /* Init Kernel Stack */#else# unsigned __int64 slot$pq_init_ksp;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size prag &mas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *slot$pq_cmc_ksp; /* CMC Kernel Stack */#else" unsigned __int64 slot$pq_cmc_ksp;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *slot$pq_cpe_ksp; /* CPE Kernel Stack */#else" ' unsigned __int64 slot$pq_cpe_ksp;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *slot$pq_mca_bsp; /* MCA Backing Store Pointer */#else" unsigned __int64 slot$pq_mca_bsp;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default t (o 64-bit pointers */N void *slot$pq_init_bsp; /* Init Backing Store Pointer */#else# unsigned __int64 slot$pq_init_bsp;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *slot$pq_cmc_bsp; /* CMC Backing Store Pointer */#else" unsigned __int64 slot$pq_cmc_bsp;#endifR#ifdef __INITIAL_POINTER_SIZE /* Define )d whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *slot$pq_cpe_bsp; /* CPE Backing Store Pointer */#else" unsigned __int64 slot$pq_cpe_bsp;#endifN/************************************************** */N/* Emulated Machine Check Error Summary cell (MCES) */N/************************************************** */ * __union {% unsigned __int64 slot$q_mces; __struct {) unsigned slot$v_mces_mca : 1;) unsigned slot$v_mces_cpe : 1;) unsigned slot$v_mces_cmc : 1;- unsigned slot$v_mces_cpe_dis : 1;- unsigned slot$v_mces_cmc_dis : 1;* unsigned slot$v_mces_init : 1;( unsigned slot$v_fill_0_ : 2;! } slot$r_mces_fields; } slot$r_mces_overlay;N/*************************** + */N/* ACPI Processor Identifier */N/*************************** */ __union {) unsigned __int64 slot$iq_acpi_id; __struct {+ unsigned int slot$il_acpi_id_l;+ unsigned int slot$il_acpi_id_h;$ } slot$r_acpi_id_fields;! } slot$r_acpi_id_overlay;N/********************************** , */N/* ACPI Processor Unique Identifier */N/********************************** */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *slot$pq_acpi_uid;#else# unsigned __int64 slot$pq_acpi_uid;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenev -er ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif! void *slot$ps_acpi_uid_l;" } slot$r_acpi_uid_overlay;N/********************************************** */N/* Handle to Processor Object in ACPI Namespace */N/********************************************** */) unsigned __int64 slot$iq_acpi_handle;N/************* .************* */N/* System Firmware Revision */N/************************** */ __union {, unsigned __int64 slot$iq_sys_fw_rev; __struct {6 unsigned short int slot$iw_sys_fw_min_rev;6 unsigned short int slot$iw_sys_fw_maj_rev;( char slot$b_fwrev_fill1 [4];# } slot$r_sys_fw_fields;$ / } slot$r_sys_fw_rev_overlay;N/********************************************************* */N/* Baseboard Management Controller (BMC) Firmware Revision */N/********************************************************* */ __union {, unsigned __int64 slot$iq_bmc_fw_rev; __struct {6 unsigned short int slot$iw_bmc_fw_min_rev;6 unsigned short int slot$iw_bmc_fw_maj_rev;( char slot$b_bmcfw_fill1 0[4];# } slot$r_bmc_fw_fields;$ } slot$r_bmc_fw_rev_overlay;N/**************************************** */N/* Management Port (MP) Firmware Revision */N/**************************************** */ __union {+ unsigned __int64 slot$iq_mp_fw_rev; __struct {5 unsigned short int slot$iw_mp_fw_min_rev;5 unsigned short int slot$iw_mp_fw 1_maj_rev;' char slot$b_mpfw_fill1 [4];" } slot$r_mp_fw_fields;# } slot$r_mp_fw_rev_overlay;N/************************** */N/* Base Processor Frequency */N/************************** */N unsigned __int64 slot$iq_base_proc_freq; /* true max CPU speed */ } CPU_SLOT; #if !defined(__VAXC)8#define slot$i2q_state slot$r_state_overlay.slot$iq_stateh#define slot$il_state slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$il_statev#define slot$v_bip slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_bipt#define slot$v_rc slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_rct#define slot$v_pa slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pat3#define slot$v_pp slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_ppt#define slot$v_oh slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_oht#define slot$v_cv slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_cvt#define slot$v_pv slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pvv#define slot$v_pmv slot$r_state_ov4erlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_pmvt#define slot$v_pl slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_plv#define slot$v_rip slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_rip|#define slot$v_hltreq slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields_overlay.slot$r_state_field1.slot$v_hltreqm#define slot$il_state_h slot$r_state_overlay.slot$r_stat5e_fields.slot$r_state_fields2_overlay.slot$il_state_h}#define slot$v_partid slot$r_state_overlay.slot$r_state_fields.slot$r_state_fields2_overlay.slot$r_state_field2.slot$v_partidG#define slot$iq_sal_mem_pa slot$r_sal_mem_pa_overlay.slot$iq_sal_mem_pad#define slot$il_sal_mem_pa_l slot$r_sal_mem_pa_overlay.slot$r_sal_mem_pa_fields.slot$il_sal_mem_pa_ld#define slot$il_sal_mem_pa_h slot$r_sal_mem_pa_overlay.slot$r_sal_mem_pa_fields.slot$il_sal_mem_pa_hG#define slot$iq_pal_mem_pa slot$r_pal_mem_pa6_overlay.slot$iq_pal_mem_pad#define slot$il_pal_mem_pa_l slot$r_pal_mem_pa_overlay.slot$r_pal_mem_pa_fields.slot$il_pal_mem_pa_ld#define slot$il_pal_mem_pa_h slot$r_pal_mem_pa_overlay.slot$r_pal_mem_pa_fields.slot$il_pal_mem_pa_h>#define slot$iq_pal_rev slot$r_pal_rev_overlay.slot$iq_pal_revw#define slot$il_pal_rev_l slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields1_overlay.slot$il_pal_rev_l#define slot$b_pal_min_rev slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev7_fields1_overlay.slot$r_pal_rev_l_fields.slot\$b_pal_min_rev#define slot$b_pal_maj_rev slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields1_overlay.slot$r_pal_rev_l_fields.slot\$b_pal_maj_rev#define slot$b_pal_var slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields1_overlay.slot$r_pal_rev_l_fields.slot$b_p\al_varx#define slot$il_pal_rev_h slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields_h_overlay.slot$il_pal_rev_h#define slot$iw_pal_compt sl8ot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields_h_overlay.slot$r_pal_rev_h_fields.slot\ $iw_pal_compt#define slot$iw_max_share slot$r_pal_rev_overlay.slot$r_pal_rev_fields.slot$r_pal_rev_fields_h_overlay.slot$r_pal_rev_h_fields.slot\ $iw_max_shareA#define slot$iq_cpu_type slot$r_cpu_type_overlay.slot$iq_cpu_type\#define slot$il_cpu_type_l slot$r_cpu_type_overlay.slot$r_cpu_type_fields.slot$il_cpu_type_l\#define slot$il_cpu_type_h slot$r_cpu_type_overlay.slot$r_cpu_type_field9s.slot$il_cpu_type_h>#define slot$iq_cpu_var slot$r_cpu_var_overlay.slot$iq_cpu_varv#define slot$il_cpu_var_l slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$il_cpu_var_l#define slot$v_vax_fp slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$r_cpu_var_field1.slot$v_vax_fp#define slot$v_ieee_fp slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$r_cpu_var_field1.slot$v_ieee\_fp|#define slot$v_pe slot$r_c:pu_var_overlay.slot$r_cpu_var_fields.slot$r_cpu_var_fields_overlay.slot$r_cpu_var_field1.slot$v_peX#define slot$il_cpu_var_h slot$r_cpu_var_overlay.slot$r_cpu_var_fields.slot$il_cpu_var_h>#define slot$iq_cpu_rev slot$r_cpu_rev_overlay.slot$iq_cpu_revX#define slot$il_cpu_rev_l slot$r_cpu_rev_overlay.slot$r_cpu_rev_fields.slot$il_cpu_rev_lX#define slot$il_cpu_rev_h slot$r_cpu_rev_overlay.slot$r_cpu_rev_fields.slot$il_cpu_rev_hD#define slot$iq_logout_pa slot$r_logout_pa_overlay.slot$iq_logout_pa`#d;efine slot$il_logout_pa_l slot$r_logout_pa_overlay.slot$r_logout_pa_fields.slot$il_logout_pa_l`#define slot$il_logout_pa_h slot$r_logout_pa_overlay.slot$r_logout_pa_fields.slot$il_logout_pa_hG#define slot$iq_logout_len slot$r_logout_len_overlay.slot$iq_logout_lend#define slot$il_logout_len_l slot$r_logout_len_overlay.slot$r_logout_len_fields.slot$il_logout_len_ld#define slot$il_logout_len_h slot$r_logout_len_overlay.slot$r_logout_len_fields.slot$il_logout_len_hD#define slot$iq_halt_pcbb slot$r_h<alt_pcbb_overlay.slot$iq_halt_pcbb`#define slot$il_halt_pcbb_l slot$r_halt_pcbb_overlay.slot$r_halt_pcbb_fields.slot$il_halt_pcbb_l`#define slot$il_halt_pcbb_h slot$r_halt_pcbb_overlay.slot$r_halt_pcbb_fields.slot$il_halt_pcbb_h>#define slot$iq_halt_pc slot$r_halt_pc_overlay.slot$iq_halt_pcX#define slot$il_halt_pc_l slot$r_halt_pc_overlay.slot$r_halt_pc_fields.slot$il_halt_pc_lX#define slot$il_halt_pc_h slot$r_halt_pc_overlay.slot$r_halt_pc_fields.slot$il_halt_pc_h>#define slot$iq_halt_ps slot$r=_halt_ps_overlay.slot$iq_halt_psX#define slot$il_halt_ps_l slot$r_halt_ps_overlay.slot$r_halt_ps_fields.slot$il_halt_ps_lX#define slot$il_halt_ps_h slot$r_halt_ps_overlay.slot$r_halt_ps_fields.slot$il_halt_ps_hA#define slot$iq_halt_arg slot$r_halt_arg_overlay.slot$iq_halt_arg\#define slot$il_halt_arg_l slot$r_halt_arg_overlay.slot$r_halt_arg_fields.slot$il_halt_arg_l\#define slot$il_halt_arg_h slot$r_halt_arg_overlay.slot$r_halt_arg_fields.slot$il_halt_arg_hA#define slot$iq_halt_ret slot$r_halt>_ret_overlay.slot$iq_halt_ret\#define slot$il_halt_ret_l slot$r_halt_ret_overlay.slot$r_halt_ret_fields.slot$il_halt_ret_l\#define slot$il_halt_ret_h slot$r_halt_ret_overlay.slot$r_halt_ret_fields.slot$il_halt_ret_h>#define slot$iq_halt_pv slot$r_halt_pv_overlay.slot$iq_halt_pvX#define slot$il_halt_pv_l slot$r_halt_pv_overlay.slot$r_halt_pv_fields.slot$il_halt_pv_lX#define slot$il_halt_pv_h slot$r_halt_pv_overlay.slot$r_halt_pv_fields.slot$il_halt_pv_hA#define slot$iq_haltcode slot$r_haltcode_o?verlay.slot$iq_haltcode\#define slot$il_haltcode_l slot$r_haltcode_overlay.slot$r_haltcode_fields.slot$il_haltcode_l\#define slot$il_haltcode_h slot$r_haltcode_overlay.slot$r_haltcode_fields.slot$il_haltcode_hG#define slot$iq_soft_flags slot$r_soft_flags_overlay.slot$iq_soft_flagsd#define slot$il_soft_flags_l slot$r_soft_flags_overlay.slot$r_soft_flags_fields.slot$il_soft_flags_ld#define slot$il_soft_flags_h slot$r_soft_flags_overlay.slot$r_soft_flags_fields.slot$il_soft_flags_hL#define slot$b@_incon_buf_area slot$r_incon_buf_overlay.slot$b_incon_buf_areaT#define slot$il_rxlen slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$il_rxlenT#define slot$il_txlen slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$il_txlenX#define slot$b_rxbuffer slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$b_rxbufferX#define slot$b_txbuffer slot$r_incon_buf_overlay.slot$r_incon_buf_fields.slot$b_txbufferJ#define slot$iq_cpu_sw_comp slot$r_cpu_sw_comp_overlay.slot$iq_cpu_sw_comph#define slot$iAl_cpu_sw_comp_l slot$r_cpu_sw_comp_overlay.slot$r_cpu_sw_comp_fields.slot$il_cpu_sw_comp_lh#define slot$il_cpu_sw_comp_h slot$r_cpu_sw_comp_overlay.slot$r_cpu_sw_comp_fields.slot$il_cpu_sw_comp_hV#define slot$iq_console_data_pa slot$r_console_data_pa_overlay.slot$iq_console_data_pax#define slot$il_console_data_pa_l slot$r_console_data_pa_overlay.slot$r_console_data_pa_fields.slot$il_console_data_pa_lx#define slot$il_console_data_pa_h slot$r_console_data_pa_overlay.slot$r_console_data_pa_fields.sloBt$il_console_data_pa_h\#define slot$iq_console_data_size slot$r_console_data_size_overlay.slot$iq_console_data_size#define slot$il_console_data_size_l slot$r_console_data_size_overlay.slot$r_console_data_size_fields.slot$il_console_data_size_l#define slot$il_console_data_size_h slot$r_console_data_size_overlay.slot$r_console_data_size_fields.slot$il_console_data_size_hD#define slot$iq_cpu_cache slot$r_cpu_cache_overlay.slot$iq_cpu_cache#define slot$il_cpu_cache_l slot$r_cpu_cache_overlay.slot$Cr_cpu_cache_fields.slot$r_cpu_cache_fields_overlay.slot$il_cpu_cache_l`#define slot$il_cpu_cache_h slot$r_cpu_cache_overlay.slot$r_cpu_cache_fields.slot$il_cpu_cache_hY#define slot$iq_cycle_count_freq slot$r_cycle_count_freq_overlay.slot$iq_cycle_count_freq|#define slot$il_cycle_count_freq_l slot$r_cycle_count_freq_overlay.slot$r_cycle_count_freq_fields.slot$il_cycle_count_freq_l|#define slot$il_cycle_count_freq_h slot$r_cycle_count_freq_overlay.slot$r_cycle_count_freq_fields.slot$il_cycle_count_Dfreq_hS#define slot$iq_clock_int_freq slot$r_clock_int_freq_overlay.slot$iq_clock_int_freqt#define slot$il_clock_int_freq_l slot$r_clock_int_freq_overlay.slot$r_clock_int_freq_fields.slot$il_clock_int_freq_lt#define slot$il_clock_int_freq_h slot$r_clock_int_freq_overlay.slot$r_clock_int_freq_fields.slot$il_clock_int_freq_h3#define slot$q_mces slot$r_mces_overlay.slot$q_mcesN#define slot$v_mces_mca slot$r_mces_overlay.slot$r_mces_fields.slot$v_mces_mcaN#define slot$v_mces_cpe slot$r_mces_overlaEy.slot$r_mces_fields.slot$v_mces_cpeN#define slot$v_mces_cmc slot$r_mces_overlay.slot$r_mces_fields.slot$v_mces_cmcV#define slot$v_mces_cpe_dis slot$r_mces_overlay.slot$r_mces_fields.slot$v_mces_cpe_disV#define slot$v_mces_cmc_dis slot$r_mces_overlay.slot$r_mces_fields.slot$v_mces_cmc_disP#define slot$v_mces_init slot$r_mces_overlay.slot$r_mces_fields.slot$v_mces_init>#define slot$iq_acpi_id slot$r_acpi_id_overlay.slot$iq_acpi_idX#define slot$il_acpi_id_l slot$r_acpi_id_overlay.slot$r_acpi_id_fiFelds.slot$il_acpi_id_lX#define slot$il_acpi_id_h slot$r_acpi_id_overlay.slot$r_acpi_id_fields.slot$il_acpi_id_hA#define slot$pq_acpi_uid slot$r_acpi_uid_overlay.slot$pq_acpi_uidE#define slot$ps_acpi_uid_l slot$r_acpi_uid_overlay.slot$ps_acpi_uid_lG#define slot$iq_sys_fw_rev slot$r_sys_fw_rev_overlay.slot$iq_sys_fw_revd#define slot$iw_sys_fw_min_rev slot$r_sys_fw_rev_overlay.slot$r_sys_fw_fields.slot$iw_sys_fw_min_revd#define slot$iw_sys_fw_maj_rev slot$r_sys_fw_rev_overlay.slot$r_sys_fw_fieldGs.slot$iw_sys_fw_maj_revG#define slot$iq_bmc_fw_rev slot$r_bmc_fw_rev_overlay.slot$iq_bmc_fw_revd#define slot$iw_bmc_fw_min_rev slot$r_bmc_fw_rev_overlay.slot$r_bmc_fw_fields.slot$iw_bmc_fw_min_revd#define slot$iw_bmc_fw_maj_rev slot$r_bmc_fw_rev_overlay.slot$r_bmc_fw_fields.slot$iw_bmc_fw_maj_revD#define slot$iq_mp_fw_rev slot$r_mp_fw_rev_overlay.slot$iq_mp_fw_rev`#define slot$iw_mp_fw_min_rev slot$r_mp_fw_rev_overlay.slot$r_mp_fw_fields.slot$iw_mp_fw_min_rev`#define slot$iw_mp_fw_maj_rev slot H$r_mp_fw_rev_overlay.slot$r_mp_fw_fields.slot$iw_mp_fw_maj_rev"#endif /* #if !defined(__VAXC) */ #define SLOT$C_LENGTH 1152#define SLOT$K_LENGTH 1152N#define SLOT$S_SLOTDEF 1072 /* Old size name, synonym */N/********************************* */N/* Memory Cluster Descriptor (MCD) */N/********************************* */ c#if !defined(__NOBASEA ILIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mcd {N/**************************************** */N/* Offset from structure base to next MCD */N/* On IA64 base is the ConfigTree PA */N/* On X86 base is the HWRPB PA J */N/* -1 if end of list, 0 if not yet valid */N/**************************************** */#pragma __nomember_alignment __int64 mcd$iq_usage_link;N/*************************************** */N/* First PFN in contiguous range of PFNs described by this MCD */N/*************************************** */& unsigned __int64 mcd$iq_start_pfn;KN/************************************* */N/* Count of PFNs described by this MCD */N/************************************* */& unsigned __int64 mcd$iq_pfn_count;N/******************************************** */N/* UEFI attribute flags passed through to VMS */N/******************************************** L */& unsigned __int64 mcd$iq_attribute;N/**************************** */N/* Memory Usage Field Values: */N/* 0 - INVALID */N/* 1 - CONSOLE */N/* 2 - NVRAM */N/* 3 - SYSTEM M */N/* 4 - SHARED */N/* 5 - MEMORYDISK */N/* 6 - RSVD_DMP Transient Type used by BootMgr */N/* 7 - RSVD_BSR Transient Type used by BootMgr */N/* 8 - HWRPB */N/* 9 - 31 Spare N*/N/***************************** */# unsigned int mcd$il_usage_bits;N/************************************** */N/* Reserved for alignment, must be zero */N/************************************** */ unsigned int mcd$il_mbz_1; } MCD;#define MCDTYPE$K_INVALID 0#define MCDTYPE$K_CONSOLE 1#define MCDTYPE$K_NVRAM 2#define MCDT OYPE$K_SYSTEM 3#define MCDTYPE$K_SHARED 4#define MCDTYPE$K_MEMORY_DISK 5#define MCDTYPE$K_RSVD_DMP 6#define MCDTYPE$K_RSVD_BSR 7#define MCDTYPE$K_HWRPB 8#define MCDTYPE$K_KERNEL_BASE 9N/********************************************************** */N/* Head of Physical Memory Cluster Descriptor List (MEMDSC) */N/********************************************************** */N#define HWRPB_PMD$C_LENGTH 24 /* Length of HWRPB_PMD$ P */N#define HWRPB_PMD$K_LENGTH 24 /* Length of HWRPB_PMD$ */N/****************************** */N#define HWRPB_PMD$S_NULLPMDDEF 80 /* Size of NULL memory descr. */N/**************************** */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomemb Qer_alignment#endiftypedef struct _pmd {N/******************************* */N/* Checksum of Memory Descriptor (MEMDSC+8 through MEMDSC_END) */N/******************************* */#pragma __nomember_alignment __union {- unsigned __int64 hwrpb_pmd$iq_chksum; __struct {/ unsigned int hwrpb_pmd$il_chksum_l;/ unsigned int hwrpb_pmd$il_chksum_h;( R } hwrpb_pmd$r_chksum_fields;% } hwrpb_pmd$r_chksum_overlay;N/*************************************** */N/* Optional Implementation-Specific Data */N/*************************************** */ __union {/ unsigned __int64 hwrpb_pmd$iq_opt_data; __struct {1 unsigned int hwrpb_pmd$il_opt_data_l;1 unsigned int hwrpb_pmd$il_opt_data_h S;* } hwrpb_pmd$r_opt_data_fields;' } hwrpb_pmd$r_opt_data_overlay;N/*************************** */N/* Number of MCD's in MEMDSC */N/*************************** */ __union {4 unsigned __int64 hwrpb_pmd$iq_cluster_count; __struct {6 unsigned int hwrpb_pmd$il_cluster_count_l;6 unsigned int hwr Tpb_pmd$il_cluster_count_h;/ } hwrpb_pmd$r_cluster_count_fields;, } hwrpb_pmd$r_cluster_count_overlay;N/* Physical Memory Region (PMR) */N/****************************** */N/* For system with PHYSICALLY DIS-CONTIGUOUS memory, PMR points to */L/* an array of Physical Memory Regions (PMR). */ __union { __union {N unsigned __int64 U hwrpb_pmd$iq_pmr; /* Start of first region */ __struct {0 unsigned int hwrpb_pmd$il_pmr_l;0 unsigned int hwrpb_pmd$il_pmr_h;) } hwrpb_pmd$r_pmr_fields;& } hwrpb_pmd$r_pmr_overlay;N/* For system with PHYSICALLY CONTIGUOUS memory, there are only two regions */P/* defined. The first region describes memory in use by the console, and the */N/* second region describes memory for use by the system. */ V __union {Y unsigned __int64 hwrpb_pmd$iq_cn_pfn_start; /* Start PFN of console region */ __struct {9 unsigned int hwrpb_pmd$il_cn_pfn_start_l;9 unsigned int hwrpb_pmd$il_cn_pfn_start_h;2 } hwrpb_pmd$r_cn_pfn_start_fields;/ } hwrpb_pmd$r_cn_pfn_start_overlay;[/* For system with DYNAMIC memory descriptors, there is only one region defined. It is a */^/* NULL cluster descriptor. It describes the listheads W of shared and private memory cluster */\/* descriptors. The first field which is normally the PFN_START field, must be set to -1. */ __union {N __int64 hwrpb_pmd$iq_null_mbmo; /* Must be minus one */ __struct {- int hwrpb_pmd$il_null_mbmo_l;- int hwrpb_pmd$il_null_mbmo_h;/ } hwrpb_pmd$r_null_mbmo_fields;, } hwrpb_pmd$r_null_mbmo_overlay;) } hwrpb_pmd$r_pmr_region_overlay; __un Xion {N/******************************* */N/* Number of PFN's in the region */N/******************************* */3 unsigned __int64 hwrpb_pmd$iq_cn_pfn_count; __struct {5 unsigned int hwrpb_pmd$il_cn_pfn_count_l;5 unsigned int hwrpb_pmd$il_cn_pfn_count_h;. } hwrpb_pmd$r_cn_pfn_count_fields;N/********************* Y************************** */N/* Must be zero field in NULL cluster descriptor */N/*********************************************** */& __int64 hwrpb_pmd$iq_null_mbz; __struct {( int hwrpb_pmd$il_null_mbz_l;( int hwrpb_pmd$il_null_mbz_h;* } hwrpb_pmd$r_null_mbz_fields;+ } hwrpb_pmd$r_cn_pfn_count_overlay; __union {N/*********************************** Z** */N/* Number of tested PFNs in the region */N/************************************* */4 unsigned __int64 hwrpb_pmd$iq_cn_test_count; __struct {6 unsigned int hwrpb_pmd$il_cn_test_count_l;6 unsigned int hwrpb_pmd$il_cn_test_count_h;/ } hwrpb_pmd$r_cn_test_count_fields;N/*********************************************** [ */N/* Must be zero field in NULL cluster descriptor */N/*********************************************** */N __int64 hwrpb_pmd$iq_null_test_mbz; /* Must be zero */ __struct {- int hwrpb_pmd$il_null_test_mbz_l;- int hwrpb_pmd$il_null_test_mbz_h;/ } hwrpb_pmd$r_null_test_mbz_fields;, } hwrpb_pmd$r_cn_test_count_overlay; __union {N/******************* \*************** */N/* Virtual Address of Memory bitmap */N/********************************** */3 unsigned __int64 hwrpb_pmd$iq_cn_bitmap_va; __struct {5 unsigned int hwrpb_pmd$il_cn_bitmap_va_l;5 unsigned int hwrpb_pmd$il_cn_bitmap_va_h;. } hwrpb_pmd$r_cn_bitmap_va_fields;N/******************************************** ] */N/* Physical offset to listhead of shared MCDs */N/* in NULL cluster descriptor */N/******************************************** */2 unsigned __int64 hwrpb_pmd$iq_null_shr_lh; __struct {4 unsigned int hwrpb_pmd$il_null_shr_lh_l;4 unsigned int hwrpb_pmd$il_null_shr_lh_h;- } hwrpb_pmd$r_null_shr_lh_fields;+ ^ } hwrpb_pmd$r_cn_bitmap_va_overlay; __union {N/**************************** */N/* Physical Address of bitmap */N/**************************** */3 unsigned __int64 hwrpb_pmd$iq_cn_bitmap_pa; __struct {5 unsigned int hwrpb_pmd$il_cn_bitmap_pa_l;5 unsigned int hwrpb_pmd$il_cn_bitmap_pa_h;. } hwrpb_pm _d$r_cn_bitmap_pa_fields;N/********************************************** */N/* Physical offset to first MCD in private list */N/* in NULL cluster descriptor */N/********************************************** */6 unsigned __int64 hwrpb_pmd$iq_null_prv_offset; __struct {8 unsigned int hwrpb_pmd$il_null_prv_offset_l;8 unsigned int ` hwrpb_pmd$il_null_prv_offset_h;* } hwrpb_pmd$r_null_prv_fields;+ } hwrpb_pmd$r_cn_bitmap_pa_overlay; __union {N/******************** */N/* Checksum of bitmap */N/******************** */7 unsigned __int64 hwrpb_pmd$iq_cn_bitmap_chksum; __struct {9 unsigned int hwrpb_pmd$il_cn_bitma ap_chksum_l;9 unsigned int hwrpb_pmd$il_cn_bitmap_chksum_h;1 } hwrpb_pmd$r_cn_bitmap_chksum_field;N/*********************************************** */N/* Must be zero field in NULL cluster descriptor */N/*********************************************** */- __int64 hwrpb_pmd$iq_null_chksum_mbz; __struct {/ int hwrpb_pmd$il_null_chksum_mbz_l;/ int hwrp bb_pmd$il_null_chksum_mbz_h;1 } hwrpb_pmd$r_null_chksum_mbz_fields;- } hwrpb_pmd$r_cn_bitmap_chksum_overl; __union {N/********************* */N/* Cluster Usage Flags */N/********************* *// unsigned __int64 hwrpb_pmd$iq_cn_usage; __struct {1 unsigned int hwrpb_pmd$il_cn_usage_l c;1 unsigned int hwrpb_pmd$il_cn_usage_h;* } hwrpb_pmd$r_cn_usage_fields;N/*********************************************** */N/* Must be zero field in NULL cluster descriptor */N/*********************************************** */, __int64 hwrpb_pmd$iq_null_usage_mbz; __struct {. int hwrpb_pmd$il_null_usage_mbz_l;. int hwrpb_pmd$il_null_usage_mbz_h;0 d } hwrpb_pmd$r_null_usage_mbz_fields;' } hwrpb_pmd$r_cn_usage_overlay;N/* Start PFN of system region */N/**************************** */ __union {3 unsigned __int64 hwrpb_pmd$iq_sy_pfn_start; __struct {5 unsigned int hwrpb_pmd$il_sy_pfn_start_l;5 unsigned int hwrpb_pmd$il_sy_pfn_start_h;. } hwrpb_pmd$r_sy_pfn_start_fields;+ e } hwrpb_pmd$r_sy_pfn_start_overlay;N/************************** */N/* Number of PFNs in region */N/************************** */ __union {3 unsigned __int64 hwrpb_pmd$iq_sy_pfn_count; __struct {5 unsigned int hwrpb_pmd$il_sy_pfn_count_l;5 unsigned int hwrpb_pmd$il_sy_pfn_count_h;. } hwrpb_ fpmd$r_sy_pfn_count_fields;+ } hwrpb_pmd$r_sy_pfn_count_overlay;N/********************************* */N/* Number of tested PFNs in region */N/********************************* */ __union {4 unsigned __int64 hwrpb_pmd$iq_sy_test_count; __struct {6 unsigned int hwrpb_pmd$il_sy_test_count_l;6 unsigned int hwrpb_pmd$il_sy_tes gt_count_h;/ } hwrpb_pmd$r_sy_test_count_fields;, } hwrpb_pmd$r_sy_test_count_overlay;N/*************************** */N/* Virtual Address of bitmap */N/*************************** */ __union {3 unsigned __int64 hwrpb_pmd$iq_sy_bitmap_va; __struct {5 unsigned int hwrpb_pmd$il_sy_bitmap_va_l;5 h unsigned int hwrpb_pmd$il_sy_bitmap_va_h;. } hwrpb_pmd$r_sy_bitmap_va_fields;+ } hwrpb_pmd$r_sy_bitmap_va_overlay;N/**************************** */N/* Physical Address of bitmap */N/**************************** */ __union {3 unsigned __int64 hwrpb_pmd$iq_sy_bitmap_pa; __struct {5 unsigned int hwrpb_pmd i$il_sy_bitmap_pa_l;5 unsigned int hwrpb_pmd$il_sy_bitmap_pa_h;. } hwrpb_pmd$r_sy_bitmap_pa_fields;+ } hwrpb_pmd$r_sy_bitmap_pa_overlay;N/******************** */N/* Checksum of bitmap */N/******************** */ __union {7 unsigned __int64 hwrpb_pmd$iq_sy_bitmap_chksum; __struct { j9 unsigned int hwrpb_pmd$il_sy_bitmap_chksum_l;9 unsigned int hwrpb_pmd$il_sy_bitmap_chksum_h;1 } hwrpb_pmd$r_sy_bitmap_chksum_field;- } hwrpb_pmd$r_sy_bitmap_chksum_overl;N/********************* */N/* Cluster Usage Flags */N/********************* */ __union {/ unsigned __int64 hwr kpb_pmd$iq_sy_usage; __struct {1 unsigned int hwrpb_pmd$il_sy_usage_l;1 unsigned int hwrpb_pmd$il_sy_usage_h;* } hwrpb_pmd$r_sy_usage_fields;' } hwrpb_pmd$r_sy_usage_overlay; } PMD; #if !defined(__VAXC)J#define hwrpb_pmd$iq_chksum hwrpb_pmd$r_chksum_overlay.hwrpb_pmd$iq_chksumh#define hwrpb_pmd$il_chksum_l hwrpb_pmd$r_chksum_overlay.hwrpb_pmd$r_chksum_fields.hwrpb_pmd$il_chksum_lh#define hwrpb_pmd$il_chksum_h hwrpb_pmd$r_chksum_ovelrlay.hwrpb_pmd$r_chksum_fields.hwrpb_pmd$il_chksum_hP#define hwrpb_pmd$iq_opt_data hwrpb_pmd$r_opt_data_overlay.hwrpb_pmd$iq_opt_datap#define hwrpb_pmd$il_opt_data_l hwrpb_pmd$r_opt_data_overlay.hwrpb_pmd$r_opt_data_fields.hwrpb_pmd$il_opt_data_lp#define hwrpb_pmd$il_opt_data_h hwrpb_pmd$r_opt_data_overlay.hwrpb_pmd$r_opt_data_fields.hwrpb_pmd$il_opt_data_h_#define hwrpb_pmd$iq_cluster_count hwrpb_pmd$r_cluster_count_overlay.hwrpb_pmd$iq_cluster_count#define hwrpb_pmd$il_cluster_count_l hwrpb_pmmd$r_cluster_count_overlay.hwrpb_pmd$r_cluster_count_fields.hwrpb_pmd$il_cluster_count_l#define hwrpb_pmd$il_cluster_count_h hwrpb_pmd$r_cluster_count_overlay.hwrpb_pmd$r_cluster_count_fields.hwrpb_pmd$il_cluster_count_h`#define hwrpb_pmd$iq_pmr hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_pmr_overlay.hwrpb_pmd$iq_pmr{#define hwrpb_pmd$il_pmr_l hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_pmr_overlay.hwrpb_pmd$r_pmr_fields.hwrpb_pmd$il_pmr_l{#define hwrpb_pmd$il_pmr_h hwrpb_pmd$r_pmr_region_overlay.nhwrpb_pmd$r_pmr_overlay.hwrpb_pmd$r_pmr_fields.hwrpb_pmd$il_pmr_h{#define hwrpb_pmd$iq_cn_pfn_start hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_cn_pfn_start_overlay.hwrpb_pmd$iq_cn_pfn_start#define hwrpb_pmd$il_cn_pfn_start_l hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_cn_pfn_start_overlay.hwrpb_pmd$r_cn_pfn_start_fields\.hwrpb_pmd$il_cn_pfn_start_l#define hwrpb_pmd$il_cn_pfn_start_h hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_cn_pfn_start_overlay.hwrpb_pmd$r_cn_pfn_start_fields\.hwrpb_pmd$il_ocn_pfn_start_hr#define hwrpb_pmd$iq_null_mbmo hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_null_mbmo_overlay.hwrpb_pmd$iq_null_mbmo#define hwrpb_pmd$il_null_mbmo_l hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_null_mbmo_overlay.hwrpb_pmd$r_null_mbmo_fields.hwrpb_pm\d$il_null_mbmo_l#define hwrpb_pmd$il_null_mbmo_h hwrpb_pmd$r_pmr_region_overlay.hwrpb_pmd$r_null_mbmo_overlay.hwrpb_pmd$r_null_mbmo_fields.hwrpb_pm\d$il_null_mbmo_h\#define hwrpb_pmd$iq_cn_pfn_count hwrpb_pmd$r_cn_pfn_count_overlay.hwrppb_pmd$iq_cn_pfn_count#define hwrpb_pmd$il_cn_pfn_count_l hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_cn_pfn_count_fields.hwrpb_pmd$il_cn_pfn_count_l#define hwrpb_pmd$il_cn_pfn_count_h hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_cn_pfn_count_fields.hwrpb_pmd$il_cn_pfn_count_hT#define hwrpb_pmd$iq_null_mbz hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$iq_null_mbzt#define hwrpb_pmd$il_null_mbz_l hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_null_mbz_fields.hwrpb_pmd$il_null_mbz_lt#define hwrpb_pmd$qil_null_mbz_h hwrpb_pmd$r_cn_pfn_count_overlay.hwrpb_pmd$r_null_mbz_fields.hwrpb_pmd$il_null_mbz_h_#define hwrpb_pmd$iq_cn_test_count hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$iq_cn_test_count#define hwrpb_pmd$il_cn_test_count_l hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$r_cn_test_count_fields.hwrpb_pmd$il_cn_test_count_l#define hwrpb_pmd$il_cn_test_count_h hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$r_cn_test_count_fields.hwrpb_pmd$il_cn_test_count_h_#define hwrpb_pmd$iq_null_test_mbz hwrpbr_pmd$r_cn_test_count_overlay.hwrpb_pmd$iq_null_test_mbz#define hwrpb_pmd$il_null_test_mbz_l hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$r_null_test_mbz_fields.hwrpb_pmd$il_null_test_mbz_l#define hwrpb_pmd$il_null_test_mbz_h hwrpb_pmd$r_cn_test_count_overlay.hwrpb_pmd$r_null_test_mbz_fields.hwrpb_pmd$il_null_test_mbz_h\#define hwrpb_pmd$iq_cn_bitmap_va hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$iq_cn_bitmap_va#define hwrpb_pmd$il_cn_bitmap_va_l hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_cn_bistmap_va_fields.hwrpb_pmd$il_cn_bitmap_va_l#define hwrpb_pmd$il_cn_bitmap_va_h hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_cn_bitmap_va_fields.hwrpb_pmd$il_cn_bitmap_va_hZ#define hwrpb_pmd$iq_null_shr_lh hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$iq_null_shr_lh}#define hwrpb_pmd$il_null_shr_lh_l hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_null_shr_lh_fields.hwrpb_pmd$il_null_shr_lh_l}#define hwrpb_pmd$il_null_shr_lh_h hwrpb_pmd$r_cn_bitmap_va_overlay.hwrpb_pmd$r_null_shr_lh_fields.hwrpb_pmd$il_tnull_shr_lh_h\#define hwrpb_pmd$iq_cn_bitmap_pa hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$iq_cn_bitmap_pa#define hwrpb_pmd$il_cn_bitmap_pa_l hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_cn_bitmap_pa_fields.hwrpb_pmd$il_cn_bitmap_pa_l#define hwrpb_pmd$il_cn_bitmap_pa_h hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_cn_bitmap_pa_fields.hwrpb_pmd$il_cn_bitmap_pa_hb#define hwrpb_pmd$iq_null_prv_offset hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$iq_null_prv_offset#define hwrpb_pmd$il_null_prv_offsetu_l hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_null_prv_fields.hwrpb_pmd$il_null_prv_offset_l#define hwrpb_pmd$il_null_prv_offset_h hwrpb_pmd$r_cn_bitmap_pa_overlay.hwrpb_pmd$r_null_prv_fields.hwrpb_pmd$il_null_prv_offset_hf#define hwrpb_pmd$iq_cn_bitmap_chksum hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$iq_cn_bitmap_chksum#define hwrpb_pmd$il_cn_bitmap_chksum_l hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$r_cn_bitmap_chksum_field.hwrpb_pmd$il_cn_bitma\ p_chksum_l#define hwrpb_pmd$il_cn_bitmvap_chksum_h hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$r_cn_bitmap_chksum_field.hwrpb_pmd$il_cn_bitma\ p_chksum_hd#define hwrpb_pmd$iq_null_chksum_mbz hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$iq_null_chksum_mbz#define hwrpb_pmd$il_null_chksum_mbz_l hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$r_null_chksum_mbz_fields.hwrpb_pmd$il_null_chks\um_mbz_l#define hwrpb_pmd$il_null_chksum_mbz_h hwrpb_pmd$r_cn_bitmap_chksum_overl.hwrpb_pmd$r_null_chksum_mbz_fields.hwrpb_pmd$il_null_chks\um_mbz_hwP#define hwrpb_pmd$iq_cn_usage hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$iq_cn_usagep#define hwrpb_pmd$il_cn_usage_l hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$r_cn_usage_fields.hwrpb_pmd$il_cn_usage_lp#define hwrpb_pmd$il_cn_usage_h hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$r_cn_usage_fields.hwrpb_pmd$il_cn_usage_h\#define hwrpb_pmd$iq_null_usage_mbz hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$iq_null_usage_mbz#define hwrpb_pmd$il_null_usage_mbz_l hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$r_null_usage_mbz_fieldsx.hwrpb_pmd$il_null_usage_mbz_l#define hwrpb_pmd$il_null_usage_mbz_h hwrpb_pmd$r_cn_usage_overlay.hwrpb_pmd$r_null_usage_mbz_fields.hwrpb_pmd$il_null_usage_mbz_h\#define hwrpb_pmd$iq_sy_pfn_start hwrpb_pmd$r_sy_pfn_start_overlay.hwrpb_pmd$iq_sy_pfn_start#define hwrpb_pmd$il_sy_pfn_start_l hwrpb_pmd$r_sy_pfn_start_overlay.hwrpb_pmd$r_sy_pfn_start_fields.hwrpb_pmd$il_sy_pfn_start_l#define hwrpb_pmd$il_sy_pfn_start_h hwrpb_pmd$r_sy_pfn_start_overlay.hwrpb_pmd$r_sy_pfn_start_fields.hwrpb_pmd$il_sy_pyfn_start_h\#define hwrpb_pmd$iq_sy_pfn_count hwrpb_pmd$r_sy_pfn_count_overlay.hwrpb_pmd$iq_sy_pfn_count#define hwrpb_pmd$il_sy_pfn_count_l hwrpb_pmd$r_sy_pfn_count_overlay.hwrpb_pmd$r_sy_pfn_count_fields.hwrpb_pmd$il_sy_pfn_count_l#define hwrpb_pmd$il_sy_pfn_count_h hwrpb_pmd$r_sy_pfn_count_overlay.hwrpb_pmd$r_sy_pfn_count_fields.hwrpb_pmd$il_sy_pfn_count_h_#define hwrpb_pmd$iq_sy_test_count hwrpb_pmd$r_sy_test_count_overlay.hwrpb_pmd$iq_sy_test_count#define hwrpb_pmd$il_sy_test_count_l hwrpbz_pmd$r_sy_test_count_overlay.hwrpb_pmd$r_sy_test_count_fields.hwrpb_pmd$il_sy_test_count_l#define hwrpb_pmd$il_sy_test_count_h hwrpb_pmd$r_sy_test_count_overlay.hwrpb_pmd$r_sy_test_count_fields.hwrpb_pmd$il_sy_test_count_h\#define hwrpb_pmd$iq_sy_bitmap_va hwrpb_pmd$r_sy_bitmap_va_overlay.hwrpb_pmd$iq_sy_bitmap_va#define hwrpb_pmd$il_sy_bitmap_va_l hwrpb_pmd$r_sy_bitmap_va_overlay.hwrpb_pmd$r_sy_bitmap_va_fields.hwrpb_pmd$il_sy_bitmap_va_l#define hwrpb_pmd$il_sy_bitmap_va_h hwrpb_pmd$r_sy_bitma{p_va_overlay.hwrpb_pmd$r_sy_bitmap_va_fields.hwrpb_pmd$il_sy_bitmap_va_h\#define hwrpb_pmd$iq_sy_bitmap_pa hwrpb_pmd$r_sy_bitmap_pa_overlay.hwrpb_pmd$iq_sy_bitmap_pa#define hwrpb_pmd$il_sy_bitmap_pa_l hwrpb_pmd$r_sy_bitmap_pa_overlay.hwrpb_pmd$r_sy_bitmap_pa_fields.hwrpb_pmd$il_sy_bitmap_pa_l#define hwrpb_pmd$il_sy_bitmap_pa_h hwrpb_pmd$r_sy_bitmap_pa_overlay.hwrpb_pmd$r_sy_bitmap_pa_fields.hwrpb_pmd$il_sy_bitmap_pa_hf#define hwrpb_pmd$iq_sy_bitmap_chksum hwrpb_pmd$r_sy_bitmap_chksum_overl.hwrpb|_pmd$iq_sy_bitmap_chksum#define hwrpb_pmd$il_sy_bitmap_chksum_l hwrpb_pmd$r_sy_bitmap_chksum_overl.hwrpb_pmd$r_sy_bitmap_chksum_field.hwrpb_pmd$il_sy_bitma\ p_chksum_l#define hwrpb_pmd$il_sy_bitmap_chksum_h hwrpb_pmd$r_sy_bitmap_chksum_overl.hwrpb_pmd$r_sy_bitmap_chksum_field.hwrpb_pmd$il_sy_bitma\ p_chksum_hP#define hwrpb_pmd$iq_sy_usage hwrpb_pmd$r_sy_usage_overlay.hwrpb_pmd$iq_sy_usagep#define hwrpb_pmd$il_sy_usage_l hwrpb_pmd$r_sy_usage_overlay.hwrpb_pmd$r_sy_usage_fields.hwrpb_pmd$il_sy_u}sage_lp#define hwrpb_pmd$il_sy_usage_h hwrpb_pmd$r_sy_usage_overlay.hwrpb_pmd$r_sy_usage_fields.hwrpb_pmd$il_sy_usage_h"#endif /* #if !defined(__VAXC) */ N#define HWRPB_PMD$S_PMDDEF 136 /* Old size name - synonym */#define HWRPB_LANG$K_UNKNOWN 0#define HWRPB_LANG$K_DANISH 48#define HWRPB_LANG$K_GERMAN 50#define HWRPB_LANG$K_SWISS 52 #define HWRPB_LANG$K_AMERICAN 54#define HWRPB_LANG$K_BRITISH 56#define HWRPB_LANG$K_SPANISH 58#define HWRPB_LANG$K_FRENCH 60 #d ~efine HWRPB_LANG$K_CANADIAN 62#define HWRPB_LANG$K_ROMANDE 64#define HWRPB_LANG$K_ITALIAN 66##define HWRPB_LANG$K_NETHERLANDS 68#define HWRPB_LANG$K_NORSK 70"#define HWRPB_LANG$K_PORTUGUESE 72#define HWRPB_LANG$K_SUOMI 74#define HWRPB_LANG$K_SWEDISH 76#define HWRPB_LANG$K_VLAAMS 78N/*********************** */N/* Console Routine Block */N/***********************  */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _hwrpb_crb {N/************************************* */N/* VA of DISPATCH Procedure Descriptor */N/************************************* */#pra gma __nomember_alignment __union {5 unsigned __int64 hwrpb_crb$iq_va_dispatch_pd; __struct {7 unsigned int hwrpb_crb$il_va_dispatch_pd_l;7 unsigned int hwrpb_crb$il_va_dispatch_pd_h;0 } hwrpb_crb$r_va_dispatch_pd_fields;- } hwrpb_crb$r_va_dispatch_pd_overlay;N/************************************* */N/* PA of DISPATCH Procedure Descriptor */N/*********** ************************** */ __union {5 unsigned __int64 hwrpb_crb$iq_pa_dispatch_pd; __struct {7 unsigned int hwrpb_crb$il_pa_dispatch_pd_l;7 unsigned int hwrpb_crb$il_pa_dispatch_pd_h;0 } hwrpb_crb$r_pa_dispatch_pd_fields;- } hwrpb_crb$r_pa_dispatch_pd_overlay;N/********************************** */N/* VA of FIXUP Procedure Descriptor  */N/********************************** */ __union {2 unsigned __int64 hwrpb_crb$iq_va_fixup_pd; __struct {4 unsigned int hwrpb_crb$il_va_fixup_pd_l;4 unsigned int hwrpb_crb$il_va_fixup_pd_h;- } hwrpb_crb$r_va_fixup_pd_fields;* } hwrpb_crb$r_va_fixup_pd_overlay;N/********************************** */N/* PA of FIXUP Procedure D escriptor */N/********************************** */ __union {2 unsigned __int64 hwrpb_crb$iq_pa_fixup_pd; __struct {4 unsigned int hwrpb_crb$il_pa_fixup_pd_l;4 unsigned int hwrpb_crb$il_pa_fixup_pd_h;- } hwrpb_crb$r_pa_fixup_pd_fields;* } hwrpb_crb$r_pa_fixup_pd_overlay;N/******************************** */N/*  Number of entries in VA/PA map */N/******************************** */ __union {0 unsigned __int64 hwrpb_crb$iq_map_count; __struct {2 unsigned int hwrpb_crb$il_map_count_l;2 unsigned int hwrpb_crb$il_map_count_h;+ } hwrpb_crb$r_map_count_fields;( } hwrpb_crb$r_map_count_overlay;N/******************************  */N/* Number of pages to be mapped */N/****************************** */ __union {1 unsigned __int64 hwrpb_crb$iq_page_count; __struct {3 unsigned int hwrpb_crb$il_page_count_l;3 unsigned int hwrpb_crb$il_page_count_h;, } hwrpb_crb$r_page_count_fields;) } hwrpb_crb$r_page_count_overlay;N/*******************  */N/* Console VA/PA map */N/******************* */ __union {/ unsigned __int64 hwrpb_crb$iq_vapa_map; __struct {1 unsigned int hwrpb_crb$il_vapa_map_l;1 unsigned int hwrpb_crb$il_vapa_map_h;* } hwrpb_crb$r_vapa_map_fields;' } hwrpb_crb$r_vapa_map_overlay; } HWRPB_CRB; #if !defined(__VAXC)b#define hwrpb_crb$iq_va_dispatch_pd hwrpb_crb$r_va_dispatch_pd_overlay.hwrpb_crb$iq_va_dispatch_pd#define hwrpb_crb$il_va_dispatch_pd_l hwrpb_crb$r_va_dispatch_pd_overlay.hwrpb_crb$r_va_dispatch_pd_fields.hwrpb_crb$il_va_dispatch\_pd_l#define hwrpb_crb$il_va_dispatch_pd_h hwrpb_crb$r_va_dispatch_pd_overlay.hwrpb_crb$r_va_dispatch_pd_fields.hwrpb_crb$il_va_dispatch\_pd_hb#define hwrpb_crb$iq_pa_dispatch_pd hwrpb_crb$r_pa_dispatch_pd_overlay.hwrpb_crb$iq_pa_dispatch_pd#define hwrpb_crb$il_pa_dispatch_pd_l hwrpb_crb$r_pa_dispatch_pd_overlay.hwrpb_crb$r_pa_dispatch_pd_fields.hwrpb_crb$il_pa_dispatch\_pd_l#define hwrpb_crb$il_pa_dispatch_pd_h hwrpb_crb$r_pa_dispatch_pd_overlay.hwrpb_crb$r_pa_dispatch_pd_fields.hwrpb_crb$il_pa_dispatch\_pd_hY#define hwrpb_crb$iq_va_fixup_pd hwrpb_crb$r_va_fixup_pd_overlay.hwrpb_crb$iq_va_fixup_pd|#define hwrpb_crb$il_va_fixup_pd_l hwrpb_crb$r_va_fixup_pd_overlay.hwrpb_crb$r_va_fixup_pd_fields.hwrpb_crb$il_va_fixup_pd_l|#define hwrpb_crb$il_va_fixup_pd_h hwrpb_crb$r_va_fixup_pd_overlay.hwrpb_crb$r_va_fixup_pd_fields.hwrpb_crb$il_va_fixup_pd_hY#define hwrpb_crb$iq_pa_fixup_pd hwrpb_crb$r_pa_fixup_pd_overlay.hwrpb_crb$iq_pa_fixup_pd|#define hwrpb_crb$il_pa_fixup_pd_l hwrpb_crb$r_pa_fixup_pd_overlay.hwrpb_crb$r_pa_fixup_pd_fields.hwrpb_crb$il_pa_fixup_pd_l|#define hwrpb_crb$il_pa_fixup_pd_h hwrpb_crb$r_pa_fixup_pd_overlay.hwrpb_crb$r_pa_fixup_pd_fields.hwrpb_crb$il_pa_fixup_pd_hS#define hwrpb_crb$iq_map_count hwrpb_crb$r_map_count_overlay.hwrpb_crb$iq_map_countt#define hwrpb_crb$il_map_count_l hwrpb_crb$r_map_count_overlay.hwrpb_crb$r_map_count_fields.hwrpb_crb$il_map_count_lt#define hwrpb_crb$il_map_count_h hwrpb_crb$r_map_count_overlay.hwrpb_crb$r_map_count_fields.hwrpb_crb$il_map_count_hV#define hwrpb_crb$iq_page_count hwrpb_crb$r_page_count_overlay.hwrpb_crb$iq_page_countx#define hwrpb_crb$il_page_count_l hwrpb_crb$r_page_count_overlay.hwrpb_crb$r_page_count_fields.hwrpb_crb$il_page_count_lx#define hwrpb_crb$il_page_count_h hwrpb_crb$r_page_count_overlay.hwrpb_crb$r_page_count_fields.hwrpb_crb$il_page_count_hP#define hwrpb_crb$iq_vapa_map hwrpb_crb$r_vapa_map_overlay.hwrpb_crb$iq_vapa_mapp#define hwrpb_crb$il_vapa_map_l hwrpb_crb$r_vapa_map_overlay.hwrpb_crb$r_vapa_map_fields.hwrpb_crb$il_vapa_map_lp#define hwrpb_crb$il_vapa_map_h hwrpb_crb$r_vapa_map_overlay.hwrpb_crb$r_vapa_map_fields.hwrpb_crb$il_vapa_map_h"#endif /* #if !defined(__VAXC) */ N#define HWRPB_CRB$C_LENGTH 56 /* Length of CRB  */N#define HWRPB_CRB$K_LENGTH 56 /* Length of CRB */N#define HWRPB_CRB$S_CRBDEF 56 /* Old size name - synonym */N/****************************** */N/* Virtual/Physical Address Map */N/****************************** */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _vapamap {N/************************* */N/* Console Virtual Address */N/************************* */#pragma __nomember_alignment __union {- unsigned __int64 hwrpb_vapamap$iq_va; __struct {/ un signed int hwrpb_vapamap$il_va_l;/ unsigned int hwrpb_vapamap$il_va_h;( } hwrpb_vapamap$r_va_fields;% } hwrpb_vapamap$r_va_overlay;N/************************** */N/* Console Physical Address */N/************************** */ __union {- unsigned __int64 hwrpb_vapamap$iq_pa; __struct {/ unsigned int hwrpb_vapamap$il_pa_l;/ unsigned int hwrpb_vapamap$il_pa_h;( } hwrpb_vapamap$r_pa_fields;% } hwrpb_vapamap$r_pa_overlay;N/********************* */N/* Page Count of Entry */N/********************* */ __union {5 unsigned __int64 hwrpb_vapamap$iq_page_count; __struct {7  unsigned int hwrpb_vapamap$il_page_count_l;7 unsigned int hwrpb_vapamap$il_page_count_h;0 } hwrpb_vapamap$r_page_count_fields;- } hwrpb_vapamap$r_page_count_overlay; } VAPAMAP; #if !defined(__VAXC)J#define hwrpb_vapamap$iq_va hwrpb_vapamap$r_va_overlay.hwrpb_vapamap$iq_vah#define hwrpb_vapamap$il_va_l hwrpb_vapamap$r_va_overlay.hwrpb_vapamap$r_va_fields.hwrpb_vapamap$il_va_lh#define hwrpb_vapamap$il_va_h hwrpb_vapamap$r_va_overlay.hwrpb_vapamap$r_va_fields.hwrpb_vapamap$il_va_hJ#define hwrpb_vapamap$iq_pa hwrpb_vapamap$r_pa_overlay.hwrpb_vapamap$iq_pah#define hwrpb_vapamap$il_pa_l hwrpb_vapamap$r_pa_overlay.hwrpb_vapamap$r_pa_fields.hwrpb_vapamap$il_pa_lh#define hwrpb_vapamap$il_pa_h hwrpb_vapamap$r_pa_overlay.hwrpb_vapamap$r_pa_fields.hwrpb_vapamap$il_pa_hb#define hwrpb_vapamap$iq_page_count hwrpb_vapamap$r_page_count_overlay.hwrpb_vapamap$iq_page_count#define hwrpb_vapamap$il_page_count_l hwrpb_vapamap$r_page_count_overlay.hwrpb_vap amap$r_page_count_fields.hwrpb_vapamap$il_page_co\unt_l#define hwrpb_vapamap$il_page_count_h hwrpb_vapamap$r_page_count_overlay.hwrpb_vapamap$r_page_count_fields.hwrpb_vapamap$il_page_co\unt_h"#endif /* #if !defined(__VAXC) */ N#define HWRPB_VAPAMAP$S_VAPAMAPDEF 24 /* Old size name synonym */N/********************** */N/* Boot Path Descriptor */N/**********************  */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _bootdev {N/*********************** */N/* Size of Bootpath Desc */N/***********************  */#pragma __nomember_alignment __union {/ unsigned __int64 hwrpb_bootdev$iq_size; __struct {1 unsigned int hwrpb_bootdev$il_size_l;1 unsigned int hwrpb_bootdev$il_size_h;* } hwrpb_bootdev$r_size_fields;' } hwrpb_bootdev$r_size_overlay;N/****************************** */N/* Boot Device Path Binary Data */N/************************* ***** */ __union {6 unsigned __int64 hwrpb_bootdev$iq_device_path; __struct {8 unsigned int hwrpb_bootdev$il_device_path_l;8 unsigned int hwrpb_bootdev$il_device_path_h;1 } hwrpb_bootdev$r_device_path_fields;- } hwrpb_bootdev$r_device_path_overla; } BOOTDEV; #if !defined(__VAXC)P#define hwrpb_bootdev$iq_size hwrpb_bootdev$r_size_overlay.hwrpb_bootdev$iq_sizep#define hwrpb_bootdev$il_size_l hwrpb_bootdev$r_size_overlay.hwrpb_bootdev$r_size_fields.hwrpb_bootdev$il_size_lp#define hwrpb_bootdev$il_size_h hwrpb_bootdev$r_size_overlay.hwrpb_bootdev$r_size_fields.hwrpb_bootdev$il_size_hd#define hwrpb_bootdev$iq_device_path hwrpb_bootdev$r_device_path_overla.hwrpb_bootdev$iq_device_path#define hwrpb_bootdev$il_device_path_l hwrpb_bootdev$r_device_path_overla.hwrpb_bootdev$r_device_path_fields.hwrpb_bootdev$il_devic\e_path_l#define hwrpb_bootdev$il_device_path_h hwrpb_bootd ev$r_device_path_overla.hwrpb_bootdev$r_device_path_fields.hwrpb_bootdev$il_devic\e_path_h"#endif /* #if !defined(__VAXC) */ N#define HWRPB_BOOTDEV$S_BOOTDEVDEF 16 /* Old size name synonym */N/* (GARY - VALIDATE OR ELIMINATE THESE) */N/* Console terminal routines */N#define HWRPB_CRB$K_GETC 1 /* Get a character from console */N#define HWRPB_CRB$K_PUTS 2 /* Put a string to console term */N#define HWRPB_CRB$K_RESET_TERM 3 /* Reset console terminal */N#define HWRPB_CRB$K_SET_TERM_INTR 4 /* Set console terminal int. */N#define HWRPB_CRB$K_SET_TERM_CTL 5 /* Set console terminal controls */N#define HWRPB_CRB$K_PROCESS_KEYCODE 6 /* Process and translate keycode */N#define HWRPB_CRB$K_CONSOLE_OPEN 7 /* Open console for I/O */N#define HWRPB_CRB$K_CONSOLE_CLOSE 8 /* Close console for I/O */N/* (GARY - VALIDATE OR ELIMINATE THESE) */N/* Console Generic IO routines */N#define HWRPB_CRB$K_OPEN 16 /* Open access to I/O device */N#define HWRPB_CRB$K_CLOSE 17 /* Close access to I/O device */#define HWRPB_CRB$K_IOCTL 18N#define HWRPB_CRB$K_READ 19 /* Perform read operation */N#define HWRPB_CRB$K_WRITE 20 /* Perform write operation  */N/* (GARY - VALIDATE OR ELIMINATE THESE) */N/* Console Env. Variable Routines */N#define HWRPB_CRB$K_SET_ENV 32 /* Set an environment varible */N#define HWRPB_CRB$K_RESET_ENV 33 /* Reset an environment variable */N#define HWRPB_CRB$K_GET_ENV 34 /* Fetch an environment varible */N#define HWRPB_CRB$K_SAVE_ENV 35 /* Save an environment varible */N/* (GARY - VALIDATE  OR ELIMINATE THESE) */N/* Write/Read FRU EEROM routines */"#define HWRPB_CRB$K_WRITE_EEROM 51!#define HWRPB_CRB$K_READ_EEROM 52(#define HWRPB_CRB$K_NEW_CPU_OWNERSHIP 53*#define HWRPB_CRB$K_RELEASE_TO_FIRMWARE 54*#define HWRPB_CRB$K_GET_HW_ERROR_RECORD 55N/* (GARY - VALIDATE OR ELIMINATE THESE) */N/* Required Environment Variables */!#define HWRPB_CRB$K_AUTO_ACTION 1#define HWRPB_CRB$K_BOOT_DEV 2!#define HWRPB_CRB$K_BOOTCMD_DEV 3 #define HWRPB_CRB$K_BOOTED_DEV 4#define HWRPB_CRB$K_BOOT_FILE 5!#define HWRPB_CRB$K_BOOTED_FILE 6"#define HWRPB_CRB$K_BOOT_OSFLAGS 7$#define HWRPB_CRB$K_BOOTED_OSFLAGS 8 #define HWRPB_CRB$K_BOOT_RESET 9#define HWRPB_CRB$K_DUMP_DEV 10##define HWRPB_CRB$K_ENABLE_AUDIT 11#define HWRPB_CRB$K_LICENSE 12#define HWRPB_CRB$K_CHAR_SET 13#define HWRPB_CRB$K_LANGUAGE 14#define HWRPB_CRB$K_TT Y_DEV 15N/* (GARY - VALIDATE OR ELIMINATE THESE) */#define HWRPB_CRB$K_PSWITCH 48%#define HWRPB_CRB$K_SAVE_ERROR_LOG 49#define HWRPB_CRB$K_HALT_CPU 50N/* (GARY - VALIDATE OR ELIMINATE THESE) */ #define HWRPB_CRB$K_PARTITION 40#define HWRPB_CRB$K_GALAXY 40&#define HWRPB_CRB$K_BOOT_DUMPKERNEL 41N/************************************************** */N/* Itanium min-state save structure - zero r elative */N/* TODO - Create the X86 variant */N/************************************************** */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mcamin {#pragma __nomember_alignmentN unsigned __int64 mcamin$iq_saved_gr_nats; /* NaT bits for saved GRs */N/****************** */N/* Static registers */N/****************** */N unsigned __int64 mcamin$iq_gr1; /* General register 1 */N unsigned __int64 mcamin$iq_gr2; /* General register 2 */N unsigned __int64 mcamin$iq_gr3; /* General register 3 */N unsigned __int64 mcamin$iq_gr4; /* General register 4 */N unsigned __int64 mcamin$iq_gr5; /* General register 5 */N unsigned __int64 mcamin$iq_gr6; /* General register 6 */N unsigned __int64 mcamin$iq_gr7; /* General register 7 */N unsigned __int64 mcamin$iq_gr8; /* General register 8 */N unsigned __int64 mcamin$iq_gr9; /* General register 9 */N unsigned __int64 mcamin$iq_gr10; /* General register 10 */N unsigned __int64 mcamin$iq_gr11; /* General register 11 */N unsigned __int64 mcamin$iq_gr12; /* General register 12 */N unsigned __int64 mcamin$iq_gr13; /* General register 13 */N unsigned __int64 mcamin$iq_gr14; /* General register 14 */N unsigned __int64 mcamin$iq_gr15; /* General register 15 */N/******************  */N/* Bank 0 registers */N/****************** */N unsigned __int64 mcamin$iq_bank0_gr16; /* Bank 0 register 16 */N unsigned __int64 mcamin$iq_bank0_gr17; /* Bank 0 register 17 */N unsigned __int64 mcamin$iq_bank0_gr18; /* Bank 0 register 18 */N unsigned __int64 mcamin$iq_bank0_gr19; /* Bank 0 register 19 */N unsigned __int64 mcamin$iq_bank0_gr20; /* Bank 0 register 20 */N unsigned __int64 mcamin$iq_bank0_gr21; /* Bank 0 register 21 */N unsigned __int64 mcamin$iq_bank0_gr22; /* Bank 0 register 22 */N unsigned __int64 mcamin$iq_bank0_gr23; /* Bank 0 register 23 */N unsigned __int64 mcamin$iq_bank0_gr24; /* Bank 0 register 24 */N unsigned __int64 mcamin$iq_bank0_gr25; /* Bank 0 register 25 */N unsigned __int64 mcamin$iq_bank0_gr26; /* Bank 0 register 26 */N unsigned __int64 mcamin$iq_bank0_gr27; /* Bank 0 register 27 */N unsigned __int64 mcamin$iq_bank0_gr28; /* Bank 0 register 28 */N unsigned __int64 mcamin$iq_bank0_gr29; /* Bank 0 register 29 */N unsigned __int64 mcamin$iq_bank0_gr30; /* Bank 0 register 30 */N unsigned __int64 mcamin$iq_bank0_gr31; /* Bank 0 register 31 */N/******************  */N/* Bank 1 registers */N/****************** */N unsigned __int64 mcamin$iq_bank1_gr16; /* Bank 1 register 16 */N unsigned __int64 mcamin$iq_bank1_gr17; /* Bank 1 register 17 */N unsigned __int64 mcamin$iq_bank1_gr18; /* Bank 1 register 18 */N unsigned __int64 mcamin$iq_bank1_gr19; /* Bank 1 register 19 */N  unsigned __int64 mcamin$iq_bank1_gr20; /* Bank 1 register 20 */N unsigned __int64 mcamin$iq_bank1_gr21; /* Bank 1 register 21 */N unsigned __int64 mcamin$iq_bank1_gr22; /* Bank 1 register 22 */N unsigned __int64 mcamin$iq_bank1_gr23; /* Bank 1 register 23 */N unsigned __int64 mcamin$iq_bank1_gr24; /* Bank 1 register 24 */N unsigned __int64 mcamin$iq_bank1_gr25; /* Bank 1 register 25 */N unsigned __int64 mcamin$iq_bank1_gr26; /* Bank 1 register 26 */N unsigned __int64 mcamin$iq_bank1_gr27; /* Bank 1 register 27 */N unsigned __int64 mcamin$iq_bank1_gr28; /* Bank 1 register 28 */N unsigned __int64 mcamin$iq_bank1_gr29; /* Bank 1 register 29 */N unsigned __int64 mcamin$iq_bank1_gr30; /* Bank 1 register 30 */N unsigned __int64 mcamin$iq_bank1_gr31; /* Bank 1 register 31 */N/***************************  */N/* Saved predicate registers */N/*************************** */N unsigned __int64 mcamin$iq_saved_prs; /* Predicate registers */N/***************** */N/* State registers */N/***************** */N unsigned __int64 mcamin$iq_br0; /* BR0 */N unsigned __int64 mcamin$iq_rsc; /* RSC */N unsigned __int64 mcamin$iq_iip; /* IIP */N unsigned __int64 mcamin$iq_ipsr; /* IPSR */N unsigned __int64 mcamin$iq_ifs; /* IFS */N/****************************** */N/* Possibly undefined registers */N/****************************** */N unsigned __int64 mcamin$iq_xip; /* XIP or undefined */N unsigned __int64 mcamin$iq_xpsr; /* XPSR or undefined */N unsigned __int64 mcamin$iq_xfs; /* XFS or undefined */ } MCAMIN;N/* MCA Constants: */N#define MCAMIN$K_LENGTH 456  /* Full length of MCAMIN$ */N/********************************************* */N/* Itanium machine check interrupt state block */N/* TODO - Create the X86 variant */N/********************************************* */&#define MCAINT$M_HALTED_IN_CONSOLE 0x1"#define MCAINT$M_CONTEXT_VALID 0x2#define MCAINT$M_NO_DATA 0x4 c#if !defined(__NOBASEALIGN_SUPPO RT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mcaint {#pragma __nomember_alignment __union {N unsigned __int64 mcaint$iq_flags; /* Flags bitmask */ __struct {Y unsigned mcaint$v_halted_in_console : 1; /* CPU is not running OS software */] unsigned mcaint$v_context_valid : 1; /* Valid data has been dumped int o buffer */[ unsigned mcaint$v_no_data : 1; /* Hardware returned no information in buffer */* unsigned mcaint$v_fill_1_ : 5;, } mcaint$r_flags_fields_overlay;! } mcaint$r_flags_overlay;[ unsigned __int64 mcaint$iq_cpu_id; /* Zero-relative CPU ID of interrupted processor */N unsigned __int64 mcaint$iq_int_type; /* Interrupt type code */O unsigned __int64 mcaint$iq_handler_gp; /* Physical GP of current handler */Y unsigned __int64 mcaint$iq_handler_ret; /* Physical PC of handler procedure return */Q unsigned __int64 mcaint$iq_handler_ksp; /* Physical KSP of console handler */Q unsigned __int64 mcaint$iq_handler_bsp; /* Physical BSP of console handler */j unsigned __int64 mcaint$iq_minstate_save_area; /* Physical address of interrupt min-state save area */b unsigned __int64 mcaint$iq_saved_context; /* Physical address of saved hardware state block */c unsigned __int64 mcaint$iq_processor_state_param; /* Itanium processor state parameter value */N unsigned __int64 mcaint$iq_state_info; /* Interrupt-specific state */U unsigned __int64 mcaint$iq_pal_proc_entry; /* Physical PC of PAL routine entry */U unsigned __int64 mcaint$iq_sal_proc_entry; /* Physical PC of SAL routine entry */N unsigned __int64 mcaint$iq_sal_gp; /* Physical GP of SAL routines */T unsigned __int64 mcaint$iq_sal_return; /* Physical PC of SAL return procedure */Y unsigned __int64 mcaint$iq_handl er_rnat; /* RNAT of console handler register stack */U unsigned __int64 mcaint$iq_handler_xfr_bsp; /* Physical BSP of console handler */N unsigned __int64 mcaint$iq_handler_rsvd1; /* Reserved cell */N unsigned __int64 mcaint$iq_handler_rsvd2; /* Reserved cell */N unsigned __int64 mcaint$iq_handler_rsvd3; /* Reserved cell */ } MCAINT; #if !defined(__VAXC)>#define mcaint$iq_flags mcaint$r_flags_overlay.mcaint$iq_flagsr#define mcaint$v_halted_in_console mcaint$r_flags_overlay.mcaint$r_flags_fields_overlay.mcaint$v_halted_in_consolej#define mcaint$v_context_valid mcaint$r_flags_overlay.mcaint$r_flags_fields_overlay.mcaint$v_context_valid^#define mcaint$v_no_data mcaint$r_flags_overlay.mcaint$r_flags_fields_overlay.mcaint$v_no_data"#endif /* #if !defined(__VAXC) */ N/* MCAINT Constants: */N#define MCAINT$K_LENGTH 160 /* Full length of MCAINT$ */N/* ************************************************************************* */N/* Itanium machine check saved context structure not in minstate save array */N/* TODO - Create the X86 variant */N/************************************************************************** */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#e ndiftypedef struct _mcasav {#pragma __nomember_alignmentN unsigned __int64 mcasav$iq_bsp; /* Interrupted BSP pointer */N unsigned __int64 mcasav$iq_bspstore; /* Interrupted BSPSTORE pointer */N unsigned __int64 mcasav$iq_rnat; /* Interrupted RNAT value */N unsigned __int64 mcasav$iq_unat; /* Interrupted UNAT value */N unsigned __int64 mcasav$iq_pfs; /* Interrupted PFS value */N unsigned __int64 mcasav$iq_fpsr; /* Interrupted FPSR value */N unsigned __int64 mcasav$iq_isr; /* Interrupted ISR value */N unsigned __int64 mcasav$iq_ifa; /* Interrupted IFA value */N unsigned __int64 mcasav$iq_itir; /* Interrupted ITIR value */N unsigned __int64 mcasav$iq_iipa; /* Interrupted IIPA value */N unsigned __int64 mcasav$iq_iim; /* Interrupted IIM value */N unsigned __int64 mcasav$iq_iha; /* Interrupted IHA value  */N unsigned __int64 mcasav$iq_ccv; /* Interrupted CCV value */N unsigned __int64 mcasav$iq_dcr; /* Interrupted DCR value */N unsigned __int64 mcasav$iq_lc; /* Interrupted LC value */N unsigned __int64 mcasav$iq_ec; /* Interrupted EC value */N unsigned __int64 mcasav$iq_br1; /* Interrupted BR1 value */N unsigned __int64 mcasav$iq_br2; /* Interrupted BR2 value */N unsigned __int64 mcasav$iq_br3; /* Interrupted BR3 value */N unsigned __int64 mcasav$iq_br4; /* Interrupted BR4 value */N unsigned __int64 mcasav$iq_br5; /* Interrupted BR5 value */N unsigned __int64 mcasav$iq_br6; /* Interrupted BR6 value */N unsigned __int64 mcasav$iq_br7; /* Interrupted BR7 value */N char mcasav$t_align1 [8]; /* Assure 32 byte alignment */N unsigned __int64 mcasav$q_f2 [2]; /* F2 */N unsigned __int64 mcasav$q_f3 [2]; /* F3 */N unsigned __int64 mcasav$q_f4 [2]; /* F4 */N unsigned __int64 mcasav$q_f5 [2]; /* F5 */N unsigned __int64 mcasav$q_f6 [2]; /* F6 */N unsigned __int64 mcasav$q_f7 [2]; /* F7 */N unsigned __int64 mcasav$q_f8 [2]; /* F8  */N unsigned __int64 mcasav$q_f9 [2]; /* F9 */N unsigned __int64 mcasav$q_f10 [2]; /* F10 */N unsigned __int64 mcasav$q_f11 [2]; /* F11 */N unsigned __int64 mcasav$q_f12 [2]; /* F12 */N unsigned __int64 mcasav$q_f13 [2]; /* F13 */N unsigned __int64 mcasav$q_f14 [2]; /* F14 */N unsigned __int64 mcasav$q_f15 [2]; /* F15 */N unsigned __int64 mcasav$q_f16 [2]; /* F16 */N unsigned __int64 mcasav$q_f17 [2]; /* F17 */N unsigned __int64 mcasav$q_f18 [2]; /* F18 */N unsigned __int64 mcasav$q_f19 [2]; /* F19 */N unsigned __int64 mcasav$q_f20 [2]; /* F20 */N unsigned __int64 mcasav$q_f21 [2]; /* F21 */N unsigned __int64 mcasav$q_f22 [2]; /* F22 */N unsigned __int64 mcasav$q_f23 [2]; /* F23 */N unsigned __int64 mcasav$q_f24 [2]; /* F24 */N unsigned __int64 mcasav$q_f25 [2]; /* F25 */N unsigned __int64 mcasav$q_f26 [2]; /* F26 */N unsigned __int64 mcasav$q_f27 [2]; /* F27  */N unsigned __int64 mcasav$q_f28 [2]; /* F28 */N unsigned __int64 mcasav$q_f29 [2]; /* F29 */N unsigned __int64 mcasav$q_f30 [2]; /* F30 */N unsigned __int64 mcasav$q_f31 [2]; /* F31 */N unsigned __int64 mcasav$q_f32 [2]; /* F32 */N unsigned __int64 mcasav$q_f33 [2]; /* F33 */N unsigned __int64 mcasav$q_f34 [2]; /* F34 */N unsigned __int64 mcasav$q_f35 [2]; /* F35 */N unsigned __int64 mcasav$q_f36 [2]; /* F36 */N unsigned __int64 mcasav$q_f37 [2]; /* F37 */N unsigned __int64 mcasav$q_f38 [2]; /* F38 */N unsigned __int64 mcasav$q_f39 [2]; /* F39 */N unsigned __int64 mcasav$q_f40 [2]; /* F40 */N unsigned __int64 mcasav$q_f41 [2]; /* F41 */N unsigned __int64 mcasav$q_f42 [2]; /* F42 */N unsigned __int64 mcasav$q_f43 [2]; /* F43 */N unsigned __int64 mcasav$q_f44 [2]; /* F44 */N unsigned __int64 mcasav$q_f45 [2]; /* F45 */N unsigned __int64 mcasav$q_f46 [2]; /* F46  */N unsigned __int64 mcasav$q_f47 [2]; /* F47 */N unsigned __int64 mcasav$q_f48 [2]; /* F48 */N unsigned __int64 mcasav$q_f49 [2]; /* F49 */N unsigned __int64 mcasav$q_f50 [2]; /* F50 */N unsigned __int64 mcasav$q_f51 [2]; /* F51 */N unsigned __int64 mcasav$q_f52 [2]; /* F52 */N unsigned __int64 mcasav$q_f53 [2]; /* F53 */N unsigned __int64 mcasav$q_f54 [2]; /* F54 */N unsigned __int64 mcasav$q_f55 [2]; /* F55 */N unsigned __int64 mcasav$q_f56 [2]; /* F56 */N unsigned __int64 mcasav$q_f57 [2]; /* F57 */N unsigned __int64 mcasav$q_f58 [2]; /* F58 */N unsigned __int64 mcasav$q_f59 [2]; /* F59 */N unsigned __int64 mcasav$q_f60 [2]; /* F60 */N unsigned __int64 mcasav$q_f61 [2]; /* F61 */N unsigned __int64 mcasav$q_f62 [2]; /* F62 */N unsigned __int64 mcasav$q_f63 [2]; /* F63 */N unsigned __int64 mcasav$q_f64 [2]; /* F64 */N unsigned __int64 mcasav$q_f65 [2]; /* F65  */N unsigned __int64 mcasav$q_f66 [2]; /* F66 */N unsigned __int64 mcasav$q_f67 [2]; /* F67 */N unsigned __int64 mcasav$q_f68 [2]; /* F68 */N unsigned __int64 mcasav$q_f69 [2]; /* F69 */N unsigned __int64 mcasav$q_f70 [2]; /* F70 */N unsigned __int64 mcasav$q_f71 [2]; /* F71 */N unsigned __int64 mcasav$q_f72 [2]; /* F72 */N unsigned __int64 mcasav$q_f73 [2]; /* F73 */N unsigned __int64 mcasav$q_f74 [2]; /* F74 */N unsigned __int64 mcasav$q_f75 [2]; /* F75 */N unsigned __int64 mcasav$q_f76 [2]; /* F76 */N unsigned __int64 mcasav$q_f77 [2]; /* F77 */N unsigned __int64 mcasav$q_f78 [2]; /* F78 */N unsigned __int64 mcasav$q_f79 [2]; /* F79 */N unsigned __int64 mcasav$q_f80 [2]; /* F80 */N unsigned __int64 mcasav$q_f81 [2]; /* F81 */N unsigned __int64 mcasav$q_f82 [2]; /* F82 */N unsigned __int64 mcasav$q_f83 [2]; /* F83 */N unsigned __int64 mcasav$q_f84 [2]; /* F84  */N unsigned __int64 mcasav$q_f85 [2]; /* F85 */N unsigned __int64 mcasav$q_f86 [2]; /* F86 */N unsigned __int64 mcasav$q_f87 [2]; /* F87 */N unsigned __int64 mcasav$q_f88 [2]; /* F88 */N unsigned __int64 mcasav$q_f89 [2]; /* F89 */N unsigned __int64 mcasav$q_f90 [2]; /* F90 */N unsigned __int64 mcasav$q_f91 [2]; /* F91 */N unsigned __int64 mcasav$q_f92 [2]; /* F92 */N unsigned __int64 mcasav$q_f93 [2]; /* F93 */N unsigned __int64 mcasav$q_f94 [2]; /* F94 */N unsigned __int64 mcasav$q_f95 [2]; /* F95 */N unsigned __int64 mcasav$q_f96 [2]; /* F96 */N unsigned __int64 mcasav$q_f97 [2]; /* F97 */N unsigned __int64 mcasav$q_f98 [2]; /* F98 */N unsigned __int64 mcasav$q_f99 [2]; /* F99 */N unsigned __int64 mcasav$q_f100 [2]; /* F100 */N unsigned __int64 mcasav$q_f101 [2]; /* F101 */N unsigned __int64 mcasav$q_f102 [2]; /* F102 */N unsigned __int64 mcasav$q_f103 [2]; /* F103  */N unsigned __int64 mcasav$q_f104 [2]; /* F104 */N unsigned __int64 mcasav$q_f105 [2]; /* F105 */N unsigned __int64 mcasav$q_f106 [2]; /* F106 */N unsigned __int64 mcasav$q_f107 [2]; /* F107 */N unsigned __int64 mcasav$q_f108 [2]; /* F108 */N unsigned __int64 mcasav$q_f109 [2]; /* F109 */N unsigned __int64 mcasav$q_f110 [2]; /* F110 */N unsigned __int64 mcasav$q_f111 [2]; /* F111 */N unsigned __int64 mcasav$q_f112 [2]; /* F112 */N unsigned __int64 mcasav$q_f113 [2]; /* F113 */N unsigned __int64 mcasav$q_f114 [2]; /* F114 */N unsigned __int64 mcasav$q_f115 [2]; /* F115 */N unsigned __int64 mcasav$q_f116 [2]; /* F116 */N unsigned __int64 mcasav$q_f117 [2]; /* F117 */N unsigned __int64 mcasav$q_f118 [2]; /* F118 */N unsigned __int64 mcasav$q_f119 [2]; /* F119 */N unsigned __int64 mcasav$q_f120 [2]; /* F120 */N unsigned __int64 mcasav$q_f121 [2]; /* F121 */N unsigned __int64 mcasav$q_f122 [2]; /* F122  */N unsigned __int64 mcasav$q_f123 [2]; /* F123 */N unsigned __int64 mcasav$q_f124 [2]; /* F124 */N unsigned __int64 mcasav$q_f125 [2]; /* F125 */N unsigned __int64 mcasav$q_f126 [2]; /* F126 */N unsigned __int64 mcasav$q_f127 [2]; /* F127 */ } MCASAV;N/* MCASAV Constants:  */N#define MCASAV$K_LENGTH 2208 /* Full length of MCASAV$ */N/************************************************* */N/* Itanium machine check interrupt state type code */N/* TODO - Create the X86 variant */N/************************************************* */N/* Hardware interrupt type codes */N#define HWIN T$K_PROCESSOR_START 1 /* CPU coming out of console mode */N#define HWINT$K_INIT 2 /* INIT interrupt */N#define HWINT$K_MCA 3 /* Machine Check Abort interrupt */O#define HWINT$K_CMC 4 /* Corrected Machine Check interrupt */P#define HWINT$K_CPE 5 /* Corrected Platform Error interrupt */ &#pragma __required_pointer_size __save&#pragma __required_pointer_size __longtypedef HWRPB * HWRPB_PQ;'#pragma __required_pointer_size __shorttypedef HWRPB * HWRPB_PL;)#pragma __required_pointer_size __restoreN/********** END OF X86_64 SECTION ************************************** */N/*IA64 */N/********** END IA64 SECTION ******************************************** */N/********** ALPHA SECTION *********************************************** */N/*** Alpha *** End Section ***  */N/********** END ALPHA SECTION ************************************** */  #ifdef EFI64#pragma pack(pop,hwrpbdef)#endif $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HWRPBDEF_LOADED */ wwp9[UM/*******DHD4DEF~HM1DEFHM2DEFHPCDEFzHPETDEF>HQBDEFMzHRBDEFdHULBDEFoHWPRTDEF~HWRPBDEFHWSCBDEF8IA64_ASM********************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc.  **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */H/* Source: 02-MAY-2002 09:33:44 $1$DGA8345:[LIB_H.SRC]HWSCBDEF.SDL;1 *//******************************************************* *************************************************************************//*** MODULE $HWSCBDEF ***/#ifndef __HWSCBDEF_LOADED#define __HWSCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#end if N/* */N/* System Control Block Entry Definitions. The system control block (SCB) */N/* specifies the entry points for exception and interrupt service routines. */Q/* The first quadword is the virtual address of the service routine associated */R/* with that entry. The second quadword is an arbitrary parameter to be passed */N/* to the service routine. The parameter for EVMS for most exceptions and */Q/* interrupts is the virtual address of the procedure descrtor for the service */N/* routine. */N/* */ N#define HWSCB$K_VECTOR 0 /* Entry point address */N#define HWSCB$K_PARAMETER 8 /* Arbitrary parameter */N#define HWSCB$Q_UNUSED_00 0 /* %X00 Unused vector */N#define HWSCB$Q_FLOAT_FAULT 16 /* %X10 Floating disabled fault */N#define HWSCB$Q_UNUSED_20 32 /* %X20 Unused vector */N#define HWSCB$Q_UNUSED_30 48 /* %X30 Unused vector */N#define HWSCB$Q_UNUSED_40 64 /* %X40 Unused vector */N#define HWSCB$Q_UNUSED_50 80 /* %X50 Unused vector */N#define HWSCB$Q_UNUSED_60 96 /* %X60 Unused vector */N#define HWSCB$Q_UNUSED_70 112 /* %X70 Unused vector */Q#define HWSCB$Q_ACCVIO 128 /* %X80 Access control violation fault */N#define HWSCB$Q_TRANSLATION_FAULT 144 /* %X90 Translation not valid fault */N#define HWSCB$Q_READ_FAULT 160 /* %XA0 Fault on read fault */N#define HWSCB$Q_WRITE_FAULT 176 /* %XB0 Fault on write fault */N#define HWSCB$Q_EXECUTE_FAULT 192 /* %XC0 Fault on execute fault */N#define HWSCB$Q_ARITHMETIC_TRAP 512 /* %X200 Arithmetic trap */N#define HWSCB$Q_KERNEL_AST 576 /* %X240 Kernel mode AST */N#define HWSCB$Q_EXEC_AST 592 /* %X250 Exec mode AST */N#define HWSCB$Q_SUPER_AST 608 /* %X260 Super mode AST */N#define HWSCB$Q_USER_AST 624 /* %X270 User mode AST */N#define HWSCB$Q_REPORT_ALIGN_FAULT 640 /* %X280 Report alignment fault */N#define HWSCB$Q_UNUSED_290 656 /* %X290 Unused vector */N#define HWSCB$Q_UNUSED_2A0 672 /* %X2A0 Unused vector */N#define HWSCB$Q_UNUSED_2B0 688 /* %X2B0 Unused vector */N#define HWSCB$Q_UNUSED_2C0 704 /* %X2C0 Unused vector */N#define HWSCB$Q_UNUSED_2D0 720 /* %X2D0 Unused vector */N#define HWSCB$Q_UNUSED_2E0 736 /* %X2E0 Unused vector */N#define HWSCB$Q_UNUSED_2F0 752 /* %X2F0 Unused vector */N#define HWSCB$Q_LOAD_F_FLOAT 768 /* %X300 Load F floating */N#define HWSCB$Q_LOAD_D_FLOAT 784 /* %X310 Load D floating */N#define HWSCB$Q_LOAD_S_FLOAT 800 /* %X320 Load S floating */N#define HWSCB$Q_LOAD_T_FLOAT 816 /* %X330 Load T floating */N#define HWSCB$Q_STORE_F_FLOAT 832 /* %X340 Store F floating */N#define HWSCB$Q_STORE_D_FLOAT 848 /* %X350 Store D floating */N#define HWSCB$Q_STORE_S_FLOAT 864 /* %X360 Store S floating  */N#define HWSCB$Q_STORE_T_FLOAT 880 /* %X370 Store T floating */O#define HWSCB$Q_LOAD_SEXT_LONG 896 /* %X380 Load sign-extended longword */N#define HWSCB$Q_LOAD_QUAD 912 /* %X390 Load quadword */V#define HWSCB$Q_LOAD_SEXT_LONG_L 928 /* %X3A0 Load sign-extended longword locked */N#define HWSCB$Q_LOAD_QUAD_L 944 /* %X3B0 Load quadword locked */N#define HWSCB$Q_STORE_LONG 960 /* %X3C0 Store longword */N#define HWSCB$Q_STORE_QUAD 976 /* %X3D0 Store quadword */N#define HWSCB$Q_STORE_LONG_C 992 /* %X3E0 Store longword conditional */N#define HWSCB$Q_STORE_QUAD_C 1008 /* %X3F0 Store quadword conditional */N#define HWSCB$Q_BREAK_POINT 1024 /* %X400 Break point trap */N#define HWSCB$Q_BUG_CHECK 1040 /* %X410 Bug check trap */N#define HWSCB$Q_ILLEGAL_INSTRUCTION 1056 /* %X420 Illegal instruction trap */N#define HWSCB$Q_ILLEGAL_PAL_OPERAND 1072 /* %X430 Illegal call PAL operand */N#define HWSCB$Q_GENTRAP 1088 /* %X440 Software generated trap */N#define HWSCB$Q_UNUSED_450 1104 /* %X450 Unused vector */N#define HWSCB$Q_UNUSED_460 1120 /* %X460 Unused vector */N#define HWSCB$Q_UNUSED_470 1136 /* %X470 Unused vector */N#define HWSCB$Q_CHANGE_MODE_KERNEL 1152 /* %X480 Change mode to kernel */N#define HWSCB$Q_CHANGE_MODE_EXEC 1168 /* %X490 Change mode to exec */N#define HWSCB$Q_CHANGE_MODE_SUPER 1184 /* %X4A0 Change mode to super */N#define HWSCB$Q_CHANGE_MODE_USER 1200 /* %X4B0 Change mode to user */N#define HWSCB$Q_DIGITAL_1 1216 /* %X4C0 Reserved for Digital */N#define HWSCB$Q_DIGITAL_2 1232 /* %X4D0 Reserved for Digital */N#define HWSCB$Q_DIGITAL_3 1248 /* %X4E0 Reserved for Digital */N#define HWSCB$Q_DIGITAL_4 1264 /* %X4F0 Reserved for Digital */N#define HWSCB$Q_UNUSED_500 1280 /* %X500 Unused */N#define HWSCB$Q_SOFT_INTERRUPT_1 1296 /* %X510 Software level 1 interrupt */N#define HWSCB$Q_SOFT_INTERRUPT_2 1312 /* %x520 Software level 2 interrupt */N#define HWSCB$Q_SOFT_INTERRUPT_3 1328 /* %X530 Software level 3 interrupt */N#define HWSCB$Q_SOFT_INTERRUPT_4 1344 /* %X540 Software level 4 interrupt */N#define HWSCB$Q_SOFT_INTERRUPT_5 1360 /* %X550 Software level 5 interrupt */N#define HWSCB$Q_SOFT_INTERRUPT_6 1376 /* %X560 Software level 6 interrupt */N#define HWSCB$Q_SOFT_INTERRUPT_7 1392 /* %X570 Software level 7 interrupt */N#define HWSCB$Q_SOFT_INTERRUPT_8 1408 /* %X580 Software level 8 interrupt */N#define HWSCB$Q_SOFT_INTERRUPT_9 1424 /* %X590 Software level 9 interrupt */O#define HWSCB$Q_SOFT_INTERRUPT_10 1440 /* %X5A0 Software level 10 interrupt */O#define HWSCB$Q_SOFT_INTERRUPT_11 1456 /* %X5B0 Software level 11 interrupt */O#define HWSCB$Q_SOFT_INTERRUPT_12 1472 /* %X5C0 Software level 12 interrupt */O#define HWSCB$Q_SOFT_INTERRUPT_13 1488 /* %X5D0 Software level 13 interrupt */O#define HWSCB$Q_SOFT_INTERRUPT_14 1504 /* %X5E0 Software level 14 interrupt */O#define HWSCB$Q_SOFT_INTERRUPT_15 1520 /* %X5F0 Software level 15 interrupt */N#define HWSCB$Q_RESCHEDULE 1328 /* Reschedule interrupt */N#define HWSCB$Q_IO_POST 1344 /* I/O post interrupt */N#define HWSCB$Q_SW_TIMER_INTERRUPT 1392 /* Software timer interrupt  */N#define HWSCB$Q_IP_CONTROL 1472 /* IP control */N#define HWSCB$Q_XDELTA 1504 /* Xdelta */N#define HWSCB$Q_INTERVAL_CLOCK 1536 /* %X600 Interval clock interrupt */N#define HWSCB$Q_INTERPROCESSOR 1552 /* %X610 Interprocessor interrupt */X#define HWSCB$Q_SYSTEM_CORRECTED_ERROR 1568 /* %X620 System corrected error interrupt */\#define HWSCB$Q_PROCESS_CORRECTED_ERROR 1584 /* %X630 Processor corrected error interrupt */N#define HWSCB$Q_POWER_FAIL 1600 /* %X640 Power fail interrupt */T#define HWSCB$Q_PERF_MONITOR 1616 /* %X650 Reserved for performance monitor */P#define HWSCB$Q_SYSTEM_MACHINE_CHECK 1632 /* %X660 System machine check abort */V#define HWSCB$Q_PROCESSOR_MACHINE_CHECK 1648 /* %X670 Processor machine check abort */Q#define HWSCB$Q_SYSTEM_ENV_EVENT 1664 /* %X680 Environmental event interrupt */S#define HWSCB$Q_PROCESSOR_SPECIFIC_1 1680 /* %X690 Reserved - processor specific * /Z#define HWSCB$Q_SYSTEM_REC_ERROR 1696 /* %X6A0 System recoverable machine check abort */]#define HWSCB$Q_PROC_REC_ERROR 1712 /* %X6B0 Processer recoverable machine check abort */N#define HWSCB$Q_IO_INTERRUPT_BASE 2048 /* %X800 */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __HWSCBDEF_LOADED */ ww:[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */L/*  Source: 14-OCT-2004 11:06:01 $1$DGA8345:[LIB_H.SRC]IA64_MCHKDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IA64_MCHKDEF ***/#ifndef __IA64_MCHKDEF_LOADED#define __IA64_MCHKDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* SAL Record Header */N/* */N/* SAL 3.0 */V/* "Itanium Processor Family System Abstraction Layer Specification, November 2002" */N/* Section B.2.1, pp. B-2 */N/* */N/* (RHD - Record Header) */N/*-- */&#define SAL_RHD$M_OEM_SYS_ID_VALID 0x1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_rhd {#pragma __nomember_alignment& unsigned __int64 sal_rhd$q_rec_id; __union {) unsigned short int sal_rhd$w_rev; __struct {. unsigned char sal_rhd$b_minor_rev;. unsigned char sal_rhd$b_major_rev;# } sal_rhd$r_rev_fields; } sal_rhd$r_rev_overlay;) unsigned char sal_rhd$b_err_severity; __union  {& unsigned char sal_rhd$b_valid; __struct {4 unsigned sal_rhd$v_oem_sys_id_valid : 1;, unsigned sal_rhd$v_reserved : 7;% } sal_rhd$r_valid_fields;" } sal_rhd$r_valid_overlay;# unsigned int sal_rhd$l_rec_len; __union {- unsigned __int64 sal_rhd$q_timestamp; __struct {, unsigned char sal_rhd$b_seconds;, unsigned char sal_rhd$b_minutes;* unsigned char sal_rhd$b_hours;/  unsigned char sal_rhd$b_reserved_1;( unsigned char sal_rhd$b_day;* unsigned char sal_rhd$b_month;) unsigned char sal_rhd$b_year;, unsigned char sal_rhd$b_century;) } sal_rhd$r_timestamp_fields;& } sal_rhd$r_timestamp_overlay; __union {. unsigned int sal_rhd$o_oem_sys_id [4]; __struct {4 unsigned __int64 sal_rhd$q_oem_sys_id_l;4 unsigned __int64 sal_rhd$q_oem_sys_id_h;*  } sal_rhd$r_oem_sys_id_fields;' } sal_rhd$r_oem_sys_id_overlay; } SAL_RHD; #if !defined(__VAXC)9#define sal_rhd$w_rev sal_rhd$r_rev_overlay.sal_rhd$w_revZ#define sal_rhd$b_minor_rev sal_rhd$r_rev_overlay.sal_rhd$r_rev_fields.sal_rhd$b_minor_revZ#define sal_rhd$b_major_rev sal_rhd$r_rev_overlay.sal_rhd$r_rev_fields.sal_rhd$b_major_rev?#define sal_rhd$b_valid sal_rhd$r_valid_overlay.sal_rhd$b_validl#define sal_rhd$v_oem_sys_id_valid sal_rhd$r_valid_overlay.sal_rhd$r_valid_fields.sal_rhd$v_oem_sys_id_validK#define sal_rhd$q_timestamp sal_rhd$r_timestamp_overlay.sal_rhd$q_timestampb#define sal_rhd$b_seconds sal_rhd$r_timestamp_overlay.sal_rhd$r_timestamp_fields.sal_rhd$b_secondsb#define sal_rhd$b_minutes sal_rhd$r_timestamp_overlay.sal_rhd$r_timestamp_fields.sal_rhd$b_minutes^#define sal_rhd$b_hours sal_rhd$r_timestamp_overlay.sal_rhd$r_timestamp_fields.sal_rhd$b_hoursZ#define sal_rhd$b_day sal_rhd$r_timestamp_overlay.sal_rhd$r_timestamp_fields.sal_rhd$b_day^#define sal_rhd$b_month sal_rhd$r_timestamp_overlay.sal_rhd$r_timestamp_fields.sal_rhd$b_month\#define sal_rhd$b_year sal_rhd$r_timestamp_overlay.sal_rhd$r_timestamp_fields.sal_rhd$b_yearb#define sal_rhd$b_century sal_rhd$r_timestamp_overlay.sal_rhd$r_timestamp_fields.sal_rhd$b_centuryN#define sal_rhd$o_oem_sys_id sal_rhd$r_oem_sys_id_overlay.sal_rhd$o_oem_sys_idn#define sal_rhd$q_oem_sys_id_l sal_rhd$r_oem_sys_id_overlay.sal_rhd$r_oem_sys_id_fields.sal_rhd$q_oem_sys_id_ln#define sal_rhd$q_oem_sys_id _h sal_rhd$r_oem_sys_id_overlay.sal_rhd$r_oem_sys_id_fields.sal_rhd$q_oem_sys_id_h"#endif /* #if !defined(__VAXC) */ #define SAL_RHD$FRAME_SIZE 40N/*++ */N/* SAL GUID Structure */N/* */N/* SAL 3.0 */V/* "Itanium Processor Family System Abstraction Layer Specification, November 2002" */N/* Table B-1, pp. B-3 */N/* */N/* (GUID - Global Unique ID) */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_guid {#pragma __nomember_alignment __union {) unsigned int sal_guid$o_guid [4]; __struct {/ unsigned __int64 sal_guid$q_guid_l;/ unsigned __int64 sal_guid$q_guid_h;( } sal_guid$r_guid_lh_fields; __struct {/ unsigned int sal_guid$l_guid_data1;5 unsigned short int sal_guid$w_guid_data2;5 unsigned short int  sal_guid$w_guid_data3; __union {7 unsigned __int64 sal_guid$q_guid_data4; __struct {: unsigned char sal_guid$b_guid_data4_0;: unsigned char sal_guid$b_guid_data4_1;: unsigned char sal_guid$b_guid_data4_2;: unsigned char sal_guid$b_guid_data4_3;: unsigned char sal_guid$b_guid_data4_4;: unsigned char sal_guid$b_guid_data4_5;:  unsigned char sal_guid$b_guid_data4_6;: unsigned char sal_guid$b_guid_data4_7;3 } sal_guid$r_guid_data4_fields;0 } sal_guid$r_guid_data4_overlay;% } sal_guid$r_guid_fields;" } sal_guid$r_guid_overlay; } SAL_GUID; #if !defined(__VAXC)?#define sal_guid$o_guid sal_guid$r_guid_overlay.sal_guid$o_guid]#define sal_guid$q_guid_l sal_guid$r_guid_overlay.sal_guid$r_guid_lh_fields.sal_guid$q_guid_l]#define sal_guid$q_guid_h sal_guid$r_guid_overlay.sal_guid$r_guid_lh_fields.sal_guid$q_guid_hb#define sal_guid$l_guid_data1 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$l_guid_data1b#define sal_guid$w_guid_data2 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$w_guid_data2b#define sal_guid$w_guid_data3 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$w_guid_data3#define sal_guid$q_guid_data4 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$r_guid_data4_overlay.sal_guid$q_guid_data4#define sal_guid$b_guid_data4_0 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$r_guid_data4_overlay.sal_guid$r_guid_data4_\fields.sal_guid$b_guid_data4_0#define sal_guid$b_guid_data4_1 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$r_guid_data4_overlay.sal_guid$r_guid_data4_\fields.sal_guid$b_guid_data4_1#define sal_guid$b_guid_data4_2 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$r_guid_data4_overlay.sal_guid$r_guid_data4_\fields.sal_guid$b_guid_data4_2#define sal_guid$b_guid_data4_3 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$r_guid_data4_overlay.sal_guid$r_guid_data4_\fields.sal_guid$b_guid_data4_3#define sal_guid$b_guid_data4_4 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$r_guid_data4_overlay.sal_guid$r_guid_data4_\fields.sal_guid$b_guid_data4_4#define sal_guid$b_guid_data4_5 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$r_guid_data4_overlay.sal_guid$r_guid_data4_\fields.sal_guid$b_guid_data4_5#def ine sal_guid$b_guid_data4_6 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$r_guid_data4_overlay.sal_guid$r_guid_data4_\fields.sal_guid$b_guid_data4_6#define sal_guid$b_guid_data4_7 sal_guid$r_guid_overlay.sal_guid$r_guid_fields.sal_guid$r_guid_data4_overlay.sal_guid$r_guid_data4_\fields.sal_guid$b_guid_data4_7"#endif /* #if !defined(__VAXC) */ #define SAL_GUID$K_LENGTH 16N/*++ */N/* SAL Section Header  */N/* */N/* SAL 3.0 */V/* "Itanium Processor Family System Abstraction Layer Specification, November 2002" */N/* Section B.2.2, pp. B-2 - B-3 */N/* */N/* (SHD - Section Header)  */N/*-- */##define SAL_SHD$M_ERR_CORRECTED 0x1)#define SAL_SHD$M_CONTAINMENT_WARNING 0x2 #define SAL_SHD$M_MUST_RESET 0x4'#define SAL_SHD$M_ERR_THRESH_EXCEED 0x8'#define SAL_SHD$M_RESOURCE_UNAVAIL 0x10+#define SAL_SHD$M_REMAINING_BITS_VALID 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_shd {#pragma __nomember_alignment SAL_GUID sal_shd$r_guid; __union {) unsigned short int sal_shd$w_rev; __struct {. unsigned char sal_shd$b_minor_rev;. unsigned char sal_shd$b_major_rev;# } sal_shd$r_rev_fields; } sal_shd$r_rev_overlay; __union {- unsigned char sal_shd$b_err_recovery; __struct {1 unsigned sal_shd$v_err _corrected : 1;7 unsigned sal_shd$v_containment_warning : 1;. unsigned sal_shd$v_must_reset : 1;5 unsigned sal_shd$v_err_thresh_exceed : 1;4 unsigned sal_shd$v_resource_unavail : 1;, unsigned sal_shd$v_reserved : 2;8 unsigned sal_shd$v_remaining_bits_valid : 1;, } sal_shd$r_err_recovery_fields;) } sal_shd$r_err_recovery_overlay;' unsigned char sal_shd$b_reserved_1;' unsigned int sal_shd$l_section_l en; } SAL_SHD; #if !defined(__VAXC)9#define sal_shd$w_rev sal_shd$r_rev_overlay.sal_shd$w_revZ#define sal_shd$b_minor_rev sal_shd$r_rev_overlay.sal_shd$r_rev_fields.sal_shd$b_minor_revZ#define sal_shd$b_major_rev sal_shd$r_rev_overlay.sal_shd$r_rev_fields.sal_shd$b_major_revT#define sal_shd$b_err_recovery sal_shd$r_err_recovery_overlay.sal_shd$b_err_recoveryt#define sal_shd$v_err_corrected sal_shd$r_err_recovery_overlay.sal_shd$r_err_recovery_fields.sal_shd$v_err_corrected#define sa l_shd$v_containment_warning sal_shd$r_err_recovery_overlay.sal_shd$r_err_recovery_fields.sal_shd$v_containment_warningn#define sal_shd$v_must_reset sal_shd$r_err_recovery_overlay.sal_shd$r_err_recovery_fields.sal_shd$v_must_reset|#define sal_shd$v_err_thresh_exceed sal_shd$r_err_recovery_overlay.sal_shd$r_err_recovery_fields.sal_shd$v_err_thresh_exceedz#define sal_shd$v_resource_unavail sal_shd$r_err_recovery_overlay.sal_shd$r_err_recovery_fields.sal_shd$v_resource_unavail#define sal_shd$v_remain  ing_bits_valid sal_shd$r_err_recovery_overlay.sal_shd$r_err_recovery_fields.sal_shd$v_remaining_bits_valid"#endif /* #if !defined(__VAXC) */ #define SAL_SHD$FRAME_SIZE 24N/*++ */N/* SAL Processor Device Error Info Section - Header Structure */N/* */N/* SAL 3.0 */V/* "It anium Processor Family System Abstraction Layer Specification, November 2002" */N/* Section B.2.3, pp. B-4 - B-5 */N/* */N/* (PHD - Processor Header) */N/*-- */(#define SAL_PHD$M_PROC_ERR_MAP_VALID 0x1,#define SAL_PHD$M_PROC_STATE_PARAM_VALID 0x2'#define SAL_PHD$ M_PROC_CR_LID_VALID 0x4&#define SAL_PHD$M_PSI_STATIC_VALID 0x8,#define SAL_PHD$M_CPUID_INFO_VALID 0x1000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_phd {#pragma __nomember_alignment SAL_SHD sal_phd$r_sal_shd; __union {) unsigned __int64 sal_phd$q_valid; __struct {6 unsigned sal_phd  $v_proc_err_map_valid : 1;: unsigned sal_phd$v_proc_state_param_valid : 1;5 unsigned sal_phd$v_proc_cr_lid_valid : 1;4 unsigned sal_phd$v_psi_static_valid : 1;3 unsigned sal_phd$v_cache_check_num : 4;1 unsigned sal_phd$v_tlb_check_num : 4;1 unsigned sal_phd$v_bus_check_num : 4;6 unsigned sal_phd$v_reg_file_check_num : 4;0 unsigned sal_phd$v_ms_check_num : 4;4 unsigned sal_phd$v_cpuid_info_va  lid : 1;/ unsigned sal_phd$v_reserved_1 : 32;. unsigned sal_phd$v_reserved_2 : 7;% } sal_phd$r_valid_fields;" } sal_phd$r_valid_overlay;, unsigned __int64 sal_phd$q_proc_err_map;0 unsigned __int64 sal_phd$q_proc_state_param;+ unsigned __int64 sal_phd$q_proc_cr_lid; } SAL_PHD; #if !defined(__VAXC)?#define sal_phd$q_valid sal_phd$r_valid_overlay.sal_phd$q_validp#define sal_phd$v_proc_err_map_valid sal_phd$r_valid_overlay.sal_phd$r_v alid_fields.sal_phd$v_proc_err_map_validx#define sal_phd$v_proc_state_param_valid sal_phd$r_valid_overlay.sal_phd$r_valid_fields.sal_phd$v_proc_state_param_validn#define sal_phd$v_proc_cr_lid_valid sal_phd$r_valid_overlay.sal_phd$r_valid_fields.sal_phd$v_proc_cr_lid_validl#define sal_phd$v_psi_static_valid sal_phd$r_valid_overlay.sal_phd$r_valid_fields.sal_phd$v_psi_static_validj#define sal_phd$v_cache_check_num sal_phd$r_valid_overlay.sal_phd$r_valid_fields.sal_phd$v_cache_check_numf#define sal_ phd$v_tlb_check_num sal_phd$r_valid_overlay.sal_phd$r_valid_fields.sal_phd$v_tlb_check_numf#define sal_phd$v_bus_check_num sal_phd$r_valid_overlay.sal_phd$r_valid_fields.sal_phd$v_bus_check_nump#define sal_phd$v_reg_file_check_num sal_phd$r_valid_overlay.sal_phd$r_valid_fields.sal_phd$v_reg_file_check_numd#define sal_phd$v_ms_check_num sal_phd$r_valid_overlay.sal_phd$r_valid_fields.sal_phd$v_ms_check_numl#define sal_phd$v_cpuid_info_valid sal_phd$r_valid_overlay.sal_phd$r_valid_fields.sal_phd$v_cp uid_info_valid"#endif /* #if !defined(__VAXC) */ #define SAL_PHD$FRAME_SIZE 56N/*++ */N/* SAL Processor Device Error Info Section - ID Structure */N/* */N/* SAL 3.0 */V/* "Itanium Processor Family System Abstraction Layer Specification, November 2002" */N/* Section B.2.3, pp. B-5 */N/* */N/* (PIDS - Processor ID Structure) */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifty pedef struct _sal_pids {#pragma __nomember_alignment __union {. unsigned __int64 sal_pids$q_cpuid [5]; __struct {/ unsigned __int64 sal_pids$q_cpuid0;/ unsigned __int64 sal_pids$q_cpuid1;/ unsigned __int64 sal_pids$q_cpuid2;/ unsigned __int64 sal_pids$q_cpuid3;/ unsigned __int64 sal_pids$q_cpuid4;& } sal_pids$r_cpuid_fields;# } sal_pids$r_cpuid_overlay;+ unsigned __int64 sal_pids$q_rese rved_1; } SAL_PIDS; #if !defined(__VAXC)B#define sal_pids$q_cpuid sal_pids$r_cpuid_overlay.sal_pids$q_cpuid\#define sal_pids$q_cpuid0 sal_pids$r_cpuid_overlay.sal_pids$r_cpuid_fields.sal_pids$q_cpuid0\#define sal_pids$q_cpuid1 sal_pids$r_cpuid_overlay.sal_pids$r_cpuid_fields.sal_pids$q_cpuid1\#define sal_pids$q_cpuid2 sal_pids$r_cpuid_overlay.sal_pids$r_cpuid_fields.sal_pids$q_cpuid2\#define sal_pids$q_cpuid3 sal_pids$r_cpuid_overlay.sal_pids$r_cpuid_fields.sal_pids$q_cpuid3\#define sal_pids$q_cpuid4 sal_pids$r_cpuid_overlay.sal_pids$r_cpuid_fields.sal_pids$q_cpuid4"#endif /* #if !defined(__VAXC) */ #define SAL_PIDS$FRAME_SIZE 48N/*++ */N/* Min-State Save Area */N/* */N/* "Intel IA-64 Architecture Software Developer's Manual, July 2000" */N/* Section 11.3.2.3, Figure  11-11, pp. 11-19 */N/* */N/* (MSSAS - Min-State Save Area Structure) */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_ mssas {#pragma __nomember_alignment2 unsigned __int64 sal_mssas$q_nat_for_saved_gr;% unsigned __int64 sal_mssas$q_gr1;% unsigned __int64 sal_mssas$q_gr2;% unsigned __int64 sal_mssas$q_gr3;% unsigned __int64 sal_mssas$q_gr4;% unsigned __int64 sal_mssas$q_gr5;% unsigned __int64 sal_mssas$q_gr6;% unsigned __int64 sal_mssas$q_gr7;% unsigned __int64 sal_mssas$q_gr8;% unsigned __int64 sal_mssas$q_gr9;& unsigned __int64 sal_mssas$q_gr10;& unsigned _  _int64 sal_mssas$q_gr11;& unsigned __int64 sal_mssas$q_gr12;& unsigned __int64 sal_mssas$q_gr13;& unsigned __int64 sal_mssas$q_gr14;& unsigned __int64 sal_mssas$q_gr15;, unsigned __int64 sal_mssas$q_bank0_gr16;, unsigned __int64 sal_mssas$q_bank0_gr17;, unsigned __int64 sal_mssas$q_bank0_gr18;, unsigned __int64 sal_mssas$q_bank0_gr19;, unsigned __int64 sal_mssas$q_bank0_gr20;, unsigned __int64 sal_mssas$q_bank0_gr21;, unsigned __int64 sal_mssas$q_bank0_gr22;  , unsigned __int64 sal_mssas$q_bank0_gr23;, unsigned __int64 sal_mssas$q_bank0_gr24;, unsigned __int64 sal_mssas$q_bank0_gr25;, unsigned __int64 sal_mssas$q_bank0_gr26;, unsigned __int64 sal_mssas$q_bank0_gr27;, unsigned __int64 sal_mssas$q_bank0_gr28;, unsigned __int64 sal_mssas$q_bank0_gr29;, unsigned __int64 sal_mssas$q_bank0_gr30;, unsigned __int64 sal_mssas$q_bank0_gr31;, unsigned __int64 sal_mssas$q_bank1_gr16;, unsigned __int64 sal_mssas$q_bank1_gr17;  , unsigned __int64 sal_mssas$q_bank1_gr18;, unsigned __int64 sal_mssas$q_bank1_gr19;, unsigned __int64 sal_mssas$q_bank1_gr20;, unsigned __int64 sal_mssas$q_bank1_gr21;, unsigned __int64 sal_mssas$q_bank1_gr22;, unsigned __int64 sal_mssas$q_bank1_gr23;, unsigned __int64 sal_mssas$q_bank1_gr24;, unsigned __int64 sal_mssas$q_bank1_gr25;, unsigned __int64 sal_mssas$q_bank1_gr26;, unsigned __int64 sal_mssas$q_bank1_gr27;, unsigned __int64 sal_mssas$q_bank1_gr28;  , unsigned __int64 sal_mssas$q_bank1_gr29;, unsigned __int64 sal_mssas$q_bank1_gr30;, unsigned __int64 sal_mssas$q_bank1_gr31;0 unsigned __int64 sal_mssas$q_predicate_regs;% unsigned __int64 sal_mssas$q_br0;% unsigned __int64 sal_mssas$q_rsc;% unsigned __int64 sal_mssas$q_iip;& unsigned __int64 sal_mssas$q_ipsr;% unsigned __int64 sal_mssas$q_ifs;% unsigned __int64 sal_mssas$q_xip;& unsigned __int64 sal_mssas$q_xpsr;% unsigned __int64 sal_mssas$q_xfs  ;1 unsigned __int64 sal_mssas$q_reserved_1 [71]; } SAL_MSSAS;!#define SAL_MSSAS$FRAME_SIZE 1024N/*++ */N/* SAL Processor Device Error Info Section - Static Structure */N/* */N/* SAL 3.0 */V/* "Itanium Processor Family System Abstraction Layer Specification, Novembe  r 2002" */N/* Section B.2.3, pp. B-5 */N/* */N/* (PSS - Processor Static Structure) */N/*-- */$#define SAL_PSS$M_MINSTATE_VALID 0x1#define SAL_PSS$M_BR_VALID 0x2#define SAL_PSS$M_CR_VALID 0x4#define SAL_PSS$M_AR_VALID 0x8#define SAL_PSS$M_RR_VALID 0x10#defin e SAL_PSS$M_FR_VALID 0x20 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_pss {#pragma __nomember_alignment __union {) unsigned __int64 sal_pss$q_valid; __struct {2 unsigned sal_pss$v_minstate_valid : 1;, unsigned sal_pss$v_br_valid : 1;, unsigned sal_pss$v_cr_valid : 1;,  unsigned sal_pss$v_ar_valid : 1;, unsigned sal_pss$v_rr_valid : 1;, unsigned sal_pss$v_fr_valid : 1;/ unsigned sal_pss$v_reserved_1 : 32;/ unsigned sal_pss$v_reserved_2 : 26;% } sal_pss$r_valid_fields;" } sal_pss$r_valid_overlay;" SAL_MSSAS sal_pss$r_min_state; __union {3 unsigned __int64 sal_pss$q_branch_regs [8]; __struct {+ unsigned __int64 sal_pss$q_br0;+ unsign  ed __int64 sal_pss$q_br1;+ unsigned __int64 sal_pss$q_br2;+ unsigned __int64 sal_pss$q_br3;+ unsigned __int64 sal_pss$q_br4;+ unsigned __int64 sal_pss$q_br5;+ unsigned __int64 sal_pss$q_br6;+ unsigned __int64 sal_pss$q_br7;+ } sal_pss$r_branch_regs_fields;( } sal_pss$r_branch_regs_overlay; __union {6 unsigned __int64 sal_pss$q_control_regs [128]; __struct {+ unsigned  __int64 sal_pss$q_cr0;+ unsigned __int64 sal_pss$q_cr1;+ unsigned __int64 sal_pss$q_cr2;+ unsigned __int64 sal_pss$q_cr3;+ unsigned __int64 sal_pss$q_cr4;+ unsigned __int64 sal_pss$q_cr5;+ unsigned __int64 sal_pss$q_cr6;+ unsigned __int64 sal_pss$q_cr7;+ unsigned __int64 sal_pss$q_cr8;+ unsigned __int64 sal_pss$q_cr9;, unsigned __int64 sal_pss$q_cr10;, unsigned  __int64 sal_pss$q_cr11;, unsigned __int64 sal_pss$q_cr12;, unsigned __int64 sal_pss$q_cr13;, unsigned __int64 sal_pss$q_cr14;, unsigned __int64 sal_pss$q_cr15;, unsigned __int64 sal_pss$q_cr16;, unsigned __int64 sal_pss$q_cr17;, unsigned __int64 sal_pss$q_cr18;, unsigned __int64 sal_pss$q_cr19;, unsigned __int64 sal_pss$q_cr20;, unsigned __int64 sal_pss$q_cr21;, unsigned  __int64 sal_pss$q_cr22;, unsigned __int64 sal_pss$q_cr23;, unsigned __int64 sal_pss$q_cr24;, unsigned __int64 sal_pss$q_cr25;, unsigned __int64 sal_pss$q_cr26;, unsigned __int64 sal_pss$q_cr27;, unsigned __int64 sal_pss$q_cr28;, unsigned __int64 sal_pss$q_cr29;, unsigned __int64 sal_pss$q_cr30;, unsigned __int64 sal_pss$q_cr31;, unsigned __int64 sal_pss$q_cr32;, unsigned  __int64 sal_pss$q_cr33;, unsigned __int64 sal_pss$q_cr34;, unsigned __int64 sal_pss$q_cr35;, unsigned __int64 sal_pss$q_cr36;, unsigned __int64 sal_pss$q_cr37;, unsigned __int64 sal_pss$q_cr38;, unsigned __int64 sal_pss$q_cr39;, unsigned __int64 sal_pss$q_cr40;, unsigned __int64 sal_pss$q_cr41;, unsigned __int64 sal_pss$q_cr42;, unsigned __int64 sal_pss$q_cr43;, unsigned  __int64 sal_pss$q_cr44;, unsigned __int64 sal_pss$q_cr45;, unsigned __int64 sal_pss$q_cr46;, unsigned __int64 sal_pss$q_cr47;, unsigned __int64 sal_pss$q_cr48;, unsigned __int64 sal_pss$q_cr49;, unsigned __int64 sal_pss$q_cr50;, unsigned __int64 sal_pss$q_cr51;, unsigned __int64 sal_pss$q_cr52;, unsigned __int64 sal_pss$q_cr53;, unsigned __int64 sal_pss$q_cr54;, unsigned  __int64 sal_pss$q_cr55;, unsigned __int64 sal_pss$q_cr56;, unsigned __int64 sal_pss$q_cr57;, unsigned __int64 sal_pss$q_cr58;, unsigned __int64 sal_pss$q_cr59;, unsigned __int64 sal_pss$q_cr60;, unsigned __int64 sal_pss$q_cr61;, unsigned __int64 sal_pss$q_cr62;, unsigned __int64 sal_pss$q_cr63;, unsigned __int64 sal_pss$q_cr64;, unsigned __int64 sal_pss$q_cr65;, unsigned  __int64 sal_pss$q_cr66;, unsigned __int64 sal_pss$q_cr67;, unsigned __int64 sal_pss$q_cr68;, unsigned __int64 sal_pss$q_cr69;, unsigned __int64 sal_pss$q_cr70;, unsigned __int64 sal_pss$q_cr71;, unsigned __int64 sal_pss$q_cr72;, unsigned __int64 sal_pss$q_cr73;, unsigned __int64 sal_pss$q_cr74;, unsigned __int64 sal_pss$q_cr75;, unsigned __int64 sal_pss$q_cr76;, unsigned __int64 sal_pss$q_cr77;, unsigned __int64 sal_pss$q_cr78;, unsigned __int64 sal_pss$q_cr79;, unsigned __int64 sal_pss$q_cr80;, unsigned __int64 sal_pss$q_cr81;, unsigned __int64 sal_pss$q_cr82;, unsigned __int64 sal_pss$q_cr83;, unsigned __int64 sal_pss$q_cr84;, unsigned __int64 sal_pss$q_cr85;, unsigned __int64 sal_pss$q_cr86;, unsigned __int64 sal_pss$q_cr87;, unsigned ! __int64 sal_pss$q_cr88;, unsigned __int64 sal_pss$q_cr89;, unsigned __int64 sal_pss$q_cr90;, unsigned __int64 sal_pss$q_cr91;, unsigned __int64 sal_pss$q_cr92;, unsigned __int64 sal_pss$q_cr93;, unsigned __int64 sal_pss$q_cr94;, unsigned __int64 sal_pss$q_cr95;, unsigned __int64 sal_pss$q_cr96;, unsigned __int64 sal_pss$q_cr97;, unsigned __int64 sal_pss$q_cr98;, unsigned " __int64 sal_pss$q_cr99;- unsigned __int64 sal_pss$q_cr100;- unsigned __int64 sal_pss$q_cr101;- unsigned __int64 sal_pss$q_cr102;- unsigned __int64 sal_pss$q_cr103;- unsigned __int64 sal_pss$q_cr104;- unsigned __int64 sal_pss$q_cr105;- unsigned __int64 sal_pss$q_cr106;- unsigned __int64 sal_pss$q_cr107;- unsigned __int64 sal_pss$q_cr108;- unsigned __int64 sal_pss$q_cr109;- # unsigned __int64 sal_pss$q_cr110;- unsigned __int64 sal_pss$q_cr111;- unsigned __int64 sal_pss$q_cr112;- unsigned __int64 sal_pss$q_cr113;- unsigned __int64 sal_pss$q_cr114;- unsigned __int64 sal_pss$q_cr115;- unsigned __int64 sal_pss$q_cr116;- unsigned __int64 sal_pss$q_cr117;- unsigned __int64 sal_pss$q_cr118;- unsigned __int64 sal_pss$q_cr119;- unsigned __int $ 64 sal_pss$q_cr120;- unsigned __int64 sal_pss$q_cr121;- unsigned __int64 sal_pss$q_cr122;- unsigned __int64 sal_pss$q_cr123;- unsigned __int64 sal_pss$q_cr124;- unsigned __int64 sal_pss$q_cr125;- unsigned __int64 sal_pss$q_cr126;- unsigned __int64 sal_pss$q_cr127;, } sal_pss$r_control_regs_fields;) } sal_pss$r_control_regs_overlay; __union {: unsigned __int64 sal_pss$q_applica % tion_regs [128]; __struct {+ unsigned __int64 sal_pss$q_ar0;+ unsigned __int64 sal_pss$q_ar1;+ unsigned __int64 sal_pss$q_ar2;+ unsigned __int64 sal_pss$q_ar3;+ unsigned __int64 sal_pss$q_ar4;+ unsigned __int64 sal_pss$q_ar5;+ unsigned __int64 sal_pss$q_ar6;+ unsigned __int64 sal_pss$q_ar7;+ unsigned __int64 sal_pss$q_ar8;+ unsigned __int64 sal_pss$q_ar9;, & unsigned __int64 sal_pss$q_ar10;, unsigned __int64 sal_pss$q_ar11;, unsigned __int64 sal_pss$q_ar12;, unsigned __int64 sal_pss$q_ar13;, unsigned __int64 sal_pss$q_ar14;, unsigned __int64 sal_pss$q_ar15;, unsigned __int64 sal_pss$q_ar16;, unsigned __int64 sal_pss$q_ar17;, unsigned __int64 sal_pss$q_ar18;, unsigned __int64 sal_pss$q_ar19;, unsigned __int64 sal_pss$q_ar20;, ' unsigned __int64 sal_pss$q_ar21;, unsigned __int64 sal_pss$q_ar22;, unsigned __int64 sal_pss$q_ar23;, unsigned __int64 sal_pss$q_ar24;, unsigned __int64 sal_pss$q_ar25;, unsigned __int64 sal_pss$q_ar26;, unsigned __int64 sal_pss$q_ar27;, unsigned __int64 sal_pss$q_ar28;, unsigned __int64 sal_pss$q_ar29;, unsigned __int64 sal_pss$q_ar30;, unsigned __int64 sal_pss$q_ar31;, ( unsigned __int64 sal_pss$q_ar32;, unsigned __int64 sal_pss$q_ar33;, unsigned __int64 sal_pss$q_ar34;, unsigned __int64 sal_pss$q_ar35;, unsigned __int64 sal_pss$q_ar36;, unsigned __int64 sal_pss$q_ar37;, unsigned __int64 sal_pss$q_ar38;, unsigned __int64 sal_pss$q_ar39;, unsigned __int64 sal_pss$q_ar40;, unsigned __int64 sal_pss$q_ar41;, unsigned __int64 sal_pss$q_ar42;, ) unsigned __int64 sal_pss$q_ar43;, unsigned __int64 sal_pss$q_ar44;, unsigned __int64 sal_pss$q_ar45;, unsigned __int64 sal_pss$q_ar46;, unsigned __int64 sal_pss$q_ar47;, unsigned __int64 sal_pss$q_ar48;, unsigned __int64 sal_pss$q_ar49;, unsigned __int64 sal_pss$q_ar50;, unsigned __int64 sal_pss$q_ar51;, unsigned __int64 sal_pss$q_ar52;, unsigned __int64 sal_pss$q_ar53;, * unsigned __int64 sal_pss$q_ar54;, unsigned __int64 sal_pss$q_ar55;, unsigned __int64 sal_pss$q_ar56;, unsigned __int64 sal_pss$q_ar57;, unsigned __int64 sal_pss$q_ar58;, unsigned __int64 sal_pss$q_ar59;, unsigned __int64 sal_pss$q_ar60;, unsigned __int64 sal_pss$q_ar61;, unsigned __int64 sal_pss$q_ar62;, unsigned __int64 sal_pss$q_ar63;, unsigned __int64 sal_pss$q_ar64;, + unsigned __int64 sal_pss$q_ar65;, unsigned __int64 sal_pss$q_ar66;, unsigned __int64 sal_pss$q_ar67;, unsigned __int64 sal_pss$q_ar68;, unsigned __int64 sal_pss$q_ar69;, unsigned __int64 sal_pss$q_ar70;, unsigned __int64 sal_pss$q_ar71;, unsigned __int64 sal_pss$q_ar72;, unsigned __int64 sal_pss$q_ar73;, unsigned __int64 sal_pss$q_ar74;, unsigned __int64 sal_pss$q_ar75;, , unsigned __int64 sal_pss$q_ar76;, unsigned __int64 sal_pss$q_ar77;, unsigned __int64 sal_pss$q_ar78;, unsigned __int64 sal_pss$q_ar79;, unsigned __int64 sal_pss$q_ar80;, unsigned __int64 sal_pss$q_ar81;, unsigned __int64 sal_pss$q_ar82;, unsigned __int64 sal_pss$q_ar83;, unsigned __int64 sal_pss$q_ar84;, unsigned __int64 sal_pss$q_ar85;, unsigned __int64 sal_pss$q_ar86;, - unsigned __int64 sal_pss$q_ar87;, unsigned __int64 sal_pss$q_ar88;, unsigned __int64 sal_pss$q_ar89;, unsigned __int64 sal_pss$q_ar90;, unsigned __int64 sal_pss$q_ar91;, unsigned __int64 sal_pss$q_ar92;, unsigned __int64 sal_pss$q_ar93;, unsigned __int64 sal_pss$q_ar94;, unsigned __int64 sal_pss$q_ar95;, unsigned __int64 sal_pss$q_ar96;, unsigned __int64 sal_pss$q_ar97;, . unsigned __int64 sal_pss$q_ar98;, unsigned __int64 sal_pss$q_ar99;- unsigned __int64 sal_pss$q_ar100;- unsigned __int64 sal_pss$q_ar101;- unsigned __int64 sal_pss$q_ar102;- unsigned __int64 sal_pss$q_ar103;- unsigned __int64 sal_pss$q_ar104;- unsigned __int64 sal_pss$q_ar105;- unsigned __int64 sal_pss$q_ar106;- unsigned __int64 sal_pss$q_ar107;- unsigned __int64 sal_pss / $q_ar108;- unsigned __int64 sal_pss$q_ar109;- unsigned __int64 sal_pss$q_ar110;- unsigned __int64 sal_pss$q_ar111;- unsigned __int64 sal_pss$q_ar112;- unsigned __int64 sal_pss$q_ar113;- unsigned __int64 sal_pss$q_ar114;- unsigned __int64 sal_pss$q_ar115;- unsigned __int64 sal_pss$q_ar116;- unsigned __int64 sal_pss$q_ar117;- unsigned __int64 sal_pss$q_ar118;- un 0 signed __int64 sal_pss$q_ar119;- unsigned __int64 sal_pss$q_ar120;- unsigned __int64 sal_pss$q_ar121;- unsigned __int64 sal_pss$q_ar122;- unsigned __int64 sal_pss$q_ar123;- unsigned __int64 sal_pss$q_ar124;- unsigned __int64 sal_pss$q_ar125;- unsigned __int64 sal_pss$q_ar126;- unsigned __int64 sal_pss$q_ar127;0 } sal_pss$r_application_regs_fields;- } sal_pss$r_application_regs_o 1 verlay; __union {3 unsigned __int64 sal_pss$q_region_regs [8]; __struct {+ unsigned __int64 sal_pss$q_rr0;+ unsigned __int64 sal_pss$q_rr1;+ unsigned __int64 sal_pss$q_rr2;+ unsigned __int64 sal_pss$q_rr3;+ unsigned __int64 sal_pss$q_rr4;+ unsigned __int64 sal_pss$q_rr5;+ unsigned __int64 sal_pss$q_rr6;+ unsigned __int64 sal_pss$q_rr7;+ } sal_pss$r_region_regs_ 2 fields;( } sal_pss$r_region_regs_overlay; __union {1 unsigned int sal_pss$o_fp_regs [128] [4]; __struct {+ unsigned int sal_pss$o_fp0 [4];+ unsigned int sal_pss$o_fp1 [4];+ unsigned int sal_pss$o_fp2 [4];+ unsigned int sal_pss$o_fp3 [4];+ unsigned int sal_pss$o_fp4 [4];+ unsigned int sal_pss$o_fp5 [4];+ unsigned int sal_pss$o_fp6 [4];+ unsigned int sal_pss$o_fp7 [4] 3 ;+ unsigned int sal_pss$o_fp8 [4];+ unsigned int sal_pss$o_fp9 [4];, unsigned int sal_pss$o_fp10 [4];, unsigned int sal_pss$o_fp11 [4];, unsigned int sal_pss$o_fp12 [4];, unsigned int sal_pss$o_fp13 [4];, unsigned int sal_pss$o_fp14 [4];, unsigned int sal_pss$o_fp15 [4];, unsigned int sal_pss$o_fp16 [4];, unsigned int sal_pss$o_fp17 [4];, unsigned int sal_pss$o_fp18 [4 4 ];, unsigned int sal_pss$o_fp19 [4];, unsigned int sal_pss$o_fp20 [4];, unsigned int sal_pss$o_fp21 [4];, unsigned int sal_pss$o_fp22 [4];, unsigned int sal_pss$o_fp23 [4];, unsigned int sal_pss$o_fp24 [4];, unsigned int sal_pss$o_fp25 [4];, unsigned int sal_pss$o_fp26 [4];, unsigned int sal_pss$o_fp27 [4];, unsigned int sal_pss$o_fp28 [4];, unsigned int sal_pss$o_fp29 [4 5 ];, unsigned int sal_pss$o_fp30 [4];, unsigned int sal_pss$o_fp31 [4];, unsigned int sal_pss$o_fp32 [4];, unsigned int sal_pss$o_fp33 [4];, unsigned int sal_pss$o_fp34 [4];, unsigned int sal_pss$o_fp35 [4];, unsigned int sal_pss$o_fp36 [4];, unsigned int sal_pss$o_fp37 [4];, unsigned int sal_pss$o_fp38 [4];, unsigned int sal_pss$o_fp39 [4];, unsigned int sal_pss$o_fp40 [4 6 ];, unsigned int sal_pss$o_fp41 [4];, unsigned int sal_pss$o_fp42 [4];, unsigned int sal_pss$o_fp43 [4];, unsigned int sal_pss$o_fp44 [4];, unsigned int sal_pss$o_fp45 [4];, unsigned int sal_pss$o_fp46 [4];, unsigned int sal_pss$o_fp47 [4];, unsigned int sal_pss$o_fp48 [4];, unsigned int sal_pss$o_fp49 [4];, unsigned int sal_pss$o_fp50 [4];, unsigned int sal_pss$o_fp51 [4 7 ];, unsigned int sal_pss$o_fp52 [4];, unsigned int sal_pss$o_fp53 [4];, unsigned int sal_pss$o_fp54 [4];, unsigned int sal_pss$o_fp55 [4];, unsigned int sal_pss$o_fp56 [4];, unsigned int sal_pss$o_fp57 [4];, unsigned int sal_pss$o_fp58 [4];, unsigned int sal_pss$o_fp59 [4];, unsigned int sal_pss$o_fp60 [4];, unsigned int sal_pss$o_fp61 [4];, unsigned int sal_pss$o_fp62 [4 8 ];, unsigned int sal_pss$o_fp63 [4];, unsigned int sal_pss$o_fp64 [4];, unsigned int sal_pss$o_fp65 [4];, unsigned int sal_pss$o_fp66 [4];, unsigned int sal_pss$o_fp67 [4];, unsigned int sal_pss$o_fp68 [4];, unsigned int sal_pss$o_fp69 [4];, unsigned int sal_pss$o_fp70 [4];, unsigned int sal_pss$o_fp71 [4];, unsigned int sal_pss$o_fp72 [4];, unsigned int sal_pss$o_fp73 [4 9 ];, unsigned int sal_pss$o_fp74 [4];, unsigned int sal_pss$o_fp75 [4];, unsigned int sal_pss$o_fp76 [4];, unsigned int sal_pss$o_fp77 [4];, unsigned int sal_pss$o_fp78 [4];, unsigned int sal_pss$o_fp79 [4];, unsigned int sal_pss$o_fp80 [4];, unsigned int sal_pss$o_fp81 [4];, unsigned int sal_pss$o_fp82 [4];, unsigned int sal_pss$o_fp83 [4];, unsigned int sal_pss$o_fp84 [4 : ];, unsigned int sal_pss$o_fp85 [4];, unsigned int sal_pss$o_fp86 [4];, unsigned int sal_pss$o_fp87 [4];, unsigned int sal_pss$o_fp88 [4];, unsigned int sal_pss$o_fp89 [4];, unsigned int sal_pss$o_fp90 [4];, unsigned int sal_pss$o_fp91 [4];, unsigned int sal_pss$o_fp92 [4];, unsigned int sal_pss$o_fp93 [4];, unsigned int sal_pss$o_fp94 [4];, unsigned int sal_pss$o_fp95 [4 ; ];, unsigned int sal_pss$o_fp96 [4];, unsigned int sal_pss$o_fp97 [4];, unsigned int sal_pss$o_fp98 [4];, unsigned int sal_pss$o_fp99 [4];- unsigned int sal_pss$o_fp100 [4];- unsigned int sal_pss$o_fp101 [4];- unsigned int sal_pss$o_fp102 [4];- unsigned int sal_pss$o_fp103 [4];- unsigned int sal_pss$o_fp104 [4];- unsigned int sal_pss$o_fp105 [4];- unsigned int sal_p < ss$o_fp106 [4];- unsigned int sal_pss$o_fp107 [4];- unsigned int sal_pss$o_fp108 [4];- unsigned int sal_pss$o_fp109 [4];- unsigned int sal_pss$o_fp110 [4];- unsigned int sal_pss$o_fp111 [4];- unsigned int sal_pss$o_fp112 [4];- unsigned int sal_pss$o_fp113 [4];- unsigned int sal_pss$o_fp114 [4];- unsigned int sal_pss$o_fp115 [4];- unsigned int sal_pss$o_fp116 [4];- = unsigned int sal_pss$o_fp117 [4];- unsigned int sal_pss$o_fp118 [4];- unsigned int sal_pss$o_fp119 [4];- unsigned int sal_pss$o_fp120 [4];- unsigned int sal_pss$o_fp121 [4];- unsigned int sal_pss$o_fp122 [4];- unsigned int sal_pss$o_fp123 [4];- unsigned int sal_pss$o_fp124 [4];- unsigned int sal_pss$o_fp125 [4];- unsigned int sal_pss$o_fp126 [4];- unsigned int sal_pss$o > _fp127 [4];' } sal_pss$r_fp_regs_fields;$ } sal_pss$r_fp_regs_overlay; } SAL_PSS; #if !defined(__VAXC)?#define sal_pss$q_valid sal_pss$r_valid_overlay.sal_pss$q_validh#define sal_pss$v_minstate_valid sal_pss$r_valid_overlay.sal_pss$r_valid_fields.sal_pss$v_minstate_valid\#define sal_pss$v_br_valid sal_pss$r_valid_overlay.sal_pss$r_valid_fields.sal_pss$v_br_valid\#define sal_pss$v_cr_valid sal_pss$r_valid_overlay.sal_pss$r_valid_fields.sal_pss$v_cr_valid\#define sa? l_pss$v_ar_valid sal_pss$r_valid_overlay.sal_pss$r_valid_fields.sal_pss$v_ar_valid\#define sal_pss$v_rr_valid sal_pss$r_valid_overlay.sal_pss$r_valid_fields.sal_pss$v_rr_valid\#define sal_pss$v_fr_valid sal_pss$r_valid_overlay.sal_pss$r_valid_fields.sal_pss$v_fr_validQ#define sal_pss$q_branch_regs sal_pss$r_branch_regs_overlay.sal_pss$q_branch_regs^#define sal_pss$q_br0 sal_pss$r_branch_regs_overlay.sal_pss$r_branch_regs_fields.sal_pss$q_br0^#define sal_pss$q_br1 sal_pss$r_branch_regs_overlay.sa@ l_pss$r_branch_regs_fields.sal_pss$q_br1^#define sal_pss$q_br2 sal_pss$r_branch_regs_overlay.sal_pss$r_branch_regs_fields.sal_pss$q_br2^#define sal_pss$q_br3 sal_pss$r_branch_regs_overlay.sal_pss$r_branch_regs_fields.sal_pss$q_br3^#define sal_pss$q_br4 sal_pss$r_branch_regs_overlay.sal_pss$r_branch_regs_fields.sal_pss$q_br4^#define sal_pss$q_br5 sal_pss$r_branch_regs_overlay.sal_pss$r_branch_regs_fields.sal_pss$q_br5^#define sal_pss$q_br6 sal_pss$r_branch_regs_overlay.sal_pss$r_branch_regs_fieldsA .sal_pss$q_br6^#define sal_pss$q_br7 sal_pss$r_branch_regs_overlay.sal_pss$r_branch_regs_fields.sal_pss$q_br7T#define sal_pss$q_control_regs sal_pss$r_control_regs_overlay.sal_pss$q_control_regs`#define sal_pss$q_cr0 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr0`#define sal_pss$q_cr1 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr1`#define sal_pss$q_cr2 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr2`#define sal_psB s$q_cr3 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr3`#define sal_pss$q_cr4 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr4`#define sal_pss$q_cr5 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr5`#define sal_pss$q_cr6 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr6`#define sal_pss$q_cr7 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr7`#define sal_pss$q_cr8 sal_pss$C r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr8`#define sal_pss$q_cr9 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr9b#define sal_pss$q_cr10 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr10b#define sal_pss$q_cr11 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr11b#define sal_pss$q_cr12 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr12b#define sal_pss$q_cr13 sal_pss$r_controlD _regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr13b#define sal_pss$q_cr14 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr14b#define sal_pss$q_cr15 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr15b#define sal_pss$q_cr16 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr16b#define sal_pss$q_cr17 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr17b#define sal_pss$q_cr18 sal_pss$r_control_regs_E overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr18b#define sal_pss$q_cr19 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr19b#define sal_pss$q_cr20 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr20b#define sal_pss$q_cr21 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr21b#define sal_pss$q_cr22 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr22b#define sal_pss$q_cr23 sal_pss$r_control_regs_overlaF y.sal_pss$r_control_regs_fields.sal_pss$q_cr23b#define sal_pss$q_cr24 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr24b#define sal_pss$q_cr25 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr25b#define sal_pss$q_cr26 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr26b#define sal_pss$q_cr27 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr27b#define sal_pss$q_cr28 sal_pss$r_control_regs_overlay.sal_G pss$r_control_regs_fields.sal_pss$q_cr28b#define sal_pss$q_cr29 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr29b#define sal_pss$q_cr30 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr30b#define sal_pss$q_cr31 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr31b#define sal_pss$q_cr32 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr32b#define sal_pss$q_cr33 sal_pss$r_control_regs_overlay.sal_pss$r_H control_regs_fields.sal_pss$q_cr33b#define sal_pss$q_cr34 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr34b#define sal_pss$q_cr35 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr35b#define sal_pss$q_cr36 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr36b#define sal_pss$q_cr37 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr37b#define sal_pss$q_cr38 sal_pss$r_control_regs_overlay.sal_pss$r_controI l_regs_fields.sal_pss$q_cr38b#define sal_pss$q_cr39 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr39b#define sal_pss$q_cr40 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr40b#define sal_pss$q_cr41 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr41b#define sal_pss$q_cr42 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr42b#define sal_pss$q_cr43 sal_pss$r_control_regs_overlay.sal_pss$r_control_regsJ _fields.sal_pss$q_cr43b#define sal_pss$q_cr44 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr44b#define sal_pss$q_cr45 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr45b#define sal_pss$q_cr46 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr46b#define sal_pss$q_cr47 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr47b#define sal_pss$q_cr48 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fieldK s.sal_pss$q_cr48b#define sal_pss$q_cr49 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr49b#define sal_pss$q_cr50 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr50b#define sal_pss$q_cr51 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr51b#define sal_pss$q_cr52 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr52b#define sal_pss$q_cr53 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_L pss$q_cr53b#define sal_pss$q_cr54 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr54b#define sal_pss$q_cr55 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr55b#define sal_pss$q_cr56 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr56b#define sal_pss$q_cr57 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr57b#define sal_pss$q_cr58 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_M cr58b#define sal_pss$q_cr59 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr59b#define sal_pss$q_cr60 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr60b#define sal_pss$q_cr61 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr61b#define sal_pss$q_cr62 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr62b#define sal_pss$q_cr63 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr63bN #define sal_pss$q_cr64 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr64b#define sal_pss$q_cr65 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr65b#define sal_pss$q_cr66 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr66b#define sal_pss$q_cr67 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr67b#define sal_pss$q_cr68 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr68b#definO e sal_pss$q_cr69 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr69b#define sal_pss$q_cr70 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr70b#define sal_pss$q_cr71 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr71b#define sal_pss$q_cr72 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr72b#define sal_pss$q_cr73 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr73b#define sal_P pss$q_cr74 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr74b#define sal_pss$q_cr75 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr75b#define sal_pss$q_cr76 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr76b#define sal_pss$q_cr77 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr77b#define sal_pss$q_cr78 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr78b#define sal_pss$q_Q cr79 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr79b#define sal_pss$q_cr80 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr80b#define sal_pss$q_cr81 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr81b#define sal_pss$q_cr82 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr82b#define sal_pss$q_cr83 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr83b#define sal_pss$q_cr84 sR al_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr84b#define sal_pss$q_cr85 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr85b#define sal_pss$q_cr86 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr86b#define sal_pss$q_cr87 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr87b#define sal_pss$q_cr88 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr88b#define sal_pss$q_cr89 sal_pssS $r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr89b#define sal_pss$q_cr90 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr90b#define sal_pss$q_cr91 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr91b#define sal_pss$q_cr92 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr92b#define sal_pss$q_cr93 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr93b#define sal_pss$q_cr94 sal_pss$r_conT trol_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr94b#define sal_pss$q_cr95 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr95b#define sal_pss$q_cr96 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr96b#define sal_pss$q_cr97 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr97b#define sal_pss$q_cr98 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr98b#define sal_pss$q_cr99 sal_pss$r_control_rU egs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr99d#define sal_pss$q_cr100 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr100d#define sal_pss$q_cr101 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr101d#define sal_pss$q_cr102 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr102d#define sal_pss$q_cr103 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr103d#define sal_pss$q_cr104 sal_pss$r_controV l_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr104d#define sal_pss$q_cr105 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr105d#define sal_pss$q_cr106 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr106d#define sal_pss$q_cr107 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr107d#define sal_pss$q_cr108 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr108d#define sal_pss$q_cr109 sal_pss$r_coW ntrol_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr109d#define sal_pss$q_cr110 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr110d#define sal_pss$q_cr111 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr111d#define sal_pss$q_cr112 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr112d#define sal_pss$q_cr113 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr113d#define sal_pss$q_cr114 sal_pss$X r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr114d#define sal_pss$q_cr115 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr115d#define sal_pss$q_cr116 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr116d#define sal_pss$q_cr117 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr117d#define sal_pss$q_cr118 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr118d#define sal_pss$q_cr119 sal_Y pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr119d#define sal_pss$q_cr120 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr120d#define sal_pss$q_cr121 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr121d#define sal_pss$q_cr122 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr122d#define sal_pss$q_cr123 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr123d#define sal_pss$q_cr124 Z sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr124d#define sal_pss$q_cr125 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr125d#define sal_pss$q_cr126 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr126d#define sal_pss$q_cr127 sal_pss$r_control_regs_overlay.sal_pss$r_control_regs_fields.sal_pss$q_cr127`#define sal_pss$q_application_regs sal_pss$r_application_regs_overlay.sal_pss$q_application_regsh#define sal_pss$q_ar0 sa[ l_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar0h#define sal_pss$q_ar1 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar1h#define sal_pss$q_ar2 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar2h#define sal_pss$q_ar3 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar3h#define sal_pss$q_ar4 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar4h\ #define sal_pss$q_ar5 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar5h#define sal_pss$q_ar6 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar6h#define sal_pss$q_ar7 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar7h#define sal_pss$q_ar8 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar8h#define sal_pss$q_ar9 sal_pss$r_application_regs_overlay.sal_pss$r_application_reg] s_fields.sal_pss$q_ar9j#define sal_pss$q_ar10 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar10j#define sal_pss$q_ar11 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar11j#define sal_pss$q_ar12 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar12j#define sal_pss$q_ar13 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar13j#define sal_pss$q_ar14 sal_pss$r_application_regs_^ overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar14j#define sal_pss$q_ar15 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar15j#define sal_pss$q_ar16 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar16j#define sal_pss$q_ar17 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar17j#define sal_pss$q_ar18 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar18j#define sal_pss$_ q_ar19 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar19j#define sal_pss$q_ar20 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar20j#define sal_pss$q_ar21 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar21j#define sal_pss$q_ar22 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar22j#define sal_pss$q_ar23 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_field` s.sal_pss$q_ar23j#define sal_pss$q_ar24 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar24j#define sal_pss$q_ar25 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar25j#define sal_pss$q_ar26 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar26j#define sal_pss$q_ar27 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar27j#define sal_pss$q_ar28 sal_pss$r_application_regs_overlaa y.sal_pss$r_application_regs_fields.sal_pss$q_ar28j#define sal_pss$q_ar29 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar29j#define sal_pss$q_ar30 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar30j#define sal_pss$q_ar31 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar31j#define sal_pss$q_ar32 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar32j#define sal_pss$q_ar33b sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar33j#define sal_pss$q_ar34 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar34j#define sal_pss$q_ar35 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar35j#define sal_pss$q_ar36 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar36j#define sal_pss$q_ar37 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_c pss$q_ar37j#define sal_pss$q_ar38 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar38j#define sal_pss$q_ar39 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar39j#define sal_pss$q_ar40 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar40j#define sal_pss$q_ar41 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar41j#define sal_pss$q_ar42 sal_pss$r_application_regs_overlay.sal_d pss$r_application_regs_fields.sal_pss$q_ar42j#define sal_pss$q_ar43 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar43j#define sal_pss$q_ar44 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar44j#define sal_pss$q_ar45 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar45j#define sal_pss$q_ar46 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar46j#define sal_pss$q_ar47 sal_pe ss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar47j#define sal_pss$q_ar48 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar48j#define sal_pss$q_ar49 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar49j#define sal_pss$q_ar50 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar50j#define sal_pss$q_ar51 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_f ar51j#define sal_pss$q_ar52 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar52j#define sal_pss$q_ar53 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar53j#define sal_pss$q_ar54 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar54j#define sal_pss$q_ar55 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar55j#define sal_pss$q_ar56 sal_pss$r_application_regs_overlay.sal_pss$r_g application_regs_fields.sal_pss$q_ar56j#define sal_pss$q_ar57 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar57j#define sal_pss$q_ar58 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar58j#define sal_pss$q_ar59 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar59j#define sal_pss$q_ar60 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar60j#define sal_pss$q_ar61 sal_pss$r_ah pplication_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar61j#define sal_pss$q_ar62 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar62j#define sal_pss$q_ar63 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar63j#define sal_pss$q_ar64 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar64j#define sal_pss$q_ar65 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar65ji #define sal_pss$q_ar66 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar66j#define sal_pss$q_ar67 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar67j#define sal_pss$q_ar68 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar68j#define sal_pss$q_ar69 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar69j#define sal_pss$q_ar70 sal_pss$r_application_regs_overlay.sal_pss$r_applicj ation_regs_fields.sal_pss$q_ar70j#define sal_pss$q_ar71 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar71j#define sal_pss$q_ar72 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar72j#define sal_pss$q_ar73 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar73j#define sal_pss$q_ar74 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar74j#define sal_pss$q_ar75 sal_pss$r_applicak tion_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar75j#define sal_pss$q_ar76 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar76j#define sal_pss$q_ar77 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar77j#define sal_pss$q_ar78 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar78j#define sal_pss$q_ar79 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar79j#definl e sal_pss$q_ar80 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar80j#define sal_pss$q_ar81 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar81j#define sal_pss$q_ar82 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar82j#define sal_pss$q_ar83 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar83j#define sal_pss$q_ar84 sal_pss$r_application_regs_overlay.sal_pss$r_application_m regs_fields.sal_pss$q_ar84j#define sal_pss$q_ar85 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar85j#define sal_pss$q_ar86 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar86j#define sal_pss$q_ar87 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar87j#define sal_pss$q_ar88 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar88j#define sal_pss$q_ar89 sal_pss$r_application_rn egs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar89j#define sal_pss$q_ar90 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar90j#define sal_pss$q_ar91 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar91j#define sal_pss$q_ar92 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar92j#define sal_pss$q_ar93 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar93j#define sal_o pss$q_ar94 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar94j#define sal_pss$q_ar95 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar95j#define sal_pss$q_ar96 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar96j#define sal_pss$q_ar97 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar97j#define sal_pss$q_ar98 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fp ields.sal_pss$q_ar98j#define sal_pss$q_ar99 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar99l#define sal_pss$q_ar100 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar100l#define sal_pss$q_ar101 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar101l#define sal_pss$q_ar102 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar102l#define sal_pss$q_ar103 sal_pss$r_application_q regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar103l#define sal_pss$q_ar104 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar104l#define sal_pss$q_ar105 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar105l#define sal_pss$q_ar106 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar106l#define sal_pss$q_ar107 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar107l#dr efine sal_pss$q_ar108 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar108l#define sal_pss$q_ar109 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar109l#define sal_pss$q_ar110 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar110l#define sal_pss$q_ar111 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar111l#define sal_pss$q_ar112 sal_pss$r_application_regs_overlay.sal_pss$rs _application_regs_fields.sal_pss$q_ar112l#define sal_pss$q_ar113 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar113l#define sal_pss$q_ar114 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar114l#define sal_pss$q_ar115 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar115l#define sal_pss$q_ar116 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar116l#define sal_pss$q_ar117 t sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar117l#define sal_pss$q_ar118 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar118l#define sal_pss$q_ar119 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar119l#define sal_pss$q_ar120 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar120l#define sal_pss$q_ar121 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fielu ds.sal_pss$q_ar121l#define sal_pss$q_ar122 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar122l#define sal_pss$q_ar123 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar123l#define sal_pss$q_ar124 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar124l#define sal_pss$q_ar125 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar125l#define sal_pss$q_ar126 sal_pss$r_application_v regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar126l#define sal_pss$q_ar127 sal_pss$r_application_regs_overlay.sal_pss$r_application_regs_fields.sal_pss$q_ar127Q#define sal_pss$q_region_regs sal_pss$r_region_regs_overlay.sal_pss$q_region_regs^#define sal_pss$q_rr0 sal_pss$r_region_regs_overlay.sal_pss$r_region_regs_fields.sal_pss$q_rr0^#define sal_pss$q_rr1 sal_pss$r_region_regs_overlay.sal_pss$r_region_regs_fields.sal_pss$q_rr1^#define sal_pss$q_rr2 sal_pss$r_region_regs_overlay.sal_w pss$r_region_regs_fields.sal_pss$q_rr2^#define sal_pss$q_rr3 sal_pss$r_region_regs_overlay.sal_pss$r_region_regs_fields.sal_pss$q_rr3^#define sal_pss$q_rr4 sal_pss$r_region_regs_overlay.sal_pss$r_region_regs_fields.sal_pss$q_rr4^#define sal_pss$q_rr5 sal_pss$r_region_regs_overlay.sal_pss$r_region_regs_fields.sal_pss$q_rr5^#define sal_pss$q_rr6 sal_pss$r_region_regs_overlay.sal_pss$r_region_regs_fields.sal_pss$q_rr6^#define sal_pss$q_rr7 sal_pss$r_region_regs_overlay.sal_pss$r_region_regs_fields.sx al_pss$q_rr7E#define sal_pss$o_fp_regs sal_pss$r_fp_regs_overlay.sal_pss$o_fp_regsV#define sal_pss$o_fp0 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp0V#define sal_pss$o_fp1 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp1V#define sal_pss$o_fp2 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp2V#define sal_pss$o_fp3 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp3V#define sal_pss$o_fp4 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fiy elds.sal_pss$o_fp4V#define sal_pss$o_fp5 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp5V#define sal_pss$o_fp6 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp6V#define sal_pss$o_fp7 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp7V#define sal_pss$o_fp8 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp8V#define sal_pss$o_fp9 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp9X#define sal_pss$o_fp10 sal_pss$r_fp_regs_overlz ay.sal_pss$r_fp_regs_fields.sal_pss$o_fp10X#define sal_pss$o_fp11 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp11X#define sal_pss$o_fp12 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp12X#define sal_pss$o_fp13 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp13X#define sal_pss$o_fp14 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp14X#define sal_pss$o_fp15 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp15X#define sal_{ pss$o_fp16 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp16X#define sal_pss$o_fp17 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp17X#define sal_pss$o_fp18 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp18X#define sal_pss$o_fp19 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp19X#define sal_pss$o_fp20 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp20X#define sal_pss$o_fp21 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_f| ields.sal_pss$o_fp21X#define sal_pss$o_fp22 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp22X#define sal_pss$o_fp23 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp23X#define sal_pss$o_fp24 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp24X#define sal_pss$o_fp25 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp25X#define sal_pss$o_fp26 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp26X#define sal_pss$o_fp27 sal_pss$r_f} p_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp27X#define sal_pss$o_fp28 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp28X#define sal_pss$o_fp29 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp29X#define sal_pss$o_fp30 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp30X#define sal_pss$o_fp31 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp31X#define sal_pss$o_fp32 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp32X~ #define sal_pss$o_fp33 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp33X#define sal_pss$o_fp34 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp34X#define sal_pss$o_fp35 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp35X#define sal_pss$o_fp36 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp36X#define sal_pss$o_fp37 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp37X#define sal_pss$o_fp38 sal_pss$r_fp_regs_overlay.sal_pss $r_fp_regs_fields.sal_pss$o_fp38X#define sal_pss$o_fp39 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp39X#define sal_pss$o_fp40 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp40X#define sal_pss$o_fp41 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp41X#define sal_pss$o_fp42 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp42X#define sal_pss$o_fp43 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp43X#define sal_pss$o_fp44 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp44X#define sal_pss$o_fp45 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp45X#define sal_pss$o_fp46 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp46X#define sal_pss$o_fp47 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp47X#define sal_pss$o_fp48 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp48X#define sal_pss$o_fp49 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_ pss$o_fp49X#define sal_pss$o_fp50 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp50X#define sal_pss$o_fp51 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp51X#define sal_pss$o_fp52 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp52X#define sal_pss$o_fp53 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp53X#define sal_pss$o_fp54 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp54X#define sal_pss$o_fp55 sal_pss$r_fp_regs_ove rlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp55X#define sal_pss$o_fp56 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp56X#define sal_pss$o_fp57 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp57X#define sal_pss$o_fp58 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp58X#define sal_pss$o_fp59 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp59X#define sal_pss$o_fp60 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp60X#define sa l_pss$o_fp61 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp61X#define sal_pss$o_fp62 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp62X#define sal_pss$o_fp63 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp63X#define sal_pss$o_fp64 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp64X#define sal_pss$o_fp65 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp65X#define sal_pss$o_fp66 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs _fields.sal_pss$o_fp66X#define sal_pss$o_fp67 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp67X#define sal_pss$o_fp68 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp68X#define sal_pss$o_fp69 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp69X#define sal_pss$o_fp70 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp70X#define sal_pss$o_fp71 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp71X#define sal_pss$o_fp72 sal_pss$r _fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp72X#define sal_pss$o_fp73 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp73X#define sal_pss$o_fp74 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp74X#define sal_pss$o_fp75 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp75X#define sal_pss$o_fp76 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp76X#define sal_pss$o_fp77 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp77 X#define sal_pss$o_fp78 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp78X#define sal_pss$o_fp79 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp79X#define sal_pss$o_fp80 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp80X#define sal_pss$o_fp81 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp81X#define sal_pss$o_fp82 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp82X#define sal_pss$o_fp83 sal_pss$r_fp_regs_overlay.sal_p ss$r_fp_regs_fields.sal_pss$o_fp83X#define sal_pss$o_fp84 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp84X#define sal_pss$o_fp85 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp85X#define sal_pss$o_fp86 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp86X#define sal_pss$o_fp87 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp87X#define sal_pss$o_fp88 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp88X#define sal_pss$o_fp 89 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp89X#define sal_pss$o_fp90 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp90X#define sal_pss$o_fp91 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp91X#define sal_pss$o_fp92 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp92X#define sal_pss$o_fp93 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp93X#define sal_pss$o_fp94 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sa l_pss$o_fp94X#define sal_pss$o_fp95 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp95X#define sal_pss$o_fp96 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp96X#define sal_pss$o_fp97 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp97X#define sal_pss$o_fp98 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp98X#define sal_pss$o_fp99 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp99Z#define sal_pss$o_fp100 sal_pss$r_fp_regs_ overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp100Z#define sal_pss$o_fp101 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp101Z#define sal_pss$o_fp102 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp102Z#define sal_pss$o_fp103 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp103Z#define sal_pss$o_fp104 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp104Z#define sal_pss$o_fp105 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp1 05Z#define sal_pss$o_fp106 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp106Z#define sal_pss$o_fp107 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp107Z#define sal_pss$o_fp108 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp108Z#define sal_pss$o_fp109 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp109Z#define sal_pss$o_fp110 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp110Z#define sal_pss$o_fp111 sal_pss$r_fp_regs_ overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp111Z#define sal_pss$o_fp112 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp112Z#define sal_pss$o_fp113 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp113Z#define sal_pss$o_fp114 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp114Z#define sal_pss$o_fp115 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp115Z#define sal_pss$o_fp116 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp1 16Z#define sal_pss$o_fp117 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp117Z#define sal_pss$o_fp118 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp118Z#define sal_pss$o_fp119 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp119Z#define sal_pss$o_fp120 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp120Z#define sal_pss$o_fp121 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp121Z#define sal_pss$o_fp122 sal_pss$r_fp_regs_ overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp122Z#define sal_pss$o_fp123 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp123Z#define sal_pss$o_fp124 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp124Z#define sal_pss$o_fp125 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp125Z#define sal_pss$o_fp126 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp126Z#define sal_pss$o_fp127 sal_pss$r_fp_regs_overlay.sal_pss$r_fp_regs_fields.sal_pss$o_fp1 27"#endif /* #if !defined(__VAXC) */ #define SAL_PSS$FRAME_SIZE 5256N/*++ */N/* SAL Processor Device Error Info Section - Module Structure */N/* */N/* SAL 3.0 */V/* "Itanium Processor Family System Abstraction Layer Specification, November 2002" */N/* Section B.2.3, pp . B-5 - B-6 */N/* */N/* (PMS - Processor Module Structure) */N/*-- */!#define SAL_PMS$M_CHECK_VALID 0x1%#define SAL_PMS$M_TARGET_ID_VALID 0x2"#define SAL_PMS$M_REQ_ID_VALID 0x4##define SAL_PMS$M_RESP_ID_VALID 0x8'#define SAL_PMS$M_PRECISE_IP_VALID 0x10 c#if !defin ed(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_pms {#pragma __nomember_alignment __union {) unsigned __int64 sal_pms$q_valid; __struct {/ unsigned sal_pms$v_check_valid : 1;3 unsigned sal_pms$v_target_id_valid : 1;0 unsigned sal_pms$v_req_id_valid : 1;1 unsigned sal_pms$v_r esp_id_valid : 1;4 unsigned sal_pms$v_precise_ip_valid : 1;/ unsigned sal_pms$v_reserved_1 : 32;/ unsigned sal_pms$v_reserved_2 : 27;% } sal_pms$r_valid_fields;" } sal_pms$r_valid_overlay;% unsigned __int64 sal_pms$q_check;) unsigned __int64 sal_pms$q_target_id;& unsigned __int64 sal_pms$q_req_id;' unsigned __int64 sal_pms$q_resp_id;* unsigned __int64 sal_pms$q_precise_ip; } SAL_PMS; #if !defined(__VAXC)?#def ine sal_pms$q_valid sal_pms$r_valid_overlay.sal_pms$q_validb#define sal_pms$v_check_valid sal_pms$r_valid_overlay.sal_pms$r_valid_fields.sal_pms$v_check_validj#define sal_pms$v_target_id_valid sal_pms$r_valid_overlay.sal_pms$r_valid_fields.sal_pms$v_target_id_validd#define sal_pms$v_req_id_valid sal_pms$r_valid_overlay.sal_pms$r_valid_fields.sal_pms$v_req_id_validf#define sal_pms$v_resp_id_valid sal_pms$r_valid_overlay.sal_pms$r_valid_fields.sal_pms$v_resp_id_validl#define sal_pms$v_precise_ip_v alid sal_pms$r_valid_overlay.sal_pms$r_valid_fields.sal_pms$v_precise_ip_valid"#endif /* #if !defined(__VAXC) */ #define SAL_PMS$FRAME_SIZE 48N/*++ */N/* SAL Platform Memory Device Error Info Section - Header Structure */N/* */N/* SAL 3.0 */V/* "Itanium Processor Family Syste m Abstraction Layer Specification, November 2002" */N/* Section B.2.4.1, pp. B-6 - B-7 */N/* */N/* (SMS - System Memory Section) */N/*-- */##define SAL_SMS$M_ERR_STS_VALID 0x1%#define SAL_SMS$M_PHYS_ADDR_VALID 0x2$#define SAL_SMS$M_PHYS_ADDR_MASK 0x4 #define SAL_SMS$ M_NODE_VALID 0x8!#define SAL_SMS$M_CARD_VALID 0x10 #define SAL_SMS$M_MOD_VALID 0x20!#define SAL_SMS$M_BANK_VALID 0x40 #define SAL_SMS$M_DEV_VALID 0x80!#define SAL_SMS$M_ROW_VALID 0x100!#define SAL_SMS$M_COL_VALID 0x200%#define SAL_SMS$M_BIT_POS_VALID 0x400$#define SAL_SMS$M_REQ_ID_VALID 0x800&#define SAL_SMS$M_RESP_ID_VALID 0x1000%#define SAL_SMS$M_TARGET_VALID 0x2000'#define SAL_SMS$M_BUS_DATA_VALID 0x4000%#define SAL_SMS$M_OEM_ID_VALID 0x8000(#define SAL_SMS$M_OEM_DATA_VALID 0x1 0000#define SAL_SMS$M_ADDR 0x10000!#define SAL_SMS$M_CONTROL 0x20000#define SAL_SMS$M_DATA 0x40000#define SAL_SMS$M_RESP 0x80000#define SAL_SMS$M_REQ 0x100000$#define SAL_SMS$M_FIRST_ERR 0x200000##define SAL_SMS$M_OVERFLOW 0x400000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_sms {#pragma __nomember_alignment SAL_ SHD sal_sms$r_sal_shd; __union {) unsigned __int64 sal_sms$q_valid; __struct {1 unsigned sal_sms$v_err_sts_valid : 1;3 unsigned sal_sms$v_phys_addr_valid : 1;2 unsigned sal_sms$v_phys_addr_mask : 1;. unsigned sal_sms$v_node_valid : 1;. unsigned sal_sms$v_card_valid : 1;- unsigned sal_sms$v_mod_valid : 1;. unsigned sal_sms$v_bank_valid : 1;- unsigned sal_sms$v_dev_valid : 1;- unsigned sal_sms$v_row_valid : 1;- unsigned sal_sms$v_col_valid : 1;1 unsigned sal_sms$v_bit_pos_valid : 1;0 unsigned sal_sms$v_req_id_valid : 1;1 unsigned sal_sms$v_resp_id_valid : 1;0 unsigned sal_sms$v_target_valid : 1;2 unsigned sal_sms$v_bus_data_valid : 1;0 unsigned sal_sms$v_oem_id_valid : 1;2 unsigned sal_sms$v_oem_data_valid : 1;/ unsigned sal_sms$v_reserved_1 : 32;/ unsigned sal_sms$v_reserved_2 : 15;% } sal_sms$r_valid_fields;" } sal_sms$r_valid_overlay; __union {+ unsigned __int64 sal_sms$q_err_sts; __struct {- unsigned char sal_sms$b_reserved;5 unsigned char sal_sms$b_encoded_err_type;( unsigned sal_sms$v_addr : 1;+ unsigned sal_sms$v_control : 1;( unsigned sal_sms$v_data : 1;( unsigned sal_sms$v_resp : 1;' unsigned sal _sms$v_req : 1;- unsigned sal_sms$v_first_err : 1;, unsigned sal_sms$v_overflow : 1;1 unsigned sal_sms$v_reserved_1_1 : 32;0 unsigned sal_sms$v_reserved_1_2 : 9;' } sal_sms$r_err_sts_fields;$ } sal_sms$r_err_sts_overlay;) unsigned __int64 sal_sms$q_phys_addr;. unsigned __int64 sal_sms$q_phys_addr_mask;& unsigned short int sal_sms$w_node;& unsigned short int sal_sms$w_card;% unsigned short int sal_sms$w_mod;& unsigned short int sal_sms$w_bank;% unsigned short int sal_sms$w_dev;% unsigned short int sal_sms$w_row;% unsigned short int sal_sms$w_col;) unsigned short int sal_sms$w_bit_pos;& unsigned __int64 sal_sms$q_req_id;' unsigned __int64 sal_sms$q_resp_id;) unsigned __int64 sal_sms$q_target_id;( unsigned __int64 sal_sms$q_bus_data; __union {* unsigned int sal_sms$o_oem_id [4]; __struct {0 unsigned __int64 sal_sms$q_oem_id_l;0 unsigned __int64 sal_sms$q_oem_id_h;& } sal_sms$r_oem_id_fields;# } sal_sms$r_oem_id_overlay; } SAL_SMS; #if !defined(__VAXC)f#define sal_sms$v_err_sts_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_err_sts_validj#define sal_sms$v_phys_addr_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_phys_addr_validh#define sal_sms$v_phys_addr_mask sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_phys_addr_mask`#define sal_sms$v_no de_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_node_valid`#define sal_sms$v_card_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_card_valid^#define sal_sms$v_mod_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_mod_valid`#define sal_sms$v_bank_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_bank_valid^#define sal_sms$v_dev_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_dev_valid^#define sal_sms$v_row_valid sal_sms$r_va lid_overlay.sal_sms$r_valid_fields.sal_sms$v_row_valid^#define sal_sms$v_col_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_col_validf#define sal_sms$v_bit_pos_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_bit_pos_validd#define sal_sms$v_req_id_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_req_id_validf#define sal_sms$v_resp_id_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_resp_id_validd#define sal_sms$v_target_valid sal_sms$r_val id_overlay.sal_sms$r_valid_fields.sal_sms$v_target_validh#define sal_sms$v_bus_data_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_bus_data_validd#define sal_sms$v_oem_id_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_oem_id_validh#define sal_sms$v_oem_data_valid sal_sms$r_valid_overlay.sal_sms$r_valid_fields.sal_sms$v_oem_data_validE#define sal_sms$q_err_sts sal_sms$r_err_sts_overlay.sal_sms$q_err_stsp#define sal_sms$b_encoded_err_type sal_sms$r_err_sts_overlay.s al_sms$r_err_sts_fields.sal_sms$b_encoded_err_typeX#define sal_sms$v_addr sal_sms$r_err_sts_overlay.sal_sms$r_err_sts_fields.sal_sms$v_addr^#define sal_sms$v_control sal_sms$r_err_sts_overlay.sal_sms$r_err_sts_fields.sal_sms$v_controlX#define sal_sms$v_data sal_sms$r_err_sts_overlay.sal_sms$r_err_sts_fields.sal_sms$v_dataX#define sal_sms$v_resp sal_sms$r_err_sts_overlay.sal_sms$r_err_sts_fields.sal_sms$v_respV#define sal_sms$v_req sal_sms$r_err_sts_overlay.sal_sms$r_err_sts_fields.sal_sms$v_reqb #define sal_sms$v_first_err sal_sms$r_err_sts_overlay.sal_sms$r_err_sts_fields.sal_sms$v_first_err`#define sal_sms$v_overflow sal_sms$r_err_sts_overlay.sal_sms$r_err_sts_fields.sal_sms$v_overflowB#define sal_sms$o_oem_id sal_sms$r_oem_id_overlay.sal_sms$o_oem_id^#define sal_sms$q_oem_id_l sal_sms$r_oem_id_overlay.sal_sms$r_oem_id_fields.sal_sms$q_oem_id_l^#define sal_sms$q_oem_id_h sal_sms$r_oem_id_overlay.sal_sms$r_oem_id_fields.sal_sms$q_oem_id_h"#endif /* #if !defined(__VAXC) */ #define  SAL_SMS$FRAME_SIZE 120N/*++ */N/* SAL Platform PCI Bus Error Info Section - Header Structure */N/* */N/* SAL 3.0 */V/* "Itanium Processor Family System Abstraction Layer Specification, November 2002" */N/* Section B.2.4.2, pp. B-8 - B-9 */N/* */N/* (SPCIBS - System PCI Bus Section) */N/*-- */&#define SAL_SPCIBS$M_ERR_STS_VALID 0x1'#define SAL_SPCIBS$M_ERR_TYPE_VALID 0x2!#define SAL_SPCIBS$M_ID_VALID 0x4##define SAL_SPCIBS$M_ADDR_VALID 0x8$#define SAL_SPCIBS$M_DATA_VALID 0x10##define SAL_SPCIBS$M_CMD_VALID 0x20&#define SAL_SPCIBS$M_REQ_ID_ VALID 0x40(#define SAL_SPCIBS$M_COMPL_ID_VALID 0x80*#define SAL_SPCIBS$M_TARGET_ID_VALID 0x100'#define SAL_SPCIBS$M_OEM_ID_VALID 0x200)#define SAL_SPCIBS$M_OEM_DATA_VALID 0x400!#define SAL_SPCIBS$M_ADDR 0x10000$#define SAL_SPCIBS$M_CONTROL 0x20000!#define SAL_SPCIBS$M_DATA 0x40000!#define SAL_SPCIBS$M_RESP 0x80000!#define SAL_SPCIBS$M_REQ 0x100000'#define SAL_SPCIBS$M_FIRST_ERR 0x200000&#define SAL_SPCIBS$M_OVERFLOW 0x400000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cpl usplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_spcibs {#pragma __nomember_alignment! SAL_SHD sal_spcibs$r_sal_shd; __union {, unsigned __int64 sal_spcibs$q_valid; __struct {4 unsigned sal_spcibs$v_err_sts_valid : 1;5 unsigned sal_spcibs$v_err_type_valid : 1;/ unsigned sal_spcibs$v_id_valid : 1;1 unsigned sal_spcib s$v_addr_valid : 1;1 unsigned sal_spcibs$v_data_valid : 1;0 unsigned sal_spcibs$v_cmd_valid : 1;3 unsigned sal_spcibs$v_req_id_valid : 1;5 unsigned sal_spcibs$v_compl_id_valid : 1;6 unsigned sal_spcibs$v_target_id_valid : 1;3 unsigned sal_spcibs$v_oem_id_valid : 1;5 unsigned sal_spcibs$v_oem_data_valid : 1;2 unsigned sal_spcibs$v_reserved_1 : 32;2 unsigned sal_spcibs$v_reserved_2 : 21;( } sal_spcibs$r_valid_fields;% } sal_spcibs$r_valid_overlay; __union {. unsigned __int64 sal_spcibs$q_err_sts; __struct {0 unsigned char sal_spcibs$b_reserved;8 unsigned char sal_spcibs$b_encoded_err_type;+ unsigned sal_spcibs$v_addr : 1;. unsigned sal_spcibs$v_control : 1;+ unsigned sal_spcibs$v_data : 1;+ unsigned sal_spcibs$v_resp : 1;* unsigned sal_spcibs$v_req : 1;0 unsigned sal_spcibs$v_first_err : 1;/ unsigned sal_spcibs$v_overflow : 1;4 unsigned sal_spcibs$v_reserved_1_1 : 32;3 unsigned sal_spcibs$v_reserved_1_2 : 9;* } sal_spcibs$r_err_sts_fields;' } sal_spcibs$r_err_sts_overlay;- unsigned short int sal_spcibs$w_err_type; __union {+ unsigned short int sal_spcibs$w_id; __struct {/ unsigned char sal_spcibs$b_bus_num;/ unsigned char sal_sp cibs$b_seg_num;% } sal_spcibs$r_id_fields;" } sal_spcibs$r_id_overlay;) unsigned int sal_spcibs$l_reserved_1;' unsigned __int64 sal_spcibs$q_addr;' unsigned __int64 sal_spcibs$q_data;& unsigned __int64 sal_spcibs$q_cmd;) unsigned __int64 sal_spcibs$q_req_id;+ unsigned __int64 sal_spcibs$q_compl_id;, unsigned __int64 sal_spcibs$q_target_id; __union {- unsigned int sal_spcibs$o_oem_id [4]; __struct {3 unsigned _ _int64 sal_spcibs$q_oem_id_l;3 unsigned __int64 sal_spcibs$q_oem_id_h;) } sal_spcibs$r_oem_id_fields;& } sal_spcibs$r_oem_id_overlay; } SAL_SPCIBS; #if !defined(__VAXC)H#define sal_spcibs$q_valid sal_spcibs$r_valid_overlay.sal_spcibs$q_validr#define sal_spcibs$v_err_sts_valid sal_spcibs$r_valid_overlay.sal_spcibs$r_valid_fields.sal_spcibs$v_err_sts_validt#define sal_spcibs$v_err_type_valid sal_spcibs$r_valid_overlay.sal_spcibs$r_valid_fields.sal_spcibs$ v_err_type_validh#define sal_spcibs$v_id_valid sal_spcibs$r_valid_overlay.sal_spcibs$r_valid_fields.sal_spcibs$v_id_validl#define sal_spcibs$v_addr_valid sal_spcibs$r_valid_overlay.sal_spcibs$r_valid_fields.sal_spcibs$v_addr_validl#define sal_spcibs$v_data_valid sal_spcibs$r_valid_overlay.sal_spcibs$r_valid_fields.sal_spcibs$v_data_validj#define sal_spcibs$v_cmd_valid sal_spcibs$r_valid_overlay.sal_spcibs$r_valid_fields.sal_spcibs$v_cmd_validp#define sal_spcibs$v_req_id_valid sal_spcibs$r_valid_o verlay.sal_spcibs$r_valid_fields.sal_spcibs$v_req_id_validt#define sal_spcibs$v_compl_id_valid sal_spcibs$r_valid_overlay.sal_spcibs$r_valid_fields.sal_spcibs$v_compl_id_validv#define sal_spcibs$v_target_id_valid sal_spcibs$r_valid_overlay.sal_spcibs$r_valid_fields.sal_spcibs$v_target_id_validp#define sal_spcibs$v_oem_id_valid sal_spcibs$r_valid_overlay.sal_spcibs$r_valid_fields.sal_spcibs$v_oem_id_validt#define sal_spcibs$v_oem_data_valid sal_spcibs$r_valid_overlay.sal_spcibs$r_valid_fields.sal_s pcibs$v_oem_data_validN#define sal_spcibs$q_err_sts sal_spcibs$r_err_sts_overlay.sal_spcibs$q_err_sts|#define sal_spcibs$b_encoded_err_type sal_spcibs$r_err_sts_overlay.sal_spcibs$r_err_sts_fields.sal_spcibs$b_encoded_err_typed#define sal_spcibs$v_addr sal_spcibs$r_err_sts_overlay.sal_spcibs$r_err_sts_fields.sal_spcibs$v_addrj#define sal_spcibs$v_control sal_spcibs$r_err_sts_overlay.sal_spcibs$r_err_sts_fields.sal_spcibs$v_controld#define sal_spcibs$v_data sal_spcibs$r_err_sts_overlay.sal_spcibs$ r_err_sts_fields.sal_spcibs$v_datad#define sal_spcibs$v_resp sal_spcibs$r_err_sts_overlay.sal_spcibs$r_err_sts_fields.sal_spcibs$v_respb#define sal_spcibs$v_req sal_spcibs$r_err_sts_overlay.sal_spcibs$r_err_sts_fields.sal_spcibs$v_reqn#define sal_spcibs$v_first_err sal_spcibs$r_err_sts_overlay.sal_spcibs$r_err_sts_fields.sal_spcibs$v_first_errl#define sal_spcibs$v_overflow sal_spcibs$r_err_sts_overlay.sal_spcibs$r_err_sts_fields.sal_spcibs$v_overflow?#define sal_spcibs$w_id sal_spcibs$r_id_overla y.sal_spcibs$w_id`#define sal_spcibs$b_bus_num sal_spcibs$r_id_overlay.sal_spcibs$r_id_fields.sal_spcibs$b_bus_num`#define sal_spcibs$b_seg_num sal_spcibs$r_id_overlay.sal_spcibs$r_id_fields.sal_spcibs$b_seg_numK#define sal_spcibs$o_oem_id sal_spcibs$r_oem_id_overlay.sal_spcibs$o_oem_idj#define sal_spcibs$q_oem_id_l sal_spcibs$r_oem_id_overlay.sal_spcibs$r_oem_id_fields.sal_spcibs$q_oem_id_lj#define sal_spcibs$q_oem_id_h sal_spcibs$r_oem_id_overlay.sal_spcibs$r_oem_id_fields.sal_spcibs$q_oem_id _h"#endif /* #if !defined(__VAXC) */ !#define SAL_SPCIBS$FRAME_SIZE 112N/*++ */N/* SAL Platform PCI Component Error Info Section - Header Structure */N/* */N/* SAL 3.0 */V/* "Itanium Processor Family System Abstraction Layer Specification, November 2002" */N/* Section B.2.4.3 , pp. B-9 - B-10 */N/* */N/* (SPCICS - System PCI Component Section) */N/*-- */&#define SAL_SPCICS$M_ERR_STS_VALID 0x1##define SAL_SPCICS$M_DATA_VALID 0x2&#define SAL_SPCICS$M_MEM_NUM_VALID 0x4%#define SAL_SPCICS$M_IO_NUM_VALID 0x8.#define SAL_SPCICS$M_REGS_DATA_PAIR_VALID 0x10 (#define SAL_SPCICS$M_OEM_DATA_VALID 0x20!#define SAL_SPCICS$M_ADDR 0x10000$#define SAL_SPCICS$M_CONTROL 0x20000!#define SAL_SPCICS$M_DATA 0x40000!#define SAL_SPCICS$M_RESP 0x80000!#define SAL_SPCICS$M_REQ 0x100000'#define SAL_SPCICS$M_FIRST_ERR 0x200000&#define SAL_SPCICS$M_OVERFLOW 0x400000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftype def struct _sal_spcics {#pragma __nomember_alignment! SAL_SHD sal_spcics$r_sal_shd; __union {, unsigned __int64 sal_spcics$q_valid; __struct {4 unsigned sal_spcics$v_err_sts_valid : 1;1 unsigned sal_spcics$v_data_valid : 1;4 unsigned sal_spcics$v_mem_num_valid : 1;3 unsigned sal_spcics$v_io_num_valid : 1;; unsigned sal_spcics$v_regs_data_pair_valid : 1;5 unsigned sal_spcics$v_oem_data_valid : 1; 2 unsigned sal_spcics$v_reserved_1 : 32;2 unsigned sal_spcics$v_reserved_2 : 26;( } sal_spcics$r_valid_fields;% } sal_spcics$r_valid_overlay; __union {. unsigned __int64 sal_spcics$q_err_sts; __struct {0 unsigned char sal_spcics$b_reserved;8 unsigned char sal_spcics$b_encoded_err_type;+ unsigned sal_spcics$v_addr : 1;. unsigned sal_spcics$v_control : 1;+ unsigned sal_spcic s$v_data : 1;+ unsigned sal_spcics$v_resp : 1;* unsigned sal_spcics$v_req : 1;0 unsigned sal_spcics$v_first_err : 1;/ unsigned sal_spcics$v_overflow : 1;4 unsigned sal_spcics$v_reserved_1_1 : 32;3 unsigned sal_spcics$v_reserved_1_2 : 9;* } sal_spcics$r_err_sts_fields;' } sal_spcics$r_err_sts_overlay; __union {/ unsigned int sal_spcics$o_pci_comp [4]; __struct {6 unsign ed short int sal_spcics$w_vendor_id;3 unsigned short int sal_spcics$w_dev_id;; unsigned short int sal_spcics$w_class_code [3];0 unsigned char sal_spcics$b_func_num;/ unsigned char sal_spcics$b_dev_num;/ unsigned char sal_spcics$b_bus_num;/ unsigned char sal_spcics$b_seg_num;6 unsigned char sal_spcics$b_reserved_1 [5];+ } sal_spcics$r_pci_comp_fields;( } sal_spcics$r_pci_comp_overlay;& unsi gned int sal_spcics$l_mem_num;% unsigned int sal_spcics$l_io_num;" char sal_spcics$b_fill_0_ [5]; } SAL_SPCICS; #if !defined(__VAXC)H#define sal_spcics$q_valid sal_spcics$r_valid_overlay.sal_spcics$q_validr#define sal_spcics$v_err_sts_valid sal_spcics$r_valid_overlay.sal_spcics$r_valid_fields.sal_spcics$v_err_sts_validl#define sal_spcics$v_data_valid sal_spcics$r_valid_overlay.sal_spcics$r_valid_fields.sal_spcics$v_data_validr#define sal_spcics$v_mem_num_valid sal_spcics$r_vali d_overlay.sal_spcics$r_valid_fields.sal_spcics$v_mem_num_validp#define sal_spcics$v_io_num_valid sal_spcics$r_valid_overlay.sal_spcics$r_valid_fields.sal_spcics$v_io_num_valid#define sal_spcics$v_regs_data_pair_valid sal_spcics$r_valid_overlay.sal_spcics$r_valid_fields.sal_spcics$v_regs_data_pair_validt#define sal_spcics$v_oem_data_valid sal_spcics$r_valid_overlay.sal_spcics$r_valid_fields.sal_spcics$v_oem_data_validN#define sal_spcics$q_err_sts sal_spcics$r_err_sts_overlay.sal_spcics$q_err_sts| #define sal_spcics$b_encoded_err_type sal_spcics$r_err_sts_overlay.sal_spcics$r_err_sts_fields.sal_spcics$b_encoded_err_typed#define sal_spcics$v_addr sal_spcics$r_err_sts_overlay.sal_spcics$r_err_sts_fields.sal_spcics$v_addrj#define sal_spcics$v_control sal_spcics$r_err_sts_overlay.sal_spcics$r_err_sts_fields.sal_spcics$v_controld#define sal_spcics$v_data sal_spcics$r_err_sts_overlay.sal_spcics$r_err_sts_fields.sal_spcics$v_datad#define sal_spcics$v_resp sal_spcics$r_err_sts_overlay.sal_spcics$r_ err_sts_fields.sal_spcics$v_respb#define sal_spcics$v_req sal_spcics$r_err_sts_overlay.sal_spcics$r_err_sts_fields.sal_spcics$v_reqn#define sal_spcics$v_first_err sal_spcics$r_err_sts_overlay.sal_spcics$r_err_sts_fields.sal_spcics$v_first_errl#define sal_spcics$v_overflow sal_spcics$r_err_sts_overlay.sal_spcics$r_err_sts_fields.sal_spcics$v_overflowQ#define sal_spcics$o_pci_comp sal_spcics$r_pci_comp_overlay.sal_spcics$o_pci_compp#define sal_spcics$w_vendor_id sal_spcics$r_pci_comp_overlay.sal_s pcics$r_pci_comp_fields.sal_spcics$w_vendor_idj#define sal_spcics$w_dev_id sal_spcics$r_pci_comp_overlay.sal_spcics$r_pci_comp_fields.sal_spcics$w_dev_idr#define sal_spcics$w_class_code sal_spcics$r_pci_comp_overlay.sal_spcics$r_pci_comp_fields.sal_spcics$w_class_coden#define sal_spcics$b_func_num sal_spcics$r_pci_comp_overlay.sal_spcics$r_pci_comp_fields.sal_spcics$b_func_numl#define sal_spcics$b_dev_num sal_spcics$r_pci_comp_overlay.sal_spcics$r_pci_comp_fields.sal_spcics$b_dev_numl#define sal_ spcics$b_bus_num sal_spcics$r_pci_comp_overlay.sal_spcics$r_pci_comp_fields.sal_spcics$b_bus_numl#define sal_spcics$b_seg_num sal_spcics$r_pci_comp_overlay.sal_spcics$r_pci_comp_fields.sal_spcics$b_seg_num"#endif /* #if !defined(__VAXC) */ #define SAL_SPCICS$FRAME_SIZE 72N/*++ */N/* SAL Platform SEL Device Error Info Section */N/*  */N/* SAL 3.0 */V/* "Itanium Processor Family System Abstraction Layer Specification, November 2002" */N/* Section B.2.4.4, pp. B-10 - B-11 */N/* */N/* (SSELS - System SEL Section) */N/*-- */$#d efine SAL_SSELS$M_REC_ID_VALID 0x1&#define SAL_SSELS$M_REC_TYPE_VALID 0x2'#define SAL_SSELS$M_TIMESTAMP_VALID 0x4&#define SAL_SSELS$M_GEN_TYPE_VALID 0x8&#define SAL_SSELS$M_EVM_REV_VALID 0x10(#define SAL_SSELS$M_SENS_TYPE_VALID 0x20'#define SAL_SSELS$M_SENS_NUM_VALID 0x40-#define SAL_SSELS$M_EVENT_DIR_TYPE_VALID 0x80+#define SAL_SSELS$M_EVENT_DATA1_VALID 0x100+#define SAL_SSELS$M_EVENT_DATA2_VALID 0x200+#define SAL_SSELS$M_EVENT_DATA3_VALID 0x400'#define SAL_SSELS$M_SYS_SW_ID_VALID 0x 1$#define SAL_SSELS$M_DEASSERTION 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_ssels {#pragma __nomember_alignment SAL_SHD sal_ssels$r_sal_shd; __union {+ unsigned __int64 sal_ssels$q_valid; __struct {2 unsigned sal_ssels$v_rec_id_valid : 1;4 unsigned sal_ssels$v_rec_typ e_valid : 1;5 unsigned sal_ssels$v_timestamp_valid : 1;4 unsigned sal_ssels$v_gen_type_valid : 1;3 unsigned sal_ssels$v_evm_rev_valid : 1;5 unsigned sal_ssels$v_sens_type_valid : 1;4 unsigned sal_ssels$v_sens_num_valid : 1;: unsigned sal_ssels$v_event_dir_type_valid : 1;7 unsigned sal_ssels$v_event_data1_valid : 1;7 unsigned sal_ssels$v_event_data2_valid : 1;7 unsigned sal_ssels$v_event_dat a3_valid : 1;1 unsigned sal_ssels$v_reserved_1 : 32;1 unsigned sal_ssels$v_reserved_2 : 21;' } sal_ssels$r_valid_fields;$ } sal_ssels$r_valid_overlay;* unsigned short int sal_ssels$w_rec_id;' unsigned char sal_ssels$b_rec_type;' unsigned int sal_ssels$l_timestamp; __union {. unsigned short int sal_ssels$w_gen_id; __struct { __union {3 unsigned char sal_ssels$b_gen_id_l; __struct {= unsigned sal_ssels$v_sys_sw_id_valid : 1;7 unsigned sal_ssels$v_sys_sw_id : 7;2 } sal_ssels$r_gen_id_l_fields;/ } sal_ssels$r_gen_id_l_overlay; __union {3 unsigned char sal_ssels$b_gen_id_h; __struct {: unsigned sal_ssels$v_ipmb_dev_lun : 2;8 unsigned sal_ssels$v_reserved_1 : 6;2 } sal_ssels$r_gen_id _h_fields;/ } sal_ssels$r_gen_id_h_overlay;( } sal_ssels$r_gen_id_fields;% } sal_ssels$r_gen_id_overlay;& unsigned char sal_ssels$b_evm_rev;( unsigned char sal_ssels$b_sens_type;' unsigned char sal_ssels$b_sens_num; __union {1 unsigned char sal_ssels$b_event_dir_type; __struct {5 unsigned sal_ssels$v_event_type_code : 7;1 unsigned sal_ssels$v_deassertion : 1;0 } sal_ssels$r_event_dir_type _fields;- } sal_ssels$r_event_dir_type_overlay;* unsigned char sal_ssels$b_event_data1;* unsigned char sal_ssels$b_event_data2;* unsigned char sal_ssels$b_event_data3; } SAL_SSELS; #if !defined(__VAXC)E#define sal_ssels$q_valid sal_ssels$r_valid_overlay.sal_ssels$q_validl#define sal_ssels$v_rec_id_valid sal_ssels$r_valid_overlay.sal_ssels$r_valid_fields.sal_ssels$v_rec_id_validp#define sal_ssels$v_rec_type_valid sal_ssels$r_valid_overlay.sal_ssels$r_valid_fields.sal_ ssels$v_rec_type_validr#define sal_ssels$v_timestamp_valid sal_ssels$r_valid_overlay.sal_ssels$r_valid_fields.sal_ssels$v_timestamp_validp#define sal_ssels$v_gen_type_valid sal_ssels$r_valid_overlay.sal_ssels$r_valid_fields.sal_ssels$v_gen_type_validn#define sal_ssels$v_evm_rev_valid sal_ssels$r_valid_overlay.sal_ssels$r_valid_fields.sal_ssels$v_evm_rev_validr#define sal_ssels$v_sens_type_valid sal_ssels$r_valid_overlay.sal_ssels$r_valid_fields.sal_ssels$v_sens_type_validp#define sal_ssels$v_sens _num_valid sal_ssels$r_valid_overlay.sal_ssels$r_valid_fields.sal_ssels$v_sens_num_valid|#define sal_ssels$v_event_dir_type_valid sal_ssels$r_valid_overlay.sal_ssels$r_valid_fields.sal_ssels$v_event_dir_type_validv#define sal_ssels$v_event_data1_valid sal_ssels$r_valid_overlay.sal_ssels$r_valid_fields.sal_ssels$v_event_data1_validv#define sal_ssels$v_event_data2_valid sal_ssels$r_valid_overlay.sal_ssels$r_valid_fields.sal_ssels$v_event_data2_validv#define sal_ssels$v_event_data3_valid sal_ssels$r_ valid_overlay.sal_ssels$r_valid_fields.sal_ssels$v_event_data3_validH#define sal_ssels$w_gen_id sal_ssels$r_gen_id_overlay.sal_ssels$w_gen_id#define sal_ssels$b_gen_id_l sal_ssels$r_gen_id_overlay.sal_ssels$r_gen_id_fields.sal_ssels$r_gen_id_l_overlay.sal_ssels$b_gen_id_l#define sal_ssels$v_sys_sw_id_valid sal_ssels$r_gen_id_overlay.sal_ssels$r_gen_id_fields.sal_ssels$r_gen_id_l_overlay.sal_ssels$r_g\*en_id_l_fields.sal_ssels$v_sys_sw_id_valid#define sal_ssels$v_sys_sw_id sal_ssels$r_gen_id_o verlay.sal_ssels$r_gen_id_fields.sal_ssels$r_gen_id_l_overlay.sal_ssels$r_gen_id_\l_fields.sal_ssels$v_sys_sw_id#define sal_ssels$b_gen_id_h sal_ssels$r_gen_id_overlay.sal_ssels$r_gen_id_fields.sal_ssels$r_gen_id_h_overlay.sal_ssels$b_gen_id_h#define sal_ssels$v_ipmb_dev_lun sal_ssels$r_gen_id_overlay.sal_ssels$r_gen_id_fields.sal_ssels$r_gen_id_h_overlay.sal_ssels$r_gen_\$id_h_fields.sal_ssels$v_ipmb_dev_lun`#define sal_ssels$b_event_dir_type sal_ssels$r_event_dir_type_overlay.sal_ssels$b_ev ent_dir_type#define sal_ssels$v_event_type_code sal_ssels$r_event_dir_type_overlay.sal_ssels$r_event_dir_type_fields.sal_ssels$v_event_type_code|#define sal_ssels$v_deassertion sal_ssels$r_event_dir_type_overlay.sal_ssels$r_event_dir_type_fields.sal_ssels$v_deassertion"#endif /* #if !defined(__VAXC) */ #define SAL_SSELS$FRAME_SIZE 48N/*++ */N/* SAL SMBIOS Device Error Info Section - Header Structure */ N/* */N/* SAL 3.0 */V/* "Itanium Processor Family System Abstraction Layer Specification, November 2002" */N/* Section B.2.4.5, pp. B-11 */N/* */N/* (SSMBIOSS - System SMBIOS Section) */N/*--  */+#define SAL_SSMBIOSS$M_EVENT_TYPE_VALID 0x1$#define SAL_SSMBIOSS$M_LEN_VALID 0x2*#define SAL_SSMBIOSS$M_TIMESTAMP_VALID 0x4%#define SAL_SSMBIOSS$M_DATA_VALID 0x8 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_ssmbioss {#pragma __nomember_alignment# SAL_SHD sal_ss mbioss$r_sal_shd; __union {. unsigned __int64 sal_ssmbioss$q_valid; __struct {9 unsigned sal_ssmbioss$v_event_type_valid : 1;2 unsigned sal_ssmbioss$v_len_valid : 1;8 unsigned sal_ssmbioss$v_timestamp_valid : 1;3 unsigned sal_ssmbioss$v_data_valid : 1;4 unsigned sal_ssmbioss$v_reserved_1 : 32;4 unsigned sal_ssmbioss$v_reserved_2 : 28;* } sal_ssmbioss$r_valid_fields;' } sal_ssmbioss$r _valid_overlay;, unsigned char sal_ssmbioss$b_event_type;% unsigned char sal_ssmbioss$b_len;/ unsigned char sal_ssmbioss$b_timestamp [6]; } SAL_SSMBIOSS; #if !defined(__VAXC)N#define sal_ssmbioss$q_valid sal_ssmbioss$r_valid_overlay.sal_ssmbioss$q_valid#define sal_ssmbioss$v_event_type_valid sal_ssmbioss$r_valid_overlay.sal_ssmbioss$r_valid_fields.sal_ssmbioss$v_event_type_validr#define sal_ssmbioss$v_len_valid sal_ssmbioss$r_valid_overlay.sal_ssmbioss$r_valid_fields.sal_ ssmbioss$v_len_valid~#define sal_ssmbioss$v_timestamp_valid sal_ssmbioss$r_valid_overlay.sal_ssmbioss$r_valid_fields.sal_ssmbioss$v_timestamp_validt#define sal_ssmbioss$v_data_valid sal_ssmbioss$r_valid_overlay.sal_ssmbioss$r_valid_fields.sal_ssmbioss$v_data_valid"#endif /* #if !defined(__VAXC) */ "#define SAL_SSMBIOSS$FRAME_SIZE 40N/*++ */N/* SAL Specific Error Info Section - Header Structure */N/* */N/* SAL 3.0 */V/* "Itanium Processor Family System Abstraction Layer Specification, November 2002" */N/* Section B.2.4.6, pp. B-11 - B-12 */N/* */N/* (SOEMS - System OEM Section) */N/*-- */%#define SAL_SOEMS$M_ERR_STS_VALID 0x1$#define SAL_SOEMS$M_REQ_ID_VALID 0x2%#define SAL_SOEMS$M_RESP_ID_VALID 0x4'#define SAL_SOEMS$M_TARGET_ID_VALID 0x8,#define SAL_SOEMS$M_SYS_SPEC_DATA_VALID 0x10%#define SAL_SOEMS$M_OEM_ID_VALID 0x20'#define SAL_SOEMS$M_OEM_DATA_VALID 0x40+#define SAL_SOEMS$M_OEM_DEV_PATH_VALID 0x80 #define SAL_SOEMS$M_ADDR 0x10000##define SAL_SOEMS$M_CONTROL 0x20000 #define SAL_SOEMS$M_DATA 0x40000 #defin e SAL_SOEMS$M_RESP 0x80000 #define SAL_SOEMS$M_REQ 0x100000&#define SAL_SOEMS$M_FIRST_ERR 0x200000%#define SAL_SOEMS$M_OVERFLOW 0x400000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_soems {#pragma __nomember_alignment SAL_SHD sal_soems$r_sal_shd; __union {+ unsigned __int64 sal_soems$q_valid; __stru ct {3 unsigned sal_soems$v_err_sts_valid : 1;2 unsigned sal_soems$v_req_id_valid : 1;3 unsigned sal_soems$v_resp_id_valid : 1;5 unsigned sal_soems$v_target_id_valid : 1;9 unsigned sal_soems$v_sys_spec_data_valid : 1;2 unsigned sal_soems$v_oem_id_valid : 1;4 unsigned sal_soems$v_oem_data_valid : 1;8 unsigned sal_soems$v_oem_dev_path_valid : 1;1 unsigned sal_soems$v_reserved_1 : 32;1 unsigned sal_soems$v_reserved_2 : 24;' } sal_soems$r_valid_fields;$ } sal_soems$r_valid_overlay; __union {- unsigned __int64 sal_soems$q_err_sts; __struct {/ unsigned char sal_soems$b_reserved;7 unsigned char sal_soems$b_encoded_err_type;* unsigned sal_soems$v_addr : 1;- unsigned sal_soems$v_control : 1;* unsigned sal_soems$v_data : 1;* unsigned sal_soems$v_resp : 1;) unsigned sal_soems$v_req : 1;/ unsigned sal_soems$v_first_err : 1;. unsigned sal_soems$v_overflow : 1;3 unsigned sal_soems$v_reserved_1_1 : 32;2 unsigned sal_soems$v_reserved_1_2 : 9;) } sal_soems$r_err_sts_fields;& } sal_soems$r_err_sts_overlay;( unsigned __int64 sal_soems$q_req_id;) unsigned __int64 sal_soems$q_resp_id;+ unsigned __int64 sal_soems$q_target_id;/ unsigned __int64 sal_soems$q_bus_spec_data;  __union {1 unsigned int sal_soems$o_oem_comp_id [4]; __struct {7 unsigned __int64 sal_soems$q_oem_comp_id_l;7 unsigned __int64 sal_soems$q_oem_comp_id_h;- } sal_soems$r_oem_comp_id_fields;* } sal_soems$r_oem_comp_id_overlay; } SAL_SOEMS; #if !defined(__VAXC)E#define sal_soems$q_valid sal_soems$r_valid_overlay.sal_soems$q_validn#define sal_soems$v_err_sts_valid sal_soems$r_valid_overlay.sal_soems$r_valid_fields.sal_s oems$v_err_sts_validl#define sal_soems$v_req_id_valid sal_soems$r_valid_overlay.sal_soems$r_valid_fields.sal_soems$v_req_id_validn#define sal_soems$v_resp_id_valid sal_soems$r_valid_overlay.sal_soems$r_valid_fields.sal_soems$v_resp_id_validr#define sal_soems$v_target_id_valid sal_soems$r_valid_overlay.sal_soems$r_valid_fields.sal_soems$v_target_id_validz#define sal_soems$v_sys_spec_data_valid sal_soems$r_valid_overlay.sal_soems$r_valid_fields.sal_soems$v_sys_spec_data_validl#define sal_soems$v_oe m_id_valid sal_soems$r_valid_overlay.sal_soems$r_valid_fields.sal_soems$v_oem_id_validp#define sal_soems$v_oem_data_valid sal_soems$r_valid_overlay.sal_soems$r_valid_fields.sal_soems$v_oem_data_validx#define sal_soems$v_oem_dev_path_valid sal_soems$r_valid_overlay.sal_soems$r_valid_fields.sal_soems$v_oem_dev_path_validK#define sal_soems$q_err_sts sal_soems$r_err_sts_overlay.sal_soems$q_err_stsx#define sal_soems$b_encoded_err_type sal_soems$r_err_sts_overlay.sal_soems$r_err_sts_fields.sal_soems$b_ encoded_err_type`#define sal_soems$v_addr sal_soems$r_err_sts_overlay.sal_soems$r_err_sts_fields.sal_soems$v_addrf#define sal_soems$v_control sal_soems$r_err_sts_overlay.sal_soems$r_err_sts_fields.sal_soems$v_control`#define sal_soems$v_data sal_soems$r_err_sts_overlay.sal_soems$r_err_sts_fields.sal_soems$v_data`#define sal_soems$v_resp sal_soems$r_err_sts_overlay.sal_soems$r_err_sts_fields.sal_soems$v_resp^#define sal_soems$v_req sal_soems$r_err_sts_overlay.sal_soems$r_err_sts_fields.sal_soems$v _reqj#define sal_soems$v_first_err sal_soems$r_err_sts_overlay.sal_soems$r_err_sts_fields.sal_soems$v_first_errh#define sal_soems$v_overflow sal_soems$r_err_sts_overlay.sal_soems$r_err_sts_fields.sal_soems$v_overflowW#define sal_soems$o_oem_comp_id sal_soems$r_oem_comp_id_overlay.sal_soems$o_oem_comp_idz#define sal_soems$q_oem_comp_id_l sal_soems$r_oem_comp_id_overlay.sal_soems$r_oem_comp_id_fields.sal_soems$q_oem_comp_id_lz#define sal_soems$q_oem_comp_id_h sal_soems$r_oem_comp_id_overlay.sal_so ems$r_oem_comp_id_fields.sal_soems$q_oem_comp_id_h"#endif /* #if !defined(__VAXC) */ #define SAL_SOEMS$FRAME_SIZE 88N/*++ */N/* CER_STAT Field */N/*-- */#define CER_STAT$M_PCER 0x8#define CER_STAT$M_SCER 0x10#define CER_STAT$M_PCEL 0x100#define CER_STAT$M_SCEL 0x1 typedef struct _cer_stat { __union {) unsigned int cer_stat$l_cpu_stat; __struct {N unsigned cer_stat$v_reserved_1 : 3; /* [2:0] */N unsigned cer_stat$v_pcer : 1; /* [3] */N unsigned cer_stat$v_scer : 1; /* [4] */N unsigned cer_stat$v_reserved_2 : 3; /* [7:5] */N unsigned cer_stat$v_pcel : 1; /* [8] */N unsigned cer_stat$v_reserved_3 : 23; /* [31:9] */) } cer_stat$r_cpu_stat_fields;& } cer_stat$r_cpu_stat_overlay; __union {) unsigned int cer_stat$l_sys_stat; __struct {N unsigned cer_stat$v_scel : 1; /* [32] */N unsigned cer_stat$v_reserved_4 : 31; /* [63:33] */) } cer_stat$r_sys_stat_fields;& } cer_stat$r_sys_stat_overlay; } CER_STAT; #if  !defined(__VAXC)K#define cer_stat$l_cpu_stat cer_stat$r_cpu_stat_overlay.cer_stat$l_cpu_stat^#define cer_stat$v_pcer cer_stat$r_cpu_stat_overlay.cer_stat$r_cpu_stat_fields.cer_stat$v_pcer^#define cer_stat$v_scer cer_stat$r_cpu_stat_overlay.cer_stat$r_cpu_stat_fields.cer_stat$v_scer^#define cer_stat$v_pcel cer_stat$r_cpu_stat_overlay.cer_stat$r_cpu_stat_fields.cer_stat$v_pcelK#define cer_stat$l_sys_stat cer_stat$r_sys_stat_overlay.cer_stat$l_sys_stat^#define cer_stat$v_scel cer_stat$r_sys_stat_ overlay.cer_stat$r_sys_stat_fields.cer_stat$v_scel"#endif /* #if !defined(__VAXC) */ #define CER_STAT$K_LENGTH 8N/*++ */N/* Correctable Error Reporting Subpacket */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadwor d#else#pragma __nomember_alignment#endiftypedef struct _cer {#pragma __nomember_alignment$ unsigned short int cer$w_length;# unsigned short int cer$w_class;" unsigned short int cer$w_type;! unsigned short int cer$w_rev;X unsigned __int64 cer$q_cpu_whami; /* Logical CPU number of reporting processor. */Q CER_STAT cer$r_cer_stat; /* Correctable error reporting status. */ } CER;#define CER$K_LENGTH 24#define CER$K_CLASS 9#define CER$K_TYPE 1#define CER$K_REV 2N/*++ */N/* Entry Terminator Subpacket */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _entry_term {#pragma __nomemb er_alignment+ unsigned short int entry_term$w_length;* unsigned short int entry_term$w_class;) unsigned short int entry_term$w_type;( unsigned short int entry_term$w_rev; } ENTRY_TERM;#define ENTRY_TERM$K_LENGTH 8#define ENTRY_TERM$K_CLASS 0#define ENTRY_TERM$K_TYPE 0#define ENTRY_TERM$K_REV 1N/*++ */N/* IA64-specific CRD_CONTROL bits. */N/* */N/* Overlay of exe$gl_crd_control.crd_control$w_sys_specific */N/* which is the upper word of exe$gl_crd_control. */N/*-- */+#define CRD_CONTROL_IA64$M_POLLING_TIME 0x7.#define CRD_CONTROL_IA64$M_DISABLE_POLLING 0x8 "typedef struct _crd_control_ia64 {m unsigned crd_control_ia64$v_polling_time : 3; /* Used for tuning the polling time for corrected errors */_ unsigned crd_control_ia64$v_disable_polling : 1; /* Disable polling for corrected errors */N unsigned crd_control_ia64$v_reserved : 4; /* Reserved */N unsigned char crd_control_ia64$b_debug; /* Reserved for debug use. */ } CRD_CONTROL_IA64;##define CRD_CONTROL_IA64$K_LENGTH 2 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __requ ired_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard "#endif /* __IA64_MCHKDEF_LOADED */ ww =;[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Devel opment, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not  **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************************************** *****************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */K/* Source: 14-AUG-2008 15:02:07 $1$DGA8345:[LIB_H.SRC]IA64_PALDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IA64_PALDEF ***/#ifndef __IA64_PALDEF_LOADED#define __IA64_PALDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment _ _save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifnde f __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* PAL Procedure return structure */N/*-- */ c#if !defined(__N OBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_ret {#pragma __nomember_alignment$ unsigned __int64 pal_ret$q_val0;$ unsigned __int64 pal_ret$q_val1;$ unsigned __int64 pal_ret$q_val2;$ unsigned __int64 pal_ret$q_val3; } PAL_RET;N/*++ */N/* PAL calls */N/*-- */ #define IA64_PAL$K_CACHE_FLUSH 1#define IA64_PAL$K_CACHE_INFO 2#define IA64_PAL$K_CACHE_INIT 3"#define IA64_PAL$K_CACHE_SUMMARY 4#define IA64_PAL$K_MEM_ATTRIB 5#define IA64_PAL$K_PTCE_INFO 6#define IA64_PAL$K_VM_INFO 7#define IA64_PAL$K_VM_SUMMARY 8%#define IA64_PAL$K_BUS_GET_FEATURES 9&#define IA64_PAL$K_BUS_SET_FEATURES 10 #define IA64_PAL$K_DEBUG _INFO 11 #define IA64_PAL$K_FIXED_ADDR 12#define IA64_PAL$K_FREQ_BASE 13!#define IA64_PAL$K_FREQ_RATIOS 14##define IA64_PAL$K_PERF_MON_INFO 15##define IA64_PAL$K_PLATFORM_ADDR 16'#define IA64_PAL$K_PROC_GET_FEATURES 17'#define IA64_PAL$K_PROC_SET_FEATURES 18#define IA64_PAL$K_RSE_INFO 19#define IA64_PAL$K_VERSION 20"#define IA64_PAL$K_MC_CLEAR_LOG 21#define IA64_PAL$K_MC_DRAIN 22!#define IA64_PAL$K_MC_EXPECTED 23&#define IA64_PAL$K_MC_DYNAMIC_STATE 24##define IA64_PAL$K_MC_ER ROR_INFO 25#define IA64_PAL$K_MC_RESUME 26%#define IA64_PAL$K_MC_REGISTER_MEM 27#define IA64_PAL$K_HALT 28 #define IA64_PAL$K_HALT_LIGHT 29#define IA64_PAL$K_COPY_INFO 30%#define IA64_PAL$K_CACHE_LINE_INIT 31$#define IA64_PAL$K_PMI_ENTRYPOINT 32%#define IA64_PAL$K_ENTER_IA_32_ENV 33"#define IA64_PAL$K_VM_PAGE_SIZE 34"#define IA64_PAL$K_MEM_FOR_TEST 37%#define IA64_PAL$K_CACHE_PROT_INFO 38##define IA64_PAL$K_REGISTER_INFO 39#define IA64_PAL$K_SHUTDOWN 40)#define IA64_PAL$K_PRE FETCH_VISIBILITY 41)#define IA64_PAL$K_LOGICAL_TO_PHYSICAL 42'#define IA64_PAL$K_CACHE_SHARED_INFO 43!#define IA64_PAL$K_PSTATE_INFO 44%#define IA64_PAL$K_MC_ERROR_INJECT 47N/*++ */N/* 256-511 reserved for architecture defined */N/* stack register calls */N/*-- */#d efine IA64_PAL$K_COPY_PAL 256 #define IA64_PAL$K_HALT_INFO 257 #define IA64_PAL$K_TEST_PROC 258!#define IA64_PAL$K_CACHE_READ 259"#define IA64_PAL$K_CACHE_WRITE 260!#define IA64_PAL$K_VM_TR_READ 261!#define IA64_PAL$K_GET_PSTATE 262!#define IA64_PAL$K_SET_PSTATE 263!#define IA64_PAL$K_BRAND_INFO 274#define IA64_PAL$K_CAR_INIT 520#define IA64_PAL$K_AUTH 521)#define IA64_PAL$K_HALT_LIGHT_SPECIAL 522*#define IA64_PAL$K_CHECK_UNLOGGED_CMCI 523!#define IA64_PAL$K_POWER_INFO 524$#d efine IA64_PAL$K_SET_MAX_POWER 527%#define IA64_PAL$K_THREAD_CONTROL 528*#define IA64_PAL$K_CACHE_DISABLED_INFO 529##define IA64_PAL$K_DEFEATURE_L3 530"#define IA64_PAL$K_SET_TIMEOUT 531##define IA64_PAL$K_CONTEXT_SAVE 544&#define IA64_PAL$K_CONTEXT_RESTORE 545&#define IA64_PAL$K_FORCE_UC_ACCESS 768N/*++ */N/* Generic return status used by PAL calls */N/*-- */#define IA64_PAL$K_SUCCESS 0#define IA64_PAL$C_SUCCESS 0#define IA64_PAL$K_UNIMPL -1#define IA64_PAL$K_INVAL_ARG -2#define IA64_PAL$K_FAIL -3!#define IA64_PAL$K_SIDE_EFFECT -4$#define IA64_PAL$K_INFO_NOT_AVAIL -6N/*++ */N/* Definitions used by PAL_BUS_GET_FEATURES/PAL_BUS_SET_FEATURES */N/*-- */N/* definition of return structure */*#define PAL_BUS$M_BCFG_REQ_PARK 0x20000000&#define PAL_BUS$M_BCFG_LOCK 0x40000000*#define PAL_BUS$M_ENA_HALF_XFER 0x800000004#define PAL_BUS$M_BCFG_DIS_XACT_QUE 0x800000000000007#define PAL_BUS$M_BCFG_DIS_RSPERR_CHK 0x1000000000000005#define PAL_BUS$M_BCFG_DIS_BERR_CHK 0x2000000000000005#define PAL_BUS$M_BCFG_DIS_IREQ_SIG 0x4000000000000004#define PAL_BUS$M_BCFG_DIS_REQ_SIG 0x8000000000000002#define PAL_BU S$M_BCFG_DIS_INIT 0x10000000000000006#define PAL_BUS$M_BCFG_DIS_INIT_SIG 0x20000000000000002#define PAL_BUS$M_BCFG_DIS_AERR 0x40000000000000006#define PAL_BUS$M_BCFG_DIS_AERR_SIG 0x8000000000000000##define PAL_BUS$M_BCFG_DIS_DERR 0x0 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_bus {#pragma __nomember_alignment& unsigned _ _int64 pal_bus$q_status;. unsigned __int64 pal_bus$q_features_avail;/ unsigned __int64 pal_bus$q_features_status; __union {4 unsigned __int64 pal_bus$q_features_control; __struct {N unsigned pal_bus$v_filler_1 : 29; /* skip to first field */N unsigned pal_bus$v_bcfg_req_park : 1; /* (1UL << 29) */N unsigned pal_bus$v_bcfg_lock : 1; /* (1UL << 30) */N unsigned pal_bus$v_ena_half_xfer : 1;  /* (1UL << 31) */N unsigned pal_bus$v_filler_2 : 23; /* */N unsigned pal_bus$v_bcfg_dis_xact_que : 1; /* (1UL << 54) */N unsigned pal_bus$v_bcfg_dis_rsperr_chk : 1; /* (1UL << 55) */N unsigned pal_bus$v_bcfg_dis_berr_chk : 1; /* (1UL << 56) */N unsigned pal_bus$v_bcfg_dis_ireq_sig : 1; /* (1UL << 57) */N unsigned pal_bus$v_bcfg_dis_req_sig : 1; /* (1UL << 58) */N unsigned pal_bus$v_bcfg_dis_init : 1; /* (1UL << 59) */N unsigned pal_bus$v_bcfg_dis_init_sig : 1; /* (1UL << 60) */N unsigned pal_bus$v_bcfg_dis_aerr : 1; /* (1UL << 61) */N unsigned pal_bus$v_bcfg_dis_aerr_sig : 1; /* (1UL << 62) */N unsigned pal_bus$v_bcfg_dis_derr : 1; /* (1UL << 63) */+ unsigned pal_bus$v_fill_0_ : 7; } pal_bus$r_fc_bits; } pal_bus$r_fc _overlay; char pal_bus$b_fill_1_ [7]; } PAL_BUS; #if !defined(__VAXC)R#define pal_bus$q_features_control pal_bus$r_fc_overlay.pal_bus$q_features_control^#define pal_bus$v_bcfg_req_park pal_bus$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_bcfg_req_parkV#define pal_bus$v_bcfg_lock pal_bus$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_bcfg_lock^#define pal_bus$v_ena_half_xfer pal_bus$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_ena_half_xferf#define pal_bus$v_bcfg_dis_xact_que pal_bus$r_fc_overl ay.pal_bus$r_fc_bits.pal_bus$v_bcfg_dis_xact_quej#define pal_bus$v_bcfg_dis_rsperr_chk pal_bus$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_bcfg_dis_rsperr_chkf#define pal_bus$v_bcfg_dis_berr_chk pal_bus$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_bcfg_dis_berr_chkf#define pal_bus$v_bcfg_dis_ireq_sig pal_bus$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_bcfg_dis_ireq_sigd#define pal_bus$v_bcfg_dis_req_sig pal_bus$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_bcfg_dis_req_sig^#define pal_bus$v_bcfg_dis_init pal_bu s$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_bcfg_dis_initf#define pal_bus$v_bcfg_dis_init_sig pal_bus$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_bcfg_dis_init_sig^#define pal_bus$v_bcfg_dis_aerr pal_bus$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_bcfg_dis_aerrf#define pal_bus$v_bcfg_dis_aerr_sig pal_bus$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_bcfg_dis_aerr_sig^#define pal_bus$v_bcfg_dis_derr pal_bus$r_fc_overlay.pal_bus$r_fc_bits.pal_bus$v_bcfg_dis_derr"#endif /* #if !defined(__VAXC) */ N/*++ */N/* Definitions used by PAL_CACHE_FLUSH */N/*-- */"#define IA64_PAL$K_CACHE_ISTREAM 1"#define IA64_PAL$K_CACHE_DSTREAM 2#define IA64_PAL$K_CACHE_BOTH 3##define IA64_PAL$K_CACHE_VALIDATE 0%#define IA64_PAL$K_CACHE_INVALIDATE 1##define IA64_PAL$K_CACHE_POLL_INT 2##define IA64_PAL$K_CACHE_PLAT_ACK 4 c#if !defin ed(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_cflush {#pragma __nomember_alignment) unsigned __int64 pal_cflush$q_status;) unsigned __int64 pal_cflush$q_vector;+ unsigned __int64 pal_cflush$q_progress;( unsigned __int64 pal_cflush$q_spare; } PAL_CFLUSH;N/*++ */N/* Definitions used by PAL_CACHE_INFO */N/*-- */&#define PAL_CINFO$M_CINFO1_UNIFIED 0x1%#define PAL_CINFO$M_CINFO1_ATTRIB 0x6'#define PAL_CINFO$M_CINFO1_ASSOC 0xFF00)#define PAL_CINFO$M_CINFO1_LSIZE 0xFF0000,#define PAL_CINFO$M_CINFO1_STRIDE 0xFF000000-#define PAL_CINFO$M_CINFO1_STLAT 0xFF00000000/#define PAL_CINFO$M_CINFO1_LDLAT 0xFF00000000002#define PAL_CINFO$M_CINFO1 _STHINT 0xFF0000000000004#define PAL_CINFO$M_CINFO1_LDHINT 0xFF00000000000000.#define PAL_CINFO$M_CINFO2_ALIASB 0xFF00000000/#define PAL_CINFO$M_CINFO2_TAGLS 0xFF00000000001#define PAL_CINFO$M_CINFO2_TAGMS 0xFF000000000000/#define PAL_CINFO$M_FILLER_2 0xFF00000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_cinfo {#p ragma __nomember_alignment( unsigned __int64 pal_cinfo$q_status; __union {2 unsigned __int64 pal_cinfo$q_config_info1; __struct {N unsigned pal_cinfo$v_cinfo1_unified : 1; /* (0x1UL << 0) 0 */N unsigned pal_cinfo$v_cinfo1_attrib : 2; /* (0x3UL << 1) 1-2 */N unsigned pal_cinfo$v_filler_1 : 5; /* 3-7 */N unsigned pal_cinfo$v_cinfo1_assoc : 8; /* (0xffUL << 8) 8-15 */N unsigned pal_c!info$v_cinfo1_lsize : 8; /* (0xffUL << 16) 16-23 */N unsigned pal_cinfo$v_cinfo1_stride : 8; /* (0xffUL << 24) 24-31 */N unsigned pal_cinfo$v_cinfo1_stlat : 8; /* (0xffUL << 32) 32-39 */N unsigned pal_cinfo$v_cinfo1_ldlat : 8; /* (0xffUL << 40) 40-47 */N unsigned pal_cinfo$v_cinfo1_sthint : 8; /* (0xffUL << 48) 48-55 */N unsigned pal_cinfo$v_cinfo1_ldhint : 8; /* (0xffUL << 56) 56-63 */% } pal_cinfo$r_info1_bits;$ } pa !l_cinfo$r_info1_overlay; __union {2 unsigned __int64 pal_cinfo$q_config_info2; __struct {2 unsigned int pal_cinfo$l_cinfo2_csize;N unsigned pal_cinfo$v_cinfo2_aliasb : 8; /* (0xff << 32) 32-39 */N unsigned pal_cinfo$v_cinfo2_tagls : 8; /* (0xff << 40) 40-47 */N unsigned pal_cinfo$v_cinfo2_tagms : 8; /* (0xff << 48) 48-55 */B unsigned pal_cinfo$v_filler_2 : 8; /* 56-63 */% } pal_cinfo$r_info !2_bits;$ } pal_cinfo$r_info2_overlay;' unsigned __int64 pal_cinfo$q_spare; } PAL_CINFO; #if !defined(__VAXC)S#define pal_cinfo$q_config_info1 pal_cinfo$r_info1_overlay.pal_cinfo$q_config_info1n#define pal_cinfo$v_cinfo1_unified pal_cinfo$r_info1_overlay.pal_cinfo$r_info1_bits.pal_cinfo$v_cinfo1_unifiedl#define pal_cinfo$v_cinfo1_attrib pal_cinfo$r_info1_overlay.pal_cinfo$r_info1_bits.pal_cinfo$v_cinfo1_attribj#define pal_cinfo$v_cinfo1_assoc pal_cinfo$r_info1_overlay.pal_c!info$r_info1_bits.pal_cinfo$v_cinfo1_assocj#define pal_cinfo$v_cinfo1_lsize pal_cinfo$r_info1_overlay.pal_cinfo$r_info1_bits.pal_cinfo$v_cinfo1_lsizel#define pal_cinfo$v_cinfo1_stride pal_cinfo$r_info1_overlay.pal_cinfo$r_info1_bits.pal_cinfo$v_cinfo1_stridej#define pal_cinfo$v_cinfo1_stlat pal_cinfo$r_info1_overlay.pal_cinfo$r_info1_bits.pal_cinfo$v_cinfo1_stlatj#define pal_cinfo$v_cinfo1_ldlat pal_cinfo$r_info1_overlay.pal_cinfo$r_info1_bits.pal_cinfo$v_cinfo1_ldlatl#define pal_cinfo$v_cinfo1_s!thint pal_cinfo$r_info1_overlay.pal_cinfo$r_info1_bits.pal_cinfo$v_cinfo1_sthintl#define pal_cinfo$v_cinfo1_ldhint pal_cinfo$r_info1_overlay.pal_cinfo$r_info1_bits.pal_cinfo$v_cinfo1_ldhintS#define pal_cinfo$q_config_info2 pal_cinfo$r_info2_overlay.pal_cinfo$q_config_info2j#define pal_cinfo$l_cinfo2_csize pal_cinfo$r_info2_overlay.pal_cinfo$r_info2_bits.pal_cinfo$l_cinfo2_csizel#define pal_cinfo$v_cinfo2_aliasb pal_cinfo$r_info2_overlay.pal_cinfo$r_info2_bits.pal_cinfo$v_cinfo2_aliasbj#define pa!l_cinfo$v_cinfo2_tagls pal_cinfo$r_info2_overlay.pal_cinfo$r_info2_bits.pal_cinfo$v_cinfo2_taglsj#define pal_cinfo$v_cinfo2_tagms pal_cinfo$r_info2_overlay.pal_cinfo$r_info2_bits.pal_cinfo$v_cinfo2_tagmsb#define pal_cinfo$v_filler_2 pal_cinfo$r_info2_overlay.pal_cinfo$r_info2_bits.pal_cinfo$v_filler_2"#endif /* #if !defined(__VAXC) */ N/*++ */N/* Config 1 information returned */N !/*-- */$#define IA64_PAL$K_CACHE_WRITETHRU 0$#define IA64_PAL$K_CACHE_WRITEBACK 1!#define IA64_PAL$K_CACHE_EITHER 2$#define IA64_PAL$K_CACHE_TYPE_INST 1$#define IA64_PAL$K_CACHE_TYPE_DATA 2N/*++ */N/* Config 2 information returned */N/*-- */!N/*++ */N/* Definitions used by PAL_CACHE_INIT */N/*-- */$#define IA64_PAL$K_CACHE_INIT_ALL -1&#define IA64_PAL$K_CACHE_NO_RESTRICT 0##define IA64_PAL$K_CACHE_RESTRICT 1N/*++ */N/* Definitions used by PAL_CACHE_PROT_INFO ! */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_cpinfo {#pragma __nomember_alignment) unsigned __int64 pal_cpinfo$q_status;/ unsigned int pal_cpinfo$l_config_info1 [2];/ unsigned int pal_cpinfo$l_config_info2 [2];/ unsigned int ! pal_cpinfo$l_config_info3 [2]; } PAL_CPINFO;N/* bitmask for config */'#define IA64_PAL$M_CPINFO_DATA_BITS 255'#define IA64_PAL$M_CPINFO_TPROT_LSB 768+#define IA64_PAL$M_CPINFO_TPROT_MSB 1032192-#define IA64_PAL$M_CPINFO_TPROT_BITS 66060288+#define IA64_PAL$M_CPINFO_METHOD 1006632960.#define IA64_PAL$M_CPINFO_TAG_DATA -1073741824N/* bitmask for config */%#define IA64_PAL$V_C !PINFO_DATA_BITS 0%#define IA64_PAL$V_CPINFO_TPROT_LSB 8&#define IA64_PAL$V_CPINFO_TPROT_MSB 14'#define IA64_PAL$V_CPINFO_TPROT_BITS 20##define IA64_PAL$V_CPINFO_METHOD 26%#define IA64_PAL$V_CPINFO_TAG_DATA 30N/* values */$#define IA64_PAL$K_CACHE_PROT_DATA 0##define IA64_PAL$K_CACHE_PROT_TAG 1(#define IA64_PAL$K_CACHE_PROT_TAG_DATA 2(#define IA64_PAL$K_CACHE_PROT_DATA_TAG 3$#define IA64_PAL$K_CACHE_PROT_NONE 0&#define !IA64_PAL$K_CACHE_PROT_ODDPAR 1'#define IA64_PAL$K_CACHE_PROT_EVENPAR 2##define IA64_PAL$K_CACHE_PROT_ECC 3N/*++ */N/* Definitions used by PAL_CACHE_SUMMARY */N/*-- */N/* return structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If  !using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_csumm {#pragma __nomember_alignment( unsigned __int64 pal_csumm$q_status;. unsigned __int64 pal_csumm$q_cache_levels;/ unsigned __int64 pal_csumm$q_unique_caches;' unsigned __int64 pal_csumm$q_spare; } PAL_CSUMM;N/*++ */N/* Definitions used by PAL_COPY_INFO ! */N/*-- */N/* return structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_copy_info {#pragma __nomember_alignment, unsigned __int64 pal_copy_info$q_status;1 unsi !gned __int64 pal_copy_info$q_buffer_size;2 unsigned __int64 pal_copy_info$q_buffer_align;+ unsigned __int64 pal_copy_info$q_spare; } PAL_COPY_INFO;N/*++ */N/* Definitions used by PAL_COPY_PAL */N/*-- */N/* return structure */ c#if !defined(__NOB !ASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_copy_pal {#pragma __nomember_alignment+ unsigned __int64 pal_copy_pal$q_status;0 unsigned __int64 pal_copy_pal$q_proc_offset;+ unsigned __int64 pal_copy_pal$q_spare1;+ unsigned __int64 pal_copy_pal$q_spare2; } PAL_COPY_PAL;N/*++ ! */N/* Definitions used by PAL_DEBUG_INFO */N/*-- */N/* return structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _pal_debug_info {#pragma __nomember_a !lignment- unsigned __int64 pal_debug_info$q_status;, unsigned __int64 pal_debug_info$q_iregs;, unsigned __int64 pal_debug_info$q_dregs;, unsigned __int64 pal_debug_info$q_spare; } PAL_DEBUG_INFO;N/*++ */N/* Definitions used by PAL_PSTATE_INFO */N/*-- */g/* return structure. PAL_PSTATE_INFO wants an ! array of 8 of these (i.e. 256 bytes), with the number */P/* of valid entries = the number of pstates = the second integer return value */)#define PAL_PSTATE_INFO$M_PERF_INDEX 0x7F:#define PAL_PSTATE_INFO$M_TYPICAL_POWER 0xFFFFFFFFFFFFF000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif!typedef struct _pal_pstate_info {#pragma __nomember_alignment ! __union {1 unsigned __int64 pal_pstate_info$q_quad1; __struct {6 unsigned pal_pstate_info$v_perf_index : 7;4 unsigned pal_pstate_info$v_filler_1 : 5;#if defined(__VAXC)< unsigned pal_pstate_info$v_typical_power_1 : 32;< unsigned pal_pstate_info$v_typical_power_2 : 20;#elseB unsigned __int64 pal_pstate_info$v_typical_power : 52;#endif( } pal_pstate_info$r_dd_bits;- } pal_pstate_info$r_pstate !_info1_ove;7 unsigned __int64 pal_pstate_info$q_trans_latency_1;7 unsigned __int64 pal_pstate_info$q_trans_latency_2;- unsigned __int64 pal_pstate_info$q_spare; } PAL_PSTATE_INFO; #if !defined(__VAXC)Z#define pal_pstate_info$q_quad1 pal_pstate_info$r_pstate_info1_ove.pal_pstate_info$q_quad1~#define pal_pstate_info$v_perf_index pal_pstate_info$r_pstate_info1_ove.pal_pstate_info$r_dd_bits.pal_pstate_info$v_perf_index#define pal_pstate_info$v_typical_power pal_pstate_info$r_ !pstate_info1_ove.pal_pstate_info$r_dd_bits.pal_pstate_info$v_typical_power"#endif /* #if !defined(__VAXC) */ N/* Pstate return values */$#define PAL_PSTATE_RETURNS$M_DDT 0x7'#define PAL_PSTATE_RETURNS$M_DDIT 0x7E0 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif)typedef struct _pal_pstate_info_retu !rns {#pragma __nomember_alignment1 unsigned __int64 pal_pstate_returns$q_status;5 unsigned __int64 pal_pstate_returns$q_pstate_num; __union {6 unsigned __int64 pal_pstate_returns$q_dd_info; __struct {2 unsigned pal_pstate_returns$v_ddt : 3;3 unsigned pal_pstate_returns$v_rsv1 : 2;3 unsigned pal_pstate_returns$v_ddit : 6;6 unsigned pal_pstate_returns$v_fill_2_ : 5;+ } pal_pstate_returns$r_dd_bits;* ! } pal_pstate_returns$r_dd_overlay;0 unsigned __int64 pal_pstate_returns$q_spare; } PAL_PSTATE_INFO_RETURNS; #if !defined(__VAXC)a#define pal_pstate_returns$q_dd_info pal_pstate_returns$r_dd_overlay.pal_pstate_returns$q_dd_infov#define pal_pstate_returns$v_ddt pal_pstate_returns$r_dd_overlay.pal_pstate_returns$r_dd_bits.pal_pstate_returns$v_ddtx#define pal_pstate_returns$v_ddit pal_pstate_returns$r_dd_overlay.pal_pstate_returns$r_dd_bits.pal_pstate_returns$v_ddit"#endif /* #if ! !defined(__VAXC) */ N/*++ */N/* Definitions used by PAL_RSE_INFO */N/*-- */N/* return structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragm !a __nomember_alignment#endiftypedef struct _pal_rse_info {#pragma __nomember_alignment+ unsigned __int64 pal_rse_info$q_status;1 unsigned __int64 pal_rse_info$q_phys_stacked;* unsigned __int64 pal_rse_info$q_hints;* unsigned __int64 pal_rse_info$q_spare; } PAL_RSE_INFO;N/*++ */N/* Definitions used by PAL_FREQ_BASE */N/*-- ! */N/* return structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_freq_base {#pragma __nomember_alignment, unsigned __int64 pal_freq_base$q_status;/ unsigned __int64 pal_freq_base$q_base_freq;, unsigned __int64 pal_freq_base$q!_spare1;, unsigned __int64 pal_freq_base$q_spare2; } PAL_FREQ_BASE; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _pal_freq_ratio {#pragma __nomember_alignment __union {- unsigned __int64 pal_freq_ratio$q_v0; __struct {6 unsigned int pal_freq_ratio$l_denominator;4 unsigned int pal !_freq_ratio$l_numerator;+ } pal_freq_ratio$r_pal_freq_v1;, } pal_freq_ratio$r_pal_freq_overlay; } PAL_FREQ_RATIO; #if !defined(__VAXC)Q#define pal_freq_ratio$q_v0 pal_freq_ratio$r_pal_freq_overlay.pal_freq_ratio$q_v0#define pal_freq_ratio$l_denominator pal_freq_ratio$r_pal_freq_overlay.pal_freq_ratio$r_pal_freq_v1.pal_freq_ratio$l_denominator|#define pal_freq_ratio$l_numerator pal_freq_ratio$r_pal_freq_overlay.pal_freq_ratio$r_pal_freq_v1.pal_freq_ratio$l_numerator !"#endif /* #if !defined(__VAXC) */ N/*++ */N/* Definitions used by PAL_HALT */N/*-- */#define IA64_PAL$K_PAL_HALT_1 1#define IA64_PAL$K_PAL_HALT_2 2#define IA64_PAL$K_PAL_HALT_3 3#define IA64_PAL$K_PAL_HALT_4 4#define IA64_PAL$K_PAL_HALT_5 5#define IA64_PAL$K_PAL_HALT_6 6#define IA64_PAL$K_P !AL_HALT_7 7N/*++ */N/* Definitions used by PAL_HALT_INFO */N/*-- */1#define PAL_HALT_INFO$M_PWR_IM 0x10000000000000001#define PAL_HALT_INFO$M_PWR_CO 0x2000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword !#else#pragma __nomember_alignment#endiftypedef struct _pal_halt_info {#pragma __nomember_alignment __union {. unsigned __int64 pal_halt_info$q_info; __struct {R unsigned short int pal_halt_info$w_pwr_exit_lat; /* (0xffffUL << 0) */T unsigned short int pal_halt_info$w_pwr_entry_lat; /* (0xffffUL << 16) */6 unsigned pal_halt_info$v_pwr_consump : 28;0 unsigned pal_halt_info$v_pwr_im : 1;0 unsigned pal_halt_info !$v_pwr_co : 1;1 unsigned pal_halt_info$v_fill_3_ : 2;. } pal_halt_info$r_pal_halt_fields;+ } pal_halt_info$r_pal_halt_overlay; } PAL_HALT_INFO; #if !defined(__VAXC)R#define pal_halt_info$q_info pal_halt_info$r_pal_halt_overlay.pal_halt_info$q_info#define pal_halt_info$w_pwr_exit_lat pal_halt_info$r_pal_halt_overlay.pal_halt_info$r_pal_halt_fields.pal_halt_info$w_pwr_exit_lat#define pal_halt_info$w_pwr_entry_lat pal_halt_info$r_pal_halt_overlay.pal_halt_!!info$r_pal_halt_fields.pal_halt_info$w_pwr_entry_lat#define pal_halt_info$v_pwr_consump pal_halt_info$r_pal_halt_overlay.pal_halt_info$r_pal_halt_fields.pal_halt_info$v_pwr_consumpv#define pal_halt_info$v_pwr_im pal_halt_info$r_pal_halt_overlay.pal_halt_info$r_pal_halt_fields.pal_halt_info$v_pwr_imv#define pal_halt_info$v_pwr_co pal_halt_info$r_pal_halt_overlay.pal_halt_info$r_pal_halt_fields.pal_halt_info$v_pwr_co"#endif /* #if !defined(__VAXC) */ N/*++ "! */N/* Definitions used by PAL_MC_CLEAR_LOG */N/*-- */N/* return structure */##define PAL_MC_CLOG$M_PEND_MCHK 0x1##define PAL_MC_CLOG$M_PEND_INIT 0x2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#els#!e#pragma __nomember_alignment#endiftypedef struct _pal_mc_clog {#pragma __nomember_alignment* unsigned __int64 pal_mc_clog$q_status; __union {/ unsigned __int64 pal_mc_clog$q_pending; __struct {1 unsigned pal_mc_clog$v_pend_mchk : 1;1 unsigned pal_mc_clog$v_pend_init : 1;/ unsigned pal_mc_clog$v_fill_4_ : 6;) } pal_mc_clog$r_mc_clog_bits;( } pal_mc_clog$r_mc_clog_overlay;* unsigned __int64 pal_mc_cl $!og$q_spare1;* unsigned __int64 pal_mc_clog$q_spare2; } PAL_MC_CLOG; #if !defined(__VAXC)Q#define pal_mc_clog$q_pending pal_mc_clog$r_mc_clog_overlay.pal_mc_clog$q_pendingp#define pal_mc_clog$v_pend_mchk pal_mc_clog$r_mc_clog_overlay.pal_mc_clog$r_mc_clog_bits.pal_mc_clog$v_pend_mchkp#define pal_mc_clog$v_pend_init pal_mc_clog$r_mc_clog_overlay.pal_mc_clog$r_mc_clog_bits.pal_mc_clog$v_pend_init"#endif /* #if !defined(__VAXC) */ N/*++ %! */N/* Definitions used by PAL_MC_ERROR_INFO */N/*-- */N/* return structure */##define PAL_MCERR$M_FILLER_1 0xFFFF*#define PAL_MCERR$M_CACHE_CHK_WAY 0x1F0000%#define PAL_MCERR$M_FILLER_2 0x200000)#define PAL_MCERR$M_CACHE_CHK_MC 0x400000)#define PAL_MCERR$M_CACHE_CHK_TV 0x800000*#define PAL_MCERR$M_CACHE_ &!CHK_WV 0x1000000,#define PAL_MCERR$M_CACHE_CHK_OPER 0xE000000-#define PAL_MCERR$M_CACHE_CHK_DATA 0x10000000,#define PAL_MCERR$M_CACHE_CHK_TAG 0x20000000/#define PAL_MCERR$M_CACHE_CHK_DCACHE 0x40000000/#define PAL_MCERR$M_CACHE_CHK_ICACHE 0x800000004#define PAL_MCERR$M_CACHE_CHK_INDEX 0xFFFFFF000000002#define PAL_MCERR$M_CACHE_CHK_MV 0x1000000000000004#define PAL_MCERR$M_CACHE_CHK_MESI 0xE000000000000006#define PAL_MCERR$M_CACHE_CHK_LEVEL 0xF000000000000000'#define PAL_MCERR$M_TLB_CHK_TRSL'!OT 0xFF##define PAL_MCERR$M_FILLER_3 0xFF00'#define PAL_MCERR$M_TLB_CHK_ITC 0x10000'#define PAL_MCERR$M_TLB_CHK_DTC 0x20000'#define PAL_MCERR$M_TLB_CHK_ITR 0x40000'#define PAL_MCERR$M_TLB_CHK_DTR 0x80000'#define PAL_MCERR$M_TLB_CHK_MC 0x100000%#define PAL_MCERR$M_BUS_CHK_SIZE 0x1F##define PAL_MCERR$M_BUS_CHK_IB 0x20##define PAL_MCERR$M_BUS_CHK_EB 0x40##define PAL_MCERR$M_BUS_CHK_CC 0x80'#define PAL_MCERR$M_BUS_CHK_TYPE 0xFF00-#define PAL_MCERR$M_BUS_CHK_SEVERITY 0x1F0000,#def(!ine PAL_MCERR$M_BUS_CHK_TADDR_V 0x200000.#define PAL_MCERR$M_BUS_CHK_RSPADDR_V 0x400000.#define PAL_MCERR$M_BUS_CHK_REQADDR_V 0x800000.#define PAL_MCERR$M_BUS_CHK_BUSINFO 0xFF000000*#define PAL_MCERR$M_BUS_CHK_MC 0x100000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_mcerr {#pragma __nomember_alignment( unsigned __int64 p )!al_mcerr$q_status; __union {0 unsigned __int64 pal_mcerr$q_error_info;* unsigned __int64 pal_mcerr$q_size; __struct {N unsigned pal_mcerr$v_filler_1 : 16; /* 0-15 */N unsigned pal_mcerr$v_cache_chk_way : 5; /* (0x1fUL << 16) 16-20 */B unsigned pal_mcerr$v_filler_2 : 1; /* 21 */N unsigned pal_mcerr$v_cache_chk_mc : 1; /* (0x1UL << 22) 22 */N unsigned pal_mcerr$v_cache_chk_tv *!: 1; /* (0x1UL << 23) 23 */N unsigned pal_mcerr$v_cache_chk_wv : 1; /* (0x1UL << 24) 24 */O unsigned pal_mcerr$v_cache_chk_oper : 3; /* (0x7UL << 25) 25-27 */N unsigned pal_mcerr$v_cache_chk_data : 1; /* (0x1UL << 28) 28 */N unsigned pal_mcerr$v_cache_chk_tag : 1; /* (0x1UL << 29) 29 */N unsigned pal_mcerr$v_cache_chk_dcache : 1; /* (0x1UL << 30) 30 */N unsigned pal_mcerr$v_cache_chk_icache : 1; /* (0x1UL << 31 +!) 31 */U unsigned pal_mcerr$v_cache_chk_index : 24; /* (0xffffffUL << 32) 32-55 */N unsigned pal_mcerr$v_cache_chk_mv : 1; /* (0x1fUL << 56) 56 */N unsigned pal_mcerr$v_cache_chk_mesi : 3; /* (0x7UL << 57) 57-59 */O unsigned pal_mcerr$v_cache_chk_level : 4; /* (0xfUL << 60) 60-63 */% } pal_mcerr$r_cache_bits; __struct {N unsigned pal_mcerr$v_tlb_chk_trslot : 8; /* (0xffUL << 0) 0-7 */B unsigned pal,!_mcerr$v_filler_3 : 8; /* 8-15 */N unsigned pal_mcerr$v_tlb_chk_itc : 1; /* (0x1UL << 16) 16 */N unsigned pal_mcerr$v_tlb_chk_dtc : 1; /* (0x1UL << 17) 17 */N unsigned pal_mcerr$v_tlb_chk_itr : 1; /* (0x1UL << 18) 18 */N unsigned pal_mcerr$v_tlb_chk_dtr : 1; /* (0x1UL << 19) 19 */N unsigned pal_mcerr$v_tlb_chk_mc : 1; /* (0x1UL << 20) 20 */- unsigned pal_mcerr$v_fill_5_ : 3;# } -!pal_mcerr$r_tlb_bits; __struct {N unsigned pal_mcerr$v_bus_chk_size : 5; /* (0x1fUL << 0) 0-4 */N unsigned pal_mcerr$v_bus_chk_ib : 1; /* (0x1UL << 5) 5 */N unsigned pal_mcerr$v_bus_chk_eb : 1; /* (0x1UL << 6) 6 */N unsigned pal_mcerr$v_bus_chk_cc : 1; /* (0x1UL << 7) 7 */N unsigned pal_mcerr$v_bus_chk_type : 8; /* (0xffUL << 8) 8-15 */Q unsigned pal_mcerr$v_bus_chk_severity : 5; /* (0.!x1fUL << 16) 16-20 */N unsigned pal_mcerr$v_bus_chk_taddr_v : 1; /* (0x1UL << 21) 21 */N unsigned pal_mcerr$v_bus_chk_rspaddr_v : 1; /* (0x1UL << 22) 22 */N unsigned pal_mcerr$v_bus_chk_reqaddr_v : 1; /* (0x1UL << 23) 23 */P unsigned pal_mcerr$v_bus_chk_businfo : 8; /* (0xffUL << 24) 24-31 */N unsigned pal_mcerr$v_bus_chk_mc : 1; /* (0x1UL << 32) 32 */- unsigned pal_mcerr$v_fill_6_ : 7;# } pal_mcerr$r_bus_bi /!ts;$ } pal_mcerr$r_mcerr_overlay;. unsigned __int64 pal_mcerr$q_inc_err_type;' unsigned __int64 pal_mcerr$q_spare; } PAL_MCERR; #if !defined(__VAXC)O#define pal_mcerr$q_error_info pal_mcerr$r_mcerr_overlay.pal_mcerr$q_error_infoC#define pal_mcerr$q_size pal_mcerr$r_mcerr_overlay.pal_mcerr$q_sizel#define pal_mcerr$v_cache_chk_way pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cache_bits.pal_mcerr$v_cache_chk_wayj#define pal_mcerr$v_cache_chk_mc pal_mcerr$r_mcerr_overlay.pal_mce0!rr$r_cache_bits.pal_mcerr$v_cache_chk_mcj#define pal_mcerr$v_cache_chk_tv pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cache_bits.pal_mcerr$v_cache_chk_tvj#define pal_mcerr$v_cache_chk_wv pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cache_bits.pal_mcerr$v_cache_chk_wvn#define pal_mcerr$v_cache_chk_oper pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cache_bits.pal_mcerr$v_cache_chk_opern#define pal_mcerr$v_cache_chk_data pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cache_bits.pal_mcerr$v_cache_chk_datal#define pal_mcerr$v_cach1!e_chk_tag pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cache_bits.pal_mcerr$v_cache_chk_tagr#define pal_mcerr$v_cache_chk_dcache pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cache_bits.pal_mcerr$v_cache_chk_dcacher#define pal_mcerr$v_cache_chk_icache pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cache_bits.pal_mcerr$v_cache_chk_icachep#define pal_mcerr$v_cache_chk_index pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cache_bits.pal_mcerr$v_cache_chk_indexj#define pal_mcerr$v_cache_chk_mv pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cac2!he_bits.pal_mcerr$v_cache_chk_mvn#define pal_mcerr$v_cache_chk_mesi pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cache_bits.pal_mcerr$v_cache_chk_mesip#define pal_mcerr$v_cache_chk_level pal_mcerr$r_mcerr_overlay.pal_mcerr$r_cache_bits.pal_mcerr$v_cache_chk_levell#define pal_mcerr$v_tlb_chk_trslot pal_mcerr$r_mcerr_overlay.pal_mcerr$r_tlb_bits.pal_mcerr$v_tlb_chk_trslot`#define pal_mcerr$v_filler_3 pal_mcerr$r_mcerr_overlay.pal_mcerr$r_tlb_bits.pal_mcerr$v_filler_3f#define pal_mcerr$v_tlb_chk_itc pal_mc3!err$r_mcerr_overlay.pal_mcerr$r_tlb_bits.pal_mcerr$v_tlb_chk_itcf#define pal_mcerr$v_tlb_chk_dtc pal_mcerr$r_mcerr_overlay.pal_mcerr$r_tlb_bits.pal_mcerr$v_tlb_chk_dtcf#define pal_mcerr$v_tlb_chk_itr pal_mcerr$r_mcerr_overlay.pal_mcerr$r_tlb_bits.pal_mcerr$v_tlb_chk_itrf#define pal_mcerr$v_tlb_chk_dtr pal_mcerr$r_mcerr_overlay.pal_mcerr$r_tlb_bits.pal_mcerr$v_tlb_chk_dtrd#define pal_mcerr$v_tlb_chk_mc pal_mcerr$r_mcerr_overlay.pal_mcerr$r_tlb_bits.pal_mcerr$v_tlb_chk_mch#define pal_mcerr$v_bus_ch4!k_size pal_mcerr$r_mcerr_overlay.pal_mcerr$r_bus_bits.pal_mcerr$v_bus_chk_sized#define pal_mcerr$v_bus_chk_ib pal_mcerr$r_mcerr_overlay.pal_mcerr$r_bus_bits.pal_mcerr$v_bus_chk_ibd#define pal_mcerr$v_bus_chk_eb pal_mcerr$r_mcerr_overlay.pal_mcerr$r_bus_bits.pal_mcerr$v_bus_chk_ebd#define pal_mcerr$v_bus_chk_cc pal_mcerr$r_mcerr_overlay.pal_mcerr$r_bus_bits.pal_mcerr$v_bus_chk_cch#define pal_mcerr$v_bus_chk_type pal_mcerr$r_mcerr_overlay.pal_mcerr$r_bus_bits.pal_mcerr$v_bus_chk_typep#define pal_mc5!err$v_bus_chk_severity pal_mcerr$r_mcerr_overlay.pal_mcerr$r_bus_bits.pal_mcerr$v_bus_chk_severityn#define pal_mcerr$v_bus_chk_taddr_v pal_mcerr$r_mcerr_overlay.pal_mcerr$r_bus_bits.pal_mcerr$v_bus_chk_taddr_vr#define pal_mcerr$v_bus_chk_rspaddr_v pal_mcerr$r_mcerr_overlay.pal_mcerr$r_bus_bits.pal_mcerr$v_bus_chk_rspaddr_vr#define pal_mcerr$v_bus_chk_reqaddr_v pal_mcerr$r_mcerr_overlay.pal_mcerr$r_bus_bits.pal_mcerr$v_bus_chk_reqaddr_vn#define pal_mcerr$v_bus_chk_businfo pal_mcerr$r_mcerr_overlay. 6!pal_mcerr$r_bus_bits.pal_mcerr$v_bus_chk_businfod#define pal_mcerr$v_bus_chk_mc pal_mcerr$r_mcerr_overlay.pal_mcerr$r_bus_bits.pal_mcerr$v_bus_chk_mc"#endif /* #if !defined(__VAXC) */ N/* values needed */$#define IA64_PAL$K_MCERR_TYPE_PROC 0%#define IA64_PAL$K_MCERR_TYPE_CACHE 1##define IA64_PAL$K_MCERR_TYPE_TLB 2##define IA64_PAL$K_MCERR_TYPE_BUS 3&#define IA64_PAL$K_MCERR_TYPE_REQADR 4&#define IA64_PAL$K_MCERR_TYPE_RSPADR 5& 7!#define IA64_PAL$K_MCERR_TYPE_TGTADR 6$#define IA64_PAL$K_MCERR_TYPE_IMPL 7N/*++ */N/* Definitions used by PAL_PERF_MON_INFO */N/*-- */N/* return structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#p 8!ragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_pm_info {#pragma __nomember_alignment* unsigned __int64 pal_pm_info$q_status; __union {, unsigned __int64 pal_pm_info$q_info; __struct {N unsigned char pal_pm_info$b_generic; /* (0xffUL << 0) */N unsigned char pal_pm_info$b_width; /* (0xffUL << 8) */N unsigned char pal_pm_info$b_cycles; /* (0xffUL << 16) 9! */N unsigned char pal_pm_info$b_retired; /* (0xffUL << 24) */+ } pal_pm_info$r_pm_info_fields;( } pal_pm_info$r_pm_info_overlay;* unsigned __int64 pal_pm_info$q_spare1;* unsigned __int64 pal_pm_info$q_spare2; } PAL_PM_INFO; #if !defined(__VAXC)K#define pal_pm_info$q_info pal_pm_info$r_pm_info_overlay.pal_pm_info$q_infon#define pal_pm_info$b_generic pal_pm_info$r_pm_info_overlay.pal_pm_info$r_pm_info_fields.pal_pm_info$b_genericj#def:!ine pal_pm_info$b_width pal_pm_info$r_pm_info_overlay.pal_pm_info$r_pm_info_fields.pal_pm_info$b_widthl#define pal_pm_info$b_cycles pal_pm_info$r_pm_info_overlay.pal_pm_info$r_pm_info_fields.pal_pm_info$b_cyclesn#define pal_pm_info$b_retired pal_pm_info$r_pm_info_overlay.pal_pm_info$r_pm_info_fields.pal_pm_info$b_retired"#endif /* #if !defined(__VAXC) */ N/* PM buffer structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplus ;!plus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_pm_buffer {#pragma __nomember_alignment9 unsigned __int64 pal_pm_buffer$q_pmc_implemented [4];9 unsigned __int64 pal_pm_buffer$q_pmd_implemented [4];6 unsigned __int64 pal_pm_buffer$q_count_cycles [4];7 unsigned __int64 pal_pm_buffer$q_count_retired [4]; } PAL_PM_BUFFER;N/*++ ! */N/* Definitions needed by PAL_VM_INFO */N/*-- */N/* return structure */$#define PAL_VM_INFO$M_PF 0x100000000)#define PAL_VM_INFO$M_UNIFIED 0x200000000+#define PAL_VM_INFO$M_TR_REDUCE 0x400000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++?! */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_vm_info {#pragma __nomember_alignment* unsigned __int64 pal_vm_info$q_status; __union {/ unsigned __int64 pal_vm_info$q_tc_info; __struct {N unsigned char pal_vm_info$b_num_sets; /* (0xffUL << 0) */N unsigned char pal_vm_info$b_num_ways; /* (0xffUL << 8) */P unsigned short int pal_vm_info$w_num_entries; @!/* (0xffffUL << 16) */N unsigned pal_vm_info$v_pf : 1; /* (0x1UL << 32) */N unsigned pal_vm_info$v_unified : 1; /* (0x1UL << 33) */N unsigned pal_vm_info$v_tr_reduce : 1; /* (0x1UL << 34) *// unsigned pal_vm_info$v_fill_7_ : 5;+ } pal_vm_info$r_tc_info_fields;( } pal_vm_info$r_tc_info_overlay;, unsigned __int64 pal_vm_info$q_tc_pages;) unsigned __int64 pal_vm_info$q_spare; } PAL_VM_IA!NFO; #if !defined(__VAXC)Q#define pal_vm_info$q_tc_info pal_vm_info$r_tc_info_overlay.pal_vm_info$q_tc_infop#define pal_vm_info$b_num_sets pal_vm_info$r_tc_info_overlay.pal_vm_info$r_tc_info_fields.pal_vm_info$b_num_setsp#define pal_vm_info$b_num_ways pal_vm_info$r_tc_info_overlay.pal_vm_info$r_tc_info_fields.pal_vm_info$b_num_waysv#define pal_vm_info$w_num_entries pal_vm_info$r_tc_info_overlay.pal_vm_info$r_tc_info_fields.pal_vm_info$w_num_entriesd#define pal_vm_info$v_pf pal_vm_info$r_tc_B!info_overlay.pal_vm_info$r_tc_info_fields.pal_vm_info$v_pfn#define pal_vm_info$v_unified pal_vm_info$r_tc_info_overlay.pal_vm_info$r_tc_info_fields.pal_vm_info$v_unifiedr#define pal_vm_info$v_tr_reduce pal_vm_info$r_tc_info_overlay.pal_vm_info$r_tc_info_fields.pal_vm_info$v_tr_reduce"#endif /* #if !defined(__VAXC) */ N/*++ */N/* Definitions needed by PAL_VM_PAGE_SIZE */N/*-- C! */N/* return structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_vm_pgsize {#pragma __nomember_alignment, unsigned __int64 pal_vm_pgsize$q_status;2 unsigned __int64 pal_vm_pgsize$q_insert_pages;1 unsiD!gned __int64 pal_vm_pgsize$q_purge_pages;+ unsigned __int64 pal_vm_pgsize$q_spare; } PAL_VM_PGSIZE;N/* bits masks */N#define IA64_PAL$M_VM_PGSIZE_4KB 4096 /* (0x1UL << 12) */N#define IA64_PAL$M_VM_PGSIZE_8KB 8192 /* (0x1UL << 13) */N#define IA64_PAL$M_VM_PGSIZE_16KB 16384 /* (0x1UL << 14) */N#define IA64_PAL$M_VM_PGSIZE_32KB 32768 /* (0x1UL << 15) E! */N#define IA64_PAL$M_VM_PGSIZE_64KB 65536 /* (0x1UL << 16) */N#define IA64_PAL$M_VM_PGSIZE_128KB 131072 /* (0x1UL << 17) */N#define IA64_PAL$M_VM_PGSIZE_256KB 262144 /* (0x1UL << 18) */N#define IA64_PAL$M_VM_PGSIZE_512KB 524288 /* (0x1UL << 19) */N#define IA64_PAL$M_VM_PGSIZE_1MB 1048576 /* (0x1UL << 20) */N#define IA64_PAL$M_VM_PGSIZE_2MB 2097152 /* (0x1UL << 21) */N#define IA64_PAL$M_VF!M_PGSIZE_4MB 4194304 /* (0x1UL << 22) */N#define IA64_PAL$M_VM_PGSIZE_8MB 8388608 /* (0x1UL << 23) */N#define IA64_PAL$M_VM_PGSIZE_16MB 16777216 /* (0x1UL << 24) */N#define IA64_PAL$M_VM_PGSIZE_32MB 33554432 /* (0x1UL << 25) */N#define IA64_PAL$M_VM_PGSIZE_64MB 67108864 /* (0x1UL << 26) */N#define IA64_PAL$M_VM_PGSIZE_128MB 134217728 /* (0x1UL << 27) */N#define IA64_PAL$M_VM_PGSIZE_256MB 268435456 /G!* (0x1UL << 28) */N#define IA64_PAL$M_VM_PGSIZE_512MB 536870912 /* (0x1UL << 29) */N#define IA64_PAL$M_VM_PGSIZE_1GB 1073741824 /* (0x1UL << 30) */N#define IA64_PAL$M_VM_PGSIZE_2GB -2147483648 /* (0x1UL << 31) */N/*++ */N/* Definitions needed for PAL_VM_SUMMARY */N/*-- H! */N/* return structure */#define PAL_VM_SUMMARY$M_VW 0x1(#define PAL_VM_SUMMARY$M_PADDR_SIZE 0xFE c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _pal_vm_summary {#pragma __nomember_alignment- unsigned __int64 pal_vm_summary$q_status; __union {0 unsigned __iI!nt64 pal_vm_summary$q_info1; __struct {L unsigned pal_vm_summary$v_vw : 1; /* (0x1UL << 0) */N unsigned pal_vm_summary$v_paddr_size : 7; /* (0x7fUL << 1) */N unsigned char pal_vm_summary$b_key_size; /* (0xffUL << 8) */N unsigned char pal_vm_summary$b_max_pkr; /* (0xffUL << 16) */N unsigned char pal_vm_summary$b_hash_id; /* (0xffUL << 24) */N unsigned char pal_vm_summary$b_max_dtr; /* ( J!0xffUL << 32) */N unsigned char pal_vm_summary$b_max_itr; /* (0xffUL << 40) */N unsigned char pal_vm_summary$b_uniq_tc; /* (0xffUL << 48) */N unsigned char pal_vm_summary$b_tc_levels; /* (0xffUL << 56) */, } pal_vm_summary$r_info1_fields;, } pal_vm_summary$r_vm_info1_overlay; __union {0 unsigned __int64 pal_vm_summary$q_info2; __struct {N unsigned char pal_vm_summary$b_va_msb; /* (0xffUL K!<< 0) */N unsigned char pal_vm_summary$b_rid_size; /* (0xffUL << 8) */, } pal_vm_summary$r_info2_fields;, } pal_vm_summary$r_vm_info2_overlay;, unsigned __int64 pal_vm_summary$q_spare; } PAL_VM_SUMMARY; #if !defined(__VAXC)W#define pal_vm_summary$q_info1 pal_vm_summary$r_vm_info1_overlay.pal_vm_summary$q_info1o#define pal_vm_summary$v_vw pal_vm_summary$r_vm_info1_overlay.pal_vm_summary$r_info1_fields.pal_vm_summary$v_vw#define pal_vm_sL!ummary$v_paddr_size pal_vm_summary$r_vm_info1_overlay.pal_vm_summary$r_info1_fields.pal_vm_summary$v_paddr_size{#define pal_vm_summary$b_key_size pal_vm_summary$r_vm_info1_overlay.pal_vm_summary$r_info1_fields.pal_vm_summary$b_key_sizey#define pal_vm_summary$b_max_pkr pal_vm_summary$r_vm_info1_overlay.pal_vm_summary$r_info1_fields.pal_vm_summary$b_max_pkry#define pal_vm_summary$b_hash_id pal_vm_summary$r_vm_info1_overlay.pal_vm_summary$r_info1_fields.pal_vm_summary$b_hash_idy#define pal_vm_sumM!mary$b_max_dtr pal_vm_summary$r_vm_info1_overlay.pal_vm_summary$r_info1_fields.pal_vm_summary$b_max_dtry#define pal_vm_summary$b_max_itr pal_vm_summary$r_vm_info1_overlay.pal_vm_summary$r_info1_fields.pal_vm_summary$b_max_itry#define pal_vm_summary$b_uniq_tc pal_vm_summary$r_vm_info1_overlay.pal_vm_summary$r_info1_fields.pal_vm_summary$b_uniq_tc}#define pal_vm_summary$b_tc_levels pal_vm_summary$r_vm_info1_overlay.pal_vm_summary$r_info1_fields.pal_vm_summary$b_tc_levelsW#define pal_vm_summary$qN!_info2 pal_vm_summary$r_vm_info2_overlay.pal_vm_summary$q_info2w#define pal_vm_summary$b_va_msb pal_vm_summary$r_vm_info2_overlay.pal_vm_summary$r_info2_fields.pal_vm_summary$b_va_msb{#define pal_vm_summary$b_rid_size pal_vm_summary$r_vm_info2_overlay.pal_vm_summary$r_info2_fields.pal_vm_summary$b_rid_size"#endif /* #if !defined(__VAXC) */ N/*++ */N/* Definitions used by PAL_FIXED_ADDR O! */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _pal_fixed_addr {#pragma __nomember_alignment- unsigned __int64 pal_fixed_addr$q_status;. unsigned __int64 pal_fixed_addr$q_address;- unsigned __int64 pal_fixed_addr$q_spare1;- unsigned __i P!nt64 pal_fixed_addr$q_spare2; } PAL_FIXED_ADDR;N/*++ */N/* Definitions used by PAL_MEM_ATTRIB */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _Q!pal_mem_attrib {#pragma __nomember_alignment- unsigned __int64 pal_mem_attrib$q_status; __union {1 unsigned __int64 pal_mem_attrib$q_attrib; __struct {2 unsigned char pal_mem_attrib$b_attrib;1 } pal_mem_attrib$r_mem_attrib_fields;- } pal_mem_attrib$r_mem_attrib_overla;- unsigned __int64 pal_mem_attrib$q_spare1;- unsigned __int64 pal_mem_attrib$q_spare2; } PAL_MEM_ATTRIB; #if !defined(__VAXC)Z#define pal_mem_attribR!$q_attrib pal_mem_attrib$r_mem_attrib_overla.pal_mem_attrib$q_attrib}#define pal_mem_attrib$b_attrib pal_mem_attrib$r_mem_attrib_overla.pal_mem_attrib$r_mem_attrib_fields.pal_mem_attrib$b_attrib"#endif /* #if !defined(__VAXC) */ N/*++ */N/* Definitions used by PAL_TR_READ */N/* (Not sure what AV, PV, DV, MV are for) */N/*-- S! */#define PAL_TR_VALID$M_AV 0x1#define PAL_TR_VALID$M_PV 0x2#define PAL_TR_VALID$M_DV 0x4#define PAL_TR_VALID$M_MV 0x8&#define PAL_TR_VALID$M_RSV1 0xFFFFFFF0.#define PAL_TR_VALID$M_RSV2 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pal_tr_valid {#pragma __noT!member_alignment( unsigned __int64 pal_tr_valid$q_val; __struct {' unsigned pal_tr_valid$v_av : 1;' unsigned pal_tr_valid$v_pv : 1;' unsigned pal_tr_valid$v_dv : 1;' unsigned pal_tr_valid$v_mv : 1;* unsigned pal_tr_valid$v_rsv1 : 28;* unsigned pal_tr_valid$v_rsv2 : 32;' } pal_tr_valid$r_tr_valid_bits;+ unsigned __int64 pal_tr_valid$q_spare1;+ unsigned __int64 pal_tr_valid$q_spare2; } PAL_TR_VALID; #if !defined U!(__VAXC)H#define pal_tr_valid$v_av pal_tr_valid$r_tr_valid_bits.pal_tr_valid$v_avH#define pal_tr_valid$v_pv pal_tr_valid$r_tr_valid_bits.pal_tr_valid$v_pvH#define pal_tr_valid$v_dv pal_tr_valid$r_tr_valid_bits.pal_tr_valid$v_dvH#define pal_tr_valid$v_mv pal_tr_valid$r_tr_valid_bits.pal_tr_valid$v_mvL#define pal_tr_valid$v_rsv1 pal_tr_valid$r_tr_valid_bits.pal_tr_valid$v_rsv1L#define pal_tr_valid$v_rsv2 pal_tr_valid$r_tr_valid_bits.pal_tr_valid$v_rsv2"#endif /* #if !defined(__VAXC) */ N/*++ V! */N/* Definitions used by PAL_LOGICAL_TO_PHYSICAL */N/*-- */'#define PAL_LOG_TO_PHY$M_NUM_LOG 0xFFFF%#define PAL_LOG_TO_PHY$M_TPC 0xFF0000(#define PAL_LOG_TO_PHY$M_RSV1 0xFF000000)#define PAL_LOG_TO_PHY$M_CPP 0xFF00000000,#define PAL_LOG_TO_PHY$M_RSV2 0xFF0000000000.#define PAL_LOG_TO_PHY$M_PPID 0xFF0000000000000#define W!PAL_LOG_TO_PHY$M_RSV3 0xFF00000000000000##define PAL_LOG_TO_PHY$M_TID 0xFFFF(#define PAL_LOG_TO_PHY$M_RSV4 0xFFFF0000+#define PAL_LOG_TO_PHY$M_CID 0xFFFF000000000#define PAL_LOG_TO_PHY$M_RSV5 0xFFFF000000000000"#define PAL_LOG_TO_PHY$M_LA 0xFFFF(#define PAL_LOG_TO_PHY$M_RSV6 0xFFFF00000#define PAL_LOG_TO_PHY$M_RSV7 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#praX!gma __nomember_alignment#endif typedef struct _pal_log_to_phy {#pragma __nomember_alignment- unsigned __int64 pal_log_to_phy$q_status; __struct {/ unsigned pal_log_to_phy$v_num_log : 16;* unsigned pal_log_to_phy$v_tpc : 8;+ unsigned pal_log_to_phy$v_rsv1 : 8;* unsigned pal_log_to_phy$v_cpp : 8;+ unsigned pal_log_to_phy$v_rsv2 : 8;+ unsigned pal_log_to_phy$v_ppid : 8;+ unsigned pal_log_to_phy$v_rsv3 : 8;( } pal_log_toY!_phy$r_log_overview; __struct {+ unsigned pal_log_to_phy$v_tid : 16;, unsigned pal_log_to_phy$v_rsv4 : 16;+ unsigned pal_log_to_phy$v_cid : 16;, unsigned pal_log_to_phy$v_rsv5 : 16;% } pal_log_to_phy$r_log_info1; __struct {* unsigned pal_log_to_phy$v_la : 16;, unsigned pal_log_to_phy$v_rsv6 : 16;, unsigned pal_log_to_phy$v_rsv7 : 32;% } pal_log_to_phy$r_log_info2; } PAL_LOG_TO_PHY; #if !defined(__VAXC)Z!W#define pal_log_to_phy$v_num_log pal_log_to_phy$r_log_overview.pal_log_to_phy$v_num_logO#define pal_log_to_phy$v_tpc pal_log_to_phy$r_log_overview.pal_log_to_phy$v_tpcO#define pal_log_to_phy$v_cpp pal_log_to_phy$r_log_overview.pal_log_to_phy$v_cppQ#define pal_log_to_phy$v_ppid pal_log_to_phy$r_log_overview.pal_log_to_phy$v_ppidL#define pal_log_to_phy$v_tid pal_log_to_phy$r_log_info1.pal_log_to_phy$v_tidL#define pal_log_to_phy$v_cid pal_log_to_phy$r_log_info1.pal_log_to_phy$v_cidJ#define pa[!l_log_to_phy$v_la pal_log_to_phy$r_log_info2.pal_log_to_phy$v_la"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __IA64_PALDEF_LOADED */ wwp<[UM/*****************************************\!**********************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP ]! **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** ^! **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */K/* Source: 14-FEB-2008 15:31:23 $1$DGA8345:[LIB_H.SRC]IA64_SALDEF.SDL;1 *//************************************************************************************* _!*******************************************//*** MODULE $IA64_SALDEF ***/#ifndef __IA64_SALDEF_LOADED#define __IA64_SALDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /*`! And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ a! */N/* SAL Procedure Function IDs */N/* */6/* 0x01XXXXXX Architected SAL functional group. */B/* 0x02XXXXXX - 0x03XXXXXX OEM SAL functional group. */B/* 0x04XXXXXX - 0xFFFFFFFF Reserved. */N/* */R/* "Itan b!ium Processor Family System Abstraction Layer Specification, July 2001" */N/* Table 9-2, Section 9.3, pp. 9-4 */N/*-- */'#define IA64_SAL$K_SET_VECTORS 16777216*#define IA64_SAL$K_GET_STATE_INFO 16777217/#define IA64_SAL$K_GET_STATE_INFO_SIZE 16777218,#define IA64_SAL$K_CLEAR_STATE_INFO 16777219%#define IA64_SAL$K_MC_RENDEZ 16777220)#define IA64_SAL$K_MC_SET_PARAMS 16777221)#def c!ine IA64_SAL$K_REG_PHYS_ADDR 16777222'#define IA64_SAL$K_CACHE_FLUSH 16777224&#define IA64_SAL$K_CACHE_INIT 16777225(#define IA64_SAL$K_PCI_CFG_READ 16777232)#define IA64_SAL$K_PCI_CFG_WRITE 16777233%#define IA64_SAL$K_FREQ_BASE 16777234,#define IA64_SAL$K_PHYSICAL_ID_INFO 16777235&#define IA64_SAL$K_UPDATE_PAL 16777248N/*++ */N/* SAL Procedure Generic Return Structure */N/* d! */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 8.2, pp. 8-5 */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif e!typedef struct _sal_ret {#pragma __nomember_alignment __int64 sal_ret$q_status;$ unsigned __int64 sal_ret$q_ret1;$ unsigned __int64 sal_ret$q_ret2;$ unsigned __int64 sal_ret$q_ret3; } SAL_RET;#define SAL_RET$K_LENGTH 32N/*++ */N/* SAL Procedure Generic Return Status */N/* */I/* Each SAL proc f!edure uses a subset of these return status values. */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Table 8-5, Section 8.2.2.1, pp. 8-7 */N/*-- */#define IA64_SAL$K_MOREINFO 3#define IA64_SAL$K_WARMBOOT 2#define IA64_SAL$K_OVRFLW 1#define IA64_SAL$K_SUCCESS 0 g!#define IA64_SAL$K_UNIMPL -1#define IA64_SAL$K_INVALARG -2#define IA64_SAL$K_FAIL -3#define IA64_SAL$K_VANOTREG -4#define IA64_SAL$K_NOINFO -5#define IA64_SAL$K_BUFREQ -9#define IA64_SAL$K_RETRY -15N/* SAL Procedures */N/*++ */N/* SAL_SET_VECTORS */N/* h! */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-21 */N/*-- */N/* Values for VEC_TYPE Argument */#define SAL_SV$K_MCA 0#define SAL_SV$K_INIT 1#define SAL_SV$K_BOOT_RENDEZ 2N/* Structure for LEN_CS_N Argument i! */$#define SAL_SV$M_LEN_PROC 0xFFFFFFFF*#define SAL_SV$M_CHECKSUM_PRES 0x100000000,#define SAL_SV$M_MOD_CHECKSUM 0xFF0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif!typedef struct _sal_sv_len_cs_n {#pragma __nomember_alignment __union {+ unsigned __int64 sal_sv$q_len_cs_n; __struct {, unsigned sal_s j!v$v_len_proc : 32;0 unsigned sal_sv$v_checksum_pres : 1;+ unsigned sal_sv$v_reserved : 7;/ unsigned sal_sv$v_mod_checksum : 8;. unsigned sal_sv$v_reserved_1 : 16;' } sal_sv$r_len_cs_n_fields;$ } sal_sv$r_len_cs_n_overlay; } SAL_SV_LEN_CS_N; #if !defined(__VAXC)E#define sal_sv$q_len_cs_n sal_sv$r_len_cs_n_overlay.sal_sv$q_len_cs_n^#define sal_sv$v_len_proc sal_sv$r_len_cs_n_overlay.sal_sv$r_len_cs_n_fields.sal_sv$v_len_ k!proch#define sal_sv$v_checksum_pres sal_sv$r_len_cs_n_overlay.sal_sv$r_len_cs_n_fields.sal_sv$v_checksum_presf#define sal_sv$v_mod_checksum sal_sv$r_len_cs_n_overlay.sal_sv$r_len_cs_n_fields.sal_sv$v_mod_checksum"#endif /* #if !defined(__VAXC) */ "#define SAL_SV_LEN_CS_N$K_LENGTH 8N/* Return Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignmentl! __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_sv_ret {#pragma __nomember_alignment __int64 sal_sv_ret$q_status;+ unsigned __int64 sal_sv_ret$q_reserved;- unsigned __int64 sal_sv_ret$q_reserved_1;- unsigned __int64 sal_sv_ret$q_reserved_2; } SAL_SV_RET;#define SAL_SV_RET$K_LENGTH 32N/*++ */N/* SAL_GET_STATE_INFO */ m!N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-10 */N/*-- */N/* Values for TYPE Argument */#define SAL_GSI$K_MCA 0#define SAL_GSI$K_INIT 1#define SAL_GSI$K_CMC 2#define SAL_GSI$K_CPE n!3 #define SAL_GSI$K_DECONFIGURED 4N/* Return Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_gsi_ret {#pragma __nomember_alignment! __int64 sal_gsi_ret$q_status;- unsigned __int64 sal_gsi_ret$q_total_len;, unsigned __int64 sal_gsi_ret$q_reserved;. o! unsigned __int64 sal_gsi_ret$q_reserved_1; } SAL_GSI_RET;#define SAL_GSI_RET$K_LENGTH 32N/*++ */N/* SAL_GET_STATE_INFO_SIZE */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-12 */N/* p!-- */N/* Values for TYPE Argument */#define SAL_GSIS$K_MCA 0#define SAL_GSIS$K_INIT 1#define SAL_GSIS$K_CMC 2#define SAL_GSIS$K_CPE 3!#define SAL_GSIS$K_DECONFIGURED 4N/* Return Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_aq!lignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_gsis_ret {#pragma __nomember_alignment" __int64 sal_gsis_ret$q_status;) unsigned __int64 sal_gsis_ret$q_size;- unsigned __int64 sal_gsis_ret$q_reserved;/ unsigned __int64 sal_gsis_ret$q_reserved_1; } SAL_GSIS_RET; #define SAL_GSIS_RET$K_LENGTH 32N/*++ */N/* SAL_CLEAR_STATE_INFO r! */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-8 */N/*-- */N/* Values for TYPE Argument */#define SAL_CSI$K_MCA 0#define SAL_CSI$K_INIT 1#define SAL_CSI$K_CMC 2#defins!e SAL_CSI$K_CPE 3 #define SAL_CSI$K_DECONFIGURED 4N/* Return Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_csi_ret {#pragma __nomember_alignment! __int64 sal_csi_ret$q_status;, unsigned __int64 sal_csi_ret$q_reserved;. unsigned __int64 sal_csi_ret$q t!_reserved_1;. unsigned __int64 sal_csi_ret$q_reserved_2; } SAL_CSI_RET;#define SAL_CSI_RET$K_LENGTH 32N/*++ */N/* SAL_MC_RENDEZ */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-13 u! */N/*-- */N/* Return Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_mcr_ret {#pragma __nomember_alignment! __int64 sal_mcr_ret$q_status;, unsigned __int64 sal_mcr_ret$q_reser v!ved;. unsigned __int64 sal_mcr_ret$q_reserved_1;. unsigned __int64 sal_mcr_ret$q_reserved_2; } SAL_MCR_RET;#define SAL_MCR_RET$K_LENGTH 32N/*++ */N/* SAL_MC_SET_PARAMS */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-15 w! */N/*-- */N/* Values for PARAM_TYPE Argument */#define SAL_MCSP$K_RENDEZ_INT 1#define SAL_MCSP$K_WAKE_UP 2#define SAL_MCSP$K_CPE_VEC 3N/* Values for I_OR_M Argument */#define SAL_MCSP$K_INT_VEC 1#define SAL_MCSP$K_MEM_ADDR 2N/* Structure for MCA_OPT Argument x! */ #define SAL_MCSP$M_RZ_ALWAYS 0x1 #define SAL_MCSP$M_BINIT_ESC 0x2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif"typedef struct _sal_mcsp_mca_opt {#pragma __nomember_alignment __union {, unsigned __int64 sal_mcsp$q_mca_opt; __struct {. unsigned sal_mcsp$v_rz_always : 1;. unsigned s y!al_mcsp$v_binit_esc : 1;. unsigned sal_mcsp$v_reserved : 30;0 unsigned sal_mcsp$v_reserved_1 : 32;( } sal_mcsp$r_mca_opt_fields;% } sal_mcsp$r_mca_opt_overlay; } SAL_MCSP_MCA_OPT; #if !defined(__VAXC)H#define sal_mcsp$q_mca_opt sal_mcsp$r_mca_opt_overlay.sal_mcsp$q_mca_optf#define sal_mcsp$v_rz_always sal_mcsp$r_mca_opt_overlay.sal_mcsp$r_mca_opt_fields.sal_mcsp$v_rz_alwaysf#define sal_mcsp$v_binit_esc sal_mcsp$r_mca_opt_overlay.sal_mcsp$r_mca z!_opt_fields.sal_mcsp$v_binit_escd#define sal_mcsp$v_reserved sal_mcsp$r_mca_opt_overlay.sal_mcsp$r_mca_opt_fields.sal_mcsp$v_reservedh#define sal_mcsp$v_reserved_1 sal_mcsp$r_mca_opt_overlay.sal_mcsp$r_mca_opt_fields.sal_mcsp$v_reserved_1"#endif /* #if !defined(__VAXC) */ ##define SAL_MCSP_MCA_OPT$K_LENGTH 8N/* Return Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'{!#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_mcsp_ret {#pragma __nomember_alignment" __int64 sal_mcsp_ret$q_status;1 unsigned __int64 sal_mcsp_ret$q_time_out_min;- unsigned __int64 sal_mcsp_ret$q_reserved;/ unsigned __int64 sal_mcsp_ret$q_reserved_1; } SAL_MCSP_RET; #define SAL_MCSP_RET$K_LENGTH 32N/*++ */N/* SAL_REG_PHYS_ADDR |! */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-20 */N/*-- */N/* Value for PHYS_ENTITY Argument */#define SAL_RPA$K_PAL_PROC 0N/* Return Structure }! */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_rpa_ret {#pragma __nomember_alignment! __int64 sal_rpa_ret$q_status;, unsigned __int64 sal_rpa_ret$q_reserved;. unsigned __int64 sal_rpa_ret$q_reserved_1;. unsigned __int64 sal_rpa_ret$q_reserved_2; } SAL_RPA_RET;~!#define SAL_RPA_RET$K_LENGTH 32N/*++ */N/* SAL_CACHE_FLUSH */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-5 */N/*-- ! */N/* Values for I_OR_D Argument */#define SAL_CF$K_FLUSH_ICACHE 1#define SAL_CF$K_FLUSH_DCACHE 2#define SAL_CF$K_FLUSH_BOTH 3 #define SAL_CF$K_MAKE_COHERENT 4N/* Return Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftype !def struct _sal_cf_ret {#pragma __nomember_alignment __int64 sal_cf_ret$q_status;+ unsigned __int64 sal_cf_ret$q_reserved;- unsigned __int64 sal_cf_ret$q_reserved_1;- unsigned __int64 sal_cf_ret$q_reserved_2; } SAL_CF_RET;#define SAL_CF_RET$K_LENGTH 32N/*++ */N/* SAL_CACHE_INIT */N/* ! */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-7 */N/*-- */N/* Return Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma !__nomember_alignment#endiftypedef struct _sal_ci_ret {#pragma __nomember_alignment __int64 sal_ci_ret$q_status;+ unsigned __int64 sal_ci_ret$q_reserved;- unsigned __int64 sal_ci_ret$q_reserved_1;- unsigned __int64 sal_ci_ret$q_reserved_2; } SAL_CI_RET;#define SAL_CI_RET$K_LENGTH 32N/*++ */N/* SAL_PCI_CFG_READ */N/* ! */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-18 */N/*-- */N/* Structure for ADDR Argument */!#define SAL_PCICR$M_REG_ADDR 0xFF"#define SAL_PCICR$M_FUNC_NUM 0x700"#define SAL_PCICR$M_DEV_NUM 0xF800$#define SAL_PCICR$M_BU!S_NUM 0xFF0000&#define SAL_PCICR$M_SEG_NUM 0xFF000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _sal_pcicr_addr {#pragma __nomember_alignment __union {* unsigned __int64 sal_pcicr$q_addr; __struct {. unsigned sal_pcicr$v_reg_addr : 8;. unsigned sal_pcicr$v_func_num : 3;- un !signed sal_pcicr$v_dev_num : 5;- unsigned sal_pcicr$v_bus_num : 8;- unsigned sal_pcicr$v_seg_num : 8;/ unsigned sal_pcicr$v_reserved : 32;& } sal_pcicr$r_addr_fields;# } sal_pcicr$r_addr_overlay; } SAL_PCICR_ADDR; #if !defined(__VAXC)B#define sal_pcicr$q_addr sal_pcicr$r_addr_overlay.sal_pcicr$q_addrb#define sal_pcicr$v_reg_addr sal_pcicr$r_addr_overlay.sal_pcicr$r_addr_fields.sal_pcicr$v_reg_addrb#define sal_pcicr$v_func_num s!al_pcicr$r_addr_overlay.sal_pcicr$r_addr_fields.sal_pcicr$v_func_num`#define sal_pcicr$v_dev_num sal_pcicr$r_addr_overlay.sal_pcicr$r_addr_fields.sal_pcicr$v_dev_num`#define sal_pcicr$v_bus_num sal_pcicr$r_addr_overlay.sal_pcicr$r_addr_fields.sal_pcicr$v_bus_num`#define sal_pcicr$v_seg_num sal_pcicr$r_addr_overlay.sal_pcicr$r_addr_fields.sal_pcicr$v_seg_num"#endif /* #if !defined(__VAXC) */ !#define SAL_PCICR_ADDR$K_LENGTH 8N/* Return Structure ! */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_pcicr_ret {#pragma __nomember_alignment# __int64 sal_pcicr_ret$q_status;+ unsigned __int64 sal_pcicr_ret$q_value;. unsigned __int64 sal_pcicr_ret$q_reserved;0 unsigned __int64 sal_pcicr_ret$q_reserved_1; } SAL_PCICR_RET;!#define SAL_PCICR_RET$K_LENGTH! 32N/*++ */N/* SAL_PCI_CFG_WRITE */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-19 */N/*-- */N/* Structure for! ADDR Argument */!#define SAL_PCICW$M_REG_ADDR 0xFF"#define SAL_PCICW$M_FUNC_NUM 0x700"#define SAL_PCICW$M_DEV_NUM 0xF800$#define SAL_PCICW$M_BUS_NUM 0xFF0000&#define SAL_PCICW$M_SEG_NUM 0xFF000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _sal_pcicw_addr {#pragma __nomember_alignment! __union {* unsigned __int64 sal_pcicw$q_addr; __struct {. unsigned sal_pcicw$v_reg_addr : 8;. unsigned sal_pcicw$v_func_num : 3;- unsigned sal_pcicw$v_dev_num : 5;- unsigned sal_pcicw$v_bus_num : 8;- unsigned sal_pcicw$v_seg_num : 8;/ unsigned sal_pcicw$v_reserved : 32;& } sal_pcicw$r_addr_fields;# } sal_pcicw$r_addr_overlay; } SAL_PCICW_ADDR; #if !defined(__VAXC)B#def!ine sal_pcicw$q_addr sal_pcicw$r_addr_overlay.sal_pcicw$q_addrb#define sal_pcicw$v_reg_addr sal_pcicw$r_addr_overlay.sal_pcicw$r_addr_fields.sal_pcicw$v_reg_addrb#define sal_pcicw$v_func_num sal_pcicw$r_addr_overlay.sal_pcicw$r_addr_fields.sal_pcicw$v_func_num`#define sal_pcicw$v_dev_num sal_pcicw$r_addr_overlay.sal_pcicw$r_addr_fields.sal_pcicw$v_dev_num`#define sal_pcicw$v_bus_num sal_pcicw$r_addr_overlay.sal_pcicw$r_addr_fields.sal_pcicw$v_bus_num`#define sal_pcicw$v_seg_num sal_pcicw$r_addr_o!verlay.sal_pcicw$r_addr_fields.sal_pcicw$v_seg_num"#endif /* #if !defined(__VAXC) */ !#define SAL_PCICW_ADDR$K_LENGTH 8N/* Return Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_pcicw_ret {#pragma __nomember_alignment# __int64 sal_pcicw_ret$q_status;. ! unsigned __int64 sal_pcicw_ret$q_reserved;0 unsigned __int64 sal_pcicw_ret$q_reserved_1;0 unsigned __int64 sal_pcicw_ret$q_reserved_2; } SAL_PCICW_RET;!#define SAL_PCICW_RET$K_LENGTH 32N/*++ */N/* SAL_FREQ_BASE */N/* */R/* "Itanium Processor Family System Abstraction Layer Specific !ation, July 2001" */N/* Section 9.3, pp. 9-9 */N/*-- */N/* Values for CLOCK_TYPE Argument */#define SAL_FB$K_SYS_CLK_FREQ 0#define SAL_FB$K_INT_TIMER 1 #define SAL_FB$K_REAL_TIME_CLK 2N/* Return Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) ! /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_fb_ret {#pragma __nomember_alignment __int64 sal_fb_ret$q_status;+ unsigned __int64 sal_fb_ret$q_reserved;- unsigned __int64 sal_fb_ret$q_reserved_1;- unsigned __int64 sal_fb_ret$q_reserved_2; } SAL_FB_RET;#define SAL_FB_RET$K_LENGTH 32N/* Return structure for PHYSICAL_ID_INFO */ c#if !d !efined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_pid_ret {#pragma __nomember_alignment! __int64 sal_pid_ret$q_status;* unsigned short int sal_pid_ret$w_plid;0 unsigned short int sal_pid_ret$w_reserved_1;* unsigned int sal_pid_ret$l_reserved_2;. unsigned __int64 sal_pid_ret$q_reserved_3;. unsigned __int64 sal_pid_ret$q_res !erved_4; } SAL_PID_RET;#define SAL_PID_RET$K_LENGTH 32N/*++ */N/* SAL_UPDATE_PAL */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Section 9.3, pp. 9-21 */N/*-- ! */N/* Structure for PARAM_BUF Argument */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif$typedef struct _sal_upal_param_buf {#pragma __nomember_alignment) unsigned __int64 sal_upal$q_next_ptr;0 unsigned __int64 sal_upal$q_upd_dat_blk_ptr;+ unsigned char sal_upal$b!_checksum_flag;- unsigned char sal_upal$b_reserved_1 [15]; } SAL_UPAL_PARAM_BUF;!#define SAL_UPAL_PBUF$K_LENGTH 32N/* Structure for Update Data Block */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif&typedef struct _sal_upal_upd_dat_blk {#pragma __nomember_alignment$ unsigned int sal_upal$l_fw_s !ize;$ unsigned int sal_upal$l_fw_date;) unsigned short int sal_upal$w_fw_ver;% unsigned char sal_upal$b_fw_type;* unsigned char sal_upal$b_reserved [5];+ unsigned __int64 sal_upal$q_fw_vend_id;- unsigned char sal_upal$b_reserved_2 [40]; } SAL_UPAL_UPD_DAT_BLK;"#define SAL_UPAL_UDBLK$K_LENGTH 64N/* Return Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 !or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sal_upal_ret {#pragma __nomember_alignment" __int64 sal_upal_ret$q_status;/ unsigned __int64 sal_upal_ret$q_error_code;4 unsigned __int64 sal_upal_ret$q_scrbuf_size_req;- unsigned __int64 sal_upal_ret$q_reserved; } SAL_UPAL_RET; #define SAL_UPAL_RET$K_LENGTH 32N/* Value for ERROR_CODE Return Value */##define SAL_UPAL$K_I !NCOMP_FW_VER -1$#define SAL_UPAL$K_AUTH_TEST_FAIL -2!#define SAL_UPAL$K_INV_FW_COMP -3"#define SAL_UPAL$K_FW_NOT_ERASE -4!#define SAL_UPAL$K_WRITE_FAIL -10!#define SAL_UPAL$K_ERASE_FAIL -11 #define SAL_UPAL$K_READ_FAIL -12##define SAL_UPAL$K_INSUFF_SPACE -13N/* SAL System Table */N/*++ */N/* SAL System Table Header ! */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Table 3-2, Section 3.2.7, pp. 3-11 - 3-12 */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_a!lignment#endif typedef struct _sal_sys_tbl_hd {#pragma __nomember_alignment% unsigned char sal_sthd$b_sig [4];* unsigned int sal_sthd$l_total_tbl_len; __union {. unsigned short int sal_sthd$w_sal_rev; __struct {3 unsigned char sal_sthd$b_minor_sal_rev;3 unsigned char sal_sthd$b_major_sal_rev;( } sal_sthd$r_sal_rev_fields;% } sal_sthd$r_sal_rev_overlay;. unsigned short int sal_sthd$w_entry_count;& unsigned cha!r sal_sthd$b_checksum;* unsigned char sal_sthd$b_reserved [7]; __union {0 unsigned short int sal_sthd$w_sal_a_ver; __struct {5 unsigned char sal_sthd$b_minor_sal_a_ver;5 unsigned char sal_sthd$b_major_sal_a_ver;* } sal_sthd$r_sal_a_ver_fields;' } sal_sthd$r_sal_a_ver_overlay; __union {0 unsigned short int sal_sthd$w_sal_b_ver; __struct {5 unsigned char sal_sthd$b_minor_sal_b_ver;5 ! unsigned char sal_sthd$b_major_sal_b_ver;* } sal_sthd$r_sal_b_ver_fields;' } sal_sthd$r_sal_b_ver_overlay;) unsigned char sal_sthd$b_oem_id [32];- unsigned char sal_sthd$b_product_id [32];, unsigned char sal_sthd$b_reserved_1 [8]; } SAL_SYS_TBL_HD; #if !defined(__VAXC)H#define sal_sthd$w_sal_rev sal_sthd$r_sal_rev_overlay.sal_sthd$w_sal_revn#define sal_sthd$b_minor_sal_rev sal_sthd$r_sal_rev_overlay.sal_sthd$r_sal_rev_fields.sal_sthd$b_minor_sal_rev!n#define sal_sthd$b_major_sal_rev sal_sthd$r_sal_rev_overlay.sal_sthd$r_sal_rev_fields.sal_sthd$b_major_sal_revN#define sal_sthd$w_sal_a_ver sal_sthd$r_sal_a_ver_overlay.sal_sthd$w_sal_a_verv#define sal_sthd$b_minor_sal_a_ver sal_sthd$r_sal_a_ver_overlay.sal_sthd$r_sal_a_ver_fields.sal_sthd$b_minor_sal_a_verv#define sal_sthd$b_major_sal_a_ver sal_sthd$r_sal_a_ver_overlay.sal_sthd$r_sal_a_ver_fields.sal_sthd$b_major_sal_a_verN#define sal_sthd$w_sal_b_ver sal_sthd$r_sal_b_ver_overlay.sal_sthd$w_sal !_b_verv#define sal_sthd$b_minor_sal_b_ver sal_sthd$r_sal_b_ver_overlay.sal_sthd$r_sal_b_ver_fields.sal_sthd$b_minor_sal_b_verv#define sal_sthd$b_major_sal_b_ver sal_sthd$r_sal_b_ver_overlay.sal_sthd$r_sal_b_ver_fields.sal_sthd$b_major_sal_b_ver"#endif /* #if !defined(__VAXC) */ #define SAL_STHD$K_LENGTH 96N/*++ */N/* SAL System Table Entrypoint Descriptor Entry */N/* ! */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Table 3-4, Section 3.2.7.1, pp. 3-12 */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif!typedef struct _ !sal_sys_tbl_epd {#pragma __nomember_alignment) unsigned char sal_stepd$b_entry_type;+ unsigned char sal_stepd$b_reserved [7];4 unsigned __int64 sal_stepd$q_phys_addr_pal_proc;4 unsigned __int64 sal_stepd$q_phys_addr_sal_proc;( unsigned __int64 sal_stepd$q_gp_sal;, unsigned int sal_stepd$o_reserved_1 [4]; } SAL_SYS_TBL_EPD;#define SAL_STEPD$K_LENGTH 48N/*++ */N/* SAL System Table Memory Descrip !tor Entry */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Table 3-5, Section 3.2.7.2, pp. 3-13 - 3-14 */N/*-- */"#define SAL_STMD$M_NEED_VA_REG 0x1##define SAL_STMD$M_MEM_ATTR_SET 0x7#define SAL_STMD$M_WB 0x1#define SAL_STMD$M_UC 0x2#defin!e SAL_STMD$M_UCE 0x4#define SAL_STMD$M_WC 0x8 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _sal_sys_tbl_md {#pragma __nomember_alignment( unsigned char sal_stmd$b_entry_type; __union {- unsigned char sal_stmd$b_need_va_reg; __struct {0 unsigned sal_stmd$v_need_va_reg : 1;- unsigned ! sal_stmd$v_reserved : 7;, } sal_stmd$r_need_va_reg_fields;) } sal_stmd$r_need_va_reg_overlay; __union {. unsigned char sal_stmd$b_mem_attr_set; __struct {1 unsigned sal_stmd$v_mem_attr_set : 3;/ unsigned sal_stmd$v_reserved_1 : 5;- } sal_stmd$r_mem_attr_set_fields;* } sal_stmd$r_mem_attr_set_overlay;0 unsigned char sal_stmd$b_page_access_rights; __union {. unsigned char sal_stmd$b_mem_attr_!sup; __struct {' unsigned sal_stmd$v_wb : 1;' unsigned sal_stmd$v_uc : 1;( unsigned sal_stmd$v_uce : 1;' unsigned sal_stmd$v_wc : 1;- unsigned sal_stmd$v_reserved : 4;- } sal_stmd$r_mem_attr_sup_fields;* } sal_stmd$r_mem_attr_sup_overlay;( unsigned char sal_stmd$b_reserved_2;& unsigned char sal_stmd$b_mem_type;' unsigned char sal_stmd$b_mem_usage;* unsigned __int64 sal_stmd$q_phys_addr;) ! unsigned int sal_stmd$l_num_4k_pages;' unsigned int sal_stmd$l_reserved_3;- unsigned __int64 sal_stmd$q_oem_reserved; } SAL_SYS_TBL_MD; #if !defined(__VAXC)T#define sal_stmd$b_need_va_reg sal_stmd$r_need_va_reg_overlay.sal_stmd$b_need_va_regr#define sal_stmd$v_need_va_reg sal_stmd$r_need_va_reg_overlay.sal_stmd$r_need_va_reg_fields.sal_stmd$v_need_va_regW#define sal_stmd$b_mem_attr_set sal_stmd$r_mem_attr_set_overlay.sal_stmd$b_mem_attr_setv#define sal_stmd$v_mem_attr_set !sal_stmd$r_mem_attr_set_overlay.sal_stmd$r_mem_attr_set_fields.sal_stmd$v_mem_attr_setW#define sal_stmd$b_mem_attr_sup sal_stmd$r_mem_attr_sup_overlay.sal_stmd$b_mem_attr_supb#define sal_stmd$v_wb sal_stmd$r_mem_attr_sup_overlay.sal_stmd$r_mem_attr_sup_fields.sal_stmd$v_wbb#define sal_stmd$v_uc sal_stmd$r_mem_attr_sup_overlay.sal_stmd$r_mem_attr_sup_fields.sal_stmd$v_ucd#define sal_stmd$v_uce sal_stmd$r_mem_attr_sup_overlay.sal_stmd$r_mem_attr_sup_fields.sal_stmd$v_uceb#define sal_stmd$v_wc sal_ !stmd$r_mem_attr_sup_overlay.sal_stmd$r_mem_attr_sup_fields.sal_stmd$v_wc"#endif /* #if !defined(__VAXC) */ #define SAL_STMD$K_LENGTH 32N/*++ */N/* SAL System Table Platform Features Descriptor Entry */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Table 3-7, Section 3.2.7.3, pp. 3-1!5 - 3-16 */N/*-- */ #define SAL_STSFD$M_BUS_LOCK 0x1%#define SAL_STSFD$M_SYS_INT_REDIR 0x2*#define SAL_STSFD$M_PROC_IPI_MSG_REDIR 0x4 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif!typedef struct _sal_sys_tbl_sfd {#pragma __nomember_alignment) un!signed char sal_stsfd$b_entry_type; __union {+ unsigned char sal_stsfd$b_sys_feat; __struct {. unsigned sal_stsfd$v_bus_lock : 1;3 unsigned sal_stsfd$v_sys_int_redir : 1;8 unsigned sal_stsfd$v_proc_ipi_msg_redir : 1;. unsigned sal_stsfd$v_reserved : 5;* } sal_stsfd$r_sys_feat_fields;' } sal_stsfd$r_sys_feat_overlay;. unsigned char sal_stsfd$b_reserved_1 [14]; } SAL_SYS_TBL_SFD; #if !defined(_!_VAXC)N#define sal_stsfd$b_sys_feat sal_stsfd$r_sys_feat_overlay.sal_stsfd$b_sys_featj#define sal_stsfd$v_bus_lock sal_stsfd$r_sys_feat_overlay.sal_stsfd$r_sys_feat_fields.sal_stsfd$v_bus_lockt#define sal_stsfd$v_sys_int_redir sal_stsfd$r_sys_feat_overlay.sal_stsfd$r_sys_feat_fields.sal_stsfd$v_sys_int_redir~#define sal_stsfd$v_proc_ipi_msg_redir sal_stsfd$r_sys_feat_overlay.sal_stsfd$r_sys_feat_fields.sal_stsfd$v_proc_ipi_msg_redir"#endif /* #if !defined(__VAXC) */ #define SAL_STSFD$K_LENG !TH 16N/*++ */N/* SAL System Table Translation Register Descriptor Entry */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Table 3-8, Section 3.2.7.4, pp. 3-16 */N/*-- */ c#if !defin !ed(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif!typedef struct _sal_sys_tbl_trd {#pragma __nomember_alignment) unsigned char sal_sttrd$b_entry_type;- unsigned char sal_sttrd$b_trans_reg_type;, unsigned char sal_sttrd$b_trans_reg_num;+ unsigned char sal_sttrd$b_reserved [5];. unsigned __int64 sal_sttrd$q_va_trans_reg;5 unsigned __int64 sal_stt !rd$q_page_size_trans_reg;, unsigned __int64 sal_sttrd$q_reserved_1; } SAL_SYS_TBL_TRD;#define SAL_STRDD$K_LENGTH 32N/*++ */N/* SAL System Table Purge Translation Cache Coherence Domain Entry */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Table 3-9, Section 3.2.7.5, pp. 3-16 ! */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif#typedef struct _sal_sys_tbl_ptccd {#pragma __nomember_alignment+ unsigned char sal_stptccd$b_entry_type;- unsigned char sal_stptccd$b_reserved [3];/ unsigned int sal_stptccd$l_num_sys_coh !_dom;5 unsigned __int64 sal_stptccd$q_coh_dom_data_addr; } SAL_SYS_TBL_PTCCD;#define SAL_STPTCCD$K_LENGTH 16N/*++ */N/* SAL System Table Application Processor Wake-up Descriptor Entry */N/* */R/* "Itanium Processor Family System Abstraction Layer Specification, July 2001" */N/* Table 3-11, Section 3.2.7.6, pp. 3-17 ! */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif#typedef struct _sal_sys_tbl_apwud {#pragma __nomember_alignment+ unsigned char sal_stapwud$b_entry_type;2 unsigned char sal_stapwud$b_wake_up_mech_type;- unsigned char sal_stapwud$b_reserved [6]!;3 unsigned __int64 sal_stapwud$q_ex_intvec_10_ff; } SAL_SYS_TBL_APWUD;#define SAL_STAPWUD$K_LENGTH 16 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __IA64_SALDEF_LOADED */ ww<[UM/*****************************!**********************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Developm!ent, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/*!* **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */F/* Source: 22-APR-1993 11:17:44 $1$DGA8345:[LIB_H.SRC]IAFDEF.SDL;1 *//******************************************************************************* !*************************************************//*** MODULE $IAFDEF ***/#ifndef __IAFDEF_LOADED#define __IAFDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set! ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ ! */N/* IAF - IMAGE ACTIVATOR FIXUP SECTION */N/* */N/* THE IMAGE ACTIVATOR FIXUP SECTION IS AN IMAGE SECTION THAT IS CREATED */N/* BY THE LINKER AND USED BY THE IMAGE ACTIVATOR TO MODIFY THE IMAGE AS */N/* IT IS ACTIVATED. THIS IS DONE TO MAINTAIN THE POSITION INDEPENDENCE */N/* OF EXTERNAL REFERENCES. ! */N/*- */N#define IAF$K_LENGTH 64 /* Length of fixed area */N#define IAF$C_LENGTH 64 /* Length of fixed area */#define IAF$S_IAFDEF 64 typedef struct _iaf {N void *iaf$l_iaflink; /* Link for image activator use */N void *iaf$l_fixuplnk; /* Link for shareable image fixups */N unsigned short i !nt iaf$w_size; /* Size of fixed part of IAF */ __union {N unsigned short int iaf$w_flags; /* Flags */ __struct {N unsigned iaf$v_shr : 1; /* This is in a shareable image */' unsigned iaf$v_fill_0_ : 7; } iaf$r_flags_bits; } iaf$r_flags_overlay;N unsigned int iaf$l_g_fixoff; /* Offset to g^ address data */N unsigned int iaf$l_dotadroff; /* Offset to .addres!s fixup data */P unsigned int iaf$l_chgprtoff; /* Offset to isect change prot. data */N unsigned int iaf$l_shlstoff; /* Offset to shareable image list */R unsigned int iaf$l_shrimgcnt; /* Number of shareable images in shlst */W unsigned int iaf$l_shlextra; /* Number of extra shareable images allowed */O void *iaf$l_permctx; /* Permanent sharable image context */N int iafdef$$_fill_1; /* Spare ! */N int iafdef$$_fill_2; /* Spare */N int iafdef$$_fill_3; /* Spare */N int iafdef$$_fill_4; /* Spare */N int iafdef$$_fill_5; /* Spare */N int iafdef$$_fill_6; /* Spare */ } IAF; #if !defined(__VAXC)3#define iaf$w_flags iaf$r_flags_overlay.iaf$w_flags@#d!efine iaf$v_shr iaf$r_flags_overlay.iaf$r_flags_bits.iaf$v_shr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IAFDEF_LOADED */ ww<[UM/*************************************************!**************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **!/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** ! **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */G/* Source: 20-APR-2006 09:19:39 $1$DGA8345:[LIB_H.SRC]ICAPDEF.SDL;1 *//************************************************************************************************* !*******************************//*** MODULE $ICAPDEF ***/#ifndef __ICAPDEF_LOADED#define __ICAPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size defaul!t to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* + ! */N/* iCAP flags reside in ICAP$GQ_STATE */N/* */N/* - */#define ICAP$M_ICAP 0x1#define ICAP$M_TICAP 0x2#define ICAP$M_GWLM 0x4#define ICAP$M_RESERVED2 0x8#define ICAP$M_RESERVED3 0x10#define ICAP$M_RESERVED4 0x20 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined !(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _icap {#pragma __nomember_alignment __union {) unsigned __int64 icap$q_quadword; __struct {N unsigned icap$v_icap : 1; /* iCAP system detected */R unsigned icap$v_ticap : 1; /* Temporary capacity is being consumed */R unsigned icap$v_gwlm : 1; /* gwlm: global workload! manager in use */* unsigned icap$v_reserved2 : 1;* unsigned icap$v_reserved3 : 1;* unsigned icap$v_reserved4 : 1;( unsigned icap$v_fill_0_ : 2; } icap$r_flag_bits; } icap$r_icap_overlay; } ICAP; #if !defined(__VAXC);#define icap$q_quadword icap$r_icap_overlay.icap$q_quadwordD#define icap$v_icap icap$r_icap_overlay.icap$r_flag_bits.icap$v_icapF#define icap$v_ticap icap$r_icap_overlay.icap$r_flag_bits.icap$v_ticapD#d !efine icap$v_gwlm icap$r_icap_overlay.icap$r_flag_bits.icap$v_gwlmN#define icap$v_reserved2 icap$r_icap_overlay.icap$r_flag_bits.icap$v_reserved2N#define icap$v_reserved3 icap$r_icap_overlay.icap$r_flag_bits.icap$v_reserved3N#define icap$v_reserved4 icap$r_icap_overlay.icap$r_flag_bits.icap$v_reserved4"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size !__restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ICAPDEF_LOADED */ ww=[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not! **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized t!o be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************************************************* !*******/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 19-APR-1993 16:12:07 $1$DGA8345:[LIB_H.SRC]ICPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ICPDEF ***/#ifndef __ICPDEF_LOADED#define __ICPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifd!ef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define !__struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* ICP - CHANGE IMAGE SECTION PROTECTION DATA */N/* */N/* THIS STRUCTURE IS USED IN THE IMAGE FIXUP SECTION BY THE LI !NKER */N/* TO INFORM THE IMAGE ACTIVATOR OF THE IMAGE SECTIONS THAT NEED */N/* THEIR PROTECTION CHANGED. */N/*- */N#define ICP$K_LENGTH 8 /* size of one section's data */N#define ICP$C_LENGTH 8 /* size of one section's data */#define ICP$S_ICPDEF 8 typedef struct _icp {R void *icp$l_baseva; ! /* virtual address of start of section */V unsigned short int icp$w_npages; /* number of pages to change protection on */N unsigned short int icp$w_newprt; /* new protection */ } ICP; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma !__standard #endif /* __ICPDEF_LOADED */ ww`=[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of !HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. ! **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */G/* Source: 10-JUL-2003 11:11:43 $1$DGA8345:[LIB !_H.SRC]ICRDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ICRDDEF ***/#ifndef __ICRDDEF_LOADED#define __ICRDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save! /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC) !#define __union union#else#define __union variant_union#endif#endif N/* */N/* Invo Context Region Descriptor Definitions. The invo context region */N/* descriptor entry contains memory management data for an invo context */N/* region. */N/* */ #define ICRD$M_I!N_USE 0x1#define ICRD$M_RESERVED_1 0xFE#define ICRD$M_MODE 0x300(#define ICRD$M_RESERVED_FLAGS 0xFFFFFC00N#define ICRD$C_LENGTH 48 /* Length of ICRD */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _icrd {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pr !agmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *icrd$pq_base_va; /* Base address for address space */#else" unsigned __int64 icrd$pq_base_va;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *icrd$pq_guard_va; /* Address of high guard page */#else !# unsigned __int64 icrd$pq_guard_va;#endifN unsigned short int icrd$w_size; /* Structure size */N unsigned char icrd$b_type; /* Dynamic structure type */N unsigned char icrd$b_subtype; /* Dynamic structore subtype */ __union {N unsigned int icrd$l_flags; /* FLAGS longword */ __struct {N unsigned icrd$v_in_use : 1; /* Region is in use */N unsigned! icrd$v_reserved_1 : 7; /* */N unsigned icrd$v_mode : 2; /* Owner and page access mode */0 unsigned icrd$v_reserved_flags : 22; } icrd$r_flags_bits; } icrd$r_flags_overlay;N unsigned __int64 icrd$q_region_id; /* ID of virtual region */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit point!ers */R void *icrd$pq_first_free_va; /* First page in region not yet created */#else( unsigned __int64 icrd$pq_first_free_va;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *icrd$pq_next_va; /* Next VA for malloc */#else" unsigned __int64 icrd$pq_next_va;#endif } ICRD; #if !defined(__VAXC)6#define !icrd$l_flags icrd$r_flags_overlay.icrd$l_flagsJ#define icrd$v_in_use icrd$r_flags_overlay.icrd$r_flags_bits.icrd$v_in_useR#define icrd$v_reserved_1 icrd$r_flags_overlay.icrd$r_flags_bits.icrd$v_reserved_1F#define icrd$v_mode icrd$r_flags_overlay.icrd$r_flags_bits.icrd$v_modeZ#define icrd$v_reserved_flags icrd$r_flags_overlay.icrd$r_flags_bits.icrd$v_reserved_flags"#endif /* #if !defined(__VAXC) */   #ifdef __INITIAL_POINTER_SIZEj#pragma __required_pointer_size __save /* Sav!e current pointer size */j#pragma __required_pointer_size __long /* Pointers are 64-bit */jtypedef struct _icrd * ICRD_PQ; /* Pointer to an ICRD structure. */jtypedef struct _icrd ** ICRD_PPQ; /* Pointer to a pointer to an ICRD structure. */j#pragma __required_pointer_size __restore /* Return to previous pointer size */#else!typedef unsi!gned __int64 ICRD_PQ;"typedef unsigned __int64 ICRD_PPQ;)#endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ICRDDEF_LOADED */ ww=[UM/***********************************************!****************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP !**/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** ! **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 23-JAN-1997 11:19:54 $1$DGA8345:[LIB_H.SRC]IDBDEF.SDL;1 *//************************************************************************************************* !*******************************//*** MODULE $IDBDEF ***/#ifndef __IDBDEF_LOADED#define __IDBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default !to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ ! */N/* IDB - INTERRUPT DISPATCH BLOCK */N/* */N/* AN INTERRUPT DISPATCH BLOCK PROVIDES THE INFORMATION NECESSARY FOR A */N/* UNIT INDEPENDENT, BUT CONTROLLER SPECIFIC, INTERRUPT DISPATCHER TO */N/* DISPATCH INTERRUPTS TO THE PROPER DRIVER TO HANDLE AN INTERRUPT ON */N/* A DEVICE UNIT. ! */N/*- */#define IDB$M_CRAM_ALLOC 0x1#define IDB$M_VLE 0x2#define IDB$M_NORESIZE 0x4#define IDB$M_MCJ 0x8#define IDB$M_SHARED_INT 0x10"#define IDB$M_DISTRIBUTED_INT 0x20#define IDB$M_ISR_CALLABLE 0x40N#define IDB$K_BASE_LENGTH 56 /*length without UCBLST */N#define IDB$C_BASE_LENGTH 56 /*length without UCBLST */  9#ifdef __cplusplus /* Define st!ructure prototypes */ struct _ucb; struct _cram; struct _spl; struct _adp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _idb {#pragma __nomember_alignmentN unsigned __int64 idb$q_csr; /*CONTROLLER CSR "ADDRESS" */N unsigned short int idb$w_size; /*SIZE OF IDB IN BYTES! */N unsigned char idb$b_type; /*STRUCTURE TYPE OF IDB */ char idb$b_spare;N unsigned short int idb$w_units; /*NUMBER OF UNITS (SIZE OF UCBLST) */N unsigned short int idb$w_tt_enable; /* DZ32 line enable field */N struct _ucb *idb$ps_owner; /*OWNER UCB ADDRESS */N struct _cram *idb$ps_cram; /*Per-controller CRAM list */N struct _spl *idb$ps_spl; /*ADDRESS OF DEVICE SPIN !LOCK */N struct _adp *idb$ps_adp; /*ADDRESS OF ADAPTER CONTROL BLOCK */ __union {N unsigned int idb$l_flags; /* IDB flags */ __struct {c unsigned idb$v_cram_alloc : 1; /* $LOAD_DRIVER has done CRAM allocation for this IDB */N unsigned idb$v_vle : 1; /* IDB$L_VECTOR points to a VLE */Y unsigned idb$v_noresize : 1; /* IDB isn't in pool and shouldn't be resized */N unsign !ed idb$v_mcj : 1; /* IDB$Q_CSR points to an MCJ */N unsigned idb$v_shared_int : 1; /* Connected as Shared Interrupt */X unsigned idb$v_distributed_int : 1; /* Connected as Distributed Interrupt */S unsigned idb$v_isr_callable : 1; /* Ints can be delivered to the ISR */' unsigned idb$v_fill_0_ : 1; } idb$r_flags_bits; } idb$r_flags_overlay;N unsigned int idb$l_device_specific; /*Available to device drivers */N ! int idb$l_vector; /*SCB offset for interrupts */N void *idb$ps_auxstruc; /*driver specific data */R unsigned int idb$l_interrupt_cpu; /*Target CPU for Distributed Interrupts */N unsigned int idb$l_reserved; /*...for future expansion */N struct _ucb *idb$l_ucblst [8]; /*UCB OR SECONDARY IDB ADDRESSES */N/*(DEFAULT OF 8) */ } IDB; #if !d!efined(__VAXC)3#define idb$l_flags idb$r_flags_overlay.idb$l_flagsN#define idb$v_cram_alloc idb$r_flags_overlay.idb$r_flags_bits.idb$v_cram_alloc@#define idb$v_vle idb$r_flags_overlay.idb$r_flags_bits.idb$v_vleJ#define idb$v_noresize idb$r_flags_overlay.idb$r_flags_bits.idb$v_noresize@#define idb$v_mcj idb$r_flags_overlay.idb$r_flags_bits.idb$v_mcjN#define idb$v_shared_int idb$r_flags_overlay.idb$r_flags_bits.idb$v_shared_intX#define idb$v_distributed_int idb$r_flags_overlay.idb$r_flags_bits.i !db$v_distributed_intR#define idb$v_isr_callable idb$r_flags_overlay.idb$r_flags_bits.idb$v_isr_callable"#endif /* #if !defined(__VAXC) */ N#define IDB$K_LENGTH 88 /*LENGTH OF STANDARD IDB */N#define IDB$C_LENGTH 88 /*LENGTH OF STANDARD IDB */N#define IDB$S_IDBDEF 88 /*OLD IDB SIZE FOR COMPATIBILITY */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporte!d */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IDBDEF_LOADED */ ww@=[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard En!terprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and! is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************* !*******************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 22-SEP-2020 13:00:08 $1$DGA8345:[LIB_H.SRC]IDTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IDTDEF ***/#ifndef __IDTDEF_LOADED#define __IDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save!#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __st!ruct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Interrupt and Exception Handler Dispatch Table Definitions. This table */N/* specifies the entry points for exception and interrupt handlers. */N/* ! */ N#define IDT$C_DE 0 /* %X00 Divide Error */N#define IDT$C_DB 1 /* %X01 Debug */N#define IDT$C_NMI 2 /* %X02 Non Maskable Interrupt */N#define IDT$C_BP 3 /* %X03 Breakpoint */N#define IDT$C_OF 4 /* %X04 Overflow */N#define IDT$C_BR 5 /* %X05 !Bound Range Exceeded */N#define IDT$C_UD 6 /* %X06 Undefined Opcode */N#define IDT$C_NM 7 /* %X07 Device Not Available */N#define IDT$C_DF 8 /* %X08 Double Fault */N#define IDT$C_UNUSED_9 9 /* %X09 Unused vector */N#define IDT$C_TS 10 /* %X0A Invalid TSS */N#define IDT$C_NP 11 /* %X0B Segment Not Present ! */N#define IDT$C_SS 12 /* %X0C Stack Segment Fault */N#define IDT$C_GP 13 /* %X0D General Protection Fault */N#define IDT$C_PF 14 /* %X0E Page Fault */N#define IDT$C_UNUSED_F 15 /* %X0F Unused vector */N#define IDT$C_MF 16 /* %X10 Math Fault */N#define IDT$C_AC 17 /* %X11 Alignment Check */N#define IDT$C_MCE 18! /* %X12 Machine Check Exception */P#define IDT$C_XM 19 /* %X13 SIMD Floating-Point Exception */N#define IDT$C_VE 20 /* %X14 Virtualization Exception */O#define IDT$C_CP 21 /* %X15 Control Protection Exception */N#define IDT$C_UNUSED_16 22 /* %X16 Unused vector */N#define IDT$C_UNUSED_17 23 /* %X17 Unused vector */N#define IDT$C_UNUSED_18 24 /*! %X18 Unused vector */N#define IDT$C_UNUSED_19 25 /* %X19 Unused vector */N#define IDT$C_UNUSED_1A 26 /* %X1A Unused vector */N#define IDT$C_UNUSED_1B 27 /* %X1B Unused vector */N#define IDT$C_UNUSED_1C 28 /* %X1C Unused vector */N#define IDT$C_VC 29 /* %X1D VMM Comm Exception */N#define IDT$C_SX 30 /* %X1E Security Exception ! */N#define IDT$C_UNUSED_1F 31 /* %X1F Unused vector */N#define IDT$C_KERNEL_AST 36 /* %X24 Kernel mode AST */N#define IDT$C_EXEC_AST 37 /* %X25 Exec mode AST */N#define IDT$C_SUPER_AST 38 /* %X26 Super mode AST */N#define IDT$C_USER_AST 39 /* %X27 User mode AST */N#define IDT$C_REPORT_ALIGN_FAULT 40 /* %X28 Report alignment fault */N#define IDT$C_!UNUSED_290 41 /* %X29 Unused vector */N#define IDT$C_UNUSED_2A0 42 /* %X2A Unused vector */N#define IDT$C_UNUSED_2B0 43 /* %X2B Unused vector */N#define IDT$C_UNUSED_2C0 44 /* %X2C Unused vector */N#define IDT$C_UNUSED_2D0 45 /* %X2D Unused vector */N#define IDT$C_UNUSED_2E0 46 /* %X2E Unused vector */N#define IDT$C_UNUSED_2F0 47 !/* %X2F Unused vector */N#define IDT$C_LOAD_F_FLOAT 48 /* %X30 Load F floating */N#define IDT$C_LOAD_D_FLOAT 49 /* %X31 Load D floating */N#define IDT$C_LOAD_S_FLOAT 50 /* %X32 Load S floating */N#define IDT$C_LOAD_T_FLOAT 51 /* %X33 Load T floating */N#define IDT$C_STORE_F_FLOAT 52 /* %X34 Store F floating */N#define IDT$C_STORE_D_FLOAT 53 /* %X35 Store D floating ! */N#define IDT$C_STORE_S_FLOAT 54 /* %X36 Store S floating */N#define IDT$C_STORE_T_FLOAT 55 /* %X37 Store T floating */N#define IDT$C_LOAD_SEXT_LONG 56 /* %X38 Load sign-extended longword */N#define IDT$C_LOAD_QUAD 57 /* %X39 Load quadword */U#define IDT$C_LOAD_SEXT_LONG_L 58 /* %X3A Load sign-extended longword locked */N#define IDT$C_LOAD_QUAD_L 59 /* %X3B Load quadword locked */N#def!ine IDT$C_STORE_LONG 60 /* %X3C Store longword */N#define IDT$C_STORE_QUAD 61 /* %X3D Store quadword */N#define IDT$C_STORE_LONG_C 62 /* %X3E Store longword conditional */N#define IDT$C_STORE_QUAD_C 63 /* %X3F Store quadword conditional */N#define IDT$C_BREAK_DBG 64 /* %X40 Debug break point trap */N#define IDT$C_BREAK_BUGCHK 65 /* %X41 Bugcheck break point trap */N#define IDT$C_ILLEGAL_INSTRUCT!ION 66 /* %X42 Illegal instruction trap */N#define IDT$C_ILLEGAL_PAL_OPERAND 67 /* %X43 Illegal call PAL operand */N#define IDT$C_GENTRAP 68 /* %X44 Software generated trap */N#define IDT$C_UNUSED_45 69 /* %X45 Unused vector */N#define IDT$C_UNUSED_46 70 /* %X46 Unused vector */N#define IDT$C_UNUSED_47 71 /* %X47 Unused vector */N#define IDT$C_CHANGE_MODE_KERNEL 72 /* %X48 Change m!ode to kernel */N#define IDT$C_CHANGE_MODE_EXEC 73 /* %X49 Change mode to exec */N#define IDT$C_CHANGE_MODE_SUPER 74 /* %X4A Change mode to super */N#define IDT$C_CHANGE_MODE_USER 75 /* %X4B Change mode to user */N#define IDT$C_HP_1 76 /* %X4C Reserved for hp */N#define IDT$C_HP_2 77 /* %X4D Reserved for hp */N#define IDT$C_HP_3 78 /* %X4E Reserved for hp */N#d!efine IDT$C_HP_4 79 /* %X4F Reserved for hp */N#define IDT$C_UNUSED_50 80 /* %X50 Unused */N#define IDT$C_SOFT_INTERRUPT_1 81 /* %X51 Software level 1 interrupt */N#define IDT$C_SOFT_INTERRUPT_2 82 /* %x52 Software level 2 interrupt */N#define IDT$C_SOFT_INTERRUPT_3 83 /* %X53 Software level 3 interrupt */N#define IDT$C_SOFT_INTERRUPT_4 84 /* %X54 Software level 4 interrupt */N#define IDT$C_SOFT_INTERRUPT!_5 85 /* %X55 Software level 5 interrupt */N#define IDT$C_SOFT_INTERRUPT_6 86 /* %X56 Software level 6 interrupt */N#define IDT$C_SOFT_INTERRUPT_7 87 /* %X57 Software level 7 interrupt */N#define IDT$C_SOFT_INTERRUPT_8 88 /* %X58 Software level 8 interrupt */N#define IDT$C_SOFT_INTERRUPT_9 89 /* %X59 Software level 9 interrupt */N#define IDT$C_SOFT_INTERRUPT_10 90 /* %X5A Software level 10 interrupt */N#define IDT$C_SOFT_INTERRUPT_11 91 /* %X5B Softwa!re level 11 interrupt */N#define IDT$C_SOFT_INTERRUPT_12 92 /* %X5C Software level 12 interrupt */N#define IDT$C_SOFT_INTERRUPT_13 93 /* %X5D Software level 13 interrupt */N#define IDT$C_SOFT_INTERRUPT_14 94 /* %X5E Software level 14 interrupt */N#define IDT$C_SOFT_INTERRUPT_15 95 /* %X5F Software level 15 interrupt */N#define IDT$C_SOFT_INTERRUPT_BASE 80 /* Reschedule interrupt */N#define IDT$C_RESCHEDULE 83 /* Reschedule interrupt */N!#define IDT$C_IO_POST 84 /* I/O post interrupt */N#define IDT$C_SW_TIMER_INTERRUPT 87 /* Software timer interrupt */N#define IDT$C_IP_CONTROL 92 /* IP control */N#define IDT$C_XDELTA 94 /* Xdelta */N#define IDT$C_INTERVAL_CLOCK 96 /* %X60 Interval clock interrupt */N#define IDT$C_INTERPROCESSOR 97 /* %X61 Interprocessor interrupt */S#define IDT$C_SYSTEM_CORRE!CTED_ERROR 98 /* %X62 System corrected error interrupt */W#define IDT$C_PROCESS_CORRECTED_ERROR 99 /* %X63 Processor corrected error interrupt */N#define IDT$C_POWER_FAIL 100 /* %X64 Power fail interrupt */S#define IDT$C_PERF_MONITOR 101 /* %X65 Reserved for performance monitor */N#define IDT$C_SYSTEM_MACHINE_CHECK 102 /* %X66 System machine check abort */R#define IDT$C_PROCESSOR_MACHINE_CHECK 103 /* %X67 Processor machine check abort */P#define IDT$C_SYSTEM_ENV_E!VENT 104 /* %X68 Environmental event interrupt */P#define IDT$C_PROCESSOR_SPECIFIC_1 105 /* %X69 Reserved - processor specific */Y#define IDT$C_SYSTEM_REC_ERROR 106 /* %X6A System recoverable machine check abort */\#define IDT$C_PROC_REC_ERROR 107 /* %X6B Processer recoverable machine check abort */N#define IDT$C_EXTERNAL_INTERRUPT 128 /* %X80 External interrupt */S#define IDT$C_BREAK_SYS 129 /* %X81 System break (BREAK_DBG is %X40) */N#define IDT$C_BR"EAK_APP 130 /* %X82 Application break */N#define IDT$C_BREAK_ARCH 131 /* %X83 Architected break (Intel) */N#define IDT$C_DEBUG_FAULT 132 /* %X84 Debug fault */T#define IDT$C_UNEXPECTED 133 /* %X85 Unexpected exception or interrupt */N#define IDT$C_NAT_CONSUMPTION 134 /* %x86 NaT comsumption fault */N#define IDT$C_TAKEN_BRANCH 135 /* %x87 Taken branch trap */N#define IDT$C_SINGLE_STEP 136 " /* %x88 Single step trap */R#define IDT$C_IA32_TRAP 137 /* %X89 IA-32 exception, interrupt, etc */N#define IDT$C_BREAK_HALT 138 /* %x8a PAL_HALT equivalent */r#define IDT$C_BREAK_UNKNOWN 139 /* %x8b Needs further processing to figure out what kind of break it is */I/* Probably a bad idea to override this! */S#define IDT$C_PROBE 140 /* %x8c Probe VA was not in TLB, emulate */v#define IDT$C_KSTK_I"NVALID 141 /* %x8d An invalid kernel stack was detected. We've switched to slot HWPCB */N/* and the intstk may not be totally valid */#define IDT$C_LOWER_PRIV 142 /* %x8e We took a lower privilege trap. This may be an ACCVIO from an unimplemented */Q/* virtual address (and the handler needs to check) or a lower priv trap. */N#define IDT$C_SPARE_1 143 /* Leave spares */#define IDT$C_SPARE_2 144b#def "ine IDT$C_COUNT 145 /* Number of entry slots. Add new entries before this. */  #include #ifdef __INITIAL_POINTER_SIZEj#pragma __required_pointer_size __save /* Save current pointer size */j#pragma __required_pointer_size __long /* Pointers are 64-bit */qtypedef void (*INTERRUPTION_HANDLER_PQ)(INTSTK *,int vector); /* Definition of handler routines called by SWIS */ltypedef void ("*SOFTINT_HANDLER_PQ)(int ipl); /* Definition of software interrupt routines called by SWIS */btypedef int (*AST_HANDLER_PQ)(INTSTK *, int mode); /* Definition of AST routines called by SWIS */j#pragma __required_pointer_size __restore /* Return to previous pointer size */#endif $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previousl"y-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IDTDEF_LOADED */ wwP#>[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, d"uplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to "anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:2 "2:25 by OpenVMS SDL V3.7 */F/* Source: 22-APR-1993 11:20:18 $1$DGA8345:[LIB_H.SRC]IFDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IFDDEF ***/#ifndef __IFDDEF_LOADED#define __IFDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Define "d whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __st "ruct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* IMAGE FILE DESCRIPTOR BLOCK - RETURNED BY IMAGE ACTIVATOR */N/*- */#define IFD$M_EXEONLY 0x1#define IFD$M_PRIV 0x2#define IFD$M_SETVECTOR 0x4N#define IFD$K_LENG "TH 28 /*LENGTH OF FIXED AREA OF IFD */N#define IFD$C_LENGTH 28 /*LENGTH OF FIXED AREA OF IFD */#define IFD$S_IFDDEF 28  9#ifdef __cplusplus /* Define structure prototypes */ struct _kfe; #endif /* #ifdef __cplusplus */ typedef struct _ifd {T unsigned short int ifd$w_size; /*SIZE IN BYTES OF IMAGE FILE DESCRIPTOR */N unsigned short int ifd$w_filnamoff; /*OFFSET TO ASCIC */N/*FULLY QUALIFIED FILE SPEC  " */N short int ifddef$$_fill_1; /*RESERVED OFFSET 1 */N short int ifddef$$_fill_2; /*RESERVED OFFSET 2 */Q unsigned short int ifd$w_chan; /*CHANNEL ON WHICH IMAGE FILE IS OPEN */N unsigned short int ifd$w_cmchan; /*COMPATIBILITY MODE CHANNEL */N struct _kfe *ifd$l_cmkfiadr; /*COMPATIBILITY MODE IMAGE */N/*KNOWN FILE ENTRY ADDRESS OR 0 " */ __union {N unsigned short int ifd$w_flags; /*IMAGE FILE DESCRIPTOR FLAGS */ __struct {N unsigned ifd$v_exeonly : 1; /*EXECUTE ONLY FILE */U unsigned ifd$v_priv : 1; /*IMAGE INSTALLED WITH ENHANCED PRIVILEGE */R unsigned ifd$v_setvector : 1; /*PRIVILEGED VECTORS TO BE INSTALLED */' unsigned ifd$v_fill_0_ : 5; } ifd$r_flags_bits; } ifd$r_flags_overlay; "N short int ifddef$$_fill_3; /*SPARE WORD */N unsigned __int64 ifd$q_curprog; /*STRING DESCRIPTOR FOR */N/*FULLY QUALIFIED FILE SPEC OF */N/*RUNNING PROGRAM */ } IFD; #if !defined(__VAXC)3#define ifd$w_flags ifd$r_flags_overlay.ifd$w_flagsH#define ifd$v_exeonly ifd$r_flags_overlay.ifd$r_flags_bits.ifd$v_exeonlyB#define ifd$v_priv" ifd$r_flags_overlay.ifd$r_flags_bits.ifd$v_privL#define ifd$v_setvector ifd$r_flags_overlay.ifd$r_flags_bits.ifd$v_setvector"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IFDDEF_LOADED */ ww"pq>[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 C"opyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc". **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */F/* Source: 06-FEB-2002 10:17:08 $1$DGA8345:[LIB_H.SRC]IFSDEF.SDL;1 *//*********************************** "*********************************************************************************************//*** MODULE $IFSDEF ***/#ifndef __IFSDEF_LOADED#define __IFSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma "__required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union "#endif#endif N/* */N/* Definitions for Interruption Function State (IFS - CR23) */N/* */#define IFS$M_IFM 0x3FFFFFFFFF%#define IFS$M_MBZ0 0x7FFFFFC000000000"#define IFS$M_V 0x8000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment _"_quadword#else#pragma __nomember_alignment#endiftypedef struct _ifs {#pragma __nomember_alignment __union {( unsigned __int64 ifs$q_register; __struct {#if defined(__VAXC)& unsigned ifs$v_ifm_1 : 32;% unsigned ifs$v_ifm_2 : 6;#elseN unsigned __int64 ifs$v_ifm : 38; /* Interruption Frame Marker */#endifN unsigned ifs$v_mbz0 : 25; /* Reserved IFS{62:38} (MBZ) */N unsigned ifs$v_v : 1; " /* Valid bit */ } ifs$r_ifsdef_bits; } ifs$r_ifs_union; } IFS; #if !defined(__VAXC)5#define ifs$q_register ifs$r_ifs_union.ifs$q_register=#define ifs$v_ifm ifs$r_ifs_union.ifs$r_ifsdef_bits.ifs$v_ifm?#define ifs$v_mbz0 ifs$r_ifs_union.ifs$r_ifsdef_bits.ifs$v_mbz09#define ifs$v_v ifs$r_ifs_union.ifs$r_ifsdef_bits.ifs$v_v"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save "/* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Dtypedef struct _ifs * IFS_PQ; /* Pointer to a IFS structure. */Qtypedef struct _ifs ** IFS_PPQ; /* Pointer to a pointer to a IFS structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 IFS_PQ;!typedef unsigned __int64 IFS_PPQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#i"fdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IFSDEF_LOADED */ ww>[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is" confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidenti"al **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********* "***********************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */F/* Source: 19-APR-1993 14:30:43 $1$DGA8345:[LIB_H.SRC]IHADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IHADEF ***/#ifndef __IHADEF_LOADED#define __IHADEF_LOADED 1 G#pragma __nostandard /* This "file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#defin"e __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* IMAGE HEADER ACTIVATION SECTION OFFSETS */N/*- " */N#define IHA$K_LENGTH 20 /*SIZE OF ACTIVATION SECTION */N#define IHA$C_LENGTH 20 /*SIZE OF ACTIVATION SECTION */#define IHA$S_IHADEF 20 typedef struct _iha {N unsigned int iha$l_tfradr1; /*FIRST TRANSFER ADDRESS */N unsigned int iha$l_tfradr2; /*SECOND TRANSFER ADDRESS */N unsigned int iha$l_tfradr3; /*THIRD TRANSFER ADDRESS */N " int ihadef$$_fill_1; /*GUARANTEED TRAILING 0 ADDRESS */N unsigned int iha$l_inishr; /*SHARED IMAGE INITIALIZATION */N/*(valid if IHD$V_INISHR set) */ } IHA; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus !" }#endif#pragma __standard #endif /* __IHADEF_LOADED */ ww>[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior ""written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of #"VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */F/* Source: 07-MAR-1996 10 $":23:40 $1$DGA8345:[LIB_H.SRC]IHDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IHDDEF ***/#ifndef __IHDDEF_LOADED#define __IHDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_p%"ointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#i &"f !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* IMAGE HEADER RECORD DEFINITIONS - FIRST RECORD OF IMAGE HEADER */N/*- */N#define IHD$K_MAJORID 12848 /* Major id value */N#define IHD$K_MINORID 13616 /* Minor id value */N#d '"efine IHD$K_EXE 1 /* Executable image */N#define IHD$K_LIM 2 /* Linkable image */#define IHD$M_LNKDEBUG 0x1#define IHD$M_LNKNOTFR 0x2#define IHD$M_NOP0BUFS 0x4#define IHD$M_PICIMG 0x8#define IHD$M_P0IMAGE 0x10#define IHD$M_DBGDMT 0x20#define IHD$M_INISHR 0x40#define IHD$M_IHSLONG 0x80#define IHD$M_UPCALLS 0x100 #define IHD$M_MATCHCTL 0x7000000N#define IHD$K_LENGTH 48 /* Length of fixed are("a */N#define IHD$C_LENGTH 48 /* Length of fixed area */N#define IHD$C_MINCODE -1 /* Low bound of ALIAS values */N#define IHD$C_NATIVE -1 /* Native mode image */N#define IHD$C_RSX 0 /* RSX image produced by TKB */N#define IHD$C_BPA 1 /* BASIC plus analog */`#define IHD$C_ALIAS 2 /* Last 126 bytes contains ASCIC of image to act)"ivate */N#define IHD$C_CLI 3 /* Image is a CLI, run LOGINOUT */N#define IHD$C_PMAX 4 /* PMAX system image */N#define IHD$C_ALPHA 5 /* ALPHA image */N#define IHD$C_MAXCODE 5 /* High bound of ALIAS values */N/* */N#define IHD$C_GEN_XLNKR 1 /* Cross linker */N#define IHD$C_GE*"N_NATIVE 2 /* First native mode image header. */N/* does not have LNKFLAGS, SYSVER and IAFVA fields */Q#define IHD$C_GEN_LNKFLG 3 /* Native with LNKFLAGS longword added */N/* does not have SYSVER and IAFVA fields */S#define IHD$C_GEN_SYSVER 4 /* Native with LNKFLAGS and SYSVER added */N/* does not have IAFVA field */N#define IHD$C_GEN_FIXUP 5 +" /* Version III image */N/* contains LNKFLAGS, SYSVER, and IAFVA fields */N#define IHD$C_GEN_NEWISD 6 /* ISD size field is a byte */N#define IHD$S_IHDDEF 512 /* Old size name - synonym */ typedef struct _ihd {S unsigned short int ihd$w_size; /* Size in bytes of Image Header record */N unsigned short int ihd$w_activoff; /* Byte offset to activation data */Y unsigned short int i,"hd$w_symdbgoff; /* Byte offset to symbol table and debug data */N unsigned short int ihd$w_imgidoff; /* Byte offset to image ident data */N unsigned short int ihd$w_patchoff; /* Byte offset to patch data */Y unsigned short int ihd$w_version_array_off; /* Byte offset to version number array */N unsigned short int ihd$w_majorid; /* Major id */N unsigned short int ihd$w_minorid; /* Minor id */N unsigned char ihd$b_hd-"rblkcnt; /* Count of header blocks */N unsigned char ihd$b_imgtype; /* Image type */N/* */N/* IMAGE TYPE CODES */N/* */N short int ihddef$$_fill_2; /* Reserved */N unsigned __int64 ihd$q_privreqs; /* Requested ." privilege mask */N unsigned short int ihd$w_iochancnt; /*! of channels requested */N/*0 if default */W unsigned short int ihd$w_imgiocnt; /*! of pages of image i/o section requested */N/*0 if default */ __union {N unsigned int ihd$l_lnkflags; /* Linker produced image flags */ __struct {N unsigned ihd$v_lnk/"debug : 1; /* Full debugging requested */N unsigned ihd$v_lnknotfr : 1; /* First transfer address missing */T unsigned ihd$v_nop0bufs : 1; /* RMS use of P0 for image i/o disabled */N unsigned ihd$v_picimg : 1; /* Image is position independent */N unsigned ihd$v_p0image : 1; /* Image is in P0 space only */N unsigned ihd$v_dbgdmt : 1; /* Image header has dmt fields */X unsigned ihd$v_inishr : 1; /* Transfe 0"r array contains valid IHA$L_INISHR */X unsigned ihd$v_ihslong : 1; /* Longword DSTBLKS and GSTRECS valid in IHS$ */N unsigned ihd$v_upcalls : 1; /* Upcalls enabled */S unsigned ihddef$$_fill_3 : 15; /*FILL OUT TO HIGH BYTE OF LONG WORD */O unsigned ihd$v_matchctl : 3; /* Match control for linkable image */' unsigned ihd$v_fill_0_ : 5;" } ihd$r_lnkflags_bits;! } ihd$r_lnkflags_overlay;U unsigned i1"nt ihd$l_ident; /* GBL SEC ident value for linkable image */Y unsigned int ihd$l_sysver; /* SYS$K_VERSION or 0 if not linked with exec */U void *ihd$l_iafva; /* Relative virtual address of fixup info */Y char ihd$t_skip [462]; /* ALIAS should be last word in 512 byte block */N unsigned short int ihd$w_alias; /* Code to use secondary image name */N/****************************************** */N2"/* */N/* Define legal range of ALIAS constants. MINCODE must be equal to the */I/* lowest value and MAXCODE must be equal to the highest value. */N/* */N/******************************************* */N/* */I/* Generation number returned 3"by IMGSHR IMG$GET_IHD to SYSIMGACT. */I/* These do not appear in the image header but are inferred from the */I/* contents of the image header */N/* */ } IHD; #if !defined(__VAXC)<#define ihd$l_lnkflags ihd$r_lnkflags_overlay.ihd$l_lnkflagsF#define ihd$r_lnkflags_bits ihd$r_lnkflags_overlay.ihd$r_lnkflags_bits9#define ihd$v_lnkdebug ihd$r_lnkflags_bits.ihd$v_lnkdebu 4"g9#define ihd$v_lnknotfr ihd$r_lnkflags_bits.ihd$v_lnknotfr9#define ihd$v_nop0bufs ihd$r_lnkflags_bits.ihd$v_nop0bufs5#define ihd$v_picimg ihd$r_lnkflags_bits.ihd$v_picimg7#define ihd$v_p0image ihd$r_lnkflags_bits.ihd$v_p0image5#define ihd$v_dbgdmt ihd$r_lnkflags_bits.ihd$v_dbgdmt5#define ihd$v_inishr ihd$r_lnkflags_bits.ihd$v_inishr7#define ihd$v_ihslong ihd$r_lnkflags_bits.ihd$v_ihslong7#define ihd$v_upcalls ihd$r_lnkflags_bits.ihd$v_upcalls9#define ihd$v_matchctl ihd$r_lnkflags_bi5"ts.ihd$v_matchctl"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IHDDEF_LOADED */ ww?[UM/***************************************************************************/M/** 6" **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** 7" **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 8" **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */F/* Source: 19-APR-1993 14:33:04 $1$DGA8345:[LIB_H.SRC]IHIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE 9"$IHIDEF ***/#ifndef __IHIDEF_LOADED#define __IHIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __c:"plusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* IMA ;"GE HEADER IDENTIFICATION SECTION OFFSETS */N/*- */R#define IHI$K_LENGTH 80 /*LENGTH OF IMAGE HEADER IDENT SECTION */R#define IHI$C_LENGTH 80 /*LENGTH OF IMAGE HEADER IDENT SECTION */#define IHI$S_IHIDEF 80 typedef struct _ihi {N char ihi$t_imgnam [40]; /*IMAGE NAME STRING */N char ihi$t_imgid [16]; /*IMAGE ID <"ENT STRING */Q unsigned __int64 ihi$q_linktime; /*DATE AND TIME THIS IMAGE WAS LINKED */N/*STANDARD SYSTEM QUADWORD FORMAT */N char ihi$t_linkid [16]; /*LINKER IDENT STRING */ } IHI; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr siz="e */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IHIDEF_LOADED */ ww?[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to >"anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M?"/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 @" */F/* Source: 21-APR-1993 10:45:34 $1$DGA8345:[LIB_H.SRC]IHPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IHPDEF ***/#ifndef __IHPDEF_LOADED#define __IHPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmaA"s supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endB"if#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* IMAGE HEADER PATCH SECTION OFFSETS */N/*- */N#define IHP$K_LENGTH 44 /*LENGTH OF PATCH HEADER SECTION */N#define IHP$C_LENGTH 44 /*LENG C"TH OF PATCH HEADER SECTION */#define IHP$S_IHPDEF 44 typedef struct _ihp {N unsigned int ihp$l_eco1; /*DEC ECO LEVELS 1-32 */N unsigned int ihp$l_eco2; /*DEC ECO LEVELS 33-64 */N unsigned int ihp$l_eco3; /*DEC ECO LEVELS 65-98 */N unsigned int ihp$l_eco4; /*USER ECO LEVELS 99-132 */N unsigned int ihp$l_rw_patsiz; /*SIZE OF FREE RW PATCH AREA */Q void *ihp$l_rw D"_patadr; /*VIR ADDR OF NEXT FREE RW PATCH AREA */N unsigned int ihp$l_ro_patsiz; /*SIZE OF FREE RO PATCH AREA */Q void *ihp$l_ro_patadr; /*VIR ADDR OF NEXT FREE RO PATCH AREA */U unsigned int ihp$l_patcomtxt; /*PATCH COMMAND TEXT VIRTUAL BLOCK NUMBER */N unsigned __int64 ihp$q_patdate; /*DATE OF MOST RECENT PATCH */ } IHP; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever pE"tr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IHPDEF_LOADED */ ww0F@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensF"ed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed byG" VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************* H"*******************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */F/* Source: 20-APR-1993 13:52:58 $1$DGA8345:[LIB_H.SRC]IHSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IHSDEF ***/#ifndef __IHSDEF_LOADED#define __IHSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __I"member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...J"#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* IMAGE HEADER SYMBOL TABLE AND DEBUG SECTION OFFSETS */N/*- */N#d K"efine IHS$K_LENGTH 28 /*LENGTH OF SYMBOL TABLE SECTION */N#define IHS$C_LENGTH 28 /*LENGTH OF SYMBOL TABLE SECTION */#define IHS$S_IHSDEF 28 typedef struct _ihs {U unsigned int ihs$l_dstvbn; /*DEBUG SYMBOL TABLE VIRTUAL BLOCK NUMBER */V unsigned int ihs$l_gstvbn; /*GLOBAL SYMBOL TABLE VIRTUAL BLOCK NUMBER */N unsigned short int ihs$w_dstblks; /*DEBUG SYMBOL TABLE BLOCK COUNT */N unsigned short int ihs$w_gstrecs; L" /*GLOBAL SYMBOL TABLE RECORD COUNT */N unsigned int ihs$l_dmtvbn; /*VBN OF DMT INFORMATION */N unsigned int ihs$l_dmtbytes; /*LENGTH OF DMT INFO */W int ihs$l_dstblks; /*Debug symbol table block count -- LONGWORD */Y int ihs$l_gstrecs; /*Global symbol table record count -- LONGWORD */ } IHS; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmaM"s supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IHSDEF_LOADED */ ww@m@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-N"Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software,O" Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************** P"*****************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */G/* Source: 16-DEC-1993 14:32:51 $1$DGA8345:[LIB_H.SRC]IHVNDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IHVNDEF ***/#ifndef __IHVNDEF_LOADED#define __IHVNDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_aliQ"gnment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif R"#ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif )#define IHVN$M_SUBVERSION_MINOR_ID 0xFFFF-#define IHVN$M_SUBVERSION_MAJOR_ID 0xFFFF0000 #typedef struct _img_version_array {Q unsigned int ihvn$l_subsystem_mask; /* Bit mask of nonzero version numbers */ __union {N unsigned i S"nt ihvn$l_subversion_array; /* First array element */ __struct {W unsigned ihvn$v_subversion_minor_id : 16; /* Minor ID for each component */W unsigned ihvn$v_subversion_major_id : 16; /* Major ID for each component */ } ihvn$r_fill_1_; } ihvn$r_fill_0_; } IMG_VERSION_ARRAY; #if !defined(__VAXC)F#define ihvn$l_subversion_array ihvn$r_fill_0_.ihvn$l_subversion_array[#define ihvn$v_subversion_minor_id ihvn$r_fill_0_.ihvn$r_f T"ill_1_.ihvn$v_subversion_minor_id[#define ihvn$v_subversion_major_id ihvn$r_fill_0_.ihvn$r_fill_1_.ihvn$v_subversion_major_id"#endif /* #if !defined(__VAXC) */ (#define IHVN$M_VERSION_MINOR_ID 0xFFFFFF*#define IHVN$M_VERSION_MAJOR_ID 0xFF000000 %typedef struct _img_overall_version { __union { int ihvn$l_version_bits; __struct {N unsigned ihvn$v_version_minor_id : 24; /* Minor ID of SYS.STB */N unsigned ihvn$v_version_major_id : 8; /* MU"ajor ID of SYS.STB */ } ihvn$r_fill_3_; } ihvn$r_fill_2_; } IMG_OVERALL_VERSION; #if !defined(__VAXC)U#define ihvn$v_version_minor_id ihvn$r_fill_2_.ihvn$r_fill_3_.ihvn$v_version_minor_idU#define ihvn$v_version_major_id ihvn$r_fill_2_.ihvn$r_fill_3_.ihvn$v_version_major_id"#endif /* #if !defined(__VAXC) */ #define IHVN$K_LENGTH 132#define IHVN$C_LENGTH 132 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined wheneverV" ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IHVNDEF_LOADED */ ww`@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** liW"censed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licenseX"d by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************* Y"***********************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */F/* Source: 22-APR-1993 11:23:14 $1$DGA8345:[LIB_H.SRC]IHXDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IHXDEF ***/#ifndef __IHXDEF_LOADED#define __IHXDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragmZ"a __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ..[".#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* IMAGE HEADER RECORD DEFINITIONS - CROSS LINKER - MAJORID = "01" */N/* 1ST RECORD OF IMAGE HEADER BLOCK */\"N/*- */T#define IHX$K_MAJORID 12592 /*^A/01/ MAJOR ID VALUE FOR CROSS LINKER */T#define IHX$K_MINORID 12592 /*^A/01/ MINOR ID VALUE FOR CROSS LINKER */Y#define IHX$K_MINORID1 12592 /*^A/01/ MINOR ID VALUE FOR CROSS LINKER WITH */N/*SYMBOL TABLE AND 3RD TRANSFER ADR */N#define IHX$K_LENGTH 56 /*LENGTH OF CROSS LINKER HEADER */N ]"#define IHX$C_LENGTH 56 /*LENGTH OF CROSS LINKER HEADER */#define IHX$S_IHXDEF 56 typedef struct _ihx {Q unsigned short int ihx$w_size; /*SIZE IN BYTE OF IMAGE HEADER RECORD */N unsigned char ihx$b_hdrblkcnt; /*COUNT OF BLOCKS IN IMAGE HEADER */N char ihxdef$$_fill_1; /*SPARE */N unsigned __int64 ihx$q_startadr; /*START ADDRESS */N unsigned short int ihx$w_majorid; /*MAJOR ^"ID OF IMAGE HEADER */N unsigned short int ihx$w_minorid; /*MINOR ID OF IMAGE HEADER */N char ihx$t_imgnam [24]; /*IMAGE NAME */N/* */N/* THE FOLLOWING FIELDS ARE PRESENT FOR MINOR ID'S GREATER OR EQUAL TO "03" */N/* */N unsigned int ihx$l_dstvbn; /*DEBUG SYMBOL TABLE VBN _" */N unsigned int ihx$l_gstvbn; /*GLOBAL SYMBOL TABLE VBN */N unsigned short int ihx$w_dstblks; /*DEBUG SYMBOL TABLE BLOCKS */N unsigned short int ihx$w_gstrecs; /*GLOBAL SYMBOL TABLE RECORD COUNT */N unsigned int ihx$l_tfradr3; /*THIRD TRANSFER ADDRESS */ } IHX; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore `" /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IHXDEF_LOADED */ ww A[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/*a"* authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, db"uplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* c" Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */G/* Source: 10-JUL-2023 17:37:13 $1$DGA8345:[LIB_H.SRC]IMCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IMCBDEF ***/#ifndef __IMCBDEF_LOADED#define __IMCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INId"TIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __structe" struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define IMCB$K_MAIN_PROGRAM 1 /* Object of RUN command */N#define IMCB$K_MERGED_IMAGE 2 /* Additional image mapped */N#define IMCB$K_GLOBAL_IMAGE_SECTION 3 /* Image described by global ISD */#define IMCB$M_EXPREG 0x1#define IMCB$M_SHAREABLE 0x2!#define IMCBf"$M_OPEN_FOR_WRITE 0x4#define IMCB$M_RES_HEADER 0x8#define IMCB$M_LOAD_IMAGE 0x10#define IMCB$M_INITIALIZE 0x20#define IMCB$M_DONE 0x40#define IMCB$M_SYS_STB 0x80##define IMCB$M_IN_CIRCULARITY 0x100#define IMCB$M_MAPPED 0x200#define IMCB$M_PROTECTED 0x400 #define IMCB$M_PARENT_PROT 0x800(#define IMCB$M_CMOD_VECTOR_MAPPED 0x1000#define IMCB$M_XLATED 0x2000#define IMCB$M_PROTSECT 0x4000!#define IMCB$M_NOTPROTSECT 0x8000$#define IMCB$M_DISCONTIGUOUS 0x10000#define IMCB$M_FORg"KABLE 0x20000'#define IMCB$M_COMPRESS_DATASEC 0x40000##define IMCB$M_VERSION_SAFE 0x80000##define IMCB$M_PRIMARY_FIX 0x100000%#define IMCB$M_DATA_RESIDENT 0x200000"#define IMCB$M_SHARE_LINK 0x400000#define IMCB$M_AUTOACT 0x800000"#define IMCB$M_MKTHREADS 0x1000000 #define IMCB$M_UPCALLS 0x2000000%#define IMCB$M_SYSTEM_IMAGE 0x4000000#define IMCB$M_PERM 0x8000000"#define IMCB$M_RELOCATE 0x10000000-#define IMCB$M_PROCESS_COPY_LDRIMG 0x20000000 #define IMCB$M_MATCH_CONTROL 0x7 #dh"efine IMCB$M_MINOR_ID 0xFFFFFF"#define IMCB$M_MAJOR_ID 0xFF000000N#define IMCB$C_LENGTH 312 /* Length of IMCB */N#define IMCB$K_LENGTH 312 /* Length of IMCB */N#define IMCB$S_IMCB$DEF 312 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _eihd; struct _kfe; struct _eiaf; struct _plv;struct _kferes;struct _ldrimg; #endif /* #ifdef __cplusplus */ i" c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _imcb {#pragma __nomember_alignmentN struct _imcb *imcb$l_flink; /* Forward link in list */N struct _imcb *imcb$l_blink; /* Backward link in list */N unsigned short int imcb$w_size; /* Size of IMCB in bytes */Q unsigned char j"imcb$b_type; /* Structure type for IMCB (DYN$C_PGD) */U unsigned char imcb$b_subtype; /* Structure subtype for IMCB (DYN$C_IMCB) */N unsigned char imcb$b_access_mode; /* Access mode of image */N unsigned char imcb$b_act_code; /* Activation code */S unsigned short int imcb$w_chan; /* Channel on which image file is opened */ __union {N unsigned int imcb$l_flags; /* Name attributes */ __k"struct {R unsigned imcb$v_expreg : 1; /* Image mapped at end of address space */N unsigned imcb$v_shareable : 1; /* Image installed /SHAREABLE */T unsigned imcb$v_open_for_write : 1; /* Image will be opened for write */N unsigned imcb$v_res_header : 1; /* Image header already decoded */S unsigned imcb$v_load_image : 1; /* Load image from sequential device */T unsigned imcb$v_initialize : 1; /* Image contains initialization cl"ode */N unsigned imcb$v_done : 1; /* Image is completely activated */N unsigned imcb$v_sys_stb : 1; /* Image is linked against SYS.STB */_ unsigned imcb$v_in_circularity : 1; /* Image is involved in an image circularity */N unsigned imcb$v_mapped : 1; /* Image is mapped in address space */N unsigned imcb$v_protected : 1; /* Image installed protected */S unsigned imcb$v_parent_prot : 1; /* Parent image installed protectedm" */\ unsigned imcb$v_cmod_vector_mapped : 1; /* Change mode vectors already mapped */N unsigned imcb$v_xlated : 1; /* Image is a translated VAX image */V unsigned imcb$v_protsect : 1; /* Image contains some protected sections */a unsigned imcb$v_notprotsect : 1; /* Image does not contain some protected sections */V unsigned imcb$v_discontiguous : 1; /* Some image sections are resident */S unsigned imcb$v_forkable : 1; /* Proten"cted image allows POSIX fork() */h unsigned imcb$v_compress_datasec : 1; /* Data sections will be laid out one after another */N/* Flag is only meaningful if DISCONTIGUOUS bit is set */^ unsigned imcb$v_version_safe : 1; /* Image is exempt from system version checks */_ unsigned imcb$v_primary_fix : 1; /* Image has had primary fixups performed on it */f unsigned imcb$v_data_resident : 1; /* Image has it's read-only data sections po"laced in */N/* the data granularity hint region. */\ unsigned imcb$v_share_link : 1; /* Image was installed with shareable linkage */` unsigned imcb$v_autoact : 1; /* Image is being automatically activated (currently */N/* this is just SYS$SSISHR). Certain errors in */N/* activation can, and should, be ignored. */P unsigned imcb$v_mkthreads : 1; /* Multiple kernep"l threads enabled */N unsigned imcb$v_upcalls : 1; /* Upcalls enabled */a unsigned imcb$v_system_image : 1; /* image is SYS$BASE_IMAGE or SYS$PUBLIC_VECTORS */N unsigned imcb$v_perm : 1; /* image is permanent. */[ unsigned imcb$v_relocate : 1; /* image relocations [to be/have been] applied */j unsigned imcb$v_process_copy_ldrimg : 1; /* (system) image has a process copy of the LDRIMG */( unsigned i q"mcb$v_fill_8_ : 2; } imcb$r_fill_1_; } imcb$r_fill_0_;N/* The image name is stored as a counted ASCII string. */N char imcb$t_image_name [40]; /* Name string (counted ASCII) */N unsigned int imcb$l_symbol_vector_size; /* Entries in symbol vector. */ __union {& unsigned __int64 imcb$q_ident; __struct { __union {2 unsigned int imcb$l_match_control; __struct {6 r" unsigned imcb$v_match_control : 3;0 unsigned imcb$v_fill_9_ : 5;% } imcb$r_fill_5_;! } imcb$r_fill_4_; __union {, unsigned int imcb$l_version; __struct {2 unsigned imcb$v_minor_id : 24;1 unsigned imcb$v_major_id : 8;% } imcb$r_fill_7_;! } imcb$r_fill_6_; } imcb$r_fill_3_; } imcb s"$r_fill_2_; __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */& void *imcb$q_starting_address;#else* unsigned __int64 imcb$q_starting_address;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */! void *imcb$q_e t"nd_address;#else% unsigned __int64 imcb$q_end_address;#endif } imcb$q_address_range;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _eihd *imcb$l_ihd; /* Address of IHD for image */N struct _kfe *imcb$l_kfe; /* Address of KFE for image */N void *imcb$l_context; /* Address of co u"ntext block */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */S void *imcb$q_base_address; /* Base address at which image is mapped */#else& unsigned __int64 imcb$q_base_address;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit p v"ointers */N void (*imcb$q_initialize)(); /* Address of initialization code */#else$ unsigned __int64 imcb$q_initialize;#endifP unsigned int imcb$l_active_sons; /* Count of not yet mapped son images */N/* Valid only during activation */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */O struct _eiaf *imcb w"$pq_fixup_vector_address; /* Address of priv fixup vec */#else/ unsigned __int64 imcb$pq_fixup_vector_address;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *imcb$pq_symbol_vector_address; /* Address of the symbol vector */#else0 unsigned __int64 imcb$pq_symbol_vector_address;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr s x"ize pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _plv *imcb$pq_plv_address; /* Address of PLVDEF for image */#else& unsigned __int64 imcb$pq_plv_address;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *imcb$pq_cmod_kernel_address; /* Address of kernel CMOD routines y"*/#else. unsigned __int64 imcb$pq_cmod_kernel_address;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *imcb$pq_cmod_exec_address; /* Address of exec CMOD routines */#else, unsigned __int64 imcb$pq_cmod_exec_address;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __lo z"ng /* And set ptr size default to 64-bit pointers */U struct _plv *imcb$pq_ssi_plv; /* Address of system service intercept PLV */#else" unsigned __int64 imcb$pq_ssi_plv;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifU struct _kferes *imcb$l_kferes_ptr; /* Pointer to resident section description */X/* The global section name of a shar{"eable image is stored as a counted ASCII string. */N char imcb$t_log_image_name [40]; /* Name string (counted ASCII) */N char imcb$t_dvi [16]; /* device id */N unsigned short int imcb$w_fid [3]; /* file id */N char imcb$b_risig [32]; /* image signiture */N short int imcb$w_fill1; /* fill for long alignment */W struct _kferes *imcb$l_kferes64_ptr; /* Pointer |"to 64-bit resident section descs */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *imcb$pq_starting_address_64; /* Start addr of 64-bit image VA */#else. unsigned __int64 imcb$pq_starting_address_64;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size def }"ault to 64-bit pointers */N void *imcb$pq_end_address_64; /* End addr of 64-bit image VA */#else) unsigned __int64 imcb$pq_end_address_64;#endifN unsigned __int64 imcb$q_linktime; /* link time */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */O struct _ldrimg *imcb$q_ldrimg; /* pointer to loaded image structure */ ~"#else unsigned __int64 imcb$q_ldrimg;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifY struct _imcb *imcb$l_prot_image_flink; /* Forward link in list of protected images */X int imcb$l_lkwset_count; /* Count of times image has been locked in WS */ } IMCB; #if !defined(__VAXC)0#define imcb$l_flags imcb$r_fill_0_.imcb$l_flags"A#define imcb$v_expreg imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_expregG#define imcb$v_shareable imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_shareableQ#define imcb$v_open_for_write imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_open_for_writeI#define imcb$v_res_header imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_res_headerI#define imcb$v_load_image imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_load_imageI#define imcb$v_initialize imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_initialize=#define imcb$v_done imcb$r_fill_0_.imcb$r_fill_1_."imcb$v_doneC#define imcb$v_sys_stb imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_sys_stbQ#define imcb$v_in_circularity imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_in_circularityA#define imcb$v_mapped imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_mappedG#define imcb$v_protected imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_protectedK#define imcb$v_parent_prot imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_parent_protY#define imcb$v_cmod_vector_mapped imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_cmod_vector_mappedA#define imcb$v_xlated imcb"$r_fill_0_.imcb$r_fill_1_.imcb$v_xlatedE#define imcb$v_protsect imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_protsectK#define imcb$v_notprotsect imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_notprotsectO#define imcb$v_discontiguous imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_discontiguousE#define imcb$v_forkable imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_forkableU#define imcb$v_compress_datasec imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_compress_datasecM#define imcb$v_version_safe imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_version"_safeK#define imcb$v_primary_fix imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_primary_fixO#define imcb$v_data_resident imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_data_residentI#define imcb$v_share_link imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_share_linkC#define imcb$v_autoact imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_autoactG#define imcb$v_mkthreads imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_mkthreadsC#define imcb$v_upcalls imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_upcallsM#define imcb$v_system_image imcb$r_fill_0_.imcb$"r_fill_1_.imcb$v_system_image=#define imcb$v_perm imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_permE#define imcb$v_relocate imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_relocate[#define imcb$v_process_copy_ldrimg imcb$r_fill_0_.imcb$r_fill_1_.imcb$v_process_copy_ldrimg0#define imcb$q_ident imcb$r_fill_2_.imcb$q_ident^#define imcb$l_match_control imcb$r_fill_2_.imcb$r_fill_3_.imcb$r_fill_4_.imcb$l_match_controlm#define imcb$v_match_control imcb$r_fill_2_.imcb$r_fill_3_.imcb$r_fill_4_.imcb$r_fill_5_.imcb$v_ma "tch_controlR#define imcb$l_version imcb$r_fill_2_.imcb$r_fill_3_.imcb$r_fill_6_.imcb$l_versionc#define imcb$v_minor_id imcb$r_fill_2_.imcb$r_fill_3_.imcb$r_fill_6_.imcb$r_fill_7_.imcb$v_minor_idc#define imcb$v_major_id imcb$r_fill_2_.imcb$r_fill_3_.imcb$r_fill_6_.imcb$r_fill_7_.imcb$v_major_idL#define imcb$q_starting_address imcb$q_address_range.imcb$q_starting_addressB#define imcb$q_end_address imcb$q_address_range.imcb$q_end_address"#endif /* #if !defined(__VAXC) */ N/* Generic names f "or common fields with different sizes. */N/* x86, c macros */ ,#define imcb$$_ldrimg imcb$q_ldrimg>#define imcb$$_starting_address imcb$q_starting_address9#define imcb$$_end_address imcb$q_end_address8#define imcb$$_initialize imcb$q_initialize:#define imcb$$_plv_address imcb$pq_plv_address.#define imcb$$_ssi_plv imcb$pq_ssi_plvD#define imcb$$_symbol_ve "ctor_address imcb$pq_symbol_vector_addressC#define imcb$$_fixup_vector_address imcb$pq_fixup_vector_address:#define imcb$$_base_address imcb$q_base_addressB#define imcb$$_cmod_kernel_address imcb$pq_cmod_kernel_address@#define imcb$$_cmod_exec_address imcb$pq_cmod_exec_addressN/* x86, bliss macros */  #ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save&#pragma __required_pointer_size __lo "ngtypedef IMCB * IMCB_PQ;'#pragma __required_pointer_size __shorttypedef IMCB * IMCB_PL;)#pragma __required_pointer_size __restore#elsetypedef __int64 IMCB_PQ;typedef __int32 IMCB_PL;,#endif /* __INITIAL_POINTER_SIZE */N/* */J/* Define the layout of the page header for locked-down image activator */I/* pool within P1 pool */N/* " */N#define IMGACT_POOL$K_LENGTH 16 /* Length of IMGACT_POOL */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _imgact_pool {#pragma __nomember_alignmentN struct _imgact_pool *imgact_pool$l_flink; /* Forward link in list */N struct _imgact_pool *imgact_pool "$l_blink; /* Backward link in list */a unsigned short int imgact_pool$w_size; /* Size of IMGACT_POOL in bytes (multiple of pages) */X unsigned char imgact_pool$b_type; /* Structure type for IMGACT_POOL (DYN$C_PGD) */d unsigned char imgact_pool$b_subtype; /* Structure subtype for IMGACT_POOL (DYN$C_IMGACT_POOL) */[ void *imgact_pool$l_free_list; /* Header for free list (first IMGACT_POOL only) */ } IMGACT_POOL; $#pragma __member_alignment __restoreR#ifdef __INITI"AL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IMCBDEF_LOADED */ ww~A[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confident"ial proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential "**/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************* "*************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */F/* Source: 02-JAN-2002 15:17:28 $1$DGA8345:[LIB_H.SRC]IMPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IMPDEF ***/#ifndef __IMPDEF_LOADED#define __IMPDEF_LOADED 1 G#pragma __nostandard /* This file uses "non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknow"n_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* RMS32 IMPURE AREA OFFSET DEFINITIONS */N/* " */N/*- */N#define IMP$C_ASYEFN 30 /* EFN FOR ASYNC WAITS */Q#define IMP$C_IOREFN 30 /* EFN FOR IO RUNDOWN SYNCHRONIZATION */N#define IMP$C_ASYQIOEFN 31 /* EFN FOR ASYNC QIOS */N#define IMP$C_SYNCEFN 27 /* BASE EFN FOR SYNCHRONOUS QIO'S */N/* (28, 29 ALSO USED) " */P#define IMP$C_MBXEFN 26 /* EFN FOR QIOS TO NETWORK MAILBOXES */N/* */N#define IMP$C_NPIOFILES 63 /* ! OF PIO SEGMENT FILES */N#define IMP$C_ENTPERSEG 15 /* ! OF IIO SEGMENT SLOTS */N/* PER INDEX TABLE SEGMENT */#define IMP$S_IMPDEF 112 typedef struct _imp { __union {N unsigned" short int imp$w_rmsstatus; /* RMS OVERALL STATUS */ __struct {N unsigned imp$v_iios : 1; /* SET IF THIS IS THE IMAGE */N/* I.O SEGMENT */O unsigned imp$v_ast : 1; /* SET IF RUNNING AT EXEC AST LEVEL */N unsigned imp$v_temp1 : 1; /* TEMPORARY FLAG */N unsigned imp$v_temp2 : 1; /* " */N unsign"ed imp$v_iorundown : 1; /* SET IF IO RUNDOWN IN PROGRESS */[ unsigned imp$v_nop0bufs : 1; /* SET IF RMS USE OF P0 FOR IMAGE I/O DISABLED */N unsigned imp$v_ruh : 1; /* Set if within RMS RU Handler */N unsigned imp$v_recovery : 1; /* SET IF RECOVERY IN PROGRESS */N unsigned imp$v_ruh_synch : 1; /* SET IF RMS IO MUST SYNCH */N/* WITH THE RU HANDLER */' unsigned imp$v_fil "l_0_ : 7;# } imp$r_rmsstatus_bits;N/* */" } imp$r_rmsstatus_overlay;N unsigned char imp$b_prot; /* PROTECTION FOR I/O BUFFER PAGES */N char impdef$$_fill_1; /* SPARE */N void *imp$l_iosegaddr; /* ADDRESS OF FIRST FREE PAGE */N/* IN THIS (IMAGE OR PROCESS) */N/* I/O SEGMENT " */N unsigned int imp$l_ioseglen; /* ! OF FREE BYTES AT ABOVE ADDR */N void *imp$l_freepglh [2]; /* FREE PAGE LIST HEAD */N unsigned int imp$l_saved_sp; /* SAVED VALUE OF SP AT ENTRY */N void *imp$l_ifabtbl; /* IFAB TABLE ADDR */N void *imp$l_irabtbl; /* IRAB TABLE ADDR */N unsigned short int imp$w_entperseg; /* ! O "F SLOTS PER TABLE SEGMENT */Z unsigned short int imp$w_num_ifabs; /* NUMBER OF IFABS & IRABS CURRENTLY ALLOCATED */N void *imp$l_asb_lookaside_list [2]; /* ASB LOOKASIDE LIST HEAD */Y void *imp$l_ifbtblink; /* START OF IFAB TABLE (LINK TO NEXT SEGMENT) */N int impdef$$_fill_2 [15]; /* FIRST IFAB TABLE SEGMENT */Y void *imp$l_irbtblink; /* START OF IRAB TABLE (LINK TO NEXT SEGMENT) */ } IMP; #if !defined(__VAXC)"?#define imp$w_rmsstatus imp$r_rmsstatus_overlay.imp$w_rmsstatusJ#define imp$v_iios imp$r_rmsstatus_overlay.imp$r_rmsstatus_bits.imp$v_iiosH#define imp$v_ast imp$r_rmsstatus_overlay.imp$r_rmsstatus_bits.imp$v_astL#define imp$v_temp1 imp$r_rmsstatus_overlay.imp$r_rmsstatus_bits.imp$v_temp1L#define imp$v_temp2 imp$r_rmsstatus_overlay.imp$r_rmsstatus_bits.imp$v_temp2T#define imp$v_iorundown imp$r_rmsstatus_overlay.imp$r_rmsstatus_bits.imp$v_iorundownR#define imp$v_nop0bufs imp$r_rmsstatus_overlay ".imp$r_rmsstatus_bits.imp$v_nop0bufsH#define imp$v_ruh imp$r_rmsstatus_overlay.imp$r_rmsstatus_bits.imp$v_ruhR#define imp$v_recovery imp$r_rmsstatus_overlay.imp$r_rmsstatus_bits.imp$v_recoveryT#define imp$v_ruh_synch imp$r_rmsstatus_overlay.imp$r_rmsstatus_bits.imp$v_ruh_synch"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the" previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IMPDEF_LOADED */ wwA[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to "be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or dis"closed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct "-2024 15:23:38 by OpenVMS SDL V3.7 */H/* Source: 08-SEP-2005 08:02:43 $1$DGA8345:[LIB_H.SRC]IMSEMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $imsemdef ***/#ifndef __IMSEMDEF_LOADED#define __IMSEMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER"_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#e"lse#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Inner mode semaphore Definitions */N/* */   #include #define IMSEM_HIST$K_LENGTH 16 c#if !defined(_"_NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _imsem_hist {#pragma __nomember_alignment% unsigned __int64 imsem_hist$q_pc;, unsigned __int64 imsem_hist$q_semaphore; } IMSEM_HIST; #define IMSEM$M_KAST_PENDING 0x1 #define IMSEM$M_EAST_PENDING 0x2#define IMSEM$M_RS_WAITRS 0x4#define IMSEM$M_TM_WAITRS 0x8!#define IMSEM$M_CHECK_UPCALL 0x1"0#define IMSEM$M_EXCLUSIVE 0x20X#define IMSEM$K_HIST_BUF_CNT 255 /* number of octaword history buffer entries */#define IMSEM$C_ACQ 1#define IMSEM$C_SPIN 2#define IMSEM$C_REL 3 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _imsem {#pragma __nomember_alignment __union {N unsigned __int64 imsem$q_imsem_qua "d; /* First quad of semaphore */ __struct {V unsigned short int imsem$w_owner_depth; /* depth of nested acquisitions */N unsigned short int imsem$w_owner; /* IM semaphore owner */c unsigned short int imsem$w_tolerant_count; /* count of tolerant thread-safe activity */ __union {N unsigned short int imsem$w_flags; /* Semaphore flags */ __struct {6 unsigned imsem$v_kast_ "pending : 1;6 unsigned imsem$v_east_pending : 1;3 unsigned imsem$v_rs_waitrs : 1;3 unsigned imsem$v_tm_waitrs : 1;6 unsigned imsem$v_check_upcall : 1;3 unsigned imsem$v_exclusive : 1;3 unsigned imsem$v_reserved : 10;' } imsem$r_flagdefs;' } imsem$r_flag_overlay;# } imsem$r_imsem_struct; } imsem$r_imsem_union;& unsign "ed int imsem$il_history_idx; int imsem$il_rsrvd;& IMSEM_HIST imsem$r_hist_buf [255]; } IMSEM; #if !defined(__VAXC)A#define imsem$q_imsem_quad imsem$r_imsem_union.imsem$q_imsem_quadX#define imsem$w_owner_depth imsem$r_imsem_union.imsem$r_imsem_struct.imsem$w_owner_depthL#define imsem$w_owner imsem$r_imsem_union.imsem$r_imsem_struct.imsem$w_owner^#define imsem$w_tolerant_count imsem$r_imsem_union.imsem$r_imsem_struct.imsem$w_tolerant_counta#define imsem$w_flags imsem$r_imsem_un"ion.imsem$r_imsem_struct.imsem$r_flag_overlay.imsem$w_flags#define imsem$v_kast_pending imsem$r_imsem_union.imsem$r_imsem_struct.imsem$r_flag_overlay.imsem$r_flagdefs.imsem$v_kast_pending#define imsem$v_east_pending imsem$r_imsem_union.imsem$r_imsem_struct.imsem$r_flag_overlay.imsem$r_flagdefs.imsem$v_east_pendingz#define imsem$v_rs_waitrs imsem$r_imsem_union.imsem$r_imsem_struct.imsem$r_flag_overlay.imsem$r_flagdefs.imsem$v_rs_waitrsz#define imsem$v_tm_waitrs imsem$r_imsem_union.imsem$r_imsem_ "struct.imsem$r_flag_overlay.imsem$r_flagdefs.imsem$v_tm_waitrs#define imsem$v_check_upcall imsem$r_imsem_union.imsem$r_imsem_struct.imsem$r_flag_overlay.imsem$r_flagdefs.imsem$v_check_upcallz#define imsem$v_exclusive imsem$r_imsem_union.imsem$r_imsem_struct.imsem$r_flag_overlay.imsem$r_flagdefs.imsem$v_exclusive"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __lo"ng /* Pointers are 64-bit */Mtypedef struct _imsem * IMSEM_PQ; /* Long pointer to a IMSEM structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else"typedef unsigned __int64 IMSEM_PQ;##endif /* __INITIAL_POINTER_SIZE *///// Add macro for IMSEM tracing//'extern unsigned __int64 imsem$gq_debug;&#define imsem_trace(_printf_args) \ if ( imsem$gq_debug & 1 ) \ { \4 int *imsem_rtn = (int *) (imsem$gq_debug & ~1); \." ((void (*)()) *imsem_rtn) _printf_args ; \ } $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IMSEMDEF_LOADED */ wwA[UM/***************************************************************************/M/** " **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** " **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** " **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */L/* Source: 15-JAN-2018 10:48:46 $1$DGA8345:[LIB_H.SRC]INDICTINTDEF.SDL;1 *//********************************************************************************************************************************//*** MODUL "E $INDICTINTDEF ***/#ifndef __INDICTINTDEF_LOADED#define __INDICTINTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#e"ndif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* Include base definitions " */ #include  N/*+ */N/* This is the internal to VMS defintion file [LIB] used with the component */N/* indictment server software pieces. */N/* */N/* **** NOTE **** */N/* " */N/* These constants are a direct conversion of Compaq Analyse's or should */N/* I say Tru64 UNIX's indict.h file. */N/* If any changes are done in that file then this file should be */N/* adjusted to match it. */N/*- */N/* " */N/* */N/* The urgency value represents the seriousness of the problem. */N/* The higher the urgency, the more serious the problem. */#define INDICT$K_MIN_URGENCY 1#define INDICT$K_MAX_URGENCY 10N/* */N/* The probability value represents the likelihood that the indicted */N/* compone"nt is the culprit. The higher the probability the more */N/* likely the initiator of the indictment notification believes the */N/* indicted component is the source of the errors. */"#define INDICT$K_MIN_PROBABILITY 1$#define INDICT$K_MAX_PROBABILITY 100N/* */N/* The total_indictments value represents the number of components */N/* being indicted for the same error. In "some cases, the indictment */N/* initiator isn't 100% sure which component needs to be replaced, */N/* so the initiator will indict more than one component. For the */N/* case where two components get indicted for the same error, the */N/* total_indictments should be set to 2. */"#define INDICT$K_MIN_INDICTMENTS 1##define INDICT$K_MAX_INDICTMENTS 10N/* " */N/* The reason for the indictment contains up to this */N/* many characters including the null terminator. */#define INDICT$K_MAX_DESCR 256N/* */N/* The initiator of the indictment request. This is the requestor's name */O/* and may contain up to this many characters including the null terminator. */!#define INDICT$K_MAX_INITIATOR 32N/* " */N/* The report handle contains up to this many characters including */N/* the null terminator. This is the requesting report program name(s). */$#define INDICT$K_MAX_REPORT_HNDL 128N/* */N/* The version number for indictment Info structure. */N/* This is set by the caller. */#define INDICT$K_V"ERSION_1 1N/* */N/* */N/* List of objects that can be indicted. If new object types get added */N/* to the enum type then place in between INDICT_COMPONENT and */N/* INDICT_OS_SPECIFIC since the validation code in sys_indict_Object API */N/* uses these values as the min and max. */N/* " */Q#define INDICT$K_COMPONENT 0 /* FRU Config ID of component indicted */N#define INDICT$K_PFN 1 /* Page Frame Number to be indicted */P#define INDICT$K_OS_SPECIFIC 2 /* OS HWR ID component to be indicted */  9#ifdef __cplusplus /* Define structure prototypes */ struct _iosb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If us "ing pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endiftypedef struct _indictrequest {#pragma __nomember_alignment void *indictreq$ps_qfl; void *indictreq$ps_qbl;N unsigned short int indictreq$w_size; /* STRUCTURE SIZE IN BYTES */N unsigned char indictreq$b_type; /* STRUCTURE TYPE CODE */N unsigned char indictreq$b_subtype; /* STRUCTURE SUB-TYPE CODE */R#ifdef __INITIAL_POINTER "_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _iosb *indictreq$pq_iosb_address; /* IOSB */#else, unsigned __int64 indictreq$pq_iosb_address;#endifN unsigned int indictreq$l_efn; /* Event Flag */N unsigned int indictreq$l_status; /* Status */! char indictreq$b_fill_0_ [4];c#if !defined(__N "OBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN ACB64 indictreq$r_base_acb; /* Embedded ACB64 structure */#pragma __nomember_alignmentN unsigned int indictreq$l_version; /* Version of Indictment Data */N unsigned int indictreq$l_object_type; /* Type of indictment */N __int64 indictreq$q_pfn_fill; /* NOSVAPTE_V9.0 Dave "Fairbanks */N unsigned __int64 indictreq$iq_component_id; /* Component Handle ID */N unsigned char indictreq$b_component_type; /* Component Handle Type */O unsigned char indictreq$b_component_subtype; /* Component Handle Subtype */' unsigned char indictreq$b_pad1 [6];N unsigned __int64 indictreq$iq_module_id; /* Module Handle ID */N unsigned char indictreq$b_module_type; /* Module Handle Type */N unsigned char indictreq$b_module_subtype"; /* Module Handle Subtype */' unsigned char indictreq$b_pad2 [6];N unsigned int indictreq$l_urgency; /* Urgency of indictment request */N unsigned int indictreq$l_probability; /* Probability of correct fault */Q unsigned int indictreq$l_total_indictments; /* Total number to be indicted */N unsigned int indictreq$l_description_size; /* Size of descriptor string */N unsigned int indictreq$l_initiator_size; /* Size of initiator string */S unsigned int indictr "eq$l_report_handle_size; /* Size of report handle string */N char indictreq$b_description [256]; /* Readable description of problem */' unsigned char indictreq$b_pad3 [8];N char indictreq$b_initiator [32]; /* Who called us */' unsigned char indictreq$b_pad4 [8];N char indictreq$b_report_handle [128]; /* report handle program name */' unsigned char indictreq$b_pad5 [8];) unsigned char indictreq$b_spare [32];c#if !defined(__NOBASEALIGN_SUPPORT") && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 indictreq$q_pfn_phys_addr; /* NOSVAPTE_V9.0 Dave Fairbanks */#pragma __nomember_alignment! char indictreq$b_fill_1_ [8]; } INDICTREQUEST;  9#ifdef __cplusplus /* Define structure prototypes */ struct _spl; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) " /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _indictdef {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif void *indict$ps_request_qfl; void *indict$ps_request_qbl;N unsigned short int indict$w_size; /* STRUCTURE SIZE IN BYT "ES */N unsigned char indict$b_type; /* STRUCTURE TYPE CODE */N unsigned char indict$b_subtype; /* STRUCTURE SUB-TYPE CODE */N struct _spl *indict$ps_lock; /* Lock for access to queue */N int indict$l_server; /* Indictment server flag */N int indict$l_que_count; /* amount of indictment que entries */ } INDICTDEF; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE " /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard "#endif /* __INDICTINTDEF_LOADED */ wwBB[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential propriet"ary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** pr"oprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************* "*************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */I/* Source: 09-JUN-1993 15:30:19 $1$DGA8345:[LIB_H.SRC]INIRTNDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE INIRTNDEF ***/#ifndef __INIRTNDEF_LOADED#define __INIRTNDEF_LOADED 1 G#pragma __nostandard /* This file uses no"n-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_"params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define INIRTN$M_CALLED 0x1#define INIRTN$M_NO_RECALL 0x2N#define INIRTN$S_INIRTNDEF 4 /* Old size name - synonym */ typedef struct _inirtn { __union { int in "irtn$l_bits; __struct {O unsigned inirtn$v_called : 1; /* Routine has been called already */Q unsigned inirtn$v_no_recall : 1; /* Routine is not to be recalled */* unsigned inirtn$v_fill_2_ : 6; } inirtn$r_fill_1_; } inirtn$r_fill_0_; } INIRTN; #if !defined(__VAXC)I#define inirtn$v_called inirtn$r_fill_0_.inirtn$r_fill_1_.inirtn$v_calledO#define inirtn$v_no_recall inirtn$r_fill_0_.inirtn$r_fill_1_.inirtn$v_no_recal"l"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __INIRTNDEF_LOADED */ wwiB[UM/***************************************************************************/M/** " **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** " **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/"M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */I/* Source: 02-MAR-2022 06:58:38 $1$DGA8345:[LIB_H.SRC]INTSTKDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $INTSTKD "EF ***/#ifndef __INTSTKDEF_LOADED#define __INTSTKDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __c"plusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */U/* Int"errupt stack - this defines the interrupt frame, which will be on the kernel */P/* or interrupt stack on x86. It is created by the code in XSWIS_EXCEPTION.S */N/* */N/* [LIB]CPUDEF.SDL contains a group of cells BC_FLAGS through BC_SS */N/* which must match the layout here. If $INTSTKDEF is changed, then */N/* $CPUDEF must be changed too. */N/* " */#define INTSTK$M_AST_CALLED 0x1#define INTSTK$M_ASTDEL 0x2 #define INTSTK$M_XSAVE_SAVED 0x4"#define INTSTK$M_FAULTY_TOWERS 0x8#define INTSTK$M_IMSEM 0x10$#define INTSTK$M_ALPHAREG_SAVED 0x20"#define INTSTK$M_FROM_SSENTRY 0x40 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ "intstk {#pragma __nomember_alignment __union {% unsigned char intstk$b_flags; __struct {h unsigned intstk$v_ast_called : 1; /* ASTDEL has been called at least once with this frame */S unsigned intstk$v_astdel : 1; /* Performing outer-mode AST delivery */\ unsigned intstk$v_xsave_saved : 1; /* XSAVE state saved prior to AST delivery */P unsigned intstk$v_faulty_towers : 1; /* Re-execute system service */X unsigned" intstk$v_imsem : 1; /* Inner-mode semaphore needs to be released */[ unsigned intstk$v_alphareg_saved : 1; /* Alpha registers saved in this frame */ unsigned intstk$v_from_ssentry : 1; /* in EXE$REFLECT(_SS) the INTSTK was built from an SSENTRY- overlays SSENTRY's SS_\ LOGGED */* unsigned intstk$v_fill_0_ : 1;! } intstk$r_flag_bits; } intstk$r_flags_union;Q unsigned char intstk$b_pprevmode; /* Save interrupted context's PREVMODE */" __union {Q unsigned char intstk$b_prevmode; /* Save interrupted context's CURMODE */) unsigned char intstk$b_prevstack;" } intstk$r_prevmode_union;N unsigned char intstk$b_ipl; /* SWIS IPL state */n unsigned int intstk$l_stkalign; /* How much allocated on this stack for int frame? Guaranteed that */N/* STKALIGN & 0XFFF0 is the actual length of the structure. In other */N/* words, the structure is always allocated on a 16- "byte boundary is */N/* is a multiple of 16-bytes long. */ __union {) unsigned short int intstk$w_size; __struct {N unsigned char intstk$b_astmode; /* Current AST delivery mode */3 unsigned char intstk$b_interrupt_depth;# } intstk$r_size_struct; } intstk$r_size_union;d unsigned char intstk$b_type; /* Make this structure look like a standard VMS structure */# unsign "ed char intstk$b_subtype;N int intstk$l_trap_type; /* Trap type */N unsigned __int64 intstk$q_fsbase; /* Saved base of FS segment */N unsigned __int64 intstk$q_rax; /* Saved x86 registers */" unsigned __int64 intstk$q_rdi;" unsigned __int64 intstk$q_rsi;" unsigned __int64 intstk$q_rdx;" unsigned __int64 intstk$q_rcx;! unsigned __int64 intstk$q_r8;! unsigned __int64 intstk$q_r9;" unsigned __int64 i "ntstk$q_rbx;" unsigned __int64 intstk$q_rbp;" unsigned __int64 intstk$q_r10;" unsigned __int64 intstk$q_r11;" unsigned __int64 intstk$q_r12;" unsigned __int64 intstk$q_r13;" unsigned __int64 intstk$q_r14;" unsigned __int64 intstk$q_r15;Q unsigned __int64 intstk$q_alphareg [32]; /* Saved emulated Alpha registers */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to "64-bit pointers */f void *intstk$pq_prev_frame; /* Pointer to the previously active Interrupt/SSENTRY frame */#else' unsigned __int64 intstk$pq_prev_frame;#endifT int intstk$l_prev_frame_mode; /* Mode interrupted by the previous frame */% unsigned int intstk$l_filler_pfm;( unsigned short int intstk$w_cpu_num;/ unsigned short int intstk$w_ssentry_offset;- unsigned short int intstk$w_filler_2 [2];N unsigned __int64 intstk$q_vector; /* Interrupt vecto "r we came in on */Z unsigned __int64 intstk$q_error_code; /* From here on this is the CPU-defined frame */" unsigned __int64 intstk$q_rip;! unsigned __int64 intstk$q_cs;% unsigned __int64 intstk$q_rflags;" unsigned __int64 intstk$q_rsp;! unsigned __int64 intstk$q_ss; } INTSTK; #if !defined(__VAXC):#define intstk$b_flags intstk$r_flags_union.intstk$b_flagsB#define intstk$r_flag_bits intstk$r_flags_union.intstk$r_flag_bitsB#define intstk$v_ast_called intstk$r_f"lag_bits.intstk$v_ast_called:#define intstk$v_astdel intstk$r_flag_bits.intstk$v_astdelD#define intstk$v_xsave_saved intstk$r_flag_bits.intstk$v_xsave_savedH#define intstk$v_faulty_towers intstk$r_flag_bits.intstk$v_faulty_towers8#define intstk$v_imsem intstk$r_flag_bits.intstk$v_imsemJ#define intstk$v_alphareg_saved intstk$r_flag_bits.intstk$v_alphareg_savedF#define intstk$v_from_ssentry intstk$r_flag_bits.intstk$v_from_ssentryC#define intstk$b_prevmode intstk$r_prevmode_union.intstk$b_prevmod "eE#define intstk$b_prevstack intstk$r_prevmode_union.intstk$b_prevstack7#define intstk$w_size intstk$r_size_union.intstk$w_sizeE#define intstk$r_size_struct intstk$r_size_union.intstk$r_size_struct>#define intstk$b_astmode intstk$r_size_struct.intstk$b_astmodeN#define intstk$b_interrupt_depth intstk$r_size_struct.intstk$b_interrupt_depth"#endif /* #if !defined(__VAXC) */ #define INTSTK$K_LENGTH 480#define INTSTK$C_LENGTH 480Y#define INTSTK$S_INTSTKDEF 480 /* Old size name", synonym for INTSTK$S_INTSTK */ #define SSENTRY$M_AST_CALLED 0x1#define SSENTRY$M_ASTDEL 0x2!#define SSENTRY$M_XSAVE_SAVED 0x4##define SSENTRY$M_FAULTY_TOWERS 0x8#define SSENTRY$M_IMSEM 0x10%#define SSENTRY$M_ALPHAREG_SAVED 0x20 #define SSENTRY$M_SS_LOGGED 0x40 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ssentry {#pragm "a __nomember_alignment __union {& unsigned char ssentry$b_flags; __struct {i unsigned ssentry$v_ast_called : 1; /* ASTDEL has been called at least once with this frame */T unsigned ssentry$v_astdel : 1; /* Performing outer-mode AST delivery */] unsigned ssentry$v_xsave_saved : 1; /* XSAVE state saved prior to AST delivery */Q unsigned ssentry$v_faulty_towers : 1; /* Re-execute system service */Y unsigned ssentry$v "_imsem : 1; /* Inner-mode semaphore needs to be released */\ unsigned ssentry$v_alphareg_saved : 1; /* Alpha registers saved in this frame */N unsigned ssentry$v_ss_logged : 1; /* Service is being logged */+ unsigned ssentry$v_fill_1_ : 1;" } ssentry$r_flag_bits; } ssentry$r_flags_union;Q unsigned char ssentry$b_pprevmode; /* Save interrupted context's PREVMODE */ __union {R unsigned char ssentry$b_prevmode; /* Save inte"rrupted context's CURMODE */* unsigned char ssentry$b_prevstack;# } ssentry$r_prevmode_union;N unsigned char ssentry$b_ipl; /* SWIS IPL state */n unsigned int ssentry$l_stkalign; /* How much allocated on this stack for int frame? Guaranteed that */N/* STKALIGN & 0XFFF0 is the actual length of the structure. In other */N/* words, the structure is always allocated on a 16-byte boundary is */N/* is a multiple of 16-bytes long. " */ __union {* unsigned short int ssentry$w_size; __struct {N unsigned char ssentry$b_astmode; /* Current AST delivery mode */$ char ssentry$b_filler_1;$ } ssentry$r_size_struct; } ssentry$r_size_union;d unsigned char ssentry$b_type; /* Make this structure look like a standard VMS structure */$ unsigned char ssentry$b_subtype; int ssentry$l_filler_3;N unsigned __int64 ssent"ry$q_fsbase; /* Saved base of FS segment */N unsigned __int64 ssentry$q_arg_info; /* RAX */N unsigned __int64 ssentry$q_arg1; /* RDI */N unsigned __int64 ssentry$q_arg2; /* RSI */N unsigned __int64 ssentry$q_arg3; /* RDX */N unsigned __int64 ssentry$q_arg4; /* RCX */N unsigned __int64 ssentry$q_arg5; /* R8 " */N unsigned __int64 ssentry$q_arg6; /* R9 */W unsigned __int64 ssentry$q_ss_log_seq; /* System service logging sequence number */V unsigned __int64 ssentry$q_ss_log_buf; /* System service logging buffer address */N unsigned __int64 ssentry$q_ret1; /* RAX return value 1 */N unsigned __int64 ssentry$q_ret2; /* RDX return value 2 */# unsigned __int64 ssentry$q_r12;# unsigned __int64 s"sentry$q_r13;Z/* Add a SSDISP structure for temporary use (in case of a priv. image provided service) */V unsigned __int64 ssentry$q_ssdisp_procedure; /* Pointer to the actual procedure */N unsigned int ssentry$l_ssdisp_flags; /* System Service flags */T unsigned char ssentry$b_ssdisp_mode; /* Execution mode for the system service */% char ssentry$b_ssdisp_filler [3];R unsigned __int64 ssentry$q_alphareg [32]; /* Saved emulated Alpha registers */R#ifdef __INITIAL_POI "NTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */f void *ssentry$pq_prev_frame; /* Pointer to the previously active Interrupt/SSENTRY frame */#else( unsigned __int64 ssentry$pq_prev_frame;#endifT int ssentry$l_prev_frame_mode; /* Mode interrupted by the previous frame */& unsigned int ssentry$l_filler_pfm; __int64 ssentry$q_filler_3;X unsigned __int64 ssentry "$q_service_number; /* Number of the system service called */- unsigned __int64 ssentry$q_service_flags;N unsigned __int64 ssentry$q_rip; /* Return Address */, unsigned __int64 ssentry$q_stkargs_size;& unsigned __int64 ssentry$q_rflags;# unsigned __int64 ssentry$q_rsp;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *ssentr "y$pq_copied_to;#else' unsigned __int64 ssentry$pq_copied_to;#endif } SSENTRY; #if !defined(__VAXC)=#define ssentry$b_flags ssentry$r_flags_union.ssentry$b_flagsE#define ssentry$r_flag_bits ssentry$r_flags_union.ssentry$r_flag_bitsE#define ssentry$v_ast_called ssentry$r_flag_bits.ssentry$v_ast_called=#define ssentry$v_astdel ssentry$r_flag_bits.ssentry$v_astdelG#define ssentry$v_xsave_saved ssentry$r_flag_bits.ssentry$v_xsave_savedK#define ssentry$v_faulty_towers ssentry$r_"flag_bits.ssentry$v_faulty_towers;#define ssentry$v_imsem ssentry$r_flag_bits.ssentry$v_imsemM#define ssentry$v_alphareg_saved ssentry$r_flag_bits.ssentry$v_alphareg_savedC#define ssentry$v_ss_logged ssentry$r_flag_bits.ssentry$v_ss_loggedF#define ssentry$b_prevmode ssentry$r_prevmode_union.ssentry$b_prevmodeH#define ssentry$b_prevstack ssentry$r_prevmode_union.ssentry$b_prevstack:#define ssentry$w_size ssentry$r_size_union.ssentry$w_sizeH#define ssentry$r_size_struct ssentry$r_size_union.s "sentry$r_size_structA#define ssentry$b_astmode ssentry$r_size_struct.ssentry$b_astmode"#endif /* #if !defined(__VAXC) */ #define SSENTRY$K_LENGTH 480#define SSENTRY$C_LENGTH 480N/* X86_64, IA64, Alpha */ #ifdef __INITIAL_POINTER_SIZEL #pragma __required_pointer_size __save /* Save current pointer size */G #pragma __required_pointer_size __long /* Pointers are 64-bit */L typedef INTSTK *INTSTK_PQ; /* Long pointer "to an INTSTK structure. */T #pragma __required_pointer_size __restore /* Return to previous pointer size */#else& typedef unsigned __int64 INTSTK_PQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* "__INTSTKDEF_LOADED */ ww@B[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. " **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M"/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */I/* Source: 23-MAR-1992 17:03:17 $1$DGA8345:[LIB_H.SRC]IO0202DEF.SDL;1 " *//********************************************************************************************************************************//*** MODULE $IO0202DEF ***/#ifndef __IO0202DEF_LOADED#define __IO0202DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the" previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __un "ion union#else#define __union variant_union#endif#endif N#define IO0202$Q_IOCSR_H 2 /* High nibble of address */N#define IO0202$Q_IOCSR 268435456 /* I/O control/status register */N#define IO0202$Q_CPU0CSR 0 /* CPU0 control/status register */N#define IO0202$Q_CPU1CSR 134217728 /* CPU1 control/status register */N#define IO0202$Q_CMM0CSR 1073741824 /* MEM0 control/status register */N#define IO0202$Q_CMM1CSR 134217728"0 /* MEM1 control/status register */N#define IO0202$Q_CMM2CSR 1610612736 /* MEM2 control/status register */N#define IO0202$Q_CMM3CSR 1879048192 /* MEM3 control/status register */N#define IO0202$Q_CERR1 268435488 /* Cbus error register 1 */N#define IO0202$Q_CERR2 268435520 /* Cbus error register 2 */N#define IO0202$Q_CERR3 268435552 /* Cbus error register 3 */N#define IO0202$Q_LMBPR 268435584 /* Lbus mailbos poin"ter register */P#define IO0202$Q_FMBPR 268435616 /* Futurebus mailbos pointer register */Q#define IO0202$Q_DIAGCSR 268435648 /* Diagnostic control/status register */Q#define IO0202$Q_FIVECT 268435680 /* Futurebus interrupt vector register */N#define IO0202$Q_FHVECT 268435712 /* Futurebus halt vector register */N#define IO0202$Q_FERRI 268435744 /* Futurebus error register 1 */N#define IO0202$Q_FERR2 268435776 /* Futurebus error register 2 "*/N#define IO0202$Q_LINT 268435808 /* Local interrupt register */N#define IO0202$Q_LERR1 268435840 /* Lbus error register 1 */N#define IO0202$Q_LERR2 268435872 /* Lbus error register 1 */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus } "#endif#pragma __standard #endif /* __IO0202DEF_LOADED */ wwPC[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior wre"IMSEMDEF" INDICTINTDEF" INIRTNDEF@INIT_RTN_SETUP" INTSTKDEF"& IO0202DEF"P IO0302DEF#$ IO0402DEF/#, IO0602DEFP# IO0702DEFg#R IO0802DEFr#. IO0902DEF# IO0C05DEF# IO0E04DEF#< IO0F05DEF#n IO1504DEF#IOBDDEF#IOCDEF:$IOCNTDEF IOC_ROUTINESS$BIOGENDEFe$ IOHANDLEDEFo$IOVECDEF$xIO_ROUTINES_DATA$ IPFINSDEF#'IPLDEF.'IPMIDEF/(IRCDEFG(IRPDEF KA1605DEF` LDR_ROUTINES"itten permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VM"S Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */I/* Source: 13-JUN-1992 19:0 "5:33 $1$DGA8345:[LIB_H.SRC]IO0302DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IO0302DEF ***/#ifndef __IO0302DEF_LOADED#define __IO0302DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __"required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __"union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif &#define IO0302$L_UART0A_RR0 -201326592&#define IO0302$L_UART0A_RR8 -201326528&#define IO0302$L_UART0B_RR0 -201326464&#define IO0302$L_UART0B_RR8 -201326400&#define IO0302$L_UART1B_RR0 -192937984&#define IO0302$L_UART1B_RR8 -192937920&#define IO0302$L_UART1A_RR0 -192937856&#define IO0302$L_UART1A_RR8 -192937792&#define IO0302$L_UART2B_RR0 -184549376&#define IO0302$L_UART2B_RR8 -184 "549312&#define IO0302$L_UART2A_RR0 -184549248&#define IO0302$L_UART2A_RR8 -184549184)#define IO0302$L_WATCH_SECONDS -167772160)#define IO0302$L_WATCH_MINUTES -167772032'#define IO0302$L_WATCH_HOURS -167771904.#define IO0302$L_WATCH_DAY_OF_MONTH -167771712'#define IO0302$L_WATCH_MONTH -167771648&#define IO0302$L_WATCH_YEAR -167771584&#define IO0302$L_WATCH_CSRA -167771520&#define IO0302$L_WATCH_CSRB -167771456&#define IO0302$L_WATCH_CSRC -167771392&#define IO0302$L_WATCH_CSRD -167771328 "%#define IO0302$L_WATCH_RAM -167771264&#define IO0302$L_GBUS_WHAMI -150994944%#define IO0302$L_GBUS_LEDS -150994880&#define IO0302$L_GBUS_PMASK -150994816%#define IO0302$L_GBUS_INTR -150994752%#define IO0302$L_GBUS_HALT -150994688'#define IO0302$L_GBUS_LSBRST -150994624%#define IO0302$L_GBUS_MISC -150994560*#define IO0302$L_GBUS_RMODE_ENA -142606336N#define IO0302$L_SLOT0_LDEV -134217728 /* DEVICE */N#define IO0302$L_SLOT0_LBER -134217664 /* ERROR " */N#define IO0302$L_SLOT0_LCNF -134217600 /* CONFIGURATION */N#define IO0302$L_SLOT0_IBR -134217536 /* REPAIR */N#define IO0302$L_SLOT0_LMMR0 -134217216 /* MEM MAPPING 0 */N#define IO0302$L_SLOT0_LMMR1 -134217152 /* MEM MAPPING 1 */N#define IO0302$L_SLOT0_LMMR2 -134217088 /* MEM MAPPING 2 */N#define IO0302$L_SLOT0_LMMR3 -134217024 /* MEM MAPPING 3 */N#def"ine IO0302$L_SLOT0_LMMR4 -134216960 /* MEM MAPPING 4 */N#define IO0302$L_SLOT0_LMMR5 -134216896 /* MEM MAPPING 5 */N#define IO0302$L_SLOT0_LMMR6 -134216832 /* MEM MAPPING 6 */N#define IO0302$L_SLOT0_LMMR7 -134216768 /* MEM MAPPING 7 */N#define IO0302$L_SLOT0_LBESR0 -134216192 /* BUS ERROR SYNDROME 0 */N#define IO0302$L_SLOT0_LBESR1 -134216128 /* BUS ERROR SYNDROME 1 */N#define IO0302$L_SLOT0_LBESR2 "-134216064 /* BUS ERROR SYNDROME 2 */N#define IO0302$L_SLOT0_LBESR3 -134216000 /* BUS ERROR SYNDROME 3 */N#define IO0302$L_SLOT0_LBECR0 -134215936 /* BUS ERROR COMMAND 0 */N#define IO0302$L_SLOT0_LBECR1 -134215872 /* BUS ERROR COMMAND 1 */N#define IO0302$L_SLOT1_LDEV -130023424 /* DEVICE REG */N#define IO0302$L_SLOT1_LBER -130023360 /* ERROR */N#define IO0302$L_SLOT1_LCNF -130023296 /* CONFIGURATION" */N#define IO0302$L_SLOT1_IBR -130023232 /* REPAIR */N#define IO0302$L_SLOT1_LMMR0 -130022912 /* MEM MAPPING 0 */N#define IO0302$L_SLOT1_LMMR1 -130022848 /* MEM MAPPING 1 */N#define IO0302$L_SLOT1_LMMR2 -130022784 /* MEM MAPPING 2 */N#define IO0302$L_SLOT1_LMMR3 -130022720 /* MEM MAPPING 3 */N#define IO0302$L_SLOT1_LMMR4 -130022656 /* MEM MAPPING 4 */N#d"efine IO0302$L_SLOT1_LMMR5 -130022592 /* MEM MAPPING 5 */N#define IO0302$L_SLOT1_LMMR6 -130022528 /* MEM MAPPING 6 */N#define IO0302$L_SLOT1_LMMR7 -130022464 /* MEM MAPPING 7 */N#define IO0302$L_SLOT1_LBESR0 -130021888 /* BUS ERROR SYNDROME 0 */N#define IO0302$L_SLOT1_LBESR1 -130021824 /* BUS ERROR SYNDROME 1 */N#define IO0302$L_SLOT1_LBESR2 -130021760 /* BUS ERROR SYNDROME 2 */N#define IO0302$L_SLOT1_LBESR"3 -130021696 /* BUS ERROR SYNDROME 3 */N#define IO0302$L_SLOT1_LBECR0 -130021632 /* BUS ERROR COMMAND 0 */N#define IO0302$L_SLOT1_LBECR1 -130021568 /* BUS ERROR COMMAND 1 */N#define IO0302$L_SLOT2_LDEV -125829120 /* DEVICE REG */N#define IO0302$L_SLOT2_LBER -125829056 /* ERROR */N#define IO0302$L_SLOT2_LCNF -125828992 /* CONFIGURATION */N#define IO0302$L_SLOT2_IBR -125828928 /* REPAIR " */N#define IO0302$L_SLOT2_LMMR0 -125828608 /* MEM MAPPING 0 */N#define IO0302$L_SLOT2_LMMR1 -125828544 /* MEM MAPPING 1 */N#define IO0302$L_SLOT2_LMMR2 -125828480 /* MEM MAPPING 2 */N#define IO0302$L_SLOT2_LMMR3 -125828416 /* MEM MAPPING 3 */N#define IO0302$L_SLOT2_LMMR4 -125828352 /* MEM MAPPING 4 */N#define IO0302$L_SLOT2_LMMR5 -125828288 /* MEM MAPPING 5 */N"#define IO0302$L_SLOT2_LMMR6 -125828224 /* MEM MAPPING 6 */N#define IO0302$L_SLOT2_LMMR7 -125828160 /* MEM MAPPING 7 */N#define IO0302$L_SLOT2_LBESR0 -125827584 /* BUS ERROR SYNDROME 0 */N#define IO0302$L_SLOT2_LBESR1 -125827520 /* BUS ERROR SYNDROME 1 */N#define IO0302$L_SLOT2_LBESR2 -125827456 /* BUS ERROR SYNDROME 2 */N#define IO0302$L_SLOT2_LBESR3 -125827392 /* BUS ERROR SYNDROME 3 */N#define IO0302$L_SLOT2_LBE#CR0 -125827328 /* BUS ERROR COMMAND 0 */N#define IO0302$L_SLOT2_LBECR1 -125827264 /* BUS ERROR COMMAND 1 */N#define IO0302$L_SLOT3_LDEV -121634816 /* DEVICE REG */N#define IO0302$L_SLOT3_LBER -121634752 /* ERROR */N#define IO0302$L_SLOT3_LCNF -121634688 /* CONFIGURATION */N#define IO0302$L_SLOT3_IBR -121634624 /* REPAIR */N#define IO0302$L_SLOT3_LMMR0 -121634304 /* MEM MAPPI#NG 0 */N#define IO0302$L_SLOT3_LMMR1 -121634240 /* MEM MAPPING 1 */N#define IO0302$L_SLOT3_LMMR2 -121634176 /* MEM MAPPING 2 */N#define IO0302$L_SLOT3_LMMR3 -121634112 /* MEM MAPPING 3 */N#define IO0302$L_SLOT3_LMMR4 -121634048 /* MEM MAPPING 4 */N#define IO0302$L_SLOT3_LMMR5 -121633984 /* MEM MAPPING 5 */N#define IO0302$L_SLOT3_LMMR6 -121633920 /* MEM MAPPING 6 */#N#define IO0302$L_SLOT3_LMMR7 -121633856 /* MEM MAPPING 7 */N#define IO0302$L_SLOT3_LBESR0 -121633280 /* BUS ERROR SYNDROME 0 */N#define IO0302$L_SLOT3_LBESR1 -121633216 /* BUS ERROR SYNDROME 1 */N#define IO0302$L_SLOT3_LBESR2 -121633152 /* BUS ERROR SYNDROME 2 */N#define IO0302$L_SLOT3_LBESR3 -121633088 /* BUS ERROR SYNDROME 3 */N#define IO0302$L_SLOT3_LBECR0 -121633024 /* BUS ERROR COMMAND 0 */N#define IO0302$L_SLOT3_L#BECR1 -121632960 /* BUS ERROR COMMAND 1 */N#define IO0302$L_SLOT4_LDEV -117440512 /* DEVICE REG */N#define IO0302$L_SLOT4_LBER -117440448 /* ERROR */N#define IO0302$L_SLOT4_LCNF -117440384 /* CONFIGURATION */N#define IO0302$L_SLOT4_IBR -117440320 /* REPAIR */N#define IO0302$L_SLOT4_LMMR0 -117440000 /* MEM MAPPING 0 */N#define IO0302$L_SLOT4_LMMR1 -117439936 /* MEM MAP#PING 1 */N#define IO0302$L_SLOT4_LMMR2 -117439872 /* MEM MAPPING 2 */N#define IO0302$L_SLOT4_LMMR3 -117439808 /* MEM MAPPING 3 */N#define IO0302$L_SLOT4_LMMR4 -117439744 /* MEM MAPPING 4 */N#define IO0302$L_SLOT4_LMMR5 -117439680 /* MEM MAPPING 5 */N#define IO0302$L_SLOT4_LMMR6 -117439616 /* MEM MAPPING 6 */N#define IO0302$L_SLOT4_LMMR7 -117439552 /* MEM MAPPING 7 #*/N#define IO0302$L_SLOT4_LBESR0 -117438976 /* BUS ERROR SYNDROME 0 */N#define IO0302$L_SLOT4_LBESR1 -117438912 /* BUS ERROR SYNDROME 1 */N#define IO0302$L_SLOT4_LBESR2 -117438848 /* BUS ERROR SYNDROME 2 */N#define IO0302$L_SLOT4_LBESR3 -117438784 /* BUS ERROR SYNDROME 3 */N#define IO0302$L_SLOT4_LBECR0 -117438720 /* BUS ERROR COMMAND 0 */N#define IO0302$L_SLOT4_LBECR1 -117438656 /* BUS ERROR COMMAND 1 */N#define IO0302$L_SLOT5#_LDEV -113246208 /* DEVICE REG */N#define IO0302$L_SLOT5_LBER -113246144 /* ERROR */N#define IO0302$L_SLOT5_LCNF -113246080 /* CONFIGURATION */N#define IO0302$L_SLOT5_IBR -113246016 /* REPAIR */N#define IO0302$L_SLOT5_LMMR0 -113245696 /* MEM MAPPING 0 */N#define IO0302$L_SLOT5_LMMR1 -113245632 /* MEM MAPPING 1 */N#define IO0302$L_SLOT5_LMMR2 -113245568 /* MEM M#APPING 2 */N#define IO0302$L_SLOT5_LMMR3 -113245504 /* MEM MAPPING 3 */N#define IO0302$L_SLOT5_LMMR4 -113245440 /* MEM MAPPING 4 */N#define IO0302$L_SLOT5_LMMR5 -113245376 /* MEM MAPPING 5 */N#define IO0302$L_SLOT5_LMMR6 -113245312 /* MEM MAPPING 6 */N#define IO0302$L_SLOT5_LMMR7 -113245248 /* MEM MAPPING 7 */N#define IO0302$L_SLOT5_LBESR0 -113244672 /* BUS ERROR SYNDROME 0 # */N#define IO0302$L_SLOT5_LBESR1 -113244608 /* BUS ERROR SYNDROME 1 */N#define IO0302$L_SLOT5_LBESR2 -113244544 /* BUS ERROR SYNDROME 2 */N#define IO0302$L_SLOT5_LBESR3 -113244480 /* BUS ERROR SYNDROME 3 */N#define IO0302$L_SLOT5_LBECR0 -113244416 /* BUS ERROR COMMAND 0 */N#define IO0302$L_SLOT5_LBECR1 -113244352 /* BUS ERROR COMMAND 1 */N#define IO0302$L_SLOT6_LDEV -109051904 /* DEVICE REG */N#define IO0302$L_SLO #T6_LBER -109051840 /* ERROR */N#define IO0302$L_SLOT6_LCNF -109051776 /* CONFIGURATION */N#define IO0302$L_SLOT6_IBR -109051712 /* REPAIR */N#define IO0302$L_SLOT6_LMMR0 -109051392 /* MEM MAPPING 0 */N#define IO0302$L_SLOT6_LMMR1 -109051328 /* MEM MAPPING 1 */N#define IO0302$L_SLOT6_LMMR2 -109051264 /* MEM MAPPING 2 */N#define IO0302$L_SLOT6_LMMR3 -109051200 /* MEM # MAPPING 3 */N#define IO0302$L_SLOT6_LMMR4 -109051136 /* MEM MAPPING 4 */N#define IO0302$L_SLOT6_LMMR5 -109051072 /* MEM MAPPING 5 */N#define IO0302$L_SLOT6_LMMR6 -109051008 /* MEM MAPPING 6 */N#define IO0302$L_SLOT6_LMMR7 -109050944 /* MEM MAPPING 7 */N#define IO0302$L_SLOT6_LBESR0 -109050368 /* BUS ERROR SYNDROME 0 */N#define IO0302$L_SLOT6_LBESR1 -109050304 /* BUS ERROR SYNDROME 1  # */N#define IO0302$L_SLOT6_LBESR2 -109050240 /* BUS ERROR SYNDROME 2 */N#define IO0302$L_SLOT6_LBESR3 -109050176 /* BUS ERROR SYNDROME 3 */N#define IO0302$L_SLOT6_LBECR0 -109050112 /* BUS ERROR COMMAND 0 */N#define IO0302$L_SLOT6_LBECR1 -109050048 /* BUS ERROR COMMAND 1 */N#define IO0302$L_SLOT7_LDEV -104857600 /* DEVICE REG */N#define IO0302$L_SLOT7_LBER -104857536 /* ERROR */N#define IO0302$L_S #LOT7_LCNF -104857472 /* CONFIGURATION */N#define IO0302$L_SLOT7_IBR -104857408 /* REPAIR */N#define IO0302$L_SLOT7_LMMR0 -104857088 /* MEM MAPPING 0 */N#define IO0302$L_SLOT7_LMMR1 -104857024 /* MEM MAPPING 1 */N#define IO0302$L_SLOT7_LMMR2 -104856960 /* MEM MAPPING 2 */N#define IO0302$L_SLOT7_LMMR3 -104856896 /* MEM MAPPING 3 */N#define IO0302$L_SLOT7_LMMR4 -104856832 /* M #EM MAPPING 4 */N#define IO0302$L_SLOT7_LMMR5 -104856768 /* MEM MAPPING 5 */N#define IO0302$L_SLOT7_LMMR6 -104856704 /* MEM MAPPING 6 */N#define IO0302$L_SLOT7_LMMR7 -104856640 /* MEM MAPPING 7 */N#define IO0302$L_SLOT7_LBESR0 -104856064 /* BUS ERROR SYNDROME 0 */N#define IO0302$L_SLOT7_LBESR1 -104856000 /* BUS ERROR SYNDROME 1 */N#define IO0302$L_SLOT7_LBESR2 -104855936 /* BUS ERROR SYNDROME 2 # */N#define IO0302$L_SLOT7_LBESR3 -104855872 /* BUS ERROR SYNDROME 3 */N#define IO0302$L_SLOT7_LBECR0 -104855808 /* BUS ERROR COMMAND 0 */N#define IO0302$L_SLOT7_LBECR1 -104855744 /* BUS ERROR COMMAND 1 */N#define IO0302$L_SLOT8_LDEV -100663296 /* DEVICE REG */N#define IO0302$L_SLOT8_LBER -100663232 /* ERROR */N#define IO0302$L_SLOT8_LCNF -100663168 /* CONFIGURATION */N#define IO0302$L#_SLOT8_IBR -100663104 /* REPAIR */N#define IO0302$L_SLOT8_LMMR0 -100662784 /* MEM MAPPING 0 */N#define IO0302$L_SLOT8_LMMR1 -100662720 /* MEM MAPPING 1 */N#define IO0302$L_SLOT8_LMMR2 -100662656 /* MEM MAPPING 2 */N#define IO0302$L_SLOT8_LMMR3 -100662592 /* MEM MAPPING 3 */N#define IO0302$L_SLOT8_LMMR4 -100662528 /* MEM MAPPING 4 */N#define IO0302$L_SLOT8_LMMR5 -100662464 /*# MEM MAPPING 5 */N#define IO0302$L_SLOT8_LMMR6 -100662400 /* MEM MAPPING 6 */N#define IO0302$L_SLOT8_LMMR7 -100662336 /* MEM MAPPING 7 */N#define IO0302$L_SLOT8_LBESR0 -100661760 /* BUS ERROR SYNDROME 0 */N#define IO0302$L_SLOT8_LBESR1 -100661696 /* BUS ERROR SYNDROME 1 */N#define IO0302$L_SLOT8_LBESR2 -100661632 /* BUS ERROR SYNDROME 2 */N#define IO0302$L_SLOT8_LBESR3 -100661568 /* BUS ERROR SYNDROME 3 # */N#define IO0302$L_SLOT8_LBECR0 -100661504 /* BUS ERROR COMMAND 0 */N#define IO0302$L_SLOT8_LBECR1 -100661440 /* BUS ERROR COMMAND 1 */N#define IO0302$L_LILID0 -100660736 /* INTERRUPT LEVEL0 IDENT */N#define IO0302$L_LILID1 -100660672 /* INTERRUPT LEVEL1 IDENT */N#define IO0302$L_LILID2 -100660608 /* INTERRUPT LEVEL2 IDENT */N#define IO0302$L_LILID3 -100660544 /* INTERRUPT LEVEL3 IDENT */N#define IO0302#$L_LCPUMASK -100660480 /* CPU INTERRUPT MASK */N#define IO0302$L_LMBPR -100660224 /* MAILBOX POINTER */N#define IO0302$L_IPCNSE -100655104 /* IO Port Chip Error */N#define IO0302$L_IPCVR -100655040 /* IO Port Chip Vector */N#define IO0302$L_IPCMSR -100654976 /* IO Port Chip Mode Select */N#define IO0302$L_IPCHST -100654912 /* IO Port Chip Hose Status */N#define IO0302$L_IPCDR -100654848 #/* IO Port Chip Diagnostic */N#define IO0302$L_LIOINTR -33554432 /* IO Interrupt reg */N#define IO0302$L_LIPINTR -33554368 /* IP Interrupt reg */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ #IO0302DEF_LOADED */ wwzC[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. # **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/*#* 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */I/* Source: 13-JUL-1992 20:06:46 $1$DGA8345:[LIB_H.SRC]IO0402DEF.SDL;1 * #//********************************************************************************************************************************//*** MODULE $IO0402DEF ***/#ifndef __IO0402DEF_LOADED#define __IO0402DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the p#reviously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __unio #n union#else#define __union variant_union#endif#endif N#define IO0402$Q_TC_NUMBER 1 /* Turbochannel number. */N/* Upper lw of physical */N/* address */N#define IO0402$Q_SCSI_CIR -804782080 /* SCSI Control Interrupts */N#define IO0402$Q_SCSI_IMER -804782072 /* SCSI Interrupt Mask Enable */N#define IO0402$Q_SCSI0_SDA -80477388#8 /* SCSI DMA Address */N#define IO0402$Q_SCSI0_SDIC -804773880 /* SCSI DMA Interrupt Control */N#define IO0402$Q_SCSI0_DMA_UNAL0 -804773872 /* SCSI DMA Unaligned Data 0 */N#define IO0402$Q_SCSI0_DMA_UNAL1 -804773864 /* SCSI DMA Unaligned Data 1 */N#define IO0402$Q_SCSI1_SDA -804773376 /* SCSI DMA Address */N#define IO0402$Q_SCSI1_SDIC -804773368 /* SCSI DMA Interrupt Control */N#define IO0402$Q_SCSI1_DMA_UNAL0 -804773360 /* SCSI DMA Unalig#ned Data 0 */N#define IO0402$Q_SCSI1_DMA_UNAL1 -804773352 /* SCSI DMA Unaligned Data 1 */N#define IO0402$Q_SCSI0_TC_LSB -804257792 /* SCSI Transfer Counter LSB */N#define IO0402$Q_SCSI0_TC_MSB -804257784 /* SCSI Transfer Counter MSB */N#define IO0402$Q_SCSI0_FIFO -804257776 /* SCSI FIFO */N#define IO0402$Q_SCSI0_CMD -804257768 /* SCSI Command */N#define IO0402$Q_SCSI0_STATUS -804257760 /* SCSI Status */N#define #IO0402$Q_SCSI0_INTR -804257752 /* SCSI Interrupt/Timeout */N#define IO0402$Q_SCSI0_SEQ -804257744 /* SCSI Sequence Step */N#define IO0402$Q_SCSI0_FF -804257736 /* SCSI FIFO Flags */N#define IO0402$Q_SCSI0_CONFIG1 -804257728 /* SCSI Configuration 1 */N#define IO0402$Q_SCSI0_CC -804257720 /* SCSI reserved/Clock Conversion */N#define IO0402$Q_SCSI0_TM -804257712 /* SCSI reserved/Test Mode */N#define IO0402$Q_SCSI0_CONFIG2 -80#4257704 /* SCSI Configuration 2 */N#define IO0402$Q_SCSI0_CONFIG3 -804257696 /* SCSI Configuration 3 */N#define IO0402$Q_SCSI1_TC_LSB -804257280 /* SCSI Transfer Counter LSB */N#define IO0402$Q_SCSI1_TC_MSB -804257272 /* SCSI Transfer Counter MSB */N#define IO0402$Q_SCSI1_FIFO -804257264 /* SCSI FIFO */N#define IO0402$Q_SCSI1_CMD -804257256 /* SCSI Command */N#define IO0402$Q_SCSI1_STATUS -804257248 /* SCSI Status # */N#define IO0402$Q_SCSI1_INTR -804257240 /* SCSI Interrupt */N#define IO0402$Q_SCSI1_SEQ -804257232 /* SCSI Sequence Step */N#define IO0402$Q_SCSI1_FF -804257224 /* SCSI FIFO Flags */N#define IO0402$Q_SCSI1_CONFIG1 -804257216 /* SCSI Configuration 1 */N#define IO0402$Q_SCSI1_CC -804257208 /* SCSI reserved/Clock Conversion */N#define IO0402$Q_SCSI1_TM -804257200 /* SCSI reserved/Test Mode */N#defin#e IO0402$Q_SCSI1_CONFIG2 -804257192 /* SCSI Configuration 2 */N#define IO0402$Q_SCSI1_CONFIG3 -804257184 /* SCSI Configuration 3 */N#define IO0402$Q_SCSI0_DMA -803733504 /* SCSI DMA Buffer */N#define IO0402$Q_SCSI1_DMA -803732992 /* SCSI DMA Buffer */N#define IO0402$Q_IOSLOT -738197504 /* IO Slot Configuration */N#define IO0402$Q_TCCONFIG -738197488 /* TC Configuration */N#define IO0402$Q_FADR -738197472 # /* Failing Address */N#define IO0402$Q_TCEREG -738197456 /* Turbochannel Error Register */N#define IO0402$Q_MCR0 -734003200 /* Memory Configuration 0 */N#define IO0402$Q_MCR1 -733872128 /* Memory Configuration 1 */N#define IO0402$Q_MCR2 -733741056 /* Memory Configuration 2 */N#define IO0402$Q_MCR3 -733609984 /* Memory Configuration 3 */N#define IO0402$Q_MCR4 -733478912 /* Memory Configur!#ation 4 */N#define IO0402$Q_MCR5 -733347840 /* Memory Configuration 5 */N#define IO0402$Q_MCR6 -733216768 /* Memory Configuration 6 */N#define IO0402$Q_MCR7 -733085696 /* Memory Configuration 7 */N#define IO0402$Q_IR -729808896 /* Interrupt Register */N#define IO0402$Q_IC -725614592 /* Interrupt Cause */N#define IO0402$Q_SG_MAP -721420288 /* Scatter/Gather */N#def"#ine IO0402$Q_TCRESET -717225984 /* Turbochannel Reset */[#define IO0402$Q_FLASH_EEPROM -268435456 /* CORE I/O ASIC registers - system ROM, part 2 */N#define IO0402$Q_IOCTL_CSR -267911168 /* CORE I/O base CSR address */N#define IO0402$Q_LDP -267911104 /* Ethernet DMA pointer */U#define IO0402$Q_SCOMM_TR -267911072 /* Serial comm transmit port 1 DMA pointer */T#define IO0402$Q_SCOMM_RC -267911040 /* Serial comm receive port 1 DMA pointer */U#d##efine IO0402$Q_PRINTER_TR -267911008 /* Serial comm transmit port 2 DMA pointer */T#define IO0402$Q_PRINTER_RC -267910976 /* Serial comm receive port 2 DMA pointer */N#define IO0402$Q_ISDN_TR -267910912 /* ISDN transmit DMA pointer */N#define IO0402$Q_ISDN_TR_BUF -267910880 /* ISDN transmit DMA buffer pointer */N#define IO0402$Q_ISDN_RC -267910848 /* ISDN receive DMA pointer */N#define IO0402$Q_ISDN_RC_BUF -267910816 /* ISDN receive DMA buffer pointer */N#define IO0402$#$Q_DATA0 -267910784 /* System Data Buffer 0 */N#define IO0402$Q_DATA1 -267910752 /* System Data Buffer 1 */N#define IO0402$Q_DATA2 -267910720 /* System Data Buffer 2 */N#define IO0402$Q_DATA3 -267910688 /* System Data Buffer 3 */N#define IO0402$Q_SSR -267910656 /* System support register */N#define IO0402$Q_SIR -267910624 /* System interrupt register */N#define IO0402$Q_SIMR -267910592 %#/* System interrupt mask register */N#define IO0402$Q_SADR -267910560 /* System address register */N#define IO0402$Q_ISDN_DATA_TR -267910528 /* ISDN Data Transmit */N#define IO0402$Q_ISDN_DATA_RC -267910496 /* ISDN Data Receive */N#define IO0402$Q_LANCE_SLOT -267910464 /* Lance slot register */N#define IO0402$Q_SCC0_SLOT -267910400 /* SCC1 slot register */N#define IO0402$Q_SCC1_SLOT -267910368 /* SCC0 slot register &# */N#define IO0402$Q_NI_ADR_ROM -267386880 /* Ethernet address ROM */N#define IO0402$Q_LANCE_RDP -266862592 /* Lance ethernet CSR */N#define IO0402$Q_LANCE_RAP -266862584 /* Lance ethernet CSR */N#define IO0402$Q_SCC0B_COMM_RAP -266338304 /* Comm Port 1 RAP */N#define IO0402$Q_SCC0B_COMM_DATA -266338296 /* Comm Port 1 data */N#define IO0402$Q_SCC0A_MOUSE_RAP -266338288 /* Mouse RAP */N#define IO04'#02$Q_SCC0A_MOUSE_DATA -266338280 /* Mouse port data register */N#define IO0402$Q_SCC1B_PRINTER_RAP -265289728 /* Comm Port 2 RAP */N#define IO0402$Q_SCC1B_PRINTER_DATA -265289720 /* Comm Port 2 data */N#define IO0402$Q_SCC1A_KEY_RAP -265289712 /* Keyboard RAP */N#define IO0402$Q_SCC1A_KEY_DATA -265289704 /* Keyboard port data register */N#define IO0402$Q_RTC_SEC -264241152 /* TOY clock CSR--seconds */N#define IO0402$Q_RTC_ALMS -264241144 (# /* TOY clock CSR--seconds alarm */N#define IO0402$Q_RTC_MIN -264241136 /* TOY clock CSR--minutes */N#define IO0402$Q_RTC_ALMN -264241128 /* TOY clock CSR--minutes alarm */N#define IO0402$Q_RTC_HOUR -264241120 /* TOY clock CSR--hours */N#define IO0402$Q_RTC_ALMH -264241112 /* TOY clock CSR--hours alarm */N#define IO0402$Q_RTC_DOW -264241104 /* TOY clock CSR--day of week */N#define IO0402$Q_RTC_DAY -264241096 /* TOY clock CSR--date o)#f month */N#define IO0402$Q_RTC_MON -264241088 /* TOY clock CSR--month */N#define IO0402$Q_RTC_YEAR -264241080 /* TOY clock CSR--year */N#define IO0402$Q_RTC_REGA -264241072 /* TOY clock CSR--register A */N#define IO0402$Q_RTC_REGB -264241064 /* TOY clock CSR--register B */N#define IO0402$Q_RTC_REGC -264241056 /* TOY clock CSR--register C */N#define IO0402$Q_RTC_REGD -264241048 /* TOY clock CSR--register D */N#define IO *#0402$Q_RTC_RAM -264241040 /* TOY clock CSR--base of BBU RAM */N#define IO0402$Q_ISDN_AUDIO -263716864 /* ISDN audio chip CSR */N#define IO0402$Q_SYSTEM_EEPROM -201326592 /* base of system ROM, part 1 */##define IO0402$Q_CPYBUF0 -199229440##define IO0402$Q_CPYBUF1 -199229432##define IO0402$Q_CPYBUF2 -199229424##define IO0402$Q_CPYBUF3 -199229416##define IO0402$Q_CPYBUF4 -199229408##define IO0402$Q_CPYBUF5 -199229400##define IO0402$Q_CPYBUF6 -199229392##define IO+#0402$Q_CPYBUF7 -199229384#define IO0402$Q_FG -199229376#define IO0402$Q_BG -199229368%#define IO0402$Q_PLANEMASK -199229360##define IO0402$Q_PIXMASK -199229352 #define IO0402$Q_MODE -199229344"#define IO0402$Q_BOOLOP -199229336$#define IO0402$Q_PIXSHIFT -199229328$#define IO0402$Q_ADDR_REG -199229320!#define IO0402$Q_BRES1 -199229312!#define IO0402$Q_BRES2 -199229304!#define IO0402$Q_BRES3 -199229296!#define IO0402$Q_BCONT -199229288 #define IO0402$Q_DEEP -199229280!#define IO04,#02$Q_START -199229272#define IO0402$Q_CI -199229264'#define IO0402$Q_V_REF_COUNT -199229248!#define IO0402$Q_V_HOR -199229240!#define IO0402$Q_V_VER -199229232#define IO0402$Q_VV -199229216#define IO0402$Q_EI -199229208'#define IO0402$Q_TCCLK_COUNT -199229200(#define IO0402$Q_VIDCLK_COUNT -199229192*#define IO0402$Q_RAMDAC_ADDR_LO -197656576*#define IO0402$Q_RAMDAC_ADDR_HI -197656568+#define IO0402$Q_RAMDAC_REG_ADDR -197656560*#define IO0402$Q_RAMDAC_MAP_LOC -197656552#define IO -#0402$Q_FB -501219328##define IO0402$Q_SLOT0_DENSE_BASE 0+#define IO0402$Q_SLOT1_DENSE_BASE 536870912,#define IO0402$Q_SLOT2_DENSE_BASE 1073741824,#define IO0402$Q_SLOT3_DENSE_BASE 1610612736-#define IO0402$Q_SLOT4_DENSE_BASE -2147483648-#define IO0402$Q_SLOT5_DENSE_BASE -1610612736-#define IO0402$Q_SLOT6_DENSE_BASE -1073741824,#define IO0402$Q_SLOT7_DENSE_BASE -536870912.#define IO0402$Q_CXTURBO_DENSE_BASE -503316480,#define IO0402$Q_SLOT0_SPARSE_BASE 268435456,#define IO0402$Q_SLOT1_S .#PARSE_BASE 805306368-#define IO0402$Q_SLOT2_SPARSE_BASE 1342177280-#define IO0402$Q_SLOT3_SPARSE_BASE 1879048192.#define IO0402$Q_SLOT4_SPARSE_BASE -1879048192.#define IO0402$Q_SLOT5_SPARSE_BASE -1342177280-#define IO0402$Q_SLOT6_SPARSE_BASE -805306368-#define IO0402$Q_SLOT7_SPARSE_BASE -268435456N#define IO0402$Q_LDP_DENSE -536608736 /* Ethernet DMA pointer */N#define IO0402$Q_NI_ADR_ROM_DENSE -536346624 /* Ethernet address ROM */N#define IO0402$Q_LANCE_RDP_DENSE -53/#6084480 /* Lance ethernet CSR */N#define IO0402$Q_IMASK_READ -1035993088 /* IR dense space */Q#define IO0402$Q_SG_DENSE -1031675904 /* Base of last page of SG dense space */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #end 0#if /* __IO0402DEF_LOADED */ wwC[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. 1# **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. 2#**/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */I/* Source: 04-FEB-1993 14:36:01 $1$DGA8345:[LIB_H.SRC]IO0602DEF 3#.SDL;1 *//********************************************************************************************************************************//*** MODULE $IO0602DEF ***/#ifndef __IO0602DEF_LOADED#define __IO0602DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Sa4#ve the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#defin5#e __union union#else#define __union variant_union#endif#endif #define IO0602$K_EISA_LOCAL 1#define IO0602$K_EISA_MEM 2#define IO0602$K_EISA_IO 3"#define IO0602$Q_EISA_INTA_CYCLE 0S#define IO0602$Q_EISA_COMBO_CHIP -1073741824 /* base address of COMBO ADDR space */\#define IO0602$Q_EISA_COMBO_CHIP_RTC -1073553408 /* base address of COMBO ADDR space, RTC */N#define IO0602$B_KBD_PS2 -1073696768 /* PS2 keyboard register, read */N#define IO0602$B_KBD_DBB -1073696768 /*6# PS2 keyboard register, write */N#define IO0602$B_KBD_PS2S -1073694720 /* PS2 status register */Z#define IO0602$B_TOY_R_INDX_REG -1073684480 /* address of index register for read addr. */Y#define IO0602$B_TOY_R_DATA_REG -1073683968 /* address of data register for read data. */[#define IO0602$B_TOY_W_INDX_REG -1073553408 /* address of index register for write addr. */Z#define IO0602$B_TOY_W_DATA_REG -1073552896 /* address of data register for write data. */N#define IO0602$K_T7#OY_SECS 0 /* seconds of TOY clock. */O#define IO0602$K_TOY_ASECS 1 /* seconds of TOY clock, alarm func. */N#define IO0602$K_TOY_MINS 2 /* minutes of TOY clock. */O#define IO0602$K_TOY_AMINS 3 /* minutes of TOY clock, alarm func. */N#define IO0602$K_TOY_HOURS 4 /* hours of TOY clock. */N#define IO0602$K_TOY_AHOURS 5 /* hours of TOY clock, alarm func. */N#define IO0602$K_TOY_DAY 6 8#/* day of week, 1-7 */N#define IO0602$K_TOY_DATE 7 /* date of month */N#define IO0602$K_TOY_MONTH 8 /* month */N#define IO0602$K_TOY_YEAR 9 /* year */N#define IO0602$K_TOY_CNTRLA 10 /* control register A */N#define IO0602$K_TOY_CNTRLB 11 /* control register B */N#define IO0602$K_TOY_CNTRLC 12 /* control register C 9# */N#define IO0602$K_TOY_CNTRLD 13 /* control register D */N#define IO0602$B_COMB_RBR -1073352704 /* Recieve Buffer Register */N#define IO0602$B_COMB_THR -1073352704 /* Transmitter Holding Register */N#define IO0602$B_COMB_DLL -1073352704 /* Divisor Latch Register(LSB) */N#define IO0602$B_COMB_DLM -1073352192 /* Divisor Latch Register(MSB) */N#define IO0602$B_COMB_IER -1073352192 /* Interrupt Enable Register */N#define IO06:#02$B_COMB_FCR -1073351680 /* */O#define IO0602$B_COMB_IIR -1073351680 /* Interrupt Identification Register */N#define IO0602$B_COMB_LCR -1073351168 /* Line Control Register */N#define IO0602$B_COMB_MCR -1073350656 /* Modem Control Register */N#define IO0602$B_COMB_LSR -1073350144 /* Line Status Register */N#define IO0602$B_COMB_MSR -1073349632 /* Modem Status Register */N#define IO0602$B_COMB_SCR -107334912;#0 /* Scratch Register */N#define IO0602$B_LPT_REG0 -1073252352 /* Data Register */N#define IO0602$B_LPT_REG1 -1073251840 /* Status Register */N#define IO0602$B_LPT_REG2 -1073251328 /* Control Register */N#define IO0602$B_COMA_RBR -1073221632 /* Recieve Buffer Register */N#define IO0602$B_COMA_THR -1073221632 /* Transmitter Holding Register */N#define IO0602$B_COMA_DLL -1073221632 /* Divisor Latch Regis<#ter(LSB) */N#define IO0602$B_COMA_DLM -1073221120 /* Divisor Latch Register(MSB) */N#define IO0602$B_COMA_IER -1073221120 /* Interrupt Enable Register */N#define IO0602$B_COMA_FCR -1073220608 /* */O#define IO0602$B_COMA_IIR -1073220608 /* Interrupt Identification Register */N#define IO0602$B_COMA_LCR -1073220096 /* Line Control Register */N#define IO0602$B_COMA_MCR -1073219584 /* Modem Control Register */N#defin =#e IO0602$B_COMA_LSR -1073219072 /* Line Status Register */N#define IO0602$B_COMA_MSR -1073218560 /* Modem Status Register */N#define IO0602$B_COMA_SCR -1073218048 /* Scratch Register */-#define IO0602$Q_EISA_CONFIG_DATA -1409286144'#define IO0602$Q_EISA_CONFIG_IRQ 107520'#define IO0602$Q_EISA_CONFIG_DMA 114688&#define IO0602$Q_EISA_CONFIG_MEM 76288+#define IO0602$Q_EISA_CONFIG_IO_PORT 102912)#define IO0602$Q_HOST_ADDR_EXT -805306368)#define IO >#0602$Q_SYS_CNTRL_REG -536870912%#define IO0602$Q_SPARE_REG -268435456 #define IO0602$Q_EISA_MEM_BASE 0#define IO0602$Q_EISA_IO_BASE 0N#define IO0602$Q_EISA_IO_ISP 0 /* base addr of ISP chip(82357) */Z#define IO0602$B_DMA1_CH0_ADDR 0 /* 0 addr of DMA1 CH-0 Base and Current Address */Z#define IO0602$B_DMA1_CH0_CNT 128 /* 1 addr of DMA1 CH-0 Base and Current Address */Z#define IO0602$B_DMA1_CH1_ADDR 256 /* 2 addr of DMA1 CH-1 Base and Current Address */Z#define ?#IO0602$B_DMA1_CH1_CNT 384 /* 3 addr of DMA1 CH-1 Base and Current Address */Z#define IO0602$B_DMA1_CH2_ADDR 512 /* 4 addr of DMA1 CH-2 Base and Current Address */Z#define IO0602$B_DMA1_CH2_CNT 640 /* 5 addr of DMA1 CH-2 Base and Current Address */Z#define IO0602$B_DMA1_CH3_ADDR 768 /* 6 addr of DMA1 CH-3 Base and Current Address */Z#define IO0602$B_DMA1_CH3_CNT 896 /* 7 addr of DMA1 CH-3 Base and Current Address */N#define IO0602$B_DMA1_STATUS 1024 /* 8 addr of D@#MA1 status */N#define IO0602$B_DMA1_WR_REQ 1152 /* 9 addr of DMA1 write request */R#define IO0602$B_DMA1_WR_MASK 1280 /* A addr of DMA1 write single mask bit */P#define IO0602$B_DMA1_WR_MODE 1408 /* B addr of DMA1 write mode register */O#define IO0602$B_DMA1_CL_BYTE 1536 /* C addr of DMA1 clear byte pointer */N#define IO0602$B_DMA1_MASTER_CLR 1664 /* D addr of DMA1 master clear */N#define IO0602$B_DMA1_CLR_MASK 1792 /* E addr of DMA1 clear mask regA# */Y#define IO0602$B_DMA1_RW_MASK_REG 1920 /* F addr of DMA1 read/write all mask reg bits */N#define IO0602$B_INT_1_CNTRL 4096 /* 20 INT1 control register */N#define IO0602$B_INT_1_MASK 4224 /* 21 INT1 mask register */N#define IO0602$B_INTV_TIMER1 8192 /* 40 Interval Timer 1 */N#define IO0602$B_REF_REQ 8320 /* 41 Refresh Request Register */N#define IO0602$B_SKR_TONE 8448 /* 42 Speaker Tone Register */N#definB#e IO0602$B_CMD_MODE 8576 /* 43 Command Mode Register */N#define IO0602$B_INTV_TIMER2 9216 /* 48 Interval Timer 2 */N#define IO0602$B_SPD_CNTRL 9472 /* 4A CPU Speed Control */N#define IO0602$B_CMD_MODE2 9600 /* 4B Command Mode Register */N#define IO0602$B_NMI_STATUS 12416 /* 61 NMI Status */N#define IO0602$B_NMI_ENABLE 14336 /* 70 NMI Enable Register */N#define IO0602$B_DMA_PAGE_R1 163C#84 /* 80 DMA PAGE Register(reserved) */N#define IO0602$B_DMA_PAGE_CH2 16512 /* 81 DMA PAGE Register CH 2 */N#define IO0602$B_DMA_PAGE_CH3 16640 /* 82 DMA PAGE Register Ch 3 */N#define IO0602$B_DMA_PAGE_CH1 16768 /* 83 DMA PAGE Register Ch 1 */N#define IO0602$B_DMA_PAGE_R2 16896 /* 84 DMA PAGE Register(reserved) */N#define IO0602$B_DMA_PAGE_R3 17024 /* 85 DMA PAGE Register(reserved) */N#define IO0602$B_DMA_PAGE_R4 17152 /* 86 DMA PAGE RegD#ister(reserved) */N#define IO0602$B_DMA_PAGE_CH0 17280 /* 87 DMA PAGE Register CH 0 */N#define IO0602$B_DMA_PAGE_R5 17408 /* 88 DMA PAGE Register(reserved) */N#define IO0602$B_DMA_PAGE_CH6 17536 /* 89 DMA PAGE Register CH 6 */N#define IO0602$B_DMA_PAGE_CH7 17664 /* 8A DMA PAGE Register CH 7 */N#define IO0602$B_DMA_PAGE_CH5 17792 /* 8B DMA PAGE Register CH 5 */N#define IO0602$B_DMA_PAGE_R6 17920 /* 8C DMA PAGE Register(reserved) */N#defE#ine IO0602$B_DMA_PAGE_R7 18048 /* 8D DMA PAGE Register(reserved) */N#define IO0602$B_DMA_PAGE_R8 18176 /* 8E DMA PAGE Register(reserved) */O#define IO0602$B_DMA_PAGE_REF 18304 /* 8F DMA PAGE Register Refresh Page */N#define IO0602$B_INT2_CNTRL 20480 /* A0 INT-2 control register */N#define IO0602$B_INT2_MASK 20608 /* A1 INT-2 mask register */[#define IO0602$B_DMA2_CH0_ADDR 24576 /* C0 addr of DMA2 CH-0 Base and Current Address */[#define IO0602F#$B_DMA2_CH0_CNT 24832 /* C2 addr of DMA2 CH-0 Base and Current Address */[#define IO0602$B_DMA2_CH1_ADDR 25088 /* C4 addr of DMA2 CH-1 Base and Current Address */[#define IO0602$B_DMA2_CH1_CNT 25344 /* C6 addr of DMA2 CH-1 Base and Current Address */[#define IO0602$B_DMA2_CH2_ADDR 25600 /* C8 addr of DMA2 CH-2 Base and Current Address */[#define IO0602$B_DMA2_CH2_CNT 25856 /* CA addr of DMA2 CH-2 Base and Current Address */[#define IO0602$B_DMA2_CH3_ADDR 26112 /* CC addrG# of DMA2 CH-3 Base and Current Address */[#define IO0602$B_DMA2_CH3_CNT 26368 /* CE addr of DMA2 CH-3 Base and Current Address */N#define IO0602$B_DMA2_STATUS 26624 /* D0 addr of DMA2 status */N#define IO0602$B_DMA2_WR_REQ 26880 /* D2 addr of DMA2 write request */S#define IO0602$B_DMA2_WR_MASK 27136 /* D4 addr of DMA2 write single mask bit */Q#define IO0602$B_DMA2_WR_MODE 27392 /* D6 addr of DMA2 write mode register */P#define IO0602$B_DMA2_CL_BYTE 27648 H# /* D8 addr of DMA2 clear byte pointer */N#define IO0602$B_DMA2_MASTER_CLR 27904 /* DA addr of DMA2 master clear */N#define IO0602$B_DMA2_CLR_MASK 28160 /* DC addr of DMA2 clear mask reg */Z#define IO0602$B_DMA2_RW_MASK_REG 28416 /* DE addr of DMA2 read/write all mask reg bits */T#define IO0602$B_DMA1_CH0_CNT_HIGH 131200 /* 401 DMA1 Ch0 base/current count high */T#define IO0602$B_DMA1_CH1_CNT_HIGH 131456 /* 403 DMA1 Ch1 base/current count high */T#define IO0602$B_DMA1_CH2_CNT_HIGH 131I#712 /* 405 DMA1 Ch2 base/current count high */T#define IO0602$B_DMA1_CH3_CNT_HIGH 131968 /* 407 DMA1 Ch3 base/current count high */[#define IO0602$B_DMA1_CHN_MODE 132352 /* 40A DMA1 Set Chaining Mode(w), Int status (r) */N#define IO0602$B_DMA1_WRT_MODE 132480 /* 40B DMA1 Ext Write Mode Reg */N#define IO0602$B_DMA1_CHN_BUF_CNTRL 132608 /* 40C DMA1 Chain Buf Control */N#define IO0602$B_DMA1_STEP_LVL 132736 /* 40D DMA1 Stepping LEvel Reg */P#define IO0602$B_EXNMI_CNTRL 143488 J# /* 461 Extended NMI and reset control */N#define IO0602$B_NMI_IO_INT_PORT 143616 /* 462 NMI IO Int Port(casual) */N#define IO0602$B_LAST_BUS_MSTR 143872 /* 464 LAst Bus MAster Granted */U#define IO0602$B_DMA_CH2_HIGH_PAGE 147584 /* 481 DMA High Page Resgister CH-2 PAge */U#define IO0602$B_DMA_CH3_HIGH_PAGE 147712 /* 482 DMA High Page Resgister CH-3 PAge */U#define IO0602$B_DMA_CH1_HIGH_PAGE 147840 /* 483 DMA High Page Resgister CH-1 PAge */U#define IO0602$B_DMA_CH0_HIGH_PAGE 148K#352 /* 487 DMA High Page Resgister CH-0 PAge */U#define IO0602$B_DMA_CH6_HIGH_PAGE 148608 /* 489 DMA High Page Resgister CH-6 PAge */U#define IO0602$B_DMA_CH7_HIGH_PAGE 148736 /* 48A DMA High Page Resgister CH-7 PAge */U#define IO0602$B_DMA_CH5_HIGH_PAGE 148864 /* 48B DMA High Page Resgister CH-5 PAge */Q#define IO0602$B_DMA_REG_REFRESH 149376 /* 48F DMA High Page Resgister Refresh */U#define IO0602$B_DMA2_CH5_CNT_HIGH 156416 /* 4C6 DMA2 Ch 5 base/current count high */U#define IO0602$B_DMAL#2_CH6_CNT_HIGH 156928 /* 4CA DMA2 Ch 6 base/current count high */U#define IO0602$B_DMA2_CH7_CNT_HIGH 157440 /* 4CE DMA2 Ch 7 base/current count high */N#define IO0602$B_INT1_LVL_CTRL 157696 /* 4D0 INT-1 Edge LEvel Control Reg */N#define IO0602$B_INT2_LVL_CTRL 157824 /* 4D1 INT-2 Edge LEvel Control Reg */N#define IO0602$B_DMA2_CHN_MODE 158208 /* 4D4 DMA2 Set chaining mode */N#define IO0602$B_DMA2_EXT_WRT_MODE 158464 /* 4D6 DMA2 Ext Write Mode Reg */N#define IO0602$B_DMA_CH0_STOP_M#7_2 159744 /* 4E0 DMA CH0 Stop Reg Bits<7:2> */O#define IO0602$B_DMA_CH0_STOP_15_8 159872 /* 4E1 DMA CH0 Stop Reg Bits<15:8> */Q#define IO0602$B_DMA_CH0_STOP_23_16 160000 /* 4E2 DMA CH0 Stop Reg Bits<23:16> */N#define IO0602$B_DMA_CH1_STOP_7_2 160256 /* 4E4 DMA CH1 Stop Reg Bits<7:2> */O#define IO0602$B_DMA_CH1_STOP_15_8 160384 /* 4E5 DMA CH1 Stop Reg Bits<15:8> */Q#define IO0602$B_DMA_CH1_STOP_23_16 160512 /* 4E6 DMA CH1 Stop Reg Bits<23:16> */N#define IO0602$B_DMA_CH2_STOP_7_2 160768 /* N#4E8 DMA CH2 Stop Reg Bits<7:2> */O#define IO0602$B_DMA_CH2_STOP_15_8 160896 /* 4E9 DMA CH2 Stop Reg Bits<15:8> */Q#define IO0602$B_DMA_CH2_STOP_23_16 161024 /* 4EA DMA CH2 Stop Reg Bits<23:16> */N#define IO0602$B_DMA_CH3_STOP_7_2 161280 /* 4EC DMA CH3 Stop Reg Bits<7:2> */O#define IO0602$B_DMA_CH3_STOP_15_8 161408 /* 4ED DMA CH3 Stop Reg Bits<15:8> */Q#define IO0602$B_DMA_CH3_STOP_23_16 161536 /* 4EE DMA CH3 Stop Reg Bits<23:16> */N#define IO0602$B_DMA_CH5_STOP_7_2 162304 /* 4F4 DMA CH5 StO#op Reg Bits<7:2> */O#define IO0602$B_DMA_CH5_STOP_15_8 162432 /* 4F5 DMA CH5 Stop Reg Bits<15:8> */Q#define IO0602$B_DMA_CH5_STOP_23_16 162560 /* 4F6 DMA CH5 Stop Reg Bits<23:16> */N#define IO0602$B_DMA_CH6_STOP_7_2 162816 /* 4F8 DMA CH6 Stop Reg Bits<7:2> */O#define IO0602$B_DMA_CH6_STOP_15_8 162944 /* 4F9 DMA CH6 Stop Reg Bits<15:8> */Q#define IO0602$B_DMA_CH6_STOP_23_16 163072 /* 4FA DMA CH6 Stop Reg Bits<23:16> */N#define IO0602$B_DMA_CH7_STOP_7_2 163328 /* 4FC DMA CH7 Stop Reg Bits<7:P#2> */O#define IO0602$B_DMA_CH7_STOP_15_8 163456 /* 4FD DMA CH7 Stop Reg Bits<15:8> */Q#define IO0602$B_DMA_CH7_STOP_23_16 163584 /* 4FE DMA CH7 Stop Reg Bits<23:16> */N#define IO0602$Q_EISA_SLOT1_BASE 524288 /* 1000 */N#define IO0602$Q_EISA_SLOT2_BASE 1048576 /* 2000 */N#define IO0602$Q_EISA_SLOT3_BASE 1572864 /* 3000 */N#define IO0602$Q_EISA_SLOT4_BASE 2097152 /* 4000 */N#define IO06Q#02$Q_EISA_SLOT5_BASE 2621440 /* 5000 */N#define IO0602$Q_EISA_SLOT6_BASE 3145728 /* 6000 */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IO0602DEF_LOADED */ wwD[UM/*R#**************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright HewlettS#-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. T# **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */I/* Source: 24-JUN-1992 16:22:38 $1$DGA8345:[LIB_H.SRC]IO0702DEF.SDL;1 *//*********************************************** U#*********************************************************************************//*** MODULE $IO0702DEF ***/#ifndef __IO0702DEF_LOADED#define __IO0702DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __reV#quired_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#e W#ndif#endif N#define IO0702$Q_TC_NUMBER 1 /* Turbochannel number. */N/* Upper lw of physical */N/* address */N#define IO0702$Q_SCSI_CIR -1878523904 /* SCSI Control Interrupts */N#define IO0702$Q_SCSI_IMER -1878523896 /* SCSI Interrupt Mask Enable */N#define IO0702$Q_SCSI0_SDA -1878515712 /* SCSI DMA Address */N#define X#IO0702$Q_SCSI0_SDIC -1878515704 /* SCSI DMA Interrupt Control */N#define IO0702$Q_SCSI0_DMA_UNAL0 -1878515696 /* SCSI DMA Unaligned Data 0 */N#define IO0702$Q_SCSI0_DMA_UNAL1 -1878515688 /* SCSI DMA Unaligned Data 1 */N#define IO0702$Q_SCSI0_TC_LSB -1877999616 /* SCSI Transfer Counter LSB */N#define IO0702$Q_SCSI0_TC_MSB -1877999608 /* SCSI Transfer Counter MSB */N#define IO0702$Q_SCSI0_FIFO -1877999600 /* SCSI FIFO */N#define IO0702$Q_SCSI0_CMD -187799Y#9592 /* SCSI Command */N#define IO0702$Q_SCSI0_STATUS -1877999584 /* SCSI Status */N#define IO0702$Q_SCSI0_INTR -1877999576 /* SCSI Interrupt/Timeout */N#define IO0702$Q_SCSI0_SEQ -1877999568 /* SCSI Sequence Step */N#define IO0702$Q_SCSI0_FF -1877999560 /* SCSI FIFO Flags */N#define IO0702$Q_SCSI0_CONFIG1 -1877999552 /* SCSI Configuration 1 */N#define IO0702$Q_SCSI0_CC -1877999544 /* SCSI reserved/CloZ#ck Conversion */N#define IO0702$Q_SCSI0_TM -1877999536 /* SCSI reserved/Test Mode */N#define IO0702$Q_SCSI0_CONFIG2 -1877999528 /* SCSI Configuration 2 */N#define IO0702$Q_SCSI0_CONFIG3 -1877999520 /* SCSI Configuration 3 */N#define IO0702$Q_SCSI0_DMA -1877475328 /* SCSI DMA Buffer */N#define IO0702$Q_IR -268435456 /* Interrupt Register */N#define IO0702$Q_TCSR -268435440 /* TC Control & Status Register */N#defin[#e IO0702$Q_MCR -268435424 /* Memory Config Register */\#define IO0702$Q_FLASH_EEPROM -1342177280 /* CORE I/O ASIC registers - system ROM, part 2 */N#define IO0702$Q_IOCTL_CSR -1341652992 /* CORE I/O base CSR address */N#define IO0702$Q_LDP -1341652928 /* Ethernet DMA pointer */U#define IO0702$Q_SCOMM_TR -1341652896 /* Serial comm transmit port 1 DMA pointer */T#define IO0702$Q_SCOMM_RC -1341652864 /* Serial comm receive port 1 DMA pointer */U#def\#ine IO0702$Q_PRINTER_TR -1341652832 /* Serial comm transmit port 2 DMA pointer */T#define IO0702$Q_PRINTER_RC -1341652800 /* Serial comm receive port 2 DMA pointer */N#define IO0702$Q_ISDN_TR -1341652736 /* ISDN transmit DMA pointer */O#define IO0702$Q_ISDN_TR_BUF -1341652704 /* ISDN transmit DMA buffer pointer */N#define IO0702$Q_ISDN_RC -1341652672 /* ISDN receive DMA pointer */O#define IO0702$Q_ISDN_RC_BUF -1341652640 /* ISDN receive DMA buffer pointer */N#define IO07]#02$Q_DATA0 -1341652608 /* System Data Buffer 0 */N#define IO0702$Q_DATA1 -1341652576 /* System Data Buffer 1 */N#define IO0702$Q_DATA2 -1341652544 /* System Data Buffer 2 */N#define IO0702$Q_DATA3 -1341652512 /* System Data Buffer 3 */N#define IO0702$Q_SSR -1341652480 /* System support register */N#define IO0702$Q_SIR -1341652448 /* System interrupt register */N#define IO0702$Q_SIMR -1341652416 ^# /* System interrupt mask register */N#define IO0702$Q_SADR -1341652384 /* System address register */N#define IO0702$Q_ISDN_DATA_TR -1341652352 /* ISDN Data Transmit */N#define IO0702$Q_ISDN_DATA_RC -1341652320 /* ISDN Data Receive */N#define IO0702$Q_LANCE_SLOT -1341652288 /* Lance slot register */N#define IO0702$Q_SCC0_SLOT -1341652224 /* SCC1 slot register */N#define IO0702$Q_SCC1_SLOT -1341652192 /* SCC0 slot register _# */N#define IO0702$Q_NI_ADR_ROM -1341128704 /* Ethernet address ROM */N#define IO0702$Q_LANCE_RDP -1340604416 /* Lance ethernet CSR */N#define IO0702$Q_LANCE_RAP -1340604408 /* Lance ethernet CSR */N#define IO0702$Q_SCC0B_COMM_RAP -1340080128 /* Comm Port 1 RAP */N#define IO0702$Q_SCC0B_COMM_DATA -1340080120 /* Comm Port 1 data */N#define IO0702$Q_SCC0A_MOUSE_RAP -1340080112 /* Mouse RAP */N#define IO`#0702$Q_SCC0A_MOUSE_DATA -1340080104 /* Mouse port data register */N#define IO0702$Q_SCC1B_PRINTER_RAP -1339031552 /* Comm Port 2 RAP */N#define IO0702$Q_SCC1B_PRINTER_DATA -1339031544 /* Comm Port 2 data */N#define IO0702$Q_SCC1A_KEY_RAP -1339031536 /* Keyboard RAP */N#define IO0702$Q_SCC1A_KEY_DATA -1339031528 /* Keyboard port data register */N#define IO0702$Q_RTC_SEC -1337982976 /* TOY clock CSR--seconds */N#define IO0702$Q_RTC_ALMS -133798296a#8 /* TOY clock CSR--seconds alarm */N#define IO0702$Q_RTC_MIN -1337982960 /* TOY clock CSR--minutes */N#define IO0702$Q_RTC_ALMN -1337982952 /* TOY clock CSR--minutes alarm */N#define IO0702$Q_RTC_HOUR -1337982944 /* TOY clock CSR--hours */N#define IO0702$Q_RTC_ALMH -1337982936 /* TOY clock CSR--hours alarm */N#define IO0702$Q_RTC_DOW -1337982928 /* TOY clock CSR--day of week */N#define IO0702$Q_RTC_DAY -1337982920 /* TOY clock CSR--dateb# of month */N#define IO0702$Q_RTC_MON -1337982912 /* TOY clock CSR--month */N#define IO0702$Q_RTC_YEAR -1337982904 /* TOY clock CSR--year */N#define IO0702$Q_RTC_REGA -1337982896 /* TOY clock CSR--register A */N#define IO0702$Q_RTC_REGB -1337982888 /* TOY clock CSR--register B */N#define IO0702$Q_RTC_REGC -1337982880 /* TOY clock CSR--register C */N#define IO0702$Q_RTC_REGD -1337982872 /* TOY clock CSR--register D */N#define c#IO0702$Q_RTC_RAM -1337982864 /* TOY clock CSR--base of BBU RAM */N#define IO0702$Q_ISDN_AUDIO -1337458688 /* ISDN audio chip CSR */N#define IO0702$Q_SYSTEM_EEPROM -1073741824 /* base of system ROM, part 1 */$#define IO0702$Q_CPYBUF0 -1072693248$#define IO0702$Q_CPYBUF1 -1072693244$#define IO0702$Q_CPYBUF2 -1072693240$#define IO0702$Q_CPYBUF3 -1072693236$#define IO0702$Q_CPYBUF4 -1072693232$#define IO0702$Q_CPYBUF5 -1072693228$#define IO0702$Q_CPYBUF6 -1072693224$#define d#IO0702$Q_CPYBUF7 -1072693220#define IO0702$Q_FG -1072693216#define IO0702$Q_BG -1072693212&#define IO0702$Q_PLANEMASK -1072693208$#define IO0702$Q_PIXMASK -1072693204!#define IO0702$Q_MODE -1072693200##define IO0702$Q_BOOLOP -1072693196%#define IO0702$Q_PIXSHIFT -1072693192%#define IO0702$Q_ADDR_REG -1072693188"#define IO0702$Q_BRES1 -1072693184"#define IO0702$Q_BRES2 -1072693180"#define IO0702$Q_BRES3 -1072693176"#define IO0702$Q_BCONT -1072693172!#define IO0702$Q_DEEP -107269316e#8"#define IO0702$Q_START -1072693164#define IO0702$Q_CI -1072693160(#define IO0702$Q_V_REF_COUNT -1072693152"#define IO0702$Q_V_HOR -1072693148"#define IO0702$Q_V_VER -1072693144(#define IO0702$Q_V_BASE_ADDR -1072693140#define IO0702$Q_VV -1072693136#define IO0702$Q_EI -1072693132(#define IO0702$Q_TCCLK_COUNT -1072693128)#define IO0702$Q_VIDCLK_COUNT -1072693124+#define IO0702$Q_RAMDAC_ADDR_LO -1071906816+#define IO0702$Q_RAMDAC_ADDR_HI -1071906812,#define IO0702$Q_RAMDAC_REG_AD f#DR -1071906808+#define IO0702$Q_RAMDAC_MAP_LOC -1071906804#define IO0702$Q_FB -1071644672##define IO0702$Q_SLOT0_DENSE_BASE 0+#define IO0702$Q_SLOT1_DENSE_BASE 536870912-#define IO0702$Q_SLOT4_DENSE_BASE -2147483648-#define IO0702$Q_SLOT5_DENSE_BASE -1610612736-#define IO0702$Q_SLOT6_DENSE_BASE -1073741824,#define IO0702$Q_SLOT0_SPARSE_BASE 268435456,#define IO0702$Q_SLOT1_SPARSE_BASE 805306368.#define IO0702$Q_SLOT4_SPARSE_BASE -1879048192.#define IO0702$Q_SLOT5_SPARSE_BASE -134217 g#7280N#define IO0702$Q_LDP_DENSE -1610350560 /* Ethernet DMA pointer */N#define IO0702$Q_NI_ADR_ROM_DENSE -1610088448 /* Ethernet address ROM */N#define IO0702$Q_LANCE_RDP_DENSE -1609826304 /* Lance ethernet CSR */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus } h##endif#pragma __standard #endif /* __IO0702DEF_LOADED */ wwdD[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior i#written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of j#VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */I/* Source: 13-JUL-1993 14 k#:58:31 $1$DGA8345:[LIB_H.SRC]IO0802DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IO0802DEF ***/#ifndef __IO0802DEF_LOADED#define __IO0802DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma l#__required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef m#__union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define IO0802$Q_PCI_IO -2147483648 /* 1 8000 0000 */N/* One 8 KB page can map the following APC control registers */N#define IO0802$Q_APC_CONTROL -805306368 /* 1 D000 0000 */N#define IO0802$Q_APC_HAE -805306368 /* 1 D000 0000 */N#define IO0802$Q_APC_INTERVAL_TIMER -805306240 /* 1 D000 0080 n# */N#define IO0802$Q_APC_BUFFER_STATUS -805306176 /* 1 D000 00C0 */N#define IO0802$Q_APC_ERROR_STATUS -805306112 /* 1 D000 0100 */N#define IO0802$Q_APC_ERROR_MASK -805306048 /* 1 D000 0140 */N#define IO0802$Q_APC_LAST_PREFIX -805305984 /* 1 D000 0180 */N#define IO0802$Q_APC_LOCK_ADDRESS -805305920 /* 1 D000 01C0 */N#define IO0802$Q_APC_LOCAL_DEVICE_PORT -805305856 /* 1 D000 0200 */N#define IO0802$Qo#_APC_MISC_DATA0 -805305728 /* 1 D000 0280 */N#define IO0802$Q_APC_MISC_DATA1 -805305664 /* 1 D000 02C0 */N/* The prefix registers occupy 16 KB. Use 2 8 KB pages to map. */N#define IO0802$Q_APC_PREFIX -788529152 /* 1 d100 0000 */N/* One 8 KB page can map the APC configuration and diagnostic registers */N#define IO0802$Q_APC_CONFIG -536870912 /* 1 e000 0000 */N#define IO0802$Q_APC_CACHE_CONTROL -536870p#912 /* 1 e000 0000 */N#define IO0802$Q_APC_PCI_CONFIG -536870784 /* 1 e000 0080 */N#define IO0802$Q_APC_PCI_STATUS -536870720 /* 1 e000 00C0 */N#define IO0802$Q_APC_MEM_BANK_01 -536870656 /* 1 e000 0100 */N#define IO0802$Q_APC_MEM_BANK_23 -536870624 /* 1 e000 0120 */N#define IO0802$Q_APC_MEM_BANK_45 -536870592 /* 1 e000 0140 */N#define IO0802$Q_APC_MEM_BANK_67 -536870560 /* 1 e000 0160 q# */N#define IO0802$Q_APC_MEM_CONTROL -536870528 /* 1 e000 0180 */N#define IO0802$Q_APC_EXT_PC_HOLE -536870464 /* 1 e000 01C0 */N#define IO0802$Q_APC_EXT_PROG_HOLE -536870432 /* 1 e000 01E0 */N#define IO0802$Q_APC_DIAG_CONTROL -536870400 /* 1 e000 0200 */N#define IO0802$Q_APC_DIAG_DATA0 -536870272 /* 1 e000 0280 */N#define IO0802$Q_APC_DIAG_DATA1 -536870208 /* 1 e000 02C0 */N#define IO0802r#$Q_APC_REV_LEVEL -536870144 /* 1 e000 0300 */N#define IO0802$Q_APC_PARITY_CONTROL -536870080 /* 1 e000 0340 */N#define IO0802$Q_APC_SM_ADDRESS -536869888 /* 1 e000 0400 */N#define IO0802$Q_APC_SM_DATA -536869824 /* 1 e000 0440 */N#define IO0802$Q_PCI_SPARSE_MEM 0 /* 2 0000 0000 */N#define IO0802$Q_PCI_DENSE_MEM 0 /* 3 0000 0000 */ $#pragma __member_alignment __restores#R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IO0802DEF_LOADED */ wwD[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This soft#tware is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is cou#nfidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//* v#*******************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 26-JUN-1995 11:08:59 $1$DGA8345:[LIB_H.SRC]IO0902DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IO0902DEF ***/#ifndef __IO0902DEF_LOADED#define __IO0902DEF_LOADED 1 G#pragma __no w#standard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params x#...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif &#define IO0902$Q_CPU0_PA_L -2147483648#define IO0902$Q_CPU0_PA_H 131&#define IO0902$Q_CPU1_PA_L -2130706432#define IO0902$Q_CPU1_PA_H 131&#define IO0902$Q_CPU2_PA_Ly# -2113929216#define IO0902$Q_CPU2_PA_H 131&#define IO0902$Q_CPU3_PA_L -2097152000#define IO0902$Q_CPU3_PA_H 131&#define IO0902$Q_SMM0_PA_L -2013265920#define IO0902$Q_SMM0_PA_H 131&#define IO0902$Q_SMM1_PA_L -1996488704#define IO0902$Q_SMM1_PA_H 131&#define IO0902$Q_SMM2_PA_L -1979711488#define IO0902$Q_SMM2_PA_H 131&#define IO0902$Q_SMM3_PA_L -1962934272#define IO0902$Q_SMM3_PA_H 131&#define IO0902$Q_T2IO_PA_L -1912602624#define IO0902$Q_T2IO_PA_H 131%#define IO0902$Q_EIO_PA_L -1z#895825408#define IO0902$Q_EIO_PA_H 131%#define IO0902$Q_IIC_PA_L -1610570240#define IO0902$Q_IIC_PA_H 131(#define IO0902$Q_DS1287_PA_L -1610609152 #define IO0902$Q_DS1287_PA_H 131)#define IO0902$Q_MASTER_ICR_L -1610570112!#define IO0902$Q_MASTER_ICR_H 131)#define IO0902$Q_SLAVE0_ICR_L -1610570048!#define IO0902$Q_SLAVE0_ICR_H 131)#define IO0902$Q_SLAVE1_ICR_L -1610569920!#define IO0902$Q_SLAVE1_ICR_H 131)#define IO0902$Q_SLAVE2_ICR_L -1610569856!#define IO0902$Q_SLAVE2_ICR_H {#131$#define IO0902$L_MASTER_ICR_PCI 1332$#define IO0902$L_SLAVE0_ICR_PCI 1334$#define IO0902$L_SLAVE1_ICR_PCI 1338$#define IO0902$L_SLAVE2_ICR_PCI 1340$#define IO0902$L_SLAVE3_ICR_PCI 1342$#define IO0902$L_SLAVE4_ICR_PCI 1336 #define IO0902$L_ESC_INT1_ICR 32!#define IO0902$L_ESC_INT2_ICR 160)#define IO0902$Q_MASTER_IMR_L -1610570080!#define IO0902$Q_MASTER_IMR_H 131)#define IO0902$Q_SLAVE0_IMR_L -1610570016!#define IO0902$Q_SLAVE0_IMR_H 131)#define IO0902$Q_SLAVE1_IMR_L -1610569888|#!#define IO0902$Q_SLAVE1_IMR_H 131)#define IO0902$Q_SLAVE2_IMR_L -1610569824!#define IO0902$Q_SLAVE2_IMR_H 131$#define IO0902$L_MASTER_IMR_PCI 1333$#define IO0902$L_SLAVE0_IMR_PCI 1335$#define IO0902$L_SLAVE1_IMR_PCI 1339$#define IO0902$L_SLAVE2_IMR_PCI 1341$#define IO0902$L_SLAVE3_IMR_PCI 1343$#define IO0902$L_SLAVE4_IMR_PCI 1337 #define IO0902$L_ESC_INT1_IMR 33!#define IO0902$L_ESC_INT2_IMR 161+#define IO0902$Q_SLU0_RCV_BUF_L -1610580224##define IO0902$Q_SLU0_RCV_BUF_H 131'#defin}#e IO0902$Q_SLU0_IER_L -1610580192#define IO0902$Q_SLU0_IER_H 131'#define IO0902$Q_SLU0_IIR_L -1610580160#define IO0902$Q_SLU0_IIR_H 131)#define IO0902$Q_SLU0_L_CTL_L -1610580128!#define IO0902$Q_SLU0_L_CTL_H 131)#define IO0902$Q_SLU0_M_CTL_L -1610580096!#define IO0902$Q_SLU0_M_CTL_H 131*#define IO0902$Q_SLU0_L_STAT_L -1610580064"#define IO0902$Q_SLU0_L_STAT_H 131*#define IO0902$Q_SLU0_M_STAT_L -1610580032"#define IO0902$Q_SLU0_M_STAT_H 131&#define IO0902$L_SLU0_RCV_BUF_PCI 1016" ~##define IO0902$L_SLU0_IER_PCI 1017"#define IO0902$L_SLU0_IIR_PCI 1018$#define IO0902$L_SLU0_L_CTL_PCI 1019$#define IO0902$L_SLU0_M_CTL_PCI 1020%#define IO0902$L_SLU0_L_STAT_PCI 1021%#define IO0902$L_SLU0_M_STAT_PCI 1022+#define IO0902$Q_SLU1_RCV_BUF_L -1610588416##define IO0902$Q_SLU1_RCV_BUF_H 131'#define IO0902$Q_SLU1_IER_L -1610588384#define IO0902$Q_SLU1_IER_H 131'#define IO0902$Q_SLU1_IIR_L -1610588352#define IO0902$Q_SLU1_IIR_H 131)#define IO0902$Q_SLU1_L_CTL_L -1610588320#!#define IO0902$Q_SLU1_L_CTL_H 131)#define IO0902$Q_SLU1_M_CTL_L -1610588288!#define IO0902$Q_SLU1_M_CTL_H 131*#define IO0902$Q_SLU1_L_STAT_L -1610588256"#define IO0902$Q_SLU1_L_STAT_H 131*#define IO0902$Q_SLU1_M_STAT_L -1610588224"#define IO0902$Q_SLU1_M_STAT_H 131%#define IO0902$L_SLU1_RCV_BUF_PCI 760!#define IO0902$L_SLU1_IER_PCI 761!#define IO0902$L_SLU1_IIR_PCI 762##define IO0902$L_SLU1_L_CTL_PCI 763##define IO0902$L_SLU1_M_CTL_PCI 764$#define IO0902$L_SLU1_L_STAT_PCI 765$#d #efine IO0902$L_SLU1_M_STAT_PCI 766 #define IO0902$B_KBD_CMD_PCI 100 #define IO0902$B_KBD_DATA_PCI 96&#define IO0902$Q_KBD_CMD_L -1610609536#define IO0902$Q_KBD_CMD_H 131'#define IO0902$Q_KBD_DATA_L -1610609664#define IO0902$Q_KBD_DATA_H 131/#define IO0902$Q_PCI_SLOT0_CFG_PA_L -1878982656'#define IO0902$Q_PCI_SLOT0_CFG_PA_H 131/#define IO0902$Q_PCI_SLOT1_CFG_PA_L -1878917120'#define IO0902$Q_PCI_SLOT1_CFG_PA_H 131/#define IO0902$Q_PCI_SLOT2_CFG_PA_L -1878786048'#define IO0902$Q_PCI #_SLOT2_CFG_PA_H 131/#define IO0902$Q_PCI_SLOT3_CFG_PA_L -1878523904'#define IO0902$Q_PCI_SLOT3_CFG_PA_H 131/#define IO0902$Q_PCI_SLOT4_CFG_PA_L -1877999616'#define IO0902$Q_PCI_SLOT4_CFG_PA_H 131/#define IO0902$Q_PCI_SLOT5_CFG_PA_L -1876951040'#define IO0902$Q_PCI_SLOT5_CFG_PA_H 131/#define IO0902$Q_PCI_SLOT6_CFG_PA_L -1874853888'#define IO0902$Q_PCI_SLOT6_CFG_PA_H 131/#define IO0902$Q_PCI_SLOT7_CFG_PA_L -1870659584'#define IO0902$Q_PCI_SLOT7_CFG_PA_H 131/#define IO0902$Q_PCI_SLO #T8_CFG_PA_L -1862270976'#define IO0902$Q_PCI_SLOT8_CFG_PA_H 131/#define IO0902$Q_PCI_SLOT9_CFG_PA_L -1845493760'#define IO0902$Q_PCI_SLOT9_CFG_PA_H 1310#define IO0902$Q_PCI_SLOT10_CFG_PA_L -1811939328(#define IO0902$Q_PCI_SLOT10_CFG_PA_H 131,#define IO0902$Q_PCI_SPARSE_IO_L -1610612736$#define IO0902$Q_PCI_SPARSE_IO_H 131##define IO0902$Q_PCI_SPARSE_MEM_L 0%#define IO0902$Q_PCI_SPARSE_MEM_H 130,#define IO0902$Q_PCI_DENSE_MEM_L -1073741824$#define IO0902$Q_PCI_DENSE_MEM_H 131/#define #IO0902$Q_PCI_CONFIG_SPACE_L -1879048192'#define IO0902$Q_PCI_CONFIG_SPACE_H 1310#define IO0902$Q_PCI_EIO_SPARSE_IO_L -1073741824(#define IO0902$Q_PCI_EIO_SPARSE_IO_H 129'#define IO0902$Q_PCI_EIO_SPARSE_MEM_L 0)#define IO0902$Q_PCI_EIO_SPARSE_MEM_H 1310#define IO0902$Q_PCI_EIO_DENSE_MEM_L -2147483648(#define IO0902$Q_PCI_EIO_DENSE_MEM_H 1293#define IO0902$Q_PCI_EIO_CONFIG_SPACE_L -1744830464+#define IO0902$Q_PCI_EIO_CONFIG_SPACE_H 131+#define IO0902$Q_T4MASTER_ICR_L -1073699200##defin #e IO0902$Q_T4MASTER_ICR_H 129+#define IO0902$Q_T4SLAVE0_ICR_L -1073699136##define IO0902$Q_T4SLAVE0_ICR_H 129+#define IO0902$Q_T4MASTER_IMR_L -1073699168##define IO0902$Q_T4MASTER_IMR_H 129+#define IO0902$Q_T4SLAVE0_IMR_L -1073699104##define IO0902$Q_T4SLAVE0_IMR_H 129##define IO0902$K_T2_VECTOR_COUNT 56##define IO0902$K_T3_VECTOR_COUNT 64&#define IO0902$K_EXTIO_VECTOR_COUNT 16 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pr#agmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IO0902DEF_LOADED */ ww@OE[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by #Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS S#oftware, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************* #*************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 22-JAN-1998 14:14:23 $1$DGA8345:[LIB_H.SRC]IO0C05DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IO0C05DEF ***/#ifndef __IO0C05DEF_LOADED#define __IO0C05DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pra#gma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params #...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define IO0C05$L_IO_PA_H 3968#define IO0C05$L_NODE_PA_H 4095'#define IO0C05$L_NODE0_PA_L -2013265920'#define IO0C05$L_NODE1_PA_L -2009071616'#define IO0C05$L_NODE2_PA_L -2004877312'#define IO0C05$L_NODE3_PA_L -2000683008'#d #efine IO0C05$L_NODE4_PA_L -1996488704'#define IO0C05$L_NODE5_PA_L -1992294400'#define IO0C05$L_NODE6_PA_L -1988100096'#define IO0C05$L_NODE7_PA_L -1983905792'#define IO0C05$L_NODE8_PA_L -1979711488N#define IO0C05$L_BROADCAST_L -1912602624 /* BROADCAST SPACE */N#define IO0C05$L_UART0_L -1610612736 /* UART 0 */N#define IO0C05$L_UART1_L -1593835520 /* UART 1 */N#define IO0C05$L_WATCH_L -1342177280 /* WATCH CHIP # */N#define IO0C05$L_GBUS_L -1073741824 /* GBUS */N#define IO0C05$K_TLIPINTR 64 /* IP INTR REG */N#define IO0C05$K_TLIOINTR4 256 /* I/O INT REG 4 */N#define IO0C05$K_TLIOINTR5 320 /* I/O INT REG 5 */N#define IO0C05$K_TLIOINTR6 384 /* I/O INT REG 6 */N#define IO0C05$K_TLIOINTR7 448 /* I/O INT REG 4 */N#def#ine IO0C05$K_TLIOINTR8 512 /* I/O INT REG 7 */N#define IO0C05$K_TLWSDQR4 1024 /* WIND SPACE DC4 */N#define IO0C05$K_TLWSDQR5 1088 /* WIND SPACE DC5 */N#define IO0C05$K_TLWSDQR6 1152 /* WIND SPACE DC6 */N#define IO0C05$K_TLWSDQR7 1216 /* WIND SPACE DC7 */N#define IO0C05$K_TLWSDQR8 1280 /* WIND SPACE DC8 */N#define IO0C05$K_TLRMDQRX 1536 # /* RM DEC CNT X */N#define IO0C05$K_TLRMDQR8 1600 /* RM DEC CNT 8 */N#define IO0C05$K_TLRDRD 2048 /* WIND SP RD DATA DATA */N#define IO0C05$K_TLRDRE 2112 /* WIND SP RD DATA ERR */#define IO0C05$K_B_RR0 0#define IO0C05$K_B_RR8 64#define IO0C05$K_A_RR0 128#define IO0C05$K_A_RR8 192#define IO0C05$K_SECONDS 0#define IO0C05$K_MINUTES 128#define IO0C05$K_HOURS 256!#define IO0C05$K_DAY#_OF_MONTH 448#define IO0C05$K_MONTH 512#define IO0C05$K_YEAR 576#define IO0C05$K_CSRA 640#define IO0C05$K_CSRB 704#define IO0C05$K_CSRC 768#define IO0C05$K_CSRD 832#define IO0C05$K_RAM 896#define IO0C05$K_WHAMI 0#define IO0C05$K_LED0 16777216#define IO0C05$K_LED1 33554432#define IO0C05$K_LED2 50331648#define IO0C05$K_MISCR 67108864#define IO0C05$K_MISCW 83886080"#define IO0C05$K_TLSBRST 100663296!#define IO0C05$K_SERNUM 117440512#define IO0C05$K_TEST 134217728N##define IO0C05$K_TLDEV 0 /* DEVICE */N#define IO0C05$K_TLBER 64 /* ERROR */N#define IO0C05$K_TLCNR 128 /* CONFIGURATION */N#define IO0C05$K_TLVID 192 /* VIRT ID */N#define IO0C05$K_TLMMR0 512 /* MEM MAPPING 0 */N#define IO0C05$K_TLMMR1 576 /* MEM MAPPING 1 */N#define IO0C05$K_TLMMR2 64#0 /* MEM MAPPING 2 */N#define IO0C05$K_TLMMR3 704 /* MEM MAPPING 3 */N#define IO0C05$K_TLMMR4 768 /* MEM MAPPING 4 */N#define IO0C05$K_TLMMR5 832 /* MEM MAPPING 5 */N#define IO0C05$K_TLMMR6 896 /* MEM MAPPING 6 */N#define IO0C05$K_TLMMR7 960 /* MEM MAPPING 7 */N#define IO0C05$K_TLFADR0 1536 /* FAILING A#DDR 0 */N#define IO0C05$K_TLFADR1 1600 /* FAILING ADDR 1 */N#define IO0C05$K_TLESR0 1664 /* BUS ERROR SYNDROME 0 */N#define IO0C05$K_TLESR1 1728 /* BUS ERROR SYNDROME 1 */N#define IO0C05$K_TLESR2 1792 /* BUS ERROR SYNDROME 2 */N#define IO0C05$K_TLESR3 1856 /* BUS ERROR SYNDROME 3 */N#define IO0C05$K_TLILID0 2560 /* TIOP INT LVL 0 */#N#define IO0C05$K_TLILID1 2624 /* TIOP INT LVL 1 */N#define IO0C05$K_TLILID2 2688 /* TIOP INT LVL 2 */N#define IO0C05$K_TLILID3 2752 /* TIOP INT LVL 3 */N#define IO0C05$K_TLCPUMASK 2816 /* TIOP CPU INT MASK */N#define IO0C05$K_TLMBPR 3072 /* TIOP MBX PNTR REG */N#define IO0C05$K_TLDIAG 4096 /* TLEP DIAG SETUP */N#define IO0C05$K_TLDTAGD#ATA 4160 /* TLEP DTAG DATA */N#define IO0C05$K_TLDTAGSTAT 4224 /* TLEP DTAG STAT */N#define IO0C05$K_TLMODCONFIG 4288 /* TLEP MOD CONFIG */N#define IO0C05$K_TLINTRMASK0 4352 /* TLEP INT MASK 0 */N#define IO0C05$K_TLINTRMASK1 4416 /* TLEP INT MASK 1 */N#define IO0C05$K_TLINTRSUM0 4480 /* TLEP INT SUM 0 */N#define IO0C05$K_TLINTRSUM1 4544 /* TLEP IN#T SUM 1 */N#define IO0C05$K_TLCON00 4608 /* TLEP CONS COMM */N#define IO0C05$K_TLCON00A 4672 /* TLEP DIGA COMM TEST */N#define IO0C05$K_TLCON00B 4736 /* TLEP DIGA COMM TEST */N#define IO0C05$K_TLCON00C 4800 /* TLEP DIGA COMM TEST */N#define IO0C05$K_TLCON10 4864 /* TLEP CONS COMM */N#define IO0C05$K_TLCON10A 4928 /* TLEP DIGA COMM TEST #*/N#define IO0C05$K_TLCON10B 4992 /* TLEP DIGA COMM TEST */N#define IO0C05$K_TLCON10C 5056 /* TLEP DIGA COMM TEST */N#define IO0C05$K_TLCON01 5120 /* TLEP CONS COMM */N#define IO0C05$K_TLCON11 5184 /* TLEP CONS COMM */N#define IO0C05$K_TLEPAERR 5376 /* TLEP ADG ERROR */N#define IO0C05$K_TLEPDERR 5440 /* TLEP DIGA ERROR */N#define IO0C05$K_TLEPM#ERR 5504 /* TLEP MMG ERROR */N#define IO0C05$K_TLEP_VMG 5568 /* TLEP VOLT MARG */N#define IO0C05$K_TLDMCMD 5632 /* TLEP DM CMD */N#define IO0C05$K_TLDMADRA 5760 /* TLEP DM A */N#define IO0C05$K_TLDMADRB 5824 /* TLEP DM B */N#define IO0C05$K_TLPM_CMD 6144 /* TLEP PERF MON CMD */N#define IO0C05$K_TLPM_TOT_CYC 6208 /* TLEP ## OF CYCLES */N#define IO0C05$K_TLPM_EV5_LAT 6272 /* TLEP EV5 RD LAT */N#define IO0C05$K_TLPM_READ_LAT 6336 /* TLEP AV RD LAT */N#define IO0C05$K_TLPM_SYS_OWNER 6400 /* TLEP # CYC OF SYS OWNER */N#define IO0C05$K_TLPM_CMD_SILO 6464 /* TLEP CMD SILO */N#define IO0C05$K_TLPM_LOCK 6528 /* TLEP # LOCK ACKS */N#define IO0C05$K_TLPM_MB 6592 /* TLEP # MB ACKS # */N#define IO0C05$K_TLPM_SD_TOTAL 6656 /* TLEP # SD */N#define IO0C05$K_TLPM_SD_ACKED 6720 /* TLEP # SD ACKS */N#define IO0C05$K_TLPM_RD_CSR 6784 /* TLEP # CSR RDS */N#define IO0C05$K_TLPM_RD 6848 /* TLEP # MEM RD MISS */N#define IO0C05$K_TLPM_RD_MOD 6912 /* TLEP # RD MISS MODS */N#define IO0C05$K_TLPM_RD_STC 6976 /* TLEP # RD MISS STXC */N#define IO0C05$K_TLP#M_VICTIM 7040 /* TLEP # BC VICTIMS */N#define IO0C05$K_TLPM_WR_CSR 7104 /* TLEP # CSR WR CMDS */N#define IO0C05$K_TLPM_WR 7168 /* TLEP # WR BLK CMDS ACKED */N#define IO0C05$K_TLPM_WR_LOCK 7232 /* TLEP # WR BLK LK CMDS ACKED */N#define IO0C05$K_TLPM_INVAL 7296 /* TLEP # INVAL */N#define IO0C05$K_TLPM_SET_SHRD 7360 /* TLEP # SET SHRDS */N#define IO0C05$K_TLPM_RD_DIRTY 7424 /* TLE#P # RD DIRTYS */N#define IO0C05$K_TLPM_ADR_SILO 7488 /* TLEP ADR SILO REG */N#define IO0C05$K_RM_RANG_REG0A 7680 /* TLEP RM MR CHAN0A */N#define IO0C05$K_RM_RANG_REG0B 7744 /* TLEP RM MR CHAN0B */N#define IO0C05$K_RM_RANG_REG1A 7808 /* TLEP RM MR CHAN1A */N#define IO0C05$K_RM_RANG_REG1B 7872 /* TLEP RM MR CHAN1B */N#define IO0C05$K_TLMODCONFIG0 4096 /* TL-6 MODULE CONFIG REG 0 # */N#define IO0C05$K_TLDTAGADDR 4224 /* TL-6 DTAG ADDRESS REG */N#define IO0C05$K_TLMODCONFIG1 4288 /* TL-6 MODULE CONFIG REG 1 */N#define IO0C05$K_TCCERR 5376 /* TL-6 TCC ERROR REGISTER */N#define IO0C05$K_TDIERR 5440 /* TL-6 TDI ERROR REGISTER */N#define IO0C05$K_TL6_VMG 5568 /* TL-6 VOLTAGE MARGINING REG */N#define IO0C05$K_TL6WERR 5632 /* TL-6 WINDOW SPACE ERROR REG */N#define IO0C05$K_T#LDTAGEX 6144 /* TL-6 DTAG TEST EXECUTE REG */N#define IO0C05$K_TLLOOPBCK 6208 /* TL-6 DIAG LOOPBACK REG. */N#define IO0C05$K_TLICCMSR 8192 /* TIOP I/O CNTRL CHIP MODE SEL */O#define IO0C05$K_TLICCNSE 8256 /* TIOP I/O CNTRL CHIP NODE SPEC ERR */N#define IO0C05$K_TLICCDR 8320 /* TIOP I/O CNTRL CHIP DIAG REG */O#define IO0C05$K_TLICCMTR 8384 /* TIOP I/O CNTRL CHIP MBX TRANS REG */P#define IO0C05$K_TLICCWRT 8448 #/* TIOP I/O CNTRL CHIP CSR WIND TRANS */N#define IO0C05$K_TLIDPNSE1 8512 /* TIOP NODE SPEC DPATH ERROR 1 */N#define IO0C05$K_TLIDPDR1 8576 /* TIOP I/O DPATH DIAG REG 1 */N#define IO0C05$K_TLIDPNSE2 8768 /* TIOP NODE SPEC DPATH ERROR 2 */N#define IO0C05$K_TLIDPDR2 8832 /* TIOP I/O DPATH DIAG REG 2 */N#define IO0C05$K_TLIDPNSE3 9024 /* TIOP NODE SPEC DPATH ERROR 3 */N#define IO0C05$K_TLIDPDR3 9088 /* TIOP I/O DPATH DIAG R#EG 3 */N#define IO0C05$K_TLIDPNSE0 10816 /* TIOP NODE SPEC DPATH ERROR 0 */N#define IO0C05$K_TLIDPDR0 10880 /* TIOP I/O DPATH DIAG REG 0 */N#define IO0C05$K_TLIPCPUMASK 10944 /* TIOP IP CPU INTR MASK */N#define IO0C05$K_TLIDPVR 11072 /* TIOP I/O DPATH VECT */N#define IO0C05$K_TLIDPMSR 11136 /* TIOP I/O DPATH MODE SEL */N#define IO0C05$K_TLIBR 11200 /* TIOP INFO BASE REPAIR */N#define IO#0C05$K_TLDHRR0A 12288 /* TIOP DOWN HOSE RANGE REGISTER 0A */N#define IO0C05$K_TLDHRR0B 12352 /* TIOP DOWN HOSE RANGE REGISTER 0B */N#define IO0C05$K_TLDHRR1A 12416 /* TIOP DOWN HOSE RANGE REGISTER 1A */N#define IO0C05$K_TLDHRR1B 12480 /* TIOP DOWN HOSE RANGE REGISTER 1B */N#define IO0C05$K_TLSECR 6144 /* TLMEM SECR EEPROM CNTL */N#define IO0C05$K_TLMIR 6208 /* TLMEM MEM INTERLEAVE */N#define IO0C05$K_TLMCR 6272 # /* TLMEM MEM CONFIG */N#define IO0C05$K_TLSTAIR 6336 /* TLMEM SELFTEST ADR ISOL */N#define IO0C05$K_TLSTER 6400 /* TLMEM SELFTEST ERR REG */N#define IO0C05$K_TLMER 6464 /* TLMEM MEM ERROR REG */N#define IO0C05$K_TLMDRA 6528 /* TLMEM MEM DIAG REG A */N#define IO0C05$K_TLMDRB 6592 /* TLMEM MEM DIAG REG B */N#define IO0C05$K_TLSTDERA_0 65536 /* TLMEM SELFTEST DATA# ERR REG A0 */N#define IO0C05$K_TLSTDERB_0 65600 /* TLMEM SELFTEST DATA ERR REG B0 */N#define IO0C05$K_TLSTDERC_0 65664 /* TLMEM SELFTEST DATA ERR REG C0 */N#define IO0C05$K_TLSTDERD_0 65728 /* TLMEM SELFTEST DATA ERR REG D0 */N#define IO0C05$K_TLSTDERE_0 65792 /* TLMEM SELFTEST DATA ERR REG E0 */N#define IO0C05$K_TLDDR0 65856 /* TLMEM DATA DIAG REG 0 */N#define IO0C05$K_TLSTDERA_1 81920 /* TLMEM SELFTEST DATA ERR REG A1 */N#define #IO0C05$K_TLSTDERB_1 81984 /* TLMEM SELFTEST DATA ERR REG B1 */N#define IO0C05$K_TLSTDERC_1 82048 /* TLMEM SELFTEST DATA ERR REG C1 */N#define IO0C05$K_TLSTDERD_1 82112 /* TLMEM SELFTEST DATA ERR REG D1 */N#define IO0C05$K_TLSTDERE_1 82176 /* TLMEM SELFTEST DATA ERR REG E1 */N#define IO0C05$K_TLDDR1 82240 /* TLMEM DATA DIAG REG 1 */N#define IO0C05$K_TLSTDERA_2 98304 /* TLMEM SELFTEST DATA ERR REG A2 */N#define IO0C05$K_TLSTDERB_2 98368 # /* TLMEM SELFTEST DATA ERR REG B2 */N#define IO0C05$K_TLSTDERC_2 98432 /* TLMEM SELFTEST DATA ERR REG C2 */N#define IO0C05$K_TLSTDERD_2 98496 /* TLMEM SELFTEST DATA ERR REG D2 */N#define IO0C05$K_TLSTDERE_2 98560 /* TLMEM SELFTEST DATA ERR REG E2 */N#define IO0C05$K_TLDDR2 98624 /* TLMEM DATA DIAG REG 2 */N#define IO0C05$K_TLSTDERA_3 114688 /* TLMEM SELFTEST DATA ERR REG A3 */N#define IO0C05$K_TLSTDERB_3 114752 /* TLMEM SELFTEST DA #TA ERR REG B3 */N#define IO0C05$K_TLSTDERC_3 114816 /* TLMEM SELFTEST DATA ERR REG C3 */N#define IO0C05$K_TLSTDERD_3 114880 /* TLMEM SELFTEST DATA ERR REG D3 */N#define IO0C05$K_TLSTDERE_3 114944 /* TLMEM SELFTEST DATA ERR REG E3 */N#define IO0C05$K_TLDDR3 115008 /* TLMEM DATA DIAG REG 3 */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restor#e /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IO0C05DEF_LOADED */ ww`E[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **#/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be u#sed, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************************************************************* #*/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 23-DEC-1993 09:20:33 $1$DGA8345:[LIB_H.SRC]IO0E04DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IO0E04DEF ***/#ifndef __IO0E04DEF_LOADED#define __IO0E04DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignment#R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#d#efine __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif -#define IO0E04$L_IOC_IACK_SC_PA_L -1073741824##define IO0E04$L_IOC_IACK_SC_PA_H 1+#define IO0E04$L_CFG_CYCLE_PA_L -2147483648!#define IO0E04$L_CFG_CYCLE_PA_H 1'#define IO0E04$L_TB_EN_PA_L -2147483648#define IO0E04$L_TB_EN_PA_H 1-#define IO0E04$L_PCI_SFT_RST_PA_L -2147483648##defin#e IO0E04$L_PCI_SFT_RST_PA_H 11#define IO0E04$L_PCI_PAR_DISABLE_PA_L -2147483648'#define IO0E04$L_PCI_PAR_DISABLE_PA_H 1#define IO0E04$L_PCI_IO_PA_L 0#define IO0E04$L_PCI_IO_PA_H 3(#define IO0E04$L_PCI_IO_END_PA_L 2097152"#define IO0E04$L_PCI_IO_END_PA_H 3##define IO0E04$L_KBD_DATA_PA_L 3072 #define IO0E04$L_KBD_DATA_PA_H 3 #define IO0E04$B_KBD_DATA_PCI 96"#define IO0E04$L_KBD_CMD_PA_L 3200#define IO0E04$L_KBD_CMD_PA_H 3 #define IO0E04$B_KBD_CMD_PCI 100!#define IO0E04$L_DS1287_PA_L# 3584#define IO0E04$L_DS1287_PA_H 3 #define IO0E04$L_COM1_PA_L 32512#define IO0E04$L_COM1_PA_H 3&#define IO0E04$L_COM1_RCV_BUF_PCI 1016"#define IO0E04$L_COM1_IER_PCI 1017"#define IO0E04$L_COM1_IIR_PCI 1018$#define IO0E04$L_COM1_L_CTL_PCI 1019$#define IO0E04$L_COM1_M_CTL_PCI 1020%#define IO0E04$L_COM1_L_STAT_PCI 1021%#define IO0E04$L_COM1_M_STAT_PCI 1022 #define IO0E04$L_COM2_PA_L 24320#define IO0E04$L_COM2_PA_H 3%#define IO0E04$L_COM2_RCV_BUF_PCI 760!#define IO0E04$L_COM2_IER_PCI #761!#define IO0E04$L_COM2_IIR_PCI 762##define IO0E04$L_COM2_L_CTL_PCI 763##define IO0E04$L_COM2_M_CTL_PCI 764$#define IO0E04$L_COM2_L_STAT_PCI 765$#define IO0E04$L_COM2_M_STAT_PCI 766!#define IO0E04$L_PPORT_PA_L 28416#define IO0E04$L_PPORT_PA_H 3"#define IO0E04$L_FLOPPY_PA_L 32256#define IO0E04$L_FLOPPY_PA_H 3"#define IO0E04$L_MASTER_ICR_PCI 32"#define IO0E04$L_MASTER_IMR_PCI 33"#define IO0E04$L_SLAVE_ICR_PCI 160"#define IO0E04$L_SLAVE_IMR_PCI 161#define IO0E04$L_PCI_IRR_REG 38 ##define IO0E04$L_PCI_IMR_REG 38%#define IO0E04$L_HAE_PA_L -2147483648#define IO0E04$L_HAE_PA_H 1+#define IO0E04$L_IOC_STAT0_PA_L -2147483584!#define IO0E04$L_IOC_STAT0_PA_H 1+#define IO0E04$L_IOC_STAT1_PA_L -2147483552!#define IO0E04$L_IOC_STAT1_PA_H 1*#define IO0E04$L_IOC_TBIA_PA_L -2147483520 #define IO0E04$L_IOC_TBIA_PA_H 1.#define IO0E04$L_IOC_W_BASE_0_PA_L -2147483392$#define IO0E04$L_IOC_W_BASE_0_PA_H 1.#define IO0E04$L_IOC_W_BASE_1_PA_L -2147483360$#define IO0E04$L_IOC_W_B #ASE_1_PA_H 1.#define IO0E04$L_IOC_W_MASK_0_PA_L -2147483328$#define IO0E04$L_IOC_W_MASK_0_PA_H 1.#define IO0E04$L_IOC_W_MASK_1_PA_L -2147483296$#define IO0E04$L_IOC_W_MASK_1_PA_H 1.#define IO0E04$L_IOC_T_BASE_0_PA_L -2147483264$#define IO0E04$L_IOC_T_BASE_0_PA_H 1.#define IO0E04$L_IOC_T_BASE_1_PA_L -2147483232$#define IO0E04$L_IOC_T_BASE_1_PA_H 1.#define IO0E04$L_IOC_TB_TAG_0_PA_L -2130706432$#define IO0E04$L_IOC_TB_TAG_0_PA_H 1.#define IO0E04$L_IOC_TB_TAG_1_PA_L -2130706400$#define IO0E04 #$L_IOC_TB_TAG_1_PA_H 1.#define IO0E04$L_IOC_TB_TAG_2_PA_L -2130706368$#define IO0E04$L_IOC_TB_TAG_2_PA_H 1.#define IO0E04$L_IOC_TB_TAG_3_PA_L -2130706336$#define IO0E04$L_IOC_TB_TAG_3_PA_H 1.#define IO0E04$L_IOC_TB_TAG_4_PA_L -2130706304$#define IO0E04$L_IOC_TB_TAG_4_PA_H 1.#define IO0E04$L_IOC_TB_TAG_5_PA_L -2130706272$#define IO0E04$L_IOC_TB_TAG_5_PA_H 1.#define IO0E04$L_IOC_TB_TAG_6_PA_L -2130706240$#define IO0E04$L_IOC_TB_TAG_6_PA_H 1.#define IO0E04$L_IOC_TB_TAG_7_PA_L -2130706208$#def #ine IO0E04$L_IOC_TB_TAG_7_PA_H 1(#define IO0E04$L_FLASH_ROM1_PA 939524096(#define IO0E04$L_FLASH_ROM2_PA 941621248(#define IO0E04$L_FLASH_ROM3_PA 943718400(#define IO0E04$L_FLASH_ROM4_PA 945815552,#define IO0E04$L_FLASH_ROM1_END_PA 941621240,#define IO0E04$L_FLASH_ROM2_END_PA 943718392,#define IO0E04$L_FLASH_ROM3_END_PA 945815544,#define IO0E04$L_FLASH_ROM4_END_PA 947912696&#define IO0E04$L_PCI_SPARSE_MEM_PA_L 0&#define IO0E04$L_PCI_SPARSE_MEM_PA_H 21#define IO0E04$L_PCI_SPARSE_MEMEND_PA_L #536870912)#define IO0E04$L_PCI_SPARSE_MEMEND_PA_H 2%#define IO0E04$L_PCI_DENSE_MEM_PA_L 0%#define IO0E04$L_PCI_DENSE_MEM_PA_H 3*#define IO0E04$L_PCI_DENSE_MEM_END_PA_L -1)#define IO0E04$L_PCI_DENSE_MEM_END_PA_H 3 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __st #andard #endif /* __IO0E04DEF_LOADED */ wwE[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of #HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. # **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 07-MAR-1997 16:37:42 $1$DGA8345:[LIB #_H.SRC]IO0F05DEF.SDL;1 *//********************************************************************************************************************************/%/*** MODULE $IO0F05DEF IDENT X-3 ***/#ifndef __IO0F05DEF_LOADED#define __IO0F05DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_p#ointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#i#f !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define IO0F05$L_NODE_PA_H 135 /* High order word */)#define IO0F05$L_CIA_GENERAL_L 1073741824(#define IO0F05$L_CIA_MEMORY_L 1342177280*#define IO0F05$L_CIA_PCI_ADDR_L 1610612736,#define IO0F05$L_FLASH_AND_GRU_L -2147483648N#define IO0F05$L_PCI_REV_L 128 /*PCI revision */N#define IO0F05$L_PCI_LAT_L 192 /*PCI Latency # */N#define IO0F05$L_CIA_CTRL_L 256 /*CIA COntrol */N#define IO0F05$L_HAE_MEM_L 1024 /*HAE memory */N#define IO0F05$L_HAE_IO_L 1088 /*HAE I/O */N#define IO0F05$L_HAE_CFG_L 1152 /*COnfig */N#define IO0F05$L_CIA_CACK_EN_L 1536 /*Ack control */N#define IO0F05$L_CIA_DIAG_L 8192 /*Diag control */N#define IO0F#05$L_CIA_CHECK_L 12288 /*Diag check */N#define IO0F05$L_PERF_MON_L 16384 /*Perf monitor */N#define IO0F05$L_PERF_CNTR_L 16448 /*Perf control */N#define IO0F05$L_CPU_ERR0_L 32768 /*Cpu err info 0 */N#define IO0F05$L_CPU_ERR1_L 32832 /*Cpu err info 1 */N#define IO0F05$L_CIA_ERR_L 33280 /*CIA err */N#define IO0F05$L_CIA_STAT_L 33344 # /*CIA status */N#define IO0F05$L_CIA_ERR_MSK_L 33408 /*CIA err mask */N#define IO0F05$L_CIA_SYN_L 33536 /*CIA syndrome */N#define IO0F05$L_CPU_MPSR0_L 33792 /*Memport stat0 */N#define IO0F05$L_CPU_MPSR1_L 33856 /*Memport stat1 */N#define IO0F05$L_PCI_ERR0_L 34816 /*PCI Err 0 */N#define IO0F05$L_PCI_ERR1_L 34880 /*PCI Err 1 # */N#define IO0F05$L_PCI_ERR2_L 34944 /*PCI Err 1 */N#define IO0F05$L_MEM_CNFG_L 0 /*Memory config */N#define IO0F05$L_MEM_BA0_L 1536 /*Mem base addr0 */N#define IO0F05$L_MEM_BA2_L 1664 /*Mem base addr2 */N#define IO0F05$L_MEM_BA4_L 1792 /*Mem base addr4 */N#define IO0F05$L_MEM_BA6_L 1920 /*Mem base addr6 */N#define IO#0F05$L_MEM_BA8_L 2048 /*Mem base addr8 */N#define IO0F05$L_MEM_BAA_L 2176 /*Mem base addrA */N#define IO0F05$L_MEM_BAC_L 2304 /*Mem base addrC */N#define IO0F05$L_MEM_BAE_L 2432 /*Mem base addrE */N#define IO0F05$L_MEM_TMG0_L 2816 /*Mem timing 0 */N#define IO0F05$L_MEM_TMG1_L 2880 /*Mem timing 1 */N#define IO0F05$L_MEM_TMG2_L 2944 # /*Mem timing 2 */N#define IO0F05$L_PCI_TBIA_L 256 /*SG TB inval */N#define IO0F05$L_PCI_W0_BASE_L 1024 /*Window base0 */N#define IO0F05$L_PCI_W0_MASK_L 1088 /*Window mask0 */N#define IO0F05$L_PCI_T0_BASE_L 1152 /*Trans base0 */N#define IO0F05$L_PCI_W1_BASE_L 1280 /*Window base1 */N#define IO0F05$L_PCI_W1_MASK_L 1344 /*Window mask1 # */N#define IO0F05$L_PCI_T1_BASE_L 1408 /*Trans base1 */N#define IO0F05$L_PCI_W2_BASE_L 1536 /*Window base2 */N#define IO0F05$L_PCI_W2_MASK_L 1600 /*Window mask2 */N#define IO0F05$L_PCI_T2_BASE_L 1664 /*Trans base2 */N#define IO0F05$L_PCI_W3_BASE_L 1792 /*Window base3 */N#define IO0F05$L_PCI_W3_MASK_L 1856 /*Window mask3 */N#define #IO0F05$L_PCI_T3_BASE_L 1920 /*Trans base3 */N#define IO0F05$L_PCI_DAC_BASE_L 1984 /*DAC Base */N#define IO0F05$L_PCI_LTB_TAG0_L 2048 /*Lock TB tag0 */N#define IO0F05$L_PCI_LTB_TAG1_L 2112 /*Lock TB tag1 */N#define IO0F05$L_PCI_LTB_TAG2_L 2176 /*Lock TB tag2 */N#define IO0F05$L_PCI_LTB_TAG3_L 2240 /*Lock TB tag3 */N#define IO0F05$L_PCI_TB_TAG0_L 230#4 /* TB tag0 */N#define IO0F05$L_PCI_TB_TAG1_L 2368 /* TB tag1 */N#define IO0F05$L_PCI_TB_TAG2_L 2432 /* TB tag2 */N#define IO0F05$L_PCI_TB_TAG3_L 2496 /* TB tag3 */N#define IO0F05$L_PCI_TB0_PAGE0_L 4096 /* TB0 page0 */N#define IO0F05$L_PCI_TB0_PAGE1_L 4160 /* TB0 page1 */N#define IO0F05$L_PCI_TB0_PAGE2_L 4224 /* TB0 page2 # */N#define IO0F05$L_PCI_TB0_PAGE3_L 4288 /* TB0 page3 */N#define IO0F05$L_PCI_TB1_PAGE0_L 4352 /* TB1 page0 */N#define IO0F05$L_PCI_TB1_PAGE1_L 4416 /* TB1 page1 */N#define IO0F05$L_PCI_TB1_PAGE2_L 4480 /* TB1 page2 */N#define IO0F05$L_PCI_TB1_PAGE3_L 4544 /* TB1 page3 */N#define IO0F05$L_PCI_TB2_PAGE0_L 4608 /* TB2 page0 */N#defin#e IO0F05$L_PCI_TB2_PAGE1_L 4672 /* TB2 page1 */N#define IO0F05$L_PCI_TB2_PAGE2_L 4736 /* TB2 page2 */N#define IO0F05$L_PCI_TB2_PAGE3_L 4800 /* TB2 page3 */N#define IO0F05$L_PCI_TB3_PAGE0_L 4864 /* TB3 page0 */N#define IO0F05$L_PCI_TB3_PAGE1_L 4928 /* TB3 page1 */N#define IO0F05$L_PCI_TB3_PAGE2_L 4992 /* TB3 page2 */N#define IO0F05$L_PCI_TB3_PAGE3_L# 5056 /* TB3 page3 */N#define IO0F05$L_PCI_TB4_PAGE0_L 5120 /* TB4 page0 */N#define IO0F05$L_PCI_TB4_PAGE1_L 5184 /* TB4 page1 */N#define IO0F05$L_PCI_TB4_PAGE2_L 5248 /* TB4 page2 */N#define IO0F05$L_PCI_TB4_PAGE3_L 5312 /* TB4 page3 */N#define IO0F05$L_PCI_TB5_PAGE0_L 5376 /* TB5 page0 */N#define IO0F05$L_PCI_TB5_PAGE1_L 5440 /* TB5 page1 # */N#define IO0F05$L_PCI_TB5_PAGE2_L 5504 /* TB5 page2 */N#define IO0F05$L_PCI_TB5_PAGE3_L 5568 /* TB5 page3 */N#define IO0F05$L_PCI_TB6_PAGE0_L 5632 /* TB6 page0 */N#define IO0F05$L_PCI_TB6_PAGE1_L 5696 /* TB6 page1 */N#define IO0F05$L_PCI_TB6_PAGE2_L 5760 /* TB6 page2 */N#define IO0F05$L_PCI_TB6_PAGE3_L 5824 /* TB6 page3 */N#def#ine IO0F05$L_PCI_TB7_PAGE0_L 5888 /* TB7 page0 */N#define IO0F05$L_PCI_TB7_PAGE1_L 5952 /* TB7 page1 */N#define IO0F05$L_PCI_TB7_PAGE2_L 6016 /* TB7 page2 */N#define IO0F05$L_PCI_TB7_PAGE3_L 6080 /* TB7 page3 */N#define IO0F05$L_GRU_INT_REQ_L 0 /* Int request */N#define IO0F05$L_GRU_INT_MASK_L 64 /* Int mask */N#define IO0F05$L_GRU_INT_EDGE_#L 128 /* Level/edge selct */N#define IO0F05$L_GRU_INT_HILO_L 192 /* Hi/lo irq select */N#define IO0F05$L_GRU_INT_CLR_L 256 /* Clear Int */N#define IO0F05$L_GRU_CACHE_CNFG_L 512 /* Cache config */N#define IO0F05$L_GRU_SET_CNFG_L 768 /* Set Cache config */N#define IO0F05$L_GRU_LEDS_L 2048 /* LEDs */N#define IO0F05$L_GRU_RESET_L 2304 /* Force system #reset */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IO0F05DEF_LOADED */ ww9F[UM/***************************************************************************/M/** # **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** # **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*****************#**********************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 23-JUN-1994 15:35:54 $1$DGA8345:[LIB_H.SRC]IO1504DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IO1504DEF ***/#ifndef __ #IO1504DEF_LOADED#define __IO1504DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern# "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif )#define IO1504$K_IOC_HAE_PA_L -2147483648#define IO1504$K_IOC_HAE_PA_H 1*#define IO1504$K_IOC_CONF_PA#_L -2147483648!#define IO1504$K_IOC_CONF_PA_H 32+#define IO1504$K_IOC_STAT0_PA_L -2147483584!#define IO1504$K_IOC_STAT0_PA_H 1+#define IO1504$K_IOC_STAT1_PA_L -2147483552!#define IO1504$K_IOC_STAT1_PA_H 1*#define IO1504$K_IOC_TBIA_PA_L -2147483520 #define IO1504$K_IOC_TBIA_PA_H 1(#define IO1504$K_TB_ENA_PA_L -2147483648 #define IO1504$K_TB_ENA_PA_H 160)#define IO1504$K_SFT_RST_PA_L -2147483648!#define IO1504$K_SFT_RST_PA_H 192)#define IO1504$K_PAR_DIS_PA_L -2147483648!#define IO15 #04$K_PAR_DIS_PA_H 224-#define IO1504$K_IOC_W_BASE0_PA_L -2147483392##define IO1504$K_IOC_W_BASE0_PA_H 1-#define IO1504$K_IOC_W_BASE1_PA_L -2147483360##define IO1504$K_IOC_W_BASE1_PA_H 1-#define IO1504$K_IOC_W_MASK0_PA_L -2147483328##define IO1504$K_IOC_W_MASK0_PA_H 1-#define IO1504$K_IOC_W_MASK1_PA_L -2147483296##define IO1504$K_IOC_W_MASK1_PA_H 1-#define IO1504$K_IOC_T_BASE0_PA_L -2147483264##define IO1504$K_IOC_T_BASE0_PA_H 1-#define IO1504$K_IOC_T_BASE1_PA_L -2147483232##def #ine IO1504$K_IOC_T_BASE1_PA_H 1-#define IO1504$K_IOC_TB_TAG0_PA_L -2130706432##define IO1504$K_IOC_TB_TAG0_PA_H 0-#define IO1504$K_IOC_TB_TAG1_PA_L -2130706432$#define IO1504$K_IOC_TB_TAG1_PA_H 32-#define IO1504$K_IOC_TB_TAG2_PA_L -2130706432$#define IO1504$K_IOC_TB_TAG2_PA_H 64-#define IO1504$K_IOC_TB_TAG3_PA_L -2130706432$#define IO1504$K_IOC_TB_TAG3_PA_H 96-#define IO1504$K_IOC_TB_TAG4_PA_L -2130706432%#define IO1504$K_IOC_TB_TAG4_PA_H 128-#define IO1504$K_IOC_TB_TAG5_PA_L -21307 #06432%#define IO1504$K_IOC_TB_TAG5_PA_H 160-#define IO1504$K_IOC_TB_TAG6_PA_L -2130706432%#define IO1504$K_IOC_TB_TAG6_PA_H 192-#define IO1504$K_IOC_TB_TAG7_PA_L -2130706432%#define IO1504$K_IOC_TB_TAG7_PA_H 224-#define IO1504$K_IOC_IACK_SC_PA_L -1610612736##define IO1504$K_IOC_IACK_SC_PA_H 1(#define IO1504$K_PCI_IO_PA_L -1073741824#define IO1504$K_PCI_IO_PA_H 1+#define IO1504$K_PCI_IO_END_PA_L -536870913"#define IO1504$K_PCI_IO_END_PA_H 1(#define IO1504$K_PCI_CFG_PA_L -536870912 ##define IO1504$K_PCI_CFG_PA_H 1&#define IO1504$K_PCI_SPARSE_MEM_PA_L 0&#define IO1504$K_PCI_SPARSE_MEM_PA_H 21#define IO1504$K_PCI_SPARSE_MEMEND_PA_L 536870912)#define IO1504$K_PCI_SPARSE_MEMEND_PA_H 2%#define IO1504$K_PCI_DENSE_MEM_PA_L 0%#define IO1504$K_PCI_DENSE_MEM_PA_H 3*#define IO1504$K_PCI_DENSE_MEM_END_PA_L -1)#define IO1504$K_PCI_DENSE_MEM_END_PA_H 3*#define IO1504$K_KBD_DATA_PA_L -1073738752 #define IO1504$K_KBD_DATA_PA_H 1 #define IO1504$B_KBD_DATA_PCI 96)#define IO1504#$K_KBD_CMD_PA_L -1073738624#define IO1504$K_KBD_CMD_PA_H 1 #define IO1504$B_KBD_CMD_PCI 100(#define IO1504$K_DS1287_PA_L -1073738240#define IO1504$K_DS1287_PA_H 1&#define IO1504$K_COM1_PA_L -1073709312#define IO1504$K_COM1_PA_H 1&#define IO1504$K_COM1_RCV_BUF_PCI 1016"#define IO1504$K_COM1_IER_PCI 1017"#define IO1504$K_COM1_IIR_PCI 1018$#define IO1504$K_COM1_L_CTL_PCI 1019$#define IO1504$K_COM1_M_CTL_PCI 1020%#define IO1504$K_COM1_L_STAT_PCI 1021%#define IO1504$K_COM1_M_STAT_PCI 102#2&#define IO1504$K_COM2_PA_L -1073717504#define IO1504$K_COM2_PA_H 1%#define IO1504$K_COM2_RCV_BUF_PCI 760!#define IO1504$K_COM2_IER_PCI 761!#define IO1504$K_COM2_IIR_PCI 762##define IO1504$K_COM2_L_CTL_PCI 763##define IO1504$K_COM2_M_CTL_PCI 764$#define IO1504$K_COM2_L_STAT_PCI 765$#define IO1504$K_COM2_M_STAT_PCI 766'#define IO1504$K_PPORT_PA_L -1073713408#define IO1504$K_PPORT_PA_H 1(#define IO1504$K_FLOPPY_PA_L -1073709568#define IO1504$K_FLOPPY_PA_H 1"#define IO1504$K_MAS#TER_ICR_PCI 32"#define IO1504$K_MASTER_IMR_PCI 33"#define IO1504$K_SLAVE_ICR_PCI 160"#define IO1504$K_SLAVE_IMR_PCI 161#define IO1504$K_PCI_IRR_REG 38#define IO1504$K_PCI_IMR_REG 38(#define IO1504$K_FLASH_ROM1_PA 939524096(#define IO1504$K_FLASH_ROM2_PA 941621248(#define IO1504$K_FLASH_ROM3_PA 943718400(#define IO1504$K_FLASH_ROM4_PA 945815552,#define IO1504$K_FLASH_ROM1_END_PA 941621240,#define IO1504$K_FLASH_ROM2_END_PA 943718392,#define IO1504$K_FLASH_ROM3_END_PA 945815544,#define #IO1504$K_FLASH_ROM4_END_PA 947912696##define IO1504$K_OPDRIVER_XMT_ISR 3##define IO1504$K_OPDRIVER_RCV_ISR 4 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IO1504DEF_LOADED */ ww`F[UM/***********************************#****************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, L#P **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** # **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:14 by OpenVMS SDL V3.7 */G/* Source: 13-APR-2022 12:57:33 $1$DGA8345:[LIB_H.SRC]IOBDDEF.SDL;1 *//*********************************************************************************** #*********************************************//*** MODULE $IOBDDEF ***/#ifndef __IOBDDEF_LOADED#define __IOBDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set p#tr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ # */N/* IOBD -- I/O Buffer Descriptor */N/* */N/* The IOBD structure is used to describe the physical address(es) of all */N/* buffers used in I/O. For the I/O to succeed, the buffer must be */N/* locked in memory. */N/* # */N/* There are two variants of the IOBD structure. The first is the primary */N/* IOBD structure, which may be embedded in an IRP. It contains room for */N/* exactly IOBD$K_FIXED_EXTENT_CNT extents. If more extents are needed */N/* to describe the physical address range of the buffer, the IOBD will be */N/* given a larger auxiliary extent list. */N/* #*/N/* An IOBD can also be created by calling IOC$CREATE_IOBD - in this case, */N/* since the IOBD has to be allocated from pool anyway, its extent list */N/* is sized to hold as many extents as are needed for the specified buffer */N/* and no auxiliary extent list is needed. */N/* */N/* The IRP, IRPE, VCRP, and DCBE structures all contain an embedded fixed- */N/* size IOBD structure#. */N/*- */  #include #ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save&#pragma __required_pointer_size __longtypedef struct _iobd * IOBD_PQ;!typedef struct _iobd ** IOBD_PPQ;)#pragma __required_pointer_size __restore#else!typedef unsigned __int64 IOBD_PQ;"typedef unsigned __int64 IOBD_PPQ;#endif#define IOBD$M_INUSE 0x4 ##define IOBD$M_AUX_EXTENTS 0x10#define IOBD$M_AUX_INUSE 0x20#define IOBD$M_REL_DEALLOC 0x80#define IOBD$M_BY_PTE 0x400#define IOBD$M_AUX_IOBD 0x800&#define IOBD$M_VALID_STORED_FLAGS 1172N#define IOBD$K_HDRLEN 48 /* IOBD header length (w/o extents) */\#define IOBD$K_FIXED_EXTENT_CNT 4 /* Number of extents in the fixed-size IOBD. This */N/* value must keep the IOBD the same size as the DIOBM */a#define IOBD$K_LENGTH 264 /* Size #of fixed size IOBD including the fixed extents */N/* */X#define IOBD$M_NORESWAIT 1 /* No resource wait - return an error instead */X#define IOBD$M_EXT_IOBD 2 /* This is an external IOBD, not one which is */N/* embedded in an IRP. This flag is ignored on */U#define IOBD$M_INIT_IOBD 4 /* Initialize, do not validate, this IOBD. */N/* When using a stack IOBD # it's possible for */Z#define IOBD$M_PTE_STRIDE_1 8 /* When building the EXT list, step through the */N/* list of passed-in PTEs one by one no matter */##define IOBD$M_VALID_PARAM_FLAGS 15 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _iobd { __union {#pragma #__nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */T struct _ext *iobd$pq_extents; /* If the IOBD is INUSE, this pointer can */#else" unsigned __int64 iobd$pq_extents;#endifN/* be used to find the extents mapped by */N/* this IOBD, whether they are embedded */N/* or auxi #liary */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */S struct _iobd *iobd$pq_aux_iobd; /* Pointer to a secondary IOBD structure */#else# unsigned __int64 iobd$pq_aux_iobd;#endifN/* Valid if and only if IOBD$V_AUX_INUSE set */# } iobd$r_extents_aux_union;N # unsigned short int iobd$w_size; /* IOBD size in bytes */N unsigned char iobd$b_type; /* IOBD type, DYN$C_MISC */N unsigned char iobd$b_subtype; /* IOBD subtype, DYN$C_IOBD */S unsigned int iobd$il_byte_offset; /* This field may be made obsolete soon, */N/* but it has been useful debugging IOBD */N/* problems. A buffer's byte offset is */N/* always included in #the physical */N/* address in the 1st extent, but on */N/* architectures where PTEs are not used */N/* to describe a buffer and on which page */N/* size can vary, it's not very useful. */P unsigned int iobd$il_byte_count; /* Total number of bytes described by */N/* the extents. # */N unsigned int iobd$il_max_extent_count; /* Maximum number of extents */N unsigned int iobd$il_extent_count; /* Number of valid extents */X unsigned int iobd$il_extents_alloc_size; /* Number of bytes of pool allocated for */N/* the extents list - only valid if */N/* IOBD$IL_FLAGS.IOBD$M_AUX_EXTENTS */N/* is set. # */ __union {N unsigned int iobd$il_flags; /* Flag bits: */ __struct {U unsigned iobd$v_fill_0 : 2; /* 01:00 Avoid common fill pattern bits */N unsigned iobd$v_inuse : 1; /* 02 This IOBD is in use */U unsigned iobd$v_fill_3 : 1; /* 03 Avoid common fill pattern bits */o unsigned iobd$v_aux_extents : 1; /* 04 IOBD$PQ_EXTENTS points to an auxiliary extents list */^# unsigned iobd$v_aux_inuse : 1; /* ** IOBD$PS_AUX_IOBD points to secondary IOBD */U unsigned iobd$v_fill_5 : 1; /* 06:05 Avoid common fill pattern bits */[ unsigned iobd$v_rel_dealloc : 1; /* 07 Deallocate this IOBD on release */U unsigned iobd$v_fill_8 : 2; /* 09:08 Avoid common fill pattern bits */g unsigned iobd$v_by_pte : 1; /* 10 IOBD was filled by PTE, not VA (BOFF is valid) */N unsigned iobd$v_aux_io #bd : 1; /* ** This is an auxiliary IOBD */( unsigned iobd$v_fill_2_ : 4; } iobd$r_fill_1_; } iobd$r_fill_0_;r/* These flags are valid in IOBD$IL_FLAGS - they are not the same flags used in the FLAGS parameter (see below) */N unsigned int iobd$il_abcnt; /* Accumulated byte count */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __ #nomember_alignment#endif __union {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *iobd$pq_va; /* VA mapped by the extents */#else unsigned __int64 iobd$pq_va;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* #And set ptr size default to 64-bit pointers */N struct _pte *iobd$pq_pte; /* PTE used to map */#else unsigned __int64 iobd$pq_pte;#endif } iobd$r_va_pte_union;N/* Number of extents in the fixed-size IOBD. */N/* There's no reason for this constant to be */N/* used outside of this module - code should */N/* use the IOBD extent count and maximum # */N/* extent count fields, or use the IOBD size */N/* and HDRLEN to calculate a maximum extent */N/* count, but the management of guard extents */N/* makes extent management best left to the */N/* code in DIOBD.C. */N/* (or smaller), to avoids changes to the offsets of */N/* I #RP fields which follow it. */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {N EXT iobd$r_fixed_extents [9]; /* + 1 for a guard extent */#pragma __nomember_alignment __struct {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or# C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 iobd$iq_base_pa_vector [4]; /* Vector of PAs */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifP unsigned int iobd$il_base_length_vector [4]; /* Vector of lengths */" } iobd$r_base_extents;#pragma __nomember_a #lignment __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */4 unsigned __int64 *iobd$pq_aux_pa_vector;#else( unsigned __int64 iobd$pq_aux_pa_vector;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */4 # unsigned int *iobd$pq_aux_length_vector;#else, unsigned __int64 iobd$pq_aux_length_vector;#endif! } iobd$r_aux_extents;! } iobd$r_extents_overlay;N/* Bits defined in the flags parameter to routines which take one */N/* */N/* NOSVAPTE platforms such as X86, and the IOBD */N/* will be filled regardless of its location - */N/* this #bit is used to bypass sanity checks */N/* performed on SVAPTE platforms such as IA64 */N/* when filling a non-IRP-embedded IOBD. */N/* it to be reused as the routine which declares */N/* it is called repeatedly - the IOBD may retain */N/* enough context (type, subtype, size) to pass */N/* validation but still have been #corrupted as */N/* other fields on the stack were used, maybe */N/* for a call to a different routine. */N/* what the value of the architecture-specific */N/* constant PTE$C_PAGE_INCR is set to. This is */N/* to support unusual PTE lists such as those */N/* built by the Modified Page Writer. # */X/* These flags are valid when used in the flags parameter supported by some routines. */ } IOBD; #if !defined(__VAXC)@#define iobd$pq_extents iobd$r_extents_aux_union.iobd$pq_extentsB#define iobd$pq_aux_iobd iobd$r_extents_aux_union.iobd$pq_aux_iobd2#define iobd$il_flags iobd$r_fill_0_.iobd$il_flags?#define iobd$v_inuse iobd$r_fill_0_.iobd$r_fill_1_.iobd$v_inuseK#define iobd$v_aux_extents iobd$r_fill_0_.iobd$r_fill_1_.iobd$v_aux_extentsG#define iobd$v_aux_inuse i#obd$r_fill_0_.iobd$r_fill_1_.iobd$v_aux_inuseK#define iobd$v_rel_dealloc iobd$r_fill_0_.iobd$r_fill_1_.iobd$v_rel_deallocA#define iobd$v_by_pte iobd$r_fill_0_.iobd$r_fill_1_.iobd$v_by_pteE#define iobd$v_aux_iobd iobd$r_fill_0_.iobd$r_fill_1_.iobd$v_aux_iobd1#define iobd$pq_va iobd$r_va_pte_union.iobd$pq_va3#define iobd$pq_pte iobd$r_va_pte_union.iobd$pq_pteH#define iobd$r_fixed_extents iobd$r_extents_overlay.iobd$r_fixed_extentsF#define iobd$r_base_extents iobd$r_extents_overlay.iobd$r_ba #se_extentsI#define iobd$iq_base_pa_vector iobd$r_base_extents.iobd$iq_base_pa_vectorQ#define iobd$il_base_length_vector iobd$r_base_extents.iobd$il_base_length_vectorD#define iobd$r_aux_extents iobd$r_extents_overlay.iobd$r_aux_extentsF#define iobd$pq_aux_pa_vector iobd$r_aux_extents.iobd$pq_aux_pa_vectorN#define iobd$pq_aux_length_vector iobd$r_aux_extents.iobd$pq_aux_length_vector"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_S#IZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IOBDDEF_LOADED */ wwF[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential propriet#ary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** pr#oprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************* #*************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */F/* Source: 14-JUN-2019 15:58:38 $1$DGA8345:[LIB_H.SRC]IOCDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IOCDEF ***/#ifndef __IOCDEF_LOADED#define __IOCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Sta#ndard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#d#efine __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* $IOCDEF - flag bits used in I/O database search r#outines. */N/* */N/*- */#define IOC$M_PHY 0x1#define IOC$M_TYPE 0x2#define IOC$M_CLASS 0x4#define IOC$M_LOCAL 0x8#define IOC$M_EXISTS 0x10#define IOC$M_2P 0x20#define IOC$M_ANY 0x40#define IOC$M_MOUNT 0x80#define IOC$M_ALT 0x100#define IOC$M_NO_TRANS 0x200#define IOC$M_ALLOC 0x400#define IOC$M_DTN 0x800#defin #e IOC$M_NOLOCK 0x1000#define IOC$M_PAC 0x2000#define IOC$M_B4CREATE 0x4000R#define IOC$S_IOCDEF 2 /* Old size name, synonym for IOC$S_IOC */ typedef struct _ioc {N/* IOC$V_PHY must be bit 0!! */N unsigned ioc$v_phy : 1; /* physical device specified */N unsigned ioc$v_type : 1; /* device type name specified */N unsigned ioc$v_class : 1; /* allocation class present $ */N unsigned ioc$v_local : 1; /* search local devices only */N unsigned ioc$v_exists : 1; /* device exists */N unsigned ioc$v_2p : 1; /* device is on UCB secondary path */N unsigned ioc$v_any : 1; /* find any matching device */N unsigned ioc$v_mount : 1; /* find only mountable devices */N unsigned ioc$v_alt : 1; /* alternate UCB found */N unsigned ioc$v$_no_trans : 1; /* caller translated logical name */N unsigned ioc$v_alloc : 1; /* allocate mountable device */N unsigned ioc$v_dtn : 1; /* search for DDRed device */N unsigned ioc$v_nolock : 1; /* don't take out device lock */N unsigned ioc$v_pac : 1; /* This is a port allocation class */] unsigned ioc$v_b4create : 1; /* don't skip UCB$V_NO_ASSIGN or UCB$V_CDP devices */ unsigned ioc$v_fill_0_ : $ 1; } IOC;N/* */N/* */N/************************************************************************** */N/* Format of AGP Command Register as defined by AGP Spec V2.0 */N/************************************************************************** */N/* */#define $IOC$M_AGP_CMD_1X 0x1#define IOC$M_AGP_CMD_2X 0x2#define IOC$M_AGP_CMD_4X 0x4#define IOC$M_AGP_CMD_FW 0x10#define IOC$M_AGP_CMD_4G 0x20#define IOC$M_AGP_ENABLE 0x100#define IOC$M_AGP_CMD_SBA 0x200%#define IOC$M_AGP_RQ_DEPTH 0xFF000000 typedef struct _agpr_cmd {N unsigned ioc$v_agp_cmd_1x : 1; /* AGP RATE = 1 */N unsigned ioc$v_agp_cmd_2x : 1; /* AGP RATE = 2 */N unsigned ioc$v_agp_cmd_4x : 1; /* AGP RATE = 4 $ */N unsigned ioc$v_reserved1 : 1; /* RESERVED */N unsigned ioc$v_agp_cmd_fw : 1; /* AGP FASTWRITE */N unsigned ioc$v_agp_cmd_4g : 1; /* AGP ADDRESS > 4GIGABYTE */N unsigned ioc$v_reserved2 : 2; /* RESERVED */N unsigned ioc$v_agp_enable : 1; /* AGP ENABLE */N unsigned ioc$v_agp_cmd_sba : 1; /* SIDEBAND ADDRESS MECHANISM */N unsi$gned ioc$v_reserved3 : 14; /* RESERVED */N unsigned ioc$v_agp_rq_depth : 8; /* AGP REQUEST QUEUE DEPTH */ } AGPR_CMD;N/* */N/* */N/************************************************************************** */N/* Format of AGP Status Register as defined by AGP Spec V2.0 */N/*************** $*********************************************************** */N/* */#define IOC$M_AGP_STS_1X 0x1#define IOC$M_AGP_STS_2X 0x2#define IOC$M_AGP_STS_4X 0x4#define IOC$M_AGP_STS_FW 0x10#define IOC$M_AGP_STS_4G 0x20#define IOC$M_AGP_STS_SBA 0x200#define IOC$M_AGP_RQ 0xFF000000 typedef struct _agpr_sts {N unsigned ioc$v_agp_sts_1x : 1; /* AGP RATE = 1 */N unsigned ioc$v_agp_sts_2$x : 1; /* AGP RATE = 2 */N unsigned ioc$v_agp_sts_4x : 1; /* AGP RATE = 4 */N unsigned ioc$v_reserved1 : 1; /* RESERVED */N unsigned ioc$v_agp_sts_fw : 1; /* AGP FASTWRITE */N unsigned ioc$v_agp_sts_4g : 1; /* AGP ADDRESS > 4GIGABYTE */N unsigned ioc$v_reserved2 : 3; /* RESERVED */N unsigned ioc$v_agp_sts_sba : 1; /* SIDEBAND AD$DRESS MECHANISM */N unsigned ioc$v_reserved3 : 14; /* RESERVED */N unsigned ioc$v_agp_rq : 8; /* AGP REQUEST QUEUE DEPTH */ } AGPR_STS;N/* */N/* */N/************************************************************************** */N/* Function codes used by system routines ioc$read_io, ioc$wri $te_io */N/************************************************************************** */N/* */#define IOC$K_BYTE_LANED 1#define IOC$K_WORD_LANED 2#define IOC$K_LONGWORD 4#define IOC$K_QUADWORD 8#define IOC$K_BYTE 256#define IOC$K_WORD 512N/* */N/* */N/*********** $*************************************************************** */N/* Function codes used by system routine ioc$node_function */N/************************************************************************** */N/* */#define IOC$K_ENABLE_INTR 1#define IOC$K_DISABLE_INTR 2#define IOC$K_ENABLE_SG 3#define IOC$K_DISABLE_SG 4#define IOC$K_ENABLE_PAR 5#define IOC$K_DISABLE_PAR 6#define IOC$K_ENABLE_BLK $M 7#define IOC$K_DISABLE_BLKM 8#define IOC$K_ISSUE_EOI 9$#define IOC$K_ENABLE_DISTRIB_INTR 10%#define IOC$K_DISABLE_DISTRIB_INTR 11!#define IOC$K_AGP_READ_COMMAND 12"#define IOC$K_AGP_WRITE_COMMAND 13N/* */N/*------------------------------------------------------------------------- */N/* Multiple Vector Interrupt ioc$node_function codes */N/* $ */#define IOC$K_MVI_MASK_EVENT 14!#define IOC$K_MVI_UNMASK_EVENT 15$#define IOC$K_MVI_REQUEST_VECTORS 16#define IOC$K_MVI_MAP_VECTOR 17##define IOC$K_MVI_DISPATCH_EVENT 18$#define IOC$K_MVI_DISPATCH_VECTOR 19$#define IOC$K_MVI_DISPATCH_UNIQUE 20N/* */N/* */N/************************************************************* $************* */N/* Function codes used by system routine ioc$node_data */N/************************************************************************** */N/* */##define IOC$K_TURBO_SLOT_DENSE_PA 1$#define IOC$K_TURBO_SLOT_SPARSE_PA 2#define IOC$K_FBUS_INT_LOC 3#define IOC$K_EISA_IRQ 4#define IOC$K_EISA_DMA_CHAN 5!#define IOC$K_EISA_CONFIG_BLOCK 6#define IOC$K_EISA_MEM_CONFIG 7 #define IOC$K_ $LBUS_DEV_BLK_PTR 8#define IOC$K_EISA_IO_PORT 9 #define IOC$K_SCSI_CLK_PERIOD 10#define IOC$K_CPU_INT_MASK 11#define IOC$K_IO_PORT_RAD 12N/* */N/* */N/*------------------------------------------------------------------------- */N/* The following codes are actually used by the I/O space */N/* mapping routine IOC$MAP_IO. But, add$ them anyway to the */N/* IOC$NODE_DATA list as unique codes. */N/* */N/* Add synonyms for the IOC$MAP_IO function codes until the */N/* old ones are legislated out of existence. */N/* */##define IOC$K_IO_CSR_BYTE_ACCESS 11!#define IOC$K_BUS_IO_BYTE_GR $AN 11##define IOC$K_IO_CSR_LONG_ACCESS 12##define IOC$K_IO_MEM_BYTE_ACCESS 13"#define IOC$K_BUS_MEM_BYTE_GRAN 13##define IOC$K_IO_MEM_LONG_ACCESS 14#define IOC$K_BUS_MEM_DENSE 14N/* */N/* */N/*------------------------------------------------------------------------- */N/* The following code is used by drivers to request the address $*/N/* swizzle factor of an I/O bus. */N/* */##define IOC$K_IO_ADDRESS_SWIZZLE 15N/* */N/* */N/*------------------------------------------------------------------------- */N/* The following two are synonyms to request the bus address $ */N/* of the direct DMA window. */N/* */ #define IOC$K_DIRECT_DMA_BASE 16#define IOC$K_DDMA_BASE_BA 16N/* */N/* */N/*------------------------------------------------------------------------- */N/* Old code uses this fu$nction code to get the size of the */N/* direct dma window. If the system is a Galaxy system, */N/* and the minpfn is nonzero, this function code will */N/* return a size of zero, even if it isn't. See DDMA_WIN_SIZE */N/* below. */N/* */ #define IOC$K_DIRECT_DMA_SIZE 17N/* $ */N/* */N/*------------------------------------------------------------------------- */N/* add an ioc$node_data code for the ISA and PCI bus user parameter. */N/* also an ioc$node_data code for the dipl problem. */N/* these are added here so that it is easy to see what the next */N/* number to use will be. (could be added $ to node_data list above) */N/* */#define IOC$K_ISA_USER_PARAM 18#define IOC$K_PCI_USER_PARAM 18#define IOC$K_DEVICE_IPL 19N/* */N/*------------------------------------------------------------------------- */N/* Add an ioc$node_data code for monster windows */N/* $ */#define IOC$K_MONSTER_WINDOW 20N/* */N/* */N/*------------------------------------------------------------------------- */N/* This function code will always return the true size of */N/* the direct dma window. DDMA_BASE_PA will return the */N/* memory address of the direct dma window $, no longer to */N/* be presumed zero. */#define IOC$K_DDMA_WIN_SIZE 21#define IOC$K_DDMA_BASE_PA 22N/* */N/* */N/*------------------------------------------------------------------------- */N/* Add an ioc$node_data code for AGP capabilities mask */N/* T$he data returned is formatted to conform to the AGP STATUS longword */N/* found in the configuration header for the AGP bus. */#define IOC$K_AGP_CAP_MASK 23N/* */N/* */N/* */N/*------------------------------------------------------------------------- */$N/* This ioc$node_data function code will identify the system building block */N/* in which an adapter resides. Support for this code is currently */N/* planned only for Wildfire and Marvel class alpha systems. All others */N/* will return SS$_ILLIOFUNC. */N/* */#define IOC$K_IO_PORT_LOC 24N/* $ */N/* */N/*------------------------------------------------------------------------- */N/* This ioc$node_data function returns the translation offset quadword */N/* from the ADP for the specified CRB. If the ADP doesn't contain a */N/* valid translation offset, this function returns SS$_ILLIOFUNC. */N/* */#define IOC$K_IO_TRA$_OFFSET 25N/* */N/* */N/*------------------------------------------------------------------------- */N/* Return a pointer to the BUSARRAYENTRY */N/* */#define IOC$K_BUSARRAYENTRY 26N/* $ */N/* */N/*------------------------------------------------------------------------- */N/* MSI and Multiple Vector Interrupt ioc$node_data codes */N/* */#define IOC$K_INT_MECH 27#define IOC$K_MSIABS 28$#define IOC$K_MVI_DEV_VECTORS_REQ 29$#define IOC$K_MVI_SYS_VECTORS_GRA 30#define IOC$K_MVI_DATA 31"#define IO$C$K_MVI_PENDING_EVENT 32N/* */N/* */N/*------------------------------------------------------------------------- */N/* Return a mask of platform DMA capabilities as defined in ADPDEF */N/* */#define IOC$K_DMA_CAP_MASK 33N/* $ */N/* */N/*------------------------------------------------------------------------- */N/* Additional MSI and Multiple Vector Interrupt ioc$node_data codes */N/* */$#define IOC$K_MVI_USR_VECTORS_REQ 34N/* */N/* $ */N/*------------------------------------------------------------------------- */N/* A function code for IOC$NODE_DATA that drivers can call to see if */N/* their platform has a SG Map. (The only platforms that should fail with */N/* SS$_ITEMNOTFOUND are Sentosa, Kauai and Bucchaneer and later platforms). */N/* */#define IOC$K_SG_MAP_PRESENT 35N/*  $ */N/* */N/************************************************************************** */N/* Values returned by IOC$K_INT_MECH node_data call. */N/* These values are mutually exclusive. */N/************************************************************************** */N/* !$ */O#define IOC$K_INT_MECH_IOSAPIC 1 /* IOSAPIC delivery mechanism (IA64) */N#define IOC$K_INT_MECH_MSI 2 /* Standard MSI mechanism */N#define IOC$K_INT_MECH_MSIX 3 /* MSI-X mechanism */N#define IOC$K_INT_MECH_IOAPIC 4 /* IOAPIC delivery mechanism (x86) */N/* */N/* */"$N/************************************************************************** */N/* MVI_DATA and MVI_QENTRY */N/************************************************************************** */N/* */N/* These structures contain Data returned by calling ioc$node_function */N/* with the function code IOC$K_MSI_REQUEST_VECTORS. */N/* #$ */N/* The Hash Table created maps Interrupt Vectors and Vector Table */N/* Entries to ISR subroutines. */N/* */N/* The sequence of events that builds this tree is as follows. */N/* */N/* AT UNIT INIT TIME: $$ */N/* */N/* . A driver calls ioc$node_function for IOC$K_MVI_REQUEST_VECTORS */N/* */N/* . This call returns an MVI_DATA structure containing the number */N/* of interrupt vectors requested by the device, the number of */N/* vectors granted by the system, and a pointer to an array of %$*/N/* queue headers, one for each of the vectors granted, containing */N/* the vector. */N/* */N/* . The driver implements its policy for distributing the vectors */N/* granted to it by walking the mvi_array and for each vector */N/* in the array, the driver calls ioc$node_function again for */N/* IOC$K_MVI_MA&$P_FUNCTION with the Interrupt Vector, the Pointer */N/* to the Subroutine for handling the Interrupt, and, in the case */N/* of MSI-X, the Vector Table Entry Index. */N/* */N/* . In the case where the driver was granted fewer vectors than */N/* requested, and the driver must share the vectors with more */N/* than one ISR subroutine or Vector Tabl'$e Entry, a queue will */N/* be formed for each shared Interrupt Vector. */N/* */N/* AT RUN TIME */N/* */N/* . When an interrupt occurs, the driver will call ioc$node_function */N/* for IOC$K_MVI_DISPATCH_VECTOR, which will run down each ISR ($ */N/* subroutine in the queue for the given vector. The driver should */N/* fork and lower IPL before calling this function. */N/* */N/* . Before exiting, the driver should call ioc$node_function for */N/* IOC$K_MVI_PENDING to see if there are any other interrupts */N/* pending. This call will return the Vector Table Index of any */N/* pending in)$terrupts. */N/* */N/* . For each pending interrupt the driver should call */N/* ioc$node_function for IOC$K_MVI_DISPATCH_VTE in a loop */N/* until all pending interrupts have been handled. */N/* */N/* . Optionally, a driver can call ioc$no*$de_function with a code */N/* of IOC$K_MASK_VTE to mask interrupts from a Vector Table Entry */N/* or IOC$_UNMASK_VTE to unmask interrupts from a Vector Table */N/* Entry. */N/* */N/* . In the case where a driver wants to assign a different vector */N/* to a given Vector Table Entry, it will call ioc$node_function +$ */N/* for IOC$K_MVI_CHANGE_VECTOR with the new vector, the Vector */N/* Table Index, and the Pointer to the ISR subroutine. */N/* */N/* */N/* MVI_DATA */N/* +-------------+ */N/* | Req,$uested | */N/* +-------------+ */N/* | Granted | */N/* +-------------+ */N/* .------| Hash_Table | */N/* | +-------------+ */N/* | -$ */N/* | .-----------------------------------------------------------------. */N/* | | | */N/* | | .-------------------------------------------------------------. | */N/* | | | | | */N/* | | | MULTIPLE VECTOR INTERRUPT HASH TABLE | | */N/* | | | .$ | | */N/* | | | MVI_QENTRY MVI_QENTRY MVI_QENTRY | | */N/* | | | +-------------+ +-------------+ +-------------+ | | */N/* | | `->| Flink |----->| Flink |----->| Flink |>-' | */N/* `----->| |<--. | |<--. | |<---' */N/* | +-------------+ | +-------------+ | +-------------+ */N/* `---<| Blink | `--| Blink | `--| Blink | */N/* +--/$-----------+ +-------------+ +-------------+ */N/* | Vector | | Vector | | Vector | */N/* +-------------+ +-------------+ +-------------+ */N/* | CPU ID | | CPU ID | | CPU ID | */N/* +-------------+ +-------------+ +-------------+ */N/* | Func Ptr | | Func Ptr | | Func Ptr | */N/* +-------------+ +-------0$------+ +-------------+ */N/* | Vec Tab Idx | | Vec Tab Idx | | Vec Tab Idx | */N/* +-------------+ +-------------+ +-------------+ */N/* | */N/* v */N/* +-------------+ +-------------+ +-------------+ */N/* | Flink |----->| Flink |----->| Flink 1$ | */N/* | |<--. | |<--. | | */N/* +-------------+ | +-------------+ | +-------------+ */N/* | Blink | `--| Blink | `--| Blink | */N/* +-------------+ +-------------+ +-------------+ */N/* | Vector | | Vector | | Vector | */N/* +-------------+ +-------------+ +-------------+ */N/* |2$ CPU ID | | CPU ID | | CPU ID | */N/* +-------------+ +-------------+ +-------------+ */N/* | Func Ptr | | Func Ptr | | Func Ptr | */N/* +-------------+ +-------------+ +-------------+ */N/* | Vec Tab Idx | | Vec Tab Idx | | Vec Tab Idx | */N/* +-------------+ +-------------+ +-------------+ */N/* | 3$ */N/* v */N/* */N/************************************************************************** */N/* MVI_QENTRY Multiple Vector Interrupt Queue Entry */N/************************************************************************** */N/* 4$ */N/* MVI_QENTRY Maps an Interrupt Vector to an ISR subroutine, and, for */N/* MSIX, an MSIX Vector Table Entry. */N/* */N/* There will be one instance of these for every vector, and in the case */N/* of MSIX, every Vector Table Entry. Additionally, for MSI, there is an */N/* array of pointers to every MVI_QENTRY structure, one for each Vector */N/* Table Ent5$ry. */N/* */N/* Because it is possible that the OS will not return all the vectors */N/* that a device requests, vectors will have to be shared among the */N/* various ISR subroutines and, in the case of MSIX, associated Vector */N/* Table Entries. */N/* 6$ */N/* Vectors that hash to the same MVI_QENTRY index will be chained in a */N/* queue. For the sake of performance, we hope our hash algorithm is */N/* good enough to hash only one vector to each queue. */N/* */N/* When the ISR dispatch function runs down a given vector, it will be */N/* hashed to a chain in the MVI_QENTRY has table and the dispatc 7$h function */N/* will execute all the ISR subroutines in that chain. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mvi_qentry {#pragma __nomember_alignment( struct _mvi_qentry *mvi_qe$ps_flink;( struct _mvi_qentry *mvi_qe$ps_ 8$blink;N int (*mvi_qe$ps_function)(); /* ISR Subroutine */ int mvi_qe$l_vector; int mvi_qe$l_cpuid;N int mvi_qe$l_vte_index; /* Useful to MVI-X only */N/* */N/* Insure quadword alignment. */N/* */ } MVI_QENTRY; c#if !defined(__NOBASEA 9$LIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mvi_data {#pragma __nomember_alignmentN int mvi_data$l_requested; /* Number of vectors requested */N int mvi_data$l_granted; /* Number of vectors granted */N int *mvi_data$ps_vec_array; /* List of granted vectors */N int *mvi_data$ps_vte_array; :$/* Vector Table Entry Array */O struct _mvi_qentry *mvi_data$ps_hash_table; /* Pointer to the Hash Table */N int *mvi_data$ps_bitmap; /* Bitmap for hash table */N int mvi_data$l_bitmap_size; /* Size of Bitmap in bits */N/* */N/* Insure quadword alignment. */N/* ;$ */" char mvi_data$b_quad_fill [4]; } MVI_DATA; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IOCDEF_LOADED */ wwKG[UM/***************************************************************************/M/** <$ **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** =$ **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** >$ **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */H/* Source: 09-MAY-2001 10:58:38 $1$DGA8345:[LIB_H.SRC]IOCNTDEF.SDL;1 *//********************************************************************************************************************************/ ?$/*** MODULE $IOCNTDEF ***/#ifndef __IOCNTDEF_LOADED#define __IOCNTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#end@$if #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define IOCNT$K_LENGTH 308 /*LENGTH OF IOCNT A$ */N#define IOCNT$C_LENGTH 308 /*LENGTH OF IOCNT */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _iocnt {#pragma __nomember_alignmentN void *iocnt$ps_ptr_1; /* */N void *iocnt$ps_ptr_2; /* */N B$unsigned short int iocnt$w_size; /* Size of IOCNT, in bytes. */S unsigned char iocnt$b_type; /* Nonpaged pool packet type, DYN$C_MISC */W unsigned char iocnt$b_subtype; /* Nonpaged pool packet subtype, DYN$C_IOCNT */N/* */N/* Fast Path counters */N/* */N/* IOC_STD$INI C$TIATE counters: */ char iocnt$b_fill_0_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifO unsigned int iocnt$l_fp_port_cpu_io; /* On port CPU and new IO (dev UCB) */#pragma __nomember_alignmentN unsigned int iocnt$l_fp_io_queued; /* IRP queued to UCB IOQ (dev UCB) */N unsigned int iocnt$l_fD$p_ucb_queued; /* UCB was already queued (dev UCB) */R unsigned int iocnt$l_fp_other_ucb_queued; /* UCB queued to CPU db (dev UCB) */N unsigned int iocnt$l_fp_ipint; /* Sent IPINT (dev UCB) */S unsigned int iocnt$l_fp_queue_self; /* Queued UCB to local IPL8 FQ (dev UCB) */] unsigned int iocnt$l_fp_aff_fkb_inuse; /* Start I/O affinity FKB found inuse (dev UCB) */n unsigned int iocnt$l_fp_ucb_was_queued; /* Number of times UCB was already queued to port CPU (dev UCBE$) */N/* Port CPU Initiate counters: */O unsigned int iocnt$l_fp_bad_start_aff; /* Affinity has changed (dev UCB) */T unsigned int iocnt$l_fp_empty_ucb; /* UCB found with no start I/Os (dev UCB) */` unsigned int iocnt$l_fp_aff_io_found; /* Number of affinitized start I/Os found (dev UCB) */^ unsigned int iocnt$l_fp_aff_io_started; /* Number of Affinitized I/Os started (dev UCB) */N/* SCS$UNSTALLUCB counters: F$ */N unsigned int iocnt$l_fp_resumed_io; /* Number of resumed I/Os (dev UCB) */N/* Fast Send Message vetoes from various layers: */Z unsigned int iocnt$l_fp_sysap_sends; /* Number of SYSAP Send messages via Fast Path */h unsigned int iocnt$l_fp_sysap_nosend; /* Number of SYSAP denials for Fast Path send msg (dev UCB) */r unsigned int iocnt$l_fp_scs_nosend; /* Number of SCS denials for Fast Path send message (not used, see CDT) */n unsignG$ed int iocnt$l_fp_port_nosend; /* Number of port driver denials for Fast Path send msg (port UCB) */t unsigned int iocnt$l_fp_port_norbun; /* Number of times lack of RBUN denied for Fast Path send msg (port UCB) */N/* Receive Send Message vetoes from various layers: */Z unsigned int iocnt$l_fp_sysap_recvs; /* Number of SYSAP Send messages via Fast Path */k unsigned int iocnt$l_fp_sysap_norecv; /* Number of SYSAP denials for Fast Path receive msg (dev UCB) */u H$unsigned int iocnt$l_fp_scs_norecv; /* Number of SCS denials for Fast Path receive message (not used, see CDT) */q unsigned int iocnt$l_fp_port_norecv; /* Number of port driver denials for Fast Path receive msg (port UCB) */#/* RBUN pool activity: */Q unsigned int iocnt$l_fp_rbun_creates; /* Number of RBUN creates (port UCB) */S unsigned int iocnt$l_fp_rbun_deletes; /* Number of RBUN deletions (port UCB) */q unsigned int iocnt$l_fp_urgent_reclaims; /* Number of Urgent RI$eclamations of SCS non-paged pool (not used) */e unsigned int iocnt$l_fp_rbun_pool_cleanups; /* Number of times RBUN pool cleaned up (port UCB) */V unsigned int iocnt$l_fp_port_typ1; /* Number of Typ1 maps over port (port UCB) */N/* Port driver ISR counters: */T unsigned int iocnt$l_fp_interrupts; /* Number of device interrupts (port UCB) */Z unsigned int iocnt$l_fp_saved_forks; /* Number of Response Q forks saved (port UCB) */v unJ$signed int iocnt$l_fp_int_queued; /* Number of interrupt fork blocks queued locally or to port CPU (port UCB) */N/* Port driver fork routine counters: */k unsigned int iocnt$l_fp_bad_int_aff; /* Affinity has changed after device interrupt IPINT (port UCB) */j unsigned int iocnt$l_fp_port_forks; /* Number of times port response queue fork executes (port UCB) */r unsigned int iocnt$l_fp_port_fork_requeues; /* Number of times port response queue fork reK$queued (port UCB) */f unsigned int iocnt$l_fp_responses; /* Number of responses taken from response queue (port UCB) */N/* Miscellaneous port activities: */_ unsigned int iocnt$l_fp_repo_cdrp; /* Number of Repossess CDRP service calls (port UCB) */a unsigned int iocnt$l_fp_affinity_changes; /* Number of affinity changes on port (port UCB) */N/* IOC_STD$REQCOM_LOCAL counters: */_ unsigned int iocntL$$l_fp_reqcom; /* Number of Fast Path request completions (dev UCB) */N unsigned int iocnt$l_fp_reserved1; /* Reserved for Fast Path */N unsigned int iocnt$l_fp_reserved2; /* Reserved for Fast Path */N unsigned int iocnt$l_fp_reserved3; /* Reserved for Fast Path */N unsigned int iocnt$l_fp_reserved4; /* Reserved for Fast Path */N unsigned int iocnt$l_fp_reserved5; /* Reserved for Fast Path */N unsigned int iocnt$l_fp_reM$served6; /* Reserved for Fast Path */N unsigned int iocnt$l_fp_reserved7; /* Reserved for Fast Path */N unsigned int iocnt$l_fp_reserved8; /* Reserved for Fast Path */N unsigned int iocnt$l_fp_reserved9; /* Reserved for Fast Path */N unsigned int iocnt$l_fp_reserved10; /* Reserved for Fast Path */N/* */N/* Fast-IO counters N$ */N/* */N unsigned int iocnt$l_fiopcnt; /* IO_PERFORM calls for this UCB */R unsigned int iocnt$l_fiocopt; /* "Channel == same" optimization count */U unsigned int iocnt$l_fioffdt; /* Count of ACP$FASTIO_BLOCK routine calls */V unsigned int iocnt$l_fioecnt; /* Number of ACP$FASTIO_BLOCK error returns */Z unsigned int iocnt$l_fioelno; /* Source code line nuO$mber of last error return */Z unsigned int iocnt$l_fioepid; /* PID of process causing the last error return */N unsigned int iocnt$l_fiovioc; /* Fast-IO calls to VIO cache */N unsigned int iocnt$l_fiovioh; /* VIO cache hits */W unsigned int iocnt$l_fiocioc; /* VIO cache I/Os (complete or partial miss) */N/* FIOVIOC - FIOVIOH - FIOCIOC is count of */N/* I/Os to file not cached but we had to invoke P$ */N/* the VIOC before we knew we didn't want to. */Z unsigned int iocnt$l_fiorvop; /* Number of read virtual operations to driver */Z unsigned int iocnt$l_fiowvop; /* Number of write virtual operations to driver */Z unsigned int iocnt$l_fiorlop; /* Number of read logical operations to driver */Z unsigned int iocnt$l_fiowlop; /* Number of write logical operations to driver */W unsigned int iocnt$l_fiobkrdQ$; /* Total Blocks read (block == 512 bytes) */W unsigned int iocnt$l_fiobkwt; /* Total Blocks written (block == 512 bytes) */N unsigned int iocnt$l_fioffin; /* Count of fast-finishes */N unsigned int iocnt$l_fiocomp; /* PID/FPC of last fast-finish */U unsigned int iocnt$l_fiobcom; /* Count of fast-finishes for buffered I/O */S unsigned int iocnt$l_fiodcom; /* Count of fast-finishes for direct I/O */[ unsigned int iocnt$lR$_fioscom; /* Count of fast-finishes with system completion */X unsigned int iocnt$l_fiobiol; /* # bufio fast-finish longword buffer copies */X unsigned int iocnt$l_fiobioq; /* # bufio fast-finish quadword buffer copies */Y unsigned int iocnt$l_fiostqf; /* Count of fast-finish STQCs that failed when */N/* decrementing IOC and checking DIRP */Z unsigned int iocnt$l_fiodirp; /* Count of fast-finishes with deaccess packS$ets */Y unsigned int iocnt$l_fioirpe; /* Count of fast-finishes with IRPEs to delete */S unsigned int iocnt$l_fiouast; /* Count of fast-finishes with user ASTs */ char iocnt$b_fill_1_ [4]; } IOCNT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pra T$gma __standard #endif /* __IOCNTDEF_LOADED */ ww rG[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permissiU$on of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, InV$c. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */H/* Source: 19-MAY-2009 09:46:58 $1$DGA834 W$5:[LIB_H.SRC]IOGENDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IOGENDEF ***/#ifndef __IOGENDEF_LOADED#define __IOGENDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_sX$ize __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defin Y$ed(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Function codes and modifiers for the $LOAD_DRIVER server. */N/* */N#define IOGEN$_LOAD 1 /* LOAD a device driver */N#define IOGEN$_RELOAD 2 /* RELOAD a device driver */N#define IO Z$GEN$_CONNECT 3 /* CONNECT unit(s) */N#define IOGEN$_INIT_CTRL 4 /* call driver ctrl init routine */N#define IOGEN$_INIT_UNIT 5 /* call driver unit init routine */N#define IOGEN$_DELIVER 6 /* perform unit delivery */#define IOGEN$K_MINFCODE 1#define IOGEN$K_MAXFCODE 6#define IOGEN$M_NOWAIT 0x10000#define IOGEN$M_LDDB 0x20000!#define IOGEN$M_SYSDEVICE 0x40000#define IOGEN$M_NOINIT 0x80000W#define IO [$GEN$S_IOGENDEF 4 /* Old size name, synonym for IOGEN$S_IOGEN */ typedef struct _iogen { __union { __struct {S unsigned short int iogen$w_fcode; /* function codes in range 1-65535 */Q unsigned short int iogen$w_modifiers; /* 16 modifier bits reserved */& } iogen$r_fcode_structure; __struct {O unsigned iogen$v_fcode_fill : 16; /* must match FCODE size above */O unsigned iogen$v_nowait : 1; /* \$asynchronous operation requested */N unsigned iogen$v_lddb : 1; /* preparsed LDDB provided */N unsigned iogen$v_sysdevice : 1; /* this is the sysdevice device */R unsigned iogen$v_noinit : 1; /* don't call init bros (for ordering) */) unsigned iogen$v_fill_0_ : 4;$ } iogen$r_modifier_bits; } iogen$r_iogen_overlay; } IOGEN; #if !defined(__VAXC)Q#define iogen$w_fcode iogen$r_iogen_overlay.iogen$r_fcode_structure. ]$iogen$w_fcodeY#define iogen$w_modifiers iogen$r_iogen_overlay.iogen$r_fcode_structure.iogen$w_modifiersQ#define iogen$v_nowait iogen$r_iogen_overlay.iogen$r_modifier_bits.iogen$v_nowaitM#define iogen$v_lddb iogen$r_iogen_overlay.iogen$r_modifier_bits.iogen$v_lddbW#define iogen$v_sysdevice iogen$r_iogen_overlay.iogen$r_modifier_bits.iogen$v_sysdeviceQ#define iogen$v_noinit iogen$r_iogen_overlay.iogen$r_modifier_bits.iogen$v_noinit"#endif /* #if !defined(__VAXC) */ N#define IOGEN$_ADAPT^$ER 16 /* ADAPTER TR number */N#define IOGEN$_NOADAPTER 17 /* connect to the NULL adapter */N#define IOGEN$_CSR 18 /* magic number for CSR accesses */S#define IOGEN$_VECTOR 19 /* byte offset into SCB/ADP vector table */T#define IOGEN$_MAXUNITS 20 /* maximum # of units for this controller */N#define IOGEN$_SYSID 21 /* SCS system id of controller */N#define IOGEN$_SYSLOA_CRB 22 _$ /* address of preexisting CRB */N#define IOGEN$_UNIT 23 /* unit number for this device */S#define IOGEN$_NUMUNITS 24 /* number of consecutive units to create */Q#define IOGEN$_DELIVER_DATA 25 /* scratch space for unit delivery rtn */N#define IOGEN$_DDB 26 /* return the address of the DDB */N#define IOGEN$_CRB 27 /* return the address of the CRB */N#define IOGEN$_IDB 28 /* return `$the address of the IDB */N#define IOGEN$_UCB 29 /* return the address of the UCB */N#define IOGEN$_SB 30 /* return the address of the SB */N#define IOGEN$_NODE 31 /* set CRB$L_NODE field */k#define IOGEN$_ALLOCLS 32 /* Allocation class for DDB -- treated as port allocation class! */N#define IOGEN$_WWID 33 /* WWID value */N#define IOGEN$_DEVPATH 34 /* pat a$h information */N#define IOGEN$_DNP 35 /* Device Name Prefix; */N#define IOGEN$_SASADDRESS 36 /* SAS Address */N#define IOGEN$_SATA_END_DEVICE 37 /* SATA end device */N#define IOGEN$_IR_VOLUME 38 /* Integrated RAID volume */N#define IOGEN$_CISS_EXT_LUN 39 /* CISS external Lun */#define IOGEN$K_MINITEM 16#define IOGEN$K_MAXITEM 39#define IOGEN$M_b$AC_LOG 0x1#define IOGEN$M_AC_SCA 0x2#define IOGEN$M_AC_LAN 0x4#define IOGEN$M_AC_LOG_ALL 0x8#define IOGEN$M_AC_VERIFY 0x10 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _autocfg {#pragma __nomember_alignment __union {O unsigned int iogen$l_autocfg_flags; /* flags for IOGEN$AUTOCONFIGURE */ __struct {N c$ unsigned iogen$v_ac_log : 1; /* log progress of configuration */R unsigned iogen$v_ac_sca : 1; /* configure all SCA ports and friends */N unsigned iogen$v_ac_lan : 1; /* configure all LAN devices */P unsigned iogen$v_ac_log_all : 1; /* log even the "noisy" messages */f unsigned iogen$v_ac_verify : 1; /* Verify a REBUILD command (done with AUTOCONFIG code) */) unsigned iogen$v_fill_1_ : 3;$ } iogen$r_ac_flags_bit d$s; } iogen$r_autoconfig; } AUTOCFG; #if !defined(__VAXC)F#define iogen$l_autocfg_flags iogen$r_autoconfig.iogen$l_autocfg_flagsN#define iogen$v_ac_log iogen$r_autoconfig.iogen$r_ac_flags_bits.iogen$v_ac_logN#define iogen$v_ac_sca iogen$r_autoconfig.iogen$r_ac_flags_bits.iogen$v_ac_scaN#define iogen$v_ac_lan iogen$r_autoconfig.iogen$r_ac_flags_bits.iogen$v_ac_lanV#define iogen$v_ac_log_all iogen$r_autoconfig.iogen$r_ac_flags_bits.iogen$v_ac_log_allT#define iogen$v_ac_verify io e$gen$r_autoconfig.iogen$r_ac_flags_bits.iogen$v_ac_verify"#endif /* #if !defined(__VAXC) */ U#define IOGEN$S_ABMDEF 8 /* Old size name, synonym for IOGEN$S_ABM */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _abm {#pragma __nomember_alignmentN int iogen$il_abm_adp; /* ADP type code f$ */N int (*iogen$ps_abm_bsr)(); /* pointer to BSR's PD */ } ABM; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IOGENDEF_LOADED */ wwPG[UM/***************************************************g$************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/h$M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** i$ **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */K/* Source: 22-DEC-1993 12:41:27 $1$DGA8345:[LIB_H.SRC]IOHANDLEDEF.SDL;1 *//*********************************************************************************************** j$*********************************//*** MODULE $IOHANDLEDEF ***/#ifndef __IOHANDLEDEF_LOADED#define __IOHANDLEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set pk$tr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ l$ */N/* This data structure contains mapping information for I/O devices. */N/*- */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _iohandle {#pragma __nomember_alignment( struct _iohandle *iohandle$ps_m$flink;( struct _iohandle *iohandle$ps_blink;' unsigned short int iohandle$w_size;" unsigned char iohandle$b_type;% unsigned char iohandle$b_subtype;! unsigned int iohandle$l_boff; __union {# __int64 iohandle$q_base_va; __struct { __union {' int iohandle$l_base_va;) int iohandle$l_base_va_l;0 } iohandle$r_base_va_l__overlay;% int iohandle$l_base_va_h;( } iohandle$r_bn$ase_va_fields;% } iohandle$r_base_va_overlay;# __int64 iohandle$q_platform_pa; __int64 iohandle$q_bus_pa;, unsigned int iohandle$l_bus_region_size;/ unsigned int iohandle$l_mapped_region_size;' unsigned int iohandle$l_attributes; int iohandle$l_fill1 [1]; int iohandle$l_fill2 [2]; } IOHANDLE; #if !defined(__VAXC)H#define iohandle$q_base_va iohandle$r_base_va_overlay.iohandle$q_base_va#define iohandle$l_base_va iohandle$r_base_va_overlay.iohand o$le$r_base_va_fields.iohandle$r_base_va_l__overlay.iohandle$l_base_va#define iohandle$l_base_va_l iohandle$r_base_va_overlay.iohandle$r_base_va_fields.iohandle$r_base_va_l__overlay.iohandle$l_base_va_lf#define iohandle$l_base_va_h iohandle$r_base_va_overlay.iohandle$r_base_va_fields.iohandle$l_base_va_h"#endif /* #if !defined(__VAXC) */ !#define IOHANDLE$K_IOHANDLELEN 64 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported p$*/b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __IOHANDLEDEF_LOADED */ wwp5H[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packarq$d Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc.,r$ and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************* s$***********************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */H/* Source: 03-NOV-2017 12:42:16 $1$DGA8345:[LIB_H.SRC]IOVECDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $iovecdef ***/#ifndef __IOVECDEF_LOADED#define __IOVECDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignt$ment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif u$#ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define IOVEC$C_LENGTH 56 /* Length Of IOVEC */N#define IOVEC$K_LENGTH 56 /* Length Of IOVEC */  9#ifdef __cplusplus /* Define structure prototypes */struct _iovec;struct _btv$adp;struct _bdtab; #endif /* #ifdef __cplusplus */ typedef struct _iovec$r_iovec { __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *iovec$pq_flink; /* IOVEC forward link */#else! unsigned __int64 iovec$pq_flink;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size prag w$mas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif, struct _iovec *iovec$pl_flink_l;* unsigned int iovec$il_flink_h;# } iovec$r_flink_fields; } iovec$r_flink_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *iovec$pq_blink; x$ /* IOVEC backward link */#else! unsigned __int64 iovec$pq_blink;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif, struct _iovec *iovec$pl_blink_l;* unsigned int iovec$il_blink_h;# } iovec$r_blink_fields; } iovec$r_blink_overlay; __union {R#ifdef __INITIAL_POI y$NTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *iovec$pq_btadp_flink; /* BTADP forward link */#else' unsigned __int64 iovec$pq_btadp_flink;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif2 z$ struct _btadp *iovec$pl_btadp_flink_l;0 unsigned int iovec$il_btadp_flink_h;) } iovec$r_btadp_flink_fields;& } iovec$r_btadp_flink_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *iovec$pq_btadp_blink; /* BTADP backward link */#else' unsigned __int64 iovec$pq_btadp_blink;#e {$ndif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif2 struct _btadp *iovec$pl_btadp_blink_l;0 unsigned int iovec$il_btadp_blink_h;) } iovec$r_btadp_blink_fields;& } iovec$r_btadp_blink_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragm |$a __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *iovec$pq_bdtab; /* BDTAB address */#else! unsigned __int64 iovec$pq_bdtab;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endiff struct _bdtab *iovec$pl_bdtab_l; /* Pointer to BDTAB, a type defined }$ in BOOLIB, not LIB */* unsigned int iovec$il_bdtab_h;# } iovec$r_bdtab_fields; } iovec$r_bdtab_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *iovec$pq_image_base; /* Adr of image base */#else& unsigned __int64 iovec$pq_image_base;#endif __struct {R#ifdef __INITIAL ~$_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif( void *iovec$pl_image_base_l;/ unsigned int iovec$il_image_base_h;( } iovec$r_image_base_fields;% } iovec$r_image_base_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size d $efault to 64-bit pointers */N void *iovec$pq_btadp; /* Current BTADP adr */#else! unsigned __int64 iovec$pq_btadp;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif, struct _btadp *iovec$pl_btadp_l;* unsigned int iovec$il_btadp_h;# } iovec$r_btadp_fields; $} iovec$r_btadp_overlay; } IOVEC$R_IOVEC; #if !defined(__VAXC);#define iovec$pq_flink iovec$r_flink_overlay.iovec$pq_flinkT#define iovec$pl_flink_l iovec$r_flink_overlay.iovec$r_flink_fields.iovec$pl_flink_lT#define iovec$il_flink_h iovec$r_flink_overlay.iovec$r_flink_fields.iovec$il_flink_h;#define iovec$pq_blink iovec$r_blink_overlay.iovec$pq_blinkT#define iovec$pl_blink_l iovec$r_blink_overlay.iovec$r_blink_fields.iovec$pl_blink_lT#define iovec$il_blink_h iovec$r_blink_overlay.iov$ec$r_blink_fields.iovec$il_blink_hM#define iovec$pq_btadp_flink iovec$r_btadp_flink_overlay.iovec$pq_btadp_flinkl#define iovec$pl_btadp_flink_l iovec$r_btadp_flink_overlay.iovec$r_btadp_flink_fields.iovec$pl_btadp_flink_ll#define iovec$il_btadp_flink_h iovec$r_btadp_flink_overlay.iovec$r_btadp_flink_fields.iovec$il_btadp_flink_hM#define iovec$pq_btadp_blink iovec$r_btadp_blink_overlay.iovec$pq_btadp_blinkl#define iovec$pl_btadp_blink_l iovec$r_btadp_blink_overlay.iovec$r_btadp_blink_fields.iove$c$pl_btadp_blink_ll#define iovec$il_btadp_blink_h iovec$r_btadp_blink_overlay.iovec$r_btadp_blink_fields.iovec$il_btadp_blink_h;#define iovec$pq_bdtab iovec$r_bdtab_overlay.iovec$pq_bdtabT#define iovec$pl_bdtab_l iovec$r_bdtab_overlay.iovec$r_bdtab_fields.iovec$pl_bdtab_lT#define iovec$il_bdtab_h iovec$r_bdtab_overlay.iovec$r_bdtab_fields.iovec$il_bdtab_hJ#define iovec$pq_image_base iovec$r_image_base_overlay.iovec$pq_image_baseh#define iovec$pl_image_base_l iovec$r_image_base_overlay.iovec$r_i $mage_base_fields.iovec$pl_image_base_lh#define iovec$il_image_base_h iovec$r_image_base_overlay.iovec$r_image_base_fields.iovec$il_image_base_h;#define iovec$pq_btadp iovec$r_btadp_overlay.iovec$pq_btadpT#define iovec$pl_btadp_l iovec$r_btadp_overlay.iovec$r_btadp_fields.iovec$pl_btadp_lT#define iovec$il_btadp_h iovec$r_btadp_overlay.iovec$r_btadp_fields.iovec$il_btadp_h"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEI#pragma __required_pointer_size __save /* Save cu$rrent pointer size */D#pragma __required_pointer_size __long /* Pointers are 64-bit */Ntypedef struct _iovec$r_iovec * IOVEC_PQ; /* Pointer to an IOVEC structure */\typedef struct _iovec$r_iovec ** IOVEC_PPQ; /* Pointer to a pointer to an IOVEC structure */E#pragma __required_pointer_size __short /* Pointers are 32-bit */Ntypedef struct _iovec$r_iovec * IOVEC_PL; /* Pointer to an IOVEC structure */\typedef struct _iovec$r_iovec ** IOVEC_PPL; /* Pointer to a pointer to an IOVEC stru $cture */P#pragma __required_pointer_size __restore /* Return to previous pointer size */#else"typedef unsigned __int64 IOVEC_PQ;#typedef unsigned __int64 IOVEC_PPQ;"typedef unsigned __int32 IOVEC_PL;#typedef unsigned __int32 IOVEC_PPL;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr siz$e */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IOVECDEF_LOADED */ ww\H[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed t$o anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/$M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 $ */P/* Source: 13-MAY-1993 14:31:56 $1$DGA8345:[LIB_H.SRC]IO_ROUTINES_DATA.SDL;1 *//********************************************************************************************************************************/"/*** MODULE $IO_ROUTINES_DATA ***/!#ifndef __IO_ROUTINES_DATA_LOADED##define __IO_ROUTINES_DATA_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_S$IZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#els$e#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DEFINITION OF IO_ROUTINES IMAGE LOCAL DATA */N/*- */ "typedef struct _io_routines_data {N void *ioc_gl_psfl; /* I$/O POST QUEUE FORWARD LINK */N void *ioc_gl_psbl; /* I/O POST QUEUE BACKWARD LINK */ } IO_ROUTINES_DATA; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard &#endif /* __IO_ROUTINES_DATA_LOADED */ wwFI[UM/*$**************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett$-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. $ **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */I/* Source: 19-FEB-2015 11:04:59 $1$DGA8345:[LIB_H.SRC]IPFINSDEF.SDL;1 *//*********************************************** $*********************************************************************************//*** MODULE $IPFINSDEF ***/#ifndef __IPFINSDEF_LOADED#define __IPFINSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __re$quired_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#e $ndif#endif N/* */I/* BUNDLE: Overall format of a 128-bit instruction bundle */N/* */#define IPFINS$M_TEMPLATE 0x1F&#define IPFINS$M_SLOT_0 0x3FFFFFFFFFE0*#define IPFINS$M_SLOT_1 0xFFFFC00000000000#define IPFINS$M_SLOT_2 0x0 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'$#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _bundle {#pragma __nomember_alignment __union { __struct {+ unsigned ipfins$v_template : 5;#if defined(__VAXC), unsigned ipfins$v_slot_0_1 : 32;+ unsigned ipfins$v_slot_0_2 : 9;#else2 unsigned __int64 ipfins$v_slot_0 : 41;#endif#if defined(__VAXC), unsigned ipfins$v_slot_1_1 : 32;+ unsigned ipfins$$v_slot_1_2 : 9;#else2 unsigned __int64 ipfins$v_slot_1 : 41;#endif#if defined(__VAXC), unsigned ipfins$v_slot_2_1 : 32;+ unsigned ipfins$v_slot_2_2 : 9;#else2 unsigned __int64 ipfins$v_slot_2 : 41;#endif$ } ipfins$r_bundle_slots; __struct {/ unsigned __int64 ipfins$q_bundle_l;/ unsigned __int64 ipfins$q_bundle_h;$ } ipfins$r_bundle_quads; } ipfins$r_bundle_union; } $BUNDLE; #if !defined(__VAXC)W#define ipfins$v_template ipfins$r_bundle_union.ipfins$r_bundle_slots.ipfins$v_templateS#define ipfins$v_slot_0 ipfins$r_bundle_union.ipfins$r_bundle_slots.ipfins$v_slot_0S#define ipfins$v_slot_1 ipfins$r_bundle_union.ipfins$r_bundle_slots.ipfins$v_slot_1S#define ipfins$v_slot_2 ipfins$r_bundle_union.ipfins$r_bundle_slots.ipfins$v_slot_2W#define ipfins$q_bundle_l ipfins$r_bundle_union.ipfins$r_bundle_quads.ipfins$q_bundle_lW#define ipfins$q_bundle_h ipfins $$r_bundle_union.ipfins$r_bundle_quads.ipfins$q_bundle_h"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Ltypedef struct _bundle * BUNDLE_PQ; /* Pointer to a bundle structure */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else#typedef unsigned __int64 BUNDLE_PQ;##endif /* __INIT $IAL_POINTER_SIZE */N/* */I/* SLOT: Each slot has an opcode and some operands */N/* */&#define IPFINS$M_OPERANDS 0x1FFFFFFFFF%#define IPFINS$M_OPCODE 0x1E000000000-#define IPFINS$M_SLOT_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nome$mber_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _slot {#pragma __nomember_alignment __union { __struct {#if defined(__VAXC). unsigned ipfins$v_operands_1 : 32;- unsigned ipfins$v_operands_2 : 5;#else4 unsigned __int64 ipfins$v_operands : 37;#endif) unsigned ipfins$v_opcode : 4;- unsigned ipfins$v_slot_fill : 23;! } ipfins$r_slot_0_63;- unsigned __int64 $ ipfins$q_total_slot; } ipfins$r_slot_union; } SLOT; #if !defined(__VAXC)R#define ipfins$v_operands ipfins$r_slot_union.ipfins$r_slot_0_63.ipfins$v_operandsN#define ipfins$v_opcode ipfins$r_slot_union.ipfins$r_slot_0_63.ipfins$v_opcodeC#define ipfins$q_total_slot ipfins$r_slot_union.ipfins$q_total_slot"#endif /* #if !defined(__VAXC) */ N/* */I/* A-Unit Formats $ */N/* */N/* */I/* A1: Integer ALU - Register-Register */N/* */#define IPFINS$M_A1_QP 0x3F#define IPFINS$M_A1_R1 0x1FC0#define IPFINS$M_A1_R2 0xFE000 #define IPFINS$M_A1_R3 0x7F00000"#define IPFINS$M_A1_X2B 0x18000000"#defin$e IPFINS$M_A1_X4 0x1E0000000"#define IPFINS$M_A1_VE 0x200000000##define IPFINS$M_A1_X2A 0xC00000000##define IPFINS$M_A1_36 0x1000000000(#define IPFINS$M_A1_OPCODE 0x1E000000000+#define IPFINS$M_A1_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _a1_format {#pragma __nomember_alignment __union { $ __struct {( unsigned ipfins$v_a1_qp : 6;( unsigned ipfins$v_a1_r1 : 7;( unsigned ipfins$v_a1_r2 : 7;( unsigned ipfins$v_a1_r3 : 7;) unsigned ipfins$v_a1_x2b : 2;( unsigned ipfins$v_a1_x4 : 4;( unsigned ipfins$v_a1_ve : 1;) unsigned ipfins$v_a1_x2a : 2;( unsigned ipfins$v_a1_36 : 1;, unsigned ipfins$v_a1_opcode : 4;+ unsigned ipfins$v_a1_fill : 23; } ip $fins$r_a1_0_63;% unsigned __int64 ipfins$q_a1; } ipfins$r_a1; } A1_FORMAT; #if !defined(__VAXC)B#define ipfins$v_a1_qp ipfins$r_a1.ipfins$r_a1_0_63.ipfins$v_a1_qpB#define ipfins$v_a1_r1 ipfins$r_a1.ipfins$r_a1_0_63.ipfins$v_a1_r1B#define ipfins$v_a1_r2 ipfins$r_a1.ipfins$r_a1_0_63.ipfins$v_a1_r2B#define ipfins$v_a1_r3 ipfins$r_a1.ipfins$r_a1_0_63.ipfins$v_a1_r3D#define ipfins$v_a1_x2b ipfins$r_a1.ipfins$r_a1_0_63.ipfins$v_a1_x2bB#define ipfins$v_a1_x4 ipfins$r_a1.ipf $ins$r_a1_0_63.ipfins$v_a1_x4B#define ipfins$v_a1_ve ipfins$r_a1.ipfins$r_a1_0_63.ipfins$v_a1_veD#define ipfins$v_a1_x2a ipfins$r_a1.ipfins$r_a1_0_63.ipfins$v_a1_x2aB#define ipfins$v_a1_36 ipfins$r_a1.ipfins$r_a1_0_63.ipfins$v_a1_36J#define ipfins$v_a1_opcode ipfins$r_a1.ipfins$r_a1_0_63.ipfins$v_a1_opcode+#define ipfins$q_a1 ipfins$r_a1.ipfins$q_a1"#endif /* #if !defined(__VAXC) */ N/* */I/* A2: Shift Left and Add $ */N/* */#define IPFINS$M_A2_QP 0x3F#define IPFINS$M_A2_R1 0x1FC0#define IPFINS$M_A2_R2 0xFE000 #define IPFINS$M_A2_R3 0x7F00000##define IPFINS$M_A2_CT2D 0x18000000"#define IPFINS$M_A2_X4 0x1E0000000"#define IPFINS$M_A2_VE 0x200000000##define IPFINS$M_A2_X2A 0xC00000000##define IPFINS$M_A2_36 0x1000000000(#define IPFINS$M_A2_OPCODE 0x1E000000000+#define IPFINS$M_A2_FI$LL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _a2_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_a2_qp : 6;( unsigned ipfins$v_a2_r1 : 7;( unsigned ipfins$v_a2_r2 : 7;( unsigned ipfins$v_a2_r3 : 7;* unsigned i$pfins$v_a2_ct2d : 2;( unsigned ipfins$v_a2_x4 : 4;( unsigned ipfins$v_a2_ve : 1;) unsigned ipfins$v_a2_x2a : 2;( unsigned ipfins$v_a2_36 : 1;, unsigned ipfins$v_a2_opcode : 4;+ unsigned ipfins$v_a2_fill : 23; } ipfins$r_a2_0_63;% unsigned __int64 ipfins$q_a2; } ipfins$r_a2; } A2_FORMAT; #if !defined(__VAXC)B#define ipfins$v_a2_qp ipfins$r_a2.ipfins$r_a2_0_63.ipfins$v_a2_qpB#define ipfi$ns$v_a2_r1 ipfins$r_a2.ipfins$r_a2_0_63.ipfins$v_a2_r1B#define ipfins$v_a2_r2 ipfins$r_a2.ipfins$r_a2_0_63.ipfins$v_a2_r2B#define ipfins$v_a2_r3 ipfins$r_a2.ipfins$r_a2_0_63.ipfins$v_a2_r3F#define ipfins$v_a2_ct2d ipfins$r_a2.ipfins$r_a2_0_63.ipfins$v_a2_ct2dB#define ipfins$v_a2_x4 ipfins$r_a2.ipfins$r_a2_0_63.ipfins$v_a2_x4B#define ipfins$v_a2_ve ipfins$r_a2.ipfins$r_a2_0_63.ipfins$v_a2_veD#define ipfins$v_a2_x2a ipfins$r_a2.ipfins$r_a2_0_63.ipfins$v_a2_x2aB#define ipfins$v_a2_36 ipfins$r_a2.i $pfins$r_a2_0_63.ipfins$v_a2_36J#define ipfins$v_a2_opcode ipfins$r_a2.ipfins$r_a2_0_63.ipfins$v_a2_opcode+#define ipfins$q_a2 ipfins$r_a2.ipfins$q_a2"#endif /* #if !defined(__VAXC) */ N/* */I/* A3: Integer ALU - Immediate(8)-Register */N/* */#define IPFINS$M_A3_QP 0x3F#define IPFINS$M_A3_R1 0x1FC0!#define IPFINS$$M_A3_IMM7B 0xFE000 #define IPFINS$M_A3_R3 0x7F00000"#define IPFINS$M_A3_X2B 0x18000000"#define IPFINS$M_A3_X4 0x1E0000000"#define IPFINS$M_A3_VE 0x200000000##define IPFINS$M_A3_X2A 0xC00000000"#define IPFINS$M_A3_S 0x1000000000(#define IPFINS$M_A3_OPCODE 0x1E000000000+#define IPFINS$M_A3_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_align$ment#endiftypedef struct _a3_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_a3_qp : 6;( unsigned ipfins$v_a3_r1 : 7;+ unsigned ipfins$v_a3_imm7b : 7;( unsigned ipfins$v_a3_r3 : 7;) unsigned ipfins$v_a3_x2b : 2;( unsigned ipfins$v_a3_x4 : 4;( unsigned ipfins$v_a3_ve : 1;) unsigned ipfins$v_a3_x2a : 2;% signed ipfins$v_a3_s : 1;, $ unsigned ipfins$v_a3_opcode : 4;+ unsigned ipfins$v_a3_fill : 23; } ipfins$r_a3_0_63;% unsigned __int64 ipfins$q_a3; } ipfins$r_a3; } A3_FORMAT; #if !defined(__VAXC)B#define ipfins$v_a3_qp ipfins$r_a3.ipfins$r_a3_0_63.ipfins$v_a3_qpB#define ipfins$v_a3_r1 ipfins$r_a3.ipfins$r_a3_0_63.ipfins$v_a3_r1H#define ipfins$v_a3_imm7b ipfins$r_a3.ipfins$r_a3_0_63.ipfins$v_a3_imm7bB#define ipfins$v_a3_r3 ipfins$r_a3.ipfins$r_a3_0_63.ipfins$v_a3_r3D#def $ine ipfins$v_a3_x2b ipfins$r_a3.ipfins$r_a3_0_63.ipfins$v_a3_x2bB#define ipfins$v_a3_x4 ipfins$r_a3.ipfins$r_a3_0_63.ipfins$v_a3_x4B#define ipfins$v_a3_ve ipfins$r_a3.ipfins$r_a3_0_63.ipfins$v_a3_veD#define ipfins$v_a3_x2a ipfins$r_a3.ipfins$r_a3_0_63.ipfins$v_a3_x2a@#define ipfins$v_a3_s ipfins$r_a3.ipfins$r_a3_0_63.ipfins$v_a3_sJ#define ipfins$v_a3_opcode ipfins$r_a3.ipfins$r_a3_0_63.ipfins$v_a3_opcode+#define ipfins$q_a3 ipfins$r_a3.ipfins$q_a3"#endif /* #if !defined(__VAXC) */ N/* $ */I/* A4: Add Immediate(14) */N/* */#define IPFINS$M_A4_QP 0x3F#define IPFINS$M_A4_R1 0x1FC0!#define IPFINS$M_A4_IMM7B 0xFE000 #define IPFINS$M_A4_R3 0x7F00000%#define IPFINS$M_A4_IMM6D 0x1F8000000"#define IPFINS$M_A4_VE 0x200000000##define IPFINS$M_A4_X2A 0xC00000000"#define IPFINS$M_A4_S 0x100000$0000(#define IPFINS$M_A4_OPCODE 0x1E000000000+#define IPFINS$M_A4_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _a4_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_a4_qp : 6;( unsigned ipfins$v_a4_r1 : 7;+ unsigned ipfins$v_a4_imm$7b : 7;( unsigned ipfins$v_a4_r3 : 7;+ unsigned ipfins$v_a4_imm6d : 6;( unsigned ipfins$v_a4_ve : 1;) unsigned ipfins$v_a4_x2a : 2;% signed ipfins$v_a4_s : 1;, unsigned ipfins$v_a4_opcode : 4;+ unsigned ipfins$v_a4_fill : 23; } ipfins$r_a4_0_63;% unsigned __int64 ipfins$q_a4; } ipfins$r_a4; } A4_FORMAT; #if !defined(__VAXC)B#define ipfins$v_a4_qp ipfins$r_a4.ipfins$r_a4_0$_63.ipfins$v_a4_qpB#define ipfins$v_a4_r1 ipfins$r_a4.ipfins$r_a4_0_63.ipfins$v_a4_r1H#define ipfins$v_a4_imm7b ipfins$r_a4.ipfins$r_a4_0_63.ipfins$v_a4_imm7bB#define ipfins$v_a4_r3 ipfins$r_a4.ipfins$r_a4_0_63.ipfins$v_a4_r3H#define ipfins$v_a4_imm6d ipfins$r_a4.ipfins$r_a4_0_63.ipfins$v_a4_imm6dB#define ipfins$v_a4_ve ipfins$r_a4.ipfins$r_a4_0_63.ipfins$v_a4_veD#define ipfins$v_a4_x2a ipfins$r_a4.ipfins$r_a4_0_63.ipfins$v_a4_x2a@#define ipfins$v_a4_s ipfins$r_a4.ipfins$r_a4_0_63.ipfins$v_a4_s $J#define ipfins$v_a4_opcode ipfins$r_a4.ipfins$r_a4_0_63.ipfins$v_a4_opcode+#define ipfins$q_a4 ipfins$r_a4.ipfins$q_a4"#endif /* #if !defined(__VAXC) */ N/* */I/* A5: Add Immediate(22) */N/* */#define IPFINS$M_A5_QP 0x3F#define IPFINS$M_A5_R1 0x1FC0!#define IPFINS$M_A5_IMM7B 0xFE000#define $IPFINS$M_A5_R3 0x300000##define IPFINS$M_A5_IMM5C 0x7C00000%#define IPFINS$M_A5_IMM9D 0xFF8000000"#define IPFINS$M_A5_S 0x1000000000(#define IPFINS$M_A5_OPCODE 0x1E000000000+#define IPFINS$M_A5_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _a5_format {#pragma __nomember_alignment __union { $__struct {( unsigned ipfins$v_a5_qp : 6;( unsigned ipfins$v_a5_r1 : 7;+ unsigned ipfins$v_a5_imm7b : 7;( unsigned ipfins$v_a5_r3 : 2;+ unsigned ipfins$v_a5_imm5c : 5;+ unsigned ipfins$v_a5_imm9d : 9;% signed ipfins$v_a5_s : 1;, unsigned ipfins$v_a5_opcode : 4;+ unsigned ipfins$v_a5_fill : 23; } ipfins$r_a5_0_63;% unsigned __int64 ipfins$q_a5; } ipfins$r_a5; $ } A5_FORMAT; #if !defined(__VAXC)B#define ipfins$v_a5_qp ipfins$r_a5.ipfins$r_a5_0_63.ipfins$v_a5_qpB#define ipfins$v_a5_r1 ipfins$r_a5.ipfins$r_a5_0_63.ipfins$v_a5_r1H#define ipfins$v_a5_imm7b ipfins$r_a5.ipfins$r_a5_0_63.ipfins$v_a5_imm7bB#define ipfins$v_a5_r3 ipfins$r_a5.ipfins$r_a5_0_63.ipfins$v_a5_r3H#define ipfins$v_a5_imm5c ipfins$r_a5.ipfins$r_a5_0_63.ipfins$v_a5_imm5cH#define ipfins$v_a5_imm9d ipfins$r_a5.ipfins$r_a5_0_63.ipfins$v_a5_imm9d@#define ipfins$v_a5_s ipfins$r_a5. $ipfins$r_a5_0_63.ipfins$v_a5_sJ#define ipfins$v_a5_opcode ipfins$r_a5.ipfins$r_a5_0_63.ipfins$v_a5_opcode+#define ipfins$q_a5 ipfins$r_a5.ipfins$q_a5"#endif /* #if !defined(__VAXC) */ N/* */I/* A6: Integer Compare - Register-Register */N/* */#define IPFINS$M_A6_QP 0x3F#define IPFINS$M_A6_P1 0xFC0#define IPFINS$M$_A6_C 0x1000#define IPFINS$M_A6_R2 0xFE000 #define IPFINS$M_A6_R3 0x7F00000"#define IPFINS$M_A6_P2 0x1F8000000"#define IPFINS$M_A6_TA 0x200000000"#define IPFINS$M_A6_X2 0xC00000000##define IPFINS$M_A6_TB 0x1000000000(#define IPFINS$M_A6_OPCODE 0x1E000000000+#define IPFINS$M_A6_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif$typedef struct _a6_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_a6_qp : 6;( unsigned ipfins$v_a6_p1 : 6;' unsigned ipfins$v_a6_c : 1;( unsigned ipfins$v_a6_r2 : 7;( unsigned ipfins$v_a6_r3 : 7;( unsigned ipfins$v_a6_p2 : 6;( unsigned ipfins$v_a6_ta : 1;( unsigned ipfins$v_a6_x2 : 2;( unsigned ipfins$v_a6_tb : 1;, unsigned ipfins$ $v_a6_opcode : 4;+ unsigned ipfins$v_a6_fill : 23; } ipfins$r_a6_0_63;% unsigned __int64 ipfins$q_a6; } ipfins$r_a6; } A6_FORMAT; #if !defined(__VAXC)B#define ipfins$v_a6_qp ipfins$r_a6.ipfins$r_a6_0_63.ipfins$v_a6_qpB#define ipfins$v_a6_p1 ipfins$r_a6.ipfins$r_a6_0_63.ipfins$v_a6_p1@#define ipfins$v_a6_c ipfins$r_a6.ipfins$r_a6_0_63.ipfins$v_a6_cB#define ipfins$v_a6_r2 ipfins$r_a6.ipfins$r_a6_0_63.ipfins$v_a6_r2B#define ipfins$v_a6_r3 ipfins$ $r_a6.ipfins$r_a6_0_63.ipfins$v_a6_r3B#define ipfins$v_a6_p2 ipfins$r_a6.ipfins$r_a6_0_63.ipfins$v_a6_p2B#define ipfins$v_a6_ta ipfins$r_a6.ipfins$r_a6_0_63.ipfins$v_a6_taB#define ipfins$v_a6_x2 ipfins$r_a6.ipfins$r_a6_0_63.ipfins$v_a6_x2B#define ipfins$v_a6_tb ipfins$r_a6.ipfins$r_a6_0_63.ipfins$v_a6_tbJ#define ipfins$v_a6_opcode ipfins$r_a6.ipfins$r_a6_0_63.ipfins$v_a6_opcode+#define ipfins$q_a6 ipfins$r_a6.ipfins$q_a6"#endif /* #if !defined(__VAXC) */ N/* $ */I/* A7: Integer Compare to Zero - Register */N/* */#define IPFINS$M_A7_QP 0x3F#define IPFINS$M_A7_P1 0xFC0#define IPFINS$M_A7_C 0x1000 #define IPFINS$M_A7_ZERO 0xFE000 #define IPFINS$M_A7_R3 0x7F00000"#define IPFINS$M_A7_P2 0x1F8000000"#define IPFINS$M_A7_TA 0x200000000"#define IPFINS$M_A7_X2 0xC00000000##define IPFINS$M_A7_TB 0x1000000000($#define IPFINS$M_A7_OPCODE 0x1E000000000+#define IPFINS$M_A7_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _a7_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_a7_qp : 6;( unsigned ipfins$v_a7_p1 : 6;' unsigned ipfins$v_a7_c : 1;*$ unsigned ipfins$v_a7_zero : 7;( unsigned ipfins$v_a7_r3 : 7;( unsigned ipfins$v_a7_p2 : 6;( unsigned ipfins$v_a7_ta : 1;( unsigned ipfins$v_a7_x2 : 2;( unsigned ipfins$v_a7_tb : 1;, unsigned ipfins$v_a7_opcode : 4;+ unsigned ipfins$v_a7_fill : 23; } ipfins$r_a7_0_63;% unsigned __int64 ipfins$q_a7; } ipfins$r_a7; } A7_FORMAT; #if !defined(__VAXC)B#define ipfins$v_a$7_qp ipfins$r_a7.ipfins$r_a7_0_63.ipfins$v_a7_qpB#define ipfins$v_a7_p1 ipfins$r_a7.ipfins$r_a7_0_63.ipfins$v_a7_p1@#define ipfins$v_a7_c ipfins$r_a7.ipfins$r_a7_0_63.ipfins$v_a7_cF#define ipfins$v_a7_zero ipfins$r_a7.ipfins$r_a7_0_63.ipfins$v_a7_zeroB#define ipfins$v_a7_r3 ipfins$r_a7.ipfins$r_a7_0_63.ipfins$v_a7_r3B#define ipfins$v_a7_p2 ipfins$r_a7.ipfins$r_a7_0_63.ipfins$v_a7_p2B#define ipfins$v_a7_ta ipfins$r_a7.ipfins$r_a7_0_63.ipfins$v_a7_taB#define ipfins$v_a7_x2 ipfins$r_a7.ipfins$r_a7 $_0_63.ipfins$v_a7_x2B#define ipfins$v_a7_tb ipfins$r_a7.ipfins$r_a7_0_63.ipfins$v_a7_tbJ#define ipfins$v_a7_opcode ipfins$r_a7.ipfins$r_a7_0_63.ipfins$v_a7_opcode+#define ipfins$q_a7 ipfins$r_a7.ipfins$q_a7"#endif /* #if !defined(__VAXC) */ N/* */I/* A8: Integer Compare - Immediate-Register */N/* */#define IPFINS$M_A$8_QP 0x3F#define IPFINS$M_A8_P1 0xFC0#define IPFINS$M_A8_C 0x1000!#define IPFINS$M_A8_IMM7B 0xFE000 #define IPFINS$M_A8_R3 0x7F00000"#define IPFINS$M_A8_P2 0x1F8000000"#define IPFINS$M_A8_TA 0x200000000"#define IPFINS$M_A8_X2 0xC00000000"#define IPFINS$M_A8_S 0x1000000000(#define IPFINS$M_A8_OPCODE 0x1E000000000+#define IPFINS$M_A8_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignme$nt __quadword#else#pragma __nomember_alignment#endiftypedef struct _a8_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_a8_qp : 6;( unsigned ipfins$v_a8_p1 : 6;' unsigned ipfins$v_a8_c : 1;+ unsigned ipfins$v_a8_imm7b : 7;( unsigned ipfins$v_a8_r3 : 7;( unsigned ipfins$v_a8_p2 : 6;( unsigned ipfins$v_a8_ta : 1;( unsigned ipfins$v_a8_x2 : 2;% $ signed ipfins$v_a8_s : 1;, unsigned ipfins$v_a8_opcode : 4;+ unsigned ipfins$v_a8_fill : 23; } ipfins$r_a8_0_63;% unsigned __int64 ipfins$q_a8; } ipfins$r_a8; } A8_FORMAT; #if !defined(__VAXC)B#define ipfins$v_a8_qp ipfins$r_a8.ipfins$r_a8_0_63.ipfins$v_a8_qpB#define ipfins$v_a8_p1 ipfins$r_a8.ipfins$r_a8_0_63.ipfins$v_a8_p1@#define ipfins$v_a8_c ipfins$r_a8.ipfins$r_a8_0_63.ipfins$v_a8_cH#define ipfins$v_a8_imm7b ipfins$r_a $8.ipfins$r_a8_0_63.ipfins$v_a8_imm7bB#define ipfins$v_a8_r3 ipfins$r_a8.ipfins$r_a8_0_63.ipfins$v_a8_r3B#define ipfins$v_a8_p2 ipfins$r_a8.ipfins$r_a8_0_63.ipfins$v_a8_p2B#define ipfins$v_a8_ta ipfins$r_a8.ipfins$r_a8_0_63.ipfins$v_a8_taB#define ipfins$v_a8_x2 ipfins$r_a8.ipfins$r_a8_0_63.ipfins$v_a8_x2@#define ipfins$v_a8_s ipfins$r_a8.ipfins$r_a8_0_63.ipfins$v_a8_sJ#define ipfins$v_a8_opcode ipfins$r_a8.ipfins$r_a8_0_63.ipfins$v_a8_opcode+#define ipfins$q_a8 ipfins$r_a8.ipfins$q_a8"#endif $/* #if !defined(__VAXC) */ N/* */I/* A9: Multimedia ALU */N/* */#define IPFINS$M_A9_QP 0x3F#define IPFINS$M_A9_R1 0x1FC0#define IPFINS$M_A9_R2 0xFE000 #define IPFINS$M_A9_R3 0x7F00000"#define IPFINS$M_A9_X2B 0x18000000"#define IPFINS$M_A9_X4 0x1E0000000"#define IPFINS$M_A9_ZB 0x200000000##d$efine IPFINS$M_A9_X2A 0xC00000000##define IPFINS$M_A9_ZA 0x1000000000(#define IPFINS$M_A9_OPCODE 0x1E000000000+#define IPFINS$M_A9_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _a9_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_a9_qp : 6;( $ unsigned ipfins$v_a9_r1 : 7;( unsigned ipfins$v_a9_r2 : 7;( unsigned ipfins$v_a9_r3 : 7;) unsigned ipfins$v_a9_x2b : 2;( unsigned ipfins$v_a9_x4 : 4;( unsigned ipfins$v_a9_zb : 1;) unsigned ipfins$v_a9_x2a : 2;( unsigned ipfins$v_a9_za : 1;, unsigned ipfins$v_a9_opcode : 4;+ unsigned ipfins$v_a9_fill : 23; } ipfins$r_a9_0_63;% unsigned __int64 ipfins$q_a9; } $ipfins$r_a9; } A9_FORMAT; #if !defined(__VAXC)B#define ipfins$v_a9_qp ipfins$r_a9.ipfins$r_a9_0_63.ipfins$v_a9_qpB#define ipfins$v_a9_r1 ipfins$r_a9.ipfins$r_a9_0_63.ipfins$v_a9_r1B#define ipfins$v_a9_r2 ipfins$r_a9.ipfins$r_a9_0_63.ipfins$v_a9_r2B#define ipfins$v_a9_r3 ipfins$r_a9.ipfins$r_a9_0_63.ipfins$v_a9_r3D#define ipfins$v_a9_x2b ipfins$r_a9.ipfins$r_a9_0_63.ipfins$v_a9_x2bB#define ipfins$v_a9_x4 ipfins$r_a9.ipfins$r_a9_0_63.ipfins$v_a9_x4B#define ipfins$v_a9_zb ipfins$r_a9.ipf $ins$r_a9_0_63.ipfins$v_a9_zbD#define ipfins$v_a9_x2a ipfins$r_a9.ipfins$r_a9_0_63.ipfins$v_a9_x2aB#define ipfins$v_a9_za ipfins$r_a9.ipfins$r_a9_0_63.ipfins$v_a9_zaJ#define ipfins$v_a9_opcode ipfins$r_a9.ipfins$r_a9_0_63.ipfins$v_a9_opcode+#define ipfins$q_a9 ipfins$r_a9.ipfins$q_a9"#endif /* #if !defined(__VAXC) */ N/* */I/* A10: Multimedia Shift and Add */N/* $ */#define IPFINS$M_A10_QP 0x3F#define IPFINS$M_A10_R1 0x1FC0#define IPFINS$M_A10_R2 0xFE000!#define IPFINS$M_A10_R3 0x7F00000$#define IPFINS$M_A10_CT2D 0x18000000##define IPFINS$M_A10_X4 0x1E0000000##define IPFINS$M_A10_ZB 0x200000000$#define IPFINS$M_A10_X2A 0xC00000000$#define IPFINS$M_A10_ZA 0x1000000000)#define IPFINS$M_A10_OPCODE 0x1E000000000,#define IPFINS$M_A10_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUP$PORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _a10_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_a10_qp : 6;) unsigned ipfins$v_a10_r1 : 7;) unsigned ipfins$v_a10_r2 : 7;) unsigned ipfins$v_a10_r3 : 7;+ unsigned ipfins$v_a10_ct2d : 2;) unsigned ipfin$s$v_a10_x4 : 4;) unsigned ipfins$v_a10_zb : 1;* unsigned ipfins$v_a10_x2a : 2;) unsigned ipfins$v_a10_za : 1;- unsigned ipfins$v_a10_opcode : 4;, unsigned ipfins$v_a10_fill : 23; } ipfins$r_a10_0_63;& unsigned __int64 ipfins$q_a10; } ipfins$r_a10; } A10_FORMAT; #if !defined(__VAXC)F#define ipfins$v_a10_qp ipfins$r_a10.ipfins$r_a10_0_63.ipfins$v_a10_qpF#define ipfins$v_a10_r1 ipfins$r_a10.ipfins$$r_a10_0_63.ipfins$v_a10_r1F#define ipfins$v_a10_r2 ipfins$r_a10.ipfins$r_a10_0_63.ipfins$v_a10_r2F#define ipfins$v_a10_r3 ipfins$r_a10.ipfins$r_a10_0_63.ipfins$v_a10_r3J#define ipfins$v_a10_ct2d ipfins$r_a10.ipfins$r_a10_0_63.ipfins$v_a10_ct2dF#define ipfins$v_a10_x4 ipfins$r_a10.ipfins$r_a10_0_63.ipfins$v_a10_x4F#define ipfins$v_a10_zb ipfins$r_a10.ipfins$r_a10_0_63.ipfins$v_a10_zbH#define ipfins$v_a10_x2a ipfins$r_a10.ipfins$r_a10_0_63.ipfins$v_a10_x2aF#define ipfins$v_a10_za ipfins$r_a10.ipf $ins$r_a10_0_63.ipfins$v_a10_zaN#define ipfins$v_a10_opcode ipfins$r_a10.ipfins$r_a10_0_63.ipfins$v_a10_opcode.#define ipfins$q_a10 ipfins$r_a10.ipfins$q_a10"#endif /* #if !defined(__VAXC) */ N/* */I/* I-Unit Formats */N/* */N/* $ */I/* I1: Multimedia Multiply and Shift */N/* */#define IPFINS$M_I1_QP 0x3F#define IPFINS$M_I1_R1 0x1FC0#define IPFINS$M_I1_R2 0xFE000 #define IPFINS$M_I1_R3 0x7F00000 #define IPFINS$M_I1_27 0x8000000"#define IPFINS$M_I1_X2B 0x30000000##define IPFINS$M_I1_CT2D 0xC0000000"#define IPFINS$M_I1_VE 0x100000000"#define IPFINS$M_I1_ZB 0x200000000##define IPFINS$M_I1_X2A 0xC00000$000##define IPFINS$M_I1_ZA 0x1000000000(#define IPFINS$M_I1_OPCODE 0x1E000000000+#define IPFINS$M_I1_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i1_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_i1_qp : 6;( unsigned ipfins$v_i1_r1 : 7; $( unsigned ipfins$v_i1_r2 : 7;( unsigned ipfins$v_i1_r3 : 7;( unsigned ipfins$v_i1_27 : 1;) unsigned ipfins$v_i1_x2b : 2;* unsigned ipfins$v_i1_ct2d : 2;( unsigned ipfins$v_i1_ve : 1;( unsigned ipfins$v_i1_zb : 1;) unsigned ipfins$v_i1_x2a : 2;( unsigned ipfins$v_i1_za : 1;, unsigned ipfins$v_i1_opcode : 4;+ unsigned ipfins$v_i1_fill : 23; } ipfins$r_i1_0_ $63;% unsigned __int64 ipfins$q_i1; } ipfins$r_i1; } I1_FORMAT; #if !defined(__VAXC)B#define ipfins$v_i1_qp ipfins$r_i1.ipfins$r_i1_0_63.ipfins$v_i1_qpB#define ipfins$v_i1_r1 ipfins$r_i1.ipfins$r_i1_0_63.ipfins$v_i1_r1B#define ipfins$v_i1_r2 ipfins$r_i1.ipfins$r_i1_0_63.ipfins$v_i1_r2B#define ipfins$v_i1_r3 ipfins$r_i1.ipfins$r_i1_0_63.ipfins$v_i1_r3B#define ipfins$v_i1_27 ipfins$r_i1.ipfins$r_i1_0_63.ipfins$v_i1_27D#define ipfins$v_i1_x2b ipfins$r_i1.ipfins$r_i1_0_63 $.ipfins$v_i1_x2bF#define ipfins$v_i1_ct2d ipfins$r_i1.ipfins$r_i1_0_63.ipfins$v_i1_ct2dB#define ipfins$v_i1_ve ipfins$r_i1.ipfins$r_i1_0_63.ipfins$v_i1_veB#define ipfins$v_i1_zb ipfins$r_i1.ipfins$r_i1_0_63.ipfins$v_i1_zbD#define ipfins$v_i1_x2a ipfins$r_i1.ipfins$r_i1_0_63.ipfins$v_i1_x2aB#define ipfins$v_i1_za ipfins$r_i1.ipfins$r_i1_0_63.ipfins$v_i1_zaJ#define ipfins$v_i1_opcode ipfins$r_i1.ipfins$r_i1_0_63.ipfins$v_i1_opcode+#define ipfins$q_i1 ipfins$r_i1.ipfins$q_i1"#endif /* #if !defi $ned(__VAXC) */ N/* */I/* I2: Multimedia Multiply/Mix/Pack/Unpack */N/* */#define IPFINS$M_I2_QP 0x3F#define IPFINS$M_I2_R1 0x1FC0#define IPFINS$M_I2_R2 0xFE000 #define IPFINS$M_I2_R3 0x7F00000 #define IPFINS$M_I2_27 0x8000000"#define IPFINS$M_I2_X2B 0x30000000"#define IPFINS$M_I2_X2C 0xC0000000"#define IPFINS$M$_I2_VE 0x100000000"#define IPFINS$M_I2_ZB 0x200000000##define IPFINS$M_I2_X2A 0xC00000000##define IPFINS$M_I2_ZA 0x1000000000(#define IPFINS$M_I2_OPCODE 0x1E000000000+#define IPFINS$M_I2_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i2_format {#pragma __nomember_alignment __union { __struct $ {( unsigned ipfins$v_i2_qp : 6;( unsigned ipfins$v_i2_r1 : 7;( unsigned ipfins$v_i2_r2 : 7;( unsigned ipfins$v_i2_r3 : 7;( unsigned ipfins$v_i2_27 : 1;) unsigned ipfins$v_i2_x2b : 2;) unsigned ipfins$v_i2_x2c : 2;( unsigned ipfins$v_i2_ve : 1;( unsigned ipfins$v_i2_zb : 1;) unsigned ipfins$v_i2_x2a : 2;( unsigned ipfins$v_i2_za : 1;, unsigned ipfins$v_i2 $_opcode : 4;+ unsigned ipfins$v_i2_fill : 23; } ipfins$r_i2_0_63;% unsigned __int64 ipfins$q_i2; } ipfins$r_i2; } I2_FORMAT; #if !defined(__VAXC)B#define ipfins$v_i2_qp ipfins$r_i2.ipfins$r_i2_0_63.ipfins$v_i2_qpB#define ipfins$v_i2_r1 ipfins$r_i2.ipfins$r_i2_0_63.ipfins$v_i2_r1B#define ipfins$v_i2_r2 ipfins$r_i2.ipfins$r_i2_0_63.ipfins$v_i2_r2B#define ipfins$v_i2_r3 ipfins$r_i2.ipfins$r_i2_0_63.ipfins$v_i2_r3B#define ipfins$v_i2_27 ipfins$r_$i2.ipfins$r_i2_0_63.ipfins$v_i2_27D#define ipfins$v_i2_x2b ipfins$r_i2.ipfins$r_i2_0_63.ipfins$v_i2_x2bD#define ipfins$v_i2_x2c ipfins$r_i2.ipfins$r_i2_0_63.ipfins$v_i2_x2cB#define ipfins$v_i2_ve ipfins$r_i2.ipfins$r_i2_0_63.ipfins$v_i2_veB#define ipfins$v_i2_zb ipfins$r_i2.ipfins$r_i2_0_63.ipfins$v_i2_zbD#define ipfins$v_i2_x2a ipfins$r_i2.ipfins$r_i2_0_63.ipfins$v_i2_x2aB#define ipfins$v_i2_za ipfins$r_i2.ipfins$r_i2_0_63.ipfins$v_i2_zaJ#define ipfins$v_i2_opcode ipfins$r_i2.ipfins$r_i2_0_63. $ipfins$v_i2_opcode+#define ipfins$q_i2 ipfins$r_i2.ipfins$q_i2"#endif /* #if !defined(__VAXC) */ N/* */I/* I3: Multimedia Mux1 */N/* */#define IPFINS$M_I3_QP 0x3F#define IPFINS$M_I3_R1 0x1FC0#define IPFINS$M_I3_R2 0xFE000"#define IPFINS$M_I3_MBT4C 0xF00000##define IPFINS$M_I3_24_27 0xF00000$0"#define IPFINS$M_I3_X2B 0x30000000"#define IPFINS$M_I3_X2C 0xC0000000"#define IPFINS$M_I3_VE 0x100000000"#define IPFINS$M_I3_ZB 0x200000000##define IPFINS$M_I3_X2A 0xC00000000##define IPFINS$M_I3_ZA 0x1000000000(#define IPFINS$M_I3_OPCODE 0x1E000000000+#define IPFINS$M_I3_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif$typedef struct _i3_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_i3_qp : 6;( unsigned ipfins$v_i3_r1 : 7;( unsigned ipfins$v_i3_r2 : 7;+ unsigned ipfins$v_i3_mbt4c : 4;+ unsigned ipfins$v_i3_24_27 : 4;) unsigned ipfins$v_i3_x2b : 2;) unsigned ipfins$v_i3_x2c : 2;( unsigned ipfins$v_i3_ve : 1;( unsigned ipfins$v_i3_zb : 1;) unsign$ed ipfins$v_i3_x2a : 2;( unsigned ipfins$v_i3_za : 1;, unsigned ipfins$v_i3_opcode : 4;+ unsigned ipfins$v_i3_fill : 23; } ipfins$r_i3_0_63;% unsigned __int64 ipfins$q_i3; } ipfins$r_i3; } I3_FORMAT; #if !defined(__VAXC)B#define ipfins$v_i3_qp ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_qpB#define ipfins$v_i3_r1 ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_r1B#define ipfins$v_i3_r2 ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_r2H$#define ipfins$v_i3_mbt4c ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_mbt4cH#define ipfins$v_i3_24_27 ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_24_27D#define ipfins$v_i3_x2b ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_x2bD#define ipfins$v_i3_x2c ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_x2cB#define ipfins$v_i3_ve ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_veB#define ipfins$v_i3_zb ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_zbD#define ipfins$v_i3_x2a ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_x2aB#define ipfi $ns$v_i3_za ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_zaJ#define ipfins$v_i3_opcode ipfins$r_i3.ipfins$r_i3_0_63.ipfins$v_i3_opcode+#define ipfins$q_i3 ipfins$r_i3.ipfins$q_i3"#endif /* #if !defined(__VAXC) */ N/* */I/* I4: Multimedia Mux2 */N/* */#define IPFINS$M_I4_QP 0x3F#define IPFINS$M_I4_R1$ 0x1FC0#define IPFINS$M_I4_R2 0xFE000##define IPFINS$M_I4_MHT8C 0xFF00000"#define IPFINS$M_I4_X2B 0x30000000"#define IPFINS$M_I4_X2C 0xC0000000"#define IPFINS$M_I4_VE 0x100000000"#define IPFINS$M_I4_ZB 0x200000000##define IPFINS$M_I4_X2A 0xC00000000##define IPFINS$M_I4_ZA 0x1000000000(#define IPFINS$M_I4_OPCODE 0x1E000000000+#define IPFINS$M_I4_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __no$member_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i4_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_i4_qp : 6;( unsigned ipfins$v_i4_r1 : 7;( unsigned ipfins$v_i4_r2 : 7;+ unsigned ipfins$v_i4_mht8c : 8;) unsigned ipfins$v_i4_x2b : 2;) unsigned ipfins$v_i4_x2c : 2;( unsigned ipfins$v_i4_ve : 1;( unsigned ipfins$v_$i4_zb : 1;) unsigned ipfins$v_i4_x2a : 2;( unsigned ipfins$v_i4_za : 1;, unsigned ipfins$v_i4_opcode : 4;+ unsigned ipfins$v_i4_fill : 23; } ipfins$r_i4_0_63;% unsigned __int64 ipfins$q_i4; } ipfins$r_i4; } I4_FORMAT; #if !defined(__VAXC)B#define ipfins$v_i4_qp ipfins$r_i4.ipfins$r_i4_0_63.ipfins$v_i4_qpB#define ipfins$v_i4_r1 ipfins$r_i4.ipfins$r_i4_0_63.ipfins$v_i4_r1B#define ipfins$v_i4_r2 ipfins$r_i4.ipf$ins$r_i4_0_63.ipfins$v_i4_r2H#define ipfins$v_i4_mht8c ipfins$r_i4.ipfins$r_i4_0_63.ipfins$v_i4_mht8cD#define ipfins$v_i4_x2b ipfins$r_i4.ipfins$r_i4_0_63.ipfins$v_i4_x2bD#define ipfins$v_i4_x2c ipfins$r_i4.ipfins$r_i4_0_63.ipfins$v_i4_x2cB#define ipfins$v_i4_ve ipfins$r_i4.ipfins$r_i4_0_63.ipfins$v_i4_veB#define ipfins$v_i4_zb ipfins$r_i4.ipfins$r_i4_0_63.ipfins$v_i4_zbD#define ipfins$v_i4_x2a ipfins$r_i4.ipfins$r_i4_0_63.ipfins$v_i4_x2aB#define ipfins$v_i4_za ipfins$r_i4.ipfins$r_i4_0_63.ipfi $ns$v_i4_zaJ#define ipfins$v_i4_opcode ipfins$r_i4.ipfins$r_i4_0_63.ipfins$v_i4_opcode+#define ipfins$q_i4 ipfins$r_i4.ipfins$q_i4"#endif /* #if !defined(__VAXC) */ N/* */I/* I5: Shift Right - Variable */N/* */#define IPFINS$M_I5_QP 0x3F#define IPFINS$M_I5_R1 0x1FC0#define IPFINS$M_I5_R2 0xFE000 #d $efine IPFINS$M_I5_R3 0x7F00000 #define IPFINS$M_I5_27 0x8000000"#define IPFINS$M_I5_X2B 0x30000000"#define IPFINS$M_I5_X2C 0xC0000000"#define IPFINS$M_I5_VE 0x100000000"#define IPFINS$M_I5_ZB 0x200000000##define IPFINS$M_I5_X2A 0xC00000000##define IPFINS$M_I5_ZA 0x1000000000(#define IPFINS$M_I5_OPCODE 0x1E000000000+#define IPFINS$M_I5_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignme$nt __quadword#else#pragma __nomember_alignment#endiftypedef struct _i5_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_i5_qp : 6;( unsigned ipfins$v_i5_r1 : 7;( unsigned ipfins$v_i5_r2 : 7;( unsigned ipfins$v_i5_r3 : 7;( unsigned ipfins$v_i5_27 : 1;) unsigned ipfins$v_i5_x2b : 2;) unsigned ipfins$v_i5_x2c : 2;( unsigned ipfins$v_i5_ve : 1;( $ unsigned ipfins$v_i5_zb : 1;) unsigned ipfins$v_i5_x2a : 2;( unsigned ipfins$v_i5_za : 1;, unsigned ipfins$v_i5_opcode : 4;+ unsigned ipfins$v_i5_fill : 23; } ipfins$r_i5_0_63;% unsigned __int64 ipfins$q_i5; } ipfins$r_i5; } I5_FORMAT; #if !defined(__VAXC)B#define ipfins$v_i5_qp ipfins$r_i5.ipfins$r_i5_0_63.ipfins$v_i5_qpB#define ipfins$v_i5_r1 ipfins$r_i5.ipfins$r_i5_0_63.ipfins$v_i5_r1B#define ipfins$$v_i5_r2 ipfins$r_i5.ipfins$r_i5_0_63.ipfins$v_i5_r2B#define ipfins$v_i5_r3 ipfins$r_i5.ipfins$r_i5_0_63.ipfins$v_i5_r3B#define ipfins$v_i5_27 ipfins$r_i5.ipfins$r_i5_0_63.ipfins$v_i5_27D#define ipfins$v_i5_x2b ipfins$r_i5.ipfins$r_i5_0_63.ipfins$v_i5_x2bD#define ipfins$v_i5_x2c ipfins$r_i5.ipfins$r_i5_0_63.ipfins$v_i5_x2cB#define ipfins$v_i5_ve ipfins$r_i5.ipfins$r_i5_0_63.ipfins$v_i5_veB#define ipfins$v_i5_zb ipfins$r_i5.ipfins$r_i5_0_63.ipfins$v_i5_zbD#define ipfins$v_i5_x2a ipfins$r_i5.ipfi $ns$r_i5_0_63.ipfins$v_i5_x2aB#define ipfins$v_i5_za ipfins$r_i5.ipfins$r_i5_0_63.ipfins$v_i5_zaJ#define ipfins$v_i5_opcode ipfins$r_i5.ipfins$r_i5_0_63.ipfins$v_i5_opcode+#define ipfins$q_i5 ipfins$r_i5.ipfins$q_i5"#endif /* #if !defined(__VAXC) */ N/* */I/* I6: Multimedia Shift Right - Fixed */N/* */#define IP$FINS$M_I6_QP 0x3F#define IPFINS$M_I6_R1 0x1FC0#define IPFINS$M_I6_13 0x2000##define IPFINS$M_I6_COUNT5B 0x7C000#define IPFINS$M_I6_19 0x80000 #define IPFINS$M_I6_R3 0x7F00000 #define IPFINS$M_I6_27 0x8000000"#define IPFINS$M_I6_X2B 0x30000000"#define IPFINS$M_I6_X2C 0xC0000000"#define IPFINS$M_I6_VE 0x100000000"#define IPFINS$M_I6_ZB 0x200000000##define IPFINS$M_I6_X2A 0xC00000000##define IPFINS$M_I6_ZA 0x1000000000(#define IPFINS$M_I6_OPCODE 0x1E000000000+#define IPFINS$M_I6_FI$LL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i6_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_i6_qp : 6;( unsigned ipfins$v_i6_r1 : 7;( unsigned ipfins$v_i6_13 : 1;- unsigned ipfins$v_i6_count5b : 5;( unsi $gned ipfins$v_i6_19 : 1;( unsigned ipfins$v_i6_r3 : 7;( unsigned ipfins$v_i6_27 : 1;) unsigned ipfins$v_i6_x2b : 2;) unsigned ipfins$v_i6_x2c : 2;( unsigned ipfins$v_i6_ve : 1;( unsigned ipfins$v_i6_zb : 1;) unsigned ipfins$v_i6_x2a : 2;( unsigned ipfins$v_i6_za : 1;, unsigned ipfins$v_i6_opcode : 4;+ unsigned ipfins$v_i6_fill : 23; } ipfins$r_i6_0_63;% unsi $gned __int64 ipfins$q_i6; } ipfins$r_i6; } I6_FORMAT; #if !defined(__VAXC)B#define ipfins$v_i6_qp ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_qpB#define ipfins$v_i6_r1 ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_r1B#define ipfins$v_i6_13 ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_13L#define ipfins$v_i6_count5b ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_count5bB#define ipfins$v_i6_19 ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_19B#define ipfins$v_i6_r3 ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v $_i6_r3B#define ipfins$v_i6_27 ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_27D#define ipfins$v_i6_x2b ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_x2bD#define ipfins$v_i6_x2c ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_x2cB#define ipfins$v_i6_ve ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_veB#define ipfins$v_i6_zb ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_zbD#define ipfins$v_i6_x2a ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_x2aB#define ipfins$v_i6_za ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_zaJ#define ipfins$v $_i6_opcode ipfins$r_i6.ipfins$r_i6_0_63.ipfins$v_i6_opcode+#define ipfins$q_i6 ipfins$r_i6.ipfins$q_i6"#endif /* #if !defined(__VAXC) */ N/* */I/* I7: Shift Left - Variable */N/* */#define IPFINS$M_I7_QP 0x3F#define IPFINS$M_I7_R1 0x1FC0#define IPFINS$M_I7_R2 0xFE000 #define IPFINS$M_I7_R3 0x7F000$00 #define IPFINS$M_I7_27 0x8000000"#define IPFINS$M_I7_X2B 0x30000000"#define IPFINS$M_I7_X2C 0xC0000000"#define IPFINS$M_I7_VE 0x100000000"#define IPFINS$M_I7_ZB 0x200000000##define IPFINS$M_I7_X2A 0xC00000000##define IPFINS$M_I7_ZA 0x1000000000(#define IPFINS$M_I7_OPCODE 0x1E000000000+#define IPFINS$M_I7_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pra$gma __nomember_alignment#endiftypedef struct _i7_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_i7_qp : 6;( unsigned ipfins$v_i7_r1 : 7;( unsigned ipfins$v_i7_r2 : 7;( unsigned ipfins$v_i7_r3 : 7;( unsigned ipfins$v_i7_27 : 1;) unsigned ipfins$v_i7_x2b : 2;) unsigned ipfins$v_i7_x2c : 2;( unsigned ipfins$v_i7_ve : 1;( unsigned ipfins$v_i7_z$b : 1;) unsigned ipfins$v_i7_x2a : 2;( unsigned ipfins$v_i7_za : 1;, unsigned ipfins$v_i7_opcode : 4;+ unsigned ipfins$v_i7_fill : 23; } ipfins$r_i7_0_63;% unsigned __int64 ipfins$q_i7; } ipfins$r_i7; } I7_FORMAT; #if !defined(__VAXC)B#define ipfins$v_i7_qp ipfins$r_i7.ipfins$r_i7_0_63.ipfins$v_i7_qpB#define ipfins$v_i7_r1 ipfins$r_i7.ipfins$r_i7_0_63.ipfins$v_i7_r1B#define ipfins$v_i7_r2 ipfins$r_i7.ipfins$$r_i7_0_63.ipfins$v_i7_r2B#define ipfins$v_i7_r3 ipfins$r_i7.ipfins$r_i7_0_63.ipfins$v_i7_r3B#define ipfins$v_i7_27 ipfins$r_i7.ipfins$r_i7_0_63.ipfins$v_i7_27D#define ipfins$v_i7_x2b ipfins$r_i7.ipfins$r_i7_0_63.ipfins$v_i7_x2bD#define ipfins$v_i7_x2c ipfins$r_i7.ipfins$r_i7_0_63.ipfins$v_i7_x2cB#define ipfins$v_i7_ve ipfins$r_i7.ipfins$r_i7_0_63.ipfins$v_i7_veB#define ipfins$v_i7_zb ipfins$r_i7.ipfins$r_i7_0_63.ipfins$v_i7_zbD#define ipfins$v_i7_x2a ipfins$r_i7.ipfins$r_i7_0_63.ipfins$v_i7_x2a $B#define ipfins$v_i7_za ipfins$r_i7.ipfins$r_i7_0_63.ipfins$v_i7_zaJ#define ipfins$v_i7_opcode ipfins$r_i7.ipfins$r_i7_0_63.ipfins$v_i7_opcode+#define ipfins$q_i7 ipfins$r_i7.ipfins$q_i7"#endif /* #if !defined(__VAXC) */ N/* */I/* I8: Multimedia Shift Left - Fixed */N/* */#define IPFINS$M_I8_QP 0x3F#define $IPFINS$M_I8_R1 0x1FC0#define IPFINS$M_I8_R2 0xFE000&#define IPFINS$M_I8_CCOUNT5C 0x1F00000##define IPFINS$M_I8_25_27 0xE000000"#define IPFINS$M_I8_X2B 0x30000000"#define IPFINS$M_I8_X2C 0xC0000000"#define IPFINS$M_I8_VE 0x100000000"#define IPFINS$M_I8_ZB 0x200000000##define IPFINS$M_I8_X2A 0xC00000000##define IPFINS$M_I8_ZA 0x1000000000(#define IPFINS$M_I8_OPCODE 0x1E000000000+#define IPFINS$M_I8_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus$) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i8_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_i8_qp : 6;( unsigned ipfins$v_i8_r1 : 7;( unsigned ipfins$v_i8_r2 : 7;. unsigned ipfins$v_i8_ccount5c : 5;+ unsigned ipfins$v_i8_25_27 : 3;) unsigned ipfins$v_i8_x2b : 2;) un$signed ipfins$v_i8_x2c : 2;( unsigned ipfins$v_i8_ve : 1;( unsigned ipfins$v_i8_zb : 1;) unsigned ipfins$v_i8_x2a : 2;( unsigned ipfins$v_i8_za : 1;, unsigned ipfins$v_i8_opcode : 4;+ unsigned ipfins$v_i8_fill : 23; } ipfins$r_i8_0_63;% unsigned __int64 ipfins$q_i8; } ipfins$r_i8; } I8_FORMAT; #if !defined(__VAXC)B#define ipfins$v_i8_qp ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_qpB#def$ine ipfins$v_i8_r1 ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_r1B#define ipfins$v_i8_r2 ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_r2N#define ipfins$v_i8_ccount5c ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_ccount5cH#define ipfins$v_i8_25_27 ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_25_27D#define ipfins$v_i8_x2b ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_x2bD#define ipfins$v_i8_x2c ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_x2cB#define ipfins$v_i8_ve ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_veB#define ipfi $ns$v_i8_zb ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_zbD#define ipfins$v_i8_x2a ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_x2aB#define ipfins$v_i8_za ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_zaJ#define ipfins$v_i8_opcode ipfins$r_i8.ipfins$r_i8_0_63.ipfins$v_i8_opcode+#define ipfins$q_i8 ipfins$r_i8.ipfins$q_i8"#endif /* #if !defined(__VAXC) */ N/* */I/* I9: Bit Strings $ */N/* */#define IPFINS$M_I9_QP 0x3F#define IPFINS$M_I9_R1 0x1FC0 #define IPFINS$M_I9_ZERO 0xFE000 #define IPFINS$M_I9_R3 0x7F00000 #define IPFINS$M_I9_27 0x8000000"#define IPFINS$M_I9_X2B 0x30000000"#define IPFINS$M_I9_X2C 0xC0000000"#define IPFINS$M_I9_VE 0x100000000"#define IPFINS$M_I9_ZB 0x200000000##define IPFINS$M_I9_X2A 0xC00000000##define IPFINS$M_I9_ZA 0x1000000000(#define IPFINS$M_I9_OPCODE 0x1E00000$0000+#define IPFINS$M_I9_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i9_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_i9_qp : 6;( unsigned ipfins$v_i9_r1 : 7;* unsigned ipfins$v_i9_zero : 7;( unsigned ipfins$v_i9_r$3 : 7;( unsigned ipfins$v_i9_27 : 1;) unsigned ipfins$v_i9_x2b : 2;) unsigned ipfins$v_i9_x2c : 2;( unsigned ipfins$v_i9_ve : 1;( unsigned ipfins$v_i9_zb : 1;) unsigned ipfins$v_i9_x2a : 2;( unsigned ipfins$v_i9_za : 1;, unsigned ipfins$v_i9_opcode : 4;+ unsigned ipfins$v_i9_fill : 23; } ipfins$r_i9_0_63;% unsigned __int64 ipfins$q_i9; } ipfins$r_i9; } I9 $_FORMAT; #if !defined(__VAXC)B#define ipfins$v_i9_qp ipfins$r_i9.ipfins$r_i9_0_63.ipfins$v_i9_qpB#define ipfins$v_i9_r1 ipfins$r_i9.ipfins$r_i9_0_63.ipfins$v_i9_r1F#define ipfins$v_i9_zero ipfins$r_i9.ipfins$r_i9_0_63.ipfins$v_i9_zeroB#define ipfins$v_i9_r3 ipfins$r_i9.ipfins$r_i9_0_63.ipfins$v_i9_r3B#define ipfins$v_i9_27 ipfins$r_i9.ipfins$r_i9_0_63.ipfins$v_i9_27D#define ipfins$v_i9_x2b ipfins$r_i9.ipfins$r_i9_0_63.ipfins$v_i9_x2bD#define ipfins$v_i9_x2c ipfins$r_i9.ipfins$r_i9_0_63.ipf $ins$v_i9_x2cB#define ipfins$v_i9_ve ipfins$r_i9.ipfins$r_i9_0_63.ipfins$v_i9_veB#define ipfins$v_i9_zb ipfins$r_i9.ipfins$r_i9_0_63.ipfins$v_i9_zbD#define ipfins$v_i9_x2a ipfins$r_i9.ipfins$r_i9_0_63.ipfins$v_i9_x2aB#define ipfins$v_i9_za ipfins$r_i9.ipfins$r_i9_0_63.ipfins$v_i9_zaJ#define ipfins$v_i9_opcode ipfins$r_i9.ipfins$r_i9_0_63.ipfins$v_i9_opcode+#define ipfins$q_i9 ipfins$r_i9.ipfins$q_i9"#endif /* #if !defined(__VAXC) */ N/* $ */I/* I10: Shift Right Pair */N/* */#define IPFINS$M_I10_QP 0x3F#define IPFINS$M_I10_R1 0x1FC0#define IPFINS$M_I10_R2 0xFE000!#define IPFINS$M_I10_R3 0x7F00000(#define IPFINS$M_I10_COUNT6D 0x1F8000000"#define IPFINS$M_I10_X 0x200000000##define IPFINS$M_I10_X2 0xC00000000$#define IPFINS$M_I10_36 0x1000000000)#define IPFINS$M_I10_OPCODE 0x1E00000000$0,#define IPFINS$M_I10_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i10_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i10_qp : 6;) unsigned ipfins$v_i10_r1 : 7;) unsigned ipfins$v_i10_r2 : 7;) unsigned ipfins$v_i1$0_r3 : 7;. unsigned ipfins$v_i10_count6d : 6;( unsigned ipfins$v_i10_x : 1;) unsigned ipfins$v_i10_x2 : 2;) unsigned ipfins$v_i10_36 : 1;- unsigned ipfins$v_i10_opcode : 4;, unsigned ipfins$v_i10_fill : 23; } ipfins$r_i10_0_63;& unsigned __int64 ipfins$q_i10; } ipfins$r_i10; } I10_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i10_qp ipfins$r_i10.ipfins$r_i10_0_63.ipfins$v_i10_qpF#def$ine ipfins$v_i10_r1 ipfins$r_i10.ipfins$r_i10_0_63.ipfins$v_i10_r1F#define ipfins$v_i10_r2 ipfins$r_i10.ipfins$r_i10_0_63.ipfins$v_i10_r2F#define ipfins$v_i10_r3 ipfins$r_i10.ipfins$r_i10_0_63.ipfins$v_i10_r3P#define ipfins$v_i10_count6d ipfins$r_i10.ipfins$r_i10_0_63.ipfins$v_i10_count6dD#define ipfins$v_i10_x ipfins$r_i10.ipfins$r_i10_0_63.ipfins$v_i10_xF#define ipfins$v_i10_x2 ipfins$r_i10.ipfins$r_i10_0_63.ipfins$v_i10_x2F#define ipfins$v_i10_36 ipfins$r_i10.ipfins$r_i10_0_63.ipfins$v_i10_36 $N#define ipfins$v_i10_opcode ipfins$r_i10.ipfins$r_i10_0_63.ipfins$v_i10_opcode.#define ipfins$q_i10 ipfins$r_i10.ipfins$q_i10"#endif /* #if !defined(__VAXC) */ N/* */I/* I11: Extract */N/* */#define IPFINS$M_I11_QP 0x3F#define IPFINS$M_I11_R1 0x1FC0#define IPFINS$M_I11_Y 0x2000"#defin$e IPFINS$M_I11_POS6B 0xFC000!#define IPFINS$M_I11_R3 0x7F00000&#define IPFINS$M_I11_LEN6D 0x1F8000000"#define IPFINS$M_I11_X 0x200000000##define IPFINS$M_I11_X2 0xC00000000$#define IPFINS$M_I11_36 0x1000000000)#define IPFINS$M_I11_OPCODE 0x1E000000000,#define IPFINS$M_I11_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftype$def struct _i11_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i11_qp : 6;) unsigned ipfins$v_i11_r1 : 7;( unsigned ipfins$v_i11_y : 1;, unsigned ipfins$v_i11_pos6b : 6;) unsigned ipfins$v_i11_r3 : 7;, unsigned ipfins$v_i11_len6d : 6;( unsigned ipfins$v_i11_x : 1;) unsigned ipfins$v_i11_x2 : 2;) unsigned ipfins$v_i11_36 : 1;- unsi $gned ipfins$v_i11_opcode : 4;, unsigned ipfins$v_i11_fill : 23; } ipfins$r_i11_0_63;& unsigned __int64 ipfins$q_i11; } ipfins$r_i11; } I11_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i11_qp ipfins$r_i11.ipfins$r_i11_0_63.ipfins$v_i11_qpF#define ipfins$v_i11_r1 ipfins$r_i11.ipfins$r_i11_0_63.ipfins$v_i11_r1D#define ipfins$v_i11_y ipfins$r_i11.ipfins$r_i11_0_63.ipfins$v_i11_yL#define ipfins$v_i11_pos6b ipfins$r_i11.ipfins$r_i11_0_63.ipfins$v_i $11_pos6bF#define ipfins$v_i11_r3 ipfins$r_i11.ipfins$r_i11_0_63.ipfins$v_i11_r3L#define ipfins$v_i11_len6d ipfins$r_i11.ipfins$r_i11_0_63.ipfins$v_i11_len6dD#define ipfins$v_i11_x ipfins$r_i11.ipfins$r_i11_0_63.ipfins$v_i11_xF#define ipfins$v_i11_x2 ipfins$r_i11.ipfins$r_i11_0_63.ipfins$v_i11_x2F#define ipfins$v_i11_36 ipfins$r_i11.ipfins$r_i11_0_63.ipfins$v_i11_36N#define ipfins$v_i11_opcode ipfins$r_i11.ipfins$r_i11_0_63.ipfins$v_i11_opcode.#define ipfins$q_i11 ipfins$r_i11.ipfins$q_i11"#end %if /* #if !defined(__VAXC) */ N/* */I/* I12: Zero and Deposit */N/* */#define IPFINS$M_I12_QP 0x3F#define IPFINS$M_I12_R1 0x1FC0#define IPFINS$M_I12_R2 0xFE000%#define IPFINS$M_I12_CPOS6C 0x3F00000 #define IPFINS$M_I12_Y 0x4000000&#define IPFINS$M_I12_LEN6D 0x1F8000000"#define IPFINS$M_I12_X 0%x200000000##define IPFINS$M_I12_X2 0xC00000000$#define IPFINS$M_I12_36 0x1000000000)#define IPFINS$M_I12_OPCODE 0x1E000000000,#define IPFINS$M_I12_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i12_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i12_qp % : 6;) unsigned ipfins$v_i12_r1 : 7;) unsigned ipfins$v_i12_r2 : 7;- unsigned ipfins$v_i12_cpos6c : 6;( unsigned ipfins$v_i12_y : 1;, unsigned ipfins$v_i12_len6d : 6;( unsigned ipfins$v_i12_x : 1;) unsigned ipfins$v_i12_x2 : 2;) unsigned ipfins$v_i12_36 : 1;- unsigned ipfins$v_i12_opcode : 4;, unsigned ipfins$v_i12_fill : 23; } ipfins$r_i12_0_63;& unsigned % __int64 ipfins$q_i12; } ipfins$r_i12; } I12_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i12_qp ipfins$r_i12.ipfins$r_i12_0_63.ipfins$v_i12_qpF#define ipfins$v_i12_r1 ipfins$r_i12.ipfins$r_i12_0_63.ipfins$v_i12_r1F#define ipfins$v_i12_r2 ipfins$r_i12.ipfins$r_i12_0_63.ipfins$v_i12_r2N#define ipfins$v_i12_cpos6c ipfins$r_i12.ipfins$r_i12_0_63.ipfins$v_i12_cpos6cD#define ipfins$v_i12_y ipfins$r_i12.ipfins$r_i12_0_63.ipfins$v_i12_yL#define ipfins$v_i12_len6d ipfins$r_i12.ipfi %ns$r_i12_0_63.ipfins$v_i12_len6dD#define ipfins$v_i12_x ipfins$r_i12.ipfins$r_i12_0_63.ipfins$v_i12_xF#define ipfins$v_i12_x2 ipfins$r_i12.ipfins$r_i12_0_63.ipfins$v_i12_x2F#define ipfins$v_i12_36 ipfins$r_i12.ipfins$r_i12_0_63.ipfins$v_i12_36N#define ipfins$v_i12_opcode ipfins$r_i12.ipfins$r_i12_0_63.ipfins$v_i12_opcode.#define ipfins$q_i12 ipfins$r_i12.ipfins$q_i12"#endif /* #if !defined(__VAXC) */ N/* */I/* I13: Ze %ro and Deposit Immediate(8) */N/* */#define IPFINS$M_I13_QP 0x3F#define IPFINS$M_I13_R1 0x1FC0"#define IPFINS$M_I13_IMM7B 0xFE000%#define IPFINS$M_I13_CPOS6C 0x3F00000 #define IPFINS$M_I13_Y 0x4000000&#define IPFINS$M_I13_LEN6D 0x1F8000000"#define IPFINS$M_I13_X 0x200000000##define IPFINS$M_I13_X2 0xC00000000##define IPFINS$M_I13_S 0x1000000000)#define IPFINS$M_I13_OPCODE 0x1E0000%00000,#define IPFINS$M_I13_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i13_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i13_qp : 6;) unsigned ipfins$v_i13_r1 : 7;, unsigned ipfins$v_i13_imm7b : 7;- unsigned ipfin%s$v_i13_cpos6c : 6;( unsigned ipfins$v_i13_y : 1;, unsigned ipfins$v_i13_len6d : 6;( unsigned ipfins$v_i13_x : 1;) unsigned ipfins$v_i13_x2 : 2;& signed ipfins$v_i13_s : 1;- unsigned ipfins$v_i13_opcode : 4;, unsigned ipfins$v_i13_fill : 23; } ipfins$r_i13_0_63;& unsigned __int64 ipfins$q_i13; } ipfins$r_i13; } I13_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i13_qp ipfins%$r_i13.ipfins$r_i13_0_63.ipfins$v_i13_qpF#define ipfins$v_i13_r1 ipfins$r_i13.ipfins$r_i13_0_63.ipfins$v_i13_r1L#define ipfins$v_i13_imm7b ipfins$r_i13.ipfins$r_i13_0_63.ipfins$v_i13_imm7bN#define ipfins$v_i13_cpos6c ipfins$r_i13.ipfins$r_i13_0_63.ipfins$v_i13_cpos6cD#define ipfins$v_i13_y ipfins$r_i13.ipfins$r_i13_0_63.ipfins$v_i13_yL#define ipfins$v_i13_len6d ipfins$r_i13.ipfins$r_i13_0_63.ipfins$v_i13_len6dD#define ipfins$v_i13_x ipfins$r_i13.ipfins$r_i13_0_63.ipfins$v_i13_xF#define ipfins$v %_i13_x2 ipfins$r_i13.ipfins$r_i13_0_63.ipfins$v_i13_x2D#define ipfins$v_i13_s ipfins$r_i13.ipfins$r_i13_0_63.ipfins$v_i13_sN#define ipfins$v_i13_opcode ipfins$r_i13.ipfins$r_i13_0_63.ipfins$v_i13_opcode.#define ipfins$q_i13 ipfins$r_i13.ipfins$q_i13"#endif /* #if !defined(__VAXC) */ N/* */I/* I14: Deposit Immediate(1) */N/*  % */#define IPFINS$M_I14_QP 0x3F#define IPFINS$M_I14_R1 0x1FC0#define IPFINS$M_I14_13 0x2000##define IPFINS$M_I14_CPOS6B 0xFC000!#define IPFINS$M_I14_R3 0x7F00000&#define IPFINS$M_I14_LEN6D 0x1F8000000"#define IPFINS$M_I14_X 0x200000000##define IPFINS$M_I14_X2 0xC00000000##define IPFINS$M_I14_S 0x1000000000)#define IPFINS$M_I14_OPCODE 0x1E000000000,#define IPFINS$M_I14_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* I %f using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i14_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i14_qp : 6;) unsigned ipfins$v_i14_r1 : 7;) unsigned ipfins$v_i14_13 : 1;- unsigned ipfins$v_i14_cpos6b : 6;) unsigned ipfins$v_i14_r3 : 7;, unsigned ipfins$v_i14_len6d : 6;( unsi %gned ipfins$v_i14_x : 1;) unsigned ipfins$v_i14_x2 : 2;& signed ipfins$v_i14_s : 1;- unsigned ipfins$v_i14_opcode : 4;, unsigned ipfins$v_i14_fill : 23; } ipfins$r_i14_0_63;& unsigned __int64 ipfins$q_i14; } ipfins$r_i14; } I14_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i14_qp ipfins$r_i14.ipfins$r_i14_0_63.ipfins$v_i14_qpF#define ipfins$v_i14_r1 ipfins$r_i14.ipfins$r_i14_0_63.ipfins$v_i14_r1F#define ipfi %ns$v_i14_13 ipfins$r_i14.ipfins$r_i14_0_63.ipfins$v_i14_13N#define ipfins$v_i14_cpos6b ipfins$r_i14.ipfins$r_i14_0_63.ipfins$v_i14_cpos6bF#define ipfins$v_i14_r3 ipfins$r_i14.ipfins$r_i14_0_63.ipfins$v_i14_r3L#define ipfins$v_i14_len6d ipfins$r_i14.ipfins$r_i14_0_63.ipfins$v_i14_len6dD#define ipfins$v_i14_x ipfins$r_i14.ipfins$r_i14_0_63.ipfins$v_i14_xF#define ipfins$v_i14_x2 ipfins$r_i14.ipfins$r_i14_0_63.ipfins$v_i14_x2D#define ipfins$v_i14_s ipfins$r_i14.ipfins$r_i14_0_63.ipfins$v_i14_sN#def %ine ipfins$v_i14_opcode ipfins$r_i14.ipfins$r_i14_0_63.ipfins$v_i14_opcode.#define ipfins$q_i14 ipfins$r_i14.ipfins$q_i14"#endif /* #if !defined(__VAXC) */ N/* */I/* I15: Deposit */N/* */#define IPFINS$M_I15_QP 0x3F#define IPFINS$M_I15_R1 0x1FC0#define IPFINS$M_I15_R2 0xFE000!#define IP%FINS$M_I15_R3 0x7F00000%#define IPFINS$M_I15_LEN4D 0x78000000(#define IPFINS$M_I15_CPOS6D 0x1F80000000)#define IPFINS$M_I15_OPCODE 0x1E000000000,#define IPFINS$M_I15_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i15_format {#pragma __nomember_alignment __union { __struct {) unsi%gned ipfins$v_i15_qp : 6;) unsigned ipfins$v_i15_r1 : 7;) unsigned ipfins$v_i15_r2 : 7;) unsigned ipfins$v_i15_r3 : 7;, unsigned ipfins$v_i15_len4d : 4;- unsigned ipfins$v_i15_cpos6d : 6;- unsigned ipfins$v_i15_opcode : 4;, unsigned ipfins$v_i15_fill : 23; } ipfins$r_i15_0_63;& unsigned __int64 ipfins$q_i15; } ipfins$r_i15; } I15_FORMAT; #if !defined(__VAXC)F#define ipfi%ns$v_i15_qp ipfins$r_i15.ipfins$r_i15_0_63.ipfins$v_i15_qpF#define ipfins$v_i15_r1 ipfins$r_i15.ipfins$r_i15_0_63.ipfins$v_i15_r1F#define ipfins$v_i15_r2 ipfins$r_i15.ipfins$r_i15_0_63.ipfins$v_i15_r2F#define ipfins$v_i15_r3 ipfins$r_i15.ipfins$r_i15_0_63.ipfins$v_i15_r3L#define ipfins$v_i15_len4d ipfins$r_i15.ipfins$r_i15_0_63.ipfins$v_i15_len4dN#define ipfins$v_i15_cpos6d ipfins$r_i15.ipfins$r_i15_0_63.ipfins$v_i15_cpos6dN#define ipfins$v_i15_opcode ipfins$r_i15.ipfins$r_i15_0_63.ipfins$v_i15_ %opcode.#define ipfins$q_i15 ipfins$r_i15.ipfins$q_i15"#endif /* #if !defined(__VAXC) */ N/* */I/* I16: Test Bit */N/* */#define IPFINS$M_I16_QP 0x3F#define IPFINS$M_I16_P1 0xFC0#define IPFINS$M_I16_C 0x1000#define IPFINS$M_I16_Y 0x2000"#define IPFINS$M_I16_POS6B 0xFC000!#define IPFI%NS$M_I16_R3 0x7F00000##define IPFINS$M_I16_P2 0x1F8000000##define IPFINS$M_I16_TA 0x200000000##define IPFINS$M_I16_X2 0xC00000000$#define IPFINS$M_I16_TB 0x1000000000)#define IPFINS$M_I16_OPCODE 0x1E000000000,#define IPFINS$M_I16_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i16_format {#pragma __nomemb%er_alignment __union { __struct {) unsigned ipfins$v_i16_qp : 6;) unsigned ipfins$v_i16_p1 : 6;( unsigned ipfins$v_i16_c : 1;( unsigned ipfins$v_i16_y : 1;, unsigned ipfins$v_i16_pos6b : 6;) unsigned ipfins$v_i16_r3 : 7;) unsigned ipfins$v_i16_p2 : 6;) unsigned ipfins$v_i16_ta : 1;) unsigned ipfins$v_i16_x2 : 2;) unsigned ipfins$v_i16_tb : 1;- unsi %gned ipfins$v_i16_opcode : 4;, unsigned ipfins$v_i16_fill : 23; } ipfins$r_i16_0_63;& unsigned __int64 ipfins$q_i16; } ipfins$r_i16; } I16_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i16_qp ipfins$r_i16.ipfins$r_i16_0_63.ipfins$v_i16_qpF#define ipfins$v_i16_p1 ipfins$r_i16.ipfins$r_i16_0_63.ipfins$v_i16_p1D#define ipfins$v_i16_c ipfins$r_i16.ipfins$r_i16_0_63.ipfins$v_i16_cD#define ipfins$v_i16_y ipfins$r_i16.ipfins$r_i16_0_63.ipfins$v_i16_y%L#define ipfins$v_i16_pos6b ipfins$r_i16.ipfins$r_i16_0_63.ipfins$v_i16_pos6bF#define ipfins$v_i16_r3 ipfins$r_i16.ipfins$r_i16_0_63.ipfins$v_i16_r3F#define ipfins$v_i16_p2 ipfins$r_i16.ipfins$r_i16_0_63.ipfins$v_i16_p2F#define ipfins$v_i16_ta ipfins$r_i16.ipfins$r_i16_0_63.ipfins$v_i16_taF#define ipfins$v_i16_x2 ipfins$r_i16.ipfins$r_i16_0_63.ipfins$v_i16_x2F#define ipfins$v_i16_tb ipfins$r_i16.ipfins$r_i16_0_63.ipfins$v_i16_tbN#define ipfins$v_i16_opcode ipfins$r_i16.ipfins$r_i16_0_63.ipfins$ %v_i16_opcode.#define ipfins$q_i16 ipfins$r_i16.ipfins$q_i16"#endif /* #if !defined(__VAXC) */ N/* */I/* I17: Test NaT */N/* */#define IPFINS$M_I17_QP 0x3F#define IPFINS$M_I17_P1 0xFC0#define IPFINS$M_I17_C 0x1000#define IPFINS$M_I17_Y 0x2000"#define IPFINS$M_I17_14_18 0x7C000#defin%e IPFINS$M_I17_X 0x80000!#define IPFINS$M_I17_R3 0x7F00000##define IPFINS$M_I17_P2 0x1F8000000##define IPFINS$M_I17_TA 0x200000000##define IPFINS$M_I17_X2 0xC00000000$#define IPFINS$M_I17_TB 0x1000000000)#define IPFINS$M_I17_OPCODE 0x1E000000000,#define IPFINS$M_I17_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef %struct _i17_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i17_qp : 6;) unsigned ipfins$v_i17_p1 : 6;( unsigned ipfins$v_i17_c : 1;( unsigned ipfins$v_i17_y : 1;, unsigned ipfins$v_i17_14_18 : 5;( unsigned ipfins$v_i17_x : 1;) unsigned ipfins$v_i17_r3 : 7;) unsigned ipfins$v_i17_p2 : 6;) unsigned ipfins$v_i17_ta : 1;) unsigned ipf %ins$v_i17_x2 : 2;) unsigned ipfins$v_i17_tb : 1;- unsigned ipfins$v_i17_opcode : 4;, unsigned ipfins$v_i17_fill : 23; } ipfins$r_i17_0_63;& unsigned __int64 ipfins$q_i17; } ipfins$r_i17; } I17_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i17_qp ipfins$r_i17.ipfins$r_i17_0_63.ipfins$v_i17_qpF#define ipfins$v_i17_p1 ipfins$r_i17.ipfins$r_i17_0_63.ipfins$v_i17_p1D#define ipfins$v_i17_c ipfins$r_i17.ipfins$r_i17_0_63.ipfi%ns$v_i17_cD#define ipfins$v_i17_y ipfins$r_i17.ipfins$r_i17_0_63.ipfins$v_i17_yL#define ipfins$v_i17_14_18 ipfins$r_i17.ipfins$r_i17_0_63.ipfins$v_i17_14_18D#define ipfins$v_i17_x ipfins$r_i17.ipfins$r_i17_0_63.ipfins$v_i17_xF#define ipfins$v_i17_r3 ipfins$r_i17.ipfins$r_i17_0_63.ipfins$v_i17_r3F#define ipfins$v_i17_p2 ipfins$r_i17.ipfins$r_i17_0_63.ipfins$v_i17_p2F#define ipfins$v_i17_ta ipfins$r_i17.ipfins$r_i17_0_63.ipfins$v_i17_taF#define ipfins$v_i17_x2 ipfins$r_i17.ipfins$r_i17_0_63.ipfin %s$v_i17_x2F#define ipfins$v_i17_tb ipfins$r_i17.ipfins$r_i17_0_63.ipfins$v_i17_tbN#define ipfins$v_i17_opcode ipfins$r_i17.ipfins$r_i17_0_63.ipfins$v_i17_opcode.#define ipfins$q_i17 ipfins$r_i17.ipfins$q_i17"#endif /* #if !defined(__VAXC) */ N/* */I/* I18: Nop/Hint (I-Unit) */N/* */#define IPFINS$M_I%18_QP 0x3F%#define IPFINS$M_I18_IMM20A 0x3FFFFC0 #define IPFINS$M_I18_Y 0x4000000##define IPFINS$M_I18_X6 0x1F8000000##define IPFINS$M_I18_X3 0xE00000000##define IPFINS$M_I18_I 0x1000000000)#define IPFINS$M_I18_OPCODE 0x1E000000000,#define IPFINS$M_I18_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i18_fo%rmat {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i18_qp : 6;. unsigned ipfins$v_i18_imm20a : 20;( unsigned ipfins$v_i18_y : 1;) unsigned ipfins$v_i18_x6 : 6;) unsigned ipfins$v_i18_x3 : 3;( unsigned ipfins$v_i18_i : 1;- unsigned ipfins$v_i18_opcode : 4;, unsigned ipfins$v_i18_fill : 23; } ipfins$r_i18_0_63;& unsigned __int64 ipfins$q_i18; % } ipfins$r_i18; } I18_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i18_qp ipfins$r_i18.ipfins$r_i18_0_63.ipfins$v_i18_qpN#define ipfins$v_i18_imm20a ipfins$r_i18.ipfins$r_i18_0_63.ipfins$v_i18_imm20aD#define ipfins$v_i18_y ipfins$r_i18.ipfins$r_i18_0_63.ipfins$v_i18_yF#define ipfins$v_i18_x6 ipfins$r_i18.ipfins$r_i18_0_63.ipfins$v_i18_x6F#define ipfins$v_i18_x3 ipfins$r_i18.ipfins$r_i18_0_63.ipfins$v_i18_x3D#define ipfins$v_i18_i ipfins$r_i18.ipfins$r_i18_0_63.ipfins$v_i18 %_iN#define ipfins$v_i18_opcode ipfins$r_i18.ipfins$r_i18_0_63.ipfins$v_i18_opcode.#define ipfins$q_i18 ipfins$r_i18.ipfins$q_i18"#endif /* #if !defined(__VAXC) */ N/* */I/* I19: Break (I-Unit) */N/* */#define IPFINS$M_I19_QP 0x3F%#define IPFINS$M_I19_IMM20A 0x3FFFFC0!#define IPFINS$M_I19_26 0x40!%00000##define IPFINS$M_I19_X6 0x1F8000000##define IPFINS$M_I19_X3 0xE00000000##define IPFINS$M_I19_I 0x1000000000)#define IPFINS$M_I19_OPCODE 0x1E000000000,#define IPFINS$M_I19_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i19_format {#pragma __nomember_alignment __union { __struct {) "% unsigned ipfins$v_i19_qp : 6;. unsigned ipfins$v_i19_imm20a : 20;) unsigned ipfins$v_i19_26 : 1;) unsigned ipfins$v_i19_x6 : 6;) unsigned ipfins$v_i19_x3 : 3;( unsigned ipfins$v_i19_i : 1;- unsigned ipfins$v_i19_opcode : 4;, unsigned ipfins$v_i19_fill : 23; } ipfins$r_i19_0_63;& unsigned __int64 ipfins$q_i19; } ipfins$r_i19; } I19_FORMAT; #if !defined(__VAXC)F#d#%efine ipfins$v_i19_qp ipfins$r_i19.ipfins$r_i19_0_63.ipfins$v_i19_qpN#define ipfins$v_i19_imm20a ipfins$r_i19.ipfins$r_i19_0_63.ipfins$v_i19_imm20aF#define ipfins$v_i19_26 ipfins$r_i19.ipfins$r_i19_0_63.ipfins$v_i19_26F#define ipfins$v_i19_x6 ipfins$r_i19.ipfins$r_i19_0_63.ipfins$v_i19_x6F#define ipfins$v_i19_x3 ipfins$r_i19.ipfins$r_i19_0_63.ipfins$v_i19_x3D#define ipfins$v_i19_i ipfins$r_i19.ipfins$r_i19_0_63.ipfins$v_i19_iN#define ipfins$v_i19_opcode ipfins$r_i19.ipfins$r_i19_0_63.ipfins$v_i1 $%9_opcode.#define ipfins$q_i19 ipfins$r_i19.ipfins$q_i19"#endif /* #if !defined(__VAXC) */ N/* */I/* I20: Integer Speculation Check (I-Unit) */N/* */#define IPFINS$M_I20_QP 0x3F!#define IPFINS$M_I20_IMM7A 0x1FC0#define IPFINS$M_I20_R2 0xFE000'#define IPFINS$M_I20_IMM13C 0x1FFF00000##define IPFINS$M_I20_X3 0xE000%%00000##define IPFINS$M_I20_S 0x1000000000)#define IPFINS$M_I20_OPCODE 0x1E000000000,#define IPFINS$M_I20_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i20_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i20_qp : 6;, unsigned ipfins$v_i20_&%imm7a : 7;) unsigned ipfins$v_i20_r2 : 7;. unsigned ipfins$v_i20_imm13c : 13;) unsigned ipfins$v_i20_x3 : 3;& signed ipfins$v_i20_s : 1;- unsigned ipfins$v_i20_opcode : 4;, unsigned ipfins$v_i20_fill : 23; } ipfins$r_i20_0_63;& unsigned __int64 ipfins$q_i20; } ipfins$r_i20; } I20_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i20_qp ipfins$r_i20.ipfins$r_i20_0_63.ipfins$v_i20_qpL#defin'%e ipfins$v_i20_imm7a ipfins$r_i20.ipfins$r_i20_0_63.ipfins$v_i20_imm7aF#define ipfins$v_i20_r2 ipfins$r_i20.ipfins$r_i20_0_63.ipfins$v_i20_r2N#define ipfins$v_i20_imm13c ipfins$r_i20.ipfins$r_i20_0_63.ipfins$v_i20_imm13cF#define ipfins$v_i20_x3 ipfins$r_i20.ipfins$r_i20_0_63.ipfins$v_i20_x3D#define ipfins$v_i20_s ipfins$r_i20.ipfins$r_i20_0_63.ipfins$v_i20_sN#define ipfins$v_i20_opcode ipfins$r_i20.ipfins$r_i20_0_63.ipfins$v_i20_opcode.#define ipfins$q_i20 ipfins$r_i20.ipfins$q_i20"#endif /* # (%if !defined(__VAXC) */ N/* */I/* I21: Move to BR */N/* */#define IPFINS$M_I21_QP 0x3F#define IPFINS$M_I21_B1 0x1C0#define IPFINS$M_I21_PBTV 0xE00#define IPFINS$M_I21_P 0x1000#define IPFINS$M_I21_R2 0xFE000 #define IPFINS$M_I21_WH 0x300000#define IPFINS$M_I21_X 0x400000 #define IPFI)%NS$M_I21_IH 0x800000'#define IPFINS$M_I21_TIMM9C 0x1FF000000##define IPFINS$M_I21_X3 0xE00000000$#define IPFINS$M_I21_36 0x1000000000)#define IPFINS$M_I21_OPCODE 0x1E000000000,#define IPFINS$M_I21_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i21_format {#pragma __nomember_alignment __union { *% __struct {) unsigned ipfins$v_i21_qp : 6;) unsigned ipfins$v_i21_b1 : 3;+ unsigned ipfins$v_i21_pbtv : 3;( unsigned ipfins$v_i21_p : 1;) unsigned ipfins$v_i21_r2 : 7;) unsigned ipfins$v_i21_wh : 2;( unsigned ipfins$v_i21_x : 1;) unsigned ipfins$v_i21_ih : 1;+ signed ipfins$v_i21_timm9c : 9;) unsigned ipfins$v_i21_x3 : 3;) unsigned ipfins$v_i21_36 : 1;- +% unsigned ipfins$v_i21_opcode : 4;, unsigned ipfins$v_i21_fill : 23; } ipfins$r_i21_0_63;& unsigned __int64 ipfins$q_i21; } ipfins$r_i21; } I21_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i21_qp ipfins$r_i21.ipfins$r_i21_0_63.ipfins$v_i21_qpF#define ipfins$v_i21_b1 ipfins$r_i21.ipfins$r_i21_0_63.ipfins$v_i21_b1J#define ipfins$v_i21_pbtv ipfins$r_i21.ipfins$r_i21_0_63.ipfins$v_i21_pbtvD#define ipfins$v_i21_p ipfins$r_i21.ipfins$r_i21_0_6,%3.ipfins$v_i21_pF#define ipfins$v_i21_r2 ipfins$r_i21.ipfins$r_i21_0_63.ipfins$v_i21_r2F#define ipfins$v_i21_wh ipfins$r_i21.ipfins$r_i21_0_63.ipfins$v_i21_whD#define ipfins$v_i21_x ipfins$r_i21.ipfins$r_i21_0_63.ipfins$v_i21_xF#define ipfins$v_i21_ih ipfins$r_i21.ipfins$r_i21_0_63.ipfins$v_i21_ihN#define ipfins$v_i21_timm9c ipfins$r_i21.ipfins$r_i21_0_63.ipfins$v_i21_timm9cF#define ipfins$v_i21_x3 ipfins$r_i21.ipfins$r_i21_0_63.ipfins$v_i21_x3F#define ipfins$v_i21_36 ipfins$r_i21.ipfins$r_i21_ -%0_63.ipfins$v_i21_36N#define ipfins$v_i21_opcode ipfins$r_i21.ipfins$r_i21_0_63.ipfins$v_i21_opcode.#define ipfins$q_i21 ipfins$r_i21.ipfins$q_i21"#endif /* #if !defined(__VAXC) */ N/* */I/* I22: Move from BR */N/* */#define IPFINS$M_I22_QP 0x3F#define IPFINS$M_I22_R1 0x1FC0#define IPFINS$M_I.%22_B2 0xE000$#define IPFINS$M_I22_16_26 0x7FF0000##define IPFINS$M_I22_X6 0x1F8000000##define IPFINS$M_I22_X3 0xE00000000$#define IPFINS$M_I22_36 0x1000000000)#define IPFINS$M_I22_OPCODE 0x1E000000000,#define IPFINS$M_I22_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i22_format {#pragma __nomember_alignme/%nt __union { __struct {) unsigned ipfins$v_i22_qp : 6;) unsigned ipfins$v_i22_r1 : 7;) unsigned ipfins$v_i22_b2 : 3;- unsigned ipfins$v_i22_16_26 : 11;) unsigned ipfins$v_i22_x6 : 6;) unsigned ipfins$v_i22_x3 : 3;) unsigned ipfins$v_i22_36 : 1;- unsigned ipfins$v_i22_opcode : 4;, unsigned ipfins$v_i22_fill : 23; } ipfins$r_i22_0_63;& unsigned __int64 0% ipfins$q_i22; } ipfins$r_i22; } I22_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i22_qp ipfins$r_i22.ipfins$r_i22_0_63.ipfins$v_i22_qpF#define ipfins$v_i22_r1 ipfins$r_i22.ipfins$r_i22_0_63.ipfins$v_i22_r1F#define ipfins$v_i22_b2 ipfins$r_i22.ipfins$r_i22_0_63.ipfins$v_i22_b2L#define ipfins$v_i22_16_26 ipfins$r_i22.ipfins$r_i22_0_63.ipfins$v_i22_16_26F#define ipfins$v_i22_x6 ipfins$r_i22.ipfins$r_i22_0_63.ipfins$v_i22_x6F#define ipfins$v_i22_x3 ipfins$r_i22.ipfins$r_i22_0_ 1%63.ipfins$v_i22_x3F#define ipfins$v_i22_36 ipfins$r_i22.ipfins$r_i22_0_63.ipfins$v_i22_36N#define ipfins$v_i22_opcode ipfins$r_i22.ipfins$r_i22_0_63.ipfins$v_i22_opcode.#define ipfins$q_i22 ipfins$r_i22.ipfins$q_i22"#endif /* #if !defined(__VAXC) */ N/* */I/* I23: Move to Predicates - Register */N/* */#define IP 2%FINS$M_I23_QP 0x3F"#define IPFINS$M_I23_MASK7A 0x1FC0#define IPFINS$M_I23_R2 0xFE000##define IPFINS$M_I23_20_23 0xF00000&#define IPFINS$M_I23_MASK8C 0xFF000000##define IPFINS$M_I23_32 0x100000000##define IPFINS$M_I23_X3 0xE00000000##define IPFINS$M_I23_S 0x1000000000)#define IPFINS$M_I23_OPCODE 0x1E000000000,#define IPFINS$M_I23_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment3% __quadword#else#pragma __nomember_alignment#endiftypedef struct _i23_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i23_qp : 6;- unsigned ipfins$v_i23_mask7a : 7;) unsigned ipfins$v_i23_r2 : 7;, unsigned ipfins$v_i23_20_23 : 4;- unsigned ipfins$v_i23_mask8c : 8;) unsigned ipfins$v_i23_32 : 1;) unsigned ipfins$v_i23_x3 : 3;& signed ipfins$v_i2 4%3_s : 1;- unsigned ipfins$v_i23_opcode : 4;, unsigned ipfins$v_i23_fill : 23; } ipfins$r_i23_0_63;& unsigned __int64 ipfins$q_i23; } ipfins$r_i23; } I23_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i23_qp ipfins$r_i23.ipfins$r_i23_0_63.ipfins$v_i23_qpN#define ipfins$v_i23_mask7a ipfins$r_i23.ipfins$r_i23_0_63.ipfins$v_i23_mask7aF#define ipfins$v_i23_r2 ipfins$r_i23.ipfins$r_i23_0_63.ipfins$v_i23_r2L#define ipfins$v_i23_20_23 ipfin 5%s$r_i23.ipfins$r_i23_0_63.ipfins$v_i23_20_23N#define ipfins$v_i23_mask8c ipfins$r_i23.ipfins$r_i23_0_63.ipfins$v_i23_mask8cF#define ipfins$v_i23_32 ipfins$r_i23.ipfins$r_i23_0_63.ipfins$v_i23_32F#define ipfins$v_i23_x3 ipfins$r_i23.ipfins$r_i23_0_63.ipfins$v_i23_x3D#define ipfins$v_i23_s ipfins$r_i23.ipfins$r_i23_0_63.ipfins$v_i23_sN#define ipfins$v_i23_opcode ipfins$r_i23.ipfins$r_i23_0_63.ipfins$v_i23_opcode.#define ipfins$q_i23 ipfins$r_i23.ipfins$q_i23"#endif /* #if !defined(__VAXC) */ 6%N/* */I/* I24: Move to Predicates - Immediate(44) */N/* */#define IPFINS$M_I24_QP 0x3F'#define IPFINS$M_I24_IMM27A 0x1FFFFFFC0##define IPFINS$M_I24_X3 0xE00000000##define IPFINS$M_I24_S 0x1000000000)#define IPFINS$M_I24_OPCODE 0x1E000000000,#define IPFINS$M_I24_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN7%_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i24_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i24_qp : 6;. unsigned ipfins$v_i24_imm27a : 27;) unsigned ipfins$v_i24_x3 : 3;& signed ipfins$v_i24_s : 1;- unsigned ipfins$v_i24_opcode : 4;, unsigned 8% ipfins$v_i24_fill : 23; } ipfins$r_i24_0_63;& unsigned __int64 ipfins$q_i24; } ipfins$r_i24; } I24_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i24_qp ipfins$r_i24.ipfins$r_i24_0_63.ipfins$v_i24_qpN#define ipfins$v_i24_imm27a ipfins$r_i24.ipfins$r_i24_0_63.ipfins$v_i24_imm27aF#define ipfins$v_i24_x3 ipfins$r_i24.ipfins$r_i24_0_63.ipfins$v_i24_x3D#define ipfins$v_i24_s ipfins$r_i24.ipfins$r_i24_0_63.ipfins$v_i24_sN#define ipfins$v_i24_opcode ipfins$r_i24 9%.ipfins$r_i24_0_63.ipfins$v_i24_opcode.#define ipfins$q_i24 ipfins$r_i24.ipfins$q_i24"#endif /* #if !defined(__VAXC) */ N/* */I/* I25: Move from Predicates/IP */N/* */#define IPFINS$M_I25_QP 0x3F#define IPFINS$M_I25_R1 0x1FC0$#define IPFINS$M_I25_13_26 0x7FFE000##define IPFINS$M_I25_X6 0x1F8000000##def:%ine IPFINS$M_I25_X3 0xE00000000$#define IPFINS$M_I25_36 0x1000000000)#define IPFINS$M_I25_OPCODE 0x1E000000000,#define IPFINS$M_I25_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i25_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i25_qp : 6;) ;% unsigned ipfins$v_i25_r1 : 7;- unsigned ipfins$v_i25_13_26 : 14;) unsigned ipfins$v_i25_x6 : 6;) unsigned ipfins$v_i25_x3 : 3;) unsigned ipfins$v_i25_36 : 1;- unsigned ipfins$v_i25_opcode : 4;, unsigned ipfins$v_i25_fill : 23; } ipfins$r_i25_0_63;& unsigned __int64 ipfins$q_i25; } ipfins$r_i25; } I25_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i25_qp ipfins$r_i25.ipfins$r_i25_<%0_63.ipfins$v_i25_qpF#define ipfins$v_i25_r1 ipfins$r_i25.ipfins$r_i25_0_63.ipfins$v_i25_r1L#define ipfins$v_i25_13_26 ipfins$r_i25.ipfins$r_i25_0_63.ipfins$v_i25_13_26F#define ipfins$v_i25_x6 ipfins$r_i25.ipfins$r_i25_0_63.ipfins$v_i25_x6F#define ipfins$v_i25_x3 ipfins$r_i25.ipfins$r_i25_0_63.ipfins$v_i25_x3F#define ipfins$v_i25_36 ipfins$r_i25.ipfins$r_i25_0_63.ipfins$v_i25_36N#define ipfins$v_i25_opcode ipfins$r_i25.ipfins$r_i25_0_63.ipfins$v_i25_opcode.#define ipfins$q_i25 ipfins$r_i25.ipfi =%ns$q_i25"#endif /* #if !defined(__VAXC) */ N/* */I/* I26: Move to AR - Register (I-Unit) */N/* */#define IPFINS$M_I26_QP 0x3F #define IPFINS$M_I26_6_12 0x1FC0#define IPFINS$M_I26_R2 0xFE000"#define IPFINS$M_I26_AR3 0x7F00000##define IPFINS$M_I26_X6 0x1F8000000##define IPFINS$M_I26_X3 0xE00000000$#define IP>%FINS$M_I26_36 0x1000000000)#define IPFINS$M_I26_OPCODE 0x1E000000000,#define IPFINS$M_I26_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i26_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i26_qp : 6;+ unsigned ipfins$v_i26_6_12 : 7;) ?% unsigned ipfins$v_i26_r2 : 7;* unsigned ipfins$v_i26_ar3 : 7;) unsigned ipfins$v_i26_x6 : 6;) unsigned ipfins$v_i26_x3 : 3;) unsigned ipfins$v_i26_36 : 1;- unsigned ipfins$v_i26_opcode : 4;, unsigned ipfins$v_i26_fill : 23; } ipfins$r_i26_0_63;& unsigned __int64 ipfins$q_i26; } ipfins$r_i26; } I26_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i26_qp ipfins$r_i26.ipfins$r_i26_0_@%63.ipfins$v_i26_qpJ#define ipfins$v_i26_6_12 ipfins$r_i26.ipfins$r_i26_0_63.ipfins$v_i26_6_12F#define ipfins$v_i26_r2 ipfins$r_i26.ipfins$r_i26_0_63.ipfins$v_i26_r2H#define ipfins$v_i26_ar3 ipfins$r_i26.ipfins$r_i26_0_63.ipfins$v_i26_ar3F#define ipfins$v_i26_x6 ipfins$r_i26.ipfins$r_i26_0_63.ipfins$v_i26_x6F#define ipfins$v_i26_x3 ipfins$r_i26.ipfins$r_i26_0_63.ipfins$v_i26_x3F#define ipfins$v_i26_36 ipfins$r_i26.ipfins$r_i26_0_63.ipfins$v_i26_36N#define ipfins$v_i26_opcode ipfins$r_i26.ipfins$ A%r_i26_0_63.ipfins$v_i26_opcode.#define ipfins$q_i26 ipfins$r_i26.ipfins$q_i26"#endif /* #if !defined(__VAXC) */ N/* */I/* I27: Move to AR - Immediate(8) (I-Unit) */N/* */#define IPFINS$M_I27_QP 0x3F #define IPFINS$M_I27_6_12 0x1FC0"#define IPFINS$M_I27_IMM7B 0xFE000"#define IPFINS$M_I27_AR3 0x7F00000##define IPFINSB%$M_I27_X6 0x1F8000000##define IPFINS$M_I27_X3 0xE00000000##define IPFINS$M_I27_S 0x1000000000)#define IPFINS$M_I27_OPCODE 0x1E000000000,#define IPFINS$M_I27_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i27_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfC%ins$v_i27_qp : 6;+ unsigned ipfins$v_i27_6_12 : 7;, unsigned ipfins$v_i27_imm7b : 7;* unsigned ipfins$v_i27_ar3 : 7;) unsigned ipfins$v_i27_x6 : 6;) unsigned ipfins$v_i27_x3 : 3;& signed ipfins$v_i27_s : 1;- unsigned ipfins$v_i27_opcode : 4;, unsigned ipfins$v_i27_fill : 23; } ipfins$r_i27_0_63;& unsigned __int64 ipfins$q_i27; } ipfins$r_i27; } I27_FORMAT; #if D%!defined(__VAXC)F#define ipfins$v_i27_qp ipfins$r_i27.ipfins$r_i27_0_63.ipfins$v_i27_qpJ#define ipfins$v_i27_6_12 ipfins$r_i27.ipfins$r_i27_0_63.ipfins$v_i27_6_12L#define ipfins$v_i27_imm7b ipfins$r_i27.ipfins$r_i27_0_63.ipfins$v_i27_imm7bH#define ipfins$v_i27_ar3 ipfins$r_i27.ipfins$r_i27_0_63.ipfins$v_i27_ar3F#define ipfins$v_i27_x6 ipfins$r_i27.ipfins$r_i27_0_63.ipfins$v_i27_x6F#define ipfins$v_i27_x3 ipfins$r_i27.ipfins$r_i27_0_63.ipfins$v_i27_x3D#define ipfins$v_i27_s ipfins$r_i27.ipfins$r E%_i27_0_63.ipfins$v_i27_sN#define ipfins$v_i27_opcode ipfins$r_i27.ipfins$r_i27_0_63.ipfins$v_i27_opcode.#define ipfins$q_i27 ipfins$r_i27.ipfins$q_i27"#endif /* #if !defined(__VAXC) */ N/* */I/* I28: Move from AR (I-Unit) */N/* */#define IPFINS$M_I28_QP 0x3F#define IPFINS$M_I28_R1 0x1FC0"#define IPFINSF%$M_I28_13_19 0xFE000"#define IPFINS$M_I28_AR3 0x7F00000##define IPFINS$M_I28_X6 0x1F8000000##define IPFINS$M_I28_X3 0xE00000000$#define IPFINS$M_I28_36 0x1000000000)#define IPFINS$M_I28_OPCODE 0x1E000000000,#define IPFINS$M_I28_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i28_format {#pragma __nomember_aG%lignment __union { __struct {) unsigned ipfins$v_i28_qp : 6;) unsigned ipfins$v_i28_r1 : 7;, unsigned ipfins$v_i28_13_19 : 7;* unsigned ipfins$v_i28_ar3 : 7;) unsigned ipfins$v_i28_x6 : 6;) unsigned ipfins$v_i28_x3 : 3;) unsigned ipfins$v_i28_36 : 1;- unsigned ipfins$v_i28_opcode : 4;, unsigned ipfins$v_i28_fill : 23; } ipfins$r_i28_0_63;& unsigned __i H%nt64 ipfins$q_i28; } ipfins$r_i28; } I28_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i28_qp ipfins$r_i28.ipfins$r_i28_0_63.ipfins$v_i28_qpF#define ipfins$v_i28_r1 ipfins$r_i28.ipfins$r_i28_0_63.ipfins$v_i28_r1L#define ipfins$v_i28_13_19 ipfins$r_i28.ipfins$r_i28_0_63.ipfins$v_i28_13_19H#define ipfins$v_i28_ar3 ipfins$r_i28.ipfins$r_i28_0_63.ipfins$v_i28_ar3F#define ipfins$v_i28_x6 ipfins$r_i28.ipfins$r_i28_0_63.ipfins$v_i28_x6F#define ipfins$v_i28_x3 ipfins$r_i28.ipfins$r_ I%i28_0_63.ipfins$v_i28_x3F#define ipfins$v_i28_36 ipfins$r_i28.ipfins$r_i28_0_63.ipfins$v_i28_36N#define ipfins$v_i28_opcode ipfins$r_i28.ipfins$r_i28_0_63.ipfins$v_i28_opcode.#define ipfins$q_i28 ipfins$r_i28.ipfins$q_i28"#endif /* #if !defined(__VAXC) */ N/* */I/* I29: Sign/Zero Extend/Compute Zero Index */N/* */#defJ%ine IPFINS$M_I29_QP 0x3F#define IPFINS$M_I29_R1 0x1FC0"#define IPFINS$M_I29_13_19 0xFE000!#define IPFINS$M_I29_R3 0x7F00000##define IPFINS$M_I29_X6 0x1F8000000##define IPFINS$M_I29_X3 0xE00000000$#define IPFINS$M_I29_36 0x1000000000)#define IPFINS$M_I29_OPCODE 0x1E000000000,#define IPFINS$M_I29_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomembK%er_alignment#endiftypedef struct _i29_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i29_qp : 6;) unsigned ipfins$v_i29_r1 : 7;, unsigned ipfins$v_i29_13_19 : 7;) unsigned ipfins$v_i29_r3 : 7;) unsigned ipfins$v_i29_x6 : 6;) unsigned ipfins$v_i29_x3 : 3;) unsigned ipfins$v_i29_36 : 1;- unsigned ipfins$v_i29_opcode : 4;, unsigned ipfins$ L%v_i29_fill : 23; } ipfins$r_i29_0_63;& unsigned __int64 ipfins$q_i29; } ipfins$r_i29; } I29_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i29_qp ipfins$r_i29.ipfins$r_i29_0_63.ipfins$v_i29_qpF#define ipfins$v_i29_r1 ipfins$r_i29.ipfins$r_i29_0_63.ipfins$v_i29_r1L#define ipfins$v_i29_13_19 ipfins$r_i29.ipfins$r_i29_0_63.ipfins$v_i29_13_19F#define ipfins$v_i29_r3 ipfins$r_i29.ipfins$r_i29_0_63.ipfins$v_i29_r3F#define ipfins$v_i29_x6 ipfins$r_i29.ipfins$r_i2 M%9_0_63.ipfins$v_i29_x6F#define ipfins$v_i29_x3 ipfins$r_i29.ipfins$r_i29_0_63.ipfins$v_i29_x3F#define ipfins$v_i29_36 ipfins$r_i29.ipfins$r_i29_0_63.ipfins$v_i29_36N#define ipfins$v_i29_opcode ipfins$r_i29.ipfins$r_i29_0_63.ipfins$v_i29_opcode.#define ipfins$q_i29 ipfins$r_i29.ipfins$q_i29"#endif /* #if !defined(__VAXC) */ N/* */N/* I30: Test Feature */N/* N% */#define IPFINS$M_I30_QP 0x3F#define IPFINS$M_I30_P1 0xFC0#define IPFINS$M_I30_C 0x1000#define IPFINS$M_I30_Y 0x2000"#define IPFINS$M_I30_IMM5B 0x7C000#define IPFINS$M_I30_X 0x80000##define IPFINS$M_I30_ZERO 0x7F00000##define IPFINS$M_I30_P2 0x1F8000000##define IPFINS$M_I30_TA 0x200000000##define IPFINS$M_I30_X2 0xC00000000$#define IPFINS$M_I30_TB 0x1000000000)#define IPFINS$M_I30_OPCODE 0x1E000000000,#define O%IPFINS$M_I30_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _i30_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_i30_qp : 6;) unsigned ipfins$v_i30_p1 : 6;( unsigned ipfins$v_i30_c : 1;( unsigned ipfins$v_i30_y : 1;, P% unsigned ipfins$v_i30_imm5b : 5;( unsigned ipfins$v_i30_x : 1;+ unsigned ipfins$v_i30_zero : 7;) unsigned ipfins$v_i30_p2 : 6;) unsigned ipfins$v_i30_ta : 1;) unsigned ipfins$v_i30_x2 : 2;) unsigned ipfins$v_i30_tb : 1;- unsigned ipfins$v_i30_opcode : 4;, unsigned ipfins$v_i30_fill : 23; } ipfins$r_i30_0_63;& unsigned __int64 ipfins$q_i30; } ipfins$r_i30; } Q%I30_FORMAT; #if !defined(__VAXC)F#define ipfins$v_i30_qp ipfins$r_i30.ipfins$r_i30_0_63.ipfins$v_i30_qpF#define ipfins$v_i30_p1 ipfins$r_i30.ipfins$r_i30_0_63.ipfins$v_i30_p1D#define ipfins$v_i30_c ipfins$r_i30.ipfins$r_i30_0_63.ipfins$v_i30_cD#define ipfins$v_i30_y ipfins$r_i30.ipfins$r_i30_0_63.ipfins$v_i30_yL#define ipfins$v_i30_imm5b ipfins$r_i30.ipfins$r_i30_0_63.ipfins$v_i30_imm5bD#define ipfins$v_i30_x ipfins$r_i30.ipfins$r_i30_0_63.ipfins$v_i30_xJ#define ipfins$v_i30_zero ipfins$r R%_i30.ipfins$r_i30_0_63.ipfins$v_i30_zeroF#define ipfins$v_i30_p2 ipfins$r_i30.ipfins$r_i30_0_63.ipfins$v_i30_p2F#define ipfins$v_i30_ta ipfins$r_i30.ipfins$r_i30_0_63.ipfins$v_i30_taF#define ipfins$v_i30_x2 ipfins$r_i30.ipfins$r_i30_0_63.ipfins$v_i30_x2F#define ipfins$v_i30_tb ipfins$r_i30.ipfins$r_i30_0_63.ipfins$v_i30_tbN#define ipfins$v_i30_opcode ipfins$r_i30.ipfins$r_i30_0_63.ipfins$v_i30_opcode.#define ipfins$q_i30 ipfins$r_i30.ipfins$q_i30"#endif /* #if !defined(__VAXC) */ N/* S% */I/* M-Unit Formats */N/* */N/* */I/* M1: Integer Load */N/* */#define IPFINS$M_M1_QP 0x3F#define IPFIT%NS$M_M1_R1 0x1FC0!#define IPFINS$M_M1_13_18 0x7E000#define IPFINS$M_M1_H 0x80000 #define IPFINS$M_M1_R3 0x7F00000#define IPFINS$M_M1_X 0x8000000##define IPFINS$M_M1_HINT 0x30000000"#define IPFINS$M_M1_X6 0xFC0000000"#define IPFINS$M_M1_M 0x1000000000(#define IPFINS$M_M1_OPCODE 0x1E000000000+#define IPFINS$M_M1_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#elsU%e#pragma __nomember_alignment#endiftypedef struct _m1_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_m1_qp : 6;( unsigned ipfins$v_m1_r1 : 7;+ unsigned ipfins$v_m1_13_18 : 6;' unsigned ipfins$v_m1_h : 1;( unsigned ipfins$v_m1_r3 : 7;' unsigned ipfins$v_m1_x : 1;* unsigned ipfins$v_m1_hint : 2;( unsigned ipfins$v_m1_x6 : 6;' unsigned ipf V%ins$v_m1_m : 1;, unsigned ipfins$v_m1_opcode : 4;+ unsigned ipfins$v_m1_fill : 23; } ipfins$r_m1_0_63;% unsigned __int64 ipfins$q_m1; } ipfins$r_m1; } M1_FORMAT; #if !defined(__VAXC)B#define ipfins$v_m1_qp ipfins$r_m1.ipfins$r_m1_0_63.ipfins$v_m1_qpB#define ipfins$v_m1_r1 ipfins$r_m1.ipfins$r_m1_0_63.ipfins$v_m1_r1H#define ipfins$v_m1_13_18 ipfins$r_m1.ipfins$r_m1_0_63.ipfins$v_m1_13_18@#define ipfins$v_m1_h ipfins$r_m1.ipfins$r_m W%1_0_63.ipfins$v_m1_hB#define ipfins$v_m1_r3 ipfins$r_m1.ipfins$r_m1_0_63.ipfins$v_m1_r3@#define ipfins$v_m1_x ipfins$r_m1.ipfins$r_m1_0_63.ipfins$v_m1_xF#define ipfins$v_m1_hint ipfins$r_m1.ipfins$r_m1_0_63.ipfins$v_m1_hintB#define ipfins$v_m1_x6 ipfins$r_m1.ipfins$r_m1_0_63.ipfins$v_m1_x6@#define ipfins$v_m1_m ipfins$r_m1.ipfins$r_m1_0_63.ipfins$v_m1_mJ#define ipfins$v_m1_opcode ipfins$r_m1.ipfins$r_m1_0_63.ipfins$v_m1_opcode+#define ipfins$q_m1 ipfins$r_m1.ipfins$q_m1"#endif /* #if !define X%d(__VAXC) */ N/* */I/* M2: Integer Load - Increment by Register */N/* */#define IPFINS$M_M2_QP 0x3F#define IPFINS$M_M2_R1 0x1FC0#define IPFINS$M_M2_R2 0xFE000 #define IPFINS$M_M2_R3 0x7F00000#define IPFINS$M_M2_X 0x8000000##define IPFINS$M_M2_HINT 0x30000000"#define IPFINS$M_M2_X6 0xFC0000000"#define IPFINS$MY%_M2_M 0x1000000000(#define IPFINS$M_M2_OPCODE 0x1E000000000+#define IPFINS$M_M2_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m2_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_m2_qp : 6;( unsigned ipfins$v_m2_r1 : 7;( unsigned iZ%pfins$v_m2_r2 : 7;( unsigned ipfins$v_m2_r3 : 7;' unsigned ipfins$v_m2_x : 1;* unsigned ipfins$v_m2_hint : 2;( unsigned ipfins$v_m2_x6 : 6;' unsigned ipfins$v_m2_m : 1;, unsigned ipfins$v_m2_opcode : 4;+ unsigned ipfins$v_m2_fill : 23; } ipfins$r_m2_0_63;% unsigned __int64 ipfins$q_m2; } ipfins$r_m2; } M2_FORMAT; #if !defined(__VAXC)B#define ipfins$v_m2_qp ipfins$r_m2.ipfin [%s$r_m2_0_63.ipfins$v_m2_qpB#define ipfins$v_m2_r1 ipfins$r_m2.ipfins$r_m2_0_63.ipfins$v_m2_r1B#define ipfins$v_m2_r2 ipfins$r_m2.ipfins$r_m2_0_63.ipfins$v_m2_r2B#define ipfins$v_m2_r3 ipfins$r_m2.ipfins$r_m2_0_63.ipfins$v_m2_r3@#define ipfins$v_m2_x ipfins$r_m2.ipfins$r_m2_0_63.ipfins$v_m2_xF#define ipfins$v_m2_hint ipfins$r_m2.ipfins$r_m2_0_63.ipfins$v_m2_hintB#define ipfins$v_m2_x6 ipfins$r_m2.ipfins$r_m2_0_63.ipfins$v_m2_x6@#define ipfins$v_m2_m ipfins$r_m2.ipfins$r_m2_0_63.ipfins$v_m2_mJ#d \%efine ipfins$v_m2_opcode ipfins$r_m2.ipfins$r_m2_0_63.ipfins$v_m2_opcode+#define ipfins$q_m2 ipfins$r_m2.ipfins$q_m2"#endif /* #if !defined(__VAXC) */ N/* */I/* M3: Integer Load - Increment by Immediate */N/* */#define IPFINS$M_M3_QP 0x3F#define IPFINS$M_M3_R1 0x1FC0!#define IPFINS$M_M3_IMM7B 0xFE000 #define IPFI]%NS$M_M3_R3 0x7F00000#define IPFINS$M_M3_I 0x8000000##define IPFINS$M_M3_HINT 0x30000000"#define IPFINS$M_M3_X6 0xFC0000000"#define IPFINS$M_M3_S 0x1000000000(#define IPFINS$M_M3_OPCODE 0x1E000000000+#define IPFINS$M_M3_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m3_format {#pragma __nomember_alignment^% __union { __struct {( unsigned ipfins$v_m3_qp : 6;( unsigned ipfins$v_m3_r1 : 7;+ unsigned ipfins$v_m3_imm7b : 7;( unsigned ipfins$v_m3_r3 : 7;' unsigned ipfins$v_m3_i : 1;* unsigned ipfins$v_m3_hint : 2;( unsigned ipfins$v_m3_x6 : 6;% signed ipfins$v_m3_s : 1;, unsigned ipfins$v_m3_opcode : 4;+ unsigned ipfins$v_m3_fill : 23; } ipfins$r_m3_0_63;% _% unsigned __int64 ipfins$q_m3; } ipfins$r_m3; } M3_FORMAT; #if !defined(__VAXC)B#define ipfins$v_m3_qp ipfins$r_m3.ipfins$r_m3_0_63.ipfins$v_m3_qpB#define ipfins$v_m3_r1 ipfins$r_m3.ipfins$r_m3_0_63.ipfins$v_m3_r1H#define ipfins$v_m3_imm7b ipfins$r_m3.ipfins$r_m3_0_63.ipfins$v_m3_imm7bB#define ipfins$v_m3_r3 ipfins$r_m3.ipfins$r_m3_0_63.ipfins$v_m3_r3@#define ipfins$v_m3_i ipfins$r_m3.ipfins$r_m3_0_63.ipfins$v_m3_iF#define ipfins$v_m3_hint ipfins$r_m3.ipfins$r_m3_0_63. `%ipfins$v_m3_hintB#define ipfins$v_m3_x6 ipfins$r_m3.ipfins$r_m3_0_63.ipfins$v_m3_x6@#define ipfins$v_m3_s ipfins$r_m3.ipfins$r_m3_0_63.ipfins$v_m3_sJ#define ipfins$v_m3_opcode ipfins$r_m3.ipfins$r_m3_0_63.ipfins$v_m3_opcode+#define ipfins$q_m3 ipfins$r_m3.ipfins$q_m3"#endif /* #if !defined(__VAXC) */ N/* */I/* M4: Integer Store */N/* a% */#define IPFINS$M_M4_QP 0x3F#define IPFINS$M_M4_6_11 0xFC0#define IPFINS$M_M4_H 0x1000#define IPFINS$M_M4_R2 0xFE000 #define IPFINS$M_M4_R3 0x7F00000#define IPFINS$M_M4_X 0x8000000##define IPFINS$M_M4_HINT 0x30000000"#define IPFINS$M_M4_X6 0xFC0000000"#define IPFINS$M_M4_M 0x1000000000(#define IPFINS$M_M4_OPCODE 0x1E000000000+#define IPFINS$M_M4_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* Ib%f using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m4_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_m4_qp : 6;* unsigned ipfins$v_m4_6_11 : 6;' unsigned ipfins$v_m4_h : 1;( unsigned ipfins$v_m4_r2 : 7;( unsigned ipfins$v_m4_r3 : 7;' unsigned ipfins$v_m4_x : 1;* unsigned ipfins$v_m4c%_hint : 2;( unsigned ipfins$v_m4_x6 : 6;' unsigned ipfins$v_m4_m : 1;, unsigned ipfins$v_m4_opcode : 4;+ unsigned ipfins$v_m4_fill : 23; } ipfins$r_m4_0_63;% unsigned __int64 ipfins$q_m4; } ipfins$r_m4; } M4_FORMAT; #if !defined(__VAXC)B#define ipfins$v_m4_qp ipfins$r_m4.ipfins$r_m4_0_63.ipfins$v_m4_qpF#define ipfins$v_m4_6_11 ipfins$r_m4.ipfins$r_m4_0_63.ipfins$v_m4_6_11@#define ipfins$v_m4_h ipfins$r_m4.ipd%fins$r_m4_0_63.ipfins$v_m4_hB#define ipfins$v_m4_r2 ipfins$r_m4.ipfins$r_m4_0_63.ipfins$v_m4_r2B#define ipfins$v_m4_r3 ipfins$r_m4.ipfins$r_m4_0_63.ipfins$v_m4_r3@#define ipfins$v_m4_x ipfins$r_m4.ipfins$r_m4_0_63.ipfins$v_m4_xF#define ipfins$v_m4_hint ipfins$r_m4.ipfins$r_m4_0_63.ipfins$v_m4_hintB#define ipfins$v_m4_x6 ipfins$r_m4.ipfins$r_m4_0_63.ipfins$v_m4_x6@#define ipfins$v_m4_m ipfins$r_m4.ipfins$r_m4_0_63.ipfins$v_m4_mJ#define ipfins$v_m4_opcode ipfins$r_m4.ipfins$r_m4_0_63.ipfins$v_m4_ e%opcode+#define ipfins$q_m4 ipfins$r_m4.ipfins$q_m4"#endif /* #if !defined(__VAXC) */ N/* */I/* M5: Integer Store - Increment by Immediate */N/* */#define IPFINS$M_M5_QP 0x3F #define IPFINS$M_M5_IMM7A 0x1FC0#define IPFINS$M_M5_R2 0xFE000 #define IPFINS$M_M5_R3 0x7F00000#define IPFINS$M_M5_I 0x8000000##define IPFIf%NS$M_M5_HINT 0x30000000"#define IPFINS$M_M5_X6 0xFC0000000"#define IPFINS$M_M5_S 0x1000000000(#define IPFINS$M_M5_OPCODE 0x1E000000000+#define IPFINS$M_M5_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m5_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$g%v_m5_qp : 6;+ unsigned ipfins$v_m5_imm7a : 7;( unsigned ipfins$v_m5_r2 : 7;( unsigned ipfins$v_m5_r3 : 7;' unsigned ipfins$v_m5_i : 1;* unsigned ipfins$v_m5_hint : 2;( unsigned ipfins$v_m5_x6 : 6;% signed ipfins$v_m5_s : 1;, unsigned ipfins$v_m5_opcode : 4;+ unsigned ipfins$v_m5_fill : 23; } ipfins$r_m5_0_63;% unsigned __int64 ipfins$q_m5; } ipfins$r_m5; h%} M5_FORMAT; #if !defined(__VAXC)B#define ipfins$v_m5_qp ipfins$r_m5.ipfins$r_m5_0_63.ipfins$v_m5_qpH#define ipfins$v_m5_imm7a ipfins$r_m5.ipfins$r_m5_0_63.ipfins$v_m5_imm7aB#define ipfins$v_m5_r2 ipfins$r_m5.ipfins$r_m5_0_63.ipfins$v_m5_r2B#define ipfins$v_m5_r3 ipfins$r_m5.ipfins$r_m5_0_63.ipfins$v_m5_r3@#define ipfins$v_m5_i ipfins$r_m5.ipfins$r_m5_0_63.ipfins$v_m5_iF#define ipfins$v_m5_hint ipfins$r_m5.ipfins$r_m5_0_63.ipfins$v_m5_hintB#define ipfins$v_m5_x6 ipfins$r_m5.ipfins$r_m5_0_6 i%3.ipfins$v_m5_x6@#define ipfins$v_m5_s ipfins$r_m5.ipfins$r_m5_0_63.ipfins$v_m5_sJ#define ipfins$v_m5_opcode ipfins$r_m5.ipfins$r_m5_0_63.ipfins$v_m5_opcode+#define ipfins$q_m5 ipfins$r_m5.ipfins$q_m5"#endif /* #if !defined(__VAXC) */ N/* */I/* M6: Floating-point Load */N/* */#define IPFINS$M_M6_QP 0j%x3F#define IPFINS$M_M6_F1 0x1FC0!#define IPFINS$M_M6_13_18 0x7E000#define IPFINS$M_M6_H 0x80000 #define IPFINS$M_M6_R3 0x7F00000#define IPFINS$M_M6_X 0x8000000##define IPFINS$M_M6_HINT 0x30000000"#define IPFINS$M_M6_X6 0xFC0000000"#define IPFINS$M_M6_M 0x1000000000(#define IPFINS$M_M6_OPCODE 0x1E000000000+#define IPFINS$M_M6_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignmentk% __quadword#else#pragma __nomember_alignment#endiftypedef struct _m6_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_m6_qp : 6;( unsigned ipfins$v_m6_f1 : 7;+ unsigned ipfins$v_m6_13_18 : 6;' unsigned ipfins$v_m6_h : 1;( unsigned ipfins$v_m6_r3 : 7;' unsigned ipfins$v_m6_x : 1;* unsigned ipfins$v_m6_hint : 2;( unsigned ipfins$v_m6_x6 : 6;' l% unsigned ipfins$v_m6_m : 1;, unsigned ipfins$v_m6_opcode : 4;+ unsigned ipfins$v_m6_fill : 23; } ipfins$r_m6_0_63;% unsigned __int64 ipfins$q_m6; } ipfins$r_m6; } M6_FORMAT; #if !defined(__VAXC)B#define ipfins$v_m6_qp ipfins$r_m6.ipfins$r_m6_0_63.ipfins$v_m6_qpB#define ipfins$v_m6_f1 ipfins$r_m6.ipfins$r_m6_0_63.ipfins$v_m6_f1H#define ipfins$v_m6_13_18 ipfins$r_m6.ipfins$r_m6_0_63.ipfins$v_m6_13_18@#define ipfins$v_m6_h ipfi m%ns$r_m6.ipfins$r_m6_0_63.ipfins$v_m6_hB#define ipfins$v_m6_r3 ipfins$r_m6.ipfins$r_m6_0_63.ipfins$v_m6_r3@#define ipfins$v_m6_x ipfins$r_m6.ipfins$r_m6_0_63.ipfins$v_m6_xF#define ipfins$v_m6_hint ipfins$r_m6.ipfins$r_m6_0_63.ipfins$v_m6_hintB#define ipfins$v_m6_x6 ipfins$r_m6.ipfins$r_m6_0_63.ipfins$v_m6_x6@#define ipfins$v_m6_m ipfins$r_m6.ipfins$r_m6_0_63.ipfins$v_m6_mJ#define ipfins$v_m6_opcode ipfins$r_m6.ipfins$r_m6_0_63.ipfins$v_m6_opcode+#define ipfins$q_m6 ipfins$r_m6.ipfins$q_m6"#end n%if /* #if !defined(__VAXC) */ N/* */I/* M7: Floating-point Load - Increment by Register */N/* */#define IPFINS$M_M7_QP 0x3F#define IPFINS$M_M7_F1 0x1FC0#define IPFINS$M_M7_R2 0xFE000 #define IPFINS$M_M7_R3 0x7F00000#define IPFINS$M_M7_X 0x8000000##define IPFINS$M_M7_HINT 0x30000000"#define IPFINS$M_M7_X6 0xFC0000000o%"#define IPFINS$M_M7_M 0x1000000000(#define IPFINS$M_M7_OPCODE 0x1E000000000+#define IPFINS$M_M7_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m7_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_m7_qp : 6;( unsigned ipfins$v_m7_f1 : 7;( p% unsigned ipfins$v_m7_r2 : 7;( unsigned ipfins$v_m7_r3 : 7;' unsigned ipfins$v_m7_x : 1;* unsigned ipfins$v_m7_hint : 2;( unsigned ipfins$v_m7_x6 : 6;' unsigned ipfins$v_m7_m : 1;, unsigned ipfins$v_m7_opcode : 4;+ unsigned ipfins$v_m7_fill : 23; } ipfins$r_m7_0_63;% unsigned __int64 ipfins$q_m7; } ipfins$r_m7; } M7_FORMAT; #if !defined(__VAXC)B#define ipfins$v_m7_qpq% ipfins$r_m7.ipfins$r_m7_0_63.ipfins$v_m7_qpB#define ipfins$v_m7_f1 ipfins$r_m7.ipfins$r_m7_0_63.ipfins$v_m7_f1B#define ipfins$v_m7_r2 ipfins$r_m7.ipfins$r_m7_0_63.ipfins$v_m7_r2B#define ipfins$v_m7_r3 ipfins$r_m7.ipfins$r_m7_0_63.ipfins$v_m7_r3@#define ipfins$v_m7_x ipfins$r_m7.ipfins$r_m7_0_63.ipfins$v_m7_xF#define ipfins$v_m7_hint ipfins$r_m7.ipfins$r_m7_0_63.ipfins$v_m7_hintB#define ipfins$v_m7_x6 ipfins$r_m7.ipfins$r_m7_0_63.ipfins$v_m7_x6@#define ipfins$v_m7_m ipfins$r_m7.ipfins$r_m7_0_63 r%.ipfins$v_m7_mJ#define ipfins$v_m7_opcode ipfins$r_m7.ipfins$r_m7_0_63.ipfins$v_m7_opcode+#define ipfins$q_m7 ipfins$r_m7.ipfins$q_m7"#endif /* #if !defined(__VAXC) */ N/* */I/* M8: Floating-point Load - Increment by Immediate */N/* */#define IPFINS$M_M8_QP 0x3F#define IPFINS$M_M8_F1 0x1FC0!#define IPFINS$M_M8_IMM7B 0xFEs%000 #define IPFINS$M_M8_R3 0x7F00000#define IPFINS$M_M8_I 0x8000000##define IPFINS$M_M8_HINT 0x30000000"#define IPFINS$M_M8_X6 0xFC0000000"#define IPFINS$M_M8_S 0x1000000000(#define IPFINS$M_M8_OPCODE 0x1E000000000+#define IPFINS$M_M8_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m8_format {#pragma __t%nomember_alignment __union { __struct {( unsigned ipfins$v_m8_qp : 6;( unsigned ipfins$v_m8_f1 : 7;+ unsigned ipfins$v_m8_imm7b : 7;( unsigned ipfins$v_m8_r3 : 7;' unsigned ipfins$v_m8_i : 1;* unsigned ipfins$v_m8_hint : 2;( unsigned ipfins$v_m8_x6 : 6;% signed ipfins$v_m8_s : 1;, unsigned ipfins$v_m8_opcode : 4;+ unsigned ipfins$v_m8_fill : 23; } ip u%fins$r_m8_0_63;% unsigned __int64 ipfins$q_m8; } ipfins$r_m8; } M8_FORMAT; #if !defined(__VAXC)B#define ipfins$v_m8_qp ipfins$r_m8.ipfins$r_m8_0_63.ipfins$v_m8_qpB#define ipfins$v_m8_f1 ipfins$r_m8.ipfins$r_m8_0_63.ipfins$v_m8_f1H#define ipfins$v_m8_imm7b ipfins$r_m8.ipfins$r_m8_0_63.ipfins$v_m8_imm7bB#define ipfins$v_m8_r3 ipfins$r_m8.ipfins$r_m8_0_63.ipfins$v_m8_r3@#define ipfins$v_m8_i ipfins$r_m8.ipfins$r_m8_0_63.ipfins$v_m8_iF#define ipfins$v_m8_hint ipfins$r_m8 v%.ipfins$r_m8_0_63.ipfins$v_m8_hintB#define ipfins$v_m8_x6 ipfins$r_m8.ipfins$r_m8_0_63.ipfins$v_m8_x6@#define ipfins$v_m8_s ipfins$r_m8.ipfins$r_m8_0_63.ipfins$v_m8_sJ#define ipfins$v_m8_opcode ipfins$r_m8.ipfins$r_m8_0_63.ipfins$v_m8_opcode+#define ipfins$q_m8 ipfins$r_m8.ipfins$q_m8"#endif /* #if !defined(__VAXC) */ N/* */I/* M9: Floating-point Store */N/* w% */#define IPFINS$M_M9_QP 0x3F#define IPFINS$M_M9_6_11 0xFC0#define IPFINS$M_M9_H 0x1000#define IPFINS$M_M9_F2 0xFE000 #define IPFINS$M_M9_R3 0x7F00000#define IPFINS$M_M9_X 0x8000000##define IPFINS$M_M9_HINT 0x30000000"#define IPFINS$M_M9_X6 0xFC0000000"#define IPFINS$M_M9_M 0x1000000000(#define IPFINS$M_M9_OPCODE 0x1E000000000+#define IPFINS$M_M9_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(_x%_cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m9_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_m9_qp : 6;* unsigned ipfins$v_m9_6_11 : 6;' unsigned ipfins$v_m9_h : 1;( unsigned ipfins$v_m9_f2 : 7;( unsigned ipfins$v_m9_r3 : 7;' unsigned ipfins$v_m9_x : 1;* uny%signed ipfins$v_m9_hint : 2;( unsigned ipfins$v_m9_x6 : 6;' unsigned ipfins$v_m9_m : 1;, unsigned ipfins$v_m9_opcode : 4;+ unsigned ipfins$v_m9_fill : 23; } ipfins$r_m9_0_63;% unsigned __int64 ipfins$q_m9; } ipfins$r_m9; } M9_FORMAT; #if !defined(__VAXC)B#define ipfins$v_m9_qp ipfins$r_m9.ipfins$r_m9_0_63.ipfins$v_m9_qpF#define ipfins$v_m9_6_11 ipfins$r_m9.ipfins$r_m9_0_63.ipfins$v_m9_6_11@#define ipfins$v_mz%9_h ipfins$r_m9.ipfins$r_m9_0_63.ipfins$v_m9_hB#define ipfins$v_m9_f2 ipfins$r_m9.ipfins$r_m9_0_63.ipfins$v_m9_f2B#define ipfins$v_m9_r3 ipfins$r_m9.ipfins$r_m9_0_63.ipfins$v_m9_r3@#define ipfins$v_m9_x ipfins$r_m9.ipfins$r_m9_0_63.ipfins$v_m9_xF#define ipfins$v_m9_hint ipfins$r_m9.ipfins$r_m9_0_63.ipfins$v_m9_hintB#define ipfins$v_m9_x6 ipfins$r_m9.ipfins$r_m9_0_63.ipfins$v_m9_x6@#define ipfins$v_m9_m ipfins$r_m9.ipfins$r_m9_0_63.ipfins$v_m9_mJ#define ipfins$v_m9_opcode ipfins$r_m9.ipfins$r_m9 {%_0_63.ipfins$v_m9_opcode+#define ipfins$q_m9 ipfins$r_m9.ipfins$q_m9"#endif /* #if !defined(__VAXC) */ N/* */I/* M10: Floating-point Store - Increment by Immediate */N/* */#define IPFINS$M_M10_QP 0x3F!#define IPFINS$M_M10_IMM7A 0x1FC0#define IPFINS$M_M10_F2 0xFE000!#define IPFINS$M_M10_R3 0x7F00000 #define IPFINS$M_M10_I|% 0x8000000$#define IPFINS$M_M10_HINT 0x30000000##define IPFINS$M_M10_X6 0xFC0000000##define IPFINS$M_M10_S 0x1000000000)#define IPFINS$M_M10_OPCODE 0x1E000000000,#define IPFINS$M_M10_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m10_format {#pragma __nomember_alignment __union { __struct { }%) unsigned ipfins$v_m10_qp : 6;, unsigned ipfins$v_m10_imm7a : 7;) unsigned ipfins$v_m10_f2 : 7;) unsigned ipfins$v_m10_r3 : 7;( unsigned ipfins$v_m10_i : 1;+ unsigned ipfins$v_m10_hint : 2;) unsigned ipfins$v_m10_x6 : 6;& signed ipfins$v_m10_s : 1;- unsigned ipfins$v_m10_opcode : 4;, unsigned ipfins$v_m10_fill : 23; } ipfins$r_m10_0_63;& unsigned __int64 i ~%pfins$q_m10; } ipfins$r_m10; } M10_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m10_qp ipfins$r_m10.ipfins$r_m10_0_63.ipfins$v_m10_qpL#define ipfins$v_m10_imm7a ipfins$r_m10.ipfins$r_m10_0_63.ipfins$v_m10_imm7aF#define ipfins$v_m10_f2 ipfins$r_m10.ipfins$r_m10_0_63.ipfins$v_m10_f2F#define ipfins$v_m10_r3 ipfins$r_m10.ipfins$r_m10_0_63.ipfins$v_m10_r3D#define ipfins$v_m10_i ipfins$r_m10.ipfins$r_m10_0_63.ipfins$v_m10_iJ#define ipfins$v_m10_hint ipfins$r_m10.ipfins$r_m10_0_63 %.ipfins$v_m10_hintF#define ipfins$v_m10_x6 ipfins$r_m10.ipfins$r_m10_0_63.ipfins$v_m10_x6D#define ipfins$v_m10_s ipfins$r_m10.ipfins$r_m10_0_63.ipfins$v_m10_sN#define ipfins$v_m10_opcode ipfins$r_m10.ipfins$r_m10_0_63.ipfins$v_m10_opcode.#define ipfins$q_m10 ipfins$r_m10.ipfins$q_m10"#endif /* #if !defined(__VAXC) */ N/* */I/* M11: Floating-point Load Pair */N/* % */#define IPFINS$M_M11_QP 0x3F#define IPFINS$M_M11_F1 0x1FC0#define IPFINS$M_M11_F2 0xFE000!#define IPFINS$M_M11_R3 0x7F00000 #define IPFINS$M_M11_X 0x8000000$#define IPFINS$M_M11_HINT 0x30000000##define IPFINS$M_M11_X6 0xFC0000000##define IPFINS$M_M11_M 0x1000000000)#define IPFINS$M_M11_OPCODE 0x1E000000000,#define IPFINS$M_M11_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If us%ing pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m11_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m11_qp : 6;) unsigned ipfins$v_m11_f1 : 7;) unsigned ipfins$v_m11_f2 : 7;) unsigned ipfins$v_m11_r3 : 7;( unsigned ipfins$v_m11_x : 1;+ unsigned ipfins$v_m11_hint : 2;) unsigned ipfin %s$v_m11_x6 : 6;( unsigned ipfins$v_m11_m : 1;- unsigned ipfins$v_m11_opcode : 4;, unsigned ipfins$v_m11_fill : 23; } ipfins$r_m11_0_63;& unsigned __int64 ipfins$q_m11; } ipfins$r_m11; } M11_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m11_qp ipfins$r_m11.ipfins$r_m11_0_63.ipfins$v_m11_qpF#define ipfins$v_m11_f1 ipfins$r_m11.ipfins$r_m11_0_63.ipfins$v_m11_f1F#define ipfins$v_m11_f2 ipfins$r_m11.ipfins$r_m11_0_63.ipfins$ %v_m11_f2F#define ipfins$v_m11_r3 ipfins$r_m11.ipfins$r_m11_0_63.ipfins$v_m11_r3D#define ipfins$v_m11_x ipfins$r_m11.ipfins$r_m11_0_63.ipfins$v_m11_xJ#define ipfins$v_m11_hint ipfins$r_m11.ipfins$r_m11_0_63.ipfins$v_m11_hintF#define ipfins$v_m11_x6 ipfins$r_m11.ipfins$r_m11_0_63.ipfins$v_m11_x6D#define ipfins$v_m11_m ipfins$r_m11.ipfins$r_m11_0_63.ipfins$v_m11_mN#define ipfins$v_m11_opcode ipfins$r_m11.ipfins$r_m11_0_63.ipfins$v_m11_opcode.#define ipfins$q_m11 ipfins$r_m11.ipfins$q_m11"#endif %/* #if !defined(__VAXC) */ N/* */I/* M12: Floating-point Load Pair - Increment by Immediate */N/* */#define IPFINS$M_M12_QP 0x3F#define IPFINS$M_M12_F1 0x1FC0#define IPFINS$M_M12_F2 0xFE000!#define IPFINS$M_M12_R3 0x7F00000 #define IPFINS$M_M12_X 0x8000000$#define IPFINS$M_M12_HINT 0x30000000##define IPFINS$M_M12_X6 0xFC000000%0##define IPFINS$M_M12_M 0x1000000000)#define IPFINS$M_M12_OPCODE 0x1E000000000,#define IPFINS$M_M12_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m12_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m12_qp : 6;) unsigned ipfins$v_m12_f1 :% 7;) unsigned ipfins$v_m12_f2 : 7;) unsigned ipfins$v_m12_r3 : 7;( unsigned ipfins$v_m12_x : 1;+ unsigned ipfins$v_m12_hint : 2;) unsigned ipfins$v_m12_x6 : 6;( unsigned ipfins$v_m12_m : 1;- unsigned ipfins$v_m12_opcode : 4;, unsigned ipfins$v_m12_fill : 23; } ipfins$r_m12_0_63;& unsigned __int64 ipfins$q_m12; } ipfins$r_m12; } M12_FORMAT; #if !defined(__VAXC)%F#define ipfins$v_m12_qp ipfins$r_m12.ipfins$r_m12_0_63.ipfins$v_m12_qpF#define ipfins$v_m12_f1 ipfins$r_m12.ipfins$r_m12_0_63.ipfins$v_m12_f1F#define ipfins$v_m12_f2 ipfins$r_m12.ipfins$r_m12_0_63.ipfins$v_m12_f2F#define ipfins$v_m12_r3 ipfins$r_m12.ipfins$r_m12_0_63.ipfins$v_m12_r3D#define ipfins$v_m12_x ipfins$r_m12.ipfins$r_m12_0_63.ipfins$v_m12_xJ#define ipfins$v_m12_hint ipfins$r_m12.ipfins$r_m12_0_63.ipfins$v_m12_hintF#define ipfins$v_m12_x6 ipfins$r_m12.ipfins$r_m12_0_63.ipfins$v_m12_x6 %D#define ipfins$v_m12_m ipfins$r_m12.ipfins$r_m12_0_63.ipfins$v_m12_mN#define ipfins$v_m12_opcode ipfins$r_m12.ipfins$r_m12_0_63.ipfins$v_m12_opcode.#define ipfins$q_m12 ipfins$r_m12.ipfins$q_m12"#endif /* #if !defined(__VAXC) */ N/* */I/* M13: Line Prefetch */N/* */#define IPFINS$M_M13_QP 0x3F %#define IPFINS$M_M13_6_11 0xFC0#define IPFINS$M_M13_H 0x1000"#define IPFINS$M_M13_13_19 0xFE000!#define IPFINS$M_M13_R3 0x7F00000 #define IPFINS$M_M13_X 0x8000000$#define IPFINS$M_M13_HINT 0x30000000##define IPFINS$M_M13_X6 0xFC0000000##define IPFINS$M_M13_M 0x1000000000)#define IPFINS$M_M13_OPCODE 0x1E000000000,#define IPFINS$M_M13_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_align%ment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m13_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m13_qp : 6;+ unsigned ipfins$v_m13_6_11 : 6;( unsigned ipfins$v_m13_h : 1;, unsigned ipfins$v_m13_13_19 : 7;) unsigned ipfins$v_m13_r3 : 7;( unsigned ipfins$v_m13_x : 1;+ unsigned ipfins$v_m13_hint : 2;) unsigned ipfins$v_m13_ %x6 : 6;( unsigned ipfins$v_m13_m : 1;- unsigned ipfins$v_m13_opcode : 4;, unsigned ipfins$v_m13_fill : 23; } ipfins$r_m13_0_63;& unsigned __int64 ipfins$q_m13; } ipfins$r_m13; } M13_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m13_qp ipfins$r_m13.ipfins$r_m13_0_63.ipfins$v_m13_qpJ#define ipfins$v_m13_6_11 ipfins$r_m13.ipfins$r_m13_0_63.ipfins$v_m13_6_11D#define ipfins$v_m13_h ipfins$r_m13.ipfins$r_m13_0_63.ipfins$v_m13%_hL#define ipfins$v_m13_13_19 ipfins$r_m13.ipfins$r_m13_0_63.ipfins$v_m13_13_19F#define ipfins$v_m13_r3 ipfins$r_m13.ipfins$r_m13_0_63.ipfins$v_m13_r3D#define ipfins$v_m13_x ipfins$r_m13.ipfins$r_m13_0_63.ipfins$v_m13_xJ#define ipfins$v_m13_hint ipfins$r_m13.ipfins$r_m13_0_63.ipfins$v_m13_hintF#define ipfins$v_m13_x6 ipfins$r_m13.ipfins$r_m13_0_63.ipfins$v_m13_x6D#define ipfins$v_m13_m ipfins$r_m13.ipfins$r_m13_0_63.ipfins$v_m13_mN#define ipfins$v_m13_opcode ipfins$r_m13.ipfins$r_m13_0_63.ipfin %s$v_m13_opcode.#define ipfins$q_m13 ipfins$r_m13.ipfins$q_m13"#endif /* #if !defined(__VAXC) */ N/* */I/* M14: Line Prefetch - Increment by Register */N/* */#define IPFINS$M_M14_QP 0x3F#define IPFINS$M_M14_6_11 0xFC0#define IPFINS$M_M14_H 0x1000#define IPFINS$M_M14_R2 0xFE000!#define IPFINS$M_M14_R3 0x7F00000 %#define IPFINS$M_M14_X 0x8000000$#define IPFINS$M_M14_HINT 0x30000000##define IPFINS$M_M14_X6 0xFC0000000##define IPFINS$M_M14_M 0x1000000000)#define IPFINS$M_M14_OPCODE 0x1E000000000,#define IPFINS$M_M14_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m14_format {#pragma __nomember_alignment __union { % __struct {) unsigned ipfins$v_m14_qp : 6;+ unsigned ipfins$v_m14_6_11 : 6;( unsigned ipfins$v_m14_h : 1;) unsigned ipfins$v_m14_r2 : 7;) unsigned ipfins$v_m14_r3 : 7;( unsigned ipfins$v_m14_x : 1;+ unsigned ipfins$v_m14_hint : 2;) unsigned ipfins$v_m14_x6 : 6;( unsigned ipfins$v_m14_m : 1;- unsigned ipfins$v_m14_opcode : 4;, unsigned ipfins$v_m14_fill : % 23; } ipfins$r_m14_0_63;& unsigned __int64 ipfins$q_m14; } ipfins$r_m14; } M14_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m14_qp ipfins$r_m14.ipfins$r_m14_0_63.ipfins$v_m14_qpJ#define ipfins$v_m14_6_11 ipfins$r_m14.ipfins$r_m14_0_63.ipfins$v_m14_6_11D#define ipfins$v_m14_h ipfins$r_m14.ipfins$r_m14_0_63.ipfins$v_m14_hF#define ipfins$v_m14_r2 ipfins$r_m14.ipfins$r_m14_0_63.ipfins$v_m14_r2F#define ipfins$v_m14_r3 ipfins$r_m14.ipfins$r_m14_0_63.ipfins$v_ %m14_r3D#define ipfins$v_m14_x ipfins$r_m14.ipfins$r_m14_0_63.ipfins$v_m14_xJ#define ipfins$v_m14_hint ipfins$r_m14.ipfins$r_m14_0_63.ipfins$v_m14_hintF#define ipfins$v_m14_x6 ipfins$r_m14.ipfins$r_m14_0_63.ipfins$v_m14_x6D#define ipfins$v_m14_m ipfins$r_m14.ipfins$r_m14_0_63.ipfins$v_m14_mN#define ipfins$v_m14_opcode ipfins$r_m14.ipfins$r_m14_0_63.ipfins$v_m14_opcode.#define ipfins$q_m14 ipfins$r_m14.ipfins$q_m14"#endif /* #if !defined(__VAXC) */ N/* % */I/* M15: Line Prefetch - Increment by Immediate */N/* */#define IPFINS$M_M15_QP 0x3F#define IPFINS$M_M15_6_11 0xFC0#define IPFINS$M_M15_H 0x1000"#define IPFINS$M_M15_IMM7B 0xFE000!#define IPFINS$M_M15_R3 0x7F00000 #define IPFINS$M_M15_I 0x8000000$#define IPFINS$M_M15_HINT 0x30000000##define IPFINS$M_M15_X6 0xFC0000000##define IPFINS$M_M15_S 0x100000000%0)#define IPFINS$M_M15_OPCODE 0x1E000000000,#define IPFINS$M_M15_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m15_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m15_qp : 6;+ unsigned ipfins$v_m15_6_11 : 6;( unsigned ipfins$v_%m15_h : 1;, unsigned ipfins$v_m15_imm7b : 7;) unsigned ipfins$v_m15_r3 : 7;( unsigned ipfins$v_m15_i : 1;+ unsigned ipfins$v_m15_hint : 2;) unsigned ipfins$v_m15_x6 : 6;& signed ipfins$v_m15_s : 1;- unsigned ipfins$v_m15_opcode : 4;, unsigned ipfins$v_m15_fill : 23; } ipfins$r_m15_0_63;& unsigned __int64 ipfins$q_m15; } ipfins$r_m15; } M15_FORMAT; #if !defined(_%_VAXC)F#define ipfins$v_m15_qp ipfins$r_m15.ipfins$r_m15_0_63.ipfins$v_m15_qpJ#define ipfins$v_m15_6_11 ipfins$r_m15.ipfins$r_m15_0_63.ipfins$v_m15_6_11D#define ipfins$v_m15_h ipfins$r_m15.ipfins$r_m15_0_63.ipfins$v_m15_hL#define ipfins$v_m15_imm7b ipfins$r_m15.ipfins$r_m15_0_63.ipfins$v_m15_imm7bF#define ipfins$v_m15_r3 ipfins$r_m15.ipfins$r_m15_0_63.ipfins$v_m15_r3D#define ipfins$v_m15_i ipfins$r_m15.ipfins$r_m15_0_63.ipfins$v_m15_iJ#define ipfins$v_m15_hint ipfins$r_m15.ipfins$r_m15_0_63.ipf %ins$v_m15_hintF#define ipfins$v_m15_x6 ipfins$r_m15.ipfins$r_m15_0_63.ipfins$v_m15_x6D#define ipfins$v_m15_s ipfins$r_m15.ipfins$r_m15_0_63.ipfins$v_m15_sN#define ipfins$v_m15_opcode ipfins$r_m15.ipfins$r_m15_0_63.ipfins$v_m15_opcode.#define ipfins$q_m15 ipfins$r_m15.ipfins$q_m15"#endif /* #if !defined(__VAXC) */ N/* */I/* M16: Exchange/Compare and Exchange */N/* % */#define IPFINS$M_M16_QP 0x3F#define IPFINS$M_M16_R1 0x1FC0#define IPFINS$M_M16_R2 0xFE000!#define IPFINS$M_M16_R3 0x7F00000 #define IPFINS$M_M16_X 0x8000000$#define IPFINS$M_M16_HINT 0x30000000##define IPFINS$M_M16_X6 0xFC0000000##define IPFINS$M_M16_M 0x1000000000)#define IPFINS$M_M16_OPCODE 0x1E000000000,#define IPFINS$M_M16_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using %pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m16_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m16_qp : 6;) unsigned ipfins$v_m16_r1 : 7;) unsigned ipfins$v_m16_r2 : 7;) unsigned ipfins$v_m16_r3 : 7;( unsigned ipfins$v_m16_x : 1;+ unsigned ipfins$v_m16_hint : 2;) unsigned ipfins$v_ %m16_x6 : 6;( unsigned ipfins$v_m16_m : 1;- unsigned ipfins$v_m16_opcode : 4;, unsigned ipfins$v_m16_fill : 23; } ipfins$r_m16_0_63;& unsigned __int64 ipfins$q_m16; } ipfins$r_m16; } M16_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m16_qp ipfins$r_m16.ipfins$r_m16_0_63.ipfins$v_m16_qpF#define ipfins$v_m16_r1 ipfins$r_m16.ipfins$r_m16_0_63.ipfins$v_m16_r1F#define ipfins$v_m16_r2 ipfins$r_m16.ipfins$r_m16_0_63.ipfins$v_m1 %6_r2F#define ipfins$v_m16_r3 ipfins$r_m16.ipfins$r_m16_0_63.ipfins$v_m16_r3D#define ipfins$v_m16_x ipfins$r_m16.ipfins$r_m16_0_63.ipfins$v_m16_xJ#define ipfins$v_m16_hint ipfins$r_m16.ipfins$r_m16_0_63.ipfins$v_m16_hintF#define ipfins$v_m16_x6 ipfins$r_m16.ipfins$r_m16_0_63.ipfins$v_m16_x6D#define ipfins$v_m16_m ipfins$r_m16.ipfins$r_m16_0_63.ipfins$v_m16_mN#define ipfins$v_m16_opcode ipfins$r_m16.ipfins$r_m16_0_63.ipfins$v_m16_opcode.#define ipfins$q_m16 ipfins$r_m16.ipfins$q_m16"#endif /* # %if !defined(__VAXC) */ N/* */I/* M17: Fetch and Add - Immediate */N/* */#define IPFINS$M_M17_QP 0x3F#define IPFINS$M_M17_R1 0x1FC0#define IPFINS$M_M17_I2B 0x6000#define IPFINS$M_M17_S 0x8000"#define IPFINS$M_M17_16_19 0xF0000!#define IPFINS$M_M17_R3 0x7F00000 #define IPFINS$M_M17_X 0x8000000$#define %IPFINS$M_M17_HINT 0x30000000##define IPFINS$M_M17_X6 0xFC0000000##define IPFINS$M_M17_M 0x1000000000)#define IPFINS$M_M17_OPCODE 0x1E000000000,#define IPFINS$M_M17_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m17_format {#pragma __nomember_alignment __union { __struct {) unsign %ed ipfins$v_m17_qp : 6;) unsigned ipfins$v_m17_r1 : 7;* unsigned ipfins$v_m17_i2b : 2;& signed ipfins$v_m17_s : 1;, unsigned ipfins$v_m17_16_19 : 4;) unsigned ipfins$v_m17_r3 : 7;( unsigned ipfins$v_m17_x : 1;+ unsigned ipfins$v_m17_hint : 2;) unsigned ipfins$v_m17_x6 : 6;( unsigned ipfins$v_m17_m : 1;- unsigned ipfins$v_m17_opcode : 4;, unsigned ipfins$v_m17_fill : % 23; } ipfins$r_m17_0_63;& unsigned __int64 ipfins$q_m17; } ipfins$r_m17; } M17_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m17_qp ipfins$r_m17.ipfins$r_m17_0_63.ipfins$v_m17_qpF#define ipfins$v_m17_r1 ipfins$r_m17.ipfins$r_m17_0_63.ipfins$v_m17_r1H#define ipfins$v_m17_i2b ipfins$r_m17.ipfins$r_m17_0_63.ipfins$v_m17_i2bD#define ipfins$v_m17_s ipfins$r_m17.ipfins$r_m17_0_63.ipfins$v_m17_sL#define ipfins$v_m17_16_19 ipfins$r_m17.ipfins$r_m17_0_63.ipfins$v %_m17_16_19F#define ipfins$v_m17_r3 ipfins$r_m17.ipfins$r_m17_0_63.ipfins$v_m17_r3D#define ipfins$v_m17_x ipfins$r_m17.ipfins$r_m17_0_63.ipfins$v_m17_xJ#define ipfins$v_m17_hint ipfins$r_m17.ipfins$r_m17_0_63.ipfins$v_m17_hintF#define ipfins$v_m17_x6 ipfins$r_m17.ipfins$r_m17_0_63.ipfins$v_m17_x6D#define ipfins$v_m17_m ipfins$r_m17.ipfins$r_m17_0_63.ipfins$v_m17_mN#define ipfins$v_m17_opcode ipfins$r_m17.ipfins$r_m17_0_63.ipfins$v_m17_opcode.#define ipfins$q_m17 ipfins$r_m17.ipfins$q_m17"#endif % /* #if !defined(__VAXC) */ N/* */I/* M18: Set FR */N/* */#define IPFINS$M_M18_QP 0x3F#define IPFINS$M_M18_F1 0x1FC0#define IPFINS$M_M18_R2 0xFE000$#define IPFINS$M_M18_20_26 0x7F00000 #define IPFINS$M_M18_X 0x8000000%#define IPFINS$M_M18_28_29 0x30000000##define IPFINS$M_M18_X6 0xFC%0000000##define IPFINS$M_M18_M 0x1000000000)#define IPFINS$M_M18_OPCODE 0x1E000000000,#define IPFINS$M_M18_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m18_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m18_qp : 6;) unsigned ipfins$v_m1%8_f1 : 7;) unsigned ipfins$v_m18_r2 : 7;, unsigned ipfins$v_m18_20_26 : 7;( unsigned ipfins$v_m18_x : 1;, unsigned ipfins$v_m18_28_29 : 2;) unsigned ipfins$v_m18_x6 : 6;( unsigned ipfins$v_m18_m : 1;- unsigned ipfins$v_m18_opcode : 4;, unsigned ipfins$v_m18_fill : 23; } ipfins$r_m18_0_63;& unsigned __int64 ipfins$q_m18; } ipfins$r_m18; } M18_FORMAT; #if !defined%(__VAXC)F#define ipfins$v_m18_qp ipfins$r_m18.ipfins$r_m18_0_63.ipfins$v_m18_qpF#define ipfins$v_m18_f1 ipfins$r_m18.ipfins$r_m18_0_63.ipfins$v_m18_f1F#define ipfins$v_m18_r2 ipfins$r_m18.ipfins$r_m18_0_63.ipfins$v_m18_r2L#define ipfins$v_m18_20_26 ipfins$r_m18.ipfins$r_m18_0_63.ipfins$v_m18_20_26D#define ipfins$v_m18_x ipfins$r_m18.ipfins$r_m18_0_63.ipfins$v_m18_xL#define ipfins$v_m18_28_29 ipfins$r_m18.ipfins$r_m18_0_63.ipfins$v_m18_28_29F#define ipfins$v_m18_x6 ipfins$r_m18.ipfins$r_m18_0_63 %.ipfins$v_m18_x6D#define ipfins$v_m18_m ipfins$r_m18.ipfins$r_m18_0_63.ipfins$v_m18_mN#define ipfins$v_m18_opcode ipfins$r_m18.ipfins$r_m18_0_63.ipfins$v_m18_opcode.#define ipfins$q_m18 ipfins$r_m18.ipfins$q_m18"#endif /* #if !defined(__VAXC) */ N/* */I/* M19: Get FR */N/* */#define IPFINS %$M_M19_QP 0x3F#define IPFINS$M_M19_R1 0x1FC0#define IPFINS$M_M19_F2 0xFE000$#define IPFINS$M_M19_20_26 0x7F00000 #define IPFINS$M_M19_X 0x8000000%#define IPFINS$M_M19_28_29 0x30000000##define IPFINS$M_M19_X6 0xFC0000000##define IPFINS$M_M19_M 0x1000000000)#define IPFINS$M_M19_OPCODE 0x1E000000000,#define IPFINS$M_M19_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword%#else#pragma __nomember_alignment#endiftypedef struct _m19_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m19_qp : 6;) unsigned ipfins$v_m19_r1 : 7;) unsigned ipfins$v_m19_f2 : 7;, unsigned ipfins$v_m19_20_26 : 7;( unsigned ipfins$v_m19_x : 1;, unsigned ipfins$v_m19_28_29 : 2;) unsigned ipfins$v_m19_x6 : 6;( unsigned ipfins$v_m19_m : 1;- % unsigned ipfins$v_m19_opcode : 4;, unsigned ipfins$v_m19_fill : 23; } ipfins$r_m19_0_63;& unsigned __int64 ipfins$q_m19; } ipfins$r_m19; } M19_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m19_qp ipfins$r_m19.ipfins$r_m19_0_63.ipfins$v_m19_qpF#define ipfins$v_m19_r1 ipfins$r_m19.ipfins$r_m19_0_63.ipfins$v_m19_r1F#define ipfins$v_m19_f2 ipfins$r_m19.ipfins$r_m19_0_63.ipfins$v_m19_f2L#define ipfins$v_m19_20_26 ipfins$r_m19.ipfins$r_m19_0_63. %ipfins$v_m19_20_26D#define ipfins$v_m19_x ipfins$r_m19.ipfins$r_m19_0_63.ipfins$v_m19_xL#define ipfins$v_m19_28_29 ipfins$r_m19.ipfins$r_m19_0_63.ipfins$v_m19_28_29F#define ipfins$v_m19_x6 ipfins$r_m19.ipfins$r_m19_0_63.ipfins$v_m19_x6D#define ipfins$v_m19_m ipfins$r_m19.ipfins$r_m19_0_63.ipfins$v_m19_mN#define ipfins$v_m19_opcode ipfins$r_m19.ipfins$r_m19_0_63.ipfins$v_m19_opcode.#define ipfins$q_m19 ipfins$r_m19.ipfins$q_m19"#endif /* #if !defined(__VAXC) */ N/* % */I/* M20: Integer Speculation Check (M-Unit) */N/* */#define IPFINS$M_M20_QP 0x3F!#define IPFINS$M_M20_IMM7A 0x1FC0#define IPFINS$M_M20_R2 0xFE000'#define IPFINS$M_M20_IMM13C 0x1FFF00000##define IPFINS$M_M20_X3 0xE00000000##define IPFINS$M_M20_S 0x1000000000)#define IPFINS$M_M20_OPCODE 0x1E000000000,#define IPFINS$M_M20_FILL 0xFFFFFE00%00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m20_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m20_qp : 6;, unsigned ipfins$v_m20_imm7a : 7;) unsigned ipfins$v_m20_r2 : 7;. unsigned ipfins$v_m20_imm13c : 13;) unsigned i %pfins$v_m20_x3 : 3;& signed ipfins$v_m20_s : 1;- unsigned ipfins$v_m20_opcode : 4;, unsigned ipfins$v_m20_fill : 23; } ipfins$r_m20_0_63;& unsigned __int64 ipfins$q_m20; } ipfins$r_m20; } M20_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m20_qp ipfins$r_m20.ipfins$r_m20_0_63.ipfins$v_m20_qpL#define ipfins$v_m20_imm7a ipfins$r_m20.ipfins$r_m20_0_63.ipfins$v_m20_imm7aF#define ipfins$v_m20_r2 ipfins$r_m20.ipfins$r_m20_0_63 %.ipfins$v_m20_r2N#define ipfins$v_m20_imm13c ipfins$r_m20.ipfins$r_m20_0_63.ipfins$v_m20_imm13cF#define ipfins$v_m20_x3 ipfins$r_m20.ipfins$r_m20_0_63.ipfins$v_m20_x3D#define ipfins$v_m20_s ipfins$r_m20.ipfins$r_m20_0_63.ipfins$v_m20_sN#define ipfins$v_m20_opcode ipfins$r_m20.ipfins$r_m20_0_63.ipfins$v_m20_opcode.#define ipfins$q_m20 ipfins$r_m20.ipfins$q_m20"#endif /* #if !defined(__VAXC) */ N/* */I/* M21: Floating-p %oint Speculation Check */N/* */#define IPFINS$M_M21_QP 0x3F!#define IPFINS$M_M21_IMM7A 0x1FC0#define IPFINS$M_M21_F2 0xFE000'#define IPFINS$M_M21_IMM13C 0x1FFF00000##define IPFINS$M_M21_X3 0xE00000000##define IPFINS$M_M21_S 0x1000000000)#define IPFINS$M_M21_OPCODE 0x1E000000000,#define IPFINS$M_M21_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplus%plus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m21_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m21_qp : 6;, unsigned ipfins$v_m21_imm7a : 7;) unsigned ipfins$v_m21_f2 : 7;. unsigned ipfins$v_m21_imm13c : 13;) unsigned ipfins$v_m21_x3 : 3;& signed ipfins$v_m21_s : 1;- % unsigned ipfins$v_m21_opcode : 4;, unsigned ipfins$v_m21_fill : 23; } ipfins$r_m21_0_63;& unsigned __int64 ipfins$q_m21; } ipfins$r_m21; } M21_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m21_qp ipfins$r_m21.ipfins$r_m21_0_63.ipfins$v_m21_qpL#define ipfins$v_m21_imm7a ipfins$r_m21.ipfins$r_m21_0_63.ipfins$v_m21_imm7aF#define ipfins$v_m21_f2 ipfins$r_m21.ipfins$r_m21_0_63.ipfins$v_m21_f2N#define ipfins$v_m21_imm13c ipfins$r_m21.ipfins$r_m2 %1_0_63.ipfins$v_m21_imm13cF#define ipfins$v_m21_x3 ipfins$r_m21.ipfins$r_m21_0_63.ipfins$v_m21_x3D#define ipfins$v_m21_s ipfins$r_m21.ipfins$r_m21_0_63.ipfins$v_m21_sN#define ipfins$v_m21_opcode ipfins$r_m21.ipfins$r_m21_0_63.ipfins$v_m21_opcode.#define ipfins$q_m21 ipfins$r_m21.ipfins$q_m21"#endif /* #if !defined(__VAXC) */ N/* */I/* M22: Integer Advanced Load Check */N/* % */#define IPFINS$M_M22_QP 0x3F#define IPFINS$M_M22_R1 0x1FC0'#define IPFINS$M_M22_IMM20B 0x1FFFFE000##define IPFINS$M_M22_X3 0xE00000000##define IPFINS$M_M22_S 0x1000000000)#define IPFINS$M_M22_OPCODE 0x1E000000000,#define IPFINS$M_M22_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __no%member_alignment#endiftypedef struct _m22_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m22_qp : 6;) unsigned ipfins$v_m22_r1 : 7;. unsigned ipfins$v_m22_imm20b : 20;) unsigned ipfins$v_m22_x3 : 3;& signed ipfins$v_m22_s : 1;- unsigned ipfins$v_m22_opcode : 4;, unsigned ipfins$v_m22_fill : 23; } ipfins$r_m22_0_63;& unsigned __int64 ipfins$q_ %m22; } ipfins$r_m22; } M22_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m22_qp ipfins$r_m22.ipfins$r_m22_0_63.ipfins$v_m22_qpF#define ipfins$v_m22_r1 ipfins$r_m22.ipfins$r_m22_0_63.ipfins$v_m22_r1N#define ipfins$v_m22_imm20b ipfins$r_m22.ipfins$r_m22_0_63.ipfins$v_m22_imm20bF#define ipfins$v_m22_x3 ipfins$r_m22.ipfins$r_m22_0_63.ipfins$v_m22_x3D#define ipfins$v_m22_s ipfins$r_m22.ipfins$r_m22_0_63.ipfins$v_m22_sN#define ipfins$v_m22_opcode ipfins$r_m22.ipfins$r_m22_0_63.ipf %ins$v_m22_opcode.#define ipfins$q_m22 ipfins$r_m22.ipfins$q_m22"#endif /* #if !defined(__VAXC) */ N/* */I/* M23: Floating-point Advanced Load Check */N/* */#define IPFINS$M_M23_QP 0x3F#define IPFINS$M_M23_F1 0x1FC0'#define IPFINS$M_M23_IMM20B 0x1FFFFE000##define IPFINS$M_M23_X3 0xE00000000##define IPFINS$M_M23_S% 0x1000000000)#define IPFINS$M_M23_OPCODE 0x1E000000000,#define IPFINS$M_M23_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m23_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m23_qp : 6;) unsigned ipfins$v_m23_f1 : 7;. unsigned% ipfins$v_m23_imm20b : 20;) unsigned ipfins$v_m23_x3 : 3;& signed ipfins$v_m23_s : 1;- unsigned ipfins$v_m23_opcode : 4;, unsigned ipfins$v_m23_fill : 23; } ipfins$r_m23_0_63;& unsigned __int64 ipfins$q_m23; } ipfins$r_m23; } M23_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m23_qp ipfins$r_m23.ipfins$r_m23_0_63.ipfins$v_m23_qpF#define ipfins$v_m23_f1 ipfins$r_m23.ipfins$r_m23_0_63.ipfins$v_m23_f1N#define ip %fins$v_m23_imm20b ipfins$r_m23.ipfins$r_m23_0_63.ipfins$v_m23_imm20bF#define ipfins$v_m23_x3 ipfins$r_m23.ipfins$r_m23_0_63.ipfins$v_m23_x3D#define ipfins$v_m23_s ipfins$r_m23.ipfins$r_m23_0_63.ipfins$v_m23_sN#define ipfins$v_m23_opcode ipfins$r_m23.ipfins$r_m23_0_63.ipfins$v_m23_opcode.#define ipfins$q_m23 ipfins$r_m23.ipfins$q_m23"#endif /* #if !defined(__VAXC) */ N/* */I/* M24: Sync/Fence/Serialize/ALAT Control % */N/* */#define IPFINS$M_M24_QP 0x3F##define IPFINS$M_M24_6_26 0x7FFFFC0"#define IPFINS$M_M24_X4 0x78000000##define IPFINS$M_M24_X2 0x180000000##define IPFINS$M_M24_X3 0xE00000000$#define IPFINS$M_M24_36 0x1000000000)#define IPFINS$M_M24_OPCODE 0x1E000000000,#define IPFINS$M_M24_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC% V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m24_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m24_qp : 6;, unsigned ipfins$v_m24_6_26 : 21;) unsigned ipfins$v_m24_x4 : 4;) unsigned ipfins$v_m24_x2 : 2;) unsigned ipfins$v_m24_x3 : 3;) unsigned ipfins$v_m24_36 : 1;- unsigned ipfins$v_m24_op %code : 4;, unsigned ipfins$v_m24_fill : 23; } ipfins$r_m24_0_63;& unsigned __int64 ipfins$q_m24; } ipfins$r_m24; } M24_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m24_qp ipfins$r_m24.ipfins$r_m24_0_63.ipfins$v_m24_qpJ#define ipfins$v_m24_6_26 ipfins$r_m24.ipfins$r_m24_0_63.ipfins$v_m24_6_26F#define ipfins$v_m24_x4 ipfins$r_m24.ipfins$r_m24_0_63.ipfins$v_m24_x4F#define ipfins$v_m24_x2 ipfins$r_m24.ipfins$r_m24_0_63.ipfins$v_m24_x2F#define ip %fins$v_m24_x3 ipfins$r_m24.ipfins$r_m24_0_63.ipfins$v_m24_x3F#define ipfins$v_m24_36 ipfins$r_m24.ipfins$r_m24_0_63.ipfins$v_m24_36N#define ipfins$v_m24_opcode ipfins$r_m24.ipfins$r_m24_0_63.ipfins$v_m24_opcode.#define ipfins$q_m24 ipfins$r_m24.ipfins$q_m24"#endif /* #if !defined(__VAXC) */ N/* */I/* M25: RSE Control */N/* % */#define IPFINS$M_M25_ZERO 0x3F##define IPFINS$M_M25_6_26 0x7FFFFC0"#define IPFINS$M_M25_X4 0x78000000##define IPFINS$M_M25_X2 0x180000000##define IPFINS$M_M25_X3 0xE00000000$#define IPFINS$M_M25_36 0x1000000000)#define IPFINS$M_M25_OPCODE 0x1E000000000,#define IPFINS$M_M25_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma %__nomember_alignment#endiftypedef struct _m25_format {#pragma __nomember_alignment __union { __struct {+ unsigned ipfins$v_m25_zero : 6;, unsigned ipfins$v_m25_6_26 : 21;) unsigned ipfins$v_m25_x4 : 4;) unsigned ipfins$v_m25_x2 : 2;) unsigned ipfins$v_m25_x3 : 3;) unsigned ipfins$v_m25_36 : 1;- unsigned ipfins$v_m25_opcode : 4;, unsigned ipfins$v_m25_fill : 23; } ip %fins$r_m25_0_63;& unsigned __int64 ipfins$q_m25; } ipfins$r_m25; } M25_FORMAT; #if !defined(__VAXC)J#define ipfins$v_m25_zero ipfins$r_m25.ipfins$r_m25_0_63.ipfins$v_m25_zeroJ#define ipfins$v_m25_6_26 ipfins$r_m25.ipfins$r_m25_0_63.ipfins$v_m25_6_26F#define ipfins$v_m25_x4 ipfins$r_m25.ipfins$r_m25_0_63.ipfins$v_m25_x4F#define ipfins$v_m25_x2 ipfins$r_m25.ipfins$r_m25_0_63.ipfins$v_m25_x2F#define ipfins$v_m25_x3 ipfins$r_m25.ipfins$r_m25_0_63.ipfins$v_m25_x3F#define %ipfins$v_m25_36 ipfins$r_m25.ipfins$r_m25_0_63.ipfins$v_m25_36N#define ipfins$v_m25_opcode ipfins$r_m25.ipfins$r_m25_0_63.ipfins$v_m25_opcode.#define ipfins$q_m25 ipfins$r_m25.ipfins$q_m25"#endif /* #if !defined(__VAXC) */ N/* */I/* M26: Integer ALAT Entry Invalidate */N/* */#define IPFINS$M_M26_QP 0x3F#define %IPFINS$M_M26_R1 0x1FC0$#define IPFINS$M_M26_13_26 0x7FFE000"#define IPFINS$M_M26_X4 0x78000000##define IPFINS$M_M26_X2 0x180000000##define IPFINS$M_M26_X3 0xE00000000$#define IPFINS$M_M26_36 0x1000000000)#define IPFINS$M_M26_OPCODE 0x1E000000000,#define IPFINS$M_M26_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef st%ruct _m26_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m26_qp : 6;) unsigned ipfins$v_m26_r1 : 7;- unsigned ipfins$v_m26_13_26 : 14;) unsigned ipfins$v_m26_x4 : 4;) unsigned ipfins$v_m26_x2 : 2;) unsigned ipfins$v_m26_x3 : 3;) unsigned ipfins$v_m26_36 : 1;- unsigned ipfins$v_m26_opcode : 4;, unsigned ipfins$v_m26_fill : 23; %} ipfins$r_m26_0_63;& unsigned __int64 ipfins$q_m26; } ipfins$r_m26; } M26_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m26_qp ipfins$r_m26.ipfins$r_m26_0_63.ipfins$v_m26_qpF#define ipfins$v_m26_r1 ipfins$r_m26.ipfins$r_m26_0_63.ipfins$v_m26_r1L#define ipfins$v_m26_13_26 ipfins$r_m26.ipfins$r_m26_0_63.ipfins$v_m26_13_26F#define ipfins$v_m26_x4 ipfins$r_m26.ipfins$r_m26_0_63.ipfins$v_m26_x4F#define ipfins$v_m26_x2 ipfins$r_m26.ipfins$r_m26_0_63.ipfins$v_m26_x2F#defin %e ipfins$v_m26_x3 ipfins$r_m26.ipfins$r_m26_0_63.ipfins$v_m26_x3F#define ipfins$v_m26_36 ipfins$r_m26.ipfins$r_m26_0_63.ipfins$v_m26_36N#define ipfins$v_m26_opcode ipfins$r_m26.ipfins$r_m26_0_63.ipfins$v_m26_opcode.#define ipfins$q_m26 ipfins$r_m26.ipfins$q_m26"#endif /* #if !defined(__VAXC) */ N/* */I/* M27: Floating-point ALAT Entry Invalidate */N/* % */#define IPFINS$M_M27_QP 0x3F#define IPFINS$M_M27_F1 0x1FC0$#define IPFINS$M_M27_13_26 0x7FFE000"#define IPFINS$M_M27_X4 0x78000000##define IPFINS$M_M27_X2 0x180000000##define IPFINS$M_M27_X3 0xE00000000$#define IPFINS$M_M27_36 0x1000000000)#define IPFINS$M_M27_OPCODE 0x1E000000000,#define IPFINS$M_M27_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_align%ment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m27_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m27_qp : 6;) unsigned ipfins$v_m27_f1 : 7;- unsigned ipfins$v_m27_13_26 : 14;) unsigned ipfins$v_m27_x4 : 4;) unsigned ipfins$v_m27_x2 : 2;) unsigned ipfins$v_m27_x3 : 3;) unsigned ipfins$v_m27_36 : 1;- unsigned ipfins$v_m2 %7_opcode : 4;, unsigned ipfins$v_m27_fill : 23; } ipfins$r_m27_0_63;& unsigned __int64 ipfins$q_m27; } ipfins$r_m27; } M27_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m27_qp ipfins$r_m27.ipfins$r_m27_0_63.ipfins$v_m27_qpF#define ipfins$v_m27_f1 ipfins$r_m27.ipfins$r_m27_0_63.ipfins$v_m27_f1L#define ipfins$v_m27_13_26 ipfins$r_m27.ipfins$r_m27_0_63.ipfins$v_m27_13_26F#define ipfins$v_m27_x4 ipfins$r_m27.ipfins$r_m27_0_63.ipfins$v_m27_x4F#def %ine ipfins$v_m27_x2 ipfins$r_m27.ipfins$r_m27_0_63.ipfins$v_m27_x2F#define ipfins$v_m27_x3 ipfins$r_m27.ipfins$r_m27_0_63.ipfins$v_m27_x3F#define ipfins$v_m27_36 ipfins$r_m27.ipfins$r_m27_0_63.ipfins$v_m27_36N#define ipfins$v_m27_opcode ipfins$r_m27.ipfins$r_m27_0_63.ipfins$v_m27_opcode.#define ipfins$q_m27 ipfins$r_m27.ipfins$q_m27"#endif /* #if !defined(__VAXC) */ N/* */I/* M28: Flush Cache % */N/* */#define IPFINS$M_M28_QP 0x3F!#define IPFINS$M_M28_6_19 0xFFFC0!#define IPFINS$M_M28_R3 0x7F00000##define IPFINS$M_M28_X6 0x1F8000000##define IPFINS$M_M28_X3 0xE00000000##define IPFINS$M_M28_X 0x1000000000)#define IPFINS$M_M28_OPCODE 0x1E000000000,#define IPFINS$M_M28_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V%4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m28_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m28_qp : 6;, unsigned ipfins$v_m28_6_19 : 14;) unsigned ipfins$v_m28_r3 : 7;) unsigned ipfins$v_m28_x6 : 6;) unsigned ipfins$v_m28_x3 : 3;( unsigned ipfins$v_m28_x : 1;- unsigned ipfins$v_m28_opcode % : 4;, unsigned ipfins$v_m28_fill : 23; } ipfins$r_m28_0_63;& unsigned __int64 ipfins$q_m28; } ipfins$r_m28; } M28_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m28_qp ipfins$r_m28.ipfins$r_m28_0_63.ipfins$v_m28_qpJ#define ipfins$v_m28_6_19 ipfins$r_m28.ipfins$r_m28_0_63.ipfins$v_m28_6_19F#define ipfins$v_m28_r3 ipfins$r_m28.ipfins$r_m28_0_63.ipfins$v_m28_r3F#define ipfins$v_m28_x6 ipfins$r_m28.ipfins$r_m28_0_63.ipfins$v_m28_x6F#define ipfins %$v_m28_x3 ipfins$r_m28.ipfins$r_m28_0_63.ipfins$v_m28_x3D#define ipfins$v_m28_x ipfins$r_m28.ipfins$r_m28_0_63.ipfins$v_m28_xN#define ipfins$v_m28_opcode ipfins$r_m28.ipfins$r_m28_0_63.ipfins$v_m28_opcode.#define ipfins$q_m28 ipfins$r_m28.ipfins$q_m28"#endif /* #if !defined(__VAXC) */ N/* */I/* M29: Move to AR - Register (M-Unit) */N/* % */#define IPFINS$M_M29_QP 0x3F #define IPFINS$M_M29_6_12 0x1FC0#define IPFINS$M_M29_R2 0xFE000"#define IPFINS$M_M29_AR3 0x7F00000##define IPFINS$M_M29_X6 0x1F8000000##define IPFINS$M_M29_X3 0xE00000000$#define IPFINS$M_M29_36 0x1000000000)#define IPFINS$M_M29_OPCODE 0x1E000000000,#define IPFINS$M_M29_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadw%ord#else#pragma __nomember_alignment#endiftypedef struct _m29_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m29_qp : 6;+ unsigned ipfins$v_m29_6_12 : 7;) unsigned ipfins$v_m29_r2 : 7;* unsigned ipfins$v_m29_ar3 : 7;) unsigned ipfins$v_m29_x6 : 6;) unsigned ipfins$v_m29_x3 : 3;) unsigned ipfins$v_m29_36 : 1;- unsigned ipfins$v_m29_opcode : 4; %, unsigned ipfins$v_m29_fill : 23; } ipfins$r_m29_0_63;& unsigned __int64 ipfins$q_m29; } ipfins$r_m29; } M29_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m29_qp ipfins$r_m29.ipfins$r_m29_0_63.ipfins$v_m29_qpJ#define ipfins$v_m29_6_12 ipfins$r_m29.ipfins$r_m29_0_63.ipfins$v_m29_6_12F#define ipfins$v_m29_r2 ipfins$r_m29.ipfins$r_m29_0_63.ipfins$v_m29_r2H#define ipfins$v_m29_ar3 ipfins$r_m29.ipfins$r_m29_0_63.ipfins$v_m29_ar3F#define ipfins$v_m %29_x6 ipfins$r_m29.ipfins$r_m29_0_63.ipfins$v_m29_x6F#define ipfins$v_m29_x3 ipfins$r_m29.ipfins$r_m29_0_63.ipfins$v_m29_x3F#define ipfins$v_m29_36 ipfins$r_m29.ipfins$r_m29_0_63.ipfins$v_m29_36N#define ipfins$v_m29_opcode ipfins$r_m29.ipfins$r_m29_0_63.ipfins$v_m29_opcode.#define ipfins$q_m29 ipfins$r_m29.ipfins$q_m29"#endif /* #if !defined(__VAXC) */ N/* */I/* M30: Move to AR - Immediate(8) (M-Unit) % */N/* */#define IPFINS$M_M30_QP 0x3F #define IPFINS$M_M30_6_12 0x1FC0"#define IPFINS$M_M30_IMM7B 0xFE000"#define IPFINS$M_M30_AR3 0x7F00000"#define IPFINS$M_M30_X4 0x78000000##define IPFINS$M_M30_X2 0x180000000##define IPFINS$M_M30_X3 0xE00000000##define IPFINS$M_M30_S 0x1000000000)#define IPFINS$M_M30_OPCODE 0x1E000000000,#define IPFINS$M_M30_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUP%PORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m30_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m30_qp : 6;+ unsigned ipfins$v_m30_6_12 : 7;, unsigned ipfins$v_m30_imm7b : 7;* unsigned ipfins$v_m30_ar3 : 7;) unsigned ipfins$v_m30_x4 : 4;) unsigned ipf%ins$v_m30_x2 : 2;) unsigned ipfins$v_m30_x3 : 3;& signed ipfins$v_m30_s : 1;- unsigned ipfins$v_m30_opcode : 4;, unsigned ipfins$v_m30_fill : 23; } ipfins$r_m30_0_63;& unsigned __int64 ipfins$q_m30; } ipfins$r_m30; } M30_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m30_qp ipfins$r_m30.ipfins$r_m30_0_63.ipfins$v_m30_qpJ#define ipfins$v_m30_6_12 ipfins$r_m30.ipfins$r_m30_0_63.ipfins$v_m30_6_12L#define ipfins%$v_m30_imm7b ipfins$r_m30.ipfins$r_m30_0_63.ipfins$v_m30_imm7bH#define ipfins$v_m30_ar3 ipfins$r_m30.ipfins$r_m30_0_63.ipfins$v_m30_ar3F#define ipfins$v_m30_x4 ipfins$r_m30.ipfins$r_m30_0_63.ipfins$v_m30_x4F#define ipfins$v_m30_x2 ipfins$r_m30.ipfins$r_m30_0_63.ipfins$v_m30_x2F#define ipfins$v_m30_x3 ipfins$r_m30.ipfins$r_m30_0_63.ipfins$v_m30_x3D#define ipfins$v_m30_s ipfins$r_m30.ipfins$r_m30_0_63.ipfins$v_m30_sN#define ipfins$v_m30_opcode ipfins$r_m30.ipfins$r_m30_0_63.ipfins$v_m30_opcode.#d %efine ipfins$q_m30 ipfins$r_m30.ipfins$q_m30"#endif /* #if !defined(__VAXC) */ N/* */I/* M31: Move from AR (M-Unit) */N/* */#define IPFINS$M_M31_QP 0x3F#define IPFINS$M_M31_R1 0x1FC0"#define IPFINS$M_M31_13_19 0xFE000"#define IPFINS$M_M31_AR3 0x7F00000##define IPFINS$M_M31_X6 0x1F8000000##define IPFI%NS$M_M31_X3 0xE00000000$#define IPFINS$M_M31_36 0x1000000000)#define IPFINS$M_M31_OPCODE 0x1E000000000,#define IPFINS$M_M31_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m31_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m31_qp : 6;) unsi%gned ipfins$v_m31_r1 : 7;, unsigned ipfins$v_m31_13_19 : 7;* unsigned ipfins$v_m31_ar3 : 7;) unsigned ipfins$v_m31_x6 : 6;) unsigned ipfins$v_m31_x3 : 3;) unsigned ipfins$v_m31_36 : 1;- unsigned ipfins$v_m31_opcode : 4;, unsigned ipfins$v_m31_fill : 23; } ipfins$r_m31_0_63;& unsigned __int64 ipfins$q_m31; } ipfins$r_m31; } M31_FORMAT; #if !defined(__VAXC)F#define ipfins$v%_m31_qp ipfins$r_m31.ipfins$r_m31_0_63.ipfins$v_m31_qpF#define ipfins$v_m31_r1 ipfins$r_m31.ipfins$r_m31_0_63.ipfins$v_m31_r1L#define ipfins$v_m31_13_19 ipfins$r_m31.ipfins$r_m31_0_63.ipfins$v_m31_13_19H#define ipfins$v_m31_ar3 ipfins$r_m31.ipfins$r_m31_0_63.ipfins$v_m31_ar3F#define ipfins$v_m31_x6 ipfins$r_m31.ipfins$r_m31_0_63.ipfins$v_m31_x6F#define ipfins$v_m31_x3 ipfins$r_m31.ipfins$r_m31_0_63.ipfins$v_m31_x3F#define ipfins$v_m31_36 ipfins$r_m31.ipfins$r_m31_0_63.ipfins$v_m31_36N#define ip %fins$v_m31_opcode ipfins$r_m31.ipfins$r_m31_0_63.ipfins$v_m31_opcode.#define ipfins$q_m31 ipfins$r_m31.ipfins$q_m31"#endif /* #if !defined(__VAXC) */ N/* */I/* M32: Move to CR */N/* */#define IPFINS$M_M32_QP 0x3F #define IPFINS$M_M32_6_12 0x1FC0#define IPFINS$M_M32_R2 0xFE000"#define IPFINS%$M_M32_CR3 0x7F00000##define IPFINS$M_M32_X6 0x1F8000000##define IPFINS$M_M32_X3 0xE00000000$#define IPFINS$M_M32_36 0x1000000000)#define IPFINS$M_M32_OPCODE 0x1E000000000,#define IPFINS$M_M32_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m32_format {#pragma __nomember_alignment __union { __ %struct {) unsigned ipfins$v_m32_qp : 6;+ unsigned ipfins$v_m32_6_12 : 7;) unsigned ipfins$v_m32_r2 : 7;* unsigned ipfins$v_m32_cr3 : 7;) unsigned ipfins$v_m32_x6 : 6;) unsigned ipfins$v_m32_x3 : 3;) unsigned ipfins$v_m32_36 : 1;- unsigned ipfins$v_m32_opcode : 4;, unsigned ipfins$v_m32_fill : 23; } ipfins$r_m32_0_63;& unsigned __int64 ipfins$q_m32; } ipfins %$r_m32; } M32_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m32_qp ipfins$r_m32.ipfins$r_m32_0_63.ipfins$v_m32_qpJ#define ipfins$v_m32_6_12 ipfins$r_m32.ipfins$r_m32_0_63.ipfins$v_m32_6_12F#define ipfins$v_m32_r2 ipfins$r_m32.ipfins$r_m32_0_63.ipfins$v_m32_r2H#define ipfins$v_m32_cr3 ipfins$r_m32.ipfins$r_m32_0_63.ipfins$v_m32_cr3F#define ipfins$v_m32_x6 ipfins$r_m32.ipfins$r_m32_0_63.ipfins$v_m32_x6F#define ipfins$v_m32_x3 ipfins$r_m32.ipfins$r_m32_0_63.ipfins$v_m32_x3F#define ipfi %ns$v_m32_36 ipfins$r_m32.ipfins$r_m32_0_63.ipfins$v_m32_36N#define ipfins$v_m32_opcode ipfins$r_m32.ipfins$r_m32_0_63.ipfins$v_m32_opcode.#define ipfins$q_m32 ipfins$r_m32.ipfins$q_m32"#endif /* #if !defined(__VAXC) */ N/* */I/* M33: Move from CR */N/* */#define IPFINS$M_M33_QP 0x3F#define IPFI%NS$M_M33_R1 0x1FC0"#define IPFINS$M_M33_13_19 0xFE000"#define IPFINS$M_M33_CR3 0x7F00000##define IPFINS$M_M33_X6 0x1F8000000##define IPFINS$M_M33_X3 0xE00000000$#define IPFINS$M_M33_36 0x1000000000)#define IPFINS$M_M33_OPCODE 0x1E000000000,#define IPFINS$M_M33_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _%m33_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m33_qp : 6;) unsigned ipfins$v_m33_r1 : 7;, unsigned ipfins$v_m33_13_19 : 7;* unsigned ipfins$v_m33_cr3 : 7;) unsigned ipfins$v_m33_x6 : 6;) unsigned ipfins$v_m33_x3 : 3;) unsigned ipfins$v_m33_36 : 1;- unsigned ipfins$v_m33_opcode : 4;, unsigned ipfins$v_m33_fill : 23; } ipfins %$r_m33_0_63;& unsigned __int64 ipfins$q_m33; } ipfins$r_m33; } M33_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m33_qp ipfins$r_m33.ipfins$r_m33_0_63.ipfins$v_m33_qpF#define ipfins$v_m33_r1 ipfins$r_m33.ipfins$r_m33_0_63.ipfins$v_m33_r1L#define ipfins$v_m33_13_19 ipfins$r_m33.ipfins$r_m33_0_63.ipfins$v_m33_13_19H#define ipfins$v_m33_cr3 ipfins$r_m33.ipfins$r_m33_0_63.ipfins$v_m33_cr3F#define ipfins$v_m33_x6 ipfins$r_m33.ipfins$r_m33_0_63.ipfins$v_m33_x6F#define ipfi %ns$v_m33_x3 ipfins$r_m33.ipfins$r_m33_0_63.ipfins$v_m33_x3F#define ipfins$v_m33_36 ipfins$r_m33.ipfins$r_m33_0_63.ipfins$v_m33_36N#define ipfins$v_m33_opcode ipfins$r_m33.ipfins$r_m33_0_63.ipfins$v_m33_opcode.#define ipfins$q_m33 ipfins$r_m33.ipfins$q_m33"#endif /* #if !defined(__VAXC) */ N/* */I/* M34: Allocate Register Stack Frame */N/* % */#define IPFINS$M_M34_QP 0x3F#define IPFINS$M_M34_R1 0x1FC0 #define IPFINS$M_M34_SOF 0xFE000"#define IPFINS$M_M34_SOL 0x7F00000##define IPFINS$M_M34_SOR 0x78000000&#define IPFINS$M_M34_31_32 0x180000000##define IPFINS$M_M34_X3 0xE00000000$#define IPFINS$M_M34_36 0x1000000000)#define IPFINS$M_M34_OPCODE 0x1E000000000,#define IPFINS$M_M34_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++% */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m34_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m34_qp : 6;) unsigned ipfins$v_m34_r1 : 7;* unsigned ipfins$v_m34_sof : 7;* unsigned ipfins$v_m34_sol : 7;* unsigned ipfins$v_m34_sor : 4;, unsigned ipfins$v_m34_31_32 : 2;) unsigned ipfins$v_m34_x3 : 3;) % unsigned ipfins$v_m34_36 : 1;- unsigned ipfins$v_m34_opcode : 4;, unsigned ipfins$v_m34_fill : 23; } ipfins$r_m34_0_63;& unsigned __int64 ipfins$q_m34; } ipfins$r_m34; } M34_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m34_qp ipfins$r_m34.ipfins$r_m34_0_63.ipfins$v_m34_qpF#define ipfins$v_m34_r1 ipfins$r_m34.ipfins$r_m34_0_63.ipfins$v_m34_r1H#define ipfins$v_m34_sof ipfins$r_m34.ipfins$r_m34_0_63.ipfins$v_m34_sofH#define %ipfins$v_m34_sol ipfins$r_m34.ipfins$r_m34_0_63.ipfins$v_m34_solH#define ipfins$v_m34_sor ipfins$r_m34.ipfins$r_m34_0_63.ipfins$v_m34_sorL#define ipfins$v_m34_31_32 ipfins$r_m34.ipfins$r_m34_0_63.ipfins$v_m34_31_32F#define ipfins$v_m34_x3 ipfins$r_m34.ipfins$r_m34_0_63.ipfins$v_m34_x3F#define ipfins$v_m34_36 ipfins$r_m34.ipfins$r_m34_0_63.ipfins$v_m34_36N#define ipfins$v_m34_opcode ipfins$r_m34.ipfins$r_m34_0_63.ipfins$v_m34_opcode.#define ipfins$q_m34 ipfins$r_m34.ipfins$q_m34"#endif /* #if ! %defined(__VAXC) */ N/* */I/* M35: Move to PSR */N/* */#define IPFINS$M_M35_QP 0x3F #define IPFINS$M_M35_6_12 0x1FC0#define IPFINS$M_M35_R2 0xFE000$#define IPFINS$M_M35_20_26 0x7F00000##define IPFINS$M_M35_X6 0x1F8000000##define IPFINS$M_M35_X3 0xE00000000$#define IPFINS$M_M35_36 0x10000000%00)#define IPFINS$M_M35_OPCODE 0x1E000000000,#define IPFINS$M_M35_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m35_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m35_qp : 6;+ unsigned ipfins$v_m35_6_12 : 7;) unsigned ipfins$v_%m35_r2 : 7;, unsigned ipfins$v_m35_20_26 : 7;) unsigned ipfins$v_m35_x6 : 6;) unsigned ipfins$v_m35_x3 : 3;) unsigned ipfins$v_m35_36 : 1;- unsigned ipfins$v_m35_opcode : 4;, unsigned ipfins$v_m35_fill : 23; } ipfins$r_m35_0_63;& unsigned __int64 ipfins$q_m35; } ipfins$r_m35; } M35_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m35_qp ipfins$r_m35.ipfins$r_m35_0_63.ipfins$v_m35_qpJ#d%efine ipfins$v_m35_6_12 ipfins$r_m35.ipfins$r_m35_0_63.ipfins$v_m35_6_12F#define ipfins$v_m35_r2 ipfins$r_m35.ipfins$r_m35_0_63.ipfins$v_m35_r2L#define ipfins$v_m35_20_26 ipfins$r_m35.ipfins$r_m35_0_63.ipfins$v_m35_20_26F#define ipfins$v_m35_x6 ipfins$r_m35.ipfins$r_m35_0_63.ipfins$v_m35_x6F#define ipfins$v_m35_x3 ipfins$r_m35.ipfins$r_m35_0_63.ipfins$v_m35_x3F#define ipfins$v_m35_36 ipfins$r_m35.ipfins$r_m35_0_63.ipfins$v_m35_36N#define ipfins$v_m35_opcode ipfins$r_m35.ipfins$r_m35_0_63.ipfins$ %v_m35_opcode.#define ipfins$q_m35 ipfins$r_m35.ipfins$q_m35"#endif /* #if !defined(__VAXC) */ N/* */I/* M36: Move from PSR */N/* */#define IPFINS$M_M36_QP 0x3F#define IPFINS$M_M36_R1 0x1FC0$#define IPFINS$M_M36_13_26 0x7FFE000##define IPFINS$M_M36_X6 0x1F8000000##define IPFINS$M_M36_X3 0xE000%00000$#define IPFINS$M_M36_36 0x1000000000)#define IPFINS$M_M36_OPCODE 0x1E000000000,#define IPFINS$M_M36_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m36_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m36_qp : 6;) unsigned ipfins$v_m36_%r1 : 7;- unsigned ipfins$v_m36_13_26 : 14;) unsigned ipfins$v_m36_x6 : 6;) unsigned ipfins$v_m36_x3 : 3;) unsigned ipfins$v_m36_36 : 1;- unsigned ipfins$v_m36_opcode : 4;, unsigned ipfins$v_m36_fill : 23; } ipfins$r_m36_0_63;& unsigned __int64 ipfins$q_m36; } ipfins$r_m36; } M36_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m36_qp ipfins$r_m36.ipfins$r_m36_0_63.ipfins$v_m36_qpF#def%ine ipfins$v_m36_r1 ipfins$r_m36.ipfins$r_m36_0_63.ipfins$v_m36_r1L#define ipfins$v_m36_13_26 ipfins$r_m36.ipfins$r_m36_0_63.ipfins$v_m36_13_26F#define ipfins$v_m36_x6 ipfins$r_m36.ipfins$r_m36_0_63.ipfins$v_m36_x6F#define ipfins$v_m36_x3 ipfins$r_m36.ipfins$r_m36_0_63.ipfins$v_m36_x3F#define ipfins$v_m36_36 ipfins$r_m36.ipfins$r_m36_0_63.ipfins$v_m36_36N#define ipfins$v_m36_opcode ipfins$r_m36.ipfins$r_m36_0_63.ipfins$v_m36_opcode.#define ipfins$q_m36 ipfins$r_m36.ipfins$q_m36"#endif /* #if ! %defined(__VAXC) */ N/* */I/* M37: Break (M-Unit) */N/* */#define IPFINS$M_M37_QP 0x3F%#define IPFINS$M_M37_IMM20A 0x3FFFFC0!#define IPFINS$M_M37_26 0x4000000"#define IPFINS$M_M37_X4 0x78000000##define IPFINS$M_M37_X2 0x180000000##define IPFINS$M_M37_X3 0xE00000000##define IPFINS$M_M37_I 0x100%0000000)#define IPFINS$M_M37_OPCODE 0x1E000000000,#define IPFINS$M_M37_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m37_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m37_qp : 6;. unsigned ipfins$v_m37_imm20a : 20;) unsigned i%pfins$v_m37_26 : 1;) unsigned ipfins$v_m37_x4 : 4;) unsigned ipfins$v_m37_x2 : 2;) unsigned ipfins$v_m37_x3 : 3;( unsigned ipfins$v_m37_i : 1;- unsigned ipfins$v_m37_opcode : 4;, unsigned ipfins$v_m37_fill : 23; } ipfins$r_m37_0_63;& unsigned __int64 ipfins$q_m37; } ipfins$r_m37; } M37_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m37_qp ipfins$r_m37.ipfins$r_m37_0_63.ipfins$v_m37_qp%N#define ipfins$v_m37_imm20a ipfins$r_m37.ipfins$r_m37_0_63.ipfins$v_m37_imm20aF#define ipfins$v_m37_26 ipfins$r_m37.ipfins$r_m37_0_63.ipfins$v_m37_26F#define ipfins$v_m37_x4 ipfins$r_m37.ipfins$r_m37_0_63.ipfins$v_m37_x4F#define ipfins$v_m37_x2 ipfins$r_m37.ipfins$r_m37_0_63.ipfins$v_m37_x2F#define ipfins$v_m37_x3 ipfins$r_m37.ipfins$r_m37_0_63.ipfins$v_m37_x3D#define ipfins$v_m37_i ipfins$r_m37.ipfins$r_m37_0_63.ipfins$v_m37_iN#define ipfins$v_m37_opcode ipfins$r_m37.ipfins$r_m37_0_63.ipfins$ %v_m37_opcode.#define ipfins$q_m37 ipfins$r_m37.ipfins$q_m37"#endif /* #if !defined(__VAXC) */ N/* */I/* M38: Probe - Register */N/* */#define IPFINS$M_M38_QP 0x3F#define IPFINS$M_M38_R1 0x1FC0#define IPFINS$M_M38_R2 0xFE000!#define IPFINS$M_M38_R3 0x7F00000##define IPFINS$M_M38_X6 0x1F8000000%##define IPFINS$M_M38_X3 0xE00000000$#define IPFINS$M_M38_36 0x1000000000)#define IPFINS$M_M38_OPCODE 0x1E000000000,#define IPFINS$M_M38_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m38_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m38_qp : 6;) % unsigned ipfins$v_m38_r1 : 7;) unsigned ipfins$v_m38_r2 : 7;) unsigned ipfins$v_m38_r3 : 7;) unsigned ipfins$v_m38_x6 : 6;) unsigned ipfins$v_m38_x3 : 3;) unsigned ipfins$v_m38_36 : 1;- unsigned ipfins$v_m38_opcode : 4;, unsigned ipfins$v_m38_fill : 23; } ipfins$r_m38_0_63;& unsigned __int64 ipfins$q_m38; } ipfins$r_m38; } M38_FORMAT; #if !defined(__VAXC)F#def%ine ipfins$v_m38_qp ipfins$r_m38.ipfins$r_m38_0_63.ipfins$v_m38_qpF#define ipfins$v_m38_r1 ipfins$r_m38.ipfins$r_m38_0_63.ipfins$v_m38_r1F#define ipfins$v_m38_r2 ipfins$r_m38.ipfins$r_m38_0_63.ipfins$v_m38_r2F#define ipfins$v_m38_r3 ipfins$r_m38.ipfins$r_m38_0_63.ipfins$v_m38_r3F#define ipfins$v_m38_x6 ipfins$r_m38.ipfins$r_m38_0_63.ipfins$v_m38_x6F#define ipfins$v_m38_x3 ipfins$r_m38.ipfins$r_m38_0_63.ipfins$v_m38_x3F#define ipfins$v_m38_36 ipfins$r_m38.ipfins$r_m38_0_63.ipfins$v_m38_36N#defin %e ipfins$v_m38_opcode ipfins$r_m38.ipfins$r_m38_0_63.ipfins$v_m38_opcode.#define ipfins$q_m38 ipfins$r_m38.ipfins$q_m38"#endif /* #if !defined(__VAXC) */ N/* */I/* M39: Probe - Immediate(2) */N/* */#define IPFINS$M_M39_QP 0x3F#define IPFINS$M_M39_R1 0x1FC0#define IPFINS$M_M39_I2B 0x6000"#define IPFI%NS$M_M39_15_19 0xF8000!#define IPFINS$M_M39_R3 0x7F00000##define IPFINS$M_M39_X6 0x1F8000000##define IPFINS$M_M39_X3 0xE00000000$#define IPFINS$M_M39_36 0x1000000000)#define IPFINS$M_M39_OPCODE 0x1E000000000,#define IPFINS$M_M39_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m39_format {#pragma __nomember%_alignment __union { __struct {) unsigned ipfins$v_m39_qp : 6;) unsigned ipfins$v_m39_r1 : 7;* unsigned ipfins$v_m39_i2b : 2;, unsigned ipfins$v_m39_15_19 : 5;) unsigned ipfins$v_m39_r3 : 7;) unsigned ipfins$v_m39_x6 : 6;) unsigned ipfins$v_m39_x3 : 3;) unsigned ipfins$v_m39_36 : 1;- unsigned ipfins$v_m39_opcode : 4;, unsigned ipfins$v_m39_fill : 23; % } ipfins$r_m39_0_63;& unsigned __int64 ipfins$q_m39; } ipfins$r_m39; } M39_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m39_qp ipfins$r_m39.ipfins$r_m39_0_63.ipfins$v_m39_qpF#define ipfins$v_m39_r1 ipfins$r_m39.ipfins$r_m39_0_63.ipfins$v_m39_r1H#define ipfins$v_m39_i2b ipfins$r_m39.ipfins$r_m39_0_63.ipfins$v_m39_i2bL#define ipfins$v_m39_15_19 ipfins$r_m39.ipfins$r_m39_0_63.ipfins$v_m39_15_19F#define ipfins$v_m39_r3 ipfins$r_m39.ipfins$r_m39_0_63.ipfins$v_m39_r3F %#define ipfins$v_m39_x6 ipfins$r_m39.ipfins$r_m39_0_63.ipfins$v_m39_x6F#define ipfins$v_m39_x3 ipfins$r_m39.ipfins$r_m39_0_63.ipfins$v_m39_x3F#define ipfins$v_m39_36 ipfins$r_m39.ipfins$r_m39_0_63.ipfins$v_m39_36N#define ipfins$v_m39_opcode ipfins$r_m39.ipfins$r_m39_0_63.ipfins$v_m39_opcode.#define ipfins$q_m39 ipfins$r_m39.ipfins$q_m39"#endif /* #if !defined(__VAXC) */ N/* */I/* M40: Probe Fault - Immediate(2) % */N/* */#define IPFINS$M_M40_QP 0x3F #define IPFINS$M_M40_6_12 0x1FC0#define IPFINS$M_M40_I2B 0x6000"#define IPFINS$M_M40_15_19 0xF8000!#define IPFINS$M_M40_R3 0x7F00000##define IPFINS$M_M40_X6 0x1F8000000##define IPFINS$M_M40_X3 0xE00000000$#define IPFINS$M_M40_36 0x1000000000)#define IPFINS$M_M40_OPCODE 0x1E000000000,#define IPFINS$M_M40_FILL 0xFFFFFE0000000000 c#if !defined(_%_NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m40_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m40_qp : 6;+ unsigned ipfins$v_m40_6_12 : 7;* unsigned ipfins$v_m40_i2b : 2;, unsigned ipfins$v_m40_15_19 : 5;) unsigned ipfins$v_m40_r3 : 7;) % unsigned ipfins$v_m40_x6 : 6;) unsigned ipfins$v_m40_x3 : 3;) unsigned ipfins$v_m40_36 : 1;- unsigned ipfins$v_m40_opcode : 4;, unsigned ipfins$v_m40_fill : 23; } ipfins$r_m40_0_63;& unsigned __int64 ipfins$q_m40; } ipfins$r_m40; } M40_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m40_qp ipfins$r_m40.ipfins$r_m40_0_63.ipfins$v_m40_qpJ#define ipfins$v_m40_6_12 ipfins$r_m40.ipfins$r_m40_0_63.ipfins$v_m40_%6_12H#define ipfins$v_m40_i2b ipfins$r_m40.ipfins$r_m40_0_63.ipfins$v_m40_i2bL#define ipfins$v_m40_15_19 ipfins$r_m40.ipfins$r_m40_0_63.ipfins$v_m40_15_19F#define ipfins$v_m40_r3 ipfins$r_m40.ipfins$r_m40_0_63.ipfins$v_m40_r3F#define ipfins$v_m40_x6 ipfins$r_m40.ipfins$r_m40_0_63.ipfins$v_m40_x6F#define ipfins$v_m40_x3 ipfins$r_m40.ipfins$r_m40_0_63.ipfins$v_m40_x3F#define ipfins$v_m40_36 ipfins$r_m40.ipfins$r_m40_0_63.ipfins$v_m40_36N#define ipfins$v_m40_opcode ipfins$r_m40.ipfins$r_m40_0_63.i %pfins$v_m40_opcode.#define ipfins$q_m40 ipfins$r_m40.ipfins$q_m40"#endif /* #if !defined(__VAXC) */ N/* */I/* M41: Translation Cache Insert */N/* */#define IPFINS$M_M41_QP 0x3F #define IPFINS$M_M41_6_12 0x1FC0#define IPFINS$M_M41_R2 0xFE000$#define IPFINS$M_M41_20_26 0x7F00000##define IPFINS$M_M41_X6 0x%1F8000000##define IPFINS$M_M41_X3 0xE00000000$#define IPFINS$M_M41_36 0x1000000000)#define IPFINS$M_M41_OPCODE 0x1E000000000,#define IPFINS$M_M41_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m41_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m41_qp& : 6;+ unsigned ipfins$v_m41_6_12 : 7;) unsigned ipfins$v_m41_r2 : 7;, unsigned ipfins$v_m41_20_26 : 7;) unsigned ipfins$v_m41_x6 : 6;) unsigned ipfins$v_m41_x3 : 3;) unsigned ipfins$v_m41_36 : 1;- unsigned ipfins$v_m41_opcode : 4;, unsigned ipfins$v_m41_fill : 23; } ipfins$r_m41_0_63;& unsigned __int64 ipfins$q_m41; } ipfins$r_m41; } M41_FORMAT; #if !defined&(__VAXC)F#define ipfins$v_m41_qp ipfins$r_m41.ipfins$r_m41_0_63.ipfins$v_m41_qpJ#define ipfins$v_m41_6_12 ipfins$r_m41.ipfins$r_m41_0_63.ipfins$v_m41_6_12F#define ipfins$v_m41_r2 ipfins$r_m41.ipfins$r_m41_0_63.ipfins$v_m41_r2L#define ipfins$v_m41_20_26 ipfins$r_m41.ipfins$r_m41_0_63.ipfins$v_m41_20_26F#define ipfins$v_m41_x6 ipfins$r_m41.ipfins$r_m41_0_63.ipfins$v_m41_x6F#define ipfins$v_m41_x3 ipfins$r_m41.ipfins$r_m41_0_63.ipfins$v_m41_x3F#define ipfins$v_m41_36 ipfins$r_m41.ipfins$r_m41_0_63 &.ipfins$v_m41_36N#define ipfins$v_m41_opcode ipfins$r_m41.ipfins$r_m41_0_63.ipfins$v_m41_opcode.#define ipfins$q_m41 ipfins$r_m41.ipfins$q_m41"#endif /* #if !defined(__VAXC) */ N/* */I/* M42: Move to Indirect Register/Translation Register Insert */N/* */#define IPFINS$M_M42_QP 0x3F #define IPFINS$M_M42_6_12 0x1FC0#define IPFINS$M_M42&_R2 0xFE000!#define IPFINS$M_M42_R3 0x7F00000##define IPFINS$M_M42_X6 0x1F8000000##define IPFINS$M_M42_X3 0xE00000000$#define IPFINS$M_M42_36 0x1000000000)#define IPFINS$M_M42_OPCODE 0x1E000000000,#define IPFINS$M_M42_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m42_format {#pragma __nomember_alignment & __union { __struct {) unsigned ipfins$v_m42_qp : 6;+ unsigned ipfins$v_m42_6_12 : 7;) unsigned ipfins$v_m42_r2 : 7;) unsigned ipfins$v_m42_r3 : 7;) unsigned ipfins$v_m42_x6 : 6;) unsigned ipfins$v_m42_x3 : 3;) unsigned ipfins$v_m42_36 : 1;- unsigned ipfins$v_m42_opcode : 4;, unsigned ipfins$v_m42_fill : 23; } ipfins$r_m42_0_63;& unsigned __int64 ipf &ins$q_m42; } ipfins$r_m42; } M42_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m42_qp ipfins$r_m42.ipfins$r_m42_0_63.ipfins$v_m42_qpJ#define ipfins$v_m42_6_12 ipfins$r_m42.ipfins$r_m42_0_63.ipfins$v_m42_6_12F#define ipfins$v_m42_r2 ipfins$r_m42.ipfins$r_m42_0_63.ipfins$v_m42_r2F#define ipfins$v_m42_r3 ipfins$r_m42.ipfins$r_m42_0_63.ipfins$v_m42_r3F#define ipfins$v_m42_x6 ipfins$r_m42.ipfins$r_m42_0_63.ipfins$v_m42_x6F#define ipfins$v_m42_x3 ipfins$r_m42.ipfins$r_m42_0_63.ipf &ins$v_m42_x3F#define ipfins$v_m42_36 ipfins$r_m42.ipfins$r_m42_0_63.ipfins$v_m42_36N#define ipfins$v_m42_opcode ipfins$r_m42.ipfins$r_m42_0_63.ipfins$v_m42_opcode.#define ipfins$q_m42 ipfins$r_m42.ipfins$q_m42"#endif /* #if !defined(__VAXC) */ N/* */I/* M43: Move from Indirect Register */N/* */#define IPFINS$M&_M43_QP 0x3F#define IPFINS$M_M43_R1 0x1FC0"#define IPFINS$M_M43_13_19 0xFE000!#define IPFINS$M_M43_R3 0x7F00000##define IPFINS$M_M43_X6 0x1F8000000##define IPFINS$M_M43_X3 0xE00000000$#define IPFINS$M_M43_36 0x1000000000)#define IPFINS$M_M43_OPCODE 0x1E000000000,#define IPFINS$M_M43_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment&#endiftypedef struct _m43_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m43_qp : 6;) unsigned ipfins$v_m43_r1 : 7;, unsigned ipfins$v_m43_13_19 : 7;) unsigned ipfins$v_m43_r3 : 7;) unsigned ipfins$v_m43_x6 : 6;) unsigned ipfins$v_m43_x3 : 3;) unsigned ipfins$v_m43_36 : 1;- unsigned ipfins$v_m43_opcode : 4;, unsigned ipfins$v_m43_fill : & 23; } ipfins$r_m43_0_63;& unsigned __int64 ipfins$q_m43; } ipfins$r_m43; } M43_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m43_qp ipfins$r_m43.ipfins$r_m43_0_63.ipfins$v_m43_qpF#define ipfins$v_m43_r1 ipfins$r_m43.ipfins$r_m43_0_63.ipfins$v_m43_r1L#define ipfins$v_m43_13_19 ipfins$r_m43.ipfins$r_m43_0_63.ipfins$v_m43_13_19F#define ipfins$v_m43_r3 ipfins$r_m43.ipfins$r_m43_0_63.ipfins$v_m43_r3F#define ipfins$v_m43_x6 ipfins$r_m43.ipfins$r_m43_0_63.ipfin &s$v_m43_x6F#define ipfins$v_m43_x3 ipfins$r_m43.ipfins$r_m43_0_63.ipfins$v_m43_x3F#define ipfins$v_m43_36 ipfins$r_m43.ipfins$r_m43_0_63.ipfins$v_m43_36N#define ipfins$v_m43_opcode ipfins$r_m43.ipfins$r_m43_0_63.ipfins$v_m43_opcode.#define ipfins$q_m43 ipfins$r_m43.ipfins$q_m43"#endif /* #if !defined(__VAXC) */ N/* */I/* M44: Set/Reset User/System Mask */N/* & */#define IPFINS$M_M44_QP 0x3F%#define IPFINS$M_M44_IMM21A 0x7FFFFC0"#define IPFINS$M_M44_X4 0x78000000$#define IPFINS$M_M44_I2D 0x180000000##define IPFINS$M_M44_X3 0xE00000000##define IPFINS$M_M44_I 0x1000000000)#define IPFINS$M_M44_OPCODE 0x1E000000000,#define IPFINS$M_M44_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadw &ord#else#pragma __nomember_alignment#endiftypedef struct _m44_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m44_qp : 6;. unsigned ipfins$v_m44_imm21a : 21;) unsigned ipfins$v_m44_x4 : 4;* unsigned ipfins$v_m44_i2d : 2;) unsigned ipfins$v_m44_x3 : 3;( unsigned ipfins$v_m44_i : 1;- unsigned ipfins$v_m44_opcode : 4;, unsigned ipfins$v_m44_fill : 2 &3; } ipfins$r_m44_0_63;& unsigned __int64 ipfins$q_m44; } ipfins$r_m44; } M44_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m44_qp ipfins$r_m44.ipfins$r_m44_0_63.ipfins$v_m44_qpN#define ipfins$v_m44_imm21a ipfins$r_m44.ipfins$r_m44_0_63.ipfins$v_m44_imm21aF#define ipfins$v_m44_x4 ipfins$r_m44.ipfins$r_m44_0_63.ipfins$v_m44_x4H#define ipfins$v_m44_i2d ipfins$r_m44.ipfins$r_m44_0_63.ipfins$v_m44_i2dF#define ipfins$v_m44_x3 ipfins$r_m44.ipfins$r_m44_0_63.ipf &ins$v_m44_x3D#define ipfins$v_m44_i ipfins$r_m44.ipfins$r_m44_0_63.ipfins$v_m44_iN#define ipfins$v_m44_opcode ipfins$r_m44.ipfins$r_m44_0_63.ipfins$v_m44_opcode.#define ipfins$q_m44 ipfins$r_m44.ipfins$q_m44"#endif /* #if !defined(__VAXC) */ N/* */I/* M45: Translation Purge */N/* */#define IPFINS$M_M&45_QP 0x3F #define IPFINS$M_M45_6_12 0x1FC0#define IPFINS$M_M45_R2 0xFE000!#define IPFINS$M_M45_R3 0x7F00000##define IPFINS$M_M45_X6 0x1F8000000##define IPFINS$M_M45_X3 0xE00000000$#define IPFINS$M_M45_36 0x1000000000)#define IPFINS$M_M45_OPCODE 0x1E000000000,#define IPFINS$M_M45_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment&#endiftypedef struct _m45_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m45_qp : 6;+ unsigned ipfins$v_m45_6_12 : 7;) unsigned ipfins$v_m45_r2 : 7;) unsigned ipfins$v_m45_r3 : 7;) unsigned ipfins$v_m45_x6 : 6;) unsigned ipfins$v_m45_x3 : 3;) unsigned ipfins$v_m45_36 : 1;- unsigned ipfins$v_m45_opcode : 4;, unsigned ipfins$v_m45_fill : 2 &3; } ipfins$r_m45_0_63;& unsigned __int64 ipfins$q_m45; } ipfins$r_m45; } M45_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m45_qp ipfins$r_m45.ipfins$r_m45_0_63.ipfins$v_m45_qpJ#define ipfins$v_m45_6_12 ipfins$r_m45.ipfins$r_m45_0_63.ipfins$v_m45_6_12F#define ipfins$v_m45_r2 ipfins$r_m45.ipfins$r_m45_0_63.ipfins$v_m45_r2F#define ipfins$v_m45_r3 ipfins$r_m45.ipfins$r_m45_0_63.ipfins$v_m45_r3F#define ipfins$v_m45_x6 ipfins$r_m45.ipfins$r_m45_0_63.ipfins$v_ &m45_x6F#define ipfins$v_m45_x3 ipfins$r_m45.ipfins$r_m45_0_63.ipfins$v_m45_x3F#define ipfins$v_m45_36 ipfins$r_m45.ipfins$r_m45_0_63.ipfins$v_m45_36N#define ipfins$v_m45_opcode ipfins$r_m45.ipfins$r_m45_0_63.ipfins$v_m45_opcode.#define ipfins$q_m45 ipfins$r_m45.ipfins$q_m45"#endif /* #if !defined(__VAXC) */ N/* */I/* M46: Translation Access */N/* & */#define IPFINS$M_M46_QP 0x3F#define IPFINS$M_M46_R1 0x1FC0"#define IPFINS$M_M46_13_19 0xFE000!#define IPFINS$M_M46_R3 0x7F00000##define IPFINS$M_M46_X6 0x1F8000000##define IPFINS$M_M46_X3 0xE00000000$#define IPFINS$M_M46_36 0x1000000000)#define IPFINS$M_M46_OPCODE 0x1E000000000,#define IPFINS$M_M46_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __no&member_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m46_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m46_qp : 6;) unsigned ipfins$v_m46_r1 : 7;, unsigned ipfins$v_m46_13_19 : 7;) unsigned ipfins$v_m46_r3 : 7;) unsigned ipfins$v_m46_x6 : 6;) unsigned ipfins$v_m46_x3 : 3;) unsigned ipfins$v_m46_36 : 1;- unsigned i &pfins$v_m46_opcode : 4;, unsigned ipfins$v_m46_fill : 23; } ipfins$r_m46_0_63;& unsigned __int64 ipfins$q_m46; } ipfins$r_m46; } M46_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m46_qp ipfins$r_m46.ipfins$r_m46_0_63.ipfins$v_m46_qpF#define ipfins$v_m46_r1 ipfins$r_m46.ipfins$r_m46_0_63.ipfins$v_m46_r1L#define ipfins$v_m46_13_19 ipfins$r_m46.ipfins$r_m46_0_63.ipfins$v_m46_13_19F#define ipfins$v_m46_r3 ipfins$r_m46.ipfins$r_m46_0_63.ipfins$v_m4 &6_r3F#define ipfins$v_m46_x6 ipfins$r_m46.ipfins$r_m46_0_63.ipfins$v_m46_x6F#define ipfins$v_m46_x3 ipfins$r_m46.ipfins$r_m46_0_63.ipfins$v_m46_x3F#define ipfins$v_m46_36 ipfins$r_m46.ipfins$r_m46_0_63.ipfins$v_m46_36N#define ipfins$v_m46_opcode ipfins$r_m46.ipfins$r_m46_0_63.ipfins$v_m46_opcode.#define ipfins$q_m46 ipfins$r_m46.ipfins$q_m46"#endif /* #if !defined(__VAXC) */ N/* */I/* M47: Purge Translation Cache Entr &y */N/* */#define IPFINS$M_M47_QP 0x3F!#define IPFINS$M_M47_6_19 0xFFFC0!#define IPFINS$M_M47_R3 0x7F00000##define IPFINS$M_M47_X6 0x1F8000000##define IPFINS$M_M47_X3 0xE00000000$#define IPFINS$M_M47_36 0x1000000000)#define IPFINS$M_M47_OPCODE 0x1E000000000,#define IPFINS$M_M47_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using &pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m47_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m47_qp : 6;, unsigned ipfins$v_m47_6_19 : 14;) unsigned ipfins$v_m47_r3 : 7;) unsigned ipfins$v_m47_x6 : 6;) unsigned ipfins$v_m47_x3 : 3;) unsigned ipfins$v_m47_36 : 1;- unsigned ipfins$ &v_m47_opcode : 4;, unsigned ipfins$v_m47_fill : 23; } ipfins$r_m47_0_63;& unsigned __int64 ipfins$q_m47; } ipfins$r_m47; } M47_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m47_qp ipfins$r_m47.ipfins$r_m47_0_63.ipfins$v_m47_qpJ#define ipfins$v_m47_6_19 ipfins$r_m47.ipfins$r_m47_0_63.ipfins$v_m47_6_19F#define ipfins$v_m47_r3 ipfins$r_m47.ipfins$r_m47_0_63.ipfins$v_m47_r3F#define ipfins$v_m47_x6 ipfins$r_m47.ipfins$r_m47_0_63.ipfins$v_m47_x6F#d &efine ipfins$v_m47_x3 ipfins$r_m47.ipfins$r_m47_0_63.ipfins$v_m47_x3F#define ipfins$v_m47_36 ipfins$r_m47.ipfins$r_m47_0_63.ipfins$v_m47_36N#define ipfins$v_m47_opcode ipfins$r_m47.ipfins$r_m47_0_63.ipfins$v_m47_opcode.#define ipfins$q_m47 ipfins$r_m47.ipfins$q_m47"#endif /* #if !defined(__VAXC) */ N/* */I/* M48: Nop (M-Unit) */N/* & */#define IPFINS$M_M48_QP 0x3F%#define IPFINS$M_M48_IMM20A 0x3FFFFC0 #define IPFINS$M_M48_Y 0x4000000"#define IPFINS$M_M48_X4 0x78000000##define IPFINS$M_M48_X2 0x180000000##define IPFINS$M_M48_X3 0xE00000000##define IPFINS$M_M48_I 0x1000000000)#define IPFINS$M_M48_OPCODE 0x1E000000000,#define IPFINS$M_M48_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomemb&er_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m48_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m48_qp : 6;. unsigned ipfins$v_m48_imm20a : 20;( unsigned ipfins$v_m48_y : 1;) unsigned ipfins$v_m48_x4 : 4;) unsigned ipfins$v_m48_x2 : 2;) unsigned ipfins$v_m48_x3 : 3;( unsigned ipfins$v_m48_i : 1;- unsigned ipfins$ &v_m48_opcode : 4;, unsigned ipfins$v_m48_fill : 23; } ipfins$r_m48_0_63;& unsigned __int64 ipfins$q_m48; } ipfins$r_m48; } M48_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m48_qp ipfins$r_m48.ipfins$r_m48_0_63.ipfins$v_m48_qpN#define ipfins$v_m48_imm20a ipfins$r_m48.ipfins$r_m48_0_63.ipfins$v_m48_imm20aD#define ipfins$v_m48_y ipfins$r_m48.ipfins$r_m48_0_63.ipfins$v_m48_yF#define ipfins$v_m48_x4 ipfins$r_m48.ipfins$r_m48_0_63.ipfins$v_m48_x4F &#define ipfins$v_m48_x2 ipfins$r_m48.ipfins$r_m48_0_63.ipfins$v_m48_x2F#define ipfins$v_m48_x3 ipfins$r_m48.ipfins$r_m48_0_63.ipfins$v_m48_x3D#define ipfins$v_m48_i ipfins$r_m48.ipfins$r_m48_0_63.ipfins$v_m48_iN#define ipfins$v_m48_opcode ipfins$r_m48.ipfins$r_m48_0_63.ipfins$v_m48_opcode.#define ipfins$q_m48 ipfins$r_m48.ipfins$q_m48"#endif /* #if !defined(__VAXC) */ N/* */I/* M49: Hint (M-Unit) & */N/* */#define IPFINS$M_M49_QP 0x3F #define IPFINS$M_M49_IMM4A 0x3C0#define IPFINS$M_M49_Z 0xC00%#define IPFINS$M_M49_IMM14B 0x3FFF000 #define IPFINS$M_M49_Y 0x4000000"#define IPFINS$M_M49_X4 0x78000000##define IPFINS$M_M49_X2 0x180000000##define IPFINS$M_M49_X3 0xE00000000##define IPFINS$M_M49_I 0x1000000000)#define IPFINS$M_M49_OPCODE 0x1E000000000,#define IPFINS$M_M49_FILL 0xFFFF &FE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m49_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m49_qp : 6;, unsigned ipfins$v_m49_imm4a : 4;( unsigned ipfins$v_m49_z : 2;. unsigned ipfins$v_m49_imm14b : 14;( unsigned!& ipfins$v_m49_y : 1;) unsigned ipfins$v_m49_x4 : 4;) unsigned ipfins$v_m49_x2 : 2;) unsigned ipfins$v_m49_x3 : 3;( unsigned ipfins$v_m49_i : 1;- unsigned ipfins$v_m49_opcode : 4;, unsigned ipfins$v_m49_fill : 23; } ipfins$r_m49_0_63;& unsigned __int64 ipfins$q_m49; } ipfins$r_m49; } M49_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m49_qp ipfins$r_m49.ipfins$r_m49_0_63.ipfins$v_m49_qp"&L#define ipfins$v_m49_imm4a ipfins$r_m49.ipfins$r_m49_0_63.ipfins$v_m49_imm4aD#define ipfins$v_m49_z ipfins$r_m49.ipfins$r_m49_0_63.ipfins$v_m49_zN#define ipfins$v_m49_imm14b ipfins$r_m49.ipfins$r_m49_0_63.ipfins$v_m49_imm14bD#define ipfins$v_m49_y ipfins$r_m49.ipfins$r_m49_0_63.ipfins$v_m49_yF#define ipfins$v_m49_x4 ipfins$r_m49.ipfins$r_m49_0_63.ipfins$v_m49_x4F#define ipfins$v_m49_x2 ipfins$r_m49.ipfins$r_m49_0_63.ipfins$v_m49_x2F#define ipfins$v_m49_x3 ipfins$r_m49.ipfins$r_m49_0_63.ipfins$ #&v_m49_x3D#define ipfins$v_m49_i ipfins$r_m49.ipfins$r_m49_0_63.ipfins$v_m49_iN#define ipfins$v_m49_opcode ipfins$r_m49.ipfins$r_m49_0_63.ipfins$v_m49_opcode.#define ipfins$q_m49 ipfins$r_m49.ipfins$q_m49"#endif /* #if !defined(__VAXC) */ N/* */I/* M50: Move to DAHR */N/* */#define IPFINS$M_M50_Q$&P 0x3F #define IPFINS$M_M50_IMM4A 0x3C0#define IPFINS$M_M50_Z 0xC00$#define IPFINS$M_M50_IMM11B 0x7FF000$#define IPFINS$M_M50_DAHR3 0x3800000 #define IPFINS$M_M50_Y 0x4000000"#define IPFINS$M_M50_X4 0x78000000##define IPFINS$M_M50_X2 0x180000000##define IPFINS$M_M50_X3 0xE00000000##define IPFINS$M_M50_I 0x1000000000)#define IPFINS$M_M50_OPCODE 0x1E000000000,#define IPFINS$M_M50_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre %&DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m50_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m50_qp : 6;, unsigned ipfins$v_m50_imm4a : 4;( unsigned ipfins$v_m50_z : 2;. unsigned ipfins$v_m50_imm11b : 11;, unsigned ipfins$v_m50_dahr3 : 3;( unsigned ipfins$v_m50_y : 1;) unsigned ipfins$v_&&m50_x4 : 4;) unsigned ipfins$v_m50_x2 : 2;) unsigned ipfins$v_m50_x3 : 3;( unsigned ipfins$v_m50_i : 1;- unsigned ipfins$v_m50_opcode : 4;, unsigned ipfins$v_m50_fill : 23; } ipfins$r_m50_0_63;& unsigned __int64 ipfins$q_m50; } ipfins$r_m50; } M50_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m50_qp ipfins$r_m50.ipfins$r_m50_0_63.ipfins$v_m50_qpL#define ipfins$v_m50_imm4a ipfins$r_m50.ipfins$r_m'&50_0_63.ipfins$v_m50_imm4aD#define ipfins$v_m50_z ipfins$r_m50.ipfins$r_m50_0_63.ipfins$v_m50_zN#define ipfins$v_m50_imm11b ipfins$r_m50.ipfins$r_m50_0_63.ipfins$v_m50_imm11bL#define ipfins$v_m50_dahr3 ipfins$r_m50.ipfins$r_m50_0_63.ipfins$v_m50_dahr3D#define ipfins$v_m50_y ipfins$r_m50.ipfins$r_m50_0_63.ipfins$v_m50_yF#define ipfins$v_m50_x4 ipfins$r_m50.ipfins$r_m50_0_63.ipfins$v_m50_x4F#define ipfins$v_m50_x2 ipfins$r_m50.ipfins$r_m50_0_63.ipfins$v_m50_x2F#define ipfins$v_m50_x3 ipfins$r_m50 (&.ipfins$r_m50_0_63.ipfins$v_m50_x3D#define ipfins$v_m50_i ipfins$r_m50.ipfins$r_m50_0_63.ipfins$v_m50_iN#define ipfins$v_m50_opcode ipfins$r_m50.ipfins$r_m50_0_63.ipfins$v_m50_opcode.#define ipfins$q_m50 ipfins$r_m50.ipfins$q_m50"#endif /* #if !defined(__VAXC) */ N/* */I/* M51: Line Prefetch */N/* )&*/#define IPFINS$M_M51_QP 0x3F#define IPFINS$M_M51_6_11 0xFC0#define IPFINS$M_M51_H 0x1000"#define IPFINS$M_M51_13_18 0x7E000#define IPFINS$M_M51_Y 0x80000!#define IPFINS$M_M51_R3 0x7F00000 #define IPFINS$M_M51_X 0x8000000$#define IPFINS$M_M51_HINT 0x30000000##define IPFINS$M_M51_X6 0xFC0000000##define IPFINS$M_M51_M 0x1000000000)#define IPFINS$M_M51_OPCODE 0x1E000000000,#define IPFINS$M_M51_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus*&) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m51_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m51_qp : 6;+ unsigned ipfins$v_m51_6_11 : 6;( unsigned ipfins$v_m51_h : 1;, unsigned ipfins$v_m51_13_18 : 6;( unsigned ipfins$v_m51_y : 1;) unsigned ipfins$v_m51_r3 : 7;( un+&signed ipfins$v_m51_x : 1;+ unsigned ipfins$v_m51_hint : 2;) unsigned ipfins$v_m51_x6 : 6;( unsigned ipfins$v_m51_m : 1;- unsigned ipfins$v_m51_opcode : 4;, unsigned ipfins$v_m51_fill : 23; } ipfins$r_m51_0_63;& unsigned __int64 ipfins$q_m51; } ipfins$r_m51; } M51_FORMAT; #if !defined(__VAXC)F#define ipfins$v_m51_qp ipfins$r_m51.ipfins$r_m51_0_63.ipfins$v_m51_qpJ#define ipfins$v_m51_6_11 ipfins$r,&_m51.ipfins$r_m51_0_63.ipfins$v_m51_6_11D#define ipfins$v_m51_h ipfins$r_m51.ipfins$r_m51_0_63.ipfins$v_m51_hL#define ipfins$v_m51_13_18 ipfins$r_m51.ipfins$r_m51_0_63.ipfins$v_m51_13_18D#define ipfins$v_m51_y ipfins$r_m51.ipfins$r_m51_0_63.ipfins$v_m51_yF#define ipfins$v_m51_r3 ipfins$r_m51.ipfins$r_m51_0_63.ipfins$v_m51_r3D#define ipfins$v_m51_x ipfins$r_m51.ipfins$r_m51_0_63.ipfins$v_m51_xJ#define ipfins$v_m51_hint ipfins$r_m51.ipfins$r_m51_0_63.ipfins$v_m51_hintF#define ipfins$v_m51_x6 ipfi -&ns$r_m51.ipfins$r_m51_0_63.ipfins$v_m51_x6D#define ipfins$v_m51_m ipfins$r_m51.ipfins$r_m51_0_63.ipfins$v_m51_mN#define ipfins$v_m51_opcode ipfins$r_m51.ipfins$r_m51_0_63.ipfins$v_m51_opcode.#define ipfins$q_m51 ipfins$r_m51.ipfins$q_m51"#endif /* #if !defined(__VAXC) */ N/* */I/* M52: Counted Line Prefetch */N/* .& */#define IPFINS$M_M52_QP 0x3F #define IPFINS$M_M52_CNT6A 0xFC0#define IPFINS$M_M52_H 0x1000%#define IPFINS$M_M52_STRIDE5B 0x3E000#define IPFINS$M_M52_18 0x40000#define IPFINS$M_M52_Y 0x80000!#define IPFINS$M_M52_R3 0x7F00000 #define IPFINS$M_M52_X 0x8000000$#define IPFINS$M_M52_HINT 0x30000000##define IPFINS$M_M52_X6 0xFC0000000##define IPFINS$M_M52_M 0x1000000000)#define IPFINS$M_M52_OPCODE 0x1E000000000,#define IPFINS$M_M52_FILL 0xFFFFFE0000000000 c#if !defined(_/&_NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _m52_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_m52_qp : 6;, unsigned ipfins$v_m52_cnt6a : 6;( unsigned ipfins$v_m52_h : 1;- signed ipfins$v_m52_stride5b : 5;) unsigned ipfins$v_m52_18 : 1;( 0& unsigned ipfins$v_m52_y : 1;) unsigned ipfins$v_m52_r3 : 7;( unsigned ipfins$v_m52_x : 1;+ unsigned ipfins$v_m52_hint : 2;) unsigned ipfins$v_m52_x6 : 6;( unsigned ipfins$v_m52_m : 1;- unsigned ipfins$v_m52_opcode : 4;, unsigned ipfins$v_m52_fill : 23; } ipfins$r_m52_0_63;& unsigned __int64 ipfins$q_m52; } ipfins$r_m52; } M52_FORMAT; #if !defined(__VAXC)F#define ipfins1&$v_m52_qp ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_qpL#define ipfins$v_m52_cnt6a ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_cnt6aD#define ipfins$v_m52_h ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_hR#define ipfins$v_m52_stride5b ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_stride5bF#define ipfins$v_m52_18 ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_18D#define ipfins$v_m52_y ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_yF#define ipfins$v_m52_r3 ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_r3D#d 2&efine ipfins$v_m52_x ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_xJ#define ipfins$v_m52_hint ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_hintF#define ipfins$v_m52_x6 ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_x6D#define ipfins$v_m52_m ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_mN#define ipfins$v_m52_opcode ipfins$r_m52.ipfins$r_m52_0_63.ipfins$v_m52_opcode.#define ipfins$q_m52 ipfins$r_m52.ipfins$q_m52"#endif /* #if !defined(__VAXC) */ N/* 3& */I/* B-Unit Formats */N/* */N/* */I/* B1: IP-Relative Branch */N/* */#define IPFINS$M_B1_QP 0x3F#define IPFINS$M_B1_BTYPE 0x1C0#define IPFINS$M_B1_9_4&11 0xE00#define IPFINS$M_B1_P 0x1000&#define IPFINS$M_B1_IMM20B 0x1FFFFE000"#define IPFINS$M_B1_WH 0x600000000!#define IPFINS$M_B1_D 0x800000000"#define IPFINS$M_B1_S 0x1000000000(#define IPFINS$M_B1_OPCODE 0x1E000000000+#define IPFINS$M_B1_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _b1_format {#pragm5&a __nomember_alignment __union { __struct {( unsigned ipfins$v_b1_qp : 6;+ unsigned ipfins$v_b1_btype : 3;* unsigned ipfins$v_b1_9_11 : 3;' unsigned ipfins$v_b1_p : 1;- unsigned ipfins$v_b1_imm20b : 20;( unsigned ipfins$v_b1_wh : 2;' unsigned ipfins$v_b1_d : 1;% signed ipfins$v_b1_s : 1;, unsigned ipfins$v_b1_opcode : 4;+ unsigned ipfins$v_b1_fill : 23; 6& } ipfins$r_b1_0_63;% unsigned __int64 ipfins$q_b1; } ipfins$r_b1; } B1_FORMAT; #if !defined(__VAXC)B#define ipfins$v_b1_qp ipfins$r_b1.ipfins$r_b1_0_63.ipfins$v_b1_qpH#define ipfins$v_b1_btype ipfins$r_b1.ipfins$r_b1_0_63.ipfins$v_b1_btypeF#define ipfins$v_b1_9_11 ipfins$r_b1.ipfins$r_b1_0_63.ipfins$v_b1_9_11@#define ipfins$v_b1_p ipfins$r_b1.ipfins$r_b1_0_63.ipfins$v_b1_pJ#define ipfins$v_b1_imm20b ipfins$r_b1.ipfins$r_b1_0_63.ipfins$v_b1_imm20bB#define ipfins 7&$v_b1_wh ipfins$r_b1.ipfins$r_b1_0_63.ipfins$v_b1_wh@#define ipfins$v_b1_d ipfins$r_b1.ipfins$r_b1_0_63.ipfins$v_b1_d@#define ipfins$v_b1_s ipfins$r_b1.ipfins$r_b1_0_63.ipfins$v_b1_sJ#define ipfins$v_b1_opcode ipfins$r_b1.ipfins$r_b1_0_63.ipfins$v_b1_opcode+#define ipfins$q_b1 ipfins$r_b1.ipfins$q_b1"#endif /* #if !defined(__VAXC) */ N/* */I/* B2: IP-Relative Counted Branch */N/* 8& */#define IPFINS$M_B2_ZERO 0x3F#define IPFINS$M_B2_BTYPE 0x1C0#define IPFINS$M_B2_9_11 0xE00#define IPFINS$M_B2_P 0x1000&#define IPFINS$M_B2_IMM20B 0x1FFFFE000"#define IPFINS$M_B2_WH 0x600000000!#define IPFINS$M_B2_D 0x800000000"#define IPFINS$M_B2_S 0x1000000000(#define IPFINS$M_B2_OPCODE 0x1E000000000+#define IPFINS$M_B2_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus9&) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _b2_format {#pragma __nomember_alignment __union { __struct {* unsigned ipfins$v_b2_zero : 6;+ unsigned ipfins$v_b2_btype : 3;* unsigned ipfins$v_b2_9_11 : 3;' unsigned ipfins$v_b2_p : 1;- unsigned ipfins$v_b2_imm20b : 20;( unsigned ipfins$v_b2_wh : 2;' :&unsigned ipfins$v_b2_d : 1;% signed ipfins$v_b2_s : 1;, unsigned ipfins$v_b2_opcode : 4;+ unsigned ipfins$v_b2_fill : 23; } ipfins$r_b2_0_63;% unsigned __int64 ipfins$q_b2; } ipfins$r_b2; } B2_FORMAT; #if !defined(__VAXC)F#define ipfins$v_b2_zero ipfins$r_b2.ipfins$r_b2_0_63.ipfins$v_b2_zeroH#define ipfins$v_b2_btype ipfins$r_b2.ipfins$r_b2_0_63.ipfins$v_b2_btypeF#define ipfins$v_b2_9_11 ipfins$r_b2.ipfins$r_b2_0_63.ip ;&fins$v_b2_9_11@#define ipfins$v_b2_p ipfins$r_b2.ipfins$r_b2_0_63.ipfins$v_b2_pJ#define ipfins$v_b2_imm20b ipfins$r_b2.ipfins$r_b2_0_63.ipfins$v_b2_imm20bB#define ipfins$v_b2_wh ipfins$r_b2.ipfins$r_b2_0_63.ipfins$v_b2_wh@#define ipfins$v_b2_d ipfins$r_b2.ipfins$r_b2_0_63.ipfins$v_b2_d@#define ipfins$v_b2_s ipfins$r_b2.ipfins$r_b2_0_63.ipfins$v_b2_sJ#define ipfins$v_b2_opcode ipfins$r_b2.ipfins$r_b2_0_63.ipfins$v_b2_opcode+#define ipfins$q_b2 ipfins$r_b2.ipfins$q_b2"#endif /* #if !defined(__ <&VAXC) */ N/* */I/* B3: IP-Relative Call */N/* */#define IPFINS$M_B3_QP 0x3F#define IPFINS$M_B3_B1 0x1C0#define IPFINS$M_B3_9_11 0xE00#define IPFINS$M_B3_P 0x1000&#define IPFINS$M_B3_IMM20B 0x1FFFFE000"#define IPFINS$M_B3_WH 0x600000000!#define IPFINS$M_B3_D 0x800000000"#define IPFINS$M_B3_S =&0x1000000000(#define IPFINS$M_B3_OPCODE 0x1E000000000+#define IPFINS$M_B3_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _b3_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_b3_qp : 6;( unsigned ipfins$v_b3_b1 : 3;* unsigned ipfins$>&v_b3_9_11 : 3;' unsigned ipfins$v_b3_p : 1;- unsigned ipfins$v_b3_imm20b : 20;( unsigned ipfins$v_b3_wh : 2;' unsigned ipfins$v_b3_d : 1;% signed ipfins$v_b3_s : 1;, unsigned ipfins$v_b3_opcode : 4;+ unsigned ipfins$v_b3_fill : 23; } ipfins$r_b3_0_63;% unsigned __int64 ipfins$q_b3; } ipfins$r_b3; } B3_FORMAT; #if !defined(__VAXC)B#define ipfins$v_b3_qp ipfins$r_b3.ipfins$?&r_b3_0_63.ipfins$v_b3_qpB#define ipfins$v_b3_b1 ipfins$r_b3.ipfins$r_b3_0_63.ipfins$v_b3_b1F#define ipfins$v_b3_9_11 ipfins$r_b3.ipfins$r_b3_0_63.ipfins$v_b3_9_11@#define ipfins$v_b3_p ipfins$r_b3.ipfins$r_b3_0_63.ipfins$v_b3_pJ#define ipfins$v_b3_imm20b ipfins$r_b3.ipfins$r_b3_0_63.ipfins$v_b3_imm20bB#define ipfins$v_b3_wh ipfins$r_b3.ipfins$r_b3_0_63.ipfins$v_b3_wh@#define ipfins$v_b3_d ipfins$r_b3.ipfins$r_b3_0_63.ipfins$v_b3_d@#define ipfins$v_b3_s ipfins$r_b3.ipfins$r_b3_0_63.ipfins$v_b3_s @&J#define ipfins$v_b3_opcode ipfins$r_b3.ipfins$r_b3_0_63.ipfins$v_b3_opcode+#define ipfins$q_b3 ipfins$r_b3.ipfins$q_b3"#endif /* #if !defined(__VAXC) */ N/* */I/* B4: Indirect Branch */N/* */#define IPFINS$M_B4_QP 0x3F#define IPFINS$M_B4_BTYPE 0x1C0#define IPFINS$M_B4_9_11 0xE00#define IPA&FINS$M_B4_P 0x1000#define IPFINS$M_B4_B2 0xE000##define IPFINS$M_B4_16_26 0x7FF0000"#define IPFINS$M_B4_X6 0x1F8000000"#define IPFINS$M_B4_WH 0x600000000!#define IPFINS$M_B4_D 0x800000000##define IPFINS$M_B4_36 0x1000000000(#define IPFINS$M_B4_OPCODE 0x1E000000000+#define IPFINS$M_B4_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignmeB&nt#endiftypedef struct _b4_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_b4_qp : 6;+ unsigned ipfins$v_b4_btype : 3;* unsigned ipfins$v_b4_9_11 : 3;' unsigned ipfins$v_b4_p : 1;( unsigned ipfins$v_b4_b2 : 3;, unsigned ipfins$v_b4_16_26 : 11;( unsigned ipfins$v_b4_x6 : 6;( unsigned ipfins$v_b4_wh : 2;' unsigned ipfins$v_b4_d : 1;( C& unsigned ipfins$v_b4_36 : 1;, unsigned ipfins$v_b4_opcode : 4;+ unsigned ipfins$v_b4_fill : 23; } ipfins$r_b4_0_63;% unsigned __int64 ipfins$q_b4; } ipfins$r_b4; } B4_FORMAT; #if !defined(__VAXC)B#define ipfins$v_b4_qp ipfins$r_b4.ipfins$r_b4_0_63.ipfins$v_b4_qpH#define ipfins$v_b4_btype ipfins$r_b4.ipfins$r_b4_0_63.ipfins$v_b4_btypeF#define ipfins$v_b4_9_11 ipfins$r_b4.ipfins$r_b4_0_63.ipfins$v_b4_9_11@#define ipfins$v_b4_p ipD&fins$r_b4.ipfins$r_b4_0_63.ipfins$v_b4_pB#define ipfins$v_b4_b2 ipfins$r_b4.ipfins$r_b4_0_63.ipfins$v_b4_b2H#define ipfins$v_b4_16_26 ipfins$r_b4.ipfins$r_b4_0_63.ipfins$v_b4_16_26B#define ipfins$v_b4_x6 ipfins$r_b4.ipfins$r_b4_0_63.ipfins$v_b4_x6B#define ipfins$v_b4_wh ipfins$r_b4.ipfins$r_b4_0_63.ipfins$v_b4_wh@#define ipfins$v_b4_d ipfins$r_b4.ipfins$r_b4_0_63.ipfins$v_b4_dB#define ipfins$v_b4_36 ipfins$r_b4.ipfins$r_b4_0_63.ipfins$v_b4_36J#define ipfins$v_b4_opcode ipfins$r_b4.ipfins$r_b4_0 E&_63.ipfins$v_b4_opcode+#define ipfins$q_b4 ipfins$r_b4.ipfins$q_b4"#endif /* #if !defined(__VAXC) */ N/* */I/* B5: Indirect Call */N/* */#define IPFINS$M_B5_QP 0x3F#define IPFINS$M_B5_B1 0x1C0#define IPFINS$M_B5_9_11 0xE00#define IPFINS$M_B5_P 0x1000#define IPFINS$M_B5_B2 0xE000$#definF&e IPFINS$M_B5_16_31 0xFFFF0000"#define IPFINS$M_B5_WH 0x700000000!#define IPFINS$M_B5_D 0x800000000##define IPFINS$M_B5_36 0x1000000000(#define IPFINS$M_B5_OPCODE 0x1E000000000+#define IPFINS$M_B5_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _b5_format {#pragma __nomember_alignment __union { G& __struct {( unsigned ipfins$v_b5_qp : 6;( unsigned ipfins$v_b5_b1 : 3;* unsigned ipfins$v_b5_9_11 : 3;' unsigned ipfins$v_b5_p : 1;( unsigned ipfins$v_b5_b2 : 3;, unsigned ipfins$v_b5_16_31 : 16;( unsigned ipfins$v_b5_wh : 3;' unsigned ipfins$v_b5_d : 1;( unsigned ipfins$v_b5_36 : 1;, unsigned ipfins$v_b5_opcode : 4;+ unsigned ipfins$v_b5_fill : 23; } H&ipfins$r_b5_0_63;% unsigned __int64 ipfins$q_b5; } ipfins$r_b5; } B5_FORMAT; #if !defined(__VAXC)B#define ipfins$v_b5_qp ipfins$r_b5.ipfins$r_b5_0_63.ipfins$v_b5_qpB#define ipfins$v_b5_b1 ipfins$r_b5.ipfins$r_b5_0_63.ipfins$v_b5_b1F#define ipfins$v_b5_9_11 ipfins$r_b5.ipfins$r_b5_0_63.ipfins$v_b5_9_11@#define ipfins$v_b5_p ipfins$r_b5.ipfins$r_b5_0_63.ipfins$v_b5_pB#define ipfins$v_b5_b2 ipfins$r_b5.ipfins$r_b5_0_63.ipfins$v_b5_b2H#define ipfins$v_b5_16_31 ipfins$r_b I&5.ipfins$r_b5_0_63.ipfins$v_b5_16_31B#define ipfins$v_b5_wh ipfins$r_b5.ipfins$r_b5_0_63.ipfins$v_b5_wh@#define ipfins$v_b5_d ipfins$r_b5.ipfins$r_b5_0_63.ipfins$v_b5_dB#define ipfins$v_b5_36 ipfins$r_b5.ipfins$r_b5_0_63.ipfins$v_b5_36J#define ipfins$v_b5_opcode ipfins$r_b5.ipfins$r_b5_0_63.ipfins$v_b5_opcode+#define ipfins$q_b5 ipfins$r_b5.ipfins$q_b5"#endif /* #if !defined(__VAXC) */ N/* */I/* B6: IP-Relative PrediJ&ct */N/* */#define IPFINS$M_B6_PBTV 0x7#define IPFINS$M_B6_X2 0x18#define IPFINS$M_B6_P 0x20!#define IPFINS$M_B6_TIMM7A 0x1FC0&#define IPFINS$M_B6_IMM20B 0x1FFFFE000##define IPFINS$M_B6_T2E 0x600000000"#define IPFINS$M_B6_IH 0x800000000"#define IPFINS$M_B6_S 0x1000000000(#define IPFINS$M_B6_OPCODE 0x1E000000000+#define IPFINS$M_B6_FILL 0xFFFFFE0000000000 c#if !defK&ined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _b6_format {#pragma __nomember_alignment __union { __struct {* unsigned ipfins$v_b6_pbtv : 3;( unsigned ipfins$v_b6_x2 : 2;' unsigned ipfins$v_b6_p : 1;, unsigned ipfins$v_b6_timm7a : 7;- unsigned ipfins$v_b6_imm20b : 20;' L& signed ipfins$v_b6_t2e : 2;( unsigned ipfins$v_b6_ih : 1;% signed ipfins$v_b6_s : 1;, unsigned ipfins$v_b6_opcode : 4;+ unsigned ipfins$v_b6_fill : 23; } ipfins$r_b6_0_63;% unsigned __int64 ipfins$q_b6; } ipfins$r_b6; } B6_FORMAT; #if !defined(__VAXC)F#define ipfins$v_b6_pbtv ipfins$r_b6.ipfins$r_b6_0_63.ipfins$v_b6_pbtvB#define ipfins$v_b6_x2 ipfins$r_b6.ipfins$r_b6_0_63.ipfins$v_b6_x2@#define ipfiM&ns$v_b6_p ipfins$r_b6.ipfins$r_b6_0_63.ipfins$v_b6_pJ#define ipfins$v_b6_timm7a ipfins$r_b6.ipfins$r_b6_0_63.ipfins$v_b6_timm7aJ#define ipfins$v_b6_imm20b ipfins$r_b6.ipfins$r_b6_0_63.ipfins$v_b6_imm20bD#define ipfins$v_b6_t2e ipfins$r_b6.ipfins$r_b6_0_63.ipfins$v_b6_t2eB#define ipfins$v_b6_ih ipfins$r_b6.ipfins$r_b6_0_63.ipfins$v_b6_ih@#define ipfins$v_b6_s ipfins$r_b6.ipfins$r_b6_0_63.ipfins$v_b6_sJ#define ipfins$v_b6_opcode ipfins$r_b6.ipfins$r_b6_0_63.ipfins$v_b6_opcode+#define ipfins$q_b6 N&ipfins$r_b6.ipfins$q_b6"#endif /* #if !defined(__VAXC) */ N/* */I/* B7: Indirect Predict */N/* */#define IPFINS$M_B7_PBTV 0x7#define IPFINS$M_B7_WH 0x18#define IPFINS$M_B7_P 0x20!#define IPFINS$M_B7_TIMM7A 0x1FC0#define IPFINS$M_B7_B2 0xE000##define IPFINS$M_B7_16_26 0x7FF0000"#define IPO&FINS$M_B7_X6 0x1F8000000##define IPFINS$M_B7_T2E 0x600000000"#define IPFINS$M_B7_IH 0x800000000##define IPFINS$M_B7_36 0x1000000000(#define IPFINS$M_B7_OPCODE 0x1E000000000+#define IPFINS$M_B7_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _b7_format {#pragma __nomember_alignment __union { __ P&struct {* unsigned ipfins$v_b7_pbtv : 3;( unsigned ipfins$v_b7_wh : 2;' unsigned ipfins$v_b7_p : 1;, unsigned ipfins$v_b7_timm7a : 7;( unsigned ipfins$v_b7_b2 : 3;, unsigned ipfins$v_b7_16_26 : 11;( unsigned ipfins$v_b7_x6 : 6;' signed ipfins$v_b7_t2e : 2;( unsigned ipfins$v_b7_ih : 1;( unsigned ipfins$v_b7_36 : 1;, unsigned ipfins$v_b7_opcode : 4;+ unsign Q&ed ipfins$v_b7_fill : 23; } ipfins$r_b7_0_63;% unsigned __int64 ipfins$q_b7; } ipfins$r_b7; } B7_FORMAT; #if !defined(__VAXC)F#define ipfins$v_b7_pbtv ipfins$r_b7.ipfins$r_b7_0_63.ipfins$v_b7_pbtvB#define ipfins$v_b7_wh ipfins$r_b7.ipfins$r_b7_0_63.ipfins$v_b7_wh@#define ipfins$v_b7_p ipfins$r_b7.ipfins$r_b7_0_63.ipfins$v_b7_pJ#define ipfins$v_b7_timm7a ipfins$r_b7.ipfins$r_b7_0_63.ipfins$v_b7_timm7aB#define ipfins$v_b7_b2 ipfins$r_b7.ipfins$r_b7_0_63.ip R&fins$v_b7_b2H#define ipfins$v_b7_16_26 ipfins$r_b7.ipfins$r_b7_0_63.ipfins$v_b7_16_26B#define ipfins$v_b7_x6 ipfins$r_b7.ipfins$r_b7_0_63.ipfins$v_b7_x6D#define ipfins$v_b7_t2e ipfins$r_b7.ipfins$r_b7_0_63.ipfins$v_b7_t2eB#define ipfins$v_b7_ih ipfins$r_b7.ipfins$r_b7_0_63.ipfins$v_b7_ihB#define ipfins$v_b7_36 ipfins$r_b7.ipfins$r_b7_0_63.ipfins$v_b7_36J#define ipfins$v_b7_opcode ipfins$r_b7.ipfins$r_b7_0_63.ipfins$v_b7_opcode+#define ipfins$q_b7 ipfins$r_b7.ipfins$q_b7"#endif /* #if !define S&d(__VAXC) */ N/* */I/* B8: Miscellaneous (B-Unit) */N/* */#define IPFINS$M_B8_ZERO 0x3F"#define IPFINS$M_B8_6_26 0x7FFFFC0"#define IPFINS$M_B8_X6 0x1F8000000&#define IPFINS$M_B8_33_36 0x1E00000000(#define IPFINS$M_B8_OPCODE 0x1E000000000+#define IPFINS$M_B8_FILL 0xFFFFFE0000000000 c#if !defined(__NT&OBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _b8_format {#pragma __nomember_alignment __union { __struct {* unsigned ipfins$v_b8_zero : 6;+ unsigned ipfins$v_b8_6_26 : 21;( unsigned ipfins$v_b8_x6 : 6;+ unsigned ipfins$v_b8_33_36 : 4;, unsigned ipfins$v_b8_opcode : 4;+ U& unsigned ipfins$v_b8_fill : 23; } ipfins$r_b8_0_63;% unsigned __int64 ipfins$q_b8; } ipfins$r_b8; } B8_FORMAT; #if !defined(__VAXC)F#define ipfins$v_b8_zero ipfins$r_b8.ipfins$r_b8_0_63.ipfins$v_b8_zeroF#define ipfins$v_b8_6_26 ipfins$r_b8.ipfins$r_b8_0_63.ipfins$v_b8_6_26B#define ipfins$v_b8_x6 ipfins$r_b8.ipfins$r_b8_0_63.ipfins$v_b8_x6H#define ipfins$v_b8_33_36 ipfins$r_b8.ipfins$r_b8_0_63.ipfins$v_b8_33_36J#define ipfins$v_b8_opcode ipfins$r_b8.ipf V&ins$r_b8_0_63.ipfins$v_b8_opcode+#define ipfins$q_b8 ipfins$r_b8.ipfins$q_b8"#endif /* #if !defined(__VAXC) */ N/* */I/* B9: Break/Nop/Hint (B-Unit) */N/* */#define IPFINS$M_B9_QP 0x3F$#define IPFINS$M_B9_IMM20A 0x3FFFFC0 #define IPFINS$M_B9_26 0x4000000"#define IPFINS$M_B9_X6 0x1F8000000%#define IPFIW&NS$M_B9_33_35 0xE00000000"#define IPFINS$M_B9_I 0x1000000000(#define IPFINS$M_B9_OPCODE 0x1E000000000+#define IPFINS$M_B9_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _b9_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_b9_qp : 6;- unsignedX& ipfins$v_b9_imm20a : 20;( unsigned ipfins$v_b9_26 : 1;( unsigned ipfins$v_b9_x6 : 6;+ unsigned ipfins$v_b9_33_35 : 3;' unsigned ipfins$v_b9_i : 1;, unsigned ipfins$v_b9_opcode : 4;+ unsigned ipfins$v_b9_fill : 23; } ipfins$r_b9_0_63;% unsigned __int64 ipfins$q_b9; } ipfins$r_b9; } B9_FORMAT; #if !defined(__VAXC)B#define ipfins$v_b9_qp ipfins$r_b9.ipfins$r_b9_0_63.ipfins$v_b9_qpJ#def Y&ine ipfins$v_b9_imm20a ipfins$r_b9.ipfins$r_b9_0_63.ipfins$v_b9_imm20aB#define ipfins$v_b9_26 ipfins$r_b9.ipfins$r_b9_0_63.ipfins$v_b9_26B#define ipfins$v_b9_x6 ipfins$r_b9.ipfins$r_b9_0_63.ipfins$v_b9_x6H#define ipfins$v_b9_33_35 ipfins$r_b9.ipfins$r_b9_0_63.ipfins$v_b9_33_35@#define ipfins$v_b9_i ipfins$r_b9.ipfins$r_b9_0_63.ipfins$v_b9_iJ#define ipfins$v_b9_opcode ipfins$r_b9.ipfins$r_b9_0_63.ipfins$v_b9_opcode+#define ipfins$q_b9 ipfins$r_b9.ipfins$q_b9"#endif /* #if !defined(__VAXC) */ Z& N/* */I/* B10: Instr Prefetch */N/* */#define IPFINS$M_B10_PBTV 0x7#define IPFINS$M_B10_X2 0x18#define IPFINS$M_B10_5 0x20##define IPFINS$M_B10_COUNT7A 0x1FC0'#define IPFINS$M_B10_IMM20B 0x1FFFFE000$#define IPFINS$M_B10_C2E 0x600000000"#define IPFINS$M_B10_F 0x800000000##define IPFINS$M_B10[&_S 0x1000000000)#define IPFINS$M_B10_OPCODE 0x1E000000000,#define IPFINS$M_B10_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _b10_format {#pragma __nomember_alignment __union { __struct {+ unsigned ipfins$v_b10_pbtv : 3;) unsigned ipfins$v_b10_x2 : 2;( unsi\&gned ipfins$v_b10_5 : 1;. unsigned ipfins$v_b10_count7a : 7;. unsigned ipfins$v_b10_imm20b : 20;* unsigned ipfins$v_b10_c2e : 2;( unsigned ipfins$v_b10_f : 1;& signed ipfins$v_b10_s : 1;- unsigned ipfins$v_b10_opcode : 4;, unsigned ipfins$v_b10_fill : 23; } ipfins$r_b10_0_63;& unsigned __int64 ipfins$q_b10; } ipfins$r_b10; } B10_FORMAT; #if !defined(__VAXC)J#define ipfins$v_b]&10_pbtv ipfins$r_b10.ipfins$r_b10_0_63.ipfins$v_b10_pbtvF#define ipfins$v_b10_x2 ipfins$r_b10.ipfins$r_b10_0_63.ipfins$v_b10_x2D#define ipfins$v_b10_5 ipfins$r_b10.ipfins$r_b10_0_63.ipfins$v_b10_5P#define ipfins$v_b10_count7a ipfins$r_b10.ipfins$r_b10_0_63.ipfins$v_b10_count7aN#define ipfins$v_b10_imm20b ipfins$r_b10.ipfins$r_b10_0_63.ipfins$v_b10_imm20bH#define ipfins$v_b10_c2e ipfins$r_b10.ipfins$r_b10_0_63.ipfins$v_b10_c2eD#define ipfins$v_b10_f ipfins$r_b10.ipfins$r_b10_0_63.ipfins$v_b10_fD ^&#define ipfins$v_b10_s ipfins$r_b10.ipfins$r_b10_0_63.ipfins$v_b10_sN#define ipfins$v_b10_opcode ipfins$r_b10.ipfins$r_b10_0_63.ipfins$v_b10_opcode.#define ipfins$q_b10 ipfins$r_b10.ipfins$q_b10"#endif /* #if !defined(__VAXC) */ N/* */I/* F-Unit Formats */N/* */N/* _& */I/* F1: Floating-point Multiply Add */N/* */#define IPFINS$M_F1_QP 0x3F#define IPFINS$M_F1_F1 0x1FC0#define IPFINS$M_F1_F2 0xFE000 #define IPFINS$M_F1_F3 0x7F00000"#define IPFINS$M_F1_F4 0x3F8000000"#define IPFINS$M_F1_SF 0xC00000000"#define IPFINS$M_F1_X 0x1000000000(#define IPFINS$M_F1_OPCODE 0x1E000000000+#define IPFINS$M_F1_FILL`& 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f1_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_f1_qp : 6;( unsigned ipfins$v_f1_f1 : 7;( unsigned ipfins$v_f1_f2 : 7;( unsigned ipfins$v_f1_f3 : 7;( unsigned ipfa&ins$v_f1_f4 : 7;( unsigned ipfins$v_f1_sf : 2;' unsigned ipfins$v_f1_x : 1;, unsigned ipfins$v_f1_opcode : 4;+ unsigned ipfins$v_f1_fill : 23; } ipfins$r_f1_0_63;% unsigned __int64 ipfins$q_f1; } ipfins$r_f1; } F1_FORMAT; #if !defined(__VAXC)B#define ipfins$v_f1_qp ipfins$r_f1.ipfins$r_f1_0_63.ipfins$v_f1_qpB#define ipfins$v_f1_f1 ipfins$r_f1.ipfins$r_f1_0_63.ipfins$v_f1_f1B#define ipfins$v_f1_f2 ipfins$r_f1 b&.ipfins$r_f1_0_63.ipfins$v_f1_f2B#define ipfins$v_f1_f3 ipfins$r_f1.ipfins$r_f1_0_63.ipfins$v_f1_f3B#define ipfins$v_f1_f4 ipfins$r_f1.ipfins$r_f1_0_63.ipfins$v_f1_f4B#define ipfins$v_f1_sf ipfins$r_f1.ipfins$r_f1_0_63.ipfins$v_f1_sf@#define ipfins$v_f1_x ipfins$r_f1.ipfins$r_f1_0_63.ipfins$v_f1_xJ#define ipfins$v_f1_opcode ipfins$r_f1.ipfins$r_f1_0_63.ipfins$v_f1_opcode+#define ipfins$q_f1 ipfins$r_f1.ipfins$q_f1"#endif /* #if !defined(__VAXC) */ N/* c& */I/* F2: Fixed-point Multiply Add */N/* */#define IPFINS$M_F2_QP 0x3F#define IPFINS$M_F2_F1 0x1FC0#define IPFINS$M_F2_F2 0xFE000 #define IPFINS$M_F2_F3 0x7F00000"#define IPFINS$M_F2_F4 0x3F8000000"#define IPFINS$M_F2_X2 0xC00000000"#define IPFINS$M_F2_X 0x1000000000(#define IPFINS$M_F2_OPCODE 0x1E000000000+#define IPFINS$M_F2_FILL 0xFFFFFd&E0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f2_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_f2_qp : 6;( unsigned ipfins$v_f2_f1 : 7;( unsigned ipfins$v_f2_f2 : 7;( unsigned ipfins$v_f2_f3 : 7;( unsigned ipfins$v_f2e&_f4 : 7;( unsigned ipfins$v_f2_x2 : 2;' unsigned ipfins$v_f2_x : 1;, unsigned ipfins$v_f2_opcode : 4;+ unsigned ipfins$v_f2_fill : 23; } ipfins$r_f2_0_63;% unsigned __int64 ipfins$q_f2; } ipfins$r_f2; } F2_FORMAT; #if !defined(__VAXC)B#define ipfins$v_f2_qp ipfins$r_f2.ipfins$r_f2_0_63.ipfins$v_f2_qpB#define ipfins$v_f2_f1 ipfins$r_f2.ipfins$r_f2_0_63.ipfins$v_f2_f1B#define ipfins$v_f2_f2 ipfins$r_f2.ipfins$ f&r_f2_0_63.ipfins$v_f2_f2B#define ipfins$v_f2_f3 ipfins$r_f2.ipfins$r_f2_0_63.ipfins$v_f2_f3B#define ipfins$v_f2_f4 ipfins$r_f2.ipfins$r_f2_0_63.ipfins$v_f2_f4B#define ipfins$v_f2_x2 ipfins$r_f2.ipfins$r_f2_0_63.ipfins$v_f2_x2@#define ipfins$v_f2_x ipfins$r_f2.ipfins$r_f2_0_63.ipfins$v_f2_xJ#define ipfins$v_f2_opcode ipfins$r_f2.ipfins$r_f2_0_63.ipfins$v_f2_opcode+#define ipfins$q_f2 ipfins$r_f2.ipfins$q_f2"#endif /* #if !defined(__VAXC) */ N/* g& */I/* F3: Parallel Floating-point Select */N/* */#define IPFINS$M_F3_QP 0x3F#define IPFINS$M_F3_F1 0x1FC0#define IPFINS$M_F3_F2 0xFE000 #define IPFINS$M_F3_F3 0x7F00000"#define IPFINS$M_F3_F4 0x3F8000000%#define IPFINS$M_F3_34_35 0xC00000000"#define IPFINS$M_F3_X 0x1000000000(#define IPFINS$M_F3_OPCODE 0x1E000000000+#define IPFINS$M_F3_FILL 0xFFFFFE000h&0000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f3_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_f3_qp : 6;( unsigned ipfins$v_f3_f1 : 7;( unsigned ipfins$v_f3_f2 : 7;( unsigned ipfins$v_f3_f3 : 7;( unsigned ipfins$v_f3_f4 i&: 7;+ unsigned ipfins$v_f3_34_35 : 2;' unsigned ipfins$v_f3_x : 1;, unsigned ipfins$v_f3_opcode : 4;+ unsigned ipfins$v_f3_fill : 23; } ipfins$r_f3_0_63;% unsigned __int64 ipfins$q_f3; } ipfins$r_f3; } F3_FORMAT; #if !defined(__VAXC)B#define ipfins$v_f3_qp ipfins$r_f3.ipfins$r_f3_0_63.ipfins$v_f3_qpB#define ipfins$v_f3_f1 ipfins$r_f3.ipfins$r_f3_0_63.ipfins$v_f3_f1B#define ipfins$v_f3_f2 ipfins$r_f3.ipfins$ j&r_f3_0_63.ipfins$v_f3_f2B#define ipfins$v_f3_f3 ipfins$r_f3.ipfins$r_f3_0_63.ipfins$v_f3_f3B#define ipfins$v_f3_f4 ipfins$r_f3.ipfins$r_f3_0_63.ipfins$v_f3_f4H#define ipfins$v_f3_34_35 ipfins$r_f3.ipfins$r_f3_0_63.ipfins$v_f3_34_35@#define ipfins$v_f3_x ipfins$r_f3.ipfins$r_f3_0_63.ipfins$v_f3_xJ#define ipfins$v_f3_opcode ipfins$r_f3.ipfins$r_f3_0_63.ipfins$v_f3_opcode+#define ipfins$q_f3 ipfins$r_f3.ipfins$q_f3"#endif /* #if !defined(__VAXC) */ N/* k& */I/* F4: Floating-point Compare */N/* */#define IPFINS$M_F4_QP 0x3F#define IPFINS$M_F4_P1 0xFC0#define IPFINS$M_F4_TA 0x1000#define IPFINS$M_F4_F2 0xFE000 #define IPFINS$M_F4_F3 0x7F00000"#define IPFINS$M_F4_P2 0x1F8000000"#define IPFINS$M_F4_RA 0x200000000"#define IPFINS$M_F4_SF 0xC00000000##define IPFINS$M_F4_RB 0x1000000000(#define l&IPFINS$M_F4_OPCODE 0x1E000000000+#define IPFINS$M_F4_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f4_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_f4_qp : 6;( unsigned ipfins$v_f4_p1 : 6;( unsigned ipfins$v_f4_ta : 1;( m& unsigned ipfins$v_f4_f2 : 7;( unsigned ipfins$v_f4_f3 : 7;( unsigned ipfins$v_f4_p2 : 6;( unsigned ipfins$v_f4_ra : 1;( unsigned ipfins$v_f4_sf : 2;( unsigned ipfins$v_f4_rb : 1;, unsigned ipfins$v_f4_opcode : 4;+ unsigned ipfins$v_f4_fill : 23; } ipfins$r_f4_0_63;% unsigned __int64 ipfins$q_f4; } ipfins$r_f4; } F4_FORMAT; #if !defined(__VAXC)B#define ipfins$v_f4_qp ipfinn&s$r_f4.ipfins$r_f4_0_63.ipfins$v_f4_qpB#define ipfins$v_f4_p1 ipfins$r_f4.ipfins$r_f4_0_63.ipfins$v_f4_p1B#define ipfins$v_f4_ta ipfins$r_f4.ipfins$r_f4_0_63.ipfins$v_f4_taB#define ipfins$v_f4_f2 ipfins$r_f4.ipfins$r_f4_0_63.ipfins$v_f4_f2B#define ipfins$v_f4_f3 ipfins$r_f4.ipfins$r_f4_0_63.ipfins$v_f4_f3B#define ipfins$v_f4_p2 ipfins$r_f4.ipfins$r_f4_0_63.ipfins$v_f4_p2B#define ipfins$v_f4_ra ipfins$r_f4.ipfins$r_f4_0_63.ipfins$v_f4_raB#define ipfins$v_f4_sf ipfins$r_f4.ipfins$r_f4_0_63.ipfins o&$v_f4_sfB#define ipfins$v_f4_rb ipfins$r_f4.ipfins$r_f4_0_63.ipfins$v_f4_rbJ#define ipfins$v_f4_opcode ipfins$r_f4.ipfins$r_f4_0_63.ipfins$v_f4_opcode+#define ipfins$q_f4 ipfins$r_f4.ipfins$q_f4"#endif /* #if !defined(__VAXC) */ N/* */I/* F5: Floating-point Class */N/* */#define IPFINS$M_F5_QP 0x3Fp&#define IPFINS$M_F5_P1 0xFC0#define IPFINS$M_F5_TA 0x1000#define IPFINS$M_F5_F2 0xFE000&#define IPFINS$M_F5_FCLASS7C 0x7F00000"#define IPFINS$M_F5_P2 0x1F8000000##define IPFINS$M_F5_FC2 0x600000000&#define IPFINS$M_F5_35_36 0x1800000000(#define IPFINS$M_F5_OPCODE 0x1E000000000+#define IPFINS$M_F5_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomeq&mber_alignment#endiftypedef struct _f5_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_f5_qp : 6;( unsigned ipfins$v_f5_p1 : 6;( unsigned ipfins$v_f5_ta : 1;( unsigned ipfins$v_f5_f2 : 7;. unsigned ipfins$v_f5_fclass7c : 7;( unsigned ipfins$v_f5_p2 : 6;) unsigned ipfins$v_f5_fc2 : 2;+ unsigned ipfins$v_f5_35_36 : 2;, unsigned ipfins$v_f5_opc r&ode : 4;+ unsigned ipfins$v_f5_fill : 23; } ipfins$r_f5_0_63;% unsigned __int64 ipfins$q_f5; } ipfins$r_f5; } F5_FORMAT; #if !defined(__VAXC)B#define ipfins$v_f5_qp ipfins$r_f5.ipfins$r_f5_0_63.ipfins$v_f5_qpB#define ipfins$v_f5_p1 ipfins$r_f5.ipfins$r_f5_0_63.ipfins$v_f5_p1B#define ipfins$v_f5_ta ipfins$r_f5.ipfins$r_f5_0_63.ipfins$v_f5_taB#define ipfins$v_f5_f2 ipfins$r_f5.ipfins$r_f5_0_63.ipfins$v_f5_f2N#define ipfins$v_f5_fclass7c ipfins$ s&r_f5.ipfins$r_f5_0_63.ipfins$v_f5_fclass7cB#define ipfins$v_f5_p2 ipfins$r_f5.ipfins$r_f5_0_63.ipfins$v_f5_p2D#define ipfins$v_f5_fc2 ipfins$r_f5.ipfins$r_f5_0_63.ipfins$v_f5_fc2H#define ipfins$v_f5_35_36 ipfins$r_f5.ipfins$r_f5_0_63.ipfins$v_f5_35_36J#define ipfins$v_f5_opcode ipfins$r_f5.ipfins$r_f5_0_63.ipfins$v_f5_opcode+#define ipfins$q_f5 ipfins$r_f5.ipfins$q_f5"#endif /* #if !defined(__VAXC) */ N/* */I/* F6: F t&loating-point Reciprocal Approximation */N/* */#define IPFINS$M_F6_QP 0x3F#define IPFINS$M_F6_F1 0x1FC0#define IPFINS$M_F6_F2 0xFE000 #define IPFINS$M_F6_F3 0x7F00000"#define IPFINS$M_F6_P2 0x1F8000000!#define IPFINS$M_F6_X 0x200000000"#define IPFINS$M_F6_SF 0xC00000000"#define IPFINS$M_F6_Q 0x1000000000(#define IPFINS$M_F6_OPCODE 0x1E000000000+#define IPFINS$M_F6_FILL 0xFFFFFE0000000000u& c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f6_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_f6_qp : 6;( unsigned ipfins$v_f6_f1 : 7;( unsigned ipfins$v_f6_f2 : 7;( unsigned ipfins$v_f6_f3 : 7;( unsigned ipfins$v_f6_p2 : 6;' v& unsigned ipfins$v_f6_x : 1;( unsigned ipfins$v_f6_sf : 2;' unsigned ipfins$v_f6_q : 1;, unsigned ipfins$v_f6_opcode : 4;+ unsigned ipfins$v_f6_fill : 23; } ipfins$r_f6_0_63;% unsigned __int64 ipfins$q_f6; } ipfins$r_f6; } F6_FORMAT; #if !defined(__VAXC)B#define ipfins$v_f6_qp ipfins$r_f6.ipfins$r_f6_0_63.ipfins$v_f6_qpB#define ipfins$v_f6_f1 ipfins$r_f6.ipfins$r_f6_0_63.ipfins$v_f6_f1B#define ipfiw&ns$v_f6_f2 ipfins$r_f6.ipfins$r_f6_0_63.ipfins$v_f6_f2B#define ipfins$v_f6_f3 ipfins$r_f6.ipfins$r_f6_0_63.ipfins$v_f6_f3B#define ipfins$v_f6_p2 ipfins$r_f6.ipfins$r_f6_0_63.ipfins$v_f6_p2@#define ipfins$v_f6_x ipfins$r_f6.ipfins$r_f6_0_63.ipfins$v_f6_xB#define ipfins$v_f6_sf ipfins$r_f6.ipfins$r_f6_0_63.ipfins$v_f6_sf@#define ipfins$v_f6_q ipfins$r_f6.ipfins$r_f6_0_63.ipfins$v_f6_qJ#define ipfins$v_f6_opcode ipfins$r_f6.ipfins$r_f6_0_63.ipfins$v_f6_opcode+#define ipfins$q_f6 ipfins$r_f6.ipfins x&$q_f6"#endif /* #if !defined(__VAXC) */ N/* */I/* F7: Floating-point Reciprocal Square Root Approximation */N/* */#define IPFINS$M_F7_QP 0x3F#define IPFINS$M_F7_F1 0x1FC0 #define IPFINS$M_F7_ZERO 0xFE000 #define IPFINS$M_F7_F3 0x7F00000"#define IPFINS$M_F7_P2 0x1F8000000!#define IPFINS$M_F7_X 0x200000000"#define IPFINS$M_F7_y&SF 0xC00000000"#define IPFINS$M_F7_Q 0x1000000000(#define IPFINS$M_F7_OPCODE 0x1E000000000+#define IPFINS$M_F7_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f7_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_f7_qp : 6;( unsigned ipfins$v_f7z&_f1 : 7;* unsigned ipfins$v_f7_zero : 7;( unsigned ipfins$v_f7_f3 : 7;( unsigned ipfins$v_f7_p2 : 6;' unsigned ipfins$v_f7_x : 1;( unsigned ipfins$v_f7_sf : 2;' unsigned ipfins$v_f7_q : 1;, unsigned ipfins$v_f7_opcode : 4;+ unsigned ipfins$v_f7_fill : 23; } ipfins$r_f7_0_63;% unsigned __int64 ipfins$q_f7; } ipfins$r_f7; } F7_FORMAT; #if !defined(__VAXC)B#define {&ipfins$v_f7_qp ipfins$r_f7.ipfins$r_f7_0_63.ipfins$v_f7_qpB#define ipfins$v_f7_f1 ipfins$r_f7.ipfins$r_f7_0_63.ipfins$v_f7_f1F#define ipfins$v_f7_zero ipfins$r_f7.ipfins$r_f7_0_63.ipfins$v_f7_zeroB#define ipfins$v_f7_f3 ipfins$r_f7.ipfins$r_f7_0_63.ipfins$v_f7_f3B#define ipfins$v_f7_p2 ipfins$r_f7.ipfins$r_f7_0_63.ipfins$v_f7_p2@#define ipfins$v_f7_x ipfins$r_f7.ipfins$r_f7_0_63.ipfins$v_f7_xB#define ipfins$v_f7_sf ipfins$r_f7.ipfins$r_f7_0_63.ipfins$v_f7_sf@#define ipfins$v_f7_q ipfins$r_f7.ip |&fins$r_f7_0_63.ipfins$v_f7_qJ#define ipfins$v_f7_opcode ipfins$r_f7.ipfins$r_f7_0_63.ipfins$v_f7_opcode+#define ipfins$q_f7 ipfins$r_f7.ipfins$q_f7"#endif /* #if !defined(__VAXC) */ N/* */I/* F8: Minimum/Maximum and Parallel Compare */N/* */#define IPFINS$M_F8_QP 0x3F#define IPFINS$M_F8_F1 0x1FC0#define IPFINS$M}&_F8_F2 0xFE000 #define IPFINS$M_F8_F3 0x7F00000"#define IPFINS$M_F8_X6 0x1F8000000!#define IPFINS$M_F8_X 0x200000000"#define IPFINS$M_F8_SF 0xC00000000##define IPFINS$M_F8_36 0x1000000000(#define IPFINS$M_F8_OPCODE 0x1E000000000+#define IPFINS$M_F8_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f8_format {~&#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_f8_qp : 6;( unsigned ipfins$v_f8_f1 : 7;( unsigned ipfins$v_f8_f2 : 7;( unsigned ipfins$v_f8_f3 : 7;( unsigned ipfins$v_f8_x6 : 6;' unsigned ipfins$v_f8_x : 1;( unsigned ipfins$v_f8_sf : 2;( unsigned ipfins$v_f8_36 : 1;, unsigned ipfins$v_f8_opcode : 4;+ unsigned ipfins$v_f8_fill : 23; & } ipfins$r_f8_0_63;% unsigned __int64 ipfins$q_f8; } ipfins$r_f8; } F8_FORMAT; #if !defined(__VAXC)B#define ipfins$v_f8_qp ipfins$r_f8.ipfins$r_f8_0_63.ipfins$v_f8_qpB#define ipfins$v_f8_f1 ipfins$r_f8.ipfins$r_f8_0_63.ipfins$v_f8_f1B#define ipfins$v_f8_f2 ipfins$r_f8.ipfins$r_f8_0_63.ipfins$v_f8_f2B#define ipfins$v_f8_f3 ipfins$r_f8.ipfins$r_f8_0_63.ipfins$v_f8_f3B#define ipfins$v_f8_x6 ipfins$r_f8.ipfins$r_f8_0_63.ipfins$v_f8_x6@#define ipfins$v_f8_x ipfins$r_f &8.ipfins$r_f8_0_63.ipfins$v_f8_xB#define ipfins$v_f8_sf ipfins$r_f8.ipfins$r_f8_0_63.ipfins$v_f8_sfB#define ipfins$v_f8_36 ipfins$r_f8.ipfins$r_f8_0_63.ipfins$v_f8_36J#define ipfins$v_f8_opcode ipfins$r_f8.ipfins$r_f8_0_63.ipfins$v_f8_opcode+#define ipfins$q_f8 ipfins$r_f8.ipfins$q_f8"#endif /* #if !defined(__VAXC) */ N/* */I/* F9: Merge and Logical */N/* & */#define IPFINS$M_F9_QP 0x3F#define IPFINS$M_F9_F1 0x1FC0#define IPFINS$M_F9_F2 0xFE000 #define IPFINS$M_F9_F3 0x7F00000"#define IPFINS$M_F9_X6 0x1F8000000!#define IPFINS$M_F9_X 0x200000000&#define IPFINS$M_F9_34_36 0x1C00000000(#define IPFINS$M_F9_OPCODE 0x1E000000000+#define IPFINS$M_F9_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __&nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f9_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_f9_qp : 6;( unsigned ipfins$v_f9_f1 : 7;( unsigned ipfins$v_f9_f2 : 7;( unsigned ipfins$v_f9_f3 : 7;( unsigned ipfins$v_f9_x6 : 6;' unsigned ipfins$v_f9_x : 1;+ unsigned ipfins$v_f9_34_36 : 3;, unsigned ipfins$v_f9 &_opcode : 4;+ unsigned ipfins$v_f9_fill : 23; } ipfins$r_f9_0_63;% unsigned __int64 ipfins$q_f9; } ipfins$r_f9; } F9_FORMAT; #if !defined(__VAXC)B#define ipfins$v_f9_qp ipfins$r_f9.ipfins$r_f9_0_63.ipfins$v_f9_qpB#define ipfins$v_f9_f1 ipfins$r_f9.ipfins$r_f9_0_63.ipfins$v_f9_f1B#define ipfins$v_f9_f2 ipfins$r_f9.ipfins$r_f9_0_63.ipfins$v_f9_f2B#define ipfins$v_f9_f3 ipfins$r_f9.ipfins$r_f9_0_63.ipfins$v_f9_f3B#define ipfins$v_f9_x6 ipfins$r_ &f9.ipfins$r_f9_0_63.ipfins$v_f9_x6@#define ipfins$v_f9_x ipfins$r_f9.ipfins$r_f9_0_63.ipfins$v_f9_xH#define ipfins$v_f9_34_36 ipfins$r_f9.ipfins$r_f9_0_63.ipfins$v_f9_34_36J#define ipfins$v_f9_opcode ipfins$r_f9.ipfins$r_f9_0_63.ipfins$v_f9_opcode+#define ipfins$q_f9 ipfins$r_f9.ipfins$q_f9"#endif /* #if !defined(__VAXC) */ N/* */I/* F10: Convert Floating-point to Fixed-point */N/* & */#define IPFINS$M_F10_QP 0x3F#define IPFINS$M_F10_F1 0x1FC0#define IPFINS$M_F10_F2 0xFE000$#define IPFINS$M_F10_20_26 0x7F00000##define IPFINS$M_F10_X6 0x1F8000000"#define IPFINS$M_F10_X 0x200000000##define IPFINS$M_F10_SF 0xC00000000$#define IPFINS$M_F10_36 0x1000000000)#define IPFINS$M_F10_OPCODE 0x1E000000000,#define IPFINS$M_F10_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus&) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f10_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_f10_qp : 6;) unsigned ipfins$v_f10_f1 : 7;) unsigned ipfins$v_f10_f2 : 7;, unsigned ipfins$v_f10_20_26 : 7;) unsigned ipfins$v_f10_x6 : 6;( unsigned ipfins$v_f10_x : 1;) un &signed ipfins$v_f10_sf : 2;) unsigned ipfins$v_f10_36 : 1;- unsigned ipfins$v_f10_opcode : 4;, unsigned ipfins$v_f10_fill : 23; } ipfins$r_f10_0_63;& unsigned __int64 ipfins$q_f10; } ipfins$r_f10; } F10_FORMAT; #if !defined(__VAXC)F#define ipfins$v_f10_qp ipfins$r_f10.ipfins$r_f10_0_63.ipfins$v_f10_qpF#define ipfins$v_f10_f1 ipfins$r_f10.ipfins$r_f10_0_63.ipfins$v_f10_f1F#define ipfins$v_f10_f2 ipfins$r_f10.ipfins$r_f1&0_0_63.ipfins$v_f10_f2L#define ipfins$v_f10_20_26 ipfins$r_f10.ipfins$r_f10_0_63.ipfins$v_f10_20_26F#define ipfins$v_f10_x6 ipfins$r_f10.ipfins$r_f10_0_63.ipfins$v_f10_x6D#define ipfins$v_f10_x ipfins$r_f10.ipfins$r_f10_0_63.ipfins$v_f10_xF#define ipfins$v_f10_sf ipfins$r_f10.ipfins$r_f10_0_63.ipfins$v_f10_sfF#define ipfins$v_f10_36 ipfins$r_f10.ipfins$r_f10_0_63.ipfins$v_f10_36N#define ipfins$v_f10_opcode ipfins$r_f10.ipfins$r_f10_0_63.ipfins$v_f10_opcode.#define ipfins$q_f10 ipfins$r_f10.ipfi &ns$q_f10"#endif /* #if !defined(__VAXC) */ N/* */I/* F11: Convert Fixed-point to Floating-point */N/* */#define IPFINS$M_F11_QP 0x3F#define IPFINS$M_F11_F1 0x1FC0#define IPFINS$M_F11_F2 0xFE000$#define IPFINS$M_F11_20_26 0x7F00000##define IPFINS$M_F11_X6 0x1F8000000"#define IPFINS$M_F11_X 0x200000000'#define IPFI&NS$M_F11_34_36 0x1C00000000)#define IPFINS$M_F11_OPCODE 0x1E000000000,#define IPFINS$M_F11_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f11_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_f11_qp : 6;) unsigned ipfins$v_f11_f1 : 7;) & unsigned ipfins$v_f11_f2 : 7;, unsigned ipfins$v_f11_20_26 : 7;) unsigned ipfins$v_f11_x6 : 6;( unsigned ipfins$v_f11_x : 1;, unsigned ipfins$v_f11_34_36 : 3;- unsigned ipfins$v_f11_opcode : 4;, unsigned ipfins$v_f11_fill : 23; } ipfins$r_f11_0_63;& unsigned __int64 ipfins$q_f11; } ipfins$r_f11; } F11_FORMAT; #if !defined(__VAXC)F#define ipfins$v_f11_qp ipfins$r_f11.ipfins$r_f11_&0_63.ipfins$v_f11_qpF#define ipfins$v_f11_f1 ipfins$r_f11.ipfins$r_f11_0_63.ipfins$v_f11_f1F#define ipfins$v_f11_f2 ipfins$r_f11.ipfins$r_f11_0_63.ipfins$v_f11_f2L#define ipfins$v_f11_20_26 ipfins$r_f11.ipfins$r_f11_0_63.ipfins$v_f11_20_26F#define ipfins$v_f11_x6 ipfins$r_f11.ipfins$r_f11_0_63.ipfins$v_f11_x6D#define ipfins$v_f11_x ipfins$r_f11.ipfins$r_f11_0_63.ipfins$v_f11_xL#define ipfins$v_f11_34_36 ipfins$r_f11.ipfins$r_f11_0_63.ipfins$v_f11_34_36N#define ipfins$v_f11_opcode ipfins$r_f11.i &pfins$r_f11_0_63.ipfins$v_f11_opcode.#define ipfins$q_f11 ipfins$r_f11.ipfins$q_f11"#endif /* #if !defined(__VAXC) */ N/* */I/* F12: Floating-point Set Controls */N/* */#define IPFINS$M_F12_QP 0x3F #define IPFINS$M_F12_6_12 0x1FC0$#define IPFINS$M_F12_AMASK7B 0xFE000&#define IPFINS$M_F12_OMASK7C 0x7F00000##d&efine IPFINS$M_F12_X6 0x1F8000000"#define IPFINS$M_F12_X 0x200000000##define IPFINS$M_F12_SF 0xC00000000$#define IPFINS$M_F12_36 0x1000000000)#define IPFINS$M_F12_OPCODE 0x1E000000000,#define IPFINS$M_F12_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f12_format {#pragma __nomember_alignment __union { & __struct {) unsigned ipfins$v_f12_qp : 6;+ unsigned ipfins$v_f12_6_12 : 7;. unsigned ipfins$v_f12_amask7b : 7;. unsigned ipfins$v_f12_omask7c : 7;) unsigned ipfins$v_f12_x6 : 6;( unsigned ipfins$v_f12_x : 1;) unsigned ipfins$v_f12_sf : 2;) unsigned ipfins$v_f12_36 : 1;- unsigned ipfins$v_f12_opcode : 4;, unsigned ipfins$v_f12_fill : 23; } ipfins$r_f12_0 &_63;& unsigned __int64 ipfins$q_f12; } ipfins$r_f12; } F12_FORMAT; #if !defined(__VAXC)F#define ipfins$v_f12_qp ipfins$r_f12.ipfins$r_f12_0_63.ipfins$v_f12_qpJ#define ipfins$v_f12_6_12 ipfins$r_f12.ipfins$r_f12_0_63.ipfins$v_f12_6_12P#define ipfins$v_f12_amask7b ipfins$r_f12.ipfins$r_f12_0_63.ipfins$v_f12_amask7bP#define ipfins$v_f12_omask7c ipfins$r_f12.ipfins$r_f12_0_63.ipfins$v_f12_omask7cF#define ipfins$v_f12_x6 ipfins$r_f12.ipfins$r_f12_0_63.ipfins$v_f12_x6D#def &ine ipfins$v_f12_x ipfins$r_f12.ipfins$r_f12_0_63.ipfins$v_f12_xF#define ipfins$v_f12_sf ipfins$r_f12.ipfins$r_f12_0_63.ipfins$v_f12_sfF#define ipfins$v_f12_36 ipfins$r_f12.ipfins$r_f12_0_63.ipfins$v_f12_36N#define ipfins$v_f12_opcode ipfins$r_f12.ipfins$r_f12_0_63.ipfins$v_f12_opcode.#define ipfins$q_f12 ipfins$r_f12.ipfins$q_f12"#endif /* #if !defined(__VAXC) */ N/* */I/* F13: Floating-point Clear Flags & */N/* */#define IPFINS$M_F13_QP 0x3F##define IPFINS$M_F13_6_26 0x7FFFFC0##define IPFINS$M_F13_X6 0x1F8000000"#define IPFINS$M_F13_X 0x200000000##define IPFINS$M_F13_SF 0xC00000000$#define IPFINS$M_F13_36 0x1000000000)#define IPFINS$M_F13_OPCODE 0x1E000000000,#define IPFINS$M_F13_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V&4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f13_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_f13_qp : 6;, unsigned ipfins$v_f13_6_26 : 21;) unsigned ipfins$v_f13_x6 : 6;( unsigned ipfins$v_f13_x : 1;) unsigned ipfins$v_f13_sf : 2;) unsigned ipfins$v_f13_36 : 1;- unsigned ipfins$v_f13_opcode & : 4;, unsigned ipfins$v_f13_fill : 23; } ipfins$r_f13_0_63;& unsigned __int64 ipfins$q_f13; } ipfins$r_f13; } F13_FORMAT; #if !defined(__VAXC)F#define ipfins$v_f13_qp ipfins$r_f13.ipfins$r_f13_0_63.ipfins$v_f13_qpJ#define ipfins$v_f13_6_26 ipfins$r_f13.ipfins$r_f13_0_63.ipfins$v_f13_6_26F#define ipfins$v_f13_x6 ipfins$r_f13.ipfins$r_f13_0_63.ipfins$v_f13_x6D#define ipfins$v_f13_x ipfins$r_f13.ipfins$r_f13_0_63.ipfins$v_f13_xF#define ipfins$v &_f13_sf ipfins$r_f13.ipfins$r_f13_0_63.ipfins$v_f13_sfF#define ipfins$v_f13_36 ipfins$r_f13.ipfins$r_f13_0_63.ipfins$v_f13_36N#define ipfins$v_f13_opcode ipfins$r_f13.ipfins$r_f13_0_63.ipfins$v_f13_opcode.#define ipfins$q_f13 ipfins$r_f13.ipfins$q_f13"#endif /* #if !defined(__VAXC) */ N/* */I/* F14: Floating-point Check Flags */N/* & */#define IPFINS$M_F14_QP 0x3F%#define IPFINS$M_F14_IMM20A 0x3FFFFC0!#define IPFINS$M_F14_26 0x4000000##define IPFINS$M_F14_X6 0x1F8000000"#define IPFINS$M_F14_X 0x200000000##define IPFINS$M_F14_SF 0xC00000000##define IPFINS$M_F14_S 0x1000000000)#define IPFINS$M_F14_OPCODE 0x1E000000000,#define IPFINS$M_F14_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment& __quadword#else#pragma __nomember_alignment#endiftypedef struct _f14_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_f14_qp : 6;. unsigned ipfins$v_f14_imm20a : 20;) unsigned ipfins$v_f14_26 : 1;) unsigned ipfins$v_f14_x6 : 6;( unsigned ipfins$v_f14_x : 1;) unsigned ipfins$v_f14_sf : 2;& signed ipfins$v_f14_s : 1;- unsigned ipfins$v_f14_opcode : & 4;, unsigned ipfins$v_f14_fill : 23; } ipfins$r_f14_0_63;& unsigned __int64 ipfins$q_f14; } ipfins$r_f14; } F14_FORMAT; #if !defined(__VAXC)F#define ipfins$v_f14_qp ipfins$r_f14.ipfins$r_f14_0_63.ipfins$v_f14_qpN#define ipfins$v_f14_imm20a ipfins$r_f14.ipfins$r_f14_0_63.ipfins$v_f14_imm20aF#define ipfins$v_f14_26 ipfins$r_f14.ipfins$r_f14_0_63.ipfins$v_f14_26F#define ipfins$v_f14_x6 ipfins$r_f14.ipfins$r_f14_0_63.ipfins$v_f14_x6D#define ipfi &ns$v_f14_x ipfins$r_f14.ipfins$r_f14_0_63.ipfins$v_f14_xF#define ipfins$v_f14_sf ipfins$r_f14.ipfins$r_f14_0_63.ipfins$v_f14_sfD#define ipfins$v_f14_s ipfins$r_f14.ipfins$r_f14_0_63.ipfins$v_f14_sN#define ipfins$v_f14_opcode ipfins$r_f14.ipfins$r_f14_0_63.ipfins$v_f14_opcode.#define ipfins$q_f14 ipfins$r_f14.ipfins$q_f14"#endif /* #if !defined(__VAXC) */ N/* */I/* F15: Break (F-Unit) & */N/* */#define IPFINS$M_F15_QP 0x3F%#define IPFINS$M_F15_IMM20A 0x3FFFFC0!#define IPFINS$M_F15_26 0x4000000##define IPFINS$M_F15_X6 0x1F8000000"#define IPFINS$M_F15_X 0x200000000&#define IPFINS$M_F15_34_35 0xC00000000##define IPFINS$M_F15_I 0x1000000000)#define IPFINS$M_F15_OPCODE 0x1E000000000,#define IPFINS$M_F15_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplus&plus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f15_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_f15_qp : 6;. unsigned ipfins$v_f15_imm20a : 20;) unsigned ipfins$v_f15_26 : 1;) unsigned ipfins$v_f15_x6 : 6;( unsigned ipfins$v_f15_x : 1;, unsigned ipfins$v_f15_34_35 : 2;( & unsigned ipfins$v_f15_i : 1;- unsigned ipfins$v_f15_opcode : 4;, unsigned ipfins$v_f15_fill : 23; } ipfins$r_f15_0_63;& unsigned __int64 ipfins$q_f15; } ipfins$r_f15; } F15_FORMAT; #if !defined(__VAXC)F#define ipfins$v_f15_qp ipfins$r_f15.ipfins$r_f15_0_63.ipfins$v_f15_qpN#define ipfins$v_f15_imm20a ipfins$r_f15.ipfins$r_f15_0_63.ipfins$v_f15_imm20aF#define ipfins$v_f15_26 ipfins$r_f15.ipfins$r_f15_0_63.ipfins$v_f15_26F#defin &e ipfins$v_f15_x6 ipfins$r_f15.ipfins$r_f15_0_63.ipfins$v_f15_x6D#define ipfins$v_f15_x ipfins$r_f15.ipfins$r_f15_0_63.ipfins$v_f15_xL#define ipfins$v_f15_34_35 ipfins$r_f15.ipfins$r_f15_0_63.ipfins$v_f15_34_35D#define ipfins$v_f15_i ipfins$r_f15.ipfins$r_f15_0_63.ipfins$v_f15_iN#define ipfins$v_f15_opcode ipfins$r_f15.ipfins$r_f15_0_63.ipfins$v_f15_opcode.#define ipfins$q_f15 ipfins$r_f15.ipfins$q_f15"#endif /* #if !defined(__VAXC) */ N/* & */I/* F16: Nop/Hint (F-Unit) */N/* */#define IPFINS$M_F16_QP 0x3F%#define IPFINS$M_F16_IMM20A 0x3FFFFC0 #define IPFINS$M_F16_Y 0x4000000##define IPFINS$M_F16_X6 0x1F8000000"#define IPFINS$M_F16_X 0x200000000&#define IPFINS$M_F16_34_35 0xC00000000##define IPFINS$M_F16_I 0x1000000000)#define IPFINS$M_F16_OPCODE 0x1E000000000,#define IPFINS$M_F16_FIL&L 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _f16_format {#pragma __nomember_alignment __union { __struct {) unsigned ipfins$v_f16_qp : 6;. unsigned ipfins$v_f16_imm20a : 20;( unsigned ipfins$v_f16_y : 1;) unsigned ipfins$v_f16_x6 : 6;( un &signed ipfins$v_f16_x : 1;, unsigned ipfins$v_f16_34_35 : 2;( unsigned ipfins$v_f16_i : 1;- unsigned ipfins$v_f16_opcode : 4;, unsigned ipfins$v_f16_fill : 23; } ipfins$r_f16_0_63;& unsigned __int64 ipfins$q_f16; } ipfins$r_f16; } F16_FORMAT; #if !defined(__VAXC)F#define ipfins$v_f16_qp ipfins$r_f16.ipfins$r_f16_0_63.ipfins$v_f16_qpN#define ipfins$v_f16_imm20a ipfins$r_f16.ipfins$r_f16_0_63.ipfins$v_f16_imm20a&D#define ipfins$v_f16_y ipfins$r_f16.ipfins$r_f16_0_63.ipfins$v_f16_yF#define ipfins$v_f16_x6 ipfins$r_f16.ipfins$r_f16_0_63.ipfins$v_f16_x6D#define ipfins$v_f16_x ipfins$r_f16.ipfins$r_f16_0_63.ipfins$v_f16_xL#define ipfins$v_f16_34_35 ipfins$r_f16.ipfins$r_f16_0_63.ipfins$v_f16_34_35D#define ipfins$v_f16_i ipfins$r_f16.ipfins$r_f16_0_63.ipfins$v_f16_iN#define ipfins$v_f16_opcode ipfins$r_f16.ipfins$r_f16_0_63.ipfins$v_f16_opcode.#define ipfins$q_f16 ipfins$r_f16.ipfins$q_f16"#endif /* #if ! &defined(__VAXC) */ N/* */I/* X-Unit Formats and Literal Extensions */N/* */N/* */I/* X1: Break (X-Unit) */N/* */#define IP&FINS$M_X1_QP 0x3F$#define IPFINS$M_X1_IMM20A 0x3FFFFC0 #define IPFINS$M_X1_26 0x4000000"#define IPFINS$M_X1_X6 0x1F8000000"#define IPFINS$M_X1_X3 0xE00000000"#define IPFINS$M_X1_I 0x1000000000(#define IPFINS$M_X1_OPCODE 0x1E000000000+#define IPFINS$M_X1_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _x1_forma&t {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_x1_qp : 6;- unsigned ipfins$v_x1_imm20a : 20;( unsigned ipfins$v_x1_26 : 1;( unsigned ipfins$v_x1_x6 : 6;( unsigned ipfins$v_x1_x3 : 3;' unsigned ipfins$v_x1_i : 1;, unsigned ipfins$v_x1_opcode : 4;+ unsigned ipfins$v_x1_fill : 23; } ipfins$r_x1_0_63;% unsigned __int64 ipfins$q_x1; &} ipfins$r_x1; } X1_FORMAT; #if !defined(__VAXC)B#define ipfins$v_x1_qp ipfins$r_x1.ipfins$r_x1_0_63.ipfins$v_x1_qpJ#define ipfins$v_x1_imm20a ipfins$r_x1.ipfins$r_x1_0_63.ipfins$v_x1_imm20aB#define ipfins$v_x1_26 ipfins$r_x1.ipfins$r_x1_0_63.ipfins$v_x1_26B#define ipfins$v_x1_x6 ipfins$r_x1.ipfins$r_x1_0_63.ipfins$v_x1_x6B#define ipfins$v_x1_x3 ipfins$r_x1.ipfins$r_x1_0_63.ipfins$v_x1_x3@#define ipfins$v_x1_i ipfins$r_x1.ipfins$r_x1_0_63.ipfins$v_x1_iJ#define ipfins$v_x1_opcode ipfin &s$r_x1.ipfins$r_x1_0_63.ipfins$v_x1_opcode+#define ipfins$q_x1 ipfins$r_x1.ipfins$q_x1"#endif /* #if !defined(__VAXC) */ N/* */I/* X2: Move Long Immediate(64) */N/* */#define IPFINS$M_X2_QP 0x3F#define IPFINS$M_X2_R1 0x1FC0!#define IPFINS$M_X2_IMM7B 0xFE000#define IPFINS$M_X2_VC 0x100000#define &IPFINS$M_X2_IC 0x200000##define IPFINS$M_X2_IMM5C 0x7C00000%#define IPFINS$M_X2_IMM9D 0xFF8000000"#define IPFINS$M_X2_I 0x1000000000(#define IPFINS$M_X2_OPCODE 0x1E000000000+#define IPFINS$M_X2_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _x2_format {#pragma __nomember_alignment __union { &__struct {( unsigned ipfins$v_x2_qp : 6;( unsigned ipfins$v_x2_r1 : 7;+ unsigned ipfins$v_x2_imm7b : 7;( unsigned ipfins$v_x2_vc : 1;( unsigned ipfins$v_x2_ic : 1;+ unsigned ipfins$v_x2_imm5c : 5;+ unsigned ipfins$v_x2_imm9d : 9;' unsigned ipfins$v_x2_i : 1;, unsigned ipfins$v_x2_opcode : 4;+ unsigned ipfins$v_x2_fill : 23; } ipfins$r_x2_0_63;% unsigned _ &_int64 ipfins$q_x2; } ipfins$r_x2; } X2_FORMAT; #if !defined(__VAXC)B#define ipfins$v_x2_qp ipfins$r_x2.ipfins$r_x2_0_63.ipfins$v_x2_qpB#define ipfins$v_x2_r1 ipfins$r_x2.ipfins$r_x2_0_63.ipfins$v_x2_r1H#define ipfins$v_x2_imm7b ipfins$r_x2.ipfins$r_x2_0_63.ipfins$v_x2_imm7bB#define ipfins$v_x2_vc ipfins$r_x2.ipfins$r_x2_0_63.ipfins$v_x2_vcB#define ipfins$v_x2_ic ipfins$r_x2.ipfins$r_x2_0_63.ipfins$v_x2_icH#define ipfins$v_x2_imm5c ipfins$r_x2.ipfins$r_x2_0_63.ipfins$v_x2_imm &5cH#define ipfins$v_x2_imm9d ipfins$r_x2.ipfins$r_x2_0_63.ipfins$v_x2_imm9d@#define ipfins$v_x2_i ipfins$r_x2.ipfins$r_x2_0_63.ipfins$v_x2_iJ#define ipfins$v_x2_opcode ipfins$r_x2.ipfins$r_x2_0_63.ipfins$v_x2_opcode+#define ipfins$q_x2 ipfins$r_x2.ipfins$q_x2"#endif /* #if !defined(__VAXC) */ N/* */I/* X3: Long Branch */N/* & */#define IPFINS$M_X3_QP 0x3F#define IPFINS$M_X3_BTYPE 0x1C0#define IPFINS$M_X3_9_11 0xE00#define IPFINS$M_X3_P 0x1000&#define IPFINS$M_X3_IMM20B 0x1FFFFE000"#define IPFINS$M_X3_WH 0x600000000!#define IPFINS$M_X3_D 0x800000000"#define IPFINS$M_X3_I 0x1000000000(#define IPFINS$M_X3_OPCODE 0x1E000000000+#define IPFINS$M_X3_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#p&ragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _x3_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_x3_qp : 6;+ unsigned ipfins$v_x3_btype : 3;* unsigned ipfins$v_x3_9_11 : 3;' unsigned ipfins$v_x3_p : 1;- unsigned ipfins$v_x3_imm20b : 20;( unsigned ipfins$v_x3_wh : 2;' unsigned ipfins$v_x3_d : 1;' unsi &gned ipfins$v_x3_i : 1;, unsigned ipfins$v_x3_opcode : 4;+ unsigned ipfins$v_x3_fill : 23; } ipfins$r_x3_0_63;% unsigned __int64 ipfins$q_x3; } ipfins$r_x3; } X3_FORMAT; #if !defined(__VAXC)B#define ipfins$v_x3_qp ipfins$r_x3.ipfins$r_x3_0_63.ipfins$v_x3_qpH#define ipfins$v_x3_btype ipfins$r_x3.ipfins$r_x3_0_63.ipfins$v_x3_btypeF#define ipfins$v_x3_9_11 ipfins$r_x3.ipfins$r_x3_0_63.ipfins$v_x3_9_11@#define ipfins$v_x3_p ipfins$r_x &3.ipfins$r_x3_0_63.ipfins$v_x3_pJ#define ipfins$v_x3_imm20b ipfins$r_x3.ipfins$r_x3_0_63.ipfins$v_x3_imm20bB#define ipfins$v_x3_wh ipfins$r_x3.ipfins$r_x3_0_63.ipfins$v_x3_wh@#define ipfins$v_x3_d ipfins$r_x3.ipfins$r_x3_0_63.ipfins$v_x3_d@#define ipfins$v_x3_i ipfins$r_x3.ipfins$r_x3_0_63.ipfins$v_x3_iJ#define ipfins$v_x3_opcode ipfins$r_x3.ipfins$r_x3_0_63.ipfins$v_x3_opcode+#define ipfins$q_x3 ipfins$r_x3.ipfins$q_x3"#endif /* #if !defined(__VAXC) */ N/* & */I/* X4: Long Call */N/* */#define IPFINS$M_X4_QP 0x3F#define IPFINS$M_X4_B1 0x1C0#define IPFINS$M_X4_9_11 0xE00#define IPFINS$M_X4_P 0x1000&#define IPFINS$M_X4_IMM20B 0x1FFFFE000"#define IPFINS$M_X4_WH 0x600000000!#define IPFINS$M_X4_D 0x800000000"#define IPFINS$M_X4_I 0x1000000000(#define IPFINS$M_X4_OPCODE 0x1E000&000000+#define IPFINS$M_X4_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _x4_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_x4_qp : 6;( unsigned ipfins$v_x4_b1 : 3;* unsigned ipfins$v_x4_9_11 : 3;' unsigned ipfins$v_x4&_p : 1;- unsigned ipfins$v_x4_imm20b : 20;( unsigned ipfins$v_x4_wh : 2;' unsigned ipfins$v_x4_d : 1;' unsigned ipfins$v_x4_i : 1;, unsigned ipfins$v_x4_opcode : 4;+ unsigned ipfins$v_x4_fill : 23; } ipfins$r_x4_0_63;% unsigned __int64 ipfins$q_x4; } ipfins$r_x4; } X4_FORMAT; #if !defined(__VAXC)B#define ipfins$v_x4_qp ipfins$r_x4.ipfins$r_x4_0_63.ipfins$v_x4_qpB#define ipfins$v_x4_&b1 ipfins$r_x4.ipfins$r_x4_0_63.ipfins$v_x4_b1F#define ipfins$v_x4_9_11 ipfins$r_x4.ipfins$r_x4_0_63.ipfins$v_x4_9_11@#define ipfins$v_x4_p ipfins$r_x4.ipfins$r_x4_0_63.ipfins$v_x4_pJ#define ipfins$v_x4_imm20b ipfins$r_x4.ipfins$r_x4_0_63.ipfins$v_x4_imm20bB#define ipfins$v_x4_wh ipfins$r_x4.ipfins$r_x4_0_63.ipfins$v_x4_wh@#define ipfins$v_x4_d ipfins$r_x4.ipfins$r_x4_0_63.ipfins$v_x4_d@#define ipfins$v_x4_i ipfins$r_x4.ipfins$r_x4_0_63.ipfins$v_x4_iJ#define ipfins$v_x4_opcode ipfins$r_x4.ipfin &s$r_x4_0_63.ipfins$v_x4_opcode+#define ipfins$q_x4 ipfins$r_x4.ipfins$q_x4"#endif /* #if !defined(__VAXC) */ N/* */I/* X5: Nop/Hint (X-Unit) */N/* */#define IPFINS$M_X5_QP 0x3F$#define IPFINS$M_X5_IMM20A 0x3FFFFC0#define IPFINS$M_X5_Y 0x4000000"#define IPFINS$M_X5_X6 0x1F8000000"#define IPFINS&$M_X5_X3 0xE00000000"#define IPFINS$M_X5_I 0x1000000000(#define IPFINS$M_X5_OPCODE 0x1E000000000+#define IPFINS$M_X5_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _x5_format {#pragma __nomember_alignment __union { __struct {( unsigned ipfins$v_x5_qp : 6;- unsigned ipfin&s$v_x5_imm20a : 20;' unsigned ipfins$v_x5_y : 1;( unsigned ipfins$v_x5_x6 : 6;( unsigned ipfins$v_x5_x3 : 3;' unsigned ipfins$v_x5_i : 1;, unsigned ipfins$v_x5_opcode : 4;+ unsigned ipfins$v_x5_fill : 23; } ipfins$r_x5_0_63;% unsigned __int64 ipfins$q_x5; } ipfins$r_x5; } X5_FORMAT; #if !defined(__VAXC)B#define ipfins$v_x5_qp ipfins$r_x5.ipfins$r_x5_0_63.ipfins$v_x5_qpJ#define ipfins &$v_x5_imm20a ipfins$r_x5.ipfins$r_x5_0_63.ipfins$v_x5_imm20a@#define ipfins$v_x5_y ipfins$r_x5.ipfins$r_x5_0_63.ipfins$v_x5_yB#define ipfins$v_x5_x6 ipfins$r_x5.ipfins$r_x5_0_63.ipfins$v_x5_x6B#define ipfins$v_x5_x3 ipfins$r_x5.ipfins$r_x5_0_63.ipfins$v_x5_x3@#define ipfins$v_x5_i ipfins$r_x5.ipfins$r_x5_0_63.ipfins$v_x5_iJ#define ipfins$v_x5_opcode ipfins$r_x5.ipfins$r_x5_0_63.ipfins$v_x5_opcode+#define ipfins$q_x5 ipfins$r_x5.ipfins$q_x5"#endif /* #if !defined(__VAXC) */ N/* & */I/* L125: Literal Extensions for X1, X2, X5 */N/* */)#define IPFINS$M_L125_IMM41 0x1FFFFFFFFFF-#define IPFINS$M_L125_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif&typedef struct _l125_format {#pragma __nomember_alignment __union { __struct {#if defined(__VAXC)0 unsigned ipfins$v_l125_imm41_1 : 32;/ unsigned ipfins$v_l125_imm41_2 : 9;#else6 unsigned __int64 ipfins$v_l125_imm41 : 41;#endif- unsigned ipfins$v_l125_fill : 23;! } ipfins$r_l125_0_63;' unsigned __int64 ipfins$q_l125; } ipfins$r_l125; } L125_FORMAT; #if !defined(__VAXC)P#define ipfi &ns$v_l125_imm41 ipfins$r_l125.ipfins$r_l125_0_63.ipfins$v_l125_imm411#define ipfins$q_l125 ipfins$r_l125.ipfins$q_l125"#endif /* #if !defined(__VAXC) */ N/* */I/* L34: Literal Extensions for X3, X4 */N/* */#define IPFINS$M_L34_0_1 0x3(#define IPFINS$M_L34_IMM39 0x1FFFFFFFFFC,#define IPFINS$M_L34_FILL 0xFFFFFE00&00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _l34_format {#pragma __nomember_alignment __union { __struct {* unsigned ipfins$v_l34_0_1 : 2;#if defined(__VAXC)/ unsigned ipfins$v_l34_imm39_1 : 32;. unsigned ipfins$v_l34_imm39_2 : 7;#else5 unsigned __int64 ipf&ins$v_l34_imm39 : 39;#endif, unsigned ipfins$v_l34_fill : 23; } ipfins$r_l34_0_63;& unsigned __int64 ipfins$q_l34; } ipfins$r_l34; } L34_FORMAT; #if !defined(__VAXC)H#define ipfins$v_l34_0_1 ipfins$r_l34.ipfins$r_l34_0_63.ipfins$v_l34_0_1L#define ipfins$v_l34_imm39 ipfins$r_l34.ipfins$r_l34_0_63.ipfins$v_l34_imm39.#define ipfins$q_l34 ipfins$r_l34.ipfins$q_l34"#endif /* #if !defined(__VAXC) */ N/* & */J/* Multi-format overlays - OPnnnx, where n = hex opcode(s) and x = unit */I/* (Intended only for use by [SDA]IPF_DECODE.C). */N/* */N/* */I/* OP8A: A-Unit Opcode 8 - A1-4,A9-10 */N/* */$ &#define IPFINS$M_OP8A_0_26 0x7FFFFFF$#define IPFINS$M_OP8A_X2B 0x18000000$#define IPFINS$M_OP8A_X4 0x1E0000000'#define IPFINS$M_OP8A_VE_ZB 0x200000000%#define IPFINS$M_OP8A_X2A 0xC00000000%#define IPFINS$M_OP8A_ZA 0x1000000000*#define IPFINS$M_OP8A_OPCODE 0x1E000000000-#define IPFINS$M_OP8A_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_ali&gnment#endiftypedef struct _op8a_overlay {#pragma __nomember_alignment __union { __struct {- unsigned ipfins$v_op8a_0_26 : 27;+ unsigned ipfins$v_op8a_x2b : 2;* unsigned ipfins$v_op8a_x4 : 4;- unsigned ipfins$v_op8a_ve_zb : 1;+ unsigned ipfins$v_op8a_x2a : 2;* unsigned ipfins$v_op8a_za : 1;. unsigned ipfins$v_op8a_opcode : 4;- unsigned ipfins$v_op8a_fill : 23;! } ipfi &ns$r_op8a_0_63;' unsigned __int64 ipfins$q_op8a; } ipfins$r_op8a; } OP8A_OVERLAY; #if !defined(__VAXC)N#define ipfins$v_op8a_0_26 ipfins$r_op8a.ipfins$r_op8a_0_63.ipfins$v_op8a_0_26L#define ipfins$v_op8a_x2b ipfins$r_op8a.ipfins$r_op8a_0_63.ipfins$v_op8a_x2bJ#define ipfins$v_op8a_x4 ipfins$r_op8a.ipfins$r_op8a_0_63.ipfins$v_op8a_x4P#define ipfins$v_op8a_ve_zb ipfins$r_op8a.ipfins$r_op8a_0_63.ipfins$v_op8a_ve_zbL#define ipfins$v_op8a_x2a ipfins$r_op8a.ipfins$r_op8a_0_ &63.ipfins$v_op8a_x2aJ#define ipfins$v_op8a_za ipfins$r_op8a.ipfins$r_op8a_0_63.ipfins$v_op8a_zaR#define ipfins$v_op8a_opcode ipfins$r_op8a.ipfins$r_op8a_0_63.ipfins$v_op8a_opcode1#define ipfins$q_op8a ipfins$r_op8a.ipfins$q_op8a"#endif /* #if !defined(__VAXC) */ N/* */I/* OPCDEA: A-Unit Opcodes C,D,E - A6-8 */N/* &*/(#define IPFINS$M_OPCDEA_0_33 0x3FFFFFFFF&#define IPFINS$M_OPCDEA_X2 0xC00000000'#define IPFINS$M_OPCDEA_TB 0x1000000000,#define IPFINS$M_OPCDEA_OPCODE 0x1E000000000/#define IPFINS$M_OPCDEA_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _opcdea_overlay {#pragma __nomember_alignment __union { &__struct {#if defined(__VAXC)1 unsigned ipfins$v_opcdea_0_33_1 : 32;0 unsigned ipfins$v_opcdea_0_33_2 : 2;#else7 unsigned __int64 ipfins$v_opcdea_0_33 : 34;#endif, unsigned ipfins$v_opcdea_x2 : 2;, unsigned ipfins$v_opcdea_tb : 1;0 unsigned ipfins$v_opcdea_opcode : 4;/ unsigned ipfins$v_opcdea_fill : 23;# } ipfins$r_opcdea_0_63;) unsigned __int64 ipfins$q_opcdea; } ipfins$r_o &pcdea; } OPCDEA_OVERLAY; #if !defined(__VAXC)V#define ipfins$v_opcdea_0_33 ipfins$r_opcdea.ipfins$r_opcdea_0_63.ipfins$v_opcdea_0_33R#define ipfins$v_opcdea_x2 ipfins$r_opcdea.ipfins$r_opcdea_0_63.ipfins$v_opcdea_x2R#define ipfins$v_opcdea_tb ipfins$r_opcdea.ipfins$r_opcdea_0_63.ipfins$v_opcdea_tbZ#define ipfins$v_opcdea_opcode ipfins$r_opcdea.ipfins$r_opcdea_0_63.ipfins$v_opcdea_opcode7#define ipfins$q_opcdea ipfins$r_opcdea.ipfins$q_opcdea"#endif /* #if !defined(__VAXC) */ N/* & */I/* OP0I: I-Unit Opcode 0 - I18-29 */N/* */$#define IPFINS$M_OP0I_0_26 0x7FFFFFF$#define IPFINS$M_OP0I_X6 0x1F8000000$#define IPFINS$M_OP0I_X3 0xE00000000%#define IPFINS$M_OP0I_36 0x1000000000*#define IPFINS$M_OP0I_OPCODE 0x1E000000000-#define IPFINS$M_OP0I_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEA&LIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _op0i_overlay {#pragma __nomember_alignment __union { __struct {- unsigned ipfins$v_op0i_0_26 : 27;* unsigned ipfins$v_op0i_x6 : 6;* unsigned ipfins$v_op0i_x3 : 3;* unsigned ipfins$v_op0i_36 : 1;. unsigned ipfins$v_op0i_opcode : 4;- & unsigned ipfins$v_op0i_fill : 23;! } ipfins$r_op0i_0_63;' unsigned __int64 ipfins$q_op0i; } ipfins$r_op0i; } OP0I_OVERLAY; #if !defined(__VAXC)N#define ipfins$v_op0i_0_26 ipfins$r_op0i.ipfins$r_op0i_0_63.ipfins$v_op0i_0_26J#define ipfins$v_op0i_x6 ipfins$r_op0i.ipfins$r_op0i_0_63.ipfins$v_op0i_x6J#define ipfins$v_op0i_x3 ipfins$r_op0i.ipfins$r_op0i_0_63.ipfins$v_op0i_x3J#define ipfins$v_op0i_36 ipfins$r_op0i.ipfins$r_op0i_0_63.ipfins$v_op0i_36R#define &ipfins$v_op0i_opcode ipfins$r_op0i.ipfins$r_op0i_0_63.ipfins$v_op0i_opcode1#define ipfins$q_op0i ipfins$r_op0i.ipfins$q_op0i"#endif /* #if !defined(__VAXC) */ N/* */I/* OP5I: I-Unit Opcode 5 - I10-14,I16-17,I30 */N/* */!#define IPFINS$M_OP5I_0_12 0x1FFF!#define IPFINS$M_OP5I_Y_13 0x2000##define IPFINS$M_OP5I_14_18 0x &7C000"#define IPFINS$M_OP5I_X_19 0x80000%#define IPFINS$M_OP5I_20_25 0x3F00000$#define IPFINS$M_OP5I_Y_26 0x4000000'#define IPFINS$M_OP5I_27_32 0x1F8000000&#define IPFINS$M_OP5I_X_33 0x200000000$#define IPFINS$M_OP5I_X2 0xC00000000%#define IPFINS$M_OP5I_36 0x1000000000*#define IPFINS$M_OP5I_OPCODE 0x1E000000000-#define IPFINS$M_OP5I_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignme&nt __quadword#else#pragma __nomember_alignment#endiftypedef struct _op5i_overlay {#pragma __nomember_alignment __union { __struct {- unsigned ipfins$v_op5i_0_12 : 13;, unsigned ipfins$v_op5i_y_13 : 1;- unsigned ipfins$v_op5i_14_18 : 5;, unsigned ipfins$v_op5i_x_19 : 1;- unsigned ipfins$v_op5i_20_25 : 6;, unsigned ipfins$v_op5i_y_26 : 1;- unsigned ipfins$v_op5i_27_32 : 6;, un &signed ipfins$v_op5i_x_33 : 1;* unsigned ipfins$v_op5i_x2 : 2;* unsigned ipfins$v_op5i_36 : 1;. unsigned ipfins$v_op5i_opcode : 4;- unsigned ipfins$v_op5i_fill : 23;! } ipfins$r_op5i_0_63;' unsigned __int64 ipfins$q_op5i; } ipfins$r_op5i; } OP5I_OVERLAY; #if !defined(__VAXC)N#define ipfins$v_op5i_0_12 ipfins$r_op5i.ipfins$r_op5i_0_63.ipfins$v_op5i_0_12N#define ipfins$v_op5i_y_13 ipfins$r_op5i.ipfins$r_op5i_0_6&3.ipfins$v_op5i_y_13P#define ipfins$v_op5i_14_18 ipfins$r_op5i.ipfins$r_op5i_0_63.ipfins$v_op5i_14_18N#define ipfins$v_op5i_x_19 ipfins$r_op5i.ipfins$r_op5i_0_63.ipfins$v_op5i_x_19P#define ipfins$v_op5i_20_25 ipfins$r_op5i.ipfins$r_op5i_0_63.ipfins$v_op5i_20_25N#define ipfins$v_op5i_y_26 ipfins$r_op5i.ipfins$r_op5i_0_63.ipfins$v_op5i_y_26P#define ipfins$v_op5i_27_32 ipfins$r_op5i.ipfins$r_op5i_0_63.ipfins$v_op5i_27_32N#define ipfins$v_op5i_x_33 ipfins$r_op5i.ipfins$r_op5i_0_63.ipfins$v_op5i_x_33 &J#define ipfins$v_op5i_x2 ipfins$r_op5i.ipfins$r_op5i_0_63.ipfins$v_op5i_x2J#define ipfins$v_op5i_36 ipfins$r_op5i.ipfins$r_op5i_0_63.ipfins$v_op5i_36R#define ipfins$v_op5i_opcode ipfins$r_op5i.ipfins$r_op5i_0_63.ipfins$v_op5i_opcode1#define ipfins$q_op5i ipfins$r_op5i.ipfins$q_op5i"#endif /* #if !defined(__VAXC) */ N/* */I/* OP7I: I-Unit Opcode 7 - I1-9 */N/* & */$#define IPFINS$M_OP7I_0_27 0xFFFFFFF$#define IPFINS$M_OP7I_X2B 0x30000000$#define IPFINS$M_OP7I_X2C 0xC0000000$#define IPFINS$M_OP7I_VE 0x100000000$#define IPFINS$M_OP7I_ZB 0x200000000%#define IPFINS$M_OP7I_X2A 0xC00000000%#define IPFINS$M_OP7I_ZA 0x1000000000*#define IPFINS$M_OP7I_OPCODE 0x1E000000000-#define IPFINS$M_OP7I_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre &DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _op7i_overlay {#pragma __nomember_alignment __union { __struct {- unsigned ipfins$v_op7i_0_27 : 28;+ unsigned ipfins$v_op7i_x2b : 2;+ unsigned ipfins$v_op7i_x2c : 2;* unsigned ipfins$v_op7i_ve : 1;* unsigned ipfins$v_op7i_zb : 1;+ unsigned ipfins$v_op7i_x2a : 2;* unsigned i &pfins$v_op7i_za : 1;. unsigned ipfins$v_op7i_opcode : 4;- unsigned ipfins$v_op7i_fill : 23;! } ipfins$r_op7i_0_63;' unsigned __int64 ipfins$q_op7i; } ipfins$r_op7i; } OP7I_OVERLAY; #if !defined(__VAXC)N#define ipfins$v_op7i_0_27 ipfins$r_op7i.ipfins$r_op7i_0_63.ipfins$v_op7i_0_27L#define ipfins$v_op7i_x2b ipfins$r_op7i.ipfins$r_op7i_0_63.ipfins$v_op7i_x2bL#define ipfins$v_op7i_x2c ipfins$r_op7i.ipfins$r_op7i_0_63.ipfins$v_op7i_x2cJ &#define ipfins$v_op7i_ve ipfins$r_op7i.ipfins$r_op7i_0_63.ipfins$v_op7i_veJ#define ipfins$v_op7i_zb ipfins$r_op7i.ipfins$r_op7i_0_63.ipfins$v_op7i_zbL#define ipfins$v_op7i_x2a ipfins$r_op7i.ipfins$r_op7i_0_63.ipfins$v_op7i_x2aJ#define ipfins$v_op7i_za ipfins$r_op7i.ipfins$r_op7i_0_63.ipfins$v_op7i_zaR#define ipfins$v_op7i_opcode ipfins$r_op7i.ipfins$r_op7i_0_63.ipfins$v_op7i_opcode1#define ipfins$q_op7i ipfins$r_op7i.ipfins$q_op7i"#endif /* #if !defined(__VAXC) */ N/* & */I/* OP0M: M-Unit Opcode 0 - M22-27,M30,M37,M44,M48-50 */N/* */#define IPFINS$M_OP0M_0_9 0x3FF#define IPFINS$M_OP0M_Z 0xC00%#define IPFINS$M_OP0M_12_25 0x3FFF000!#define IPFINS$M_OP0M_Y 0x4000000##define IPFINS$M_OP0M_X4 0x78000000$#define IPFINS$M_OP0M_X2 0x180000000$#define IPFINS$M_OP0M_X3 0xE00000000%#define IPFINS$M_OP0M_36 0x1000000000&*#define IPFINS$M_OP0M_OPCODE 0x1E000000000-#define IPFINS$M_OP0M_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _op0m_overlay {#pragma __nomember_alignment __union { __struct {, unsigned ipfins$v_op0m_0_9 : 10;) unsigned ipfins$v_op0m_z : 2;. unsigned ipfins$&v_op0m_12_25 : 14;) unsigned ipfins$v_op0m_y : 1;* unsigned ipfins$v_op0m_x4 : 4;* unsigned ipfins$v_op0m_x2 : 2;* unsigned ipfins$v_op0m_x3 : 3;* unsigned ipfins$v_op0m_36 : 1;. unsigned ipfins$v_op0m_opcode : 4;- unsigned ipfins$v_op0m_fill : 23;! } ipfins$r_op0m_0_63;' unsigned __int64 ipfins$q_op0m; } ipfins$r_op0m; } OP0M_OVERLAY; #if !defined(__VAXC)L#define ipfins$v_o&p0m_0_9 ipfins$r_op0m.ipfins$r_op0m_0_63.ipfins$v_op0m_0_9H#define ipfins$v_op0m_z ipfins$r_op0m.ipfins$r_op0m_0_63.ipfins$v_op0m_zP#define ipfins$v_op0m_12_25 ipfins$r_op0m.ipfins$r_op0m_0_63.ipfins$v_op0m_12_25H#define ipfins$v_op0m_y ipfins$r_op0m.ipfins$r_op0m_0_63.ipfins$v_op0m_yJ#define ipfins$v_op0m_x4 ipfins$r_op0m.ipfins$r_op0m_0_63.ipfins$v_op0m_x4J#define ipfins$v_op0m_x2 ipfins$r_op0m.ipfins$r_op0m_0_63.ipfins$v_op0m_x2J#define ipfins$v_op0m_x3 ipfins$r_op0m.ipfins$r_op0m_0_63.ipfins &$v_op0m_x3J#define ipfins$v_op0m_36 ipfins$r_op0m.ipfins$r_op0m_0_63.ipfins$v_op0m_36R#define ipfins$v_op0m_opcode ipfins$r_op0m.ipfins$r_op0m_0_63.ipfins$v_op0m_opcode1#define ipfins$q_op0m ipfins$r_op0m.ipfins$q_op0m"#endif /* #if !defined(__VAXC) */ N/* */I/* OP1M: M-Unit Opcode 1 - M20-21,M28-29,M31-36,M38-43,M45-47 */N/* */$#defin&e IPFINS$M_OP1M_0_26 0x7FFFFFF$#define IPFINS$M_OP1M_X6 0x1F8000000$#define IPFINS$M_OP1M_X3 0xE00000000%#define IPFINS$M_OP1M_36 0x1000000000*#define IPFINS$M_OP1M_OPCODE 0x1E000000000-#define IPFINS$M_OP1M_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _op1m_overlay {#pragma __nomember_alignment __unio&n { __struct {- unsigned ipfins$v_op1m_0_26 : 27;* unsigned ipfins$v_op1m_x6 : 6;* unsigned ipfins$v_op1m_x3 : 3;* unsigned ipfins$v_op1m_36 : 1;. unsigned ipfins$v_op1m_opcode : 4;- unsigned ipfins$v_op1m_fill : 23;! } ipfins$r_op1m_0_63;' unsigned __int64 ipfins$q_op1m; } ipfins$r_op1m; } OP1M_OVERLAY; #if !defined(__VAXC)N#define ipfins$v_op1m_0_26 ipfins$r_op1m.ipfins$r_ &op1m_0_63.ipfins$v_op1m_0_26J#define ipfins$v_op1m_x6 ipfins$r_op1m.ipfins$r_op1m_0_63.ipfins$v_op1m_x6J#define ipfins$v_op1m_x3 ipfins$r_op1m.ipfins$r_op1m_0_63.ipfins$v_op1m_x3J#define ipfins$v_op1m_36 ipfins$r_op1m.ipfins$r_op1m_0_63.ipfins$v_op1m_36R#define ipfins$v_op1m_opcode ipfins$r_op1m.ipfins$r_op1m_0_63.ipfins$v_op1m_opcode1#define ipfins$q_op1m ipfins$r_op1m.ipfins$q_op1m"#endif /* #if !defined(__VAXC) */ N/* & */I/* OP4M: M-Unit Opcode 4 - M1-2,M4,M16-17,M19 */N/* */$#define IPFINS$M_OP4M_0_26 0x7FFFFFF!#define IPFINS$M_OP4M_X 0x8000000&#define IPFINS$M_OP4M_28_29 0x30000000$#define IPFINS$M_OP4M_X6 0xFC0000000$#define IPFINS$M_OP4M_M 0x1000000000*#define IPFINS$M_OP4M_OPCODE 0x1E000000000-#define IPFINS$M_OP4M_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplus&plus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _op4m_overlay {#pragma __nomember_alignment __union { __struct {- unsigned ipfins$v_op4m_0_26 : 27;) unsigned ipfins$v_op4m_x : 1;- unsigned ipfins$v_op4m_28_29 : 2;* unsigned ipfins$v_op4m_x6 : 6;) unsigned ipfins$v_op4m_m : 1;. unsigned ipfins$v_op4m_opcode : &4;- unsigned ipfins$v_op4m_fill : 23;! } ipfins$r_op4m_0_63;' unsigned __int64 ipfins$q_op4m; } ipfins$r_op4m; } OP4M_OVERLAY; #if !defined(__VAXC)N#define ipfins$v_op4m_0_26 ipfins$r_op4m.ipfins$r_op4m_0_63.ipfins$v_op4m_0_26H#define ipfins$v_op4m_x ipfins$r_op4m.ipfins$r_op4m_0_63.ipfins$v_op4m_xP#define ipfins$v_op4m_28_29 ipfins$r_op4m.ipfins$r_op4m_0_63.ipfins$v_op4m_28_29J#define ipfins$v_op4m_x6 ipfins$r_op4m.ipfins$r_op4m_0_63.ipfins$v &_op4m_x6H#define ipfins$v_op4m_m ipfins$r_op4m.ipfins$r_op4m_0_63.ipfins$v_op4m_mR#define ipfins$v_op4m_opcode ipfins$r_op4m.ipfins$r_op4m_0_63.ipfins$v_op4m_opcode1#define ipfins$q_op4m ipfins$r_op4m.ipfins$q_op4m"#endif /* #if !defined(__VAXC) */ N/* */I/* OP5M: M-Unit Opcode 5 - M3,M5 */N/* */%#define IP&FINS$M_OP5M_0_29 0x3FFFFFFF$#define IPFINS$M_OP5M_X6 0xFC0000000%#define IPFINS$M_OP5M_36 0x1000000000*#define IPFINS$M_OP5M_OPCODE 0x1E000000000-#define IPFINS$M_OP5M_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _op5m_overlay {#pragma __nomember_alignment __union { __struct {- &unsigned ipfins$v_op5m_0_29 : 30;* unsigned ipfins$v_op5m_x6 : 6;* unsigned ipfins$v_op5m_36 : 1;. unsigned ipfins$v_op5m_opcode : 4;- unsigned ipfins$v_op5m_fill : 23;! } ipfins$r_op5m_0_63;' unsigned __int64 ipfins$q_op5m; } ipfins$r_op5m; } OP5M_OVERLAY; #if !defined(__VAXC)N#define ipfins$v_op5m_0_29 ipfins$r_op5m.ipfins$r_op5m_0_63.ipfins$v_op5m_0_29J#define ipfins$v_op5m_x6 ipfins$r_op5m.ipfins$r_op5m_0 &_63.ipfins$v_op5m_x6J#define ipfins$v_op5m_36 ipfins$r_op5m.ipfins$r_op5m_0_63.ipfins$v_op5m_36R#define ipfins$v_op5m_opcode ipfins$r_op5m.ipfins$r_op5m_0_63.ipfins$v_op5m_opcode1#define ipfins$q_op5m ipfins$r_op5m.ipfins$q_op5m"#endif /* #if !defined(__VAXC) */ N/* */I/* OP6M: M-Unit Opcode 6 - M6-7,M9,M11-14,M18,M51-52 */N/* &*/"#define IPFINS$M_OP6M_0_18 0x7FFFF#define IPFINS$M_OP6M_Y 0x80000%#define IPFINS$M_OP6M_20_26 0x7F00000!#define IPFINS$M_OP6M_X 0x8000000&#define IPFINS$M_OP6M_28_29 0x30000000$#define IPFINS$M_OP6M_X6 0xFC0000000$#define IPFINS$M_OP6M_M 0x1000000000*#define IPFINS$M_OP6M_OPCODE 0x1E000000000-#define IPFINS$M_OP6M_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword&#else#pragma __nomember_alignment#endiftypedef struct _op6m_overlay {#pragma __nomember_alignment __union { __struct {- unsigned ipfins$v_op6m_0_18 : 19;) unsigned ipfins$v_op6m_y : 1;- unsigned ipfins$v_op6m_20_26 : 7;) unsigned ipfins$v_op6m_x : 1;- unsigned ipfins$v_op6m_28_29 : 2;* unsigned ipfins$v_op6m_x6 : 6;) unsigned ipfins$v_op6m_m : 1;. unsigned ipfins$v_op6m_opcod &e : 4;- unsigned ipfins$v_op6m_fill : 23;! } ipfins$r_op6m_0_63;' unsigned __int64 ipfins$q_op6m; } ipfins$r_op6m; } OP6M_OVERLAY; #if !defined(__VAXC)N#define ipfins$v_op6m_0_18 ipfins$r_op6m.ipfins$r_op6m_0_63.ipfins$v_op6m_0_18H#define ipfins$v_op6m_y ipfins$r_op6m.ipfins$r_op6m_0_63.ipfins$v_op6m_yP#define ipfins$v_op6m_20_26 ipfins$r_op6m.ipfins$r_op6m_0_63.ipfins$v_op6m_20_26H#define ipfins$v_op6m_x ipfins$r_op6m.ipfins$r_op6m_0_63.ipfin &s$v_op6m_xP#define ipfins$v_op6m_28_29 ipfins$r_op6m.ipfins$r_op6m_0_63.ipfins$v_op6m_28_29J#define ipfins$v_op6m_x6 ipfins$r_op6m.ipfins$r_op6m_0_63.ipfins$v_op6m_x6H#define ipfins$v_op6m_m ipfins$r_op6m.ipfins$r_op6m_0_63.ipfins$v_op6m_mR#define ipfins$v_op6m_opcode ipfins$r_op6m.ipfins$r_op6m_0_63.ipfins$v_op6m_opcode1#define ipfins$q_op6m ipfins$r_op6m.ipfins$q_op6m"#endif /* #if !defined(__VAXC) */ N/* */I/* OP7 &M: M-Unit Opcode 7 - M8,M10,M15 */N/* */%#define IPFINS$M_OP7M_0_29 0x3FFFFFFF$#define IPFINS$M_OP7M_X6 0xFC0000000%#define IPFINS$M_OP7M_36 0x1000000000*#define IPFINS$M_OP7M_OPCODE 0x1E000000000-#define IPFINS$M_OP7M_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword&#else#pragma __nomember_alignment#endiftypedef struct _op7m_overlay {#pragma __nomember_alignment __union { __struct {- unsigned ipfins$v_op7m_0_29 : 30;* unsigned ipfins$v_op7m_x6 : 6;* unsigned ipfins$v_op7m_36 : 1;. unsigned ipfins$v_op7m_opcode : 4;- unsigned ipfins$v_op7m_fill : 23;! } ipfins$r_op7m_0_63;' unsigned __int64 ipfins$q_op7m; } ipfins$r_op7m; } OP7M_OVERLAY; & #if !defined(__VAXC)N#define ipfins$v_op7m_0_29 ipfins$r_op7m.ipfins$r_op7m_0_63.ipfins$v_op7m_0_29J#define ipfins$v_op7m_x6 ipfins$r_op7m.ipfins$r_op7m_0_63.ipfins$v_op7m_x6J#define ipfins$v_op7m_36 ipfins$r_op7m.ipfins$r_op7m_0_63.ipfins$v_op7m_36R#define ipfins$v_op7m_opcode ipfins$r_op7m.ipfins$r_op7m_0_63.ipfins$v_op7m_opcode1#define ipfins$q_op7m ipfins$r_op7m.ipfins$q_op7m"#endif /* #if !defined(__VAXC) */ N/* & */I/* OP02B: B-Unit Opcode 0,2 - B4,B7-9 */N/* */#define IPFINS$M_OP02B_0_5 0x3F"#define IPFINS$M_OP02B_BTYPE 0x1C0%#define IPFINS$M_OP02B_9_26 0x7FFFE00%#define IPFINS$M_OP02B_X6 0x1F8000000)#define IPFINS$M_OP02B_33_36 0x1E00000000+#define IPFINS$M_OP02B_OPCODE 0x1E000000000.#define IPFINS$M_OP02B_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(_&_cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _op02b_overlay {#pragma __nomember_alignment __union { __struct {, unsigned ipfins$v_op02b_0_5 : 6;. unsigned ipfins$v_op02b_btype : 3;. unsigned ipfins$v_op02b_9_26 : 18;+ unsigned ipfins$v_op02b_x6 : 6;. unsigned ipfins$v_op02b_33_36 : 4;/ unsigned ipfins$ &v_op02b_opcode : 4;. unsigned ipfins$v_op02b_fill : 23;" } ipfins$r_op02b_0_63;( unsigned __int64 ipfins$q_op02b; } ipfins$r_op02b; } OP02B_OVERLAY; #if !defined(__VAXC)P#define ipfins$v_op02b_0_5 ipfins$r_op02b.ipfins$r_op02b_0_63.ipfins$v_op02b_0_5T#define ipfins$v_op02b_btype ipfins$r_op02b.ipfins$r_op02b_0_63.ipfins$v_op02b_btypeR#define ipfins$v_op02b_9_26 ipfins$r_op02b.ipfins$r_op02b_0_63.ipfins$v_op02b_9_26N#define ipfins$v_op02b_x6 ipfi &ns$r_op02b.ipfins$r_op02b_0_63.ipfins$v_op02b_x6T#define ipfins$v_op02b_33_36 ipfins$r_op02b.ipfins$r_op02b_0_63.ipfins$v_op02b_33_36V#define ipfins$v_op02b_opcode ipfins$r_op02b.ipfins$r_op02b_0_63.ipfins$v_op02b_opcode4#define ipfins$q_op02b ipfins$r_op02b.ipfins$q_op02b"#endif /* #if !defined(__VAXC) */ N/* */I/* OP4B: B-Unit Opcode 4 - B1-2 */N/* & */#define IPFINS$M_OP4B_0_5 0x3F!#define IPFINS$M_OP4B_BTYPE 0x1C0'#define IPFINS$M_OP4B_9_36 0x1FFFFFFE00*#define IPFINS$M_OP4B_OPCODE 0x1E000000000-#define IPFINS$M_OP4B_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _op4b_overlay {#pragma __nomember_alignment& __union { __struct {+ unsigned ipfins$v_op4b_0_5 : 6;- unsigned ipfins$v_op4b_btype : 3;- unsigned ipfins$v_op4b_9_36 : 28;. unsigned ipfins$v_op4b_opcode : 4;- unsigned ipfins$v_op4b_fill : 23;! } ipfins$r_op4b_0_63;' unsigned __int64 ipfins$q_op4b; } ipfins$r_op4b; } OP4B_OVERLAY; #if !defined(__VAXC)L#define ipfins$v_op4b_0_5 ipfins$r_op4b.ipfins$r_op4b_0_63.ipfins$v_op4b_0_5P &#define ipfins$v_op4b_btype ipfins$r_op4b.ipfins$r_op4b_0_63.ipfins$v_op4b_btypeN#define ipfins$v_op4b_9_36 ipfins$r_op4b.ipfins$r_op4b_0_63.ipfins$v_op4b_9_36R#define ipfins$v_op4b_opcode ipfins$r_op4b.ipfins$r_op4b_0_63.ipfins$v_op4b_opcode1#define ipfins$q_op4b ipfins$r_op4b.ipfins$q_op4b"#endif /* #if !defined(__VAXC) */ N/* */I/* OP7B: B-Unit Opcode 7 - B6,B10 */N/* & */#define IPFINS$M_OP7B_0_2 0x7#define IPFINS$M_OP7B_X2 0x18'#define IPFINS$M_OP7B_5_36 0x1FFFFFFFE0*#define IPFINS$M_OP7B_OPCODE 0x1E000000000-#define IPFINS$M_OP7B_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _op7b_overlay {#pragma __nome&mber_alignment __union { __struct {+ unsigned ipfins$v_op7b_0_2 : 3;* unsigned ipfins$v_op7b_x2 : 2;- unsigned ipfins$v_op7b_5_36 : 32;. unsigned ipfins$v_op7b_opcode : 4;- unsigned ipfins$v_op7b_fill : 23;! } ipfins$r_op7b_0_63;' unsigned __int64 ipfins$q_op7b; } ipfins$r_op7b; } OP7B_OVERLAY; #if !defined(__VAXC)L#define ipfins$v_op7b_0_2 ipfins$r_op7b.ipfins$r_op7b_0_63.ipfins$ &v_op7b_0_2J#define ipfins$v_op7b_x2 ipfins$r_op7b.ipfins$r_op7b_0_63.ipfins$v_op7b_x2N#define ipfins$v_op7b_5_36 ipfins$r_op7b.ipfins$r_op7b_0_63.ipfins$v_op7b_5_36R#define ipfins$v_op7b_opcode ipfins$r_op7b.ipfins$r_op7b_0_63.ipfins$v_op7b_opcode1#define ipfins$q_op7b ipfins$r_op7b.ipfins$q_op7b"#endif /* #if !defined(__VAXC) */ N/* */I/* OP01F: F-Unit Opcodes 0,1 - F6-16 */N/* & */%#define IPFINS$M_OP01F_0_26 0x7FFFFFF%#define IPFINS$M_OP01F_X6 0x1F8000000$#define IPFINS$M_OP01F_X 0x200000000(#define IPFINS$M_OP01F_34_35 0xC00000000%#define IPFINS$M_OP01F_Q 0x1000000000+#define IPFINS$M_OP01F_OPCODE 0x1E000000000.#define IPFINS$M_OP01F_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __q&uadword#else#pragma __nomember_alignment#endiftypedef struct _op01f_overlay {#pragma __nomember_alignment __union { __struct {. unsigned ipfins$v_op01f_0_26 : 27;+ unsigned ipfins$v_op01f_x6 : 6;* unsigned ipfins$v_op01f_x : 1;. unsigned ipfins$v_op01f_34_35 : 2;* unsigned ipfins$v_op01f_q : 1;/ unsigned ipfins$v_op01f_opcode : 4;. unsigned ipfins$v_op01f_fill : 23;" } ipfins &$r_op01f_0_63;( unsigned __int64 ipfins$q_op01f; } ipfins$r_op01f; } OP01F_OVERLAY; #if !defined(__VAXC)R#define ipfins$v_op01f_0_26 ipfins$r_op01f.ipfins$r_op01f_0_63.ipfins$v_op01f_0_26N#define ipfins$v_op01f_x6 ipfins$r_op01f.ipfins$r_op01f_0_63.ipfins$v_op01f_x6L#define ipfins$v_op01f_x ipfins$r_op01f.ipfins$r_op01f_0_63.ipfins$v_op01f_xT#define ipfins$v_op01f_34_35 ipfins$r_op01f.ipfins$r_op01f_0_63.ipfins$v_op01f_34_35L#define ipfins$v_op01f_q ipfins$r_op01f.ipfi &ns$r_op01f_0_63.ipfins$v_op01f_qV#define ipfins$v_op01f_opcode ipfins$r_op01f.ipfins$r_op01f_0_63.ipfins$v_op01f_opcode4#define ipfins$q_op01f ipfins$r_op01f.ipfins$q_op01f"#endif /* #if !defined(__VAXC) */ N/* */I/* OPEF: F-Unit Opcode E - F2-3 */N/* */&#define IPFINS$M_OPEF_0_33 0x3FFFFFFFF$#define IPFINS&$M_OPEF_X2 0xC00000000$#define IPFINS$M_OPEF_X 0x1000000000*#define IPFINS$M_OPEF_OPCODE 0x1E000000000-#define IPFINS$M_OPEF_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _opef_overlay {#pragma __nomember_alignment __union { __struct {#if defined(__VAXC)/ unsigned ipfins$v_opef_0&_33_1 : 32;. unsigned ipfins$v_opef_0_33_2 : 2;#else5 unsigned __int64 ipfins$v_opef_0_33 : 34;#endif* unsigned ipfins$v_opef_x2 : 2;) unsigned ipfins$v_opef_x : 1;. unsigned ipfins$v_opef_opcode : 4;- unsigned ipfins$v_opef_fill : 23;! } ipfins$r_opef_0_63;' unsigned __int64 ipfins$q_opef; } ipfins$r_opef; } OPEF_OVERLAY; #if !defined(__VAXC)N#define ipfins$v_opef_0_33 ipfins$r_ &opef.ipfins$r_opef_0_63.ipfins$v_opef_0_33J#define ipfins$v_opef_x2 ipfins$r_opef.ipfins$r_opef_0_63.ipfins$v_opef_x2H#define ipfins$v_opef_x ipfins$r_opef.ipfins$r_opef_0_63.ipfins$v_opef_xR#define ipfins$v_opef_opcode ipfins$r_opef.ipfins$r_opef_0_63.ipfins$v_opef_opcode1#define ipfins$q_opef ipfins$r_opef.ipfins$q_opef"#endif /* #if !defined(__VAXC) */ N/* */I/* OP0X: X-Unit Opcode 0 - X1 & */N/* */$#define IPFINS$M_OP0X_0_26 0x7FFFFFF$#define IPFINS$M_OP0X_X6 0x1F8000000$#define IPFINS$M_OP0X_X3 0xE00000000%#define IPFINS$M_OP0X_36 0x1000000000*#define IPFINS$M_OP0X_OPCODE 0x1E000000000-#define IPFINS$M_OP0X_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pra&gma __nomember_alignment#endiftypedef struct _op0x_overlay {#pragma __nomember_alignment __union { __struct {- unsigned ipfins$v_op0x_0_26 : 27;* unsigned ipfins$v_op0x_x6 : 6;* unsigned ipfins$v_op0x_x3 : 3;* unsigned ipfins$v_op0x_36 : 1;. unsigned ipfins$v_op0x_opcode : 4;- unsigned ipfins$v_op0x_fill : 23;! } ipfins$r_op0x_0_63;' unsigned __int64 ipfins$q_op0x; } ipfins$r &_op0x; } OP0X_OVERLAY; #if !defined(__VAXC)N#define ipfins$v_op0x_0_26 ipfins$r_op0x.ipfins$r_op0x_0_63.ipfins$v_op0x_0_26J#define ipfins$v_op0x_x6 ipfins$r_op0x.ipfins$r_op0x_0_63.ipfins$v_op0x_x6J#define ipfins$v_op0x_x3 ipfins$r_op0x.ipfins$r_op0x_0_63.ipfins$v_op0x_x3J#define ipfins$v_op0x_36 ipfins$r_op0x.ipfins$r_op0x_0_63.ipfins$v_op0x_36R#define ipfins$v_op0x_opcode ipfins$r_op0x.ipfins$r_op0x_0_63.ipfins$v_op0x_opcode1#define ipfins$q_op0x ipfins$r_op0x.ipfins$q_op0x"#endif & /* #if !defined(__VAXC) */ N/* */I/* OP6X: X-Unit Opcode 6 - X2 */N/* */"#define IPFINS$M_OP6X_0_19 0xFFFFF!#define IPFINS$M_OP6X_VC 0x100000(#define IPFINS$M_OP6X_21_36 0x1FFFE00000*#define IPFINS$M_OP6X_OPCODE 0x1E000000000-#define IPFINS$M_OP6X_FILL 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN&_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _op6x_overlay {#pragma __nomember_alignment __union { __struct {- unsigned ipfins$v_op6x_0_19 : 20;* unsigned ipfins$v_op6x_vc : 1;. unsigned ipfins$v_op6x_21_36 : 16;. unsigned ipfins$v_op6x_opcode : 4;- unsigned ipfins$v_op6x_fill : 23;! & } ipfins$r_op6x_0_63;' unsigned __int64 ipfins$q_op6x; } ipfins$r_op6x; } OP6X_OVERLAY; #if !defined(__VAXC)N#define ipfins$v_op6x_0_19 ipfins$r_op6x.ipfins$r_op6x_0_63.ipfins$v_op6x_0_19J#define ipfins$v_op6x_vc ipfins$r_op6x.ipfins$r_op6x_0_63.ipfins$v_op6x_vcP#define ipfins$v_op6x_21_36 ipfins$r_op6x.ipfins$r_op6x_0_63.ipfins$v_op6x_21_36R#define ipfins$v_op6x_opcode ipfins$r_op6x.ipfins$r_op6x_0_63.ipfins$v_op6x_opcode1#define ipfins$q_op6x ipfins$r_op6x.ip &fins$q_op6x"#endif /* #if !defined(__VAXC) */ N/* */I/* OPCX: X-Unit Opcode C - X3 */N/* */#define IPFINS$M_OPCX_0_5 0x3F!#define IPFINS$M_OPCX_BTYPE 0x1C0'#define IPFINS$M_OPCX_9_36 0x1FFFFFFE00*#define IPFINS$M_OPCX_OPCODE 0x1E000000000-#define IPFINS$M_OPCX_FILL 0xFFFFFE0000000000 c#if !defin&ed(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _opcx_overlay {#pragma __nomember_alignment __union { __struct {+ unsigned ipfins$v_opcx_0_5 : 6;- unsigned ipfins$v_opcx_btype : 3;- unsigned ipfins$v_opcx_9_36 : 28;. unsigned ipfins$v_opcx_opcode : 4;- unsigned ipfins$v_opcx_f 'ill : 23;! } ipfins$r_opcx_0_63;' unsigned __int64 ipfins$q_opcx; } ipfins$r_opcx; } OPCX_OVERLAY; #if !defined(__VAXC)L#define ipfins$v_opcx_0_5 ipfins$r_opcx.ipfins$r_opcx_0_63.ipfins$v_opcx_0_5P#define ipfins$v_opcx_btype ipfins$r_opcx.ipfins$r_opcx_0_63.ipfins$v_opcx_btypeN#define ipfins$v_opcx_9_36 ipfins$r_opcx.ipfins$r_opcx_0_63.ipfins$v_opcx_9_36R#define ipfins$v_opcx_opcode ipfins$r_opcx.ipfins$r_opcx_0_63.ipfins$v_opcx_opcode1#define ipfins$q_o 'pcx ipfins$r_opcx.ipfins$q_opcx"#endif /* #if !defined(__VAXC) */ N/* */I/* Memory format: union of all M-Unit formats */I/* (not all formats yet included, just sufficient for */I/* fault handling) plus opcode values */N/* */#define IPFINS$M_MEM_QP 0x3F#define IPFINS'$M_MEM_R1 0x1FC0#define IPFINS$M_MEM_R2 0xFE000!#define IPFINS$M_MEM_R3 0x7F00000 #define IPFINS$M_MEM_X 0x8000000$#define IPFINS$M_MEM_HINT 0x30000000##define IPFINS$M_MEM_X6 0xFC0000000##define IPFINS$M_MEM_M 0x1000000000)#define IPFINS$M_MEM_OPCODE 0x1E000000000-#define IPFINS$M_MEM_FILL1 0xFFFFFE0000000000 #define IPFINS$M_MEM_FILL10 0x3F#define IPFINS$M_MEM_F1 0x1FC0#define IPFINS$M_MEM_F2 0xFE000%#define IPFINS$M_MEM_FILL11 0x7F00000 #define IPFINS$M_MEM_I 0x8000000&#def 'ine IPFINS$M_MEM_FILL12 0x30000000'#define IPFINS$M_MEM_FILL13 0xFC0000000##define IPFINS$M_MEM_S 0x1000000000)#define IPFINS$M_MEM_FILL14 0x1E000000000.#define IPFINS$M_MEM_FILL15 0xFFFFFE0000000000 #define IPFINS$M_MEM_FILL20 0x3F!#define IPFINS$M_MEM_IMM7A 0x1FC0"#define IPFINS$M_MEM_IMM7B 0xFE000%#define IPFINS$M_MEM_FILL21 0x7F00000%#define IPFINS$M_MEM_FILL22 0x8000000&#define IPFINS$M_MEM_FILL23 0x30000000'#define IPFINS$M_MEM_FILL24 0xFC0000000(#define IPFINS$M_MEM_FILL25 0x'1000000000)#define IPFINS$M_MEM_FILL26 0x1E000000000.#define IPFINS$M_MEM_FILL27 0xFFFFFE0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mem_format {#pragma __nomember_alignment __union {& unsigned __int64 ipfins$q_mem; __struct {) unsigned ipfins$v_mem_qp : 6;) unsigned ipfin 's$v_mem_r1 : 7;) unsigned ipfins$v_mem_r2 : 7;) unsigned ipfins$v_mem_r3 : 7;( unsigned ipfins$v_mem_x : 1;+ unsigned ipfins$v_mem_hint : 2;) unsigned ipfins$v_mem_x6 : 6;( unsigned ipfins$v_mem_m : 1;- unsigned ipfins$v_mem_opcode : 4;- unsigned ipfins$v_mem_fill1 : 23; } ipfins$r_mem_0; __struct {- unsigned ipfins$v_mem_fill10 : 6;) unsigned ipfins$ 'v_mem_f1 : 7;) unsigned ipfins$v_mem_f2 : 7;- unsigned ipfins$v_mem_fill11 : 7;( unsigned ipfins$v_mem_i : 1;- unsigned ipfins$v_mem_fill12 : 2;- unsigned ipfins$v_mem_fill13 : 6;( unsigned ipfins$v_mem_s : 1;- unsigned ipfins$v_mem_fill14 : 4;. unsigned ipfins$v_mem_fill15 : 23; } ipfins$r_mem_1; __struct {- unsigned ipfins$v_mem_fill20 : 6;, unsigned' ipfins$v_mem_imm7a : 7;, unsigned ipfins$v_mem_imm7b : 7;- unsigned ipfins$v_mem_fill21 : 7;- unsigned ipfins$v_mem_fill22 : 1;- unsigned ipfins$v_mem_fill23 : 2;- unsigned ipfins$v_mem_fill24 : 6;- unsigned ipfins$v_mem_fill25 : 1;- unsigned ipfins$v_mem_fill26 : 4;. unsigned ipfins$v_mem_fill27 : 23; } ipfins$r_mem_2; } ipfins$r_mem; } MEM_FORMAT; #if !defined(__V 'AXC).#define ipfins$q_mem ipfins$r_mem.ipfins$q_memC#define ipfins$v_mem_qp ipfins$r_mem.ipfins$r_mem_0.ipfins$v_mem_qpC#define ipfins$v_mem_r1 ipfins$r_mem.ipfins$r_mem_0.ipfins$v_mem_r1C#define ipfins$v_mem_r2 ipfins$r_mem.ipfins$r_mem_0.ipfins$v_mem_r2C#define ipfins$v_mem_r3 ipfins$r_mem.ipfins$r_mem_0.ipfins$v_mem_r3A#define ipfins$v_mem_x ipfins$r_mem.ipfins$r_mem_0.ipfins$v_mem_xG#define ipfins$v_mem_hint ipfins$r_mem.ipfins$r_mem_0.ipfins$v_mem_hintC#define ipfins$v_mem_x6 ipfins '$r_mem.ipfins$r_mem_0.ipfins$v_mem_x6A#define ipfins$v_mem_m ipfins$r_mem.ipfins$r_mem_0.ipfins$v_mem_mK#define ipfins$v_mem_opcode ipfins$r_mem.ipfins$r_mem_0.ipfins$v_mem_opcodeC#define ipfins$v_mem_f1 ipfins$r_mem.ipfins$r_mem_1.ipfins$v_mem_f1C#define ipfins$v_mem_f2 ipfins$r_mem.ipfins$r_mem_1.ipfins$v_mem_f2A#define ipfins$v_mem_i ipfins$r_mem.ipfins$r_mem_1.ipfins$v_mem_iI#define ipfins$v_mem_imm7a ipfins$r_mem.ipfins$r_mem_2.ipfins$v_mem_imm7aI#define ipfins$v_mem_imm7b ipfins$r_ 'mem.ipfins$r_mem_2.ipfins$v_mem_imm7b"#endif /* #if !defined(__VAXC) */ #define IPFINS$C_MEM_LD 256#define IPFINS$C_MEM_LDS 257#define IPFINS$C_MEM_LDA 258#define IPFINS$C_MEM_LDSA 259#define IPFINS$C_MEM_LDBIAS 260#define IPFINS$C_MEM_LDACQ 261#define IPFINS$C_MEM_LDCCLR 264#define IPFINS$C_MEM_LDCNC 265"#define IPFINS$C_MEM_LDCCLRACQ 266#define IPFINS$C_MEM_ST 268#define IPFINS$C_MEM_STREL 269#define IPFINS$C_MEM_LD_IMM 320 #define IPFINS$C_MEM_LDS_IMM 321 #defin 'e IPFINS$C_MEM_LDA_IMM 322!#define IPFINS$C_MEM_LDSA_IMM 323##define IPFINS$C_MEM_LDBIAS_IMM 324"#define IPFINS$C_MEM_LDACQ_IMM 325##define IPFINS$C_MEM_LDCCLR_IMM 328"#define IPFINS$C_MEM_LDCNC_IMM 329&#define IPFINS$C_MEM_LDCCLRACQ_IMM 330#define IPFINS$C_MEM_ST_IMM 332"#define IPFINS$C_MEM_STREL_IMM 333#define IPFINS$C_MEM_LDF 384#define IPFINS$C_MEM_LDFS 385#define IPFINS$C_MEM_LDFA 386#define IPFINS$C_MEM_LDFSA 387 #define IPFINS$C_MEM_LDFCCLR 392#define IPFINS$C_MEM_LDF 'CNC 393#define IPFINS$C_MEM_STF 396 #define IPFINS$C_MEM_LDF_IMM 448!#define IPFINS$C_MEM_LDFS_IMM 449!#define IPFINS$C_MEM_LDFA_IMM 450"#define IPFINS$C_MEM_LDFSA_IMM 451$#define IPFINS$C_MEM_LDFCCLR_IMM 456##define IPFINS$C_MEM_LDFCNC_IMM 457 #define IPFINS$C_MEM_STF_IMM 460N/* Probe opcodes found in MEM_X6 field */N#define IPFINS$C_PROBE_RR 56 /* Prober register form */N#define IPFINS$C_PROBE_WR 57 /* Probew regi 'ster form */N#define IPFINS$C_PROBE_RI 24 /* Prober immediate form */N#define IPFINS$C_PROBE_WI 25 /* Probew immediate form */N#define IPFINS$C_PROBE_RWF 49 /* Proberw fault form */N#define IPFINS$C_PROBE_RF 50 /* Prober fault form */N#define IPFINS$C_PROBE_WF 51 /* Probew fault form */N/* */I '/* Macros for Immediate Formation (Table 4-80 on Pages 259 to 261) */I/* and for Memory Opcode Formation */N/* */ #define a2_count2(slot) \/ (((A2_FORMAT *)&(slot))->ipfins$v_a2_ct2d + 1)#define a3_imm8(slot) \0 ((((A3_FORMAT *)&(slot))->ipfins$v_a3_s << 7) \. | ((A3_FORMAT *)&(slot))->ipfins$v_a3_imm7b)#define a4_imm14(slot) \1 ((((A4_FORMAT *)&(slot))->ipfins$v_a4_s < '< 13) \6 | (((A4_FORMAT *)&(slot))->ipfins$v_a4_imm6d << 7) \. | ((A4_FORMAT *)&(slot))->ipfins$v_a4_imm7b)#define a5_imm22(slot) \1 ((((A5_FORMAT *)&(slot))->ipfins$v_a5_s << 21) \7 | (((A5_FORMAT *)&(slot))->ipfins$v_a5_imm5c << 16) \6 | (((A5_FORMAT *)&(slot))->ipfins$v_a5_imm9d << 7) \. | ((A5_FORMAT *)&(slot))->ipfins$v_a5_imm7b)#define a8_imm8(slot) \0 ((((A8_FORMAT *)&(slot))->ipfins$v_a8_s << 7) \. | ((A8_FORMAT *)&(slot))->ipfins$v_a8_imm7b)#define a10_count2(slot) \1 ' (((A10_FORMAT *)&(slot))->ipfins$v_a10_ct2d + 1)#define i1_count2(slot) \7 ((((I1_FORMAT *)&(slot))->ipfins$v_i1_ct2d == 0) ? 0 \9 : (((I1_FORMAT *)&(slot))->ipfins$v_i1_ct2d == 1) ? 7 \> : (((I1_FORMAT *)&(slot))->ipfins$v_i1_ct2d == 2) ? 15 : 16)#define i3_mbtype4(slot) \A ((((I3_FORMAT *)&(slot))->ipfins$v_i3_mbt4c == 0x0) ? "@brcst" \A : (((I3_FORMAT *)&(slot))->ipfins$v_i3_mbt4c == 0x8) ? "@mix" \B : (((I3_FORMAT *)&(slot))->ipfins$v_i3_mbt4c == 0x9) ? "@shuf" \A : (((I3_FO 'RMAT *)&(slot))->ipfins$v_i3_mbt4c == 0xA) ? "@alt" \E : (((I3_FORMAT *)&(slot))->ipfins$v_i3_mbt4c == 0xB) ? "@rev" : "")#define i4_mhtype8(slot) \, (((I4_FORMAT *)&(slot))->ipfins$v_i4_mht8c)#define i6_count5(slot) \. (((I6_FORMAT *)&(slot))->ipfins$v_i6_count5b)#define i8_count5(slot) \4 (31 - ((I8_FORMAT *)&(slot))->ipfins$v_i8_ccount5c)#define i10_count6(slot) \0 (((I10_FORMAT *)&(slot))->ipfins$v_i10_count6d)#define i11_len6(slot) \2 (((I11_FORMAT *)&(slot))->ipfins$v_i11_le'n6d + 1)#define i11_pos6(slot) \. (((I11_FORMAT *)&(slot))->ipfins$v_i11_pos6b)#define i12_len6(slot) \2 (((I12_FORMAT *)&(slot))->ipfins$v_i12_len6d + 1)#define i12_pos6(slot) \4 (63 - ((I12_FORMAT *)&(slot))->ipfins$v_i12_cpos6c)#define i13_len6(slot) \2 (((I13_FORMAT *)&(slot))->ipfins$v_i13_len6d + 1)#define i13_pos6(slot) \4 (63 - ((I13_FORMAT *)&(slot))->ipfins$v_i13_cpos6c)#define i13_imm8(slot) \2 ((((I13_FORMAT *)&(slot))->ipfins$v_i13_s << 7) \0 | ((I13_FORMAT *)&(slot))-'>ipfins$v_i13_imm7b)#define i14_len6(slot) \2 (((I14_FORMAT *)&(slot))->ipfins$v_i14_len6d + 1)#define i14_pos6(slot) \4 (63 - ((I14_FORMAT *)&(slot))->ipfins$v_i14_cpos6b)#define i14_imm1(slot) \* (((I14_FORMAT *)&(slot))->ipfins$v_i14_s)#define i15_len4(slot) \2 (((I15_FORMAT *)&(slot))->ipfins$v_i15_len4d + 1)#define i15_pos6(slot) \4 (63 - ((I15_FORMAT *)&(slot))->ipfins$v_i15_cpos6d)#define i16_pos6(slot) \. (((I16_FORMAT *)&(slot))->ipfins$v_i16_pos6b)#define i18_imm21(slot) '\3 ((((I18_FORMAT *)&(slot))->ipfins$v_i18_i << 20) \1 | ((I18_FORMAT *)&(slot))->ipfins$v_i18_imm20a)#define i19_imm21(slot) \3 ((((I19_FORMAT *)&(slot))->ipfins$v_i19_i << 20) \1 | ((I19_FORMAT *)&(slot))->ipfins$v_i19_imm20a)#define i20_target25(slot) \4 (((((I20_FORMAT *)&(slot))->ipfins$v_i20_s << 20) \9 | (((I20_FORMAT *)&(slot))->ipfins$v_i20_imm13c << 7) \6 | ((I20_FORMAT *)&(slot))->ipfins$v_i20_imm7a) << 4)#define i21_tag13(slot) \4 (((I21_FORMAT *)&(slot))->ipfins$ 'v_i21_timm9c << 4)#define i23_mask17(slot) \3 ((((I23_FORMAT *)&(slot))->ipfins$v_i23_s << 16) \9 | (((I23_FORMAT *)&(slot))->ipfins$v_i23_mask8c << 8) \8 | (((I23_FORMAT *)&(slot))->ipfins$v_i23_mask7a << 1))#define i24_imm44(slot) \: (((int64)((I24_FORMAT *)&(slot))->ipfins$v_i24_s << 43) \A | ((uint64)((I24_FORMAT *)&(slot))->ipfins$v_i24_imm27a << 16))#define i27_imm8(slot) \2 ((((I27_FORMAT *)&(slot))->ipfins$v_i27_s << 7) \0 | ((I27_FORMAT *)&(slot))->ipfins$v_i27_imm7b)#d 'efine i30_imm5(slot) \3 (((I30_FORMAT *)&(slot))->ipfins$v_i30_imm5b + 32)#define m3_imm9(slot) \0 ((((M3_FORMAT *)&(slot))->ipfins$v_m3_s << 8) \2 | (((M3_FORMAT *)&(slot))->ipfins$v_m3_i << 7) \. | ((M3_FORMAT *)&(slot))->ipfins$v_m3_imm7b)#define m5_imm9(slot) \0 ((((M5_FORMAT *)&(slot))->ipfins$v_m5_s << 8) \2 | (((M5_FORMAT *)&(slot))->ipfins$v_m5_i << 7) \. | ((M5_FORMAT *)&(slot))->ipfins$v_m5_imm7a)#define m8_imm9(slot) \0 ((((M8_FORMAT *)&(slot))->ipfins$v_m8_s << 8) \2 ' | (((M8_FORMAT *)&(slot))->ipfins$v_m8_i << 7) \. | ((M8_FORMAT *)&(slot))->ipfins$v_m8_imm7b)#define m10_imm9(slot) \2 ((((M10_FORMAT *)&(slot))->ipfins$v_m10_s << 8) \4 | (((M10_FORMAT *)&(slot))->ipfins$v_m10_i << 7) \0 | ((M10_FORMAT *)&(slot))->ipfins$v_m10_imm7a)#define m15_imm9(slot) \2 ((((M15_FORMAT *)&(slot))->ipfins$v_m15_s << 8) \4 | (((M15_FORMAT *)&(slot))->ipfins$v_m15_i << 7) \0 | ((M15_FORMAT *)&(slot))->ipfins$v_m15_imm7b)#define m17_inc3(slot) \= (((((M17_FORMAT ' *)&(slot))->ipfins$v_m17_s == 0) ? 1 : -1) \; * ((((M17_FORMAT *)&(slot))->ipfins$v_m17_i2b == 3) ? 1 \; : 1 << (4 - ((M17_FORMAT *)&(slot))->ipfins$v_m17_i2b)))#define m20_target25(slot) \4 (((((M20_FORMAT *)&(slot))->ipfins$v_m20_s << 20) \9 | (((M20_FORMAT *)&(slot))->ipfins$v_m20_imm13c << 7) \6 | ((M20_FORMAT *)&(slot))->ipfins$v_m20_imm7a) << 4)#define m21_target25(slot) \4 (((((M21_FORMAT *)&(slot))->ipfins$v_m21_s << 20) \9 | (((M21_FORMAT *)&(slot))->ipfins$v_m21_imm13c '<< 7) \6 | ((M21_FORMAT *)&(slot))->ipfins$v_m21_imm7a) << 4)#define m22_target25(slot) \4 (((((M22_FORMAT *)&(slot))->ipfins$v_m22_s << 20) \7 | ((M22_FORMAT *)&(slot))->ipfins$v_m22_imm20b) << 4)#define m23_target25(slot) \4 (((((M23_FORMAT *)&(slot))->ipfins$v_m23_s << 20) \7 | ((M23_FORMAT *)&(slot))->ipfins$v_m23_imm20b) << 4)#define m30_imm8(slot) \2 ((((M30_FORMAT *)&(slot))->ipfins$v_m30_s << 7) \0 | ((M30_FORMAT *)&(slot))->ipfins$v_m30_imm7b)#define m34_il(slot) \, ((( 'M34_FORMAT *)&(slot))->ipfins$v_m34_sol)#define m34_o(slot) \- (((M34_FORMAT *)&(slot))->ipfins$v_m34_sof \. - ((M34_FORMAT *)&(slot))->ipfins$v_m34_sol)#define m34_r(slot) \1 (((M34_FORMAT *)&(slot))->ipfins$v_m34_sor << 3)#define m37_imm21(slot) \3 ((((M37_FORMAT *)&(slot))->ipfins$v_m37_i << 20) \1 | ((M37_FORMAT *)&(slot))->ipfins$v_m37_imm20a)#define m39_imm2(slot) \, (((M39_FORMAT *)&(slot))->ipfins$v_m39_i2b)#define m40_imm2(slot) \, (((M40_FORMAT *)&(slot))->ipfins$v_ 'm40_i2b)#define m44_imm24(slot) \3 ((((M44_FORMAT *)&(slot))->ipfins$v_m44_i << 23) \7 | (((M44_FORMAT *)&(slot))->ipfins$v_m44_i2d << 21) \1 | ((M44_FORMAT *)&(slot))->ipfins$v_m44_imm21a)#define m48_imm21(slot) \3 ((((M48_FORMAT *)&(slot))->ipfins$v_m48_i << 20) \1 | ((M48_FORMAT *)&(slot))->ipfins$v_m48_imm20a)#define m49_imm19(slot) \3 ((((M49_FORMAT *)&(slot))->ipfins$v_m49_i << 18) \9 | (((M49_FORMAT *)&(slot))->ipfins$v_m49_imm14b << 4) \0 | ((M49_FORMAT *)&(slot))- '>ipfins$v_m49_imm4a)#define m50_imm16(slot) \3 ((((M50_FORMAT *)&(slot))->ipfins$v_m50_i << 15) \9 | (((M50_FORMAT *)&(slot))->ipfins$v_m50_imm11b << 4) \0 | ((M50_FORMAT *)&(slot))->ipfins$v_m50_imm4a)#define m52_cnt6(slot) \2 (((M52_FORMAT *)&(slot))->ipfins$v_m52_cnt6a + 1)#define m52_stride5(slot) \6 (((M52_FORMAT *)&(slot))->ipfins$v_m52_stride5b << 6)#define b1_target25(slot) \2 (((((B1_FORMAT *)&(slot))->ipfins$v_b1_s << 20) \5 | ((B1_FORMAT *)&(slot))->ipfins$v_b1_imm20b ') << 4)#define b2_target25(slot) \2 (((((B2_FORMAT *)&(slot))->ipfins$v_b2_s << 20) \5 | ((B2_FORMAT *)&(slot))->ipfins$v_b2_imm20b) << 4)#define b3_target25(slot) \2 (((((B3_FORMAT *)&(slot))->ipfins$v_b3_s << 20) \5 | ((B3_FORMAT *)&(slot))->ipfins$v_b3_imm20b) << 4)#define b6_target25(slot) \2 (((((B6_FORMAT *)&(slot))->ipfins$v_b6_s << 20) \5 | ((B6_FORMAT *)&(slot))->ipfins$v_b6_imm20b) << 4)#define b6_tag13(slot) \3 (((((B6_FORMAT *)&(slot))->ipfins$v_b6_t2e << 7) \5 '| ((B6_FORMAT *)&(slot))->ipfins$v_b6_timm7a) << 4)#define b7_tag13(slot) \3 (((((B7_FORMAT *)&(slot))->ipfins$v_b7_t2e << 7) \5 | ((B7_FORMAT *)&(slot))->ipfins$v_b7_timm7a) << 4)#define b9_imm21(slot) \1 ((((B9_FORMAT *)&(slot))->ipfins$v_b9_i << 20) \/ | ((B9_FORMAT *)&(slot))->ipfins$v_b9_imm20a)#define b10_target25(slot) \4 (((((B10_FORMAT *)&(slot))->ipfins$v_b10_s << 20) \7 | ((B10_FORMAT *)&(slot))->ipfins$v_b10_imm20b) << 4)#define b10_count9(slot) \4 ((((B10_FORMAT *) '&(slot))->ipfins$v_b10_c2e << 7) \2 | ((B10_FORMAT *)&(slot))->ipfins$v_b10_count7a)#define f5_fclass9(slot) \7 ((((F5_FORMAT *)&(slot))->ipfins$v_f5_fclass7c << 2) \, | ((F5_FORMAT *)&(slot))->ipfins$v_f5_fc2)#define f12_amask7(slot) \0 (((F12_FORMAT *)&(slot))->ipfins$v_f12_amask7b)#define f12_omask7(slot) \0 (((F12_FORMAT *)&(slot))->ipfins$v_f12_omask7c)#define f14_target25(slot) \4 (((((F14_FORMAT *)&(slot))->ipfins$v_f14_s << 20) \7 | ((F14_FORMAT *)&(slot))->ipfins$v_f14_imm2 '0a) << 4)#define f15_imm21(slot) \3 ((((F15_FORMAT *)&(slot))->ipfins$v_f15_i << 20) \1 | ((F15_FORMAT *)&(slot))->ipfins$v_f15_imm20a)#define f16_imm21(slot) \3 ((((F16_FORMAT *)&(slot))->ipfins$v_f16_i << 20) \1 | ((F16_FORMAT *)&(slot))->ipfins$v_f16_imm20a)!#define x1_imm62(x_slot,l_slot) \; ((((L125_FORMAT *)&(l_slot))->ipfins$v_l125_imm41 << 21) \5 | (((X1_FORMAT *)&(x_slot))->ipfins$v_x1_i << 20) \1 | ((X1_FORMAT *)&(x_slot))->ipfins$v_x1_imm20a)!#define x2_imm64(x_s !'lot,l_slot) \; (((uint64)((X2_FORMAT *)&(x_slot))->ipfins$v_x2_i << 63) \= | (((L125_FORMAT *)&(l_slot))->ipfins$v_l125_imm41 << 22) \6 | (((X2_FORMAT *)&(x_slot))->ipfins$v_x2_ic << 21) \9 | (((X2_FORMAT *)&(x_slot))->ipfins$v_x2_imm5c << 16) \8 | (((X2_FORMAT *)&(x_slot))->ipfins$v_x2_imm9d << 7) \0 | ((X2_FORMAT *)&(x_slot))->ipfins$v_x2_imm7b)$#define x3_target64(x_slot,l_slot) \< ((((uint64)((X3_FORMAT *)&(x_slot))->ipfins$v_x3_i << 59) \; | (((L34_FORMAT *)&(l_slot))->ipfins$v "'_l34_imm39 << 20) \7 | ((X3_FORMAT *)&(x_slot))->ipfins$v_x3_imm20b) << 4)$#define x4_target64(x_slot,l_slot) \< ((((uint64)((X4_FORMAT *)&(x_slot))->ipfins$v_x4_i << 59) \; | (((L34_FORMAT *)&(l_slot))->ipfins$v_l34_imm39 << 20) \7 | ((X4_FORMAT *)&(x_slot))->ipfins$v_x4_imm20b) << 4)!#define x5_imm62(x_slot,l_slot) \; ((((L125_FORMAT *)&(l_slot))->ipfins$v_l125_imm41 << 21) \5 | (((X5_FORMAT *)&(x_slot))->ipfins$v_x5_i << 20) \1 | ((X5_FORMAT *)&(x_slot))->ipfins$v_x5_imm20a)#'#pragma inline (mem_opcode)(static int mem_opcode (MEM_FORMAT slot) {$ if (slot.ipfins$v_mem_opcode&1) 1 return ((slot.ipfins$v_mem_opcode << 6) |- (slot.ipfins$v_mem_x6 >> 2)); else 1 return ((slot.ipfins$v_mem_opcode << 6) |, (slot.ipfins$v_mem_x << 4) |- (slot.ipfins$v_mem_x6 >> 2));} $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pra$'gma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IPFINSDEF_LOADED */ wwPL[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterpri%'se Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is no&'t **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************************* ''*************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */F/* Source: 29-APR-2021 17:26:56 $1$DGA8345:[LIB_H.SRC]IPLDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IPLDEF ***/#ifndef __IPLDEF_LOADED#define __IPLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pra('gma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct)'#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* PROCESSOR INTERRUPT PRIORITY LEVEL DEFINTIONS */N/*- */N/* *' */N#define IPL$_HWCLK 22 /*HARDWARE CLOCK LEVEL */P#define IPL$_PERFMON 15 /*PERFORMANCE MONITORING SYNCH LEVEL */N#define IPL$_IOPOST 4 /*I/O POST PROCESSING LEVEL */N#define IPL$_MAILBOX 11 /*WRITE MAILBOX INTERLOCK LEVEL */N#define IPL$_POWER 31 /*POWERFAIL INTERLOCK LEVEL */N#define IPL$_QUEUEAST 6 /*QUEUE AST LEVE+'L */N#define IPL$_RESCHED 3 /*SCHEDULER LEVEL */T#define IPL$_SYNCH 8 /*SYSTEM DATA BASE SYNCHRONIZATION LEVEL */N#define IPL$_TIMER 8 /*TIME QUEUE PROCESSING LEVEL */N#define IPL$_TIMERFORK 7 /*TIMER FORK INTERRUPT LEVEL */N#define IPL$_ASTDEL 2 /*AST DELIVERY INTERRUPT */N#define IPL$_SCS 8 /*SCS SYNCHRONIZATION IPL ,'*/N#define IPL$_IPINTR 22 /*IP INTERRUPT SYNCHRONIZATION IPL */N#define IPL$_SCHED 8 /*SCHEDULING DATABASE IPL */N#define IPL$_MMG 8 /*MMG DATABASE IPL */N#define IPL$_IO_MISC 8 /*IO_MISC IPL */N#define IPL$_FILSYS 8 /*FILSYS DATABASE IPL */N#define IPL$_TX_SYNCH 8 /*TX_SYNCH IPL */N#define IPL$_LCKMGR 8 -' /*LOCK MANAGER IPL */N#define IPL$_IOLOCK8 8 /*IOLOCK8 DATABASE IPL */N#define IPL$_PORT 8 /*PORTLOCK IPL */N#define IPL$_IOLOCK9 9 /*IOLOCK9 DATABASE IPL */N#define IPL$_IOLOCK10 10 /*IOLOCK10 DATABASE IPL */N#define IPL$_IOLOCK11 11 /*IOLOCK11 DATABASE IPL */N#define IPL$_POOL 11 /*POOL D.'ATABASE IPL */N#define IPL$_POOL_S2 11 /*POOL_S2 DATABASE IPL */N#define IPL$_INVALIDATE 21 /*INVALIDATE DATABASE IPL */N#define IPL$_VIRTCONS 22 /*VIRTCONS DATABASE IPL */N#define IPL$_EMB 31 /*EMB DATABASE IPL */N#define IPL$_MCHECK 31 /*MACHINE CHECK IPL */N#define IPL$_MEGA 31 /*IPL FOR KITCHEN SINK LOCK /' */N#define IPL$_FORKABLE_IPL 3904 /*Mask of IPL's which are forkable */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IPLDEF_LOADED */ wwpM[UM/*******************************************************************0'********/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** 1' **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 2' **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */G/* Source: 22-APR-2010 18:33:16 $1$DGA8345:[LIB_H.SRC]IPMIDEF.SDL;1 *//******************************************************************************************************************* 3'*************//*** MODULE $IPMIDEF ***/#ifndef __IPMIDEF_LOADED#define __IPMIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointe4'rs */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* 5' */N/* IPMI Max Buffer size */N#define IPMI$K_MAX_BUFSIZE 512 /* For both request and response */N/* */N/* IMB request flags */N#define IPMI$K_NO_IMB_RESPONSE 1 /* don't wait for IMB response */N/* */N/*6' + */N/* This structure represents a IMB* request directed to the IPMI driver */N/* The first struct covers the first common part of the request, some IPMI */N/* commands don't even have any request data. */N/* - */N#define IPMI$K_MIN_REQSIZE 13 /* Request without data */Q#define IPMI$SACPIPWR_REQ$K_7'DATLEN 2 /* data length of Set ACPI Power state */Y#define IPMI$SACPIPWR_REQ$K_LENGTH 15 /* total length of Set ACPI Power state struct */##define IPMI$CH_CTRL_REQ$M_CTRL 0xFN#define IPMI$CH_CTRL_REQ$K_DATLEN 1 /* data length of Chassis control */T#define IPMI$CH_CTRL_REQ$K_LENGTH 14 /* total length of Chassis control struct */"#define IPMI$CH_ID_REQ$M_FORCE 0x1N#define IPMI$CH_ID_REQ$K_DATLEN 2 /* data length of Chassis Indentify */V#define IPMI$CH_ID_REQ$K_LENGTH 15 8' /* total length of Chassis Indentify struct */!#define IPMI$S_EV_R_REQ$M_LUN 0x3O#define IPMI$S_EV_R_REQ$K_DATLEN 2 /* data length of Set event receiver */W#define IPMI$S_EV_R_REQ$K_LENGTH 15 /* total length of Set event receiver struct */'#define IPMI$P_EV_REQ$M_EVENT_TYPE 0x7F&#define IPMI$P_EV_REQ$M_EVENT_DIR 0x80N#define IPMI$P_EV_REQ$K_DATLEN 8 /* data length of Platform event */S#define IPMI$P_EV_REQ$K_LENGTH 21 /* total length of Platform event struct */%9'#define IPMI$GD_SDR_I_REQ$M_COUNT 0x1P#define IPMI$GD_SDR_I_REQ$K_DATLEN 1 /* data length of Get Device SDR info */X#define IPMI$GD_SDR_I_REQ$K_LENGTH 14 /* total length of Get Device SDR info struct */W#define IPMI$G_SEN_RF_REQ$K_DATLEN 2 /* data length of Get sensor reading factors */_#define IPMI$G_SEN_RF_REQ$K_LENGTH 15 /* total length of Get sensor reading factors struct */R#define IPMI$S_SEN_H_REQ$K_DATLEN 4 /* data length of Set sensor hysteresis */Z#define IPMI$S_SEN_H_R :'EQ$K_LENGTH 17 /* total length of Set sensor hysteresis struct */R#define IPMI$G_SEN_H_REQ$K_DATLEN 2 /* data length of Get sensor hysteresis */Z#define IPMI$G_SEN_H_REQ$K_LENGTH 15 /* total length of Get sensor hysteresis struct */'#define IPMI$S_SEN_TH_REQ$M_L_NC_TF 0x1&#define IPMI$S_SEN_TH_REQ$M_L_C_TF 0x2'#define IPMI$S_SEN_TH_REQ$M_L_NR_TF 0x4'#define IPMI$S_SEN_TH_REQ$M_U_NC_TF 0x8'#define IPMI$S_SEN_TH_REQ$M_U_C_TF 0x10(#define IPMI$S_SEN_TH_REQ$M_U_NR_TF 0x20Q#define IP ;'MI$S_SEN_TH_REQ$K_DATLEN 8 /* data length of Set sensor threshold */Y#define IPMI$S_SEN_TH_REQ$K_LENGTH 21 /* total length of Set sensor threshold struct */Q#define IPMI$G_SEN_TH_REQ$K_DATLEN 1 /* data length of Get sensor threshold */Y#define IPMI$G_SEN_TH_REQ$K_LENGTH 14 /* total length of Get sensor threshold struct */$#define IPMI$S_SEN_EE_REQ$M_RSVD 0xF$#define IPMI$S_SEN_EE_REQ$M_SEL 0x30)#define IPMI$S_SEN_EE_REQ$M_DIS_SCAN 0x40(#define IPMI$S_SEN_EE_REQ$M_DIS_ALL 0x80T#d<'efine IPMI$S_SEN_EE_REQ$K_DATLEN 6 /* data length of Set sensor event enable */\#define IPMI$S_SEN_EE_REQ$K_LENGTH 19 /* total length of Set sensor event enable struct */T#define IPMI$G_SEN_EE_REQ$K_DATLEN 1 /* data length of Get sensor event enable */\#define IPMI$G_SEN_EE_REQ$K_LENGTH 14 /* total length of Get sensor event enable struct */$#define IPMI$S_SEN_E_REQ$M_RSVD 0x7F'#define IPMI$S_SEN_E_REQ$M_DIS_ALL 0x80Q#define IPMI$S_SEN_E_REQ$K_DATLEN 6 /* data length of Re-arm sen='sor events */Y#define IPMI$S_SEN_E_REQ$K_LENGTH 19 /* total length of Re-arm sensor events struct */T#define IPMI$G_SEN_ES_REQ$K_DATLEN 1 /* data length of Get sensor event status */\#define IPMI$G_SEN_ES_REQ$K_LENGTH 14 /* total length of Get sensor event status struct */P#define IPMI$G_SEN_R_REQ$K_DATLEN 1 /* data length of Get sensor reading */W#define IPMI$G_SEN_R_REQ$K_LENGTH 14 /* total length of Get sensor reading struct */+#define IPMI$S_SEN_TY_REQ$M_EVENT_TYPE 0x7FN>'#define IPMI$S_SEN_TY_REQ$K_DATLEN 3 /* data length of Set sensor type */T#define IPMI$S_SEN_TY_REQ$K_LENGTH 16 /* total length of Set sensor type struct */N#define IPMI$G_SEN_TY_REQ$K_DATLEN 1 /* data length of Get sensor type */T#define IPMI$G_SEN_TY_REQ$K_LENGTH 14 /* total length of Get sensor type struct */S#define IPMI$GFRU_I_REQ$K_DATLEN 1 /* data length of Get FRU Inventory area */[#define IPMI$GFRU_I_REQ$K_LENGTH 14 /* total length of Get FRU Inventory area struct?' */N#define IPMI$RFRU_REQ$K_DATLEN 4 /* data length of Read FRU data */R#define IPMI$RFRU_REQ$K_LENGTH 17 /* total lenght of Read FRU data struct */N#define IPMI$GSDR_REQ$K_DATLEN 6 /* data length of Get SDR entry */R#define IPMI$GSDR_REQ$K_LENGTH 19 /* total length of Get SDR entry struct */N#define IPMI$GSEL_REQ$K_DATLEN 6 /* data length of Get SEL entry */R#define IPMI$GSEL_REQ$K_LENGTH 19 /* total length of Get SEL entry struct */N#define @'IPMI$ASEL_REQ$K_DATLEN 16 /* data length of Add SEL entry */R#define IPMI$ASEL_REQ$K_LENGTH 29 /* total length of Add SEL entry struct */U#define IPMI$DSEL_REQ$K_DATLEN 4 /* data length of Delete SEL entry request */U#define IPMI$DSEL_REQ$K_LENGTH 17 /* total length of Delete SEL entry struct */N#define IPMI$CSEL_REQ$K_DATLEN 6 /* data length of Clear SEL request */N#define IPMI$CSEL_REQ$K_LENGTH 19 /* total length of Clear SEL struct */Q#define IPMI$SA'SEL_T_REQ$K_DATLEN 4 /* data length of Set SEL Time request */Q#define IPMI$SSEL_T_REQ$K_LENGTH 17 /* total length of Set SEL Time struct */R#define IPMI$AFPL_REQ$K_DATLEN 16 /* data length of Add FPL entry request */R#define IPMI$AFPL_REQ$K_LENGTH 29 /* total length of Add FPL entry struct */T#define IPMI$GTOKEN_I_REQ$K_DATLEN 2 /* data length of Get Token Info request */S#define IPMI$GTOKEN_I_REQ$K_LENGTH 15 /* total length of Get Token Info struct */P#define IPMIB'$RTOKEN_REQ$K_DATLEN 2 /* data length of Read Token request */O#define IPMI$RTOKEN_REQ$K_LENGTH 15 /* total length of Read Token struct */X#define IPMI$P_RTOKEN_REQ$K_DATLEN 5 /* data length of Partial Read Token request */W#define IPMI$P_RTOKEN_REQ$K_LENGTH 18 /* total length of Partial Read Token struct */S#define IPMI$L_PROP_REQ$K_DATLEN 130 /* data length of Lock Property request */R#define IPMI$L_PROP_REQ$K_LENGTH 143 /* total length of Lock Property struct */U#def C'ine IPMI$U_PROP_REQ$K_DATLEN 2 /* data length of UnLock Property request */T#define IPMI$U_PROP_REQ$K_LENGTH 15 /* total length of UnLock Property struct */R#define IPMI$G_PROP_REQ$K_DATLEN 11 /* data length of Get Property request */Q#define IPMI$G_PROP_REQ$K_LENGTH 24 /* total length of Get Property struct */ typedef struct _imbrequest { __union { __struct {N unsigned int ipmi$req$l_flags; /* request flags */N unsiD'gned int ipmi$req$l_timeout; /* in uSec units ignored... */N unsigned char ipmi$req$b_rssa; /* IMB address of responder */N unsigned char ipmi$req$b_cmd; /* IMB command */S unsigned char ipmi$req$b_netfn; /* Network Function code for command */N unsigned char ipmi$req$b_rslun; /* Logical unit on responder */N unsigned char ipmi$req$b_datlen; /* Length of request data */N unsigned char ipmi$req$b E'_data [499]; /* Request data */ } ipmi$r_req;N/* */N/* IPMI Set ACPI Power state command */N/* */ __struct {1 char ipmi$sacpipwr_req$b_fill_1 [13];R unsigned char ipmi$sacpipwr_req$b_sys_pwr_st; /* system power state */R unsigned char ipmi$sacpi F'pwr_req$b_dev_pwr_st; /* device power state */# } ipmi$r_s_acpipwr_req;N/* */N/* IPMI Chassis control command */N/* */ __struct {0 char ipmi$ch_ctrl_req$b_fill_1 [13]; __union {4 unsigned char ipmi$ch_ctrl_req$b_b2; __struct {VG' unsigned ipmi$ch_ctrl_req$v_ctrl : 4; /* Chassis control values */= unsigned ipmi$ch_ctrl_req$v_fill_18_ : 4;1 } ipmi$ch_ctrl_req$r_fill_1_;- } ipmi$ch_ctrl_req$r_fill_0_;! } ipmi$r_ch_ctrl_req;N/* */N/* IPMI Chassis ID command */N/* H' */ __struct {. char ipmi$ch_id_req$b_fill_1 [13];W unsigned char ipmi$ch_id_req$b_interval; /* Identify Interval in seconds */ __union {5 unsigned char ipmi$ch_id_req$b_flags; __struct {\ unsigned ipmi$ch_id_req$v_force : 1; /* Force the Identify ON forever */; unsigned ipmi$ch_id_req$v_fill_19_ : 7;/ } ipmi$ch_id_req$r_fill_3_;+ I' } ipmi$ch_id_req$r_fill_2_; } ipmi$r_ch_id_req;N/* */N/* IPMI Set event receiver command */N/* */ __struct {/ char ipmi$s_ev_r_req$b_fill_1 [13];Y unsigned char ipmi$s_ev_r_req$b_slave_adr; /* Event receiver slave address */ __union {3 J' unsigned char ipmi$s_ev_r_req$b_b2; __struct {S unsigned ipmi$s_ev_r_req$v_lun : 2; /* LUN of event receiver */< unsigned ipmi$s_ev_r_req$v_fill_20_ : 6;0 } ipmi$s_ev_r_req$r_fill_5_;, } ipmi$s_ev_r_req$r_fill_4_; } ipmi$r_s_evr_req;N/* */N/* IPMI Platform event or event messenger command (System interface fo K'rmat) */N/* */ __struct {- char ipmi$p_ev_req$b_fill_1 [13];N unsigned char ipmi$p_ev_req$b_generate_id; /* Generator ID */N unsigned char ipmi$p_ev_req$b_rev; /* Event message format rev */N unsigned char ipmi$p_ev_req$b_sensor_type; /* Sensor Type */N unsigned char ipmi$p_ev_req$b_sensor_num; /* Sensor number */ __union {5 L' unsigned char ipmi$p_ev_req$b_ev_t_d; __struct {N unsigned ipmi$p_ev_req$v_event_type : 7; /* Event type */Q unsigned ipmi$p_ev_req$v_event_dir : 1; /* Event direction */. } ipmi$p_ev_req$r_fill_7_;* } ipmi$p_ev_req$r_fill_6_;N unsigned char ipmi$p_ev_req$b_data1; /* Event data 1 */N unsigned char ipmi$p_ev_req$b_data2; /* Event data 2 */N M' unsigned char ipmi$p_ev_req$b_data3; /* Event data 3 */ } ipmi$r_p_ev_req;N/* */N/* IPMI Get Device SDR info command */N/* */ __struct {1 char ipmi$gd_sdr_i_req$b_fill_1 [13]; __union {< unsigned char ipmi$gd_sdr_i_req$b_operation; N' __struct {Y unsigned ipmi$gd_sdr_i_req$v_count : 1; /* Get SDR or Sensor count */> unsigned ipmi$gd_sdr_i_req$v_fill_21_ : 7;2 } ipmi$gd_sdr_i_req$r_fill_9_;. } ipmi$gd_sdr_i_req$r_fill_8_;! } ipmi$r_gdsdr_i_req;N/* */N/* IPMI Get sensor reading factors command */N/* O' */ __struct {1 char ipmi$g_sen_rf_req$b_fill_1 [13];N unsigned char ipmi$g_sen_rf_req$b_sensor; /* Sensor number */N unsigned char ipmi$g_sen_rf_req$b_read_byte; /* Reading byte */ } ipmi$r_g_srf_req;N/* */N/* IPMI Set sensor hysteresis command */N/* P' */ __struct {0 char ipmi$s_sen_h_req$b_fill_1 [13];N unsigned char ipmi$s_sen_h_req$b_sensor; /* Sensor number */^ unsigned char ipmi$s_sen_h_req$b_mask; /* Future hystereris mask. Write as 'FF' */W unsigned char ipmi$s_sen_h_req$b_pos; /* Positive-going hystereris value */W unsigned char ipmi$s_sen_h_req$b_neg; /* Negative-going hystereris value */ } ipmi$r Q'_s_sh_req;N/* */N/* IPMI Get sensor hysteresis command */N/* */ __struct {0 char ipmi$g_sen_h_req$b_fill_1 [13];N unsigned char ipmi$g_sen_h_req$b_sensor; /* Sensor number */^ unsigned char ipmi$g_sen_h_req$b_mask; /* Future hystereris mask. Write as 'FF' */ R' } ipmi$r_g_sh_req;N/* */N/* IPMI Set sensor threshold command */N/* */ __struct {1 char ipmi$s_sen_th_req$b_fill_1 [13];N unsigned char ipmi$s_sen_th_req$b_sensor; /* Sensor number */ __union {5 unsigned char ipmi$s_sen_th_req$b_b2; S' __struct {h unsigned ipmi$s_sen_th_req$v_l_nc_tf : 1; /* 1 = set lower non-critical threshold */c unsigned ipmi$s_sen_th_req$v_l_c_tf : 1; /* 1 = set lower critical threshold */k unsigned ipmi$s_sen_th_req$v_l_nr_tf : 1; /* 1 = set lower non-recoverable threshold */h unsigned ipmi$s_sen_th_req$v_u_nc_tf : 1; /* 1 = set upper non-critical threshold */c unsigned ipmi$s_sen_th_req$v_u_c_tf : T'1; /* 1 = set upper critical threshold */k unsigned ipmi$s_sen_th_req$v_u_nr_tf : 1; /* 1 = set upper non-recoverable threshold */> unsigned ipmi$s_sen_th_req$v_fill_22_ : 2;3 } ipmi$s_sen_th_req$r_fill_11_;/ } ipmi$s_sen_th_req$r_fill_10_;\ unsigned char ipmi$s_sen_th_req$b_l_nc_thres; /* Lower non-critical threshold */W unsigned char ipmi$s_sen_th_req$b_l_c_thres; /* Lower critical threshold */_U' unsigned char ipmi$s_sen_th_req$b_l_nr_thres; /* Lower non-recoverable threshold */\ unsigned char ipmi$s_sen_th_req$b_u_nc_thres; /* Upper non-critical threshold */W unsigned char ipmi$s_sen_th_req$b_u_c_thres; /* Upper critical threshold */_ unsigned char ipmi$s_sen_th_req$b_u_nr_thres; /* Upper non-recoverable threshold */ } ipmi$r_s_sth_req;N/* */N/* IPMI Get V'sensor threshold command */N/* */ __struct {1 char ipmi$g_sen_th_req$b_fill_1 [13];N unsigned char ipmi$g_sen_th_req$b_sensor; /* Sensor number */ } ipmi$r_g_sth_req;N/* */N/* IPMI Set sensor event enable command */N/* W' */ __struct {1 char ipmi$s_sen_ee_req$b_fill_1 [13];N unsigned char ipmi$s_sen_ee_req$b_sensor; /* Sensor number */ __union {5 unsigned char ipmi$s_sen_ee_req$b_b2; __struct {N unsigned ipmi$s_sen_ee_req$v_rsvd : 4; /* Reserved */i unsigned ipmi$s_sen_ee_req$v_sel : 2; /* enable or disable selected evenX't messages */h unsigned ipmi$s_sen_ee_req$v_dis_scan : 1; /* 0 = disable scanning on this sensor */b unsigned ipmi$s_sen_ee_req$v_dis_all : 1; /* 0 = disable all event messages */3 } ipmi$s_sen_ee_req$r_fill_13_;/ } ipmi$s_sen_ee_req$r_fill_12_;Z unsigned short int ipmi$s_sen_ee_req$w_assert; /* Selected assertion events */^ unsigned short int ipmi$s_sen_ee_req$w_deassert; /* Selected deassertion eve Y'nts */ } ipmi$r_s_see_req;N/* */N/* IPMI Get sensor event enable command */N/* */ __struct {1 char ipmi$g_sen_ee_req$b_fill_1 [13];N unsigned char ipmi$g_sen_ee_req$b_sensor; /* Sensor number */ } ipmi$r_g_see_req;N/* Z' */N/* IPMI Re-arm sensor events command */N/* */ __struct {0 char ipmi$s_sen_e_req$b_fill_1 [13];N unsigned char ipmi$s_sen_e_req$b_sensor; /* Sensor number */ __union {4 unsigned char ipmi$s_sen_e_req$b_b2; __struct {N unsigned ipmi$s_sen_e_['req$v_rsvd : 7; /* Reserved */` unsigned ipmi$s_sen_e_req$v_dis_all : 1; /* 0 = re-arm all event messages */2 } ipmi$s_sen_e_req$r_fill_15_;. } ipmi$s_sen_e_req$r_fill_14_;` unsigned short int ipmi$s_sen_e_req$w_assert; /* re-arm selected assertion events */d unsigned short int ipmi$s_sen_e_req$w_deassert; /* re-arm selected deassertion events */ } ipmi$r_r_se_req;N/* \' */N/* IPMI Get sensor event status command */N/* */ __struct {1 char ipmi$g_sen_es_req$b_fill_1 [13];N unsigned char ipmi$g_sen_es_req$b_sensor; /* Sensor number */ } ipmi$r_g_ses_req;N/* */N/* IPMI Get sensor reading command ]' */N/* */ __struct {0 char ipmi$g_sen_r_req$b_fill_1 [13];N unsigned char ipmi$g_sen_r_req$b_sensor; /* Sensor number */ } ipmi$r_g_sr_req;N/* */N/* IPMI Set sensor type command */N/* ^' */ __struct {1 char ipmi$s_sen_ty_req$b_fill_1 [13];N unsigned char ipmi$s_sen_ty_req$b_sensor; /* Sensor number */Q unsigned char ipmi$s_sen_ty_req$b_sensor_type; /* Sensor type code */ __union {5 unsigned char ipmi$s_sen_ty_req$b_b3; __struct {^ unsigned ipmi$s_sen_ty_req$v_event_type : 7; /* Event/reading type code */> _'unsigned ipmi$s_sen_ty_req$v_fill_23_ : 1;3 } ipmi$s_sen_ty_req$r_fill_17_;/ } ipmi$s_sen_ty_req$r_fill_16_; } ipmi$r_s_sty_req;N/* */N/* IPMI Get sensor type command */N/* */ __struct {1 char ipmi$g_sen_ty_req$b_fill_1 [13];N `' unsigned char ipmi$g_sen_ty_req$b_sensor; /* Sensor number */ } ipmi$r_g_sty_req;N/* */N/* IPMI Get FRU Inventory Area command */N/* */ __struct {/ char ipmi$gfru_i_req$b_fill_1 [13];N unsigned char ipmi$gfru_i_req$b_fru_id; /* Fru Device id */ a' } ipmi$r_gfru_i_req;N/* */N/* IPMI Read FRU data command */N/* */ __struct {- char ipmi$rfru_req$b_fill_1 [13];N unsigned char ipmi$rfru_req$b_fru_id; /* Fru Device id */U unsigned short int ipmi$rfru_req$w_offset; /* Offset into the FRU data */N b' unsigned char ipmi$rfru_req$b_bcnt; /* read bytecount */ } ipmi$r_rfru_req;N/* */N/* IPMI Get SDR entry command */N/* */ __struct {- char ipmi$gsdr_req$b_fill_1 [13];N unsigned short int ipmi$gsdr_req$w_res_id; /* Reservation id */N c' unsigned short int ipmi$gsdr_req$w_rec_id; /* Record id */N unsigned char ipmi$gsdr_req$b_offset; /* Offset into the record */N unsigned char ipmi$gsdr_req$b_bcnt; /* read bytecount */ } ipmi$r_gsdr_req;N/* */N/* IPMI Get SEL entry command */N/* */ d' __struct {- char ipmi$gsel_req$b_fill_1 [13];N unsigned short int ipmi$gsel_req$w_res_id; /* Reservation id */] unsigned short int ipmi$gsel_req$w_rec_id; /* Record id 0000 first - ffff last */N unsigned char ipmi$gsel_req$b_offset; /* Offset into the record */N unsigned char ipmi$gsel_req$b_bcnt; /* read bytecount */ } ipmi$r_gsel_req;N/* e' */N/* IPMI ADD SEL entry command */N/* */ __struct {- char ipmi$asel_req$b_fill_1 [13];N unsigned char ipmi$asel_req$b_data [16]; /* Add SEL Record Data */ } ipmi$r_asel_req;N/* */N/* IPMI Delete SEL entry command f' */N/* */ __struct {- char ipmi$dsel_req$b_fill_1 [13];N unsigned short int ipmi$dsel_req$w_res_id; /* Reservation id */g unsigned short int ipmi$dsel_req$w_rec_id; /* Record id to delete 0000 first - ffff last */ } ipmi$r_dsel_req;N/* */N/* IPMI Clear SEL command g' */N/* */ __struct {- char ipmi$csel_req$b_fill_1 [13];N unsigned short int ipmi$csel_req$w_res_id; /* Reservation id */N unsigned char ipmi$csel_req$b_c; /* 'C' */N unsigned char ipmi$csel_req$b_l; /* 'L' */N unsigned char ipmi$csel_req$b_r; /* 'R' */d h' unsigned char ipmi$csel_req$b_cmd; /* Command: 'AA' initiate erase, '00' erase status */ } ipmi$r_csel_req;N/* */N/* IPMI Set SEL Time command */N/* */ __struct {/ char ipmi$ssel_t_req$b_fill_1 [13];P unsigned int ipmi$ssel_t_req$l_time; /* Time value to se i't it with */ } ipmi$r_ssel_t_req;N/* */N/* IPMI Add FPL entry command */N/* */ __struct {- char ipmi$afpl_req$b_fill_1 [13];N unsigned char ipmi$afpl_req$b_data [16]; /* Add FPL Record Data */ } ipmi$r_afpl_req;N/* j' */N/* IPMI Get Token Info command */N/* */ __struct {1 char ipmi$gtoken_i_req$b_fill_1 [13];N unsigned short int ipmi$gtoken_i_req$w_token_id; /* Token id */ } ipmi$r_gtkn_i_req;N/* */N/* IPMI Read Token command k' */N/* */ __struct {/ char ipmi$rtoken_req$b_fill_1 [13];N unsigned short int ipmi$rtoken_req$w_token_id; /* Token id */ } ipmi$r_rtkn_req;N/* */N/* IPMI Partial Read Token command */N/* l' */ __struct {1 char ipmi$p_rtoken_req$b_fill_1 [13];N unsigned short int ipmi$p_rtoken_req$w_token_id; /* Token id */V unsigned short int ipmi$p_rtoken_req$w_offset; /* Offset into the token */N unsigned char ipmi$p_rtoken_req$b_bcnt; /* read bytecount */ } ipmi$r_prtkn_req;N/* */N/* IPMI Lock Property comm m'and */N/* */ __struct {/ char ipmi$l_prop_req$b_fill_1 [13];N unsigned char ipmi$l_prop_req$b_id; /* Property id to lock */X unsigned char ipmi$l_prop_req$b_sw_id [128]; /* Software ID of requester. */O unsigned char ipmi$l_prop_req$b_type; /* Type of lock to acquire */ } ipmi$r_lprop_req;N/* n' */N/* IPMI UnLock Property command */N/* */ __struct {/ char ipmi$u_prop_req$b_fill_1 [13];N unsigned char ipmi$u_prop_req$b_id; /* Property id to unlock */N unsigned char ipmi$u_prop_req$b_type; /* Type of lock to unlock */ } ipmi$r_uprop_req;N/* o' */N/* IPMI Get Property command */N/* */ __struct {/ char ipmi$g_prop_req$b_fill_1 [13];` unsigned int ipmi$g_prop_req$l_lock; /* Reservation Lock number for this Property */N unsigned char ipmi$g_prop_req$b_id; /* Property id */Q unsigned int ipmi$ p'g_prop_req$l_offset; /* Offset into the Property */N unsigned short int ipmi$g_prop_req$w_bcnt; /* get bytecount */ } ipmi$r_gprop_req; } ipmi$r_requ; } IMBREQUEST; #if !defined(__VAXC)@#define ipmi$req$l_flags ipmi$r_requ.ipmi$r_req.ipmi$req$l_flagsD#define ipmi$req$l_timeout ipmi$r_requ.ipmi$r_req.ipmi$req$l_timeout>#define ipmi$req$b_rssa ipmi$r_requ.ipmi$r_req.ipmi$req$b_rssa<#define ipmi$req$b_cmd ipmi$r_requ.ipmi$r_req.ipmi$req$b_cmd@#definq'e ipmi$req$b_netfn ipmi$r_requ.ipmi$r_req.ipmi$req$b_netfn@#define ipmi$req$b_rslun ipmi$r_requ.ipmi$r_req.ipmi$req$b_rslunB#define ipmi$req$b_datlen ipmi$r_requ.ipmi$r_req.ipmi$req$b_datlen>#define ipmi$req$b_data ipmi$r_requ.ipmi$r_req.ipmi$req$b_dataf#define ipmi$sacpipwr_req$b_sys_pwr_st ipmi$r_requ.ipmi$r_s_acpipwr_req.ipmi$sacpipwr_req$b_sys_pwr_stf#define ipmi$sacpipwr_req$b_dev_pwr_st ipmi$r_requ.ipmi$r_s_acpipwr_req.ipmi$sacpipwr_req$b_dev_pwr_st#define ipmi$ch_ctrl_req$v_ctrl ipmi$r_rr'equ.ipmi$r_ch_ctrl_req.ipmi$ch_ctrl_req$r_fill_0_.ipmi$ch_ctrl_req$r_fill_1_.ipmi$ch_ctrl_r\ eq$v_ctrlX#define ipmi$ch_id_req$b_interval ipmi$r_requ.ipmi$r_ch_id_req.ipmi$ch_id_req$b_intervalk#define ipmi$ch_id_req$b_flags ipmi$r_requ.ipmi$r_ch_id_req.ipmi$ch_id_req$r_fill_2_.ipmi$ch_id_req$b_flags#define ipmi$ch_id_req$v_force ipmi$r_requ.ipmi$r_ch_id_req.ipmi$ch_id_req$r_fill_2_.ipmi$ch_id_req$r_fill_3_.ipmi$ch_id_req$v_force\#define ipmi$s_ev_r_req$b_slave_adr ipmi$r_requ.ipmi$r_s_evr_req.is'pmi$s_ev_r_req$b_slave_adrh#define ipmi$s_ev_r_req$b_b2 ipmi$r_requ.ipmi$r_s_evr_req.ipmi$s_ev_r_req$r_fill_4_.ipmi$s_ev_r_req$b_b2#define ipmi$s_ev_r_req$v_lun ipmi$r_requ.ipmi$r_s_evr_req.ipmi$s_ev_r_req$r_fill_4_.ipmi$s_ev_r_req$r_fill_5_.ipmi$s_ev_r_req$v_lun[#define ipmi$p_ev_req$b_generate_id ipmi$r_requ.ipmi$r_p_ev_req.ipmi$p_ev_req$b_generate_idK#define ipmi$p_ev_req$b_rev ipmi$r_requ.ipmi$r_p_ev_req.ipmi$p_ev_req$b_rev[#define ipmi$p_ev_req$b_sensor_type ipmi$r_requ.ipmi$r_p_ev_req.ipt'mi$p_ev_req$b_sensor_typeY#define ipmi$p_ev_req$b_sensor_num ipmi$r_requ.ipmi$r_p_ev_req.ipmi$p_ev_req$b_sensor_num#define ipmi$p_ev_req$v_event_type ipmi$r_requ.ipmi$r_p_ev_req.ipmi$p_ev_req$r_fill_6_.ipmi$p_ev_req$r_fill_7_.ipmi$p_ev_req$v_even\t_type#define ipmi$p_ev_req$v_event_dir ipmi$r_requ.ipmi$r_p_ev_req.ipmi$p_ev_req$r_fill_6_.ipmi$p_ev_req$r_fill_7_.ipmi$p_ev_req$v_event\_dirO#define ipmi$p_ev_req$b_data1 ipmi$r_requ.ipmi$r_p_ev_req.ipmi$p_ev_req$b_data1O#define ipmi$p_ev_req$u'b_data2 ipmi$r_requ.ipmi$r_p_ev_req.ipmi$p_ev_req$b_data2O#define ipmi$p_ev_req$b_data3 ipmi$r_requ.ipmi$r_p_ev_req.ipmi$p_ev_req$b_data3#define ipmi$gd_sdr_i_req$v_count ipmi$r_requ.ipmi$r_gdsdr_i_req.ipmi$gd_sdr_i_req$r_fill_8_.ipmi$gd_sdr_i_req$r_fill_9_.ipmi$gd_sd\r_i_req$v_countZ#define ipmi$g_sen_rf_req$b_sensor ipmi$r_requ.ipmi$r_g_srf_req.ipmi$g_sen_rf_req$b_sensor`#define ipmi$g_sen_rf_req$b_read_byte ipmi$r_requ.ipmi$r_g_srf_req.ipmi$g_sen_rf_req$b_read_byteW#define ipmi$s_sen_h_rv'eq$b_sensor ipmi$r_requ.ipmi$r_s_sh_req.ipmi$s_sen_h_req$b_sensorS#define ipmi$s_sen_h_req$b_mask ipmi$r_requ.ipmi$r_s_sh_req.ipmi$s_sen_h_req$b_maskQ#define ipmi$s_sen_h_req$b_pos ipmi$r_requ.ipmi$r_s_sh_req.ipmi$s_sen_h_req$b_posQ#define ipmi$s_sen_h_req$b_neg ipmi$r_requ.ipmi$r_s_sh_req.ipmi$s_sen_h_req$b_negW#define ipmi$g_sen_h_req$b_sensor ipmi$r_requ.ipmi$r_g_sh_req.ipmi$g_sen_h_req$b_sensorS#define ipmi$g_sen_h_req$b_mask ipmi$r_requ.ipmi$r_g_sh_req.ipmi$g_sen_h_req$b_maskZ#define w'ipmi$s_sen_th_req$b_sensor ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$b_sensoro#define ipmi$s_sen_th_req$b_b2 ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$r_fill_10_.ipmi$s_sen_th_req$b_b2#define ipmi$s_sen_th_req$v_l_nc_tf ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$r_fill_10_.ipmi$s_sen_th_req$r_fill_11_.ipmi$s_s\en_th_req$v_l_nc_tf#define ipmi$s_sen_th_req$v_l_c_tf ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$r_fill_10_.ipmi$s_sen_th_req$r_fill_11_.ipmi$s_se\n_th_req$v_l_c_tfx'#define ipmi$s_sen_th_req$v_l_nr_tf ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$r_fill_10_.ipmi$s_sen_th_req$r_fill_11_.ipmi$s_s\en_th_req$v_l_nr_tf#define ipmi$s_sen_th_req$v_u_nc_tf ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$r_fill_10_.ipmi$s_sen_th_req$r_fill_11_.ipmi$s_s\en_th_req$v_u_nc_tf#define ipmi$s_sen_th_req$v_u_c_tf ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$r_fill_10_.ipmi$s_sen_th_req$r_fill_11_.ipmi$s_se\n_th_req$v_u_c_tf#define ipmi$s_sen_th_req$v_u_nr_tf ipy'mi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$r_fill_10_.ipmi$s_sen_th_req$r_fill_11_.ipmi$s_s\en_th_req$v_u_nr_tfb#define ipmi$s_sen_th_req$b_l_nc_thres ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$b_l_nc_thres`#define ipmi$s_sen_th_req$b_l_c_thres ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$b_l_c_thresb#define ipmi$s_sen_th_req$b_l_nr_thres ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$b_l_nr_thresb#define ipmi$s_sen_th_req$b_u_nc_thres ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$b_u_z'nc_thres`#define ipmi$s_sen_th_req$b_u_c_thres ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$b_u_c_thresb#define ipmi$s_sen_th_req$b_u_nr_thres ipmi$r_requ.ipmi$r_s_sth_req.ipmi$s_sen_th_req$b_u_nr_thresZ#define ipmi$g_sen_th_req$b_sensor ipmi$r_requ.ipmi$r_g_sth_req.ipmi$g_sen_th_req$b_sensorZ#define ipmi$s_sen_ee_req$b_sensor ipmi$r_requ.ipmi$r_s_see_req.ipmi$s_sen_ee_req$b_sensoro#define ipmi$s_sen_ee_req$b_b2 ipmi$r_requ.ipmi$r_s_see_req.ipmi$s_sen_ee_req$r_fill_12_.ipmi$s_sen_ee_req$b_b2{'#define ipmi$s_sen_ee_req$v_rsvd ipmi$r_requ.ipmi$r_s_see_req.ipmi$s_sen_ee_req$r_fill_12_.ipmi$s_sen_ee_req$r_fill_13_.ipmi$s_sen_\ ee_req$v_rsvd#define ipmi$s_sen_ee_req$v_sel ipmi$r_requ.ipmi$r_s_see_req.ipmi$s_sen_ee_req$r_fill_12_.ipmi$s_sen_ee_req$r_fill_13_.ipmi$s_sen_e\ e_req$v_sel#define ipmi$s_sen_ee_req$v_dis_scan ipmi$r_requ.ipmi$r_s_see_req.ipmi$s_sen_ee_req$r_fill_12_.ipmi$s_sen_ee_req$r_fill_13_.ipmi$s_\sen_ee_req$v_dis_scan#define ipmi$s_sen_ee_req$v_dis_all ipmi$r_requ.ip|'mi$r_s_see_req.ipmi$s_sen_ee_req$r_fill_12_.ipmi$s_sen_ee_req$r_fill_13_.ipmi$s_s\en_ee_req$v_dis_allZ#define ipmi$s_sen_ee_req$w_assert ipmi$r_requ.ipmi$r_s_see_req.ipmi$s_sen_ee_req$w_assert^#define ipmi$s_sen_ee_req$w_deassert ipmi$r_requ.ipmi$r_s_see_req.ipmi$s_sen_ee_req$w_deassertZ#define ipmi$g_sen_ee_req$b_sensor ipmi$r_requ.ipmi$r_g_see_req.ipmi$g_sen_ee_req$b_sensorW#define ipmi$s_sen_e_req$b_sensor ipmi$r_requ.ipmi$r_r_se_req.ipmi$s_sen_e_req$b_sensork#define ipmi$s_sen_e_req$b_b2 }'ipmi$r_requ.ipmi$r_r_se_req.ipmi$s_sen_e_req$r_fill_14_.ipmi$s_sen_e_req$b_b2#define ipmi$s_sen_e_req$v_rsvd ipmi$r_requ.ipmi$r_r_se_req.ipmi$s_sen_e_req$r_fill_14_.ipmi$s_sen_e_req$r_fill_15_.ipmi$s_sen_e_re\q$v_rsvd#define ipmi$s_sen_e_req$v_dis_all ipmi$r_requ.ipmi$r_r_se_req.ipmi$s_sen_e_req$r_fill_14_.ipmi$s_sen_e_req$r_fill_15_.ipmi$s_sen_e\_req$v_dis_allW#define ipmi$s_sen_e_req$w_assert ipmi$r_requ.ipmi$r_r_se_req.ipmi$s_sen_e_req$w_assert[#define ipmi$s_sen_e_req$w_deassert ipmi$r~'_requ.ipmi$r_r_se_req.ipmi$s_sen_e_req$w_deassertZ#define ipmi$g_sen_es_req$b_sensor ipmi$r_requ.ipmi$r_g_ses_req.ipmi$g_sen_es_req$b_sensorW#define ipmi$g_sen_r_req$b_sensor ipmi$r_requ.ipmi$r_g_sr_req.ipmi$g_sen_r_req$b_sensorZ#define ipmi$s_sen_ty_req$b_sensor ipmi$r_requ.ipmi$r_s_sty_req.ipmi$s_sen_ty_req$b_sensord#define ipmi$s_sen_ty_req$b_sensor_type ipmi$r_requ.ipmi$r_s_sty_req.ipmi$s_sen_ty_req$b_sensor_typeo#define ipmi$s_sen_ty_req$b_b3 ipmi$r_requ.ipmi$r_s_sty_req.ipmi$s_sen_ty_req$'r_fill_16_.ipmi$s_sen_ty_req$b_b3#define ipmi$s_sen_ty_req$v_event_type ipmi$r_requ.ipmi$r_s_sty_req.ipmi$s_sen_ty_req$r_fill_16_.ipmi$s_sen_ty_req$r_fill_17_.ipmi$\s_sen_ty_req$v_event_typeZ#define ipmi$g_sen_ty_req$b_sensor ipmi$r_requ.ipmi$r_g_sty_req.ipmi$g_sen_ty_req$b_sensorW#define ipmi$gfru_i_req$b_fru_id ipmi$r_requ.ipmi$r_gfru_i_req.ipmi$gfru_i_req$b_fru_idQ#define ipmi$rfru_req$b_fru_id ipmi$r_requ.ipmi$r_rfru_req.ipmi$rfru_req$b_fru_idQ#define ipmi$rfru_req$w_offset ipmi$r_requ'.ipmi$r_rfru_req.ipmi$rfru_req$w_offsetM#define ipmi$rfru_req$b_bcnt ipmi$r_requ.ipmi$r_rfru_req.ipmi$rfru_req$b_bcntQ#define ipmi$gsdr_req$w_res_id ipmi$r_requ.ipmi$r_gsdr_req.ipmi$gsdr_req$w_res_idQ#define ipmi$gsdr_req$w_rec_id ipmi$r_requ.ipmi$r_gsdr_req.ipmi$gsdr_req$w_rec_idQ#define ipmi$gsdr_req$b_offset ipmi$r_requ.ipmi$r_gsdr_req.ipmi$gsdr_req$b_offsetM#define ipmi$gsdr_req$b_bcnt ipmi$r_requ.ipmi$r_gsdr_req.ipmi$gsdr_req$b_bcntQ#define ipmi$gsel_req$w_res_id ipmi$r_requ.ipmi$r_gs'el_req.ipmi$gsel_req$w_res_idQ#define ipmi$gsel_req$w_rec_id ipmi$r_requ.ipmi$r_gsel_req.ipmi$gsel_req$w_rec_idQ#define ipmi$gsel_req$b_offset ipmi$r_requ.ipmi$r_gsel_req.ipmi$gsel_req$b_offsetM#define ipmi$gsel_req$b_bcnt ipmi$r_requ.ipmi$r_gsel_req.ipmi$gsel_req$b_bcntM#define ipmi$asel_req$b_data ipmi$r_requ.ipmi$r_asel_req.ipmi$asel_req$b_dataQ#define ipmi$dsel_req$w_res_id ipmi$r_requ.ipmi$r_dsel_req.ipmi$dsel_req$w_res_idQ#define ipmi$dsel_req$w_rec_id ipmi$r_requ.ipmi$r_dsel_req.ipm'i$dsel_req$w_rec_idQ#define ipmi$csel_req$w_res_id ipmi$r_requ.ipmi$r_csel_req.ipmi$csel_req$w_res_idG#define ipmi$csel_req$b_c ipmi$r_requ.ipmi$r_csel_req.ipmi$csel_req$b_cG#define ipmi$csel_req$b_l ipmi$r_requ.ipmi$r_csel_req.ipmi$csel_req$b_lG#define ipmi$csel_req$b_r ipmi$r_requ.ipmi$r_csel_req.ipmi$csel_req$b_rK#define ipmi$csel_req$b_cmd ipmi$r_requ.ipmi$r_csel_req.ipmi$csel_req$b_cmdS#define ipmi$ssel_t_req$l_time ipmi$r_requ.ipmi$r_ssel_t_req.ipmi$ssel_t_req$l_timeM#define ipmi$a'fpl_req$b_data ipmi$r_requ.ipmi$r_afpl_req.ipmi$afpl_req$b_data_#define ipmi$gtoken_i_req$w_token_id ipmi$r_requ.ipmi$r_gtkn_i_req.ipmi$gtoken_i_req$w_token_idY#define ipmi$rtoken_req$w_token_id ipmi$r_requ.ipmi$r_rtkn_req.ipmi$rtoken_req$w_token_id^#define ipmi$p_rtoken_req$w_token_id ipmi$r_requ.ipmi$r_prtkn_req.ipmi$p_rtoken_req$w_token_idZ#define ipmi$p_rtoken_req$w_offset ipmi$r_requ.ipmi$r_prtkn_req.ipmi$p_rtoken_req$w_offsetV#define ipmi$p_rtoken_req$b_bcnt ipmi$r_requ.ipmi$r_prtkn_req.'ipmi$p_rtoken_req$b_bcntN#define ipmi$l_prop_req$b_id ipmi$r_requ.ipmi$r_lprop_req.ipmi$l_prop_req$b_idT#define ipmi$l_prop_req$b_sw_id ipmi$r_requ.ipmi$r_lprop_req.ipmi$l_prop_req$b_sw_idR#define ipmi$l_prop_req$b_type ipmi$r_requ.ipmi$r_lprop_req.ipmi$l_prop_req$b_typeN#define ipmi$u_prop_req$b_id ipmi$r_requ.ipmi$r_uprop_req.ipmi$u_prop_req$b_idR#define ipmi$u_prop_req$b_type ipmi$r_requ.ipmi$r_uprop_req.ipmi$u_prop_req$b_typeR#define ipmi$g_prop_req$l_lock ipmi$r_requ.ipmi$r_gprop_req.ipmi$g '_prop_req$l_lockN#define ipmi$g_prop_req$b_id ipmi$r_requ.ipmi$r_gprop_req.ipmi$g_prop_req$b_idV#define ipmi$g_prop_req$l_offset ipmi$r_requ.ipmi$r_gprop_req.ipmi$g_prop_req$l_offsetR#define ipmi$g_prop_req$w_bcnt ipmi$r_requ.ipmi$r_gprop_req.ipmi$g_prop_req$w_bcnt"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* ' */N/* + */Q/* This structure represents a IMB* response from a command to the IPMI driver */P/* The first struct is covers the common completion code(ccode) some commands */N/* only have a completion code for a response. */N/* - */N#define IPMI$K_MIN_RESPSIZE 1 /* Response with' only ccode */*#define IPMI$GDEVID_RSP$M_IPMI_V_MAJOR 0xF+#define IPMI$GDEVID_RSP$M_IPMI_V_MINOR 0xF0l#define IPMI$GDEVID_RSP$K_NO_AXREV_LEN 12 /* length of Get Device Id response without optional aux fw rev */[#define IPMI$GDEVID_RSP$K_LENGTH 16 /* total length of Get Device Id response struct */Z#define IPMI$GST_RSP$K_LENGTH 3 /* total length of Get selftest response struct */b#define IPMI$GACPIPWR_RSP$K_LENGTH 3 /* total length of Get ACPI Power state response struct '*/]#define IPMI$GD_GUID_RSP$K_LENGTH 17 /* total length of Get Device GUID response struct */`#define IPMI$G_WATCHDOG_RSP$K_LENGTH 9 /* total length of Get Watchdog timer response struct */l#define IPMI$GBTCAP_RSP$K_LENGTH 6 /* total length of Get BT Interface Capablilities response struct */]#define IPMI$GS_GUID_RSP$K_LENGTH 17 /* total length of Get System GUID response struct */&#define IPMI$GCH_CAP_RSP$M_INTRUDE 0x1$#define IPMI$GCH_CAP_RSP$M_LCKED 0x2'#define IPMI$GCH_CAP_RSP '$M_DIAG_INT 0x4$#define IPMI$GCH_CAP_RSP$M_P_LCK 0x8f#define IPMI$GCH_CAP_RSP$K_LENGTH 7 /* total length of Get Chassis Capabilities response struct */"#define IPMI$GCH_STAT_RSP$M_ON 0x1##define IPMI$GCH_STAT_RSP$M_OVR 0x2&#define IPMI$GCH_STAT_RSP$M_P_LOCK 0x4%#define IPMI$GCH_STAT_RSP$M_P_FLT 0x8'#define IPMI$GCH_STAT_RSP$M_P_CFLT 0x10)#define IPMI$GCH_STAT_RSP$M_P_POLICY 0x60"#define IPMI$GCH_STAT_RSP$M_AC 0x1%#define IPMI$GCH_STAT_RSP$M_L_OVR 0x2'#define IPMI$GCH_STAT_RSP$M_L_ 'P_LCK 0x4'#define IPMI$GCH_STAT_RSP$M_L_P_FLT 0x8%#define IPMI$GCH_STAT_RSP$M_IPMI 0x10'#define IPMI$GCH_STAT_RSP$M_INTRUDE 0x1&#define IPMI$GCH_STAT_RSP$M_FP_LCK 0x2%#define IPMI$GCH_STAT_RSP$M_DRIVE 0x4##define IPMI$GCH_STAT_RSP$M_FAN 0x8`#define IPMI$GCH_STAT_RSP$K_LENGTH 5 /* total length of Get Chassis Status response struct */!#define IPMI$G_EV_R_RSP$M_LUN 0x3`#define IPMI$G_EV_R_RSP$K_LENGTH 3 /* total length of get event receiver response struct */$#define IPMI$GD_SDR_ 'I_RSP$M_LUN0 0x1$#define IPMI$GD_SDR_I_RSP$M_LUN1 0x2$#define IPMI$GD_SDR_I_RSP$M_LUN2 0x4$#define IPMI$GD_SDR_I_RSP$M_LUN3 0x8%#define IPMI$GD_SDR_I_RSP$M_RSVD 0x70$#define IPMI$GD_SDR_I_RSP$M_POP 0x80a#define IPMI$GD_SDR_I_RSP$K_LENGTH 7 /* total length of Get Device SDR info response struct */$#define IPMI$G_SEN_RF_RSP$M_TOL 0x3F%#define IPMI$G_SEN_RF_RSP$M_M_MS 0xC0'#define IPMI$G_SEN_RF_RSP$M_ACC_LS 0x3F%#define IPMI$G_SEN_RF_RSP$M_B_MS 0xC0$#define IPMI$G_SEN_RF_RSP$M_RSVD 0x3 ''#define IPMI$G_SEN_RF_RSP$M_ACC_EXP 0xC'#define IPMI$G_SEN_RF_RSP$M_ACC_MS 0xF0%#define IPMI$G_SEN_RF_RSP$M_B_EXP 0xF'#define IPMI$G_SEN_RF_RSP$M_RESULT 0xF0h#define IPMI$G_SEN_RF_RSP$K_LENGTH 8 /* total length of Get sensor reading factors response struct */c#define IPMI$G_SEN_H_RSP$K_LENGTH 3 /* total length of Get sensor hysteresis response struct */'#define IPMI$G_SEN_TH_RSP$M_L_NC_TF 0x1&#define IPMI$G_SEN_TH_RSP$M_L_C_TF 0x2'#define IPMI$G_SEN_TH_RSP$M_L_NR_TF 0x4'#defin 'e IPMI$G_SEN_TH_RSP$M_U_NC_TF 0x8'#define IPMI$G_SEN_TH_RSP$M_U_C_TF 0x10(#define IPMI$G_SEN_TH_RSP$M_U_NR_TF 0x20b#define IPMI$G_SEN_TH_RSP$K_LENGTH 8 /* total length of Get sensor threshold response struct */%#define IPMI$G_SEN_EE_RSP$M_RSVD 0x3F)#define IPMI$G_SEN_EE_RSP$M_SCAN_DIS 0x40(#define IPMI$G_SEN_EE_RSP$M_ALL_DIS 0x80e#define IPMI$G_SEN_EE_RSP$K_LENGTH 6 /* total length of Get sensor event enable response struct */%#define IPMI$G_SEN_ES_RSP$M_RSVD 0x1F%#define IPMI$G_S 'EN_ES_RSP$M_BUSY 0x20)#define IPMI$G_SEN_ES_RSP$M_SCAN_DIS 0x40(#define IPMI$G_SEN_ES_RSP$M_ALL_DIS 0x80e#define IPMI$G_SEN_ES_RSP$K_LENGTH 6 /* total length of Get sensor event status response struct */$#define IPMI$G_SEN_R_RSP$M_RSVD 0x1F$#define IPMI$G_SEN_R_RSP$M_BUSY 0x20(#define IPMI$G_SEN_R_RSP$M_SCAN_DIS 0x40'#define IPMI$G_SEN_R_RSP$M_ALL_DIS 0x80`#define IPMI$G_SEN_R_RSP$K_LENGTH 7 /* total length of Get sensor reading response struct */+#define IPMI$G_SEN_TY_RSP$M_EVENT_ 'TYPE 0x7F]#define IPMI$G_SEN_TY_RSP$K_LENGTH 3 /* total length of Get sensor type response struct */%#define IPMI$GFRU_I_RSP$M_WRD_ACC 0x1`#define IPMI$GFRU_I_RSP$K_LENGTH 4 /* total length of FRU Inventory Area response struct */[#define IPMI$RFRU_RSP$K_LENGTH 258 /* total length of Read FRU Data response struct */)#define IPMI$GSDR_I_RSP$M_SDR_V_MAJOR 0xF*#define IPMI$GSDR_I_RSP$M_SDR_V_MINOR 0xF0(#define IPMI$GSDR_I_RSP$M_ALLOC_INFO 0x1!#define IPMI$GSDR_I_RSP$M_RES 0x2# '#define IPMI$GSDR_I_RSP$M_P_ADD 0x4!#define IPMI$GSDR_I_RSP$M_DEL 0x8##define IPMI$GSDR_I_RSP$M_RSVD 0x10'#define IPMI$GSDR_I_RSP$M_NONMODAL 0x20$#define IPMI$GSDR_I_RSP$M_MODAL 0x40"#define IPMI$GSDR_I_RSP$M_OVR 0x80e#define IPMI$GSDR_I_RSP$K_LENGTH 15 /* total length of Get SDR Repository Info response struct */p#define IPMI$GSDR_A_RSP$K_LENGTH 10 /* total length of Get SDR Repository Allocation Info response struct */d#define IPMI$RESSDR_R_RSP$K_LENGTH 3 /* total length of R 'eserve SDR Repository response struct */U#define IPMI$GSDR_RSP$K_LENGTH 259 /* total length of get SDR response struct */e#define IPMI$GSDR_T_RSP$K_LENGTH 5 /* total length of Get SDR Repository Time response struct */)#define IPMI$GSEL_I_RSP$M_SEL_V_MAJOR 0xF*#define IPMI$GSEL_I_RSP$M_SEL_V_MINOR 0xF0(#define IPMI$GSEL_I_RSP$M_ALLOC_INFO 0x1!#define IPMI$GSEL_I_RSP$M_RES 0x2##define IPMI$GSEL_I_RSP$M_P_ADD 0x4!#define IPMI$GSEL_I_RSP$M_DEL 0x8$#define IPMI$GSEL_I_RSP$M_RESVD '0x70"#define IPMI$GSEL_I_RSP$M_OVR 0x80Z#define IPMI$GSEL_I_RSP$K_LENGTH 15 /* total length of Get SEL Info response struct */e#define IPMI$GSEL_A_RSP$K_LENGTH 10 /* total length of Get SEL Allocation Info response struct */Y#define IPMI$RESSEL_RSP$K_LENGTH 3 /* total length of Reserve SEL response struct */U#define IPMI$GSEL_RSP$K_LENGTH 19 /* total length of Get SEL response struct */U#define IPMI$ASEL_RSP$K_LENGTH 3 /* total length of Add SEL response struct */X '#define IPMI$DSEL_RSP$K_LENGTH 3 /* total length of Delete SEL response struct */%#define IPMI$CSEL_RSP$M_E_PRGRESS 0xF%#define IPMI$CSEL_RSP$M_E_P_RSVD 0xF0W#define IPMI$CSEL_RSP$K_LENGTH 2 /* total length of Clear SEL response struct */Z#define IPMI$GSEL_T_RSP$K_LENGTH 5 /* total length of Get SEL Time response struct */'#define IPMI$GTOKEN_I_RSP$M_R_GUEST 0x1&#define IPMI$GTOKEN_I_RSP$M_R_USER 0x2'#define IPMI$GTOKEN_I_RSP$M_R_ADMIN 0x4'#define IPMI$GTOKEN_I_RSP$M_W_ 'GUEST 0x8'#define IPMI$GTOKEN_I_RSP$M_W_USER 0x10(#define IPMI$GTOKEN_I_RSP$M_W_ADMIN 0x20)#define IPMI$GTOKEN_I_RSP$M_CHECKSUM 0x40'#define IPMI$GTOKEN_I_RSP$M_E_INFO 0x80\#define IPMI$GTOKEN_I_RSP$K_LENGTH 2 /* total length of Get Token Info response struct */X#define IPMI$RTOKEN_RSP$K_LENGTH 257 /* total length of Read Token response struct */`#define IPMI$P_RTOKEN_RSP$K_LENGTH 257 /* total length of Partial Read Token response struct */[#define IPMI$L_PROP_RSP$K_LENGTH 137 /* ' total length of Lock Property response struct */Z#define IPMI$G_PROP_RSP$K_LENGTH 257 /* total length of Get Property response struct */ typedef struct _imbresponse { __union { __struct {N unsigned char ipmi$rsp$b_ccode; /* IMB completion code */N unsigned char ipmi$rsp$b_data [511]; /* Response data */ } ipmi$r_rsp;N/* */N/* IPMI Get Device I'D command response */N/* */ __struct {. char ipmi$gdevid_rsp$b_fill_1 [1];N unsigned char ipmi$gdevid_rsp$b_dev_id; /* Master Device ID */N unsigned char ipmi$gdevid_rsp$b_dev_rev; /* */N unsigned char ipmi$gdevid_rsp$b_frmw_rev1; /* Major FW revision */N unsigned char ipmi$gdevid_rsp$b_frmw_rev2; / '* Minor FW revision */ __union {U unsigned char ipmi$gdevid_rsp$b_ipmi_ver; /* Combined IPMI version */ __struct {Y unsigned ipmi$gdevid_rsp$v_ipmi_v_major : 4; /* IPMI Version Major */Y unsigned ipmi$gdevid_rsp$v_ipmi_v_minor : 4; /* IPMI Version Minor */1 } ipmi$gdevid_rsp$r_fill_25_;- } ipmi$gdevid_rsp$r_fill_24_;X unsigned char ipmi$gdevid_rsp$b_dev_support;' /* Additional Device Support */N unsigned char ipmi$gdevid_rsp$b_manuf_id [3]; /* */N unsigned char ipmi$gdevid_rsp$b_prod_id [2]; /* */i unsigned char ipmi$gdevid_rsp$b_ax_firm_rev [4]; /* Auxiliary Firmware Revision (optional) */ } ipmi$r_gdevid_rsp;N/* */N/* IPMI Get Selftest command response */N/* ' */ __struct {+ char ipmi$gst_rsp$b_fill_1 [1];N unsigned char ipmi$gst_rsp$b_rslt1; /* Selftest result 1 */N unsigned char ipmi$gst_rsp$b_rslt2; /* Selftest resule 2 */ } ipmi$r_gst_rsp;N/* */N/* IPMI Get ACPI Power state command response */N/* ' */ __struct {0 char ipmi$gacpipwr_rsp$b_fill_1 [1];R unsigned char ipmi$gacpipwr_rsp$b_sys_pwr_st; /* system power state */R unsigned char ipmi$gacpipwr_rsp$b_dev_pwr_st; /* device power state */# } ipmi$r_g_acpipwr_rsp;N/* */N/* IPMI Get Device GUID command response */N/* ' */ __struct {/ char ipmi$gd_guid_rsp$b_fill_1 [1];N unsigned char ipmi$gd_guid_rsp$b_guid [16]; /* Device GUID data */! } ipmi$r_gd_guid_rsp;N/* */N/* IPMI Get Watchdog timer command response */N/* */ ' __struct {2 char ipmi$g_watchdog_rsp$b_fill_1 [1];N unsigned char ipmi$g_watchdog_rsp$b_use; /* Timer use */N unsigned char ipmi$g_watchdog_rsp$b_action; /* Timer actions */S unsigned char ipmi$g_watchdog_rsp$b_pretime; /* Pre-timeout interval */Y unsigned char ipmi$g_watchdog_rsp$b_use_exp; /* Timer use expiration flags */[ unsigned short int ipmi$g_watchdog_rsp$w_i_count; /* Initial countdown value */Z ' unsigned short int ipmi$g_watchdog_rsp$w_p_count; /* Preset countdown value */! } ipmi$r_g_watch_rsp;N/* */N/* IPMI Get BT Interface Capapbilities command response */N/* */ __struct {. char ipmi$gbtcap_rsp$b_fill_1 [1];W unsigned char ipmi$gbtcap_rsp$b_max_req; /* Maximum outsta'nding requests */N unsigned char ipmi$gbtcap_rsp$b_in_size; /* Input buffer size */N unsigned char ipmi$gbtcap_rsp$b_out_size; /* Output buffer size */k unsigned char ipmi$gbtcap_rsp$b_max_time; /* BMC Request-to-Response time in seconds; 30 max */U unsigned char ipmi$gbtcap_rsp$b_max_rtry; /* Maximum recommened retrys */ } ipmi$r_gbtcap_rsp;N/* */N/* IPMI Get Sy 'stem GUID command response */N/* */ __struct {/ char ipmi$gs_guid_rsp$b_fill_1 [1];N unsigned char ipmi$gs_guid_rsp$b_guid [16]; /* System GUID data */! } ipmi$r_gs_guid_rsp;N/* */N/* IPMI Get Chassis Capabilities command response */N/* ' */ __struct {/ char ipmi$gch_cap_rsp$b_fill_1 [1]; __union {O unsigned char ipmi$gch_cap_rsp$b_flgs; /* Capabilities Flags */ __struct {p unsigned ipmi$gch_cap_rsp$v_intrude : 1; /* Provides intrusion (physical security) sensor */] unsigned ipmi$gch_cap_rsp$v_lcked : 1; /* Provides front panel lockout */u 'unsigned ipmi$gch_cap_rsp$v_diag_int : 1; /* Provides Diagnostic Interrupt (FP NMI) (IPMI 1.5) */d unsigned ipmi$gch_cap_rsp$v_p_lck : 1; /* Provides power interlock (IPMI 1.5) */= unsigned ipmi$gch_cap_rsp$v_fill_70_ : 4;2 } ipmi$gch_cap_rsp$r_fill_27_;. } ipmi$gch_cap_rsp$r_fill_26_;[ unsigned char ipmi$gch_cap_rsp$b_fru_adr; /* Chassis FRU Info Device Address */V unsigned char ipmi$gch_cap_rsp$b_s'dr_adr; /* Chassis SDR Device Address */V unsigned char ipmi$gch_cap_rsp$b_sel_adr; /* Chassis SEL Device Address */d unsigned char ipmi$gch_cap_rsp$b_sm_adr; /* Chassis System Mamangement Device Address */X unsigned char ipmi$gch_cap_rsp$b_br_adr; /* Chassis Bridge Device Address */! } ipmi$r_gch_cap_rsp;N/* */N/* IPMI Get Chassis Status command response ' */N/* */ __struct {0 char ipmi$gch_stat_rsp$b_fill_1 [1]; __union {T unsigned char ipmi$gch_stat_rsp$b_cur_pwr; /* Current power state */ __struct {N unsigned ipmi$gch_stat_rsp$v_on : 1; /* Power is on */N unsigned ipmi$gch_stat_rsp$v_ovr : 1; /* Power Overload */] unsigned ipmi$gch_stat '_rsp$v_p_lock : 1; /* Power interlock (IPMI 1.5) */N unsigned ipmi$gch_stat_rsp$v_p_flt : 1; /* Power Fault */V unsigned ipmi$gch_stat_rsp$v_p_cflt : 1; /* Power Control Fault */Y unsigned ipmi$gch_stat_rsp$v_p_policy : 2; /* Power Restore Policy */> unsigned ipmi$gch_stat_rsp$v_fill_71_ : 1;3 } ipmi$gch_stat_rsp$r_fill_29_;/ } ipmi$gch_stat_rsp$r_fill_28_; __union {Q' unsigned char ipmi$gch_stat_rsp$b_lst_pwr; /* Last power event */ __struct {N unsigned ipmi$gch_stat_rsp$v_ac : 1; /* AC failed */j unsigned ipmi$gch_stat_rsp$v_l_ovr : 1; /* Last power down caused by Power Overload */x unsigned ipmi$gch_stat_rsp$v_l_p_lck : 1; /* Last power down caused by Power interlock (IPMI 1.5) */i unsigned ipmi$gch_stat_rsp$v_l_p_flt : 1; /* Last power down c 'aused by Power Fault */k unsigned ipmi$gch_stat_rsp$v_ipmi : 1; /* Last 'power is on' state was done via IPMI */> unsigned ipmi$gch_stat_rsp$v_fill_72_ : 3;3 } ipmi$gch_stat_rsp$r_fill_31_;/ } ipmi$gch_stat_rsp$r_fill_30_; __union {T unsigned char ipmi$gch_stat_rsp$b_chas_sta; /* Misc Chassis State */ __struct {\ unsigned ipmi$gch_stat_rsp$v_intrude : 1; '/* Chassis intrusion active */] unsigned ipmi$gch_stat_rsp$v_fp_lck : 1; /* Front Panel Lockout Active */N unsigned ipmi$gch_stat_rsp$v_drive : 1; /* Drive fault */Z unsigned ipmi$gch_stat_rsp$v_fan : 1; /* Cooling/Fan Fault detected */> unsigned ipmi$gch_stat_rsp$v_fill_73_ : 4;3 } ipmi$gch_stat_rsp$r_fill_33_;/ } ipmi$gch_stat_rsp$r_fill_32_; unsigned char ipmi$gch_sta't_rsp$b_frnt_panl; /* Front Panel Button Capabilities and disable/enable status (Optional) */" } ipmi$r_gch_stat_rsp;N/* */N/* IPMI Get event receiver command response */N/* */ __struct {. char ipmi$g_ev_r_rsp$b_fill_1 [1];Y unsigned char ipmi$g_ev_r_rsp$b_slave_adr; /* Event 'receiver slave address */ __union {3 unsigned char ipmi$g_ev_r_rsp$b_b2; __struct {S unsigned ipmi$g_ev_r_rsp$v_lun : 2; /* LUN of event receiver */< unsigned ipmi$g_ev_r_rsp$v_fill_74_ : 6;1 } ipmi$g_ev_r_rsp$r_fill_35_;- } ipmi$g_ev_r_rsp$r_fill_34_; } ipmi$r_g_evr_rsp;N/* */N/* IPMI 'Get Device SDR info command response */N/* */ __struct {0 char ipmi$gd_sdr_i_rsp$b_fill_1 [1];j unsigned char ipmi$gd_sdr_i_rsp$b_count; /* Number of Sensors per LUN or SDRs in the device */ __union {7 unsigned char ipmi$gd_sdr_i_rsp$b_flag; __struct {] unsigned ipmi$gd_sdr_i_rsp$v_lun0 : 1; /* '1 = Device LUN 0 has sensors */] unsigned ipmi$gd_sdr_i_rsp$v_lun1 : 1; /* 1 = Device LUN 1 has sensors */] unsigned ipmi$gd_sdr_i_rsp$v_lun2 : 1; /* 1 = Device LUN 2 has sensors */] unsigned ipmi$gd_sdr_i_rsp$v_lun3 : 1; /* 1 = Device LUN 3 has sensors */: unsigned ipmi$gd_sdr_i_rsp$v_rsvd : 3;c unsigned ipmi$gd_sdr_i_rsp$v_pop : 1; /* Dynamic or static Sensor population */3 } 'ipmi$gd_sdr_i_rsp$r_fill_37_;/ } ipmi$gd_sdr_i_rsp$r_fill_36_;] unsigned int ipmi$gd_sdr_i_rsp$l_change; /* Sensor population change indicator */! } ipmi$r_gdsdr_i_rsp;N/* */N/* IPMI Get sensor reading factors command response */N/* */ __struct {0 char ipmi$g_sen_rf '_rsp$b_fill_1 [1];N unsigned char ipmi$g_sen_rf_rsp$b_nread; /* Next reading factor */N unsigned char ipmi$g_sen_rf_rsp$b_m_ls; /* M: ls 8 bits */ __union {8 unsigned char ipmi$g_sen_rf_rsp$b_byte4; __struct {N unsigned ipmi$g_sen_rf_rsp$v_tol : 6; /* Tolerance */N unsigned ipmi$g_sen_rf_rsp$v_m_ms : 2; /* M: ms 2 bits */3 } ipmi$g_sen_rf_rsp$r_fill_39_;/ ' } ipmi$g_sen_rf_rsp$r_fill_38_;N unsigned char ipmi$g_sen_rf_rsp$b_b_ls; /* B: ls 8 bits */ __union {8 unsigned char ipmi$g_sen_rf_rsp$b_byte6; __struct {V unsigned ipmi$g_sen_rf_rsp$v_acc_ls : 6; /* Accuracy ls 6 bits */N unsigned ipmi$g_sen_rf_rsp$v_b_ms : 2; /* B: ms 2 bits */3 } ipmi$g_sen_rf_rsp$r_fill_41_;/ } ipmi$g_sen_rf_rsp$r_fill '_40_; __union {8 unsigned char ipmi$g_sen_rf_rsp$b_byte7; __struct {N unsigned ipmi$g_sen_rf_rsp$v_rsvd : 2; /* Reserved */g unsigned ipmi$g_sen_rf_rsp$v_acc_exp : 2; /* Accuracy exponent 2 bits, unsigned */V unsigned ipmi$g_sen_rf_rsp$v_acc_ms : 4; /* Accuracy ms 4 bits */3 } ipmi$g_sen_rf_rsp$r_fill_43_;/ } ipmi$g_sen_rf_rsp$r_fill_42_; ' __union {8 unsigned char ipmi$g_sen_rf_rsp$b_byte8; __struct {\ unsigned ipmi$g_sen_rf_rsp$v_b_exp : 4; /* B exponent 4 bits, signed */a unsigned ipmi$g_sen_rf_rsp$v_result : 4; /* Result exponent 4 bits, signed */3 } ipmi$g_sen_rf_rsp$r_fill_45_;/ } ipmi$g_sen_rf_rsp$r_fill_44_; } ipmi$r_g_srf_rsp;N/* ' */N/* IPMI Get sensor hysteresis command response */N/* */ __struct {/ char ipmi$g_sen_h_rsp$b_fill_1 [1];W unsigned char ipmi$g_sen_h_rsp$b_pos; /* Positive-going hystereris value */W unsigned char ipmi$g_sen_h_rsp$b_neg; /* Negative-going hystereris value */ } ipmi$r_g_sh_rsp;N/* ' */N/* IPMI Get sensor threshold command response */N/* */ __struct {0 char ipmi$g_sen_th_rsp$b_fill_1 [1]; __union {5 unsigned char ipmi$g_sen_th_rsp$b_b2; __struct {d unsigned ipmi$g_sen_th_rsp$v_l_nc_tf : 1; /* 1 = Lower non-critical threshold */_ unsigned ipmi$'g_sen_th_rsp$v_l_c_tf : 1; /* 1 = Lower critical threshold */g unsigned ipmi$g_sen_th_rsp$v_l_nr_tf : 1; /* 1 = Lower non-recoverable threshold */d unsigned ipmi$g_sen_th_rsp$v_u_nc_tf : 1; /* 1 = Upper non-critical threshold */_ unsigned ipmi$g_sen_th_rsp$v_u_c_tf : 1; /* 1 = Upper critical threshold */g unsigned ipmi$g_sen_th_rsp$v_u_nr_tf : 1; /* 1 = Upper non-recoverable threshold */> unsigned i'pmi$g_sen_th_rsp$v_fill_75_ : 2;3 } ipmi$g_sen_th_rsp$r_fill_47_;/ } ipmi$g_sen_th_rsp$r_fill_46_;\ unsigned char ipmi$g_sen_th_rsp$b_l_nc_thres; /* Lower non-critical threshold */W unsigned char ipmi$g_sen_th_rsp$b_l_c_thres; /* Lower critical threshold */_ unsigned char ipmi$g_sen_th_rsp$b_l_nr_thres; /* Lower non-recoverable threshold */\ unsigned char ipmi$g_sen_th_rsp$b_u_nc_thres; /* Upper non-critical thresh 'old */W unsigned char ipmi$g_sen_th_rsp$b_u_c_thres; /* Upper critical threshold */_ unsigned char ipmi$g_sen_th_rsp$b_u_nr_thres; /* Upper non-recoverable threshold */ } ipmi$r_g_sth_rsp;N/* */N/* IPMI Get sensor event enable command response */N/* */ __struct {0 ch 'ar ipmi$g_sen_ee_rsp$b_fill_1 [1]; __union {5 unsigned char ipmi$g_sen_ee_rsp$b_b2; __struct {N unsigned ipmi$g_sen_ee_rsp$v_rsvd : 6; /* Reserved */a unsigned ipmi$g_sen_ee_rsp$v_scan_dis : 1; /* 0 = sensor scanning disabled */c unsigned ipmi$g_sen_ee_rsp$v_all_dis : 1; /* 0 = all event messages disabled */3 } ipmi$g_sen_ee_rsp$r_fill_49_;/ } ipmi$g'_sen_ee_rsp$r_fill_48_;Y unsigned short int ipmi$g_sen_ee_rsp$w_assert; /* assertion events enabled */] unsigned short int ipmi$g_sen_ee_rsp$w_deassert; /* deassertion events enabled */ } ipmi$r_g_see_rsp;N/* */N/* IPMI Get sensor event status command response */N/* */ __struct '{0 char ipmi$g_sen_es_rsp$b_fill_1 [1]; __union {5 unsigned char ipmi$g_sen_es_rsp$b_b2; __struct {N unsigned ipmi$g_sen_es_rsp$v_rsvd : 5; /* Reserved */s unsigned ipmi$g_sen_es_rsp$v_busy : 1; /* 1 = reading/state unavailable (busy being updated) */a unsigned ipmi$g_sen_es_rsp$v_scan_dis : 1; /* 0 = sensor scanning disabled */c unsigned ipmi$g_sen_es_r'sp$v_all_dis : 1; /* 0 = all event messages disabled */3 } ipmi$g_sen_es_rsp$r_fill_51_;/ } ipmi$g_sen_es_rsp$r_fill_50_;Z unsigned short int ipmi$g_sen_es_rsp$w_assert; /* assertion events occurred */^ unsigned short int ipmi$g_sen_es_rsp$w_deassert; /* deassertion events occurred */ } ipmi$r_g_ses_rsp;N/* */N/* IPMI Get sensor reading command respons 'e */N/* */ __struct {/ char ipmi$g_sen_r_rsp$b_fill_1 [1];d unsigned char ipmi$g_sen_r_rsp$b_value; /* Sensor value (ignore if not analog sensor) */ __union {4 unsigned char ipmi$g_sen_r_rsp$b_b3; __struct {N unsigned ipmi$g_sen_r_rsp$v_rsvd : 5; /* Reserved */r unsign'ed ipmi$g_sen_r_rsp$v_busy : 1; /* 1 = reading/state unavailable (busy being updated) */` unsigned ipmi$g_sen_r_rsp$v_scan_dis : 1; /* 0 = sensor scanning disabled */b unsigned ipmi$g_sen_r_rsp$v_all_dis : 1; /* 0 = all event messages disabled */2 } ipmi$g_sen_r_rsp$r_fill_53_;. } ipmi$g_sen_r_rsp$r_fill_52_;Y unsigned short int ipmi$g_sen_r_rsp$w_assert; /* assertion events occurred */] unsigned short ' int ipmi$g_sen_r_rsp$w_deassert; /* deassertion events occurred */ } ipmi$r_g_sr_rsp;N/* */N/* IPMI Get sensor type command response */N/* */ __struct {0 char ipmi$g_sen_ty_rsp$b_fill_1 [1];Q unsigned char ipmi$g_sen_ty_rsp$b_sensor_type; /* Sensor type code */ ' __union {5 unsigned char ipmi$g_sen_ty_rsp$b_b3; __struct {^ unsigned ipmi$g_sen_ty_rsp$v_event_type : 7; /* Event/reading type code */> unsigned ipmi$g_sen_ty_rsp$v_fill_76_ : 1;3 } ipmi$g_sen_ty_rsp$r_fill_55_;/ } ipmi$g_sen_ty_rsp$r_fill_54_; } ipmi$r_g_sty_rsp;N/* */N/* IPMI Get FRU Inventory 'Area command response */N/* */ __struct {. char ipmi$gfru_i_rsp$b_fill_1 [1];X unsigned short int ipmi$gfru_i_rsp$w_area_sze; /* FRU Inventory area size */ __union {4 unsigned char ipmi$gfru_i_rsp$b_flg; __struct {h unsigned ipmi$gfru_i_rsp$v_wrd_acc : 1; /* Device is accessed by words not bytes. */ '< unsigned ipmi$gfru_i_rsp$v_fill_77_ : 7;1 } ipmi$gfru_i_rsp$r_fill_57_;- } ipmi$gfru_i_rsp$r_fill_56_; } ipmi$r_gfru_i_rsp;N/* */N/* IPMI Read FRU data command response */N/* */ __struct {, char ipmi$rfru_rsp$b_fill_1 [1];U' unsigned char ipmi$rfru_rsp$b_cnt; /* Count of how many FRU bytes read */p unsigned char ipmi$rfru_rsp$b_data [256]; /* Possible returned from the FRU read (typical 32 max) */ } ipmi$r_rfru_rsp;N/* */N/* IPMI Get SDR Repository Info command response */N/* */ __struct {. ' char ipmi$gsdr_i_rsp$b_fill_1 [1]; __union {S unsigned char ipmi$gsdr_i_rsp$b_sdr_ver; /* Combined SDR version */ __struct {W unsigned ipmi$gsdr_i_rsp$v_sdr_v_major : 4; /* SDR Version Major */W unsigned ipmi$gsdr_i_rsp$v_sdr_v_minor : 4; /* SDR Version Minor */1 } ipmi$gsdr_i_rsp$r_fill_59_;- } ipmi$gsdr_i_rsp$r_fill_58_;j unsigned short int ipmi$gsdr_i_rsp$w'_record_cnt; /* Number of records in the SDR Repository */[ unsigned short int ipmi$gsdr_i_rsp$w_free_space; /* Free space left in bytes */Y unsigned int ipmi$gsdr_i_rsp$l_add_time; /* Most recent addition timestamp */i unsigned int ipmi$gsdr_i_rsp$l_erase_time; /* Most recent erase(delete or clear) timestamp */ __union {Q unsigned char ipmi$gsdr_i_rsp$b_op_sup; /* Operation Supported */ __struct { ' unsigned ipmi$gsdr_i_rsp$v_alloc_info : 1; /* Get SDR Repository Allocation Information command supported */f unsigned ipmi$gsdr_i_rsp$v_res : 1; /* Reserve SDR Repository command supported */a unsigned ipmi$gsdr_i_rsp$v_p_add : 1; /* Partial add SDR command supported */Z unsigned ipmi$gsdr_i_rsp$v_del : 1; /* Delete SDR command supported */N unsigned ipmi$gsdr_i_rsp$v_rsvd : 1; /* Reserved */v ' unsigned ipmi$gsdr_i_rsp$v_nonmodal : 1; /* Non-Modal SDR Repository update operation supported */o unsigned ipmi$gsdr_i_rsp$v_modal : 1; /* Modal SDR Repository update operation supported */{ unsigned ipmi$gsdr_i_rsp$v_ovr : 1; /* Overflow Flag; SDR could not be written due to lack of space */1 } ipmi$gsdr_i_rsp$r_fill_61_;- } ipmi$gsdr_i_rsp$r_fill_60_; } ipmi$r_gsdr_i_rsp;N/* ' */N/* IPMI Get SDR Repository Allocation Info command response */N/* */ __struct {. char ipmi$gsdr_a_rsp$b_fill_1 [1];` unsigned short int ipmi$gsdr_a_rsp$w_alloc; /* Number of posible allocation units */_ unsigned short int ipmi$gsdr_a_rsp$w_unit_size; /* Allocation unit size in bytes */_ unsigned short' int ipmi$gsdr_a_rsp$w_f_units; /* Number of free allocation units */f unsigned short int ipmi$gsdr_a_rsp$w_f_block; /* Largest free block in allocation units */c unsigned char ipmi$gsdr_a_rsp$b_max_size; /* Maximum record size in allocation units */ } ipmi$r_gsdr_a_rsp;N/* */N/* IPMI Reserve SDR Repository command response */N/* and/or ' */N/* IPMI Reserve Device SDR repository command response */N/* */ __struct {0 char ipmi$ressdr_r_rsp$b_fill_1 [1];O unsigned short int ipmi$ressdr_r_rsp$w_res_id; /* Reservation id */" } ipmi$r_ressdr_r_rsp;N/* */N/* IPMI Get SDR command respon'se */N/* and/or */N/* IPMI Get Device SDR response */N/* */ __struct {, char ipmi$gsdr_rsp$b_fill_1 [1];d unsigned short int ipmi$gsdr_rsp$w_rec_id; /* Record ID of the next record in the SDR */o unsigned char ipmi$gsdr_rsp$b_data ' [256]; /* Possible returned from the get SDR (typical 32 max) */ } ipmi$r_gsdr_rsp;N/* */N/* IPMI Get SDR Repository Time command response */N/* */ __struct {. char ipmi$gsdr_t_rsp$b_fill_1 [1];N unsigned int ipmi$gsdr_t_rsp$l_time; /* Present time */ } ip 'mi$r_gsdr_t_rsp;N/* */N/* IPMI Get SEL Info command response */N/* */ __struct {. char ipmi$gsel_i_rsp$b_fill_1 [1]; __union {S unsigned char ipmi$gsel_i_rsp$b_sel_ver; /* Combined SEL version */ __struct {W unsigned ipmi$gsel'_i_rsp$v_sel_v_major : 4; /* SEL Version Major */W unsigned ipmi$gsel_i_rsp$v_sel_v_minor : 4; /* SEL Version Minor */1 } ipmi$gsel_i_rsp$r_fill_63_;- } ipmi$gsel_i_rsp$r_fill_62_;W unsigned short int ipmi$gsel_i_rsp$w_entry_cnt; /* Number of log entries */[ unsigned short int ipmi$gsel_i_rsp$w_free_space; /* Free space left in bytes */Y unsigned int ipmi$gsel_i_rsp$l_add_time; /* Most recent addition tim'estamp */i unsigned int ipmi$gsel_i_rsp$l_erase_time; /* Most recent erase(delete or clear) timestamp */ __union {O unsigned char ipmi$gsel_i_rsp$b_op_sup; /* Operation Support */ __struct {u unsigned ipmi$gsel_i_rsp$v_alloc_info : 1; /* Get SEL Allocation Information command supported */\ unsigned ipmi$gsel_i_rsp$v_res : 1; /* Resereve SEL command supported */a unsigned ipmi$gs'el_i_rsp$v_p_add : 1; /* Partial add SEL command supported */Z unsigned ipmi$gsel_i_rsp$v_del : 1; /* Delete SEL command supported */N unsigned ipmi$gsel_i_rsp$v_resvd : 3; /* Reserved */{ unsigned ipmi$gsel_i_rsp$v_ovr : 1; /* Overflow Flag; Events have been dropped due to lack of space */1 } ipmi$gsel_i_rsp$r_fill_65_;- } ipmi$gsel_i_rsp$r_fill_64_; } ipmi$r_gsel_i_rsp;N/* ' */N/* IPMI Get SEL Allocation Info command response */N/* */ __struct {. char ipmi$gsel_a_rsp$b_fill_1 [1];f unsigned short int ipmi$gsel_a_rsp$w_alloc_units; /* Number of posible allocation units */_ unsigned short int ipmi$gsel_a_rsp$w_unit_size; /* Allocation unit size in bytes */_ ' unsigned short int ipmi$gsel_a_rsp$w_f_units; /* Number of free allocation units */f unsigned short int ipmi$gsel_a_rsp$w_f_block; /* Largest free block in allocation units */c unsigned char ipmi$gsel_a_rsp$b_max_size; /* Maximum record size in allocation units */ } ipmi$r_gsel_a_rsp;N/* */N/* IPMI Reserve SEL command response */N/* ' */ __struct {. char ipmi$ressel_rsp$b_fill_1 [1];N unsigned short int ipmi$ressel_rsp$w_res_id; /* Reservation id */ } ipmi$r_ressel_rsp;N/* */N/* IPMI Get SEL command response */N/* */ __stru'ct {, char ipmi$gsel_rsp$b_fill_1 [1];d unsigned short int ipmi$gsel_rsp$w_rec_id; /* Record ID of the next record in the SEL */` unsigned char ipmi$gsel_rsp$b_data [16]; /* Data returned from the Get SEL record */ } ipmi$r_gsel_rsp;N/* */N/* IPMI Add SEL command response */N/* ' */ __struct {, char ipmi$asel_rsp$b_fill_1 [1];^ unsigned short int ipmi$asel_rsp$w_rec_id; /* Record ID of the SEL record added */ } ipmi$r_asel_rsp;N/* */N/* IPMI Delete SEL command response */N/* */ __struct {, char ipmi$dsel_r 'sp$b_fill_1 [1];a unsigned short int ipmi$dsel_rsp$w_rec_id; /* Record ID for the deleted SEL record */ } ipmi$r_dsel_rsp;N/* */N/* IPMI Clear SEL command response */N/* */ __struct {, char ipmi$csel_rsp$b_fill_1 [1]; __union {3 unsigned ' char ipmi$csel_rsp$b_pgrs; __struct {g unsigned ipmi$csel_rsp$v_e_prgress : 4; /* Erasure Progress 1 == erase completed */N unsigned ipmi$csel_rsp$v_e_p_rsvd : 4; /* Reserved *// } ipmi$csel_rsp$r_fill_67_;+ } ipmi$csel_rsp$r_fill_66_; } ipmi$r_csel_rsp;N/* */N/* IPMI Get SEL Time command response ' */N/* */ __struct {. char ipmi$gsel_t_rsp$b_fill_1 [1];N unsigned int ipmi$gsel_t_rsp$l_time; /* Present time */ } ipmi$r_gsel_t_rsp;N/* */N/* IPMI Get Token Info command response */N/* ' */ __struct {0 char ipmi$gtoken_i_rsp$b_fill_1 [1]; __union {N unsigned char ipmi$gtoken_i_rsp$b_attr; /* Token attributes */ __struct {V unsigned ipmi$gtoken_i_rsp$v_r_guest : 1; /* Read access: Guest */T unsigned ipmi$gtoken_i_rsp$v_r_user : 1; /* Read access: User */^ unsigned ipmi$gtoken_i_rsp$v_r_admin : 1; /* Read access: Administrator */W ' unsigned ipmi$gtoken_i_rsp$v_w_guest : 1; /* Write access: Guest */U unsigned ipmi$gtoken_i_rsp$v_w_user : 1; /* Write access: User */_ unsigned ipmi$gtoken_i_rsp$v_w_admin : 1; /* Write access: Administrator */X unsigned ipmi$gtoken_i_rsp$v_checksum : 1; /* Token is checksumed */e unsigned ipmi$gtoken_i_rsp$v_e_info : 1; /* Extended info available (not used) */3 } ipmi$gtoken_i_rsp$ 'r_fill_69_;/ } ipmi$gtoken_i_rsp$r_fill_68_; } ipmi$r_gtkn_i_rsp;N/* */N/* IPMI Read Token command response */N/* */ __struct {. char ipmi$rtoken_rsp$b_fill_1 [1];t unsigned char ipmi$rtoken_rsp$b_data [256]; /* Possible returned from the read token ( 'typical 30 max) */ } ipmi$r_rtkn_rsp;N/* */N/* IPMI Partial Read Token command response */N/* */ __struct {0 char ipmi$p_rtoken_rsp$b_fill_1 [1];~ unsigned char ipmi$p_rtoken_rsp$b_data [256]; /* Possible returned from the partial read token (typical 30 max) */ } 'ipmi$r_prtkn_rsp;N/* */N/* IPMI Lock Property command response */N/* */ __struct {. char ipmi$l_prop_rsp$b_fill_1 [1];S unsigned int ipmi$l_prop_rsp$l_lock; /* Lock number if lock succeeds */j unsigned int ipmi$l_prop_rsp$l_lock_time; /* Time the last lock of this proper 'ty was given */\ unsigned char ipmi$l_prop_rsp$b_sw_id [128]; /* Software ID of last requester */ } ipmi$r_lprop_rsp;N/* */N/* IPMI Get Property command response */N/* */ __struct {. char ipmi$g_prop_rsp$b_fill_1 [1];j unsigned short int ipmi$g_prop_rsp$w_c 'nt; /* Count of how many Get Property bytes returned */j unsigned char ipmi$g_prop_rsp$b_data [254]; /* Possible returned data from the Get Property */ } ipmi$r_gprop_rsp; } ipmi$r_rspu; } IMBRESPONSE; #if !defined(__VAXC)@#define ipmi$rsp$b_ccode ipmi$r_rspu.ipmi$r_rsp.ipmi$rsp$b_ccode>#define ipmi$rsp$b_data ipmi$r_rspu.ipmi$r_rsp.ipmi$rsp$b_dataW#define ipmi$gdevid_rsp$b_dev_id ipmi$r_rspu.ipmi$r_gdevid_rsp.ipmi$gdevid_rsp$b_dev_idY#define ipmi$gde'vid_rsp$b_dev_rev ipmi$r_rspu.ipmi$r_gdevid_rsp.ipmi$gdevid_rsp$b_dev_rev]#define ipmi$gdevid_rsp$b_frmw_rev1 ipmi$r_rspu.ipmi$r_gdevid_rsp.ipmi$gdevid_rsp$b_frmw_rev1]#define ipmi$gdevid_rsp$b_frmw_rev2 ipmi$r_rspu.ipmi$r_gdevid_rsp.ipmi$gdevid_rsp$b_frmw_rev2v#define ipmi$gdevid_rsp$b_ipmi_ver ipmi$r_rspu.ipmi$r_gdevid_rsp.ipmi$gdevid_rsp$r_fill_24_.ipmi$gdevid_rsp$b_ipmi_ver#define ipmi$gdevid_rsp$v_ipmi_v_major ipmi$r_rspu.ipmi$r_gdevid_rsp.ipmi$gdevid_rsp$r_fill_24_.ipmi$gdevid_rsp$r_fill'_25_.ipmi$gde\vid_rsp$v_ipmi_v_major#define ipmi$gdevid_rsp$v_ipmi_v_minor ipmi$r_rspu.ipmi$r_gdevid_rsp.ipmi$gdevid_rsp$r_fill_24_.ipmi$gdevid_rsp$r_fill_25_.ipmi$gde\vid_rsp$v_ipmi_v_minora#define ipmi$gdevid_rsp$b_dev_support ipmi$r_rspu.ipmi$r_gdevid_rsp.ipmi$gdevid_rsp$b_dev_support[#define ipmi$gdevid_rsp$b_manuf_id ipmi$r_rspu.ipmi$r_gdevid_rsp.ipmi$gdevid_rsp$b_manuf_idY#define ipmi$gdevid_rsp$b_prod_id ipmi$r_rspu.ipmi$r_gdevid_rsp.ipmi$gdevid_rsp$b_prod_ida#define ipmi$gdevid_rs'p$b_ax_firm_rev ipmi$r_rspu.ipmi$r_gdevid_rsp.ipmi$gdevid_rsp$b_ax_firm_revL#define ipmi$gst_rsp$b_rslt1 ipmi$r_rspu.ipmi$r_gst_rsp.ipmi$gst_rsp$b_rslt1L#define ipmi$gst_rsp$b_rslt2 ipmi$r_rspu.ipmi$r_gst_rsp.ipmi$gst_rsp$b_rslt2f#define ipmi$gacpipwr_rsp$b_sys_pwr_st ipmi$r_rspu.ipmi$r_g_acpipwr_rsp.ipmi$gacpipwr_rsp$b_sys_pwr_stf#define ipmi$gacpipwr_rsp$b_dev_pwr_st ipmi$r_rspu.ipmi$r_g_acpipwr_rsp.ipmi$gacpipwr_rsp$b_dev_pwr_stV#define ipmi$gd_guid_rsp$b_guid ipmi$r_rspu.ipmi$r_gd_guid_rsp.i'pmi$gd_guid_rsp$b_guidZ#define ipmi$g_watchdog_rsp$b_use ipmi$r_rspu.ipmi$r_g_watch_rsp.ipmi$g_watchdog_rsp$b_use`#define ipmi$g_watchdog_rsp$b_action ipmi$r_rspu.ipmi$r_g_watch_rsp.ipmi$g_watchdog_rsp$b_actionb#define ipmi$g_watchdog_rsp$b_pretime ipmi$r_rspu.ipmi$r_g_watch_rsp.ipmi$g_watchdog_rsp$b_pretimeb#define ipmi$g_watchdog_rsp$b_use_exp ipmi$r_rspu.ipmi$r_g_watch_rsp.ipmi$g_watchdog_rsp$b_use_expb#define ipmi$g_watchdog_rsp$w_i_count ipmi$r_rspu.ipmi$r_g_watch_rsp.ipmi$g_watchdog_rsp$w_i'_countb#define ipmi$g_watchdog_rsp$w_p_count ipmi$r_rspu.ipmi$r_g_watch_rsp.ipmi$g_watchdog_rsp$w_p_countY#define ipmi$gbtcap_rsp$b_max_req ipmi$r_rspu.ipmi$r_gbtcap_rsp.ipmi$gbtcap_rsp$b_max_reqY#define ipmi$gbtcap_rsp$b_in_size ipmi$r_rspu.ipmi$r_gbtcap_rsp.ipmi$gbtcap_rsp$b_in_size[#define ipmi$gbtcap_rsp$b_out_size ipmi$r_rspu.ipmi$r_gbtcap_rsp.ipmi$gbtcap_rsp$b_out_size[#define ipmi$gbtcap_rsp$b_max_time ipmi$r_rspu.ipmi$r_gbtcap_rsp.ipmi$gbtcap_rsp$b_max_time[#define ipmi$gbtcap_rsp$b_'max_rtry ipmi$r_rspu.ipmi$r_gbtcap_rsp.ipmi$gbtcap_rsp$b_max_rtryV#define ipmi$gs_guid_rsp$b_guid ipmi$r_rspu.ipmi$r_gs_guid_rsp.ipmi$gs_guid_rsp$b_guidr#define ipmi$gch_cap_rsp$b_flgs ipmi$r_rspu.ipmi$r_gch_cap_rsp.ipmi$gch_cap_rsp$r_fill_26_.ipmi$gch_cap_rsp$b_flgs#define ipmi$gch_cap_rsp$v_intrude ipmi$r_rspu.ipmi$r_gch_cap_rsp.ipmi$gch_cap_rsp$r_fill_26_.ipmi$gch_cap_rsp$r_fill_27_.ipmi$gch_\cap_rsp$v_intrude#define ipmi$gch_cap_rsp$v_lcked ipmi$r_rspu.ipmi$r_gch_cap_rsp.ipmi$gch_cap_rsp'$r_fill_26_.ipmi$gch_cap_rsp$r_fill_27_.ipmi$gch_ca\ p_rsp$v_lcked#define ipmi$gch_cap_rsp$v_diag_int ipmi$r_rspu.ipmi$r_gch_cap_rsp.ipmi$gch_cap_rsp$r_fill_26_.ipmi$gch_cap_rsp$r_fill_27_.ipmi$gch\_cap_rsp$v_diag_int#define ipmi$gch_cap_rsp$v_p_lck ipmi$r_rspu.ipmi$r_gch_cap_rsp.ipmi$gch_cap_rsp$r_fill_26_.ipmi$gch_cap_rsp$r_fill_27_.ipmi$gch_ca\ p_rsp$v_p_lck\#define ipmi$gch_cap_rsp$b_fru_adr ipmi$r_rspu.ipmi$r_gch_cap_rsp.ipmi$gch_cap_rsp$b_fru_adr\#define ipmi$gch_cap_rsp$b_sdr_adr i'pmi$r_rspu.ipmi$r_gch_cap_rsp.ipmi$gch_cap_rsp$b_sdr_adr\#define ipmi$gch_cap_rsp$b_sel_adr ipmi$r_rspu.ipmi$r_gch_cap_rsp.ipmi$gch_cap_rsp$b_sel_adrZ#define ipmi$gch_cap_rsp$b_sm_adr ipmi$r_rspu.ipmi$r_gch_cap_rsp.ipmi$gch_cap_rsp$b_sm_adrZ#define ipmi$gch_cap_rsp$b_br_adr ipmi$r_rspu.ipmi$r_gch_cap_rsp.ipmi$gch_cap_rsp$b_br_adr|#define ipmi$gch_stat_rsp$b_cur_pwr ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_28_.ipmi$gch_stat_rsp$b_cur_pwr#define ipmi$gch_stat_rsp$v_on ipmi$r_rspu.i'pmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_28_.ipmi$gch_stat_rsp$r_fill_29_.ipmi$gch_s\ tat_rsp$v_on#define ipmi$gch_stat_rsp$v_ovr ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_28_.ipmi$gch_stat_rsp$r_fill_29_.ipmi$gch_\stat_rsp$v_ovr#define ipmi$gch_stat_rsp$v_p_lock ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_28_.ipmi$gch_stat_rsp$r_fill_29_.ipmi$g\ch_stat_rsp$v_p_lock#define ipmi$gch_stat_rsp$v_p_flt ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_28_.i'pmi$gch_stat_rsp$r_fill_29_.ipmi$gc\h_stat_rsp$v_p_flt#define ipmi$gch_stat_rsp$v_p_cflt ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_28_.ipmi$gch_stat_rsp$r_fill_29_.ipmi$g\ch_stat_rsp$v_p_cflt#define ipmi$gch_stat_rsp$v_p_policy ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_28_.ipmi$gch_stat_rsp$r_fill_29_.ipmi\$gch_stat_rsp$v_p_policy|#define ipmi$gch_stat_rsp$b_lst_pwr ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_30_.ipmi$gch_stat_rsp$b_lst_pwr#defin'e ipmi$gch_stat_rsp$v_ac ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_30_.ipmi$gch_stat_rsp$r_fill_31_.ipmi$gch_s\ tat_rsp$v_ac#define ipmi$gch_stat_rsp$v_l_ovr ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_30_.ipmi$gch_stat_rsp$r_fill_31_.ipmi$gc\h_stat_rsp$v_l_ovr#define ipmi$gch_stat_rsp$v_l_p_lck ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_30_.ipmi$gch_stat_rsp$r_fill_31_.ipmi$\gch_stat_rsp$v_l_p_lck#define ipmi$gch_stat_rsp$v_l_p_flt ipmi$r_rspu.ipmi'$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_30_.ipmi$gch_stat_rsp$r_fill_31_.ipmi$\gch_stat_rsp$v_l_p_flt#define ipmi$gch_stat_rsp$v_ipmi ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_30_.ipmi$gch_stat_rsp$r_fill_31_.ipmi$gch\_stat_rsp$v_ipmi~#define ipmi$gch_stat_rsp$b_chas_sta ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_32_.ipmi$gch_stat_rsp$b_chas_sta#define ipmi$gch_stat_rsp$v_intrude ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_32_.ipmi$gch_stat_rsp$r_fil 'l_33_.ipmi$\gch_stat_rsp$v_intrude#define ipmi$gch_stat_rsp$v_fp_lck ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_32_.ipmi$gch_stat_rsp$r_fill_33_.ipmi$g\ch_stat_rsp$v_fp_lck#define ipmi$gch_stat_rsp$v_drive ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_32_.ipmi$gch_stat_rsp$r_fill_33_.ipmi$gc\h_stat_rsp$v_drive#define ipmi$gch_stat_rsp$v_fan ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$r_fill_32_.ipmi$gch_stat_rsp$r_fill_33_.ipmi$gch_\stat_rsp$v_fanc#define 'ipmi$gch_stat_rsp$b_frnt_panl ipmi$r_rspu.ipmi$r_gch_stat_rsp.ipmi$gch_stat_rsp$b_frnt_panl\#define ipmi$g_ev_r_rsp$b_slave_adr ipmi$r_rspu.ipmi$r_g_evr_rsp.ipmi$g_ev_r_rsp$b_slave_adri#define ipmi$g_ev_r_rsp$b_b2 ipmi$r_rspu.ipmi$r_g_evr_rsp.ipmi$g_ev_r_rsp$r_fill_34_.ipmi$g_ev_r_rsp$b_b2#define ipmi$g_ev_r_rsp$v_lun ipmi$r_rspu.ipmi$r_g_evr_rsp.ipmi$g_ev_r_rsp$r_fill_34_.ipmi$g_ev_r_rsp$r_fill_35_.ipmi$g_ev_r_rsp$v_\lunZ#define ipmi$gd_sdr_i_rsp$b_count ipmi$r_rspu.ipmi$r_gdsdr_i_rsp.ipmi$'gd_sdr_i_rsp$b_countu#define ipmi$gd_sdr_i_rsp$b_flag ipmi$r_rspu.ipmi$r_gdsdr_i_rsp.ipmi$gd_sdr_i_rsp$r_fill_36_.ipmi$gd_sdr_i_rsp$b_flag#define ipmi$gd_sdr_i_rsp$v_lun0 ipmi$r_rspu.ipmi$r_gdsdr_i_rsp.ipmi$gd_sdr_i_rsp$r_fill_36_.ipmi$gd_sdr_i_rsp$r_fill_37_.ipmi$gd_s\dr_i_rsp$v_lun0#define ipmi$gd_sdr_i_rsp$v_lun1 ipmi$r_rspu.ipmi$r_gdsdr_i_rsp.ipmi$gd_sdr_i_rsp$r_fill_36_.ipmi$gd_sdr_i_rsp$r_fill_37_.ipmi$gd_s\dr_i_rsp$v_lun1#define ipmi$gd_sdr_i_rsp$v_lun2 ipmi$r_rspu.ipmi$r_gdsdr_i_'rsp.ipmi$gd_sdr_i_rsp$r_fill_36_.ipmi$gd_sdr_i_rsp$r_fill_37_.ipmi$gd_s\dr_i_rsp$v_lun2#define ipmi$gd_sdr_i_rsp$v_lun3 ipmi$r_rspu.ipmi$r_gdsdr_i_rsp.ipmi$gd_sdr_i_rsp$r_fill_36_.ipmi$gd_sdr_i_rsp$r_fill_37_.ipmi$gd_s\dr_i_rsp$v_lun3#define ipmi$gd_sdr_i_rsp$v_pop ipmi$r_rspu.ipmi$r_gdsdr_i_rsp.ipmi$gd_sdr_i_rsp$r_fill_36_.ipmi$gd_sdr_i_rsp$r_fill_37_.ipmi$gd_sd\ r_i_rsp$v_pop\#define ipmi$gd_sdr_i_rsp$l_change ipmi$r_rspu.ipmi$r_gdsdr_i_rsp.ipmi$gd_sdr_i_rsp$l_changeX#define ipmi$g_sen'_rf_rsp$b_nread ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$b_nreadV#define ipmi$g_sen_rf_rsp$b_m_ls ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$b_m_lsu#define ipmi$g_sen_rf_rsp$b_byte4 ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$r_fill_38_.ipmi$g_sen_rf_rsp$b_byte4#define ipmi$g_sen_rf_rsp$v_tol ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$r_fill_38_.ipmi$g_sen_rf_rsp$r_fill_39_.ipmi$g_sen_r\ f_rsp$v_tol#define ipmi$g_sen_rf_rsp$v_m_ms ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rs'p$r_fill_38_.ipmi$g_sen_rf_rsp$r_fill_39_.ipmi$g_sen_\ rf_rsp$v_m_msV#define ipmi$g_sen_rf_rsp$b_b_ls ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$b_b_lsu#define ipmi$g_sen_rf_rsp$b_byte6 ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$r_fill_40_.ipmi$g_sen_rf_rsp$b_byte6#define ipmi$g_sen_rf_rsp$v_acc_ls ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$r_fill_40_.ipmi$g_sen_rf_rsp$r_fill_41_.ipmi$g_se\n_rf_rsp$v_acc_ls#define ipmi$g_sen_rf_rsp$v_b_ms ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen'_rf_rsp$r_fill_40_.ipmi$g_sen_rf_rsp$r_fill_41_.ipmi$g_sen_\ rf_rsp$v_b_msu#define ipmi$g_sen_rf_rsp$b_byte7 ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$r_fill_42_.ipmi$g_sen_rf_rsp$b_byte7#define ipmi$g_sen_rf_rsp$v_rsvd ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$r_fill_42_.ipmi$g_sen_rf_rsp$r_fill_43_.ipmi$g_sen_\ rf_rsp$v_rsvd#define ipmi$g_sen_rf_rsp$v_acc_exp ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$r_fill_42_.ipmi$g_sen_rf_rsp$r_fill_43_.ipmi$g_s\en_rf_rsp$v_acc_exp#d'efine ipmi$g_sen_rf_rsp$v_acc_ms ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$r_fill_42_.ipmi$g_sen_rf_rsp$r_fill_43_.ipmi$g_se\n_rf_rsp$v_acc_msu#define ipmi$g_sen_rf_rsp$b_byte8 ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$r_fill_44_.ipmi$g_sen_rf_rsp$b_byte8#define ipmi$g_sen_rf_rsp$v_b_exp ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$r_fill_44_.ipmi$g_sen_rf_rsp$r_fill_45_.ipmi$g_sen\_rf_rsp$v_b_exp#define ipmi$g_sen_rf_rsp$v_result ipmi$r_rspu.ipmi$r_g_srf_rsp.ipmi$g_sen_rf_rsp$'r_fill_44_.ipmi$g_sen_rf_rsp$r_fill_45_.ipmi$g_se\n_rf_rsp$v_resultQ#define ipmi$g_sen_h_rsp$b_pos ipmi$r_rspu.ipmi$r_g_sh_rsp.ipmi$g_sen_h_rsp$b_posQ#define ipmi$g_sen_h_rsp$b_neg ipmi$r_rspu.ipmi$r_g_sh_rsp.ipmi$g_sen_h_rsp$b_nego#define ipmi$g_sen_th_rsp$b_b2 ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$r_fill_46_.ipmi$g_sen_th_rsp$b_b2#define ipmi$g_sen_th_rsp$v_l_nc_tf ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$r_fill_46_.ipmi$g_sen_th_rsp$r_fill_47_.ipmi$g_s\en_th_rsp$v_l_nc_t'f#define ipmi$g_sen_th_rsp$v_l_c_tf ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$r_fill_46_.ipmi$g_sen_th_rsp$r_fill_47_.ipmi$g_se\n_th_rsp$v_l_c_tf#define ipmi$g_sen_th_rsp$v_l_nr_tf ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$r_fill_46_.ipmi$g_sen_th_rsp$r_fill_47_.ipmi$g_s\en_th_rsp$v_l_nr_tf#define ipmi$g_sen_th_rsp$v_u_nc_tf ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$r_fill_46_.ipmi$g_sen_th_rsp$r_fill_47_.ipmi$g_s\en_th_rsp$v_u_nc_tf#define ipmi$g_sen_th_rsp$v_u_c_tf i'pmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$r_fill_46_.ipmi$g_sen_th_rsp$r_fill_47_.ipmi$g_se\n_th_rsp$v_u_c_tf#define ipmi$g_sen_th_rsp$v_u_nr_tf ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$r_fill_46_.ipmi$g_sen_th_rsp$r_fill_47_.ipmi$g_s\en_th_rsp$v_u_nr_tfb#define ipmi$g_sen_th_rsp$b_l_nc_thres ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$b_l_nc_thres`#define ipmi$g_sen_th_rsp$b_l_c_thres ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$b_l_c_thresb#define ipmi$g_sen_th_rsp$b_l_nr_t'hres ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$b_l_nr_thresb#define ipmi$g_sen_th_rsp$b_u_nc_thres ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$b_u_nc_thres`#define ipmi$g_sen_th_rsp$b_u_c_thres ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$b_u_c_thresb#define ipmi$g_sen_th_rsp$b_u_nr_thres ipmi$r_rspu.ipmi$r_g_sth_rsp.ipmi$g_sen_th_rsp$b_u_nr_threso#define ipmi$g_sen_ee_rsp$b_b2 ipmi$r_rspu.ipmi$r_g_see_rsp.ipmi$g_sen_ee_rsp$r_fill_48_.ipmi$g_sen_ee_rsp$b_b2#define ipmi$g_sen_ee_rsp$v_'rsvd ipmi$r_rspu.ipmi$r_g_see_rsp.ipmi$g_sen_ee_rsp$r_fill_48_.ipmi$g_sen_ee_rsp$r_fill_49_.ipmi$g_sen_\ ee_rsp$v_rsvd#define ipmi$g_sen_ee_rsp$v_scan_dis ipmi$r_rspu.ipmi$r_g_see_rsp.ipmi$g_sen_ee_rsp$r_fill_48_.ipmi$g_sen_ee_rsp$r_fill_49_.ipmi$g_\sen_ee_rsp$v_scan_dis#define ipmi$g_sen_ee_rsp$v_all_dis ipmi$r_rspu.ipmi$r_g_see_rsp.ipmi$g_sen_ee_rsp$r_fill_48_.ipmi$g_sen_ee_rsp$r_fill_49_.ipmi$g_s\en_ee_rsp$v_all_disZ#define ipmi$g_sen_ee_rsp$w_assert ipmi$r_rspu.ipmi$r_g_see_rsp.ipmi$g'_sen_ee_rsp$w_assert^#define ipmi$g_sen_ee_rsp$w_deassert ipmi$r_rspu.ipmi$r_g_see_rsp.ipmi$g_sen_ee_rsp$w_deasserto#define ipmi$g_sen_es_rsp$b_b2 ipmi$r_rspu.ipmi$r_g_ses_rsp.ipmi$g_sen_es_rsp$r_fill_50_.ipmi$g_sen_es_rsp$b_b2#define ipmi$g_sen_es_rsp$v_rsvd ipmi$r_rspu.ipmi$r_g_ses_rsp.ipmi$g_sen_es_rsp$r_fill_50_.ipmi$g_sen_es_rsp$r_fill_51_.ipmi$g_sen_\ es_rsp$v_rsvd#define ipmi$g_sen_es_rsp$v_busy ipmi$r_rspu.ipmi$r_g_ses_rsp.ipmi$g_sen_es_rsp$r_fill_50_.ipmi$g_sen_es_rsp$r_fill_51_.ipmi'$g_sen_\ es_rsp$v_busy#define ipmi$g_sen_es_rsp$v_scan_dis ipmi$r_rspu.ipmi$r_g_ses_rsp.ipmi$g_sen_es_rsp$r_fill_50_.ipmi$g_sen_es_rsp$r_fill_51_.ipmi$g_\sen_es_rsp$v_scan_dis#define ipmi$g_sen_es_rsp$v_all_dis ipmi$r_rspu.ipmi$r_g_ses_rsp.ipmi$g_sen_es_rsp$r_fill_50_.ipmi$g_sen_es_rsp$r_fill_51_.ipmi$g_s\en_es_rsp$v_all_disZ#define ipmi$g_sen_es_rsp$w_assert ipmi$r_rspu.ipmi$r_g_ses_rsp.ipmi$g_sen_es_rsp$w_assert^#define ipmi$g_sen_es_rsp$w_deassert ipmi$r_rspu.ipmi$r_g_ses_rsp.ipmi$g_s'en_es_rsp$w_deassertU#define ipmi$g_sen_r_rsp$b_value ipmi$r_rspu.ipmi$r_g_sr_rsp.ipmi$g_sen_r_rsp$b_valuek#define ipmi$g_sen_r_rsp$b_b3 ipmi$r_rspu.ipmi$r_g_sr_rsp.ipmi$g_sen_r_rsp$r_fill_52_.ipmi$g_sen_r_rsp$b_b3#define ipmi$g_sen_r_rsp$v_rsvd ipmi$r_rspu.ipmi$r_g_sr_rsp.ipmi$g_sen_r_rsp$r_fill_52_.ipmi$g_sen_r_rsp$r_fill_53_.ipmi$g_sen_r_rs\p$v_rsvd#define ipmi$g_sen_r_rsp$v_busy ipmi$r_rspu.ipmi$r_g_sr_rsp.ipmi$g_sen_r_rsp$r_fill_52_.ipmi$g_sen_r_rsp$r_fill_53_.ipmi$g_sen_r_rs\p$v_busy'#define ipmi$g_sen_r_rsp$v_scan_dis ipmi$r_rspu.ipmi$r_g_sr_rsp.ipmi$g_sen_r_rsp$r_fill_52_.ipmi$g_sen_r_rsp$r_fill_53_.ipmi$g_sen_\r_rsp$v_scan_dis#define ipmi$g_sen_r_rsp$v_all_dis ipmi$r_rspu.ipmi$r_g_sr_rsp.ipmi$g_sen_r_rsp$r_fill_52_.ipmi$g_sen_r_rsp$r_fill_53_.ipmi$g_sen_r\_rsp$v_all_disW#define ipmi$g_sen_r_rsp$w_assert ipmi$r_rspu.ipmi$r_g_sr_rsp.ipmi$g_sen_r_rsp$w_assert[#define ipmi$g_sen_r_rsp$w_deassert ipmi$r_rspu.ipmi$r_g_sr_rsp.ipmi$g_sen_r_rsp$w_deassertd#define ipmi$g_sen'_ty_rsp$b_sensor_type ipmi$r_rspu.ipmi$r_g_sty_rsp.ipmi$g_sen_ty_rsp$b_sensor_typeo#define ipmi$g_sen_ty_rsp$b_b3 ipmi$r_rspu.ipmi$r_g_sty_rsp.ipmi$g_sen_ty_rsp$r_fill_54_.ipmi$g_sen_ty_rsp$b_b3#define ipmi$g_sen_ty_rsp$v_event_type ipmi$r_rspu.ipmi$r_g_sty_rsp.ipmi$g_sen_ty_rsp$r_fill_54_.ipmi$g_sen_ty_rsp$r_fill_55_.ipmi$\g_sen_ty_rsp$v_event_type[#define ipmi$gfru_i_rsp$w_area_sze ipmi$r_rspu.ipmi$r_gfru_i_rsp.ipmi$gfru_i_rsp$w_area_szel#define ipmi$gfru_i_rsp$b_flg ipmi$r_rspu.ipmi$r_gfr'u_i_rsp.ipmi$gfru_i_rsp$r_fill_56_.ipmi$gfru_i_rsp$b_flg#define ipmi$gfru_i_rsp$v_wrd_acc ipmi$r_rspu.ipmi$r_gfru_i_rsp.ipmi$gfru_i_rsp$r_fill_56_.ipmi$gfru_i_rsp$r_fill_57_.ipmi$gfru_i_r\ sp$v_wrd_accK#define ipmi$rfru_rsp$b_cnt ipmi$r_rspu.ipmi$r_rfru_rsp.ipmi$rfru_rsp$b_cntM#define ipmi$rfru_rsp$b_data ipmi$r_rspu.ipmi$r_rfru_rsp.ipmi$rfru_rsp$b_datat#define ipmi$gsdr_i_rsp$b_sdr_ver ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$r_fill_58_.ipmi$gsdr_i_rsp$b_sdr_ver#define ipmi$gsdr_i_rsp$'v_sdr_v_major ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$r_fill_58_.ipmi$gsdr_i_rsp$r_fill_59_.ipmi$gsdr\_i_rsp$v_sdr_v_major#define ipmi$gsdr_i_rsp$v_sdr_v_minor ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$r_fill_58_.ipmi$gsdr_i_rsp$r_fill_59_.ipmi$gsdr\_i_rsp$v_sdr_v_minor_#define ipmi$gsdr_i_rsp$w_record_cnt ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$w_record_cnt_#define ipmi$gsdr_i_rsp$w_free_space ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$w_free_space[#define ipmi$gsdr_i_rs'p$l_add_time ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$l_add_time_#define ipmi$gsdr_i_rsp$l_erase_time ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$l_erase_timer#define ipmi$gsdr_i_rsp$b_op_sup ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$r_fill_60_.ipmi$gsdr_i_rsp$b_op_sup#define ipmi$gsdr_i_rsp$v_alloc_info ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$r_fill_60_.ipmi$gsdr_i_rsp$r_fill_61_.ipmi$gsdr_\i_rsp$v_alloc_info#define ipmi$gsdr_i_rsp$v_res ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$g'sdr_i_rsp$r_fill_60_.ipmi$gsdr_i_rsp$r_fill_61_.ipmi$gsdr_i_rsp$v\_res#define ipmi$gsdr_i_rsp$v_p_add ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$r_fill_60_.ipmi$gsdr_i_rsp$r_fill_61_.ipmi$gsdr_i_rsp\$v_p_add#define ipmi$gsdr_i_rsp$v_del ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$r_fill_60_.ipmi$gsdr_i_rsp$r_fill_61_.ipmi$gsdr_i_rsp$v\_del#define ipmi$gsdr_i_rsp$v_nonmodal ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$r_fill_60_.ipmi$gsdr_i_rsp$r_fill_61_.ipmi$gsdr_i_\rsp$v_nonmodal'#define ipmi$gsdr_i_rsp$v_modal ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$r_fill_60_.ipmi$gsdr_i_rsp$r_fill_61_.ipmi$gsdr_i_rsp\$v_modal#define ipmi$gsdr_i_rsp$v_ovr ipmi$r_rspu.ipmi$r_gsdr_i_rsp.ipmi$gsdr_i_rsp$r_fill_60_.ipmi$gsdr_i_rsp$r_fill_61_.ipmi$gsdr_i_rsp$v\_ovrU#define ipmi$gsdr_a_rsp$w_alloc ipmi$r_rspu.ipmi$r_gsdr_a_rsp.ipmi$gsdr_a_rsp$w_alloc]#define ipmi$gsdr_a_rsp$w_unit_size ipmi$r_rspu.ipmi$r_gsdr_a_rsp.ipmi$gsdr_a_rsp$w_unit_sizeY#define ipmi$gsdr_a_rsp$w_f_units ip(mi$r_rspu.ipmi$r_gsdr_a_rsp.ipmi$gsdr_a_rsp$w_f_unitsY#define ipmi$gsdr_a_rsp$w_f_block ipmi$r_rspu.ipmi$r_gsdr_a_rsp.ipmi$gsdr_a_rsp$w_f_block[#define ipmi$gsdr_a_rsp$b_max_size ipmi$r_rspu.ipmi$r_gsdr_a_rsp.ipmi$gsdr_a_rsp$b_max_size]#define ipmi$ressdr_r_rsp$w_res_id ipmi$r_rspu.ipmi$r_ressdr_r_rsp.ipmi$ressdr_r_rsp$w_res_idQ#define ipmi$gsdr_rsp$w_rec_id ipmi$r_rspu.ipmi$r_gsdr_rsp.ipmi$gsdr_rsp$w_rec_idM#define ipmi$gsdr_rsp$b_data ipmi$r_rspu.ipmi$r_gsdr_rsp.ipmi$gsdr_rsp$b_dataS#def(ine ipmi$gsdr_t_rsp$l_time ipmi$r_rspu.ipmi$r_gsdr_t_rsp.ipmi$gsdr_t_rsp$l_timet#define ipmi$gsel_i_rsp$b_sel_ver ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$r_fill_62_.ipmi$gsel_i_rsp$b_sel_ver#define ipmi$gsel_i_rsp$v_sel_v_major ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$r_fill_62_.ipmi$gsel_i_rsp$r_fill_63_.ipmi$gsel\_i_rsp$v_sel_v_major#define ipmi$gsel_i_rsp$v_sel_v_minor ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$r_fill_62_.ipmi$gsel_i_rsp$r_fill_63_.ipmi$gsel\_i_rsp$v_sel_v_m(inor]#define ipmi$gsel_i_rsp$w_entry_cnt ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$w_entry_cnt_#define ipmi$gsel_i_rsp$w_free_space ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$w_free_space[#define ipmi$gsel_i_rsp$l_add_time ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$l_add_time_#define ipmi$gsel_i_rsp$l_erase_time ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$l_erase_timer#define ipmi$gsel_i_rsp$b_op_sup ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$r_fill_64_.ipmi$gsel_i_rsp$b_op_sup(#define ipmi$gsel_i_rsp$v_alloc_info ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$r_fill_64_.ipmi$gsel_i_rsp$r_fill_65_.ipmi$gsel_\i_rsp$v_alloc_info#define ipmi$gsel_i_rsp$v_res ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$r_fill_64_.ipmi$gsel_i_rsp$r_fill_65_.ipmi$gsel_i_rsp$v\_res#define ipmi$gsel_i_rsp$v_p_add ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$r_fill_64_.ipmi$gsel_i_rsp$r_fill_65_.ipmi$gsel_i_rsp\$v_p_add#define ipmi$gsel_i_rsp$v_del ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$g(sel_i_rsp$r_fill_64_.ipmi$gsel_i_rsp$r_fill_65_.ipmi$gsel_i_rsp$v\_del#define ipmi$gsel_i_rsp$v_ovr ipmi$r_rspu.ipmi$r_gsel_i_rsp.ipmi$gsel_i_rsp$r_fill_64_.ipmi$gsel_i_rsp$r_fill_65_.ipmi$gsel_i_rsp$v\_ovra#define ipmi$gsel_a_rsp$w_alloc_units ipmi$r_rspu.ipmi$r_gsel_a_rsp.ipmi$gsel_a_rsp$w_alloc_units]#define ipmi$gsel_a_rsp$w_unit_size ipmi$r_rspu.ipmi$r_gsel_a_rsp.ipmi$gsel_a_rsp$w_unit_sizeY#define ipmi$gsel_a_rsp$w_f_units ipmi$r_rspu.ipmi$r_gsel_a_rsp.ipmi$gsel_a_rsp$w_f_unitsY#def(ine ipmi$gsel_a_rsp$w_f_block ipmi$r_rspu.ipmi$r_gsel_a_rsp.ipmi$gsel_a_rsp$w_f_block[#define ipmi$gsel_a_rsp$b_max_size ipmi$r_rspu.ipmi$r_gsel_a_rsp.ipmi$gsel_a_rsp$b_max_sizeW#define ipmi$ressel_rsp$w_res_id ipmi$r_rspu.ipmi$r_ressel_rsp.ipmi$ressel_rsp$w_res_idQ#define ipmi$gsel_rsp$w_rec_id ipmi$r_rspu.ipmi$r_gsel_rsp.ipmi$gsel_rsp$w_rec_idM#define ipmi$gsel_rsp$b_data ipmi$r_rspu.ipmi$r_gsel_rsp.ipmi$gsel_rsp$b_dataQ#define ipmi$asel_rsp$w_rec_id ipmi$r_rspu.ipmi$r_asel_rsp.ipmi$asel_r(sp$w_rec_idQ#define ipmi$dsel_rsp$w_rec_id ipmi$r_rspu.ipmi$r_dsel_rsp.ipmi$dsel_rsp$w_rec_id#define ipmi$csel_rsp$v_e_prgress ipmi$r_rspu.ipmi$r_csel_rsp.ipmi$csel_rsp$r_fill_66_.ipmi$csel_rsp$r_fill_67_.ipmi$csel_rsp$v_e_p\rgressS#define ipmi$gsel_t_rsp$l_time ipmi$r_rspu.ipmi$r_gsel_t_rsp.ipmi$gsel_t_rsp$l_timet#define ipmi$gtoken_i_rsp$b_attr ipmi$r_rspu.ipmi$r_gtkn_i_rsp.ipmi$gtoken_i_rsp$r_fill_68_.ipmi$gtoken_i_rsp$b_attr#define ipmi$gtoken_i_rsp$v_r_guest ipmi$r_rspu.ipmi$r_gtkn_i_(rsp.ipmi$gtoken_i_rsp$r_fill_68_.ipmi$gtoken_i_rsp$r_fill_69_.ipmi$gt\oken_i_rsp$v_r_guest#define ipmi$gtoken_i_rsp$v_r_user ipmi$r_rspu.ipmi$r_gtkn_i_rsp.ipmi$gtoken_i_rsp$r_fill_68_.ipmi$gtoken_i_rsp$r_fill_69_.ipmi$gto\ken_i_rsp$v_r_user#define ipmi$gtoken_i_rsp$v_r_admin ipmi$r_rspu.ipmi$r_gtkn_i_rsp.ipmi$gtoken_i_rsp$r_fill_68_.ipmi$gtoken_i_rsp$r_fill_69_.ipmi$gt\oken_i_rsp$v_r_admin#define ipmi$gtoken_i_rsp$v_w_guest ipmi$r_rspu.ipmi$r_gtkn_i_rsp.ipmi$gtoken_i_rsp$r_fill_68_.ipmi$gt(oken_i_rsp$r_fill_69_.ipmi$gt\oken_i_rsp$v_w_guest#define ipmi$gtoken_i_rsp$v_w_user ipmi$r_rspu.ipmi$r_gtkn_i_rsp.ipmi$gtoken_i_rsp$r_fill_68_.ipmi$gtoken_i_rsp$r_fill_69_.ipmi$gto\ken_i_rsp$v_w_user#define ipmi$gtoken_i_rsp$v_w_admin ipmi$r_rspu.ipmi$r_gtkn_i_rsp.ipmi$gtoken_i_rsp$r_fill_68_.ipmi$gtoken_i_rsp$r_fill_69_.ipmi$gt\oken_i_rsp$v_w_admin#define ipmi$gtoken_i_rsp$v_checksum ipmi$r_rspu.ipmi$r_gtkn_i_rsp.ipmi$gtoken_i_rsp$r_fill_68_.ipmi$gtoken_i_rsp$r_fill_69_.ipmi$g\token_i_ (rsp$v_checksum#define ipmi$gtoken_i_rsp$v_e_info ipmi$r_rspu.ipmi$r_gtkn_i_rsp.ipmi$gtoken_i_rsp$r_fill_68_.ipmi$gtoken_i_rsp$r_fill_69_.ipmi$gto\ken_i_rsp$v_e_infoQ#define ipmi$rtoken_rsp$b_data ipmi$r_rspu.ipmi$r_rtkn_rsp.ipmi$rtoken_rsp$b_dataV#define ipmi$p_rtoken_rsp$b_data ipmi$r_rspu.ipmi$r_prtkn_rsp.ipmi$p_rtoken_rsp$b_dataR#define ipmi$l_prop_rsp$l_lock ipmi$r_rspu.ipmi$r_lprop_rsp.ipmi$l_prop_rsp$l_lock\#define ipmi$l_prop_rsp$l_lock_time ipmi$r_rspu.ipmi$r_lprop_rsp.ipmi$l_prop_rsp ($l_lock_timeT#define ipmi$l_prop_rsp$b_sw_id ipmi$r_rspu.ipmi$r_lprop_rsp.ipmi$l_prop_rsp$b_sw_idP#define ipmi$g_prop_rsp$w_cnt ipmi$r_rspu.ipmi$r_gprop_rsp.ipmi$g_prop_rsp$w_cntR#define ipmi$g_prop_rsp$b_data ipmi$r_rspu.ipmi$r_gprop_rsp.ipmi$g_prop_rsp$b_data"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* +  ( */N/* IPMI IMB command codes */N/* - */N/* */N#define IPMI$K_CMD_G_DEVICE_ID 1 /* Get device ID command */N#define IPMI$K_CMD_COLD_RESET 2 /* Cold reset (unsupported) */N#define IPMI$K_CMD_WARM_RESET 3 /* Warm reset (unsupported () */N#define IPMI$K_CMD_G_SELFTEST 4 /* Get selftest results */Q#define IPMI$K_CMD_MFG_ON 5 /* Manufacturing Test on (unsupported) */N#define IPMI$K_CMD_S_ACPI_POWER 6 /* Set acpi power state */N#define IPMI$K_CMD_G_ACPI_POWER 7 /* Get acpi power state */N#define IPMI$K_CMD_G_DEVICE_GUID 8 /* Get device guid */P#define IPMI$K_CMD_R_WATCHDOG 34 /* Reset Watchdog timer (unsupported) */N#defin (e IPMI$K_CMD_S_WATCHDOG 36 /* Set Watchdog timer (unsupported) */N#define IPMI$K_CMD_G_WATCHDOG 37 /* Get Watchdog timer */N#define IPMI$K_CMD_G_BT_CAPABILITY 54 /* Get bt capability */N#define IPMI$K_CMD_G_SYSTEM_GUID 55 /* Get system guid */N#define IPMI$K_CMD_G_CHASSIS_CAPA 0 /* Get chassis capability */N#define IPMI$K_CMD_G_CHASSIS_STAT 1 /* Get chassis status */N#define IPMI$K_CMD_CHASSIS_CTRL (2 /* Chassis control */N#define IPMI$K_CMD_CHASSIS_RESET 3 /* Chassis reset (obsolete) */N#define IPMI$K_CMD_CHAS_ID 4 /* Chassis Identify command */N#define IPMI$K_CMD_S_EVENT_RCVR 0 /* Set event receiver */N#define IPMI$K_CMD_G_EVENT_RCVR 1 /* Get event receiver */O#define IPMI$K_CMD_PLATFORM_EVENT 2 /* Platform event or event messenger */N#define IPMI$K_CMD_G_DEV_SDR_INFO 32 /* Get Device SD(R info */N#define IPMI$K_CMD_G_DEV_SDR 33 /* Get Device SDR */N#define IPMI$K_CMD_RES_DEV_SDR_REPOS 34 /* Reserve Device SDR repository */N#define IPMI$K_CMD_G_SENSOR_READ_FAC 35 /* Get sensor reading factors */N#define IPMI$K_CMD_S_SENSOR_HYSTER 36 /* Set sensor hysteresis */N#define IPMI$K_CMD_G_SENSOR_HYSTER 37 /* Get sensor hysteresis */N#define IPMI$K_CMD_S_SENSOR_THRES 38 /* Set sensor threshold */N#d(efine IPMI$K_CMD_G_SENSOR_THRES 39 /* Get sensor threshold */N#define IPMI$K_CMD_S_SENSOR_EVENT_ENA 40 /* Set sensor event enable */N#define IPMI$K_CMD_G_SENSOR_EVENT_ENA 41 /* Get sensor event enable */N#define IPMI$K_CMD_RARM_SENSOR_EVENT 42 /* Re-arm sensor events */N#define IPMI$K_CMD_G_SENSOR_EVENT_STAT 43 /* Get sensor event status */N#define IPMI$K_CMD_G_SENSOR_READING 45 /* Get sensor reading */N#define IPMI$K_CMD_S_SENSOR_(TYPE 46 /* Set sensor type */N#define IPMI$K_CMD_G_SENSOR_TYPE 47 /* Get sensor type */N#define IPMI$K_CMD_G_FRU_INV 16 /* Get FRU Inventory Area command */N#define IPMI$K_CMD_READ_FRU 17 /* Read FRU data command */N#define IPMI$K_CMD_G_SDR_REPOS_INFO 32 /* Get SDR repository info */P#define IPMI$K_CMD_G_SDR_REPOS_ALLOC 33 /* Get SDR repository allocation info */N#define IPMI$K_CMD_RES_SDR_REPOS 34 /* Reserve S(DR repository */N#define IPMI$K_CMD_G_SDR_ENTRY 35 /* Get SDR entry command */N#define IPMI$K_CMD_G_SDR_REPOS_TIME 40 /* Get SDR repository Time */N#define IPMI$K_CMD_G_SEL_INFO 64 /* Get SEL info */N#define IPMI$K_CMD_G_SEL_ALLOC_INFO 65 /* Get SEL allocation info */N#define IPMI$K_CMD_RES_SEL 66 /* Reserve SEL */N#define IPMI$K_CMD_G_SEL_ENTRY 67 /* Get SEL entry command */(N#define IPMI$K_CMD_A_SEL_ENTRY 68 /* Add SEL entry command */N#define IPMI$K_CMD_DEL_SEL_ENTRY 70 /* delete SEL entry command */N#define IPMI$K_CMD_CLEAR_SEL 71 /* Clear SEL command */N#define IPMI$K_CMD_G_SEL_TIME 72 /* Get SEL time */N#define IPMI$K_CMD_S_SEL_TIME 73 /* Set SEL time */N#define IPMI$K_CMD_A_FPL_ENTRY 196 /* Add FPL entry command */N#define IPMI$K_CMD_GET_T(OKEN_INFO 1 /* Get Token Info command */N#define IPMI$K_CMD_READ_TOKEN 2 /* Read Token command */N#define IPMI$K_CMD_PART_READ_TOKEN 8 /* Partial Read Token command */N#define IPMI$K_CMD_LOCK_PROPERTY 0 /* Lock Property command */N#define IPMI$K_CMD_UNLOCK_PROPERTY 1 /* Unlock Property command */N#define IPMI$K_CMD_GET_PROPERTY 2 /* Get Property command */N/* ( */N/* */N/* + */N/* IPMI IMB Completion Codes */N/* - */N/* These are the generic Completion codes. Codes specific to a */N/* message are listed below. (*/N/* */N#define IPMI$K_CCODE_OK 0 /* Good response */N#define IPMI$K_CCODE_NO_DATA 128 /* No data */N#define IPMI$K_CCODE_BUSY 192 /* device is busy */$#define IPMI$K_CCODE_CMD_INVALID 193(#define IPMI$K_CCODE_CMD_LUN_INVALID 194 #define IPMI$K_CCODE_TIMEOUT 195 #define IPMI$K_CCODE_NOSPACE 196"#define IPMI$K_CCODE_RESID_BAD 197 (##define IPMI$K_CCODE_DATA_TRUNC 198(#define IPMI$K_CCODE_DATALEN_INVALID 199'#define IPMI$K_CCODE_DATALEN_EXCEED 200(#define IPMI$K_CCODE_PARAM_BAD_RANGE 201%#define IPMI$K_CCODE_DATA_BAD_RET 202$#define IPMI$K_CCODE_OBJ_NOEXIST 203*#define IPMI$K_CCODE_DATAFIELD_INVALID 204(#define IPMI$K_CCODE_CMD_OBJ_INVALID 205$#define IPMI$K_CCODE_NO_RESPONSE 206$#define IPMI$K_CCODE_DUP_REQUEST 207(#define IPMI$K_CCODE_SDR_NO_RESPONSE 208'#define IPMI$K_CCODE_FW_NO_RESPONSE 209)#define IPMI$K_C (CODE_INIT_NO_RESPONSE 210 #define IPMI$K_CCODE_NO_DEST 211 #define IPMI$K_CCODE_NO_PRIV 212(#define IPMI$K_CCODE_NOSUPPORT_STATE 213!#define IPMI$K_CCODE_DISABLED 214N#define IPMI$K_CCODE_UNKNOWN 255 /* Unknown Completion code */N/* */N/* */N/* Specific Completion codes */N/* ( */N#define IPMI$K_CCODE_TOKEN_BAD_CHKSUM 112 /* Invalid Token checksum */N#define IPMI$K_CCODE_FRU_BUSY 129 /* FRU device is busy */[#define IPMI$K_CCODE_SEL_ERASING 129 /* Cannot execute command, SEL erase in progress */N#define IPMI$K_CCODE_SEL_NOSUPPORT 128 /* SEL Option not supported */N/* */N/* ( */N/* */N/* */N/* + */N/* These are the QIO IOCTL commands that the IPMI driver supports */N/* - */N/* ( */)#define IPMI$K_IOCTL_SEND_MESSAGE_CMD 100)#define IPMI$K_IOCTL_IPMI_VERSION_CMD 101N/* */N/* + */N/* IPMI Slave Address */N/* - */N/* ( */N#define IPMI$K_BMC_SA 32 /* BMC slave address */T#define IPMI$K_MP_SA 70 /* MP slave address (foundation systems) */N/* */N/* + */N/* The Logical Unit Number LUN. This is a sub-address that allows */N/* messages to be routed to different "logical units" that reside */N/* behin(d the same I2C slave address. */N/* - */N/* */N#define IPMI$K_BMC_LUN 0 /* BMC only responds to this LUN */N#define IPMI$K_OEM1_LUN 1 /* OEM1 defined LUN */N#define IPMI$K_SMS_LUN 2 /* BMC forwards to SMS buffer */N#define IPMI$K_OEM2_LUN 3 ( /* OEM2 defined LUN */N/* */N/* + */N/* IPMI Network Function Codes. */N/* The network function is used to cluster commands into functional */N/* command sets. In a parsing hierarchy, the LUN field may be thought */N/* of as the selector for a particular Network Function hand (ler in */N/* the node, and the Network Function may be considered the selector */N/* for a particular command set handler within the node. */N/* - */N/* */#define IPMI$K_CHASSIS_NETFN 0#define IPMI$K_BRIDGE_NETFN 2#define IPMI$K_SE_NETFN 4#define IPMI$K_APP_NETFN 6#define IPMI$K_FIRMWARE_NETFN 8#define IPMI ($K_STORAGE_NETFN 10!#define IPMI$K_TRANSPORT_NETFN 12#define IPMI$K_OEM30_NETFN 48#define IPMI$K_OEM32_NETFN 50#define IPMI$K_OEM34_NETFN 52N/* */N/* + */N/* IPMI versions that we support and see. */N/* - */N/* !( */#define IPMI$K_VERSION_1_0 1#define IPMI$K_VERSION_1_5 81#define IPMI$K_VERSION_2_0 2"#define IPMI$K_VERSION_UNKNOWN 255N/* */N/* + */N/* IPMI Event structures. */N/* The event IDs are allocated in the CCODE event database */N/* at http"(://callahan.rose.hp.com/FMT/eventdb/index.html */N/* Other constants here are defined in "Event Architecture */N/* Specification" Revision 1.70 (6/23/05) or later. */N/* - */N/* */"#define IPMI$E0$M_EVENT_ID 0x3FFFFN#define IPMI$E0$K_OS_BOOT_COMPLETE 5857 /* See CCODE event database */N #(#define IPMI$E0$K_OS_OPENVMS_BUGCHECK 7319 /* See CCODE event database */N#define IPMI$E0$K_OS_OPENVMS_SHUTDOWN 7321 /* See CCODE event database */ #define IPMI$E0$M_RSVD1 0x7C0000##define IPMI$E0$M_TIME_FLG 0x800000&#define IPMI$E0$M_DATA_TYPE 0x1F000000N#define IPMI$E0$K_MAJOR_CHANGE 20 /* Major change in system state */&#define IPMI$E0$M_ALERT_LVL 0xE0000000N#define IPMI$E0$K_MINOR_FORWARD 0 /* Minor forward progress */N#define IPMI$E0$K_MAJOR_FORWARD 1 $( /* Major forward progress */U#define IPMI$E0$K_INFORMATIONAL 2 /* Informational event (VMS boot/shutdown) */N#define IPMI$E0$K_WARNING 3 /* Warning (non-critical error) */N#define IPMI$E0$K_CRITICAL 5 /* Critical (VMS system crash) */N#define IPMI$E0$K_FATAL 7 /* Fatal */"#define IPMI$E0$M_SYSTEM_STATE 0xFN#define IPMI$E0$K_BOOT_COMPLETE 1 /* Boot complete */N#define IPMI$E0$ %(K_STATE_CHANGE 12 /* State change */$#define IPMI$E0$M_LEDS_COMMAND 0x3F0#define IPMI$E0$M_LCV 0x400#define IPMI$E0$M_FLAGS 0x3800#define IPMI$E0$M_RSVD2 0xC000R#define IPMI$E0$K_CRITICAL_SHUTDOWN 25 /* Critical shutdown (VMS system crash) */U#define IPMI$E0$K_SHUTDOWN 26 /* Normal shutdown (VMS operator shutdown) */N#define IPMI$E0$K_LENGTH 16 /* total length of e0 event struct */ typedef struct _e0_event {N unsigned short int ipm &(i$e0$w_rec_id; /* Record ID for the E0 record */N unsigned char ipmi$e0$b_rec_type; /* Record Type "E0 hex" */N unsigned char ipmi$e0$b_report_id; /* Reporting Entity ID */ __union {$ unsigned int ipmi$e0$l_misc; __struct {N unsigned ipmi$e0$v_event_id : 18; /* Event ID */N unsigned ipmi$e0$v_rsvd1 : 5; /* Reserved */N unsigned ipmi$e0$v_time_flg : 1; /* Timestam '(p flag */N unsigned ipmi$e0$v_data_type : 5; /* Event Data type */N unsigned ipmi$e0$v_alert_lvl : 3; /* Alert level */! } ipmi$e0$r_fill_79_; } ipmi$e0$r_fill_78_; __union {N unsigned __int64 ipmi$e0$q_data; /* Event data */ __struct {N unsigned ipmi$e0$v_system_state : 4; /* System state */N unsigned ipmi$e0$v_leds_command : 6; /* Depr((ecated */N unsigned ipmi$e0$v_lcv : 1; /* Deprecated */N unsigned ipmi$e0$v_flags : 3; /* nPar vs. cell */N unsigned ipmi$e0$v_rsvd2 : 2; /* Reserved */N unsigned char ipmi$e0$b_state_change; /* State change event */X unsigned char ipmi$e0$b_addnl_type; /* Additional change information type */R unsigned int ipmi$e0$l_addnl_info; /* Additional change info )(rmation */! } ipmi$e0$r_fill_81_; } ipmi$e0$r_fill_80_; } E0_EVENT; #if !defined(__VAXC)S#define ipmi$e0$v_event_id ipmi$e0$r_fill_78_.ipmi$e0$r_fill_79_.ipmi$e0$v_event_idS#define ipmi$e0$v_time_flg ipmi$e0$r_fill_78_.ipmi$e0$r_fill_79_.ipmi$e0$v_time_flgU#define ipmi$e0$v_data_type ipmi$e0$r_fill_78_.ipmi$e0$r_fill_79_.ipmi$e0$v_data_typeU#define ipmi$e0$v_alert_lvl ipmi$e0$r_fill_78_.ipmi$e0$r_fill_79_.ipmi$e0$v_alert_lvl[#define ipmi$e0$v_system_state ipm*(i$e0$r_fill_80_.ipmi$e0$r_fill_81_.ipmi$e0$v_system_state[#define ipmi$e0$v_leds_command ipmi$e0$r_fill_80_.ipmi$e0$r_fill_81_.ipmi$e0$v_leds_commandI#define ipmi$e0$v_lcv ipmi$e0$r_fill_80_.ipmi$e0$r_fill_81_.ipmi$e0$v_lcvM#define ipmi$e0$v_flags ipmi$e0$r_fill_80_.ipmi$e0$r_fill_81_.ipmi$e0$v_flags[#define ipmi$e0$b_state_change ipmi$e0$r_fill_80_.ipmi$e0$r_fill_81_.ipmi$e0$b_state_changeW#define ipmi$e0$b_addnl_type ipmi$e0$r_fill_80_.ipmi$e0$r_fill_81_.ipmi$e0$b_addnl_typeW#define ipmi +($e0$l_addnl_info ipmi$e0$r_fill_80_.ipmi$e0$r_fill_81_.ipmi$e0$l_addnl_info"#endif /* #if !defined(__VAXC) */ !#define IPMI$T2$M_EVENT_TYPE 0x7F #define IPMI$T2$M_EVENT_DIR 0x80Q#define IPMI$T2$K_LENGTH 16 /* total length of Type 2 event struct */ typedef struct _t2_event {N unsigned short int ipmi$t2$w_rec_id; /* Record ID for the Type 2 record */N unsigned char ipmi$t2$b_rec_type; /* Record Type "02 hex" */N unsigned int ipmi$t2$l_time; /* ,( Timestamp */N unsigned short int ipmi$t2$w_generate_id; /* Generator ID */N unsigned char ipmi$t2$b_rev; /* Event message format rev */N unsigned char ipmi$t2$b_sensor_type; /* Sensor Type */N unsigned char ipmi$t2$b_sensor_num; /* Sensor number */ __union {' unsigned char ipmi$t2$b_ev_t_d; __struct {N unsigned ipmi$t2$v_event_type : 7; /* Event type -( */N unsigned ipmi$t2$v_event_dir : 1; /* Event direction */! } ipmi$t2$r_fill_83_; } ipmi$t2$r_fill_82_;N unsigned char ipmi$t2$b_data1; /* Event data 1 */N unsigned char ipmi$t2$b_data2; /* Event data 2 */N unsigned char ipmi$t2$b_data3; /* Event data 3 */ } T2_EVENT; #if !defined(__VAXC)W#define ipmi$t2$v_event_type ipmi$t2$r_fill_82_.ipmi$t2$r_fill .(_83_.ipmi$t2$v_event_typeU#define ipmi$t2$v_event_dir ipmi$t2$r_fill_82_.ipmi$t2$r_fill_83_.ipmi$t2$v_event_dir"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Flags for Send/Get Messages for bridge IPMI commands */N/* */%#define IPMI$K_USE_SEND_MSG_CM /(D 65536%#define IPMI$K_USE_GET_MSG_CMD 131072N/* */N/* Flag for Satellite controller Support on Kauai Systems */N/* */'#define IPMI$K_SEND_TO_SAT_CNTRL 262144N/* */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever0( ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IPMIDEF_LOADED */ wwON[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** li1(censed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software license2(d by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************* 3(***********************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */I/* Source: 09-JUN-1993 15:42:57 $1$DGA8345:[LIB_H.SRC]RMSFILSTR.SDL;1 *//********************************************************************************************************************************//*** MODULE $IRCDEF ***/#ifndef __IRCDEF_LOADED#define __IRCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#p4(ragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_param5(s ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* index record definition */N/* 6( */N/* this is the definition of RMS-11/RMS-32 index file record formats */N/* */#define IRC$M_PTRSZ 0x3#define IRC$M_RECORDCB 0xFC#define IRC$M_DELETED 0x4#define IRC$M_NOPTRSZ 0x10#define IRC$M_FIRST_KEY 0x80#define IRC$M_RRV 0x8#define IRC$M_NODUPCNT 0x10#define IRC$M_RU_DELETE 0x20#define IRC$M_RU_UPDATE 0x40Y#define IRC$C_IDXPTRBAS 2 /* used to determine size of pointer in inde 7(x */N#define IRC$C_IDXOVHDSZ 1 /* includes record control byte */N/* */N#define IRC$S_IRCDEF 1 /* Old size name - synonym */ typedef struct _irc { __union {N unsigned char irc$b_control; /* record control byte */ __struct {N unsigned irc$v_ptrsz : 2; /* size of pointer */N unsigned irc$v_recor8(dcb : 6; /* record control bits */" } irc$r_control_bits0;N/* */Q/* record control bits used only in primary data record and SIDR array element */N/* control bytes */N/* */ __struct {N unsigned irc$$_fill_1 : 2; /* skip size of pointer field 9(*/N unsigned irc$v_deleted : 1; /* record is deleted */& unsigned irc$$_fill_2 : 1;N unsigned irc$v_noptrsz : 1; /* no RRV */N unsigned irc$$_fill_3 : 2; /* skip 2 bits */) unsigned irc$v_first_key : 1;" } irc$r_control_bits1;N/* */N/* record control bits used only in primary data record contro :(l bytes */N/* */ __struct {N unsigned irc$$_fill_3 : 3; /* skip over first 3 bits */N unsigned irc$v_rrv : 1; /* rrv record */' unsigned irc$v_fill_5_ : 4;" } irc$r_control_bits2;N/* */N/* record control bits used only in prologue 2 SIDR record control b ;(ytes */N/* */ __struct {N unsigned irc$$_fill_5 : 4; /* skip 4 bits */N unsigned irc$v_nodupcnt : 1; /* DUP_CNT field absent */' unsigned irc$v_fill_6_ : 3;" } irc$r_control_bits3;N/* */R/* record control bits used only in prologue 3 RRV, UDR and SIDR record co<(ntrol */P/* bytes of RU journalled files. (RU_UPDATE is set only in UDR record control */N/* bytes) */N/* */ __struct {N unsigned irc$$_fill_6 : 5; /* skip 5 bits */N unsigned irc$v_ru_delete : 1; /* record is RU deleted */N unsigned irc$v_ru_update : 1; /* record is RU updated =( */' unsigned irc$v_fill_7_ : 1;" } irc$r_control_bits4;N/* */S/* record control bits reserved for RMS-11 use only (these may not be re-defined */N/* except for prologue 3 records) */N/* */N/* Bit number 5 */N/* Bit number >(6 */N/* */N/* */N/* index bucket record */N/* */ __struct { char irc$$_fill_7;#if defined(__VAXC)# char irc$t_bucketptr[];#else ?(V/* Warning: empty char[] member for irc$t_bucketptr at end of structure not created */"#endif /* #if defined(__VAXC) */N/* just present for consistency) */N/* data bucket record */N/* */$ } irc$r_control_fields4; } irc$r_record_control; } IRC; #if !defined(__VAXC)8#define irc$b_control irc$r_re @(cord_control.irc$b_controlD#define irc$r_control_bits0 irc$r_record_control.irc$r_control_bits03#define irc$v_ptrsz irc$r_control_bits0.irc$v_ptrsz9#define irc$v_recordcb irc$r_control_bits0.irc$v_recordcbD#define irc$r_control_bits1 irc$r_record_control.irc$r_control_bits17#define irc$v_deleted irc$r_control_bits1.irc$v_deleted7#define irc$v_noptrsz irc$r_control_bits1.irc$v_noptrsz;#define irc$v_first_key irc$r_control_bits1.irc$v_first_keyD#define irc$r_control_bits2 irc$r_record_contr A(ol.irc$r_control_bits2/#define irc$v_rrv irc$r_control_bits2.irc$v_rrvD#define irc$r_control_bits3 irc$r_record_control.irc$r_control_bits39#define irc$v_nodupcnt irc$r_control_bits3.irc$v_nodupcntD#define irc$r_control_bits4 irc$r_record_control.irc$r_control_bits4;#define irc$v_ru_delete irc$r_control_bits4.irc$v_ru_delete;#define irc$v_ru_update irc$r_control_bits4.irc$v_ru_updateH#define irc$r_control_fields4 irc$r_record_control.irc$r_control_fields4=#define irc$t_bucketptr irc$r_cont B(rol_fields4.irc$t_bucketptr"#endif /* #if !defined(__VAXC) */ N#define IRC$S_IRCDEF1 3 /* Old size name - synonym */ typedef struct _irc1 { IRC irc$r_irc;N unsigned char irc$b_id; /* record id */S unsigned char irc$b_rrv_id; /* rrv's id -- always in the same place */N/* */N/* prologue 3 data bucket record C( */N/* */ } IRC1;\#define IRC$C_DATSZFLD 2 /* size of size field in variable length records */[#define IRC$C_DATPTRBAS 3 /* used to determine size of RRV in data buckets */Z#define IRC$C_DCNTSZFLD 4 /* size of duplicate count field in Plg 2 SIDRs */[#define IRC$C_DATOVHDSZ 2 /* includes the record control byte, and the id */S#define IRC$C_FIXOVHD(DSZ 7 /* the record overhead for fixed record */S#define IRC$C_VAROVHDSZ 9 /* record overhead for variable records */N#define IRC$C_RRVOVHDSZ 7 /* size of RRV */N/* */\#define IRC$C_DATPTRBS3 4 /* used to determine size of RRV in data buckets */N#define IRC$C_DATOVHSZ3 3 /* record control byte, and id */V#define IRC$C_FIXOVHE(SZ3 9 /* record overhead for fixed length records */Y#define IRC$C_VAROVHSZ3 11 /* record overhead for variable length records */N#define IRC$C_RRVOVHSZ3 9 /* size of RRV */N#define IRC$C_SDROVHSZ3 2 /* record overhead for SIDRs */N#define IRC$C_KEYCMPOVH 2 /* key compression overhead */N#define IRC$C_DATCMPOVH 3 /* data compression overhead */N#define IRC$S_IRCDEF2 5 F( /* Old size name - synonym */ typedef struct _irc2 { IRC irc$r_irc;N unsigned short int irc$w_id; /* record id */S unsigned short int irc$w_rrv_id; /* rrv's id -- always in the same place */N/* */N/* constants */N/* */G(N/* prologue 3 constants */N/* */ } IRC2; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IRCDEF_LOADED */ w H(wN[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** I( 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS SoftwJ(are, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:18 by OpenVMS SDL V3.7 */F/* Source: 24-JUL-2023 11:46:15 $1$DGA8345:[LIB_H.SRC]IRPDEF.SDL;1 *//*************************** K(*****************************************************************************************************//*** MODULE $IRPDEF ***/#ifndef __IRPDEF_LOADED#define __IRPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[L(#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union varian M(t_union#endif#endif N/*+ */N/* IRP - I/O REQUEST PACKET */N/* */N/* I/O REQUEST PACKETS ARE CONSTRUCTED BY THE QUEUE I/O REQUEST SYSTEM */N/* SERVICE. THE CONTENT OF AN I/O REQUEST PACKET DESCRIBES A FUNCTION TO */N/* BE PERFORMED ON A DEVICE UNIT. N(*/N/* */N/* NOTE: Several fields of the IRP must be at the same offsets as their */N/* corresponding fields in the IRPE and CDRP. The equivalency of these */N/* offsets is verified by ASSUME statements in the [LIB]VFY_IRP_A_LIKES.MAR */N/* module. These ASSUMEs may need to be altered as well whenever an IRP */N/* field is removed or altered. */N/*- O( */  O#include /* Define the IOBD type; IRP contains an embedded IOBD */#define IRP$M_WLE_REUSE 0x1#define IRP$M_WLE_SUPWL 0x2!#define IRP$M_WLE_READ_CONTID 0x4"#define IRP$M_WLE_WROTE_CONTID 0x8#define IRP$M_HIST_LOGGED 0x10#define IRP$M_ALLO_FAIL 0x20#define IRP$M_HIST_LOST 0x40#define IRP$M_TABFU 0x80#define IRP$M_BUFIO 0x1#define IRP$M_FUNC 0x2#define IRP$M_PAGIO 0x4#define IRP$M_COMPLX 0x8#definP(e IRP$M_VIRTUAL 0x10#define IRP$M_CHAINED 0x20#define IRP$M_SWAPIO 0x40#define IRP$M_DIAGBUF 0x80#define IRP$M_PHYSIO 0x100#define IRP$M_TERMIO 0x200#define IRP$M_MBXIO 0x400#define IRP$M_EXTEND 0x800#define IRP$M_FILACP 0x1000#define IRP$M_MVIRP 0x2000#define IRP$M_SRVIO 0x4000"#define IRP$M_CCB_LOOKED_UP 0x8000!#define IRP$M_CACHE_PAGIO 0x10000#define IRP$M_FILL_BIT 0x20000#define IRP$M_BUFOBJ 0x40000#define IRP$M_TRUSTED 0x80000"#define IRP$M_FASTIO_DONE 0x100000Q(#define IRP$M_FASTIO 0x200000"#define IRP$M_FAST_FINISH 0x400000#define IRP$M_DOPMS 0x800000#define IRP$M_HIFORK 0x1000000!#define IRP$M_SRV_ABORT 0x2000000(#define IRP$M_LOCK_RELEASEABLE 0x4000000$#define IRP$M_DID_FAST_FDT 0x8000000 #define IRP$M_SYNCSTS 0x10000000 #define IRP$M_FINIPL8 0x20000000##define IRP$M_FILE_FLUSH 0x40000000 #define IRP$M_BARRIER 0x80000000$#define IRP$M_READ_TO_EOF 0x80000000 #define IRP$M_START_PAST_HWM 0x1#define IRP$M_END_PAST_HWM 0x2#define IRP$M_ERR(ASE 0x4#define IRP$M_PART_HWM 0x8#define IRP$M_LCKIO 0x10#define IRP$M_SHDIO 0x20#define IRP$M_CACHEIO 0x40#define IRP$M_WLE 0x80#define IRP$M_CACHE_SAFE 0x100#define IRP$M_NOCACHE 0x200#define IRP$M_ABORTIO 0x400#define IRP$M_FORCEMV 0x800#define IRP$M_HBRIO 0x1000#define IRP$M_ON_ACT_Q 0x2000"#define IRP$M_MPDEV_RETRIED 0x4000#define IRP$M_MPWIO 0x8000"#define IRP$M_FREE_STS2_16 0x10000"#define IRP$M_FREE_STS2_17 0x20000"#define IRP$M_FREE_STS2_18 0x40000#define IRS(P$M_PVIRP 0x80000 #define IRP$M_USEALTDDT 0x100000 #define IRP$M_PID_S0_MV 0x200000##define IRP$M_CACHE_RESUME 0x400000##define IRP$M_FREE_STS2_23 0x800000$#define IRP$M_FREE_STS2_24 0x1000000#define IRP$M_QSVD 0x2000000#define IRP$M_PR_VREG 0x4000000*#define IRP$M_SKIP_BD_CDRP_CHECK 0x8000000#define IRP$M_RWH 0x10000000%#define IRP$M_FREE_STS2_29 0x20000000%#define IRP$M_FREE_STS2_30 0x40000000%#define IRP$M_FREE_STS2_31 0x80000000'#define IRP$M_FREE_STS2_BITS -511246336#defT(ine IRP$M_FCODE 0x3FP#define IRP$K_CDRP 616 /* Offset to the CDRP within the IRP */O#define IRP$C_CDRP 616 /* Offset to the CDRP within the IRP */#define IRP$M_PIO_ERROR 0x1#define IRP$M_PIO_FANOUT 0x2#define IRP$M_PIO_NOQUE 0x4#define IRP$M_PIO_CANCEL 0x8#define IRP$M_PIO_CTHRDOK 0x10#define IRP$M_PIO_PHASEII 0x20#define IRP$M_PIO_BBR 0x40##define IRP$M_SHD_EXPEL_REMOVED 0x1#define IRP$M_SHD_RETRY 0x2#define IRP$M_CLN_READY 0x1#define IRU(P$M_CLN_DONE 0x2$#define IRP$M_SHADOW_SERVER_FINI 0x4!#define IRP$M_RTN_ALT_SUCCESS 0x8#define IRP$M_WBM_DELETE 0x10#define IRP$M_WBM_LOGGED 0x20"#define IRP$M_CLN_SCB_WRITTEN 0x40#define IRP$K_BT_LEN 712#define IRP$C_BT_LEN 712#define IRP$K_CD_LEN 760#define IRP$C_CD_LEN 760  9#ifdef __cplusplus /* Define structure prototypes */ struct _wcb; struct _ucb; struct _ctxb; struct _shad; struct _hrb;struct _bufio; struct _bod;struct _iocpt; struct _aib; struct _V(irpe;struct _fdt_context; struct _ddt; struct _arb; struct _kpb; struct _ccb; struct _fkb; struct _cdt; struct _psb; struct _cdrp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _irp {#pragma __nomember_alignmentN struct _irp *irp$l_ioqfl; /*I/O QUEUE FORWARD LINK */N W( struct _irp *irp$l_ioqbl; /*I/O QUEUE BACKWARD LINK */N unsigned short int irp$w_size; /*SIZE OF IRP IN BYTES */N unsigned char irp$b_type; /*STRUCTURE TYPE FOR IRP */ __union {N unsigned char irp$b_rmod; /*ACCESS MODE OF REQUEST */ __struct {N unsigned irp$v_mode : 2; /* MODE SUBFIELD */( unsigned irp$v_fill_24_ : 6; } irp$r_rmod_b X(its; } irp$r_rmod_overlay;N unsigned int irp$l_pid; /*PROCESS ID OF REQUESTING PROCESS */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 irp$q_param_0; /*For PAGEFAULT and IOCIOPOST */ __struct {] int irp$l_acb64x_offset; /* Offset Y(to ACB64X structure embedded in this IRP */ } irp$r_fill_1_; } irp$r_fill_0_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 irp$q_param_1; /*For PAGEFAULT and IOCIOPOST */ __struct {f unsigned int irp$l_acb_flags; /* ACB flags; valid only Z( if ACB$M_FLAGS_VALID in RMOD set */N unsigned int irp$l_thread_pid; /* (Reserved for Kernel Threads) */ } irp$r_fill_3_; } irp$r_fill_2_; __union {N struct _wcb *irp$l_wind; /*ADDRESS OF WINDOW BLOCK */N struct _irp *irp$l_mirp; /*LINK TO MASTER IRP */N void (*irp$l_kast)(); /*PIGGY BACK KERNEL AST ADDRESS */ } irp$r_wind_overlay;N struct _ucb *irp$l_ucb; /*AD [(DRESS OF DEVICE UCB */ __union {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void (*irp$pq_acb64_ast)(); /* 64-bit user AST routine address */#else# \( unsigned __int64 irp$pq_acb64_ast;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _irp *irp$l_shd_iofl; /* Link to clone IRPs */N struct _ctxb *irp$l_ctxb; /* Link to CTXB */U int irp$l_iirp_p0; /* Generic parameter cell in internal IRPs * ](/" } irp$r_acb64_ast_overlay; __union {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR unsigned __int64 irp$q_acb64_astprm; /* 64-bit user AST parameter value */#pragma __nomember_alignmentN struct _shad *irp$l_shad; /* SHAD address */N struct _hrb *irp$l_hrb; /* HRB address ^( */_ int irp$l_mv_tmo; /* Timeout value in internal mount verification IRPs */U int irp$l_iirp_p1; /* Generic parameter cell in internal IRPs */% } irp$r_acb64_astprm_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 irp$q_user_thread_id; /* Unique user thread identifier _(*/#pragma __nomember_alignmentO unsigned char irp$b_efn; /*EVENT FLAG NUMBER AND EVENT GROUP */Q unsigned char irp$b_pri; /*BASE PRIORITY OF REQUESTING PROCESS */N unsigned char irp$b_cln_indx; /*Shadow Clone membership index */N __union { /* Write log flags. */g unsigned char irp$b_wlg_flags; /* These flags are shared by DUDRIVER and SHDRIVER and MSCP. */N __struct { `(/* Write log Flags Status Bits */N unsigned irp$v_wle_reuse : 1; /* Reuse writelog entry */N unsigned irp$v_wle_supwl : 1; /* Supplementary writelog */N unsigned irp$v_wle_read_contid : 1; /* Read the controller ID */N unsigned irp$v_wle_wrote_contid : 1; /* Controller ID recorded */Z unsigned irp$v_hist_logged : 1; /* Write Log Successfully created or reused */\ unsigned irp$v_allo_fail : 1; /* Allocatioa(n Failure Table successfully update */N unsigned irp$v_hist_lost : 1; /* Write log state lost */N unsigned irp$v_tabfu : 1; /* Write log table full */" } irp$r_wlg_flag_bits;N/* */" } irp$r_wlg_flags_overlay;N/* */N unsigned int irp$l_chan; /* Process I/O channel b( */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *irp$pq_iosb; /* 64-bit address of caller's IOSB */#else c( unsigned __int64 irp$pq_iosb;#endif __struct { __union {N unsigned int irp$l_cln_wle; /* write log entry */T __int64 irp$q_param_2; /* For PAGEFAULT and IOCIOPOST (Kthreads) */U int irp$l_iirp_p2; /* Generic parameter cell in internal IRPs */% } irp$r_iosb_overlay; } irp$r_fill_5_; } irp$r_fill_4_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If d(using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN unsigned __int64 irp$q_status; /*Big time REQUEST STATUS */ __struct {_ __union { /* Create a union so that STS bits can be overloaded */ __union {N unsigned int irp$l_sts; /* Status */ __struct {e(V unsigned irp$v_bufio : 1; /* BUFFERED I/O FLAG ;THESE BITS */Z unsigned irp$v_func : 1; /* 1=>READ FUNCTION ;MUST BE ADJACENT */V unsigned irp$v_pagio : 1; /* PAGING I/O FLAG ;AND IN ORDER */N unsigned irp$v_complx : 1; /* COMPLEX BUFFERED I/O */O unsigned irp$v_virtual : 1; /* VIRTUAL I/O FUNCTION */Y unsigned irp$v_chained : 1; /* CHAINED BUFFERED I/f(O OPERATION */S unsigned irp$v_swapio : 1; /* SWAP OR MPW I/O OPERATION */V unsigned irp$v_diagbuf : 1; /* DIAGNOSTIC BUFFER ALLOCATED */N unsigned irp$v_physio : 1; /* PHYSICAL I/O */c unsigned irp$v_termio : 1; /* TERMINAL I/O (FOR SELECTING PRIORITY INC) */N unsigned irp$v_mbxio : 1; /* MAILBOX BUFFERED READ */W unsigned irp$v_extend : 1; /g(* AN IRPE IS LINKED TO THIS IRP */_ unsigned irp$v_filacp : 1; /* FILE ACP I/O (BOTH DIOCNT AND BIOCNT) */O unsigned irp$v_mvirp : 1; /* MOUNT VERIFICATION IRP */s unsigned irp$v_srvio : 1; /* SERVER TYPE I/O (TRIGGER MOUNTVER ON ERROR BUT DON'T STALL) */l unsigned irp$v_ccb_looked_up : 1; /* Set if IRP$PS_CCB contains valid CCB address */N unsigned irp$v_cache_pagio : 1; /* Ch(ached page i/o */N unsigned irp$v_fill_bit : 1; /* Unused */Q unsigned irp$v_bufobj : 1; /* Set if buffer object I/O */V unsigned irp$v_trusted : 1; /* Set if trusted Component I/O */e unsigned irp$v_fastio_done : 1; /* Set if this is an available Fast-IO IRP */q unsigned irp$v_fastio : 1; /* Set if IRP created by $IO_SETUP -- special delete action */` i( unsigned irp$v_fast_finish : 1; /* Set if IPL8 completion is expected */h unsigned irp$v_dopms : 1; /* =1 if this IRP should call PMS$ logging routines */T unsigned irp$v_hifork : 1; /* Device fork IPL > IPL$C_SCS */X unsigned irp$v_srv_abort : 1; /* Server I/O should be aborted */ unsigned irp$v_lock_releaseable : 1; /* Forklock can be released in favor of PM spinlock on Start I/O */x j( unsigned irp$v_did_fast_fdt : 1; /* Fast-IO may have locked buffers via standard FDT dispatch */a unsigned irp$v_syncsts : 1; /* VIOC can return SS$_SYNC on HIT if set. */N unsigned irp$v_finipl8 : 1; /* Finish at IPL8 hook */^ unsigned irp$v_file_flush : 1; /* Flush the file following this I/O */] unsigned irp$v_barrier : 1; /* Insert a barrier following this I/O */( k( } irp$r_fill_9_;$ } irp$r_fill_8_; __union {3 unsigned int irp$l_sts_overlay; __struct {d unsigned irp$v_filler_1 : 31; /* Fill to overlay READ_TO_EOF with BARRIER */] unsigned irp$v_read_to_eof : 1; /* Reserved for Internal Use only. */) } irp$r_fill_11_;% } irp$r_fill_10_;! } irp$r_sts_bits;N/* End of uniol(n */ __union {N unsigned int irp$l_sts2; /* EXTENSION OF STATUS WORD */ __struct {[ unsigned irp$v_start_past_hwm : 1; /* I/O STARTS PAST HIGHWATER MARK */W unsigned irp$v_end_past_hwm : 1; /* I/O ENDS PAST HIGHWATER MARK */N unsigned irp$v_erase : 1; /* ERASE I/O FUNCTION */T unsigned irp$v_part_hwm(m : 1; /* PARTIAL HIGHWATER MARK UPDATE */O unsigned irp$v_lckio : 1; /* Locked I/O request (DECnet) */N unsigned irp$v_shdio : 1; /* This is a shadowing IRP */N unsigned irp$v_cacheio : 1; /* uses VBN cache buffers */T unsigned irp$v_wle : 1; /* I/O USES A WRITE LOG Phase I ENTRY */N unsigned irp$v_cache_safe : 1; /* this indicates that */N/* the request has been n( */N/* checked as regards */N/* caching. */N unsigned irp$v_nocache : 1; /* IO$M_NOVCACHE was */N/* set in QIO function */N unsigned irp$v_abortio : 1; /* set in EXE$ABORTIO */[ unsigned irp$v_forcemv : 1; /* set to indicate forced MV in o(progress */R unsigned irp$v_hbrio : 1; /* This is a host based raid IRP. */q unsigned irp$v_on_act_q : 1; /* Set if application IRP has already been queued (for HBVS) */ unsigned irp$v_mpdev_retried : 1; /* Set if I/O on a multipath device will be tried on a different path */u unsigned irp$v_mpwio : 1; /* Set on, specifically, modified page writes and NOT on swapper I/O */N/* p( */s unsigned irp$v_free_sts2_16 : 1; /* STS2 bit #16 is free, available for debug or development */N/* */s unsigned irp$v_free_sts2_17 : 1; /* STS2 bit #17 is free, available for debug or development */N/* */s unsigned irp$v_free_sts2_18 : 1; /* STS2 bit #18 is q(free, available for debug or development */R unsigned irp$v_pvirp : 1; /* Set if a path verification IRP */p unsigned irp$v_usealtddt : 1; /* Set if IRP$PS_ALTDDT should be used instead of UCB$L_DDT */q unsigned irp$v_pid_s0_mv : 1; /* Set if normal MV desired for IRP$L_PID with S0/S1 address */^ unsigned irp$v_cache_resume : 1; /* Set if cache needs to see IRP again */N/* r( */s unsigned irp$v_free_sts2_23 : 1; /* STS2 bit #23 is free, available for debug or development */N/* */s unsigned irp$v_free_sts2_24 : 1; /* STS2 bit #24 is free, available for debug or development */i unsigned irp$v_qsvd : 1; /* Obsolete QIOserver function bit that will never be set */N/* However, the pain to remove it exceeds the benefis(t, at this time. */s unsigned irp$v_pr_vreg : 1; /* Set if Persistent Registrations need to be verified on device */| unsigned irp$v_skip_bd_cdrp_check : 1; /* X-68b Inhibit BD/CDRP consistency check (MSCP.MAR X-77A1A1) */_ unsigned irp$v_rwh : 1; /* X-68b Read/Write History attached to this IRP */N/* */s unsigned irp$v_free_sts2_29 : 1; /* t(STS2 bit #29 is free, available for debug or development */N/* */s unsigned irp$v_free_sts2_30 : 1; /* STS2 bit #30 is free, available for debug or development */N/* */s unsigned irp$v_free_sts2_31 : 1; /* STS2 bit #30 is free, available for debug or development */% } irp$r_fill_13_;! u( } irp$r_fill_12_;N/* Mask of all free bits that are available for debug or development */ } irp$r_fill_7_; } irp$r_fill_6_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default v( to 64-bit pointers */V struct _pte *irp$pq_va_pte; /* X-85a 64-bit process virtual addr of PTE */#else unsigned __int64 irp$pq_va_pte;#endif __union {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *irp$pq_void; /* Untyped 64b pointer */#else unsigned __int64 irp$pq_void;#e w(ndifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */T struct _bufio *irp$pq_bufio_pkt; /* 64-bit pointer to buffered I/O packet */#else# unsigned __int64 irp$pq_bufio_pkt;#endifN/* X-85c */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_px(ointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *irp$ps_void; /* Untyped 32b pointer */N struct _bod *irp$ps_bod; /* Buffer Object Descriptor */N struct _iocpt *irp$ps_iocpt; /* I/O Cache Page Table */N struct _aib *irp$ps_aib; /* ACP I/O Buffer pointer */T struct _bufio *irp$ps_bufio_pkt; /* 32-bit pointer to buffered I/O packet */ } irp$r_sv y(apte_overlay;N unsigned int irp$l_bcnt; /*BYTE COUNT OF TRANSFER */N unsigned int irp$l_boff; /* Byte offset */ __union {N unsigned int irp$l_oboff; /* Original BOFF, for segmented DIO */N unsigned int irp$l_aboff; /* "Ambient" BOFF, for NETDRIVER */ } irp$r_oboff_overlay;N struct _irpe *irp$l_extend; /* ADDRESS OF IRPE */ __union {a struct _fdt_contex z(t *irp$ps_fdt_context; /* Contains addr of the FDT Context structure */V struct _ddt *irp$ps_altddt; /* Pointer to DDT if IRP$V_USEALTDDT is set */$ } irp$r_fdt_context_overlay; char irp$b_fill_25_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif" __int64 irp$q_fill_diobm [11];N/* X-82, X-85d {( */S IOBD irp$r_iobd; /* Embedded I/O Buffer Descriptor (IOBD) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */W struct _ext *irp$pq_extent; /* Pointer to 1st buffer extent to reference */#else unsigned __int64 irp$pq_extent;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined |(whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */b struct _ext *irp$pq_orig_extent; /* Original EXTENT, for restoration after segmented I/O */#else% unsigned __int64 irp$pq_orig_extent;#endifN __union { /* */N unsigned __int64 irp$q_extent_boffs; /* */N __struct { /* }( */P int irp$l_extent_boff; /* Byte offset into 1st buffer extent */g int irp$l_orig_extent_boff; /* Original EXTENT_BOFF, for restoration after segmented I/O */' } irp$r_extent_boff_struct;N/* */" } irp$r_extent_boff_union;N/* */ __union {N unsigned __int64 irp$q_media; /* ~( 64 bit LBN of request */ __struct { __union {X unsigned int irp$l_iost1; /*FIRST I/O STATUS LONGWORD (FOR I/O POST) */N unsigned int irp$l_media; /*MEDIA ADDRESS */& } irp$r_iost1_overlay; __union {N unsigned int irp$l_iost2; /*SECOND I/O STATUS LONGWORD */ __union {N int irp$l_tt_term; /*ADDRESS OF READ TERMINATORS MASK */N ( unsigned char irp$b_carcon; /*CARRIAGE CONTROL */, } irp$r_tt_term_overlay;& } irp$r_iost2_overlay; } irp$r_fill_15_; } irp$r_fill_14_; __union {N unsigned __int64 irp$q_nt_prvmsk; /* PRIVILEGE MASK FOR DECNET */N unsigned __int64 irp$q_station; /* STATION FIELD FOR DECNET DRIVERS */ __union {N unsigned __int64 irp$q_tt_state; /* TERMINAL STATE DEFINITIONS */ ( __struct {N unsigned int irp$l_abcnt; /* ACCUMULATED BYTES TRANSFERED */N unsigned int irp$l_obcnt; /* ORIGINAL TRANSFER BYTE COUNT */( } irp$r_tt_state_fields;% } irp$r_tt_state_overlay;" } irp$r_nt_prvmsk_overlay; __union {N unsigned int irp$l_func; /* I/O function code */ __struct {N unsigned irp$v_fcode : 6; /* FUNCTION CODE FIELD */N ( unsigned irp$v_fmod : 10; /* FUNCTION MODIFIER FIELD */ } irp$r_func_bits; } irp$r_func_overlay; __union {N unsigned int irp$l_dt_modifs; /* Disk modifiers */ __struct { __union {3 unsigned short int irp$w_dt_modifs;Y unsigned short int irp$w_shd_mscp_disk_modifier; /*FIELD FOR MODIFIERS */* } irp$r_dt_modifs_overlay; } irp$r_fill_17_; ( } irp$r_fill_16_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN unsigned __int64 irp$q_segvbn; /* 64-bit VBN */V unsigned int irp$l_segvbn; /* VIRTUAL BLOCK NUMBER OF CURRENT SEGMENT */ } irp$r_segvbn_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE ( /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *irp$l_diagbuf; /* DIAGNOSTIC BUFFER ADDRESS */N void *irp$l_scb_buf; /* SCB BUFFER ADDRESS */N unsigned short int irp$w_tt_prmpt; /* PROMPT SIZE */ } irp$r_diagbuf_overlay; __union {N unsigned int irp$l_seqnum; /* SEQUENCE NUMBER ( */N struct _ucb *irp$l_dcd_src_ucb; /* DISK COPY DATA SOURCE UCB */ } irp$r_seqnum_overlay;N struct _arb *irp$l_arb; /* ACCESS RIGHTS BLOCK ADDRESS */ __union {N void *irp$l_keydesc; /* ADDRESS OF ENCRYPTION DESCRIPTOR */N unsigned int irp$l_wle_ptr; /* Clone Write log index */N unsigned char irp$b_cpy_mode; /* Copy mode identifier */ } irp$r_keydesc_overlay;N ( struct _kpb *irp$ps_kpb; /* Pointer to KP block */N struct _ccb *irp$ps_ccb; /* Pointer to CCB for this I/O */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 irp$q_qio_p1; /* QIO argument #1 (64-bits) */ __struct {N ( int irp$l_qio_p1; /* (low-order 32-bit) */ } irp$r_fill_19_; } irp$r_fill_18_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 irp$q_qio_p2; /* QIO argument #2 (64-bits) */ __struct {N int irp$l_qio_p2; ( /* (low-order 32-bit) */ } irp$r_fill_21_; } irp$r_fill_20_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 irp$q_qio_p3; /* QIO argument #3 (64-bits) */N int irp$l_qio_p3; /* (low-order 32-bit) */O (__int64 irp$q_param_3; /* (for PAGEFAULT and IOCIOPOST) */ } irp$r_qio_p3_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 irp$q_qio_p4; /* QIO argument #4 (64-bits) */N int irp$l_qio_p4; /* (low-order 32-bit) */ ( } irp$r_qio_p4_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 irp$q_qio_p5; /* QIO argument #5 (64-bits) */ __struct {N int irp$l_qio_p5; /* (low-order 32-bit) */ } irp$r_fill_23_; } irp$r_fill_22_ (;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 irp$q_qio_p6; /* QIO argument #6 (64-bits) */N int irp$l_qio_p6; /* (low-order 32-bit) */ } irp$r_qio_p6_overlay;N unsigned __int64 irp$q_lbn_64; /* 64-bit LBN ( */C/* ALL FIELDS INSERTED ABOVE THIS POINT IN THE IRP */</* MUST BE CHANGED IN THE CDRPDEF.SDL FILE. */ N/* Standard IRP must contain space for Class Driver CDRP fields. */N struct _fkb *irp$l_fqfl; /* Fork Queue FLINK */N struct _fkb *irp$l_fqbl; /* Fork Queue Blink */S unsigned short int irp$w_cdrpsize; /* Size field for positive section only */N unsigned char irp$b_cd_type; ( /* Type, always of interest */N unsigned char irp$b_flck; /* Fork Lock number */N void (*irp$l_fpc)(); /* Fork PC */N __int64 irp$q_fr3; /* Fork R3 */N __int64 irp$q_fr4; /* Fork R4 */T void (*irp$l_savd_rtn)(); /* Saved return address from level 1 JSB */O void *irp$l_msg_buf; /* Address of al(located MSCP buffer */N unsigned int irp$l_rspid; /* Allocated Request ID */U struct _cdt *irp$l_cdt; /* Address of Connection Descriptor Table */N unsigned __int64 irp$q_res_wait_state; /* SCS Resource Wait State */] int irp$l_scs_stall_data; /* Data cell used by SCS to save data over a stall */N void *irp$l_rwcptr; /* RWAITCNT pointer */_ void *irp$l_bd_addr; /* Address of Bu (ffer Descriptor that maps I/O buffer */N void *irp$l_rbun; /* Address of Resource Bundle */N void *irp$l_lbufh_ad; /* Local BUFfer Handle ADress */W struct _psb *irp$ar_psb; /* Pointer to PSB from which QIO was called. */ I/* Extensions to the CDRP within the IRP */ __union {N/* Host-Based Shadowing Extension */ __struct {N unsi(gned char irp$b_shd_pio_cnt; /* Tot num phys IRPs assoc. */N unsigned char irp$b_shd_pio_act; /* Tot num phys IRPs active. */N/* Note Keep SHD_PIO_FLAGS, SHD_PIO_ERRCNT, contiguous. */ __union {N unsigned char irp$b_shd_pio_flags; /* Master Flags Byte */ __struct {N unsigned irp$v_pio_error : 1; /* Errant clone in Chain */N unsigned irp$v_pio_fanout : 1; /* Chained Clones(. */N unsigned irp$v_pio_noque : 1; /* Don't queue to server */N unsigned irp$v_pio_cancel : 1; /* This master cancelled */P unsigned irp$v_pio_cthrdok : 1; /* Copy thread validated. */R unsigned irp$v_pio_phaseii : 1; /* Bi-phasic Phase II write */_ unsigned irp$v_pio_bbr : 1; /* Bad Block Replacement has been attempted */0 unsigned irp$v_fill_26_ : 1;% (} irp$r_pio_bits;* } irp$r_pio_flags_overlay;O unsigned char irp$b_shd_pio_errcnt; /* Number of errors in chain */N unsigned char irp$b_shd_pio_errindex; /* Index of erring device */N unsigned char irp$b_shd_pio_errsev; /* Relative error severity */' short int irp$w_shd_filler;N unsigned __int64 irp$q_shd_lock_fr0; /* Lock fork R0 */N unsigned __int64 irp$q_shd_lock_fr1; /* Lock fork R1 */(N unsigned __int64 irp$q_shd_lock_fr2; /* Lock fork R2 */N unsigned __int64 irp$q_shd_lock_fr4; /* Lock fork R4 */N unsigned __int64 irp$q_shd_lock_fr5; /* Lock fork R5 */N void (*irp$l_shd_lock_fpc)(); /* Lock fork PC */ __union {T unsigned int irp$l_shd_pio_error; /* BCNT and Error Status (SS$_) */i unsigned int irp$l_wbm_rmtsnd_sts; /* In WBM, return statu (s of ioc_std$remote_set_bits */) } irp$r_shd_wbm_overlay1; __union {N struct _irp *irp$l_shd_pio_lnk; /* Link to clone IRP(s) */S unsigned int irp$l_wbm_refcnt; /* In WBM, count of IRP reference */) } irp$r_shd_wbm_overlay2;N int (*irp$l_shdspc)(); /* Shadowing return PC */N struct _irp *irp$l_shd_control_irp; /* address of control IRP */N int irp$l_shd_temp; ( /* used for temporary storage */O unsigned __int64 irp$q_shd_saved_r1; /* second save area for WLG */0 unsigned __int64 irp$q_shd_saved_r2;0 unsigned __int64 irp$q_shd_saved_r4;N unsigned int irp$l_shd_svd_cnt_irp; /* save SHD_CONTROL_IRP */N unsigned int irp$l_shd_saved_status; /* save area for status */Q unsigned int irp$l_shd_wlg_mode_fpc; /* saved PC for WLG_MODE fork */N unsigned int irp$l_shd(_perlkid; /* holds sublock id for */N/* per-disk */N unsigned int irp$l_shd_expel_timer; /* Clone error timer */ __union {N unsigned int irp$l_shd_expel_flags; /* Clone IRP flags */ __struct {R unsigned irp$v_shd_expel_removed : 1; /* Device is expelled */Z unsigned irp$v_shd_retry : 1; /* PACKACK the Member timeout se (conds */0 unsigned irp$v_fill_27_ : 6;' } irp$r_expel_bits;, } irp$r_expel_flags_overlay;Z unsigned int irp$l_shd_expel_mask; /* indicate units to be expelled in MIRP */$ char irp$b_fill_28_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nome(mber_alignmentU unsigned __int64 irp$q_datacheckretrycounter; /* For said purposes */[ unsigned __int64 irp$q_shd_reserv_q8; /* will be needed for 64-bit saves */- } irp$r_shd_resvd_q8_overlay; __union {[ unsigned __int64 irp$q_current_clone; /* will be needed for 64-bit saves */N unsigned __int64 irp$q_shd_devdsc; /* */O __struct { /* used for finding/cr (eating DSAxxx: */N unsigned int irp$l_shd_devdsc; /* */ __union {# __struct {W unsigned short int irp$w_shd_vun; /* virtual unit number */Z unsigned short int irp$w_shd_dev_type; /* device type = DSA */2 } irp$r_shd_dsa_stuff;] unsigned short int irp$w_shd_copy_type; /* type of copy to perform */1 ( } irp$r_shd_dev2_overlay;, } irp$r_shd_dev_overlay;- } irp$r_shd_resvd_q9_overlay;X unsigned __int64 irp$q_shd_reserv_q10; /* will be needed for 64-bit saves */ __union {N unsigned char irp$b_shd_flags; /* Shadow Clone Flags */N __struct { /* Clone Flags Status Bits */N unsigned irp$v_cln_ready : 1; /* Clone is ready for I/O */N ( unsigned irp$v_cln_done : 1; /* Clone has done I/O */ unsigned irp$v_shadow_server_fini : 1; /* Indicator on some IRPs to SHDRIVER that Shadow Server finished with I\RP */U unsigned irp$v_rtn_alt_success : 1; /* Mini Copy Return status */` unsigned irp$v_wbm_delete : 1; /* Mini Copy WBM Delete bit map was called */O unsigned irp$v_wbm_logged : 1; /* Mini Copy Tracing Code */Q unsigned ( irp$v_cln_scb_written : 1; /* Data Check recovery */0 unsigned irp$v_fill_29_ : 1;* } irp$r_shd_flag_bits;N/* */* } irp$r_shd_flags_overlay;N/* */( } irp$r_shadowing_extension;I/* Block Transfer Extension */ __struct {N (unsigned int irp$l_lboff; /* Local Byte OFFset */ __union {N void *irp$l_rbufh_ad; /* Remote BUFfer Handle ADress */+ struct _cdrp *irp$l_cdrpfl;) } irp$r_rbufh_ad_overlay;N unsigned int irp$l_rboff; /* Remote Byte OFFset */N unsigned int irp$l_xct_len; /* Transfer length in bytes */' } irp$r_blk_xfer_extension;I/* Class Driver Extension ( */ __struct {N char irp$t_lbufhndl [12]; /* Local buffer handle */\ unsigned int irp$l_ubarsrce; /* Scratch Cell used for DU/TUDRIVER convenience */N unsigned int irp$l_dutuflags; /* Class driver status flags: */N unsigned short int irp$w_dutucntr; /* General purpose counter */Z unsigned short int irp$w_endmsgsiz; /* Size of most recent MSCP end message */N unsigned int( irp$l_pdt; /* PDT for this CDRP */Y unsigned int irp$l_walk_cddb; /* Current controller for connection walking */X unsigned int irp$l_walk_alcls; /* Allocation class for connection walking */e unsigned int irp$l_walk_svpc; /* Return address for resumption from connection walking */N unsigned int irp$l_lb_cddb; /* Load balancing CDDB */$ char irp$b_fill_30_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defin (ed(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif* unsigned int irp$l_dutu_rsvd1;#pragma __nomember_alignment* unsigned int irp$l_dutu_rsvd2;* unsigned int irp$l_dutu_rsvd3;* unsigned int irp$l_dutu_rsvd4;& } irp$r_cls_drv_extension;N/* File system extensions */N __union { ( /* VBN to start HWM erase */- unsigned __int64 irp$q_erase_vbn;) unsigned int irp$l_erase_vbn;& } irp$r_erase_vbn_overlay; } irp$r_cdrp_extensions; char irp$b_fill_31_ [3];  char irp$b_fill_32_ [4]; } IRP; #if !defined(__VAXC)0#define irp$b_rmod irp$r_rmod_overlay.irp$b_rmod@#define irp$v_mode irp$r_rmod_overlay.irp$r_rmod_bits.irp$v_mode1#define irp$q_param_0 irp$r_fill_0_.irp$q_param_0K#define irp$l_acb64x_offse (t irp$r_fill_0_.irp$r_fill_1_.irp$l_acb64x_offset1#define irp$q_param_1 irp$r_fill_2_.irp$q_param_1C#define irp$l_acb_flags irp$r_fill_2_.irp$r_fill_3_.irp$l_acb_flagsE#define irp$l_thread_pid irp$r_fill_2_.irp$r_fill_3_.irp$l_thread_pid0#define irp$l_wind irp$r_wind_overlay.irp$l_wind0#define irp$l_mirp irp$r_wind_overlay.irp$l_mirp0#define irp$l_kast irp$r_wind_overlay.irp$l_kastA#define irp$pq_acb64_ast irp$r_acb64_ast_overlay.irp$pq_acb64_ast=#define irp$l_shd_iofl irp$r_acb64_ast_ove (rlay.irp$l_shd_iofl5#define irp$l_ctxb irp$r_acb64_ast_overlay.irp$l_ctxb;#define irp$l_iirp_p0 irp$r_acb64_ast_overlay.irp$l_iirp_p0H#define irp$q_acb64_astprm irp$r_acb64_astprm_overlay.irp$q_acb64_astprm8#define irp$l_shad irp$r_acb64_astprm_overlay.irp$l_shad6#define irp$l_hrb irp$r_acb64_astprm_overlay.irp$l_hrb<#define irp$l_mv_tmo irp$r_acb64_astprm_overlay.irp$l_mv_tmo>#define irp$l_iirp_p1 irp$r_acb64_astprm_overlay.irp$l_iirp_p1?#define irp$b_wlg_flags irp$r_wlg_flags_overlay.irp$(b_wlg_flagsS#define irp$v_wle_reuse irp$r_wlg_flags_overlay.irp$r_wlg_flag_bits.irp$v_wle_reuseS#define irp$v_wle_supwl irp$r_wlg_flags_overlay.irp$r_wlg_flag_bits.irp$v_wle_supwl_#define irp$v_wle_read_contid irp$r_wlg_flags_overlay.irp$r_wlg_flag_bits.irp$v_wle_read_contida#define irp$v_wle_wrote_contid irp$r_wlg_flags_overlay.irp$r_wlg_flag_bits.irp$v_wle_wrote_contidW#define irp$v_hist_logged irp$r_wlg_flags_overlay.irp$r_wlg_flag_bits.irp$v_hist_loggedS#define irp$v_allo_fail irp$r_wl(g_flags_overlay.irp$r_wlg_flag_bits.irp$v_allo_failS#define irp$v_hist_lost irp$r_wlg_flags_overlay.irp$r_wlg_flag_bits.irp$v_hist_lostK#define irp$v_tabfu irp$r_wlg_flags_overlay.irp$r_wlg_flag_bits.irp$v_tabfu-#define irp$pq_iosb irp$r_fill_4_.irp$pq_iosbR#define irp$l_cln_wle irp$r_fill_4_.irp$r_fill_5_.irp$r_iosb_overlay.irp$l_cln_wleR#define irp$q_param_2 irp$r_fill_4_.irp$r_fill_5_.irp$r_iosb_overlay.irp$q_param_2R#define irp$l_iirp_p2 irp$r_fill_4_.irp$r_fill_5_.irp$r_iosb_overlay.irp ($l_iirp_p2/#define irp$q_status irp$r_fill_6_.irp$q_statusA#define irp$r_sts_bits irp$r_fill_6_.irp$r_fill_7_.irp$r_sts_bits8#define irp$l_sts irp$r_sts_bits.irp$r_fill_8_.irp$l_stsJ#define irp$v_bufio irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_bufioH#define irp$v_func irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_funcJ#define irp$v_pagio irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_pagioL#define irp$v_complx irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_complxN#define irp$v_(virtual irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_virtualN#define irp$v_chained irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_chainedL#define irp$v_swapio irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_swapioN#define irp$v_diagbuf irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_diagbufL#define irp$v_physio irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_physioL#define irp$v_termio irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_termioJ#define irp$v_mbxio irp$r_sts_bits.irp$r_fill_(8_.irp$r_fill_9_.irp$v_mbxioL#define irp$v_extend irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_extendL#define irp$v_filacp irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_filacpJ#define irp$v_mvirp irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_mvirpJ#define irp$v_srvio irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_srvioZ#define irp$v_ccb_looked_up irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_ccb_looked_upV#define irp$v_cache_pagio irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_c(ache_pagioP#define irp$v_fill_bit irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_fill_bitL#define irp$v_bufobj irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_bufobjN#define irp$v_trusted irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_trustedV#define irp$v_fastio_done irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_fastio_doneL#define irp$v_fastio irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_fastioV#define irp$v_fast_finish irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_fast_finishJ(#define irp$v_dopms irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_dopmsL#define irp$v_hifork irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_hiforkR#define irp$v_srv_abort irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_srv_abort`#define irp$v_lock_releaseable irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_lock_releaseableX#define irp$v_did_fast_fdt irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_did_fast_fdtN#define irp$v_syncsts irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_syncstsN(#define irp$v_finipl8 irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_finipl8T#define irp$v_file_flush irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_file_flushN#define irp$v_barrier irp$r_sts_bits.irp$r_fill_8_.irp$r_fill_9_.irp$v_barrierI#define irp$l_sts_overlay irp$r_sts_bits.irp$r_fill_10_.irp$l_sts_overlayX#define irp$v_read_to_eof irp$r_sts_bits.irp$r_fill_10_.irp$r_fill_11_.irp$v_read_to_eofH#define irp$l_sts2 irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$l_sts2k#define irp$v_start_(past_hwm irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_start_past_hwmg#define irp$v_end_past_hwm irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_end_past_hwmY#define irp$v_erase irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_erase_#define irp$v_part_hwm irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_part_hwmY#define irp$v_lckio irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_lckioY#define irp$v_shdio irp$r_fi(ll_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_shdio]#define irp$v_cacheio irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_cacheioU#define irp$v_wle irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_wlec#define irp$v_cache_safe irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_cache_safe]#define irp$v_nocache irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_nocache]#define irp$v_abortio irp$r_fill_6_.irp$r_fill_7_.irp$r_fill(_12_.irp$r_fill_13_.irp$v_abortio]#define irp$v_forcemv irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_forcemvY#define irp$v_hbrio irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_hbrio_#define irp$v_on_act_q irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_on_act_qi#define irp$v_mpdev_retried irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_mpdev_retriedY#define irp$v_mpwio irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13(_.irp$v_mpwiog#define irp$v_free_sts2_16 irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_free_sts2_16g#define irp$v_free_sts2_17 irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_free_sts2_17g#define irp$v_free_sts2_18 irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_free_sts2_18Y#define irp$v_pvirp irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_pvirpa#define irp$v_usealtddt irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13(_.irp$v_usealtddta#define irp$v_pid_s0_mv irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_pid_s0_mvg#define irp$v_cache_resume irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_cache_resumeg#define irp$v_free_sts2_23 irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_free_sts2_23g#define irp$v_free_sts2_24 irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_free_sts2_24W#define irp$v_qsvd irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_(fill_13_.irp$v_qsvd]#define irp$v_pr_vreg irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_pr_vregs#define irp$v_skip_bd_cdrp_check irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_skip_bd_cdrp_checkU#define irp$v_rwh irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_rwhg#define irp$v_free_sts2_29 irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_free_sts2_29g#define irp$v_free_sts2_30 irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_ (fill_13_.irp$v_free_sts2_30g#define irp$v_free_sts2_31 irp$r_fill_6_.irp$r_fill_7_.irp$r_fill_12_.irp$r_fill_13_.irp$v_free_sts2_314#define irp$pq_void irp$r_svapte_overlay.irp$pq_void>#define irp$pq_bufio_pkt irp$r_svapte_overlay.irp$pq_bufio_pkt4#define irp$ps_void irp$r_svapte_overlay.irp$ps_void2#define irp$ps_bod irp$r_svapte_overlay.irp$ps_bod6#define irp$ps_iocpt irp$r_svapte_overlay.irp$ps_iocpt2#define irp$ps_aib irp$r_svapte_overlay.irp$ps_aib>#define irp$ps_bufio_pkt irp$r_svapte_(overlay.irp$ps_bufio_pkt3#define irp$l_oboff irp$r_oboff_overlay.irp$l_oboff3#define irp$l_aboff irp$r_oboff_overlay.irp$l_aboffG#define irp$ps_fdt_context irp$r_fdt_context_overlay.irp$ps_fdt_context=#define irp$ps_altddt irp$r_fdt_context_overlay.irp$ps_altddtE#define irp$q_extent_boffs irp$r_extent_boff_union.irp$q_extent_boffs\#define irp$l_extent_boff irp$r_extent_boff_union.irp$r_extent_boff_struct.irp$l_extent_bofff#define irp$l_orig_extent_boff irp$r_extent_boff_union.irp$r_extent_(boff_struct.irp$l_orig_extent_boff.#define irp$q_media irp$r_fill_14_.irp$q_mediaQ#define irp$l_iost1 irp$r_fill_14_.irp$r_fill_15_.irp$r_iost1_overlay.irp$l_iost1Q#define irp$l_media irp$r_fill_14_.irp$r_fill_15_.irp$r_iost1_overlay.irp$l_mediaQ#define irp$l_iost2 irp$r_fill_14_.irp$r_fill_15_.irp$r_iost2_overlay.irp$l_iost2k#define irp$l_tt_term irp$r_fill_14_.irp$r_fill_15_.irp$r_iost2_overlay.irp$r_tt_term_overlay.irp$l_tt_termi#define irp$b_carcon irp$r_fill_14_.irp$r_fill_15_.irp$r_ios(t2_overlay.irp$r_tt_term_overlay.irp$b_carcon?#define irp$q_nt_prvmsk irp$r_nt_prvmsk_overlay.irp$q_nt_prvmsk;#define irp$q_station irp$r_nt_prvmsk_overlay.irp$q_stationT#define irp$q_tt_state irp$r_nt_prvmsk_overlay.irp$r_tt_state_overlay.irp$q_tt_stated#define irp$l_abcnt irp$r_nt_prvmsk_overlay.irp$r_tt_state_overlay.irp$r_tt_state_fields.irp$l_abcntd#define irp$l_obcnt irp$r_nt_prvmsk_overlay.irp$r_tt_state_overlay.irp$r_tt_state_fields.irp$l_obcnt0#define irp$l_func irp$r_func_overlay.ir(p$l_funcB#define irp$v_fcode irp$r_func_overlay.irp$r_func_bits.irp$v_fcode@#define irp$v_fmod irp$r_func_overlay.irp$r_func_bits.irp$v_fmod6#define irp$l_dt_modifs irp$r_fill_16_.irp$l_dt_modifs]#define irp$w_dt_modifs irp$r_fill_16_.irp$r_fill_17_.irp$r_dt_modifs_overlay.irp$w_dt_modifsw#define irp$w_shd_mscp_disk_modifier irp$r_fill_16_.irp$r_fill_17_.irp$r_dt_modifs_overlay.irp$w_shd_mscp_disk_modifier6#define irp$q_segvbn irp$r_segvbn_overlay.irp$q_segvbn6#define irp$l_segvbn irp$r_segvb (n_overlay.irp$l_segvbn9#define irp$l_diagbuf irp$r_diagbuf_overlay.irp$l_diagbuf9#define irp$l_scb_buf irp$r_diagbuf_overlay.irp$l_scb_buf;#define irp$w_tt_prmpt irp$r_diagbuf_overlay.irp$w_tt_prmpt6#define irp$l_seqnum irp$r_seqnum_overlay.irp$l_seqnum@#define irp$l_dcd_src_ucb irp$r_seqnum_overlay.irp$l_dcd_src_ucb9#define irp$l_keydesc irp$r_keydesc_overlay.irp$l_keydesc9#define irp$l_wle_ptr irp$r_keydesc_overlay.irp$l_wle_ptr;#define irp$b_cpy_mode irp$r_keydesc_overlay.irp$b_cpy_mod (e0#define irp$q_qio_p1 irp$r_fill_18_.irp$q_qio_p1?#define irp$l_qio_p1 irp$r_fill_18_.irp$r_fill_19_.irp$l_qio_p10#define irp$q_qio_p2 irp$r_fill_20_.irp$q_qio_p2?#define irp$l_qio_p2 irp$r_fill_20_.irp$r_fill_21_.irp$l_qio_p26#define irp$q_qio_p3 irp$r_qio_p3_overlay.irp$q_qio_p36#define irp$l_qio_p3 irp$r_qio_p3_overlay.irp$l_qio_p38#define irp$q_param_3 irp$r_qio_p3_overlay.irp$q_param_36#define irp$q_qio_p4 irp$r_qio_p4_overlay.irp$q_qio_p46#define irp$l_qio_p4 irp$r_qio_p4_overlay.ir(p$l_qio_p40#define irp$q_qio_p5 irp$r_fill_22_.irp$q_qio_p5?#define irp$l_qio_p5 irp$r_fill_22_.irp$r_fill_23_.irp$l_qio_p56#define irp$q_qio_p6 irp$r_qio_p6_overlay.irp$q_qio_p66#define irp$l_qio_p6 irp$r_qio_p6_overlay.irp$l_qio_p6[#define irp$b_shd_pio_cnt irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$b_shd_pio_cnt[#define irp$b_shd_pio_act irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$b_shd_pio_actw#define irp$b_shd_pio_flags irp$r_cdrp_extensions.irp$r_shadowing_extension.ir(p$r_pio_flags_overlay.irp$b_shd_pio_flags~#define irp$v_pio_error irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_pio_flags_overlay.irp$r_pio_bits.irp$v_pio_error#define irp$v_pio_fanout irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_pio_flags_overlay.irp$r_pio_bits.irp$v_pio_fanout~#define irp$v_pio_noque irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_pio_flags_overlay.irp$r_pio_bits.irp$v_pio_noque#define irp$v_pio_cancel irp$r_cdrp_extensions.irp$r_shadowing_extension.irp($r_pio_flags_overlay.irp$r_pio_bits.irp$v_pio_cancel#define irp$v_pio_cthrdok irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_pio_flags_overlay.irp$r_pio_bits.irp$v_pio_cthrdok#define irp$v_pio_phaseii irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_pio_flags_overlay.irp$r_pio_bits.irp$v_pio_phaseiiz#define irp$v_pio_bbr irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_pio_flags_overlay.irp$r_pio_bits.irp$v_pio_bbra#define irp$b_shd_pio_errcnt irp$r_cdrp_extensions.irp$r_shadowi(ng_extension.irp$b_shd_pio_errcnte#define irp$b_shd_pio_errindex irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$b_shd_pio_errindexa#define irp$b_shd_pio_errsev irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$b_shd_pio_errsev]#define irp$q_shd_lock_fr0 irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$q_shd_lock_fr0]#define irp$q_shd_lock_fr1 irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$q_shd_lock_fr1]#define irp$q_shd_lock_fr2 irp$r_cdrp_extensions.irp$r_shadowing_extension(.irp$q_shd_lock_fr2]#define irp$q_shd_lock_fr4 irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$q_shd_lock_fr4]#define irp$q_shd_lock_fr5 irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$q_shd_lock_fr5]#define irp$l_shd_lock_fpc irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$l_shd_lock_fpcv#define irp$l_shd_pio_error irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_wbm_overlay1.irp$l_shd_pio_errorx#define irp$l_wbm_rmtsnd_sts irp$r_cdrp_extensions.irp$r_shadowing_extension(.irp$r_shd_wbm_overlay1.irp$l_wbm_rmtsnd_stsr#define irp$l_shd_pio_lnk irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_wbm_overlay2.irp$l_shd_pio_lnkp#define irp$l_wbm_refcnt irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_wbm_overlay2.irp$l_wbm_refcntQ#define irp$l_shdspc irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$l_shdspcc#define irp$l_shd_control_irp irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$l_shd_control_irpU#define irp$l_shd_temp irp$r_cdrp_extensions(.irp$r_shadowing_extension.irp$l_shd_temp]#define irp$q_shd_saved_r1 irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$q_shd_saved_r1]#define irp$q_shd_saved_r2 irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$q_shd_saved_r2]#define irp$q_shd_saved_r4 irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$q_shd_saved_r4c#define irp$l_shd_svd_cnt_irp irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$l_shd_svd_cnt_irpe#define irp$l_shd_saved_status irp$r_cdrp_extensions.irp$r_shadowing_ext(ension.irp$l_shd_saved_statuse#define irp$l_shd_wlg_mode_fpc irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$l_shd_wlg_mode_fpc[#define irp$l_shd_perlkid irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$l_shd_perlkidc#define irp$l_shd_expel_timer irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$l_shd_expel_timer}#define irp$l_shd_expel_flags irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_expel_flags_overlay.irp$l_shd_expel_flags#define irp$v_shd_expel_removed irp$r_cdrp_ext(ensions.irp$r_shadowing_extension.irp$r_expel_flags_overlay.irp$r_expel_bits.irp$v_sh\d_expel_removed#define irp$v_shd_retry irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_expel_flags_overlay.irp$r_expel_bits.irp$v_shd_retrya#define irp$l_shd_expel_mask irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$l_shd_expel_mask#define irp$q_datacheckretrycounter irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_resvd_q8_overlay.irp$q_datacheckretry\counterz#define irp$q_shd_reserv(_q8 irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_resvd_q8_overlay.irp$q_shd_reserv_q8z#define irp$q_current_clone irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_resvd_q9_overlay.irp$q_current_clonet#define irp$q_shd_devdsc irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_resvd_q9_overlay.irp$q_shd_devdsc#define irp$l_shd_devdsc irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_resvd_q9_overlay.irp$r_shd_dev_overlay.irp$l_shd\_devdsc#define irp$w_shd_vu(n irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_resvd_q9_overlay.irp$r_shd_dev_overlay.irp$r_shd_de\,v2_overlay.irp$r_shd_dsa_stuff.irp$w_shd_vun#define irp$w_shd_dev_type irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_resvd_q9_overlay.irp$r_shd_dev_overlay.irp$r_s\6hd_dev2_overlay.irp$r_shd_dsa_stuff.irp$w_shd_dev_type#define irp$w_shd_copy_type irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_resvd_q9_overlay.irp$r_shd_dev_overlay.irp$r_\$shd_dev2_overlay.irp$w(_shd_copy_typea#define irp$q_shd_reserv_q10 irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$q_shd_reserv_q10o#define irp$b_shd_flags irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_flags_overlay.irp$b_shd_flags#define irp$v_cln_ready irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_flags_overlay.irp$r_shd_flag_bits.irp$v_cln_ready#define irp$v_cln_done irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_flags_overlay.irp$r_shd_flag_bits.irp$v_cln_done#define ir(p$v_shadow_server_fini irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_flags_overlay.irp$r_shd_flag_bits.irp$v_\shadow_server_fini#define irp$v_rtn_alt_success irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_flags_overlay.irp$r_shd_flag_bits.irp$v_rtn\ _alt_success#define irp$v_wbm_delete irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_flags_overlay.irp$r_shd_flag_bits.irp$v_wbm_dele\te#define irp$v_wbm_logged irp$r_cdrp_extensions.irp$r_shadowing_extension.irp($r_shd_flags_overlay.irp$r_shd_flag_bits.irp$v_wbm_logg\ed#define irp$v_cln_scb_written irp$r_cdrp_extensions.irp$r_shadowing_extension.irp$r_shd_flags_overlay.irp$r_shd_flag_bits.irp$v_cln\ _scb_writtenN#define irp$l_lboff irp$r_cdrp_extensions.irp$r_blk_xfer_extension.irp$l_lboffk#define irp$l_rbufh_ad irp$r_cdrp_extensions.irp$r_blk_xfer_extension.irp$r_rbufh_ad_overlay.irp$l_rbufh_adg#define irp$l_cdrpfl irp$r_cdrp_extensions.irp$r_blk_xfer_extension.irp$r_rbufh_ad_overlay.irp$l_cdrpflN(#define irp$l_rboff irp$r_cdrp_extensions.irp$r_blk_xfer_extension.irp$l_rboffR#define irp$l_xct_len irp$r_cdrp_extensions.irp$r_blk_xfer_extension.irp$l_xct_lenS#define irp$t_lbufhndl irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$t_lbufhndlS#define irp$l_ubarsrce irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$l_ubarsrceU#define irp$l_dutuflags irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$l_dutuflagsS#define irp$w_dutucntr irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$w_dutucnt(rU#define irp$w_endmsgsiz irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$w_endmsgsizI#define irp$l_pdt irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$l_pdtU#define irp$l_walk_cddb irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$l_walk_cddbW#define irp$l_walk_alcls irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$l_walk_alclsU#define irp$l_walk_svpc irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$l_walk_svpcQ#define irp$l_lb_cddb irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$(l_lb_cddbW#define irp$l_dutu_rsvd1 irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$l_dutu_rsvd1W#define irp$l_dutu_rsvd2 irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$l_dutu_rsvd2W#define irp$l_dutu_rsvd3 irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$l_dutu_rsvd3W#define irp$l_dutu_rsvd4 irp$r_cdrp_extensions.irp$r_cls_drv_extension.irp$l_dutu_rsvd4U#define irp$q_erase_vbn irp$r_cdrp_extensions.irp$r_erase_vbn_overlay.irp$q_erase_vbnU#define irp$l_erase_vbn irp$r_cdrp_extensions. (irp$r_erase_vbn_overlay.irp$l_erase_vbn"#endif /* #if !defined(__VAXC) */ N#define IRP$K_LENGTH 856 /* LENGTH OF STANDARD IRP */N#define IRP$C_LENGTH 856 /* LENGTH OF STANDARD IRP */N#define IRP$S_IRPDEF 856 /* OLD IRP SIZE FOR COMPATIBILITY */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore( the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IRPDEF_LOADED */ ww`CT[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized( to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or( disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7 (-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */G/* Source: 24-JUL-2023 11:46:16 $1$DGA8345:[LIB_H.SRC]IRPEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IRPEDEF ***/#ifndef __IRPEDEF_LOADED#define __IRPEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER(_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#e(lse#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* IRPE - I/O REQUEST PACKET EXTENSION */N/* */N/* I/O REQUEST PACKET EXTENSIONS ARE USED TO HOLD ADDITIONAL INFORMATION */P/*( ABOUT I/O REQUESTS FOR DEVICES THAT REQUIRE MORE CONTEXT THAN CAN FIT INTO */N/* THE STANDARD IRP. IRPE'S ARE BUILT AND LINKED ONTO IRP'S BY DEVICE */N/* DRIVER FDT ROUTINES. ANY FIELDS THAT ARE NOT DEFINED IN THIS STRUCTURE */N/* MAY BE USED TO HOLD DRIVER DEPENDENT DATA. */N/* */N/* THE CURRENTLY DEFINED FIELDS IN THE IRPE WERE POSITIONED SO THAT THE */N/* PACKET COULD BE USED AS( A FORK BLOCK. THIS SHOULD BE KEPT IN MIND IF */N/* AND WHEN NEW FIELDS ARE DEFINED. */N/* */O/* NOTE: Most of the fields of the IRPE must be at the same offsets as their */N/* corresponding fields in the IRP. The equivalency of these offsets is */N/* verified by ASSUME statements in the [LIB]VFY_IRP_A_LIKES.MAR module. */P/* These ASSUMEs may need to be altered as well wh(enever an IRPE or IRP field */N/* is removed or altered. */N/*- */  X#include /* Define the IOBD type; IRP contains an embedded IOBD */#define IRPE$M_FUNC 0x2#define IRPE$M_EXTEND 0x800#define IRPE$M_QSVD 0x8000#define IRPE$M_QCOMPLEX 0x10000#define IRPE$M_NORETRY 0x20000#define IRPE$M_QBARRIER 0x40000  9#ifdef __cplusplus (/* Define structure prototypes */struct _bufio; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _irpe {#pragma __nomember_alignmentN int irpe$l_fill_1; /* SPARE LONGWORD */N int irpe$l_fill_2; /* SPARE LONGWORD */N unsigned ( short int irpe$w_size; /* SIZE OF IRPE IN BYTES */N unsigned char irpe$b_type; /* STRUCTURE TYPE FOR IRPE */N unsigned char irpe$b_rmod; /* RMOD BYTE */P int irpe$l_fill_4; /* Explicit filler for quad alignment */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __ (union {#pragma __nomember_alignmentO __int64 irpe$q_driver_p0; /* Available for driver-specific use */ __struct {N unsigned int irpe$l_driver_p0; /* (low-order 32-bits) */N unsigned int irpe$l_driver_p1; /* (high-order 32-bits) */ } irpe$r_fill_1_; } irpe$r_fill_0_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword (#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentO __int64 irpe$q_driver_p2; /* Available for driver-specific use */ __struct {N unsigned int irpe$l_driver_p2; /* (low-order 32-bits) */N unsigned int irpe$l_driver_p3; /* (high-order 32-bits) */ } irpe$r_fill_3_; } irpe$r_fill_2_;N int irpe$l_fill_5 [12]; /* Filler to match IRP */c#if !def(ined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment' unsigned __int64 irpe$q_status; __struct { __union {N unsigned int irpe$l_sts; /* Status bits */ __struct {N unsigned irpe$v_fill_7 : 1; /* Skip over 1 bit */W( unsigned irpe$v_func : 1; /* 1=>read function, 0=>write function */N unsigned irpe$v_fill_7a : 9; /* SKIP OVER 9 BITS */Y unsigned irpe$v_extend : 1; /* ANOTHER IRPE IS LINKED TO THIS ONE */0 unsigned irpe$v_fill_6_ : 4;& } irpe$r_sts_bits;% } irpe$r_sts_overlay;V __union { /* Flesh out STS2 to include QIOserver bits */) unsigned i(nt irpe$l_sts2;N __struct { /* The bit field structure... */N unsigned irpe$v_fill_8 : 15; /* Skip over 15 bits */N unsigned irpe$v_qsvd : 1; /* Set if QIOserver function */Y unsigned irpe$v_qcomplex : 1; /* Set if QIOserver complex function */j unsigned irpe$v_noretry : 1; /* Do not retry this operation if QIOserver path fails */] unsigned irpe$v_qbarrier : 1 (; /* This is a QIOserver barrier operation */0 unsigned irpe$v_fill_7_ : 5;' } irpe$r_sts2_bits;& } irpe$r_sts2_overlay; } irpe$r_fill_5_; } irpe$r_fill_4_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas suppor (ted */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */V struct _pte *irpe$pq_va_pte; /* X-18a 64-bit process virtual addr of PTE */#else! unsigned __int64 irpe$pq_va_pte;#endif#pragma __nomember_alignmentN __union { /* X-18b */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to (64-bit pointers */N struct _bufio *irpe$pq_bufio_pkt; /* */#else$ unsigned __int64 irpe$pq_bufio_pkt;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *irpe$pq_void; /* Untyped 64b pointer */#else unsigned __int64 irpe$pq_void;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined wh (enever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *irpe$ps_void; /* Untyped 32b pointer */N struct _bufio *irpe$ps_bufio_pkt; /* Pointer to buffered I/O packet */ } irpe$r_svapte_overlay;N unsigned int irpe$l_bcnt; /* Byte count for locked buffer */S unsigned int irpe$l_boff; /* Byte offset in page for locked buffer */N un (signed int irpe$l_oboff; /* Original BOFF, for segmented DIO */N struct _irpe *irpe$l_extend; /* ADDRESS OF NEXT IRPE */N int irpe$l_fill_6 [1]; /* Filler to match IRP */ char irpe$b_fill_8_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif# __int64 irpe$q_fill_diobm [11];N/* X-17, X-18c ( */S IOBD irpe$r_iobd; /* Embedded I/O Buffer Descriptor (IOBD) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */W struct _ext *irpe$pq_extent; /* Pointer to 1st buffer extent to reference */#else! unsigned __int64 irpe$pq_extent;#endif#pragma __nomember_alignmentR#ifdef( __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */b struct _ext *irpe$pq_orig_extent; /* Original EXTENT, for restoration after segmented I/O */#else& unsigned __int64 irpe$pq_orig_extent;#endifP unsigned int irpe$l_extent_boff; /* Byte offset into 1st buffer extent */i unsigned int irpe$l_orig_extent_boff; /* Original EXTENT_BOFF, for restoration after segmented ( I/O */ } IRPE; #if !defined(__VAXC)8#define irpe$q_driver_p0 irpe$r_fill_0_.irpe$q_driver_p0G#define irpe$l_driver_p0 irpe$r_fill_0_.irpe$r_fill_1_.irpe$l_driver_p0G#define irpe$l_driver_p1 irpe$r_fill_0_.irpe$r_fill_1_.irpe$l_driver_p18#define irpe$q_driver_p2 irpe$r_fill_2_.irpe$q_driver_p2G#define irpe$l_driver_p2 irpe$r_fill_2_.irpe$r_fill_3_.irpe$l_driver_p2G#define irpe$l_driver_p3 irpe$r_fill_2_.irpe$r_fill_3_.irpe$l_driver_p32#define irpe$q_status irpe$r_fill_4_.irpe$q_(statusN#define irpe$l_sts irpe$r_fill_4_.irpe$r_fill_5_.irpe$r_sts_overlay.irpe$l_sts`#define irpe$v_func irpe$r_fill_4_.irpe$r_fill_5_.irpe$r_sts_overlay.irpe$r_sts_bits.irpe$v_funcd#define irpe$v_extend irpe$r_fill_4_.irpe$r_fill_5_.irpe$r_sts_overlay.irpe$r_sts_bits.irpe$v_extendQ#define irpe$l_sts2 irpe$r_fill_4_.irpe$r_fill_5_.irpe$r_sts2_overlay.irpe$l_sts2b#define irpe$v_qsvd irpe$r_fill_4_.irpe$r_fill_5_.irpe$r_sts2_overlay.irpe$r_sts2_bits.irpe$v_qsvdj#define irpe$v_qcomplex irpe$r_fil(l_4_.irpe$r_fill_5_.irpe$r_sts2_overlay.irpe$r_sts2_bits.irpe$v_qcomplexh#define irpe$v_noretry irpe$r_fill_4_.irpe$r_fill_5_.irpe$r_sts2_overlay.irpe$r_sts2_bits.irpe$v_noretryj#define irpe$v_qbarrier irpe$r_fill_4_.irpe$r_fill_5_.irpe$r_sts2_overlay.irpe$r_sts2_bits.irpe$v_qbarrierA#define irpe$pq_bufio_pkt irpe$r_svapte_overlay.irpe$pq_bufio_pkt7#define irpe$pq_void irpe$r_svapte_overlay.irpe$pq_void7#define irpe$ps_void irpe$r_svapte_overlay.irpe$ps_voidA#define irpe$ps_bufio_pkt irpe$r_s (vapte_overlay.irpe$ps_bufio_pkt"#endif /* #if !defined(__VAXC) */ N#define IRPE$K_LENGTH 504 /* LENGTH OF IRPE */N#define IRPE$C_LENGTH 504 /* LENGTH OF IRPE */U#define IRPE$S_IRPEDEF 504 /* Old size name, synonym for IRPE$S_IRPE */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore( the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IRPEDEF_LOADED */ ww`%Y[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorizgo$IOVECDEF$xIO_ROUTINES_DATA$ IPFINSDEF#'IPLDEF.'IPMIDEF/(IRCDEFG(IRPDEF(IRPEDEF( ISACFGDEF(ISDDEF ) ISDOLDDEF )ISRDEF>)pITEMLDEFF)ITIRDEFP)DIVRDEFV)lIVTDEFh)JIBDEF|) KA0202DEF:*  KA0302DEF-J KA0402DEF- KA0602DEF- KA0702DEF%.b KA0802DEFF. KA0902DEF0 KA0905DEF1 KA0C05DEF3V KA0E04DEF3d KA0F05DEF KA1605DEF3 KDZDEF3dKEYDEF3jKFDDEF` LDR_ROUTINES(ed to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated (or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: ( 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */I/* Source: 23-OCT-2002 11:41:37 $1$DGA8345:[LIB_H.SRC]ISACFGDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ISACFGDEF ***/#ifndef __ISACFGDEF_LOADED#define __ISACFGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITI(AL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct s(truct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* This file describes the layout of the configuration data blocks */N/* for ISA devices. There are two data structures described in this */N/* file. The first is the ISA_CFG_DATA block that VMS uses to store ( */N/* ISA configuration information for ISA devices. There is an */N/* ISA_CFG_DATA block for each ISA device in the system. The second data */N/* structure described in this file is the console supplied ISA config */N/* information, stored in nvram. The console ISA configuration */N/* information actually consists of a header and a number of entries. */N/* The console ISA config header is defined as ISACFG_HDR and the console */N/* ISA config entr(ies are defined as ISACFG_ENTRY. */N/* */N/* During ISA configuration, data is read from the console ISA config */N/* information and stored in ISA_CFG_DATA blocks. Then, data is also */N/* read from the user-editable file SYS$MANAGER:ISA_CONFIG.DAT and stored */N/* in ISA_CFG_DATA blocks. Then the drivers are loaded for the ISA */N/* devices. ( */N/* */N/* The ISA_CFG_DATA block contains ISA Bus resource information */N/* for each device, sych as IRQ, DMA channels, IO Ports, Memory addr, */N/* slot number. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /*( If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _isa_cfg_data {#pragma __nomember_alignment* struct _isa_cfg_data *isacfg$ps_flink;* struct _isa_cfg_data *isacfg$ps_blink;% unsigned short int isacfg$w_size; unsigned char isacfg$b_type;# unsigned char isacfg$b_subtype; unsigned int isacfg$l_irq;# unsigned int isacfg$l_membuff0;" unsigned int isacfg$l_memlen0;# unsigned i(nt isacfg$l_membuff1;" unsigned int isacfg$l_memlen1;# unsigned int isacfg$l_membuff2;" unsigned int isacfg$l_memlen2;# unsigned int isacfg$l_membuff3;" unsigned int isacfg$l_memlen3;# unsigned int isacfg$l_dmachan0;# unsigned int isacfg$l_dmachan1;# unsigned int isacfg$l_dmachan2;# unsigned int isacfg$l_dmachan3;) unsigned short int isacfg$w_io_port0;( unsigned short int isacfg$w_io_len0;) unsigned short int isacfg$w_io_port1;( unsigned sho (rt int isacfg$w_io_len1;) unsigned short int isacfg$w_io_port2;( unsigned short int isacfg$w_io_len2;) unsigned short int isacfg$w_io_port3;( unsigned short int isacfg$w_io_len3;) unsigned short int isacfg$w_io_port4;( unsigned short int isacfg$w_io_len4;) unsigned short int isacfg$w_io_port5;( unsigned short int isacfg$w_io_len5;) unsigned short int isacfg$w_io_port6;( unsigned short int isacfg$w_io_len6;) unsigned short int isacfg$w_io_port7;( un(signed short int isacfg$w_io_len7;) unsigned short int isacfg$w_io_port8;( unsigned short int isacfg$w_io_len8;( unsigned char isacfg$b_dev_name [4];' unsigned char isacfg$b_driver [16]; unsigned int isacfg$l_flags; unsigned int isacfg$l_node;+ unsigned char isacfg$b_user_param [72]; __union {# unsigned int isacfg$l_irq2;# unsigned int isacfg$l_rsv1; } isacfg$r_irq_overlay; unsigned int isacfg$l_rsv2; } ISA_CFG_DATA; (#if !defined(__VAXC)8#define isacfg$l_irq2 isacfg$r_irq_overlay.isacfg$l_irq28#define isacfg$l_rsv1 isacfg$r_irq_overlay.isacfg$l_rsv1"#endif /* #if !defined(__VAXC) */ %#define ISA$K_ISA_CFG_DATA_LENGTH 208#define ISACFG$K_PORT 0#define ISACFG$K_MEM 1#define ISACFG$K_IRQ 2#define ISACFG$K_NAME 3#define ISACFG$K_NODE 4#define ISACFG$K_DRIVER 5#define ISACFG$K_DMA 6#define ISACFG$K_USER_PARAM 7 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If usin(g pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _isacfg_hdr {#pragma __nomember_alignment. unsigned char isacfg_hdr$b_identifier [8];2 unsigned short int isacfg_hdr$w_major_version;2 unsigned short int isacfg_hdr$w_minor_version;$ unsigned int isacfg_hdr$l_fill1;* unsigned int isacfg_hdr$l_num_entries;1 unsigned int isacfg_hdr$l_first_entry_offset;- unsigned int isacfg_hdr$l_table_checksum(;. unsigned int isacfg_hdr$l_header_checksum; } ISACFG_HDR;#define ISACFG_HDR$K_LENGTH 32 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _isacfg_entry {#pragma __nomember_alignment+ unsigned int isacfg_entry$l_entry_type;* unsigned int isacfg_entry$l_reserved0;) unsigned int isacfg_entry$l_isa_slot;* unsigned ( int isacfg_entry$l_reserved1;( unsigned int isacfg_entry$l_dev_num;* unsigned int isacfg_entry$l_reserved2;. unsigned int isacfg_entry$l_total_devices;* unsigned int isacfg_entry$l_reserved3;2 unsigned __int64 isacfg_entry$q_io_base_addr0;2 unsigned __int64 isacfg_entry$q_io_base_addr1;2 unsigned __int64 isacfg_entry$q_io_base_addr2;2 unsigned __int64 isacfg_entry$q_io_base_addr3;2 unsigned __int64 isacfg_entry$q_io_base_addr4;2 unsigned __int64 isacfg_entry$q_ (io_base_addr5;3 unsigned __int64 isacfg_entry$q_mem0_base_addr;0 unsigned __int64 isacfg_entry$q_mem0_length;3 unsigned __int64 isacfg_entry$q_mem1_base_addr;0 unsigned __int64 isacfg_entry$q_mem1_length;3 unsigned __int64 isacfg_entry$q_mem2_base_addr;0 unsigned __int64 isacfg_entry$q_mem2_length;2 unsigned __int64 isacfg_entry$q_rom_base_addr;/ unsigned __int64 isacfg_entry$q_rom_length;. unsigned int isacfg_entry$l_device_enable;* unsigned int isacfg_entr (y$l_reserved4;% unsigned int isacfg_entry$l_dma0;% unsigned int isacfg_entry$l_dma1;% unsigned int isacfg_entry$l_dma2;% unsigned int isacfg_entry$l_dma3;0 unsigned int isacfg_entry$l_irq0_assignment;0 unsigned int isacfg_entry$l_irq1_assignment;0 unsigned int isacfg_entry$l_irq2_assignment;0 unsigned int isacfg_entry$l_irq3_assignment;- unsigned char isacfg_entry$b_handle [16]; } ISACFG_ENTRY;!#define ISACFG_ENTRY$K_LENGTH 200#define ISACFG$K_NOT_USE(D 0#define ISACFG$K_SINGLE_DEV 1"#define ISACFG$K_MULTI_EMBED_DEV 2#define ISACFG$K_MULTI_DEV 3##define ISACFG$K_ISACFG_HDR_SIZE 32 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ISACFGDEF_LOADED */ wwY[UM/*******(********************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packa(rd Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. ( **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */F/* Source: 11-MAY-1993 14:19:26 $1$DGA8345:[LIB_H.SRC]ISDDEF.SDL;1 *//********************************************************* (***********************************************************************//*** MODULE $ISDDEF ***/#ifndef __ISDDEF_LOADED#define __ISDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_siz(e __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N (/*+ */N/* IMAGE SECTION DESCRIPTOR DEFINITIONS */N/*- */N#define ISD$K_LENDZRO 12 /*LENGTH OF DEMAND ZERO ISD */N#define ISD$C_LENDZRO 12 /*LENGTH OF DEMAND ZERO ISD */#define ISD$M_GBL 0x1#define ISD$M_CRF 0x2#define ISD$M_DZRO 0x4#define ISD$M_WRT 0x8#define IS )D$M_MATCHCTL 0x70#define ISD$M_LASTCLU 0x80#define ISD$M_INITALCODE 0x100#define ISD$M_BASED 0x200#define ISD$M_FIXUPVEC 0x400#define ISD$M_RESIDENT 0x800#define ISD$M_VECTOR 0x20000#define ISD$M_PROTECT 0x40000U#define ISD$S_FLAGSIZ 24 /* NUMBER OF FLAG BITS, ISD TYPE EXCLUDED */N#define ISD$K_LENPRIV 16 /*LENGTH OF PRIVATE ISD */N#define ISD$C_LENPRIV 16 /*LENGTH OF PRIVATE ISD */N#define ISD$K_LENGLBL 36 ) /*LENGTH OF OLD GLOBAL ISD */N#define ISD$C_LENGLBL 36 /*LENGTH OF OLD GLOBAL ISD */N#define ISD$K_MAXLENGLBL 64 /*MAX LENGTH OF NEW GLOBAL ISD */N#define ISD$C_MAXLENGLBL 64 /*MAX LENGTH OF NEW GLOBAL ISD */N/*+ */N#define ISD$K_MATALL 0 /*MATCH ALWAYS, USE GLOBAL SECTION */N#define ISD$K_MATEQU 1 /*MATCH IF ISD)$L_IDENT EQU GBL ID */N#define ISD$K_MATLEQ 2 /*MATCH IF ISD$L_IDENT LEQ GBL ID */N#define ISD$K_MATNEV 3 /*MATCH NEVER, USE PRIVATE COPY */N/*+ */N#define ISD$K_NORMAL 0 /*NORMAL PROGRAM IMAGE SECTION */N/*NO SPECIAL ACTION REQUIRED */N#define ISD$K_SHRFXD 1 /*SHAREABLE FIXED SECTION */N)#define ISD$K_PRVFXD 2 /*PRIVATE FIXED SECTION */N#define ISD$K_SHRPIC 3 /*SHAREABLE PIC SECTION */N#define ISD$K_PRVPIC 4 /*PRIVATE PIC SECTION */N#define ISD$K_USRSTACK 253 /*USER STACK SECTION */N#define ISD$S_ISDDEF 64 /* Old size name - synonym */ typedef struct _isd {N unsigned short int isd$w_size; /*SIZE IN BYTES OF THIS ISD */)N unsigned short int isd$w_pagcnt; /*! OF PAGES DESCRIBED BY THIS ISD */ __union {N unsigned int isd$l_vpnpfc; /*VPN & PFC VIELDS */ __struct {N unsigned isd$v_vpn : 21; /* STARTING VIRTUAL PAGE NUMBER */N unsigned isd$v_p1 : 1; /* P1 SPACE */N unsigned isd$v_system : 1; /* SYSTEM SPACE */N unsigned isddef$$_fill_1 : 1; /* SPARE ) */N unsigned isd$v_pfc : 8; /* PAGE FAULT CLUSTER */! } isd$r_vpnpfc_bits0; __struct {N unsigned isd$v_vpg : 23; /* VIRTUAL PAGE INCLUDING P1 & S */' unsigned isd$v_fill_0_ : 1;! } isd$r_vpnpfc_bits1; __struct {% char isddef$$_fill_4 [3];N unsigned char isd$b_pfc; /*PAGE FAULT CLUSTER */# } isd$r_vpnpfc_fields2; } isd$r_ )vpnpfc_overlay; __union {N unsigned int isd$l_flags; /*FLAGS AND ISD TYPE */ __struct {N unsigned isd$v_gbl : 1; /* GLOBAL */N unsigned isd$v_crf : 1; /* COPY ON REFERENCE */N unsigned isd$v_dzro : 1; /* DEMAND ZERO PAGE */N unsigned isd$v_wrt : 1; /* WRITABLE */N unsigned isd$v_matchctl : 3; /* IDENT )MATCH CONTROL FIELD */S unsigned isd$v_lastclu : 1; /* ISD IS PART OF LAST P0 SPACE CLUSTER */S unsigned isd$v_initalcode : 1; /* ISD IS PART OF INITIALIZATION CODE */N unsigned isd$v_based : 1; /* ISECT IS BASED */N unsigned isd$v_fixupvec : 1; /* ISECT IS FIXUP SECTION */N unsigned isd$v_resident : 1; /* ISECT IS MEMORY-RESIDENT */P unsigned isddef$$_fill_2 : 5; /* UNUSED, RESERVED FO )R FUTURE USE */P unsigned isd$v_vector : 1; /* VECTOR CONTAINED IN IMAGE SECTION */N unsigned isd$v_protect : 1; /* IMAGE SECTION IS PROTECTED */P unsigned isddef$$_fill_3 : 5; /* UNUSED, RESERVED FOR FUTURE USE */ } isd$r_flags_bits; __struct {% char isddef$$_fill_5 [3];N unsigned char isd$b_type; /*ISD TYPE CODE */! } isd$r_flags_fields; } isd$r_flags_overlay;N ) unsigned int isd$l_vbn; /*BASE VIRTUAL BLOCK NUMBER */N unsigned int isd$l_ident; /*IDENT FOR GLOBAL SECTION */N char isd$t_gblnam [44]; /*GLOBAL NAME COUNTED STRING */N/* MATCH CONTROL VIELD VALUES */N/*- */N/*BASE OF ZERO , INCR 1 */N/* ISD TYPE FIELD DEFINITI )ONS */N/*- */ } ISD; #if !defined(__VAXC)6#define isd$l_vpnpfc isd$r_vpnpfc_overlay.isd$l_vpnpfcC#define isd$v_vpn isd$r_vpnpfc_overlay.isd$r_vpnpfc_bits0.isd$v_vpnA#define isd$v_p1 isd$r_vpnpfc_overlay.isd$r_vpnpfc_bits0.isd$v_p1I#define isd$v_system isd$r_vpnpfc_overlay.isd$r_vpnpfc_bits0.isd$v_systemC#define isd$v_pfc isd$r_vpnpfc_overlay.isd$r_vpnpfc_bits0.isd$v_ )pfcC#define isd$v_vpg isd$r_vpnpfc_overlay.isd$r_vpnpfc_bits1.isd$v_vpgE#define isd$b_pfc isd$r_vpnpfc_overlay.isd$r_vpnpfc_fields2.isd$b_pfc3#define isd$l_flags isd$r_flags_overlay.isd$l_flags@#define isd$v_gbl isd$r_flags_overlay.isd$r_flags_bits.isd$v_gbl@#define isd$v_crf isd$r_flags_overlay.isd$r_flags_bits.isd$v_crfB#define isd$v_dzro isd$r_flags_overlay.isd$r_flags_bits.isd$v_dzro@#define isd$v_wrt isd$r_flags_overlay.isd$r_flags_bits.isd$v_wrtJ#define isd$v_matchctl isd$r_flags_ove )rlay.isd$r_flags_bits.isd$v_matchctlH#define isd$v_lastclu isd$r_flags_overlay.isd$r_flags_bits.isd$v_lastcluN#define isd$v_initalcode isd$r_flags_overlay.isd$r_flags_bits.isd$v_initalcodeD#define isd$v_based isd$r_flags_overlay.isd$r_flags_bits.isd$v_basedJ#define isd$v_fixupvec isd$r_flags_overlay.isd$r_flags_bits.isd$v_fixupvecJ#define isd$v_resident isd$r_flags_overlay.isd$r_flags_bits.isd$v_residentF#define isd$v_vector isd$r_flags_overlay.isd$r_flags_bits.isd$v_vectorH#define isd$v_protec )t isd$r_flags_overlay.isd$r_flags_bits.isd$v_protectD#define isd$b_type isd$r_flags_overlay.isd$r_flags_fields.isd$b_type"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ISDDEF_LOADED */ ww)Z[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyr)ight Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. ) **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */I/* Source: 11-MAY-1993 14:26:44 $1$DGA8345:[LIB_H.SRC]ISDOLDDEF.SDL;1 *//*********************************** )*********************************************************************************************//*** MODULE ISDOLDDEF ***/#ifndef __ISDOLDDEF_LOADED#define __ISDOLDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#p)ragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_ )union#endif#endif N/*+ */N/* OLD IMAGE SECTION DESCRIPTOR DEFINITIONS */N/*- */N#define ISD_K_LENDZRO 12 /*LENGTH OF DEMAND ZERO ISD */N#define ISD_C_LENDZRO 12 /*LENGTH OF DEMAND ZERO ISD */#define ISD_M_GBL 0x1#define ISD_M_CRF 0x2#define ISD_M_DZRO 0x4#defin )e ISD_M_WRT 0x8#define ISD_M_MATCHCTL 0x70#define ISD_M_LASTCLU 0x80#define ISD_M_COPYALWAY 0x100#define ISD_M_BASED 0x200#define ISD_M_FIXUPVEC 0x400#define ISD_M_VECTOR 0x20000#define ISD_M_PROTECT 0x40000U#define ISD_S_FLAGSIZ 24 /* NUMBER OF FLAG BITS, ISD TYPE EXCLUDED */N#define ISD_K_LENPRIV 16 /*LENGTH OF PRIVATE ISD */N#define ISD_C_LENPRIV 16 /*LENGTH OF PRIVATE ISD */N#define ISD_K_LENGLBL 36 ) /*LENGTH OF GLOBAL ISD */N#define ISD_C_LENGLBL 36 /*LENGTH OF GLOBAL ISD */N/*+ */N#define ISD_K_MATALL 0 /*MATCH ALWAYS, USE GLOBAL SECTION */N#define ISD_K_MATEQU 1 /*MATCH IF ISD_L_IDENT EQU GBL ID */N#define ISD_K_MATLEQ 2 /*MATCH IF ISD_L_IDENT LEQ GBL ID */N#define ISD_K_MATNEV 3 /*MATCH NEVER, U)SE PRIVATE COPY */N/*+ */N#define ISD_K_NORMAL 0 /*NORMAL PROGRAM IMAGE SECTION */N/*NO SPECIAL ACTION REQUIRED */N#define ISD_K_SHRFXD 1 /*SHAREABLE FIXED SECTION */N#define ISD_K_PRVFXD 2 /*PRIVATE FIXED SECTION */N#define ISD_K_SHRPIC 3 /*SHAREABLE PIC SECTION */N#d )efine ISD_K_PRVPIC 4 /*PRIVATE PIC SECTION */N#define ISD_K_USRSTACK 253 /*USER STACK SECTION */N#define ISD_S_ISDOLDDEF 36 /* Old size name - synonym */ typedef struct _isdold {N unsigned short int isd_w_size; /*SIZE IN BYTES OF THIS ISD */N unsigned short int isd_w_pagcnt; /*! OF PAGES DESCRIBED BY THIS ISD */ __union {N unsigned int isd_l_vpnpfc; /*VPN & PFC VIELDS ) */ __struct {N unsigned isd_v_vpn : 21; /* STARTING VIRTUAL PAGE NUMBER */N unsigned isd_v_p1 : 1; /* P1 SPACE */N unsigned isd_v_system : 1; /* SYSTEM SPACE */N unsigned isdolddef___fill_1 : 1; /* SPARE */N unsigned isd_v_pfc : 8; /* PAGE FAULT CLUSTER */! } isd_r_vpnpfc_bits0; __struct {N ) unsigned isd_v_vpg : 23; /* VIRTUAL PAGE INCLUDING P1 & S */' unsigned isd_v_fill_0_ : 1;! } isd_r_vpnpfc_bits1; __struct {( char isdolddef___fill_4 [3];N unsigned char isd_b_pfc; /*PAGE FAULT CLUSTER */# } isd_r_vpnpfc_fields2; } isd_r_vpnpfc_overlay; __union {N unsigned int isd_l_flags; /*FLAGS AND ISD TYPE */ __struct {N unsigned i)sd_v_gbl : 1; /* GLOBAL */N unsigned isd_v_crf : 1; /* COPY ON REFERENCE */N unsigned isd_v_dzro : 1; /* DEMAND ZERO PAGE */N unsigned isd_v_wrt : 1; /* WRITABLE */N unsigned isd_v_matchctl : 3; /* IDENT MATCH CONTROL FIELD */S unsigned isd_v_lastclu : 1; /* ISD IS PART OF LAST P0 SPACE CLUSTER */N unsigned isd_v_copyalway : 1; )/* COPY ALWAYS FROM USER IMAGE */N unsigned isd_v_based : 1; /* ISECT IS BASED */N unsigned isd_v_fixupvec : 1; /* ISECT IS FIXUP SECTION */S unsigned isdolddef___fill_2 : 6; /* UNUSED, RESERVED FOR FUTURE USE */P unsigned isd_v_vector : 1; /* VECTOR CONTAINED IN IMAGE SECTION */N unsigned isd_v_protect : 1; /* IMAGE SECTION IS PROTECTED */S unsigned isdolddef___fill_3 : 5; /* UNUSED, RESE )RVED FOR FUTURE USE */ } isd_r_flags_bits; __struct {( char isdolddef___fill_5 [3];N unsigned char isd_b_type; /*ISD TYPE CODE */! } isd_r_flags_fields; } isd_r_flags_overlay;N unsigned int isd_l_vbn; /*BASE VIRTUAL BLOCK NUMBER */N unsigned int isd_l_ident; /*IDENT FOR GLOBAL SECTION */N char isd_t_gblnam [16]; /*GLOBAL NAME COUNTED STRING ) */N/* MATCH CONTROL VIELD VALUES */N/*- */N/*BASE OF ZERO , INCR 1 */N/* ISD TYPE FIELD DEFINITIONS */N/*- */ } ISDOLD; #if !defined(__VAXC)6#define isd_l_vpnpfc isd_r_vpnpfc_overlay.isd_l_vpnpfcB#d )efine isd_r_vpnpfc_bits0 isd_r_vpnpfc_overlay.isd_r_vpnpfc_bits0.#define isd_v_vpn isd_r_vpnpfc_bits0.isd_v_vpn,#define isd_v_p1 isd_r_vpnpfc_bits0.isd_v_p14#define isd_v_system isd_r_vpnpfc_bits0.isd_v_system.#define isd_v_pfc isd_r_vpnpfc_bits0.isd_v_pfcB#define isd_r_vpnpfc_bits1 isd_r_vpnpfc_overlay.isd_r_vpnpfc_bits1.#define isd_v_vpg isd_r_vpnpfc_bits1.isd_v_vpgF#define isd_r_vpnpfc_fields2 isd_r_vpnpfc_overlay.isd_r_vpnpfc_fields20#define isd_b_pfc isd_r_vpnpfc_fields2.isd_b_pfc3#defin )e isd_l_flags isd_r_flags_overlay.isd_l_flags=#define isd_r_flags_bits isd_r_flags_overlay.isd_r_flags_bits,#define isd_v_gbl isd_r_flags_bits.isd_v_gbl,#define isd_v_crf isd_r_flags_bits.isd_v_crf.#define isd_v_dzro isd_r_flags_bits.isd_v_dzro,#define isd_v_wrt isd_r_flags_bits.isd_v_wrt6#define isd_v_matchctl isd_r_flags_bits.isd_v_matchctl4#define isd_v_lastclu isd_r_flags_bits.isd_v_lastclu8#define isd_v_copyalway isd_r_flags_bits.isd_v_copyalway0#define isd_v_based isd_r_flags_bits.isd )_v_based6#define isd_v_fixupvec isd_r_flags_bits.isd_v_fixupvec2#define isd_v_vector isd_r_flags_bits.isd_v_vector4#define isd_v_protect isd_r_flags_bits.isd_v_protectA#define isd_r_flags_fields isd_r_flags_overlay.isd_r_flags_fields0#define isd_b_type isd_r_flags_fields.isd_b_type"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Res!)tore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ISDOLDDEF_LOADED */ wwZ[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** au")thorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, dupli#)cated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Cre $)ated: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Source: 15-SEP-2003 13:54:22 $1$DGA8345:[LIB_H.SRC]ISRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ISRDEF ***/#ifndef __ISRDEF_LOADED#define __ISRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POI%)NTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct&)#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Definitions for Interruption Status Register */N/* */#define ISR$M_CODE 0xFFFF#define ISR$M_SHORT_CODE 0xF #define ISR$M_SHORT_')CODE4_7 0xF0#define ISR$M_HIGH_CODE 0xFF00#define ISR$M_FD_DFL 0x1#define ISR$M_FD_DFH 0x2#define ISR$M_FF_VH 0x1#define ISR$M_FF_DH 0x2#define ISR$M_FF_ZH 0x4#define ISR$M_FF_SWAH 0x8#define ISR$M_FF_VL 0x10#define ISR$M_FF_DL 0x20#define ISR$M_FF_ZL 0x40#define ISR$M_FF_SWAL 0x80#define ISR$M_FT_FP 0x1#define ISR$M_FT_MBZ1 0x2#define ISR$M_FT_MBZ2 0x4#define ISR$M_FT_SS 0x8#define ISR$M_FT_MBZ4 0x10#define ISR$M_FT_MBZ5 0x20#define ISR$M_FT_MBZ6 0x40#def()ine ISR$M_FT_OL 0x80#define ISR$M_FT_UL 0x100#define ISR$M_FT_IL 0x200#define ISR$M_FT_FPAL 0x400#define ISR$M_FT_OH 0x800#define ISR$M_FT_UH 0x1000#define ISR$M_FT_IH 0x2000#define ISR$M_FT_FPAH 0x4000#define ISR$M_FP 0x1#define ISR$M_LP 0x2#define ISR$M_TB 0x4#define ISR$M_SS 0x8#define ISR$M_UI 0x10#define ISR$M_FILL1 0xFFE0#define ISR$M_VECTOR 0xFF0000#define ISR$M_MBZ0 0xFF000000#define ISR$M_X 0x100000000#define ISR$M_W 0x200000000#define ISR$M_R 0x40))0000000#define ISR$M_NA 0x800000000#define ISR$M_SP 0x1000000000#define ISR$M_RS 0x2000000000#define ISR$M_IR 0x4000000000#define ISR$M_NI 0x8000000000#define ISR$M_SO 0x10000000000#define ISR$M_EI 0x60000000000#define ISR$M_ED 0x80000000000%#define ISR$M_MBZ2 0xFFFFF00000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef *)struct _isr {#pragma __nomember_alignment __union {3 unsigned __int64 isr$q_interruption_status; __struct { __union {N unsigned isr$v_code : 16; /* 0 Interruption Code */ __struct {Z unsigned isr$v_short_code : 4; /* Low 4 bits of code, aka code(3:0) */^ unsigned isr$v_short_code4_7 : 4; /* Next 4 bits of code, aka code(4:7) */[ unsigned isr$v_high_code :+) 8; /* In case anyone uses this separately */, } isr$r_short_code_bits;R __struct { /* Floating-point disabled status bits */_ unsigned isr$v_fd_dfl : 1; /* Fault came from low FP registers disabled */a unsigned isr$v_fd_dfh : 1; /* Fault camae from high FP registers disabled *// unsigned isr$v_fill_0_ : 6;0 } isr$r_float_disabled_bits;O __struct { ,) /* Floating-point fault status bits */- unsigned isr$v_ff_vh : 1;- unsigned isr$v_ff_dh : 1;- unsigned isr$v_ff_zh : 1;/ unsigned isr$v_ff_swah : 1;- unsigned isr$v_ff_vl : 1;- unsigned isr$v_ff_dl : 1;- unsigned isr$v_ff_zl : 1;/ unsigned isr$v_ff_swal : 1;- } isr$r_float_fault_bits;N __ -)struct { /* Floating-point trap status bits */- unsigned isr$v_ft_fp : 1;/ unsigned isr$v_ft_mbz1 : 1;/ unsigned isr$v_ft_mbz2 : 1;- unsigned isr$v_ft_ss : 1;/ unsigned isr$v_ft_mbz4 : 1;/ unsigned isr$v_ft_mbz5 : 1;/ unsigned isr$v_ft_mbz6 : 1;- unsigned isr$v_ft_ol : 1;- unsigned isr$v_ft_ul : 1;- .) unsigned isr$v_ft_il : 1;/ unsigned isr$v_ft_fpal : 1;- unsigned isr$v_ft_oh : 1;- unsigned isr$v_ft_uh : 1;- unsigned isr$v_ft_ih : 1;/ unsigned isr$v_ft_fpah : 1;/ unsigned isr$v_fill_1_ : 1;, } isr$r_float_trap_bits;N __struct { /* Various trap bits */N unsigned isr$v_fp : /)1; /* Floating point exception */N unsigned isr$v_lp : 1; /* Lower privilege transfer trap */N unsigned isr$v_tb : 1; /* Taken branch trap */N unsigned isr$v_ss : 1; /* Single step trap */] unsigned isr$v_ui : 1; /* Unimplemented instruction address trap */. unsigned isr$v_fill1 : 11;& } isr$r_trap_bits;% } isr$r_code_overlay;[ 0) unsigned isr$v_vector : 8; /* 16 IA-32 exception/interception vector number */N unsigned isr$v_mbz0 : 8; /* 24 Reserved ISR{31:24} (MBZ) */N unsigned isr$v_x : 1; /* 32 Execute excpetion */N unsigned isr$v_w : 1; /* 33 Write exception */N unsigned isr$v_r : 1; /* 34 Read exception */N unsigned isr$v_na : 1; /* 35 Non-access exception */N un1)signed isr$v_sp : 1; /* 36 Speculative load exception */N unsigned isr$v_rs : 1; /* 37 Register Stack frame */N unsigned isr$v_ir : 1; /* 38 Incomplete Register frame */N unsigned isr$v_ni : 1; /* 39 Nested interruption */N unsigned isr$v_so : 1; /* 40 IA-32 Supervisor Override */X unsigned isr$v_ei : 2; /* 41 Excepting IA-64 instruction slot number */N unsigned isr$v_ed 2): 1; /* 43 Exception Deferral */N unsigned isr$v_mbz2 : 20; /* 44 Reserved ISR{63:44} */ } isr$r_isrdef_bits; } isr$r_isr_union; } ISR; #if !defined(__VAXC)K#define isr$q_interruption_status isr$r_isr_union.isr$q_interruption_statusR#define isr$v_code isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$v_codet#define isr$v_short_code isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_short_code_bits.isr$v_short_co3)dez#define isr$v_short_code4_7 isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_short_code_bits.isr$v_short_code4_7r#define isr$v_high_code isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_short_code_bits.isr$v_high_codep#define isr$v_fd_dfl isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_disabled_bits.isr$v_fd_dflp#define isr$v_fd_dfh isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_disabled_bits.isr$v_fd_dfhk#define isr$v_ff_vh isr$r_isr_unio4)n.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_fault_bits.isr$v_ff_vhk#define isr$v_ff_dh isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_fault_bits.isr$v_ff_dhk#define isr$v_ff_zh isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_fault_bits.isr$v_ff_zho#define isr$v_ff_swah isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_fault_bits.isr$v_ff_swahk#define isr$v_ff_vl isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_fault_bits.5)isr$v_ff_vlk#define isr$v_ff_dl isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_fault_bits.isr$v_ff_dlk#define isr$v_ff_zl isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_fault_bits.isr$v_ff_zlo#define isr$v_ff_swal isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_fault_bits.isr$v_ff_swalj#define isr$v_ft_fp isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_fpn#define isr$v_ft_mbz1 isr$r_isr_union.isr$r_isrdef6)_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_mbz1n#define isr$v_ft_mbz2 isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_mbz2j#define isr$v_ft_ss isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_ssn#define isr$v_ft_mbz4 isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_mbz4n#define isr$v_ft_mbz5 isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_mbz5n7)#define isr$v_ft_mbz6 isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_mbz6j#define isr$v_ft_ol isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_olj#define isr$v_ft_ul isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_ulj#define isr$v_ft_il isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_iln#define isr$v_ft_fpal isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_ove8)rlay.isr$r_float_trap_bits.isr$v_ft_fpalj#define isr$v_ft_oh isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_ohj#define isr$v_ft_uh isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_uhj#define isr$v_ft_ih isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_ihn#define isr$v_ft_fpah isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_float_trap_bits.isr$v_ft_fpah^#define isr$v_fp isr$r_isr_u9)nion.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_trap_bits.isr$v_fp^#define isr$v_lp isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_trap_bits.isr$v_lp^#define isr$v_tb isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_trap_bits.isr$v_tb^#define isr$v_ss isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_trap_bits.isr$v_ss^#define isr$v_ui isr$r_isr_union.isr$r_isrdef_bits.isr$r_code_overlay.isr$r_trap_bits.isr$v_uid#define isr$v_fill1 isr$r_isr_union.isr$r_isrdef_bits. :)isr$r_code_overlay.isr$r_trap_bits.isr$v_fill1C#define isr$v_vector isr$r_isr_union.isr$r_isrdef_bits.isr$v_vector?#define isr$v_mbz0 isr$r_isr_union.isr$r_isrdef_bits.isr$v_mbz09#define isr$v_x isr$r_isr_union.isr$r_isrdef_bits.isr$v_x9#define isr$v_w isr$r_isr_union.isr$r_isrdef_bits.isr$v_w9#define isr$v_r isr$r_isr_union.isr$r_isrdef_bits.isr$v_r;#define isr$v_na isr$r_isr_union.isr$r_isrdef_bits.isr$v_na;#define isr$v_sp isr$r_isr_union.isr$r_isrdef_bits.isr$v_sp;#define isr$v_rs i ;)sr$r_isr_union.isr$r_isrdef_bits.isr$v_rs;#define isr$v_ir isr$r_isr_union.isr$r_isrdef_bits.isr$v_ir;#define isr$v_ni isr$r_isr_union.isr$r_isrdef_bits.isr$v_ni;#define isr$v_so isr$r_isr_union.isr$r_isrdef_bits.isr$v_so;#define isr$v_ei isr$r_isr_union.isr$r_isrdef_bits.isr$v_ei;#define isr$v_ed isr$r_isr_union.isr$r_isrdef_bits.isr$v_ed?#define isr$v_mbz2 isr$r_isr_union.isr$r_isrdef_bits.isr$v_mbz2"#endif /* #if !defined(__VAXC) */ N/* ISR codes, for general exceptions: ISR{3:0}<) */N#define ISR$C_ILLEGAL_OP 0 /* Illegal operation fault */N#define ISR$C_PRIV_OP 1 /* Privileged operation fault */N#define ISR$C_PRIV_REG 2 /* Privileged register faults */N#define ISR$C_RESVD_REG 3 /* Privileged operation fault */W#define ISR$C_ILLEGAL_ISA 4 /* Disabled instruction set transition fault */N/* ISR codes, for non-access instructions ISR{3:0} =) */N#define ISR$C_TPA 0 /* Translate physical */N#define ISR$C_FC 1 /* Flush cache */N#define ISR$C_PROBE 2 /* Non-faulting probe */N#define ISR$C_TAK 3 /* Translation access key */T#define ISR$C_LFETCH 4 /* Line fetch (faulting and non-faulting) */N#define ISR$C_PROBE_FAULT 5 /* Faulting probe */ >)#ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Dtypedef struct _isr * ISR_PQ; /* Pointer to a ISR structure. */Qtypedef struct _isr ** ISR_PPQ; /* Pointer to a pointer to a ISR structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 ISR_PQ;!typedef unsigned __int64 ISR_PPQ;##endif /?)* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ISRDEF_LOADED */ wwZ[UM/***************************************************************************/M/** @) **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** A) **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************B)************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */H/* Source: 11-MAY-1993 14:14:22 $1$DGA8345:[LIB_H.SRC]ITEMLDEF.SDL;1 *//********************************************************************************************************************************/$/*** MODULE $ITEMLDEF IDENT X-1 ***/#i C)fndef __ITEMLDEF_LOADED#define __ITEMLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus D) extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */I/* Structure used E)by DECnet-VAX internally used itemlists */N/* */N#define ITEML$K_LENGTH 12 /* Length of ItemList Header */ typedef struct _item_alloc {N unsigned int iteml$l_actlen; /* Actual length of itemlist */N void *iteml$a_pointer; /* Pointer to the start of the list */N unsigned short int iteml$w_size; /* Allocated size of the structure */N unsigned c F)har iteml$b_type; /* DYN$C_NET */N unsigned char iteml$b_subtype; /* DYN$C_NET_ITEM */#if defined(__VAXC) char iteml$t_itemlist[];#elseW/* Warning: empty char[] member for iteml$t_itemlist at end of structure not created */"#endif /* #if defined(__VAXC) */ } ITEM_ALLOC; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_sG)ize __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ITEMLDEF_LOADED */ ww Z[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and isH) not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorizI)ed to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************* J)***********/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */G/* Source: 06-FEB-2002 10:19:17 $1$DGA8345:[LIB_H.SRC]ITIRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ITIRDEF ***/#ifndef __ITIRDEF_LOADED#define __ITIRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmeK)ntR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)L)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Definitions for Interruption TLB Insertion Register (ITIR - CR21) */N/* */#define ITIR$M_MBZ0 0x3#define ITIR$M_PS 0xFC#defM)ine ITIR$M_KEY 0xFFFFFF00&#define ITIR$M_MBZ2 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _itir {#pragma __nomember_alignment __union {) unsigned __int64 itir$q_register; __struct {N unsigned itir$v_mbz0 : 2; /* CWI2 - reserved */N unsigned itir$v_ N)ps : 6; /* Page size */N unsigned itir$v_key : 24; /* Protection key */N unsigned itir$v_mbz2 : 32; /* CWI1 - reserved */" } itir$r_itirdef_bits; } itir$r_itir_union; } ITIR; #if !defined(__VAXC)9#define itir$q_register itir$r_itir_union.itir$q_registerE#define itir$v_mbz0 itir$r_itir_union.itir$r_itirdef_bits.itir$v_mbz0A#define itir$v_ps itir$r_itir_union.itir$r_itirdef_bits. O)itir$v_psC#define itir$v_key itir$r_itir_union.itir$r_itirdef_bits.itir$v_keyE#define itir$v_mbz2 itir$r_itir_union.itir$r_itirdef_bits.itir$v_mbz2"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Gtypedef struct _itir * ITIR_PQ; /* Pointer to a ITIR structure. */Stypedef struct _itir ** ITIR_PPQ; /* Pointer to a poiP)nter to a ITIR structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else!typedef unsigned __int64 ITIR_PQ;"typedef unsigned __int64 ITIR_PPQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#p Q)ragma __standard #endif /* __ITIRDEF_LOADED */ ww@H[[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permisR)sion of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, S)Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Source: 27-JUN-2017 07:13:07 $1$DGA8 T)345:[LIB_H.SRC]IVRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IVRDEF ***/#ifndef __IVRDEF_LOADED#define __IVRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __U)save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VV)AXC)#define __union union#else#define __union variant_union#endif#endif #define IVR$C_VECTOR_NMI 2#define IVR$C_VECTOR_MCE 18 #define IVR$C_VECTOR_HWCLOCK 224#define IVR$C_VECTOR_IPINT 225#define IVR$C_VECTOR_PRFMON 251O#define IVR$C_VECTOR_CMCI 252 /* Corrected Machine Check Interrupt */N#define IVR$C_VECTOR_THERMAL 253 /* Thermal Monitor */'#define IVR$C_VECTOR_BENIGN_RELEASE 254N#define IVR$C_VECTOR_SPURIOUS 255 /* X86 spuriouW)s interrupt */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IVRDEF_LOADED */ wwPo[[UM/***************************************************************************/M/** X) **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** Y)**/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*******************Z)********************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Source: 06-FEB-2002 10:20:15 $1$DGA8345:[LIB_H.SRC]IVTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $IVTDEF ***/#ifndef __IVTDEF_LOA[)DED#define __IVTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#defin\)e __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* Interruption Vector Table offsets. Offsets are from the base of the */N/* IVA (Interruption Vector Address) ]) */N#define IVT$C_OFF_VHPTFLT 0 /* VHPT Translation fault */N#define IVT$C_OFF_ITLBFLT 1024 /* Instruction TLB fault */N#define IVT$C_OFF_DTLBFLT 2048 /* Data TLB fault */N#define IVT$C_OFF_ALTITLBFLT 3072 /* Alternate ITLB fault */N#define IVT$C_OFF_ALTDTLBFLT 4096 /* Alternate DTLB fault */N#define IVT$C_OFF_NESTEDTLBFLT 5120 /* Nested TLB fault ^) */N#define IVT$C_OFF_IKEYMISSFLT 6144 /* Inst Key Miss fault */N#define IVT$C_OFF_DKEYMISSFLT 7168 /* Data Key Miss fault */N#define IVT$C_OFF_DIRTYBITFLT 8192 /* Dirty-Bit fault */N#define IVT$C_OFF_IACCESSBITFLT 9216 /* Inst Access-Bit fault */N#define IVT$C_OFF_DACCESSBITFLT 10240 /* Data Access-Bit fault */N#define IVT$C_OFF_BREAKFLT 11264 /* Break Inst fault */N#define IVT$_)C_OFF_EXTINT 12288 /* External Interrupt */N/* Offsets %X3400 to %X4C00 are reserved */N#define IVT$C_OFF_3400 13312 /* Reserved */N#define IVT$C_OFF_3800 14336 /* Reserved */N#define IVT$C_OFF_3C00 15360 /* Reserved */N#define IVT$C_OFF_4000 16384 /* Reserved */N#define IVT$C_OFF_4400 17408 `) /* Reserved */N#define IVT$C_OFF_4800 18432 /* Reserved */N#define IVT$C_OFF_4C00 19456 /* Reserved */N#define IVT$C_OFF_PAGENOTPFLT 20480 /* Page Not Present fault */N#define IVT$C_OFF_KEYPERMFLT 20736 /* Key Permission fault */N#define IVT$C_OFF_IACCESSRTFLT 20992 /* Inst Access-Rights fault */N#define IVT$C_OFF_DACCESSRTFLT 21248 /* Data Access-Rights faa)ult */N#define IVT$C_OFF_GPFLT 21504 /* General Exception fault */N#define IVT$C_OFF_FPDISFLT 21760 /* Disable-FP fault */N#define IVT$C_OFF_NATFLT 22016 /* NAT Consumption fault */N#define IVT$C_OFF_SPECLNFLT 22272 /* Speculation fault */N#define IVT$C_OFF_5800 22528 /* Reserved */N#define IVT$C_OFF_DBGFLT 22784 /* Debug fault */N#define IVb)T$C_OFF_ALIGNFLT 23040 /* Unaligned Reference fault */N#define IVT$C_OFF_LOCKDREFFLT 23296 /* Locked Data Reference fault */N#define IVT$C_OFF_FPFLT 23552 /* Floating Point fault */N#define IVT$C_OFF_FPTRAP 23808 /* Floating Point Trap */N#define IVT$C_OFF_LOPRIVTRAP 24064 /* Lower-Privilege Transfer Trap */N#define IVT$C_OFF_TAKENBRTRAP 24320 /* Taken Branch Trap */N#define IVT$C_OFF_SSTEPTRAP 24576 c) /* Single Step Trap */N/* Offsets %X6100 to %X6800 are reserved */N#define IVT$C_OFF_6100 24832 /* Reserved */N#define IVT$C_OFF_6200 25088 /* Reserved */N#define IVT$C_OFF_6300 25344 /* Reserved */N#define IVT$C_OFF_6400 25600 /* Reserved */N#define IVT$C_OFF_6500 25856 /* Reserved d) */N#define IVT$C_OFF_6600 26112 /* Reserved */N#define IVT$C_OFF_6700 26368 /* Reserved */N#define IVT$C_OFF_6800 26624 /* Reserved */N#define IVT$C_OFF_IA32EXCEPTN 26880 /* iA32 Exception */N#define IVT$C_OFF_IA32INTERCEPT 27136 /* iA32 Intercept */N#define IVT$C_OFF_IA32INT 27392 /* iA32 Interrupt */N/* Offsee)ts %X6C00 to %X7F00 are reserved */N#define IVT$C_OFF_6C00 27648 /* Reserved */N#define IVT$C_OFF_6D00 27904 /* Reserved */N#define IVT$C_OFF_6E00 28160 /* Reserved */N#define IVT$C_OFF_6F00 28416 /* Reserved */N#define IVT$C_OFF_7000 28672 /* Reserved */N#define IVT$C_OFF_7100 28928 f) /* Reserved */N#define IVT$C_OFF_7200 29184 /* Reserved */N#define IVT$C_OFF_7300 29440 /* Reserved */N#define IVT$C_OFF_7400 29696 /* Reserved */N#define IVT$C_OFF_7500 29952 /* Reserved */N#define IVT$C_OFF_7600 30208 /* Reserved */N#define IVT$C_OFF_7700 30464 /* Reserved g) */N#define IVT$C_OFF_7800 30720 /* Reserved */N#define IVT$C_OFF_7900 30976 /* Reserved */N#define IVT$C_OFF_7A00 31232 /* Reserved */N#define IVT$C_OFF_7B00 31488 /* Reserved */N#define IVT$C_OFF_7C00 31744 /* Reserved */N#define IVT$C_OFF_7D00 32000 /* Reserved */N#definh)e IVT$C_OFF_7E00 32256 /* Reserved */N#define IVT$C_OFF_7F00 32512 /* Reserved */N/* Size of Interrupt Vector Table */N#define IVT$C_SIZE 32768 /* Size in bytes of the IVT */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previoui)sly-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __IVTDEF_LOADED */ wwp[[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used,j) duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed tk)o anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15 l):22:32 by OpenVMS SDL V3.7 */F/* Source: 13-NOV-2017 10:29:54 $1$DGA8345:[LIB_H.SRC]JIBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $JIBDEF ***/#ifndef __JIBDEF_LOADED#define __JIBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defim)ned whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __n)struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* Job Information Block - Structure containing common context for a set */N/* of related processes. */N/* */O/* Note: The Execuo)tive module SYSCREPRC assumes that the job mount list head */N/* preceeds the username field in the JIB. */N/* */N/* JIB Synchronization: */N/* */N/* The JIB is a shared structure across a subprocess tree. Synchronization */N/* is complex because many of the quota anp)d limit fields have no functional */M/* relationship whatsoever. So a number of methods of synchronization are */K/* used, based on exactly what is being manipulated. Below is a list of */I/* fields with their methods of synch. */N/* */@/* Field Synchronization Method */@/* ----- ---------------------- */P/* BYTCNT/BYTLM Intq)erlocked arithmetic sequences. Should never be manually */C/* manipulated: use the EXE$DEBIT/CREDIT routines in the */;/* EXSUBROUT module. */N/* */O/* TQCNT/TQLM Interlocked arithmetic sequences. When waiting because of a */I/* lack of TQCNT, the JIB FLAGS bit TQCNT_WAITERS must be set; */C/* the JIB address is the EFWM and the process should be */D/* r) placed in the MWAIT queue. When TQCNT is incremented, */H/* the TQCNT_WAITERS bit must be interrogated. If it is set, */G/* then waiting process should be made executable via a call */;/* to EXE$JIB_AVAIL or similar inline code. */N/* */M/* PGFLCNT Interlocked arithmetic sequences. Should never be manually */K/* manipulated to charge for pagefile quota: use $more_pgflquotas) */I/* macro. Macros $init_pgflquota and $ret_pgflquota are also */;/* available. */N/* */E/* PGFLQUOTA MMG spinlock. */N/* */E/* MTLFL/MTLBL SCH$IOLOCK/UNLOCK. */N/* t) */Y/* FILCNT/FILLM, Interlocked arithmetic sequences. These fields are never increased */[/* ENQCNT/ENQLM, or decreased by more than 1 at a time, and are never waited on. */N/* PRCCNT/PRCLM */N/*- */#define JIB$C_DETACHED 0#define JIB$C_NETWORK 1#define JIB$C_BATCH 2#define JIB$C_LOCAL 3#define JIB$C_DIALUP 4#define JIB$C_u)REMOTE 5 #define JIB$M_BYTCNT_WAITERS 0x1#define JIB$M_TQCNT_WAITERS 0x2#define JIB$M_MEDDLE 0x4N#define JIB$K_LENGTH 140 /* Structure length */N#define JIB$C_LENGTH 140 /* Structure length */N#define JIB$S_JIBDEF 140 /* Old JIB sized for compatability */  9#ifdef __cplusplus /* Define structure prototypes */ struct _mtl; #endif /* #ifdef __cplusplus */ typedef struct _jib {W struct _mtl *jv)ib$l_mtlfl; /* Job mounted volume list head forward link */T struct _mtl *jib$l_mtlbl; /* Job mounted volume list head back link */N unsigned short int jib$w_size; /* Size of structure in bytes */N unsigned char jib$b_type; /* Structure type code */V unsigned char jib$b_daytypes; /* Set bits 0-6 flag non-prime days of week */N char jib$t_username [12]; /* User name for easy access */N char jib$t_accouw)nt [8]; /* Account name for resident access */N unsigned int jib$l_bytcnt; /* Buffered I/O byte count avail */N unsigned int jib$l_bytlm; /* Original value for Byte count */N unsigned int jib$l_pbytcnt; /* Paged pool byte count remaining */N unsigned int jib$l_pbytlim; /* Paged pool byte limit */N unsigned int jib$l_filcnt; /* Open File count remaining */N unsigned int jib$l_fillm; /* Opex)n file limit */O unsigned int jib$l_tqcnt; /* Timer queue entry count remaining */N unsigned int jib$l_tqlm; /* Timer queue entry limit */N unsigned int jib$l_pgflquota; /* Paging file quota */O int jib$l_pgflcnt; /* Paging file limit *** signed *** */N unsigned int jib$l_cpulim; /* CPU time quota remaining */N unsigned int jib$l_prccnt; /* Count of subprocesses exiy)sting */N unsigned int jib$l_prclim; /* Limit on number of subprocesses */O unsigned short int jib$w_shrfcnt; /* Shared file block count remaining */N unsigned short int jib$w_shrflim; /* Shared file count limit */N unsigned int jib$l_enqcnt; /* Enqueue count avail */N unsigned int jib$l_enqlm; /* Enqueue limit */N unsigned short int jib$w_maxjobs; /* Max jobs limit on user */N unsignedz) short int jib$w_maxdetach; /* Max detached processes for user */N unsigned int jib$l_mpid; /* PID of master process */U void *jib$l_jlnamfl; /* Forward link for job-wide logical names */R void *jib$l_jlnambl; /* Back link for job-wide logical names */Q unsigned int jib$l_pdayhours; /* Field describing primary day access */N unsigned int jib$l_odayhours; /* Field describing off day access */N unsigned int jib$l {)_jobtype; /* Job origin type */ __union {N unsigned int jib$l_flags; /* FLAG bits */ __struct {T unsigned jib$v_bytcnt_waiters : 1; /* Processes are waiting on BYTCNT */R unsigned jib$v_tqcnt_waiters : 1; /* Processes are waiting on TQCNT */N unsigned jib$v_meddle : 1; /* Job table has been altered */' unsigned jib$v_fill_0_ : 5; } jib$r_flag_bits; |) } jib$r_flags_overlay;N unsigned int jib$l_org_bytlm; /* Original BYTLM */N unsigned int jib$l_org_pbytlm; /* Original PBYTLM */N unsigned int jib$l_jtquota; /* Job table quota */ } JIB; #if !defined(__VAXC)3#define jib$l_flags jib$r_flags_overlay.jib$l_flagsU#define jib$v_bytcnt_waiters jib$r_flags_overlay.jib$r_flag_bits.jib$v_bytcnt_waitersS#define jib$v_tqcnt_waiters jib$r_flags_overlay.jib$r_flag_b})its.jib$v_tqcnt_waitersE#define jib$v_meddle jib$r_flags_overlay.jib$r_flag_bits.jib$v_meddle"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __JIBDEF_LOADED */ ww \[UM/***************~)************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enter)prise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. ) **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */I/* Source: 25-MAR-1993 14:44:52 $1$DGA8345:[LIB_H.SRC]KA0202DEF.SDL;1 *//************************************************************* )*******************************************************************//*** MODULE $KA0202DEF ***/#ifndef __KA0202DEF_LOADED#define __KA0202DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer)_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif) "#define KA0202$K_MAX_CPU_MODULES 2%#define KA0202$K_MAX_MEMORY_MODULES 4'#define KA0202$M_IOCSR_ENET_HLT_ENA 0x1##define KA0202$M_IOCSR_ENET_HLT 0x2(#define KA0202$M_IOCSR_FBUS_HLT_ENA 0x10$#define KA0202$M_IOCSR_FBUS_HLT 0x20(#define KA0202$M_IOCSR_FBUS_INT_STS 0x40(#define KA0202$M_IOCSR_FBUS_RESET_L 0x80*#define KA0202$M_IOCSR_FBUS_PWR_FAIL 0x100&#define KA0202$M_IOCSR_MBX_ENA_L 0x200+#define KA0202$M_IOCSR_FBUS_DMA_ENA_L 0x400+#define KA0202$M_IOCSR_LBUS_DMA_ENA_L 0x800&#defin )e KA0202$M_IOCSR_CA_WWP_0 0x1000&#define KA0202$M_IOCSR_CA_WWP_2 0x2000(#define KA0202$M_IOCSR_DATA_WWP_L 0x4000+#define KA0202$M_IOCSR_FMBPR_RESET_L 0x8000,#define KA0202$M_IOCSR_LMBPR_RESET_L 0x10000+#define KA0202$M_IOCSR_LBUS_RESET_L 0x20000-#define KA0202$M_IOCSR_FBUS_COMP_PE_L 0x40000-#define KA0202$M_IOCSR_LBUS_COMP_PE_L 0x800000#define KA0202$M_IOCSR_FBUS_RESET_H 0x8000000000.#define KA0202$M_IOCSR_MBX_ENA_H 0x200000000003#define KA0202$M_IOCSR_FBUS_DMA_ENA_H 0x400000000003#def )ine KA0202$M_IOCSR_LBUS_DMA_ENA_H 0x80000000000.#define KA0202$M_IOCSR_CA_WWP_1 0x100000000000.#define KA0202$M_IOCSR_CA_WWP_3 0x2000000000000#define KA0202$M_IOCSR_DATA_WWP_H 0x4000000000003#define KA0202$M_IOCSR_FMBPR_RESET_H 0x8000000000004#define KA0202$M_IOCSR_LMBPR_RESET_H 0x10000000000003#define KA0202$M_IOCSR_LBUS_RESET_H 0x20000000000005#define KA0202$M_IOCSR_FBUS_COMP_PE_H 0x40000000000005#define KA0202$M_IOCSR_LBUS_COMP_PE_H 0x8000000000000)#define KA0202$M_CERR1_UNCORR_RDERR_)L 0x1"#define KA0202$M_CERR1_NOACK_L 0x2&#define KA0202$M_CERR1_CMDADR_PE_L 0x4'#define KA0202$M_CERR1_MCMDADR_PE_L 0x8'#define KA0202$M_CERR1_WRTDAT_PE_L 0x10(#define KA0202$M_CERR1_MWRTDAT_PE_L 0x20&#define KA0202$M_CERR1_RDDAT_PE_L 0x40'#define KA0202$M_CERR1_MRDDAT_PE_L 0x80*#define KA0202$M_CERR1_CMDADR_PE_LW0 0x100*#define KA0202$M_CERR1_CMDADR_PE_LW2 0x200'#define KA0202$M_CERR1_DAT_PE_LW0 0x400'#define KA0202$M_CERR1_DAT_PE_LW2 0x800(#define KA0202$M_CERR1_DAT_PE_LW4 0x1000( )#define KA0202$M_CERR1_DAT_PE_LW6 0x2000+#define KA0202$M_CERR1_CSTALL_SYNC_H 0x4000*#define KA0202$M_CERR1_FBUS_MBX_ERR 0x8000.#define KA0202$M_CERR1_CMD_WRTDAT_PE_L 0x10000'#define KA0202$M_CERR1_BUS_SYNC 0x200001#define KA0202$M_CERR1_UNCORR_RDERR_H 0x100000000*#define KA0202$M_CERR1_NOACK_H 0x200000000.#define KA0202$M_CERR1_CMDADR_PE_H 0x400000000/#define KA0202$M_CERR1_MCMDADR_PE_H 0x800000000/#define KA0202$M_CERR1_WRTDAT_PE_H 0x10000000000#define KA0202$M_CERR1_MWRTDAT_PE_H 0x20 )00000000.#define KA0202$M_CERR1_RDDAT_PE_H 0x4000000000/#define KA0202$M_CERR1_MRDDAT_PE_H 0x80000000002#define KA0202$M_CERR1_CMDADR_PE_LW1 0x100000000002#define KA0202$M_CERR1_CMDADR_PE_LW3 0x20000000000/#define KA0202$M_CERR1_DAT_PE_LW1 0x40000000000/#define KA0202$M_CERR1_DAT_PE_LW3 0x800000000000#define KA0202$M_CERR1_DAT_PE_LW5 0x1000000000000#define KA0202$M_CERR1_DAT_PE_LW7 0x2000000000003#define KA0202$M_CERR1_CSTALL_SYNC_L 0x400000000000.#define KA0202$M_CERR1_LBUS_MBX 0x800000 )0000006#define KA0202$M_CERR1_CMD_WRTDAT_PE_H 0x1000000000000##define KA0202$M_CERR2_L 0xFFFFFFFF+#define KA0202$M_CERR2_H 0xFFFFFFFF00000000*#define KA0202$M_LMBPR_MBX_ADDR 0xFFFFFFC0*#define KA0202$M_FMBPR_MBX_ADDR 0xFFFFFFC0%#define KA0202$M_FIVECT_VECTOR 0xFFFF%#define KA0202$M_FHVECT_VECTOR 0xFFFF$#define KA0202$M_FERR1_DATA_PE_L 0x1$#define KA0202$M_FERR1_ADDR_PE_L 0x2'#define KA0202$M_FERR1_FILL1 0xFFFFFFFC,#define KA0202$M_FERR1_DATA_PE_H 0x100000000,#define KA0202$M_FERR1_ADD)R_PE_H 0x200000000##define KA0202$M_LINT_SCSI0_IRQ 0x1##define KA0202$M_LINT_SCSI1_IRQ 0x2##define KA0202$M_LINT_SCSI2_IRQ 0x4##define KA0202$M_LINT_SCSI3_IRQ 0x8$#define KA0202$M_LINT_SCSI4_IRQ 0x10)#define KA0202$M_LINT_SLU_IRQ 0x100000000)#define KA0202$M_LINT_NI0_IRQ 0x200000000)#define KA0202$M_LINT_NI1_IRQ 0x400000000*#define KA0202$M_LINT_SBUS_IRQ 0x800000000#define KA0202$M_LERR1_EVEN 0x1&#define KA0202$M_LERR1_ODD 0x100000000#define KA0202$K_LENGTH 57344X#define KA0202 )$S_KA0202DEF 57344 /* Old size name, synonym for KA0202$S_KA0202 */ typedef struct _ka0202 { __union { __int64 ka0202$q_iocsr; __struct {P unsigned ka0202$v_iocsr_enet_hlt_ena : 1; /* Ethernet halt enable */N unsigned ka0202$v_iocsr_enet_hlt : 1; /* Ethernet halt */N unsigned ka0202$v_iocsr_fill1 : 2; /* Filler */Q unsigned ka0202$v_iocsr_fbus_hlt_ena : 1; /* Futurebus halt enable */N ) unsigned ka0202$v_iocsr_fbus_hlt : 1; /* Futurebus halt */V unsigned ka0202$v_iocsr_fbus_int_sts : 1; /* Futurebus interrupt status */N unsigned ka0202$v_iocsr_fbus_reset_l : 1; /* Fbus reset */P unsigned ka0202$v_iocsr_fbus_pwr_fail : 1; /* Fbus power fail msg */N unsigned ka0202$v_iocsr_mbx_ena_l : 1; /* Mailbox enable even */W unsigned ka0202$v_iocsr_fbus_dma_ena_l : 1; /* Futurebus DMA enable even */R ) unsigned ka0202$v_iocsr_lbus_dma_ena_l : 1; /* Lbus DMA enable even */\ unsigned ka0202$v_iocsr_ca_wwp_0 : 1; /* Command/address write wrong parity 0 */\ unsigned ka0202$v_iocsr_ca_wwp_2 : 1; /* Command/address write wrong parity 2 */V unsigned ka0202$v_iocsr_data_wwp_l : 1; /* Data write wrong parity even */W unsigned ka0202$v_iocsr_fmbpr_reset_l : 1; /* Reset fbus mbx pointer reg */W unsigned ka0202$v_iocsr_lmbpr_reset_l : 1; /* Reset )lbus mbx pointer reg */N unsigned ka0202$v_iocsr_lbus_reset_l : 1; /* Lbus reset */Y unsigned ka0202$v_iocsr_fbus_comp_pe_l : 1; /* Fbus complement parity even */Y unsigned ka0202$v_iocsr_lbus_comp_pe_l : 1; /* Lbus complement parity even *// unsigned ka0202$v_iocsr_fill2 : 12;. unsigned ka0202$v_iocsr_fill3 : 7;N unsigned ka0202$v_iocsr_fbus_reset_h : 1; /* Fbus reset */. unsigned ka0202$v_iocsr_fi)ll4 : 1;N unsigned ka0202$v_iocsr_mbx_ena_h : 1; /* Mailbox enable odd */V unsigned ka0202$v_iocsr_fbus_dma_ena_h : 1; /* Futurebus DMA enable odd */Q unsigned ka0202$v_iocsr_lbus_dma_ena_h : 1; /* Lbus DMA enable odd */\ unsigned ka0202$v_iocsr_ca_wwp_1 : 1; /* Command/address write wrong parity 1 */\ unsigned ka0202$v_iocsr_ca_wwp_3 : 1; /* Command/address write wrong parity 3 */U unsigned ka0202$v_iocsr_data_wwp_h : 1; /* D)ata write wrong parity odd */W unsigned ka0202$v_iocsr_fmbpr_reset_h : 1; /* Reset fbus mbx pointer reg */W unsigned ka0202$v_iocsr_lmbpr_reset_h : 1; /* Reset lbus mbx pointer reg */N unsigned ka0202$v_iocsr_lbus_reset_h : 1; /* Lbus reset */Y unsigned ka0202$v_iocsr_fbus_comp_pe_h : 1; /* Fbus complement parity even */Y unsigned ka0202$v_iocsr_lbus_comp_pe_h : 1; /* Lbus complement parity even */* unsigned ka0202$v_ )fill_0_ : 4;" } ka0202$r_iocsr_bits;! } ka0202$r_iocsr_overlay; char ka0202$b_fill1 [24]; __union { __int64 ka0202$q_cerr1; __struct {V unsigned ka0202$v_cerr1_uncorr_rderr_l : 1; /* Uncorrectable read error */N unsigned ka0202$v_cerr1_noack_l : 1; /* No acknowledge error */\ unsigned ka0202$v_cerr1_cmdadr_pe_l : 1; /* Command address parity error even */d unsigned ka0202$v_cerr1_mcmdadr_pe_l : 1; )/* Missed command address parity error even */W unsigned ka0202$v_cerr1_wrtdat_pe_l : 1; /* Write data parity error even */_ unsigned ka0202$v_cerr1_mwrtdat_pe_l : 1; /* Missed write data parity error even */U unsigned ka0202$v_cerr1_rddat_pe_l : 1; /* Read data parity error even */] unsigned ka0202$v_cerr1_mrddat_pe_l : 1; /* Missed read data parity error even */d unsigned ka0202$v_cerr1_cmdadr_pe_lw0 : 1; /* Command address parity error) longword 0 */d unsigned ka0202$v_cerr1_cmdadr_pe_lw2 : 1; /* Command address parity error longword 2 */V unsigned ka0202$v_cerr1_dat_pe_lw0 : 1; /* Data parity error longword 0 */V unsigned ka0202$v_cerr1_dat_pe_lw2 : 1; /* Data parity error longword 2 */V unsigned ka0202$v_cerr1_dat_pe_lw4 : 1; /* Data parity error longword 4 */V unsigned ka0202$v_cerr1_dat_pe_lw6 : 1; /* Data parity error longword 6 */6 unsigned ka0202$v_cerr1_)cstall_sync_h : 1;S unsigned ka0202$v_cerr1_fbus_mbx_err : 1; /* Futurebus mailbox error */8 unsigned ka0202$v_cerr1_cmd_wrtdat_pe_l : 1;1 unsigned ka0202$v_cerr1_bus_sync : 1;N unsigned ka0202$v_cerr1_fill1 : 14; /* Filler */V unsigned ka0202$v_cerr1_uncorr_rderr_h : 1; /* Uncorrectable read error */N unsigned ka0202$v_cerr1_noack_h : 1; /* No acknowledge error */\ unsigned ka0202$v_cerr1_cmdadr)_pe_h : 1; /* Command address parity error even */d unsigned ka0202$v_cerr1_mcmdadr_pe_h : 1; /* Missed command address parity error even */W unsigned ka0202$v_cerr1_wrtdat_pe_h : 1; /* Write data parity error even */_ unsigned ka0202$v_cerr1_mwrtdat_pe_h : 1; /* Missed write data parity error even */U unsigned ka0202$v_cerr1_rddat_pe_h : 1; /* Read data parity error even */] unsigned ka0202$v_cerr1_mrddat_pe_h : 1; /* Missed read data par)ity error even */d unsigned ka0202$v_cerr1_cmdadr_pe_lw1 : 1; /* Command address parity error longword 0 */d unsigned ka0202$v_cerr1_cmdadr_pe_lw3 : 1; /* Command address parity error longword 2 */V unsigned ka0202$v_cerr1_dat_pe_lw1 : 1; /* Data parity error longword 0 */V unsigned ka0202$v_cerr1_dat_pe_lw3 : 1; /* Data parity error longword 2 */V unsigned ka0202$v_cerr1_dat_pe_lw5 : 1; /* Data parity error longword 4 */V unsign )ed ka0202$v_cerr1_dat_pe_lw7 : 1; /* Data parity error longword 6 */6 unsigned ka0202$v_cerr1_cstall_sync_l : 1;N unsigned ka0202$v_cerr1_lbus_mbx : 1; /* Lbus mailbox error */8 unsigned ka0202$v_cerr1_cmd_wrtdat_pe_h : 1;* unsigned ka0202$v_fill_1_ : 7;" } ka0202$r_cerr1_bits;! } ka0202$r_cerr1_overlay; char ka0202$b_fill2 [24]; __union {N unsigned __int64 ka0202$q_cerr2; /* Cobra Error register 2 */) __struct {+ unsigned ka0202$v_cerr2_l : 32;+ unsigned ka0202$v_cerr2_h : 32;" } ka0202$r_cerr2_bits;! } ka0202$r_cerr2_overlay; char ka0202$b_fill3 [24]; __union { __int64 ka0202$q_cerr3;! } ka0202$r_cerr3_overlay; char ka0202$b_fill4 [24]; __union { __int64 ka0202$q_lmbpr; __struct {N unsigned ka0202$v_lmbpr_fill1 : 6; /* Filler */N unsi )gned ka0202$v_lmbpr_mbx_addr : 26; /* Lbus mailbox address */" } ka0202$r_lmbpr_bits;! } ka0202$r_lmbpr_overlay; char ka0202$b_fill5 [24]; __union { __int64 ka0202$q_fmbpr; __struct {N unsigned ka0202$v_fmbpr_fill1 : 6; /* Filler */R unsigned ka0202$v_fmbpr_mbx_addr : 26; /* Futurebus mailbox address */" } ka0202$r_fmbpr_bits;! } ka0202$r_fmbpr_overlay; char ka0202$b_fill6 [24];) __union {! __int64 ka0202$q_diagcsr;# } ka0202$r_diagcsr_overlay; char ka0202$b_fill7 [24]; __union { __int64 ka0202$q_fivect; __struct {R unsigned ka0202$v_fivect_vector : 16; /* Futurebus interrupt vector */# } ka0202$r_fivect_bits;" } ka0202$r_fivect_overlay; char ka0202$b_fill8 [24]; __union { __int64 ka0202$q_fhvect; __struct {N unsigned ka0202$v_fhvect_vector : 16 ); /* Futurebus halt vector */# } ka0202$r_fhvect_bits;" } ka0202$r_fhvect_overlay; char ka0202$b_fill9 [24]; __union { __int64 ka0202$q_ferr1; __struct {2 unsigned ka0202$v_ferr1_data_pe_l : 1;2 unsigned ka0202$v_ferr1_addr_pe_l : 1;/ unsigned ka0202$v_ferr1_fill1 : 30;2 unsigned ka0202$v_ferr1_data_pe_h : 1;2 unsigned ka0202$v_ferr1_addr_pe_h : 1;* unsigned ka0202$v_fill_2_ ): 6;" } ka0202$r_ferr1_bits;! } ka0202$r_ferr1_overlay; char ka0202$b_fill10 [24]; __union { __int64 ka0202$q_ferr2;! } ka0202$r_ferr2_overlay; char ka0202$b_fill11 [24]; __union { __int64 ka0202$q_lint; __struct {T unsigned ka0202$v_lint_scsi0_irq : 1; /* SCSI bus 0 interrupt request */T unsigned ka0202$v_lint_scsi1_irq : 1; /* SCSI bus 1 interrupt request */T unsigned ka0202$v_lint_s)csi2_irq : 1; /* SCSI bus 2 interrupt request */T unsigned ka0202$v_lint_scsi3_irq : 1; /* SCSI bus 3 interrupt request */T unsigned ka0202$v_lint_scsi4_irq : 1; /* SCSI bus 4 interrupt request */N unsigned ka0202$v_lint_fill1 : 27; /* Filler */X unsigned ka0202$v_lint_slu_irq : 1; /* Seriel line unit interrupt request */R unsigned ka0202$v_lint_ni0_irq : 1; /* Ethernet 0 interrupt request */R unsigned ka0202$v_ )lint_ni1_irq : 1; /* Ethernet 1 interrupt request */S unsigned ka0202$v_lint_sbus_irq : 1; /* Serial bus interrupt request */* unsigned ka0202$v_fill_3_ : 4;! } ka0202$r_lint_bits; } ka0202$r_lint_overlay; char ka0202$b_fill12 [24]; __union { __int64 ka0202$q_lerr1; __struct {N unsigned ka0202$v_lerr1_even : 1; /* Even error */N unsigned ka0202$v_lerr1_fill1 : 31; /* Filler ) */N unsigned ka0202$v_lerr1_odd : 1; /* Odd error */* unsigned ka0202$v_fill_4_ : 7;" } ka0202$r_lerr1_bits;! } ka0202$r_lerr1_overlay; char ka0202$b_fill13 [24]; __union { __int64 ka0202$q_lerr2;! } ka0202$r_lerr2_overlay; char ka0202$b_fill14 [7768];! __int64 ka0202$q_cpu0 [1024];! __int64 ka0202$q_cpu1 [1024];! __int64 ka0202$q_cmm0 [1024];! __int64 ka0202$q_cmm1 [1024];! ) __int64 ka0202$q_cmm2 [1024];! __int64 ka0202$q_cmm3 [1024]; } KA0202; #if !defined(__VAXC)<#define ka0202$q_iocsr ka0202$r_iocsr_overlay.ka0202$q_iocsrj#define ka0202$v_iocsr_enet_hlt_ena ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_enet_hlt_enab#define ka0202$v_iocsr_enet_hlt ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_enet_hltj#define ka0202$v_iocsr_fbus_hlt_ena ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fbus_hlt_enab#define ka0202$v)_iocsr_fbus_hlt ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fbus_hltj#define ka0202$v_iocsr_fbus_int_sts ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fbus_int_stsj#define ka0202$v_iocsr_fbus_reset_l ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fbus_reset_ll#define ka0202$v_iocsr_fbus_pwr_fail ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fbus_pwr_faild#define ka0202$v_iocsr_mbx_ena_l ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_mbx_e)na_ln#define ka0202$v_iocsr_fbus_dma_ena_l ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fbus_dma_ena_ln#define ka0202$v_iocsr_lbus_dma_ena_l ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_lbus_dma_ena_lb#define ka0202$v_iocsr_ca_wwp_0 ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_ca_wwp_0b#define ka0202$v_iocsr_ca_wwp_2 ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_ca_wwp_2f#define ka0202$v_iocsr_data_wwp_l ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits).ka0202$v_iocsr_data_wwp_ll#define ka0202$v_iocsr_fmbpr_reset_l ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fmbpr_reset_ll#define ka0202$v_iocsr_lmbpr_reset_l ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_lmbpr_reset_lj#define ka0202$v_iocsr_lbus_reset_l ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_lbus_reset_ln#define ka0202$v_iocsr_fbus_comp_pe_l ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fbus_comp_pe_ln#define ka0202$v_iocsr_lbus_comp_pe_l )ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_lbus_comp_pe_lj#define ka0202$v_iocsr_fbus_reset_h ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fbus_reset_hd#define ka0202$v_iocsr_mbx_ena_h ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_mbx_ena_hn#define ka0202$v_iocsr_fbus_dma_ena_h ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fbus_dma_ena_hn#define ka0202$v_iocsr_lbus_dma_ena_h ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_lbus_dma_ena_h)b#define ka0202$v_iocsr_ca_wwp_1 ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_ca_wwp_1b#define ka0202$v_iocsr_ca_wwp_3 ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_ca_wwp_3f#define ka0202$v_iocsr_data_wwp_h ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_data_wwp_hl#define ka0202$v_iocsr_fmbpr_reset_h ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fmbpr_reset_hl#define ka0202$v_iocsr_lmbpr_reset_h ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_i)ocsr_lmbpr_reset_hj#define ka0202$v_iocsr_lbus_reset_h ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_lbus_reset_hn#define ka0202$v_iocsr_fbus_comp_pe_h ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_fbus_comp_pe_hn#define ka0202$v_iocsr_lbus_comp_pe_h ka0202$r_iocsr_overlay.ka0202$r_iocsr_bits.ka0202$v_iocsr_lbus_comp_pe_h<#define ka0202$q_cerr1 ka0202$r_cerr1_overlay.ka0202$q_cerr1n#define ka0202$v_cerr1_uncorr_rderr_l ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_ce)rr1_uncorr_rderr_l`#define ka0202$v_cerr1_noack_l ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_noack_lh#define ka0202$v_cerr1_cmdadr_pe_l ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_cmdadr_pe_lj#define ka0202$v_cerr1_mcmdadr_pe_l ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_mcmdadr_pe_lh#define ka0202$v_cerr1_wrtdat_pe_l ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_wrtdat_pe_lj#define ka0202$v_cerr1_mwrtdat_pe_l ka0202$r_cerr1_overlay.ka0202$r_)cerr1_bits.ka0202$v_cerr1_mwrtdat_pe_lf#define ka0202$v_cerr1_rddat_pe_l ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_rddat_pe_lh#define ka0202$v_cerr1_mrddat_pe_l ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_mrddat_pe_ll#define ka0202$v_cerr1_cmdadr_pe_lw0 ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_cmdadr_pe_lw0l#define ka0202$v_cerr1_cmdadr_pe_lw2 ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_cmdadr_pe_lw2f#define ka0202$v_cerr1_dat_pe_lw0 ka)0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_dat_pe_lw0f#define ka0202$v_cerr1_dat_pe_lw2 ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_dat_pe_lw2f#define ka0202$v_cerr1_dat_pe_lw4 ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_dat_pe_lw4f#define ka0202$v_cerr1_dat_pe_lw6 ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_dat_pe_lw6l#define ka0202$v_cerr1_cstall_sync_h ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_cstall_sync_hj#define ka0202$v)_cerr1_fbus_mbx_err ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_fbus_mbx_errp#define ka0202$v_cerr1_cmd_wrtdat_pe_l ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_cmd_wrtdat_pe_lb#define ka0202$v_cerr1_bus_sync ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_bus_syncn#define ka0202$v_cerr1_uncorr_rderr_h ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_uncorr_rderr_h`#define ka0202$v_cerr1_noack_h ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1)_noack_hh#define ka0202$v_cerr1_cmdadr_pe_h ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_cmdadr_pe_hj#define ka0202$v_cerr1_mcmdadr_pe_h ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_mcmdadr_pe_hh#define ka0202$v_cerr1_wrtdat_pe_h ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_wrtdat_pe_hj#define ka0202$v_cerr1_mwrtdat_pe_h ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_mwrtdat_pe_hf#define ka0202$v_cerr1_rddat_pe_h ka0202$r_cerr1_overlay.ka0202$r_ce)rr1_bits.ka0202$v_cerr1_rddat_pe_hh#define ka0202$v_cerr1_mrddat_pe_h ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_mrddat_pe_hl#define ka0202$v_cerr1_cmdadr_pe_lw1 ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_cmdadr_pe_lw1l#define ka0202$v_cerr1_cmdadr_pe_lw3 ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_cmdadr_pe_lw3f#define ka0202$v_cerr1_dat_pe_lw1 ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_dat_pe_lw1f#define ka0202$v_cerr1_dat_pe_lw3 ka0202)$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_dat_pe_lw3f#define ka0202$v_cerr1_dat_pe_lw5 ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_dat_pe_lw5f#define ka0202$v_cerr1_dat_pe_lw7 ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_dat_pe_lw7l#define ka0202$v_cerr1_cstall_sync_l ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_cstall_sync_lb#define ka0202$v_cerr1_lbus_mbx ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_lbus_mbxp#define ka0202$v_cerr1_c)md_wrtdat_pe_h ka0202$r_cerr1_overlay.ka0202$r_cerr1_bits.ka0202$v_cerr1_cmd_wrtdat_pe_h<#define ka0202$q_cerr2 ka0202$r_cerr2_overlay.ka0202$q_cerr2T#define ka0202$v_cerr2_l ka0202$r_cerr2_overlay.ka0202$r_cerr2_bits.ka0202$v_cerr2_lT#define ka0202$v_cerr2_h ka0202$r_cerr2_overlay.ka0202$r_cerr2_bits.ka0202$v_cerr2_h<#define ka0202$q_cerr3 ka0202$r_cerr3_overlay.ka0202$q_cerr3<#define ka0202$q_lmbpr ka0202$r_lmbpr_overlay.ka0202$q_lmbprb#define ka0202$v_lmbpr_mbx_addr ka0202$r_lmbpr_overlay.ka0)202$r_lmbpr_bits.ka0202$v_lmbpr_mbx_addr<#define ka0202$q_fmbpr ka0202$r_fmbpr_overlay.ka0202$q_fmbprb#define ka0202$v_fmbpr_mbx_addr ka0202$r_fmbpr_overlay.ka0202$r_fmbpr_bits.ka0202$v_fmbpr_mbx_addrB#define ka0202$q_diagcsr ka0202$r_diagcsr_overlay.ka0202$q_diagcsr?#define ka0202$q_fivect ka0202$r_fivect_overlay.ka0202$q_fivectb#define ka0202$v_fivect_vector ka0202$r_fivect_overlay.ka0202$r_fivect_bits.ka0202$v_fivect_vector?#define ka0202$q_fhvect ka0202$r_fhvect_overlay.ka0202$q_fhvectb#d)efine ka0202$v_fhvect_vector ka0202$r_fhvect_overlay.ka0202$r_fhvect_bits.ka0202$v_fhvect_vector<#define ka0202$q_ferr1 ka0202$r_ferr1_overlay.ka0202$q_ferr1d#define ka0202$v_ferr1_data_pe_l ka0202$r_ferr1_overlay.ka0202$r_ferr1_bits.ka0202$v_ferr1_data_pe_ld#define ka0202$v_ferr1_addr_pe_l ka0202$r_ferr1_overlay.ka0202$r_ferr1_bits.ka0202$v_ferr1_addr_pe_l\#define ka0202$v_ferr1_fill1 ka0202$r_ferr1_overlay.ka0202$r_ferr1_bits.ka0202$v_ferr1_fill1d#define ka0202$v_ferr1_data_pe_h ka0202$r_ferr1_)overlay.ka0202$r_ferr1_bits.ka0202$v_ferr1_data_pe_hd#define ka0202$v_ferr1_addr_pe_h ka0202$r_ferr1_overlay.ka0202$r_ferr1_bits.ka0202$v_ferr1_addr_pe_h<#define ka0202$q_ferr2 ka0202$r_ferr2_overlay.ka0202$q_ferr29#define ka0202$q_lint ka0202$r_lint_overlay.ka0202$q_lint`#define ka0202$v_lint_scsi0_irq ka0202$r_lint_overlay.ka0202$r_lint_bits.ka0202$v_lint_scsi0_irq`#define ka0202$v_lint_scsi1_irq ka0202$r_lint_overlay.ka0202$r_lint_bits.ka0202$v_lint_scsi1_irq`#define ka0202$v_lint_scsi2_irq )ka0202$r_lint_overlay.ka0202$r_lint_bits.ka0202$v_lint_scsi2_irq`#define ka0202$v_lint_scsi3_irq ka0202$r_lint_overlay.ka0202$r_lint_bits.ka0202$v_lint_scsi3_irq`#define ka0202$v_lint_scsi4_irq ka0202$r_lint_overlay.ka0202$r_lint_bits.ka0202$v_lint_scsi4_irq\#define ka0202$v_lint_slu_irq ka0202$r_lint_overlay.ka0202$r_lint_bits.ka0202$v_lint_slu_irq\#define ka0202$v_lint_ni0_irq ka0202$r_lint_overlay.ka0202$r_lint_bits.ka0202$v_lint_ni0_irq\#define ka0202$v_lint_ni1_irq ka0202$r_lint_overlay.ka02 )02$r_lint_bits.ka0202$v_lint_ni1_irq^#define ka0202$v_lint_sbus_irq ka0202$r_lint_overlay.ka0202$r_lint_bits.ka0202$v_lint_sbus_irq<#define ka0202$q_lerr1 ka0202$r_lerr1_overlay.ka0202$q_lerr1Z#define ka0202$v_lerr1_even ka0202$r_lerr1_overlay.ka0202$r_lerr1_bits.ka0202$v_lerr1_evenX#define ka0202$v_lerr1_odd ka0202$r_lerr1_overlay.ka0202$r_lerr1_bits.ka0202$v_lerr1_odd<#define ka0202$q_lerr2 ka0202$r_lerr2_overlay.ka0202$q_lerr2"#endif /* #if !defined(__VAXC) */ (#define KA0202_CPU$M_BCC_E )NB_ALLOC_L 0x1*#define KA0202_CPU$M_BCC_FRC_FILL_SH_L 0x2&#define KA0202_CPU$M_BCC_ENB_TPC_L 0x4'#define KA0202_CPU$M_BCC_FILL_WTP_L 0x8(#define KA0202_CPU$M_BCC_FILL_WCP_L 0x10)#define KA0202_CPU$M_BCC_FILL_WDTP_L 0x20'#define KA0202_CPU$M_BCC_ENB_CEI_L 0x40(#define KA0202_CPU$M_BCC_ENB_EDCC_L 0x80,#define KA0202_CPU$M_BCC_ENB_EDC_CHK_L 0x100+#define KA0202_CPU$M_BCC_ENB_BC_CIO_L 0x200*#define KA0202_CPU$M_BCC_DIS_BLK_W_L 0x400,#define KA0202_CPU$M_BCC_ENB_BC_INIT_L 0x800*#define KA02 )02_CPU$M_BCC_FOR_EDCC_L 0x1000(#define KA0202_CPU$M_BCC_SH_D_V_L 0xE000)#define KA0202_CPU$M_BCC_EDC_L 0x3FFF00000#define KA0202_CPU$M_BCC_CACHE_SIZE_L 0xC00000000#define KA0202_CPU$M_BCC_ENB_ALLOC_H 0x1000000002#define KA0202_CPU$M_BCC_FRC_FILL_SH_H 0x200000000.#define KA0202_CPU$M_BCC_ENB_TPC_H 0x400000000/#define KA0202_CPU$M_BCC_FILL_WTP_H 0x8000000000#define KA0202_CPU$M_BCC_FILL_WCP_H 0x10000000001#define KA0202_CPU$M_BCC_FILL_WDTP_H 0x2000000000/#define KA0202_CPU$M_BCC_ENB_CEI_H 0 )x40000000000#define KA0202_CPU$M_BCC_ENB_EDCC_H 0x80000000004#define KA0202_CPU$M_BCC_ENB_EDC_CHK_H 0x100000000003#define KA0202_CPU$M_BCC_ENB_BC_CIO_H 0x200000000002#define KA0202_CPU$M_BCC_DIS_BLK_W_H 0x400000000004#define KA0202_CPU$M_BCC_ENB_BC_INIT_H 0x800000000002#define KA0202_CPU$M_BCC_FOR_EDCC_H 0x1000000000000#define KA0202_CPU$M_BCC_SH_D_V_H 0xE000000000003#define KA0202_CPU$M_BCC_EDC_L_H 0x3FFF0000000000008#define KA0202_CPU$M_BCC_CACHE_SIZE_H 0xC000000000000000N#define KA0202 )_BCC$K_CACHE_SIZE_512K 0 /* Cache size is 512Kb */N#define KA0202_BCC$K_CACHE_SIZE_1MB 1 /* Cache size is 1Mb */N#define KA0202_BCC$K_CACHE_SIZE_4MB 2 /* Cache size is 4Mb */!#define KA0202_CPU$M_BCCE_MCE 0x4 #define KA0202_CPU$M_BCCE_CE 0x8)#define KA0202_CPU$M_BCCE_CNTRL_PAR 0x100"#define KA0202_CPU$M_BCCE_SH 0x200%#define KA0202_CPU$M_BCCE_DIRTY 0x400%#define KA0202_CPU$M_BCCE_VALID 0x800*#define KA0202_CPU$M_BCCE_BC_EDC_L 0x20000.#defin )e KA0202_CPU$M_BCCE_EDC_SYND_0 0x1FC0000/#define KA0202_CPU$M_BCCE_EDC_SYND_2 0xFE000000+#define KA0202_CPU$M_BCCE_MCE_H 0x100000000*#define KA0202_CPU$M_BCCE_CE_H 0x2000000002#define KA0202_CPU$M_BCCE_READ_ONLY 0x7FFC000000001#define KA0202_CPU$M_BCCE_BC_EDC_H 0x8000000000005#define KA0202_CPU$M_BCCE_EDC_SYND_1 0x7F0000000000007#define KA0202_CPU$M_BCCE_EDC_SYND_3 0x3F80000000000000,#define KA0202_CPU$M_BCCEA_BCMAP_OFF 0x1FFFF*#define KA0202_CPU$M_BCCEA_TAG_PAR 0x40000/#define KA0202_C )PU$M_BCCEA_TAG_VALUE 0x7FF800006#define KA0202_CPU$M_BCCEA_BCMAP_OFF_H 0x1FFFF000000004#define KA0202_CPU$M_BCCEA_TAG_PAR_H 0x40000000000009#define KA0202_CPU$M_BCCEA_TAG_VALUE_H 0x7FF8000000000000!#define KA0202_CPU$M_BCUE_MPE 0x1 #define KA0202_CPU$M_BCUE_PE 0x2%#define KA0202_CPU$M_BCUE_MUNCE_L 0x4$#define KA0202_CPU$M_BCUE_UNCE_L 0x8(#define KA0202_CPU$M_BCUE_CTRL_PAR 0x100"#define KA0202_CPU$M_BCUE_SH 0x200%#define KA0202_CPU$M_BCUE_DIRTY 0x400%#define KA0202_CPU$M_BCUE_VALID 0x80 )0*#define KA0202_CPU$M_BCUE_BC_EDC_L 0x20000.#define KA0202_CPU$M_BCUE_EDC_SYND_0 0x1FC0000/#define KA0202_CPU$M_BCUE_EDC_SYND_2 0xFE000000*#define KA0202_CPU$M_BCUE_PE_H 0x100000000-#define KA0202_CPU$M_BCUE_MUNCE_H 0x200000000,#define KA0202_CPU$M_BCUE_UNCE_H 0x4000000002#define KA0202_CPU$M_BCUE_BC_EDC_H 0x10000000000005#define KA0202_CPU$M_BCUE_EDC_SYND_1 0xFE0000000000007#define KA0202_CPU$M_BCUE_EDC_SYND_3 0x7F00000000000000,#define KA0202_CPU$M_BCUEA_BCMAP_OFF 0x1FFFF&#define KA )0202_CPU$M_BCUEA_PTP 0x20000%#define KA0202_CPU$M_BCUEA_TP 0x40000(#define KA0202_CPU$M_BCUEA_TV 0x7FF800005#define KA0202_CPU$M_BCUEA_BCMAP_OFF_H 0xFFFF800000000#define KA0202_CPU$M_BCUEA_PTP_H 0x1000000000000/#define KA0202_CPU$M_BCUEA_TP_H 0x20000000000002#define KA0202_CPU$M_BCUEA_TV_H 0x3FFC000000000000 #define KA0202_CPU$M_MDTER_L 0x1#define KA0202_CPU$M_DTER_L 0x2&#define KA0202_CPU$M_DTER_TOFF_L 0x3FC.#define KA0202_CPU$M_DTER_DUP_TAG_L 0x3FFFFC00(#define KA0202_CPU$M_DTER_DTP )0x40000000(#define KA0202_CPU$M_MDTER_H 0x100000000'#define KA0202_CPU$M_DTER_H 0x200000000,#define KA0202_CPU$M_DTER_DT_H 0x3FC000000006#define KA0202_CPU$M_DTER_DUP_TAG_H 0x3FFFFC00000000002#define KA0202_CPU$M_DTER_DTP_H 0x4000000000000000"#define KA0202_CPU$M_CBCTL_DWP 0x1##define KA0202_CPU$M_CBCTL_CAWP 0x6"#define KA0202_CPU$M_CBCTL_EPC 0x8&#define KA0202_CPU$M_CBCTL_FRC_SH 0x10(#define KA0202_CPU$M_CBCTL_CMDER_ID 0xE0$#define KA0202_CPU$M_CBCTL_ACM 0x700'#define KA0202_CPU$M_CBCTL )_ENB_CI 0x800$#define KA0202_CPU$M_CBCTL_RD 0x1000*#define KA0202_CPU$M_CBCTL_QW_2_SEL 0x2000+#define KA0202_CPU$M_CBCTL_SEL_DRACK 0x4000,#define KA0202_CPU$M_CBCTL_DWP_H 0x100000000-#define KA0202_CPU$M_CBCTL_CAWP_H 0x600000000,#define KA0202_CPU$M_CBCTL_EPC_H 0x8000000000#define KA0202_CPU$M_CBCTL_FRC_SH_H 0x10000000002#define KA0202_CPU$M_CBCTL_CMDER_ID_H 0xE000000000.#define KA0202_CPU$M_CBCTL_ACM_H 0x700000000001#define KA0202_CPU$M_CBCTL_ENB_CI_H 0x80000000000.#define KA0202_CPU$M )_CBCTL_RD_H 0x1000000000004#define KA0202_CPU$M_CBCTL_QW_2_SEL_H 0x2000000000005#define KA0202_CPU$M_CBCTL_SEL_DRACK_H 0x400000000000!#define KA0202_CPU$M_CBE_RD_L 0x2"#define KA0202_CPU$M_CBE_CAP_L 0x4##define KA0202_CPU$M_CBE_MCAP_L 0x8&#define KA0202_CPU$M_CBE_PE_WRD_L 0x10'#define KA0202_CPU$M_CBE_MPE_WRD_L 0x20%#define KA0202_CPU$M_CBE_PE_RD_L 0x40&#define KA0202_CPU$M_CBE_MPE_RD_L 0x80(#define KA0202_CPU$M_CBE_CA_PE_LW0 0x100(#define KA0202_CPU$M_CBE_CA_PE_LW2 0x200'#define KA02 )02_CPU$M_CBE_D_PE_LW0 0x400'#define KA0202_CPU$M_CBE_D_PE_LW2 0x800(#define KA0202_CPU$M_CBE_D_PE_LW4 0x1000(#define KA0202_CPU$M_CBE_D_PE_LW6 0x2000'#define KA0202_CPU$M_CBE_CA_NACK 0x4000,#define KA0202_CPU$M_CBE_WR_DATA_NACK 0x8000*#define KA0202_CPU$M_CBE_MCOUNT 0x7E000000.#define KA0202_CPU$M_CBE_MADR_VALID 0x80000000)#define KA0202_CPU$M_CBE_RD_H 0x200000000*#define KA0202_CPU$M_CBE_CAP_H 0x400000000+#define KA0202_CPU$M_CBE_MCAP_H 0x800000000.#define KA0202_CPU$M_CBE_PE_WRD_H 0x )1000000000/#define KA0202_CPU$M_CBE_MPE_WRD_H 0x2000000000-#define KA0202_CPU$M_CBE_PE_RD_H 0x4000000000.#define KA0202_CPU$M_CBE_MPE_RD_H 0x80000000000#define KA0202_CPU$M_CBE_CA_PE_LW1 0x100000000000#define KA0202_CPU$M_CBE_CA_PE_LW3 0x20000000000/#define KA0202_CPU$M_CBE_D_PE_LW1 0x40000000000/#define KA0202_CPU$M_CBE_D_PE_LW3 0x800000000000#define KA0202_CPU$M_CBE_D_PE_LW5 0x1000000000000#define KA0202_CPU$M_CBE_D_PE_LW7 0x2000000000001#define KA0202_CPU$M_CBE_UNDEFINED 0x40000000000 )02#define KA0202_CPU$M_CBE_UNDEFINED2 0x8000000000004#define KA0202_CPU$M_CBE_MCOUNT_H 0x7E000000000000008#define KA0202_CPU$M_CBE_MADR_VALID_H 0x8000000000000000##define KA0202_CPU$M_CBEAL_SBO1 0x30#define KA0202_CPU$M_CBEAL_ADDR_CAD_L 0xFFFFFFFC+#define KA0202_CPU$M_CBEAL_SBO2 0x3000000008#define KA0202_CPU$M_CBEAL_ADDR_CAD_H 0xFFFFFFFC00000000##define KA0202_CPU$M_CBEAH_SBO1 0x3'#define KA0202_CPU$M_CBEAH_EA_L 0x3FFFC,#define KA0202_CPU$M_CBEAH_T_TYPE_L 0x1C0000-#define KA0202_CPU$M )_CBEAH_CMDR_ID_L 0xE00000*#define KA0202_CPU$M_CBEAH_SBO2 0xFF000000+#define KA0202_CPU$M_CBEAH_SBO3 0x300000000/#define KA0202_CPU$M_CBEAH_EA_H 0x3FFFC000000004#define KA0202_CPU$M_CBEAH_T_TYPE_H 0x1C0000000000005#define KA0202_CPU$M_CBEAH_CMDR_ID_H 0xE00000000000002#define KA0202_CPU$M_CBEAH_SBO4 0xFF00000000000000'#define KA0202_CPU$M_IPIR_UNDEFINED 0x11#define KA0202_CPU$M_IPIR_REQ_INT_CPU 0x100000000&#define KA0202_CPU$M_SIC_UNDEFINED 0x1'#define KA0202_CPU$M_SIC_UNDEFINED1 0x2 )#define KA0202_CPU$M_SIC_EIC 0x4.#define KA0202_CPU$M_SIC_IT_ICLEAR 0x1000000000#define KA0202_CPU$M_SIC_SYS_EVT_CLR 0x200000000/#define KA0202_CPU$M_SIC_UNDEFINED2 0x400000000$#define KA0202_CPU$M_ADLK_LA_V_L 0x1)#define KA0202_CPU$M_ADLK_LA_L 0xFFFFFFF8,#define KA0202_CPU$M_ADLK_LA_V_H 0x1000000001#define KA0202_CPU$M_ADLK_LA_H 0xFFFFFFF800000000&#define KA0202_CPU$M_MADRL_VALID_L 0x1'#define KA0202_CPU$M_MADRL_T_TYPE_L 0x2/#define KA0202_CPU$M_MADRL_ADDRESS_L 0xFFFFFFFC.#define KA02 )02_CPU$M_MADRL_VALID_H 0x100000000/#define KA0202_CPU$M_MADRL_T_TYPE_H 0x2000000007#define KA0202_CPU$M_MADRL_ADDRESS_H 0xFFFFFFFC00000000 #define KA0202_CPU$K_LENGTH 8192a#define KA0202_CPU$S_CPUDEF 8192 /* Old size name, synonym for KA0202_CPU$$S_KA0202CPU */ typedef struct _ka0202cpu { __union {! __int64 ka0202_cpu$q_bcc; __struct {6 unsigned ka0202_cpu$v_bcc_enb_alloc_l : 1;8 unsigned ka0202_cpu$v_bcc_frc_fill_sh_l : 1;4 ) unsigned ka0202_cpu$v_bcc_enb_tpc_l : 1;5 unsigned ka0202_cpu$v_bcc_fill_wtp_l : 1;5 unsigned ka0202_cpu$v_bcc_fill_wcp_l : 1;6 unsigned ka0202_cpu$v_bcc_fill_wdtp_l : 1;4 unsigned ka0202_cpu$v_bcc_enb_cei_l : 1;5 unsigned ka0202_cpu$v_bcc_enb_edcc_l : 1;8 unsigned ka0202_cpu$v_bcc_enb_edc_chk_l : 1;7 unsigned ka0202_cpu$v_bcc_enb_bc_cio_l : 1;6 unsigned ka0202_cpu$v_bcc_dis_blk_w_l : 1;8 ) unsigned ka0202_cpu$v_bcc_enb_bc_init_l : 1;5 unsigned ka0202_cpu$v_bcc_for_edcc_l : 1;3 unsigned ka0202_cpu$v_bcc_sh_d_v_l : 3;1 unsigned ka0202_cpu$v_bcc_edc_l : 14;7 unsigned ka0202_cpu$v_bcc_cache_size_l : 2;6 unsigned ka0202_cpu$v_bcc_enb_alloc_h : 1;8 unsigned ka0202_cpu$v_bcc_frc_fill_sh_h : 1;4 unsigned ka0202_cpu$v_bcc_enb_tpc_h : 1;5 unsigned ka0202_cpu$v_bcc_fill_wtp_h : 1;5 )unsigned ka0202_cpu$v_bcc_fill_wcp_h : 1;6 unsigned ka0202_cpu$v_bcc_fill_wdtp_h : 1;4 unsigned ka0202_cpu$v_bcc_enb_cei_h : 1;5 unsigned ka0202_cpu$v_bcc_enb_edcc_h : 1;8 unsigned ka0202_cpu$v_bcc_enb_edc_chk_h : 1;7 unsigned ka0202_cpu$v_bcc_enb_bc_cio_h : 1;6 unsigned ka0202_cpu$v_bcc_dis_blk_w_h : 1;8 unsigned ka0202_cpu$v_bcc_enb_bc_init_h : 1;5 unsigned ka0202_cpu$v_bcc_for_edcc_h : 1;3 ) unsigned ka0202_cpu$v_bcc_sh_d_v_h : 3;3 unsigned ka0202_cpu$v_bcc_edc_l_h : 14;7 unsigned ka0202_cpu$v_bcc_cache_size_h : 2;$ } ka0202_cpu$r_bcc_bits;# } ka0202_cpu$r_bcc_overlay;# char ka0202_cpu$b_fill13a [24]; __union {" __int64 ka0202_cpu$q_bcce; __struct {1 unsigned ka0202_cpu$v_bcce_fill1 : 2;/ unsigned ka0202_cpu$v_bcce_mce : 1;. unsigned ka0202_cpu$v_bcce_ce : 1;1 )unsigned ka0202_cpu$v_bcce_fill2 : 4;5 unsigned ka0202_cpu$v_bcce_cntrl_par : 1;. unsigned ka0202_cpu$v_bcce_sh : 1;1 unsigned ka0202_cpu$v_bcce_dirty : 1;1 unsigned ka0202_cpu$v_bcce_valid : 1;1 unsigned ka0202_cpu$v_bcce_fill3 : 5;4 unsigned ka0202_cpu$v_bcce_bc_edc_l : 1;6 unsigned ka0202_cpu$v_bcce_edc_synd_0 : 7;6 unsigned ka0202_cpu$v_bcce_edc_synd_2 : 7;1 unsigned ka0202_cpu$v_bcce_m )ce_h : 1;0 unsigned ka0202_cpu$v_bcce_ce_h : 1;6 unsigned ka0202_cpu$v_bcce_read_only : 13;4 unsigned ka0202_cpu$v_bcce_bc_edc_h : 1;6 unsigned ka0202_cpu$v_bcce_edc_synd_1 : 7;6 unsigned ka0202_cpu$v_bcce_edc_synd_3 : 7;. unsigned ka0202_cpu$v_fill_5_ : 2;% } ka0202_cpu$r_bcce_bits;$ } ka0202_cpu$r_bcce_overlay;# char ka0202_cpu$b_fill13b [24]; __union {# __int64 ka0202_cpu$q_bccea; ) __struct {7 unsigned ka0202_cpu$v_bccea_bcmap_off : 17;2 unsigned ka0202_cpu$v_bccea_fill1 : 1;4 unsigned ka0202_cpu$v_bccea_tag_par : 1;7 unsigned ka0202_cpu$v_bccea_tag_value : 12;2 unsigned ka0202_cpu$v_bccea_fill2 : 1;9 unsigned ka0202_cpu$v_bccea_bcmap_off_h : 17;4 unsigned ka0202_cpu$v_bccea_fill1_h : 1;6 unsigned ka0202_cpu$v_bccea_tag_par_h : 1;9 unsigned ka0202_cpu$v_bccea_tag_ )value_h : 12;4 unsigned ka0202_cpu$v_bccea_fill2_h : 1;& } ka0202_cpu$r_bccea_bits;% } ka0202_cpu$r_bccea_overlay;$ char ka0202_cpu$b_fill13b1 [24]; __union {" __int64 ka0202_cpu$q_bcue; __struct {/ unsigned ka0202_cpu$v_bcue_mpe : 1;. unsigned ka0202_cpu$v_bcue_pe : 1;3 unsigned ka0202_cpu$v_bcue_munce_l : 1;2 unsigned ka0202_cpu$v_bcue_unce_l : 1;1 unsigned ka0202_cpu$v_bcue_f )ill1 : 4;4 unsigned ka0202_cpu$v_bcue_ctrl_par : 1;. unsigned ka0202_cpu$v_bcue_sh : 1;1 unsigned ka0202_cpu$v_bcue_dirty : 1;1 unsigned ka0202_cpu$v_bcue_valid : 1;1 unsigned ka0202_cpu$v_bcue_fill2 : 5;4 unsigned ka0202_cpu$v_bcue_bc_edc_l : 1;6 unsigned ka0202_cpu$v_bcue_edc_synd_0 : 7;6 unsigned ka0202_cpu$v_bcue_edc_synd_2 : 7;0 unsigned ka0202_cpu$v_bcue_pe_h : 1;3 unsigned ) ka0202_cpu$v_bcue_munce_h : 1;2 unsigned ka0202_cpu$v_bcue_unce_h : 1;2 unsigned ka0202_cpu$v_bcue_fill3 : 13;4 unsigned ka0202_cpu$v_bcue_bc_edc_h : 1;6 unsigned ka0202_cpu$v_bcue_edc_synd_1 : 7;6 unsigned ka0202_cpu$v_bcue_edc_synd_3 : 7;. unsigned ka0202_cpu$v_fill_6_ : 1;% } ka0202_cpu$r_bcue_bits;$ } ka0202_cpu$r_bcue_overlay;# char ka0202_cpu$b_fill13c [24]; __union {# __int64 ka0202 )_cpu$q_bcuea; __struct {7 unsigned ka0202_cpu$v_bcuea_bcmap_off : 17;0 unsigned ka0202_cpu$v_bcuea_ptp : 1;/ unsigned ka0202_cpu$v_bcuea_tp : 1;0 unsigned ka0202_cpu$v_bcuea_tv : 12;9 unsigned ka0202_cpu$v_bcuea_bcmap_off_h : 17;2 unsigned ka0202_cpu$v_bcuea_ptp_h : 1;1 unsigned ka0202_cpu$v_bcuea_tp_h : 1;2 unsigned ka0202_cpu$v_bcuea_tv_h : 12;. unsigned ka0202_cpu$v_fill_7_ : )2;& } ka0202_cpu$r_bcuea_bits;% } ka0202_cpu$r_bcuea_overlay;# char ka0202_cpu$b_fill13d [24]; __union {" __int64 ka0202_cpu$q_dter; __struct {. unsigned ka0202_cpu$v_mdter_l : 1;- unsigned ka0202_cpu$v_dter_l : 1;2 unsigned ka0202_cpu$v_dter_toff_l : 8;6 unsigned ka0202_cpu$v_dter_dup_tag_l : 20;/ unsigned ka0202_cpu$v_dter_dtp : 1;1 unsigned ka0202_cpu$v_dter_fill1 : 1;. ) unsigned ka0202_cpu$v_mdter_h : 1;- unsigned ka0202_cpu$v_dter_h : 1;0 unsigned ka0202_cpu$v_dter_dt_h : 8;6 unsigned ka0202_cpu$v_dter_dup_tag_h : 20;1 unsigned ka0202_cpu$v_dter_dtp_h : 1;3 unsigned ka0202_cpu$v_dter_fill1_h : 1;% } ka0202_cpu$r_dter_bits;$ } ka0202_cpu$r_dter_overlay;# char ka0202_cpu$b_fill13e [24]; __union {# __int64 ka0202_cpu$q_cbctl; __struct {0 ) unsigned ka0202_cpu$v_cbctl_dwp : 1;1 unsigned ka0202_cpu$v_cbctl_cawp : 2;0 unsigned ka0202_cpu$v_cbctl_epc : 1;3 unsigned ka0202_cpu$v_cbctl_frc_sh : 1;5 unsigned ka0202_cpu$v_cbctl_cmder_id : 3;0 unsigned ka0202_cpu$v_cbctl_acm : 3;3 unsigned ka0202_cpu$v_cbctl_enb_ci : 1;/ unsigned ka0202_cpu$v_cbctl_rd : 1;5 unsigned ka0202_cpu$v_cbctl_qw_2_sel : 1;6 unsigned ka0202_cpu$v_cbctl_sel_ )drack : 1;3 unsigned ka0202_cpu$v_cbctl_fill1 : 17;2 unsigned ka0202_cpu$v_cbctl_dwp_h : 1;3 unsigned ka0202_cpu$v_cbctl_cawp_h : 2;2 unsigned ka0202_cpu$v_cbctl_epc_h : 1;5 unsigned ka0202_cpu$v_cbctl_frc_sh_h : 1;7 unsigned ka0202_cpu$v_cbctl_cmder_id_h : 3;2 unsigned ka0202_cpu$v_cbctl_acm_h : 3;5 unsigned ka0202_cpu$v_cbctl_enb_ci_h : 1;1 unsigned ka0202_cpu$v_cbctl_rd_h : 1;7 ) unsigned ka0202_cpu$v_cbctl_qw_2_sel_h : 1;8 unsigned ka0202_cpu$v_cbctl_sel_drack_h : 1;5 unsigned ka0202_cpu$v_cbctl_fill1_h : 17;& } ka0202_cpu$r_cbctl_bits;% } ka0202_cpu$r_cbctl_overlay;# char ka0202_cpu$b_fill13f [24]; __union {! __int64 ka0202_cpu$q_cbe; __struct {0 unsigned ka0202_cpu$v_cbe_fill1 : 1;/ unsigned ka0202_cpu$v_cbe_rd_l : 1;0 unsigned ka0202_cpu$v_cbe_cap_l : 1;1 ) unsigned ka0202_cpu$v_cbe_mcap_l : 1;3 unsigned ka0202_cpu$v_cbe_pe_wrd_l : 1;4 unsigned ka0202_cpu$v_cbe_mpe_wrd_l : 1;2 unsigned ka0202_cpu$v_cbe_pe_rd_l : 1;3 unsigned ka0202_cpu$v_cbe_mpe_rd_l : 1;4 unsigned ka0202_cpu$v_cbe_ca_pe_lw0 : 1;4 unsigned ka0202_cpu$v_cbe_ca_pe_lw2 : 1;3 unsigned ka0202_cpu$v_cbe_d_pe_lw0 : 1;3 unsigned ka0202_cpu$v_cbe_d_pe_lw2 : 1;3 unsigned ka0 )202_cpu$v_cbe_d_pe_lw4 : 1;3 unsigned ka0202_cpu$v_cbe_d_pe_lw6 : 1;2 unsigned ka0202_cpu$v_cbe_ca_nack : 1;7 unsigned ka0202_cpu$v_cbe_wr_data_nack : 1;0 unsigned ka0202_cpu$v_cbe_fill2 : 9;1 unsigned ka0202_cpu$v_cbe_mcount : 6;5 unsigned ka0202_cpu$v_cbe_madr_valid : 1;0 unsigned ka0202_cpu$v_cbe_fill3 : 1;/ unsigned ka0202_cpu$v_cbe_rd_h : 1;0 unsigned ka0202_cpu$v_cbe_cap_h : 1;1 ) unsigned ka0202_cpu$v_cbe_mcap_h : 1;3 unsigned ka0202_cpu$v_cbe_pe_wrd_h : 1;4 unsigned ka0202_cpu$v_cbe_mpe_wrd_h : 1;2 unsigned ka0202_cpu$v_cbe_pe_rd_h : 1;3 unsigned ka0202_cpu$v_cbe_mpe_rd_h : 1;4 unsigned ka0202_cpu$v_cbe_ca_pe_lw1 : 1;4 unsigned ka0202_cpu$v_cbe_ca_pe_lw3 : 1;3 unsigned ka0202_cpu$v_cbe_d_pe_lw1 : 1;3 unsigned ka0202_cpu$v_cbe_d_pe_lw3 : 1;3 unsigned ka0202_ )cpu$v_cbe_d_pe_lw5 : 1;3 unsigned ka0202_cpu$v_cbe_d_pe_lw7 : 1;4 unsigned ka0202_cpu$v_cbe_undefined : 1;5 unsigned ka0202_cpu$v_cbe_undefined2 : 1;2 unsigned ka0202_cpu$v_cbe_fill2_h : 9;3 unsigned ka0202_cpu$v_cbe_mcount_h : 6;7 unsigned ka0202_cpu$v_cbe_madr_valid_h : 1;$ } ka0202_cpu$r_cbe_bits;# } ka0202_cpu$r_cbe_overlay;# char ka0202_cpu$b_fill13g [24]; __union {# __int64 ka0202)_cpu$q_cbeal; __struct {1 unsigned ka0202_cpu$v_cbeal_sbo1 : 2;8 unsigned ka0202_cpu$v_cbeal_addr_cad_l : 30;1 unsigned ka0202_cpu$v_cbeal_sbo2 : 2;8 unsigned ka0202_cpu$v_cbeal_addr_cad_h : 30;& } ka0202_cpu$r_cbeal_bits;% } ka0202_cpu$r_cbeal_overlay;# char ka0202_cpu$b_fill13h [24]; __union {# __int64 ka0202_cpu$q_cbeah; __struct {1 unsigned ka0202_cpu$v_cbeah_sbo1 : 2;2 ) unsigned ka0202_cpu$v_cbeah_ea_l : 16;5 unsigned ka0202_cpu$v_cbeah_t_type_l : 3;6 unsigned ka0202_cpu$v_cbeah_cmdr_id_l : 3;1 unsigned ka0202_cpu$v_cbeah_sbo2 : 8;1 unsigned ka0202_cpu$v_cbeah_sbo3 : 2;2 unsigned ka0202_cpu$v_cbeah_ea_h : 16;5 unsigned ka0202_cpu$v_cbeah_t_type_h : 3;6 unsigned ka0202_cpu$v_cbeah_cmdr_id_h : 3;1 unsigned ka0202_cpu$v_cbeah_sbo4 : 8;& } ka0202_cpu)$r_cbeah_bits;% } ka0202_cpu$r_cbeah_overlay;" char ka0202_cpu$b_fill13 [24]; __union {" __int64 ka0202_cpu$q_pmbx;$ } ka0202_cpu$r_pmbx_overlay;# char ka0202_cpu$b_fill13j [24]; __union {" __int64 ka0202_cpu$q_ipir; __struct {5 unsigned ka0202_cpu$v_ipir_undefined : 1;2 unsigned ka0202_cpu$v_ipir_fill1 : 31;7 unsigned ka0202_cpu$v_ipir_req_int_cpu : 1;2 unsigned ka0202_cpu$v_ipir_fill2 : ) 31;% } ka0202_cpu$r_ipir_bits;$ } ka0202_cpu$r_ipir_overlay;# char ka0202_cpu$b_fill13k [24]; __union {! __int64 ka0202_cpu$q_sic; __struct {4 unsigned ka0202_cpu$v_sic_undefined : 1;5 unsigned ka0202_cpu$v_sic_undefined1 : 1;. unsigned ka0202_cpu$v_sic_eic : 1;1 unsigned ka0202_cpu$v_sic_fill1 : 29;4 unsigned ka0202_cpu$v_sic_it_iclear : 1;6 unsigned ka0202_cpu$v_sic_sys_evt_ )clr : 1;5 unsigned ka0202_cpu$v_sic_undefined2 : 1;1 unsigned ka0202_cpu$v_sic_fill2 : 29;$ } ka0202_cpu$r_sic_bits;# } ka0202_cpu$r_sic_overlay;# char ka0202_cpu$b_fill13l [24]; __union {" __int64 ka0202_cpu$q_adlk; __struct {2 unsigned ka0202_cpu$v_adlk_la_v_l : 1;1 unsigned ka0202_cpu$v_adlk_fill1 : 2;1 unsigned ka0202_cpu$v_adlk_la_l : 29;2 unsigned ka0202_cpu$v_adlk_la_v_ )h : 1;1 unsigned ka0202_cpu$v_adlk_fill2 : 2;1 unsigned ka0202_cpu$v_adlk_la_h : 29;% } ka0202_cpu$r_adlk_bits;$ } ka0202_cpu$r_adlk_overlay;# char ka0202_cpu$b_fill13m [24]; __union {# __int64 ka0202_cpu$q_madrl; __struct {4 unsigned ka0202_cpu$v_madrl_valid_l : 1;5 unsigned ka0202_cpu$v_madrl_t_type_l : 1;7 unsigned ka0202_cpu$v_madrl_address_l : 30;4 unsigned ka0202_cpu$v_)madrl_valid_h : 1;5 unsigned ka0202_cpu$v_madrl_t_type_h : 1;7 unsigned ka0202_cpu$v_madrl_address_h : 30;& } ka0202_cpu$r_madrl_bits;% } ka0202_cpu$r_madrl_overlay;# char ka0202_cpu$b_fill13n [24]; __union {# __int64 ka0202_cpu$q_unimp;% } ka0202_cpu$r_unimp_overlay;$ char ka0202_cpu$b_fill15 [7704]; } KA0202CPU; #if !defined(__VAXC)B#define ka0202_cpu$q_bcc ka0202_cpu$r_bcc_overlay.ka0202_cpu$q_bccp#define ka)0202_cpu$v_bcc_enb_alloc_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_alloc_lt#define ka0202_cpu$v_bcc_frc_fill_sh_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_frc_fill_sh_ll#define ka0202_cpu$v_bcc_enb_tpc_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_tpc_ln#define ka0202_cpu$v_bcc_fill_wtp_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_fill_wtp_ln#define ka0202_cpu$v_bcc_fill_wcp_l ka0202_cpu$r_bcc_overlay.k)a0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_fill_wcp_lp#define ka0202_cpu$v_bcc_fill_wdtp_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_fill_wdtp_ll#define ka0202_cpu$v_bcc_enb_cei_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_cei_ln#define ka0202_cpu$v_bcc_enb_edcc_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_edcc_lt#define ka0202_cpu$v_bcc_enb_edc_chk_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_edc_chk_lr#d)efine ka0202_cpu$v_bcc_enb_bc_cio_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_bc_cio_lp#define ka0202_cpu$v_bcc_dis_blk_w_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_dis_blk_w_lt#define ka0202_cpu$v_bcc_enb_bc_init_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_bc_init_ln#define ka0202_cpu$v_bcc_for_edcc_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_for_edcc_lj#define ka0202_cpu$v_bcc_sh_d_v_l ka0202_cpu$r_b)cc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_sh_d_v_ld#define ka0202_cpu$v_bcc_edc_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_edc_lr#define ka0202_cpu$v_bcc_cache_size_l ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_cache_size_lp#define ka0202_cpu$v_bcc_enb_alloc_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_alloc_ht#define ka0202_cpu$v_bcc_frc_fill_sh_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_frc_fill_sh)_hl#define ka0202_cpu$v_bcc_enb_tpc_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_tpc_hn#define ka0202_cpu$v_bcc_fill_wtp_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_fill_wtp_hn#define ka0202_cpu$v_bcc_fill_wcp_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_fill_wcp_hp#define ka0202_cpu$v_bcc_fill_wdtp_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_fill_wdtp_hl#define ka0202_cpu$v_bcc_enb_cei_h ka0202_cpu$r_bcc_ov)erlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_cei_hn#define ka0202_cpu$v_bcc_enb_edcc_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_edcc_ht#define ka0202_cpu$v_bcc_enb_edc_chk_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_edc_chk_hr#define ka0202_cpu$v_bcc_enb_bc_cio_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_bc_cio_hp#define ka0202_cpu$v_bcc_dis_blk_w_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_dis)_blk_w_ht#define ka0202_cpu$v_bcc_enb_bc_init_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_enb_bc_init_hn#define ka0202_cpu$v_bcc_for_edcc_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_for_edcc_hj#define ka0202_cpu$v_bcc_sh_d_v_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_sh_d_v_hh#define ka0202_cpu$v_bcc_edc_l_h ka0202_cpu$r_bcc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_edc_l_hr#define ka0202_cpu$v_bcc_cache_size_h ka0202_cpu$r_b)cc_overlay.ka0202_cpu$r_bcc_bits.ka0202_cpu$v_bcc_cache_size_hE#define ka0202_cpu$q_bcce ka0202_cpu$r_bcce_overlay.ka0202_cpu$q_bcced#define ka0202_cpu$v_bcce_mce ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_mceb#define ka0202_cpu$v_bcce_ce ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_cep#define ka0202_cpu$v_bcce_cntrl_par ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_cntrl_parb#define ka0202_cpu$v_bcce_sh ka0202_cpu$r_bcce_overlay).ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_shh#define ka0202_cpu$v_bcce_dirty ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_dirtyh#define ka0202_cpu$v_bcce_valid ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_validn#define ka0202_cpu$v_bcce_bc_edc_l ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_bc_edc_lr#define ka0202_cpu$v_bcce_edc_synd_0 ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_edc_synd_0r#define ka0202_cpu$v)_bcce_edc_synd_2 ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_edc_synd_2h#define ka0202_cpu$v_bcce_mce_h ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_mce_hf#define ka0202_cpu$v_bcce_ce_h ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_ce_hp#define ka0202_cpu$v_bcce_read_only ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_read_onlyn#define ka0202_cpu$v_bcce_bc_edc_h ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka)0202_cpu$v_bcce_bc_edc_hr#define ka0202_cpu$v_bcce_edc_synd_1 ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_edc_synd_1r#define ka0202_cpu$v_bcce_edc_synd_3 ka0202_cpu$r_bcce_overlay.ka0202_cpu$r_bcce_bits.ka0202_cpu$v_bcce_edc_synd_3H#define ka0202_cpu$q_bccea ka0202_cpu$r_bccea_overlay.ka0202_cpu$q_bcceat#define ka0202_cpu$v_bccea_bcmap_off ka0202_cpu$r_bccea_overlay.ka0202_cpu$r_bccea_bits.ka0202_cpu$v_bccea_bcmap_offp#define ka0202_cpu$v_bccea_tag_par ka0202_cpu$r_bccea_ov)erlay.ka0202_cpu$r_bccea_bits.ka0202_cpu$v_bccea_tag_part#define ka0202_cpu$v_bccea_tag_value ka0202_cpu$r_bccea_overlay.ka0202_cpu$r_bccea_bits.ka0202_cpu$v_bccea_tag_valuex#define ka0202_cpu$v_bccea_bcmap_off_h ka0202_cpu$r_bccea_overlay.ka0202_cpu$r_bccea_bits.ka0202_cpu$v_bccea_bcmap_off_ht#define ka0202_cpu$v_bccea_tag_par_h ka0202_cpu$r_bccea_overlay.ka0202_cpu$r_bccea_bits.ka0202_cpu$v_bccea_tag_par_hx#define ka0202_cpu$v_bccea_tag_value_h ka0202_cpu$r_bccea_overlay.ka0202_cpu$r_bccea_bits.)ka0202_cpu$v_bccea_tag_value_hE#define ka0202_cpu$q_bcue ka0202_cpu$r_bcue_overlay.ka0202_cpu$q_bcued#define ka0202_cpu$v_bcue_mpe ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_mpeb#define ka0202_cpu$v_bcue_pe ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_pel#define ka0202_cpu$v_bcue_munce_l ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_munce_lj#define ka0202_cpu$v_bcue_unce_l ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_c)pu$v_bcue_unce_ln#define ka0202_cpu$v_bcue_ctrl_par ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_ctrl_parb#define ka0202_cpu$v_bcue_sh ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_shh#define ka0202_cpu$v_bcue_dirty ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_dirtyh#define ka0202_cpu$v_bcue_valid ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_validn#define ka0202_cpu$v_bcue_bc_edc_l ka0202_cpu$r_bcue_overlay.ka0)202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_bc_edc_lr#define ka0202_cpu$v_bcue_edc_synd_0 ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_edc_synd_0r#define ka0202_cpu$v_bcue_edc_synd_2 ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_edc_synd_2f#define ka0202_cpu$v_bcue_pe_h ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_pe_hl#define ka0202_cpu$v_bcue_munce_h ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_munce_hj#define ka02)02_cpu$v_bcue_unce_h ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_unce_hn#define ka0202_cpu$v_bcue_bc_edc_h ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_bc_edc_hr#define ka0202_cpu$v_bcue_edc_synd_1 ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_edc_synd_1r#define ka0202_cpu$v_bcue_edc_synd_3 ka0202_cpu$r_bcue_overlay.ka0202_cpu$r_bcue_bits.ka0202_cpu$v_bcue_edc_synd_3H#define ka0202_cpu$q_bcuea ka0202_cpu$r_bcuea_overlay.ka0202_cpu$q)_bcueat#define ka0202_cpu$v_bcuea_bcmap_off ka0202_cpu$r_bcuea_overlay.ka0202_cpu$r_bcuea_bits.ka0202_cpu$v_bcuea_bcmap_offh#define ka0202_cpu$v_bcuea_ptp ka0202_cpu$r_bcuea_overlay.ka0202_cpu$r_bcuea_bits.ka0202_cpu$v_bcuea_ptpf#define ka0202_cpu$v_bcuea_tp ka0202_cpu$r_bcuea_overlay.ka0202_cpu$r_bcuea_bits.ka0202_cpu$v_bcuea_tpf#define ka0202_cpu$v_bcuea_tv ka0202_cpu$r_bcuea_overlay.ka0202_cpu$r_bcuea_bits.ka0202_cpu$v_bcuea_tvx#define ka0202_cpu$v_bcuea_bcmap_off_h ka0202_cpu$r_bcuea_overlay.)ka0202_cpu$r_bcuea_bits.ka0202_cpu$v_bcuea_bcmap_off_hl#define ka0202_cpu$v_bcuea_ptp_h ka0202_cpu$r_bcuea_overlay.ka0202_cpu$r_bcuea_bits.ka0202_cpu$v_bcuea_ptp_hj#define ka0202_cpu$v_bcuea_tp_h ka0202_cpu$r_bcuea_overlay.ka0202_cpu$r_bcuea_bits.ka0202_cpu$v_bcuea_tp_hj#define ka0202_cpu$v_bcuea_tv_h ka0202_cpu$r_bcuea_overlay.ka0202_cpu$r_bcuea_bits.ka0202_cpu$v_bcuea_tv_hE#define ka0202_cpu$q_dter ka0202_cpu$r_dter_overlay.ka0202_cpu$q_dterb#define ka0202_cpu$v_mdter_l ka0202_cpu$r_dter_overl)ay.ka0202_cpu$r_dter_bits.ka0202_cpu$v_mdter_l`#define ka0202_cpu$v_dter_l ka0202_cpu$r_dter_overlay.ka0202_cpu$r_dter_bits.ka0202_cpu$v_dter_lj#define ka0202_cpu$v_dter_toff_l ka0202_cpu$r_dter_overlay.ka0202_cpu$r_dter_bits.ka0202_cpu$v_dter_toff_lp#define ka0202_cpu$v_dter_dup_tag_l ka0202_cpu$r_dter_overlay.ka0202_cpu$r_dter_bits.ka0202_cpu$v_dter_dup_tag_ld#define ka0202_cpu$v_dter_dtp ka0202_cpu$r_dter_overlay.ka0202_cpu$r_dter_bits.ka0202_cpu$v_dter_dtpb#define ka0202_cpu$v_mdter_h ka0202_)cpu$r_dter_overlay.ka0202_cpu$r_dter_bits.ka0202_cpu$v_mdter_h`#define ka0202_cpu$v_dter_h ka0202_cpu$r_dter_overlay.ka0202_cpu$r_dter_bits.ka0202_cpu$v_dter_hf#define ka0202_cpu$v_dter_dt_h ka0202_cpu$r_dter_overlay.ka0202_cpu$r_dter_bits.ka0202_cpu$v_dter_dt_hp#define ka0202_cpu$v_dter_dup_tag_h ka0202_cpu$r_dter_overlay.ka0202_cpu$r_dter_bits.ka0202_cpu$v_dter_dup_tag_hh#define ka0202_cpu$v_dter_dtp_h ka0202_cpu$r_dter_overlay.ka0202_cpu$r_dter_bits.ka0202_cpu$v_dter_dtp_hH#define ka0202_cpu$q)_cbctl ka0202_cpu$r_cbctl_overlay.ka0202_cpu$q_cbctlh#define ka0202_cpu$v_cbctl_dwp ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_dwpj#define ka0202_cpu$v_cbctl_cawp ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_cawph#define ka0202_cpu$v_cbctl_epc ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_epcn#define ka0202_cpu$v_cbctl_frc_sh ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_frc_shr#define ka0202_cpu$v)_cbctl_cmder_id ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_cmder_idh#define ka0202_cpu$v_cbctl_acm ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_acmn#define ka0202_cpu$v_cbctl_enb_ci ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_enb_cif#define ka0202_cpu$v_cbctl_rd ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_rdr#define ka0202_cpu$v_cbctl_qw_2_sel ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.k)a0202_cpu$v_cbctl_qw_2_selt#define ka0202_cpu$v_cbctl_sel_drack ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_sel_drackl#define ka0202_cpu$v_cbctl_dwp_h ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_dwp_hn#define ka0202_cpu$v_cbctl_cawp_h ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_cawp_hl#define ka0202_cpu$v_cbctl_epc_h ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_epc_hr#define ka0202_cpu$v_cbctl_f)rc_sh_h ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_frc_sh_hv#define ka0202_cpu$v_cbctl_cmder_id_h ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_cmder_id_hl#define ka0202_cpu$v_cbctl_acm_h ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_acm_hr#define ka0202_cpu$v_cbctl_enb_ci_h ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_enb_ci_hj#define ka0202_cpu$v_cbctl_rd_h ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_)cbctl_bits.ka0202_cpu$v_cbctl_rd_hv#define ka0202_cpu$v_cbctl_qw_2_sel_h ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_qw_2_sel_hx#define ka0202_cpu$v_cbctl_sel_drack_h ka0202_cpu$r_cbctl_overlay.ka0202_cpu$r_cbctl_bits.ka0202_cpu$v_cbctl_sel_drack_hB#define ka0202_cpu$q_cbe ka0202_cpu$r_cbe_overlay.ka0202_cpu$q_cbeb#define ka0202_cpu$v_cbe_rd_l ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_rd_ld#define ka0202_cpu$v_cbe_cap_l ka0202_cpu$r_cbe_overlay.ka02)02_cpu$r_cbe_bits.ka0202_cpu$v_cbe_cap_lf#define ka0202_cpu$v_cbe_mcap_l ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_mcap_lj#define ka0202_cpu$v_cbe_pe_wrd_l ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_pe_wrd_ll#define ka0202_cpu$v_cbe_mpe_wrd_l ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_mpe_wrd_lh#define ka0202_cpu$v_cbe_pe_rd_l ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_pe_rd_lj#define ka0202_cpu$v_cbe_mpe_rd_l ka)0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_mpe_rd_ll#define ka0202_cpu$v_cbe_ca_pe_lw0 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_ca_pe_lw0l#define ka0202_cpu$v_cbe_ca_pe_lw2 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_ca_pe_lw2j#define ka0202_cpu$v_cbe_d_pe_lw0 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_d_pe_lw0j#define ka0202_cpu$v_cbe_d_pe_lw2 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_d_pe_lw2)j#define ka0202_cpu$v_cbe_d_pe_lw4 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_d_pe_lw4j#define ka0202_cpu$v_cbe_d_pe_lw6 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_d_pe_lw6h#define ka0202_cpu$v_cbe_ca_nack ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_ca_nackr#define ka0202_cpu$v_cbe_wr_data_nack ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_wr_data_nackf#define ka0202_cpu$v_cbe_mcount ka0202_cpu$r_cbe_overlay.ka0202_cp)u$r_cbe_bits.ka0202_cpu$v_cbe_mcountn#define ka0202_cpu$v_cbe_madr_valid ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_madr_validb#define ka0202_cpu$v_cbe_rd_h ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_rd_hd#define ka0202_cpu$v_cbe_cap_h ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_cap_hf#define ka0202_cpu$v_cbe_mcap_h ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_mcap_hj#define ka0202_cpu$v_cbe_pe_wrd_h ka0202_cpu$r_cbe)_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_pe_wrd_hl#define ka0202_cpu$v_cbe_mpe_wrd_h ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_mpe_wrd_hh#define ka0202_cpu$v_cbe_pe_rd_h ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_pe_rd_hj#define ka0202_cpu$v_cbe_mpe_rd_h ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_mpe_rd_hl#define ka0202_cpu$v_cbe_ca_pe_lw1 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_ca_pe_lw1l#define ka0202)_cpu$v_cbe_ca_pe_lw3 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_ca_pe_lw3j#define ka0202_cpu$v_cbe_d_pe_lw1 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_d_pe_lw1j#define ka0202_cpu$v_cbe_d_pe_lw3 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_d_pe_lw3j#define ka0202_cpu$v_cbe_d_pe_lw5 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_d_pe_lw5j#define ka0202_cpu$v_cbe_d_pe_lw7 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka020)2_cpu$v_cbe_d_pe_lw7l#define ka0202_cpu$v_cbe_undefined ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_undefinedn#define ka0202_cpu$v_cbe_undefined2 ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_undefined2j#define ka0202_cpu$v_cbe_mcount_h ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_mcount_hr#define ka0202_cpu$v_cbe_madr_valid_h ka0202_cpu$r_cbe_overlay.ka0202_cpu$r_cbe_bits.ka0202_cpu$v_cbe_madr_valid_hH#define ka0202_cpu$q_cbeal ka0202_cpu$*r_cbeal_overlay.ka0202_cpu$q_cbealj#define ka0202_cpu$v_cbeal_sbo1 ka0202_cpu$r_cbeal_overlay.ka0202_cpu$r_cbeal_bits.ka0202_cpu$v_cbeal_sbo1v#define ka0202_cpu$v_cbeal_addr_cad_l ka0202_cpu$r_cbeal_overlay.ka0202_cpu$r_cbeal_bits.ka0202_cpu$v_cbeal_addr_cad_lj#define ka0202_cpu$v_cbeal_sbo2 ka0202_cpu$r_cbeal_overlay.ka0202_cpu$r_cbeal_bits.ka0202_cpu$v_cbeal_sbo2v#define ka0202_cpu$v_cbeal_addr_cad_h ka0202_cpu$r_cbeal_overlay.ka0202_cpu$r_cbeal_bits.ka0202_cpu$v_cbeal_addr_cad_hH#define ka0202*_cpu$q_cbeah ka0202_cpu$r_cbeah_overlay.ka0202_cpu$q_cbeahj#define ka0202_cpu$v_cbeah_sbo1 ka0202_cpu$r_cbeah_overlay.ka0202_cpu$r_cbeah_bits.ka0202_cpu$v_cbeah_sbo1j#define ka0202_cpu$v_cbeah_ea_l ka0202_cpu$r_cbeah_overlay.ka0202_cpu$r_cbeah_bits.ka0202_cpu$v_cbeah_ea_lr#define ka0202_cpu$v_cbeah_t_type_l ka0202_cpu$r_cbeah_overlay.ka0202_cpu$r_cbeah_bits.ka0202_cpu$v_cbeah_t_type_lt#define ka0202_cpu$v_cbeah_cmdr_id_l ka0202_cpu$r_cbeah_overlay.ka0202_cpu$r_cbeah_bits.ka0202_cpu$v_cbeah_cmdr_id*_lj#define ka0202_cpu$v_cbeah_sbo2 ka0202_cpu$r_cbeah_overlay.ka0202_cpu$r_cbeah_bits.ka0202_cpu$v_cbeah_sbo2j#define ka0202_cpu$v_cbeah_sbo3 ka0202_cpu$r_cbeah_overlay.ka0202_cpu$r_cbeah_bits.ka0202_cpu$v_cbeah_sbo3j#define ka0202_cpu$v_cbeah_ea_h ka0202_cpu$r_cbeah_overlay.ka0202_cpu$r_cbeah_bits.ka0202_cpu$v_cbeah_ea_hr#define ka0202_cpu$v_cbeah_t_type_h ka0202_cpu$r_cbeah_overlay.ka0202_cpu$r_cbeah_bits.ka0202_cpu$v_cbeah_t_type_ht#define ka0202_cpu$v_cbeah_cmdr_id_h ka0202_cpu$r_cbeah_overla*y.ka0202_cpu$r_cbeah_bits.ka0202_cpu$v_cbeah_cmdr_id_hj#define ka0202_cpu$v_cbeah_sbo4 ka0202_cpu$r_cbeah_overlay.ka0202_cpu$r_cbeah_bits.ka0202_cpu$v_cbeah_sbo4E#define ka0202_cpu$q_pmbx ka0202_cpu$r_pmbx_overlay.ka0202_cpu$q_pmbxE#define ka0202_cpu$q_ipir ka0202_cpu$r_ipir_overlay.ka0202_cpu$q_ipirp#define ka0202_cpu$v_ipir_undefined ka0202_cpu$r_ipir_overlay.ka0202_cpu$r_ipir_bits.ka0202_cpu$v_ipir_undefinedt#define ka0202_cpu$v_ipir_req_int_cpu ka0202_cpu$r_ipir_overlay.ka0202_cpu$r_ipir_bi*ts.ka0202_cpu$v_ipir_req_int_cpuB#define ka0202_cpu$q_sic ka0202_cpu$r_sic_overlay.ka0202_cpu$q_sicl#define ka0202_cpu$v_sic_undefined ka0202_cpu$r_sic_overlay.ka0202_cpu$r_sic_bits.ka0202_cpu$v_sic_undefinedn#define ka0202_cpu$v_sic_undefined1 ka0202_cpu$r_sic_overlay.ka0202_cpu$r_sic_bits.ka0202_cpu$v_sic_undefined1`#define ka0202_cpu$v_sic_eic ka0202_cpu$r_sic_overlay.ka0202_cpu$r_sic_bits.ka0202_cpu$v_sic_eicl#define ka0202_cpu$v_sic_it_iclear ka0202_cpu$r_sic_overlay.ka0202_cpu$r_sic_bits.ka*0202_cpu$v_sic_it_iclearp#define ka0202_cpu$v_sic_sys_evt_clr ka0202_cpu$r_sic_overlay.ka0202_cpu$r_sic_bits.ka0202_cpu$v_sic_sys_evt_clrn#define ka0202_cpu$v_sic_undefined2 ka0202_cpu$r_sic_overlay.ka0202_cpu$r_sic_bits.ka0202_cpu$v_sic_undefined2E#define ka0202_cpu$q_adlk ka0202_cpu$r_adlk_overlay.ka0202_cpu$q_adlkj#define ka0202_cpu$v_adlk_la_v_l ka0202_cpu$r_adlk_overlay.ka0202_cpu$r_adlk_bits.ka0202_cpu$v_adlk_la_v_lf#define ka0202_cpu$v_adlk_la_l ka0202_cpu$r_adlk_overlay.ka0202_cpu$r_adlk*_bits.ka0202_cpu$v_adlk_la_lj#define ka0202_cpu$v_adlk_la_v_h ka0202_cpu$r_adlk_overlay.ka0202_cpu$r_adlk_bits.ka0202_cpu$v_adlk_la_v_hf#define ka0202_cpu$v_adlk_la_h ka0202_cpu$r_adlk_overlay.ka0202_cpu$r_adlk_bits.ka0202_cpu$v_adlk_la_hH#define ka0202_cpu$q_madrl ka0202_cpu$r_madrl_overlay.ka0202_cpu$q_madrlp#define ka0202_cpu$v_madrl_valid_l ka0202_cpu$r_madrl_overlay.ka0202_cpu$r_madrl_bits.ka0202_cpu$v_madrl_valid_lr#define ka0202_cpu$v_madrl_t_type_l ka0202_cpu$r_madrl_overlay.ka0202_cpu$r_*madrl_bits.ka0202_cpu$v_madrl_t_type_lt#define ka0202_cpu$v_madrl_address_l ka0202_cpu$r_madrl_overlay.ka0202_cpu$r_madrl_bits.ka0202_cpu$v_madrl_address_lp#define ka0202_cpu$v_madrl_valid_h ka0202_cpu$r_madrl_overlay.ka0202_cpu$r_madrl_bits.ka0202_cpu$v_madrl_valid_hr#define ka0202_cpu$v_madrl_t_type_h ka0202_cpu$r_madrl_overlay.ka0202_cpu$r_madrl_bits.ka0202_cpu$v_madrl_t_type_ht#define ka0202_cpu$v_madrl_address_h ka0202_cpu$r_madrl_overlay.ka0202_cpu$r_madrl_bits.ka0202_cpu$v_madrl_address_hH*#define ka0202_cpu$q_unimp ka0202_cpu$r_unimp_overlay.ka0202_cpu$q_unimp"#endif /* #if !defined(__VAXC) */ #define KA0202_CMM$M_CME_ES1 0x1 #define KA0202_CMM$M_CME_SE1 0x2##define KA0202_CMM$M_CME_CA_PE1 0x4$#define KA0202_CMM$M_CME_MCA_PE1 0x8$#define KA0202_CMM$M_CME_WD_PE1 0x10%#define KA0202_CMM$M_CME_MWD_PE1 0x20(#define KA0202_CMM$M_CME_CA_PE_LW0 0x100(#define KA0202_CMM$M_CME_CA_PE_LW2 0x200'#define KA0202_CMM$M_CME_D_PE_LW0 0x400'#define KA0202_CMM$M_CME_D_PE_LW2 0x800(#d *efine KA0202_CMM$M_CME_D_PE_LW4 0x1000(#define KA0202_CMM$M_CME_D_PE_LW6 0x2000%#define KA0202_CMM$M_CME_EUE1 0x10000&#define KA0202_CMM$M_CME_MEUE1 0x20000%#define KA0202_CMM$M_CME_ECE1 0x40000&#define KA0202_CMM$M_CME_MECE1 0x80000(#define KA0202_CMM$M_CME_ES2 0x100000000(#define KA0202_CMM$M_CME_SE2 0x200000000+#define KA0202_CMM$M_CME_CA_PE2 0x400000000,#define KA0202_CMM$M_CME_MCA_PE2 0x800000000,#define KA0202_CMM$M_CME_WD_PE2 0x1000000000-#define KA0202_CMM$M_CME_MWD_PE2 0x2000000 *0000#define KA0202_CMM$M_CME_CA_PE_LW1 0x100000000000#define KA0202_CMM$M_CME_CA_PE_LW3 0x20000000000/#define KA0202_CMM$M_CME_D_PE_LW1 0x40000000000/#define KA0202_CMM$M_CME_D_PE_LW3 0x800000000000#define KA0202_CMM$M_CME_D_PE_LW5 0x1000000000000#define KA0202_CMM$M_CME_D_PE_LW7 0x200000000000-#define KA0202_CMM$M_CME_EUE2 0x1000000000000.#define KA0202_CMM$M_CME_MEUE2 0x2000000000000-#define KA0202_CMM$M_CME_ECE2 0x4000000000000.#define KA0202_CMM$M_CME_MECE2 0x8000000000000%#define *KA0202_CMM$M_CNFG_MOD_ID1 0x3(#define KA0202_CMM$M_CNFG_MOD_SIZE1 0x70$#define KA0202_CMM$M_CNFG_EMD1 0x100,#define KA0202_CMM$M_CNFG_INTR_MODE1 0xC0000-#define KA0202_CMM$M_CNFG_INTR_UNIT1 0x300000/#define KA0202_CMM$M_CNFG_BASE_ADDR1 0x7FC00000-#define KA0202_CMM$M_CNFG_MEM_ENB1 0x80000000-#define KA0202_CMM$M_CNFG_MOD_ID2 0x3000000000#define KA0202_CMM$M_CNFG_MOD_SIZE2 0x7000000000,#define KA0202_CMM$M_CNFG_EMD2 0x100000000004#define KA0202_CMM$M_CNFG_INTR_MODE2 0xC0000000000005#def *ine KA0202_CMM$M_CNFG_INTR_UNIT2 0x300000000000007#define KA0202_CMM$M_CNFG_BASE_ADDR2 0x7FC00000000000005#define KA0202_CMM$M_CNFG_MEM_ENB2 0x8000000000000000+#define KA0202_CMM$M_EDC1_READ_CBITS1 0xFFF-#define KA0202_CMM$M_EDC1_WR_CBITS1 0xFFF00003#define KA0202_CMM$M_EDC1_READ_CBITS2 0xFFF000000005#define KA0202_CMM$M_EDC1_WR_CBITS2 0xFFF000000000000)#define KA0202_CMM$M_EDC2_SYNDROME1 0xFFF1#define KA0202_CMM$M_EDC2_SYNDROME2 0xFFF00000000%#define KA0202_CMM$M_EDCTL_SRB1 0xFFF' *#define KA0202_CMM$M_EDCTL_USCB1 0x1000(#define KA0202_CMM$M_EDCTL_USWCB1 0x2000'#define KA0202_CMM$M_EDCTL_DIPC1 0x4000)#define KA0202_CMM$M_EDCTL_ENB_ES1 0x8000*#define KA0202_CMM$M_EDCTL_SWCB1 0xFFF0000+#define KA0202_CMM$M_EDCTL_CRDP1 0x10000000/#define KA0202_CMM$M_EDCTL_ENB_CRDR1 0x20000000/#define KA0202_CMM$M_EDCTL_DEDCCORR1 0x400000001#define KA0202_CMM$M_EDCTL_DEDCREPORT1 0x80000000-#define KA0202_CMM$M_EDCTL_SRB2 0xFFF00000000/#define KA0202_CMM$M_EDCTL_USCB2 0x10000000000 *00#define KA0202_CMM$M_EDCTL_USWCB2 0x200000000000/#define KA0202_CMM$M_EDCTL_DIPC2 0x4000000000001#define KA0202_CMM$M_EDCTL_ENB_ES2 0x8000000000002#define KA0202_CMM$M_EDCTL_SWCB2 0xFFF0000000000003#define KA0202_CMM$M_EDCTL_CRDP2 0x10000000000000007#define KA0202_CMM$M_EDCTL_ENB_CRDR2 0x20000000000000007#define KA0202_CMM$M_EDCTL_DEDCCORR2 0x40000000000000009#define KA0202_CMM$M_EDCTL_DEDCREPORT2 0x8000000000000000$#define KA0202_CMM$M_SBCTRL_DSD1 0x1$#define KA0202_CMM$M_SBCTRL_DS *H1 0x2$#define KA0202_CMM$M_SBCTRL_DSF1 0x4$#define KA0202_CMM$M_SBCTRL_DSI1 0x8&#define KA0202_CMM$M_SBCTRL_ERWD1 0x10%#define KA0202_CMM$M_SBCTRL_FHB1 0x20,#define KA0202_CMM$M_SBCTRL_DSD2 0x100000000,#define KA0202_CMM$M_SBCTRL_DSH2 0x200000000,#define KA0202_CMM$M_SBCTRL_DSF2 0x400000000,#define KA0202_CMM$M_SBCTRL_DSI2 0x800000000.#define KA0202_CMM$M_SBCTRL_ERWD2 0x1000000000-#define KA0202_CMM$M_SBCTRL_FHB2 0x2000000000##define KA0202_CMM$M_RCTRL_RC1 0xFF(#define KA0202_CMM$M_RCT *RL_REF_ENB 0x100+#define KA0202_CMM$M_RCTRL_RC2 0xFF000000001#define KA0202_CMM$M_RCTRL_REF_ENB2 0x10000000000%#define KA0202_CMM$M_CRDCTL_SM1 0xFFF&#define KA0202_CMM$M_CRDCTL_BS1 0x3000'#define KA0202_CMM$M_CRDCTL_CFE1 0x4000-#define KA0202_CMM$M_CRDCTL_SM2 0xFFF00000000.#define KA0202_CMM$M_CRDCTL_BS2 0x300000000000/#define KA0202_CMM$M_CRDCTL_CFE2 0x400000000000 #define KA0202_CMM$K_LENGTH 8192`#define KA0202_CMM$S_CMMDEF 8192 /* Old size name, synonym for KA0202_CMM$S_KA02*02CMM */ typedef struct _ka0202cmm { __union {! __int64 ka0202_cmm$q_cme; __struct {. unsigned ka0202_cmm$v_cme_es1 : 1;. unsigned ka0202_cmm$v_cme_se1 : 1;1 unsigned ka0202_cmm$v_cme_ca_pe1 : 1;2 unsigned ka0202_cmm$v_cme_mca_pe1 : 1;1 unsigned ka0202_cmm$v_cme_wd_pe1 : 1;2 unsigned ka0202_cmm$v_cme_mwd_pe1 : 1;0 unsigned ka0202_cmm$v_cme_fill1 : 2;4 unsigned ka0202_cmm$v_ *cme_ca_pe_lw0 : 1;4 unsigned ka0202_cmm$v_cme_ca_pe_lw2 : 1;3 unsigned ka0202_cmm$v_cme_d_pe_lw0 : 1;3 unsigned ka0202_cmm$v_cme_d_pe_lw2 : 1;3 unsigned ka0202_cmm$v_cme_d_pe_lw4 : 1;3 unsigned ka0202_cmm$v_cme_d_pe_lw6 : 1;0 unsigned ka0202_cmm$v_cme_fill2 : 2;/ unsigned ka0202_cmm$v_cme_eue1 : 1;0 unsigned ka0202_cmm$v_cme_meue1 : 1;/ unsigned ka0202_cmm$v_cme_ece1 : 1;0 unsi *gned ka0202_cmm$v_cme_mece1 : 1;1 unsigned ka0202_cmm$v_cme_fill3 : 12;. unsigned ka0202_cmm$v_cme_es2 : 1;. unsigned ka0202_cmm$v_cme_se2 : 1;1 unsigned ka0202_cmm$v_cme_ca_pe2 : 1;2 unsigned ka0202_cmm$v_cme_mca_pe2 : 1;1 unsigned ka0202_cmm$v_cme_wd_pe2 : 1;2 unsigned ka0202_cmm$v_cme_mwd_pe2 : 1;0 unsigned ka0202_cmm$v_cme_fill4 : 2;4 unsigned ka0202_cmm$v_cme_ca_pe_lw1 : 1;4 *unsigned ka0202_cmm$v_cme_ca_pe_lw3 : 1;3 unsigned ka0202_cmm$v_cme_d_pe_lw1 : 1;3 unsigned ka0202_cmm$v_cme_d_pe_lw3 : 1;3 unsigned ka0202_cmm$v_cme_d_pe_lw5 : 1;3 unsigned ka0202_cmm$v_cme_d_pe_lw7 : 1;0 unsigned ka0202_cmm$v_cme_fill5 : 2;/ unsigned ka0202_cmm$v_cme_eue2 : 1;0 unsigned ka0202_cmm$v_cme_meue2 : 1;/ unsigned ka0202_cmm$v_cme_ece2 : 1;0 unsigned ka0202_cmm$v_cme_mece2 : 1;*1 unsigned ka0202_cmm$v_cme_fill6 : 12;$ } ka0202_cmm$r_cme_bits;# } ka0202_cmm$r_cme_overlay;" char ka0202_cmm$b_fill_1 [24]; __union {# __int64 ka0202_cmm$q_trap1; __struct {. unsigned int ka0202_cmm$l_trap1_l;. unsigned int ka0202_cmm$l_trap1_h;& } ka0202_cmm$r_trap1_bits;% } ka0202_cmm$r_trap1_overlay;" char ka0202_cmm$b_fill_2 [24]; __union {# __int64 ka0202_cmm$q_trap2; * __struct {. unsigned int ka0202_cmm$l_trap2_l;. unsigned int ka0202_cmm$l_trap2_h;& } ka0202_cmm$r_trap2_bits;% } ka0202_cmm$r_trap2_overlay;" char ka0202_cmm$b_fill_3 [24]; __union {" __int64 ka0202_cmm$q_cnfg; __struct {3 unsigned ka0202_cmm$v_cnfg_mod_id1 : 2;1 unsigned ka0202_cmm$v_cnfg_fill1 : 2;5 unsigned ka0202_cmm$v_cnfg_mod_size1 : 3;1 unsigned ka0202_cmm$v_ *cnfg_fill2 : 1;0 unsigned ka0202_cmm$v_cnfg_emd1 : 1;1 unsigned ka0202_cmm$v_cnfg_fill3 : 9;6 unsigned ka0202_cmm$v_cnfg_intr_mode1 : 2;6 unsigned ka0202_cmm$v_cnfg_intr_unit1 : 2;6 unsigned ka0202_cmm$v_cnfg_base_addr1 : 9;4 unsigned ka0202_cmm$v_cnfg_mem_enb1 : 1;3 unsigned ka0202_cmm$v_cnfg_mod_id2 : 2;1 unsigned ka0202_cmm$v_cnfg_fill4 : 2;5 unsigned ka0202_cmm$v_cnfg_mod_size2 : 3;1 * unsigned ka0202_cmm$v_cnfg_fill5 : 1;0 unsigned ka0202_cmm$v_cnfg_emd2 : 1;1 unsigned ka0202_cmm$v_cnfg_fill6 : 9;6 unsigned ka0202_cmm$v_cnfg_intr_mode2 : 2;6 unsigned ka0202_cmm$v_cnfg_intr_unit2 : 2;6 unsigned ka0202_cmm$v_cnfg_base_addr2 : 9;4 unsigned ka0202_cmm$v_cnfg_mem_enb2 : 1;% } ka0202_cmm$r_cnfg_bits;$ } ka0202_cmm$r_cnfg_overlay;" char ka0202_cmm$b_fill_4 [24]; __union {" * __int64 ka0202_cmm$q_edc1; __struct {8 unsigned ka0202_cmm$v_edc1_read_cbits1 : 12;1 unsigned ka0202_cmm$v_edc1_fill1 : 4;6 unsigned ka0202_cmm$v_edc1_wr_cbits1 : 12;1 unsigned ka0202_cmm$v_edc1_fill2 : 4;8 unsigned ka0202_cmm$v_edc1_read_cbits2 : 12;1 unsigned ka0202_cmm$v_edc1_fill3 : 4;6 unsigned ka0202_cmm$v_edc1_wr_cbits2 : 12;1 unsigned ka0202_cmm$v_edc1_fill4 : 4;% } *ka0202_cmm$r_edc1_bits;$ } ka0202_cmm$r_edc1_overlay;" char ka0202_cmm$b_fill_5 [24]; __union {" __int64 ka0202_cmm$q_edc2; __struct {6 unsigned ka0202_cmm$v_edc2_syndrome1 : 12;2 unsigned ka0202_cmm$v_edc2_fill1 : 20;6 unsigned ka0202_cmm$v_edc2_syndrome2 : 12;2 unsigned ka0202_cmm$v_edc2_fill2 : 20;% } ka0202_cmm$r_edc2_bits;$ } ka0202_cmm$r_edc2_overlay;" char ka0202_cmm$b_fill_6 [24]; * __union {# __int64 ka0202_cmm$q_edctl; __struct {2 unsigned ka0202_cmm$v_edctl_srb1 : 12;2 unsigned ka0202_cmm$v_edctl_uscb1 : 1;3 unsigned ka0202_cmm$v_edctl_uswcb1 : 1;2 unsigned ka0202_cmm$v_edctl_dipc1 : 1;4 unsigned ka0202_cmm$v_edctl_enb_es1 : 1;3 unsigned ka0202_cmm$v_edctl_swcb1 : 12;2 unsigned ka0202_cmm$v_edctl_crdp1 : 1;6 unsigned ka0202_cmm$v_edctl_enb_crdr1 : 1;6 * unsigned ka0202_cmm$v_edctl_dedccorr1 : 1;8 unsigned ka0202_cmm$v_edctl_dedcreport1 : 1;2 unsigned ka0202_cmm$v_edctl_srb2 : 12;2 unsigned ka0202_cmm$v_edctl_uscb2 : 1;3 unsigned ka0202_cmm$v_edctl_uswcb2 : 1;2 unsigned ka0202_cmm$v_edctl_dipc2 : 1;4 unsigned ka0202_cmm$v_edctl_enb_es2 : 1;3 unsigned ka0202_cmm$v_edctl_swcb2 : 12;2 unsigned ka0202_cmm$v_edctl_crdp2 : 1;6 unsigned ka0202_ *cmm$v_edctl_enb_crdr2 : 1;6 unsigned ka0202_cmm$v_edctl_dedccorr2 : 1;8 unsigned ka0202_cmm$v_edctl_dedcreport2 : 1;& } ka0202_cmm$r_edctl_bits;% } ka0202_cmm$r_edctl_overlay;" char ka0202_cmm$b_fill_7 [24]; __union {$ __int64 ka0202_cmm$q_sbctrl; __struct {2 unsigned ka0202_cmm$v_sbctrl_dsd1 : 1;2 unsigned ka0202_cmm$v_sbctrl_dsh1 : 1;2 unsigned ka0202_cmm$v_sbctrl_dsf1 : 1;2 unsi *gned ka0202_cmm$v_sbctrl_dsi1 : 1;3 unsigned ka0202_cmm$v_sbctrl_erwd1 : 1;2 unsigned ka0202_cmm$v_sbctrl_fhb1 : 1;4 unsigned ka0202_cmm$v_sbctrl_fill1 : 26;2 unsigned ka0202_cmm$v_sbctrl_dsd2 : 1;2 unsigned ka0202_cmm$v_sbctrl_dsh2 : 1;2 unsigned ka0202_cmm$v_sbctrl_dsf2 : 1;2 unsigned ka0202_cmm$v_sbctrl_dsi2 : 1;3 unsigned ka0202_cmm$v_sbctrl_erwd2 : 1;2 unsigned ka0202_cmm$v_sbctrl_fhb2 : *1;4 unsigned ka0202_cmm$v_sbctrl_fill2 : 26;' } ka0202_cmm$r_sbctrl_bits;& } ka0202_cmm$r_sbctrl_overlay;" char ka0202_cmm$b_fill_8 [24]; __union {# __int64 ka0202_cmm$q_rctrl; __struct {0 unsigned ka0202_cmm$v_rctrl_rc1 : 8;4 unsigned ka0202_cmm$v_rctrl_ref_enb : 1;3 unsigned ka0202_cmm$v_rctrl_fill1 : 23;0 unsigned ka0202_cmm$v_rctrl_rc2 : 8;5 unsigned ka0202_cmm$v_rctrl_ref_en *b2 : 1;3 unsigned ka0202_cmm$v_rctrl_fill2 : 23;& } ka0202_cmm$r_rctrl_bits;$ } ka0202_cmm$r_csr8_overlay;" char ka0202_cmm$b_fill_9 [24]; __union {$ __int64 ka0202_cmm$q_crdctl; __struct {2 unsigned ka0202_cmm$v_crdctl_sm1 : 12;1 unsigned ka0202_cmm$v_crdctl_bs1 : 2;2 unsigned ka0202_cmm$v_crdctl_cfe1 : 1;4 unsigned ka0202_cmm$v_crdctl_fill1 : 17;2 unsigned ka0202_cmm$v_crdctl_s!*m2 : 12;1 unsigned ka0202_cmm$v_crdctl_bs2 : 2;2 unsigned ka0202_cmm$v_crdctl_cfe2 : 1;4 unsigned ka0202_cmm$v_crdctl_fill2 : 17;' } ka0202_cmm$r_crdctl_bits;& } ka0202_cmm$r_crdctl_overlay;# char ka0202_cmm$b_fill_10 [24]; __union {# __int64 ka0202_cmm$q_csr10;% } ka0202_cmm$r_csr10_overlay;# char ka0202_cmm$b_fill_11 [24]; __union {# __int64 ka0202_cmm$q_csr11;% } ka0202_cmm$r_csr11_ove"*rlay;# char ka0202_cmm$b_fill_12 [24]; __union {# __int64 ka0202_cmm$q_csr12;% } ka0202_cmm$r_csr12_overlay;# char ka0202_cmm$b_fill_13 [24]; __union {# __int64 ka0202_cmm$q_csr13;% } ka0202_cmm$r_csr13_overlay;# char ka0202_cmm$b_fill_14 [24]; __union {# __int64 ka0202_cmm$q_csr14;% } ka0202_cmm$r_csr14_overlay;# char ka0202_cmm$b_fill_15 [24]; __union {# __int64 ka0202_cmm$q_csr15;% } #*ka0202_cmm$r_csr15_overlay;$ char ka0202_cmm$b_fill17 [7704]; } KA0202CMM; #if !defined(__VAXC)B#define ka0202_cmm$q_cme ka0202_cmm$r_cme_overlay.ka0202_cmm$q_cme`#define ka0202_cmm$v_cme_es1 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_es1`#define ka0202_cmm$v_cme_se1 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_se1f#define ka0202_cmm$v_cme_ca_pe1 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_ca_pe1h#define ka0202_cmm$v_cme_m$*ca_pe1 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_mca_pe1f#define ka0202_cmm$v_cme_wd_pe1 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_wd_pe1h#define ka0202_cmm$v_cme_mwd_pe1 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_mwd_pe1l#define ka0202_cmm$v_cme_ca_pe_lw0 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_ca_pe_lw0l#define ka0202_cmm$v_cme_ca_pe_lw2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_ca_pe_l%*w2j#define ka0202_cmm$v_cme_d_pe_lw0 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_d_pe_lw0j#define ka0202_cmm$v_cme_d_pe_lw2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_d_pe_lw2j#define ka0202_cmm$v_cme_d_pe_lw4 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_d_pe_lw4j#define ka0202_cmm$v_cme_d_pe_lw6 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_d_pe_lw6b#define ka0202_cmm$v_cme_eue1 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cm&*e_bits.ka0202_cmm$v_cme_eue1d#define ka0202_cmm$v_cme_meue1 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_meue1b#define ka0202_cmm$v_cme_ece1 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_ece1d#define ka0202_cmm$v_cme_mece1 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_mece1`#define ka0202_cmm$v_cme_es2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_es2`#define ka0202_cmm$v_cme_se2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bit'*s.ka0202_cmm$v_cme_se2f#define ka0202_cmm$v_cme_ca_pe2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_ca_pe2h#define ka0202_cmm$v_cme_mca_pe2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_mca_pe2f#define ka0202_cmm$v_cme_wd_pe2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_wd_pe2h#define ka0202_cmm$v_cme_mwd_pe2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_mwd_pe2l#define ka0202_cmm$v_cme_ca_pe_lw1 ka0202_cmm$r_cme_overlay.ka(*0202_cmm$r_cme_bits.ka0202_cmm$v_cme_ca_pe_lw1l#define ka0202_cmm$v_cme_ca_pe_lw3 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_ca_pe_lw3j#define ka0202_cmm$v_cme_d_pe_lw1 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_d_pe_lw1j#define ka0202_cmm$v_cme_d_pe_lw3 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_d_pe_lw3j#define ka0202_cmm$v_cme_d_pe_lw5 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_d_pe_lw5j#define ka0202_cmm$v_cme)*_d_pe_lw7 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_d_pe_lw7b#define ka0202_cmm$v_cme_eue2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_eue2d#define ka0202_cmm$v_cme_meue2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_meue2b#define ka0202_cmm$v_cme_ece2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_ece2d#define ka0202_cmm$v_cme_mece2 ka0202_cmm$r_cme_overlay.ka0202_cmm$r_cme_bits.ka0202_cmm$v_cme_mece2H#define ka0202_cmm**$q_trap1 ka0202_cmm$r_trap1_overlay.ka0202_cmm$q_trap1d#define ka0202_cmm$l_trap1_l ka0202_cmm$r_trap1_overlay.ka0202_cmm$r_trap1_bits.ka0202_cmm$l_trap1_ld#define ka0202_cmm$l_trap1_h ka0202_cmm$r_trap1_overlay.ka0202_cmm$r_trap1_bits.ka0202_cmm$l_trap1_hH#define ka0202_cmm$q_trap2 ka0202_cmm$r_trap2_overlay.ka0202_cmm$q_trap2d#define ka0202_cmm$l_trap2_l ka0202_cmm$r_trap2_overlay.ka0202_cmm$r_trap2_bits.ka0202_cmm$l_trap2_ld#define ka0202_cmm$l_trap2_h ka0202_cmm$r_trap2_overlay.ka0202_cmm$r_t+*rap2_bits.ka0202_cmm$l_trap2_hE#define ka0202_cmm$q_cnfg ka0202_cmm$r_cnfg_overlay.ka0202_cmm$q_cnfgl#define ka0202_cmm$v_cnfg_mod_id1 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_mod_id1p#define ka0202_cmm$v_cnfg_mod_size1 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_mod_size1f#define ka0202_cmm$v_cnfg_emd1 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_emd1r#define ka0202_cmm$v_cnfg_intr_mode1 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$,*r_cnfg_bits.ka0202_cmm$v_cnfg_intr_mode1r#define ka0202_cmm$v_cnfg_intr_unit1 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_intr_unit1r#define ka0202_cmm$v_cnfg_base_addr1 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_base_addr1n#define ka0202_cmm$v_cnfg_mem_enb1 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_mem_enb1l#define ka0202_cmm$v_cnfg_mod_id2 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_mod_id2p#define ka-*0202_cmm$v_cnfg_mod_size2 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_mod_size2f#define ka0202_cmm$v_cnfg_emd2 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_emd2r#define ka0202_cmm$v_cnfg_intr_mode2 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_intr_mode2r#define ka0202_cmm$v_cnfg_intr_unit2 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_intr_unit2r#define ka0202_cmm$v_cnfg_base_addr2 ka0202_cmm$r_cnfg_overlay.ka0.*202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_base_addr2n#define ka0202_cmm$v_cnfg_mem_enb2 ka0202_cmm$r_cnfg_overlay.ka0202_cmm$r_cnfg_bits.ka0202_cmm$v_cnfg_mem_enb2E#define ka0202_cmm$q_edc1 ka0202_cmm$r_edc1_overlay.ka0202_cmm$q_edc1t#define ka0202_cmm$v_edc1_read_cbits1 ka0202_cmm$r_edc1_overlay.ka0202_cmm$r_edc1_bits.ka0202_cmm$v_edc1_read_cbits1p#define ka0202_cmm$v_edc1_wr_cbits1 ka0202_cmm$r_edc1_overlay.ka0202_cmm$r_edc1_bits.ka0202_cmm$v_edc1_wr_cbits1t#define ka0202_cmm$v_edc1_read_cbits2 ka/*0202_cmm$r_edc1_overlay.ka0202_cmm$r_edc1_bits.ka0202_cmm$v_edc1_read_cbits2p#define ka0202_cmm$v_edc1_wr_cbits2 ka0202_cmm$r_edc1_overlay.ka0202_cmm$r_edc1_bits.ka0202_cmm$v_edc1_wr_cbits2E#define ka0202_cmm$q_edc2 ka0202_cmm$r_edc2_overlay.ka0202_cmm$q_edc2p#define ka0202_cmm$v_edc2_syndrome1 ka0202_cmm$r_edc2_overlay.ka0202_cmm$r_edc2_bits.ka0202_cmm$v_edc2_syndrome1p#define ka0202_cmm$v_edc2_syndrome2 ka0202_cmm$r_edc2_overlay.ka0202_cmm$r_edc2_bits.ka0202_cmm$v_edc2_syndrome2H#define ka02020*_cmm$q_edctl ka0202_cmm$r_edctl_overlay.ka0202_cmm$q_edctlj#define ka0202_cmm$v_edctl_srb1 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_srb1l#define ka0202_cmm$v_edctl_uscb1 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_uscb1n#define ka0202_cmm$v_edctl_uswcb1 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_uswcb1l#define ka0202_cmm$v_edctl_dipc1 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_dipc1p#defin1*e ka0202_cmm$v_edctl_enb_es1 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_enb_es1l#define ka0202_cmm$v_edctl_swcb1 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_swcb1l#define ka0202_cmm$v_edctl_crdp1 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_crdp1t#define ka0202_cmm$v_edctl_enb_crdr1 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_enb_crdr1t#define ka0202_cmm$v_edctl_dedccorr1 ka0202_cmm$r_edctl_over2*lay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_dedccorr1x#define ka0202_cmm$v_edctl_dedcreport1 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_dedcreport1j#define ka0202_cmm$v_edctl_srb2 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_srb2l#define ka0202_cmm$v_edctl_uscb2 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_uscb2n#define ka0202_cmm$v_edctl_uswcb2 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_uswc3*b2l#define ka0202_cmm$v_edctl_dipc2 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_dipc2p#define ka0202_cmm$v_edctl_enb_es2 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_enb_es2l#define ka0202_cmm$v_edctl_swcb2 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_swcb2l#define ka0202_cmm$v_edctl_crdp2 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_crdp2t#define ka0202_cmm$v_edctl_enb_crdr2 ka0202_cmm$r_edctl_ov4*erlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_enb_crdr2t#define ka0202_cmm$v_edctl_dedccorr2 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_dedccorr2x#define ka0202_cmm$v_edctl_dedcreport2 ka0202_cmm$r_edctl_overlay.ka0202_cmm$r_edctl_bits.ka0202_cmm$v_edctl_dedcreport2K#define ka0202_cmm$q_sbctrl ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$q_sbctrln#define ka0202_cmm$v_sbctrl_dsd1 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$r_sbctrl_bits.ka0202_cmm$v_sbctrl_dsd1n#define ka0202_c5*mm$v_sbctrl_dsh1 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$r_sbctrl_bits.ka0202_cmm$v_sbctrl_dsh1n#define ka0202_cmm$v_sbctrl_dsf1 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$r_sbctrl_bits.ka0202_cmm$v_sbctrl_dsf1n#define ka0202_cmm$v_sbctrl_dsi1 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$r_sbctrl_bits.ka0202_cmm$v_sbctrl_dsi1p#define ka0202_cmm$v_sbctrl_erwd1 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$r_sbctrl_bits.ka0202_cmm$v_sbctrl_erwd1n#define ka0202_cmm$v_sbctrl_fhb1 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$6*r_sbctrl_bits.ka0202_cmm$v_sbctrl_fhb1n#define ka0202_cmm$v_sbctrl_dsd2 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$r_sbctrl_bits.ka0202_cmm$v_sbctrl_dsd2n#define ka0202_cmm$v_sbctrl_dsh2 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$r_sbctrl_bits.ka0202_cmm$v_sbctrl_dsh2n#define ka0202_cmm$v_sbctrl_dsf2 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$r_sbctrl_bits.ka0202_cmm$v_sbctrl_dsf2n#define ka0202_cmm$v_sbctrl_dsi2 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$r_sbctrl_bits.ka0202_cmm$v_sbctrl_dsi2p#define ka0202_cmm7*$v_sbctrl_erwd2 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$r_sbctrl_bits.ka0202_cmm$v_sbctrl_erwd2n#define ka0202_cmm$v_sbctrl_fhb2 ka0202_cmm$r_sbctrl_overlay.ka0202_cmm$r_sbctrl_bits.ka0202_cmm$v_sbctrl_fhb2G#define ka0202_cmm$q_rctrl ka0202_cmm$r_csr8_overlay.ka0202_cmm$q_rctrlg#define ka0202_cmm$v_rctrl_rc1 ka0202_cmm$r_csr8_overlay.ka0202_cmm$r_rctrl_bits.ka0202_cmm$v_rctrl_rc1o#define ka0202_cmm$v_rctrl_ref_enb ka0202_cmm$r_csr8_overlay.ka0202_cmm$r_rctrl_bits.ka0202_cmm$v_rctrl_ref_enbg#def8*ine ka0202_cmm$v_rctrl_rc2 ka0202_cmm$r_csr8_overlay.ka0202_cmm$r_rctrl_bits.ka0202_cmm$v_rctrl_rc2q#define ka0202_cmm$v_rctrl_ref_enb2 ka0202_cmm$r_csr8_overlay.ka0202_cmm$r_rctrl_bits.ka0202_cmm$v_rctrl_ref_enb2K#define ka0202_cmm$q_crdctl ka0202_cmm$r_crdctl_overlay.ka0202_cmm$q_crdctll#define ka0202_cmm$v_crdctl_sm1 ka0202_cmm$r_crdctl_overlay.ka0202_cmm$r_crdctl_bits.ka0202_cmm$v_crdctl_sm1l#define ka0202_cmm$v_crdctl_bs1 ka0202_cmm$r_crdctl_overlay.ka0202_cmm$r_crdctl_bits.ka0202_cmm$v_cr9*dctl_bs1n#define ka0202_cmm$v_crdctl_cfe1 ka0202_cmm$r_crdctl_overlay.ka0202_cmm$r_crdctl_bits.ka0202_cmm$v_crdctl_cfe1l#define ka0202_cmm$v_crdctl_sm2 ka0202_cmm$r_crdctl_overlay.ka0202_cmm$r_crdctl_bits.ka0202_cmm$v_crdctl_sm2l#define ka0202_cmm$v_crdctl_bs2 ka0202_cmm$r_crdctl_overlay.ka0202_cmm$r_crdctl_bits.ka0202_cmm$v_crdctl_bs2n#define ka0202_cmm$v_crdctl_cfe2 ka0202_cmm$r_crdctl_overlay.ka0202_cmm$r_crdctl_bits.ka0202_cmm$v_crdctl_cfe2H#define ka0202_cmm$q_csr10 ka0202_cmm$r_csr10_overla :*y.ka0202_cmm$q_csr10H#define ka0202_cmm$q_csr11 ka0202_cmm$r_csr11_overlay.ka0202_cmm$q_csr11H#define ka0202_cmm$q_csr12 ka0202_cmm$r_csr12_overlay.ka0202_cmm$q_csr12H#define ka0202_cmm$q_csr13 ka0202_cmm$r_csr13_overlay.ka0202_cmm$q_csr13H#define ka0202_cmm$q_csr14 ka0202_cmm$r_csr14_overlay.ka0202_cmm$q_csr14H#define ka0202_cmm$q_csr15 ka0202_cmm$r_csr15_overlay.ka0202_cmm$q_csr15"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE ;* /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KA0202DEF_LOADED */ ww\[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary <*software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** propri=*etary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************** >**********************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */I/* Source: 11-MAY-1993 15:20:14 $1$DGA8345:[LIB_H.SRC]KA0302DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KA0302DEF ***/#ifndef __KA0302DEF_LOADED#define __KA0302DEF_LOADED 1 G#pragma __nostandard /* This file uses non-?*ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_pa@*rams#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif (#define KA0302$M_SLOT0_LDEV_DTYPE 0xFFFF+#define KA0302$M_SLOT0_LDEV_DREV 0xFFFF0000!#define KA0302$M_SLOT0_LBER_E 0x1##define KA0302$M_SLOT0_LBER_UCE 0x2$#define KA0302$M_SLOT0_LBER_UCE2 0x4"#def A*ine KA0302$M_SLOT0_LBER_CE 0x8$#define KA0302$M_SLOT0_LBER_CE2 0x10$#define KA0302$M_SLOT0_LBER_CPE 0x20%#define KA0302$M_SLOT0_LBER_CPE2 0x40%#define KA0302$M_SLOT0_LBER_CDPE 0x80'#define KA0302$M_SLOT0_LBER_CDPE2 0x100%#define KA0302$M_SLOT0_LBER_TDE 0x200%#define KA0302$M_SLOT0_LBER_STE 0x400&#define KA0302$M_SLOT0_LBER_CNFE 0x800'#define KA0302$M_SLOT0_LBER_NXAE 0x1000&#define KA0302$M_SLOT0_LBER_CAE 0x2000&#define KA0302$M_SLOT0_LBER_SHE 0x4000&#define KA0302$M_SLOT0_LBER_DIE 0x B*8000(#define KA0302$M_SLOT0_LBER_DTCE 0x10000(#define KA0302$M_SLOT0_LBER_CTCE 0x20000(#define KA0302$M_SLOT0_LBER_NSES 0x40000$#define KA0302$M_SLOT0_LCNR_CEEN 0x1.#define KA0302$M_SLOT0_LCNR_RSTSTAT 0x10000000,#define KA0302$M_SLOT0_LCNR_NHALT 0x20000000+#define KA0302$M_SLOT0_LCNR_NRST 0x40000000*#define KA0302$M_SLOT0_LCNR_STF 0x80000000'#define KA0302$M_SLOT0_IBR_RCV_SDAT 0x1'#define KA0302$M_SLOT0_IBR_XMT_SDAT 0x2##define KA0302$M_SLOT0_IBR_SCLK 0x4##define KA0302$M_SLOT0_LMMR0_EC*N 0x1$#define KA0302$M_SLOT0_LMMR0_INT 0x6$#define KA0302$M_SLOT0_LMMR0_IA 0x18%#define KA0302$M_SLOT0_LMMR0_AW 0x1E0)#define KA0302$M_SLOT0_LMMR0_NBANKS 0x600,#define KA0302$M_SLOT0_LMMR0_ADDR 0xFFFE0000##define KA0302$M_SLOT0_LMMR1_EN 0x1$#define KA0302$M_SLOT0_LMMR1_INT 0x6$#define KA0302$M_SLOT0_LMMR1_IA 0x18%#define KA0302$M_SLOT0_LMMR1_AW 0x1E0)#define KA0302$M_SLOT0_LMMR1_NBANKS 0x600,#define KA0302$M_SLOT0_LMMR1_ADDR 0xFFFE0000##define KA0302$M_SLOT0_LMMR2_EN 0x1$#define KA D*0302$M_SLOT0_LMMR2_INT 0x6$#define KA0302$M_SLOT0_LMMR2_IA 0x18%#define KA0302$M_SLOT0_LMMR2_AW 0x1E0)#define KA0302$M_SLOT0_LMMR2_NBANKS 0x600,#define KA0302$M_SLOT0_LMMR2_ADDR 0xFFFE0000##define KA0302$M_SLOT0_LMMR3_EN 0x1$#define KA0302$M_SLOT0_LMMR3_INT 0x6$#define KA0302$M_SLOT0_LMMR3_IA 0x18%#define KA0302$M_SLOT0_LMMR3_AW 0x1E0)#define KA0302$M_SLOT0_LMMR3_NBANKS 0x600,#define KA0302$M_SLOT0_LMMR3_ADDR 0xFFFE0000##define KA0302$M_SLOT0_LMMR4_EN 0x1$#define KA0302$M_SLOT0_LMMR4E*_INT 0x6$#define KA0302$M_SLOT0_LMMR4_IA 0x18%#define KA0302$M_SLOT0_LMMR4_AW 0x1E0)#define KA0302$M_SLOT0_LMMR4_NBANKS 0x600,#define KA0302$M_SLOT0_LMMR4_ADDR 0xFFFE0000##define KA0302$M_SLOT0_LMMR5_EN 0x1$#define KA0302$M_SLOT0_LMMR5_INT 0x6$#define KA0302$M_SLOT0_LMMR5_IA 0x18%#define KA0302$M_SLOT0_LMMR5_AW 0x1E0)#define KA0302$M_SLOT0_LMMR5_NBANKS 0x600,#define KA0302$M_SLOT0_LMMR5_ADDR 0xFFFE0000##define KA0302$M_SLOT0_LMMR6_EN 0x1$#define KA0302$M_SLOT0_LMMR6_INT 0x6$#define F*KA0302$M_SLOT0_LMMR6_IA 0x18%#define KA0302$M_SLOT0_LMMR6_AW 0x1E0)#define KA0302$M_SLOT0_LMMR6_NBANKS 0x600,#define KA0302$M_SLOT0_LMMR6_ADDR 0xFFFE0000##define KA0302$M_SLOT0_LMMR7_EN 0x1$#define KA0302$M_SLOT0_LMMR7_INT 0x6$#define KA0302$M_SLOT0_LMMR7_IA 0x18%#define KA0302$M_SLOT0_LMMR7_AW 0x1E0)#define KA0302$M_SLOT0_LMMR7_NBANKS 0x600,#define KA0302$M_SLOT0_LMMR7_ADDR 0xFFFE0000+#define KA0302$M_SLOT0_LBESR0_SYNDROME 0x7F+#define KA0302$M_SLOT0_LBESR1_SYNDROME 0x7F+#define KA G*0302$M_SLOT0_LBESR2_SYNDROME 0x7F+#define KA0302$M_SLOT0_LBESR3_SYNDROME 0x7F%#define KA0302$M_SLOT0_LBECR1_CA 0x7F'#define KA0302$M_SLOT0_LBECR1_CID 0x780(#define KA0302$M_SLOT0_LBECR1_RID 0x7800(#define KA0302$M_SLOT0_LBECR1_CNF 0x8000,#define KA0302$M_SLOT0_LBECR1_SHARED 0x10000+#define KA0302$M_SLOT0_LBECR1_DIRTY 0x20000,#define KA0302$M_SLOT0_LBECR1_DCYCLE 0xC0000$#define KA0302$M_SLOT0_MCR_DTYPE 0x1##define KA0302$M_SLOT0_MCR_STRN 0xC #define KA0302$M_SLOT0_AMR_E 0x1##define KAH*0302$M_SLOT0_AMR_INTL 0x6"#define KA0302$M_SLOT0_AMR_IA 0x18##define KA0302$M_SLOT0_AMR_AW 0x1E0'#define KA0302$M_SLOT0_AMR_NBANKS 0x600*#define KA0302$M_SLOT0_AMR_MADR 0xFFFE0000##define KA0302$M_SLOT0_MERA_CER 0x1$#define KA0302$M_SLOT0_MERA_UCER 0x2$#define KA0302$M_SLOT0_MERA_MULE 0x4$#define KA0302$M_SLOT0_MERA_APER 0x8%#define KA0302$M_SLOT0_MERA_CERA 0x10%#define KA0302$M_SLOT0_MERA_CERB 0x20&#define KA0302$M_SLOT0_MERA_FSTR 0x1C0'#define KA0302$M_SLOT0_MERA_BNKER 0x200'#def I*ine KA0302$M_SLOT0_MERA_UCERA 0x400'#define KA0302$M_SLOT0_MERA_UCERB 0x800'#define KA0302$M_SLOT0_MSYNDA_SYND 0xFF$#define KA0302$M_SLOT0_MDRA_FCBS 0x1$#define KA0302$M_SLOT0_MDRA_DRDC 0x2$#define KA0302$M_SLOT0_MDRA_DWDC 0x4$#define KA0302$M_SLOT0_MDRA_BPAS 0x8%#define KA0302$M_SLOT0_MDRA_EXST 0x10%#define KA0302$M_SLOT0_MDRA_STPM 0x20%#define KA0302$M_SLOT0_MDRA_MODE 0x40%#define KA0302$M_SLOT0_MDRA_IGSB 0x80&#define KA0302$M_SLOT0_MDRA_FRPE 0x100&#define KA0302$M_SLOT0_MDRA_FCPEJ* 0x200*#define KA0302$M_SLOT0_MDRA_DCRD 0x8000000*#define KA0302$M_SLOT0_MDRA_RFR 0x30000000,#define KA0302$M_SLOT0_MDRA_BRFSH 0x40000000,#define KA0302$M_SLOT0_MDRA_DRFSH 0x80000000%#define KA0302$M_SLOT0_MCBSA_SCB 0xFF##define KA0302$M_SLOT0_MERB_CER 0x1$#define KA0302$M_SLOT0_MERB_UCER 0x2$#define KA0302$M_SLOT0_MERB_MULE 0x4$#define KA0302$M_SLOT0_MERB_APER 0x8'#define KA0302$M_SLOT0_MSYNDB_SYND 0xFF$#define KA0302$M_SLOT0_MDRB_FCBS 0x1$#define KA0302$M_SLOT0_MDRB_DRDC 0x2$#define K*KA0302$M_SLOT0_MDRB_DWDC 0x4$#define KA0302$M_SLOT0_MDRB_BPAS 0x8%#define KA0302$M_SLOT0_MDRB_EXST 0x10%#define KA0302$M_SLOT0_MDRB_STPM 0x20%#define KA0302$M_SLOT0_MDRB_MODE 0x40%#define KA0302$M_SLOT0_MDRB_IGSB 0x80%#define KA0302$M_SLOT0_MCBSB_SCB 0xFF$#define KA0302$K_LSB_SLOT_SIZE 24576(#define KA0302$M_SLOT1_LDEV_DTYPE 0xFFFF+#define KA0302$M_SLOT1_LDEV_DREV 0xFFFF0000!#define KA0302$M_SLOT1_LBER_E 0x1##define KA0302$M_SLOT1_LBER_UCE 0x2$#define KA0302$M_SLOT1_LBER_UCE2 0x4" L*#define KA0302$M_SLOT1_LBER_CE 0x8$#define KA0302$M_SLOT1_LBER_CE2 0x10$#define KA0302$M_SLOT1_LBER_CPE 0x20%#define KA0302$M_SLOT1_LBER_CPE2 0x40%#define KA0302$M_SLOT1_LBER_CDPE 0x80'#define KA0302$M_SLOT1_LBER_CDPE2 0x100%#define KA0302$M_SLOT1_LBER_TDE 0x200%#define KA0302$M_SLOT1_LBER_STE 0x400&#define KA0302$M_SLOT1_LBER_CNFE 0x800'#define KA0302$M_SLOT1_LBER_NXAE 0x1000&#define KA0302$M_SLOT1_LBER_CAE 0x2000&#define KA0302$M_SLOT1_LBER_SHE 0x4000&#define KA0302$M_SLOT1_LBER_DI M*E 0x8000(#define KA0302$M_SLOT1_LBER_DTCE 0x10000(#define KA0302$M_SLOT1_LBER_CTCE 0x20000(#define KA0302$M_SLOT1_LBER_NSES 0x40000$#define KA0302$M_SLOT1_LCNR_CEEN 0x1.#define KA0302$M_SLOT1_LCNR_RSTSTAT 0x10000000,#define KA0302$M_SLOT1_LCNR_NHALT 0x20000000+#define KA0302$M_SLOT1_LCNR_NRST 0x40000000*#define KA0302$M_SLOT1_LCNR_STF 0x80000000'#define KA0302$M_SLOT1_IBR_RCV_SDAT 0x1'#define KA0302$M_SLOT1_IBR_XMT_SDAT 0x2##define KA0302$M_SLOT1_IBR_SCLK 0x4##define KA0302$M_SLOT1_LMMN*R0_EN 0x1$#define KA0302$M_SLOT1_LMMR0_INT 0x6$#define KA0302$M_SLOT1_LMMR0_IA 0x18%#define KA0302$M_SLOT1_LMMR0_AW 0x1E0)#define KA0302$M_SLOT1_LMMR0_NBANKS 0x600,#define KA0302$M_SLOT1_LMMR0_ADDR 0xFFFE0000##define KA0302$M_SLOT1_LMMR1_EN 0x1$#define KA0302$M_SLOT1_LMMR1_INT 0x6$#define KA0302$M_SLOT1_LMMR1_IA 0x18%#define KA0302$M_SLOT1_LMMR1_AW 0x1E0)#define KA0302$M_SLOT1_LMMR1_NBANKS 0x600,#define KA0302$M_SLOT1_LMMR1_ADDR 0xFFFE0000##define KA0302$M_SLOT1_LMMR2_EN 0x1$#defin O*e KA0302$M_SLOT1_LMMR2_INT 0x6$#define KA0302$M_SLOT1_LMMR2_IA 0x18%#define KA0302$M_SLOT1_LMMR2_AW 0x1E0)#define KA0302$M_SLOT1_LMMR2_NBANKS 0x600,#define KA0302$M_SLOT1_LMMR2_ADDR 0xFFFE0000##define KA0302$M_SLOT1_LMMR3_EN 0x1$#define KA0302$M_SLOT1_LMMR3_INT 0x6$#define KA0302$M_SLOT1_LMMR3_IA 0x18%#define KA0302$M_SLOT1_LMMR3_AW 0x1E0)#define KA0302$M_SLOT1_LMMR3_NBANKS 0x600,#define KA0302$M_SLOT1_LMMR3_ADDR 0xFFFE0000##define KA0302$M_SLOT1_LMMR4_EN 0x1$#define KA0302$M_SLOT1_LP*MMR4_INT 0x6$#define KA0302$M_SLOT1_LMMR4_IA 0x18%#define KA0302$M_SLOT1_LMMR4_AW 0x1E0)#define KA0302$M_SLOT1_LMMR4_NBANKS 0x600,#define KA0302$M_SLOT1_LMMR4_ADDR 0xFFFE0000##define KA0302$M_SLOT1_LMMR5_EN 0x1$#define KA0302$M_SLOT1_LMMR5_INT 0x6$#define KA0302$M_SLOT1_LMMR5_IA 0x18%#define KA0302$M_SLOT1_LMMR5_AW 0x1E0)#define KA0302$M_SLOT1_LMMR5_NBANKS 0x600,#define KA0302$M_SLOT1_LMMR5_ADDR 0xFFFE0000##define KA0302$M_SLOT1_LMMR6_EN 0x1$#define KA0302$M_SLOT1_LMMR6_INT 0x6$#def Q*ine KA0302$M_SLOT1_LMMR6_IA 0x18%#define KA0302$M_SLOT1_LMMR6_AW 0x1E0)#define KA0302$M_SLOT1_LMMR6_NBANKS 0x600,#define KA0302$M_SLOT1_LMMR6_ADDR 0xFFFE0000##define KA0302$M_SLOT1_LMMR7_EN 0x1$#define KA0302$M_SLOT1_LMMR7_INT 0x6$#define KA0302$M_SLOT1_LMMR7_IA 0x18%#define KA0302$M_SLOT1_LMMR7_AW 0x1E0)#define KA0302$M_SLOT1_LMMR7_NBANKS 0x600,#define KA0302$M_SLOT1_LMMR7_ADDR 0xFFFE0000+#define KA0302$M_SLOT1_LBESR0_SYNDROME 0x7F+#define KA0302$M_SLOT1_LBESR1_SYNDROME 0x7F+#defin R*e KA0302$M_SLOT1_LBESR2_SYNDROME 0x7F+#define KA0302$M_SLOT1_LBESR3_SYNDROME 0x7F%#define KA0302$M_SLOT1_LBECR1_CA 0x7F'#define KA0302$M_SLOT1_LBECR1_CID 0x780(#define KA0302$M_SLOT1_LBECR1_RID 0x7800(#define KA0302$M_SLOT1_LBECR1_CNF 0x8000,#define KA0302$M_SLOT1_LBECR1_SHARED 0x10000+#define KA0302$M_SLOT1_LBECR1_DIRTY 0x20000,#define KA0302$M_SLOT1_LBECR1_DCYCLE 0xC0000(#define KA0302$M_SLOT2_LDEV_DTYPE 0xFFFF+#define KA0302$M_SLOT2_LDEV_DREV 0xFFFF0000!#define KA0302$M_SLOT2_LBER_S*E 0x1##define KA0302$M_SLOT2_LBER_UCE 0x2$#define KA0302$M_SLOT2_LBER_UCE2 0x4"#define KA0302$M_SLOT2_LBER_CE 0x8$#define KA0302$M_SLOT2_LBER_CE2 0x10$#define KA0302$M_SLOT2_LBER_CPE 0x20%#define KA0302$M_SLOT2_LBER_CPE2 0x40%#define KA0302$M_SLOT2_LBER_CDPE 0x80'#define KA0302$M_SLOT2_LBER_CDPE2 0x100%#define KA0302$M_SLOT2_LBER_TDE 0x200%#define KA0302$M_SLOT2_LBER_STE 0x400&#define KA0302$M_SLOT2_LBER_CNFE 0x800'#define KA0302$M_SLOT2_LBER_NXAE 0x1000&#define KA0302$M_SLOT2_LBE T*R_CAE 0x2000&#define KA0302$M_SLOT2_LBER_SHE 0x4000&#define KA0302$M_SLOT2_LBER_DIE 0x8000(#define KA0302$M_SLOT2_LBER_DTCE 0x10000(#define KA0302$M_SLOT2_LBER_CTCE 0x20000(#define KA0302$M_SLOT2_LBER_NSES 0x40000$#define KA0302$M_SLOT2_LCNR_CEEN 0x1.#define KA0302$M_SLOT2_LCNR_RSTSTAT 0x10000000,#define KA0302$M_SLOT2_LCNR_NHALT 0x20000000+#define KA0302$M_SLOT2_LCNR_NRST 0x40000000*#define KA0302$M_SLOT2_LCNR_STF 0x80000000'#define KA0302$M_SLOT2_IBR_RCV_SDAT 0x1'#define KA0302$M_SLOT2U*_IBR_XMT_SDAT 0x2##define KA0302$M_SLOT2_IBR_SCLK 0x4##define KA0302$M_SLOT2_LMMR0_EN 0x1$#define KA0302$M_SLOT2_LMMR0_INT 0x6$#define KA0302$M_SLOT2_LMMR0_IA 0x18%#define KA0302$M_SLOT2_LMMR0_AW 0x1E0)#define KA0302$M_SLOT2_LMMR0_NBANKS 0x600,#define KA0302$M_SLOT2_LMMR0_ADDR 0xFFFE0000##define KA0302$M_SLOT2_LMMR1_EN 0x1$#define KA0302$M_SLOT2_LMMR1_INT 0x6$#define KA0302$M_SLOT2_LMMR1_IA 0x18%#define KA0302$M_SLOT2_LMMR1_AW 0x1E0)#define KA0302$M_SLOT2_LMMR1_NBANKS 0x600,#defin V*e KA0302$M_SLOT2_LMMR1_ADDR 0xFFFE0000##define KA0302$M_SLOT2_LMMR2_EN 0x1$#define KA0302$M_SLOT2_LMMR2_INT 0x6$#define KA0302$M_SLOT2_LMMR2_IA 0x18%#define KA0302$M_SLOT2_LMMR2_AW 0x1E0)#define KA0302$M_SLOT2_LMMR2_NBANKS 0x600,#define KA0302$M_SLOT2_LMMR2_ADDR 0xFFFE0000##define KA0302$M_SLOT2_LMMR3_EN 0x1$#define KA0302$M_SLOT2_LMMR3_INT 0x6$#define KA0302$M_SLOT2_LMMR3_IA 0x18%#define KA0302$M_SLOT2_LMMR3_AW 0x1E0)#define KA0302$M_SLOT2_LMMR3_NBANKS 0x600,#define KA0302$M_SLOT2_L W*MMR3_ADDR 0xFFFE0000##define KA0302$M_SLOT2_LMMR4_EN 0x1$#define KA0302$M_SLOT2_LMMR4_INT 0x6$#define KA0302$M_SLOT2_LMMR4_IA 0x18%#define KA0302$M_SLOT2_LMMR4_AW 0x1E0)#define KA0302$M_SLOT2_LMMR4_NBANKS 0x600,#define KA0302$M_SLOT2_LMMR4_ADDR 0xFFFE0000##define KA0302$M_SLOT2_LMMR5_EN 0x1$#define KA0302$M_SLOT2_LMMR5_INT 0x6$#define KA0302$M_SLOT2_LMMR5_IA 0x18%#define KA0302$M_SLOT2_LMMR5_AW 0x1E0)#define KA0302$M_SLOT2_LMMR5_NBANKS 0x600,#define KA0302$M_SLOT2_LMMR5_ADDR 0xFFFE00X*00##define KA0302$M_SLOT2_LMMR6_EN 0x1$#define KA0302$M_SLOT2_LMMR6_INT 0x6$#define KA0302$M_SLOT2_LMMR6_IA 0x18%#define KA0302$M_SLOT2_LMMR6_AW 0x1E0)#define KA0302$M_SLOT2_LMMR6_NBANKS 0x600,#define KA0302$M_SLOT2_LMMR6_ADDR 0xFFFE0000##define KA0302$M_SLOT2_LMMR7_EN 0x1$#define KA0302$M_SLOT2_LMMR7_INT 0x6$#define KA0302$M_SLOT2_LMMR7_IA 0x18%#define KA0302$M_SLOT2_LMMR7_AW 0x1E0)#define KA0302$M_SLOT2_LMMR7_NBANKS 0x600,#define KA0302$M_SLOT2_LMMR7_ADDR 0xFFFE0000+#define KA0302 Y*$M_SLOT2_LBESR0_SYNDROME 0x7F+#define KA0302$M_SLOT2_LBESR1_SYNDROME 0x7F+#define KA0302$M_SLOT2_LBESR2_SYNDROME 0x7F+#define KA0302$M_SLOT2_LBESR3_SYNDROME 0x7F%#define KA0302$M_SLOT2_LBECR1_CA 0x7F'#define KA0302$M_SLOT2_LBECR1_CID 0x780(#define KA0302$M_SLOT2_LBECR1_RID 0x7800(#define KA0302$M_SLOT2_LBECR1_CNF 0x8000,#define KA0302$M_SLOT2_LBECR1_SHARED 0x10000+#define KA0302$M_SLOT2_LBECR1_DIRTY 0x20000,#define KA0302$M_SLOT2_LBECR1_DCYCLE 0xC0000(#define KA0302$M_SLOT3_LDEV_DTYPZ*E 0xFFFF+#define KA0302$M_SLOT3_LDEV_DREV 0xFFFF0000!#define KA0302$M_SLOT3_LBER_E 0x1##define KA0302$M_SLOT3_LBER_UCE 0x2$#define KA0302$M_SLOT3_LBER_UCE2 0x4"#define KA0302$M_SLOT3_LBER_CE 0x8$#define KA0302$M_SLOT3_LBER_CE2 0x10$#define KA0302$M_SLOT3_LBER_CPE 0x20%#define KA0302$M_SLOT3_LBER_CPE2 0x40%#define KA0302$M_SLOT3_LBER_CDPE 0x80'#define KA0302$M_SLOT3_LBER_CDPE2 0x100%#define KA0302$M_SLOT3_LBER_TDE 0x200%#define KA0302$M_SLOT3_LBER_STE 0x400&#define KA0302$M_SLOT3_L [*BER_CNFE 0x800'#define KA0302$M_SLOT3_LBER_NXAE 0x1000&#define KA0302$M_SLOT3_LBER_CAE 0x2000&#define KA0302$M_SLOT3_LBER_SHE 0x4000&#define KA0302$M_SLOT3_LBER_DIE 0x8000(#define KA0302$M_SLOT3_LBER_DTCE 0x10000(#define KA0302$M_SLOT3_LBER_CTCE 0x20000(#define KA0302$M_SLOT3_LBER_NSES 0x40000$#define KA0302$M_SLOT3_LCNR_CEEN 0x1.#define KA0302$M_SLOT3_LCNR_RSTSTAT 0x10000000,#define KA0302$M_SLOT3_LCNR_NHALT 0x20000000+#define KA0302$M_SLOT3_LCNR_NRST 0x40000000*#define KA0302$M_SLOT3_L\*CNR_STF 0x80000000'#define KA0302$M_SLOT3_IBR_RCV_SDAT 0x1'#define KA0302$M_SLOT3_IBR_XMT_SDAT 0x2##define KA0302$M_SLOT3_IBR_SCLK 0x4##define KA0302$M_SLOT3_LMMR0_EN 0x1$#define KA0302$M_SLOT3_LMMR0_INT 0x6$#define KA0302$M_SLOT3_LMMR0_IA 0x18%#define KA0302$M_SLOT3_LMMR0_AW 0x1E0)#define KA0302$M_SLOT3_LMMR0_NBANKS 0x600,#define KA0302$M_SLOT3_LMMR0_ADDR 0xFFFE0000##define KA0302$M_SLOT3_LMMR1_EN 0x1$#define KA0302$M_SLOT3_LMMR1_INT 0x6$#define KA0302$M_SLOT3_LMMR1_IA 0x18%#defin ]*e KA0302$M_SLOT3_LMMR1_AW 0x1E0)#define KA0302$M_SLOT3_LMMR1_NBANKS 0x600,#define KA0302$M_SLOT3_LMMR1_ADDR 0xFFFE0000##define KA0302$M_SLOT3_LMMR2_EN 0x1$#define KA0302$M_SLOT3_LMMR2_INT 0x6$#define KA0302$M_SLOT3_LMMR2_IA 0x18%#define KA0302$M_SLOT3_LMMR2_AW 0x1E0)#define KA0302$M_SLOT3_LMMR2_NBANKS 0x600,#define KA0302$M_SLOT3_LMMR2_ADDR 0xFFFE0000##define KA0302$M_SLOT3_LMMR3_EN 0x1$#define KA0302$M_SLOT3_LMMR3_INT 0x6$#define KA0302$M_SLOT3_LMMR3_IA 0x18%#define KA0302$M_SLOT3_L^*MMR3_AW 0x1E0)#define KA0302$M_SLOT3_LMMR3_NBANKS 0x600,#define KA0302$M_SLOT3_LMMR3_ADDR 0xFFFE0000##define KA0302$M_SLOT3_LMMR4_EN 0x1$#define KA0302$M_SLOT3_LMMR4_INT 0x6$#define KA0302$M_SLOT3_LMMR4_IA 0x18%#define KA0302$M_SLOT3_LMMR4_AW 0x1E0)#define KA0302$M_SLOT3_LMMR4_NBANKS 0x600,#define KA0302$M_SLOT3_LMMR4_ADDR 0xFFFE0000##define KA0302$M_SLOT3_LMMR5_EN 0x1$#define KA0302$M_SLOT3_LMMR5_INT 0x6$#define KA0302$M_SLOT3_LMMR5_IA 0x18%#define KA0302$M_SLOT3_LMMR5_AW 0x1E0)#d _*efine KA0302$M_SLOT3_LMMR5_NBANKS 0x600,#define KA0302$M_SLOT3_LMMR5_ADDR 0xFFFE0000##define KA0302$M_SLOT3_LMMR6_EN 0x1$#define KA0302$M_SLOT3_LMMR6_INT 0x6$#define KA0302$M_SLOT3_LMMR6_IA 0x18%#define KA0302$M_SLOT3_LMMR6_AW 0x1E0)#define KA0302$M_SLOT3_LMMR6_NBANKS 0x600,#define KA0302$M_SLOT3_LMMR6_ADDR 0xFFFE0000##define KA0302$M_SLOT3_LMMR7_EN 0x1$#define KA0302$M_SLOT3_LMMR7_INT 0x6$#define KA0302$M_SLOT3_LMMR7_IA 0x18%#define KA0302$M_SLOT3_LMMR7_AW 0x1E0)#define KA0302$M_SLO `*T3_LMMR7_NBANKS 0x600,#define KA0302$M_SLOT3_LMMR7_ADDR 0xFFFE0000+#define KA0302$M_SLOT3_LBESR0_SYNDROME 0x7F+#define KA0302$M_SLOT3_LBESR1_SYNDROME 0x7F+#define KA0302$M_SLOT3_LBESR2_SYNDROME 0x7F+#define KA0302$M_SLOT3_LBESR3_SYNDROME 0x7F%#define KA0302$M_SLOT3_LBECR1_CA 0x7F'#define KA0302$M_SLOT3_LBECR1_CID 0x780(#define KA0302$M_SLOT3_LBECR1_RID 0x7800(#define KA0302$M_SLOT3_LBECR1_CNF 0x8000,#define KA0302$M_SLOT3_LBECR1_SHARED 0x10000+#define KA0302$M_SLOT3_LBECR1_DIRTY 0x20a*000,#define KA0302$M_SLOT3_LBECR1_DCYCLE 0xC0000(#define KA0302$M_SLOT4_LDEV_DTYPE 0xFFFF+#define KA0302$M_SLOT4_LDEV_DREV 0xFFFF0000!#define KA0302$M_SLOT4_LBER_E 0x1##define KA0302$M_SLOT4_LBER_UCE 0x2$#define KA0302$M_SLOT4_LBER_UCE2 0x4"#define KA0302$M_SLOT4_LBER_CE 0x8$#define KA0302$M_SLOT4_LBER_CE2 0x10$#define KA0302$M_SLOT4_LBER_CPE 0x20%#define KA0302$M_SLOT4_LBER_CPE2 0x40%#define KA0302$M_SLOT4_LBER_CDPE 0x80'#define KA0302$M_SLOT4_LBER_CDPE2 0x100%#define KA0302$M_SLO b*T4_LBER_TDE 0x200%#define KA0302$M_SLOT4_LBER_STE 0x400&#define KA0302$M_SLOT4_LBER_CNFE 0x800'#define KA0302$M_SLOT4_LBER_NXAE 0x1000&#define KA0302$M_SLOT4_LBER_CAE 0x2000&#define KA0302$M_SLOT4_LBER_SHE 0x4000&#define KA0302$M_SLOT4_LBER_DIE 0x8000(#define KA0302$M_SLOT4_LBER_DTCE 0x10000(#define KA0302$M_SLOT4_LBER_CTCE 0x20000(#define KA0302$M_SLOT4_LBER_NSES 0x40000$#define KA0302$M_SLOT4_LCNR_CEEN 0x1.#define KA0302$M_SLOT4_LCNR_RSTSTAT 0x10000000,#define KA0302$M_SLOT4_LCNR_NHAL c*T 0x20000000+#define KA0302$M_SLOT4_LCNR_NRST 0x40000000*#define KA0302$M_SLOT4_LCNR_STF 0x80000000'#define KA0302$M_SLOT4_IBR_RCV_SDAT 0x1'#define KA0302$M_SLOT4_IBR_XMT_SDAT 0x2##define KA0302$M_SLOT4_IBR_SCLK 0x4##define KA0302$M_SLOT4_LMMR0_EN 0x1$#define KA0302$M_SLOT4_LMMR0_INT 0x6$#define KA0302$M_SLOT4_LMMR0_IA 0x18%#define KA0302$M_SLOT4_LMMR0_AW 0x1E0)#define KA0302$M_SLOT4_LMMR0_NBANKS 0x600,#define KA0302$M_SLOT4_LMMR0_ADDR 0xFFFE0000##define KA0302$M_SLOT4_LMMR1_EN 0x1 d*$#define KA0302$M_SLOT4_LMMR1_INT 0x6$#define KA0302$M_SLOT4_LMMR1_IA 0x18%#define KA0302$M_SLOT4_LMMR1_AW 0x1E0)#define KA0302$M_SLOT4_LMMR1_NBANKS 0x600,#define KA0302$M_SLOT4_LMMR1_ADDR 0xFFFE0000##define KA0302$M_SLOT4_LMMR2_EN 0x1$#define KA0302$M_SLOT4_LMMR2_INT 0x6$#define KA0302$M_SLOT4_LMMR2_IA 0x18%#define KA0302$M_SLOT4_LMMR2_AW 0x1E0)#define KA0302$M_SLOT4_LMMR2_NBANKS 0x600,#define KA0302$M_SLOT4_LMMR2_ADDR 0xFFFE0000##define KA0302$M_SLOT4_LMMR3_EN 0x1$#define KA0302$M e*_SLOT4_LMMR3_INT 0x6$#define KA0302$M_SLOT4_LMMR3_IA 0x18%#define KA0302$M_SLOT4_LMMR3_AW 0x1E0)#define KA0302$M_SLOT4_LMMR3_NBANKS 0x600,#define KA0302$M_SLOT4_LMMR3_ADDR 0xFFFE0000##define KA0302$M_SLOT4_LMMR4_EN 0x1$#define KA0302$M_SLOT4_LMMR4_INT 0x6$#define KA0302$M_SLOT4_LMMR4_IA 0x18%#define KA0302$M_SLOT4_LMMR4_AW 0x1E0)#define KA0302$M_SLOT4_LMMR4_NBANKS 0x600,#define KA0302$M_SLOT4_LMMR4_ADDR 0xFFFE0000##define KA0302$M_SLOT4_LMMR5_EN 0x1$#define KA0302$M_SLOT4_LMMR5_INT 0f*x6$#define KA0302$M_SLOT4_LMMR5_IA 0x18%#define KA0302$M_SLOT4_LMMR5_AW 0x1E0)#define KA0302$M_SLOT4_LMMR5_NBANKS 0x600,#define KA0302$M_SLOT4_LMMR5_ADDR 0xFFFE0000##define KA0302$M_SLOT4_LMMR6_EN 0x1$#define KA0302$M_SLOT4_LMMR6_INT 0x6$#define KA0302$M_SLOT4_LMMR6_IA 0x18%#define KA0302$M_SLOT4_LMMR6_AW 0x1E0)#define KA0302$M_SLOT4_LMMR6_NBANKS 0x600,#define KA0302$M_SLOT4_LMMR6_ADDR 0xFFFE0000##define KA0302$M_SLOT4_LMMR7_EN 0x1$#define KA0302$M_SLOT4_LMMR7_INT 0x6$#define KA0302 g*$M_SLOT4_LMMR7_IA 0x18%#define KA0302$M_SLOT4_LMMR7_AW 0x1E0)#define KA0302$M_SLOT4_LMMR7_NBANKS 0x600,#define KA0302$M_SLOT4_LMMR7_ADDR 0xFFFE0000+#define KA0302$M_SLOT4_LBESR0_SYNDROME 0x7F+#define KA0302$M_SLOT4_LBESR1_SYNDROME 0x7F+#define KA0302$M_SLOT4_LBESR2_SYNDROME 0x7F+#define KA0302$M_SLOT4_LBESR3_SYNDROME 0x7F%#define KA0302$M_SLOT4_LBECR1_CA 0x7F'#define KA0302$M_SLOT4_LBECR1_CID 0x780(#define KA0302$M_SLOT4_LBECR1_RID 0x7800(#define KA0302$M_SLOT4_LBECR1_CNF 0x8000,#d h*efine KA0302$M_SLOT4_LBECR1_SHARED 0x10000+#define KA0302$M_SLOT4_LBECR1_DIRTY 0x20000,#define KA0302$M_SLOT4_LBECR1_DCYCLE 0xC0000(#define KA0302$M_SLOT5_LDEV_DTYPE 0xFFFF+#define KA0302$M_SLOT5_LDEV_DREV 0xFFFF0000!#define KA0302$M_SLOT5_LBER_E 0x1##define KA0302$M_SLOT5_LBER_UCE 0x2$#define KA0302$M_SLOT5_LBER_UCE2 0x4"#define KA0302$M_SLOT5_LBER_CE 0x8$#define KA0302$M_SLOT5_LBER_CE2 0x10$#define KA0302$M_SLOT5_LBER_CPE 0x20%#define KA0302$M_SLOT5_LBER_CPE2 0x40%#define KA0302$M_S i*LOT5_LBER_CDPE 0x80'#define KA0302$M_SLOT5_LBER_CDPE2 0x100%#define KA0302$M_SLOT5_LBER_TDE 0x200%#define KA0302$M_SLOT5_LBER_STE 0x400&#define KA0302$M_SLOT5_LBER_CNFE 0x800'#define KA0302$M_SLOT5_LBER_NXAE 0x1000&#define KA0302$M_SLOT5_LBER_CAE 0x2000&#define KA0302$M_SLOT5_LBER_SHE 0x4000&#define KA0302$M_SLOT5_LBER_DIE 0x8000(#define KA0302$M_SLOT5_LBER_DTCE 0x10000(#define KA0302$M_SLOT5_LBER_CTCE 0x20000(#define KA0302$M_SLOT5_LBER_NSES 0x40000$#define KA0302$M_SLOT5_LCNR_CEEN 0 j*x1.#define KA0302$M_SLOT5_LCNR_RSTSTAT 0x10000000,#define KA0302$M_SLOT5_LCNR_NHALT 0x20000000+#define KA0302$M_SLOT5_LCNR_NRST 0x40000000*#define KA0302$M_SLOT5_LCNR_STF 0x80000000'#define KA0302$M_SLOT5_IBR_RCV_SDAT 0x1'#define KA0302$M_SLOT5_IBR_XMT_SDAT 0x2##define KA0302$M_SLOT5_IBR_SCLK 0x4##define KA0302$M_SLOT5_LMMR0_EN 0x1$#define KA0302$M_SLOT5_LMMR0_INT 0x6$#define KA0302$M_SLOT5_LMMR0_IA 0x18%#define KA0302$M_SLOT5_LMMR0_AW 0x1E0)#define KA0302$M_SLOT5_LMMR0_NBANKS 0x600 k*,#define KA0302$M_SLOT5_LMMR0_ADDR 0xFFFE0000##define KA0302$M_SLOT5_LMMR1_EN 0x1$#define KA0302$M_SLOT5_LMMR1_INT 0x6$#define KA0302$M_SLOT5_LMMR1_IA 0x18%#define KA0302$M_SLOT5_LMMR1_AW 0x1E0)#define KA0302$M_SLOT5_LMMR1_NBANKS 0x600,#define KA0302$M_SLOT5_LMMR1_ADDR 0xFFFE0000##define KA0302$M_SLOT5_LMMR2_EN 0x1$#define KA0302$M_SLOT5_LMMR2_INT 0x6$#define KA0302$M_SLOT5_LMMR2_IA 0x18%#define KA0302$M_SLOT5_LMMR2_AW 0x1E0)#define KA0302$M_SLOT5_LMMR2_NBANKS 0x600,#define KA0302$M l*_SLOT5_LMMR2_ADDR 0xFFFE0000##define KA0302$M_SLOT5_LMMR3_EN 0x1$#define KA0302$M_SLOT5_LMMR3_INT 0x6$#define KA0302$M_SLOT5_LMMR3_IA 0x18%#define KA0302$M_SLOT5_LMMR3_AW 0x1E0)#define KA0302$M_SLOT5_LMMR3_NBANKS 0x600,#define KA0302$M_SLOT5_LMMR3_ADDR 0xFFFE0000##define KA0302$M_SLOT5_LMMR4_EN 0x1$#define KA0302$M_SLOT5_LMMR4_INT 0x6$#define KA0302$M_SLOT5_LMMR4_IA 0x18%#define KA0302$M_SLOT5_LMMR4_AW 0x1E0)#define KA0302$M_SLOT5_LMMR4_NBANKS 0x600,#define KA0302$M_SLOT5_LMMR4_ADDR m*0xFFFE0000##define KA0302$M_SLOT5_LMMR5_EN 0x1$#define KA0302$M_SLOT5_LMMR5_INT 0x6$#define KA0302$M_SLOT5_LMMR5_IA 0x18%#define KA0302$M_SLOT5_LMMR5_AW 0x1E0)#define KA0302$M_SLOT5_LMMR5_NBANKS 0x600,#define KA0302$M_SLOT5_LMMR5_ADDR 0xFFFE0000##define KA0302$M_SLOT5_LMMR6_EN 0x1$#define KA0302$M_SLOT5_LMMR6_INT 0x6$#define KA0302$M_SLOT5_LMMR6_IA 0x18%#define KA0302$M_SLOT5_LMMR6_AW 0x1E0)#define KA0302$M_SLOT5_LMMR6_NBANKS 0x600,#define KA0302$M_SLOT5_LMMR6_ADDR 0xFFFE0000##defin n*e KA0302$M_SLOT5_LMMR7_EN 0x1$#define KA0302$M_SLOT5_LMMR7_INT 0x6$#define KA0302$M_SLOT5_LMMR7_IA 0x18%#define KA0302$M_SLOT5_LMMR7_AW 0x1E0)#define KA0302$M_SLOT5_LMMR7_NBANKS 0x600,#define KA0302$M_SLOT5_LMMR7_ADDR 0xFFFE0000+#define KA0302$M_SLOT5_LBESR0_SYNDROME 0x7F+#define KA0302$M_SLOT5_LBESR1_SYNDROME 0x7F+#define KA0302$M_SLOT5_LBESR2_SYNDROME 0x7F+#define KA0302$M_SLOT5_LBESR3_SYNDROME 0x7F%#define KA0302$M_SLOT5_LBECR1_CA 0x7F'#define KA0302$M_SLOT5_LBECR1_CID 0x780(#d o*efine KA0302$M_SLOT5_LBECR1_RID 0x7800(#define KA0302$M_SLOT5_LBECR1_CNF 0x8000,#define KA0302$M_SLOT5_LBECR1_SHARED 0x10000+#define KA0302$M_SLOT5_LBECR1_DIRTY 0x20000,#define KA0302$M_SLOT5_LBECR1_DCYCLE 0xC0000(#define KA0302$M_SLOT6_LDEV_DTYPE 0xFFFF+#define KA0302$M_SLOT6_LDEV_DREV 0xFFFF0000!#define KA0302$M_SLOT6_LBER_E 0x1##define KA0302$M_SLOT6_LBER_UCE 0x2$#define KA0302$M_SLOT6_LBER_UCE2 0x4"#define KA0302$M_SLOT6_LBER_CE 0x8$#define KA0302$M_SLOT6_LBER_CE2 0x10$#define KA03 p*02$M_SLOT6_LBER_CPE 0x20%#define KA0302$M_SLOT6_LBER_CPE2 0x40%#define KA0302$M_SLOT6_LBER_CDPE 0x80'#define KA0302$M_SLOT6_LBER_CDPE2 0x100%#define KA0302$M_SLOT6_LBER_TDE 0x200%#define KA0302$M_SLOT6_LBER_STE 0x400&#define KA0302$M_SLOT6_LBER_CNFE 0x800'#define KA0302$M_SLOT6_LBER_NXAE 0x1000&#define KA0302$M_SLOT6_LBER_CAE 0x2000&#define KA0302$M_SLOT6_LBER_SHE 0x4000&#define KA0302$M_SLOT6_LBER_DIE 0x8000(#define KA0302$M_SLOT6_LBER_DTCE 0x10000(#define KA0302$M_SLOT6_LBER_CTCE 0 q*x20000(#define KA0302$M_SLOT6_LBER_NSES 0x40000$#define KA0302$M_SLOT6_LCNR_CEEN 0x1.#define KA0302$M_SLOT6_LCNR_RSTSTAT 0x10000000,#define KA0302$M_SLOT6_LCNR_NHALT 0x20000000+#define KA0302$M_SLOT6_LCNR_NRST 0x40000000*#define KA0302$M_SLOT6_LCNR_STF 0x80000000'#define KA0302$M_SLOT6_IBR_RCV_SDAT 0x1'#define KA0302$M_SLOT6_IBR_XMT_SDAT 0x2##define KA0302$M_SLOT6_IBR_SCLK 0x4##define KA0302$M_SLOT6_LMMR0_EN 0x1$#define KA0302$M_SLOT6_LMMR0_INT 0x6$#define KA0302$M_SLOT6_LMMR0_IA 0x18 r*%#define KA0302$M_SLOT6_LMMR0_AW 0x1E0)#define KA0302$M_SLOT6_LMMR0_NBANKS 0x600,#define KA0302$M_SLOT6_LMMR0_ADDR 0xFFFE0000##define KA0302$M_SLOT6_LMMR1_EN 0x1$#define KA0302$M_SLOT6_LMMR1_INT 0x6$#define KA0302$M_SLOT6_LMMR1_IA 0x18%#define KA0302$M_SLOT6_LMMR1_AW 0x1E0)#define KA0302$M_SLOT6_LMMR1_NBANKS 0x600,#define KA0302$M_SLOT6_LMMR1_ADDR 0xFFFE0000##define KA0302$M_SLOT6_LMMR2_EN 0x1$#define KA0302$M_SLOT6_LMMR2_INT 0x6$#define KA0302$M_SLOT6_LMMR2_IA 0x18%#define KA0302$M s*_SLOT6_LMMR2_AW 0x1E0)#define KA0302$M_SLOT6_LMMR2_NBANKS 0x600,#define KA0302$M_SLOT6_LMMR2_ADDR 0xFFFE0000##define KA0302$M_SLOT6_LMMR3_EN 0x1$#define KA0302$M_SLOT6_LMMR3_INT 0x6$#define KA0302$M_SLOT6_LMMR3_IA 0x18%#define KA0302$M_SLOT6_LMMR3_AW 0x1E0)#define KA0302$M_SLOT6_LMMR3_NBANKS 0x600,#define KA0302$M_SLOT6_LMMR3_ADDR 0xFFFE0000##define KA0302$M_SLOT6_LMMR4_EN 0x1$#define KA0302$M_SLOT6_LMMR4_INT 0x6$#define KA0302$M_SLOT6_LMMR4_IA 0x18%#define KA0302$M_SLOT6_LMMR4_AW 0xt*1E0)#define KA0302$M_SLOT6_LMMR4_NBANKS 0x600,#define KA0302$M_SLOT6_LMMR4_ADDR 0xFFFE0000##define KA0302$M_SLOT6_LMMR5_EN 0x1$#define KA0302$M_SLOT6_LMMR5_INT 0x6$#define KA0302$M_SLOT6_LMMR5_IA 0x18%#define KA0302$M_SLOT6_LMMR5_AW 0x1E0)#define KA0302$M_SLOT6_LMMR5_NBANKS 0x600,#define KA0302$M_SLOT6_LMMR5_ADDR 0xFFFE0000##define KA0302$M_SLOT6_LMMR6_EN 0x1$#define KA0302$M_SLOT6_LMMR6_INT 0x6$#define KA0302$M_SLOT6_LMMR6_IA 0x18%#define KA0302$M_SLOT6_LMMR6_AW 0x1E0)#define KA03 u*02$M_SLOT6_LMMR6_NBANKS 0x600,#define KA0302$M_SLOT6_LMMR6_ADDR 0xFFFE0000##define KA0302$M_SLOT6_LMMR7_EN 0x1$#define KA0302$M_SLOT6_LMMR7_INT 0x6$#define KA0302$M_SLOT6_LMMR7_IA 0x18%#define KA0302$M_SLOT6_LMMR7_AW 0x1E0)#define KA0302$M_SLOT6_LMMR7_NBANKS 0x600,#define KA0302$M_SLOT6_LMMR7_ADDR 0xFFFE0000+#define KA0302$M_SLOT6_LBESR0_SYNDROME 0x7F+#define KA0302$M_SLOT6_LBESR1_SYNDROME 0x7F+#define KA0302$M_SLOT6_LBESR2_SYNDROME 0x7F+#define KA0302$M_SLOT6_LBESR3_SYNDROME 0x7F% v*#define KA0302$M_SLOT6_LBECR1_CA 0x7F'#define KA0302$M_SLOT6_LBECR1_CID 0x780(#define KA0302$M_SLOT6_LBECR1_RID 0x7800(#define KA0302$M_SLOT6_LBECR1_CNF 0x8000,#define KA0302$M_SLOT6_LBECR1_SHARED 0x10000+#define KA0302$M_SLOT6_LBECR1_DIRTY 0x20000,#define KA0302$M_SLOT6_LBECR1_DCYCLE 0xC0000(#define KA0302$M_SLOT7_LDEV_DTYPE 0xFFFF+#define KA0302$M_SLOT7_LDEV_DREV 0xFFFF0000!#define KA0302$M_SLOT7_LBER_E 0x1##define KA0302$M_SLOT7_LBER_UCE 0x2$#define KA0302$M_SLOT7_LBER_UCE2 0x4"#d w*efine KA0302$M_SLOT7_LBER_CE 0x8$#define KA0302$M_SLOT7_LBER_CE2 0x10$#define KA0302$M_SLOT7_LBER_CPE 0x20%#define KA0302$M_SLOT7_LBER_CPE2 0x40%#define KA0302$M_SLOT7_LBER_CDPE 0x80'#define KA0302$M_SLOT7_LBER_CDPE2 0x100%#define KA0302$M_SLOT7_LBER_TDE 0x200%#define KA0302$M_SLOT7_LBER_STE 0x400&#define KA0302$M_SLOT7_LBER_CNFE 0x800'#define KA0302$M_SLOT7_LBER_NXAE 0x1000&#define KA0302$M_SLOT7_LBER_CAE 0x2000&#define KA0302$M_SLOT7_LBER_SHE 0x4000&#define KA0302$M_SLOT7_LBER_DIE x*0x8000(#define KA0302$M_SLOT7_LBER_DTCE 0x10000(#define KA0302$M_SLOT7_LBER_CTCE 0x20000(#define KA0302$M_SLOT7_LBER_NSES 0x40000$#define KA0302$M_SLOT7_LCNR_CEEN 0x1.#define KA0302$M_SLOT7_LCNR_RSTSTAT 0x10000000,#define KA0302$M_SLOT7_LCNR_NHALT 0x20000000+#define KA0302$M_SLOT7_LCNR_NRST 0x40000000*#define KA0302$M_SLOT7_LCNR_STF 0x80000000'#define KA0302$M_SLOT7_IBR_RCV_SDAT 0x1'#define KA0302$M_SLOT7_IBR_XMT_SDAT 0x2##define KA0302$M_SLOT7_IBR_SCLK 0x4##define KA0302$M_SLOT7_LMMR0y*_EN 0x1$#define KA0302$M_SLOT7_LMMR0_INT 0x6$#define KA0302$M_SLOT7_LMMR0_IA 0x18%#define KA0302$M_SLOT7_LMMR0_AW 0x1E0)#define KA0302$M_SLOT7_LMMR0_NBANKS 0x600,#define KA0302$M_SLOT7_LMMR0_ADDR 0xFFFE0000##define KA0302$M_SLOT7_LMMR1_EN 0x1$#define KA0302$M_SLOT7_LMMR1_INT 0x6$#define KA0302$M_SLOT7_LMMR1_IA 0x18%#define KA0302$M_SLOT7_LMMR1_AW 0x1E0)#define KA0302$M_SLOT7_LMMR1_NBANKS 0x600,#define KA0302$M_SLOT7_LMMR1_ADDR 0xFFFE0000##define KA0302$M_SLOT7_LMMR2_EN 0x1$#define z*KA0302$M_SLOT7_LMMR2_INT 0x6$#define KA0302$M_SLOT7_LMMR2_IA 0x18%#define KA0302$M_SLOT7_LMMR2_AW 0x1E0)#define KA0302$M_SLOT7_LMMR2_NBANKS 0x600,#define KA0302$M_SLOT7_LMMR2_ADDR 0xFFFE0000##define KA0302$M_SLOT7_LMMR3_EN 0x1$#define KA0302$M_SLOT7_LMMR3_INT 0x6$#define KA0302$M_SLOT7_LMMR3_IA 0x18%#define KA0302$M_SLOT7_LMMR3_AW 0x1E0)#define KA0302$M_SLOT7_LMMR3_NBANKS 0x600,#define KA0302$M_SLOT7_LMMR3_ADDR 0xFFFE0000##define KA0302$M_SLOT7_LMMR4_EN 0x1$#define KA0302$M_SLOT7_LMM{*R4_INT 0x6$#define KA0302$M_SLOT7_LMMR4_IA 0x18%#define KA0302$M_SLOT7_LMMR4_AW 0x1E0)#define KA0302$M_SLOT7_LMMR4_NBANKS 0x600,#define KA0302$M_SLOT7_LMMR4_ADDR 0xFFFE0000##define KA0302$M_SLOT7_LMMR5_EN 0x1$#define KA0302$M_SLOT7_LMMR5_INT 0x6$#define KA0302$M_SLOT7_LMMR5_IA 0x18%#define KA0302$M_SLOT7_LMMR5_AW 0x1E0)#define KA0302$M_SLOT7_LMMR5_NBANKS 0x600,#define KA0302$M_SLOT7_LMMR5_ADDR 0xFFFE0000##define KA0302$M_SLOT7_LMMR6_EN 0x1$#define KA0302$M_SLOT7_LMMR6_INT 0x6$#defin |*e KA0302$M_SLOT7_LMMR6_IA 0x18%#define KA0302$M_SLOT7_LMMR6_AW 0x1E0)#define KA0302$M_SLOT7_LMMR6_NBANKS 0x600,#define KA0302$M_SLOT7_LMMR6_ADDR 0xFFFE0000##define KA0302$M_SLOT7_LMMR7_EN 0x1$#define KA0302$M_SLOT7_LMMR7_INT 0x6$#define KA0302$M_SLOT7_LMMR7_IA 0x18%#define KA0302$M_SLOT7_LMMR7_AW 0x1E0)#define KA0302$M_SLOT7_LMMR7_NBANKS 0x600,#define KA0302$M_SLOT7_LMMR7_ADDR 0xFFFE0000+#define KA0302$M_SLOT7_LBESR0_SYNDROME 0x7F+#define KA0302$M_SLOT7_LBESR1_SYNDROME 0x7F+#define }*KA0302$M_SLOT7_LBESR2_SYNDROME 0x7F+#define KA0302$M_SLOT7_LBESR3_SYNDROME 0x7F%#define KA0302$M_SLOT7_LBECR1_CA 0x7F'#define KA0302$M_SLOT7_LBECR1_CID 0x780(#define KA0302$M_SLOT7_LBECR1_RID 0x7800(#define KA0302$M_SLOT7_LBECR1_CNF 0x8000,#define KA0302$M_SLOT7_LBECR1_SHARED 0x10000+#define KA0302$M_SLOT7_LBECR1_DIRTY 0x20000,#define KA0302$M_SLOT7_LBECR1_DCYCLE 0xC0000(#define KA0302$M_SLOT8_LDEV_DTYPE 0xFFFF+#define KA0302$M_SLOT8_LDEV_DREV 0xFFFF0000!#define KA0302$M_SLOT8_LBER_E ~*0x1##define KA0302$M_SLOT8_LBER_UCE 0x2$#define KA0302$M_SLOT8_LBER_UCE2 0x4"#define KA0302$M_SLOT8_LBER_CE 0x8$#define KA0302$M_SLOT8_LBER_CE2 0x10$#define KA0302$M_SLOT8_LBER_CPE 0x20%#define KA0302$M_SLOT8_LBER_CPE2 0x40%#define KA0302$M_SLOT8_LBER_CDPE 0x80'#define KA0302$M_SLOT8_LBER_CDPE2 0x100%#define KA0302$M_SLOT8_LBER_TDE 0x200%#define KA0302$M_SLOT8_LBER_STE 0x400&#define KA0302$M_SLOT8_LBER_CNFE 0x800'#define KA0302$M_SLOT8_LBER_NXAE 0x1000&#define KA0302$M_SLOT8_LBER_ *CAE 0x2000&#define KA0302$M_SLOT8_LBER_SHE 0x4000&#define KA0302$M_SLOT8_LBER_DIE 0x8000(#define KA0302$M_SLOT8_LBER_DTCE 0x10000(#define KA0302$M_SLOT8_LBER_CTCE 0x20000(#define KA0302$M_SLOT8_LBER_NSES 0x40000$#define KA0302$M_SLOT8_LCNR_CEEN 0x1.#define KA0302$M_SLOT8_LCNR_RSTSTAT 0x10000000,#define KA0302$M_SLOT8_LCNR_NHALT 0x20000000+#define KA0302$M_SLOT8_LCNR_NRST 0x40000000*#define KA0302$M_SLOT8_LCNR_STF 0x80000000'#define KA0302$M_SLOT8_IBR_RCV_SDAT 0x1'#define KA0302$M_SLOT8_I*BR_XMT_SDAT 0x2##define KA0302$M_SLOT8_IBR_SCLK 0x4##define KA0302$M_SLOT8_LMMR0_EN 0x1$#define KA0302$M_SLOT8_LMMR0_INT 0x6$#define KA0302$M_SLOT8_LMMR0_IA 0x18%#define KA0302$M_SLOT8_LMMR0_AW 0x1E0)#define KA0302$M_SLOT8_LMMR0_NBANKS 0x600,#define KA0302$M_SLOT8_LMMR0_ADDR 0xFFFE0000##define KA0302$M_SLOT8_LMMR1_EN 0x1$#define KA0302$M_SLOT8_LMMR1_INT 0x6$#define KA0302$M_SLOT8_LMMR1_IA 0x18%#define KA0302$M_SLOT8_LMMR1_AW 0x1E0)#define KA0302$M_SLOT8_LMMR1_NBANKS 0x600,#define *KA0302$M_SLOT8_LMMR1_ADDR 0xFFFE0000##define KA0302$M_SLOT8_LMMR2_EN 0x1$#define KA0302$M_SLOT8_LMMR2_INT 0x6$#define KA0302$M_SLOT8_LMMR2_IA 0x18%#define KA0302$M_SLOT8_LMMR2_AW 0x1E0)#define KA0302$M_SLOT8_LMMR2_NBANKS 0x600,#define KA0302$M_SLOT8_LMMR2_ADDR 0xFFFE0000##define KA0302$M_SLOT8_LMMR3_EN 0x1$#define KA0302$M_SLOT8_LMMR3_INT 0x6$#define KA0302$M_SLOT8_LMMR3_IA 0x18%#define KA0302$M_SLOT8_LMMR3_AW 0x1E0)#define KA0302$M_SLOT8_LMMR3_NBANKS 0x600,#define KA0302$M_SLOT8_LMM *R3_ADDR 0xFFFE0000##define KA0302$M_SLOT8_LMMR4_EN 0x1$#define KA0302$M_SLOT8_LMMR4_INT 0x6$#define KA0302$M_SLOT8_LMMR4_IA 0x18%#define KA0302$M_SLOT8_LMMR4_AW 0x1E0)#define KA0302$M_SLOT8_LMMR4_NBANKS 0x600,#define KA0302$M_SLOT8_LMMR4_ADDR 0xFFFE0000##define KA0302$M_SLOT8_LMMR5_EN 0x1$#define KA0302$M_SLOT8_LMMR5_INT 0x6$#define KA0302$M_SLOT8_LMMR5_IA 0x18%#define KA0302$M_SLOT8_LMMR5_AW 0x1E0)#define KA0302$M_SLOT8_LMMR5_NBANKS 0x600,#define KA0302$M_SLOT8_LMMR5_ADDR 0xFFFE0000 *##define KA0302$M_SLOT8_LMMR6_EN 0x1$#define KA0302$M_SLOT8_LMMR6_INT 0x6$#define KA0302$M_SLOT8_LMMR6_IA 0x18%#define KA0302$M_SLOT8_LMMR6_AW 0x1E0)#define KA0302$M_SLOT8_LMMR6_NBANKS 0x600,#define KA0302$M_SLOT8_LMMR6_ADDR 0xFFFE0000##define KA0302$M_SLOT8_LMMR7_EN 0x1$#define KA0302$M_SLOT8_LMMR7_INT 0x6$#define KA0302$M_SLOT8_LMMR7_IA 0x18%#define KA0302$M_SLOT8_LMMR7_AW 0x1E0)#define KA0302$M_SLOT8_LMMR7_NBANKS 0x600,#define KA0302$M_SLOT8_LMMR7_ADDR 0xFFFE0000+#define KA0302$M *_SLOT8_LBESR0_SYNDROME 0x7F+#define KA0302$M_SLOT8_LBESR1_SYNDROME 0x7F+#define KA0302$M_SLOT8_LBESR2_SYNDROME 0x7F+#define KA0302$M_SLOT8_LBESR3_SYNDROME 0x7F%#define KA0302$M_SLOT8_LBECR1_CA 0x7F'#define KA0302$M_SLOT8_LBECR1_CID 0x780(#define KA0302$M_SLOT8_LBECR1_RID 0x7800(#define KA0302$M_SLOT8_LBECR1_CNF 0x8000,#define KA0302$M_SLOT8_LBECR1_SHARED 0x10000+#define KA0302$M_SLOT8_LBECR1_DIRTY 0x20000,#define KA0302$M_SLOT8_LBECR1_DCYCLE 0xC0000$#define KA0302$M_LILID0_IDENT 0xFF*FF$#define KA0302$M_LILID1_IDENT 0xFFFF$#define KA0302$M_LILID2_IDENT 0xFFFF$#define KA0302$M_LILID3_IDENT 0xFFFF"#define KA0302$M_LCPUMASK_CPU0 0xF##define KA0302$M_LCPUMASK_CPU1 0xF0$#define KA0302$M_LCPUMASK_CPU2 0xF00%#define KA0302$M_LCPUMASK_CPU3 0xF000)#define KA0302$M_IPCNSE_MBX_HOSE0_TIP 0x1)#define KA0302$M_IPCNSE_MBX_HOSE1_TIP 0x2)#define KA0302$M_IPCNSE_MBX_HOSE2_TIP 0x4)#define KA0302$M_IPCNSE_MBX_HOSE3_TIP 0x8)#define KA0302$M_IPCNSE_UPHOSE0_OFLO 0x10)#define KA0302$M *_IPCNSE_UPHOSE1_OFLO 0x20)#define KA0302$M_IPCNSE_UPHOSE2_OFLO 0x40)#define KA0302$M_IPCNSE_UPHOSE3_OFLO 0x80-#define KA0302$M_IPCNSE_UPHOSE0_PKT_ERR 0x100-#define KA0302$M_IPCNSE_UPHOSE1_PKT_ERR 0x200-#define KA0302$M_IPCNSE_UPHOSE2_PKT_ERR 0x400-#define KA0302$M_IPCNSE_UPHOSE3_PKT_ERR 0x800.#define KA0302$M_IPCNSE_UPHOSE0_PAR_ERR 0x1000.#define KA0302$M_IPCNSE_UPHOSE1_PAR_ERR 0x2000.#define KA0302$M_IPCNSE_UPHOSE2_PAR_ERR 0x4000.#define KA0302$M_IPCNSE_UPHOSE3_PAR_ERR 0x8000)#defin *e KA0302$M_IPCNSE_UP_HIC_IE 0x10000+#define KA0302$M_IPCNSE_IPC_INT_ERR 0x20000+#define KA0302$M_IPCNSE_UP_VRTX_ERR 0x40000+#define KA0302$M_IPCNSE_DN_VRTX_ERR 0x80000.#define KA0302$M_IPCNSE_MULT_INTR_ERR 0x100000,#define KA0302$M_IPCNSE_INTR_NSES 0x80000000$#define KA0302$M_IPCVR_VECTOR 0xFFFF$#define KA0302$M_IPCMSR_ARB_HIGH 0x1##define KA0302$M_IPCMSR_ARB_CTL 0x6$#define KA0302$M_IPCHST_H0_ERROR 0x1$#define KA0302$M_IPCHST_H0_PWROK 0x2$#define KA0302$M_IPCHST_H0_CBLOK 0x4*#define *KA0302$M_IPCHST_H0_PWROK_TRANS 0x8%#define KA0302$M_IPCHST_H1_ERROR 0x10%#define KA0302$M_IPCHST_H1_PWROK 0x20%#define KA0302$M_IPCHST_H1_CBLOK 0x40+#define KA0302$M_IPCHST_H1_PWROK_TRANS 0x80&#define KA0302$M_IPCHST_H2_ERROR 0x100&#define KA0302$M_IPCHST_H2_PWROK 0x200&#define KA0302$M_IPCHST_H2_CBLOK 0x400,#define KA0302$M_IPCHST_H2_PWROK_TRANS 0x800'#define KA0302$M_IPCHST_H3_ERROR 0x1000'#define KA0302$M_IPCHST_H3_PWROK 0x2000'#define KA0302$M_IPCHST_H3_CBLOK 0x4000-#define KA03 *02$M_IPCHST_H3_PWROK_TRANS 0x8000,#define KA0302$M_IPCHST_HOSE0_RST 0x10000000,#define KA0302$M_IPCHST_HOSE1_RST 0x20000000,#define KA0302$M_IPCHST_HOSE2_RST 0x40000000,#define KA0302$M_IPCHST_HOSE3_RST 0x80000000%#define KA0302$K_IPCHST_BUS_PRESENT 6)#define KA0302$M_IPCDR_FRC_DN_ILL_CMD 0x1)#define KA0302$M_IPCDR_FRC_DN_SEQ_ERR 0x2%#define KA0302$M_IPCDR_FRC_DN_DPE 0xC(#define KA0302$M_IPCDR_DIS_LSB_CMD 0x400)#define KA0302$M_IPCDR_HIC_LPBCK_EN 0x800(#define KA0302$M_IPCDR_FRC_DAT_P*E 0x1000(#define KA0302$M_IPCDR_FRC_CMD_PE 0x2000(#define KA0302$M_IPCDR_FRC_CNFE 0x400000'#define KA0302$M_IPCDR_FRC_CAE 0x800000*#define KA0302$M_IPCDR_DIAG_ECC 0x7F000000-#define KA0302$M_IPCDR_DIAG_ECC_EN 0x80000000!#define KA0302$M_LIOINTR_CPU0 0xF"#define KA0302$M_LIOINTR_CPU1 0xF0##define KA0302$M_LIOINTR_CPU2 0xF00$#define KA0302$M_LIOINTR_CPU3 0xF000!#define KA0302$M_LIPINTR_CPU0 0xF"#define KA0302$M_LIPINTR_CPU1 0xF0##define KA0302$M_LIPINTR_CPU2 0xF00$#define KA0302$M_LIP*INTR_CPU3 0xF000"#define KA0302$M_WATCH_CSRA_RS 0xF##define KA0302$M_WATCH_CSRA_DV 0x70$#define KA0302$M_WATCH_CSRA_UIP 0x80##define KA0302$M_WATCH_CSRB_DSE 0x1%#define KA0302$M_WATCH_CSRB_24_12 0x2"#define KA0302$M_WATCH_CSRB_DM 0x4$#define KA0302$M_WATCH_CSRB_SQWE 0x8$#define KA0302$M_WATCH_CSRB_UIE 0x10$#define KA0302$M_WATCH_CSRB_AIE 0x20$#define KA0302$M_WATCH_CSRB_PIE 0x40$#define KA0302$M_WATCH_CSRB_SET 0x80##define KA0302$M_WATCH_CSRC_UF 0x10##define KA0302$M_WATCH_CSRC_AF 0x2*0##define KA0302$M_WATCH_CSRC_PF 0x40%#define KA0302$M_WATCH_CSRC_IRQF 0x80$#define KA0302$M_WATCH_CSRD_VRT 0x80##define KA0302$M_GBUS_WHAMI_NID 0x7##define KA0302$M_GBUS_WHAMI_MFG 0x8(#define KA0302$M_GBUS_WHAMI_LSB_BAD 0x10"#define KA0302$M_GBUS_LEDS_STP 0x1##define KA0302$M_GBUS_LEDS_CONW 0x2"#define KA0302$M_GBUS_LEDS_RUN 0x4##define KA0302$M_GBUS_LEDS_LED3 0x8$#define KA0302$M_GBUS_LEDS_LED4 0x10$#define KA0302$M_GBUS_LEDS_LED5 0x20$#define KA0302$M_GBUS_LEDS_LED6 0x40$#defin *e KA0302$M_GBUS_LEDS_LED7 0x80&#define KA0302$M_GBUS_PMASK_HALTEN 0x1'#define KA0302$M_GBUS_PMASK_SELTERM 0x6'#define KA0302$M_GBUS_INTR_UARTINT0 0x1'#define KA0302$M_GBUS_INTR_UARTINT1 0x2##define KA0302$M_GBUS_INTR_LSB0 0x4$#define KA0302$M_GBUS_INTR_LSB2 0x20"#define KA0302$M_GBUS_INTR_IP 0x40%#define KA0302$M_GBUS_INTR_INTIM 0x80%#define KA0302$M_GBUS_HALT_PHALT 0x40%#define KA0302$M_GBUS_HALT_NHALT 0x80%#define KA0302$M_GBUS_MISC_EXPSEL 0x3X#define KA0302$S_KA0302DEF 262404 * /* Old size name, synonym for KA0302$S_KA0302 */ typedef struct _ka0302 { __union {) unsigned int ka0302$l_slot0_ldev; __struct {4 unsigned ka0302$v_slot0_ldev_dtype : 16;3 unsigned ka0302$v_slot0_ldev_drev : 16;' } ka0302$r_slot0_ldev_bits;& } ka0302$r_slot0_ldev_overlay;' unsigned char ka0302$b_fill10 [60]; __union {) unsigned int ka0302$l_slot0_lber; __struct {/ unsigned ka030 *2$v_slot0_lber_e : 1;1 unsigned ka0302$v_slot0_lber_uce : 1;2 unsigned ka0302$v_slot0_lber_uce2 : 1;0 unsigned ka0302$v_slot0_lber_ce : 1;1 unsigned ka0302$v_slot0_lber_ce2 : 1;1 unsigned ka0302$v_slot0_lber_cpe : 1;2 unsigned ka0302$v_slot0_lber_cpe2 : 1;2 unsigned ka0302$v_slot0_lber_cdpe : 1;3 unsigned ka0302$v_slot0_lber_cdpe2 : 1;1 unsigned ka0302$v_slot0_lber_tde : 1;1 un *signed ka0302$v_slot0_lber_ste : 1;2 unsigned ka0302$v_slot0_lber_cnfe : 1;2 unsigned ka0302$v_slot0_lber_nxae : 1;1 unsigned ka0302$v_slot0_lber_cae : 1;1 unsigned ka0302$v_slot0_lber_she : 1;1 unsigned ka0302$v_slot0_lber_die : 1;2 unsigned ka0302$v_slot0_lber_dtce : 1;2 unsigned ka0302$v_slot0_lber_ctce : 1;2 unsigned ka0302$v_slot0_lber_nses : 1;4 unsigned ka0302$v_slot0_lber_fill1 : 13; *' } ka0302$r_slot0_lber_bits;& } ka0302$r_slot0_lber_overlay;' unsigned char ka0302$b_fill20 [60]; __union {) unsigned int ka0302$l_slot0_lcnr; __struct {2 unsigned ka0302$v_slot0_lcnr_ceen : 1;4 unsigned ka0302$v_slot0_lcnr_fill1 : 27;5 unsigned ka0302$v_slot0_lcnr_rststat : 1;3 unsigned ka0302$v_slot0_lcnr_nhalt : 1;2 unsigned ka0302$v_slot0_lcnr_nrst : 1;1 unsigned ka0302$v_ *slot0_lcnr_stf : 1;' } ka0302$r_slot0_lcnr_bits;& } ka0302$r_slot0_lcnr_overlay;' unsigned char ka0302$b_fill25 [60]; __union {( unsigned int ka0302$l_slot0_ibr; __struct {5 unsigned ka0302$v_slot0_ibr_rcv_sdat : 1;5 unsigned ka0302$v_slot0_ibr_xmt_sdat : 1;1 unsigned ka0302$v_slot0_ibr_sclk : 1;3 unsigned ka0302$v_slot0_ibr_fill1 : 29;& } ka0302$r_slot0_ibr_bits;% } ka0302$r_slo *t0_ibr_overlay;( unsigned char ka0302$b_fill30 [316]; __union {* unsigned int ka0302$l_slot0_lmmr0; __struct {1 unsigned ka0302$v_slot0_lmmr0_en : 1;2 unsigned ka0302$v_slot0_lmmr0_int : 2;1 unsigned ka0302$v_slot0_lmmr0_ia : 2;1 unsigned ka0302$v_slot0_lmmr0_aw : 4;5 unsigned ka0302$v_slot0_lmmr0_nbanks : 2;4 unsigned ka0302$v_slot0_lmmr0_fill1 : 6;4 unsigned ka0302$v_slot0_lmmr0_addr * : 15;( } ka0302$r_slot0_lmmr0_bits;' } ka0302$r_slot0_lmmr0_overlay;' unsigned char ka0302$b_fill40 [60]; __union {* unsigned int ka0302$l_slot0_lmmr1; __struct {1 unsigned ka0302$v_slot0_lmmr1_en : 1;2 unsigned ka0302$v_slot0_lmmr1_int : 2;1 unsigned ka0302$v_slot0_lmmr1_ia : 2;1 unsigned ka0302$v_slot0_lmmr1_aw : 4;5 unsigned ka0302$v_slot0_lmmr1_nbanks : 2;4 unsigned ka030 *2$v_slot0_lmmr1_fill1 : 6;4 unsigned ka0302$v_slot0_lmmr1_addr : 15;( } ka0302$r_slot0_lmmr1_bits;' } ka0302$r_slot0_lmmr1_overlay;' unsigned char ka0302$b_fill50 [60]; __union {* unsigned int ka0302$l_slot0_lmmr2; __struct {1 unsigned ka0302$v_slot0_lmmr2_en : 1;2 unsigned ka0302$v_slot0_lmmr2_int : 2;1 unsigned ka0302$v_slot0_lmmr2_ia : 2;1 unsigned ka0302$v_slot0_lmmr2_aw : 4;5 * unsigned ka0302$v_slot0_lmmr2_nbanks : 2;4 unsigned ka0302$v_slot0_lmmr2_fill1 : 6;4 unsigned ka0302$v_slot0_lmmr2_addr : 15;( } ka0302$r_slot0_lmmr2_bits;' } ka0302$r_slot0_lmmr2_overlay;' unsigned char ka0302$b_fill60 [60]; __union {* unsigned int ka0302$l_slot0_lmmr3; __struct {1 unsigned ka0302$v_slot0_lmmr3_en : 1;2 unsigned ka0302$v_slot0_lmmr3_int : 2;1 unsigned ka0302$v_slot0_lm *mr3_ia : 2;1 unsigned ka0302$v_slot0_lmmr3_aw : 4;5 unsigned ka0302$v_slot0_lmmr3_nbanks : 2;4 unsigned ka0302$v_slot0_lmmr3_fill1 : 6;4 unsigned ka0302$v_slot0_lmmr3_addr : 15;( } ka0302$r_slot0_lmmr3_bits;' } ka0302$r_slot0_lmmr3_overlay;' unsigned char ka0302$b_fill70 [60]; __union {* unsigned int ka0302$l_slot0_lmmr4; __struct {1 unsigned ka0302$v_slot0_lmmr4_en : 1;2 unsi *gned ka0302$v_slot0_lmmr4_int : 2;1 unsigned ka0302$v_slot0_lmmr4_ia : 2;1 unsigned ka0302$v_slot0_lmmr4_aw : 4;5 unsigned ka0302$v_slot0_lmmr4_nbanks : 2;4 unsigned ka0302$v_slot0_lmmr4_fill1 : 6;4 unsigned ka0302$v_slot0_lmmr4_addr : 15;( } ka0302$r_slot0_lmmr4_bits;' } ka0302$r_slot0_lmmr4_overlay;' unsigned char ka0302$b_fill80 [60]; __union {* unsigned int ka0302$l_slot0_lmmr5; __struct * {1 unsigned ka0302$v_slot0_lmmr5_en : 1;2 unsigned ka0302$v_slot0_lmmr5_int : 2;1 unsigned ka0302$v_slot0_lmmr5_ia : 2;1 unsigned ka0302$v_slot0_lmmr5_aw : 4;5 unsigned ka0302$v_slot0_lmmr5_nbanks : 2;4 unsigned ka0302$v_slot0_lmmr5_fill1 : 6;4 unsigned ka0302$v_slot0_lmmr5_addr : 15;( } ka0302$r_slot0_lmmr5_bits;' } ka0302$r_slot0_lmmr5_overlay;' unsigned char ka0302$b_fill90 [60]; * __union {* unsigned int ka0302$l_slot0_lmmr6; __struct {1 unsigned ka0302$v_slot0_lmmr6_en : 1;2 unsigned ka0302$v_slot0_lmmr6_int : 2;1 unsigned ka0302$v_slot0_lmmr6_ia : 2;1 unsigned ka0302$v_slot0_lmmr6_aw : 4;5 unsigned ka0302$v_slot0_lmmr6_nbanks : 2;4 unsigned ka0302$v_slot0_lmmr6_fill1 : 6;4 unsigned ka0302$v_slot0_lmmr6_addr : 15;( } ka0302$r_slot0_lmmr6_bits;' } ka *0302$r_slot0_lmmr6_overlay;( unsigned char ka0302$b_fill100 [60]; __union {* unsigned int ka0302$l_slot0_lmmr7; __struct {1 unsigned ka0302$v_slot0_lmmr7_en : 1;2 unsigned ka0302$v_slot0_lmmr7_int : 2;1 unsigned ka0302$v_slot0_lmmr7_ia : 2;1 unsigned ka0302$v_slot0_lmmr7_aw : 4;5 unsigned ka0302$v_slot0_lmmr7_nbanks : 2;4 unsigned ka0302$v_slot0_lmmr7_fill1 : 6;4 unsigned ka0302$v_slot*0_lmmr7_addr : 15;( } ka0302$r_slot0_lmmr7_bits;' } ka0302$r_slot0_lmmr7_overlay;) unsigned char ka0302$b_fill110 [572]; __union {+ unsigned int ka0302$l_slot0_lbesr0; __struct {8 unsigned ka0302$v_slot0_lbesr0_syndrome : 7;6 unsigned ka0302$v_slot0_lbesr0_fill1 : 25;) } ka0302$r_slot0_lbesr0_bits;( } ka0302$r_slot0_lbesr0_overlay;( unsigned char ka0302$b_fill120 [60]; __union {+ unsigned * int ka0302$l_slot0_lbesr1; __struct {8 unsigned ka0302$v_slot0_lbesr1_syndrome : 7;6 unsigned ka0302$v_slot0_lbesr1_fill1 : 25;) } ka0302$r_slot0_lbesr1_bits;( } ka0302$r_slot0_lbesr1_overlay;( unsigned char ka0302$b_fill130 [60]; __union {+ unsigned int ka0302$l_slot0_lbesr2; __struct {8 unsigned ka0302$v_slot0_lbesr2_syndrome : 7;6 unsigned ka0302$v_slot0_lbesr2_fill1 : 25;) } *ka0302$r_slot0_lbesr2_bits;( } ka0302$r_slot0_lbesr2_overlay;( unsigned char ka0302$b_fill140 [60]; __union {+ unsigned int ka0302$l_slot0_lbesr3; __struct {8 unsigned ka0302$v_slot0_lbesr3_syndrome : 7;6 unsigned ka0302$v_slot0_lbesr3_fill1 : 25;) } ka0302$r_slot0_lbesr3_bits;( } ka0302$r_slot0_lbesr3_overlay;( unsigned char ka0302$b_fill150 [60]; __union {+ unsigned int ka0302$l_slot0_lbecr0; * __struct {2 unsigned int ka0302$l_slot0_lbecr0_ca;) } ka0302$r_slot0_lbecr0_bits;( } ka0302$r_slot0_lbecr0_overlay;( unsigned char ka0302$b_fill160 [60]; __union {+ unsigned int ka0302$l_slot0_lbecr1; __struct {2 unsigned ka0302$v_slot0_lbecr1_ca : 7;3 unsigned ka0302$v_slot0_lbecr1_cid : 4;3 unsigned ka0302$v_slot0_lbecr1_rid : 4;3 unsigned ka0302$v_slot0_lbecr1_cnf : 1;6 * unsigned ka0302$v_slot0_lbecr1_shared : 1;5 unsigned ka0302$v_slot0_lbecr1_dirty : 1;6 unsigned ka0302$v_slot0_lbecr1_dcycle : 2;6 unsigned ka0302$v_slot0_lbecr1_fill1 : 12;) } ka0302$r_slot0_lbecr1_bits;( } ka0302$r_slot0_lbecr1_overlay;* unsigned char ka0302$b_fill170 [1212]; __union {* unsigned int ka0302$l_slot0_lmode; __struct {5 unsigned ka0302$v_slot0_lmode_fill1 : 32;( } ka0302$r_s*lot0_lmode_bits;' } ka0302$r_slot0_lmode_overlay;( unsigned char ka0302$b_fill180 [60]; __union {* unsigned int ka0302$l_slot0_lmerr; __struct {5 unsigned ka0302$v_slot0_lmerr_fill1 : 32;( } ka0302$r_slot0_lmerr_bits;' } ka0302$r_slot0_lmerr_overlay;( unsigned char ka0302$b_fill190 [60]; __union {* unsigned int ka0302$l_slot0_llock; __struct {5 unsigned ka0302$v_slot0_llock_fill1 : 32;( * } ka0302$r_slot0_llock_bits;' } ka0302$r_slot0_llock_overlay;( unsigned char ka0302$b_fill200 [60]; __union {* unsigned int ka0302$l_slot0_ledto; __struct {5 unsigned ka0302$v_slot0_ledto_fill1 : 32;( } ka0302$r_slot0_ledto_bits;' } ka0302$r_slot0_ledto_overlay;( unsigned char ka0302$b_fill210 [60]; __union {* unsigned int ka0302$l_slot0_ldiag; __struct {5 unsigned ka0302$v_slot0_*ldiag_fill1 : 32;( } ka0302$r_slot0_ldiag_bits;' } ka0302$r_slot0_ldiag_overlay;( unsigned char ka0302$b_fill220 [60]; __union {* unsigned int ka0302$l_slot0_ltaga; __struct {5 unsigned ka0302$v_slot0_ltaga_fill1 : 32;( } ka0302$r_slot0_ltaga_bits;' } ka0302$r_slot0_ltaga_overlay;( unsigned char ka0302$b_fill230 [60]; __union {* unsigned int ka0302$l_slot0_ltagw; __struct {5 un*signed ka0302$v_slot0_ltagw_fill1 : 32;( } ka0302$r_slot0_ltagw_bits;' } ka0302$r_slot0_ltagw_overlay;) unsigned char ka0302$b_fill240 [124]; __union {* unsigned int ka0302$l_slot0_lcon0; __struct {5 unsigned ka0302$v_slot0_lcon0_fill1 : 32;( } ka0302$r_slot0_lcon0_bits;' } ka0302$r_slot0_lcon0_overlay;( unsigned char ka0302$b_fill250 [60]; __union {* unsigned int ka0302$l_slot0_lcon1; __st*ruct {5 unsigned ka0302$v_slot0_lcon1_fill1 : 32;( } ka0302$r_slot0_lcon1_bits;' } ka0302$r_slot0_lcon1_overlay;) unsigned char ka0302$b_fill260 [188]; __union {* unsigned int ka0302$l_slot0_lperf; __struct {5 unsigned ka0302$v_slot0_lperf_fill1 : 32;( } ka0302$r_slot0_lperf_bits;' } ka0302$r_slot0_lperf_overlay;( unsigned char ka0302$b_fill270 [60]; __union {+ unsigned int ka0302$l_sl*ot0_lcntr0; __struct {6 unsigned ka0302$v_slot0_lcntr0_fill1 : 32;) } ka0302$r_slot0_lcntr0_bits;( } ka0302$r_slot0_lcntr0_overlay;( unsigned char ka0302$b_fill280 [60]; __union {+ unsigned int ka0302$l_slot0_lcntr1; __struct {6 unsigned ka0302$v_slot0_lcntr1_fill1 : 32;) } ka0302$r_slot0_lcntr1_bits;( } ka0302$r_slot0_lcntr1_overlay;( unsigned char ka0302$b_fill290 [60]; __union {. * unsigned int ka0302$l_slot0_lmissaddr; __struct {9 unsigned ka0302$v_slot0_lmissaddr_fill1 : 32;, } ka0302$r_slot0_lmissaddr_bits;+ } ka0302$r_slot0_lmissaddr_overlay;* unsigned char ka0302$b_fill300 [4156]; __union {( unsigned int ka0302$l_slot0_mcr; __struct {2 unsigned ka0302$v_slot0_mcr_dtype : 1;2 unsigned ka0302$v_slot0_mcr_fill1 : 1;1 unsigned ka0302$v_slot0_mcr_strn : 2;3 * unsigned ka0302$v_slot0_mcr_fill2 : 28;& } ka0302$r_slot0_mcr_bits;% } ka0302$r_slot0_mcr_overlay;( unsigned char ka0302$b_fill305 [60]; __union {( unsigned int ka0302$l_slot0_amr; __struct {. unsigned ka0302$v_slot0_amr_e : 1;1 unsigned ka0302$v_slot0_amr_intl : 2;/ unsigned ka0302$v_slot0_amr_ia : 2;/ unsigned ka0302$v_slot0_amr_aw : 4;3 unsigned ka0302$v_slot0_amr_nbanks : 2;2 * unsigned ka0302$v_slot0_amr_fill1 : 6;2 unsigned ka0302$v_slot0_amr_madr : 15;& } ka0302$r_slot0_amr_bits;% } ka0302$r_slot0_amr_overlay;( unsigned char ka0302$b_fill310 [60]; __union {* unsigned int ka0302$l_slot0_mstr0; __struct {5 unsigned ka0302$v_slot0_mstr0_fill1 : 32;( } ka0302$r_slot0_mstr0_bits;' } ka0302$r_slot0_mstr0_overlay;( unsigned char ka0302$b_fill320 [60]; __union {* * unsigned int ka0302$l_slot0_mstr1; __struct {5 unsigned ka0302$v_slot0_mstr1_fill1 : 32;( } ka0302$r_slot0_mstr1_bits;' } ka0302$r_slot0_mstr1_overlay;( unsigned char ka0302$b_fill330 [60]; __union {) unsigned int ka0302$l_slot0_fadr; __struct {4 unsigned ka0302$v_slot0_fadr_fill1 : 32;' } ka0302$r_slot0_fadr_bits;& } ka0302$r_slot0_fadr_overlay;( unsigned char ka0302$b_fill340 [60]; * __union {) unsigned int ka0302$l_slot0_mera; __struct {1 unsigned ka0302$v_slot0_mera_cer : 1;2 unsigned ka0302$v_slot0_mera_ucer : 1;2 unsigned ka0302$v_slot0_mera_mule : 1;2 unsigned ka0302$v_slot0_mera_aper : 1;2 unsigned ka0302$v_slot0_mera_cera : 1;2 unsigned ka0302$v_slot0_mera_cerb : 1;2 unsigned ka0302$v_slot0_mera_fstr : 3;3 unsigned ka0302$v_slot0_mera_bnker : 1;3 * unsigned ka0302$v_slot0_mera_ucera : 1;3 unsigned ka0302$v_slot0_mera_ucerb : 1;4 unsigned ka0302$v_slot0_mera_fill1 : 20;' } ka0302$r_slot0_mera_bits;& } ka0302$r_slot0_mera_overlay;( unsigned char ka0302$b_fill350 [60]; __union {+ unsigned int ka0302$l_slot0_msynda; __struct {4 unsigned ka0302$v_slot0_msynda_synd : 8;6 unsigned ka0302$v_slot0_msynda_fill1 : 24;) } ka0302$r_slot0_msy *nda_bits;( } ka0302$r_slot0_msynda_overlay;( unsigned char ka0302$b_fill360 [60]; __union {) unsigned int ka0302$l_slot0_mdra; __struct {2 unsigned ka0302$v_slot0_mdra_fcbs : 1;2 unsigned ka0302$v_slot0_mdra_drdc : 1;2 unsigned ka0302$v_slot0_mdra_dwdc : 1;2 unsigned ka0302$v_slot0_mdra_bpas : 1;2 unsigned ka0302$v_slot0_mdra_exst : 1;2 unsigned ka0302$v_slot0_mdra_stpm : 1;2 unsi *gned ka0302$v_slot0_mdra_mode : 1;2 unsigned ka0302$v_slot0_mdra_igsb : 1;2 unsigned ka0302$v_slot0_mdra_frpe : 1;2 unsigned ka0302$v_slot0_mdra_fcpe : 1;4 unsigned ka0302$v_slot0_mdra_fill1 : 17;2 unsigned ka0302$v_slot0_mdra_dcrd : 1;1 unsigned ka0302$v_slot0_mdra_rfr : 2;3 unsigned ka0302$v_slot0_mdra_brfsh : 1;3 unsigned ka0302$v_slot0_mdra_drfsh : 1;' } ka0302$r_slot0_mdra_bits;& * } ka0302$r_slot0_mdra_overlay;( unsigned char ka0302$b_fill370 [60]; __union {* unsigned int ka0302$l_slot0_mcbsa; __struct {2 unsigned ka0302$v_slot0_mcbsa_scb : 8;5 unsigned ka0302$v_slot0_mcbsa_fill1 : 24;( } ka0302$r_slot0_mcbsa_bits;' } ka0302$r_slot0_mcbsa_overlay;* unsigned char ka0302$b_fill380 [7996]; __union {) unsigned int ka0302$l_slot0_merb; __struct {1 unsigned ka0302$v_ *slot0_merb_cer : 1;2 unsigned ka0302$v_slot0_merb_ucer : 1;2 unsigned ka0302$v_slot0_merb_mule : 1;2 unsigned ka0302$v_slot0_merb_aper : 1;4 unsigned ka0302$v_slot0_merb_fill1 : 28;' } ka0302$r_slot0_merb_bits;& } ka0302$r_slot0_merb_overlay;( unsigned char ka0302$b_fill390 [60]; __union {+ unsigned int ka0302$l_slot0_msyndb; __struct {4 unsigned ka0302$v_slot0_msyndb_synd : 8;6 *unsigned ka0302$v_slot0_msyndb_fill1 : 24;) } ka0302$r_slot0_msyndb_bits;( } ka0302$r_slot0_msyndb_overlay;( unsigned char ka0302$b_fill400 [60]; __union {) unsigned int ka0302$l_slot0_mdrb; __struct {2 unsigned ka0302$v_slot0_mdrb_fcbs : 1;2 unsigned ka0302$v_slot0_mdrb_drdc : 1;2 unsigned ka0302$v_slot0_mdrb_dwdc : 1;2 unsigned ka0302$v_slot0_mdrb_bpas : 1;2 unsigned ka0302$v_slot0_mdrb_exs *t : 1;2 unsigned ka0302$v_slot0_mdrb_stpm : 1;2 unsigned ka0302$v_slot0_mdrb_mode : 1;2 unsigned ka0302$v_slot0_mdrb_igsb : 1;4 unsigned ka0302$v_slot0_mdrb_fill1 : 24;' } ka0302$r_slot0_mdrb_bits;& } ka0302$r_slot0_mdrb_overlay;( unsigned char ka0302$b_fill410 [60]; __union {* unsigned int ka0302$l_slot0_mcbsb; __struct {2 unsigned ka0302$v_slot0_mcbsb_scb : 8;5 unsigned ka0302$v_*slot0_mcbsb_fill1 : 24;( } ka0302$r_slot0_mcbsb_bits;' } ka0302$r_slot0_mcbsb_overlay;* unsigned char ka0302$b_fill420 [7676]; __union {) unsigned int ka0302$l_slot1_ldev; __struct {4 unsigned ka0302$v_slot1_ldev_dtype : 16;3 unsigned ka0302$v_slot1_ldev_drev : 16;' } ka0302$r_slot1_ldev_bits;& } ka0302$r_slot1_ldev_overlay;( unsigned char ka0302$b_fill430 [60]; __union {) unsigned int k *a0302$l_slot1_lber; __struct {/ unsigned ka0302$v_slot1_lber_e : 1;1 unsigned ka0302$v_slot1_lber_uce : 1;2 unsigned ka0302$v_slot1_lber_uce2 : 1;0 unsigned ka0302$v_slot1_lber_ce : 1;1 unsigned ka0302$v_slot1_lber_ce2 : 1;1 unsigned ka0302$v_slot1_lber_cpe : 1;2 unsigned ka0302$v_slot1_lber_cpe2 : 1;2 unsigned ka0302$v_slot1_lber_cdpe : 1;3 unsigned ka0302$v_slot1_lber_cdpe2 : 1 *;1 unsigned ka0302$v_slot1_lber_tde : 1;1 unsigned ka0302$v_slot1_lber_ste : 1;2 unsigned ka0302$v_slot1_lber_cnfe : 1;2 unsigned ka0302$v_slot1_lber_nxae : 1;1 unsigned ka0302$v_slot1_lber_cae : 1;1 unsigned ka0302$v_slot1_lber_she : 1;1 unsigned ka0302$v_slot1_lber_die : 1;2 unsigned ka0302$v_slot1_lber_dtce : 1;2 unsigned ka0302$v_slot1_lber_ctce : 1;2 unsigned ka0302$v_slot *1_lber_nses : 1;4 unsigned ka0302$v_slot1_lber_fill1 : 13;' } ka0302$r_slot1_lber_bits;& } ka0302$r_slot1_lber_overlay;( unsigned char ka0302$b_fill440 [60]; __union {) unsigned int ka0302$l_slot1_lcnr; __struct {2 unsigned ka0302$v_slot1_lcnr_ceen : 1;4 unsigned ka0302$v_slot1_lcnr_fill1 : 27;5 unsigned ka0302$v_slot1_lcnr_rststat : 1;3 unsigned ka0302$v_slot1_lcnr_nhalt : 1;2 *unsigned ka0302$v_slot1_lcnr_nrst : 1;1 unsigned ka0302$v_slot1_lcnr_stf : 1;' } ka0302$r_slot1_lcnr_bits;& } ka0302$r_slot1_lcnr_overlay;( unsigned char ka0302$b_fill445 [60]; __union {( unsigned int ka0302$l_slot1_ibr; __struct {5 unsigned ka0302$v_slot1_ibr_rcv_sdat : 1;5 unsigned ka0302$v_slot1_ibr_xmt_sdat : 1;1 unsigned ka0302$v_slot1_ibr_sclk : 1;3 unsigned ka0302$v_slot1_ibr_fill1 *: 29;& } ka0302$r_slot1_ibr_bits;% } ka0302$r_slot1_ibr_overlay;) unsigned char ka0302$b_fill450 [316]; __union {* unsigned int ka0302$l_slot1_lmmr0; __struct {1 unsigned ka0302$v_slot1_lmmr0_en : 1;2 unsigned ka0302$v_slot1_lmmr0_int : 2;1 unsigned ka0302$v_slot1_lmmr0_ia : 2;1 unsigned ka0302$v_slot1_lmmr0_aw : 4;5 unsigned ka0302$v_slot1_lmmr0_nbanks : 2;4 unsigned ka0302$ *v_slot1_lmmr0_fill1 : 6;4 unsigned ka0302$v_slot1_lmmr0_addr : 15;( } ka0302$r_slot1_lmmr0_bits;' } ka0302$r_slot1_lmmr0_overlay;( unsigned char ka0302$b_fill460 [60]; __union {* unsigned int ka0302$l_slot1_lmmr1; __struct {1 unsigned ka0302$v_slot1_lmmr1_en : 1;2 unsigned ka0302$v_slot1_lmmr1_int : 2;1 unsigned ka0302$v_slot1_lmmr1_ia : 2;1 unsigned ka0302$v_slot1_lmmr1_aw : 4;5 * unsigned ka0302$v_slot1_lmmr1_nbanks : 2;4 unsigned ka0302$v_slot1_lmmr1_fill1 : 6;4 unsigned ka0302$v_slot1_lmmr1_addr : 15;( } ka0302$r_slot1_lmmr1_bits;' } ka0302$r_slot1_lmmr1_overlay;( unsigned char ka0302$b_fill470 [60]; __union {* unsigned int ka0302$l_slot1_lmmr2; __struct {1 unsigned ka0302$v_slot1_lmmr2_en : 1;2 unsigned ka0302$v_slot1_lmmr2_int : 2;1 unsigned ka0302$v_slot1_lmmr *2_ia : 2;1 unsigned ka0302$v_slot1_lmmr2_aw : 4;5 unsigned ka0302$v_slot1_lmmr2_nbanks : 2;4 unsigned ka0302$v_slot1_lmmr2_fill1 : 6;4 unsigned ka0302$v_slot1_lmmr2_addr : 15;( } ka0302$r_slot1_lmmr2_bits;' } ka0302$r_slot1_lmmr2_overlay;( unsigned char ka0302$b_fill480 [60]; __union {* unsigned int ka0302$l_slot1_lmmr3; __struct {1 unsigned ka0302$v_slot1_lmmr3_en : 1;2 unsign *ed ka0302$v_slot1_lmmr3_int : 2;1 unsigned ka0302$v_slot1_lmmr3_ia : 2;1 unsigned ka0302$v_slot1_lmmr3_aw : 4;5 unsigned ka0302$v_slot1_lmmr3_nbanks : 2;4 unsigned ka0302$v_slot1_lmmr3_fill1 : 6;4 unsigned ka0302$v_slot1_lmmr3_addr : 15;( } ka0302$r_slot1_lmmr3_bits;' } ka0302$r_slot1_lmmr3_overlay;( unsigned char ka0302$b_fill490 [60]; __union {* unsigned int ka0302$l_slot1_lmmr4; __struct *{1 unsigned ka0302$v_slot1_lmmr4_en : 1;2 unsigned ka0302$v_slot1_lmmr4_int : 2;1 unsigned ka0302$v_slot1_lmmr4_ia : 2;1 unsigned ka0302$v_slot1_lmmr4_aw : 4;5 unsigned ka0302$v_slot1_lmmr4_nbanks : 2;4 unsigned ka0302$v_slot1_lmmr4_fill1 : 6;4 unsigned ka0302$v_slot1_lmmr4_addr : 15;( } ka0302$r_slot1_lmmr4_bits;' } ka0302$r_slot1_lmmr4_overlay;( unsigned char ka0302$b_fill500 [60]; *__union {* unsigned int ka0302$l_slot1_lmmr5; __struct {1 unsigned ka0302$v_slot1_lmmr5_en : 1;2 unsigned ka0302$v_slot1_lmmr5_int : 2;1 unsigned ka0302$v_slot1_lmmr5_ia : 2;1 unsigned ka0302$v_slot1_lmmr5_aw : 4;5 unsigned ka0302$v_slot1_lmmr5_nbanks : 2;4 unsigned ka0302$v_slot1_lmmr5_fill1 : 6;4 unsigned ka0302$v_slot1_lmmr5_addr : 15;( } ka0302$r_slot1_lmmr5_bits;' } ka03 *02$r_slot1_lmmr5_overlay;( unsigned char ka0302$b_fill510 [60]; __union {* unsigned int ka0302$l_slot1_lmmr6; __struct {1 unsigned ka0302$v_slot1_lmmr6_en : 1;2 unsigned ka0302$v_slot1_lmmr6_int : 2;1 unsigned ka0302$v_slot1_lmmr6_ia : 2;1 unsigned ka0302$v_slot1_lmmr6_aw : 4;5 unsigned ka0302$v_slot1_lmmr6_nbanks : 2;4 unsigned ka0302$v_slot1_lmmr6_fill1 : 6;4 unsigned ka0302$v_slot1_ *lmmr6_addr : 15;( } ka0302$r_slot1_lmmr6_bits;' } ka0302$r_slot1_lmmr6_overlay;( unsigned char ka0302$b_fill520 [60]; __union {* unsigned int ka0302$l_slot1_lmmr7; __struct {1 unsigned ka0302$v_slot1_lmmr7_en : 1;2 unsigned ka0302$v_slot1_lmmr7_int : 2;1 unsigned ka0302$v_slot1_lmmr7_ia : 2;1 unsigned ka0302$v_slot1_lmmr7_aw : 4;5 unsigned ka0302$v_slot1_lmmr7_nbanks : 2;4 unsi *gned ka0302$v_slot1_lmmr7_fill1 : 6;4 unsigned ka0302$v_slot1_lmmr7_addr : 15;( } ka0302$r_slot1_lmmr7_bits;' } ka0302$r_slot1_lmmr7_overlay;) unsigned char ka0302$b_fill530 [572]; __union {+ unsigned int ka0302$l_slot1_lbesr0; __struct {8 unsigned ka0302$v_slot1_lbesr0_syndrome : 7;6 unsigned ka0302$v_slot1_lbesr0_fill1 : 25;) } ka0302$r_slot1_lbesr0_bits;( } ka0302$r_slot1_lbesr0_overlay;( * unsigned char ka0302$b_fill540 [60]; __union {+ unsigned int ka0302$l_slot1_lbesr1; __struct {8 unsigned ka0302$v_slot1_lbesr1_syndrome : 7;6 unsigned ka0302$v_slot1_lbesr1_fill1 : 25;) } ka0302$r_slot1_lbesr1_bits;( } ka0302$r_slot1_lbesr1_overlay;( unsigned char ka0302$b_fill550 [60]; __union {+ unsigned int ka0302$l_slot1_lbesr2; __struct {8 unsigned ka0302$v_slot1_lbesr2_syndrome : 7; *6 unsigned ka0302$v_slot1_lbesr2_fill1 : 25;) } ka0302$r_slot1_lbesr2_bits;( } ka0302$r_slot1_lbesr2_overlay;( unsigned char ka0302$b_fill560 [60]; __union {+ unsigned int ka0302$l_slot1_lbesr3; __struct {8 unsigned ka0302$v_slot1_lbesr3_syndrome : 7;6 unsigned ka0302$v_slot1_lbesr3_fill1 : 25;) } ka0302$r_slot1_lbesr3_bits;( } ka0302$r_slot1_lbesr3_overlay;( unsigned char ka0302$b_fill570 [*60]; __union {+ unsigned int ka0302$l_slot1_lbecr0; __struct {2 unsigned int ka0302$l_slot1_lbecr0_ca;) } ka0302$r_slot1_lbecr0_bits;( } ka0302$r_slot1_lbecr0_overlay;( unsigned char ka0302$b_fill580 [60]; __union {+ unsigned int ka0302$l_slot1_lbecr1; __struct {2 unsigned ka0302$v_slot1_lbecr1_ca : 7;3 unsigned ka0302$v_slot1_lbecr1_cid : 4;3 unsigned ka0302$v_slot1_lbecr1_rid * : 4;3 unsigned ka0302$v_slot1_lbecr1_cnf : 1;6 unsigned ka0302$v_slot1_lbecr1_shared : 1;5 unsigned ka0302$v_slot1_lbecr1_dirty : 1;6 unsigned ka0302$v_slot1_lbecr1_dcycle : 2;6 unsigned ka0302$v_slot1_lbecr1_fill1 : 12;) } ka0302$r_slot1_lbecr1_bits;( } ka0302$r_slot1_lbecr1_overlay;* unsigned char ka0302$b_fill590 [1212]; __union {* unsigned int ka0302$l_slot1_lmode; __struct {5 * unsigned ka0302$v_slot1_lmode_fill1 : 32;( } ka0302$r_slot1_lmode_bits;' } ka0302$r_slot1_lmode_overlay;( unsigned char ka0302$b_fill600 [60]; __union {* unsigned int ka0302$l_slot1_lmerr; __struct {5 unsigned ka0302$v_slot1_lmerr_fill1 : 32;( } ka0302$r_slot1_lmerr_bits;' } ka0302$r_slot1_lmerr_overlay;( unsigned char ka0302$b_fill610 [60]; __union {* unsigned int ka0302$l_slot1_llock; *__struct {5 unsigned ka0302$v_slot1_llock_fill1 : 32;( } ka0302$r_slot1_llock_bits;' } ka0302$r_slot1_llock_overlay;( unsigned char ka0302$b_fill620 [60]; __union {* unsigned int ka0302$l_slot1_ledto; __struct {5 unsigned ka0302$v_slot1_ledto_fill1 : 32;( } ka0302$r_slot1_ledto_bits;' } ka0302$r_slot1_ledto_overlay;( unsigned char ka0302$b_fill630 [60]; __union {* unsigned int ka0302$l_*slot1_ldiag; __struct {5 unsigned ka0302$v_slot1_ldiag_fill1 : 32;( } ka0302$r_slot1_ldiag_bits;' } ka0302$r_slot1_ldiag_overlay;( unsigned char ka0302$b_fill640 [60]; __union {* unsigned int ka0302$l_slot1_ltaga; __struct {5 unsigned ka0302$v_slot1_ltaga_fill1 : 32;( } ka0302$r_slot1_ltaga_bits;' } ka0302$r_slot1_ltaga_overlay;( unsigned char ka0302$b_fill650 [60]; __union {* *unsigned int ka0302$l_slot1_ltagw; __struct {5 unsigned ka0302$v_slot1_ltagw_fill1 : 32;( } ka0302$r_slot1_ltagw_bits;' } ka0302$r_slot1_ltagw_overlay;) unsigned char ka0302$b_fill660 [124]; __union {* unsigned int ka0302$l_slot1_lcon0; __struct {5 unsigned ka0302$v_slot1_lcon0_fill1 : 32;( } ka0302$r_slot1_lcon0_bits;' } ka0302$r_slot1_lcon0_overlay;( unsigned char ka0302$b_fill670 [60];* __union {* unsigned int ka0302$l_slot1_lcon1; __struct {5 unsigned ka0302$v_slot1_lcon1_fill1 : 32;( } ka0302$r_slot1_lcon1_bits;' } ka0302$r_slot1_lcon1_overlay;) unsigned char ka0302$b_fill680 [188]; __union {* unsigned int ka0302$l_slot1_lperf; __struct {5 unsigned ka0302$v_slot1_lperf_fill1 : 32;( } ka0302$r_slot1_lperf_bits;' } ka0302$r_slot1_lperf_overlay;( unsigned char *ka0302$b_fill690 [60]; __union {+ unsigned int ka0302$l_slot1_lcntr0; __struct {6 unsigned ka0302$v_slot1_lcntr0_fill1 : 32;) } ka0302$r_slot1_lcntr0_bits;( } ka0302$r_slot1_lcntr0_overlay;( unsigned char ka0302$b_fill700 [60]; __union {+ unsigned int ka0302$l_slot1_lcntr1; __struct {6 unsigned ka0302$v_slot1_lcntr1_fill1 : 32;) } ka0302$r_slot1_lcntr1_bits;( } ka0302$r_slot1_lcntr*1_overlay;( unsigned char ka0302$b_fill705 [60]; __union {. unsigned int ka0302$l_slot1_lmissaddr; __struct {9 unsigned ka0302$v_slot1_lmissaddr_fill1 : 32;, } ka0302$r_slot1_lmissaddr_bits;+ } ka0302$r_slot1_lmissaddr_overlay;* unsigned char ka0302$b_fill706 [4156]; __union {( unsigned int ka0302$l_slot1_mcr; __struct {3 unsigned ka0302$v_slot1_mcr_fill1 : 32;& } ka0302$r_slot1_mcr_bit*s;% } ka0302$r_slot1_mcr_overlay;( unsigned char ka0302$b_fill710 [60]; __union {( unsigned int ka0302$l_slot1_amr; __struct {3 unsigned ka0302$v_slot1_amr_fill1 : 32;& } ka0302$r_slot1_amr_bits;% } ka0302$r_slot1_amr_overlay;( unsigned char ka0302$b_fill720 [60]; __union {* unsigned int ka0302$l_slot1_mstr0; __struct {5 unsigned ka0302$v_slot1_mstr0_fill1 : 32;( } ka0302$r_slo*t1_mstr0_bits;' } ka0302$r_slot1_mstr0_overlay;( unsigned char ka0302$b_fill730 [60]; __union {* unsigned int ka0302$l_slot1_mstr1; __struct {5 unsigned ka0302$v_slot1_mstr1_fill1 : 32;( } ka0302$r_slot1_mstr1_bits;' } ka0302$r_slot1_mstr1_overlay;( unsigned char ka0302$b_fill740 [60]; __union {) unsigned int ka0302$l_slot1_fadr; __struct {4 unsigned ka0302$v_slot1_fadr_fill1 : 32;' * } ka0302$r_slot1_fadr_bits;& } ka0302$r_slot1_fadr_overlay;( unsigned char ka0302$b_fill750 [60]; __union {) unsigned int ka0302$l_slot1_mera; __struct {4 unsigned ka0302$v_slot1_mera_fill1 : 32;' } ka0302$r_slot1_mera_bits;& } ka0302$r_slot1_mera_overlay;( unsigned char ka0302$b_fill760 [60]; __union {+ unsigned int ka0302$l_slot1_msynda; __struct {6 unsigned ka0302$v_slot1_msynda_f*ill1 : 32;) } ka0302$r_slot1_msynda_bits;( } ka0302$r_slot1_msynda_overlay;( unsigned char ka0302$b_fill770 [60]; __union {) unsigned int ka0302$l_slot1_mdra; __struct {4 unsigned ka0302$v_slot1_mdra_fill1 : 32;' } ka0302$r_slot1_mdra_bits;& } ka0302$r_slot1_mdra_overlay;( unsigned char ka0302$b_fill780 [60]; __union {* unsigned int ka0302$l_slot1_mcbsa; __struct {5 unsigned ka0*302$v_slot1_mcbsa_fill1 : 32;( } ka0302$r_slot1_mcbsa_bits;' } ka0302$r_slot1_mcbsa_overlay;* unsigned char ka0302$b_fill790 [7996]; __union {) unsigned int ka0302$l_slot1_merb; __struct {4 unsigned ka0302$v_slot1_merb_fill1 : 32;' } ka0302$r_slot1_merb_bits;& } ka0302$r_slot1_merb_overlay;( unsigned char ka0302$b_fill800 [60]; __union {+ unsigned int ka0302$l_slot1_msyndb; __struct {6 * unsigned ka0302$v_slot1_msyndb_fill1 : 32;) } ka0302$r_slot1_msyndb_bits;( } ka0302$r_slot1_msyndb_overlay;( unsigned char ka0302$b_fill810 [60]; __union {) unsigned int ka0302$l_slot1_mdrb; __struct {4 unsigned ka0302$v_slot1_mdrb_fill1 : 32;' } ka0302$r_slot1_mdrb_bits;& } ka0302$r_slot1_mdrb_overlay;( unsigned char ka0302$b_fill820 [60]; __union {* unsigned int ka0302$l_slot1_mcbsb; * __struct {5 unsigned ka0302$v_slot1_mcbsb_fill1 : 32;( } ka0302$r_slot1_mcbsb_bits;' } ka0302$r_slot1_mcbsb_overlay;* unsigned char ka0302$b_fill830 [7676]; __union {) unsigned int ka0302$l_slot2_ldev; __struct {4 unsigned ka0302$v_slot2_ldev_dtype : 16;3 unsigned ka0302$v_slot2_ldev_drev : 16;' } ka0302$r_slot2_ldev_bits;& } ka0302$r_slot2_ldev_overlay;( unsigned char ka0302$b_fill8 *40 [60]; __union {) unsigned int ka0302$l_slot2_lber; __struct {/ unsigned ka0302$v_slot2_lber_e : 1;1 unsigned ka0302$v_slot2_lber_uce : 1;2 unsigned ka0302$v_slot2_lber_uce2 : 1;0 unsigned ka0302$v_slot2_lber_ce : 1;1 unsigned ka0302$v_slot2_lber_ce2 : 1;1 unsigned ka0302$v_slot2_lber_cpe : 1;2 unsigned ka0302$v_slot2_lber_cpe2 : 1;2 unsigned ka0302$v_slot2_lber_cdpe : 1;3 * unsigned ka0302$v_slot2_lber_cdpe2 : 1;1 unsigned ka0302$v_slot2_lber_tde : 1;1 unsigned ka0302$v_slot2_lber_ste : 1;2 unsigned ka0302$v_slot2_lber_cnfe : 1;2 unsigned ka0302$v_slot2_lber_nxae : 1;1 unsigned ka0302$v_slot2_lber_cae : 1;1 unsigned ka0302$v_slot2_lber_she : 1;1 unsigned ka0302$v_slot2_lber_die : 1;2 unsigned ka0302$v_slot2_lber_dtce : 1;2 unsigned ka0302$v_slot2_lb *er_ctce : 1;2 unsigned ka0302$v_slot2_lber_nses : 1;4 unsigned ka0302$v_slot2_lber_fill1 : 13;' } ka0302$r_slot2_lber_bits;& } ka0302$r_slot2_lber_overlay;( unsigned char ka0302$b_fill850 [60]; __union {) unsigned int ka0302$l_slot2_lcnr; __struct {2 unsigned ka0302$v_slot2_lcnr_ceen : 1;4 unsigned ka0302$v_slot2_lcnr_fill1 : 27;5 unsigned ka0302$v_slot2_lcnr_rststat : 1;3 unsign *ed ka0302$v_slot2_lcnr_nhalt : 1;2 unsigned ka0302$v_slot2_lcnr_nrst : 1;1 unsigned ka0302$v_slot2_lcnr_stf : 1;' } ka0302$r_slot2_lcnr_bits;& } ka0302$r_slot2_lcnr_overlay;( unsigned char ka0302$b_fill855 [60]; __union {( unsigned int ka0302$l_slot2_ibr; __struct {5 unsigned ka0302$v_slot2_ibr_rcv_sdat : 1;5 unsigned ka0302$v_slot2_ibr_xmt_sdat : 1;1 unsigned ka0302$v_slot2_ibr_sclk : 1; *3 unsigned ka0302$v_slot2_ibr_fill1 : 29;& } ka0302$r_slot2_ibr_bits;% } ka0302$r_slot2_ibr_overlay;) unsigned char ka0302$b_fill860 [316]; __union {* unsigned int ka0302$l_slot2_lmmr0; __struct {1 unsigned ka0302$v_slot2_lmmr0_en : 1;2 unsigned ka0302$v_slot2_lmmr0_int : 2;1 unsigned ka0302$v_slot2_lmmr0_ia : 2;1 unsigned ka0302$v_slot2_lmmr0_aw : 4;5 unsigned ka0302$v_slot2_ *lmmr0_nbanks : 2;4 unsigned ka0302$v_slot2_lmmr0_fill1 : 6;4 unsigned ka0302$v_slot2_lmmr0_addr : 15;( } ka0302$r_slot2_lmmr0_bits;' } ka0302$r_slot2_lmmr0_overlay;( unsigned char ka0302$b_fill870 [60]; __union {* unsigned int ka0302$l_slot2_lmmr1; __struct {1 unsigned ka0302$v_slot2_lmmr1_en : 1;2 unsigned ka0302$v_slot2_lmmr1_int : 2;1 unsigned ka0302$v_slot2_lmmr1_ia : 2;1 un *signed ka0302$v_slot2_lmmr1_aw : 4;5 unsigned ka0302$v_slot2_lmmr1_nbanks : 2;4 unsigned ka0302$v_slot2_lmmr1_fill1 : 6;4 unsigned ka0302$v_slot2_lmmr1_addr : 15;( } ka0302$r_slot2_lmmr1_bits;' } ka0302$r_slot2_lmmr1_overlay;( unsigned char ka0302$b_fill880 [60]; __union {* unsigned int ka0302$l_slot2_lmmr2; __struct {1 unsigned ka0302$v_slot2_lmmr2_en : 1;2 unsigned ka0302$v_slot2_lmmr2_in *t : 2;1 unsigned ka0302$v_slot2_lmmr2_ia : 2;1 unsigned ka0302$v_slot2_lmmr2_aw : 4;5 unsigned ka0302$v_slot2_lmmr2_nbanks : 2;4 unsigned ka0302$v_slot2_lmmr2_fill1 : 6;4 unsigned ka0302$v_slot2_lmmr2_addr : 15;( } ka0302$r_slot2_lmmr2_bits;' } ka0302$r_slot2_lmmr2_overlay;( unsigned char ka0302$b_fill890 [60]; __union {* unsigned int ka0302$l_slot2_lmmr3; __struct {1 unsigned k *a0302$v_slot2_lmmr3_en : 1;2 unsigned ka0302$v_slot2_lmmr3_int : 2;1 unsigned ka0302$v_slot2_lmmr3_ia : 2;1 unsigned ka0302$v_slot2_lmmr3_aw : 4;5 unsigned ka0302$v_slot2_lmmr3_nbanks : 2;4 unsigned ka0302$v_slot2_lmmr3_fill1 : 6;4 unsigned ka0302$v_slot2_lmmr3_addr : 15;( } ka0302$r_slot2_lmmr3_bits;' } ka0302$r_slot2_lmmr3_overlay;( unsigned char ka0302$b_fill900 [60]; __union {* unsign *ed int ka0302$l_slot2_lmmr4; __struct {1 unsigned ka0302$v_slot2_lmmr4_en : 1;2 unsigned ka0302$v_slot2_lmmr4_int : 2;1 unsigned ka0302$v_slot2_lmmr4_ia : 2;1 unsigned ka0302$v_slot2_lmmr4_aw : 4;5 unsigned ka0302$v_slot2_lmmr4_nbanks : 2;4 unsigned ka0302$v_slot2_lmmr4_fill1 : 6;4 unsigned ka0302$v_slot2_lmmr4_addr : 15;( } ka0302$r_slot2_lmmr4_bits;' } ka0302$r_slot2_lmmr4_overlay; *( unsigned char ka0302$b_fill910 [60]; __union {* unsigned int ka0302$l_slot2_lmmr5; __struct {1 unsigned ka0302$v_slot2_lmmr5_en : 1;2 unsigned ka0302$v_slot2_lmmr5_int : 2;1 unsigned ka0302$v_slot2_lmmr5_ia : 2;1 unsigned ka0302$v_slot2_lmmr5_aw : 4;5 unsigned ka0302$v_slot2_lmmr5_nbanks : 2;4 unsigned ka0302$v_slot2_lmmr5_fill1 : 6;4 unsigned ka0302$v_slot2_lmmr5_addr : 15;( * } ka0302$r_slot2_lmmr5_bits;' } ka0302$r_slot2_lmmr5_overlay;( unsigned char ka0302$b_fill920 [60]; __union {* unsigned int ka0302$l_slot2_lmmr6; __struct {1 unsigned ka0302$v_slot2_lmmr6_en : 1;2 unsigned ka0302$v_slot2_lmmr6_int : 2;1 unsigned ka0302$v_slot2_lmmr6_ia : 2;1 unsigned ka0302$v_slot2_lmmr6_aw : 4;5 unsigned ka0302$v_slot2_lmmr6_nbanks : 2;4 unsigned ka0302$v_slot2_lmmr6_ *fill1 : 6;4 unsigned ka0302$v_slot2_lmmr6_addr : 15;( } ka0302$r_slot2_lmmr6_bits;' } ka0302$r_slot2_lmmr6_overlay;( unsigned char ka0302$b_fill930 [60]; __union {* unsigned int ka0302$l_slot2_lmmr7; __struct {1 unsigned ka0302$v_slot2_lmmr7_en : 1;2 unsigned ka0302$v_slot2_lmmr7_int : 2;1 unsigned ka0302$v_slot2_lmmr7_ia : 2;1 unsigned ka0302$v_slot2_lmmr7_aw : 4;5 unsigned ka0 *302$v_slot2_lmmr7_nbanks : 2;4 unsigned ka0302$v_slot2_lmmr7_fill1 : 6;4 unsigned ka0302$v_slot2_lmmr7_addr : 15;( } ka0302$r_slot2_lmmr7_bits;' } ka0302$r_slot2_lmmr7_overlay;) unsigned char ka0302$b_fill940 [572]; __union {+ unsigned int ka0302$l_slot2_lbesr0; __struct {8 unsigned ka0302$v_slot2_lbesr0_syndrome : 7;6 unsigned ka0302$v_slot2_lbesr0_fill1 : 25;) } ka0302$r_slot2_lbesr0_bits*;( } ka0302$r_slot2_lbesr0_overlay;( unsigned char ka0302$b_fill950 [60]; __union {+ unsigned int ka0302$l_slot2_lbesr1; __struct {8 unsigned ka0302$v_slot2_lbesr1_syndrome : 7;6 unsigned ka0302$v_slot2_lbesr1_fill1 : 25;) } ka0302$r_slot2_lbesr1_bits;( } ka0302$r_slot2_lbesr1_overlay;( unsigned char ka0302$b_fill960 [60]; __union {+ unsigned int ka0302$l_slot2_lbesr2; __struct {8 * unsigned ka0302$v_slot2_lbesr2_syndrome : 7;6 unsigned ka0302$v_slot2_lbesr2_fill1 : 25;) } ka0302$r_slot2_lbesr2_bits;( } ka0302$r_slot2_lbesr2_overlay;( unsigned char ka0302$b_fill970 [60]; __union {+ unsigned int ka0302$l_slot2_lbesr3; __struct {8 unsigned ka0302$v_slot2_lbesr3_syndrome : 7;6 unsigned ka0302$v_slot2_lbesr3_fill1 : 25;) } ka0302$r_slot2_lbesr3_bits;( } ka0302$r_slot2_lbesr*3_overlay;( unsigned char ka0302$b_fill980 [60]; __union {+ unsigned int ka0302$l_slot2_lbecr0; __struct {2 unsigned int ka0302$l_slot2_lbecr0_ca;) } ka0302$r_slot2_lbecr0_bits;( } ka0302$r_slot2_lbecr0_overlay;( unsigned char ka0302$b_fill990 [60]; __union {+ unsigned int ka0302$l_slot2_lbecr1; __struct {2 unsigned ka0302$v_slot2_lbecr1_ca : 7;3 unsigned ka0302$v_slot2_lbecr1_cid : 4; *3 unsigned ka0302$v_slot2_lbecr1_rid : 4;3 unsigned ka0302$v_slot2_lbecr1_cnf : 1;6 unsigned ka0302$v_slot2_lbecr1_shared : 1;5 unsigned ka0302$v_slot2_lbecr1_dirty : 1;6 unsigned ka0302$v_slot2_lbecr1_dcycle : 2;6 unsigned ka0302$v_slot2_lbecr1_fill1 : 12;) } ka0302$r_slot2_lbecr1_bits;( } ka0302$r_slot2_lbecr1_overlay;+ unsigned char ka0302$b_fill1000 [1212]; __union {* unsigned int ka0*302$l_slot2_lmode; __struct {5 unsigned ka0302$v_slot2_lmode_fill1 : 32;( } ka0302$r_slot2_lmode_bits;' } ka0302$r_slot2_lmode_overlay;) unsigned char ka0302$b_fill1010 [60]; __union {* unsigned int ka0302$l_slot2_lmerr; __struct {5 unsigned ka0302$v_slot2_lmerr_fill1 : 32;( } ka0302$r_slot2_lmerr_bits;' } ka0302$r_slot2_lmerr_overlay;) unsigned char ka0302$b_fill1020 [60]; __union { ** unsigned int ka0302$l_slot2_llock; __struct {5 unsigned ka0302$v_slot2_llock_fill1 : 32;( } ka0302$r_slot2_llock_bits;' } ka0302$r_slot2_llock_overlay;) unsigned char ka0302$b_fill1030 [60]; __union {* unsigned int ka0302$l_slot2_ledto; __struct {5 unsigned ka0302$v_slot2_ledto_fill1 : 32;( } ka0302$r_slot2_ledto_bits;' } ka0302$r_slot2_ledto_overlay;) unsigned char ka0302$b_fill1*040 [60]; __union {* unsigned int ka0302$l_slot2_ldiag; __struct {5 unsigned ka0302$v_slot2_ldiag_fill1 : 32;( } ka0302$r_slot2_ldiag_bits;' } ka0302$r_slot2_ldiag_overlay;) unsigned char ka0302$b_fill1050 [60]; __union {* unsigned int ka0302$l_slot2_ltaga; __struct {5 unsigned ka0302$v_slot2_ltaga_fill1 : 32;( } ka0302$r_slot2_ltaga_bits;' } ka0302$r_slot2_ltaga_overlay;) un*signed char ka0302$b_fill1060 [60]; __union {* unsigned int ka0302$l_slot2_ltagw; __struct {5 unsigned ka0302$v_slot2_ltagw_fill1 : 32;( } ka0302$r_slot2_ltagw_bits;' } ka0302$r_slot2_ltagw_overlay;* unsigned char ka0302$b_fill1070 [124]; __union {* unsigned int ka0302$l_slot2_lcon0; __struct {5 unsigned ka0302$v_slot2_lcon0_fill1 : 32;( } ka0302$r_slot2_lcon0_bits;' } ka0302$r_slo*t2_lcon0_overlay;) unsigned char ka0302$b_fill1080 [60]; __union {* unsigned int ka0302$l_slot2_lcon1; __struct {5 unsigned ka0302$v_slot2_lcon1_fill1 : 32;( } ka0302$r_slot2_lcon1_bits;' } ka0302$r_slot2_lcon1_overlay;* unsigned char ka0302$b_fill1090 [188]; __union {* unsigned int ka0302$l_slot2_lperf; __struct {5 unsigned ka0302$v_slot2_lperf_fill1 : 32;( } ka0302$r_slot2_lperf_bit*s;' } ka0302$r_slot2_lperf_overlay;) unsigned char ka0302$b_fill1100 [60]; __union {+ unsigned int ka0302$l_slot2_lcntr0; __struct {6 unsigned ka0302$v_slot2_lcntr0_fill1 : 32;) } ka0302$r_slot2_lcntr0_bits;( } ka0302$r_slot2_lcntr0_overlay;) unsigned char ka0302$b_fill1110 [60]; __union {+ unsigned int ka0302$l_slot2_lcntr1; __struct {6 unsigned ka0302$v_slot2_lcntr1_fill1 : 32;) * } ka0302$r_slot2_lcntr1_bits;( } ka0302$r_slot2_lcntr1_overlay;) unsigned char ka0302$b_fill1120 [60]; __union {. unsigned int ka0302$l_slot2_lmissaddr; __struct {9 unsigned ka0302$v_slot2_lmissaddr_fill1 : 32;, } ka0302$r_slot2_lmissaddr_bits;+ } ka0302$r_slot2_lmissaddr_overlay;+ unsigned char ka0302$b_fill1125 [4156]; __union {( unsigned int ka0302$l_slot2_mcr; __struct {3 unsign*ed ka0302$v_slot2_mcr_fill1 : 32;& } ka0302$r_slot2_mcr_bits;% } ka0302$r_slot2_mcr_overlay;) unsigned char ka0302$b_fill1130 [60]; __union {( unsigned int ka0302$l_slot2_amr; __struct {3 unsigned ka0302$v_slot2_amr_fill1 : 32;& } ka0302$r_slot2_amr_bits;% } ka0302$r_slot2_amr_overlay;) unsigned char ka0302$b_fill1140 [60]; __union {* unsigned int ka0302$l_slot2_mstr0; __struct {5 * unsigned ka0302$v_slot2_mstr0_fill1 : 32;( } ka0302$r_slot2_mstr0_bits;' } ka0302$r_slot2_mstr0_overlay;) unsigned char ka0302$b_fill1150 [60]; __union {* unsigned int ka0302$l_slot2_mstr1; __struct {5 unsigned ka0302$v_slot2_mstr1_fill1 : 32;( } ka0302$r_slot2_mstr1_bits;' } ka0302$r_slot2_mstr1_overlay;) unsigned char ka0302$b_fill1160 [60]; __union {) unsigned int ka0302$l_slot2_fadr; * __struct {4 unsigned ka0302$v_slot2_fadr_fill1 : 32;' } ka0302$r_slot2_fadr_bits;& } ka0302$r_slot2_fadr_overlay;) unsigned char ka0302$b_fill1170 [60]; __union {) unsigned int ka0302$l_slot2_mera; __struct {4 unsigned ka0302$v_slot2_mera_fill1 : 32;' } ka0302$r_slot2_mera_bits;& } ka0302$r_slot2_mera_overlay;) unsigned char ka0302$b_fill1180 [60]; __union {+ unsigned int ka0302$*l_slot2_msynda; __struct {6 unsigned ka0302$v_slot2_msynda_fill1 : 32;) } ka0302$r_slot2_msynda_bits;( } ka0302$r_slot2_msynda_overlay;) unsigned char ka0302$b_fill1190 [60]; __union {) unsigned int ka0302$l_slot2_mdra; __struct {4 unsigned ka0302$v_slot2_mdra_fill1 : 32;' } ka0302$r_slot2_mdra_bits;& } ka0302$r_slot2_mdra_overlay;) unsigned char ka0302$b_fill1200 [60]; __union {* * unsigned int ka0302$l_slot2_mcbsa; __struct {5 unsigned ka0302$v_slot2_mcbsa_fill1 : 32;( } ka0302$r_slot2_mcbsa_bits;' } ka0302$r_slot2_mcbsa_overlay;+ unsigned char ka0302$b_fill1210 [7996]; __union {) unsigned int ka0302$l_slot2_merb; __struct {4 unsigned ka0302$v_slot2_merb_fill1 : 32;' } ka0302$r_slot2_merb_bits;& } ka0302$r_slot2_merb_overlay;) unsigned char ka0302$b_fill1220 [6*0]; __union {+ unsigned int ka0302$l_slot2_msyndb; __struct {6 unsigned ka0302$v_slot2_msyndb_fill1 : 32;) } ka0302$r_slot2_msyndb_bits;( } ka0302$r_slot2_msyndb_overlay;) unsigned char ka0302$b_fill1230 [60]; __union {) unsigned int ka0302$l_slot2_mdrb; __struct {4 unsigned ka0302$v_slot2_mdrb_fill1 : 32;' } ka0302$r_slot2_mdrb_bits;& } ka0302$r_slot2_mdrb_overlay;) unsigned* char ka0302$b_fill1240 [60]; __union {* unsigned int ka0302$l_slot2_mcbsb; __struct {5 unsigned ka0302$v_slot2_mcbsb_fill1 : 32;( } ka0302$r_slot2_mcbsb_bits;' } ka0302$r_slot2_mcbsb_overlay;+ unsigned char ka0302$b_fill1250 [7676]; __union {) unsigned int ka0302$l_slot3_ldev; __struct {4 unsigned ka0302$v_slot3_ldev_dtype : 16;3 unsigned ka0302$v_slot3_ldev_drev : 16;' } ka *0302$r_slot3_ldev_bits;& } ka0302$r_slot3_ldev_overlay;) unsigned char ka0302$b_fill1260 [60]; __union {) unsigned int ka0302$l_slot3_lber; __struct {/ unsigned ka0302$v_slot3_lber_e : 1;1 unsigned ka0302$v_slot3_lber_uce : 1;2 unsigned ka0302$v_slot3_lber_uce2 : 1;0 unsigned ka0302$v_slot3_lber_ce : 1;1 unsigned ka0302$v_slot3_lber_ce2 : 1;1 unsigned ka0302$v_slot3_lber_cpe : 1;2 * unsigned ka0302$v_slot3_lber_cpe2 : 1;2 unsigned ka0302$v_slot3_lber_cdpe : 1;3 unsigned ka0302$v_slot3_lber_cdpe2 : 1;1 unsigned ka0302$v_slot3_lber_tde : 1;1 unsigned ka0302$v_slot3_lber_ste : 1;2 unsigned ka0302$v_slot3_lber_cnfe : 1;2 unsigned ka0302$v_slot3_lber_nxae : 1;1 unsigned ka0302$v_slot3_lber_cae : 1;1 unsigned ka0302$v_slot3_lber_she : 1;1 unsigned ka0302$v_slot3_lber_d *ie : 1;2 unsigned ka0302$v_slot3_lber_dtce : 1;2 unsigned ka0302$v_slot3_lber_ctce : 1;2 unsigned ka0302$v_slot3_lber_nses : 1;4 unsigned ka0302$v_slot3_lber_fill1 : 13;' } ka0302$r_slot3_lber_bits;& } ka0302$r_slot3_lber_overlay;) unsigned char ka0302$b_fill1270 [60]; __union {) unsigned int ka0302$l_slot3_lcnr; __struct {2 unsigned ka0302$v_slot3_lcnr_ceen : 1;4 unsigned ka030 *2$v_slot3_lcnr_fill1 : 27;5 unsigned ka0302$v_slot3_lcnr_rststat : 1;3 unsigned ka0302$v_slot3_lcnr_nhalt : 1;2 unsigned ka0302$v_slot3_lcnr_nrst : 1;1 unsigned ka0302$v_slot3_lcnr_stf : 1;' } ka0302$r_slot3_lcnr_bits;& } ka0302$r_slot3_lcnr_overlay;( unsigned char ka0302$b_fill275 [60]; __union {( unsigned int ka0302$l_slot3_ibr; __struct {5 unsigned ka0302$v_slot3_ibr_rcv_sdat : 1;5 * unsigned ka0302$v_slot3_ibr_xmt_sdat : 1;1 unsigned ka0302$v_slot3_ibr_sclk : 1;3 unsigned ka0302$v_slot3_ibr_fill1 : 29;& } ka0302$r_slot3_ibr_bits;% } ka0302$r_slot3_ibr_overlay;* unsigned char ka0302$b_fill1280 [316]; __union {* unsigned int ka0302$l_slot3_lmmr0; __struct {1 unsigned ka0302$v_slot3_lmmr0_en : 1;2 unsigned ka0302$v_slot3_lmmr0_int : 2;1 unsigned ka0302$v_slot3_lm *mr0_ia : 2;1 unsigned ka0302$v_slot3_lmmr0_aw : 4;5 unsigned ka0302$v_slot3_lmmr0_nbanks : 2;4 unsigned ka0302$v_slot3_lmmr0_fill1 : 6;4 unsigned ka0302$v_slot3_lmmr0_addr : 15;( } ka0302$r_slot3_lmmr0_bits;' } ka0302$r_slot3_lmmr0_overlay;) unsigned char ka0302$b_fill1290 [60]; __union {* unsigned int ka0302$l_slot3_lmmr1; __struct {1 unsigned ka0302$v_slot3_lmmr1_en : 1;2 un *signed ka0302$v_slot3_lmmr1_int : 2;1 unsigned ka0302$v_slot3_lmmr1_ia : 2;1 unsigned ka0302$v_slot3_lmmr1_aw : 4;5 unsigned ka0302$v_slot3_lmmr1_nbanks : 2;4 unsigned ka0302$v_slot3_lmmr1_fill1 : 6;4 unsigned ka0302$v_slot3_lmmr1_addr : 15;( } ka0302$r_slot3_lmmr1_bits;' } ka0302$r_slot3_lmmr1_overlay;) unsigned char ka0302$b_fill1300 [60]; __union {* unsigned int ka0302$l_slot3_lmmr2; __st *ruct {1 unsigned ka0302$v_slot3_lmmr2_en : 1;2 unsigned ka0302$v_slot3_lmmr2_int : 2;1 unsigned ka0302$v_slot3_lmmr2_ia : 2;1 unsigned ka0302$v_slot3_lmmr2_aw : 4;5 unsigned ka0302$v_slot3_lmmr2_nbanks : 2;4 unsigned ka0302$v_slot3_lmmr2_fill1 : 6;4 unsigned ka0302$v_slot3_lmmr2_addr : 15;( } ka0302$r_slot3_lmmr2_bits;' } ka0302$r_slot3_lmmr2_overlay;) unsigned char ka0302$b_fill1310 [60] *; __union {* unsigned int ka0302$l_slot3_lmmr3; __struct {1 unsigned ka0302$v_slot3_lmmr3_en : 1;2 unsigned ka0302$v_slot3_lmmr3_int : 2;1 unsigned ka0302$v_slot3_lmmr3_ia : 2;1 unsigned ka0302$v_slot3_lmmr3_aw : 4;5 unsigned ka0302$v_slot3_lmmr3_nbanks : 2;4 unsigned ka0302$v_slot3_lmmr3_fill1 : 6;4 unsigned ka0302$v_slot3_lmmr3_addr : 15;( } ka0302$r_slot3_lmmr3_bits;' * } ka0302$r_slot3_lmmr3_overlay;) unsigned char ka0302$b_fill1320 [60]; __union {* unsigned int ka0302$l_slot3_lmmr4; __struct {1 unsigned ka0302$v_slot3_lmmr4_en : 1;2 unsigned ka0302$v_slot3_lmmr4_int : 2;1 unsigned ka0302$v_slot3_lmmr4_ia : 2;1 unsigned ka0302$v_slot3_lmmr4_aw : 4;5 unsigned ka0302$v_slot3_lmmr4_nbanks : 2;4 unsigned ka0302$v_slot3_lmmr4_fill1 : 6;4 unsigned ka030 *2$v_slot3_lmmr4_addr : 15;( } ka0302$r_slot3_lmmr4_bits;' } ka0302$r_slot3_lmmr4_overlay;) unsigned char ka0302$b_fill1330 [60]; __union {* unsigned int ka0302$l_slot3_lmmr5; __struct {1 unsigned ka0302$v_slot3_lmmr5_en : 1;2 unsigned ka0302$v_slot3_lmmr5_int : 2;1 unsigned ka0302$v_slot3_lmmr5_ia : 2;1 unsigned ka0302$v_slot3_lmmr5_aw : 4;5 unsigned ka0302$v_slot3_lmmr5_nbanks : 2;4 * unsigned ka0302$v_slot3_lmmr5_fill1 : 6;4 unsigned ka0302$v_slot3_lmmr5_addr : 15;( } ka0302$r_slot3_lmmr5_bits;' } ka0302$r_slot3_lmmr5_overlay;) unsigned char ka0302$b_fill1340 [60]; __union {* unsigned int ka0302$l_slot3_lmmr6; __struct {1 unsigned ka0302$v_slot3_lmmr6_en : 1;2 unsigned ka0302$v_slot3_lmmr6_int : 2;1 unsigned ka0302$v_slot3_lmmr6_ia : 2;1 unsigned ka0302$v_slot3_ +lmmr6_aw : 4;5 unsigned ka0302$v_slot3_lmmr6_nbanks : 2;4 unsigned ka0302$v_slot3_lmmr6_fill1 : 6;4 unsigned ka0302$v_slot3_lmmr6_addr : 15;( } ka0302$r_slot3_lmmr6_bits;' } ka0302$r_slot3_lmmr6_overlay;) unsigned char ka0302$b_fill1350 [60]; __union {* unsigned int ka0302$l_slot3_lmmr7; __struct {1 unsigned ka0302$v_slot3_lmmr7_en : 1;2 unsigned ka0302$v_slot3_lmmr7_int : 2;1 +unsigned ka0302$v_slot3_lmmr7_ia : 2;1 unsigned ka0302$v_slot3_lmmr7_aw : 4;5 unsigned ka0302$v_slot3_lmmr7_nbanks : 2;4 unsigned ka0302$v_slot3_lmmr7_fill1 : 6;4 unsigned ka0302$v_slot3_lmmr7_addr : 15;( } ka0302$r_slot3_lmmr7_bits;' } ka0302$r_slot3_lmmr7_overlay;* unsigned char ka0302$b_fill1360 [572]; __union {+ unsigned int ka0302$l_slot3_lbesr0; __struct {8 unsigned ka0302$v_slot3_lb +esr0_syndrome : 7;6 unsigned ka0302$v_slot3_lbesr0_fill1 : 25;) } ka0302$r_slot3_lbesr0_bits;( } ka0302$r_slot3_lbesr0_overlay;) unsigned char ka0302$b_fill1370 [60]; __union {+ unsigned int ka0302$l_slot3_lbesr1; __struct {8 unsigned ka0302$v_slot3_lbesr1_syndrome : 7;6 unsigned ka0302$v_slot3_lbesr1_fill1 : 25;) } ka0302$r_slot3_lbesr1_bits;( } ka0302$r_slot3_lbesr1_overlay;) unsigned cha+r ka0302$b_fill1380 [60]; __union {+ unsigned int ka0302$l_slot3_lbesr2; __struct {8 unsigned ka0302$v_slot3_lbesr2_syndrome : 7;6 unsigned ka0302$v_slot3_lbesr2_fill1 : 25;) } ka0302$r_slot3_lbesr2_bits;( } ka0302$r_slot3_lbesr2_overlay;) unsigned char ka0302$b_fill1390 [60]; __union {+ unsigned int ka0302$l_slot3_lbesr3; __struct {8 unsigned ka0302$v_slot3_lbesr3_syndrome : 7;6 + unsigned ka0302$v_slot3_lbesr3_fill1 : 25;) } ka0302$r_slot3_lbesr3_bits;( } ka0302$r_slot3_lbesr3_overlay;) unsigned char ka0302$b_fill1400 [60]; __union {+ unsigned int ka0302$l_slot3_lbecr0; __struct {2 unsigned int ka0302$l_slot3_lbecr0_ca;) } ka0302$r_slot3_lbecr0_bits;( } ka0302$r_slot3_lbecr0_overlay;) unsigned char ka0302$b_fill1410 [60]; __union {+ unsigned int ka0302$l_slot3_lbecr1; + __struct {2 unsigned ka0302$v_slot3_lbecr1_ca : 7;3 unsigned ka0302$v_slot3_lbecr1_cid : 4;3 unsigned ka0302$v_slot3_lbecr1_rid : 4;3 unsigned ka0302$v_slot3_lbecr1_cnf : 1;6 unsigned ka0302$v_slot3_lbecr1_shared : 1;5 unsigned ka0302$v_slot3_lbecr1_dirty : 1;6 unsigned ka0302$v_slot3_lbecr1_dcycle : 2;6 unsigned ka0302$v_slot3_lbecr1_fill1 : 12;) } ka0302$r_slot3_lbecr1_bits;( + } ka0302$r_slot3_lbecr1_overlay;+ unsigned char ka0302$b_fill1420 [1212]; __union {* unsigned int ka0302$l_slot3_lmode; __struct {5 unsigned ka0302$v_slot3_lmode_fill1 : 32;( } ka0302$r_slot3_lmode_bits;' } ka0302$r_slot3_lmode_overlay;) unsigned char ka0302$b_fill1430 [60]; __union {* unsigned int ka0302$l_slot3_lmerr; __struct {5 unsigned ka0302$v_slot3_lmerr_fill1 : 32;( } ka+0302$r_slot3_lmerr_bits;' } ka0302$r_slot3_lmerr_overlay;) unsigned char ka0302$b_fill1440 [60]; __union {* unsigned int ka0302$l_slot3_llock; __struct {5 unsigned ka0302$v_slot3_llock_fill1 : 32;( } ka0302$r_slot3_llock_bits;' } ka0302$r_slot3_llock_overlay;) unsigned char ka0302$b_fill1450 [60]; __union {* unsigned int ka0302$l_slot3_ledto; __struct {5 unsigned ka0302$v_slot3_ledto_fill+1 : 32;( } ka0302$r_slot3_ledto_bits;' } ka0302$r_slot3_ledto_overlay;) unsigned char ka0302$b_fill1460 [60]; __union {* unsigned int ka0302$l_slot3_ldiag; __struct {5 unsigned ka0302$v_slot3_ldiag_fill1 : 32;( } ka0302$r_slot3_ldiag_bits;' } ka0302$r_slot3_ldiag_overlay;) unsigned char ka0302$b_fill1470 [60]; __union {* unsigned int ka0302$l_slot3_ltaga; __struct {5 unsigned + ka0302$v_slot3_ltaga_fill1 : 32;( } ka0302$r_slot3_ltaga_bits;' } ka0302$r_slot3_ltaga_overlay;) unsigned char ka0302$b_fill1480 [60]; __union {* unsigned int ka0302$l_slot3_ltagw; __struct {5 unsigned ka0302$v_slot3_ltagw_fill1 : 32;( } ka0302$r_slot3_ltagw_bits;' } ka0302$r_slot3_ltagw_overlay;* unsigned char ka0302$b_fill1490 [124]; __union {* unsigned int ka0302$l_slot3_lcon0; __struct + {5 unsigned ka0302$v_slot3_lcon0_fill1 : 32;( } ka0302$r_slot3_lcon0_bits;' } ka0302$r_slot3_lcon0_overlay;) unsigned char ka0302$b_fill1500 [60]; __union {* unsigned int ka0302$l_slot3_lcon1; __struct {5 unsigned ka0302$v_slot3_lcon1_fill1 : 32;( } ka0302$r_slot3_lcon1_bits;' } ka0302$r_slot3_lcon1_overlay;* unsigned char ka0302$b_fill1510 [188]; __union {* unsigned int ka0302$l_slot +3_lperf; __struct {5 unsigned ka0302$v_slot3_lperf_fill1 : 32;( } ka0302$r_slot3_lperf_bits;' } ka0302$r_slot3_lperf_overlay;) unsigned char ka0302$b_fill1520 [60]; __union {+ unsigned int ka0302$l_slot3_lcntr0; __struct {6 unsigned ka0302$v_slot3_lcntr0_fill1 : 32;) } ka0302$r_slot3_lcntr0_bits;( } ka0302$r_slot3_lcntr0_overlay;) unsigned char ka0302$b_fill1530 [60]; __union {+ + unsigned int ka0302$l_slot3_lcntr1; __struct {6 unsigned ka0302$v_slot3_lcntr1_fill1 : 32;) } ka0302$r_slot3_lcntr1_bits;( } ka0302$r_slot3_lcntr1_overlay;) unsigned char ka0302$b_fill1540 [60]; __union {. unsigned int ka0302$l_slot3_lmissaddr; __struct {9 unsigned ka0302$v_slot3_lmissaddr_fill1 : 32;, } ka0302$r_slot3_lmissaddr_bits;+ } ka0302$r_slot3_lmissaddr_overlay;+ unsigned char  +ka0302$b_fill1545 [4156]; __union {( unsigned int ka0302$l_slot3_mcr; __struct {3 unsigned ka0302$v_slot3_mcr_fill1 : 32;& } ka0302$r_slot3_mcr_bits;% } ka0302$r_slot3_mcr_overlay;) unsigned char ka0302$b_fill1550 [60]; __union {( unsigned int ka0302$l_slot3_amr; __struct {3 unsigned ka0302$v_slot3_amr_fill1 : 32;& } ka0302$r_slot3_amr_bits;% } ka0302$r_slot3_amr_overlay;) un+signed char ka0302$b_fill1560 [60]; __union {* unsigned int ka0302$l_slot3_mstr0; __struct {5 unsigned ka0302$v_slot3_mstr0_fill1 : 32;( } ka0302$r_slot3_mstr0_bits;' } ka0302$r_slot3_mstr0_overlay;) unsigned char ka0302$b_fill1570 [60]; __union {* unsigned int ka0302$l_slot3_mstr1; __struct {5 unsigned ka0302$v_slot3_mstr1_fill1 : 32;( } ka0302$r_slot3_mstr1_bits;' } ka0302$r_slo+t3_mstr1_overlay;) unsigned char ka0302$b_fill1580 [60]; __union {) unsigned int ka0302$l_slot3_fadr; __struct {4 unsigned ka0302$v_slot3_fadr_fill1 : 32;' } ka0302$r_slot3_fadr_bits;& } ka0302$r_slot3_fadr_overlay;) unsigned char ka0302$b_fill1590 [60]; __union {) unsigned int ka0302$l_slot3_mera; __struct {4 unsigned ka0302$v_slot3_mera_fill1 : 32;' } ka0302$r_slot3_mera_bits;& + } ka0302$r_slot3_mera_overlay;) unsigned char ka0302$b_fill1600 [60]; __union {+ unsigned int ka0302$l_slot3_msynda; __struct {6 unsigned ka0302$v_slot3_msynda_fill1 : 32;) } ka0302$r_slot3_msynda_bits;( } ka0302$r_slot3_msynda_overlay;) unsigned char ka0302$b_fill1610 [60]; __union {) unsigned int ka0302$l_slot3_mdra; __struct {4 unsigned ka0302$v_slot3_mdra_fill1 : 32;' } ka03+02$r_slot3_mdra_bits;& } ka0302$r_slot3_mdra_overlay;) unsigned char ka0302$b_fill1620 [60]; __union {* unsigned int ka0302$l_slot3_mcbsa; __struct {5 unsigned ka0302$v_slot3_mcbsa_fill1 : 32;( } ka0302$r_slot3_mcbsa_bits;' } ka0302$r_slot3_mcbsa_overlay;+ unsigned char ka0302$b_fill1630 [7996]; __union {) unsigned int ka0302$l_slot3_merb; __struct {4 unsigned ka0302$v_slot3_merb_fill1 :+ 32;' } ka0302$r_slot3_merb_bits;& } ka0302$r_slot3_merb_overlay;) unsigned char ka0302$b_fill1640 [60]; __union {+ unsigned int ka0302$l_slot3_msyndb; __struct {6 unsigned ka0302$v_slot3_msyndb_fill1 : 32;) } ka0302$r_slot3_msyndb_bits;( } ka0302$r_slot3_msyndb_overlay;) unsigned char ka0302$b_fill1650 [60]; __union {) unsigned int ka0302$l_slot3_mdrb; __struct {4 unsigned k+a0302$v_slot3_mdrb_fill1 : 32;' } ka0302$r_slot3_mdrb_bits;& } ka0302$r_slot3_mdrb_overlay;) unsigned char ka0302$b_fill1660 [60]; __union {* unsigned int ka0302$l_slot3_mcbsb; __struct {5 unsigned ka0302$v_slot3_mcbsb_fill1 : 32;( } ka0302$r_slot3_mcbsb_bits;' } ka0302$r_slot3_mcbsb_overlay;+ unsigned char ka0302$b_fill1670 [7676]; __union {) unsigned int ka0302$l_slot4_ldev; __struct { +4 unsigned ka0302$v_slot4_ldev_dtype : 16;3 unsigned ka0302$v_slot4_ldev_drev : 16;' } ka0302$r_slot4_ldev_bits;& } ka0302$r_slot4_ldev_overlay;) unsigned char ka0302$b_fill1680 [60]; __union {) unsigned int ka0302$l_slot4_lber; __struct {/ unsigned ka0302$v_slot4_lber_e : 1;1 unsigned ka0302$v_slot4_lber_uce : 1;2 unsigned ka0302$v_slot4_lber_uce2 : 1;0 unsigned ka0302$v_slot +4_lber_ce : 1;1 unsigned ka0302$v_slot4_lber_ce2 : 1;1 unsigned ka0302$v_slot4_lber_cpe : 1;2 unsigned ka0302$v_slot4_lber_cpe2 : 1;2 unsigned ka0302$v_slot4_lber_cdpe : 1;3 unsigned ka0302$v_slot4_lber_cdpe2 : 1;1 unsigned ka0302$v_slot4_lber_tde : 1;1 unsigned ka0302$v_slot4_lber_ste : 1;2 unsigned ka0302$v_slot4_lber_cnfe : 1;2 unsigned ka0302$v_slot4_lber_nxae : 1;1 unsigned + ka0302$v_slot4_lber_cae : 1;1 unsigned ka0302$v_slot4_lber_she : 1;1 unsigned ka0302$v_slot4_lber_die : 1;2 unsigned ka0302$v_slot4_lber_dtce : 1;2 unsigned ka0302$v_slot4_lber_ctce : 1;2 unsigned ka0302$v_slot4_lber_nses : 1;4 unsigned ka0302$v_slot4_lber_fill1 : 13;' } ka0302$r_slot4_lber_bits;& } ka0302$r_slot4_lber_overlay;) unsigned char ka0302$b_fill1690 [60]; __union {) unsigned i +nt ka0302$l_slot4_lcnr; __struct {2 unsigned ka0302$v_slot4_lcnr_ceen : 1;4 unsigned ka0302$v_slot4_lcnr_fill1 : 27;5 unsigned ka0302$v_slot4_lcnr_rststat : 1;3 unsigned ka0302$v_slot4_lcnr_nhalt : 1;2 unsigned ka0302$v_slot4_lcnr_nrst : 1;1 unsigned ka0302$v_slot4_lcnr_stf : 1;' } ka0302$r_slot4_lcnr_bits;& } ka0302$r_slot4_lcnr_overlay;) unsigned char ka0302$b_fill1695 [60]; __union + {( unsigned int ka0302$l_slot4_ibr; __struct {5 unsigned ka0302$v_slot4_ibr_rcv_sdat : 1;5 unsigned ka0302$v_slot4_ibr_xmt_sdat : 1;1 unsigned ka0302$v_slot4_ibr_sclk : 1;3 unsigned ka0302$v_slot4_ibr_fill1 : 29;& } ka0302$r_slot4_ibr_bits;% } ka0302$r_slot4_ibr_overlay;* unsigned char ka0302$b_fill1700 [316]; __union {* unsigned int ka0302$l_slot4_lmmr0; __struct {1 un +signed ka0302$v_slot4_lmmr0_en : 1;2 unsigned ka0302$v_slot4_lmmr0_int : 2;1 unsigned ka0302$v_slot4_lmmr0_ia : 2;1 unsigned ka0302$v_slot4_lmmr0_aw : 4;5 unsigned ka0302$v_slot4_lmmr0_nbanks : 2;4 unsigned ka0302$v_slot4_lmmr0_fill1 : 6;4 unsigned ka0302$v_slot4_lmmr0_addr : 15;( } ka0302$r_slot4_lmmr0_bits;' } ka0302$r_slot4_lmmr0_overlay;) unsigned char ka0302$b_fill1710 [60]; __union {* + unsigned int ka0302$l_slot4_lmmr1; __struct {1 unsigned ka0302$v_slot4_lmmr1_en : 1;2 unsigned ka0302$v_slot4_lmmr1_int : 2;1 unsigned ka0302$v_slot4_lmmr1_ia : 2;1 unsigned ka0302$v_slot4_lmmr1_aw : 4;5 unsigned ka0302$v_slot4_lmmr1_nbanks : 2;4 unsigned ka0302$v_slot4_lmmr1_fill1 : 6;4 unsigned ka0302$v_slot4_lmmr1_addr : 15;( } ka0302$r_slot4_lmmr1_bits;' } ka0302$r_slot4_lmmr1 +_overlay;) unsigned char ka0302$b_fill1720 [60]; __union {* unsigned int ka0302$l_slot4_lmmr2; __struct {1 unsigned ka0302$v_slot4_lmmr2_en : 1;2 unsigned ka0302$v_slot4_lmmr2_int : 2;1 unsigned ka0302$v_slot4_lmmr2_ia : 2;1 unsigned ka0302$v_slot4_lmmr2_aw : 4;5 unsigned ka0302$v_slot4_lmmr2_nbanks : 2;4 unsigned ka0302$v_slot4_lmmr2_fill1 : 6;4 unsigned ka0302$v_slot4_lmmr2_addr : 1 +5;( } ka0302$r_slot4_lmmr2_bits;' } ka0302$r_slot4_lmmr2_overlay;) unsigned char ka0302$b_fill1730 [60]; __union {* unsigned int ka0302$l_slot4_lmmr3; __struct {1 unsigned ka0302$v_slot4_lmmr3_en : 1;2 unsigned ka0302$v_slot4_lmmr3_int : 2;1 unsigned ka0302$v_slot4_lmmr3_ia : 2;1 unsigned ka0302$v_slot4_lmmr3_aw : 4;5 unsigned ka0302$v_slot4_lmmr3_nbanks : 2;4 unsigned ka0302$ +v_slot4_lmmr3_fill1 : 6;4 unsigned ka0302$v_slot4_lmmr3_addr : 15;( } ka0302$r_slot4_lmmr3_bits;' } ka0302$r_slot4_lmmr3_overlay;) unsigned char ka0302$b_fill1740 [60]; __union {* unsigned int ka0302$l_slot4_lmmr4; __struct {1 unsigned ka0302$v_slot4_lmmr4_en : 1;2 unsigned ka0302$v_slot4_lmmr4_int : 2;1 unsigned ka0302$v_slot4_lmmr4_ia : 2;1 unsigned ka0302$v_slot4_lmmr4_aw : 4;5 + unsigned ka0302$v_slot4_lmmr4_nbanks : 2;4 unsigned ka0302$v_slot4_lmmr4_fill1 : 6;4 unsigned ka0302$v_slot4_lmmr4_addr : 15;( } ka0302$r_slot4_lmmr4_bits;' } ka0302$r_slot4_lmmr4_overlay;) unsigned char ka0302$b_fill1750 [60]; __union {* unsigned int ka0302$l_slot4_lmmr5; __struct {1 unsigned ka0302$v_slot4_lmmr5_en : 1;2 unsigned ka0302$v_slot4_lmmr5_int : 2;1 unsigned ka0302$v_slot4_ +lmmr5_ia : 2;1 unsigned ka0302$v_slot4_lmmr5_aw : 4;5 unsigned ka0302$v_slot4_lmmr5_nbanks : 2;4 unsigned ka0302$v_slot4_lmmr5_fill1 : 6;4 unsigned ka0302$v_slot4_lmmr5_addr : 15;( } ka0302$r_slot4_lmmr5_bits;' } ka0302$r_slot4_lmmr5_overlay;) unsigned char ka0302$b_fill1760 [60]; __union {* unsigned int ka0302$l_slot4_lmmr6; __struct {1 unsigned ka0302$v_slot4_lmmr6_en : 1;2 +unsigned ka0302$v_slot4_lmmr6_int : 2;1 unsigned ka0302$v_slot4_lmmr6_ia : 2;1 unsigned ka0302$v_slot4_lmmr6_aw : 4;5 unsigned ka0302$v_slot4_lmmr6_nbanks : 2;4 unsigned ka0302$v_slot4_lmmr6_fill1 : 6;4 unsigned ka0302$v_slot4_lmmr6_addr : 15;( } ka0302$r_slot4_lmmr6_bits;' } ka0302$r_slot4_lmmr6_overlay;) unsigned char ka0302$b_fill1770 [60]; __union {* unsigned int ka0302$l_slot4_lmmr7; __ !+struct {1 unsigned ka0302$v_slot4_lmmr7_en : 1;2 unsigned ka0302$v_slot4_lmmr7_int : 2;1 unsigned ka0302$v_slot4_lmmr7_ia : 2;1 unsigned ka0302$v_slot4_lmmr7_aw : 4;5 unsigned ka0302$v_slot4_lmmr7_nbanks : 2;4 unsigned ka0302$v_slot4_lmmr7_fill1 : 6;4 unsigned ka0302$v_slot4_lmmr7_addr : 15;( } ka0302$r_slot4_lmmr7_bits;' } ka0302$r_slot4_lmmr7_overlay;* unsigned char ka0302$b_fill1780 [5"+72]; __union {+ unsigned int ka0302$l_slot4_lbesr0; __struct {8 unsigned ka0302$v_slot4_lbesr0_syndrome : 7;6 unsigned ka0302$v_slot4_lbesr0_fill1 : 25;) } ka0302$r_slot4_lbesr0_bits;( } ka0302$r_slot4_lbesr0_overlay;) unsigned char ka0302$b_fill1790 [60]; __union {+ unsigned int ka0302$l_slot4_lbesr1; __struct {8 unsigned ka0302$v_slot4_lbesr1_syndrome : 7;6 unsigned ka0302$v_#+slot4_lbesr1_fill1 : 25;) } ka0302$r_slot4_lbesr1_bits;( } ka0302$r_slot4_lbesr1_overlay;) unsigned char ka0302$b_fill1800 [60]; __union {+ unsigned int ka0302$l_slot4_lbesr2; __struct {8 unsigned ka0302$v_slot4_lbesr2_syndrome : 7;6 unsigned ka0302$v_slot4_lbesr2_fill1 : 25;) } ka0302$r_slot4_lbesr2_bits;( } ka0302$r_slot4_lbesr2_overlay;) unsigned char ka0302$b_fill1810 [60]; __union {+ $+ unsigned int ka0302$l_slot4_lbesr3; __struct {8 unsigned ka0302$v_slot4_lbesr3_syndrome : 7;6 unsigned ka0302$v_slot4_lbesr3_fill1 : 25;) } ka0302$r_slot4_lbesr3_bits;( } ka0302$r_slot4_lbesr3_overlay;) unsigned char ka0302$b_fill1820 [60]; __union {+ unsigned int ka0302$l_slot4_lbecr0; __struct {2 unsigned int ka0302$l_slot4_lbecr0_ca;) } ka0302$r_slot4_lbecr0_bits;( } ka0302$r_s %+lot4_lbecr0_overlay;) unsigned char ka0302$b_fill1830 [60]; __union {+ unsigned int ka0302$l_slot4_lbecr1; __struct {2 unsigned ka0302$v_slot4_lbecr1_ca : 7;3 unsigned ka0302$v_slot4_lbecr1_cid : 4;3 unsigned ka0302$v_slot4_lbecr1_rid : 4;3 unsigned ka0302$v_slot4_lbecr1_cnf : 1;6 unsigned ka0302$v_slot4_lbecr1_shared : 1;5 unsigned ka0302$v_slot4_lbecr1_dirty : 1;6 unsigned ka0302$v_&+slot4_lbecr1_dcycle : 2;6 unsigned ka0302$v_slot4_lbecr1_fill1 : 12;) } ka0302$r_slot4_lbecr1_bits;( } ka0302$r_slot4_lbecr1_overlay;+ unsigned char ka0302$b_fill1840 [1212]; __union {* unsigned int ka0302$l_slot4_lmode; __struct {5 unsigned ka0302$v_slot4_lmode_fill1 : 32;( } ka0302$r_slot4_lmode_bits;' } ka0302$r_slot4_lmode_overlay;) unsigned char ka0302$b_fill1850 [60]; __union {* un'+signed int ka0302$l_slot4_lmerr; __struct {5 unsigned ka0302$v_slot4_lmerr_fill1 : 32;( } ka0302$r_slot4_lmerr_bits;' } ka0302$r_slot4_lmerr_overlay;) unsigned char ka0302$b_fill1860 [60]; __union {* unsigned int ka0302$l_slot4_llock; __struct {5 unsigned ka0302$v_slot4_llock_fill1 : 32;( } ka0302$r_slot4_llock_bits;' } ka0302$r_slot4_llock_overlay;) unsigned char ka0302$b_fill1870 [60];(+ __union {* unsigned int ka0302$l_slot4_ledto; __struct {5 unsigned ka0302$v_slot4_ledto_fill1 : 32;( } ka0302$r_slot4_ledto_bits;' } ka0302$r_slot4_ledto_overlay;) unsigned char ka0302$b_fill1880 [60]; __union {* unsigned int ka0302$l_slot4_ldiag; __struct {5 unsigned ka0302$v_slot4_ldiag_fill1 : 32;( } ka0302$r_slot4_ldiag_bits;' } ka0302$r_slot4_ldiag_overlay;) unsigned char )+ka0302$b_fill1890 [60]; __union {* unsigned int ka0302$l_slot4_ltaga; __struct {5 unsigned ka0302$v_slot4_ltaga_fill1 : 32;( } ka0302$r_slot4_ltaga_bits;' } ka0302$r_slot4_ltaga_overlay;) unsigned char ka0302$b_fill1900 [60]; __union {* unsigned int ka0302$l_slot4_ltagw; __struct {5 unsigned ka0302$v_slot4_ltagw_fill1 : 32;( } ka0302$r_slot4_ltagw_bits;' } ka0302$r_slot4_ltagw_ove*+rlay;* unsigned char ka0302$b_fill1910 [124]; __union {* unsigned int ka0302$l_slot4_lcon0; __struct {5 unsigned ka0302$v_slot4_lcon0_fill1 : 32;( } ka0302$r_slot4_lcon0_bits;' } ka0302$r_slot4_lcon0_overlay;) unsigned char ka0302$b_fill1920 [60]; __union {* unsigned int ka0302$l_slot4_lcon1; __struct {5 unsigned ka0302$v_slot4_lcon1_fill1 : 32;( } ka0302$r_slot4_lcon1_bits;' ++} ka0302$r_slot4_lcon1_overlay;* unsigned char ka0302$b_fill1930 [188]; __union {* unsigned int ka0302$l_slot4_lperf; __struct {5 unsigned ka0302$v_slot4_lperf_fill1 : 32;( } ka0302$r_slot4_lperf_bits;' } ka0302$r_slot4_lperf_overlay;) unsigned char ka0302$b_fill1940 [60]; __union {+ unsigned int ka0302$l_slot4_lcntr0; __struct {6 unsigned ka0302$v_slot4_lcntr0_fill1 : 32;) } ka0302$r,+_slot4_lcntr0_bits;( } ka0302$r_slot4_lcntr0_overlay;) unsigned char ka0302$b_fill1950 [60]; __union {+ unsigned int ka0302$l_slot4_lcntr1; __struct {6 unsigned ka0302$v_slot4_lcntr1_fill1 : 32;) } ka0302$r_slot4_lcntr1_bits;( } ka0302$r_slot4_lcntr1_overlay;) unsigned char ka0302$b_fill1960 [60]; __union {. unsigned int ka0302$l_slot4_lmissaddr; __struct {9 unsigned ka0302$v_slot4_lmissa-+ddr_fill1 : 32;, } ka0302$r_slot4_lmissaddr_bits;+ } ka0302$r_slot4_lmissaddr_overlay;+ unsigned char ka0302$b_fill1965 [4156]; __union {( unsigned int ka0302$l_slot4_mcr; __struct {3 unsigned ka0302$v_slot4_mcr_fill1 : 32;& } ka0302$r_slot4_mcr_bits;% } ka0302$r_slot4_mcr_overlay;) unsigned char ka0302$b_fill1970 [60]; __union {( unsigned int ka0302$l_slot4_amr; __struct {3 .+unsigned ka0302$v_slot4_amr_fill1 : 32;& } ka0302$r_slot4_amr_bits;% } ka0302$r_slot4_amr_overlay;) unsigned char ka0302$b_fill1980 [60]; __union {* unsigned int ka0302$l_slot4_mstr0; __struct {5 unsigned ka0302$v_slot4_mstr0_fill1 : 32;( } ka0302$r_slot4_mstr0_bits;' } ka0302$r_slot4_mstr0_overlay;) unsigned char ka0302$b_fill1990 [60]; __union {* unsigned int ka0302$l_slot4_mstr1; __stru/+ct {5 unsigned ka0302$v_slot4_mstr1_fill1 : 32;( } ka0302$r_slot4_mstr1_bits;' } ka0302$r_slot4_mstr1_overlay;) unsigned char ka0302$b_fill2000 [60]; __union {) unsigned int ka0302$l_slot4_fadr; __struct {4 unsigned ka0302$v_slot4_fadr_fill1 : 32;' } ka0302$r_slot4_fadr_bits;& } ka0302$r_slot4_fadr_overlay;) unsigned char ka0302$b_fill2010 [60]; __union {) unsigned int ka0302$l_slot4_0+mera; __struct {4 unsigned ka0302$v_slot4_mera_fill1 : 32;' } ka0302$r_slot4_mera_bits;& } ka0302$r_slot4_mera_overlay;) unsigned char ka0302$b_fill2020 [60]; __union {+ unsigned int ka0302$l_slot4_msynda; __struct {6 unsigned ka0302$v_slot4_msynda_fill1 : 32;) } ka0302$r_slot4_msynda_bits;( } ka0302$r_slot4_msynda_overlay;) unsigned char ka0302$b_fill2030 [60]; __union {) un1+signed int ka0302$l_slot4_mdra; __struct {4 unsigned ka0302$v_slot4_mdra_fill1 : 32;' } ka0302$r_slot4_mdra_bits;& } ka0302$r_slot4_mdra_overlay;) unsigned char ka0302$b_fill2040 [60]; __union {* unsigned int ka0302$l_slot4_mcbsa; __struct {5 unsigned ka0302$v_slot4_mcbsa_fill1 : 32;( } ka0302$r_slot4_mcbsa_bits;' } ka0302$r_slot4_mcbsa_overlay;+ unsigned char ka0302$b_fill2050 [7996]; 2+ __union {) unsigned int ka0302$l_slot4_merb; __struct {4 unsigned ka0302$v_slot4_merb_fill1 : 32;' } ka0302$r_slot4_merb_bits;& } ka0302$r_slot4_merb_overlay;) unsigned char ka0302$b_fill2060 [60]; __union {+ unsigned int ka0302$l_slot4_msyndb; __struct {6 unsigned ka0302$v_slot4_msyndb_fill1 : 32;) } ka0302$r_slot4_msyndb_bits;( } ka0302$r_slot4_msyndb_overlay;) unsigned char ka3+0302$b_fill2070 [60]; __union {) unsigned int ka0302$l_slot4_mdrb; __struct {4 unsigned ka0302$v_slot4_mdrb_fill1 : 32;' } ka0302$r_slot4_mdrb_bits;& } ka0302$r_slot4_mdrb_overlay;) unsigned char ka0302$b_fill2080 [60]; __union {* unsigned int ka0302$l_slot4_mcbsb; __struct {5 unsigned ka0302$v_slot4_mcbsb_fill1 : 32;( } ka0302$r_slot4_mcbsb_bits;' } ka0302$r_slot4_mcbsb_overlay;4++ unsigned char ka0302$b_fill2090 [7676]; __union {) unsigned int ka0302$l_slot5_ldev; __struct {4 unsigned ka0302$v_slot5_ldev_dtype : 16;3 unsigned ka0302$v_slot5_ldev_drev : 16;' } ka0302$r_slot5_ldev_bits;& } ka0302$r_slot5_ldev_overlay;) unsigned char ka0302$b_fill2100 [60]; __union {) unsigned int ka0302$l_slot5_lber; __struct {/ unsigned ka0302$v_slot5_lber_e : 1;1 5+ unsigned ka0302$v_slot5_lber_uce : 1;2 unsigned ka0302$v_slot5_lber_uce2 : 1;0 unsigned ka0302$v_slot5_lber_ce : 1;1 unsigned ka0302$v_slot5_lber_ce2 : 1;1 unsigned ka0302$v_slot5_lber_cpe : 1;2 unsigned ka0302$v_slot5_lber_cpe2 : 1;2 unsigned ka0302$v_slot5_lber_cdpe : 1;3 unsigned ka0302$v_slot5_lber_cdpe2 : 1;1 unsigned ka0302$v_slot5_lber_tde : 1;1 unsigned ka0302$v_slot5_lber_ste : 1 6+;2 unsigned ka0302$v_slot5_lber_cnfe : 1;2 unsigned ka0302$v_slot5_lber_nxae : 1;1 unsigned ka0302$v_slot5_lber_cae : 1;1 unsigned ka0302$v_slot5_lber_she : 1;1 unsigned ka0302$v_slot5_lber_die : 1;2 unsigned ka0302$v_slot5_lber_dtce : 1;2 unsigned ka0302$v_slot5_lber_ctce : 1;2 unsigned ka0302$v_slot5_lber_nses : 1;4 unsigned ka0302$v_slot5_lber_fill1 : 13;' } ka0302$r_slot5_lbe 7+r_bits;& } ka0302$r_slot5_lber_overlay;) unsigned char ka0302$b_fill2110 [60]; __union {) unsigned int ka0302$l_slot5_lcnr; __struct {2 unsigned ka0302$v_slot5_lcnr_ceen : 1;4 unsigned ka0302$v_slot5_lcnr_fill1 : 27;5 unsigned ka0302$v_slot5_lcnr_rststat : 1;3 unsigned ka0302$v_slot5_lcnr_nhalt : 1;2 unsigned ka0302$v_slot5_lcnr_nrst : 1;1 unsigned ka0302$v_slot5_lcnr_stf : 1;' 8+ } ka0302$r_slot5_lcnr_bits;& } ka0302$r_slot5_lcnr_overlay;) unsigned char ka0302$b_fill2115 [60]; __union {( unsigned int ka0302$l_slot5_ibr; __struct {5 unsigned ka0302$v_slot5_ibr_rcv_sdat : 1;5 unsigned ka0302$v_slot5_ibr_xmt_sdat : 1;1 unsigned ka0302$v_slot5_ibr_sclk : 1;3 unsigned ka0302$v_slot5_ibr_fill1 : 29;& } ka0302$r_slot5_ibr_bits;% } ka0302$r_slot5_ibr_overlay;* unsigned 9+ char ka0302$b_fill2120 [316]; __union {* unsigned int ka0302$l_slot5_lmmr0; __struct {1 unsigned ka0302$v_slot5_lmmr0_en : 1;2 unsigned ka0302$v_slot5_lmmr0_int : 2;1 unsigned ka0302$v_slot5_lmmr0_ia : 2;1 unsigned ka0302$v_slot5_lmmr0_aw : 4;5 unsigned ka0302$v_slot5_lmmr0_nbanks : 2;4 unsigned ka0302$v_slot5_lmmr0_fill1 : 6;4 unsigned ka0302$v_slot5_lmmr0_addr : 15;( } ka0302 :+$r_slot5_lmmr0_bits;' } ka0302$r_slot5_lmmr0_overlay;) unsigned char ka0302$b_fill2130 [60]; __union {* unsigned int ka0302$l_slot5_lmmr1; __struct {1 unsigned ka0302$v_slot5_lmmr1_en : 1;2 unsigned ka0302$v_slot5_lmmr1_int : 2;1 unsigned ka0302$v_slot5_lmmr1_ia : 2;1 unsigned ka0302$v_slot5_lmmr1_aw : 4;5 unsigned ka0302$v_slot5_lmmr1_nbanks : 2;4 unsigned ka0302$v_slot5_lmmr1_fill1 : 6; ;+4 unsigned ka0302$v_slot5_lmmr1_addr : 15;( } ka0302$r_slot5_lmmr1_bits;' } ka0302$r_slot5_lmmr1_overlay;) unsigned char ka0302$b_fill2140 [60]; __union {* unsigned int ka0302$l_slot5_lmmr2; __struct {1 unsigned ka0302$v_slot5_lmmr2_en : 1;2 unsigned ka0302$v_slot5_lmmr2_int : 2;1 unsigned ka0302$v_slot5_lmmr2_ia : 2;1 unsigned ka0302$v_slot5_lmmr2_aw : 4;5 unsigned ka0302$v_sl <+ot5_lmmr2_nbanks : 2;4 unsigned ka0302$v_slot5_lmmr2_fill1 : 6;4 unsigned ka0302$v_slot5_lmmr2_addr : 15;( } ka0302$r_slot5_lmmr2_bits;' } ka0302$r_slot5_lmmr2_overlay;) unsigned char ka0302$b_fill2150 [60]; __union {* unsigned int ka0302$l_slot5_lmmr3; __struct {1 unsigned ka0302$v_slot5_lmmr3_en : 1;2 unsigned ka0302$v_slot5_lmmr3_int : 2;1 unsigned ka0302$v_slot5_lmmr3_ia : 2;1 =+ unsigned ka0302$v_slot5_lmmr3_aw : 4;5 unsigned ka0302$v_slot5_lmmr3_nbanks : 2;4 unsigned ka0302$v_slot5_lmmr3_fill1 : 6;4 unsigned ka0302$v_slot5_lmmr3_addr : 15;( } ka0302$r_slot5_lmmr3_bits;' } ka0302$r_slot5_lmmr3_overlay;) unsigned char ka0302$b_fill2160 [60]; __union {* unsigned int ka0302$l_slot5_lmmr4; __struct {1 unsigned ka0302$v_slot5_lmmr4_en : 1;2 unsigned ka0302$v_slot5_ >+lmmr4_int : 2;1 unsigned ka0302$v_slot5_lmmr4_ia : 2;1 unsigned ka0302$v_slot5_lmmr4_aw : 4;5 unsigned ka0302$v_slot5_lmmr4_nbanks : 2;4 unsigned ka0302$v_slot5_lmmr4_fill1 : 6;4 unsigned ka0302$v_slot5_lmmr4_addr : 15;( } ka0302$r_slot5_lmmr4_bits;' } ka0302$r_slot5_lmmr4_overlay;) unsigned char ka0302$b_fill2170 [60]; __union {* unsigned int ka0302$l_slot5_lmmr5; __struct {1 ?+unsigned ka0302$v_slot5_lmmr5_en : 1;2 unsigned ka0302$v_slot5_lmmr5_int : 2;1 unsigned ka0302$v_slot5_lmmr5_ia : 2;1 unsigned ka0302$v_slot5_lmmr5_aw : 4;5 unsigned ka0302$v_slot5_lmmr5_nbanks : 2;4 unsigned ka0302$v_slot5_lmmr5_fill1 : 6;4 unsigned ka0302$v_slot5_lmmr5_addr : 15;( } ka0302$r_slot5_lmmr5_bits;' } ka0302$r_slot5_lmmr5_overlay;) unsigned char ka0302$b_fill2180 [60]; __union {* @+ unsigned int ka0302$l_slot5_lmmr6; __struct {1 unsigned ka0302$v_slot5_lmmr6_en : 1;2 unsigned ka0302$v_slot5_lmmr6_int : 2;1 unsigned ka0302$v_slot5_lmmr6_ia : 2;1 unsigned ka0302$v_slot5_lmmr6_aw : 4;5 unsigned ka0302$v_slot5_lmmr6_nbanks : 2;4 unsigned ka0302$v_slot5_lmmr6_fill1 : 6;4 unsigned ka0302$v_slot5_lmmr6_addr : 15;( } ka0302$r_slot5_lmmr6_bits;' } ka0302$r_slot5_lmm A+r6_overlay;) unsigned char ka0302$b_fill2190 [60]; __union {* unsigned int ka0302$l_slot5_lmmr7; __struct {1 unsigned ka0302$v_slot5_lmmr7_en : 1;2 unsigned ka0302$v_slot5_lmmr7_int : 2;1 unsigned ka0302$v_slot5_lmmr7_ia : 2;1 unsigned ka0302$v_slot5_lmmr7_aw : 4;5 unsigned ka0302$v_slot5_lmmr7_nbanks : 2;4 unsigned ka0302$v_slot5_lmmr7_fill1 : 6;4 unsigned ka0302$v_slot5_lmmr7_addr :B+ 15;( } ka0302$r_slot5_lmmr7_bits;' } ka0302$r_slot5_lmmr7_overlay;* unsigned char ka0302$b_fill2200 [572]; __union {+ unsigned int ka0302$l_slot5_lbesr0; __struct {8 unsigned ka0302$v_slot5_lbesr0_syndrome : 7;6 unsigned ka0302$v_slot5_lbesr0_fill1 : 25;) } ka0302$r_slot5_lbesr0_bits;( } ka0302$r_slot5_lbesr0_overlay;) unsigned char ka0302$b_fill2210 [60]; __union {+ unsigned int ka0302$ C+l_slot5_lbesr1; __struct {8 unsigned ka0302$v_slot5_lbesr1_syndrome : 7;6 unsigned ka0302$v_slot5_lbesr1_fill1 : 25;) } ka0302$r_slot5_lbesr1_bits;( } ka0302$r_slot5_lbesr1_overlay;) unsigned char ka0302$b_fill2220 [60]; __union {+ unsigned int ka0302$l_slot5_lbesr2; __struct {8 unsigned ka0302$v_slot5_lbesr2_syndrome : 7;6 unsigned ka0302$v_slot5_lbesr2_fill1 : 25;) } ka0302$r_sD+lot5_lbesr2_bits;( } ka0302$r_slot5_lbesr2_overlay;) unsigned char ka0302$b_fill2230 [60]; __union {+ unsigned int ka0302$l_slot5_lbesr3; __struct {8 unsigned ka0302$v_slot5_lbesr3_syndrome : 7;6 unsigned ka0302$v_slot5_lbesr3_fill1 : 25;) } ka0302$r_slot5_lbesr3_bits;( } ka0302$r_slot5_lbesr3_overlay;) unsigned char ka0302$b_fill2240 [60]; __union {+ unsigned int ka0302$l_slot5_lbecr0; __ E+struct {2 unsigned int ka0302$l_slot5_lbecr0_ca;) } ka0302$r_slot5_lbecr0_bits;( } ka0302$r_slot5_lbecr0_overlay;) unsigned char ka0302$b_fill2250 [60]; __union {+ unsigned int ka0302$l_slot5_lbecr1; __struct {2 unsigned ka0302$v_slot5_lbecr1_ca : 7;3 unsigned ka0302$v_slot5_lbecr1_cid : 4;3 unsigned ka0302$v_slot5_lbecr1_rid : 4;3 unsigned ka0302$v_slot5_lbecr1_cnf : 1;6 un F+signed ka0302$v_slot5_lbecr1_shared : 1;5 unsigned ka0302$v_slot5_lbecr1_dirty : 1;6 unsigned ka0302$v_slot5_lbecr1_dcycle : 2;6 unsigned ka0302$v_slot5_lbecr1_fill1 : 12;) } ka0302$r_slot5_lbecr1_bits;( } ka0302$r_slot5_lbecr1_overlay;+ unsigned char ka0302$b_fill2260 [1212]; __union {* unsigned int ka0302$l_slot5_lmode; __struct {5 unsigned ka0302$v_slot5_lmode_fill1 : 32;( } ka0302$r_sloG+t5_lmode_bits;' } ka0302$r_slot5_lmode_overlay;) unsigned char ka0302$b_fill2270 [60]; __union {* unsigned int ka0302$l_slot5_lmerr; __struct {5 unsigned ka0302$v_slot5_lmerr_fill1 : 32;( } ka0302$r_slot5_lmerr_bits;' } ka0302$r_slot5_lmerr_overlay;) unsigned char ka0302$b_fill2280 [60]; __union {* unsigned int ka0302$l_slot5_llock; __struct {5 unsigned ka0302$v_slot5_llock_fill1 : 32;(H+ } ka0302$r_slot5_llock_bits;' } ka0302$r_slot5_llock_overlay;) unsigned char ka0302$b_fill2290 [60]; __union {* unsigned int ka0302$l_slot5_ledto; __struct {5 unsigned ka0302$v_slot5_ledto_fill1 : 32;( } ka0302$r_slot5_ledto_bits;' } ka0302$r_slot5_ledto_overlay;) unsigned char ka0302$b_fill2300 [60]; __union {* unsigned int ka0302$l_slot5_ldiag; __struct {5 unsigned ka0302$v_I+slot5_ldiag_fill1 : 32;( } ka0302$r_slot5_ldiag_bits;' } ka0302$r_slot5_ldiag_overlay;) unsigned char ka0302$b_fill2310 [60]; __union {* unsigned int ka0302$l_slot5_ltaga; __struct {5 unsigned ka0302$v_slot5_ltaga_fill1 : 32;( } ka0302$r_slot5_ltaga_bits;' } ka0302$r_slot5_ltaga_overlay;) unsigned char ka0302$b_fill2320 [60]; __union {* unsigned int ka0302$l_slot5_ltagw; __struct {5 J+ unsigned ka0302$v_slot5_ltagw_fill1 : 32;( } ka0302$r_slot5_ltagw_bits;' } ka0302$r_slot5_ltagw_overlay;* unsigned char ka0302$b_fill2330 [124]; __union {* unsigned int ka0302$l_slot5_lcon0; __struct {5 unsigned ka0302$v_slot5_lcon0_fill1 : 32;( } ka0302$r_slot5_lcon0_bits;' } ka0302$r_slot5_lcon0_overlay;) unsigned char ka0302$b_fill2340 [60]; __union {* unsigned int ka0302$l_slot5_lcon1;K+ __struct {5 unsigned ka0302$v_slot5_lcon1_fill1 : 32;( } ka0302$r_slot5_lcon1_bits;' } ka0302$r_slot5_lcon1_overlay;* unsigned char ka0302$b_fill2350 [188]; __union {* unsigned int ka0302$l_slot5_lperf; __struct {5 unsigned ka0302$v_slot5_lperf_fill1 : 32;( } ka0302$r_slot5_lperf_bits;' } ka0302$r_slot5_lperf_overlay;) unsigned char ka0302$b_fill2360 [60]; __union {+ unsigned iL+nt ka0302$l_slot5_lcntr0; __struct {6 unsigned ka0302$v_slot5_lcntr0_fill1 : 32;) } ka0302$r_slot5_lcntr0_bits;( } ka0302$r_slot5_lcntr0_overlay;) unsigned char ka0302$b_fill2370 [60]; __union {+ unsigned int ka0302$l_slot5_lcntr1; __struct {6 unsigned ka0302$v_slot5_lcntr1_fill1 : 32;) } ka0302$r_slot5_lcntr1_bits;( } ka0302$r_slot5_lcntr1_overlay;) unsigned char ka0302$b_fill2380 [60];M+ __union {. unsigned int ka0302$l_slot5_lmissaddr; __struct {9 unsigned ka0302$v_slot5_lmissaddr_fill1 : 32;, } ka0302$r_slot5_lmissaddr_bits;+ } ka0302$r_slot5_lmissaddr_overlay;+ unsigned char ka0302$b_fill2385 [4156]; __union {( unsigned int ka0302$l_slot5_mcr; __struct {3 unsigned ka0302$v_slot5_mcr_fill1 : 32;& } ka0302$r_slot5_mcr_bits;% } ka0302$r_slot5_mcr_overlay;) unsiN+gned char ka0302$b_fill2390 [60]; __union {( unsigned int ka0302$l_slot5_amr; __struct {3 unsigned ka0302$v_slot5_amr_fill1 : 32;& } ka0302$r_slot5_amr_bits;% } ka0302$r_slot5_amr_overlay;) unsigned char ka0302$b_fill2400 [60]; __union {* unsigned int ka0302$l_slot5_mstr0; __struct {5 unsigned ka0302$v_slot5_mstr0_fill1 : 32;( } ka0302$r_slot5_mstr0_bits;' } ka0302$r_slot5_mstr0_oO+verlay;) unsigned char ka0302$b_fill2410 [60]; __union {* unsigned int ka0302$l_slot5_mstr1; __struct {5 unsigned ka0302$v_slot5_mstr1_fill1 : 32;( } ka0302$r_slot5_mstr1_bits;' } ka0302$r_slot5_mstr1_overlay;) unsigned char ka0302$b_fill2420 [60]; __union {) unsigned int ka0302$l_slot5_fadr; __struct {4 unsigned ka0302$v_slot5_fadr_fill1 : 32;' } ka0302$r_slot5_fadr_bits;& P+} ka0302$r_slot5_fadr_overlay;) unsigned char ka0302$b_fill2430 [60]; __union {) unsigned int ka0302$l_slot5_mera; __struct {4 unsigned ka0302$v_slot5_mera_fill1 : 32;' } ka0302$r_slot5_mera_bits;& } ka0302$r_slot5_mera_overlay;) unsigned char ka0302$b_fill2440 [60]; __union {+ unsigned int ka0302$l_slot5_msynda; __struct {6 unsigned ka0302$v_slot5_msynda_fill1 : 32;) } ka0302$r_slot5Q+_msynda_bits;( } ka0302$r_slot5_msynda_overlay;) unsigned char ka0302$b_fill2450 [60]; __union {) unsigned int ka0302$l_slot5_mdra; __struct {4 unsigned ka0302$v_slot5_mdra_fill1 : 32;' } ka0302$r_slot5_mdra_bits;& } ka0302$r_slot5_mdra_overlay;) unsigned char ka0302$b_fill2460 [60]; __union {* unsigned int ka0302$l_slot5_mcbsa; __struct {5 unsigned ka0302$v_slot5_mcbsa_fill1 : 32;( R+ } ka0302$r_slot5_mcbsa_bits;' } ka0302$r_slot5_mcbsa_overlay;+ unsigned char ka0302$b_fill2470 [7996]; __union {) unsigned int ka0302$l_slot5_merb; __struct {4 unsigned ka0302$v_slot5_merb_fill1 : 32;' } ka0302$r_slot5_merb_bits;& } ka0302$r_slot5_merb_overlay;) unsigned char ka0302$b_fill2480 [60]; __union {+ unsigned int ka0302$l_slot5_msyndb; __struct {6 unsigned ka0302$v_slotS+5_msyndb_fill1 : 32;) } ka0302$r_slot5_msyndb_bits;( } ka0302$r_slot5_msyndb_overlay;) unsigned char ka0302$b_fill2490 [60]; __union {) unsigned int ka0302$l_slot5_mdrb; __struct {4 unsigned ka0302$v_slot5_mdrb_fill1 : 32;' } ka0302$r_slot5_mdrb_bits;& } ka0302$r_slot5_mdrb_overlay;) unsigned char ka0302$b_fill2500 [60]; __union {* unsigned int ka0302$l_slot5_mcbsb; __struct {5 T+ unsigned ka0302$v_slot5_mcbsb_fill1 : 32;( } ka0302$r_slot5_mcbsb_bits;' } ka0302$r_slot5_mcbsb_overlay;+ unsigned char ka0302$b_fill2510 [7676]; __union {) unsigned int ka0302$l_slot6_ldev; __struct {4 unsigned ka0302$v_slot6_ldev_dtype : 16;3 unsigned ka0302$v_slot6_ldev_drev : 16;' } ka0302$r_slot6_ldev_bits;& } ka0302$r_slot6_ldev_overlay;) unsigned char ka0302$b_fill2520 [60]; __union { U+) unsigned int ka0302$l_slot6_lber; __struct {/ unsigned ka0302$v_slot6_lber_e : 1;1 unsigned ka0302$v_slot6_lber_uce : 1;2 unsigned ka0302$v_slot6_lber_uce2 : 1;0 unsigned ka0302$v_slot6_lber_ce : 1;1 unsigned ka0302$v_slot6_lber_ce2 : 1;1 unsigned ka0302$v_slot6_lber_cpe : 1;2 unsigned ka0302$v_slot6_lber_cpe2 : 1;2 unsigned ka0302$v_slot6_lber_cdpe : 1;3 unsigned ka030 V+2$v_slot6_lber_cdpe2 : 1;1 unsigned ka0302$v_slot6_lber_tde : 1;1 unsigned ka0302$v_slot6_lber_ste : 1;2 unsigned ka0302$v_slot6_lber_cnfe : 1;2 unsigned ka0302$v_slot6_lber_nxae : 1;1 unsigned ka0302$v_slot6_lber_cae : 1;1 unsigned ka0302$v_slot6_lber_she : 1;1 unsigned ka0302$v_slot6_lber_die : 1;2 unsigned ka0302$v_slot6_lber_dtce : 1;2 unsigned ka0302$v_slot6_lber_ctce : 1;2 W+ unsigned ka0302$v_slot6_lber_nses : 1;5 unsigned ka0302$v_slot6__lber_fill1 : 13;' } ka0302$r_slot6_lber_bits;& } ka0302$r_slot6_lber_overlay;) unsigned char ka0302$b_fill2530 [60]; __union {) unsigned int ka0302$l_slot6_lcnr; __struct {2 unsigned ka0302$v_slot6_lcnr_ceen : 1;4 unsigned ka0302$v_slot6_lcnr_fill1 : 27;5 unsigned ka0302$v_slot6_lcnr_rststat : 1;3 unsigned ka0302$v_slot6_lc X+nr_nhalt : 1;2 unsigned ka0302$v_slot6_lcnr_nrst : 1;1 unsigned ka0302$v_slot6_lcnr_stf : 1;' } ka0302$r_slot6_lcnr_bits;& } ka0302$r_slot6_lcnr_overlay;) unsigned char ka0302$b_fill2535 [60]; __union {( unsigned int ka0302$l_slot6_ibr; __struct {5 unsigned ka0302$v_slot6_ibr_rcv_sdat : 1;5 unsigned ka0302$v_slot6_ibr_xmt_sdat : 1;1 unsigned ka0302$v_slot6_ibr_sclk : 1;3 unsi Y+gned ka0302$v_slot6_ibr_fill1 : 29;& } ka0302$r_slot6_ibr_bits;% } ka0302$r_slot6_ibr_overlay;* unsigned char ka0302$b_fill2540 [316]; __union {* unsigned int ka0302$l_slot6_lmmr0; __struct {1 unsigned ka0302$v_slot6_lmmr0_en : 1;2 unsigned ka0302$v_slot6_lmmr0_int : 2;1 unsigned ka0302$v_slot6_lmmr0_ia : 2;1 unsigned ka0302$v_slot6_lmmr0_aw : 4;5 unsigned ka0302$v_slot6_lmmr0_nbanks : 2; Z+4 unsigned ka0302$v_slot6_lmmr0_fill1 : 6;4 unsigned ka0302$v_slot6_lmmr0_addr : 15;( } ka0302$r_slot6_lmmr0_bits;' } ka0302$r_slot6_lmmr0_overlay;) unsigned char ka0302$b_fill2550 [60]; __union {* unsigned int ka0302$l_slot6_lmmr1; __struct {1 unsigned ka0302$v_slot6_lmmr1_en : 1;2 unsigned ka0302$v_slot6_lmmr1_int : 2;1 unsigned ka0302$v_slot6_lmmr1_ia : 2;1 unsigned ka0302$v_ [+slot6_lmmr1_aw : 4;5 unsigned ka0302$v_slot6_lmmr1_nbanks : 2;4 unsigned ka0302$v_slot6_lmmr1_fill1 : 6;4 unsigned ka0302$v_slot6_lmmr1_addr : 15;( } ka0302$r_slot6_lmmr1_bits;' } ka0302$r_slot6_lmmr1_overlay;) unsigned char ka0302$b_fill2560 [60]; __union {* unsigned int ka0302$l_slot6_lmmr2; __struct {1 unsigned ka0302$v_slot6_lmmr2_en : 1;2 unsigned ka0302$v_slot6_lmmr2_int : 2;1 \+ unsigned ka0302$v_slot6_lmmr2_ia : 2;1 unsigned ka0302$v_slot6_lmmr2_aw : 4;5 unsigned ka0302$v_slot6_lmmr2_nbanks : 2;4 unsigned ka0302$v_slot6_lmmr2_fill1 : 6;4 unsigned ka0302$v_slot6_lmmr2_addr : 15;( } ka0302$r_slot6_lmmr2_bits;' } ka0302$r_slot6_lmmr2_overlay;) unsigned char ka0302$b_fill2570 [60]; __union {* unsigned int ka0302$l_slot6_lmmr3; __struct {1 unsigned ka0302$v_slot ]+6_lmmr3_en : 1;2 unsigned ka0302$v_slot6_lmmr3_int : 2;1 unsigned ka0302$v_slot6_lmmr3_ia : 2;1 unsigned ka0302$v_slot6_lmmr3_aw : 4;5 unsigned ka0302$v_slot6_lmmr3_nbanks : 2;4 unsigned ka0302$v_slot6_lmmr3_fill1 : 6;4 unsigned ka0302$v_slot6_lmmr3_addr : 15;( } ka0302$r_slot6_lmmr3_bits;' } ka0302$r_slot6_lmmr3_overlay;) unsigned char ka0302$b_fill2580 [60]; __union {* unsigned int ka0 ^+302$l_slot6_lmmr4; __struct {1 unsigned ka0302$v_slot6_lmmr4_en : 1;2 unsigned ka0302$v_slot6_lmmr4_int : 2;1 unsigned ka0302$v_slot6_lmmr4_ia : 2;1 unsigned ka0302$v_slot6_lmmr4_aw : 4;5 unsigned ka0302$v_slot6_lmmr4_nbanks : 2;4 unsigned ka0302$v_slot6_lmmr4_fill1 : 6;4 unsigned ka0302$v_slot6_lmmr4_addr : 15;( } ka0302$r_slot6_lmmr4_bits;' } ka0302$r_slot6_lmmr4_overlay;) unsi _+gned char ka0302$b_fill2590 [60]; __union {* unsigned int ka0302$l_slot6_lmmr5; __struct {1 unsigned ka0302$v_slot6_lmmr5_en : 1;2 unsigned ka0302$v_slot6_lmmr5_int : 2;1 unsigned ka0302$v_slot6_lmmr5_ia : 2;1 unsigned ka0302$v_slot6_lmmr5_aw : 4;5 unsigned ka0302$v_slot6_lmmr5_nbanks : 2;4 unsigned ka0302$v_slot6_lmmr5_fill1 : 6;4 unsigned ka0302$v_slot6_lmmr5_addr : 15;( } ka `+0302$r_slot6_lmmr5_bits;' } ka0302$r_slot6_lmmr5_overlay;) unsigned char ka0302$b_fill2600 [60]; __union {* unsigned int ka0302$l_slot6_lmmr6; __struct {1 unsigned ka0302$v_slot6_lmmr6_en : 1;2 unsigned ka0302$v_slot6_lmmr6_int : 2;1 unsigned ka0302$v_slot6_lmmr6_ia : 2;1 unsigned ka0302$v_slot6_lmmr6_aw : 4;5 unsigned ka0302$v_slot6_lmmr6_nbanks : 2;4 unsigned ka0302$v_slot6_lmmr6_fill1 a+: 6;4 unsigned ka0302$v_slot6_lmmr6_addr : 15;( } ka0302$r_slot6_lmmr6_bits;' } ka0302$r_slot6_lmmr6_overlay;) unsigned char ka0302$b_fill2610 [60]; __union {* unsigned int ka0302$l_slot6_lmmr7; __struct {1 unsigned ka0302$v_slot6_lmmr7_en : 1;2 unsigned ka0302$v_slot6_lmmr7_int : 2;1 unsigned ka0302$v_slot6_lmmr7_ia : 2;1 unsigned ka0302$v_slot6_lmmr7_aw : 4;5 unsigned ka0302$ b+v_slot6_lmmr7_nbanks : 2;4 unsigned ka0302$v_slot6_lmmr7_fill1 : 6;4 unsigned ka0302$v_slot6_lmmr7_addr : 15;( } ka0302$r_slot6_lmmr7_bits;' } ka0302$r_slot6_lmmr7_overlay;* unsigned char ka0302$b_fill2620 [572]; __union {+ unsigned int ka0302$l_slot6_lbesr0; __struct {8 unsigned ka0302$v_slot6_lbesr0_syndrome : 7;6 unsigned ka0302$v_slot6_lbesr0_fill1 : 25;) } ka0302$r_slot6_lbesr0_bits;(c+ } ka0302$r_slot6_lbesr0_overlay;) unsigned char ka0302$b_fill2630 [60]; __union {+ unsigned int ka0302$l_slot6_lbesr1; __struct {8 unsigned ka0302$v_slot6_lbesr1_syndrome : 7;6 unsigned ka0302$v_slot6_lbesr1_fill1 : 25;) } ka0302$r_slot6_lbesr1_bits;( } ka0302$r_slot6_lbesr1_overlay;) unsigned char ka0302$b_fill2640 [60]; __union {+ unsigned int ka0302$l_slot6_lbesr2; __struct {8 d+ unsigned ka0302$v_slot6_lbesr2_syndrome : 7;6 unsigned ka0302$v_slot6_lbesr2_fill1 : 25;) } ka0302$r_slot6_lbesr2_bits;( } ka0302$r_slot6_lbesr2_overlay;) unsigned char ka0302$b_fill2650 [60]; __union {+ unsigned int ka0302$l_slot6_lbesr3; __struct {8 unsigned ka0302$v_slot6_lbesr3_syndrome : 7;6 unsigned ka0302$v_slot6_lbesr3_fill1 : 25;) } ka0302$r_slot6_lbesr3_bits;( } ka0302$r_slot6_lbee+sr3_overlay;) unsigned char ka0302$b_fill2660 [60]; __union {+ unsigned int ka0302$l_slot6_lbecr0; __struct {2 unsigned int ka0302$l_slot6_lbecr0_ca;) } ka0302$r_slot6_lbecr0_bits;( } ka0302$r_slot6_lbecr0_overlay;) unsigned char ka0302$b_fill2670 [60]; __union {+ unsigned int ka0302$l_slot6_lbecr1; __struct {2 unsigned ka0302$v_slot6_lbecr1_ca : 7;3 unsigned ka0302$v_slot6_lbecr1_cid f+ : 4;3 unsigned ka0302$v_slot6_lbecr1_rid : 4;3 unsigned ka0302$v_slot6_lbecr1_cnf : 1;6 unsigned ka0302$v_slot6_lbecr1_shared : 1;5 unsigned ka0302$v_slot6_lbecr1_dirty : 1;6 unsigned ka0302$v_slot6_lbecr1_dcycle : 2;6 unsigned ka0302$v_slot6_lbecr1_fill1 : 12;) } ka0302$r_slot6_lbecr1_bits;( } ka0302$r_slot6_lbecr1_overlay;+ unsigned char ka0302$b_fill2680 [1212]; __union {* unsigned ig+nt ka0302$l_slot6_lmode; __struct {5 unsigned ka0302$v_slot6_lmode_fill1 : 32;( } ka0302$r_slot6_lmode_bits;' } ka0302$r_slot6_lmode_overlay;) unsigned char ka0302$b_fill2690 [60]; __union {* unsigned int ka0302$l_slot6_lmerr; __struct {5 unsigned ka0302$v_slot6_lmerr_fill1 : 32;( } ka0302$r_slot6_lmerr_bits;' } ka0302$r_slot6_lmerr_overlay;) unsigned char ka0302$b_fill2700 [60]; __unh+ion {* unsigned int ka0302$l_slot6_llock; __struct {5 unsigned ka0302$v_slot6_llock_fill1 : 32;( } ka0302$r_slot6_llock_bits;' } ka0302$r_slot6_llock_overlay;) unsigned char ka0302$b_fill2710 [60]; __union {* unsigned int ka0302$l_slot6_ledto; __struct {5 unsigned ka0302$v_slot6_ledto_fill1 : 32;( } ka0302$r_slot6_ledto_bits;' } ka0302$r_slot6_ledto_overlay;) unsigned char ka0302$bi+_fill2720 [60]; __union {* unsigned int ka0302$l_slot6_ldiag; __struct {5 unsigned ka0302$v_slot6_ldiag_fill1 : 32;( } ka0302$r_slot6_ldiag_bits;' } ka0302$r_slot6_ldiag_overlay;) unsigned char ka0302$b_fill2730 [60]; __union {* unsigned int ka0302$l_slot6_ltaga; __struct {5 unsigned ka0302$v_slot6_ltaga_fill1 : 32;( } ka0302$r_slot6_ltaga_bits;' } ka0302$r_slot6_ltaga_overlay;)j+ unsigned char ka0302$b_fill2740 [60]; __union {* unsigned int ka0302$l_slot6_ltagw; __struct {5 unsigned ka0302$v_slot6_ltagw_fill1 : 32;( } ka0302$r_slot6_ltagw_bits;' } ka0302$r_slot6_ltagw_overlay;* unsigned char ka0302$b_fill2750 [124]; __union {* unsigned int ka0302$l_slot6_lcon0; __struct {5 unsigned ka0302$v_slot6_lcon0_fill1 : 32;( } ka0302$r_slot6_lcon0_bits;' } ka0302k+$r_slot6_lcon0_overlay;) unsigned char ka0302$b_fill2760 [60]; __union {* unsigned int ka0302$l_slot6_lcon1; __struct {5 unsigned ka0302$v_slot6_lcon1_fill1 : 32;( } ka0302$r_slot6_lcon1_bits;' } ka0302$r_slot6_lcon1_overlay;* unsigned char ka0302$b_fill2770 [188]; __union {* unsigned int ka0302$l_slot6_lperf; __struct {5 unsigned ka0302$v_slot6_lperf_fill1 : 32;( } ka0302$r_slot6_lpel+rf_bits;' } ka0302$r_slot6_lperf_overlay;) unsigned char ka0302$b_fill2780 [60]; __union {+ unsigned int ka0302$l_slot6_lcntr0; __struct {6 unsigned ka0302$v_slot6_lcntr0_fill1 : 32;) } ka0302$r_slot6_lcntr0_bits;( } ka0302$r_slot6_lcntr0_overlay;) unsigned char ka0302$b_fill2790 [60]; __union {+ unsigned int ka0302$l_slot6_lcntr1; __struct {6 unsigned ka0302$v_slot6_lcntr1_fill1 : 32;)m+ } ka0302$r_slot6_lcntr1_bits;( } ka0302$r_slot6_lcntr1_overlay;) unsigned char ka0302$b_fill2800 [60]; __union {. unsigned int ka0302$l_slot6_lmissaddr; __struct {9 unsigned ka0302$v_slot6_lmissaddr_fill1 : 32;, } ka0302$r_slot6_lmissaddr_bits;+ } ka0302$r_slot6_lmissaddr_overlay;+ unsigned char ka0302$b_fill2805 [4156]; __union {( unsigned int ka0302$l_slot6_mcr; __struct {3 n+unsigned ka0302$v_slot6_mcr_fill1 : 32;& } ka0302$r_slot6_mcr_bits;% } ka0302$r_slot6_mcr_overlay;) unsigned char ka0302$b_fill2810 [60]; __union {( unsigned int ka0302$l_slot6_amr; __struct {3 unsigned ka0302$v_slot6_amr_fill1 : 32;& } ka0302$r_slot6_amr_bits;% } ka0302$r_slot6_amr_overlay;) unsigned char ka0302$b_fill2820 [60]; __union {* unsigned int ka0302$l_slot6_mstr0; __struct {5 o+ unsigned ka0302$v_slot6_mstr0_fill1 : 32;( } ka0302$r_slot6_mstr0_bits;' } ka0302$r_slot6_mstr0_overlay;) unsigned char ka0302$b_fill2830 [60]; __union {* unsigned int ka0302$l_slot6_mstr1; __struct {5 unsigned ka0302$v_slot6_mstr1_fill1 : 32;( } ka0302$r_slot6_mstr1_bits;' } ka0302$r_slot6_mstr1_overlay;) unsigned char ka0302$b_fill2840 [60]; __union {) unsigned int ka0302$l_slot6_fadrp+; __struct {4 unsigned ka0302$v_slot6_fadr_fill1 : 32;' } ka0302$r_slot6_fadr_bits;& } ka0302$r_slot6_fadr_overlay;) unsigned char ka0302$b_fill2850 [60]; __union {) unsigned int ka0302$l_slot6_mera; __struct {4 unsigned ka0302$v_slot6_mera_fill1 : 32;' } ka0302$r_slot6_mera_bits;& } ka0302$r_slot6_mera_overlay;) unsigned char ka0302$b_fill2860 [60]; __union {+ unsigned int kq+a0302$l_slot6_msynda; __struct {6 unsigned ka0302$v_slot6_msynda_fill1 : 32;) } ka0302$r_slot6_msynda_bits;( } ka0302$r_slot6_msynda_overlay;) unsigned char ka0302$b_fill2870 [60]; __union {) unsigned int ka0302$l_slot6_mdra; __struct {4 unsigned ka0302$v_slot6_mdra_fill1 : 32;' } ka0302$r_slot6_mdra_bits;& } ka0302$r_slot6_mdra_overlay;) unsigned char ka0302$b_fill2880 [60]; __union r+ {* unsigned int ka0302$l_slot6_mcbsa; __struct {5 unsigned ka0302$v_slot6_mcbsa_fill1 : 32;( } ka0302$r_slot6_mcbsa_bits;' } ka0302$r_slot6_mcbsa_overlay;+ unsigned char ka0302$b_fill2890 [7996]; __union {) unsigned int ka0302$l_slot6_merb; __struct {4 unsigned ka0302$v_slot6_merb_fill1 : 32;' } ka0302$r_slot6_merb_bits;& } ka0302$r_slot6_merb_overlay;) unsigned char ka0302$b_fill2s+900 [60]; __union {+ unsigned int ka0302$l_slot6_msyndb; __struct {6 unsigned ka0302$v_slot6_msyndb_fill1 : 32;) } ka0302$r_slot6_msyndb_bits;( } ka0302$r_slot6_msyndb_overlay;) unsigned char ka0302$b_fill2910 [60]; __union {) unsigned int ka0302$l_slot6_mdrb; __struct {4 unsigned ka0302$v_slot6_mdrb_fill1 : 32;' } ka0302$r_slot6_mdrb_bits;& } ka0302$r_slot6_mdrb_overlay;) unt+signed char ka0302$b_fill2920 [60]; __union {* unsigned int ka0302$l_slot6_mcbsb; __struct {5 unsigned ka0302$v_slot6_mcbsb_fill1 : 32;( } ka0302$r_slot6_mcbsb_bits;' } ka0302$r_slot6_mcbsb_overlay;+ unsigned char ka0302$b_fill2930 [7676]; __union {) unsigned int ka0302$l_slot7_ldev; __struct {4 unsigned ka0302$v_slot7_ldev_dtype : 16;3 unsigned ka0302$v_slot7_ldev_drev : 16;' u+ } ka0302$r_slot7_ldev_bits;& } ka0302$r_slot7_ldev_overlay;) unsigned char ka0302$b_fill2940 [60]; __union {) unsigned int ka0302$l_slot7_lber; __struct {/ unsigned ka0302$v_slot7_lber_e : 1;1 unsigned ka0302$v_slot7_lber_uce : 1;2 unsigned ka0302$v_slot7_lber_uce2 : 1;0 unsigned ka0302$v_slot7_lber_ce : 1;1 unsigned ka0302$v_slot7_lber_ce2 : 1;1 unsigned ka0302$v_slot7_lber_cpe : 1;2 v+ unsigned ka0302$v_slot7_lber_cpe2 : 1;2 unsigned ka0302$v_slot7_lber_cdpe : 1;3 unsigned ka0302$v_slot7_lber_cdpe2 : 1;1 unsigned ka0302$v_slot7_lber_tde : 1;1 unsigned ka0302$v_slot7_lber_ste : 1;2 unsigned ka0302$v_slot7_lber_cnfe : 1;2 unsigned ka0302$v_slot7_lber_nxae : 1;1 unsigned ka0302$v_slot7_lber_cae : 1;1 unsigned ka0302$v_slot7_lber_she : 1;1 unsigned ka0302$v_slot7_ w+lber_die : 1;2 unsigned ka0302$v_slot7_lber_dtce : 1;2 unsigned ka0302$v_slot7_lber_ctce : 1;2 unsigned ka0302$v_slot7_lber_nses : 1;4 unsigned ka0302$v_slot7_lber_fill1 : 13;' } ka0302$r_slot7_lber_bits;& } ka0302$r_slot7_lber_overlay;) unsigned char ka0302$b_fill2950 [60]; __union {) unsigned int ka0302$l_slot7_lcnr; __struct {2 unsigned ka0302$v_slot7_lcnr_ceen : 1;4 unsigned x+ ka0302$v_slot7_lcnr_fill1 : 27;5 unsigned ka0302$v_slot7_lcnr_rststat : 1;3 unsigned ka0302$v_slot7_lcnr_nhalt : 1;2 unsigned ka0302$v_slot7_lcnr_nrst : 1;1 unsigned ka0302$v_slot7_lcnr_stf : 1;' } ka0302$r_slot7_lcnr_bits;& } ka0302$r_slot7_lcnr_overlay;) unsigned char ka0302$b_fill2955 [60]; __union {( unsigned int ka0302$l_slot7_ibr; __struct {5 unsigned ka0302$v_slot7_ibr_rcv_sdat : 1 y+;5 unsigned ka0302$v_slot7_ibr_xmt_sdat : 1;1 unsigned ka0302$v_slot7_ibr_sclk : 1;3 unsigned ka0302$v_slot7_ibr_fill1 : 29;& } ka0302$r_slot7_ibr_bits;% } ka0302$r_slot7_ibr_overlay;* unsigned char ka0302$b_fill2960 [316]; __union {* unsigned int ka0302$l_slot7_lmmr0; __struct {1 unsigned ka0302$v_slot7_lmmr0_en : 1;2 unsigned ka0302$v_slot7_lmmr0_int : 2;1 unsigned ka0302$v_ z+slot7_lmmr0_ia : 2;1 unsigned ka0302$v_slot7_lmmr0_aw : 4;5 unsigned ka0302$v_slot7_lmmr0_nbanks : 2;4 unsigned ka0302$v_slot7_lmmr0_fill1 : 6;4 unsigned ka0302$v_slot7_lmmr0_addr : 15;( } ka0302$r_slot7_lmmr0_bits;' } ka0302$r_slot7_lmmr0_overlay;) unsigned char ka0302$b_fill2970 [60]; __union {* unsigned int ka0302$l_slot7_lmmr1; __struct {1 unsigned ka0302$v_slot7_lmmr1_en : 1;2 {+ unsigned ka0302$v_slot7_lmmr1_int : 2;1 unsigned ka0302$v_slot7_lmmr1_ia : 2;1 unsigned ka0302$v_slot7_lmmr1_aw : 4;5 unsigned ka0302$v_slot7_lmmr1_nbanks : 2;4 unsigned ka0302$v_slot7_lmmr1_fill1 : 6;4 unsigned ka0302$v_slot7_lmmr1_addr : 15;( } ka0302$r_slot7_lmmr1_bits;' } ka0302$r_slot7_lmmr1_overlay;) unsigned char ka0302$b_fill2980 [60]; __union {* unsigned int ka0302$l_slot7_lmmr2; |+ __struct {1 unsigned ka0302$v_slot7_lmmr2_en : 1;2 unsigned ka0302$v_slot7_lmmr2_int : 2;1 unsigned ka0302$v_slot7_lmmr2_ia : 2;1 unsigned ka0302$v_slot7_lmmr2_aw : 4;5 unsigned ka0302$v_slot7_lmmr2_nbanks : 2;4 unsigned ka0302$v_slot7_lmmr2_fill1 : 6;4 unsigned ka0302$v_slot7_lmmr2_addr : 15;( } ka0302$r_slot7_lmmr2_bits;' } ka0302$r_slot7_lmmr2_overlay;) unsigned char ka0302$b_fill2 }+990 [60]; __union {* unsigned int ka0302$l_slot7_lmmr3; __struct {1 unsigned ka0302$v_slot7_lmmr3_en : 1;2 unsigned ka0302$v_slot7_lmmr3_int : 2;1 unsigned ka0302$v_slot7_lmmr3_ia : 2;1 unsigned ka0302$v_slot7_lmmr3_aw : 4;5 unsigned ka0302$v_slot7_lmmr3_nbanks : 2;4 unsigned ka0302$v_slot7_lmmr3_fill1 : 6;4 unsigned ka0302$v_slot7_lmmr3_addr : 15;( } ka0302$r_slot7_lmmr3_bits; ~+' } ka0302$r_slot7_lmmr3_overlay;) unsigned char ka0302$b_fill3000 [60]; __union {* unsigned int ka0302$l_slot7_lmmr4; __struct {1 unsigned ka0302$v_slot7_lmmr4_en : 1;2 unsigned ka0302$v_slot7_lmmr4_int : 2;1 unsigned ka0302$v_slot7_lmmr4_ia : 2;1 unsigned ka0302$v_slot7_lmmr4_aw : 4;5 unsigned ka0302$v_slot7_lmmr4_nbanks : 2;4 unsigned ka0302$v_slot7_lmmr4_fill1 : 6;4 unsign +ed ka0302$v_slot7_lmmr4_addr : 15;( } ka0302$r_slot7_lmmr4_bits;' } ka0302$r_slot7_lmmr4_overlay;) unsigned char ka0302$b_fill3010 [60]; __union {* unsigned int ka0302$l_slot7_lmmr5; __struct {1 unsigned ka0302$v_slot7_lmmr5_en : 1;2 unsigned ka0302$v_slot7_lmmr5_int : 2;1 unsigned ka0302$v_slot7_lmmr5_ia : 2;1 unsigned ka0302$v_slot7_lmmr5_aw : 4;5 unsigned ka0302$v_slot7_lmmr5_nbanks : 2 +;4 unsigned ka0302$v_slot7_lmmr5_fill1 : 6;4 unsigned ka0302$v_slot7_lmmr5_addr : 15;( } ka0302$r_slot7_lmmr5_bits;' } ka0302$r_slot7_lmmr5_overlay;) unsigned char ka0302$b_fill3020 [60]; __union {* unsigned int ka0302$l_slot7_lmmr6; __struct {1 unsigned ka0302$v_slot7_lmmr6_en : 1;2 unsigned ka0302$v_slot7_lmmr6_int : 2;1 unsigned ka0302$v_slot7_lmmr6_ia : 2;1 unsigned ka0302$ +v_slot7_lmmr6_aw : 4;5 unsigned ka0302$v_slot7_lmmr6_nbanks : 2;4 unsigned ka0302$v_slot7_lmmr6_fill1 : 6;4 unsigned ka0302$v_slot7_lmmr6_addr : 15;( } ka0302$r_slot7_lmmr6_bits;' } ka0302$r_slot7_lmmr6_overlay;) unsigned char ka0302$b_fill3030 [60]; __union {* unsigned int ka0302$l_slot7_lmmr7; __struct {1 unsigned ka0302$v_slot7_lmmr7_en : 1;2 unsigned ka0302$v_slot7_lmmr7_int : 2;1 + unsigned ka0302$v_slot7_lmmr7_ia : 2;1 unsigned ka0302$v_slot7_lmmr7_aw : 4;5 unsigned ka0302$v_slot7_lmmr7_nbanks : 2;4 unsigned ka0302$v_slot7_lmmr7_fill1 : 6;4 unsigned ka0302$v_slot7_lmmr7_addr : 15;( } ka0302$r_slot7_lmmr7_bits;' } ka0302$r_slot7_lmmr7_overlay;* unsigned char ka0302$b_fill3040 [572]; __union {+ unsigned int ka0302$l_slot7_lbesr0; __struct {8 unsigned ka0302$v_ +slot7_lbesr0_syndrome : 7;6 unsigned ka0302$v_slot7_lbesr0_fill1 : 25;) } ka0302$r_slot7_lbesr0_bits;( } ka0302$r_slot7_lbesr0_overlay;) unsigned char ka0302$b_fill3050 [60]; __union {+ unsigned int ka0302$l_slot7_lbesr1; __struct {8 unsigned ka0302$v_slot7_lbesr1_syndrome : 7;6 unsigned ka0302$v_slot7_lbesr1_fill1 : 25;) } ka0302$r_slot7_lbesr1_bits;( } ka0302$r_slot7_lbesr1_overlay;) unsi+gned char ka0302$b_fill3060 [60]; __union {+ unsigned int ka0302$l_slot7_lbesr2; __struct {8 unsigned ka0302$v_slot7_lbesr2_syndrome : 7;6 unsigned ka0302$v_slot7_lbesr2_fill1 : 25;) } ka0302$r_slot7_lbesr2_bits;( } ka0302$r_slot7_lbesr2_overlay;) unsigned char ka0302$b_fill3070 [60]; __union {+ unsigned int ka0302$l_slot7_lbesr3; __struct {8 unsigned ka0302$v_slot7_lbesr3_syndrome : 7;6 + unsigned ka0302$v_slot7_lbesr3_fill1 : 25;) } ka0302$r_slot7_lbesr3_bits;( } ka0302$r_slot7_lbesr3_overlay;) unsigned char ka0302$b_fill3080 [60]; __union {+ unsigned int ka0302$l_slot7_lbecr0; __struct {2 unsigned int ka0302$l_slot7_lbecr0_ca;) } ka0302$r_slot7_lbecr0_bits;( } ka0302$r_slot7_lbecr0_overlay;) unsigned char ka0302$b_fill3090 [60]; __union {+ unsigned int ka0302$l_slot7_lb +ecr1; __struct {2 unsigned ka0302$v_slot7_lbecr1_ca : 7;3 unsigned ka0302$v_slot7_lbecr1_cid : 4;3 unsigned ka0302$v_slot7_lbecr1_rid : 4;3 unsigned ka0302$v_slot7_lbecr1_cnf : 1;6 unsigned ka0302$v_slot7_lbecr1_shared : 1;5 unsigned ka0302$v_slot7_lbecr1_dirty : 1;6 unsigned ka0302$v_slot7_lbecr1_dcycle : 2;6 unsigned ka0302$v_slot7_lbecr1_fill1 : 12;) } ka0302$r_slot7_lbecr1_bi+ts;( } ka0302$r_slot7_lbecr1_overlay;+ unsigned char ka0302$b_fill3100 [1212]; __union {* unsigned int ka0302$l_slot7_lmode; __struct {5 unsigned ka0302$v_slot7_lmode_fill1 : 32;( } ka0302$r_slot7_lmode_bits;' } ka0302$r_slot7_lmode_overlay;) unsigned char ka0302$b_fill3110 [60]; __union {* unsigned int ka0302$l_slot7_lmerr; __struct {5 unsigned ka0302$v_slot7_lmerr_fill1 : 32;( + } ka0302$r_slot7_lmerr_bits;' } ka0302$r_slot7_lmerr_overlay;) unsigned char ka0302$b_fill3120 [60]; __union {* unsigned int ka0302$l_slot7_llock; __struct {5 unsigned ka0302$v_slot7_llock_fill1 : 32;( } ka0302$r_slot7_llock_bits;' } ka0302$r_slot7_llock_overlay;) unsigned char ka0302$b_fill3130 [60]; __union {* unsigned int ka0302$l_slot7_ledto; __struct {5 unsigned ka0302$v_slot7_le+dto_fill1 : 32;( } ka0302$r_slot7_ledto_bits;' } ka0302$r_slot7_ledto_overlay;) unsigned char ka0302$b_fill3140 [60]; __union {* unsigned int ka0302$l_slot7_ldiag; __struct {5 unsigned ka0302$v_slot7_ldiag_fill1 : 32;( } ka0302$r_slot7_ldiag_bits;' } ka0302$r_slot7_ldiag_overlay;) unsigned char ka0302$b_fill3150 [60]; __union {* unsigned int ka0302$l_slot7_ltaga; __struct {5 +unsigned ka0302$v_slot7_ltaga_fill1 : 32;( } ka0302$r_slot7_ltaga_bits;' } ka0302$r_slot7_ltaga_overlay;) unsigned char ka0302$b_fill3160 [60]; __union {* unsigned int ka0302$l_slot7_ltagw; __struct {5 unsigned ka0302$v_slot7_ltagw_fill1 : 32;( } ka0302$r_slot7_ltagw_bits;' } ka0302$r_slot7_ltagw_overlay;* unsigned char ka0302$b_fill3170 [124]; __union {* unsigned int ka0302$l_slot7_lcon0; +__struct {5 unsigned ka0302$v_slot7_lcon0_fill1 : 32;( } ka0302$r_slot7_lcon0_bits;' } ka0302$r_slot7_lcon0_overlay;) unsigned char ka0302$b_fill3180 [60]; __union {* unsigned int ka0302$l_slot7_lcon1; __struct {5 unsigned ka0302$v_slot7_lcon1_fill1 : 32;( } ka0302$r_slot7_lcon1_bits;' } ka0302$r_slot7_lcon1_overlay;* unsigned char ka0302$b_fill3190 [188]; __union {* unsigned int ka030+2$l_slot7_lperf; __struct {5 unsigned ka0302$v_slot7_lperf_fill1 : 32;( } ka0302$r_slot7_lperf_bits;' } ka0302$r_slot7_lperf_overlay;) unsigned char ka0302$b_fill3200 [60]; __union {+ unsigned int ka0302$l_slot7_lcntr0; __struct {6 unsigned ka0302$v_slot7_lcntr0_fill1 : 32;) } ka0302$r_slot7_lcntr0_bits;( } ka0302$r_slot7_lcntr0_overlay;) unsigned char ka0302$b_fill3210 [60]; __union + {+ unsigned int ka0302$l_slot7_lcntr1; __struct {6 unsigned ka0302$v_slot7_lcntr1_fill1 : 32;) } ka0302$r_slot7_lcntr1_bits;( } ka0302$r_slot7_lcntr1_overlay;) unsigned char ka0302$b_fill3220 [60]; __union {. unsigned int ka0302$l_slot7_lmissaddr; __struct {9 unsigned ka0302$v_slot7_lmissaddr_fill1 : 32;, } ka0302$r_slot7_lmissaddr_bits;+ } ka0302$r_slot7_lmissaddr_overlay;+ unsign+ed char ka0302$b_fill3225 [4156]; __union {( unsigned int ka0302$l_slot7_mcr; __struct {3 unsigned ka0302$v_slot7_mcr_fill1 : 32;& } ka0302$r_slot7_mcr_bits;% } ka0302$r_slot7_mcr_overlay;) unsigned char ka0302$b_fill3230 [60]; __union {( unsigned int ka0302$l_slot7_amr; __struct {3 unsigned ka0302$v_slot7_amr_fill1 : 32;& } ka0302$r_slot7_amr_bits;% } ka0302$r_slot7_amr_overlay;+) unsigned char ka0302$b_fill3240 [60]; __union {* unsigned int ka0302$l_slot7_mstr0; __struct {5 unsigned ka0302$v_slot7_mstr0_fill1 : 32;( } ka0302$r_slot7_mstr0_bits;' } ka0302$r_slot7_mstr0_overlay;) unsigned char ka0302$b_fill3250 [60]; __union {* unsigned int ka0302$l_slot7_mstr1; __struct {5 unsigned ka0302$v_slot7_mstr1_fill1 : 32;( } ka0302$r_slot7_mstr1_bits;' } ka03+02$r_slot7_mstr1_overlay;) unsigned char ka0302$b_fill3260 [60]; __union {) unsigned int ka0302$l_slot7_fadr; __struct {4 unsigned ka0302$v_slot7_fadr_fill1 : 32;' } ka0302$r_slot7_fadr_bits;& } ka0302$r_slot7_fadr_overlay;) unsigned char ka0302$b_fill3270 [60]; __union {) unsigned int ka0302$l_slot7_mera; __struct {4 unsigned ka0302$v_slot7_mera_fill1 : 32;' } ka0302$r_slot7_mera_bi+ts;& } ka0302$r_slot7_mera_overlay;) unsigned char ka0302$b_fill3280 [60]; __union {+ unsigned int ka0302$l_slot7_msynda; __struct {6 unsigned ka0302$v_slot7_msynda_fill1 : 32;) } ka0302$r_slot7_msynda_bits;( } ka0302$r_slot7_msynda_overlay;) unsigned char ka0302$b_fill3290 [60]; __union {) unsigned int ka0302$l_slot7_mdra; __struct {4 unsigned ka0302$v_slot7_mdra_fill1 : 32;' + } ka0302$r_slot7_mdra_bits;& } ka0302$r_slot7_mdra_overlay;) unsigned char ka0302$b_fill3300 [60]; __union {* unsigned int ka0302$l_slot7_mcbsa; __struct {5 unsigned ka0302$v_slot7_mcbsa_fill1 : 32;( } ka0302$r_slot7_mcbsa_bits;' } ka0302$r_slot7_mcbsa_overlay;+ unsigned char ka0302$b_fill3310 [7996]; __union {) unsigned int ka0302$l_slot7_merb; __struct {4 unsigned ka0302$v_slot7_merb+_fill1 : 32;' } ka0302$r_slot7_merb_bits;& } ka0302$r_slot7_merb_overlay;) unsigned char ka0302$b_fill3320 [60]; __union {+ unsigned int ka0302$l_slot7_msyndb; __struct {6 unsigned ka0302$v_slot7_msyndb_fill1 : 32;) } ka0302$r_slot7_msyndb_bits;( } ka0302$r_slot7_msyndb_overlay;) unsigned char ka0302$b_fill3330 [60]; __union {) unsigned int ka0302$l_slot7_mdrb; __struct {4 un+signed ka0302$v_slot7_mdrb_fill1 : 32;' } ka0302$r_slot7_mdrb_bits;& } ka0302$r_slot7_mdrb_overlay;) unsigned char ka0302$b_fill3340 [60]; __union {* unsigned int ka0302$l_slot7_mcbsb; __struct {5 unsigned ka0302$v_slot7_mcbsb_fill1 : 32;( } ka0302$r_slot7_mcbsb_bits;' } ka0302$r_slot7_mcbsb_overlay;+ unsigned char ka0302$b_fill3350 [7676]; __union {) unsigned int ka0302$l_slot8_ldev; __st +ruct {4 unsigned ka0302$v_slot8_ldev_dtype : 16;3 unsigned ka0302$v_slot8_ldev_drev : 16;' } ka0302$r_slot8_ldev_bits;& } ka0302$r_slot8_ldev_overlay;) unsigned char ka0302$b_fill3360 [60]; __union {) unsigned int ka0302$l_slot8_lber; __struct {/ unsigned ka0302$v_slot8_lber_e : 1;1 unsigned ka0302$v_slot8_lber_uce : 1;2 unsigned ka0302$v_slot8_lber_uce2 : 1;0 unsigned ka030 +2$v_slot8_lber_ce : 1;1 unsigned ka0302$v_slot8_lber_ce2 : 1;1 unsigned ka0302$v_slot8_lber_cpe : 1;2 unsigned ka0302$v_slot8_lber_cpe2 : 1;2 unsigned ka0302$v_slot8_lber_cdpe : 1;3 unsigned ka0302$v_slot8_lber_cdpe2 : 1;1 unsigned ka0302$v_slot8_lber_tde : 1;1 unsigned ka0302$v_slot8_lber_ste : 1;2 unsigned ka0302$v_slot8_lber_cnfe : 1;2 unsigned ka0302$v_slot8_lber_nxae : 1;1 +unsigned ka0302$v_slot8_lber_cae : 1;1 unsigned ka0302$v_slot8_lber_she : 1;1 unsigned ka0302$v_slot8_lber_die : 1;2 unsigned ka0302$v_slot8_lber_dtce : 1;2 unsigned ka0302$v_slot8_lber_ctce : 1;2 unsigned ka0302$v_slot8_lber_nses : 1;4 unsigned ka0302$v_slot8_lber_fill1 : 13;' } ka0302$r_slot8_lber_bits;& } ka0302$r_slot8_lber_overlay;) unsigned char ka0302$b_fill3370 [60]; __union {) un +signed int ka0302$l_slot8_lcnr; __struct {2 unsigned ka0302$v_slot8_lcnr_ceen : 1;4 unsigned ka0302$v_slot8_lcnr_fill1 : 27;5 unsigned ka0302$v_slot8_lcnr_rststat : 1;3 unsigned ka0302$v_slot8_lcnr_nhalt : 1;2 unsigned ka0302$v_slot8_lcnr_nrst : 1;1 unsigned ka0302$v_slot8_lcnr_stf : 1;' } ka0302$r_slot8_lcnr_bits;& } ka0302$r_slot8_lcnr_overlay;) unsigned char ka0302$b_fill3375 [60]; +__union {( unsigned int ka0302$l_slot8_ibr; __struct {5 unsigned ka0302$v_slot8_ibr_rcv_sdat : 1;5 unsigned ka0302$v_slot8_ibr_xmt_sdat : 1;1 unsigned ka0302$v_slot8_ibr_sclk : 1;3 unsigned ka0302$v_slot8_ibr_fill1 : 29;& } ka0302$r_slot8_ibr_bits;% } ka0302$r_slot8_ibr_overlay;* unsigned char ka0302$b_fill3380 [316]; __union {* unsigned int ka0302$l_slot8_lmmr0; __struct {1 + unsigned ka0302$v_slot8_lmmr0_en : 1;2 unsigned ka0302$v_slot8_lmmr0_int : 2;1 unsigned ka0302$v_slot8_lmmr0_ia : 2;1 unsigned ka0302$v_slot8_lmmr0_aw : 4;5 unsigned ka0302$v_slot8_lmmr0_nbanks : 2;4 unsigned ka0302$v_slot8_lmmr0_fill1 : 6;4 unsigned ka0302$v_slot8_lmmr0_addr : 15;( } ka0302$r_slot8_lmmr0_bits;' } ka0302$r_slot8_lmmr0_overlay;) unsigned char ka0302$b_fill3390 [60]; __union + {* unsigned int ka0302$l_slot8_lmmr1; __struct {1 unsigned ka0302$v_slot8_lmmr1_en : 1;2 unsigned ka0302$v_slot8_lmmr1_int : 2;1 unsigned ka0302$v_slot8_lmmr1_ia : 2;1 unsigned ka0302$v_slot8_lmmr1_aw : 4;5 unsigned ka0302$v_slot8_lmmr1_nbanks : 2;4 unsigned ka0302$v_slot8_lmmr1_fill1 : 6;4 unsigned ka0302$v_slot8_lmmr1_addr : 15;( } ka0302$r_slot8_lmmr1_bits;' } ka0302$r_slo +t8_lmmr1_overlay;) unsigned char ka0302$b_fill3400 [60]; __union {* unsigned int ka0302$l_slot8_lmmr2; __struct {1 unsigned ka0302$v_slot8_lmmr2_en : 1;2 unsigned ka0302$v_slot8_lmmr2_int : 2;1 unsigned ka0302$v_slot8_lmmr2_ia : 2;1 unsigned ka0302$v_slot8_lmmr2_aw : 4;5 unsigned ka0302$v_slot8_lmmr2_nbanks : 2;4 unsigned ka0302$v_slot8_lmmr2_fill1 : 6;4 unsigned ka0302$v_slot8_lmmr2_ +addr : 15;( } ka0302$r_slot8_lmmr2_bits;' } ka0302$r_slot8_lmmr2_overlay;) unsigned char ka0302$b_fill3410 [60]; __union {* unsigned int ka0302$l_slot8_lmmr3; __struct {1 unsigned ka0302$v_slot8_lmmr3_en : 1;2 unsigned ka0302$v_slot8_lmmr3_int : 2;1 unsigned ka0302$v_slot8_lmmr3_ia : 2;1 unsigned ka0302$v_slot8_lmmr3_aw : 4;5 unsigned ka0302$v_slot8_lmmr3_nbanks : 2;4 unsigned + ka0302$v_slot8_lmmr3_fill1 : 6;4 unsigned ka0302$v_slot8_lmmr3_addr : 15;( } ka0302$r_slot8_lmmr3_bits;' } ka0302$r_slot8_lmmr3_overlay;) unsigned char ka0302$b_fill3420 [60]; __union {* unsigned int ka0302$l_slot8_lmmr4; __struct {1 unsigned ka0302$v_slot8_lmmr4_en : 1;2 unsigned ka0302$v_slot8_lmmr4_int : 2;1 unsigned ka0302$v_slot8_lmmr4_ia : 2;1 unsigned ka0302$v_slot8_lmmr4_aw : 4;5 + unsigned ka0302$v_slot8_lmmr4_nbanks : 2;4 unsigned ka0302$v_slot8_lmmr4_fill1 : 6;4 unsigned ka0302$v_slot8_lmmr4_addr : 15;( } ka0302$r_slot8_lmmr4_bits;' } ka0302$r_slot8_lmmr4_overlay;) unsigned char ka0302$b_fill3430 [60]; __union {* unsigned int ka0302$l_slot8_lmmr5; __struct {1 unsigned ka0302$v_slot8_lmmr5_en : 1;2 unsigned ka0302$v_slot8_lmmr5_int : 2;1 unsigned ka0302$ +v_slot8_lmmr5_ia : 2;1 unsigned ka0302$v_slot8_lmmr5_aw : 4;5 unsigned ka0302$v_slot8_lmmr5_nbanks : 2;4 unsigned ka0302$v_slot8_lmmr5_fill1 : 6;4 unsigned ka0302$v_slot8_lmmr5_addr : 15;( } ka0302$r_slot8_lmmr5_bits;' } ka0302$r_slot8_lmmr5_overlay;) unsigned char ka0302$b_fill3440 [60]; __union {* unsigned int ka0302$l_slot8_lmmr6; __struct {1 unsigned ka0302$v_slot8_lmmr6_en : 1;2 + unsigned ka0302$v_slot8_lmmr6_int : 2;1 unsigned ka0302$v_slot8_lmmr6_ia : 2;1 unsigned ka0302$v_slot8_lmmr6_aw : 4;5 unsigned ka0302$v_slot8_lmmr6_nbanks : 2;4 unsigned ka0302$v_slot8_lmmr6_fill1 : 6;4 unsigned ka0302$v_slot8_lmmr6_addr : 15;( } ka0302$r_slot8_lmmr6_bits;' } ka0302$r_slot8_lmmr6_overlay;) unsigned char ka0302$b_fill3450 [60]; __union {* unsigned int ka0302$l_slot8_lmmr7; + __struct {1 unsigned ka0302$v_slot8_lmmr7_en : 1;2 unsigned ka0302$v_slot8_lmmr7_int : 2;1 unsigned ka0302$v_slot8_lmmr7_ia : 2;1 unsigned ka0302$v_slot8_lmmr7_aw : 4;5 unsigned ka0302$v_slot8_lmmr7_nbanks : 2;4 unsigned ka0302$v_slot8_lmmr7_fill1 : 6;4 unsigned ka0302$v_slot8_lmmr7_addr : 15;( } ka0302$r_slot8_lmmr7_bits;' } ka0302$r_slot8_lmmr7_overlay;* unsigned char ka0302$b_fil+l3460 [572]; __union {+ unsigned int ka0302$l_slot8_lbesr0; __struct {8 unsigned ka0302$v_slot8_lbesr0_syndrome : 7;6 unsigned ka0302$v_slot8_lbesr0_fill1 : 25;) } ka0302$r_slot8_lbesr0_bits;( } ka0302$r_slot8_lbesr0_overlay;) unsigned char ka0302$b_fill3470 [60]; __union {+ unsigned int ka0302$l_slot8_lbesr1; __struct {8 unsigned ka0302$v_slot8_lbesr1_syndrome : 7;6 unsigned k +a0302$v_slot8_lbesr1_fill1 : 25;) } ka0302$r_slot8_lbesr1_bits;( } ka0302$r_slot8_lbesr1_overlay;) unsigned char ka0302$b_fill3480 [60]; __union {+ unsigned int ka0302$l_slot8_lbesr2; __struct {8 unsigned ka0302$v_slot8_lbesr2_syndrome : 7;6 unsigned ka0302$v_slot8_lbesr2_fill1 : 25;) } ka0302$r_slot8_lbesr2_bits;( } ka0302$r_slot8_lbesr2_overlay;) unsigned char ka0302$b_fill3490 [60]; __union { ++ unsigned int ka0302$l_slot8_lbesr3; __struct {8 unsigned ka0302$v_slot8_lbesr3_syndrome : 7;6 unsigned ka0302$v_slot8_lbesr3_fill1 : 25;) } ka0302$r_slot8_lbesr3_bits;( } ka0302$r_slot8_lbesr3_overlay;) unsigned char ka0302$b_fill3500 [60]; __union {+ unsigned int ka0302$l_slot8_lbecr0; __struct {2 unsigned int ka0302$l_slot8_lbecr0_ca;) } ka0302$r_slot8_lbecr0_bits;( } ka +0302$r_slot8_lbecr0_overlay;) unsigned char ka0302$b_fill3510 [60]; __union {+ unsigned int ka0302$l_slot8_lbecr1; __struct {2 unsigned ka0302$v_slot8_lbecr1_ca : 7;3 unsigned ka0302$v_slot8_lbecr1_cid : 4;3 unsigned ka0302$v_slot8_lbecr1_rid : 4;3 unsigned ka0302$v_slot8_lbecr1_cnf : 1;6 unsigned ka0302$v_slot8_lbecr1_shared : 1;5 unsigned ka0302$v_slot8_lbecr1_dirty : 1;6 unsigned k +a0302$v_slot8_lbecr1_dcycle : 2;6 unsigned ka0302$v_slot8_lbecr1_fill1 : 12;) } ka0302$r_slot8_lbecr1_bits;( } ka0302$r_slot8_lbecr1_overlay;* unsigned char ka0302$b_fill3520 [700]; __union {% unsigned int ka0302$l_lilid0; __struct {0 unsigned ka0302$v_lilid0_ident : 16;0 unsigned ka0302$v_lilid0_fill1 : 16;# } ka0302$r_lilid0_bits;" } ka0302$r_lilid0_overlay;) unsigned char ka0302$b_fill353+0 [60]; __union {% unsigned int ka0302$l_lilid1; __struct {0 unsigned ka0302$v_lilid1_ident : 16;0 unsigned ka0302$v_lilid1_fill1 : 16;# } ka0302$r_lilid1_bits;" } ka0302$r_lilid1_overlay;) unsigned char ka0302$b_fill3540 [60]; __union {% unsigned int ka0302$l_lilid2; __struct {0 unsigned ka0302$v_lilid2_ident : 16;0 unsigned ka0302$v_lilid2_fill1 : 16;# } ka0302$r+_lilid2_bits;" } ka0302$r_lilid2_overlay;) unsigned char ka0302$b_fill3550 [60]; __union {% unsigned int ka0302$l_lilid3; __struct {0 unsigned ka0302$v_lilid3_ident : 16;0 unsigned ka0302$v_lilid3_fill1 : 16;# } ka0302$r_lilid3_bits;" } ka0302$r_lilid3_overlay;) unsigned char ka0302$b_fill3560 [60]; __union {' unsigned int ka0302$l_lcpumask; __struct {0 unsigned ka0302$v_lcpu +mask_cpu0 : 4;0 unsigned ka0302$v_lcpumask_cpu1 : 4;0 unsigned ka0302$v_lcpumask_cpu2 : 4;0 unsigned ka0302$v_lcpumask_cpu3 : 4;2 unsigned ka0302$v_lcpumask_fill1 : 16;% } ka0302$r_lcpumask_bits;$ } ka0302$r_lcpumask_overlay;* unsigned char ka0302$b_fill3570 [252]; __union { __int64 ka0302$q_lmbpr; __struct {1 unsigned ka0302$v_lmbpr_fill1_1 : 32;1 unsigned ka0302$v_lmbpr_fill1_ +2 : 32;" } ka0302$r_lmbpr_bits;! } ka0302$r_lmbpr_overlay;+ unsigned char ka0302$b_fill3580 [5112]; __union {% unsigned int ka0302$l_ipcnse; __struct {7 unsigned ka0302$v_ipcnse_mbx_hose0_tip : 1;7 unsigned ka0302$v_ipcnse_mbx_hose1_tip : 1;7 unsigned ka0302$v_ipcnse_mbx_hose2_tip : 1;7 unsigned ka0302$v_ipcnse_mbx_hose3_tip : 1;6 unsigned ka0302$v_ipcnse_uphose0_oflo : 1;6 +unsigned ka0302$v_ipcnse_uphose1_oflo : 1;6 unsigned ka0302$v_ipcnse_uphose2_oflo : 1;6 unsigned ka0302$v_ipcnse_uphose3_oflo : 1;9 unsigned ka0302$v_ipcnse_uphose0_pkt_err : 1;9 unsigned ka0302$v_ipcnse_uphose1_pkt_err : 1;9 unsigned ka0302$v_ipcnse_uphose2_pkt_err : 1;9 unsigned ka0302$v_ipcnse_uphose3_pkt_err : 1;9 unsigned ka0302$v_ipcnse_uphose0_par_err : 1;9 unsigned ka0302$v_ipcnse_uphose1_par_e +rr : 1;9 unsigned ka0302$v_ipcnse_uphose2_par_err : 1;9 unsigned ka0302$v_ipcnse_uphose3_par_err : 1;3 unsigned ka0302$v_ipcnse_up_hic_ie : 1;5 unsigned ka0302$v_ipcnse_ipc_int_err : 1;5 unsigned ka0302$v_ipcnse_up_vrtx_err : 1;5 unsigned ka0302$v_ipcnse_dn_vrtx_err : 1;7 unsigned ka0302$v_ipcnse_mult_intr_err : 1;0 unsigned ka0302$v_ipcnse_fill2 : 10;3 unsigned ka0302$v_ipcnse_intr_nses+ : 1;# } ka0302$r_ipcnse_bits;" } ka0302$r_ipcnse_overlay;) unsigned char ka0302$b_fill3590 [60]; __union {$ unsigned int ka0302$l_ipcvr; __struct {0 unsigned ka0302$v_ipcvr_vector : 16;/ unsigned ka0302$v_ipcvr_fill1 : 16;" } ka0302$r_ipcvr_bits;! } ka0302$r_ipcvr_overlay;) unsigned char ka0302$b_fill3610 [60]; __union {% unsigned int ka0302$l_ipcmsr; __struct {2 + unsigned ka0302$v_ipcmsr_arb_high : 1;1 unsigned ka0302$v_ipcmsr_arb_ctl : 2;0 unsigned ka0302$v_ipcmsr_fill1 : 29;# } ka0302$r_ipcmsr_bits;" } ka0302$r_ipcmsr_overlay;) unsigned char ka0302$b_fill3620 [60]; __union {% unsigned int ka0302$l_ipchst; __struct {2 unsigned ka0302$v_ipchst_h0_error : 1;2 unsigned ka0302$v_ipchst_h0_pwrok : 1;2 unsigned ka0302$v_ipchst_h0_cblok : 1;8 + unsigned ka0302$v_ipchst_h0_pwrok_trans : 1;2 unsigned ka0302$v_ipchst_h1_error : 1;2 unsigned ka0302$v_ipchst_h1_pwrok : 1;2 unsigned ka0302$v_ipchst_h1_cblok : 1;8 unsigned ka0302$v_ipchst_h1_pwrok_trans : 1;2 unsigned ka0302$v_ipchst_h2_error : 1;2 unsigned ka0302$v_ipchst_h2_pwrok : 1;2 unsigned ka0302$v_ipchst_h2_cblok : 1;8 unsigned ka0302$v_ipchst_h2_pwrok_trans : 1;2 unsigned ka0302$v_ +ipchst_h3_error : 1;2 unsigned ka0302$v_ipchst_h3_pwrok : 1;2 unsigned ka0302$v_ipchst_h3_cblok : 1;8 unsigned ka0302$v_ipchst_h3_pwrok_trans : 1;0 unsigned ka0302$v_ipchst_fill4 : 12;3 unsigned ka0302$v_ipchst_hose0_rst : 1;3 unsigned ka0302$v_ipchst_hose1_rst : 1;3 unsigned ka0302$v_ipchst_hose2_rst : 1;3 unsigned ka0302$v_ipchst_hose3_rst : 1;# } ka0302$r_ipchst_bits;" } ka0302$r +_ipchst_overlay;) unsigned char ka0302$b_fill3630 [60]; __union {$ unsigned int ka0302$l_ipcdr; __struct {7 unsigned ka0302$v_ipcdr_frc_dn_ill_cmd : 1;7 unsigned ka0302$v_ipcdr_frc_dn_seq_err : 1;3 unsigned ka0302$v_ipcdr_frc_dn_dpe : 2;. unsigned ka0302$v_ipcdr_fill1 : 6;4 unsigned ka0302$v_ipcdr_dis_lsb_cmd : 1;5 unsigned ka0302$v_ipcdr_hic_lpbck_en : 1;3 unsigned ka0302$v_ipcdr_frc_ +dat_pe : 1;3 unsigned ka0302$v_ipcdr_frc_cmd_pe : 1;. unsigned ka0302$v_ipcdr_fill2 : 8;1 unsigned ka0302$v_ipcdr_frc_cnfe : 1;0 unsigned ka0302$v_ipcdr_frc_cae : 1;1 unsigned ka0302$v_ipcdr_diag_ecc : 7;4 unsigned ka0302$v_ipcdr_diag_ecc_en : 1;" } ka0302$r_ipcdr_bits;! } ka0302$r_ipcdr_overlay;+ unsigned char ka0302$b_fill3650 [7932]; __union {& unsigned int ka0302$l_liointr; +__struct {/ unsigned ka0302$v_liointr_cpu0 : 4;/ unsigned ka0302$v_liointr_cpu1 : 4;/ unsigned ka0302$v_liointr_cpu2 : 4;/ unsigned ka0302$v_liointr_cpu3 : 4;1 unsigned ka0302$v_liointr_fill1 : 16;$ } ka0302$r_liointr_bits;# } ka0302$r_liointr_overlay;) unsigned char ka0302$b_fill3660 [60]; __union {& unsigned int ka0302$l_lipintr; __struct {/ unsigned ka0302$v_lipintr_cpu0 + : 4;/ unsigned ka0302$v_lipintr_cpu1 : 4;/ unsigned ka0302$v_lipintr_cpu2 : 4;/ unsigned ka0302$v_lipintr_cpu3 : 4;1 unsigned ka0302$v_lipintr_fill1 : 16;$ } ka0302$r_lipintr_bits;# } ka0302$r_lipintr_overlay;+ unsigned char ka0302$b_fill3670 [8124]; __union {) unsigned int ka0302$l_uart0a_rr0; __struct {4 unsigned ka0302$v_uart0a_rr0_fill1 : 32;' } ka0302$r_uart0a_rr0_bits+;& } ka0302$r_uart0a_rr0_overlay;) unsigned char ka0302$b_fill3680 [60]; __union {) unsigned int ka0302$l_uart0a_rr8; __struct {4 unsigned ka0302$v_uart0a_rr8_fill1 : 32;' } ka0302$r_uart0a_rr8_bits;& } ka0302$r_uart0a_rr8_overlay;) unsigned char ka0302$b_fill3690 [60]; __union {) unsigned int ka0302$l_uart0b_rr0; __struct {4 unsigned ka0302$v_uart0b_rr0_fill1 : 32;' } ka0302+$r_uart0b_rr0_bits;& } ka0302$r_uart0b_rr0_overlay;) unsigned char ka0302$b_fill3700 [60]; __union {) unsigned int ka0302$l_uart0b_rr8; __struct {4 unsigned ka0302$v_uart0b_rr8_fill1 : 32;' } ka0302$r_uart0b_rr8_bits;& } ka0302$r_uart0b_rr8_overlay;+ unsigned char ka0302$b_fill3710 [7996]; __union { __union {- unsigned int ka0302$l_uart1b_rr0; __struct {8 unsigned k+a0302$v_uart1b_rr0_fill1 : 32;+ } ka0302$r_uart1b_rr0_bits;* } ka0302$r_uart1b_rr0_overlay; __struct {- unsigned int ka0302$l_uart1b_wr0;* } ka0302$r_uart1b_wr0_overlay;# } ka0302$r_uart1b0_overlay;) unsigned char ka0302$b_fill3740 [60]; __union {) unsigned int ka0302$l_uart1b_rr8; __struct {4 unsigned ka0302$v_uart1b_rr8_fill1 : 32;' } ka0302$r_uart1b_rr8_bits;& } +ka0302$r_uart1b_rr8_overlay;) unsigned char ka0302$b_fill3750 [60]; __union {) unsigned int ka0302$l_uart1a_rr0; __struct {4 unsigned ka0302$v_uart1a_rr0_fill1 : 32;' } ka0302$r_uart1a_rr0_bits;& } ka0302$r_uart1a_rr0_overlay;) unsigned char ka0302$b_fill3720 [60]; __union {) unsigned int ka0302$l_uart1a_rr8; __struct {4 unsigned ka0302$v_uart1a_rr8_fill1 : 32;' } ka0302$r_uart1a_rr8_+bits;& } ka0302$r_uart1a_rr8_overlay;+ unsigned char ka0302$b_fill3730 [7996]; __union {) unsigned int ka0302$l_uart2b_rr0; __struct {4 unsigned ka0302$v_uart2b_rr0_fill1 : 32;' } ka0302$r_uart2b_rr0_bits;& } ka0302$r_uart2b_rr0_overlay;) unsigned char ka0302$b_fill3780 [60]; __union {) unsigned int ka0302$l_uart2b_rr8; __struct {4 unsigned ka0302$v_uart2b_rr8_fill1 : 32;' } +ka0302$r_uart2b_rr8_bits;& } ka0302$r_uart2b_rr8_overlay;) unsigned char ka0302$b_fill3790 [60]; __union {) unsigned int ka0302$l_uart2a_rr0; __struct {4 unsigned ka0302$v_uart2a_rr0_fill1 : 32;' } ka0302$r_uart2a_rr0_bits;& } ka0302$r_uart2a_rr0_overlay;) unsigned char ka0302$b_fill3760 [60]; __union {) unsigned int ka0302$l_uart2a_rr8; __struct {4 unsigned ka0302$v_uart2a_rr8_fill1 : 3+2;' } ka0302$r_uart2a_rr8_bits;& } ka0302$r_uart2a_rr8_overlay;+ unsigned char ka0302$b_fill3770 [7996]; __union {, unsigned int ka0302$l_watch_seconds; __struct {7 unsigned ka0302$v_watch_seconds_fill1 : 32;* } ka0302$r_watch_seconds_bits;) } ka0302$r_watch_seconds_overlay;* unsigned char ka0302$b_fill3800 [124]; __union {, unsigned int ka0302$l_watch_minutes; __struct {7 unsi+gned ka0302$v_watch_minutes_fill1 : 32;* } ka0302$r_watch_minutes_bits;) } ka0302$r_watch_minutes_overlay;* unsigned char ka0302$b_fill3810 [124]; __union {* unsigned int ka0302$l_watch_hours; __struct {5 unsigned ka0302$v_watch_hours_fill1 : 32;( } ka0302$r_watch_hours_bits;' } ka0302$r_watch_hours_overlay;* unsigned char ka0302$b_fill3820 [188]; __union {( unsigned int ka0302$l_watch_dom; +__struct {3 unsigned ka0302$v_watch_dom_fill1 : 32;& } ka0302$r_watch_dom_bits;% } ka0302$r_watch_dom_overlay;) unsigned char ka0302$b_fill3830 [60]; __union {* unsigned int ka0302$l_watch_month; __struct {5 unsigned ka0302$v_watch_month_fill1 : 32;( } ka0302$r_watch_month_bits;' } ka0302$r_watch_month_overlay;) unsigned char ka0302$b_fill3840 [60]; __union {) unsigned int ka0302$l_wa+tch_year; __struct {4 unsigned ka0302$v_watch_year_fill1 : 32;' } ka0302$r_watch_year_bits;& } ka0302$r_watch_year_overlay;) unsigned char ka0302$b_fill3850 [60]; __union {) unsigned int ka0302$l_watch_csra; __struct {0 unsigned ka0302$v_watch_csra_rs : 4;0 unsigned ka0302$v_watch_csra_dv : 3;1 unsigned ka0302$v_watch_csra_uip : 1;4 unsigned ka0302$v_watch_csra_fill1 : 24;' + } ka0302$r_watch_csra_bits;& } ka0302$r_watch_csra_overlay;) unsigned char ka0302$b_fill3860 [60]; __union {) unsigned int ka0302$l_watch_csrb; __struct {1 unsigned ka0302$v_watch_csrb_dse : 1;3 unsigned ka0302$v_watch_csrb_24_12 : 1;0 unsigned ka0302$v_watch_csrb_dm : 1;2 unsigned ka0302$v_watch_csrb_sqwe : 1;1 unsigned ka0302$v_watch_csrb_uie : 1;1 unsigned ka0302$v_watch_csrb_a +ie : 1;1 unsigned ka0302$v_watch_csrb_pie : 1;1 unsigned ka0302$v_watch_csrb_set : 1;4 unsigned ka0302$v_watch_csrb_fill1 : 24;' } ka0302$r_watch_csrb_bits;& } ka0302$r_watch_csrb_overlay;) unsigned char ka0302$b_fill3870 [60]; __union {) unsigned int ka0302$l_watch_csrc; __struct {3 unsigned ka0302$v_watch_csrc_fill1 : 4;0 unsigned ka0302$v_watch_csrc_uf : 1;0 unsigned ka030 +2$v_watch_csrc_af : 1;0 unsigned ka0302$v_watch_csrc_pf : 1;2 unsigned ka0302$v_watch_csrc_irqf : 1;4 unsigned ka0302$v_watch_csrc_fill2 : 24;' } ka0302$r_watch_csrc_bits;& } ka0302$r_watch_csrc_overlay;) unsigned char ka0302$b_fill3880 [60]; __union {) unsigned int ka0302$l_watch_csrd; __struct {3 unsigned ka0302$v_watch_csrd_fill1 : 7;1 unsigned ka0302$v_watch_csrd_vrt : 1;4 +unsigned ka0302$v_watch_csrd_fill2 : 24;' } ka0302$r_watch_csrd_bits;& } ka0302$r_watch_csrd_overlay;) unsigned char ka0302$b_fill3890 [60]; __union {( unsigned int ka0302$l_watch_ram; __struct {3 unsigned ka0302$v_watch_ram_fill1 : 32;& } ka0302$r_watch_ram_bits;% } ka0302$r_watch_ram_overlay;+ unsigned char ka0302$b_fill3900 [7292]; __union {) unsigned int ka0302$l_gbus_whami; __struct +{1 unsigned ka0302$v_gbus_whami_nid : 3;1 unsigned ka0302$v_gbus_whami_mfg : 1;5 unsigned ka0302$v_gbus_whami_lsb_bad : 1;4 unsigned ka0302$v_gbus_whami_fill1 : 27;' } ka0302$r_gbus_whami_bits;& } ka0302$r_gbus_whami_overlay;) unsigned char ka0302$b_fill3910 [60]; __union {( unsigned int ka0302$l_gbus_leds; __struct {0 unsigned ka0302$v_gbus_leds_stp : 1;1 unsigned ka0302$v_gb +us_leds_conw : 1;0 unsigned ka0302$v_gbus_leds_run : 1;1 unsigned ka0302$v_gbus_leds_led3 : 1;1 unsigned ka0302$v_gbus_leds_led4 : 1;1 unsigned ka0302$v_gbus_leds_led5 : 1;1 unsigned ka0302$v_gbus_leds_led6 : 1;1 unsigned ka0302$v_gbus_leds_led7 : 1;3 unsigned ka0302$v_gbus_leds_fill1 : 24;& } ka0302$r_gbus_leds_bits;% } ka0302$r_gbus_leds_overlay;) unsigned char ka0302$b_fill3920 [60]; + __union {) unsigned int ka0302$l_gbus_pmask; __struct {4 unsigned ka0302$v_gbus_pmask_halten : 1;5 unsigned ka0302$v_gbus_pmask_selterm : 2;4 unsigned ka0302$v_gbus_pmask_fill1 : 29;' } ka0302$r_gbus_pmask_bits;& } ka0302$r_gbus_pmask_overlay;) unsigned char ka0302$b_fill3930 [60]; __union {( unsigned int ka0302$l_gbus_intr; __struct {5 unsigned ka0302$v_gbus_intr_uartint0 : 1 +;5 unsigned ka0302$v_gbus_intr_uartint1 : 1;1 unsigned ka0302$v_gbus_intr_lsb0 : 1;2 unsigned ka0302$v_gbus_intr_fill1 : 2;1 unsigned ka0302$v_gbus_intr_lsb2 : 1;/ unsigned ka0302$v_gbus_intr_ip : 1;2 unsigned ka0302$v_gbus_intr_intim : 1;3 unsigned ka0302$v_gbus_intr_fill2 : 24;& } ka0302$r_gbus_intr_bits;% } ka0302$r_gbus_intr_overlay;) unsigned char ka0302$b_fill3940 [60]; __unio+n {( unsigned int ka0302$l_gbus_halt; __struct {2 unsigned ka0302$v_gbus_halt_fill1 : 6;2 unsigned ka0302$v_gbus_halt_phalt : 1;2 unsigned ka0302$v_gbus_halt_nhalt : 1;3 unsigned ka0302$v_gbus_halt_fill2 : 24;& } ka0302$r_gbus_halt_bits;% } ka0302$r_gbus_halt_overlay;) unsigned char ka0302$b_fill3950 [60]; __union {* unsigned int ka0302$l_gbus_lsbrst; __struct {5 unsigned+ ka0302$v_gbus_lsbrst_fill1 : 32;( } ka0302$r_gbus_lsbrst_bits;' } ka0302$r_gbus_lsbrst_overlay;) unsigned char ka0302$b_fill3960 [60]; __union {( unsigned int ka0302$l_gbus_misc; __struct {3 unsigned ka0302$v_gbus_misc_expsel : 2;3 unsigned ka0302$v_gbus_misc_fill1 : 30;& } ka0302$r_gbus_misc_bits;% } ka0302$r_gbus_misc_overlay;+ unsigned char ka0302$b_fill3970 [7804]; __union {- unsi +gned int ka0302$l_gbus_rmode_ena; __struct {8 unsigned ka0302$v_gbus_rmode_ena_fill1 : 32;+ } ka0302$r_gbus_rmode_ena_bits;* } ka0302$r_gbus_rmode_ena_overlay;* unsigned char ka0302$b_fill3971 [252];& unsigned int ka0302$l_gbus_ltagrw; } KA0302; #if !defined(__VAXC)K#define ka0302$l_slot0_ldev ka0302$r_slot0_ldev_overlay.ka0302$l_slot0_ldevp#define ka0302$v_slot0_ldev_dtype ka0302$r_slot0_ldev_overlay.ka0302$r_slot0_ldev_bits.ka0302$v_+slot0_ldev_dtypen#define ka0302$v_slot0_ldev_drev ka0302$r_slot0_ldev_overlay.ka0302$r_slot0_ldev_bits.ka0302$v_slot0_ldev_drevK#define ka0302$l_slot0_lber ka0302$r_slot0_lber_overlay.ka0302$l_slot0_lberh#define ka0302$v_slot0_lber_e ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_el#define ka0302$v_slot0_lber_uce ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_ucen#define ka0302$v_slot0_lber_uce2 ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_b+its.ka0302$v_slot0_lber_uce2j#define ka0302$v_slot0_lber_ce ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_cel#define ka0302$v_slot0_lber_ce2 ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_ce2l#define ka0302$v_slot0_lber_cpe ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_cpen#define ka0302$v_slot0_lber_cpe2 ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_cpe2n#define ka0302$v_slot0_lber_cdpe ka0+302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_cdpep#define ka0302$v_slot0_lber_cdpe2 ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_cdpe2l#define ka0302$v_slot0_lber_tde ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_tdel#define ka0302$v_slot0_lber_ste ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_sten#define ka0302$v_slot0_lber_cnfe ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_s+lot0_lber_cnfen#define ka0302$v_slot0_lber_nxae ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_nxael#define ka0302$v_slot0_lber_cae ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_cael#define ka0302$v_slot0_lber_she ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_shel#define ka0302$v_slot0_lber_die ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_dien#define ka0302$v_slot0_lber_dtce ka0302$r_slot0_+lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_dtcen#define ka0302$v_slot0_lber_ctce ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_ctcen#define ka0302$v_slot0_lber_nses ka0302$r_slot0_lber_overlay.ka0302$r_slot0_lber_bits.ka0302$v_slot0_lber_nsesK#define ka0302$l_slot0_lcnr ka0302$r_slot0_lcnr_overlay.ka0302$l_slot0_lcnrn#define ka0302$v_slot0_lcnr_ceen ka0302$r_slot0_lcnr_overlay.ka0302$r_slot0_lcnr_bits.ka0302$v_slot0_lcnr_ceent#define ka0302$v_slot0_lcnr_+rststat ka0302$r_slot0_lcnr_overlay.ka0302$r_slot0_lcnr_bits.ka0302$v_slot0_lcnr_rststatp#define ka0302$v_slot0_lcnr_nhalt ka0302$r_slot0_lcnr_overlay.ka0302$r_slot0_lcnr_bits.ka0302$v_slot0_lcnr_nhaltn#define ka0302$v_slot0_lcnr_nrst ka0302$r_slot0_lcnr_overlay.ka0302$r_slot0_lcnr_bits.ka0302$v_slot0_lcnr_nrstl#define ka0302$v_slot0_lcnr_stf ka0302$r_slot0_lcnr_overlay.ka0302$r_slot0_lcnr_bits.ka0302$v_slot0_lcnr_stfH#define ka0302$l_slot0_ibr ka0302$r_slot0_ibr_overlay.ka0302$l_slot0_ibrr#defin+e ka0302$v_slot0_ibr_rcv_sdat ka0302$r_slot0_ibr_overlay.ka0302$r_slot0_ibr_bits.ka0302$v_slot0_ibr_rcv_sdatr#define ka0302$v_slot0_ibr_xmt_sdat ka0302$r_slot0_ibr_overlay.ka0302$r_slot0_ibr_bits.ka0302$v_slot0_ibr_xmt_sdatj#define ka0302$v_slot0_ibr_sclk ka0302$r_slot0_ibr_overlay.ka0302$r_slot0_ibr_bits.ka0302$v_slot0_ibr_sclkN#define ka0302$l_slot0_lmmr0 ka0302$r_slot0_lmmr0_overlay.ka0302$l_slot0_lmmr0n#define ka0302$v_slot0_lmmr0_en ka0302$r_slot0_lmmr0_overlay.ka0302$r_slot0_lmmr0_bits.ka030+2$v_slot0_lmmr0_enp#define ka0302$v_slot0_lmmr0_int ka0302$r_slot0_lmmr0_overlay.ka0302$r_slot0_lmmr0_bits.ka0302$v_slot0_lmmr0_intn#define ka0302$v_slot0_lmmr0_ia ka0302$r_slot0_lmmr0_overlay.ka0302$r_slot0_lmmr0_bits.ka0302$v_slot0_lmmr0_ian#define ka0302$v_slot0_lmmr0_aw ka0302$r_slot0_lmmr0_overlay.ka0302$r_slot0_lmmr0_bits.ka0302$v_slot0_lmmr0_awv#define ka0302$v_slot0_lmmr0_nbanks ka0302$r_slot0_lmmr0_overlay.ka0302$r_slot0_lmmr0_bits.ka0302$v_slot0_lmmr0_nbanksr#define ka0302$v_slot0_lmmr0+_addr ka0302$r_slot0_lmmr0_overlay.ka0302$r_slot0_lmmr0_bits.ka0302$v_slot0_lmmr0_addrN#define ka0302$l_slot0_lmmr1 ka0302$r_slot0_lmmr1_overlay.ka0302$l_slot0_lmmr1n#define ka0302$v_slot0_lmmr1_en ka0302$r_slot0_lmmr1_overlay.ka0302$r_slot0_lmmr1_bits.ka0302$v_slot0_lmmr1_enp#define ka0302$v_slot0_lmmr1_int ka0302$r_slot0_lmmr1_overlay.ka0302$r_slot0_lmmr1_bits.ka0302$v_slot0_lmmr1_intn#define ka0302$v_slot0_lmmr1_ia ka0302$r_slot0_lmmr1_overlay.ka0302$r_slot0_lmmr1_bits.ka0302$v_slot0_lmmr1_ian+#define ka0302$v_slot0_lmmr1_aw ka0302$r_slot0_lmmr1_overlay.ka0302$r_slot0_lmmr1_bits.ka0302$v_slot0_lmmr1_awv#define ka0302$v_slot0_lmmr1_nbanks ka0302$r_slot0_lmmr1_overlay.ka0302$r_slot0_lmmr1_bits.ka0302$v_slot0_lmmr1_nbanksr#define ka0302$v_slot0_lmmr1_addr ka0302$r_slot0_lmmr1_overlay.ka0302$r_slot0_lmmr1_bits.ka0302$v_slot0_lmmr1_addrN#define ka0302$l_slot0_lmmr2 ka0302$r_slot0_lmmr2_overlay.ka0302$l_slot0_lmmr2n#define ka0302$v_slot0_lmmr2_en ka0302$r_slot0_lmmr2_overlay.ka0302$r_slot0_lm+mr2_bits.ka0302$v_slot0_lmmr2_enp#define ka0302$v_slot0_lmmr2_int ka0302$r_slot0_lmmr2_overlay.ka0302$r_slot0_lmmr2_bits.ka0302$v_slot0_lmmr2_intn#define ka0302$v_slot0_lmmr2_ia ka0302$r_slot0_lmmr2_overlay.ka0302$r_slot0_lmmr2_bits.ka0302$v_slot0_lmmr2_ian#define ka0302$v_slot0_lmmr2_aw ka0302$r_slot0_lmmr2_overlay.ka0302$r_slot0_lmmr2_bits.ka0302$v_slot0_lmmr2_awv#define ka0302$v_slot0_lmmr2_nbanks ka0302$r_slot0_lmmr2_overlay.ka0302$r_slot0_lmmr2_bits.ka0302$v_slot0_lmmr2_nbanksr#define ka0302+$v_slot0_lmmr2_addr ka0302$r_slot0_lmmr2_overlay.ka0302$r_slot0_lmmr2_bits.ka0302$v_slot0_lmmr2_addrN#define ka0302$l_slot0_lmmr3 ka0302$r_slot0_lmmr3_overlay.ka0302$l_slot0_lmmr3n#define ka0302$v_slot0_lmmr3_en ka0302$r_slot0_lmmr3_overlay.ka0302$r_slot0_lmmr3_bits.ka0302$v_slot0_lmmr3_enp#define ka0302$v_slot0_lmmr3_int ka0302$r_slot0_lmmr3_overlay.ka0302$r_slot0_lmmr3_bits.ka0302$v_slot0_lmmr3_intn#define ka0302$v_slot0_lmmr3_ia ka0302$r_slot0_lmmr3_overlay.ka0302$r_slot0_lmmr3_bits.ka0302$v_sl+ot0_lmmr3_ian#define ka0302$v_slot0_lmmr3_aw ka0302$r_slot0_lmmr3_overlay.ka0302$r_slot0_lmmr3_bits.ka0302$v_slot0_lmmr3_awv#define ka0302$v_slot0_lmmr3_nbanks ka0302$r_slot0_lmmr3_overlay.ka0302$r_slot0_lmmr3_bits.ka0302$v_slot0_lmmr3_nbanksr#define ka0302$v_slot0_lmmr3_addr ka0302$r_slot0_lmmr3_overlay.ka0302$r_slot0_lmmr3_bits.ka0302$v_slot0_lmmr3_addrN#define ka0302$l_slot0_lmmr4 ka0302$r_slot0_lmmr4_overlay.ka0302$l_slot0_lmmr4n#define ka0302$v_slot0_lmmr4_en ka0302$r_slot0_lmmr4_overlay.ka0+302$r_slot0_lmmr4_bits.ka0302$v_slot0_lmmr4_enp#define ka0302$v_slot0_lmmr4_int ka0302$r_slot0_lmmr4_overlay.ka0302$r_slot0_lmmr4_bits.ka0302$v_slot0_lmmr4_intn#define ka0302$v_slot0_lmmr4_ia ka0302$r_slot0_lmmr4_overlay.ka0302$r_slot0_lmmr4_bits.ka0302$v_slot0_lmmr4_ian#define ka0302$v_slot0_lmmr4_aw ka0302$r_slot0_lmmr4_overlay.ka0302$r_slot0_lmmr4_bits.ka0302$v_slot0_lmmr4_awv#define ka0302$v_slot0_lmmr4_nbanks ka0302$r_slot0_lmmr4_overlay.ka0302$r_slot0_lmmr4_bits.ka0302$v_slot0_lmmr4_nbanksr+#define ka0302$v_slot0_lmmr4_addr ka0302$r_slot0_lmmr4_overlay.ka0302$r_slot0_lmmr4_bits.ka0302$v_slot0_lmmr4_addrN#define ka0302$l_slot0_lmmr5 ka0302$r_slot0_lmmr5_overlay.ka0302$l_slot0_lmmr5n#define ka0302$v_slot0_lmmr5_en ka0302$r_slot0_lmmr5_overlay.ka0302$r_slot0_lmmr5_bits.ka0302$v_slot0_lmmr5_enp#define ka0302$v_slot0_lmmr5_int ka0302$r_slot0_lmmr5_overlay.ka0302$r_slot0_lmmr5_bits.ka0302$v_slot0_lmmr5_intn#define ka0302$v_slot0_lmmr5_ia ka0302$r_slot0_lmmr5_overlay.ka0302$r_slot0_lmmr5_bi+ts.ka0302$v_slot0_lmmr5_ian#define ka0302$v_slot0_lmmr5_aw ka0302$r_slot0_lmmr5_overlay.ka0302$r_slot0_lmmr5_bits.ka0302$v_slot0_lmmr5_awv#define ka0302$v_slot0_lmmr5_nbanks ka0302$r_slot0_lmmr5_overlay.ka0302$r_slot0_lmmr5_bits.ka0302$v_slot0_lmmr5_nbanksr#define ka0302$v_slot0_lmmr5_addr ka0302$r_slot0_lmmr5_overlay.ka0302$r_slot0_lmmr5_bits.ka0302$v_slot0_lmmr5_addrN#define ka0302$l_slot0_lmmr6 ka0302$r_slot0_lmmr6_overlay.ka0302$l_slot0_lmmr6n#define ka0302$v_slot0_lmmr6_en ka0302$r_slot0_lmm+r6_overlay.ka0302$r_slot0_lmmr6_bits.ka0302$v_slot0_lmmr6_enp#define ka0302$v_slot0_lmmr6_int ka0302$r_slot0_lmmr6_overlay.ka0302$r_slot0_lmmr6_bits.ka0302$v_slot0_lmmr6_intn#define ka0302$v_slot0_lmmr6_ia ka0302$r_slot0_lmmr6_overlay.ka0302$r_slot0_lmmr6_bits.ka0302$v_slot0_lmmr6_ian#define ka0302$v_slot0_lmmr6_aw ka0302$r_slot0_lmmr6_overlay.ka0302$r_slot0_lmmr6_bits.ka0302$v_slot0_lmmr6_awv#define ka0302$v_slot0_lmmr6_nbanks ka0302$r_slot0_lmmr6_overlay.ka0302$r_slot0_lmmr6_bits.ka0302$v_slot0_+lmmr6_nbanksr#define ka0302$v_slot0_lmmr6_addr ka0302$r_slot0_lmmr6_overlay.ka0302$r_slot0_lmmr6_bits.ka0302$v_slot0_lmmr6_addrN#define ka0302$l_slot0_lmmr7 ka0302$r_slot0_lmmr7_overlay.ka0302$l_slot0_lmmr7n#define ka0302$v_slot0_lmmr7_en ka0302$r_slot0_lmmr7_overlay.ka0302$r_slot0_lmmr7_bits.ka0302$v_slot0_lmmr7_enp#define ka0302$v_slot0_lmmr7_int ka0302$r_slot0_lmmr7_overlay.ka0302$r_slot0_lmmr7_bits.ka0302$v_slot0_lmmr7_intn#define ka0302$v_slot0_lmmr7_ia ka0302$r_slot0_lmmr7_overlay.ka0302$r_+slot0_lmmr7_bits.ka0302$v_slot0_lmmr7_ian#define ka0302$v_slot0_lmmr7_aw ka0302$r_slot0_lmmr7_overlay.ka0302$r_slot0_lmmr7_bits.ka0302$v_slot0_lmmr7_awv#define ka0302$v_slot0_lmmr7_nbanks ka0302$r_slot0_lmmr7_overlay.ka0302$r_slot0_lmmr7_bits.ka0302$v_slot0_lmmr7_nbanksr#define ka0302$v_slot0_lmmr7_addr ka0302$r_slot0_lmmr7_overlay.ka0302$r_slot0_lmmr7_bits.ka0302$v_slot0_lmmr7_addrQ#define ka0302$l_slot0_lbesr0 ka0302$r_slot0_lbesr0_overlay.ka0302$l_slot0_lbesr0~#define ka0302$v_slot0_lbesr0_sy+ndrome ka0302$r_slot0_lbesr0_overlay.ka0302$r_slot0_lbesr0_bits.ka0302$v_slot0_lbesr0_syndromeQ#define ka0302$l_slot0_lbesr1 ka0302$r_slot0_lbesr1_overlay.ka0302$l_slot0_lbesr1~#define ka0302$v_slot0_lbesr1_syndrome ka0302$r_slot0_lbesr1_overlay.ka0302$r_slot0_lbesr1_bits.ka0302$v_slot0_lbesr1_syndromeQ#define ka0302$l_slot0_lbesr2 ka0302$r_slot0_lbesr2_overlay.ka0302$l_slot0_lbesr2~#define ka0302$v_slot0_lbesr2_syndrome ka0302$r_slot0_lbesr2_overlay.ka0302$r_slot0_lbesr2_bits.ka0302$v_slot0_lbe+sr2_syndromeQ#define ka0302$l_slot0_lbesr3 ka0302$r_slot0_lbesr3_overlay.ka0302$l_slot0_lbesr3~#define ka0302$v_slot0_lbesr3_syndrome ka0302$r_slot0_lbesr3_overlay.ka0302$r_slot0_lbesr3_bits.ka0302$v_slot0_lbesr3_syndromeQ#define ka0302$l_slot0_lbecr0 ka0302$r_slot0_lbecr0_overlay.ka0302$l_slot0_lbecr0r#define ka0302$l_slot0_lbecr0_ca ka0302$r_slot0_lbecr0_overlay.ka0302$r_slot0_lbecr0_bits.ka0302$l_slot0_lbecr0_caQ#define ka0302$l_slot0_lbecr1 ka0302$r_slot0_lbecr1_overlay.ka0302$l_slot0_lbecr+1r#define ka0302$v_slot0_lbecr1_ca ka0302$r_slot0_lbecr1_overlay.ka0302$r_slot0_lbecr1_bits.ka0302$v_slot0_lbecr1_cat#define ka0302$v_slot0_lbecr1_cid ka0302$r_slot0_lbecr1_overlay.ka0302$r_slot0_lbecr1_bits.ka0302$v_slot0_lbecr1_cidt#define ka0302$v_slot0_lbecr1_rid ka0302$r_slot0_lbecr1_overlay.ka0302$r_slot0_lbecr1_bits.ka0302$v_slot0_lbecr1_ridt#define ka0302$v_slot0_lbecr1_cnf ka0302$r_slot0_lbecr1_overlay.ka0302$r_slot0_lbecr1_bits.ka0302$v_slot0_lbecr1_cnfz#define ka0302$v_slot0_lbecr1_sh+ared ka0302$r_slot0_lbecr1_overlay.ka0302$r_slot0_lbecr1_bits.ka0302$v_slot0_lbecr1_sharedx#define ka0302$v_slot0_lbecr1_dirty ka0302$r_slot0_lbecr1_overlay.ka0302$r_slot0_lbecr1_bits.ka0302$v_slot0_lbecr1_dirtyz#define ka0302$v_slot0_lbecr1_dcycle ka0302$r_slot0_lbecr1_overlay.ka0302$r_slot0_lbecr1_bits.ka0302$v_slot0_lbecr1_dcycleN#define ka0302$l_slot0_lmode ka0302$r_slot0_lmode_overlay.ka0302$l_slot0_lmodeN#define ka0302$l_slot0_lmerr ka0302$r_slot0_lmerr_overlay.ka0302$l_slot0_lmerrN#define +ka0302$l_slot0_llock ka0302$r_slot0_llock_overlay.ka0302$l_slot0_llockN#define ka0302$l_slot0_ledto ka0302$r_slot0_ledto_overlay.ka0302$l_slot0_ledtoN#define ka0302$l_slot0_ldiag ka0302$r_slot0_ldiag_overlay.ka0302$l_slot0_ldiagN#define ka0302$l_slot0_ltaga ka0302$r_slot0_ltaga_overlay.ka0302$l_slot0_ltagaN#define ka0302$l_slot0_ltagw ka0302$r_slot0_ltagw_overlay.ka0302$l_slot0_ltagwN#define ka0302$l_slot0_lcon0 ka0302$r_slot0_lcon0_overlay.ka0302$l_slot0_lcon0N#define ka0302$l_slot0_lcon1 ka030+2$r_slot0_lcon1_overlay.ka0302$l_slot0_lcon1N#define ka0302$l_slot0_lperf ka0302$r_slot0_lperf_overlay.ka0302$l_slot0_lperfQ#define ka0302$l_slot0_lcntr0 ka0302$r_slot0_lcntr0_overlay.ka0302$l_slot0_lcntr0Q#define ka0302$l_slot0_lcntr1 ka0302$r_slot0_lcntr1_overlay.ka0302$l_slot0_lcntr1Z#define ka0302$l_slot0_lmissaddr ka0302$r_slot0_lmissaddr_overlay.ka0302$l_slot0_lmissaddrH#define ka0302$l_slot0_mcr ka0302$r_slot0_mcr_overlay.ka0302$l_slot0_mcrl#define ka0302$v_slot0_mcr_dtype ka0302$r_slot+0_mcr_overlay.ka0302$r_slot0_mcr_bits.ka0302$v_slot0_mcr_dtypej#define ka0302$v_slot0_mcr_strn ka0302$r_slot0_mcr_overlay.ka0302$r_slot0_mcr_bits.ka0302$v_slot0_mcr_strnH#define ka0302$l_slot0_amr ka0302$r_slot0_amr_overlay.ka0302$l_slot0_amrd#define ka0302$v_slot0_amr_e ka0302$r_slot0_amr_overlay.ka0302$r_slot0_amr_bits.ka0302$v_slot0_amr_ej#define ka0302$v_slot0_amr_intl ka0302$r_slot0_amr_overlay.ka0302$r_slot0_amr_bits.ka0302$v_slot0_amr_intlf#define ka0302$v_slot0_amr_ia ka0302$r_slot0_amr_o+verlay.ka0302$r_slot0_amr_bits.ka0302$v_slot0_amr_iaf#define ka0302$v_slot0_amr_aw ka0302$r_slot0_amr_overlay.ka0302$r_slot0_amr_bits.ka0302$v_slot0_amr_awn#define ka0302$v_slot0_amr_nbanks ka0302$r_slot0_amr_overlay.ka0302$r_slot0_amr_bits.ka0302$v_slot0_amr_nbanksj#define ka0302$v_slot0_amr_madr ka0302$r_slot0_amr_overlay.ka0302$r_slot0_amr_bits.ka0302$v_slot0_amr_madrN#define ka0302$l_slot0_mstr0 ka0302$r_slot0_mstr0_overlay.ka0302$l_slot0_mstr0N#define ka0302$l_slot0_mstr1 ka0302$r_slot0_mstr+1_overlay.ka0302$l_slot0_mstr1K#define ka0302$l_slot0_fadr ka0302$r_slot0_fadr_overlay.ka0302$l_slot0_fadrK#define ka0302$l_slot0_mera ka0302$r_slot0_mera_overlay.ka0302$l_slot0_meral#define ka0302$v_slot0_mera_cer ka0302$r_slot0_mera_overlay.ka0302$r_slot0_mera_bits.ka0302$v_slot0_mera_cern#define ka0302$v_slot0_mera_ucer ka0302$r_slot0_mera_overlay.ka0302$r_slot0_mera_bits.ka0302$v_slot0_mera_ucern#define ka0302$v_slot0_mera_mule ka0302$r_slot0_mera_overlay.ka0302$r_slot0_mera_bits.ka0302$v_s+lot0_mera_mulen#define ka0302$v_slot0_mera_aper ka0302$r_slot0_mera_overlay.ka0302$r_slot0_mera_bits.ka0302$v_slot0_mera_apern#define ka0302$v_slot0_mera_cera ka0302$r_slot0_mera_overlay.ka0302$r_slot0_mera_bits.ka0302$v_slot0_mera_ceran#define ka0302$v_slot0_mera_cerb ka0302$r_slot0_mera_overlay.ka0302$r_slot0_mera_bits.ka0302$v_slot0_mera_cerbn#define ka0302$v_slot0_mera_fstr ka0302$r_slot0_mera_overlay.ka0302$r_slot0_mera_bits.ka0302$v_slot0_mera_fstrp#define ka0302$v_slot0_mera_bnker ka0302$r+_slot0_mera_overlay.ka0302$r_slot0_mera_bits.ka0302$v_slot0_mera_bnkerp#define ka0302$v_slot0_mera_ucera ka0302$r_slot0_mera_overlay.ka0302$r_slot0_mera_bits.ka0302$v_slot0_mera_ucerap#define ka0302$v_slot0_mera_ucerb ka0302$r_slot0_mera_overlay.ka0302$r_slot0_mera_bits.ka0302$v_slot0_mera_ucerbQ#define ka0302$l_slot0_msynda ka0302$r_slot0_msynda_overlay.ka0302$l_slot0_msyndav#define ka0302$v_slot0_msynda_synd ka0302$r_slot0_msynda_overlay.ka0302$r_slot0_msynda_bits.ka0302$v_slot0_msynda_syndK#d+efine ka0302$l_slot0_mdra ka0302$r_slot0_mdra_overlay.ka0302$l_slot0_mdran#define ka0302$v_slot0_mdra_fcbs ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_fcbsn#define ka0302$v_slot0_mdra_drdc ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_drdcn#define ka0302$v_slot0_mdra_dwdc ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_dwdcn#define ka0302$v_slot0_mdra_bpas ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v+_slot0_mdra_bpasn#define ka0302$v_slot0_mdra_exst ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_exstn#define ka0302$v_slot0_mdra_stpm ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_stpmn#define ka0302$v_slot0_mdra_mode ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_moden#define ka0302$v_slot0_mdra_igsb ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_igsbn#define ka0302$v_slot0_mdra_frpe ka0302$+r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_frpen#define ka0302$v_slot0_mdra_fcpe ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_fcpen#define ka0302$v_slot0_mdra_dcrd ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_dcrdl#define ka0302$v_slot0_mdra_rfr ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_rfrp#define ka0302$v_slot0_mdra_brfsh ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot+0_mdra_brfshp#define ka0302$v_slot0_mdra_drfsh ka0302$r_slot0_mdra_overlay.ka0302$r_slot0_mdra_bits.ka0302$v_slot0_mdra_drfshN#define ka0302$l_slot0_mcbsa ka0302$r_slot0_mcbsa_overlay.ka0302$l_slot0_mcbsap#define ka0302$v_slot0_mcbsa_scb ka0302$r_slot0_mcbsa_overlay.ka0302$r_slot0_mcbsa_bits.ka0302$v_slot0_mcbsa_scbK#define ka0302$l_slot0_merb ka0302$r_slot0_merb_overlay.ka0302$l_slot0_merbl#define ka0302$v_slot0_merb_cer ka0302$r_slot0_merb_overlay.ka0302$r_slot0_merb_bits.ka0302$v_slot0_merb_c+ern#define ka0302$v_slot0_merb_ucer ka0302$r_slot0_merb_overlay.ka0302$r_slot0_merb_bits.ka0302$v_slot0_merb_ucern#define ka0302$v_slot0_merb_mule ka0302$r_slot0_merb_overlay.ka0302$r_slot0_merb_bits.ka0302$v_slot0_merb_mulen#define ka0302$v_slot0_merb_aper ka0302$r_slot0_merb_overlay.ka0302$r_slot0_merb_bits.ka0302$v_slot0_merb_aperQ#define ka0302$l_slot0_msyndb ka0302$r_slot0_msyndb_overlay.ka0302$l_slot0_msyndbv#define ka0302$v_slot0_msyndb_synd ka0302$r_slot0_msyndb_overlay.ka0302$r_slot0_ms+yndb_bits.ka0302$v_slot0_msyndb_syndK#define ka0302$l_slot0_mdrb ka0302$r_slot0_mdrb_overlay.ka0302$l_slot0_mdrbn#define ka0302$v_slot0_mdrb_fcbs ka0302$r_slot0_mdrb_overlay.ka0302$r_slot0_mdrb_bits.ka0302$v_slot0_mdrb_fcbsn#define ka0302$v_slot0_mdrb_drdc ka0302$r_slot0_mdrb_overlay.ka0302$r_slot0_mdrb_bits.ka0302$v_slot0_mdrb_drdcn#define ka0302$v_slot0_mdrb_dwdc ka0302$r_slot0_mdrb_overlay.ka0302$r_slot0_mdrb_bits.ka0302$v_slot0_mdrb_dwdcn#define ka0302$v_slot0_mdrb_bpas ka0302$r_slot0_mdrb_o+verlay.ka0302$r_slot0_mdrb_bits.ka0302$v_slot0_mdrb_bpasn#define ka0302$v_slot0_mdrb_exst ka0302$r_slot0_mdrb_overlay.ka0302$r_slot0_mdrb_bits.ka0302$v_slot0_mdrb_exstn#define ka0302$v_slot0_mdrb_stpm ka0302$r_slot0_mdrb_overlay.ka0302$r_slot0_mdrb_bits.ka0302$v_slot0_mdrb_stpmn#define ka0302$v_slot0_mdrb_mode ka0302$r_slot0_mdrb_overlay.ka0302$r_slot0_mdrb_bits.ka0302$v_slot0_mdrb_moden#define ka0302$v_slot0_mdrb_igsb ka0302$r_slot0_mdrb_overlay.ka0302$r_slot0_mdrb_bits.ka0302$v_slot0_mdrb_igsbN+#define ka0302$l_slot0_mcbsb ka0302$r_slot0_mcbsb_overlay.ka0302$l_slot0_mcbsbp#define ka0302$v_slot0_mcbsb_scb ka0302$r_slot0_mcbsb_overlay.ka0302$r_slot0_mcbsb_bits.ka0302$v_slot0_mcbsb_scbK#define ka0302$l_slot1_ldev ka0302$r_slot1_ldev_overlay.ka0302$l_slot1_ldevp#define ka0302$v_slot1_ldev_dtype ka0302$r_slot1_ldev_overlay.ka0302$r_slot1_ldev_bits.ka0302$v_slot1_ldev_dtypen#define ka0302$v_slot1_ldev_drev ka0302$r_slot1_ldev_overlay.ka0302$r_slot1_ldev_bits.ka0302$v_slot1_ldev_drevK#define +ka0302$l_slot1_lber ka0302$r_slot1_lber_overlay.ka0302$l_slot1_lberh#define ka0302$v_slot1_lber_e ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_el#define ka0302$v_slot1_lber_uce ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_ucen#define ka0302$v_slot1_lber_uce2 ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_uce2j#define ka0302$v_slot1_lber_ce ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_cel+#define ka0302$v_slot1_lber_ce2 ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_ce2l#define ka0302$v_slot1_lber_cpe ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_cpen#define ka0302$v_slot1_lber_cpe2 ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_cpe2n#define ka0302$v_slot1_lber_cdpe ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_cdpep#define ka0302$v_slot1_lber_cdpe2 ka0302$r_slot1_lber_overlay.+ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_cdpe2l#define ka0302$v_slot1_lber_tde ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_tdel#define ka0302$v_slot1_lber_ste ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_sten#define ka0302$v_slot1_lber_cnfe ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_cnfen#define ka0302$v_slot1_lber_nxae ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_nxael#define ka+0302$v_slot1_lber_cae ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_cael#define ka0302$v_slot1_lber_she ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_shel#define ka0302$v_slot1_lber_die ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_dien#define ka0302$v_slot1_lber_dtce ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_dtcen#define ka0302$v_slot1_lber_ctce ka0302$r_slot1_lber_overlay.ka0302$r_slot+1_lber_bits.ka0302$v_slot1_lber_ctcen#define ka0302$v_slot1_lber_nses ka0302$r_slot1_lber_overlay.ka0302$r_slot1_lber_bits.ka0302$v_slot1_lber_nsesK#define ka0302$l_slot1_lcnr ka0302$r_slot1_lcnr_overlay.ka0302$l_slot1_lcnrn#define ka0302$v_slot1_lcnr_ceen ka0302$r_slot1_lcnr_overlay.ka0302$r_slot1_lcnr_bits.ka0302$v_slot1_lcnr_ceent#define ka0302$v_slot1_lcnr_rststat ka0302$r_slot1_lcnr_overlay.ka0302$r_slot1_lcnr_bits.ka0302$v_slot1_lcnr_rststatp#define ka0302$v_slot1_lcnr_nhalt ka0302$r_slot1+_lcnr_overlay.ka0302$r_slot1_lcnr_bits.ka0302$v_slot1_lcnr_nhaltn#define ka0302$v_slot1_lcnr_nrst ka0302$r_slot1_lcnr_overlay.ka0302$r_slot1_lcnr_bits.ka0302$v_slot1_lcnr_nrstl#define ka0302$v_slot1_lcnr_stf ka0302$r_slot1_lcnr_overlay.ka0302$r_slot1_lcnr_bits.ka0302$v_slot1_lcnr_stfH#define ka0302$l_slot1_ibr ka0302$r_slot1_ibr_overlay.ka0302$l_slot1_ibrr#define ka0302$v_slot1_ibr_rcv_sdat ka0302$r_slot1_ibr_overlay.ka0302$r_slot1_ibr_bits.ka0302$v_slot1_ibr_rcv_sdatr#define ka0302$v_slot1_ibr_x+mt_sdat ka0302$r_slot1_ibr_overlay.ka0302$r_slot1_ibr_bits.ka0302$v_slot1_ibr_xmt_sdatj#define ka0302$v_slot1_ibr_sclk ka0302$r_slot1_ibr_overlay.ka0302$r_slot1_ibr_bits.ka0302$v_slot1_ibr_sclkN#define ka0302$l_slot1_lmmr0 ka0302$r_slot1_lmmr0_overlay.ka0302$l_slot1_lmmr0n#define ka0302$v_slot1_lmmr0_en ka0302$r_slot1_lmmr0_overlay.ka0302$r_slot1_lmmr0_bits.ka0302$v_slot1_lmmr0_enp#define ka0302$v_slot1_lmmr0_int ka0302$r_slot1_lmmr0_overlay.ka0302$r_slot1_lmmr0_bits.ka0302$v_slot1_lmmr0_intn#def+ine ka0302$v_slot1_lmmr0_ia ka0302$r_slot1_lmmr0_overlay.ka0302$r_slot1_lmmr0_bits.ka0302$v_slot1_lmmr0_ian#define ka0302$v_slot1_lmmr0_aw ka0302$r_slot1_lmmr0_overlay.ka0302$r_slot1_lmmr0_bits.ka0302$v_slot1_lmmr0_awv#define ka0302$v_slot1_lmmr0_nbanks ka0302$r_slot1_lmmr0_overlay.ka0302$r_slot1_lmmr0_bits.ka0302$v_slot1_lmmr0_nbanksr#define ka0302$v_slot1_lmmr0_addr ka0302$r_slot1_lmmr0_overlay.ka0302$r_slot1_lmmr0_bits.ka0302$v_slot1_lmmr0_addrN#define ka0302$l_slot1_lmmr1 ka0302$r_slot1_lmmr1_+overlay.ka0302$l_slot1_lmmr1n#define ka0302$v_slot1_lmmr1_en ka0302$r_slot1_lmmr1_overlay.ka0302$r_slot1_lmmr1_bits.ka0302$v_slot1_lmmr1_enp#define ka0302$v_slot1_lmmr1_int ka0302$r_slot1_lmmr1_overlay.ka0302$r_slot1_lmmr1_bits.ka0302$v_slot1_lmmr1_intn#define ka0302$v_slot1_lmmr1_ia ka0302$r_slot1_lmmr1_overlay.ka0302$r_slot1_lmmr1_bits.ka0302$v_slot1_lmmr1_ian#define ka0302$v_slot1_lmmr1_aw ka0302$r_slot1_lmmr1_overlay.ka0302$r_slot1_lmmr1_bits.ka0302$v_slot1_lmmr1_awv#define ka0302$v_slot1_lmm+r1_nbanks ka0302$r_slot1_lmmr1_overlay.ka0302$r_slot1_lmmr1_bits.ka0302$v_slot1_lmmr1_nbanksr#define ka0302$v_slot1_lmmr1_addr ka0302$r_slot1_lmmr1_overlay.ka0302$r_slot1_lmmr1_bits.ka0302$v_slot1_lmmr1_addrN#define ka0302$l_slot1_lmmr2 ka0302$r_slot1_lmmr2_overlay.ka0302$l_slot1_lmmr2n#define ka0302$v_slot1_lmmr2_en ka0302$r_slot1_lmmr2_overlay.ka0302$r_slot1_lmmr2_bits.ka0302$v_slot1_lmmr2_enp#define ka0302$v_slot1_lmmr2_int ka0302$r_slot1_lmmr2_overlay.ka0302$r_slot1_lmmr2_bits.ka0302$v_slot1_l+mmr2_intn#define ka0302$v_slot1_lmmr2_ia ka0302$r_slot1_lmmr2_overlay.ka0302$r_slot1_lmmr2_bits.ka0302$v_slot1_lmmr2_ian#define ka0302$v_slot1_lmmr2_aw ka0302$r_slot1_lmmr2_overlay.ka0302$r_slot1_lmmr2_bits.ka0302$v_slot1_lmmr2_awv#define ka0302$v_slot1_lmmr2_nbanks ka0302$r_slot1_lmmr2_overlay.ka0302$r_slot1_lmmr2_bits.ka0302$v_slot1_lmmr2_nbanksr#define ka0302$v_slot1_lmmr2_addr ka0302$r_slot1_lmmr2_overlay.ka0302$r_slot1_lmmr2_bits.ka0302$v_slot1_lmmr2_addrN#define ka0302$l_slot1_lmmr3 ka0302$+r_slot1_lmmr3_overlay.ka0302$l_slot1_lmmr3n#define ka0302$v_slot1_lmmr3_en ka0302$r_slot1_lmmr3_overlay.ka0302$r_slot1_lmmr3_bits.ka0302$v_slot1_lmmr3_enp#define ka0302$v_slot1_lmmr3_int ka0302$r_slot1_lmmr3_overlay.ka0302$r_slot1_lmmr3_bits.ka0302$v_slot1_lmmr3_intn#define ka0302$v_slot1_lmmr3_ia ka0302$r_slot1_lmmr3_overlay.ka0302$r_slot1_lmmr3_bits.ka0302$v_slot1_lmmr3_ian#define ka0302$v_slot1_lmmr3_aw ka0302$r_slot1_lmmr3_overlay.ka0302$r_slot1_lmmr3_bits.ka0302$v_slot1_lmmr3_awv#define ka03+02$v_slot1_lmmr3_nbanks ka0302$r_slot1_lmmr3_overlay.ka0302$r_slot1_lmmr3_bits.ka0302$v_slot1_lmmr3_nbanksr#define ka0302$v_slot1_lmmr3_addr ka0302$r_slot1_lmmr3_overlay.ka0302$r_slot1_lmmr3_bits.ka0302$v_slot1_lmmr3_addrN#define ka0302$l_slot1_lmmr4 ka0302$r_slot1_lmmr4_overlay.ka0302$l_slot1_lmmr4n#define ka0302$v_slot1_lmmr4_en ka0302$r_slot1_lmmr4_overlay.ka0302$r_slot1_lmmr4_bits.ka0302$v_slot1_lmmr4_enp#define ka0302$v_slot1_lmmr4_int ka0302$r_slot1_lmmr4_overlay.ka0302$r_slot1_lmmr4_bits.ka+0302$v_slot1_lmmr4_intn#define ka0302$v_slot1_lmmr4_ia ka0302$r_slot1_lmmr4_overlay.ka0302$r_slot1_lmmr4_bits.ka0302$v_slot1_lmmr4_ian#define ka0302$v_slot1_lmmr4_aw ka0302$r_slot1_lmmr4_overlay.ka0302$r_slot1_lmmr4_bits.ka0302$v_slot1_lmmr4_awv#define ka0302$v_slot1_lmmr4_nbanks ka0302$r_slot1_lmmr4_overlay.ka0302$r_slot1_lmmr4_bits.ka0302$v_slot1_lmmr4_nbanksr#define ka0302$v_slot1_lmmr4_addr ka0302$r_slot1_lmmr4_overlay.ka0302$r_slot1_lmmr4_bits.ka0302$v_slot1_lmmr4_addrN#define ka0302$l_slot1+_lmmr5 ka0302$r_slot1_lmmr5_overlay.ka0302$l_slot1_lmmr5n#define ka0302$v_slot1_lmmr5_en ka0302$r_slot1_lmmr5_overlay.ka0302$r_slot1_lmmr5_bits.ka0302$v_slot1_lmmr5_enp#define ka0302$v_slot1_lmmr5_int ka0302$r_slot1_lmmr5_overlay.ka0302$r_slot1_lmmr5_bits.ka0302$v_slot1_lmmr5_intn#define ka0302$v_slot1_lmmr5_ia ka0302$r_slot1_lmmr5_overlay.ka0302$r_slot1_lmmr5_bits.ka0302$v_slot1_lmmr5_ian#define ka0302$v_slot1_lmmr5_aw ka0302$r_slot1_lmmr5_overlay.ka0302$r_slot1_lmmr5_bits.ka0302$v_slot1_lmmr5_aw,v#define ka0302$v_slot1_lmmr5_nbanks ka0302$r_slot1_lmmr5_overlay.ka0302$r_slot1_lmmr5_bits.ka0302$v_slot1_lmmr5_nbanksr#define ka0302$v_slot1_lmmr5_addr ka0302$r_slot1_lmmr5_overlay.ka0302$r_slot1_lmmr5_bits.ka0302$v_slot1_lmmr5_addrN#define ka0302$l_slot1_lmmr6 ka0302$r_slot1_lmmr6_overlay.ka0302$l_slot1_lmmr6n#define ka0302$v_slot1_lmmr6_en ka0302$r_slot1_lmmr6_overlay.ka0302$r_slot1_lmmr6_bits.ka0302$v_slot1_lmmr6_enp#define ka0302$v_slot1_lmmr6_int ka0302$r_slot1_lmmr6_overlay.ka0302$r_slot1,_lmmr6_bits.ka0302$v_slot1_lmmr6_intn#define ka0302$v_slot1_lmmr6_ia ka0302$r_slot1_lmmr6_overlay.ka0302$r_slot1_lmmr6_bits.ka0302$v_slot1_lmmr6_ian#define ka0302$v_slot1_lmmr6_aw ka0302$r_slot1_lmmr6_overlay.ka0302$r_slot1_lmmr6_bits.ka0302$v_slot1_lmmr6_awv#define ka0302$v_slot1_lmmr6_nbanks ka0302$r_slot1_lmmr6_overlay.ka0302$r_slot1_lmmr6_bits.ka0302$v_slot1_lmmr6_nbanksr#define ka0302$v_slot1_lmmr6_addr ka0302$r_slot1_lmmr6_overlay.ka0302$r_slot1_lmmr6_bits.ka0302$v_slot1_lmmr6_addrN#define ,ka0302$l_slot1_lmmr7 ka0302$r_slot1_lmmr7_overlay.ka0302$l_slot1_lmmr7n#define ka0302$v_slot1_lmmr7_en ka0302$r_slot1_lmmr7_overlay.ka0302$r_slot1_lmmr7_bits.ka0302$v_slot1_lmmr7_enp#define ka0302$v_slot1_lmmr7_int ka0302$r_slot1_lmmr7_overlay.ka0302$r_slot1_lmmr7_bits.ka0302$v_slot1_lmmr7_intn#define ka0302$v_slot1_lmmr7_ia ka0302$r_slot1_lmmr7_overlay.ka0302$r_slot1_lmmr7_bits.ka0302$v_slot1_lmmr7_ian#define ka0302$v_slot1_lmmr7_aw ka0302$r_slot1_lmmr7_overlay.ka0302$r_slot1_lmmr7_bits.ka0302$v_,slot1_lmmr7_awv#define ka0302$v_slot1_lmmr7_nbanks ka0302$r_slot1_lmmr7_overlay.ka0302$r_slot1_lmmr7_bits.ka0302$v_slot1_lmmr7_nbanksr#define ka0302$v_slot1_lmmr7_addr ka0302$r_slot1_lmmr7_overlay.ka0302$r_slot1_lmmr7_bits.ka0302$v_slot1_lmmr7_addrQ#define ka0302$l_slot1_lbesr0 ka0302$r_slot1_lbesr0_overlay.ka0302$l_slot1_lbesr0~#define ka0302$v_slot1_lbesr0_syndrome ka0302$r_slot1_lbesr0_overlay.ka0302$r_slot1_lbesr0_bits.ka0302$v_slot1_lbesr0_syndromeQ#define ka0302$l_slot1_lbesr1 ka0302$r_slo,t1_lbesr1_overlay.ka0302$l_slot1_lbesr1~#define ka0302$v_slot1_lbesr1_syndrome ka0302$r_slot1_lbesr1_overlay.ka0302$r_slot1_lbesr1_bits.ka0302$v_slot1_lbesr1_syndromeQ#define ka0302$l_slot1_lbesr2 ka0302$r_slot1_lbesr2_overlay.ka0302$l_slot1_lbesr2~#define ka0302$v_slot1_lbesr2_syndrome ka0302$r_slot1_lbesr2_overlay.ka0302$r_slot1_lbesr2_bits.ka0302$v_slot1_lbesr2_syndromeQ#define ka0302$l_slot1_lbesr3 ka0302$r_slot1_lbesr3_overlay.ka0302$l_slot1_lbesr3~#define ka0302$v_slot1_lbesr3_syndrome k,a0302$r_slot1_lbesr3_overlay.ka0302$r_slot1_lbesr3_bits.ka0302$v_slot1_lbesr3_syndromeQ#define ka0302$l_slot1_lbecr0 ka0302$r_slot1_lbecr0_overlay.ka0302$l_slot1_lbecr0r#define ka0302$l_slot1_lbecr0_ca ka0302$r_slot1_lbecr0_overlay.ka0302$r_slot1_lbecr0_bits.ka0302$l_slot1_lbecr0_caQ#define ka0302$l_slot1_lbecr1 ka0302$r_slot1_lbecr1_overlay.ka0302$l_slot1_lbecr1r#define ka0302$v_slot1_lbecr1_ca ka0302$r_slot1_lbecr1_overlay.ka0302$r_slot1_lbecr1_bits.ka0302$v_slot1_lbecr1_cat#define ka0302$v_s,lot1_lbecr1_cid ka0302$r_slot1_lbecr1_overlay.ka0302$r_slot1_lbecr1_bits.ka0302$v_slot1_lbecr1_cidt#define ka0302$v_slot1_lbecr1_rid ka0302$r_slot1_lbecr1_overlay.ka0302$r_slot1_lbecr1_bits.ka0302$v_slot1_lbecr1_ridt#define ka0302$v_slot1_lbecr1_cnf ka0302$r_slot1_lbecr1_overlay.ka0302$r_slot1_lbecr1_bits.ka0302$v_slot1_lbecr1_cnfz#define ka0302$v_slot1_lbecr1_shared ka0302$r_slot1_lbecr1_overlay.ka0302$r_slot1_lbecr1_bits.ka0302$v_slot1_lbecr1_sharedx#define ka0302$v_slot1_lbecr1_dirty ka0302$r_s,lot1_lbecr1_overlay.ka0302$r_slot1_lbecr1_bits.ka0302$v_slot1_lbecr1_dirtyz#define ka0302$v_slot1_lbecr1_dcycle ka0302$r_slot1_lbecr1_overlay.ka0302$r_slot1_lbecr1_bits.ka0302$v_slot1_lbecr1_dcycleN#define ka0302$l_slot1_lmode ka0302$r_slot1_lmode_overlay.ka0302$l_slot1_lmodeN#define ka0302$l_slot1_lmerr ka0302$r_slot1_lmerr_overlay.ka0302$l_slot1_lmerrN#define ka0302$l_slot1_llock ka0302$r_slot1_llock_overlay.ka0302$l_slot1_llockN#define ka0302$l_slot1_ledto ka0302$r_slot1_ledto_overlay.ka0302$l,_slot1_ledtoN#define ka0302$l_slot1_ldiag ka0302$r_slot1_ldiag_overlay.ka0302$l_slot1_ldiagN#define ka0302$l_slot1_ltaga ka0302$r_slot1_ltaga_overlay.ka0302$l_slot1_ltagaN#define ka0302$l_slot1_ltagw ka0302$r_slot1_ltagw_overlay.ka0302$l_slot1_ltagwN#define ka0302$l_slot1_lcon0 ka0302$r_slot1_lcon0_overlay.ka0302$l_slot1_lcon0N#define ka0302$l_slot1_lcon1 ka0302$r_slot1_lcon1_overlay.ka0302$l_slot1_lcon1N#define ka0302$l_slot1_lperf ka0302$r_slot1_lperf_overlay.ka0302$l_slot1_lperfQ#define ka03 ,02$l_slot1_lcntr0 ka0302$r_slot1_lcntr0_overlay.ka0302$l_slot1_lcntr0Q#define ka0302$l_slot1_lcntr1 ka0302$r_slot1_lcntr1_overlay.ka0302$l_slot1_lcntr1Z#define ka0302$l_slot1_lmissaddr ka0302$r_slot1_lmissaddr_overlay.ka0302$l_slot1_lmissaddrH#define ka0302$l_slot1_mcr ka0302$r_slot1_mcr_overlay.ka0302$l_slot1_mcrH#define ka0302$l_slot1_amr ka0302$r_slot1_amr_overlay.ka0302$l_slot1_amrN#define ka0302$l_slot1_mstr0 ka0302$r_slot1_mstr0_overlay.ka0302$l_slot1_mstr0N#define ka0302$l_slot1_mstr1 k ,a0302$r_slot1_mstr1_overlay.ka0302$l_slot1_mstr1K#define ka0302$l_slot1_fadr ka0302$r_slot1_fadr_overlay.ka0302$l_slot1_fadrK#define ka0302$l_slot1_mera ka0302$r_slot1_mera_overlay.ka0302$l_slot1_meraQ#define ka0302$l_slot1_msynda ka0302$r_slot1_msynda_overlay.ka0302$l_slot1_msyndaK#define ka0302$l_slot1_mdra ka0302$r_slot1_mdra_overlay.ka0302$l_slot1_mdraN#define ka0302$l_slot1_mcbsa ka0302$r_slot1_mcbsa_overlay.ka0302$l_slot1_mcbsaK#define ka0302$l_slot1_merb ka0302$r_slot1_merb_overlay.ka ,0302$l_slot1_merbQ#define ka0302$l_slot1_msyndb ka0302$r_slot1_msyndb_overlay.ka0302$l_slot1_msyndbK#define ka0302$l_slot1_mdrb ka0302$r_slot1_mdrb_overlay.ka0302$l_slot1_mdrbN#define ka0302$l_slot1_mcbsb ka0302$r_slot1_mcbsb_overlay.ka0302$l_slot1_mcbsbK#define ka0302$l_slot2_ldev ka0302$r_slot2_ldev_overlay.ka0302$l_slot2_ldevp#define ka0302$v_slot2_ldev_dtype ka0302$r_slot2_ldev_overlay.ka0302$r_slot2_ldev_bits.ka0302$v_slot2_ldev_dtypen#define ka0302$v_slot2_ldev_drev ka0302$r_slot2_ldev ,_overlay.ka0302$r_slot2_ldev_bits.ka0302$v_slot2_ldev_drevK#define ka0302$l_slot2_lber ka0302$r_slot2_lber_overlay.ka0302$l_slot2_lberh#define ka0302$v_slot2_lber_e ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_el#define ka0302$v_slot2_lber_uce ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_ucen#define ka0302$v_slot2_lber_uce2 ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_uce2j#define ka0302$v_slot2_lber_ce ka0302$r_ ,slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_cel#define ka0302$v_slot2_lber_ce2 ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_ce2l#define ka0302$v_slot2_lber_cpe ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_cpen#define ka0302$v_slot2_lber_cpe2 ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_cpe2n#define ka0302$v_slot2_lber_cdpe ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_,cdpep#define ka0302$v_slot2_lber_cdpe2 ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_cdpe2l#define ka0302$v_slot2_lber_tde ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_tdel#define ka0302$v_slot2_lber_ste ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_sten#define ka0302$v_slot2_lber_cnfe ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_cnfen#define ka0302$v_slot2_lber_nxae ka0302$r_slot2_lber_o,verlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_nxael#define ka0302$v_slot2_lber_cae ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_cael#define ka0302$v_slot2_lber_she ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_shel#define ka0302$v_slot2_lber_die ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_dien#define ka0302$v_slot2_lber_dtce ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_dtcen#defin,e ka0302$v_slot2_lber_ctce ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_ctcen#define ka0302$v_slot2_lber_nses ka0302$r_slot2_lber_overlay.ka0302$r_slot2_lber_bits.ka0302$v_slot2_lber_nsesK#define ka0302$l_slot2_lcnr ka0302$r_slot2_lcnr_overlay.ka0302$l_slot2_lcnrn#define ka0302$v_slot2_lcnr_ceen ka0302$r_slot2_lcnr_overlay.ka0302$r_slot2_lcnr_bits.ka0302$v_slot2_lcnr_ceent#define ka0302$v_slot2_lcnr_rststat ka0302$r_slot2_lcnr_overlay.ka0302$r_slot2_lcnr_bits.ka0302$v_,slot2_lcnr_rststatp#define ka0302$v_slot2_lcnr_nhalt ka0302$r_slot2_lcnr_overlay.ka0302$r_slot2_lcnr_bits.ka0302$v_slot2_lcnr_nhaltn#define ka0302$v_slot2_lcnr_nrst ka0302$r_slot2_lcnr_overlay.ka0302$r_slot2_lcnr_bits.ka0302$v_slot2_lcnr_nrstl#define ka0302$v_slot2_lcnr_stf ka0302$r_slot2_lcnr_overlay.ka0302$r_slot2_lcnr_bits.ka0302$v_slot2_lcnr_stfH#define ka0302$l_slot2_ibr ka0302$r_slot2_ibr_overlay.ka0302$l_slot2_ibrr#define ka0302$v_slot2_ibr_rcv_sdat ka0302$r_slot2_ibr_overlay.ka0302$r_slot,2_ibr_bits.ka0302$v_slot2_ibr_rcv_sdatr#define ka0302$v_slot2_ibr_xmt_sdat ka0302$r_slot2_ibr_overlay.ka0302$r_slot2_ibr_bits.ka0302$v_slot2_ibr_xmt_sdatj#define ka0302$v_slot2_ibr_sclk ka0302$r_slot2_ibr_overlay.ka0302$r_slot2_ibr_bits.ka0302$v_slot2_ibr_sclkN#define ka0302$l_slot2_lmmr0 ka0302$r_slot2_lmmr0_overlay.ka0302$l_slot2_lmmr0n#define ka0302$v_slot2_lmmr0_en ka0302$r_slot2_lmmr0_overlay.ka0302$r_slot2_lmmr0_bits.ka0302$v_slot2_lmmr0_enp#define ka0302$v_slot2_lmmr0_int ka0302$r_slot2_lm,mr0_overlay.ka0302$r_slot2_lmmr0_bits.ka0302$v_slot2_lmmr0_intn#define ka0302$v_slot2_lmmr0_ia ka0302$r_slot2_lmmr0_overlay.ka0302$r_slot2_lmmr0_bits.ka0302$v_slot2_lmmr0_ian#define ka0302$v_slot2_lmmr0_aw ka0302$r_slot2_lmmr0_overlay.ka0302$r_slot2_lmmr0_bits.ka0302$v_slot2_lmmr0_awv#define ka0302$v_slot2_lmmr0_nbanks ka0302$r_slot2_lmmr0_overlay.ka0302$r_slot2_lmmr0_bits.ka0302$v_slot2_lmmr0_nbanksr#define ka0302$v_slot2_lmmr0_addr ka0302$r_slot2_lmmr0_overlay.ka0302$r_slot2_lmmr0_bits.ka0302$v_,slot2_lmmr0_addrN#define ka0302$l_slot2_lmmr1 ka0302$r_slot2_lmmr1_overlay.ka0302$l_slot2_lmmr1n#define ka0302$v_slot2_lmmr1_en ka0302$r_slot2_lmmr1_overlay.ka0302$r_slot2_lmmr1_bits.ka0302$v_slot2_lmmr1_enp#define ka0302$v_slot2_lmmr1_int ka0302$r_slot2_lmmr1_overlay.ka0302$r_slot2_lmmr1_bits.ka0302$v_slot2_lmmr1_intn#define ka0302$v_slot2_lmmr1_ia ka0302$r_slot2_lmmr1_overlay.ka0302$r_slot2_lmmr1_bits.ka0302$v_slot2_lmmr1_ian#define ka0302$v_slot2_lmmr1_aw ka0302$r_slot2_lmmr1_overlay.ka0302$r_,slot2_lmmr1_bits.ka0302$v_slot2_lmmr1_awv#define ka0302$v_slot2_lmmr1_nbanks ka0302$r_slot2_lmmr1_overlay.ka0302$r_slot2_lmmr1_bits.ka0302$v_slot2_lmmr1_nbanksr#define ka0302$v_slot2_lmmr1_addr ka0302$r_slot2_lmmr1_overlay.ka0302$r_slot2_lmmr1_bits.ka0302$v_slot2_lmmr1_addrN#define ka0302$l_slot2_lmmr2 ka0302$r_slot2_lmmr2_overlay.ka0302$l_slot2_lmmr2n#define ka0302$v_slot2_lmmr2_en ka0302$r_slot2_lmmr2_overlay.ka0302$r_slot2_lmmr2_bits.ka0302$v_slot2_lmmr2_enp#define ka0302$v_slot2_lmmr2_int ka0,302$r_slot2_lmmr2_overlay.ka0302$r_slot2_lmmr2_bits.ka0302$v_slot2_lmmr2_intn#define ka0302$v_slot2_lmmr2_ia ka0302$r_slot2_lmmr2_overlay.ka0302$r_slot2_lmmr2_bits.ka0302$v_slot2_lmmr2_ian#define ka0302$v_slot2_lmmr2_aw ka0302$r_slot2_lmmr2_overlay.ka0302$r_slot2_lmmr2_bits.ka0302$v_slot2_lmmr2_awv#define ka0302$v_slot2_lmmr2_nbanks ka0302$r_slot2_lmmr2_overlay.ka0302$r_slot2_lmmr2_bits.ka0302$v_slot2_lmmr2_nbanksr#define ka0302$v_slot2_lmmr2_addr ka0302$r_slot2_lmmr2_overlay.ka0302$r_slot2_lmmr2_,bits.ka0302$v_slot2_lmmr2_addrN#define ka0302$l_slot2_lmmr3 ka0302$r_slot2_lmmr3_overlay.ka0302$l_slot2_lmmr3n#define ka0302$v_slot2_lmmr3_en ka0302$r_slot2_lmmr3_overlay.ka0302$r_slot2_lmmr3_bits.ka0302$v_slot2_lmmr3_enp#define ka0302$v_slot2_lmmr3_int ka0302$r_slot2_lmmr3_overlay.ka0302$r_slot2_lmmr3_bits.ka0302$v_slot2_lmmr3_intn#define ka0302$v_slot2_lmmr3_ia ka0302$r_slot2_lmmr3_overlay.ka0302$r_slot2_lmmr3_bits.ka0302$v_slot2_lmmr3_ian#define ka0302$v_slot2_lmmr3_aw ka0302$r_slot2_lmmr3_ove,rlay.ka0302$r_slot2_lmmr3_bits.ka0302$v_slot2_lmmr3_awv#define ka0302$v_slot2_lmmr3_nbanks ka0302$r_slot2_lmmr3_overlay.ka0302$r_slot2_lmmr3_bits.ka0302$v_slot2_lmmr3_nbanksr#define ka0302$v_slot2_lmmr3_addr ka0302$r_slot2_lmmr3_overlay.ka0302$r_slot2_lmmr3_bits.ka0302$v_slot2_lmmr3_addrN#define ka0302$l_slot2_lmmr4 ka0302$r_slot2_lmmr4_overlay.ka0302$l_slot2_lmmr4n#define ka0302$v_slot2_lmmr4_en ka0302$r_slot2_lmmr4_overlay.ka0302$r_slot2_lmmr4_bits.ka0302$v_slot2_lmmr4_enp#define ka0302$v_slot2,_lmmr4_int ka0302$r_slot2_lmmr4_overlay.ka0302$r_slot2_lmmr4_bits.ka0302$v_slot2_lmmr4_intn#define ka0302$v_slot2_lmmr4_ia ka0302$r_slot2_lmmr4_overlay.ka0302$r_slot2_lmmr4_bits.ka0302$v_slot2_lmmr4_ian#define ka0302$v_slot2_lmmr4_aw ka0302$r_slot2_lmmr4_overlay.ka0302$r_slot2_lmmr4_bits.ka0302$v_slot2_lmmr4_awv#define ka0302$v_slot2_lmmr4_nbanks ka0302$r_slot2_lmmr4_overlay.ka0302$r_slot2_lmmr4_bits.ka0302$v_slot2_lmmr4_nbanksr#define ka0302$v_slot2_lmmr4_addr ka0302$r_slot2_lmmr4_overlay.ka0302$,r_slot2_lmmr4_bits.ka0302$v_slot2_lmmr4_addrN#define ka0302$l_slot2_lmmr5 ka0302$r_slot2_lmmr5_overlay.ka0302$l_slot2_lmmr5n#define ka0302$v_slot2_lmmr5_en ka0302$r_slot2_lmmr5_overlay.ka0302$r_slot2_lmmr5_bits.ka0302$v_slot2_lmmr5_enp#define ka0302$v_slot2_lmmr5_int ka0302$r_slot2_lmmr5_overlay.ka0302$r_slot2_lmmr5_bits.ka0302$v_slot2_lmmr5_intn#define ka0302$v_slot2_lmmr5_ia ka0302$r_slot2_lmmr5_overlay.ka0302$r_slot2_lmmr5_bits.ka0302$v_slot2_lmmr5_ian#define ka0302$v_slot2_lmmr5_aw ka0302$r_s,lot2_lmmr5_overlay.ka0302$r_slot2_lmmr5_bits.ka0302$v_slot2_lmmr5_awv#define ka0302$v_slot2_lmmr5_nbanks ka0302$r_slot2_lmmr5_overlay.ka0302$r_slot2_lmmr5_bits.ka0302$v_slot2_lmmr5_nbanksr#define ka0302$v_slot2_lmmr5_addr ka0302$r_slot2_lmmr5_overlay.ka0302$r_slot2_lmmr5_bits.ka0302$v_slot2_lmmr5_addrN#define ka0302$l_slot2_lmmr6 ka0302$r_slot2_lmmr6_overlay.ka0302$l_slot2_lmmr6n#define ka0302$v_slot2_lmmr6_en ka0302$r_slot2_lmmr6_overlay.ka0302$r_slot2_lmmr6_bits.ka0302$v_slot2_lmmr6_enp#define ,ka0302$v_slot2_lmmr6_int ka0302$r_slot2_lmmr6_overlay.ka0302$r_slot2_lmmr6_bits.ka0302$v_slot2_lmmr6_intn#define ka0302$v_slot2_lmmr6_ia ka0302$r_slot2_lmmr6_overlay.ka0302$r_slot2_lmmr6_bits.ka0302$v_slot2_lmmr6_ian#define ka0302$v_slot2_lmmr6_aw ka0302$r_slot2_lmmr6_overlay.ka0302$r_slot2_lmmr6_bits.ka0302$v_slot2_lmmr6_awv#define ka0302$v_slot2_lmmr6_nbanks ka0302$r_slot2_lmmr6_overlay.ka0302$r_slot2_lmmr6_bits.ka0302$v_slot2_lmmr6_nbanksr#define ka0302$v_slot2_lmmr6_addr ka0302$r_slot2_lmmr6_o,verlay.ka0302$r_slot2_lmmr6_bits.ka0302$v_slot2_lmmr6_addrN#define ka0302$l_slot2_lmmr7 ka0302$r_slot2_lmmr7_overlay.ka0302$l_slot2_lmmr7n#define ka0302$v_slot2_lmmr7_en ka0302$r_slot2_lmmr7_overlay.ka0302$r_slot2_lmmr7_bits.ka0302$v_slot2_lmmr7_enp#define ka0302$v_slot2_lmmr7_int ka0302$r_slot2_lmmr7_overlay.ka0302$r_slot2_lmmr7_bits.ka0302$v_slot2_lmmr7_intn#define ka0302$v_slot2_lmmr7_ia ka0302$r_slot2_lmmr7_overlay.ka0302$r_slot2_lmmr7_bits.ka0302$v_slot2_lmmr7_ian#define ka0302$v_slot2_lmmr7,_aw ka0302$r_slot2_lmmr7_overlay.ka0302$r_slot2_lmmr7_bits.ka0302$v_slot2_lmmr7_awv#define ka0302$v_slot2_lmmr7_nbanks ka0302$r_slot2_lmmr7_overlay.ka0302$r_slot2_lmmr7_bits.ka0302$v_slot2_lmmr7_nbanksr#define ka0302$v_slot2_lmmr7_addr ka0302$r_slot2_lmmr7_overlay.ka0302$r_slot2_lmmr7_bits.ka0302$v_slot2_lmmr7_addrQ#define ka0302$l_slot2_lbesr0 ka0302$r_slot2_lbesr0_overlay.ka0302$l_slot2_lbesr0~#define ka0302$v_slot2_lbesr0_syndrome ka0302$r_slot2_lbesr0_overlay.ka0302$r_slot2_lbesr0_bits.ka0302,$v_slot2_lbesr0_syndromeQ#define ka0302$l_slot2_lbesr1 ka0302$r_slot2_lbesr1_overlay.ka0302$l_slot2_lbesr1~#define ka0302$v_slot2_lbesr1_syndrome ka0302$r_slot2_lbesr1_overlay.ka0302$r_slot2_lbesr1_bits.ka0302$v_slot2_lbesr1_syndromeQ#define ka0302$l_slot2_lbesr2 ka0302$r_slot2_lbesr2_overlay.ka0302$l_slot2_lbesr2~#define ka0302$v_slot2_lbesr2_syndrome ka0302$r_slot2_lbesr2_overlay.ka0302$r_slot2_lbesr2_bits.ka0302$v_slot2_lbesr2_syndromeQ#define ka0302$l_slot2_lbesr3 ka0302$r_slot2_lbesr3_over ,lay.ka0302$l_slot2_lbesr3~#define ka0302$v_slot2_lbesr3_syndrome ka0302$r_slot2_lbesr3_overlay.ka0302$r_slot2_lbesr3_bits.ka0302$v_slot2_lbesr3_syndromeQ#define ka0302$l_slot2_lbecr0 ka0302$r_slot2_lbecr0_overlay.ka0302$l_slot2_lbecr0r#define ka0302$l_slot2_lbecr0_ca ka0302$r_slot2_lbecr0_overlay.ka0302$r_slot2_lbecr0_bits.ka0302$l_slot2_lbecr0_caQ#define ka0302$l_slot2_lbecr1 ka0302$r_slot2_lbecr1_overlay.ka0302$l_slot2_lbecr1r#define ka0302$v_slot2_lbecr1_ca ka0302$r_slot2_lbecr1_overlay.ka0!,302$r_slot2_lbecr1_bits.ka0302$v_slot2_lbecr1_cat#define ka0302$v_slot2_lbecr1_cid ka0302$r_slot2_lbecr1_overlay.ka0302$r_slot2_lbecr1_bits.ka0302$v_slot2_lbecr1_cidt#define ka0302$v_slot2_lbecr1_rid ka0302$r_slot2_lbecr1_overlay.ka0302$r_slot2_lbecr1_bits.ka0302$v_slot2_lbecr1_ridt#define ka0302$v_slot2_lbecr1_cnf ka0302$r_slot2_lbecr1_overlay.ka0302$r_slot2_lbecr1_bits.ka0302$v_slot2_lbecr1_cnfz#define ka0302$v_slot2_lbecr1_shared ka0302$r_slot2_lbecr1_overlay.ka0302$r_slot2_lbecr1_bits.ka0302$v",_slot2_lbecr1_sharedx#define ka0302$v_slot2_lbecr1_dirty ka0302$r_slot2_lbecr1_overlay.ka0302$r_slot2_lbecr1_bits.ka0302$v_slot2_lbecr1_dirtyz#define ka0302$v_slot2_lbecr1_dcycle ka0302$r_slot2_lbecr1_overlay.ka0302$r_slot2_lbecr1_bits.ka0302$v_slot2_lbecr1_dcycleN#define ka0302$l_slot2_lmode ka0302$r_slot2_lmode_overlay.ka0302$l_slot2_lmodeN#define ka0302$l_slot2_lmerr ka0302$r_slot2_lmerr_overlay.ka0302$l_slot2_lmerrN#define ka0302$l_slot2_llock ka0302$r_slot2_llock_overlay.ka0302$l_slot2_llock#,N#define ka0302$l_slot2_ledto ka0302$r_slot2_ledto_overlay.ka0302$l_slot2_ledtoN#define ka0302$l_slot2_ldiag ka0302$r_slot2_ldiag_overlay.ka0302$l_slot2_ldiagN#define ka0302$l_slot2_ltaga ka0302$r_slot2_ltaga_overlay.ka0302$l_slot2_ltagaN#define ka0302$l_slot2_ltagw ka0302$r_slot2_ltagw_overlay.ka0302$l_slot2_ltagwN#define ka0302$l_slot2_lcon0 ka0302$r_slot2_lcon0_overlay.ka0302$l_slot2_lcon0N#define ka0302$l_slot2_lcon1 ka0302$r_slot2_lcon1_overlay.ka0302$l_slot2_lcon1N#define ka0302$l_slot2_l$,perf ka0302$r_slot2_lperf_overlay.ka0302$l_slot2_lperfQ#define ka0302$l_slot2_lcntr0 ka0302$r_slot2_lcntr0_overlay.ka0302$l_slot2_lcntr0Q#define ka0302$l_slot2_lcntr1 ka0302$r_slot2_lcntr1_overlay.ka0302$l_slot2_lcntr1Z#define ka0302$l_slot2_lmissaddr ka0302$r_slot2_lmissaddr_overlay.ka0302$l_slot2_lmissaddrH#define ka0302$l_slot2_mcr ka0302$r_slot2_mcr_overlay.ka0302$l_slot2_mcrH#define ka0302$l_slot2_amr ka0302$r_slot2_amr_overlay.ka0302$l_slot2_amrN#define ka0302$l_slot2_mstr0 ka0302$r_slot%,2_mstr0_overlay.ka0302$l_slot2_mstr0N#define ka0302$l_slot2_mstr1 ka0302$r_slot2_mstr1_overlay.ka0302$l_slot2_mstr1K#define ka0302$l_slot2_fadr ka0302$r_slot2_fadr_overlay.ka0302$l_slot2_fadrK#define ka0302$l_slot2_mera ka0302$r_slot2_mera_overlay.ka0302$l_slot2_meraQ#define ka0302$l_slot2_msynda ka0302$r_slot2_msynda_overlay.ka0302$l_slot2_msyndaK#define ka0302$l_slot2_mdra ka0302$r_slot2_mdra_overlay.ka0302$l_slot2_mdraN#define ka0302$l_slot2_mcbsa ka0302$r_slot2_mcbsa_overlay.ka0302$l_slo&,t2_mcbsaK#define ka0302$l_slot2_merb ka0302$r_slot2_merb_overlay.ka0302$l_slot2_merbQ#define ka0302$l_slot2_msyndb ka0302$r_slot2_msyndb_overlay.ka0302$l_slot2_msyndbK#define ka0302$l_slot2_mdrb ka0302$r_slot2_mdrb_overlay.ka0302$l_slot2_mdrbN#define ka0302$l_slot2_mcbsb ka0302$r_slot2_mcbsb_overlay.ka0302$l_slot2_mcbsbK#define ka0302$l_slot3_ldev ka0302$r_slot3_ldev_overlay.ka0302$l_slot3_ldevp#define ka0302$v_slot3_ldev_dtype ka0302$r_slot3_ldev_overlay.ka0302$r_slot3_ldev_bits.ka0302$v_sl',ot3_ldev_dtypen#define ka0302$v_slot3_ldev_drev ka0302$r_slot3_ldev_overlay.ka0302$r_slot3_ldev_bits.ka0302$v_slot3_ldev_drevK#define ka0302$l_slot3_lber ka0302$r_slot3_lber_overlay.ka0302$l_slot3_lberh#define ka0302$v_slot3_lber_e ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_el#define ka0302$v_slot3_lber_uce ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_ucen#define ka0302$v_slot3_lber_uce2 ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bit(,s.ka0302$v_slot3_lber_uce2j#define ka0302$v_slot3_lber_ce ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_cel#define ka0302$v_slot3_lber_ce2 ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_ce2l#define ka0302$v_slot3_lber_cpe ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_cpen#define ka0302$v_slot3_lber_cpe2 ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_cpe2n#define ka0302$v_slot3_lber_cdpe ka030),2$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_cdpep#define ka0302$v_slot3_lber_cdpe2 ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_cdpe2l#define ka0302$v_slot3_lber_tde ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_tdel#define ka0302$v_slot3_lber_ste ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_sten#define ka0302$v_slot3_lber_cnfe ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slo*,t3_lber_cnfen#define ka0302$v_slot3_lber_nxae ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_nxael#define ka0302$v_slot3_lber_cae ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_cael#define ka0302$v_slot3_lber_she ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_shel#define ka0302$v_slot3_lber_die ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_dien#define ka0302$v_slot3_lber_dtce ka0302$r_slot3_lb+,er_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_dtcen#define ka0302$v_slot3_lber_ctce ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_ctcen#define ka0302$v_slot3_lber_nses ka0302$r_slot3_lber_overlay.ka0302$r_slot3_lber_bits.ka0302$v_slot3_lber_nsesK#define ka0302$l_slot3_lcnr ka0302$r_slot3_lcnr_overlay.ka0302$l_slot3_lcnrn#define ka0302$v_slot3_lcnr_ceen ka0302$r_slot3_lcnr_overlay.ka0302$r_slot3_lcnr_bits.ka0302$v_slot3_lcnr_ceent#define ka0302$v_slot3_lcnr_rs,,tstat ka0302$r_slot3_lcnr_overlay.ka0302$r_slot3_lcnr_bits.ka0302$v_slot3_lcnr_rststatp#define ka0302$v_slot3_lcnr_nhalt ka0302$r_slot3_lcnr_overlay.ka0302$r_slot3_lcnr_bits.ka0302$v_slot3_lcnr_nhaltn#define ka0302$v_slot3_lcnr_nrst ka0302$r_slot3_lcnr_overlay.ka0302$r_slot3_lcnr_bits.ka0302$v_slot3_lcnr_nrstl#define ka0302$v_slot3_lcnr_stf ka0302$r_slot3_lcnr_overlay.ka0302$r_slot3_lcnr_bits.ka0302$v_slot3_lcnr_stfH#define ka0302$l_slot3_ibr ka0302$r_slot3_ibr_overlay.ka0302$l_slot3_ibrr#define -,ka0302$v_slot3_ibr_rcv_sdat ka0302$r_slot3_ibr_overlay.ka0302$r_slot3_ibr_bits.ka0302$v_slot3_ibr_rcv_sdatr#define ka0302$v_slot3_ibr_xmt_sdat ka0302$r_slot3_ibr_overlay.ka0302$r_slot3_ibr_bits.ka0302$v_slot3_ibr_xmt_sdatj#define ka0302$v_slot3_ibr_sclk ka0302$r_slot3_ibr_overlay.ka0302$r_slot3_ibr_bits.ka0302$v_slot3_ibr_sclkN#define ka0302$l_slot3_lmmr0 ka0302$r_slot3_lmmr0_overlay.ka0302$l_slot3_lmmr0n#define ka0302$v_slot3_lmmr0_en ka0302$r_slot3_lmmr0_overlay.ka0302$r_slot3_lmmr0_bits.ka0302$.,v_slot3_lmmr0_enp#define ka0302$v_slot3_lmmr0_int ka0302$r_slot3_lmmr0_overlay.ka0302$r_slot3_lmmr0_bits.ka0302$v_slot3_lmmr0_intn#define ka0302$v_slot3_lmmr0_ia ka0302$r_slot3_lmmr0_overlay.ka0302$r_slot3_lmmr0_bits.ka0302$v_slot3_lmmr0_ian#define ka0302$v_slot3_lmmr0_aw ka0302$r_slot3_lmmr0_overlay.ka0302$r_slot3_lmmr0_bits.ka0302$v_slot3_lmmr0_awv#define ka0302$v_slot3_lmmr0_nbanks ka0302$r_slot3_lmmr0_overlay.ka0302$r_slot3_lmmr0_bits.ka0302$v_slot3_lmmr0_nbanksr#define ka0302$v_slot3_lmmr0_a/,ddr ka0302$r_slot3_lmmr0_overlay.ka0302$r_slot3_lmmr0_bits.ka0302$v_slot3_lmmr0_addrN#define ka0302$l_slot3_lmmr1 ka0302$r_slot3_lmmr1_overlay.ka0302$l_slot3_lmmr1n#define ka0302$v_slot3_lmmr1_en ka0302$r_slot3_lmmr1_overlay.ka0302$r_slot3_lmmr1_bits.ka0302$v_slot3_lmmr1_enp#define ka0302$v_slot3_lmmr1_int ka0302$r_slot3_lmmr1_overlay.ka0302$r_slot3_lmmr1_bits.ka0302$v_slot3_lmmr1_intn#define ka0302$v_slot3_lmmr1_ia ka0302$r_slot3_lmmr1_overlay.ka0302$r_slot3_lmmr1_bits.ka0302$v_slot3_lmmr1_ian#d0,efine ka0302$v_slot3_lmmr1_aw ka0302$r_slot3_lmmr1_overlay.ka0302$r_slot3_lmmr1_bits.ka0302$v_slot3_lmmr1_awv#define ka0302$v_slot3_lmmr1_nbanks ka0302$r_slot3_lmmr1_overlay.ka0302$r_slot3_lmmr1_bits.ka0302$v_slot3_lmmr1_nbanksr#define ka0302$v_slot3_lmmr1_addr ka0302$r_slot3_lmmr1_overlay.ka0302$r_slot3_lmmr1_bits.ka0302$v_slot3_lmmr1_addrN#define ka0302$l_slot3_lmmr2 ka0302$r_slot3_lmmr2_overlay.ka0302$l_slot3_lmmr2n#define ka0302$v_slot3_lmmr2_en ka0302$r_slot3_lmmr2_overlay.ka0302$r_slot3_lmmr1,2_bits.ka0302$v_slot3_lmmr2_enp#define ka0302$v_slot3_lmmr2_int ka0302$r_slot3_lmmr2_overlay.ka0302$r_slot3_lmmr2_bits.ka0302$v_slot3_lmmr2_intn#define ka0302$v_slot3_lmmr2_ia ka0302$r_slot3_lmmr2_overlay.ka0302$r_slot3_lmmr2_bits.ka0302$v_slot3_lmmr2_ian#define ka0302$v_slot3_lmmr2_aw ka0302$r_slot3_lmmr2_overlay.ka0302$r_slot3_lmmr2_bits.ka0302$v_slot3_lmmr2_awv#define ka0302$v_slot3_lmmr2_nbanks ka0302$r_slot3_lmmr2_overlay.ka0302$r_slot3_lmmr2_bits.ka0302$v_slot3_lmmr2_nbanksr#define ka0302$v2,_slot3_lmmr2_addr ka0302$r_slot3_lmmr2_overlay.ka0302$r_slot3_lmmr2_bits.ka0302$v_slot3_lmmr2_addrN#define ka0302$l_slot3_lmmr3 ka0302$r_slot3_lmmr3_overlay.ka0302$l_slot3_lmmr3n#define ka0302$v_slot3_lmmr3_en ka0302$r_slot3_lmmr3_overlay.ka0302$r_slot3_lmmr3_bits.ka0302$v_slot3_lmmr3_enp#define ka0302$v_slot3_lmmr3_int ka0302$r_slot3_lmmr3_overlay.ka0302$r_slot3_lmmr3_bits.ka0302$v_slot3_lmmr3_intn#define ka0302$v_slot3_lmmr3_ia ka0302$r_slot3_lmmr3_overlay.ka0302$r_slot3_lmmr3_bits.ka0302$v_slot3,3_lmmr3_ian#define ka0302$v_slot3_lmmr3_aw ka0302$r_slot3_lmmr3_overlay.ka0302$r_slot3_lmmr3_bits.ka0302$v_slot3_lmmr3_awv#define ka0302$v_slot3_lmmr3_nbanks ka0302$r_slot3_lmmr3_overlay.ka0302$r_slot3_lmmr3_bits.ka0302$v_slot3_lmmr3_nbanksr#define ka0302$v_slot3_lmmr3_addr ka0302$r_slot3_lmmr3_overlay.ka0302$r_slot3_lmmr3_bits.ka0302$v_slot3_lmmr3_addrN#define ka0302$l_slot3_lmmr4 ka0302$r_slot3_lmmr4_overlay.ka0302$l_slot3_lmmr4n#define ka0302$v_slot3_lmmr4_en ka0302$r_slot3_lmmr4_overlay.ka0304,2$r_slot3_lmmr4_bits.ka0302$v_slot3_lmmr4_enp#define ka0302$v_slot3_lmmr4_int ka0302$r_slot3_lmmr4_overlay.ka0302$r_slot3_lmmr4_bits.ka0302$v_slot3_lmmr4_intn#define ka0302$v_slot3_lmmr4_ia ka0302$r_slot3_lmmr4_overlay.ka0302$r_slot3_lmmr4_bits.ka0302$v_slot3_lmmr4_ian#define ka0302$v_slot3_lmmr4_aw ka0302$r_slot3_lmmr4_overlay.ka0302$r_slot3_lmmr4_bits.ka0302$v_slot3_lmmr4_awv#define ka0302$v_slot3_lmmr4_nbanks ka0302$r_slot3_lmmr4_overlay.ka0302$r_slot3_lmmr4_bits.ka0302$v_slot3_lmmr4_nbanksr#d5,efine ka0302$v_slot3_lmmr4_addr ka0302$r_slot3_lmmr4_overlay.ka0302$r_slot3_lmmr4_bits.ka0302$v_slot3_lmmr4_addrN#define ka0302$l_slot3_lmmr5 ka0302$r_slot3_lmmr5_overlay.ka0302$l_slot3_lmmr5n#define ka0302$v_slot3_lmmr5_en ka0302$r_slot3_lmmr5_overlay.ka0302$r_slot3_lmmr5_bits.ka0302$v_slot3_lmmr5_enp#define ka0302$v_slot3_lmmr5_int ka0302$r_slot3_lmmr5_overlay.ka0302$r_slot3_lmmr5_bits.ka0302$v_slot3_lmmr5_intn#define ka0302$v_slot3_lmmr5_ia ka0302$r_slot3_lmmr5_overlay.ka0302$r_slot3_lmmr5_bits6,.ka0302$v_slot3_lmmr5_ian#define ka0302$v_slot3_lmmr5_aw ka0302$r_slot3_lmmr5_overlay.ka0302$r_slot3_lmmr5_bits.ka0302$v_slot3_lmmr5_awv#define ka0302$v_slot3_lmmr5_nbanks ka0302$r_slot3_lmmr5_overlay.ka0302$r_slot3_lmmr5_bits.ka0302$v_slot3_lmmr5_nbanksr#define ka0302$v_slot3_lmmr5_addr ka0302$r_slot3_lmmr5_overlay.ka0302$r_slot3_lmmr5_bits.ka0302$v_slot3_lmmr5_addrN#define ka0302$l_slot3_lmmr6 ka0302$r_slot3_lmmr6_overlay.ka0302$l_slot3_lmmr6n#define ka0302$v_slot3_lmmr6_en ka0302$r_slot3_lmmr67,_overlay.ka0302$r_slot3_lmmr6_bits.ka0302$v_slot3_lmmr6_enp#define ka0302$v_slot3_lmmr6_int ka0302$r_slot3_lmmr6_overlay.ka0302$r_slot3_lmmr6_bits.ka0302$v_slot3_lmmr6_intn#define ka0302$v_slot3_lmmr6_ia ka0302$r_slot3_lmmr6_overlay.ka0302$r_slot3_lmmr6_bits.ka0302$v_slot3_lmmr6_ian#define ka0302$v_slot3_lmmr6_aw ka0302$r_slot3_lmmr6_overlay.ka0302$r_slot3_lmmr6_bits.ka0302$v_slot3_lmmr6_awv#define ka0302$v_slot3_lmmr6_nbanks ka0302$r_slot3_lmmr6_overlay.ka0302$r_slot3_lmmr6_bits.ka0302$v_slot3_lm8,mr6_nbanksr#define ka0302$v_slot3_lmmr6_addr ka0302$r_slot3_lmmr6_overlay.ka0302$r_slot3_lmmr6_bits.ka0302$v_slot3_lmmr6_addrN#define ka0302$l_slot3_lmmr7 ka0302$r_slot3_lmmr7_overlay.ka0302$l_slot3_lmmr7n#define ka0302$v_slot3_lmmr7_en ka0302$r_slot3_lmmr7_overlay.ka0302$r_slot3_lmmr7_bits.ka0302$v_slot3_lmmr7_enp#define ka0302$v_slot3_lmmr7_int ka0302$r_slot3_lmmr7_overlay.ka0302$r_slot3_lmmr7_bits.ka0302$v_slot3_lmmr7_intn#define ka0302$v_slot3_lmmr7_ia ka0302$r_slot3_lmmr7_overlay.ka0302$r_sl9,ot3_lmmr7_bits.ka0302$v_slot3_lmmr7_ian#define ka0302$v_slot3_lmmr7_aw ka0302$r_slot3_lmmr7_overlay.ka0302$r_slot3_lmmr7_bits.ka0302$v_slot3_lmmr7_awv#define ka0302$v_slot3_lmmr7_nbanks ka0302$r_slot3_lmmr7_overlay.ka0302$r_slot3_lmmr7_bits.ka0302$v_slot3_lmmr7_nbanksr#define ka0302$v_slot3_lmmr7_addr ka0302$r_slot3_lmmr7_overlay.ka0302$r_slot3_lmmr7_bits.ka0302$v_slot3_lmmr7_addrQ#define ka0302$l_slot3_lbesr0 ka0302$r_slot3_lbesr0_overlay.ka0302$l_slot3_lbesr0~#define ka0302$v_slot3_lbesr0_synd:,rome ka0302$r_slot3_lbesr0_overlay.ka0302$r_slot3_lbesr0_bits.ka0302$v_slot3_lbesr0_syndromeQ#define ka0302$l_slot3_lbesr1 ka0302$r_slot3_lbesr1_overlay.ka0302$l_slot3_lbesr1~#define ka0302$v_slot3_lbesr1_syndrome ka0302$r_slot3_lbesr1_overlay.ka0302$r_slot3_lbesr1_bits.ka0302$v_slot3_lbesr1_syndromeQ#define ka0302$l_slot3_lbesr2 ka0302$r_slot3_lbesr2_overlay.ka0302$l_slot3_lbesr2~#define ka0302$v_slot3_lbesr2_syndrome ka0302$r_slot3_lbesr2_overlay.ka0302$r_slot3_lbesr2_bits.ka0302$v_slot3_lbesr;,2_syndromeQ#define ka0302$l_slot3_lbesr3 ka0302$r_slot3_lbesr3_overlay.ka0302$l_slot3_lbesr3~#define ka0302$v_slot3_lbesr3_syndrome ka0302$r_slot3_lbesr3_overlay.ka0302$r_slot3_lbesr3_bits.ka0302$v_slot3_lbesr3_syndromeQ#define ka0302$l_slot3_lbecr0 ka0302$r_slot3_lbecr0_overlay.ka0302$l_slot3_lbecr0r#define ka0302$l_slot3_lbecr0_ca ka0302$r_slot3_lbecr0_overlay.ka0302$r_slot3_lbecr0_bits.ka0302$l_slot3_lbecr0_caQ#define ka0302$l_slot3_lbecr1 ka0302$r_slot3_lbecr1_overlay.ka0302$l_slot3_lbecr1<,r#define ka0302$v_slot3_lbecr1_ca ka0302$r_slot3_lbecr1_overlay.ka0302$r_slot3_lbecr1_bits.ka0302$v_slot3_lbecr1_cat#define ka0302$v_slot3_lbecr1_cid ka0302$r_slot3_lbecr1_overlay.ka0302$r_slot3_lbecr1_bits.ka0302$v_slot3_lbecr1_cidt#define ka0302$v_slot3_lbecr1_rid ka0302$r_slot3_lbecr1_overlay.ka0302$r_slot3_lbecr1_bits.ka0302$v_slot3_lbecr1_ridt#define ka0302$v_slot3_lbecr1_cnf ka0302$r_slot3_lbecr1_overlay.ka0302$r_slot3_lbecr1_bits.ka0302$v_slot3_lbecr1_cnfz#define ka0302$v_slot3_lbecr1_shar=,ed ka0302$r_slot3_lbecr1_overlay.ka0302$r_slot3_lbecr1_bits.ka0302$v_slot3_lbecr1_sharedx#define ka0302$v_slot3_lbecr1_dirty ka0302$r_slot3_lbecr1_overlay.ka0302$r_slot3_lbecr1_bits.ka0302$v_slot3_lbecr1_dirtyz#define ka0302$v_slot3_lbecr1_dcycle ka0302$r_slot3_lbecr1_overlay.ka0302$r_slot3_lbecr1_bits.ka0302$v_slot3_lbecr1_dcycleN#define ka0302$l_slot3_lmode ka0302$r_slot3_lmode_overlay.ka0302$l_slot3_lmodeN#define ka0302$l_slot3_lmerr ka0302$r_slot3_lmerr_overlay.ka0302$l_slot3_lmerrN#define ka>,0302$l_slot3_llock ka0302$r_slot3_llock_overlay.ka0302$l_slot3_llockN#define ka0302$l_slot3_ledto ka0302$r_slot3_ledto_overlay.ka0302$l_slot3_ledtoN#define ka0302$l_slot3_ldiag ka0302$r_slot3_ldiag_overlay.ka0302$l_slot3_ldiagN#define ka0302$l_slot3_ltaga ka0302$r_slot3_ltaga_overlay.ka0302$l_slot3_ltagaN#define ka0302$l_slot3_ltagw ka0302$r_slot3_ltagw_overlay.ka0302$l_slot3_ltagwN#define ka0302$l_slot3_lcon0 ka0302$r_slot3_lcon0_overlay.ka0302$l_slot3_lcon0N#define ka0302$l_slot3_lcon1 ka0302$?,r_slot3_lcon1_overlay.ka0302$l_slot3_lcon1N#define ka0302$l_slot3_lperf ka0302$r_slot3_lperf_overlay.ka0302$l_slot3_lperfQ#define ka0302$l_slot3_lcntr0 ka0302$r_slot3_lcntr0_overlay.ka0302$l_slot3_lcntr0Q#define ka0302$l_slot3_lcntr1 ka0302$r_slot3_lcntr1_overlay.ka0302$l_slot3_lcntr1Z#define ka0302$l_slot3_lmissaddr ka0302$r_slot3_lmissaddr_overlay.ka0302$l_slot3_lmissaddrH#define ka0302$l_slot3_mcr ka0302$r_slot3_mcr_overlay.ka0302$l_slot3_mcrH#define ka0302$l_slot3_amr ka0302$r_slot3_amr_ov@,erlay.ka0302$l_slot3_amrN#define ka0302$l_slot3_mstr0 ka0302$r_slot3_mstr0_overlay.ka0302$l_slot3_mstr0N#define ka0302$l_slot3_mstr1 ka0302$r_slot3_mstr1_overlay.ka0302$l_slot3_mstr1K#define ka0302$l_slot3_fadr ka0302$r_slot3_fadr_overlay.ka0302$l_slot3_fadrK#define ka0302$l_slot3_mera ka0302$r_slot3_mera_overlay.ka0302$l_slot3_meraQ#define ka0302$l_slot3_msynda ka0302$r_slot3_msynda_overlay.ka0302$l_slot3_msyndaK#define ka0302$l_slot3_mdra ka0302$r_slot3_mdra_overlay.ka0302$l_slot3_mdraN#dA,efine ka0302$l_slot3_mcbsa ka0302$r_slot3_mcbsa_overlay.ka0302$l_slot3_mcbsaK#define ka0302$l_slot3_merb ka0302$r_slot3_merb_overlay.ka0302$l_slot3_merbQ#define ka0302$l_slot3_msyndb ka0302$r_slot3_msyndb_overlay.ka0302$l_slot3_msyndbK#define ka0302$l_slot3_mdrb ka0302$r_slot3_mdrb_overlay.ka0302$l_slot3_mdrbN#define ka0302$l_slot3_mcbsb ka0302$r_slot3_mcbsb_overlay.ka0302$l_slot3_mcbsbK#define ka0302$l_slot4_ldev ka0302$r_slot4_ldev_overlay.ka0302$l_slot4_ldevp#define ka0302$v_slot4_ldev_dtB,ype ka0302$r_slot4_ldev_overlay.ka0302$r_slot4_ldev_bits.ka0302$v_slot4_ldev_dtypen#define ka0302$v_slot4_ldev_drev ka0302$r_slot4_ldev_overlay.ka0302$r_slot4_ldev_bits.ka0302$v_slot4_ldev_drevK#define ka0302$l_slot4_lber ka0302$r_slot4_lber_overlay.ka0302$l_slot4_lberh#define ka0302$v_slot4_lber_e ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_el#define ka0302$v_slot4_lber_uce ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_ucen#define ka0302$vC,_slot4_lber_uce2 ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_uce2j#define ka0302$v_slot4_lber_ce ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_cel#define ka0302$v_slot4_lber_ce2 ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_ce2l#define ka0302$v_slot4_lber_cpe ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_cpen#define ka0302$v_slot4_lber_cpe2 ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bD,its.ka0302$v_slot4_lber_cpe2n#define ka0302$v_slot4_lber_cdpe ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_cdpep#define ka0302$v_slot4_lber_cdpe2 ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_cdpe2l#define ka0302$v_slot4_lber_tde ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_tdel#define ka0302$v_slot4_lber_ste ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_sten#define ka0302$v_slot4_lber_cnE,fe ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_cnfen#define ka0302$v_slot4_lber_nxae ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_nxael#define ka0302$v_slot4_lber_cae ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_cael#define ka0302$v_slot4_lber_she ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_shel#define ka0302$v_slot4_lber_die ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$F,v_slot4_lber_dien#define ka0302$v_slot4_lber_dtce ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_dtcen#define ka0302$v_slot4_lber_ctce ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_ctcen#define ka0302$v_slot4_lber_nses ka0302$r_slot4_lber_overlay.ka0302$r_slot4_lber_bits.ka0302$v_slot4_lber_nsesK#define ka0302$l_slot4_lcnr ka0302$r_slot4_lcnr_overlay.ka0302$l_slot4_lcnrn#define ka0302$v_slot4_lcnr_ceen ka0302$r_slot4_lcnr_overlay.ka0302$r_slotG,4_lcnr_bits.ka0302$v_slot4_lcnr_ceent#define ka0302$v_slot4_lcnr_rststat ka0302$r_slot4_lcnr_overlay.ka0302$r_slot4_lcnr_bits.ka0302$v_slot4_lcnr_rststatp#define ka0302$v_slot4_lcnr_nhalt ka0302$r_slot4_lcnr_overlay.ka0302$r_slot4_lcnr_bits.ka0302$v_slot4_lcnr_nhaltn#define ka0302$v_slot4_lcnr_nrst ka0302$r_slot4_lcnr_overlay.ka0302$r_slot4_lcnr_bits.ka0302$v_slot4_lcnr_nrstl#define ka0302$v_slot4_lcnr_stf ka0302$r_slot4_lcnr_overlay.ka0302$r_slot4_lcnr_bits.ka0302$v_slot4_lcnr_stfH#define ka0302H,$l_slot4_ibr ka0302$r_slot4_ibr_overlay.ka0302$l_slot4_ibrr#define ka0302$v_slot4_ibr_rcv_sdat ka0302$r_slot4_ibr_overlay.ka0302$r_slot4_ibr_bits.ka0302$v_slot4_ibr_rcv_sdatr#define ka0302$v_slot4_ibr_xmt_sdat ka0302$r_slot4_ibr_overlay.ka0302$r_slot4_ibr_bits.ka0302$v_slot4_ibr_xmt_sdatj#define ka0302$v_slot4_ibr_sclk ka0302$r_slot4_ibr_overlay.ka0302$r_slot4_ibr_bits.ka0302$v_slot4_ibr_sclkN#define ka0302$l_slot4_lmmr0 ka0302$r_slot4_lmmr0_overlay.ka0302$l_slot4_lmmr0n#define ka0302$v_slot4_lmmI,r0_en ka0302$r_slot4_lmmr0_overlay.ka0302$r_slot4_lmmr0_bits.ka0302$v_slot4_lmmr0_enp#define ka0302$v_slot4_lmmr0_int ka0302$r_slot4_lmmr0_overlay.ka0302$r_slot4_lmmr0_bits.ka0302$v_slot4_lmmr0_intn#define ka0302$v_slot4_lmmr0_ia ka0302$r_slot4_lmmr0_overlay.ka0302$r_slot4_lmmr0_bits.ka0302$v_slot4_lmmr0_ian#define ka0302$v_slot4_lmmr0_aw ka0302$r_slot4_lmmr0_overlay.ka0302$r_slot4_lmmr0_bits.ka0302$v_slot4_lmmr0_awv#define ka0302$v_slot4_lmmr0_nbanks ka0302$r_slot4_lmmr0_overlay.ka0302$r_slot4_lmJ,mr0_bits.ka0302$v_slot4_lmmr0_nbanksr#define ka0302$v_slot4_lmmr0_addr ka0302$r_slot4_lmmr0_overlay.ka0302$r_slot4_lmmr0_bits.ka0302$v_slot4_lmmr0_addrN#define ka0302$l_slot4_lmmr1 ka0302$r_slot4_lmmr1_overlay.ka0302$l_slot4_lmmr1n#define ka0302$v_slot4_lmmr1_en ka0302$r_slot4_lmmr1_overlay.ka0302$r_slot4_lmmr1_bits.ka0302$v_slot4_lmmr1_enp#define ka0302$v_slot4_lmmr1_int ka0302$r_slot4_lmmr1_overlay.ka0302$r_slot4_lmmr1_bits.ka0302$v_slot4_lmmr1_intn#define ka0302$v_slot4_lmmr1_ia ka0302$r_slot4K,_lmmr1_overlay.ka0302$r_slot4_lmmr1_bits.ka0302$v_slot4_lmmr1_ian#define ka0302$v_slot4_lmmr1_aw ka0302$r_slot4_lmmr1_overlay.ka0302$r_slot4_lmmr1_bits.ka0302$v_slot4_lmmr1_awv#define ka0302$v_slot4_lmmr1_nbanks ka0302$r_slot4_lmmr1_overlay.ka0302$r_slot4_lmmr1_bits.ka0302$v_slot4_lmmr1_nbanksr#define ka0302$v_slot4_lmmr1_addr ka0302$r_slot4_lmmr1_overlay.ka0302$r_slot4_lmmr1_bits.ka0302$v_slot4_lmmr1_addrN#define ka0302$l_slot4_lmmr2 ka0302$r_slot4_lmmr2_overlay.ka0302$l_slot4_lmmr2n#define ka03L,02$v_slot4_lmmr2_en ka0302$r_slot4_lmmr2_overlay.ka0302$r_slot4_lmmr2_bits.ka0302$v_slot4_lmmr2_enp#define ka0302$v_slot4_lmmr2_int ka0302$r_slot4_lmmr2_overlay.ka0302$r_slot4_lmmr2_bits.ka0302$v_slot4_lmmr2_intn#define ka0302$v_slot4_lmmr2_ia ka0302$r_slot4_lmmr2_overlay.ka0302$r_slot4_lmmr2_bits.ka0302$v_slot4_lmmr2_ian#define ka0302$v_slot4_lmmr2_aw ka0302$r_slot4_lmmr2_overlay.ka0302$r_slot4_lmmr2_bits.ka0302$v_slot4_lmmr2_awv#define ka0302$v_slot4_lmmr2_nbanks ka0302$r_slot4_lmmr2_overlay.ka0M,302$r_slot4_lmmr2_bits.ka0302$v_slot4_lmmr2_nbanksr#define ka0302$v_slot4_lmmr2_addr ka0302$r_slot4_lmmr2_overlay.ka0302$r_slot4_lmmr2_bits.ka0302$v_slot4_lmmr2_addrN#define ka0302$l_slot4_lmmr3 ka0302$r_slot4_lmmr3_overlay.ka0302$l_slot4_lmmr3n#define ka0302$v_slot4_lmmr3_en ka0302$r_slot4_lmmr3_overlay.ka0302$r_slot4_lmmr3_bits.ka0302$v_slot4_lmmr3_enp#define ka0302$v_slot4_lmmr3_int ka0302$r_slot4_lmmr3_overlay.ka0302$r_slot4_lmmr3_bits.ka0302$v_slot4_lmmr3_intn#define ka0302$v_slot4_lmmr3_ia N,ka0302$r_slot4_lmmr3_overlay.ka0302$r_slot4_lmmr3_bits.ka0302$v_slot4_lmmr3_ian#define ka0302$v_slot4_lmmr3_aw ka0302$r_slot4_lmmr3_overlay.ka0302$r_slot4_lmmr3_bits.ka0302$v_slot4_lmmr3_awv#define ka0302$v_slot4_lmmr3_nbanks ka0302$r_slot4_lmmr3_overlay.ka0302$r_slot4_lmmr3_bits.ka0302$v_slot4_lmmr3_nbanksr#define ka0302$v_slot4_lmmr3_addr ka0302$r_slot4_lmmr3_overlay.ka0302$r_slot4_lmmr3_bits.ka0302$v_slot4_lmmr3_addrN#define ka0302$l_slot4_lmmr4 ka0302$r_slot4_lmmr4_overlay.ka0302$l_slot4_lmmr4O,n#define ka0302$v_slot4_lmmr4_en ka0302$r_slot4_lmmr4_overlay.ka0302$r_slot4_lmmr4_bits.ka0302$v_slot4_lmmr4_enp#define ka0302$v_slot4_lmmr4_int ka0302$r_slot4_lmmr4_overlay.ka0302$r_slot4_lmmr4_bits.ka0302$v_slot4_lmmr4_intn#define ka0302$v_slot4_lmmr4_ia ka0302$r_slot4_lmmr4_overlay.ka0302$r_slot4_lmmr4_bits.ka0302$v_slot4_lmmr4_ian#define ka0302$v_slot4_lmmr4_aw ka0302$r_slot4_lmmr4_overlay.ka0302$r_slot4_lmmr4_bits.ka0302$v_slot4_lmmr4_awv#define ka0302$v_slot4_lmmr4_nbanks ka0302$r_slot4_lmmP,r4_overlay.ka0302$r_slot4_lmmr4_bits.ka0302$v_slot4_lmmr4_nbanksr#define ka0302$v_slot4_lmmr4_addr ka0302$r_slot4_lmmr4_overlay.ka0302$r_slot4_lmmr4_bits.ka0302$v_slot4_lmmr4_addrN#define ka0302$l_slot4_lmmr5 ka0302$r_slot4_lmmr5_overlay.ka0302$l_slot4_lmmr5n#define ka0302$v_slot4_lmmr5_en ka0302$r_slot4_lmmr5_overlay.ka0302$r_slot4_lmmr5_bits.ka0302$v_slot4_lmmr5_enp#define ka0302$v_slot4_lmmr5_int ka0302$r_slot4_lmmr5_overlay.ka0302$r_slot4_lmmr5_bits.ka0302$v_slot4_lmmr5_intn#define ka0302$v_sQ,lot4_lmmr5_ia ka0302$r_slot4_lmmr5_overlay.ka0302$r_slot4_lmmr5_bits.ka0302$v_slot4_lmmr5_ian#define ka0302$v_slot4_lmmr5_aw ka0302$r_slot4_lmmr5_overlay.ka0302$r_slot4_lmmr5_bits.ka0302$v_slot4_lmmr5_awv#define ka0302$v_slot4_lmmr5_nbanks ka0302$r_slot4_lmmr5_overlay.ka0302$r_slot4_lmmr5_bits.ka0302$v_slot4_lmmr5_nbanksr#define ka0302$v_slot4_lmmr5_addr ka0302$r_slot4_lmmr5_overlay.ka0302$r_slot4_lmmr5_bits.ka0302$v_slot4_lmmr5_addrN#define ka0302$l_slot4_lmmr6 ka0302$r_slot4_lmmr6_overlay.ka0302R,$l_slot4_lmmr6n#define ka0302$v_slot4_lmmr6_en ka0302$r_slot4_lmmr6_overlay.ka0302$r_slot4_lmmr6_bits.ka0302$v_slot4_lmmr6_enp#define ka0302$v_slot4_lmmr6_int ka0302$r_slot4_lmmr6_overlay.ka0302$r_slot4_lmmr6_bits.ka0302$v_slot4_lmmr6_intn#define ka0302$v_slot4_lmmr6_ia ka0302$r_slot4_lmmr6_overlay.ka0302$r_slot4_lmmr6_bits.ka0302$v_slot4_lmmr6_ian#define ka0302$v_slot4_lmmr6_aw ka0302$r_slot4_lmmr6_overlay.ka0302$r_slot4_lmmr6_bits.ka0302$v_slot4_lmmr6_awv#define ka0302$v_slot4_lmmr6_nbanks ka03S,02$r_slot4_lmmr6_overlay.ka0302$r_slot4_lmmr6_bits.ka0302$v_slot4_lmmr6_nbanksr#define ka0302$v_slot4_lmmr6_addr ka0302$r_slot4_lmmr6_overlay.ka0302$r_slot4_lmmr6_bits.ka0302$v_slot4_lmmr6_addrN#define ka0302$l_slot4_lmmr7 ka0302$r_slot4_lmmr7_overlay.ka0302$l_slot4_lmmr7n#define ka0302$v_slot4_lmmr7_en ka0302$r_slot4_lmmr7_overlay.ka0302$r_slot4_lmmr7_bits.ka0302$v_slot4_lmmr7_enp#define ka0302$v_slot4_lmmr7_int ka0302$r_slot4_lmmr7_overlay.ka0302$r_slot4_lmmr7_bits.ka0302$v_slot4_lmmr7_intn#defT,ine ka0302$v_slot4_lmmr7_ia ka0302$r_slot4_lmmr7_overlay.ka0302$r_slot4_lmmr7_bits.ka0302$v_slot4_lmmr7_ian#define ka0302$v_slot4_lmmr7_aw ka0302$r_slot4_lmmr7_overlay.ka0302$r_slot4_lmmr7_bits.ka0302$v_slot4_lmmr7_awv#define ka0302$v_slot4_lmmr7_nbanks ka0302$r_slot4_lmmr7_overlay.ka0302$r_slot4_lmmr7_bits.ka0302$v_slot4_lmmr7_nbanksr#define ka0302$v_slot4_lmmr7_addr ka0302$r_slot4_lmmr7_overlay.ka0302$r_slot4_lmmr7_bits.ka0302$v_slot4_lmmr7_addrQ#define ka0302$l_slot4_lbesr0 ka0302$r_slot4_lbesrU,0_overlay.ka0302$l_slot4_lbesr0~#define ka0302$v_slot4_lbesr0_syndrome ka0302$r_slot4_lbesr0_overlay.ka0302$r_slot4_lbesr0_bits.ka0302$v_slot4_lbesr0_syndromeQ#define ka0302$l_slot4_lbesr1 ka0302$r_slot4_lbesr1_overlay.ka0302$l_slot4_lbesr1~#define ka0302$v_slot4_lbesr1_syndrome ka0302$r_slot4_lbesr1_overlay.ka0302$r_slot4_lbesr1_bits.ka0302$v_slot4_lbesr1_syndromeQ#define ka0302$l_slot4_lbesr2 ka0302$r_slot4_lbesr2_overlay.ka0302$l_slot4_lbesr2~#define ka0302$v_slot4_lbesr2_syndrome ka0302$r_V,slot4_lbesr2_overlay.ka0302$r_slot4_lbesr2_bits.ka0302$v_slot4_lbesr2_syndromeQ#define ka0302$l_slot4_lbesr3 ka0302$r_slot4_lbesr3_overlay.ka0302$l_slot4_lbesr3~#define ka0302$v_slot4_lbesr3_syndrome ka0302$r_slot4_lbesr3_overlay.ka0302$r_slot4_lbesr3_bits.ka0302$v_slot4_lbesr3_syndromeQ#define ka0302$l_slot4_lbecr0 ka0302$r_slot4_lbecr0_overlay.ka0302$l_slot4_lbecr0r#define ka0302$l_slot4_lbecr0_ca ka0302$r_slot4_lbecr0_overlay.ka0302$r_slot4_lbecr0_bits.ka0302$l_slot4_lbecr0_caQ#define ka0302W,$l_slot4_lbecr1 ka0302$r_slot4_lbecr1_overlay.ka0302$l_slot4_lbecr1r#define ka0302$v_slot4_lbecr1_ca ka0302$r_slot4_lbecr1_overlay.ka0302$r_slot4_lbecr1_bits.ka0302$v_slot4_lbecr1_cat#define ka0302$v_slot4_lbecr1_cid ka0302$r_slot4_lbecr1_overlay.ka0302$r_slot4_lbecr1_bits.ka0302$v_slot4_lbecr1_cidt#define ka0302$v_slot4_lbecr1_rid ka0302$r_slot4_lbecr1_overlay.ka0302$r_slot4_lbecr1_bits.ka0302$v_slot4_lbecr1_ridt#define ka0302$v_slot4_lbecr1_cnf ka0302$r_slot4_lbecr1_overlay.ka0302$r_slot4_lbecrX,1_bits.ka0302$v_slot4_lbecr1_cnfz#define ka0302$v_slot4_lbecr1_shared ka0302$r_slot4_lbecr1_overlay.ka0302$r_slot4_lbecr1_bits.ka0302$v_slot4_lbecr1_sharedx#define ka0302$v_slot4_lbecr1_dirty ka0302$r_slot4_lbecr1_overlay.ka0302$r_slot4_lbecr1_bits.ka0302$v_slot4_lbecr1_dirtyz#define ka0302$v_slot4_lbecr1_dcycle ka0302$r_slot4_lbecr1_overlay.ka0302$r_slot4_lbecr1_bits.ka0302$v_slot4_lbecr1_dcycleN#define ka0302$l_slot4_lmode ka0302$r_slot4_lmode_overlay.ka0302$l_slot4_lmodeN#define ka0302$l_slot4Y,_lmerr ka0302$r_slot4_lmerr_overlay.ka0302$l_slot4_lmerrN#define ka0302$l_slot4_llock ka0302$r_slot4_llock_overlay.ka0302$l_slot4_llockN#define ka0302$l_slot4_ledto ka0302$r_slot4_ledto_overlay.ka0302$l_slot4_ledtoN#define ka0302$l_slot4_ldiag ka0302$r_slot4_ldiag_overlay.ka0302$l_slot4_ldiagN#define ka0302$l_slot4_ltaga ka0302$r_slot4_ltaga_overlay.ka0302$l_slot4_ltagaN#define ka0302$l_slot4_ltagw ka0302$r_slot4_ltagw_overlay.ka0302$l_slot4_ltagwN#define ka0302$l_slot4_lcon0 ka0302$r_slot4_lconZ,0_overlay.ka0302$l_slot4_lcon0N#define ka0302$l_slot4_lcon1 ka0302$r_slot4_lcon1_overlay.ka0302$l_slot4_lcon1N#define ka0302$l_slot4_lperf ka0302$r_slot4_lperf_overlay.ka0302$l_slot4_lperfQ#define ka0302$l_slot4_lcntr0 ka0302$r_slot4_lcntr0_overlay.ka0302$l_slot4_lcntr0Q#define ka0302$l_slot4_lcntr1 ka0302$r_slot4_lcntr1_overlay.ka0302$l_slot4_lcntr1Z#define ka0302$l_slot4_lmissaddr ka0302$r_slot4_lmissaddr_overlay.ka0302$l_slot4_lmissaddrH#define ka0302$l_slot4_mcr ka0302$r_slot4_mcr_overlay.[,ka0302$l_slot4_mcrH#define ka0302$l_slot4_amr ka0302$r_slot4_amr_overlay.ka0302$l_slot4_amrN#define ka0302$l_slot4_mstr0 ka0302$r_slot4_mstr0_overlay.ka0302$l_slot4_mstr0N#define ka0302$l_slot4_mstr1 ka0302$r_slot4_mstr1_overlay.ka0302$l_slot4_mstr1K#define ka0302$l_slot4_fadr ka0302$r_slot4_fadr_overlay.ka0302$l_slot4_fadrK#define ka0302$l_slot4_mera ka0302$r_slot4_mera_overlay.ka0302$l_slot4_meraQ#define ka0302$l_slot4_msynda ka0302$r_slot4_msynda_overlay.ka0302$l_slot4_msyndaK#define ka03\,02$l_slot4_mdra ka0302$r_slot4_mdra_overlay.ka0302$l_slot4_mdraN#define ka0302$l_slot4_mcbsa ka0302$r_slot4_mcbsa_overlay.ka0302$l_slot4_mcbsaK#define ka0302$l_slot4_merb ka0302$r_slot4_merb_overlay.ka0302$l_slot4_merbQ#define ka0302$l_slot4_msyndb ka0302$r_slot4_msyndb_overlay.ka0302$l_slot4_msyndbK#define ka0302$l_slot4_mdrb ka0302$r_slot4_mdrb_overlay.ka0302$l_slot4_mdrbN#define ka0302$l_slot4_mcbsb ka0302$r_slot4_mcbsb_overlay.ka0302$l_slot4_mcbsbK#define ka0302$l_slot5_ldev ka0302$r_slo],t5_ldev_overlay.ka0302$l_slot5_ldevp#define ka0302$v_slot5_ldev_dtype ka0302$r_slot5_ldev_overlay.ka0302$r_slot5_ldev_bits.ka0302$v_slot5_ldev_dtypen#define ka0302$v_slot5_ldev_drev ka0302$r_slot5_ldev_overlay.ka0302$r_slot5_ldev_bits.ka0302$v_slot5_ldev_drevK#define ka0302$l_slot5_lber ka0302$r_slot5_lber_overlay.ka0302$l_slot5_lberh#define ka0302$v_slot5_lber_e ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_el#define ka0302$v_slot5_lber_uce ka0302$r_slot5_lber_overla^,y.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_ucen#define ka0302$v_slot5_lber_uce2 ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_uce2j#define ka0302$v_slot5_lber_ce ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_cel#define ka0302$v_slot5_lber_ce2 ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_ce2l#define ka0302$v_slot5_lber_cpe ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_cpen#define ka0302_,$v_slot5_lber_cpe2 ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_cpe2n#define ka0302$v_slot5_lber_cdpe ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_cdpep#define ka0302$v_slot5_lber_cdpe2 ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_cdpe2l#define ka0302$v_slot5_lber_tde ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_tdel#define ka0302$v_slot5_lber_ste ka0302$r_slot5_lber_overlay.ka0302$r_slo`,t5_lber_bits.ka0302$v_slot5_lber_sten#define ka0302$v_slot5_lber_cnfe ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_cnfen#define ka0302$v_slot5_lber_nxae ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_nxael#define ka0302$v_slot5_lber_cae ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_cael#define ka0302$v_slot5_lber_she ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_shel#define ka0302$v_slot5_la,ber_die ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_dien#define ka0302$v_slot5_lber_dtce ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_dtcen#define ka0302$v_slot5_lber_ctce ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_ctcen#define ka0302$v_slot5_lber_nses ka0302$r_slot5_lber_overlay.ka0302$r_slot5_lber_bits.ka0302$v_slot5_lber_nsesK#define ka0302$l_slot5_lcnr ka0302$r_slot5_lcnr_overlay.ka0302$l_slot5_lcnrn#definb,e ka0302$v_slot5_lcnr_ceen ka0302$r_slot5_lcnr_overlay.ka0302$r_slot5_lcnr_bits.ka0302$v_slot5_lcnr_ceent#define ka0302$v_slot5_lcnr_rststat ka0302$r_slot5_lcnr_overlay.ka0302$r_slot5_lcnr_bits.ka0302$v_slot5_lcnr_rststatp#define ka0302$v_slot5_lcnr_nhalt ka0302$r_slot5_lcnr_overlay.ka0302$r_slot5_lcnr_bits.ka0302$v_slot5_lcnr_nhaltn#define ka0302$v_slot5_lcnr_nrst ka0302$r_slot5_lcnr_overlay.ka0302$r_slot5_lcnr_bits.ka0302$v_slot5_lcnr_nrstl#define ka0302$v_slot5_lcnr_stf ka0302$r_slot5_lcnr_overc,lay.ka0302$r_slot5_lcnr_bits.ka0302$v_slot5_lcnr_stfH#define ka0302$l_slot5_ibr ka0302$r_slot5_ibr_overlay.ka0302$l_slot5_ibrr#define ka0302$v_slot5_ibr_rcv_sdat ka0302$r_slot5_ibr_overlay.ka0302$r_slot5_ibr_bits.ka0302$v_slot5_ibr_rcv_sdatr#define ka0302$v_slot5_ibr_xmt_sdat ka0302$r_slot5_ibr_overlay.ka0302$r_slot5_ibr_bits.ka0302$v_slot5_ibr_xmt_sdatj#define ka0302$v_slot5_ibr_sclk ka0302$r_slot5_ibr_overlay.ka0302$r_slot5_ibr_bits.ka0302$v_slot5_ibr_sclkN#define ka0302$l_slot5_lmmr0 ka0302$r_d,slot5_lmmr0_overlay.ka0302$l_slot5_lmmr0n#define ka0302$v_slot5_lmmr0_en ka0302$r_slot5_lmmr0_overlay.ka0302$r_slot5_lmmr0_bits.ka0302$v_slot5_lmmr0_enp#define ka0302$v_slot5_lmmr0_int ka0302$r_slot5_lmmr0_overlay.ka0302$r_slot5_lmmr0_bits.ka0302$v_slot5_lmmr0_intn#define ka0302$v_slot5_lmmr0_ia ka0302$r_slot5_lmmr0_overlay.ka0302$r_slot5_lmmr0_bits.ka0302$v_slot5_lmmr0_ian#define ka0302$v_slot5_lmmr0_aw ka0302$r_slot5_lmmr0_overlay.ka0302$r_slot5_lmmr0_bits.ka0302$v_slot5_lmmr0_awv#define ka0302e,$v_slot5_lmmr0_nbanks ka0302$r_slot5_lmmr0_overlay.ka0302$r_slot5_lmmr0_bits.ka0302$v_slot5_lmmr0_nbanksr#define ka0302$v_slot5_lmmr0_addr ka0302$r_slot5_lmmr0_overlay.ka0302$r_slot5_lmmr0_bits.ka0302$v_slot5_lmmr0_addrN#define ka0302$l_slot5_lmmr1 ka0302$r_slot5_lmmr1_overlay.ka0302$l_slot5_lmmr1n#define ka0302$v_slot5_lmmr1_en ka0302$r_slot5_lmmr1_overlay.ka0302$r_slot5_lmmr1_bits.ka0302$v_slot5_lmmr1_enp#define ka0302$v_slot5_lmmr1_int ka0302$r_slot5_lmmr1_overlay.ka0302$r_slot5_lmmr1_bits.ka03f,02$v_slot5_lmmr1_intn#define ka0302$v_slot5_lmmr1_ia ka0302$r_slot5_lmmr1_overlay.ka0302$r_slot5_lmmr1_bits.ka0302$v_slot5_lmmr1_ian#define ka0302$v_slot5_lmmr1_aw ka0302$r_slot5_lmmr1_overlay.ka0302$r_slot5_lmmr1_bits.ka0302$v_slot5_lmmr1_awv#define ka0302$v_slot5_lmmr1_nbanks ka0302$r_slot5_lmmr1_overlay.ka0302$r_slot5_lmmr1_bits.ka0302$v_slot5_lmmr1_nbanksr#define ka0302$v_slot5_lmmr1_addr ka0302$r_slot5_lmmr1_overlay.ka0302$r_slot5_lmmr1_bits.ka0302$v_slot5_lmmr1_addrN#define ka0302$l_slot5_lg,mmr2 ka0302$r_slot5_lmmr2_overlay.ka0302$l_slot5_lmmr2n#define ka0302$v_slot5_lmmr2_en ka0302$r_slot5_lmmr2_overlay.ka0302$r_slot5_lmmr2_bits.ka0302$v_slot5_lmmr2_enp#define ka0302$v_slot5_lmmr2_int ka0302$r_slot5_lmmr2_overlay.ka0302$r_slot5_lmmr2_bits.ka0302$v_slot5_lmmr2_intn#define ka0302$v_slot5_lmmr2_ia ka0302$r_slot5_lmmr2_overlay.ka0302$r_slot5_lmmr2_bits.ka0302$v_slot5_lmmr2_ian#define ka0302$v_slot5_lmmr2_aw ka0302$r_slot5_lmmr2_overlay.ka0302$r_slot5_lmmr2_bits.ka0302$v_slot5_lmmr2_awvh,#define ka0302$v_slot5_lmmr2_nbanks ka0302$r_slot5_lmmr2_overlay.ka0302$r_slot5_lmmr2_bits.ka0302$v_slot5_lmmr2_nbanksr#define ka0302$v_slot5_lmmr2_addr ka0302$r_slot5_lmmr2_overlay.ka0302$r_slot5_lmmr2_bits.ka0302$v_slot5_lmmr2_addrN#define ka0302$l_slot5_lmmr3 ka0302$r_slot5_lmmr3_overlay.ka0302$l_slot5_lmmr3n#define ka0302$v_slot5_lmmr3_en ka0302$r_slot5_lmmr3_overlay.ka0302$r_slot5_lmmr3_bits.ka0302$v_slot5_lmmr3_enp#define ka0302$v_slot5_lmmr3_int ka0302$r_slot5_lmmr3_overlay.ka0302$r_slot5_li,mmr3_bits.ka0302$v_slot5_lmmr3_intn#define ka0302$v_slot5_lmmr3_ia ka0302$r_slot5_lmmr3_overlay.ka0302$r_slot5_lmmr3_bits.ka0302$v_slot5_lmmr3_ian#define ka0302$v_slot5_lmmr3_aw ka0302$r_slot5_lmmr3_overlay.ka0302$r_slot5_lmmr3_bits.ka0302$v_slot5_lmmr3_awv#define ka0302$v_slot5_lmmr3_nbanks ka0302$r_slot5_lmmr3_overlay.ka0302$r_slot5_lmmr3_bits.ka0302$v_slot5_lmmr3_nbanksr#define ka0302$v_slot5_lmmr3_addr ka0302$r_slot5_lmmr3_overlay.ka0302$r_slot5_lmmr3_bits.ka0302$v_slot5_lmmr3_addrN#define kaj,0302$l_slot5_lmmr4 ka0302$r_slot5_lmmr4_overlay.ka0302$l_slot5_lmmr4n#define ka0302$v_slot5_lmmr4_en ka0302$r_slot5_lmmr4_overlay.ka0302$r_slot5_lmmr4_bits.ka0302$v_slot5_lmmr4_enp#define ka0302$v_slot5_lmmr4_int ka0302$r_slot5_lmmr4_overlay.ka0302$r_slot5_lmmr4_bits.ka0302$v_slot5_lmmr4_intn#define ka0302$v_slot5_lmmr4_ia ka0302$r_slot5_lmmr4_overlay.ka0302$r_slot5_lmmr4_bits.ka0302$v_slot5_lmmr4_ian#define ka0302$v_slot5_lmmr4_aw ka0302$r_slot5_lmmr4_overlay.ka0302$r_slot5_lmmr4_bits.ka0302$v_slk,ot5_lmmr4_awv#define ka0302$v_slot5_lmmr4_nbanks ka0302$r_slot5_lmmr4_overlay.ka0302$r_slot5_lmmr4_bits.ka0302$v_slot5_lmmr4_nbanksr#define ka0302$v_slot5_lmmr4_addr ka0302$r_slot5_lmmr4_overlay.ka0302$r_slot5_lmmr4_bits.ka0302$v_slot5_lmmr4_addrN#define ka0302$l_slot5_lmmr5 ka0302$r_slot5_lmmr5_overlay.ka0302$l_slot5_lmmr5n#define ka0302$v_slot5_lmmr5_en ka0302$r_slot5_lmmr5_overlay.ka0302$r_slot5_lmmr5_bits.ka0302$v_slot5_lmmr5_enp#define ka0302$v_slot5_lmmr5_int ka0302$r_slot5_lmmr5_overlay.kal,0302$r_slot5_lmmr5_bits.ka0302$v_slot5_lmmr5_intn#define ka0302$v_slot5_lmmr5_ia ka0302$r_slot5_lmmr5_overlay.ka0302$r_slot5_lmmr5_bits.ka0302$v_slot5_lmmr5_ian#define ka0302$v_slot5_lmmr5_aw ka0302$r_slot5_lmmr5_overlay.ka0302$r_slot5_lmmr5_bits.ka0302$v_slot5_lmmr5_awv#define ka0302$v_slot5_lmmr5_nbanks ka0302$r_slot5_lmmr5_overlay.ka0302$r_slot5_lmmr5_bits.ka0302$v_slot5_lmmr5_nbanksr#define ka0302$v_slot5_lmmr5_addr ka0302$r_slot5_lmmr5_overlay.ka0302$r_slot5_lmmr5_bits.ka0302$v_slot5_lmmr5_adm,drN#define ka0302$l_slot5_lmmr6 ka0302$r_slot5_lmmr6_overlay.ka0302$l_slot5_lmmr6n#define ka0302$v_slot5_lmmr6_en ka0302$r_slot5_lmmr6_overlay.ka0302$r_slot5_lmmr6_bits.ka0302$v_slot5_lmmr6_enp#define ka0302$v_slot5_lmmr6_int ka0302$r_slot5_lmmr6_overlay.ka0302$r_slot5_lmmr6_bits.ka0302$v_slot5_lmmr6_intn#define ka0302$v_slot5_lmmr6_ia ka0302$r_slot5_lmmr6_overlay.ka0302$r_slot5_lmmr6_bits.ka0302$v_slot5_lmmr6_ian#define ka0302$v_slot5_lmmr6_aw ka0302$r_slot5_lmmr6_overlay.ka0302$r_slot5_lmmr6_bin,ts.ka0302$v_slot5_lmmr6_awv#define ka0302$v_slot5_lmmr6_nbanks ka0302$r_slot5_lmmr6_overlay.ka0302$r_slot5_lmmr6_bits.ka0302$v_slot5_lmmr6_nbanksr#define ka0302$v_slot5_lmmr6_addr ka0302$r_slot5_lmmr6_overlay.ka0302$r_slot5_lmmr6_bits.ka0302$v_slot5_lmmr6_addrN#define ka0302$l_slot5_lmmr7 ka0302$r_slot5_lmmr7_overlay.ka0302$l_slot5_lmmr7n#define ka0302$v_slot5_lmmr7_en ka0302$r_slot5_lmmr7_overlay.ka0302$r_slot5_lmmr7_bits.ka0302$v_slot5_lmmr7_enp#define ka0302$v_slot5_lmmr7_int ka0302$r_slot5_lmo,mr7_overlay.ka0302$r_slot5_lmmr7_bits.ka0302$v_slot5_lmmr7_intn#define ka0302$v_slot5_lmmr7_ia ka0302$r_slot5_lmmr7_overlay.ka0302$r_slot5_lmmr7_bits.ka0302$v_slot5_lmmr7_ian#define ka0302$v_slot5_lmmr7_aw ka0302$r_slot5_lmmr7_overlay.ka0302$r_slot5_lmmr7_bits.ka0302$v_slot5_lmmr7_awv#define ka0302$v_slot5_lmmr7_nbanks ka0302$r_slot5_lmmr7_overlay.ka0302$r_slot5_lmmr7_bits.ka0302$v_slot5_lmmr7_nbanksr#define ka0302$v_slot5_lmmr7_addr ka0302$r_slot5_lmmr7_overlay.ka0302$r_slot5_lmmr7_bits.ka0302$v_p,slot5_lmmr7_addrQ#define ka0302$l_slot5_lbesr0 ka0302$r_slot5_lbesr0_overlay.ka0302$l_slot5_lbesr0~#define ka0302$v_slot5_lbesr0_syndrome ka0302$r_slot5_lbesr0_overlay.ka0302$r_slot5_lbesr0_bits.ka0302$v_slot5_lbesr0_syndromeQ#define ka0302$l_slot5_lbesr1 ka0302$r_slot5_lbesr1_overlay.ka0302$l_slot5_lbesr1~#define ka0302$v_slot5_lbesr1_syndrome ka0302$r_slot5_lbesr1_overlay.ka0302$r_slot5_lbesr1_bits.ka0302$v_slot5_lbesr1_syndromeQ#define ka0302$l_slot5_lbesr2 ka0302$r_slot5_lbesr2_overlay.ka03q,02$l_slot5_lbesr2~#define ka0302$v_slot5_lbesr2_syndrome ka0302$r_slot5_lbesr2_overlay.ka0302$r_slot5_lbesr2_bits.ka0302$v_slot5_lbesr2_syndromeQ#define ka0302$l_slot5_lbesr3 ka0302$r_slot5_lbesr3_overlay.ka0302$l_slot5_lbesr3~#define ka0302$v_slot5_lbesr3_syndrome ka0302$r_slot5_lbesr3_overlay.ka0302$r_slot5_lbesr3_bits.ka0302$v_slot5_lbesr3_syndromeQ#define ka0302$l_slot5_lbecr0 ka0302$r_slot5_lbecr0_overlay.ka0302$l_slot5_lbecr0r#define ka0302$l_slot5_lbecr0_ca ka0302$r_slot5_lbecr0_overlayr,.ka0302$r_slot5_lbecr0_bits.ka0302$l_slot5_lbecr0_caQ#define ka0302$l_slot5_lbecr1 ka0302$r_slot5_lbecr1_overlay.ka0302$l_slot5_lbecr1r#define ka0302$v_slot5_lbecr1_ca ka0302$r_slot5_lbecr1_overlay.ka0302$r_slot5_lbecr1_bits.ka0302$v_slot5_lbecr1_cat#define ka0302$v_slot5_lbecr1_cid ka0302$r_slot5_lbecr1_overlay.ka0302$r_slot5_lbecr1_bits.ka0302$v_slot5_lbecr1_cidt#define ka0302$v_slot5_lbecr1_rid ka0302$r_slot5_lbecr1_overlay.ka0302$r_slot5_lbecr1_bits.ka0302$v_slot5_lbecr1_ridt#define ka0302$vs,_slot5_lbecr1_cnf ka0302$r_slot5_lbecr1_overlay.ka0302$r_slot5_lbecr1_bits.ka0302$v_slot5_lbecr1_cnfz#define ka0302$v_slot5_lbecr1_shared ka0302$r_slot5_lbecr1_overlay.ka0302$r_slot5_lbecr1_bits.ka0302$v_slot5_lbecr1_sharedx#define ka0302$v_slot5_lbecr1_dirty ka0302$r_slot5_lbecr1_overlay.ka0302$r_slot5_lbecr1_bits.ka0302$v_slot5_lbecr1_dirtyz#define ka0302$v_slot5_lbecr1_dcycle ka0302$r_slot5_lbecr1_overlay.ka0302$r_slot5_lbecr1_bits.ka0302$v_slot5_lbecr1_dcycleN#define ka0302$l_slot5_lmode ka030t,2$r_slot5_lmode_overlay.ka0302$l_slot5_lmodeN#define ka0302$l_slot5_lmerr ka0302$r_slot5_lmerr_overlay.ka0302$l_slot5_lmerrN#define ka0302$l_slot5_llock ka0302$r_slot5_llock_overlay.ka0302$l_slot5_llockN#define ka0302$l_slot5_ledto ka0302$r_slot5_ledto_overlay.ka0302$l_slot5_ledtoN#define ka0302$l_slot5_ldiag ka0302$r_slot5_ldiag_overlay.ka0302$l_slot5_ldiagN#define ka0302$l_slot5_ltaga ka0302$r_slot5_ltaga_overlay.ka0302$l_slot5_ltagaN#define ka0302$l_slot5_ltagw ka0302$r_slot5_ltagw_overlay.kau,0302$l_slot5_ltagwN#define ka0302$l_slot5_lcon0 ka0302$r_slot5_lcon0_overlay.ka0302$l_slot5_lcon0N#define ka0302$l_slot5_lcon1 ka0302$r_slot5_lcon1_overlay.ka0302$l_slot5_lcon1N#define ka0302$l_slot5_lperf ka0302$r_slot5_lperf_overlay.ka0302$l_slot5_lperfQ#define ka0302$l_slot5_lcntr0 ka0302$r_slot5_lcntr0_overlay.ka0302$l_slot5_lcntr0Q#define ka0302$l_slot5_lcntr1 ka0302$r_slot5_lcntr1_overlay.ka0302$l_slot5_lcntr1Z#define ka0302$l_slot5_lmissaddr ka0302$r_slot5_lmissaddr_overlay.ka0302$l_slov,t5_lmissaddrH#define ka0302$l_slot5_mcr ka0302$r_slot5_mcr_overlay.ka0302$l_slot5_mcrH#define ka0302$l_slot5_amr ka0302$r_slot5_amr_overlay.ka0302$l_slot5_amrN#define ka0302$l_slot5_mstr0 ka0302$r_slot5_mstr0_overlay.ka0302$l_slot5_mstr0N#define ka0302$l_slot5_mstr1 ka0302$r_slot5_mstr1_overlay.ka0302$l_slot5_mstr1K#define ka0302$l_slot5_fadr ka0302$r_slot5_fadr_overlay.ka0302$l_slot5_fadrK#define ka0302$l_slot5_mera ka0302$r_slot5_mera_overlay.ka0302$l_slot5_meraQ#define ka0302$l_slot5_msyndw,a ka0302$r_slot5_msynda_overlay.ka0302$l_slot5_msyndaK#define ka0302$l_slot5_mdra ka0302$r_slot5_mdra_overlay.ka0302$l_slot5_mdraN#define ka0302$l_slot5_mcbsa ka0302$r_slot5_mcbsa_overlay.ka0302$l_slot5_mcbsaK#define ka0302$l_slot5_merb ka0302$r_slot5_merb_overlay.ka0302$l_slot5_merbQ#define ka0302$l_slot5_msyndb ka0302$r_slot5_msyndb_overlay.ka0302$l_slot5_msyndbK#define ka0302$l_slot5_mdrb ka0302$r_slot5_mdrb_overlay.ka0302$l_slot5_mdrbN#define ka0302$l_slot5_mcbsb ka0302$r_slot5_mcbsb_ovx,erlay.ka0302$l_slot5_mcbsbK#define ka0302$l_slot6_ldev ka0302$r_slot6_ldev_overlay.ka0302$l_slot6_ldevp#define ka0302$v_slot6_ldev_dtype ka0302$r_slot6_ldev_overlay.ka0302$r_slot6_ldev_bits.ka0302$v_slot6_ldev_dtypen#define ka0302$v_slot6_ldev_drev ka0302$r_slot6_ldev_overlay.ka0302$r_slot6_ldev_bits.ka0302$v_slot6_ldev_drevK#define ka0302$l_slot6_lber ka0302$r_slot6_lber_overlay.ka0302$l_slot6_lberh#define ka0302$v_slot6_lber_e ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_sloty,6_lber_el#define ka0302$v_slot6_lber_uce ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_ucen#define ka0302$v_slot6_lber_uce2 ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_uce2j#define ka0302$v_slot6_lber_ce ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_cel#define ka0302$v_slot6_lber_ce2 ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_ce2l#define ka0302$v_slot6_lber_cpe ka0302$r_slot6_lber_overz,lay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_cpen#define ka0302$v_slot6_lber_cpe2 ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_cpe2n#define ka0302$v_slot6_lber_cdpe ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_cdpep#define ka0302$v_slot6_lber_cdpe2 ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_cdpe2l#define ka0302$v_slot6_lber_tde ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_tdel#def{,ine ka0302$v_slot6_lber_ste ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_sten#define ka0302$v_slot6_lber_cnfe ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_cnfen#define ka0302$v_slot6_lber_nxae ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_nxael#define ka0302$v_slot6_lber_cae ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_cael#define ka0302$v_slot6_lber_she ka0302$r_slot6_lber_overlay.ka0302|,$r_slot6_lber_bits.ka0302$v_slot6_lber_shel#define ka0302$v_slot6_lber_die ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_dien#define ka0302$v_slot6_lber_dtce ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_dtcen#define ka0302$v_slot6_lber_ctce ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_ctcen#define ka0302$v_slot6_lber_nses ka0302$r_slot6_lber_overlay.ka0302$r_slot6_lber_bits.ka0302$v_slot6_lber_nsesK#define ka0302$l},_slot6_lcnr ka0302$r_slot6_lcnr_overlay.ka0302$l_slot6_lcnrn#define ka0302$v_slot6_lcnr_ceen ka0302$r_slot6_lcnr_overlay.ka0302$r_slot6_lcnr_bits.ka0302$v_slot6_lcnr_ceent#define ka0302$v_slot6_lcnr_rststat ka0302$r_slot6_lcnr_overlay.ka0302$r_slot6_lcnr_bits.ka0302$v_slot6_lcnr_rststatp#define ka0302$v_slot6_lcnr_nhalt ka0302$r_slot6_lcnr_overlay.ka0302$r_slot6_lcnr_bits.ka0302$v_slot6_lcnr_nhaltn#define ka0302$v_slot6_lcnr_nrst ka0302$r_slot6_lcnr_overlay.ka0302$r_slot6_lcnr_bits.ka0302$v_slot6~,_lcnr_nrstl#define ka0302$v_slot6_lcnr_stf ka0302$r_slot6_lcnr_overlay.ka0302$r_slot6_lcnr_bits.ka0302$v_slot6_lcnr_stfH#define ka0302$l_slot6_ibr ka0302$r_slot6_ibr_overlay.ka0302$l_slot6_ibrr#define ka0302$v_slot6_ibr_rcv_sdat ka0302$r_slot6_ibr_overlay.ka0302$r_slot6_ibr_bits.ka0302$v_slot6_ibr_rcv_sdatr#define ka0302$v_slot6_ibr_xmt_sdat ka0302$r_slot6_ibr_overlay.ka0302$r_slot6_ibr_bits.ka0302$v_slot6_ibr_xmt_sdatj#define ka0302$v_slot6_ibr_sclk ka0302$r_slot6_ibr_overlay.ka0302$r_slot6_ibr_,bits.ka0302$v_slot6_ibr_sclkN#define ka0302$l_slot6_lmmr0 ka0302$r_slot6_lmmr0_overlay.ka0302$l_slot6_lmmr0n#define ka0302$v_slot6_lmmr0_en ka0302$r_slot6_lmmr0_overlay.ka0302$r_slot6_lmmr0_bits.ka0302$v_slot6_lmmr0_enp#define ka0302$v_slot6_lmmr0_int ka0302$r_slot6_lmmr0_overlay.ka0302$r_slot6_lmmr0_bits.ka0302$v_slot6_lmmr0_intn#define ka0302$v_slot6_lmmr0_ia ka0302$r_slot6_lmmr0_overlay.ka0302$r_slot6_lmmr0_bits.ka0302$v_slot6_lmmr0_ian#define ka0302$v_slot6_lmmr0_aw ka0302$r_slot6_lmmr0_overl,ay.ka0302$r_slot6_lmmr0_bits.ka0302$v_slot6_lmmr0_awv#define ka0302$v_slot6_lmmr0_nbanks ka0302$r_slot6_lmmr0_overlay.ka0302$r_slot6_lmmr0_bits.ka0302$v_slot6_lmmr0_nbanksr#define ka0302$v_slot6_lmmr0_addr ka0302$r_slot6_lmmr0_overlay.ka0302$r_slot6_lmmr0_bits.ka0302$v_slot6_lmmr0_addrN#define ka0302$l_slot6_lmmr1 ka0302$r_slot6_lmmr1_overlay.ka0302$l_slot6_lmmr1n#define ka0302$v_slot6_lmmr1_en ka0302$r_slot6_lmmr1_overlay.ka0302$r_slot6_lmmr1_bits.ka0302$v_slot6_lmmr1_enp#define ka0302$v_slot6_l,mmr1_int ka0302$r_slot6_lmmr1_overlay.ka0302$r_slot6_lmmr1_bits.ka0302$v_slot6_lmmr1_intn#define ka0302$v_slot6_lmmr1_ia ka0302$r_slot6_lmmr1_overlay.ka0302$r_slot6_lmmr1_bits.ka0302$v_slot6_lmmr1_ian#define ka0302$v_slot6_lmmr1_aw ka0302$r_slot6_lmmr1_overlay.ka0302$r_slot6_lmmr1_bits.ka0302$v_slot6_lmmr1_awv#define ka0302$v_slot6_lmmr1_nbanks ka0302$r_slot6_lmmr1_overlay.ka0302$r_slot6_lmmr1_bits.ka0302$v_slot6_lmmr1_nbanksr#define ka0302$v_slot6_lmmr1_addr ka0302$r_slot6_lmmr1_overlay.ka0302$r_,slot6_lmmr1_bits.ka0302$v_slot6_lmmr1_addrN#define ka0302$l_slot6_lmmr2 ka0302$r_slot6_lmmr2_overlay.ka0302$l_slot6_lmmr2n#define ka0302$v_slot6_lmmr2_en ka0302$r_slot6_lmmr2_overlay.ka0302$r_slot6_lmmr2_bits.ka0302$v_slot6_lmmr2_enp#define ka0302$v_slot6_lmmr2_int ka0302$r_slot6_lmmr2_overlay.ka0302$r_slot6_lmmr2_bits.ka0302$v_slot6_lmmr2_intn#define ka0302$v_slot6_lmmr2_ia ka0302$r_slot6_lmmr2_overlay.ka0302$r_slot6_lmmr2_bits.ka0302$v_slot6_lmmr2_ian#define ka0302$v_slot6_lmmr2_aw ka0302$r_slo,t6_lmmr2_overlay.ka0302$r_slot6_lmmr2_bits.ka0302$v_slot6_lmmr2_awv#define ka0302$v_slot6_lmmr2_nbanks ka0302$r_slot6_lmmr2_overlay.ka0302$r_slot6_lmmr2_bits.ka0302$v_slot6_lmmr2_nbanksr#define ka0302$v_slot6_lmmr2_addr ka0302$r_slot6_lmmr2_overlay.ka0302$r_slot6_lmmr2_bits.ka0302$v_slot6_lmmr2_addrN#define ka0302$l_slot6_lmmr3 ka0302$r_slot6_lmmr3_overlay.ka0302$l_slot6_lmmr3n#define ka0302$v_slot6_lmmr3_en ka0302$r_slot6_lmmr3_overlay.ka0302$r_slot6_lmmr3_bits.ka0302$v_slot6_lmmr3_enp#define ka,0302$v_slot6_lmmr3_int ka0302$r_slot6_lmmr3_overlay.ka0302$r_slot6_lmmr3_bits.ka0302$v_slot6_lmmr3_intn#define ka0302$v_slot6_lmmr3_ia ka0302$r_slot6_lmmr3_overlay.ka0302$r_slot6_lmmr3_bits.ka0302$v_slot6_lmmr3_ian#define ka0302$v_slot6_lmmr3_aw ka0302$r_slot6_lmmr3_overlay.ka0302$r_slot6_lmmr3_bits.ka0302$v_slot6_lmmr3_awv#define ka0302$v_slot6_lmmr3_nbanks ka0302$r_slot6_lmmr3_overlay.ka0302$r_slot6_lmmr3_bits.ka0302$v_slot6_lmmr3_nbanksr#define ka0302$v_slot6_lmmr3_addr ka0302$r_slot6_lmmr3_ove,rlay.ka0302$r_slot6_lmmr3_bits.ka0302$v_slot6_lmmr3_addrN#define ka0302$l_slot6_lmmr4 ka0302$r_slot6_lmmr4_overlay.ka0302$l_slot6_lmmr4n#define ka0302$v_slot6_lmmr4_en ka0302$r_slot6_lmmr4_overlay.ka0302$r_slot6_lmmr4_bits.ka0302$v_slot6_lmmr4_enp#define ka0302$v_slot6_lmmr4_int ka0302$r_slot6_lmmr4_overlay.ka0302$r_slot6_lmmr4_bits.ka0302$v_slot6_lmmr4_intn#define ka0302$v_slot6_lmmr4_ia ka0302$r_slot6_lmmr4_overlay.ka0302$r_slot6_lmmr4_bits.ka0302$v_slot6_lmmr4_ian#define ka0302$v_slot6_lmmr4_a,w ka0302$r_slot6_lmmr4_overlay.ka0302$r_slot6_lmmr4_bits.ka0302$v_slot6_lmmr4_awv#define ka0302$v_slot6_lmmr4_nbanks ka0302$r_slot6_lmmr4_overlay.ka0302$r_slot6_lmmr4_bits.ka0302$v_slot6_lmmr4_nbanksr#define ka0302$v_slot6_lmmr4_addr ka0302$r_slot6_lmmr4_overlay.ka0302$r_slot6_lmmr4_bits.ka0302$v_slot6_lmmr4_addrN#define ka0302$l_slot6_lmmr5 ka0302$r_slot6_lmmr5_overlay.ka0302$l_slot6_lmmr5n#define ka0302$v_slot6_lmmr5_en ka0302$r_slot6_lmmr5_overlay.ka0302$r_slot6_lmmr5_bits.ka0302$v_slot6_lmmr5_,enp#define ka0302$v_slot6_lmmr5_int ka0302$r_slot6_lmmr5_overlay.ka0302$r_slot6_lmmr5_bits.ka0302$v_slot6_lmmr5_intn#define ka0302$v_slot6_lmmr5_ia ka0302$r_slot6_lmmr5_overlay.ka0302$r_slot6_lmmr5_bits.ka0302$v_slot6_lmmr5_ian#define ka0302$v_slot6_lmmr5_aw ka0302$r_slot6_lmmr5_overlay.ka0302$r_slot6_lmmr5_bits.ka0302$v_slot6_lmmr5_awv#define ka0302$v_slot6_lmmr5_nbanks ka0302$r_slot6_lmmr5_overlay.ka0302$r_slot6_lmmr5_bits.ka0302$v_slot6_lmmr5_nbanksr#define ka0302$v_slot6_lmmr5_addr ka0302$r_s,lot6_lmmr5_overlay.ka0302$r_slot6_lmmr5_bits.ka0302$v_slot6_lmmr5_addrN#define ka0302$l_slot6_lmmr6 ka0302$r_slot6_lmmr6_overlay.ka0302$l_slot6_lmmr6n#define ka0302$v_slot6_lmmr6_en ka0302$r_slot6_lmmr6_overlay.ka0302$r_slot6_lmmr6_bits.ka0302$v_slot6_lmmr6_enp#define ka0302$v_slot6_lmmr6_int ka0302$r_slot6_lmmr6_overlay.ka0302$r_slot6_lmmr6_bits.ka0302$v_slot6_lmmr6_intn#define ka0302$v_slot6_lmmr6_ia ka0302$r_slot6_lmmr6_overlay.ka0302$r_slot6_lmmr6_bits.ka0302$v_slot6_lmmr6_ian#define ka0302$v,_slot6_lmmr6_aw ka0302$r_slot6_lmmr6_overlay.ka0302$r_slot6_lmmr6_bits.ka0302$v_slot6_lmmr6_awv#define ka0302$v_slot6_lmmr6_nbanks ka0302$r_slot6_lmmr6_overlay.ka0302$r_slot6_lmmr6_bits.ka0302$v_slot6_lmmr6_nbanksr#define ka0302$v_slot6_lmmr6_addr ka0302$r_slot6_lmmr6_overlay.ka0302$r_slot6_lmmr6_bits.ka0302$v_slot6_lmmr6_addrN#define ka0302$l_slot6_lmmr7 ka0302$r_slot6_lmmr7_overlay.ka0302$l_slot6_lmmr7n#define ka0302$v_slot6_lmmr7_en ka0302$r_slot6_lmmr7_overlay.ka0302$r_slot6_lmmr7_bits.ka0302$,v_slot6_lmmr7_enp#define ka0302$v_slot6_lmmr7_int ka0302$r_slot6_lmmr7_overlay.ka0302$r_slot6_lmmr7_bits.ka0302$v_slot6_lmmr7_intn#define ka0302$v_slot6_lmmr7_ia ka0302$r_slot6_lmmr7_overlay.ka0302$r_slot6_lmmr7_bits.ka0302$v_slot6_lmmr7_ian#define ka0302$v_slot6_lmmr7_aw ka0302$r_slot6_lmmr7_overlay.ka0302$r_slot6_lmmr7_bits.ka0302$v_slot6_lmmr7_awv#define ka0302$v_slot6_lmmr7_nbanks ka0302$r_slot6_lmmr7_overlay.ka0302$r_slot6_lmmr7_bits.ka0302$v_slot6_lmmr7_nbanksr#define ka0302$v_slot6_lmmr7_a,ddr ka0302$r_slot6_lmmr7_overlay.ka0302$r_slot6_lmmr7_bits.ka0302$v_slot6_lmmr7_addrQ#define ka0302$l_slot6_lbesr0 ka0302$r_slot6_lbesr0_overlay.ka0302$l_slot6_lbesr0~#define ka0302$v_slot6_lbesr0_syndrome ka0302$r_slot6_lbesr0_overlay.ka0302$r_slot6_lbesr0_bits.ka0302$v_slot6_lbesr0_syndromeQ#define ka0302$l_slot6_lbesr1 ka0302$r_slot6_lbesr1_overlay.ka0302$l_slot6_lbesr1~#define ka0302$v_slot6_lbesr1_syndrome ka0302$r_slot6_lbesr1_overlay.ka0302$r_slot6_lbesr1_bits.ka0302$v_slot6_lbesr1_syndro,meQ#define ka0302$l_slot6_lbesr2 ka0302$r_slot6_lbesr2_overlay.ka0302$l_slot6_lbesr2~#define ka0302$v_slot6_lbesr2_syndrome ka0302$r_slot6_lbesr2_overlay.ka0302$r_slot6_lbesr2_bits.ka0302$v_slot6_lbesr2_syndromeQ#define ka0302$l_slot6_lbesr3 ka0302$r_slot6_lbesr3_overlay.ka0302$l_slot6_lbesr3~#define ka0302$v_slot6_lbesr3_syndrome ka0302$r_slot6_lbesr3_overlay.ka0302$r_slot6_lbesr3_bits.ka0302$v_slot6_lbesr3_syndromeQ#define ka0302$l_slot6_lbecr0 ka0302$r_slot6_lbecr0_overlay.ka0302$l_slot6_lbe,cr0r#define ka0302$l_slot6_lbecr0_ca ka0302$r_slot6_lbecr0_overlay.ka0302$r_slot6_lbecr0_bits.ka0302$l_slot6_lbecr0_caQ#define ka0302$l_slot6_lbecr1 ka0302$r_slot6_lbecr1_overlay.ka0302$l_slot6_lbecr1r#define ka0302$v_slot6_lbecr1_ca ka0302$r_slot6_lbecr1_overlay.ka0302$r_slot6_lbecr1_bits.ka0302$v_slot6_lbecr1_cat#define ka0302$v_slot6_lbecr1_cid ka0302$r_slot6_lbecr1_overlay.ka0302$r_slot6_lbecr1_bits.ka0302$v_slot6_lbecr1_cidt#define ka0302$v_slot6_lbecr1_rid ka0302$r_slot6_lbecr1_overlay.ka,0302$r_slot6_lbecr1_bits.ka0302$v_slot6_lbecr1_ridt#define ka0302$v_slot6_lbecr1_cnf ka0302$r_slot6_lbecr1_overlay.ka0302$r_slot6_lbecr1_bits.ka0302$v_slot6_lbecr1_cnfz#define ka0302$v_slot6_lbecr1_shared ka0302$r_slot6_lbecr1_overlay.ka0302$r_slot6_lbecr1_bits.ka0302$v_slot6_lbecr1_sharedx#define ka0302$v_slot6_lbecr1_dirty ka0302$r_slot6_lbecr1_overlay.ka0302$r_slot6_lbecr1_bits.ka0302$v_slot6_lbecr1_dirtyz#define ka0302$v_slot6_lbecr1_dcycle ka0302$r_slot6_lbecr1_overlay.ka0302$r_slot6_lbecr1_b,its.ka0302$v_slot6_lbecr1_dcycleN#define ka0302$l_slot6_lmode ka0302$r_slot6_lmode_overlay.ka0302$l_slot6_lmodeN#define ka0302$l_slot6_lmerr ka0302$r_slot6_lmerr_overlay.ka0302$l_slot6_lmerrN#define ka0302$l_slot6_llock ka0302$r_slot6_llock_overlay.ka0302$l_slot6_llockN#define ka0302$l_slot6_ledto ka0302$r_slot6_ledto_overlay.ka0302$l_slot6_ledtoN#define ka0302$l_slot6_ldiag ka0302$r_slot6_ldiag_overlay.ka0302$l_slot6_ldiagN#define ka0302$l_slot6_ltaga ka0302$r_slot6_ltaga_overlay.ka0302$l_slot6,_ltagaN#define ka0302$l_slot6_ltagw ka0302$r_slot6_ltagw_overlay.ka0302$l_slot6_ltagwN#define ka0302$l_slot6_lcon0 ka0302$r_slot6_lcon0_overlay.ka0302$l_slot6_lcon0N#define ka0302$l_slot6_lcon1 ka0302$r_slot6_lcon1_overlay.ka0302$l_slot6_lcon1N#define ka0302$l_slot6_lperf ka0302$r_slot6_lperf_overlay.ka0302$l_slot6_lperfQ#define ka0302$l_slot6_lcntr0 ka0302$r_slot6_lcntr0_overlay.ka0302$l_slot6_lcntr0Q#define ka0302$l_slot6_lcntr1 ka0302$r_slot6_lcntr1_overlay.ka0302$l_slot6_lcntr1Z#define ka,0302$l_slot6_lmissaddr ka0302$r_slot6_lmissaddr_overlay.ka0302$l_slot6_lmissaddrH#define ka0302$l_slot6_mcr ka0302$r_slot6_mcr_overlay.ka0302$l_slot6_mcrH#define ka0302$l_slot6_amr ka0302$r_slot6_amr_overlay.ka0302$l_slot6_amrN#define ka0302$l_slot6_mstr0 ka0302$r_slot6_mstr0_overlay.ka0302$l_slot6_mstr0N#define ka0302$l_slot6_mstr1 ka0302$r_slot6_mstr1_overlay.ka0302$l_slot6_mstr1K#define ka0302$l_slot6_fadr ka0302$r_slot6_fadr_overlay.ka0302$l_slot6_fadrK#define ka0302$l_slot6_mera ka0302$r_s,lot6_mera_overlay.ka0302$l_slot6_meraQ#define ka0302$l_slot6_msynda ka0302$r_slot6_msynda_overlay.ka0302$l_slot6_msyndaK#define ka0302$l_slot6_mdra ka0302$r_slot6_mdra_overlay.ka0302$l_slot6_mdraN#define ka0302$l_slot6_mcbsa ka0302$r_slot6_mcbsa_overlay.ka0302$l_slot6_mcbsaK#define ka0302$l_slot6_merb ka0302$r_slot6_merb_overlay.ka0302$l_slot6_merbQ#define ka0302$l_slot6_msyndb ka0302$r_slot6_msyndb_overlay.ka0302$l_slot6_msyndbK#define ka0302$l_slot6_mdrb ka0302$r_slot6_mdrb_overlay.ka0302,$l_slot6_mdrbN#define ka0302$l_slot6_mcbsb ka0302$r_slot6_mcbsb_overlay.ka0302$l_slot6_mcbsbK#define ka0302$l_slot7_ldev ka0302$r_slot7_ldev_overlay.ka0302$l_slot7_ldevp#define ka0302$v_slot7_ldev_dtype ka0302$r_slot7_ldev_overlay.ka0302$r_slot7_ldev_bits.ka0302$v_slot7_ldev_dtypen#define ka0302$v_slot7_ldev_drev ka0302$r_slot7_ldev_overlay.ka0302$r_slot7_ldev_bits.ka0302$v_slot7_ldev_drevK#define ka0302$l_slot7_lber ka0302$r_slot7_lber_overlay.ka0302$l_slot7_lberh#define ka0302$v_slot7_lber_,e ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_el#define ka0302$v_slot7_lber_uce ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_ucen#define ka0302$v_slot7_lber_uce2 ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_uce2j#define ka0302$v_slot7_lber_ce ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_cel#define ka0302$v_slot7_lber_ce2 ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot,7_lber_ce2l#define ka0302$v_slot7_lber_cpe ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_cpen#define ka0302$v_slot7_lber_cpe2 ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_cpe2n#define ka0302$v_slot7_lber_cdpe ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_cdpep#define ka0302$v_slot7_lber_cdpe2 ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_cdpe2l#define ka0302$v_slot7_lber_tde ka0302$r_slot7,_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_tdel#define ka0302$v_slot7_lber_ste ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_sten#define ka0302$v_slot7_lber_cnfe ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_cnfen#define ka0302$v_slot7_lber_nxae ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_nxael#define ka0302$v_slot7_lber_cae ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_cae,l#define ka0302$v_slot7_lber_she ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_shel#define ka0302$v_slot7_lber_die ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_dien#define ka0302$v_slot7_lber_dtce ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_dtcen#define ka0302$v_slot7_lber_ctce ka0302$r_slot7_lber_overlay.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_ctcen#define ka0302$v_slot7_lber_nses ka0302$r_slot7_lber_overlay,.ka0302$r_slot7_lber_bits.ka0302$v_slot7_lber_nsesK#define ka0302$l_slot7_lcnr ka0302$r_slot7_lcnr_overlay.ka0302$l_slot7_lcnrn#define ka0302$v_slot7_lcnr_ceen ka0302$r_slot7_lcnr_overlay.ka0302$r_slot7_lcnr_bits.ka0302$v_slot7_lcnr_ceent#define ka0302$v_slot7_lcnr_rststat ka0302$r_slot7_lcnr_overlay.ka0302$r_slot7_lcnr_bits.ka0302$v_slot7_lcnr_rststatp#define ka0302$v_slot7_lcnr_nhalt ka0302$r_slot7_lcnr_overlay.ka0302$r_slot7_lcnr_bits.ka0302$v_slot7_lcnr_nhaltn#define ka0302$v_slot7_lcnr_nrst, ka0302$r_slot7_lcnr_overlay.ka0302$r_slot7_lcnr_bits.ka0302$v_slot7_lcnr_nrstl#define ka0302$v_slot7_lcnr_stf ka0302$r_slot7_lcnr_overlay.ka0302$r_slot7_lcnr_bits.ka0302$v_slot7_lcnr_stfH#define ka0302$l_slot7_ibr ka0302$r_slot7_ibr_overlay.ka0302$l_slot7_ibrr#define ka0302$v_slot7_ibr_rcv_sdat ka0302$r_slot7_ibr_overlay.ka0302$r_slot7_ibr_bits.ka0302$v_slot7_ibr_rcv_sdatr#define ka0302$v_slot7_ibr_xmt_sdat ka0302$r_slot7_ibr_overlay.ka0302$r_slot7_ibr_bits.ka0302$v_slot7_ibr_xmt_sdatj#define ka,0302$v_slot7_ibr_sclk ka0302$r_slot7_ibr_overlay.ka0302$r_slot7_ibr_bits.ka0302$v_slot7_ibr_sclkN#define ka0302$l_slot7_lmmr0 ka0302$r_slot7_lmmr0_overlay.ka0302$l_slot7_lmmr0n#define ka0302$v_slot7_lmmr0_en ka0302$r_slot7_lmmr0_overlay.ka0302$r_slot7_lmmr0_bits.ka0302$v_slot7_lmmr0_enp#define ka0302$v_slot7_lmmr0_int ka0302$r_slot7_lmmr0_overlay.ka0302$r_slot7_lmmr0_bits.ka0302$v_slot7_lmmr0_intn#define ka0302$v_slot7_lmmr0_ia ka0302$r_slot7_lmmr0_overlay.ka0302$r_slot7_lmmr0_bits.ka0302$v_slot7_,lmmr0_ian#define ka0302$v_slot7_lmmr0_aw ka0302$r_slot7_lmmr0_overlay.ka0302$r_slot7_lmmr0_bits.ka0302$v_slot7_lmmr0_awv#define ka0302$v_slot7_lmmr0_nbanks ka0302$r_slot7_lmmr0_overlay.ka0302$r_slot7_lmmr0_bits.ka0302$v_slot7_lmmr0_nbanksr#define ka0302$v_slot7_lmmr0_addr ka0302$r_slot7_lmmr0_overlay.ka0302$r_slot7_lmmr0_bits.ka0302$v_slot7_lmmr0_addrN#define ka0302$l_slot7_lmmr1 ka0302$r_slot7_lmmr1_overlay.ka0302$l_slot7_lmmr1n#define ka0302$v_slot7_lmmr1_en ka0302$r_slot7_lmmr1_overlay.ka0302$,r_slot7_lmmr1_bits.ka0302$v_slot7_lmmr1_enp#define ka0302$v_slot7_lmmr1_int ka0302$r_slot7_lmmr1_overlay.ka0302$r_slot7_lmmr1_bits.ka0302$v_slot7_lmmr1_intn#define ka0302$v_slot7_lmmr1_ia ka0302$r_slot7_lmmr1_overlay.ka0302$r_slot7_lmmr1_bits.ka0302$v_slot7_lmmr1_ian#define ka0302$v_slot7_lmmr1_aw ka0302$r_slot7_lmmr1_overlay.ka0302$r_slot7_lmmr1_bits.ka0302$v_slot7_lmmr1_awv#define ka0302$v_slot7_lmmr1_nbanks ka0302$r_slot7_lmmr1_overlay.ka0302$r_slot7_lmmr1_bits.ka0302$v_slot7_lmmr1_nbanksr#def,ine ka0302$v_slot7_lmmr1_addr ka0302$r_slot7_lmmr1_overlay.ka0302$r_slot7_lmmr1_bits.ka0302$v_slot7_lmmr1_addrN#define ka0302$l_slot7_lmmr2 ka0302$r_slot7_lmmr2_overlay.ka0302$l_slot7_lmmr2n#define ka0302$v_slot7_lmmr2_en ka0302$r_slot7_lmmr2_overlay.ka0302$r_slot7_lmmr2_bits.ka0302$v_slot7_lmmr2_enp#define ka0302$v_slot7_lmmr2_int ka0302$r_slot7_lmmr2_overlay.ka0302$r_slot7_lmmr2_bits.ka0302$v_slot7_lmmr2_intn#define ka0302$v_slot7_lmmr2_ia ka0302$r_slot7_lmmr2_overlay.ka0302$r_slot7_lmmr2_bits.k,a0302$v_slot7_lmmr2_ian#define ka0302$v_slot7_lmmr2_aw ka0302$r_slot7_lmmr2_overlay.ka0302$r_slot7_lmmr2_bits.ka0302$v_slot7_lmmr2_awv#define ka0302$v_slot7_lmmr2_nbanks ka0302$r_slot7_lmmr2_overlay.ka0302$r_slot7_lmmr2_bits.ka0302$v_slot7_lmmr2_nbanksr#define ka0302$v_slot7_lmmr2_addr ka0302$r_slot7_lmmr2_overlay.ka0302$r_slot7_lmmr2_bits.ka0302$v_slot7_lmmr2_addrN#define ka0302$l_slot7_lmmr3 ka0302$r_slot7_lmmr3_overlay.ka0302$l_slot7_lmmr3n#define ka0302$v_slot7_lmmr3_en ka0302$r_slot7_lmmr3_o,verlay.ka0302$r_slot7_lmmr3_bits.ka0302$v_slot7_lmmr3_enp#define ka0302$v_slot7_lmmr3_int ka0302$r_slot7_lmmr3_overlay.ka0302$r_slot7_lmmr3_bits.ka0302$v_slot7_lmmr3_intn#define ka0302$v_slot7_lmmr3_ia ka0302$r_slot7_lmmr3_overlay.ka0302$r_slot7_lmmr3_bits.ka0302$v_slot7_lmmr3_ian#define ka0302$v_slot7_lmmr3_aw ka0302$r_slot7_lmmr3_overlay.ka0302$r_slot7_lmmr3_bits.ka0302$v_slot7_lmmr3_awv#define ka0302$v_slot7_lmmr3_nbanks ka0302$r_slot7_lmmr3_overlay.ka0302$r_slot7_lmmr3_bits.ka0302$v_slot7_lmmr,3_nbanksr#define ka0302$v_slot7_lmmr3_addr ka0302$r_slot7_lmmr3_overlay.ka0302$r_slot7_lmmr3_bits.ka0302$v_slot7_lmmr3_addrN#define ka0302$l_slot7_lmmr4 ka0302$r_slot7_lmmr4_overlay.ka0302$l_slot7_lmmr4n#define ka0302$v_slot7_lmmr4_en ka0302$r_slot7_lmmr4_overlay.ka0302$r_slot7_lmmr4_bits.ka0302$v_slot7_lmmr4_enp#define ka0302$v_slot7_lmmr4_int ka0302$r_slot7_lmmr4_overlay.ka0302$r_slot7_lmmr4_bits.ka0302$v_slot7_lmmr4_intn#define ka0302$v_slot7_lmmr4_ia ka0302$r_slot7_lmmr4_overlay.ka0302$r_slot,7_lmmr4_bits.ka0302$v_slot7_lmmr4_ian#define ka0302$v_slot7_lmmr4_aw ka0302$r_slot7_lmmr4_overlay.ka0302$r_slot7_lmmr4_bits.ka0302$v_slot7_lmmr4_awv#define ka0302$v_slot7_lmmr4_nbanks ka0302$r_slot7_lmmr4_overlay.ka0302$r_slot7_lmmr4_bits.ka0302$v_slot7_lmmr4_nbanksr#define ka0302$v_slot7_lmmr4_addr ka0302$r_slot7_lmmr4_overlay.ka0302$r_slot7_lmmr4_bits.ka0302$v_slot7_lmmr4_addrN#define ka0302$l_slot7_lmmr5 ka0302$r_slot7_lmmr5_overlay.ka0302$l_slot7_lmmr5n#define ka0302$v_slot7_lmmr5_en ka0302$r,_slot7_lmmr5_overlay.ka0302$r_slot7_lmmr5_bits.ka0302$v_slot7_lmmr5_enp#define ka0302$v_slot7_lmmr5_int ka0302$r_slot7_lmmr5_overlay.ka0302$r_slot7_lmmr5_bits.ka0302$v_slot7_lmmr5_intn#define ka0302$v_slot7_lmmr5_ia ka0302$r_slot7_lmmr5_overlay.ka0302$r_slot7_lmmr5_bits.ka0302$v_slot7_lmmr5_ian#define ka0302$v_slot7_lmmr5_aw ka0302$r_slot7_lmmr5_overlay.ka0302$r_slot7_lmmr5_bits.ka0302$v_slot7_lmmr5_awv#define ka0302$v_slot7_lmmr5_nbanks ka0302$r_slot7_lmmr5_overlay.ka0302$r_slot7_lmmr5_bits.ka030,2$v_slot7_lmmr5_nbanksr#define ka0302$v_slot7_lmmr5_addr ka0302$r_slot7_lmmr5_overlay.ka0302$r_slot7_lmmr5_bits.ka0302$v_slot7_lmmr5_addrN#define ka0302$l_slot7_lmmr6 ka0302$r_slot7_lmmr6_overlay.ka0302$l_slot7_lmmr6n#define ka0302$v_slot7_lmmr6_en ka0302$r_slot7_lmmr6_overlay.ka0302$r_slot7_lmmr6_bits.ka0302$v_slot7_lmmr6_enp#define ka0302$v_slot7_lmmr6_int ka0302$r_slot7_lmmr6_overlay.ka0302$r_slot7_lmmr6_bits.ka0302$v_slot7_lmmr6_intn#define ka0302$v_slot7_lmmr6_ia ka0302$r_slot7_lmmr6_overlay,.ka0302$r_slot7_lmmr6_bits.ka0302$v_slot7_lmmr6_ian#define ka0302$v_slot7_lmmr6_aw ka0302$r_slot7_lmmr6_overlay.ka0302$r_slot7_lmmr6_bits.ka0302$v_slot7_lmmr6_awv#define ka0302$v_slot7_lmmr6_nbanks ka0302$r_slot7_lmmr6_overlay.ka0302$r_slot7_lmmr6_bits.ka0302$v_slot7_lmmr6_nbanksr#define ka0302$v_slot7_lmmr6_addr ka0302$r_slot7_lmmr6_overlay.ka0302$r_slot7_lmmr6_bits.ka0302$v_slot7_lmmr6_addrN#define ka0302$l_slot7_lmmr7 ka0302$r_slot7_lmmr7_overlay.ka0302$l_slot7_lmmr7n#define ka0302$v_slot7_lmm,r7_en ka0302$r_slot7_lmmr7_overlay.ka0302$r_slot7_lmmr7_bits.ka0302$v_slot7_lmmr7_enp#define ka0302$v_slot7_lmmr7_int ka0302$r_slot7_lmmr7_overlay.ka0302$r_slot7_lmmr7_bits.ka0302$v_slot7_lmmr7_intn#define ka0302$v_slot7_lmmr7_ia ka0302$r_slot7_lmmr7_overlay.ka0302$r_slot7_lmmr7_bits.ka0302$v_slot7_lmmr7_ian#define ka0302$v_slot7_lmmr7_aw ka0302$r_slot7_lmmr7_overlay.ka0302$r_slot7_lmmr7_bits.ka0302$v_slot7_lmmr7_awv#define ka0302$v_slot7_lmmr7_nbanks ka0302$r_slot7_lmmr7_overlay.ka0302$r_slot7_lm,mr7_bits.ka0302$v_slot7_lmmr7_nbanksr#define ka0302$v_slot7_lmmr7_addr ka0302$r_slot7_lmmr7_overlay.ka0302$r_slot7_lmmr7_bits.ka0302$v_slot7_lmmr7_addrQ#define ka0302$l_slot7_lbesr0 ka0302$r_slot7_lbesr0_overlay.ka0302$l_slot7_lbesr0~#define ka0302$v_slot7_lbesr0_syndrome ka0302$r_slot7_lbesr0_overlay.ka0302$r_slot7_lbesr0_bits.ka0302$v_slot7_lbesr0_syndromeQ#define ka0302$l_slot7_lbesr1 ka0302$r_slot7_lbesr1_overlay.ka0302$l_slot7_lbesr1~#define ka0302$v_slot7_lbesr1_syndrome ka0302$r_slot7_lb,esr1_overlay.ka0302$r_slot7_lbesr1_bits.ka0302$v_slot7_lbesr1_syndromeQ#define ka0302$l_slot7_lbesr2 ka0302$r_slot7_lbesr2_overlay.ka0302$l_slot7_lbesr2~#define ka0302$v_slot7_lbesr2_syndrome ka0302$r_slot7_lbesr2_overlay.ka0302$r_slot7_lbesr2_bits.ka0302$v_slot7_lbesr2_syndromeQ#define ka0302$l_slot7_lbesr3 ka0302$r_slot7_lbesr3_overlay.ka0302$l_slot7_lbesr3~#define ka0302$v_slot7_lbesr3_syndrome ka0302$r_slot7_lbesr3_overlay.ka0302$r_slot7_lbesr3_bits.ka0302$v_slot7_lbesr3_syndromeQ#define ka,0302$l_slot7_lbecr0 ka0302$r_slot7_lbecr0_overlay.ka0302$l_slot7_lbecr0r#define ka0302$l_slot7_lbecr0_ca ka0302$r_slot7_lbecr0_overlay.ka0302$r_slot7_lbecr0_bits.ka0302$l_slot7_lbecr0_caQ#define ka0302$l_slot7_lbecr1 ka0302$r_slot7_lbecr1_overlay.ka0302$l_slot7_lbecr1r#define ka0302$v_slot7_lbecr1_ca ka0302$r_slot7_lbecr1_overlay.ka0302$r_slot7_lbecr1_bits.ka0302$v_slot7_lbecr1_cat#define ka0302$v_slot7_lbecr1_cid ka0302$r_slot7_lbecr1_overlay.ka0302$r_slot7_lbecr1_bits.ka0302$v_slot7_lbecr1_cid,t#define ka0302$v_slot7_lbecr1_rid ka0302$r_slot7_lbecr1_overlay.ka0302$r_slot7_lbecr1_bits.ka0302$v_slot7_lbecr1_ridt#define ka0302$v_slot7_lbecr1_cnf ka0302$r_slot7_lbecr1_overlay.ka0302$r_slot7_lbecr1_bits.ka0302$v_slot7_lbecr1_cnfz#define ka0302$v_slot7_lbecr1_shared ka0302$r_slot7_lbecr1_overlay.ka0302$r_slot7_lbecr1_bits.ka0302$v_slot7_lbecr1_sharedx#define ka0302$v_slot7_lbecr1_dirty ka0302$r_slot7_lbecr1_overlay.ka0302$r_slot7_lbecr1_bits.ka0302$v_slot7_lbecr1_dirtyz#define ka0302$v_slot7,_lbecr1_dcycle ka0302$r_slot7_lbecr1_overlay.ka0302$r_slot7_lbecr1_bits.ka0302$v_slot7_lbecr1_dcycleN#define ka0302$l_slot7_lmode ka0302$r_slot7_lmode_overlay.ka0302$l_slot7_lmodeN#define ka0302$l_slot7_lmerr ka0302$r_slot7_lmerr_overlay.ka0302$l_slot7_lmerrN#define ka0302$l_slot7_llock ka0302$r_slot7_llock_overlay.ka0302$l_slot7_llockN#define ka0302$l_slot7_ledto ka0302$r_slot7_ledto_overlay.ka0302$l_slot7_ledtoN#define ka0302$l_slot7_ldiag ka0302$r_slot7_ldiag_overlay.ka0302$l_slot7_ldiagN#def,ine ka0302$l_slot7_ltaga ka0302$r_slot7_ltaga_overlay.ka0302$l_slot7_ltagaN#define ka0302$l_slot7_ltagw ka0302$r_slot7_ltagw_overlay.ka0302$l_slot7_ltagwN#define ka0302$l_slot7_lcon0 ka0302$r_slot7_lcon0_overlay.ka0302$l_slot7_lcon0N#define ka0302$l_slot7_lcon1 ka0302$r_slot7_lcon1_overlay.ka0302$l_slot7_lcon1N#define ka0302$l_slot7_lperf ka0302$r_slot7_lperf_overlay.ka0302$l_slot7_lperfQ#define ka0302$l_slot7_lcntr0 ka0302$r_slot7_lcntr0_overlay.ka0302$l_slot7_lcntr0Q#define ka0302$l_slot7_lcn,tr1 ka0302$r_slot7_lcntr1_overlay.ka0302$l_slot7_lcntr1Z#define ka0302$l_slot7_lmissaddr ka0302$r_slot7_lmissaddr_overlay.ka0302$l_slot7_lmissaddrH#define ka0302$l_slot7_mcr ka0302$r_slot7_mcr_overlay.ka0302$l_slot7_mcrH#define ka0302$l_slot7_amr ka0302$r_slot7_amr_overlay.ka0302$l_slot7_amrN#define ka0302$l_slot7_mstr0 ka0302$r_slot7_mstr0_overlay.ka0302$l_slot7_mstr0N#define ka0302$l_slot7_mstr1 ka0302$r_slot7_mstr1_overlay.ka0302$l_slot7_mstr1K#define ka0302$l_slot7_fadr ka0302$r_slot7_fadr_,overlay.ka0302$l_slot7_fadrK#define ka0302$l_slot7_mera ka0302$r_slot7_mera_overlay.ka0302$l_slot7_meraQ#define ka0302$l_slot7_msynda ka0302$r_slot7_msynda_overlay.ka0302$l_slot7_msyndaK#define ka0302$l_slot7_mdra ka0302$r_slot7_mdra_overlay.ka0302$l_slot7_mdraN#define ka0302$l_slot7_mcbsa ka0302$r_slot7_mcbsa_overlay.ka0302$l_slot7_mcbsaK#define ka0302$l_slot7_merb ka0302$r_slot7_merb_overlay.ka0302$l_slot7_merbQ#define ka0302$l_slot7_msyndb ka0302$r_slot7_msyndb_overlay.ka0302$l_slot7_msy,ndbK#define ka0302$l_slot7_mdrb ka0302$r_slot7_mdrb_overlay.ka0302$l_slot7_mdrbN#define ka0302$l_slot7_mcbsb ka0302$r_slot7_mcbsb_overlay.ka0302$l_slot7_mcbsbK#define ka0302$l_slot8_ldev ka0302$r_slot8_ldev_overlay.ka0302$l_slot8_ldevp#define ka0302$v_slot8_ldev_dtype ka0302$r_slot8_ldev_overlay.ka0302$r_slot8_ldev_bits.ka0302$v_slot8_ldev_dtypen#define ka0302$v_slot8_ldev_drev ka0302$r_slot8_ldev_overlay.ka0302$r_slot8_ldev_bits.ka0302$v_slot8_ldev_drevK#define ka0302$l_slot8_lber ka0302$r_s,lot8_lber_overlay.ka0302$l_slot8_lberh#define ka0302$v_slot8_lber_e ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_el#define ka0302$v_slot8_lber_uce ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_ucen#define ka0302$v_slot8_lber_uce2 ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_uce2j#define ka0302$v_slot8_lber_ce ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_cel#define ka0302$v_slot8_lber_ce,2 ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_ce2l#define ka0302$v_slot8_lber_cpe ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_cpen#define ka0302$v_slot8_lber_cpe2 ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_cpe2n#define ka0302$v_slot8_lber_cdpe ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_cdpep#define ka0302$v_slot8_lber_cdpe2 ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka030,2$v_slot8_lber_cdpe2l#define ka0302$v_slot8_lber_tde ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_tdel#define ka0302$v_slot8_lber_ste ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_sten#define ka0302$v_slot8_lber_cnfe ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_cnfen#define ka0302$v_slot8_lber_nxae ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_nxael#define ka0302$v_slot8_lber_cae ka0302$r,_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_cael#define ka0302$v_slot8_lber_she ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_shel#define ka0302$v_slot8_lber_die ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_dien#define ka0302$v_slot8_lber_dtce ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_dtcen#define ka0302$v_slot8_lber_ctce ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lbe,r_ctcen#define ka0302$v_slot8_lber_nses ka0302$r_slot8_lber_overlay.ka0302$r_slot8_lber_bits.ka0302$v_slot8_lber_nsesK#define ka0302$l_slot8_lcnr ka0302$r_slot8_lcnr_overlay.ka0302$l_slot8_lcnrn#define ka0302$v_slot8_lcnr_ceen ka0302$r_slot8_lcnr_overlay.ka0302$r_slot8_lcnr_bits.ka0302$v_slot8_lcnr_ceent#define ka0302$v_slot8_lcnr_rststat ka0302$r_slot8_lcnr_overlay.ka0302$r_slot8_lcnr_bits.ka0302$v_slot8_lcnr_rststatp#define ka0302$v_slot8_lcnr_nhalt ka0302$r_slot8_lcnr_overlay.ka0302$r_slot8_l,cnr_bits.ka0302$v_slot8_lcnr_nhaltn#define ka0302$v_slot8_lcnr_nrst ka0302$r_slot8_lcnr_overlay.ka0302$r_slot8_lcnr_bits.ka0302$v_slot8_lcnr_nrstl#define ka0302$v_slot8_lcnr_stf ka0302$r_slot8_lcnr_overlay.ka0302$r_slot8_lcnr_bits.ka0302$v_slot8_lcnr_stfH#define ka0302$l_slot8_ibr ka0302$r_slot8_ibr_overlay.ka0302$l_slot8_ibrr#define ka0302$v_slot8_ibr_rcv_sdat ka0302$r_slot8_ibr_overlay.ka0302$r_slot8_ibr_bits.ka0302$v_slot8_ibr_rcv_sdatr#define ka0302$v_slot8_ibr_xmt_sdat ka0302$r_slot8_ibr_ove,rlay.ka0302$r_slot8_ibr_bits.ka0302$v_slot8_ibr_xmt_sdatj#define ka0302$v_slot8_ibr_sclk ka0302$r_slot8_ibr_overlay.ka0302$r_slot8_ibr_bits.ka0302$v_slot8_ibr_sclkN#define ka0302$l_slot8_lmmr0 ka0302$r_slot8_lmmr0_overlay.ka0302$l_slot8_lmmr0n#define ka0302$v_slot8_lmmr0_en ka0302$r_slot8_lmmr0_overlay.ka0302$r_slot8_lmmr0_bits.ka0302$v_slot8_lmmr0_enp#define ka0302$v_slot8_lmmr0_int ka0302$r_slot8_lmmr0_overlay.ka0302$r_slot8_lmmr0_bits.ka0302$v_slot8_lmmr0_intn#define ka0302$v_slot8_lmmr0_ia ka,0302$r_slot8_lmmr0_overlay.ka0302$r_slot8_lmmr0_bits.ka0302$v_slot8_lmmr0_ian#define ka0302$v_slot8_lmmr0_aw ka0302$r_slot8_lmmr0_overlay.ka0302$r_slot8_lmmr0_bits.ka0302$v_slot8_lmmr0_awv#define ka0302$v_slot8_lmmr0_nbanks ka0302$r_slot8_lmmr0_overlay.ka0302$r_slot8_lmmr0_bits.ka0302$v_slot8_lmmr0_nbanksr#define ka0302$v_slot8_lmmr0_addr ka0302$r_slot8_lmmr0_overlay.ka0302$r_slot8_lmmr0_bits.ka0302$v_slot8_lmmr0_addrN#define ka0302$l_slot8_lmmr1 ka0302$r_slot8_lmmr1_overlay.ka0302$l_slot8_lmmr1n,#define ka0302$v_slot8_lmmr1_en ka0302$r_slot8_lmmr1_overlay.ka0302$r_slot8_lmmr1_bits.ka0302$v_slot8_lmmr1_enp#define ka0302$v_slot8_lmmr1_int ka0302$r_slot8_lmmr1_overlay.ka0302$r_slot8_lmmr1_bits.ka0302$v_slot8_lmmr1_intn#define ka0302$v_slot8_lmmr1_ia ka0302$r_slot8_lmmr1_overlay.ka0302$r_slot8_lmmr1_bits.ka0302$v_slot8_lmmr1_ian#define ka0302$v_slot8_lmmr1_aw ka0302$r_slot8_lmmr1_overlay.ka0302$r_slot8_lmmr1_bits.ka0302$v_slot8_lmmr1_awv#define ka0302$v_slot8_lmmr1_nbanks ka0302$r_slot8_lmmr1,_overlay.ka0302$r_slot8_lmmr1_bits.ka0302$v_slot8_lmmr1_nbanksr#define ka0302$v_slot8_lmmr1_addr ka0302$r_slot8_lmmr1_overlay.ka0302$r_slot8_lmmr1_bits.ka0302$v_slot8_lmmr1_addrN#define ka0302$l_slot8_lmmr2 ka0302$r_slot8_lmmr2_overlay.ka0302$l_slot8_lmmr2n#define ka0302$v_slot8_lmmr2_en ka0302$r_slot8_lmmr2_overlay.ka0302$r_slot8_lmmr2_bits.ka0302$v_slot8_lmmr2_enp#define ka0302$v_slot8_lmmr2_int ka0302$r_slot8_lmmr2_overlay.ka0302$r_slot8_lmmr2_bits.ka0302$v_slot8_lmmr2_intn#define ka0302$v_slo,t8_lmmr2_ia ka0302$r_slot8_lmmr2_overlay.ka0302$r_slot8_lmmr2_bits.ka0302$v_slot8_lmmr2_ian#define ka0302$v_slot8_lmmr2_aw ka0302$r_slot8_lmmr2_overlay.ka0302$r_slot8_lmmr2_bits.ka0302$v_slot8_lmmr2_awv#define ka0302$v_slot8_lmmr2_nbanks ka0302$r_slot8_lmmr2_overlay.ka0302$r_slot8_lmmr2_bits.ka0302$v_slot8_lmmr2_nbanksr#define ka0302$v_slot8_lmmr2_addr ka0302$r_slot8_lmmr2_overlay.ka0302$r_slot8_lmmr2_bits.ka0302$v_slot8_lmmr2_addrN#define ka0302$l_slot8_lmmr3 ka0302$r_slot8_lmmr3_overlay.ka0302$l,_slot8_lmmr3n#define ka0302$v_slot8_lmmr3_en ka0302$r_slot8_lmmr3_overlay.ka0302$r_slot8_lmmr3_bits.ka0302$v_slot8_lmmr3_enp#define ka0302$v_slot8_lmmr3_int ka0302$r_slot8_lmmr3_overlay.ka0302$r_slot8_lmmr3_bits.ka0302$v_slot8_lmmr3_intn#define ka0302$v_slot8_lmmr3_ia ka0302$r_slot8_lmmr3_overlay.ka0302$r_slot8_lmmr3_bits.ka0302$v_slot8_lmmr3_ian#define ka0302$v_slot8_lmmr3_aw ka0302$r_slot8_lmmr3_overlay.ka0302$r_slot8_lmmr3_bits.ka0302$v_slot8_lmmr3_awv#define ka0302$v_slot8_lmmr3_nbanks ka0302,$r_slot8_lmmr3_overlay.ka0302$r_slot8_lmmr3_bits.ka0302$v_slot8_lmmr3_nbanksr#define ka0302$v_slot8_lmmr3_addr ka0302$r_slot8_lmmr3_overlay.ka0302$r_slot8_lmmr3_bits.ka0302$v_slot8_lmmr3_addrN#define ka0302$l_slot8_lmmr4 ka0302$r_slot8_lmmr4_overlay.ka0302$l_slot8_lmmr4n#define ka0302$v_slot8_lmmr4_en ka0302$r_slot8_lmmr4_overlay.ka0302$r_slot8_lmmr4_bits.ka0302$v_slot8_lmmr4_enp#define ka0302$v_slot8_lmmr4_int ka0302$r_slot8_lmmr4_overlay.ka0302$r_slot8_lmmr4_bits.ka0302$v_slot8_lmmr4_intn#defin,e ka0302$v_slot8_lmmr4_ia ka0302$r_slot8_lmmr4_overlay.ka0302$r_slot8_lmmr4_bits.ka0302$v_slot8_lmmr4_ian#define ka0302$v_slot8_lmmr4_aw ka0302$r_slot8_lmmr4_overlay.ka0302$r_slot8_lmmr4_bits.ka0302$v_slot8_lmmr4_awv#define ka0302$v_slot8_lmmr4_nbanks ka0302$r_slot8_lmmr4_overlay.ka0302$r_slot8_lmmr4_bits.ka0302$v_slot8_lmmr4_nbanksr#define ka0302$v_slot8_lmmr4_addr ka0302$r_slot8_lmmr4_overlay.ka0302$r_slot8_lmmr4_bits.ka0302$v_slot8_lmmr4_addrN#define ka0302$l_slot8_lmmr5 ka0302$r_slot8_lmmr5_ov,erlay.ka0302$l_slot8_lmmr5n#define ka0302$v_slot8_lmmr5_en ka0302$r_slot8_lmmr5_overlay.ka0302$r_slot8_lmmr5_bits.ka0302$v_slot8_lmmr5_enp#define ka0302$v_slot8_lmmr5_int ka0302$r_slot8_lmmr5_overlay.ka0302$r_slot8_lmmr5_bits.ka0302$v_slot8_lmmr5_intn#define ka0302$v_slot8_lmmr5_ia ka0302$r_slot8_lmmr5_overlay.ka0302$r_slot8_lmmr5_bits.ka0302$v_slot8_lmmr5_ian#define ka0302$v_slot8_lmmr5_aw ka0302$r_slot8_lmmr5_overlay.ka0302$r_slot8_lmmr5_bits.ka0302$v_slot8_lmmr5_awv#define ka0302$v_slot8_lmmr5,_nbanks ka0302$r_slot8_lmmr5_overlay.ka0302$r_slot8_lmmr5_bits.ka0302$v_slot8_lmmr5_nbanksr#define ka0302$v_slot8_lmmr5_addr ka0302$r_slot8_lmmr5_overlay.ka0302$r_slot8_lmmr5_bits.ka0302$v_slot8_lmmr5_addrN#define ka0302$l_slot8_lmmr6 ka0302$r_slot8_lmmr6_overlay.ka0302$l_slot8_lmmr6n#define ka0302$v_slot8_lmmr6_en ka0302$r_slot8_lmmr6_overlay.ka0302$r_slot8_lmmr6_bits.ka0302$v_slot8_lmmr6_enp#define ka0302$v_slot8_lmmr6_int ka0302$r_slot8_lmmr6_overlay.ka0302$r_slot8_lmmr6_bits.ka0302$v_slot8_lmm,r6_intn#define ka0302$v_slot8_lmmr6_ia ka0302$r_slot8_lmmr6_overlay.ka0302$r_slot8_lmmr6_bits.ka0302$v_slot8_lmmr6_ian#define ka0302$v_slot8_lmmr6_aw ka0302$r_slot8_lmmr6_overlay.ka0302$r_slot8_lmmr6_bits.ka0302$v_slot8_lmmr6_awv#define ka0302$v_slot8_lmmr6_nbanks ka0302$r_slot8_lmmr6_overlay.ka0302$r_slot8_lmmr6_bits.ka0302$v_slot8_lmmr6_nbanksr#define ka0302$v_slot8_lmmr6_addr ka0302$r_slot8_lmmr6_overlay.ka0302$r_slot8_lmmr6_bits.ka0302$v_slot8_lmmr6_addrN#define ka0302$l_slot8_lmmr7 ka0302$r_,slot8_lmmr7_overlay.ka0302$l_slot8_lmmr7n#define ka0302$v_slot8_lmmr7_en ka0302$r_slot8_lmmr7_overlay.ka0302$r_slot8_lmmr7_bits.ka0302$v_slot8_lmmr7_enp#define ka0302$v_slot8_lmmr7_int ka0302$r_slot8_lmmr7_overlay.ka0302$r_slot8_lmmr7_bits.ka0302$v_slot8_lmmr7_intn#define ka0302$v_slot8_lmmr7_ia ka0302$r_slot8_lmmr7_overlay.ka0302$r_slot8_lmmr7_bits.ka0302$v_slot8_lmmr7_ian#define ka0302$v_slot8_lmmr7_aw ka0302$r_slot8_lmmr7_overlay.ka0302$r_slot8_lmmr7_bits.ka0302$v_slot8_lmmr7_awv#define ka0302,$v_slot8_lmmr7_nbanks ka0302$r_slot8_lmmr7_overlay.ka0302$r_slot8_lmmr7_bits.ka0302$v_slot8_lmmr7_nbanksr#define ka0302$v_slot8_lmmr7_addr ka0302$r_slot8_lmmr7_overlay.ka0302$r_slot8_lmmr7_bits.ka0302$v_slot8_lmmr7_addrQ#define ka0302$l_slot8_lbesr0 ka0302$r_slot8_lbesr0_overlay.ka0302$l_slot8_lbesr0~#define ka0302$v_slot8_lbesr0_syndrome ka0302$r_slot8_lbesr0_overlay.ka0302$r_slot8_lbesr0_bits.ka0302$v_slot8_lbesr0_syndromeQ#define ka0302$l_slot8_lbesr1 ka0302$r_slot8_lbesr1_overlay.ka0302$l_slo,t8_lbesr1~#define ka0302$v_slot8_lbesr1_syndrome ka0302$r_slot8_lbesr1_overlay.ka0302$r_slot8_lbesr1_bits.ka0302$v_slot8_lbesr1_syndromeQ#define ka0302$l_slot8_lbesr2 ka0302$r_slot8_lbesr2_overlay.ka0302$l_slot8_lbesr2~#define ka0302$v_slot8_lbesr2_syndrome ka0302$r_slot8_lbesr2_overlay.ka0302$r_slot8_lbesr2_bits.ka0302$v_slot8_lbesr2_syndromeQ#define ka0302$l_slot8_lbesr3 ka0302$r_slot8_lbesr3_overlay.ka0302$l_slot8_lbesr3~#define ka0302$v_slot8_lbesr3_syndrome ka0302$r_slot8_lbesr3_overlay.k,a0302$r_slot8_lbesr3_bits.ka0302$v_slot8_lbesr3_syndromeQ#define ka0302$l_slot8_lbecr0 ka0302$r_slot8_lbecr0_overlay.ka0302$l_slot8_lbecr0r#define ka0302$l_slot8_lbecr0_ca ka0302$r_slot8_lbecr0_overlay.ka0302$r_slot8_lbecr0_bits.ka0302$l_slot8_lbecr0_caQ#define ka0302$l_slot8_lbecr1 ka0302$r_slot8_lbecr1_overlay.ka0302$l_slot8_lbecr1r#define ka0302$v_slot8_lbecr1_ca ka0302$r_slot8_lbecr1_overlay.ka0302$r_slot8_lbecr1_bits.ka0302$v_slot8_lbecr1_cat#define ka0302$v_slot8_lbecr1_cid ka0302$r_slot8,_lbecr1_overlay.ka0302$r_slot8_lbecr1_bits.ka0302$v_slot8_lbecr1_cidt#define ka0302$v_slot8_lbecr1_rid ka0302$r_slot8_lbecr1_overlay.ka0302$r_slot8_lbecr1_bits.ka0302$v_slot8_lbecr1_ridt#define ka0302$v_slot8_lbecr1_cnf ka0302$r_slot8_lbecr1_overlay.ka0302$r_slot8_lbecr1_bits.ka0302$v_slot8_lbecr1_cnfz#define ka0302$v_slot8_lbecr1_shared ka0302$r_slot8_lbecr1_overlay.ka0302$r_slot8_lbecr1_bits.ka0302$v_slot8_lbecr1_sharedx#define ka0302$v_slot8_lbecr1_dirty ka0302$r_slot8_lbecr1_overlay.ka0302$r_s,lot8_lbecr1_bits.ka0302$v_slot8_lbecr1_dirtyz#define ka0302$v_slot8_lbecr1_dcycle ka0302$r_slot8_lbecr1_overlay.ka0302$r_slot8_lbecr1_bits.ka0302$v_slot8_lbecr1_dcycle?#define ka0302$l_lilid0 ka0302$r_lilid0_overlay.ka0302$l_lilid0`#define ka0302$v_lilid0_ident ka0302$r_lilid0_overlay.ka0302$r_lilid0_bits.ka0302$v_lilid0_ident?#define ka0302$l_lilid1 ka0302$r_lilid1_overlay.ka0302$l_lilid1`#define ka0302$v_lilid1_ident ka0302$r_lilid1_overlay.ka0302$r_lilid1_bits.ka0302$v_lilid1_ident?#define ,ka0302$l_lilid2 ka0302$r_lilid2_overlay.ka0302$l_lilid2`#define ka0302$v_lilid2_ident ka0302$r_lilid2_overlay.ka0302$r_lilid2_bits.ka0302$v_lilid2_ident?#define ka0302$l_lilid3 ka0302$r_lilid3_overlay.ka0302$l_lilid3`#define ka0302$v_lilid3_ident ka0302$r_lilid3_overlay.ka0302$r_lilid3_bits.ka0302$v_lilid3_identE#define ka0302$l_lcpumask ka0302$r_lcpumask_overlay.ka0302$l_lcpumaskf#define ka0302$v_lcpumask_cpu0 ka0302$r_lcpumask_overlay.ka0302$r_lcpumask_bits.ka0302$v_lcpumask_cpu0f#define ka,0302$v_lcpumask_cpu1 ka0302$r_lcpumask_overlay.ka0302$r_lcpumask_bits.ka0302$v_lcpumask_cpu1f#define ka0302$v_lcpumask_cpu2 ka0302$r_lcpumask_overlay.ka0302$r_lcpumask_bits.ka0302$v_lcpumask_cpu2f#define ka0302$v_lcpumask_cpu3 ka0302$r_lcpumask_overlay.ka0302$r_lcpumask_bits.ka0302$v_lcpumask_cpu3<#define ka0302$q_lmbpr ka0302$r_lmbpr_overlay.ka0302$q_lmbpr?#define ka0302$l_ipcnse ka0302$r_ipcnse_overlay.ka0302$l_ipcnsep#define ka0302$v_ipcnse_mbx_hose0_tip ka0302$r_ipcnse_overlay.ka0302$r_ipcns,e_bits.ka0302$v_ipcnse_mbx_hose0_tipp#define ka0302$v_ipcnse_mbx_hose1_tip ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_mbx_hose1_tipp#define ka0302$v_ipcnse_mbx_hose2_tip ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_mbx_hose2_tipp#define ka0302$v_ipcnse_mbx_hose3_tip ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_mbx_hose3_tipn#define ka0302$v_ipcnse_uphose0_oflo ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_uphose0_oflon#define ka0302,$v_ipcnse_uphose1_oflo ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_uphose1_oflon#define ka0302$v_ipcnse_uphose2_oflo ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_uphose2_oflon#define ka0302$v_ipcnse_uphose3_oflo ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_uphose3_oflot#define ka0302$v_ipcnse_uphose0_pkt_err ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_uphose0_pkt_errt#define ka0302$v_ipcnse_uphose1_pkt_err ka0302$r_ipcnse_overlay.ka,0302$r_ipcnse_bits.ka0302$v_ipcnse_uphose1_pkt_errt#define ka0302$v_ipcnse_uphose2_pkt_err ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_uphose2_pkt_errt#define ka0302$v_ipcnse_uphose3_pkt_err ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_uphose3_pkt_errt#define ka0302$v_ipcnse_uphose0_par_err ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_uphose0_par_errt#define ka0302$v_ipcnse_uphose1_par_err ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse,_uphose1_par_errt#define ka0302$v_ipcnse_uphose2_par_err ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_uphose2_par_errt#define ka0302$v_ipcnse_uphose3_par_err ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_uphose3_par_errh#define ka0302$v_ipcnse_up_hic_ie ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_up_hic_iel#define ka0302$v_ipcnse_ipc_int_err ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_ipc_int_errl#define ka0302$v_ipcnse_up_vrtx_err ,ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_up_vrtx_errl#define ka0302$v_ipcnse_dn_vrtx_err ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_dn_vrtx_errp#define ka0302$v_ipcnse_mult_intr_err ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_mult_intr_errh#define ka0302$v_ipcnse_intr_nses ka0302$r_ipcnse_overlay.ka0302$r_ipcnse_bits.ka0302$v_ipcnse_intr_nses<#define ka0302$l_ipcvr ka0302$r_ipcvr_overlay.ka0302$l_ipcvr^#define ka0302$v_ipcvr_vector ka0302$r_i,pcvr_overlay.ka0302$r_ipcvr_bits.ka0302$v_ipcvr_vector?#define ka0302$l_ipcmsr ka0302$r_ipcmsr_overlay.ka0302$l_ipcmsrf#define ka0302$v_ipcmsr_arb_high ka0302$r_ipcmsr_overlay.ka0302$r_ipcmsr_bits.ka0302$v_ipcmsr_arb_highd#define ka0302$v_ipcmsr_arb_ctl ka0302$r_ipcmsr_overlay.ka0302$r_ipcmsr_bits.ka0302$v_ipcmsr_arb_ctl?#define ka0302$l_ipchst ka0302$r_ipchst_overlay.ka0302$l_ipchstf#define ka0302$v_ipchst_h0_error ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h0_errorf#define ,ka0302$v_ipchst_h0_pwrok ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h0_pwrokf#define ka0302$v_ipchst_h0_cblok ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h0_cblokr#define ka0302$v_ipchst_h0_pwrok_trans ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h0_pwrok_transf#define ka0302$v_ipchst_h1_error ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h1_errorf#define ka0302$v_ipchst_h1_pwrok ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v,_ipchst_h1_pwrokf#define ka0302$v_ipchst_h1_cblok ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h1_cblokr#define ka0302$v_ipchst_h1_pwrok_trans ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h1_pwrok_transf#define ka0302$v_ipchst_h2_error ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h2_errorf#define ka0302$v_ipchst_h2_pwrok ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h2_pwrokf#define ka0302$v_ipchst_h2_cblok ka0302$r_ipchst_overlay.ka0,302$r_ipchst_bits.ka0302$v_ipchst_h2_cblokr#define ka0302$v_ipchst_h2_pwrok_trans ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h2_pwrok_transf#define ka0302$v_ipchst_h3_error ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h3_errorf#define ka0302$v_ipchst_h3_pwrok ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h3_pwrokf#define ka0302$v_ipchst_h3_cblok ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h3_cblokr#define ka0302$v_ipchst_h3_pwrok_t,rans ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_h3_pwrok_transh#define ka0302$v_ipchst_hose0_rst ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_hose0_rsth#define ka0302$v_ipchst_hose1_rst ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_hose1_rsth#define ka0302$v_ipchst_hose2_rst ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_hose2_rsth#define ka0302$v_ipchst_hose3_rst ka0302$r_ipchst_overlay.ka0302$r_ipchst_bits.ka0302$v_ipchst_hose3_rst<,#define ka0302$l_ipcdr ka0302$r_ipcdr_overlay.ka0302$l_ipcdrn#define ka0302$v_ipcdr_frc_dn_ill_cmd ka0302$r_ipcdr_overlay.ka0302$r_ipcdr_bits.ka0302$v_ipcdr_frc_dn_ill_cmdn#define ka0302$v_ipcdr_frc_dn_seq_err ka0302$r_ipcdr_overlay.ka0302$r_ipcdr_bits.ka0302$v_ipcdr_frc_dn_seq_errf#define ka0302$v_ipcdr_frc_dn_dpe ka0302$r_ipcdr_overlay.ka0302$r_ipcdr_bits.ka0302$v_ipcdr_frc_dn_dpeh#define ka0302$v_ipcdr_dis_lsb_cmd ka0302$r_ipcdr_overlay.ka0302$r_ipcdr_bits.ka0302$v_ipcdr_dis_lsb_cmdj#define ka,0302$v_ipcdr_hic_lpbck_en ka0302$r_ipcdr_overlay.ka0302$r_ipcdr_bits.ka0302$v_ipcdr_hic_lpbck_enf#define ka0302$v_ipcdr_frc_dat_pe ka0302$r_ipcdr_overlay.ka0302$r_ipcdr_bits.ka0302$v_ipcdr_frc_dat_pef#define ka0302$v_ipcdr_frc_cmd_pe ka0302$r_ipcdr_overlay.ka0302$r_ipcdr_bits.ka0302$v_ipcdr_frc_cmd_peb#define ka0302$v_ipcdr_frc_cnfe ka0302$r_ipcdr_overlay.ka0302$r_ipcdr_bits.ka0302$v_ipcdr_frc_cnfe`#define ka0302$v_ipcdr_frc_cae ka0302$r_ipcdr_overlay.ka0302$r_ipcdr_bits.ka0302$v_ipcdr_frc_caeb#d,efine ka0302$v_ipcdr_diag_ecc ka0302$r_ipcdr_overlay.ka0302$r_ipcdr_bits.ka0302$v_ipcdr_diag_ecch#define ka0302$v_ipcdr_diag_ecc_en ka0302$r_ipcdr_overlay.ka0302$r_ipcdr_bits.ka0302$v_ipcdr_diag_ecc_enB#define ka0302$l_liointr ka0302$r_liointr_overlay.ka0302$l_liointrb#define ka0302$v_liointr_cpu0 ka0302$r_liointr_overlay.ka0302$r_liointr_bits.ka0302$v_liointr_cpu0b#define ka0302$v_liointr_cpu1 ka0302$r_liointr_overlay.ka0302$r_liointr_bits.ka0302$v_liointr_cpu1b#define ka0302$v_liointr_cpu2 ka03,02$r_liointr_overlay.ka0302$r_liointr_bits.ka0302$v_liointr_cpu2b#define ka0302$v_liointr_cpu3 ka0302$r_liointr_overlay.ka0302$r_liointr_bits.ka0302$v_liointr_cpu3B#define ka0302$l_lipintr ka0302$r_lipintr_overlay.ka0302$l_lipintrb#define ka0302$v_lipintr_cpu0 ka0302$r_lipintr_overlay.ka0302$r_lipintr_bits.ka0302$v_lipintr_cpu0b#define ka0302$v_lipintr_cpu1 ka0302$r_lipintr_overlay.ka0302$r_lipintr_bits.ka0302$v_lipintr_cpu1b#define ka0302$v_lipintr_cpu2 ka0302$r_lipintr_overlay.ka0302$r_lipintr_,bits.ka0302$v_lipintr_cpu2b#define ka0302$v_lipintr_cpu3 ka0302$r_lipintr_overlay.ka0302$r_lipintr_bits.ka0302$v_lipintr_cpu3K#define ka0302$l_uart0a_rr0 ka0302$r_uart0a_rr0_overlay.ka0302$l_uart0a_rr0K#define ka0302$l_uart0a_rr8 ka0302$r_uart0a_rr8_overlay.ka0302$l_uart0a_rr8K#define ka0302$l_uart0b_rr0 ka0302$r_uart0b_rr0_overlay.ka0302$l_uart0b_rr0K#define ka0302$l_uart0b_rr8 ka0302$r_uart0b_rr8_overlay.ka0302$l_uart0b_rr8d#define ka0302$l_uart1b_rr0 ka0302$r_uart1b0_overlay.ka0302$r_uart,1b_rr0_overlay.ka0302$l_uart1b_rr0d#define ka0302$l_uart1b_wr0 ka0302$r_uart1b0_overlay.ka0302$r_uart1b_wr0_overlay.ka0302$l_uart1b_wr0K#define ka0302$l_uart1b_rr8 ka0302$r_uart1b_rr8_overlay.ka0302$l_uart1b_rr8K#define ka0302$l_uart1a_rr0 ka0302$r_uart1a_rr0_overlay.ka0302$l_uart1a_rr0K#define ka0302$l_uart1a_rr8 ka0302$r_uart1a_rr8_overlay.ka0302$l_uart1a_rr8K#define ka0302$l_uart2b_rr0 ka0302$r_uart2b_rr0_overlay.ka0302$l_uart2b_rr0K#define ka0302$l_uart2b_rr8 ka0302$r_uart2b_rr8_overlay.,ka0302$l_uart2b_rr8K#define ka0302$l_uart2a_rr0 ka0302$r_uart2a_rr0_overlay.ka0302$l_uart2a_rr0K#define ka0302$l_uart2a_rr8 ka0302$r_uart2a_rr8_overlay.ka0302$l_uart2a_rr8T#define ka0302$l_watch_seconds ka0302$r_watch_seconds_overlay.ka0302$l_watch_secondsT#define ka0302$l_watch_minutes ka0302$r_watch_minutes_overlay.ka0302$l_watch_minutesN#define ka0302$l_watch_hours ka0302$r_watch_hours_overlay.ka0302$l_watch_hoursH#define ka0302$l_watch_dom ka0302$r_watch_dom_overlay.ka0302$l_watch_domN#d,efine ka0302$l_watch_month ka0302$r_watch_month_overlay.ka0302$l_watch_monthK#define ka0302$l_watch_year ka0302$r_watch_year_overlay.ka0302$l_watch_yearK#define ka0302$l_watch_csra ka0302$r_watch_csra_overlay.ka0302$l_watch_csraj#define ka0302$v_watch_csra_rs ka0302$r_watch_csra_overlay.ka0302$r_watch_csra_bits.ka0302$v_watch_csra_rsj#define ka0302$v_watch_csra_dv ka0302$r_watch_csra_overlay.ka0302$r_watch_csra_bits.ka0302$v_watch_csra_dvl#define ka0302$v_watch_csra_uip ka0302$r_watch_csra_over,lay.ka0302$r_watch_csra_bits.ka0302$v_watch_csra_uipK#define ka0302$l_watch_csrb ka0302$r_watch_csrb_overlay.ka0302$l_watch_csrbl#define ka0302$v_watch_csrb_dse ka0302$r_watch_csrb_overlay.ka0302$r_watch_csrb_bits.ka0302$v_watch_csrb_dsep#define ka0302$v_watch_csrb_24_12 ka0302$r_watch_csrb_overlay.ka0302$r_watch_csrb_bits.ka0302$v_watch_csrb_24_12j#define ka0302$v_watch_csrb_dm ka0302$r_watch_csrb_overlay.ka0302$r_watch_csrb_bits.ka0302$v_watch_csrb_dmn#define ka0302$v_watch_csrb_sqwe ka0302$r_,watch_csrb_overlay.ka0302$r_watch_csrb_bits.ka0302$v_watch_csrb_sqwel#define ka0302$v_watch_csrb_uie ka0302$r_watch_csrb_overlay.ka0302$r_watch_csrb_bits.ka0302$v_watch_csrb_uiel#define ka0302$v_watch_csrb_aie ka0302$r_watch_csrb_overlay.ka0302$r_watch_csrb_bits.ka0302$v_watch_csrb_aiel#define ka0302$v_watch_csrb_pie ka0302$r_watch_csrb_overlay.ka0302$r_watch_csrb_bits.ka0302$v_watch_csrb_piel#define ka0302$v_watch_csrb_set ka0302$r_watch_csrb_overlay.ka0302$r_watch_csrb_bits.ka0302$v_watch_csrb_s,etK#define ka0302$l_watch_csrc ka0302$r_watch_csrc_overlay.ka0302$l_watch_csrcj#define ka0302$v_watch_csrc_uf ka0302$r_watch_csrc_overlay.ka0302$r_watch_csrc_bits.ka0302$v_watch_csrc_ufj#define ka0302$v_watch_csrc_af ka0302$r_watch_csrc_overlay.ka0302$r_watch_csrc_bits.ka0302$v_watch_csrc_afj#define ka0302$v_watch_csrc_pf ka0302$r_watch_csrc_overlay.ka0302$r_watch_csrc_bits.ka0302$v_watch_csrc_pfn#define ka0302$v_watch_csrc_irqf ka0302$r_watch_csrc_overlay.ka0302$r_watch_csrc_bits.ka0302$v_watch,_csrc_irqfK#define ka0302$l_watch_csrd ka0302$r_watch_csrd_overlay.ka0302$l_watch_csrdl#define ka0302$v_watch_csrd_vrt ka0302$r_watch_csrd_overlay.ka0302$r_watch_csrd_bits.ka0302$v_watch_csrd_vrtH#define ka0302$l_watch_ram ka0302$r_watch_ram_overlay.ka0302$l_watch_ramK#define ka0302$l_gbus_whami ka0302$r_gbus_whami_overlay.ka0302$l_gbus_whamil#define ka0302$v_gbus_whami_nid ka0302$r_gbus_whami_overlay.ka0302$r_gbus_whami_bits.ka0302$v_gbus_whami_nidl#define ka0302$v_gbus_whami_mfg ka0302$r_gbu,s_whami_overlay.ka0302$r_gbus_whami_bits.ka0302$v_gbus_whami_mfgt#define ka0302$v_gbus_whami_lsb_bad ka0302$r_gbus_whami_overlay.ka0302$r_gbus_whami_bits.ka0302$v_gbus_whami_lsb_badH#define ka0302$l_gbus_leds ka0302$r_gbus_leds_overlay.ka0302$l_gbus_ledsh#define ka0302$v_gbus_leds_stp ka0302$r_gbus_leds_overlay.ka0302$r_gbus_leds_bits.ka0302$v_gbus_leds_stpj#define ka0302$v_gbus_leds_conw ka0302$r_gbus_leds_overlay.ka0302$r_gbus_leds_bits.ka0302$v_gbus_leds_conwh#define ka0302$v_gbus_leds_run ka0,302$r_gbus_leds_overlay.ka0302$r_gbus_leds_bits.ka0302$v_gbus_leds_runj#define ka0302$v_gbus_leds_led3 ka0302$r_gbus_leds_overlay.ka0302$r_gbus_leds_bits.ka0302$v_gbus_leds_led3j#define ka0302$v_gbus_leds_led4 ka0302$r_gbus_leds_overlay.ka0302$r_gbus_leds_bits.ka0302$v_gbus_leds_led4j#define ka0302$v_gbus_leds_led5 ka0302$r_gbus_leds_overlay.ka0302$r_gbus_leds_bits.ka0302$v_gbus_leds_led5j#define ka0302$v_gbus_leds_led6 ka0302$r_gbus_leds_overlay.ka0302$r_gbus_leds_bits.ka0302$v_gbus_leds_led6j#d,efine ka0302$v_gbus_leds_led7 ka0302$r_gbus_leds_overlay.ka0302$r_gbus_leds_bits.ka0302$v_gbus_leds_led7K#define ka0302$l_gbus_pmask ka0302$r_gbus_pmask_overlay.ka0302$l_gbus_pmaskr#define ka0302$v_gbus_pmask_halten ka0302$r_gbus_pmask_overlay.ka0302$r_gbus_pmask_bits.ka0302$v_gbus_pmask_haltent#define ka0302$v_gbus_pmask_selterm ka0302$r_gbus_pmask_overlay.ka0302$r_gbus_pmask_bits.ka0302$v_gbus_pmask_seltermH#define ka0302$l_gbus_intr ka0302$r_gbus_intr_overlay.ka0302$l_gbus_intrr#define ka0302,$v_gbus_intr_uartint0 ka0302$r_gbus_intr_overlay.ka0302$r_gbus_intr_bits.ka0302$v_gbus_intr_uartint0r#define ka0302$v_gbus_intr_uartint1 ka0302$r_gbus_intr_overlay.ka0302$r_gbus_intr_bits.ka0302$v_gbus_intr_uartint1j#define ka0302$v_gbus_intr_lsb0 ka0302$r_gbus_intr_overlay.ka0302$r_gbus_intr_bits.ka0302$v_gbus_intr_lsb0j#define ka0302$v_gbus_intr_lsb2 ka0302$r_gbus_intr_overlay.ka0302$r_gbus_intr_bits.ka0302$v_gbus_intr_lsb2f#define ka0302$v_gbus_intr_ip ka0302$r_gbus_intr_overlay.ka0302$r_gbus_i,ntr_bits.ka0302$v_gbus_intr_ipl#define ka0302$v_gbus_intr_intim ka0302$r_gbus_intr_overlay.ka0302$r_gbus_intr_bits.ka0302$v_gbus_intr_intimH#define ka0302$l_gbus_halt ka0302$r_gbus_halt_overlay.ka0302$l_gbus_haltl#define ka0302$v_gbus_halt_phalt ka0302$r_gbus_halt_overlay.ka0302$r_gbus_halt_bits.ka0302$v_gbus_halt_phaltl#define ka0302$v_gbus_halt_nhalt ka0302$r_gbus_halt_overlay.ka0302$r_gbus_halt_bits.ka0302$v_gbus_halt_nhaltN#define ka0302$l_gbus_lsbrst ka0302$r_gbus_lsbrst_overlay.ka0302$l_gbu ,s_lsbrstH#define ka0302$l_gbus_misc ka0302$r_gbus_misc_overlay.ka0302$l_gbus_miscn#define ka0302$v_gbus_misc_expsel ka0302$r_gbus_misc_overlay.ka0302$r_gbus_misc_bits.ka0302$v_gbus_misc_expselW#define ka0302$l_gbus_rmode_ena ka0302$r_gbus_rmode_ena_overlay.ka0302$l_gbus_rmode_ena"#endif /* #if !defined(__VAXC) */ !#define FLAG$M_FINT_VECTOR 0xFFFF#define FLAG$M_NID_NODESIDE 0x1#define FLAG$M_NID_GA 0x3E%#define FLAG$M_NID_BUS_ADDRESS 0xFFC0##define FLAG$M_STO_VALUE 0x7F000000##def ,ine FLAG$M_STO_FILL1 0x80000000%#define FLAG$M_ERRORHI_CMD_FIELD 0xFF*#define FLAG$M_ERRORHI_STATUS_FIELD 0xFF00(#define FLAG$M_ERRORHI_CAP_LINES 0x70000"#define FLAG$M_ERRORHI_USE 0x80000)#define FLAG$M_ERRORHI_PROTO_ERR 0x400000%#define FLAG$M_ERRORHI_DA_PE 0x800000'#define FLAG$M_ERRORHI_CMD_PE 0x1000000$#define FLAG$M_ERRORHI_NXA 0x4000000+#define FLAG$M_ERRORHI_DISC_PHASE 0x8000000,#define FLAG$M_ERRORHI_DATA_PHASE 0x10000000+#define FLAG$M_ERRORHI_CON_PHASE 0x20000000(#define ,FLAG$M_ERRORHI_MASTER 0x40000000)#define FLAG$M_ERRORHI_ERR_SUM 0x80000000 #define FLAG$M_ERRORLO_NXTID 0x1#define FLAG$M_TTO_VAL 0x1E0000#define FLAG$M_BZRTRY_BRT 0x3FF&#define FLAG$M_BZRTRY_RETDLY 0xFFF8000#define FLAG$M_FCTL_SM 0x1#define FLAG$M_FCTL_SI 0x2#define FLAG$M_FCTL_PRE 0x4#define FLAG$M_FCTL_STF 0x8 #define FLAG$M_FCTL_MERR_EN 0x10'#define FLAG$M_FCTL_SEL_SLV_ERR_EN 0x20##define FLAG$M_FCTL_SLV_ERR_EN 0x40$#define FLAG$M_FCTL_HOSE_ERR_EN 0x80)#define FLAG$M_FCT,L_FATAL_ERR_ST_EN 0x100$#define FLAG$M_FCTL_FBUS_RESET 0x200##define FLAG$M_FCTL_FINTEN_14 0x400##define FLAG$M_FCTL_FINTEN_15 0x800$#define FLAG$M_FCTL_FINTEN_16 0x1000$#define FLAG$M_FCTL_FINTEN_17 0x2000!#define FLAG$M_FCTL_FINTEN 0x4000#define FLAG$M_FCTL_GF0 0x8000#define FLAG$M_FCTL_GF1 0x10000$#define FLAG$M_FCTL_MEMDECEN 0x20000##define FLAG$M_FCTL_CSRRBEN 0x40000##define FLAG$M_FCTL_ENUPRST 0x80000"#define FLAG$M_DIAG_DNP_HDRERR 0x1 #define FLAG$M_DIAG_DNP_DERR 0x2#def,ine FLAG$M_DIAG_DRE 0x4#define FLAG$M_DIAG_FTTO 0x8#define FLAG$M_DIAG_FBI 0x10#define FLAG$M_DIAG_SDL 0x20#define FLAG$M_DIAG_LBD 0x40#define FLAG$M_DIAG_LBEN 0x80#define FLAG$M_DIAG_LBRDY 0x100#define FLAG$M_DIAG_CP 0x8000#define FLAG$M_DIAG_CM 0xFF0000!#define FLAG$M_DIAG_BP 0xFF000000#define FLAG$M_FERR_FINTERR 0x1#define FLAG$M_FERR_DHURR 0x2#define FLAG$M_FERR_DHDPE 0x4#define FLAG$M_FERR_TTO 0x8#define FLAG$M_FERR_STO 0x10#define FLAG$M_FERR_BRTO 0x20#d,efine FLAG$M_FERR_DPCU 0x8000$#define FLAG$M_FERR_FIFOFULL 0x10000&#define FLAG$M_FERR_DNHSE_ICCE 0x20000%#define FLAG$M_FERR_DNHSE_PLE 0x40000(#define FLAG$M_FERR_DNHSE_IDMALE 0x80000(#define FLAG$M_FERR_DNHSE_CMDLE 0x100000'#define FLAG$M_FERR_DNHSE_HCPE 0x200000)#define FLAG$M_FERR_DNHSE_SEQERR 0x400000##define FLAG$M_FERR_UMBCMD 0x800000"#define FLAG$M_FERR_BINT 0x1000000#define FLAG$M_IBR_RCV_SDAT 0x1#define FLAG$M_IBR_XMT_SDAT 0x2#define FLAG$M_IBR_SCLK 0x4'#define FLAG$M,_DEVICE_ID_FLAG_ID 0xFFFF$#define FLAG$M_DEVICE_ID_REV 0xF0000*#define FLAG$M_DEVICE_ID_NODESIDE 0x100000%#define FLAG$M_DEVICE_ID_GA 0x3E00000[#define FLAG$S_FLAGDEF 60 /* Old size name, synonym for FLAG$S_KA0302FLAG */ typedef struct _ka0302flag { __union {! unsigned int flag$l_fint; __struct {- unsigned flag$v_fint_vector : 16;+ unsigned flag$v_fint_fill : 16; } flag$r_fint_bits; } flag$r_fint_over,lay; __union { unsigned int flag$l_nid; __struct {- unsigned flag$v_nid_nodeside : 1;' unsigned flag$v_nid_ga : 5;1 unsigned flag$v_nid_bus_address : 10;* unsigned flag$v_nid_fill : 16; } flag$r_nid_bits; } flag$r_nid_overlay; __union { unsigned int flag$l_sto; __struct {* unsigned flag$v_sto_fill : 24;* unsigned flag$v_sto_value : 7;* unsign ,ed flag$v_sto_fill1 : 1; } flag$r_sto_bits; } flag$r_sto_overlay; __union {$ unsigned int flag$l_errorhi; __struct {2 unsigned flag$v_errorhi_cmd_field : 8;5 unsigned flag$v_errorhi_status_field : 8;2 unsigned flag$v_errorhi_cap_lines : 3;, unsigned flag$v_errorhi_use : 1;- unsigned flag$v_errorhi_fill : 2;2 unsigned flag$v_errorhi_proto_err : 1;. unsigned flag$v_errorh ,i_da_pe : 1;/ unsigned flag$v_errorhi_cmd_pe : 1;. unsigned flag$v_errorhi_fill1 : 1;, unsigned flag$v_errorhi_nxa : 1;3 unsigned flag$v_errorhi_disc_phase : 1;3 unsigned flag$v_errorhi_data_phase : 1;2 unsigned flag$v_errorhi_con_phase : 1;/ unsigned flag$v_errorhi_master : 1;0 unsigned flag$v_errorhi_err_sum : 1;" } flag$r_errorhi_bits;! } flag$r_errorhi_overlay; __union {$, unsigned int flag$l_errorlo; __struct {. unsigned flag$v_errorlo_nxtid : 1;/ unsigned flag$v_errorlo_fill1 : 31;" } flag$r_errorlo_bits;! } flag$r_errorlo_overlay; __union {# unsigned int flag$l_fadrhi; __struct {- unsigned flag$v_fadrhi_fill : 32;! } flag$r_fadrhi_bits; } flag$r_fadrhi_overlay; __union {# unsigned int flag$l_fadrlo; __struct {- , unsigned flag$v_fadrlo_fill : 32;! } flag$r_fadrlo_bits; } flag$r_fadrlo_overlay; __union { unsigned int flag$l_tto; __struct {* unsigned flag$v_tto_fill : 17;( unsigned flag$v_tto_val : 4;+ unsigned flag$v_tto_fill1 : 11; } flag$r_tto_bits; } flag$r_tto_overlay; __union {# unsigned int flag$l_bzrtry; __struct {, unsigned flag$v_bzrtry_brt : 10;, , unsigned flag$v_bzrtry_fill : 5;/ unsigned flag$v_bzrtry_retdly : 13;- unsigned flag$v_bzrtry_fill1 : 4;! } flag$r_bzrtry_bits; } flag$r_bzrtry_overlay; __union {! unsigned int flag$l_fctl; __struct {( unsigned flag$v_fctl_sm : 1;( unsigned flag$v_fctl_si : 1;) unsigned flag$v_fctl_pre : 1;) unsigned flag$v_fctl_stf : 1;- unsigned flag$v_fctl_merr_en : 1;4 , unsigned flag$v_fctl_sel_slv_err_en : 1;0 unsigned flag$v_fctl_slv_err_en : 1;1 unsigned flag$v_fctl_hose_err_en : 1;5 unsigned flag$v_fctl_fatal_err_st_en : 1;0 unsigned flag$v_fctl_fbus_reset : 1;/ unsigned flag$v_fctl_finten_14 : 1;/ unsigned flag$v_fctl_finten_15 : 1;/ unsigned flag$v_fctl_finten_16 : 1;/ unsigned flag$v_fctl_finten_17 : 1;, unsigned flag$v_fctl_finten : 1;) , unsigned flag$v_fctl_gf0 : 1;) unsigned flag$v_fctl_gf1 : 1;. unsigned flag$v_fctl_memdecen : 1;- unsigned flag$v_fctl_csrrben : 1;- unsigned flag$v_fctl_enuprst : 1;+ unsigned flag$v_fctl_fill : 12; } flag$r_fctl_bits; } flag$r_fctl_overlay; __union {! unsigned int flag$l_diag; __struct {0 unsigned flag$v_diag_dnp_hdrerr : 1;. unsigned flag$v_diag_dnp_d ,err : 1;) unsigned flag$v_diag_dre : 1;* unsigned flag$v_diag_ftto : 1;) unsigned flag$v_diag_fbi : 1;) unsigned flag$v_diag_sdl : 1;) unsigned flag$v_diag_lbd : 1;* unsigned flag$v_diag_lben : 1;+ unsigned flag$v_diag_lbrdy : 1;* unsigned flag$v_diag_fill : 6;( unsigned flag$v_diag_cp : 1;( unsigned flag$v_diag_cm : 8;( unsigned flag$v_diag_bp : 8; } fl,ag$r_diag_bits; } flag$r_diag_overlay; __union {! unsigned int flag$l_fgpr; __struct {+ unsigned flag$v_fgpr_fill : 32; } flag$r_fgpr_bits; } flag$r_fgpr_overlay; __union {! unsigned int flag$l_ferr; __struct {- unsigned flag$v_ferr_finterr : 1;+ unsigned flag$v_ferr_dhurr : 1;+ unsigned flag$v_ferr_dhdpe : 1;) unsigned flag$v_ferr_tto : 1;) ,unsigned flag$v_ferr_sto : 1;* unsigned flag$v_ferr_brto : 1;* unsigned flag$v_ferr_fill : 9;* unsigned flag$v_ferr_dpcu : 1;. unsigned flag$v_ferr_fifofull : 1;0 unsigned flag$v_ferr_dnhse_icce : 1;/ unsigned flag$v_ferr_dnhse_ple : 1;2 unsigned flag$v_ferr_dnhse_idmale : 1;1 unsigned flag$v_ferr_dnhse_cmdle : 1;0 unsigned flag$v_ferr_dnhse_hcpe : 1;2 unsigned flag$v_ferr_dnhse_s,eqerr : 1;, unsigned flag$v_ferr_umbcmd : 1;* unsigned flag$v_ferr_bint : 1;+ unsigned flag$v_ferr_fill1 : 6;( unsigned flag$v_fill_0_ : 1; } flag$r_ferr_bits; } flag$r_ferr_overlay; __union { unsigned int flag$l_ibr; __struct {- unsigned flag$v_ibr_rcv_sdat : 1;- unsigned flag$v_ibr_xmt_sdat : 1;) unsigned flag$v_ibr_sclk : 1;* unsigned flag$v_ibr_fill :, 29; } flag$r_ibr_bits; } flag$r_ibr_overlay; __union {& unsigned int flag$l_device_id; __struct {3 unsigned flag$v_device_id_flag_id : 16;. unsigned flag$v_device_id_rev : 4;3 unsigned flag$v_device_id_nodeside : 1;- unsigned flag$v_device_id_ga : 5;/ unsigned flag$v_device_id_fill : 6;$ } flag$r_device_id_bits;# } flag$r_device_id_overlay; } KA0302FLAG; #if ,!defined(__VAXC)3#define flag$l_fint flag$r_fint_overlay.flag$l_fintR#define flag$v_fint_vector flag$r_fint_overlay.flag$r_fint_bits.flag$v_fint_vector0#define flag$l_nid flag$r_nid_overlay.flag$l_nidR#define flag$v_nid_nodeside flag$r_nid_overlay.flag$r_nid_bits.flag$v_nid_nodesideF#define flag$v_nid_ga flag$r_nid_overlay.flag$r_nid_bits.flag$v_nid_gaX#define flag$v_nid_bus_address flag$r_nid_overlay.flag$r_nid_bits.flag$v_nid_bus_address0#define flag$l_sto flag$r_sto_overlay.flag$l_stoL#def,ine flag$v_sto_value flag$r_sto_overlay.flag$r_sto_bits.flag$v_sto_valueL#define flag$v_sto_fill1 flag$r_sto_overlay.flag$r_sto_bits.flag$v_sto_fill1<#define flag$l_errorhi flag$r_errorhi_overlay.flag$l_errorhid#define flag$v_errorhi_cmd_field flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_cmd_fieldj#define flag$v_errorhi_status_field flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_status_fieldd#define flag$v_errorhi_cap_lines flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v,_errorhi_cap_linesX#define flag$v_errorhi_use flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_used#define flag$v_errorhi_proto_err flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_proto_err\#define flag$v_errorhi_da_pe flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_da_pe^#define flag$v_errorhi_cmd_pe flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_cmd_peX#define flag$v_errorhi_nxa flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_nxaf#define flag$v,_errorhi_disc_phase flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_disc_phasef#define flag$v_errorhi_data_phase flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_data_phased#define flag$v_errorhi_con_phase flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_con_phase^#define flag$v_errorhi_master flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_master`#define flag$v_errorhi_err_sum flag$r_errorhi_overlay.flag$r_errorhi_bits.flag$v_errorhi_err_sum<#define flag$l_e,rrorlo flag$r_errorlo_overlay.flag$l_errorlo\#define flag$v_errorlo_nxtid flag$r_errorlo_overlay.flag$r_errorlo_bits.flag$v_errorlo_nxtid9#define flag$l_fadrhi flag$r_fadrhi_overlay.flag$l_fadrhi9#define flag$l_fadrlo flag$r_fadrlo_overlay.flag$l_fadrlo0#define flag$l_tto flag$r_tto_overlay.flag$l_ttoH#define flag$v_tto_val flag$r_tto_overlay.flag$r_tto_bits.flag$v_tto_val9#define flag$l_bzrtry flag$r_bzrtry_overlay.flag$l_bzrtryT#define flag$v_bzrtry_brt flag$r_bzrtry_overlay.flag$r_bzrtry_,bits.flag$v_bzrtry_brtZ#define flag$v_bzrtry_retdly flag$r_bzrtry_overlay.flag$r_bzrtry_bits.flag$v_bzrtry_retdly3#define flag$l_fctl flag$r_fctl_overlay.flag$l_fctlJ#define flag$v_fctl_sm flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_smJ#define flag$v_fctl_si flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_siL#define flag$v_fctl_pre flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_preL#define flag$v_fctl_stf flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_stfT#define flag$v_fctl_merr_en ,flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_merr_enb#define flag$v_fctl_sel_slv_err_en flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_sel_slv_err_enZ#define flag$v_fctl_slv_err_en flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_slv_err_en\#define flag$v_fctl_hose_err_en flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_hose_err_end#define flag$v_fctl_fatal_err_st_en flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_fatal_err_st_enZ#define flag$v_fctl_fbus_reset flag$r_fctl_overlay.flag$r_fc,tl_bits.flag$v_fctl_fbus_resetX#define flag$v_fctl_finten_14 flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_finten_14X#define flag$v_fctl_finten_15 flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_finten_15X#define flag$v_fctl_finten_16 flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_finten_16X#define flag$v_fctl_finten_17 flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_finten_17R#define flag$v_fctl_finten flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_fintenL#define flag$v_fctl_gf0 flag$r,_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_gf0L#define flag$v_fctl_gf1 flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_gf1V#define flag$v_fctl_memdecen flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_memdecenT#define flag$v_fctl_csrrben flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_csrrbenT#define flag$v_fctl_enuprst flag$r_fctl_overlay.flag$r_fctl_bits.flag$v_fctl_enuprst3#define flag$l_diag flag$r_diag_overlay.flag$l_diagZ#define flag$v_diag_dnp_hdrerr flag$r_diag_overlay.flag$r_diag_bit-s.flag$v_diag_dnp_hdrerrV#define flag$v_diag_dnp_derr flag$r_diag_overlay.flag$r_diag_bits.flag$v_diag_dnp_derrL#define flag$v_diag_dre flag$r_diag_overlay.flag$r_diag_bits.flag$v_diag_dreN#define flag$v_diag_ftto flag$r_diag_overlay.flag$r_diag_bits.flag$v_diag_fttoL#define flag$v_diag_fbi flag$r_diag_overlay.flag$r_diag_bits.flag$v_diag_fbiL#define flag$v_diag_sdl flag$r_diag_overlay.flag$r_diag_bits.flag$v_diag_sdlL#define flag$v_diag_lbd flag$r_diag_overlay.flag$r_diag_bits.flag$v_diag_lbdN-#define flag$v_diag_lben flag$r_diag_overlay.flag$r_diag_bits.flag$v_diag_lbenP#define flag$v_diag_lbrdy flag$r_diag_overlay.flag$r_diag_bits.flag$v_diag_lbrdyJ#define flag$v_diag_cp flag$r_diag_overlay.flag$r_diag_bits.flag$v_diag_cpJ#define flag$v_diag_cm flag$r_diag_overlay.flag$r_diag_bits.flag$v_diag_cmJ#define flag$v_diag_bp flag$r_diag_overlay.flag$r_diag_bits.flag$v_diag_bp3#define flag$l_fgpr flag$r_fgpr_overlay.flag$l_fgpr3#define flag$l_ferr flag$r_ferr_overlay.flag$l_ferrT#define -flag$v_ferr_finterr flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_finterrP#define flag$v_ferr_dhurr flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_dhurrP#define flag$v_ferr_dhdpe flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_dhdpeL#define flag$v_ferr_tto flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_ttoL#define flag$v_ferr_sto flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_stoN#define flag$v_ferr_brto flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_brtoN#define flag$v_ferr_dpcu fla-g$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_dpcuV#define flag$v_ferr_fifofull flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_fifofullZ#define flag$v_ferr_dnhse_icce flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_dnhse_icceX#define flag$v_ferr_dnhse_ple flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_dnhse_ple^#define flag$v_ferr_dnhse_idmale flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_dnhse_idmale\#define flag$v_ferr_dnhse_cmdle flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_dnhse_c-mdleZ#define flag$v_ferr_dnhse_hcpe flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_dnhse_hcpe^#define flag$v_ferr_dnhse_seqerr flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_dnhse_seqerrR#define flag$v_ferr_umbcmd flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_umbcmdN#define flag$v_ferr_bint flag$r_ferr_overlay.flag$r_ferr_bits.flag$v_ferr_bint0#define flag$l_ibr flag$r_ibr_overlay.flag$l_ibrR#define flag$v_ibr_rcv_sdat flag$r_ibr_overlay.flag$r_ibr_bits.flag$v_ibr_rcv_sdatR#define flag$v-_ibr_xmt_sdat flag$r_ibr_overlay.flag$r_ibr_bits.flag$v_ibr_xmt_sdatJ#define flag$v_ibr_sclk flag$r_ibr_overlay.flag$r_ibr_bits.flag$v_ibr_sclkB#define flag$l_device_id flag$r_device_id_overlay.flag$l_device_idh#define flag$v_device_id_flag_id flag$r_device_id_overlay.flag$r_device_id_bits.flag$v_device_id_flag_id`#define flag$v_device_id_rev flag$r_device_id_overlay.flag$r_device_id_bits.flag$v_device_id_revj#define flag$v_device_id_nodeside flag$r_device_id_overlay.flag$r_device_id_bits.flag$v_-device_id_nodeside^#define flag$v_device_id_ga flag$r_device_id_overlay.flag$r_device_id_bits.flag$v_device_id_ga"#endif /* #if !defined(__VAXC) */ #define LAMB$M_LDIAG_F39 0x100#define LAMB$M_LDIAG_STE 0x200#define LAMB$M_LDIAG_FXA 0x400#define LAMB$M_LDIAG_ASM 0x1800 #define LAMB$M_LDIAG_DRNK 0x4000 #define LAMB$M_LDIAG_FPE 0xF0000!#define LAMB$M_LDIAG_CRE 0x100000"#define LAMB$M_LDIAG_FRRM 0x600000"#define LAMB$M_LDIAG_LOOP 0x800000##define LAMB$M_LDIAG_LOCK 0x1000000!#defin-e LAMB$M_LDIAG_AS 0x2000000##define LAMB$M_LDIAG_DLLF 0xC000000$#define LAMB$M_LDIAG_NODE 0xF0000000#define LAMB$M_IMSK_IMBER 0x10#define LAMB$M_IMSK_IRBDPE 0x20#define LAMB$M_IMSK_IDFDPE 0x40#define LAMB$M_IMSK_ITTO 0x2000 #define LAMB$M_IMSK_ICNAK 0x8000 #define LAMB$M_IMSK_IRER 0x10000 #define LAMB$M_IMSK_IRSE 0x20000 #define LAMB$M_IMSK_INRR 0x40000 #define LAMB$M_IMSK_ICRD 0x80000##define LAMB$M_IMSK_IWDNAK 0x100000$#define LAMB$M_IMSK_IRIDNAK 0x200000!#define LAMB$M_IMSK_-IWSE 0x400000!#define LAMB$M_IMSK_IXPE 0x800000"#define LAMB$M_IMSK_IIPE 0x1000000"#define LAMB$M_IMSK_IWEI 0x2000000!#define LAMB$M_IMSK_ICC 0x8000000#define LAMB$M_LEVR_VEC 0xFFFF#define LAMB$M_LERR_FE 0x8#define LAMB$M_LERR_MBOF 0x10#define LAMB$M_LERR_RBDPE 0x20#define LAMB$M_LERR_DFDPE 0x40#define LAMB$M_LERR_MBIA 0x1000#define LAMB$M_LERR_MBIC 0x2000#define LAMB$M_LERR_MBPE 0x4000 #define LAMB$M_LERR_IVID 0x78000$#define LAMB$M_LERR_DHDPE 0x10000000%#define LAMB$M_L -ERR_XMIPE0 0x20000000%#define LAMB$M_LERR_XMIPE1 0x40000000%#define LAMB$M_LERR_XMIPE2 0x80000000#define LAMB$M_IPR1_IP1 0xF#define LAMB$M_IPR1_IP2 0xF0#define LAMB$M_IPR1_IP3 0xF00#define LAMB$M_IPR1_IP4 0xF000#define LAMB$M_IPR1_IP5 0xF0000 #define LAMB$M_IPR1_IP6 0xF00000!#define LAMB$M_IPR1_IP7 0xF000000"#define LAMB$M_IPR1_IP8 0xF0000000#define LAMB$M_IPR2_IP9 0xF#define LAMB$M_IPR2_IP10 0xF0#define LAMB$M_IPR2_IP11 0xF00#define LAMB$M_IPR2_IP12 0xF000 #define LA -MB$M_IPR2_IP13 0xF0000!#define LAMB$M_IPR2_IP14 0xF00000##define LAMB$M_IPR2_LEIP 0x80000000#define LAMB$M_IIPR_IPL14ID 0xF #define LAMB$M_IIPR_IPL15ID 0xF0!#define LAMB$M_IIPR_IPL16ID 0xF00"#define LAMB$M_IIPR_IPL17ID 0xF000##define LAMB$M_IIPR_IDENTID 0xF0000T#define LAMB$S_LAMBDEF 96 /* Old size name, synonym for LAMB$S_LAMB */ typedef struct _lamb { char lamb$b_ldiag_base [64]; __union {" unsigned int lamb$l_ldiag; __struct {, - unsigned lamb$v_ldiag_fill1 : 8;* unsigned lamb$v_ldiag_f39 : 1;* unsigned lamb$v_ldiag_ste : 1;* unsigned lamb$v_ldiag_fxa : 1;* unsigned lamb$v_ldiag_asm : 2;, unsigned lamb$v_ldiag_fill2 : 1;+ unsigned lamb$v_ldiag_drnk : 1;, unsigned lamb$v_ldiag_fill3 : 1;* unsigned lamb$v_ldiag_fpe : 4;* unsigned lamb$v_ldiag_cre : 1;+ unsigned lamb$v_ldiag_frrm : 2;+ unsigned - lamb$v_ldiag_loop : 1;+ unsigned lamb$v_ldiag_lock : 1;) unsigned lamb$v_ldiag_as : 1;+ unsigned lamb$v_ldiag_dllf : 2;+ unsigned lamb$v_ldiag_node : 4; } lamb$r_ldiag_bits; } lamb$r_ldiag_overlay; __union {! unsigned int lamb$l_imsk; __struct {+ unsigned lamb$v_imsk_fill1 : 4;+ unsigned lamb$v_imsk_imber : 1;, unsigned lamb$v_imsk_irbdpe : 1;, unsign -ed lamb$v_imsk_idfdpe : 1;+ unsigned lamb$v_imsk_fill2 : 6;* unsigned lamb$v_imsk_itto : 1;+ unsigned lamb$v_imsk_fill3 : 1;+ unsigned lamb$v_imsk_icnak : 1;* unsigned lamb$v_imsk_irer : 1;* unsigned lamb$v_imsk_irse : 1;* unsigned lamb$v_imsk_inrr : 1;* unsigned lamb$v_imsk_icrd : 1;, unsigned lamb$v_imsk_iwdnak : 1;- unsigned lamb$v_imsk_iridnak : 1;* unsigned lamb$-v_imsk_iwse : 1;* unsigned lamb$v_imsk_ixpe : 1;* unsigned lamb$v_imsk_iipe : 1;* unsigned lamb$v_imsk_iwei : 1;+ unsigned lamb$v_imsk_fill4 : 1;) unsigned lamb$v_imsk_icc : 1;+ unsigned lamb$v_imsk_fill5 : 1;( unsigned lamb$v_fill_1_ : 3; } lamb$r_imsk_bits; } lamb$r_imsk_overlay; __union {! unsigned int lamb$l_levr; __struct {* unsigned lamb$v_levr_vec :- 16; } lamb$r_levr_bits; } lamb$r_levr_overlay; __union {! unsigned int lamb$l_lerr; __struct {+ unsigned lamb$v_lerr_fill1 : 3;( unsigned lamb$v_lerr_fe : 1;* unsigned lamb$v_lerr_mbof : 1;+ unsigned lamb$v_lerr_rbdpe : 1;+ unsigned lamb$v_lerr_dfdpe : 1;+ unsigned lamb$v_lerr_fill2 : 5;* unsigned lamb$v_lerr_mbia : 1;* unsigned lamb$v_lerr_mbic : 1;* - unsigned lamb$v_lerr_mbpe : 1;* unsigned lamb$v_lerr_ivid : 4;+ unsigned lamb$v_lerr_fill3 : 9;+ unsigned lamb$v_lerr_dhdpe : 1;, unsigned lamb$v_lerr_xmipe0 : 1;, unsigned lamb$v_lerr_xmipe1 : 1;, unsigned lamb$v_lerr_xmipe2 : 1; } lamb$r_lerr_bits; } lamb$r_lerr_overlay; unsigned int lamb$l_lgpr; __union {! unsigned int lamb$l_ipr1; __struct {) unsign-ed lamb$v_ipr1_ip1 : 4;) unsigned lamb$v_ipr1_ip2 : 4;) unsigned lamb$v_ipr1_ip3 : 4;) unsigned lamb$v_ipr1_ip4 : 4;) unsigned lamb$v_ipr1_ip5 : 4;) unsigned lamb$v_ipr1_ip6 : 4;) unsigned lamb$v_ipr1_ip7 : 4;) unsigned lamb$v_ipr1_ip8 : 4; } lamb$r_ipr1_bits; } lamb$r_ipr1_overlay; __union {! unsigned int lamb$l_ipr2; __struct {) unsigned lamb$v_ipr2-_ip9 : 4;* unsigned lamb$v_ipr2_ip10 : 4;* unsigned lamb$v_ipr2_ip11 : 4;* unsigned lamb$v_ipr2_ip12 : 4;* unsigned lamb$v_ipr2_ip13 : 4;* unsigned lamb$v_ipr2_ip14 : 4;+ unsigned lamb$v_ipr2_fill1 : 7;* unsigned lamb$v_ipr2_leip : 1; } lamb$r_ipr2_bits; } lamb$r_ipr2_overlay; __union {! unsigned int lamb$l_iipr; __struct {- unsigned lamb$v_iipr_ipl14id : 4-;- unsigned lamb$v_iipr_ipl15id : 4;- unsigned lamb$v_iipr_ipl16id : 4;- unsigned lamb$v_iipr_ipl17id : 4;- unsigned lamb$v_iipr_identid : 4;( unsigned lamb$v_fill_2_ : 4; } lamb$r_iipr_bits; } lamb$r_iipr_overlay; } LAMB; #if !defined(__VAXC)6#define lamb$l_ldiag lamb$r_ldiag_overlay.lamb$l_ldiagP#define lamb$v_ldiag_f39 lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_f39P#define lamb$v_ldiag_ste- lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_steP#define lamb$v_ldiag_fxa lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_fxaP#define lamb$v_ldiag_asm lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_asmR#define lamb$v_ldiag_drnk lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_drnkP#define lamb$v_ldiag_fpe lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_fpeP#define lamb$v_ldiag_cre lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_creR#define lamb$v_ldiag_frrm lamb$r_ldi-ag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_frrmR#define lamb$v_ldiag_loop lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_loopR#define lamb$v_ldiag_lock lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_lockN#define lamb$v_ldiag_as lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_asR#define lamb$v_ldiag_dllf lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_dllfR#define lamb$v_ldiag_node lamb$r_ldiag_overlay.lamb$r_ldiag_bits.lamb$v_ldiag_node3#define lamb$l_imsk lamb$r_imsk_overlay.la-mb$l_imskP#define lamb$v_imsk_imber lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_imberR#define lamb$v_imsk_irbdpe lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_irbdpeR#define lamb$v_imsk_idfdpe lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_idfdpeN#define lamb$v_imsk_itto lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_ittoP#define lamb$v_imsk_icnak lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_icnakN#define lamb$v_imsk_irer lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_irerN#d-efine lamb$v_imsk_irse lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_irseN#define lamb$v_imsk_inrr lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_inrrN#define lamb$v_imsk_icrd lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_icrdR#define lamb$v_imsk_iwdnak lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_iwdnakT#define lamb$v_imsk_iridnak lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_iridnakN#define lamb$v_imsk_iwse lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_iwseN#define lamb$v_ims-k_ixpe lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_ixpeN#define lamb$v_imsk_iipe lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_iipeN#define lamb$v_imsk_iwei lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_iweiL#define lamb$v_imsk_icc lamb$r_imsk_overlay.lamb$r_imsk_bits.lamb$v_imsk_icc3#define lamb$l_levr lamb$r_levr_overlay.lamb$l_levrL#define lamb$v_levr_vec lamb$r_levr_overlay.lamb$r_levr_bits.lamb$v_levr_vec3#define lamb$l_lerr lamb$r_lerr_overlay.lamb$l_lerrJ#define lamb$v_lerr_-fe lamb$r_lerr_overlay.lamb$r_lerr_bits.lamb$v_lerr_feN#define lamb$v_lerr_mbof lamb$r_lerr_overlay.lamb$r_lerr_bits.lamb$v_lerr_mbofP#define lamb$v_lerr_rbdpe lamb$r_lerr_overlay.lamb$r_lerr_bits.lamb$v_lerr_rbdpeP#define lamb$v_lerr_dfdpe lamb$r_lerr_overlay.lamb$r_lerr_bits.lamb$v_lerr_dfdpeN#define lamb$v_lerr_mbia lamb$r_lerr_overlay.lamb$r_lerr_bits.lamb$v_lerr_mbiaN#define lamb$v_lerr_mbic lamb$r_lerr_overlay.lamb$r_lerr_bits.lamb$v_lerr_mbicN#define lamb$v_lerr_mbpe lamb$r_lerr_overlay.l-amb$r_lerr_bits.lamb$v_lerr_mbpeN#define lamb$v_lerr_ivid lamb$r_lerr_overlay.lamb$r_lerr_bits.lamb$v_lerr_ividP#define lamb$v_lerr_dhdpe lamb$r_lerr_overlay.lamb$r_lerr_bits.lamb$v_lerr_dhdpeR#define lamb$v_lerr_xmipe0 lamb$r_lerr_overlay.lamb$r_lerr_bits.lamb$v_lerr_xmipe0R#define lamb$v_lerr_xmipe1 lamb$r_lerr_overlay.lamb$r_lerr_bits.lamb$v_lerr_xmipe1R#define lamb$v_lerr_xmipe2 lamb$r_lerr_overlay.lamb$r_lerr_bits.lamb$v_lerr_xmipe23#define lamb$l_ipr1 lamb$r_ipr1_overlay.lamb$l_ipr1L#def-ine lamb$v_ipr1_ip1 lamb$r_ipr1_overlay.lamb$r_ipr1_bits.lamb$v_ipr1_ip1L#define lamb$v_ipr1_ip2 lamb$r_ipr1_overlay.lamb$r_ipr1_bits.lamb$v_ipr1_ip2L#define lamb$v_ipr1_ip3 lamb$r_ipr1_overlay.lamb$r_ipr1_bits.lamb$v_ipr1_ip3L#define lamb$v_ipr1_ip4 lamb$r_ipr1_overlay.lamb$r_ipr1_bits.lamb$v_ipr1_ip4L#define lamb$v_ipr1_ip5 lamb$r_ipr1_overlay.lamb$r_ipr1_bits.lamb$v_ipr1_ip5L#define lamb$v_ipr1_ip6 lamb$r_ipr1_overlay.lamb$r_ipr1_bits.lamb$v_ipr1_ip6L#define lamb$v_ipr1_ip7 lamb$r_ipr1_overla-y.lamb$r_ipr1_bits.lamb$v_ipr1_ip7L#define lamb$v_ipr1_ip8 lamb$r_ipr1_overlay.lamb$r_ipr1_bits.lamb$v_ipr1_ip83#define lamb$l_ipr2 lamb$r_ipr2_overlay.lamb$l_ipr2L#define lamb$v_ipr2_ip9 lamb$r_ipr2_overlay.lamb$r_ipr2_bits.lamb$v_ipr2_ip9N#define lamb$v_ipr2_ip10 lamb$r_ipr2_overlay.lamb$r_ipr2_bits.lamb$v_ipr2_ip10N#define lamb$v_ipr2_ip11 lamb$r_ipr2_overlay.lamb$r_ipr2_bits.lamb$v_ipr2_ip11N#define lamb$v_ipr2_ip12 lamb$r_ipr2_overlay.lamb$r_ipr2_bits.lamb$v_ipr2_ip12N#define lamb$v_ipr2_-ip13 lamb$r_ipr2_overlay.lamb$r_ipr2_bits.lamb$v_ipr2_ip13N#define lamb$v_ipr2_ip14 lamb$r_ipr2_overlay.lamb$r_ipr2_bits.lamb$v_ipr2_ip14N#define lamb$v_ipr2_leip lamb$r_ipr2_overlay.lamb$r_ipr2_bits.lamb$v_ipr2_leip3#define lamb$l_iipr lamb$r_iipr_overlay.lamb$l_iiprT#define lamb$v_iipr_ipl14id lamb$r_iipr_overlay.lamb$r_iipr_bits.lamb$v_iipr_ipl14idT#define lamb$v_iipr_ipl15id lamb$r_iipr_overlay.lamb$r_iipr_bits.lamb$v_iipr_ipl15idT#define lamb$v_iipr_ipl16id lamb$r_iipr_overlay.lamb$r_iipr_ -bits.lamb$v_iipr_ipl16idT#define lamb$v_iipr_ipl17id lamb$r_iipr_overlay.lamb$r_iipr_bits.lamb$v_iipr_ipl17idT#define lamb$v_iipr_identid lamb$r_iipr_overlay.lamb$r_iipr_bits.lamb$v_iipr_identid"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif -#pragma __standard #endif /* __KA0302DEF_LOADED */ wwPQ`[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written  -permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Soft!-ware, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */I/* Source: 15-MAR-1993 09:30:33 $ "-1$DGA8345:[LIB_H.SRC]KA0402DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KA0402DEF ***/#ifndef __KA0402DEF_LOADED#define __KA0402DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __requir#-ed_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union$-#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif $#define KA0402$M_IOSLOT_SLOT0_SG 0x1$#define KA0402$M_IOSLOT_SLOT0_BM 0x2$#define KA0402$M_IOSLOT_SLOT0_PE 0x4$#define KA0402$M_IOSLOT_SLOT1_SG 0x8%#define KA0402$M_IOSLOT_SLOT1_BM 0x10%#define KA0402$M_IOSLOT_SLOT1_PE 0x20%#define KA0402$M_IOSLOT_SLOT2_SG 0x40%#define KA0402$M_IOSLOT_SLOT2_BM 0x80&#define KA0402$M_IOSLOT_SLOT2_PE 0x100&#define KA0402$M_IOSLOT_SLOT3_SG 0x200&#defin %-e KA0402$M_IOSLOT_SLOT3_BM 0x400&#define KA0402$M_IOSLOT_SLOT3_PE 0x800'#define KA0402$M_IOSLOT_SLOT4_SG 0x1000'#define KA0402$M_IOSLOT_SLOT4_BM 0x2000'#define KA0402$M_IOSLOT_SLOT4_PE 0x4000'#define KA0402$M_IOSLOT_SLOT5_SG 0x8000(#define KA0402$M_IOSLOT_SLOT5_BM 0x10000(#define KA0402$M_IOSLOT_SLOT5_PE 0x20000(#define KA0402$M_IOSLOT_SLOT6_SG 0x40000(#define KA0402$M_IOSLOT_SLOT6_BM 0x80000)#define KA0402$M_IOSLOT_SLOT6_PE 0x100000(#define KA0402$M_IOSLOT_CORE_SG 0x200000(#define KA &-0402$M_IOSLOT_CORE_BM 0x400000(#define KA0402$M_IOSLOT_CORE_PE 0x800000,#define KA0402$M_IOSLOT_CXTURBO_SG 0x1000000,#define KA0402$M_IOSLOT_CXTURBO_BM 0x2000000,#define KA0402$M_IOSLOT_CXTURBO_PE 0x4000000*#define KA0402$M_IOSLOT_RM_BYTE0 0x8000000+#define KA0402$M_IOSLOT_RM_BYTE1 0x10000000+#define KA0402$M_IOSLOT_RM_BYTE2 0x20000000+#define KA0402$M_IOSLOT_RM_BYTE3 0x40000000+#define KA0402$M_IOSLOT_RM_VALID 0x80000000$#define KA0402$M_TCCONFIG_MAGIC 0x1F)#define KA0402$M_TCCONFIG_PA'-GE_SIZE 0x100##define KA0402$M_TCEREG_SLOT_ID 0xF#define KA0402$M_TCEREG_SG 0x10#define KA0402$M_TCEREG_BM 0x20#define KA0402$M_TCEREG_PE 0x40!#define KA0402$M_TCEREG_LOCK 0x80%#define KA0402$M_TCEREG_OFFSET 0x1F00)#define KA0402$M_TCEREG_SYNDROME 0x7F0000*#define KA0402$M_TCEREG_WM_BYTE0 0x1000000*#define KA0402$M_TCEREG_WM_BYTE1 0x2000000*#define KA0402$M_TCEREG_WM_BYTE2 0x4000000*#define KA0402$M_TCEREG_WM_BYTE3 0x8000000$#define KA0402$M_TCEREG_W 0x40000000$#define KA0402$M(-_TCEREG_D 0x80000000 #define KA0402$M_IR_TC_INT 0x1FF#define KA0402$M_IR_SEO 0x80000 #define KA0402$M_IR_DBF 0x100000 #define KA0402$M_IR_X2K 0x200000 #define KA0402$M_IR_TCR 0x400000 #define KA0402$M_IR_TPE 0x800000!#define KA0402$M_IR_TER 0x1000000!#define KA0402$M_IR_SBE 0x2000000!#define KA0402$M_IR_DBE 0x4000000 #define KA0402$M_IR_TO 0x8000000!#define KA0402$M_IR_TL 0x10000000!#define KA0402$M_IR_IA 0x20000000!#define KA0402$M_IR_NV 0x40000000!#define KA0402$M_IR_PE 0x80000)-000 #define KA0402$M_IC_TC_INT 0x1FF#define KA0402$M_IC_SEO 0x80000 #define KA0402$M_IC_DBF 0x100000 #define KA0402$M_IC_X2K 0x200000 #define KA0402$M_IC_TCR 0x400000 #define KA0402$M_IC_TPE 0x800000!#define KA0402$M_IC_TER 0x1000000!#define KA0402$M_IC_SBE 0x2000000!#define KA0402$M_IC_DBE 0x4000000 #define KA0402$M_IC_TO 0x8000000!#define KA0402$M_IC_TL 0x10000000!#define KA0402$M_IC_IA 0x20000000!#define KA0402$M_IC_NV 0x40000000!#define KA0402$M_IC_PE 0x80000000&#define KA *-0402$M_LDP_DMA_PA_LO 0xFFFE0)#define KA0402$M_LDP_DMA_PA_HI 0xFFF00000+#define KA0402$M_SCOMM_TR_DMA_PA 0xFFFFFFE0+#define KA0402$M_SCOMM_RC_DMA_PA 0xFFFFFFE0-#define KA0402$M_PRINTER_TR_DMA_PA 0xFFFFFFE0-#define KA0402$M_PRINTER_RC_DMA_PA 0xFFFFFFE0*#define KA0402$M_ISDN_TR_DMA_PA 0xFFFFFFE0.#define KA0402$M_ISDN_TR_BUF_DMA_PA 0xFFFFFFE0*#define KA0402$M_ISDN_RC_DMA_PA 0xFFFFFFE0.#define KA0402$M_ISDN_RC_BUF_DMA_PA 0xFFFFFFE0#define KA0402$M_SSR_LEDS 0xFF&#define KA0402$M_SSR_LANCE_R +-ESET 0x100$#define KA0402$M_SSR_RTC_RESET 0x400$#define KA0402$M_SSR_SSC_RESET 0x800&#define KA0402$M_SSR_ISDN_RESET 0x1000'#define KA0402$M_SSR_10BASET_SEL 0x2000'#define KA0402$M_SSR_NI_LOOPBACK 0x4000!#define KA0402$M_SSR_TXDIS 0x8000)#define KA0402$M_SSR_LANCE_DMA_EN 0x10000+#define KA0402$M_SSR_ISDN_RC_DMA_EN 0x80000,#define KA0402$M_SSR_ISDN_TR_DMA_EN 0x1000001#define KA0402$M_SSR_PRINTER_RC_DMA_EN 0x100000001#define KA0402$M_SSR_PRINTER_TR_DMA_EN 0x20000000.#define KA0402$M_S ,-SR_COMM_RC_DMA_EN 0x40000000.#define KA0402$M_SSR_COMM_TR_DMA_EN 0x80000000#define KA0402$M_SIR_HALT0 0x1#define KA0402$M_SIR_HALT1 0x2$#define KA0402$M_SIR_ALT_CONSOLE 0x8!#define KA0402$M_SIR_SCC0_SI 0x40!#define KA0402$M_SIR_SCC1_SI 0x80"#define KA0402$M_SIR_NI_INTR 0x100%#define KA0402$M_SIR_ISDN_INTR 0x2000)#define KA0402$M_SIR_LANCE_DMA_RE 0x10000*#define KA0402$M_SIR_ISDN_DMA_MRE 0x100000.#define KA0402$M_SIR_ISDN_DMA_RC_INTR 0x200000.#define KA0402$M_SIR_ISDN_DMA_TR_INTR 0x40 --0000,#define KA0402$M_SIR_PP_RC_DMA_OVR 0x1000000,#define KA0402$M_SIR_PP_RC_HP_INTR 0x2000000,#define KA0402$M_SIR_PP_TR_DMA_MRE 0x4000000,#define KA0402$M_SIR_PP_TR_PE_INTR 0x8000000/#define KA0402$M_SIR_COMM_RC_DMA_OVR 0x10000000/#define KA0402$M_SIR_COMM_RC_HP_INTR 0x20000000/#define KA0402$M_SIR_COMM_TR_DMA_MRE 0x40000000/#define KA0402$M_SIR_COMM_TR_PE_INTR 0x80000000#define KA0402$M_SIMR_HALT0 0x1#define KA0402$M_SIMR_HALT1 0x2%#define KA0402$M_SIMR_ALT_CONSOLE 0x8"#define .-KA0402$M_SIMR_SCC0_SI 0x40"#define KA0402$M_SIMR_SCC1_SI 0x80##define KA0402$M_SIMR_NI_INTR 0x100&#define KA0402$M_SIMR_ISDN_INTR 0x2000*#define KA0402$M_SIMR_LANCE_DMA_RE 0x10000+#define KA0402$M_SIMR_ISDN_DMA_MRE 0x100000/#define KA0402$M_SIMR_ISDN_DMA_RC_INTR 0x200000/#define KA0402$M_SIMR_ISDN_DMA_TR_INTR 0x400000-#define KA0402$M_SIMR_PP_RC_DMA_OVR 0x1000000-#define KA0402$M_SIMR_PP_RC_HP_INTR 0x2000000-#define KA0402$M_SIMR_PP_TR_DMA_MRE 0x4000000-#define KA0402$M_SIMR_PP_TR_PE /-_INTR 0x80000000#define KA0402$M_SIMR_COMM_RC_DMA_OVR 0x100000000#define KA0402$M_SIMR_COMM_RC_HP_INTR 0x200000000#define KA0402$M_SIMR_COMM_TR_DMA_MRE 0x400000000#define KA0402$M_SIMR_COMM_TR_PE_INTR 0x80000000'#define KA0402$M_SADR_TC_ADDR 0x1FFFFE0+#define KA0402$M_ISDN_DATA_TR_DATA 0xFFFFFF+#define KA0402$M_ISDN_DATA_RC_DATA 0xFFFFFF"#define KA0402$M_LANCE_SLOT_CS 0xF)#define KA0402$M_LANCE_SLOT_HW_ADDR 0x3F0!#define KA0402$M_SCC0_SLOT_CS 0xF(#define KA0402$M_SCC0_SLOT_HW_ADDR 0x3 0-F0!#define KA0402$M_SCC1_SLOT_CS 0xF(#define KA0402$M_SCC1_SLOT_HW_ADDR 0x3F0O#define KA0402$S_KA0402DEF 434176 /* Old KA0402 size for compatibility */ typedef struct _ka0402 { __union {N void *ka0402$l_ioslot; /* Slot mode register */ __struct {2 unsigned ka0402$v_ioslot_slot0_sg : 1;2 unsigned ka0402$v_ioslot_slot0_bm : 1;2 unsigned ka0402$v_ioslot_slot0_pe : 1;2 unsigned ka0402$v_ioslot_s 1-lot1_sg : 1;2 unsigned ka0402$v_ioslot_slot1_bm : 1;2 unsigned ka0402$v_ioslot_slot1_pe : 1;2 unsigned ka0402$v_ioslot_slot2_sg : 1;2 unsigned ka0402$v_ioslot_slot2_bm : 1;2 unsigned ka0402$v_ioslot_slot2_pe : 1;2 unsigned ka0402$v_ioslot_slot3_sg : 1;2 unsigned ka0402$v_ioslot_slot3_bm : 1;2 unsigned ka0402$v_ioslot_slot3_pe : 1;2 unsigned ka0402$v_ioslot_slot4_sg : 1;2 unsigned ka0 2-402$v_ioslot_slot4_bm : 1;2 unsigned ka0402$v_ioslot_slot4_pe : 1;2 unsigned ka0402$v_ioslot_slot5_sg : 1;2 unsigned ka0402$v_ioslot_slot5_bm : 1;2 unsigned ka0402$v_ioslot_slot5_pe : 1;2 unsigned ka0402$v_ioslot_slot6_sg : 1;2 unsigned ka0402$v_ioslot_slot6_bm : 1;2 unsigned ka0402$v_ioslot_slot6_pe : 1;1 unsigned ka0402$v_ioslot_core_sg : 1;1 unsigned ka0402$v_ioslot_core_bm : 1;1 3- unsigned ka0402$v_ioslot_core_pe : 1;4 unsigned ka0402$v_ioslot_cxturbo_sg : 1;4 unsigned ka0402$v_ioslot_cxturbo_bm : 1;4 unsigned ka0402$v_ioslot_cxturbo_pe : 1;2 unsigned ka0402$v_ioslot_rm_byte0 : 1;2 unsigned ka0402$v_ioslot_rm_byte1 : 1;2 unsigned ka0402$v_ioslot_rm_byte2 : 1;2 unsigned ka0402$v_ioslot_rm_byte3 : 1;2 unsigned ka0402$v_ioslot_rm_valid : 1;# } ka0402$r_ioslot_bits;" 4- } ka0402$r_ioslot_overlay;( unsigned char ka0402$b_fill390 [12]; __union {N void *ka0402$l_tcconfig; /* TC Configuration register */ __struct {1 unsigned ka0402$v_tcconfig_magic : 5;1 unsigned ka0402$v_tcconfig_fill1 : 3;5 unsigned ka0402$v_tcconfig_page_size : 1;1 unsigned ka0402$v_tcconfig_fill : 23;% } ka0402$r_tcconfig_bits;$ } ka0402$r_tcconfig_overlay;( unsigned char ka0402 5-$b_fill400 [12];N void *ka0402$l_fadr; /* Failing Address register */( unsigned char ka0402$b_fill410 [12]; __union {N void *ka0402$l_tcereg; /* Error register */ __struct {1 unsigned ka0402$v_tcereg_slot_id : 4;, unsigned ka0402$v_tcereg_sg : 1;, unsigned ka0402$v_tcereg_bm : 1;, unsigned ka0402$v_tcereg_pe : 1;. unsigned ka0402$v_tcereg_lock : 1;0 6- unsigned ka0402$v_tcereg_offset : 5;/ unsigned ka0402$v_tcereg_fill2 : 3;2 unsigned ka0402$v_tcereg_syndrome : 7;/ unsigned ka0402$v_tcereg_fill3 : 1;2 unsigned ka0402$v_tcereg_wm_byte0 : 1;2 unsigned ka0402$v_tcereg_wm_byte1 : 1;2 unsigned ka0402$v_tcereg_wm_byte2 : 1;2 unsigned ka0402$v_tcereg_wm_byte3 : 1;/ unsigned ka0402$v_tcereg_fill4 : 2;+ unsigned ka0402$v_tcereg_w : 1;+ 7- unsigned ka0402$v_tcereg_d : 1;# } ka0402$r_tcereg_bits;" } ka0402$r_tcereg_overlay;* unsigned char ka0402$b_fill420 [8140];N void *ka0402$l_mcr0; /* Memory configuration 0 */* unsigned char ka0402$b_fill430 [8188];N void *ka0402$l_mcr1; /* Memory configuration 1 */* unsigned char ka0402$b_fill440 [8188];N void *ka0402$l_mcr2; /* Memory configuration 2 */* unsigned char ka0402 8-$b_fill450 [8188];N void *ka0402$l_mcr3; /* Memory configuration 3 */* unsigned char ka0402$b_fill460 [8188];N void *ka0402$l_mcr4; /* Memory configuration 4 */* unsigned char ka0402$b_fill470 [8188];N void *ka0402$l_mcr5; /* Memory configuration 5 */* unsigned char ka0402$b_fill480 [8188];N void *ka0402$l_mcr6; /* Memory configuration 6 */* unsigned char ka0402$b_fill490 9- [8188];N void *ka0402$l_mcr7; /* Memory configuration 7 */* unsigned char ka0402$b_fill500 [8188]; __union {N void *ka0402$l_ir; /* Interrupt register */ __struct {, unsigned ka0402$v_ir_tc_int : 9;, unsigned ka0402$v_ir_fill1 : 10;) unsigned ka0402$v_ir_seo : 1;) unsigned ka0402$v_ir_dbf : 1;) unsigned ka0402$v_ir_x2k : 1;) unsigned ka0402$v_ :-ir_tcr : 1;) unsigned ka0402$v_ir_tpe : 1;) unsigned ka0402$v_ir_ter : 1;) unsigned ka0402$v_ir_sbe : 1;) unsigned ka0402$v_ir_dbe : 1;( unsigned ka0402$v_ir_to : 1;( unsigned ka0402$v_ir_tl : 1;( unsigned ka0402$v_ir_ia : 1;( unsigned ka0402$v_ir_nv : 1;( unsigned ka0402$v_ir_pe : 1; } ka0402$r_ir_bits; } ka0402$r_ir_overlay;* unsigned char ka0402$b_fill510 [8188 ;-]; __union {N void *ka0402$l_ic; /* Interrupt Cause register */ __struct {, unsigned ka0402$v_ic_tc_int : 9;, unsigned ka0402$v_ic_fill1 : 10;) unsigned ka0402$v_ic_seo : 1;) unsigned ka0402$v_ic_dbf : 1;) unsigned ka0402$v_ic_x2k : 1;) unsigned ka0402$v_ic_tcr : 1;) unsigned ka0402$v_ic_tpe : 1;) unsigned ka0402$v_ic_ter : 1;) unsigned ka0402$ <-v_ic_sbe : 1;) unsigned ka0402$v_ic_dbe : 1;( unsigned ka0402$v_ic_to : 1;( unsigned ka0402$v_ic_tl : 1;( unsigned ka0402$v_ic_ia : 1;( unsigned ka0402$v_ic_nv : 1;( unsigned ka0402$v_ic_pe : 1; } ka0402$r_ic_bits; } ka0402$r_ic_overlay;* unsigned char ka0402$b_fill520 [8188];N void *ka0402$l_sg_map; /* Scatter/gather map (32 pages) */, unsigned char ka0402$b_fill530 [262140];N =- void *ka0402$l_tcreset; /* TC reset register */* unsigned char ka0402$b_fill540 [8188];N void *ka0402$l_ioctl_csr; /* Core I/O base CSR address */( unsigned char ka0402$b_fill560 [60]; __union {N void *ka0402$l_ldp; /* Ethernet Lance DMA pointer */ __struct {, unsigned ka0402$v_ldp_fill1 : 5;1 unsigned ka0402$v_ldp_dma_pa_lo : 15;1 unsigned ka0402$v_ldp_dma_pa_hi >-: 12; } ka0402$r_ldp_bits; } ka0402$r_ldp_overlay;( unsigned char ka0402$b_fill570 [28]; __union {U void *ka0402$l_scomm_tr; /* Serial comm transmit port 1 DMA pointer */ __struct {1 unsigned ka0402$v_scomm_tr_fill1 : 5;3 unsigned ka0402$v_scomm_tr_dma_pa : 27;% } ka0402$r_scomm_tr_bits;$ } ka0402$r_scomm_tr_overlay;( unsigned char ka0402$b_fill580 [28]; __union {T void *ka0402 ?-$l_scomm_rc; /* Serial comm receive port 1 DMA pointer */ __struct {1 unsigned ka0402$v_scomm_rc_fill1 : 5;3 unsigned ka0402$v_scomm_rc_dma_pa : 27;% } ka0402$r_scomm_rc_bits;$ } ka0402$r_scomm_rc_overlay;( unsigned char ka0402$b_fill590 [28]; __union {O void *ka0402$l_printer_tr; /* Printer transmit port DMA pointer */ __struct {3 unsigned ka0402$v_printer_tr_fill1 : 5;5 unsign @-ed ka0402$v_printer_tr_dma_pa : 27;' } ka0402$r_printer_tr_bits;& } ka0402$r_printer_tr_overlay;( unsigned char ka0402$b_fill600 [28]; __union {N void *ka0402$l_printer_rc; /* Printer receive port DMA pointer */ __struct {3 unsigned ka0402$v_printer_rc_fill1 : 5;5 unsigned ka0402$v_printer_rc_dma_pa : 27;' } ka0402$r_printer_rc_bits;& } ka0402$r_printer_rc_overlay;( unsigned char ka0402$b_fill610 A- [60]; __union {N void *ka0402$l_isdn_tr; /* ISDN transmit DMA pointer */ __struct {0 unsigned ka0402$v_isdn_tr_fill1 : 5;2 unsigned ka0402$v_isdn_tr_dma_pa : 27;$ } ka0402$r_isdn_tr_bits;# } ka0402$r_isdn_tr_overlay;( unsigned char ka0402$b_fill620 [28]; __union {N void *ka0402$l_isdn_tr_buf; /* ISDN transmit DMA buffer pointer */ __struct {4 unsigned ka0402$v_isdn_tr_buf_ B-fill1 : 5;6 unsigned ka0402$v_isdn_tr_buf_dma_pa : 27;( } ka0402$r_isdn_tr_buf_bits;' } ka0402$r_isdn_tr_buf_overlay;( unsigned char ka0402$b_fill630 [28]; __union {N void *ka0402$l_isdn_rc; /* ISDN receive DMA pointer */ __struct {0 unsigned ka0402$v_isdn_rc_fill1 : 5;2 unsigned ka0402$v_isdn_rc_dma_pa : 27;$ } ka0402$r_isdn_rc_bits;# } ka0402$r_isdn_rc_overlay;( unsigned cha C-r ka0402$b_fill640 [28]; __union {N void *ka0402$l_isdn_rc_buf; /* ISDN receive DMA buffer pointer */ __struct {4 unsigned ka0402$v_isdn_rc_buf_fill1 : 5;6 unsigned ka0402$v_isdn_rc_buf_dma_pa : 27;( } ka0402$r_isdn_rc_buf_bits;' } ka0402$r_isdn_rc_buf_overlay;( unsigned char ka0402$b_fill650 [28];N void *ka0402$l_data0; /* System Data Buffer 0 */( unsigned char ka0402$b_fill660 [28];N D-void *ka0402$l_data1; /* System Data Buffer 1 */( unsigned char ka0402$b_fill670 [28];N void *ka0402$l_data2; /* System Data Buffer 2 */( unsigned char ka0402$b_fill680 [28];N void *ka0402$l_data3; /* System Data Buffer 3 */( unsigned char ka0402$b_fill690 [28]; __union {N void *ka0402$l_ssr; /* System support register */ __struct {+ unsigned ka040 E-2$v_ssr_leds : 8;2 unsigned ka0402$v_ssr_lance_reset : 1;, unsigned ka0402$v_ssr_fill1 : 1;0 unsigned ka0402$v_ssr_rtc_reset : 1;0 unsigned ka0402$v_ssr_ssc_reset : 1;1 unsigned ka0402$v_ssr_isdn_reset : 1;2 unsigned ka0402$v_ssr_10baset_sel : 1;2 unsigned ka0402$v_ssr_ni_loopback : 1;, unsigned ka0402$v_ssr_txdis : 1;3 unsigned ka0402$v_ssr_lance_dma_en : 1;, unsigned ka0402$v_ss F-r_fill3 : 2;5 unsigned ka0402$v_ssr_isdn_rc_dma_en : 1;5 unsigned ka0402$v_ssr_isdn_tr_dma_en : 1;, unsigned ka0402$v_ssr_fill4 : 2;, unsigned ka0402$v_ssr_fill5 : 5;8 unsigned ka0402$v_ssr_printer_rc_dma_en : 1;8 unsigned ka0402$v_ssr_printer_tr_dma_en : 1;5 unsigned ka0402$v_ssr_comm_rc_dma_en : 1;5 unsigned ka0402$v_ssr_comm_tr_dma_en : 1; } ka0402$r_ssr_bits; } ka0402$r_ssr_ove G-rlay;( unsigned char ka0402$b_fill700 [28]; __union {N void *ka0402$l_sir; /* System interrupt register */ __struct {, unsigned ka0402$v_sir_halt0 : 1;, unsigned ka0402$v_sir_halt1 : 1;, unsigned ka0402$v_sir_fill1 : 1;2 unsigned ka0402$v_sir_alt_console : 1;, unsigned ka0402$v_sir_fill2 : 2;. unsigned ka0402$v_sir_scc0_si : 1;. unsigned ka0402$v_sir_scc1_si : 1;. H- unsigned ka0402$v_sir_ni_intr : 1;, unsigned ka0402$v_sir_fill3 : 4;0 unsigned ka0402$v_sir_isdn_intr : 1;, unsigned ka0402$v_sir_fill4 : 2;3 unsigned ka0402$v_sir_lance_dma_re : 1;, unsigned ka0402$v_sir_fill5 : 3;3 unsigned ka0402$v_sir_isdn_dma_mre : 1;7 unsigned ka0402$v_sir_isdn_dma_rc_intr : 1;7 unsigned ka0402$v_sir_isdn_dma_tr_intr : 1;, unsigned ka0402$v_sir_fill6 : 1;4 I- unsigned ka0402$v_sir_pp_rc_dma_ovr : 1;4 unsigned ka0402$v_sir_pp_rc_hp_intr : 1;4 unsigned ka0402$v_sir_pp_tr_dma_mre : 1;4 unsigned ka0402$v_sir_pp_tr_pe_intr : 1;6 unsigned ka0402$v_sir_comm_rc_dma_ovr : 1;6 unsigned ka0402$v_sir_comm_rc_hp_intr : 1;6 unsigned ka0402$v_sir_comm_tr_dma_mre : 1;6 unsigned ka0402$v_sir_comm_tr_pe_intr : 1; } ka0402$r_sir_bits; } ka0402$r_sir_overlay;( J-unsigned char ka0402$b_fill710 [28]; __union {N void *ka0402$l_simr; /* System interrupt mask register */ __struct {- unsigned ka0402$v_simr_halt0 : 1;- unsigned ka0402$v_simr_halt1 : 1;- unsigned ka0402$v_simr_fill1 : 1;3 unsigned ka0402$v_simr_alt_console : 1;- unsigned ka0402$v_simr_fill2 : 2;/ unsigned ka0402$v_simr_scc0_si : 1;/ unsigned ka0402$v_simr_scc1_si : 1;/ K- unsigned ka0402$v_simr_ni_intr : 1;- unsigned ka0402$v_simr_fill3 : 4;1 unsigned ka0402$v_simr_isdn_intr : 1;- unsigned ka0402$v_simr_fill4 : 2;4 unsigned ka0402$v_simr_lance_dma_re : 1;- unsigned ka0402$v_simr_fill5 : 3;4 unsigned ka0402$v_simr_isdn_dma_mre : 1;8 unsigned ka0402$v_simr_isdn_dma_rc_intr : 1;8 unsigned ka0402$v_simr_isdn_dma_tr_intr : 1;- unsigned ka0402$v_simr_fill6 L- : 1;5 unsigned ka0402$v_simr_pp_rc_dma_ovr : 1;5 unsigned ka0402$v_simr_pp_rc_hp_intr : 1;5 unsigned ka0402$v_simr_pp_tr_dma_mre : 1;5 unsigned ka0402$v_simr_pp_tr_pe_intr : 1;7 unsigned ka0402$v_simr_comm_rc_dma_ovr : 1;7 unsigned ka0402$v_simr_comm_rc_hp_intr : 1;7 unsigned ka0402$v_simr_comm_tr_dma_mre : 1;7 unsigned ka0402$v_simr_comm_tr_pe_intr : 1;! } ka0402$r_simr_bits; M- } ka0402$r_simr_overlay;( unsigned char ka0402$b_fill720 [28]; __union {N void *ka0402$l_sadr; /* System address register */ __struct {- unsigned ka0402$v_sadr_fill1 : 5;0 unsigned ka0402$v_sadr_tc_addr : 20;- unsigned ka0402$v_sadr_fill2 : 7;! } ka0402$r_sadr_bits; } ka0402$r_sadr_overlay;( unsigned char ka0402$b_fill730 [28]; __union {N void *ka0402$l_isdn_data_tr; /* I N-SDN Data Transmit */ __struct {5 unsigned ka0402$v_isdn_data_tr_data : 24;4 unsigned ka0402$v_isdn_data_tr_fill : 8;) } ka0402$r_isdn_data_tr_bits;( } ka0402$r_isdn_data_tr_overlay;( unsigned char ka0402$b_fill740 [28]; __union {N void *ka0402$l_isdn_data_rc; /* ISDN Data Receive */ __struct {5 unsigned ka0402$v_isdn_data_rc_data : 24;4 unsigned ka0402$v_isdn_d O-ata_rc_fill : 8;) } ka0402$r_isdn_data_rc_bits;( } ka0402$r_isdn_data_rc_overlay;( unsigned char ka0402$b_fill750 [28]; __union {N void *ka0402$l_lance_slot; /* Lance slot register */ __struct {0 unsigned ka0402$v_lance_slot_cs : 4;5 unsigned ka0402$v_lance_slot_hw_addr : 6;3 unsigned ka0402$v_lance_slot_fill : 22;' } ka0402$r_lance_slot_bits;& } ka0402$r_lance_slot_overlay;( P- unsigned char ka0402$b_fill760 [60]; __union {N void *ka0402$l_scc0_slot; /* SCC0 slot register */ __struct {/ unsigned ka0402$v_scc0_slot_cs : 4;4 unsigned ka0402$v_scc0_slot_hw_addr : 6;2 unsigned ka0402$v_scc0_slot_fill : 22;& } ka0402$r_scc0_slot_bits;% } ka0402$r_scc0_slot_overlay;( unsigned char ka0402$b_fill770 [28]; __union {N void *ka0402$l_scc1_slot; /* SCC1 slot Q- register */ __struct {/ unsigned ka0402$v_scc1_slot_cs : 4;4 unsigned ka0402$v_scc1_slot_hw_addr : 6;2 unsigned ka0402$v_scc1_slot_fill : 22;& } ka0402$r_scc1_slot_bits;% } ka0402$r_scc1_slot_overlay;* unsigned char ka0402$b_fill780 [7388];N void *ka0402$l_ni_adr_rom; /* Ethernet address ROM */* unsigned char ka0402$b_fill790 [8188];N void *ka0402$l_lance_rdp; /* Lance ethR-ernet CSR */R unsigned char ka0402$b_fill800 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_lance_rap; /* Lance ethernet CSR */* unsigned char ka0402$b_fill810 [8180];N void *ka0402$l_scc0b_comm_rap; /* Comm Port 1 RAP */R unsigned char ka0402$b_fill820 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_scc0b_comm_data; /* Comm Port 1 data */R unsigned char ka0402$bS-_fill830 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_scc0a_mouse_rap; /* Mouse RAP */R unsigned char ka0402$b_fill840 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_scc0a_mouse_data; /* Mouse port data register */* unsigned char ka0402$b_fill850 [8164];N void *ka0402$l_scc1b_print_rap; /* Printer Port 2 RAP */R unsigned char ka0402$b_fill860 [4]; /* Fill to allow sparse space byte mask T-*/N void *ka0402$l_scc1b_print_data; /* Printer Port 2 data */R unsigned char ka0402$b_fill870 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_scc1a_key_rap; /* Keyboard RAP */R unsigned char ka0402$b_fill880 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_scc1a_key_data; /* Keyboard port data register */* unsigned char ka0402$b_fill890 [8164];N void *ka0402$l_rtc_sec; /* TOY cloU-ck CSR--seconds */R unsigned char ka0402$b_fill900 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_alms; /* TOY clock CSR--seconds alarm */R unsigned char ka0402$b_fill910 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_min; /* TOY clock CSR--minutes */R unsigned char ka0402$b_fill920 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_almn; /* TOY clock CSR--minuteV-s alarm */R unsigned char ka0402$b_fill930 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_hour; /* TOY clock CSR--hours */R unsigned char ka0402$b_fill940 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_almh; /* TOY clock CSR--hours alarm */R unsigned char ka0402$b_fill950 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_dow; /* TOY clock CSR--day of week */W-R unsigned char ka0402$b_fill960 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_day; /* TOY clock CSR--date of month */R unsigned char ka0402$b_fill970 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_mon; /* TOY clock CSR--month */R unsigned char ka0402$b_fill980 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_year; /* TOY clock CSR--year */R unsignedX- char ka0402$b_fill990 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_rega; /* TOY clock CSR--register A */S unsigned char ka0402$b_fill1000 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_regb; /* TOY clock CSR--register B */S unsigned char ka0402$b_fill1010 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_regc; /* TOY clock CSR--register C */S unsigned char ka04Y-02$b_fill1020 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_regd; /* TOY clock CSR--register D */S unsigned char ka0402$b_fill1030 [4]; /* Fill to allow sparse space byte mask */N void *ka0402$l_rtc_ram; /* TOY clock CSR--base of BBU RAM */O unsigned char ka0402$b_fill1035 [260]; /* Fill to SCSO HOST ID location */P unsigned int ka0402$l_scsi_host_id; /* SCSI Host id for use by PKCDRIVER. */+ unsigned char ka0402$b_fill1Z-040 [7812];N void *ka0402$l_isdn_audio; /* ISDN audio chip CSR */N unsigned char ka0402$b_fill1050 [8188]; /* Fill to page boundary */N unsigned int ka0402$l_imask_read; /* Interrupt mask, read */N unsigned char ka0402$b_fill1060 [8188]; /* Fill to page boundary */N unsigned char ka0402$b_fill1065 [8188]; /* Fill to last lw in page */N unsigned int ka0402$l_imask_write; /* Interrupt mask, write */ } KA0402[-; #if !defined(__VAXC)?#define ka0402$l_ioslot ka0402$r_ioslot_overlay.ka0402$l_ioslotf#define ka0402$v_ioslot_slot0_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot0_sgf#define ka0402$v_ioslot_slot0_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot0_bmf#define ka0402$v_ioslot_slot0_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot0_pef#define ka0402$v_ioslot_slot1_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot\-1_sgf#define ka0402$v_ioslot_slot1_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot1_bmf#define ka0402$v_ioslot_slot1_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot1_pef#define ka0402$v_ioslot_slot2_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot2_sgf#define ka0402$v_ioslot_slot2_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot2_bmf#define ka0402$v_ioslot_slot2_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402]-$v_ioslot_slot2_pef#define ka0402$v_ioslot_slot3_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot3_sgf#define ka0402$v_ioslot_slot3_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot3_bmf#define ka0402$v_ioslot_slot3_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot3_pef#define ka0402$v_ioslot_slot4_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot4_sgf#define ka0402$v_ioslot_slot4_bm ka0402$r_ioslot_overlay.ka0402$r_iosl^-ot_bits.ka0402$v_ioslot_slot4_bmf#define ka0402$v_ioslot_slot4_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot4_pef#define ka0402$v_ioslot_slot5_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot5_sgf#define ka0402$v_ioslot_slot5_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot5_bmf#define ka0402$v_ioslot_slot5_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot5_pef#define ka0402$v_ioslot_slot6_sg ka0402$r_ioslot_overlay_-.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot6_sgf#define ka0402$v_ioslot_slot6_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot6_bmf#define ka0402$v_ioslot_slot6_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_slot6_ped#define ka0402$v_ioslot_core_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_core_sgd#define ka0402$v_ioslot_core_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_core_bmd#define ka0402$v_ioslot_core_pe ka0402$r_ioslo`-t_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_core_pej#define ka0402$v_ioslot_cxturbo_sg ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_cxturbo_sgj#define ka0402$v_ioslot_cxturbo_bm ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_cxturbo_bmj#define ka0402$v_ioslot_cxturbo_pe ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_cxturbo_pef#define ka0402$v_ioslot_rm_byte0 ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_rm_byte0f#define ka0402$v_iosloa-t_rm_byte1 ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_rm_byte1f#define ka0402$v_ioslot_rm_byte2 ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_rm_byte2f#define ka0402$v_ioslot_rm_byte3 ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_rm_byte3f#define ka0402$v_ioslot_rm_valid ka0402$r_ioslot_overlay.ka0402$r_ioslot_bits.ka0402$v_ioslot_rm_validE#define ka0402$l_tcconfig ka0402$r_tcconfig_overlay.ka0402$l_tcconfigh#define ka0402$v_tcconfig_magic ka0402$rb-_tcconfig_overlay.ka0402$r_tcconfig_bits.ka0402$v_tcconfig_magicp#define ka0402$v_tcconfig_page_size ka0402$r_tcconfig_overlay.ka0402$r_tcconfig_bits.ka0402$v_tcconfig_page_size?#define ka0402$l_tcereg ka0402$r_tcereg_overlay.ka0402$l_tceregd#define ka0402$v_tcereg_slot_id ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_slot_idZ#define ka0402$v_tcereg_sg ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_sgZ#define ka0402$v_tcereg_bm ka0402$r_tcereg_overlay.ka0402$r_tceregc-_bits.ka0402$v_tcereg_bmZ#define ka0402$v_tcereg_pe ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_pe^#define ka0402$v_tcereg_lock ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_lockb#define ka0402$v_tcereg_offset ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_offsetf#define ka0402$v_tcereg_syndrome ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_syndromef#define ka0402$v_tcereg_wm_byte0 ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_td-cereg_wm_byte0f#define ka0402$v_tcereg_wm_byte1 ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_wm_byte1f#define ka0402$v_tcereg_wm_byte2 ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_wm_byte2f#define ka0402$v_tcereg_wm_byte3 ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_wm_byte3X#define ka0402$v_tcereg_w ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_wX#define ka0402$v_tcereg_d ka0402$r_tcereg_overlay.ka0402$r_tcereg_bits.ka0402$v_tcereg_de-3#define ka0402$l_ir ka0402$r_ir_overlay.ka0402$l_irR#define ka0402$v_ir_tc_int ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_tc_intL#define ka0402$v_ir_seo ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_seoL#define ka0402$v_ir_dbf ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_dbfL#define ka0402$v_ir_x2k ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_x2kL#define ka0402$v_ir_tcr ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_tcrL#define ka0402$v_ir_tpe ka0402$r_ir_overlay.ka0402$r_if-r_bits.ka0402$v_ir_tpeL#define ka0402$v_ir_ter ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_terL#define ka0402$v_ir_sbe ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_sbeL#define ka0402$v_ir_dbe ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_dbeJ#define ka0402$v_ir_to ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_toJ#define ka0402$v_ir_tl ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_tlJ#define ka0402$v_ir_ia ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_iaJ#define ka0402$v_ir_g-nv ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_nvJ#define ka0402$v_ir_pe ka0402$r_ir_overlay.ka0402$r_ir_bits.ka0402$v_ir_pe3#define ka0402$l_ic ka0402$r_ic_overlay.ka0402$l_icR#define ka0402$v_ic_tc_int ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_tc_intL#define ka0402$v_ic_seo ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_seoL#define ka0402$v_ic_dbf ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_dbfL#define ka0402$v_ic_x2k ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_x2kL#dh-efine ka0402$v_ic_tcr ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_tcrL#define ka0402$v_ic_tpe ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_tpeL#define ka0402$v_ic_ter ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_terL#define ka0402$v_ic_sbe ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_sbeL#define ka0402$v_ic_dbe ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_dbeJ#define ka0402$v_ic_to ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_toJ#define ka0402$v_ic_tl ka0402$r_ic_overlayi-.ka0402$r_ic_bits.ka0402$v_ic_tlJ#define ka0402$v_ic_ia ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_iaJ#define ka0402$v_ic_nv ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_nvJ#define ka0402$v_ic_pe ka0402$r_ic_overlay.ka0402$r_ic_bits.ka0402$v_ic_pe6#define ka0402$l_ldp ka0402$r_ldp_overlay.ka0402$l_ldp\#define ka0402$v_ldp_dma_pa_lo ka0402$r_ldp_overlay.ka0402$r_ldp_bits.ka0402$v_ldp_dma_pa_lo\#define ka0402$v_ldp_dma_pa_hi ka0402$r_ldp_overlay.ka0402$r_ldp_bits.ka0402$v_ldp_dma_pa_hiEj-#define ka0402$l_scomm_tr ka0402$r_scomm_tr_overlay.ka0402$l_scomm_trj#define ka0402$v_scomm_tr_dma_pa ka0402$r_scomm_tr_overlay.ka0402$r_scomm_tr_bits.ka0402$v_scomm_tr_dma_paE#define ka0402$l_scomm_rc ka0402$r_scomm_rc_overlay.ka0402$l_scomm_rcj#define ka0402$v_scomm_rc_dma_pa ka0402$r_scomm_rc_overlay.ka0402$r_scomm_rc_bits.ka0402$v_scomm_rc_dma_paK#define ka0402$l_printer_tr ka0402$r_printer_tr_overlay.ka0402$l_printer_trr#define ka0402$v_printer_tr_dma_pa ka0402$r_printer_tr_overlay.ka040k-2$r_printer_tr_bits.ka0402$v_printer_tr_dma_paK#define ka0402$l_printer_rc ka0402$r_printer_rc_overlay.ka0402$l_printer_rcr#define ka0402$v_printer_rc_dma_pa ka0402$r_printer_rc_overlay.ka0402$r_printer_rc_bits.ka0402$v_printer_rc_dma_paB#define ka0402$l_isdn_tr ka0402$r_isdn_tr_overlay.ka0402$l_isdn_trf#define ka0402$v_isdn_tr_dma_pa ka0402$r_isdn_tr_overlay.ka0402$r_isdn_tr_bits.ka0402$v_isdn_tr_dma_paN#define ka0402$l_isdn_tr_buf ka0402$r_isdn_tr_buf_overlay.ka0402$l_isdn_tr_bufv#define ka04l-02$v_isdn_tr_buf_dma_pa ka0402$r_isdn_tr_buf_overlay.ka0402$r_isdn_tr_buf_bits.ka0402$v_isdn_tr_buf_dma_paB#define ka0402$l_isdn_rc ka0402$r_isdn_rc_overlay.ka0402$l_isdn_rcf#define ka0402$v_isdn_rc_dma_pa ka0402$r_isdn_rc_overlay.ka0402$r_isdn_rc_bits.ka0402$v_isdn_rc_dma_paN#define ka0402$l_isdn_rc_buf ka0402$r_isdn_rc_buf_overlay.ka0402$l_isdn_rc_bufv#define ka0402$v_isdn_rc_buf_dma_pa ka0402$r_isdn_rc_buf_overlay.ka0402$r_isdn_rc_buf_bits.ka0402$v_isdn_rc_buf_dma_pa6#define ka0402$l_ssr ka040m-2$r_ssr_overlay.ka0402$l_ssrR#define ka0402$v_ssr_leds ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_leds`#define ka0402$v_ssr_lance_reset ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_lance_reset\#define ka0402$v_ssr_rtc_reset ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_rtc_reset\#define ka0402$v_ssr_ssc_reset ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_ssc_reset^#define ka0402$v_ssr_isdn_reset ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_isdn_reset`#define kan-0402$v_ssr_10baset_sel ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_10baset_sel`#define ka0402$v_ssr_ni_loopback ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_ni_loopbackT#define ka0402$v_ssr_txdis ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_txdisb#define ka0402$v_ssr_lance_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_lance_dma_enf#define ka0402$v_ssr_isdn_rc_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_isdn_rc_dma_enf#define ka0402$v_ssr_isdn_tr_do-ma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_isdn_tr_dma_enl#define ka0402$v_ssr_printer_rc_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_printer_rc_dma_enl#define ka0402$v_ssr_printer_tr_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_printer_tr_dma_enf#define ka0402$v_ssr_comm_rc_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_comm_rc_dma_enf#define ka0402$v_ssr_comm_tr_dma_en ka0402$r_ssr_overlay.ka0402$r_ssr_bits.ka0402$v_ssr_comm_tr_dma_en6#defp-ine ka0402$l_sir ka0402$r_sir_overlay.ka0402$l_sirT#define ka0402$v_sir_halt0 ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_halt0T#define ka0402$v_sir_halt1 ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_halt1`#define ka0402$v_sir_alt_console ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_alt_consoleX#define ka0402$v_sir_scc0_si ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_scc0_siX#define ka0402$v_sir_scc1_si ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_scc1_siX#defq-ine ka0402$v_sir_ni_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_ni_intr\#define ka0402$v_sir_isdn_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_isdn_intrb#define ka0402$v_sir_lance_dma_re ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_lance_dma_reb#define ka0402$v_sir_isdn_dma_mre ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_isdn_dma_mrej#define ka0402$v_sir_isdn_dma_rc_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_isdn_dma_rc_intrj#define ka0402$v_sr-ir_isdn_dma_tr_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_isdn_dma_tr_intrd#define ka0402$v_sir_pp_rc_dma_ovr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_pp_rc_dma_ovrd#define ka0402$v_sir_pp_rc_hp_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_pp_rc_hp_intrd#define ka0402$v_sir_pp_tr_dma_mre ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_pp_tr_dma_mred#define ka0402$v_sir_pp_tr_pe_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_pp_tr_pe_intrh#define s-ka0402$v_sir_comm_rc_dma_ovr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_comm_rc_dma_ovrh#define ka0402$v_sir_comm_rc_hp_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_comm_rc_hp_intrh#define ka0402$v_sir_comm_tr_dma_mre ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_comm_tr_dma_mreh#define ka0402$v_sir_comm_tr_pe_intr ka0402$r_sir_overlay.ka0402$r_sir_bits.ka0402$v_sir_comm_tr_pe_intr9#define ka0402$l_simr ka0402$r_simr_overlay.ka0402$l_simrX#define ka0402$v_simr_halt0 kat-0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_halt0X#define ka0402$v_simr_halt1 ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_halt1d#define ka0402$v_simr_alt_console ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_alt_console\#define ka0402$v_simr_scc0_si ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_scc0_si\#define ka0402$v_simr_scc1_si ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_scc1_si\#define ka0402$v_simr_ni_intr ka0402$r_simr_overlay.ka0402$r_simr_u-bits.ka0402$v_simr_ni_intr`#define ka0402$v_simr_isdn_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_isdn_intrf#define ka0402$v_simr_lance_dma_re ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_lance_dma_ref#define ka0402$v_simr_isdn_dma_mre ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_isdn_dma_mren#define ka0402$v_simr_isdn_dma_rc_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_isdn_dma_rc_intrn#define ka0402$v_simr_isdn_dma_tr_intr ka0402$r_simr_overlayv-.ka0402$r_simr_bits.ka0402$v_simr_isdn_dma_tr_intrh#define ka0402$v_simr_pp_rc_dma_ovr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_pp_rc_dma_ovrh#define ka0402$v_simr_pp_rc_hp_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_pp_rc_hp_intrh#define ka0402$v_simr_pp_tr_dma_mre ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_pp_tr_dma_mreh#define ka0402$v_simr_pp_tr_pe_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_pp_tr_pe_intrl#define ka0402$v_simr_comm_rc_w-dma_ovr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_comm_rc_dma_ovrl#define ka0402$v_simr_comm_rc_hp_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_comm_rc_hp_intrl#define ka0402$v_simr_comm_tr_dma_mre ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_comm_tr_dma_mrel#define ka0402$v_simr_comm_tr_pe_intr ka0402$r_simr_overlay.ka0402$r_simr_bits.ka0402$v_simr_comm_tr_pe_intr9#define ka0402$l_sadr ka0402$r_sadr_overlay.ka0402$l_sadr\#define ka0402$v_sadr_tc_addr ka0402x-$r_sadr_overlay.ka0402$r_sadr_bits.ka0402$v_sadr_tc_addrQ#define ka0402$l_isdn_data_tr ka0402$r_isdn_data_tr_overlay.ka0402$l_isdn_data_trv#define ka0402$v_isdn_data_tr_data ka0402$r_isdn_data_tr_overlay.ka0402$r_isdn_data_tr_bits.ka0402$v_isdn_data_tr_dataQ#define ka0402$l_isdn_data_rc ka0402$r_isdn_data_rc_overlay.ka0402$l_isdn_data_rcv#define ka0402$v_isdn_data_rc_data ka0402$r_isdn_data_rc_overlay.ka0402$r_isdn_data_rc_bits.ka0402$v_isdn_data_rc_dataK#define ka0402$l_lance_slot ka0402$r_lany-ce_slot_overlay.ka0402$l_lance_slotj#define ka0402$v_lance_slot_cs ka0402$r_lance_slot_overlay.ka0402$r_lance_slot_bits.ka0402$v_lance_slot_cst#define ka0402$v_lance_slot_hw_addr ka0402$r_lance_slot_overlay.ka0402$r_lance_slot_bits.ka0402$v_lance_slot_hw_addrH#define ka0402$l_scc0_slot ka0402$r_scc0_slot_overlay.ka0402$l_scc0_slotf#define ka0402$v_scc0_slot_cs ka0402$r_scc0_slot_overlay.ka0402$r_scc0_slot_bits.ka0402$v_scc0_slot_csp#define ka0402$v_scc0_slot_hw_addr ka0402$r_scc0_slot_overlay.ka z-0402$r_scc0_slot_bits.ka0402$v_scc0_slot_hw_addrH#define ka0402$l_scc1_slot ka0402$r_scc1_slot_overlay.ka0402$l_scc1_slotf#define ka0402$v_scc1_slot_cs ka0402$r_scc1_slot_overlay.ka0402$r_scc1_slot_bits.ka0402$v_scc1_slot_csp#define ka0402$v_scc1_slot_hw_addr ka0402$r_scc1_slot_overlay.ka0402$r_scc1_slot_bits.ka0402$v_scc1_slot_hw_addr"#endif /* #if !defined(__VAXC) */ $#define KA0402$M_SG_MAP_PPN 0x1FFFFF"#define KA0402$M_SG_MAP_P 0x200000"#define KA0402$M_SG_MAP_F 0x400000"#define KA0402{-$M_SG_MAP_V 0x800000 ,typedef struct _ka0402$r_sg_map_entry_bits { __union { __struct {. unsigned ka0402$v_sg_map_ppn : 21;+ unsigned ka0402$v_sg_map_p : 1;+ unsigned ka0402$v_sg_map_f : 1;+ unsigned ka0402$v_sg_map_v : 1;) } ka0402$r_sg_map_entry_bits;( } ka0402$r_sg_map_entry_overlay;! } KA0402$R_SG_MAP_ENTRY_BITS; #if !defined(__VAXC)h#define ka0402$v_sg_map_ppn ka0402$r_sg_map_entry_overlay.ka04 |-02$r_sg_map_entry_bits.ka0402$v_sg_map_ppnd#define ka0402$v_sg_map_p ka0402$r_sg_map_entry_overlay.ka0402$r_sg_map_entry_bits.ka0402$v_sg_map_pd#define ka0402$v_sg_map_f ka0402$r_sg_map_entry_overlay.ka0402$r_sg_map_entry_bits.ka0402$v_sg_map_fd#define ka0402$v_sg_map_v ka0402$r_sg_map_entry_overlay.ka0402$r_sg_map_entry_bits.ka0402$v_sg_map_v"#endif /* #if !defined(__VAXC) */ ,#define KA0402$M_SG_MAP_VA_LW_IN_PAGE 0x1FFF)#define KA0402$M_SG_MAP_VA_PAGE 0xFFFE000 )typedef struct _ka0402 }-$r_sg_map_va_bits { __union { __struct {8 unsigned ka0402$v_sg_map_va_lw_in_page : 13;2 unsigned ka0402$v_sg_map_va_page : 15;* unsigned ka0402$v_fill_0_ : 4;& } ka0402$r_sg_map_va_bits;% } ka0402$r_sg_map_va_overlay; } KA0402$R_SG_MAP_VA_BITS; #if !defined(__VAXC)v#define ka0402$v_sg_map_va_lw_in_page ka0402$r_sg_map_va_overlay.ka0402$r_sg_map_va_bits.ka0402$v_sg_map_va_lw_in_pagej#define ka0402$v_sg_map_va_page ka~-0402$r_sg_map_va_overlay.ka0402$r_sg_map_va_bits.ka0402$v_sg_map_va_page"#endif /* #if !defined(__VAXC) */ #define KA0402$K_IO_SCB_VEC 2048"#define KA0402$K_CORE_IO_TC_SLOT 7"#define KA0402$K_CXTURBO_TC_SLOT 8#define KA0402$K_TC_SLOT0_VEC 0#define KA0402$K_TC_SLOT1_VEC 1#define KA0402$K_TC_SLOT2_VEC 2#define KA0402$K_TC_SLOT3_VEC 3#define KA0402$K_TC_SLOT4_VEC 4#define KA0402$K_TC_SLOT5_VEC 5#define KA0402$K_TC_SLOT6_VEC 6#define KA0402$K_ETHERNET_VEC 7#define KA0402-$K_ISDN_VEC 8#define KA0402$K_CXTURBO_VEC 9#define KA0402$K_SCC_VEC 10#define KA0402$K_OPDRVR_XMIT 11#define KA0402$K_OPDRVR_RCV 12!#define KA0402$K_TOTAL_VECTORS 13#define KA0402$M_MASK0 0x1#define KA0402$M_MASK1 0x2#define KA0402$M_MASK2 0x4#define KA0402$M_MASK3 0x8 )typedef struct _ka0402$r_byte_mask_bits { __union { __struct {( unsigned ka0402$v_mask0 : 1;( unsigned ka0402$v_mask1 : 1;( unsigned ka0402$v_mask2 : 1;( - unsigned ka0402$v_mask3 : 1;* unsigned ka0402$v_fill_1_ : 4;& } ka0402$r_byte_mask_bits;% } ka0402$r_byte_mask_overlay; } KA0402$R_BYTE_MASK_BITS; #if !defined(__VAXC)X#define ka0402$v_mask0 ka0402$r_byte_mask_overlay.ka0402$r_byte_mask_bits.ka0402$v_mask0X#define ka0402$v_mask1 ka0402$r_byte_mask_overlay.ka0402$r_byte_mask_bits.ka0402$v_mask1X#define ka0402$v_mask2 ka0402$r_byte_mask_overlay.ka0402$r_byte_mask_bits.ka0402$v_mask2X#define ka0402-$v_mask3 ka0402$r_byte_mask_overlay.ka0402$r_byte_mask_bits.ka0402$v_mask3"#endif /* #if !defined(__VAXC) */ P/* The following definition defines an entry of a Saved Error Register Table. */T/* This table is pointed to by a cell in the Turbo ADP. The table is divided up */T/* into an entry for each slot. Each entry contains saved copies of IR, TCEREG, */V/* and FADR. The entries are written by the machine check handler on an error, and */N/* read by a driver (at some appropriate time) t -o determine if a TC error */N/* occurred. */N/* Define Saved Register Table Entry */&#define KA0402$M_SAVED_IR_TC_INT 0x1FF%#define KA0402$M_SAVED_IR_SEO 0x80000&#define KA0402$M_SAVED_IR_DBF 0x100000&#define KA0402$M_SAVED_IR_X2K 0x200000&#define KA0402$M_SAVED_IR_TCR 0x400000&#define KA0402$M_SAVED_IR_TPE 0x800000'#define KA0402$M_SAVED_IR_TER 0x1000000'#define KA0402$M_SAVED_IR_SBE 0x -2000000'#define KA0402$M_SAVED_IR_DBE 0x4000000&#define KA0402$M_SAVED_IR_TO 0x8000000'#define KA0402$M_SAVED_IR_TL 0x10000000'#define KA0402$M_SAVED_IR_IA 0x20000000'#define KA0402$M_SAVED_IR_NV 0x40000000'#define KA0402$M_SAVED_IR_PE 0x80000000)#define KA0402$M_SAVED_TCEREG_SLOT_ID 0xF%#define KA0402$M_SAVED_TCEREG_SG 0x10%#define KA0402$M_SAVED_TCEREG_BM 0x20%#define KA0402$M_SAVED_TCEREG_PE 0x40'#define KA0402$M_SAVED_TCEREG_LOCK 0x80+#define KA0402$M_SAVED_TCEREG_OFFSET 0x1 -F00/#define KA0402$M_SAVED_TCEREG_SYNDROME 0x7F00000#define KA0402$M_SAVED_TCEREG_WM_BYTE0 0x10000000#define KA0402$M_SAVED_TCEREG_WM_BYTE1 0x20000000#define KA0402$M_SAVED_TCEREG_WM_BYTE2 0x40000000#define KA0402$M_SAVED_TCEREG_WM_BYTE3 0x8000000*#define KA0402$M_SAVED_TCEREG_W 0x40000000*#define KA0402$M_SAVED_TCEREG_D 0x80000000(#define KA0402$K_SAVED_REG_ENTRY_SIZE 16 !typedef struct _saved_reg_entry { __union {N unsigned int ka0402$l_saved_ir; /* Interrupt reason - */ __struct {2 unsigned ka0402$v_saved_ir_tc_int : 9;2 unsigned ka0402$v_saved_ir_fill1 : 10;/ unsigned ka0402$v_saved_ir_seo : 1;/ unsigned ka0402$v_saved_ir_dbf : 1;/ unsigned ka0402$v_saved_ir_x2k : 1;/ unsigned ka0402$v_saved_ir_tcr : 1;/ unsigned ka0402$v_saved_ir_tpe : 1;/ unsigned ka0402$v_saved_ir_ter : 1;/ unsigned ka0402$v_saved_ir_sbe : 1;/ un -signed ka0402$v_saved_ir_dbe : 1;. unsigned ka0402$v_saved_ir_to : 1;. unsigned ka0402$v_saved_ir_tl : 1;. unsigned ka0402$v_saved_ir_ia : 1;. unsigned ka0402$v_saved_ir_nv : 1;. unsigned ka0402$v_saved_ir_pe : 1;% } ka0402$r_saved_ir_bits;$ } ka0402$r_saved_ir_overlay; __union {N unsigned int ka0402$l_saved_tcereg; /* Error register */ __struct {7 unsigned ka0402$v_save -d_tcereg_slot_id : 4;2 unsigned ka0402$v_saved_tcereg_sg : 1;2 unsigned ka0402$v_saved_tcereg_bm : 1;2 unsigned ka0402$v_saved_tcereg_pe : 1;4 unsigned ka0402$v_saved_tcereg_lock : 1;6 unsigned ka0402$v_saved_tcereg_offset : 5;5 unsigned ka0402$v_saved_tcereg_fill2 : 3;8 unsigned ka0402$v_saved_tcereg_syndrome : 7;5 unsigned ka0402$v_saved_tcereg_fill3 : 1;8 unsigned ka0402$v_saved_tcereg_wm_ -byte0 : 1;8 unsigned ka0402$v_saved_tcereg_wm_byte1 : 1;8 unsigned ka0402$v_saved_tcereg_wm_byte2 : 1;8 unsigned ka0402$v_saved_tcereg_wm_byte3 : 1;5 unsigned ka0402$v_saved_tcereg_fill4 : 2;1 unsigned ka0402$v_saved_tcereg_w : 1;1 unsigned ka0402$v_saved_tcereg_d : 1;) } ka0402$r_saved_tcereg_bits;( } ka0402$r_saved_tcereg_overlay;N void *ka0402$l_saved_fadr; /* Failing Address - */N unsigned int ka0402$l_fill; /* to quad boundary */ } SAVED_REG_ENTRY; #if !defined(__VAXC)E#define ka0402$l_saved_ir ka0402$r_saved_ir_overlay.ka0402$l_saved_irj#define ka0402$v_saved_ir_tc_int ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_tc_intd#define ka0402$v_saved_ir_seo ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_seod#define ka0402$v_saved_ir_dbf ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_-saved_ir_dbfd#define ka0402$v_saved_ir_x2k ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_x2kd#define ka0402$v_saved_ir_tcr ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_tcrd#define ka0402$v_saved_ir_tpe ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_tped#define ka0402$v_saved_ir_ter ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_terd#define ka0402$v_saved_ir_sbe ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka040-2$v_saved_ir_sbed#define ka0402$v_saved_ir_dbe ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_dbeb#define ka0402$v_saved_ir_to ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_tob#define ka0402$v_saved_ir_tl ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_tlb#define ka0402$v_saved_ir_ia ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_iab#define ka0402$v_saved_ir_nv ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v-_saved_ir_nvb#define ka0402$v_saved_ir_pe ka0402$r_saved_ir_overlay.ka0402$r_saved_ir_bits.ka0402$v_saved_ir_peQ#define ka0402$l_saved_tcereg ka0402$r_saved_tcereg_overlay.ka0402$l_saved_tcereg|#define ka0402$v_saved_tcereg_slot_id ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_slot_idr#define ka0402$v_saved_tcereg_sg ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_sgr#define ka0402$v_saved_tcereg_bm ka0402$r_saved_tcereg_overlay.ka0-402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_bmr#define ka0402$v_saved_tcereg_pe ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_pev#define ka0402$v_saved_tcereg_lock ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_lockz#define ka0402$v_saved_tcereg_offset ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_offset~#define ka0402$v_saved_tcereg_syndrome ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.-ka0402$v_saved_tcereg_syndrome~#define ka0402$v_saved_tcereg_wm_byte0 ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_wm_byte0~#define ka0402$v_saved_tcereg_wm_byte1 ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_wm_byte1~#define ka0402$v_saved_tcereg_wm_byte2 ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_wm_byte2~#define ka0402$v_saved_tcereg_wm_byte3 ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg -_bits.ka0402$v_saved_tcereg_wm_byte3p#define ka0402$v_saved_tcereg_w ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_wp#define ka0402$v_saved_tcereg_d ka0402$r_saved_tcereg_overlay.ka0402$r_saved_tcereg_bits.ka0402$v_saved_tcereg_d"#endif /* #if !defined(__VAXC) */ N/* Define indexes into error table. Indexes are 0 thru 10. */N/* The count of the number of entries is 11. */#define KA0402$K_SLOT0_INDEX 0#define -KA0402$K_SLOT1_INDEX 1#define KA0402$K_SLOT2_INDEX 2#define KA0402$K_SLOT3_INDEX 3#define KA0402$K_SLOT4_INDEX 4#define KA0402$K_SLOT5_INDEX 5#define KA0402$K_SCSI_INDEX 6 #define KA0402$K_CORE_NI_INDEX 7!#define KA0402$K_CORE_SLU_INDEX 8"#define KA0402$K_CORE_ISDN_INDEX 9!#define KA0402$K_CXTURBO_INDEX 10)#define KA0402$K_SAVED_REG_ENTRY_COUNT 11 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __-required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KA0402DEF_LOADED */ wwa[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Dev-elopment, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not - **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************************* -*******************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */I/* Source: 24-MAR-1993 14:33:00 $1$DGA8345:[LIB_H.SRC]KA0602DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KA0602DEF ***/#ifndef __KA0602DEF_LOADED#define __KA0602DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save-#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __st-ruct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif '#define KA0602$M_COMBO_TOY_RTCA_RS0 0x1'#define KA0602$M_COMBO_TOY_RTCA_RS1 0x2'#define KA0602$M_COMBO_TOY_RTCA_RS2 0x4'#define KA0602$M_COMBO_TOY_RTCA_RS3 0x8(#define KA0602$M_COMBO_TOY_RTCA_DV0 0x10(#define KA0602$M_COMBO_TOY_RTCA_DV1 0x20(#define KA0602 -$M_COMBO_TOY_RTCA_DV2 0x40(#define KA0602$M_COMBO_TOY_RTCA_UIP 0x80'#define KA0602$M_COMBO_TOY_RTCB_DSE 0x1(#define KA0602$M_COMBO_TOY_RTCB_2412 0x2&#define KA0602$M_COMBO_TOY_RTCB_DM 0x4(#define KA0602$M_COMBO_TOY_RTCB_UIE 0x10(#define KA0602$M_COMBO_TOY_RTCB_AIE 0x20(#define KA0602$M_COMBO_TOY_RTCB_PIE 0x40(#define KA0602$M_COMBO_TOY_RTCB_SET 0x80'#define KA0602$M_COMBO_TOY_RTCC_UF 0x10'#define KA0602$M_COMBO_TOY_RTCC_AF 0x20'#define KA0602$M_COMBO_TOY_RTCC_PF 0x40)#define KA0602$M_C-OMBO_TOY_RTCC_IRQF 0x80(#define KA0602$M_COMBO_TOY_RTCD_VRT 0x80##define KA0602$M_HAE_EISA_ADDR 0x7F #define KA0602$M_SYSCTL_LEDS 0xF #define KA0602$M_SYSCTL_IOR 0x10##define KA0602$M_SYSCTL_ERRENB 0x20"#define KA0602$M_SYSCTL_MCNFG 0xC0"#define KA0602$M_INT1_OCW2_IRQ 0x7##define KA0602$M_INT1_OCW2_SEL 0x18##define KA0602$M_INT1_OCW2_EOI 0x20"#define KA0602$M_INT1_OCW2_SL 0x40##define KA0602$M_INT1_OCW2_ROT 0x80"#define KA0602$M_INT1_OCW3_RIS 0x1!#define KA0602$M_INT1_OCW3_RR 0x2 -#define KA0602$M_INT1_OCW3_P 0x4##define KA0602$M_INT1_OCW3_SEL 0x18##define KA0602$M_INT1_OCW3_SMM 0x20$#define KA0602$M_INT1_OCW3_ESMM 0x40!#define KA0602$M_INT1_OCW1_M0 0x1!#define KA0602$M_INT1_OCW1_M1 0x2!#define KA0602$M_INT1_OCW1_M2 0x4!#define KA0602$M_INT1_OCW1_M3 0x8"#define KA0602$M_INT1_OCW1_M4 0x10"#define KA0602$M_INT1_OCW1_M5 0x20"#define KA0602$M_INT1_OCW1_M6 0x40"#define KA0602$M_INT1_OCW1_M7 0x80"#define KA0602$M_INT2_OCW2_IRQ 0x7##define KA0602$M_INT2_OCW2_SEL 0x1-8##define KA0602$M_INT2_OCW2_EOI 0x20"#define KA0602$M_INT2_OCW2_SL 0x40##define KA0602$M_INT2_OCW2_ROT 0x80"#define KA0602$M_INT2_OCW3_RIS 0x1!#define KA0602$M_INT2_OCW3_RR 0x2 #define KA0602$M_INT2_OCW3_P 0x4##define KA0602$M_INT2_OCW3_SEL 0x18##define KA0602$M_INT2_OCW3_SMM 0x20$#define KA0602$M_INT2_OCW3_ESMM 0x40!#define KA0602$M_INT2_OCW1_M0 0x1!#define KA0602$M_INT2_OCW1_M1 0x2!#define KA0602$M_INT2_OCW1_M2 0x4!#define KA0602$M_INT2_OCW1_M3 0x8"#define KA0602$M_INT2_OCW1-_M4 0x10"#define KA0602$M_INT2_OCW1_M5 0x20"#define KA0602$M_INT2_OCW1_M6 0x40"#define KA0602$M_INT2_OCW1_M7 0x80X#define KA0602$S_KA0602DEF 548865 /* Old size name, synonym for KA0602$S_KA0602 */ typedef struct _ka0602 { __union {) unsigned int ka0602$l_port_index;& } ka0602$r_port_index_overlay;! char ka0602$b_fill0001 [508]; __union {( unsigned int ka0602$l_port_data;% } ka0602$r_port_data_overlay;! char ka0602$b_fill0002 [508];- __union {- unsigned int ka0602$l_combo_toy_mins;* } ka0602$r_combo_toy_mins_overlay;! char ka0602$b_fill0003 [508]; __union {. unsigned int ka0602$l_combo_toy_amins;+ } ka0602$r_combo_toy_amins_overlay;! char ka0602$b_fill0004 [508]; __union {, unsigned int ka0602$l_combo_toy_hrs;) } ka0602$r_combo_toy_hrs_overlay;! char ka0602$b_fill0005 [508]; __union {- unsigned int ka0602$l_combo_toy_ahrs;* -} ka0602$r_combo_toy_ahrs_overlay;! char ka0602$b_fill0006 [508]; __union {, unsigned int ka0602$l_combo_toy_day;) } ka0602$r_combo_toy_day_overlay;! char ka0602$b_fill0007 [508]; __union {- unsigned int ka0602$l_combo_toy_mnth;* } ka0602$r_combo_toy_mnth_overlay;! char ka0602$b_fill0008 [508]; __union {- unsigned int ka0602$l_combo_toy_year;* } ka0602$r_combo_toy_year_overlay;! char ka0602$b_fill0009 [508]; -__union {- unsigned int ka0602$l_combo_toy_rtca; __struct {5 unsigned ka0602$v_combo_toy_rtca_rs0 : 1;5 unsigned ka0602$v_combo_toy_rtca_rs1 : 1;5 unsigned ka0602$v_combo_toy_rtca_rs2 : 1;5 unsigned ka0602$v_combo_toy_rtca_rs3 : 1;5 unsigned ka0602$v_combo_toy_rtca_dv0 : 1;5 unsigned ka0602$v_combo_toy_rtca_dv1 : 1;5 unsigned ka0602$v_combo_toy_rtca_dv2 : 1;5 unsigned ka0602$v_co -mbo_toy_rtca_uip : 1;+ } ka0602$r_combo_toy_rtca_bits;* } ka0602$r_combo_toy_rtca_overlay;! char ka0602$b_fill0010 [508]; __union {- unsigned int ka0602$l_combo_toy_rtcb; __struct {5 unsigned ka0602$v_combo_toy_rtcb_dse : 1;6 unsigned ka0602$v_combo_toy_rtcb_2412 : 1;4 unsigned ka0602$v_combo_toy_rtcb_dm : 1;6 unsigned ka0602$v_combo_toy_rtcb_fill : 1;5 unsigned ka0602$v_combo_toy_rtcb_uie - : 1;5 unsigned ka0602$v_combo_toy_rtcb_aie : 1;5 unsigned ka0602$v_combo_toy_rtcb_pie : 1;5 unsigned ka0602$v_combo_toy_rtcb_set : 1;+ } ka0602$r_combo_toy_rtcb_bits;* } ka0602$r_combo_toy_rtcb_overlay;! char ka0602$b_fill0011 [508]; __union {- unsigned int ka0602$l_combo_toy_rtcc; __struct {6 unsigned ka0602$v_combo_toy_rtcc_fill : 4;4 unsigned ka0602$v_combo_toy_rtcc_uf : 1;4 - unsigned ka0602$v_combo_toy_rtcc_af : 1;4 unsigned ka0602$v_combo_toy_rtcc_pf : 1;6 unsigned ka0602$v_combo_toy_rtcc_irqf : 1;+ } ka0602$r_combo_toy_rtcc_bits;* } ka0602$r_combo_toy_rtcc_overlay;! char ka0602$b_fill0012 [508]; __union {- unsigned int ka0602$l_combo_toy_rtcd; __struct {6 unsigned ka0602$v_combo_toy_rtcd_fill : 7;5 unsigned ka0602$v_combo_toy_rtcd_vrt : 1;+ } ka0602$r_com-bo_toy_rtcd_bits;* } ka0602$r_combo_toy_rtcd_overlay;" char ka0602$b_fill0013 [2044]; __union {" unsigned int ka0602$l_hae; __struct {0 unsigned ka0602$v_hae_eisa_addr : 7;, unsigned ka0602$v_hae_fill1 : 1; } ka0602$r_hae_bits; } ka0602$r_hae_overlay;! char ka0602$b_fill2aa [8188]; __union {% unsigned int ka0602$l_sysctl; __struct {. unsigned ka0602$v_sysctl_leds : 4;- - unsigned ka0602$v_sysctl_ior : 1;0 unsigned ka0602$v_sysctl_errenb : 1;/ unsigned ka0602$v_sysctl_mcnfg : 2;# } ka0602$r_sysctl_bits;" } ka0602$r_sysctl_overlay; char ka0602$b_fill3 [8188]; __union {+ unsigned char ka0602$b_dma1_ch0_ca;' } ka0602$r_dma1_ch0_ca_overlay; char ka0602$b_fill4 [4095]; __union {) unsigned char ka0602$b_int1_ocw2; __struct {0 unsigned ka0602$v_int1_o -cw2_irq : 3;0 unsigned ka0602$v_int1_ocw2_sel : 2;0 unsigned ka0602$v_int1_ocw2_eoi : 1;/ unsigned ka0602$v_int1_ocw2_sl : 1;0 unsigned ka0602$v_int1_ocw2_rot : 1;& } ka0602$r_int1_ocw2_bits; __struct {0 unsigned ka0602$v_int1_ocw3_ris : 1;/ unsigned ka0602$v_int1_ocw3_rr : 1;. unsigned ka0602$v_int1_ocw3_p : 1;0 unsigned ka0602$v_int1_ocw3_sel : 2;0 unsigned ka0602$v_in -t1_ocw3_smm : 1;1 unsigned ka0602$v_int1_ocw3_esmm : 1;1 unsigned ka0602$v_int1_ocw3_fill : 1;& } ka0602$r_int1_ocw3_bits;% } ka0602$r_int1_ocw2_overlay; char ka0602$b_fill5 [127]; __union {) unsigned char ka0602$b_int1_ocw1; __struct {/ unsigned ka0602$v_int1_ocw1_m0 : 1;/ unsigned ka0602$v_int1_ocw1_m1 : 1;/ unsigned ka0602$v_int1_ocw1_m2 : 1;/ unsigned ka0602$v_int1_ocw1_-m3 : 1;/ unsigned ka0602$v_int1_ocw1_m4 : 1;/ unsigned ka0602$v_int1_ocw1_m5 : 1;/ unsigned ka0602$v_int1_ocw1_m6 : 1;/ unsigned ka0602$v_int1_ocw1_m7 : 1;& } ka0602$r_int1_ocw1_bits;% } ka0602$r_int1_ocw1_overlay; char ka0602$b_fill6 [16255]; __union {) unsigned char ka0602$b_int2_ocw2; __struct {0 unsigned ka0602$v_int2_ocw2_irq : 3;0 unsigned ka0602$v_int2_ocw2_sel : 2;0 - unsigned ka0602$v_int2_ocw2_eoi : 1;/ unsigned ka0602$v_int2_ocw2_sl : 1;0 unsigned ka0602$v_int2_ocw2_rot : 1;& } ka0602$r_int2_ocw2_bits; __struct {0 unsigned ka0602$v_int2_ocw3_ris : 1;/ unsigned ka0602$v_int2_ocw3_rr : 1;. unsigned ka0602$v_int2_ocw3_p : 1;0 unsigned ka0602$v_int2_ocw3_sel : 2;0 unsigned ka0602$v_int2_ocw3_smm : 1;1 unsigned ka0602$v_int2_ocw3_esmm :- 1;1 unsigned ka0602$v_int2_ocw3_fill : 1;& } ka0602$r_int2_ocw3_bits;% } ka0602$r_int2_ocw2_overlay; char ka0602$b_fill7 [127]; __union {) unsigned char ka0602$b_int2_ocw1; __struct {/ unsigned ka0602$v_int2_ocw1_m0 : 1;/ unsigned ka0602$v_int2_ocw1_m1 : 1;/ unsigned ka0602$v_int2_ocw1_m2 : 1;/ unsigned ka0602$v_int2_ocw1_m3 : 1;/ unsigned ka0602$v_int2_ocw1_m4 : 1;/ - unsigned ka0602$v_int2_ocw1_m5 : 1;/ unsigned ka0602$v_int2_ocw1_m6 : 1;/ unsigned ka0602$v_int2_ocw1_m7 : 1;& } ka0602$r_int2_ocw1_bits;% } ka0602$r_int2_ocw1_overlay;! char ka0602$b_fill8 [503680]; } KA0602; #if !defined(__VAXC)K#define ka0602$l_port_index ka0602$r_port_index_overlay.ka0602$l_port_indexH#define ka0602$l_port_data ka0602$r_port_data_overlay.ka0602$l_port_dataW#define ka0602$l_combo_toy_mins ka0602$r_combo_toy-_mins_overlay.ka0602$l_combo_toy_minsZ#define ka0602$l_combo_toy_amins ka0602$r_combo_toy_amins_overlay.ka0602$l_combo_toy_aminsT#define ka0602$l_combo_toy_hrs ka0602$r_combo_toy_hrs_overlay.ka0602$l_combo_toy_hrsW#define ka0602$l_combo_toy_ahrs ka0602$r_combo_toy_ahrs_overlay.ka0602$l_combo_toy_ahrsT#define ka0602$l_combo_toy_day ka0602$r_combo_toy_day_overlay.ka0602$l_combo_toy_dayW#define ka0602$l_combo_toy_mnth ka0602$r_combo_toy_mnth_overlay.ka0602$l_combo_toy_mnthW#define ka0602$l_combo-_toy_year ka0602$r_combo_toy_year_overlay.ka0602$l_combo_toy_yearW#define ka0602$l_combo_toy_rtca ka0602$r_combo_toy_rtca_overlay.ka0602$l_combo_toy_rtca|#define ka0602$v_combo_toy_rtca_rs0 ka0602$r_combo_toy_rtca_overlay.ka0602$r_combo_toy_rtca_bits.ka0602$v_combo_toy_rtca_rs0|#define ka0602$v_combo_toy_rtca_rs1 ka0602$r_combo_toy_rtca_overlay.ka0602$r_combo_toy_rtca_bits.ka0602$v_combo_toy_rtca_rs1|#define ka0602$v_combo_toy_rtca_rs2 ka0602$r_combo_toy_rtca_overlay.ka0602$r_combo_toy_rtca_bits-.ka0602$v_combo_toy_rtca_rs2|#define ka0602$v_combo_toy_rtca_rs3 ka0602$r_combo_toy_rtca_overlay.ka0602$r_combo_toy_rtca_bits.ka0602$v_combo_toy_rtca_rs3|#define ka0602$v_combo_toy_rtca_dv0 ka0602$r_combo_toy_rtca_overlay.ka0602$r_combo_toy_rtca_bits.ka0602$v_combo_toy_rtca_dv0|#define ka0602$v_combo_toy_rtca_dv1 ka0602$r_combo_toy_rtca_overlay.ka0602$r_combo_toy_rtca_bits.ka0602$v_combo_toy_rtca_dv1|#define ka0602$v_combo_toy_rtca_dv2 ka0602$r_combo_toy_rtca_overlay.ka0602$r_combo_toy_rtca_bits.k-a0602$v_combo_toy_rtca_dv2|#define ka0602$v_combo_toy_rtca_uip ka0602$r_combo_toy_rtca_overlay.ka0602$r_combo_toy_rtca_bits.ka0602$v_combo_toy_rtca_uipW#define ka0602$l_combo_toy_rtcb ka0602$r_combo_toy_rtcb_overlay.ka0602$l_combo_toy_rtcb|#define ka0602$v_combo_toy_rtcb_dse ka0602$r_combo_toy_rtcb_overlay.ka0602$r_combo_toy_rtcb_bits.ka0602$v_combo_toy_rtcb_dse~#define ka0602$v_combo_toy_rtcb_2412 ka0602$r_combo_toy_rtcb_overlay.ka0602$r_combo_toy_rtcb_bits.ka0602$v_combo_toy_rtcb_2412z#define -ka0602$v_combo_toy_rtcb_dm ka0602$r_combo_toy_rtcb_overlay.ka0602$r_combo_toy_rtcb_bits.ka0602$v_combo_toy_rtcb_dm|#define ka0602$v_combo_toy_rtcb_uie ka0602$r_combo_toy_rtcb_overlay.ka0602$r_combo_toy_rtcb_bits.ka0602$v_combo_toy_rtcb_uie|#define ka0602$v_combo_toy_rtcb_aie ka0602$r_combo_toy_rtcb_overlay.ka0602$r_combo_toy_rtcb_bits.ka0602$v_combo_toy_rtcb_aie|#define ka0602$v_combo_toy_rtcb_pie ka0602$r_combo_toy_rtcb_overlay.ka0602$r_combo_toy_rtcb_bits.ka0602$v_combo_toy_rtcb_pie|#define ka06-02$v_combo_toy_rtcb_set ka0602$r_combo_toy_rtcb_overlay.ka0602$r_combo_toy_rtcb_bits.ka0602$v_combo_toy_rtcb_setW#define ka0602$l_combo_toy_rtcc ka0602$r_combo_toy_rtcc_overlay.ka0602$l_combo_toy_rtccz#define ka0602$v_combo_toy_rtcc_uf ka0602$r_combo_toy_rtcc_overlay.ka0602$r_combo_toy_rtcc_bits.ka0602$v_combo_toy_rtcc_ufz#define ka0602$v_combo_toy_rtcc_af ka0602$r_combo_toy_rtcc_overlay.ka0602$r_combo_toy_rtcc_bits.ka0602$v_combo_toy_rtcc_afz#define ka0602$v_combo_toy_rtcc_pf ka0602$r_combo_toy_-rtcc_overlay.ka0602$r_combo_toy_rtcc_bits.ka0602$v_combo_toy_rtcc_pf~#define ka0602$v_combo_toy_rtcc_irqf ka0602$r_combo_toy_rtcc_overlay.ka0602$r_combo_toy_rtcc_bits.ka0602$v_combo_toy_rtcc_irqfW#define ka0602$l_combo_toy_rtcd ka0602$r_combo_toy_rtcd_overlay.ka0602$l_combo_toy_rtcd|#define ka0602$v_combo_toy_rtcd_vrt ka0602$r_combo_toy_rtcd_overlay.ka0602$r_combo_toy_rtcd_bits.ka0602$v_combo_toy_rtcd_vrt6#define ka0602$l_hae ka0602$r_hae_overlay.ka0602$l_hae\#define ka0602$v_hae_eisa_addr ka060-2$r_hae_overlay.ka0602$r_hae_bits.ka0602$v_hae_eisa_addr?#define ka0602$l_sysctl ka0602$r_sysctl_overlay.ka0602$l_sysctl^#define ka0602$v_sysctl_leds ka0602$r_sysctl_overlay.ka0602$r_sysctl_bits.ka0602$v_sysctl_leds\#define ka0602$v_sysctl_ior ka0602$r_sysctl_overlay.ka0602$r_sysctl_bits.ka0602$v_sysctl_iorb#define ka0602$v_sysctl_errenb ka0602$r_sysctl_overlay.ka0602$r_sysctl_bits.ka0602$v_sysctl_errenb`#define ka0602$v_sysctl_mcnfg ka0602$r_sysctl_overlay.ka0602$r_sysctl_bits.ka0602$v_sysctl_m-cnfgN#define ka0602$b_dma1_ch0_ca ka0602$r_dma1_ch0_ca_overlay.ka0602$b_dma1_ch0_caH#define ka0602$b_int1_ocw2 ka0602$r_int1_ocw2_overlay.ka0602$b_int1_ocw2h#define ka0602$v_int1_ocw2_irq ka0602$r_int1_ocw2_overlay.ka0602$r_int1_ocw2_bits.ka0602$v_int1_ocw2_irqh#define ka0602$v_int1_ocw2_sel ka0602$r_int1_ocw2_overlay.ka0602$r_int1_ocw2_bits.ka0602$v_int1_ocw2_selh#define ka0602$v_int1_ocw2_eoi ka0602$r_int1_ocw2_overlay.ka0602$r_int1_ocw2_bits.ka0602$v_int1_ocw2_eoif#define ka0602$v_int1_ocw2_s-l ka0602$r_int1_ocw2_overlay.ka0602$r_int1_ocw2_bits.ka0602$v_int1_ocw2_slh#define ka0602$v_int1_ocw2_rot ka0602$r_int1_ocw2_overlay.ka0602$r_int1_ocw2_bits.ka0602$v_int1_ocw2_roth#define ka0602$v_int1_ocw3_ris ka0602$r_int1_ocw2_overlay.ka0602$r_int1_ocw3_bits.ka0602$v_int1_ocw3_risf#define ka0602$v_int1_ocw3_rr ka0602$r_int1_ocw2_overlay.ka0602$r_int1_ocw3_bits.ka0602$v_int1_ocw3_rrd#define ka0602$v_int1_ocw3_p ka0602$r_int1_ocw2_overlay.ka0602$r_int1_ocw3_bits.ka0602$v_int1_ocw3_ph#define ka06-02$v_int1_ocw3_sel ka0602$r_int1_ocw2_overlay.ka0602$r_int1_ocw3_bits.ka0602$v_int1_ocw3_selh#define ka0602$v_int1_ocw3_smm ka0602$r_int1_ocw2_overlay.ka0602$r_int1_ocw3_bits.ka0602$v_int1_ocw3_smmj#define ka0602$v_int1_ocw3_esmm ka0602$r_int1_ocw2_overlay.ka0602$r_int1_ocw3_bits.ka0602$v_int1_ocw3_esmmH#define ka0602$b_int1_ocw1 ka0602$r_int1_ocw1_overlay.ka0602$b_int1_ocw1f#define ka0602$v_int1_ocw1_m0 ka0602$r_int1_ocw1_overlay.ka0602$r_int1_ocw1_bits.ka0602$v_int1_ocw1_m0f#define ka0602$v_int-1_ocw1_m1 ka0602$r_int1_ocw1_overlay.ka0602$r_int1_ocw1_bits.ka0602$v_int1_ocw1_m1f#define ka0602$v_int1_ocw1_m2 ka0602$r_int1_ocw1_overlay.ka0602$r_int1_ocw1_bits.ka0602$v_int1_ocw1_m2f#define ka0602$v_int1_ocw1_m3 ka0602$r_int1_ocw1_overlay.ka0602$r_int1_ocw1_bits.ka0602$v_int1_ocw1_m3f#define ka0602$v_int1_ocw1_m4 ka0602$r_int1_ocw1_overlay.ka0602$r_int1_ocw1_bits.ka0602$v_int1_ocw1_m4f#define ka0602$v_int1_ocw1_m5 ka0602$r_int1_ocw1_overlay.ka0602$r_int1_ocw1_bits.ka0602$v_int1_ocw1_m5f#defin-e ka0602$v_int1_ocw1_m6 ka0602$r_int1_ocw1_overlay.ka0602$r_int1_ocw1_bits.ka0602$v_int1_ocw1_m6f#define ka0602$v_int1_ocw1_m7 ka0602$r_int1_ocw1_overlay.ka0602$r_int1_ocw1_bits.ka0602$v_int1_ocw1_m7H#define ka0602$b_int2_ocw2 ka0602$r_int2_ocw2_overlay.ka0602$b_int2_ocw2h#define ka0602$v_int2_ocw2_irq ka0602$r_int2_ocw2_overlay.ka0602$r_int2_ocw2_bits.ka0602$v_int2_ocw2_irqh#define ka0602$v_int2_ocw2_sel ka0602$r_int2_ocw2_overlay.ka0602$r_int2_ocw2_bits.ka0602$v_int2_ocw2_selh#define ka0602$v_i-nt2_ocw2_eoi ka0602$r_int2_ocw2_overlay.ka0602$r_int2_ocw2_bits.ka0602$v_int2_ocw2_eoif#define ka0602$v_int2_ocw2_sl ka0602$r_int2_ocw2_overlay.ka0602$r_int2_ocw2_bits.ka0602$v_int2_ocw2_slh#define ka0602$v_int2_ocw2_rot ka0602$r_int2_ocw2_overlay.ka0602$r_int2_ocw2_bits.ka0602$v_int2_ocw2_roth#define ka0602$v_int2_ocw3_ris ka0602$r_int2_ocw2_overlay.ka0602$r_int2_ocw3_bits.ka0602$v_int2_ocw3_risf#define ka0602$v_int2_ocw3_rr ka0602$r_int2_ocw2_overlay.ka0602$r_int2_ocw3_bits.ka0602$v_int2_ocw3_rr-d#define ka0602$v_int2_ocw3_p ka0602$r_int2_ocw2_overlay.ka0602$r_int2_ocw3_bits.ka0602$v_int2_ocw3_ph#define ka0602$v_int2_ocw3_sel ka0602$r_int2_ocw2_overlay.ka0602$r_int2_ocw3_bits.ka0602$v_int2_ocw3_selh#define ka0602$v_int2_ocw3_smm ka0602$r_int2_ocw2_overlay.ka0602$r_int2_ocw3_bits.ka0602$v_int2_ocw3_smmj#define ka0602$v_int2_ocw3_esmm ka0602$r_int2_ocw2_overlay.ka0602$r_int2_ocw3_bits.ka0602$v_int2_ocw3_esmmH#define ka0602$b_int2_ocw1 ka0602$r_int2_ocw1_overlay.ka0602$b_int2_ocw1f#define -ka0602$v_int2_ocw1_m0 ka0602$r_int2_ocw1_overlay.ka0602$r_int2_ocw1_bits.ka0602$v_int2_ocw1_m0f#define ka0602$v_int2_ocw1_m1 ka0602$r_int2_ocw1_overlay.ka0602$r_int2_ocw1_bits.ka0602$v_int2_ocw1_m1f#define ka0602$v_int2_ocw1_m2 ka0602$r_int2_ocw1_overlay.ka0602$r_int2_ocw1_bits.ka0602$v_int2_ocw1_m2f#define ka0602$v_int2_ocw1_m3 ka0602$r_int2_ocw1_overlay.ka0602$r_int2_ocw1_bits.ka0602$v_int2_ocw1_m3f#define ka0602$v_int2_ocw1_m4 ka0602$r_int2_ocw1_overlay.ka0602$r_int2_ocw1_bits.ka0602$v_int2_ocw -1_m4f#define ka0602$v_int2_ocw1_m5 ka0602$r_int2_ocw1_overlay.ka0602$r_int2_ocw1_bits.ka0602$v_int2_ocw1_m5f#define ka0602$v_int2_ocw1_m6 ka0602$r_int2_ocw1_overlay.ka0602$r_int2_ocw1_bits.ka0602$v_int2_ocw1_m6f#define ka0602$v_int2_ocw1_m7 ka0602$r_int2_ocw1_overlay.ka0602$r_int2_ocw1_bits.ka0602$v_int2_ocw1_m7"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_poi-nter_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KA0602DEF_LOADED */ wwba[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP-, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** -authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************************************* -*******************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */I/* Source: 24-MAR-1993 14:47:16 $1$DGA8345:[LIB_H.SRC]KA0702DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KA0702DEF ***/#ifndef __KA0702DEF_LOADED#define __KA0702DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __-nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !d-efined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define KA0702$M_IR_SFB_INT 0x4 #define KA0702$M_IR_SCSI_INT 0x8##define KA0702$M_IR_COREIO_INT 0x10$#define KA0702$M_IR_BC_TPE 0x8000000%#define KA0702$M_IR_TC_ORE 0x10000000%#define KA0702$M_IR_TC_TOE 0x20000000"#define KA0702$M_IR_BPE 0x40000000"#define KA0702$M_I-R_MPE 0x80000000#define KA0702$M_TCSR_AP0 0x1#define KA0702$M_TCSR_AP1 0x2#define KA0702$M_TCSR_AP2 0x4#define KA0702$M_TCSR_AP3 0x8#define KA0702$M_TCSR_AP4 0x10!#define KA0702$M_MCR_SP0_SIZE 0x1!#define KA0702$M_MCR_SP1_SIZE 0x2!#define KA0702$M_MCR_SP2_SIZE 0x4!#define KA0702$M_MCR_SP3_SIZE 0x8&#define KA0702$M_LDP_DMA_PA_LO 0xFFFE0)#define KA0702$M_LDP_DMA_PA_HI 0xFFF00000+#define KA0702$M_SCOMM_TR_DMA_PA 0xFFFFFFE0+#define KA0702$M_SCOMM_RC_DMA_PA 0xFFFFFFE0-#define -KA0702$M_PRINTER_TR_DMA_PA 0xFFFFFFE0-#define KA0702$M_PRINTER_RC_DMA_PA 0xFFFFFFE0*#define KA0702$M_ISDN_TR_DMA_PA 0xFFFFFFE0.#define KA0702$M_ISDN_TR_BUF_DMA_PA 0xFFFFFFE0*#define KA0702$M_ISDN_RC_DMA_PA 0xFFFFFFE0.#define KA0702$M_ISDN_RC_BUF_DMA_PA 0xFFFFFFE0 #define KA0702$M_SSR_IO_MASK 0xF$#define KA0702$M_SSR_IO_MASK_EN 0x10#define KA0702$M_SSR_FPE 0x80&#define KA0702$M_SSR_LANCE_RESET 0x100$#define KA0702$M_SSR_RTC_RESET 0x400$#define KA0702$M_SSR_SCC_RESET 0x800&#define KA0702 -$M_SSR_ISDN_RESET 0x1000!#define KA0702$M_SSR_TXDIS 0x8000)#define KA0702$M_SSR_LANCE_DMA_EN 0x10000(#define KA0702$M_SSR_ISDN_RCV_EN 0x80000(#define KA0702$M_SSR_ISDN_TR_EN 0x100000##define KA0702$M_SSR_SMR0 0x1000000##define KA0702$M_SSR_SMR1 0x2000000##define KA0702$M_SSR_SMRA 0x4000000(#define KA0702$M_SSR_FAST_MODE 0x8000000-#define KA0702$M_SSR_KBD_RC_DMA_EN 0x10000000-#define KA0702$M_SSR_KBD_TR_DMA_EN 0x20000000.#define KA0702$M_SSR_COMM_RC_DMA_EN 0x40000000.#define KA0702$M-_SSR_COMM_TR_DMA_EN 0x80000000#define KA0702$M_SIR_HALT0 0x1#define KA0702$M_SIR_HALT1 0x2!#define KA0702$M_SIR_TC_SLOT0 0x4!#define KA0702$M_SIR_TC_SLOT1 0x8"#define KA0702$M_SIR_SCC0_INT 0x40"#define KA0702$M_SIR_SCC1_INT 0x80$#define KA0702$M_SIR_LANCE_INT 0x100$#define KA0702$M_SIR_ISDN_INT 0x2000$#define KA0702$M_SIR_CONS_SEL 0x8000)#define KA0702$M_SIR_LANCE_DMA_ER 0x10000*#define KA0702$M_SIR_ISDN_DMA_MRE 0x100000.#define KA0702$M_SIR_ISDN_DMA_RC_INTR 0x200000.#define KA0702$M -_SIR_ISDN_DMA_TR_INTR 0x400000*#define KA0702$M_SIR_SCC1_DMA_OV 0x1000000+#define KA0702$M_SIR_SCC1_RCV_INT 0x2000000-#define KA0702$M_SIR_SCC1_TR_DMA_ME 0x4000000*#define KA0702$M_SIR_SCC1_TR_INT 0x8000000+#define KA0702$M_SIR_SCC0_DMA_OV 0x10000000,#define KA0702$M_SIR_SCC0_RCV_INT 0x20000000.#define KA0702$M_SIR_SCC0_TR_DMA_ME 0x40000000+#define KA0702$M_SIR_SCC0_TR_INT 0x80000000#define KA0702$M_SIMR_HALT0 0x1#define KA0702$M_SIMR_HALT1 0x2"#define KA0702$M_SIMR_TC_SLOT0 0x4"#d -efine KA0702$M_SIMR_TC_SLOT1 0x8##define KA0702$M_SIMR_SCC0_INT 0x40##define KA0702$M_SIMR_SCC1_INT 0x80%#define KA0702$M_SIMR_LANCE_INT 0x100%#define KA0702$M_SIMR_ISDN_INT 0x2000%#define KA0702$M_SIMR_CONS_SEL 0x8000*#define KA0702$M_SIMR_LANCE_DMA_ER 0x10000+#define KA0702$M_SIMR_ISDN_DMA_MRE 0x100000/#define KA0702$M_SIMR_ISDN_DMA_RC_INTR 0x200000/#define KA0702$M_SIMR_ISDN_DMA_TR_INTR 0x400000+#define KA0702$M_SIMR_SCC1_DMA_OV 0x1000000,#define KA0702$M_SIMR_SCC1_RCV_INT 0x200 -0000.#define KA0702$M_SIMR_SCC1_TR_DMA_ME 0x4000000+#define KA0702$M_SIMR_SCC1_TR_INT 0x8000000,#define KA0702$M_SIMR_SCC0_DMA_OV 0x10000000-#define KA0702$M_SIMR_SCC0_RCV_INT 0x20000000/#define KA0702$M_SIMR_SCC0_TR_DMA_ME 0x40000000,#define KA0702$M_SIMR_SCC0_TR_INT 0x80000000'#define KA0702$M_SADR_TC_ADDR 0x1FFFFE0+#define KA0702$M_ISDN_DATA_TR_DATA 0xFFFFFF+#define KA0702$M_ISDN_DATA_RC_DATA 0xFFFFFF"#define KA0702$M_LANCE_SLOT_CS 0xF)#define KA0702$M_LANCE_SLOT_HW_ADDR 0x3F0!#d-efine KA0702$M_SCC0_SLOT_CS 0xF(#define KA0702$M_SCC0_SLOT_HW_ADDR 0x3F0!#define KA0702$M_SCC1_SLOT_CS 0xF(#define KA0702$M_SCC1_SLOT_HW_ADDR 0x3F0#define KA0702$M_MODE_FIELD 0x7#define KA0702$M_BOOLOP_OP 0xF%#define KA0702$M_PIXELSHIFT_COUNT 0xF(#define KA0702$M_ADDR_REG_VALUE 0xFFFFFF!#define KA0702$M_BRES1_EI1 0xFFFF%#define KA0702$M_BRES1_AI1 0xFFFF0000!#define KA0702$M_BRES2_EI2 0xFFFF%#define KA0702$M_BRES2_AI2 0xFFFF0000#define KA0702$M_BRES3_LL 0xF%#define KA0702$M_BRE-S3_IEV 0xFFFF8000#define KA0702$M_DEEP_PLANE 0x3%#define KA0702$M_V_REF_COUNT_VC 0x3FF##define KA0702$M_V_HOR_PIXELS 0x1FF #define KA0702$M_V_HOR_FP 0x3E00%#define KA0702$M_V_HOR_SYNCH 0x1FC000##define KA0702$M_V_HOR_BP 0xFE00000#define KA0702$M_V_VER_SL 0x7FF #define KA0702$M_V_VER_FP 0xF800%#define KA0702$M_V_VER_SYNCH 0x3F0000##define KA0702$M_V_VER_BP 0xFC00000&#define KA0702$M_V_BASE_ADDR_ROW 0x1FF*#define KA0702$M_RAMDAC_ADDR_LO_BYTE0 0xFF*#define KA0702$M_RAMDAC_ADDR_HI_ -BYTE0 0xFF+#define KA0702$M_RAMDAC_REG_ADDR_BYTE0 0xFF*#define KA0702$M_RAMDAC_MAP_LOC_BYTE0 0xFFX#define KA0702$S_KA0702DEF 2179072 /* Old size name, synonym for KA0702$S_KA0702 */ typedef struct _ka0702 { __union {N unsigned int ka0702$l_ir; /* Interrupt register */ __struct {+ unsigned ka0702$v_ir_fill1 : 2;- unsigned ka0702$v_ir_sfb_int : 1;. unsigned ka0702$v_ir_scsi_int : 1;0 unsigned ka0 -702$v_ir_coreio_int : 1;, unsigned ka0702$v_ir_fill2 : 22;, unsigned ka0702$v_ir_bc_tpe : 1;, unsigned ka0702$v_ir_tc_ore : 1;, unsigned ka0702$v_ir_tc_toe : 1;) unsigned ka0702$v_ir_bpe : 1;) unsigned ka0702$v_ir_mpe : 1; } ka0702$r_ir_bits; } ka0702$r_ir_overlay;Y unsigned char ka0702$b_fill510 [12]; /* fill to next sparse space addr offset = 10 */ __union {N unsigned int ka0702$l_tcsr -; /* TC status and control register */ __struct {+ unsigned ka0702$v_tcsr_ap0 : 1;+ unsigned ka0702$v_tcsr_ap1 : 1;+ unsigned ka0702$v_tcsr_ap2 : 1;+ unsigned ka0702$v_tcsr_ap3 : 1;+ unsigned ka0702$v_tcsr_ap4 : 1;- unsigned ka0702$v_tcsr_fill : 27;! } ka0702$r_tcsr_bits; } ka0702$r_tcsr_overlay;Y unsigned char ka0702$b_fill511 [12]; /* fill to next sparse space addr offset = 20 */ - __union {N unsigned int ka0702$l_mcr; /* Memory Configuration Register */ __struct {N unsigned ka0702$v_mcr_sp0_size : 1; /* SIMM PAIR0 Size */N unsigned ka0702$v_mcr_sp1_size : 1; /* SIMM PAIR1 Size */N unsigned ka0702$v_mcr_sp2_size : 1; /* SIMM PAIR2 Size */N unsigned ka0702$v_mcr_sp3_size : 1; /* SIMM PAIR3 Size */* unsigned ka0702$v_fill_0_ : 4; } ka0702$r -_mcr_bits; } ka0702$r_mcr_overlay;* unsigned char ka0702$b_fill520 [8156];N unsigned int ka0702$l_ioctl_csr; /* Core I/O base CSR address */( unsigned char ka0702$b_fill560 [60]; __union {N unsigned int ka0702$l_ldp; /* Ethernet Lance DMA pointer */ __struct {, unsigned ka0702$v_ldp_fill1 : 5;1 unsigned ka0702$v_ldp_dma_pa_lo : 15;1 unsigned ka0702$v_ldp_dma_pa_hi : 12; } ka0702$r_ldp -_bits; } ka0702$r_ldp_overlay;( unsigned char ka0702$b_fill570 [28]; __union {U unsigned int ka0702$l_scomm_tr; /* Serial comm transmit port 1 DMA pointer */ __struct {1 unsigned ka0702$v_scomm_tr_fill1 : 5;3 unsigned ka0702$v_scomm_tr_dma_pa : 27;% } ka0702$r_scomm_tr_bits;$ } ka0702$r_scomm_tr_overlay;( unsigned char ka0702$b_fill580 [28]; __union {T unsigned int ka0702$l_scomm_rc; /* Serial comm - receive port 1 DMA pointer */ __struct {1 unsigned ka0702$v_scomm_rc_fill1 : 5;3 unsigned ka0702$v_scomm_rc_dma_pa : 27;% } ka0702$r_scomm_rc_bits;$ } ka0702$r_scomm_rc_overlay;( unsigned char ka0702$b_fill590 [28]; __union {Q unsigned int ka0702$l_printer_tr; /* Printer transmit port DMA pointer */ __struct {3 unsigned ka0702$v_printer_tr_fill1 : 5;5 unsigned ka0702$v_printer_tr_dma_pa : -27;' } ka0702$r_printer_tr_bits;& } ka0702$r_printer_tr_overlay;( unsigned char ka0702$b_fill600 [28]; __union {P unsigned int ka0702$l_printer_rc; /* Printer receive port DMA pointer */ __struct {3 unsigned ka0702$v_printer_rc_fill1 : 5;5 unsigned ka0702$v_printer_rc_dma_pa : 27;' } ka0702$r_printer_rc_bits;& } ka0702$r_printer_rc_overlay;( unsigned char ka0702$b_fill610 [60]; __union {N - unsigned int ka0702$l_isdn_tr; /* ISDN transmit DMA pointer */ __struct {0 unsigned ka0702$v_isdn_tr_fill1 : 5;2 unsigned ka0702$v_isdn_tr_dma_pa : 27;$ } ka0702$r_isdn_tr_bits;# } ka0702$r_isdn_tr_overlay;( unsigned char ka0702$b_fill620 [28]; __union {Q unsigned int ka0702$l_isdn_tr_buf; /* ISDN transmit DMA buffer pointer */ __struct {4 unsigned ka0702$v_isdn_tr_buf_fill1 : 5;6 un -signed ka0702$v_isdn_tr_buf_dma_pa : 27;( } ka0702$r_isdn_tr_buf_bits;' } ka0702$r_isdn_tr_buf_overlay;( unsigned char ka0702$b_fill630 [28]; __union {N unsigned int ka0702$l_isdn_rc; /* ISDN receive DMA pointer */ __struct {0 unsigned ka0702$v_isdn_rc_fill1 : 5;2 unsigned ka0702$v_isdn_rc_dma_pa : 27;$ } ka0702$r_isdn_rc_bits;# } ka0702$r_isdn_rc_overlay;( unsigned char ka0702$b_fill640 [28]; - __union {Q unsigned int ka0702$l_isdn_rc_buf; /* ISDN receive DMA buffer pointer */ __struct {4 unsigned ka0702$v_isdn_rc_buf_fill1 : 5;6 unsigned ka0702$v_isdn_rc_buf_dma_pa : 27;( } ka0702$r_isdn_rc_buf_bits;' } ka0702$r_isdn_rc_buf_overlay;( unsigned char ka0702$b_fill650 [28];N unsigned int ka0702$l_data0; /* System Data Buffer 0 */( unsigned char ka0702$b_fill660 [28];N unsigned int ka0702$l_ -data1; /* System Data Buffer 1 */( unsigned char ka0702$b_fill670 [28];N unsigned int ka0702$l_data2; /* System Data Buffer 2 */( unsigned char ka0702$b_fill680 [28];N unsigned int ka0702$l_data3; /* System Data Buffer 3 */( unsigned char ka0702$b_fill690 [28]; __union {N unsigned int ka0702$l_ssr; /* System support register */ __struct {. unsigned ka0702$v_ssr_io_mask : 4;1 - unsigned ka0702$v_ssr_io_mask_en : 1;1 unsigned ka0702$v_ssr_sys_ok_led : 1;, unsigned ka0702$v_ssr_fill1 : 1;* unsigned ka0702$v_ssr_fpe : 1;2 unsigned ka0702$v_ssr_lance_reset : 1;, unsigned ka0702$v_ssr_fill2 : 1;0 unsigned ka0702$v_ssr_rtc_reset : 1;0 unsigned ka0702$v_ssr_scc_reset : 1;1 unsigned ka0702$v_ssr_isdn_reset : 1;, unsigned ka0702$v_ssr_fill3 : 2;, unsi -gned ka0702$v_ssr_txdis : 1;3 unsigned ka0702$v_ssr_lance_dma_en : 1;, unsigned ka0702$v_ssr_fill4 : 2;2 unsigned ka0702$v_ssr_isdn_rcv_en : 1;1 unsigned ka0702$v_ssr_isdn_tr_en : 1;, unsigned ka0702$v_ssr_fill5 : 3;+ unsigned ka0702$v_ssr_smr0 : 1;+ unsigned ka0702$v_ssr_smr1 : 1;+ unsigned ka0702$v_ssr_smra : 1;0 unsigned ka0702$v_ssr_fast_mode : 1;4 unsigned ka0702$v_ssr_kbd_ -rc_dma_en : 1;4 unsigned ka0702$v_ssr_kbd_tr_dma_en : 1;5 unsigned ka0702$v_ssr_comm_rc_dma_en : 1;5 unsigned ka0702$v_ssr_comm_tr_dma_en : 1; } ka0702$r_ssr_bits; } ka0702$r_ssr_overlay;( unsigned char ka0702$b_fill700 [28]; __union {N unsigned int ka0702$l_sir; /* System interrupt register */ __struct {, unsigned ka0702$v_sir_halt0 : 1;, unsigned ka0702$v_sir_halt1 : 1;/ - unsigned ka0702$v_sir_tc_slot0 : 1;/ unsigned ka0702$v_sir_tc_slot1 : 1;, unsigned ka0702$v_sir_fill1 : 2;/ unsigned ka0702$v_sir_scc0_int : 1;/ unsigned ka0702$v_sir_scc1_int : 1;0 unsigned ka0702$v_sir_lance_int : 1;, unsigned ka0702$v_sir_fill2 : 4;/ unsigned ka0702$v_sir_isdn_int : 1;, unsigned ka0702$v_sir_fill3 : 1;/ unsigned ka0702$v_sir_cons_sel : 1;3 unsigned k -a0702$v_sir_lance_dma_er : 1;, unsigned ka0702$v_sir_fill4 : 3;3 unsigned ka0702$v_sir_isdn_dma_mre : 1;7 unsigned ka0702$v_sir_isdn_dma_rc_intr : 1;7 unsigned ka0702$v_sir_isdn_dma_tr_intr : 1;, unsigned ka0702$v_sir_fill6 : 1;2 unsigned ka0702$v_sir_scc1_dma_ov : 1;3 unsigned ka0702$v_sir_scc1_rcv_int : 1;5 unsigned ka0702$v_sir_scc1_tr_dma_me : 1;2 unsigned ka0702$v_sir_scc1_tr_int : 1; -2 unsigned ka0702$v_sir_scc0_dma_ov : 1;3 unsigned ka0702$v_sir_scc0_rcv_int : 1;5 unsigned ka0702$v_sir_scc0_tr_dma_me : 1;2 unsigned ka0702$v_sir_scc0_tr_int : 1; } ka0702$r_sir_bits; } ka0702$r_sir_overlay;( unsigned char ka0702$b_fill710 [28]; __union {N unsigned int ka0702$l_simr; /* System interrupt mask register */ __struct {- unsigned ka0702$v_simr_halt0 : 1;- un -signed ka0702$v_simr_halt1 : 1;0 unsigned ka0702$v_simr_tc_slot0 : 1;0 unsigned ka0702$v_simr_tc_slot1 : 1;- unsigned ka0702$v_simr_fill1 : 2;0 unsigned ka0702$v_simr_scc0_int : 1;0 unsigned ka0702$v_simr_scc1_int : 1;1 unsigned ka0702$v_simr_lance_int : 1;- unsigned ka0702$v_simr_fill2 : 4;0 unsigned ka0702$v_simr_isdn_int : 1;- unsigned ka0702$v_simr_fill3 : 1;0 unsigned ka070 -2$v_simr_cons_sel : 1;4 unsigned ka0702$v_simr_lance_dma_er : 1;- unsigned ka0702$v_simr_fill4 : 3;4 unsigned ka0702$v_simr_isdn_dma_mre : 1;8 unsigned ka0702$v_simr_isdn_dma_rc_intr : 1;8 unsigned ka0702$v_simr_isdn_dma_tr_intr : 1;- unsigned ka0702$v_simr_fill6 : 1;3 unsigned ka0702$v_simr_scc1_dma_ov : 1;4 unsigned ka0702$v_simr_scc1_rcv_int : 1;6 unsigned ka0702$v_simr_scc1_tr_dma_me : 1; -3 unsigned ka0702$v_simr_scc1_tr_int : 1;3 unsigned ka0702$v_simr_scc0_dma_ov : 1;4 unsigned ka0702$v_simr_scc0_rcv_int : 1;6 unsigned ka0702$v_simr_scc0_tr_dma_me : 1;3 unsigned ka0702$v_simr_scc0_tr_int : 1;! } ka0702$r_simr_bits; } ka0702$r_simr_overlay;( unsigned char ka0702$b_fill720 [28]; __union {N unsigned int ka0702$l_sadr; /* System address register */ __struct {- - unsigned ka0702$v_sadr_fill1 : 5;0 unsigned ka0702$v_sadr_tc_addr : 20;- unsigned ka0702$v_sadr_fill2 : 7;! } ka0702$r_sadr_bits; } ka0702$r_sadr_overlay;( unsigned char ka0702$b_fill730 [28]; __union {N unsigned int ka0702$l_isdn_data_tr; /* ISDN Data Transmit */ __struct {5 unsigned ka0702$v_isdn_data_tr_data : 24;4 unsigned ka0702$v_isdn_data_tr_fill : 8;) } ka0702$r -_isdn_data_tr_bits;( } ka0702$r_isdn_data_tr_overlay;( unsigned char ka0702$b_fill740 [28]; __union {N unsigned int ka0702$l_isdn_data_rc; /* ISDN Data Receive */ __struct {5 unsigned ka0702$v_isdn_data_rc_data : 24;4 unsigned ka0702$v_isdn_data_rc_fill : 8;) } ka0702$r_isdn_data_rc_bits;( } ka0702$r_isdn_data_rc_overlay;( unsigned char ka0702$b_fill750 [28]; __union {N unsigned int ka0702$ -l_lance_slot; /* Lance slot register */ __struct {0 unsigned ka0702$v_lance_slot_cs : 4;5 unsigned ka0702$v_lance_slot_hw_addr : 6;3 unsigned ka0702$v_lance_slot_fill : 22;' } ka0702$r_lance_slot_bits;& } ka0702$r_lance_slot_overlay;( unsigned char ka0702$b_fill760 [60]; __union {N unsigned int ka0702$l_scc0_slot; /* SCC0 slot register */ __struct {/ unsigned ka0702$v_ -scc0_slot_cs : 4;4 unsigned ka0702$v_scc0_slot_hw_addr : 6;2 unsigned ka0702$v_scc0_slot_fill : 22;& } ka0702$r_scc0_slot_bits;% } ka0702$r_scc0_slot_overlay;( unsigned char ka0702$b_fill770 [28]; __union {N unsigned int ka0702$l_scc1_slot; /* SCC1 slot register */ __struct {/ unsigned ka0702$v_scc1_slot_cs : 4;4 unsigned ka0702$v_scc1_slot_hw_addr : 6;2 unsigned ka0702$v_scc1_s -lot_fill : 22;& } ka0702$r_scc1_slot_bits;% } ka0702$r_scc1_slot_overlay;* unsigned char ka0702$b_fill780 [7388];N unsigned int ka0702$l_ni_adr_rom; /* Ethernet address ROM */* unsigned char ka0702$b_fill790 [8188];N unsigned int ka0702$l_lance_rdp; /* Lance ethernet CSR */R unsigned char ka0702$b_fill800 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_lance_rap; /* Lance ethernet CSR */-* unsigned char ka0702$b_fill810 [8180];N unsigned int ka0702$l_scc0b_comm_rap; /* Comm Port 1 RAP */R unsigned char ka0702$b_fill820 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_scc0b_comm_data; /* Comm Port 1 data */R unsigned char ka0702$b_fill830 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_scc0a_mouse_rap; /* Mouse RAP */R unsigned char ka0702$b_fill840 [4]; /* Fill to a-llow sparse space byte mask */N unsigned int ka0702$l_scc0a_mouse_data; /* Mouse port data register */* unsigned char ka0702$b_fill850 [8164];N unsigned int ka0702$l_scc1b_print_rap; /* Printer Port 2 RAP */R unsigned char ka0702$b_fill860 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_scc1b_print_data; /* Printer Port 2 data */R unsigned char ka0702$b_fill870 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka070-2$l_scc1a_key_rap; /* Keyboard RAP */R unsigned char ka0702$b_fill880 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_scc1a_key_data; /* Keyboard port data register */* unsigned char ka0702$b_fill890 [8164];N unsigned int ka0702$l_rtc_sec; /* TOY clock CSR--seconds */R unsigned char ka0702$b_fill900 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_alms; /* TOY clock CSR--seconds alarm -*/R unsigned char ka0702$b_fill910 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_min; /* TOY clock CSR--minutes */R unsigned char ka0702$b_fill920 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_almn; /* TOY clock CSR--minutes alarm */R unsigned char ka0702$b_fill930 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_hour; /* TOY clock CSR--hours */R unsign-ed char ka0702$b_fill940 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_almh; /* TOY clock CSR--hours alarm */R unsigned char ka0702$b_fill950 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_dow; /* TOY clock CSR--day of week */R unsigned char ka0702$b_fill960 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_day; /* TOY clock CSR--date of month */R unsigned char ka0702-$b_fill970 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_mon; /* TOY clock CSR--month */R unsigned char ka0702$b_fill980 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_year; /* TOY clock CSR--year */R unsigned char ka0702$b_fill990 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_rega; /* TOY clock CSR--register A */S unsigned char ka0702$b_fill1000 [4-]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_regb; /* TOY clock CSR--register B */S unsigned char ka0702$b_fill1010 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_regc; /* TOY clock CSR--register C */S unsigned char ka0702$b_fill1020 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_rtc_regd; /* TOY clock CSR--register D */S unsigned char ka0702$b_fill1030 [4]; /* Fi-ll to allow sparse space byte mask */N unsigned int ka0702$l_rtc_ram; /* TOY clock CSR--base of BBU RAM */N unsigned char ka0702$b_fill1035 [260]; /* Fill to SCSI Host ID location */N unsigned int ka0702$l_scsi_host_id; /* SCSI Host ID */+ unsigned char ka0702$b_fill1040 [7812];N unsigned int ka0702$l_isdn_audio; /* ISDN audio chip CSR */+ unsigned char ka0702$b_fill1050 [8188];N unsigned int ka0702$l_cpybuf0; /* Copy Buffer- register */S unsigned char ka0702$b_fill1070 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_cpybuf1; /* Copy Buffer register */S unsigned char ka0702$b_fill1080 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_cpybuf2; /* Copy Buffer register */S unsigned char ka0702$b_fill1090 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_cpybuf3; /* Copy Buffer registe-r */S unsigned char ka0702$b_fill1110 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_cpybuf4; /* Copy Buffer register */S unsigned char ka0702$b_fill1120 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_cpybuf5; /* Copy Buffer register */S unsigned char ka0702$b_fill1130 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_cpybuf6; /* Copy Buffer register - */S unsigned char ka0702$b_fill1140 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_cpybuf7; /* Copy Buffer register */S unsigned char ka0702$b_fill1150 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_fg; /* Foreground */S unsigned char ka0702$b_fill1160 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_bg; /* Background */-S unsigned char ka0702$b_fill1170 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_planemask; /* Planemask */S unsigned char ka0702$b_fill1180 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_pixelmask; /* Pixel Mask register */S unsigned char ka0702$b_fill1190 [4]; /* Fill to allow sparse space byte mask */ __union {N unsigned int ka0702$l_mode; /* Mode register - */ __struct {- unsigned ka0702$v_mode_field : 3;- unsigned ka0702$v_mode_fill : 29;! } ka0702$r_mode_bits; } ka0702$r_mode_overlay;S unsigned char ka0702$b_fill1200 [4]; /* Fill to allow sparse space byte mask */ __union {N unsigned int ka0702$l_boolop; /* Boolean Op register */ __struct {, unsigned ka0702$v_boolop_op : 4;/ unsigned ka0702$v_boolop_fill : 28;# - } ka0702$r_boolop_bits;" } ka0702$r_boolop_overlay;S unsigned char ka0702$b_fill1210 [4]; /* Fill to allow sparse space byte mask */ __union {N unsigned int ka0702$l_pixelshift; /* Pixel Shift register */ __struct {3 unsigned ka0702$v_pixelshift_count : 4;3 unsigned ka0702$v_pixelshift_fill : 28;' } ka0702$r_pixelshift_bits;& } ka0702$r_pixelshift_overlay;S unsigned char ka0702$b_fill1220 [4]; /* Fi -ll to allow sparse space byte mask */ __union {N unsigned int ka0702$l_addr_reg; /* Address register */ __struct {2 unsigned ka0702$v_addr_reg_value : 24;0 unsigned ka0702$v_addr_reg_fill : 8;% } ka0702$r_addr_reg_bits;$ } ka0702$r_addr_reg_overlay;S unsigned char ka0702$b_fill1230 [4]; /* Fill to allow sparse space byte mask */ __union {N unsigned int ka0702$l_bres1; /* Bresenham register 1 - */ __struct {- unsigned ka0702$v_bres1_ei1 : 16;- unsigned ka0702$v_bres1_ai1 : 16;" } ka0702$r_bres1_bits;! } ka0702$r_bres1_overlay;S unsigned char ka0702$b_fill1240 [4]; /* Fill to allow sparse space byte mask */ __union {N unsigned int ka0702$l_bres2; /* Bresenham register 2 */ __struct {- unsigned ka0702$v_bres2_ei2 : 16;- unsigned ka0702$v_bres2_ai2 : 16;" - } ka0702$r_bres2_bits;! } ka0702$r_bres2_overlay;S unsigned char ka0702$b_fill1250 [4]; /* Fill to allow sparse space byte mask */ __union {N unsigned int ka0702$l_bres3; /* Bresenham register 3 */ __struct {+ unsigned ka0702$v_bres3_ll : 4;/ unsigned ka0702$v_bres3_fill1 : 11;- unsigned ka0702$v_bres3_iev : 17;" } ka0702$r_bres3_bits;! } ka0702$r_bres3_overlay;S unsigned cha -r ka0702$b_fill1260 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_bcont; /* Bresenham continue */S unsigned char ka0702$b_fill1270 [4]; /* Fill to allow sparse space byte mask */ __union {N unsigned int ka0702$l_deep; /* Deep register */ __struct {- unsigned ka0702$v_deep_plane : 2;- unsigned ka0702$v_deep_fill : 30;! } ka0702$r_deep_bits; } ka0702$r_d -eep_overlay;S unsigned char ka0702$b_fill1280 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_start; /* Start register */S unsigned char ka0702$b_fill1290 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_ci; /* Clear interrupt */) unsigned char ka0702$b_fill1300 [12]; __union {N unsigned int ka0702$l_v_ref_count; /* Video refresh count */ __struct { -2 unsigned ka0702$v_v_ref_count_vc : 10;4 unsigned ka0702$v_v_ref_count_fill : 22;( } ka0702$r_v_ref_count_bits;' } ka0702$r_v_ref_count_overlay;S unsigned char ka0702$b_fill1310 [4]; /* Fill to allow sparse space byte mask */ __union {N unsigned int ka0702$l_v_hor; /* Video horizontal setup */ __struct {/ unsigned ka0702$v_v_hor_pixels : 9;+ unsigned ka0702$v_v_hor_fp : 5;. un -signed ka0702$v_v_hor_synch : 7;+ unsigned ka0702$v_v_hor_bp : 7;. unsigned ka0702$v_v_hor_fill1 : 4;" } ka0702$r_v_hor_bits;! } ka0702$r_v_hor_overlay;S unsigned char ka0702$b_fill1320 [4]; /* Fill to allow sparse space byte mask */ __union {N unsigned int ka0702$l_v_ver; /* Video vertical setup */ __struct {, unsigned ka0702$v_v_ver_sl : 11;+ unsigned ka0702$v_v_ver_fp : 5;. - unsigned ka0702$v_v_ver_synch : 6;+ unsigned ka0702$v_v_ver_bp : 6;. unsigned ka0702$v_v_ver_fill1 : 4;" } ka0702$r_v_ver_bits;! } ka0702$r_v_ver_overlay;N unsigned char ka0702$b_fill1325 [4]; /* Fill to allow a longword of */ __union {N unsigned int ka0702$l_v_base_addr; /* Video Base Address */ __struct {2 unsigned ka0702$v_v_base_addr_row : 9;4 unsigned ka0702$v_v_base_addr_fill : 23;-( } ka0702$r_v_base_addr_bits;' } ka0702$r_v_base_addr_overlay;S unsigned char ka0702$b_fill1330 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_vv; /* Video valid */S unsigned char ka0702$b_fill1340 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_ei; /* Enable interrupts */S unsigned char ka0702$b_fill1350 [4]; /* Fill to allow sparse space byte mask */N - unsigned int ka0702$l_tcclk_count; /* TC clk count */S unsigned char ka0702$b_fill1360 [4]; /* Fill to allow sparse space byte mask */N unsigned int ka0702$l_vidclk_count; /* TC clk count */+ unsigned char ka0702$b_fill1370 [7940]; __union {R unsigned int ka0702$l_ramdac_addr_lo; /* RAMDAC color map and registers */ __struct {7 unsigned ka0702$v_ramdac_addr_lo_byte0 : 8;7 unsigned ka0702$v_ramdac -_addr_lo_fill : 24;+ } ka0702$r_ramdac_addr_lo_bits;* } ka0702$r_ramdac_addr_lo_overlay;S unsigned char ka0702$b_fill1380 [4]; /* Fill to allow sparse space byte mask */ __union {R unsigned int ka0702$l_ramdac_addr_hi; /* RAMDAC color map and registers */ __struct {7 unsigned ka0702$v_ramdac_addr_hi_byte0 : 8;7 unsigned ka0702$v_ramdac_addr_hi_fill : 24;+ } ka0702$r_ramdac_addr_hi_bits;* } ka0702$r_ramda -c_addr_hi_overlay;S unsigned char ka0702$b_fill1390 [4]; /* Fill to allow sparse space byte mask */ __union {S unsigned int ka0702$l_ramdac_reg_addr; /* RAMDAC color map and registers */ __struct {8 unsigned ka0702$v_ramdac_reg_addr_byte0 : 8;8 unsigned ka0702$v_ramdac_reg_addr_fill : 24;, } ka0702$r_ramdac_reg_addr_bits;+ } ka0702$r_ramdac_reg_addr_overlay;S unsigned char ka0702$b_fill1400 [4]; /* Fill to allow sparse spa -ce byte mask */ __union {R unsigned int ka0702$l_ramdac_map_loc; /* RAMDAC color map and registers */ __struct {7 unsigned ka0702$v_ramdac_map_loc_byte0 : 8;7 unsigned ka0702$v_ramdac_map_loc_fill : 24;+ } ka0702$r_ramdac_map_loc_bits;* } ka0702$r_ramdac_map_loc_overlay;+ unsigned char ka0702$b_fill1410 [8164];N unsigned int ka0702$l_fb; /* Video RAM (2 MB dense) */. unsigned char ka0702$b_fill142 -0 [2097148]; } KA0702; #if !defined(__VAXC)3#define ka0702$l_ir ka0702$r_ir_overlay.ka0702$l_irT#define ka0702$v_ir_sfb_int ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_sfb_intV#define ka0702$v_ir_scsi_int ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_scsi_intZ#define ka0702$v_ir_coreio_int ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_coreio_intR#define ka0702$v_ir_bc_tpe ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_bc_tpeR#define ka0702$v_ir_tc_ore ka0702$r_ir_overlay..ka0702$r_ir_bits.ka0702$v_ir_tc_oreR#define ka0702$v_ir_tc_toe ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_tc_toeL#define ka0702$v_ir_bpe ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_bpeL#define ka0702$v_ir_mpe ka0702$r_ir_overlay.ka0702$r_ir_bits.ka0702$v_ir_mpe9#define ka0702$l_tcsr ka0702$r_tcsr_overlay.ka0702$l_tcsrT#define ka0702$v_tcsr_ap0 ka0702$r_tcsr_overlay.ka0702$r_tcsr_bits.ka0702$v_tcsr_ap0T#define ka0702$v_tcsr_ap1 ka0702$r_tcsr_overlay.ka0702$r_tcsr_bits.ka0702$v_tcsr_a.p1T#define ka0702$v_tcsr_ap2 ka0702$r_tcsr_overlay.ka0702$r_tcsr_bits.ka0702$v_tcsr_ap2T#define ka0702$v_tcsr_ap3 ka0702$r_tcsr_overlay.ka0702$r_tcsr_bits.ka0702$v_tcsr_ap3T#define ka0702$v_tcsr_ap4 ka0702$r_tcsr_overlay.ka0702$r_tcsr_bits.ka0702$v_tcsr_ap46#define ka0702$l_mcr ka0702$r_mcr_overlay.ka0702$l_mcrZ#define ka0702$v_mcr_sp0_size ka0702$r_mcr_overlay.ka0702$r_mcr_bits.ka0702$v_mcr_sp0_sizeZ#define ka0702$v_mcr_sp1_size ka0702$r_mcr_overlay.ka0702$r_mcr_bits.ka0702$v_mcr_sp1_sizeZ#def.ine ka0702$v_mcr_sp2_size ka0702$r_mcr_overlay.ka0702$r_mcr_bits.ka0702$v_mcr_sp2_sizeZ#define ka0702$v_mcr_sp3_size ka0702$r_mcr_overlay.ka0702$r_mcr_bits.ka0702$v_mcr_sp3_size6#define ka0702$l_ldp ka0702$r_ldp_overlay.ka0702$l_ldp\#define ka0702$v_ldp_dma_pa_lo ka0702$r_ldp_overlay.ka0702$r_ldp_bits.ka0702$v_ldp_dma_pa_lo\#define ka0702$v_ldp_dma_pa_hi ka0702$r_ldp_overlay.ka0702$r_ldp_bits.ka0702$v_ldp_dma_pa_hiE#define ka0702$l_scomm_tr ka0702$r_scomm_tr_overlay.ka0702$l_scomm_trj#define ka.0702$v_scomm_tr_dma_pa ka0702$r_scomm_tr_overlay.ka0702$r_scomm_tr_bits.ka0702$v_scomm_tr_dma_paE#define ka0702$l_scomm_rc ka0702$r_scomm_rc_overlay.ka0702$l_scomm_rcj#define ka0702$v_scomm_rc_dma_pa ka0702$r_scomm_rc_overlay.ka0702$r_scomm_rc_bits.ka0702$v_scomm_rc_dma_paK#define ka0702$l_printer_tr ka0702$r_printer_tr_overlay.ka0702$l_printer_trr#define ka0702$v_printer_tr_dma_pa ka0702$r_printer_tr_overlay.ka0702$r_printer_tr_bits.ka0702$v_printer_tr_dma_paK#define ka0702$l_printer_rc ka0702.$r_printer_rc_overlay.ka0702$l_printer_rcr#define ka0702$v_printer_rc_dma_pa ka0702$r_printer_rc_overlay.ka0702$r_printer_rc_bits.ka0702$v_printer_rc_dma_paB#define ka0702$l_isdn_tr ka0702$r_isdn_tr_overlay.ka0702$l_isdn_trf#define ka0702$v_isdn_tr_dma_pa ka0702$r_isdn_tr_overlay.ka0702$r_isdn_tr_bits.ka0702$v_isdn_tr_dma_paN#define ka0702$l_isdn_tr_buf ka0702$r_isdn_tr_buf_overlay.ka0702$l_isdn_tr_bufv#define ka0702$v_isdn_tr_buf_dma_pa ka0702$r_isdn_tr_buf_overlay.ka0702$r_isdn_tr_buf_bits.ka0.702$v_isdn_tr_buf_dma_paB#define ka0702$l_isdn_rc ka0702$r_isdn_rc_overlay.ka0702$l_isdn_rcf#define ka0702$v_isdn_rc_dma_pa ka0702$r_isdn_rc_overlay.ka0702$r_isdn_rc_bits.ka0702$v_isdn_rc_dma_paN#define ka0702$l_isdn_rc_buf ka0702$r_isdn_rc_buf_overlay.ka0702$l_isdn_rc_bufv#define ka0702$v_isdn_rc_buf_dma_pa ka0702$r_isdn_rc_buf_overlay.ka0702$r_isdn_rc_buf_bits.ka0702$v_isdn_rc_buf_dma_pa6#define ka0702$l_ssr ka0702$r_ssr_overlay.ka0702$l_ssrX#define ka0702$v_ssr_io_mask ka0702$r_ssr_overlay.ka.0702$r_ssr_bits.ka0702$v_ssr_io_mask^#define ka0702$v_ssr_io_mask_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_io_mask_enP#define ka0702$v_ssr_fpe ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_fpe`#define ka0702$v_ssr_lance_reset ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_lance_reset\#define ka0702$v_ssr_rtc_reset ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_rtc_reset\#define ka0702$v_ssr_scc_reset ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_scc_reset^#def.ine ka0702$v_ssr_isdn_reset ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_isdn_resetT#define ka0702$v_ssr_txdis ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_txdisb#define ka0702$v_ssr_lance_dma_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_lance_dma_en`#define ka0702$v_ssr_isdn_rcv_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_isdn_rcv_en^#define ka0702$v_ssr_isdn_tr_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_isdn_tr_enR#define ka0702$v_ssr_smr0 ka0702$r._ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_smr0R#define ka0702$v_ssr_smr1 ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_smr1R#define ka0702$v_ssr_smra ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_smra\#define ka0702$v_ssr_fast_mode ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_fast_moded#define ka0702$v_ssr_kbd_rc_dma_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_kbd_rc_dma_end#define ka0702$v_ssr_kbd_tr_dma_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_kbd_t .r_dma_enf#define ka0702$v_ssr_comm_rc_dma_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_comm_rc_dma_enf#define ka0702$v_ssr_comm_tr_dma_en ka0702$r_ssr_overlay.ka0702$r_ssr_bits.ka0702$v_ssr_comm_tr_dma_en6#define ka0702$l_sir ka0702$r_sir_overlay.ka0702$l_sirT#define ka0702$v_sir_halt0 ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_halt0T#define ka0702$v_sir_halt1 ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_halt1Z#define ka0702$v_sir_tc_slot0 ka0702$r_sir_overlay.ka0702$r_ .sir_bits.ka0702$v_sir_tc_slot0Z#define ka0702$v_sir_tc_slot1 ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_tc_slot1Z#define ka0702$v_sir_scc0_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc0_intZ#define ka0702$v_sir_scc1_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc1_int\#define ka0702$v_sir_lance_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_lance_intZ#define ka0702$v_sir_isdn_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_isdn_intZ#define ka07 .02$v_sir_cons_sel ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_cons_selb#define ka0702$v_sir_lance_dma_er ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_lance_dma_erb#define ka0702$v_sir_isdn_dma_mre ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_isdn_dma_mrej#define ka0702$v_sir_isdn_dma_rc_intr ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_isdn_dma_rc_intrj#define ka0702$v_sir_isdn_dma_tr_intr ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_isdn_dma_tr_intr`#define ka .0702$v_sir_scc1_dma_ov ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc1_dma_ovb#define ka0702$v_sir_scc1_rcv_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc1_rcv_intf#define ka0702$v_sir_scc1_tr_dma_me ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc1_tr_dma_me`#define ka0702$v_sir_scc1_tr_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc1_tr_int`#define ka0702$v_sir_scc0_dma_ov ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc0_dma_ovb#define ka0702$v_s .ir_scc0_rcv_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc0_rcv_intf#define ka0702$v_sir_scc0_tr_dma_me ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc0_tr_dma_me`#define ka0702$v_sir_scc0_tr_int ka0702$r_sir_overlay.ka0702$r_sir_bits.ka0702$v_sir_scc0_tr_int9#define ka0702$l_simr ka0702$r_simr_overlay.ka0702$l_simrX#define ka0702$v_simr_halt0 ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_halt0X#define ka0702$v_simr_halt1 ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0.702$v_simr_halt1^#define ka0702$v_simr_tc_slot0 ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_tc_slot0^#define ka0702$v_simr_tc_slot1 ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_tc_slot1^#define ka0702$v_simr_scc0_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc0_int^#define ka0702$v_simr_scc1_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc1_int`#define ka0702$v_simr_lance_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_lance_int^#defin.e ka0702$v_simr_isdn_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_isdn_int^#define ka0702$v_simr_cons_sel ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_cons_self#define ka0702$v_simr_lance_dma_er ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_lance_dma_erf#define ka0702$v_simr_isdn_dma_mre ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_isdn_dma_mren#define ka0702$v_simr_isdn_dma_rc_intr ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_isdn_dma_rc_intrn.#define ka0702$v_simr_isdn_dma_tr_intr ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_isdn_dma_tr_intrd#define ka0702$v_simr_scc1_dma_ov ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc1_dma_ovf#define ka0702$v_simr_scc1_rcv_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc1_rcv_intj#define ka0702$v_simr_scc1_tr_dma_me ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc1_tr_dma_med#define ka0702$v_simr_scc1_tr_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka070.2$v_simr_scc1_tr_intd#define ka0702$v_simr_scc0_dma_ov ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc0_dma_ovf#define ka0702$v_simr_scc0_rcv_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc0_rcv_intj#define ka0702$v_simr_scc0_tr_dma_me ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc0_tr_dma_med#define ka0702$v_simr_scc0_tr_int ka0702$r_simr_overlay.ka0702$r_simr_bits.ka0702$v_simr_scc0_tr_int9#define ka0702$l_sadr ka0702$r_sadr_overlay.ka0702$l_sadr\#define .ka0702$v_sadr_tc_addr ka0702$r_sadr_overlay.ka0702$r_sadr_bits.ka0702$v_sadr_tc_addrQ#define ka0702$l_isdn_data_tr ka0702$r_isdn_data_tr_overlay.ka0702$l_isdn_data_trv#define ka0702$v_isdn_data_tr_data ka0702$r_isdn_data_tr_overlay.ka0702$r_isdn_data_tr_bits.ka0702$v_isdn_data_tr_dataQ#define ka0702$l_isdn_data_rc ka0702$r_isdn_data_rc_overlay.ka0702$l_isdn_data_rcv#define ka0702$v_isdn_data_rc_data ka0702$r_isdn_data_rc_overlay.ka0702$r_isdn_data_rc_bits.ka0702$v_isdn_data_rc_dataK#define ka07.02$l_lance_slot ka0702$r_lance_slot_overlay.ka0702$l_lance_slotj#define ka0702$v_lance_slot_cs ka0702$r_lance_slot_overlay.ka0702$r_lance_slot_bits.ka0702$v_lance_slot_cst#define ka0702$v_lance_slot_hw_addr ka0702$r_lance_slot_overlay.ka0702$r_lance_slot_bits.ka0702$v_lance_slot_hw_addrH#define ka0702$l_scc0_slot ka0702$r_scc0_slot_overlay.ka0702$l_scc0_slotf#define ka0702$v_scc0_slot_cs ka0702$r_scc0_slot_overlay.ka0702$r_scc0_slot_bits.ka0702$v_scc0_slot_csp#define ka0702$v_scc0_slot_hw_addr k.a0702$r_scc0_slot_overlay.ka0702$r_scc0_slot_bits.ka0702$v_scc0_slot_hw_addrH#define ka0702$l_scc1_slot ka0702$r_scc1_slot_overlay.ka0702$l_scc1_slotf#define ka0702$v_scc1_slot_cs ka0702$r_scc1_slot_overlay.ka0702$r_scc1_slot_bits.ka0702$v_scc1_slot_csp#define ka0702$v_scc1_slot_hw_addr ka0702$r_scc1_slot_overlay.ka0702$r_scc1_slot_bits.ka0702$v_scc1_slot_hw_addr9#define ka0702$l_mode ka0702$r_mode_overlay.ka0702$l_modeX#define ka0702$v_mode_field ka0702$r_mode_overlay.ka0702$r_mode_bits.ka0702$.v_mode_field?#define ka0702$l_boolop ka0702$r_boolop_overlay.ka0702$l_boolopZ#define ka0702$v_boolop_op ka0702$r_boolop_overlay.ka0702$r_boolop_bits.ka0702$v_boolop_opK#define ka0702$l_pixelshift ka0702$r_pixelshift_overlay.ka0702$l_pixelshiftp#define ka0702$v_pixelshift_count ka0702$r_pixelshift_overlay.ka0702$r_pixelshift_bits.ka0702$v_pixelshift_countE#define ka0702$l_addr_reg ka0702$r_addr_reg_overlay.ka0702$l_addr_regh#define ka0702$v_addr_reg_value ka0702$r_addr_reg_overlay.ka0702$r_add.r_reg_bits.ka0702$v_addr_reg_value<#define ka0702$l_bres1 ka0702$r_bres1_overlay.ka0702$l_bres1X#define ka0702$v_bres1_ei1 ka0702$r_bres1_overlay.ka0702$r_bres1_bits.ka0702$v_bres1_ei1X#define ka0702$v_bres1_ai1 ka0702$r_bres1_overlay.ka0702$r_bres1_bits.ka0702$v_bres1_ai1<#define ka0702$l_bres2 ka0702$r_bres2_overlay.ka0702$l_bres2X#define ka0702$v_bres2_ei2 ka0702$r_bres2_overlay.ka0702$r_bres2_bits.ka0702$v_bres2_ei2X#define ka0702$v_bres2_ai2 ka0702$r_bres2_overlay.ka0702$r_bres2_bits.ka0702.$v_bres2_ai2<#define ka0702$l_bres3 ka0702$r_bres3_overlay.ka0702$l_bres3V#define ka0702$v_bres3_ll ka0702$r_bres3_overlay.ka0702$r_bres3_bits.ka0702$v_bres3_llX#define ka0702$v_bres3_iev ka0702$r_bres3_overlay.ka0702$r_bres3_bits.ka0702$v_bres3_iev9#define ka0702$l_deep ka0702$r_deep_overlay.ka0702$l_deepX#define ka0702$v_deep_plane ka0702$r_deep_overlay.ka0702$r_deep_bits.ka0702$v_deep_planeN#define ka0702$l_v_ref_count ka0702$r_v_ref_count_overlay.ka0702$l_v_ref_countn#define ka0702$v_v_ref._count_vc ka0702$r_v_ref_count_overlay.ka0702$r_v_ref_count_bits.ka0702$v_v_ref_count_vc<#define ka0702$l_v_hor ka0702$r_v_hor_overlay.ka0702$l_v_hor^#define ka0702$v_v_hor_pixels ka0702$r_v_hor_overlay.ka0702$r_v_hor_bits.ka0702$v_v_hor_pixelsV#define ka0702$v_v_hor_fp ka0702$r_v_hor_overlay.ka0702$r_v_hor_bits.ka0702$v_v_hor_fp\#define ka0702$v_v_hor_synch ka0702$r_v_hor_overlay.ka0702$r_v_hor_bits.ka0702$v_v_hor_synchV#define ka0702$v_v_hor_bp ka0702$r_v_hor_overlay.ka0702$r_v_hor_bits.ka0702$.v_v_hor_bp<#define ka0702$l_v_ver ka0702$r_v_ver_overlay.ka0702$l_v_verV#define ka0702$v_v_ver_sl ka0702$r_v_ver_overlay.ka0702$r_v_ver_bits.ka0702$v_v_ver_slV#define ka0702$v_v_ver_fp ka0702$r_v_ver_overlay.ka0702$r_v_ver_bits.ka0702$v_v_ver_fp\#define ka0702$v_v_ver_synch ka0702$r_v_ver_overlay.ka0702$r_v_ver_bits.ka0702$v_v_ver_synchV#define ka0702$v_v_ver_bp ka0702$r_v_ver_overlay.ka0702$r_v_ver_bits.ka0702$v_v_ver_bpN#define ka0702$l_v_base_addr ka0702$r_v_base_addr_overlay.ka0702$l_v_base_.addrp#define ka0702$v_v_base_addr_row ka0702$r_v_base_addr_overlay.ka0702$r_v_base_addr_bits.ka0702$v_v_base_addr_rowW#define ka0702$l_ramdac_addr_lo ka0702$r_ramdac_addr_lo_overlay.ka0702$l_ramdac_addr_lo#define ka0702$v_ramdac_addr_lo_byte0 ka0702$r_ramdac_addr_lo_overlay.ka0702$r_ramdac_addr_lo_bits.ka0702$v_ramdac_addr_lo_byte0W#define ka0702$l_ramdac_addr_hi ka0702$r_ramdac_addr_hi_overlay.ka0702$l_ramdac_addr_hi#define ka0702$v_ramdac_addr_hi_byte0 ka0702$r_ramdac_addr_hi_overlay.ka0702.$r_ramdac_addr_hi_bits.ka0702$v_ramdac_addr_hi_byte0Z#define ka0702$l_ramdac_reg_addr ka0702$r_ramdac_reg_addr_overlay.ka0702$l_ramdac_reg_addr#define ka0702$v_ramdac_reg_addr_byte0 ka0702$r_ramdac_reg_addr_overlay.ka0702$r_ramdac_reg_addr_bits.ka0702$v_ramdac_reg_addr_byte0W#define ka0702$l_ramdac_map_loc ka0702$r_ramdac_map_loc_overlay.ka0702$l_ramdac_map_loc#define ka0702$v_ramdac_map_loc_byte0 ka0702$r_ramdac_map_loc_overlay.ka0702$r_ramdac_map_loc_bits.ka0702$v_ramdac_map_loc_byte0"#endif. /* #if !defined(__VAXC) */ #define KA0702$K_IO_SCB_VEC 2048#define KA0702$K_SCSI_TC_SLOT 3"#define KA0702$K_CORE_IO_TC_SLOT 4"#define KA0702$K_CXTURBO_TC_SLOT 2#define KA0702$K_TC_SLOT0_VEC 0#define KA0702$K_TC_SLOT1_VEC 1 #define KA0702$K_TC_EMPTY2_VEC 2 #define KA0702$K_TC_EMPTY3_VEC 3#define KA0702$K_TC_SLOT4_VEC 4#define KA0702$K_COREIO_VEC 5#define KA0702$K_SFB_VEC 6#define KA0702$K_ETHERNET_VEC 7#define KA0702$K_SCC_VEC 8#define KA0702$K_OPDRVR_XMIT 9#define .KA0702$K_OPDRVR_RCV 10#define KA0702$K_ISDN_VEC 11!#define KA0702$K_TOTAL_VECTORS 12#define KA0702$M_MASK0 0x1#define KA0702$M_MASK1 0x2#define KA0702$M_MASK2 0x4#define KA0702$M_MASK3 0x8 +typedef struct _ka0702$r_ka0702_mask_bits { __union { __struct {( unsigned ka0702$v_mask0 : 1;( unsigned ka0702$v_mask1 : 1;( unsigned ka0702$v_mask2 : 1;( unsigned ka0702$v_mask3 : 1;* unsigned ka0702$v_fill_1_ : 4;& . } ka0702$r_byte_mask_bits;% } ka0702$r_byte_mask_overlay; } KA0702$R_KA0702_MASK_BITS; #if !defined(__VAXC)X#define ka0702$v_mask0 ka0702$r_byte_mask_overlay.ka0702$r_byte_mask_bits.ka0702$v_mask0X#define ka0702$v_mask1 ka0702$r_byte_mask_overlay.ka0702$r_byte_mask_bits.ka0702$v_mask1X#define ka0702$v_mask2 ka0702$r_byte_mask_overlay.ka0702$r_byte_mask_bits.ka0702$v_mask2X#define ka0702$v_mask3 ka0702$r_byte_mask_overlay.ka0702$r_byte_mask_bits.ka0702$v_mask3"#endif /*. #if !defined(__VAXC) */ P/* The following definition defines an entry of a Saved Error Register Table. */T/* This table is pointed to by a cell in the Turbo ADP. The table is divided up */T/* into an entry for each slot. Each entry contains saved copies of IR, TCEREG, */V/* and FADR. The entries are written by the machine check handler on an error, and */N/* read by a driver (at some appropriate time) to determine if a TC error */N/* occurred. . */N/* Define Saved Register Table Entry */%#define KA0702$M_SAVED_IR_SFB_INT 0x4&#define KA0702$M_SAVED_IR_SCSI_INT 0x8)#define KA0702$M_SAVED_IR_COREIO_INT 0x10*#define KA0702$M_SAVED_IR_BC_TPE 0x8000000+#define KA0702$M_SAVED_IR_TC_ORE 0x10000000+#define KA0702$M_SAVED_IR_TC_TOE 0x20000000(#define KA0702$M_SAVED_IR_BPE 0x40000000(#define KA0702$M_SAVED_IR_MPE 0x80000000'#define KA0702$K_SAVED_REG_ENTRY_SIZE 8 "typedef st !.ruct _ka0702_saved_reg { __union {N unsigned int ka0702$l_saved_ir; /* Interrupt reason */ __struct {1 unsigned ka0702$v_saved_ir_fill1 : 2;3 unsigned ka0702$v_saved_ir_sfb_int : 1;4 unsigned ka0702$v_saved_ir_scsi_int : 1;6 unsigned ka0702$v_saved_ir_coreio_int : 1;2 unsigned ka0702$v_saved_ir_fill2 : 22;2 unsigned ka0702$v_saved_ir_bc_tpe : 1;2 unsigned ka0702$v_saved_ir_tc_ ".ore : 1;2 unsigned ka0702$v_saved_ir_tc_toe : 1;/ unsigned ka0702$v_saved_ir_bpe : 1;/ unsigned ka0702$v_saved_ir_mpe : 1;% } ka0702$r_saved_ir_bits;$ } ka0702$r_saved_ir_overlay;N unsigned int ka0702$l_fill; /* to quad boundary */ } KA0702_SAVED_REG; #if !defined(__VAXC)E#define ka0702$l_saved_ir ka0702$r_saved_ir_overlay.ka0702$l_saved_irl#define ka0702$v_saved_ir_sfb_int ka0702$r_saved_ir_overlay.ka#.0702$r_saved_ir_bits.ka0702$v_saved_ir_sfb_intn#define ka0702$v_saved_ir_scsi_int ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_scsi_intr#define ka0702$v_saved_ir_coreio_int ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_coreio_intj#define ka0702$v_saved_ir_bc_tpe ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_bc_tpej#define ka0702$v_saved_ir_tc_ore ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_tc_orej#define ka0702$.$v_saved_ir_tc_toe ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_tc_toed#define ka0702$v_saved_ir_bpe ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_bped#define ka0702$v_saved_ir_mpe ka0702$r_saved_ir_overlay.ka0702$r_saved_ir_bits.ka0702$v_saved_ir_mpe"#endif /* #if !defined(__VAXC) */ N/* Define indexes into error table. Indexes are 0 thru 10. */N/* The count of the number of entries is 11. */#define %.KA0702$K_SLOT0_INDEX 0#define KA0702$K_SLOT1_INDEX 1#define KA0702$K_SLOT2_INDEX 2#define KA0702$K_SLOT3_INDEX 3#define KA0702$K_SCSI_INDEX 4#define KA0702$K_COREIO_INDEX 5 #define KA0702$K_CXTURBO_INDEX 6(#define KA0702$K_SAVED_REG_ENTRY_COUNT 7 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __c&.plusplus }#endif#pragma __standard #endif /* __KA0702DEF_LOADED */ wwa[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the '.**/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior writte(.n permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */I/* Source: ). 16-SEP-1993 16:28:19 $1$DGA8345:[LIB_H.SRC]KA0802DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KA0802DEF ***/#ifndef __KA0802DEF_LOADED#define __KA0802DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas suppor*.ted */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#end+.if #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define KA0802$M_APC_HAE 0x1F*#define KA0802$M_APC_INTERVAL_TIMER 0xFFFF(#define KA0802$M_APC_BUFFER_STATUS_E 0x1(#define KA0802$M_APC_BUFFER_STATUS_O 0x2(#define KA0802$M_APC_BUFFER_STATUS_M 0x4(#define KA0802$M_APC_BUFFER_STATUS_H 0x8(#define KA0802$M_APC_ERROR_STATUS 0xFFFF&#define KA0802$M_APC_ERROR_MASK 0xFFFF)#define KA0802$M_APC_LAST_PREFIX_LEN 0x60*#def ,.ine KA0802$M_APC_LAST_PREFIX_OFF 0x180,#define KA0802$M_APC_LAST_PREFIX_CYCLE 0xE00-#define KA0802$M_APC_LAST_PREFIX_FILL1 0x1000)#define KA0802$M_APC_LAST_PREFIX_A 0x2000)#define KA0802$M_APC_LAST_PREFIX_E 0x4000*#define KA0802$M_APC_LAST_PREFIX_RW 0x8000*#define KA0802$M_APC_LAST_PREFIX_V 0x100001#define KA0802$M_APC_LAST_PREFIX_FILL2 0xFFFE0000'#define KA0802$M_APC_LOCK_ADDRESS_L 0x1,#define KA0802$M_APC_LOCK_ADDRESS 0xFFFFFFE0$#define KA0802$M_APC_PREFIX_LEN 0x18$#define KA0802$M_A-.PC_PREFIX_OFF 0x60,#define KA0802$M_APC_PREFIX_SUB_FOR_10 0x180'#define KA0802$M_APC_PREFIX_CYCLE 0xE00,#define KA0802$M_APC_PREFIX_SUB_87_EN 0x1000.#define KA0802$M_APC_PREFIX_SUB_11_9_EN 0x2000O#define KA0802$S_KA0802DEF 32768 /* Old KA0802 size for compatibility */ #pragma __member_alignmenttypedef struct _ka0802 { __union { void *ka0802$l_apc_hae; __struct {* unsigned ka0802$v_apc_hae : 5;0 unsigned ka0802$v_apc_hae_fill : 27; ..$ } ka0802$r_apc_hae_bits;# } ka0802$r_apc_hae_overlay;( unsigned char ka0802$b_fill10 [124]; __union {* void *ka0802$l_apc_interval_timer; __struct {6 unsigned ka0802$v_apc_interval_timer : 16;; unsigned ka0802$v_apc_interval_timer_fill : 16;/ } ka0802$r_apc_interval_timer_bits;- } ka0802$r_apc_interval_timer_overla;' unsigned char ka0802$b_fill20 [60]; __union {) void *ka0802$l_apc_buf /.fer_status; __struct {6 unsigned ka0802$v_apc_buffer_status_e : 1;6 unsigned ka0802$v_apc_buffer_status_o : 1;6 unsigned ka0802$v_apc_buffer_status_m : 1;6 unsigned ka0802$v_apc_buffer_status_h : 1;: unsigned ka0802$v_apc_buffer_status_fill : 28;. } ka0802$r_apc_buffer_status_bits;- } ka0802$r_apc_buffer_status_overlay;' unsigned char ka0802$b_fill30 [60]; __union {( void *ka0802$l_apc_error 0._status; __struct {4 unsigned ka0802$v_apc_error_status : 16;9 unsigned ka0802$v_apc_error_status_fill : 16;- } ka0802$r_apc_error_status_bits;, } ka0802$r_apc_error_status_overlay;' unsigned char ka0802$b_fill40 [60]; __union {& void *ka0802$l_apc_error_mask; __struct {2 unsigned ka0802$v_apc_error_mask : 16;7 unsigned ka0802$v_apc_error_mask_fill : 16;+ } ka0802$r_apc_error_mas 1.k_bits;* } ka0802$r_apc_error_mask_overlay;' unsigned char ka0802$b_fill50 [60]; __union {' void *ka0802$l_apc_last_prefix; __struct {7 unsigned ka0802$v_apc_last_prefix_fill : 5;6 unsigned ka0802$v_apc_last_prefix_len : 2;6 unsigned ka0802$v_apc_last_prefix_off : 2;8 unsigned ka0802$v_apc_last_prefix_cycle : 3;8 unsigned ka0802$v_apc_last_prefix_fill1 : 1;4 unsigned ka0802$v_apc_last_prefi 2.x_a : 1;4 unsigned ka0802$v_apc_last_prefix_e : 1;5 unsigned ka0802$v_apc_last_prefix_rw : 1;4 unsigned ka0802$v_apc_last_prefix_v : 1;9 unsigned ka0802$v_apc_last_prefix_fill2 : 15;, } ka0802$r_apc_last_prefix_bits;+ } ka0802$r_apc_last_prefix_overlay;' unsigned char ka0802$b_fill60 [60]; __union {( void *ka0802$l_apc_lock_address; __struct {5 unsigned ka0802$v_apc_lock_address_l : 1;8 3. unsigned ka0802$v_apc_lock_address_fill : 4;4 unsigned ka0802$v_apc_lock_address : 27;- } ka0802$r_apc_lock_address_bits;, } ka0802$r_apc_lock_address_overlay;' unsigned char ka0802$b_fill70 [60]; __union {- void *ka0802$l_apc_local_device_port; __struct {= unsigned ka0802$v_apc_local_device_port_fil : 32;1 } ka0802$r_apc_local_device_port_bit;- } ka0802$r_apc_local_device_port_ove;( unsign4.ed char ka0802$b_fill80 [124]; __union {& void *ka0802$l_apc_misc_data0; __struct {7 unsigned ka0802$v_apc_misc_data0_fill : 32;+ } ka0802$r_apc_misc_data0_bits;* } ka0802$r_apc_misc_data0_overlay;' unsigned char ka0802$b_fill90 [60]; __union {& void *ka0802$l_apc_misc_data1; __struct {7 unsigned ka0802$v_apc_misc_data1_fill : 32;+ } ka0802$r_apc_misc_data1_bits;* } ka0802$r_apc_m 5.isc_data1_overlay;* unsigned char ka0802$b_fill100 [7484]; __union {" void *ka0802$l_apc_prefix; __struct {2 unsigned ka0802$v_apc_prefix_fill : 3;1 unsigned ka0802$v_apc_prefix_len : 2;1 unsigned ka0802$v_apc_prefix_off : 2;8 unsigned ka0802$v_apc_prefix_sub_for_10 : 2;3 unsigned ka0802$v_apc_prefix_cycle : 3;7 unsigned ka0802$v_apc_prefix_sub_87_en : 1;9 unsigned ka0802$v_apc_prefix_s 6.ub_11_9_en : 1;4 unsigned ka0802$v_apc_prefix_fill1 : 18;' } ka0802$r_apc_prefix_bits;& } ka0802$r_apc_prefix_overlay;* unsigned char ka0802$b_fill110 [8188];* unsigned char ka0802$b_fill120 [8192]; __union {) void *ka0802$l_apc_cache_control; __struct {: unsigned ka0802$v_apc_cache_control_fill : 32;. } ka0802$r_apc_cache_control_bits;- } ka0802$r_apc_cache_control_overlay;) unsigned char ka0802$b7._fill130 [124]; __union {& void *ka0802$l_apc_pci_config; __struct {7 unsigned ka0802$v_apc_pci_config_fill : 32;+ } ka0802$r_apc_pci_config_bits;* } ka0802$r_apc_pci_config_overlay;( unsigned char ka0802$b_fill140 [60]; __union {& void *ka0802$l_apc_pci_status; __struct {7 unsigned ka0802$v_apc_pci_status_fill : 32;+ } ka0802$r_apc_pci_status_bits;* } ka0802$r_apc_pci_status_over8.lay;( unsigned char ka0802$b_fill150 [60]; __union {' void *ka0802$l_apc_mem_bank_01; __struct {8 unsigned ka0802$v_apc_mem_bank_01_fill : 32;, } ka0802$r_apc_mem_bank_01_bits;+ } ka0802$r_apc_mem_bank_01_overlay;( unsigned char ka0802$b_fill160 [28]; __union {' void *ka0802$l_apc_mem_bank_23; __struct {8 unsigned ka0802$v_apc_mem_bank_23_fill : 32;, } ka0802$r_apc_mem_bank_23_bits;+ 9. } ka0802$r_apc_mem_bank_23_overlay;( unsigned char ka0802$b_fill170 [28]; __union {' void *ka0802$l_apc_mem_bank_45; __struct {8 unsigned ka0802$v_apc_mem_bank_45_fill : 32;, } ka0802$r_apc_mem_bank_45_bits;+ } ka0802$r_apc_mem_bank_45_overlay;( unsigned char ka0802$b_fill180 [28]; __union {' void *ka0802$l_apc_mem_bank_67; __struct {8 unsigned ka0802$v_apc_mem_bank_67_fill : 32;, :. } ka0802$r_apc_mem_bank_67_bits;+ } ka0802$r_apc_mem_bank_67_overlay;( unsigned char ka0802$b_fill190 [28]; __union {' void *ka0802$l_apc_mem_control; __struct {8 unsigned ka0802$v_apc_mem_control_fill : 32;, } ka0802$r_apc_mem_control_bits;+ } ka0802$r_apc_mem_control_overlay;( unsigned char ka0802$b_fill200 [60]; __union {' void *ka0802$l_apc_ext_pc_hole; __struct {8 unsigned ka0802$v_ ;.apc_ext_pc_hole_fill : 32;, } ka0802$r_apc_ext_pc_hole_bits;+ } ka0802$r_apc_ext_pc_hole_overlay;( unsigned char ka0802$b_fill210 [28]; __union {) void *ka0802$l_apc_ext_prog_hole; __struct {: unsigned ka0802$v_apc_ext_prog_hole_fill : 32;. } ka0802$r_apc_ext_prog_hole_bits;- } ka0802$r_apc_ext_prog_hole_overlay;( unsigned char ka0802$b_fill220 [28];$ void *ka0802$l_apc_diag_control;) unsigned char ka0802$b<._fill230 [124];" void *ka0802$l_apc_diag_data0;( unsigned char ka0802$b_fill240 [60];" void *ka0802$l_apc_diag_data1;( unsigned char ka0802$b_fill250 [60];! void *ka0802$l_apc_rev_level;( unsigned char ka0802$b_fill260 [60];& void *ka0802$l_apc_parity_control;) unsigned char ka0802$b_fill270 [188];" void *ka0802$l_apc_sm_address;( unsigned char ka0802$b_fill280 [60]; void *ka0802$l_apc_sm_data;* unsigned char ka0802$b_fill290 [7100]; } KA0802;=. #if !defined(__VAXC)B#define ka0802$l_apc_hae ka0802$r_apc_hae_overlay.ka0802$l_apc_haeX#define ka0802$v_apc_hae ka0802$r_apc_hae_overlay.ka0802$r_apc_hae_bits.ka0802$v_apc_haeb#define ka0802$l_apc_interval_timer ka0802$r_apc_interval_timer_overla.ka0802$l_apc_interval_timer#define ka0802$v_apc_interval_timer ka0802$r_apc_interval_timer_overla.ka0802$r_apc_interval_timer_bits.ka0802$v_apc_interval_timer`#define ka0802$l_apc_buffer_status ka0802$r_apc_buffer_status_overlay.ka0802$l_apc_buf>.fer_status#define ka0802$v_apc_buffer_status_e ka0802$r_apc_buffer_status_overlay.ka0802$r_apc_buffer_status_bits.ka0802$v_apc_buffer_status_e#define ka0802$v_apc_buffer_status_o ka0802$r_apc_buffer_status_overlay.ka0802$r_apc_buffer_status_bits.ka0802$v_apc_buffer_status_o#define ka0802$v_apc_buffer_status_m ka0802$r_apc_buffer_status_overlay.ka0802$r_apc_buffer_status_bits.ka0802$v_apc_buffer_status_m#define ka0802$v_apc_buffer_status_h ka0802$r_apc_buffer_status_overlay.ka0802$r_apc_buffer_?.status_bits.ka0802$v_apc_buffer_status_h]#define ka0802$l_apc_error_status ka0802$r_apc_error_status_overlay.ka0802$l_apc_error_status|#define ka0802$v_apc_error_status ka0802$r_apc_error_status_overlay.ka0802$r_apc_error_status_bits.ka0802$v_apc_error_statusW#define ka0802$l_apc_error_mask ka0802$r_apc_error_mask_overlay.ka0802$l_apc_error_maskt#define ka0802$v_apc_error_mask ka0802$r_apc_error_mask_overlay.ka0802$r_apc_error_mask_bits.ka0802$v_apc_error_maskZ#define ka0802$l_apc_last_prefix k@.a0802$r_apc_last_prefix_overlay.ka0802$l_apc_last_prefix#define ka0802$v_apc_last_prefix_len ka0802$r_apc_last_prefix_overlay.ka0802$r_apc_last_prefix_bits.ka0802$v_apc_last_prefix_len#define ka0802$v_apc_last_prefix_off ka0802$r_apc_last_prefix_overlay.ka0802$r_apc_last_prefix_bits.ka0802$v_apc_last_prefix_off#define ka0802$v_apc_last_prefix_cycle ka0802$r_apc_last_prefix_overlay.ka0802$r_apc_last_prefix_bits.ka0802$v_apc_last_prefix_cycle#define ka0802$v_apc_last_prefix_fill1 ka0802$r_apc_laA.st_prefix_overlay.ka0802$r_apc_last_prefix_bits.ka0802$v_apc_last_prefix_fill1|#define ka0802$v_apc_last_prefix_a ka0802$r_apc_last_prefix_overlay.ka0802$r_apc_last_prefix_bits.ka0802$v_apc_last_prefix_a|#define ka0802$v_apc_last_prefix_e ka0802$r_apc_last_prefix_overlay.ka0802$r_apc_last_prefix_bits.ka0802$v_apc_last_prefix_e~#define ka0802$v_apc_last_prefix_rw ka0802$r_apc_last_prefix_overlay.ka0802$r_apc_last_prefix_bits.ka0802$v_apc_last_prefix_rw|#define ka0802$v_apc_last_prefix_v ka0802$r_apB.c_last_prefix_overlay.ka0802$r_apc_last_prefix_bits.ka0802$v_apc_last_prefix_v#define ka0802$v_apc_last_prefix_fill2 ka0802$r_apc_last_prefix_overlay.ka0802$r_apc_last_prefix_bits.ka0802$v_apc_last_prefix_fill2]#define ka0802$l_apc_lock_address ka0802$r_apc_lock_address_overlay.ka0802$l_apc_lock_address#define ka0802$v_apc_lock_address_l ka0802$r_apc_lock_address_overlay.ka0802$r_apc_lock_address_bits.ka0802$v_apc_lock_address_l|#define ka0802$v_apc_lock_address ka0802$r_apc_lock_address_overlaC.y.ka0802$r_apc_lock_address_bits.ka0802$v_apc_lock_addressh#define ka0802$l_apc_local_device_port ka0802$r_apc_local_device_port_ove.ka0802$l_apc_local_device_portW#define ka0802$l_apc_misc_data0 ka0802$r_apc_misc_data0_overlay.ka0802$l_apc_misc_data0W#define ka0802$l_apc_misc_data1 ka0802$r_apc_misc_data1_overlay.ka0802$l_apc_misc_data1K#define ka0802$l_apc_prefix ka0802$r_apc_prefix_overlay.ka0802$l_apc_prefixl#define ka0802$v_apc_prefix_len ka0802$r_apc_prefix_overlay.ka0802$r_apc_prefix_biD.ts.ka0802$v_apc_prefix_lenl#define ka0802$v_apc_prefix_off ka0802$r_apc_prefix_overlay.ka0802$r_apc_prefix_bits.ka0802$v_apc_prefix_offz#define ka0802$v_apc_prefix_sub_for_10 ka0802$r_apc_prefix_overlay.ka0802$r_apc_prefix_bits.ka0802$v_apc_prefix_sub_for_10p#define ka0802$v_apc_prefix_cycle ka0802$r_apc_prefix_overlay.ka0802$r_apc_prefix_bits.ka0802$v_apc_prefix_cyclex#define ka0802$v_apc_prefix_sub_87_en ka0802$r_apc_prefix_overlay.ka0802$r_apc_prefix_bits.ka0802$v_apc_prefix_sub_87_en|#define E.ka0802$v_apc_prefix_sub_11_9_en ka0802$r_apc_prefix_overlay.ka0802$r_apc_prefix_bits.ka0802$v_apc_prefix_sub_11_9_en`#define ka0802$l_apc_cache_control ka0802$r_apc_cache_control_overlay.ka0802$l_apc_cache_controlW#define ka0802$l_apc_pci_config ka0802$r_apc_pci_config_overlay.ka0802$l_apc_pci_configW#define ka0802$l_apc_pci_status ka0802$r_apc_pci_status_overlay.ka0802$l_apc_pci_statusZ#define ka0802$l_apc_mem_bank_01 ka0802$r_apc_mem_bank_01_overlay.ka0802$l_apc_mem_bank_01Z#define ka0802$l_aF.pc_mem_bank_23 ka0802$r_apc_mem_bank_23_overlay.ka0802$l_apc_mem_bank_23Z#define ka0802$l_apc_mem_bank_45 ka0802$r_apc_mem_bank_45_overlay.ka0802$l_apc_mem_bank_45Z#define ka0802$l_apc_mem_bank_67 ka0802$r_apc_mem_bank_67_overlay.ka0802$l_apc_mem_bank_67Z#define ka0802$l_apc_mem_control ka0802$r_apc_mem_control_overlay.ka0802$l_apc_mem_controlZ#define ka0802$l_apc_ext_pc_hole ka0802$r_apc_ext_pc_hole_overlay.ka0802$l_apc_ext_pc_hole`#define ka0802$l_apc_ext_prog_hole ka0802$r_apc_ext_prog_hole_ovG.erlay.ka0802$l_apc_ext_prog_hole"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KA0802DEF_LOADED */ ww^c[UM/***************************************************************************H./M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** I. **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** J. **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */I/* Source: 10-MAR-1995 16:55:05 $1$DGA8345:[LIB_H.SRC]KA0902DEF.SDL;1 *//************************************************************************************************************************* K.*******//*** MODULE $KA0902DEF ***/#ifndef __KA0902DEF_LOADED#define __KA0902DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointeL.rs */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif "#define KA0902$K_MAX_CPU_MODULES 4%#define KA0902$K_MAXM._MEMORY_MODULES 4##define KA0902$K_OPDRIVER_RCV_ISR 6$#define KA0902$K_OPDRIVER_XMT_ISR 15&#define KA0902_IIO$M_IOCSR_EN_LDEN 0x1!#define KA0902_IIO$M_IOCSR_EL 0x2##define KA0902_IIO$M_IOCSR_ESMV 0x4##define KA0902_IIO$M_IOCSR_PDBP 0x8(#define KA0902_IIO$M_IOCSR_PCIPRST0 0x10(#define KA0902_IIO$M_IOCSR_PCIPRST1 0x20##define KA0902_IIO$M_IOCSR_INT 0x40%#define KA0902_IIO$M_IOCSR_TLBEE 0x80&#define KA0902_IIO$M_IOCSR_CXACK 0x100&#define KA0902_IIO$M_IOCSR_FILL2 0x200%#define KA0902_I N.IO$M_IOCSR_EXEX 0x400&#define KA0902_IIO$M_IOCSR_FILL3 0x800(#define KA0902_IIO$M_IOCSR_CAWWP0 0x1000(#define KA0902_IIO$M_IOCSR_CAWWP2 0x2000'#define KA0902_IIO$M_IOCSR_DWWPE 0x4000&#define KA0902_IIO$M_IOCSR_MBA5 0x8000'#define KA0902_IIO$M_IOCSR_MBA6 0x10000'#define KA0902_IIO$M_IOCSR_MBA7 0x20000+#define KA0902_IIO$M_IOCSR_PCIPRST3 0x40000+#define KA0902_IIO$M_IOCSR_PCIPRST4 0x80000*#define KA0902_IIO$M_IOCSR_PDWWP1 0x100000*#define KA0902_IIO$M_IOCSR_PDWWP0 0x200000'#define KA09 O.02_IIO$M_IOCSR_PBR 0x400000'#define KA0902_IIO$M_IOCSR_PIR 0x800000*#define KA0902_IIO$M_IOCSR_ENCOI 0x1000000)#define KA0902_IIO$M_IOCSR_EPMS 0x2000000)#define KA0902_IIO$M_IOCSR_ETLB 0x4000000)#define KA0902_IIO$M_IOCSR_EACC 0x8000000*#define KA0902_IIO$M_IOCSR_FTLB 0x10000000*#define KA0902_IIO$M_IOCSR_ECPC 0x20000000)#define KA0902_IIO$M_IOCSR_CIR 0x40000000)#define KA0902_IIO$M_IOCSR_EPL 0x80000000$#define KA0902_IIO$M_IOCSR_CBBCE 0x1"#define KA0902_IIO$M_IOCSR_TRN 0xE$#define P.KA0902_IIO$M_IOCSR_SMVL 0x70$#define KA0902_IIO$M_IOCSR_MBA4 0x80$#define KA0902_IIO$M_IOCSR_EPR 0x100'#define KA0902_IIO$M_IOCSR_RDPE64 0x200'#define KA0902_IIO$M_IOCSR_ADPE64 0x400'#define KA0902_IIO$M_IOCSR_WDPE64 0x800(#define KA0902_IIO$M_IOCSR_CAWWP1 0x1000(#define KA0902_IIO$M_IOCSR_CAWWP3 0x2000'#define KA0902_IIO$M_IOCSR_DWWPO 0x4000'#define KA0902_IIO$M_IOCSR_T24ST 0x8000'#define KA0902_IIO$M_IOCSR_PPC1 0x10000'#define KA0902_IIO$M_IOCSR_PPC2 0x20000(#define KA0902_IIO$M_I Q.OCSR_STALL 0x40000(#define KA0902_IIO$M_IOCSR_FILL4 0x80000'#define KA0902_IIO$M_IOCSR_PRM 0x100000'#define KA0902_IIO$M_IOCSR_PWM 0x200000+#define KA0902_IIO$M_IOCSR_FPRDPED 0x400000+#define KA0902_IIO$M_IOCSR_FPADPED 0x800000,#define KA0902_IIO$M_IOCSR_FPWDPED 0x1000000*#define KA0902_IIO$M_IOCSR_EPNMI 0x2000000*#define KA0902_IIO$M_IOCSR_EPDTI 0x4000000*#define KA0902_IIO$M_IOCSR_EPSEI 0x8000000+#define KA0902_IIO$M_IOCSR_EPPEI 0x10000000+#define KA0902_IIO$M_IOCSR_ERDPC 0x20000000 R.,#define KA0902_IIO$M_IOCSR_EPADPC 0x40000000+#define KA0902_IIO$M_IOCSR_EWDPC 0x80000000"#define KA0902_IIO$M_CERR1_URE 0x1"#define KA0902_IIO$M_CERR1_NAE 0x2##define KA0902_IIO$M_CERR1_CAPE 0x4$#define KA0902_IIO$M_CERR1_MCAPE 0x8%#define KA0902_IIO$M_CERR1_RWDPE 0x10%#define KA0902_IIO$M_CERR1_MWRPE 0x20$#define KA0902_IIO$M_CERR1_RDPE 0x40%#define KA0902_IIO$M_CERR1_MRDPE 0x80&#define KA0902_IIO$M_CERR1_CAPE0 0x100&#define KA0902_IIO$M_CERR1_CAPE2 0x200%#define KA0902_IIO$M_CERR1S._DPE0 0x400%#define KA0902_IIO$M_CERR1_DPE2 0x800&#define KA0902_IIO$M_CERR1_DPE4 0x1000&#define KA0902_IIO$M_CERR1_DPE6 0x2000'#define KA0902_IIO$M_CERR1_CWDP 0x10000&#define KA0902_IIO$M_CERR1_BSE 0x20000(#define KA0902_IIO$M_CERR1_IPFNE 0x40000&#define KA0902_IIO$M_CERR1_CAPE1 0x100&#define KA0902_IIO$M_CERR1_CAPE3 0x200%#define KA0902_IIO$M_CERR1_DPE1 0x400%#define KA0902_IIO$M_CERR1_DPE3 0x800&#define KA0902_IIO$M_CERR1_DPE5 0x1000&#define KA0902_IIO$M_CERR1_DPE7 0x2000'#define T.KA0902_IIO$M_CERR3_L 0xFFFFFFFF/#define KA0902_IIO$M_CERR3_H 0xFFFFFFFF00000000$#define KA0902_IIO$M_PERR1_PWDPE 0x1##define KA0902_IIO$M_PERR1_PAPE 0x2$#define KA0902_IIO$M_PERR1_PRDPE 0x4"#define KA0902_IIO$M_PERR1_PPE 0x8##define KA0902_IIO$M_PERR1_PSE 0x10$#define KA0902_IIO$M_PERR1_PDTE 0x20##define KA0902_IIO$M_PERR1_NMI 0x40%#define KA0902_IIO$M_PERR1_PPCSE 0x80'#define KA0902_IIO$M_PERR1_WDPE64 0x100'#define KA0902_IIO$M_PERR1_ADPE64 0x200'#define KA0902_IIO$M_PERR1_RDPE64 U.0x400##define KA0902_IIO$M_PERR1_TA 0x800*#define KA0902_IIO$M_PERR1_PRDPE64 0x10000*#define KA0902_IIO$M_PERR1_PADPE64 0x20000*#define KA0902_IIO$M_PERR1_PWDPE64 0x40000&#define KA0902_IIO$M_PERR1_PTA 0x80000&#define KA0902_IIO$M_PSCM_L 0xFFFFFFFF.#define KA0902_IIO$M_PSCM_H 0xFFFFFFFF00000000(#define KA0902_IIO$M_HAE1_PUA_BIT26 0x20&#define KA0902_IIO$M_HBASE_PHE1 0x2000&#define KA0902_IIO$M_HBASE_PHE2 0x4000+#define KA0902_IIO$M_HBASE_R0_ENA 0x1000000+#define KA0902_IIO$M_HBASE_R1_EN V.A 0x2000000+#define KA0902_IIO$M_HBASE_R2_ENA 0x4000000+#define KA0902_IIO$M_HBASE_R3_ENA 0x8000000,#define KA0902_IIO$M_HBASE_R4_ENA 0x10000000,#define KA0902_IIO$M_HBASE_R5_ENA 0x20000000,#define KA0902_IIO$M_HBASE_R6_ENA 0x40000000,#define KA0902_IIO$M_HBASE_R7_ENA 0x80000000%#define KA0902_IIO$M_HBASE_R8_ENA 0x1%#define KA0902_IIO$M_HBASE_R9_ENA 0x2&#define KA0902_IIO$M_HBASE_R10_ENA 0x4&#define KA0902_IIO$M_HBASE_R11_ENA 0x8'#define KA0902_IIO$M_HBASE_R12_ENA 0x10'#define KA0902 W._IIO$M_HBASE_R13_ENA 0x20'#define KA0902_IIO$M_HBASE_R14_ENA 0x40'#define KA0902_IIO$M_WBASE1_PPE 0x20000'#define KA0902_IIO$M_WBASE1_SGE 0x40000'#define KA0902_IIO$M_WBASE1_PWE 0x80000'#define KA0902_IIO$M_WBASE2_PPE 0x20000'#define KA0902_IIO$M_WBASE2_SGE 0x40000'#define KA0902_IIO$M_WBASE2_PWE 0x80000$#define KA0902_IIO$M_TLBBR_TLBBV 0x1(#define KA0902_IIO$M_TLBBR_TLBBD 0x7FFFE&#define KA0902_IIO$M_IVRPR_PRVECT 0xFF%#define KA0902_IIO$M_IVRPR_IA 0x3FFFF-#define KA0902_IIO$M_HAE X.3_CFG_TYPE 0xC0000000&#define KA0902_IIO$M_WBASE3_PPE 0x1000'#define KA0902_IIO$M_WBASE3_SGE 0x40000'#define KA0902_IIO$M_WBASE3_PWE 0x80000(#define KA0902_IIO$M_TDR0_TLBTD0 0x3FFFF+#define KA0902_IIO$M_TDR0_TLBTD1 0x3FFC0000##define KA0902_IIO$M_TDR0_TLBV0 0x1(#define KA0902_IIO$M_TDR0_TLBPFN 0x7FFFE(#define KA0902_IIO$M_TDR1_TLBTD0 0x3FFFF+#define KA0902_IIO$M_TDR1_TLBTD1 0x3FFC0000##define KA0902_IIO$M_TDR1_TLBV1 0x1(#define KA0902_IIO$M_TDR1_TLBPFN 0x7FFFE(#define KA0902_IIO$M_T Y.DR2_TLBTD0 0x3FFFF+#define KA0902_IIO$M_TDR2_TLBTD1 0x3FFC0000##define KA0902_IIO$M_TDR2_TLBV2 0x1(#define KA0902_IIO$M_TDR2_TLBPFN 0x7FFFE(#define KA0902_IIO$M_TDR3_TLBTD0 0x3FFFF+#define KA0902_IIO$M_TDR3_TLBTD1 0x3FFC0000##define KA0902_IIO$M_TDR3_TLBV3 0x1(#define KA0902_IIO$M_TDR3_TLBPFN 0x7FFFE(#define KA0902_IIO$M_TDR4_TLBTD0 0x3FFFF+#define KA0902_IIO$M_TDR4_TLBTD1 0x3FFC0000##define KA0902_IIO$M_TDR4_TLBV4 0x1(#define KA0902_IIO$M_TDR4_TLBPFN 0x7FFFE(#define KA0902_IIO$M_TDR Z.5_TLBTD0 0x3FFFF+#define KA0902_IIO$M_TDR5_TLBTD1 0x3FFC0000##define KA0902_IIO$M_TDR5_TLBV5 0x1(#define KA0902_IIO$M_TDR5_TLBPFN 0x7FFFE(#define KA0902_IIO$M_TDR6_TLBTD0 0x3FFFF+#define KA0902_IIO$M_TDR6_TLBTD1 0x3FFC0000##define KA0902_IIO$M_TDR6_TLBV6 0x1(#define KA0902_IIO$M_TDR6_TLBPFN 0x7FFFE(#define KA0902_IIO$M_TDR7_TLBTD0 0x3FFFF+#define KA0902_IIO$M_TDR7_TLBTD1 0x3FFC0000##define KA0902_IIO$M_TDR7_TLBV7 0x1(#define KA0902_IIO$M_TDR7_TLBPFN 0x7FFFE&#define KA0902_IIO$M_WBASE[.4_PPE 0x1000'#define KA0902_IIO$M_WBASE4_SGE 0x40000'#define KA0902_IIO$M_WBASE4_PWE 0x80000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0902_iio {N/* I/O control/status register */#pragma __nomember_alignment __union {# __int64 ka0902_iio$q_iocsr; __struct {\. __union {2 unsigned int ka0902_iio$l_iocsr_l; __struct {T unsigned ka0902_iio$v_iocsr_en_lden : 1; /* dense hole enable */N unsigned ka0902_iio$v_iocsr_el : 1; /* Enable loopback */Y unsigned ka0902_iio$v_iocsr_esmv : 1; /* State Machine Visibility */T unsigned ka0902_iio$v_iocsr_pdbp : 1; /* Drive PCI bad parity */V unsigned ka0902_iio$v_iocsr_pciprs].t0 : 1; /* PCI slot 0 present */V unsigned ka0902_iio$v_iocsr_pciprst1 : 1; /* PCI slot 1 present */Y unsigned ka0902_iio$v_iocsr_int : 1; /* external interrupt pin sts */Q unsigned ka0902_iio$v_iocsr_tlbee : 1; /* TLB error enable */Q unsigned ka0902_iio$v_iocsr_cxack : 1; /* log cxack errors */N unsigned ka0902_iio$v_iocsr_fill2 : 1; /* */W unsigned ka0902_iio$v_io^.csr_exex : 1; /* Exclusive Exchange cmd */N unsigned ka0902_iio$v_iocsr_fill3 : 1; /* */[ unsigned ka0902_iio$v_iocsr_cawwp0 : 1; /* Write CBUS C/A bad parity */[ unsigned ka0902_iio$v_iocsr_cawwp2 : 1; /* Write CBUS C/A bad parity */[ unsigned ka0902_iio$v_iocsr_dwwpe : 1; /* Write CBUS even bad parity */T unsigned ka0902_iio$v_iocsr_mba5 : 1; /* external MBA5 status */T _. unsigned ka0902_iio$v_iocsr_mba6 : 1; /* external MBA6 status */T unsigned ka0902_iio$v_iocsr_mba7 : 1; /* external MBA7 status */S unsigned ka0902_iio$v_iocsr_pciprst3 : 1; /* slot 4 present1 */S unsigned ka0902_iio$v_iocsr_pciprst4 : 1; /* slot 4 present2 */[ unsigned ka0902_iio$v_iocsr_pdwwp1 : 1; /* Write CBUS DMA bad parity */[ unsigned ka0902_iio$v_iocsr_pdwwp0 : 1; /* Write CBUS DMA ba`.d parity */N unsigned ka0902_iio$v_iocsr_pbr : 1; /* PCI bus reset */R unsigned ka0902_iio$v_iocsr_pir : 1; /* PCI interface reset */Y unsigned ka0902_iio$v_iocsr_encoi : 1; /* Enable NOACK,CUCERR,SYNC */W unsigned ka0902_iio$v_iocsr_epms : 1; /* Enable PCI memory space */Y unsigned ka0902_iio$v_iocsr_etlb : 1; /* Enable Translation buffer */Y unsigned ka0902_iio$v_iocsr_eacc :a. 1; /* Enable atomic CBUS cycles */X unsigned ka0902_iio$v_iocsr_ftlb : 1; /* Flush Translation buffer */X unsigned ka0902_iio$v_iocsr_ecpc : 1; /* Enable CBUS parity check */S unsigned ka0902_iio$v_iocsr_cir : 1; /* CBUS interface reset */N unsigned ka0902_iio$v_iocsr_epl : 1; /* Enable PCI lock */0 } ka0902_iio$r_iocsr_l_bits;1 } ka0902_iio$r_iocsr_fields_l_ol; __union b. {2 unsigned int ka0902_iio$l_iocsr_h; __struct {Y unsigned ka0902_iio$v_iocsr_cbbce : 1; /* Enable CBUS back-to-back */Q unsigned ka0902_iio$v_iocsr_trn : 3; /* T2 revision number */T unsigned ka0902_iio$v_iocsr_smvl : 3; /* State machine select */T unsigned ka0902_iio$v_iocsr_mba4 : 1; /* external MBA4 status */U unsigned ka0902_iio$v_iocsr_epr : 1; /* Enable passic.ve release */X unsigned ka0902_iio$v_iocsr_rdpe64 : 1; /* T4 parity: master read */W unsigned ka0902_iio$v_iocsr_adpe64 : 1; /* T4 parity: target rcv */Y unsigned ka0902_iio$v_iocsr_wdpe64 : 1; /* T4 parity: target write */W unsigned ka0902_iio$v_iocsr_cawwp1 : 1; /* CBUS C/A bad parity 1 */W unsigned ka0902_iio$v_iocsr_cawwp3 : 1; /* CBUS C/A bad parity 3 */U unsigned ka0902_iid.o$v_iocsr_dwwpo : 1; /* CBUS data parity odd */] unsigned ka0902_iio$v_iocsr_t24st : 1; /* clear: T2 compatability mode */V unsigned ka0902_iio$v_iocsr_ppc1 : 1; /* 2nd PIO buf is PPC buf */V unsigned ka0902_iio$v_iocsr_ppc2 : 1; /* 3rd PIO buf is PPC buf */V unsigned ka0902_iio$v_iocsr_stall : 1; /* enable DMA stall mode */: unsigned ka0902_iio$v_iocsr_fill4 : 1;P unsigned ka0902_e.iio$v_iocsr_prm : 1; /* PCI read multiple */Q unsigned ka0902_iio$v_iocsr_pwm : 1; /* PCI write multiple */X unsigned ka0902_iio$v_iocsr_fprdped : 1; /* PCI Force RDPE detect */W unsigned ka0902_iio$v_iocsr_fpadped : 1; /* PCI Force APE detect */X unsigned ka0902_iio$v_iocsr_fpwdped : 1; /* PCI Force RWPE detect */O unsigned ka0902_iio$v_iocsr_epnmi : 1; /* PCI enable NMI */O unsif.gned ka0902_iio$v_iocsr_epdti : 1; /* PCI enable DTI */Z unsigned ka0902_iio$v_iocsr_epsei : 1; /* PCI enable SERR interrupt */Z unsigned ka0902_iio$v_iocsr_eppei : 1; /* PCI enable PERR interrupt */Z unsigned ka0902_iio$v_iocsr_erdpc : 1; /* PCI enable RDPE interrupt */] unsigned ka0902_iio$v_iocsr_epadpc : 1; /* PCI enable addr parity int. */Z unsigned ka0902_iio$v_iocsr_ewdpc : 1; /* PCI enable WD g.parity int. */0 } ka0902_iio$r_iocsr_h_bits;1 } ka0902_iio$r_iocsr_fields_h_ol;( } ka0902_iio$r_iocsr_fields; } ka0902_iio$r_iocsr_ol;! char ka0902_iio$b_fill1 [24];N/* Cbus error register 1 */ __union {# __int64 ka0902_iio$q_cerr1; __struct { __union {2 unsigned int ka0902_iio$l_cerr1_l; __struct {W h. unsigned ka0902_iio$v_cerr1_ure : 1; /* Uncorrectable read error */S unsigned ka0902_iio$v_cerr1_nae : 1; /* No acknowledge error */a unsigned ka0902_iio$v_cerr1_cape : 1; /* Command address parity error even */i unsigned ka0902_iio$v_cerr1_mcape : 1; /* Missed command address parity error even */] unsigned ka0902_iio$v_cerr1_rwdpe : 1; /* Write data parity error even */d unsigned ka0902_iio$i.v_cerr1_mwrpe : 1; /* Missed write data parity error even */[ unsigned ka0902_iio$v_cerr1_rdpe : 1; /* Read data parity error even */c unsigned ka0902_iio$v_cerr1_mrdpe : 1; /* Missed read data parity error even */\ unsigned ka0902_iio$v_cerr1_cape0 : 1; /* C/A parity error longword 0 */\ unsigned ka0902_iio$v_cerr1_cape2 : 1; /* C/A parity error longword 2 */\ unsigned ka0902_iio$v_cerr1_dpe0 : 1; /*j. Data parity error longword 0 */\ unsigned ka0902_iio$v_cerr1_dpe2 : 1; /* Data parity error longword 2 */\ unsigned ka0902_iio$v_cerr1_dpe4 : 1; /* Data parity error longword 4 */\ unsigned ka0902_iio$v_cerr1_dpe6 : 1; /* Data parity error longword 6 */: unsigned ka0902_iio$v_cerr1_fill1 : 2;N unsigned ka0902_iio$v_cerr1_cwdp : 1; /* Command WDPE */N unsigned ka0902_iio$v_cerr1_bs k.e : 1; /* Bus sync error */N unsigned ka0902_iio$v_cerr1_ipfne : 1; /* Invalid PFN */; unsigned ka0902_iio$v_cerr1_fill2 : 13;0 } ka0902_iio$r_cerr1_l_bits;1 } ka0902_iio$r_cerr1_fields_l_ol; __union {2 unsigned int ka0902_iio$l_cerr1_h; __struct {: unsigned ka0902_iio$v_cerr1_fill3 : 8;U unsigned ka0902_iio$v_cerr1_cape1 : 1; /* C/A l.parity error LW1 */U unsigned ka0902_iio$v_cerr1_cape3 : 1; /* C/A parity error LW3 */U unsigned ka0902_iio$v_cerr1_dpe1 : 1; /* Data parity error LW1 */U unsigned ka0902_iio$v_cerr1_dpe3 : 1; /* Data parity error LW3 */U unsigned ka0902_iio$v_cerr1_dpe5 : 1; /* Data parity error LW5 */U unsigned ka0902_iio$v_cerr1_dpe7 : 1; /* Data parity error LW7 */; unsigned ka0902_iio$v_ce m.rr1_fill4 : 18;0 } ka0902_iio$r_cerr1_h_bits;1 } ka0902_iio$r_cerr1_fields_h_ol;( } ka0902_iio$r_cerr1_fields; } ka0902_iio$r_cerr1_ol;! char ka0902_iio$b_fill2 [24];N/* Cbus error register 2 */ __union {, unsigned __int64 ka0902_iio$q_cerr2; __struct {. unsigned int ka0902_iio$l_cerr2_l;. unsigned int ka0902_iio$l_cerr2_h;& } n.ka0902_iio$r_cerr2_bits;% } ka0902_iio$r_cerr2_overlay;! char ka0902_iio$b_fill3 [24];N/* Cbus error register 3 */ __union {, unsigned __int64 ka0902_iio$q_cerr3; __struct {/ unsigned ka0902_iio$v_cerr3_l : 32;/ unsigned ka0902_iio$v_cerr3_h : 32;& } ka0902_iio$r_cerr3_bits;% } ka0902_iio$r_cerr3_overlay;! char ka0902_iio$b_fill4 [24];N/* PCI error register 1 o. */ __union {# __int64 ka0902_iio$q_perr1; __struct { __union {2 unsigned int ka0902_iio$l_perr1_l; __struct {\ unsigned ka0902_iio$v_perr1_pwdpe : 1; /* PCI write data parity error */X unsigned ka0902_iio$v_perr1_pape : 1; /* PCI address parity error */[ unsigned ka0902_iio$v_perr1_prdpe : 1; /* PCI read data parity ep.rror */O unsigned ka0902_iio$v_perr1_ppe : 1; /* PCI parity error */O unsigned ka0902_iio$v_perr1_pse : 1; /* PCI system error */X unsigned ka0902_iio$v_perr1_pdte : 1; /* PCI device timeout error */U unsigned ka0902_iio$v_perr1_nmi : 1; /* Non-maskable interrupt */U unsigned ka0902_iio$v_perr1_ppcse : 1; /* Bad size on PPC xfer */^ unsigned ka0902_iio$v_perr1_wdpe64 : 1; /* Parq.ity: write data,T4 target */\ unsigned ka0902_iio$v_perr1_adpe64 : 1; /* Parity: address, T4 target */^ unsigned ka0902_iio$v_perr1_rdpe64 : 1; /* Parity: read data, T4 master */N unsigned ka0902_iio$v_perr1_ta : 1; /* Target abort */: unsigned ka0902_iio$v_perr1_fill1 : 4;V unsigned ka0902_iio$v_perr1_prdpe64 : 1; /* enable logging rdpe */V unsigned ka0902_iio$v_perr1_padpe64 : r.1; /* enable logging adpe */V unsigned ka0902_iio$v_perr1_pwdpe64 : 1; /* enable logging wdpe */P unsigned ka0902_iio$v_perr1_pta : 1; /* enable loggine TA */; unsigned ka0902_iio$v_perr1_fill2 : 12;0 } ka0902_iio$r_perr1_l_bits;1 } ka0902_iio$r_perr1_fields_l_ol; __union {2 unsigned int ka0902_iio$l_perr1_h; __struct {; unsigned ka0902_s.iio$v_perr1_fill3 : 32;0 } ka0902_iio$r_perr1_h_bits;1 } ka0902_iio$r_perr1_fields_h_ol;( } ka0902_iio$r_perr1_fields; } ka0902_iio$r_perr1_ol;! char ka0902_iio$b_fill5 [24];N/* PCI error register 2 */ __union {# __int64 ka0902_iio$q_perr2; __struct { __union {2 unsigned int ka0902_iio$l_perr2_l; __struct {Q t. unsigned ka0902_iio$v_perr2_pea : 32; /* PCI error address */0 } ka0902_iio$r_perr2_l_bits;1 } ka0902_iio$r_perr2_fields_l_ol; __union {2 unsigned int ka0902_iio$l_perr2_h; __struct {P unsigned ka0902_iio$v_perr2_pec : 5; /* PCI error command */; unsigned ka0902_iio$v_perr2_fill1 : 27;0 } ka0902_iio$r_perr2_h_bits;1 } ka0902 u._iio$r_perr2_fields_h_ol;( } ka0902_iio$r_perr2_fields; } ka0902_iio$r_perr2_ol;! char ka0902_iio$b_fill6 [24];N/* PCI special cycle register */ __union {+ unsigned __int64 ka0902_iio$q_pscm; __struct {. unsigned ka0902_iio$v_pscm_l : 32;. unsigned ka0902_iio$v_pscm_h : 32;% } ka0902_iio$r_pscm_bits;$ } ka0902_iio$r_pscm_overlay;! char ka0902_iio$b_fill7 v.[24];N/* High Address Extension register 1 */N/* Note extra bit for T4 */N/* */ __union {" __int64 ka0902_iio$q_hae1; __struct { __union {1 unsigned int ka0902_iio$l_hae1_l; __struct {U unsigned ka0902_iio$v_hae1_pua1 : 5; /* PCI upper address w.(T2) */^ unsigned ka0902_iio$v_hae1_pua_bit26 : 1; /* extra addr bit for T4 only */: unsigned ka0902_iio$v_hae1_fill1 : 26;/ } ka0902_iio$r_hae1_l_bits;0 } ka0902_iio$r_hae1_fields_l_ol; __union {1 unsigned int ka0902_iio$l_hae1_h; __struct {: unsigned ka0902_iio$v_hae1_fill2 : 32;/ } ka0902_iio$r_hae1_h_bits;0 } ka0902 x._iio$r_hae1_fields_h_ol;' } ka0902_iio$r_hae1_fields; } ka0902_iio$r_hae1_ol;! char ka0902_iio$b_fill8 [24];N/* High Address Extension register 2 */N/* Note 1 less bit for T4 */ __union {" __int64 ka0902_iio$q_hae2; __struct { __union {1 unsigned int ka0902_iio$l_hae2_l; __struct {P unsigned y. ka0902_iio$v_hae2_pua2 : 8; /* PCI upper address */P unsigned ka0902_iio$v_hae2_pua1 : 1; /* and 1 more for T2 */: unsigned ka0902_iio$v_hae2_fill1 : 23;/ } ka0902_iio$r_hae2_l_bits;0 } ka0902_iio$r_hae2_fields_l_ol; __union {1 unsigned int ka0902_iio$l_hae2_h; __struct {: unsigned ka0902_iio$v_hae2_fill2 : 32;/ } ka0902_iio$r_hae2_h_bi z.ts;0 } ka0902_iio$r_hae2_fields_h_ol;' } ka0902_iio$r_hae2_fields; } ka0902_iio$r_hae2_ol;! char ka0902_iio$b_fill9 [24];N/* PCI Hole base register */ __union {# __int64 ka0902_iio$q_hbase; __struct { __union {2 unsigned int ka0902_iio$l_hbase_l; __struct {T unsigned ka0902_iio$v_hbase_phea : 9; /* PCI hole end ad{.dress */: unsigned ka0902_iio$v_hbase_fill1 : 4;W unsigned ka0902_iio$v_hbase_phe1 : 1; /* PCI fixed hole enable 1 */N/* Note that although at first glance this seems */N/* incompatible with T2, the sense is the same - T4 */N/* merely allows subsets of 512-1mb */\ unsigned ka0902_iio$v_hbase_phe2 : 1; /* PCI programmable hole enable */V |. unsigned ka0902_iio$v_hbase_phsa : 9; /* PCI hole start address */R unsigned ka0902_iio$v_hbase_r0_ena : 1; /* enable region 0 */R unsigned ka0902_iio$v_hbase_r1_ena : 1; /* enable region 1 */R unsigned ka0902_iio$v_hbase_r2_ena : 1; /* enable region 2 */R unsigned ka0902_iio$v_hbase_r3_ena : 1; /* enable region 3 */R unsigned ka0902_iio$v_hbase_r4_ena : 1; /* enable region 4 */R }. unsigned ka0902_iio$v_hbase_r5_ena : 1; /* enable region 5 */R unsigned ka0902_iio$v_hbase_r6_ena : 1; /* enable region 6 */R unsigned ka0902_iio$v_hbase_r7_ena : 1; /* enable region 7 */0 } ka0902_iio$r_hbase_l_bits;1 } ka0902_iio$r_hbase_fields_l_ol; __union {2 unsigned int ka0902_iio$l_hbase_h; __struct {R unsigned ka0902_iio$v_hbase_r8_ena :~. 1; /* enable region 8 */R unsigned ka0902_iio$v_hbase_r9_ena : 1; /* enable region 9 */T unsigned ka0902_iio$v_hbase_r10_ena : 1; /* enable region 10 */S unsigned ka0902_iio$v_hbase_r11_ena : 1; /* enable region 11 */S unsigned ka0902_iio$v_hbase_r12_ena : 1; /* enable region 12 */S unsigned ka0902_iio$v_hbase_r13_ena : 1; /* enable region 13 */S unsigned ka0902_iio$v_hbase_r1 .4_ena : 1; /* enable region 14 */; unsigned ka0902_iio$v_hbase_fill2 : 25;0 } ka0902_iio$r_hbase_h_bits;1 } ka0902_iio$r_hbase_fields_h_ol;( } ka0902_iio$r_hbase_fields; } ka0902_iio$r_hbase_ol;" char ka0902_iio$b_fill10 [24];N/* PCI Window base register 1 */ __union {$ __int64 ka0902_iio$q_wbase1; __struct { __union {3 . unsigned int ka0902_iio$l_wbase1_l; __struct {X unsigned ka0902_iio$v_wbase1_pwea : 12; /* PCI window end address */; unsigned ka0902_iio$v_wbase1_fill1 : 5;X unsigned ka0902_iio$v_wbase1_ppe : 1; /* PCI peer-to-peer enabled */Z unsigned ka0902_iio$v_wbase1_sge : 1; /* PCI Scatter-Gather enabled */Q unsigned ka0902_iio$v_wbase1_pwe : 1; /* PCI window enable */Z . unsigned ka0902_iio$v_wbase1_pwsa : 12; /* PCI window start address */1 } ka0902_iio$r_wbase1_l_bits;2 } ka0902_iio$r_wbase1_fields_l_ol; __union {3 unsigned int ka0902_iio$l_wbase1_h; __struct {< unsigned ka0902_iio$v_wbase1_fill3 : 32;1 } ka0902_iio$r_wbase1_h_bits;2 } ka0902_iio$r_wbase1_fields_h_ol;) } ka0902_iio$r_wbase1_fields;! } .ka0902_iio$r_wbase1_ol;" char ka0902_iio$b_fill11 [24];N/* PCI Window mask register 1 */ __union {$ __int64 ka0902_iio$q_wmask1; __struct { __union {3 unsigned int ka0902_iio$l_wmask1_l; __struct {< unsigned ka0902_iio$v_wmask1_fill1 : 20;P unsigned ka0902_iio$v_wmask1_pwm : 11; /* PCI window mask */; unsigned ka0902_ .iio$v_wmask1_fill2 : 1;1 } ka0902_iio$r_wmask1_l_bits;2 } ka0902_iio$r_wmask1_fields_l_ol; __union {3 unsigned int ka0902_iio$l_wmask1_h; __struct {< unsigned ka0902_iio$v_wmask1_fill3 : 32;1 } ka0902_iio$r_wmask1_h_bits;2 } ka0902_iio$r_wmask1_fields_h_ol;) } ka0902_iio$r_wmask1_fields;! } ka0902_iio$r_wmask1_ol;" char ka0902_iio$b_ .fill12 [24];N/* PCI Translated Base register 1 */ __union {$ __int64 ka0902_iio$q_tbase1; __struct { __union {3 unsigned int ka0902_iio$l_tbase1_l; __struct {; unsigned ka0902_iio$v_tbase1_fill1 : 9;T unsigned ka0902_iio$v_tbase1_tba : 22; /* PCI Translated Base */; unsigned ka0902_iio$v_tbase1_fill2 : 1;1 . } ka0902_iio$r_tbase1_l_bits;2 } ka0902_iio$r_tbase1_fields_l_ol; __union {3 unsigned int ka0902_iio$l_tbase1_h; __struct {< unsigned ka0902_iio$v_tbase1_fill3 : 32;1 } ka0902_iio$r_tbase1_h_bits;2 } ka0902_iio$r_tbase1_fields_h_ol;) } ka0902_iio$r_tbase1_fields;! } ka0902_iio$r_tbase1_ol;" char ka0902_iio$b_fill13 [24];N/* PCI Window base register 2 . */ __union {$ __int64 ka0902_iio$q_wbase2; __struct { __union {3 unsigned int ka0902_iio$l_wbase2_l; __struct {X unsigned ka0902_iio$v_wbase2_pwea : 12; /* PCI window end address */; unsigned ka0902_iio$v_wbase2_fill1 : 5;X unsigned ka0902_iio$v_wbase2_ppe : 1; /* PCI peer-to-peer enabled */Z unsigned k .a0902_iio$v_wbase2_sge : 1; /* PCI Scatter-Gather enabled */Q unsigned ka0902_iio$v_wbase2_pwe : 1; /* PCI window enable */Z unsigned ka0902_iio$v_wbase2_pwsa : 12; /* PCI window start address */1 } ka0902_iio$r_wbase2_l_bits;2 } ka0902_iio$r_wbase2_fields_l_ol; __union {3 unsigned int ka0902_iio$l_wbase2_h; __struct {< unsigned ka0902_iio$v_wbase2_fill3 :. 32;1 } ka0902_iio$r_wbase2_h_bits;2 } ka0902_iio$r_wbase2_fields_h_ol;) } ka0902_iio$r_wbase2_fields;! } ka0902_iio$r_wbase2_ol;" char ka0902_iio$b_fill14 [24];N/* PCI Window mask register 2 */ __union {$ __int64 ka0902_iio$q_wmask2; __struct { __union {3 unsigned int ka0902_iio$l_wmask2_l; __struct {< . unsigned ka0902_iio$v_wmask2_fill1 : 20;P unsigned ka0902_iio$v_wmask2_pwm : 11; /* PCI window mask */; unsigned ka0902_iio$v_wmask2_fill2 : 1;1 } ka0902_iio$r_wmask2_l_bits;2 } ka0902_iio$r_wmask2_fields_l_ol; __union {3 unsigned int ka0902_iio$l_wmask2_h; __struct {< unsigned ka0902_iio$v_wmask2_fill3 : 32;1 } ka0902_iio$r_wmask2_.h_bits;2 } ka0902_iio$r_wmask2_fields_h_ol;) } ka0902_iio$r_wmask2_fields;! } ka0902_iio$r_wmask2_ol;" char ka0902_iio$b_fill15 [24];N/* PCI Translated Base register 2 */ __union {$ __int64 ka0902_iio$q_tbase2; __struct { __union {3 unsigned int ka0902_iio$l_tbase2_l; __struct {; unsigned ka0902_iio$v_tbase2_fill1 : 9;T . unsigned ka0902_iio$v_tbase2_tba : 22; /* PCI Translated Base */; unsigned ka0902_iio$v_tbase2_fill2 : 1;1 } ka0902_iio$r_tbase2_l_bits;2 } ka0902_iio$r_tbase2_fields_l_ol; __union {3 unsigned int ka0902_iio$l_tbase2_h; __struct {< unsigned ka0902_iio$v_tbase2_fill3 : 32;1 } ka0902_iio$r_tbase2_h_bits;2 } ka0902_iio$r_tba .se2_fields_h_ol;) } ka0902_iio$r_tbase2_fields;! } ka0902_iio$r_tbase2_ol;" char ka0902_iio$b_fill16 [24];N/* PCI TLB by-pass register */ __union {# __int64 ka0902_iio$q_tlbbr; __struct { __union {2 unsigned int ka0902_iio$l_tlbbr_l; __struct {R unsigned ka0902_iio$v_tlbbr_tlbbv : 1; /* TLB by-pass valid */R unsign .ed ka0902_iio$v_tlbbr_tlbbd : 18; /* TLB by-pass data */; unsigned ka0902_iio$v_tlbbr_fill1 : 13;0 } ka0902_iio$r_tlbbr_l_bits;1 } ka0902_iio$r_tlbbr_fields_l_ol; __union {2 unsigned int ka0902_iio$l_tlbbr_h; __struct {; unsigned ka0902_iio$v_tlbbr_fill2 : 32;0 } ka0902_iio$r_tlbbr_h_bits;1 } ka0902_iio$r_tlbbr_fields_h_ol;( } .ka0902_iio$r_tlbbr_fields; } ka0902_iio$r_tlbbr_ol;" char ka0902_iio$b_fill17 [24];N/* PCI Invalid Passive Release register */O/* for late T2 and T4, contains both IVR and passive release vector fields */ __union {# __int64 ka0902_iio$q_ivrpr; __struct { __union {2 unsigned int ka0902_iio$l_ivrpr_l; __struct {U unsigned ka0902_iio$v_ivrpr_prvect : 8; /* P .assive release vec */; unsigned ka0902_iio$v_ivrpr_fill1 : 24;0 } ka0902_iio$r_ivrpr_l_bits;1 } ka0902_iio$r_ivrpr_fields_l_ol; __union {2 unsigned int ka0902_iio$l_ivrpr_h; __struct {P unsigned ka0902_iio$v_ivrpr_ia : 18; /* Interrupt address */; unsigned ka0902_iio$v_ivrpr_fill2 : 14;0 } ka0902_iio$r_ivrpr_h_bits;1 } .ka0902_iio$r_ivrpr_fields_h_ol;( } ka0902_iio$r_ivrpr_fields; } ka0902_iio$r_ivrpr_ol;" char ka0902_iio$b_fill18 [24];N/* High Address Extension register 3 */ __union {" __int64 ka0902_iio$q_hae3; __struct { __union {1 unsigned int ka0902_iio$l_hae3_l; __struct {: unsigned ka0902_iio$v_hae3_fill1 : 30;< unsigned ka0902_iio$ .v_hae3_cfg_type : 2;/ } ka0902_iio$r_hae3_l_bits;0 } ka0902_iio$r_hae3_fields_l_ol; __union {1 unsigned int ka0902_iio$l_hae3_h; __struct {: unsigned ka0902_iio$v_hae3_fill2 : 32;/ } ka0902_iio$r_hae3_h_bits;0 } ka0902_iio$r_hae3_fields_h_ol;' } ka0902_iio$r_hae3_fields; } ka0902_iio$r_hae3_ol;# char ka0902_iio$b_fill180 [24];N/* H .igh Address Extension register 4 */ __union {" __int64 ka0902_iio$q_hae4; __struct { __union {1 unsigned int ka0902_iio$l_hae4_l; __struct {O unsigned ka0902_iio$v_hae4_pua : 2; /* PCI upper address */: unsigned ka0902_iio$v_hae4_fill1 : 30;/ } ka0902_iio$r_hae4_l_bits;0 } ka0902_iio$r_hae4_fields_l_ol; . __union {1 unsigned int ka0902_iio$l_hae4_h; __struct {: unsigned ka0902_iio$v_hae4_fill2 : 32;/ } ka0902_iio$r_hae4_h_bits;0 } ka0902_iio$r_hae4_fields_h_ol;' } ka0902_iio$r_hae4_fields; } ka0902_iio$r_hae4_ol;# char ka0902_iio$b_fill181 [24];N/* PCI Window base register 3 */N/* added for T4 . */ __union {$ __int64 ka0902_iio$q_wbase3; __struct { __union {3 unsigned int ka0902_iio$l_wbase3_l; __struct {X unsigned ka0902_iio$v_wbase3_pwea : 12; /* PCI window end address */W unsigned ka0902_iio$v_wbase3_ppe : 1; /* PCI peer-to-peer enable */; unsigned ka0902_iio$v_wbase3_fill1 : 5;Z unsigned ka0902_iio$v_wbase3_sge : . 1; /* PCI Scatter-Gather enabled */Q unsigned ka0902_iio$v_wbase3_pwe : 1; /* PCI window enable */Z unsigned ka0902_iio$v_wbase3_pwsa : 12; /* PCI window start address */1 } ka0902_iio$r_wbase3_l_bits;2 } ka0902_iio$r_wbase3_fields_l_ol; __union {3 unsigned int ka0902_iio$l_wbase3_h; __struct {< unsigned ka0902_iio$v_wbase3_fill3 : 32;1 . } ka0902_iio$r_wbase3_h_bits;2 } ka0902_iio$r_wbase3_fields_h_ol;) } ka0902_iio$r_wbase3_fields;! } ka0902_iio$r_wbase3_ol;# char ka0902_iio$b_fill182 [24];N/* PCI Window mask register 3 */N/* added for T4 */ __union {$ __int64 ka0902_iio$q_wmask3; __struct { __union {3 unsigned int ka0902_iio$l_ .wmask3_l; __struct {< unsigned ka0902_iio$v_wmask3_fill1 : 20;P unsigned ka0902_iio$v_wmask3_pwm : 11; /* PCI window mask */; unsigned ka0902_iio$v_wmask3_fill2 : 1;1 } ka0902_iio$r_wmask3_l_bits;2 } ka0902_iio$r_wmask3_fields_l_ol; __union {3 unsigned int ka0902_iio$l_wmask3_h; __struct {< unsigned ka0902_iio$v_wmas .k3_fill3 : 32;1 } ka0902_iio$r_wmask3_h_bits;2 } ka0902_iio$r_wmask3_fields_h_ol;) } ka0902_iio$r_wmask3_fields;! } ka0902_iio$r_wmask3_ol;# char ka0902_iio$b_fill183 [24];N/* PCI Translated Base register 3 */N/* added for T4 */ __union {$ __int64 ka0902_iio$q_tbase3; __struct { __union {3 . unsigned int ka0902_iio$l_tbase3_l; __struct {; unsigned ka0902_iio$v_tbase3_fill1 : 9;T unsigned ka0902_iio$v_tbase3_tba : 22; /* PCI Translated Base */; unsigned ka0902_iio$v_tbase3_fill2 : 1;1 } ka0902_iio$r_tbase3_l_bits;2 } ka0902_iio$r_tbase3_fields_l_ol; __union {3 unsigned int ka0902_iio$l_tbase3_h; __struct {< . unsigned ka0902_iio$v_tbase3_fill3 : 32;1 } ka0902_iio$r_tbase3_h_bits;2 } ka0902_iio$r_tbase3_fields_h_ol;) } ka0902_iio$r_tbase3_fields;! } ka0902_iio$r_tbase3_ol;# char ka0902_iio$b_fill184 [56];N/* TLB data register 0 */ __union {" __int64 ka0902_iio$q_tdr0; __struct { __union {1 unsigned int ka0902_iio$l_tdr0_l; . __struct {U unsigned ka0902_iio$v_tdr0_tlbtd0 : 18; /* Tag for TLB entry 0 */Q unsigned ka0902_iio$v_tdr0_tlbtd1 : 12; /* Extended for T4 */9 unsigned ka0902_iio$v_tdr0_fill1 : 2;/ } ka0902_iio$r_tdr0_l_bits;0 } ka0902_iio$r_tdr0_fields_l_ol; __union {1 unsigned int ka0902_iio$l_tdr0_h; __struct {S unsigned ka0902_ii .o$v_tdr0_tlbv0 : 1; /* Valid tag for TLB 0 */O unsigned ka0902_iio$v_tdr0_tlbpfn : 18; /* PFN for TLB 0 */: unsigned ka0902_iio$v_tdr0_fill2 : 13;/ } ka0902_iio$r_tdr0_h_bits;0 } ka0902_iio$r_tdr0_fields_h_ol;' } ka0902_iio$r_tdr0_fields; } ka0902_iio$r_tdr0_ol;" char ka0902_iio$b_fill19 [24];N/* TLB data register 1 */ __union {" .__int64 ka0902_iio$q_tdr1; __struct { __union {1 unsigned int ka0902_iio$l_tdr1_l; __struct {U unsigned ka0902_iio$v_tdr1_tlbtd0 : 18; /* Tag for TLB entry 0 */Q unsigned ka0902_iio$v_tdr1_tlbtd1 : 12; /* Extended for T4 */9 unsigned ka0902_iio$v_tdr1_fill1 : 2;/ } ka0902_iio$r_tdr1_l_bits;0 } ka0902_iio$r_tdr1_fields_l_ol; __unio .n {1 unsigned int ka0902_iio$l_tdr1_h; __struct {S unsigned ka0902_iio$v_tdr1_tlbv1 : 1; /* Valid tag for TLB 1 */O unsigned ka0902_iio$v_tdr1_tlbpfn : 18; /* PFN for TLB 1 */: unsigned ka0902_iio$v_tdr1_fill2 : 13;/ } ka0902_iio$r_tdr1_h_bits;0 } ka0902_iio$r_tdr1_fields_h_ol;' } ka0902_iio$r_tdr1_fields; } ka0902_iio$r_tdr1_ol;" char ka090 .2_iio$b_fill20 [24];N/* TLB data register 2 */ __union {" __int64 ka0902_iio$q_tdr2; __struct { __union {1 unsigned int ka0902_iio$l_tdr2_l; __struct {U unsigned ka0902_iio$v_tdr2_tlbtd0 : 18; /* Tag for TLB entry 0 */Q unsigned ka0902_iio$v_tdr2_tlbtd1 : 12; /* Extended for T4 */9 unsigned ka0902_iio$v_tdr2_fill1 . : 2;/ } ka0902_iio$r_tdr2_l_bits;0 } ka0902_iio$r_tdr2_fields_l_ol; __union {1 unsigned int ka0902_iio$l_tdr2_h; __struct {S unsigned ka0902_iio$v_tdr2_tlbv2 : 1; /* Valid tag for TLB 2 */O unsigned ka0902_iio$v_tdr2_tlbpfn : 18; /* PFN for TLB 2 */: unsigned ka0902_iio$v_tdr2_fill2 : 13;/ } ka0902_iio$r_tdr2_h_bits;0 . } ka0902_iio$r_tdr2_fields_h_ol;' } ka0902_iio$r_tdr2_fields; } ka0902_iio$r_tdr2_ol;" char ka0902_iio$b_fill21 [24];N/* TLB data register 3 */ __union {" __int64 ka0902_iio$q_tdr3; __struct { __union {1 unsigned int ka0902_iio$l_tdr3_l; __struct {U unsigned ka0902_iio$v_tdr3_tlbtd0 : 18; /* Tag for TLB entry 0 */Q . unsigned ka0902_iio$v_tdr3_tlbtd1 : 12; /* Extended for T4 */9 unsigned ka0902_iio$v_tdr3_fill1 : 2;/ } ka0902_iio$r_tdr3_l_bits;0 } ka0902_iio$r_tdr3_fields_l_ol; __union {1 unsigned int ka0902_iio$l_tdr3_h; __struct {S unsigned ka0902_iio$v_tdr3_tlbv3 : 1; /* Valid tag for TLB 3 */O unsigned ka0902_iio$v_tdr3_tlbpfn : 18; /* PFN for TLB 3 */ .: unsigned ka0902_iio$v_tdr3_fill2 : 13;/ } ka0902_iio$r_tdr3_h_bits;0 } ka0902_iio$r_tdr3_fields_h_ol;' } ka0902_iio$r_tdr3_fields; } ka0902_iio$r_tdr3_ol;" char ka0902_iio$b_fill22 [24];N/* TLB data register 4 */ __union {" __int64 ka0902_iio$q_tdr4; __struct { __union {1 unsigned int ka0902_iio$l_tdr4_l; . __struct {U unsigned ka0902_iio$v_tdr4_tlbtd0 : 18; /* Tag for TLB entry 0 */Q unsigned ka0902_iio$v_tdr4_tlbtd1 : 12; /* Extended for T4 */9 unsigned ka0902_iio$v_tdr4_fill1 : 2;/ } ka0902_iio$r_tdr4_l_bits;0 } ka0902_iio$r_tdr4_fields_l_ol; __union {1 unsigned int ka0902_iio$l_tdr4_h; __struct {S unsigned ka0902_iio$ .v_tdr4_tlbv4 : 1; /* Valid tag for TLB 4 */O unsigned ka0902_iio$v_tdr4_tlbpfn : 18; /* PFN for TLB 4 */: unsigned ka0902_iio$v_tdr4_fill2 : 13;/ } ka0902_iio$r_tdr4_h_bits;0 } ka0902_iio$r_tdr4_fields_h_ol;' } ka0902_iio$r_tdr4_fields; } ka0902_iio$r_tdr4_ol;" char ka0902_iio$b_fill23 [24];N/* TLB data register 5 */ __union {" __ .int64 ka0902_iio$q_tdr5; __struct { __union {1 unsigned int ka0902_iio$l_tdr5_l; __struct {U unsigned ka0902_iio$v_tdr5_tlbtd0 : 18; /* Tag for TLB entry 0 */Q unsigned ka0902_iio$v_tdr5_tlbtd1 : 12; /* Extended for T4 */9 unsigned ka0902_iio$v_tdr5_fill1 : 2;/ } ka0902_iio$r_tdr5_l_bits;0 } ka0902_iio$r_tdr5_fields_l_ol; __union . {1 unsigned int ka0902_iio$l_tdr5_h; __struct {S unsigned ka0902_iio$v_tdr5_tlbv5 : 1; /* Valid tag for TLB 5 */O unsigned ka0902_iio$v_tdr5_tlbpfn : 18; /* PFN for TLB 5 */: unsigned ka0902_iio$v_tdr5_fill2 : 13;/ } ka0902_iio$r_tdr5_h_bits;0 } ka0902_iio$r_tdr5_fields_h_ol;' } ka0902_iio$r_tdr5_fields; } ka0902_iio$r_tdr5_ol;" char ka0902_ .iio$b_fill24 [24];N/* TLB data register 6 */ __union {" __int64 ka0902_iio$q_tdr6; __struct { __union {1 unsigned int ka0902_iio$l_tdr6_l; __struct {U unsigned ka0902_iio$v_tdr6_tlbtd0 : 18; /* Tag for TLB entry 0 */Q unsigned ka0902_iio$v_tdr6_tlbtd1 : 12; /* Extended for T4 */9 unsigned ka0902_iio$v_tdr6_fill1 : . 2;/ } ka0902_iio$r_tdr6_l_bits;0 } ka0902_iio$r_tdr6_fields_l_ol; __union {1 unsigned int ka0902_iio$l_tdr6_h; __struct {S unsigned ka0902_iio$v_tdr6_tlbv6 : 1; /* Valid tag for TLB 6 */O unsigned ka0902_iio$v_tdr6_tlbpfn : 18; /* PFN for TLB 6 */: unsigned ka0902_iio$v_tdr6_fill2 : 13;/ } ka0902_iio$r_tdr6_h_bits;0 .} ka0902_iio$r_tdr6_fields_h_ol;' } ka0902_iio$r_tdr6_fields; } ka0902_iio$r_tdr6_ol;" char ka0902_iio$b_fill25 [24];N/* TLB data register 7 */ __union {" __int64 ka0902_iio$q_tdr7; __struct { __union {1 unsigned int ka0902_iio$l_tdr7_l; __struct {U unsigned ka0902_iio$v_tdr7_tlbtd0 : 18; /* Tag for TLB entry 0 */Q . unsigned ka0902_iio$v_tdr7_tlbtd1 : 12; /* Extended for T4 */9 unsigned ka0902_iio$v_tdr7_fill1 : 2;/ } ka0902_iio$r_tdr7_l_bits;0 } ka0902_iio$r_tdr7_fields_l_ol; __union {1 unsigned int ka0902_iio$l_tdr7_h; __struct {S unsigned ka0902_iio$v_tdr7_tlbv7 : 1; /* Valid tag for TLB 7 */O unsigned ka0902_iio$v_tdr7_tlbpfn : 18; /* PFN for TLB 7 */: . unsigned ka0902_iio$v_tdr7_fill2 : 13;/ } ka0902_iio$r_tdr7_h_bits;0 } ka0902_iio$r_tdr7_fields_h_ol;' } ka0902_iio$r_tdr7_fields; } ka0902_iio$r_tdr7_ol;" char ka0902_iio$b_fill26 [24];N/* PCI Window base register 4 */N/* added for T4 */ __union {$ __int64 ka0902_iio$q_wbase4; __struct {. __union {3 unsigned int ka0902_iio$l_wbase4_l; __struct {X unsigned ka0902_iio$v_wbase4_pwea : 12; /* PCI window end address */W unsigned ka0902_iio$v_wbase4_ppe : 1; /* PCI peer-to-peer enable */; unsigned ka0902_iio$v_wbase4_fill1 : 5;Z unsigned ka0902_iio$v_wbase4_sge : 1; /* PCI Scatter-Gather enabled */Q unsigned ka0902_iio$v_wbase4_pwe : 1; /* P .CI window enable */Z unsigned ka0902_iio$v_wbase4_pwsa : 12; /* PCI window start address */1 } ka0902_iio$r_wbase4_l_bits;2 } ka0902_iio$r_wbase4_fields_l_ol; __union {3 unsigned int ka0902_iio$l_wbase4_h; __struct {< unsigned ka0902_iio$v_wbase4_fill3 : 32;1 } ka0902_iio$r_wbase4_h_bits;2 } ka0902_iio$r_wbase4_fields_h_ol;) } .ka0902_iio$r_wbase4_fields;! } ka0902_iio$r_wbase4_ol;# char ka0902_iio$b_fill261 [24];N/* PCI Window mask register 4 */N/* added for T4 */ __union {$ __int64 ka0902_iio$q_wmask4; __struct { __union {3 unsigned int ka0902_iio$l_wmask4_l; __struct {< unsigned ka0902_iio$v_wmask4_fill1 : 2 .0;P unsigned ka0902_iio$v_wmask4_pwm : 11; /* PCI window mask */; unsigned ka0902_iio$v_wmask4_fill2 : 1;1 } ka0902_iio$r_wmask4_l_bits;2 } ka0902_iio$r_wmask4_fields_l_ol; __union {3 unsigned int ka0902_iio$l_wmask4_h; __struct {< unsigned ka0902_iio$v_wmask4_fill3 : 32;1 } ka0902_iio$r_wmask4_h_bits;2 } ka0902_iio$r_w .mask4_fields_h_ol;) } ka0902_iio$r_wmask4_fields;! } ka0902_iio$r_wmask4_ol;# char ka0902_iio$b_fill262 [24];N/* PCI Translated Base register 4 */N/* added for T4 */ __union {$ __int64 ka0902_iio$q_tbase4; __struct { __union {3 unsigned int ka0902_iio$l_tbase4_l; __struct {; unsi .gned ka0902_iio$v_tbase4_fill1 : 9;T unsigned ka0902_iio$v_tbase4_tba : 22; /* PCI Translated Base */; unsigned ka0902_iio$v_tbase4_fill2 : 1;1 } ka0902_iio$r_tbase4_l_bits;2 } ka0902_iio$r_tbase4_fields_l_ol; __union {3 unsigned int ka0902_iio$l_tbase4_h; __struct {< unsigned ka0902_iio$v_tbase4_fill3 : 32;1 } ka0902_iio$r_tbase4_h_bi .ts;2 } ka0902_iio$r_tbase4_fields_h_ol;) } ka0902_iio$r_tbase4_fields;! } ka0902_iio$r_tbase4_ol;# char ka0902_iio$b_fill263 [24];N/* PCI IC Interrupt Controller Address Indirection Register */N/* Load with offset of desired configuration register */N/* See ICIC spec for definition */ __union {! __int64 ka0902_iio$q_air; __struct { __un .ion {0 unsigned int ka0902_iio$l_air_l; __struct {9 unsigned ka0902_iio$v_air_fill2 : 32;. } ka0902_iio$r_air_l_bits;/ } ka0902_iio$r_air_fields_l_ol; __union {0 unsigned int ka0902_iio$l_air_h; __struct {9 unsigned ka0902_iio$v_air_fill3 : 32;. } ka0902_iio$r_air_h_bits;/ } ka0902_iio$r_air_fields_h_ol; .& } ka0902_iio$r_air_fields; } ka0902_iio$r_air_ol;# char ka0902_iio$b_fill264 [24];N/* PCI IC Interrupt Controller Vector Register */N/* Read to obtain the 8-bit interrupt vector. */N/* Write to cause an SEOI to the vector indicated by the low 6 bits. */ __union {$ __int64 ka0902_iio$q_vector; __struct { __union {3 unsigned int ka0902_iio$l_vector_l; . __struct {< unsigned ka0902_iio$v_vector_fill2 : 32;1 } ka0902_iio$r_vector_l_bits;2 } ka0902_iio$r_vector_fields_l_ol; __union {3 unsigned int ka0902_iio$l_vector_h; __struct {< unsigned ka0902_iio$v_vector_fill3 : 32;1 } ka0902_iio$r_vector_h_bits;2 } ka0902_iio$r_vector_fields_h_ol;) } ka0902_iio$r_vector_fi .elds;! } ka0902_iio$r_vector_ol;# char ka0902_iio$b_fill265 [24];N/* PCI IC Interrupt Controller Data Indirection Register */N/* Read or write DIR to access configuration register */N/* identified by AIR. See ICIC spec for details. */ __union {! __int64 ka0902_iio$q_dir; __struct { __union {0 unsigned int ka0902_iio$l_dir_l; __struct {9 . unsigned ka0902_iio$v_dir_fill2 : 32;. } ka0902_iio$r_dir_l_bits;/ } ka0902_iio$r_dir_fields_l_ol; __union {0 unsigned int ka0902_iio$l_dir_h; __struct {9 unsigned ka0902_iio$v_dir_fill3 : 32;. } ka0902_iio$r_dir_h_bits;/ } ka0902_iio$r_dir_fields_h_ol;& } ka0902_iio$r_dir_fields; } ka0902_iio$r_dir_ol;# char ka0902_iio$ .b_fill266 [24];N/* PCI IC Interrupt Controller setup register */N/* added for T3 and T4 */N/* See ICIC spec for definition */ __union {" __int64 ka0902_iio$q_icic; __struct { __union {1 unsigned int ka0902_iio$l_icic_l; __struct {X unsigned ka0902_iio$v_icic_flush_addr : 24; /* E .ISA flush address */N unsigned ka0902_iio$v_icic_enable : 1; /* Enable ICIC */O unsigned ka0902_iio$v_icic_clock : 1; /* Fast/slow clock */9 unsigned ka0902_iio$v_icic_fill2 : 6;/ } ka0902_iio$r_icic_l_bits;0 } ka0902_iio$r_icic_fields_l_ol; __union {1 unsigned int ka0902_iio$l_icic_h; __struct {: unsigned ka0902_iio$v_icic_fill3 : 3 .2;/ } ka0902_iio$r_icic_h_bits;0 } ka0902_iio$r_icic_fields_h_ol;' } ka0902_iio$r_icic_fields; } ka0902_iio$r_icic_ol;# char ka0902_iio$b_fill267 [24]; } KA0902_IIO; #if !defined(__VAXC)C#define ka0902_iio$q_iocsr ka0902_iio$r_iocsr_ol.ka0902_iio$q_iocsr#define ka0902_iio$l_iocsr_l ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$l_iocsr_l#define ka0902_iio$v_iocsr_en_lden ka0902_.iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocs\#r_l_bits.ka0902_iio$v_iocsr_en_lden#define ka0902_iio$v_iocsr_el ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l_b\its.ka0902_iio$v_iocsr_el#define ka0902_iio$v_iocsr_esmv ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l\_bits.ka0902_iio$v_iocsr_esmv#define ka0902_iio$v_iocsr_pdbp ka0902_iio$r_ioc.sr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l\_bits.ka0902_iio$v_iocsr_pdbp#define ka0902_iio$v_iocsr_pciprst0 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_ioc\%sr_l_bits.ka0902_iio$v_iocsr_pciprst0#define ka0902_iio$v_iocsr_pciprst1 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_ioc\%sr_l_bits.ka0902_iio$v_iocsr_pciprst1#define ka0902_iio$v_iocsr_int ka0902_ii.o$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l_\bits.ka0902_iio$v_iocsr_int#define ka0902_iio$v_iocsr_tlbee ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_\l_bits.ka0902_iio$v_iocsr_tlbee#define ka0902_iio$v_iocsr_cxack ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_\l_bits.ka0902_iio$v_iocsr_cxack#define ka0902_iio$v_iocsr_fill2 ka0902_iio$r_.iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_\l_bits.ka0902_iio$v_iocsr_fill2#define ka0902_iio$v_iocsr_exex ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l\_bits.ka0902_iio$v_iocsr_exex#define ka0902_iio$v_iocsr_fill3 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_\l_bits.ka0902_iio$v_iocsr_fill3#define ka0902_iio$v_iocsr_cawwp0 ka0902_iio$r_ioc.sr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr\!_l_bits.ka0902_iio$v_iocsr_cawwp0#define ka0902_iio$v_iocsr_cawwp2 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr\!_l_bits.ka0902_iio$v_iocsr_cawwp2#define ka0902_iio$v_iocsr_dwwpe ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_\l_bits.ka0902_iio$v_iocsr_dwwpe#define ka0902_iio$v_iocsr_mba5 ka0902_iio$r_ioc.sr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l\_bits.ka0902_iio$v_iocsr_mba5#define ka0902_iio$v_iocsr_mba6 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l\_bits.ka0902_iio$v_iocsr_mba6#define ka0902_iio$v_iocsr_mba7 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l\_bits.ka0902_iio$v_iocsr_mba7#define ka0902_iio$v_iocsr_pciprst3 ka0902_iio$r_iocsr_o.l.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_ioc\%sr_l_bits.ka0902_iio$v_iocsr_pciprst3#define ka0902_iio$v_iocsr_pciprst4 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_ioc\%sr_l_bits.ka0902_iio$v_iocsr_pciprst4#define ka0902_iio$v_iocsr_pdwwp1 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr\!_l_bits.ka0902_iio$v_iocsr_pdwwp1#define ka0902_iio$v_iocsr_pdwwp0 ka0902_iio.$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr\!_l_bits.ka0902_iio$v_iocsr_pdwwp0#define ka0902_iio$v_iocsr_pbr ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l_\bits.ka0902_iio$v_iocsr_pbr#define ka0902_iio$v_iocsr_pir ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l_\bits.ka0902_iio$v_iocsr_pir#define ka0902_iio$v_iocsr_encoi ka0902_iio$r_iocsr_.ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_\l_bits.ka0902_iio$v_iocsr_encoi#define ka0902_iio$v_iocsr_epms ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l\_bits.ka0902_iio$v_iocsr_epms#define ka0902_iio$v_iocsr_etlb ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l\_bits.ka0902_iio$v_iocsr_etlb#define ka0902_iio$v_iocsr_eacc ka0902_iio$r_iocsr_ol.ka09.02_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l\_bits.ka0902_iio$v_iocsr_eacc#define ka0902_iio$v_iocsr_ftlb ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l\_bits.ka0902_iio$v_iocsr_ftlb#define ka0902_iio$v_iocsr_ecpc ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l\_bits.ka0902_iio$v_iocsr_ecpc#define ka0902_iio$v_iocsr_cir ka0902_iio$r_iocsr_ol.ka0902_iio$r_.iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l_\bits.ka0902_iio$v_iocsr_cir#define ka0902_iio$v_iocsr_epl ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_l_ol.ka0902_iio$r_iocsr_l_\bits.ka0902_iio$v_iocsr_epl#define ka0902_iio$l_iocsr_h ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$l_iocsr_h#define ka0902_iio$v_iocsr_cbbce ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka.0902_iio$r_iocsr_\h_bits.ka0902_iio$v_iocsr_cbbce#define ka0902_iio$v_iocsr_trn ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_h_\bits.ka0902_iio$v_iocsr_trn#define ka0902_iio$v_iocsr_smvl ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_h\_bits.ka0902_iio$v_iocsr_smvl#define ka0902_iio$v_iocsr_mba4 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$.r_iocsr_h\_bits.ka0902_iio$v_iocsr_mba4#define ka0902_iio$v_iocsr_epr ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_h_\bits.ka0902_iio$v_iocsr_epr#define ka0902_iio$v_iocsr_rdpe64 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr\!_h_bits.ka0902_iio$v_iocsr_rdpe64#define ka0902_iio$v_iocsr_adpe64 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_io.csr\!_h_bits.ka0902_iio$v_iocsr_adpe64#define ka0902_iio$v_iocsr_wdpe64 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr\!_h_bits.ka0902_iio$v_iocsr_wdpe64#define ka0902_iio$v_iocsr_cawwp1 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr\!_h_bits.ka0902_iio$v_iocsr_cawwp1#define ka0902_iio$v_iocsr_cawwp3 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$.r_iocsr\!_h_bits.ka0902_iio$v_iocsr_cawwp3#define ka0902_iio$v_iocsr_dwwpo ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_\h_bits.ka0902_iio$v_iocsr_dwwpo#define ka0902_iio$v_iocsr_t24st ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_\h_bits.ka0902_iio$v_iocsr_t24st#define ka0902_iio$v_iocsr_ppc1 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_.iocsr_h\_bits.ka0902_iio$v_iocsr_ppc1#define ka0902_iio$v_iocsr_ppc2 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_h\_bits.ka0902_iio$v_iocsr_ppc2#define ka0902_iio$v_iocsr_stall ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_\h_bits.ka0902_iio$v_iocsr_stall#define ka0902_iio$v_iocsr_fill4 ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr._\h_bits.ka0902_iio$v_iocsr_fill4#define ka0902_iio$v_iocsr_prm ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_h_\bits.ka0902_iio$v_iocsr_prm#define ka0902_iio$v_iocsr_pwm ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_h_\bits.ka0902_iio$v_iocsr_pwm#define ka0902_iio$v_iocsr_fprdped ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocs\#r_h_bi.ts.ka0902_iio$v_iocsr_fprdped#define ka0902_iio$v_iocsr_fpadped ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocs\#r_h_bits.ka0902_iio$v_iocsr_fpadped#define ka0902_iio$v_iocsr_fpwdped ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocs\#r_h_bits.ka0902_iio$v_iocsr_fpwdped#define ka0902_iio$v_iocsr_epnmi ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr._\h_bits.ka0902_iio$v_iocsr_epnmi#define ka0902_iio$v_iocsr_epdti ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_\h_bits.ka0902_iio$v_iocsr_epdti#define ka0902_iio$v_iocsr_epsei ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_\h_bits.ka0902_iio$v_iocsr_epsei#define ka0902_iio$v_iocsr_eppei ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_\.h_bits.ka0902_iio$v_iocsr_eppei#define ka0902_iio$v_iocsr_erdpc ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_\h_bits.ka0902_iio$v_iocsr_erdpc#define ka0902_iio$v_iocsr_epadpc ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr\!_h_bits.ka0902_iio$v_iocsr_epadpc#define ka0902_iio$v_iocsr_ewdpc ka0902_iio$r_iocsr_ol.ka0902_iio$r_iocsr_fields.ka0902_iio$r_iocsr_fields_h_ol.ka0902_iio$r_iocsr_\.h_bits.ka0902_iio$v_iocsr_ewdpcC#define ka0902_iio$q_cerr1 ka0902_iio$r_cerr1_ol.ka0902_iio$q_cerr1#define ka0902_iio$l_cerr1_l ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$l_cerr1_l#define ka0902_iio$v_cerr1_ure ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_l_\bits.ka0902_iio$v_cerr1_ure#define ka0902_iio$v_cerr1_nae ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l._ol.ka0902_iio$r_cerr1_l_\bits.ka0902_iio$v_cerr1_nae#define ka0902_iio$v_cerr1_cape ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_l\_bits.ka0902_iio$v_cerr1_cape#define ka0902_iio$v_cerr1_mcape ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_\l_bits.ka0902_iio$v_cerr1_mcape#define ka0902_iio$v_cerr1_rwdpe ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka.0902_iio$r_cerr1_\l_bits.ka0902_iio$v_cerr1_rwdpe#define ka0902_iio$v_cerr1_mwrpe ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_\l_bits.ka0902_iio$v_cerr1_mwrpe#define ka0902_iio$v_cerr1_rdpe ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_l\_bits.ka0902_iio$v_cerr1_rdpe#define ka0902_iio$v_cerr1_mrdpe ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902._iio$r_cerr1_\l_bits.ka0902_iio$v_cerr1_mrdpe#define ka0902_iio$v_cerr1_cape0 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_\l_bits.ka0902_iio$v_cerr1_cape0#define ka0902_iio$v_cerr1_cape2 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_\l_bits.ka0902_iio$v_cerr1_cape2#define ka0902_iio$v_cerr1_dpe0 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_ii.o$r_cerr1_l\_bits.ka0902_iio$v_cerr1_dpe0#define ka0902_iio$v_cerr1_dpe2 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_l\_bits.ka0902_iio$v_cerr1_dpe2#define ka0902_iio$v_cerr1_dpe4 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_l\_bits.ka0902_iio$v_cerr1_dpe4#define ka0902_iio$v_cerr1_dpe6 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr.1_l\_bits.ka0902_iio$v_cerr1_dpe6#define ka0902_iio$v_cerr1_cwdp ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_l\_bits.ka0902_iio$v_cerr1_cwdp#define ka0902_iio$v_cerr1_bse ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_l_\bits.ka0902_iio$v_cerr1_bse#define ka0902_iio$v_cerr1_ipfne ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_l_ol.ka0902_iio$r_cerr1_\l_bi.ts.ka0902_iio$v_cerr1_ipfne#define ka0902_iio$l_cerr1_h ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_h_ol.ka0902_iio$l_cerr1_h#define ka0902_iio$v_cerr1_cape1 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_h_ol.ka0902_iio$r_cerr1_\h_bits.ka0902_iio$v_cerr1_cape1#define ka0902_iio$v_cerr1_cape3 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_h_ol.ka0902_iio$r_cerr1_\h_bits.ka0902_iio$v_cerr1_cape3#define ka.0902_iio$v_cerr1_dpe1 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_h_ol.ka0902_iio$r_cerr1_h\_bits.ka0902_iio$v_cerr1_dpe1#define ka0902_iio$v_cerr1_dpe3 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_h_ol.ka0902_iio$r_cerr1_h\_bits.ka0902_iio$v_cerr1_dpe3#define ka0902_iio$v_cerr1_dpe5 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_h_ol.ka0902_iio$r_cerr1_h\_bits.ka0902_iio$v_cerr1_dpe5#define ka0902_iio.$v_cerr1_dpe7 ka0902_iio$r_cerr1_ol.ka0902_iio$r_cerr1_fields.ka0902_iio$r_cerr1_fields_h_ol.ka0902_iio$r_cerr1_h\_bits.ka0902_iio$v_cerr1_dpe7H#define ka0902_iio$q_cerr2 ka0902_iio$r_cerr2_overlay.ka0902_iio$q_cerr2d#define ka0902_iio$l_cerr2_l ka0902_iio$r_cerr2_overlay.ka0902_iio$r_cerr2_bits.ka0902_iio$l_cerr2_ld#define ka0902_iio$l_cerr2_h ka0902_iio$r_cerr2_overlay.ka0902_iio$r_cerr2_bits.ka0902_iio$l_cerr2_hH#define ka0902_iio$q_cerr3 ka0902_iio$r_cerr3_overlay.ka0902_iio$q_cerr3d#defin.e ka0902_iio$v_cerr3_l ka0902_iio$r_cerr3_overlay.ka0902_iio$r_cerr3_bits.ka0902_iio$v_cerr3_ld#define ka0902_iio$v_cerr3_h ka0902_iio$r_cerr3_overlay.ka0902_iio$r_cerr3_bits.ka0902_iio$v_cerr3_hC#define ka0902_iio$q_perr1 ka0902_iio$r_perr1_ol.ka0902_iio$q_perr1#define ka0902_iio$l_perr1_l ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$l_perr1_l#define ka0902_iio$v_perr1_pwdpe ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l._ol.ka0902_iio$r_perr1_\l_bits.ka0902_iio$v_perr1_pwdpe#define ka0902_iio$v_perr1_pape ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_perr1_l\_bits.ka0902_iio$v_perr1_pape#define ka0902_iio$v_perr1_prdpe ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_perr1_\l_bits.ka0902_iio$v_perr1_prdpe#define ka0902_iio$v_perr1_ppe ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka.0902_iio$r_perr1_l_\bits.ka0902_iio$v_perr1_ppe#define ka0902_iio$v_perr1_pse ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_perr1_l_\bits.ka0902_iio$v_perr1_pse#define ka0902_iio$v_perr1_pdte ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_perr1_l\_bits.ka0902_iio$v_perr1_pdte#define ka0902_iio$v_perr1_nmi ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_p.err1_l_\bits.ka0902_iio$v_perr1_nmi#define ka0902_iio$v_perr1_ppcse ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_perr1_\l_bits.ka0902_iio$v_perr1_ppcse#define ka0902_iio$v_perr1_wdpe64 ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_perr1\!_l_bits.ka0902_iio$v_perr1_wdpe64#define ka0902_iio$v_perr1_adpe64 ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_pe.rr1\!_l_bits.ka0902_iio$v_perr1_adpe64#define ka0902_iio$v_perr1_rdpe64 ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_perr1\!_l_bits.ka0902_iio$v_perr1_rdpe64#define ka0902_iio$v_perr1_ta ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_perr1_l_b\its.ka0902_iio$v_perr1_ta#define ka0902_iio$v_perr1_prdpe64 ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_perr\.#1_l_bits.ka0902_iio$v_perr1_prdpe64#define ka0902_iio$v_perr1_padpe64 ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_perr\#1_l_bits.ka0902_iio$v_perr1_padpe64#define ka0902_iio$v_perr1_pwdpe64 ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r_perr\#1_l_bits.ka0902_iio$v_perr1_pwdpe64#define ka0902_iio$v_perr1_pta ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_l_ol.ka0902_iio$r._perr1_l_\bits.ka0902_iio$v_perr1_pta#define ka0902_iio$l_perr1_h ka0902_iio$r_perr1_ol.ka0902_iio$r_perr1_fields.ka0902_iio$r_perr1_fields_h_ol.ka0902_iio$l_perr1_hC#define ka0902_iio$q_perr2 ka0902_iio$r_perr2_ol.ka0902_iio$q_perr2#define ka0902_iio$l_perr2_l ka0902_iio$r_perr2_ol.ka0902_iio$r_perr2_fields.ka0902_iio$r_perr2_fields_l_ol.ka0902_iio$l_perr2_l#define ka0902_iio$v_perr2_pea ka0902_iio$r_perr2_ol.ka0902_iio$r_perr2_fields.ka0902_iio$r_perr2_fields_l_ol.ka0902_iio$r_perr2_l_\.bits.ka0902_iio$v_perr2_pea#define ka0902_iio$l_perr2_h ka0902_iio$r_perr2_ol.ka0902_iio$r_perr2_fields.ka0902_iio$r_perr2_fields_h_ol.ka0902_iio$l_perr2_h#define ka0902_iio$v_perr2_pec ka0902_iio$r_perr2_ol.ka0902_iio$r_perr2_fields.ka0902_iio$r_perr2_fields_h_ol.ka0902_iio$r_perr2_h_\bits.ka0902_iio$v_perr2_pecE#define ka0902_iio$q_pscm ka0902_iio$r_pscm_overlay.ka0902_iio$q_pscm`#define ka0902_iio$v_pscm_l ka0902_iio$r_pscm_overlay.ka0902_iio$r_pscm_bits.ka0902_iio$v_pscm_l`#define ka09.02_iio$v_pscm_h ka0902_iio$r_pscm_overlay.ka0902_iio$r_pscm_bits.ka0902_iio$v_pscm_h@#define ka0902_iio$q_hae1 ka0902_iio$r_hae1_ol.ka0902_iio$q_hae1{#define ka0902_iio$l_hae1_l ka0902_iio$r_hae1_ol.ka0902_iio$r_hae1_fields.ka0902_iio$r_hae1_fields_l_ol.ka0902_iio$l_hae1_l#define ka0902_iio$v_hae1_pua1 ka0902_iio$r_hae1_ol.ka0902_iio$r_hae1_fields.ka0902_iio$r_hae1_fields_l_ol.ka0902_iio$r_hae1_l_bits\.ka0902_iio$v_hae1_pua1#define ka0902_iio$v_hae1_pua_bit26 ka0902_iio$r_hae1_ol.ka0902_iio$.r_hae1_fields.ka0902_iio$r_hae1_fields_l_ol.ka0902_iio$r_hae1_l\!_bits.ka0902_iio$v_hae1_pua_bit26{#define ka0902_iio$l_hae1_h ka0902_iio$r_hae1_ol.ka0902_iio$r_hae1_fields.ka0902_iio$r_hae1_fields_h_ol.ka0902_iio$l_hae1_h@#define ka0902_iio$q_hae2 ka0902_iio$r_hae2_ol.ka0902_iio$q_hae2{#define ka0902_iio$l_hae2_l ka0902_iio$r_hae2_ol.ka0902_iio$r_hae2_fields.ka0902_iio$r_hae2_fields_l_ol.ka0902_iio$l_hae2_l#define ka0902_iio$v_hae2_pua2 ka0902_iio$r_hae2_ol.ka0902_iio$r_hae2_fields.ka0902_ii.o$r_hae2_fields_l_ol.ka0902_iio$r_hae2_l_bits\.ka0902_iio$v_hae2_pua2#define ka0902_iio$v_hae2_pua1 ka0902_iio$r_hae2_ol.ka0902_iio$r_hae2_fields.ka0902_iio$r_hae2_fields_l_ol.ka0902_iio$r_hae2_l_bits\.ka0902_iio$v_hae2_pua1{#define ka0902_iio$l_hae2_h ka0902_iio$r_hae2_ol.ka0902_iio$r_hae2_fields.ka0902_iio$r_hae2_fields_h_ol.ka0902_iio$l_hae2_hC#define ka0902_iio$q_hbase ka0902_iio$r_hbase_ol.ka0902_iio$q_hbase#define ka0902_iio$l_hbase_l ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields..ka0902_iio$r_hbase_fields_l_ol.ka0902_iio$l_hbase_l#define ka0902_iio$v_hbase_phea ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0902_iio$r_hbase_l\_bits.ka0902_iio$v_hbase_phea#define ka0902_iio$v_hbase_phe1 ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0902_iio$r_hbase_l\_bits.ka0902_iio$v_hbase_phe1#define ka0902_iio$v_hbase_phe2 ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0902_ii.o$r_hbase_l\_bits.ka0902_iio$v_hbase_phe2#define ka0902_iio$v_hbase_phsa ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0902_iio$r_hbase_l\_bits.ka0902_iio$v_hbase_phsa#define ka0902_iio$v_hbase_r0_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0902_iio$r_hbase\!_l_bits.ka0902_iio$v_hbase_r0_ena#define ka0902_iio$v_hbase_r1_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0902_iio$.r_hbase\!_l_bits.ka0902_iio$v_hbase_r1_ena#define ka0902_iio$v_hbase_r2_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0902_iio$r_hbase\!_l_bits.ka0902_iio$v_hbase_r2_ena#define ka0902_iio$v_hbase_r3_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0902_iio$r_hbase\!_l_bits.ka0902_iio$v_hbase_r3_ena#define ka0902_iio$v_hbase_r4_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0902_.iio$r_hbase\!_l_bits.ka0902_iio$v_hbase_r4_ena#define ka0902_iio$v_hbase_r5_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0902_iio$r_hbase\!_l_bits.ka0902_iio$v_hbase_r5_ena#define ka0902_iio$v_hbase_r6_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0902_iio$r_hbase\!_l_bits.ka0902_iio$v_hbase_r6_ena#define ka0902_iio$v_hbase_r7_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_l_ol.ka0.902_iio$r_hbase\!_l_bits.ka0902_iio$v_hbase_r7_ena#define ka0902_iio$l_hbase_h ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_h_ol.ka0902_iio$l_hbase_h#define ka0902_iio$v_hbase_r8_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_h_ol.ka0902_iio$r_hbase\!_h_bits.ka0902_iio$v_hbase_r8_ena#define ka0902_iio$v_hbase_r9_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_h_ol.ka0902_iio$r_hbase\!_h_bits.ka0902_iio.$v_hbase_r9_ena#define ka0902_iio$v_hbase_r10_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_h_ol.ka0902_iio$r_hbas\#e_h_bits.ka0902_iio$v_hbase_r10_ena#define ka0902_iio$v_hbase_r11_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_h_ol.ka0902_iio$r_hbas\#e_h_bits.ka0902_iio$v_hbase_r11_ena#define ka0902_iio$v_hbase_r12_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_h_ol.ka0902_iio$r_hbas\#e_h_bits.k.a0902_iio$v_hbase_r12_ena#define ka0902_iio$v_hbase_r13_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_h_ol.ka0902_iio$r_hbas\#e_h_bits.ka0902_iio$v_hbase_r13_ena#define ka0902_iio$v_hbase_r14_ena ka0902_iio$r_hbase_ol.ka0902_iio$r_hbase_fields.ka0902_iio$r_hbase_fields_h_ol.ka0902_iio$r_hbas\#e_h_bits.ka0902_iio$v_hbase_r14_enaF#define ka0902_iio$q_wbase1 ka0902_iio$r_wbase1_ol.ka0902_iio$q_wbase1#define ka0902_iio$l_wbase1_l ka0902_iio$r_wbase1_ol.ka0902_ii.o$r_wbase1_fields.ka0902_iio$r_wbase1_fields_l_ol.ka0902_iio$l_wbase1\_l#define ka0902_iio$v_wbase1_pwea ka0902_iio$r_wbase1_ol.ka0902_iio$r_wbase1_fields.ka0902_iio$r_wbase1_fields_l_ol.ka0902_iio$r_wba\#se1_l_bits.ka0902_iio$v_wbase1_pwea#define ka0902_iio$v_wbase1_ppe ka0902_iio$r_wbase1_ol.ka0902_iio$r_wbase1_fields.ka0902_iio$r_wbase1_fields_l_ol.ka0902_iio$r_wbas\!e1_l_bits.ka0902_iio$v_wbase1_ppe#define ka0902_iio$v_wbase1_sge ka0902_iio$r_wbase1_ol.ka0902_iio$r_wbase1_fields.ka0902._iio$r_wbase1_fields_l_ol.ka0902_iio$r_wbas\!e1_l_bits.ka0902_iio$v_wbase1_sge#define ka0902_iio$v_wbase1_pwe ka0902_iio$r_wbase1_ol.ka0902_iio$r_wbase1_fields.ka0902_iio$r_wbase1_fields_l_ol.ka0902_iio$r_wbas\!e1_l_bits.ka0902_iio$v_wbase1_pwe#define ka0902_iio$v_wbase1_pwsa ka0902_iio$r_wbase1_ol.ka0902_iio$r_wbase1_fields.ka0902_iio$r_wbase1_fields_l_ol.ka0902_iio$r_wba\#se1_l_bits.ka0902_iio$v_wbase1_pwsa#define ka0902_iio$l_wbase1_h ka0902_iio$r_wbase1_ol.ka0902_iio$r_wbase1_fields.ka.0902_iio$r_wbase1_fields_h_ol.ka0902_iio$l_wbase1\_hF#define ka0902_iio$q_wmask1 ka0902_iio$r_wmask1_ol.ka0902_iio$q_wmask1#define ka0902_iio$l_wmask1_l ka0902_iio$r_wmask1_ol.ka0902_iio$r_wmask1_fields.ka0902_iio$r_wmask1_fields_l_ol.ka0902_iio$l_wmask1\_l#define ka0902_iio$v_wmask1_pwm ka0902_iio$r_wmask1_ol.ka0902_iio$r_wmask1_fields.ka0902_iio$r_wmask1_fields_l_ol.ka0902_iio$r_wmas\!k1_l_bits.ka0902_iio$v_wmask1_pwm#define ka0902_iio$l_wmask1_h ka0902_iio$r_wmask1_ol.ka0902_iio$r_wmas.k1_fields.ka0902_iio$r_wmask1_fields_h_ol.ka0902_iio$l_wmask1\_hF#define ka0902_iio$q_tbase1 ka0902_iio$r_tbase1_ol.ka0902_iio$q_tbase1#define ka0902_iio$l_tbase1_l ka0902_iio$r_tbase1_ol.ka0902_iio$r_tbase1_fields.ka0902_iio$r_tbase1_fields_l_ol.ka0902_iio$l_tbase1\_l#define ka0902_iio$v_tbase1_tba ka0902_iio$r_tbase1_ol.ka0902_iio$r_tbase1_fields.ka0902_iio$r_tbase1_fields_l_ol.ka0902_iio$r_tbas\!e1_l_bits.ka0902_iio$v_tbase1_tba#define ka0902_iio$l_tbase1_h ka0902_iio$r_tbase1_ol.ka090.2_iio$r_tbase1_fields.ka0902_iio$r_tbase1_fields_h_ol.ka0902_iio$l_tbase1\_hF#define ka0902_iio$q_wbase2 ka0902_iio$r_wbase2_ol.ka0902_iio$q_wbase2#define ka0902_iio$l_wbase2_l ka0902_iio$r_wbase2_ol.ka0902_iio$r_wbase2_fields.ka0902_iio$r_wbase2_fields_l_ol.ka0902_iio$l_wbase2\_l#define ka0902_iio$v_wbase2_pwea ka0902_iio$r_wbase2_ol.ka0902_iio$r_wbase2_fields.ka0902_iio$r_wbase2_fields_l_ol.ka0902_iio$r_wba\#se2_l_bits.ka0902_iio$v_wbase2_pwea#define ka0902_iio$v_wbase2_ppe ka0902_iio$r._wbase2_ol.ka0902_iio$r_wbase2_fields.ka0902_iio$r_wbase2_fields_l_ol.ka0902_iio$r_wbas\!e2_l_bits.ka0902_iio$v_wbase2_ppe#define ka0902_iio$v_wbase2_sge ka0902_iio$r_wbase2_ol.ka0902_iio$r_wbase2_fields.ka0902_iio$r_wbase2_fields_l_ol.ka0902_iio$r_wbas\!e2_l_bits.ka0902_iio$v_wbase2_sge#define ka0902_iio$v_wbase2_pwe ka0902_iio$r_wbase2_ol.ka0902_iio$r_wbase2_fields.ka0902_iio$r_wbase2_fields_l_ol.ka0902_iio$r_wbas\!e2_l_bits.ka0902_iio$v_wbase2_pwe#define ka0902_iio$v_wbase2_pwsa ka0902_.iio$r_wbase2_ol.ka0902_iio$r_wbase2_fields.ka0902_iio$r_wbase2_fields_l_ol.ka0902_iio$r_wba\#se2_l_bits.ka0902_iio$v_wbase2_pwsa#define ka0902_iio$l_wbase2_h ka0902_iio$r_wbase2_ol.ka0902_iio$r_wbase2_fields.ka0902_iio$r_wbase2_fields_h_ol.ka0902_iio$l_wbase2\_hF#define ka0902_iio$q_wmask2 ka0902_iio$r_wmask2_ol.ka0902_iio$q_wmask2#define ka0902_iio$l_wmask2_l ka0902_iio$r_wmask2_ol.ka0902_iio$r_wmask2_fields.ka0902_iio$r_wmask2_fields_l_ol.ka0902_iio$l_wmask2\_l#define ka0902_iio$v_wmask.2_pwm ka0902_iio$r_wmask2_ol.ka0902_iio$r_wmask2_fields.ka0902_iio$r_wmask2_fields_l_ol.ka0902_iio$r_wmas\!k2_l_bits.ka0902_iio$v_wmask2_pwm#define ka0902_iio$l_wmask2_h ka0902_iio$r_wmask2_ol.ka0902_iio$r_wmask2_fields.ka0902_iio$r_wmask2_fields_h_ol.ka0902_iio$l_wmask2\_hF#define ka0902_iio$q_tbase2 ka0902_iio$r_tbase2_ol.ka0902_iio$q_tbase2#define ka0902_iio$l_tbase2_l ka0902_iio$r_tbase2_ol.ka0902_iio$r_tbase2_fields.ka0902_iio$r_tbase2_fields_l_ol.ka0902_iio$l_tbase2\_l#define ka0902._iio$v_tbase2_tba ka0902_iio$r_tbase2_ol.ka0902_iio$r_tbase2_fields.ka0902_iio$r_tbase2_fields_l_ol.ka0902_iio$r_tbas\!e2_l_bits.ka0902_iio$v_tbase2_tba#define ka0902_iio$l_tbase2_h ka0902_iio$r_tbase2_ol.ka0902_iio$r_tbase2_fields.ka0902_iio$r_tbase2_fields_h_ol.ka0902_iio$l_tbase2\_hC#define ka0902_iio$q_tlbbr ka0902_iio$r_tlbbr_ol.ka0902_iio$q_tlbbr#define ka0902_iio$l_tlbbr_l ka0902_iio$r_tlbbr_ol.ka0902_iio$r_tlbbr_fields.ka0902_iio$r_tlbbr_fields_l_ol.ka0902_iio$l_tlbbr_l#define ka09.02_iio$v_tlbbr_tlbbv ka0902_iio$r_tlbbr_ol.ka0902_iio$r_tlbbr_fields.ka0902_iio$r_tlbbr_fields_l_ol.ka0902_iio$r_tlbbr_\l_bits.ka0902_iio$v_tlbbr_tlbbv#define ka0902_iio$v_tlbbr_tlbbd ka0902_iio$r_tlbbr_ol.ka0902_iio$r_tlbbr_fields.ka0902_iio$r_tlbbr_fields_l_ol.ka0902_iio$r_tlbbr_\l_bits.ka0902_iio$v_tlbbr_tlbbd#define ka0902_iio$l_tlbbr_h ka0902_iio$r_tlbbr_ol.ka0902_iio$r_tlbbr_fields.ka0902_iio$r_tlbbr_fields_h_ol.ka0902_iio$l_tlbbr_hC#define ka0902_iio$q_ivrpr ka0902_iio$r_ivrpr_ol.ka0.902_iio$q_ivrpr#define ka0902_iio$l_ivrpr_l ka0902_iio$r_ivrpr_ol.ka0902_iio$r_ivrpr_fields.ka0902_iio$r_ivrpr_fields_l_ol.ka0902_iio$l_ivrpr_l#define ka0902_iio$v_ivrpr_prvect ka0902_iio$r_ivrpr_ol.ka0902_iio$r_ivrpr_fields.ka0902_iio$r_ivrpr_fields_l_ol.ka0902_iio$r_ivrpr\!_l_bits.ka0902_iio$v_ivrpr_prvect#define ka0902_iio$l_ivrpr_h ka0902_iio$r_ivrpr_ol.ka0902_iio$r_ivrpr_fields.ka0902_iio$r_ivrpr_fields_h_ol.ka0902_iio$l_ivrpr_h#define ka0902_iio$v_ivrpr_ia ka0902_iio$r_ivrpr_ol.ka0902._iio$r_ivrpr_fields.ka0902_iio$r_ivrpr_fields_h_ol.ka0902_iio$r_ivrpr_h_b\its.ka0902_iio$v_ivrpr_ia@#define ka0902_iio$q_hae3 ka0902_iio$r_hae3_ol.ka0902_iio$q_hae3{#define ka0902_iio$l_hae3_l ka0902_iio$r_hae3_ol.ka0902_iio$r_hae3_fields.ka0902_iio$r_hae3_fields_l_ol.ka0902_iio$l_hae3_l#define ka0902_iio$v_hae3_cfg_type ka0902_iio$r_hae3_ol.ka0902_iio$r_hae3_fields.ka0902_iio$r_hae3_fields_l_ol.ka0902_iio$r_hae3_l_\bits.ka0902_iio$v_hae3_cfg_type{#define ka0902_iio$l_hae3_h ka0902_iio$r_h.ae3_ol.ka0902_iio$r_hae3_fields.ka0902_iio$r_hae3_fields_h_ol.ka0902_iio$l_hae3_h@#define ka0902_iio$q_hae4 ka0902_iio$r_hae4_ol.ka0902_iio$q_hae4{#define ka0902_iio$l_hae4_l ka0902_iio$r_hae4_ol.ka0902_iio$r_hae4_fields.ka0902_iio$r_hae4_fields_l_ol.ka0902_iio$l_hae4_l#define ka0902_iio$v_hae4_pua ka0902_iio$r_hae4_ol.ka0902_iio$r_hae4_fields.ka0902_iio$r_hae4_fields_l_ol.ka0902_iio$r_hae4_l_bits.\ka0902_iio$v_hae4_pua{#define ka0902_iio$l_hae4_h ka0902_iio$r_hae4_ol.ka0902_iio$r_hae4_field.s.ka0902_iio$r_hae4_fields_h_ol.ka0902_iio$l_hae4_hF#define ka0902_iio$q_wbase3 ka0902_iio$r_wbase3_ol.ka0902_iio$q_wbase3#define ka0902_iio$l_wbase3_l ka0902_iio$r_wbase3_ol.ka0902_iio$r_wbase3_fields.ka0902_iio$r_wbase3_fields_l_ol.ka0902_iio$l_wbase3\_l#define ka0902_iio$v_wbase3_pwea ka0902_iio$r_wbase3_ol.ka0902_iio$r_wbase3_fields.ka0902_iio$r_wbase3_fields_l_ol.ka0902_iio$r_wba\#se3_l_bits.ka0902_iio$v_wbase3_pwea#define ka0902_iio$v_wbase3_ppe ka0902_iio$r_wbase3_ol.ka0902_iio$r_wb.ase3_fields.ka0902_iio$r_wbase3_fields_l_ol.ka0902_iio$r_wbas\!e3_l_bits.ka0902_iio$v_wbase3_ppe#define ka0902_iio$v_wbase3_sge ka0902_iio$r_wbase3_ol.ka0902_iio$r_wbase3_fields.ka0902_iio$r_wbase3_fields_l_ol.ka0902_iio$r_wbas\!e3_l_bits.ka0902_iio$v_wbase3_sge#define ka0902_iio$v_wbase3_pwe ka0902_iio$r_wbase3_ol.ka0902_iio$r_wbase3_fields.ka0902_iio$r_wbase3_fields_l_ol.ka0902_iio$r_wbas\!e3_l_bits.ka0902_iio$v_wbase3_pwe#define ka0902_iio$v_wbase3_pwsa ka0902_iio$r_wbase3_ol.ka0902_iio.$r_wbase3_fields.ka0902_iio$r_wbase3_fields_l_ol.ka0902_iio$r_wba\#se3_l_bits.ka0902_iio$v_wbase3_pwsa#define ka0902_iio$l_wbase3_h ka0902_iio$r_wbase3_ol.ka0902_iio$r_wbase3_fields.ka0902_iio$r_wbase3_fields_h_ol.ka0902_iio$l_wbase3\_hF#define ka0902_iio$q_wmask3 ka0902_iio$r_wmask3_ol.ka0902_iio$q_wmask3#define ka0902_iio$l_wmask3_l ka0902_iio$r_wmask3_ol.ka0902_iio$r_wmask3_fields.ka0902_iio$r_wmask3_fields_l_ol.ka0902_iio$l_wmask3\_l#define ka0902_iio$v_wmask3_pwm ka0902_iio$r_wmask3_.ol.ka0902_iio$r_wmask3_fields.ka0902_iio$r_wmask3_fields_l_ol.ka0902_iio$r_wmas\!k3_l_bits.ka0902_iio$v_wmask3_pwm#define ka0902_iio$l_wmask3_h ka0902_iio$r_wmask3_ol.ka0902_iio$r_wmask3_fields.ka0902_iio$r_wmask3_fields_h_ol.ka0902_iio$l_wmask3\_hF#define ka0902_iio$q_tbase3 ka0902_iio$r_tbase3_ol.ka0902_iio$q_tbase3#define ka0902_iio$l_tbase3_l ka0902_iio$r_tbase3_ol.ka0902_iio$r_tbase3_fields.ka0902_iio$r_tbase3_fields_l_ol.ka0902_iio$l_tbase3\_l#define ka0902_iio$v_tbase3_tba ka0902_i.io$r_tbase3_ol.ka0902_iio$r_tbase3_fields.ka0902_iio$r_tbase3_fields_l_ol.ka0902_iio$r_tbas\!e3_l_bits.ka0902_iio$v_tbase3_tba#define ka0902_iio$l_tbase3_h ka0902_iio$r_tbase3_ol.ka0902_iio$r_tbase3_fields.ka0902_iio$r_tbase3_fields_h_ol.ka0902_iio$l_tbase3\_h@#define ka0902_iio$q_tdr0 ka0902_iio$r_tdr0_ol.ka0902_iio$q_tdr0{#define ka0902_iio$l_tdr0_l ka0902_iio$r_tdr0_ol.ka0902_iio$r_tdr0_fields.ka0902_iio$r_tdr0_fields_l_ol.ka0902_iio$l_tdr0_l#define ka0902_iio$v_tdr0_tlbtd0 ka0902_iio$r_.tdr0_ol.ka0902_iio$r_tdr0_fields.ka0902_iio$r_tdr0_fields_l_ol.ka0902_iio$r_tdr0_l_bi\ts.ka0902_iio$v_tdr0_tlbtd0#define ka0902_iio$v_tdr0_tlbtd1 ka0902_iio$r_tdr0_ol.ka0902_iio$r_tdr0_fields.ka0902_iio$r_tdr0_fields_l_ol.ka0902_iio$r_tdr0_l_bi\ts.ka0902_iio$v_tdr0_tlbtd1{#define ka0902_iio$l_tdr0_h ka0902_iio$r_tdr0_ol.ka0902_iio$r_tdr0_fields.ka0902_iio$r_tdr0_fields_h_ol.ka0902_iio$l_tdr0_h#define ka0902_iio$v_tdr0_tlbv0 ka0902_iio$r_tdr0_ol.ka0902_iio$r_tdr0_fields.ka0902_iio$r_tdr0_fi.elds_h_ol.ka0902_iio$r_tdr0_h_bit\s.ka0902_iio$v_tdr0_tlbv0#define ka0902_iio$v_tdr0_tlbpfn ka0902_iio$r_tdr0_ol.ka0902_iio$r_tdr0_fields.ka0902_iio$r_tdr0_fields_h_ol.ka0902_iio$r_tdr0_h_bi\ts.ka0902_iio$v_tdr0_tlbpfn@#define ka0902_iio$q_tdr1 ka0902_iio$r_tdr1_ol.ka0902_iio$q_tdr1{#define ka0902_iio$l_tdr1_l ka0902_iio$r_tdr1_ol.ka0902_iio$r_tdr1_fields.ka0902_iio$r_tdr1_fields_l_ol.ka0902_iio$l_tdr1_l#define ka0902_iio$v_tdr1_tlbtd0 ka0902_iio$r_tdr1_ol.ka0902_iio$r_tdr1_fields.ka0902_.iio$r_tdr1_fields_l_ol.ka0902_iio$r_tdr1_l_bi\ts.ka0902_iio$v_tdr1_tlbtd0#define ka0902_iio$v_tdr1_tlbtd1 ka0902_iio$r_tdr1_ol.ka0902_iio$r_tdr1_fields.ka0902_iio$r_tdr1_fields_l_ol.ka0902_iio$r_tdr1_l_bi\ts.ka0902_iio$v_tdr1_tlbtd1{#define ka0902_iio$l_tdr1_h ka0902_iio$r_tdr1_ol.ka0902_iio$r_tdr1_fields.ka0902_iio$r_tdr1_fields_h_ol.ka0902_iio$l_tdr1_h#define ka0902_iio$v_tdr1_tlbv1 ka0902_iio$r_tdr1_ol.ka0902_iio$r_tdr1_fields.ka0902_iio$r_tdr1_fields_h_ol.ka0902_iio$r_tdr1_h_bit\s.ka/0902_iio$v_tdr1_tlbv1#define ka0902_iio$v_tdr1_tlbpfn ka0902_iio$r_tdr1_ol.ka0902_iio$r_tdr1_fields.ka0902_iio$r_tdr1_fields_h_ol.ka0902_iio$r_tdr1_h_bi\ts.ka0902_iio$v_tdr1_tlbpfn@#define ka0902_iio$q_tdr2 ka0902_iio$r_tdr2_ol.ka0902_iio$q_tdr2{#define ka0902_iio$l_tdr2_l ka0902_iio$r_tdr2_ol.ka0902_iio$r_tdr2_fields.ka0902_iio$r_tdr2_fields_l_ol.ka0902_iio$l_tdr2_l#define ka0902_iio$v_tdr2_tlbtd0 ka0902_iio$r_tdr2_ol.ka0902_iio$r_tdr2_fields.ka0902_iio$r_tdr2_fields_l_ol.ka0902_iio$r_tdr2/_l_bi\ts.ka0902_iio$v_tdr2_tlbtd0#define ka0902_iio$v_tdr2_tlbtd1 ka0902_iio$r_tdr2_ol.ka0902_iio$r_tdr2_fields.ka0902_iio$r_tdr2_fields_l_ol.ka0902_iio$r_tdr2_l_bi\ts.ka0902_iio$v_tdr2_tlbtd1{#define ka0902_iio$l_tdr2_h ka0902_iio$r_tdr2_ol.ka0902_iio$r_tdr2_fields.ka0902_iio$r_tdr2_fields_h_ol.ka0902_iio$l_tdr2_h#define ka0902_iio$v_tdr2_tlbv2 ka0902_iio$r_tdr2_ol.ka0902_iio$r_tdr2_fields.ka0902_iio$r_tdr2_fields_h_ol.ka0902_iio$r_tdr2_h_bit\s.ka0902_iio$v_tdr2_tlbv2#define ka0902_i/io$v_tdr2_tlbpfn ka0902_iio$r_tdr2_ol.ka0902_iio$r_tdr2_fields.ka0902_iio$r_tdr2_fields_h_ol.ka0902_iio$r_tdr2_h_bi\ts.ka0902_iio$v_tdr2_tlbpfn@#define ka0902_iio$q_tdr3 ka0902_iio$r_tdr3_ol.ka0902_iio$q_tdr3{#define ka0902_iio$l_tdr3_l ka0902_iio$r_tdr3_ol.ka0902_iio$r_tdr3_fields.ka0902_iio$r_tdr3_fields_l_ol.ka0902_iio$l_tdr3_l#define ka0902_iio$v_tdr3_tlbtd0 ka0902_iio$r_tdr3_ol.ka0902_iio$r_tdr3_fields.ka0902_iio$r_tdr3_fields_l_ol.ka0902_iio$r_tdr3_l_bi\ts.ka0902_iio$v_tdr3_tlbtd0#d/efine ka0902_iio$v_tdr3_tlbtd1 ka0902_iio$r_tdr3_ol.ka0902_iio$r_tdr3_fields.ka0902_iio$r_tdr3_fields_l_ol.ka0902_iio$r_tdr3_l_bi\ts.ka0902_iio$v_tdr3_tlbtd1{#define ka0902_iio$l_tdr3_h ka0902_iio$r_tdr3_ol.ka0902_iio$r_tdr3_fields.ka0902_iio$r_tdr3_fields_h_ol.ka0902_iio$l_tdr3_h#define ka0902_iio$v_tdr3_tlbv3 ka0902_iio$r_tdr3_ol.ka0902_iio$r_tdr3_fields.ka0902_iio$r_tdr3_fields_h_ol.ka0902_iio$r_tdr3_h_bit\s.ka0902_iio$v_tdr3_tlbv3#define ka0902_iio$v_tdr3_tlbpfn ka0902_iio$r_tdr3_ol.ka/0902_iio$r_tdr3_fields.ka0902_iio$r_tdr3_fields_h_ol.ka0902_iio$r_tdr3_h_bi\ts.ka0902_iio$v_tdr3_tlbpfn@#define ka0902_iio$q_tdr4 ka0902_iio$r_tdr4_ol.ka0902_iio$q_tdr4{#define ka0902_iio$l_tdr4_l ka0902_iio$r_tdr4_ol.ka0902_iio$r_tdr4_fields.ka0902_iio$r_tdr4_fields_l_ol.ka0902_iio$l_tdr4_l#define ka0902_iio$v_tdr4_tlbtd0 ka0902_iio$r_tdr4_ol.ka0902_iio$r_tdr4_fields.ka0902_iio$r_tdr4_fields_l_ol.ka0902_iio$r_tdr4_l_bi\ts.ka0902_iio$v_tdr4_tlbtd0#define ka0902_iio$v_tdr4_tlbtd1 ka0902_ii/o$r_tdr4_ol.ka0902_iio$r_tdr4_fields.ka0902_iio$r_tdr4_fields_l_ol.ka0902_iio$r_tdr4_l_bi\ts.ka0902_iio$v_tdr4_tlbtd1{#define ka0902_iio$l_tdr4_h ka0902_iio$r_tdr4_ol.ka0902_iio$r_tdr4_fields.ka0902_iio$r_tdr4_fields_h_ol.ka0902_iio$l_tdr4_h#define ka0902_iio$v_tdr4_tlbv4 ka0902_iio$r_tdr4_ol.ka0902_iio$r_tdr4_fields.ka0902_iio$r_tdr4_fields_h_ol.ka0902_iio$r_tdr4_h_bit\s.ka0902_iio$v_tdr4_tlbv4#define ka0902_iio$v_tdr4_tlbpfn ka0902_iio$r_tdr4_ol.ka0902_iio$r_tdr4_fields.ka0902_iio$r_tdr4/_fields_h_ol.ka0902_iio$r_tdr4_h_bi\ts.ka0902_iio$v_tdr4_tlbpfn@#define ka0902_iio$q_tdr5 ka0902_iio$r_tdr5_ol.ka0902_iio$q_tdr5{#define ka0902_iio$l_tdr5_l ka0902_iio$r_tdr5_ol.ka0902_iio$r_tdr5_fields.ka0902_iio$r_tdr5_fields_l_ol.ka0902_iio$l_tdr5_l#define ka0902_iio$v_tdr5_tlbtd0 ka0902_iio$r_tdr5_ol.ka0902_iio$r_tdr5_fields.ka0902_iio$r_tdr5_fields_l_ol.ka0902_iio$r_tdr5_l_bi\ts.ka0902_iio$v_tdr5_tlbtd0#define ka0902_iio$v_tdr5_tlbtd1 ka0902_iio$r_tdr5_ol.ka0902_iio$r_tdr5_fields.ka0/902_iio$r_tdr5_fields_l_ol.ka0902_iio$r_tdr5_l_bi\ts.ka0902_iio$v_tdr5_tlbtd1{#define ka0902_iio$l_tdr5_h ka0902_iio$r_tdr5_ol.ka0902_iio$r_tdr5_fields.ka0902_iio$r_tdr5_fields_h_ol.ka0902_iio$l_tdr5_h#define ka0902_iio$v_tdr5_tlbv5 ka0902_iio$r_tdr5_ol.ka0902_iio$r_tdr5_fields.ka0902_iio$r_tdr5_fields_h_ol.ka0902_iio$r_tdr5_h_bit\s.ka0902_iio$v_tdr5_tlbv5#define ka0902_iio$v_tdr5_tlbpfn ka0902_iio$r_tdr5_ol.ka0902_iio$r_tdr5_fields.ka0902_iio$r_tdr5_fields_h_ol.ka0902_iio$r_tdr5_h_bi\ts/.ka0902_iio$v_tdr5_tlbpfn@#define ka0902_iio$q_tdr6 ka0902_iio$r_tdr6_ol.ka0902_iio$q_tdr6{#define ka0902_iio$l_tdr6_l ka0902_iio$r_tdr6_ol.ka0902_iio$r_tdr6_fields.ka0902_iio$r_tdr6_fields_l_ol.ka0902_iio$l_tdr6_l#define ka0902_iio$v_tdr6_tlbtd0 ka0902_iio$r_tdr6_ol.ka0902_iio$r_tdr6_fields.ka0902_iio$r_tdr6_fields_l_ol.ka0902_iio$r_tdr6_l_bi\ts.ka0902_iio$v_tdr6_tlbtd0#define ka0902_iio$v_tdr6_tlbtd1 ka0902_iio$r_tdr6_ol.ka0902_iio$r_tdr6_fields.ka0902_iio$r_tdr6_fields_l_ol.ka0902_iio$r_ /tdr6_l_bi\ts.ka0902_iio$v_tdr6_tlbtd1{#define ka0902_iio$l_tdr6_h ka0902_iio$r_tdr6_ol.ka0902_iio$r_tdr6_fields.ka0902_iio$r_tdr6_fields_h_ol.ka0902_iio$l_tdr6_h#define ka0902_iio$v_tdr6_tlbv6 ka0902_iio$r_tdr6_ol.ka0902_iio$r_tdr6_fields.ka0902_iio$r_tdr6_fields_h_ol.ka0902_iio$r_tdr6_h_bit\s.ka0902_iio$v_tdr6_tlbv6#define ka0902_iio$v_tdr6_tlbpfn ka0902_iio$r_tdr6_ol.ka0902_iio$r_tdr6_fields.ka0902_iio$r_tdr6_fields_h_ol.ka0902_iio$r_tdr6_h_bi\ts.ka0902_iio$v_tdr6_tlbpfn@#define ka09 /02_iio$q_tdr7 ka0902_iio$r_tdr7_ol.ka0902_iio$q_tdr7{#define ka0902_iio$l_tdr7_l ka0902_iio$r_tdr7_ol.ka0902_iio$r_tdr7_fields.ka0902_iio$r_tdr7_fields_l_ol.ka0902_iio$l_tdr7_l#define ka0902_iio$v_tdr7_tlbtd0 ka0902_iio$r_tdr7_ol.ka0902_iio$r_tdr7_fields.ka0902_iio$r_tdr7_fields_l_ol.ka0902_iio$r_tdr7_l_bi\ts.ka0902_iio$v_tdr7_tlbtd0#define ka0902_iio$v_tdr7_tlbtd1 ka0902_iio$r_tdr7_ol.ka0902_iio$r_tdr7_fields.ka0902_iio$r_tdr7_fields_l_ol.ka0902_iio$r_tdr7_l_bi\ts.ka0902_iio$v_tdr7_tlbtd1 /{#define ka0902_iio$l_tdr7_h ka0902_iio$r_tdr7_ol.ka0902_iio$r_tdr7_fields.ka0902_iio$r_tdr7_fields_h_ol.ka0902_iio$l_tdr7_h#define ka0902_iio$v_tdr7_tlbv7 ka0902_iio$r_tdr7_ol.ka0902_iio$r_tdr7_fields.ka0902_iio$r_tdr7_fields_h_ol.ka0902_iio$r_tdr7_h_bit\s.ka0902_iio$v_tdr7_tlbv7#define ka0902_iio$v_tdr7_tlbpfn ka0902_iio$r_tdr7_ol.ka0902_iio$r_tdr7_fields.ka0902_iio$r_tdr7_fields_h_ol.ka0902_iio$r_tdr7_h_bi\ts.ka0902_iio$v_tdr7_tlbpfnF#define ka0902_iio$q_wbase4 ka0902_iio$r_wbase4_ol.k /a0902_iio$q_wbase4#define ka0902_iio$l_wbase4_l ka0902_iio$r_wbase4_ol.ka0902_iio$r_wbase4_fields.ka0902_iio$r_wbase4_fields_l_ol.ka0902_iio$l_wbase4\_l#define ka0902_iio$v_wbase4_pwea ka0902_iio$r_wbase4_ol.ka0902_iio$r_wbase4_fields.ka0902_iio$r_wbase4_fields_l_ol.ka0902_iio$r_wba\#se4_l_bits.ka0902_iio$v_wbase4_pwea#define ka0902_iio$v_wbase4_ppe ka0902_iio$r_wbase4_ol.ka0902_iio$r_wbase4_fields.ka0902_iio$r_wbase4_fields_l_ol.ka0902_iio$r_wbas\!e4_l_bits.ka0902_iio$v_wbase4_ppe#defin /e ka0902_iio$v_wbase4_sge ka0902_iio$r_wbase4_ol.ka0902_iio$r_wbase4_fields.ka0902_iio$r_wbase4_fields_l_ol.ka0902_iio$r_wbas\!e4_l_bits.ka0902_iio$v_wbase4_sge#define ka0902_iio$v_wbase4_pwe ka0902_iio$r_wbase4_ol.ka0902_iio$r_wbase4_fields.ka0902_iio$r_wbase4_fields_l_ol.ka0902_iio$r_wbas\!e4_l_bits.ka0902_iio$v_wbase4_pwe#define ka0902_iio$v_wbase4_pwsa ka0902_iio$r_wbase4_ol.ka0902_iio$r_wbase4_fields.ka0902_iio$r_wbase4_fields_l_ol.ka0902_iio$r_wba\#se4_l_bits.ka0902_iio$v_wbase4_pwsa/#define ka0902_iio$l_wbase4_h ka0902_iio$r_wbase4_ol.ka0902_iio$r_wbase4_fields.ka0902_iio$r_wbase4_fields_h_ol.ka0902_iio$l_wbase4\_hF#define ka0902_iio$q_wmask4 ka0902_iio$r_wmask4_ol.ka0902_iio$q_wmask4#define ka0902_iio$l_wmask4_l ka0902_iio$r_wmask4_ol.ka0902_iio$r_wmask4_fields.ka0902_iio$r_wmask4_fields_l_ol.ka0902_iio$l_wmask4\_l#define ka0902_iio$v_wmask4_pwm ka0902_iio$r_wmask4_ol.ka0902_iio$r_wmask4_fields.ka0902_iio$r_wmask4_fields_l_ol.ka0902_iio$r_wmas\!k4_l_bits.ka0902_iio$v_w/mask4_pwm#define ka0902_iio$l_wmask4_h ka0902_iio$r_wmask4_ol.ka0902_iio$r_wmask4_fields.ka0902_iio$r_wmask4_fields_h_ol.ka0902_iio$l_wmask4\_hF#define ka0902_iio$q_tbase4 ka0902_iio$r_tbase4_ol.ka0902_iio$q_tbase4#define ka0902_iio$l_tbase4_l ka0902_iio$r_tbase4_ol.ka0902_iio$r_tbase4_fields.ka0902_iio$r_tbase4_fields_l_ol.ka0902_iio$l_tbase4\_l#define ka0902_iio$v_tbase4_tba ka0902_iio$r_tbase4_ol.ka0902_iio$r_tbase4_fields.ka0902_iio$r_tbase4_fields_l_ol.ka0902_iio$r_tbas\!e4_l_bits.ka/0902_iio$v_tbase4_tba#define ka0902_iio$l_tbase4_h ka0902_iio$r_tbase4_ol.ka0902_iio$r_tbase4_fields.ka0902_iio$r_tbase4_fields_h_ol.ka0902_iio$l_tbase4\_h=#define ka0902_iio$q_air ka0902_iio$r_air_ol.ka0902_iio$q_airv#define ka0902_iio$l_air_l ka0902_iio$r_air_ol.ka0902_iio$r_air_fields.ka0902_iio$r_air_fields_l_ol.ka0902_iio$l_air_lv#define ka0902_iio$l_air_h ka0902_iio$r_air_ol.ka0902_iio$r_air_fields.ka0902_iio$r_air_fields_h_ol.ka0902_iio$l_air_hF#define ka0902_iio$q_vector ka0902_iio$r/_vector_ol.ka0902_iio$q_vector#define ka0902_iio$l_vector_l ka0902_iio$r_vector_ol.ka0902_iio$r_vector_fields.ka0902_iio$r_vector_fields_l_ol.ka0902_iio$l_vector\_l#define ka0902_iio$l_vector_h ka0902_iio$r_vector_ol.ka0902_iio$r_vector_fields.ka0902_iio$r_vector_fields_h_ol.ka0902_iio$l_vector\_h=#define ka0902_iio$q_dir ka0902_iio$r_dir_ol.ka0902_iio$q_dirv#define ka0902_iio$l_dir_l ka0902_iio$r_dir_ol.ka0902_iio$r_dir_fields.ka0902_iio$r_dir_fields_l_ol.ka0902_iio$l_dir_lv#define ka0902/_iio$l_dir_h ka0902_iio$r_dir_ol.ka0902_iio$r_dir_fields.ka0902_iio$r_dir_fields_h_ol.ka0902_iio$l_dir_h@#define ka0902_iio$q_icic ka0902_iio$r_icic_ol.ka0902_iio$q_icic{#define ka0902_iio$l_icic_l ka0902_iio$r_icic_ol.ka0902_iio$r_icic_fields.ka0902_iio$r_icic_fields_l_ol.ka0902_iio$l_icic_l#define ka0902_iio$v_icic_flush_addr ka0902_iio$r_icic_ol.ka0902_iio$r_icic_fields.ka0902_iio$r_icic_fields_l_ol.ka0902_iio$r_icic_\#l_bits.ka0902_iio$v_icic_flush_addr#define ka0902_iio$v_icic_enable ka0 /902_iio$r_icic_ol.ka0902_iio$r_icic_fields.ka0902_iio$r_icic_fields_l_ol.ka0902_iio$r_icic_l_bi\ts.ka0902_iio$v_icic_enable#define ka0902_iio$v_icic_clock ka0902_iio$r_icic_ol.ka0902_iio$r_icic_fields.ka0902_iio$r_icic_fields_l_ol.ka0902_iio$r_icic_l_bit\s.ka0902_iio$v_icic_clock{#define ka0902_iio$l_icic_h ka0902_iio$r_icic_ol.ka0902_iio$r_icic_fields.ka0902_iio$r_icic_fields_h_ol.ka0902_iio$l_icic_h"#endif /* #if !defined(__VAXC) */ #define KA0902_IIO$K_LENGTH 1248N/* New for T4 an/d Lynx (T3), the IC Interrupt Controller. */N/* ICIC register definitions. To access these registers, write the offset */N/* into the AIR register, then read the DIR register or write your data */N/* to the DIR register. */N/* */N#define KA0902_ICIC$K_MASK 64 /* ICIC interrupt mask register */N#define KA0902_ICIC$K_ELCR 80 /*/ ICIC edge level register */O#define KA0902_ICIC$K_EISA 96 /* ICIC device is behind EISA bridge */N#define KA0902_ICIC$K_MODE 112 /* Bit 0: priority or round robin */N/* */N/* Sable CPU register definitions */N/* */(#define KA0902_CPU$M_BCC_ENB_ALLOC_L 0x1*#define KA0902_CPU$M_BCC /_FRC_FILL_SH_L 0x2&#define KA0902_CPU$M_BCC_ENB_TPC_L 0x4'#define KA0902_CPU$M_BCC_FILL_WTP_L 0x8(#define KA0902_CPU$M_BCC_FILL_WCP_L 0x10)#define KA0902_CPU$M_BCC_FILL_WDTP_L 0x20'#define KA0902_CPU$M_BCC_ENB_CEI_L 0x40(#define KA0902_CPU$M_BCC_ENB_EDCC_L 0x80,#define KA0902_CPU$M_BCC_ENB_EDC_CHK_L 0x100+#define KA0902_CPU$M_BCC_ENB_BC_CIO_L 0x200*#define KA0902_CPU$M_BCC_DIS_BLK_W_L 0x400,#define KA0902_CPU$M_BCC_ENB_BC_INIT_L 0x800*#define KA0902_CPU$M_BCC_FOR_EDCC_L 0x1000(#define /KA0902_CPU$M_BCC_SH_D_V_L 0xE000)#define KA0902_CPU$M_BCC_EDC_L 0x3FFF00000#define KA0902_CPU$M_BCC_CACHE_SIZE_L 0xC0000000(#define KA0902_CPU$M_BCC_ENB_ALLOC_H 0x1*#define KA0902_CPU$M_BCC_FRC_FILL_SH_H 0x2&#define KA0902_CPU$M_BCC_ENB_TPC_H 0x4'#define KA0902_CPU$M_BCC_FILL_WTP_H 0x8(#define KA0902_CPU$M_BCC_FILL_WCP_H 0x10)#define KA0902_CPU$M_BCC_FILL_WDTP_H 0x20'#define KA0902_CPU$M_BCC_ENB_CEI_H 0x40(#define KA0902_CPU$M_BCC_ENB_EDCC_H 0x80,#define KA0902_CPU$M_BCC_ENB_EDC_CHK_H 0 /x100+#define KA0902_CPU$M_BCC_ENB_BC_CIO_H 0x200*#define KA0902_CPU$M_BCC_DIS_BLK_W_H 0x400,#define KA0902_CPU$M_BCC_ENB_BC_INIT_H 0x800*#define KA0902_CPU$M_BCC_FOR_EDCC_H 0x1000(#define KA0902_CPU$M_BCC_SH_D_V_H 0xE000+#define KA0902_CPU$M_BCC_EDC_L_H 0x3FFF00000#define KA0902_CPU$M_BCC_CACHE_SIZE_H 0xC0000000N#define KA0902_BCC$K_RESERVED 0 /* Reserved */N#define KA0902_BCC$K_CACHE_SIZE_1MB 1 /* Cache size is 1Mb */N#define KA0902_BCC$K_C /ACHE_SIZE_4MB 2 /* Cache size is 4Mb */##define KA0902_CPU$M_BCCE_MCE_L 0x4"#define KA0902_CPU$M_BCCE_CE_L 0x8+#define KA0902_CPU$M_BCCE_CNTRL_PAR_L 0x100$#define KA0902_CPU$M_BCCE_SH_L 0x200'#define KA0902_CPU$M_BCCE_DIRTY_L 0x400'#define KA0902_CPU$M_BCCE_VALID_L 0x800*#define KA0902_CPU$M_BCCE_BC_EDC_L 0x20000.#define KA0902_CPU$M_BCCE_EDC_SYND_0 0x1FC0000/#define KA0902_CPU$M_BCCE_EDC_SYND_2 0xFE000000##define KA0902_CPU$M_BCCE_MCE_H 0x4"#define KA0902_CPU$M_BCCE_ /CE_H 0x8+#define KA0902_CPU$M_BCCE_READ_ONLY 0x1FFF0*#define KA0902_CPU$M_BCCE_BC_EDC_H 0x20000.#define KA0902_CPU$M_BCCE_EDC_SYND_1 0x1FC0000/#define KA0902_CPU$M_BCCE_EDC_SYND_3 0xFE000000.#define KA0902_CPU$M_BCCEA_BCMAP_OFF_L 0x1FFFF,#define KA0902_CPU$M_BCCEA_TAG_PAR_L 0x400001#define KA0902_CPU$M_BCCEA_TAG_VALUE_L 0x7FF80000.#define KA0902_CPU$M_BCCEA_BCMAP_OFF_H 0x1FFFF,#define KA0902_CPU$M_BCCEA_TAG_PAR_H 0x400001#define KA0902_CPU$M_BCCEA_TAG_VALUE_H 0x7FF80000##define KA0902_C /PU$M_BCUE_MPE_L 0x1"#define KA0902_CPU$M_BCUE_PE_L 0x2%#define KA0902_CPU$M_BCUE_MUNCE_L 0x4$#define KA0902_CPU$M_BCUE_UNCE_L 0x8*#define KA0902_CPU$M_BCUE_CTRL_PAR_L 0x100$#define KA0902_CPU$M_BCUE_SH_L 0x200'#define KA0902_CPU$M_BCUE_DIRTY_L 0x400'#define KA0902_CPU$M_BCUE_VALID_L 0x800*#define KA0902_CPU$M_BCUE_BC_EDC_L 0x20000.#define KA0902_CPU$M_BCUE_EDC_SYND_0 0x1FC0000/#define KA0902_CPU$M_BCUE_EDC_SYND_2 0xFE000000##define KA0902_CPU$M_BCUE_MPE_H 0x1"#define KA0902_CPU$M_BCU /E_PE_H 0x2%#define KA0902_CPU$M_BCUE_MUNCE_H 0x4$#define KA0902_CPU$M_BCUE_UNCE_H 0x8*#define KA0902_CPU$M_BCUE_BC_EDC_H 0x20000.#define KA0902_CPU$M_BCUE_EDC_SYND_1 0x1FC0000/#define KA0902_CPU$M_BCUE_EDC_SYND_3 0xFE000000.#define KA0902_CPU$M_BCUEA_BCMAP_OFF_L 0x1FFFF(#define KA0902_CPU$M_BCUEA_PTP_L 0x20000'#define KA0902_CPU$M_BCUEA_TP_L 0x40000*#define KA0902_CPU$M_BCUEA_TV_L 0x7FF80000-#define KA0902_CPU$M_BCUEA_FILL1_L 0x80000000.#define KA0902_CPU$M_BCUEA_BCMAP_OFF_H 0x1FFFF(#d /efine KA0902_CPU$M_BCUEA_PTP_H 0x20000'#define KA0902_CPU$M_BCUEA_TP_H 0x40000*#define KA0902_CPU$M_BCUEA_TV_H 0x7FF80000-#define KA0902_CPU$M_BCUEA_FILL1_H 0x80000000%#define KA0902_CPU$M_DTER_MDTER_L 0x1$#define KA0902_CPU$M_DTER_DTER_L 0x2&#define KA0902_CPU$M_DTER_TOFF_L 0x3FC-#define KA0902_CPU$M_DTER_BANK0_TAG_L 0x7FC00-#define KA0902_CPU$M_DTER_BANK0_PAR_L 0x800000#define KA0902_CPU$M_DTER_BANK1_TAG_L 0x1FF000000#define KA0902_CPU$M_DTER_BANK1_PAR_L 0x20000000%#define KA0902_CPU /$M_DTER_MDTER_H 0x1$#define KA0902_CPU$M_DTER_DTER_H 0x2&#define KA0902_CPU$M_DTER_TOFF_H 0x3FC-#define KA0902_CPU$M_DTER_BANK0_TAG_H 0x7FC00-#define KA0902_CPU$M_DTER_BANK0_PAR_H 0x800000#define KA0902_CPU$M_DTER_BANK1_TAG_H 0x1FF000000#define KA0902_CPU$M_DTER_BANK1_PAR_H 0x20000000$#define KA0902_CPU$M_CBCTL_DWP_L 0x1%#define KA0902_CPU$M_CBCTL_CAWP_L 0x6$#define KA0902_CPU$M_CBCTL_EPC_L 0x8(#define KA0902_CPU$M_CBCTL_FRC_SH_L 0x10*#define KA0902_CPU$M_CBCTL_CMDER_ID_L 0xE0&#define /KA0902_CPU$M_CBCTL_ACM_L 0x700)#define KA0902_CPU$M_CBCTL_ENB_CI_L 0x800&#define KA0902_CPU$M_CBCTL_RD_L 0x1000,#define KA0902_CPU$M_CBCTL_QW_2_SEL_L 0x2000-#define KA0902_CPU$M_CBCTL_SEL_DRACK_L 0x4000$#define KA0902_CPU$M_CBCTL_DWP_H 0x1%#define KA0902_CPU$M_CBCTL_CAWP_H 0x6$#define KA0902_CPU$M_CBCTL_EPC_H 0x8(#define KA0902_CPU$M_CBCTL_FRC_SH_H 0x10*#define KA0902_CPU$M_CBCTL_CMDER_ID_H 0xE0&#define KA0902_CPU$M_CBCTL_ACM_H 0x700)#define KA0902_CPU$M_CBCTL_ENB_CI_H 0x800&#define KA /0902_CPU$M_CBCTL_RD_H 0x1000,#define KA0902_CPU$M_CBCTL_QW_2_SEL_H 0x2000-#define KA0902_CPU$M_CBCTL_SEL_DRACK_H 0x4000##define KA0902_CPU$M_CBE_DIAG_L 0x2"#define KA0902_CPU$M_CBE_CAP_L 0x4##define KA0902_CPU$M_CBE_MCAP_L 0x8&#define KA0902_CPU$M_CBE_PE_WRD_L 0x10'#define KA0902_CPU$M_CBE_MPE_WRD_L 0x20%#define KA0902_CPU$M_CBE_PE_RD_L 0x40&#define KA0902_CPU$M_CBE_MPE_RD_L 0x80(#define KA0902_CPU$M_CBE_CA_PE_LW0 0x100(#define KA0902_CPU$M_CBE_CA_PE_LW2 0x200'#define KA0902_CPU$M_CBE !/_D_PE_LW0 0x400'#define KA0902_CPU$M_CBE_D_PE_LW2 0x800(#define KA0902_CPU$M_CBE_D_PE_LW4 0x1000(#define KA0902_CPU$M_CBE_D_PE_LW6 0x2000)#define KA0902_CPU$M_CBE_CA_NACK_L 0x4000.#define KA0902_CPU$M_CBE_WR_DATA_NACK_L 0x8000,#define KA0902_CPU$M_CBE_MCOUNT_L 0x3F0000000#define KA0902_CPU$M_CBE_MADR_VALID_L 0x40000000##define KA0902_CPU$M_CBE_DIAG_H 0x2"#define KA0902_CPU$M_CBE_CAP_H 0x4##define KA0902_CPU$M_CBE_MCAP_H 0x8&#define KA0902_CPU$M_CBE_PE_WRD_H 0x10'#define KA0902_CPU$M_C "/BE_MPE_WRD_H 0x20%#define KA0902_CPU$M_CBE_PE_RD_H 0x40&#define KA0902_CPU$M_CBE_MPE_RD_H 0x80(#define KA0902_CPU$M_CBE_CA_PE_LW1 0x100(#define KA0902_CPU$M_CBE_CA_PE_LW3 0x200'#define KA0902_CPU$M_CBE_D_PE_LW1 0x400'#define KA0902_CPU$M_CBE_D_PE_LW3 0x800(#define KA0902_CPU$M_CBE_D_PE_LW5 0x1000(#define KA0902_CPU$M_CBE_D_PE_LW7 0x2000)#define KA0902_CPU$M_CBE_UNDEFINED 0x4000*#define KA0902_CPU$M_CBE_UNDEFINED2 0x8000,#define KA0902_CPU$M_CBE_MCOUNT_H 0x3F0000000#define KA0902_CPU$M #/_CBE_MADR_VALID_H 0x40000000$#define KA0902_CPU$M_CBEAL_SBO_L 0x30#define KA0902_CPU$M_CBEAL_ADDR_CAD_L 0xFFFFFFFC$#define KA0902_CPU$M_CBEAL_SBO_H 0x30#define KA0902_CPU$M_CBEAL_ADDR_CAD_H 0xFFFFFFFC$#define KA0902_CPU$M_CBEAH_SB0_L 0x3'#define KA0902_CPU$M_CBEAH_EA_L 0x3FFFC,#define KA0902_CPU$M_CBEAH_T_TYPE_L 0x1C0000-#define KA0902_CPU$M_CBEAH_CMDR_ID_L 0xE00000+#define KA0902_CPU$M_CBEAH_SB1_L 0xFF000000$#define KA0902_CPU$M_CBEAH_SB0_H 0x3'#define KA0902_CPU$M_CBEAH_EA_H 0x3FFFC, $/#define KA0902_CPU$M_CBEAH_T_TYPE_H 0x1C0000-#define KA0902_CPU$M_CBEAH_CMDR_ID_H 0xE00000+#define KA0902_CPU$M_CBEAH_SB1_H 0xFF000000,#define KA0902_CPU$M_PMBX_FILL1_L 0xFFFFFFFF,#define KA0902_CPU$M_PMBX_FILL1_H 0xFFFFFFFF'#define KA0902_CPU$M_IPIR_UNDEFINED 0x1)#define KA0902_CPU$M_IPIR_REQ_INT_CPU 0x1+#define KA0902_CPU$M_IPIR_REQ_NODE_HALT 0x8'#define KA0902_CPU$M_SIC_UNDEFINED0 0x1'#define KA0902_CPU$M_SIC_UNDEFINED1 0x2 #define KA0902_CPU$M_SIC_EIC 0x4'#define KA0902_CPU$M_SIC %/_UNDEFINED2 0x8&#define KA0902_CPU$M_SIC_IT_ICLEAR 0x1(#define KA0902_CPU$M_SIC_SYS_EVT_CLR 0x2'#define KA0902_CPU$M_SIC_UNDEFINED3 0x4*#define KA0902_CPU$M_SIC_NODE_HALT_CLR 0x8$#define KA0902_CPU$M_ADLK_LA_V_L 0x1)#define KA0902_CPU$M_ADLK_LA_L 0xFFFFFFF8$#define KA0902_CPU$M_ADLK_LA_V_H 0x1)#define KA0902_CPU$M_ADLK_LA_H 0xFFFFFFF8&#define KA0902_CPU$M_MADRL_VALID_L 0x1'#define KA0902_CPU$M_MADRL_T_TYPE_L 0x2/#define KA0902_CPU$M_MADRL_ADDRESS_L 0xFFFFFFFC&#define KA0902_CPU$M_MAD &/RL_VALID_H 0x1'#define KA0902_CPU$M_MADRL_T_TYPE_H 0x2/#define KA0902_CPU$M_MADRL_ADDRESS_H 0xFFFFFFFC%#define KA0902_CPU$M_CRREVS_REV_L 0xF+#define KA0902_CPU$M_CRREVS_CPU_MODE_L 0x10,#define KA0902_CPU$M_CRREVS_C3_SPEED_L 0xFE0(#define KA0902_CPU$M_CRREVS_SB0_L 0x1000*#define KA0902_CPU$M_CRREVS_FILL1_L 0x2000-#define KA0902_CPU$M_CRREVS_IO_RETRY_L 0x4000.#define KA0902_CPU$M_CRREVS_PCH_INV_L 0x200000%#define KA0902_CPU$M_CRREVS_REV_H 0xF+#define KA0902_CPU$M_CRREVS_CPU_MODE_H 0x10 '/,#define KA0902_CPU$M_CRREVS_C3_SPEED_H 0xFE0(#define KA0902_CPU$M_CRREVS_SB0_H 0x1000*#define KA0902_CPU$M_CRREVS_FILL1_H 0x2000-#define KA0902_CPU$M_CRREVS_IO_RETRY_H 0x4000.#define KA0902_CPU$M_CRREVS_PCH_INV_H 0x200000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0902_cpu {N/* B-Cache Control Register 0 (/ */#pragma __nomember_alignment __union {! __int64 ka0902_cpu$q_bcc; __struct { __union {0 unsigned int ka0902_cpu$l_bcc_l; __struct {> unsigned ka0902_cpu$v_bcc_enb_alloc_l : 1;@ unsigned ka0902_cpu$v_bcc_frc_fill_sh_l : 1;< unsigned ka0902_cpu$v_bcc_enb_tpc_l : 1;= unsigned ka0902_cpu$v_bcc_fill_wtp_l : 1;= )/ unsigned ka0902_cpu$v_bcc_fill_wcp_l : 1;> unsigned ka0902_cpu$v_bcc_fill_wdtp_l : 1;< unsigned ka0902_cpu$v_bcc_enb_cei_l : 1;= unsigned ka0902_cpu$v_bcc_enb_edcc_l : 1;@ unsigned ka0902_cpu$v_bcc_enb_edc_chk_l : 1;? unsigned ka0902_cpu$v_bcc_enb_bc_cio_l : 1;> unsigned ka0902_cpu$v_bcc_dis_blk_w_l : 1;@ unsigned ka0902_cpu$v_bcc_enb_bc_init_l : 1;= */ unsigned ka0902_cpu$v_bcc_for_edcc_l : 1;; unsigned ka0902_cpu$v_bcc_sh_d_v_l : 3;9 unsigned ka0902_cpu$v_bcc_edc_l : 14;? unsigned ka0902_cpu$v_bcc_cache_size_l : 2;. } ka0902_cpu$r_bcc_l_bits;/ } ka0902_cpu$r_bcc_fields_l_ol; __union {0 unsigned int ka0902_cpu$l_bcc_h; __struct {> unsigned ka0902_cpu$v_bcc_enb_alloc_ +/h : 1;@ unsigned ka0902_cpu$v_bcc_frc_fill_sh_h : 1;< unsigned ka0902_cpu$v_bcc_enb_tpc_h : 1;= unsigned ka0902_cpu$v_bcc_fill_wtp_h : 1;= unsigned ka0902_cpu$v_bcc_fill_wcp_h : 1;> unsigned ka0902_cpu$v_bcc_fill_wdtp_h : 1;< unsigned ka0902_cpu$v_bcc_enb_cei_h : 1;= unsigned ka0902_cpu$v_bcc_enb_edcc_h : 1;@ unsigned ka0902_cpu$v_bcc_enb_ed ,/c_chk_h : 1;? unsigned ka0902_cpu$v_bcc_enb_bc_cio_h : 1;> unsigned ka0902_cpu$v_bcc_dis_blk_w_h : 1;@ unsigned ka0902_cpu$v_bcc_enb_bc_init_h : 1;= unsigned ka0902_cpu$v_bcc_for_edcc_h : 1;; unsigned ka0902_cpu$v_bcc_sh_d_v_h : 3;; unsigned ka0902_cpu$v_bcc_edc_l_h : 14;? unsigned ka0902_cpu$v_bcc_cache_size_h : 2;. } ka0902_cpu$r_bcc_h_b-/its;/ } ka0902_cpu$r_bcc_fields_h_ol;& } ka0902_cpu$r_bcc_fields; } ka0902_cpu$r_bcc_ol;" char ka0902_cpu$b_fill27 [24];N/* B-Cache Correctable Error Register, BCCE */ __union {" __int64 ka0902_cpu$q_bcce; __struct { __union {1 unsigned int ka0902_cpu$l_bcce_l; __struct {9 unsigned ka0902_cpu$v_bcce_fill1 : 2;9 un ./signed ka0902_cpu$v_bcce_mce_l : 1;8 unsigned ka0902_cpu$v_bcce_ce_l : 1;9 unsigned ka0902_cpu$v_bcce_fill2 : 4;? unsigned ka0902_cpu$v_bcce_cntrl_par_l : 1;8 unsigned ka0902_cpu$v_bcce_sh_l : 1;; unsigned ka0902_cpu$v_bcce_dirty_l : 1;; unsigned ka0902_cpu$v_bcce_valid_l : 1;9 unsigned ka0902_cpu$v_bcce_fill3 : 5;< unsigned ka0902_cpu$v_ //bcce_bc_edc_l : 1;> unsigned ka0902_cpu$v_bcce_edc_synd_0 : 7;> unsigned ka0902_cpu$v_bcce_edc_synd_2 : 7;/ } ka0902_cpu$r_bcce_l_bits;0 } ka0902_cpu$r_bcce_fields_l_ol; __union {1 unsigned int ka0902_cpu$l_bcce_h; __struct {9 unsigned ka0902_cpu$v_bcce_fill4 : 2;9 unsigned ka0902_cpu$v_bcce_mce_h : 1;8 unsigned ka0 0/902_cpu$v_bcce_ce_h : 1;> unsigned ka0902_cpu$v_bcce_read_only : 13;< unsigned ka0902_cpu$v_bcce_bc_edc_h : 1;> unsigned ka0902_cpu$v_bcce_edc_synd_1 : 7;> unsigned ka0902_cpu$v_bcce_edc_synd_3 : 7;/ } ka0902_cpu$r_bcce_h_bits;0 } ka0902_cpu$r_bcce_fields_h_ol;' } ka0902_cpu$r_bcce_fields; } ka0902_cpu$r_bcce_ol;" char ka0902_cpu$b_fill28 [24];N/* B-Cache Cor 1/rectable Error Register, BCCEA */ __union {# __int64 ka0902_cpu$q_bccea; __struct { __union {2 unsigned int ka0902_cpu$l_bccea_l; __struct {A unsigned ka0902_cpu$v_bccea_bcmap_off_l : 17;: unsigned ka0902_cpu$v_bccea_fill1 : 1;> unsigned ka0902_cpu$v_bccea_tag_par_l : 1;A unsigned ka0902_cpu$v_bccea_tag_value_l : 12; 2/: unsigned ka0902_cpu$v_bccea_fill2 : 1;0 } ka0902_cpu$r_bccea_l_bits;1 } ka0902_cpu$r_bccea_fields_l_ol; __union {2 unsigned int ka0902_cpu$l_bccea_h; __struct {A unsigned ka0902_cpu$v_bccea_bcmap_off_h : 17;< unsigned ka0902_cpu$v_bccea_fill1_h : 1;> unsigned ka0902_cpu$v_bccea_tag_par_h : 1;A unsigned ka0902_cpu$v_ 3/bccea_tag_value_h : 12;< unsigned ka0902_cpu$v_bccea_fill2_h : 1;0 } ka0902_cpu$r_bccea_h_bits;1 } ka0902_cpu$r_bccea_fields_h_ol;( } ka0902_cpu$r_bccea_fields; } ka0902_cpu$r_bccea_ol;" char ka0902_cpu$b_fill29 [24];N/* B-Cache UNCRectable Error Register, BCUE */ __union {" __int64 ka0902_cpu$q_bcue; __struct { __union {1 unsigned i 4/nt ka0902_cpu$l_bcue_l; __struct {9 unsigned ka0902_cpu$v_bcue_mpe_l : 1;8 unsigned ka0902_cpu$v_bcue_pe_l : 1;; unsigned ka0902_cpu$v_bcue_munce_l : 1;: unsigned ka0902_cpu$v_bcue_unce_l : 1;9 unsigned ka0902_cpu$v_bcue_fill1 : 4;> unsigned ka0902_cpu$v_bcue_ctrl_par_l : 1;8 unsigned ka0902_cpu$v_bcue_sh_l : 1;; unsigned 5/ ka0902_cpu$v_bcue_dirty_l : 1;; unsigned ka0902_cpu$v_bcue_valid_l : 1;9 unsigned ka0902_cpu$v_bcue_fill2 : 5;< unsigned ka0902_cpu$v_bcue_bc_edc_l : 1;> unsigned ka0902_cpu$v_bcue_edc_synd_0 : 7;> unsigned ka0902_cpu$v_bcue_edc_synd_2 : 7;/ } ka0902_cpu$r_bcue_l_bits;0 } ka0902_cpu$r_bcue_fields_l_ol; __union {1 unsigned int ka0902_ 6/cpu$l_bcue_h; __struct {9 unsigned ka0902_cpu$v_bcue_mpe_h : 1;8 unsigned ka0902_cpu$v_bcue_pe_h : 1;; unsigned ka0902_cpu$v_bcue_munce_h : 1;: unsigned ka0902_cpu$v_bcue_unce_h : 1;: unsigned ka0902_cpu$v_bcue_fill3 : 13;< unsigned ka0902_cpu$v_bcue_bc_edc_h : 1;> unsigned ka0902_cpu$v_bcue_edc_synd_1 : 7;> unsigned ka0907/2_cpu$v_bcue_edc_synd_3 : 7;/ } ka0902_cpu$r_bcue_h_bits;0 } ka0902_cpu$r_bcue_fields_h_ol;' } ka0902_cpu$r_bcue_fields; } ka0902_cpu$r_bcue_ol;" char ka0902_cpu$b_fill30 [24];N/* B-Cache UNCRectable Error Address Register, BCUEA */ __union {# __int64 ka0902_cpu$q_bcuea; __struct { __union {2 unsigned int ka0902_cpu$l_bcuea_l; __struct {A 8/ unsigned ka0902_cpu$v_bcuea_bcmap_off_l : 17;: unsigned ka0902_cpu$v_bcuea_ptp_l : 1;9 unsigned ka0902_cpu$v_bcuea_tp_l : 1;: unsigned ka0902_cpu$v_bcuea_tv_l : 12;< unsigned ka0902_cpu$v_bcuea_fill1_l : 1;0 } ka0902_cpu$r_bcuea_l_bits;1 } ka0902_cpu$r_bcuea_fields_l_ol; __union {2 unsigned int ka0902_cpu$l_bcuea_h; __st 9/ruct {A unsigned ka0902_cpu$v_bcuea_bcmap_off_h : 17;: unsigned ka0902_cpu$v_bcuea_ptp_h : 1;9 unsigned ka0902_cpu$v_bcuea_tp_h : 1;: unsigned ka0902_cpu$v_bcuea_tv_h : 12;< unsigned ka0902_cpu$v_bcuea_fill1_h : 1;0 } ka0902_cpu$r_bcuea_h_bits;1 } ka0902_cpu$r_bcuea_fields_h_ol;( } ka0902_cpu$r_bcuea_fields; } ka0902_cpu$r_bcuea_ol;" char :/ ka0902_cpu$b_fill31 [24];N/* Duplicate Tag Error Register DTER */ __union {" __int64 ka0902_cpu$q_dter; __struct { __union {1 unsigned int ka0902_cpu$l_dter_l; __struct {; unsigned ka0902_cpu$v_dter_mdter_l : 1;: unsigned ka0902_cpu$v_dter_dter_l : 1;: unsigned ka0902_cpu$v_dter_toff_l : 8;? unsigned ka0902_ ;/cpu$v_dter_bank0_tag_l : 9;? unsigned ka0902_cpu$v_dter_bank0_par_l : 1;? unsigned ka0902_cpu$v_dter_bank1_tag_l : 9;? unsigned ka0902_cpu$v_dter_bank1_par_l : 1;; unsigned ka0902_cpu$v_dter_fill1_l : 2;/ } ka0902_cpu$r_dter_l_bits;0 } ka0902_cpu$r_dter_fields_l_ol; __union {1 unsigned int ka0902_cpu$l_dter_h; __struct {; /v_cbctl_dwp_l : 1;; unsigned ka0902_cpu$v_cbctl_cawp_l : 2;: unsigned ka0902_cpu$v_cbctl_epc_l : 1;= unsigned ka0902_cpu$v_cbctl_frc_sh_l : 1;? unsigned ka0902_cpu$v_cbctl_cmder_id_l : 3;: unsigned ka0902_cpu$v_cbctl_acm_l : 3;= unsigned ka0902_cpu$v_cbctl_enb_ci_l : 1;9 unsigned ka0902_cpu$v_cbctl_rd_l : 1;? unsigned ka0902_cpu$v_cbctl_qw ?/_2_sel_l : 1;@ unsigned ka0902_cpu$v_cbctl_sel_drack_l : 1;= unsigned ka0902_cpu$v_cbctl_fill1_l : 17;0 } ka0902_cpu$r_cbctl_l_bits;1 } ka0902_cpu$r_cbctl_fields_l_ol; __union {2 unsigned int ka0902_cpu$l_cbctl_h; __struct {: unsigned ka0902_cpu$v_cbctl_dwp_h : 1;; unsigned ka0902_cpu$v_cbctl_cawp_h : 2;: unsigned k @/a0902_cpu$v_cbctl_epc_h : 1;= unsigned ka0902_cpu$v_cbctl_frc_sh_h : 1;? unsigned ka0902_cpu$v_cbctl_cmder_id_h : 3;: unsigned ka0902_cpu$v_cbctl_acm_h : 3;= unsigned ka0902_cpu$v_cbctl_enb_ci_h : 1;9 unsigned ka0902_cpu$v_cbctl_rd_h : 1;? unsigned ka0902_cpu$v_cbctl_qw_2_sel_h : 1;@ unsigned ka0902_cpu$v_cbctl_sel_drack_h : 1;= unsigned kA/a0902_cpu$v_cbctl_fill1_h : 17;0 } ka0902_cpu$r_cbctl_h_bits;1 } ka0902_cpu$r_cbctl_fields_h_ol;( } ka0902_cpu$r_cbctl_fields; } ka0902_cpu$r_cbctl_ol;" char ka0902_cpu$b_fill33 [24];N/* Cobra bus Error Register - CBE */ __union {! __int64 ka0902_cpu$q_cbe; __struct { __union {0 unsigned int ka0902_cpu$l_cbe_l; __struct {: B/ unsigned ka0902_cpu$v_cbe_fill1_l : 1;9 unsigned ka0902_cpu$v_cbe_diag_l : 1;8 unsigned ka0902_cpu$v_cbe_cap_l : 1;9 unsigned ka0902_cpu$v_cbe_mcap_l : 1;; unsigned ka0902_cpu$v_cbe_pe_wrd_l : 1;< unsigned ka0902_cpu$v_cbe_mpe_wrd_l : 1;: unsigned ka0902_cpu$v_cbe_pe_rd_l : 1;; unsigned ka0902_cpu$v_cbe_mpe_rd_l : 1;< un C/signed ka0902_cpu$v_cbe_ca_pe_lw0 : 1;< unsigned ka0902_cpu$v_cbe_ca_pe_lw2 : 1;; unsigned ka0902_cpu$v_cbe_d_pe_lw0 : 1;; unsigned ka0902_cpu$v_cbe_d_pe_lw2 : 1;; unsigned ka0902_cpu$v_cbe_d_pe_lw4 : 1;; unsigned ka0902_cpu$v_cbe_d_pe_lw6 : 1;< unsigned ka0902_cpu$v_cbe_ca_nack_l : 1;A unsigned ka0902_cpu$v_cbe_wr_data_nack_l : 1;8 unsign D/ed ka0902_cpu$v_cbe_fill2 : 8;; unsigned ka0902_cpu$v_cbe_mcount_l : 6;? unsigned ka0902_cpu$v_cbe_madr_valid_l : 1;6 unsigned ka0902_cpu$v_fill_0_ : 1;. } ka0902_cpu$r_cbe_l_bits;/ } ka0902_cpu$r_cbe_fields_l_ol; __union {0 unsigned int ka0902_cpu$l_cbe_h; __struct {8 unsigned ka0902_cpu$v_cbe_fill3 : 1;9 unsigned k E/a0902_cpu$v_cbe_diag_h : 1;8 unsigned ka0902_cpu$v_cbe_cap_h : 1;9 unsigned ka0902_cpu$v_cbe_mcap_h : 1;; unsigned ka0902_cpu$v_cbe_pe_wrd_h : 1;< unsigned ka0902_cpu$v_cbe_mpe_wrd_h : 1;: unsigned ka0902_cpu$v_cbe_pe_rd_h : 1;; unsigned ka0902_cpu$v_cbe_mpe_rd_h : 1;< unsigned ka0902_cpu$v_cbe_ca_pe_lw1 : 1;< unsigned ka0902_cpu$v_cbe_ca_p F/e_lw3 : 1;; unsigned ka0902_cpu$v_cbe_d_pe_lw1 : 1;; unsigned ka0902_cpu$v_cbe_d_pe_lw3 : 1;; unsigned ka0902_cpu$v_cbe_d_pe_lw5 : 1;; unsigned ka0902_cpu$v_cbe_d_pe_lw7 : 1;< unsigned ka0902_cpu$v_cbe_undefined : 1;= unsigned ka0902_cpu$v_cbe_undefined2 : 1;: unsigned ka0902_cpu$v_cbe_fill2_h : 8;; unsigned ka0902_cpu$v_cbe_mcount_h : 6; G/? unsigned ka0902_cpu$v_cbe_madr_valid_h : 1;6 unsigned ka0902_cpu$v_fill_1_ : 1;. } ka0902_cpu$r_cbe_h_bits;/ } ka0902_cpu$r_cbe_fields_h_ol;& } ka0902_cpu$r_cbe_fields; } ka0902_cpu$r_cbe_ol;" char ka0902_cpu$b_fill34 [24];N/* Cobra bus Error Address Low Register - CBEAL */ __union {# __int64 ka0902_cpu$q_cbeal; __struct { __union H/ {2 unsigned int ka0902_cpu$l_cbeal_l; __struct {: unsigned ka0902_cpu$v_cbeal_sbo_l : 2;@ unsigned ka0902_cpu$v_cbeal_addr_cad_l : 30;0 } ka0902_cpu$r_cbeal_l_bits;1 } ka0902_cpu$r_cbeal_fields_l_ol; __union {2 unsigned int ka0902_cpu$l_cbeal_h; __struct {: unsigned ka0902_cpu$v_cbeal_sbo_h : 2;@ unsign I/ed ka0902_cpu$v_cbeal_addr_cad_h : 30;0 } ka0902_cpu$r_cbeal_h_bits;1 } ka0902_cpu$r_cbeal_fields_h_ol;( } ka0902_cpu$r_cbeal_fields; } ka0902_cpu$r_cbeal_ol;" char ka0902_cpu$b_fill35 [24];N/* Cobra bus Error Address High Register - CBEAH */ __union {# __int64 ka0902_cpu$q_cbeah; __struct { __union {2 unsigned int ka0902_cpu$l_cbeah_l; __st J/ruct {: unsigned ka0902_cpu$v_cbeah_sb0_l : 2;: unsigned ka0902_cpu$v_cbeah_ea_l : 16;= unsigned ka0902_cpu$v_cbeah_t_type_l : 3;> unsigned ka0902_cpu$v_cbeah_cmdr_id_l : 3;: unsigned ka0902_cpu$v_cbeah_sb1_l : 8;0 } ka0902_cpu$r_cbeah_l_bits;1 } ka0902_cpu$r_cbeah_fields_l_ol; __union {2 unsigned int ka0902_cpu$l_cbeah_h; K/ __struct {: unsigned ka0902_cpu$v_cbeah_sb0_h : 2;: unsigned ka0902_cpu$v_cbeah_ea_h : 16;= unsigned ka0902_cpu$v_cbeah_t_type_h : 3;> unsigned ka0902_cpu$v_cbeah_cmdr_id_h : 3;: unsigned ka0902_cpu$v_cbeah_sb1_h : 8;0 } ka0902_cpu$r_cbeah_h_bits;1 } ka0902_cpu$r_cbeah_fields_h_ol;( } ka0902_cpu$r_cbeah_fields; } ka0902_cpu$r_cbeah_ol;" L/ char ka0902_cpu$b_fill36 [24];N/* Processor Mailbox Register - PMBX */ __union {" __int64 ka0902_cpu$q_pmbx; __struct { __union {1 unsigned int ka0902_cpu$l_pmbx_l; __struct {< unsigned ka0902_cpu$v_pmbx_fill1_l : 32;/ } ka0902_cpu$r_pmbx_l_bits;0 } ka0902_cpu$r_pmbx_fields_l_ol; __union {1 unsigned M/ int ka0902_cpu$l_pmbx_h; __struct {< unsigned ka0902_cpu$v_pmbx_fill1_h : 32;/ } ka0902_cpu$r_pmbx_h_bits;0 } ka0902_cpu$r_pmbx_fields_h_ol;' } ka0902_cpu$r_pmbx_fields; } ka0902_cpu$r_pmbx_ol;" char ka0902_cpu$b_fill37 [24];N/* Interprocessor Interrupt Request Register - IPIR */ __union {" __int64 ka0902_cpu$q_ipir; __struct { __union N/ {1 unsigned int ka0902_cpu$l_ipir_l; __struct {= unsigned ka0902_cpu$v_ipir_undefined : 1;: unsigned ka0902_cpu$v_ipir_fill1 : 31;/ } ka0902_cpu$r_ipir_l_bits;0 } ka0902_cpu$r_ipir_fields_l_ol; __union {1 unsigned int ka0902_cpu$l_ipir_h; __struct {? unsigned ka0902_cpu$v_ipir_req_int_cpu : 1;9 unsi O/gned ka0902_cpu$v_ipir_fill2 : 2;A unsigned ka0902_cpu$v_ipir_req_node_halt : 1;: unsigned ka0902_cpu$v_ipir_fill3 : 28;/ } ka0902_cpu$r_ipir_h_bits;0 } ka0902_cpu$r_ipir_fields_h_ol;' } ka0902_cpu$r_ipir_fields; } ka0902_cpu$r_ipir_ol;" char ka0902_cpu$b_fill38 [24];N/* System Interrupt Clear Register - SIC */ __union {! __int64 ka0902_cpu$q_sic; P/ __struct { __union {0 unsigned int ka0902_cpu$l_sic_l; __struct {= unsigned ka0902_cpu$v_sic_undefined0 : 1;= unsigned ka0902_cpu$v_sic_undefined1 : 1;6 unsigned ka0902_cpu$v_sic_eic : 1;= unsigned ka0902_cpu$v_sic_undefined2 : 1;9 unsigned ka0902_cpu$v_sic_fill1 : 28;. } ka0902_cpu$r_sic_l_bits;/ } ka09 Q/02_cpu$r_sic_fields_l_ol; __union {0 unsigned int ka0902_cpu$l_sic_h; __struct {< unsigned ka0902_cpu$v_sic_it_iclear : 1;> unsigned ka0902_cpu$v_sic_sys_evt_clr : 1;= unsigned ka0902_cpu$v_sic_undefined3 : 1;@ unsigned ka0902_cpu$v_sic_node_halt_clr : 1;9 unsigned ka0902_cpu$v_sic_fill2 : 28;. } ka0902_cpu$r_sic_h_bits;/ R/ } ka0902_cpu$r_sic_fields_h_ol;& } ka0902_cpu$r_sic_fields; } ka0902_cpu$r_sic_ol;" char ka0902_cpu$b_fill39 [24];N/* Address Lock Register - ADLK */ __union {" __int64 ka0902_cpu$q_adlk; __struct { __union {1 unsigned int ka0902_cpu$l_adlk_l; __struct {: unsigned ka0902_cpu$v_adlk_la_v_l : 1;9 unsigned ka0902_cp S/u$v_adlk_fill1 : 2;9 unsigned ka0902_cpu$v_adlk_la_l : 29;/ } ka0902_cpu$r_adlk_l_bits;0 } ka0902_cpu$r_adlk_fields_l_ol; __union {1 unsigned int ka0902_cpu$l_adlk_h; __struct {: unsigned ka0902_cpu$v_adlk_la_v_h : 1;9 unsigned ka0902_cpu$v_adlk_fill2 : 2;9 unsigned ka0902_cpu$v_adlk_la_h : 29;/ } ka0902_cpu$r_adlT/k_h_bits;0 } ka0902_cpu$r_adlk_fields_h_ol;' } ka0902_cpu$r_adlk_fields; } ka0902_cpu$r_adlk_ol;" char ka0902_cpu$b_fill40 [24];N/* Miss Address Register - MADRL */ __union {# __int64 ka0902_cpu$q_madrl; __struct { __union {2 unsigned int ka0902_cpu$l_madrl_l; __struct {< unsigned ka0902_cpu$v_madrl_valid_l : 1;= U/ unsigned ka0902_cpu$v_madrl_t_type_l : 1;? unsigned ka0902_cpu$v_madrl_address_l : 30;0 } ka0902_cpu$r_madrl_l_bits;1 } ka0902_cpu$r_madrl_fields_l_ol; __union {2 unsigned int ka0902_cpu$l_madrl_h; __struct {< unsigned ka0902_cpu$v_madrl_valid_h : 1;= unsigned ka0902_cpu$v_madrl_t_type_h : 1;? unsigned ka0902_cpu$v_madrl_adV/dress_h : 30;0 } ka0902_cpu$r_madrl_h_bits;1 } ka0902_cpu$r_madrl_fields_h_ol;( } ka0902_cpu$r_madrl_fields; } ka0902_cpu$r_madrl_ol;" char ka0902_cpu$b_fill41 [24];N/* C3 revision Register - CRREVS */ __union {$ __int64 ka0902_cpu$q_crrevs; __struct { __union {3 unsigned int ka0902_cpu$l_crrevs_l; __struct {; W/ unsigned ka0902_cpu$v_crrevs_rev_l : 4;@ unsigned ka0902_cpu$v_crrevs_cpu_mode_l : 1;@ unsigned ka0902_cpu$v_crrevs_c3_speed_l : 7;; unsigned ka0902_cpu$v_crrevs_sb0_l : 1;= unsigned ka0902_cpu$v_crrevs_fill1_l : 1;@ unsigned ka0902_cpu$v_crrevs_io_retry_l : 1;= unsigned ka0902_cpu$v_crrevs_fill2_l : 6;? unsigned ka0902_cpu$v_crrevs_pch_inv_l : 1;= X/ unsigned ka0902_cpu$v_crrevs_fill3_l : 7;6 unsigned ka0902_cpu$v_fill_2_ : 3;1 } ka0902_cpu$r_crrevs_l_bits;2 } ka0902_cpu$r_crrevs_fields_l_ol; __union {3 unsigned int ka0902_cpu$l_crrevs_h; __struct {; unsigned ka0902_cpu$v_crrevs_rev_h : 4;@ unsigned ka0902_cpu$v_crrevs_cpu_mode_h : 1;@ unsigned ka0902_cpu$v_crrevs Y/_c3_speed_h : 7;; unsigned ka0902_cpu$v_crrevs_sb0_h : 1;= unsigned ka0902_cpu$v_crrevs_fill1_h : 1;@ unsigned ka0902_cpu$v_crrevs_io_retry_h : 1;= unsigned ka0902_cpu$v_crrevs_fill2_h : 6;? unsigned ka0902_cpu$v_crrevs_pch_inv_h : 1;= unsigned ka0902_cpu$v_crrevs_fill3_h : 7;6 unsigned ka0902_cpu$v_fill_3_ : 3;1 } ka0902_cpu$r_crrevs_h_bi Z/ts;2 } ka0902_cpu$r_crrevs_fields_h_ol;) } ka0902_cpu$r_crrevs_fields;! } ka0902_cpu$r_crrevs_ol; } KA0902_CPU; #if !defined(__VAXC)=#define ka0902_cpu$q_bcc ka0902_cpu$r_bcc_ol.ka0902_cpu$q_bccv#define ka0902_cpu$l_bcc_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$l_bcc_l#define ka0902_cpu$v_bcc_enb_alloc_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_bi\ts.k[/a0902_cpu$v_bcc_enb_alloc_l#define ka0902_cpu$v_bcc_frc_fill_sh_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_\#bits.ka0902_cpu$v_bcc_frc_fill_sh_l#define ka0902_cpu$v_bcc_enb_tpc_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_bits\.ka0902_cpu$v_bcc_enb_tpc_l#define ka0902_cpu$v_bcc_fill_wtp_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_bit\s.ka09\/02_cpu$v_bcc_fill_wtp_l#define ka0902_cpu$v_bcc_fill_wcp_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_bit\s.ka0902_cpu$v_bcc_fill_wcp_l#define ka0902_cpu$v_bcc_fill_wdtp_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_bi\ts.ka0902_cpu$v_bcc_fill_wdtp_l#define ka0902_cpu$v_bcc_enb_cei_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_bits\.ka0902_cpu$]/v_bcc_enb_cei_l#define ka0902_cpu$v_bcc_enb_edcc_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_bit\s.ka0902_cpu$v_bcc_enb_edcc_l#define ka0902_cpu$v_bcc_enb_edc_chk_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_\#bits.ka0902_cpu$v_bcc_enb_edc_chk_l#define ka0902_cpu$v_bcc_enb_bc_cio_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_b\!its.ka0902_cpu$v^/_bcc_enb_bc_cio_l#define ka0902_cpu$v_bcc_dis_blk_w_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_bi\ts.ka0902_cpu$v_bcc_dis_blk_w_l#define ka0902_cpu$v_bcc_enb_bc_init_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_\#bits.ka0902_cpu$v_bcc_enb_bc_init_l#define ka0902_cpu$v_bcc_for_edcc_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_bit\s.ka0902_cpu_/$v_bcc_for_edcc_l#define ka0902_cpu$v_bcc_sh_d_v_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_bits.\ka0902_cpu$v_bcc_sh_d_v_l#define ka0902_cpu$v_bcc_edc_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_bits.ka0\902_cpu$v_bcc_edc_l#define ka0902_cpu$v_bcc_cache_size_l ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_l_ol.ka0902_cpu$r_bcc_l_b\!its.ka0902_cpu$v_bcc_cache_size_l`/v#define ka0902_cpu$l_bcc_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$l_bcc_h#define ka0902_cpu$v_bcc_enb_alloc_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_bi\ts.ka0902_cpu$v_bcc_enb_alloc_h#define ka0902_cpu$v_bcc_frc_fill_sh_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_\#bits.ka0902_cpu$v_bcc_frc_fill_sh_h#define ka0902_cpu$v_bcc_enb_tpc_h ka0902_cpa/u$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_bits\.ka0902_cpu$v_bcc_enb_tpc_h#define ka0902_cpu$v_bcc_fill_wtp_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_bit\s.ka0902_cpu$v_bcc_fill_wtp_h#define ka0902_cpu$v_bcc_fill_wcp_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_bit\s.ka0902_cpu$v_bcc_fill_wcp_h#define ka0902_cpu$v_bcc_fill_wdtp_h ka0902_cpu$r_bcc_b/ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_bi\ts.ka0902_cpu$v_bcc_fill_wdtp_h#define ka0902_cpu$v_bcc_enb_cei_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_bits\.ka0902_cpu$v_bcc_enb_cei_h#define ka0902_cpu$v_bcc_enb_edcc_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_bit\s.ka0902_cpu$v_bcc_enb_edcc_h#define ka0902_cpu$v_bcc_enb_edc_chk_h ka0902_cpu$r_bcc_ol.ka0c/902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_\#bits.ka0902_cpu$v_bcc_enb_edc_chk_h#define ka0902_cpu$v_bcc_enb_bc_cio_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_b\!its.ka0902_cpu$v_bcc_enb_bc_cio_h#define ka0902_cpu$v_bcc_dis_blk_w_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_bi\ts.ka0902_cpu$v_bcc_dis_blk_w_h#define ka0902_cpu$v_bcc_enb_bc_init_h ka0902_cpu$r_bcc_old/.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_\#bits.ka0902_cpu$v_bcc_enb_bc_init_h#define ka0902_cpu$v_bcc_for_edcc_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_bit\s.ka0902_cpu$v_bcc_for_edcc_h#define ka0902_cpu$v_bcc_sh_d_v_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_bits.\ka0902_cpu$v_bcc_sh_d_v_h#define ka0902_cpu$v_bcc_edc_l_h ka0902_cpu$r_bcc_ol.ka0902_cpu$e/r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_bits.k\a0902_cpu$v_bcc_edc_l_h#define ka0902_cpu$v_bcc_cache_size_h ka0902_cpu$r_bcc_ol.ka0902_cpu$r_bcc_fields.ka0902_cpu$r_bcc_fields_h_ol.ka0902_cpu$r_bcc_h_b\!its.ka0902_cpu$v_bcc_cache_size_h@#define ka0902_cpu$q_bcce ka0902_cpu$r_bcce_ol.ka0902_cpu$q_bcce{#define ka0902_cpu$l_bcce_l ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_l_ol.ka0902_cpu$l_bcce_l#define ka0902_cpu$v_bcce_mce_l ka0902_cpu$r_bccf/e_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_l_ol.ka0902_cpu$r_bcce_l_bit\s.ka0902_cpu$v_bcce_mce_l#define ka0902_cpu$v_bcce_ce_l ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_l_ol.ka0902_cpu$r_bcce_l_bits\.ka0902_cpu$v_bcce_ce_l#define ka0902_cpu$v_bcce_cntrl_par_l ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_l_ol.ka0902_cpu$r_bcce\%_l_bits.ka0902_cpu$v_bcce_cntrl_par_l#define ka0902_cpu$v_bcce_sh_l ka0902_cpu$r_bcce_ol.ka0902g/_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_l_ol.ka0902_cpu$r_bcce_l_bits\.ka0902_cpu$v_bcce_sh_l#define ka0902_cpu$v_bcce_dirty_l ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_l_ol.ka0902_cpu$r_bcce_l_b\its.ka0902_cpu$v_bcce_dirty_l#define ka0902_cpu$v_bcce_valid_l ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_l_ol.ka0902_cpu$r_bcce_l_b\its.ka0902_cpu$v_bcce_valid_l#define ka0902_cpu$v_bcce_bc_edc_l ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcch/e_fields.ka0902_cpu$r_bcce_fields_l_ol.ka0902_cpu$r_bcce_l_\bits.ka0902_cpu$v_bcce_bc_edc_l#define ka0902_cpu$v_bcce_edc_synd_0 ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_l_ol.ka0902_cpu$r_bcce_\#l_bits.ka0902_cpu$v_bcce_edc_synd_0#define ka0902_cpu$v_bcce_edc_synd_2 ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_l_ol.ka0902_cpu$r_bcce_\#l_bits.ka0902_cpu$v_bcce_edc_synd_2{#define ka0902_cpu$l_bcce_h ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bccei/_fields.ka0902_cpu$r_bcce_fields_h_ol.ka0902_cpu$l_bcce_h#define ka0902_cpu$v_bcce_mce_h ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_h_ol.ka0902_cpu$r_bcce_h_bit\s.ka0902_cpu$v_bcce_mce_h#define ka0902_cpu$v_bcce_ce_h ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_h_ol.ka0902_cpu$r_bcce_h_bits\.ka0902_cpu$v_bcce_ce_h#define ka0902_cpu$v_bcce_read_only ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_h_ol.ka0902_cpu$rj/_bcce_h\!_bits.ka0902_cpu$v_bcce_read_only#define ka0902_cpu$v_bcce_bc_edc_h ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_h_ol.ka0902_cpu$r_bcce_h_\bits.ka0902_cpu$v_bcce_bc_edc_h#define ka0902_cpu$v_bcce_edc_synd_1 ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_h_ol.ka0902_cpu$r_bcce_\#h_bits.ka0902_cpu$v_bcce_edc_synd_1#define ka0902_cpu$v_bcce_edc_synd_3 ka0902_cpu$r_bcce_ol.ka0902_cpu$r_bcce_fields.ka0902_cpu$r_bcce_fields_h_ol.ka0902_k/cpu$r_bcce_\#h_bits.ka0902_cpu$v_bcce_edc_synd_3C#define ka0902_cpu$q_bccea ka0902_cpu$r_bccea_ol.ka0902_cpu$q_bccea#define ka0902_cpu$l_bccea_l ka0902_cpu$r_bccea_ol.ka0902_cpu$r_bccea_fields.ka0902_cpu$r_bccea_fields_l_ol.ka0902_cpu$l_bccea_l#define ka0902_cpu$v_bccea_bcmap_off_l ka0902_cpu$r_bccea_ol.ka0902_cpu$r_bccea_fields.ka0902_cpu$r_bccea_fields_l_ol.ka0902_cpu$r_\+bccea_l_bits.ka0902_cpu$v_bccea_bcmap_off_l#define ka0902_cpu$v_bccea_tag_par_l ka0902_cpu$r_bccea_ol.ka0902_cpu$r_bcl/cea_fields.ka0902_cpu$r_bccea_fields_l_ol.ka0902_cpu$r_bc\'cea_l_bits.ka0902_cpu$v_bccea_tag_par_l#define ka0902_cpu$v_bccea_tag_value_l ka0902_cpu$r_bccea_ol.ka0902_cpu$r_bccea_fields.ka0902_cpu$r_bccea_fields_l_ol.ka0902_cpu$r_\+bccea_l_bits.ka0902_cpu$v_bccea_tag_value_l#define ka0902_cpu$l_bccea_h ka0902_cpu$r_bccea_ol.ka0902_cpu$r_bccea_fields.ka0902_cpu$r_bccea_fields_h_ol.ka0902_cpu$l_bccea_h#define ka0902_cpu$v_bccea_bcmap_off_h ka0902_cpu$r_bccea_ol.ka0902_cpu$r_bccea_fields.ka0902_m/cpu$r_bccea_fields_h_ol.ka0902_cpu$r_\+bccea_h_bits.ka0902_cpu$v_bccea_bcmap_off_h#define ka0902_cpu$v_bccea_tag_par_h ka0902_cpu$r_bccea_ol.ka0902_cpu$r_bccea_fields.ka0902_cpu$r_bccea_fields_h_ol.ka0902_cpu$r_bc\'cea_h_bits.ka0902_cpu$v_bccea_tag_par_h#define ka0902_cpu$v_bccea_tag_value_h ka0902_cpu$r_bccea_ol.ka0902_cpu$r_bccea_fields.ka0902_cpu$r_bccea_fields_h_ol.ka0902_cpu$r_\+bccea_h_bits.ka0902_cpu$v_bccea_tag_value_h@#define ka0902_cpu$q_bcue ka0902_cpu$r_bcue_ol.ka0902_cpu$q_bcuen/{#define ka0902_cpu$l_bcue_l ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$l_bcue_l#define ka0902_cpu$v_bcue_mpe_l ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$r_bcue_l_bit\s.ka0902_cpu$v_bcue_mpe_l#define ka0902_cpu$v_bcue_pe_l ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$r_bcue_l_bits\.ka0902_cpu$v_bcue_pe_l#define ka0902_cpu$v_bcue_munce_l ka0902_cpu$r_bcue_ol.ko/a0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$r_bcue_l_b\its.ka0902_cpu$v_bcue_munce_l#define ka0902_cpu$v_bcue_unce_l ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$r_bcue_l_bi\ts.ka0902_cpu$v_bcue_unce_l#define ka0902_cpu$v_bcue_ctrl_par_l ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$r_bcue_\#l_bits.ka0902_cpu$v_bcue_ctrl_par_l#define ka0902_cpu$v_bcue_sh_l ka0902_cpu$r_bcue_ol.ka0902_cp/pu$r_bcue_fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$r_bcue_l_bits\.ka0902_cpu$v_bcue_sh_l#define ka0902_cpu$v_bcue_dirty_l ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$r_bcue_l_b\its.ka0902_cpu$v_bcue_dirty_l#define ka0902_cpu$v_bcue_valid_l ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$r_bcue_l_b\its.ka0902_cpu$v_bcue_valid_l#define ka0902_cpu$v_bcue_bc_edc_l ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_q/fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$r_bcue_l_\bits.ka0902_cpu$v_bcue_bc_edc_l#define ka0902_cpu$v_bcue_edc_synd_0 ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$r_bcue_\#l_bits.ka0902_cpu$v_bcue_edc_synd_0#define ka0902_cpu$v_bcue_edc_synd_2 ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_l_ol.ka0902_cpu$r_bcue_\#l_bits.ka0902_cpu$v_bcue_edc_synd_2{#define ka0902_cpu$l_bcue_h ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fr/ields.ka0902_cpu$r_bcue_fields_h_ol.ka0902_cpu$l_bcue_h#define ka0902_cpu$v_bcue_mpe_h ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_h_ol.ka0902_cpu$r_bcue_h_bit\s.ka0902_cpu$v_bcue_mpe_h#define ka0902_cpu$v_bcue_pe_h ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_h_ol.ka0902_cpu$r_bcue_h_bits\.ka0902_cpu$v_bcue_pe_h#define ka0902_cpu$v_bcue_munce_h ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_h_ol.ka0902_cpu$r_bcus/e_h_b\its.ka0902_cpu$v_bcue_munce_h#define ka0902_cpu$v_bcue_unce_h ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_h_ol.ka0902_cpu$r_bcue_h_bi\ts.ka0902_cpu$v_bcue_unce_h#define ka0902_cpu$v_bcue_bc_edc_h ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_h_ol.ka0902_cpu$r_bcue_h_\bits.ka0902_cpu$v_bcue_bc_edc_h#define ka0902_cpu$v_bcue_edc_synd_1 ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_h_ol.ka0902_cpu$r_bcue_\#t/h_bits.ka0902_cpu$v_bcue_edc_synd_1#define ka0902_cpu$v_bcue_edc_synd_3 ka0902_cpu$r_bcue_ol.ka0902_cpu$r_bcue_fields.ka0902_cpu$r_bcue_fields_h_ol.ka0902_cpu$r_bcue_\#h_bits.ka0902_cpu$v_bcue_edc_synd_3C#define ka0902_cpu$q_bcuea ka0902_cpu$r_bcuea_ol.ka0902_cpu$q_bcuea#define ka0902_cpu$l_bcuea_l ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cpu$r_bcuea_fields_l_ol.ka0902_cpu$l_bcuea_l#define ka0902_cpu$v_bcuea_bcmap_off_l ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cpu/u$r_bcuea_fields_l_ol.ka0902_cpu$r_\+bcuea_l_bits.ka0902_cpu$v_bcuea_bcmap_off_l#define ka0902_cpu$v_bcuea_ptp_l ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cpu$r_bcuea_fields_l_ol.ka0902_cpu$r_bcuea_\l_bits.ka0902_cpu$v_bcuea_ptp_l#define ka0902_cpu$v_bcuea_tp_l ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cpu$r_bcuea_fields_l_ol.ka0902_cpu$r_bcuea_l\_bits.ka0902_cpu$v_bcuea_tp_l#define ka0902_cpu$v_bcuea_tv_l ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cv/pu$r_bcuea_fields_l_ol.ka0902_cpu$r_bcuea_l\_bits.ka0902_cpu$v_bcuea_tv_l#define ka0902_cpu$v_bcuea_fill1_l ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cpu$r_bcuea_fields_l_ol.ka0902_cpu$r_bcue\#a_l_bits.ka0902_cpu$v_bcuea_fill1_l#define ka0902_cpu$l_bcuea_h ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cpu$r_bcuea_fields_h_ol.ka0902_cpu$l_bcuea_h#define ka0902_cpu$v_bcuea_bcmap_off_h ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cpu$r_bcuea_fields_h_ol.ka0902_cw/pu$r_\+bcuea_h_bits.ka0902_cpu$v_bcuea_bcmap_off_h#define ka0902_cpu$v_bcuea_ptp_h ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cpu$r_bcuea_fields_h_ol.ka0902_cpu$r_bcuea_\h_bits.ka0902_cpu$v_bcuea_ptp_h#define ka0902_cpu$v_bcuea_tp_h ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cpu$r_bcuea_fields_h_ol.ka0902_cpu$r_bcuea_h\_bits.ka0902_cpu$v_bcuea_tp_h#define ka0902_cpu$v_bcuea_tv_h ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cpu$r_bcuea_fields_h_ol.ka0902_x/cpu$r_bcuea_h\_bits.ka0902_cpu$v_bcuea_tv_h#define ka0902_cpu$v_bcuea_fill1_h ka0902_cpu$r_bcuea_ol.ka0902_cpu$r_bcuea_fields.ka0902_cpu$r_bcuea_fields_h_ol.ka0902_cpu$r_bcue\#a_h_bits.ka0902_cpu$v_bcuea_fill1_h@#define ka0902_cpu$q_dter ka0902_cpu$r_dter_ol.ka0902_cpu$q_dter{#define ka0902_cpu$l_dter_l ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_l_ol.ka0902_cpu$l_dter_l#define ka0902_cpu$v_dter_mdter_l ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dy/ter_fields_l_ol.ka0902_cpu$r_dter_l_b\its.ka0902_cpu$v_dter_mdter_l#define ka0902_cpu$v_dter_dter_l ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_l_ol.ka0902_cpu$r_dter_l_bi\ts.ka0902_cpu$v_dter_dter_l#define ka0902_cpu$v_dter_toff_l ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_l_ol.ka0902_cpu$r_dter_l_bi\ts.ka0902_cpu$v_dter_toff_l#define ka0902_cpu$v_dter_bank0_tag_l ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fielz/ds_l_ol.ka0902_cpu$r_dter\%_l_bits.ka0902_cpu$v_dter_bank0_tag_l#define ka0902_cpu$v_dter_bank0_par_l ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_l_ol.ka0902_cpu$r_dter\%_l_bits.ka0902_cpu$v_dter_bank0_par_l#define ka0902_cpu$v_dter_bank1_tag_l ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_l_ol.ka0902_cpu$r_dter\%_l_bits.ka0902_cpu$v_dter_bank1_tag_l#define ka0902_cpu$v_dter_bank1_par_l ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902{/_cpu$r_dter_fields_l_ol.ka0902_cpu$r_dter\%_l_bits.ka0902_cpu$v_dter_bank1_par_l{#define ka0902_cpu$l_dter_h ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_h_ol.ka0902_cpu$l_dter_h#define ka0902_cpu$v_dter_mdter_h ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_h_ol.ka0902_cpu$r_dter_h_b\its.ka0902_cpu$v_dter_mdter_h#define ka0902_cpu$v_dter_dter_h ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_h_ol.ka0902_cpu$r_dter_h_b|/i\ts.ka0902_cpu$v_dter_dter_h#define ka0902_cpu$v_dter_toff_h ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_h_ol.ka0902_cpu$r_dter_h_bi\ts.ka0902_cpu$v_dter_toff_h#define ka0902_cpu$v_dter_bank0_tag_h ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_h_ol.ka0902_cpu$r_dter\%_h_bits.ka0902_cpu$v_dter_bank0_tag_h#define ka0902_cpu$v_dter_bank0_par_h ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_h_ol.ka0902_cpu$r_dter\%}/_h_bits.ka0902_cpu$v_dter_bank0_par_h#define ka0902_cpu$v_dter_bank1_tag_h ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_h_ol.ka0902_cpu$r_dter\%_h_bits.ka0902_cpu$v_dter_bank1_tag_h#define ka0902_cpu$v_dter_bank1_par_h ka0902_cpu$r_dter_ol.ka0902_cpu$r_dter_fields.ka0902_cpu$r_dter_fields_h_ol.ka0902_cpu$r_dter\%_h_bits.ka0902_cpu$v_dter_bank1_par_hC#define ka0902_cpu$q_cbctl ka0902_cpu$r_cbctl_ol.ka0902_cpu$q_cbctl#define ka0902_cpu$l_cbctl_l ka0902_cpu$r_cbctl_~/ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_l_ol.ka0902_cpu$l_cbctl_l#define ka0902_cpu$v_cbctl_dwp_l ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_l_ol.ka0902_cpu$r_cbctl_\l_bits.ka0902_cpu$v_cbctl_dwp_l#define ka0902_cpu$v_cbctl_cawp_l ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_l_ol.ka0902_cpu$r_cbctl\!_l_bits.ka0902_cpu$v_cbctl_cawp_l#define ka0902_cpu$v_cbctl_epc_l ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka090/2_cpu$r_cbctl_fields_l_ol.ka0902_cpu$r_cbctl_\l_bits.ka0902_cpu$v_cbctl_epc_l#define ka0902_cpu$v_cbctl_frc_sh_l ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_l_ol.ka0902_cpu$r_cbc\%tl_l_bits.ka0902_cpu$v_cbctl_frc_sh_l#define ka0902_cpu$v_cbctl_cmder_id_l ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_l_ol.ka0902_cpu$r_c\)bctl_l_bits.ka0902_cpu$v_cbctl_cmder_id_l#define ka0902_cpu$v_cbctl_acm_l ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbct/l_fields.ka0902_cpu$r_cbctl_fields_l_ol.ka0902_cpu$r_cbctl_\l_bits.ka0902_cpu$v_cbctl_acm_l#define ka0902_cpu$v_cbctl_enb_ci_l ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_l_ol.ka0902_cpu$r_cbc\%tl_l_bits.ka0902_cpu$v_cbctl_enb_ci_l#define ka0902_cpu$v_cbctl_rd_l ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_l_ol.ka0902_cpu$r_cbctl_l\_bits.ka0902_cpu$v_cbctl_rd_l#define ka0902_cpu$v_cbctl_qw_2_sel_l ka0902_cpu$r_cbctl_ol.ka0902_cpu/$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_l_ol.ka0902_cpu$r_c\)bctl_l_bits.ka0902_cpu$v_cbctl_qw_2_sel_l#define ka0902_cpu$v_cbctl_sel_drack_l ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_l_ol.ka0902_cpu$r_\+cbctl_l_bits.ka0902_cpu$v_cbctl_sel_drack_l#define ka0902_cpu$l_cbctl_h ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_h_ol.ka0902_cpu$l_cbctl_h#define ka0902_cpu$v_cbctl_dwp_h ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_/cpu$r_cbctl_fields_h_ol.ka0902_cpu$r_cbctl_\h_bits.ka0902_cpu$v_cbctl_dwp_h#define ka0902_cpu$v_cbctl_cawp_h ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_h_ol.ka0902_cpu$r_cbctl\!_h_bits.ka0902_cpu$v_cbctl_cawp_h#define ka0902_cpu$v_cbctl_epc_h ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_h_ol.ka0902_cpu$r_cbctl_\h_bits.ka0902_cpu$v_cbctl_epc_h#define ka0902_cpu$v_cbctl_frc_sh_h ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka09/02_cpu$r_cbctl_fields_h_ol.ka0902_cpu$r_cbc\%tl_h_bits.ka0902_cpu$v_cbctl_frc_sh_h#define ka0902_cpu$v_cbctl_cmder_id_h ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_h_ol.ka0902_cpu$r_c\)bctl_h_bits.ka0902_cpu$v_cbctl_cmder_id_h#define ka0902_cpu$v_cbctl_acm_h ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_h_ol.ka0902_cpu$r_cbctl_\h_bits.ka0902_cpu$v_cbctl_acm_h#define ka0902_cpu$v_cbctl_enb_ci_h ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbc/tl_fields.ka0902_cpu$r_cbctl_fields_h_ol.ka0902_cpu$r_cbc\%tl_h_bits.ka0902_cpu$v_cbctl_enb_ci_h#define ka0902_cpu$v_cbctl_rd_h ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_h_ol.ka0902_cpu$r_cbctl_h\_bits.ka0902_cpu$v_cbctl_rd_h#define ka0902_cpu$v_cbctl_qw_2_sel_h ka0902_cpu$r_cbctl_ol.ka0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_h_ol.ka0902_cpu$r_c\)bctl_h_bits.ka0902_cpu$v_cbctl_qw_2_sel_h#define ka0902_cpu$v_cbctl_sel_drack_h ka0902_cpu$r_cbctl_ol.k/a0902_cpu$r_cbctl_fields.ka0902_cpu$r_cbctl_fields_h_ol.ka0902_cpu$r_\+cbctl_h_bits.ka0902_cpu$v_cbctl_sel_drack_h=#define ka0902_cpu$q_cbe ka0902_cpu$r_cbe_ol.ka0902_cpu$q_cbev#define ka0902_cpu$l_cbe_l ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$l_cbe_l#define ka0902_cpu$v_cbe_diag_l ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits.ka\0902_cpu$v_cbe_diag_l#define ka0902_cpu$v_cbe_cap_l ka0902_cpu$r_cb/e_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits.ka0\902_cpu$v_cbe_cap_l#define ka0902_cpu$v_cbe_mcap_l ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits.ka\0902_cpu$v_cbe_mcap_l#define ka0902_cpu$v_cbe_pe_wrd_l ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits.\ka0902_cpu$v_cbe_pe_wrd_l#define ka0902_cpu$v_cbe_mpe_wrd_l ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fiel/ds.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits\.ka0902_cpu$v_cbe_mpe_wrd_l#define ka0902_cpu$v_cbe_pe_rd_l ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits.k\a0902_cpu$v_cbe_pe_rd_l#define ka0902_cpu$v_cbe_mpe_rd_l ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits.\ka0902_cpu$v_cbe_mpe_rd_l#define ka0902_cpu$v_cbe_ca_pe_lw0 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_/fields_l_ol.ka0902_cpu$r_cbe_l_bits\.ka0902_cpu$v_cbe_ca_pe_lw0#define ka0902_cpu$v_cbe_ca_pe_lw2 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits\.ka0902_cpu$v_cbe_ca_pe_lw2#define ka0902_cpu$v_cbe_d_pe_lw0 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits.\ka0902_cpu$v_cbe_d_pe_lw0#define ka0902_cpu$v_cbe_d_pe_lw2 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka090/2_cpu$r_cbe_l_bits.\ka0902_cpu$v_cbe_d_pe_lw2#define ka0902_cpu$v_cbe_d_pe_lw4 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits.\ka0902_cpu$v_cbe_d_pe_lw4#define ka0902_cpu$v_cbe_d_pe_lw6 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits.\ka0902_cpu$v_cbe_d_pe_lw6#define ka0902_cpu$v_cbe_ca_nack_l ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits\/.ka0902_cpu$v_cbe_ca_nack_l#define ka0902_cpu$v_cbe_wr_data_nack_l ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l\%_bits.ka0902_cpu$v_cbe_wr_data_nack_l#define ka0902_cpu$v_cbe_mcount_l ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_bits.\ka0902_cpu$v_cbe_mcount_l#define ka0902_cpu$v_cbe_madr_valid_l ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_l_ol.ka0902_cpu$r_cbe_l_b\!its./ka0902_cpu$v_cbe_madr_valid_lv#define ka0902_cpu$l_cbe_h ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$l_cbe_h#define ka0902_cpu$v_cbe_diag_h ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits.ka\0902_cpu$v_cbe_diag_h#define ka0902_cpu$v_cbe_cap_h ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits.ka0\902_cpu$v_cbe_cap_h#define ka0902_cpu$v_cbe_mcap_h ka0902_c/pu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits.ka\0902_cpu$v_cbe_mcap_h#define ka0902_cpu$v_cbe_pe_wrd_h ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits.\ka0902_cpu$v_cbe_pe_wrd_h#define ka0902_cpu$v_cbe_mpe_wrd_h ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits\.ka0902_cpu$v_cbe_mpe_wrd_h#define ka0902_cpu$v_cbe_pe_rd_h ka0902_cpu$r_cbe_ol.ka0902_cp/u$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits.k\a0902_cpu$v_cbe_pe_rd_h#define ka0902_cpu$v_cbe_mpe_rd_h ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits.\ka0902_cpu$v_cbe_mpe_rd_h#define ka0902_cpu$v_cbe_ca_pe_lw1 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits\.ka0902_cpu$v_cbe_ca_pe_lw1#define ka0902_cpu$v_cbe_ca_pe_lw3 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0/902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits\.ka0902_cpu$v_cbe_ca_pe_lw3#define ka0902_cpu$v_cbe_d_pe_lw1 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits.\ka0902_cpu$v_cbe_d_pe_lw1#define ka0902_cpu$v_cbe_d_pe_lw3 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits.\ka0902_cpu$v_cbe_d_pe_lw3#define ka0902_cpu$v_cbe_d_pe_lw5 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_field/s_h_ol.ka0902_cpu$r_cbe_h_bits.\ka0902_cpu$v_cbe_d_pe_lw5#define ka0902_cpu$v_cbe_d_pe_lw7 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits.\ka0902_cpu$v_cbe_d_pe_lw7#define ka0902_cpu$v_cbe_undefined ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits\.ka0902_cpu$v_cbe_undefined#define ka0902_cpu$v_cbe_undefined2 ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cp/u$r_cbe_h_bit\s.ka0902_cpu$v_cbe_undefined2#define ka0902_cpu$v_cbe_mcount_h ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_bits.\ka0902_cpu$v_cbe_mcount_h#define ka0902_cpu$v_cbe_madr_valid_h ka0902_cpu$r_cbe_ol.ka0902_cpu$r_cbe_fields.ka0902_cpu$r_cbe_fields_h_ol.ka0902_cpu$r_cbe_h_b\!its.ka0902_cpu$v_cbe_madr_valid_hC#define ka0902_cpu$q_cbeal ka0902_cpu$r_cbeal_ol.ka0902_cpu$q_cbeal#define ka0902_cpu$l_cbeal_l ka0902_cpu$r_cbeal_ol.ka090/2_cpu$r_cbeal_fields.ka0902_cpu$r_cbeal_fields_l_ol.ka0902_cpu$l_cbeal_l#define ka0902_cpu$v_cbeal_sbo_l ka0902_cpu$r_cbeal_ol.ka0902_cpu$r_cbeal_fields.ka0902_cpu$r_cbeal_fields_l_ol.ka0902_cpu$r_cbeal_\l_bits.ka0902_cpu$v_cbeal_sbo_l#define ka0902_cpu$v_cbeal_addr_cad_l ka0902_cpu$r_cbeal_ol.ka0902_cpu$r_cbeal_fields.ka0902_cpu$r_cbeal_fields_l_ol.ka0902_cpu$r_c\)beal_l_bits.ka0902_cpu$v_cbeal_addr_cad_l#define ka0902_cpu$l_cbeal_h ka0902_cpu$r_cbeal_ol.ka0902_cpu$r_cbeal_fields.ka0902_cp/u$r_cbeal_fields_h_ol.ka0902_cpu$l_cbeal_h#define ka0902_cpu$v_cbeal_sbo_h ka0902_cpu$r_cbeal_ol.ka0902_cpu$r_cbeal_fields.ka0902_cpu$r_cbeal_fields_h_ol.ka0902_cpu$r_cbeal_\h_bits.ka0902_cpu$v_cbeal_sbo_h#define ka0902_cpu$v_cbeal_addr_cad_h ka0902_cpu$r_cbeal_ol.ka0902_cpu$r_cbeal_fields.ka0902_cpu$r_cbeal_fields_h_ol.ka0902_cpu$r_c\)beal_h_bits.ka0902_cpu$v_cbeal_addr_cad_hC#define ka0902_cpu$q_cbeah ka0902_cpu$r_cbeah_ol.ka0902_cpu$q_cbeah#define ka0902_cpu$l_cbeah_l ka0902_cpu$r_cbea/h_ol.ka0902_cpu$r_cbeah_fields.ka0902_cpu$r_cbeah_fields_l_ol.ka0902_cpu$l_cbeah_l#define ka0902_cpu$v_cbeah_sb0_l ka0902_cpu$r_cbeah_ol.ka0902_cpu$r_cbeah_fields.ka0902_cpu$r_cbeah_fields_l_ol.ka0902_cpu$r_cbeah_\l_bits.ka0902_cpu$v_cbeah_sb0_l#define ka0902_cpu$v_cbeah_ea_l ka0902_cpu$r_cbeah_ol.ka0902_cpu$r_cbeah_fields.ka0902_cpu$r_cbeah_fields_l_ol.ka0902_cpu$r_cbeah_l\_bits.ka0902_cpu$v_cbeah_ea_l#define ka0902_cpu$v_cbeah_t_type_l ka0902_cpu$r_cbeah_ol.ka0902_cpu$r_cbeah_fields.ka09/02_cpu$r_cbeah_fields_l_ol.ka0902_cpu$r_cbe\%ah_l_bits.ka0902_cpu$v_cbeah_t_type_l#define ka0902_cpu$v_cbeah_cmdr_id_l ka0902_cpu$r_cbeah_ol.ka0902_cpu$r_cbeah_fields.ka0902_cpu$r_cbeah_fields_l_ol.ka0902_cpu$r_cb\'eah_l_bits.ka0902_cpu$v_cbeah_cmdr_id_l#define ka0902_cpu$v_cbeah_sb1_l ka0902_cpu$r_cbeah_ol.ka0902_cpu$r_cbeah_fields.ka0902_cpu$r_cbeah_fields_l_ol.ka0902_cpu$r_cbeah_\l_bits.ka0902_cpu$v_cbeah_sb1_l#define ka0902_cpu$l_cbeah_h ka0902_cpu$r_cbeah_ol.ka0902_cpu$r_cbeah_fields/.ka0902_cpu$r_cbeah_fields_h_ol.ka0902_cpu$l_cbeah_h#define ka0902_cpu$v_cbeah_sb0_h ka0902_cpu$r_cbeah_ol.ka0902_cpu$r_cbeah_fields.ka0902_cpu$r_cbeah_fields_h_ol.ka0902_cpu$r_cbeah_\h_bits.ka0902_cpu$v_cbeah_sb0_h#define ka0902_cpu$v_cbeah_ea_h ka0902_cpu$r_cbeah_ol.ka0902_cpu$r_cbeah_fields.ka0902_cpu$r_cbeah_fields_h_ol.ka0902_cpu$r_cbeah_h\_bits.ka0902_cpu$v_cbeah_ea_h#define ka0902_cpu$v_cbeah_t_type_h ka0902_cpu$r_cbeah_ol.ka0902_cpu$r_cbeah_fields.ka0902_cpu$r_cbeah_fields_h_ol.ka0/902_cpu$r_cbe\%ah_h_bits.ka0902_cpu$v_cbeah_t_type_h#define ka0902_cpu$v_cbeah_cmdr_id_h ka0902_cpu$r_cbeah_ol.ka0902_cpu$r_cbeah_fields.ka0902_cpu$r_cbeah_fields_h_ol.ka0902_cpu$r_cb\'eah_h_bits.ka0902_cpu$v_cbeah_cmdr_id_h#define ka0902_cpu$v_cbeah_sb1_h ka0902_cpu$r_cbeah_ol.ka0902_cpu$r_cbeah_fields.ka0902_cpu$r_cbeah_fields_h_ol.ka0902_cpu$r_cbeah_\h_bits.ka0902_cpu$v_cbeah_sb1_h@#define ka0902_cpu$q_pmbx ka0902_cpu$r_pmbx_ol.ka0902_cpu$q_pmbx{#define ka0902_cpu$l_pmbx_l ka0902_cpu$r/_pmbx_ol.ka0902_cpu$r_pmbx_fields.ka0902_cpu$r_pmbx_fields_l_ol.ka0902_cpu$l_pmbx_l#define ka0902_cpu$v_pmbx_fill1_l ka0902_cpu$r_pmbx_ol.ka0902_cpu$r_pmbx_fields.ka0902_cpu$r_pmbx_fields_l_ol.ka0902_cpu$r_pmbx_l_b\its.ka0902_cpu$v_pmbx_fill1_l{#define ka0902_cpu$l_pmbx_h ka0902_cpu$r_pmbx_ol.ka0902_cpu$r_pmbx_fields.ka0902_cpu$r_pmbx_fields_h_ol.ka0902_cpu$l_pmbx_h#define ka0902_cpu$v_pmbx_fill1_h ka0902_cpu$r_pmbx_ol.ka0902_cpu$r_pmbx_fields.ka0902_cpu$r_pmbx_fields_h_ol.ka0902_cpu$r_pmbx_/h_b\its.ka0902_cpu$v_pmbx_fill1_h@#define ka0902_cpu$q_ipir ka0902_cpu$r_ipir_ol.ka0902_cpu$q_ipir{#define ka0902_cpu$l_ipir_l ka0902_cpu$r_ipir_ol.ka0902_cpu$r_ipir_fields.ka0902_cpu$r_ipir_fields_l_ol.ka0902_cpu$l_ipir_l#define ka0902_cpu$v_ipir_undefined ka0902_cpu$r_ipir_ol.ka0902_cpu$r_ipir_fields.ka0902_cpu$r_ipir_fields_l_ol.ka0902_cpu$r_ipir_l\!_bits.ka0902_cpu$v_ipir_undefined{#define ka0902_cpu$l_ipir_h ka0902_cpu$r_ipir_ol.ka0902_cpu$r_ipir_fields.ka0902_cpu$r_ipir_fields_h_ol.ka/0902_cpu$l_ipir_h#define ka0902_cpu$v_ipir_req_int_cpu ka0902_cpu$r_ipir_ol.ka0902_cpu$r_ipir_fields.ka0902_cpu$r_ipir_fields_h_ol.ka0902_cpu$r_ipir\%_h_bits.ka0902_cpu$v_ipir_req_int_cpu#define ka0902_cpu$v_ipir_req_node_halt ka0902_cpu$r_ipir_ol.ka0902_cpu$r_ipir_fields.ka0902_cpu$r_ipir_fields_h_ol.ka0902_cpu$r_ip\)ir_h_bits.ka0902_cpu$v_ipir_req_node_halt=#define ka0902_cpu$q_sic ka0902_cpu$r_sic_ol.ka0902_cpu$q_sicv#define ka0902_cpu$l_sic_l ka0902_cpu$r_sic_ol.ka0902_cpu$r_sic_fields/.ka0902_cpu$r_sic_fields_l_ol.ka0902_cpu$l_sic_l#define ka0902_cpu$v_sic_undefined0 ka0902_cpu$r_sic_ol.ka0902_cpu$r_sic_fields.ka0902_cpu$r_sic_fields_l_ol.ka0902_cpu$r_sic_l_bit\s.ka0902_cpu$v_sic_undefined0#define ka0902_cpu$v_sic_undefined1 ka0902_cpu$r_sic_ol.ka0902_cpu$r_sic_fields.ka0902_cpu$r_sic_fields_l_ol.ka0902_cpu$r_sic_l_bit\s.ka0902_cpu$v_sic_undefined1#define ka0902_cpu$v_sic_eic ka0902_cpu$r_sic_ol.ka0902_cpu$r_sic_fields.ka0902_cpu$r_sic_fields_l_ol.ka0902_cpu$r_sic_l_bit/s.ka090\2_cpu$v_sic_eic#define ka0902_cpu$v_sic_undefined2 ka0902_cpu$r_sic_ol.ka0902_cpu$r_sic_fields.ka0902_cpu$r_sic_fields_l_ol.ka0902_cpu$r_sic_l_bit\s.ka0902_cpu$v_sic_undefined2v#define ka0902_cpu$l_sic_h ka0902_cpu$r_sic_ol.ka0902_cpu$r_sic_fields.ka0902_cpu$r_sic_fields_h_ol.ka0902_cpu$l_sic_h#define ka0902_cpu$v_sic_it_iclear ka0902_cpu$r_sic_ol.ka0902_cpu$r_sic_fields.ka0902_cpu$r_sic_fields_h_ol.ka0902_cpu$r_sic_h_bits\.ka0902_cpu$v_sic_it_iclear#define ka0902_cpu$v_sic_sys/_evt_clr ka0902_cpu$r_sic_ol.ka0902_cpu$r_sic_fields.ka0902_cpu$r_sic_fields_h_ol.ka0902_cpu$r_sic_h_bi\ts.ka0902_cpu$v_sic_sys_evt_clr#define ka0902_cpu$v_sic_undefined3 ka0902_cpu$r_sic_ol.ka0902_cpu$r_sic_fields.ka0902_cpu$r_sic_fields_h_ol.ka0902_cpu$r_sic_h_bit\s.ka0902_cpu$v_sic_undefined3#define ka0902_cpu$v_sic_node_halt_clr ka0902_cpu$r_sic_ol.ka0902_cpu$r_sic_fields.ka0902_cpu$r_sic_fields_h_ol.ka0902_cpu$r_sic_h_\#bits.ka0902_cpu$v_sic_node_halt_clr@#define ka0902_cpu$q_adlk ka/0902_cpu$r_adlk_ol.ka0902_cpu$q_adlk{#define ka0902_cpu$l_adlk_l ka0902_cpu$r_adlk_ol.ka0902_cpu$r_adlk_fields.ka0902_cpu$r_adlk_fields_l_ol.ka0902_cpu$l_adlk_l#define ka0902_cpu$v_adlk_la_v_l ka0902_cpu$r_adlk_ol.ka0902_cpu$r_adlk_fields.ka0902_cpu$r_adlk_fields_l_ol.ka0902_cpu$r_adlk_l_bi\ts.ka0902_cpu$v_adlk_la_v_l#define ka0902_cpu$v_adlk_la_l ka0902_cpu$r_adlk_ol.ka0902_cpu$r_adlk_fields.ka0902_cpu$r_adlk_fields_l_ol.ka0902_cpu$r_adlk_l_bits\.ka0902_cpu$v_adlk_la_l{#define ka0902_cpu/$l_adlk_h ka0902_cpu$r_adlk_ol.ka0902_cpu$r_adlk_fields.ka0902_cpu$r_adlk_fields_h_ol.ka0902_cpu$l_adlk_h#define ka0902_cpu$v_adlk_la_v_h ka0902_cpu$r_adlk_ol.ka0902_cpu$r_adlk_fields.ka0902_cpu$r_adlk_fields_h_ol.ka0902_cpu$r_adlk_h_bi\ts.ka0902_cpu$v_adlk_la_v_h#define ka0902_cpu$v_adlk_la_h ka0902_cpu$r_adlk_ol.ka0902_cpu$r_adlk_fields.ka0902_cpu$r_adlk_fields_h_ol.ka0902_cpu$r_adlk_h_bits\.ka0902_cpu$v_adlk_la_hC#define ka0902_cpu$q_madrl ka0902_cpu$r_madrl_ol.ka0902_cpu$q_madrl#def/ine ka0902_cpu$l_madrl_l ka0902_cpu$r_madrl_ol.ka0902_cpu$r_madrl_fields.ka0902_cpu$r_madrl_fields_l_ol.ka0902_cpu$l_madrl_l#define ka0902_cpu$v_madrl_valid_l ka0902_cpu$r_madrl_ol.ka0902_cpu$r_madrl_fields.ka0902_cpu$r_madrl_fields_l_ol.ka0902_cpu$r_madr\#l_l_bits.ka0902_cpu$v_madrl_valid_l#define ka0902_cpu$v_madrl_t_type_l ka0902_cpu$r_madrl_ol.ka0902_cpu$r_madrl_fields.ka0902_cpu$r_madrl_fields_l_ol.ka0902_cpu$r_mad\%rl_l_bits.ka0902_cpu$v_madrl_t_type_l#define ka0902_cpu$v_madrl_address/_l ka0902_cpu$r_madrl_ol.ka0902_cpu$r_madrl_fields.ka0902_cpu$r_madrl_fields_l_ol.ka0902_cpu$r_ma\'drl_l_bits.ka0902_cpu$v_madrl_address_l#define ka0902_cpu$l_madrl_h ka0902_cpu$r_madrl_ol.ka0902_cpu$r_madrl_fields.ka0902_cpu$r_madrl_fields_h_ol.ka0902_cpu$l_madrl_h#define ka0902_cpu$v_madrl_valid_h ka0902_cpu$r_madrl_ol.ka0902_cpu$r_madrl_fields.ka0902_cpu$r_madrl_fields_h_ol.ka0902_cpu$r_madr\#l_h_bits.ka0902_cpu$v_madrl_valid_h#define ka0902_cpu$v_madrl_t_type_h ka0902_cpu$r_madrl_ol.ka09/02_cpu$r_madrl_fields.ka0902_cpu$r_madrl_fields_h_ol.ka0902_cpu$r_mad\%rl_h_bits.ka0902_cpu$v_madrl_t_type_h#define ka0902_cpu$v_madrl_address_h ka0902_cpu$r_madrl_ol.ka0902_cpu$r_madrl_fields.ka0902_cpu$r_madrl_fields_h_ol.ka0902_cpu$r_ma\'drl_h_bits.ka0902_cpu$v_madrl_address_hF#define ka0902_cpu$q_crrevs ka0902_cpu$r_crrevs_ol.ka0902_cpu$q_crrevs#define ka0902_cpu$l_crrevs_l ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_l_ol.ka0902_cpu$l_crrevs\_l#define /ka0902_cpu$v_crrevs_rev_l ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_l_ol.ka0902_cpu$r_cr\%revs_l_bits.ka0902_cpu$v_crrevs_rev_l#define ka0902_cpu$v_crrevs_cpu_mode_l ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_l_ol.ka0902_cpu\/$r_crrevs_l_bits.ka0902_cpu$v_crrevs_cpu_mode_l#define ka0902_cpu$v_crrevs_c3_speed_l ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_l_ol.ka0902_cpu\/$r_crrevs_l_bits.ka090/2_cpu$v_crrevs_c3_speed_l#define ka0902_cpu$v_crrevs_sb0_l ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_l_ol.ka0902_cpu$r_cr\%revs_l_bits.ka0902_cpu$v_crrevs_sb0_l#define ka0902_cpu$v_crrevs_io_retry_l ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_l_ol.ka0902_cpu\/$r_crrevs_l_bits.ka0902_cpu$v_crrevs_io_retry_l#define ka0902_cpu$v_crrevs_pch_inv_l ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_l_ol./ka0902_cpu$\-r_crrevs_l_bits.ka0902_cpu$v_crrevs_pch_inv_l#define ka0902_cpu$l_crrevs_h ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_h_ol.ka0902_cpu$l_crrevs\_h#define ka0902_cpu$v_crrevs_rev_h ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_h_ol.ka0902_cpu$r_cr\%revs_h_bits.ka0902_cpu$v_crrevs_rev_h#define ka0902_cpu$v_crrevs_cpu_mode_h ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_h_ol.ka0902_cpu\//$r_crrevs_h_bits.ka0902_cpu$v_crrevs_cpu_mode_h#define ka0902_cpu$v_crrevs_c3_speed_h ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_h_ol.ka0902_cpu\/$r_crrevs_h_bits.ka0902_cpu$v_crrevs_c3_speed_h#define ka0902_cpu$v_crrevs_sb0_h ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_h_ol.ka0902_cpu$r_cr\%revs_h_bits.ka0902_cpu$v_crrevs_sb0_h#define ka0902_cpu$v_crrevs_io_retry_h ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_ /cpu$r_crrevs_fields_h_ol.ka0902_cpu\/$r_crrevs_h_bits.ka0902_cpu$v_crrevs_io_retry_h#define ka0902_cpu$v_crrevs_pch_inv_h ka0902_cpu$r_crrevs_ol.ka0902_cpu$r_crrevs_fields.ka0902_cpu$r_crrevs_fields_h_ol.ka0902_cpu$\-r_crrevs_h_bits.ka0902_cpu$v_crrevs_pch_inv_h"#endif /* #if !defined(__VAXC) */ #define KA0902_CPU$K_LENGTH 488N/* */N/* Sable Memory Module register definitions */N/* / */!#define KA0902_SMM$M_CME_ES_L 0x1!#define KA0902_SMM$M_CME_SE_L 0x2$#define KA0902_SMM$M_CME_CA_PE_L 0x4%#define KA0902_SMM$M_CME_MCA_PE_L 0x8%#define KA0902_SMM$M_CME_WD_PE_L 0x10&#define KA0902_SMM$M_CME_MWD_PE_L 0x20(#define KA0902_SMM$M_CME_CA_PE_LW0 0x100(#define KA0902_SMM$M_CME_CA_PE_LW2 0x200'#define KA0902_SMM$M_CME_D_PE_LW0 0x400'#define KA0902_SMM$M_CME_D_PE_LW2 0x800(#define KA0902_SMM$M_CME_D_PE_/LW4 0x1000(#define KA0902_SMM$M_CME_D_PE_LW6 0x2000&#define KA0902_SMM$M_CME_EUE_L 0x10000'#define KA0902_SMM$M_CME_MEUE_L 0x20000&#define KA0902_SMM$M_CME_ECE_L 0x40000'#define KA0902_SMM$M_CME_MECE_L 0x80000!#define KA0902_SMM$M_CME_ES_H 0x1!#define KA0902_SMM$M_CME_SE_H 0x2$#define KA0902_SMM$M_CME_CA_PE_H 0x4%#define KA0902_SMM$M_CME_MCA_PE_H 0x8%#define KA0902_SMM$M_CME_WD_PE_H 0x10&#define KA0902_SMM$M_CME_MWD_PE_H 0x20(#define KA0902_SMM$M_CME_CA_PE_LW1 0x100(#define KA0902_S /MM$M_CME_CA_PE_LW3 0x200'#define KA0902_SMM$M_CME_D_PE_LW1 0x400'#define KA0902_SMM$M_CME_D_PE_LW3 0x800(#define KA0902_SMM$M_CME_D_PE_LW5 0x1000(#define KA0902_SMM$M_CME_D_PE_LW7 0x2000&#define KA0902_SMM$M_CME_EUE_H 0x10000'#define KA0902_SMM$M_CME_MEUE_H 0x20000&#define KA0902_SMM$M_CME_ECE_H 0x40000'#define KA0902_SMM$M_CME_MECE_H 0x80000##define KA0902_SMM$M_CNFG_MID_L 0x3(#define KA0902_SMM$M_CNFG_DRAM_ACC_L 0x8&#define KA0902_SMM$M_CNFG_MSIZE_L 0xF0&#define KA0902_SMM$M_CNFG_DI /AG_L 0x100+#define KA0902_SMM$M_CNFG_CSIC_REV_L 0xF000+#define KA0902_SMM$M_CNFG_ALT_CSR_L 0x10000(#define KA0902_SMM$M_CNFG_ILVM_L 0xC0000)#define KA0902_SMM$M_CNFG_ILVU_L 0x300000/#define KA0902_SMM$M_CNFG_BASE_ADR_L 0x7F800000.#define KA0902_SMM$M_CNFG_MEM_ENA_L 0x80000000##define KA0902_SMM$M_CNFG_MID_H 0x3(#define KA0902_SMM$M_CNFG_DRAM_ACC_H 0x8&#define KA0902_SMM$M_CNFG_MSIZE_H 0xF0&#define KA0902_SMM$M_CNFG_DIAG_H 0x100+#define KA0902_SMM$M_CNFG_CSIC_REV_H 0xF000+#define KA09 /02_SMM$M_CNFG_ALT_CSR_H 0x10000(#define KA0902_SMM$M_CNFG_ILVM_H 0xC0000)#define KA0902_SMM$M_CNFG_ILVU_H 0x300000/#define KA0902_SMM$M_CNFG_BASE_ADR_H 0x7F800000.#define KA0902_SMM$M_CNFG_MEM_ENA_H 0x80000000,#define KA0902_SMM$M_EDC1_READ_CBITS_L 0xFFF.#define KA0902_SMM$M_EDC1_WR_CBITS_L 0xFFF0000,#define KA0902_SMM$M_EDC1_READ_CBITS_H 0xFFF.#define KA0902_SMM$M_EDC1_WR_CBITS_H 0xFFF0000*#define KA0902_SMM$M_EDC2_SYNDROME_L 0xFFF*#define KA0902_SMM$M_EDC2_SYNDROME_H 0xFFF&#define KA09 /02_SMM$M_EDCTL_SRB_L 0xFFF(#define KA0902_SMM$M_EDCTL_USCB_L 0x1000)#define KA0902_SMM$M_EDCTL_USWCB_L 0x2000(#define KA0902_SMM$M_EDCTL_DIPC_L 0x4000*#define KA0902_SMM$M_EDCTL_ENB_ES_L 0x8000+#define KA0902_SMM$M_EDCTL_SWCB_L 0xFFF0000,#define KA0902_SMM$M_EDCTL_CRDP_L 0x100000000#define KA0902_SMM$M_EDCTL_ENB_CRDR_L 0x200000000#define KA0902_SMM$M_EDCTL_DEDCCORR_L 0x400000002#define KA0902_SMM$M_EDCTL_DEDCREPORT_L 0x80000000&#define KA0902_SMM$M_EDCTL_SRB_H 0xFFF(#define KA0902_SMM$M_E /DCTL_USCB_H 0x1000)#define KA0902_SMM$M_EDCTL_USWCB_H 0x2000(#define KA0902_SMM$M_EDCTL_DIPC_H 0x4000*#define KA0902_SMM$M_EDCTL_ENB_ES_H 0x8000+#define KA0902_SMM$M_EDCTL_SWCB_H 0xFFF0000,#define KA0902_SMM$M_EDCTL_CRDP_H 0x100000000#define KA0902_SMM$M_EDCTL_ENB_CRDR_H 0x200000000#define KA0902_SMM$M_EDCTL_DEDCCORR_H 0x400000002#define KA0902_SMM$M_EDCTL_DEDCREPORT_H 0x80000000%#define KA0902_SMM$M_SBCTRL_DSD_L 0x1%#define KA0902_SMM$M_SBCTRL_DSH_L 0x2%#define KA0902_SMM$M_SBCTRL_DSF_/L 0x4%#define KA0902_SMM$M_SBCTRL_DSI_L 0x8'#define KA0902_SMM$M_SBCTRL_ERWD_L 0x10&#define KA0902_SMM$M_SBCTRL_FHB_L 0x20(#define KA0902_SMM$M_SBCTRL_FILL1_L 0xC0(#define KA0902_SMM$M_SBCTRL_HBSM_L 0x100(#define KA0902_SMM$M_SBCTRL_HBHF_L 0x200&#define KA0902_SMM$M_SBCTRL_FL_L 0x400%#define KA0902_SMM$M_SBCTRL_DSD_H 0x1%#define KA0902_SMM$M_SBCTRL_DSH_H 0x2%#define KA0902_SMM$M_SBCTRL_DSF_H 0x4%#define KA0902_SMM$M_SBCTRL_DSI_H 0x8'#define KA0902_SMM$M_SBCTRL_ERWD_H 0x10&#define /KA0902_SMM$M_SBCTRL_FHB_H 0x20(#define KA0902_SMM$M_SBCTRL_FILL1_H 0xC0(#define KA0902_SMM$M_SBCTRL_HBSM_H 0x100(#define KA0902_SMM$M_SBCTRL_HBHF_H 0x200&#define KA0902_SMM$M_SBCTRL_FL_H 0x400$#define KA0902_SMM$M_RCTRL_RC_L 0xFF*#define KA0902_SMM$M_RCTRL_REF_ENB_L 0x100'#define KA0902_SMM$M_RCTRL_NUT_L 0x1000'#define KA0902_SMM$M_RCTRL_HIT_L 0x2000$#define KA0902_SMM$M_RCTRL_RC_H 0xFF*#define KA0902_SMM$M_RCTRL_REF_ENB_H 0x100'#define KA0902_SMM$M_RCTRL_NUT_H 0x1000'#define KA0902_SMM/$M_RCTRL_HIT_H 0x2000&#define KA0902_SMM$M_CRDCTL_SM_L 0xFFF'#define KA0902_SMM$M_CRDCTL_BS_L 0x3000(#define KA0902_SMM$M_CRDCTL_CFE_L 0x4000&#define KA0902_SMM$M_CRDCTL_SM_H 0xFFF'#define KA0902_SMM$M_CRDCTL_BS_H 0x3000(#define KA0902_SMM$M_CRDCTL_CFE_H 0x4000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0902_smm {N/* Sable M /emory Module CSR0 Error Register */#pragma __nomember_alignment __union {! __int64 ka0902_smm$q_cme; __struct { __union {0 unsigned int ka0902_smm$l_cme_l; __struct {7 unsigned ka0902_smm$v_cme_es_l : 1;7 unsigned ka0902_smm$v_cme_se_l : 1;: unsigned ka0902_smm$v_cme_ca_pe_l : 1;; unsigned ka0902_smm$v_cme_mca_pe /_l : 1;: unsigned ka0902_smm$v_cme_wd_pe_l : 1;; unsigned ka0902_smm$v_cme_mwd_pe_l : 1;: unsigned ka0902_smm$v_cme_fill1_l : 2;< unsigned ka0902_smm$v_cme_ca_pe_lw0 : 1;< unsigned ka0902_smm$v_cme_ca_pe_lw2 : 1;; unsigned ka0902_smm$v_cme_d_pe_lw0 : 1;; unsigned ka0902_smm$v_cme_d_pe_lw2 : 1;; unsigned ka0902_smm$v_cme_d_pe_lw4 : 1;; / unsigned ka0902_smm$v_cme_d_pe_lw6 : 1;: unsigned ka0902_smm$v_cme_fill2_l : 2;8 unsigned ka0902_smm$v_cme_eue_l : 1;9 unsigned ka0902_smm$v_cme_meue_l : 1;8 unsigned ka0902_smm$v_cme_ece_l : 1;9 unsigned ka0902_smm$v_cme_mece_l : 1;; unsigned ka0902_smm$v_cme_fill3_l : 12;. } ka0902_smm$r_cme_l_bits;/ } ka0902_smm$r_cme_fields_ /l_ol; __union {0 unsigned int ka0902_smm$l_cme_h; __struct {7 unsigned ka0902_smm$v_cme_es_h : 1;7 unsigned ka0902_smm$v_cme_se_h : 1;: unsigned ka0902_smm$v_cme_ca_pe_h : 1;; unsigned ka0902_smm$v_cme_mca_pe_h : 1;: unsigned ka0902_smm$v_cme_wd_pe_h : 1;; unsigned ka0902_smm$v_cme_mwd_pe_h : 1;8 unsigned ka090 /2_smm$v_cme_fill4 : 2;< unsigned ka0902_smm$v_cme_ca_pe_lw1 : 1;< unsigned ka0902_smm$v_cme_ca_pe_lw3 : 1;; unsigned ka0902_smm$v_cme_d_pe_lw1 : 1;; unsigned ka0902_smm$v_cme_d_pe_lw3 : 1;; unsigned ka0902_smm$v_cme_d_pe_lw5 : 1;; unsigned ka0902_smm$v_cme_d_pe_lw7 : 1;8 unsigned ka0902_smm$v_cme_fill5 : 2;8 unsigned ka0902_smm$v_cme_eue_h /: 1;9 unsigned ka0902_smm$v_cme_meue_h : 1;8 unsigned ka0902_smm$v_cme_ece_h : 1;9 unsigned ka0902_smm$v_cme_mece_h : 1;9 unsigned ka0902_smm$v_cme_fill6 : 12;. } ka0902_smm$r_cme_h_bits;/ } ka0902_smm$r_cme_fields_h_ol;& } ka0902_smm$r_cme_fields; } ka0902_smm$r_cme_ol;" char ka0902_smm$b_fill43 [24];N/* Sable Memory Module CSR1 Command Trap 1 / */ __union {# __int64 ka0902_smm$q_trap1; __struct { __union {2 unsigned int ka0902_smm$l_trap1_l; __struct {= unsigned ka0902_smm$v_trap1_fill1_l : 32;0 } ka0902_smm$r_trap1_l_bits;1 } ka0902_smm$r_trap1_fields_l_ol; __union {2 unsigned int ka0902_smm$l_trap1_h; __struct {= unsigned / ka0902_smm$v_trap1_fill1_h : 32;0 } ka0902_smm$r_trap1_h_bits;1 } ka0902_smm$r_trap1_fields_h_ol;( } ka0902_smm$r_trap1_fields; } ka0902_smm$r_trap1_ol;" char ka0902_smm$b_fill44 [24];N/* Sable Memory Module CSR2 Command Trap 2 */ __union {# __int64 ka0902_smm$q_trap2; __struct { __union {2 unsigned int ka0902_smm$l_trap2_l; __struct / {= unsigned ka0902_smm$v_trap2_fill1_l : 32;0 } ka0902_smm$r_trap2_l_bits;1 } ka0902_smm$r_trap2_fields_l_ol; __union {2 unsigned int ka0902_smm$l_trap2_h; __struct {= unsigned ka0902_smm$v_trap2_fill1_h : 32;0 } ka0902_smm$r_trap2_h_bits;1 } ka0902_smm$r_trap2_fields_h_ol;( } ka0902_smm$r_trap2_fields; } ka0902_smm /$r_trap2_ol;" char ka0902_smm$b_fill45 [24];N/* Sable Memory Module CSR3 Configuration */ __union {" __int64 ka0902_smm$q_cnfg; __struct { __union {1 unsigned int ka0902_smm$l_cnfg_l; __struct {9 unsigned ka0902_smm$v_cnfg_mid_l : 2;; unsigned ka0902_smm$v_cnfg_fill1_l : 1;> unsigned ka0902_smm$v_cnfg_dram_acc_l : 1;; / unsigned ka0902_smm$v_cnfg_msize_l : 4;: unsigned ka0902_smm$v_cnfg_diag_l : 1;; unsigned ka0902_smm$v_cnfg_fill2_l : 3;> unsigned ka0902_smm$v_cnfg_csic_rev_l : 4;= unsigned ka0902_smm$v_cnfg_alt_csr_l : 1;; unsigned ka0902_smm$v_cnfg_fill3_l : 1;: unsigned ka0902_smm$v_cnfg_ilvm_l : 2;: unsigned ka0902_smm$v_cnfg_ilvu_l : 2;; un /signed ka0902_smm$v_cnfg_fill4_l : 1;> unsigned ka0902_smm$v_cnfg_base_adr_l : 8;= unsigned ka0902_smm$v_cnfg_mem_ena_l : 1;/ } ka0902_smm$r_cnfg_l_bits;0 } ka0902_smm$r_cnfg_fields_l_ol; __union {1 unsigned int ka0902_smm$l_cnfg_h; __struct {9 unsigned ka0902_smm$v_cnfg_mid_h : 2;; unsigned ka0902_smm$v_cnfg_fill1_h : 1;> / unsigned ka0902_smm$v_cnfg_dram_acc_h : 1;; unsigned ka0902_smm$v_cnfg_msize_h : 4;: unsigned ka0902_smm$v_cnfg_diag_h : 1;; unsigned ka0902_smm$v_cnfg_fill2_h : 3;> unsigned ka0902_smm$v_cnfg_csic_rev_h : 4;= unsigned ka0902_smm$v_cnfg_alt_csr_h : 1;; unsigned ka0902_smm$v_cnfg_fill3_h : 1;: unsigned ka0902_smm$v_cnfg_ilvm_h : 2;: / unsigned ka0902_smm$v_cnfg_ilvu_h : 2;; unsigned ka0902_smm$v_cnfg_fill4_h : 1;> unsigned ka0902_smm$v_cnfg_base_adr_h : 8;= unsigned ka0902_smm$v_cnfg_mem_ena_h : 1;/ } ka0902_smm$r_cnfg_h_bits;0 } ka0902_smm$r_cnfg_fields_h_ol;' } ka0902_smm$r_cnfg_fields; } ka0902_smm$r_cnfg_ol;" char ka0902_smm$b_fill46 [24];N/* Sable Memory Module CSR4 EDC Status 1 / */ __union {" __int64 ka0902_smm$q_edc1; __struct { __union {1 unsigned int ka0902_smm$l_edc1_l; __struct {A unsigned ka0902_smm$v_edc1_read_cbits_l : 12;: unsigned ka0902_smm$v_edc1_fill_l : 4;? unsigned ka0902_smm$v_edc1_wr_cbits_l : 12;; unsigned ka0902_smm$v_edc1_fill2_l : 4;/ } ka0902_smm$r_edc1_l_bits;0 / } ka0902_smm$r_edc1_fields_l_ol; __union {1 unsigned int ka0902_smm$l_edc1_h; __struct {A unsigned ka0902_smm$v_edc1_read_cbits_h : 12;: unsigned ka0902_smm$v_edc1_fill_h : 4;? unsigned ka0902_smm$v_edc1_wr_cbits_h : 12;; unsigned ka0902_smm$v_edc1_fill2_h : 4;/ } ka0902_smm$r_edc1_h_bits;0 } ka0902_smm$r_edc1_fields_h_o/l;' } ka0902_smm$r_edc1_fields; } ka0902_smm$r_edc1_ol;" char ka0902_smm$b_fill47 [24];N/* Sable Memory Module CSR5 EDC Status 2 */ __union {" __int64 ka0902_smm$q_edc2; __struct { __union {1 unsigned int ka0902_smm$l_edc2_l; __struct {? unsigned ka0902_smm$v_edc2_syndrome_l : 12;; unsigned ka0902_smm$v_edc2_fill_l : 20;/ / } ka0902_smm$r_edc2_l_bits;0 } ka0902_smm$r_edc2_fields_l_ol; __union {1 unsigned int ka0902_smm$l_edc2_h; __struct {? unsigned ka0902_smm$v_edc2_syndrome_h : 12;; unsigned ka0902_smm$v_edc2_fill_h : 20;/ } ka0902_smm$r_edc2_h_bits;0 } ka0902_smm$r_edc2_fields_h_ol;' } ka0902_smm$r_edc2_fields; } ka0902_smm$r_edc2_ol; /" char ka0902_smm$b_fill48 [24];N/* Sable Memory Module CSR6 EDC Control */ __union {# __int64 ka0902_smm$q_edctl; __struct { __union {2 unsigned int ka0902_smm$l_edctl_l; __struct {; unsigned ka0902_smm$v_edctl_srb_l : 12;; unsigned ka0902_smm$v_edctl_uscb_l : 1;< unsigned ka0902_smm$v_edctl_uswcb_l : 1;; /unsigned ka0902_smm$v_edctl_dipc_l : 1;= unsigned ka0902_smm$v_edctl_enb_es_l : 1;< unsigned ka0902_smm$v_edctl_swcb_l : 12;; unsigned ka0902_smm$v_edctl_crdp_l : 1;? unsigned ka0902_smm$v_edctl_enb_crdr_l : 1;? unsigned ka0902_smm$v_edctl_dedccorr_l : 1;A unsigned ka0902_smm$v_edctl_dedcreport_l : 1;0 } ka0902_smm$r_edctl_l_bits;1 } ka0902_s /mm$r_edctl_fields_l_ol; __union {2 unsigned int ka0902_smm$l_edctl_h; __struct {; unsigned ka0902_smm$v_edctl_srb_h : 12;; unsigned ka0902_smm$v_edctl_uscb_h : 1;< unsigned ka0902_smm$v_edctl_uswcb_h : 1;; unsigned ka0902_smm$v_edctl_dipc_h : 1;= unsigned ka0902_smm$v_edctl_enb_es_h : 1;< unsigned ka0902_smm$v_edctl_swcb_h : 12;; / unsigned ka0902_smm$v_edctl_crdp_h : 1;? unsigned ka0902_smm$v_edctl_enb_crdr_h : 1;? unsigned ka0902_smm$v_edctl_dedccorr_h : 1;A unsigned ka0902_smm$v_edctl_dedcreport_h : 1;0 } ka0902_smm$r_edctl_h_bits;1 } ka0902_smm$r_edctl_fields_h_ol;( } ka0902_smm$r_edctl_fields; } ka0902_smm$r_edctl_ol;" char ka0902_smm$b_fill49 [24];N/* Sable Memory Module CSR7 St /ream Buffer Control */ __union {$ __int64 ka0902_smm$q_sbctrl; __struct { __union {3 unsigned int ka0902_smm$l_sbctrl_l; __struct {; unsigned ka0902_smm$v_sbctrl_dsd_l : 1;; unsigned ka0902_smm$v_sbctrl_dsh_l : 1;; unsigned ka0902_smm$v_sbctrl_dsf_l : 1;; unsigned ka0902_smm$v_sbctrl_dsi_l : 1;< unsi /gned ka0902_smm$v_sbctrl_erwd_l : 1;; unsigned ka0902_smm$v_sbctrl_fhb_l : 1;= unsigned ka0902_smm$v_sbctrl_fill1_l : 2;< unsigned ka0902_smm$v_sbctrl_hbsm_l : 1;< unsigned ka0902_smm$v_sbctrl_hbhf_l : 1;: unsigned ka0902_smm$v_sbctrl_fl_l : 1;> unsigned ka0902_smm$v_sbctrl_fill2_l : 21;1 } ka0902_smm$r_sbctrl_l_bits;2 } ka0902_smm$r_sbctrl_fiel /ds_l_ol; __union {3 unsigned int ka0902_smm$l_sbctrl_h; __struct {; unsigned ka0902_smm$v_sbctrl_dsd_h : 1;; unsigned ka0902_smm$v_sbctrl_dsh_h : 1;; unsigned ka0902_smm$v_sbctrl_dsf_h : 1;; unsigned ka0902_smm$v_sbctrl_dsi_h : 1;< unsigned ka0902_smm$v_sbctrl_erwd_h : 1;; unsigned ka0902_smm$v_sbctrl_fhb_h : 1;= / unsigned ka0902_smm$v_sbctrl_fill1_h : 2;< unsigned ka0902_smm$v_sbctrl_hbsm_h : 1;< unsigned ka0902_smm$v_sbctrl_hbhf_h : 1;: unsigned ka0902_smm$v_sbctrl_fl_h : 1;> unsigned ka0902_smm$v_sbctrl_fill2_h : 21;1 } ka0902_smm$r_sbctrl_h_bits;2 } ka0902_smm$r_sbctrl_fields_h_ol;) } ka0902_smm$r_sbctrl_fields;! } ka0902_smm$r_sbctrl_ol;" char ka0902_smm$b_fill /50 [24];N/* Sable Memory Module CSR8 Refresh control */ __union {# __int64 ka0902_smm$q_rctrl; __struct { __union {2 unsigned int ka0902_smm$l_rctrl_l; __struct {9 unsigned ka0902_smm$v_rctrl_rc_l : 8;> unsigned ka0902_smm$v_rctrl_ref_enb_l : 1;< unsigned ka0902_smm$v_rctrl_fill1_l : 3;: unsigned ka0902_smm$v_rctrl_ /nut_l : 1;: unsigned ka0902_smm$v_rctrl_hit_l : 1;= unsigned ka0902_smm$v_rctrl_fill2_l : 18;0 } ka0902_smm$r_rctrl_l_bits;1 } ka0902_smm$r_rctrl_fields_l_ol; __union {2 unsigned int ka0902_smm$l_rctrl_h; __struct {9 unsigned ka0902_smm$v_rctrl_rc_h : 8;> unsigned ka0902_smm$v_rctrl_ref_enb_h : 1;< unsigned ka0902_sm /m$v_rctrl_fill1_h : 3;: unsigned ka0902_smm$v_rctrl_nut_h : 1;: unsigned ka0902_smm$v_rctrl_hit_h : 1;= unsigned ka0902_smm$v_rctrl_fill2_h : 18;0 } ka0902_smm$r_rctrl_h_bits;1 } ka0902_smm$r_rctrl_fields_h_ol;( } ka0902_smm$r_rctrl_fields; } ka0902_smm$r_rctrl_ol;" char ka0902_smm$b_fill51 [24];N/* Sable Memory Module CSR9 CRD Filter control */ /__union {$ __int64 ka0902_smm$q_crdctl; __struct { __union {3 unsigned int ka0902_smm$l_crdctl_l; __struct {; unsigned ka0902_smm$v_crdctl_sm_l : 12;: unsigned ka0902_smm$v_crdctl_bs_l : 2;; unsigned ka0902_smm$v_crdctl_cfe_l : 1;= unsigned ka0902_smm$v_crdctl_fill_l : 17;1 } ka0902_smm$r_crdctl_l_bits;2 } ka0902_s /mm$r_crdctl_fields_l_ol; __union {3 unsigned int ka0902_smm$l_crdctl_h; __struct {; unsigned ka0902_smm$v_crdctl_sm_h : 12;: unsigned ka0902_smm$v_crdctl_bs_h : 2;; unsigned ka0902_smm$v_crdctl_cfe_h : 1;= unsigned ka0902_smm$v_crdctl_fill_h : 17;1 } ka0902_smm$r_crdctl_h_bits;2 } ka0902_smm$r_crdctl_fields_h_ol;) } ka0902 /_smm$r_crdctl_fields;! } ka0902_smm$r_crdctl_ol; } KA0902_SMM; #if !defined(__VAXC)=#define ka0902_smm$q_cme ka0902_smm$r_cme_ol.ka0902_smm$q_cmev#define ka0902_smm$l_cme_l ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$l_cme_l#define ka0902_smm$v_cme_es_l ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.ka09\02_smm$v_cme_es_l#define ka0902_smm$v_cme_se_l ka0902_smm$r_cme_ol.ka0902_smm$r/_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.ka09\02_smm$v_cme_se_l#define ka0902_smm$v_cme_ca_pe_l ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.k\a0902_smm$v_cme_ca_pe_l#define ka0902_smm$v_cme_mca_pe_l ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.\ka0902_smm$v_cme_mca_pe_l#define ka0902_smm$v_cme_wd_pe_l ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cm/e_fields_l_ol.ka0902_smm$r_cme_l_bits.k\a0902_smm$v_cme_wd_pe_l#define ka0902_smm$v_cme_mwd_pe_l ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.\ka0902_smm$v_cme_mwd_pe_l#define ka0902_smm$v_cme_ca_pe_lw0 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits\.ka0902_smm$v_cme_ca_pe_lw0#define ka0902_smm$v_cme_ca_pe_lw2 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka09/02_smm$r_cme_l_bits\.ka0902_smm$v_cme_ca_pe_lw2#define ka0902_smm$v_cme_d_pe_lw0 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.\ka0902_smm$v_cme_d_pe_lw0#define ka0902_smm$v_cme_d_pe_lw2 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.\ka0902_smm$v_cme_d_pe_lw2#define ka0902_smm$v_cme_d_pe_lw4 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits/.\ka0902_smm$v_cme_d_pe_lw4#define ka0902_smm$v_cme_d_pe_lw6 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.\ka0902_smm$v_cme_d_pe_lw6#define ka0902_smm$v_cme_eue_l ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.ka0\902_smm$v_cme_eue_l#define ka0902_smm$v_cme_meue_l ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.ka\0902_smm$v_cme_meue_l/#define ka0902_smm$v_cme_ece_l ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.ka0\902_smm$v_cme_ece_l#define ka0902_smm$v_cme_mece_l ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_l_ol.ka0902_smm$r_cme_l_bits.ka\0902_smm$v_cme_mece_lv#define ka0902_smm$l_cme_h ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$l_cme_h#define ka0902_smm$v_cme_es_h ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fie/lds.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.ka09\02_smm$v_cme_es_h#define ka0902_smm$v_cme_se_h ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.ka09\02_smm$v_cme_se_h#define ka0902_smm$v_cme_ca_pe_h ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.k\a0902_smm$v_cme_ca_pe_h#define ka0902_smm$v_cme_mca_pe_h ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.k/a0902_smm$r_cme_h_bits.\ka0902_smm$v_cme_mca_pe_h#define ka0902_smm$v_cme_wd_pe_h ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.k\a0902_smm$v_cme_wd_pe_h#define ka0902_smm$v_cme_mwd_pe_h ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.\ka0902_smm$v_cme_mwd_pe_h#define ka0902_smm$v_cme_ca_pe_lw1 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bit/s\.ka0902_smm$v_cme_ca_pe_lw1#define ka0902_smm$v_cme_ca_pe_lw3 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits\.ka0902_smm$v_cme_ca_pe_lw3#define ka0902_smm$v_cme_d_pe_lw1 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.\ka0902_smm$v_cme_d_pe_lw1#define ka0902_smm$v_cme_d_pe_lw3 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.\ka0902_smm$v/_cme_d_pe_lw3#define ka0902_smm$v_cme_d_pe_lw5 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.\ka0902_smm$v_cme_d_pe_lw5#define ka0902_smm$v_cme_d_pe_lw7 ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.\ka0902_smm$v_cme_d_pe_lw7#define ka0902_smm$v_cme_eue_h ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.ka0\902_smm$v_cme_eue_h#define ka/0902_smm$v_cme_meue_h ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.ka\0902_smm$v_cme_meue_h#define ka0902_smm$v_cme_ece_h ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.ka0\902_smm$v_cme_ece_h#define ka0902_smm$v_cme_mece_h ka0902_smm$r_cme_ol.ka0902_smm$r_cme_fields.ka0902_smm$r_cme_fields_h_ol.ka0902_smm$r_cme_h_bits.ka\0902_smm$v_cme_mece_hC#define ka0902_smm$q_trap1 ka0902_smm$r_trap/1_ol.ka0902_smm$q_trap1#define ka0902_smm$l_trap1_l ka0902_smm$r_trap1_ol.ka0902_smm$r_trap1_fields.ka0902_smm$r_trap1_fields_l_ol.ka0902_smm$l_trap1_l#define ka0902_smm$l_trap1_h ka0902_smm$r_trap1_ol.ka0902_smm$r_trap1_fields.ka0902_smm$r_trap1_fields_h_ol.ka0902_smm$l_trap1_hC#define ka0902_smm$q_trap2 ka0902_smm$r_trap2_ol.ka0902_smm$q_trap2#define ka0902_smm$l_trap2_l ka0902_smm$r_trap2_ol.ka0902_smm$r_trap2_fields.ka0902_smm$r_trap2_fields_l_ol.ka0902_smm$l_trap2_l#define ka0902_smm$l/_trap2_h ka0902_smm$r_trap2_ol.ka0902_smm$r_trap2_fields.ka0902_smm$r_trap2_fields_h_ol.ka0902_smm$l_trap2_h@#define ka0902_smm$q_cnfg ka0902_smm$r_cnfg_ol.ka0902_smm$q_cnfg{#define ka0902_smm$l_cnfg_l ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_l_ol.ka0902_smm$l_cnfg_l#define ka0902_smm$v_cnfg_mid_l ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_l_ol.ka0902_smm$r_cnfg_l_bit\s.ka0902_smm$v_cnfg_mid_l#define ka0902_smm$v_cnfg_dram_acc_l ka090/2_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_l_ol.ka0902_smm$r_cnfg_\#l_bits.ka0902_smm$v_cnfg_dram_acc_l#define ka0902_smm$v_cnfg_msize_l ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_l_ol.ka0902_smm$r_cnfg_l_b\its.ka0902_smm$v_cnfg_msize_l#define ka0902_smm$v_cnfg_diag_l ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_l_ol.ka0902_smm$r_cnfg_l_bi\ts.ka0902_smm$v_cnfg_diag_l#define ka0902_smm$v_cnfg_csic_rev_l ka0902_sm/m$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_l_ol.ka0902_smm$r_cnfg_\#l_bits.ka0902_smm$v_cnfg_csic_rev_l#define ka0902_smm$v_cnfg_alt_csr_l ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_l_ol.ka0902_smm$r_cnfg_l\!_bits.ka0902_smm$v_cnfg_alt_csr_l#define ka0902_smm$v_cnfg_ilvm_l ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_l_ol.ka0902_smm$r_cnfg_l_bi\ts.ka0902_smm$v_cnfg_ilvm_l#define ka0902_smm$v_cnfg_ilvu_l ka0902_smm$r_/cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_l_ol.ka0902_smm$r_cnfg_l_bi\ts.ka0902_smm$v_cnfg_ilvu_l#define ka0902_smm$v_cnfg_base_adr_l ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_l_ol.ka0902_smm$r_cnfg_\#l_bits.ka0902_smm$v_cnfg_base_adr_l#define ka0902_smm$v_cnfg_mem_ena_l ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_l_ol.ka0902_smm$r_cnfg_l\!_bits.ka0902_smm$v_cnfg_mem_ena_l{#define ka0902_smm$l_cnfg_h ka0902_smm$r_cnfg_/ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_h_ol.ka0902_smm$l_cnfg_h#define ka0902_smm$v_cnfg_mid_h ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_h_ol.ka0902_smm$r_cnfg_h_bit\s.ka0902_smm$v_cnfg_mid_h#define ka0902_smm$v_cnfg_dram_acc_h ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_h_ol.ka0902_smm$r_cnfg_\#h_bits.ka0902_smm$v_cnfg_dram_acc_h#define ka0902_smm$v_cnfg_msize_h ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r/_cnfg_fields_h_ol.ka0902_smm$r_cnfg_h_b\its.ka0902_smm$v_cnfg_msize_h#define ka0902_smm$v_cnfg_diag_h ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_h_ol.ka0902_smm$r_cnfg_h_bi\ts.ka0902_smm$v_cnfg_diag_h#define ka0902_smm$v_cnfg_csic_rev_h ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_h_ol.ka0902_smm$r_cnfg_\#h_bits.ka0902_smm$v_cnfg_csic_rev_h#define ka0902_smm$v_cnfg_alt_csr_h ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_c/nfg_fields_h_ol.ka0902_smm$r_cnfg_h\!_bits.ka0902_smm$v_cnfg_alt_csr_h#define ka0902_smm$v_cnfg_ilvm_h ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_h_ol.ka0902_smm$r_cnfg_h_bi\ts.ka0902_smm$v_cnfg_ilvm_h#define ka0902_smm$v_cnfg_ilvu_h ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_h_ol.ka0902_smm$r_cnfg_h_bi\ts.ka0902_smm$v_cnfg_ilvu_h#define ka0902_smm$v_cnfg_base_adr_h ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fie/lds_h_ol.ka0902_smm$r_cnfg_\#h_bits.ka0902_smm$v_cnfg_base_adr_h#define ka0902_smm$v_cnfg_mem_ena_h ka0902_smm$r_cnfg_ol.ka0902_smm$r_cnfg_fields.ka0902_smm$r_cnfg_fields_h_ol.ka0902_smm$r_cnfg_h\!_bits.ka0902_smm$v_cnfg_mem_ena_h@#define ka0902_smm$q_edc1 ka0902_smm$r_edc1_ol.ka0902_smm$q_edc1{#define ka0902_smm$l_edc1_l ka0902_smm$r_edc1_ol.ka0902_smm$r_edc1_fields.ka0902_smm$r_edc1_fields_l_ol.ka0902_smm$l_edc1_l#define ka0902_smm$v_edc1_read_cbits_l ka0902_smm$r_edc1_ol.ka0902_smm$r_edc/1_fields.ka0902_smm$r_edc1_fields_l_ol.ka0902_smm$r_edc\'1_l_bits.ka0902_smm$v_edc1_read_cbits_l#define ka0902_smm$v_edc1_wr_cbits_l ka0902_smm$r_edc1_ol.ka0902_smm$r_edc1_fields.ka0902_smm$r_edc1_fields_l_ol.ka0902_smm$r_edc1_\#l_bits.ka0902_smm$v_edc1_wr_cbits_l{#define ka0902_smm$l_edc1_h ka0902_smm$r_edc1_ol.ka0902_smm$r_edc1_fields.ka0902_smm$r_edc1_fields_h_ol.ka0902_smm$l_edc1_h#define ka0902_smm$v_edc1_read_cbits_h ka0902_smm$r_edc1_ol.ka0902_smm$r_edc1_fields.ka0902_smm$r_edc1_field/s_h_ol.ka0902_smm$r_edc\'1_h_bits.ka0902_smm$v_edc1_read_cbits_h#define ka0902_smm$v_edc1_wr_cbits_h ka0902_smm$r_edc1_ol.ka0902_smm$r_edc1_fields.ka0902_smm$r_edc1_fields_h_ol.ka0902_smm$r_edc1_\#h_bits.ka0902_smm$v_edc1_wr_cbits_h@#define ka0902_smm$q_edc2 ka0902_smm$r_edc2_ol.ka0902_smm$q_edc2{#define ka0902_smm$l_edc2_l ka0902_smm$r_edc2_ol.ka0902_smm$r_edc2_fields.ka0902_smm$r_edc2_fields_l_ol.ka0902_smm$l_edc2_l#define ka0902_smm$v_edc2_syndrome_l ka0902_smm$r_edc2_ol.ka0902_smm$r_edc/2_fields.ka0902_smm$r_edc2_fields_l_ol.ka0902_smm$r_edc2_\#l_bits.ka0902_smm$v_edc2_syndrome_l{#define ka0902_smm$l_edc2_h ka0902_smm$r_edc2_ol.ka0902_smm$r_edc2_fields.ka0902_smm$r_edc2_fields_h_ol.ka0902_smm$l_edc2_h#define ka0902_smm$v_edc2_syndrome_h ka0902_smm$r_edc2_ol.ka0902_smm$r_edc2_fields.ka0902_smm$r_edc2_fields_h_ol.ka0902_smm$r_edc2_\#h_bits.ka0902_smm$v_edc2_syndrome_hC#define ka0902_smm$q_edctl ka0902_smm$r_edctl_ol.ka0902_smm$q_edctl#define ka0902_smm$l_edctl_l ka0902_smm$/r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_l_ol.ka0902_smm$l_edctl_l#define ka0902_smm$v_edctl_srb_l ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_l_ol.ka0902_smm$r_edctl_\l_bits.ka0902_smm$v_edctl_srb_l#define ka0902_smm$v_edctl_uscb_l ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_l_ol.ka0902_smm$r_edctl\!_l_bits.ka0902_smm$v_edctl_uscb_l#define ka0902_smm$v_edctl_uswcb_l ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fi/elds.ka0902_smm$r_edctl_fields_l_ol.ka0902_smm$r_edct\#l_l_bits.ka0902_smm$v_edctl_uswcb_l#define ka0902_smm$v_edctl_dipc_l ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_l_ol.ka0902_smm$r_edctl\!_l_bits.ka0902_smm$v_edctl_dipc_l#define ka0902_smm$v_edctl_enb_es_l ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_l_ol.ka0902_smm$r_edc\%tl_l_bits.ka0902_smm$v_edctl_enb_es_l#define ka0902_smm$v_edctl_swcb_l ka0902_smm$r_edctl_ol.ka0902_smm$r/_edctl_fields.ka0902_smm$r_edctl_fields_l_ol.ka0902_smm$r_edctl\!_l_bits.ka0902_smm$v_edctl_swcb_l#define ka0902_smm$v_edctl_crdp_l ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_l_ol.ka0902_smm$r_edctl\!_l_bits.ka0902_smm$v_edctl_crdp_l#define ka0902_smm$v_edctl_enb_crdr_l ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_l_ol.ka0902_smm$r_e\)dctl_l_bits.ka0902_smm$v_edctl_enb_crdr_l#define ka0902_smm$v_edctl_dedccorr_l ka0902_smm$r_edctl/_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_l_ol.ka0902_smm$r_e\)dctl_l_bits.ka0902_smm$v_edctl_dedccorr_l#define ka0902_smm$v_edctl_dedcreport_l ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_l_ol.ka0902_smm$r\-_edctl_l_bits.ka0902_smm$v_edctl_dedcreport_l#define ka0902_smm$l_edctl_h ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_h_ol.ka0902_smm$l_edctl_h#define ka0902_smm$v_edctl_srb_h ka0902_smm$r_edctl_ol.ka0902_smm$r_edct/l_fields.ka0902_smm$r_edctl_fields_h_ol.ka0902_smm$r_edctl_\h_bits.ka0902_smm$v_edctl_srb_h#define ka0902_smm$v_edctl_uscb_h ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_h_ol.ka0902_smm$r_edctl\!_h_bits.ka0902_smm$v_edctl_uscb_h#define ka0902_smm$v_edctl_uswcb_h ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_h_ol.ka0902_smm$r_edct\#l_h_bits.ka0902_smm$v_edctl_uswcb_h#define ka0902_smm$v_edctl_dipc_h ka0902_smm$r_edctl_ol.ka0902_smm$r/_edctl_fields.ka0902_smm$r_edctl_fields_h_ol.ka0902_smm$r_edctl\!_h_bits.ka0902_smm$v_edctl_dipc_h#define ka0902_smm$v_edctl_enb_es_h ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_h_ol.ka0902_smm$r_edc\%tl_h_bits.ka0902_smm$v_edctl_enb_es_h#define ka0902_smm$v_edctl_swcb_h ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_h_ol.ka0902_smm$r_edctl\!_h_bits.ka0902_smm$v_edctl_swcb_h#define ka0902_smm$v_edctl_crdp_h ka0902_smm$r_edctl_ol.ka09/02_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_h_ol.ka0902_smm$r_edctl\!_h_bits.ka0902_smm$v_edctl_crdp_h#define ka0902_smm$v_edctl_enb_crdr_h ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_h_ol.ka0902_smm$r_e\)dctl_h_bits.ka0902_smm$v_edctl_enb_crdr_h#define ka0902_smm$v_edctl_dedccorr_h ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_h_ol.ka0902_smm$r_e\)dctl_h_bits.ka0902_smm$v_edctl_dedccorr_h#define ka0902_smm$v_edctl_dedcreport_h /ka0902_smm$r_edctl_ol.ka0902_smm$r_edctl_fields.ka0902_smm$r_edctl_fields_h_ol.ka0902_smm$r\-_edctl_h_bits.ka0902_smm$v_edctl_dedcreport_hF#define ka0902_smm$q_sbctrl ka0902_smm$r_sbctrl_ol.ka0902_smm$q_sbctrl#define ka0902_smm$l_sbctrl_l ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_l_ol.ka0902_smm$l_sbctrl\_l#define ka0902_smm$v_sbctrl_dsd_l ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_l_ol.ka0902_smm$r_sb\%ctrl_l_bits.ka0902_s/mm$v_sbctrl_dsd_l#define ka0902_smm$v_sbctrl_dsh_l ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_l_ol.ka0902_smm$r_sb\%ctrl_l_bits.ka0902_smm$v_sbctrl_dsh_l#define ka0902_smm$v_sbctrl_dsf_l ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_l_ol.ka0902_smm$r_sb\%ctrl_l_bits.ka0902_smm$v_sbctrl_dsf_l#define ka0902_smm$v_sbctrl_dsi_l ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_l_ol.ka0902_smm$r_sb\%ctrl/_l_bits.ka0902_smm$v_sbctrl_dsi_l#define ka0902_smm$v_sbctrl_erwd_l ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_l_ol.ka0902_smm$r_s\'bctrl_l_bits.ka0902_smm$v_sbctrl_erwd_l#define ka0902_smm$v_sbctrl_fhb_l ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_l_ol.ka0902_smm$r_sb\%ctrl_l_bits.ka0902_smm$v_sbctrl_fhb_l#define ka0902_smm$v_sbctrl_fill1_l ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_l_ol.ka/0902_smm$r_\)sbctrl_l_bits.ka0902_smm$v_sbctrl_fill1_l#define ka0902_smm$v_sbctrl_hbsm_l ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_l_ol.ka0902_smm$r_s\'bctrl_l_bits.ka0902_smm$v_sbctrl_hbsm_l#define ka0902_smm$v_sbctrl_hbhf_l ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_l_ol.ka0902_smm$r_s\'bctrl_l_bits.ka0902_smm$v_sbctrl_hbhf_l#define ka0902_smm$v_sbctrl_fl_l ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_/sbctrl_fields_l_ol.ka0902_smm$r_sbc\#trl_l_bits.ka0902_smm$v_sbctrl_fl_l#define ka0902_smm$l_sbctrl_h ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_h_ol.ka0902_smm$l_sbctrl\_h#define ka0902_smm$v_sbctrl_dsd_h ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_h_ol.ka0902_smm$r_sb\%ctrl_h_bits.ka0902_smm$v_sbctrl_dsd_h#define ka0902_smm$v_sbctrl_dsh_h ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_h_ol.ka/0902_smm$r_sb\%ctrl_h_bits.ka0902_smm$v_sbctrl_dsh_h#define ka0902_smm$v_sbctrl_dsf_h ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_h_ol.ka0902_smm$r_sb\%ctrl_h_bits.ka0902_smm$v_sbctrl_dsf_h#define ka0902_smm$v_sbctrl_dsi_h ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_h_ol.ka0902_smm$r_sb\%ctrl_h_bits.ka0902_smm$v_sbctrl_dsi_h#define ka0902_smm$v_sbctrl_erwd_h ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbct/rl_fields_h_ol.ka0902_smm$r_s\'bctrl_h_bits.ka0902_smm$v_sbctrl_erwd_h#define ka0902_smm$v_sbctrl_fhb_h ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_h_ol.ka0902_smm$r_sb\%ctrl_h_bits.ka0902_smm$v_sbctrl_fhb_h#define ka0902_smm$v_sbctrl_fill1_h ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_h_ol.ka0902_smm$r_\)sbctrl_h_bits.ka0902_smm$v_sbctrl_fill1_h#define ka0902_smm$v_sbctrl_hbsm_h ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fi/elds.ka0902_smm$r_sbctrl_fields_h_ol.ka0902_smm$r_s\'bctrl_h_bits.ka0902_smm$v_sbctrl_hbsm_h#define ka0902_smm$v_sbctrl_hbhf_h ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_h_ol.ka0902_smm$r_s\'bctrl_h_bits.ka0902_smm$v_sbctrl_hbhf_h#define ka0902_smm$v_sbctrl_fl_h ka0902_smm$r_sbctrl_ol.ka0902_smm$r_sbctrl_fields.ka0902_smm$r_sbctrl_fields_h_ol.ka0902_smm$r_sbc\#trl_h_bits.ka0902_smm$v_sbctrl_fl_hC#define ka0902_smm$q_rctrl ka0902_smm$r_rctrl_ol.ka0902_smm$q_/rctrl#define ka0902_smm$l_rctrl_l ka0902_smm$r_rctrl_ol.ka0902_smm$r_rctrl_fields.ka0902_smm$r_rctrl_fields_l_ol.ka0902_smm$l_rctrl_l#define ka0902_smm$v_rctrl_rc_l ka0902_smm$r_rctrl_ol.ka0902_smm$r_rctrl_fields.ka0902_smm$r_rctrl_fields_l_ol.ka0902_smm$r_rctrl_l\_bits.ka0902_smm$v_rctrl_rc_l#define ka0902_smm$v_rctrl_ref_enb_l ka0902_smm$r_rctrl_ol.ka0902_smm$r_rctrl_fields.ka0902_smm$r_rctrl_fields_l_ol.ka0902_smm$r_rc\'trl_l_bits.ka0902_smm$v_rctrl_ref_enb_l#define ka0902_smm$v_rctrl/_nut_l ka0902_smm$r_rctrl_ol.ka0902_smm$r_rctrl_fields.ka0902_smm$r_rctrl_fields_l_ol.ka0902_smm$r_rctrl_\l_bits.ka0902_smm$v_rctrl_nut_l#define ka0902_smm$v_rctrl_hit_l ka0902_smm$r_rctrl_ol.ka0902_smm$r_rctrl_fields.ka0902_smm$r_rctrl_fields_l_ol.ka0902_smm$r_rctrl_\l_bits.ka0902_smm$v_rctrl_hit_l#define ka0902_smm$l_rctrl_h ka0902_smm$r_rctrl_ol.ka0902_smm$r_rctrl_fields.ka0902_smm$r_rctrl_fields_h_ol.ka0902_smm$l_rctrl_h#define ka0902_smm$v_rctrl_rc_h ka0902_smm$r_rctrl_ol.ka0902_smm$r/_rctrl_fields.ka0902_smm$r_rctrl_fields_h_ol.ka0902_smm$r_rctrl_h\_bits.ka0902_smm$v_rctrl_rc_h#define ka0902_smm$v_rctrl_ref_enb_h ka0902_smm$r_rctrl_ol.ka0902_smm$r_rctrl_fields.ka0902_smm$r_rctrl_fields_h_ol.ka0902_smm$r_rc\'trl_h_bits.ka0902_smm$v_rctrl_ref_enb_h#define ka0902_smm$v_rctrl_nut_h ka0902_smm$r_rctrl_ol.ka0902_smm$r_rctrl_fields.ka0902_smm$r_rctrl_fields_h_ol.ka0902_smm$r_rctrl_\h_bits.ka0902_smm$v_rctrl_nut_h#define ka0902_smm$v_rctrl_hit_h ka0902_smm$r_rctrl_ol.ka0902_/smm$r_rctrl_fields.ka0902_smm$r_rctrl_fields_h_ol.ka0902_smm$r_rctrl_\h_bits.ka0902_smm$v_rctrl_hit_hF#define ka0902_smm$q_crdctl ka0902_smm$r_crdctl_ol.ka0902_smm$q_crdctl#define ka0902_smm$l_crdctl_l ka0902_smm$r_crdctl_ol.ka0902_smm$r_crdctl_fields.ka0902_smm$r_crdctl_fields_l_ol.ka0902_smm$l_crdctl\_l#define ka0902_smm$v_crdctl_sm_l ka0902_smm$r_crdctl_ol.ka0902_smm$r_crdctl_fields.ka0902_smm$r_crdctl_fields_l_ol.ka0902_smm$r_crd\#ctl_l_bits.ka0902_smm$v_crdctl_sm_l#define ka0902_smm/$v_crdctl_bs_l ka0902_smm$r_crdctl_ol.ka0902_smm$r_crdctl_fields.ka0902_smm$r_crdctl_fields_l_ol.ka0902_smm$r_crd\#ctl_l_bits.ka0902_smm$v_crdctl_bs_l#define ka0902_smm$v_crdctl_cfe_l ka0902_smm$r_crdctl_ol.ka0902_smm$r_crdctl_fields.ka0902_smm$r_crdctl_fields_l_ol.ka0902_smm$r_cr\%dctl_l_bits.ka0902_smm$v_crdctl_cfe_l#define ka0902_smm$l_crdctl_h ka0902_smm$r_crdctl_ol.ka0902_smm$r_crdctl_fields.ka0902_smm$r_crdctl_fields_h_ol.ka0902_smm$l_crdctl\_h#define ka0902_smm$v_crdctl_sm_h ka0902_/smm$r_crdctl_ol.ka0902_smm$r_crdctl_fields.ka0902_smm$r_crdctl_fields_h_ol.ka0902_smm$r_crd\#ctl_h_bits.ka0902_smm$v_crdctl_sm_h#define ka0902_smm$v_crdctl_bs_h ka0902_smm$r_crdctl_ol.ka0902_smm$r_crdctl_fields.ka0902_smm$r_crdctl_fields_h_ol.ka0902_smm$r_crd\#ctl_h_bits.ka0902_smm$v_crdctl_bs_h#define ka0902_smm$v_crdctl_cfe_h ka0902_smm$r_crdctl_ol.ka0902_smm$r_crdctl_fields.ka0902_smm$r_crdctl_fields_h_ol.ka0902_smm$r_cr\%dctl_h_bits.ka0902_smm$v_crdctl_cfe_h"#endif /* #if !defined(__VA /XC) */ #define KA0902_SMM$K_LENGTH 296N/* */N/* DS1287A register definitions */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _ka0902_ds1 /287a {#pragma __nomember_alignment0 unsigned char ka0902_ds1287a$b_fill1 [3584];- unsigned int ka0902_ds1287a$l_port_index;. unsigned char ka0902_ds1287a$b_fill2 [28];, unsigned int ka0902_ds1287a$l_port_data;& char ka0902_ds1287a$b_fill_4_ [4]; } KA0902_DS1287A;N/* */N/* IIC register definitions */N/* / */&#define KA0902_IIC$M_DATA_READ_DIR 0x1"#define KA0902_IIC$M_STATUS_BB 0x1##define KA0902_IIC$M_STATUS_LAB 0x2##define KA0902_IIC$M_STATUS_AAS 0x4##define KA0902_IIC$M_STATUS_ADO 0x8$#define KA0902_IIC$M_STATUS_BER 0x10$#define KA0902_IIC$M_STATUS_STS 0x20$#define KA0902_IIC$M_STATUS_RES 0x40$#define KA0902_IIC$M_STATUS_PIN 0x800#define KA0902_IIC$M_IIC_STATUS_FILL2 0xFFFFFF00!#define KA0902_IIC$M_CMD_ACKB 0x1 #define KA0902_IIC$M_CMD_STO 0x2 #define KA0902_I /IC$M_CMD_STA 0x4 #define KA0902_IIC$M_CMD_ENI 0x8 #define KA0902_IIC$M_CMD_S3 0x10 #define KA0902_IIC$M_CMD_S2 0x20!#define KA0902_IIC$M_CMD_ESO 0x40!#define KA0902_IIC$M_CMD_PIN 0x80-#define KA0902_IIC$M_IIC_CMD_FILL3 0xFFFFFF00N#define KA0902_IIC$K_CPU0_EEPROM_SLAVE 168 /* Slave address of CPU0 EEPROM */N#define KA0902_IIC$K_CPU1_EEPROM_SLAVE 170 /* Slave address of CPU0 EEPROM */N#define KA0902_IIC$K_CPU2_EEPROM_SLAVE 174 /* Slave address of CPU0 EEPROM */N#define KA0902_IIC$K_CPU3_0EEPROM_SLAVE 162 /* Slave address of CPU0 EEPROM */N#define KA0902_IIC$K_MEM0_EEPROM_SLAVE 160 /* Slave address of MEM0 EEPROM */N#define KA0902_IIC$K_MEM1_EEPROM_SLAVE 162 /* Slave address of MEM1 EEPROM */N#define KA0902_IIC$K_MEM2_EEPROM_SLAVE 164 /* Slave address of MEM2 EEPROM */N#define KA0902_IIC$K_MEM3_EEPROM_SLAVE 166 /* Slave address of MEM3 EEPROM */N#define KA0902_IIC$K_IO_EEPROM_SLAVE 172 /* Slave address of I/O EEPROM */O#define KA0902_IIC$K_EXTIO_EEPROM_SLAVE 174 /* Slave 0 addr. of Ext.I/O EEPROM */N#define KA0902_IIC$K_MASTER_SLAVE 182 /* Slave address of master */N#define KA0902_IIC$K_IIC_CLOCK 28 /* Clock speed 90khz + 12Mhz */N#define KA0902_IIC$K_IIC_RETRY_MAX 10 /* Maximum number of retrys */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0902_iic {#pragma __no0member_alignment- unsigned char ka0902_iic$b_fill1 [42496]; __union {+ unsigned int ka0902_iic$l_iic_data; __struct {N unsigned ka0902_iic$v_data_read_dir : 1; /* Write the data */6 unsigned ka0902_iic$v_iic_data_fill2 : 31;) } ka0902_iic$r_iic_data_bits;# } ka0902_iic$r_iic_data_ov;* unsigned char ka0902_iic$b_fill2 [28]; __union {- unsigned int ka0902_iic$l_iic_status; __struct {N 0 unsigned ka0902_iic$v_status_bb : 1; /* Bus Busy NOT */N unsigned ka0902_iic$v_status_lab : 1; /* Lost Arbitration */N unsigned ka0902_iic$v_status_aas : 1; /* Addressed as Slave */S unsigned ka0902_iic$v_status_ado : 1; /* Address 0/Last recieved bit */N unsigned ka0902_iic$v_status_ber : 1; /* Bus Error */N unsigned ka0902_iic$v_status_sts : 1; /* External Stop signal */N unsigned ka0902_ 0iic$v_status_res : 1; /* Reserved must be 0 */N unsigned ka0902_iic$v_status_pin : 1; /* Pending Interrupt NOT */8 unsigned ka0902_iic$v_iic_status_fill2 : 24;+ } ka0902_iic$r_iic_status_bits; __struct {Q unsigned ka0902_iic$v_cmd_ackb : 1; /* Acknowledge after each byte */N unsigned ka0902_iic$v_cmd_sto : 1; /* Send Stop condition */N unsigned ka0902_iic$v_cmd_sta : 1; /* Send Start condition */N 0 unsigned ka0902_iic$v_cmd_eni : 1; /* External Interrupt Enable */N unsigned ka0902_iic$v_cmd_s3 : 1; /* Interrupt Vector Register */N unsigned ka0902_iic$v_cmd_s2 : 1; /* Clock Register */N unsigned ka0902_iic$v_cmd_eso : 1; /* Enable serial output */N unsigned ka0902_iic$v_cmd_pin : 1; /* Pending Interrupt Not */5 unsigned ka0902_iic$v_iic_cmd_fill3 : 24;( } ka0902_iic$r_iic_cmd_bits;% } ka 00902_iic$r_iic_status_ov;" char ka0902_iic$b_fill_5_ [4]; } KA0902_IIC; #if !defined(__VAXC)L#define ka0902_iic$l_iic_data ka0902_iic$r_iic_data_ov.ka0902_iic$l_iic_dataq#define ka0902_iic$v_data_read_dir ka0902_iic$r_iic_data_ov.ka0902_iic$r_iic_data_bits.ka0902_iic$v_data_read_dirR#define ka0902_iic$l_iic_status ka0902_iic$r_iic_status_ov.ka0902_iic$l_iic_statusm#define ka0902_iic$v_status_bb ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_status_bits.ka0902_iic$v_status_bbo#defin0e ka0902_iic$v_status_lab ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_status_bits.ka0902_iic$v_status_labo#define ka0902_iic$v_status_aas ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_status_bits.ka0902_iic$v_status_aaso#define ka0902_iic$v_status_ado ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_status_bits.ka0902_iic$v_status_adoo#define ka0902_iic$v_status_ber ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_status_bits.ka0902_iic$v_status_bero#define ka0902_iic$v_status_sts ka0902_iic$r_iic_status_0ov.ka0902_iic$r_iic_status_bits.ka0902_iic$v_status_stso#define ka0902_iic$v_status_res ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_status_bits.ka0902_iic$v_status_reso#define ka0902_iic$v_status_pin ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_status_bits.ka0902_iic$v_status_pinh#define ka0902_iic$v_cmd_ackb ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_cmd_bits.ka0902_iic$v_cmd_ackbf#define ka0902_iic$v_cmd_sto ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_cmd_bits.ka0902_iic$v_cmd_stof#define ka 00902_iic$v_cmd_sta ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_cmd_bits.ka0902_iic$v_cmd_staf#define ka0902_iic$v_cmd_eni ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_cmd_bits.ka0902_iic$v_cmd_enid#define ka0902_iic$v_cmd_s3 ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_cmd_bits.ka0902_iic$v_cmd_s3d#define ka0902_iic$v_cmd_s2 ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_cmd_bits.ka0902_iic$v_cmd_s2f#define ka0902_iic$v_cmd_eso ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_cmd_bits.ka0902_iic$v_cmd_esof 0#define ka0902_iic$v_cmd_pin ka0902_iic$r_iic_status_ov.ka0902_iic$r_iic_cmd_bits.ka0902_iic$v_cmd_pin"#endif /* #if !defined(__VAXC) */ N/* */N/* EISA register definitions */N/* */N#define KA0902_ESC$K_RID 8 /* Revision ID register */N#define KA0902_ESC$K_MS 64 /* 0 Mode Select register */N#define KA0902_ESC$K_ESCID 2 /* EISA Config space enable */R#define KA0902_ESC$K_SGRBA 87 /* Scatter Gather Base Address register */N#define KA0902_ESC$K_PIRQ0 64 /* PCI IRQ 0 register */N#define KA0902_ESC$K_PIRQ1 65 /* PCI IRQ 0 register */N#define KA0902_ESC$K_PIRQ2 66 /* PCI IRQ 0 register */N#define KA0902_ESC$K_PIRQ3 67 /* PCI IRQ 0 register  0 */N#define KA0902_ESC$K_EISAID0 80 /* EISA ID register 0 */N#define KA0902_ESC$K_EISAID1 81 /* EISA ID register 1 */N#define KA0902_ESC$K_EISAID2 82 /* EISA ID register 2 */N#define KA0902_ESC$K_EISAID3 83 /* EISA ID register 3 */S#define KA0902_ESC$K_CFG_ENABLE 15 /* Value of ESCID to enable config space */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre 0DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0902_esc {#pragma __nomember_alignment, unsigned char ka0902_esc$b_fill1 [1088];R unsigned int ka0902_esc$l_cfgai; /* Configuration Address Index register */* unsigned char ka0902_esc$b_fill2 [28];O unsigned int ka0902_esc$l_cfgdi; /* Configuration Data Index register */, unsigned char ka0902_esc$b_fill3 [1988];N unsigned int ka0902_esc$l_nmis 0c; /* NMI Status and Control register */- unsigned char ka0902_esc$b_fill4 [32764];N unsigned int ka0902_esc$l_nmiesc; /* NMI Extended Status and Control */* unsigned char ka0902_esc$b_fill5 [92];N unsigned int ka0902_esc$l_lebmg; /* Last EISA Bus Master Granted */N/* Define index of... */" char ka0902_esc$b_fill_6_ [4]; } KA0902_ESC; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE 0 /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KA0902DEF_LOADED */ wwpe[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietar0y software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** prop0rietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************* 0***********************************************************************************************/=/* Created: 7-Oct-2024 15:22:35 by OpenVMS SDL V3.7 */I/* Source: 14-NOV-1994 19:26:43 $1$DGA8345:[LIB_H.SRC]KA0905DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KA0905DEF ***/#ifndef __KA0905DEF_LOADED#define __KA0905DEF_LOADED 1 G#pragma __nostandard /* This file uses no0n-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_0params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif "#define KA0905$K_MAX_CPU_MODULES 4%#define KA0905$K_MAX_MEMORY_MODULES 4N/* */N/* Gamma CPU register definitions 0 */N/* */"#define KA0905_CPU$M_CREG_RN_0 0xF'#define KA0905_CPU$M_CREG_FILL_01 0xFF0'#define KA0905_CPU$M_CREG_EBSS_0 0x1000)#define KA0905_CPU$M_CREG_FILL_02 0xFE000*#define KA0905_CPU$M_CREG_EEDLY_0 0x100000*#define KA0905_CPU$M_CREG_FILL_03 0x600000(#define KA0905_CPU$M_CREG_EFF_0 0x800000)#define KA0905_CPU$M_CREG_DIC_0 0x1000000(#define KA0905_CPU$M_CREG_E4_0 0x2000000)#define KA09 005_CPU$M_CREG_AMB_0 0x4000000)#define KA0905_CPU$M_CREG_ASD_0 0x8000000)#define KA0905_CPU$M_CREG_CS_0 0x70000000,#define KA0905_CPU$M_CREG_FILL_04 0x80000000"#define KA0905_CPU$M_CREG_RN_1 0xF"#define KA0905_CPU$M_CREG_ESI 0xF0$#define KA0905_CPU$M_CREG_EIOI 0x300%#define KA0905_CPU$M_CREG_EAIOI 0xC00'#define KA0905_CPU$M_CREG_EBSS_1 0x1000)#define KA0905_CPU$M_CREG_FILL_05 0xFE000+#define KA0905_CPU$M_CREG_EE_DLY_1 0x100000*#define KA0905_CPU$M_CREG_FILL_06 0x600000(#define KA0905 0_CPU$M_CREG_EFF_1 0x800000)#define KA0905_CPU$M_CREG_DIC_1 0x1000000(#define KA0905_CPU$M_CREG_E4_1 0x2000000)#define KA0905_CPU$M_CREG_AMB_1 0x4000000)#define KA0905_CPU$M_CREG_ASD_1 0x8000000)#define KA0905_CPU$M_CREG_CS_1 0x70000000,#define KA0905_CPU$M_CREG_FILL_07 0x80000000N#define KA0905_CREG$K_RESERVED 0 /* Reserved */N#define KA0905_CREG$K_CACHE_SIZE_1MB 1 /* Cache size is 1Mb */N#define KA0905_CREG$K_CACHE_SIZE_2MB 2 /* Cache size 0is 2Mb */N#define KA0905_CREG$K_CACHE_SIZE_4MB 3 /* Cache size is 4Mb */N#define KA0905_CREG$K_CACHE_SIZE_8MB 4 /* Cache size is 8Mb */N#define KA0905_CREG$K_CACHE_SIZE_16MB 5 /* Cache size is 16Mb */'#define KA0905_CPU$M_ESREG_EVBCEF_0 0x7&#define KA0905_CPU$M_ESREG_FILL_01 0x8)#define KA0905_CPU$M_ESREG_EVB_FEF_0 0xF0&#define KA0905_CPU$M_ESREG_DTS_0 0x400(#define KA0905_CPU$M_ESREG_FILL_02 0x800(#define KA0905_CPU$M_ESREG_IBPE_ 00 0x1000(#define KA0905_CPU$M_ESREG_IBEI_0 0x6000'#define KA0905_CPU$M_ESREG_IBS_0 0x8000*#define KA0905_CPU$M_ESREG_CBEF_0 0xFF0000*#define KA0905_CPU$M_ESREG_CBS_0 0x1000000*#define KA0905_CPU$M_ESREG_CBC_0 0x2000000,#define KA0905_CPU$M_ESREG_FILL_03 0xC000000,#define KA0905_CPU$M_ESREG_EVNR_0 0x10000000-#define KA0905_CPU$M_ESREG_FILL_04 0xE0000000'#define KA0905_CPU$M_ESREG_EVBCEF_1 0x7'#define KA0905_CPU$M_ESREG_EVBCEI_1 0x8(#define KA0905_CPU$M_ESREG_EVBFEF_1 0xF0&#define KA0905 0_CPU$M_ESREG_DTS_1 0x400(#define KA0905_CPU$M_ESREG_FILL_05 0x800(#define KA0905_CPU$M_ESREG_IBPE_1 0x1000(#define KA0905_CPU$M_ESREG_IBEI_1 0x6000'#define KA0905_CPU$M_ESREG_IBS_1 0x8000)#define KA0905_CPU$M_ESREG_CBEF_1 0xF0000+#define KA0905_CPU$M_ESREG_FILL_06 0xF00000*#define KA0905_CPU$M_ESREG_CBS_1 0x1000000*#define KA0905_CPU$M_ESREG_CBC_1 0x2000000,#define KA0905_CPU$M_ESREG_FILL_07 0xC000000,#define KA0905_CPU$M_ESREG_EVNR_1 0x10000000,#define KA0905_CPU$M_ESREG_EVSF_1 0x200000 000-#define KA0905_CPU$M_ESREG_FILL_08 0xC0000000'#define KA0905_CPU$M_EVBCR_EACBPC_0 0x1&#define KA0905_CPU$M_EVBCR_FILL_01 0xE&#define KA0905_CPU$M_EVBCR_ECEI_0 0x10%#define KA0905_CPU$M_EVBCR_EEC_0 0x20&#define KA0905_CPU$M_EVBCR_EREC_0 0x40,#define KA0905_CPU$M_EVBCR_FILL_02 0x7FFFF80(#define KA0905_CPU$M_EVBCR_FFS 0x8000000*#define KA0905_CPU$M_EVBCR_RSFS 0x10000000-#define KA0905_CPU$M_EVBCR_FILL_03 0xE0000000'#define KA0905_CPU$M_EVBCR_EACBPC_1 0x1&#define KA0905_CPU$M_EVBCR_FIL 0L_04 0xE&#define KA0905_CPU$M_EVBCR_ECEI_1 0x10%#define KA0905_CPU$M_EVBCR_EEC_1 0x20&#define KA0905_CPU$M_EVBCR_EREC_1 0x40&#define KA0905_CPU$M_EVBCR_DEEC_1 0x80-#define KA0905_CPU$M_EVBCR_FILL_05 0xFFFFFF00-#define KA0905_CPU$M_EVBVEAR_VEA_0 0x3FFFFFFF/#define KA0905_CPU$M_EVBVEAR_FILL_01 0xC0000000-#define KA0905_CPU$M_EVBVEAR_VEA_1 0x3FFFFFFF/#define KA0905_CPU$M_EVBVEAR_FILL_02 0xC0000000$#define KA0905_CPU$M_EVBCER_CE_0 0x3$#define KA0905_CPU$M_EVBCER_RD_0 0x4%#define KA0905_C 0PU$M_EVBCER_MCE_0 0x8(#define KA0905_CPU$M_EVBCER_FILL_01 0xF0'#define KA0905_CPU$M_EVBCER_ES_0 0xFF00)#define KA0905_CPU$M_EVBCER_ES_2 0xFF0000.#define KA0905_CPU$M_EVBCER_FILL_02 0xFF000000$#define KA0905_CPU$M_EVBCER_CE_1 0x3$#define KA0905_CPU$M_EVBCER_RD_1 0x4%#define KA0905_CPU$M_EVBCER_MCE_1 0x8(#define KA0905_CPU$M_EVBCER_FILL_03 0xF0'#define KA0905_CPU$M_EVBCER_ES_1 0xFF00)#define KA0905_CPU$M_EVBCER_ES_3 0xFF0000.#define KA0905_CPU$M_EVBCER_FILL_04 0xFF000000-#define KA0905 0_CPU$M_EVBCEAR_CEA_0 0xFFFFFFFF-#define KA0905_CPU$M_EVBCEAR_CEA_1 0xFFFFFFFF$#define KA0905_CPU$M_EVBUER_UE_0 0x3$#define KA0905_CPU$M_EVBUER_RD_0 0x4'#define KA0905_CPU$M_EVBUER_FILL_01 0x8(#define KA0905_CPU$M_EVBUER_PEACB_0 0x10'#define KA0905_CPU$M_EVBUER_PEVA_0 0x20(#define KA0905_CPU$M_EVBUER_FILL_02 0xC0'#define KA0905_CPU$M_EVBUER_ES_0 0xFF00)#define KA0905_CPU$M_EVBUER_ES_2 0xFF0000-#define KA0905_CPU$M_EVBUER_FILL_03 0xF000000.#define KA0905_CPU$M_EVBUER_EVBCB_0 0xF0000000 0$#define KA0905_CPU$M_EVBUER_UE_1 0x3$#define KA0905_CPU$M_EVBUER_RD_1 0x4'#define KA0905_CPU$M_EVBUER_FILL_04 0x8(#define KA0905_CPU$M_EVBUER_PEACB_1 0x10'#define KA0905_CPU$M_EVBUER_PEVA_1 0x20(#define KA0905_CPU$M_EVBUER_FILL_05 0xC0'#define KA0905_CPU$M_EVBUER_ES_1 0xFF00)#define KA0905_CPU$M_EVBUER_ES_3 0xFF0000-#define KA0905_CPU$M_EVBUER_FILL_06 0xF000000.#define KA0905_CPU$M_EVBUER_EVBCB_1 0xF0000000-#define KA0905_CPU$M_EVBUEAR_UEA_0 0xFFFFFFFF-#define KA0905_CPU$M_EVBUEAR_U 0EA_1 0xFFFFFFFF/#define KA0905_CPU$M_EVBRESV_FILL_01 0xFFFFFFFF/#define KA0905_CPU$M_EVBRESV_FILL_02 0xFFFFFFFF$#define KA0905_CPU$M_DTCTR_DTE_0 0x1&#define KA0905_CPU$M_DTCTR_FILL_01 0xE&#define KA0905_CPU$M_DTCTR_ECPC_0 0x10$#define KA0905_CPU$M_DTCTR_FBCP 0x20'#define KA0905_CPU$M_DTCTR_FILL_02 0xC0'#define KA0905_CPU$M_DTCTR_ETPC_0 0x100%#define KA0905_CPU$M_DTCTR_FBTP 0x200(#define KA0905_CPU$M_DTCTR_FILL_03 0xC00(#define KA0905_CPU$M_DTCTR_DTDM_0 0x1000-#define KA0905_CPU$M_DTC !0TR_FILL_04 0xFFFFE000$#define KA0905_CPU$M_DTCTR_DTE_1 0x1&#define KA0905_CPU$M_DTCTR_FILL_05 0xE&#define KA0905_CPU$M_DTCTR_ECPC_1 0x10'#define KA0905_CPU$M_DTCTR_FILL_06 0xE0'#define KA0905_CPU$M_DTCTR_ETPC_1 0x100(#define KA0905_CPU$M_DTCTR_FILL_07 0xE00(#define KA0905_CPU$M_DTCTR_DTDM_1 0x1000-#define KA0905_CPU$M_DTCTR_FILL_08 0xFFFFE000&#define KA0905_CPU$M_DTER_FILL_01 0x1F'#define KA0905_CPU$M_DTER_DTEA 0xFFFFE0+#define KA0905_CPU$M_DTER_FILL_02 0xF000000+#define KA0905_CPU$M "0_DTER_TCPE_0 0x10000000,#define KA0905_CPU$M_DTER_FILL_03 0x60000000*#define KA0905_CPU$M_DTER_TPE_0 0x80000000+#define KA0905_CPU$M_DTER_FILL_04 0xFFFFFFF+#define KA0905_CPU$M_DTER_TCPE_1 0x10000000,#define KA0905_CPU$M_DTER_FILL_05 0x60000000*#define KA0905_CPU$M_DTER_TPE_1 0x80000000"#define KA0905_CPU$M_DTTCR_TCF 0x7##define KA0905_CPU$M_DTTCR_TCPF 0x8'#define KA0905_CPU$M_DTTCR_FILL_01 0x10%#define KA0905_CPU$M_DTTCR_AF 0xFFFE0(#define KA0905_CPU$M_DTTCR_MTAF 0xF00000)#define KA #00905_CPU$M_DTTCR_PTF 0x7F000000)#define KA0905_CPU$M_DTTCR_TPF 0x80000000-#define KA0905_CPU$M_DTTCR_FILL_02 0xFFFFFFFF"#define KA0905_CPU$M_DTTR_TC_0 0x7##define KA0905_CPU$M_DTTR_TCP_0 0x8)#define KA0905_CPU$M_DTTR_FILL_01 0xFFFF0)#define KA0905_CPU$M_DTTR_TD_0 0x7FF00000)#define KA0905_CPU$M_DTTR_TP_0 0x80000000"#define KA0905_CPU$M_DTTR_TC_1 0x7##define KA0905_CPU$M_DTTR_TCP_1 0x8)#define KA0905_CPU$M_DTTR_FILL_02 0xFFFF0)#define KA0905_CPU$M_DTTR_TD_1 0x7FF00000)#define KA09 $005_CPU$M_DTTR_TP_1 0x80000000.#define KA0905_CPU$M_DTRESV_FILL_01 0xFFFFFFFF.#define KA0905_CPU$M_DTRESV_FILL_02 0xFFFFFFFF&#define KA0905_CPU$M_IBCSR_FILL_01 0xF&#define KA0905_CPU$M_IBCSR_IBPE_0 0x10(#define KA0905_CPU$M_IBCSR_SCDIPE_0 0x20(#define KA0905_CPU$M_IBCSR_CCDIPE_0 0x40(#define KA0905_CPU$M_IBCSR_FILL_02 0xF80(#define KA0905_CPU$M_IBCSR_EIPC_0 0x1000(#define KA0905_CPU$M_IBCSR_DBIP_0 0x2000-#define KA0905_CPU$M_IBCSR_FILL_03 0xFFFFC000&#define KA0905_CPU$M_IBCSR_FILL_04 0xF& %0#define KA0905_CPU$M_IBCSR_IBPE_1 0x10(#define KA0905_CPU$M_IBCSR_SCDIPE_1 0x20(#define KA0905_CPU$M_IBCSR_CCDIPE_1 0x40(#define KA0905_CPU$M_IBCSR_FILL_05 0xF80(#define KA0905_CPU$M_IBCSR_EIPC_1 0x1000-#define KA0905_CPU$M_IBCSR_FILL_06 0xFFFFE000-#define KA0905_CPU$M_IBEAR_CBCAC_0 0xFFFFFFFF-#define KA0905_CPU$M_IBEAR_CBCAC_1 0xFFFFFFFF"#define KA0905_CPU$M_ACR_CBE_0 0x1$#define KA0905_CPU$M_ACR_FILL_01 0xE##define KA0905_CPU$M_ACR_BME_0 0x10##define KA0905_CPU$M_ACR_DME_0 0x20%#def &0ine KA0905_CPU$M_ACR_FILL_02 0xC0$#define KA0905_CPU$M_ACR_PME_0 0x100%#define KA0905_CPU$M_ACR_BCRE_0 0x200&#define KA0905_CPU$M_ACR_FILL_03 0xC00&#define KA0905_CPU$M_ACR_DCBR_0 0x1000+#define KA0905_CPU$M_ACR_FILL_04 0xFFFFE000"#define KA0905_CPU$M_ACR_CBE_1 0x1$#define KA0905_CPU$M_ACR_FILL_05 0xE##define KA0905_CPU$M_ACR_BME_1 0x10##define KA0905_CPU$M_ACR_DME_1 0x20%#define KA0905_CPU$M_ACR_FILL_06 0xC0$#define KA0905_CPU$M_ACR_PME_1 0x100%#define KA0905_CPU$M_ACR_BCRE_1 0x200 '0&#define KA0905_CPU$M_ACR_FILL_07 0xC00&#define KA0905_CPU$M_ACR_DCBR_1 0x1000+#define KA0905_CPU$M_ACR_FILL_08 0xFFFFE000##define KA0905_CPU$M_CBCR_EPC_0 0x1##define KA0905_CPU$M_CBCR_DWP_0 0x2$#define KA0905_CPU$M_CBCR_CAWP_0 0x4%#define KA0905_CPU$M_CBCR_FILL_01 0x8!#define KA0905_CPU$M_CBCR_FS 0x10'#define KA0905_CPU$M_CBCR_FILL_02 0xFE0(#define KA0905_CPU$M_CBCR_ECBEI_0 0x1000(#define KA0905_CPU$M_CBCR_FILL_03 0xE000&#define KA0905_CPU$M_CBCR_DSRC 0x10000,#define KA0905_CPU$M_C (0BCR_FILL_04 0xFFFE0000##define KA0905_CPU$M_CBCR_EPC_1 0x1##define KA0905_CPU$M_CBCR_DWP_1 0x2$#define KA0905_CPU$M_CBCR_CAWP_1 0x4&#define KA0905_CPU$M_CBCR_FILL_05 0xF8##define KA0905_CPU$M_CBCR_CID 0x700'#define KA0905_CPU$M_CBCR_FILL_06 0x800(#define KA0905_CPU$M_CBCR_ECBEI_1 0x1000,#define KA0905_CPU$M_CBCR_FILL_07 0xFFFFE000##define KA0905_CPU$M_CBER_URE_0 0x1%#define KA0905_CPU$M_CBER_FILL_01 0xE'#define KA0905_CPU$M_CBER_CALLPE_0 0x10'#define KA0905_CPU$M_CBER_CAHLPE_0 0x20 )0&#define KA0905_CPU$M_CBER_FILL_02 0xC0'#define KA0905_CPU$M_CBER_PELW0WD 0x100'#define KA0905_CPU$M_CBER_PELW1WD 0x200'#define KA0905_CPU$M_CBER_PELW4WD 0x400'#define KA0905_CPU$M_CBER_PELW5WD 0x800(#define KA0905_CPU$M_CBER_FILL_03 0xF000)#define KA0905_CPU$M_CBER_PELW0RD 0x10000)#define KA0905_CPU$M_CBER_PELW1RD 0x20000)#define KA0905_CPU$M_CBER_PELW4RD 0x40000)#define KA0905_CPU$M_CBER_PELW5RD 0x80000&#define KA0905_CPU$M_CBER_USR 0x100000*#define KA0905_CPU$M_CBER_FILL_04 0xE0 *00000(#define KA0905_CPU$M_CBER_CANA 0x1000000+#define KA0905_CPU$M_CBER_FILL_05 0xE000000)#define KA0905_CPU$M_CBER_D0NA 0x10000000)#define KA0905_CPU$M_CBER_D1NA 0x20000000,#define KA0905_CPU$M_CBER_FILL_06 0xC0000000##define KA0905_CPU$M_CBER_UCR_1 0x1%#define KA0905_CPU$M_CBER_FILL_07 0xE'#define KA0905_CPU$M_CBER_CALLPE_1 0x10'#define KA0905_CPU$M_CBER_CAHLPE_1 0x20&#define KA0905_CPU$M_CBER_FILL_08 0xC0'#define KA0905_CPU$M_CBER_PELW2WD 0x100'#define KA0905_CPU$M_CBER_PELW3WD +00x200'#define KA0905_CPU$M_CBER_PELW6WD 0x400'#define KA0905_CPU$M_CBER_PELW7WD 0x800(#define KA0905_CPU$M_CBER_FILL_09 0xF000)#define KA0905_CPU$M_CBER_PELW2RD 0x10000)#define KA0905_CPU$M_CBER_PELW3RD 0x20000)#define KA0905_CPU$M_CBER_PELW6RD 0x40000)#define KA0905_CPU$M_CBER_PELW7RD 0x80000,#define KA0905_CPU$M_CBER_FILL_10 0xFFF00000-#define KA0905_CPU$M_CBEALR_CBLA_0 0xFFFFFFFF-#define KA0905_CPU$M_CBEALR_CBLA_1 0xFFFFFFFF-#define KA0905_CPU$M_CBEAHR_CBHA_0 0xFFFFFFFF-#defin ,0e KA0905_CPU$M_CBEAHR_CBHA_1 0xFFFFFFFF.#define KA0905_CPU$M_CBRESV_FILL_01 0xFFFFFFFF.#define KA0905_CPU$M_CBRESV_FILL_02 0xFFFFFFFF"#define KA0905_CPU$M_ALR_LAV_0 0x1%#define KA0905_CPU$M_ALR_FILL_01 0x1E(#define KA0905_CPU$M_ALR_LA_0 0xFFFFFFE0"#define KA0905_CPU$M_ALR_LAV_1 0x1%#define KA0905_CPU$M_ALR_FILL_02 0x1E(#define KA0905_CPU$M_ALR_LA_1 0xFFFFFFE0+#define KA0905_CPU$M_PMBR_DATA_0 0xFFFFFFFF+#define KA0905_CPU$M_PMBR_DATA_1 0xFFFFFFFF+#define KA0905_CPU$M_IIRR_FILL_0 0xFFFFF-0FFF'#define KA0905_CPU$M_IIRR_FILL_02 0xFFF$#define KA0905_CPU$M_IIRR_RHI 0x1000(#define KA0905_CPU$M_IIRR_FILL_03 0xE000$#define KA0905_CPU$M_IIRR_II 0x10000,#define KA0905_CPU$M_IIRR_FILL_04 0xFFFE0000%#define KA0905_CPU$M_SICR_CBEIC_0 0x1,#define KA0905_CPU$M_SICR_FILL_01 0xFFFFFFFE%#define KA0905_CPU$M_SICR_CBEIC_1 0x1%#define KA0905_CPU$M_SICR_FILL_02 0xE"#define KA0905_CPU$M_SICR_ITI 0x10&#define KA0905_CPU$M_SICR_FILL_03 0xE0##define KA0905_CPU$M_SICR_SEC 0x100'#define KA0905 .0_CPU$M_SICR_FILL_04 0xE00%#define KA0905_CPU$M_SICR_NHIC 0x1000(#define KA0905_CPU$M_SICR_FILL_05 0xE000%#define KA0905_CPU$M_SICR_IIC 0x10000)#define KA0905_CPU$M_SICR_FILL_06 0xE0000'#define KA0905_CPU$M_SICR_IOII 0x300000,#define KA0905_CPU$M_SICR_FILL_07 0xFFC00000"#define KA0905_CPU$M_PMCR_SS_0 0x1%#define KA0905_CPU$M_PMCR_FILL_01 0xE##define KA0905_CPU$M_PMCR_AM_0 0x30'#define KA0905_CPU$M_PMCR_FILL_02 0xFC0'#define KA0905_CPU$M_PMCR_SPMR10 0xF000'#define KA0905_CPU$M_PMCR_/0SPMR9 0xF0000(#define KA0905_CPU$M_PMCR_SPMR8 0xF00000)#define KA0905_CPU$M_PMCR_SPMR7 0xF000000*#define KA0905_CPU$M_PMCR_SPMR6 0xF0000000"#define KA0905_CPU$M_PMCR_SS_1 0x1"#define KA0905_CPU$M_PMCR_EPMO 0x6%#define KA0905_CPU$M_PMCR_FILL_03 0x8##define KA0905_CPU$M_PMCR_AM_1 0x30'#define KA0905_CPU$M_PMCR_CIDMASK 0x1C0(#define KA0905_CPU$M_PMCR_CIDMATCH 0xE00&#define KA0905_CPU$M_PMCR_SPMR5 0xF000'#define KA0905_CPU$M_PMCR_SPMR4 0xF0000(#define KA0905_CPU$M_PMCR_SPMR3 0xF00000)#d 00efine KA0905_CPU$M_PMCR_SPMR2 0xF000000*#define KA0905_CPU$M_PMCR_SPMR1 0xF0000000'#define KA0905_CPU$M_PMR1_C6 0x7FFFFFFF(#define KA0905_CPU$M_PMR1_OF6 0x80000000'#define KA0905_CPU$M_PMR1_C1 0x7FFFFFFF(#define KA0905_CPU$M_PMR1_OF1 0x80000000'#define KA0905_CPU$M_PMR2_C7 0x7FFFFFFF(#define KA0905_CPU$M_PMR2_OF7 0x80000000'#define KA0905_CPU$M_PMR2_C2 0x7FFFFFFF(#define KA0905_CPU$M_PMR2_OF2 0x80000000'#define KA0905_CPU$M_PMR3_C8 0x7FFFFFFF(#define KA0905_CPU$M_PMR3_OF8 0x80000000' 10#define KA0905_CPU$M_PMR3_C3 0x7FFFFFFF(#define KA0905_CPU$M_PMR3_OF3 0x80000000'#define KA0905_CPU$M_PMR4_C9 0x7FFFFFFF(#define KA0905_CPU$M_PMR4_OF9 0x80000000'#define KA0905_CPU$M_PMR4_C4 0x7FFFFFFF(#define KA0905_CPU$M_PMR4_OF4 0x80000000(#define KA0905_CPU$M_PMR5_C10 0x7FFFFFFF)#define KA0905_CPU$M_PMR5_OF10 0x80000000'#define KA0905_CPU$M_PMR5_C5 0x7FFFFFFF(#define KA0905_CPU$M_PMR5_OF5 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre 20DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0905_cpu {N/* Configuration Register, CREG */#pragma __nomember_alignment __union {" __int64 ka0905_cpu$q_creg; __struct { __union {1 unsigned int ka0905_cpu$l_creg_l; __struct {P unsigned ka0905_cpu$v_creg_rn_0 : 4; /* Revision Number 300 */; unsigned ka0905_cpu$v_creg_fill_01 : 8;\ unsigned ka0905_cpu$v_creg_ebss_0 : 1; /* Enable Bus sizing Support 0 */; unsigned ka0905_cpu$v_creg_fill_02 : 7;S unsigned ka0905_cpu$v_creg_eedly_0 : 1; /* Enable EXCH DYL 0 */; unsigned ka0905_cpu$v_creg_fill_03 : 2;R unsigned ka0905_cpu$v_creg_eff_0 : 1; /* Enable Fast Fill 0 */W unsigned ka0905_cpu$v_creg_dic40_0 : 1; /* Disable IDELBC-CSTALL 0 */O unsigned ka0905_cpu$v_creg_e4_0 : 1; /* Enable 4IDLEBC 0 */N unsigned ka0905_cpu$v_creg_amb_0 : 1; /* Ack MB 0 */O unsigned ka0905_cpu$v_creg_asd_0 : 1; /* Ack Set Dirty 0 */N unsigned ka0905_cpu$v_creg_cs_0 : 3; /* Cache Size 0 */; unsigned ka0905_cpu$v_creg_fill_04 : 1;/ } ka0905_cpu$r_creg_l_bits;0 } ka0905_cpu$r 50_creg_fields_l_ol; __union {1 unsigned int ka0905_cpu$l_creg_h; __struct {P unsigned ka0905_cpu$v_creg_rn_1 : 4; /* Revision Number 1 */V unsigned ka0905_cpu$v_creg_esi : 4; /* Enable System Interrupts */T unsigned ka0905_cpu$v_creg_eioi : 2; /* Enable I/O Interrupts */Y unsigned ka0905_cpu$v_creg_eaioi : 2; /* Enable Alt I/O Interrupts */\ unsigned ka060905_cpu$v_creg_ebss_1 : 1; /* Enable Bus sizing Support 1 */; unsigned ka0905_cpu$v_creg_fill_05 : 7;T unsigned ka0905_cpu$v_creg_ee_dly_1 : 1; /* Enable EXCH DYL 1 */; unsigned ka0905_cpu$v_creg_fill_06 : 2;R unsigned ka0905_cpu$v_creg_eff_1 : 1; /* Enable Fast Fill 1 */V unsigned ka0905_cpu$v_creg_dic_1 : 1; /* Disable IDELBC-STALL 1 */O unsigned ka0905_cpu$v_creg_e4_1 : 1; /* En 70able 4IDLEBC 1 */N unsigned ka0905_cpu$v_creg_amb_1 : 1; /* Ack MB 1 */O unsigned ka0905_cpu$v_creg_asd_1 : 1; /* Ack Set Dirty 1 */N unsigned ka0905_cpu$v_creg_cs_1 : 3; /* Cache Size 1 */; unsigned ka0905_cpu$v_creg_fill_07 : 1;/ } ka0905_cpu$r_creg_h_bits;0 } ka0905_cpu$r_creg_fields_h_ol;' } ka0905_cpu$r_creg_fields; } ka0905_cpu$r_creg_ol;# ch 80ar ka0905_cpu$b_fill_01 [24];N/* Error Summary Register, ESREG */ __union {# __int64 ka0905_cpu$q_esreg; __struct { __union {2 unsigned int ka0905_cpu$l_esreg_l; __struct {a unsigned ka0905_cpu$v_esreg_evbcef_0 : 3; /* EVB Correctable Error Field 0 */< unsigned ka0905_cpu$v_esreg_fill_01 : 1;\ unsigned ka0905_cpu$v_esreg_ev90b_fef_0 : 4; /* EVB Fatal Error Field 0 */R unsigned ka0905_cpu$v_esreg_dtef_0 : 2; /* DT Error Field 0 */N unsigned ka0905_cpu$v_esreg_dts_0 : 1; /* DT Summary 0 */< unsigned ka0905_cpu$v_esreg_fill_02 : 1;S unsigned ka0905_cpu$v_esreg_ibpe_0 : 1; /* IB Parity Error 0 */Q unsigned ka0905_cpu$v_esreg_ibei_0 : 2; /* IB Error Info 0 */N unsigned ka0905_cpu$v_esreg_ibs_0 : 1; /* IB S:0ummary 0 */R unsigned ka0905_cpu$v_esreg_cbef_0 : 8; /* CB Error Field 0 */N unsigned ka0905_cpu$v_esreg_cbs_0 : 1; /* CB Summary 0 */N unsigned ka0905_cpu$v_esreg_cbc_0 : 1; /* CB CMDR 0 */< unsigned ka0905_cpu$v_esreg_fill_03 : 2;Q unsigned ka0905_cpu$v_esreg_evnr_0 : 1; /* EV Noresponse 0 */< unsigned ka0905_cpu$v_esreg_fill_04 : 3;0 } ka0905_cpu$r_esreg ;0_l_bits;1 } ka0905_cpu$r_esreg_fields_l_ol; __union {2 unsigned int ka0905_cpu$l_esreg_h; __struct {a unsigned ka0905_cpu$v_esreg_evbcef_1 : 3; /* EVB Correctable Error Field 1 */_ unsigned ka0905_cpu$v_esreg_evbcei_1 : 1; /* EVB Correctable Error Int 1 */[ unsigned ka0905_cpu$v_esreg_evbfef_1 : 4; /* EVB Fatal Error Field 1 */R unsigned ka0905_cpu$v_esre<0g_dtef_1 : 2; /* DT Error Field 1 */N unsigned ka0905_cpu$v_esreg_dts_1 : 1; /* DT Summary 1 */< unsigned ka0905_cpu$v_esreg_fill_05 : 1;S unsigned ka0905_cpu$v_esreg_ibpe_1 : 1; /* IB Parity Error 1 */Q unsigned ka0905_cpu$v_esreg_ibei_1 : 2; /* IB Error Info 1 */N unsigned ka0905_cpu$v_esreg_ibs_1 : 1; /* IB Summary 1 */R unsigned ka0905_cpu$v_esreg_cbef_1 : 4; /* CB Error Fiel=0d 1 */< unsigned ka0905_cpu$v_esreg_fill_06 : 4;N unsigned ka0905_cpu$v_esreg_cbs_1 : 1; /* CB Summary 1 */N unsigned ka0905_cpu$v_esreg_cbc_1 : 1; /* CB CMDR 1 */< unsigned ka0905_cpu$v_esreg_fill_07 : 2;Q unsigned ka0905_cpu$v_esreg_evnr_1 : 1; /* EV Noresponse 1 */N unsigned ka0905_cpu$v_esreg_evsf_1 : 1; /* EX Sysfail 1 */< unsigned ka0905_cpu$v_esreg_fi>0ll_08 : 2;0 } ka0905_cpu$r_esreg_h_bits;1 } ka0905_cpu$r_esreg_fields_h_ol;( } ka0905_cpu$r_esreg_fields; } ka0905_cpu$r_esreg_ol;# char ka0905_cpu$b_fill_02 [24];N/* EVBCR Control Register, EVBCR */ __union {# __int64 ka0905_cpu$q_evbcr; __struct { __union {2 unsigned int ka0905_cpu$l_evbcr_l; __struct {` ?0 unsigned ka0905_cpu$v_evbcr_eacbpc_0 : 1; /* Enable Addr-CMD Bus Parity 0 */< unsigned ka0905_cpu$v_evbcr_fill_01 : 3;Y unsigned ka0905_cpu$v_evbcr_ecei_0 : 1; /* Enable Corr Error Int 0 */X unsigned ka0905_cpu$v_evbcr_eec_0 : 1; /* Enable ECC Correction 0 */_ unsigned ka0905_cpu$v_evbcr_erec_0 : 1; /* Enable Rattler ECC Checking 0 */= unsigned ka0905_cpu$v_evbcr_fill_02 : 20;R @0 unsigned ka0905_cpu$v_evbcr_ffs : 1; /* Force Filled Shared */V unsigned ka0905_cpu$v_evbcr_rsfs : 1; /* RMM STXC Filled Shared */< unsigned ka0905_cpu$v_evbcr_fill_03 : 3;0 } ka0905_cpu$r_evbcr_l_bits;1 } ka0905_cpu$r_evbcr_fields_l_ol; __union {2 unsigned int ka0905_cpu$l_evbcr_h; __struct {` unsigned ka0905_cpu$v_evbcr_eacbpc_1 : 1; /* Enable Addr-CMD BA0us Parity 1 */< unsigned ka0905_cpu$v_evbcr_fill_04 : 3;Y unsigned ka0905_cpu$v_evbcr_ecei_1 : 1; /* Enable Corr Error Int 1 */X unsigned ka0905_cpu$v_evbcr_eec_1 : 1; /* Enable ECC Correction 1 */_ unsigned ka0905_cpu$v_evbcr_erec_1 : 1; /* Enable Rattler ECC Checking 1 */\ unsigned ka0905_cpu$v_evbcr_deec_1 : 1; /* Disable EV5 ECC Checking 1 */= unsigned ka0905_cpu$v_evbcr_fill_0B05 : 24;0 } ka0905_cpu$r_evbcr_h_bits;1 } ka0905_cpu$r_evbcr_fields_h_ol;( } ka0905_cpu$r_evbcr_fields; } ka0905_cpu$r_evbcr_ol;# char ka0905_cpu$b_fill_03 [24];N/* EVB Victim Error Address Register, EVBVEAR */ __union {% __int64 ka0905_cpu$q_evbvear; __struct { __union {4 unsigned int ka0905_cpu$l_evbvear_l; __struct {X C0 unsigned ka0905_cpu$v_evbvear_vea_0 : 30; /* Victim Err Address 0 */> unsigned ka0905_cpu$v_evbvear_fill_01 : 2;2 } ka0905_cpu$r_evbvear_l_bits;3 } ka0905_cpu$r_evbvear_fields_l_ol; __union {4 unsigned int ka0905_cpu$l_evbvear_h; __struct {X unsigned ka0905_cpu$v_evbvear_vea_1 : 30; /* Victim Err Address 1 */> unsigned ka0905_cpu$v_evbvear_fill_02 : 2; D02 } ka0905_cpu$r_evbvear_h_bits;3 } ka0905_cpu$r_evbvear_fields_h_ol;* } ka0905_cpu$r_evbvear_fields;" } ka0905_cpu$r_evbvear_ol;# char ka0905_cpu$b_fill_04 [24];N/* EVB Correctable Error Register, EVBCER */ __union {$ __int64 ka0905_cpu$q_evbcer; __struct { __union {3 unsigned int ka0905_cpu$l_evbcer_l; __struct {T E0 unsigned ka0905_cpu$v_evbcer_ce_0 : 2; /* Correctable Error 0 */N unsigned ka0905_cpu$v_evbcer_rd_0 : 1; /* Read Dirty 0 */\ unsigned ka0905_cpu$v_evbcer_mce_0 : 1; /* Missed correctable Error 0 */= unsigned ka0905_cpu$v_evbcer_fill_01 : 4;O unsigned ka0905_cpu$v_evbcer_es_0 : 8; /* ECC Syndrome 0 */O unsigned ka0905_cpu$v_evbcer_es_2 : 8; /* ECC Syndrome 2 */= unsigned ka090 F05_cpu$v_evbcer_fill_02 : 8;1 } ka0905_cpu$r_evbcer_l_bits;2 } ka0905_cpu$r_evbcer_fields_l_ol; __union {3 unsigned int ka0905_cpu$l_evbcer_h; __struct {T unsigned ka0905_cpu$v_evbcer_ce_1 : 2; /* Correctable Error 1 */N unsigned ka0905_cpu$v_evbcer_rd_1 : 1; /* Read Dirty 1 */\ unsigned ka0905_cpu$v_evbcer_mce_1 : 1; /* Missed correctable Error 1 */= G0 unsigned ka0905_cpu$v_evbcer_fill_03 : 4;O unsigned ka0905_cpu$v_evbcer_es_1 : 8; /* ECC Syndrome 1 */O unsigned ka0905_cpu$v_evbcer_es_3 : 8; /* ECC Syndrome 3 */= unsigned ka0905_cpu$v_evbcer_fill_04 : 8;1 } ka0905_cpu$r_evbcer_h_bits;2 } ka0905_cpu$r_evbcer_fields_h_ol;) } ka0905_cpu$r_evbcer_fields;! } ka0905_cpu$r_evbcer_ol;# char ka0905_cpu$b_fill_05 [24] H0;N/* EVB Correctable Error Address Register, EVBCEAR */ __union {% __int64 ka0905_cpu$q_evbcear; __struct { __union {4 unsigned int ka0905_cpu$l_evbcear_l; __struct {S unsigned ka0905_cpu$v_evbcear_cea_0 : 32; /* Corr Err Addr 0 */2 } ka0905_cpu$r_evbcear_l_bits;3 } ka0905_cpu$r_evbcear_fields_l_ol; __union {4 unsi I0gned int ka0905_cpu$l_evbcear_h; __struct {S unsigned ka0905_cpu$v_evbcear_cea_1 : 32; /* Corr Err Addr 1 */2 } ka0905_cpu$r_evbcear_h_bits;3 } ka0905_cpu$r_evbcear_fields_h_ol;* } ka0905_cpu$r_evbcear_fields;" } ka0905_cpu$r_evbcear_ol;# char ka0905_cpu$b_fill_06 [24];N/* EVB Uncorrectable Error Register, EVBUER */ __union {$ __int64 ka0905_cpu$q_evbuer; J0 __struct { __union {3 unsigned int ka0905_cpu$l_evbuer_l; __struct {V unsigned ka0905_cpu$v_evbuer_ue_0 : 2; /* Uncorrectable Error 0 */N unsigned ka0905_cpu$v_evbuer_rd_0 : 1; /* Read Dirty 0 */= unsigned ka0905_cpu$v_evbuer_fill_01 : 1;` unsigned ka0905_cpu$v_evbuer_peacb_0 : 1; /* Parity Err on Addr-CMD Bus 0 */^ unsigned ka0905_cpu$v_evK0buer_peva_0 : 1; /* Parity Err on Victim Addr 0 */= unsigned ka0905_cpu$v_evbuer_fill_02 : 2;O unsigned ka0905_cpu$v_evbuer_es_0 : 8; /* ECC Syndrome 0 */O unsigned ka0905_cpu$v_evbuer_es_2 : 8; /* ECC Syndrome 2 */= unsigned ka0905_cpu$v_evbuer_fill_03 : 4;Q unsigned ka0905_cpu$v_evbuer_evbcb_0 : 4; /* EVB CMD-Bus 0 */1 } ka0905_cpu$r_evbuer_l_bits;2 } ka0905_c L0pu$r_evbuer_fields_l_ol; __union {3 unsigned int ka0905_cpu$l_evbuer_h; __struct {V unsigned ka0905_cpu$v_evbuer_ue_1 : 2; /* Uncorrectable Error 1 */N unsigned ka0905_cpu$v_evbuer_rd_1 : 1; /* Read Dirty 1 */= unsigned ka0905_cpu$v_evbuer_fill_04 : 1;` unsigned ka0905_cpu$v_evbuer_peacb_1 : 1; /* Parity Err on Addr-CMD Bus 1 */^ unsigned ka0905_cpu$v_M0evbuer_peva_1 : 1; /* Parity Err on Victim Addr 1 */= unsigned ka0905_cpu$v_evbuer_fill_05 : 2;O unsigned ka0905_cpu$v_evbuer_es_1 : 8; /* ECC Syndrome 1 */O unsigned ka0905_cpu$v_evbuer_es_3 : 8; /* ECC Syndrome 3 */= unsigned ka0905_cpu$v_evbuer_fill_06 : 4;Q unsigned ka0905_cpu$v_evbuer_evbcb_1 : 4; /* EVB CMD-Bus 1 */1 } ka0905_cpu$r_evbuer_h_bits;2 } ka0905 N0_cpu$r_evbuer_fields_h_ol;) } ka0905_cpu$r_evbuer_fields;! } ka0905_cpu$r_evbuer_ol;# char ka0905_cpu$b_fill_07 [24];N/* EVB Uncorrectable Error Address Register, EVBUEAR */ __union {% __int64 ka0905_cpu$q_evbuear; __struct { __union {4 unsigned int ka0905_cpu$l_evbuear_l; __struct {X unsigned ka0905_cpu$v_evbuear_uea_0 : 32; /* Uncorr Err Address 0 */2 O0 } ka0905_cpu$r_evbuear_l_bits;3 } ka0905_cpu$r_evbuear_fields_l_ol; __union {4 unsigned int ka0905_cpu$l_evbuear_h; __struct {X unsigned ka0905_cpu$v_evbuear_uea_1 : 32; /* Uncorr Err Address 1 */2 } ka0905_cpu$r_evbuear_h_bits;3 } ka0905_cpu$r_evbuear_fields_h_ol;* } ka0905_cpu$r_evbuear_fields;" } ka0905_cpu$r_evbuear_ol;# char ka0905_cpu$ P0b_fill_08 [24];N/* EVB Reserver Register, EVBRESV */ __union {% __int64 ka0905_cpu$q_evbresv; __struct { __union {4 unsigned int ka0905_cpu$l_evbresv_l; __struct {? unsigned ka0905_cpu$v_evbresv_fill_01 : 32;2 } ka0905_cpu$r_evbresv_l_bits;3 } ka0905_cpu$r_evbresv_fields_l_ol; __union {4 unsigned i Q0nt ka0905_cpu$l_evbresv_h; __struct {? unsigned ka0905_cpu$v_evbresv_fill_02 : 32;2 } ka0905_cpu$r_evbresv_h_bits;3 } ka0905_cpu$r_evbresv_fields_h_ol;* } ka0905_cpu$r_evbresv_fields;" } ka0905_cpu$r_evbresv_ol;# char ka0905_cpu$b_fill_09 [24];N/* Duplicate tag Control Register, DTCTR */ __union {# __int64 ka0905_cpu$q_dtctr; __struct { R0 __union {2 unsigned int ka0905_cpu$l_dtctr_l; __struct {W unsigned ka0905_cpu$v_dtctr_dte_0 : 1; /* Duplicate Tag Enable 0 */< unsigned ka0905_cpu$v_dtctr_fill_01 : 3;\ unsigned ka0905_cpu$v_dtctr_ecpc_0 : 1; /* Ena ctrl Parity Checking 0 */W unsigned ka0905_cpu$v_dtctr_fbcp : 1; /* Fill Bad Control Parity */< unsigned ka0905_cpu$v_dtctr_fill_02 : 2;^ S0 unsigned ka0905_cpu$v_dtctr_etpc_0 : 1; /* Enable Tag Parity Checking 0 */S unsigned ka0905_cpu$v_dtctr_fbtp : 1; /* Fill Bad Tag Parity */< unsigned ka0905_cpu$v_dtctr_fill_03 : 2;[ unsigned ka0905_cpu$v_dtctr_dtdm_0 : 1; /* Duplicate Tag Diag Mode 0 */= unsigned ka0905_cpu$v_dtctr_fill_04 : 19;0 } ka0905_cpu$r_dtctr_l_bits;1 } ka0905_cpu$r_dtctr_fields_l_ol; T0 __union {2 unsigned int ka0905_cpu$l_dtctr_h; __struct {W unsigned ka0905_cpu$v_dtctr_dte_1 : 1; /* Duplicate Tag Enable 1 */< unsigned ka0905_cpu$v_dtctr_fill_05 : 3;\ unsigned ka0905_cpu$v_dtctr_ecpc_1 : 1; /* Ena ctrl Parity Checking 1 */< unsigned ka0905_cpu$v_dtctr_fill_06 : 3;^ unsigned ka0905_cpu$v_dtctr_etpc_1 : 1; /* Enable Tag Parity Checking 1 */< U0 unsigned ka0905_cpu$v_dtctr_fill_07 : 3;[ unsigned ka0905_cpu$v_dtctr_dtdm_1 : 1; /* Duplicate Tag Diag Mode 1 */= unsigned ka0905_cpu$v_dtctr_fill_08 : 19;0 } ka0905_cpu$r_dtctr_h_bits;1 } ka0905_cpu$r_dtctr_fields_h_ol;( } ka0905_cpu$r_dtctr_fields; } ka0905_cpu$r_dtctr_ol;# char ka0905_cpu$b_fill_10 [24];N/* Duplicate Tag Error Register, DTER V0 */ __union {" __int64 ka0905_cpu$q_dter; __struct { __union {1 unsigned int ka0905_cpu$l_dter_l; __struct {; unsigned ka0905_cpu$v_dter_fill_01 : 5;R unsigned ka0905_cpu$v_dter_dtea : 19; /* DTER Error Address */; unsigned ka0905_cpu$v_dter_fill_02 : 4;T unsigned ka0905_cpu$v_dter_tcpe_0 : 1; /* Tag Con Par Error 0 */; unsi W0gned ka0905_cpu$v_dter_fill_03 : 2;R unsigned ka0905_cpu$v_dter_tpe_0 : 1; /* Tag Parity Error 0 *// } ka0905_cpu$r_dter_l_bits;0 } ka0905_cpu$r_dter_fields_l_ol; __union {1 unsigned int ka0905_cpu$l_dter_h; __struct {< unsigned ka0905_cpu$v_dter_fill_04 : 28;T unsigned ka0905_cpu$v_dter_tcpe_1 : 1; /* Tag Con Par Error 1 */; unsigned k X0a0905_cpu$v_dter_fill_05 : 2;R unsigned ka0905_cpu$v_dter_tpe_1 : 1; /* Tag Parity Error 1 *// } ka0905_cpu$r_dter_h_bits;0 } ka0905_cpu$r_dter_fields_h_ol;' } ka0905_cpu$r_dter_fields; } ka0905_cpu$r_dter_ol;# char ka0905_cpu$b_fill_11 [24];N/* Duplicate_Tag Test Control Register, DTTCR */ __union {# __int64 ka0905_cpu$q_dttcr; __struct { __union Y0 {2 unsigned int ka0905_cpu$l_dttcr_l; __struct {P unsigned ka0905_cpu$v_dttcr_tcf : 3; /* Tag Control Field */X unsigned ka0905_cpu$v_dttcr_tcpf : 1; /* Tag Control Parity Field */< unsigned ka0905_cpu$v_dttcr_fill_01 : 1;N unsigned ka0905_cpu$v_dttcr_af : 15; /* Address Field */U unsigned ka0905_cpu$v_dttcr_mtaf : 4; /* Mux Tag Address Field */P Z0 unsigned ka0905_cpu$v_dttcr_ptf : 7; /* Partial Tag Field */O unsigned ka0905_cpu$v_dttcr_tpf : 1; /* Tag Parity field */0 } ka0905_cpu$r_dttcr_l_bits;1 } ka0905_cpu$r_dttcr_fields_l_ol; __union {2 unsigned int ka0905_cpu$l_dttcr_h; __struct {= unsigned ka0905_cpu$v_dttcr_fill_02 : 32;0 } ka0905_cpu$r_dttcr_h_bits;1 } ka0905_cpu$r_dttcr_f [0ields_h_ol;( } ka0905_cpu$r_dttcr_fields; } ka0905_cpu$r_dttcr_ol;# char ka0905_cpu$b_fill_12 [24];N/* Duplicate Tag Test Register, DTTR */ __union {" __int64 ka0905_cpu$q_dttr; __struct { __union {1 unsigned int ka0905_cpu$l_dttr_l; __struct {N unsigned ka0905_cpu$v_dttr_tc_0 : 3; /* Tag Control 0 */T unsigned ka0905_cp \0u$v_dttr_tcp_0 : 1; /* Tag Control Parity 0 */< unsigned ka0905_cpu$v_dttr_fill_01 : 16;N unsigned ka0905_cpu$v_dttr_td_0 : 11; /* Tag Data 0 */N unsigned ka0905_cpu$v_dttr_tp_0 : 1; /* Tag Parity 0 *// } ka0905_cpu$r_dttr_l_bits;0 } ka0905_cpu$r_dttr_fields_l_ol; __union {1 unsigned int ka0905_cpu$l_dttr_h; __struct {N unsigned k ]0a0905_cpu$v_dttr_tc_1 : 3; /* Tag Control 1 */T unsigned ka0905_cpu$v_dttr_tcp_1 : 1; /* Tag Control Parity 1 */< unsigned ka0905_cpu$v_dttr_fill_02 : 16;N unsigned ka0905_cpu$v_dttr_td_1 : 11; /* Tag Data 1 */N unsigned ka0905_cpu$v_dttr_tp_1 : 1; /* Tag Parity 1 *// } ka0905_cpu$r_dttr_h_bits;0 } ka0905_cpu$r_dttr_fields_h_ol;' } ka0905_cpu$r_dttr_fields; ^0 } ka0905_cpu$r_dttr_ol;# char ka0905_cpu$b_fill_13 [24];N/* Duplicate Tag Reserve Register, DTRESV */ __union {$ __int64 ka0905_cpu$q_dtresv; __struct { __union {3 unsigned int ka0905_cpu$l_dtresv_l; __struct {> unsigned ka0905_cpu$v_dtresv_fill_01 : 32;1 } ka0905_cpu$r_dtresv_l_bits;2 } ka0905_cpu$r_dtresv_fields_l_ol; _0 __union {3 unsigned int ka0905_cpu$l_dtresv_h; __struct {> unsigned ka0905_cpu$v_dtresv_fill_02 : 32;1 } ka0905_cpu$r_dtresv_h_bits;2 } ka0905_cpu$r_dtresv_fields_h_ol;) } ka0905_cpu$r_dtresv_fields;! } ka0905_cpu$r_dtresv_ol;# char ka0905_cpu$b_fill_14 [24];N/* I-Bus Control and Status Register, IBCSR */ __union {# __int64 ka0905_c `0pu$q_ibcsr; __struct { __union {2 unsigned int ka0905_cpu$l_ibcsr_l; __struct {< unsigned ka0905_cpu$v_ibcsr_fill_01 : 4;V unsigned ka0905_cpu$v_ibcsr_ibpe_0 : 1; /* I-bus Parity Error 0 */f unsigned ka0905_cpu$v_ibcsr_scdipe_0 : 1; /* Snoop Cyc During I-bus Par Error 0 */e unsigned ka0905_cpu$v_ibcsr_ccdipe_0 : 1; /* CMDR Cyc During I-bus Par Error 0 */< a0 unsigned ka0905_cpu$v_ibcsr_fill_02 : 5;] unsigned ka0905_cpu$v_ibcsr_eipc_0 : 1; /* Enable I-bus Par Checking 0 */Z unsigned ka0905_cpu$v_ibcsr_dbip_0 : 1; /* Drive Bad I-bus Parity 0 */= unsigned ka0905_cpu$v_ibcsr_fill_03 : 18;0 } ka0905_cpu$r_ibcsr_l_bits;1 } ka0905_cpu$r_ibcsr_fields_l_ol; __union {2 unsigned int ka0905_cpu$l_ibcsr_h; __stb0ruct {< unsigned ka0905_cpu$v_ibcsr_fill_04 : 4;V unsigned ka0905_cpu$v_ibcsr_ibpe_1 : 1; /* I-bus Parity Error 1 */f unsigned ka0905_cpu$v_ibcsr_scdipe_1 : 1; /* Snoop Cyc During I-bus Par Error 1 */e unsigned ka0905_cpu$v_ibcsr_ccdipe_1 : 1; /* CMDR Cyc During I-bus Par Error 1 */< unsigned ka0905_cpu$v_ibcsr_fill_05 : 5;] unsigned ka0905_cpu$v_ibcsr_eipc_1 : 1; /* Enable I-bus c0Par Checking 1 */= unsigned ka0905_cpu$v_ibcsr_fill_06 : 19;0 } ka0905_cpu$r_ibcsr_h_bits;1 } ka0905_cpu$r_ibcsr_fields_h_ol;( } ka0905_cpu$r_ibcsr_fields; } ka0905_cpu$r_ibcsr_ol;# char ka0905_cpu$b_fill_15 [24];N/* I-Bus Error Address Register, IBEAR */ __union {# __int64 ka0905_cpu$q_ibear; __struct { __union {2 unsigned i d0nt ka0905_cpu$l_ibear_l; __struct {U unsigned ka0905_cpu$v_ibear_cbcac_0 : 32; /* C-bus2 CA cycle 0 */0 } ka0905_cpu$r_ibear_l_bits;1 } ka0905_cpu$r_ibear_fields_l_ol; __union {2 unsigned int ka0905_cpu$l_ibear_h; __struct {U unsigned ka0905_cpu$v_ibear_cbcac_1 : 32; /* C-bus2 CA cycle 1 */0 } ka0905_cpu$r_ibear_h_bits;1 e0} ka0905_cpu$r_ibear_fields_h_ol;( } ka0905_cpu$r_ibear_fields; } ka0905_cpu$r_ibear_ol;# char ka0905_cpu$b_fill_16 [24];N/* Arbitrarion Control Register, ACR */ __union {! __int64 ka0905_cpu$q_acr; __struct { __union {0 unsigned int ka0905_cpu$l_acr_l; __struct {P unsigned ka0905_cpu$v_acr_cbe_0 : 1; /* CBUS2 Equalizer 0 */: f0 unsigned ka0905_cpu$v_acr_fill_01 : 3;P unsigned ka0905_cpu$v_acr_bme_0 : 1; /* Bad Mode Enable 0 */S unsigned ka0905_cpu$v_acr_dme_0 : 1; /* Donate Mode Enable 0 */: unsigned ka0905_cpu$v_acr_fill_02 : 2;Q unsigned ka0905_cpu$v_acr_pme_0 : 1; /* Pawn Mode Enable 0 */N unsigned ka0905_cpu$v_acr_bcre_0 : 1; /* BCREQ Enable 0 */: unsigned ka0905_cpu$v_acr_fill_03 : 2;W g0 unsigned ka0905_cpu$v_acr_dcbr_0 : 1; /* Disable CBUS2 Request 0 */; unsigned ka0905_cpu$v_acr_fill_04 : 19;. } ka0905_cpu$r_acr_l_bits;/ } ka0905_cpu$r_acr_fields_l_ol; __union {0 unsigned int ka0905_cpu$l_acr_h; __struct {P unsigned ka0905_cpu$v_acr_cbe_1 : 1; /* CBUS2 Equalizer 1 */: unsigned ka0905_cpu$v_acr_fill_05 : 3;P h0unsigned ka0905_cpu$v_acr_bme_1 : 1; /* Bad Mode Enable 1 */S unsigned ka0905_cpu$v_acr_dme_1 : 1; /* Donate Mode Enable 1 */: unsigned ka0905_cpu$v_acr_fill_06 : 2;Q unsigned ka0905_cpu$v_acr_pme_1 : 1; /* Pawn Mode Enable 1 */N unsigned ka0905_cpu$v_acr_bcre_1 : 1; /* BCREQ Enable 1 */: unsigned ka0905_cpu$v_acr_fill_07 : 2;W unsigned ka0905_cpu$v_acr_dcbr_1 : 1; /* Disable CBUS2 i0 Request 1 */; unsigned ka0905_cpu$v_acr_fill_08 : 19;. } ka0905_cpu$r_acr_h_bits;/ } ka0905_cpu$r_acr_fields_h_ol;& } ka0905_cpu$r_acr_fields; } ka0905_cpu$r_acr_ol;# char ka0905_cpu$b_fill_17 [24];N/* Cobra-bus2 Control Register, CBCR */ __union {" __int64 ka0905_cpu$q_cbcr; __struct { __union {1 unsigned int ka0905_cpu$l_ j0cbcr_l; __struct {X unsigned ka0905_cpu$v_cbcr_epc_0 : 1; /* Enable Parity Checking 0 */S unsigned ka0905_cpu$v_cbcr_dwp_0 : 1; /* Data Wrong Parity 0 */S unsigned ka0905_cpu$v_cbcr_cawp_0 : 1; /* C/A Wrong Parity 0 */; unsigned ka0905_cpu$v_cbcr_fill_01 : 1;N unsigned ka0905_cpu$v_cbcr_fs : 1; /* Force Shared */; unsigned ka0905_cpu$v_cbcr_fill_02 : 7;] k0 unsigned ka0905_cpu$v_cbcr_ecbei_0 : 1; /* Enable CBUS Err Interrupt 0 */; unsigned ka0905_cpu$v_cbcr_fill_03 : 3;[ unsigned ka0905_cpu$v_cbcr_dsrc : 1; /* Dis Shared Response checking */< unsigned ka0905_cpu$v_cbcr_fill_04 : 15;/ } ka0905_cpu$r_cbcr_l_bits;0 } ka0905_cpu$r_cbcr_fields_l_ol; __union {1 unsigned int ka0905_cpu$l_cbcr_h; l0__struct {X unsigned ka0905_cpu$v_cbcr_epc_1 : 1; /* Enable Parity Checking 1 */S unsigned ka0905_cpu$v_cbcr_dwp_1 : 1; /* Date Wrong Parity 1 */S unsigned ka0905_cpu$v_cbcr_cawp_1 : 1; /* C/A Wrong Parity 1 */; unsigned ka0905_cpu$v_cbcr_fill_05 : 5;N unsigned ka0905_cpu$v_cbcr_cid : 3; /* Commander ID */; unsigned ka0905_cpu$v_cbcr_fill_06 : 1;] unsign m0ed ka0905_cpu$v_cbcr_ecbei_1 : 1; /* Enable CBUS Err Interrupt 0 */< unsigned ka0905_cpu$v_cbcr_fill_07 : 19;/ } ka0905_cpu$r_cbcr_h_bits;0 } ka0905_cpu$r_cbcr_fields_h_ol;' } ka0905_cpu$r_cbcr_fields; } ka0905_cpu$r_cbcr_ol;# char ka0905_cpu$b_fill_18 [24];N/* Cobra-bus2 Error Register, CBER */ __union {" __int64 ka0905_cpu$q_cber; __struct { n0 __union {1 unsigned int ka0905_cpu$l_cber_l; __struct {Z unsigned ka0905_cpu$v_cber_ure_0 : 1; /* Uncorrectable Read Error 0 */; unsigned ka0905_cpu$v_cber_fill_01 : 3;Z unsigned ka0905_cpu$v_cber_callpe_0 : 1; /* C/A Low LW Parity Err 0 */[ unsigned ka0905_cpu$v_cber_cahlpe_0 : 1; /* C/A Hign LW Parity Err 0 */; unsigned ka0905_cpu$v_cber_fill_02 : 2;[ o0 unsigned ka0905_cpu$v_cber_pelw0wd : 1; /* Parity Err LW0 Write Data */[ unsigned ka0905_cpu$v_cber_pelw1wd : 1; /* Parity Err LW1 Write Data */[ unsigned ka0905_cpu$v_cber_pelw4wd : 1; /* Parity Err LW4 Write Data */[ unsigned ka0905_cpu$v_cber_pelw5wd : 1; /* Parity Err LW5 Write Data */; unsigned ka0905_cpu$v_cber_fill_03 : 4;Z unsigned ka0905_cpu$v_cber_pelw0rd : 1; /* Parity Erp0r LW0 Read Data */Z unsigned ka0905_cpu$v_cber_pelw1rd : 1; /* Parity Err LW1 Read Data */Z unsigned ka0905_cpu$v_cber_pelw4rd : 1; /* Parity Err LW4 Read Data */Z unsigned ka0905_cpu$v_cber_pelw5rd : 1; /* Parity Err LW5 Read Data */X unsigned ka0905_cpu$v_cber_usr : 1; /* Unexpected Shared Response */; unsigned ka0905_cpu$v_cber_fill_04 : 3;N unsigned ka0905_cpu$v_cber_cana : 1; / q0* C/A Not Acked */; unsigned ka0905_cpu$v_cber_fill_05 : 3;O unsigned ka0905_cpu$v_cber_d0na : 1; /* Data 0 Not Acked */O unsigned ka0905_cpu$v_cber_d1na : 1; /* Data 1 Not Acked */; unsigned ka0905_cpu$v_cber_fill_06 : 2;/ } ka0905_cpu$r_cber_l_bits;0 } ka0905_cpu$r_cber_fields_l_ol; __union {1 unsigned int ka0905_cpu$l_cber_h; __str0ruct {Z unsigned ka0905_cpu$v_cber_ucr_1 : 1; /* Uncorrectable Read Error 1 */; unsigned ka0905_cpu$v_cber_fill_07 : 3;Z unsigned ka0905_cpu$v_cber_callpe_1 : 1; /* C/A Low LW Parity Err 1 */[ unsigned ka0905_cpu$v_cber_cahlpe_1 : 1; /* C/A High LW Parity Err 1 */; unsigned ka0905_cpu$v_cber_fill_08 : 2;[ unsigned ka0905_cpu$v_cber_pelw2wd : 1; /* Parity Err LW2 Write Data */[s0 unsigned ka0905_cpu$v_cber_pelw3wd : 1; /* Parity Err LW3 Write Data */[ unsigned ka0905_cpu$v_cber_pelw6wd : 1; /* Parity Err LW6 Write Data */[ unsigned ka0905_cpu$v_cber_pelw7wd : 1; /* Parity Err LW7 Write Data */; unsigned ka0905_cpu$v_cber_fill_09 : 4;Z unsigned ka0905_cpu$v_cber_pelw2rd : 1; /* Parity Err LW2 Read Data */Z unsigned ka0905_cpu$v_cber_pelw3rd : 1; /* Parity t0Err LW3 Read Data */Z unsigned ka0905_cpu$v_cber_pelw6rd : 1; /* Parity Err LW6 Read Data */Z unsigned ka0905_cpu$v_cber_pelw7rd : 1; /* Parity Err LW7 Read Data */< unsigned ka0905_cpu$v_cber_fill_10 : 12;/ } ka0905_cpu$r_cber_h_bits;0 } ka0905_cpu$r_cber_fields_h_ol;' } ka0905_cpu$r_cber_fields; } ka0905_cpu$r_cber_ol;# char ka0905_cpu$b_fill_19 [24];N/* Cobra-bus2 Error Addr u0ess Low Register, CBEALR */ __union {$ __int64 ka0905_cpu$q_cbealr; __struct { __union {3 unsigned int ka0905_cpu$l_cbealr_l; __struct {X unsigned ka0905_cpu$v_cbealr_cbla_0 : 32; /* CBus 2 Low Address 0 */1 } ka0905_cpu$r_cbealr_l_bits;2 } ka0905_cpu$r_cbealr_fields_l_ol; __union {3 unsigned int ka0905_cpu$l_cbealr v0_h; __struct {X unsigned ka0905_cpu$v_cbealr_cbla_1 : 32; /* CBus 2 Low Address 1 */1 } ka0905_cpu$r_cbealr_h_bits;2 } ka0905_cpu$r_cbealr_fields_h_ol;) } ka0905_cpu$r_cbealr_fields;! } ka0905_cpu$r_cbealr_ol;# char ka0905_cpu$b_fill_20 [24];N/* Cobra-bus2 Error Address High Register, CBEAHR */ __union {$ __int64 ka0905_cpu$q_cbeahr; __struct { w0 __union {3 unsigned int ka0905_cpu$l_cbeahr_l; __struct {V unsigned ka0905_cpu$v_cbeahr_cbha_0 : 32; /* CBus 2 High Addr 0 */1 } ka0905_cpu$r_cbeahr_l_bits;2 } ka0905_cpu$r_cbeahr_fields_l_ol; __union {3 unsigned int ka0905_cpu$l_cbeahr_h; __struct {V unsigned ka0905_cpu$v_cbeahr_cbha_1 : 32; /* CBus 2 High Addr 1 */1 x0 } ka0905_cpu$r_cbeahr_h_bits;2 } ka0905_cpu$r_cbeahr_fields_h_ol;) } ka0905_cpu$r_cbeahr_fields;! } ka0905_cpu$r_cbeahr_ol;# char ka0905_cpu$b_fill_21 [24];N/* Cobra-bus2 Reserve Register, CBRESV */ __union {$ __int64 ka0905_cpu$q_cbresv; __struct { __union {3 unsigned int ka0905_cpu$l_cbresv_l; __struct {> unsigned ka0 y0905_cpu$v_cbresv_fill_01 : 32;1 } ka0905_cpu$r_cbresv_l_bits;2 } ka0905_cpu$r_cbresv_fields_l_ol; __union {3 unsigned int ka0905_cpu$l_cbresv_h; __struct {> unsigned ka0905_cpu$v_cbresv_fill_02 : 32;1 } ka0905_cpu$r_cbresv_h_bits;2 } ka0905_cpu$r_cbresv_fields_h_ol;) } ka0905_cpu$r_cbresv_fields;! } ka0905_cpu$r_cbresv_ol;# char ka090 z05_cpu$b_fill_22 [24];N/* Address Lock Register, ALR */ __union {! __int64 ka0905_cpu$q_alr; __struct { __union {0 unsigned int ka0905_cpu$l_alr_l; __struct {S unsigned ka0905_cpu$v_alr_lav_0 : 1; /* Lock Address Valid 0 */: unsigned ka0905_cpu$v_alr_fill_01 : 4;N unsigned ka0905_cpu$v_alr_la_0 : 27; /* Lock Address 0 */ {0. } ka0905_cpu$r_alr_l_bits;/ } ka0905_cpu$r_alr_fields_l_ol; __union {0 unsigned int ka0905_cpu$l_alr_h; __struct {S unsigned ka0905_cpu$v_alr_lav_1 : 1; /* Lock Address Valid 1 */: unsigned ka0905_cpu$v_alr_fill_02 : 4;N unsigned ka0905_cpu$v_alr_la_1 : 27; /* Lock Address 1 */. } ka0905_cpu$r_alr_h_bits;/ } ka0905_cpu |0$r_alr_fields_h_ol;& } ka0905_cpu$r_alr_fields; } ka0905_cpu$r_alr_ol;# char ka0905_cpu$b_fill_23 [24];N/* Processor Mailbox Register, PMBR */ __union {" __int64 ka0905_cpu$q_pmbr; __struct { __union {1 unsigned int ka0905_cpu$l_pmbr_l; __struct {N unsigned ka0905_cpu$v_pmbr_data_0 : 32; /* Data 0 *// } ka0905_cpu$r }0_pmbr_l_bits;0 } ka0905_cpu$r_pmbr_fields_l_ol; __union {1 unsigned int ka0905_cpu$l_pmbr_h; __struct {N unsigned ka0905_cpu$v_pmbr_data_1 : 32; /* Data 1 *// } ka0905_cpu$r_pmbr_h_bits;0 } ka0905_cpu$r_pmbr_fields_h_ol;' } ka0905_cpu$r_pmbr_fields; } ka0905_cpu$r_pmbr_ol;# char ka0905_cpu$b_fill_24 [24];N/* Inter-processor Interrupt Request Reg~0ister, IIRR */ __union {" __int64 ka0905_cpu$q_iirr; __struct { __union {1 unsigned int ka0905_cpu$l_iirr_l; __struct {; unsigned ka0905_cpu$v_iirr_fill_0 : 32;/ } ka0905_cpu$r_iirr_l_bits;0 } ka0905_cpu$r_iirr_fields_l_ol; __union {1 unsigned int ka0905_cpu$l_iirr_h; __struct {< 0 unsigned ka0905_cpu$v_iirr_fill_02 : 12;U unsigned ka0905_cpu$v_iirr_rhi : 1; /* Requiest Halt Interrupt */; unsigned ka0905_cpu$v_iirr_fill_03 : 3;U unsigned ka0905_cpu$v_iirr_ii : 1; /* Interprocessor Interrupt */< unsigned ka0905_cpu$v_iirr_fill_04 : 15;/ } ka0905_cpu$r_iirr_h_bits;0 } ka0905_cpu$r_iirr_fields_h_ol;' } ka0905_cpu$r_iirr_fields; } ka0905_cpu 0$r_iirr_ol;# char ka0905_cpu$b_fill_25 [24];N/* System Interrupt Clear Register, SICR */ __union {" __int64 ka0905_cpu$q_sicr; __struct { __union {1 unsigned int ka0905_cpu$l_sicr_l; __struct {] unsigned ka0905_cpu$v_sicr_cbeic_0 : 1; /* CBus2 Err Interrupt Clear 0 */< unsigned ka0905_cpu$v_sicr_fill_01 : 31;/ } ka0905_cpu$r_s 0icr_l_bits;0 } ka0905_cpu$r_sicr_fields_l_ol; __union {1 unsigned int ka0905_cpu$l_sicr_h; __struct {] unsigned ka0905_cpu$v_sicr_cbeic_1 : 1; /* CBus2 Err Interrupt Clear 1 */; unsigned ka0905_cpu$v_sicr_fill_02 : 3;V unsigned ka0905_cpu$v_sicr_iti : 1; /* Interval Timer Interrupt */; unsigned ka0905_cpu$v_sicr_fill_03 : 3;P unsigned0 ka0905_cpu$v_sicr_sec : 1; /* System Event Clear */; unsigned ka0905_cpu$v_sicr_fill_04 : 3;X unsigned ka0905_cpu$v_sicr_nhic : 1; /* Node Halt-Interrupt Clear */; unsigned ka0905_cpu$v_sicr_fill_05 : 3;V unsigned ka0905_cpu$v_sicr_iic : 1; /* Interprocessor Int Clear */; unsigned ka0905_cpu$v_sicr_fill_06 : 3;P unsigned ka0905_cpu$v_sicr_ioii : 2; /* I/O Interrupt IRQ */< 0 unsigned ka0905_cpu$v_sicr_fill_07 : 10;/ } ka0905_cpu$r_sicr_h_bits;0 } ka0905_cpu$r_sicr_fields_h_ol;' } ka0905_cpu$r_sicr_fields; } ka0905_cpu$r_sicr_ol;# char ka0905_cpu$b_fill_26 [24];N/* Performance Monitor Control Register, PMCR */ __union {" __int64 ka0905_cpu$q_pmcr; __struct { __union {1 unsigned int ka0905_cpu$l_pmcr_l; 0 __struct {N unsigned ka0905_cpu$v_pmcr_ss_0 : 1; /* Start Stop 0 */; unsigned ka0905_cpu$v_pmcr_fill_01 : 3;N unsigned ka0905_cpu$v_pmcr_am_0 : 2; /* Address Match 0 */; unsigned ka0905_cpu$v_pmcr_fill_02 : 6;N unsigned ka0905_cpu$v_pmcr_spmr10 : 4; /* Select PMR10 */N unsigned ka0905_cpu$v_pmcr_spmr9 : 4; /* Select PMR9 */N unsigned ka0905_cp 0u$v_pmcr_spmr8 : 4; /* Select PMR8 */N unsigned ka0905_cpu$v_pmcr_spmr7 : 4; /* Select PMR7 */N unsigned ka0905_cpu$v_pmcr_spmr6 : 4; /* Select PMR6 *// } ka0905_cpu$r_pmcr_l_bits;0 } ka0905_cpu$r_pmcr_fields_l_ol; __union {1 unsigned int ka0905_cpu$l_pmcr_h; __struct {N unsigned ka0905_cpu$v_pmcr_ss_1 : 1; /* Start Stop 1 */U 0 unsigned ka0905_cpu$v_pmcr_epmo : 2; /* Enable Perf Mon Output */; unsigned ka0905_cpu$v_pmcr_fill_03 : 1;N unsigned ka0905_cpu$v_pmcr_am_1 : 2; /* Address Match 1 */N unsigned ka0905_cpu$v_pmcr_cidmask : 3; /* CID Mask */N unsigned ka0905_cpu$v_pmcr_cidmatch : 3; /* CIT Match */N unsigned ka0905_cpu$v_pmcr_spmr5 : 4; /* Select PMR5 */N unsigned ka0905_cpu$v_pmcr_spmr4 : 0 4; /* Select PMR4 */N unsigned ka0905_cpu$v_pmcr_spmr3 : 4; /* Select PMR3 */N unsigned ka0905_cpu$v_pmcr_spmr2 : 4; /* Select PMR2 */N unsigned ka0905_cpu$v_pmcr_spmr1 : 4; /* Select PMR1 *// } ka0905_cpu$r_pmcr_h_bits;0 } ka0905_cpu$r_pmcr_fields_h_ol;' } ka0905_cpu$r_pmcr_fields; } ka0905_cpu$r_pmcr_ol;# char ka0905_cpu$b_fill_27 [24];N/* Performance Monitor Reg 0ister 1, PMR1 */ __union {" __int64 ka0905_cpu$q_pmr1; __struct { __union {1 unsigned int ka0905_cpu$l_pmr1_l; __struct {N unsigned ka0905_cpu$v_pmr1_c6 : 31; /* Counter 6 */N unsigned ka0905_cpu$v_pmr1_of6 : 1; /* Overflow 6 *// } ka0905_cpu$r_pmr1_l_bits;0 } ka0905_cpu$r_pmr1_fields_l_ol; 0__union {1 unsigned int ka0905_cpu$l_pmr1_h; __struct {N unsigned ka0905_cpu$v_pmr1_c1 : 31; /* Counter 1 */N unsigned ka0905_cpu$v_pmr1_of1 : 1; /* Overflow 1 *// } ka0905_cpu$r_pmr1_h_bits;0 } ka0905_cpu$r_pmr1_fields_h_ol;' } ka0905_cpu$r_pmr1_fields; } ka0905_cpu$r_pmr1_ol;# char ka0905_cpu$b_fill_28 [24];N/* Performance Monitor Register 2, PMR 02 */ __union {" __int64 ka0905_cpu$q_pmr2; __struct { __union {1 unsigned int ka0905_cpu$l_pmr2_l; __struct {N unsigned ka0905_cpu$v_pmr2_c7 : 31; /* Counter 7 */N unsigned ka0905_cpu$v_pmr2_of7 : 1; /* Overflow 7 *// } ka0905_cpu$r_pmr2_l_bits;0 } ka0905_cpu$r_pmr2_fields_l_ol; __union {1 0 unsigned int ka0905_cpu$l_pmr2_h; __struct {N unsigned ka0905_cpu$v_pmr2_c2 : 31; /* Counter 2 */N unsigned ka0905_cpu$v_pmr2_of2 : 1; /* Overflow 2 *// } ka0905_cpu$r_pmr2_h_bits;0 } ka0905_cpu$r_pmr2_fields_h_ol;' } ka0905_cpu$r_pmr2_fields; } ka0905_cpu$r_pmr2_ol;# char ka0905_cpu$b_fill_29 [24];N/* Performance Monitor Register 3, PMR3 0 */ __union {" __int64 ka0905_cpu$q_pmr3; __struct { __union {1 unsigned int ka0905_cpu$l_pmr3_l; __struct {N unsigned ka0905_cpu$v_pmr3_c8 : 31; /* Counter 8 */N unsigned ka0905_cpu$v_pmr3_of8 : 1; /* Overflow 8 *// } ka0905_cpu$r_pmr3_l_bits;0 } ka0905_cpu$r_pmr3_fields_l_ol; __union {1 0 unsigned int ka0905_cpu$l_pmr3_h; __struct {N unsigned ka0905_cpu$v_pmr3_c3 : 31; /* Counter 3 */N unsigned ka0905_cpu$v_pmr3_of3 : 1; /* Overflow 3 *// } ka0905_cpu$r_pmr3_h_bits;0 } ka0905_cpu$r_pmr3_fields_h_ol;' } ka0905_cpu$r_pmr3_fields; } ka0905_cpu$r_pmr3_ol;# char ka0905_cpu$b_fill_30 [24];N/* Performance Monitor Register 4, PMR4 0 */ __union {" __int64 ka0905_cpu$q_pmr4; __struct { __union {1 unsigned int ka0905_cpu$l_pmr4_l; __struct {N unsigned ka0905_cpu$v_pmr4_c9 : 31; /* Counter 9 */N unsigned ka0905_cpu$v_pmr4_of9 : 1; /* Overflow 9 *// } ka0905_cpu$r_pmr4_l_bits;0 } ka0905_cpu$r_pmr4_fields_l_ol; __union {1 unsigned 0 int ka0905_cpu$l_pmr4_h; __struct {N unsigned ka0905_cpu$v_pmr4_c4 : 31; /* Counter 4 */N unsigned ka0905_cpu$v_pmr4_of4 : 1; /* Overflow 4 *// } ka0905_cpu$r_pmr4_h_bits;0 } ka0905_cpu$r_pmr4_fields_h_ol;' } ka0905_cpu$r_pmr4_fields; } ka0905_cpu$r_pmr4_ol;# char ka0905_cpu$b_fill_31 [24];N/* Performance Monitor Register 5, PMR5 0 */ __union {" __int64 ka0905_cpu$q_pmr5; __struct { __union {1 unsigned int ka0905_cpu$l_pmr5_l; __struct {N unsigned ka0905_cpu$v_pmr5_c10 : 31; /* Counter 10 */N unsigned ka0905_cpu$v_pmr5_of10 : 1; /* Overflow 10 *// } ka0905_cpu$r_pmr5_l_bits;0 } ka0905_cpu$r_pmr5_fields_l_ol; __union {1 unsigned int ka0905_ 0cpu$l_pmr5_h; __struct {N unsigned ka0905_cpu$v_pmr5_c5 : 31; /* Counter 5 */N unsigned ka0905_cpu$v_pmr5_of5 : 1; /* Overflow 5 *// } ka0905_cpu$r_pmr5_h_bits;0 } ka0905_cpu$r_pmr5_fields_h_ol;' } ka0905_cpu$r_pmr5_fields; } ka0905_cpu$r_pmr5_ol; } KA0905_CPU; #if !defined(__VAXC)@#define ka0905_cpu$q_creg ka0905_cpu$r_creg_ol.ka0905_cpu$q_creg{#define ka09005_cpu$l_creg_l ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$l_creg_l#define ka0905_cpu$v_creg_rn_0 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$r_creg_l_bits\.ka0905_cpu$v_creg_rn_0#define ka0905_cpu$v_creg_fill_01 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$r_creg_l_b\its.ka0905_cpu$v_creg_fill_01#define ka0905_cpu$v_creg_ebss_0 ka0905_cpu$r_creg_ol.ka0905_cpu$r0_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$r_creg_l_bi\ts.ka0905_cpu$v_creg_ebss_0#define ka0905_cpu$v_creg_fill_02 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$r_creg_l_b\its.ka0905_cpu$v_creg_fill_02#define ka0905_cpu$v_creg_eedly_0 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$r_creg_l_b\its.ka0905_cpu$v_creg_eedly_0#define ka0905_cpu$v_creg_fill_03 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fie0lds.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$r_creg_l_b\its.ka0905_cpu$v_creg_fill_03#define ka0905_cpu$v_creg_eff_0 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$r_creg_l_bit\s.ka0905_cpu$v_creg_eff_0#define ka0905_cpu$v_creg_dic_0 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$r_creg_l_bit\s.ka0905_cpu$v_creg_dic_0#define ka0905_cpu$v_creg_e4_0 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_cr0eg_fields_l_ol.ka0905_cpu$r_creg_l_bits\.ka0905_cpu$v_creg_e4_0#define ka0905_cpu$v_creg_amb_0 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$r_creg_l_bit\s.ka0905_cpu$v_creg_amb_0#define ka0905_cpu$v_creg_asd_0 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$r_creg_l_bit\s.ka0905_cpu$v_creg_asd_0#define ka0905_cpu$v_creg_cs_0 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_0cpu$r_creg_l_bits\.ka0905_cpu$v_creg_cs_0#define ka0905_cpu$v_creg_fill_04 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_l_ol.ka0905_cpu$r_creg_l_b\its.ka0905_cpu$v_creg_fill_04{#define ka0905_cpu$l_creg_h ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$l_creg_h#define ka0905_cpu$v_creg_rn_1 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_bits\.ka0905_cpu$v_creg_rn_1#define 0ka0905_cpu$v_creg_esi ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_bits.\ka0905_cpu$v_creg_esi#define ka0905_cpu$v_creg_eioi ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_bits\.ka0905_cpu$v_creg_eioi#define ka0905_cpu$v_creg_eaioi ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_bit\s.ka0905_cpu$v_creg_eaioi#define ka0905_cpu$v_creg_ebss_1 k0a0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_bi\ts.ka0905_cpu$v_creg_ebss_1#define ka0905_cpu$v_creg_fill_05 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_b\its.ka0905_cpu$v_creg_fill_05#define ka0905_cpu$v_creg_ee_dly_1 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_\bits.ka0905_cpu$v_creg_ee_dly_1#define ka0905_cpu$v_creg_fill_06 ka0905_c0pu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_b\its.ka0905_cpu$v_creg_fill_06#define ka0905_cpu$v_creg_eff_1 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_bit\s.ka0905_cpu$v_creg_eff_1#define ka0905_cpu$v_creg_dic_1 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_bit\s.ka0905_cpu$v_creg_dic_1#define ka0905_cpu$v_creg_e4_1 ka0905_cpu$r_creg_ol.ka09050_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_bits\.ka0905_cpu$v_creg_e4_1#define ka0905_cpu$v_creg_amb_1 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_bit\s.ka0905_cpu$v_creg_amb_1#define ka0905_cpu$v_creg_asd_1 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_bit\s.ka0905_cpu$v_creg_asd_1#define ka0905_cpu$v_creg_cs_1 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka00905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_bits\.ka0905_cpu$v_creg_cs_1#define ka0905_cpu$v_creg_fill_07 ka0905_cpu$r_creg_ol.ka0905_cpu$r_creg_fields.ka0905_cpu$r_creg_fields_h_ol.ka0905_cpu$r_creg_h_b\its.ka0905_cpu$v_creg_fill_07C#define ka0905_cpu$q_esreg ka0905_cpu$r_esreg_ol.ka0905_cpu$q_esreg#define ka0905_cpu$l_esreg_l ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$l_esreg_l#define ka0905_cpu$v_esreg_evbcef_0 ka0905_cpu$r_esreg_ol.ka00905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esr\%eg_l_bits.ka0905_cpu$v_esreg_evbcef_0#define ka0905_cpu$v_esreg_fill_01 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esre\#g_l_bits.ka0905_cpu$v_esreg_fill_01#define ka0905_cpu$v_esreg_evb_fef_0 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_es\'reg_l_bits.ka0905_cpu$v_esreg_evb_fef_0#define ka0905_cpu$v_esreg_dts_0 ka0905_cpu$0r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esreg_\l_bits.ka0905_cpu$v_esreg_dts_0#define ka0905_cpu$v_esreg_fill_02 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esre\#g_l_bits.ka0905_cpu$v_esreg_fill_02#define ka0905_cpu$v_esreg_ibpe_0 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esreg\!_l_bits.ka0905_cpu$v_esreg_ibpe_0#define ka0905_cpu$v_esreg_ibei_0 ka09050_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esreg\!_l_bits.ka0905_cpu$v_esreg_ibei_0#define ka0905_cpu$v_esreg_ibs_0 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esreg_\l_bits.ka0905_cpu$v_esreg_ibs_0#define ka0905_cpu$v_esreg_cbef_0 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esreg\!_l_bits.ka0905_cpu$v_esreg_cbef_0#define ka0905_cpu$v_esreg_cbs_0 ka09005_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esreg_\l_bits.ka0905_cpu$v_esreg_cbs_0#define ka0905_cpu$v_esreg_cbc_0 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esreg_\l_bits.ka0905_cpu$v_esreg_cbc_0#define ka0905_cpu$v_esreg_fill_03 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esre\#g_l_bits.ka0905_cpu$v_esreg_fill_03#define ka0905_cpu$v_esreg_evnr_0 ka00905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esreg\!_l_bits.ka0905_cpu$v_esreg_evnr_0#define ka0905_cpu$v_esreg_fill_04 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_l_ol.ka0905_cpu$r_esre\#g_l_bits.ka0905_cpu$v_esreg_fill_04#define ka0905_cpu$l_esreg_h ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$l_esreg_h#define ka0905_cpu$v_esreg_evbcef_1 ka0905_cpu$r_esreg_ol.ka0905_cpu$r0_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esr\%eg_h_bits.ka0905_cpu$v_esreg_evbcef_1#define ka0905_cpu$v_esreg_evbcei_1 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esr\%eg_h_bits.ka0905_cpu$v_esreg_evbcei_1#define ka0905_cpu$v_esreg_evbfef_1 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esr\%eg_h_bits.ka0905_cpu$v_esreg_evbfef_1#define ka0905_cpu$v_esreg_dts_1 ka0905_cpu$r_esreg_ol0.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esreg_\h_bits.ka0905_cpu$v_esreg_dts_1#define ka0905_cpu$v_esreg_fill_05 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esre\#g_h_bits.ka0905_cpu$v_esreg_fill_05#define ka0905_cpu$v_esreg_ibpe_1 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esreg\!_h_bits.ka0905_cpu$v_esreg_ibpe_1#define ka0905_cpu$v_esreg_ibei_1 ka0905_cpu$r_esr0eg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esreg\!_h_bits.ka0905_cpu$v_esreg_ibei_1#define ka0905_cpu$v_esreg_ibs_1 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esreg_\h_bits.ka0905_cpu$v_esreg_ibs_1#define ka0905_cpu$v_esreg_cbef_1 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esreg\!_h_bits.ka0905_cpu$v_esreg_cbef_1#define ka0905_cpu$v_esreg_fill_06 ka0905_cpu$r_0esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esre\#g_h_bits.ka0905_cpu$v_esreg_fill_06#define ka0905_cpu$v_esreg_cbs_1 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esreg_\h_bits.ka0905_cpu$v_esreg_cbs_1#define ka0905_cpu$v_esreg_cbc_1 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esreg_\h_bits.ka0905_cpu$v_esreg_cbc_1#define ka0905_cpu$v_esreg_fill_07 ka0905_cpu$0r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esre\#g_h_bits.ka0905_cpu$v_esreg_fill_07#define ka0905_cpu$v_esreg_evnr_1 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esreg\!_h_bits.ka0905_cpu$v_esreg_evnr_1#define ka0905_cpu$v_esreg_evsf_1 ka0905_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esreg\!_h_bits.ka0905_cpu$v_esreg_evsf_1#define ka0905_cpu$v_esreg_fill_08 ka09005_cpu$r_esreg_ol.ka0905_cpu$r_esreg_fields.ka0905_cpu$r_esreg_fields_h_ol.ka0905_cpu$r_esre\#g_h_bits.ka0905_cpu$v_esreg_fill_08C#define ka0905_cpu$q_evbcr ka0905_cpu$r_evbcr_ol.ka0905_cpu$q_evbcr#define ka0905_cpu$l_evbcr_l ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_l_ol.ka0905_cpu$l_evbcr_l#define ka0905_cpu$v_evbcr_eacbpc_0 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_l_ol.ka0905_cpu$r_evb\%cr_l_bits.ka0905_cpu$v_evbcr_eacbpc_00#define ka0905_cpu$v_evbcr_fill_01 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_l_ol.ka0905_cpu$r_evbc\#r_l_bits.ka0905_cpu$v_evbcr_fill_01#define ka0905_cpu$v_evbcr_ecei_0 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_l_ol.ka0905_cpu$r_evbcr\!_l_bits.ka0905_cpu$v_evbcr_ecei_0#define ka0905_cpu$v_evbcr_eec_0 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_l_ol.ka0905_cpu$r_evbcr_\l_bits.ka0905_cpu$v_evbcr_eec_00#define ka0905_cpu$v_evbcr_erec_0 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_l_ol.ka0905_cpu$r_evbcr\!_l_bits.ka0905_cpu$v_evbcr_erec_0#define ka0905_cpu$v_evbcr_fill_02 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_l_ol.ka0905_cpu$r_evbc\#r_l_bits.ka0905_cpu$v_evbcr_fill_02#define ka0905_cpu$v_evbcr_ffs ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_l_ol.ka0905_cpu$r_evbcr_l_\bits.ka0905_cpu$v_evbcr_ff0s#define ka0905_cpu$v_evbcr_rsfs ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_l_ol.ka0905_cpu$r_evbcr_l\_bits.ka0905_cpu$v_evbcr_rsfs#define ka0905_cpu$v_evbcr_fill_03 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_l_ol.ka0905_cpu$r_evbc\#r_l_bits.ka0905_cpu$v_evbcr_fill_03#define ka0905_cpu$l_evbcr_h ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_h_ol.ka0905_cpu$l_evbcr_h#define ka0905_cpu$v_evbcr_eacbpc_01 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_h_ol.ka0905_cpu$r_evb\%cr_h_bits.ka0905_cpu$v_evbcr_eacbpc_1#define ka0905_cpu$v_evbcr_fill_04 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_h_ol.ka0905_cpu$r_evbc\#r_h_bits.ka0905_cpu$v_evbcr_fill_04#define ka0905_cpu$v_evbcr_ecei_1 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_h_ol.ka0905_cpu$r_evbcr\!_h_bits.ka0905_cpu$v_evbcr_ecei_1#define ka0905_cpu$v_evb0cr_eec_1 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_h_ol.ka0905_cpu$r_evbcr_\h_bits.ka0905_cpu$v_evbcr_eec_1#define ka0905_cpu$v_evbcr_erec_1 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_h_ol.ka0905_cpu$r_evbcr\!_h_bits.ka0905_cpu$v_evbcr_erec_1#define ka0905_cpu$v_evbcr_deec_1 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_h_ol.ka0905_cpu$r_evbcr\!_h_bits.ka0905_cpu$v_evbcr_deec_1#define ka0905_cpu$v_e0vbcr_fill_05 ka0905_cpu$r_evbcr_ol.ka0905_cpu$r_evbcr_fields.ka0905_cpu$r_evbcr_fields_h_ol.ka0905_cpu$r_evbc\#r_h_bits.ka0905_cpu$v_evbcr_fill_05I#define ka0905_cpu$q_evbvear ka0905_cpu$r_evbvear_ol.ka0905_cpu$q_evbvear#define ka0905_cpu$l_evbvear_l ka0905_cpu$r_evbvear_ol.ka0905_cpu$r_evbvear_fields.ka0905_cpu$r_evbvear_fields_l_ol.ka0905_cpu$l_ev\bvear_l#define ka0905_cpu$v_evbvear_vea_0 ka0905_cpu$r_evbvear_ol.ka0905_cpu$r_evbvear_fields.ka0905_cpu$r_evbvear_fields_l_ol.ka0905_cpu$\+r_0evbvear_l_bits.ka0905_cpu$v_evbvear_vea_0#define ka0905_cpu$v_evbvear_fill_01 ka0905_cpu$r_evbvear_ol.ka0905_cpu$r_evbvear_fields.ka0905_cpu$r_evbvear_fields_l_ol.ka0905_cp\/u$r_evbvear_l_bits.ka0905_cpu$v_evbvear_fill_01#define ka0905_cpu$l_evbvear_h ka0905_cpu$r_evbvear_ol.ka0905_cpu$r_evbvear_fields.ka0905_cpu$r_evbvear_fields_h_ol.ka0905_cpu$l_ev\bvear_h#define ka0905_cpu$v_evbvear_vea_1 ka0905_cpu$r_evbvear_ol.ka0905_cpu$r_evbvear_fields.ka0905_cpu$r_evbvear_fields_h_ol.ka0905_cpu$\+0r_evbvear_h_bits.ka0905_cpu$v_evbvear_vea_1#define ka0905_cpu$v_evbvear_fill_02 ka0905_cpu$r_evbvear_ol.ka0905_cpu$r_evbvear_fields.ka0905_cpu$r_evbvear_fields_h_ol.ka0905_cp\/u$r_evbvear_h_bits.ka0905_cpu$v_evbvear_fill_02F#define ka0905_cpu$q_evbcer ka0905_cpu$r_evbcer_ol.ka0905_cpu$q_evbcer#define ka0905_cpu$l_evbcer_l ka0905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_l_ol.ka0905_cpu$l_evbcer\_l#define ka0905_cpu$v_evbcer_ce_0 ka0905_cpu$r_evbcer_ol.ka0905_cpu0$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_l_ol.ka0905_cpu$r_evb\#cer_l_bits.ka0905_cpu$v_evbcer_ce_0#define ka0905_cpu$v_evbcer_rd_0 ka0905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_l_ol.ka0905_cpu$r_evb\#cer_l_bits.ka0905_cpu$v_evbcer_rd_0#define ka0905_cpu$v_evbcer_mce_0 ka0905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_l_ol.ka0905_cpu$r_ev\%bcer_l_bits.ka0905_cpu$v_evbcer_mce_0#define ka0905_cpu$v_evbcer_fill_01 ka0905_cpu$r_evbce0r_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_l_ol.ka0905_cpu$r_\)evbcer_l_bits.ka0905_cpu$v_evbcer_fill_01#define ka0905_cpu$v_evbcer_es_0 ka0905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_l_ol.ka0905_cpu$r_evb\#cer_l_bits.ka0905_cpu$v_evbcer_es_0#define ka0905_cpu$v_evbcer_es_2 ka0905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_l_ol.ka0905_cpu$r_evb\#cer_l_bits.ka0905_cpu$v_evbcer_es_2#define ka0905_cpu$v_evbcer_fill_02 ka00905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_l_ol.ka0905_cpu$r_\)evbcer_l_bits.ka0905_cpu$v_evbcer_fill_02#define ka0905_cpu$l_evbcer_h ka0905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_h_ol.ka0905_cpu$l_evbcer\_h#define ka0905_cpu$v_evbcer_ce_1 ka0905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_h_ol.ka0905_cpu$r_evb\#cer_h_bits.ka0905_cpu$v_evbcer_ce_1#define ka0905_cpu$v_evbcer_rd_1 ka0905_cpu$r_evbcer_ol.0ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_h_ol.ka0905_cpu$r_evb\#cer_h_bits.ka0905_cpu$v_evbcer_rd_1#define ka0905_cpu$v_evbcer_mce_1 ka0905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_h_ol.ka0905_cpu$r_ev\%bcer_h_bits.ka0905_cpu$v_evbcer_mce_1#define ka0905_cpu$v_evbcer_fill_03 ka0905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_h_ol.ka0905_cpu$r_\)evbcer_h_bits.ka0905_cpu$v_evbcer_fill_03#define ka0905_cpu$v_evbcer_es_1 ka09005_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_h_ol.ka0905_cpu$r_evb\#cer_h_bits.ka0905_cpu$v_evbcer_es_1#define ka0905_cpu$v_evbcer_es_3 ka0905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_h_ol.ka0905_cpu$r_evb\#cer_h_bits.ka0905_cpu$v_evbcer_es_3#define ka0905_cpu$v_evbcer_fill_04 ka0905_cpu$r_evbcer_ol.ka0905_cpu$r_evbcer_fields.ka0905_cpu$r_evbcer_fields_h_ol.ka0905_cpu$r_\)evbcer_h_bits.ka0905_cpu$v_evbcer_fill_04I#define ka0905_cpu$q_e0vbcear ka0905_cpu$r_evbcear_ol.ka0905_cpu$q_evbcear#define ka0905_cpu$l_evbcear_l ka0905_cpu$r_evbcear_ol.ka0905_cpu$r_evbcear_fields.ka0905_cpu$r_evbcear_fields_l_ol.ka0905_cpu$l_ev\bcear_l#define ka0905_cpu$v_evbcear_cea_0 ka0905_cpu$r_evbcear_ol.ka0905_cpu$r_evbcear_fields.ka0905_cpu$r_evbcear_fields_l_ol.ka0905_cpu$\+r_evbcear_l_bits.ka0905_cpu$v_evbcear_cea_0#define ka0905_cpu$l_evbcear_h ka0905_cpu$r_evbcear_ol.ka0905_cpu$r_evbcear_fields.ka0905_cpu$r_evbcear_fields_h_ol.ka0905_cpu$l0_ev\bcear_h#define ka0905_cpu$v_evbcear_cea_1 ka0905_cpu$r_evbcear_ol.ka0905_cpu$r_evbcear_fields.ka0905_cpu$r_evbcear_fields_h_ol.ka0905_cpu$\+r_evbcear_h_bits.ka0905_cpu$v_evbcear_cea_1F#define ka0905_cpu$q_evbuer ka0905_cpu$r_evbuer_ol.ka0905_cpu$q_evbuer#define ka0905_cpu$l_evbuer_l ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_l_ol.ka0905_cpu$l_evbuer\_l#define ka0905_cpu$v_evbuer_ue_0 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbu0er_fields_l_ol.ka0905_cpu$r_evb\#uer_l_bits.ka0905_cpu$v_evbuer_ue_0#define ka0905_cpu$v_evbuer_rd_0 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_l_ol.ka0905_cpu$r_evb\#uer_l_bits.ka0905_cpu$v_evbuer_rd_0#define ka0905_cpu$v_evbuer_fill_01 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_l_ol.ka0905_cpu$r_\)evbuer_l_bits.ka0905_cpu$v_evbuer_fill_01#define ka0905_cpu$v_evbuer_peacb_0 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_field0s.ka0905_cpu$r_evbuer_fields_l_ol.ka0905_cpu$r_\)evbuer_l_bits.ka0905_cpu$v_evbuer_peacb_0#define ka0905_cpu$v_evbuer_peva_0 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_l_ol.ka0905_cpu$r_e\'vbuer_l_bits.ka0905_cpu$v_evbuer_peva_0#define ka0905_cpu$v_evbuer_fill_02 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_l_ol.ka0905_cpu$r_\)evbuer_l_bits.ka0905_cpu$v_evbuer_fill_02#define ka0905_cpu$v_evbuer_es_0 ka0905_cpu$r_evbuer_ol.ka00905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_l_ol.ka0905_cpu$r_evb\#uer_l_bits.ka0905_cpu$v_evbuer_es_0#define ka0905_cpu$v_evbuer_es_2 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_l_ol.ka0905_cpu$r_evb\#uer_l_bits.ka0905_cpu$v_evbuer_es_2#define ka0905_cpu$v_evbuer_fill_03 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_l_ol.ka0905_cpu$r_\)evbuer_l_bits.ka0905_cpu$v_evbuer_fill_03#define ka0905_cpu$v_evbuer_evbcb_0 ka09050_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_l_ol.ka0905_cpu$r_\)evbuer_l_bits.ka0905_cpu$v_evbuer_evbcb_0#define ka0905_cpu$l_evbuer_h ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_h_ol.ka0905_cpu$l_evbuer\_h#define ka0905_cpu$v_evbuer_ue_1 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_h_ol.ka0905_cpu$r_evb\#uer_h_bits.ka0905_cpu$v_evbuer_ue_1#define ka0905_cpu$v_evbuer_rd_1 ka0905_cpu$r_evbuer_ol.ka09005_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_h_ol.ka0905_cpu$r_evb\#uer_h_bits.ka0905_cpu$v_evbuer_rd_1#define ka0905_cpu$v_evbuer_fill_04 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_h_ol.ka0905_cpu$r_\)evbuer_h_bits.ka0905_cpu$v_evbuer_fill_04#define ka0905_cpu$v_evbuer_peacb_1 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_h_ol.ka0905_cpu$r_\)evbuer_h_bits.ka0905_cpu$v_evbuer_peacb_1#define ka0905_cpu$v_evbuer_peva_1 ka00905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_h_ol.ka0905_cpu$r_e\'vbuer_h_bits.ka0905_cpu$v_evbuer_peva_1#define ka0905_cpu$v_evbuer_fill_05 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_h_ol.ka0905_cpu$r_\)evbuer_h_bits.ka0905_cpu$v_evbuer_fill_05#define ka0905_cpu$v_evbuer_es_1 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_h_ol.ka0905_cpu$r_evb\#uer_h_bits.ka0905_cpu$v_evbuer_es_1#define ka0905_cpu0$v_evbuer_es_3 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_h_ol.ka0905_cpu$r_evb\#uer_h_bits.ka0905_cpu$v_evbuer_es_3#define ka0905_cpu$v_evbuer_fill_06 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_h_ol.ka0905_cpu$r_\)evbuer_h_bits.ka0905_cpu$v_evbuer_fill_06#define ka0905_cpu$v_evbuer_evbcb_1 ka0905_cpu$r_evbuer_ol.ka0905_cpu$r_evbuer_fields.ka0905_cpu$r_evbuer_fields_h_ol.ka0905_cpu$r_\)evbuer_h_bits.ka0905_cpu$v_evbuer_evbcb_01I#define ka0905_cpu$q_evbuear ka0905_cpu$r_evbuear_ol.ka0905_cpu$q_evbuear#define ka0905_cpu$l_evbuear_l ka0905_cpu$r_evbuear_ol.ka0905_cpu$r_evbuear_fields.ka0905_cpu$r_evbuear_fields_l_ol.ka0905_cpu$l_ev\buear_l#define ka0905_cpu$v_evbuear_uea_0 ka0905_cpu$r_evbuear_ol.ka0905_cpu$r_evbuear_fields.ka0905_cpu$r_evbuear_fields_l_ol.ka0905_cpu$\+r_evbuear_l_bits.ka0905_cpu$v_evbuear_uea_0#define ka0905_cpu$l_evbuear_h ka0905_cpu$r_evbuear_ol.ka0905_cpu$r_evbuear_fields.ka0905_cpu$r_evbuea0r_fields_h_ol.ka0905_cpu$l_ev\buear_h#define ka0905_cpu$v_evbuear_uea_1 ka0905_cpu$r_evbuear_ol.ka0905_cpu$r_evbuear_fields.ka0905_cpu$r_evbuear_fields_h_ol.ka0905_cpu$\+r_evbuear_h_bits.ka0905_cpu$v_evbuear_uea_1I#define ka0905_cpu$q_evbresv ka0905_cpu$r_evbresv_ol.ka0905_cpu$q_evbresv#define ka0905_cpu$l_evbresv_l ka0905_cpu$r_evbresv_ol.ka0905_cpu$r_evbresv_fields.ka0905_cpu$r_evbresv_fields_l_ol.ka0905_cpu$l_ev\bresv_l#define ka0905_cpu$v_evbresv_fill_01 ka0905_cpu$r_evbresv_ol.ka00905_cpu$r_evbresv_fields.ka0905_cpu$r_evbresv_fields_l_ol.ka0905_cp\/u$r_evbresv_l_bits.ka0905_cpu$v_evbresv_fill_01#define ka0905_cpu$l_evbresv_h ka0905_cpu$r_evbresv_ol.ka0905_cpu$r_evbresv_fields.ka0905_cpu$r_evbresv_fields_h_ol.ka0905_cpu$l_ev\bresv_h#define ka0905_cpu$v_evbresv_fill_02 ka0905_cpu$r_evbresv_ol.ka0905_cpu$r_evbresv_fields.ka0905_cpu$r_evbresv_fields_h_ol.ka0905_cp\/u$r_evbresv_h_bits.ka0905_cpu$v_evbresv_fill_02C#define ka0905_cpu$q_dtctr ka0905_cpu$r_dtctr_ol.ka0905_cp0u$q_dtctr#define ka0905_cpu$l_dtctr_l ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_l_ol.ka0905_cpu$l_dtctr_l#define ka0905_cpu$v_dtctr_dte_0 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_l_ol.ka0905_cpu$r_dtctr_\l_bits.ka0905_cpu$v_dtctr_dte_0#define ka0905_cpu$v_dtctr_fill_01 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_l_ol.ka0905_cpu$r_dtct\#r_l_bits.ka0905_cpu$v_dtctr_fill_01#define ka0905_cpu$v_dtc0tr_ecpc_0 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_l_ol.ka0905_cpu$r_dtctr\!_l_bits.ka0905_cpu$v_dtctr_ecpc_0#define ka0905_cpu$v_dtctr_fbcp ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_l_ol.ka0905_cpu$r_dtctr_l\_bits.ka0905_cpu$v_dtctr_fbcp#define ka0905_cpu$v_dtctr_fill_02 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_l_ol.ka0905_cpu$r_dtct\#r_l_bits.ka0905_cpu$v_dtctr_fill_02#define ka0905_cpu$v_d0tctr_etpc_0 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_l_ol.ka0905_cpu$r_dtctr\!_l_bits.ka0905_cpu$v_dtctr_etpc_0#define ka0905_cpu$v_dtctr_fbtp ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_l_ol.ka0905_cpu$r_dtctr_l\_bits.ka0905_cpu$v_dtctr_fbtp#define ka0905_cpu$v_dtctr_fill_03 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_l_ol.ka0905_cpu$r_dtct\#r_l_bits.ka0905_cpu$v_dtctr_fill_03#define ka0905_cpu$v0_dtctr_dtdm_0 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_l_ol.ka0905_cpu$r_dtctr\!_l_bits.ka0905_cpu$v_dtctr_dtdm_0#define ka0905_cpu$v_dtctr_fill_04 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_l_ol.ka0905_cpu$r_dtct\#r_l_bits.ka0905_cpu$v_dtctr_fill_04#define ka0905_cpu$l_dtctr_h ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_h_ol.ka0905_cpu$l_dtctr_h#define ka0905_cpu$v_dtctr_dte_1 ka0905_cpu$r_dtctr_ol0.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_h_ol.ka0905_cpu$r_dtctr_\h_bits.ka0905_cpu$v_dtctr_dte_1#define ka0905_cpu$v_dtctr_fill_05 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_h_ol.ka0905_cpu$r_dtct\#r_h_bits.ka0905_cpu$v_dtctr_fill_05#define ka0905_cpu$v_dtctr_ecpc_1 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_h_ol.ka0905_cpu$r_dtctr\!_h_bits.ka0905_cpu$v_dtctr_ecpc_1#define ka0905_cpu$v_dtctr_fill_06 ka0905_cpu$r_dt0ctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_h_ol.ka0905_cpu$r_dtct\#r_h_bits.ka0905_cpu$v_dtctr_fill_06#define ka0905_cpu$v_dtctr_etpc_1 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_h_ol.ka0905_cpu$r_dtctr\!_h_bits.ka0905_cpu$v_dtctr_etpc_1#define ka0905_cpu$v_dtctr_fill_07 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_h_ol.ka0905_cpu$r_dtct\#r_h_bits.ka0905_cpu$v_dtctr_fill_07#define ka0905_cpu$v_dtctr_dtdm_1 ka0905_c0pu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_h_ol.ka0905_cpu$r_dtctr\!_h_bits.ka0905_cpu$v_dtctr_dtdm_1#define ka0905_cpu$v_dtctr_fill_08 ka0905_cpu$r_dtctr_ol.ka0905_cpu$r_dtctr_fields.ka0905_cpu$r_dtctr_fields_h_ol.ka0905_cpu$r_dtct\#r_h_bits.ka0905_cpu$v_dtctr_fill_08@#define ka0905_cpu$q_dter ka0905_cpu$r_dter_ol.ka0905_cpu$q_dter{#define ka0905_cpu$l_dter_l ka0905_cpu$r_dter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r_dter_fields_l_ol.ka0905_cpu$l_dter_l#define ka09050_cpu$v_dter_fill_01 ka0905_cpu$r_dter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r_dter_fields_l_ol.ka0905_cpu$r_dter_l_b\its.ka0905_cpu$v_dter_fill_01#define ka0905_cpu$v_dter_dtea ka0905_cpu$r_dter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r_dter_fields_l_ol.ka0905_cpu$r_dter_l_bits\.ka0905_cpu$v_dter_dtea#define ka0905_cpu$v_dter_fill_02 ka0905_cpu$r_dter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r_dter_fields_l_ol.ka0905_cpu$r_dter_l_b\its.ka0905_cpu$v_dter_fill_02#define ka0905_cpu$v_dter_tc0pe_0 ka0905_cpu$r_dter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r_dter_fields_l_ol.ka0905_cpu$r_dter_l_bi\ts.ka0905_cpu$v_dter_tcpe_0#define ka0905_cpu$v_dter_fill_03 ka0905_cpu$r_dter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r_dter_fields_l_ol.ka0905_cpu$r_dter_l_b\its.ka0905_cpu$v_dter_fill_03#define ka0905_cpu$v_dter_tpe_0 ka0905_cpu$r_dter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r_dter_fields_l_ol.ka0905_cpu$r_dter_l_bit\s.ka0905_cpu$v_dter_tpe_0{#define ka0905_cpu$l_dter_h ka0905_cpu$r_d0ter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r_dter_fields_h_ol.ka0905_cpu$l_dter_h#define ka0905_cpu$v_dter_fill_04 ka0905_cpu$r_dter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r_dter_fields_h_ol.ka0905_cpu$r_dter_h_b\its.ka0905_cpu$v_dter_fill_04#define ka0905_cpu$v_dter_tcpe_1 ka0905_cpu$r_dter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r_dter_fields_h_ol.ka0905_cpu$r_dter_h_bi\ts.ka0905_cpu$v_dter_tcpe_1#define ka0905_cpu$v_dter_fill_05 ka0905_cpu$r_dter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r0_dter_fields_h_ol.ka0905_cpu$r_dter_h_b\its.ka0905_cpu$v_dter_fill_05#define ka0905_cpu$v_dter_tpe_1 ka0905_cpu$r_dter_ol.ka0905_cpu$r_dter_fields.ka0905_cpu$r_dter_fields_h_ol.ka0905_cpu$r_dter_h_bit\s.ka0905_cpu$v_dter_tpe_1C#define ka0905_cpu$q_dttcr ka0905_cpu$r_dttcr_ol.ka0905_cpu$q_dttcr#define ka0905_cpu$l_dttcr_l ka0905_cpu$r_dttcr_ol.ka0905_cpu$r_dttcr_fields.ka0905_cpu$r_dttcr_fields_l_ol.ka0905_cpu$l_dttcr_l#define ka0905_cpu$v_dttcr_tcf ka0905_cpu$r_dttcr_ol.ka0905_cpu$r_dttc0r_fields.ka0905_cpu$r_dttcr_fields_l_ol.ka0905_cpu$r_dttcr_l_\bits.ka0905_cpu$v_dttcr_tcf#define ka0905_cpu$v_dttcr_tcpf ka0905_cpu$r_dttcr_ol.ka0905_cpu$r_dttcr_fields.ka0905_cpu$r_dttcr_fields_l_ol.ka0905_cpu$r_dttcr_l\_bits.ka0905_cpu$v_dttcr_tcpf#define ka0905_cpu$v_dttcr_fill_01 ka0905_cpu$r_dttcr_ol.ka0905_cpu$r_dttcr_fields.ka0905_cpu$r_dttcr_fields_l_ol.ka0905_cpu$r_dttc\#r_l_bits.ka0905_cpu$v_dttcr_fill_01#define ka0905_cpu$v_dttcr_af ka0905_cpu$r_dttcr_ol.ka0905_cpu$r_dttcr_fie0lds.ka0905_cpu$r_dttcr_fields_l_ol.ka0905_cpu$r_dttcr_l_b\its.ka0905_cpu$v_dttcr_af#define ka0905_cpu$v_dttcr_mtaf ka0905_cpu$r_dttcr_ol.ka0905_cpu$r_dttcr_fields.ka0905_cpu$r_dttcr_fields_l_ol.ka0905_cpu$r_dttcr_l\_bits.ka0905_cpu$v_dttcr_mtaf#define ka0905_cpu$v_dttcr_ptf ka0905_cpu$r_dttcr_ol.ka0905_cpu$r_dttcr_fields.ka0905_cpu$r_dttcr_fields_l_ol.ka0905_cpu$r_dttcr_l_\bits.ka0905_cpu$v_dttcr_ptf#define ka0905_cpu$v_dttcr_tpf ka0905_cpu$r_dttcr_ol.ka0905_cpu$r_dttcr_fields.ka0905_cp0u$r_dttcr_fields_l_ol.ka0905_cpu$r_dttcr_l_\bits.ka0905_cpu$v_dttcr_tpf#define ka0905_cpu$l_dttcr_h ka0905_cpu$r_dttcr_ol.ka0905_cpu$r_dttcr_fields.ka0905_cpu$r_dttcr_fields_h_ol.ka0905_cpu$l_dttcr_h#define ka0905_cpu$v_dttcr_fill_02 ka0905_cpu$r_dttcr_ol.ka0905_cpu$r_dttcr_fields.ka0905_cpu$r_dttcr_fields_h_ol.ka0905_cpu$r_dttc\#r_h_bits.ka0905_cpu$v_dttcr_fill_02@#define ka0905_cpu$q_dttr ka0905_cpu$r_dttr_ol.ka0905_cpu$q_dttr{#define ka0905_cpu$l_dttr_l ka0905_cpu$r_dttr_ol.ka0905_cpu$r_0dttr_fields.ka0905_cpu$r_dttr_fields_l_ol.ka0905_cpu$l_dttr_l#define ka0905_cpu$v_dttr_tc_0 ka0905_cpu$r_dttr_ol.ka0905_cpu$r_dttr_fields.ka0905_cpu$r_dttr_fields_l_ol.ka0905_cpu$r_dttr_l_bits\.ka0905_cpu$v_dttr_tc_0#define ka0905_cpu$v_dttr_tcp_0 ka0905_cpu$r_dttr_ol.ka0905_cpu$r_dttr_fields.ka0905_cpu$r_dttr_fields_l_ol.ka0905_cpu$r_dttr_l_bit\s.ka0905_cpu$v_dttr_tcp_0#define ka0905_cpu$v_dttr_fill_01 ka0905_cpu$r_dttr_ol.ka0905_cpu$r_dttr_fields.ka0905_cpu$r_dttr_fields_l_ol.ka0905_cpu0$r_dttr_l_b\its.ka0905_cpu$v_dttr_fill_01#define ka0905_cpu$v_dttr_td_0 ka0905_cpu$r_dttr_ol.ka0905_cpu$r_dttr_fields.ka0905_cpu$r_dttr_fields_l_ol.ka0905_cpu$r_dttr_l_bits\.ka0905_cpu$v_dttr_td_0#define ka0905_cpu$v_dttr_tp_0 ka0905_cpu$r_dttr_ol.ka0905_cpu$r_dttr_fields.ka0905_cpu$r_dttr_fields_l_ol.ka0905_cpu$r_dttr_l_bits\.ka0905_cpu$v_dttr_tp_0{#define ka0905_cpu$l_dttr_h ka0905_cpu$r_dttr_ol.ka0905_cpu$r_dttr_fields.ka0905_cpu$r_dttr_fields_h_ol.ka0905_cpu$l_dttr_h#define ka09050_cpu$v_dttr_tc_1 ka0905_cpu$r_dttr_ol.ka0905_cpu$r_dttr_fields.ka0905_cpu$r_dttr_fields_h_ol.ka0905_cpu$r_dttr_h_bits\.ka0905_cpu$v_dttr_tc_1#define ka0905_cpu$v_dttr_tcp_1 ka0905_cpu$r_dttr_ol.ka0905_cpu$r_dttr_fields.ka0905_cpu$r_dttr_fields_h_ol.ka0905_cpu$r_dttr_h_bit\s.ka0905_cpu$v_dttr_tcp_1#define ka0905_cpu$v_dttr_fill_02 ka0905_cpu$r_dttr_ol.ka0905_cpu$r_dttr_fields.ka0905_cpu$r_dttr_fields_h_ol.ka0905_cpu$r_dttr_h_b\its.ka0905_cpu$v_dttr_fill_02#define ka0905_cpu$v_dttr_td_1 k0a0905_cpu$r_dttr_ol.ka0905_cpu$r_dttr_fields.ka0905_cpu$r_dttr_fields_h_ol.ka0905_cpu$r_dttr_h_bits\.ka0905_cpu$v_dttr_td_1#define ka0905_cpu$v_dttr_tp_1 ka0905_cpu$r_dttr_ol.ka0905_cpu$r_dttr_fields.ka0905_cpu$r_dttr_fields_h_ol.ka0905_cpu$r_dttr_h_bits\.ka0905_cpu$v_dttr_tp_1F#define ka0905_cpu$q_dtresv ka0905_cpu$r_dtresv_ol.ka0905_cpu$q_dtresv#define ka0905_cpu$l_dtresv_l ka0905_cpu$r_dtresv_ol.ka0905_cpu$r_dtresv_fields.ka0905_cpu$r_dtresv_fields_l_ol.ka0905_cpu$l_dtresv\_l#define 0ka0905_cpu$v_dtresv_fill_01 ka0905_cpu$r_dtresv_ol.ka0905_cpu$r_dtresv_fields.ka0905_cpu$r_dtresv_fields_l_ol.ka0905_cpu$r_\)dtresv_l_bits.ka0905_cpu$v_dtresv_fill_01#define ka0905_cpu$l_dtresv_h ka0905_cpu$r_dtresv_ol.ka0905_cpu$r_dtresv_fields.ka0905_cpu$r_dtresv_fields_h_ol.ka0905_cpu$l_dtresv\_h#define ka0905_cpu$v_dtresv_fill_02 ka0905_cpu$r_dtresv_ol.ka0905_cpu$r_dtresv_fields.ka0905_cpu$r_dtresv_fields_h_ol.ka0905_cpu$r_\)dtresv_h_bits.ka0905_cpu$v_dtresv_fill_02C#define ka0905_cpu$q0_ibcsr ka0905_cpu$r_ibcsr_ol.ka0905_cpu$q_ibcsr#define ka0905_cpu$l_ibcsr_l ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_l_ol.ka0905_cpu$l_ibcsr_l#define ka0905_cpu$v_ibcsr_fill_01 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_l_ol.ka0905_cpu$r_ibcs\#r_l_bits.ka0905_cpu$v_ibcsr_fill_01#define ka0905_cpu$v_ibcsr_ibpe_0 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_l_ol.ka0905_cpu$r_ibcsr\!_l_bits.ka0905_cpu$v0_ibcsr_ibpe_0#define ka0905_cpu$v_ibcsr_scdipe_0 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_l_ol.ka0905_cpu$r_ibc\%sr_l_bits.ka0905_cpu$v_ibcsr_scdipe_0#define ka0905_cpu$v_ibcsr_ccdipe_0 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_l_ol.ka0905_cpu$r_ibc\%sr_l_bits.ka0905_cpu$v_ibcsr_ccdipe_0#define ka0905_cpu$v_ibcsr_fill_02 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_l_ol.ka0905_cpu$r_ibcs\#r_l_bits0.ka0905_cpu$v_ibcsr_fill_02#define ka0905_cpu$v_ibcsr_eipc_0 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_l_ol.ka0905_cpu$r_ibcsr\!_l_bits.ka0905_cpu$v_ibcsr_eipc_0#define ka0905_cpu$v_ibcsr_dbip_0 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_l_ol.ka0905_cpu$r_ibcsr\!_l_bits.ka0905_cpu$v_ibcsr_dbip_0#define ka0905_cpu$v_ibcsr_fill_03 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_l_ol.ka0905_cpu$r_ibcs\#r_0l_bits.ka0905_cpu$v_ibcsr_fill_03#define ka0905_cpu$l_ibcsr_h ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_h_ol.ka0905_cpu$l_ibcsr_h#define ka0905_cpu$v_ibcsr_fill_04 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_h_ol.ka0905_cpu$r_ibcs\#r_h_bits.ka0905_cpu$v_ibcsr_fill_04#define ka0905_cpu$v_ibcsr_ibpe_1 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_h_ol.ka0905_cpu$r_ibcsr\!_h_bits.ka0905_cpu$v_ibcsr_ibpe_10#define ka0905_cpu$v_ibcsr_scdipe_1 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_h_ol.ka0905_cpu$r_ibc\%sr_h_bits.ka0905_cpu$v_ibcsr_scdipe_1#define ka0905_cpu$v_ibcsr_ccdipe_1 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_h_ol.ka0905_cpu$r_ibc\%sr_h_bits.ka0905_cpu$v_ibcsr_ccdipe_1#define ka0905_cpu$v_ibcsr_fill_05 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_h_ol.ka0905_cpu$r_ibcs\#r_h_bits.ka0905_cpu$v_0ibcsr_fill_05#define ka0905_cpu$v_ibcsr_eipc_1 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_h_ol.ka0905_cpu$r_ibcsr\!_h_bits.ka0905_cpu$v_ibcsr_eipc_1#define ka0905_cpu$v_ibcsr_fill_06 ka0905_cpu$r_ibcsr_ol.ka0905_cpu$r_ibcsr_fields.ka0905_cpu$r_ibcsr_fields_h_ol.ka0905_cpu$r_ibcs\#r_h_bits.ka0905_cpu$v_ibcsr_fill_06C#define ka0905_cpu$q_ibear ka0905_cpu$r_ibear_ol.ka0905_cpu$q_ibear#define ka0905_cpu$l_ibear_l ka0905_cpu$r_ibear_ol.ka0905_cpu$r_ibear_fields.k0a0905_cpu$r_ibear_fields_l_ol.ka0905_cpu$l_ibear_l#define ka0905_cpu$v_ibear_cbcac_0 ka0905_cpu$r_ibear_ol.ka0905_cpu$r_ibear_fields.ka0905_cpu$r_ibear_fields_l_ol.ka0905_cpu$r_ibea\#r_l_bits.ka0905_cpu$v_ibear_cbcac_0#define ka0905_cpu$l_ibear_h ka0905_cpu$r_ibear_ol.ka0905_cpu$r_ibear_fields.ka0905_cpu$r_ibear_fields_h_ol.ka0905_cpu$l_ibear_h#define ka0905_cpu$v_ibear_cbcac_1 ka0905_cpu$r_ibear_ol.ka0905_cpu$r_ibear_fields.ka0905_cpu$r_ibear_fields_h_ol.ka0905_cpu$r_ibea\#r_h_bits.ka0905_cp0u$v_ibear_cbcac_1=#define ka0905_cpu$q_acr ka0905_cpu$r_acr_ol.ka0905_cpu$q_acrv#define ka0905_cpu$l_acr_l ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_l_ol.ka0905_cpu$l_acr_l#define ka0905_cpu$v_acr_cbe_0 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_l_ol.ka0905_cpu$r_acr_l_bits.ka0\905_cpu$v_acr_cbe_0#define ka0905_cpu$v_acr_fill_01 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_l_ol.ka0905_cpu$r_acr_l_bits.k\a0905_cpu$v_0acr_fill_01#define ka0905_cpu$v_acr_bme_0 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_l_ol.ka0905_cpu$r_acr_l_bits.ka0\905_cpu$v_acr_bme_0#define ka0905_cpu$v_acr_dme_0 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_l_ol.ka0905_cpu$r_acr_l_bits.ka0\905_cpu$v_acr_dme_0#define ka0905_cpu$v_acr_fill_02 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_l_ol.ka0905_cpu$r_acr_l_bits.k\a0905_cpu$v_acr_fill_02#define ka0905_cpu$v0_acr_pme_0 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_l_ol.ka0905_cpu$r_acr_l_bits.ka0\905_cpu$v_acr_pme_0#define ka0905_cpu$v_acr_bcre_0 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_l_ol.ka0905_cpu$r_acr_l_bits.ka\0905_cpu$v_acr_bcre_0#define ka0905_cpu$v_acr_fill_03 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_l_ol.ka0905_cpu$r_acr_l_bits.k\a0905_cpu$v_acr_fill_03#define ka0905_cpu$v_acr_dcbr_0 ka0905_cpu$r_acr_ol.0ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_l_ol.ka0905_cpu$r_acr_l_bits.ka\0905_cpu$v_acr_dcbr_0#define ka0905_cpu$v_acr_fill_04 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_l_ol.ka0905_cpu$r_acr_l_bits.k\a0905_cpu$v_acr_fill_04v#define ka0905_cpu$l_acr_h ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_h_ol.ka0905_cpu$l_acr_h#define ka0905_cpu$v_acr_cbe_1 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_h_ol.ka0905_cpu$r_acr0_h_bits.ka0\905_cpu$v_acr_cbe_1#define ka0905_cpu$v_acr_fill_05 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_h_ol.ka0905_cpu$r_acr_h_bits.k\a0905_cpu$v_acr_fill_05#define ka0905_cpu$v_acr_bme_1 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_h_ol.ka0905_cpu$r_acr_h_bits.ka0\905_cpu$v_acr_bme_1#define ka0905_cpu$v_acr_dme_1 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_h_ol.ka0905_cpu$r_acr_h_bits.ka0\905_cpu$v_acr_dme_10#define ka0905_cpu$v_acr_fill_06 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_h_ol.ka0905_cpu$r_acr_h_bits.k\a0905_cpu$v_acr_fill_06#define ka0905_cpu$v_acr_pme_1 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_h_ol.ka0905_cpu$r_acr_h_bits.ka0\905_cpu$v_acr_pme_1#define ka0905_cpu$v_acr_bcre_1 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_h_ol.ka0905_cpu$r_acr_h_bits.ka\0905_cpu$v_acr_bcre_1#define ka0905_cpu$v_acr_fill_007 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_h_ol.ka0905_cpu$r_acr_h_bits.k\a0905_cpu$v_acr_fill_07#define ka0905_cpu$v_acr_dcbr_1 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_h_ol.ka0905_cpu$r_acr_h_bits.ka\0905_cpu$v_acr_dcbr_1#define ka0905_cpu$v_acr_fill_08 ka0905_cpu$r_acr_ol.ka0905_cpu$r_acr_fields.ka0905_cpu$r_acr_fields_h_ol.ka0905_cpu$r_acr_h_bits.k\a0905_cpu$v_acr_fill_08@#define ka0905_cpu$q_cbcr ka0905_cpu$r_cbcr_ol.ka0905_cpu$0q_cbcr{#define ka0905_cpu$l_cbcr_l ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_l_ol.ka0905_cpu$l_cbcr_l#define ka0905_cpu$v_cbcr_epc_0 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_l_ol.ka0905_cpu$r_cbcr_l_bit\s.ka0905_cpu$v_cbcr_epc_0#define ka0905_cpu$v_cbcr_dwp_0 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_l_ol.ka0905_cpu$r_cbcr_l_bit\s.ka0905_cpu$v_cbcr_dwp_0#define ka0905_cpu$v_cbcr_cawp_0 ka0905_cpu$r_cb0cr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_l_ol.ka0905_cpu$r_cbcr_l_bi\ts.ka0905_cpu$v_cbcr_cawp_0#define ka0905_cpu$v_cbcr_fill_01 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_l_ol.ka0905_cpu$r_cbcr_l_b\its.ka0905_cpu$v_cbcr_fill_01#define ka0905_cpu$v_cbcr_fs ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_l_ol.ka0905_cpu$r_cbcr_l_bits.k\a0905_cpu$v_cbcr_fs#define ka0905_cpu$v_cbcr_fill_02 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_0cbcr_fields.ka0905_cpu$r_cbcr_fields_l_ol.ka0905_cpu$r_cbcr_l_b\its.ka0905_cpu$v_cbcr_fill_02#define ka0905_cpu$v_cbcr_ecbei_0 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_l_ol.ka0905_cpu$r_cbcr_l_b\its.ka0905_cpu$v_cbcr_ecbei_0#define ka0905_cpu$v_cbcr_fill_03 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_l_ol.ka0905_cpu$r_cbcr_l_b\its.ka0905_cpu$v_cbcr_fill_03#define ka0905_cpu$v_cbcr_dsrc ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields0.ka0905_cpu$r_cbcr_fields_l_ol.ka0905_cpu$r_cbcr_l_bits\.ka0905_cpu$v_cbcr_dsrc#define ka0905_cpu$v_cbcr_fill_04 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_l_ol.ka0905_cpu$r_cbcr_l_b\its.ka0905_cpu$v_cbcr_fill_04{#define ka0905_cpu$l_cbcr_h ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_h_ol.ka0905_cpu$l_cbcr_h#define ka0905_cpu$v_cbcr_epc_1 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_h_ol.ka0905_cpu$r_cbcr_h_bi0t\s.ka0905_cpu$v_cbcr_epc_1#define ka0905_cpu$v_cbcr_dwp_1 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_h_ol.ka0905_cpu$r_cbcr_h_bit\s.ka0905_cpu$v_cbcr_dwp_1#define ka0905_cpu$v_cbcr_cawp_1 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_h_ol.ka0905_cpu$r_cbcr_h_bi\ts.ka0905_cpu$v_cbcr_cawp_1#define ka0905_cpu$v_cbcr_fill_05 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_h_ol.ka0905_cpu$r_cbcr_h_b\its.ka0905_cpu0$v_cbcr_fill_05#define ka0905_cpu$v_cbcr_cid ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_h_ol.ka0905_cpu$r_cbcr_h_bits.\ka0905_cpu$v_cbcr_cid#define ka0905_cpu$v_cbcr_fill_06 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_h_ol.ka0905_cpu$r_cbcr_h_b\its.ka0905_cpu$v_cbcr_fill_06#define ka0905_cpu$v_cbcr_ecbei_1 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_h_ol.ka0905_cpu$r_cbcr_h_b\its.ka0905_cpu$v_cbcr_ecbei_10#define ka0905_cpu$v_cbcr_fill_07 ka0905_cpu$r_cbcr_ol.ka0905_cpu$r_cbcr_fields.ka0905_cpu$r_cbcr_fields_h_ol.ka0905_cpu$r_cbcr_h_b\its.ka0905_cpu$v_cbcr_fill_07@#define ka0905_cpu$q_cber ka0905_cpu$r_cber_ol.ka0905_cpu$q_cber{#define ka0905_cpu$l_cber_l ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$l_cber_l#define ka0905_cpu$v_cber_ure_0 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_bit\s.ka0905_cpu0$v_cber_ure_0#define ka0905_cpu$v_cber_fill_01 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_fill_01#define ka0905_cpu$v_cber_callpe_0 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_\bits.ka0905_cpu$v_cber_callpe_0#define ka0905_cpu$v_cber_cahlpe_0 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_\bits.ka0905_cpu$v_cber0_cahlpe_0#define ka0905_cpu$v_cber_fill_02 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_fill_02#define ka0905_cpu$v_cber_pelw0wd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_pelw0wd#define ka0905_cpu$v_cber_pelw1wd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_pelw1w0d#define ka0905_cpu$v_cber_pelw4wd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_pelw4wd#define ka0905_cpu$v_cber_pelw5wd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_pelw5wd#define ka0905_cpu$v_cber_fill_03 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_fill_03#def0ine ka0905_cpu$v_cber_pelw0rd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_pelw0rd#define ka0905_cpu$v_cber_pelw1rd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_pelw1rd#define ka0905_cpu$v_cber_pelw4rd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_pelw4rd#define ka09005_cpu$v_cber_pelw5rd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_pelw5rd#define ka0905_cpu$v_cber_usr ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_bits.\ka0905_cpu$v_cber_usr#define ka0905_cpu$v_cber_fill_04 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_fill_04#define ka0905_cpu$v_cber_ca0na ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_bits\.ka0905_cpu$v_cber_cana#define ka0905_cpu$v_cber_fill_05 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_fill_05#define ka0905_cpu$v_cber_d0na ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_bits\.ka0905_cpu$v_cber_d0na#define ka0905_cpu$v_cber_d1na ka0905_cpu$r_cber0_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_bits\.ka0905_cpu$v_cber_d1na#define ka0905_cpu$v_cber_fill_06 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_l_ol.ka0905_cpu$r_cber_l_b\its.ka0905_cpu$v_cber_fill_06{#define ka0905_cpu$l_cber_h ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$l_cber_h#define ka0905_cpu$v_cber_ucr_1 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields0_h_ol.ka0905_cpu$r_cber_h_bit\s.ka0905_cpu$v_cber_ucr_1#define ka0905_cpu$v_cber_fill_07 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cber_h_b\its.ka0905_cpu$v_cber_fill_07#define ka0905_cpu$v_cber_callpe_1 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cber_h_\bits.ka0905_cpu$v_cber_callpe_1#define ka0905_cpu$v_cber_cahlpe_1 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.k0a0905_cpu$r_cber_h_\bits.ka0905_cpu$v_cber_cahlpe_1#define ka0905_cpu$v_cber_fill_08 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cber_h_b\its.ka0905_cpu$v_cber_fill_08#define ka0905_cpu$v_cber_pelw2wd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cber_h_b\its.ka0905_cpu$v_cber_pelw2wd#define ka0905_cpu$v_cber_pelw3wd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_c0pu$r_cber_h_b\its.ka0905_cpu$v_cber_pelw3wd#define ka0905_cpu$v_cber_pelw6wd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cber_h_b\its.ka0905_cpu$v_cber_pelw6wd#define ka0905_cpu$v_cber_pelw7wd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cber_h_b\its.ka0905_cpu$v_cber_pelw7wd#define ka0905_cpu$v_cber_fill_09 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cbe0r_h_b\its.ka0905_cpu$v_cber_fill_09#define ka0905_cpu$v_cber_pelw2rd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cber_h_b\its.ka0905_cpu$v_cber_pelw2rd#define ka0905_cpu$v_cber_pelw3rd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cber_h_b\its.ka0905_cpu$v_cber_pelw3rd#define ka0905_cpu$v_cber_pelw6rd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cber_h_b\0its.ka0905_cpu$v_cber_pelw6rd#define ka0905_cpu$v_cber_pelw7rd ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cber_h_b\its.ka0905_cpu$v_cber_pelw7rd#define ka0905_cpu$v_cber_fill_10 ka0905_cpu$r_cber_ol.ka0905_cpu$r_cber_fields.ka0905_cpu$r_cber_fields_h_ol.ka0905_cpu$r_cber_h_b\its.ka0905_cpu$v_cber_fill_10F#define ka0905_cpu$q_cbealr ka0905_cpu$r_cbealr_ol.ka0905_cpu$q_cbealr#define ka0905_cpu$l_cbealr_l ka0905_cpu$r_cbealr_ol.ka0905_cpu$r_cbea0lr_fields.ka0905_cpu$r_cbealr_fields_l_ol.ka0905_cpu$l_cbealr\_l#define ka0905_cpu$v_cbealr_cbla_0 ka0905_cpu$r_cbealr_ol.ka0905_cpu$r_cbealr_fields.ka0905_cpu$r_cbealr_fields_l_ol.ka0905_cpu$r_c\'bealr_l_bits.ka0905_cpu$v_cbealr_cbla_0#define ka0905_cpu$l_cbealr_h ka0905_cpu$r_cbealr_ol.ka0905_cpu$r_cbealr_fields.ka0905_cpu$r_cbealr_fields_h_ol.ka0905_cpu$l_cbealr\_h#define ka0905_cpu$v_cbealr_cbla_1 ka0905_cpu$r_cbealr_ol.ka0905_cpu$r_cbealr_fields.ka0905_cpu$r_cbealr_fields_h_ol.ka0905_0cpu$r_c\'bealr_h_bits.ka0905_cpu$v_cbealr_cbla_1F#define ka0905_cpu$q_cbeahr ka0905_cpu$r_cbeahr_ol.ka0905_cpu$q_cbeahr#define ka0905_cpu$l_cbeahr_l ka0905_cpu$r_cbeahr_ol.ka0905_cpu$r_cbeahr_fields.ka0905_cpu$r_cbeahr_fields_l_ol.ka0905_cpu$l_cbeahr\_l#define ka0905_cpu$v_cbeahr_cbha_0 ka0905_cpu$r_cbeahr_ol.ka0905_cpu$r_cbeahr_fields.ka0905_cpu$r_cbeahr_fields_l_ol.ka0905_cpu$r_c\'beahr_l_bits.ka0905_cpu$v_cbeahr_cbha_0#define ka0905_cpu$l_cbeahr_h ka0905_cpu$r_cbeahr_ol.ka0905_cpu$r_cb0eahr_fields.ka0905_cpu$r_cbeahr_fields_h_ol.ka0905_cpu$l_cbeahr\_h#define ka0905_cpu$v_cbeahr_cbha_1 ka0905_cpu$r_cbeahr_ol.ka0905_cpu$r_cbeahr_fields.ka0905_cpu$r_cbeahr_fields_h_ol.ka0905_cpu$r_c\'beahr_h_bits.ka0905_cpu$v_cbeahr_cbha_1F#define ka0905_cpu$q_cbresv ka0905_cpu$r_cbresv_ol.ka0905_cpu$q_cbresv#define ka0905_cpu$l_cbresv_l ka0905_cpu$r_cbresv_ol.ka0905_cpu$r_cbresv_fields.ka0905_cpu$r_cbresv_fields_l_ol.ka0905_cpu$l_cbresv\_l#define ka0905_cpu$v_cbresv_fill_01 ka0905_cpu$r_c0bresv_ol.ka0905_cpu$r_cbresv_fields.ka0905_cpu$r_cbresv_fields_l_ol.ka0905_cpu$r_\)cbresv_l_bits.ka0905_cpu$v_cbresv_fill_01#define ka0905_cpu$l_cbresv_h ka0905_cpu$r_cbresv_ol.ka0905_cpu$r_cbresv_fields.ka0905_cpu$r_cbresv_fields_h_ol.ka0905_cpu$l_cbresv\_h#define ka0905_cpu$v_cbresv_fill_02 ka0905_cpu$r_cbresv_ol.ka0905_cpu$r_cbresv_fields.ka0905_cpu$r_cbresv_fields_h_ol.ka0905_cpu$r_\)cbresv_h_bits.ka0905_cpu$v_cbresv_fill_02=#define ka0905_cpu$q_alr ka0905_cpu$r_alr_ol.ka0905_cpu$q_alr0v#define ka0905_cpu$l_alr_l ka0905_cpu$r_alr_ol.ka0905_cpu$r_alr_fields.ka0905_cpu$r_alr_fields_l_ol.ka0905_cpu$l_alr_l#define ka0905_cpu$v_alr_lav_0 ka0905_cpu$r_alr_ol.ka0905_cpu$r_alr_fields.ka0905_cpu$r_alr_fields_l_ol.ka0905_cpu$r_alr_l_bits.ka0\905_cpu$v_alr_lav_0#define ka0905_cpu$v_alr_fill_01 ka0905_cpu$r_alr_ol.ka0905_cpu$r_alr_fields.ka0905_cpu$r_alr_fields_l_ol.ka0905_cpu$r_alr_l_bits.k\a0905_cpu$v_alr_fill_01#define ka0905_cpu$v_alr_la_0 ka0905_cpu$r_alr_ol.ka0905_cpu$r_alr_f0ields.ka0905_cpu$r_alr_fields_l_ol.ka0905_cpu$r_alr_l_bits.ka09\05_cpu$v_alr_la_0v#define ka0905_cpu$l_alr_h ka0905_cpu$r_alr_ol.ka0905_cpu$r_alr_fields.ka0905_cpu$r_alr_fields_h_ol.ka0905_cpu$l_alr_h#define ka0905_cpu$v_alr_lav_1 ka0905_cpu$r_alr_ol.ka0905_cpu$r_alr_fields.ka0905_cpu$r_alr_fields_h_ol.ka0905_cpu$r_alr_h_bits.ka0\905_cpu$v_alr_lav_1#define ka0905_cpu$v_alr_fill_02 ka0905_cpu$r_alr_ol.ka0905_cpu$r_alr_fields.ka0905_cpu$r_alr_fields_h_ol.ka0905_cpu$r_alr_h_bits.k\a0905_cpu$0v_alr_fill_02#define ka0905_cpu$v_alr_la_1 ka0905_cpu$r_alr_ol.ka0905_cpu$r_alr_fields.ka0905_cpu$r_alr_fields_h_ol.ka0905_cpu$r_alr_h_bits.ka09\05_cpu$v_alr_la_1@#define ka0905_cpu$q_pmbr ka0905_cpu$r_pmbr_ol.ka0905_cpu$q_pmbr{#define ka0905_cpu$l_pmbr_l ka0905_cpu$r_pmbr_ol.ka0905_cpu$r_pmbr_fields.ka0905_cpu$r_pmbr_fields_l_ol.ka0905_cpu$l_pmbr_l#define ka0905_cpu$v_pmbr_data_0 ka0905_cpu$r_pmbr_ol.ka0905_cpu$r_pmbr_fields.ka0905_cpu$r_pmbr_fields_l_ol.ka0905_cpu$r_pmbr_l_bi\ts.ka0905_0cpu$v_pmbr_data_0{#define ka0905_cpu$l_pmbr_h ka0905_cpu$r_pmbr_ol.ka0905_cpu$r_pmbr_fields.ka0905_cpu$r_pmbr_fields_h_ol.ka0905_cpu$l_pmbr_h#define ka0905_cpu$v_pmbr_data_1 ka0905_cpu$r_pmbr_ol.ka0905_cpu$r_pmbr_fields.ka0905_cpu$r_pmbr_fields_h_ol.ka0905_cpu$r_pmbr_h_bi\ts.ka0905_cpu$v_pmbr_data_1@#define ka0905_cpu$q_iirr ka0905_cpu$r_iirr_ol.ka0905_cpu$q_iirr{#define ka0905_cpu$l_iirr_l ka0905_cpu$r_iirr_ol.ka0905_cpu$r_iirr_fields.ka0905_cpu$r_iirr_fields_l_ol.ka0905_cpu$l_iirr_l#def0ine ka0905_cpu$v_iirr_fill_0 ka0905_cpu$r_iirr_ol.ka0905_cpu$r_iirr_fields.ka0905_cpu$r_iirr_fields_l_ol.ka0905_cpu$r_iirr_l_bi\ts.ka0905_cpu$v_iirr_fill_0{#define ka0905_cpu$l_iirr_h ka0905_cpu$r_iirr_ol.ka0905_cpu$r_iirr_fields.ka0905_cpu$r_iirr_fields_h_ol.ka0905_cpu$l_iirr_h#define ka0905_cpu$v_iirr_fill_02 ka0905_cpu$r_iirr_ol.ka0905_cpu$r_iirr_fields.ka0905_cpu$r_iirr_fields_h_ol.ka0905_cpu$r_iirr_h_b\its.ka0905_cpu$v_iirr_fill_02#define ka0905_cpu$v_iirr_rhi ka0905_cpu$r_iirr_ol.ka00905_cpu$r_iirr_fields.ka0905_cpu$r_iirr_fields_h_ol.ka0905_cpu$r_iirr_h_bits.\ka0905_cpu$v_iirr_rhi#define ka0905_cpu$v_iirr_fill_03 ka0905_cpu$r_iirr_ol.ka0905_cpu$r_iirr_fields.ka0905_cpu$r_iirr_fields_h_ol.ka0905_cpu$r_iirr_h_b\its.ka0905_cpu$v_iirr_fill_03#define ka0905_cpu$v_iirr_ii ka0905_cpu$r_iirr_ol.ka0905_cpu$r_iirr_fields.ka0905_cpu$r_iirr_fields_h_ol.ka0905_cpu$r_iirr_h_bits.k\a0905_cpu$v_iirr_ii#define ka0905_cpu$v_iirr_fill_04 ka0905_cpu$r_iirr_ol.ka0905_cpu$r_iirr_fields.0ka0905_cpu$r_iirr_fields_h_ol.ka0905_cpu$r_iirr_h_b\its.ka0905_cpu$v_iirr_fill_04@#define ka0905_cpu$q_sicr ka0905_cpu$r_sicr_ol.ka0905_cpu$q_sicr{#define ka0905_cpu$l_sicr_l ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_l_ol.ka0905_cpu$l_sicr_l#define ka0905_cpu$v_sicr_cbeic_0 ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_l_ol.ka0905_cpu$r_sicr_l_b\its.ka0905_cpu$v_sicr_cbeic_0#define ka0905_cpu$v_sicr_fill_01 ka0905_cpu$r_sicr_ol.ka0905_0cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_l_ol.ka0905_cpu$r_sicr_l_b\its.ka0905_cpu$v_sicr_fill_01{#define ka0905_cpu$l_sicr_h ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$l_sicr_h#define ka0905_cpu$v_sicr_cbeic_1 ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$r_sicr_h_b\its.ka0905_cpu$v_sicr_cbeic_1#define ka0905_cpu$v_sicr_fill_02 ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.1ka0905_cpu$r_sicr_h_b\its.ka0905_cpu$v_sicr_fill_02#define ka0905_cpu$v_sicr_iti ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$r_sicr_h_bits.\ka0905_cpu$v_sicr_iti#define ka0905_cpu$v_sicr_fill_03 ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$r_sicr_h_b\its.ka0905_cpu$v_sicr_fill_03#define ka0905_cpu$v_sicr_sec ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$r_sicr_h_1bits.\ka0905_cpu$v_sicr_sec#define ka0905_cpu$v_sicr_fill_04 ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$r_sicr_h_b\its.ka0905_cpu$v_sicr_fill_04#define ka0905_cpu$v_sicr_nhic ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$r_sicr_h_bits\.ka0905_cpu$v_sicr_nhic#define ka0905_cpu$v_sicr_fill_05 ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$r_sicr_h_b\its.ka0905_cpu1$v_sicr_fill_05#define ka0905_cpu$v_sicr_iic ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$r_sicr_h_bits.\ka0905_cpu$v_sicr_iic#define ka0905_cpu$v_sicr_fill_06 ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$r_sicr_h_b\its.ka0905_cpu$v_sicr_fill_06#define ka0905_cpu$v_sicr_ioii ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$r_sicr_h_bits\.ka0905_cpu$v_sicr_ioii#def1ine ka0905_cpu$v_sicr_fill_07 ka0905_cpu$r_sicr_ol.ka0905_cpu$r_sicr_fields.ka0905_cpu$r_sicr_fields_h_ol.ka0905_cpu$r_sicr_h_b\its.ka0905_cpu$v_sicr_fill_07@#define ka0905_cpu$q_pmcr ka0905_cpu$r_pmcr_ol.ka0905_cpu$q_pmcr{#define ka0905_cpu$l_pmcr_l ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_l_ol.ka0905_cpu$l_pmcr_l#define ka0905_cpu$v_pmcr_ss_0 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_l_ol.ka0905_cpu$r_pmcr_l_bits\.ka0905_cpu$v_pmcr1_ss_0#define ka0905_cpu$v_pmcr_fill_01 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_l_ol.ka0905_cpu$r_pmcr_l_b\its.ka0905_cpu$v_pmcr_fill_01#define ka0905_cpu$v_pmcr_am_0 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_l_ol.ka0905_cpu$r_pmcr_l_bits\.ka0905_cpu$v_pmcr_am_0#define ka0905_cpu$v_pmcr_fill_02 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_l_ol.ka0905_cpu$r_pmcr_l_b\its.ka0905_cpu$v_pmcr_fill_02#defin1e ka0905_cpu$v_pmcr_spmr10 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_l_ol.ka0905_cpu$r_pmcr_l_bi\ts.ka0905_cpu$v_pmcr_spmr10#define ka0905_cpu$v_pmcr_spmr9 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_l_ol.ka0905_cpu$r_pmcr_l_bit\s.ka0905_cpu$v_pmcr_spmr9#define ka0905_cpu$v_pmcr_spmr8 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_l_ol.ka0905_cpu$r_pmcr_l_bit\s.ka0905_cpu$v_pmcr_spmr8#define ka0905_cpu$v_pmc1r_spmr7 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_l_ol.ka0905_cpu$r_pmcr_l_bit\s.ka0905_cpu$v_pmcr_spmr7#define ka0905_cpu$v_pmcr_spmr6 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_l_ol.ka0905_cpu$r_pmcr_l_bit\s.ka0905_cpu$v_pmcr_spmr6{#define ka0905_cpu$l_pmcr_h ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_h_ol.ka0905_cpu$l_pmcr_h#define ka0905_cpu$v_pmcr_ss_1 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka01905_cpu$r_pmcr_fields_h_ol.ka0905_cpu$r_pmcr_h_bits\.ka0905_cpu$v_pmcr_ss_1#define ka0905_cpu$v_pmcr_epmo ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_h_ol.ka0905_cpu$r_pmcr_h_bits\.ka0905_cpu$v_pmcr_epmo#define ka0905_cpu$v_pmcr_fill_03 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_h_ol.ka0905_cpu$r_pmcr_h_b\its.ka0905_cpu$v_pmcr_fill_03#define ka0905_cpu$v_pmcr_am_1 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_field1s_h_ol.ka0905_cpu$r_pmcr_h_bits\.ka0905_cpu$v_pmcr_am_1#define ka0905_cpu$v_pmcr_cidmask ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_h_ol.ka0905_cpu$r_pmcr_h_b\its.ka0905_cpu$v_pmcr_cidmask#define ka0905_cpu$v_pmcr_cidmatch ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_h_ol.ka0905_cpu$r_pmcr_h_\bits.ka0905_cpu$v_pmcr_cidmatch#define ka0905_cpu$v_pmcr_spmr5 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_h_ol.ka09 105_cpu$r_pmcr_h_bit\s.ka0905_cpu$v_pmcr_spmr5#define ka0905_cpu$v_pmcr_spmr4 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_h_ol.ka0905_cpu$r_pmcr_h_bit\s.ka0905_cpu$v_pmcr_spmr4#define ka0905_cpu$v_pmcr_spmr3 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_h_ol.ka0905_cpu$r_pmcr_h_bit\s.ka0905_cpu$v_pmcr_spmr3#define ka0905_cpu$v_pmcr_spmr2 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_h_ol.ka0905_cpu$r_pmcr_h_bit\ 1s.ka0905_cpu$v_pmcr_spmr2#define ka0905_cpu$v_pmcr_spmr1 ka0905_cpu$r_pmcr_ol.ka0905_cpu$r_pmcr_fields.ka0905_cpu$r_pmcr_fields_h_ol.ka0905_cpu$r_pmcr_h_bit\s.ka0905_cpu$v_pmcr_spmr1@#define ka0905_cpu$q_pmr1 ka0905_cpu$r_pmr1_ol.ka0905_cpu$q_pmr1{#define ka0905_cpu$l_pmr1_l ka0905_cpu$r_pmr1_ol.ka0905_cpu$r_pmr1_fields.ka0905_cpu$r_pmr1_fields_l_ol.ka0905_cpu$l_pmr1_l#define ka0905_cpu$v_pmr1_c6 ka0905_cpu$r_pmr1_ol.ka0905_cpu$r_pmr1_fields.ka0905_cpu$r_pmr1_fields_l_ol.ka0905_cpu$r_pmr1 1_l_bits.k\a0905_cpu$v_pmr1_c6#define ka0905_cpu$v_pmr1_of6 ka0905_cpu$r_pmr1_ol.ka0905_cpu$r_pmr1_fields.ka0905_cpu$r_pmr1_fields_l_ol.ka0905_cpu$r_pmr1_l_bits.\ka0905_cpu$v_pmr1_of6{#define ka0905_cpu$l_pmr1_h ka0905_cpu$r_pmr1_ol.ka0905_cpu$r_pmr1_fields.ka0905_cpu$r_pmr1_fields_h_ol.ka0905_cpu$l_pmr1_h#define ka0905_cpu$v_pmr1_c1 ka0905_cpu$r_pmr1_ol.ka0905_cpu$r_pmr1_fields.ka0905_cpu$r_pmr1_fields_h_ol.ka0905_cpu$r_pmr1_h_bits.k\a0905_cpu$v_pmr1_c1#define ka0905_cpu$v_pmr1_of1 ka 10905_cpu$r_pmr1_ol.ka0905_cpu$r_pmr1_fields.ka0905_cpu$r_pmr1_fields_h_ol.ka0905_cpu$r_pmr1_h_bits.\ka0905_cpu$v_pmr1_of1@#define ka0905_cpu$q_pmr2 ka0905_cpu$r_pmr2_ol.ka0905_cpu$q_pmr2{#define ka0905_cpu$l_pmr2_l ka0905_cpu$r_pmr2_ol.ka0905_cpu$r_pmr2_fields.ka0905_cpu$r_pmr2_fields_l_ol.ka0905_cpu$l_pmr2_l#define ka0905_cpu$v_pmr2_c7 ka0905_cpu$r_pmr2_ol.ka0905_cpu$r_pmr2_fields.ka0905_cpu$r_pmr2_fields_l_ol.ka0905_cpu$r_pmr2_l_bits.k\a0905_cpu$v_pmr2_c7#define ka0905_cpu$v_pmr2_of7 ka 10905_cpu$r_pmr2_ol.ka0905_cpu$r_pmr2_fields.ka0905_cpu$r_pmr2_fields_l_ol.ka0905_cpu$r_pmr2_l_bits.\ka0905_cpu$v_pmr2_of7{#define ka0905_cpu$l_pmr2_h ka0905_cpu$r_pmr2_ol.ka0905_cpu$r_pmr2_fields.ka0905_cpu$r_pmr2_fields_h_ol.ka0905_cpu$l_pmr2_h#define ka0905_cpu$v_pmr2_c2 ka0905_cpu$r_pmr2_ol.ka0905_cpu$r_pmr2_fields.ka0905_cpu$r_pmr2_fields_h_ol.ka0905_cpu$r_pmr2_h_bits.k\a0905_cpu$v_pmr2_c2#define ka0905_cpu$v_pmr2_of2 ka0905_cpu$r_pmr2_ol.ka0905_cpu$r_pmr2_fields.ka0905_cpu$r_pmr2_fiel1ds_h_ol.ka0905_cpu$r_pmr2_h_bits.\ka0905_cpu$v_pmr2_of2@#define ka0905_cpu$q_pmr3 ka0905_cpu$r_pmr3_ol.ka0905_cpu$q_pmr3{#define ka0905_cpu$l_pmr3_l ka0905_cpu$r_pmr3_ol.ka0905_cpu$r_pmr3_fields.ka0905_cpu$r_pmr3_fields_l_ol.ka0905_cpu$l_pmr3_l#define ka0905_cpu$v_pmr3_c8 ka0905_cpu$r_pmr3_ol.ka0905_cpu$r_pmr3_fields.ka0905_cpu$r_pmr3_fields_l_ol.ka0905_cpu$r_pmr3_l_bits.k\a0905_cpu$v_pmr3_c8#define ka0905_cpu$v_pmr3_of8 ka0905_cpu$r_pmr3_ol.ka0905_cpu$r_pmr3_fields.ka0905_cpu$r_pmr3_fiel1ds_l_ol.ka0905_cpu$r_pmr3_l_bits.\ka0905_cpu$v_pmr3_of8{#define ka0905_cpu$l_pmr3_h ka0905_cpu$r_pmr3_ol.ka0905_cpu$r_pmr3_fields.ka0905_cpu$r_pmr3_fields_h_ol.ka0905_cpu$l_pmr3_h#define ka0905_cpu$v_pmr3_c3 ka0905_cpu$r_pmr3_ol.ka0905_cpu$r_pmr3_fields.ka0905_cpu$r_pmr3_fields_h_ol.ka0905_cpu$r_pmr3_h_bits.k\a0905_cpu$v_pmr3_c3#define ka0905_cpu$v_pmr3_of3 ka0905_cpu$r_pmr3_ol.ka0905_cpu$r_pmr3_fields.ka0905_cpu$r_pmr3_fields_h_ol.ka0905_cpu$r_pmr3_h_bits.\ka0905_cpu$v_pmr3_of3@#defin1e ka0905_cpu$q_pmr4 ka0905_cpu$r_pmr4_ol.ka0905_cpu$q_pmr4{#define ka0905_cpu$l_pmr4_l ka0905_cpu$r_pmr4_ol.ka0905_cpu$r_pmr4_fields.ka0905_cpu$r_pmr4_fields_l_ol.ka0905_cpu$l_pmr4_l#define ka0905_cpu$v_pmr4_c9 ka0905_cpu$r_pmr4_ol.ka0905_cpu$r_pmr4_fields.ka0905_cpu$r_pmr4_fields_l_ol.ka0905_cpu$r_pmr4_l_bits.k\a0905_cpu$v_pmr4_c9#define ka0905_cpu$v_pmr4_of9 ka0905_cpu$r_pmr4_ol.ka0905_cpu$r_pmr4_fields.ka0905_cpu$r_pmr4_fields_l_ol.ka0905_cpu$r_pmr4_l_bits.\ka0905_cpu$v_pmr4_of9{#defin1e ka0905_cpu$l_pmr4_h ka0905_cpu$r_pmr4_ol.ka0905_cpu$r_pmr4_fields.ka0905_cpu$r_pmr4_fields_h_ol.ka0905_cpu$l_pmr4_h#define ka0905_cpu$v_pmr4_c4 ka0905_cpu$r_pmr4_ol.ka0905_cpu$r_pmr4_fields.ka0905_cpu$r_pmr4_fields_h_ol.ka0905_cpu$r_pmr4_h_bits.k\a0905_cpu$v_pmr4_c4#define ka0905_cpu$v_pmr4_of4 ka0905_cpu$r_pmr4_ol.ka0905_cpu$r_pmr4_fields.ka0905_cpu$r_pmr4_fields_h_ol.ka0905_cpu$r_pmr4_h_bits.\ka0905_cpu$v_pmr4_of4@#define ka0905_cpu$q_pmr5 ka0905_cpu$r_pmr5_ol.ka0905_cpu$q_pmr5{#defin1e ka0905_cpu$l_pmr5_l ka0905_cpu$r_pmr5_ol.ka0905_cpu$r_pmr5_fields.ka0905_cpu$r_pmr5_fields_l_ol.ka0905_cpu$l_pmr5_l#define ka0905_cpu$v_pmr5_c10 ka0905_cpu$r_pmr5_ol.ka0905_cpu$r_pmr5_fields.ka0905_cpu$r_pmr5_fields_l_ol.ka0905_cpu$r_pmr5_l_bits.\ka0905_cpu$v_pmr5_c10#define ka0905_cpu$v_pmr5_of10 ka0905_cpu$r_pmr5_ol.ka0905_cpu$r_pmr5_fields.ka0905_cpu$r_pmr5_fields_l_ol.ka0905_cpu$r_pmr5_l_bits\.ka0905_cpu$v_pmr5_of10{#define ka0905_cpu$l_pmr5_h ka0905_cpu$r_pmr5_ol.ka0905_cpu$r_pmr5_f 1ields.ka0905_cpu$r_pmr5_fields_h_ol.ka0905_cpu$l_pmr5_h#define ka0905_cpu$v_pmr5_c5 ka0905_cpu$r_pmr5_ol.ka0905_cpu$r_pmr5_fields.ka0905_cpu$r_pmr5_fields_h_ol.ka0905_cpu$r_pmr5_h_bits.k\a0905_cpu$v_pmr5_c5#define ka0905_cpu$v_pmr5_of5 ka0905_cpu$r_pmr5_ol.ka0905_cpu$r_pmr5_fields.ka0905_cpu$r_pmr5_fields_h_ol.ka0905_cpu$r_pmr5_h_bits.\ka0905_cpu$v_pmr5_of5"#endif /* #if !defined(__VAXC) */ #define KA0905_CPU$K_LENGTH 1000 $#pragma __member_alignment __restoreR#ifdef __INITIAL_P1OINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KA0905DEF_LOADED */ wwf[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidentia1l proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **1/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************* 1***********************************************************************************************************/=/* Created: 7-Oct-2024 15:22:35 by OpenVMS SDL V3.7 */I/* Source: 20-JAN-1998 11:03:32 $1$DGA8345:[LIB_H.SRC]KA0C05DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KA0C05DEF ***/#ifndef __KA0C05DEF_LOADED#define __KA0C05DEF_LOADED 1 G#pragma __nostandard /* This 1file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#defin1e __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif (#define KA0C05_BSB$M_TLIPINT_MASK 0xFFFF)#define KA0C05_BSB$M_TLIOINT4_MASK 0xFFFF+#define KA0C05_BSB$M_TLIOINT4_IPL14 0x10000+#define KA0C05_BSB$M_TLIOINT4_IPL15 0x20000+#define KA0C 105_BSB$M_TLIOINT4_IPL16 0x40000+#define KA0C05_BSB$M_TLIOINT4_IPL17 0x80000)#define KA0C05_BSB$M_TLIOINT5_MASK 0xFFFF+#define KA0C05_BSB$M_TLIOINT5_IPL14 0x10000+#define KA0C05_BSB$M_TLIOINT5_IPL15 0x20000+#define KA0C05_BSB$M_TLIOINT5_IPL16 0x40000+#define KA0C05_BSB$M_TLIOINT5_IPL17 0x80000)#define KA0C05_BSB$M_TLIOINT6_MASK 0xFFFF+#define KA0C05_BSB$M_TLIOINT6_IPL14 0x10000+#define KA0C05_BSB$M_TLIOINT6_IPL15 0x20000+#define KA0C05_BSB$M_TLIOINT6_IPL16 0x40000+#define KA0C05_B 1SB$M_TLIOINT6_IPL17 0x80000)#define KA0C05_BSB$M_TLIOINT7_MASK 0xFFFF+#define KA0C05_BSB$M_TLIOINT7_IPL14 0x10000+#define KA0C05_BSB$M_TLIOINT7_IPL15 0x20000+#define KA0C05_BSB$M_TLIOINT7_IPL16 0x40000+#define KA0C05_BSB$M_TLIOINT7_IPL17 0x80000)#define KA0C05_BSB$M_TLIOINT8_MASK 0xFFFF+#define KA0C05_BSB$M_TLIOINT8_IPL14 0x10000+#define KA0C05_BSB$M_TLIOINT8_IPL15 0x20000+#define KA0C05_BSB$M_TLIOINT8_IPL16 0x40000+#define KA0C05_BSB$M_TLIOINT8_IPL17 0x80000 c#if !defined(__N1OBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0c05_bsb {#pragma __nomember_alignment __union {, unsigned int ka0c05_bsb$l_tlprivate; __struct {4 unsigned ka0c05_bsb$v_tlprivate_f1 : 32;* } ka0c05_bsb$r_tlprivate_bits;) } ka0c05_bsb$r_tlprivate_overlay;( unsigned char ka0c05_bsb$b_f10 [60]; 1__union {* unsigned int ka0c05_bsb$l_tlipint; __struct {4 unsigned ka0c05_bsb$v_tlipint_mask : 16;2 unsigned ka0c05_bsb$v_tlipint_f1 : 16;( } ka0c05_bsb$r_tlipint_bits;' } ka0c05_bsb$r_tlipint_overlay;) unsigned char ka0c05_bsb$b_f20 [188]; __union {+ unsigned int ka0c05_bsb$l_tlioint4; __struct {5 unsigned ka0c05_bsb$v_tlioint4_mask : 16;5 unsigned ka0c05_bsb$v_tlioint4_ipl14 : 1; 15 unsigned ka0c05_bsb$v_tlioint4_ipl15 : 1;5 unsigned ka0c05_bsb$v_tlioint4_ipl16 : 1;5 unsigned ka0c05_bsb$v_tlioint4_ipl17 : 1;3 unsigned ka0c05_bsb$v_tlioint4_f1 : 12;) } ka0c05_bsb$r_tlioint4_bits;( } ka0c05_bsb$r_tlioint4_overlay;+ unsigned char ka0c05_bsb$b_fill30 [60]; __union {+ unsigned int ka0c05_bsb$l_tlioint5; __struct {5 unsigned ka0c05_bsb$v_tlioint5_mask : 16;5 1 unsigned ka0c05_bsb$v_tlioint5_ipl14 : 1;5 unsigned ka0c05_bsb$v_tlioint5_ipl15 : 1;5 unsigned ka0c05_bsb$v_tlioint5_ipl16 : 1;5 unsigned ka0c05_bsb$v_tlioint5_ipl17 : 1;3 unsigned ka0c05_bsb$v_tlioint5_f1 : 12;) } ka0c05_bsb$r_tlioint5_bits;( } ka0c05_bsb$r_tlioint5_overlay;+ unsigned char ka0c05_bsb$b_fill40 [60]; __union {+ unsigned int ka0c05_bsb$l_tlioint6; __struct {5 unsigned k 1a0c05_bsb$v_tlioint6_mask : 16;5 unsigned ka0c05_bsb$v_tlioint6_ipl14 : 1;5 unsigned ka0c05_bsb$v_tlioint6_ipl15 : 1;5 unsigned ka0c05_bsb$v_tlioint6_ipl16 : 1;5 unsigned ka0c05_bsb$v_tlioint6_ipl17 : 1;3 unsigned ka0c05_bsb$v_tlioint6_f1 : 12;) } ka0c05_bsb$r_tlioint6_bits;( } ka0c05_bsb$r_tlioint6_overlay;+ unsigned char ka0c05_bsb$b_fill50 [60]; __union {+ unsigned int ka0c05_bsb$l_tlioint7; !1 __struct {5 unsigned ka0c05_bsb$v_tlioint7_mask : 16;5 unsigned ka0c05_bsb$v_tlioint7_ipl14 : 1;5 unsigned ka0c05_bsb$v_tlioint7_ipl15 : 1;5 unsigned ka0c05_bsb$v_tlioint7_ipl16 : 1;5 unsigned ka0c05_bsb$v_tlioint7_ipl17 : 1;3 unsigned ka0c05_bsb$v_tlioint7_f1 : 12;) } ka0c05_bsb$r_tlioint7_bits;( } ka0c05_bsb$r_tlioint7_overlay;+ unsigned char ka0c05_bsb$b_fill60 [60]; __union {+ "1 unsigned int ka0c05_bsb$l_tlioint8; __struct {5 unsigned ka0c05_bsb$v_tlioint8_mask : 16;5 unsigned ka0c05_bsb$v_tlioint8_ipl14 : 1;5 unsigned ka0c05_bsb$v_tlioint8_ipl15 : 1;5 unsigned ka0c05_bsb$v_tlioint8_ipl16 : 1;5 unsigned ka0c05_bsb$v_tlioint8_ipl17 : 1;3 unsigned ka0c05_bsb$v_tlioint8_f1 : 12;) } ka0c05_bsb$r_tlioint8_bits;( } ka0c05_bsb$r_tlioint8_overlay;, unsigned char ka#10c05_bsb$b_fill70 [508]; __union {+ unsigned int ka0c05_bsb$l_tlwsdqr4; __struct {3 unsigned ka0c05_bsb$v_tlwsdqr4_f1 : 32;) } ka0c05_bsb$r_tlwsdqr4_bits;( } ka0c05_bsb$r_tlwsdqr4_overlay;+ unsigned char ka0c05_bsb$b_fill80 [60]; __union {+ unsigned int ka0c05_bsb$l_tlwsdqr5; __struct {3 unsigned ka0c05_bsb$v_tlwsdqr5_f1 : 32;) } ka0c05_bsb$r_tlwsdqr5_bits;( } ka0c05_bsb$r_tlwsd$1qr5_overlay;+ unsigned char ka0c05_bsb$b_fill90 [60]; __union {+ unsigned int ka0c05_bsb$l_tlwsdqr6; __struct {3 unsigned ka0c05_bsb$v_tlwsdqr6_f1 : 32;) } ka0c05_bsb$r_tlwsdqr6_bits;( } ka0c05_bsb$r_tlwsdqr6_overlay;) unsigned char ka0c05_bsb$b_f100 [60]; __union {+ unsigned int ka0c05_bsb$l_tlwsdqr7; __struct {3 unsigned ka0c05_bsb$v_tlwsdqr7_f1 : 32;) } ka0c05_bsb$r_tlwsdqr7_bits%1;( } ka0c05_bsb$r_tlwsdqr7_overlay;) unsigned char ka0c05_bsb$b_f110 [60]; __union {+ unsigned int ka0c05_bsb$l_tlwsdqr8; __struct {3 unsigned ka0c05_bsb$v_tlwsdqr8_f1 : 32;) } ka0c05_bsb$r_tlwsdqr8_bits;( } ka0c05_bsb$r_tlwsdqr8_overlay;* unsigned char ka0c05_bsb$b_f120 [252]; __union {+ unsigned int ka0c05_bsb$l_tlrmdqrx; __struct {3 unsigned ka0c05_bsb$v_tlrmdqrx_f1 : 32;) &1 } ka0c05_bsb$r_tlrmdqrx_bits;( } ka0c05_bsb$r_tlrmdqrx_overlay;) unsigned char ka0c05_bsb$b_f130 [60]; __union {+ unsigned int ka0c05_bsb$l_tlrmdqr8; __struct {3 unsigned ka0c05_bsb$v_tlrmdqr8_f1 : 32;) } ka0c05_bsb$r_tlrmdqr8_bits;( } ka0c05_bsb$r_tlrmdqr8_overlay;* unsigned char ka0c05_bsb$b_f140 [444]; __union {$ __int64 ka0c05_bsb$q_tlrdrd;& } ka0c05_bsb$r_tlrdrd_overlay;) unsigned char ka0c05'1_bsb$b_f150 [60]; __union {) unsigned int ka0c05_bsb$l_tlrdre; __struct {1 unsigned ka0c05_bsb$v_tlrdre_f1 : 32;' } ka0c05_bsb$r_tlrdre_bits;& } ka0c05_bsb$r_tlrdre_overlay;+ unsigned char ka0c05_bsb$b_f160 [4156]; __union {( unsigned int ka0c05_bsb$l_tlmcr; __struct {0 unsigned ka0c05_bsb$v_tlmcr_f1 : 32;& } ka0c05_bsb$r_tlmcr_bits;% } ka0c05_bsb$r_tlmcr_overlay;+ unsigned c (1har ka0c05_bsb$b_f170 [1916];" char ka0c05_bsb$b_fill_0_ [4]; } KA0C05_BSB; #if !defined(__VAXC)T#define ka0c05_bsb$l_tlprivate ka0c05_bsb$r_tlprivate_overlay.ka0c05_bsb$l_tlprivateN#define ka0c05_bsb$l_tlipint ka0c05_bsb$r_tlipint_overlay.ka0c05_bsb$l_tlipintr#define ka0c05_bsb$v_tlipint_mask ka0c05_bsb$r_tlipint_overlay.ka0c05_bsb$r_tlipint_bits.ka0c05_bsb$v_tlipint_maskQ#define ka0c05_bsb$l_tlioint4 ka0c05_bsb$r_tlioint4_overlay.ka0c05_bsb$l_tlioint4v#define ka0c05_bsb$v_tlioi)1nt4_mask ka0c05_bsb$r_tlioint4_overlay.ka0c05_bsb$r_tlioint4_bits.ka0c05_bsb$v_tlioint4_maskx#define ka0c05_bsb$v_tlioint4_ipl14 ka0c05_bsb$r_tlioint4_overlay.ka0c05_bsb$r_tlioint4_bits.ka0c05_bsb$v_tlioint4_ipl14x#define ka0c05_bsb$v_tlioint4_ipl15 ka0c05_bsb$r_tlioint4_overlay.ka0c05_bsb$r_tlioint4_bits.ka0c05_bsb$v_tlioint4_ipl15x#define ka0c05_bsb$v_tlioint4_ipl16 ka0c05_bsb$r_tlioint4_overlay.ka0c05_bsb$r_tlioint4_bits.ka0c05_bsb$v_tlioint4_ipl16x#define ka0c05_bsb$v_tlioint4_ipl17 ka0c05_bsb*1$r_tlioint4_overlay.ka0c05_bsb$r_tlioint4_bits.ka0c05_bsb$v_tlioint4_ipl17Q#define ka0c05_bsb$l_tlioint5 ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$l_tlioint5v#define ka0c05_bsb$v_tlioint5_mask ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$r_tlioint5_bits.ka0c05_bsb$v_tlioint5_maskx#define ka0c05_bsb$v_tlioint5_ipl14 ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$r_tlioint5_bits.ka0c05_bsb$v_tlioint5_ipl14x#define ka0c05_bsb$v_tlioint5_ipl15 ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$r_tlioint5_bits.ka0c05_bsb$+1v_tlioint5_ipl15x#define ka0c05_bsb$v_tlioint5_ipl16 ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$r_tlioint5_bits.ka0c05_bsb$v_tlioint5_ipl16x#define ka0c05_bsb$v_tlioint5_ipl17 ka0c05_bsb$r_tlioint5_overlay.ka0c05_bsb$r_tlioint5_bits.ka0c05_bsb$v_tlioint5_ipl17Q#define ka0c05_bsb$l_tlioint6 ka0c05_bsb$r_tlioint6_overlay.ka0c05_bsb$l_tlioint6v#define ka0c05_bsb$v_tlioint6_mask ka0c05_bsb$r_tlioint6_overlay.ka0c05_bsb$r_tlioint6_bits.ka0c05_bsb$v_tlioint6_maskx#define ka0c05_bsb$v_tlioint6_ipl14 ka0c,105_bsb$r_tlioint6_overlay.ka0c05_bsb$r_tlioint6_bits.ka0c05_bsb$v_tlioint6_ipl14x#define ka0c05_bsb$v_tlioint6_ipl15 ka0c05_bsb$r_tlioint6_overlay.ka0c05_bsb$r_tlioint6_bits.ka0c05_bsb$v_tlioint6_ipl15x#define ka0c05_bsb$v_tlioint6_ipl16 ka0c05_bsb$r_tlioint6_overlay.ka0c05_bsb$r_tlioint6_bits.ka0c05_bsb$v_tlioint6_ipl16x#define ka0c05_bsb$v_tlioint6_ipl17 ka0c05_bsb$r_tlioint6_overlay.ka0c05_bsb$r_tlioint6_bits.ka0c05_bsb$v_tlioint6_ipl17Q#define ka0c05_bsb$l_tlioint7 ka0c05_bsb$r_tlioint7_overla-1y.ka0c05_bsb$l_tlioint7v#define ka0c05_bsb$v_tlioint7_mask ka0c05_bsb$r_tlioint7_overlay.ka0c05_bsb$r_tlioint7_bits.ka0c05_bsb$v_tlioint7_maskx#define ka0c05_bsb$v_tlioint7_ipl14 ka0c05_bsb$r_tlioint7_overlay.ka0c05_bsb$r_tlioint7_bits.ka0c05_bsb$v_tlioint7_ipl14x#define ka0c05_bsb$v_tlioint7_ipl15 ka0c05_bsb$r_tlioint7_overlay.ka0c05_bsb$r_tlioint7_bits.ka0c05_bsb$v_tlioint7_ipl15x#define ka0c05_bsb$v_tlioint7_ipl16 ka0c05_bsb$r_tlioint7_overlay.ka0c05_bsb$r_tlioint7_bits.ka0c05_bsb$v_tlioint7_i.1pl16x#define ka0c05_bsb$v_tlioint7_ipl17 ka0c05_bsb$r_tlioint7_overlay.ka0c05_bsb$r_tlioint7_bits.ka0c05_bsb$v_tlioint7_ipl17Q#define ka0c05_bsb$l_tlioint8 ka0c05_bsb$r_tlioint8_overlay.ka0c05_bsb$l_tlioint8v#define ka0c05_bsb$v_tlioint8_mask ka0c05_bsb$r_tlioint8_overlay.ka0c05_bsb$r_tlioint8_bits.ka0c05_bsb$v_tlioint8_maskx#define ka0c05_bsb$v_tlioint8_ipl14 ka0c05_bsb$r_tlioint8_overlay.ka0c05_bsb$r_tlioint8_bits.ka0c05_bsb$v_tlioint8_ipl14x#define ka0c05_bsb$v_tlioint8_ipl15 ka0c05_bsb$r_tli/1oint8_overlay.ka0c05_bsb$r_tlioint8_bits.ka0c05_bsb$v_tlioint8_ipl15x#define ka0c05_bsb$v_tlioint8_ipl16 ka0c05_bsb$r_tlioint8_overlay.ka0c05_bsb$r_tlioint8_bits.ka0c05_bsb$v_tlioint8_ipl16x#define ka0c05_bsb$v_tlioint8_ipl17 ka0c05_bsb$r_tlioint8_overlay.ka0c05_bsb$r_tlioint8_bits.ka0c05_bsb$v_tlioint8_ipl17Q#define ka0c05_bsb$l_tlwsdqr4 ka0c05_bsb$r_tlwsdqr4_overlay.ka0c05_bsb$l_tlwsdqr4Q#define ka0c05_bsb$l_tlwsdqr5 ka0c05_bsb$r_tlwsdqr5_overlay.ka0c05_bsb$l_tlwsdqr5Q#define ka0c05_bsb$l_tlw01sdqr6 ka0c05_bsb$r_tlwsdqr6_overlay.ka0c05_bsb$l_tlwsdqr6Q#define ka0c05_bsb$l_tlwsdqr7 ka0c05_bsb$r_tlwsdqr7_overlay.ka0c05_bsb$l_tlwsdqr7Q#define ka0c05_bsb$l_tlwsdqr8 ka0c05_bsb$r_tlwsdqr8_overlay.ka0c05_bsb$l_tlwsdqr8Q#define ka0c05_bsb$l_tlrmdqrx ka0c05_bsb$r_tlrmdqrx_overlay.ka0c05_bsb$l_tlrmdqrxQ#define ka0c05_bsb$l_tlrmdqr8 ka0c05_bsb$r_tlrmdqr8_overlay.ka0c05_bsb$l_tlrmdqr8K#define ka0c05_bsb$q_tlrdrd ka0c05_bsb$r_tlrdrd_overlay.ka0c05_bsb$q_tlrdrdK#define ka0c05_bsb$l_tlrdre ka0c 1105_bsb$r_tlrdre_overlay.ka0c05_bsb$l_tlrdreH#define ka0c05_bsb$l_tlmcr ka0c05_bsb$r_tlmcr_overlay.ka0c05_bsb$l_tlmcr"#endif /* #if !defined(__VAXC) */ (#define KA0C05_TLEP$M_TLDEV_DTYPE 0xFFFF*#define KA0C05_TLEP$M_TLDEV_SWREV 0xFF0000,#define KA0C05_TLEP$M_TLDEV_HWREV 0xFF000000$#define KA0C05_TLEP$M_TLBER_ATCE 0x1##define KA0C05_TLEP$M_TLBER_APE 0x2##define KA0C05_TLEP$M_TLBER_BBE 0x4$#define KA0C05_TLEP$M_TLBER_LKTO 0x8$#define KA0C05_TLEP$M_TLBER_NAE 0x10%#define KA0C05_TLEP$M_TL 21BER_RTCE 0x20'#define KA0C05_TLEP$M_TLBER_ACKTCE 0x40%#define KA0C05_TLEP$M_TLBER_MMRE 0x80&#define KA0C05_TLEP$M_TLBER_FNAE 0x100'#define KA0C05_TLEP$M_TLBER_REQDE 0x200&#define KA0C05_TLEP$M_TLBER_ATDE 0x400'#define KA0C05_TLEP$M_TLBER_UDE 0x10000(#define KA0C05_TLEP$M_TLBER_CWDE 0x20000(#define KA0C05_TLEP$M_TLBER_CRDE 0x40000(#define KA0C05_TLEP$M_TLBER_DS0 0x100000(#define KA0C05_TLEP$M_TLBER_DS1 0x200000(#define KA0C05_TLEP$M_TLBER_DS2 0x400000(#define KA0C05_TLEP$M_TLBER_DS3 0x 31800000*#define KA0C05_TLEP$M_TLBER_DTDE 0x1000000+#define KA0C05_TLEP$M_TLBER_FDTCE 0x2000000+#define KA0C05_TLEP$M_TLBER_UACKE 0x4000000+#define KA0C05_TLEP$M_TLBER_ABTCE 0x8000000,#define KA0C05_TLEP$M_TLBER_DCTCE 0x10000000+#define KA0C05_TLEP$M_TLBER_SEQE 0x20000000*#define KA0C05_TLEP$M_TLBER_DSE 0x40000000*#define KA0C05_TLEP$M_TLBER_DTO 0x80000000$#define KA0C05_TLEP$M_TLCNR_CWDD 0x1$#define KA0C05_TLEP$M_TLCNR_CRDD 0x2$#define KA0C05_TLEP$M_TLCNR_DTOD 0x8(#define KA0C05_TLEP$M_ 41TLCNR_NODE_ID 0xF0&#define KA0C05_TLEP$M_TLCNR_VCNT 0xF00(#define KA0C05_TLEP$M_TLCNR_STF_A 0x1000(#define KA0C05_TLEP$M_TLCNR_STF_B 0x2000+#define KA0C05_TLEP$M_TLCNR_HALT_A 0x100000+#define KA0C05_TLEP$M_TLCNR_HALT_B 0x200000+#define KA0C05_TLEP$M_TLCNR_NRST 0x40000000+#define KA0C05_TLEP$M_TLCNR_LOFE 0x80000000#define KA0C05_TLEP$M_VID_A 0xF #define KA0C05_TLEP$M_VID_B 0xF0(#define KA0C05_TLEP$M_TLMMR0_INTMASK 0x3)#define KA0C05_TLEP$M_TLMMR0_ADRMASK 0xF0(#define KA0C05_TLEP$M_TL 51MMR0_INTLV 0x700(#define KA0C05_TLEP$M_TLMMR0_SBANK 0x800.#define KA0C05_TLEP$M_TLMMR0_ADDRESS 0x3FFF000-#define KA0C05_TLEP$M_TLMMR0_VALID 0x80000000(#define KA0C05_TLEP$M_TLMMR1_INTMASK 0x3)#define KA0C05_TLEP$M_TLMMR1_ADRMASK 0xF0(#define KA0C05_TLEP$M_TLMMR1_INTLV 0x700(#define KA0C05_TLEP$M_TLMMR1_SBANK 0x800.#define KA0C05_TLEP$M_TLMMR1_ADDRESS 0x3FFF000-#define KA0C05_TLEP$M_TLMMR1_VALID 0x80000000(#define KA0C05_TLEP$M_TLMMR2_INTMASK 0x3)#define KA0C05_TLEP$M_TLMMR2_ADRMASK 0xF0 61(#define KA0C05_TLEP$M_TLMMR2_INTLV 0x700(#define KA0C05_TLEP$M_TLMMR2_SBANK 0x800.#define KA0C05_TLEP$M_TLMMR2_ADDRESS 0x3FFF000-#define KA0C05_TLEP$M_TLMMR2_VALID 0x80000000(#define KA0C05_TLEP$M_TLMMR3_INTMASK 0x3)#define KA0C05_TLEP$M_TLMMR3_ADRMASK 0xF0(#define KA0C05_TLEP$M_TLMMR3_INTLV 0x700(#define KA0C05_TLEP$M_TLMMR3_SBANK 0x800.#define KA0C05_TLEP$M_TLMMR3_ADDRESS 0x3FFF000-#define KA0C05_TLEP$M_TLMMR3_VALID 0x80000000(#define KA0C05_TLEP$M_TLMMR4_INTMASK 0x3)#define KA0C05_T 71LEP$M_TLMMR4_ADRMASK 0xF0(#define KA0C05_TLEP$M_TLMMR4_INTLV 0x700(#define KA0C05_TLEP$M_TLMMR4_SBANK 0x800.#define KA0C05_TLEP$M_TLMMR4_ADDRESS 0x3FFF000-#define KA0C05_TLEP$M_TLMMR4_VALID 0x80000000(#define KA0C05_TLEP$M_TLMMR5_INTMASK 0x3)#define KA0C05_TLEP$M_TLMMR5_ADRMASK 0xF0(#define KA0C05_TLEP$M_TLMMR5_INTLV 0x700(#define KA0C05_TLEP$M_TLMMR5_SBANK 0x800.#define KA0C05_TLEP$M_TLMMR5_ADDRESS 0x3FFF000-#define KA0C05_TLEP$M_TLMMR5_VALID 0x80000000(#define KA0C05_TLEP$M_TLMMR6_INT 81MASK 0x3)#define KA0C05_TLEP$M_TLMMR6_ADRMASK 0xF0(#define KA0C05_TLEP$M_TLMMR6_INTLV 0x700(#define KA0C05_TLEP$M_TLMMR6_SBANK 0x800.#define KA0C05_TLEP$M_TLMMR6_ADDRESS 0x3FFF000-#define KA0C05_TLEP$M_TLMMR6_VALID 0x80000000(#define KA0C05_TLEP$M_TLMMR7_INTMASK 0x3)#define KA0C05_TLEP$M_TLMMR7_ADRMASK 0xF0(#define KA0C05_TLEP$M_TLMMR7_INTLV 0x700(#define KA0C05_TLEP$M_TLMMR7_SBANK 0x800.#define KA0C05_TLEP$M_TLMMR7_ADDRESS 0x3FFF000-#define KA0C05_TLEP$M_TLMMR7_VALID 0x80000000'#defin 91e KA0C05_TLEP$M_TLESR0_SYND0 0xFF)#define KA0C05_TLEP$M_TLESR0_SYND1 0xFF00(#define KA0C05_TLEP$M_TLESR0_TDE 0x10000(#define KA0C05_TLEP$M_TLESR0_TCE 0x20000*#define KA0C05_TLEP$M_TLESR0_DVTCE 0x40000)#define KA0C05_TLEP$M_TLESR0_UECC 0x80000+#define KA0C05_TLEP$M_TLESR0_CWECC 0x100000+#define KA0C05_TLEP$M_TLESR0_CRECC 0x200000*#define KA0C05_TLEP$M_TLESR0_CPU0 0x400000*#define KA0C05_TLEP$M_TLESR0_CPU1 0x800000.#define KA0C05_TLEP$M_TLESR0_LOFSYN 0x80000000'#define KA0C05_TLEP$M_TLES :1R1_SYND0 0xFF)#define KA0C05_TLEP$M_TLESR1_SYND1 0xFF00(#define KA0C05_TLEP$M_TLESR1_TDE 0x10000(#define KA0C05_TLEP$M_TLESR1_TCE 0x20000*#define KA0C05_TLEP$M_TLESR1_DVTCE 0x40000)#define KA0C05_TLEP$M_TLESR1_UECC 0x80000+#define KA0C05_TLEP$M_TLESR1_CWECC 0x100000+#define KA0C05_TLEP$M_TLESR1_CRECC 0x200000*#define KA0C05_TLEP$M_TLESR1_CPU0 0x400000*#define KA0C05_TLEP$M_TLESR1_CPU1 0x800000.#define KA0C05_TLEP$M_TLESR1_LOFSYN 0x80000000'#define KA0C05_TLEP$M_TLESR2_SYND0 0xFF)#def ;1ine KA0C05_TLEP$M_TLESR2_SYND1 0xFF00(#define KA0C05_TLEP$M_TLESR2_TDE 0x10000(#define KA0C05_TLEP$M_TLESR2_TCE 0x20000*#define KA0C05_TLEP$M_TLESR2_DVTCE 0x40000)#define KA0C05_TLEP$M_TLESR2_UECC 0x80000+#define KA0C05_TLEP$M_TLESR2_CWECC 0x100000+#define KA0C05_TLEP$M_TLESR2_CRECC 0x200000*#define KA0C05_TLEP$M_TLESR2_CPU0 0x400000*#define KA0C05_TLEP$M_TLESR2_CPU1 0x800000.#define KA0C05_TLEP$M_TLESR2_LOFSYN 0x80000000'#define KA0C05_TLEP$M_TLESR3_SYND0 0xFF)#define KA0C05_TLEP$M_TL <1ESR3_SYND1 0xFF00(#define KA0C05_TLEP$M_TLESR3_TDE 0x10000(#define KA0C05_TLEP$M_TLESR3_TCE 0x20000*#define KA0C05_TLEP$M_TLESR3_DVTCE 0x40000)#define KA0C05_TLEP$M_TLESR3_UECC 0x80000+#define KA0C05_TLEP$M_TLESR3_CWECC 0x100000+#define KA0C05_TLEP$M_TLESR3_CRECC 0x200000*#define KA0C05_TLEP$M_TLESR3_CPU0 0x400000*#define KA0C05_TLEP$M_TLESR3_CPU1 0x800000.#define KA0C05_TLEP$M_TLESR3_LOFSYN 0x80000000&#define KA0C05_TLEP$M_TLDIAG_FRIGN 0x1%#define KA0C05_TLEP$M_TLDIAG_DTWR 0x2%#defin =1e KA0C05_TLEP$M_TLDIAG_DTRD 0x4%#define KA0C05_TLEP$M_TLDIAG_DTCP 0x8%#define KA0C05_TLEP$M_TLDIAG_FVW 0x10%#define KA0C05_TLEP$M_TLDIAG_FAE 0x20&#define KA0C05_TLEP$M_TLDIAG_FCBE 0x40&#define KA0C05_TLEP$M_TLDIAG_FDBE 0x80&#define KA0C05_TLEP$M_TLDIAG_FDE 0xF00'#define KA0C05_TLEP$M_TLDIAG_FTW 0x1000,#define KA0C05_TLEP$M_TLDIAG_ASRT_FLT 0x2000,#define KA0C05_TLEP$M_TLDIAG_QWVAL_EN 0x4000)#define KA0C05_TLEP$M_TLDIAG_GSLOW 0x8000*#define KA0C05_TLEP$M_TLDTAGD_DTAG_PAR 0x1/#define KA >10C05_TLEP$M_TLDTAGD_DTAG_DATA 0xFFFFE)#define KA0C05_TLEP$M_TLDTAGS_STATPAR 0x1'#define KA0C05_TLEP$M_TLDTAGS_STATD 0x2'#define KA0C05_TLEP$M_TLDTAGS_STATS 0x4'#define KA0C05_TLEP$M_TLDTAGS_STATV 0x8)#define KA0C05_TLEP$M_TLMCFG_CPU0DSBL 0x1)#define KA0C05_TLEP$M_TLMCFG_CPU1DSBL 0x2(#define KA0C05_TLEP$M_TLMCFG_BC_SIZE 0xC'#define KA0C05_TLEP$M_TLMCFG_LO_EN 0x10)#define KA0C05_TLEP$M_TLMCFG_RM_SIZE 0x20)#define KA0C05_TLEP$M_TLMCFG_BCIDLE 0x3C0,#define KA0C05_TLEP$M_TLMCFG_CQ_ENTR ?1Y 0x1C00,#define KA0C05_TLEP$M_TLMCFG_BQ_ENTRY 0xE000-#define KA0C05_TLEP$M_TLMCFG_SYS_DSBL 0x10000-#define KA0C05_TLEP$M_TLMCFG_EV5_DSBL 0x20000-#define KA0C05_TLEP$M_TLMCFG_FLT_DSBL 0x40000+#define KA0C05_TLEP$M_TLIMASK0_DUART0EN 0x1+#define KA0C05_TLEP$M_TLIMASK0_IPL14_EN 0x2+#define KA0C05_TLEP$M_TLIMASK0_IPL15_EN 0x4+#define KA0C05_TLEP$M_TLIMASK0_IPL16_EN 0x8,#define KA0C05_TLEP$M_TLIMASK0_IPL17_EN 0x10)#define KA0C05_TLEP$M_TLIMASK0_IP_EN 0x20,#define KA0C05_TLEP$M_TLIMASK0_I @1NTIM_EN 0x40+#define KA0C05_TLEP$M_TLIMASK0_HALT_EN 0x80*#define KA0C05_TLEP$M_TLIMASK0_CP_EN 0x100+#define KA0C05_TLEP$M_TLIMASK1_DUART0EN 0x1+#define KA0C05_TLEP$M_TLIMASK1_IPL14_EN 0x2+#define KA0C05_TLEP$M_TLIMASK1_IPL15_EN 0x4+#define KA0C05_TLEP$M_TLIMASK1_IPL16_EN 0x8,#define KA0C05_TLEP$M_TLIMASK1_IPL17_EN 0x10)#define KA0C05_TLEP$M_TLIMASK1_IP_EN 0x20,#define KA0C05_TLEP$M_TLIMASK1_INTIM_EN 0x40+#define KA0C05_TLEP$M_TLIMASK1_HALT_EN 0x80*#define KA0C05_TLEP$M_TLIMASK1_CP_EN A1 0x100+#define KA0C05_TLEP$M_TLISUM0_DUART0INT 0x1+#define KA0C05_TLEP$M_TLISUM0_IPL14_INT 0x2+#define KA0C05_TLEP$M_TLISUM0_IPL15_INT 0x4+#define KA0C05_TLEP$M_TLISUM0_IPL16_INT 0x8,#define KA0C05_TLEP$M_TLISUM0_IPL17_INT 0x10)#define KA0C05_TLEP$M_TLISUM0_IP_INT 0x20,#define KA0C05_TLEP$M_TLISUM0_INTIM_INT 0x40)#define KA0C05_TLEP$M_TLISUM0_IPL14 0xF80+#define KA0C05_TLEP$M_TLISUM0_IPL15 0x1F000,#define KA0C05_TLEP$M_TLISUM0_IPL16 0x3E0000-#define KA0C05_TLEP$M_TLISUM0_IPL17 0x7C00 B1000/#define KA0C05_TLEP$M_TLISUM0_CP_HALT 0x8000000-#define KA0C05_TLEP$M_TLISUM0_HALT 0x10000000+#define KA0C05_TLEP$M_TLISUM1_DUART0INT 0x1+#define KA0C05_TLEP$M_TLISUM1_IPL14_INT 0x2+#define KA0C05_TLEP$M_TLISUM1_IPL15_INT 0x4+#define KA0C05_TLEP$M_TLISUM1_IPL16_INT 0x8,#define KA0C05_TLEP$M_TLISUM1_IPL17_INT 0x10)#define KA0C05_TLEP$M_TLISUM1_IP_INT 0x20,#define KA0C05_TLEP$M_TLISUM1_INTIM_INT 0x40)#define KA0C05_TLEP$M_TLISUM1_IPL14 0xF80+#define KA0C05_TLEP$M_TLISUM1_IPL15 0x C11F000,#define KA0C05_TLEP$M_TLISUM1_IPL16 0x3E0000-#define KA0C05_TLEP$M_TLISUM1_IPL17 0x7C00000/#define KA0C05_TLEP$M_TLISUM1_CP_HALT 0x8000000-#define KA0C05_TLEP$M_TLISUM1_HALT 0x10000000*#define KA0C05_TLEP$M_TLEPAERR_E2MAPE0 0x1*#define KA0C05_TLEP$M_TLEPAERR_E2MAPE1 0x2*#define KA0C05_TLEP$M_TLEPAERR_M2AAPE0 0x4*#define KA0C05_TLEP$M_TLEPAERR_M2AAPE1 0x8)#define KA0C05_TLEP$M_TLEPAERR_DTDPE 0x10)#define KA0C05_TLEP$M_TLEPAERR_DTSPE 0x20*#define KA0C05_TLEP$M_TLEPAERR_D2ACPE 0x40 D1+#define KA0C05_TLEP$M_TLEPAERR_SYSDERR 0x80+#define KA0C05_TLEP$M_TLEPAERR_SYSFLT 0x100+#define KA0C05_TLEP$M_TLEPAERR_RD_ERR 0x600,#define KA0C05_TLEP$M_TLEPAERR_IBOXTO 0x1800-#define KA0C05_TLEP$M_TLEPAERR_RD_PEND 0x6000)#define KA0C05_TLEP$M_TLEPAERR_NXM 0x8000-#define KA0C05_TLEP$M_TLEPAERR_NO_ACK 0x30000)#define KA0C05_TLEP$M_TLEPDERR_A2DCPE 0x1*#define KA0C05_TLEP$M_TLEPDERR_D2DCPE0 0x2'#define KA0C05_TLEP$M_TLEPDERR_GBTO 0x4*#define KA0C05_TLEP$M_TLEPMERR_A2MAPE0 0x1*#defin E1e KA0C05_TLEP$M_TLEPMERR_A2MAPE1 0x2)#define KA0C05_TLEP$M_TLEPMERR_D2MCPE 0x4*#define KA0C05_TLEP$M_TLEPMERR_D2DCPE1 0x8+#define KA0C05_TLEP$M_TLEPMERR_D2DCPE2 0x10+#define KA0C05_TLEP$M_TLEPMERR_D2DCPE3 0x20+#define KA0C05_TLEP$M_TLEPMERR_RSTSTAT 0x40%#define KA0C05_TLEP$M_TLEP_VMG_5P 0x1%#define KA0C05_TLEP$M_TLEP_VMG_5M 0x2%#define KA0C05_TLEP$M_TLEP_VMG_3P 0x4%#define KA0C05_TLEP$M_TLEP_VMG_3M 0x8*#define KA0C05_TLEP$M_TLDMCMD_SIZE_512 0x1)#define KA0C05_TLEP$M_TLDMCMD_SIZE_1K F10x2)#define KA0C05_TLEP$M_TLDMCMD_SIZE_2K 0x4)#define KA0C05_TLEP$M_TLDMCMD_SIZE_4K 0x8*#define KA0C05_TLEP$M_TLDMCMD_SIZE_8K 0x10'#define KA0C05_TLEP$M_TLDMCMD_CMD 0x300)#define KA0C05_TLEP$M_TLDMCMD_VALID 0x800)#define KA0C05_TLEP$M_TLDMCMD_RM_3 0x1000)#define KA0C05_TLEP$M_TLDMCMD_RM_4 0x2000,#define KA0C05_TLEP$M_TLDMCMD_RM_INLV 0x4000,#define KA0C05_TLEP$M_TLDMCMD_CPU_ID 0x10000.#define KA0C05_TLEP$M_TLDMCMD_IN_PROG 0x100000+#define KA0C05_TLEP$M_TLDMCMD_DONE 0x200000.#define G1KA0C05_TLEP$M_TLDMADRA_ADDR 0x3FFFFFFF.#define KA0C05_TLEP$M_TLDMADRB_ADDR 0x3FFFFFFF)#define KA0C05_TLEP$M_TLPM_CMD_CPUNUM 0x1*#define KA0C05_TLEP$M_TLPM_CMD_SET_SEL 0x6(#define KA0C05_TLEP$M_TLPM_CMD_VALID 0x8,#define KA0C05_TLEP$M_TLPM_CMD_READ_SET 0x10,#define KA0C05_TLEP$M_TLPM_CMD_OVRF_EN 0x800-#define KA0C05_TLEP$M_TLPM_CMD_TOT_CYC 0x1000-#define KA0C05_TLEP$M_TLPM_CMD_EV5_LAT 0x2000,#define KA0C05_TLEP$M_TLPM_CMD_RD_LAT 0x4000-#define KA0C05_TLEP$M_TLPM_CMD_SYS_OWN 0x8000)#defin H1e KA0C05_TLEP$M_TLPM_CMD_F2 0x10000+#define KA0C05_TLEP$M_TLPM_CMD_LOCK 0x20000)#define KA0C05_TLEP$M_TLPM_CMD_MB 0x40000-#define KA0C05_TLEP$M_TLPM_CMD_SD_TOT 0x80000.#define KA0C05_TLEP$M_TLPM_CMD_SD_ACK 0x100000.#define KA0C05_TLEP$M_TLPM_CMD_RD_CSR 0x200000*#define KA0C05_TLEP$M_TLPM_CMD_RD 0x400000.#define KA0C05_TLEP$M_TLPM_CMD_RD_MOD 0x800000/#define KA0C05_TLEP$M_TLPM_CMD_RD_STC 0x1000000,#define KA0C05_TLEP$M_TLPM_CMD_VIC 0x2000000/#define KA0C05_TLEP$M_TLPM_CMD_WR_CSR 0x400000 I10+#define KA0C05_TLEP$M_TLPM_CMD_WR 0x80000001#define KA0C05_TLEP$M_TLPM_CMD_WR_LOCK 0x10000000/#define KA0C05_TLEP$M_TLPM_CMD_INVAL 0x200000001#define KA0C05_TLEP$M_TLPM_CMD_SET_SHR 0x400000001#define KA0C05_TLEP$M_TLPM_CMD_RD_DIRT 0x80000000'#define KA0C05_TLEP$M_RM_REG0A_AEXT 0xF.#define KA0C05_TLEP$M_RM_REG0A_BADDR 0xFFFFF00/#define KA0C05_TLEP$M_RM_REG0A_VALID 0x80000000'#define KA0C05_TLEP$M_RM_REG0B_AEXT 0xF.#define KA0C05_TLEP$M_RM_REG0B_BADDR 0xFFFFF00/#define KA0C05_TLEP$J1M_RM_REG0B_VALID 0x80000000'#define KA0C05_TLEP$M_RM_REG1A_AEXT 0xF.#define KA0C05_TLEP$M_RM_REG1A_BADDR 0xFFFFF00/#define KA0C05_TLEP$M_RM_REG1A_VALID 0x80000000'#define KA0C05_TLEP$M_RM_REG1B_AEXT 0xF.#define KA0C05_TLEP$M_RM_REG1B_BADDR 0xFFFFF00/#define KA0C05_TLEP$M_RM_REG1B_VALID 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftyK1pedef struct _ka0c05_tlep {#pragma __nomember_alignment __union {) unsigned int ka0c05_tlep$l_tldev; __struct {4 unsigned ka0c05_tlep$v_tldev_dtype : 16;3 unsigned ka0c05_tlep$v_tldev_swrev : 8;3 unsigned ka0c05_tlep$v_tldev_hwrev : 8;' } ka0c05_tlep$r_tldev_bits;& } ka0c05_tlep$r_tldev_overlay;* unsigned char ka0c05_tlep$b_f200 [60]; __union {) unsigned int ka0c05_tlep$l_tlber; __struct L1 {2 unsigned ka0c05_tlep$v_tlber_atce : 1;1 unsigned ka0c05_tlep$v_tlber_ape : 1;1 unsigned ka0c05_tlep$v_tlber_bbe : 1;2 unsigned ka0c05_tlep$v_tlber_lkto : 1;1 unsigned ka0c05_tlep$v_tlber_nae : 1;2 unsigned ka0c05_tlep$v_tlber_rtce : 1;4 unsigned ka0c05_tlep$v_tlber_acktce : 1;2 unsigned ka0c05_tlep$v_tlber_mmre : 1;2 unsigned ka0c05_tlep$v_tlber_fnae : 1;3 unsigned ka0c05_tl M1ep$v_tlber_reqde : 1;2 unsigned ka0c05_tlep$v_tlber_atde : 1;0 unsigned ka0c05_tlep$v_tlber_f1 : 5;1 unsigned ka0c05_tlep$v_tlber_ude : 1;2 unsigned ka0c05_tlep$v_tlber_cwde : 1;2 unsigned ka0c05_tlep$v_tlber_crde : 1;3 unsigned ka0c05_tlep$v_tlber_cwde2 : 1;1 unsigned ka0c05_tlep$v_tlber_ds0 : 1;1 unsigned ka0c05_tlep$v_tlber_ds1 : 1;1 unsigned ka0c05_tlep$v_tlber_ds2 : 1;1 un N1signed ka0c05_tlep$v_tlber_ds3 : 1;2 unsigned ka0c05_tlep$v_tlber_dtde : 1;3 unsigned ka0c05_tlep$v_tlber_fdtce : 1;3 unsigned ka0c05_tlep$v_tlber_uacke : 1;3 unsigned ka0c05_tlep$v_tlber_abtce : 1;3 unsigned ka0c05_tlep$v_tlber_dctce : 1;2 unsigned ka0c05_tlep$v_tlber_seqe : 1;1 unsigned ka0c05_tlep$v_tlber_dse : 1;1 unsigned ka0c05_tlep$v_tlber_dto : 1;' } ka0c05_tlep$r_tlber_bits;& O1 } ka0c05_tlep$r_tlber_overlay;* unsigned char ka0c05_tlep$b_f210 [60]; __union {) unsigned int ka0c05_tlep$l_tlcnr; __struct {2 unsigned ka0c05_tlep$v_tlcnr_cwdd : 1;2 unsigned ka0c05_tlep$v_tlcnr_crdd : 1;0 unsigned ka0c05_tlep$v_tlcnr_f1 : 1;2 unsigned ka0c05_tlep$v_tlcnr_dtod : 1;5 unsigned ka0c05_tlep$v_tlcnr_node_id : 4;2 unsigned ka0c05_tlep$v_tlcnr_vcnt : 4;3 unsigned ka0c05_ P1tlep$v_tlcnr_stf_a : 1;3 unsigned ka0c05_tlep$v_tlcnr_stf_b : 1;0 unsigned ka0c05_tlep$v_tlcnr_f2 : 6;4 unsigned ka0c05_tlep$v_tlcnr_halt_a : 1;4 unsigned ka0c05_tlep$v_tlcnr_halt_b : 1;3 unsigned ka0c05_tlep$v_tlcnr_fill3 : 8;2 unsigned ka0c05_tlep$v_tlcnr_nrst : 1;2 unsigned ka0c05_tlep$v_tlcnr_lofe : 1;' } ka0c05_tlep$r_tlcnr_bits;& } ka0c05_tlep$r_tlcnr_overlay;* unsigned char ka0c05_tleQ1p$b_f220 [60]; __union {) unsigned int ka0c05_tlep$l_tlvid; __struct {- unsigned ka0c05_tlep$v_vid_a : 4;- unsigned ka0c05_tlep$v_vid_b : 4;/ unsigned ka0c05_tlep$v_vid_f1 : 24;' } ka0c05_tlep$r_tlvid_bits;& } ka0c05_tlep$r_tlvid_overlay;+ unsigned char ka0c05_tlep$b_f230 [316]; __union {* unsigned int ka0c05_tlep$l_tlmmr0; __struct {6 unsigned ka0c05_tlep$v_tlmmr0_intmask : R12;1 unsigned ka0c05_tlep$v_tlmmr0_f1 : 2;6 unsigned ka0c05_tlep$v_tlmmr0_adrmask : 4;4 unsigned ka0c05_tlep$v_tlmmr0_intlv : 3;4 unsigned ka0c05_tlep$v_tlmmr0_sbank : 1;7 unsigned ka0c05_tlep$v_tlmmr0_address : 14;1 unsigned ka0c05_tlep$v_tlmmr0_f2 : 5;4 unsigned ka0c05_tlep$v_tlmmr0_valid : 1;( } ka0c05_tlep$r_tlmmr0_bits;' } ka0c05_tlep$r_tlmmr0_overlay;* unsigned char ka0c05_tlep$b_f240 [ S160]; __union {* unsigned int ka0c05_tlep$l_tlmmr1; __struct {6 unsigned ka0c05_tlep$v_tlmmr1_intmask : 2;1 unsigned ka0c05_tlep$v_tlmmr1_f1 : 2;6 unsigned ka0c05_tlep$v_tlmmr1_adrmask : 4;4 unsigned ka0c05_tlep$v_tlmmr1_intlv : 3;4 unsigned ka0c05_tlep$v_tlmmr1_sbank : 1;7 unsigned ka0c05_tlep$v_tlmmr1_address : 14;1 unsigned ka0c05_tlep$v_tlmmr1_f2 : 5;4 unsigned ka0c05_tlep$v_t T1lmmr1_valid : 1;( } ka0c05_tlep$r_tlmmr1_bits;' } ka0c05_tlep$r_tlmmr1_overlay;* unsigned char ka0c05_tlep$b_f250 [60]; __union {* unsigned int ka0c05_tlep$l_tlmmr2; __struct {6 unsigned ka0c05_tlep$v_tlmmr2_intmask : 2;1 unsigned ka0c05_tlep$v_tlmmr2_f1 : 2;6 unsigned ka0c05_tlep$v_tlmmr2_adrmask : 4;4 unsigned ka0c05_tlep$v_tlmmr2_intlv : 3;4 unsigned ka0c05_tlep$v_tlmmr2_sbank : 1;7 U1 unsigned ka0c05_tlep$v_tlmmr2_address : 14;1 unsigned ka0c05_tlep$v_tlmmr2_f2 : 5;4 unsigned ka0c05_tlep$v_tlmmr2_valid : 1;( } ka0c05_tlep$r_tlmmr2_bits;' } ka0c05_tlep$r_tlmmr2_overlay;* unsigned char ka0c05_tlep$b_f260 [60]; __union {* unsigned int ka0c05_tlep$l_tlmmr3; __struct {6 unsigned ka0c05_tlep$v_tlmmr3_intmask : 2;1 unsigned ka0c05_tlep$v_tlmmr3_f1 : 2;6 unsigned ka0c05_tl V1ep$v_tlmmr3_adrmask : 4;4 unsigned ka0c05_tlep$v_tlmmr3_intlv : 3;4 unsigned ka0c05_tlep$v_tlmmr3_sbank : 1;7 unsigned ka0c05_tlep$v_tlmmr3_address : 14;1 unsigned ka0c05_tlep$v_tlmmr3_f2 : 5;4 unsigned ka0c05_tlep$v_tlmmr3_valid : 1;( } ka0c05_tlep$r_tlmmr3_bits;' } ka0c05_tlep$r_tlmmr3_overlay;* unsigned char ka0c05_tlep$b_f270 [60]; __union {* unsigned int ka0c05_tlep$l_tlmmr4; __struct { W16 unsigned ka0c05_tlep$v_tlmmr4_intmask : 2;1 unsigned ka0c05_tlep$v_tlmmr4_f1 : 2;6 unsigned ka0c05_tlep$v_tlmmr4_adrmask : 4;4 unsigned ka0c05_tlep$v_tlmmr4_intlv : 3;4 unsigned ka0c05_tlep$v_tlmmr4_sbank : 1;7 unsigned ka0c05_tlep$v_tlmmr4_address : 14;1 unsigned ka0c05_tlep$v_tlmmr4_f2 : 5;4 unsigned ka0c05_tlep$v_tlmmr4_valid : 1;( } ka0c05_tlep$r_tlmmr4_bits;' } ka0c05_tlep$r_tl X1mmr4_overlay;* unsigned char ka0c05_tlep$b_f280 [60]; __union {* unsigned int ka0c05_tlep$l_tlmmr5; __struct {6 unsigned ka0c05_tlep$v_tlmmr5_intmask : 2;1 unsigned ka0c05_tlep$v_tlmmr5_f1 : 2;6 unsigned ka0c05_tlep$v_tlmmr5_adrmask : 4;4 unsigned ka0c05_tlep$v_tlmmr5_intlv : 3;4 unsigned ka0c05_tlep$v_tlmmr5_sbank : 1;7 unsigned ka0c05_tlep$v_tlmmr5_address : 14;1 unsigned ka0c05_tlep$v Y1_tlmmr5_f2 : 5;4 unsigned ka0c05_tlep$v_tlmmr5_valid : 1;( } ka0c05_tlep$r_tlmmr5_bits;' } ka0c05_tlep$r_tlmmr5_overlay;* unsigned char ka0c05_tlep$b_f290 [60]; __union {* unsigned int ka0c05_tlep$l_tlmmr6; __struct {6 unsigned ka0c05_tlep$v_tlmmr6_intmask : 2;1 unsigned ka0c05_tlep$v_tlmmr6_f1 : 2;6 unsigned ka0c05_tlep$v_tlmmr6_adrmask : 4;4 unsigned ka0c05_tlep$v_tlmmr6_intlv : 3;4 Z1 unsigned ka0c05_tlep$v_tlmmr6_sbank : 1;7 unsigned ka0c05_tlep$v_tlmmr6_address : 14;1 unsigned ka0c05_tlep$v_tlmmr6_f2 : 5;4 unsigned ka0c05_tlep$v_tlmmr6_valid : 1;( } ka0c05_tlep$r_tlmmr6_bits;' } ka0c05_tlep$r_tlmmr6_overlay;- unsigned char ka0c05_tlep$b_fill300 [60]; __union {* unsigned int ka0c05_tlep$l_tlmmr7; __struct {6 unsigned ka0c05_tlep$v_tlmmr7_intmask : 2;1 unsigned ka0 [1c05_tlep$v_tlmmr7_f1 : 2;6 unsigned ka0c05_tlep$v_tlmmr7_adrmask : 4;4 unsigned ka0c05_tlep$v_tlmmr7_intlv : 3;4 unsigned ka0c05_tlep$v_tlmmr7_sbank : 1;7 unsigned ka0c05_tlep$v_tlmmr7_address : 14;1 unsigned ka0c05_tlep$v_tlmmr7_f2 : 5;4 unsigned ka0c05_tlep$v_tlmmr7_valid : 1;( } ka0c05_tlep$r_tlmmr7_bits;' } ka0c05_tlep$r_tlmmr7_overlay;. unsigned char ka0c05_tlep$b_fill310 [700]; __union {* \1 unsigned int ka0c05_tlep$l_tlesr0; __struct {4 unsigned ka0c05_tlep$v_tlesr0_synd0 : 8;4 unsigned ka0c05_tlep$v_tlesr0_synd1 : 8;2 unsigned ka0c05_tlep$v_tlesr0_tde : 1;2 unsigned ka0c05_tlep$v_tlesr0_tce : 1;4 unsigned ka0c05_tlep$v_tlesr0_dvtce : 1;3 unsigned ka0c05_tlep$v_tlesr0_uecc : 1;4 unsigned ka0c05_tlep$v_tlesr0_cwecc : 1;4 unsigned ka0c05_tlep$v_tlesr0_crecc : 1;3 un ]1signed ka0c05_tlep$v_tlesr0_cpu0 : 1;3 unsigned ka0c05_tlep$v_tlesr0_cpu1 : 1;1 unsigned ka0c05_tlep$v_tlesr0_f1 : 7;5 unsigned ka0c05_tlep$v_tlesr0_lofsyn : 1;( } ka0c05_tlep$r_tlesr0_bits;' } ka0c05_tlep$r_tlesr0_overlay;- unsigned char ka0c05_tlep$b_fill320 [60]; __union {* unsigned int ka0c05_tlep$l_tlesr1; __struct {4 unsigned ka0c05_tlep$v_tlesr1_synd0 : 8;4 unsigned ka0c05_tlep$v_t ^1lesr1_synd1 : 8;2 unsigned ka0c05_tlep$v_tlesr1_tde : 1;2 unsigned ka0c05_tlep$v_tlesr1_tce : 1;4 unsigned ka0c05_tlep$v_tlesr1_dvtce : 1;3 unsigned ka0c05_tlep$v_tlesr1_uecc : 1;4 unsigned ka0c05_tlep$v_tlesr1_cwecc : 1;4 unsigned ka0c05_tlep$v_tlesr1_crecc : 1;3 unsigned ka0c05_tlep$v_tlesr1_cpu0 : 1;3 unsigned ka0c05_tlep$v_tlesr1_cpu1 : 1;1 unsigned ka0c05_tlep$v_tlesr1_f1 : 7;5 _1 unsigned ka0c05_tlep$v_tlesr1_lofsyn : 1;( } ka0c05_tlep$r_tlesr1_bits;' } ka0c05_tlep$r_tlesr1_overlay;- unsigned char ka0c05_tlep$b_fill330 [60]; __union {* unsigned int ka0c05_tlep$l_tlesr2; __struct {4 unsigned ka0c05_tlep$v_tlesr2_synd0 : 8;4 unsigned ka0c05_tlep$v_tlesr2_synd1 : 8;2 unsigned ka0c05_tlep$v_tlesr2_tde : 1;2 unsigned ka0c05_tlep$v_tlesr2_tce : 1;4 unsigned ka0c05_tlep `1$v_tlesr2_dvtce : 1;3 unsigned ka0c05_tlep$v_tlesr2_uecc : 1;4 unsigned ka0c05_tlep$v_tlesr2_cwecc : 1;4 unsigned ka0c05_tlep$v_tlesr2_crecc : 1;3 unsigned ka0c05_tlep$v_tlesr2_cpu0 : 1;3 unsigned ka0c05_tlep$v_tlesr2_cpu1 : 1;1 unsigned ka0c05_tlep$v_tlesr2_f1 : 7;5 unsigned ka0c05_tlep$v_tlesr2_lofsyn : 1;( } ka0c05_tlep$r_tlesr2_bits;' } ka0c05_tlep$r_tlesr2_overlay;- unsigned char ka0c a105_tlep$b_fill340 [60]; __union {* unsigned int ka0c05_tlep$l_tlesr3; __struct {4 unsigned ka0c05_tlep$v_tlesr3_synd0 : 8;4 unsigned ka0c05_tlep$v_tlesr3_synd1 : 8;2 unsigned ka0c05_tlep$v_tlesr3_tde : 1;2 unsigned ka0c05_tlep$v_tlesr3_tce : 1;4 unsigned ka0c05_tlep$v_tlesr3_dvtce : 1;3 unsigned ka0c05_tlep$v_tlesr3_uecc : 1;4 unsigned ka0c05_tlep$v_tlesr3_cwecc : 1;4 unsigned ka0 b1c05_tlep$v_tlesr3_crecc : 1;3 unsigned ka0c05_tlep$v_tlesr3_cpu0 : 1;3 unsigned ka0c05_tlep$v_tlesr3_cpu1 : 1;1 unsigned ka0c05_tlep$v_tlesr3_f1 : 7;5 unsigned ka0c05_tlep$v_tlesr3_lofsyn : 1;( } ka0c05_tlep$r_tlesr3_bits;' } ka0c05_tlep$r_tlesr3_overlay;/ unsigned char ka0c05_tlep$b_fill350 [2236]; __union {* unsigned int ka0c05_tlep$l_tldiag; __struct {4 unsigned ka0c05_tlep$v_tldiag_fr c1ign : 1;3 unsigned ka0c05_tlep$v_tldiag_dtwr : 1;3 unsigned ka0c05_tlep$v_tldiag_dtrd : 1;3 unsigned ka0c05_tlep$v_tldiag_dtcp : 1;2 unsigned ka0c05_tlep$v_tldiag_fvw : 1;2 unsigned ka0c05_tlep$v_tldiag_fae : 1;3 unsigned ka0c05_tlep$v_tldiag_fcbe : 1;3 unsigned ka0c05_tlep$v_tldiag_fdbe : 1;2 unsigned ka0c05_tlep$v_tldiag_fde : 4;2 unsigned ka0c05_tlep$v_tldiag_ftw : 1;7 unsign d1ed ka0c05_tlep$v_tldiag_asrt_flt : 1;7 unsigned ka0c05_tlep$v_tldiag_qwval_en : 1;4 unsigned ka0c05_tlep$v_tldiag_gslow : 1;2 unsigned ka0c05_tlep$v_tldiag_f1 : 16;( } ka0c05_tlep$r_tldiag_bits;' } ka0c05_tlep$r_tldiag_overlay;- unsigned char ka0c05_tlep$b_fill360 [60]; __union {+ unsigned int ka0c05_tlep$l_tldtagd; __struct {8 unsigned ka0c05_tlep$v_tldtagd_dtag_par : 1;: unsigned ka0c05_ e1tlep$v_tldtagd_dtag_data : 19;3 unsigned ka0c05_tlep$v_tldtagd_f1 : 12;) } ka0c05_tlep$r_tldtagd_bits;( } ka0c05_tlep$r_tldtagd_overlay;- unsigned char ka0c05_tlep$b_fill370 [60]; __union {+ unsigned int ka0c05_tlep$l_tldtags; __struct {7 unsigned ka0c05_tlep$v_tldtags_statpar : 1;5 unsigned ka0c05_tlep$v_tldtags_statd : 1;5 unsigned ka0c05_tlep$v_tldtags_stats : 1;5 unsigned ka0c05_tlep f1$v_tldtags_statv : 1;3 unsigned ka0c05_tlep$v_tldtags_f1 : 28;) } ka0c05_tlep$r_tldtags_bits;( } ka0c05_tlep$r_tldtags_overlay;- unsigned char ka0c05_tlep$b_fill380 [60]; __union {* unsigned int ka0c05_tlep$l_tlmcfg; __struct {7 unsigned ka0c05_tlep$v_tlmcfg_cpu0dsbl : 1;7 unsigned ka0c05_tlep$v_tlmcfg_cpu1dsbl : 1;6 unsigned ka0c05_tlep$v_tlmcfg_bc_size : 2;4 unsigned ka0c05_tlep$v_tlmcf g1g_lo_en : 1;6 unsigned ka0c05_tlep$v_tlmcfg_rm_size : 1;5 unsigned ka0c05_tlep$v_tlmcfg_bcidle : 4;7 unsigned ka0c05_tlep$v_tlmcfg_cq_entry : 3;7 unsigned ka0c05_tlep$v_tlmcfg_bq_entry : 3;7 unsigned ka0c05_tlep$v_tlmcfg_sys_dsbl : 1;7 unsigned ka0c05_tlep$v_tlmcfg_ev5_dsbl : 1;7 unsigned ka0c05_tlep$v_tlmcfg_flt_dsbl : 1;2 unsigned ka0c05_tlep$v_tlmcfg_f1 : 13;( } ka0c05_tlep$r_tlmcfg_bit h1s;' } ka0c05_tlep$r_tlmcfg_overlay;- unsigned char ka0c05_tlep$b_fill390 [60]; __union {, unsigned int ka0c05_tlep$l_tlimask0; __struct {9 unsigned ka0c05_tlep$v_tlimask0_duart0en : 1;9 unsigned ka0c05_tlep$v_tlimask0_ipl14_en : 1;9 unsigned ka0c05_tlep$v_tlimask0_ipl15_en : 1;9 unsigned ka0c05_tlep$v_tlimask0_ipl16_en : 1;9 unsigned ka0c05_tlep$v_tlimask0_ipl17_en : 1;6 unsigned ka0c05_ i1tlep$v_tlimask0_ip_en : 1;9 unsigned ka0c05_tlep$v_tlimask0_intim_en : 1;8 unsigned ka0c05_tlep$v_tlimask0_halt_en : 1;6 unsigned ka0c05_tlep$v_tlimask0_cp_en : 1;4 unsigned ka0c05_tlep$v_tlimask0_f1 : 23;* } ka0c05_tlep$r_tlimask0_bits;) } ka0c05_tlep$r_tlimask0_overlay;- unsigned char ka0c05_tlep$b_fill400 [60]; __union {, unsigned int ka0c05_tlep$l_tlimask1; __struct {9 unsigned ka0c05_tl j1ep$v_tlimask1_duart0en : 1;9 unsigned ka0c05_tlep$v_tlimask1_ipl14_en : 1;9 unsigned ka0c05_tlep$v_tlimask1_ipl15_en : 1;9 unsigned ka0c05_tlep$v_tlimask1_ipl16_en : 1;9 unsigned ka0c05_tlep$v_tlimask1_ipl17_en : 1;6 unsigned ka0c05_tlep$v_tlimask1_ip_en : 1;9 unsigned ka0c05_tlep$v_tlimask1_intim_en : 1;8 unsigned ka0c05_tlep$v_tlimask1_halt_en : 1;6 unsigned ka0c05_tlep$v_tlimask1_cp_en : 1;4 k1 unsigned ka0c05_tlep$v_tlimask1_f1 : 23;* } ka0c05_tlep$r_tlimask1_bits;) } ka0c05_tlep$r_tlimask1_overlay;- unsigned char ka0c05_tlep$b_fill410 [60]; __union {+ unsigned int ka0c05_tlep$l_tlisum0; __struct {9 unsigned ka0c05_tlep$v_tlisum0_duart0int : 1;9 unsigned ka0c05_tlep$v_tlisum0_ipl14_int : 1;9 unsigned ka0c05_tlep$v_tlisum0_ipl15_int : 1;9 unsigned ka0c05_tlep$v_tlisum0_ipl16_int : 1; l19 unsigned ka0c05_tlep$v_tlisum0_ipl17_int : 1;6 unsigned ka0c05_tlep$v_tlisum0_ip_int : 1;9 unsigned ka0c05_tlep$v_tlisum0_intim_int : 1;5 unsigned ka0c05_tlep$v_tlisum0_ipl14 : 5;5 unsigned ka0c05_tlep$v_tlisum0_ipl15 : 5;5 unsigned ka0c05_tlep$v_tlisum0_ipl16 : 5;5 unsigned ka0c05_tlep$v_tlisum0_ipl17 : 5;7 unsigned ka0c05_tlep$v_tlisum0_cp_halt : 1;4 unsigned ka0c05_tlep$v_tlisum0_hal m1t : 1;2 unsigned ka0c05_tlep$v_tlisum0_f1 : 3;) } ka0c05_tlep$r_tlisum0_bits;( } ka0c05_tlep$r_tlisum0_overlay;- unsigned char ka0c05_tlep$b_fill420 [60]; __union {+ unsigned int ka0c05_tlep$l_tlisum1; __struct {9 unsigned ka0c05_tlep$v_tlisum1_duart0int : 1;9 unsigned ka0c05_tlep$v_tlisum1_ipl14_int : 1;9 unsigned ka0c05_tlep$v_tlisum1_ipl15_int : 1;9 unsigned ka0c05_tlep$v_tlisum1_ipl16 n1_int : 1;9 unsigned ka0c05_tlep$v_tlisum1_ipl17_int : 1;6 unsigned ka0c05_tlep$v_tlisum1_ip_int : 1;9 unsigned ka0c05_tlep$v_tlisum1_intim_int : 1;5 unsigned ka0c05_tlep$v_tlisum1_ipl14 : 5;5 unsigned ka0c05_tlep$v_tlisum1_ipl15 : 5;5 unsigned ka0c05_tlep$v_tlisum1_ipl16 : 5;5 unsigned ka0c05_tlep$v_tlisum1_ipl17 : 5;7 unsigned ka0c05_tlep$v_tlisum1_cp_halt : 1;4 unsigned ka0c05_tlep$v_to1lisum1_halt : 1;2 unsigned ka0c05_tlep$v_tlisum1_f1 : 3;) } ka0c05_tlep$r_tlisum1_bits;( } ka0c05_tlep$r_tlisum1_overlay;- unsigned char ka0c05_tlep$b_fill430 [60]; __union {+ unsigned int ka0c05_tlep$l_tlcon00; __struct {3 unsigned ka0c05_tlep$v_tlcon00_f1 : 32;) } ka0c05_tlep$r_tlcon00_bits;( } ka0c05_tlep$r_tlcon00_overlay;- unsigned char ka0c05_tlep$b_fill440 [60]; __union {, unsign p1ed int ka0c05_tlep$l_tlcon00a; __struct {4 unsigned ka0c05_tlep$v_tlcon00a_f1 : 32;* } ka0c05_tlep$r_tlcon00a_bits;) } ka0c05_tlep$r_tlcon00a_overlay;- unsigned char ka0c05_tlep$b_fill450 [60]; __union {, unsigned int ka0c05_tlep$l_tlcon00b; __struct {4 unsigned ka0c05_tlep$v_tlcon00b_f1 : 32;* } ka0c05_tlep$r_tlcon00b_bits;) } ka0c05_tlep$r_tlcon00b_overlay;- unsigned char ka0c05_tlep$b_fillq1460 [60]; __union {, unsigned int ka0c05_tlep$l_tlcon00c; __struct {4 unsigned ka0c05_tlep$v_tlcon00c_f1 : 32;* } ka0c05_tlep$r_tlcon00c_bits;) } ka0c05_tlep$r_tlcon00c_overlay;- unsigned char ka0c05_tlep$b_fill470 [60]; __union {+ unsigned int ka0c05_tlep$l_tlcon10; __struct {3 unsigned ka0c05_tlep$v_tlcon10_f1 : 32;) } ka0c05_tlep$r_tlcon10_bits;( } ka0c05_tlep$r_tlcon10_overlar1y;- unsigned char ka0c05_tlep$b_fill480 [60]; __union {, unsigned int ka0c05_tlep$l_tlcon10a; __struct {4 unsigned ka0c05_tlep$v_tlcon10a_f1 : 32;* } ka0c05_tlep$r_tlcon10a_bits;) } ka0c05_tlep$r_tlcon10a_overlay;- unsigned char ka0c05_tlep$b_fill490 [60]; __union {, unsigned int ka0c05_tlep$l_tlcon10b; __struct {4 unsigned ka0c05_tlep$v_tlcon10b_f1 : 32;* } ka0c05_tlep$r_tlcon10b_bits;s1) } ka0c05_tlep$r_tlcon10b_overlay;- unsigned char ka0c05_tlep$b_fill500 [60]; __union {, unsigned int ka0c05_tlep$l_tlcon10c; __struct {4 unsigned ka0c05_tlep$v_tlcon10c_f1 : 32;* } ka0c05_tlep$r_tlcon10c_bits;) } ka0c05_tlep$r_tlcon10c_overlay;- unsigned char ka0c05_tlep$b_fill510 [60]; __union {+ unsigned int ka0c05_tlep$l_tlcon01; __struct {3 unsigned ka0c05_tlep$v_tlcon01_f1 : 32;)t1 } ka0c05_tlep$r_tlcon01_bits;( } ka0c05_tlep$r_tlcon01_overlay;- unsigned char ka0c05_tlep$b_fill520 [60]; __union {+ unsigned int ka0c05_tlep$l_tlcon11; __struct {3 unsigned ka0c05_tlep$v_tlcon11_f1 : 32;) } ka0c05_tlep$r_tlcon11_bits;( } ka0c05_tlep$r_tlcon11_overlay;. unsigned char ka0c05_tlep$b_fill530 [188]; __union {, unsigned int ka0c05_tlep$l_tlepaerr; __struct {8 unsi u1gned ka0c05_tlep$v_tlepaerr_e2mape0 : 1;8 unsigned ka0c05_tlep$v_tlepaerr_e2mape1 : 1;8 unsigned ka0c05_tlep$v_tlepaerr_m2aape0 : 1;8 unsigned ka0c05_tlep$v_tlepaerr_m2aape1 : 1;6 unsigned ka0c05_tlep$v_tlepaerr_dtdpe : 1;6 unsigned ka0c05_tlep$v_tlepaerr_dtspe : 1;7 unsigned ka0c05_tlep$v_tlepaerr_d2acpe : 1;8 unsigned ka0c05_tlep$v_tlepaerr_sysderr : 1;7 unsigned ka0c05_tlep$v_tlepaerr_sysflt : 1;7 v1 unsigned ka0c05_tlep$v_tlepaerr_rd_err : 2;7 unsigned ka0c05_tlep$v_tlepaerr_iboxto : 2;8 unsigned ka0c05_tlep$v_tlepaerr_rd_pend : 2;4 unsigned ka0c05_tlep$v_tlepaerr_nxm : 1;7 unsigned ka0c05_tlep$v_tlepaerr_no_ack : 2;4 unsigned ka0c05_tlep$v_tlepaerr_f1 : 14;* } ka0c05_tlep$r_tlepaerr_bits;) } ka0c05_tlep$r_tlepaerr_overlay;- unsigned char ka0c05_tlep$b_fill540 [60]; __union {, unsigned i w1nt ka0c05_tlep$l_tlepderr; __struct {7 unsigned ka0c05_tlep$v_tlepderr_a2dcpe : 1;8 unsigned ka0c05_tlep$v_tlepderr_d2dcpe0 : 1;5 unsigned ka0c05_tlep$v_tlepderr_gbto : 1;4 unsigned ka0c05_tlep$v_tlepderr_f1 : 29;* } ka0c05_tlep$r_tlepderr_bits;) } ka0c05_tlep$r_tlepderr_overlay;- unsigned char ka0c05_tlep$b_fill550 [60]; __union {, unsigned int ka0c05_tlep$l_tlepmerr; __struct {8 x1 unsigned ka0c05_tlep$v_tlepmerr_a2mape0 : 1;8 unsigned ka0c05_tlep$v_tlepmerr_a2mape1 : 1;7 unsigned ka0c05_tlep$v_tlepmerr_d2mcpe : 1;8 unsigned ka0c05_tlep$v_tlepmerr_d2dcpe1 : 1;8 unsigned ka0c05_tlep$v_tlepmerr_d2dcpe2 : 1;8 unsigned ka0c05_tlep$v_tlepmerr_d2dcpe3 : 1;8 unsigned ka0c05_tlep$v_tlepmerr_rststat : 1;4 unsigned ka0c05_tlep$v_tlepmerr_f1 : 25;* } ka0c05_tlep$r_tlepmerr_bits;) } ka y10c05_tlep$r_tlepmerr_overlay;- unsigned char ka0c05_tlep$b_fill560 [60]; __union {, unsigned int ka0c05_tlep$l_tlep_vmg; __struct {3 unsigned ka0c05_tlep$v_tlep_vmg_5p : 1;3 unsigned ka0c05_tlep$v_tlep_vmg_5m : 1;3 unsigned ka0c05_tlep$v_tlep_vmg_3p : 1;3 unsigned ka0c05_tlep$v_tlep_vmg_3m : 1;4 unsigned ka0c05_tlep$v_tlep_vmg_f1 : 28;* } ka0c05_tlep$r_tlep_vmg_bits;) } ka0c05_tlep$r_tlep z1_vmg_overlay;- unsigned char ka0c05_tlep$b_fill570 [60]; __union {+ unsigned int ka0c05_tlep$l_tldmcmd; __struct {8 unsigned ka0c05_tlep$v_tldmcmd_size_512 : 1;7 unsigned ka0c05_tlep$v_tldmcmd_size_1k : 1;7 unsigned ka0c05_tlep$v_tldmcmd_size_2k : 1;7 unsigned ka0c05_tlep$v_tldmcmd_size_4k : 1;7 unsigned ka0c05_tlep$v_tldmcmd_size_8k : 1;2 unsigned ka0c05_tlep$v_tldmcmd_f1 : 3;3 unsi {1gned ka0c05_tlep$v_tldmcmd_cmd : 2;2 unsigned ka0c05_tlep$v_tldmcmd_f2 : 1;5 unsigned ka0c05_tlep$v_tldmcmd_valid : 1;4 unsigned ka0c05_tlep$v_tldmcmd_rm_3 : 1;4 unsigned ka0c05_tlep$v_tldmcmd_rm_4 : 1;7 unsigned ka0c05_tlep$v_tldmcmd_rm_inlv : 1;5 unsigned ka0c05_tlep$v_tldmcmd_fill3 : 1;6 unsigned ka0c05_tlep$v_tldmcmd_cpu_id : 1;5 unsigned ka0c05_tlep$v_tldmcmd_fill4 : 3;7 unsigned ka0c0 |15_tlep$v_tldmcmd_in_prog : 1;4 unsigned ka0c05_tlep$v_tldmcmd_done : 1;6 unsigned ka0c05_tlep$v_tldmcmd_fill5 : 10;) } ka0c05_tlep$r_tldmcmd_bits;( } ka0c05_tlep$r_tldmcmd_overlay;. unsigned char ka0c05_tlep$b_fill580 [124]; __union {, unsigned int ka0c05_tlep$l_tldmadra; __struct {6 unsigned ka0c05_tlep$v_tldmadra_addr : 30;3 unsigned ka0c05_tlep$v_tldmadra_f1 : 2;* } ka0c05_tlep$r_tldmadra}1_bits;) } ka0c05_tlep$r_tldmadra_overlay;- unsigned char ka0c05_tlep$b_fill590 [60]; __union {, unsigned int ka0c05_tlep$l_tldmadrb; __struct {6 unsigned ka0c05_tlep$v_tldmadrb_addr : 30;3 unsigned ka0c05_tlep$v_tldmadrb_f1 : 2;* } ka0c05_tlep$r_tldmadrb_bits;) } ka0c05_tlep$r_tldmadrb_overlay;. unsigned char ka0c05_tlep$b_fill600 [316]; __union {, unsigned int ka0c05_tlep$l_tlpm_cmd; __stru ~1ct {7 unsigned ka0c05_tlep$v_tlpm_cmd_cpunum : 1;8 unsigned ka0c05_tlep$v_tlpm_cmd_set_sel : 2;6 unsigned ka0c05_tlep$v_tlpm_cmd_valid : 1;9 unsigned ka0c05_tlep$v_tlpm_cmd_read_set : 1;3 unsigned ka0c05_tlep$v_tlpm_cmd_f1 : 6;8 unsigned ka0c05_tlep$v_tlpm_cmd_ovrf_en : 1;8 unsigned ka0c05_tlep$v_tlpm_cmd_tot_cyc : 1;8 unsigned ka0c05_tlep$v_tlpm_cmd_ev5_lat : 1;7 unsigned ka0c05_tlep$v_tlp 1m_cmd_rd_lat : 1;8 unsigned ka0c05_tlep$v_tlpm_cmd_sys_own : 1;3 unsigned ka0c05_tlep$v_tlpm_cmd_f2 : 1;5 unsigned ka0c05_tlep$v_tlpm_cmd_lock : 1;3 unsigned ka0c05_tlep$v_tlpm_cmd_mb : 1;7 unsigned ka0c05_tlep$v_tlpm_cmd_sd_tot : 1;7 unsigned ka0c05_tlep$v_tlpm_cmd_sd_ack : 1;7 unsigned ka0c05_tlep$v_tlpm_cmd_rd_csr : 1;3 unsigned ka0c05_tlep$v_tlpm_cmd_rd : 1;7 unsigned ka0c05_tlep$v_t 1lpm_cmd_rd_mod : 1;7 unsigned ka0c05_tlep$v_tlpm_cmd_rd_stc : 1;4 unsigned ka0c05_tlep$v_tlpm_cmd_vic : 1;7 unsigned ka0c05_tlep$v_tlpm_cmd_wr_csr : 1;3 unsigned ka0c05_tlep$v_tlpm_cmd_wr : 1;8 unsigned ka0c05_tlep$v_tlpm_cmd_wr_lock : 1;6 unsigned ka0c05_tlep$v_tlpm_cmd_inval : 1;8 unsigned ka0c05_tlep$v_tlpm_cmd_set_shr : 1;8 unsigned ka0c05_tlep$v_tlpm_cmd_rd_dirt : 1;* } ka0c05_tlep$r_tl1pm_cmd_bits;) } ka0c05_tlep$r_tlpm_cmd_overlay;- unsigned char ka0c05_tlep$b_fill610 [60]; __union {3 unsigned int ka0c05_tlep$l_tlpm_tot_cycles; __struct {; unsigned ka0c05_tlep$v_tlpm_tot_cycles_f1 : 32;1 } ka0c05_tlep$r_tlpm_tot_cycles_bits;- } ka0c05_tlep$r_tlpm_tot_cycles_over;- unsigned char ka0c05_tlep$b_fill620 [60]; __union {0 unsigned int ka0c05_tlep$l_tlpm_ev5_lat; __struct {8 1 unsigned ka0c05_tlep$v_tlpm_ev5_lat_f1 : 32;. } ka0c05_tlep$r_tlpm_ev5_lat_bits;- } ka0c05_tlep$r_tlpm_ev5_lat_overlay;- unsigned char ka0c05_tlep$b_fill630 [60]; __union {1 unsigned int ka0c05_tlep$l_tlpm_read_lat; __struct {9 unsigned ka0c05_tlep$v_tlpm_read_lat_f1 : 32;/ } ka0c05_tlep$r_tlpm_read_lat_bits;- } ka0c05_tlep$r_tlpm_read_lat_overla;- unsigned char ka0c05_tlep$b_fill640 [60]; __union {. 1 unsigned int ka0c05_tlep$l_tlpm_owner; __struct {6 unsigned ka0c05_tlep$v_tlpm_owner_f1 : 32;, } ka0c05_tlep$r_tlpm_owner_bits;+ } ka0c05_tlep$r_tlpm_owner_overlay;- unsigned char ka0c05_tlep$b_fill650 [60]; __union {- unsigned int ka0c05_tlep$l_tlpm_silo; __struct {5 unsigned ka0c05_tlep$v_tlpm_silo_f1 : 32;+ } ka0c05_tlep$r_tlpm_silo_bits;* } ka0c05_tlep$r_tlpm_silo_overlay;- unsign1ed char ka0c05_tlep$b_fill660 [60]; __union {- unsigned int ka0c05_tlep$l_tlpm_lock; __struct {5 unsigned ka0c05_tlep$v_tlpm_lock_f1 : 32;+ } ka0c05_tlep$r_tlpm_lock_bits;* } ka0c05_tlep$r_tlpm_lock_overlay;- unsigned char ka0c05_tlep$b_fill670 [60]; __union {+ unsigned int ka0c05_tlep$l_tlpm_mb; __struct {3 unsigned ka0c05_tlep$v_tlpm_mb_f1 : 32;) } ka0c05_tlep$r_tlpm_mb_bits;( 1 } ka0c05_tlep$r_tlpm_mb_overlay;- unsigned char ka0c05_tlep$b_fill680 [60]; __union {+ unsigned int ka0c05_tlep$l_tlpm_sd; __struct {3 unsigned ka0c05_tlep$v_tlpm_sd_f1 : 32;) } ka0c05_tlep$r_tlpm_sd_bits;( } ka0c05_tlep$r_tlpm_sd_overlay;- unsigned char ka0c05_tlep$b_fill690 [60]; __union {/ unsigned int ka0c05_tlep$l_tlpm_sd_ack; __struct {7 unsigned ka0c05_tlep$v_tlpm_sd_ack_f1 : 32;- 1 } ka0c05_tlep$r_tlpm_sd_ack_bits;, } ka0c05_tlep$r_tlpm_sd_ack_overlay;- unsigned char ka0c05_tlep$b_fill700 [60]; __union {/ unsigned int ka0c05_tlep$l_tlpm_rd_csr; __struct {7 unsigned ka0c05_tlep$v_tlpm_rd_csr_f1 : 32;- } ka0c05_tlep$r_tlpm_rd_csr_bits;, } ka0c05_tlep$r_tlpm_rd_csr_overlay;- unsigned char ka0c05_tlep$b_fill710 [60]; __union {0 unsigned int ka0c05_tlep$l_tlpm_rd_miss; __stru 1ct {8 unsigned ka0c05_tlep$v_tlpm_rd_miss_f1 : 32;. } ka0c05_tlep$r_tlpm_rd_miss_bits;- } ka0c05_tlep$r_tlpm_rd_miss_overlay;- unsigned char ka0c05_tlep$b_fill720 [60]; __union {/ unsigned int ka0c05_tlep$l_tlpm_rd_mod; __struct {7 unsigned ka0c05_tlep$v_tlpm_rd_mod_f1 : 32;- } ka0c05_tlep$r_tlpm_rd_mod_bits;, } ka0c05_tlep$r_tlpm_rd_mod_overlay;- unsigned char ka0c05_tlep$b_fill730 [60]; __un 1ion {/ unsigned int ka0c05_tlep$l_tlpm_rd_stc; __struct {7 unsigned ka0c05_tlep$v_tlpm_rd_stc_f1 : 32;- } ka0c05_tlep$r_tlpm_rd_stc_bits;, } ka0c05_tlep$r_tlpm_rd_stc_overlay;- unsigned char ka0c05_tlep$b_fill740 [60]; __union {/ unsigned int ka0c05_tlep$l_tlpm_victim; __struct {7 unsigned ka0c05_tlep$v_tlpm_victim_f1 : 32;- } ka0c05_tlep$r_tlpm_victim_bits;, } ka0c05_tlep$r_tlpm_vic1tim_overlay;- unsigned char ka0c05_tlep$b_fill750 [60]; __union {/ unsigned int ka0c05_tlep$l_tlpm_wr_csr; __struct {7 unsigned ka0c05_tlep$v_tlpm_wr_csr_f1 : 32;- } ka0c05_tlep$r_tlpm_wr_csr_bits;, } ka0c05_tlep$r_tlpm_wr_csr_overlay;- unsigned char ka0c05_tlep$b_fill760 [60]; __union {+ unsigned int ka0c05_tlep$l_tlpm_wr; __struct {3 unsigned ka0c05_tlep$v_tlpm_wr_f1 : 32;) } ka0c105_tlep$r_tlpm_wr_bits;( } ka0c05_tlep$r_tlpm_wr_overlay;- unsigned char ka0c05_tlep$b_fill770 [60]; __union {0 unsigned int ka0c05_tlep$l_tlpm_wr_lock; __struct {8 unsigned ka0c05_tlep$v_tlpm_wr_lock_f1 : 32;. } ka0c05_tlep$r_tlpm_wr_lock_bits;- } ka0c05_tlep$r_tlpm_wr_lock_overlay;- unsigned char ka0c05_tlep$b_fill780 [60]; __union {. unsigned int ka0c05_tlep$l_tlpm_inval; __struct {6 un 1signed ka0c05_tlep$v_tlpm_inval_f1 : 32;, } ka0c05_tlep$r_tlpm_inval_bits;+ } ka0c05_tlep$r_tlpm_inval_overlay;- unsigned char ka0c05_tlep$b_fill790 [60]; __union {/ unsigned int ka0c05_tlep$l_tlpm_s_shrd; __struct {7 unsigned ka0c05_tlep$v_tlpm_s_shrd_f1 : 32;- } ka0c05_tlep$r_tlpm_s_shrd_bits;, } ka0c05_tlep$r_tlpm_s_shrd_overlay;- unsigned char ka0c05_tlep$b_fill800 [60]; __union {+ unsigned int 1 ka0c05_tlep$l_tlpm_rd; __struct {3 unsigned ka0c05_tlep$v_tlpm_rd_f1 : 32;) } ka0c05_tlep$r_tlpm_rd_bits;( } ka0c05_tlep$r_tlpm_rd_overlay;- unsigned char ka0c05_tlep$b_fill810 [60]; __union {. unsigned int ka0c05_tlep$l_tlpm_asilo; __struct {6 unsigned ka0c05_tlep$v_tlpm_asilo_f1 : 32;, } ka0c05_tlep$r_tlpm_asilo_bits;+ } ka0c05_tlep$r_tlpm_asilo_overlay;- unsigned char ka0c05_tlep$b_fill 1820 [60]; __union {, unsigned int ka0c05_tlep$l_rm_reg0a; __struct {5 unsigned ka0c05_tlep$v_rm_reg0a_aext : 4;3 unsigned ka0c05_tlep$v_rm_reg0a_f1 : 4;7 unsigned ka0c05_tlep$v_rm_reg0a_baddr : 20;3 unsigned ka0c05_tlep$v_rm_reg0a_f2 : 3;6 unsigned ka0c05_tlep$v_rm_reg0a_valid : 1;* } ka0c05_tlep$r_rm_reg0a_bits;) } ka0c05_tlep$r_rm_reg0a_overlay;- unsigned char ka0c05_tlep$b_fill830 [60] 1; __union {, unsigned int ka0c05_tlep$l_rm_reg0b; __struct {5 unsigned ka0c05_tlep$v_rm_reg0b_aext : 4;3 unsigned ka0c05_tlep$v_rm_reg0b_f1 : 4;7 unsigned ka0c05_tlep$v_rm_reg0b_baddr : 20;3 unsigned ka0c05_tlep$v_rm_reg0b_f2 : 3;6 unsigned ka0c05_tlep$v_rm_reg0b_valid : 1;* } ka0c05_tlep$r_rm_reg0b_bits;) } ka0c05_tlep$r_rm_reg0b_overlay;- unsigned char ka0c05_tlep$b_fill840 [60]; 1__union {, unsigned int ka0c05_tlep$l_rm_reg1a; __struct {5 unsigned ka0c05_tlep$v_rm_reg1a_aext : 4;3 unsigned ka0c05_tlep$v_rm_reg1a_f1 : 4;7 unsigned ka0c05_tlep$v_rm_reg1a_baddr : 20;3 unsigned ka0c05_tlep$v_rm_reg1a_f2 : 3;6 unsigned ka0c05_tlep$v_rm_reg1a_valid : 1;* } ka0c05_tlep$r_rm_reg1a_bits;) } ka0c05_tlep$r_rm_reg1a_overlay;- unsigned char ka0c05_tlep$b_fill850 [60]; __union 1 {, unsigned int ka0c05_tlep$l_rm_reg1b; __struct {5 unsigned ka0c05_tlep$v_rm_reg1b_aext : 4;3 unsigned ka0c05_tlep$v_rm_reg1b_f1 : 4;7 unsigned ka0c05_tlep$v_rm_reg1b_baddr : 20;3 unsigned ka0c05_tlep$v_rm_reg1b_f2 : 3;6 unsigned ka0c05_tlep$v_rm_reg1b_valid : 1;* } ka0c05_tlep$r_rm_reg1b_bits;) } ka0c05_tlep$r_rm_reg1b_overlay;. unsigned char ka0c05_tlep$b_fill860 [316]; } KA0C05_TLEP;1 #if !defined(__VAXC)K#define ka0c05_tlep$l_tldev ka0c05_tlep$r_tldev_overlay.ka0c05_tlep$l_tldevp#define ka0c05_tlep$v_tldev_dtype ka0c05_tlep$r_tldev_overlay.ka0c05_tlep$r_tldev_bits.ka0c05_tlep$v_tldev_dtypep#define ka0c05_tlep$v_tldev_swrev ka0c05_tlep$r_tldev_overlay.ka0c05_tlep$r_tldev_bits.ka0c05_tlep$v_tldev_swrevp#define ka0c05_tlep$v_tldev_hwrev ka0c05_tlep$r_tldev_overlay.ka0c05_tlep$r_tldev_bits.ka0c05_tlep$v_tldev_hwrevK#define ka0c05_tlep$l_tlber ka0c05_tlep$r_tlber_overlay.ka0c105_tlep$l_tlbern#define ka0c05_tlep$v_tlber_atce ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_atcel#define ka0c05_tlep$v_tlber_ape ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_apel#define ka0c05_tlep$v_tlber_bbe ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_bben#define ka0c05_tlep$v_tlber_lkto ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_lktol#define ka0c05_tlep$v_tlber_nae ka0c05_tlep$1r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_naen#define ka0c05_tlep$v_tlber_rtce ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_rtcer#define ka0c05_tlep$v_tlber_acktce ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_acktcen#define ka0c05_tlep$v_tlber_mmre ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_mmren#define ka0c05_tlep$v_tlber_fnae ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_1tlber_fnaep#define ka0c05_tlep$v_tlber_reqde ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_reqden#define ka0c05_tlep$v_tlber_atde ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_atdel#define ka0c05_tlep$v_tlber_ude ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_uden#define ka0c05_tlep$v_tlber_cwde ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_cwden#define ka0c05_tlep$v_tlber_crde ka0c05_tlep$r1_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_crdel#define ka0c05_tlep$v_tlber_ds0 ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_ds0l#define ka0c05_tlep$v_tlber_ds1 ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_ds1l#define ka0c05_tlep$v_tlber_ds2 ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_ds2l#define ka0c05_tlep$v_tlber_ds3 ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_ds3n1#define ka0c05_tlep$v_tlber_dtde ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_dtdep#define ka0c05_tlep$v_tlber_fdtce ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_fdtcep#define ka0c05_tlep$v_tlber_uacke ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_uackep#define ka0c05_tlep$v_tlber_abtce ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_abtcep#define ka0c05_tlep$v_tlber_dctce ka0c05_tlep$r_tlbe1r_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_dctcen#define ka0c05_tlep$v_tlber_seqe ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_seqel#define ka0c05_tlep$v_tlber_dse ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_dsel#define ka0c05_tlep$v_tlber_dto ka0c05_tlep$r_tlber_overlay.ka0c05_tlep$r_tlber_bits.ka0c05_tlep$v_tlber_dtoK#define ka0c05_tlep$l_tlcnr ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$l_tlcnrn#define ka0c05_tlep$v_tlcnr_cwdd k1a0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_cwddn#define ka0c05_tlep$v_tlcnr_crdd ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_crddn#define ka0c05_tlep$v_tlcnr_dtod ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_dtodt#define ka0c05_tlep$v_tlcnr_node_id ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_node_idn#define ka0c05_tlep$v_tlcnr_vcnt ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.1ka0c05_tlep$v_tlcnr_vcntp#define ka0c05_tlep$v_tlcnr_stf_a ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_stf_ap#define ka0c05_tlep$v_tlcnr_stf_b ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_stf_br#define ka0c05_tlep$v_tlcnr_halt_a ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_halt_ar#define ka0c05_tlep$v_tlcnr_halt_b ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_halt_bn#define ka0c05_tlep$1v_tlcnr_nrst ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_nrstn#define ka0c05_tlep$v_tlcnr_lofe ka0c05_tlep$r_tlcnr_overlay.ka0c05_tlep$r_tlcnr_bits.ka0c05_tlep$v_tlcnr_lofeK#define ka0c05_tlep$l_tlvid ka0c05_tlep$r_tlvid_overlay.ka0c05_tlep$l_tlvidd#define ka0c05_tlep$v_vid_a ka0c05_tlep$r_tlvid_overlay.ka0c05_tlep$r_tlvid_bits.ka0c05_tlep$v_vid_ad#define ka0c05_tlep$v_vid_b ka0c05_tlep$r_tlvid_overlay.ka0c05_tlep$r_tlvid_bits.ka0c05_tlep$v_vid_bN#define ka0c05_tlep$1l_tlmmr0 ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$l_tlmmr0x#define ka0c05_tlep$v_tlmmr0_intmask ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr0_bits.ka0c05_tlep$v_tlmmr0_intmaskx#define ka0c05_tlep$v_tlmmr0_adrmask ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr0_bits.ka0c05_tlep$v_tlmmr0_adrmaskt#define ka0c05_tlep$v_tlmmr0_intlv ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr0_bits.ka0c05_tlep$v_tlmmr0_intlvt#define ka0c05_tlep$v_tlmmr0_sbank ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr01_bits.ka0c05_tlep$v_tlmmr0_sbankx#define ka0c05_tlep$v_tlmmr0_address ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr0_bits.ka0c05_tlep$v_tlmmr0_addresst#define ka0c05_tlep$v_tlmmr0_valid ka0c05_tlep$r_tlmmr0_overlay.ka0c05_tlep$r_tlmmr0_bits.ka0c05_tlep$v_tlmmr0_validN#define ka0c05_tlep$l_tlmmr1 ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$l_tlmmr1x#define ka0c05_tlep$v_tlmmr1_intmask ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_intmaskx#define ka0c05_tlep$v_tlmmr1_a1drmask ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_adrmaskt#define ka0c05_tlep$v_tlmmr1_intlv ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_intlvt#define ka0c05_tlep$v_tlmmr1_sbank ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_sbankx#define ka0c05_tlep$v_tlmmr1_address ka0c05_tlep$r_tlmmr1_overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_addresst#define ka0c05_tlep$v_tlmmr1_valid ka0c05_tlep$r_tlmmr1_1overlay.ka0c05_tlep$r_tlmmr1_bits.ka0c05_tlep$v_tlmmr1_validN#define ka0c05_tlep$l_tlmmr2 ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$l_tlmmr2x#define ka0c05_tlep$v_tlmmr2_intmask ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_intmaskx#define ka0c05_tlep$v_tlmmr2_adrmask ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_adrmaskt#define ka0c05_tlep$v_tlmmr2_intlv ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_intlvt#d1efine ka0c05_tlep$v_tlmmr2_sbank ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_sbankx#define ka0c05_tlep$v_tlmmr2_address ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_addresst#define ka0c05_tlep$v_tlmmr2_valid ka0c05_tlep$r_tlmmr2_overlay.ka0c05_tlep$r_tlmmr2_bits.ka0c05_tlep$v_tlmmr2_validN#define ka0c05_tlep$l_tlmmr3 ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$l_tlmmr3x#define ka0c05_tlep$v_tlmmr3_intmask ka0c05_tlep$r_tlmmr3_overlay.ka0c105_tlep$r_tlmmr3_bits.ka0c05_tlep$v_tlmmr3_intmaskx#define ka0c05_tlep$v_tlmmr3_adrmask ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$r_tlmmr3_bits.ka0c05_tlep$v_tlmmr3_adrmaskt#define ka0c05_tlep$v_tlmmr3_intlv ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$r_tlmmr3_bits.ka0c05_tlep$v_tlmmr3_intlvt#define ka0c05_tlep$v_tlmmr3_sbank ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$r_tlmmr3_bits.ka0c05_tlep$v_tlmmr3_sbankx#define ka0c05_tlep$v_tlmmr3_address ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$r_tlmmr3_bits.ka0c105_tlep$v_tlmmr3_addresst#define ka0c05_tlep$v_tlmmr3_valid ka0c05_tlep$r_tlmmr3_overlay.ka0c05_tlep$r_tlmmr3_bits.ka0c05_tlep$v_tlmmr3_validN#define ka0c05_tlep$l_tlmmr4 ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$l_tlmmr4x#define ka0c05_tlep$v_tlmmr4_intmask ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_intmaskx#define ka0c05_tlep$v_tlmmr4_adrmask ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_adrmaskt#define ka0c05_tlep$v_tlmmr4_intlv ka01c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_intlvt#define ka0c05_tlep$v_tlmmr4_sbank ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_sbankx#define ka0c05_tlep$v_tlmmr4_address ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_addresst#define ka0c05_tlep$v_tlmmr4_valid ka0c05_tlep$r_tlmmr4_overlay.ka0c05_tlep$r_tlmmr4_bits.ka0c05_tlep$v_tlmmr4_validN#define ka0c05_tlep$l_tlmmr5 ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tle1p$l_tlmmr5x#define ka0c05_tlep$v_tlmmr5_intmask ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_intmaskx#define ka0c05_tlep$v_tlmmr5_adrmask ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_adrmaskt#define ka0c05_tlep$v_tlmmr5_intlv ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_intlvt#define ka0c05_tlep$v_tlmmr5_sbank ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_sbankx#define ka0c051_tlep$v_tlmmr5_address ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_addresst#define ka0c05_tlep$v_tlmmr5_valid ka0c05_tlep$r_tlmmr5_overlay.ka0c05_tlep$r_tlmmr5_bits.ka0c05_tlep$v_tlmmr5_validN#define ka0c05_tlep$l_tlmmr6 ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$l_tlmmr6x#define ka0c05_tlep$v_tlmmr6_intmask ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$r_tlmmr6_bits.ka0c05_tlep$v_tlmmr6_intmaskx#define ka0c05_tlep$v_tlmmr6_adrmask ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$1r_tlmmr6_bits.ka0c05_tlep$v_tlmmr6_adrmaskt#define ka0c05_tlep$v_tlmmr6_intlv ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$r_tlmmr6_bits.ka0c05_tlep$v_tlmmr6_intlvt#define ka0c05_tlep$v_tlmmr6_sbank ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$r_tlmmr6_bits.ka0c05_tlep$v_tlmmr6_sbankx#define ka0c05_tlep$v_tlmmr6_address ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$r_tlmmr6_bits.ka0c05_tlep$v_tlmmr6_addresst#define ka0c05_tlep$v_tlmmr6_valid ka0c05_tlep$r_tlmmr6_overlay.ka0c05_tlep$r_tlmmr6_bits.ka0c05_tlep$v_1tlmmr6_validN#define ka0c05_tlep$l_tlmmr7 ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$l_tlmmr7x#define ka0c05_tlep$v_tlmmr7_intmask ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_intmaskx#define ka0c05_tlep$v_tlmmr7_adrmask ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_adrmaskt#define ka0c05_tlep$v_tlmmr7_intlv ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_intlvt#define ka0c05_tlep$v_tlmmr7_sbank ka0c05_tlep$r_t1lmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_sbankx#define ka0c05_tlep$v_tlmmr7_address ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_addresst#define ka0c05_tlep$v_tlmmr7_valid ka0c05_tlep$r_tlmmr7_overlay.ka0c05_tlep$r_tlmmr7_bits.ka0c05_tlep$v_tlmmr7_validN#define ka0c05_tlep$l_tlesr0 ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$l_tlesr0t#define ka0c05_tlep$v_tlesr0_synd0 ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_synd0t1#define ka0c05_tlep$v_tlesr0_synd1 ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_synd1p#define ka0c05_tlep$v_tlesr0_tde ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_tdep#define ka0c05_tlep$v_tlesr0_tce ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_tcet#define ka0c05_tlep$v_tlesr0_dvtce ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_dvtcer#define ka0c05_tlep$v_tlesr0_uecc ka0c05_t1lep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_uecct#define ka0c05_tlep$v_tlesr0_cwecc ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_cwecct#define ka0c05_tlep$v_tlesr0_crecc ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_creccr#define ka0c05_tlep$v_tlesr0_cpu0 ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_cpu0r#define ka0c05_tlep$v_tlesr0_cpu1 ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tle1sr0_bits.ka0c05_tlep$v_tlesr0_cpu1v#define ka0c05_tlep$v_tlesr0_lofsyn ka0c05_tlep$r_tlesr0_overlay.ka0c05_tlep$r_tlesr0_bits.ka0c05_tlep$v_tlesr0_lofsynN#define ka0c05_tlep$l_tlesr1 ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$l_tlesr1t#define ka0c05_tlep$v_tlesr1_synd0 ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_synd0t#define ka0c05_tlep$v_tlesr1_synd1 ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_synd1p#define ka0c05_tlep$v_tlesr1_tde k1a0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_tdep#define ka0c05_tlep$v_tlesr1_tce ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_tcet#define ka0c05_tlep$v_tlesr1_dvtce ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_dvtcer#define ka0c05_tlep$v_tlesr1_uecc ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_uecct#define ka0c05_tlep$v_tlesr1_cwecc ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_1tlesr1_bits.ka0c05_tlep$v_tlesr1_cwecct#define ka0c05_tlep$v_tlesr1_crecc ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_creccr#define ka0c05_tlep$v_tlesr1_cpu0 ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_cpu0r#define ka0c05_tlep$v_tlesr1_cpu1 ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_cpu1v#define ka0c05_tlep$v_tlesr1_lofsyn ka0c05_tlep$r_tlesr1_overlay.ka0c05_tlep$r_tlesr1_bits.ka0c05_tlep$v_tlesr1_lofs1ynN#define ka0c05_tlep$l_tlesr2 ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$l_tlesr2t#define ka0c05_tlep$v_tlesr2_synd0 ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_synd0t#define ka0c05_tlep$v_tlesr2_synd1 ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_synd1p#define ka0c05_tlep$v_tlesr2_tde ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_tdep#define ka0c05_tlep$v_tlesr2_tce ka0c05_tlep$r_tlesr2_overlay.ka0c05_tle1p$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_tcet#define ka0c05_tlep$v_tlesr2_dvtce ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_dvtcer#define ka0c05_tlep$v_tlesr2_uecc ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_uecct#define ka0c05_tlep$v_tlesr2_cwecc ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_cwecct#define ka0c05_tlep$v_tlesr2_crecc ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_c1reccr#define ka0c05_tlep$v_tlesr2_cpu0 ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_cpu0r#define ka0c05_tlep$v_tlesr2_cpu1 ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_cpu1v#define ka0c05_tlep$v_tlesr2_lofsyn ka0c05_tlep$r_tlesr2_overlay.ka0c05_tlep$r_tlesr2_bits.ka0c05_tlep$v_tlesr2_lofsynN#define ka0c05_tlep$l_tlesr3 ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$l_tlesr3t#define ka0c05_tlep$v_tlesr3_synd0 ka0c05_tlep$r_tlesr3_overlay.ka0c105_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_synd0t#define ka0c05_tlep$v_tlesr3_synd1 ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_synd1p#define ka0c05_tlep$v_tlesr3_tde ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_tdep#define ka0c05_tlep$v_tlesr3_tce ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_tcet#define ka0c05_tlep$v_tlesr3_dvtce ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr31_dvtcer#define ka0c05_tlep$v_tlesr3_uecc ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_uecct#define ka0c05_tlep$v_tlesr3_cwecc ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_cwecct#define ka0c05_tlep$v_tlesr3_crecc ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_creccr#define ka0c05_tlep$v_tlesr3_cpu0 ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_cpu0r#define ka0c05_tlep$v_tlesr3_c1pu1 ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_cpu1v#define ka0c05_tlep$v_tlesr3_lofsyn ka0c05_tlep$r_tlesr3_overlay.ka0c05_tlep$r_tlesr3_bits.ka0c05_tlep$v_tlesr3_lofsynN#define ka0c05_tlep$l_tldiag ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$l_tldiagt#define ka0c05_tlep$v_tldiag_frign ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_frignr#define ka0c05_tlep$v_tldiag_dtwr ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v1_tldiag_dtwrr#define ka0c05_tlep$v_tldiag_dtrd ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_dtrdr#define ka0c05_tlep$v_tldiag_dtcp ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_dtcpp#define ka0c05_tlep$v_tldiag_fvw ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_fvwp#define ka0c05_tlep$v_tldiag_fae ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_faer#define ka0c05_tlep$v_tldiag_fcb1e ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_fcber#define ka0c05_tlep$v_tldiag_fdbe ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_fdbep#define ka0c05_tlep$v_tldiag_fde ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_fdep#define ka0c05_tlep$v_tldiag_ftw ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_ftwz#define ka0c05_tlep$v_tldiag_asrt_flt ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep1$r_tldiag_bits.ka0c05_tlep$v_tldiag_asrt_fltz#define ka0c05_tlep$v_tldiag_qwval_en ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_qwval_ent#define ka0c05_tlep$v_tldiag_gslow ka0c05_tlep$r_tldiag_overlay.ka0c05_tlep$r_tldiag_bits.ka0c05_tlep$v_tldiag_gslowQ#define ka0c05_tlep$l_tldtagd ka0c05_tlep$r_tldtagd_overlay.ka0c05_tlep$l_tldtagd~#define ka0c05_tlep$v_tldtagd_dtag_par ka0c05_tlep$r_tldtagd_overlay.ka0c05_tlep$r_tldtagd_bits.ka0c05_tlep$v_tldtagd_dtag_par#defin1e ka0c05_tlep$v_tldtagd_dtag_data ka0c05_tlep$r_tldtagd_overlay.ka0c05_tlep$r_tldtagd_bits.ka0c05_tlep$v_tldtagd_dtag_dataQ#define ka0c05_tlep$l_tldtags ka0c05_tlep$r_tldtags_overlay.ka0c05_tlep$l_tldtags|#define ka0c05_tlep$v_tldtags_statpar ka0c05_tlep$r_tldtags_overlay.ka0c05_tlep$r_tldtags_bits.ka0c05_tlep$v_tldtags_statparx#define ka0c05_tlep$v_tldtags_statd ka0c05_tlep$r_tldtags_overlay.ka0c05_tlep$r_tldtags_bits.ka0c05_tlep$v_tldtags_statdx#define ka0c05_tlep$v_tldtags_stats ka0c05_tlep$r_1tldtags_overlay.ka0c05_tlep$r_tldtags_bits.ka0c05_tlep$v_tldtags_statsx#define ka0c05_tlep$v_tldtags_statv ka0c05_tlep$r_tldtags_overlay.ka0c05_tlep$r_tldtags_bits.ka0c05_tlep$v_tldtags_statvN#define ka0c05_tlep$l_tlmcfg ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$l_tlmcfgz#define ka0c05_tlep$v_tlmcfg_cpu0dsbl ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_cpu0dsblz#define ka0c05_tlep$v_tlmcfg_cpu1dsbl ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_t1lmcfg_cpu1dsblx#define ka0c05_tlep$v_tlmcfg_bc_size ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_bc_sizet#define ka0c05_tlep$v_tlmcfg_lo_en ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_lo_enx#define ka0c05_tlep$v_tlmcfg_rm_size ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_rm_sizev#define ka0c05_tlep$v_tlmcfg_bcidle ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_bcidlez#define 1ka0c05_tlep$v_tlmcfg_cq_entry ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_cq_entryz#define ka0c05_tlep$v_tlmcfg_bq_entry ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_bq_entryz#define ka0c05_tlep$v_tlmcfg_sys_dsbl ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_sys_dsblz#define ka0c05_tlep$v_tlmcfg_ev5_dsbl ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_ev5_dsblz#define ka0c05_tle1p$v_tlmcfg_flt_dsbl ka0c05_tlep$r_tlmcfg_overlay.ka0c05_tlep$r_tlmcfg_bits.ka0c05_tlep$v_tlmcfg_flt_dsblT#define ka0c05_tlep$l_tlimask0 ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$l_tlimask0#define ka0c05_tlep$v_tlimask0_duart0en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_duart0en#define ka0c05_tlep$v_tlimask0_ipl14_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_ipl14_en#define ka0c05_tlep$v_tlimask0_ipl15_en ka0c05_tle1p$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_ipl15_en#define ka0c05_tlep$v_tlimask0_ipl16_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_ipl16_en#define ka0c05_tlep$v_tlimask0_ipl17_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_ipl17_en|#define ka0c05_tlep$v_tlimask0_ip_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_ip_en#define ka0c05_tlep$v_tlimask0_int1im_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_intim_en#define ka0c05_tlep$v_tlimask0_halt_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_halt_en|#define ka0c05_tlep$v_tlimask0_cp_en ka0c05_tlep$r_tlimask0_overlay.ka0c05_tlep$r_tlimask0_bits.ka0c05_tlep$v_tlimask0_cp_enT#define ka0c05_tlep$l_tlimask1 ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$l_tlimask1#define ka0c05_tlep$v_tlimask1_duart0en ka0c05_tlep$r_tlimask1_ove1rlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_duart0en#define ka0c05_tlep$v_tlimask1_ipl14_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_ipl14_en#define ka0c05_tlep$v_tlimask1_ipl15_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_ipl15_en#define ka0c05_tlep$v_tlimask1_ipl16_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_ipl16_en#define ka0c05_tlep$v_tlimask1_ipl17_en ka0c105_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_ipl17_en|#define ka0c05_tlep$v_tlimask1_ip_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_ip_en#define ka0c05_tlep$v_tlimask1_intim_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_intim_en#define ka0c05_tlep$v_tlimask1_halt_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_halt_en|#define ka0c05_tlep$v_tlimask11_cp_en ka0c05_tlep$r_tlimask1_overlay.ka0c05_tlep$r_tlimask1_bits.ka0c05_tlep$v_tlimask1_cp_enQ#define ka0c05_tlep$l_tlisum0 ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$l_tlisum0#define ka0c05_tlep$v_tlisum0_duart0int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_duart0int#define ka0c05_tlep$v_tlisum0_ipl14_int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl14_int#define ka0c05_tlep$v_tlisum0_ipl15_int ka0c05_tlep$r_tlisum0_over1lay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl15_int#define ka0c05_tlep$v_tlisum0_ipl16_int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl16_int#define ka0c05_tlep$v_tlisum0_ipl17_int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl17_intz#define ka0c05_tlep$v_tlisum0_ip_int ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ip_int#define ka0c05_tlep$v_tlisum0_intim_int ka0c05_tlep$r_tlis1um0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_intim_intx#define ka0c05_tlep$v_tlisum0_ipl14 ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl14x#define ka0c05_tlep$v_tlisum0_ipl15 ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl15x#define ka0c05_tlep$v_tlisum0_ipl16 ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl16x#define ka0c05_tlep$v_tlisum0_ipl17 ka0c05_tlep$r_tlisum0_overlay.ka10c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_ipl17|#define ka0c05_tlep$v_tlisum0_cp_halt ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_cp_haltv#define ka0c05_tlep$v_tlisum0_halt ka0c05_tlep$r_tlisum0_overlay.ka0c05_tlep$r_tlisum0_bits.ka0c05_tlep$v_tlisum0_haltQ#define ka0c05_tlep$l_tlisum1 ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$l_tlisum1#define ka0c05_tlep$v_tlisum1_duart0int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_dua1rt0int#define ka0c05_tlep$v_tlisum1_ipl14_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl14_int#define ka0c05_tlep$v_tlisum1_ipl15_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl15_int#define ka0c05_tlep$v_tlisum1_ipl16_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl16_int#define ka0c05_tlep$v_tlisum1_ipl17_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep1$v_tlisum1_ipl17_intz#define ka0c05_tlep$v_tlisum1_ip_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ip_int#define ka0c05_tlep$v_tlisum1_intim_int ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_intim_intx#define ka0c05_tlep$v_tlisum1_ipl14 ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl14x#define ka0c05_tlep$v_tlisum1_ipl15 ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_t1lisum1_ipl15x#define ka0c05_tlep$v_tlisum1_ipl16 ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl16x#define ka0c05_tlep$v_tlisum1_ipl17 ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_ipl17|#define ka0c05_tlep$v_tlisum1_cp_halt ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_cp_haltv#define ka0c05_tlep$v_tlisum1_halt ka0c05_tlep$r_tlisum1_overlay.ka0c05_tlep$r_tlisum1_bits.ka0c05_tlep$v_tlisum1_haltQ#d1efine ka0c05_tlep$l_tlcon00 ka0c05_tlep$r_tlcon00_overlay.ka0c05_tlep$l_tlcon00T#define ka0c05_tlep$l_tlcon00a ka0c05_tlep$r_tlcon00a_overlay.ka0c05_tlep$l_tlcon00aT#define ka0c05_tlep$l_tlcon00b ka0c05_tlep$r_tlcon00b_overlay.ka0c05_tlep$l_tlcon00bT#define ka0c05_tlep$l_tlcon00c ka0c05_tlep$r_tlcon00c_overlay.ka0c05_tlep$l_tlcon00cQ#define ka0c05_tlep$l_tlcon10 ka0c05_tlep$r_tlcon10_overlay.ka0c05_tlep$l_tlcon10T#define ka0c05_tlep$l_tlcon10a ka0c05_tlep$r_tlcon10a_overlay.ka0c05_tlep$l_tlcon110aT#define ka0c05_tlep$l_tlcon10b ka0c05_tlep$r_tlcon10b_overlay.ka0c05_tlep$l_tlcon10bT#define ka0c05_tlep$l_tlcon10c ka0c05_tlep$r_tlcon10c_overlay.ka0c05_tlep$l_tlcon10cQ#define ka0c05_tlep$l_tlcon01 ka0c05_tlep$r_tlcon01_overlay.ka0c05_tlep$l_tlcon01Q#define ka0c05_tlep$l_tlcon11 ka0c05_tlep$r_tlcon11_overlay.ka0c05_tlep$l_tlcon11T#define ka0c05_tlep$l_tlepaerr ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$l_tlepaerr#define ka0c05_tlep$v_tlepaerr_e2mape0 ka0c05_tlep$r_tlepaerr_overlay.ka0c051_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_e2mape0#define ka0c05_tlep$v_tlepaerr_e2mape1 ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_e2mape1#define ka0c05_tlep$v_tlepaerr_m2aape0 ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_m2aape0#define ka0c05_tlep$v_tlepaerr_m2aape1 ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_m2aape1|#define ka0c05_tlep$v_tlepaerr_dtdpe ka0c05_tlep$r_tlepaerr_ov1erlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_dtdpe|#define ka0c05_tlep$v_tlepaerr_dtspe ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_dtspe~#define ka0c05_tlep$v_tlepaerr_d2acpe ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_d2acpe#define ka0c05_tlep$v_tlepaerr_sysderr ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_sysderr~#define ka0c05_tlep$v_tlepaerr_sysflt ka0c05_tlep$r_tlepae1rr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_sysflt~#define ka0c05_tlep$v_tlepaerr_rd_err ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_rd_err~#define ka0c05_tlep$v_tlepaerr_iboxto ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_iboxto#define ka0c05_tlep$v_tlepaerr_rd_pend ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_rd_pendx#define ka0c05_tlep$v_tlepaerr_nxm ka0c05_tlep$r_t1lepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_nxm~#define ka0c05_tlep$v_tlepaerr_no_ack ka0c05_tlep$r_tlepaerr_overlay.ka0c05_tlep$r_tlepaerr_bits.ka0c05_tlep$v_tlepaerr_no_ackT#define ka0c05_tlep$l_tlepderr ka0c05_tlep$r_tlepderr_overlay.ka0c05_tlep$l_tlepderr~#define ka0c05_tlep$v_tlepderr_a2dcpe ka0c05_tlep$r_tlepderr_overlay.ka0c05_tlep$r_tlepderr_bits.ka0c05_tlep$v_tlepderr_a2dcpe#define ka0c05_tlep$v_tlepderr_d2dcpe0 ka0c05_tlep$r_tlepderr_overlay.ka0c05_tlep$r_tlepderr1_bits.ka0c05_tlep$v_tlepderr_d2dcpe0z#define ka0c05_tlep$v_tlepderr_gbto ka0c05_tlep$r_tlepderr_overlay.ka0c05_tlep$r_tlepderr_bits.ka0c05_tlep$v_tlepderr_gbtoT#define ka0c05_tlep$l_tlepmerr ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$l_tlepmerr#define ka0c05_tlep$v_tlepmerr_a2mape0 ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_a2mape0#define ka0c05_tlep$v_tlepmerr_a2mape1 ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_a2mape11~#define ka0c05_tlep$v_tlepmerr_d2mcpe ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_d2mcpe#define ka0c05_tlep$v_tlepmerr_d2dcpe1 ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_d2dcpe1#define ka0c05_tlep$v_tlepmerr_d2dcpe2 ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_d2dcpe2#define ka0c05_tlep$v_tlepmerr_d2dcpe3 ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlep1merr_d2dcpe3#define ka0c05_tlep$v_tlepmerr_rststat ka0c05_tlep$r_tlepmerr_overlay.ka0c05_tlep$r_tlepmerr_bits.ka0c05_tlep$v_tlepmerr_rststatT#define ka0c05_tlep$l_tlep_vmg ka0c05_tlep$r_tlep_vmg_overlay.ka0c05_tlep$l_tlep_vmgv#define ka0c05_tlep$v_tlep_vmg_5p ka0c05_tlep$r_tlep_vmg_overlay.ka0c05_tlep$r_tlep_vmg_bits.ka0c05_tlep$v_tlep_vmg_5pv#define ka0c05_tlep$v_tlep_vmg_5m ka0c05_tlep$r_tlep_vmg_overlay.ka0c05_tlep$r_tlep_vmg_bits.ka0c05_tlep$v_tlep_vmg_5mv#define ka0c05_tlep$v_tlep_vmg_3p ka10c05_tlep$r_tlep_vmg_overlay.ka0c05_tlep$r_tlep_vmg_bits.ka0c05_tlep$v_tlep_vmg_3pv#define ka0c05_tlep$v_tlep_vmg_3m ka0c05_tlep$r_tlep_vmg_overlay.ka0c05_tlep$r_tlep_vmg_bits.ka0c05_tlep$v_tlep_vmg_3mQ#define ka0c05_tlep$l_tldmcmd ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$l_tldmcmd~#define ka0c05_tlep$v_tldmcmd_size_512 ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_size_512|#define ka0c05_tlep$v_tldmcmd_size_1k ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_1bits.ka0c05_tlep$v_tldmcmd_size_1k|#define ka0c05_tlep$v_tldmcmd_size_2k ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_size_2k|#define ka0c05_tlep$v_tldmcmd_size_4k ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_size_4k|#define ka0c05_tlep$v_tldmcmd_size_8k ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_size_8kt#define ka0c05_tlep$v_tldmcmd_cmd ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.k1a0c05_tlep$v_tldmcmd_cmdx#define ka0c05_tlep$v_tldmcmd_valid ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_validv#define ka0c05_tlep$v_tldmcmd_rm_3 ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_rm_3v#define ka0c05_tlep$v_tldmcmd_rm_4 ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_rm_4|#define ka0c05_tlep$v_tldmcmd_rm_inlv ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_r1m_inlvz#define ka0c05_tlep$v_tldmcmd_cpu_id ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_cpu_id|#define ka0c05_tlep$v_tldmcmd_in_prog ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_in_progv#define ka0c05_tlep$v_tldmcmd_done ka0c05_tlep$r_tldmcmd_overlay.ka0c05_tlep$r_tldmcmd_bits.ka0c05_tlep$v_tldmcmd_doneT#define ka0c05_tlep$l_tldmadra ka0c05_tlep$r_tldmadra_overlay.ka0c05_tlep$l_tldmadraz#define ka0c05_tlep$v_tldmadra_addr ka0c051_tlep$r_tldmadra_overlay.ka0c05_tlep$r_tldmadra_bits.ka0c05_tlep$v_tldmadra_addrT#define ka0c05_tlep$l_tldmadrb ka0c05_tlep$r_tldmadrb_overlay.ka0c05_tlep$l_tldmadrbz#define ka0c05_tlep$v_tldmadrb_addr ka0c05_tlep$r_tldmadrb_overlay.ka0c05_tlep$r_tldmadrb_bits.ka0c05_tlep$v_tldmadrb_addrT#define ka0c05_tlep$l_tlpm_cmd ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$l_tlpm_cmd~#define ka0c05_tlep$v_tlpm_cmd_cpunum ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_cpunum1#define ka0c05_tlep$v_tlpm_cmd_set_sel ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_set_sel|#define ka0c05_tlep$v_tlpm_cmd_valid ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_valid#define ka0c05_tlep$v_tlpm_cmd_read_set ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_read_set#define ka0c05_tlep$v_tlpm_cmd_ovrf_en ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_c1md_ovrf_en#define ka0c05_tlep$v_tlpm_cmd_tot_cyc ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_tot_cyc#define ka0c05_tlep$v_tlpm_cmd_ev5_lat ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_ev5_lat~#define ka0c05_tlep$v_tlpm_cmd_rd_lat ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_rd_lat#define ka0c05_tlep$v_tlpm_cmd_sys_own ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_t1lep$v_tlpm_cmd_sys_ownv#define ka0c05_tlep$v_tlpm_cmd_f2 ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_f2z#define ka0c05_tlep$v_tlpm_cmd_lock ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_lockv#define ka0c05_tlep$v_tlpm_cmd_mb ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_mb~#define ka0c05_tlep$v_tlpm_cmd_sd_tot ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cm1d_sd_tot~#define ka0c05_tlep$v_tlpm_cmd_sd_ack ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_sd_ack~#define ka0c05_tlep$v_tlpm_cmd_rd_csr ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_rd_csrv#define ka0c05_tlep$v_tlpm_cmd_rd ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_rd~#define ka0c05_tlep$v_tlpm_cmd_rd_mod ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_1rd_mod~#define ka0c05_tlep$v_tlpm_cmd_rd_stc ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_rd_stcx#define ka0c05_tlep$v_tlpm_cmd_vic ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_vic~#define ka0c05_tlep$v_tlpm_cmd_wr_csr ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_wr_csrv#define ka0c05_tlep$v_tlpm_cmd_wr ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_wr1#define ka0c05_tlep$v_tlpm_cmd_wr_lock ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_wr_lock|#define ka0c05_tlep$v_tlpm_cmd_inval ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_inval#define ka0c05_tlep$v_tlpm_cmd_set_shr ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd_set_shr#define ka0c05_tlep$v_tlpm_cmd_rd_dirt ka0c05_tlep$r_tlpm_cmd_overlay.ka0c05_tlep$r_tlpm_cmd_bits.ka0c05_tlep$v_tlpm_cmd1_rd_dirtf#define ka0c05_tlep$l_tlpm_tot_cycles ka0c05_tlep$r_tlpm_tot_cycles_over.ka0c05_tlep$l_tlpm_tot_cycles`#define ka0c05_tlep$l_tlpm_ev5_lat ka0c05_tlep$r_tlpm_ev5_lat_overlay.ka0c05_tlep$l_tlpm_ev5_latb#define ka0c05_tlep$l_tlpm_read_lat ka0c05_tlep$r_tlpm_read_lat_overla.ka0c05_tlep$l_tlpm_read_latZ#define ka0c05_tlep$l_tlpm_owner ka0c05_tlep$r_tlpm_owner_overlay.ka0c05_tlep$l_tlpm_ownerW#define ka0c05_tlep$l_tlpm_silo ka0c05_tlep$r_tlpm_silo_overlay.ka0c05_tlep$l_tlpm_siloW#define ka0c105_tlep$l_tlpm_lock ka0c05_tlep$r_tlpm_lock_overlay.ka0c05_tlep$l_tlpm_lockQ#define ka0c05_tlep$l_tlpm_mb ka0c05_tlep$r_tlpm_mb_overlay.ka0c05_tlep$l_tlpm_mbQ#define ka0c05_tlep$l_tlpm_sd ka0c05_tlep$r_tlpm_sd_overlay.ka0c05_tlep$l_tlpm_sd]#define ka0c05_tlep$l_tlpm_sd_ack ka0c05_tlep$r_tlpm_sd_ack_overlay.ka0c05_tlep$l_tlpm_sd_ack]#define ka0c05_tlep$l_tlpm_rd_csr ka0c05_tlep$r_tlpm_rd_csr_overlay.ka0c05_tlep$l_tlpm_rd_csr`#define ka0c05_tlep$l_tlpm_rd_miss ka0c05_tlep$r_tlpm_rd_miss_overla1y.ka0c05_tlep$l_tlpm_rd_miss]#define ka0c05_tlep$l_tlpm_rd_mod ka0c05_tlep$r_tlpm_rd_mod_overlay.ka0c05_tlep$l_tlpm_rd_mod]#define ka0c05_tlep$l_tlpm_rd_stc ka0c05_tlep$r_tlpm_rd_stc_overlay.ka0c05_tlep$l_tlpm_rd_stc]#define ka0c05_tlep$l_tlpm_victim ka0c05_tlep$r_tlpm_victim_overlay.ka0c05_tlep$l_tlpm_victim]#define ka0c05_tlep$l_tlpm_wr_csr ka0c05_tlep$r_tlpm_wr_csr_overlay.ka0c05_tlep$l_tlpm_wr_csrQ#define ka0c05_tlep$l_tlpm_wr ka0c05_tlep$r_tlpm_wr_overlay.ka0c05_tlep$l_tlpm_wr`#define 1ka0c05_tlep$l_tlpm_wr_lock ka0c05_tlep$r_tlpm_wr_lock_overlay.ka0c05_tlep$l_tlpm_wr_lockZ#define ka0c05_tlep$l_tlpm_inval ka0c05_tlep$r_tlpm_inval_overlay.ka0c05_tlep$l_tlpm_inval]#define ka0c05_tlep$l_tlpm_s_shrd ka0c05_tlep$r_tlpm_s_shrd_overlay.ka0c05_tlep$l_tlpm_s_shrdQ#define ka0c05_tlep$l_tlpm_rd ka0c05_tlep$r_tlpm_rd_overlay.ka0c05_tlep$l_tlpm_rdZ#define ka0c05_tlep$l_tlpm_asilo ka0c05_tlep$r_tlpm_asilo_overlay.ka0c05_tlep$l_tlpm_asiloT#define ka0c05_tlep$l_rm_reg0a ka0c05_tlep$r_rm_reg01a_overlay.ka0c05_tlep$l_rm_reg0az#define ka0c05_tlep$v_rm_reg0a_aext ka0c05_tlep$r_rm_reg0a_overlay.ka0c05_tlep$r_rm_reg0a_bits.ka0c05_tlep$v_rm_reg0a_aext|#define ka0c05_tlep$v_rm_reg0a_baddr ka0c05_tlep$r_rm_reg0a_overlay.ka0c05_tlep$r_rm_reg0a_bits.ka0c05_tlep$v_rm_reg0a_baddr|#define ka0c05_tlep$v_rm_reg0a_valid ka0c05_tlep$r_rm_reg0a_overlay.ka0c05_tlep$r_rm_reg0a_bits.ka0c05_tlep$v_rm_reg0a_validT#define ka0c05_tlep$l_rm_reg0b ka0c05_tlep$r_rm_reg0b_overlay.ka0c05_tlep$l_rm_reg0bz#define ka10c05_tlep$v_rm_reg0b_aext ka0c05_tlep$r_rm_reg0b_overlay.ka0c05_tlep$r_rm_reg0b_bits.ka0c05_tlep$v_rm_reg0b_aext|#define ka0c05_tlep$v_rm_reg0b_baddr ka0c05_tlep$r_rm_reg0b_overlay.ka0c05_tlep$r_rm_reg0b_bits.ka0c05_tlep$v_rm_reg0b_baddr|#define ka0c05_tlep$v_rm_reg0b_valid ka0c05_tlep$r_rm_reg0b_overlay.ka0c05_tlep$r_rm_reg0b_bits.ka0c05_tlep$v_rm_reg0b_validT#define ka0c05_tlep$l_rm_reg1a ka0c05_tlep$r_rm_reg1a_overlay.ka0c05_tlep$l_rm_reg1az#define ka0c05_tlep$v_rm_reg1a_aext ka0c05_tlep$r_rm_r1eg1a_overlay.ka0c05_tlep$r_rm_reg1a_bits.ka0c05_tlep$v_rm_reg1a_aext|#define ka0c05_tlep$v_rm_reg1a_baddr ka0c05_tlep$r_rm_reg1a_overlay.ka0c05_tlep$r_rm_reg1a_bits.ka0c05_tlep$v_rm_reg1a_baddr|#define ka0c05_tlep$v_rm_reg1a_valid ka0c05_tlep$r_rm_reg1a_overlay.ka0c05_tlep$r_rm_reg1a_bits.ka0c05_tlep$v_rm_reg1a_validT#define ka0c05_tlep$l_rm_reg1b ka0c05_tlep$r_rm_reg1b_overlay.ka0c05_tlep$l_rm_reg1bz#define ka0c05_tlep$v_rm_reg1b_aext ka0c05_tlep$r_rm_reg1b_overlay.ka0c05_tlep$r_rm_reg1b_bits.ka0 1c05_tlep$v_rm_reg1b_aext|#define ka0c05_tlep$v_rm_reg1b_baddr ka0c05_tlep$r_rm_reg1b_overlay.ka0c05_tlep$r_rm_reg1b_bits.ka0c05_tlep$v_rm_reg1b_baddr|#define ka0c05_tlep$v_rm_reg1b_valid ka0c05_tlep$r_rm_reg1b_overlay.ka0c05_tlep$r_rm_reg1b_bits.ka0c05_tlep$v_rm_reg1b_valid"#endif /* #if !defined(__VAXC) */ (#define KA0C08_TLEP$M_TLDEV_DTYPE 0xFFFF*#define KA0C08_TLEP$M_TLDEV_SWREV 0xFF0000,#define KA0C08_TLEP$M_TLDEV_HWREV 0xFF000000$#define KA0C08_TLEP$M_TLBER_ATCE 0x1##define KA0C08_TLE1P$M_TLBER_APE 0x2##define KA0C08_TLEP$M_TLBER_BBE 0x4$#define KA0C08_TLEP$M_TLBER_LKTO 0x8$#define KA0C08_TLEP$M_TLBER_NAE 0x10%#define KA0C08_TLEP$M_TLBER_RTCE 0x20'#define KA0C08_TLEP$M_TLBER_ACKTCE 0x40%#define KA0C08_TLEP$M_TLBER_MMRE 0x80&#define KA0C08_TLEP$M_TLBER_FNAE 0x100'#define KA0C08_TLEP$M_TLBER_REQDE 0x200&#define KA0C08_TLEP$M_TLBER_ATDE 0x400'#define KA0C08_TLEP$M_TLBER_UDE 0x10000(#define KA0C08_TLEP$M_TLBER_CWDE 0x20000(#define KA0C08_TLEP$M_TLBER_CRDE 0x40000(#d 1efine KA0C08_TLEP$M_TLBER_DS0 0x100000(#define KA0C08_TLEP$M_TLBER_DS1 0x200000(#define KA0C08_TLEP$M_TLBER_DS2 0x400000(#define KA0C08_TLEP$M_TLBER_DS3 0x800000*#define KA0C08_TLEP$M_TLBER_DTDE 0x1000000+#define KA0C08_TLEP$M_TLBER_FDTCE 0x2000000+#define KA0C08_TLEP$M_TLBER_UACKE 0x4000000+#define KA0C08_TLEP$M_TLBER_ABTCE 0x8000000,#define KA0C08_TLEP$M_TLBER_DCTCE 0x10000000+#define KA0C08_TLEP$M_TLBER_SEQE 0x20000000*#define KA0C08_TLEP$M_TLBER_DSE 0x40000000*#define KA0C08_TLEP$M_ 1TLBER_DTO 0x80000000$#define KA0C08_TLEP$M_TLCNR_CWDD 0x1$#define KA0C08_TLEP$M_TLCNR_CRDD 0x2$#define KA0C08_TLEP$M_TLCNR_DTOD 0x8(#define KA0C08_TLEP$M_TLCNR_NODE_ID 0xF0&#define KA0C08_TLEP$M_TLCNR_VCNT 0xF00(#define KA0C08_TLEP$M_TLCNR_STF_A 0x1000(#define KA0C08_TLEP$M_TLCNR_STF_B 0x2000+#define KA0C08_TLEP$M_TLCNR_HALT_A 0x100000+#define KA0C08_TLEP$M_TLCNR_HALT_B 0x200000+#define KA0C08_TLEP$M_TLCNR_NRST 0x40000000+#define KA0C08_TLEP$M_TLCNR_LOFE 0x80000000#define KA0C08_TLEP$ 1M_VID_A 0xF #define KA0C08_TLEP$M_VID_B 0xF0(#define KA0C08_TLEP$M_TLMMR0_INTMASK 0x3)#define KA0C08_TLEP$M_TLMMR0_ADRMASK 0xF0(#define KA0C08_TLEP$M_TLMMR0_INTLV 0x700(#define KA0C08_TLEP$M_TLMMR0_SBANK 0x800.#define KA0C08_TLEP$M_TLMMR0_ADDRESS 0x3FFF000-#define KA0C08_TLEP$M_TLMMR0_VALID 0x80000000(#define KA0C08_TLEP$M_TLMMR1_INTMASK 0x3)#define KA0C08_TLEP$M_TLMMR1_ADRMASK 0xF0(#define KA0C08_TLEP$M_TLMMR1_INTLV 0x700(#define KA0C08_TLEP$M_TLMMR1_SBANK 0x800.#define KA0C08_TLEP$M_ 1TLMMR1_ADDRESS 0x3FFF000-#define KA0C08_TLEP$M_TLMMR1_VALID 0x80000000(#define KA0C08_TLEP$M_TLMMR2_INTMASK 0x3)#define KA0C08_TLEP$M_TLMMR2_ADRMASK 0xF0(#define KA0C08_TLEP$M_TLMMR2_INTLV 0x700(#define KA0C08_TLEP$M_TLMMR2_SBANK 0x800.#define KA0C08_TLEP$M_TLMMR2_ADDRESS 0x3FFF000-#define KA0C08_TLEP$M_TLMMR2_VALID 0x80000000(#define KA0C08_TLEP$M_TLMMR3_INTMASK 0x3)#define KA0C08_TLEP$M_TLMMR3_ADRMASK 0xF0(#define KA0C08_TLEP$M_TLMMR3_INTLV 0x700(#define KA0C08_TLEP$M_TLMMR3_SBANK 0x8 100.#define KA0C08_TLEP$M_TLMMR3_ADDRESS 0x3FFF000-#define KA0C08_TLEP$M_TLMMR3_VALID 0x80000000(#define KA0C08_TLEP$M_TLMMR4_INTMASK 0x3)#define KA0C08_TLEP$M_TLMMR4_ADRMASK 0xF0(#define KA0C08_TLEP$M_TLMMR4_INTLV 0x700(#define KA0C08_TLEP$M_TLMMR4_SBANK 0x800.#define KA0C08_TLEP$M_TLMMR4_ADDRESS 0x3FFF000-#define KA0C08_TLEP$M_TLMMR4_VALID 0x80000000(#define KA0C08_TLEP$M_TLMMR5_INTMASK 0x3)#define KA0C08_TLEP$M_TLMMR5_ADRMASK 0xF0(#define KA0C08_TLEP$M_TLMMR5_INTLV 0x700(#define KA0C 108_TLEP$M_TLMMR5_SBANK 0x800.#define KA0C08_TLEP$M_TLMMR5_ADDRESS 0x3FFF000-#define KA0C08_TLEP$M_TLMMR5_VALID 0x80000000(#define KA0C08_TLEP$M_TLMMR6_INTMASK 0x3)#define KA0C08_TLEP$M_TLMMR6_ADRMASK 0xF0(#define KA0C08_TLEP$M_TLMMR6_INTLV 0x700(#define KA0C08_TLEP$M_TLMMR6_SBANK 0x800.#define KA0C08_TLEP$M_TLMMR6_ADDRESS 0x3FFF000-#define KA0C08_TLEP$M_TLMMR6_VALID 0x80000000(#define KA0C08_TLEP$M_TLMMR7_INTMASK 0x3)#define KA0C08_TLEP$M_TLMMR7_ADRMASK 0xF0(#define KA0C08_TLEP$M_TLMMR7 1_INTLV 0x700(#define KA0C08_TLEP$M_TLMMR7_SBANK 0x800.#define KA0C08_TLEP$M_TLMMR7_ADDRESS 0x3FFF000-#define KA0C08_TLEP$M_TLMMR7_VALID 0x80000000'#define KA0C08_TLEP$M_TLESR0_SYND0 0xFF)#define KA0C08_TLEP$M_TLESR0_SYND1 0xFF00(#define KA0C08_TLEP$M_TLESR0_TDE 0x10000(#define KA0C08_TLEP$M_TLESR0_TCE 0x20000*#define KA0C08_TLEP$M_TLESR0_DVTCE 0x40000)#define KA0C08_TLEP$M_TLESR0_UECC 0x80000+#define KA0C08_TLEP$M_TLESR0_CWECC 0x100000+#define KA0C08_TLEP$M_TLESR0_CRECC 0x200000*#def 1ine KA0C08_TLEP$M_TLESR0_CPU0 0x400000*#define KA0C08_TLEP$M_TLESR0_CPU1 0x800000.#define KA0C08_TLEP$M_TLESR0_LOFSYN 0x80000000'#define KA0C08_TLEP$M_TLESR1_SYND0 0xFF)#define KA0C08_TLEP$M_TLESR1_SYND1 0xFF00(#define KA0C08_TLEP$M_TLESR1_TDE 0x10000(#define KA0C08_TLEP$M_TLESR1_TCE 0x20000*#define KA0C08_TLEP$M_TLESR1_DVTCE 0x40000)#define KA0C08_TLEP$M_TLESR1_UECC 0x80000+#define KA0C08_TLEP$M_TLESR1_CWECC 0x100000+#define KA0C08_TLEP$M_TLESR1_CRECC 0x200000*#define KA0C08_TLEP$M_TL 1ESR1_CPU0 0x400000*#define KA0C08_TLEP$M_TLESR1_CPU1 0x800000.#define KA0C08_TLEP$M_TLESR1_LOFSYN 0x80000000'#define KA0C08_TLEP$M_TLESR2_SYND0 0xFF)#define KA0C08_TLEP$M_TLESR2_SYND1 0xFF00(#define KA0C08_TLEP$M_TLESR2_TDE 0x10000(#define KA0C08_TLEP$M_TLESR2_TCE 0x20000*#define KA0C08_TLEP$M_TLESR2_DVTCE 0x40000)#define KA0C08_TLEP$M_TLESR2_UECC 0x80000+#define KA0C08_TLEP$M_TLESR2_CWECC 0x100000+#define KA0C08_TLEP$M_TLESR2_CRECC 0x200000*#define KA0C08_TLEP$M_TLESR2_CPU0 0x400000* 1#define KA0C08_TLEP$M_TLESR2_CPU1 0x800000.#define KA0C08_TLEP$M_TLESR2_LOFSYN 0x80000000'#define KA0C08_TLEP$M_TLESR3_SYND0 0xFF)#define KA0C08_TLEP$M_TLESR3_SYND1 0xFF00(#define KA0C08_TLEP$M_TLESR3_TDE 0x10000(#define KA0C08_TLEP$M_TLESR3_TCE 0x20000*#define KA0C08_TLEP$M_TLESR3_DVTCE 0x40000)#define KA0C08_TLEP$M_TLESR3_UECC 0x80000+#define KA0C08_TLEP$M_TLESR3_CWECC 0x100000+#define KA0C08_TLEP$M_TLESR3_CRECC 0x200000*#define KA0C08_TLEP$M_TLESR3_CPU0 0x400000*#define KA0C08_TLEP$ 1M_TLESR3_CPU1 0x800000.#define KA0C08_TLEP$M_TLESR3_LOFSYN 0x80000000)#define KA0C08_TLEP$M_TLMODCFG0_FRIGN 0x1(#define KA0C08_TLEP$M_TLMODCFG0_FDE0 0x2(#define KA0C08_TLEP$M_TLMODCFG0_FDE1 0x4*#define KA0C08_TLEP$M_TLMODCFG0_P1_UDE 0x8,#define KA0C08_TLEP$M_TLMODCFG0_P1_CRDE 0x10+#define KA0C08_TLEP$M_TLMODCFG0_DLY_IN 0x20,#define KA0C08_TLEP$M_TLMODCFG0_DLY_OUT 0x40-#define KA0C08_TLEP$M_TLMODCFG0_DPQ_MAX 0x380-#define KA0C08_TLEP$M_TLMODCFG0_MMRE_DS 0x400-#define KA0C08_TLEP$M_TLMODC 1FG0_FASTFLS 0x800.#define KA0C08_TLEP$M_TLMODCFG0_DELAY_A 0x1000.#define KA0C08_TLEP$M_TLMODCFG0_ILGLCSR 0x2000.#define KA0C08_TLEP$M_TLMODCFG0_E_SLOWR 0x4000.#define KA0C08_TLEP$M_TLMODCFG0_ASRT_FT 0x8000/#define KA0C08_TLEP$M_TLMODCFG0_DTAG_PE 0x10000/#define KA0C08_TLEP$M_TLMODCFG0_DTAG0_D 0x20000/#define KA0C08_TLEP$M_TLMODCFG0_DTAG1_D 0x40000.#define KA0C08_TLEP$M_TLMODCFG0_D_WRAP 0x80000/#define KA0C08_TLEP$M_TLMODCFG0_BQ_MAX 0x7000001#define KA0C08_TLEP$M_TLMODCFG0_BC_SIZE 0x1800 10002#define KA0C08_TLEP$M_TLMODCFG0_FDE_CMD 0x1E000000/#define KA0C08_TLEP$M_TLMODCFG0_FSBE 0x20000000/#define KA0C08_TLEP$M_TLMODCFG0_FDE2 0x40000000/#define KA0C08_TLEP$M_TLMODCFG0_FDE3 0x80000000(#define KA0C08_TLEP$M_TLDTAGDATA_PAR 0x1-#define KA0C08_TLEP$M_TLDTAGDATA_DATA 0x3FFFE-#define KA0C08_TLEP$M_TLDTAGADDR_ADDR 0x3FFFF1#define KA0C08_TLEP$M_TLDTAGADDR_CPU_SL 0x1000000+#define KA0C08_TLEP$M_TLMODCFG1_OVRTK_E 0x1*#define KA0C08_TLEP$M_TLMODCFG1_P0_RID 0xE+#define KA0C08_TLE 1P$M_TLMODCFG1_P1_RID 0x70-#define KA0C08_TLEP$M_TLMODCFG1_MBPR_RY 0x180-#define KA0C08_TLEP$M_TLMODCFG1_FAULT_D 0x200-#define KA0C08_TLEP$M_TLMODCFG1_FSTRQ_D 0x400-#define KA0C08_TLEP$M_TLMODCFG1_P0_RQ_D 0x800.#define KA0C08_TLEP$M_TLMODCFG1_P1_RQ_D 0x1000.#define KA0C08_TLEP$M_TLMODCFG1_D_PROBE 0x6000-#define KA0C08_TLEP$M_TLMODCFG1_FSTPTH 0x8000/#define KA0C08_TLEP$M_TLMODCFG1_DLSB_PR 0x10000/#define KA0C08_TLEP$M_TLMODCFG1_VIC_SKP 0x20000/#define KA0C08_TLEP$M_TLMODCFG1_FRCE_SQ 0x 140000.#define KA0C08_TLEP$M_TLMODCFG1_DB_BUB 0x80000/#define KA0C08_TLEP$M_TLMODCFG1_FST_VQ 0x1000000#define KA0C08_TLEP$M_TLMODCFG1_FST_PRQ 0x2000000#define KA0C08_TLEP$M_TLMODCFG1_BUSWRTE 0x4000000#define KA0C08_TLEP$M_TLMODCFG1_FST_WRT 0x8000001#define KA0C08_TLEP$M_TLMODCFG1_FRC_SHR 0x10000001#define KA0C08_TLEP$M_TLMODCFG1_VQRBCTL 0x20000001#define KA0C08_TLEP$M_TLMODCFG1_CSR_SIZ 0x4000000+#define KA0C08_TLEP$M_TLIMASK0_DUART0EN 0x1+#define KA0C08_TLEP$M_TLIMASK0_IPL14_EN 0x2+#d 1efine KA0C08_TLEP$M_TLIMASK0_IPL15_EN 0x4+#define KA0C08_TLEP$M_TLIMASK0_IPL16_EN 0x8,#define KA0C08_TLEP$M_TLIMASK0_IPL17_EN 0x10)#define KA0C08_TLEP$M_TLIMASK0_IP_EN 0x20,#define KA0C08_TLEP$M_TLIMASK0_INTIM_EN 0x40+#define KA0C08_TLEP$M_TLIMASK0_HALT_EN 0x80*#define KA0C08_TLEP$M_TLIMASK0_CP_EN 0x100+#define KA0C08_TLEP$M_TLIMASK1_DUART0EN 0x1+#define KA0C08_TLEP$M_TLIMASK1_IPL14_EN 0x2+#define KA0C08_TLEP$M_TLIMASK1_IPL15_EN 0x4+#define KA0C08_TLEP$M_TLIMASK1_IPL16_EN 0x8,#defin 1e KA0C08_TLEP$M_TLIMASK1_IPL17_EN 0x10)#define KA0C08_TLEP$M_TLIMASK1_IP_EN 0x20,#define KA0C08_TLEP$M_TLIMASK1_INTIM_EN 0x40+#define KA0C08_TLEP$M_TLIMASK1_HALT_EN 0x80*#define KA0C08_TLEP$M_TLIMASK1_CP_EN 0x100+#define KA0C08_TLEP$M_TLISUM0_DUART0INT 0x1+#define KA0C08_TLEP$M_TLISUM0_IPL14_INT 0x2+#define KA0C08_TLEP$M_TLISUM0_IPL15_INT 0x4+#define KA0C08_TLEP$M_TLISUM0_IPL16_INT 0x8,#define KA0C08_TLEP$M_TLISUM0_IPL17_INT 0x10)#define KA0C08_TLEP$M_TLISUM0_IP_INT 0x20,#define KA0C 108_TLEP$M_TLISUM0_INTIM_INT 0x40)#define KA0C08_TLEP$M_TLISUM0_IPL14 0xF80+#define KA0C08_TLEP$M_TLISUM0_IPL15 0x1F000,#define KA0C08_TLEP$M_TLISUM0_IPL16 0x3E0000-#define KA0C08_TLEP$M_TLISUM0_IPL17 0x7C00000/#define KA0C08_TLEP$M_TLISUM0_CP_HALT 0x8000000-#define KA0C08_TLEP$M_TLISUM0_HALT 0x10000000+#define KA0C08_TLEP$M_TLISUM1_DUART0INT 0x1+#define KA0C08_TLEP$M_TLISUM1_IPL14_INT 0x2+#define KA0C08_TLEP$M_TLISUM1_IPL15_INT 0x4+#define KA0C08_TLEP$M_TLISUM1_IPL16_INT 0x8,#defin 1e KA0C08_TLEP$M_TLISUM1_IPL17_INT 0x10)#define KA0C08_TLEP$M_TLISUM1_IP_INT 0x20,#define KA0C08_TLEP$M_TLISUM1_INTIM_INT 0x40)#define KA0C08_TLEP$M_TLISUM1_IPL14 0xF80+#define KA0C08_TLEP$M_TLISUM1_IPL15 0x1F000,#define KA0C08_TLEP$M_TLISUM1_IPL16 0x3E0000-#define KA0C08_TLEP$M_TLISUM1_IPL17 0x7C00000/#define KA0C08_TLEP$M_TLISUM1_CP_HALT 0x8000000-#define KA0C08_TLEP$M_TLISUM1_HALT 0x10000000+#define KA0C08_TLEP$M_TCCERR_P0_MBPR_TO 0x1+#define KA0C08_TLEP$M_TCCERR_P1_MBPR_TO 0x2&#d 1efine KA0C08_TLEP$M_TCCERR_DTPE0 0x4&#define KA0C08_TLEP$M_TCCERR_DTPE1 0x8)#define KA0C08_TLEP$M_TCCERR_SYSDERR 0x10,#define KA0C08_TLEP$M_TCCERR_WSPC_RD_ER 0x20*#define KA0C08_TLEP$M_TCCERR_SYSFAULT 0xC0-#define KA0C08_TLEP$M_TCCERR_FAULT_ASRT 0x100-#define KA0C08_TLEP$M_TCCERR_P0_FTLMMRE 0x200-#define KA0C08_TLEP$M_TCCERR_P1_FTLMMRE 0x400*#define KA0C08_TLEP$M_TCCERR_P0_MMRE 0x800+#define KA0C08_TLEP$M_TCCERR_P1_MMRE 0x1000.#define KA0C08_TLEP$M_TCCERR_CSR_WR_NXM 0x2000-#define KA0C 108_TLEP$M_TCCERR_CSR_XACTN 0x4000,#define KA0C08_TLEP$M_TCCERR_TCC_REV 0xF00000#define KA0C08_TLEP$M_TCCERR_P0_ILGLCSR 0x1000000#define KA0C08_TLEP$M_TCCERR_P1_ILGLCSR 0x200000%#define KA0C08_TLEP$M_TDIERR_GBTO 0x4$#define KA0C08_TLEP$M_TL6_VMG_5P 0x1$#define KA0C08_TLEP$M_TL6_VMG_5M 0x2$#define KA0C08_TLEP$M_TL6_VMG_3P 0x4$#define KA0C08_TLEP$M_TL6_VMG_3M 0x8(#define KA0C08_TLEP$M_TL6WERR_SELECT 0x3+#define KA0C08_TLEP$M_TL6WERR_R0_RD_PND 0x1-#define KA0C08_TLEP$M_TL6WERR_R0_ADDR 0xFFFF18-#define KA0C08_TLEP$M_TL6WERR_R1_ADDR 0x7FFFF+#define KA0C08_TLEP$M_TL6WERR_R2_RD_PND 0x1-#define KA0C08_TLEP$M_TL6WERR_R2_ADDR 0xFFFF8-#define KA0C08_TLEP$M_TL6WERR_R3_ADDR 0x7FFFF,#define KA0C08_TLEP$M_TLDTAGEX_F1 0xFFFFFFFF c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0c08_tlep {#pragma __nomember_alignment __unio1n {) unsigned int ka0c08_tlep$l_tldev; __struct {4 unsigned ka0c08_tlep$v_tldev_dtype : 16;3 unsigned ka0c08_tlep$v_tldev_swrev : 8;3 unsigned ka0c08_tlep$v_tldev_hwrev : 8;' } ka0c08_tlep$r_tldev_bits;& } ka0c08_tlep$r_tldev_overlay;* unsigned char ka0c08_tlep$b_f200 [60]; __union {) unsigned int ka0c08_tlep$l_tlber; __struct {2 unsigned ka0c08_tlep$v_tlber_atce : 1;1 1unsigned ka0c08_tlep$v_tlber_ape : 1;1 unsigned ka0c08_tlep$v_tlber_bbe : 1;2 unsigned ka0c08_tlep$v_tlber_lkto : 1;1 unsigned ka0c08_tlep$v_tlber_nae : 1;2 unsigned ka0c08_tlep$v_tlber_rtce : 1;4 unsigned ka0c08_tlep$v_tlber_acktce : 1;2 unsigned ka0c08_tlep$v_tlber_mmre : 1;2 unsigned ka0c08_tlep$v_tlber_fnae : 1;3 unsigned ka0c08_tlep$v_tlber_reqde : 1;2 unsigned ka0c08_tlep$v_tlber_atde 1: 1;0 unsigned ka0c08_tlep$v_tlber_f1 : 5;1 unsigned ka0c08_tlep$v_tlber_ude : 1;2 unsigned ka0c08_tlep$v_tlber_cwde : 1;2 unsigned ka0c08_tlep$v_tlber_crde : 1;3 unsigned ka0c08_tlep$v_tlber_cwde2 : 1;1 unsigned ka0c08_tlep$v_tlber_ds0 : 1;1 unsigned ka0c08_tlep$v_tlber_ds1 : 1;1 unsigned ka0c08_tlep$v_tlber_ds2 : 1;1 unsigned ka0c08_tlep$v_tlber_ds3 : 1;2 unsigned ka0c08_tlep 1$v_tlber_dtde : 1;3 unsigned ka0c08_tlep$v_tlber_fdtce : 1;3 unsigned ka0c08_tlep$v_tlber_uacke : 1;3 unsigned ka0c08_tlep$v_tlber_abtce : 1;3 unsigned ka0c08_tlep$v_tlber_dctce : 1;2 unsigned ka0c08_tlep$v_tlber_seqe : 1;1 unsigned ka0c08_tlep$v_tlber_dse : 1;1 unsigned ka0c08_tlep$v_tlber_dto : 1;' } ka0c08_tlep$r_tlber_bits;& } ka0c08_tlep$r_tlber_overlay;* unsigned char ka0c08_tlep$b_ 1f210 [60]; __union {) unsigned int ka0c08_tlep$l_tlcnr; __struct {2 unsigned ka0c08_tlep$v_tlcnr_cwdd : 1;2 unsigned ka0c08_tlep$v_tlcnr_crdd : 1;0 unsigned ka0c08_tlep$v_tlcnr_f1 : 1;2 unsigned ka0c08_tlep$v_tlcnr_dtod : 1;5 unsigned ka0c08_tlep$v_tlcnr_node_id : 4;2 unsigned ka0c08_tlep$v_tlcnr_vcnt : 4;3 unsigned ka0c08_tlep$v_tlcnr_stf_a : 1;3 unsigned ka0c08_tlep$v_tlcnr_stf 1_b : 1;0 unsigned ka0c08_tlep$v_tlcnr_f2 : 6;4 unsigned ka0c08_tlep$v_tlcnr_halt_a : 1;4 unsigned ka0c08_tlep$v_tlcnr_halt_b : 1;3 unsigned ka0c08_tlep$v_tlcnr_fill3 : 8;2 unsigned ka0c08_tlep$v_tlcnr_nrst : 1;2 unsigned ka0c08_tlep$v_tlcnr_lofe : 1;' } ka0c08_tlep$r_tlcnr_bits;& } ka0c08_tlep$r_tlcnr_overlay;* unsigned char ka0c08_tlep$b_f220 [60]; __union {) unsigned int ka0c08_tlep$l_tlv1id; __struct {- unsigned ka0c08_tlep$v_vid_a : 4;- unsigned ka0c08_tlep$v_vid_b : 4;/ unsigned ka0c08_tlep$v_vid_f1 : 24;' } ka0c08_tlep$r_tlvid_bits;& } ka0c08_tlep$r_tlvid_overlay;+ unsigned char ka0c08_tlep$b_f230 [316]; __union {* unsigned int ka0c08_tlep$l_tlmmr0; __struct {6 unsigned ka0c08_tlep$v_tlmmr0_intmask : 2;1 unsigned ka0c08_tlep$v_tlmmr0_f1 : 2;6 un 2signed ka0c08_tlep$v_tlmmr0_adrmask : 4;4 unsigned ka0c08_tlep$v_tlmmr0_intlv : 3;4 unsigned ka0c08_tlep$v_tlmmr0_sbank : 1;7 unsigned ka0c08_tlep$v_tlmmr0_address : 14;1 unsigned ka0c08_tlep$v_tlmmr0_f2 : 5;4 unsigned ka0c08_tlep$v_tlmmr0_valid : 1;( } ka0c08_tlep$r_tlmmr0_bits;' } ka0c08_tlep$r_tlmmr0_overlay;* unsigned char ka0c08_tlep$b_f240 [60]; __union {* unsigned int ka0c08_tlep$l_tlmmr1; 2 __struct {6 unsigned ka0c08_tlep$v_tlmmr1_intmask : 2;1 unsigned ka0c08_tlep$v_tlmmr1_f1 : 2;6 unsigned ka0c08_tlep$v_tlmmr1_adrmask : 4;4 unsigned ka0c08_tlep$v_tlmmr1_intlv : 3;4 unsigned ka0c08_tlep$v_tlmmr1_sbank : 1;7 unsigned ka0c08_tlep$v_tlmmr1_address : 14;1 unsigned ka0c08_tlep$v_tlmmr1_f2 : 5;4 unsigned ka0c08_tlep$v_tlmmr1_valid : 1;( } ka0c08_tlep$r_tlmmr1_bits;' } 2ka0c08_tlep$r_tlmmr1_overlay;* unsigned char ka0c08_tlep$b_f250 [60]; __union {* unsigned int ka0c08_tlep$l_tlmmr2; __struct {6 unsigned ka0c08_tlep$v_tlmmr2_intmask : 2;1 unsigned ka0c08_tlep$v_tlmmr2_f1 : 2;6 unsigned ka0c08_tlep$v_tlmmr2_adrmask : 4;4 unsigned ka0c08_tlep$v_tlmmr2_intlv : 3;4 unsigned ka0c08_tlep$v_tlmmr2_sbank : 1;7 unsigned ka0c08_tlep$v_tlmmr2_address : 14;1 unsign 2ed ka0c08_tlep$v_tlmmr2_f2 : 5;4 unsigned ka0c08_tlep$v_tlmmr2_valid : 1;( } ka0c08_tlep$r_tlmmr2_bits;' } ka0c08_tlep$r_tlmmr2_overlay;* unsigned char ka0c08_tlep$b_f260 [60]; __union {* unsigned int ka0c08_tlep$l_tlmmr3; __struct {6 unsigned ka0c08_tlep$v_tlmmr3_intmask : 2;1 unsigned ka0c08_tlep$v_tlmmr3_f1 : 2;6 unsigned ka0c08_tlep$v_tlmmr3_adrmask : 4;4 unsigned ka0c08_tlep$v_tlmmr3_in 2tlv : 3;4 unsigned ka0c08_tlep$v_tlmmr3_sbank : 1;7 unsigned ka0c08_tlep$v_tlmmr3_address : 14;1 unsigned ka0c08_tlep$v_tlmmr3_f2 : 5;4 unsigned ka0c08_tlep$v_tlmmr3_valid : 1;( } ka0c08_tlep$r_tlmmr3_bits;' } ka0c08_tlep$r_tlmmr3_overlay;* unsigned char ka0c08_tlep$b_f270 [60]; __union {* unsigned int ka0c08_tlep$l_tlmmr4; __struct {6 unsigned ka0c08_tlep$v_tlmmr4_intmask : 2;1 2unsigned ka0c08_tlep$v_tlmmr4_f1 : 2;6 unsigned ka0c08_tlep$v_tlmmr4_adrmask : 4;4 unsigned ka0c08_tlep$v_tlmmr4_intlv : 3;4 unsigned ka0c08_tlep$v_tlmmr4_sbank : 1;7 unsigned ka0c08_tlep$v_tlmmr4_address : 14;1 unsigned ka0c08_tlep$v_tlmmr4_f2 : 5;4 unsigned ka0c08_tlep$v_tlmmr4_valid : 1;( } ka0c08_tlep$r_tlmmr4_bits;' } ka0c08_tlep$r_tlmmr4_overlay;* unsigned char ka0c08_tlep$b_f280 [60]; __unio 2n {* unsigned int ka0c08_tlep$l_tlmmr5; __struct {6 unsigned ka0c08_tlep$v_tlmmr5_intmask : 2;1 unsigned ka0c08_tlep$v_tlmmr5_f1 : 2;6 unsigned ka0c08_tlep$v_tlmmr5_adrmask : 4;4 unsigned ka0c08_tlep$v_tlmmr5_intlv : 3;4 unsigned ka0c08_tlep$v_tlmmr5_sbank : 1;7 unsigned ka0c08_tlep$v_tlmmr5_address : 14;1 unsigned ka0c08_tlep$v_tlmmr5_f2 : 5;4 unsigned ka0c08_tlep$v_tlmmr5_valid : 1; 2( } ka0c08_tlep$r_tlmmr5_bits;' } ka0c08_tlep$r_tlmmr5_overlay;* unsigned char ka0c08_tlep$b_f290 [60]; __union {* unsigned int ka0c08_tlep$l_tlmmr6; __struct {6 unsigned ka0c08_tlep$v_tlmmr6_intmask : 2;1 unsigned ka0c08_tlep$v_tlmmr6_f1 : 2;6 unsigned ka0c08_tlep$v_tlmmr6_adrmask : 4;4 unsigned ka0c08_tlep$v_tlmmr6_intlv : 3;4 unsigned ka0c08_tlep$v_tlmmr6_sbank : 1;7 unsigned k 2a0c08_tlep$v_tlmmr6_address : 14;1 unsigned ka0c08_tlep$v_tlmmr6_f2 : 5;4 unsigned ka0c08_tlep$v_tlmmr6_valid : 1;( } ka0c08_tlep$r_tlmmr6_bits;' } ka0c08_tlep$r_tlmmr6_overlay;- unsigned char ka0c08_tlep$b_fill300 [60]; __union {* unsigned int ka0c08_tlep$l_tlmmr7; __struct {6 unsigned ka0c08_tlep$v_tlmmr7_intmask : 2;1 unsigned ka0c08_tlep$v_tlmmr7_f1 : 2;6 unsigned ka0c08_tlep$v_tlmmr7_ 2adrmask : 4;4 unsigned ka0c08_tlep$v_tlmmr7_intlv : 3;4 unsigned ka0c08_tlep$v_tlmmr7_sbank : 1;7 unsigned ka0c08_tlep$v_tlmmr7_address : 14;1 unsigned ka0c08_tlep$v_tlmmr7_f2 : 5;4 unsigned ka0c08_tlep$v_tlmmr7_valid : 1;( } ka0c08_tlep$r_tlmmr7_bits;' } ka0c08_tlep$r_tlmmr7_overlay;. unsigned char ka0c08_tlep$b_fill310 [700]; __union {* unsigned int ka0c08_tlep$l_tlesr0; __struct {4 2 unsigned ka0c08_tlep$v_tlesr0_synd0 : 8;4 unsigned ka0c08_tlep$v_tlesr0_synd1 : 8;2 unsigned ka0c08_tlep$v_tlesr0_tde : 1;2 unsigned ka0c08_tlep$v_tlesr0_tce : 1;4 unsigned ka0c08_tlep$v_tlesr0_dvtce : 1;3 unsigned ka0c08_tlep$v_tlesr0_uecc : 1;4 unsigned ka0c08_tlep$v_tlesr0_cwecc : 1;4 unsigned ka0c08_tlep$v_tlesr0_crecc : 1;3 unsigned ka0c08_tlep$v_tlesr0_cpu0 : 1;3 unsigned ka0c08_tl 2ep$v_tlesr0_cpu1 : 1;1 unsigned ka0c08_tlep$v_tlesr0_f1 : 7;5 unsigned ka0c08_tlep$v_tlesr0_lofsyn : 1;( } ka0c08_tlep$r_tlesr0_bits;' } ka0c08_tlep$r_tlesr0_overlay;- unsigned char ka0c08_tlep$b_fill320 [60]; __union {* unsigned int ka0c08_tlep$l_tlesr1; __struct {4 unsigned ka0c08_tlep$v_tlesr1_synd0 : 8;4 unsigned ka0c08_tlep$v_tlesr1_synd1 : 8;2 unsigned ka0c08_tlep$v_tlesr1_tde : 1;2 2 unsigned ka0c08_tlep$v_tlesr1_tce : 1;4 unsigned ka0c08_tlep$v_tlesr1_dvtce : 1;3 unsigned ka0c08_tlep$v_tlesr1_uecc : 1;4 unsigned ka0c08_tlep$v_tlesr1_cwecc : 1;4 unsigned ka0c08_tlep$v_tlesr1_crecc : 1;3 unsigned ka0c08_tlep$v_tlesr1_cpu0 : 1;3 unsigned ka0c08_tlep$v_tlesr1_cpu1 : 1;1 unsigned ka0c08_tlep$v_tlesr1_f1 : 7;5 unsigned ka0c08_tlep$v_tlesr1_lofsyn : 1;( } ka0c08_t 2lep$r_tlesr1_bits;' } ka0c08_tlep$r_tlesr1_overlay;- unsigned char ka0c08_tlep$b_fill330 [60]; __union {* unsigned int ka0c08_tlep$l_tlesr2; __struct {4 unsigned ka0c08_tlep$v_tlesr2_synd0 : 8;4 unsigned ka0c08_tlep$v_tlesr2_synd1 : 8;2 unsigned ka0c08_tlep$v_tlesr2_tde : 1;2 unsigned ka0c08_tlep$v_tlesr2_tce : 1;4 unsigned ka0c08_tlep$v_tlesr2_dvtce : 1;3 unsigned ka0c08_tlep$v_tlesr2_uecc : 2 1;4 unsigned ka0c08_tlep$v_tlesr2_cwecc : 1;4 unsigned ka0c08_tlep$v_tlesr2_crecc : 1;3 unsigned ka0c08_tlep$v_tlesr2_cpu0 : 1;3 unsigned ka0c08_tlep$v_tlesr2_cpu1 : 1;1 unsigned ka0c08_tlep$v_tlesr2_f1 : 7;5 unsigned ka0c08_tlep$v_tlesr2_lofsyn : 1;( } ka0c08_tlep$r_tlesr2_bits;' } ka0c08_tlep$r_tlesr2_overlay;- unsigned char ka0c08_tlep$b_fill340 [60]; __union {* unsigned int ka0c08_ 2tlep$l_tlesr3; __struct {4 unsigned ka0c08_tlep$v_tlesr3_synd0 : 8;4 unsigned ka0c08_tlep$v_tlesr3_synd1 : 8;2 unsigned ka0c08_tlep$v_tlesr3_tde : 1;2 unsigned ka0c08_tlep$v_tlesr3_tce : 1;4 unsigned ka0c08_tlep$v_tlesr3_dvtce : 1;3 unsigned ka0c08_tlep$v_tlesr3_uecc : 1;4 unsigned ka0c08_tlep$v_tlesr3_cwecc : 1;4 unsigned ka0c08_tlep$v_tlesr3_crecc : 1;3 unsigned ka0c08_tlep$v_tlesr 23_cpu0 : 1;3 unsigned ka0c08_tlep$v_tlesr3_cpu1 : 1;1 unsigned ka0c08_tlep$v_tlesr3_f1 : 7;5 unsigned ka0c08_tlep$v_tlesr3_lofsyn : 1;( } ka0c08_tlep$r_tlesr3_bits;' } ka0c08_tlep$r_tlesr3_overlay;/ unsigned char ka0c08_tlep$b_fill350 [2236]; __union {- unsigned int ka0c08_tlep$l_tlmodcfg0; __struct {7 unsigned ka0c08_tlep$v_tlmodcfg0_frign : 1;6 unsigned ka0c08_tlep$v_tlmodcfg0_fde0 : 21;6 unsigned ka0c08_tlep$v_tlmodcfg0_fde1 : 1;8 unsigned ka0c08_tlep$v_tlmodcfg0_p1_ude : 1;9 unsigned ka0c08_tlep$v_tlmodcfg0_p1_crde : 1;8 unsigned ka0c08_tlep$v_tlmodcfg0_dly_in : 1;9 unsigned ka0c08_tlep$v_tlmodcfg0_dly_out : 1;9 unsigned ka0c08_tlep$v_tlmodcfg0_dpq_max : 3;9 unsigned ka0c08_tlep$v_tlmodcfg0_mmre_ds : 1;9 unsigned ka0c08_tlep$v_tlmodcfg0_fastfls : 1;9 unsigned ka0c08_tl 2ep$v_tlmodcfg0_delay_a : 1;9 unsigned ka0c08_tlep$v_tlmodcfg0_ilglcsr : 1;9 unsigned ka0c08_tlep$v_tlmodcfg0_e_slowr : 1;9 unsigned ka0c08_tlep$v_tlmodcfg0_asrt_ft : 1;9 unsigned ka0c08_tlep$v_tlmodcfg0_dtag_pe : 1;9 unsigned ka0c08_tlep$v_tlmodcfg0_dtag0_d : 1;9 unsigned ka0c08_tlep$v_tlmodcfg0_dtag1_d : 1;8 unsigned ka0c08_tlep$v_tlmodcfg0_d_wrap : 1;8 unsigned ka0c08_tlep$v_tlmodcfg0_bq_max : 3;9 2 unsigned ka0c08_tlep$v_tlmodcfg0_bc_size : 2;9 unsigned ka0c08_tlep$v_tlmodcfg0_fde_cmd : 4;6 unsigned ka0c08_tlep$v_tlmodcfg0_fsbe : 1;6 unsigned ka0c08_tlep$v_tlmodcfg0_fde2 : 1;6 unsigned ka0c08_tlep$v_tlmodcfg0_fde3 : 1;+ } ka0c08_tlep$r_tlmodcfg0_bits;* } ka0c08_tlep$r_tlmodcfg0_overlay;- unsigned char ka0c08_tlep$b_fill360 [60]; __union {. unsigned int ka0c08_tlep$l_tldtagdata; __struct 2 {6 unsigned ka0c08_tlep$v_tldtagdata_par : 1;8 unsigned ka0c08_tlep$v_tldtagdata_data : 17;6 unsigned ka0c08_tlep$v_tldtagdata_f1 : 14;, } ka0c08_tlep$r_tldtagdata_bits;+ } ka0c08_tlep$r_tldtagdata_overlay;- unsigned char ka0c08_tlep$b_fill370 [60]; __union {. unsigned int ka0c08_tlep$l_tldtagaddr; __struct {8 unsigned ka0c08_tlep$v_tldtagaddr_addr : 18;5 unsigned ka0c08_tlep$v_tldtagaddr_ 2f1 : 6;9 unsigned ka0c08_tlep$v_tldtagaddr_cpu_sl : 1;5 unsigned ka0c08_tlep$v_tldtagaddr_f2 : 7;, } ka0c08_tlep$r_tldtagaddr_bits;+ } ka0c08_tlep$r_tldtagaddr_overlay;- unsigned char ka0c08_tlep$b_fill380 [60]; __union {- unsigned int ka0c08_tlep$l_tlmodcfg1; __struct {9 unsigned ka0c08_tlep$v_tlmodcfg1_ovrtk_e : 1;8 unsigned ka0c08_tlep$v_tlmodcfg1_p0_rid : 3;8 unsigned ka0c08_tlep$v_t 2lmodcfg1_p1_rid : 3;9 unsigned ka0c08_tlep$v_tlmodcfg1_mbpr_ry : 2;9 unsigned ka0c08_tlep$v_tlmodcfg1_fault_d : 1;9 unsigned ka0c08_tlep$v_tlmodcfg1_fstrq_d : 1;9 unsigned ka0c08_tlep$v_tlmodcfg1_p0_rq_d : 1;9 unsigned ka0c08_tlep$v_tlmodcfg1_p1_rq_d : 1;9 unsigned ka0c08_tlep$v_tlmodcfg1_d_probe : 2;8 unsigned ka0c08_tlep$v_tlmodcfg1_fstpth : 1;9 unsigned ka0c08_tlep$v_tlmodcfg1_dlsb_pr : 1;9 2 unsigned ka0c08_tlep$v_tlmodcfg1_vic_skp : 1;9 unsigned ka0c08_tlep$v_tlmodcfg1_frce_sq : 1;8 unsigned ka0c08_tlep$v_tlmodcfg1_db_bub : 1;8 unsigned ka0c08_tlep$v_tlmodcfg1_fst_vq : 1;9 unsigned ka0c08_tlep$v_tlmodcfg1_fst_prq : 1;9 unsigned ka0c08_tlep$v_tlmodcfg1_buswrte : 1;9 unsigned ka0c08_tlep$v_tlmodcfg1_fst_wrt : 1;9 unsigned ka0c08_tlep$v_tlmodcfg1_frc_shr : 1;9 unsigned ka0c08_tlep$v_t 2lmodcfg1_vqrbctl : 1;9 unsigned ka0c08_tlep$v_tlmodcfg1_csr_siz : 1;4 unsigned ka0c08_tlep$v_tlmodcfg1_f1 : 5;+ } ka0c08_tlep$r_tlmodcfg1_bits;* } ka0c08_tlep$r_tlmodcfg1_overlay;- unsigned char ka0c08_tlep$b_fill390 [60]; __union {, unsigned int ka0c08_tlep$l_tlimask0; __struct {9 unsigned ka0c08_tlep$v_tlimask0_duart0en : 1;9 unsigned ka0c08_tlep$v_tlimask0_ipl14_en : 1;9 unsigned ka0c0 28_tlep$v_tlimask0_ipl15_en : 1;9 unsigned ka0c08_tlep$v_tlimask0_ipl16_en : 1;9 unsigned ka0c08_tlep$v_tlimask0_ipl17_en : 1;6 unsigned ka0c08_tlep$v_tlimask0_ip_en : 1;9 unsigned ka0c08_tlep$v_tlimask0_intim_en : 1;8 unsigned ka0c08_tlep$v_tlimask0_halt_en : 1;6 unsigned ka0c08_tlep$v_tlimask0_cp_en : 1;4 unsigned ka0c08_tlep$v_tlimask0_f1 : 23;* } ka0c08_tlep$r_tlimask0_bits;) } ka0c08_tlep$r_ 2tlimask0_overlay;- unsigned char ka0c08_tlep$b_fill400 [60]; __union {, unsigned int ka0c08_tlep$l_tlimask1; __struct {9 unsigned ka0c08_tlep$v_tlimask1_duart0en : 1;9 unsigned ka0c08_tlep$v_tlimask1_ipl14_en : 1;9 unsigned ka0c08_tlep$v_tlimask1_ipl15_en : 1;9 unsigned ka0c08_tlep$v_tlimask1_ipl16_en : 1;9 unsigned ka0c08_tlep$v_tlimask1_ipl17_en : 1;6 unsigned ka0c08_tlep$v_tlimask1_ip_en : 1; 29 unsigned ka0c08_tlep$v_tlimask1_intim_en : 1;8 unsigned ka0c08_tlep$v_tlimask1_halt_en : 1;6 unsigned ka0c08_tlep$v_tlimask1_cp_en : 1;4 unsigned ka0c08_tlep$v_tlimask1_f1 : 23;* } ka0c08_tlep$r_tlimask1_bits;) } ka0c08_tlep$r_tlimask1_overlay;- unsigned char ka0c08_tlep$b_fill410 [60]; __union {+ unsigned int ka0c08_tlep$l_tlisum0; __struct {9 unsigned ka0c08_tlep$v_tlisum0_duart0int : 1 2;9 unsigned ka0c08_tlep$v_tlisum0_ipl14_int : 1;9 unsigned ka0c08_tlep$v_tlisum0_ipl15_int : 1;9 unsigned ka0c08_tlep$v_tlisum0_ipl16_int : 1;9 unsigned ka0c08_tlep$v_tlisum0_ipl17_int : 1;6 unsigned ka0c08_tlep$v_tlisum0_ip_int : 1;9 unsigned ka0c08_tlep$v_tlisum0_intim_int : 1;5 unsigned ka0c08_tlep$v_tlisum0_ipl14 : 5;5 unsigned ka0c08_tlep$v_tlisum0_ipl15 : 5;5 unsigned ka0c08_tlep$v 2_tlisum0_ipl16 : 5;5 unsigned ka0c08_tlep$v_tlisum0_ipl17 : 5;7 unsigned ka0c08_tlep$v_tlisum0_cp_halt : 1;4 unsigned ka0c08_tlep$v_tlisum0_halt : 1;2 unsigned ka0c08_tlep$v_tlisum0_f1 : 3;) } ka0c08_tlep$r_tlisum0_bits;( } ka0c08_tlep$r_tlisum0_overlay;- unsigned char ka0c08_tlep$b_fill420 [60]; __union {+ unsigned int ka0c08_tlep$l_tlisum1; __struct {9 unsigned ka0c08_tlep$v_tlisum1_dua 2rt0int : 1;9 unsigned ka0c08_tlep$v_tlisum1_ipl14_int : 1;9 unsigned ka0c08_tlep$v_tlisum1_ipl15_int : 1;9 unsigned ka0c08_tlep$v_tlisum1_ipl16_int : 1;9 unsigned ka0c08_tlep$v_tlisum1_ipl17_int : 1;6 unsigned ka0c08_tlep$v_tlisum1_ip_int : 1;9 unsigned ka0c08_tlep$v_tlisum1_intim_int : 1;5 unsigned ka0c08_tlep$v_tlisum1_ipl14 : 5;5 unsigned ka0c08_tlep$v_tlisum1_ipl15 : 5;5 unsigned ka0 2c08_tlep$v_tlisum1_ipl16 : 5;5 unsigned ka0c08_tlep$v_tlisum1_ipl17 : 5;7 unsigned ka0c08_tlep$v_tlisum1_cp_halt : 1;4 unsigned ka0c08_tlep$v_tlisum1_halt : 1;2 unsigned ka0c08_tlep$v_tlisum1_f1 : 3;) } ka0c08_tlep$r_tlisum1_bits;( } ka0c08_tlep$r_tlisum1_overlay;- unsigned char ka0c08_tlep$b_fill430 [60]; __union {+ unsigned int ka0c08_tlep$l_tlcon00; __struct {3 unsigned ka0c08_tlep$v_t 2lcon00_f1 : 32;) } ka0c08_tlep$r_tlcon00_bits;( } ka0c08_tlep$r_tlcon00_overlay;- unsigned char ka0c08_tlep$b_fill440 [60]; __union {, unsigned int ka0c08_tlep$l_tlcon00a; __struct {4 unsigned ka0c08_tlep$v_tlcon00a_f1 : 32;* } ka0c08_tlep$r_tlcon00a_bits;) } ka0c08_tlep$r_tlcon00a_overlay;- unsigned char ka0c08_tlep$b_fill450 [60]; __union {, unsigned int ka0c08_tlep$l_tlcon00b; __struct !2{4 unsigned ka0c08_tlep$v_tlcon00b_f1 : 32;* } ka0c08_tlep$r_tlcon00b_bits;) } ka0c08_tlep$r_tlcon00b_overlay;- unsigned char ka0c08_tlep$b_fill460 [60]; __union {, unsigned int ka0c08_tlep$l_tlcon00c; __struct {4 unsigned ka0c08_tlep$v_tlcon00c_f1 : 32;* } ka0c08_tlep$r_tlcon00c_bits;) } ka0c08_tlep$r_tlcon00c_overlay;- unsigned char ka0c08_tlep$b_fill470 [60]; __union {+ unsigned int k "2a0c08_tlep$l_tlcon10; __struct {3 unsigned ka0c08_tlep$v_tlcon10_f1 : 32;) } ka0c08_tlep$r_tlcon10_bits;( } ka0c08_tlep$r_tlcon10_overlay;- unsigned char ka0c08_tlep$b_fill480 [60]; __union {, unsigned int ka0c08_tlep$l_tlcon10a; __struct {4 unsigned ka0c08_tlep$v_tlcon10a_f1 : 32;* } ka0c08_tlep$r_tlcon10a_bits;) } ka0c08_tlep$r_tlcon10a_overlay;- unsigned char ka0c08_tlep$b_fill490 [60];#2 __union {, unsigned int ka0c08_tlep$l_tlcon10b; __struct {4 unsigned ka0c08_tlep$v_tlcon10b_f1 : 32;* } ka0c08_tlep$r_tlcon10b_bits;) } ka0c08_tlep$r_tlcon10b_overlay;- unsigned char ka0c08_tlep$b_fill500 [60]; __union {, unsigned int ka0c08_tlep$l_tlcon10c; __struct {4 unsigned ka0c08_tlep$v_tlcon10c_f1 : 32;* } ka0c08_tlep$r_tlcon10c_bits;) } ka0c08_tlep$r_tlcon10c_overlay;- $2unsigned char ka0c08_tlep$b_fill510 [60]; __union {+ unsigned int ka0c08_tlep$l_tlcon01; __struct {3 unsigned ka0c08_tlep$v_tlcon01_f1 : 32;) } ka0c08_tlep$r_tlcon01_bits;( } ka0c08_tlep$r_tlcon01_overlay;- unsigned char ka0c08_tlep$b_fill520 [60]; __union {+ unsigned int ka0c08_tlep$l_tlcon11; __struct {3 unsigned ka0c08_tlep$v_tlcon11_f1 : 32;) } ka0c08_tlep$r_tlcon11_bits;( %2} ka0c08_tlep$r_tlcon11_overlay;. unsigned char ka0c08_tlep$b_fill530 [188]; __union {* unsigned int ka0c08_tlep$l_tccerr; __struct {9 unsigned ka0c08_tlep$v_tccerr_p0_mbpr_to : 1;9 unsigned ka0c08_tlep$v_tccerr_p1_mbpr_to : 1;4 unsigned ka0c08_tlep$v_tccerr_dtpe0 : 1;4 unsigned ka0c08_tlep$v_tccerr_dtpe1 : 1;6 unsigned ka0c08_tlep$v_tccerr_sysderr : 1;9 unsigned ka0c08_tlep$v_tccerr_wspc_rd_er : 1; &27 unsigned ka0c08_tlep$v_tccerr_sysfault : 2;9 unsigned ka0c08_tlep$v_tccerr_fault_asrt : 1;9 unsigned ka0c08_tlep$v_tccerr_p0_ftlmmre : 1;9 unsigned ka0c08_tlep$v_tccerr_p1_ftlmmre : 1;6 unsigned ka0c08_tlep$v_tccerr_p0_mmre : 1;6 unsigned ka0c08_tlep$v_tccerr_p1_mmre : 1;9 unsigned ka0c08_tlep$v_tccerr_csr_wr_nxm : 1;8 unsigned ka0c08_tlep$v_tccerr_csr_xactn : 1;1 unsigned ka0c08_tlep$v_t '2ccerr_f1 : 1;6 unsigned ka0c08_tlep$v_tccerr_tcc_rev : 4;9 unsigned ka0c08_tlep$v_tccerr_p0_ilglcsr : 1;9 unsigned ka0c08_tlep$v_tccerr_p1_ilglcsr : 1;2 unsigned ka0c08_tlep$v_tccerr_f2 : 10;( } ka0c08_tlep$r_tccerr_bits;' } ka0c08_tlep$r_tccerr_overlay;- unsigned char ka0c08_tlep$b_fill540 [60]; __union {* unsigned int ka0c08_tlep$l_tdierr; __struct {1 unsigned ka0c08_tlep$v_tdierr_f1 : 2 (2;3 unsigned ka0c08_tlep$v_tdierr_gbto : 1;2 unsigned ka0c08_tlep$v_tdierr_f2 : 29;( } ka0c08_tlep$r_tdierr_bits;' } ka0c08_tlep$r_tdierr_overlay;. unsigned char ka0c08_tlep$b_fill550 [124]; __union {+ unsigned int ka0c08_tlep$l_tl6_vmg; __struct {2 unsigned ka0c08_tlep$v_tl6_vmg_5p : 1;2 unsigned ka0c08_tlep$v_tl6_vmg_5m : 1;2 unsigned ka0c08_tlep$v_tl6_vmg_3p : 1;2 unsigned ka0 )2c08_tlep$v_tl6_vmg_3m : 1;3 unsigned ka0c08_tlep$v_tl6_vmg_f1 : 28;) } ka0c08_tlep$r_tl6_vmg_bits;( } ka0c08_tlep$r_tl6_vmg_overlay;- unsigned char ka0c08_tlep$b_fill570 [60]; __union {+ unsigned int ka0c08_tlep$l_tl6werr; __struct {6 unsigned ka0c08_tlep$v_tl6werr_select : 2;3 unsigned ka0c08_tlep$v_tl6werr_f1 : 30;0 } ka0c08_tlep$r_tl6werr_select_bits; __struct {9 unsigned ka0 *2c08_tlep$v_tl6werr_r0_rd_pnd : 1;5 unsigned ka0c08_tlep$v_tl6werr_r0_f1 : 2;8 unsigned ka0c08_tlep$v_tl6werr_r0_addr : 17;6 unsigned ka0c08_tlep$v_tl6werr_r0_f2 : 12;1 } ka0c08_tlep$r_tl6werr_register0_bi; __struct {8 unsigned ka0c08_tlep$v_tl6werr_r1_addr : 19;6 unsigned ka0c08_tlep$v_tl6werr_r1_f1 : 13;1 } ka0c08_tlep$r_tl6werr_register1_bi; __struct {9 unsigned ka0c08_tlep$v_tl6 +2werr_r2_rd_pnd : 1;5 unsigned ka0c08_tlep$v_tl6werr_r2_f1 : 2;8 unsigned ka0c08_tlep$v_tl6werr_r2_addr : 17;6 unsigned ka0c08_tlep$v_tl6werr_r2_f2 : 12;1 } ka0c08_tlep$r_tl6werr_register2_bi; __struct {8 unsigned ka0c08_tlep$v_tl6werr_r3_addr : 19;6 unsigned ka0c08_tlep$v_tl6werr_r3_f1 : 13;1 } ka0c08_tlep$r_tl6werr_register3_bi;( } ka0c08_tlep$r_tl6werr_overlay;. unsigned char ka0c08_tlep$b_,2fill580 [508]; __union {, unsigned int ka0c08_tlep$l_tldtagex; __struct {4 unsigned ka0c08_tlep$v_tldtagex_f1 : 32;* } ka0c08_tlep$r_tldtagex_bits;) } ka0c08_tlep$r_tldtagex_overlay;- unsigned char ka0c08_tlep$b_fill610 [60]; __union {- unsigned int ka0c08_tlep$l_tlloopbck; __struct {5 unsigned ka0c08_tlep$v_tlloopbck_f1 : 32;+ } ka0c08_tlep$r_tlloopbck_bits;* } ka0c08_tlep$r_tllo -2opbck_overlay;- unsigned char ka0c08_tlep$b_fill620 [60]; } KA0C08_TLEP; #if !defined(__VAXC)K#define ka0c08_tlep$l_tldev ka0c08_tlep$r_tldev_overlay.ka0c08_tlep$l_tldevp#define ka0c08_tlep$v_tldev_dtype ka0c08_tlep$r_tldev_overlay.ka0c08_tlep$r_tldev_bits.ka0c08_tlep$v_tldev_dtypep#define ka0c08_tlep$v_tldev_swrev ka0c08_tlep$r_tldev_overlay.ka0c08_tlep$r_tldev_bits.ka0c08_tlep$v_tldev_swrevp#define ka0c08_tlep$v_tldev_hwrev ka0c08_tlep$r_tldev_overlay.ka0c08_tlep$r_tldev_bits.ka0.2c08_tlep$v_tldev_hwrevK#define ka0c08_tlep$l_tlber ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$l_tlbern#define ka0c08_tlep$v_tlber_atce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_atcel#define ka0c08_tlep$v_tlber_ape ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_apel#define ka0c08_tlep$v_tlber_bbe ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_bben#define ka0c08_tlep$v_tlber_lkto ka0c08_tlep$r_tlber_overlay.ka0c08_tlep/2$r_tlber_bits.ka0c08_tlep$v_tlber_lktol#define ka0c08_tlep$v_tlber_nae ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_naen#define ka0c08_tlep$v_tlber_rtce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_rtcer#define ka0c08_tlep$v_tlber_acktce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_acktcen#define ka0c08_tlep$v_tlber_mmre ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_mmren#define ka0c08_t02lep$v_tlber_fnae ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_fnaep#define ka0c08_tlep$v_tlber_reqde ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_reqden#define ka0c08_tlep$v_tlber_atde ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_atdel#define ka0c08_tlep$v_tlber_ude ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_uden#define ka0c08_tlep$v_tlber_cwde ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r12_tlber_bits.ka0c08_tlep$v_tlber_cwden#define ka0c08_tlep$v_tlber_crde ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_crdel#define ka0c08_tlep$v_tlber_ds0 ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_ds0l#define ka0c08_tlep$v_tlber_ds1 ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_ds1l#define ka0c08_tlep$v_tlber_ds2 ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_ds2l#define ka0c08_tlep$v_tlbe22r_ds3 ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_ds3n#define ka0c08_tlep$v_tlber_dtde ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_dtdep#define ka0c08_tlep$v_tlber_fdtce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_fdtcep#define ka0c08_tlep$v_tlber_uacke ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_uackep#define ka0c08_tlep$v_tlber_abtce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_32bits.ka0c08_tlep$v_tlber_abtcep#define ka0c08_tlep$v_tlber_dctce ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_dctcen#define ka0c08_tlep$v_tlber_seqe ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_seqel#define ka0c08_tlep$v_tlber_dse ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_dsel#define ka0c08_tlep$v_tlber_dto ka0c08_tlep$r_tlber_overlay.ka0c08_tlep$r_tlber_bits.ka0c08_tlep$v_tlber_dtoK#define ka0c08_tlep$l_tlcnr 42ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$l_tlcnrn#define ka0c08_tlep$v_tlcnr_cwdd ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_cwddn#define ka0c08_tlep$v_tlcnr_crdd ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_crddn#define ka0c08_tlep$v_tlcnr_dtod ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_dtodt#define ka0c08_tlep$v_tlcnr_node_id ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_node_idn#d52efine ka0c08_tlep$v_tlcnr_vcnt ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_vcntp#define ka0c08_tlep$v_tlcnr_stf_a ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_stf_ap#define ka0c08_tlep$v_tlcnr_stf_b ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_stf_br#define ka0c08_tlep$v_tlcnr_halt_a ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_halt_ar#define ka0c08_tlep$v_tlcnr_halt_b ka0c08_tlep$r_tlc62nr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_halt_bn#define ka0c08_tlep$v_tlcnr_nrst ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_nrstn#define ka0c08_tlep$v_tlcnr_lofe ka0c08_tlep$r_tlcnr_overlay.ka0c08_tlep$r_tlcnr_bits.ka0c08_tlep$v_tlcnr_lofeK#define ka0c08_tlep$l_tlvid ka0c08_tlep$r_tlvid_overlay.ka0c08_tlep$l_tlvidd#define ka0c08_tlep$v_vid_a ka0c08_tlep$r_tlvid_overlay.ka0c08_tlep$r_tlvid_bits.ka0c08_tlep$v_vid_ad#define ka0c08_tlep$v_vid_b ka0c08_tle72p$r_tlvid_overlay.ka0c08_tlep$r_tlvid_bits.ka0c08_tlep$v_vid_bN#define ka0c08_tlep$l_tlmmr0 ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$l_tlmmr0x#define ka0c08_tlep$v_tlmmr0_intmask ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_intmaskx#define ka0c08_tlep$v_tlmmr0_adrmask ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_adrmaskt#define ka0c08_tlep$v_tlmmr0_intlv ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_intlvt82#define ka0c08_tlep$v_tlmmr0_sbank ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_sbankx#define ka0c08_tlep$v_tlmmr0_address ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_addresst#define ka0c08_tlep$v_tlmmr0_valid ka0c08_tlep$r_tlmmr0_overlay.ka0c08_tlep$r_tlmmr0_bits.ka0c08_tlep$v_tlmmr0_validN#define ka0c08_tlep$l_tlmmr1 ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$l_tlmmr1x#define ka0c08_tlep$v_tlmmr1_intmask ka0c08_tlep$r_tlmmr1_overlay.ka920c08_tlep$r_tlmmr1_bits.ka0c08_tlep$v_tlmmr1_intmaskx#define ka0c08_tlep$v_tlmmr1_adrmask ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$r_tlmmr1_bits.ka0c08_tlep$v_tlmmr1_adrmaskt#define ka0c08_tlep$v_tlmmr1_intlv ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$r_tlmmr1_bits.ka0c08_tlep$v_tlmmr1_intlvt#define ka0c08_tlep$v_tlmmr1_sbank ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$r_tlmmr1_bits.ka0c08_tlep$v_tlmmr1_sbankx#define ka0c08_tlep$v_tlmmr1_address ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$r_tlmmr1_bits.ka:20c08_tlep$v_tlmmr1_addresst#define ka0c08_tlep$v_tlmmr1_valid ka0c08_tlep$r_tlmmr1_overlay.ka0c08_tlep$r_tlmmr1_bits.ka0c08_tlep$v_tlmmr1_validN#define ka0c08_tlep$l_tlmmr2 ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$l_tlmmr2x#define ka0c08_tlep$v_tlmmr2_intmask ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_intmaskx#define ka0c08_tlep$v_tlmmr2_adrmask ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_adrmaskt#define ka0c08_tlep$v_tlmmr2_intlv k;2a0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_intlvt#define ka0c08_tlep$v_tlmmr2_sbank ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_sbankx#define ka0c08_tlep$v_tlmmr2_address ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_addresst#define ka0c08_tlep$v_tlmmr2_valid ka0c08_tlep$r_tlmmr2_overlay.ka0c08_tlep$r_tlmmr2_bits.ka0c08_tlep$v_tlmmr2_validN#define ka0c08_tlep$l_tlmmr3 ka0c08_tlep$r_tlmmr3_overlay.ka0c08_t<2lep$l_tlmmr3x#define ka0c08_tlep$v_tlmmr3_intmask ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_intmaskx#define ka0c08_tlep$v_tlmmr3_adrmask ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_adrmaskt#define ka0c08_tlep$v_tlmmr3_intlv ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_intlvt#define ka0c08_tlep$v_tlmmr3_sbank ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_sbankx#define ka0c=208_tlep$v_tlmmr3_address ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_addresst#define ka0c08_tlep$v_tlmmr3_valid ka0c08_tlep$r_tlmmr3_overlay.ka0c08_tlep$r_tlmmr3_bits.ka0c08_tlep$v_tlmmr3_validN#define ka0c08_tlep$l_tlmmr4 ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$l_tlmmr4x#define ka0c08_tlep$v_tlmmr4_intmask ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$r_tlmmr4_bits.ka0c08_tlep$v_tlmmr4_intmaskx#define ka0c08_tlep$v_tlmmr4_adrmask ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tle>2p$r_tlmmr4_bits.ka0c08_tlep$v_tlmmr4_adrmaskt#define ka0c08_tlep$v_tlmmr4_intlv ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$r_tlmmr4_bits.ka0c08_tlep$v_tlmmr4_intlvt#define ka0c08_tlep$v_tlmmr4_sbank ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$r_tlmmr4_bits.ka0c08_tlep$v_tlmmr4_sbankx#define ka0c08_tlep$v_tlmmr4_address ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$r_tlmmr4_bits.ka0c08_tlep$v_tlmmr4_addresst#define ka0c08_tlep$v_tlmmr4_valid ka0c08_tlep$r_tlmmr4_overlay.ka0c08_tlep$r_tlmmr4_bits.ka0c08_tlep$?2v_tlmmr4_validN#define ka0c08_tlep$l_tlmmr5 ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$l_tlmmr5x#define ka0c08_tlep$v_tlmmr5_intmask ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_intmaskx#define ka0c08_tlep$v_tlmmr5_adrmask ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_adrmaskt#define ka0c08_tlep$v_tlmmr5_intlv ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_intlvt#define ka0c08_tlep$v_tlmmr5_sbank ka0c08_tlep$r@2_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_sbankx#define ka0c08_tlep$v_tlmmr5_address ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_addresst#define ka0c08_tlep$v_tlmmr5_valid ka0c08_tlep$r_tlmmr5_overlay.ka0c08_tlep$r_tlmmr5_bits.ka0c08_tlep$v_tlmmr5_validN#define ka0c08_tlep$l_tlmmr6 ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$l_tlmmr6x#define ka0c08_tlep$v_tlmmr6_intmask ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_intA2maskx#define ka0c08_tlep$v_tlmmr6_adrmask ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_adrmaskt#define ka0c08_tlep$v_tlmmr6_intlv ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_intlvt#define ka0c08_tlep$v_tlmmr6_sbank ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_sbankx#define ka0c08_tlep$v_tlmmr6_address ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_addresst#define ka0c08_tlep$B2v_tlmmr6_valid ka0c08_tlep$r_tlmmr6_overlay.ka0c08_tlep$r_tlmmr6_bits.ka0c08_tlep$v_tlmmr6_validN#define ka0c08_tlep$l_tlmmr7 ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$l_tlmmr7x#define ka0c08_tlep$v_tlmmr7_intmask ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7_bits.ka0c08_tlep$v_tlmmr7_intmaskx#define ka0c08_tlep$v_tlmmr7_adrmask ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7_bits.ka0c08_tlep$v_tlmmr7_adrmaskt#define ka0c08_tlep$v_tlmmr7_intlv ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7C2_bits.ka0c08_tlep$v_tlmmr7_intlvt#define ka0c08_tlep$v_tlmmr7_sbank ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7_bits.ka0c08_tlep$v_tlmmr7_sbankx#define ka0c08_tlep$v_tlmmr7_address ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7_bits.ka0c08_tlep$v_tlmmr7_addresst#define ka0c08_tlep$v_tlmmr7_valid ka0c08_tlep$r_tlmmr7_overlay.ka0c08_tlep$r_tlmmr7_bits.ka0c08_tlep$v_tlmmr7_validN#define ka0c08_tlep$l_tlesr0 ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$l_tlesr0t#define ka0c08_tlep$v_tlesr0_synd0D2 ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_synd0t#define ka0c08_tlep$v_tlesr0_synd1 ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_synd1p#define ka0c08_tlep$v_tlesr0_tde ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_tdep#define ka0c08_tlep$v_tlesr0_tce ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_tcet#define ka0c08_tlep$v_tlesr0_dvtce ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$E2r_tlesr0_bits.ka0c08_tlep$v_tlesr0_dvtcer#define ka0c08_tlep$v_tlesr0_uecc ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_uecct#define ka0c08_tlep$v_tlesr0_cwecc ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_cwecct#define ka0c08_tlep$v_tlesr0_crecc ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_creccr#define ka0c08_tlep$v_tlesr0_cpu0 ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_cpF2u0r#define ka0c08_tlep$v_tlesr0_cpu1 ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_cpu1v#define ka0c08_tlep$v_tlesr0_lofsyn ka0c08_tlep$r_tlesr0_overlay.ka0c08_tlep$r_tlesr0_bits.ka0c08_tlep$v_tlesr0_lofsynN#define ka0c08_tlep$l_tlesr1 ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$l_tlesr1t#define ka0c08_tlep$v_tlesr1_synd0 ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_synd0t#define ka0c08_tlep$v_tlesr1_synd1 ka0c08_tlep$r_tlesr1_overlay.ka0cG208_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_synd1p#define ka0c08_tlep$v_tlesr1_tde ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_tdep#define ka0c08_tlep$v_tlesr1_tce ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_tcet#define ka0c08_tlep$v_tlesr1_dvtce ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_dvtcer#define ka0c08_tlep$v_tlesr1_uecc ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_H2uecct#define ka0c08_tlep$v_tlesr1_cwecc ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_cwecct#define ka0c08_tlep$v_tlesr1_crecc ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_creccr#define ka0c08_tlep$v_tlesr1_cpu0 ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_cpu0r#define ka0c08_tlep$v_tlesr1_cpu1 ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_cpu1v#define ka0c08_tlep$v_tlesr1_lofI2syn ka0c08_tlep$r_tlesr1_overlay.ka0c08_tlep$r_tlesr1_bits.ka0c08_tlep$v_tlesr1_lofsynN#define ka0c08_tlep$l_tlesr2 ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$l_tlesr2t#define ka0c08_tlep$v_tlesr2_synd0 ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_synd0t#define ka0c08_tlep$v_tlesr2_synd1 ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_synd1p#define ka0c08_tlep$v_tlesr2_tde ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_J2tlesr2_tdep#define ka0c08_tlep$v_tlesr2_tce ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_tcet#define ka0c08_tlep$v_tlesr2_dvtce ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_dvtcer#define ka0c08_tlep$v_tlesr2_uecc ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_uecct#define ka0c08_tlep$v_tlesr2_cwecc ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_cwecct#define ka0c08_tlep$v_tlesr2K2_crecc ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_creccr#define ka0c08_tlep$v_tlesr2_cpu0 ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_cpu0r#define ka0c08_tlep$v_tlesr2_cpu1 ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_cpu1v#define ka0c08_tlep$v_tlesr2_lofsyn ka0c08_tlep$r_tlesr2_overlay.ka0c08_tlep$r_tlesr2_bits.ka0c08_tlep$v_tlesr2_lofsynN#define ka0c08_tlep$l_tlesr3 ka0c08_tlep$r_tlesr3_overlay.ka0c08L2_tlep$l_tlesr3t#define ka0c08_tlep$v_tlesr3_synd0 ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_synd0t#define ka0c08_tlep$v_tlesr3_synd1 ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_synd1p#define ka0c08_tlep$v_tlesr3_tde ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_tdep#define ka0c08_tlep$v_tlesr3_tce ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_tcet#define ka0c08_tlep$v_tlesM2r3_dvtce ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_dvtcer#define ka0c08_tlep$v_tlesr3_uecc ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_uecct#define ka0c08_tlep$v_tlesr3_cwecc ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_cwecct#define ka0c08_tlep$v_tlesr3_crecc ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_creccr#define ka0c08_tlep$v_tlesr3_cpu0 ka0c08_tlep$r_tlesr3_overlayN2.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_cpu0r#define ka0c08_tlep$v_tlesr3_cpu1 ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_cpu1v#define ka0c08_tlep$v_tlesr3_lofsyn ka0c08_tlep$r_tlesr3_overlay.ka0c08_tlep$r_tlesr3_bits.ka0c08_tlep$v_tlesr3_lofsynW#define ka0c08_tlep$l_tlmodcfg0 ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$l_tlmodcfg0#define ka0c08_tlep$v_tlmodcfg0_frign ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_friO2gn~#define ka0c08_tlep$v_tlmodcfg0_fde0 ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fde0~#define ka0c08_tlep$v_tlmodcfg0_fde1 ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fde1#define ka0c08_tlep$v_tlmodcfg0_p1_ude ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_p1_ude#define ka0c08_tlep$v_tlmodcfg0_p1_crde ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$vP2_tlmodcfg0_p1_crde#define ka0c08_tlep$v_tlmodcfg0_dly_in ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dly_in#define ka0c08_tlep$v_tlmodcfg0_dly_out ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dly_out#define ka0c08_tlep$v_tlmodcfg0_dpq_max ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dpq_max#define ka0c08_tlep$v_tlmodcfg0_mmre_ds ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_Q2tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_mmre_ds#define ka0c08_tlep$v_tlmodcfg0_fastfls ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fastfls#define ka0c08_tlep$v_tlmodcfg0_delay_a ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_delay_a#define ka0c08_tlep$v_tlmodcfg0_ilglcsr ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_ilglcsr#define ka0c08_tlep$v_tlmodcfg0_e_slowr ka0c08_tlep$r_tlR2modcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_e_slowr#define ka0c08_tlep$v_tlmodcfg0_asrt_ft ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_asrt_ft#define ka0c08_tlep$v_tlmodcfg0_dtag_pe ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dtag_pe#define ka0c08_tlep$v_tlmodcfg0_dtag0_d ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dtag0_d#define ka0c08_tlep$v_tlmoS2dcfg0_dtag1_d ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_dtag1_d#define ka0c08_tlep$v_tlmodcfg0_d_wrap ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_d_wrap#define ka0c08_tlep$v_tlmodcfg0_bq_max ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_bq_max#define ka0c08_tlep$v_tlmodcfg0_bc_size ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_bc_sizeT2#define ka0c08_tlep$v_tlmodcfg0_fde_cmd ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fde_cmd~#define ka0c08_tlep$v_tlmodcfg0_fsbe ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fsbe~#define ka0c08_tlep$v_tlmodcfg0_fde2 ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmodcfg0_fde2~#define ka0c08_tlep$v_tlmodcfg0_fde3 ka0c08_tlep$r_tlmodcfg0_overlay.ka0c08_tlep$r_tlmodcfg0_bits.ka0c08_tlep$v_tlmoU2dcfg0_fde3Z#define ka0c08_tlep$l_tldtagdata ka0c08_tlep$r_tldtagdata_overlay.ka0c08_tlep$l_tldtagdata#define ka0c08_tlep$v_tldtagdata_par ka0c08_tlep$r_tldtagdata_overlay.ka0c08_tlep$r_tldtagdata_bits.ka0c08_tlep$v_tldtagdata_par#define ka0c08_tlep$v_tldtagdata_data ka0c08_tlep$r_tldtagdata_overlay.ka0c08_tlep$r_tldtagdata_bits.ka0c08_tlep$v_tldtagdata_dataZ#define ka0c08_tlep$l_tldtagaddr ka0c08_tlep$r_tldtagaddr_overlay.ka0c08_tlep$l_tldtagaddr#define ka0c08_tlep$v_tldtagaddr_addr ka0c08_tleV2p$r_tldtagaddr_overlay.ka0c08_tlep$r_tldtagaddr_bits.ka0c08_tlep$v_tldtagaddr_addr#define ka0c08_tlep$v_tldtagaddr_cpu_sl ka0c08_tlep$r_tldtagaddr_overlay.ka0c08_tlep$r_tldtagaddr_bits.ka0c08_tlep$v_tldtagaddr_cpu\_slW#define ka0c08_tlep$l_tlmodcfg1 ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$l_tlmodcfg1#define ka0c08_tlep$v_tlmodcfg1_ovrtk_e ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_ovrtk_e#define ka0c08_tlep$v_tlmodcfg1_p0_rid ka0c08_tlep$r_tlmodW2cfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_p0_rid#define ka0c08_tlep$v_tlmodcfg1_p1_rid ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_p1_rid#define ka0c08_tlep$v_tlmodcfg1_mbpr_ry ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_mbpr_ry#define ka0c08_tlep$v_tlmodcfg1_fault_d ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fault_d#define ka0c08_tlep$v_tlmodcfg1_X2fstrq_d ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fstrq_d#define ka0c08_tlep$v_tlmodcfg1_p0_rq_d ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_p0_rq_d#define ka0c08_tlep$v_tlmodcfg1_p1_rq_d ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_p1_rq_d#define ka0c08_tlep$v_tlmodcfg1_d_probe ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_d_probe#dY2efine ka0c08_tlep$v_tlmodcfg1_fstpth ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fstpth#define ka0c08_tlep$v_tlmodcfg1_dlsb_pr ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_dlsb_pr#define ka0c08_tlep$v_tlmodcfg1_vic_skp ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_vic_skp#define ka0c08_tlep$v_tlmodcfg1_frce_sq ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_Z2tlep$v_tlmodcfg1_frce_sq#define ka0c08_tlep$v_tlmodcfg1_db_bub ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_db_bub#define ka0c08_tlep$v_tlmodcfg1_fst_vq ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fst_vq#define ka0c08_tlep$v_tlmodcfg1_fst_prq ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fst_prq#define ka0c08_tlep$v_tlmodcfg1_buswrte ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tle[2p$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_buswrte#define ka0c08_tlep$v_tlmodcfg1_fst_wrt ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_fst_wrt#define ka0c08_tlep$v_tlmodcfg1_frc_shr ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_frc_shr#define ka0c08_tlep$v_tlmodcfg1_vqrbctl ka0c08_tlep$r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_vqrbctl#define ka0c08_tlep$v_tlmodcfg1_csr_siz ka0c08_tlep$\2r_tlmodcfg1_overlay.ka0c08_tlep$r_tlmodcfg1_bits.ka0c08_tlep$v_tlmodcfg1_csr_sizT#define ka0c08_tlep$l_tlimask0 ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$l_tlimask0#define ka0c08_tlep$v_tlimask0_duart0en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_duart0en#define ka0c08_tlep$v_tlimask0_ipl14_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_ipl14_en#define ka0c08_tlep$v_tlimask0_ipl15_en ka0c08_tlep$r_tlimask0_overlay.ka0]2c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_ipl15_en#define ka0c08_tlep$v_tlimask0_ipl16_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_ipl16_en#define ka0c08_tlep$v_tlimask0_ipl17_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_ipl17_en|#define ka0c08_tlep$v_tlimask0_ip_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_ip_en#define ka0c08_tlep$v_tlimask0_intim_en ka0c08_tlep$r_tlim^2ask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_intim_en#define ka0c08_tlep$v_tlimask0_halt_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_halt_en|#define ka0c08_tlep$v_tlimask0_cp_en ka0c08_tlep$r_tlimask0_overlay.ka0c08_tlep$r_tlimask0_bits.ka0c08_tlep$v_tlimask0_cp_enT#define ka0c08_tlep$l_tlimask1 ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$l_tlimask1#define ka0c08_tlep$v_tlimask1_duart0en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlima_2sk1_bits.ka0c08_tlep$v_tlimask1_duart0en#define ka0c08_tlep$v_tlimask1_ipl14_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_ipl14_en#define ka0c08_tlep$v_tlimask1_ipl15_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_ipl15_en#define ka0c08_tlep$v_tlimask1_ipl16_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_ipl16_en#define ka0c08_tlep$v_tlimask1_ipl17_en ka0c08_tlep$r_tlimask1_overl`2ay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_ipl17_en|#define ka0c08_tlep$v_tlimask1_ip_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_ip_en#define ka0c08_tlep$v_tlimask1_intim_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_intim_en#define ka0c08_tlep$v_tlimask1_halt_en ka0c08_tlep$r_tlimask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_halt_en|#define ka0c08_tlep$v_tlimask1_cp_en ka0c08_tlep$r_tlia2mask1_overlay.ka0c08_tlep$r_tlimask1_bits.ka0c08_tlep$v_tlimask1_cp_enQ#define ka0c08_tlep$l_tlisum0 ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$l_tlisum0#define ka0c08_tlep$v_tlisum0_duart0int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_duart0int#define ka0c08_tlep$v_tlisum0_ipl14_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl14_int#define ka0c08_tlep$v_tlisum0_ipl15_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisumb20_bits.ka0c08_tlep$v_tlisum0_ipl15_int#define ka0c08_tlep$v_tlisum0_ipl16_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl16_int#define ka0c08_tlep$v_tlisum0_ipl17_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl17_intz#define ka0c08_tlep$v_tlisum0_ip_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ip_int#define ka0c08_tlep$v_tlisum0_intim_int ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$c2r_tlisum0_bits.ka0c08_tlep$v_tlisum0_intim_intx#define ka0c08_tlep$v_tlisum0_ipl14 ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl14x#define ka0c08_tlep$v_tlisum0_ipl15 ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl15x#define ka0c08_tlep$v_tlisum0_ipl16 ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_ipl16x#define ka0c08_tlep$v_tlisum0_ipl17 ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bitsd2.ka0c08_tlep$v_tlisum0_ipl17|#define ka0c08_tlep$v_tlisum0_cp_halt ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_cp_haltv#define ka0c08_tlep$v_tlisum0_halt ka0c08_tlep$r_tlisum0_overlay.ka0c08_tlep$r_tlisum0_bits.ka0c08_tlep$v_tlisum0_haltQ#define ka0c08_tlep$l_tlisum1 ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$l_tlisum1#define ka0c08_tlep$v_tlisum1_duart0int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_duart0int#define ka0c08_te2lep$v_tlisum1_ipl14_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl14_int#define ka0c08_tlep$v_tlisum1_ipl15_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl15_int#define ka0c08_tlep$v_tlisum1_ipl16_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl16_int#define ka0c08_tlep$v_tlisum1_ipl17_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl17_intz#df2efine ka0c08_tlep$v_tlisum1_ip_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ip_int#define ka0c08_tlep$v_tlisum1_intim_int ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_intim_intx#define ka0c08_tlep$v_tlisum1_ipl14 ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl14x#define ka0c08_tlep$v_tlisum1_ipl15 ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl15x#define kag20c08_tlep$v_tlisum1_ipl16 ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl16x#define ka0c08_tlep$v_tlisum1_ipl17 ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_ipl17|#define ka0c08_tlep$v_tlisum1_cp_halt ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_cp_haltv#define ka0c08_tlep$v_tlisum1_halt ka0c08_tlep$r_tlisum1_overlay.ka0c08_tlep$r_tlisum1_bits.ka0c08_tlep$v_tlisum1_haltQ#define ka0c08_tlep$l_tlcoh2n00 ka0c08_tlep$r_tlcon00_overlay.ka0c08_tlep$l_tlcon00T#define ka0c08_tlep$l_tlcon00a ka0c08_tlep$r_tlcon00a_overlay.ka0c08_tlep$l_tlcon00aT#define ka0c08_tlep$l_tlcon00b ka0c08_tlep$r_tlcon00b_overlay.ka0c08_tlep$l_tlcon00bT#define ka0c08_tlep$l_tlcon00c ka0c08_tlep$r_tlcon00c_overlay.ka0c08_tlep$l_tlcon00cQ#define ka0c08_tlep$l_tlcon10 ka0c08_tlep$r_tlcon10_overlay.ka0c08_tlep$l_tlcon10T#define ka0c08_tlep$l_tlcon10a ka0c08_tlep$r_tlcon10a_overlay.ka0c08_tlep$l_tlcon10aT#define ka0c08_tlep$i2l_tlcon10b ka0c08_tlep$r_tlcon10b_overlay.ka0c08_tlep$l_tlcon10bT#define ka0c08_tlep$l_tlcon10c ka0c08_tlep$r_tlcon10c_overlay.ka0c08_tlep$l_tlcon10cQ#define ka0c08_tlep$l_tlcon01 ka0c08_tlep$r_tlcon01_overlay.ka0c08_tlep$l_tlcon01Q#define ka0c08_tlep$l_tlcon11 ka0c08_tlep$r_tlcon11_overlay.ka0c08_tlep$l_tlcon11N#define ka0c08_tlep$l_tccerr ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$l_tccerr~#define ka0c08_tlep$v_tccerr_p0_mbpr_to ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlepj2$v_tccerr_p0_mbpr_to~#define ka0c08_tlep$v_tccerr_p1_mbpr_to ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p1_mbpr_tot#define ka0c08_tlep$v_tccerr_dtpe0 ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_dtpe0t#define ka0c08_tlep$v_tccerr_dtpe1 ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_dtpe1x#define ka0c08_tlep$v_tccerr_sysderr ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_sysderrk2~#define ka0c08_tlep$v_tccerr_wspc_rd_er ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_wspc_rd_erz#define ka0c08_tlep$v_tccerr_sysfault ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_sysfault~#define ka0c08_tlep$v_tccerr_fault_asrt ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_fault_asrt~#define ka0c08_tlep$v_tccerr_p0_ftlmmre ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p0_ftlmml2re~#define ka0c08_tlep$v_tccerr_p1_ftlmmre ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p1_ftlmmrex#define ka0c08_tlep$v_tccerr_p0_mmre ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p0_mmrex#define ka0c08_tlep$v_tccerr_p1_mmre ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p1_mmre~#define ka0c08_tlep$v_tccerr_csr_wr_nxm ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_csr_wr_nxm|#dm2efine ka0c08_tlep$v_tccerr_csr_xactn ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_csr_xactnx#define ka0c08_tlep$v_tccerr_tcc_rev ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_tcc_rev~#define ka0c08_tlep$v_tccerr_p0_ilglcsr ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p0_ilglcsr~#define ka0c08_tlep$v_tccerr_p1_ilglcsr ka0c08_tlep$r_tccerr_overlay.ka0c08_tlep$r_tccerr_bits.ka0c08_tlep$v_tccerr_p1_ilglcsrN#defn2ine ka0c08_tlep$l_tdierr ka0c08_tlep$r_tdierr_overlay.ka0c08_tlep$l_tdierrr#define ka0c08_tlep$v_tdierr_gbto ka0c08_tlep$r_tdierr_overlay.ka0c08_tlep$r_tdierr_bits.ka0c08_tlep$v_tdierr_gbtoQ#define ka0c08_tlep$l_tl6_vmg ka0c08_tlep$r_tl6_vmg_overlay.ka0c08_tlep$l_tl6_vmgr#define ka0c08_tlep$v_tl6_vmg_5p ka0c08_tlep$r_tl6_vmg_overlay.ka0c08_tlep$r_tl6_vmg_bits.ka0c08_tlep$v_tl6_vmg_5pr#define ka0c08_tlep$v_tl6_vmg_5m ka0c08_tlep$r_tl6_vmg_overlay.ka0c08_tlep$r_tl6_vmg_bits.ka0c08_tlep$v_tl6_vmg_5mo2r#define ka0c08_tlep$v_tl6_vmg_3p ka0c08_tlep$r_tl6_vmg_overlay.ka0c08_tlep$r_tl6_vmg_bits.ka0c08_tlep$v_tl6_vmg_3pr#define ka0c08_tlep$v_tl6_vmg_3m ka0c08_tlep$r_tl6_vmg_overlay.ka0c08_tlep$r_tl6_vmg_bits.ka0c08_tlep$v_tl6_vmg_3mQ#define ka0c08_tlep$l_tl6werr ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$l_tl6werr#define ka0c08_tlep$v_tl6werr_select ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_select_bits.ka0c08_tlep$v_tl6werr_select#define ka0c08_tlep$v_tl6werr_r0_rd_pnd ka0c08_tlep$r_tlp26werr_overlay.ka0c08_tlep$r_tl6werr_register0_bi.ka0c08_tlep$v_tl6werr_r0_r\d_pnd#define ka0c08_tlep$v_tl6werr_r0_addr ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_register0_bi.ka0c08_tlep$v_tl6werr_r0_addr#define ka0c08_tlep$v_tl6werr_r1_addr ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_register1_bi.ka0c08_tlep$v_tl6werr_r1_addr#define ka0c08_tlep$v_tl6werr_r2_rd_pnd ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_register2_bi.ka0c08_tlep$v_tl6werr_r2_r\d_pnd#define kaq20c08_tlep$v_tl6werr_r2_addr ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_register2_bi.ka0c08_tlep$v_tl6werr_r2_addr#define ka0c08_tlep$v_tl6werr_r3_addr ka0c08_tlep$r_tl6werr_overlay.ka0c08_tlep$r_tl6werr_register3_bi.ka0c08_tlep$v_tl6werr_r3_addrT#define ka0c08_tlep$l_tldtagex ka0c08_tlep$r_tldtagex_overlay.ka0c08_tlep$l_tldtagexv#define ka0c08_tlep$v_tldtagex_f1 ka0c08_tlep$r_tldtagex_overlay.ka0c08_tlep$r_tldtagex_bits.ka0c08_tlep$v_tldtagex_f1W#define ka0c08_tlep$l_tlloopbck ka0c08_tler2p$r_tlloopbck_overlay.ka0c08_tlep$l_tlloopbck"#endif /* #if !defined(__VAXC) */ )#define KA0C05_TLMEM$M_TLDEV_DTYPE 0xFFFF+#define KA0C05_TLMEM$M_TLDEV_SWREV 0xFF0000-#define KA0C05_TLMEM$M_TLDEV_HWREV 0xFF000000%#define KA0C05_TLMEM$M_TLBER_ATCE 0x1$#define KA0C05_TLMEM$M_TLBER_APE 0x2$#define KA0C05_TLMEM$M_TLBER_BBE 0x4%#define KA0C05_TLMEM$M_TLBER_LKTO 0x8%#define KA0C05_TLMEM$M_TLBER_NAE 0x10&#define KA0C05_TLMEM$M_TLBER_RTCE 0x20(#define KA0C05_TLMEM$M_TLBER_ACKTCE 0x40&#d s2efine KA0C05_TLMEM$M_TLBER_MMRE 0x80'#define KA0C05_TLMEM$M_TLBER_FNAE 0x100(#define KA0C05_TLMEM$M_TLBER_REQDE 0x200'#define KA0C05_TLMEM$M_TLBER_ATDE 0x400(#define KA0C05_TLMEM$M_TLBER_UDE 0x10000)#define KA0C05_TLMEM$M_TLBER_CWDE 0x20000)#define KA0C05_TLMEM$M_TLBER_CRDE 0x40000)#define KA0C05_TLMEM$M_TLBER_DS0 0x100000)#define KA0C05_TLMEM$M_TLBER_DS1 0x200000)#define KA0C05_TLMEM$M_TLBER_DS2 0x400000)#define KA0C05_TLMEM$M_TLBER_DS3 0x800000+#define KA0C05_TLMEM$M_TLBER_DTDE 0x t21000000,#define KA0C05_TLMEM$M_TLBER_FDTCE 0x2000000,#define KA0C05_TLMEM$M_TLBER_UACKE 0x4000000,#define KA0C05_TLMEM$M_TLBER_ABTCE 0x8000000-#define KA0C05_TLMEM$M_TLBER_DCTCE 0x10000000,#define KA0C05_TLMEM$M_TLBER_SEQE 0x20000000+#define KA0C05_TLMEM$M_TLBER_DSE 0x40000000+#define KA0C05_TLMEM$M_TLBER_DTO 0x80000000%#define KA0C05_TLMEM$M_TLCNR_CWDD 0x1%#define KA0C05_TLMEM$M_TLCNR_CRDD 0x2&#define KA0C05_TLMEM$M_TLCNR_LKTOD 0x4%#define KA0C05_TLMEM$M_TLCNR_DTOD 0x8)#define KA0C u205_TLMEM$M_TLCNR_NODE_ID 0xF0'#define KA0C05_TLMEM$M_TLCNR_VCNT 0xF00)#define KA0C05_TLMEM$M_TLCNR_STF_A 0x1000)#define KA0C05_TLMEM$M_TLCNR_STF_B 0x2000)#define KA0C05_TLMEM$M_TLCNR_STF_C 0x4000)#define KA0C05_TLMEM$M_TLCNR_STF_D 0x8000*#define KA0C05_TLMEM$M_TLCNR_STF_E 0x10000*#define KA0C05_TLMEM$M_TLCNR_STF_F 0x20000*#define KA0C05_TLMEM$M_TLCNR_STF_G 0x40000*#define KA0C05_TLMEM$M_TLCNR_STF_H 0x80000,#define KA0C05_TLMEM$M_TLCNR_HALT_A 0x100000,#define KA0C05_TLMEM$M_TLCNR_HALT_ v2B 0x200000,#define KA0C05_TLMEM$M_TLCNR_HALT_C 0x400000,#define KA0C05_TLMEM$M_TLCNR_HALT_D 0x800000-#define KA0C05_TLMEM$M_TLCNR_HALT_E 0x1000000-#define KA0C05_TLMEM$M_TLCNR_HALT_F 0x2000000-#define KA0C05_TLMEM$M_TLCNR_HALT_G 0x4000000-#define KA0C05_TLMEM$M_TLCNR_HALT_H 0x8000000/#define KA0C05_TLMEM$M_TLCNR_RSTSTAT 0x10000000,#define KA0C05_TLMEM$M_TLCNR_NRST 0x40000000,#define KA0C05_TLMEM$M_TLCNR_LOFE 0x80000000 #define KA0C05_TLMEM$M_VID_A 0xF!#define KA0C05_TLMEM$M_VID_B 0xF0 w2"#define KA0C05_TLMEM$M_VID_C 0xF00##define KA0C05_TLMEM$M_VID_D 0xF000$#define KA0C05_TLMEM$M_VID_E 0xF0000%#define KA0C05_TLMEM$M_VID_F 0xF00000&#define KA0C05_TLMEM$M_VID_G 0xF000000'#define KA0C05_TLMEM$M_VID_H 0xF0000000.#define KA0C05_TLMEM$M_TLFADR0_FADR 0xFFFFFFF8(#define KA0C05_TLMEM$M_TLFADR1_FADR 0xFF+#define KA0C05_TLMEM$M_TLFADR1_FCMD 0x70000-#define KA0C05_TLMEM$M_TLFADR1_FBANK 0xF00000-#define KA0C05_TLMEM$M_TLFADR1_ADRV 0x1000000-#define KA0C05_TLMEM$M_TLFADR1_CMDV 0x x22000000.#define KA0C05_TLMEM$M_TLFADR1_BANKV 0x4000000##define KA0C05_TLMEM$K_VICTIM 65536&#define KA0C05_TLMEM$K_BUS_READ 131072'#define KA0C05_TLMEM$K_BUS_WRITE 196608,#define KA0C05_TLMEM$K_READ_BANK_LOCK 262144.#define KA0C05_TLMEM$K_WRITE_BANK_UNLCK 327680&#define KA0C05_TLMEM$K_CSR_READ 393216'#define KA0C05_TLMEM$K_CSR_WRITE 458752(#define KA0C05_TLMEM$M_TLESR0_SYND0 0xFF*#define KA0C05_TLMEM$M_TLESR0_SYND1 0xFF00)#define KA0C05_TLMEM$M_TLESR0_TDE 0x10000)#define KA0C05_TLMEM$M y2_TLESR0_TCE 0x20000+#define KA0C05_TLMEM$M_TLESR0_DVTCE 0x40000*#define KA0C05_TLMEM$M_TLESR0_UECC 0x80000,#define KA0C05_TLMEM$M_TLESR0_CWECC 0x100000,#define KA0C05_TLMEM$M_TLESR0_CRECC 0x200000/#define KA0C05_TLMEM$M_TLESR0_LOFSYN 0x80000000(#define KA0C05_TLMEM$M_TLESR1_SYND0 0xFF*#define KA0C05_TLMEM$M_TLESR1_SYND1 0xFF00)#define KA0C05_TLMEM$M_TLESR1_TDE 0x10000)#define KA0C05_TLMEM$M_TLESR1_TCE 0x20000+#define KA0C05_TLMEM$M_TLESR1_DVTCE 0x40000*#define KA0C05_TLMEM$M_TLESR1_UE z2CC 0x80000,#define KA0C05_TLMEM$M_TLESR1_CWECC 0x100000,#define KA0C05_TLMEM$M_TLESR1_CRECC 0x200000/#define KA0C05_TLMEM$M_TLESR1_LOFSYN 0x80000000(#define KA0C05_TLMEM$M_TLESR2_SYND0 0xFF*#define KA0C05_TLMEM$M_TLESR2_SYND1 0xFF00)#define KA0C05_TLMEM$M_TLESR2_TDE 0x10000)#define KA0C05_TLMEM$M_TLESR2_TCE 0x20000+#define KA0C05_TLMEM$M_TLESR2_DVTCE 0x40000*#define KA0C05_TLMEM$M_TLESR2_UECC 0x80000,#define KA0C05_TLMEM$M_TLESR2_CWECC 0x100000,#define KA0C05_TLMEM$M_TLESR2_CRECC 0x2000 {200/#define KA0C05_TLMEM$M_TLESR2_LOFSYN 0x80000000(#define KA0C05_TLMEM$M_TLESR3_SYND0 0xFF*#define KA0C05_TLMEM$M_TLESR3_SYND1 0xFF00)#define KA0C05_TLMEM$M_TLESR3_TDE 0x10000)#define KA0C05_TLMEM$M_TLESR3_TCE 0x20000+#define KA0C05_TLMEM$M_TLESR3_DVTCE 0x40000*#define KA0C05_TLMEM$M_TLESR3_UECC 0x80000,#define KA0C05_TLMEM$M_TLESR3_CWECC 0x100000,#define KA0C05_TLMEM$M_TLESR3_CRECC 0x200000/#define KA0C05_TLMEM$M_TLESR3_LOFSYN 0x80000000*#define KA0C05_TLMEM$M_TLSECR_RCV_SDAT 0x1*#d |2efine KA0C05_TLMEM$M_TLSECR_XMT_SDAT 0x2&#define KA0C05_TLMEM$M_TLSECR_SCLK 0x4$#define KA0C05_TLMEM$M_TLMIR_INT 0x7)#define KA0C05_TLMEM$M_TLMIR_V 0x80000000%#define KA0C05_TLMEM$M_TLMCR_DTYP 0x1%#define KA0C05_TLMEM$M_TLMCR_STRN 0xC%#define KA0C05_TLMEM$M_TLMCR_DTR 0x30'#define KA0C05_TLMEM$M_TLMCR_DEFLT 0x40'#define KA0C05_TLMEM$M_TLMCR_SHRD 0x100)#define KA0C05_TLMEM$M_TLMCR_OPTION 0x200+#define KA0C05_TLMEM$M_TLMCR_BDC 0x10000000,#define KA0C05_TLMEM$M_TLMCR_BREN 0x20000000,#d }2efine KA0C05_TLMEM$M_TLMCR_BDIS 0x40000000+#define KA0C05_TLMEM$M_TLMCR_BAT 0x80000000&#define KA0C05_TLMEM$M_TLSTER_FSTR 0x7'#define KA0C05_TLMEM$M_TLSTER_STE0 0x10'#define KA0C05_TLMEM$M_TLSTER_STE1 0x20'#define KA0C05_TLMEM$M_TLSTER_STE2 0x40'#define KA0C05_TLMEM$M_TLSTER_STE3 0x80%#define KA0C05_TLMEM$M_TLMER_FSTR 0x7&#define KA0C05_TLMEM$M_TLMDRA_AMEN 0x1'#define KA0C05_TLMEM$M_TLMDRA_FRAPE 0x2'#define KA0C05_TLMEM$M_TLMDRA_FCAPE 0x4&#define KA0C05_TLMEM$M_TLMDRA_MMPS 0x8'#def ~2ine KA0C05_TLMEM$M_TLMDRA_EXST 0x10'#define KA0C05_TLMEM$M_TLMDRA_FRUN 0x20'#define KA0C05_TLMEM$M_TLMDRA_POEM 0x40(#define KA0C05_TLMEM$M_TLMDRA_POEMC 0x80(#define KA0C05_TLMEM$M_TLMDRA_DEDA 0x100,#define KA0C05_TLMEM$M_TLMDRA_RFR 0x30000000.#define KA0C05_TLMEM$M_TLMDRA_BRFSH 0x40000000.#define KA0C05_TLMEM$M_TLMDRA_DRFSH 0x80000000-#define KA0C05_TLMEM$M_TLMDRB_MADR 0xFFFFFFFF,#define KA0C05_TLMEM$M_TLSTDERE_0_STE 0xFFFF-#define KA0C05_TLMEM$M_TLSTDERE_0_VRC 0x70000%#define KA0C05_T 2LMEM$M_TLDDR0_LOE 0x1&#define KA0C05_TLMEM$M_TLDDR0_CDER 0x2&#define KA0C05_TLMEM$M_TLDDR0_ICFR 0x4%#define KA0C05_TLMEM$M_TLDDR0_PAT 0x8'#define KA0C05_TLMEM$M_TLDDR0_CFLP 0x70)#define KA0C05_TLMEM$M_TLDDR0_DFLP 0x3F00*#define KA0C05_TLMEM$M_TLDDR0_EFLPC 0x4000*#define KA0C05_TLMEM$M_TLDDR0_EFLPD 0x8000-#define KA0C05_TLMEM$M_TLDDR0_MARG 0x80000000,#define KA0C05_TLMEM$M_TLSTDERE_1_STE 0xFFFF-#define KA0C05_TLMEM$M_TLSTDERE_1_VRC 0x70000%#define KA0C05_TLMEM$M_TLDDR1_LOE 0x1&#defin 2e KA0C05_TLMEM$M_TLDDR1_CDER 0x2&#define KA0C05_TLMEM$M_TLDDR1_ICFR 0x4%#define KA0C05_TLMEM$M_TLDDR1_PAT 0x8'#define KA0C05_TLMEM$M_TLDDR1_CFLP 0x70)#define KA0C05_TLMEM$M_TLDDR1_DFLP 0x3F00*#define KA0C05_TLMEM$M_TLDDR1_EFLPC 0x4000*#define KA0C05_TLMEM$M_TLDDR1_EFLPD 0x8000-#define KA0C05_TLMEM$M_TLDDR1_MARG 0x80000000,#define KA0C05_TLMEM$M_TLSTDERE_2_STE 0xFFFF-#define KA0C05_TLMEM$M_TLSTDERE_2_VRC 0x70000%#define KA0C05_TLMEM$M_TLDDR2_LOE 0x1&#define KA0C05_TLMEM$M_TLDDR2_CDER 0 2x2&#define KA0C05_TLMEM$M_TLDDR2_ICFR 0x4%#define KA0C05_TLMEM$M_TLDDR2_PAT 0x8'#define KA0C05_TLMEM$M_TLDDR2_CFLP 0x70)#define KA0C05_TLMEM$M_TLDDR2_DFLP 0x3F00*#define KA0C05_TLMEM$M_TLDDR2_EFLPC 0x4000*#define KA0C05_TLMEM$M_TLDDR2_EFLPD 0x8000-#define KA0C05_TLMEM$M_TLDDR2_MARG 0x80000000,#define KA0C05_TLMEM$M_TLSTDERE_3_STE 0xFFFF-#define KA0C05_TLMEM$M_TLSTDERE_3_VRC 0x70000%#define KA0C05_TLMEM$M_TLDDR3_LOE 0x1&#define KA0C05_TLMEM$M_TLDDR3_CDER 0x2&#define KA0C05_TLMEM$M_TLD2DR3_ICFR 0x4%#define KA0C05_TLMEM$M_TLDDR3_PAT 0x8'#define KA0C05_TLMEM$M_TLDDR3_CFLP 0x70)#define KA0C05_TLMEM$M_TLDDR3_DFLP 0x3F00*#define KA0C05_TLMEM$M_TLDDR3_EFLPC 0x4000*#define KA0C05_TLMEM$M_TLDDR3_EFLPD 0x8000-#define KA0C05_TLMEM$M_TLDDR3_MARG 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0c05_tlmem {#pra2gma __nomember_alignment __union {* unsigned int ka0c05_tlmem$l_tldev; __struct {5 unsigned ka0c05_tlmem$v_tldev_dtype : 16;4 unsigned ka0c05_tlmem$v_tldev_swrev : 8;4 unsigned ka0c05_tlmem$v_tldev_hwrev : 8;( } ka0c05_tlmem$r_tldev_bits;' } ka0c05_tlmem$r_tldev_overlay;. unsigned char ka0c05_tlmem$b_fill900 [60]; __union {* unsigned int ka0c05_tlmem$l_tlber; __struct {3 unsigned 2 ka0c05_tlmem$v_tlber_atce : 1;2 unsigned ka0c05_tlmem$v_tlber_ape : 1;2 unsigned ka0c05_tlmem$v_tlber_bbe : 1;3 unsigned ka0c05_tlmem$v_tlber_lkto : 1;2 unsigned ka0c05_tlmem$v_tlber_nae : 1;3 unsigned ka0c05_tlmem$v_tlber_rtce : 1;5 unsigned ka0c05_tlmem$v_tlber_acktce : 1;3 unsigned ka0c05_tlmem$v_tlber_mmre : 1;3 unsigned ka0c05_tlmem$v_tlber_fnae : 1;4 unsigned ka0c05_tlmem$v_tlber_re 2qde : 1;3 unsigned ka0c05_tlmem$v_tlber_atde : 1;1 unsigned ka0c05_tlmem$v_tlber_f1 : 5;2 unsigned ka0c05_tlmem$v_tlber_ude : 1;3 unsigned ka0c05_tlmem$v_tlber_cwde : 1;3 unsigned ka0c05_tlmem$v_tlber_crde : 1;4 unsigned ka0c05_tlmem$v_tlber_cwde2 : 1;2 unsigned ka0c05_tlmem$v_tlber_ds0 : 1;2 unsigned ka0c05_tlmem$v_tlber_ds1 : 1;2 unsigned ka0c05_tlmem$v_tlber_ds2 : 1;2 unsigned 2 ka0c05_tlmem$v_tlber_ds3 : 1;3 unsigned ka0c05_tlmem$v_tlber_dtde : 1;4 unsigned ka0c05_tlmem$v_tlber_fdtce : 1;4 unsigned ka0c05_tlmem$v_tlber_uacke : 1;4 unsigned ka0c05_tlmem$v_tlber_abtce : 1;4 unsigned ka0c05_tlmem$v_tlber_dctce : 1;3 unsigned ka0c05_tlmem$v_tlber_seqe : 1;2 unsigned ka0c05_tlmem$v_tlber_dse : 1;2 unsigned ka0c05_tlmem$v_tlber_dto : 1;( } ka0c05_tlmem$r_tlber_bits;' 2 } ka0c05_tlmem$r_tlber_overlay;. unsigned char ka0c05_tlmem$b_fill910 [60]; __union {* unsigned int ka0c05_tlmem$l_tlcnr; __struct {3 unsigned ka0c05_tlmem$v_tlcnr_cwdd : 1;3 unsigned ka0c05_tlmem$v_tlcnr_crdd : 1;4 unsigned ka0c05_tlmem$v_tlcnr_lktod : 1;3 unsigned ka0c05_tlmem$v_tlcnr_dtod : 1;6 unsigned ka0c05_tlmem$v_tlcnr_node_id : 4;3 unsigned ka0c05_tlmem$v_tlcnr_vcnt : 4;4 2unsigned ka0c05_tlmem$v_tlcnr_stf_a : 1;4 unsigned ka0c05_tlmem$v_tlcnr_stf_b : 1;4 unsigned ka0c05_tlmem$v_tlcnr_stf_c : 1;4 unsigned ka0c05_tlmem$v_tlcnr_stf_d : 1;4 unsigned ka0c05_tlmem$v_tlcnr_stf_e : 1;4 unsigned ka0c05_tlmem$v_tlcnr_stf_f : 1;4 unsigned ka0c05_tlmem$v_tlcnr_stf_g : 1;4 unsigned ka0c05_tlmem$v_tlcnr_stf_h : 1;5 unsigned ka0c05_tlmem$v_tlcnr_halt_a : 1;5 unsigned ka0c05_tl 2mem$v_tlcnr_halt_b : 1;5 unsigned ka0c05_tlmem$v_tlcnr_halt_c : 1;5 unsigned ka0c05_tlmem$v_tlcnr_halt_d : 1;5 unsigned ka0c05_tlmem$v_tlcnr_halt_e : 1;5 unsigned ka0c05_tlmem$v_tlcnr_halt_f : 1;5 unsigned ka0c05_tlmem$v_tlcnr_halt_g : 1;5 unsigned ka0c05_tlmem$v_tlcnr_halt_h : 1;6 unsigned ka0c05_tlmem$v_tlcnr_rststat : 1;1 unsigned ka0c05_tlmem$v_tlcnr_f1 : 1;3 unsigned ka0c05_tlmem$v_ 2tlcnr_nrst : 1;3 unsigned ka0c05_tlmem$v_tlcnr_lofe : 1;( } ka0c05_tlmem$r_tlcnr_bits;' } ka0c05_tlmem$r_tlcnr_overlay;. unsigned char ka0c05_tlmem$b_fill920 [60]; __union {* unsigned int ka0c05_tlmem$l_tlvid; __struct {. unsigned ka0c05_tlmem$v_vid_a : 4;. unsigned ka0c05_tlmem$v_vid_b : 4;. unsigned ka0c05_tlmem$v_vid_c : 4;. unsigned ka0c05_tlmem$v_vid_d : 4;. unsigned ka0c05_ 2tlmem$v_vid_e : 4;. unsigned ka0c05_tlmem$v_vid_f : 4;. unsigned ka0c05_tlmem$v_vid_g : 4;. unsigned ka0c05_tlmem$v_vid_h : 4;( } ka0c05_tlmem$r_tlvid_bits;' } ka0c05_tlmem$r_tlvid_overlay;0 unsigned char ka0c05_tlmem$b_fill930 [1340]; __union {, unsigned int ka0c05_tlmem$l_tlfadr0; __struct {3 unsigned ka0c05_tlmem$v_tlfadr0_f1 : 3;6 unsigned ka0c05_tlmem$v_tlfadr0_fadr : 29;* } 2ka0c05_tlmem$r_tlfadr0_bits;) } ka0c05_tlmem$r_tlfadr0_overlay;. unsigned char ka0c05_tlmem$b_fill940 [60]; __union {, unsigned int ka0c05_tlmem$l_tlfadr1; __struct {5 unsigned ka0c05_tlmem$v_tlfadr1_fadr : 8;3 unsigned ka0c05_tlmem$v_tlfadr1_f1 : 8;5 unsigned ka0c05_tlmem$v_tlfadr1_fcmd : 3;3 unsigned ka0c05_tlmem$v_tlfadr1_f2 : 1;6 unsigned ka0c05_tlmem$v_tlfadr1_fbank : 4;5 unsigned ka0 2c05_tlmem$v_tlfadr1_adrv : 1;5 unsigned ka0c05_tlmem$v_tlfadr1_cmdv : 1;6 unsigned ka0c05_tlmem$v_tlfadr1_bankv : 1;6 unsigned ka0c05_tlmem$v_tlfadr1_fill3 : 5;* } ka0c05_tlmem$r_tlfadr1_bits;) } ka0c05_tlmem$r_tlfadr1_overlay;. unsigned char ka0c05_tlmem$b_fill950 [60]; __union {+ unsigned int ka0c05_tlmem$l_tlesr0; __struct {5 unsigned ka0c05_tlmem$v_tlesr0_synd0 : 8;5 unsigned ka0c05_tl 2mem$v_tlesr0_synd1 : 8;3 unsigned ka0c05_tlmem$v_tlesr0_tde : 1;3 unsigned ka0c05_tlmem$v_tlesr0_tce : 1;5 unsigned ka0c05_tlmem$v_tlesr0_dvtce : 1;4 unsigned ka0c05_tlmem$v_tlesr0_uecc : 1;5 unsigned ka0c05_tlmem$v_tlesr0_cwecc : 1;5 unsigned ka0c05_tlmem$v_tlesr0_crecc : 1;2 unsigned ka0c05_tlmem$v_tlesr0_f1 : 9;6 unsigned ka0c05_tlmem$v_tlesr0_lofsyn : 1;) } ka0c05_tlmem$r_tlesr0_bits; 2( } ka0c05_tlmem$r_tlesr0_overlay;. unsigned char ka0c05_tlmem$b_fill960 [60]; __union {+ unsigned int ka0c05_tlmem$l_tlesr1; __struct {5 unsigned ka0c05_tlmem$v_tlesr1_synd0 : 8;5 unsigned ka0c05_tlmem$v_tlesr1_synd1 : 8;3 unsigned ka0c05_tlmem$v_tlesr1_tde : 1;3 unsigned ka0c05_tlmem$v_tlesr1_tce : 1;5 unsigned ka0c05_tlmem$v_tlesr1_dvtce : 1;4 unsigned ka0c05_tlmem$v_tlesr1_uecc : 1;5 2 unsigned ka0c05_tlmem$v_tlesr1_cwecc : 1;5 unsigned ka0c05_tlmem$v_tlesr1_crecc : 1;2 unsigned ka0c05_tlmem$v_tlesr1_f1 : 9;6 unsigned ka0c05_tlmem$v_tlesr1_lofsyn : 1;) } ka0c05_tlmem$r_tlesr1_bits;( } ka0c05_tlmem$r_tlesr1_overlay;. unsigned char ka0c05_tlmem$b_fill970 [60]; __union {+ unsigned int ka0c05_tlmem$l_tlesr2; __struct {5 unsigned ka0c05_tlmem$v_tlesr2_synd0 : 8;5 2unsigned ka0c05_tlmem$v_tlesr2_synd1 : 8;3 unsigned ka0c05_tlmem$v_tlesr2_tde : 1;3 unsigned ka0c05_tlmem$v_tlesr2_tce : 1;5 unsigned ka0c05_tlmem$v_tlesr2_dvtce : 1;4 unsigned ka0c05_tlmem$v_tlesr2_uecc : 1;5 unsigned ka0c05_tlmem$v_tlesr2_cwecc : 1;5 unsigned ka0c05_tlmem$v_tlesr2_crecc : 1;2 unsigned ka0c05_tlmem$v_tlesr2_f1 : 9;6 unsigned ka0c05_tlmem$v_tlesr2_lofsyn : 1;) } ka0c05_tlm 2em$r_tlesr2_bits;( } ka0c05_tlmem$r_tlesr2_overlay;. unsigned char ka0c05_tlmem$b_fill980 [60]; __union {+ unsigned int ka0c05_tlmem$l_tlesr3; __struct {5 unsigned ka0c05_tlmem$v_tlesr3_synd0 : 8;5 unsigned ka0c05_tlmem$v_tlesr3_synd1 : 8;3 unsigned ka0c05_tlmem$v_tlesr3_tde : 1;3 unsigned ka0c05_tlmem$v_tlesr3_tce : 1;5 unsigned ka0c05_tlmem$v_tlesr3_dvtce : 1;4 unsigned ka0c05_tlmem$v_ 2tlesr3_uecc : 1;5 unsigned ka0c05_tlmem$v_tlesr3_cwecc : 1;5 unsigned ka0c05_tlmem$v_tlesr3_crecc : 1;2 unsigned ka0c05_tlmem$v_tlesr3_f1 : 9;6 unsigned ka0c05_tlmem$v_tlesr3_lofsyn : 1;) } ka0c05_tlmem$r_tlesr3_bits;( } ka0c05_tlmem$r_tlesr3_overlay;0 unsigned char ka0c05_tlmem$b_fill990 [4284]; __union {+ unsigned int ka0c05_tlmem$l_tlsecr; __struct {8 unsigned ka0c05_tlmem$v_tlsecr_rcv_s 2dat : 1;8 unsigned ka0c05_tlmem$v_tlsecr_xmt_sdat : 1;4 unsigned ka0c05_tlmem$v_tlsecr_sclk : 1;3 unsigned ka0c05_tlmem$v_tlsecr_f1 : 29;) } ka0c05_tlmem$r_tlsecr_bits;( } ka0c05_tlmem$r_tlsecr_overlay;, unsigned char ka0c05_tlmem$b_f1000 [60]; __union {* unsigned int ka0c05_tlmem$l_tlmir; __struct {2 unsigned ka0c05_tlmem$v_tlmir_int : 3;2 unsigned ka0c05_tlmem$v_tlmir_f1 : 28;0 2unsigned ka0c05_tlmem$v_tlmir_v : 1;( } ka0c05_tlmem$r_tlmir_bits;' } ka0c05_tlmem$r_tlmir_overlay;, unsigned char ka0c05_tlmem$b_f1010 [60]; __union {* unsigned int ka0c05_tlmem$l_tlmcr; __struct {3 unsigned ka0c05_tlmem$v_tlmcr_dtyp : 1;1 unsigned ka0c05_tlmem$v_tlmcr_f1 : 1;3 unsigned ka0c05_tlmem$v_tlmcr_strn : 2;2 unsigned ka0c05_tlmem$v_tlmcr_dtr : 2;4 unsigned ka0c05_tlmem$v_tlmcr_de 2flt : 1;1 unsigned ka0c05_tlmem$v_tlmcr_f2 : 1;3 unsigned ka0c05_tlmem$v_tlmcr_shrd : 1;5 unsigned ka0c05_tlmem$v_tlmcr_option : 1;5 unsigned ka0c05_tlmem$v_tlmcr_fill3 : 18;2 unsigned ka0c05_tlmem$v_tlmcr_bdc : 1;3 unsigned ka0c05_tlmem$v_tlmcr_bren : 1;3 unsigned ka0c05_tlmem$v_tlmcr_bdis : 1;2 unsigned ka0c05_tlmem$v_tlmcr_bat : 1;( } ka0c05_tlmem$r_tlmcr_bits;' } ka0c05_tlmem$r2_tlmcr_overlay;, unsigned char ka0c05_tlmem$b_f1020 [60]; __union {, unsigned int ka0c05_tlmem$l_tlstair; __struct {4 unsigned ka0c05_tlmem$v_tlstair_f1 : 32;* } ka0c05_tlmem$r_tlstair_bits;) } ka0c05_tlmem$r_tlstair_overlay;, unsigned char ka0c05_tlmem$b_f1030 [60]; __union {+ unsigned int ka0c05_tlmem$l_tlster; __struct {4 unsigned ka0c05_tlmem$v_tlster_fstr : 3;2 unsigned ka0c05_tlme 2m$v_tlster_f1 : 1;4 unsigned ka0c05_tlmem$v_tlster_ste0 : 1;4 unsigned ka0c05_tlmem$v_tlster_ste1 : 1;4 unsigned ka0c05_tlmem$v_tlster_ste2 : 1;4 unsigned ka0c05_tlmem$v_tlster_ste3 : 1;3 unsigned ka0c05_tlmem$v_tlster_f2 : 24;) } ka0c05_tlmem$r_tlster_bits;( } ka0c05_tlmem$r_tlster_overlay;, unsigned char ka0c05_tlmem$b_f1040 [60]; __union {* unsigned int ka0c05_tlmem$l_tlmer; __struct {3 2 unsigned ka0c05_tlmem$v_tlmer_fstr : 3;2 unsigned ka0c05_tlmem$v_tlmer_f1 : 29;( } ka0c05_tlmem$r_tlmer_bits;' } ka0c05_tlmem$r_tlmer_overlay;, unsigned char ka0c05_tlmem$b_f1050 [60]; __union {+ unsigned int ka0c05_tlmem$l_tlmdra; __struct {4 unsigned ka0c05_tlmem$v_tlmdra_amen : 1;5 unsigned ka0c05_tlmem$v_tlmdra_frape : 1;5 unsigned ka0c05_tlmem$v_tlmdra_fcape : 1;4 unsigned k 2a0c05_tlmem$v_tlmdra_mmps : 1;4 unsigned ka0c05_tlmem$v_tlmdra_exst : 1;4 unsigned ka0c05_tlmem$v_tlmdra_frun : 1;4 unsigned ka0c05_tlmem$v_tlmdra_poem : 1;5 unsigned ka0c05_tlmem$v_tlmdra_poemc : 1;4 unsigned ka0c05_tlmem$v_tlmdra_deda : 1;3 unsigned ka0c05_tlmem$v_tlmdra_f1 : 19;3 unsigned ka0c05_tlmem$v_tlmdra_rfr : 2;5 unsigned ka0c05_tlmem$v_tlmdra_brfsh : 1;5 unsigned ka0c05_tlmem$v_tl2mdra_drfsh : 1;) } ka0c05_tlmem$r_tlmdra_bits;( } ka0c05_tlmem$r_tlmdra_overlay;, unsigned char ka0c05_tlmem$b_f1060 [60]; __union {+ unsigned int ka0c05_tlmem$l_tlmdrb; __struct {5 unsigned ka0c05_tlmem$v_tlmdrb_madr : 32;) } ka0c05_tlmem$r_tlmdrb_bits;( } ka0c05_tlmem$r_tlmdrb_overlay;. unsigned char ka0c05_tlmem$b_f1070 [1596]; __union {/ unsigned int ka0c05_tlmem$l_tlstdera_0; __struct2 {7 unsigned ka0c05_tlmem$v_tlstdera_0_f1 : 32;- } ka0c05_tlmem$r_tlstdera_0_bits;, } ka0c05_tlmem$r_tlstdera_0_overlay;, unsigned char ka0c05_tlmem$b_f1080 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstderb_0; __struct {7 unsigned ka0c05_tlmem$v_tlstderb_0_f1 : 32;- } ka0c05_tlmem$r_tlstderb_0_bits;, } ka0c05_tlmem$r_tlstderb_0_overlay;, unsigned char ka0c05_tlmem$b_f1090 [60]; __union {/ 2 unsigned int ka0c05_tlmem$l_tlstderc_0; __struct {7 unsigned ka0c05_tlmem$v_tlstderc_0_f1 : 32;- } ka0c05_tlmem$r_tlstderc_0_bits;, } ka0c05_tlmem$r_tlstderc_0_overlay;, unsigned char ka0c05_tlmem$b_f1100 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstderd_0; __struct {7 unsigned ka0c05_tlmem$v_tlstderd_0_f1 : 32;- } ka0c05_tlmem$r_tlstderd_0_bits;, } ka0c05_tlmem$r_tlstderd_0_overla 2y;, unsigned char ka0c05_tlmem$b_f1110 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstdere_0; __struct {8 unsigned ka0c05_tlmem$v_tlstdere_0_ste : 16;7 unsigned ka0c05_tlmem$v_tlstdere_0_vrc : 3;7 unsigned ka0c05_tlmem$v_tlstdere_0_f1 : 13;- } ka0c05_tlmem$r_tlstdere_0_bits;, } ka0c05_tlmem$r_tlstdere_0_overlay;, unsigned char ka0c05_tlmem$b_f1120 [60]; __union {+ unsigned int ka0c05_tlmem$l_tl 2ddr0; __struct {3 unsigned ka0c05_tlmem$v_tlddr0_loe : 1;4 unsigned ka0c05_tlmem$v_tlddr0_cder : 1;4 unsigned ka0c05_tlmem$v_tlddr0_icfr : 1;3 unsigned ka0c05_tlmem$v_tlddr0_pat : 1;4 unsigned ka0c05_tlmem$v_tlddr0_cflp : 3;2 unsigned ka0c05_tlmem$v_tlddr0_f1 : 1;4 unsigned ka0c05_tlmem$v_tlddr0_dflp : 6;5 unsigned ka0c05_tlmem$v_tlddr0_eflpc : 1;5 unsigned ka0c05_tlmem$v_tlddr0_e 2flpd : 1;3 unsigned ka0c05_tlmem$v_tlddr0_f2 : 15;4 unsigned ka0c05_tlmem$v_tlddr0_marg : 1;) } ka0c05_tlmem$r_tlddr0_bits;( } ka0c05_tlmem$r_tlddr0_overlay;. unsigned char ka0c05_tlmem$b_f1130 [7868]; __union {/ unsigned int ka0c05_tlmem$l_tlstdera_1; __struct {7 unsigned ka0c05_tlmem$v_tlstdera_1_f1 : 32;- } ka0c05_tlmem$r_tlstdera_1_bits;, } ka0c05_tlmem$r_tlstdera_1_overlay;, unsigned 2 char ka0c05_tlmem$b_f1140 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstderb_1; __struct {7 unsigned ka0c05_tlmem$v_tlstderb_1_f1 : 32;- } ka0c05_tlmem$r_tlstderb_1_bits;, } ka0c05_tlmem$r_tlstderb_1_overlay;, unsigned char ka0c05_tlmem$b_f1150 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstderc_1; __struct {7 unsigned ka0c05_tlmem$v_tlstderc_1_f1 : 32;- } ka0c05_tlmem$r_tlstderc_1_2bits;, } ka0c05_tlmem$r_tlstderc_1_overlay;, unsigned char ka0c05_tlmem$b_f1160 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstderd_1; __struct {7 unsigned ka0c05_tlmem$v_tlstderd_1_f1 : 32;- } ka0c05_tlmem$r_tlstderd_1_bits;, } ka0c05_tlmem$r_tlstderd_1_overlay;, unsigned char ka0c05_tlmem$b_f1170 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstdere_1; __struct {8 unsigned ka0c05_tlme 2m$v_tlstdere_1_ste : 16;7 unsigned ka0c05_tlmem$v_tlstdere_1_vrc : 3;7 unsigned ka0c05_tlmem$v_tlstdere_1_f1 : 13;- } ka0c05_tlmem$r_tlstdere_1_bits;, } ka0c05_tlmem$r_tlstdere_1_overlay;, unsigned char ka0c05_tlmem$b_f1180 [60]; __union {+ unsigned int ka0c05_tlmem$l_tlddr1; __struct {3 unsigned ka0c05_tlmem$v_tlddr1_loe : 1;4 unsigned ka0c05_tlmem$v_tlddr1_cder : 1;4 unsigned ka0c05_tlme 2m$v_tlddr1_icfr : 1;3 unsigned ka0c05_tlmem$v_tlddr1_pat : 1;4 unsigned ka0c05_tlmem$v_tlddr1_cflp : 3;2 unsigned ka0c05_tlmem$v_tlddr1_f1 : 1;4 unsigned ka0c05_tlmem$v_tlddr1_dflp : 6;5 unsigned ka0c05_tlmem$v_tlddr1_eflpc : 1;5 unsigned ka0c05_tlmem$v_tlddr1_eflpd : 1;3 unsigned ka0c05_tlmem$v_tlddr1_f2 : 15;4 unsigned ka0c05_tlmem$v_tlddr1_marg : 1;) } ka0c05_tlmem$r_tlddr1_bits;( 2 } ka0c05_tlmem$r_tlddr1_overlay;. unsigned char ka0c05_tlmem$b_f1190 [7868]; __union {/ unsigned int ka0c05_tlmem$l_tlstdera_2; __struct {7 unsigned ka0c05_tlmem$v_tlstdera_2_f1 : 32;- } ka0c05_tlmem$r_tlstdera_2_bits;, } ka0c05_tlmem$r_tlstdera_2_overlay;, unsigned char ka0c05_tlmem$b_f1200 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstderb_2; __struct {7 unsigned ka0c05_tlmem$v_tlstderb_2_f21 : 32;- } ka0c05_tlmem$r_tlstderb_2_bits;, } ka0c05_tlmem$r_tlstderb_2_overlay;, unsigned char ka0c05_tlmem$b_f1210 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstderc_2; __struct {7 unsigned ka0c05_tlmem$v_tlstderc_2_f1 : 32;- } ka0c05_tlmem$r_tlstderc_2_bits;, } ka0c05_tlmem$r_tlstderc_2_overlay;, unsigned char ka0c05_tlmem$b_f1220 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstderd_2; 2 __struct {7 unsigned ka0c05_tlmem$v_tlstderd_2_f1 : 32;- } ka0c05_tlmem$r_tlstderd_2_bits;, } ka0c05_tlmem$r_tlstderd_2_overlay;, unsigned char ka0c05_tlmem$b_f1230 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstdere_2; __struct {8 unsigned ka0c05_tlmem$v_tlstdere_2_ste : 16;7 unsigned ka0c05_tlmem$v_tlstdere_2_vrc : 3;7 unsigned ka0c05_tlmem$v_tlstdere_2_f1 : 13;- } ka0c05_tlmem$r 2_tlstdere_2_bits;, } ka0c05_tlmem$r_tlstdere_2_overlay;, unsigned char ka0c05_tlmem$b_f1240 [60]; __union {+ unsigned int ka0c05_tlmem$l_tlddr2; __struct {3 unsigned ka0c05_tlmem$v_tlddr2_loe : 1;4 unsigned ka0c05_tlmem$v_tlddr2_cder : 1;4 unsigned ka0c05_tlmem$v_tlddr2_icfr : 1;3 unsigned ka0c05_tlmem$v_tlddr2_pat : 1;4 unsigned ka0c05_tlmem$v_tlddr2_cflp : 3;2 unsigned ka0c05_tlmem$v_tldd 2r2_f1 : 1;4 unsigned ka0c05_tlmem$v_tlddr2_dflp : 6;5 unsigned ka0c05_tlmem$v_tlddr2_eflpc : 1;5 unsigned ka0c05_tlmem$v_tlddr2_eflpd : 1;3 unsigned ka0c05_tlmem$v_tlddr2_f2 : 15;4 unsigned ka0c05_tlmem$v_tlddr2_marg : 1;) } ka0c05_tlmem$r_tlddr2_bits;( } ka0c05_tlmem$r_tlddr2_overlay;. unsigned char ka0c05_tlmem$b_f1250 [7868]; __union {/ unsigned int ka0c05_tlmem$l_tlstdera_3; __struct { 27 unsigned ka0c05_tlmem$v_tlstdera_3_f1 : 32;- } ka0c05_tlmem$r_tlstdera_3_bits;, } ka0c05_tlmem$r_tlstdera_3_overlay;, unsigned char ka0c05_tlmem$b_f1260 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstderb_3; __struct {7 unsigned ka0c05_tlmem$v_tlstderb_3_f1 : 32;- } ka0c05_tlmem$r_tlstderb_3_bits;, } ka0c05_tlmem$r_tlstderb_3_overlay;, unsigned char ka0c05_tlmem$b_f1270 [60]; __union {/ 2 unsigned int ka0c05_tlmem$l_tlstderc_3; __struct {7 unsigned ka0c05_tlmem$v_tlstderc_3_f1 : 32;- } ka0c05_tlmem$r_tlstderc_3_bits;, } ka0c05_tlmem$r_tlstderc_3_overlay;, unsigned char ka0c05_tlmem$b_f1280 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstderd_3; __struct {7 unsigned ka0c05_tlmem$v_tlstderd_3_f1 : 32;- } ka0c05_tlmem$r_tlstderd_3_bits;, } ka0c05_tlmem$r_tlstderd_3_overlay;, 2 unsigned char ka0c05_tlmem$b_f1290 [60]; __union {/ unsigned int ka0c05_tlmem$l_tlstdere_3; __struct {8 unsigned ka0c05_tlmem$v_tlstdere_3_ste : 16;7 unsigned ka0c05_tlmem$v_tlstdere_3_vrc : 3;7 unsigned ka0c05_tlmem$v_tlstdere_3_f1 : 13;- } ka0c05_tlmem$r_tlstdere_3_bits;, } ka0c05_tlmem$r_tlstdere_3_overlay;, unsigned char ka0c05_tlmem$b_f1300 [60]; __union {+ unsigned int ka0c05_tlmem$l_tlddr3 2; __struct {3 unsigned ka0c05_tlmem$v_tlddr3_loe : 1;4 unsigned ka0c05_tlmem$v_tlddr3_cder : 1;4 unsigned ka0c05_tlmem$v_tlddr3_icfr : 1;3 unsigned ka0c05_tlmem$v_tlddr3_pat : 1;4 unsigned ka0c05_tlmem$v_tlddr3_cflp : 3;2 unsigned ka0c05_tlmem$v_tlddr3_f1 : 1;4 unsigned ka0c05_tlmem$v_tlddr3_dflp : 6;5 unsigned ka0c05_tlmem$v_tlddr3_eflpc : 1;5 unsigned ka0c05_tlmem$v_tlddr3_eflpd 2 : 1;3 unsigned ka0c05_tlmem$v_tlddr3_f2 : 15;4 unsigned ka0c05_tlmem$v_tlddr3_marg : 1;) } ka0c05_tlmem$r_tlddr3_bits;( } ka0c05_tlmem$r_tlddr3_overlay;. unsigned char ka0c05_tlmem$b_f1310 [7868]; } KA0C05_TLMEM; #if !defined(__VAXC)N#define ka0c05_tlmem$l_tldev ka0c05_tlmem$r_tldev_overlay.ka0c05_tlmem$l_tldevt#define ka0c05_tlmem$v_tldev_dtype ka0c05_tlmem$r_tldev_overlay.ka0c05_tlmem$r_tldev_bits.ka0c05_tlmem$v_tldev_dtypet#define ka20c05_tlmem$v_tldev_swrev ka0c05_tlmem$r_tldev_overlay.ka0c05_tlmem$r_tldev_bits.ka0c05_tlmem$v_tldev_swrevt#define ka0c05_tlmem$v_tldev_hwrev ka0c05_tlmem$r_tldev_overlay.ka0c05_tlmem$r_tldev_bits.ka0c05_tlmem$v_tldev_hwrevN#define ka0c05_tlmem$l_tlber ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$l_tlberr#define ka0c05_tlmem$v_tlber_atce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_atcep#define ka0c05_tlmem$v_tlber_ape ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_b2its.ka0c05_tlmem$v_tlber_apep#define ka0c05_tlmem$v_tlber_bbe ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_bber#define ka0c05_tlmem$v_tlber_lkto ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_lktop#define ka0c05_tlmem$v_tlber_nae ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_naer#define ka0c05_tlmem$v_tlber_rtce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_rtcev#define ka0c05_t2lmem$v_tlber_acktce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_acktcer#define ka0c05_tlmem$v_tlber_mmre ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_mmrer#define ka0c05_tlmem$v_tlber_fnae ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_fnaet#define ka0c05_tlmem$v_tlber_reqde ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_reqder#define ka0c05_tlmem$v_tlber_atde ka0c05_tlmem$r_tlb2er_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_atdep#define ka0c05_tlmem$v_tlber_ude ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_uder#define ka0c05_tlmem$v_tlber_cwde ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_cwder#define ka0c05_tlmem$v_tlber_crde ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_crdep#define ka0c05_tlmem$v_tlber_ds0 ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_t2lmem$v_tlber_ds0p#define ka0c05_tlmem$v_tlber_ds1 ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_ds1p#define ka0c05_tlmem$v_tlber_ds2 ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_ds2p#define ka0c05_tlmem$v_tlber_ds3 ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_ds3r#define ka0c05_tlmem$v_tlber_dtde ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_dtdet#define ka0c05_tlmem$v_tlber_f2dtce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_fdtcet#define ka0c05_tlmem$v_tlber_uacke ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_uacket#define ka0c05_tlmem$v_tlber_abtce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_abtcet#define ka0c05_tlmem$v_tlber_dctce ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_dctcer#define ka0c05_tlmem$v_tlber_seqe ka0c05_tlmem$r_tlber_overlay.k2a0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_seqep#define ka0c05_tlmem$v_tlber_dse ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_dsep#define ka0c05_tlmem$v_tlber_dto ka0c05_tlmem$r_tlber_overlay.ka0c05_tlmem$r_tlber_bits.ka0c05_tlmem$v_tlber_dtoN#define ka0c05_tlmem$l_tlcnr ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$l_tlcnrr#define ka0c05_tlmem$v_tlcnr_cwdd ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_cwddr#define ka0c05_tlmem$v_tlcnr_c2rdd ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_crddt#define ka0c05_tlmem$v_tlcnr_lktod ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_lktodr#define ka0c05_tlmem$v_tlcnr_dtod ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_dtodx#define ka0c05_tlmem$v_tlcnr_node_id ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_node_idr#define ka0c05_tlmem$v_tlcnr_vcnt ka0c05_tlmem$r_tlcnr_overlay.k2a0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_vcntt#define ka0c05_tlmem$v_tlcnr_stf_a ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_at#define ka0c05_tlmem$v_tlcnr_stf_b ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_bt#define ka0c05_tlmem$v_tlcnr_stf_c ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_ct#define ka0c05_tlmem$v_tlcnr_stf_d ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlm2em$v_tlcnr_stf_dt#define ka0c05_tlmem$v_tlcnr_stf_e ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_et#define ka0c05_tlmem$v_tlcnr_stf_f ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_ft#define ka0c05_tlmem$v_tlcnr_stf_g ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_gt#define ka0c05_tlmem$v_tlcnr_stf_h ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_stf_hv#define ka0c05_t2lmem$v_tlcnr_halt_a ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_av#define ka0c05_tlmem$v_tlcnr_halt_b ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_bv#define ka0c05_tlmem$v_tlcnr_halt_c ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_cv#define ka0c05_tlmem$v_tlcnr_halt_d ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_dv#define ka0c05_tlmem$v_tlcnr_halt_e ka0c052_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_ev#define ka0c05_tlmem$v_tlcnr_halt_f ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_fv#define ka0c05_tlmem$v_tlcnr_halt_g ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_gv#define ka0c05_tlmem$v_tlcnr_halt_h ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_halt_hx#define ka0c05_tlmem$v_tlcnr_rststat ka0c05_tlmem$r_tlcnr_overlay.ka20c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_rststatr#define ka0c05_tlmem$v_tlcnr_nrst ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_nrstr#define ka0c05_tlmem$v_tlcnr_lofe ka0c05_tlmem$r_tlcnr_overlay.ka0c05_tlmem$r_tlcnr_bits.ka0c05_tlmem$v_tlcnr_lofeN#define ka0c05_tlmem$l_tlvid ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$l_tlvidh#define ka0c05_tlmem$v_vid_a ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_ah#define ka0c05_tlmem$v_vid_b ka0c025_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_bh#define ka0c05_tlmem$v_vid_c ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_ch#define ka0c05_tlmem$v_vid_d ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_dh#define ka0c05_tlmem$v_vid_e ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_eh#define ka0c05_tlmem$v_vid_f ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_fh#define ka20c05_tlmem$v_vid_g ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_gh#define ka0c05_tlmem$v_vid_h ka0c05_tlmem$r_tlvid_overlay.ka0c05_tlmem$r_tlvid_bits.ka0c05_tlmem$v_vid_hT#define ka0c05_tlmem$l_tlfadr0 ka0c05_tlmem$r_tlfadr0_overlay.ka0c05_tlmem$l_tlfadr0z#define ka0c05_tlmem$v_tlfadr0_fadr ka0c05_tlmem$r_tlfadr0_overlay.ka0c05_tlmem$r_tlfadr0_bits.ka0c05_tlmem$v_tlfadr0_fadrT#define ka0c05_tlmem$l_tlfadr1 ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$l_tlfadr1z#define 2ka0c05_tlmem$v_tlfadr1_fadr ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_fadrz#define ka0c05_tlmem$v_tlfadr1_fcmd ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_fcmd|#define ka0c05_tlmem$v_tlfadr1_fbank ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_fbankz#define ka0c05_tlmem$v_tlfadr1_adrv ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_adrvz#define ka0c05_t2lmem$v_tlfadr1_cmdv ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_cmdv|#define ka0c05_tlmem$v_tlfadr1_bankv ka0c05_tlmem$r_tlfadr1_overlay.ka0c05_tlmem$r_tlfadr1_bits.ka0c05_tlmem$v_tlfadr1_bankvQ#define ka0c05_tlmem$l_tlesr0 ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$l_tlesr0x#define ka0c05_tlmem$v_tlesr0_synd0 ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_synd0x#define ka0c05_tlmem$v_tlesr0_synd1 ka0c05_tlmem$r_tlesr0_overlay.2ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_synd1t#define ka0c05_tlmem$v_tlesr0_tde ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_tdet#define ka0c05_tlmem$v_tlesr0_tce ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_tcex#define ka0c05_tlmem$v_tlesr0_dvtce ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_dvtcev#define ka0c05_tlmem$v_tlesr0_uecc ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.2ka0c05_tlmem$v_tlesr0_ueccx#define ka0c05_tlmem$v_tlesr0_cwecc ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_cweccx#define ka0c05_tlmem$v_tlesr0_crecc ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_creccz#define ka0c05_tlmem$v_tlesr0_lofsyn ka0c05_tlmem$r_tlesr0_overlay.ka0c05_tlmem$r_tlesr0_bits.ka0c05_tlmem$v_tlesr0_lofsynQ#define ka0c05_tlmem$l_tlesr1 ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$l_tlesr1x#define ka0c05_tlmem$v_tle2sr1_synd0 ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_synd0x#define ka0c05_tlmem$v_tlesr1_synd1 ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_synd1t#define ka0c05_tlmem$v_tlesr1_tde ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_tdet#define ka0c05_tlmem$v_tlesr1_tce ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_tcex#define ka0c05_tlmem$v_tlesr1_dvtce ka0c05_tlmem$r_t2lesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_dvtcev#define ka0c05_tlmem$v_tlesr1_uecc ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_ueccx#define ka0c05_tlmem$v_tlesr1_cwecc ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_cweccx#define ka0c05_tlmem$v_tlesr1_crecc ka0c05_tlmem$r_tlesr1_overlay.ka0c05_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_creccz#define ka0c05_tlmem$v_tlesr1_lofsyn ka0c05_tlmem$r_tlesr1_overlay.ka0c025_tlmem$r_tlesr1_bits.ka0c05_tlmem$v_tlesr1_lofsynQ#define ka0c05_tlmem$l_tlesr2 ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$l_tlesr2x#define ka0c05_tlmem$v_tlesr2_synd0 ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_synd0x#define ka0c05_tlmem$v_tlesr2_synd1 ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_synd1t#define ka0c05_tlmem$v_tlesr2_tde ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_tdet#define 2ka0c05_tlmem$v_tlesr2_tce ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_tcex#define ka0c05_tlmem$v_tlesr2_dvtce ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_dvtcev#define ka0c05_tlmem$v_tlesr2_uecc ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_ueccx#define ka0c05_tlmem$v_tlesr2_cwecc ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_cweccx#define ka0c05_tlmem$v_tlesr2_cr2ecc ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_creccz#define ka0c05_tlmem$v_tlesr2_lofsyn ka0c05_tlmem$r_tlesr2_overlay.ka0c05_tlmem$r_tlesr2_bits.ka0c05_tlmem$v_tlesr2_lofsynQ#define ka0c05_tlmem$l_tlesr3 ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$l_tlesr3x#define ka0c05_tlmem$v_tlesr3_synd0 ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_synd0x#define ka0c05_tlmem$v_tlesr3_synd1 ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr23_bits.ka0c05_tlmem$v_tlesr3_synd1t#define ka0c05_tlmem$v_tlesr3_tde ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_tdet#define ka0c05_tlmem$v_tlesr3_tce ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_tcex#define ka0c05_tlmem$v_tlesr3_dvtce ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_dvtcev#define ka0c05_tlmem$v_tlesr3_uecc ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr23_ueccx#define ka0c05_tlmem$v_tlesr3_cwecc ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_cweccx#define ka0c05_tlmem$v_tlesr3_crecc ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_creccz#define ka0c05_tlmem$v_tlesr3_lofsyn ka0c05_tlmem$r_tlesr3_overlay.ka0c05_tlmem$r_tlesr3_bits.ka0c05_tlmem$v_tlesr3_lofsynQ#define ka0c05_tlmem$l_tlsecr ka0c05_tlmem$r_tlsecr_overlay.ka0c05_tlmem$l_tlsecr~#define ka0c05_tlmem$v_tlsecr_rcv_sdat ka0c05_2tlmem$r_tlsecr_overlay.ka0c05_tlmem$r_tlsecr_bits.ka0c05_tlmem$v_tlsecr_rcv_sdat~#define ka0c05_tlmem$v_tlsecr_xmt_sdat ka0c05_tlmem$r_tlsecr_overlay.ka0c05_tlmem$r_tlsecr_bits.ka0c05_tlmem$v_tlsecr_xmt_sdatv#define ka0c05_tlmem$v_tlsecr_sclk ka0c05_tlmem$r_tlsecr_overlay.ka0c05_tlmem$r_tlsecr_bits.ka0c05_tlmem$v_tlsecr_sclkN#define ka0c05_tlmem$l_tlmir ka0c05_tlmem$r_tlmir_overlay.ka0c05_tlmem$l_tlmirp#define ka0c05_tlmem$v_tlmir_int ka0c05_tlmem$r_tlmir_overlay.ka0c05_tlmem$r_tlmir_bits.ka0c05_t2lmem$v_tlmir_intl#define ka0c05_tlmem$v_tlmir_v ka0c05_tlmem$r_tlmir_overlay.ka0c05_tlmem$r_tlmir_bits.ka0c05_tlmem$v_tlmir_vN#define ka0c05_tlmem$l_tlmcr ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$l_tlmcrr#define ka0c05_tlmem$v_tlmcr_dtyp ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_dtypr#define ka0c05_tlmem$v_tlmcr_strn ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_strnp#define ka0c05_tlmem$v_tlmcr_dtr ka0c05_tlmem$r_tlmcr_overlay.ka0c205_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_dtrt#define ka0c05_tlmem$v_tlmcr_deflt ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_defltr#define ka0c05_tlmem$v_tlmcr_shrd ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_shrdv#define ka0c05_tlmem$v_tlmcr_option ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_optionp#define ka0c05_tlmem$v_tlmcr_bdc ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_t2lmcr_bdcr#define ka0c05_tlmem$v_tlmcr_bren ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_brenr#define ka0c05_tlmem$v_tlmcr_bdis ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_bdisp#define ka0c05_tlmem$v_tlmcr_bat ka0c05_tlmem$r_tlmcr_overlay.ka0c05_tlmem$r_tlmcr_bits.ka0c05_tlmem$v_tlmcr_batT#define ka0c05_tlmem$l_tlstair ka0c05_tlmem$r_tlstair_overlay.ka0c05_tlmem$l_tlstairQ#define ka0c05_tlmem$l_tlster ka0c05_tlmem$r_tlster_overlay.ka0c205_tlmem$l_tlsterv#define ka0c05_tlmem$v_tlster_fstr ka0c05_tlmem$r_tlster_overlay.ka0c05_tlmem$r_tlster_bits.ka0c05_tlmem$v_tlster_fstrv#define ka0c05_tlmem$v_tlster_ste0 ka0c05_tlmem$r_tlster_overlay.ka0c05_tlmem$r_tlster_bits.ka0c05_tlmem$v_tlster_ste0v#define ka0c05_tlmem$v_tlster_ste1 ka0c05_tlmem$r_tlster_overlay.ka0c05_tlmem$r_tlster_bits.ka0c05_tlmem$v_tlster_ste1v#define ka0c05_tlmem$v_tlster_ste2 ka0c05_tlmem$r_tlster_overlay.ka0c05_tlmem$r_tlster_bits.ka0c05_tlmem$v_tlster_ste2v#defin2e ka0c05_tlmem$v_tlster_ste3 ka0c05_tlmem$r_tlster_overlay.ka0c05_tlmem$r_tlster_bits.ka0c05_tlmem$v_tlster_ste3N#define ka0c05_tlmem$l_tlmer ka0c05_tlmem$r_tlmer_overlay.ka0c05_tlmem$l_tlmerr#define ka0c05_tlmem$v_tlmer_fstr ka0c05_tlmem$r_tlmer_overlay.ka0c05_tlmem$r_tlmer_bits.ka0c05_tlmem$v_tlmer_fstrQ#define ka0c05_tlmem$l_tlmdra ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$l_tlmdrav#define ka0c05_tlmem$v_tlmdra_amen ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdr2a_amenx#define ka0c05_tlmem$v_tlmdra_frape ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_frapex#define ka0c05_tlmem$v_tlmdra_fcape ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_fcapev#define ka0c05_tlmem$v_tlmdra_mmps ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_mmpsv#define ka0c05_tlmem$v_tlmdra_exst ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_exstv#define ka0c052_tlmem$v_tlmdra_frun ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_frunv#define ka0c05_tlmem$v_tlmdra_poem ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_poemx#define ka0c05_tlmem$v_tlmdra_poemc ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_poemcv#define ka0c05_tlmem$v_tlmdra_deda ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_dedat#define ka0c05_tlmem$v_tlmdra_rfr ka0c205_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_rfrx#define ka0c05_tlmem$v_tlmdra_brfsh ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_brfshx#define ka0c05_tlmem$v_tlmdra_drfsh ka0c05_tlmem$r_tlmdra_overlay.ka0c05_tlmem$r_tlmdra_bits.ka0c05_tlmem$v_tlmdra_drfshQ#define ka0c05_tlmem$l_tlmdrb ka0c05_tlmem$r_tlmdrb_overlay.ka0c05_tlmem$l_tlmdrbv#define ka0c05_tlmem$v_tlmdrb_madr ka0c05_tlmem$r_tlmdrb_overlay.ka0c05_tlmem$r_tlmdrb_bits.ka0c052_tlmem$v_tlmdrb_madr]#define ka0c05_tlmem$l_tlstdera_0 ka0c05_tlmem$r_tlstdera_0_overlay.ka0c05_tlmem$l_tlstdera_0]#define ka0c05_tlmem$l_tlstderb_0 ka0c05_tlmem$r_tlstderb_0_overlay.ka0c05_tlmem$l_tlstderb_0]#define ka0c05_tlmem$l_tlstderc_0 ka0c05_tlmem$r_tlstderc_0_overlay.ka0c05_tlmem$l_tlstderc_0]#define ka0c05_tlmem$l_tlstderd_0 ka0c05_tlmem$r_tlstderd_0_overlay.ka0c05_tlmem$l_tlstderd_0]#define ka0c05_tlmem$l_tlstdere_0 ka0c05_tlmem$r_tlstdere_0_overlay.ka0c05_tlmem$l_tlstdere_0#def2ine ka0c05_tlmem$v_tlstdere_0_ste ka0c05_tlmem$r_tlstdere_0_overlay.ka0c05_tlmem$r_tlstdere_0_bits.ka0c05_tlmem$v_tlstdere_0_ste#define ka0c05_tlmem$v_tlstdere_0_vrc ka0c05_tlmem$r_tlstdere_0_overlay.ka0c05_tlmem$r_tlstdere_0_bits.ka0c05_tlmem$v_tlstdere_0_vrcQ#define ka0c05_tlmem$l_tlddr0 ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$l_tlddr0t#define ka0c05_tlmem$v_tlddr0_loe ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_loev#define ka0c05_tlmem$v_tlddr0_cder ka0c025_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_cderv#define ka0c05_tlmem$v_tlddr0_icfr ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_icfrt#define ka0c05_tlmem$v_tlddr0_pat ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_patv#define ka0c05_tlmem$v_tlddr0_cflp ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_cflpv#define ka0c05_tlmem$v_tlddr0_dflp ka0c05_tlmem$r_tlddr0_overlay.ka02c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_dflpx#define ka0c05_tlmem$v_tlddr0_eflpc ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_eflpcx#define ka0c05_tlmem$v_tlddr0_eflpd ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_eflpdv#define ka0c05_tlmem$v_tlddr0_marg ka0c05_tlmem$r_tlddr0_overlay.ka0c05_tlmem$r_tlddr0_bits.ka0c05_tlmem$v_tlddr0_marg]#define ka0c05_tlmem$l_tlstdera_1 ka0c05_tlmem$r_tlstdera_1_overlay.ka0c05_tlmem$l_tlstder2a_1]#define ka0c05_tlmem$l_tlstderb_1 ka0c05_tlmem$r_tlstderb_1_overlay.ka0c05_tlmem$l_tlstderb_1]#define ka0c05_tlmem$l_tlstderc_1 ka0c05_tlmem$r_tlstderc_1_overlay.ka0c05_tlmem$l_tlstderc_1]#define ka0c05_tlmem$l_tlstderd_1 ka0c05_tlmem$r_tlstderd_1_overlay.ka0c05_tlmem$l_tlstderd_1]#define ka0c05_tlmem$l_tlstdere_1 ka0c05_tlmem$r_tlstdere_1_overlay.ka0c05_tlmem$l_tlstdere_1#define ka0c05_tlmem$v_tlstdere_1_ste ka0c05_tlmem$r_tlstdere_1_overlay.ka0c05_tlmem$r_tlstdere_1_bits.ka0c05_tlmem$2v_tlstdere_1_ste#define ka0c05_tlmem$v_tlstdere_1_vrc ka0c05_tlmem$r_tlstdere_1_overlay.ka0c05_tlmem$r_tlstdere_1_bits.ka0c05_tlmem$v_tlstdere_1_vrcQ#define ka0c05_tlmem$l_tlddr1 ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$l_tlddr1t#define ka0c05_tlmem$v_tlddr1_loe ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_loev#define ka0c05_tlmem$v_tlddr1_cder ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_cderv#define ka0c05_tlmem$v_tlddr1_ic2fr ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_icfrt#define ka0c05_tlmem$v_tlddr1_pat ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_patv#define ka0c05_tlmem$v_tlddr1_cflp ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_cflpv#define ka0c05_tlmem$v_tlddr1_dflp ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_dflpx#define ka0c05_tlmem$v_tlddr1_eflpc ka0c05_tlmem$r_tlddr1_ov2erlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_eflpcx#define ka0c05_tlmem$v_tlddr1_eflpd ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_eflpdv#define ka0c05_tlmem$v_tlddr1_marg ka0c05_tlmem$r_tlddr1_overlay.ka0c05_tlmem$r_tlddr1_bits.ka0c05_tlmem$v_tlddr1_marg]#define ka0c05_tlmem$l_tlstdera_2 ka0c05_tlmem$r_tlstdera_2_overlay.ka0c05_tlmem$l_tlstdera_2]#define ka0c05_tlmem$l_tlstderb_2 ka0c05_tlmem$r_tlstderb_2_overlay.ka0c05_tlmem$l_tlstderb_2]#define ka20c05_tlmem$l_tlstderc_2 ka0c05_tlmem$r_tlstderc_2_overlay.ka0c05_tlmem$l_tlstderc_2]#define ka0c05_tlmem$l_tlstderd_2 ka0c05_tlmem$r_tlstderd_2_overlay.ka0c05_tlmem$l_tlstderd_2]#define ka0c05_tlmem$l_tlstdere_2 ka0c05_tlmem$r_tlstdere_2_overlay.ka0c05_tlmem$l_tlstdere_2#define ka0c05_tlmem$v_tlstdere_2_ste ka0c05_tlmem$r_tlstdere_2_overlay.ka0c05_tlmem$r_tlstdere_2_bits.ka0c05_tlmem$v_tlstdere_2_ste#define ka0c05_tlmem$v_tlstdere_2_vrc ka0c05_tlmem$r_tlstdere_2_overlay.ka0c05_tlmem$r_tlstder2e_2_bits.ka0c05_tlmem$v_tlstdere_2_vrcQ#define ka0c05_tlmem$l_tlddr2 ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$l_tlddr2t#define ka0c05_tlmem$v_tlddr2_loe ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_loev#define ka0c05_tlmem$v_tlddr2_cder ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_cderv#define ka0c05_tlmem$v_tlddr2_icfr ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_icfrt#define ka0c05_tlmem$v_t2lddr2_pat ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_patv#define ka0c05_tlmem$v_tlddr2_cflp ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_cflpv#define ka0c05_tlmem$v_tlddr2_dflp ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_dflpx#define ka0c05_tlmem$v_tlddr2_eflpc ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_eflpcx#define ka0c05_tlmem$v_tlddr2_eflpd ka0c05_tlmem$r2_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_eflpdv#define ka0c05_tlmem$v_tlddr2_marg ka0c05_tlmem$r_tlddr2_overlay.ka0c05_tlmem$r_tlddr2_bits.ka0c05_tlmem$v_tlddr2_marg]#define ka0c05_tlmem$l_tlstdera_3 ka0c05_tlmem$r_tlstdera_3_overlay.ka0c05_tlmem$l_tlstdera_3]#define ka0c05_tlmem$l_tlstderb_3 ka0c05_tlmem$r_tlstderb_3_overlay.ka0c05_tlmem$l_tlstderb_3]#define ka0c05_tlmem$l_tlstderc_3 ka0c05_tlmem$r_tlstderc_3_overlay.ka0c05_tlmem$l_tlstderc_3]#define ka0c05_tlmem$l_tls2tderd_3 ka0c05_tlmem$r_tlstderd_3_overlay.ka0c05_tlmem$l_tlstderd_3]#define ka0c05_tlmem$l_tlstdere_3 ka0c05_tlmem$r_tlstdere_3_overlay.ka0c05_tlmem$l_tlstdere_3#define ka0c05_tlmem$v_tlstdere_3_ste ka0c05_tlmem$r_tlstdere_3_overlay.ka0c05_tlmem$r_tlstdere_3_bits.ka0c05_tlmem$v_tlstdere_3_ste#define ka0c05_tlmem$v_tlstdere_3_vrc ka0c05_tlmem$r_tlstdere_3_overlay.ka0c05_tlmem$r_tlstdere_3_bits.ka0c05_tlmem$v_tlstdere_3_vrcQ#define ka0c05_tlmem$l_tlddr3 ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem2$l_tlddr3t#define ka0c05_tlmem$v_tlddr3_loe ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_loev#define ka0c05_tlmem$v_tlddr3_cder ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_cderv#define ka0c05_tlmem$v_tlddr3_icfr ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_icfrt#define ka0c05_tlmem$v_tlddr3_pat ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_patv#define ka0c05_tlm2em$v_tlddr3_cflp ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_cflpv#define ka0c05_tlmem$v_tlddr3_dflp ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_dflpx#define ka0c05_tlmem$v_tlddr3_eflpc ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_eflpcx#define ka0c05_tlmem$v_tlddr3_eflpd ka0c05_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_eflpdv#define ka0c05_tlmem$v_tlddr3_marg ka0c025_tlmem$r_tlddr3_overlay.ka0c05_tlmem$r_tlddr3_bits.ka0c05_tlmem$v_tlddr3_marg"#endif /* #if !defined(__VAXC) */ #define KA0C05_CMD$K_NOP 0#define KA0C05_CMD$K_VICTIM 1#define KA0C05_CMD$K_BUS_READ 2 #define KA0C05_CMD$K_BUS_WRITE 3%#define KA0C05_CMD$K_READ_BANK_LOCK 4(#define KA0C05_CMD$K_WRITE_BANK_UNLOCK 5#define KA0C05_CMD$K_CSR_READ 6 #define KA0C05_CMD$K_CSR_WRITE 7(#define KA0C05_TIOP$M_TLDEV_DTYPE 0xFFFF*#define KA0C05_TIOP$M_TLDEV_SWREV 0xFF0000,#define KA0C05_TIOP$M_2TLDEV_HWREV 0xFF000000$#define KA0C05_TIOP$M_TLBER_ATCE 0x1##define KA0C05_TIOP$M_TLBER_APE 0x2##define KA0C05_TIOP$M_TLBER_BBE 0x4$#define KA0C05_TIOP$M_TLBER_LKTO 0x8$#define KA0C05_TIOP$M_TLBER_NAE 0x10%#define KA0C05_TIOP$M_TLBER_RTCE 0x20'#define KA0C05_TIOP$M_TLBER_ACKTCE 0x40%#define KA0C05_TIOP$M_TLBER_MMRE 0x80&#define KA0C05_TIOP$M_TLBER_FNAE 0x100'#define KA0C05_TIOP$M_TLBER_REQDE 0x200&#define KA0C05_TIOP$M_TLBER_ATDE 0x400'#define KA0C05_TIOP$M_TLBER_UDE 0x10000(#defin 2e KA0C05_TIOP$M_TLBER_CWDE 0x20000(#define KA0C05_TIOP$M_TLBER_CRDE 0x40000(#define KA0C05_TIOP$M_TLBER_DS0 0x100000(#define KA0C05_TIOP$M_TLBER_DS1 0x200000(#define KA0C05_TIOP$M_TLBER_DS2 0x400000(#define KA0C05_TIOP$M_TLBER_DS3 0x800000*#define KA0C05_TIOP$M_TLBER_DTDE 0x1000000+#define KA0C05_TIOP$M_TLBER_FDTCE 0x2000000+#define KA0C05_TIOP$M_TLBER_UACKE 0x4000000+#define KA0C05_TIOP$M_TLBER_ABTCE 0x8000000,#define KA0C05_TIOP$M_TLBER_DCTCE 0x10000000+#define KA0C05_TIOP$M_TLBER_SEQE2 0x20000000*#define KA0C05_TIOP$M_TLBER_DSE 0x40000000*#define KA0C05_TIOP$M_TLBER_DTO 0x80000000$#define KA0C05_TIOP$M_TLCNR_CWDD 0x1$#define KA0C05_TIOP$M_TLCNR_CRDD 0x2%#define KA0C05_TIOP$M_TLCNR_LKTOD 0x4$#define KA0C05_TIOP$M_TLCNR_DTOD 0x8(#define KA0C05_TIOP$M_TLCNR_NODE_ID 0xF0&#define KA0C05_TIOP$M_TLCNR_VCNT 0xF00(#define KA0C05_TIOP$M_TLCNR_STF_A 0x1000(#define KA0C05_TIOP$M_TLCNR_STF_B 0x2000(#define KA0C05_TIOP$M_TLCNR_STF_C 0x4000(#define KA0C05_TIOP$M_TLCNR_STF_D 0x8000) 2#define KA0C05_TIOP$M_TLCNR_STF_E 0x10000)#define KA0C05_TIOP$M_TLCNR_STF_F 0x20000)#define KA0C05_TIOP$M_TLCNR_STF_G 0x40000)#define KA0C05_TIOP$M_TLCNR_STF_H 0x80000+#define KA0C05_TIOP$M_TLCNR_HALT_A 0x100000+#define KA0C05_TIOP$M_TLCNR_HALT_B 0x200000+#define KA0C05_TIOP$M_TLCNR_HALT_C 0x400000+#define KA0C05_TIOP$M_TLCNR_HALT_D 0x800000,#define KA0C05_TIOP$M_TLCNR_HALT_E 0x1000000,#define KA0C05_TIOP$M_TLCNR_HALT_F 0x2000000,#define KA0C05_TIOP$M_TLCNR_HALT_G 0x4000000,#define 2KA0C05_TIOP$M_TLCNR_HALT_H 0x8000000.#define KA0C05_TIOP$M_TLCNR_RSTSTAT 0x10000000+#define KA0C05_TIOP$M_TLCNR_NRST 0x40000000+#define KA0C05_TIOP$M_TLCNR_LOFE 0x80000000(#define KA0C05_TIOP$M_TLMMR0_INTMASK 0x3)#define KA0C05_TIOP$M_TLMMR0_ADRMASK 0xF0(#define KA0C05_TIOP$M_TLMMR0_INTLV 0x700(#define KA0C05_TIOP$M_TLMMR0_SBANK 0x800.#define KA0C05_TIOP$M_TLMMR0_ADDRESS 0x3FFF000-#define KA0C05_TIOP$M_TLMMR0_VALID 0x80000000(#define KA0C05_TIOP$M_TLMMR1_INTMASK 0x3)#define KA0C05_TIOP$ 2M_TLMMR1_ADRMASK 0xF0(#define KA0C05_TIOP$M_TLMMR1_INTLV 0x700(#define KA0C05_TIOP$M_TLMMR1_SBANK 0x800.#define KA0C05_TIOP$M_TLMMR1_ADDRESS 0x3FFF000-#define KA0C05_TIOP$M_TLMMR1_VALID 0x80000000(#define KA0C05_TIOP$M_TLMMR2_INTMASK 0x3)#define KA0C05_TIOP$M_TLMMR2_ADRMASK 0xF0(#define KA0C05_TIOP$M_TLMMR2_INTLV 0x700(#define KA0C05_TIOP$M_TLMMR2_SBANK 0x800.#define KA0C05_TIOP$M_TLMMR2_ADDRESS 0x3FFF000-#define KA0C05_TIOP$M_TLMMR2_VALID 0x80000000(#define KA0C05_TIOP$M_TLMMR3_INTMASK 2 0x3)#define KA0C05_TIOP$M_TLMMR3_ADRMASK 0xF0(#define KA0C05_TIOP$M_TLMMR3_INTLV 0x700(#define KA0C05_TIOP$M_TLMMR3_SBANK 0x800.#define KA0C05_TIOP$M_TLMMR3_ADDRESS 0x3FFF000-#define KA0C05_TIOP$M_TLMMR3_VALID 0x80000000(#define KA0C05_TIOP$M_TLMMR4_INTMASK 0x3)#define KA0C05_TIOP$M_TLMMR4_ADRMASK 0xF0(#define KA0C05_TIOP$M_TLMMR4_INTLV 0x700(#define KA0C05_TIOP$M_TLMMR4_SBANK 0x800.#define KA0C05_TIOP$M_TLMMR4_ADDRESS 0x3FFF000-#define KA0C05_TIOP$M_TLMMR4_VALID 0x80000000(#define KA 20C05_TIOP$M_TLMMR5_INTMASK 0x3)#define KA0C05_TIOP$M_TLMMR5_ADRMASK 0xF0(#define KA0C05_TIOP$M_TLMMR5_INTLV 0x700(#define KA0C05_TIOP$M_TLMMR5_SBANK 0x800.#define KA0C05_TIOP$M_TLMMR5_ADDRESS 0x3FFF000-#define KA0C05_TIOP$M_TLMMR5_VALID 0x80000000(#define KA0C05_TIOP$M_TLMMR6_INTMASK 0x3)#define KA0C05_TIOP$M_TLMMR6_ADRMASK 0xF0(#define KA0C05_TIOP$M_TLMMR6_INTLV 0x700(#define KA0C05_TIOP$M_TLMMR6_SBANK 0x800.#define KA0C05_TIOP$M_TLMMR6_ADDRESS 0x3FFF000-#define KA0C05_TIOP$M_TLMMR6_VAL 2ID 0x80000000(#define KA0C05_TIOP$M_TLMMR7_INTMASK 0x3)#define KA0C05_TIOP$M_TLMMR7_ADRMASK 0xF0(#define KA0C05_TIOP$M_TLMMR7_INTLV 0x700(#define KA0C05_TIOP$M_TLMMR7_SBANK 0x800.#define KA0C05_TIOP$M_TLMMR7_ADDRESS 0x3FFF000-#define KA0C05_TIOP$M_TLMMR7_VALID 0x80000000-#define KA0C05_TIOP$M_TLFADR0_FADR 0xFFFFFFF8'#define KA0C05_TIOP$M_TLFADR1_FADR 0xFF*#define KA0C05_TIOP$M_TLFADR1_FCMD 0x70000,#define KA0C05_TIOP$M_TLFADR1_FBANK 0xF00000,#define KA0C05_TIOP$M_TLFADR1_ADRV 0x1000000 2,#define KA0C05_TIOP$M_TLFADR1_CMDV 0x2000000-#define KA0C05_TIOP$M_TLFADR1_BANKV 0x4000000'#define KA0C05_TIOP$M_TLESR0_SYND0 0xFF)#define KA0C05_TIOP$M_TLESR0_SYND1 0xFF00(#define KA0C05_TIOP$M_TLESR0_TDE 0x10000(#define KA0C05_TIOP$M_TLESR0_TCE 0x20000*#define KA0C05_TIOP$M_TLESR0_DVTCE 0x40000)#define KA0C05_TIOP$M_TLESR0_UECC 0x80000+#define KA0C05_TIOP$M_TLESR0_CWECC 0x100000+#define KA0C05_TIOP$M_TLESR0_CRECC 0x200000.#define KA0C05_TIOP$M_TLESR0_LOFSYN 0x80000000'#define KA0C 205_TIOP$M_TLESR1_SYND0 0xFF)#define KA0C05_TIOP$M_TLESR1_SYND1 0xFF00(#define KA0C05_TIOP$M_TLESR1_TDE 0x10000(#define KA0C05_TIOP$M_TLESR1_TCE 0x20000*#define KA0C05_TIOP$M_TLESR1_DVTCE 0x40000)#define KA0C05_TIOP$M_TLESR1_UECC 0x80000+#define KA0C05_TIOP$M_TLESR1_CWECC 0x100000+#define KA0C05_TIOP$M_TLESR1_CRECC 0x200000.#define KA0C05_TIOP$M_TLESR1_LOFSYN 0x80000000'#define KA0C05_TIOP$M_TLESR2_SYND0 0xFF)#define KA0C05_TIOP$M_TLESR2_SYND1 0xFF00(#define KA0C05_TIOP$M_TLESR2_TDE 0 2x10000(#define KA0C05_TIOP$M_TLESR2_TCE 0x20000*#define KA0C05_TIOP$M_TLESR2_DVTCE 0x40000)#define KA0C05_TIOP$M_TLESR2_UECC 0x80000+#define KA0C05_TIOP$M_TLESR2_CWECC 0x100000+#define KA0C05_TIOP$M_TLESR2_CRECC 0x200000.#define KA0C05_TIOP$M_TLESR2_LOFSYN 0x80000000'#define KA0C05_TIOP$M_TLESR3_SYND0 0xFF)#define KA0C05_TIOP$M_TLESR3_SYND1 0xFF00(#define KA0C05_TIOP$M_TLESR3_TDE 0x10000(#define KA0C05_TIOP$M_TLESR3_TCE 0x20000*#define KA0C05_TIOP$M_TLESR3_DVTCE 0x40000)#define KA0C05 2_TIOP$M_TLESR3_UECC 0x80000+#define KA0C05_TIOP$M_TLESR3_CWECC 0x100000+#define KA0C05_TIOP$M_TLESR3_CRECC 0x200000.#define KA0C05_TIOP$M_TLESR3_LOFSYN 0x80000000*#define KA0C05_TIOP$M_TLILID0_IDENT 0xFFFF*#define KA0C05_TIOP$M_TLILID1_IDENT 0xFFFF*#define KA0C05_TIOP$M_TLILID2_IDENT 0xFFFF*#define KA0C05_TIOP$M_TLILID3_IDENT 0xFFFF+#define KA0C05_TIOP$M_TLCPUMASK_MASK 0xFFFF&#define KA0C05_TIOP$M_TLRMR0A_MASK 0xF)#define KA0C05_TIOP$M_TLRMR0A_ILV_EN 0x10,#define KA0C05_TIOP$M_TLRMR0A_ 2BADR 0xFFFFF00.#define KA0C05_TIOP$M_TLRMR0A_NVRAM 0x40000000.#define KA0C05_TIOP$M_TLRMR0A_VALID 0x80000000&#define KA0C05_TIOP$M_TLRMR0B_MASK 0xF)#define KA0C05_TIOP$M_TLRMR0B_ILV_EN 0x10,#define KA0C05_TIOP$M_TLRMR0B_BADR 0xFFFFF00.#define KA0C05_TIOP$M_TLRMR0B_NVRAM 0x40000000.#define KA0C05_TIOP$M_TLRMR0B_VALID 0x80000000&#define KA0C05_TIOP$M_TLRMR1A_MASK 0xF)#define KA0C05_TIOP$M_TLRMR1A_ILV_EN 0x10,#define KA0C05_TIOP$M_TLRMR1A_BADR 0xFFFFF00.#define KA0C05_TIOP$M_TLRMR1A_NVRAM 0x 240000000.#define KA0C05_TIOP$M_TLRMR1A_VALID 0x80000000&#define KA0C05_TIOP$M_TLRMR1B_MASK 0xF)#define KA0C05_TIOP$M_TLRMR1B_ILV_EN 0x10,#define KA0C05_TIOP$M_TLRMR1B_BADR 0xFFFFF00.#define KA0C05_TIOP$M_TLRMR1B_NVRAM 0x40000000.#define KA0C05_TIOP$M_TLRMR1B_VALID 0x80000000)#define KA0C05_TIOP$M_TLICMSR_ARB_CTL 0x3)#define KA0C05_TIOP$M_TLICMSR_SUP_CTL 0xC,#define KA0C05_TIOP$M_TLICMSR_FORCE_ACK 0x10(#define KA0C05_TIOP$M_TLICMSR_RMNXM 0x20+#define KA0C05_TIOP$M_TLICMSR_ACK_DSBL 0x40* 2#define KA0C05_TIOP$M_TLICNSE_ACK_DROP 0x4'#define KA0C05_TIOP$M_TLICNSE_RMNXM 0x8+#define KA0C05_TIOP$M_TLICNSE_MBX_STAT 0xF0(#define KA0C05_TIOP$M_TLICNSE_OFLO 0xF00*#define KA0C05_TIOP$M_TLICNSE_PKT_E 0xF000+#define KA0C05_TIOP$M_TLICNSE_PAR_E 0xF00000#define KA0C05_TIOP$M_TLICNSE_UP_HDP_IE 0x300000,#define KA0C05_TIOP$M_TLICNSE_INT_E 0x4000001#define KA0C05_TIOP$M_TLICNSE_DN_VRTX_E 0x18000001#define KA0C05_TIOP$M_TLICNSE_UP_VRTX_E 0x6000000*#define KA0C05_TIOP$M_TLICNSE_IE 0x8000000 2/#define KA0C05_TIOP$M_TLICNSE_BUS_PE 0x100000001#define KA0C05_TIOP$M_TLICNSE_WND_OFLO 0x200000000#define KA0C05_TIOP$M_TLICNSE_RM_OFLO 0x400000001#define KA0C05_TIOP$M_TLICNSE_INT_NSES 0x80000000'#define KA0C05_TIOP$M_TLICDR_IDP_PE 0x1$#define KA0C05_TIOP$M_TLICDR_DSE 0x2$#define KA0C05_TIOP$M_TLICDR_DTO 0x4(#define KA0C05_TIOP$M_TLICDR_DIS_CMD 0x8)#define KA0C05_TIOP$M_TLICDR_DIS_FLT 0x10(#define KA0C05_TIOP$M_TLICDR_CMD_PE 0x20)#define KA0C05_TIOP$M_TLICDR_BNK_BSY 0x40-#define KA 20C05_TIOP$M_TLICDR_IDP_CMD_PE 0x100.#define KA0C05_TIOP$M_TLICDR_EN_HID 0x80000000)#define KA0C05_TIOP$M_TLICMTR_MBX_TIP 0xF%#define KA0C05_TIOP$M_TLICWRT_WIP 0xF&#define KA0C05_TIOP$M_TLIDPNSE_ERR 0x1&#define KA0C05_TIOP$M_TLIDPNSE_POK 0x2(#define KA0C05_TIOP$M_TLIDPNSE_CBLOK 0x4+#define KA0C05_TIOP$M_TLIDPNSE_POK_TRAN 0x8,#define KA0C05_TIOP$M_TLIDPNSE_SOFT_ERR 0x100#define KA0C05_TIOP$M_TLIDPNSE_RM_M_ERR 0xC00000,#define KA0C05_TIOP$M_TLIDPNSE_CPE 0x10000001#define KA0C05_TIOP$M_TLID 2PNSE_UP_V_ERR 0x6000000+#define KA0C05_TIOP$M_TLIDPNSE_IE 0x8000000,#define KA0C05_TIOP$M_TLIDPNSE_PE 0x10000000/#define KA0C05_TIOP$M_TLIDPNSE_RESET 0x80000000)#define KA0C05_TIOP$M_TLIPMASK_CPU 0xFFFF+#define KA0C05_TIOP$M_TLIDPVR_VECTOR 0xFFFF(#define KA0C05_TIOP$M_TLIBR_RCV_SDAT 0x1(#define KA0C05_TIOP$M_TLIBR_XMT_SDAT 0x2$#define KA0C05_TIOP$M_TLIBR_SCLK 0x4 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_a2lignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0c05_tiop {#pragma __nomember_alignment __union {) unsigned int ka0c05_tiop$l_tldev; __struct {4 unsigned ka0c05_tiop$v_tldev_dtype : 16;3 unsigned ka0c05_tiop$v_tldev_swrev : 8;3 unsigned ka0c05_tiop$v_tldev_hwrev : 8;' } ka0c05_tiop$r_tldev_bits;& } ka0c05_tiop$r_tldev_overlay;+ unsigned char ka0c05_tiop$b_f1400 [60]; 2__union {) unsigned int ka0c05_tiop$l_tlber; __struct {2 unsigned ka0c05_tiop$v_tlber_atce : 1;1 unsigned ka0c05_tiop$v_tlber_ape : 1;1 unsigned ka0c05_tiop$v_tlber_bbe : 1;2 unsigned ka0c05_tiop$v_tlber_lkto : 1;1 unsigned ka0c05_tiop$v_tlber_nae : 1;2 unsigned ka0c05_tiop$v_tlber_rtce : 1;4 unsigned ka0c05_tiop$v_tlber_acktce : 1;2 unsigned ka0c05_tiop$v_tlber_mmre : 1;2 2 unsigned ka0c05_tiop$v_tlber_fnae : 1;3 unsigned ka0c05_tiop$v_tlber_reqde : 1;2 unsigned ka0c05_tiop$v_tlber_atde : 1;0 unsigned ka0c05_tiop$v_tlber_f1 : 5;1 unsigned ka0c05_tiop$v_tlber_ude : 1;2 unsigned ka0c05_tiop$v_tlber_cwde : 1;2 unsigned ka0c05_tiop$v_tlber_crde : 1;3 unsigned ka0c05_tiop$v_tlber_cwde2 : 1;1 unsigned ka0c05_tiop$v_tlber_ds0 : 1;1 unsigned ka0c05_tiop$v_tlber_ds1 : 2 1;1 unsigned ka0c05_tiop$v_tlber_ds2 : 1;1 unsigned ka0c05_tiop$v_tlber_ds3 : 1;2 unsigned ka0c05_tiop$v_tlber_dtde : 1;3 unsigned ka0c05_tiop$v_tlber_fdtce : 1;3 unsigned ka0c05_tiop$v_tlber_uacke : 1;3 unsigned ka0c05_tiop$v_tlber_abtce : 1;3 unsigned ka0c05_tiop$v_tlber_dctce : 1;2 unsigned ka0c05_tiop$v_tlber_seqe : 1;1 unsigned ka0c05_tiop$v_tlber_dse : 1;1 unsigned ka0 2c05_tiop$v_tlber_dto : 1;' } ka0c05_tiop$r_tlber_bits;& } ka0c05_tiop$r_tlber_overlay;+ unsigned char ka0c05_tiop$b_f1410 [60]; __union {) unsigned int ka0c05_tiop$l_tlcnr; __struct {2 unsigned ka0c05_tiop$v_tlcnr_cwdd : 1;2 unsigned ka0c05_tiop$v_tlcnr_crdd : 1;3 unsigned ka0c05_tiop$v_tlcnr_lktod : 1;2 unsigned ka0c05_tiop$v_tlcnr_dtod : 1;5 unsigned ka0c05_tiop$v_tlcnr_node_id : 4;2 2 unsigned ka0c05_tiop$v_tlcnr_vcnt : 4;3 unsigned ka0c05_tiop$v_tlcnr_stf_a : 1;3 unsigned ka0c05_tiop$v_tlcnr_stf_b : 1;3 unsigned ka0c05_tiop$v_tlcnr_stf_c : 1;3 unsigned ka0c05_tiop$v_tlcnr_stf_d : 1;3 unsigned ka0c05_tiop$v_tlcnr_stf_e : 1;3 unsigned ka0c05_tiop$v_tlcnr_stf_f : 1;3 unsigned ka0c05_tiop$v_tlcnr_stf_g : 1;3 unsigned ka0c05_tiop$v_tlcnr_stf_h : 1;4 unsigned ka0 2c05_tiop$v_tlcnr_halt_a : 1;4 unsigned ka0c05_tiop$v_tlcnr_halt_b : 1;4 unsigned ka0c05_tiop$v_tlcnr_halt_c : 1;4 unsigned ka0c05_tiop$v_tlcnr_halt_d : 1;4 unsigned ka0c05_tiop$v_tlcnr_halt_e : 1;4 unsigned ka0c05_tiop$v_tlcnr_halt_f : 1;4 unsigned ka0c05_tiop$v_tlcnr_halt_g : 1;4 unsigned ka0c05_tiop$v_tlcnr_halt_h : 1;5 unsigned ka0c05_tiop$v_tlcnr_rststat : 1;0 unsigned ka0c05_tiop$v_tlcnr_f 21 : 1;2 unsigned ka0c05_tiop$v_tlcnr_nrst : 1;2 unsigned ka0c05_tiop$v_tlcnr_lofe : 1;' } ka0c05_tiop$r_tlcnr_bits;& } ka0c05_tiop$r_tlcnr_overlay;, unsigned char ka0c05_tiop$b_f1420 [380]; __union {* unsigned int ka0c05_tiop$l_tlmmr0; __struct {6 unsigned ka0c05_tiop$v_tlmmr0_intmask : 2;1 unsigned ka0c05_tiop$v_tlmmr0_f1 : 2;6 unsigned ka0c05_tiop$v_tlmmr0_adrmask : 4;4 unsigned 2 ka0c05_tiop$v_tlmmr0_intlv : 3;4 unsigned ka0c05_tiop$v_tlmmr0_sbank : 1;7 unsigned ka0c05_tiop$v_tlmmr0_address : 14;1 unsigned ka0c05_tiop$v_tlmmr0_f2 : 5;4 unsigned ka0c05_tiop$v_tlmmr0_valid : 1;( } ka0c05_tiop$r_tlmmr0_bits;' } ka0c05_tiop$r_tlmmr0_overlay;+ unsigned char ka0c05_tiop$b_f1440 [60]; __union {* unsigned int ka0c05_tiop$l_tlmmr1; __struct {6 unsigned ka0c05_tiop$v_tlmmr1_ 2intmask : 2;1 unsigned ka0c05_tiop$v_tlmmr1_f1 : 2;6 unsigned ka0c05_tiop$v_tlmmr1_adrmask : 4;4 unsigned ka0c05_tiop$v_tlmmr1_intlv : 3;4 unsigned ka0c05_tiop$v_tlmmr1_sbank : 1;7 unsigned ka0c05_tiop$v_tlmmr1_address : 14;1 unsigned ka0c05_tiop$v_tlmmr1_f2 : 5;4 unsigned ka0c05_tiop$v_tlmmr1_valid : 1;( } ka0c05_tiop$r_tlmmr1_bits;' } ka0c05_tiop$r_tlmmr1_overlay;+ unsigned char ka0c05_tio 2p$b_f1450 [60]; __union {* unsigned int ka0c05_tiop$l_tlmmr2; __struct {6 unsigned ka0c05_tiop$v_tlmmr2_intmask : 2;1 unsigned ka0c05_tiop$v_tlmmr2_f1 : 2;6 unsigned ka0c05_tiop$v_tlmmr2_adrmask : 4;4 unsigned ka0c05_tiop$v_tlmmr2_intlv : 3;4 unsigned ka0c05_tiop$v_tlmmr2_sbank : 1;7 unsigned ka0c05_tiop$v_tlmmr2_address : 14;1 unsigned ka0c05_tiop$v_tlmmr2_f2 : 5;4 unsigned ka0 3c05_tiop$v_tlmmr2_valid : 1;( } ka0c05_tiop$r_tlmmr2_bits;' } ka0c05_tiop$r_tlmmr2_overlay;+ unsigned char ka0c05_tiop$b_f1460 [60]; __union {* unsigned int ka0c05_tiop$l_tlmmr3; __struct {6 unsigned ka0c05_tiop$v_tlmmr3_intmask : 2;1 unsigned ka0c05_tiop$v_tlmmr3_f1 : 2;6 unsigned ka0c05_tiop$v_tlmmr3_adrmask : 4;4 unsigned ka0c05_tiop$v_tlmmr3_intlv : 3;4 unsigned ka0c05_tiop$v_tlmmr3_sban 3k : 1;7 unsigned ka0c05_tiop$v_tlmmr3_address : 14;1 unsigned ka0c05_tiop$v_tlmmr3_f2 : 5;4 unsigned ka0c05_tiop$v_tlmmr3_valid : 1;( } ka0c05_tiop$r_tlmmr3_bits;' } ka0c05_tiop$r_tlmmr3_overlay;+ unsigned char ka0c05_tiop$b_f1470 [60]; __union {* unsigned int ka0c05_tiop$l_tlmmr4; __struct {6 unsigned ka0c05_tiop$v_tlmmr4_intmask : 2;1 unsigned ka0c05_tiop$v_tlmmr4_f1 : 2;6 un 3signed ka0c05_tiop$v_tlmmr4_adrmask : 4;4 unsigned ka0c05_tiop$v_tlmmr4_intlv : 3;4 unsigned ka0c05_tiop$v_tlmmr4_sbank : 1;7 unsigned ka0c05_tiop$v_tlmmr4_address : 14;1 unsigned ka0c05_tiop$v_tlmmr4_f2 : 5;4 unsigned ka0c05_tiop$v_tlmmr4_valid : 1;( } ka0c05_tiop$r_tlmmr4_bits;' } ka0c05_tiop$r_tlmmr4_overlay;+ unsigned char ka0c05_tiop$b_f1480 [60]; __union {* unsigned int ka0c05_tiop$l_tlmmr5; 3 __struct {6 unsigned ka0c05_tiop$v_tlmmr5_intmask : 2;1 unsigned ka0c05_tiop$v_tlmmr5_f1 : 2;6 unsigned ka0c05_tiop$v_tlmmr5_adrmask : 4;4 unsigned ka0c05_tiop$v_tlmmr5_intlv : 3;4 unsigned ka0c05_tiop$v_tlmmr5_sbank : 1;7 unsigned ka0c05_tiop$v_tlmmr5_address : 14;1 unsigned ka0c05_tiop$v_tlmmr5_f2 : 5;4 unsigned ka0c05_tiop$v_tlmmr5_valid : 1;( } ka0c05_tiop$r_tlmmr5_bits;' 3} ka0c05_tiop$r_tlmmr5_overlay;+ unsigned char ka0c05_tiop$b_f1490 [60]; __union {* unsigned int ka0c05_tiop$l_tlmmr6; __struct {6 unsigned ka0c05_tiop$v_tlmmr6_intmask : 2;1 unsigned ka0c05_tiop$v_tlmmr6_f1 : 2;6 unsigned ka0c05_tiop$v_tlmmr6_adrmask : 4;4 unsigned ka0c05_tiop$v_tlmmr6_intlv : 3;4 unsigned ka0c05_tiop$v_tlmmr6_sbank : 1;7 unsigned ka0c05_tiop$v_tlmmr6_address : 14;1 un 3signed ka0c05_tiop$v_tlmmr6_f2 : 5;4 unsigned ka0c05_tiop$v_tlmmr6_valid : 1;( } ka0c05_tiop$r_tlmmr6_bits;' } ka0c05_tiop$r_tlmmr6_overlay;+ unsigned char ka0c05_tiop$b_f1500 [60]; __union {* unsigned int ka0c05_tiop$l_tlmmr7; __struct {6 unsigned ka0c05_tiop$v_tlmmr7_intmask : 2;1 unsigned ka0c05_tiop$v_tlmmr7_f1 : 2;6 unsigned ka0c05_tiop$v_tlmmr7_adrmask : 4;4 unsigned ka0c05_tiop$v_tlm 3mr7_intlv : 3;4 unsigned ka0c05_tiop$v_tlmmr7_sbank : 1;7 unsigned ka0c05_tiop$v_tlmmr7_address : 14;1 unsigned ka0c05_tiop$v_tlmmr7_f2 : 5;4 unsigned ka0c05_tiop$v_tlmmr7_valid : 1;( } ka0c05_tiop$r_tlmmr7_bits;' } ka0c05_tiop$r_tlmmr7_overlay;, unsigned char ka0c05_tiop$b_f1510 [572]; __union {+ unsigned int ka0c05_tiop$l_tlfadr0; __struct {2 unsigned ka0c05_tiop$v_tlfadr0_f1 : 3;5 3 unsigned ka0c05_tiop$v_tlfadr0_fadr : 29;) } ka0c05_tiop$r_tlfadr0_bits;( } ka0c05_tiop$r_tlfadr0_overlay;+ unsigned char ka0c05_tiop$b_f1520 [60]; __union {+ unsigned int ka0c05_tiop$l_tlfadr1; __struct {4 unsigned ka0c05_tiop$v_tlfadr1_fadr : 8;2 unsigned ka0c05_tiop$v_tlfadr1_f1 : 8;4 unsigned ka0c05_tiop$v_tlfadr1_fcmd : 3;2 unsigned ka0c05_tiop$v_tlfadr1_f2 : 1;5 unsigned ka0c05_ 3tiop$v_tlfadr1_fbank : 4;4 unsigned ka0c05_tiop$v_tlfadr1_adrv : 1;4 unsigned ka0c05_tiop$v_tlfadr1_cmdv : 1;5 unsigned ka0c05_tiop$v_tlfadr1_bankv : 1;5 unsigned ka0c05_tiop$v_tlfadr1_fill3 : 5;) } ka0c05_tiop$r_tlfadr1_bits;( } ka0c05_tiop$r_tlfadr1_overlay;+ unsigned char ka0c05_tiop$b_f1530 [60]; __union {* unsigned int ka0c05_tiop$l_tlesr0; __struct {4 unsigned ka0c05_tiop$v_tlesr0_sy 3nd0 : 8;4 unsigned ka0c05_tiop$v_tlesr0_synd1 : 8;2 unsigned ka0c05_tiop$v_tlesr0_tde : 1;2 unsigned ka0c05_tiop$v_tlesr0_tce : 1;4 unsigned ka0c05_tiop$v_tlesr0_dvtce : 1;3 unsigned ka0c05_tiop$v_tlesr0_uecc : 1;4 unsigned ka0c05_tiop$v_tlesr0_cwecc : 1;4 unsigned ka0c05_tiop$v_tlesr0_crecc : 1;1 unsigned ka0c05_tiop$v_tlesr0_f1 : 9;5 unsigned ka0c05_tiop$v_tlesr0_lofsyn : 1;( } 3ka0c05_tiop$r_tlesr0_bits;' } ka0c05_tiop$r_tlesr0_overlay;+ unsigned char ka0c05_tiop$b_f1540 [60]; __union {* unsigned int ka0c05_tiop$l_tlesr1; __struct {4 unsigned ka0c05_tiop$v_tlesr1_synd0 : 8;4 unsigned ka0c05_tiop$v_tlesr1_synd1 : 8;2 unsigned ka0c05_tiop$v_tlesr1_tde : 1;2 unsigned ka0c05_tiop$v_tlesr1_tce : 1;4 unsigned ka0c05_tiop$v_tlesr1_dvtce : 1;3 unsigned ka0c05_tiop$v_tlesr1_ 3uecc : 1;4 unsigned ka0c05_tiop$v_tlesr1_cwecc : 1;4 unsigned ka0c05_tiop$v_tlesr1_crecc : 1;1 unsigned ka0c05_tiop$v_tlesr1_f1 : 9;5 unsigned ka0c05_tiop$v_tlesr1_lofsyn : 1;( } ka0c05_tiop$r_tlesr1_bits;' } ka0c05_tiop$r_tlesr1_overlay;+ unsigned char ka0c05_tiop$b_f1550 [60]; __union {* unsigned int ka0c05_tiop$l_tlesr2; __struct {4 unsigned ka0c05_tiop$v_tlesr2_synd0 : 8;4 3unsigned ka0c05_tiop$v_tlesr2_synd1 : 8;2 unsigned ka0c05_tiop$v_tlesr2_tde : 1;2 unsigned ka0c05_tiop$v_tlesr2_tce : 1;4 unsigned ka0c05_tiop$v_tlesr2_dvtce : 1;3 unsigned ka0c05_tiop$v_tlesr2_uecc : 1;4 unsigned ka0c05_tiop$v_tlesr2_cwecc : 1;4 unsigned ka0c05_tiop$v_tlesr2_crecc : 1;1 unsigned ka0c05_tiop$v_tlesr2_f1 : 9;5 unsigned ka0c05_tiop$v_tlesr2_lofsyn : 1;( } ka0c05_tiop$r_tlesr2_b 3its;' } ka0c05_tiop$r_tlesr2_overlay;+ unsigned char ka0c05_tiop$b_f1560 [60]; __union {* unsigned int ka0c05_tiop$l_tlesr3; __struct {4 unsigned ka0c05_tiop$v_tlesr3_synd0 : 8;4 unsigned ka0c05_tiop$v_tlesr3_synd1 : 8;2 unsigned ka0c05_tiop$v_tlesr3_tde : 1;2 unsigned ka0c05_tiop$v_tlesr3_tce : 1;4 unsigned ka0c05_tiop$v_tlesr3_dvtce : 1;3 unsigned ka0c05_tiop$v_tlesr3_uecc : 1;4 3 unsigned ka0c05_tiop$v_tlesr3_cwecc : 1;4 unsigned ka0c05_tiop$v_tlesr3_crecc : 1;1 unsigned ka0c05_tiop$v_tlesr3_f1 : 9;5 unsigned ka0c05_tiop$v_tlesr3_lofsyn : 1;( } ka0c05_tiop$r_tlesr3_bits;' } ka0c05_tiop$r_tlesr3_overlay;, unsigned char ka0c05_tiop$b_f1570 [700]; __union {+ unsigned int ka0c05_tiop$l_tlilid0; __struct {6 unsigned ka0c05_tiop$v_tlilid0_ident : 16;3 unsigned ka0c05_ti3op$v_tlilid0_f1 : 16;) } ka0c05_tiop$r_tlilid0_bits;( } ka0c05_tiop$r_tlilid0_overlay;+ unsigned char ka0c05_tiop$b_f1580 [60]; __union {+ unsigned int ka0c05_tiop$l_tlilid1; __struct {6 unsigned ka0c05_tiop$v_tlilid1_ident : 16;3 unsigned ka0c05_tiop$v_tlilid1_f1 : 16;) } ka0c05_tiop$r_tlilid1_bits;( } ka0c05_tiop$r_tlilid1_overlay;+ unsigned char ka0c05_tiop$b_f1590 [60]; __union {+ 3unsigned int ka0c05_tiop$l_tlilid2; __struct {6 unsigned ka0c05_tiop$v_tlilid2_ident : 16;3 unsigned ka0c05_tiop$v_tlilid2_f1 : 16;) } ka0c05_tiop$r_tlilid2_bits;( } ka0c05_tiop$r_tlilid2_overlay;+ unsigned char ka0c05_tiop$b_f1600 [60]; __union {+ unsigned int ka0c05_tiop$l_tlilid3; __struct {6 unsigned ka0c05_tiop$v_tlilid3_ident : 16;3 unsigned ka0c05_tiop$v_tlilid3_f1 : 16;) 3 } ka0c05_tiop$r_tlilid3_bits;( } ka0c05_tiop$r_tlilid3_overlay;+ unsigned char ka0c05_tiop$b_f1610 [60]; __union {- unsigned int ka0c05_tiop$l_tlcpumask; __struct {7 unsigned ka0c05_tiop$v_tlcpumask_mask : 16;5 unsigned ka0c05_tiop$v_tlcpumask_f1 : 16;+ } ka0c05_tiop$r_tlcpumask_bits;* } ka0c05_tiop$r_tlcpumask_overlay;, unsigned char ka0c05_tiop$b_f1620 [252]; __union {% __int64 ka0c05_tiop$q_tl 3mbpr;' } ka0c05_tiop$r_tlmbpr_overlay;- unsigned char ka0c05_tiop$b_f1630 [4600]; __union {+ unsigned int ka0c05_tiop$l_tlrmr0a; __struct {4 unsigned ka0c05_tiop$v_tlrmr0a_mask : 4;6 unsigned ka0c05_tiop$v_tlrmr0a_ilv_en : 1;2 unsigned ka0c05_tiop$v_tlrmr0a_f1 : 3;5 unsigned ka0c05_tiop$v_tlrmr0a_badr : 20;2 unsigned ka0c05_tiop$v_tlrmr0a_f2 : 2;5 unsigned ka0c05_tiop$v_tlrmr0a_nvram : 1; 35 unsigned ka0c05_tiop$v_tlrmr0a_valid : 1;) } ka0c05_tiop$r_tlrmr0a_bits;( } ka0c05_tiop$r_tlrmr0a_overlay;+ unsigned char ka0c05_tiop$b_f1640 [60]; __union {+ unsigned int ka0c05_tiop$l_tlrmr0b; __struct {4 unsigned ka0c05_tiop$v_tlrmr0b_mask : 4;6 unsigned ka0c05_tiop$v_tlrmr0b_ilv_en : 1;2 unsigned ka0c05_tiop$v_tlrmr0b_f1 : 3;5 unsigned ka0c05_tiop$v_tlrmr0b_badr : 20;2 un 3signed ka0c05_tiop$v_tlrmr0b_f2 : 2;5 unsigned ka0c05_tiop$v_tlrmr0b_nvram : 1;5 unsigned ka0c05_tiop$v_tlrmr0b_valid : 1;) } ka0c05_tiop$r_tlrmr0b_bits;( } ka0c05_tiop$r_tlrmr0b_overlay;+ unsigned char ka0c05_tiop$b_f1650 [60]; __union {+ unsigned int ka0c05_tiop$l_tlrmr1a; __struct {4 unsigned ka0c05_tiop$v_tlrmr1a_mask : 4;6 unsigned ka0c05_tiop$v_tlrmr1a_ilv_en : 1;2 unsigned ka0c05_ti 3op$v_tlrmr1a_f1 : 3;5 unsigned ka0c05_tiop$v_tlrmr1a_badr : 20;2 unsigned ka0c05_tiop$v_tlrmr1a_f2 : 2;5 unsigned ka0c05_tiop$v_tlrmr1a_nvram : 1;5 unsigned ka0c05_tiop$v_tlrmr1a_valid : 1;) } ka0c05_tiop$r_tlrmr1a_bits;( } ka0c05_tiop$r_tlrmr1a_overlay;+ unsigned char ka0c05_tiop$b_f1660 [60]; __union {+ unsigned int ka0c05_tiop$l_tlrmr1b; __struct {4 unsigned ka0c05_tiop$v_tlrmr1b_mask 3: 4;6 unsigned ka0c05_tiop$v_tlrmr1b_ilv_en : 1;2 unsigned ka0c05_tiop$v_tlrmr1b_f1 : 3;5 unsigned ka0c05_tiop$v_tlrmr1b_badr : 20;2 unsigned ka0c05_tiop$v_tlrmr1b_f2 : 2;5 unsigned ka0c05_tiop$v_tlrmr1b_nvram : 1;5 unsigned ka0c05_tiop$v_tlrmr1b_valid : 1;) } ka0c05_tiop$r_tlrmr1b_bits;( } ka0c05_tiop$r_tlrmr1b_overlay;, unsigned char ka0c05_tiop$b_f1670 [316]; __union {+ unsigned int ka0 3c05_tiop$l_tlicmsr; __struct {7 unsigned ka0c05_tiop$v_tlicmsr_arb_ctl : 2;7 unsigned ka0c05_tiop$v_tlicmsr_sup_ctl : 2;9 unsigned ka0c05_tiop$v_tlicmsr_force_ack : 1;5 unsigned ka0c05_tiop$v_tlicmsr_rmnxm : 1;8 unsigned ka0c05_tiop$v_tlicmsr_ack_dsbl : 1;3 unsigned ka0c05_tiop$v_tlicmsr_f1 : 25;) } ka0c05_tiop$r_tlicmsr_bits;( } ka0c05_tiop$r_tlicmsr_overlay;+ unsigned char ka0c05_tiop$b_ 3f1700 [60]; __union {+ unsigned int ka0c05_tiop$l_tlicnse; __struct {2 unsigned ka0c05_tiop$v_tlicnse_f1 : 2;8 unsigned ka0c05_tiop$v_tlicnse_ack_drop : 1;5 unsigned ka0c05_tiop$v_tlicnse_rmnxm : 1;8 unsigned ka0c05_tiop$v_tlicnse_mbx_stat : 4;4 unsigned ka0c05_tiop$v_tlicnse_oflo : 4;5 unsigned ka0c05_tiop$v_tlicnse_pkt_e : 4;5 unsigned ka0c05_tiop$v_tlicnse_par_e : 4;9 unsign 3ed ka0c05_tiop$v_tlicnse_up_hdp_ie : 2;5 unsigned ka0c05_tiop$v_tlicnse_int_e : 1;9 unsigned ka0c05_tiop$v_tlicnse_dn_vrtx_e : 2;9 unsigned ka0c05_tiop$v_tlicnse_up_vrtx_e : 2;2 unsigned ka0c05_tiop$v_tlicnse_ie : 1;6 unsigned ka0c05_tiop$v_tlicnse_bus_pe : 1;8 unsigned ka0c05_tiop$v_tlicnse_wnd_oflo : 1;7 unsigned ka0c05_tiop$v_tlicnse_rm_oflo : 1;8 unsigned ka0c05_tiop$v_tlicnse_int_nses : 1;) 3 } ka0c05_tiop$r_tlicnse_bits;( } ka0c05_tiop$r_tlicnse_overlay;+ unsigned char ka0c05_tiop$b_f1710 [60]; __union {* unsigned int ka0c05_tiop$l_tlicdr; __struct {5 unsigned ka0c05_tiop$v_tlicdr_idp_pe : 1;2 unsigned ka0c05_tiop$v_tlicdr_dse : 1;2 unsigned ka0c05_tiop$v_tlicdr_dto : 1;6 unsigned ka0c05_tiop$v_tlicdr_dis_cmd : 1;6 unsigned ka0c05_tiop$v_tlicdr_dis_flt : 1;5 unsigned ka0c0 35_tiop$v_tlicdr_cmd_pe : 1;6 unsigned ka0c05_tiop$v_tlicdr_bnk_bsy : 1;1 unsigned ka0c05_tiop$v_tlicdr_f1 : 1;9 unsigned ka0c05_tiop$v_tlicdr_idp_cmd_pe : 1;2 unsigned ka0c05_tiop$v_tlicdr_f2 : 22;5 unsigned ka0c05_tiop$v_tlicdr_en_hid : 1;( } ka0c05_tiop$r_tlicdr_bits;' } ka0c05_tiop$r_tlicdr_overlay;+ unsigned char ka0c05_tiop$b_f1720 [60]; __union {+ unsigned int ka0c05_tiop$l_tlicmtr; 3__struct {7 unsigned ka0c05_tiop$v_tlicmtr_mbx_tip : 4;3 unsigned ka0c05_tiop$v_tlicmtr_f1 : 28;) } ka0c05_tiop$r_tlicmtr_bits;( } ka0c05_tiop$r_tlicmtr_overlay;+ unsigned char ka0c05_tiop$b_f1730 [60]; __union {+ unsigned int ka0c05_tiop$l_tlicwrt; __struct {3 unsigned ka0c05_tiop$v_tlicwrt_wip : 4;3 unsigned ka0c05_tiop$v_tlicwrt_f1 : 28;) } ka0c05_tiop$r_tlicwrt_bits;( } ka 30c05_tiop$r_tlicwrt_overlay;+ unsigned char ka0c05_tiop$b_f1740 [60]; __union {- unsigned int ka0c05_tiop$l_tlidpnse1; __struct {4 unsigned ka0c05_tiop$v_tlidpnse_err : 1;4 unsigned ka0c05_tiop$v_tlidpnse_pok : 1;6 unsigned ka0c05_tiop$v_tlidpnse_cblok : 1;9 unsigned ka0c05_tiop$v_tlidpnse_pok_tran : 1;9 unsigned ka0c05_tiop$v_tlidpnse_soft_err : 1;4 unsigned ka0c05_tiop$v_tlidpnse_f1 : 17;9 3 unsigned ka0c05_tiop$v_tlidpnse_rm_m_err : 2;4 unsigned ka0c05_tiop$v_tlidpnse_cpe : 1;9 unsigned ka0c05_tiop$v_tlidpnse_up_v_err : 2;3 unsigned ka0c05_tiop$v_tlidpnse_ie : 1;3 unsigned ka0c05_tiop$v_tlidpnse_pe : 1;3 unsigned ka0c05_tiop$v_tlidpnse_f2 : 2;6 unsigned ka0c05_tiop$v_tlidpnse_reset : 1;* } ka0c05_tiop$r_tlidpnse_bits;* } ka0c05_tiop$r_tlidpnse1_overlay;+ unsigned char ka0c05_tiop$b_3f1750 [60]; __union {, unsigned int ka0c05_tiop$l_tlidpdr1;) } ka0c05_tiop$r_tlidpdr1_overlay;, unsigned char ka0c05_tiop$b_f1760 [188]; __union {- unsigned int ka0c05_tiop$l_tlidpnse2;* } ka0c05_tiop$r_tlidpnse2_overlay;+ unsigned char ka0c05_tiop$b_f1770 [60]; __union {, unsigned int ka0c05_tiop$l_tlidpdr2;) } ka0c05_tiop$r_tlidpdr2_overlay;, unsigned char ka0c05_tiop$b_f1780 [188]; __union {- unsigned i 3nt ka0c05_tiop$l_tlidpnse3;* } ka0c05_tiop$r_tlidpnse3_overlay;+ unsigned char ka0c05_tiop$b_f1790 [60]; __union {, unsigned int ka0c05_tiop$l_tlidpdr3;) } ka0c05_tiop$r_tlidpdr3_overlay;- unsigned char ka0c05_tiop$b_f1800 [1724]; __union {- unsigned int ka0c05_tiop$l_tlidpnse0;* } ka0c05_tiop$r_tlidpnse0_overlay;+ unsigned char ka0c05_tiop$b_f1810 [60]; __union {, unsigned int ka0c05_tiop$l_tlidpdr0;) } ka0c05!3_tiop$r_tlidpdr0_overlay;+ unsigned char ka0c05_tiop$b_f1820 [60]; __union {, unsigned int ka0c05_tiop$l_tlipmask; __struct {5 unsigned ka0c05_tiop$v_tlipmask_cpu : 16;4 unsigned ka0c05_tiop$v_tlipmask_f1 : 16;* } ka0c05_tiop$r_tlipmask_bits;) } ka0c05_tiop$r_tlipmask_overlay;. unsigned char ka0c05_tiop$b_fill830 [124]; __union {+ unsigned int ka0c05_tiop$l_tlidpvr; __struct {7 unsign "3ed ka0c05_tiop$v_tlidpvr_vector : 16;3 unsigned ka0c05_tiop$v_tlidpvr_f1 : 16;) } ka0c05_tiop$r_tlidpvr_bits;( } ka0c05_tiop$r_tlidpvr_overlay;+ unsigned char ka0c05_tiop$b_f1840 [60]; __union {, unsigned int ka0c05_tiop$l_tlidpmsr;) } ka0c05_tiop$r_tlidpmsr_overlay;+ unsigned char ka0c05_tiop$b_f1850 [60]; __union {) unsigned int ka0c05_tiop$l_tlibr; __struct {6 unsigned ka0c05_tiop$v_tlibr_rcv_s #3dat : 1;6 unsigned ka0c05_tiop$v_tlibr_xmt_sdat : 1;2 unsigned ka0c05_tiop$v_tlibr_sclk : 1;1 unsigned ka0c05_tiop$v_tlibr_f1 : 29;' } ka0c05_tiop$r_tlibr_bits;& } ka0c05_tiop$r_tlibr_overlay;- unsigned char ka0c05_tiop$b_f1860 [5180]; } KA0C05_TIOP; #if !defined(__VAXC)K#define ka0c05_tiop$l_tldev ka0c05_tiop$r_tldev_overlay.ka0c05_tiop$l_tldevp#define ka0c05_tiop$v_tldev_dtype ka0c05_tiop$r_tldev_overlay.ka0c05_tiop$r_tldev_$3bits.ka0c05_tiop$v_tldev_dtypep#define ka0c05_tiop$v_tldev_swrev ka0c05_tiop$r_tldev_overlay.ka0c05_tiop$r_tldev_bits.ka0c05_tiop$v_tldev_swrevp#define ka0c05_tiop$v_tldev_hwrev ka0c05_tiop$r_tldev_overlay.ka0c05_tiop$r_tldev_bits.ka0c05_tiop$v_tldev_hwrevK#define ka0c05_tiop$l_tlber ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$l_tlbern#define ka0c05_tiop$v_tlber_atce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_atcel#define ka0c05_tiop$v_tlber_ape ka0c05_tiop$r_tlber_over%3lay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_apel#define ka0c05_tiop$v_tlber_bbe ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_bben#define ka0c05_tiop$v_tlber_lkto ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_lktol#define ka0c05_tiop$v_tlber_nae ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_naen#define ka0c05_tiop$v_tlber_rtce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_rtcer#define &3ka0c05_tiop$v_tlber_acktce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_acktcen#define ka0c05_tiop$v_tlber_mmre ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_mmren#define ka0c05_tiop$v_tlber_fnae ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_fnaep#define ka0c05_tiop$v_tlber_reqde ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_reqden#define ka0c05_tiop$v_tlber_atde ka0c05_tiop$r_tlber_overlay'3.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_atdel#define ka0c05_tiop$v_tlber_ude ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_uden#define ka0c05_tiop$v_tlber_cwde ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_cwden#define ka0c05_tiop$v_tlber_crde ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_crdel#define ka0c05_tiop$v_tlber_ds0 ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_ds0l#define ka(30c05_tiop$v_tlber_ds1 ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_ds1l#define ka0c05_tiop$v_tlber_ds2 ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_ds2l#define ka0c05_tiop$v_tlber_ds3 ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_ds3n#define ka0c05_tiop$v_tlber_dtde ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_dtdep#define ka0c05_tiop$v_tlber_fdtce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$)3r_tlber_bits.ka0c05_tiop$v_tlber_fdtcep#define ka0c05_tiop$v_tlber_uacke ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_uackep#define ka0c05_tiop$v_tlber_abtce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_abtcep#define ka0c05_tiop$v_tlber_dctce ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_dctcen#define ka0c05_tiop$v_tlber_seqe ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_seqel#define ka0c*305_tiop$v_tlber_dse ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_dsel#define ka0c05_tiop$v_tlber_dto ka0c05_tiop$r_tlber_overlay.ka0c05_tiop$r_tlber_bits.ka0c05_tiop$v_tlber_dtoK#define ka0c05_tiop$l_tlcnr ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$l_tlcnrn#define ka0c05_tiop$v_tlcnr_cwdd ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_cwddn#define ka0c05_tiop$v_tlcnr_crdd ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_cr+3ddp#define ka0c05_tiop$v_tlcnr_lktod ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_lktodn#define ka0c05_tiop$v_tlcnr_dtod ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_dtodt#define ka0c05_tiop$v_tlcnr_node_id ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_node_idn#define ka0c05_tiop$v_tlcnr_vcnt ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_vcntp#define ka0c05_tiop$v_tlcnr_stf_a ka0c05_tiop$,3r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_ap#define ka0c05_tiop$v_tlcnr_stf_b ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_bp#define ka0c05_tiop$v_tlcnr_stf_c ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_cp#define ka0c05_tiop$v_tlcnr_stf_d ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_dp#define ka0c05_tiop$v_tlcnr_stf_e ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_ti-3op$v_tlcnr_stf_ep#define ka0c05_tiop$v_tlcnr_stf_f ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_fp#define ka0c05_tiop$v_tlcnr_stf_g ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_gp#define ka0c05_tiop$v_tlcnr_stf_h ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_stf_hr#define ka0c05_tiop$v_tlcnr_halt_a ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_ar#define ka0c05_tiop$v_tlcnr_ha.3lt_b ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_br#define ka0c05_tiop$v_tlcnr_halt_c ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_cr#define ka0c05_tiop$v_tlcnr_halt_d ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_dr#define ka0c05_tiop$v_tlcnr_halt_e ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_er#define ka0c05_tiop$v_tlcnr_halt_f ka0c05_tiop$r_tlcnr_overlay.ka0c05_ti/3op$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_fr#define ka0c05_tiop$v_tlcnr_halt_g ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_gr#define ka0c05_tiop$v_tlcnr_halt_h ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_halt_ht#define ka0c05_tiop$v_tlcnr_rststat ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_rststatn#define ka0c05_tiop$v_tlcnr_nrst ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_nrstn03#define ka0c05_tiop$v_tlcnr_lofe ka0c05_tiop$r_tlcnr_overlay.ka0c05_tiop$r_tlcnr_bits.ka0c05_tiop$v_tlcnr_lofeN#define ka0c05_tiop$l_tlmmr0 ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$l_tlmmr0x#define ka0c05_tiop$v_tlmmr0_intmask ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_intmaskx#define ka0c05_tiop$v_tlmmr0_adrmask ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_adrmaskt#define ka0c05_tiop$v_tlmmr0_intlv ka0c05_tiop$r_tlmmr0_overlay.ka0c0513_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_intlvt#define ka0c05_tiop$v_tlmmr0_sbank ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_sbankx#define ka0c05_tiop$v_tlmmr0_address ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_addresst#define ka0c05_tiop$v_tlmmr0_valid ka0c05_tiop$r_tlmmr0_overlay.ka0c05_tiop$r_tlmmr0_bits.ka0c05_tiop$v_tlmmr0_validN#define ka0c05_tiop$l_tlmmr1 ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$l_tlmmr1x#define ka0c05_tiop$23v_tlmmr1_intmask ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_intmaskx#define ka0c05_tiop$v_tlmmr1_adrmask ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_adrmaskt#define ka0c05_tiop$v_tlmmr1_intlv ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_intlvt#define ka0c05_tiop$v_tlmmr1_sbank ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_sbankx#define ka0c05_tiop$v_tlmmr1_address ka0c05_ti33op$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_addresst#define ka0c05_tiop$v_tlmmr1_valid ka0c05_tiop$r_tlmmr1_overlay.ka0c05_tiop$r_tlmmr1_bits.ka0c05_tiop$v_tlmmr1_validN#define ka0c05_tiop$l_tlmmr2 ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$l_tlmmr2x#define ka0c05_tiop$v_tlmmr2_intmask ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmmr2_intmaskx#define ka0c05_tiop$v_tlmmr2_adrmask ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmm43r2_adrmaskt#define ka0c05_tiop$v_tlmmr2_intlv ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmmr2_intlvt#define ka0c05_tiop$v_tlmmr2_sbank ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmmr2_sbankx#define ka0c05_tiop$v_tlmmr2_address ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmmr2_addresst#define ka0c05_tiop$v_tlmmr2_valid ka0c05_tiop$r_tlmmr2_overlay.ka0c05_tiop$r_tlmmr2_bits.ka0c05_tiop$v_tlmmr2_validN#define ka0c05_tio53p$l_tlmmr3 ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$l_tlmmr3x#define ka0c05_tiop$v_tlmmr3_intmask ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmmr3_bits.ka0c05_tiop$v_tlmmr3_intmaskx#define ka0c05_tiop$v_tlmmr3_adrmask ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmmr3_bits.ka0c05_tiop$v_tlmmr3_adrmaskt#define ka0c05_tiop$v_tlmmr3_intlv ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmmr3_bits.ka0c05_tiop$v_tlmmr3_intlvt#define ka0c05_tiop$v_tlmmr3_sbank ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmm63r3_bits.ka0c05_tiop$v_tlmmr3_sbankx#define ka0c05_tiop$v_tlmmr3_address ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmmr3_bits.ka0c05_tiop$v_tlmmr3_addresst#define ka0c05_tiop$v_tlmmr3_valid ka0c05_tiop$r_tlmmr3_overlay.ka0c05_tiop$r_tlmmr3_bits.ka0c05_tiop$v_tlmmr3_validN#define ka0c05_tiop$l_tlmmr4 ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$l_tlmmr4x#define ka0c05_tiop$v_tlmmr4_intmask ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_intmaskx#define ka0c05_tiop$v_tlmmr473_adrmask ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_adrmaskt#define ka0c05_tiop$v_tlmmr4_intlv ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_intlvt#define ka0c05_tiop$v_tlmmr4_sbank ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_sbankx#define ka0c05_tiop$v_tlmmr4_address ka0c05_tiop$r_tlmmr4_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_addresst#define ka0c05_tiop$v_tlmmr4_valid ka0c05_tiop$r_tlmmr834_overlay.ka0c05_tiop$r_tlmmr4_bits.ka0c05_tiop$v_tlmmr4_validN#define ka0c05_tiop$l_tlmmr5 ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$l_tlmmr5x#define ka0c05_tiop$v_tlmmr5_intmask ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_intmaskx#define ka0c05_tiop$v_tlmmr5_adrmask ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_adrmaskt#define ka0c05_tiop$v_tlmmr5_intlv ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_intlvt93#define ka0c05_tiop$v_tlmmr5_sbank ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_sbankx#define ka0c05_tiop$v_tlmmr5_address ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_addresst#define ka0c05_tiop$v_tlmmr5_valid ka0c05_tiop$r_tlmmr5_overlay.ka0c05_tiop$r_tlmmr5_bits.ka0c05_tiop$v_tlmmr5_validN#define ka0c05_tiop$l_tlmmr6 ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$l_tlmmr6x#define ka0c05_tiop$v_tlmmr6_intmask ka0c05_tiop$r_tlmmr6_overlay.ka:30c05_tiop$r_tlmmr6_bits.ka0c05_tiop$v_tlmmr6_intmaskx#define ka0c05_tiop$v_tlmmr6_adrmask ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$r_tlmmr6_bits.ka0c05_tiop$v_tlmmr6_adrmaskt#define ka0c05_tiop$v_tlmmr6_intlv ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$r_tlmmr6_bits.ka0c05_tiop$v_tlmmr6_intlvt#define ka0c05_tiop$v_tlmmr6_sbank ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$r_tlmmr6_bits.ka0c05_tiop$v_tlmmr6_sbankx#define ka0c05_tiop$v_tlmmr6_address ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$r_tlmmr6_bits.ka;30c05_tiop$v_tlmmr6_addresst#define ka0c05_tiop$v_tlmmr6_valid ka0c05_tiop$r_tlmmr6_overlay.ka0c05_tiop$r_tlmmr6_bits.ka0c05_tiop$v_tlmmr6_validN#define ka0c05_tiop$l_tlmmr7 ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$l_tlmmr7x#define ka0c05_tiop$v_tlmmr7_intmask ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_intmaskx#define ka0c05_tiop$v_tlmmr7_adrmask ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_adrmaskt#define ka0c05_tiop$v_tlmmr7_intlv k<3a0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_intlvt#define ka0c05_tiop$v_tlmmr7_sbank ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_sbankx#define ka0c05_tiop$v_tlmmr7_address ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_addresst#define ka0c05_tiop$v_tlmmr7_valid ka0c05_tiop$r_tlmmr7_overlay.ka0c05_tiop$r_tlmmr7_bits.ka0c05_tiop$v_tlmmr7_validQ#define ka0c05_tiop$l_tlfadr0 ka0c05_tiop$r_tlfadr0_overlay.ka0c05=3_tiop$l_tlfadr0v#define ka0c05_tiop$v_tlfadr0_fadr ka0c05_tiop$r_tlfadr0_overlay.ka0c05_tiop$r_tlfadr0_bits.ka0c05_tiop$v_tlfadr0_fadrQ#define ka0c05_tiop$l_tlfadr1 ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$l_tlfadr1v#define ka0c05_tiop$v_tlfadr1_fadr ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_fadrv#define ka0c05_tiop$v_tlfadr1_fcmd ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_fcmdx#define ka0c05_tiop$v_tlfadr1_fbank ka0c05_t>3iop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_fbankv#define ka0c05_tiop$v_tlfadr1_adrv ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_adrvv#define ka0c05_tiop$v_tlfadr1_cmdv ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_cmdvx#define ka0c05_tiop$v_tlfadr1_bankv ka0c05_tiop$r_tlfadr1_overlay.ka0c05_tiop$r_tlfadr1_bits.ka0c05_tiop$v_tlfadr1_bankvN#define ka0c05_tiop$l_tlesr0 ka0c05_tiop$r_tlesr0_overlay.ka0c05_t?3iop$l_tlesr0t#define ka0c05_tiop$v_tlesr0_synd0 ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_synd0t#define ka0c05_tiop$v_tlesr0_synd1 ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_synd1p#define ka0c05_tiop$v_tlesr0_tde ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_tdep#define ka0c05_tiop$v_tlesr0_tce ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_tcet#define ka0c05_tiop$v_tlesr0@3_dvtce ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_dvtcer#define ka0c05_tiop$v_tlesr0_uecc ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_uecct#define ka0c05_tiop$v_tlesr0_cwecc ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_cwecct#define ka0c05_tiop$v_tlesr0_crecc ka0c05_tiop$r_tlesr0_overlay.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_creccv#define ka0c05_tiop$v_tlesr0_lofsyn ka0c05_tiop$r_tlesr0_overlayA3.ka0c05_tiop$r_tlesr0_bits.ka0c05_tiop$v_tlesr0_lofsynN#define ka0c05_tiop$l_tlesr1 ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$l_tlesr1t#define ka0c05_tiop$v_tlesr1_synd0 ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_synd0t#define ka0c05_tiop$v_tlesr1_synd1 ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_synd1p#define ka0c05_tiop$v_tlesr1_tde ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_tdep#define ka0c05_tiop$B3v_tlesr1_tce ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_tcet#define ka0c05_tiop$v_tlesr1_dvtce ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_dvtcer#define ka0c05_tiop$v_tlesr1_uecc ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_uecct#define ka0c05_tiop$v_tlesr1_cwecc ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_cwecct#define ka0c05_tiop$v_tlesr1_crecc ka0c05_tiop$r_tlesr1_overC3lay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_creccv#define ka0c05_tiop$v_tlesr1_lofsyn ka0c05_tiop$r_tlesr1_overlay.ka0c05_tiop$r_tlesr1_bits.ka0c05_tiop$v_tlesr1_lofsynN#define ka0c05_tiop$l_tlesr2 ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$l_tlesr2t#define ka0c05_tiop$v_tlesr2_synd0 ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_synd0t#define ka0c05_tiop$v_tlesr2_synd1 ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_synd1p#define ka0cD305_tiop$v_tlesr2_tde ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_tdep#define ka0c05_tiop$v_tlesr2_tce ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_tcet#define ka0c05_tiop$v_tlesr2_dvtce ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_dvtcer#define ka0c05_tiop$v_tlesr2_uecc ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_uecct#define ka0c05_tiop$v_tlesr2_cwecc ka0c05_tiop$r_tlesr2_E3overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_cwecct#define ka0c05_tiop$v_tlesr2_crecc ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_creccv#define ka0c05_tiop$v_tlesr2_lofsyn ka0c05_tiop$r_tlesr2_overlay.ka0c05_tiop$r_tlesr2_bits.ka0c05_tiop$v_tlesr2_lofsynN#define ka0c05_tiop$l_tlesr3 ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$l_tlesr3t#define ka0c05_tiop$v_tlesr3_synd0 ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_synd0t#define F3ka0c05_tiop$v_tlesr3_synd1 ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_synd1p#define ka0c05_tiop$v_tlesr3_tde ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_tdep#define ka0c05_tiop$v_tlesr3_tce ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_tcet#define ka0c05_tiop$v_tlesr3_dvtce ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_dvtcer#define ka0c05_tiop$v_tlesr3_uecc ka0c05_tiop$r_tlG3esr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_uecct#define ka0c05_tiop$v_tlesr3_cwecc ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_cwecct#define ka0c05_tiop$v_tlesr3_crecc ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_creccv#define ka0c05_tiop$v_tlesr3_lofsyn ka0c05_tiop$r_tlesr3_overlay.ka0c05_tiop$r_tlesr3_bits.ka0c05_tiop$v_tlesr3_lofsynQ#define ka0c05_tiop$l_tlilid0 ka0c05_tiop$r_tlilid0_overlay.ka0c05_tiop$l_tlilid0xH3#define ka0c05_tiop$v_tlilid0_ident ka0c05_tiop$r_tlilid0_overlay.ka0c05_tiop$r_tlilid0_bits.ka0c05_tiop$v_tlilid0_identQ#define ka0c05_tiop$l_tlilid1 ka0c05_tiop$r_tlilid1_overlay.ka0c05_tiop$l_tlilid1x#define ka0c05_tiop$v_tlilid1_ident ka0c05_tiop$r_tlilid1_overlay.ka0c05_tiop$r_tlilid1_bits.ka0c05_tiop$v_tlilid1_identQ#define ka0c05_tiop$l_tlilid2 ka0c05_tiop$r_tlilid2_overlay.ka0c05_tiop$l_tlilid2x#define ka0c05_tiop$v_tlilid2_ident ka0c05_tiop$r_tlilid2_overlay.ka0c05_tiop$r_tlilid2_bits.kI3a0c05_tiop$v_tlilid2_identQ#define ka0c05_tiop$l_tlilid3 ka0c05_tiop$r_tlilid3_overlay.ka0c05_tiop$l_tlilid3x#define ka0c05_tiop$v_tlilid3_ident ka0c05_tiop$r_tlilid3_overlay.ka0c05_tiop$r_tlilid3_bits.ka0c05_tiop$v_tlilid3_identW#define ka0c05_tiop$l_tlcpumask ka0c05_tiop$r_tlcpumask_overlay.ka0c05_tiop$l_tlcpumask~#define ka0c05_tiop$v_tlcpumask_mask ka0c05_tiop$r_tlcpumask_overlay.ka0c05_tiop$r_tlcpumask_bits.ka0c05_tiop$v_tlcpumask_maskN#define ka0c05_tiop$q_tlmbpr ka0c05_tiop$r_tlmbpr_overJ3lay.ka0c05_tiop$q_tlmbprQ#define ka0c05_tiop$l_tlrmr0a ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$l_tlrmr0av#define ka0c05_tiop$v_tlrmr0a_mask ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$r_tlrmr0a_bits.ka0c05_tiop$v_tlrmr0a_maskz#define ka0c05_tiop$v_tlrmr0a_ilv_en ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$r_tlrmr0a_bits.ka0c05_tiop$v_tlrmr0a_ilv_env#define ka0c05_tiop$v_tlrmr0a_badr ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$r_tlrmr0a_bits.ka0c05_tiop$v_tlrmr0a_badrx#define ka0c05_tiop$v_tlrmr0a_nvK3ram ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$r_tlrmr0a_bits.ka0c05_tiop$v_tlrmr0a_nvramx#define ka0c05_tiop$v_tlrmr0a_valid ka0c05_tiop$r_tlrmr0a_overlay.ka0c05_tiop$r_tlrmr0a_bits.ka0c05_tiop$v_tlrmr0a_validQ#define ka0c05_tiop$l_tlrmr0b ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$l_tlrmr0bv#define ka0c05_tiop$v_tlrmr0b_mask ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$r_tlrmr0b_bits.ka0c05_tiop$v_tlrmr0b_maskz#define ka0c05_tiop$v_tlrmr0b_ilv_en ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$r_tlrmr0b_bL3its.ka0c05_tiop$v_tlrmr0b_ilv_env#define ka0c05_tiop$v_tlrmr0b_badr ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$r_tlrmr0b_bits.ka0c05_tiop$v_tlrmr0b_badrx#define ka0c05_tiop$v_tlrmr0b_nvram ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$r_tlrmr0b_bits.ka0c05_tiop$v_tlrmr0b_nvramx#define ka0c05_tiop$v_tlrmr0b_valid ka0c05_tiop$r_tlrmr0b_overlay.ka0c05_tiop$r_tlrmr0b_bits.ka0c05_tiop$v_tlrmr0b_validQ#define ka0c05_tiop$l_tlrmr1a ka0c05_tiop$r_tlrmr1a_overlay.ka0c05_tiop$l_tlrmr1av#define ka0c05_tiop$v_tlM3rmr1a_mask ka0c05_tiop$r_tlrmr1a_overlay.ka0c05_tiop$r_tlrmr1a_bits.ka0c05_tiop$v_tlrmr1a_maskz#define ka0c05_tiop$v_tlrmr1a_ilv_en ka0c05_tiop$r_tlrmr1a_overlay.ka0c05_tiop$r_tlrmr1a_bits.ka0c05_tiop$v_tlrmr1a_ilv_env#define ka0c05_tiop$v_tlrmr1a_badr ka0c05_tiop$r_tlrmr1a_overlay.ka0c05_tiop$r_tlrmr1a_bits.ka0c05_tiop$v_tlrmr1a_badrx#define ka0c05_tiop$v_tlrmr1a_nvram ka0c05_tiop$r_tlrmr1a_overlay.ka0c05_tiop$r_tlrmr1a_bits.ka0c05_tiop$v_tlrmr1a_nvramx#define ka0c05_tiop$v_tlrmr1a_valid ka0c05_tN3iop$r_tlrmr1a_overlay.ka0c05_tiop$r_tlrmr1a_bits.ka0c05_tiop$v_tlrmr1a_validQ#define ka0c05_tiop$l_tlrmr1b ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$l_tlrmr1bv#define ka0c05_tiop$v_tlrmr1b_mask ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$r_tlrmr1b_bits.ka0c05_tiop$v_tlrmr1b_maskz#define ka0c05_tiop$v_tlrmr1b_ilv_en ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$r_tlrmr1b_bits.ka0c05_tiop$v_tlrmr1b_ilv_env#define ka0c05_tiop$v_tlrmr1b_badr ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$r_tlrmr1b_bits.ka0c05_tO3iop$v_tlrmr1b_badrx#define ka0c05_tiop$v_tlrmr1b_nvram ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$r_tlrmr1b_bits.ka0c05_tiop$v_tlrmr1b_nvramx#define ka0c05_tiop$v_tlrmr1b_valid ka0c05_tiop$r_tlrmr1b_overlay.ka0c05_tiop$r_tlrmr1b_bits.ka0c05_tiop$v_tlrmr1b_validQ#define ka0c05_tiop$l_tlicmsr ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$l_tlicmsr|#define ka0c05_tiop$v_tlicmsr_arb_ctl ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$r_tlicmsr_bits.ka0c05_tiop$v_tlicmsr_arb_ctl|#define ka0c05_tiop$v_tlicmsr_suP3p_ctl ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$r_tlicmsr_bits.ka0c05_tiop$v_tlicmsr_sup_ctl#define ka0c05_tiop$v_tlicmsr_force_ack ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$r_tlicmsr_bits.ka0c05_tiop$v_tlicmsr_force_ackx#define ka0c05_tiop$v_tlicmsr_rmnxm ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$r_tlicmsr_bits.ka0c05_tiop$v_tlicmsr_rmnxm~#define ka0c05_tiop$v_tlicmsr_ack_dsbl ka0c05_tiop$r_tlicmsr_overlay.ka0c05_tiop$r_tlicmsr_bits.ka0c05_tiop$v_tlicmsr_ack_dsblQ#define ka0c05_tiop$l_tlicnse kaQ30c05_tiop$r_tlicnse_overlay.ka0c05_tiop$l_tlicnse~#define ka0c05_tiop$v_tlicnse_ack_drop ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_ack_dropx#define ka0c05_tiop$v_tlicnse_rmnxm ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_rmnxm~#define ka0c05_tiop$v_tlicnse_mbx_stat ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_mbx_statv#define ka0c05_tiop$v_tlicnse_oflo ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiopR3$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_oflox#define ka0c05_tiop$v_tlicnse_pkt_e ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_pkt_ex#define ka0c05_tiop$v_tlicnse_par_e ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_par_e#define ka0c05_tiop$v_tlicnse_up_hdp_ie ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_up_hdp_iex#define ka0c05_tiop$v_tlicnse_int_e ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_S3bits.ka0c05_tiop$v_tlicnse_int_e#define ka0c05_tiop$v_tlicnse_dn_vrtx_e ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_dn_vrtx_e#define ka0c05_tiop$v_tlicnse_up_vrtx_e ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_up_vrtx_er#define ka0c05_tiop$v_tlicnse_ie ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_iez#define ka0c05_tiop$v_tlicnse_bus_pe ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.kaT30c05_tiop$v_tlicnse_bus_pe~#define ka0c05_tiop$v_tlicnse_wnd_oflo ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_wnd_oflo|#define ka0c05_tiop$v_tlicnse_rm_oflo ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_rm_oflo~#define ka0c05_tiop$v_tlicnse_int_nses ka0c05_tiop$r_tlicnse_overlay.ka0c05_tiop$r_tlicnse_bits.ka0c05_tiop$v_tlicnse_int_nsesN#define ka0c05_tiop$l_tlicdr ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$l_tlicdrv#define ka0c05_tU3iop$v_tlicdr_idp_pe ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_idp_pep#define ka0c05_tiop$v_tlicdr_dse ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_dsep#define ka0c05_tiop$v_tlicdr_dto ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_dtox#define ka0c05_tiop$v_tlicdr_dis_cmd ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_dis_cmdx#define ka0c05_tiop$v_tlicdr_dis_flt ka0c05_tiop$r_tV3licdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_dis_fltv#define ka0c05_tiop$v_tlicdr_cmd_pe ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_cmd_pex#define ka0c05_tiop$v_tlicdr_bnk_bsy ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_bnk_bsy~#define ka0c05_tiop$v_tlicdr_idp_cmd_pe ka0c05_tiop$r_tlicdr_overlay.ka0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_idp_cmd_pev#define ka0c05_tiop$v_tlicdr_en_hid ka0c05_tiop$r_tlicdr_overlay.kW3a0c05_tiop$r_tlicdr_bits.ka0c05_tiop$v_tlicdr_en_hidQ#define ka0c05_tiop$l_tlicmtr ka0c05_tiop$r_tlicmtr_overlay.ka0c05_tiop$l_tlicmtr|#define ka0c05_tiop$v_tlicmtr_mbx_tip ka0c05_tiop$r_tlicmtr_overlay.ka0c05_tiop$r_tlicmtr_bits.ka0c05_tiop$v_tlicmtr_mbx_tipQ#define ka0c05_tiop$l_tlicwrt ka0c05_tiop$r_tlicwrt_overlay.ka0c05_tiop$l_tlicwrtt#define ka0c05_tiop$v_tlicwrt_wip ka0c05_tiop$r_tlicwrt_overlay.ka0c05_tiop$r_tlicwrt_bits.ka0c05_tiop$v_tlicwrt_wipW#define ka0c05_tiop$l_tlidpnse1 ka0c05_tX3iop$r_tlidpnse1_overlay.ka0c05_tiop$l_tlidpnse1y#define ka0c05_tiop$v_tlidpnse_err ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_erry#define ka0c05_tiop$v_tlidpnse_pok ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_pok}#define ka0c05_tiop$v_tlidpnse_cblok ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_cblok#define ka0c05_tiop$v_tlidpnse_pok_tran ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tY3iop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_pok_tran#define ka0c05_tiop$v_tlidpnse_soft_err ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_soft_err#define ka0c05_tiop$v_tlidpnse_rm_m_err ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_rm_m_erry#define ka0c05_tiop$v_tlidpnse_cpe ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_cpe#define ka0c05_tiop$v_tlidpnse_up_v_err ka0c05_tiop$r_tlidpnZ3se1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_up_v_errw#define ka0c05_tiop$v_tlidpnse_ie ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_iew#define ka0c05_tiop$v_tlidpnse_pe ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_pe}#define ka0c05_tiop$v_tlidpnse_reset ka0c05_tiop$r_tlidpnse1_overlay.ka0c05_tiop$r_tlidpnse_bits.ka0c05_tiop$v_tlidpnse_resetT#define ka0c05_tiop$l_tlidpdr1 ka0c05_tiop$r_tlidpdr1_overla[3y.ka0c05_tiop$l_tlidpdr1W#define ka0c05_tiop$l_tlidpnse2 ka0c05_tiop$r_tlidpnse2_overlay.ka0c05_tiop$l_tlidpnse2T#define ka0c05_tiop$l_tlidpdr2 ka0c05_tiop$r_tlidpdr2_overlay.ka0c05_tiop$l_tlidpdr2W#define ka0c05_tiop$l_tlidpnse3 ka0c05_tiop$r_tlidpnse3_overlay.ka0c05_tiop$l_tlidpnse3T#define ka0c05_tiop$l_tlidpdr3 ka0c05_tiop$r_tlidpdr3_overlay.ka0c05_tiop$l_tlidpdr3W#define ka0c05_tiop$l_tlidpnse0 ka0c05_tiop$r_tlidpnse0_overlay.ka0c05_tiop$l_tlidpnse0T#define ka0c05_tiop$l_tlidpdr0 ka0c05_\3tiop$r_tlidpdr0_overlay.ka0c05_tiop$l_tlidpdr0T#define ka0c05_tiop$l_tlipmask ka0c05_tiop$r_tlipmask_overlay.ka0c05_tiop$l_tlipmaskx#define ka0c05_tiop$v_tlipmask_cpu ka0c05_tiop$r_tlipmask_overlay.ka0c05_tiop$r_tlipmask_bits.ka0c05_tiop$v_tlipmask_cpuQ#define ka0c05_tiop$l_tlidpvr ka0c05_tiop$r_tlidpvr_overlay.ka0c05_tiop$l_tlidpvrz#define ka0c05_tiop$v_tlidpvr_vector ka0c05_tiop$r_tlidpvr_overlay.ka0c05_tiop$r_tlidpvr_bits.ka0c05_tiop$v_tlidpvr_vectorT#define ka0c05_tiop$l_tlidpmsr ka0c05_tiop]3$r_tlidpmsr_overlay.ka0c05_tiop$l_tlidpmsrK#define ka0c05_tiop$l_tlibr ka0c05_tiop$r_tlibr_overlay.ka0c05_tiop$l_tlibrv#define ka0c05_tiop$v_tlibr_rcv_sdat ka0c05_tiop$r_tlibr_overlay.ka0c05_tiop$r_tlibr_bits.ka0c05_tiop$v_tlibr_rcv_sdatv#define ka0c05_tiop$v_tlibr_xmt_sdat ka0c05_tiop$r_tlibr_overlay.ka0c05_tiop$r_tlibr_bits.ka0c05_tiop$v_tlibr_xmt_sdatn#define ka0c05_tiop$v_tlibr_sclk ka0c05_tiop$r_tlibr_overlay.ka0c05_tiop$r_tlibr_bits.ka0c05_tiop$v_tlibr_sclk"#endif /* #if !defined(__VAXC) ^3*/  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0c05_uart0b {#pragma __nomember_alignment __union {0 unsigned int ka0c05_uart0b$l_uart0b_rr0; __struct {8 unsigned ka0c05_uart0b$v_uart0b_rr0_f1 : 32;. } ka0c05_uart0b$r_uart0b_rr0_bits;- } ka0c05_uart0b$r_uart0b_rr0_overlay; _3- unsigned char ka0c05_uart0b$b_f2000 [60]; __union {0 unsigned int ka0c05_uart0b$l_uart0b_rr8; __struct {8 unsigned ka0c05_uart0b$v_uart0b_rr8_f1 : 32;. } ka0c05_uart0b$r_uart0b_rr8_bits;- } ka0c05_uart0b$r_uart0b_rr8_overlay;- unsigned char ka0c05_uart0b$b_f2010 [60]; __union {0 unsigned int ka0c05_uart0b$l_uart0a_rr0; __struct {8 unsigned ka0c05_uart0b$v_uart0a_rr0_f1 : 32;. } ka0c05`3_uart0b$r_uart0a_rr0_bits;- } ka0c05_uart0b$r_uart0a_rr0_overlay;- unsigned char ka0c05_uart0b$b_f2020 [60]; __union {0 unsigned int ka0c05_uart0b$l_uart0a_rr8; __struct {8 unsigned ka0c05_uart0b$v_uart0a_rr8_f1 : 32;. } ka0c05_uart0b$r_uart0a_rr8_bits;- } ka0c05_uart0b$r_uart0a_rr8_overlay;/ unsigned char ka0c05_uart0b$b_f2030 [7996]; } KA0C05_UART0B; #if !defined(__VAXC)`#define ka0c05_uart0b$l_uart0b_rr0 ka0c05_ a3uart0b$r_uart0b_rr0_overlay.ka0c05_uart0b$l_uart0b_rr0`#define ka0c05_uart0b$l_uart0b_rr8 ka0c05_uart0b$r_uart0b_rr8_overlay.ka0c05_uart0b$l_uart0b_rr8`#define ka0c05_uart0b$l_uart0a_rr0 ka0c05_uart0b$r_uart0a_rr0_overlay.ka0c05_uart0b$l_uart0a_rr0`#define ka0c05_uart0b$l_uart0a_rr8 ka0c05_uart0b$r_uart0a_rr8_overlay.ka0c05_uart0b$l_uart0a_rr8"#endif /* #if !defined(__VAXC) */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __b3nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0c05_uart1b {#pragma __nomember_alignment __union { __union {4 unsigned int ka0c05_uart1b$l_uart1b_rr0; __struct {< unsigned ka0c05_uart1b$v_uart1b_rr0_f1 : 32;2 } ka0c05_uart1b$r_uart1b_rr0_bits;1 } ka0c05_uart1b$r_uart1b_rr0_overlay; __struct {4 unsigned int ka0c05_uart1b$l_uart1b_wr0;1 c3 } ka0c05_uart1b$r_uart1b_wr0_overlay;* } ka0c05_uart1b$r_uart1b0_overlay;- unsigned char ka0c05_uart1b$b_f2040 [60]; __union {0 unsigned int ka0c05_uart1b$l_uart1b_rr8; __struct {8 unsigned ka0c05_uart1b$v_uart1b_rr8_f1 : 32;. } ka0c05_uart1b$r_uart1b_rr8_bits;- } ka0c05_uart1b$r_uart1b_rr8_overlay;- unsigned char ka0c05_uart1b$b_f2050 [60]; __union {0 unsigned int ka0c05_uart1b$l_uart1a_rr0; __st d3ruct {8 unsigned ka0c05_uart1b$v_uart1a_rr0_f1 : 32;. } ka0c05_uart1b$r_uart1a_rr0_bits;- } ka0c05_uart1b$r_uart1a_rr0_overlay;- unsigned char ka0c05_uart1b$b_f2060 [60]; __union {0 unsigned int ka0c05_uart1b$l_uart1a_rr8; __struct {8 unsigned ka0c05_uart1b$v_uart1a_rr8_f1 : 32;. } ka0c05_uart1b$r_uart1a_rr8_bits;- } ka0c05_uart1b$r_uart1a_rr8_overlay;/ unsigned char ka0c05_uart1b$b_f2070 [7996]; e3 } KA0C05_UART1B; #if !defined(__VAXC)#define ka0c05_uart1b$l_uart1b_rr0 ka0c05_uart1b$r_uart1b0_overlay.ka0c05_uart1b$r_uart1b_rr0_overlay.ka0c05_uart1b$l_uart1b_rr0#define ka0c05_uart1b$l_uart1b_wr0 ka0c05_uart1b$r_uart1b0_overlay.ka0c05_uart1b$r_uart1b_wr0_overlay.ka0c05_uart1b$l_uart1b_wr0`#define ka0c05_uart1b$l_uart1b_rr8 ka0c05_uart1b$r_uart1b_rr8_overlay.ka0c05_uart1b$l_uart1b_rr8`#define ka0c05_uart1b$l_uart1a_rr0 ka0c05_uart1b$r_uart1a_rr0_overlay.ka0c05_uart1b$l_uart1a_rr0`#def f3ine ka0c05_uart1b$l_uart1a_rr8 ka0c05_uart1b$r_uart1a_rr8_overlay.ka0c05_uart1b$l_uart1a_rr8"#endif /* #if !defined(__VAXC) */ (#define KA0C05_WATCH$M_WATCH_CSRA_RS 0xF)#define KA0C05_WATCH$M_WATCH_CSRA_DV 0x70*#define KA0C05_WATCH$M_WATCH_CSRA_UIP 0x80)#define KA0C05_WATCH$M_WATCH_CSRB_DSE 0x1+#define KA0C05_WATCH$M_WATCH_CSRB_24_12 0x2(#define KA0C05_WATCH$M_WATCH_CSRB_DM 0x4*#define KA0C05_WATCH$M_WATCH_CSRB_SQWE 0x8*#define KA0C05_WATCH$M_WATCH_CSRB_UIE 0x10*#define KA0C05_WATCH$M g3_WATCH_CSRB_AIE 0x20*#define KA0C05_WATCH$M_WATCH_CSRB_PIE 0x40*#define KA0C05_WATCH$M_WATCH_CSRB_SET 0x80)#define KA0C05_WATCH$M_WATCH_CSRC_UF 0x10)#define KA0C05_WATCH$M_WATCH_CSRC_AF 0x20)#define KA0C05_WATCH$M_WATCH_CSRC_PF 0x40+#define KA0C05_WATCH$M_WATCH_CSRC_IRQF 0x80*#define KA0C05_WATCH$M_WATCH_CSRD_VRT 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomemberh3_alignment#endiftypedef struct _ka0c05_watch {#pragma __nomember_alignment __union {2 unsigned int ka0c05_watch$l_watch_seconds; __struct {: unsigned ka0c05_watch$v_watch_seconds_f1 : 32;0 } ka0c05_watch$r_watch_seconds_bits;- } ka0c05_watch$r_watch_seconds_overl;0 unsigned char ka0c05_watch$b_fill3000 [124]; __union {2 unsigned int ka0c05_watch$l_watch_minutes; __struct {: unsigned ka0c05_watch$v_ i3watch_minutes_f1 : 32;0 } ka0c05_watch$r_watch_minutes_bits;- } ka0c05_watch$r_watch_minutes_overl;0 unsigned char ka0c05_watch$b_fill3010 [124]; __union {0 unsigned int ka0c05_watch$l_watch_hours; __struct {8 unsigned ka0c05_watch$v_watch_hours_f1 : 32;. } ka0c05_watch$r_watch_hours_bits;- } ka0c05_watch$r_watch_hours_overlay;0 unsigned char ka0c05_watch$b_fill3020 [188]; __union {. unsigned int ka0c0 j35_watch$l_watch_dom; __struct {6 unsigned ka0c05_watch$v_watch_dom_f1 : 32;, } ka0c05_watch$r_watch_dom_bits;+ } ka0c05_watch$r_watch_dom_overlay;/ unsigned char ka0c05_watch$b_fill3030 [60]; __union {0 unsigned int ka0c05_watch$l_watch_month; __struct {8 unsigned ka0c05_watch$v_watch_month_f1 : 32;. } ka0c05_watch$r_watch_month_bits;- } ka0c05_watch$r_watch_month_overlay;/ unsigned char ka0c k305_watch$b_fill3040 [60]; __union {/ unsigned int ka0c05_watch$l_watch_year; __struct {7 unsigned ka0c05_watch$v_watch_year_f1 : 32;- } ka0c05_watch$r_watch_year_bits;, } ka0c05_watch$r_watch_year_overlay;/ unsigned char ka0c05_watch$b_fill3050 [60]; __union {/ unsigned int ka0c05_watch$l_watch_csra; __struct {6 unsigned ka0c05_watch$v_watch_csra_rs : 4;6 unsigned ka0c05_watch$v_watch_cs l3ra_dv : 3;7 unsigned ka0c05_watch$v_watch_csra_uip : 1;7 unsigned ka0c05_watch$v_watch_csra_f1 : 24;- } ka0c05_watch$r_watch_csra_bits;, } ka0c05_watch$r_watch_csra_overlay;/ unsigned char ka0c05_watch$b_fill3060 [60]; __union {/ unsigned int ka0c05_watch$l_watch_csrb; __struct {7 unsigned ka0c05_watch$v_watch_csrb_dse : 1;9 unsigned ka0c05_watch$v_watch_csrb_24_12 : 1;6 unsigned ka0c05_ m3watch$v_watch_csrb_dm : 1;8 unsigned ka0c05_watch$v_watch_csrb_sqwe : 1;7 unsigned ka0c05_watch$v_watch_csrb_uie : 1;7 unsigned ka0c05_watch$v_watch_csrb_aie : 1;7 unsigned ka0c05_watch$v_watch_csrb_pie : 1;7 unsigned ka0c05_watch$v_watch_csrb_set : 1;7 unsigned ka0c05_watch$v_watch_csrb_f1 : 24;- } ka0c05_watch$r_watch_csrb_bits;, } ka0c05_watch$r_watch_csrb_overlay;/ unsigned char ka0c05_watch$b_fil n3l3070 [60]; __union {/ unsigned int ka0c05_watch$l_watch_csrc; __struct {6 unsigned ka0c05_watch$v_watch_csrc_f1 : 4;6 unsigned ka0c05_watch$v_watch_csrc_uf : 1;6 unsigned ka0c05_watch$v_watch_csrc_af : 1;6 unsigned ka0c05_watch$v_watch_csrc_pf : 1;8 unsigned ka0c05_watch$v_watch_csrc_irqf : 1;7 unsigned ka0c05_watch$v_watch_csrc_f2 : 24;- } ka0c05_watch$r_watch_csrc_bits;, } ka0c05 o3_watch$r_watch_csrc_overlay;/ unsigned char ka0c05_watch$b_fill3080 [60]; __union {/ unsigned int ka0c05_watch$l_watch_csrd; __struct {6 unsigned ka0c05_watch$v_watch_csrd_f1 : 7;7 unsigned ka0c05_watch$v_watch_csrd_vrt : 1;7 unsigned ka0c05_watch$v_watch_csrd_f2 : 24;- } ka0c05_watch$r_watch_csrd_bits;, } ka0c05_watch$r_watch_csrd_overlay;/ unsigned char ka0c05_watch$b_fill3090 [60]; __union {. p3 unsigned int ka0c05_watch$l_watch_ram; __struct {6 unsigned ka0c05_watch$v_watch_ram_f1 : 32;, } ka0c05_watch$r_watch_ram_bits;+ } ka0c05_watch$r_watch_ram_overlay;1 unsigned char ka0c05_watch$b_fill3100 [7292]; } KA0C05_WATCH; #if !defined(__VAXC)d#define ka0c05_watch$l_watch_seconds ka0c05_watch$r_watch_seconds_overl.ka0c05_watch$l_watch_secondsd#define ka0c05_watch$l_watch_minutes ka0c05_watch$r_watch_minutes_overl.ka0c05_watch$l_watchq3_minutes`#define ka0c05_watch$l_watch_hours ka0c05_watch$r_watch_hours_overlay.ka0c05_watch$l_watch_hoursZ#define ka0c05_watch$l_watch_dom ka0c05_watch$r_watch_dom_overlay.ka0c05_watch$l_watch_dom`#define ka0c05_watch$l_watch_month ka0c05_watch$r_watch_month_overlay.ka0c05_watch$l_watch_month]#define ka0c05_watch$l_watch_year ka0c05_watch$r_watch_year_overlay.ka0c05_watch$l_watch_year]#define ka0c05_watch$l_watch_csra ka0c05_watch$r_watch_csra_overlay.ka0c05_watch$l_watch_csra#define ka0c05_wr3atch$v_watch_csra_rs ka0c05_watch$r_watch_csra_overlay.ka0c05_watch$r_watch_csra_bits.ka0c05_watch$v_watch_csra_rs#define ka0c05_watch$v_watch_csra_dv ka0c05_watch$r_watch_csra_overlay.ka0c05_watch$r_watch_csra_bits.ka0c05_watch$v_watch_csra_dv#define ka0c05_watch$v_watch_csra_uip ka0c05_watch$r_watch_csra_overlay.ka0c05_watch$r_watch_csra_bits.ka0c05_watch$v_watch_csra_uip]#define ka0c05_watch$l_watch_csrb ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$l_watch_csrb#define ka0c05_watch$v_watchs3_csrb_dse ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_dse#define ka0c05_watch$v_watch_csrb_24_12 ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_\24_12#define ka0c05_watch$v_watch_csrb_dm ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_dm#define ka0c05_watch$v_watch_csrb_sqwe ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_ct3srb_s\qwe#define ka0c05_watch$v_watch_csrb_uie ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_uie#define ka0c05_watch$v_watch_csrb_aie ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_aie#define ka0c05_watch$v_watch_csrb_pie ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watch_csrb_bits.ka0c05_watch$v_watch_csrb_pie#define ka0c05_watch$v_watch_csrb_set ka0c05_watch$r_watch_csrb_overlay.ka0c05_watch$r_watu3ch_csrb_bits.ka0c05_watch$v_watch_csrb_set]#define ka0c05_watch$l_watch_csrc ka0c05_watch$r_watch_csrc_overlay.ka0c05_watch$l_watch_csrc#define ka0c05_watch$v_watch_csrc_uf ka0c05_watch$r_watch_csrc_overlay.ka0c05_watch$r_watch_csrc_bits.ka0c05_watch$v_watch_csrc_uf#define ka0c05_watch$v_watch_csrc_af ka0c05_watch$r_watch_csrc_overlay.ka0c05_watch$r_watch_csrc_bits.ka0c05_watch$v_watch_csrc_af#define ka0c05_watch$v_watch_csrc_pf ka0c05_watch$r_watch_csrc_overlay.ka0c05_watch$r_watch_csrc_bits.v3ka0c05_watch$v_watch_csrc_pf#define ka0c05_watch$v_watch_csrc_irqf ka0c05_watch$r_watch_csrc_overlay.ka0c05_watch$r_watch_csrc_bits.ka0c05_watch$v_watch_csrc_i\rqf]#define ka0c05_watch$l_watch_csrd ka0c05_watch$r_watch_csrd_overlay.ka0c05_watch$l_watch_csrd#define ka0c05_watch$v_watch_csrd_vrt ka0c05_watch$r_watch_csrd_overlay.ka0c05_watch$r_watch_csrd_bits.ka0c05_watch$v_watch_csrd_vrtZ#define ka0c05_watch$l_watch_ram ka0c05_watch$r_watch_ram_overlay.ka0c05_watch$l_watch_ram"#endif /* #ifw3 !defined(__VAXC) */ $#define KA0C05_GBUS$M_GWHAMI_CPU 0x1$#define KA0C05_GBUS$M_GWHAMI_NID 0xE%#define KA0C05_GBUS$M_GWHAMI_BAD 0x10(#define KA0C05_GBUS$M_GWHAMI_CONWIN 0x20*#define KA0C05_GBUS$M_GWHAMI_MFG_MODE 0x40'#define KA0C05_GBUS$M_GMISCR_CACSIZ 0x3(#define KA0C05_GBUS$M_GMISCR_PROCCNT 0x4'#define KA0C05_GBUS$M_GMISCR_SECURE 0x8%#define KA0C05_GBUS$M_GMISCR_RUN 0x10)#define KA0C05_GBUS$M_GMISCR_CONWIN0 0x40)#define KA0C05_GBUS$M_GMISCR_CONWIN1 0x80*#define KA0C05_GBUS$M_GM x3ISCW_DRIVE_BAD 0x4)#define KA0C05_GBUS$M_GMISCW_FPROM_WE 0x8+#define KA0C05_GBUS$M_GMISCW_DRIVE_RUN 0x10,#define KA0C05_GBUS$M_GMISCW_DRV_CONWIN 0x20)#define KA0C05_GBUS$M_GMISCW_CONWIN0 0x40)#define KA0C05_GBUS$M_GMISCW_CONWIN1 0x80%#define KA0C05_GBUS$M_GSERNUM_CLK 0x1*#define KA0C05_GBUS$M_GSERNUM_RCV_DATA 0x2*#define KA0C05_GBUS$M_GSERNUM_XMT_DATA 0x4)#define KA0C05_GBUS$M_GSERNUM_EXPSEL 0x18'#define KA0C05_GBUS$M_GSERNUM_PIUB 0x20'#define KA0C05_GBUS$M_GSERNUM_PIUA 0x40&#definy3e KA0C05_GBUS$M_GSERNUM_STP 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0c05_gbus {#pragma __nomember_alignment __union {* unsigned int ka0c05_gbus$l_gwhami; __struct {2 unsigned ka0c05_gbus$v_gwhami_cpu : 1;2 unsigned ka0c05_gbus$v_gwhami_nid : 3;2 unsigned ka0c05_gb z3us$v_gwhami_bad : 1;5 unsigned ka0c05_gbus$v_gwhami_conwin : 1;7 unsigned ka0c05_gbus$v_gwhami_mfg_mode : 1;2 unsigned ka0c05_gbus$v_gwhami_f1 : 25;( } ka0c05_gbus$r_gwhami_bits;' } ka0c05_gbus$r_gwhami_overlay;0 unsigned char ka0c05_gbus$b_fill3110 [8188]; __union {- unsigned int ka0c05_gbus$l_gbus_led0; __struct {5 unsigned ka0c05_gbus$v_gbus_led0_f1 : 32;+ } ka0c05_gbus$r_gbus_led0_bits{3;* } ka0c05_gbus$r_gbus_led0_overlay;0 unsigned char ka0c05_gbus$b_fill3120 [8188]; __union {- unsigned int ka0c05_gbus$l_gbus_led1; __struct {5 unsigned ka0c05_gbus$v_gbus_led1_f1 : 32;+ } ka0c05_gbus$r_gbus_led1_bits;* } ka0c05_gbus$r_gbus_led1_overlay;0 unsigned char ka0c05_gbus$b_fill3130 [8188]; __union {- unsigned int ka0c05_gbus$l_gbus_led2; __struct {5 unsigned ka0c05_gbus$v_gbus_ |3led2_f1 : 32;+ } ka0c05_gbus$r_gbus_led2_bits;* } ka0c05_gbus$r_gbus_led2_overlay;0 unsigned char ka0c05_gbus$b_fill3140 [8188]; __union {* unsigned int ka0c05_gbus$l_gmiscr; __struct {5 unsigned ka0c05_gbus$v_gmiscr_cacsiz : 2;6 unsigned ka0c05_gbus$v_gmiscr_proccnt : 1;5 unsigned ka0c05_gbus$v_gmiscr_secure : 1;2 unsigned ka0c05_gbus$v_gmiscr_run : 1;1 unsigned ka0c05_gbus$v_gmiscr_f1 : 1 }3;6 unsigned ka0c05_gbus$v_gmiscr_conwin0 : 1;6 unsigned ka0c05_gbus$v_gmiscr_conwin1 : 1;2 unsigned ka0c05_gbus$v_gmiscr_f2 : 24;( } ka0c05_gbus$r_gmiscr_bits;' } ka0c05_gbus$r_gmiscr_overlay;0 unsigned char ka0c05_gbus$b_fill3150 [8188]; __union {* unsigned int ka0c05_gbus$l_gmiscw; __struct {1 unsigned ka0c05_gbus$v_gmiscw_f1 : 2;8 unsigned ka0c05_gbus$v_gmiscw_drive_bad : 1;7 ~3unsigned ka0c05_gbus$v_gmiscw_fprom_we : 1;8 unsigned ka0c05_gbus$v_gmiscw_drive_run : 1;9 unsigned ka0c05_gbus$v_gmiscw_drv_conwin : 1;6 unsigned ka0c05_gbus$v_gmiscw_conwin0 : 1;6 unsigned ka0c05_gbus$v_gmiscw_conwin1 : 1;2 unsigned ka0c05_gbus$v_gmiscw_f2 : 24;( } ka0c05_gbus$r_gmiscw_bits;' } ka0c05_gbus$r_gmiscw_overlay;0 unsigned char ka0c05_gbus$b_fill3160 [8188]; __union {0 unsigned int ka0c05_ 3gbus$l_gbus_tlsbrst; __struct {8 unsigned ka0c05_gbus$v_gbus_tlsbrst_f1 : 32;. } ka0c05_gbus$r_gbus_tlsbrst_bits;- } ka0c05_gbus$r_gbus_tlsbrst_overlay;0 unsigned char ka0c05_gbus$b_fill3170 [8188]; __union {+ unsigned int ka0c05_gbus$l_gsernum; __struct {3 unsigned ka0c05_gbus$v_gsernum_clk : 1;8 unsigned ka0c05_gbus$v_gsernum_rcv_data : 1;8 unsigned ka0c05_gbus$v_gsernum_xmt_data : 1;6 3 unsigned ka0c05_gbus$v_gsernum_expsel : 2;4 unsigned ka0c05_gbus$v_gsernum_piub : 1;4 unsigned ka0c05_gbus$v_gsernum_piua : 1;3 unsigned ka0c05_gbus$v_gsernum_stp : 1;3 unsigned ka0c05_gbus$v_gsernum_f1 : 24;) } ka0c05_gbus$r_gsernum_bits;( } ka0c05_gbus$r_gsernum_overlay;0 unsigned char ka0c05_gbus$b_fill3180 [8188]; __union {- unsigned int ka0c05_gbus$l_gbus_test; __struct {5 unsi 3gned ka0c05_gbus$v_gbus_test_f1 : 32;+ } ka0c05_gbus$r_gbus_test_bits;* } ka0c05_gbus$r_gbus_test_overlay;0 unsigned char ka0c05_gbus$b_fill3190 [8188]; } KA0C05_GBUS; #if !defined(__VAXC)N#define ka0c05_gbus$l_gwhami ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$l_gwhamip#define ka0c05_gbus$v_gwhami_cpu ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$r_gwhami_bits.ka0c05_gbus$v_gwhami_cpup#define ka0c05_gbus$v_gwhami_nid ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$r_gwhami_bit3s.ka0c05_gbus$v_gwhami_nidp#define ka0c05_gbus$v_gwhami_bad ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$r_gwhami_bits.ka0c05_gbus$v_gwhami_badv#define ka0c05_gbus$v_gwhami_conwin ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$r_gwhami_bits.ka0c05_gbus$v_gwhami_conwinz#define ka0c05_gbus$v_gwhami_mfg_mode ka0c05_gbus$r_gwhami_overlay.ka0c05_gbus$r_gwhami_bits.ka0c05_gbus$v_gwhami_mfg_modeW#define ka0c05_gbus$l_gbus_led0 ka0c05_gbus$r_gbus_led0_overlay.ka0c05_gbus$l_gbus_led0W#define ka0c05_gbus$l_gbus_led31 ka0c05_gbus$r_gbus_led1_overlay.ka0c05_gbus$l_gbus_led1W#define ka0c05_gbus$l_gbus_led2 ka0c05_gbus$r_gbus_led2_overlay.ka0c05_gbus$l_gbus_led2N#define ka0c05_gbus$l_gmiscr ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$l_gmiscrv#define ka0c05_gbus$v_gmiscr_cacsiz ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_cacsizx#define ka0c05_gbus$v_gmiscr_proccnt ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_proccntv#define ka0c05_gbus$v_gmiscr_secur3e ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_securep#define ka0c05_gbus$v_gmiscr_run ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_runx#define ka0c05_gbus$v_gmiscr_conwin0 ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_conwin0x#define ka0c05_gbus$v_gmiscr_conwin1 ka0c05_gbus$r_gmiscr_overlay.ka0c05_gbus$r_gmiscr_bits.ka0c05_gbus$v_gmiscr_conwin1N#define ka0c05_gbus$l_gmiscw ka0c05_gbus$r_gmiscw_overlay.ka0c305_gbus$l_gmiscw|#define ka0c05_gbus$v_gmiscw_drive_bad ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmiscw_drive_badz#define ka0c05_gbus$v_gmiscw_fprom_we ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmiscw_fprom_we|#define ka0c05_gbus$v_gmiscw_drive_run ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmiscw_drive_run~#define ka0c05_gbus$v_gmiscw_drv_conwin ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmi3scw_drv_conwinx#define ka0c05_gbus$v_gmiscw_conwin0 ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmiscw_conwin0x#define ka0c05_gbus$v_gmiscw_conwin1 ka0c05_gbus$r_gmiscw_overlay.ka0c05_gbus$r_gmiscw_bits.ka0c05_gbus$v_gmiscw_conwin1`#define ka0c05_gbus$l_gbus_tlsbrst ka0c05_gbus$r_gbus_tlsbrst_overlay.ka0c05_gbus$l_gbus_tlsbrstQ#define ka0c05_gbus$l_gsernum ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$l_gsernumt#define ka0c05_gbus$v_gsernum_clk ka0c05_gbus$r_gsernum_overlay.3ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_clk~#define ka0c05_gbus$v_gsernum_rcv_data ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_rcv_data~#define ka0c05_gbus$v_gsernum_xmt_data ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_xmt_dataz#define ka0c05_gbus$v_gsernum_expsel ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_expselv#define ka0c05_gbus$v_gsernum_piub ka0c05_gbus$r_gsernum_overlay.ka0c05_3gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_piubv#define ka0c05_gbus$v_gsernum_piua ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_piuat#define ka0c05_gbus$v_gsernum_stp ka0c05_gbus$r_gsernum_overlay.ka0c05_gbus$r_gsernum_bits.ka0c05_gbus$v_gsernum_stpW#define ka0c05_gbus$l_gbus_test ka0c05_gbus$r_gbus_test_overlay.ka0c05_gbus$l_gbus_test"#endif /* #if !defined(__VAXC) */ X#define S_KA0C05DEF 73728 /* Old size name, synonym for KA0C05$S_KA0C05 */3 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KA0C05DEF_LOADED */ wwRi[UM/***************************************************************************/M/** 3 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE3, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*****************************************3**********************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:35 by OpenVMS SDL V3.7 */I/* Source: 21-JAN-1994 16:46:22 $1$DGA8345:[LIB_H.SRC]KA0E04DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KA0E04DEF ***/#ifndef __KA0E04DEF_LOADED#defin 3e __KA0E04DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknow3n_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif $#define KA0E04$M_IOC_PCI_CFG_CYC 0x3#define KA0E04$M_IOC_CERR 0x10#define KA0E04$M_IOC_CLOST 0x20&#define KA0E04$M_IOC_PCI_S3OFT_RST 0x40 #define KA0E04$M_IOC_TLB_EN 0x80##define KA0E04$M_IOC_HAE 0xF8000000#define KA0E04$M_STAT0_CMD 0xF#define KA0E04$M_STAT0_ERR 0x10 #define KA0E04$M_STAT0_LOST 0x20!#define KA0E04$M_STAT0_T_HIT 0x40!#define KA0E04$M_STAT0_T_REF 0x80!#define KA0E04$M_STAT0_CODE 0x700'#define KA0E04$M_STAT0_P_NBR 0xFFFFE000(#define KA0E04$M_WBASE0_WBASE 0xFFF00000&#define KA0E04$M_WBASE0_SG 0x100000000'#define KA0E04$M_WBASE0_WEN 0x200000000(#define KA0E04$M_WBASE1_WBASE 0xFFF00000&#def3ine KA0E04$M_WBASE1_SG 0x100000000'#define KA0E04$M_WBASE1_WEN 0x200000000(#define KA0E04$M_WMASK0_WMASK 0xFFF00000(#define KA0E04$M_WMASK1_WMASK 0xFFF00000(#define KA0E04$M_TBASE0_TBASE 0xFFF00000(#define KA0E04$M_TBASE1_TBASE 0xFFFFFC00 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ka0e04 {#pragma __nomember_alignment __unio 3n {& unsigned __int64 ka0e04$q_ioc; __struct {2 unsigned ka0e04$v_ioc_pci_cfg_cyc : 2;, unsigned ka0e04$v_ioc_fill2 : 2;+ unsigned ka0e04$v_ioc_cerr : 1;, unsigned ka0e04$v_ioc_clost : 1;3 unsigned ka0e04$v_ioc_pci_soft_rst : 1;- unsigned ka0e04$v_ioc_tlb_en : 1;- unsigned ka0e04$v_ioc_fill3 : 19;* unsigned ka0e04$v_ioc_hae : 5;- unsigned ka0e04$v_ioc_fill4 : 32; 3 } ka0e04$r_ioc_bits; } ka0e04$r_ioc_u;\ char ka0e04$b_fill1 [56]; /* this should pad from PA 180000008 to 180000040 */ __union {, unsigned __int64 ka0e04$q_ioc_stat0; __struct {, unsigned ka0e04$v_stat0_cmd : 4;, unsigned ka0e04$v_stat0_err : 1;- unsigned ka0e04$v_stat0_lost : 1;. unsigned ka0e04$v_stat0_t_hit : 1;. unsigned ka0e04$v_stat0_t_ref : 1;- unsigned ka0e04$v_stat0_ 3code : 3;- unsigned ka0e04$v_stat0_fill : 2;/ unsigned ka0e04$v_stat0_p_nbr : 19;/ unsigned ka0e04$v_stat0_fill1 : 32;& } ka0e04$r_ioc_stat0_bits; } ka0e04$r_ioc_stat0;T char ka0e04$b_fill2 [24]; /* pad from PA 1.8000.0048 to 1.8000.0060 */ __union {, unsigned __int64 ka0e04$q_ioc_stat1; } ka0e04$r_ioc_stat1;T char ka0e04$b_fill3 [24]; /* pad from PA 1.8000.0068 to 1.8000.0080 */ __un 3ion {+ unsigned __int64 ka0e04$q_ioc_tbia; } ka0e04$r_ioc_tbia;T char ka0e04$b_fill4 [120]; /* pad from PA 1.8000.0088 to 1.8000.0100 */ __union {- unsigned __int64 ka0e04$q_ioc_wbase0; __struct {/ unsigned ka0e04$v_wbase0_fill : 20;0 unsigned ka0e04$v_wbase0_wbase : 12;, unsigned ka0e04$v_wbase0_sg : 1;- unsigned ka0e04$v_wbase0_wen : 1;0 unsigned ka0e04$v_wbase0_fill1 : 30;' 3 } ka0e04$r_ioc_wbase0_bits; } ka0e04$r_ioc_wbase0;T char ka0e04$b_fill5 [24]; /* pad from PA 1.8000.0108 to 1.8000.0120 */ __union {- unsigned __int64 ka0e04$q_ioc_wbase1; __struct {/ unsigned ka0e04$v_wbase1_fill : 20;0 unsigned ka0e04$v_wbase1_wbase : 12;, unsigned ka0e04$v_wbase1_sg : 1;- unsigned ka0e04$v_wbase1_wen : 1;0 unsigned ka0e04$v_wbase1_fill2 : 30;' } ka0e04$r 3_ioc_wbase1_bits; } ka0e04$r_ioc_wbase1;T char ka0e04$b_fill6 [24]; /* pad from PA 1.8000.0128 to 1.8000.0140 */ __union {- unsigned __int64 ka0e04$q_ioc_wmask0; __struct {/ unsigned ka0e04$v_wmask0_fill : 20;0 unsigned ka0e04$v_wmask0_wmask : 12;0 unsigned ka0e04$v_wmask0_fill1 : 32;' } ka0e04$r_ioc_wmask0_bits; } ka0e04$r_ioc_wmask0;T char ka0e04$b_fill7 [24]; /* pad from PA 1.8 3000.0148 to 1.8000.0160 */ __union {- unsigned __int64 ka0e04$q_ioc_wmask1; __struct {/ unsigned ka0e04$v_wmask1_fill : 20;0 unsigned ka0e04$v_wmask1_wmask : 12;0 unsigned ka0e04$v_wmask1_fill1 : 32;' } ka0e04$r_ioc_wmask1_bits; } ka0e04$r_ioc_wmask1;T char ka0e04$b_fill8 [24]; /* pad from PA 1.8000.0168 to 1.8000.0180 */ __union {- unsigned __int64 ka0e04$q_ioc_tbase0; __struct 3{/ unsigned ka0e04$v_tbase0_fill : 20;0 unsigned ka0e04$v_tbase0_tbase : 12;0 unsigned ka0e04$v_tbase0_fill1 : 32;' } ka0e04$r_ioc_tbase0_bits; } ka0e04$r_ioc_tbase0;T char ka0e04$b_fill9 [24]; /* pad from PA 1.8000.0188 to 1.8000.01A0 */ __union {- unsigned __int64 ka0e04$q_ioc_tbase1; __struct {/ unsigned ka0e04$v_tbase1_fill : 10;0 unsigned ka0e04$v_tbase1_tbase : 22;0 3 unsigned ka0e04$v_tbase1_fill1 : 32;' } ka0e04$r_ioc_tbase1_bits; } ka0e04$r_ioc_tbase1; } KA0E04; #if !defined(__VAXC)0#define ka0e04$q_ioc ka0e04$r_ioc_u.ka0e04$q_iocZ#define ka0e04$v_ioc_pci_cfg_cyc ka0e04$r_ioc_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_pci_cfg_cycL#define ka0e04$v_ioc_cerr ka0e04$r_ioc_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_cerrN#define ka0e04$v_ioc_clost ka0e04$r_ioc_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_clost\#define ka0e04$v_ioc_pci_soft_rst ka0e04$r_ioc3_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_pci_soft_rstP#define ka0e04$v_ioc_tlb_en ka0e04$r_ioc_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_tlb_enJ#define ka0e04$v_ioc_hae ka0e04$r_ioc_u.ka0e04$r_ioc_bits.ka0e04$v_ioc_hae@#define ka0e04$q_ioc_stat0 ka0e04$r_ioc_stat0.ka0e04$q_ioc_stat0X#define ka0e04$v_stat0_cmd ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_cmdX#define ka0e04$v_stat0_err ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_errZ#define ka0e04$v_stat0_lost ka0e04$r_ioc_stat0.ka0e04$3r_ioc_stat0_bits.ka0e04$v_stat0_lost\#define ka0e04$v_stat0_t_hit ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_t_hit\#define ka0e04$v_stat0_t_ref ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_t_refZ#define ka0e04$v_stat0_code ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_code\#define ka0e04$v_stat0_p_nbr ka0e04$r_ioc_stat0.ka0e04$r_ioc_stat0_bits.ka0e04$v_stat0_p_nbr@#define ka0e04$q_ioc_stat1 ka0e04$r_ioc_stat1.ka0e04$q_ioc_stat1=#define ka0e04$q_ioc_tbia ka30e04$r_ioc_tbia.ka0e04$q_ioc_tbiaC#define ka0e04$q_ioc_wbase0 ka0e04$r_ioc_wbase0.ka0e04$q_ioc_wbase0`#define ka0e04$v_wbase0_wbase ka0e04$r_ioc_wbase0.ka0e04$r_ioc_wbase0_bits.ka0e04$v_wbase0_wbaseZ#define ka0e04$v_wbase0_sg ka0e04$r_ioc_wbase0.ka0e04$r_ioc_wbase0_bits.ka0e04$v_wbase0_sg\#define ka0e04$v_wbase0_wen ka0e04$r_ioc_wbase0.ka0e04$r_ioc_wbase0_bits.ka0e04$v_wbase0_wenC#define ka0e04$q_ioc_wbase1 ka0e04$r_ioc_wbase1.ka0e04$q_ioc_wbase1`#define ka0e04$v_wbase1_wbase ka0e04$r_ioc_wba3se1.ka0e04$r_ioc_wbase1_bits.ka0e04$v_wbase1_wbaseZ#define ka0e04$v_wbase1_sg ka0e04$r_ioc_wbase1.ka0e04$r_ioc_wbase1_bits.ka0e04$v_wbase1_sg\#define ka0e04$v_wbase1_wen ka0e04$r_ioc_wbase1.ka0e04$r_ioc_wbase1_bits.ka0e04$v_wbase1_wenC#define ka0e04$q_ioc_wmask0 ka0e04$r_ioc_wmask0.ka0e04$q_ioc_wmask0`#define ka0e04$v_wmask0_wmask ka0e04$r_ioc_wmask0.ka0e04$r_ioc_wmask0_bits.ka0e04$v_wmask0_wmaskC#define ka0e04$q_ioc_wmask1 ka0e04$r_ioc_wmask1.ka0e04$q_ioc_wmask1`#define ka0e04$v_wmask1_wmask 3ka0e04$r_ioc_wmask1.ka0e04$r_ioc_wmask1_bits.ka0e04$v_wmask1_wmaskC#define ka0e04$q_ioc_tbase0 ka0e04$r_ioc_tbase0.ka0e04$q_ioc_tbase0`#define ka0e04$v_tbase0_tbase ka0e04$r_ioc_tbase0.ka0e04$r_ioc_tbase0_bits.ka0e04$v_tbase0_tbaseC#define ka0e04$q_ioc_tbase1 ka0e04$r_ioc_tbase1.ka0e04$q_ioc_tbase1`#define ka0e04$v_tbase1_tbase ka0e04$r_ioc_tbase1.ka0e04$r_ioc_tbase1_bits.ka0e04$v_tbase1_tbase"#endif /* #if !defined(__VAXC) */ ##define KA0E04$K_OPDRIVER_XMT_ISR 1$#define KA0E04$K_OPDRIVE3R_RCV_ISR 12 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KA0E04DEF_LOADED */ ww0i[UM/***************************************************************************/M/** 3 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/*3* VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************3************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:35 by OpenVMS SDL V3.7 */I/* Source: 07-MAR-1997 16:36:13 $1$DGA8345:[LIB_H.SRC]KA0F05DEF.SDL;1 *//********************************************************************************************************************************/%/*** MODULE $KA0F05DEF IDENT X-5 ***/#ifndef __ 3KA0F05DEF_LOADED#define __KA0F05DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern3 "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* GRU space 3 */N/* */#define GRU$M_INT_CLR 0x1#define GRU$M_CNFG_CLK_DIV 0xF0"#define GRU$M_CNFG_CACHE_SP 0x1800"#define GRU$M_CNFG_CACHE_SZ 0xE000##define GRU$M_CNFG_MMB0_CFG 0xF0000%#define GRU$M_CNFG_MMB1_CFG 0xF000000#define GRU$M_CNFG_SS7_MMB0 0x3#define GRU$M_CNFG_SS6_MMB0 0xC #define GRU$M_CNFG_SS5_MMB0 0x30 #define GRU$M_CNFG_SS4_MMB0 0xC0!#define GRU$M_CNFG_SS3_M3MB0 0x300!#define GRU$M_CNFG_SS2_MMB0 0xC00"#define GRU$M_CNFG_SS1_MMB0 0x3000"#define GRU$M_CNFG_SS0_MMB0 0xC000##define GRU$M_CNFG_SS7_MMB1 0x30000##define GRU$M_CNFG_SS6_MMB1 0xC0000$#define GRU$M_CNFG_SS5_MMB1 0x300000$#define GRU$M_CNFG_SS4_MMB1 0xC00000%#define GRU$M_CNFG_SS3_MMB1 0x3000000%#define GRU$M_CNFG_SS2_MMB1 0xC000000&#define GRU$M_CNFG_SS1_MMB1 0x30000000&#define GRU$M_CNFG_SS0_MMB1 0xC0000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If 3using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gru {N/* */N/* The following element is the displacement in the virtual io table from */N/* the cia structure to the gru structure (see map_local_io_0f05() in */N/* io_support_0f05.c). */N/* 3 */#pragma __nomember_alignment- unsigned char gru$b_displacement [57344];N/* */N/* GRU Interrupt request register - 0x8780000000 */N/* */ __union { int gru$l_int_req;2 unsigned char int_req$b_displacement [64]; } gru$r_int_req_overlay;N/* 3 */N/* GRU Interrupt mask register - 0x8780000040 */N/* */ __union { int gru$l_int_mask;3 unsigned char int_mask$b_displacement [64];! } gru$r_int_mask_overlay;N/* */N/* GRU Interrupt Level/edge select register - 0x8780000080 3 */N/* */ __union { int gru$l_int_edge;3 unsigned char int_edge$b_displacement [64];! } gru$r_int_edge_overlay;N/* */N/* GRU Interrupt High/Low select register - 0x87800000C0 */N/* */ __union { int gru$l_int_hi 3lo;3 unsigned char int_hilo$b_displacement [64];! } gru$r_int_hilo_overlay;N/* */N/* GRU Interrupt clear register - 0x8780000100 */N/* */ __union { int gru$l_int_clear; __struct {N unsigned gru$v_int_clr : 1; /* */* unsigned g 3ru$v_iclr_fill : 31;# } gru$r_int_clear_bits;3 unsigned char int_clr$b_displacement [256]; } gru$r_int_clr_overlay;N/* */N/* GRU Cache and Memory Config register - 0x8780000200 */N/* */ __union { int gru$l_cache_config; __struct {N unsigned gru$v_cc_fill : 4; /* 3 */N unsigned gru$v_cnfg_clk_div : 4; /* */N unsigned gru$v_cc_fill1 : 3; /* */N unsigned gru$v_cnfg_cache_sp : 2; /* */N unsigned gru$v_cnfg_cache_sz : 3; /* */N unsigned gru$v_cnfg_mmb0_cfg : 4; /* */N unsigned gru$v_cc_fill2 : 4; /* 3 */N unsigned gru$v_cnfg_mmb1_cfg : 4; /* */( unsigned gru$v_cc_fill3 : 4;& } gru$r_cache_config_bits;6 unsigned char cache_cnfg$b_displacement [256];# } gru$r_cache_cnfg_overlay;N/* */N/* GRU SET Memory Config register - 0x8780000300 */N/* */ 3 __union { int gru$l_set_config; __struct {N unsigned gru$v_cnfg_ss7_mmb0 : 2; /* */N unsigned gru$v_cnfg_ss6_mmb0 : 2; /* */N unsigned gru$v_cnfg_ss5_mmb0 : 2; /* */N unsigned gru$v_cnfg_ss4_mmb0 : 2; /* */N unsigned gru$v_cnfg_ss3_mmb0 : 2; /* */N unsigned gru$v_cnfg_ss2_mm3b0 : 2; /* */N unsigned gru$v_cnfg_ss1_mmb0 : 2; /* */N unsigned gru$v_cnfg_ss0_mmb0 : 2; /* */N unsigned gru$v_cnfg_ss7_mmb1 : 2; /* */N unsigned gru$v_cnfg_ss6_mmb1 : 2; /* */N unsigned gru$v_cnfg_ss5_mmb1 : 2; /* */N unsigned gru$v_cnfg_ss4_mmb1 : 2; /* 3 */N unsigned gru$v_cnfg_ss3_mmb1 : 2; /* */N unsigned gru$v_cnfg_ss2_mmb1 : 2; /* */N unsigned gru$v_cnfg_ss1_mmb1 : 2; /* */N unsigned gru$v_cnfg_ss0_mmb1 : 2; /* */$ } gru$r_set_config_bits;5 unsigned char set_cnfg$b_displacement [1280];! } gru$r_set_cnfg_overlay;N/* 3 */N/* GRU LED register - 0x8780000800 */N/* */ __union { int gru$l_led;/ unsigned char led$b_displacement [256]; } gru$r_led_overlay;N/* */N/* GRU RESET register - 0x8780000900 */N/* 3 */ __union { int gru$l_reset;1 unsigned char reset$b_displacement [256]; } gru$r_reset_overlay; } GRU; #if !defined(__VAXC)9#define gru$l_int_req gru$r_int_req_overlay.gru$l_int_req<#define gru$l_int_mask gru$r_int_mask_overlay.gru$l_int_mask<#define gru$l_int_edge gru$r_int_edge_overlay.gru$l_int_edge<#define gru$l_int_hilo gru$r_int_hilo_overlay.gru$l_int_hilo=#define gru$l_int_clear gru$r_int_clr_over3lay.gru$l_int_clearN#define gru$v_int_clr gru$r_int_clr_overlay.gru$r_int_clear_bits.gru$v_int_clrR#define gru$v_iclr_fill gru$r_int_clr_overlay.gru$r_int_clear_bits.gru$v_iclr_fillF#define gru$l_cache_config gru$r_cache_cnfg_overlay.gru$l_cache_config^#define gru$v_cnfg_clk_div gru$r_cache_cnfg_overlay.gru$r_cache_config_bits.gru$v_cnfg_clk_div`#define gru$v_cnfg_cache_sp gru$r_cache_cnfg_overlay.gru$r_cache_config_bits.gru$v_cnfg_cache_sp`#define gru$v_cnfg_cache_sz gru$r_cache_cnfg_overlay.g3ru$r_cache_config_bits.gru$v_cnfg_cache_sz`#define gru$v_cnfg_mmb0_cfg gru$r_cache_cnfg_overlay.gru$r_cache_config_bits.gru$v_cnfg_mmb0_cfg`#define gru$v_cnfg_mmb1_cfg gru$r_cache_cnfg_overlay.gru$r_cache_config_bits.gru$v_cnfg_mmb1_cfg@#define gru$l_set_config gru$r_set_cnfg_overlay.gru$l_set_config\#define gru$v_cnfg_ss7_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss7_mmb0\#define gru$v_cnfg_ss6_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss6_mmb0\#define gru$3v_cnfg_ss5_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss5_mmb0\#define gru$v_cnfg_ss4_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss4_mmb0\#define gru$v_cnfg_ss3_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss3_mmb0\#define gru$v_cnfg_ss2_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss2_mmb0\#define gru$v_cnfg_ss1_mmb0 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss1_mmb0\#define gru$v_cnfg_ss0_mmb0 gru$r_set_cnfg_overl3ay.gru$r_set_config_bits.gru$v_cnfg_ss0_mmb0\#define gru$v_cnfg_ss7_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss7_mmb1\#define gru$v_cnfg_ss6_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss6_mmb1\#define gru$v_cnfg_ss5_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss5_mmb1\#define gru$v_cnfg_ss4_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss4_mmb1\#define gru$v_cnfg_ss3_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ 3ss3_mmb1\#define gru$v_cnfg_ss2_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss2_mmb1\#define gru$v_cnfg_ss1_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss1_mmb1\#define gru$v_cnfg_ss0_mmb1 gru$r_set_cnfg_overlay.gru$r_set_config_bits.gru$v_cnfg_ss0_mmb1-#define gru$l_led gru$r_led_overlay.gru$l_led3#define gru$l_reset gru$r_reset_overlay.gru$l_reset"#endif /* #if !defined(__VAXC) */ N/* 3 */N/* DS1287A register definitions */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _ka0f05_ds1287a {#pragma __nomember_alignment0 unsigned char ka0f05_ds1287a$b_fill1 [3584];- unsigned int ka0f05_ds12873a$l_port_index;. unsigned char ka0f05_ds1287a$b_fill2 [28];, unsigned int ka0f05_ds1287a$l_port_data;& char ka0f05_ds1287a$b_fill_0_ [4]; } KA0F05_DS1287A; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KA0F05DEF_LOADED */ 3wwPj[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M3/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS S3oftware, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:35 by OpenVMS SDL V3.7 */F/* Source: 11-MAY-1993 14:33:46 $1$DGA8345:[LIB_H.SRC]KDZDEF.SDL;1 *//*********************** 3*********************************************************************************************************//*** MODULE $KDZDEF ***/#ifndef __KDZDEF_LOADED#define __KDZDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size 3*/[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union va 3riant_union#endif#endif N/*+ */O/* KDZ11 Offset Definitions for Registers Accessible Through BI Node Private */N/* Space. Note that in making these registers available in virtual space, */O/* we have only mapped real registers. Therefore these virtual offsets are */N/* different than the hardware physical offsets. */N/*- 3 */#define KDZ$M_PCNTL_RSTRT 0x1#define KDZ$M_PCNTL_PHYLOG 0x2#define KDZ$M_PCNTL_SECENB 0x4#define KDZ$M_PCNTL_STINIT 0x8#define KDZ$M_PCNTL_STFAST 0x10#define KDZ$M_PCNTL_ENBAPT 0x20#define KDZ$M_PCNTL_STPASS 0x40#define KDZ$M_PCNTL_RUN 0x80 #define KDZ$M_PCNTL_CLREVL 0x200#define KDZ$M_PCNTL_WRMEM 0x400#define KDZ$M_PCNTL_EV4 0x800#define KDZ$M_PCNTL_EV3 0x1000#define KDZ$M_PCNTL_EV2 0x2000#define KDZ$M_PCNTL_EV1 0x4000#define KDZ$M_PCNTL_EV0 0x8000 #defin3e KDZ$M_PCNTL_WWPO 0x10000!#define KDZ$M_PCNTL_NIDIS 0x80000##define KDZ$M_PCNTL_CNSLIE 0x100000##define KDZ$M_PCNTL_CNSLCL 0x200000##define KDZ$M_PCNTL_CNSLIN 0x400000!#define KDZ$M_PCNTL_WWPE 0x800000$#define KDZ$M_PCNTL_RXDONE 0x1000000$#define KDZ$M_PCNTL_RXSTAT 0x2000000$#define KDZ$M_PCNTL_CLRIPI 0x4000000$#define KDZ$M_PCNTL_IPINTR 0x8000000$#define KDZ$M_PCNTL_CRDIE 0x10000000%#define KDZ$M_PCNTL_CLRCRD 0x20000000%#define KDZ$M_PCNTL_CRDINT 0x40000000N#define KDZ$S_KDZDEF 4 34032 /* Old size name - synonym */ typedef struct _kdz {N/* */N/* BIIC registers - here we reserve space for the 256 bytes that these */D/* registers occupy and we also fill out the virtual page to */C/* 512 bytes so that other items appear on page boundaries. */E/* Being able to address the BIIC via these virtual addresses */B/* allows a Scorpio CPU to determine its ow3n node number. */B/* That is, a reference here is via node private space and */B/* always addresses a nodes own registers via a loop back */B/* request. */N/* */N unsigned char kdz$b_biicbase; /*BIIC register Base */N char kdzdef$$_fill_1 [511]; /* Fill out to page. */N/* 3 */N/* Port Control CSR register */N/* */ __union {N unsigned int kdz$l_pcntl; /*Port Control CSR Register */N __struct { /* Port Controller CSR */N unsigned kdz$v_pcntl_rstrt : 1; /* (RO) Front Panel Switch */N/* selecting RSTRT/HALT 3 */N unsigned kdz$v_pcntl_phylog : 1; /* (RO) Backplane Bit */N/* selecting PHYS/LOG Console */N unsigned kdz$v_pcntl_secenb : 1; /* (RO) Front Panel Switch */N/* to lock out console input */N unsigned kdz$v_pcntl_stinit : 1; /* Self-Test INIT. */N unsigned kdz$v_pcntl_stfast : 1; /* (RO) Backplane bit to */3N/* select Fast Self-Test. */N unsigned kdz$v_pcntl_enbapt : 1; /* Enable APT. */N unsigned kdz$v_pcntl_stpass : 1; /* Self-Test Pass. */N unsigned kdz$v_pcntl_run : 1; /* 1=>Program mode,0=>Console */N unsigned kdz$$_fill_2 : 1; /* */N unsigned kdz$v_pcntl_clrevl : 1; /* Clear Event Lock */N unsigned kdz3$v_pcntl_wrmem : 1; /* Write Memory Bit */N unsigned kdz$v_pcntl_ev4 : 1; /* Event Bits - These */N unsigned kdz$v_pcntl_ev3 : 1; /* RO bits are event */N unsigned kdz$v_pcntl_ev2 : 1; /* codes from BIIC to */N unsigned kdz$v_pcntl_ev1 : 1; /* allow CPU to monitor */N unsigned kdz$v_pcntl_ev0 : 1; /* BI status */N unsigned kdz$v_pcntl_wwpo : 1; /* Writ3e Wrong Parity Odd */M unsigned kdz$$_fill_3 : 2; /*bitfield mask; /* Disable RX50 */N unsigned kdz$v_pcntl_nidis : 1; /* Disable NI Lance */N unsigned kdz$v_pcntl_cnslie : 1; /* Console Interrupt Enable */N unsigned kdz$v_pcntl_cnslcl : 1; /* Clear Console Interrupt */N unsigned kdz$v_pcntl_cnslin : 1; /* Console Interrupt RCVD */N unsigned kdz$v_pcntl_wwpe : 1; /* Write Wrong Parity Even 3*/N unsigned kdz$v_pcntl_rxdone : 1; /* RX Done Interrupt */N unsigned kdz$v_pcntl_rxstat : 1; /* RX Status Interrupt */N unsigned kdz$v_pcntl_clripi : 1; /* Clear IP Interrupt */N unsigned kdz$v_pcntl_ipintr : 1; /* IP Interrupt RCVD */N unsigned kdz$v_pcntl_crdie : 1; /* CRD Interrupt Enable */N unsigned kdz$v_pcntl_clrcrd : 1; /* Clear CRD Interrupt */N unsigned k 3dz$v_pcntl_crdint : 1; /* CRD Interrupt RCVD */' unsigned kdz$v_fill_0_ : 1; } kdz$r_pcntl_bits; } kdz$r_pcntl_overlay;N char kdzdef$$_fill_4 [508]; /* Fill out page */N/* */N/* NI Packet Buffer */N/* */N unsigned char kd3z$b_nibuf; /*NI Packet Buffer Base */N char kdzdef$$_fill_5 [32767]; /* Fill out to 32KB */N/* */N/* EEPROM */N/* */N unsigned char kdz$b_eeprom; /*EEPROM Base */N char kdzdef$$_fill_6 [8191]; /* Fil3l out to 8KB */N/* */N/* NI Data Register */N/* */N unsigned int kdz$l_nidata; /* NI Data Register */N char kdzdef$$_fill_7 [508]; /* Fill out page */N/* 3 */N/* NI Address Register */N/* */N void *kdz$l_niaddr; /* NI Address Register */N char kdzdef$$_fill_8 [508]; /* Fill out page */N/* */N/* RCX50 Registers */N/* 3 */N unsigned char kdz$b_rcx50; /* RCX50 Registers */N char kdzdef$$_fill_9 [511]; /* Fill out page */N/* */N/* Watch Chip Registers */N/* */N unsigned char kdz$b_watch; /* W 3atch Chip Registers */N char kdzdef$$_fill_10 [511]; /* Fill out page */ } KDZ; #if !defined(__VAXC)3#define kdz$l_pcntl kdz$r_pcntl_overlay.kdz$l_pcntlP#define kdz$v_pcntl_rstrt kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_rstrtR#define kdz$v_pcntl_phylog kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_phylogR#define kdz$v_pcntl_secenb kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_secenbR#define kdz$v_pcntl_stinit kdz$r_pcntl_overlay.k3dz$r_pcntl_bits.kdz$v_pcntl_stinitR#define kdz$v_pcntl_stfast kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_stfastR#define kdz$v_pcntl_enbapt kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_enbaptR#define kdz$v_pcntl_stpass kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_stpassL#define kdz$v_pcntl_run kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_runR#define kdz$v_pcntl_clrevl kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_clrevlP#define kdz$v_pcntl_wrmem kdz$r_pcntl_overlay.kdz$r_pcnt3l_bits.kdz$v_pcntl_wrmemL#define kdz$v_pcntl_ev4 kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_ev4L#define kdz$v_pcntl_ev3 kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_ev3L#define kdz$v_pcntl_ev2 kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_ev2L#define kdz$v_pcntl_ev1 kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_ev1L#define kdz$v_pcntl_ev0 kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_ev0N#define kdz$v_pcntl_wwpo kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_wwpoP#define kd3z$v_pcntl_nidis kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_nidisR#define kdz$v_pcntl_cnslie kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_cnslieR#define kdz$v_pcntl_cnslcl kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_cnslclR#define kdz$v_pcntl_cnslin kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_cnslinN#define kdz$v_pcntl_wwpe kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_wwpeR#define kdz$v_pcntl_rxdone kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_rxdoneR#define kdz$v_pcnt3l_rxstat kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_rxstatR#define kdz$v_pcntl_clripi kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_clripiR#define kdz$v_pcntl_ipintr kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_ipintrP#define kdz$v_pcntl_crdie kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_crdieR#define kdz$v_pcntl_clrcrd kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_clrcrdR#define kdz$v_pcntl_crdint kdz$r_pcntl_overlay.kdz$r_pcntl_bits.kdz$v_pcntl_crdint"#endif /* #if !define3d(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KDZDEF_LOADED */ wwpcj[UM/***************************************************************************/M/** 3 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/*3* VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************3************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */I/* Source: 09-JUN-1993 15:42:57 $1$DGA8345:[LIB_H.SRC]RMSFILSTR.SDL;1 *//********************************************************************************************************************************//*** MODULE $KEYDEF ***/#ifndef __KEYDEF_LOADED 3#define __KEYDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __3unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* definitions for the key descriptors in th 3e prologue */N/* */N/* these definitions are associated w/ the plg and area definitions */N/* */#define KEY$M_DUPKEYS 0x1#define KEY$M_CHGKEYS 0x2#define KEY$M_NULKEYS 0x4#define KEY$M_IDX_COMPR 0x8#define KEY$M_INITIDX 0x10#define KEY$M_KEY_COMPR 0x40#define KEY$M_REC_COMPR 0x80[#define KEY$C_MAX_DAT 10 3 /* (PLG3) Maximum size of a non-compressed data */N/* record */V#define KEY$C_MAX_PRIMARY 6 /* (PLG3) Maximum size of a non-compressed */N/* primary key */V#define KEY$C_MAX_INDEX 6 /* (PLG3) Maximum size of a non-compressed */N/* index and SIDR key */N#define KEY$C_STRING 0 3 /* string data type */N#define KEY$C_SGNWORD 1 /* signed binary word */N#define KEY$C_UNSGNWORD 2 /* unsigned binary word */N#define KEY$C_SGNLONG 3 /* signed binary long word */N#define KEY$C_UNSGNLONG 4 /* unsigned binary long word */N#define KEY$C_PACKED 5 /* packed decimal */N#define KEY$C_SGNQUAD 6 /* signed 3binary quadword */N#define KEY$C_UNSGNQUAD 7 /* unsigned binary quadword */N#define KEY$C_COLLATED 8 /* collated */N#define KEY$C_MAX_ASCEND 8 /* maximum ASCENDING data type */N#define KEY$C_DSTRING 32 /* descending string data type */N#define KEY$C_DSGNWORD 33 /* " signed binary word */N#define KEY$C_DUNSGNWORD 34 /* " unsigned binary word 3*/Q#define KEY$C_DSGNLONG 35 /* " signed binary long word */S#define KEY$C_DUNSGNLONG 36 /* " unsigned binary long word */N#define KEY$C_DPACKED 37 /* " packed decimal */O#define KEY$C_DSGNQUAD 38 /* " signed binary quadword */Q#define KEY$C_DUNSGNQUAD 39 /* " unsigned binary quadword */N#define KEY$C_DCOLLATED 40 /* " collated */N#defin3e KEY$C_MAX_DATA 40 /* maximum data type value allowed */_#define KEY$K_BLN 96 /* length of key descriptor in the prologue (plg 3) */_#define KEY$C_BLN 96 /* length of key descriptor in the prologue (plg 3) */Y#define KEY$C_SPARE 6 /* these are spare words in key block (plg 3) */N#define KEY$S_KEYDEF 96 /* Old size name - synonym */ typedef struct _prologue_key {N unsigned int key$l_idxfl3; /* vbn for next key descriptor */N unsigned short int key$w_noff; /* offset to next key descriptor */N unsigned char key$b_ianum; /* index area number */N unsigned char key$b_lanum; /* level 1 area number */N unsigned char key$b_danum; /* data area number */N unsigned char key$b_rootlev; /* root level */N unsigned char key$b_idxbktsz; /* index bucke 3t size */N unsigned char key$b_datbktsz; /* data bucket size */N unsigned int key$l_rootvbn; /* root bucket pointer */ __union {N unsigned char key$b_flags; /* flag bits */ __struct {N unsigned key$v_dupkeys : 1; /* duplicate key values allowed */X unsigned key$v_chgkeys : 1; /* key value may change on $update operation */N unsigned key$v_nulke 3ys : 1; /* null key character enabled */N unsigned key$v_idx_compr : 1; /* index is compressed */N unsigned key$v_initidx : 1; /* index must be initialized */N unsigned key$$_fill_1 : 1; /* spare */X unsigned key$v_key_compr : 1; /* (PLG3) key is compressed in data record */' unsigned key$v_fill_8_ : 1; } key$r_flags_bits0; __struct {N unsigned key$$_fil3l_2 : 1; /* space over dupkeys */N unsigned key$$_fill_3 : 2; /* spare */N unsigned key$$_fill_4 : 1; /* space over idx_compr */N unsigned key$$_fill_5 : 1; /* space over initidx */N unsigned key$$_fill_6 : 1; /* spare */N unsigned key$$_fill_7 : 1; /* space over key compr */Q unsigned key$v_rec_compr : 1; /* (PLG3) Data 3 record is compressed */ } key$r_flags_bits1; } key$r_flags_overlay;N unsigned char key$b_datatype; /* data type for key */N unsigned char key$b_segments; /* number of segments in key */N unsigned char key$b_nullchar; /* "null" character */N unsigned char key$b_keysz; /* total key size */N unsigned char key$b_keyref; /* key of reference */N unsigned3 short int key$w_minrecsz; /* minimum record length */N unsigned short int key$w_idxfill; /* index fill quantity */N unsigned short int key$w_datfill; /* data fill quantity */ __union {N unsigned short int key$w_position; /* key seg position */N unsigned short int key$w_position0; /* another name for position 0 */! } key$r_position_overlay;N unsigned short int key$w_position1; /* position 1 3 */N unsigned short int key$w_position2; /* position 2 */N unsigned short int key$w_position3; /* position 3 */N unsigned short int key$w_position4; /* position 4 */' unsigned short int key$w_position5;' unsigned short int key$w_position6;' unsigned short int key$w_position7; __union {N unsigned char key$b_size; /* key segment size */N unsigned char key$b_si 3ze0; /* another name for size */ } key$r_size_overlay;N unsigned char key$b_size1; /* size 1 */ unsigned char key$b_size2; unsigned char key$b_size3; unsigned char key$b_size4; unsigned char key$b_size5; unsigned char key$b_size6; unsigned char key$b_size7;N char key$t_keynam [32]; /* key name */N unsigned int key$l_ldvbn; /* first data bucket 3 */ __union {N unsigned char key$b_type; /* key segment datatype (plg 3) */V unsigned char key$b_type0; /* another name for first datatype (plg 3) */ } key$r_type_overlay;N unsigned char key$b_type1; /* (plg 3) */N unsigned char key$b_type2; /* (plg 3) */N unsigned char key$b_type3; /* (plg 3) */N unsigned char key$b_type4; /* 3 (plg 3) */N unsigned char key$b_type5; /* (plg 3) */N unsigned char key$b_type6; /* (plg 3) */N unsigned char key$b_type7; /* (plg 3) */ } PROLOGUE_KEY; #if !defined(__VAXC)3#define key$b_flags key$r_flags_overlay.key$b_flags?#define key$r_flags_bits0 key$r_flags_overlay.key$r_flags_bits05#define key$v_dupkeys key$r_flags_bits0.key$v_dupkeys5#def 3ine key$v_chgkeys key$r_flags_bits0.key$v_chgkeys5#define key$v_nulkeys key$r_flags_bits0.key$v_nulkeys9#define key$v_idx_compr key$r_flags_bits0.key$v_idx_compr5#define key$v_initidx key$r_flags_bits0.key$v_initidx9#define key$v_key_compr key$r_flags_bits0.key$v_key_compr?#define key$r_flags_bits1 key$r_flags_overlay.key$r_flags_bits19#define key$v_rec_compr key$r_flags_bits1.key$v_rec_compr<#define key$w_position key$r_position_overlay.key$w_position>#define key$w_position0 key$r_posi 3tion_overlay.key$w_position00#define key$b_size key$r_size_overlay.key$b_size2#define key$b_size0 key$r_size_overlay.key$b_size00#define key$b_type key$r_type_overlay.key$b_type2#define key$b_type0 key$r_type_overlay.key$b_type0"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif3#ifdef __cplusplus }#endif#pragma __standard #endif /* __KEYDEF_LOADED */ wwj[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone witho3ut the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prio3r written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SDL V3.7 */F/* 3 Source: 20-JAN-2004 10:53:17 $1$DGA8345:[LIB_H.SRC]KFDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KFDDEF ***/#ifndef __KFDDEF_LOADED#define __KFDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported 3*/\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif3 #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* KNOWN FILE DEVICE AND DIRECTORY BLOCK DEFINITIONS */N/* */P#define KFD$C_LENGTH 17 /* Length of fixed area of kfd entry */N#define KFD$S_KFDDEF 17 /* Old size name 3 - synonym */ typedef struct _kfd {Z struct _kfd *kfd$l_link; /* Device, Directory, Extension (KFD) list link */R void *kfd$l_kfelist; /* Ordered Known file entry list header */N unsigned short int kfd$w_size; /* Size of block */N unsigned char kfd$b_type; /* Structure type */N unsigned char kfd$b_spare; /* spare */N unsigned short int kfd$w_refcnt; 3 /* Number of KFE's with same KFD */N unsigned char kfd$b_devlen; /* Length of Device string */N unsigned char kfd$b_dirlen; /* Length of Directory string */\ unsigned char kfd$b_ddtstrlen; /* Length of Device, Directory, Type (DDT) string */#if defined(__VAXC) char kfd$t_ddtstr[];#elseS/* Warning: empty char[] member for kfd$t_ddtstr at end of structure not created */"#endif /* #if defined(__VAXC) */ } KFD; $#pragma __member3_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KFDDEF_LOADED */ wwj[UM/***************************************************************************/M/** **/M/** HPE CONFID3ENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. Thi3s software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************** 3**********//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SDL V3.7 */H/* Source: 11-MAY-1993 15:50:20 $1$DGA8345:[LIB_H.SRC]KFE52DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KFE52DEF ***/#ifndef __KFE52DEF_LOADED#define __KFE52DEF_LOADED 1 G 3#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __opti3onal_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* CIRRUS CIO module related definitions */ 3N/* */#define KFE52RAM$M_REV 0x7FF$#define KFE52RAM$M_SERIALNO 0x3FF800%#define KFE52RAM$M_MODULEID 0x3C00000N#define KFE52RAM$S_RAMDEF 8 /* Old size name - synonym */ typedef struct _cirram {N __union { /* Module data */N unsigned int kfe52ram$l_moddata; /* */N __struct { /* 3 */N unsigned kfe52ram$v_rev : 11; /* Module revision filed */N unsigned kfe52ram$v_serialno : 11; /* Module serial number */N unsigned kfe52ram$v_moduleid : 4; /* Module id type */, unsigned kfe52ram$v_fill_0_ : 6;& } kfe52ram$r_moddate_bits;% } kfe52ram$r_moddate_overlay;N unsigned int kfe52ram$l_modstatus; /* Module status */ } CIRRAM; #if !d 3efined(__VAXC)H#define kfe52ram$l_moddata kfe52ram$r_moddate_overlay.kfe52ram$l_moddataX#define kfe52ram$v_rev kfe52ram$r_moddate_overlay.kfe52ram$r_moddate_bits.kfe52ram$v_revb#define kfe52ram$v_serialno kfe52ram$r_moddate_overlay.kfe52ram$r_moddate_bits.kfe52ram$v_serialnob#define kfe52ram$v_moduleid kfe52ram$r_moddate_overlay.kfe52ram$r_moddate_bits.kfe52ram$v_moduleid"#endif /* #if !defined(__VAXC) */ N#define KFE52RAM$K_MOD_GOOD 179 /* Good module status */N#defin 3e KFE52RAM$K_MOD_BAD 76 /* Bad module status */N#define KFE52RAM$L_TRDB 13312 /* Trace RAM data block */N/* SLIM offsets and definitions */#define SLI520$M_TCA 0x7C#define SLI520$M_TESTPTRS 0x80#define SLI520$M_DIAGMODE 0x100#define SLI520$M_DMASEL 0x400#define SLI520$M_DISARB 0x800N#define SLI520$S_SLIMDEF 4 /* Old size name - synonym */ typedef struct _cirslim { 3 __union {N unsigned int sli520$l_icsr0; /* II32 Control register */ __struct {) unsigned sli520$v_fill_3 : 2;N unsigned sli520$v_tca : 5; /* Trace RAM number */N unsigned sli520$v_testptrs : 1; /* Test pointers */N unsigned sli520$v_diagmode : 1; /* Diagnostic mode */) unsigned sli520$v_fill_2 : 1;N unsigned sli520$v_dmasel : 1; /* DMA select 4 */N unsigned sli520$v_disarb : 1; /* Disable arbitration */* unsigned sli520$v_fill_1_ : 4;" } sli520$r_icsr0_bits;! } sli520$r_icsr0_overlay; } CIRSLIM; #if !defined(__VAXC)<#define sli520$l_icsr0 sli520$r_icsr0_overlay.sli520$l_icsr0L#define sli520$v_tca sli520$r_icsr0_overlay.sli520$r_icsr0_bits.sli520$v_tcaV#define sli520$v_testptrs sli520$r_icsr0_overlay.sli520$r_icsr0_bits.sli520$v_testptrsV#define sli520$v_diagm 4ode sli520$r_icsr0_overlay.sli520$r_icsr0_bits.sli520$v_diagmodeR#define sli520$v_dmasel sli520$r_icsr0_overlay.sli520$r_icsr0_bits.sli520$v_dmaselR#define sli520$v_disarb sli520$r_icsr0_overlay.sli520$r_icsr0_bits.sli520$v_disarb"#endif /* #if !defined(__VAXC) */ N/* FIREWALL offsets */N#define FIR520$S_FIRDEF 48 /* Old size name - synonym */ typedef struct _cirfir {N unsigned int fir520$l_intvec0; /*4 SWIFT */N unsigned int fir520$l_intvec1; /* LANCE */N unsigned int fir520$l_intvec2; /* Not used */N unsigned int fir520$l_intvec3; /* PCM */N unsigned int fir520$l_uccrvec; /* UCCR (read only) */N unsigned int fir520$l_dccrvec; /* DCCR (read only) */! unsigned int fir520$l_fill_1;W unsigned int fir520$l_winvec4; /* Vector that has won interrupt arbitration */b unsigned int fir520$l_ipl; /* IPL settings for INTVEC0 - INTVEC3 (Interrupt Level) */N unsigned int fir520$l_imr; /* Interrupt Mask Register */P unsigned int fir520$l_ics; /* Interrupt Control/Status register. */N unsigned int fir520$l_pcmvec; /* PCM */ } CIRFIR;N/* SCB offsets per section of the second page of the SCB. The second page */N/* of the 4SCB is divided into 16 sections each of which correspond to */N/* a slot (TR) number. */N#define KA520SCB$S_CIRCSCBDEF 20 /* Old size name - synonym */ typedef struct _cirscb {N unsigned int ka520scb$l_coni; /* Console input */N unsigned int ka520scb$l_cono; /* Console output */N unsigned int ka520scb$l_lance; /* LANCE */N un4signed int ka520scb$l_swift; /* SWIFT */N unsigned int ka520scb$l_pcm; /* PCM */ } CIRSCB;O/* The physical byte offsets of various register from the beginning of a CIO */N/* module. */N#define KFE52$K_COMM_RAM 0 /* COMM RAM */N#define KFE52$K_COMM_SIZE 65536 /* COMM RAM size */N#define KFE52$4K_SL_RAM 65536 /* SWIFT/LANCE RAM */N#define KFE52$K_SL_SIZE 196608 /* SWIFT/LANCE RAM size */N#define KFE52$K_LANCE_RAM 65536 /* LANCE RAM */N#define KFE52$K_LANCE_SIZE 65536 /* LANCE RAM size */N#define KFE52$K_SWIFT_RAM 131072 /* SWIFT RAM */N#define KFE52$K_SWIFT_SIZE 131072 /* SWIFT RAM size */N#define KFE52$K_ETH_ADR_ROM 9043968 4/* Ethernet address ROM */N#define KFE52$K_SSC_CSR 9699328 /* SSC CSR and RAM */N#define KFE52$K_SSC_TOY_CLOCK 9699436 /* SSC TOY clock */N#define KFE52$K_FIREWALL 10485760 /* Firewall registers */N#define KFE52$K_DMA_BCNT 10489856 /* DMA byte count */N#define KFE52$K_DMA_STL 10489860 /* DMA sub transfer length */N#define KFE52$K_DMA_STS 10489864 /* DMA status 4 */N#define KFE52$K_PCM_CSR 10498048 /* PCM CSR */N#define KFE52$K_FW_CSR 10502144 /* Firewall CSR */N#define KFE52$K_CONS_CSR 10510336 /* Console registers */N#define KFE52$K_SLIM_CSR 12582912 /* SLIM CSR */N#define KFE52$K_SWIFT_CSR 12582976 /* SWIFT CSR */N#define KFE52$K_LANCE_CSR 12583040 /* LANCE CSR */N/* CONSOLE R 4EGISTER offsets and definitions */#define CON520$M_UTYP 0x100#define CON520$M_UID 0xE00#define CON520$M_UBRK 0x1000#define CON520$M_UEIE 0x2000#define CON520$M_UFIE 0x4000#define CON520$M_UBSY 0x8000#define CON520$M_DTYP 0x100#define CON520$M_DID 0xE00#define CON520$M_DEIE 0x2000#define CON520$M_DFIE 0x4000#define CON520$M_DBSY 0x8000N#define CON520$S_CONDEF 8 /* Old size name - synonym */ typedef struct _circon {  4 __union {S unsigned int con520$l_uccr; /* UPWARD Console Communication Register */ __struct {N unsigned con520$v_udata : 8; /* Data */N unsigned con520$v_utyp : 1; /* Type */N unsigned con520$v_uid : 3; /* ID */N unsigned con520$v_ubrk : 1; /* CIO module Broken */N unsigned con520$v_ueie : 1; /* Empty Interrupt enabl 4e */N unsigned con520$v_ufie : 1; /* Full Interrupt enable */N unsigned con520$v_ubsy : 1; /* Busy */! } con520$r_uccr_bits; } con520$r_uccr_overlay; __union {U unsigned int con520$l_dccr; /* DOWNWARD Console Communication Register */ __struct {N unsigned con520$v_ddata : 8; /* Data */N unsigned con520$v_dtyp : 1; /* Type 4 */N unsigned con520$v_did : 3; /* ID */N unsigned con520$v_dfill : 1; /* MBZ */N unsigned con520$v_deie : 1; /* Empty interrupt enable */N unsigned con520$v_dfie : 1; /* Full Interrupt enable */N unsigned con520$v_dbsy : 1; /* Busy */! } con520$r_dccr_bits; } con520$r_dccr_overlay; } CIRC 4ON; #if !defined(__VAXC)9#define con520$l_uccr con520$r_uccr_overlay.con520$l_uccrN#define con520$v_udata con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_udataL#define con520$v_utyp con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_utypJ#define con520$v_uid con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_uidL#define con520$v_ubrk con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_ubrkL#define con520$v_ueie con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_ueieL#define con520$v_ufie co4n520$r_uccr_overlay.con520$r_uccr_bits.con520$v_ufieL#define con520$v_ubsy con520$r_uccr_overlay.con520$r_uccr_bits.con520$v_ubsy9#define con520$l_dccr con520$r_dccr_overlay.con520$l_dccrN#define con520$v_ddata con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_ddataL#define con520$v_dtyp con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_dtypJ#define con520$v_did con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_didL#define con520$v_deie con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_deieL#d 4efine con520$v_dfie con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_dfieL#define con520$v_dbsy con520$r_dccr_overlay.con520$r_dccr_bits.con520$v_dbsy"#endif /* #if !defined(__VAXC) */ !#define FWCSR520$M_TRACE_READ 0x1 #define FWCSR520$M_CPU_WRITE 0x2#define FWCSR520$M_CPU_READ 0x4##define FWCSR520$M_CPU_XCHK_ENA 0x8#define FWCSR520$M_FW_LOCK 0x10 #define FWCSR520$M_II32_DRV 0x20#define FWCSR520$M_DMR_ENA 0x40!#define FWCSR520$M_DIAG_MODE 0x80$#define FWCSR520$M_IO_XCHK_ERR 04x100"#define FWCSR520$M_DIAG_XCHK 0x200$#define FWCSR520$M_IO_XCHK_ENA 0x400#define FWCSR520$M_MBZ 0x800!#define FWCSR520$M_RAIL_ID 0x1000!#define FWCSR520$M_SLOT_ID 0xE000N#define FWCSR520$S_FWCSRDEF 4 /* Old size name - synonym */ typedef struct _cirfwcsr { __union {N unsigned int fwcsr520$l_fwcsr; /* Firewall Control register */ __struct {N unsigned fwcsr520$v_trace_read : 1; /* Read Trace RAMs */P un4signed fwcsr520$v_cpu_write : 1; /* CVAX write downward console */N unsigned fwcsr520$v_cpu_read : 1; /* CVAX read upward console */N unsigned fwcsr520$v_cpu_xchk_ena : 1; /* CVAX crosscheck enable */N unsigned fwcsr520$v_fw_lock : 1; /* Firewall lock */N unsigned fwcsr520$v_ii32_drv : 1; /* 1132(T) drive */N unsigned fwcsr520$v_dmr_ena : 1; /* DMR enable */N unsigned fwcsr520$v_diag_m4ode : 1; /* Diagnostic mode */N unsigned fwcsr520$v_io_xchk_err : 1; /* UVAX crosscheck error */N unsigned fwcsr520$v_diag_xchk : 1; /* Diagnostic crosscheck bit */N unsigned fwcsr520$v_io_xchk_ena : 1; /* UVAX crosscheck enable */N unsigned fwcsr520$v_mbz : 1; /* Must be zero */N unsigned fwcsr520$v_rail_id : 1; /* Rail ID */N unsigned fwcsr520$v_slot_id : 3; /* Slot ID 4 */N unsigned fwcsr520$v_unused : 16; /* Unused */$ } fwcsr520$r_fwcsr_bits;# } fwcsr520$r_fwcsr_overlay; } CIRFWCSR; #if !defined(__VAXC)B#define fwcsr520$l_fwcsr fwcsr520$r_fwcsr_overlay.fwcsr520$l_fwcsrb#define fwcsr520$v_trace_read fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_trace_read`#define fwcsr520$v_cpu_write fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_cpu_write^#define fwcsr520$v_cpu_r4ead fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_cpu_readf#define fwcsr520$v_cpu_xchk_ena fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_cpu_xchk_ena\#define fwcsr520$v_fw_lock fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_fw_lock^#define fwcsr520$v_ii32_drv fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_ii32_drv\#define fwcsr520$v_dmr_ena fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_dmr_ena`#define fwcsr520$v_diag_mode fwcsr520$r_fwcsr_4overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_diag_moded#define fwcsr520$v_io_xchk_err fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_io_xchk_err`#define fwcsr520$v_diag_xchk fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_diag_xchkd#define fwcsr520$v_io_xchk_ena fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_io_xchk_enaT#define fwcsr520$v_mbz fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_mbz\#define fwcsr520$v_rail_id fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwc 4sr_bits.fwcsr520$v_rail_id\#define fwcsr520$v_slot_id fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_slot_idZ#define fwcsr520$v_unused fwcsr520$r_fwcsr_overlay.fwcsr520$r_fwcsr_bits.fwcsr520$v_unused"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus4 }#endif#pragma __standard #endif /* __KFE52DEF_LOADED */ wwtk[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** `0 KA0905DEF1 KA0C05DEF3V KA0E04DEF3d KA0F05DEF KA1605DEF3 KDZDEF3dKEYDEF3jKFDDEF3>KFE52DEF4XKFEDEF04 KFERESDEFC4KFHDEFK4HKFIDEF`4KFPBDEFh4KFPDEFp4KFRHDEFy4KPBDEF4 KPSTACKDEF4KRIPRDEF4LANDEF'5HLANIDEF05Z LANIPROTODEF85dLANUDEF\5 LAN_LNMDEFc5LCADEF5 LCKCPUDEF5 LCKCTXDEF5N LCKDLBDEF5> LCKMGRDEF5LCKRQDEF5j LCKSTRDEF5LCSDEF` LDR_ROUTINES4prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permissi4on of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SDL V3.7 */F/* Source: 18-JUN-2 4020 15:50:27 $1$DGA8345:[LIB_H.SRC]KFEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KFEDEF ***/#ifndef __KFEDEF_LOADED#define __KFEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __requ4ired_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __unio4n#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* KNOWN FILE ENTRY DEFINITIONS */N/* */#define KFE$M_PROTECT 0x1#define KFE$M_LIM 0x2#define KFE$M_PROCPRIV 0x4#define KFE$M_OPEN 0x8#define KFE$M_HDRRES 0x10#define KFE$M_SHARED 0x240#define KFE$M_KFE_NAMING 0x40#define KFE$M_COMPRESS 0x80#define KFE$M_NOPURGE 0x100#define KFE$M_ACCOUNT 0x200#define KFE$M_WRITEABLE 0x400#define KFE$M_EXEONLY 0x800"#define KFE$M_DISCONTIGUOUS 0x1000 #define KFE$M_DELETE_PEND 0x2000!#define KFE$M_VERSION_SAFE 0x4000"#define KFE$M_DATA_RESIDENT 0x8000#define KFE$M_AUTHPRIV 0x1#define KFE$M_ARB_SUPPORT 0x2#define KFE$M_GLX_WRITE 0x4#define KFE$M_GLX_IDENT 0x8#define KFE$M_ELF 0x10#define KFE$M_SHARE_ADDR 0x20# 4#define KFE$M_RSRVD_6_31 0xFFFFFFC0P#define KFE$K_LENGTH 144 /* Length of fixed area of KFE entry */P#define KFE$C_LENGTH 144 /* Length of fixed area of KFE entry */N/* Count of flags used */N#define KFE$K_NUMBER_OF_FLAGS 22 /* Number of flag bits used. */N#define KFE$S_KFEDEF 144 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes * 4/ struct _kfd; struct _wcb; struct _ihd;struct _ldrimg; struct _orb;struct _kferes; #endif /* #ifdef __cplusplus */ typedef struct _kfe {N void *kfe$l_hshlnk; /* Known file Hash table link */P struct _kfe *kfe$l_kfelink; /* Ordered Known file entry list link */N unsigned short int kfe$w_size; /* Size of block */N unsigned char kfe$b_type; /* Structure type */a unsigned char kfe$b_hs!4hidx; /* KFE hash table index (index into vector of HSHQ's) */N struct _kfd *kfe$l_kfd; /* Device, Directory, Type block */ __union {N unsigned short int kfe$w_flags; /* Flags word */ __struct {Q unsigned kfe$v_protect : 1; /* Known file was installed protected */N unsigned kfe$v_lim : 1; /* Linkable image */N unsigned kfe$v_procpriv : 1; /* Use process privilege mask"4 */N unsigned kfe$v_open : 1; /* Image installed /OPEN */N unsigned kfe$v_hdrres : 1; /* Image header block is resident */N unsigned kfe$v_shared : 1; /* Image is shared */W unsigned kfe$v_kfe_naming : 1; /* use KFE based name for global sections */N unsigned kfe$v_compress : 1; /* Image sections are compressed */N unsigned kfe$v_nopurge : 1; /* Image entry may not be purged */N #4 unsigned kfe$v_account : 1; /* Image level accounting */N unsigned kfe$v_writeable : 1; /* Global sections are writeable */S unsigned kfe$v_exeonly : 1; /* Image has only execute access allowed */O unsigned kfe$v_discontiguous : 1; /* Image has resident sections */N unsigned kfe$v_delete_pend : 1; /* Delete pending on KFE */] unsigned kfe$v_version_safe : 1; /* Image is exempt from system version checks */^ $4 unsigned kfe$v_data_resident : 1; /* Image has resident read-only data sections */ } kfe$r_flags_bits; } kfe$r_flags_overlay;N unsigned short int kfe$w_gblseccnt; /* Global section count if shared */N unsigned int kfe$l_usecnt; /* Usage counter */ __union {N struct _wcb *kfe$l_wcb; /* WCB address if open */ __struct { __union {N unsigned short int kfe$w_fid; /* F %4ile id */U unsigned short int kfe$w_fid_num; /* File number field of file id */$ } kfe$r_fid_overlay;Z unsigned short int kfe$w_fid_seq; /* File sequence number field of file id */" } kfe$r_window_fields; } kfe$r_window_overlay; __union {O struct _ihd *kfe$l_imghdr; /* Image header address if resident */O struct _ldrimg *kfe$l_ldrimg; /* Pointer to IMGHDR (if ELF format) */X &4unsigned short int kfe$w_fid_rvn; /* Relative volume number field of file id */ } kfe$r_imghdr_overlay;N unsigned __int64 kfe$q_procpriv; /* Process privilege mask */N unsigned char kfe$b_matchctl; /* Global section match control */N char kfedef$$_fill_4; /* spare byte */O unsigned short int kfe$w_amecod; /* Image header code specifying AME */N unsigned int kfe$l_ident; /* Global section ident valu'4e */N struct _orb *kfe$l_orb; /* Address of Object Rights Block */N unsigned short int kfe$w_shrcnt; /* High water mark for sharing */b unsigned short int kfe$w_maxshrisd; /* Highest ISD number for which a global section exists */V struct _kferes *kfe$l_kferes_ptr; /* Pointer to resident section description */N unsigned int kfe$l_ref_count; /* Reference count */N unsigned int kfe$l_priv_isd_cnt; /* Private, non-stack ISDs (4 */j unsigned int kfe$l_image_size; /* Size in bytes of installed image (if image header is opened) */N/* FILNAMLEN and FILNAM are now obsolete. Do not use them. Use IMAGENAME */N unsigned int kfe$l_obsolete_1; /* Shifted Off the Layout */\ unsigned int kfe$l_imagename_offset; /* Offset to Counted String of file (image) name */ __union {N unsigned int kfe$l_flags2; /* Overflow Flags longword */ __struct {N )4unsigned kfe$v_authpriv : 1; /* Authorized privs used */T unsigned kfe$v_arb_support : 1; /* An arb_support value was specified */N unsigned kfe$v_glx_write : 1; /* installed /write=galaxy */N unsigned kfe$v_glx_ident : 1; /* installed /write=galaxy=ident */N unsigned kfe$v_elf : 1; /* image is ELF format (IA64) */N unsigned kfe$v_share_addr : 1; /* installed /share=address_data */N unsigned kfe$v_rsrvd*4_6_31 : 26; /* The unused bits */ } kfe$r_flags2_bits; } kfe$r_flags2_overlay;N void *kfe$ar_authrights; /* Image authorized rights */N void *kfe$ar_rights; /* Image active rights (initial) */N unsigned int kfe$l_arb_support; /* ARB support compatibility flag */N unsigned __int64 kfe$q_authpriv; /* Image authorized privileges */R unsigned int kfe$l_risig_offset; /* Offset to referenced image +4signature */X unsigned short int kfe$w_filver; /* file version number, used for INSTALL LIST */N short int kfedef$$_fill_5; /* spare word */N __struct { /* Image signature */N char kfe$t_dvi [16]; /* Device ID */V unsigned __int64 kfe$q_file_id; /* FID (even if the file is installed OPEN) */N unsigned int kfe$l_process_base; /* Process space base address ,4 */N unsigned int kfe$l_system_base; /* System space base address */ } kfe$r_risig; } KFE; #if !defined(__VAXC)3#define kfe$w_flags kfe$r_flags_overlay.kfe$w_flags=#define kfe$r_flags_bits kfe$r_flags_overlay.kfe$r_flags_bits4#define kfe$v_protect kfe$r_flags_bits.kfe$v_protect,#define kfe$v_lim kfe$r_flags_bits.kfe$v_lim6#define kfe$v_procpriv kfe$r_flags_bits.kfe$v_procpriv.#define kfe$v_open kfe$r_flags_bits.kfe$v_open2#define kfe$v_hdrres kfe$r_flags_bit -4s.kfe$v_hdrres2#define kfe$v_shared kfe$r_flags_bits.kfe$v_shared:#define kfe$v_kfe_naming kfe$r_flags_bits.kfe$v_kfe_naming6#define kfe$v_compress kfe$r_flags_bits.kfe$v_compress4#define kfe$v_nopurge kfe$r_flags_bits.kfe$v_nopurge4#define kfe$v_account kfe$r_flags_bits.kfe$v_account8#define kfe$v_writeable kfe$r_flags_bits.kfe$v_writeable4#define kfe$v_exeonly kfe$r_flags_bits.kfe$v_exeonly@#define kfe$v_discontiguous kfe$r_flags_bits.kfe$v_discontiguous<#define kfe$v_delete_pend kfe$r_flag .4s_bits.kfe$v_delete_pend>#define kfe$v_version_safe kfe$r_flags_bits.kfe$v_version_safe@#define kfe$v_data_resident kfe$r_flags_bits.kfe$v_data_resident0#define kfe$l_wcb kfe$r_window_overlay.kfe$l_wcbD#define kfe$r_window_fields kfe$r_window_overlay.kfe$r_window_fields?#define kfe$r_fid_overlay kfe$r_window_fields.kfe$r_fid_overlay-#define kfe$w_fid kfe$r_fid_overlay.kfe$w_fid5#define kfe$w_fid_num kfe$r_fid_overlay.kfe$w_fid_num7#define kfe$w_fid_seq kfe$r_window_fields.kfe$w_fid_seq6#d /4efine kfe$l_imghdr kfe$r_imghdr_overlay.kfe$l_imghdr6#define kfe$l_ldrimg kfe$r_imghdr_overlay.kfe$l_ldrimg8#define kfe$w_fid_rvn kfe$r_imghdr_overlay.kfe$w_fid_rvn6#define kfe$l_flags2 kfe$r_flags2_overlay.kfe$l_flags2@#define kfe$r_flags2_bits kfe$r_flags2_overlay.kfe$r_flags2_bits7#define kfe$v_authpriv kfe$r_flags2_bits.kfe$v_authpriv=#define kfe$v_arb_support kfe$r_flags2_bits.kfe$v_arb_support9#define kfe$v_glx_write kfe$r_flags2_bits.kfe$v_glx_write9#define kfe$v_glx_ident kfe$r_flag 04s2_bits.kfe$v_glx_ident-#define kfe$v_elf kfe$r_flags2_bits.kfe$v_elf;#define kfe$v_share_addr kfe$r_flags2_bits.kfe$v_share_addr;#define kfe$v_rsrvd_6_31 kfe$r_flags2_bits.kfe$v_rsrvd_6_31'#define kfe$t_dvi kfe$r_risig.kfe$t_dvi/#define kfe$q_file_id kfe$r_risig.kfe$q_file_id9#define kfe$l_process_base kfe$r_risig.kfe$l_process_base7#define kfe$l_system_base kfe$r_risig.kfe$l_system_base"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL14_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KFEDEF_LOADED */ wwk[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential 24proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/34M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************** 44*********************************************************************************************************/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SDL V3.7 */I/* Source: 18-APR-2008 15:21:59 $1$DGA8345:[LIB_H.SRC]KFERESDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KFERESDEF ***/#ifndef __KFERESDEF_LOADED#define __KFERESDEF_LOADED 1 G#pragma __nostandard /* This fi54le uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define 64__unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* KNOWN FILE ENTRY DEFINITIONS FOR RESIDENT SECTIONS */N/* 74 */N/* Note: The image activator also copies this structure and */I/* expands the structure to represent the image's data */I/* sections which have been compressed in process space. */N/* */#define KFERES$M_SHARE_LINK 0x1##define KFERES$M_64BIT_SECTIONS 0x2 #define KFERES$K_FIXED_LENGTH 32 #define KFERES$C_FIXED_LENGTH 32N#defin 84e KFERES$S_KFERESDEF 32 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _kfe; #endif /* #ifdef __cplusplus */ typedef struct _kferes {N struct _kfe *kferes$l_kfe; /* Back pointer to KFE */N unsigned int kferes$l_count; /* Count of resident sections */N unsigned short int kferes$w_size; /* Size of block */N unsigned char kferes$b_type; /* Str 94ucture type */N unsigned char kferes$b_subtype; /* Subtype */N unsigned int kferes$l_data_count; /* Count of data sections */N void *kferes$l_fixup_buffer; /* Pointer to fixup buffer */N unsigned int kferes$l_fixup_size; /* Size of fixup buffer */ __union {N unsigned int kferes$l_flags; /* Flags field */ __struct {W unsigned kferes$v_shar :4e_link : 1; /* Image is installed in a special way */N/* to gain maximum performance (linkage */N/* has been made shareable). */N unsigned kferes$v_64bit_sections : 1; /* 64-bit section records */* unsigned kferes$v_fill_0_ : 6;" } kferes$r_flags_bits;! } kferes$r_flags_overlay;Q void *kferes$l_start_address; /* For images installed with shareable */N/* linkage ;4, this is the starting P1 address */N char kferes$t_sections [4]; /* Offset to sections */N/* (needs an abitrary nonzero length for C) */ } KFERES; #if !defined(__VAXC)<#define kferes$l_flags kferes$r_flags_overlay.kferes$l_flagsF#define kferes$r_flags_bits kferes$r_flags_overlay.kferes$r_flags_bitsC#define kferes$v_share_link kferes$r_flags_bits.kferes$v_share_linkK#define kferes$v_64bit_section <4s kferes$r_flags_bits.kferes$v_64bit_sections"#endif /* #if !defined(__VAXC) */ N#define KFERES$K_COMPRESSED_DATA 0 /* For SDA use only */!#define KFERES$K_READ_ONLY_DATA 1#define KFERES$K_CODE 2#define KFERES$K_DZRO 3#define KFERES$K_WRT 4#define KFERES$K_LINKAGE 5N#define KFERES$K_RESIDENT_CODE 6 /* For SDA use only */N#define KFERES$K_RESIDENT_DATA 7 /* For SDA use only */N#define KFERES$K_UNKNOWN 8 =4 /* For SDA use only */#define KFERES$M_SHARESECT 0x1"#define KFERES$C_SECTION_LENGTH 24"#define KFERES$K_SECTION_LENGTH 24N#define KFERES$S_KFERESDEF_SECTION 24 /* Old size name - synonym */ typedef struct _kferes_section {N void *kferes$l_va; /* Starting VA */N unsigned int kferes$l_length; /* Length in bytes */N unsigned int kferes$l_vbn; /* Starting VBN in image file */N >4 void *kferes$l_image_offset; /* VA offset in image */N unsigned int kferes$l_section_type; /* Type of section */ __union {N unsigned int kferes$l_section_flags; /* Name attributes */ __struct {N unsigned kferes$v_sharesect : 1; /* Section is shareable */* unsigned kferes$v_fill_3_ : 7; } kferes$r_fill_2_; } kferes$r_fill_1_; } KFERES_SECTION; #if !defined(_ ?4_VAXC)F#define kferes$l_section_flags kferes$r_fill_1_.kferes$l_section_flagsO#define kferes$v_sharesect kferes$r_fill_1_.kferes$r_fill_2_.kferes$v_sharesect"#endif /* #if !defined(__VAXC) */ #define KFERES64$M_SHARESECT 0x1$#define KFERES64$C_SECTION_LENGTH 48$#define KFERES64$K_SECTION_LENGTH 48 &typedef struct _kferes_64bit_section {Q struct _kferes_64bit_section *kferes64$l_next; /* Pointer to next KFERES64 */N unsigned int kferes64$l_vbn; /* Starting VBN in image f @4ile */N unsigned short int kferes64$w_size; /* Size of block */N unsigned char kferes64$b_type; /* Structure type */N unsigned char kferes64$b_subtype; /* Subtype */N unsigned int kferes64$l_section_type; /* Type of section */ __union {N unsigned int kferes64$l_section_flags; /* Name attributes */ __struct {N unsigned kferes64$v_sharesect : 1; /* Sect A4ion is shareable */, unsigned kferes64$v_fill_6_ : 7;! } kferes64$r_fill_5_; } kferes64$r_fill_4_;N int kferes64$l_fill1; /* fill for quad alignment */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *kferes64$pq_va; /* Starting VA */#else! unsigned __int64 kfer B4es64$pq_va;#endifN unsigned __int64 kferes64$q_length; /* Length in bytes */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *kferes64$pq_image_offset; /* VA offset in image */#else+ unsigned __int64 kferes64$pq_image_offset;#endif } KFERES_64BIT_SECTION; #if !defined(__VAXC)L#define kferes64$l_section_flaC4gs kferes64$r_fill_4_.kferes64$l_section_flagsW#define kferes64$v_sharesect kferes64$r_fill_4_.kferes64$r_fill_5_.kferes64$v_sharesect"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KFERESDEF_LOADED */ D4 ww l[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/E4M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMSF4 Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SDL V3.7 */F/* Source: 20-APR-1993 14:01:13 $1$DGA8345:[LIB_H.SRC]KFHDEF.SDL;1 *//********************* G4***********************************************************************************************************//*** MODULE $KFHDEF ***/#ifndef __KFHDEF_LOADED#define __KFHDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr sizH4e */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union I4variant_union#endif#endif N/* */M/* KNOWN FILE IMAGE HEADER DEFINITIONS *** obsolete, to be removed *** */N/* */N#define KFH$K_LENGTH 12 /*LENGTH OF OVERHEAD AREA */N#define KFH$C_LENGTH 12 /*LENGTH OF OVERHEAD AREA */#define KFH$S_KFHDEF 12N/* J4 */  9#ifdef __cplusplus /* Define structure prototypes */ struct _kfe; #endif /* #ifdef __cplusplus */ typedef struct _kfh {Q void *kfh$l_bufend; /*ADDRESS OF END OF KNOWN FILE HEADER */T struct _kfe *kfh$l_kfiadr; /*ADDRESS OF ASSOCIATED KNOWN FILE ENTRY */N unsigned short int kfh$w_size; /*SIZE OF DYNAMIC STRUCTURE */N unsigned char kfh$b_type; /*DYNAMIC STRUCTURE TYPE K4*/N char kfhdef$$_fill_1; /*SPARE BYTE */N/* THE REMAINDER OF THIS STRUCTURE CONTAINS THE IMAGE HEADER OF THE */N/* SPECIFIED KNOWN FILE. THE LOCATION KFI$L_IMGHDR IN THE KNOWN FILE */N/* ENTRY POINTS KFH$C_LENGTH INTO THIS STRUCTURE, I.E AT THE IMAGE HEADER */N/* ITSELF. */N/* */ } KFH; $#pragmL4a __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KFHDEF_LOADED */ ww@_l[UM/***************************************************************************/M/** **/M/** M4HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDEN4NTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/******************************************************* O4********************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SDL V3.7 */F/* Source: 11-MAY-1993 16:52:48 $1$DGA8345:[LIB_H.SRC]KFIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KFIDEF ***/#ifndef __KFIDEF_LOADED#define __KFIDEF_LOADED 1 P4G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __opQ4tional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */G/* KNOWN FILE ENTRY DEFINITIONS *** obsolete, to be removed *** */N/* R4 */#define KFI$M_KFIHD 0x1#define KFI$M_FILIDOPEN 0x2#define KFI$M_DONOTOPEN 0x4#define KFI$M_NOREPLACE 0x40#define KFI$M_MARKDEL 0x80P#define KFI$K_KFIHDLEN 20 /*LENGTH OF KFI HEADER FIXED PORTION */P#define KFI$C_KFIHDLEN 20 /*LENGTH OF KFI HEADER FIXED PORTION */#define KFI$M_KFISEQ 0x3#define KFI$M_KP_OPEN 0x1#define KFI$M_KP_RESHDR 0x2#define KFI$M_KP_SHARED 0x4#defin S4e KFI$M_PROTECT 0x8#define KFI$M_LIM 0x40#define KFI$M_PROCPRIV 0x80#define KFI$M_IS_RESHDR 0x100#define KFI$M_IS_SHARED 0x200#define KFI$M_SHMIDENT 0x4000#define KFI$M_COMPATMOD 0x8000O#define KFI$K_LENGTH 52 /*LENGTH OF FIXED AREA OF KFI ENTRY */O#define KFI$C_LENGTH 52 /*LENGTH OF FIXED AREA OF KFI ENTRY */N#define KFI$S_KFIDEF 52 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure protot T4ypes */ struct _wcb; struct _ihd; #endif /* #ifdef __cplusplus */ typedef struct _kfi {N struct _kfi *kfi$l_kfiqfl; /*KNOWN FILE QUEUE FORWARD LINK */N struct _kfi *kfi$l_kfiqbl; /*KNOWN FILE QUEUE BACK LINK */N unsigned short int kfi$w_size; /*SIZE OF BLOCK */N unsigned char kfi$b_type; /*STRUCTURE TYPE */ __union {N unsigned char kfi$b_kfictl; /*CONTROL BITS U4 */ __struct {N unsigned kfi$v_kfihd : 1; /*KNOWN FILE HEADER BLOCK */N unsigned kfi$v_filidopen : 1; /*OPEN BY FILE ID IF SET */N unsigned kfi$v_donotopen : 1; /*DO NOT OPEN THE FILE IF SET */N unsigned kfidef$$_fill_1 : 3; /*SPARE */O unsigned kfi$v_noreplace : 1; /*DELETE AND DO NOT REPLACE ENTRY */N unsigned kfi$v_markdel : 1; /*ENTRY IS TO BE DELETED V4 */ } kfi$r_kfictl_bits; } kfi$r_kfictl_overlay; __union {N unsigned char kfi$b_devucb; /*DEVICE UCB OFFSET */N unsigned char kfi$b_devnam; /*NAME THE ABOVE CONSISTENTLY */ } kfi$r_devucb_overlay;N unsigned char kfi$b_dirnam; /*DIRECTORY NAME STRING OFFSET */N unsigned char kfi$b_filnam; /*FILE NAME STRING OFFSET */N unsigned char kfi$b_typnam; /*FILE TYPE STRING O W4FFSET */N unsigned short int kfi$w_refcnt; /*REFERENCE COUNT */W unsigned char kfi$b_kfiqnum; /*KFIQ NUMBER (INDEX INTO VECTOR OF KFIQ'S) */ __union {N unsigned char kfi$b_kfiseq; /*KNOWN FILE ENTRY SEQUENCE NUMBER */ __struct {N unsigned kfi$v_kfiseq : 2; /*SEQUENCE NUMBER FIELD */' unsigned kfi$v_fill_0_ : 6; } kfi$r_kfiseq_bits; } kfi$r_kfiseq_overlay; __unX4ion {N unsigned short int kfi$w_flags; /*FLAGS WORD */ __struct {N unsigned kfi$v_kp_open : 1; /*KEEP THE IMAGE FILE OPEN */N unsigned kfi$v_kp_reshdr : 1; /*MAKE IMAGE HEADER RESIDENT */N unsigned kfi$v_kp_shared : 1; /*MAKE IMAGE SHARED */P unsigned kfi$v_protect : 1; /*KNOWN FILE WAS INSTALLED PROTECTED */N unsigned kfidef$$_fill_2 : 2; /*SPARE BITS Y4 */N unsigned kfi$v_lim : 1; /*LINKABLE IMAGE */N unsigned kfi$v_procpriv : 1; /*USE PROCESS PRIVILEGE MASK */N unsigned kfi$v_is_reshdr : 1; /*IMAGE HEADER BLOCK IS RESIDENT */N unsigned kfi$v_is_shared : 1; /*IMAGE IS SHARED */N unsigned kfidef$$_fill_3 : 4; /*SPARE BITS */N unsigned kfi$v_shmident : 1; /*SHARED MEMORY IDENT ALREADY SET */N unsigned Z4 kfi$v_compatmod : 1; /*IMAGE IS COMPATABILITY MODE */ } kfi$r_flags_bits; } kfi$r_flags_overlay;N unsigned short int kfi$w_gblseccnt; /*GLOBAL SECTION COUNT IF SHARED */N unsigned int kfi$l_usecnt; /*USAGE COUNTER */ __union {N struct _wcb *kfi$l_window; /*WCB ADDRESS IF OPEN */ __struct { __union {N unsigned short int kfi$w_fid; /*FILE ID */ [4T unsigned short int kfi$w_fid_num; /*FILE NUMBER FIELD OF FILE ID */$ } kfi$r_fid_overlay;Y unsigned short int kfi$w_fid_seq; /*FILE SEQUENCE NUMBER FIELD OF FILE ID */" } kfi$r_window_fields; } kfi$r_window_overlay; __union {N struct _ihd *kfi$l_imghdr; /*IMAGE HEADER ADDRESS IF RESIDENT */W unsigned short int kfi$w_fid_rvn; /*RELATIVE VOLUME NUMBER FIELD OF FILE ID */ } kfi$r_imghdr_overlay; \4N unsigned __int64 kfi$q_procpriv; /*PROCESS PRIVILEGE MASK */N unsigned char kfi$b_matchctl; /*GLOBAL SECTION MATCH CONTROL */N char kfidef$$_fill_4; /*SPARE BYTE */N unsigned short int kfi$w_amecod; /*IMAGE HEADER CODE SPECIFYING AME */N unsigned int kfi$l_ident; /*GLOBAL SECTION IDENT VALUE */ } KFI; #if !defined(__VAXC)6#define kfi$b_kfictl kfi$r_kfictl_overlay.kfi$b_kfictlF#define kf]4i$v_kfihd kfi$r_kfictl_overlay.kfi$r_kfictl_bits.kfi$v_kfihdN#define kfi$v_filidopen kfi$r_kfictl_overlay.kfi$r_kfictl_bits.kfi$v_filidopenN#define kfi$v_donotopen kfi$r_kfictl_overlay.kfi$r_kfictl_bits.kfi$v_donotopenN#define kfi$v_noreplace kfi$r_kfictl_overlay.kfi$r_kfictl_bits.kfi$v_noreplaceJ#define kfi$v_markdel kfi$r_kfictl_overlay.kfi$r_kfictl_bits.kfi$v_markdel6#define kfi$b_devucb kfi$r_devucb_overlay.kfi$b_devucb6#define kfi$b_devnam kfi$r_devucb_overlay.kfi$b_devnam6#define kfi$b_kf^4iseq kfi$r_kfiseq_overlay.kfi$b_kfiseqH#define kfi$v_kfiseq kfi$r_kfiseq_overlay.kfi$r_kfiseq_bits.kfi$v_kfiseq3#define kfi$w_flags kfi$r_flags_overlay.kfi$w_flagsH#define kfi$v_kp_open kfi$r_flags_overlay.kfi$r_flags_bits.kfi$v_kp_openL#define kfi$v_kp_reshdr kfi$r_flags_overlay.kfi$r_flags_bits.kfi$v_kp_reshdrL#define kfi$v_kp_shared kfi$r_flags_overlay.kfi$r_flags_bits.kfi$v_kp_sharedH#define kfi$v_protect kfi$r_flags_overlay.kfi$r_flags_bits.kfi$v_protect@#define kfi$v_lim kfi$r_flags_over_4lay.kfi$r_flags_bits.kfi$v_limJ#define kfi$v_procpriv kfi$r_flags_overlay.kfi$r_flags_bits.kfi$v_procprivL#define kfi$v_is_reshdr kfi$r_flags_overlay.kfi$r_flags_bits.kfi$v_is_reshdrL#define kfi$v_is_shared kfi$r_flags_overlay.kfi$r_flags_bits.kfi$v_is_sharedJ#define kfi$v_shmident kfi$r_flags_overlay.kfi$r_flags_bits.kfi$v_shmidentL#define kfi$v_compatmod kfi$r_flags_overlay.kfi$r_flags_bits.kfi$v_compatmod6#define kfi$l_window kfi$r_window_overlay.kfi$l_windowV#define kfi$w_fid kfi$r_window_o `4verlay.kfi$r_window_fields.kfi$r_fid_overlay.kfi$w_fid^#define kfi$w_fid_num kfi$r_window_overlay.kfi$r_window_fields.kfi$r_fid_overlay.kfi$w_fid_numL#define kfi$w_fid_seq kfi$r_window_overlay.kfi$r_window_fields.kfi$w_fid_seq6#define kfi$l_imghdr kfi$r_imghdr_overlay.kfi$l_imghdr8#define kfi$w_fid_rvn kfi$r_imghdr_overlay.kfi$w_fid_rvn"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported a4*/b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KFIDEF_LOADED */ ww`l[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enteb4rprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and ic4s not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************************** d4*****************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */G/* Source: 20-APR-1993 14:03:49 $1$DGA8345:[LIB_H.SRC]KFPBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KFPBDEF ***/#ifndef __KFPBDEF_LOADED#define __KFPBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save4e#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __f4struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* KNOWN FILE POINTER BLOCK DEFINITIONS */N/* */N#define KFPB$K_LENGTH 16 g4 /* Length of pointer block */N#define KFPB$C_LENGTH 16 /* Length of pointer block */#define KFPB$S_KFPBDEF 16  9#ifdef __cplusplus /* Define structure prototypes */ struct _kfd; #endif /* #ifdef __cplusplus */ typedef struct _kfpb {Z struct _kfd *kfpb$l_kfdlst; /* Device, Directory, Extension (KFD) list link */S void *kfpb$l_kfehshtab; /* Address of Known file name hash table */N unsigned short i h4nt kfpb$w_size; /* Size of pointer block in bytes */N unsigned char kfpb$b_type; /* Pointer block type */N unsigned char kfpb$b_spare; /* spare byte */N unsigned short int kfpb$w_kfdlstcnt; /* Number of entries in KFD list */N unsigned short int kfpb$w_hshtablen; /* Length of Hash table */ } KFPB; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas i4supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KFPBDEF_LOADED */ wwl[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-j4Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software,k4 Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************** l4*****************************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */F/* Source: 19-APR-1993 14:37:38 $1$DGA8345:[LIB_H.SRC]KFPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $KFPDEF ***/#ifndef __KFPDEF_LOADED#define __KFPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignmem4nt __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #in4fndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */K/* KNOWN FILE POINTER BLOCK DEFINITIONS *** obsolete, to be removed *** */N/* */#define KFP$S_KFPD o4EF 16 typedef struct _kfp {R unsigned char kfp$b_quecount; /*INDEX OF LAST KNOWN FILE LIST IN USE */N char kfpdef$$_fill_1; /*SPARE BYTE */N short int kfpdef$$_fill_2; /*SPARE WORD */N int kfpdef$$_fill_3; /*SPARE LONG WORD */N unsigned short int kfp$w_size; /*SIZE OF POINTER BLOCK IN BYTES */N unsigned char kfp$b_type; /*POINTER BLOCK TYPE p4 */N unsigned char kfp$b_type1; /*TYPE OF STRUCTURE POINTED TO */N unsigned int kfp$l_que0; /*POINTER TO KNOWN FILE QUEUE 0 */ } KFP; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KFPDEF_LOADED q4*/ ww"m[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. r4**/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyrights4 VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */G/* Source: 11-MAY-1993 16:59:08 $1$DGA8345:[LIB_H.SRC]KFRHDEF.SDL;1 *//*************** t4*****************************************************************************************************************//*** MODULE $KFRHDEF ***/#ifndef __KFRHDEF_LOADED#define __KFRHDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined requiredu4 ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define v4__union variant_union#endif#endif N/* */N/* KNOWN FILE RESIDENT IMAGE HEADER DEFINITIONS */N/* */N#define KFRH$K_LENGTH 12 /* Length of overhead area */N#define KFRH$C_LENGTH 12 /* Length of overhead area */N#define KFRH$S_KFRHDEF 12 /* Old size name - syn w4onym */N/* */ typedef struct _kfrh {R void *kfrh$l_bufend; /* Address of end of known file header */N unsigned short int kfrh$w_alias; /* Use secondary name on activation */N short int kfrhdef$$_fill_1; /* SPARE BYTE */N unsigned short int kfrh$w_size; /* Size of dynamic structure */N unsigned char kfrh$b_type; /* Dynamic struc x4ture type */N unsigned char kfrh$b_hdrver; /* Image header version */#if defined(__VAXC) char kfrh$t_ihd[];#elseQ/* Warning: empty char[] member for kfrh$t_ihd at end of structure not created */"#endif /* #if defined(__VAXC) */N/* THE REMAINDER OF THIS STRUCTURE CONTAINS THE IMAGE HEADER OF THE */N/* SPECIFIED KNOWN FILE. THE LOCATION KFE$L_IMGHDR IN THE KNOWN FILE */N/* ENTRY POINTS KFRH$C_LENGTH INTO THIS STRUCTURE, I.E AT THE IMAGE y4HEADER */N/* ITSELF. */N/* */ } KFRH; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KFRHDEF_LOADED z4 */ wwIm[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. {4 **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyrig|4ht VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:37 by OpenVMS SDL V3.7 */F/* Source: 18-NOV-2021 16:02:59 $1$DGA8345:[LIB_H.SRC]KPBDEF.SDL;1 *//*************** }4*****************************************************************************************************************//*** MODULE $KPBDEF ***/#ifndef __KPBDEF_LOADED#define __KPBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required p~4tr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __ 4union variant_union#endif#endif N/*+ */N/* KPB - Kernel Process Block */N/* */N/* The Kernel Process Block contains the saved registers, state and */N/* stack pointer for a kernel process. */N/* 4 */N/* The KPB consists of 5 areas: */N/* */B/* 1 Base, */B/* 2a Scheduling, */B/* 2b VMS Special Parameters, */B/* 3 Spinlock, */B/* 4 Debug, and 4 */B/* 5 General Parameters */N/* */P/* The KPB can be used in one of two general types: the VMS executive sofware */N/* type (VEST) and the fully general type (FGT). */N/* */O/* In the VEST KPB, the relationship of KPB sections 1 thru 3 are fixed into */N/* the relationship show4n in this structure defintion file. Since the */N/* relationships between the VEST KPB fields are fixed, all major fields */N/* can be addressed relative to a single pointer register. This reduces */N/* the number of indirect reference operations and increases performance. */N/* The penality for the improved performance is a non-dynamic structure */N/* format. In VEST KPBs, the Spinlock area is optional. This causes the */N/* Debug area to be variably located. Typically, 4VEST KPBs do not use the */N/* General Parameters area. */N/* */N/* In the FGT KPB, only the KPB Base section has the format described in */N/* this structure definition file. In addition, the KPB VMS Special */N/* Parameters section is not present in FGT KPBs. Since the KPB Base size */O/* is fixed, the KPB Scheduling section can be referenced using offsets from4 */N/* the KPB base pointer register. All other sections are variable sized, */N/* and must be referenced through the pointers provided in the KPB Base. */N/* */N/* *NB* - The length of each integer numbered area above is rounded to an */I/* integral number of quadwords. */N/* */N/* This module also symb 4olically defines the flags parameter value calls */N/* to EXE$KP_ALLOCATE_KPB. */N/* */N/*- */  F#include /* Define the TQE type; UCB contains a pointer */F#include /* Define the FKB type; UCB contains a pointer */N#define KPBDBG$K_PC_VEC_CNT 8 /* Size of PC vect 4or */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _kpbdbg {#pragma __nomember_alignmentN unsigned int kpbdbg$is_start_time; /* Time of last start/restart */N unsigned int kpbdbg$is_start_count; /* Count of STARTs */N unsigned int kpbdbg$is_restart_count; /* Count of RESTARTs 4 */N unsigned int kpbdbg$is_vec_index; /* PC vector index */N int (*kpbdbg$is_pc_vec [8])(); /* PC trace vector */ } KPBDBG;N#define KPBDBG$K_LENGTH 48 /* Length of KPB Debug section */Y#define KPBDBG$S_KPBDBGDEF 48 /* Old size name, synonym for KPBDBG$S_KPBDBG */ N/* Bliss complains about there being two definitions for SPL_CTX$V_VALID, */N/* so this structure is only defined for all the langauages I can fi 4nd */N/* which are not Bliss variants */#define SPL_CTX$M_FORK 0x1#define SPL_CTX$M_PORT 0x2#define SPL_CTX$M_DYN 0x4#define SPL_CTX$M_SPL_BITS 7N/* Keep NOT_REL bits in same relative */P#define SPL_CTX$V_NOT_REL 4 /* Bit-shift for not-releaseable bits */##define SPL_CTX$M_FORK_NOT_REL 0x10##define SPL_CTX$M_PORT_NOT_REL 0x20"#define SPL_CTX$M_DYN_NOT_REL 0x40"#define SPL_CTX$M_NOT_REL_4BITS 112N/* These parameter bits may or may not be stored */#define SPL_CTX$M_MIN 0x100#define SPL_CTX$M_MIN_OK 0x200 #define SPL_CTX$M_PARAM_BITS 768N#define SPL_CTX$V_VALID 30 /* Bit-shift for valid bit */"#define SPL_CTX$M_VALID 0x40000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifNtypedef st4ruct _spl_ctx { /* X-28 */#pragma __nomember_alignmentN unsigned spl_ctx$v_fork : 1; /* Fork spinlock owned */N unsigned spl_ctx$v_port : 1; /* Port spinlock owned */N unsigned spl_ctx$v_dyn : 1; /* Dynamic spinlock owned */N unsigned spl_ctx$v_rsvd0 : 1; /* Fill out nibble */N/* order as the spinlock bits above */O un4signed spl_ctx$v_fork_not_rel : 1; /* Fork spinlock is not releaseable */O unsigned spl_ctx$v_port_not_rel : 1; /* Port spinlock is not releaseable */Q unsigned spl_ctx$v_dyn_not_rel : 1; /* Dynamic spinlock is not releaseable */N unsigned spl_ctx$v_rsvd1 : 1; /* Fill out nibble */P unsigned spl_ctx$v_min : 1; /* Establish minimum spinlock context */] unsigned spl_ctx$v_min_ok : 1; /* Establish minimum spinlock context if possible */N un 4signed spl_ctx$v_rsvd2 : 2; /* Fill out nibble */N unsigned spl_ctx$v_rsvd3 : 18; /* Clear to just under LW sign bit */T unsigned spl_ctx$v_valid : 1; /* To avoid treating an SVA as a SPL_CTX, */N/* negative SPL_CTX values are invalid */# unsigned spl_ctx$v_fill_0_ : 1; } SPL_CTX;  9#ifdef __cplusplus /* Define structure prototypes */ struct _spl; #endif /* #ifdef __cplusplus */ c#if !defined 4(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _kpbspl {#pragma __nomember_alignmentU void (*kpbspl$ps_spl_stall_rtn)(); /* Spinlock STALL handling routine pointer */W void (*kpbspl$ps_spl_restrt_rtn)(); /* Spinlock RESTART handling routine pointer */N/* X-28 */N struct _sp 4l *kpbspl$ps_spl_fork; /* Fork spinlock address */N struct _spl *kpbspl$ps_spl_port; /* Port spinlock address */N struct _spl *kpbspl$ps_spl_dyn; /* Dynamic spinlock address */ __union {N int kpbspl$l_ipl; /* IPL of all spinlocks as longword */ __struct {N unsigned char kpbspl$b_ipl; /* IPL of all spinlocks as byte */ } kpbspl$r_fill_2_; } kpbspl$r_fill_1_;N/* End IPL union 4 */N int kpbspl$l_saved_spl_ctx; /* Re/starter's spinlock context */\ int kpbspl$l_archived_spl_ctx; /* X-30 Spinlock contexts archived since re/start */N int kpbspl$l_req_spl_ctx; /* Requested spinlock context */N int kpbspl$l_fork_own_cnt; /* Fork SPL$L_OWN_COUNT on re/start */ } KPBSPL; #if !defined(__VAXC)2#define kpbspl$l_ipl kpbspl$r_fill_1_.kpbspl$l_iplC#define kpbspl$b 4_ipl kpbspl$r_fill_1_.kpbspl$r_fill_2_.kpbspl$b_ipl"#endif /* #if !defined(__VAXC) */ N#define KPBSPL$K_LENGTH 40 /* Length of KPB Spinlock section */Y#define KPBSPL$S_KPBSPLDEF 40 /* Old size name, synonym for KPBSPL$S_KPBSPL */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _kpbsch {#pragma __nomember_a4lignmentW void (*kpbsch$ps_sch_stall_rtn)(); /* Scheduling STALL handling routine pointer */Y void (*kpbsch$ps_sch_restrt_rtn)(); /* Scheduling RESTART handling routine pointer */N struct _fkb *kpbsch$ps_fkblk; /* pointer to a fork BLOCK */U void (*kpbsch$ps_sch_end_rtn)(); /* Scheduling END handling routine pointer */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#e 4lse#pragma __nomember_alignment#endif __union {( unsigned char kpbsch$b_fkb [48];#pragma __nomember_alignment __struct {N struct _fkb *kpbsch$ps_fqfl; /* fork queue flink */N struct _fkb *kpbsch$ps_fqbl; /* fork queue blink */N unsigned short int kpbsch$iw_fkb_size; /* fork block size */N unsigned char kpbsch$ib_fkb_type; /* fork block type */N unsigned char kpbsch 4$ib_flck; /* fork lock */N void (*kpbsch$ps_fpc)(); /* fork PC */N __int64 kpbsch$q_fr3; /* fork R3 */N __int64 kpbsch$q_fr4; /* fork R4 */ } kpbsch$r_fkb;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif 4( unsigned char kpbsch$b_tqe [64];#pragma __nomember_alignment __struct {N struct _tqe *kpbsch$ps_tqfl; /* timer queue flink */N struct _tqe *kpbsch$ps_tqbl; /* timer queue blink */N unsigned short int kpbsch$iw_tqe_size; /* TQE size */N unsigned char kpbsch$ib_tqe_type; /* TQE type */N unsigned char kpbsch$ib_rqtype; /* timer request type */N 4 void (*kpbsch$ps_tqe_fpc)(); /* timer routine pointer */N __int64 kpbsch$q_tqe_fr3; /* timer routine R3 */N __int64 kpbsch$q_tqe_fr4; /* timer routine R4 */N __int64 kpbsch$iq_time; /* timer due time */( __int64 kpbsch$q_fill_delta;# int kpbsch$l_fill_rmod;" int kpbsch$l_fill_efn;$ int kpbsch$l_fill_rqpid;% int kpbsch$l_fill_cputim; 4 } kpbsch$r_tqe; } kpbsch$r_sch_blocks; } KPBSCH; #if !defined(__VAXC)F#define kpbsch$ps_fqfl kpbsch$r_sch_blocks.kpbsch$r_fkb.kpbsch$ps_fqflF#define kpbsch$ps_fqbl kpbsch$r_sch_blocks.kpbsch$r_fkb.kpbsch$ps_fqblN#define kpbsch$iw_fkb_size kpbsch$r_sch_blocks.kpbsch$r_fkb.kpbsch$iw_fkb_sizeN#define kpbsch$ib_fkb_type kpbsch$r_sch_blocks.kpbsch$r_fkb.kpbsch$ib_fkb_typeF#define kpbsch$ib_flck kpbsch$r_sch_blocks.kpbsch$r_fkb.kpbsch$ib_flckD#define kpbsch$ps_fpc kpbsch4$r_sch_blocks.kpbsch$r_fkb.kpbsch$ps_fpcB#define kpbsch$q_fr3 kpbsch$r_sch_blocks.kpbsch$r_fkb.kpbsch$q_fr3B#define kpbsch$q_fr4 kpbsch$r_sch_blocks.kpbsch$r_fkb.kpbsch$q_fr4F#define kpbsch$ps_tqfl kpbsch$r_sch_blocks.kpbsch$r_tqe.kpbsch$ps_tqflF#define kpbsch$ps_tqbl kpbsch$r_sch_blocks.kpbsch$r_tqe.kpbsch$ps_tqblN#define kpbsch$iw_tqe_size kpbsch$r_sch_blocks.kpbsch$r_tqe.kpbsch$iw_tqe_sizeN#define kpbsch$ib_tqe_type kpbsch$r_sch_blocks.kpbsch$r_tqe.kpbsch$ib_tqe_typeJ#define kpbsch$ib_rqtype 4 kpbsch$r_sch_blocks.kpbsch$r_tqe.kpbsch$ib_rqtypeL#define kpbsch$ps_tqe_fpc kpbsch$r_sch_blocks.kpbsch$r_tqe.kpbsch$ps_tqe_fpcJ#define kpbsch$q_tqe_fr3 kpbsch$r_sch_blocks.kpbsch$r_tqe.kpbsch$q_tqe_fr3J#define kpbsch$q_tqe_fr4 kpbsch$r_sch_blocks.kpbsch$r_tqe.kpbsch$q_tqe_fr4F#define kpbsch$iq_time kpbsch$r_sch_blocks.kpbsch$r_tqe.kpbsch$iq_time"#endif /* #if !defined(__VAXC) */ N#define KPBSCH$K_LENGTH 80 /* Length of KPB Scheduling section */Y#define KPBSCH$S_KPBSCHDEF 80 4 /* Old size name, synonym for KPBSCH$S_KPBSCH */#define KP$M_VEST 0x4#define KP$M_SPLOCK 0x20#define KP$M_DEBUG 0x40!#define KP$M_DEALLOC_AT_END 0x100#define KP$M_SAVE_FP 0x1000$#define KP$M_SET_STACK_LIMITS 0x8000N#define KP$M_IO 292 /* The right flags for I/O */R#define KP$M_LKMGR 4 /* The right flags for the lock manager */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ *4/'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _kpflags {#pragma __nomember_alignment __union { int kp$is_flags; __struct {$ unsigned kp$v_fill1 : 2;N unsigned kp$v_vest : 1; /* KPB VEST format required */$ unsigned kp$v_fill2 : 2;N unsigned kp$v_splock : 1; /* Spinlock (3) area required */N unsigned kp$v_debug : 1; /* Debug (4 4) area present */$ unsigned kp$v_fill3 : 1;T unsigned kp$v_dealloc_at_end : 1; /* KP_END should call KP_DEALLOCATE */$ unsigned kp$v_fill4 : 3;] unsigned kp$v_save_fp : 1; /* Save FP registers on context switch (IA64 only) */$ unsigned kp$v_fill5 : 2;Z unsigned kp$v_set_stack_limits : 1; /* Call SETSTK_64 on every stack switch */$ unsigned kp$v_fill6 : 3;$ unsigned kp$v_fill7 : 2;N/* Verified for x8 46 port - Greg Jordan */, unsigned kp$v_fill_alphareg : 1;( unsigned kp$v_fill_rsvd : 8;( unsigned kp$v_fill_mode : 2; } kp$r_fill_4_; } kp$r_fill_3_; } KPFLAGS; #if !defined(__VAXC)5#define kp$v_vest kp$r_fill_3_.kp$r_fill_4_.kp$v_vest9#define kp$v_splock kp$r_fill_3_.kp$r_fill_4_.kp$v_splock7#define kp$v_debug kp$r_fill_3_.kp$r_fill_4_.kp$v_debugI#define kp$v_dealloc_at_end kp$r_fill_3_.k 4p$r_fill_4_.kp$v_dealloc_at_end;#define kp$v_save_fp kp$r_fill_3_.kp$r_fill_4_.kp$v_save_fpM#define kp$v_set_stack_limits kp$r_fill_3_.kp$r_fill_4_.kp$v_set_stack_limits"#endif /* #if !defined(__VAXC) */ V#define KP$S_KPDEF 4 /* Old size name, synonym for KP$S_KPFLAGS */#define KP$M_LOCK_MEM_STACK 0x1#define KP$M_LOCK_RSE_STACK 0x2#define KP$M_BOTH_STACKS 3 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'4#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _kplckflags {#pragma __nomember_alignment __union { int kp$is_lckflags; __struct {N unsigned kp$v_lock_mem_stack : 1; /* Lock main or memory stack */N unsigned kp$v_lock_rse_stack : 1; /* Lock RSE stack (IA64) */& unsigned kp$v_fill_7_ : 6; } kp$r_fill_6_; } kp$r_fill_5_; } KPLCKFLAGS; #if !defin 4ed(__VAXC)I#define kp$v_lock_mem_stack kp$r_fill_5_.kp$r_fill_6_.kp$v_lock_mem_stackI#define kp$v_lock_rse_stack kp$r_fill_5_.kp$r_fill_6_.kp$v_lock_rse_stack"#endif /* #if !defined(__VAXC) */ R#define KPB$K_MIN_IO_STACK 49152 /* Minimum I/O stack size in bytes IA64 */R#define KPB$K_MAX_MPW_STACK 8192 /* Maximum stack needed for page writes */#define KPB$M_VALID 0x1#define KPB$M_ACTIVE 0x2#define KPB$M_VEST 0x4#define KPB$M_DELETING 0x8#define KPB$M_SCHED 0x10#def4ine KPB$M_SPLOCK 0x20#define KPB$M_DEBUG 0x40#define KPB$M_PARAM 0x80"#define KPB$M_DEALLOC_AT_END 0x100 #define KPB$M_BYPASS_CACHE 0x200#define KPB$M_HLL_MASK 0x400"#define KPB$M_RESERVED_CACHE 0x800#define KPB$M_SAVE_FP 0x1000%#define KPB$M_MEM_STACK_LOCKED 0x2000%#define KPB$M_RSE_STACK_LOCKED 0x4000%#define KPB$M_SET_STACK_LIMITS 0x8000#define KPB$M_TQE_WAIT 0x10000#define KPB$M_FORK 0x20000#define KPB$M_FORK_WAIT 0x40000*#define KPB$M_SAVED_DEALLOC_AT_END 0x80000#defin 4e KPB$M_SPL_CTX 0x100000&#define KPB$M_ALPHAREG_LOCKED 0x200000#define KPB$M_RSVD 0x3FC00000#define KPB$M_ACMODE 0xC0000000##define KPB$M_STALL_CTX_BITS 458752N#define KPREG$K_MIN_REG_MASK 738258944 /* Minimum register mask */N#define KPREG$K_MIN_IO_REG_MASK 738259004 /* Min I/O register mask */N#define KPREG$K_ERR_REG_MASK -738263037 /* Error mask */N#define KPREG$K_HLL_REG_MASK 738263036 /* Default HLL mask */N#define KPB$K_LE 4NGTH 192 /* Length of KPB base section */#define KPB$K_TQE_LENGTH 64N/* length of TQE block */N#define KPB$K_NON_VEST_LENGTH 272 /* End of NON_VEST KPB offsets */N/* Begin VMS Special Parameters Area */#define KPB$K_KEEP 1#define KPB$K_RELEASE 2#define KPB$K_LOW 3#define KPB$K_HIGH 4N#define KPB$K_SCH_LENGTH 320 /* Length of KPB + SCH */4  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; struct _irp; struct _spl; struct _lkb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _kpb {#pragma __nomember_alignmentN struct _kpb *kpb$ps_flink; /* Forward link */N struct _kpb *kpb 4$ps_blink; /* Backward link */N unsigned short int kpb$iw_size; /* Structure size in bytes */N unsigned char kpb$ib_type; /* Structure type */N unsigned char kpb$ib_subtype; /* Structure subtype */N unsigned int kpb$is_stack_size; /* Stack size in bytes */N/* Verified for x86 port - Clair Grant */ __union { __union {N 4 unsigned int kpb$is_flags; /* Flags bitmask */ __struct {N unsigned kpb$v_valid : 1; /* KPB is valid */N unsigned kpb$v_active : 1; /* KPB is in active use */N unsigned kpb$v_vest : 1; /* KPB is VEST format */N unsigned kpb$v_deleting : 1; /* KPB is being deleted */N unsigned kpb$v_sched : 1; /* Scheduling (2) area present */N 4 unsigned kpb$v_splock : 1; /* Spinlock (3) area present */N unsigned kpb$v_debug : 1; /* Debug (4) area present */N unsigned kpb$v_param : 1; /* Parameter (5) area present */Y unsigned kpb$v_dealloc_at_end : 1; /* KP_END should call KP_DEALLOCATE */V unsigned kpb$v_bypass_cache : 1; /* Don't cache KPB on deallocation */P unsigned kpb$v_hll_mask : 1; /* Register mask is HLL_REG_MASK */O 4 unsigned kpb$v_reserved_cache : 1; /* Use reserved KPB cache */\ unsigned kpb$v_save_fp : 1; /* Caller requires FP state saved (IA64 only) */S unsigned kpb$v_mem_stack_locked : 1; /* Stack pages locked in WS */S unsigned kpb$v_rse_stack_locked : 1; /* Stack pages locked in WS */_ unsigned kpb$v_set_stack_limits : 1; /* Call SETSTK_64 on every stack switch */R unsigned kpb$v_tqe_wait : 1; /* X-28 Stalled by EXE$KP_TQE4_WAIT */N unsigned kpb$v_fork : 1; /* X-28 Stalled by EXE$KP_FORK */T unsigned kpb$v_fork_wait : 1; /* X-28 Stalled by EXE$KP_FORK_WAIT */| unsigned kpb$v_saved_dealloc_at_end : 1; /* X-28 Bit saved & cleared to force execution of KPB$PS_SCH_END */W unsigned kpb$v_spl_ctx : 1; /* X-28 KPB has been SPL_CTX-initialized */N/* Verified for x86 port - Greg Jordan */Z unsigned kpb$v_alp 4hareg_locked : 1; /* X86 Alpha Registers locked in WS */N unsigned kpb$v_rsvd : 8; /* Reserved for future flags */N unsigned kpb$v_acmode : 2; /* Original mode of KP */ } kpb$r_fill_9_; } kpb$r_fill_8_; } kpb$r_flags_overlay;N unsigned int kpb$is_reg_mask; /* Register save mask */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __ 4nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN void *kpb$ps_saved_sp; /* Previous stack pointer */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *kpb$pq_saved_sp; /* Previous stack pointer */#else" unsigned __int64 kpb$pq_saved_sp;#e 4ndif } kpb$r_save_sp_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *kpb$ps_stack_base; /* S 4tack base address */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *kpb$pq_stack_base; /* Stack base address */#else$ unsigned __int64 kpb$pq_stack_base;#endif# } kpb$r_stack_base_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_a 4lignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *kpb$ps_stack_sp; /* Current SP */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long / 4* And set ptr size default to 64-bit pointers */N void *kpb$pq_stack_sp; /* Current SP */#else" unsigned __int64 kpb$pq_stack_sp;#endif! } kpb$r_stack_sp_overlay;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *kpb$ps_sch_ptr; /* Address of SCH area */N void *kpb$ps_spl_p4tr; /* Address of SPL area */N void *kpb$ps_dbg_ptr; /* Address of DBG area */N void *kpb$ps_prm_ptr; /* Address of PRM area */N unsigned int kpb$is_prm_length; /* Length of PRM area */Q unsigned int kpb$is_rse_stack_length; /* Size of RSE backing store (bytes) */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_ali 4gnment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *kpb$pq_rse_stack_base; /* RSE backing store pointer */#else( unsigned __int64 kpb$pq_rse_stack_base;#endif#pragma __nomember_alignmentN unsigned __int64 kpb$q_region_id; /* Used for p2 allocations */R#ifdef __INITIAL 4_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *kpb$pq_prv_mem_base; /* returned by SETSTK_64 */#else& unsigned __int64 kpb$pq_prv_mem_base;#endifN unsigned __int64 kpb$q_prv_mem_len; /* returned by SETSTK_64 */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* An 4d set ptr size default to 64-bit pointers */N void *kpb$pq_prv_rse_base; /* returned by SETSTK_64 */#else& unsigned __int64 kpb$pq_prv_rse_base;#endifN unsigned __int64 kpb$q_prv_rse_len; /* returned by SETSTK_64 */N unsigned __int64 kpb$q_mem_region_id; /* Used for mem stack regions */N __int64 kpb$q_rsrvd_future [8]; /* Cells for future use */ R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported 4*/[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifW void (*kpb$ps_sch_stall_rtn)(); /* Scheduling STALL handling routine pointer */Y void (*kpb$ps_sch_restrt_rtn)(); /* Scheduling RESTART handling routine pointer */N struct _fkb *kpb$ps_fkblk; /* pointer to a fork block */U void (*kpb$ps_sch_end_rtn)(); /* Scheduling END handling routine pointer */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(_ 4_cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {% unsigned char kpb$b_fkb [48];#pragma __nomember_alignment __struct {N struct _fkb *kpb$ps_fqfl; /* fork queue flink */N struct _fkb *kpb$ps_fqbl; /* fork queue blink */N unsigned short int kpb$iw_fkb_size; /* fork block size */N unsign4ed char kpb$ib_fkb_type; /* fork block type */N unsigned char kpb$ib_flck; /* fork lock */N void (*kpb$ps_fpc)(); /* fork PC */N __int64 kpb$q_fr3; /* fork R3 */N __int64 kpb$q_fr4; /* fork R4 */ } kpb$r_fkb;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ * 4/'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif% unsigned char kpb$b_tqe [64];#pragma __nomember_alignment __struct {N struct _tqe *kpb$ps_tqfl; /* timer queue flink */N struct _tqe *kpb$ps_tqbl; /* timer queue blink */N unsigned short int kpb$iw_tqe_size; /* TQE size */N unsigned char kpb$ib_tqe_type; /* TQE type */N 4 unsigned char kpb$ib_rqtype; /* timer request type */N void (*kpb$ps_tqe_fpc)(); /* timer routine pointer */N __int64 kpb$q_tqe_fr3; /* timer routine R3 */N __int64 kpb$q_tqe_fr4; /* timer routine R4 */N __int64 kpb$iq_time; /* timer due time */% __int64 kpb$q_fill_delta; int kpb$l_fill_rmod; int kpb$l_fill_efn;! 4 int kpb$l_fill_rqpid;" int kpb$l_fill_cputim; } kpb$r_tqe; } kpb$r_sch_blocks;N/* (VEST KPB's only) */ __union { __struct {N struct _ucb *kpb$ps_ucb; /* UCB address */N struct _irp *kpb$ps_irp; /* IRP address */I/* vestioblks union fill; */ __struct {4O unsigned int kpb$is_timeout_time; /* WFI%%CH time out time */O unsigned int kpb$is_restore_ipl; /* WFI%%CH IPL to restore */U unsigned int kpb$is_channel_data; /* WFI%%CH/REQCHN channel data */ } kpb$r_iocblk; __struct {N void *kpb$ps_scsi_ptr1; /* SCSI gen. struc ptr #1 */N void *kpb$ps_scsi_ptr2; /* SCSI gen. struc ptr #2 */N void *kpb$ps_scs 4i_scdrp; /* SCSI transfer SCDRP addr. */ } kpb$r_scsiblk; __struct {N unsigned int kpb$is_timeout; /* time out time */N unsigned int kpb$is_newipl; /* IPL to restore */N struct _spl *kpb$ps_dlck; /* device spin lock */% } kpb$r_interruptblk; } kpb$r_vestio;I/* end vestio; */ __st 4ruct {N struct _lkb *kpb$ps_lkb; /* LKB address */ } kpb$r_vestlmgr; } kpb$r_vestprm;N char kpb$t_align_7 [4]; /* QUADWORD ALIGN */U void (*kpb$ps_spl_stall_rtn)(); /* Spinlock STALL handling routine pointer */W void (*kpb$ps_spl_restrt_rtn)(); /* Spinlock RESTART handling routine pointer */N/* X-28 */N struct _spl *kpb 4$ps_spl_fork; /* Fork spinlock address */N struct _spl *kpb$ps_spl_port; /* Port spinlock address */N struct _spl *kpb$ps_spl_dyn; /* Dynamic spinlock address */ __union {N int kpb$l_ipl; /* IPL of all spinlocks as longword */ __struct {N unsigned char kpb$b_ipl; /* IPL of all spinlocks as byte */ } kpb$r_fill_11_; } kpb$r_fill_10_;N/* End IPL union 4 */N int kpb$l_saved_spl_ctx; /* Re/starter's spinlock context */\ int kpb$l_archived_spl_ctx; /* X-30 Spinlock contexts archived since re/start */N int kpb$l_req_spl_ctx; /* Requested spinlock context */N int kpb$l_fork_own_cnt; /* Fork SPL$L_OWN_COUNT on re/start */ } KPB; #if !defined(__VAXC)C#define kpb$is_flags kpb$r_flags_overlay.kpb$r_fill_8_.kpb$is_flagsO#define kpb$4v_valid kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_validQ#define kpb$v_active kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_activeM#define kpb$v_vest kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_vestU#define kpb$v_deleting kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_deletingO#define kpb$v_sched kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_schedQ#define kpb$v_splock kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_splockO#define kpb$v_debu4g kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_debugO#define kpb$v_param kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_parama#define kpb$v_dealloc_at_end kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_dealloc_at_end]#define kpb$v_bypass_cache kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_bypass_cacheU#define kpb$v_hll_mask kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_hll_maska#define kpb$v_reserved_cache kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_4.kpb$v_reserved_cacheS#define kpb$v_save_fp kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_save_fpe#define kpb$v_mem_stack_locked kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_mem_stack_lockede#define kpb$v_rse_stack_locked kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_rse_stack_lockede#define kpb$v_set_stack_limits kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_set_stack_limitsU#define kpb$v_tqe_wait kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_tqe_wai4tM#define kpb$v_fork kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_forkW#define kpb$v_fork_wait kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_fork_waitm#define kpb$v_saved_dealloc_at_end kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_saved_dealloc_at_endS#define kpb$v_spl_ctx kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_spl_ctxc#define kpb$v_alphareg_locked kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_alphareg_lockedM#define kpb$v_rsvd kpb$r_flags_o4verlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_rsvdQ#define kpb$v_acmode kpb$r_flags_overlay.kpb$r_fill_8_.kpb$r_fill_9_.kpb$v_acmode=#define kpb$ps_saved_sp kpb$r_save_sp_overlay.kpb$ps_saved_sp=#define kpb$pq_saved_sp kpb$r_save_sp_overlay.kpb$pq_saved_spD#define kpb$ps_stack_base kpb$r_stack_base_overlay.kpb$ps_stack_baseD#define kpb$pq_stack_base kpb$r_stack_base_overlay.kpb$pq_stack_base>#define kpb$ps_stack_sp kpb$r_stack_sp_overlay.kpb$ps_stack_sp>#define kpb$pq_stack_sp kpb$r_stack_sp_ove 4rlay.kpb$pq_stack_sp:#define kpb$ps_fqfl kpb$r_sch_blocks.kpb$r_fkb.kpb$ps_fqfl:#define kpb$ps_fqbl kpb$r_sch_blocks.kpb$r_fkb.kpb$ps_fqblB#define kpb$iw_fkb_size kpb$r_sch_blocks.kpb$r_fkb.kpb$iw_fkb_sizeB#define kpb$ib_fkb_type kpb$r_sch_blocks.kpb$r_fkb.kpb$ib_fkb_type:#define kpb$ib_flck kpb$r_sch_blocks.kpb$r_fkb.kpb$ib_flck8#define kpb$ps_fpc kpb$r_sch_blocks.kpb$r_fkb.kpb$ps_fpc6#define kpb$q_fr3 kpb$r_sch_blocks.kpb$r_fkb.kpb$q_fr36#define kpb$q_fr4 kpb$r_sch_blocks.kpb$r_fkb.kpb$q_fr44:#define kpb$ps_tqfl kpb$r_sch_blocks.kpb$r_tqe.kpb$ps_tqfl:#define kpb$ps_tqbl kpb$r_sch_blocks.kpb$r_tqe.kpb$ps_tqblB#define kpb$iw_tqe_size kpb$r_sch_blocks.kpb$r_tqe.kpb$iw_tqe_sizeB#define kpb$ib_tqe_type kpb$r_sch_blocks.kpb$r_tqe.kpb$ib_tqe_type>#define kpb$ib_rqtype kpb$r_sch_blocks.kpb$r_tqe.kpb$ib_rqtype@#define kpb$ps_tqe_fpc kpb$r_sch_blocks.kpb$r_tqe.kpb$ps_tqe_fpc>#define kpb$q_tqe_fr3 kpb$r_sch_blocks.kpb$r_tqe.kpb$q_tqe_fr3>#define kpb$q_tqe_fr4 kpb$r_sch_blocks.kpb$r_tqe.kpb$q4_tqe_fr4:#define kpb$iq_time kpb$r_sch_blocks.kpb$r_tqe.kpb$iq_time8#define kpb$ps_ucb kpb$r_vestprm.kpb$r_vestio.kpb$ps_ucb8#define kpb$ps_irp kpb$r_vestprm.kpb$r_vestio.kpb$ps_irpW#define kpb$is_timeout_time kpb$r_vestprm.kpb$r_vestio.kpb$r_iocblk.kpb$is_timeout_timeU#define kpb$is_restore_ipl kpb$r_vestprm.kpb$r_vestio.kpb$r_iocblk.kpb$is_restore_iplW#define kpb$is_channel_data kpb$r_vestprm.kpb$r_vestio.kpb$r_iocblk.kpb$is_channel_dataR#define kpb$ps_scsi_ptr1 kpb$r_vestprm.kpb$r_vestio.4kpb$r_scsiblk.kpb$ps_scsi_ptr1R#define kpb$ps_scsi_ptr2 kpb$r_vestprm.kpb$r_vestio.kpb$r_scsiblk.kpb$ps_scsi_ptr2T#define kpb$ps_scsi_scdrp kpb$r_vestprm.kpb$r_vestio.kpb$r_scsiblk.kpb$ps_scsi_scdrpS#define kpb$is_timeout kpb$r_vestprm.kpb$r_vestio.kpb$r_interruptblk.kpb$is_timeoutQ#define kpb$is_newipl kpb$r_vestprm.kpb$r_vestio.kpb$r_interruptblk.kpb$is_newiplM#define kpb$ps_dlck kpb$r_vestprm.kpb$r_vestio.kpb$r_interruptblk.kpb$ps_dlck:#define kpb$ps_lkb kpb$r_vestprm.kpb$r_vestlmgr.kpb$ps 4_lkb*#define kpb$l_ipl kpb$r_fill_10_.kpb$l_ipl9#define kpb$b_ipl kpb$r_fill_10_.kpb$r_fill_11_.kpb$b_ipl"#endif /* #if !defined(__VAXC) */ N#define KPB$K_SPL_LENGTH 360 /* Length of KPB + SCH + SPL */R#define KPB$S_KPBDEF 360 /* Old size name, synonym for KPB$S_KPB */ #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Dtypedef 4struct _kpb * KPB_PQ; /* Pointer to a KPB structure. */Qtypedef struct _kpb ** KPB_PPQ; /* Pointer to a pointer to a KPB structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 KPB_PQ;!typedef unsigned __int64 KPB_PPQ;##endif /* __INITIAL_POINTER_SIZE */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_siz4e __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KPBDEF_LOADED */ wwm[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not4 **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized t4o be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************************************************* 4*******/=/* Created: 7-Oct-2024 15:22:36 by OpenVMS SDL V3.7 */J/* Source: 31-MAY-2022 07:54:24 $1$DGA8345:[LIB_H.SRC]KPSTACKDEF.SDL;1 *//********************************************************************************************************************************/&/*** MODULE $KPSTACKDEF IDENT X-6 ***/#ifndef __KPSTACKDEF_LOADED#define __KPSTACKDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma 4__nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if 4!defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* Compared to the IA64 one, the x86-64 KPSTACK record is simpler. */N/* It has no optional floating-point part and therefore no flags word. */N/* It does have space to save the Alpha pseudo-registers. */#define KPSTACK$K_LENGTH 80 c#i 4f !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _kpstack {#pragma __nomember_alignmentN unsigned short int kpstack$w_size; /* Structure size */N unsigned char kpstack$b_type; /* DYN$C_MISC */N unsigned char kpstack$b_subtype; /* DYN$C_KPSTACK */ int kpstack$l_fi 4ll;N __int64 kpstack$q_saved_rbx; /* Preserved general registers */ __int64 kpstack$q_saved_rbp; __int64 kpstack$q_saved_r12; __int64 kpstack$q_saved_r13; __int64 kpstack$q_saved_r14; __int64 kpstack$q_saved_r15;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */$ void *kpstack$pq_saved_alphareg;#else, unsigned __int64 kpstack$pq 4_saved_alphareg;#endif0 unsigned __int64 kpstack$q_saved_kstack_top;3 unsigned __int64 kpstack$q_saved_kstack_bottom; } KPSTACK;N/* KPSIG */R/* This is the layout of the base of a KP memory stack, which looks as follows: */N/* */N/* 0(SP) Scratch space for (sp at call to KP routine) */N/* 8(SP) called routine 4 */N/* 16(SP) Saved GP (caller's GP) */N/* 24(SP) 00000000.00000000 (alignment) */N/* 32(SP) 00000000.00000000 } */N/* 40(SP) 00000000.00000000 } signature expected by code */N/* 48(SP) DEADDEAD.DEADDEAD } */J/* 56(SP) KPB address (highest useable address) 4 */N/* [Guard Page] */N/* */Q/* The low 4 quads are used by the IA64 implementation. The high 4 quads are */N/* required by both the Alpha and IA64 code. */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __no 4member_alignment#endiftypedef struct _kpsig {#pragma __nomember_alignmentN unsigned __int64 kpsig$q_zero1; /* MBZ */N unsigned __int64 kpsig$q_zero2; /* MBZ */N unsigned __int64 kpsig$q_dead_sig; /* 0xDEADDEAD.DEADDEAD */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void4 *kpsig$pq_kpb; /* pointer to KPB */#else unsigned __int64 kpsig$pq_kpb;#endif } KPSIG; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KPSTACKDEF_LOADED */ ww n[UM/*************4**************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Ent4erprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. 4 **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */H/* Source: 25-MAR-2003 16:37:39 $1$DGA8345:[LIB_H.SRC]KRIPRDEF.SDL;1 *//************************************************************* 4*******************************************************************//*** MODULE $KRIPRDEF ***/#ifndef __KRIPRDEF_LOADED#define __KRIPRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_s4ize __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif 4N/*------------------------------------------------------------------- */N/* KRIPR - IPF Kernel Register Holding Emulated Processor Registers */N/* */#define KRIPR$M_IPL 0xFF#define KRIPR$M_PREVMODE 0xF00##define KRIPR$M_CURSTACKMODE 0xF000(#define KRIPR$M_INTERRUPT_DEPTH 0xFF0000 #define KRIPR$M_KT_ID 0xFF000000)#define KRIPR$M_FILL_6 0x3FFFFFFFFFFFFFFF3#define KRIPR$M_SWIS_DISABLE_LOG 0x400000000000040003#define KRIPR$M_SWIS_INHIBIT_LOG 0x8000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _kripr {#pragma __nomember_alignment __union {N __int64 kripr$q_quadword; /* Entire register */ __struct {d char kripr$b_ipl; /* IPL (needs only 5 bits, but unless 4we need more later, */N/* multiples of 4 bits makes it easier to read/debug */P char kripr$b_modes; /* PREVMODE and CURSTACKMODE together */r char kripr$b_interrupt_depth; /* Count the depths of interrupt state (see interrupt pending in SRM) */P char kripr$b_kt_id; /* Kernel thread id of current thread */ char kripr$b_fill_2; char kripr$b_fill_3; char kripr$b_fill_4; char kri4pr$b_flags; } kripr$r_bytes; __struct {d unsigned kripr$v_ipl : 8; /* IPL (needs only 5 bits, but unless we need more later, */a unsigned kripr$v_prevmode : 4; /* Previous mode. Needs only 2 bits, but (see IPL) */j unsigned kripr$v_curstackmode : 4; /* Current stack mode. Needs only 2 bits, but (see IPL) */z unsigned kripr$v_interrupt_depth : 8; /* Count the depths of interrupt state (see interrupt pending in SRM) */P 4 unsigned kripr$v_kt_id : 8; /* Kernel thread id of current thread */ } kripr$r_nibbles; __struct {+ unsigned kripr$v_fill_6_1 : 32;+ unsigned kripr$v_fill_6_2 : 30;2 unsigned kripr$v_swis_disable_log : 1;2 unsigned kripr$v_swis_inhibit_log : 1; } kripr$r_bits; } kripr$r_fields; } KRIPR; #if !defined(__VAXC)8#define kripr$q_quadword kripr$r_fields.kripr$q_quadword<#define kripr$b_ipl krip4r$r_fields.kripr$r_bytes.kripr$b_ipl@#define kripr$b_modes kripr$r_fields.kripr$r_bytes.kripr$b_modesT#define kripr$b_interrupt_depth kripr$r_fields.kripr$r_bytes.kripr$b_interrupt_depth@#define kripr$b_kt_id kripr$r_fields.kripr$r_bytes.kripr$b_kt_idB#define kripr$b_fill_2 kripr$r_fields.kripr$r_bytes.kripr$b_fill_2B#define kripr$b_fill_3 kripr$r_fields.kripr$r_bytes.kripr$b_fill_3B#define kripr$b_fill_4 kripr$r_fields.kripr$r_bytes.kripr$b_fill_4@#define kripr$b_flags kripr$r_fields.kripr$r_b4ytes.kripr$b_flags>#define kripr$v_ipl kripr$r_fields.kripr$r_nibbles.kripr$v_iplH#define kripr$v_prevmode kripr$r_fields.kripr$r_nibbles.kripr$v_prevmodeP#define kripr$v_curstackmode kripr$r_fields.kripr$r_nibbles.kripr$v_curstackmodeV#define kripr$v_interrupt_depth kripr$r_fields.kripr$r_nibbles.kripr$v_interrupt_depthB#define kripr$v_kt_id kripr$r_fields.kripr$r_nibbles.kripr$v_kt_idU#define kripr$v_swis_disable_log kripr$r_fields.kripr$r_bits.kripr$v_swis_disable_logU#define kripr$v_swis_i 4nhibit_log kripr$r_fields.kripr$r_bits.kripr$v_swis_inhibit_log"#endif /* #if !defined(__VAXC) */ N/****************************************************** */N/* */N/* The following constants define which kernel registers */N/* are used for what purpose. When you want to reference */N/* them, use KR$C_ in place of the register symbols supplied */N4/* by the language. For example, in C, you can access the */N/* SLOT_VA by saying */N/* */N/* __getReg(KR$C_SLOT_VA) */N/* */N/****************************************************** */c#define KR$C_SLOT_VA 3079 4 /* Here is the virtual address of the CPU slot structure */U#define KR$C_CPUDB_VA 3078 /* The virtual address of the CPU database */S#define KR$C_NEXT_TIMER 3077 /* The value of the next timer interrupt */l#define KR$C_KRIPR 3075 /* This register contains several different data as defined above */ @/* They must have included builtins.h if they were using this */#if (_IA64_REG_AR_KR0 != 3072)S#error KRIPRDEF assumes that _IA64_REG_AR_K04 is equal to 3072, and this is not true#endif $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __KRIPRDEF_LOADED */ ww[n[UM/***************************************************************************/M/** 4 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** 4 **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 4**/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LANDE 4F ***/#ifndef __LANDEF_LOADED#define __LANDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cpluspl4us extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* This stru4cture represents the LAN entity. There are medium-specific */N/* portions for CSMA/CD, FDDI, Token Ring and ATM. */N/*-- */ #define LAN$M_REG_VCI 0x1#define LAN$M_DAT_LOCK 0x2#define LAN$M_LAN_INIT 0x4#define LAN$M_CNM_INIT 0x8#define LAN$M_FNM_INIT 0x10#define LAN$M_TNM_INIT 0x20#define LAN$M_ANM_INIT 0x40##define LAN$M_HOT_REPLACE_DRVR 0x80#define LAN$M_C_REG_EMAA 0x1#def4ine LAN$M_C_CREATED 0x2#define LAN$M_C_WAIT 0x4#define LAN$M_F_REG_EMAA 0x1#define LAN$M_F_CREATED 0x2#define LAN$M_F_WAIT 0x4#define LAN$M_F_L_WAIT 0x8#define LAN$M_F_H_WAIT 0x10#define LAN$M_T_REG_EMAA 0x1#define LAN$M_T_CREATED 0x2#define LAN$M_A_REG_EMAA 0x1#define LAN$M_A_CREATED 0x2N#define LAN$C_TIMEOUT 1 /* 1 Device timeout */N#define LAN$C_XMTTMO 3 /* 3 Transmit timeout */N#define LAN$C_RCVLOCK 5 4 /* 5 Receiver Lockup */N#define LAN$C_POWERFAIL 7 /* 7 Device powerfail */N#define LAN$C_HARDWARE 9 /* 9 Device hardware error */N#define LAN$C_CONSRUNT 11 /* 11 Device Runt error (DEQNA) */N#define LAN$C_MISS 13 /* 13 MISS error (LANCE) */S#define LAN$C_INIT_FAILURE 15 /* 15 Initialization Failure (DEUNA/LUA) */N#define LAN$C_PORT_UNDEFINED 17 /* 17 Port4 Undefined (DEBNA/DEBNT) */N#define LAN$C_PORT_DISABLED 19 /* 19 Port Disabled (DEBNA/DEBNT) */R#define LAN$C_CCAFAILED 21 /* 21 Can Change Address attempt failed */N#define LAN$C_NM_DISABLED 23 /* 23 Network management disabled */N#define LAN$C_UPDATE 25 /* 25 Firmware update */N#define LAN$C_RESET 27 /* 27 Forced reset */N#define LAN$C_DEAD 29 /* 29 Forced dead 4 */N/* Timer constant for the LAN one second timer. */ #define LAN$C_TQE_DELTA 10000000N/* Define the common LAN driver function codes */N#define LAN$C_FC_INIT 0 /* Initialize LAN device */N#define LAN$C_FC_XMIT 1 /* Transmit request */N#define LAN$C_FC_RECV 2 /* Receive request */N#define LAN$C_FC_STOP 3 /* Stop port 4 */N#define LAN$C_FC_RDCNTS 4 /* Read counters */N#define LAN$C_FC_RCCNTS 5 /* Read and clear counters */N#define LAN$C_FC_CHNGPRO 6 /* Change channel */N#define LAN$C_FC_STRTPRO 7 /* Start channel */N#define LAN$C_FC_STRTPROPHA 8 /* Start channel with a new PHA */N#define LAN$C_FC_STOPPRO 9 /* Stop channel */N#define LA4N$C_FC_DIAG 10 /* Diagnostic function */N#define LAN$C_FC_SENSE_MAC 11 /* Sense Medium specific parameters */N#define LAN$C_FC_SET_MAC 12 /* Set Medium specific parameters */N#define LAN$C_FC_SET_FA 13 /* Set Functional Address mask */R#define LAN$C_FC_XMIT_CM 14 /* Internal (ATM) connection mgr packet */[#define LAN$C_FC_XMIT_PAD 15 /* Transmit packet that needs to be padded (ATM) */R#define LAN$C_FC_E 4NDDRVRI 16 /* End of driver independent func codes */N/* Define the common LAN diagnostic function codes */#define LAN$M_DIAG_STARTUP 64 #define LAN$M_DIAG_SET_TRACE 128!#define LAN$M_DIAG_READ_TRACE 256#define LAN$M_DIAG_READ_REV 512#define LAN$M_DIAG_ERASE 1024#define LAN$M_DIAG_READ_BW 1024#define LAN$V_DIAG_READ_BW 10%#define LAN$M_DIAG_READ_COUNTERS 2048!#define LAN$M_DIAG_READ_UCBS 4096#define LAN$M_DIAG_RESET 8192#define LAN$M_DIAG4_DEBUG 16384#define LAN$M_DIAG_SET_BW 32768#define LAN$V_DIAG_SET_BW 15N/* Notes on adding more LAN diagnostic function codes. */z#define LAN$V_DIAG_STARTUP 6 /* 2^6 = 64 Startup a new driver (Update/driver) (used with IO$M_STARTUP) */h#define LAN$V_DIAG_SET_TRACE 7 /* 2^7 = 128 Set trace parameters (used with IO$M_NOWAIT) */f#define LAN$V_DIAG_READ_TRACE 8 /* 2^8 = 256 Read trace data (used with IO$M_NOCLEANUP) */h#define LAN$V_4DIAG_READ_REV 9 /* 2^9 = 512 Read revision data (used with IO$M_NOBLOCK ) */`#define LAN$V_DIAG_ERASE 10 /* 2^10 = 1024 Clean up after error (Update/driver) */g#define LAN$V_DIAG_READ_COUNTERS 11 /* 2^11 = 2048 Read counters data (used with IO$M_REMOUNT) */`#define LAN$V_DIAG_READ_UCBS 12 /* 2^12 = 4096 Read UCB data (used with IO$M_CYCLE) */g#define LAN$V_DIAG_RESET 13 /* 2^13 = 8192 Issue a forced reset (used with IO$M_RESET) */b#defin4e LAN$V_DIAG_DEBUG 14 /* 2^14 = 16384 Issue a device-specific debug function */N#define LAN$V_DIAG_TRACE_ENTRY 15 /* 2^15 = 32768 Make a trace entry */V#define LAN$V_DIAG_TRACE_MERGE 16 /* 2^16 = 65536 Merge interrupt trace data */`#define LAN$V_DIAG_FCARP_TABLE 17 /* 2^17 = 131072 FC address resolution Protocol Table */S#define LAN$V_DIAG_VLAN_TABLE 18 /* 2^18 = 262144 Retrieve the VLAN table */^/* The next four entries are used for IPL8 code to communica 4te with LANCP by sending QASTs. */N#define LAN$K_LENGTH 832 /* Size of the LAN block */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _lan {N/* First get to the end of the user-visible LAN section. Then we will */N/* extend the LAN block for use by just the LAN drivers. */#pragma __no4member_alignment char lan$b_filler [24];N/* There are multiple sections to the LAN block. The first section is */N/* the section that is shared by all instances of the LAN module. This */N/* first section is device and medium independent. The subsequent sections */N/* are specific to a particular medium. */N/************************************************************************* */N/* LAN DRIVER COMMON SECTION 4 */N/************************************************************************* */ char lan$t_tqe [64];N/* TQE for the one second timer */ __union {! unsigned int lan$l_flags; __struct {N unsigned lan$v_reg_vci : 1; /* LAN is registered with VCI */N unsigned lan$v_dat_lock : 1; /* A Duplicate Address Test is in */N/* progress on one of this machine's 4 */N/* LAN devices */N unsigned lan$v_lan_init : 1; /* The LAN module has initialized */N/* its portion of the LAN block */P unsigned lan$v_cnm_init : 1; /* The CSMACD module has initialized */N/* its portion of the LAN block */N unsigned lan$v_fnm_init : 1; /* The FDDI module has initialized */N/* its p4ortion of the LAN block */N unsigned lan$v_tnm_init : 1; /* The TR module has initialized */N/* its portion of the LAN block */N unsigned lan$v_anm_init : 1; /* The ATM module has initialized */N/* its portion of the LAN block */Q unsigned lan$v_hot_replace_drvr : 1; /* A port driver is unloading */ } lan$r_fill_1_;4 } lan$r_fill_0_;O unsigned int lan$l_lsb; /* Linked list of LAN Station Blocks */N unsigned int lan$l_stactr; /* Number of stations */N unsigned int lan$l_lanudef_ver; /* LANUDEF version */N unsigned int lan$l_lanidef_ver; /* LANIDEF version */O void *lan$a_com_portlock; /* Address of LAN's common code lock */N unsigned int lan$l_reserved3; /* Reserved for future use 4*/N unsigned int lan$l_reserved4; /* Reserved for future use */N/* Common network management fields */O void *lan$a_findlsb; /* Find LSB; given Local Entity Name */N void *lan$a_new_eib; /* Latest EIB address */N __int64 lan$q_desc; /* A descriptor */N char lan$t_mca_item [12]; /* Storage area for a MCA set item */N/* Synchronization f4ield */N unsigned int lan$l_sequence; /* Sequence number (used for DAT) */N/************************************************************************* */N/* CSMACD SECTION */N/************************************************************************* */N/* Versions */N unsigned __int64 lan$q_c_nm_m_ver; /* NM 4MACRO version */N unsigned int lan$l_c_nm_c_ver0; /* NM C version */N unsigned int lan$l_c_nm_c_ver1; /* NM C version */N unsigned __int64 lan$q_c_nm_ev_ver; /* NM Event version */N/* Flags */ __union {# unsigned int lan$l_c_flags; __struct {O unsigned lan$v_c_reg_emaa : 1; /* Module is registered with EMAA 4 */N unsigned lan$v_c_created : 1; /* Module entity is CREATED */N unsigned lan$v_c_wait : 1; /* Module is waiting for the device */( unsigned lan$v_fill_10_ : 5; } lan$r_fill_3_; } lan$r_fill_2_;N int lan$l_extra_l_1; /* Preserve quadword alignment */N/* Time stamp fields (all values stored from ABSTIMTICS) */N unsigned int lan$l_c_cretim; /* Time the module was last created */N 5 unsigned int lan$l_c_deltim; /* Time the module was last deleted */N/* Counters (all counters are wrap) */P unsigned int lan$l_c_crectr; /* Number of times module was created */P unsigned int lan$l_c_delctr; /* Number of times module was deleted */N/* Routines in the CSMACD module that are called by the drivers. All names */N/* must begin with the letter C. These routines are accessed through the */N/* $CJSB macro. 5 */N void *lan$a_cvalcnm; /* Client name validation routine */N void *lan$a_csetcnm; /* Client name set routine */N void *lan$a_ccreate_port; /* Create a port entity */N void *lan$a_csetpha; /* Set the PHA to default */N void *lan$a_csense; /* Return additional parameters */N void *lan$a_cdelete_port; /* Delete 5a port entity */N void *lan$a_ctimer; /* Timer routine */N void *lan$a_cirpdone; /* To return an IRP request */N/* Station events */N void *lan$a_cevexc; /* To declare an event */N void *lan$a_cevccf; /* To declare an event */N void *lan$a_cevlat; /* To declare an event 5*/N void *lan$a_cevfce; /* To declare an event */N void *lan$a_cevali; /* To declare an event */N void *lan$a_cevdor; /* To declare an event */N void *lan$a_cevusb; /* To declare an event */N void *lan$a_cevuub; /* To declare an event */N void *lan$a_cevuid; /* To declare an event */N void *lan$a_cevumd5; /* To declare an event */N void *lan$a_cevftl; /* To declare an event */N void *lan$a_cevrdl; /* To declare an event */N/* CSMACD module fields */N void *lan$a_csmacd_eab; /* CSMACD entity EAB address */N void *lan$a_csmacd_port_eab; /* Port entity EAB address */N void *lan$a_csmacd_station_eab; /* Stati5on entity EAB address */N void *lan$a_csmacd_eib; /* Module EIB */N/************************************************************************* */N/* FDDI SECTION */N/************************************************************************* */N/* Versions */N unsigned __int64 lan$q_f_nm_m_ver; /* NM MACRO version 5 */N unsigned int lan$l_f_nm_c_ver0; /* NM C version */N unsigned int lan$l_f_nm_c_ver1; /* NM C version */N unsigned __int64 lan$q_f_nm_ev_ver; /* NM Event version */N/* Flags */ __union {# unsigned int lan$l_f_flags; __struct {O unsigned lan$v_f_reg_emaa : 1; /* Module is registered with EMAA */N unsigned l 5an$v_f_created : 1; /* Module entity is CREATED */N unsigned lan$v_f_wait : 1; /* Module is waiting for the device */N unsigned lan$v_f_l_wait : 1; /* Link is waiting for the device */P unsigned lan$v_f_h_wait : 1; /* PhyPort is waiting for the device */( unsigned lan$v_fill_11_ : 3; } lan$r_fill_5_; } lan$r_fill_4_;N int lan$l_extra_l_2; /* Preserve quadword alignment */N/* Time stamp fields (all va5lues stored from ABSTIMTICS) */N unsigned int lan$l_f_cretim; /* Time the module was last created */N unsigned int lan$l_f_deltim; /* Time the module was last deleted */N/* Counters (all counters are wrap) */P unsigned int lan$l_f_crectr; /* Number of times module was created */P unsigned int lan$l_f_delctr; /* Number of times module was deleted */N/* Routines in the FDDI module that are called by  5the drivers. These */N/* are not accessed through the FJSB routine, so it doesn't have to */N/* begin with F. */N void *lan$a_smt_response; /* SMT responses for NM are passed */N/* to this routine */N/* Routines in the FDDI module that are called by the drivers. All names */N/* must begin with the letter F. These routines are accessed through the  5*/N/* $FJSB macro. */N void *lan$a_fvalcnm; /* Client name validation routine */N void *lan$a_fsetcnm; /* Client name set routine */N void *lan$a_fcreate_port; /* Create a port entity */N void *lan$a_fsense; /* Return additional parameters */N void *lan$a_fdelete_port; /* Delete a port entity */N void *lan$a_ftimer 5; /* Timer routine */N void *lan$a_firpdone; /* To return an IRP request */N/* Station events */N void *lan$a_fevstf; /* Self-Test Failure */N void *lan$a_fevtrr; /* TRace Received */N void *lan$a_fevcch; /* Configuration Change */N/* Link events  5 */N void *lan$a_fevtur; /* Transmit Underrun */N void *lan$a_fevtfl; /* Transmit Failure */N void *lan$a_fevfce; /* Frame Check Error */N void *lan$a_fevfse; /* Frame Status Error */N void *lan$a_fevrdl; /* Receive Data Length error */N void *lan$a_fevuid; /* Unrecognized Individual Dest.  5 */N void *lan$a_fevumd; /* Unrecognized Multicast Dest. */N void *lan$a_fevdor; /* Receive Data Overrun */N void *lan$a_fevlbu; /* Link Buffer Unavailable */N void *lan$a_fevusb; /* System Buffer Unavailable */N void *lan$a_fevuub; /* User Buffer Unavailable */N void *lan$a_fevrii; /* Ring Initialization Initiated */N void *lan$a_fevr5ir; /* Ring Initialization Received */N void *lan$a_fevrbi; /* Ring Beacon Initiated */N void *lan$a_fevdaf; /* Duplicate Address Failure */N void *lan$a_fevdtd; /* Duplicate Token Detected */N void *lan$a_fevrpe; /* Ring Purge Error */S void *lan$a_fevfci; /* Frame Content Independent strip error */N void *lan$a_fevtri; 5/* TRace Initiated */N void *lan$a_fevdbr; /* Directed Beacon Received */N/* PHY PORT events */N void *lan$a_fevlem; /* Link Error Monitor */N void *lan$a_fevebe; /* Elasticity Buffer Error */N void *lan$a_fevlct; /* Link Confidence Test reject */N/* FDDI module fields 5 */N void *lan$a_fddi_eab; /* FDDI entity EAB address */N void *lan$a_fddi_port_eab; /* Port entity EAB address */N void *lan$a_fddi_station_eab; /* Station entity EAB address */N void *lan$a_fddi_link_eab; /* Link entity EAB address */N void *lan$a_fddi_phyport_eab; /* PHY port entity EAB address */N void *lan$a_fddi_eib; /* Module EIB */N/***********5************************************************************** */N/* TOKEN RING SECTION */N/************************************************************************* */N/* Versions */N unsigned __int64 lan$q_t_nm_m_ver; /* NM MACRO version */N unsigned int lan$l_t_nm_c_ver0; /* NM C version */N unsigned int lan$l_t_nm_c_ver1; 5 /* NM C version */N unsigned __int64 lan$q_t_nm_ev_ver; /* NM Event version */N/* Flags */ __union {# unsigned int lan$l_t_flags; __struct {O unsigned lan$v_t_reg_emaa : 1; /* Module is registered with EMAA */N unsigned lan$v_t_created : 1; /* Module entity is CREATED */( unsigned lan$v_fill_12_ : 6; } lan$r_fill5_7_; } lan$r_fill_6_;N int lan$l_extra_l_3; /* Preserve quadword alignment */N/* Time stamp fields (all values stored from ABSTIMTICS) */N unsigned int lan$l_t_cretim; /* Time the module was last created */N unsigned int lan$l_t_deltim; /* Time the module was last deleted */N/* Counters (all counters are wrap) */P unsigned int lan$l_t_crectr; /* Number of times module was crea5ted */P unsigned int lan$l_t_delctr; /* Number of times module was deleted */N/* Routines in the Token Ring module that are called by the drivers. All */N/* names must begin with the letter T. These routines are accessed through */N/* the $TJSB macro. */N void *lan$a_tvalcnm; /* Client name validation routine */N void *lan$a_tsetcnm; /* Client name set routine */N void *lan$a_5tcreate_port; /* Create a port entity */N void *lan$a_tsense; /* Return additional parameters */N void *lan$a_tdelete_port; /* Delete a port entity */N void *lan$a_ttimer; /* Timer routine */N void *lan$a_tirpdone; /* To return an IRP request */N/* Token Ring module fields */N void *lan$a_tr_eab; /*5 TR entity EAB address */N void *lan$a_tr_port_eab; /* Port entity EAB address */N void *lan$a_tr_station_eab; /* Station entity EAB address */R void *lan$a_tr_sr_eab; /* Station's Source Routing EAB address */N void *lan$a_tr_eib; /* Module EIB */N/************************************************************************* */N/* ATM SECTION 5 */N/************************************************************************* */N/* Versions */N unsigned __int64 lan$q_a_nm_m_ver; /* NM MACRO version */N unsigned int lan$l_a_nm_c_ver0; /* NM C version */N unsigned int lan$l_a_nm_c_ver1; /* NM C version */N unsigned __int64 lan$q_a_nm_ev_ver; /* NM Event version */N/* Flags 5 */ __union {# unsigned int lan$l_a_flags; __struct {O unsigned lan$v_a_reg_emaa : 1; /* Module is registered with EMAA */N unsigned lan$v_a_created : 1; /* Module entity is CREATED */( unsigned lan$v_fill_13_ : 6; } lan$r_fill_9_; } lan$r_fill_8_;N/* ATM common PORT lock */N void *lan$a_atm_5portlock; /* PORT lock */N/* Time stamp fields (all values stored from ABSTIMTICS) */N unsigned int lan$l_a_cretim; /* Time the module was last created */N unsigned int lan$l_a_deltim; /* Time the module was last deleted */N/* Counters (all counters are wrap) */P unsigned int lan$l_a_crectr; /* Number of times module was created */P unsigned int lan$l_a_delctr; /* N5umber of times module was deleted */N/* Routines in the ATM module that are called by the drivers. All */N/* names must begin with the letter A. These routines are accessed through */N/* the $AJSB macro. */N void *lan$a_avalcnm; /* Client name validation routine */N void *lan$a_asetcnm; /* Client name set routine */N void *lan$a_acreate_port; /* Create a port entity 5 */N void *lan$a_asense; /* Return additional parameters */N void *lan$a_adelete_port; /* Delete a port entity */N void *lan$a_atimer; /* Timer routine */N void *lan$a_airpdone; /* To return an IRP request */N/* ATM module fields */N void *lan$a_atm_eab; /* ATM entity EAB address */N void *lan$5a_atm_port_eab; /* Port entity EAB address */N void *lan$a_atm_station_eab; /* Station entity EAB address */N void *lan$a_atm_eib; /* Module EIB */N/************************************************************************* */N/* End of medium specific sections */N/************************************************************************* */N/* Miscellaneous constants 5 */O/* LAN device driver fork routine status definitions. These values are used */N/* by the driver to indicate the type of error event that has occurred, if */O/* any. If an error has occurred, the value contained in the low word of R3 */N/* (fork routine conventions) will contain one of the following values. */N/* */N/* NOTE: if R3 = Hardware, then the upper word of R3 contains 5the device's */N/* CSR contents at the time of the error. */N/* */N/* Some LAN diagnostic codes comes with an associated QIO function modifier */R/* for $qio calls, for example: to read the internal counters we call $qio with */N/* IO$_DIAGNOSE | IO$M_REMOUNT. Furthermore, we do not use the high 16-bits */N/* modifiers in irp$l_func, and, therefore, to add codes beyond 16, we pass */Q/* t5he LAN diagnostic function (i.e. LAN$V_DIAG_whatever) code in irp$l_qio_p3 */N/* with the QIO function code set IO$_DIAGNOSE and no $QIO modifier bits. */Q/* Drivers then check for the LAN diagnostic function code (the first argument */Q/* in lsb$a_diag routine) set to 32 (meaning no modifiers set in $qio function */N/* code) and get the diagnostic function code from ipr$l_qio_p3. */^/* The main communication need is for drivers to send OPCOM messages, but the mechanism is */_/* 5 not limited to that. To queue an AST to LANACP we need 2 items and a message. The 2 items */a/* are the LANACP pid and the LANACP (user mode) routine that the AST suppose to call when it */_/* fires (these are UPID and UASTADR). The message is a piece of non-paged pool, generally a */]/* VCRP, that is put in the LACP_QUEUE. This queue is interlocked and its size matches the */[/* cache size boundary since since memory is locked in whole cache sizes and boundaries. */N/* !5 */R/* LANACP_RTN is the routine that LANACP calls (forks) to pass its information */N/* (pid and ast routine) to IPL8 code. */N unsigned int lan$l_upid; /* LANACP PID */N void (*lan$ps_uastadr)(); /* LANACP AST routine address */ char lan$b_fill_14_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C"5++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN void (*lan$a_lanacp_rtn)(); /* LANACP/LAN init routine */#pragma __nomember_alignment char lan$b_fill_15_ [60];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */#else#pragma __nomember_alignment#endifR __union { /* LAN COMMON to LANACP interlock QUEUE */#pragma __nomember_alignment #5 __struct {f void *lan$ps_lanacp_flink; /* Normally a queue of VCRPs, but we can't do it explicitly */\ void *lan$ps_lanacp_blink; /* here because of dependencies with [BOOTDRIVER] */ } lan$r_k2uq;! char lan$b_k_qbytes [64]; } lan$r_lacp_queue; } LAN; #if !defined(__VAXC)-#define lan$l_flags lan$r_fill_0_.lan$l_flags?#define lan$v_reg_vci lan$r_fill_0_.lan$r_fill_1_.lan$v_reg_vciA#define lan$v_dat_lock lan$r_fill_0_.lan$r_fil $5l_1_.lan$v_dat_lockA#define lan$v_lan_init lan$r_fill_0_.lan$r_fill_1_.lan$v_lan_initA#define lan$v_cnm_init lan$r_fill_0_.lan$r_fill_1_.lan$v_cnm_initA#define lan$v_fnm_init lan$r_fill_0_.lan$r_fill_1_.lan$v_fnm_initA#define lan$v_tnm_init lan$r_fill_0_.lan$r_fill_1_.lan$v_tnm_initA#define lan$v_anm_init lan$r_fill_0_.lan$r_fill_1_.lan$v_anm_initQ#define lan$v_hot_replace_drvr lan$r_fill_0_.lan$r_fill_1_.lan$v_hot_replace_drvr1#define lan$l_c_flags lan$r_fill_2_.lan$l_c_flagsE#define %5lan$v_c_reg_emaa lan$r_fill_2_.lan$r_fill_3_.lan$v_c_reg_emaaC#define lan$v_c_created lan$r_fill_2_.lan$r_fill_3_.lan$v_c_created=#define lan$v_c_wait lan$r_fill_2_.lan$r_fill_3_.lan$v_c_wait1#define lan$l_f_flags lan$r_fill_4_.lan$l_f_flagsE#define lan$v_f_reg_emaa lan$r_fill_4_.lan$r_fill_5_.lan$v_f_reg_emaaC#define lan$v_f_created lan$r_fill_4_.lan$r_fill_5_.lan$v_f_created=#define lan$v_f_wait lan$r_fill_4_.lan$r_fill_5_.lan$v_f_waitA#define lan$v_f_l_wait lan$r_fill_4_.lan$r_fill_5_ &5.lan$v_f_l_waitA#define lan$v_f_h_wait lan$r_fill_4_.lan$r_fill_5_.lan$v_f_h_wait1#define lan$l_t_flags lan$r_fill_6_.lan$l_t_flagsE#define lan$v_t_reg_emaa lan$r_fill_6_.lan$r_fill_7_.lan$v_t_reg_emaaC#define lan$v_t_created lan$r_fill_6_.lan$r_fill_7_.lan$v_t_created1#define lan$l_a_flags lan$r_fill_8_.lan$l_a_flagsE#define lan$v_a_reg_emaa lan$r_fill_8_.lan$r_fill_9_.lan$v_a_reg_emaaC#define lan$v_a_created lan$r_fill_8_.lan$r_fill_9_.lan$v_a_created.#define lan$r_k2uq lan$r_lacp_qu'5eue.lan$r_k2uq:#define lan$ps_lanacp_flink lan$r_k2uq.lan$ps_lanacp_flink:#define lan$ps_lanacp_blink lan$r_k2uq.lan$ps_lanacp_blink6#define lan$b_k_qbytes lan$r_lacp_queue.lan$b_k_qbytes"#endif /* #if !defined(__VAXC) */    $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#end (5if#pragma __standard #endif /* __LANDEF_LOADED */ ww0n[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written pe)5rmission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Softwa*5re, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$ +5DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LANIDEF ***/#ifndef __LANIDEF_LOADED#define __LANIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer,5_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !def-5ined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* LANIDEF Version Identification */#define LAN$C_LANIDEF_VER 119 %#define LAN_VERSION_V831H1_OR_LATER 1"#define LAN_VERSION_V84_OR_LATER 1C#ifdef __LANIDEF_LOADED /* True if generated via SDL/VMS_DEV */#ifndef __EFBDEF_LOADED#include %#endif /* #ifndef __EFBDEF_LOADED */#ifndef __FWDDEF_LOADED#include %#endif /*.5 #ifndef __FWDDEF_LOADED */#ifndef __LANDEF_LOADED#include %#endif /* #ifndef __LANDEF_LOADED */#ifndef __LANIPROTODEF_LOADED#include +#endif /* #ifndef __LANIPROTODEF_LOADED */#ifndef __LEVTDEF_LOADED#include &#endif /* #ifndef __LEVTDEF_LOADED */#ifndef __LHBDEF_LOADED#include %#endif /* #ifndef __LHBDEF_LOADED */#ifndef __LLBDEF_LOADED#include %#endif /* #ifndef __LLBDEF_LOADED */#ifndef __LAN_LNMD/5EF_LOADED#include )#endif /* #ifndef __LAN_LNMDEF_LOADED */#ifndef __LOOPDEF_LOADED#include &#endif /* #ifndef __LOOPDEF_LOADED */#ifndef __LPBDEF_LOADED#include %#endif /* #ifndef __LPBDEF_LOADED */#ifndef __LSBDEF_LOADED#include %#endif /* #ifndef __LSBDEF_LOADED */#ifndef __MULTIDEF_LOADED#include '#endif /* #ifndef __MULTIDEF_LOADED */#ifndef __P2BDEF_LOADED#include %#endif /* #ifndef05 __P2BDEF_LOADED */#ifndef __PDUDEF_LOADED#include %#endif /* #ifndef __PDUDEF_LOADED */#ifndef __RHDRDEF_LOADED#include &#endif /* #ifndef __RHDRDEF_LOADED */#ifndef __SMTDEF_LOADED#include %#endif /* #ifndef __SMTDEF_LOADED */#ifndef __SOURCEDEF_LOADED#include (#endif /* #ifndef __SOURCEDEF_LOADED */#ifndef __UCBNIDEF_LOADED#include '#endif /* #ifndef __UCBNIDEF_LOADED */$#endif /* #ifdef __LANIDEF_LOADE15D */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LANIDEF_LOADED */ wwPn[UM/***************************************************************************/M/** 25 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFT35WARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************45**************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LANIPROTODEF ***/#ifndef __LANIPROTODEF_LOADED 55#define __LANIPROTODEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#def65ine __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* MOP LOOPBACK packet definition for Duplicate Address Test (DAT) */N#define MPLP$C_LEN 12 75 /* Size of 802 SNAP Header */ typedef struct _mop_loop {N unsigned short int mplp$w_skip; /* Skip count */N unsigned short int mplp$w_func1; /* Original Function Code */" unsigned char mplp$g_addr [6];N/* Address */N unsigned short int mplp$w_func2; /* spot for reply function code */ } MOP_LOOP;N/* 802.2 XID packet constant def's 85 */N#define LLC$C_XID_LEN 6 /* length of XID packet */N#define XID$C_FMT_ID 129 /* XID format Identifier (^X81) */N#define XID$C_DATA 1 /* XID Data (^X0001) */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __c95plusplus }#endif#pragma __standard "#endif /* __LANIPROTODEF_LOADED */ ww`o[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the:5 **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior writ;5ten permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */G/* Sourc <5e: 26-JAN-2022 23:16:38 $1$DGA8345:[LIB_H.SRC]LANUDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LANUDEF ***/#ifndef __LANUDEF_LOADED#define __LANUDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */=5\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif >5#ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* LANUDEF Version Identification */#define LAN$C_LANUDEF_VER 38O/* This constant represents the largest data link header for all formats and */O/* for all mediums. Token Ring has the largest header (for the mediums) and */N/* 802E has the largest header (for the formats). This includes any device */N/* specific needs (for exa?5mple the 3 additional bytes required by most of */N/* the FDDI devices). */N/* */N/* 03 bytes for device specific FDDI stuff */N/* 01 byte for FC */N/* 12 bytes for DA/SA */N/* 08 bytes for DSAP/SSAP/CTL/PID @5 */N/* 32 bytes for Source Routing header */N/* 02 bytes for a length field */#define LAN$C_MAX_HDR_SIZE 58P/* This constant is used (after swapping the protocol type bytes) to validate */N/* a protocol type. */#define LAN$C_PTY_MIN 1501N/* Protocol Types */N#define LAN$C_PTA5Y_DUMP_LOAD 352 /* S-DNA Dump/Load (MOP) */N#define LAN$C_PTY_RMTCN 608 /* S-DNA Remote Console (MOP) */N#define LAN$C_PTY_ROUTE 864 /* S-DNA Routing */N#define LAN$C_PTY_LAT 1120 /* S-Local Area Transport (LAT) */N#define LAN$C_PTY_DIAG 1376 /* S-Diagnostics */N#define LAN$C_PTY_CUST 1632 /* S-Customer Use */W#define LAN$C_PTY_SCA 1888 /*B5 S-System Communication Architecture (SCA) */N#define LAN$C_PTY_LOOPB 144 /* S-Loopback Assist protocol type */N#define LAN$C_PTY_IP 8 /* S-IP */N#define LAN$C_PTY_ARP 1544 /* S-ARP */N#define LAN$C_PTY_RARP 13696 /* S-RARP */N#define LAN$C_PTY_BRIDGE 14464 /* S-BRIDGE */N#define LAN$C_PTY_ELN 15232 /* S-VAX ELN C5 */N#define LAN$C_PTY_DNAME 15488 /* S-DNA Name Service */N#define LAN$C_PTY_ENCRY 15744 /* S-Encryption */N#define LAN$C_PTY_DTIME 16000 /* S-DNA Time Service */N#define LAN$C_PTY_LTM 16256 /* S-LTM */N#define LAN$C_PTY_BIOS 16512 /* S-BIOS */N#define LAN$C_PTY_LAST 16768 /* S-Local Area Storage (LAST) */N#defD5ine LAN$C_PTY_AMDS 18560 /* S-AMDS (Captain) */S#define LAN$C_PTY_DNV 254 /* S-DECnet Phase V (Link state routing) */N/* PID Values */S#define LAN$C_PID_RMTCN0 8 /* DNA Remote Console (802 MOP) byte <0> */V#define LAN$C_PID_RMTCN1 39856896 /* DNA Remote Console (802 MOP) bytes <4:1> */N#define LAN$C_PID_LOOPB0 8 /* Loopback (802) byte <0> */N#define LAE5N$C_PID_LOOPB1 9448192 /* Loopback (802) bytes <4:1> */N/* DIGITAL multicast address assignments */N#define LAN$C_MCA_L_MOP 16777387 /* DNA Dump/Load Assistance (MOP) */N#define LAN$C_MCA_W_MOP 0 /* DNA Dump/Load Assistance (MOP) */N#define LAN$C_MCA_L_RMTCN 33554603 /* DNA Remote Console (MOP) */N#define LAN$C_MCA_W_RMTCN 0 /* DNA Remote Console (MOP) */N#define LAN$C_MCA_L_ROUTERS 50331819F5 /* DNA Routing Routers */N#define LAN$C_MCA_W_ROUTERS 0 /* DNA Routing Routers */N#define LAN$C_MCA_L_ENDNODE 67109035 /* DNA Routing End nodes */N#define LAN$C_MCA_W_ENDNODE 0 /* DNA Routing End nodes */N#define LAN$C_MCA_L_LAT 196779 /* Local Area Transport (LAT) */N#define LAN$C_MCA_W_LAT 0 /* Local Area Transport (LAT) */N#define LAN$C_MCA_L_CUST 262315 /* Customer Use G5 */D/*CONSTANT MCA_W_CUST EQUALS %X0000-%XFFFF TAG C PREFIX LAN$; */U#define LAN$C_MCA_L_SCA 17039531 /* System Communication Architecture (SCA) */C/*CONSTANT MCA_W_SCA EQUALS %X0000-%XFFFF TAG C PREFIX LAN$; */N/* Cross-company address assignments */N#define LAN$C_CCA_L_BROADCAST -1 /* Broadcast */N#define LAN$C_CCA_W_BROADCAST 65535 /* Broadcast */N#define LAN$C_CCA_L_H5LOOPBACKA 207 /* Loopback Assistance */N#define LAN$C_CCA_W_LOOPBACKA 0 /* Loopback Assistance */N/* DNA SNAP SAP assignments */N#define LAN$C_NULL_SAP 0 /* The NULL SAP */R#define LAN$C_LLC_MGT_FNC_SAP 2 /* LLC SUBLAYER MANAGEMENT FUNCTION SAP */N#define LAN$C_LLC_MGT_SAP 3 /* LLC SUBLAYER MANAGEMENT SAP */N#define LAN$C_SNAP_SAP 170 /*I5 The SNAP SAP */N/* DNA DSAP assignments */N#define LAN$C_GLOBAL_DSAP 255 /* GLOBAL DSAP */N/* DNA GROUP SAP assignments */S#define LAN$C_MAX_NO_GSAP 4 /* Maximum number of group SAPs per user */N/* LAN frame constants */N#define LAN$C_CRC 4 /* Size of Ethernet CRJ5C */N#define LAN$C_ADDR_SIZE 6 /* Maximum size of NI address */N#define LAN$C_LEN_SIZE 2 /* Size of the length field */N/* LAN frame constants (medium independent maximums) */X#define LAN$C_HDRSIZE_ETH 21 /* Maximum of Ethernet Packet without padding */U#define LAN$C_HDRSIZE_PAD 23 /* Maximum of Ethernet Packet with padding */N#define LAN$C_HDRSIZE_CLI 17 /* Maximum of 802 Packet K5 */N#define LAN$C_HDRSIZE_USR 18 /* Maximum of 802 Packet */N#define LAN$C_HDRSIZE_802E 22 /* Maximum of 802E Packet */N/* ATM frame constants */N#define ATM$C_MAX_PKTSIZE 9234 /* Maximum of ATM Packet */N#define ATM$C_MAX_PKTSIZE_ETH 9234 /* Maximum of ATM Packet */N#define ATM$C_MAX_PKTSIZE_PAD 9234 /* Maximum of ATM Packet */N#define ATM$C_MAL5X_PKTSIZE_CLI 9234 /* Maximum of ATM Packet */N#define ATM$C_MAX_PKTSIZE_USR 9234 /* Maximum of ATM Packet */N#define ATM$C_MAX_PKTSIZE_802E 9234 /* Maximum of ATM Packet */^#define ATM$C_MAX_PKTSIZE_HWA 9264 /* Maximum hardware Packet including header and CRC */N#define ATM$C_MIN_PKTSIZE 0 /* Minimum of ATM Packet */N#define ATM$C_HDRSIZE_ETH 14 /* Maximum of ATM Header */N#define ATM$C_HDRSIZE_PAD M516 /* Maximum of ATM Header */N#define ATM$C_HDRSIZE_CLI 17 /* Maximum of ATM Header */N#define ATM$C_HDRSIZE_USR 18 /* Maximum of ATM Header */N#define ATM$C_HDRSIZE_802E 22 /* Maximum of ATM Header */N#define ATM$C_SPEED 155 /* Nominal default line speed */N/* CSMACD frame constants */X#define CSMACD$C_MAX_PKTSIZE 1500 /* Maximum oN5f Ethernet Packet without padding */X#define CSMACD$C_MAX_PKTSIZE_ETH 1500 /* Maximum of Ethernet Packet without padding */U#define CSMACD$C_MAX_PKTSIZE_PAD 1498 /* Maximum of Ethernet Packet with padding */N#define CSMACD$C_MAX_PKTSIZE_CLI 1497 /* Maximum of 802 Packet */N#define CSMACD$C_MAX_PKTSIZE_USR 1496 /* Maximum of 802 Packet */N#define CSMACD$C_MAX_PKTSIZE_802E 1492 /* Maximum of 802E Packet */^#define CSMACD$C_MAX_PKTSIZE_HWA 1518 /* MaximumO5 hardware Packet including header and CRC */N#define CSMACD$C_MIN_PKTSIZE 46 /* Minimum of Ethernet Packet */N#define CSMACD$C_MAX802_PKTSIZ 1497 /* Maximum of 802 Packet */N#define CSMACD$C_MAX802E_PKTSIZ 1492 /* Maximum of 802E Packet */X#define CSMACD$C_MAXETH_PKTSIZ 1500 /* Maximum of Ethernet Packet without padding */U#define CSMACD$C_MAXETHPAD_PKTSIZ 1498 /* Maximum of Ethernet Packet with padding */X#define CSMACD$C_HDRSIZE_ETH 14 /*P5 Maximum of Ethernet Header without padding */U#define CSMACD$C_HDRSIZE_PAD 16 /* Maximum of Ethernet Header with padding */N#define CSMACD$C_HDRSIZE_CLI 17 /* Maximum of 802 Header */N#define CSMACD$C_HDRSIZE_USR 18 /* Maximum of 802 Header */N#define CSMACD$C_HDRSIZE_802E 22 /* Maximum of 802E Header */N#define CSMACD$C_SPEED 10 /* Nominal default line speed */N/* FDDI frame constants Q5 */X#define FDDI$C_MAX_PKTSIZE 4470 /* Maximum of Ethernet Packet without padding */U#define FDDI$C_MAX_PKTSIZE_PAD 4468 /* Maximum of Ethernet Packet with padding */N#define FDDI$C_MAX_PKTSIZE_CLI 4475 /* Maximum of 802 Packet */N#define FDDI$C_MAX_PKTSIZE_USR 4474 /* Maximum of 802 Packet */N#define FDDI$C_MAX_PKTSIZE_802E 4470 /* Maximum of 802E Packet */O#define FDDI$C_MAX_PKTSIZE_ETH 4470 /* Maximum of MappR5ed Ethernet Packet */^#define FDDI$C_MAX_PKTSIZE_HWA 4495 /* Maximum hardware Packet including header and CRC */N#define FDDI$C_MIN_PKTSIZE 0 /* Minimum of Ethernet Packet */N#define FDDI$C_MAX802_PKTSIZ 4475 /* Maximum of 802 Packet */N#define FDDI$C_MAX802E_PKTSIZ 4470 /* Maximum of 802E Packet */O#define FDDI$C_MAXMPETH_PKTSIZ 4470 /* Maximum of Mapped Ethernet Packet */^#define FDDI$C_MAXMPETHPAD_PKTSIZ 4468 /* Maximum of Mapped EthS5ernet Packet with pad field */X#define FDDI$C_HDRSIZE_ETH 21 /* Maximum of Ethernet Header without padding */U#define FDDI$C_HDRSIZE_PAD 23 /* Maximum of Ethernet Header with padding */N#define FDDI$C_HDRSIZE_CLI 16 /* Maximum of 802 Header */N#define FDDI$C_HDRSIZE_USR 17 /* Maximum of 802 Header */N#define FDDI$C_HDRSIZE_802E 21 /* Maximum of 802E Header */N#define FDDI$C_SPEED 100 /* Nominal defauT5lt line speed */N/* TOKEN RING frame constants */R#define TR$C_MAX_PKTSIZE 4436 /* Maximum of TR Packet without padding */O#define TR$C_MAX_PKTSIZE_PAD 4434 /* Maximum of TR Packet with padding */N#define TR$C_MAX_PKTSIZE_CLI 4441 /* Maximum of 802 Packet */N#define TR$C_MAX_PKTSIZE_USR 4440 /* Maximum of 802 Packet */N#define TR$C_MAX_PKTSIZE_802E 4436 /* Maximum of 802E Packet U5*/O#define TR$C_MAX_PKTSIZE_ETH 4436 /* Maximum of Mapped Ethernet Packet */^#define TR$C_MAX_PKTSIZE_HWA 4462 /* Maximum hardware Packet including header and CRC */N#define TR$C_MIN_PKTSIZE 0 /* Minimum of Ethernet Packet */N#define TR$C_MAX802_PKTSIZ 4441 /* Maximum of 802 Packet */N#define TR$C_MAX802E_PKTSIZ 4436 /* Maximum of 802E Packet */O#define TR$C_MAXMPETH_PKTSIZ 4436 /* Maximum of Mapped Ethernet Packet */^#dV5efine TR$C_MAXMPETHPAD_PKTSIZ 4434 /* Maximum of Mapped Ethernet Packet with pad field */X#define TR$C_HDRSIZE_ETH 52 /* Maximum of Ethernet Header without padding */U#define TR$C_HDRSIZE_PAD 54 /* Maximum of Ethernet Header with padding */N#define TR$C_HDRSIZE_CLI 47 /* Maximum of 802 Header */N#define TR$C_HDRSIZE_USR 48 /* Maximum of 802 Header */N#define TR$C_HDRSIZE_802E 52 /* Maximum of 802E Header W5 */N#define TR$C_SPEED 16 /* Nominal default line speed */N/* LAN Item List definitions */N#define DLL$K_DL_ENTITY 1 /* Create Input */N#define DLL$K_CLIENT 2 /* Create Input */N#define DLL$K_DL_TEMPLATE 3 /* Create Input */N#define DLL$K_LAN_DEVICE 4 /* Create Input */N#define DLL$K_PORT_EX5NTITY 5 /* Create Output */N#define DLL$K_MINIMUM_BUFFER_SIZE 6 /* Enable Input */N#define DLL$K_PREFERRED_BUFFER_SIZE 7 /* Enable Input */N#define DLL$K_PROTOCOLID 8 /* Enable Input */N#define DLL$K_DECUSERDATA 9 /* Enable Input */N#define DLL$K_PROFILE 10 /* Enable Output */N#define DLL$K_ACTUAL_BUFFER_SIZE 11 /* EnaY5ble Output */N/*++ */O/* This structure represents a LAN module entity. There will be one used to */Q/* represent CSMA/CD; even if there are multiple CSMA/CD stations. There will */N/* also be one used to represent FDDI. */N/* */N/* These are the common fields of the LAN module entity. Z5 */N/*-- */ N#define LAN$K_FIXED_LENGTH 24 /* Length of LAN block */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _lanudef {N/* This is version 1 of the LAN structure. Use #1 (no symbol) for the */N/* version field. [5 */#pragma __nomember_alignmentN unsigned int lan$l_version; /* S-Version of LAN database */N unsigned int lan$l_reserved1; /* Reserved */N void *lan$a_get_device; /* Address of LAN$GET_DEVICE */N unsigned int lan$l_reserved2; /* Reserved */N void *lan$a_create_port; /* Address of LAN$CREATE_PORT */N void *lan$a_delete\5_port; /* Address of LAN$DELETE_PORT */ } LANUDEF;  C#ifdef __LANUDEF_LOADED /* True if generated via SDL/VMS_DEV */#ifndef __LDCDEF_LOADED#include %#endif /* #ifndef __LDCDEF_LOADED */#ifndef __LILDEF_LOADED#include %#endif /* #ifndef __LILDEF_LOADED */#ifndef __VCIBDLLDEF_LOADED#include )#endif /* #ifndef __VCIBDLLDEF_LOADED */#ifndef __VCRPLANDEF_LOADED#include )#endif /* #ifndef __V]5CRPLANDEF_LOADED */#ifndef __PROTODEF_LOADED#include '#endif /* #ifndef __PROTODEF_LOADED */$#endif /* #ifdef __LANUDEF_LOADED */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LANUDEF_LOADED */ wwlo[U^5M/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hew_5lett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. `5 **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************* a5***********************************************************************************//*** MODULE $LAN_LNMDEF ***/#ifndef __LAN_LNMDEF_LOADED#define __LAN_LNMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragmb5a __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_unio c5n#endif#endif N/*++ */N/* CMIP Generic Client Name constants */N/*-- */$#define LAN$K_CMIP_GENERIC_CLIENT 34!#define LAN$K_CMIP_USER_PROCESS 0 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore d5 /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LAN_LNMDEF_LOADED */ wwo[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/e5M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be usef5d, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/ g5=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */F/* Source: 09-JAN-1996 14:32:07 $1$DGA8345:[LIB_H.SRC]LCADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LCADEF ***/#ifndef __LCADEF_LOADED#define __LCADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INIh5TIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __structi5 struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif "#define LCA$L_MEM_BCR0_L 536870912#define LCA$L_MEM_BCR0_H 1"#define LCA$L_MEM_BCR1_L 536870920#define LCA$L_MEM_BCR1_H 1"#define LCA$L_MEM_BCR2_L 536870928#define LCA$L_MEM_BCR2_H 1"#define LCA$L_MEM_BCR3_L 536870936#define LCA$L_MEM_BCR3_H 1"#define LCA$L_MEM_BMR0_L 536870944#define LCA$L_MEM_j5BMR0_H 1"#define LCA$L_MEM_BMR1_L 536870952#define LCA$L_MEM_BMR1_H 1"#define LCA$L_MEM_BMR2_L 536870960#define LCA$L_MEM_BMR2_H 1"#define LCA$L_MEM_BMR3_L 536870968#define LCA$L_MEM_BMR3_H 1"#define LCA$L_MEM_BTR0_L 536870976#define LCA$L_MEM_BTR0_H 1"#define LCA$L_MEM_BTR1_L 536870984#define LCA$L_MEM_BTR1_H 1"#define LCA$L_MEM_BTR2_L 536870992#define LCA$L_MEM_BTR2_H 1"#define LCA$L_MEM_BTR3_L 536871000#define LCA$L_MEM_BTR3_H 1!#define LCA$L_MEM_GTR_L 536871008#define LCA$k5L_MEM_GTR_H 1!#define LCA$L_MEM_ESR_L 536871016#define LCA$L_MEM_ESR_H 1!#define LCA$L_MEM_EAR_L 536871024#define LCA$L_MEM_EAR_H 1!#define LCA$L_MEM_CAR_L 536871032#define LCA$L_MEM_CAR_H 1!#define LCA$L_MEM_VGR_L 536871040#define LCA$L_MEM_VGR_H 1!#define LCA$L_MEM_PLM_L 536871048#define LCA$L_MEM_PLM_H 1!#define LCA$L_MEM_FOR_L 536871056#define LCA$L_MEM_FOR_H 1#define LCA$L_PMR_L 536871064#define LCA$L_PMR_H 1&#define LCA$L_IOC_HAE_PA_L -2147483648#define LCl5A$L_IOC_HAE_PA_H 1*#define LCA$L_IOC_CFG_CYC_PA_L -2147483648!#define LCA$L_IOC_CFG_CYC_PA_H 32(#define LCA$L_IOC_STAT0_PA_L -2147483584#define LCA$L_IOC_STAT0_PA_H 1(#define LCA$L_IOC_STAT1_PA_L -2147483552#define LCA$L_IOC_STAT1_PA_H 1'#define LCA$L_IOC_TBIA_PA_L -2147483520#define LCA$L_IOC_TBIA_PA_H 1)#define LCA$L_IOC_TB_ENA_PA_L -2147483648!#define LCA$L_IOC_TB_ENA_PA_H 160*#define LCA$L_PCI_SFT_RST_PA_L -2147483648"#define LCA$L_PCI_SFT_RST_PA_H 192*#define LCA$L_PCI_PAR_DIm5S_PA_L -2147483648"#define LCA$L_PCI_PAR_DIS_PA_H 224*#define LCA$L_IOC_W_BASE0_PA_L -2147483392 #define LCA$L_IOC_W_BASE0_PA_H 1*#define LCA$L_IOC_W_BASE1_PA_L -2147483360 #define LCA$L_IOC_W_BASE1_PA_H 1*#define LCA$L_IOC_W_MASK0_PA_L -2147483328 #define LCA$L_IOC_W_MASK0_PA_H 1*#define LCA$L_IOC_W_MASK1_PA_L -2147483296 #define LCA$L_IOC_W_MASK1_PA_H 1*#define LCA$L_IOC_T_BASE0_PA_L -2147483264 #define LCA$L_IOC_T_BASE0_PA_H 1*#define LCA$L_IOC_T_BASE1_PA_L -2147483232 #define LCA$L_IOn5C_T_BASE1_PA_H 1*#define LCA$L_IOC_TB_TAG0_PA_L -2130706432 #define LCA$L_IOC_TB_TAG0_PA_H 1*#define LCA$L_IOC_TB_TAG1_PA_L -2130706400 #define LCA$L_IOC_TB_TAG1_PA_H 1*#define LCA$L_IOC_TB_TAG2_PA_L -2130706368 #define LCA$L_IOC_TB_TAG2_PA_H 1*#define LCA$L_IOC_TB_TAG3_PA_L -2130706336 #define LCA$L_IOC_TB_TAG3_PA_H 1*#define LCA$L_IOC_TB_TAG4_PA_L -2130706304 #define LCA$L_IOC_TB_TAG4_PA_H 1*#define LCA$L_IOC_TB_TAG5_PA_L -2130706272 #define LCA$L_IOC_TB_TAG5_PA_H 1*#define LCA$L_IOC_TBo5_TAG6_PA_L -2130706240 #define LCA$L_IOC_TB_TAG6_PA_H 1*#define LCA$L_IOC_TB_TAG7_PA_L -2130706208 #define LCA$L_IOC_TB_TAG7_PA_H 1*#define LCA$L_IOC_IACK_SC_PA_L -1610612736 #define LCA$L_IOC_IACK_SC_PA_H 1%#define LCA$L_PCI_IO_PA_L -1073741824#define LCA$L_PCI_IO_PA_H 1%#define LCA$L_PCI_CFG_PA_L -536870912#define LCA$L_PCI_CFG_PA_H 1##define LCA$L_PCI_SPARSE_MEM_PA_L 0##define LCA$L_PCI_SPARSE_MEM_PA_H 2"#define LCA$L_PCI_DENSE_MEM_PA_L 0"#define LCA$L_PCI_DENSE_MEM_PA_H 3#defp5ine LCA$M_PMR_PRMDIV 0x7#define LCA$M_PMR_OVRDIV 0x38#define LCA$M_PMR_INTOVR 0x40#define LCA$M_PMR_DMAOVR 0x80'#define LCA$M_PMR_OVRCC_EVEN 0xFFFF0000.#define LCA$M_PMR_OVRCC_ODD 0xFFFFFF0000000000#define LCA$K_PMR_SPEED_IDLE 4#define LCA$K_PMR_SPEED_LOW 2 #define LCA$K_PMR_SPEED_MEDIUM 1#define LCA$K_PMR_SPEED_HIGH 0!#define LCA$M_HAE_BITS 0xF8000000#define LCA$M_CFG_AD 0x3#define LCA$M_STAT0_CMD 0xF#define LCA$M_IOC_ERR 0x10#define LCA$M_IOC_LOST_ERR 0x20#define LCq5A$M_IOC_T_HIT 0x40#define LCA$M_IOC_T_REF 0x80 #define LCA$M_IOC_ERR_CODE 0x700##define LCA$M_STAT1_ADDR 0xFFFFFFFF#define LCA$M_TB_EN 0x80 #define LCA$M_PCI_SFT_RESET 0x40#define LCA$M_PCI_PAR_DIS 0x20%#define LCA$M_W_BASE0_BITS 0xFFF00000$#define LCA$M_W_BASE0_SG 0x100000000%#define LCA$M_W_BASE0_WEN 0x200000000%#define LCA$M_W_BASE1_BITS 0xFFF00000$#define LCA$M_W_BASE1_SG 0x100000000%#define LCA$M_W_BASE1_WEN 0x200000000%#define LCA$M_W_MASK0_BITS 0xFFF00000%#define LCA$M_W_ r5MASK1_BITS 0xFFF00000%#define LCA$M_T_BASE0_BITS 0xFFFFFC00%#define LCA$M_T_BASE1_BITS 0xFFFFFC00%#define LCA$M_TB_TAG0_BITS 0xFFFFE000%#define LCA$M_TB_TAG1_BITS 0xFFFFE000%#define LCA$M_TB_TAG2_BITS 0xFFFFE000%#define LCA$M_TB_TAG3_BITS 0xFFFFE000%#define LCA$M_TB_TAG4_BITS 0xFFFFE000%#define LCA$M_TB_TAG5_BITS 0xFFFFE000%#define LCA$M_TB_TAG6_BITS 0xFFFFE000%#define LCA$M_TB_TAG7_BITS 0xFFFFE000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using prs5e DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _lca {#pragma __nomember_alignment __union { __int64 lca$q_bcr0; __struct {+ unsigned lca$v_bcr0_fill1 : 32;+ unsigned lca$v_bcr0_fill2 : 32; } lca$r_bcr0_fields; } lca$r_bcr0; __union { __int64 lca$q_bcr1; __struct {+ unsigned lca$v_bcr1_fill1 : 32;+ t5 unsigned lca$v_bcr1_fill2 : 32; } lca$r_bcr1_fields; } lca$r_bcr1; __union { __int64 lca$q_bcr2; __struct {+ unsigned lca$v_bcr2_fill1 : 32;+ unsigned lca$v_bcr2_fill2 : 32; } lca$r_bcr2_fields; } lca$r_bcr2; __union { __int64 lca$q_bcr3; __struct {+ unsigned lca$v_bcr3_fill1 : 32;+ unsigned lca$v_bcr3_fill2 : 32; } lca$r_bcr3_fields;u5 } lca$r_bcr3; __union { __int64 lca$q_bmr0; __struct {+ unsigned lca$v_bmr0_fill1 : 32;+ unsigned lca$v_bmr0_fill2 : 32; } lca$r_bmr0_fields; } lca$r_bmr0; __union { __int64 lca$q_bmr1; __struct {+ unsigned lca$v_bmr1_fill1 : 32;+ unsigned lca$v_bmr1_fill2 : 32; } lca$r_bmr1_fields; } lca$r_bmr1; __union { __int64 lca$q_bmr2;v5 __struct {+ unsigned lca$v_bmr2_fill1 : 32;+ unsigned lca$v_bmr2_fill2 : 32; } lca$r_bmr2_fields; } lca$r_bmr2; __union { __int64 lca$q_bmr3; __struct {+ unsigned lca$v_bmr3_fill1 : 32;+ unsigned lca$v_bmr3_fill2 : 32; } lca$r_bmr3_fields; } lca$r_bmr3; __union { __int64 lca$q_btr0; __struct {+ unsigned lca$v_btr0_fill1 : 32;+w5 unsigned lca$v_btr0_fill2 : 32; } lca$r_btr0_fields; } lca$r_btr0; __union { __int64 lca$q_btr1; __struct {+ unsigned lca$v_btr1_fill1 : 32;+ unsigned lca$v_btr1_fill2 : 32; } lca$r_btr1_fields; } lca$r_btr1; __union { __int64 lca$q_btr2; __struct {+ unsigned lca$v_btr2_fill1 : 32;+ unsigned lca$v_btr2_fill2 : 32; } lca$r_btr2x5_fields; } lca$r_btr2; __union { __int64 lca$q_btr3; __struct {+ unsigned lca$v_btr3_fill1 : 32;+ unsigned lca$v_btr3_fill2 : 32; } lca$r_btr3_fields; } lca$r_btr3; __union { __int64 lca$q_gtr; __struct {* unsigned lca$v_gtr_fill1 : 32;* unsigned lca$v_gtr_fill2 : 32; } lca$r_gtr_fields; } lca$r_gtr; __union { __int64 lca$q_esr;y5 __struct {* unsigned lca$v_esr_fill1 : 32;* unsigned lca$v_esr_fill2 : 32; } lca$r_esr_fields; } lca$r_esr; __union { __int64 lca$q_ear; __struct {* unsigned lca$v_ear_fill1 : 32;* unsigned lca$v_ear_fill2 : 32; } lca$r_ear_fields; } lca$r_ear; __union { __int64 lca$q_car; __struct {* unsigned lca$v_car_fill1 : 32;* unsignedz5 lca$v_car_fill2 : 32; } lca$r_car_fields; } lca$r_car; __union { __int64 lca$q_vgr; __struct {* unsigned lca$v_vgr_fill1 : 32;* unsigned lca$v_vgr_fill2 : 32; } lca$r_vgr_fields; } lca$r_vgr; __union { __int64 lca$q_plm; __struct {* unsigned lca$v_plm_fill1 : 32;* unsigned lca$v_plm_fill2 : 32; } lca$r_plm_fields; } lca$r_plm; __ {5union { __int64 lca$q_for; __struct {* unsigned lca$v_for_fill1 : 32;* unsigned lca$v_for_fill2 : 32; } lca$r_for_fields; } lca$r_for; __union { __int64 lca$q_pmr; __struct {N unsigned lca$v_pmr_prmdiv : 3; /* Primary speed divisor */N unsigned lca$v_pmr_ovrdiv : 3; /* Override speed divisor */N unsigned lca$v_pmr_intovr : 1; /* Interrupt selects override |5*/N unsigned lca$v_pmr_dmaovr : 1; /* DMA selects override */) unsigned lca$v_pmr_fill1 : 8;N unsigned lca$v_pmr_ovrcc_even : 16; /* Even bits of Override CC */) unsigned lca$v_pmr_fill2 : 8;N unsigned lca$v_pmr_ovrcc_odd : 24; /* Odd bits of Override CC */ } lca$r_pmr_fields; } lca$r_pmr; char lca$b_fill10 [8032]; __union { __int64 lca$q_hae; __struct {* unsigned}5 lca$v_hae_fill1 : 27;( unsigned lca$v_hae_bits : 5;* unsigned lca$v_hae_fill2 : 32; } lca$r_hae_fields; } lca$r_hae; char lca$b_fill11 [24]; __union {" __int64 lca$q_pci_cfg_cyc; __struct {& unsigned lca$v_cfg_ad : 2;2 unsigned lca$v_pci_cfg_cyc_fill1 : 30;2 unsigned lca$v_pci_cfg_cyc_fill2 : 32;' } lca$r_pci_cfg_cyc_fields; } lca$r_pci_cfg_cyc; char lca$b_fill1~52 [24]; __union { __int64 lca$q_stat0; __struct {) unsigned lca$v_stat0_cmd : 4;' unsigned lca$v_ioc_err : 1;, unsigned lca$v_ioc_lost_err : 1;) unsigned lca$v_ioc_t_hit : 1;) unsigned lca$v_ioc_t_ref : 1;, unsigned lca$v_ioc_err_code : 3;, unsigned lca$v_stat0_fill10 : 2;+ unsigned lca$v_ioc_pg_nbr : 19;, unsigned lca$v_stat0_fill2 : 32;! } lca$r_stat50_fields; } lca$r_stat0; char lca$b_fill13 [24]; __union { __int64 lca$q_stat1; __struct {+ unsigned lca$v_stat1_addr : 32;, unsigned lca$v_stat1_fill2 : 32;! } lca$r_stat1_fields; } lca$r_stat1; char lca$b_fill14 [24]; __union { __int64 lca$q_tbia; __struct {+ unsigned lca$v_tbia_fill1 : 32;+ unsigned lca$v_tbia_fill2 : 32; } lca$r_tbia_field5s; } lca$r_tbia; char lca$b_fill15 [24]; __union { __int64 lca$q_tb_ena; __struct {, unsigned lca$v_tb_ena_fill1 : 7;% unsigned lca$v_tb_en : 1;- unsigned lca$v_tb_ena_fill2 : 24;- unsigned lca$v_tb_ena_fill3 : 32;" } lca$r_tb_ena_fields; } lca$r_tb_ena; char lca$b_fill16 [24]; __union {" __int64 lca$q_pci_sft_rst; __struct {1 unsigned lca$v_pci5_sft_rst_fill1 : 6;- unsigned lca$v_pci_sft_reset : 1;2 unsigned lca$v_pci_sft_rst_fill2 : 25;2 unsigned lca$v_pci_sft_rst_fill3 : 32;' } lca$r_pci_sft_rst_fields; } lca$r_pci_sft_rst; char lca$b_fill17 [24]; __union {" __int64 lca$q_pci_par_dis; __struct {1 unsigned lca$v_pci_par_dis_fill1 : 5;+ unsigned lca$v_pci_par_dis : 1;2 unsigned lca$v_pci_par_dis_fill2 : 26;2 5 unsigned lca$v_pci_par_dis_fill3 : 32;' } lca$r_pci_par_dis_fields; } lca$r_pci_par_dis; char lca$b_fill18 [24]; __union { __int64 lca$q_w_base0; __struct {. unsigned lca$v_w_base0_fill1 : 20;- unsigned lca$v_w_base0_bits : 12;* unsigned lca$v_w_base0_sg : 1;+ unsigned lca$v_w_base0_wen : 1;. unsigned lca$v_w_base0_fill3 : 30;# } lca$r_w_base0_fields; } lca$r_5w_base0; char lca$b_fill19 [24]; __union { __int64 lca$q_w_base1; __struct {. unsigned lca$v_w_base1_fill1 : 20;- unsigned lca$v_w_base1_bits : 12;* unsigned lca$v_w_base1_sg : 1;+ unsigned lca$v_w_base1_wen : 1;. unsigned lca$v_w_base1_fill3 : 30;# } lca$r_w_base1_fields; } lca$r_w_base1; char lca$b_fill20 [24]; __union { __int64 lca$q_w_mask0; __struct {5. unsigned lca$v_w_mask0_fill1 : 20;- unsigned lca$v_w_mask0_bits : 12;. unsigned lca$v_w_mask0_fill3 : 32;# } lca$r_w_mask0_fields; } lca$r_w_mask0; char lca$b_fill21 [24]; __union { __int64 lca$q_w_mask1; __struct {. unsigned lca$v_w_mask1_fill1 : 20;- unsigned lca$v_w_mask1_bits : 12;. unsigned lca$v_w_mask1_fill3 : 32;# } lca$r_w_mask1_fields; } lca$5r_w_mask1; char lca$b_fill22 [24]; __union { __int64 lca$q_t_base0; __struct {. unsigned lca$v_t_base0_fill1 : 10;- unsigned lca$v_t_base0_bits : 22;. unsigned lca$v_t_base0_fill3 : 32;# } lca$r_t_base0_fields; } lca$r_t_base0; char lca$b_fill23 [24]; __union { __int64 lca$q_t_base1; __struct {. unsigned lca$v_t_base1_fill1 : 10;- unsigned lca$v_t_base1_bit5s : 22;. unsigned lca$v_t_base1_fill3 : 32;# } lca$r_t_base1_fields; } lca$r_t_base1; char lca$b_fill24 [7768]; __union { __int64 lca$q_tb_tag0; __struct {. unsigned lca$v_tb_tag0_fill1 : 13;- unsigned lca$v_tb_tag0_bits : 19;. unsigned lca$v_tb_tag0_fill3 : 32;# } lca$r_tb_tag0_fields; } lca$r_tb_tag0; char lca$b_fill25 [24]; __union { __int64 lca$q_tb_tag51; __struct {. unsigned lca$v_tb_tag1_fill1 : 13;- unsigned lca$v_tb_tag1_bits : 19;. unsigned lca$v_tb_tag1_fill3 : 32;# } lca$r_tb_tag1_fields; } lca$r_tb_tag1; char lca$b_fill26 [24]; __union { __int64 lca$q_tb_tag2; __struct {. unsigned lca$v_tb_tag2_fill1 : 13;- unsigned lca$v_tb_tag2_bits : 19;. unsigned lca$v_tb_tag2_fill3 : 32;# } lca$r_tb_tag2_5fields; } lca$r_tb_tag2; char lca$b_fill27 [24]; __union { __int64 lca$q_tb_tag3; __struct {. unsigned lca$v_tb_tag3_fill1 : 13;- unsigned lca$v_tb_tag3_bits : 19;. unsigned lca$v_tb_tag3_fill3 : 32;# } lca$r_tb_tag3_fields; } lca$r_tb_tag3; char lca$b_fill28 [24]; __union { __int64 lca$q_tb_tag4; __struct {. unsigned lca$v_tb_tag4_fill1 : 13;- un5signed lca$v_tb_tag4_bits : 19;. unsigned lca$v_tb_tag4_fill3 : 32;# } lca$r_tb_tag4_fields; } lca$r_tb_tag4; char lca$b_fill29 [24]; __union { __int64 lca$q_tb_tag5; __struct {. unsigned lca$v_tb_tag5_fill1 : 13;- unsigned lca$v_tb_tag5_bits : 19;. unsigned lca$v_tb_tag5_fill3 : 32;# } lca$r_tb_tag5_fields; } lca$r_tb_tag5; char lca$b_fill30 [24]; __union { 5 __int64 lca$q_tb_tag6; __struct {. unsigned lca$v_tb_tag6_fill1 : 13;- unsigned lca$v_tb_tag6_bits : 19;. unsigned lca$v_tb_tag6_fill3 : 32;# } lca$r_tb_tag6_fields; } lca$r_tb_tag6; char lca$b_fill31 [24]; __union { __int64 lca$q_tb_tag7; __struct {. unsigned lca$v_tb_tag7_fill1 : 13;- unsigned lca$v_tb_tag7_bits : 19;. unsigned lca$v_tb_tag7_fill3 : 32;# 5 } lca$r_tb_tag7_fields; } lca$r_tb_tag7; char lca$b_fill32 [7960]; } LCA; #if !defined(__VAXC)(#define lca$q_bcr0 lca$r_bcr0.lca$q_bcr0(#define lca$q_bcr1 lca$r_bcr1.lca$q_bcr1(#define lca$q_bcr2 lca$r_bcr2.lca$q_bcr2(#define lca$q_bcr3 lca$r_bcr3.lca$q_bcr3(#define lca$q_bmr0 lca$r_bmr0.lca$q_bmr0(#define lca$q_bmr1 lca$r_bmr1.lca$q_bmr1(#define lca$q_bmr2 lca$r_bmr2.lca$q_bmr2(#define lca$q_bmr3 lca$r_bmr3.lca$q_bmr3(#define lca$q_btr0 lca$r_btr0.lca$q_btr0( 5#define lca$q_btr1 lca$r_btr1.lca$q_btr1(#define lca$q_btr2 lca$r_btr2.lca$q_btr2(#define lca$q_btr3 lca$r_btr3.lca$q_btr3%#define lca$q_gtr lca$r_gtr.lca$q_gtr%#define lca$q_esr lca$r_esr.lca$q_esr%#define lca$q_ear lca$r_ear.lca$q_ear%#define lca$q_car lca$r_car.lca$q_car%#define lca$q_vgr lca$r_vgr.lca$q_vgr%#define lca$q_plm lca$r_plm.lca$q_plm%#define lca$q_for lca$r_for.lca$q_for%#define lca$q_pmr lca$r_pmr.lca$q_pmrD#define lca$v_pmr_prmdiv lca$r_pmr.lca$r_pmr_fields.lca$v_pm 5r_prmdivD#define lca$v_pmr_ovrdiv lca$r_pmr.lca$r_pmr_fields.lca$v_pmr_ovrdivD#define lca$v_pmr_intovr lca$r_pmr.lca$r_pmr_fields.lca$v_pmr_intovrD#define lca$v_pmr_dmaovr lca$r_pmr.lca$r_pmr_fields.lca$v_pmr_dmaovrL#define lca$v_pmr_ovrcc_even lca$r_pmr.lca$r_pmr_fields.lca$v_pmr_ovrcc_evenJ#define lca$v_pmr_ovrcc_odd lca$r_pmr.lca$r_pmr_fields.lca$v_pmr_ovrcc_odd%#define lca$q_hae lca$r_hae.lca$q_hae@#define lca$v_hae_bits lca$r_hae.lca$r_hae_fields.lca$v_hae_bits=#define lca$q_pci_cfg_cyc 5lca$r_pci_cfg_cyc.lca$q_pci_cfg_cycL#define lca$v_cfg_ad lca$r_pci_cfg_cyc.lca$r_pci_cfg_cyc_fields.lca$v_cfg_ad+#define lca$q_stat0 lca$r_stat0.lca$q_stat0F#define lca$v_stat0_cmd lca$r_stat0.lca$r_stat0_fields.lca$v_stat0_cmdB#define lca$v_ioc_err lca$r_stat0.lca$r_stat0_fields.lca$v_ioc_errL#define lca$v_ioc_lost_err lca$r_stat0.lca$r_stat0_fields.lca$v_ioc_lost_errF#define lca$v_ioc_t_hit lca$r_stat0.lca$r_stat0_fields.lca$v_ioc_t_hitF#define lca$v_ioc_t_ref lca$r_stat0.lca$r_stat0_fields 5.lca$v_ioc_t_refL#define lca$v_ioc_err_code lca$r_stat0.lca$r_stat0_fields.lca$v_ioc_err_code+#define lca$q_stat1 lca$r_stat1.lca$q_stat1H#define lca$v_stat1_addr lca$r_stat1.lca$r_stat1_fields.lca$v_stat1_addr(#define lca$q_tbia lca$r_tbia.lca$q_tbia.#define lca$q_tb_ena lca$r_tb_ena.lca$q_tb_ena@#define lca$v_tb_en lca$r_tb_ena.lca$r_tb_ena_fields.lca$v_tb_en=#define lca$q_pci_sft_rst lca$r_pci_sft_rst.lca$q_pci_sft_rstZ#define lca$v_pci_sft_reset lca$r_pci_sft_rst.lca$r_pci_sft_rst_fields5.lca$v_pci_sft_reset=#define lca$q_pci_par_dis lca$r_pci_par_dis.lca$q_pci_par_disV#define lca$v_pci_par_dis lca$r_pci_par_dis.lca$r_pci_par_dis_fields.lca$v_pci_par_dis1#define lca$q_w_base0 lca$r_w_base0.lca$q_w_base0P#define lca$v_w_base0_bits lca$r_w_base0.lca$r_w_base0_fields.lca$v_w_base0_bitsL#define lca$v_w_base0_sg lca$r_w_base0.lca$r_w_base0_fields.lca$v_w_base0_sgN#define lca$v_w_base0_wen lca$r_w_base0.lca$r_w_base0_fields.lca$v_w_base0_wen1#define lca$q_w_base1 lca$r_w_base1.lca$5q_w_base1P#define lca$v_w_base1_bits lca$r_w_base1.lca$r_w_base1_fields.lca$v_w_base1_bitsL#define lca$v_w_base1_sg lca$r_w_base1.lca$r_w_base1_fields.lca$v_w_base1_sgN#define lca$v_w_base1_wen lca$r_w_base1.lca$r_w_base1_fields.lca$v_w_base1_wen1#define lca$q_w_mask0 lca$r_w_mask0.lca$q_w_mask0P#define lca$v_w_mask0_bits lca$r_w_mask0.lca$r_w_mask0_fields.lca$v_w_mask0_bits1#define lca$q_w_mask1 lca$r_w_mask1.lca$q_w_mask1P#define lca$v_w_mask1_bits lca$r_w_mask1.lca$r_w_mask1_fields.lca$v_ 5w_mask1_bits1#define lca$q_t_base0 lca$r_t_base0.lca$q_t_base0P#define lca$v_t_base0_bits lca$r_t_base0.lca$r_t_base0_fields.lca$v_t_base0_bits1#define lca$q_t_base1 lca$r_t_base1.lca$q_t_base1P#define lca$v_t_base1_bits lca$r_t_base1.lca$r_t_base1_fields.lca$v_t_base1_bits1#define lca$q_tb_tag0 lca$r_tb_tag0.lca$q_tb_tag0P#define lca$v_tb_tag0_bits lca$r_tb_tag0.lca$r_tb_tag0_fields.lca$v_tb_tag0_bits1#define lca$q_tb_tag1 lca$r_tb_tag1.lca$q_tb_tag1P#define lca$v_tb_tag1_bits lca$r_tb_ta 5g1.lca$r_tb_tag1_fields.lca$v_tb_tag1_bits1#define lca$q_tb_tag2 lca$r_tb_tag2.lca$q_tb_tag2P#define lca$v_tb_tag2_bits lca$r_tb_tag2.lca$r_tb_tag2_fields.lca$v_tb_tag2_bits1#define lca$q_tb_tag3 lca$r_tb_tag3.lca$q_tb_tag3P#define lca$v_tb_tag3_bits lca$r_tb_tag3.lca$r_tb_tag3_fields.lca$v_tb_tag3_bits1#define lca$q_tb_tag4 lca$r_tb_tag4.lca$q_tb_tag4P#define lca$v_tb_tag4_bits lca$r_tb_tag4.lca$r_tb_tag4_fields.lca$v_tb_tag4_bits1#define lca$q_tb_tag5 lca$r_tb_tag5.lca$q_tb_tag5P#define 5lca$v_tb_tag5_bits lca$r_tb_tag5.lca$r_tb_tag5_fields.lca$v_tb_tag5_bits1#define lca$q_tb_tag6 lca$r_tb_tag6.lca$q_tb_tag6P#define lca$v_tb_tag6_bits lca$r_tb_tag6.lca$r_tb_tag6_fields.lca$v_tb_tag6_bits1#define lca$q_tb_tag7 lca$r_tb_tag7.lca$q_tb_tag7P#define lca$v_tb_tag7_bits lca$r_tb_tag7.lca$r_tb_tag7_fields.lca$v_tb_tag7_bits"#endif /* #if !defined(__VAXC) */ #define LCA$K_LENGTH 24576N/* */N/* DS1287A regis 5ter definitions */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _lca_ds1287a {#pragma __nomember_alignment- unsigned char lca_ds1287a$b_fill1 [3584];* unsigned int lca_ds1287a$l_port_index;+ unsigned c 5har lca_ds1287a$b_fill2 [28];) unsigned int lca_ds1287a$l_port_data;# char lca_ds1287a$b_fill_0_ [4]; } LCA_DS1287A;O#define LCA_TAG_IDLE_CPU$K_ENABLE 1 /* Enable Busy/Idle power management */P#define LCA_TAG_IDLE_CPU$K_DISABLE 2 /* Disable Busy/Idle power management */N#define LCA_TAG_IDLE_CPU$K_SET_SPEED 3 /* Set speed */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#p5ragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LCADEF_LOADED */ ww/p[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise5 Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not 5 **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************* 5***********************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */I/* Source: 30-NOV-2000 14:33:24 $1$DGA8345:[LIB_H.SRC]LCKCPUDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LCKCPUDEF ***/#ifndef __LCKCPUDEF_LOADED#define __LCKCPUDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __s5ave#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef 5__struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* LCKCPU - Lock manager per-CPU context block */N/* */N#define LCKCPU$K_LENGT5H 304 /* Length of LCKCPU */N#define LCKCPU$C_LENGTH 304 /* Length of LCKCPU */N#define LCKCPU$C_CACHE_MIN 128 /* low cache limit */N#define LCKCPU$C_CACHE_MAX 256 /* high cache limit */N#define LCKCPU$C_LKB_DPC_MAX 64 /* high LKB dpc limit */N#define LCKCPU$C_RSB_DPC_MAX 32 /* high RSB dpc limit */N#define LCKCPU$C_LCKRQ_CACHE_MIN 10 /* low L 5CKRQ cache limit */N#define LCKCPU$C_LCKRQ_CACHE_MAX 25 /* high LCKRQ cache limit */N#define LCKCPU$C_FORCE_TRIM_MIN 8 /* Trim to this if force trim set */O#define LCKCPU$C_FORCE_TRIM_MAX 16 /* Set max to this if force trim set */N#define LCKCPU$C_RECOVERY_INCREMENT 4 /* */  9#ifdef __cplusplus /* Define structure prototypes */ struct _cpu; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPO 5RT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _lckcpu {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lckcpu$q_link; /* link to next LCKCPU block */#else unsigned __int64 lckcpu$q_l 5ink;#endifN unsigned short int lckcpu$w_mbo; /* must-be-one field */N unsigned char lckcpu$b_type; /* structure type */N unsigned char lckcpu$b_subtype; /* structure sub-type */N int lckcpu$l_phy_id; /* CPU Id */N unsigned __int64 lckcpu$q_size; /* structure size */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma 5__required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _cpu *lckcpu$q_cpudb; /* pointer to per-CPU database */#else! unsigned __int64 lckcpu$q_cpudb;#endifN unsigned __int64 lckcpu$q_reserved1; /* reserved */N unsigned __int64 lckcpu$q_reserved2; /* reserved */N unsigned __int64 lckcpu$q_reserved3; /* reserved */N unsigned __int64 lckcpu$q_reserved4; /* reserv5ed */N unsigned __int64 lckcpu$q_lkb_alloc; /* LKB allocations out of cache */N unsigned __int64 lckcpu$q_rsb_alloc; /* RSB allocations out of cache */N unsigned __int64 lckcpu$l_enqnew_loc; /* new lock requests (local) */N unsigned __int64 lckcpu$l_enqnew_in; /* new lock requests (incoming) */N unsigned __int64 lckcpu$l_enqnew_out; /* new lock requests (outgoing) */N unsigned __int64 lckcpu$l_enqcvt_loc; /* conversion requests (local) 5*/N unsigned __int64 lckcpu$l_enqcvt_in; /* conversion requests (incoming) */N unsigned __int64 lckcpu$l_enqcvt_out; /* conversion requests (outgoing) */N unsigned __int64 lckcpu$l_deq_loc; /* dequeue requests (local) */N unsigned __int64 lckcpu$l_deq_in; /* dequeue requests (incoming) */N unsigned __int64 lckcpu$l_deq_out; /* dequeue requests (outgoing) */N unsigned __int64 lckcpu$l_enqwait; /* lock requests that has to wait */N unsigned __int64 l5ckcpu$l_enqnotqd; /* lock requests not queued */N unsigned __int64 lckcpu$l_blk_loc; /* blocking AST's (local) */N unsigned __int64 lckcpu$l_blk_in; /* blocking AST's (incoming) */N unsigned __int64 lckcpu$l_blk_out; /* blocking AST's (outgoing) */N unsigned __int64 lckcpu$l_dir_in; /* directory functions (incoming) */N unsigned __int64 lckcpu$l_dir_out; /* directory functions (outgoing) */- unsigned __int64 lckcpu$q_lkb_cache_link;- 5 unsigned __int64 lckcpu$q_rsb_cache_link;N unsigned int lckcpu$l_lkb_cache_count; /* LKB cache */( unsigned int lckcpu$l_lkb_cache_min;( unsigned int lckcpu$l_lkb_cache_max;N unsigned int lckcpu$l_rsb_cache_count; /* RSB cache */( unsigned int lckcpu$l_rsb_cache_min;( unsigned int lckcpu$l_rsb_cache_max;+ unsigned __int64 lckcpu$q_lkb_dpc_link;+ unsigned __int64 lckcpu$q_rsb_dpc_link;N unsigned int lckcpu$l_lkb_dpc_coun 5t; /* LKB delete pending cache queue */& unsigned int lckcpu$l_lkb_dpc_max;N unsigned int lckcpu$l_rsb_dpc_count; /* RSB delete pending cache queue */& unsigned int lckcpu$l_rsb_dpc_max;N unsigned int lckcpu$l_lckrq_cache_link; /* LCKRQ cache */, unsigned int lckcpu$l_lckrq_cache_count;* unsigned int lckcpu$l_lckrq_cache_min;* unsigned int lckcpu$l_lckrq_cache_max;W unsigned int lckcpu$l_force_trim; /* LBS forces LKB/RSB trim to recover memory */+5 unsigned int lckcpu$l_force_trim_count; } LCKCPU; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LCKCPUDEF_LOADED */ wwVp[UM/***************************************************************************/M/** 5 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** 5 **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 5 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:28 by OpenVMS SDL V3.7 */I/* Source: 01-SEP-1997 12:12:00 $1$DGA8345:[LIB_H.SRC]LCKCTXDEF.SDL;1 *//********************************************************************************************************************************//* 5** MODULE $LCKCTXDEF ***/#ifndef __LCKCTXDEF_LOADED#define __LCKCTXDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#end5if #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ 5 */N/* LCKCTX - LOCK CONTEXT BLOCK */N/* */N/*- */ #define LCKCTX$M_BUSY 0x1#define LCKCTX$M_CANCEL 0x2#define LCKCTX$M_CMP_RQD 0x4N#define LCKCTX$K_LEN 200 /* FIXED LENGTH */N#define LCKCTX$C_LEN 200 /* FIXED LENGTH */#d 5efine LCKCTX$S_LCKCTXDEF 200  9#ifdef __cplusplus /* Define structure prototypes */ struct _lkb; #endif /* #ifdef __cplusplus */ typedef struct _lckctx { __struct {N void *lckctx$l_fqfl; /* FORWARD LINK */N void *lckctx$l_fqbl; /* BACKWARD LINK */N unsigned short int lckctx$w_size; /* SIZE */N unsigned char lckctx$b_type; /* TYPE 5 */N unsigned char lckctx$b_flck; /* FORK LOCK */N unsigned int lckctx$l_fpc; /* FORK PC */N __int64 lckctx$q_fr3; /* FORK R3 */N __int64 lckctx$q_fr4; /* FORK R4 */ } lckctx$r_fork_block; __union {N unsigned int lckctx$l_flags; /* FLAGS */N __struct { /* FLAG BI 5TS */N unsigned lckctx$v_busy : 1; /* BUSY */N unsigned lckctx$v_cancel : 1; /* OPERATION CANCELED */N unsigned lckctx$v_cmp_rqd : 1; /* COMPLETION REQUIRED */* unsigned lckctx$v_fill_0_ : 5;# } lckctx$r_status_bits;! } lckctx$r_flags_overlay; char lckctx$b_fill_1_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V54.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _lkb *lckctx$q_lkb; /* LKB ADDRESS */#else unsigned __int64 lckctx$q_lkb;#endif#pragma __nomember_alignment __union { __struct {N unsigned __int645 lckctx$q_cr3; /* CALLER'S R3 */N unsigned __int64 lckctx$q_cr4; /* CALLER'S R4 */N unsigned __int64 lckctx$q_cr5; /* CALLER'S R5 */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lckctx$pq_ret1; /* STORAGE FOR SECOND RETURN */#else! unsigned __int64 lckctx$pq_re 5t1;#endifN unsigned __int64 lckctx$q_tmp1; /* TEMPORARY STORAGE */ } lckctx$r_s1; __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lckctx$pq_cpladr; /* COMPLETION NOTIFICATION ADDR */#else# unsigned __int64 lckctx$pq_cpladr;#endifN unsigned __int64 lckctx$q_cplprm; /* CON 5TEXT PARAMETER */ } lckctx$r_s2; } lckctx$r_u1; __union {N char lckctx$b_args [112]; /* WHOLE ARGUMENT LIST */N __struct { /* INDIVIDUAL ARGUMENTS */6 unsigned __int64 lckctx$q_enq_lock_acmode;1 unsigned __int64 lckctx$q_enq_lkmode;/ unsigned __int64 lckctx$q_enq_lksb;0 unsigned __int64 lckctx$q_enq_flags;1 unsigned __int64 lckctx$q_enq_ 5resnam;0 unsigned __int64 lckctx$q_enq_parid;2 unsigned __int64 lckctx$q_enq_cmp_adr;3 unsigned __int64 lckctx$q_enq_ctx_prm1;3 unsigned __int64 lckctx$q_enq_ctx_prm2;3 unsigned __int64 lckctx$q_enq_ctx_prm3;2 unsigned __int64 lckctx$q_enq_blk_adr;6 unsigned __int64 lckctx$q_enq_name_acmode;3 unsigned __int64 lckctx$q_enq_priority;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas 5supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers *// void *lckctx$pq_enq_req_acpted_adr;#else/ unsigned __int64 lckctx$pq_enq_req_acpted_adr;#endif% } lckctx$r_enq_arguments;N __struct { /* INDIVIDUAL ARGUMENTS */1 unsigned __int64 lckctx$q_deq_lockid;1 unsigned __int64 lckctx$q_deq_valblk;0 unsigned __int64 lckctx$q_deq_flags;3 5 unsigned __int64 lckctx$q_deq_ctx_prm1;3 unsigned __int64 lckctx$q_deq_ctx_prm2;3 unsigned __int64 lckctx$q_deq_ctx_prm3;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lckctx$pq_deq_retadr; /* DEQ arguments must not */#else' unsigned __int64 lckctx$pq_deq_retadr;#endifN/* overlap ENQ_CTX_PRM2 or later 5 */% } lckctx$r_deq_arguments; } lckctx$r_u2; } LCKCTX; #if !defined(__VAXC)7#define lckctx$l_fqfl lckctx$r_fork_block.lckctx$l_fqfl7#define lckctx$l_fqbl lckctx$r_fork_block.lckctx$l_fqbl7#define lckctx$w_size lckctx$r_fork_block.lckctx$w_size7#define lckctx$b_type lckctx$r_fork_block.lckctx$b_type7#define lckctx$b_flck lckctx$r_fork_block.lckctx$b_flck5#define lckctx$l_fpc lckctx$r_fork_block.lckctx$l_fpc5#define lckctx5$q_fr3 lckctx$r_fork_block.lckctx$q_fr35#define lckctx$q_fr4 lckctx$r_fork_block.lckctx$q_fr4<#define lckctx$l_flags lckctx$r_flags_overlay.lckctx$l_flagsO#define lckctx$v_busy lckctx$r_flags_overlay.lckctx$r_status_bits.lckctx$v_busyS#define lckctx$v_cancel lckctx$r_flags_overlay.lckctx$r_status_bits.lckctx$v_cancelU#define lckctx$v_cmp_rqd lckctx$r_flags_overlay.lckctx$r_status_bits.lckctx$v_cmp_rqd9#define lckctx$q_cr3 lckctx$r_u1.lckctx$r_s1.lckctx$q_cr39#define lckctx$q_cr4 lckctx$r_ 5u1.lckctx$r_s1.lckctx$q_cr49#define lckctx$q_cr5 lckctx$r_u1.lckctx$r_s1.lckctx$q_cr5=#define lckctx$pq_ret1 lckctx$r_u1.lckctx$r_s1.lckctx$pq_ret1;#define lckctx$q_tmp1 lckctx$r_u1.lckctx$r_s1.lckctx$q_tmp1A#define lckctx$pq_cpladr lckctx$r_u1.lckctx$r_s2.lckctx$pq_cpladr?#define lckctx$q_cplprm lckctx$r_u1.lckctx$r_s2.lckctx$q_cplprm/#define lckctx$b_args lckctx$r_u2.lckctx$b_args\#define lckctx$q_enq_lock_acmode lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_lock_acmodeR#define lckc5tx$q_enq_lkmode lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_lkmodeN#define lckctx$q_enq_lksb lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_lksbP#define lckctx$q_enq_flags lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_flagsR#define lckctx$q_enq_resnam lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_resnamP#define lckctx$q_enq_parid lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_paridT#define lckctx$q_enq_cmp_adr lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_cmp_adrV#define lckctx$q_enq5_ctx_prm1 lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_ctx_prm1V#define lckctx$q_enq_ctx_prm2 lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_ctx_prm2V#define lckctx$q_enq_ctx_prm3 lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_ctx_prm3T#define lckctx$q_enq_blk_adr lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_blk_adr\#define lckctx$q_enq_name_acmode lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_name_acmodeV#define lckctx$q_enq_priority lckctx$r_u2.lckctx$r_enq_arguments.lckctx$q_enq_prio5rityd#define lckctx$pq_enq_req_acpted_adr lckctx$r_u2.lckctx$r_enq_arguments.lckctx$pq_enq_req_acpted_adrR#define lckctx$q_deq_lockid lckctx$r_u2.lckctx$r_deq_arguments.lckctx$q_deq_lockidR#define lckctx$q_deq_valblk lckctx$r_u2.lckctx$r_deq_arguments.lckctx$q_deq_valblkP#define lckctx$q_deq_flags lckctx$r_u2.lckctx$r_deq_arguments.lckctx$q_deq_flagsV#define lckctx$q_deq_ctx_prm1 lckctx$r_u2.lckctx$r_deq_arguments.lckctx$q_deq_ctx_prm1V#define lckctx$q_deq_ctx_prm2 lckctx$r_u2.lckctx$r_deq_argum 5ents.lckctx$q_deq_ctx_prm2V#define lckctx$q_deq_ctx_prm3 lckctx$r_u2.lckctx$r_deq_arguments.lckctx$q_deq_ctx_prm3T#define lckctx$pq_deq_retadr lckctx$r_u2.lckctx$r_deq_arguments.lckctx$pq_deq_retadr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#e 5ndif#pragma __standard #endif /* __LCKCTXDEF_LOADED */ wwp[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior writ5ten permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS 5Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */I/* Source: 27-NOV-1997 09:13: 516 $1$DGA8345:[LIB_H.SRC]LCKDLBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LCKDLBDEF ***/#ifndef __LCKDLBDEF_LOADED#define __LCKDLBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __re5quired_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __un 5ion#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* LCKDLB - Lock manager deadlock context block */N/*- */N#define LCKDLB$K_LENGTH 24 /* Length of LCKDLB */N#define LCKDLB$C_LENGTH 24 /* Length of LCKDLB 5 */ typedef struct _lckdlb {" unsigned int lckdlb$l_maxerng;" unsigned int lckdlb$l_maxsrng; unsigned int lckdlb$l_prev; unsigned int lckdlb$l_sr4;" unsigned __int64 lckdlb$q_sr6; } LCKDLB; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __ 5standard #endif /* __LCKDLBDEF_LOADED */ ww p[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission o5f HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. 5 **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:37 by OpenVMS SDL V3.7 */I/* Source: 06-DEC-2000 18:11:46 $1$DGA8345:[L 5IB_H.SRC]LCKMGRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LCKMGRDEF ***/#ifndef __LCKMGRDEF_LOADED#define __LCKMGRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_s5ize __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defin 5ed(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* This macro defines the bit definitions for the global Lock Manager */N/* cell LCK$GL_FLAGS. */N/* */N/*- */#define LC 5KMGR$M_CLUINT 0x1#define LCKMGR$M_LCKINT 0x2#define LCKMGR$M_CHK_BTR 0x4#define LCKMGR$M_FRK_ENBL 0x8N#define LCKMGR$S_LCKMGRDEF 1 /* Old size name - synonym */ typedef struct _lckmgr {N unsigned lckmgr$v_cluint : 1; /* CLuster Init Complete */N unsigned lckmgr$v_lckint : 1; /* Lock Manager Init Complete */N unsigned lckmgr$v_chk_btr : 1; /* Check for better master */N unsigned lckmgr$v_frk_enbl : 1; /* F 5ork interface enabled */" unsigned lckmgr$v_fill_0_ : 4; } LCKMGR;N/* */N/* Define threshold values for dynamic remastering. */N/* */$#define LCKMGR$K_RM8SEC_ACT_THRSH 80$#define LCKMGR$K_RM8SEC_SYS_THRSH 80N/* Definitions for response codes for lock manager front end routines. */N/* 5 */N/* */N#define FRTN$K_QUEIT 0 /* request must be queued */N#define FRTN$K_GRNT1 1 /* request is compatible */_#define FRTN$K_GRNT2 2 /* rqst is compat, max-modes computed, grant waiters */b#define FRTN$K_GRNT3 3 /* rqst is compat, max-mode not computed, grant waiters */ Ntypede 5f struct _frtn_codes { /* front end routine response codes */ unsigned char frtn$b_codes; } FRTN_CODES;N/* */I/* Lock manager routine handling definitions */N/* */#define LCK$K_CH_CVT_GRANTED 1#define LCK$K_CH_QUEUED_EXIT 2#define LCK$K_CH_CVTNOTQED 3#define LCK$K_CH_LOCAL_CVT 4#define LCK$K_CH_F 5ORK_EXIT 5N/* */I/* Lock manager routine handling definitions */N/* */#define LCK$K_LH_LOCAL_LOCK 1#define LCK$K_LH_SYNC_EXIT 2#define LCK$K_LH_QUEUED_EXIT 3#define LCK$K_LH_NOT_QUEUED 4#define LCK$K_LH_FORK_EXIT 5N/* */I/* Lock Manager Flags 5 */N/* */#define LCKMGR$M_HC 0x1#define LCKMGR$M_PERCPU 0x2#define LCKMGR$C_OFF 0!#define LCKMGR$M_STATUS_BITS 0xFF!#define LCKMGR$M_MODE_BITS 0xFF00(#define LCKMGR$M_DISABLE_FAST_RM 0x10000)#define LCKMGR$M_RESERVED_UNUSED 0xFE0000&#define LCKMGR$M_CPUID_BITS 0xFF000000#define LCKMGR$M_STATUS 0xFF#define LCKMGR$M_MODE 0xFF00"#define LCKMGR$M_RESERVED 0xFF00005!#define LCKMGR$M_CPUID 0xFF000000 typedef struct _lckmgr_flags { __union {$ unsigned int lckmgr$l_flags; __struct { __union {. unsigned char lckmgr$b_status; __struct {- unsigned lckmgr$v_hc : 1;1 unsigned lckmgr$v_percpu : 1;2 unsigned lckmgr$v_fill_5_ : 6;' } lckmgr$r_fill_2_;# } lckmgr$r_fill_1_;( unsigned c 5har lckmgr$b_mode;, unsigned char lckmgr$b_reserved;) unsigned char lckmgr$b_cpuid;% } lckmgr$r_lckmgr_fields; __union {$ int lckmgr$l_flags_bits; __struct {2 unsigned lckmgr$v_status_bits : 8;0 unsigned lckmgr$v_mode_bits : 8;6 unsigned lckmgr$v_disable_fast_rm : 1;6 unsigned lckmgr$v_reserved_unused : 7;1 unsigned lckmgr$v_cpuid_bits : 8;# 5 } lckmgr$r_fill_4_; } lckmgr$r_fill_3_; __struct {) unsigned lckmgr$v_status : 8;' unsigned lckmgr$v_mode : 8;+ unsigned lckmgr$v_reserved : 8;( unsigned lckmgr$v_cpuid : 8;$ } lckmgr$r_lckmgr_masks;" } lckmgr$r_lckmgr_overlay; } LCKMGR_FLAGS; #if !defined(__VAXC)=#define lckmgr$l_flags lckmgr$r_lckmgr_overlay.lckmgr$l_flagsg#define lckmgr$b_status lckmgr$r_lckmgr_overlay.lckmgr$r_l5ckmgr_fields.lckmgr$r_fill_1_.lckmgr$b_statusp#define lckmgr$v_hc lckmgr$r_lckmgr_overlay.lckmgr$r_lckmgr_fields.lckmgr$r_fill_1_.lckmgr$r_fill_2_.lckmgr$v_hcx#define lckmgr$v_percpu lckmgr$r_lckmgr_overlay.lckmgr$r_lckmgr_fields.lckmgr$r_fill_1_.lckmgr$r_fill_2_.lckmgr$v_percpuR#define lckmgr$b_mode lckmgr$r_lckmgr_overlay.lckmgr$r_lckmgr_fields.lckmgr$b_modeZ#define lckmgr$b_reserved lckmgr$r_lckmgr_overlay.lckmgr$r_lckmgr_fields.lckmgr$b_reservedT#define lckmgr$b_cpuid lckmgr$r_lckmgr_overlay5.lckmgr$r_lckmgr_fields.lckmgr$b_cpuids#define lckmgr$v_disable_fast_rm lckmgr$r_lckmgr_overlay.lckmgr$r_fill_3_.lckmgr$r_fill_4_.lckmgr$v_disable_fast_rmU#define lckmgr$v_status lckmgr$r_lckmgr_overlay.lckmgr$r_lckmgr_masks.lckmgr$v_statusQ#define lckmgr$v_mode lckmgr$r_lckmgr_overlay.lckmgr$r_lckmgr_masks.lckmgr$v_modeY#define lckmgr$v_reserved lckmgr$r_lckmgr_overlay.lckmgr$r_lckmgr_masks.lckmgr$v_reservedS#define lckmgr$v_cpuid lckmgr$r_lckmgr_overlay.lckmgr$r_lckmgr_masks.lckmgr$v_cpuid5"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LCKMGRDEF_LOADED */ ww@Aq[UM/***************************************************************************/M/** 5 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** 5 **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M5/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */H/* Source: 05-APR-2004 12:13:44 $1$DGA8345:[LIB_H.SRC]LCKRQDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LCKRQDEF ** 5*/#ifndef __LCKRQDEF_LOADED#define __LCKRQDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cpluspl5us extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* LCKRQ - L5ock manager request block */N/* */#define LCKRQ$K_FREE 0#define LCKRQ$K_LOADED 1#define LCKRQ$K_WORKING 2#define LCKRQ$K_COMPLETE 3#define LCKRQ$K_DELETE 4#define LCKRQ$K_FINAL_PROC -1#define LCKRQ$K_RWSCS 1#define LCKRQ$K_ENQ -1#define LCKRQ$K_CVT 0#define LCKRQ$K_DEQ 1#define LCKRQ$M_BUSY 0x1N#define LCKRQ$K_LENGTH 320 /* Length of LCKRQ 5 */N#define LCKRQ$C_LENGTH 320 /* Length of LCKRQ */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _lckrq {#pragma __nomember_alignment __struct {% struct _lckrq *lckrq$l_flink;% struct _lckrq *lckrq$l_blink;( unsigned short int lckrq$w_size;# unsigned char lckr 5q$b_type;N unsigned char lckrq$b_flck; /* FORK LOCK */N unsigned int lckrq$l_fpc; /* FORK PC */N unsigned __int64 lckrq$q_fr3; /* FORK R3 */N unsigned __int64 lckrq$q_fr4; /* FORK R4 */ } lckrq$r_fork_block; unsigned int lckrq$l_state; char lckrq$b_fill_0_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using 5pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned int lckrq$l_lksb_status; /* lksb_status and lkid need */#pragma __nomember_alignmentN unsigned int lckrq$l_lkid; /* to be adjacent fields */ unsigned int lckrq$l_status; unsigned int lckrq$l_func; unsigned int lckrq$l_efn; unsigned int lckrq$l_lkmode; unsigned int lckrq$l_flags; unsigned int lckrq$l_parid; 5 unsigned int lckrq$l_acmode;# unsigned int lckrq$l_rng_flags;# unsigned int lckrq$l_prev_mode;" unsigned int lckrq$l_priority; unsigned int lckrq$l_pcb; unsigned int lckrq$l_rsnlen;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endif char lckrq$t_resnam [32];#pragma __nomember_alignment __union {c#if !defined(__NOBASEALIGN_S5UPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endif( unsigned int lckrq$q_valblk [4];" char lckrq$t_xvalblk [64];! } lckrq$r_valblk_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif" unsigned __int64 lckrq$q_lksb;#pra5gma __nomember_alignment$ unsigned __int64 lckrq$q_astadr;$ unsigned __int64 lckrq$q_astprm;$ unsigned __int64 lckrq$q_blkast;# unsigned int lckrq$l_savd_tpid;$ unsigned int lckrq$l_grp_acmode; unsigned int lckrq$l_rsdmid;' unsigned int lckrq$l_valblk_access;( unsigned __int64 lckrq$q_store_quad;" unsigned int lckrq$l_rqstsrng;" unsigned int lckrq$l_rqsterng; __union {' unsigned int lckrq$l_fkb_flags; __struct {& unsigned5 lckrq$v_busy : 1;) unsigned lckrq$v_fill_1_ : 7;" } lckrq$r_status_bits; } lckrq$r_flags_overlay; unsigned int lckrq$l_ktb;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif! unsigned __int64 lckrq$q_seq;#pragma __nomember_alignmentN char lckrq$t_align2 [48]; /* Fill cache line */ 5} LCKRQ; #if !defined(__VAXC)6#define lckrq$l_flink lckrq$r_fork_block.lckrq$l_flink6#define lckrq$l_blink lckrq$r_fork_block.lckrq$l_blink4#define lckrq$w_size lckrq$r_fork_block.lckrq$w_size4#define lckrq$b_type lckrq$r_fork_block.lckrq$b_type4#define lckrq$b_flck lckrq$r_fork_block.lckrq$b_flck2#define lckrq$l_fpc lckrq$r_fork_block.lckrq$l_fpc2#define lckrq$q_fr3 lckrq$r_fork_block.lckrq$q_fr32#define lckrq$q_fr4 lckrq$r_fork_block.lckrq$q_fr4<#define lckrq$q_valblk lckrq$r_valblk_ov 5erlay.lckrq$q_valblk>#define lckrq$t_xvalblk lckrq$r_valblk_overlay.lckrq$t_xvalblkA#define lckrq$l_fkb_flags lckrq$r_flags_overlay.lckrq$l_fkb_flagsK#define lckrq$v_busy lckrq$r_flags_overlay.lckrq$r_status_bits.lckrq$v_busy"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif5#ifdef __cplusplus }#endif#pragma __standard #endif /* __LCKRQDEF_LOADED */ ww`q[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone witho5ut the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prio5r written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */I/* 5 Source: 24-AUG-2001 04:04:28 $1$DGA8345:[LIB_H.SRC]LCKSTRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LCKSTRDEF ***/#ifndef __LCKSTRDEF_LOADED#define __LCKSTRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragma5s supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#end5if#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* LCKSTR - Lock manager structure context block */N/* */N#define LCKSTR$K_LENGTH 384 /* Length of LCKSTR */N#define LCKSTR$C_LENGTH 384 /* Len 5gth of LCKSTR */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _lckstr {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lckstr$q_fill1; /* res 5erved */#else! unsigned __int64 lckstr$q_fill1;#endifN unsigned short int lckstr$w_mbo; /* must-be-one field */N unsigned char lckstr$b_type; /* structure type */N unsigned char lckstr$b_subtype; /* structure sub-type */N int lckstr$l_fill2; /* reserved */N unsigned __int64 lckstr$q_size; /* structure size */R#ifdef __INITIAL_POI 5NTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lckstr$q_queuelock; /* pointer to queue lock */#else% unsigned __int64 lckstr$q_queuelock;#endifO unsigned __int64 lckstr$q_lckrq_table; /* pointer to LCKRQ address table */X unsigned __int64 lckstr$q_lckrq_curidx; /* current index into LCKRQ address table */V unsigned int lckstr$l_lckmgr_cpuid; /*5 CPU id, where lckmgr_server process runs */R unsigned int lckstr$l_lckmgr_pcb; /* PCB address of lckmgr_server process */N unsigned int lckstr$l_lckmgr_pid; /* PID of lckmgr_server process */N unsigned int lckstr$l_flag; /* flag */V unsigned __int64 lckstr$q_spin_count; /* number of times lckmgr was in spinloop */R unsigned __int64 lckstr$q_spin_time_acc; /* accumulated spin time in cycles */N unsigned __int64 lckstr$q_req_count; /* 5number of lock requests handled */S unsigned __int64 lckstr$q_req_time_acc; /* accumulated time to work requests */N unsigned int lckstr$l_overflow_queue; /* overflow queue */N unsigned int lckstr$l_overflow_shadow; /* overflow shadow queue */N unsigned int lckstr$l_sanity_counter; /* sanity check counter */ char lckstr$b_fill_0_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __ 5nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 lckstr$q_seq; /* sequence number */( unsigned __int64 lckstr$q_reserved1;#pragma __nomember_alignment( unsigned __int64 lckstr$q_reserved2;( unsigned __int64 lckstr$q_reserved3;( unsigned __int64 lckstr$q_reserved4;N char lckstr$t_align2 [104]; /* Assure 128 byte alignment */ __union {Y unsigned __int64 lckstr$q_lckrq_nxtidx; /* nex 5t index into LCKRQ address table */ __struct {( unsigned int lckstr$l_fill3;] unsigned int lckstr$l_lckrq_shadidx; /* shadow of current idx into LCKRQ table */ } lckstr$r_shadidx; } lckstr$r_idx_overlay;N char lckstr$t_align3 [120]; /* Assure 128 byte alignment */ } LCKSTR; #if !defined(__VAXC)H#define lckstr$q_lckrq_nxtidx lckstr$r_idx_overlay.lckstr$q_lckrq_nxtidxK#define lckstr$l_fill3 lckstr$r_idx_overlay.5lckstr$r_shadidx.lckstr$l_fill3[#define lckstr$l_lckrq_shadidx lckstr$r_idx_overlay.lckstr$r_shadidx.lckstr$l_lckrq_shadidx"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LCKSTRDEF_LOADED */ ww5q[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 20524 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software,5 Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */F/* Source: 03-MAY-2000 16:25:34 $1$DGA8345:[LIB_H.SRC]LCSDEF.SDL;1 *//******************************* 5*************************************************************************************************//*** MODULE $LCSDEF ***/#ifndef __LCSDEF_LOADED#define __LCSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pra5gma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_un 5ion#endif#endif N/* */N/* Structure(s) for RMS conversions between a local character set */N/* (e.g., Super DEC Kanji) and Unicode for filenames */N/* */N/* This structure, when inserted into the known extension queue, */N/* registers an RMS extension with the base RMS. It should contain */N 5/* entry points for a set of conversion functions for the selected */N/* local character set. */N/* */  N#define LCS$S_NAME 32 /* Maximum space for extension name */#define LCS$C_BLN 72#define LCS$K_BLN 72 typedef struct _lcs {N void *lcs$l_flink; /* links to next and previous */N void *lcs$l_blink; 5 /* registered LCS structures. */N unsigned short int lcs$w_size; /* allocated size of structure */N unsigned short int lcs$w_namlen; /* length of extension name */N char lcs$t_name [32]; /* space for extension name */g int (*lcs$a_calc_vtf7_to_local)(); /* Calculate length of converted string (in local code-set). */Z int (*lcs$a_conv_vtf7_to_local)(); /* Convert string from VTF-7 to local code-set. */^ int (*lcs$5a_calc_local_to_vtf7)(); /* Calculate length of converted string (in VTF-7). */Z int (*lcs$a_conv_local_to_vtf7)(); /* Convert string from local code-set to VTF-7. */i int (*lcs$a_conv_filesys_to_local)(); /* Convert string from File System format to local code-set. */n int (*lcs$a_build_local_pqb)(); /* Called by SYS$CREPRC to copy a LCS from a parent process to PQB. */l int (*lcs$a_restore_local_pqb)(); /* Called by EXE$PROCSTRT to copy a LCS from PQB to a subprocess. */ 5 } LCS; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LCSDEF_LOADED */ wwr[UM/***************************************************************************/M/** 5 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SO6FTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************************6****************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */F/* Source: 30-SEP-1999 14:42:18 $1$DGA8345:[LIB_H.SRC]LDBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LDBDEF ***/#ifndef __LDBDEF_LOADED#define __ 6LDBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_para6ms ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* $LOAD_DRIVER Data Block 6 */N/* */#define LDB$M_DDB 0x1#define LDB$M_CRB 0x2#define LDB$M_IDB 0x4#define LDB$M_UCB 0x8#define LDB$M_LINKED_UCB 0x10#define LDB$M_NOADAP 0x20#define LDB$M_CRBBLT 0x40#define LDB$M_SCBVEC 0x80#define LDB$M_REMOTE 0x100#define LDB$M_SCS 0x200#define LDB$M_SCSI_PORT 0x400#define LDB$M_ADD_UNIT 0x800#define LDB$M_SUD 0x1000W#define LDB$K_MAXVEC 32 /* maxim6um # of interrupt vectors per device */#define LDB$K_LENGTH 532#define LDB$C_LENGTH 532N#define LDB$S_LDBDEF 532 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _adp; struct _dpt; struct _sb; struct _ddb; struct _crb; struct _idb; struct _ucb; struct _fkb; #endif /* #ifdef __cplusplus */ typedef struct _ldb {N struct _ldb *ldb$ps_flink; /* Link to next LDB */N struct6 _ldb *ldb$ps_blink; /* Link to previous LDB */N unsigned short int ldb$w_size; /* size of this structure */N unsigned char ldb$b_type; /* structure type */N unsigned char ldb$b_subtype; /* structure subtype */N/* Status information */ __union {N unsigned int ldb$l_flags; /* control and status flags */ __struct {6N unsigned ldb$v_ddb : 1; /* built a DDB */N unsigned ldb$v_crb : 1; /* built a CRB */N unsigned ldb$v_idb : 1; /* built an IDB */N unsigned ldb$v_ucb : 1; /* built a UCB */S unsigned ldb$v_linked_ucb : 1; /* UCB has been linked into DDB chain */N unsigned ldb$v_noadap : 1; /* connect to NULL adapter */N unsign6ed ldb$v_crbblt : 1; /* SYSLOA_CRB item was specified */N unsigned ldb$v_scbvec : 1; /* VECTOR is offset into SCB */N unsigned ldb$v_remote : 1; /* device is on a remote system */N unsigned ldb$v_scs : 1; /* associated driver requires SCS */N unsigned ldb$v_scsi_port : 1; /* device is a SCSI port */N unsigned ldb$v_add_unit : 1; /* may be an "add unit" request */N unsigned ldb$v_sud : 1; /* b 6uilt a SUD */' unsigned ldb$v_fill_0_ : 3; } ldb$r_flags_bits; } ldb$r_flags_overlay;N/* Input items */N unsigned int ldb$l_unit; /* unit number to connect */N unsigned __int64 ldb$q_csr; /* CSR "magic number" */N unsigned __int64 ldb$q_sysid; /* SCS SYSID of controller */O unsigned int ldb$l_vector [32]; /* 6 byte offset into SCB/vector table */N unsigned int ldb$l_numvec; /* number of interrupt vectors */N unsigned int ldb$l_maxunits; /* maximum number of units allowed */N/* Input/Output items */N unsigned __int64 ldb$q_dlvr_data; /* working copy of deliver data */N void *ldb$ps_user_dlvr; /* address of caller's deliver data */N int ldb$l_numunits; /* number of units to conn 6ect now */N/* Output items */N struct _adp *ldb$ps_adp; /* address of ADaPter control block */N struct _dpt *ldb$ps_dpt; /* address of Driver Prologue Table */N struct _sb *ldb$ps_sb; /* address of System Block */N struct _ddb *ldb$ps_ddb; /* address of Device Data Block */N struct _crb *ldb$ps_crb; /* address of Channel Request Block */Q struct _ 6idb *ldb$ps_idb; /* address of Interrupt Dispatch Block */N struct _ucb *ldb$ps_ucb; /* address of Unit Control Block */N struct _fkb *ldb$ps_fork; /* address of associated fork block */N/* Working data */S struct _ddb *ldb$ps_lastddb; /* DDB address returned by IOC$SEARCHALL */N int ldb$il_dpt_maxunits; /* DPT's view of MAXUNITS */N __union { 6 /* name used when searching DPTLIST */N char ldb$t_dpt_name [16]; /* name stored in ASCIC format */ __struct {O unsigned char ldb$ib_dpt_namelen; /* character count in DPT_NAME */N char ldb$t_dpt_namestr [15]; /* actual string */ } ldb$r_ascic_name; } ldb$r_name_overlay;N int ldb$il_devlen; /* length of device name in DEVNAM */N void *ldb$ps_searchname; /* n6ame used for IOC$SEARCHALL */N int ldb$il_ddb_namelen; /* length of DEVNAM copied to DDB */N void *ldb$ps_ddb_name; /* beginning of name to copy to DDB */N char ldb$t_devnam [16]; /* name of device being connected */N __union { /* name of device driver to load */N char ldb$t_drvnam [256]; /* name stored in ASCIC format */ __struct {N unsigned char ldb$ib_drvnamlen; /* c 6haracter count in DRVNAM */N char ldb$t_drvnamstr [255]; /* actual string */! } ldb$r_ascic_drvnam; } ldb$r_drvnam_overlay; } LDB; #if !defined(__VAXC)3#define ldb$l_flags ldb$r_flags_overlay.ldb$l_flags@#define ldb$v_ddb ldb$r_flags_overlay.ldb$r_flags_bits.ldb$v_ddb@#define ldb$v_crb ldb$r_flags_overlay.ldb$r_flags_bits.ldb$v_crb@#define ldb$v_idb ldb$r_flags_overlay.ldb$r_flags_bits.ldb$v_idb@#define ldb$v_ucb ldb$r_flags_over6lay.ldb$r_flags_bits.ldb$v_ucbN#define ldb$v_linked_ucb ldb$r_flags_overlay.ldb$r_flags_bits.ldb$v_linked_ucbF#define ldb$v_noadap ldb$r_flags_overlay.ldb$r_flags_bits.ldb$v_noadapF#define ldb$v_crbblt ldb$r_flags_overlay.ldb$r_flags_bits.ldb$v_crbbltF#define ldb$v_scbvec ldb$r_flags_overlay.ldb$r_flags_bits.ldb$v_scbvecF#define ldb$v_remote ldb$r_flags_overlay.ldb$r_flags_bits.ldb$v_remote@#define ldb$v_scs ldb$r_flags_overlay.ldb$r_flags_bits.ldb$v_scsL#define ldb$v_scsi_port ldb$r_flags_over6lay.ldb$r_flags_bits.ldb$v_scsi_portJ#define ldb$v_add_unit ldb$r_flags_overlay.ldb$r_flags_bits.ldb$v_add_unit@#define ldb$v_sud ldb$r_flags_overlay.ldb$r_flags_bits.ldb$v_sud8#define ldb$t_dpt_name ldb$r_name_overlay.ldb$t_dpt_nameQ#define ldb$ib_dpt_namelen ldb$r_name_overlay.ldb$r_ascic_name.ldb$ib_dpt_namelenO#define ldb$t_dpt_namestr ldb$r_name_overlay.ldb$r_ascic_name.ldb$t_dpt_namestr6#define ldb$t_drvnam ldb$r_drvnam_overlay.ldb$t_drvnamQ#define ldb$ib_drvnamlen ldb$r_drvnam_overlay.6ldb$r_ascic_drvnam.ldb$ib_drvnamlenO#define ldb$t_drvnamstr ldb$r_drvnam_overlay.ldb$r_ascic_drvnam.ldb$t_drvnamstr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LDBDEF_LOADED */ wwRr[c5LCADEF5 LCKCPUDEF5 LCKCTXDEF5N LCKDLBDEF5> LCKMGRDEF5LCKRQDEF5j LCKSTRDEF5LCSDEF5\LDBDEF6LDCDEF6LDRDEF&6&LDRHPDEFB6 LDRIMGDEF` LDR_ROUTINES6UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright6 Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. 6 **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */G/* Source: 26-JAN-2022 23:16:38 $1$DGA8345:[LIB_H.SRC]LANUDEF.SDL;1 *//***************************************** 6***************************************************************************************//*** MODULE $LDCDEF ***/#ifndef __LDCDEF_LOADED#define __LDCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __requ6ired_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#end 6if#endif N/*++ */N/* LAN Device Characteristics structure */N/* */N/* This data structure is returned on a call to LAN$GET_DEVICE. It is */N/* embedded in the LSB. */N/*-- */ N#defin 6e LDC$K_LENGTH 40 /* Length of LDC block */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ldcdef {#pragma __nomember_alignmentN void *ldc$a_name; /* S-Address of a counted string */N/* containing the device name */N unsigned int ldc$l 6_type; /* Type of device - same as */N/* VCIB$W_DLL_TYPE */ __union {U unsigned short int ldc$w_rcvsize; /* Number of entries in the receive ring */U unsigned int ldc$l_rcvsize; /* S-Number of entries in the receive ring */ } ldc$r_rcvsize_overlay; __union {N unsigned char ldc$b_devtype; /* VMS Device type (from the UCB) */N unsigned int ldc$l_devtype; /* VMS6 Device type (from the UCB) */ } ldc$r_devtype_overlay;N unsigned int ldc$l_mopid; /* S-MOP ID for this device */N unsigned int ldc$l_mopname; /* S-Counted string (always three */N/* characters) for MOP name */N unsigned int ldc$l_linespeed; /* Line speed (in megabits/sec) */N unsigned int ldc$l_devspeed; /* Device speed (in megabits/sec) */N int ldc$l_tso_mtu; 6 /* Size of the TSO MTU */N int ldc$l_extra; /* Pad to quadword boundary */N/* Remember to make sure that this structure is an integral number of */N/* quadwords. That helps keep the LSB fields aligned. */ } LDCDEF; #if !defined(__VAXC)9#define ldc$w_rcvsize ldc$r_rcvsize_overlay.ldc$w_rcvsize9#define ldc$l_rcvsize ldc$r_rcvsize_overlay.ldc$l_rcvsize9#define ldc$b_devtype ldc$r_devtype_overlay.ldc$b_devtype9#d6efine ldc$l_devtype ldc$r_devtype_overlay.ldc$l_devtype"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LDCDEF_LOADED */ wwРr[UM/***************************************************6************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/ 6M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** !6 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */F/* Source: 04-JAN-2016 18:26:53 $1$DGA8345:[LIB_H.SRC]LDRDEF.SDL;1 *//***************************************************************************************************** "6***************************//*** MODULE $LDRDEF ***/#ifndef __LDRDEF_LOADED#define __LDRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 3#62-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define LDR$M_PAG 0x1#define LDR$M_UNL 0x$62#define LDR$M_OVR 0x4#define LDR$M_USER_BUF 0x8#define LDR$M_NO_SLICE 0x10#define LDR$M_SDA 0x20 typedef struct _ldr_dyn { __union { int ldr$l_bits; __struct {N unsigned ldr$v_pag : 1; /* If set, paging is disabled */N unsigned ldr$v_unl : 1; /* Image is unloadable */N unsigned ldr$v_ovr : 1; /* If set, do not overlay image */N unsigned ldr$v_user_buf : 1; /* Optional user bu %6ffer */N/* is specified on input */N unsigned ldr$v_no_slice : 1; /* Image is not to be sliced */N/* during load. */N unsigned ldr$v_sda : 1; /* This is the execlet for an */N/* SDA extension */' unsigned ldr$v_fill_2_ : 2; } ldr$r_fill_1_; } ldr$&6r_fill_0_; } LDR_DYN; #if !defined(__VAXC)7#define ldr$v_pag ldr$r_fill_0_.ldr$r_fill_1_.ldr$v_pag7#define ldr$v_unl ldr$r_fill_0_.ldr$r_fill_1_.ldr$v_unl7#define ldr$v_ovr ldr$r_fill_0_.ldr$r_fill_1_.ldr$v_ovrA#define ldr$v_user_buf ldr$r_fill_0_.ldr$r_fill_1_.ldr$v_user_bufA#define ldr$v_no_slice ldr$r_fill_0_.ldr$r_fill_1_.ldr$v_no_slice7#define ldr$v_sda ldr$r_fill_0_.ldr$r_fill_1_.ldr$v_sda"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#i'6fdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LDRDEF_LOADED */ wwr[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is(6 confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidenti)6al **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********* *6***********************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */H/* Source: 26-DEC-2018 16:35:47 $1$DGA8345:[LIB_H.SRC]LDRHPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LDRHPDEF ***/#ifndef __LDRHPDEF_LOADED#define __LDRHPDEF_LOADED 1 G#pragma __nostandard +6/* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else,6#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define LDRHP$K_CODE 0 /* execlet code UR */N#define LDRHP$K_DATA 1 /* execlet data URKW */N#define LDRHP$K_EXEC_D-6ATA 2 /* exec data area ERKW */N#define LDRHP$K_RES_CODE 3 /* resident code UR */N#define LDRHP$K_RES_DATA 4 /* resident data URKW */N#define LDRHP$K_EXEC_DATA_S2 5 /* S2 space exec data area ERKW */N#define LDRHP$K_CODE_S2 6 /* S2 space execlet code UR */N#define LDRHP$K_RES_CODE_S2 7 /* S2 space resident code UR */N#define LDRHP$K_DATA_S2 8 /* S2 sp .6ace execlet data area ERKW */N#define LDRHP$K_RO_DATA_S0 9 /* S0 read-only data UR for x86 */S#define LDRHP$K_RO_RES_DATA_S0 10 /* S0 read-only resident data UR for x86 */N#define LDRHP$K_RES_DATA_S2 11 /* S2 resident data for x86 */N#define LDRHP$K_NUM_TYPES 12 /* number of page types */#define LDRHP$M_ALLOC_FAIL 0x1#define LDRHP$M_RELEASED 0x2#define LDRHP$C_LENGTH 128#define LDRHP$K_LENGTH 128N#define LDRHP$S_LDRHPDEF 128 /6 /* Old size name - synonym */ typedef struct _ldrhp { __union {N unsigned __int64 ldrhp$q_type; /* type, code or data page */ __struct {( unsigned int ldrhp$l_type_l;( unsigned int ldrhp$l_type_h;" } ldrhp$r_type_fields; } ldrhp$r_type_overlay; __union {N unsigned __int64 ldrhp$q_size; /* size of huge page */ __struct {( unsigned int ldrhp$l_siz06e_l;( unsigned int ldrhp$l_size_h;" } ldrhp$r_size_fields; } ldrhp$r_size_overlay; __union {N __int64 ldrhp$q_va; /* Base VA of huge page */ __struct { void *ldrhp$l_va_l; int ldrhp$l_va_h; } ldrhp$r_va_fields; } ldrhp$r_va_overlay; __union {N __int64 ldrhp$q_pa; /* Base PA of huge page */ __struct { void *ld16rhp$l_pa_l; int ldrhp$l_pa_h; } ldrhp$r_pa_fields; } ldrhp$r_pa_overlay; __union {N unsigned __int64 ldrhp$q_slice_size; /* size of allocation quantity */ __struct {. unsigned int ldrhp$l_slice_size_l;. unsigned int ldrhp$l_slice_size_h;( } ldrhp$r_slice_size_fields;% } ldrhp$r_slice_size_overlay; __union {O unsigned __int64 ldrhp$q_next_slice; /* next available slice in page */ 26 __struct {. unsigned int ldrhp$l_next_slice_l;. unsigned int ldrhp$l_next_slice_h;( } ldrhp$r_next_slice_fields;% } ldrhp$r_next_slice_overlay; __union {N unsigned __int64 ldrhp$q_free_slices; /* free slices in page */ __struct {/ unsigned int ldrhp$l_free_slices_l;/ unsigned int ldrhp$l_free_slices_h;) } ldrhp$r_free_slices_fields;& } ldrhp$r_free_slices_overlay; 36__union {N unsigned __int64 ldrhp$q_used_slices; /* used slices in page */ __struct {/ unsigned int ldrhp$l_used_slices_l;/ unsigned int ldrhp$l_used_slices_h;) } ldrhp$r_used_slices_fields;& } ldrhp$r_used_slices_overlay; __union {W unsigned __int64 ldrhp$q_startup_pages; /* pages in use when LDR$WRAPUP runs */ __struct {1 unsigned int ldrhp$l_startup_pages_l;1 unsigned int ldr 46hp$l_startup_pages_h;+ } ldrhp$r_startup_pages_fields;( } ldrhp$r_startup_pages_overlay; __union {N unsigned __int64 ldrhp$q_bitmap_size; /* size of huge page bitmap */ __struct {/ unsigned int ldrhp$l_bitmap_size_l;/ unsigned int ldrhp$l_bitmap_size_h;) } ldrhp$r_bitmap_size_fields;& } ldrhp$r_bitmap_size_overlay; __union {N __int64 ldrhp$q_bitmap_va; /* base VA of huge page bitmap 56*/ __struct {& void *ldrhp$l_bitmap_va_l;$ int ldrhp$l_bitmap_va_h;' } ldrhp$r_bitmap_va_fields;$ } ldrhp$r_bitmap_va_overlay; __union {N unsigned __int64 ldrhp$q_flags; /* flags */ __struct {N unsigned ldrhp$v_alloc_fail : 1; /* allocation attempt failed */O unsigned ldrhp$v_released : 1; /* unused pfns have been released */) unsigned ldrhp$v_fill_0_ : 6; 66! } ldrhp$r_flags_bits; __struct {) unsigned int ldrhp$l_flags_l;) unsigned int ldrhp$l_flags_h;# } ldrhp$r_flags_fields; } ldrhp$r_flags_overlay; __union {T unsigned __int64 ldrhp$q_failpage_cnt; /* Count of pages in failed allocs */ __struct {0 unsigned int ldrhp$l_failpage_cnt_l;0 unsigned int ldrhp$l_failpage_cnt_h;* } ldrhp$r_failpage_cnt_fields;' } ldrhp$r_ 76failpage_cnt_overlay; __union {Q unsigned __int64 ldrhp$q_failpage_max; /* Size of biggest failed alloc */ __struct {0 unsigned int ldrhp$l_failpage_max_l;0 unsigned int ldrhp$l_failpage_max_h;* } ldrhp$r_failpage_max_fields;' } ldrhp$r_failpage_max_overlay; __union {N unsigned __int64 ldrhp$q_fail_pre_cnt; /* Count of failed allocs */N __struct { /* pre-LDR$WRAPUP */ 860 unsigned int ldrhp$l_fail_pre_cnt_l;0 unsigned int ldrhp$l_fail_pre_cnt_h;* } ldrhp$r_fail_pre_cnt_fields;' } ldrhp$r_fail_pre_cnt_overlay; __union {N unsigned __int64 ldrhp$q_fail_post_cnt; /* Count of failed allocs */N __struct { /* post-LDR$WRAPUP */1 unsigned int ldrhp$l_fail_post_cnt_l;1 unsigned int ldrhp$l_fail_post_cnt_h;+ } ldrhp$r_fail_post_cnt_fi 96elds;( } ldrhp$r_fail_post_cnt_overlay; } LDRHP; #if !defined(__VAXC)6#define ldrhp$q_type ldrhp$r_type_overlay.ldrhp$q_typeN#define ldrhp$l_type_l ldrhp$r_type_overlay.ldrhp$r_type_fields.ldrhp$l_type_lN#define ldrhp$l_type_h ldrhp$r_type_overlay.ldrhp$r_type_fields.ldrhp$l_type_h6#define ldrhp$q_size ldrhp$r_size_overlay.ldrhp$q_sizeN#define ldrhp$l_size_l ldrhp$r_size_overlay.ldrhp$r_size_fields.ldrhp$l_size_lN#define ldrhp$l_size_h ldrhp$r_size_overlay.ldrhp$r_size_fields. :6ldrhp$l_size_h0#define ldrhp$q_va ldrhp$r_va_overlay.ldrhp$q_vaF#define ldrhp$l_va_l ldrhp$r_va_overlay.ldrhp$r_va_fields.ldrhp$l_va_lF#define ldrhp$l_va_h ldrhp$r_va_overlay.ldrhp$r_va_fields.ldrhp$l_va_h0#define ldrhp$q_pa ldrhp$r_pa_overlay.ldrhp$q_paF#define ldrhp$l_pa_l ldrhp$r_pa_overlay.ldrhp$r_pa_fields.ldrhp$l_pa_lF#define ldrhp$l_pa_h ldrhp$r_pa_overlay.ldrhp$r_pa_fields.ldrhp$l_pa_hH#define ldrhp$q_slice_size ldrhp$r_slice_size_overlay.ldrhp$q_slice_sizef#define ldrhp$l_slice_size_l;6 ldrhp$r_slice_size_overlay.ldrhp$r_slice_size_fields.ldrhp$l_slice_size_lf#define ldrhp$l_slice_size_h ldrhp$r_slice_size_overlay.ldrhp$r_slice_size_fields.ldrhp$l_slice_size_hH#define ldrhp$q_next_slice ldrhp$r_next_slice_overlay.ldrhp$q_next_slicef#define ldrhp$l_next_slice_l ldrhp$r_next_slice_overlay.ldrhp$r_next_slice_fields.ldrhp$l_next_slice_lf#define ldrhp$l_next_slice_h ldrhp$r_next_slice_overlay.ldrhp$r_next_slice_fields.ldrhp$l_next_slice_hK#define ldrhp$q_free_slices ldrhp$r_free_sli<6ces_overlay.ldrhp$q_free_slicesj#define ldrhp$l_free_slices_l ldrhp$r_free_slices_overlay.ldrhp$r_free_slices_fields.ldrhp$l_free_slices_lj#define ldrhp$l_free_slices_h ldrhp$r_free_slices_overlay.ldrhp$r_free_slices_fields.ldrhp$l_free_slices_hK#define ldrhp$q_used_slices ldrhp$r_used_slices_overlay.ldrhp$q_used_slicesj#define ldrhp$l_used_slices_l ldrhp$r_used_slices_overlay.ldrhp$r_used_slices_fields.ldrhp$l_used_slices_lj#define ldrhp$l_used_slices_h ldrhp$r_used_slices_overlay.ldrhp$r_used=6_slices_fields.ldrhp$l_used_slices_hQ#define ldrhp$q_startup_pages ldrhp$r_startup_pages_overlay.ldrhp$q_startup_pagesr#define ldrhp$l_startup_pages_l ldrhp$r_startup_pages_overlay.ldrhp$r_startup_pages_fields.ldrhp$l_startup_pages_lr#define ldrhp$l_startup_pages_h ldrhp$r_startup_pages_overlay.ldrhp$r_startup_pages_fields.ldrhp$l_startup_pages_hK#define ldrhp$q_bitmap_size ldrhp$r_bitmap_size_overlay.ldrhp$q_bitmap_sizej#define ldrhp$l_bitmap_size_l ldrhp$r_bitmap_size_overlay.ldrhp$r_bitmap_s>6ize_fields.ldrhp$l_bitmap_size_lj#define ldrhp$l_bitmap_size_h ldrhp$r_bitmap_size_overlay.ldrhp$r_bitmap_size_fields.ldrhp$l_bitmap_size_hE#define ldrhp$q_bitmap_va ldrhp$r_bitmap_va_overlay.ldrhp$q_bitmap_vab#define ldrhp$l_bitmap_va_l ldrhp$r_bitmap_va_overlay.ldrhp$r_bitmap_va_fields.ldrhp$l_bitmap_va_lb#define ldrhp$l_bitmap_va_h ldrhp$r_bitmap_va_overlay.ldrhp$r_bitmap_va_fields.ldrhp$l_bitmap_va_h9#define ldrhp$q_flags ldrhp$r_flags_overlay.ldrhp$q_flagsC#define ldrhp$r_flags_bits ldrhp?6$r_flags_overlay.ldrhp$r_flags_bits@#define ldrhp$v_alloc_fail ldrhp$r_flags_bits.ldrhp$v_alloc_fail<#define ldrhp$v_released ldrhp$r_flags_bits.ldrhp$v_releasedR#define ldrhp$l_flags_l ldrhp$r_flags_overlay.ldrhp$r_flags_fields.ldrhp$l_flags_lR#define ldrhp$l_flags_h ldrhp$r_flags_overlay.ldrhp$r_flags_fields.ldrhp$l_flags_hN#define ldrhp$q_failpage_cnt ldrhp$r_failpage_cnt_overlay.ldrhp$q_failpage_cntn#define ldrhp$l_failpage_cnt_l ldrhp$r_failpage_cnt_overlay.ldrhp$r_failpage_cnt_fields.ldrh@6p$l_failpage_cnt_ln#define ldrhp$l_failpage_cnt_h ldrhp$r_failpage_cnt_overlay.ldrhp$r_failpage_cnt_fields.ldrhp$l_failpage_cnt_hN#define ldrhp$q_failpage_max ldrhp$r_failpage_max_overlay.ldrhp$q_failpage_maxn#define ldrhp$l_failpage_max_l ldrhp$r_failpage_max_overlay.ldrhp$r_failpage_max_fields.ldrhp$l_failpage_max_ln#define ldrhp$l_failpage_max_h ldrhp$r_failpage_max_overlay.ldrhp$r_failpage_max_fields.ldrhp$l_failpage_max_hN#define ldrhp$q_fail_pre_cnt ldrhp$r_fail_pre_cnt_overlay.ldrhp$q_failA6_pre_cntn#define ldrhp$l_fail_pre_cnt_l ldrhp$r_fail_pre_cnt_overlay.ldrhp$r_fail_pre_cnt_fields.ldrhp$l_fail_pre_cnt_ln#define ldrhp$l_fail_pre_cnt_h ldrhp$r_fail_pre_cnt_overlay.ldrhp$r_fail_pre_cnt_fields.ldrhp$l_fail_pre_cnt_hQ#define ldrhp$q_fail_post_cnt ldrhp$r_fail_post_cnt_overlay.ldrhp$q_fail_post_cntr#define ldrhp$l_fail_post_cnt_l ldrhp$r_fail_post_cnt_overlay.ldrhp$r_fail_post_cnt_fields.ldrhp$l_fail_post_cnt_lr#define ldrhp$l_fail_post_cnt_h ldrhp$r_fail_post_cnt_overlay.ldrhp$r_faB6il_post_cnt_fields.ldrhp$l_fail_post_cnt_h"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZE$#pragma __required_pointer_size save$#pragma __required_pointer_size longtypedef LDRHP * LDRHP_PQ;%#pragma __required_pointer_size shorttypedef LDRHP * LDRHP_PL;'#pragma __required_pointer_size restore#endif $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restC6ore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LDRHPDEF_LOADED */ ww@s[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **D6/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be uE6sed, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************************************************************* F6*/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */I/* Source: 10-JUL-2023 07:05:15 $1$DGA8345:[LIB_H.SRC]LDRIMGDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LDRIMGDEF ***/#ifndef __LDRIMGDEF_LOADED#define __LDRIMGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentG6R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#dH6efine __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ldrisd {#pragma __nomember_alignmentN unsigned __int64 ldrisd$iq_vbn; /* image s I6ection VBN */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */\ void *ldrisd$pq_base; /* process virtual image section base (relocated) */#else! unsigned __int64 ldrisd$pq_base;#endifr unsigned __int64 ldrisd$iq_len; /* image section length in memory (filled from filesz with demand zero) */R unsigned __int64 ldrisd$iq_link_baJ6se; /* image section offset (linker base) */d unsigned __int64 ldrisd$iq_link_end; /* image section end (unrelocated, rounded to 'bigpage') */]/* to avoid privileged applications depending on the size of LDRISD, the size is recorded) */N unsigned __int64 ldrisd$iq_filesz; /* image section length in file */N unsigned int ldrisd$i_type; /* ELF segment type */N short int ldrisd$w_size; /* size of this structure */N short int ldrisd$wK6_stx; /* section table index */N unsigned int ldrisd$i_flags; /* ELF segment flags */P int ldrisd$l_reserved_1; /* reserve some space for debug/patch */P __int64 ldrisd$q_reserved_2 [2]; /* reserve some space for debug/patch */ } LDRISD;Z/* In support of Shared Address Data (SAD), an LDRRQI is created for each needed image. */T/* the LDRRQI contains dynamic table entries for needed images, plus the register */X/* image L6signature to verify that the proper image is activated. (if not, SAD cannot */N/* be used for that image activation) */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ldrrqi {#pragma __nomember_alignmentP __int64 ldrrqi$q_needed; /* strtab index for needed image name */Z __int64 ld M6rrqi$q_needed_ident; /* image ident (required IDENT of needed image) */N __int64 ldrrqi$q_fixup_rela_cnt; /* count of fixups */N __int64 ldrrqi$q_fixup_rela_off; /* dynseg offset to firs fixup */N char ldrrqi$b_risig [32]; /* image signiture */P __int64 ldrrqi$q_reserved [2]; /* reserve some space for debug/patch */ } LDRRQI;#define LDRIMG$M_NOT_XQP 0x1#define LDRIMG$M_DELAY_INIT 0x2#define LDRIMG$M_NO_PFN_DBN6 0x4#define LDRIMG$M_NOOVERLAY 0x8#define LDRIMG$M_CAN_UNL 0x10#define LDRIMG$M_UNL_PEN 0x20#define LDRIMG$M_SYNC 0x40#define LDRIMG$M_VALID 0x80"#define LDRIMG$M_GSTVA_VALID 0x100"#define LDRIMG$M_PAGED_RELOC 0x200%#define LDRIMG$M_NONPAGED_RELOC 0x400##define LDRIMG$M_PAGED_FIXUPS 0x800'#define LDRIMG$M_NONPAGED_FIXUPS 0x1000)#define LDRIMG$M_SECOND_PASS_FIXUP 0x2000 #define LDRIMG$M_NO_SLICE 0x4000 #define LDRIMG$M_DYN_LOAD 0x8000$#define LDRIMG$M_NPAGED_LOAD 0x10000##defO6ine LDRIMG$M_MSG_LOADED 0x20000$#define LDRIMG$M_INITIALIZED 0x40000"#define LDRIMG$M_INIT_GONE 0x80000#define LDRIMG$M_SDA 0x100000#define LDRIMG$C_LENGTH 296#define LDRIMG$K_LENGTH 296N#define LDRIMG$S_LDRIMGDEF 296 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _wcb; struct _imcb;struct _transfer_address;struct _spf_blk; struct _char; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_S P6UPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ldrimg {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _ldrimg *ldrimg$pq_flink; /* forward link */#else" unsigned __int64 ldrimg Q6$pq_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _ldrimg *ldrimg$pq_blink; /* backward link */#else" unsigned __int64 ldrimg$pq_blink;#endifN unsigned short int ldrimg$w_size; /* structure size */N unsigned char ldrimg$b_type; /* DYN$C_LOADCODE */N unsigned char R6ldrimg$b_subtype; /* DYN$C_LDRIMG */ __union {N unsigned int ldrimg$l_flags; /* status flags */ __struct {N unsigned ldrimg$v_not_xqp : 1; /* not opened by XQP */P unsigned ldrimg$v_delay_init : 1; /* needs delayed initialization */O unsigned ldrimg$v_no_pfn_db : 1; /* no PFN data base when loaded */N unsigned ldrimg$v_nooverlay : 1; /* not overlaid by bugcheck */N S6 unsigned ldrimg$v_can_unl : 1; /* unloadable exec image */N unsigned ldrimg$v_unl_pen : 1; /* exec image unload is pending */N unsigned ldrimg$v_sync : 1; /* synchronize access to this block */O unsigned ldrimg$v_valid : 1; /* contents of this block are valid */S unsigned ldrimg$v_gstva_valid : 1; /* GSTVA contains a valid address */N unsigned ldrimg$v_paged_reloc : 1; /* paged relocations done */Q unsignedT6 ldrimg$v_nonpaged_reloc : 1; /* nonpaged relocations done */N unsigned ldrimg$v_paged_fixups : 1; /* paged fix-ups done */O unsigned ldrimg$v_nonpaged_fixups : 1; /* Non-paged fix-ups done */R unsigned ldrimg$v_second_pass_fixup : 1; /* 2nd pass fixup required */N unsigned ldrimg$v_no_slice : 1; /* execlet not sliced */N unsigned ldrimg$v_dyn_load : 1; /* loaded by dynamic loader */O unsigned ldrimg$v_npagedU6_load : 1; /* paged code loaded nonpaged */P unsigned ldrimg$v_msg_loaded : 1; /* message section found/loaded */N unsigned ldrimg$v_initialized : 1; /* initialization complete */O unsigned ldrimg$v_init_gone : 1; /* when set, init sections have */N/* been deallocated - I64 only */N unsigned ldrimg$v_sda : 1; /* This is the execlet for an */N/* SDA extension V6 */* unsigned ldrimg$v_fill_0_ : 3;" } ldrimg$r_flags_bits;! } ldrimg$r_flags_overlay;N unsigned __int64 ldrimg$q_linktime; /* link time */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N int (*ldrimg$pq_init_rtn)(); /* delayed initialization routine */#else% unsigned __int64 ldri W6mg$pq_init_rtn;#endifN int ldrimg$l_version; /* image version */N unsigned int ldrimg$l_fill1; /* Correct alignment */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _wcb *ldrimg$pq_wcb; /* WCB pointer */#else unsigned __int64 ldrimg$pq_wcb;#endifN int ldrimg X6$l_pid; /* pid of proc attempting load */N int ldrimg$l_chan; /* chan number */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ldrimg$pq_basimgvec; /* VA of list of base image vectors */#else& unsigned __int64 ldrimg$pq_basimgvec;#endifP int ldrimg$l_num_basvec; /* numbe Y6r of base image contributions */N int ldrimg$l_seq; /* sequence number */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ldrimg$pq_unlvec; /* VA of unload routine vector */#else# unsigned __int64 ldrimg$pq_unlvec;#endifN unsigned int ldrimg$l_fill2; /* correct alignment */N Z6 int ldrimg$l_refcnt; /* number of references pending */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ldrimg$pq_symvva; /* Address of symbol vector */#else# unsigned __int64 ldrimg$pq_symvva;#endifN unsigned int ldrimg$l_symv_count; /* count of symbol vector entries */R unsigned int ldrimg$l_anomoly; [6 /* count of unusual conditions detected */N/* while loading this image */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */O void *ldrimg$pq_ssvec; /* Address of system service vectors */#else" unsigned __int64 ldrimg$pq_ssvec;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas \6supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ldrimg$pq_fst; /* Address of FST for boot time IO */#else unsigned __int64 ldrimg$pq_fst;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Z void *ldrimg$pq_vec_segment; /* Address of segment(isect) with VEC attribute */#e ]6lse( unsigned __int64 ldrimg$pq_vec_segment;#endifN unsigned int ldrimg$l_segcount; /* count of segments */N unsigned int ldrimg$l_imgnamlen; /* count for image name */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _ldrisd *ldrimg$pq_segments; /* pointer to ISD array */#else% unsigned __int64 ldrimg$p ^6q_segments;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */P struct _ldrisd *ldrimg$pq_dyn_seg; /* pointer to the dynamic segment ISD */#else$ unsigned __int64 ldrimg$pq_dyn_seg;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers _6*/N char *ldrimg$pq_imgnam; /* image name string */#else# unsigned __int64 ldrimg$pq_imgnam;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */R struct _imcb *ldrimg$pq_imcb; /* pointer to IMCB (for process iamges) */#else! unsigned __int64 ldrimg$pq_imcb;#endifN unsigned int ldrimg$l_needed_count; /* count of need `6ed images */N unsigned int ldrimg$l_link_flags; /* linker flags (DT_VMS_LNKFLAGS) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */[ struct _transfer_address *ldrimg$p_tfradr; /* pointer to ELF transfer adress struct. */#else" unsigned __int64 ldrimg$p_tfradr;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported a6*/Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */^ struct _ldrimg (*(*ldrimg$pq_needed)); /* pointer to array of pointers to needed images */#else# unsigned __int64 ldrimg$pq_needed;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Z struct _spf_blk (*(*ldrimg$pq_needed_spf)); /* array of pointers to 2nd pass fix b6ups */#else' unsigned __int64 ldrimg$pq_needed_spf;#endifN unsigned int ldrimg$l_ldrimg_size; /* length of the LDRIMG structure. */N unsigned int ldrimg$l_ldrisd_size; /* length of each LDRISD structure. */N unsigned int ldrimg$l_xlated; /* translated image type. */N unsigned int ldrimg$l_public_image_index; /* */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __lo c6ng /* And set ptr size default to 64-bit pointers */Q void *ldrimg$pq_public_image_flink; /* queue element for "public" execlets */#else/ unsigned __int64 ldrimg$pq_public_image_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */' void *ldrimg$pq_public_image_blink;#else/ unsigned __int64 ldrimg$pq_public_image_blink;#endifR#ifdef __INITIAL d6_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _ldrrqi *ldrimg$pq_ldrrqi; /* pointer to array of LDRRQI */#else# unsigned __int64 ldrimg$pq_ldrrqi;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _char *ldrimg$pq_strtab; e6 /* pointer to string table */#else# unsigned __int64 ldrimg$pq_strtab;#endifN __int64 ldrimg$q_reserved_1; /* reserved space for debug/patch */P __int64 ldrimg$q_reserved_2 [4]; /* reserve some space for debug/patch */ } LDRIMG; #if !defined(__VAXC)<#define ldrimg$l_flags ldrimg$r_flags_overlay.ldrimg$l_flagsF#define ldrimg$r_flags_bits ldrimg$r_flags_overlay.ldrimg$r_flags_bits=#define ldrimg$v_not_xqp ldrimg$r_flags_bits.ldrimg$v_not_xqpC#definf6e ldrimg$v_delay_init ldrimg$r_flags_bits.ldrimg$v_delay_initA#define ldrimg$v_no_pfn_db ldrimg$r_flags_bits.ldrimg$v_no_pfn_dbA#define ldrimg$v_nooverlay ldrimg$r_flags_bits.ldrimg$v_nooverlay=#define ldrimg$v_can_unl ldrimg$r_flags_bits.ldrimg$v_can_unl=#define ldrimg$v_unl_pen ldrimg$r_flags_bits.ldrimg$v_unl_pen7#define ldrimg$v_sync ldrimg$r_flags_bits.ldrimg$v_sync9#define ldrimg$v_valid ldrimg$r_flags_bits.ldrimg$v_validE#define ldrimg$v_gstva_valid ldrimg$r_flags_bits.ldrimg$v_gsg6tva_validE#define ldrimg$v_paged_reloc ldrimg$r_flags_bits.ldrimg$v_paged_relocK#define ldrimg$v_nonpaged_reloc ldrimg$r_flags_bits.ldrimg$v_nonpaged_relocG#define ldrimg$v_paged_fixups ldrimg$r_flags_bits.ldrimg$v_paged_fixupsM#define ldrimg$v_nonpaged_fixups ldrimg$r_flags_bits.ldrimg$v_nonpaged_fixupsQ#define ldrimg$v_second_pass_fixup ldrimg$r_flags_bits.ldrimg$v_second_pass_fixup?#define ldrimg$v_no_slice ldrimg$r_flags_bits.ldrimg$v_no_slice?#define ldrimg$v_dyn_load ldrimg$r_flags h6_bits.ldrimg$v_dyn_loadE#define ldrimg$v_npaged_load ldrimg$r_flags_bits.ldrimg$v_npaged_loadC#define ldrimg$v_msg_loaded ldrimg$r_flags_bits.ldrimg$v_msg_loadedE#define ldrimg$v_initialized ldrimg$r_flags_bits.ldrimg$v_initializedA#define ldrimg$v_init_gone ldrimg$r_flags_bits.ldrimg$v_init_gone5#define ldrimg$v_sda ldrimg$r_flags_bits.ldrimg$v_sda"#endif /* #if !defined(__VAXC) */  typedef struct _ldrhdl {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas su i6pported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ldrhdl$pq_base; /* base virtual address */#else! unsigned __int64 ldrhdl$pq_base;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */P struct _ldrimg *ldrhdl$pq_ldrimg; /* ldrimg address of the loaded image */#else# unsj6igned __int64 ldrhdl$pq_ldrimg;#endifN int ldrhdl$l_seq; /* sequence number */ } LDRHDL;  0#define ALLOCA_LDRHDL() __ALLOCA(sizeof(LDRHDL))#ifdef __x86_64X#define SET_LDRHDL(H,B,L,S) H->ldrhdl$pq_base=B; H->ldrhdl$pq_ldrimg=L;H->ldrhdl$l_seq=S#elseV#define SET_LDRHDL(H,B,L,S) H->ldrhdl$l_base=B; H->ldrhdl$l_ldrimg=L;H->ldrhdl$l_seq=S#endifN/* Generic names for common fields with different sizes. */ 3#define ldrhdl k6$$_base ldrhdl$pq_base5#define ldrhdl$$_ldrimg ldrhdl$pq_ldrimg3#define ldrimg$$_basimgvec ldrimg$pq_basimgvec,#define ldrimg$$_blink ldrimg$pq_blink/#define ldrimg$$_dyn_seg ldrimg$pq_dyn_seg,#define ldrimg$$_flink ldrimg$pq_flink(#define ldrimg$$_fst ldrimg$pq_fst*#define ldrimg$$_imcb ldrimg$pq_imcb.#define ldrimg$$_imgnam ldrimg$pq_imgnam7#define ldrimg$$_init_rtn ldrimg$pq_init_rtn.#define ldrimg$$_ldrrq l6i ldrimg$pq_ldrrqi.#define ldrimg$$_needed ldrimg$pq_needed9#define ldrimg$$_needed_spf ldrimg$pq_needed_spfA#define ldrimg$$_public_image_blink ldrimg$pq_public_image_blinkA#define ldrimg$$_public_image_flink ldrimg$pq_public_image_flink1#define ldrimg$$_segments ldrimg$pq_segments,#define ldrimg$$_ssvec ldrimg$pq_ssvec5#define ldrimg$$_strtab ldrimg$pq_strtab.#define ldrimg$$_symvva ldrimg$pq_symvva5#define ldrimg$$_unlvec m6 ldrimg$pq_unlvec:#define ldrimg$$_vec_segment ldrimg$pq_vec_segment(#define ldrimg$$_wcb ldrimg$pq_wcb*#define ldrisd$$_base ldrisd$pq_base.#define ldrisd$$_filesz ldrisd$iq_filesz(#define ldrisd$$_len ldrisd$iq_len3#define ldrisd$$_link_base ldrisd$iq_link_base1#define ldrisd$$_link_end ldrisd$iq_link_end(#define ldrisd$$_vbn ldrisd$iq_vbn  #ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save&#pragma __required_pn6ointer_size __longtypedef LDRIMG * LDRIMG_PQ;typedef LDRIMG ** LDRIMG_PPQ;typedef LDRISD * LDRISD_PQ;typedef LDRISD ** LDRISD_PPQ;typedef LDRHDL * LDRHDL_PQ;'#pragma __required_pointer_size __shorttypedef LDRIMG * LDRIMG_PL;typedef LDRIMG ** LDRIMG_PPL;typedef LDRISD * LDRISD_PL;typedef LDRISD ** LDRISD_PPL;typedef LDRHDL * LDRHDL_PL;)#pragma __required_pointer_size __restore#elsetypedef __int64 LDRIMG_PQ;typedef __int64 LDRIMG_PPQ;typedef __int32 LDRIMG_PL;o6typedef __int32 LDRIMG_PPL;typedef __int64 LDRISD_PQ;typedef __int64 LDRISD_PPQ;typedef __int32 LDRISD_PL;typedef __int32 LDRISD_PPL;typedef __int32 LDRHDL_PQ;typedef __int64 LDRHDL_PL;,#endif /* __INITIAL_POINTER_SIZE */ #ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save&#pragma __required_pointer_size __longtypedef LDRRQI * LDRRQI_PQ;'#pragma __required_pointer_size __shorttypedef LDRRQI * LDRRQI_PL;)#pragma __required_pointer_size __restp6ore#elsetypedef __int64 LDRRQI_PQ;typedef __int32 LDRRQI_PL;,#endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LDRIMGDEF_LOADED */ ww`t[UM/*********************************q6******************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development,r6 LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** s6 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************* t6***********************************************//*** MODULE $LEVTDEF ***/#ifndef __LEVTDEF_LOADED#define __LEVTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And setu6 ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ v6 */N/* Local Event block for passing an event to the event logger */N/*-- */N#define LEVT$K_LENGTH 74 /* Size of Event */ typedef struct _levtdef {+ unsigned short int levt$w_eventtypelen;+ unsigned short int levt$w_eventtypetag;" unsigned int levt$l_eventtype;+ unsigned short int levt$w_entityuidlen;+ w6 unsigned short int levt$w_entityuidtag;& unsigned int levt$o_entityuid [4];+ unsigned short int levt$w_eventtimelen;+ unsigned short int levt$w_eventtimetag;& unsigned int levt$o_eventtime [4];* unsigned short int levt$w_eventuidlen;* unsigned short int levt$w_eventuidtag;% unsigned int levt$o_eventuid [4];, unsigned short int levt$w_entitynamelen;, unsigned short int levt$w_entitynametag;) unsigned short int levt$w_entityname; } LEVTDEF;  $#px6ragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LEVTDEF_LOADED */ wwNt[UM/***************************************************************************/M/** **/y6M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. Cz6ONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************************{6**************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:38 by OpenVMS SDL V3.7 */I/* Source: 13-DEC-2018 14:10:45 $1$DGA8345:[LIB_H.SRC]LGIINTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LGIINTDEF ***/#ifndef __LGIINTDEF_LOADED#define __LGII |6NTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params}6 ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define LGI$C_LENGTH 24 /* Data structure length */N#define LGI$K_LENGTH 24 /* Data structure ~6length */N#define LGI$C_CHARTIME 15 /* Terminal driver timeout value */N#define LGI$K_CHARTIME 15 /* Terminal driver timeout value */N#define LGI$S_LGIDATDEF 24 /* Old size name - synonym */ typedef struct _lgidat {O unsigned int lgi$l_origuic; /* Original UIC at job creation time */Q char lgi$t_outfnm [20]; /* For batch, file name/type of output */N/* for spooling log file in batch jobs 6 */ } LGIDAT;#define LGI$M_OPENACCT 0x1#define LGI$M_PASSWORD 0x2#define LGI$M_PASSWORD2 0x4#define LGI$M_GENPWD 0x8N#define LGI$_PRIMARY_PASSWORD 1 /* primary password */N#define LGI$_SECONDARY_PASSWORD 2 /* secondary password */N#define LGI$_SOURCE_NODE 3 /* source nodename */N#define LGI$_SOURCE_ID 4 /* source id (username) */N#define LGI$_SOURCE_ADDRES6S 5 /* source DECnet address */N#define LGI$_SOURCE_TERMINAL 6 /* source terminal */N#define LGI$_PARENT_USERNAME 7 /* parent username */N#define LGI$_PARENT_PID 8 /* parent PID */N#define LGI$_JOB_TYPE 9 /* job type */N#define LGI$_MAX_CODE 10 /* last item code (plus one) */N#define LGI$S_LGIAUTHDEF 4 /* Old size 6name - synonym */ typedef struct _lgiauth { __union {& unsigned int lgi$l_auth_flags; __struct {N unsigned lgi$v_openacct : 1; /* account requires no passwords */N unsigned lgi$v_password : 1; /* account has primary password */N unsigned lgi$v_password2 : 1; /* account has secondary password */N unsigned lgi$v_genpwd : 1; /* Extra bit returned by the */N/* VMS ACME for the old 6 */N/* DECwindows login */' unsigned lgi$v_fill_2_ : 4; } lgi$r_fill_1_; } lgi$r_fill_0_; } LGIAUTH; #if !defined(__VAXC)7#define lgi$l_auth_flags lgi$r_fill_0_.lgi$l_auth_flagsA#define lgi$v_openacct lgi$r_fill_0_.lgi$r_fill_1_.lgi$v_openacctA#define lgi$v_password lgi$r_fill_0_.lgi$r_fill_1_.lgi$v_passwordC#define lgi$v_password2 lgi$r_fill_0_.lgi$r_fill_1_.lgi$v_pa 6ssword2=#define lgi$v_genpwd lgi$r_fill_0_.lgi$r_fill_1_.lgi$v_genpwd"#endif /* #if !defined(__VAXC) */ N#define LGI$_DISUSER_STOP 1 /* stop on error */N#define LGI$_DISUSER_RETURN 2 /* return on error */N#define LGI$_VALIDATE_STOP 1 /* stop on error */N#define LGI$_VALIDATE_RETURN 2 /* return on error */N#define LGI$_GET_INPUT_STOP 0 /* stop on error 6 */N#define LGI$_GET_INPUT_HANGUP 1 /* hangup quietly on error */N#define LGI$_GET_INPUT_RETURN_TMO 2 /* return on timout */#define LGI$M_NET_PROXY 0x1#define LGI$M_NET_PREAUTH 0x2"#define LGI$M_NET_DEFAULT_USER 0x4#define LGI$M_NET_PROXY_OK 0x8'#define LGI$M_NET_REM_INFO_PRESENT 0x10N#define LGI$S_LGINETDEF 2 /* Old size name - synonym */ typedef struct _lginet { __union {0 unsigned short int lgi$w_net_aut6h_flags; __struct {N unsigned lgi$v_net_proxy : 1; /* DECNET wants proxy login */N unsigned lgi$v_net_preauth : 1; /* DECNET has authenticated */T unsigned lgi$v_net_default_user : 1; /* DECNET application or session */N/* database has username */N unsigned lgi$v_net_proxy_ok : 1; /* (local use) proxy validated */T unsigned lgi$v_net_rem_info_present : 1; /* Phase V prov 6ided rem info */' unsigned lgi$v_fill_5_ : 3; } lgi$r_fill_4_; } lgi$r_fill_3_; } LGINET; #if !defined(__VAXC)?#define lgi$w_net_auth_flags lgi$r_fill_3_.lgi$w_net_auth_flagsC#define lgi$v_net_proxy lgi$r_fill_3_.lgi$r_fill_4_.lgi$v_net_proxyG#define lgi$v_net_preauth lgi$r_fill_3_.lgi$r_fill_4_.lgi$v_net_preauthQ#define lgi$v_net_default_user lgi$r_fill_3_.lgi$r_fill_4_.lgi$v_net_default_userI#define lgi$v_net_proxy_ok lgi$r_fill_3_.lgi$r_fill_4_6.lgi$v_net_proxy_okY#define lgi$v_net_rem_info_present lgi$r_fill_3_.lgi$r_fill_4_.lgi$v_net_rem_info_present"#endif /* #if !defined(__VAXC) */   9#ifdef __cplusplus /* Define structure prototypes */ struct _rab; #endif /* #ifdef __cplusplus */ typedef struct _lgiarg_vector {N int (*lgi$icb_get_input)(); /* Addresses of callbacks */ int (*lgi$icb_decw_ident)(); int (*lgi$icb_decw_auth)();! void (*lgi$icb_get_syspwd)(); int (*lgi$6icb_userprompt)(); int (*lgi$icb_userparse)(); int (*lgi$icb_autologin)(); int (*lgi$icb_password)(); int (*lgi$icb_check_pass)(); int (*lgi$icb_validate)();" void (*lgi$icb_acctexpired)();! void (*lgi$icb_pwdexpired)(); int (*lgi$icb_disuser)();! void (*lgi$icb_modalhours)();N void *lgi$a_icr_creprc_flags; /* Addresses of variables */ char *lgi$a_icr_job_type; char *lgi$a_icr_subprocess;! char *lgi$a_icr_terminal_dev;6! void *lgi$a_icr_tt_phydevnam;! void *lgi$a_icr_tt_accpornam; void *lgi$a_icr_cliname; void *lgi$a_icr_clitables; void *lgi$a_icr_ncb; void *lgi$a_icr_loglink;! void *lgi$a_icr_rem_node_nam; void *lgi$a_icr_rem_id; void *lgi$a_icr_uaf_record;% struct _rab *lgi$a_icr_input_rab; char *lgi$a_icr_autologin; void *lgi$a_icr_username; void *lgi$a_icr_pwd1; void *lgi$a_icr_pwd2; void *lgi$a_icr_pwdcount; void *lgi$a_icr_ne6tflags; } LGIARG_VECTOR;#define LGI$ICR_INIT 4#define LGI$ICR_IACT_START 8#define LGI$ICR_DECWINIT 12#define LGI$ICR_IDENTIFY 16#define LGI$ICR_AUTHENTICATE 20#define LGI$ICR_CHKRESTRICT 24#define LGI$ICR_FINISH 28#define LGI$ICR_LOGOUT 32#define LGI$ICR_JOBSTEP 36#define LGI$ICR_CHKLICENSE 40 #typedef struct _lgicallout_vector {' unsigned int lgi$l_icr_entry_count; int (*lgi$a_icr_init)();" int (*lgi$a_icr_iact_start)(); int (*lgi$a_icr_decwinit6)(); int (*lgi$a_icr_identify)();$ int (*lgi$a_icr_authenticate)();# int (*lgi$a_icr_chkrestrict)(); int (*lgi$a_icr_finish)(); int (*lgi$a_icr_logout)(); int (*lgi$a_icr_jobstep)();" int (*lgi$a_icr_chklicense)(); } LGICALLOUT_VECTOR;#define LGI$M_UPCASE 0x1#define LGI$M_SYNTAX 0x2#define LGI$M_LENGTH 0x4 typedef struct _lgipass { __union {& unsigned int lgi$l_pass_flags; __struct {N unsigned lgi$v_upcase : 1; /* 6 upcase password if appropriate */N unsigned lgi$v_syntax : 1; /* check password syntax */O unsigned lgi$v_length : 1; /* check for maximum password length */' unsigned lgi$v_fill_8_ : 5; } lgi$r_fill_7_; } lgi$r_fill_6_; } LGIPASS; #if !defined(__VAXC)7#define lgi$l_pass_flags lgi$r_fill_6_.lgi$l_pass_flags=#define lgi$v_upcase lgi$r_fill_6_.lgi$r_fill_7_.lgi$v_upcase=#define lgi$v_syntax lgi$r_fill_6_.lgi$r_fil6l_7_.lgi$v_syntax=#define lgi$v_length lgi$r_fill_6_.lgi$r_fill_7_.lgi$v_length"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LGIINTDEF_LOADED */ wwt[UM/*************************6**************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Deve6lopment, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/6M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//************************************************************************* 6*******************************************************//*** MODULE $LHBDEF ***/#ifndef __LHBDEF_LOADED#define __LHBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* A6nd set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ 6 */N/* LAN PHYPort Block (LHB) used by network management */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _lhbdef {#pragma __nomember_alignmentN void *lhb$a_lsb; 6 /* Pointer to LSB for this PHYPort */N void *lhb$a_eib; /* Pointer to EIB for this PHYPort */P int lhb$l_hnm_len; /* Allocated size of PHYPort name LIL */O void *lhb$a_hnm; /* Pointer to PHYPort name item list */N unsigned __int64 lhb$q_descriptor; /* Generic descriptor */ } LHBDEF;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas su6pported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LHBDEF_LOADED */ wwt[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Pack6ard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc6., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************* 6*************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */G/* Source: 26-JAN-2022 23:16:38 $1$DGA8345:[LIB_H.SRC]LANUDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LILDEF ***/#ifndef __LILDEF_LOADED#define __LILDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment6 __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifn6def __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* LAN Item List definitions */N/* */P/* This data struc 6ture should look like a DECnet-VAX item list. We don't use */N/* the DECnet-VAX item list symbols because they are not available. */N/*-- */N#define LIL$T_DATA 12 /* Start of the itemlist */N#define LIL$T_ITEMVAL 4 /* Value for this item */ typedef struct _lildef { __union {N/* This structure definition will describe the header of the itemlist. 6*/ __struct {N unsigned int lil$l_listlen; /* Number of bytes in the list */N void *lil$a_listadr; /* Address of the list */N unsigned short int lil$w_size; /* Size of structure */N unsigned char lil$b_type; /* Type = DYN$C_NET */N unsigned char lil$b_subtype; /* Subtype = DYN$C_NET_ITEM */" } lil$r_header_fields;N/* This structure definition will describe a 6n item in the itemlist. Note */N/* that the ITEMLEN field includes the size of the ITEMLEN, ITEMTAG, and */N/* ITEMVAL fields. */ __struct {O unsigned short int lil$w_itemlen; /* Number of bytes in the item */N unsigned short int lil$w_itemtag; /* Size of structure */ } lil$r_list_fields; } lil$r_lil_union; } LILDEF; #if !defined(__VAXC)?#define lil$r_header_f 6ields lil$r_lil_union.lil$r_header_fields7#define lil$l_listlen lil$r_header_fields.lil$l_listlen7#define lil$a_listadr lil$r_header_fields.lil$a_listadr1#define lil$w_size lil$r_header_fields.lil$w_size1#define lil$b_type lil$r_header_fields.lil$b_type7#define lil$b_subtype lil$r_header_fields.lil$b_subtype;#define lil$r_list_fields lil$r_lil_union.lil$r_list_fields5#define lil$w_itemlen lil$r_list_fields.lil$w_itemlen5#define lil$w_itemtag lil$r_list_fields.lil$w_itemtag"#endif /*6 #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LILDEF_LOADED */ wwu[UM/***************************************************************************/M/** 6 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** 6 **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************6************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by OpenVMS SDL V3.7 */F/* Source: 12-MAY-1993 09:40:14 $1$DGA8345:[LIB_H.SRC]LIRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LIRDEF ***/#ifndef __LIRDEF6_LOADED#define __LIRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#d6efine __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* $LIRDEF - LOADABLE IMAGE RECORD D6EFINITION */N/* */N/* A LOADABLE IMAGE RECORD DEFINES A ALTERNATE EXEC IMAGE THAT CAN */N/* BE LOADED BY INIT OR SYSINIT INTO THE SYSTEM. */N/*- */N#define LIR$K_ID 257 /* LIR ID plus version */N#define LIR$K_INIT 0 /* INIT 6 */N#define LIR$K_SYSINIT 1 /* SYSINIT */N#define LIR$K_WARNING 0 /* WARNING */N#define LIR$K_SUCCESS 1 /* SUCCESS */N#define LIR$K_ERROR 2 /* ERROR */N#define LIR$K_INFORMATION 3 /* INFORMATION */N#define LIR$K_FIXED 8 /* Length of fixed portion */N#define 6LIR$C_FIXED 8 /* Length of fixed portion */N#define LIR$K_LENGTH 256 /*Length of LIR */N#define LIR$C_LENGTH 256 /*Length of LIR */N#define LIR$S_LIRDEF 8 /* Old size name - synonym */ typedef struct _lir {N unsigned short int lir$w_id; /* LIR ID field */N unsigned short int lir$w_phase; /* LIR phase indicator */N/* LIR 6 phase values */N unsigned short int lir$w_severity; /* LIR severity indicator */N/* LIR severity values */N unsigned char lir$b_err_len; /* Error message length */N unsigned char lir$b_err_off; /* Error message offset */#if defined(__VAXC) char lir$t_image_name[];#elseW/* Warning: empty char[] member for lir$t_image_name6 at end of structure not created */"#endif /* #if defined(__VAXC) */ } LIR; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LIRDEF_LOADED */ ww_u[UM/*******************************************************************6********/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** 6 **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 6 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by OpenVMS SDL V3.7 */F/* Source: 06-MAY-2005 05:49:03 $1$DGA8345:[LIB_H.SRC]LKBDEF.SDL;1 *//********************************************************************************************************************* 6***********//*** MODULE $LKBDEF ***/#ifndef __LKBDEF_LOADED#define __LKBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers *6/#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ 6 */N/* */N/* LKB - Lock Block */N/* */N/* Lock blocks represent lock requests (one block for each request). */N/* Each lock block has a corresponding entry in the lock id table which */N/* points to it. It is also linked onto one of the three state queues */N/* in 6a resource block (RSB). */N/* */N/*- */ #define LKB$M_FLAGS_VALID 0x4#define LKB$M_PKAST 0x10#define LKB$M_NODELETE 0x20#define LKB$M_QUOTA 0x40#define LKB$M_KAST 0x80N#define LKB$K_ACB64LEN 64 /* Length of ACB64 portion of LKB */#define LKB$M_DCPLAST 0x1#define LKB$M_ASYNC 60x4#define LKB$M_BLKASTQED 0x8#define LKB$M_MSTCPY 0x10#define LKB$M_NOQUOTA 0x20#define LKB$M_TIMOUTQ 0x40#define LKB$M_WASSYSOWN 0x80#define LKB$M_CVTTOSYS 0x100#define LKB$M_PROTECT 0x200#define LKB$M_RESEND 0x400#define LKB$M_RM_RBRQD 0x800#define LKB$M_FLOCK 0x1000#define LKB$M_IP 0x2000#define LKB$M_CACHED 0x4000#define LKB$M_RNGBLK 0x8000#define LKB$M_BRL 0x10000#define LKB$M_NEWSUBRNG 0x20000#define LKB$M_CVTSUBRNG 0x40000#define LKB$M_RNGCHG 0x80000 6#define LKB$M_2PC_IP 0x100000#define LKB$M_2PC_PEND 0x200000 #define LKB$M_BLKASTFLG 0x400000#define LKB$M_GRSUBRNG 0x800000#define LKB$M_PCACHED 0x1000000 #define LKB$M_VALBLKRD 0x2000000!#define LKB$M_VALBLKWRT 0x4000000#define LKB$M_DPC 0x8000000#define LKB$M_PERCPU 0x10000000#define LKB$M_INDEX 0xFFFFFFN#define LKB$K_GRANTED 1 /* Granted */N#define LKB$K_CONVERT 0 /* Conversion */N#define LKB$6K_WAITING -1 /* Waiting */N#define LKB$K_RETRY -2 /* Retry request */N#define LKB$K_SCSWAIT -3 /* SCS wait */N#define LKB$K_RSPNOTQED -4 /* Response not queued */N#define LKB$K_RSPQUEUED -5 /* Response queued */N#define LKB$K_RSPGRANTD -6 /* Response granted */N#define LKB$K_RSPDOLOCL -7 6 /* Response do locally */N#define LKB$K_RSPRESEND -8 /* Response resend */N#define LKB$K_RSPWAIT -9 /* Response wait */N#define LKB$K_RSP2PCRDY -10 /* Response ready */N#define LKB$K_RSPFATAL -11 /* Fatal Message Response */#define LKB$M_DBLKAST 0x2N#define LKB$K_LENGTH 256 /* Length of LKB */N#define LKB$C_LENGTH 256 6 /* Length of LKB */N#define LKB$S_LKBDEF 256 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _acb; struct _lkb; struct _rsb; #endif /* #ifdef __cplusplus */ typedef struct _lkb$r_lkb {N struct _acb *lkb$l_astqfl; /* AST Queue forward link */N struct _acb *lkb$l_astqbl; /* AST Queue backward link */N unsigned short int lkb$w_size; /* S 6ize of LKB in bytes */N unsigned char lkb$b_type; /* Structure type */ __union {N unsigned char lkb$b_rmod; /* Access mode of request */ __struct {N unsigned lkb$v_mode : 2; /* Mode subfield */N unsigned lkb$v_flags_valid : 1; /* ACB flags valid indicator */) unsigned lkbdef$$_fill_1 : 1;N unsigned lkb$v_pkast : 1; /* Piggyback Special Kernel 6AST */N unsigned lkb$v_nodelete : 1; /* Don't delete ACB on delivery */N unsigned lkb$v_quota : 1; /* Account for quota */N unsigned lkb$v_kast : 1; /* Special Kernel AST */ } lkb$r_fill_1_; } lkb$r_fill_0_;N unsigned int lkb$l_pid; /* Process ID of requesting process */N unsigned int lkb$l_acb64x; /* Offset to ACB64X structure */ int lkb$l_acb_fill;N unsigned6 int lkb$l_acb_flags; /* AST control flags */N unsigned int lkb$l_tpid; /* Kernel Thread ID */N void (*lkb$l_kast)(); /* Special Kernel AST address */N char lkb$b_spare_1 [4]; /* spare */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N 6 void (*lkb$pq_ast)(); /* Address of AST routine */#else unsigned __int64 lkb$pq_ast;#endifN unsigned short int lkb$w_rqseqnm; /* Request sequence number */N unsigned __int64 lkb$q_rqseqnm; /* Request sequence number */ } lkb$r_ast_overlay; __union {N unsigned __int64 lkb$q_astprm; /* AST parameter */N unsigned int lkb$l_epid; /* EPID (Master copies only) */ } lkb$r_as 6tprm_overlay;R unsigned __int64 lkb$q_user_thread_id; /* ACB unique user thread identifier */N unsigned int lkb$l_acb; /* Pointer to ACB */N unsigned int lkb$l_refcnt; /* Sub-LKB reference count */N unsigned int lkb$l_flags; /* User specified flags */ __union {N unsigned int lkb$l_status; /* Internal status */ __struct {N unsigned lkb$v_dcplast : 1; /* Deliv6er Completion AST */* unsigned lkb$v_reserved_1 : 1;N unsigned lkb$v_async : 1; /* Request completed asynchronously */N unsigned lkb$v_blkastqed : 1; /* Blocking AST has been queued */N unsigned lkb$v_mstcpy : 1; /* LKB is a Master copy */N unsigned lkb$v_noquota : 1; /* Don't charge quota */N unsigned lkb$v_timoutq : 1; /* LKB is on timeout queue */N unsigned lkb$v_was6sysown : 1; /* Was System Owned lock */N unsigned lkb$v_cvttosys : 1; /* Convert to System Owned */N unsigned lkb$v_protect : 1; /* Protected lock */N unsigned lkb$v_resend : 1; /* Resend during failover */N unsigned lkb$v_rm_rbrqd : 1; /* Remaster rebuild required */N unsigned lkb$v_flock : 1; /* Fork lock */N unsigned lkb$v_ip : 1; /* Operation in 6progress */N unsigned lkb$v_cached : 1; /* LKB is in cache */N unsigned lkb$v_rngblk : 1; /* Range block specified */N unsigned lkb$v_brl : 1; /* Indicate byte range lock */N unsigned lkb$v_newsubrng : 1; /* New sub-range request */N unsigned lkb$v_cvtsubrng : 1; /* Sub-range convert request */N unsigned lkb$v_rngchg : 1; /* Changing range */N 6 unsigned lkb$v_2pc_ip : 1; /* Two phase operation in progress */N unsigned lkb$v_2pc_pend : 1; /* Two phase operation pending */N unsigned lkb$v_blkastflg : 1; /* Indicates BLKAST specified */N unsigned lkb$v_grsubrng : 1; /* Granted sub-range lock */N unsigned lkb$v_pcached : 1; /* LKB is to be cached */S unsigned lkb$v_valblkrd : 1; /* Indicates read access to value block */U unsigned l 6kb$v_valblkwrt : 1; /* Indicates write access to value block */N unsigned lkb$v_dpc : 1; /* Delete pending cache */N unsigned lkb$v_percpu : 1; /* Per-CPU lock request */' unsigned lkb$v_fill_8_ : 3; } lkb$r_fill_3_; } lkb$r_fill_2_;N unsigned int lkb$l_lkst1; /* First lock status longword */ __union {N unsigned int lkb$l_lkst2; /* Second lock status longword */ 6 __union {N unsigned int lkb$l_lkid; /* Lock ID */ __struct {N unsigned lkb$v_index : 24; /* Lock ID Index */N unsigned lkb$v_seqn : 8; /* Lock ID Sequence Number */ } lkb$r_fill_5_; } lkb$r_fill_4_; } lkb$r_lkst2_overlay;N unsigned char lkb$b_rqmode; /* Request mode */N unsigned char lkb$b_grmode; /* Granted 6 mode */N unsigned char lkb$b_tslt; /* Timestamp lifetime */N unsigned char lkb$b_efn; /* Event Flag Number */ __union {N unsigned char lkb$b_state; /* Lock state */N unsigned int lkb$l_state; /* Lock state */ } lkb$r_state_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragm 6a __nomember_alignment __octaword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lkb$q_sqfl; /* State queue forward link */#else unsigned __int64 lkb$q_sqfl;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragm 6a __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lkb$q_sqbl; /* State queue backward link */#else unsigned __int64 lkb$q_sqbl;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required 6_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lkb$q_ownqfl; /* Owner queue forward link */#else unsigned __int64 lkb$q_ownqfl;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lkb$q_ownqbl; /* Owner queue backward link */#else unsigne 6d __int64 lkb$q_ownqbl;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lkb$q_timoutqfl; /* Timeout queue forward link */#else" unsigned __int64 6lkb$q_timoutqfl;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lkb$q_timoutqbl; /* Timeout queue backward link */#else" unsigned __int64 lkb$q_timoutqbl;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword 6#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _lkb *lkb$q_parent; /* Address of parent LKB */#else unsigned __int64 lkb$q_parent;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default6 to 64-bit pointers */N struct _rsb *lkb$q_rsb; /* Address of owner RSB */#else unsigned __int64 lkb$q_rsb;#endif#pragma __nomember_alignment __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void (*lkb$pq_lksb)(); /* Address of lock status block */#else unsigned __int64 lkb$pq_lksb;#endifO 6 unsigned int lkb$l_dlckpri; /* Deadlock priority (Master copies) */ } lkb$r_lksb_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *lkb$l_rqstsr 6ng; /* Starting byte of requested range */#pragma __nomember_alignmentN void *lkb$l_rqsterng; /* Ending byte of requested range */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN void *lkb$l_grntsrng; /* Starting byte of granted range */#pragma __nomember_alignmentN void *lkb$l_grnterng; 6 /* Ending byte of granted range */N void *lkb$l_lckctx; /* Address of Lock Context Block */N unsigned int lkb$l_remlkid; /* Remote Lock ID (Master) */ __union {N unsigned int lkb$l_csid; /* Cluster System ID (Master only) */N unsigned __int64 lkb$q_oldastprm; /* Old AST parameter */ } lkb$r_csid_overlay;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __re 6quired_pointer_size __long /* And set ptr size default to 64-bit pointers */N int (*lkb$pq_oldblkast)(); /* Old Blocking AST address */#else# unsigned __int64 lkb$pq_oldblkast;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */O int (*lkb$pq_cplastadr)(); /* Address of Completion AST routine */#else# unsigned __int64 lkb$pq_c 6plastadr;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N int (*lkb$pq_blkastadr)(); /* Address of Blocking AST routine */#else# unsigned __int64 lkb$pq_blkastadr;#endifN unsigned int lkb$l_priority; /* Request's priority */N unsigned int lkb$l_tskpid; /* Task ID */N unsigned int 6 lkb$l_rsdmid; /* Resource Domain ID */N unsigned int lkb$l_pcb; /* Address of PCB */N unsigned int lkb$l_lckrq; /* Address of per-CPU lock request */ __union {N unsigned int lkb$l_status2; /* Internal status */ __struct {* unsigned lkb$v_reserved_2 : 1;N unsigned lkb$v_dblkast : 1; /* Deliver Blocking AST */+ unsigned lkb$v_reserved_3 : 627;' unsigned lkb$v_fill_9_ : 3; } lkb$r_fill_7_; } lkb$r_fill_6_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 lkb$q_duetime; /* duetime for waiting locks */ } LKB$R_LKB; #if !defined(__VAXC)+#define lkb$b_rmod lkb$r_fill_0_.lkb$b_rmod9#define lkb$v_mode lkb$r_fill_0_.lkb$r_fil 6l_1_.lkb$v_modeG#define lkb$v_flags_valid lkb$r_fill_0_.lkb$r_fill_1_.lkb$v_flags_valid;#define lkb$v_pkast lkb$r_fill_0_.lkb$r_fill_1_.lkb$v_pkastA#define lkb$v_nodelete lkb$r_fill_0_.lkb$r_fill_1_.lkb$v_nodelete;#define lkb$v_quota lkb$r_fill_0_.lkb$r_fill_1_.lkb$v_quota9#define lkb$v_kast lkb$r_fill_0_.lkb$r_fill_1_.lkb$v_kast/#define lkb$pq_ast lkb$r_ast_overlay.lkb$pq_ast5#define lkb$w_rqseqnm lkb$r_ast_overlay.lkb$w_rqseqnm5#define lkb$q_rqseqnm lkb$r_ast_overlay.lkb$q_rqseqnm6 6#define lkb$q_astprm lkb$r_astprm_overlay.lkb$q_astprm2#define lkb$l_epid lkb$r_astprm_overlay.lkb$l_epid/#define lkb$l_status lkb$r_fill_2_.lkb$l_status?#define lkb$v_dcplast lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_dcplast;#define lkb$v_async lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_asyncC#define lkb$v_blkastqed lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_blkastqed=#define lkb$v_mstcpy lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_mstcpy?#define lkb$v_noquota lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_noquota?#define lkb$v_timout 6q lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_timoutqC#define lkb$v_wassysown lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_wassysownA#define lkb$v_cvttosys lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_cvttosys?#define lkb$v_protect lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_protect=#define lkb$v_resend lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_resendA#define lkb$v_rm_rbrqd lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_rm_rbrqd;#define lkb$v_flock lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_flock5#define lkb$v_ip lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_ip=#defin6e lkb$v_cached lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_cached=#define lkb$v_rngblk lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_rngblk7#define lkb$v_brl lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_brlC#define lkb$v_newsubrng lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_newsubrngC#define lkb$v_cvtsubrng lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_cvtsubrng=#define lkb$v_rngchg lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_rngchg=#define lkb$v_2pc_ip lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_2pc_ipA#define lkb$v_2pc_pend lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_2 6pc_pendC#define lkb$v_blkastflg lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_blkastflgA#define lkb$v_grsubrng lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_grsubrng?#define lkb$v_pcached lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_pcachedA#define lkb$v_valblkrd lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_valblkrdC#define lkb$v_valblkwrt lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_valblkwrt7#define lkb$v_dpc lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_dpc=#define lkb$v_percpu lkb$r_fill_2_.lkb$r_fill_3_.lkb$v_percpu3#define lkb$l_lkst2 lkb$r_lkst2_ 6overlay.lkb$l_lkst2?#define lkb$l_lkid lkb$r_lkst2_overlay.lkb$r_fill_4_.lkb$l_lkidO#define lkb$v_index lkb$r_lkst2_overlay.lkb$r_fill_4_.lkb$r_fill_5_.lkb$v_indexM#define lkb$v_seqn lkb$r_lkst2_overlay.lkb$r_fill_4_.lkb$r_fill_5_.lkb$v_seqn3#define lkb$b_state lkb$r_state_overlay.lkb$b_state3#define lkb$l_state lkb$r_state_overlay.lkb$l_state2#define lkb$pq_lksb lkb$r_lksb_overlay.lkb$pq_lksb6#define lkb$l_dlckpri lkb$r_lksb_overlay.lkb$l_dlckpri0#define lkb$l_csid lkb$r_csid_overlay.lk6b$l_csid:#define lkb$q_oldastprm lkb$r_csid_overlay.lkb$q_oldastprm1#define lkb$l_status2 lkb$r_fill_6_.lkb$l_status2?#define lkb$v_dblkast lkb$r_fill_6_.lkb$r_fill_7_.lkb$v_dblkast"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma 6__standard #endif /* __LKBDEF_LOADED */ wwu[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of 6HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. 6 **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB 6_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LLBDEF ***/#ifndef __LLBDEF_LOADED#define __LLBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save 6 /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)6#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* LAN Link Block (LLB) used by network management */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignme 6nt#endiftypedef struct _llbdef {#pragma __nomember_alignmentN void *llb$a_lsb; /* Pointer to LSB for this link */N void *llb$a_eib; /* Pointer to EIB for this link */N int llb$l_lnm_len; /* Allocated size of LNM item list */N void *llb$a_lnm; /* Pointer to link name item list */N unsigned __int64 llb$q_descriptor; /* Generic descriptor */P unsigned int llb$l_last_tid; 6 /* Last used SMT frame Transaction ID */ char llb$b_fill_16_ [4]; } LLBDEF;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LLBDEF_LOADED */ ww0u[UM/***********************************************************6****************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** 6 **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 6 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:33 by OpenVMS SDL V3.7 */F/* Source: 27-APR-2022 11:23:39 $1$DGA8345:[LIB_H.SRC]LMBDEF.SDL;1 *//************************************************************************************************************* 6*******************//*** MODULE $LMBDEF ***/#ifndef __LMBDEF_LOADED#define __LMBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit po6inters */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ 6 */N/* LMB - Logical Memory Block */N/* */N/* Logical Memory Block definitions (for subsetted crash dumps) */N/* Layout of each Logical Memory Block and accompanying hole descriptor. */N/* Logical Memory Blocks are portions of selective memory dumps. "Holes" */N/* refer to areas of invalid or inaccessible virtual address space at the */6N/* time of the dump. */N/*- */N#define LMB$C_SYSTEM_PTK 0 /* 0 PT Space (Kernel mode) */N#define LMB$C_SYSTEM_PTE 1 /* 1 PT Space (Executive mode) */N#define LMB$C_SYSTEM_PTS 2 /* 2 PT Space (Supervisor mode) */N#define LMB$C_SYSTEM_PTU 3 /* 3 PT Space (User mode) */T#define LMB$C_S0S1 4 6 /* 4 S0/S1 Space (excluding SPT window) */Y#define LMB$C_S2_EXEC 5 /* 5 S2 Space: NPP, errlog buffers, execlets */N#define LMB$C_S2_PFNDB 6 /* 6 S2 Space: PFN database */N#define LMB$C_S2_WSL_GPT 7 /* 7 S2 Space: WSL & GPT */Z#define LMB$C_S2_LCKMGR_XFC 8 /* 8 S2 Space: Locks, Resources, XFC metadata */S#define LMB$C_KEY_PROCESS_PTK 9 /* 9 Process page tables (Kernel mode) */V#define LMB$C_6KEY_PROCESS_PTE 10 /* 10 Process page tables (Executive mode) */W#define LMB$C_KEY_PROCESS_PTS 11 /* 11 Process page tables (Supervisor mode) */Q#define LMB$C_KEY_PROCESS_PTU 12 /* 12 Process page tables (User mode) */m#define LMB$C_KEY_PROCESS_MEM 13 /* 13 Process memory (current/swapper/etc., site- or VSI-defined) */^#define LMB$C_KEY_GBL 14 /* 14 Global Pages (associated with key processes) */S#define LMB$C_OTHER_PROCESS_PTK 15 /* 15 Pro6cess page tables (Kernel mode) */V#define LMB$C_OTHER_PROCESS_PTE 16 /* 16 Process page tables (Executive mode) */W#define LMB$C_OTHER_PROCESS_PTS 17 /* 17 Process page tables (Supervisor mode) */Q#define LMB$C_OTHER_PROCESS_PTU 18 /* 18 Process page tables (User mode) */V#define LMB$C_OTHER_PROCESS_MEM 19 /* 19 Process memory (all other processes) */b#define LMB$C_OTHER_GBL 20 /* 20 Global Pages (not associated with key processes) */N/* Make changes and 6additions before this line */N#define LMB$C_NUMTYPES 21 /* 21 The number of LMB types */N#define LMB$C_SDMP_PRCMSK 1031680 /* Bitmask of LMBs for processes */N/* (9-13, 15-19) */N#define LMB$C_SDMP_PTMSK 499215 /* Bitmask of LMBs for page tables */N/* (0-3, 9-12, 15-18) */[#define LMB$C_PROCESS_SPACE 256 /* 2566 Entire process space from zero to the gap */X#define LMB$C_PPT_KERNEL 257 /* 257 Process half of kernel mode page table */[#define LMB$C_PPT_EXEC 258 /* 258 Process half of executive mode page table */\#define LMB$C_PPT_SUPER 259 /* 259 Process half of supervisor mode page table */V#define LMB$C_PPT_USER 260 /* 260 Process half of user mode page table */X#define LMB$C_SYSTEM_SPACE 261 /* 261 Process-pertinent data in system space */N#d6efine LMB$C_PDMP_PRCMSK 31 /* Bitmask of LMBs for processes */N/* (256-260) */N#define LMB$C_PDMP_PTMSK 30 /* Bitmask of LMBs for page tables */N/* (257-260) */Q#define LMB_AXP_I64$C_SHARED_MEMORY -2 /* -2 Galaxy shared memory (complete) */V#define LMB_AXP_I64$C_SHARED_REGION -1 /* -1 Galaxy shared memory region (single) */N#define LMB_AXP_6I64$C_PT 0 /* 0 PT Space */T#define LMB_AXP_I64$C_S0S1 1 /* 1 S0/S1 Space (excluding SPT window) */W#define LMB_AXP_I64$C_S2 2 /* 2 S2 Space (includes PFN database, GPT) */Y#define LMB_AXP_I64$C_REPLICATED_SYS 3 /* 3 Replicated system space (Wildfires etc) */N#define LMB_AXP_I64$C_MMAPS 4 /* 4 Galaxy memory map pages */N#define LMB_AXP_I64$C_KEY_PROCESS_PT 5 /* 5 Process page tables ... */m#define LMB_AX6P_I64$C_KEY_PROCESS_MEM 6 /* 6 ... and memory (current/swapper/etc., site- or VSI-defined) */^#define LMB_AXP_I64$C_KEY_GBL 7 /* 7 Global Pages (associated with key processes) */N#define LMB_AXP_I64$C_OTHER_PROCESS_PT 8 /* 8 Process page tables ... */X#define LMB_AXP_I64$C_OTHER_PROCESS_MEM 9 /* 9 ... and memory (all other processes) */b#define LMB_AXP_I64$C_OTHER_GBL 10 /* 10 Global Pages (not associated with key processes) */N/* Make changes and additions before this 6line */N#define LMB_AXP_I64$C_NUMTYPES 11 /* 11 The number of LMB types */N#define LMB_AXP_I64$C_SDMP_PRCMSK 3456 /* Bitmask of LMBs for processes */N/* (5-6, 8-9, all offset by 2) */a#define LMB_AXP_I64$C_PROCESS_SPACE 256 /* 256 Entire process space from zero to the L1PT page */X#define LMB_AXP_I64$C_SYSTEM_SPACE 257 /* 257 Process-pertinent data in system space */N#define LMB_AXP_I64$C_PDMP_PRCMSK 1 6 /* Bitmask of LMBs for processes */N/* (256) */N#define LMB_X86$C_SYSTEM_PTK 0 /* 0 PT Space (Kernel mode) */N#define LMB_X86$C_SYSTEM_PTE 1 /* 1 PT Space (Executive mode) */N#define LMB_X86$C_SYSTEM_PTS 2 /* 2 PT Space (Supervisor mode) */N#define LMB_X86$C_SYSTEM_PTU 3 /* 3 PT Space (User mode) */T#define LMB_X86$C_S0S1 4 /* 4 S0/S1 Space (excl6uding SPT window) */Y#define LMB_X86$C_S2_EXEC 5 /* 5 S2 Space: NPP, errlog buffers, execlets */N#define LMB_X86$C_S2_PFNDB 6 /* 6 S2 Space: PFN database */N#define LMB_X86$C_S2_WSL_GPT 7 /* 7 S2 Space: WSL & GPT */Z#define LMB_X86$C_S2_LCKMGR_XFC 8 /* 8 S2 Space: Locks, Resources, XFC metadata */S#define LMB_X86$C_KEY_PROCESS_PTK 9 /* 9 Process page tables (Kernel mode) */V#define LMB_X86$C_KEY_PROCESS_PTE 10 /* 10 Process6 page tables (Executive mode) */W#define LMB_X86$C_KEY_PROCESS_PTS 11 /* 11 Process page tables (Supervisor mode) */Q#define LMB_X86$C_KEY_PROCESS_PTU 12 /* 12 Process page tables (User mode) */m#define LMB_X86$C_KEY_PROCESS_MEM 13 /* 13 Process memory (current/swapper/etc., site- or VSI-defined) */^#define LMB_X86$C_KEY_GBL 14 /* 14 Global Pages (associated with key processes) */S#define LMB_X86$C_OTHER_PROCESS_PTK 15 /* 15 Process page tables (Kernel mode) */V#def6ine LMB_X86$C_OTHER_PROCESS_PTE 16 /* 16 Process page tables (Executive mode) */W#define LMB_X86$C_OTHER_PROCESS_PTS 17 /* 17 Process page tables (Supervisor mode) */Q#define LMB_X86$C_OTHER_PROCESS_PTU 18 /* 18 Process page tables (User mode) */V#define LMB_X86$C_OTHER_PROCESS_MEM 19 /* 19 Process memory (all other processes) */b#define LMB_X86$C_OTHER_GBL 20 /* 20 Global Pages (not associated with key processes) */N/* Make changes and additions before this line 6 */N#define LMB_X86$C_NUMTYPES 21 /* 21 The number of LMB types */N#define LMB_X86$C_SDMP_PRCMSK 1031680 /* Bitmask of LMBs for processes */N/* (9-13, 15-19) */N#define LMB_X86$C_SDMP_PTMSK 499215 /* Bitmask of LMBs for page tables */N/* (0-3, 9-12, 15-18) */[#define LMB_X86$C_PROCESS_SPACE 256 /* 256 Entire process space from zero to the g6ap */X#define LMB_X86$C_PPT_KERNEL 257 /* 257 Process half of kernel mode page table */[#define LMB_X86$C_PPT_EXEC 258 /* 258 Process half of executive mode page table */\#define LMB_X86$C_PPT_SUPER 259 /* 259 Process half of supervisor mode page table */V#define LMB_X86$C_PPT_USER 260 /* 260 Process half of user mode page table */X#define LMB_X86$C_SYSTEM_SPACE 261 /* 261 Process-pertinent data in system space */N#define LMB_X86$C_PDMP_PRCMSK 31 /* 6 Bitmask of LMBs for processes */N/* (256-260) */N#define LMB_X86$C_PDMP_PTMSK 30 /* Bitmask of LMBs for page tables */N/* (257-260) */#define LMB$M_INCOMPLETE 0x1#define LMB$M_KEYPROC_LMB 0x2#define LMB$M_REMPROC_LMB 0x4#define LMB$M_GLOBAL_LMB 0x8#define LMB$M_EMBED_HOLES 0x10#define LMB$M_EMBED_MAP 0x20N#define LMB$K_LENGTH 136 /* 6 Logical mem block length */N#define LMB$C_LENGTH 136 /* Logical mem block length */N#define LMB$S_LMBDEF 136 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _phd; struct _pcb; #endif /* #ifdef __cplusplus */ typedef struct _lmb {N short int lmb$w_type; /* Type of LMB */N/* X86_64 6 */N/* */I/* LMB types list #3: The system dump list for X86_64 */N/* */N/* LMB flavors */N/* */I/* LMB types list #4: The process dump list for X86_64 */N/* 6 */N/* LMB flavors for process dumps */N/* */\/* This variant of the list exists so that SHOW DUMP can work on Alpha/IA64 system dumps. */I/* The contents must be identical to list #1 above. */N/* */N/* LMB flavors for Alpha & IA64 6 */N/* */]/* This variant of the list exists so that SHOW DUMP can work on Alpha/IA64 process dumps. */I/* The contents must be identical to list #2 above. */N/* */N/* LMB flavors for process dumps */N/* 6 */U/* This variant of the list exists so that SHOW DUMP can work on X86 system dumps. */I/* The contents must be identical to list #3 above. */N/* */N/* LMB flavors */N/* */V/* This variant of the list exists so that SHOW DUMP can work on X86 process 6 dumps. */I/* The contents must be identical to list #4 above. */N/* */N/* LMB flavors for process dumps */ __union { __struct {N unsigned short int lmb$w_flags; /* Flags for this LMB */ } lmb$r_lmb_fields; __struct {N unsigned lmb$v_incomplete : 1; /* LMB not completely written */` 6 unsigned lmb$v_keyproc_lmb : 1; /* A key process LMB (x86 interleaved dumps only) */d unsigned lmb$v_remproc_lmb : 1; /* A non-key process LMB (x86 interleaved dumps only) */` unsigned lmb$v_global_lmb : 1; /* A global pages LMB (x86 interleaved dumps only) */w unsigned lmb$v_embed_holes : 1; /* Hole table is embedded in the LMB header (x86 interleaved dumps only) */z unsigned lmb$v_embed_map : 1; /* Compression map is embedded in the LMB header 6 (x86 interleaved dumps only) */' unsigned lmb$v_fill_0_ : 2; } lmb$r_lmb_bits; } lmb$r_lmb_overlay; __union { __struct {n int lmb$l_act_length; /* LMB data actual length (blocks) (not used for interleaved dumps) */p int lmb$l_nocomp_length; /* as ACT_LENGTH without compression (not used for interleaved dumps) */ } lmb$r_lmb_8; __struct {N struct _phd *lmb$l_phdadr; /* SVA of this 6 process's PHD */ int lmb$l_spare_1; } lmb$r_lmb_9; } lmb$r_lmb_7; __union {w unsigned short int lmb$w_hole_tbl; /* Relative VBN in dump of start of the table describing the holes in the */N/* virtual address space. In an interleaved dump, nonzero value is the */N/* offset in bytes to the hole table within the LMB header block. */i unsigned short int lmb$w_pmap_tbl; /* Just another name for the same relative VBN in dump 6with */N/* shared memory dumps. */ } lmb$r_lmb_1;q unsigned short int lmb$w_cmap_tbl; /* In an interleaved dump, nonzero value is the offset in bytes to the */N/* compression map within the LMB header block */ __union {N unsigned int lmb$l_total_holes; /* Count of holes in LMB */] unsigned int lmb$l_total_pmaps; /* count of PMAPs (fragments) in shared memory LMB */ 7 } lmb$r_lmb_2; __union {N struct _pcb *lmb$l_pcbadr; /* SVA of this process's PCB */Y unsigned int lmb$l_rad; /* RAD for this LMB of replicated system space */ } lmb$r_lmb_3;N unsigned __int64 lmb$q_time_check; /* Ones-complement of EMB$Q_CR_TIME */R char lmb$t_process_name [16]; /* Process name (only for TYPE=PROCESS) */ __union { __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas su 7pported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */S void *lmb$pq_start_va; /* Start of range of addresses searched */#else" unsigned __int64 lmb$pq_start_va;#endifN/* for holes by BUGCHECK */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */P 7 void *lmb$pq_end_va; /* End of range of addresses searched */#else unsigned __int64 lmb$pq_end_va;#endifN/* for holes by BUGCHECK */ } lmb$r_lmb_5; __struct {Y unsigned __int64 lmb$q_start_offset; /* Start of range of addresses dumped */N/* by DUMP_SHARED_MEMORY */U unsigned __int64 lmb$q_end_offset; /* End of range of addresses dump 7ed */N/* by DUMP_SHARED_MEMORY */ } lmb$r_lmb_6; } lmb$r_lmb_4;` char lmb$t_region_tag [8]; /* No GLX$ symbols for X86, just leave a stub for SDA */N/* */X/* Use the reclaimed space here for some interleaved dumps cells. 56 bytes available. */N/* */N __int64 lmb$q_7act_length; /* LMB data actual length (blocks) */O __int64 lmb$q_nocomp_length; /* as ACT_LENGTH without compression */k unsigned __int64 lmb$q_holetbl_vbn; /* Start VBN of the LMB's hole table, zero if embedded in header */p unsigned __int64 lmb$q_compmap_vbn; /* Start VBN of the LMB's compression map, zero if embedded in header */c unsigned int lmb$l_holetbl_bytes; /* Bytes used by hole table (even if appended to header) */w unsigned int lmb$l_compmap_bytes7; /* Bytes used for the compression map if embedded in header (otherwise zero) */m unsigned int lmb$l_compmap_blocks; /* Blocks used for the compression map, zero if embedded in header */h unsigned int lmb$l_compmap_entries; /* Count of compression map entries for LMB (embedded or not) */c unsigned int lmb$l_slice; /* 1-based slice number for a sliced LMB (e.g. S2_PFNDB) */O unsigned short int lmb$w_scan_actor; /* Actor used to do page table scan */N unsigned short 7 int lmb$w_dump_actor; /* Actor used to do memory dump */w unsigned int lmb$l_cmap_start; /* Offset into compression map of first entry for this LMB (interleaved=MBZ) */m unsigned int lmb$l_cmap_count; /* Count of compression map entries for this LMB (interleaved=MBZ) */ c char lmb$t_expansion_space [376]; /* Space available for hole table and/or compression map */ } LMB; #if !defined(__VAXC)B#define lmb$w_flags lmb$r_lmb_overlay.lmb$r_lmb_fields.lmb$w_flags7J#define lmb$v_incomplete lmb$r_lmb_overlay.lmb$r_lmb_bits.lmb$v_incompleteL#define lmb$v_keyproc_lmb lmb$r_lmb_overlay.lmb$r_lmb_bits.lmb$v_keyproc_lmbL#define lmb$v_remproc_lmb lmb$r_lmb_overlay.lmb$r_lmb_bits.lmb$v_remproc_lmbJ#define lmb$v_global_lmb lmb$r_lmb_overlay.lmb$r_lmb_bits.lmb$v_global_lmbL#define lmb$v_embed_holes lmb$r_lmb_overlay.lmb$r_lmb_bits.lmb$v_embed_holesH#define lmb$v_embed_map lmb$r_lmb_overlay.lmb$r_lmb_bits.lmb$v_embed_mapA#define lmb$l_act_length lmb$r_lmb_7.lmb$r_l 7mb_8.lmb$l_act_lengthG#define lmb$l_nocomp_length lmb$r_lmb_7.lmb$r_lmb_8.lmb$l_nocomp_length9#define lmb$l_phdadr lmb$r_lmb_7.lmb$r_lmb_9.lmb$l_phdadr1#define lmb$w_hole_tbl lmb$r_lmb_1.lmb$w_hole_tbl1#define lmb$w_pmap_tbl lmb$r_lmb_1.lmb$w_pmap_tbl7#define lmb$l_total_holes lmb$r_lmb_2.lmb$l_total_holes7#define lmb$l_total_pmaps lmb$r_lmb_2.lmb$l_total_pmaps-#define lmb$l_pcbadr lmb$r_lmb_3.lmb$l_pcbadr'#define lmb$l_rad lmb$r_lmb_3.lmb$l_rad?#define lmb$pq_start_va lmb$r_lmb_4.lm 7b$r_lmb_5.lmb$pq_start_va;#define lmb$pq_end_va lmb$r_lmb_4.lmb$r_lmb_5.lmb$pq_end_vaE#define lmb$q_start_offset lmb$r_lmb_4.lmb$r_lmb_6.lmb$q_start_offsetA#define lmb$q_end_offset lmb$r_lmb_4.lmb$r_lmb_6.lmb$q_end_offset"#endif /* #if !defined(__VAXC) */ #define LMB$K_HOLE_LENGTH 16#define LMB$C_HOLE_LENGTH 16N/* Size of each hole table entry. */ typedef struct _lmb_hole {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pr 7agmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *lmb$pq_hole_start_va; /* Starting VA for this hole */#else' unsigned __int64 lmb$pq_hole_start_va;#endifR unsigned __int64 lmb$q_hole_total_pages; /* Running total of pages of holes */N/* up to the starting VA of this hole */N/* Offset to get to the next hole */N/* table ent 7ry. */ } LMB_HOLE; #ifdef __INITIAL_POINTER_SIZEH#pragma __required_pointer_size __save /* Save current pointer size */C#pragma __required_pointer_size __long /* Pointers are 64-bit */Otypedef struct _lmb_hole * LMB_HOLE_PQ; /* Pointer to an LMB hole structure */O#pragma __required_pointer_size __restore /* Return to previous pointer size */#else%typedef unsigned __int64 LMB_HOLE_PQ;##endif /* __INITIAL_POINTER_ 7SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LMBDEF_LOADED */ wwPJv[UM/***************************************************************************/M/**  7 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SO7FTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************************7****************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by OpenVMS SDL V3.7 */I/* Source: 02-SEP-1989 10:46:49 $1$DGA8345:[LIB_H.SRC]LMFITMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LMFITMDEF ***/#ifndef __LMFITMDEF_LOADED 7#define __LMFITMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __7unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* LMFITMDEF - LMF internal item-list defini7tions */N/* */N/* Items lists used by the internal routines LMF$LOAD and LMF$UNLOAD, */N/* which manipulate the on-disk and in-memory License databases. */N/* These routines now have a callable interface, and the caller needs */N/* access to these item codes. */N/*- 7 */N/* These are the item codes passed from the LMF utility to the callable */N/* routines in the item list. New codes should be added to the end. */#define LMF$K_LDB 0#define LMF$K_PRODUCER 1#define LMF$K_PRODUCT 2#define LMF$K_VERSION 3#define LMF$K_ISSUER 4#define LMF$K_COMMENT 5#define LMF$K_AUTHORIZATION 6#define LMF$K_UNITS 7#define LMF$K_AVAILABILITY 8#define LMF$K_ACTIVITY 9#define LMF$K_TOKEN 10#define LMF$K_TERMINATION 11#define LMF$K_DATE 172#define LMF$K_HARDWARE_ID 13#define LMF$K_CHECKSUM 14#define LMF$K_INCLUDE 15#define LMF$K_EXCLUDE 16#define LMF$K_OPTIONS 17#define LMF$K_OUTPUT_NAME 18"#define LMF$K_EXTINCT_QUALIFIER 19#define LMF$K_LOAD_QUALIFIER 20!#define LMF$K_CUST_TERMINATION 21#define LMF$K_CUST_DATE 22#define LMF$K_FULL_QUALIFIER 23 #define LMF$K_BRIEF_QUALIFIER 24#define LMF$K_CREATION_DATE 25##define LMF$K_LMF_VERSION_NUMBER 26"#define LMF$K_CREATING_USERNAME 27#define LMF$K_LOG_QUALIFIER 728 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LMFITMDEF_LOADED */ wwpv[UM/***************************************************************************/M/** 7 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFT7WARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************7**************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by OpenVMS SDL V3.7 */I/* Source: 16-JUL-1997 11:08:42 $1$DGA8345:[LIB_H.SRC]LNMSTRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LNMSTRDEF ***/#ifndef __LNMSTRDEF_LOADED#d 7efine __LNMSTRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __un7known_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define LNMB$M_NO_ALIAS 0x1#define LNMB$M_CONFINE 0x2#define LNMB$M_CRELOG 0x4#define LNMB$M_TABLE 0x8#define LNMB$M7_NODELETE 0x10#define LNMB$M_CLUSTERWIDE 0x20#define LNMB$M_REMACTION 0x40N#define LNMB$S_LNMBDEF 33 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */struct _lnmth; struct _lnmx; #endif /* #ifdef __cplusplus */ typedef struct _lnmb {N struct _lnmb *lnmb$l_flink; /* Forward link in list */N struct _lnmb *lnmb$l_blink; /* Backward link in list */N unsigned short int7 lnmb$w_size; /* Size of LNMB in bytes */N unsigned char lnmb$b_type; /* Structure type for LNMB */N char lnmb$b_pad; /* Align to longword boundary */V unsigned int lnmb$l_acmode; /* Owner access mode / integrity level byte */O struct _lnmth *lnmb$l_table; /* Logical name table header address */N struct _lnmx *lnmb$l_lnmx; /* Pointer to first LNMX */ __union {N unsigned int l7nmb$l_flags; /* Name attributes */ __struct {N unsigned lnmb$v_no_alias : 1; /* Do not allow outer mode alias */N unsigned lnmb$v_confine : 1; /* Do not copy into subprocess */N unsigned lnmb$v_crelog : 1; /* Created with old $CRELOG service */N unsigned lnmb$v_table : 1; /* This is a table name */U unsigned lnmb$v_nodelete : 1; /* Do not allow this table to be deleted */S unsign7ed lnmb$v_clusterwide : 1; /* Name is in a "clusterwide" table */N/* (this bit drives collision semantics, return of */N/* clusterwide as $TRNLNM attribute) */N/* (only this bit could be set for "clusterwide" name or table */N/* on a node booted standalone) */Z unsigned lnmb$v_remaction : 1; /* Name is replicated on other cluster nodes */N/* (this bit drives repli 7cation and stall semantics) */N/* (if this is set, clusterwide should be set) */( unsigned lnmb$v_fill_0_ : 1; } lnmb$r_bits; } lnmb$r_flag_bits;N unsigned int lnmb$l_namelen; /* Length of logical name string */N char lnmb$t_name; /* Name string */N/* Translation blocks follow name - */N/* pointed to by LNMB$L_LNMX 7 */ } LNMB; #if !defined(__VAXC)2#define lnmb$l_flags lnmb$r_flag_bits.lnmb$l_flags0#define lnmb$r_bits lnmb$r_flag_bits.lnmb$r_bits3#define lnmb$v_no_alias lnmb$r_bits.lnmb$v_no_alias1#define lnmb$v_confine lnmb$r_bits.lnmb$v_confine/#define lnmb$v_crelog lnmb$r_bits.lnmb$v_crelog-#define lnmb$v_table lnmb$r_bits.lnmb$v_table3#define lnmb$v_nodelete lnmb$r_bits.lnmb$v_nodelete9#define lnmb$v_clusterwide lnmb$r_bits.lnmb$v_clusterwide !75#define lnmb$v_remaction lnmb$r_bits.lnmb$v_remaction"#endif /* #if !defined(__VAXC) */ #define LNMX$M_CONCEALED 0x1#define LNMX$M_TERMINAL 0x2N#define LNMX$C_HSHFCN -128 /* Hash function value */N#define LNMX$C_BACKPTR -127 /* Backpointer translation */N#define LNMX$C_TABLE -126 /* Logical name table header */]#define LNMX$C_IGNORED_INDEX -125 /* Modified back pointer for process-private names */N#define LNMX "7$C_CW_LINKS -124 /* Links clusterwide LNMBs together */N#define LNMX$S_LNMXDEF 25 /* Old size name - synonym */ typedef struct _lnmx { __union {N unsigned int lnmx$l_flags; /* Translation attributes */ __struct {U unsigned lnmx$v_concealed : 1; /* Do not display result of translation */X unsigned lnmx$v_terminal : 1; /* Do not retranslate result of translation */( unsigned lnmx$v_fill_1 #7_ : 6; } lnmx$r_bits; } lnmx$r_flag_bits;N int lnmx$l_index; /* Translation index */X int lnmx$l_hash; /* Hash code for logical names in directories */N struct _lnmx *lnmx$l_next; /* Pointer to next lnmx */P unsigned int lnmx$l_pad; /* Padding to keep quadword alignment */N unsigned int lnmx$l_xlen; /* Length of translation string */N char lnmx$t_xlation; $7 /* Translation string */N/* Additional translation blocks follow xlation - */N/* pointed to by LNMX$L_NEXT. */ } LNMX; #if !defined(__VAXC)2#define lnmx$l_flags lnmx$r_flag_bits.lnmx$l_flags0#define lnmx$r_bits lnmx$r_flag_bits.lnmx$r_bits5#define lnmx$v_concealed lnmx$r_bits.lnmx$v_concealed3#define lnmx$v_terminal lnmx$r_bits.lnmx$v_terminal"#endif /* #if !defined(__VAXC) */ #d%7efine LNMX$S_CW_LNMX 36 typedef struct _cwlnmx { char lnmx$b_res_1 [24];P void *lnmx$l_cw_flink; /* Forward link for clusterwide names */Q void *lnmx$l_cw_blink; /* Backward link for clusterwide names */N struct _lnmb *lnmx$l_cw_lnmb; /* Pointer to LNMB start address */ } CWLNMX;#define LNMTH$M_SHAREABLE 0x1#define LNMTH$M_DIRECTORY 0x2#define LNMTH$M_GROUP 0x4#define LNMTH$M_SYSTEM 0x8 #define LNMTH$M_CLUSTERWIDE 0x10#def&7ine LNMTH$M_REMACTION 0x20N#define LNMTH$K_LENGTH 40 /* Length of header */N#define LNMTH$S_LNMTHDEF 40 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _orb; #endif /* #ifdef __cplusplus */ typedef struct _lnmth { __union {N unsigned int lnmth$l_flags; /* Logical name table flags */ __struct {\ unsigned lnmth$v_shareable : 1; /* Logical'7 name table is shareable (S0 space) */Y unsigned lnmth$v_directory : 1; /* Logical name table is a directory table */^ unsigned lnmth$v_group : 1; /* Logical name table is a group logical name table */b unsigned lnmth$v_system : 1; /* Logical name table is the system logical name table */N unsigned lnmth$v_clusterwide : 1; /* Table is "clusterwide" */\ unsigned lnmth$v_remaction : 1; /* Table is replicated on other cluster nodes */) (7 unsigned lnmth$v_fill_2_ : 2; } lnmth$r_bits; } lnmth$r_flag_bits;N void *lnmth$l_hash; /* Address of hash table */N struct _orb *lnmth$l_orb; /* Address of Object Rights Block */N struct _lnmb *lnmth$l_name; /* Address of containing LNMB block */N void *lnmth$l_parent; /* Address of parent table */N void *lnmth$l_child; /* Address of a child table */N vo )7id *lnmth$l_sibling; /* Address of a sibling table */N void *lnmth$l_qtable; /* Address of table holding quota */N int lnmth$l_byteslm; /* Initial quota */N int lnmth$l_bytes; /* Remaining quota */ } LNMTH; #if !defined(__VAXC)5#define lnmth$l_flags lnmth$r_flag_bits.lnmth$l_flags3#define lnmth$r_bits lnmth$r_flag_bits.lnmth$r_bits8#define lnmth$v_shareable lnmth$r_bits.lnm *7th$v_shareable8#define lnmth$v_directory lnmth$r_bits.lnmth$v_directory0#define lnmth$v_group lnmth$r_bits.lnmth$v_group2#define lnmth$v_system lnmth$r_bits.lnmth$v_system<#define lnmth$v_clusterwide lnmth$r_bits.lnmth$v_clusterwide8#define lnmth$v_remaction lnmth$r_bits.lnmth$v_remaction"#endif /* #if !defined(__VAXC) */ N#define LNMC$K_NUM_ENTRIES 25 /* Number of table header entries. */N#define LNMC$K_LENGTH 128 /* Length of header */N#define LN +7MC$S_LNMCDEF 128 /* Old size name - synonym */ typedef struct _lnmc {N struct _lnmc *lnmc$l_flink; /* Forward link in list */N struct _lnmc *lnmc$l_blink; /* Backward link in list */N unsigned short int lnmc$w_size; /* Size of LNMC in bytes */N unsigned char lnmc$b_type; /* Structure type for LNMC */N unsigned char lnmc$b_mode; /* Access mode */N unsi,7gned int lnmc$l_cacheindx; /* Current entry number */N void *lnmc$l_tbladdr; /* Logical name table name address */O unsigned int lnmc$l_procdirseq; /* Process directory sequence number */N unsigned int lnmc$l_sysdirseq; /* System directory sequence number */Q struct _lnmth *lnmc$l_entry [25]; /* Logical name table header addresses */ } LNMC;N#define LNMHSH$C_BUCKET 12 /* Length of fixed part of LNMHSH */N#define LNMHSH -7$K_BUCKET 12 /* Length of fixed part of LNMHSH */N#define LNMHSH$S_LNMHSHDEF 12 /* Old size name - synonym */ typedef struct _lnmhsh {N unsigned int lnmhsh$l_mask; /* Mask for hash value */N int lnmhsh$l_fill_1; /* Spare longword */N unsigned short int lnmhsh$w_size; /* Size of LNMHSH in bytes */N unsigned char lnmhsh$b_type; /* Structure type for LNMHSH */N char l.7nmhsh$b_fill_2; /* Spare byte */ } LNMHSH; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LNMSTRDEF_LOADED */ wwv[UM/***************************************************************/7************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** 07 **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 17 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:39 by OpenVMS SDL V3.7 */F/* Source: 12-MAY-1993 10:59:28 $1$DGA8345:[LIB_H.SRC]LOGDEF.SDL;1 *//***************************************************************************************************************** 27***************//*** MODULE $LOGDEF ***/#ifndef __LOGDEF_LOADED#define __LOGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointe37rs */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ 47 */N/* LOG - LOGICAL NAME BLOCK */N/* */N/* THERE IS ONE LOGICAL NAME BLOCK FOR EACH LOGICAL NAME ASSIGNMENT IN A */N/* SYSTEM. LOGICAL NAME BLOCKS CAN BE LINKED INTO ONE OF THREE TABLES: */N/* 1. A PER PROCESS TABLE. */N/* 2. A GROUP WIDE TABLE. */N/*57 3. THE SYSTEM WIDE TABLE. */N/*- */N#define LOG$K_LENGTH 20 /*LENGTH OF FIXED PART OF LOG */N#define LOG$C_LENGTH 20 /*LENGTH OF FIXED PART OF LOG */N#define LOG$C_SYSTEM 0 /*SYSTEM NAME TABLE */N#define LOG$C_GROUP 1 /*GROUP NAME TABLE */N#define LOG$C_PROCESS 2 67 /*PROCESS NAME TABLE */N/* */S#define LOG$C_NAMLENGTH 64 /*MAXIMUM LENGTH OF LOGICAL NAME STRING */N#define LOG$S_LOGDEF 20 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */struct _mb_ucb; #endif /* #ifdef __cplusplus */ typedef struct _logname {N void *log$l_ltfl; /*LOGICAL TABLE 77FORWARD LINK */N void *log$l_ltbl; /*LOGICAL TABLE BACKWARD LINK */N unsigned short int log$w_size; /*SIZE OF LOG IN BYTES */N unsigned char log$b_type; /*STRUCTURE TYPE FOR LOG */N unsigned char log$b_table; /*LOGICAL NAME TABLE TYPE */N unsigned short int log$w_group; /*CREATOR GROUP NUMBER */N unsigned char log$b_amod; /*ACCESS MODE OF CREATOR */N 87 char logdef$$_fill_1; /*SPARE BYTE */ __union {N struct _mb_ucb *log$l_mbxucb; /*MAILBOX UCB ADDRESS */ __struct {% char logdef$$_fill_2 [4];#if defined(__VAXC) char log$t_name[];#elseQ/* Warning: empty char[] member for log$t_name at end of structure not created */"#endif /* #if defined(__VAXC) */N/* */N/* LOGIC 97AL NAME TABLE NUMBERS */N/* */N/* MAXIMUM LENGTH OF LOGICAL NAME STRING */N/* */" } log$r_mbxucb_fields; } log$r_mbxucb_overlay; } LOGNAME; #if !defined(__VAXC)6#define log$l_mbxucb log$r_mbxucb_overlay.log$l_mbxucbF#define log$t_name log$r_m;7bxucb_overlay.log$r_mbxucb_fields.log$t_name"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LOGDEF_LOADED */ ww w[UM/*******************************************************************cM?OSRDEF{?OSRVDEF? OSSFLGDEF?$P1PLDEF?P2BDEF?PACDEFl PAGING_MACROS?bPBBDEF?8PBDEF?`PBHDEF?0PBODEF?VPCBDEF@PCIDEFA PCMCIADEFA PCSAMPLEDEF+APCTXDEFvA PD6729DEFAPDBDEFAPDTDEF\Bd PDTLISTDEFdBPDUDEFBPFBDEFBPFLDEFB PFLMAPDEFBPFNDEFB PFN_MACROSBPFREEDEF PMS_ROUTINES POOL_ZONESb PTE_FUNCTIONS RAD_MACROS SCH_ROUTINES. SCS_ROUTINES<7********/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** =7 **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** >7 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//******************************************************************************************************************* ?7*************//*** MODULE $LOOPDEF ***/#ifndef __LOOPDEF_LOADED#define __LOOPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointe@7rs */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ A7 */N/* Loopback message field definitions. */N/*--- */N#define LOOP$W_SKIPBYTES 2 /* The bytes to skip */ typedef struct _loopdef {N unsigned short int loop$w_skipcount; /* Skip count to function code */ } LOOPDEF; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas suB7pported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LOOPDEF_LOADED */ ww4w[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-PaC7ckard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, ID7nc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************** E7***************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LPBDEF ***/#ifndef __LPBDEF_LOADED#define __LPBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignmeF7nt __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #iG7fndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* LAN Port Block (LPB) used by network management */N/*-- */ c#if !defined H7(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _lpbdef {#pragma __nomember_alignmentN int lpb$l_flink; /* Forward link to next LBP */N int lpb$l_blink; /* Backword link to previous LBP */N short int lpb$w_size; /* Size of LBP */N char lpb$b_type; I7 /* Structure type (DYN$C_DECNET) */Q char lpb$b_subtype; /* Structure subtype DYN$C_NET_LAN_LPB */N void *lpb$a_lsb; /* Pointer to LSB for this port */N unsigned __int64 lpb$q_ucb; /* UCB NM area queue head */N unsigned __int64 lpb$q_descriptor; /* Generic descriptor */N void *lpb$a_eib; /* Pointer to EIB for this port */N int lpb$l_cnm_len; /* Allocated s J7ize of CNM item list */N void *lpb$a_cnm; /* Pointer to client name item list */P unsigned int lpb$l_port_ext; /* Port name extension (last 4 chars) */N int lpb$l_pnm_len; /* Port name item list length */N void *lpb$a_pnm; /* Pointer to port name item list */' unsigned char lpb$b_port_name [50];N/* Port name item list */ char lpb$b_fill_17_ [6]; } K7LPBDEF;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LPBDEF_LOADED */ ww[w[UM/***************************************************************************/M/** L7 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMM7S SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*******************************N7********************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $LSBDEF ***/#ifndef __LSBDEF_LOADED#def O7ine __LSBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknowP7n_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include `/* SDL has a bug which causes the BLISSF file to produce invalid LSB fields (missing commas). */O/*Q7 Workaround is to not allow it to produce a BLISSF definition for the LSB. */ N/*++ */N/* Define the LAN Station Block (LSB) fields. */N/* */N/* This structure represents a LAN station entity. There will be one used */O/* to represent each station. Each driver extends this structure to add its */N/* own device specifR7ic fields. */N/*-- */#define LSB$M_CREATED 0x1#define LSB$M_ENABLED 0x2#define LSB$M_BENABLED 0x4#define LSB$M_NMDIS 0x8#define LSB$M_ELAN 0x10#define LSB$M_CLIP 0x20#define LSB$M_TIMER 0x40#define LSB$M_LLAN 0x80#define LSB$M_FAILDEV 0x100#define LSB$M_FAST_TIMER 0x200#define LSB$M_FAIL_NVALID 0x400#define LSB$M_NM_MAC_ADDR 0x1N#define LSB$C_TIMUSB 240S7 /* Seconds with no USBs before we */N/* reduce RCVFIL/RCVADD */N#define LSB$C_MIN_RCV_MIN 32 /* Minimum value for RCVMNR */N#define LSB$C_DEF_RCV_MIN 128 /* Default value for RCVMNR */N#define LSB$C_MAX_RCV_MIN 1024 /* Maximum value for RCVMNR */N#define LSB$C_MIN_RCV_MAX 64 /* Minimum value for RCVMXR */N#define LSB$C_DEF_RCV_MAX 256 /* DefaultT7 value for RCVMXR */N#define LSB$C_MAX_RCV_MAX 1536 /* Maximum value for RCVMXR */N#define LSB$C_RCV_INC 8 /* Increase when SBU occurs */N#define LSB$C_RCV_DEC 1 /* Decrease when no SBU occurs */O#define LSB$C_RCV_ADD 64 /* Number of additional buffers that */N/* can be added to the rcvbuf queue */N#define LSB$C_QUEUES 1024 /* Start of LSB queues U7 */#define LSB$C_ABORT_QS 1N/* Number of queues from which we */#define LSB$C_QS_CLEAN_ACT 7N/* Number of Queues to clean up when */#define LSB$C_QS_CLEAN_INACT 8N/* Number of Queues to clean up when */#define LSB$C_INIT_QS 10N/* Number of Queues to be initialized */N#define LSB$G_V4_CTRSECT 1160 /* Start of counter sectioV7n */N#define LSB$G_END_V4_CTRSECT 1344 /* End of MOP V4 counter section */N/* The following counters are CSMACD architected counters, but they are */R#define LSB$C_QUAD_CTRSIZE_C 248 /* Size of quadword CSMACD counter area */N/* The following are the FDDI specific counters that are needed in addition */N#define LSB$G_PIVCLR 1704 /* Start of Phase IV clear counters */#define LSB$C_PIVSIZ 552N/* Size of Phase IV clear counters W7 */N#define LSB$G_CTRSECT 2258 /* Start of counter section */#define LSB$M_SFL_EXC 0x1#define LSB$M_SFL_CCF 0x2#define LSB$M_SFL_SHC 0x4#define LSB$M_SFL_OPC 0x8#define LSB$M_SFL_FTL 0x10#define LSB$M_SFL_RFD 0x20#define LSB$M_SFL_TUR 0x40#define LSB$M_SFL_TFL 0x80#define LSB$M_RFL_BCE 0x1#define LSB$M_RFL_FME 0x2#define LSB$M_RFL_FTL 0x4#define LSB$M_RFL_RSE 0x8#define LSB$M_RFL_RLE 0x10N#define LSB$G_END_CTRSECT 2312 /* EX7nd of counter section */#define LSB$M_TRSFL_TUR 0x1#define LSB$M_TRSFL_LE 0x2#define LSB$M_TRSFL_ABS 0x4#define LSB$M_TRSFL_LF 0x8#define LSB$M_TRSFL_TE 0x10#define LSB$M_TRSFL_UF 0x20#define LSB$M_TRSFL_RC 0x40#define LSB$M_TRRFL_RC 0x1#define LSB$M_TRRFL_FCE 0x2#define LSB$M_TRIFL_LWF 0x1#define LSB$M_TRIFL_SLE 0x2#define LSB$M_TRIFL_TMO 0x4#define LSB$M_TRIFL_RPT 0x8#define LSB$M_TRIFL_BCN 0x10#define LSB$M_TRIFL_DAD 0x20#define LSB$M_TRIFL_PSF 0xY740#define LSB$M_TRIFL_RR 0x80#define LSB$M_TRTFL_LWF 0x1#define LSB$M_TRTFL_SSD 0x2#define LSB$M_TRTFL_ARF 0x4#define LSB$M_TRTFL_RR 0x8N#define LSB$C_CTRSIZE 262 /* Size of counter area */N/* Miscellaneous characteristics of the device/driver */#define LSB$M_DEVCTR 0x1#define LSB$M_DEVXIDTEST 0x2#define LSB$M_MULSEG 0x4#define LSB$M_RCVMGT 0x8#define LSB$M_VLAN 0x10#define LSB$M_VIRTUAL 0x20#define LSB$M_LINKVALID 0x40#dZ7efine LSB$M_AUTOVALID 0x80#define LSB$M_JUMBOVALID 0x100#define LSB$M_TSO 0x200#define LSB$M_LRO 0x400#define LSB$M_IP_CSUM 0x800#define LSB$M_IPV6_CSUM 0x1000#define LSB$M_SCTP_CSUM 0x2000#define LSB$M_IP_RXCSUM 0x4000#define LSB$M_TXMBUF 0x8000#define LSB$M_RUN 0x1#define LSB$M_INITED 0x2#define LSB$M_MCA_OVF 0x4#define LSB$M_FAT_ERR 0x8#define LSB$M_BLKCTL 0x10#define LSB$M_PCHACT 0x20 #define LSB$M_NEED_DAT_LOCK 0x40#define LSB$M_GOT_DAT_LOCK 0x80#define [7LSB$M_RING_AVAIL 0x100#define LSB$M_FULL_DUPLEX 0x200$#define LSB$M_HOT_REPLACE_DRVR 0x400$#define LSB$M_HOT_REPLACE_ADAP 0x800#define LSB$M_FP_CPUAFF 0x1000#define LSB$M_AUTO_ENA 0x2000#define LSB$M_JUMBO_ENA 0x4000N#define LSB$C_ALLPRM 2560 /* Start of settable parameters */#define LSB$C_ALLPRMSIZ 12N/* End of the parameters that must match for all users. */#define LSB$C_CPYPRMSIZ 24N/* End of the parameters that are copied into the LSB on INI \7T. */ #define LSB$C_MCA_TABLE_SIZE 512#define LSB$C_MBX_MAX 12Q#define LSB$C_LLAN_FSET_MAX 136 /* Logical LAN's failset info.(SETMAC) */N#define LSB$C_SRVRTN_PCLI_PAR 1 /* PCLI device specific paramter, */N#define LSB$C_SRVRTN_VLAN_CONNECT 2 /* Connect VLAN block */N#define LSB$C_SRVRTN_VLAN_DISCONNECT 3 /* disconnect VLAN block */Q#define LSB$C_SRVRTN_AFFINITY 4 /* Underlying device has changed CPUDB */ #define LSB$K_SPAR ]7E_LONGWORDS 16N#define LSB$C_FIXED_LENGTH 7688 /* Size of fixed portion of the LSB */N/* This is the end of the common section for all drivers. However, we have */$#define LSB$M_CSMACD_ELAN_ACTIVE 0x1##define LSB$M_CSMACD_ELAN_START 0x2"#define LSB$M_CSMACD_ELAN_SHUT 0x4)#define LSB$M_CSMACD_ELAN_UNAVAILABLE 0x8##define LSB$M_CSMACD_LIS_ACTIVE 0x1"#define LSB$M_CSMACD_LIS_START 0x2!#define LSB$M_CSMACD_LIS_SHUT 0x4(#define LSB$M_CSMACD_LIS_UNAVAILABLE 0x8N#define LSB$C_CSMACD_L ^7ENGTH 8136 /* Size of base CSMACD LSB */#define LSB$M_FDDI_BOO 0x1#define LSB$M_FDDI_CTY 0x2#define LSB$M_FDDI_UNTO 0x4N#define LSB$C_FDDI_LENGTH 7848 /* Size of base FDDI LSB */N/* Values for LSB$L_LINK_STATE */#define LSB$C_FDDI_OFF_INIT 0#define LSB$C_FDDI_OFF_READY 1"#define LSB$C_FDDI_OFF_FAULT_REC 2!#define LSB$C_FDDI_ON_RING_INIT 3 #define LSB$C_FDDI_ON_RING_RUN 4#define LSB$C_FDDI_BROKEN 5N/* _7 Values for LSB$L_RP_STATE */#define LSB$C_FDDI_OFF 0 #define LSB$C_FDDI_CAND_PURGER 1#define LSB$C_FDDI_NON_PURGER 2#define LSB$C_FDDI_PURGER 3N/* Values for LSB$L_FDDI_DAT */N#define LSB$C_FDDI_UNK 0 /* Unknown */N#define LSB$C_FDDI_SUC 1 /* Success */N#define LSB$C_FDDI_FAIL 2 /* Failed `7 */N/* Values for LSB$L_FDDI_PHY_STATE */N#define LSB$C_FDDI_INT_LOOP 0 /* Internal loopback */N#define LSB$C_FDDI_PHY_BROKEN 1 /* Broken */N#define LSB$C_FDDI_PHY_OFF_READY 2 /* Off ready */N#define LSB$C_FDDI_WAITING 3 /* Waiting */N#define LSB$C_FDDI_STARTING 4 /* Starting */N#define LSa7B$C_FDDI_FAILED 5 /* Failed */N#define LSB$C_FDDI_WATCH 6 /* Watch */N#define LSB$C_FDDI_IN_USE 7 /* In use */N/* Default values for MAC parameters */N#define LSB$C_FDDI_T_REQ_DFLT 100000 /* 8 ms in 80ns units */N#define LSB$C_FDDI_TVX_DFLT 32768 /* 2.62144 ms in 80ns units */N#define LSB$C_FDDI_RTTO_DFLT 1250000 b70 /* 1000 ms in 80ns units */#define LSB$C_MAX_XPLOR_BUF 6N#define LSB$C_TR_LENGTH 7816 /* Size of base TR LSB */N#define LSB$C_TR_SPEED_4 0 /* Speed Values */#define LSB$C_TR_SPEED_16 1N#define LSB$C_TR_LNK_OFF 1 /* Link State Values */#define LSB$C_TR_LNK_INI 2#define LSB$C_TR_LNK_RUN 3#define LSB$C_TR_LNK_RCY 4#define LSB$C_TR_LNK_CNT 5#define LSB$C_TR_LNK_BRK 2N#define LSB$C_ATM_LEc7NGTH 7808 /* Size of base ATM LSB */  9#ifdef __cplusplus /* Define structure prototypes */ struct _vlan; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */#else#pragma __nomember_alignment#endiftypedef struct _lsbdef {N/* Embedded extended fork blocks */N/* The first part of the LSB is the fork block for the Interrupt Servi d7ce */N/* Routine. That fork block is always first because it is the most used */N/* fork block and placing it first makes that code more efficient. The */N/* other fork blocks follow the ISR fork block */#pragma __nomember_alignment char lsb$g_efbisr [64];N/* Interrupt Service Rtn Fork Block */ char lsb$g_efbipl8 [64];N/* IPL 8 Fork Block */ che7ar lsb$g_efbreset [64];N/* Reset Fork Block */ char lsb$g_efbnm [64];N/* Network Management Fork Block */N unsigned int lsb$l_error; /* Fatal error code */N int lsb$l_extra_l_0; /* Preserve quadword alignment */N/* Fields for ring pointers/indices for PUT/GET RCV/XMT/CMD/UNS/SMT */N unsigned int lsb$l_putrcv; /* Put RCV ff7ield */N unsigned int lsb$l_getrcv; /* Get RCV field */N unsigned int lsb$l_putxmt; /* Put XMT field */N unsigned int lsb$l_getxmt; /* Get XMT field */N unsigned int lsb$l_putcmd; /* Put CMD field */N unsigned int lsb$l_getcmd; /* Get CMD field */N unsigned int lsb$l_putuns; /* Put UNS field */g7N unsigned int lsb$l_getuns; /* Get UNS field */N unsigned int lsb$l_putsmt; /* Put SMT field */N unsigned int lsb$l_getsmt; /* Get SMT field */N/* Counters for requests outstanding/available */N unsigned int lsb$l_xmtavl; /* XMT entries owned by host */N unsigned int lsb$l_rcvcnt; /* RCV buffers owned by device */N unsigned int lsb$l_xh7mtcnt; /* XMT entries owned by device */N unsigned int lsb$l_cmdcnt; /* CMD entries owned by device */N unsigned int lsb$l_unscnt; /* UNS entries owned by device */N unsigned int lsb$l_smtcnt; /* SMT entries owned by device */N/* Fields for pointing at rings for SDA display */N void *lsb$a_rcvrng; /* Address of RCV ring */N unsigned int lsb$l_rcvent; /* Number i7of entries in RCV ring */N unsigned int lsb$l_rcvsiz; /* Number of bytes in RCV entry */N void *lsb$a_xmtrng; /* Address of XMT ring */N unsigned int lsb$l_xmtent; /* Number of entries in XMT ring */N unsigned int lsb$l_xmtsiz; /* Number of bytes in XMT entry */N void *lsb$a_cmdrng; /* Address of CMD ring */N unsigned int lsb$l_cmdent; /* Number of entries in CMD ring j7*/N unsigned int lsb$l_cmdsiz; /* Number of bytes in CMD entry */N void *lsb$a_unsrng; /* Address of UNS ring */N unsigned int lsb$l_unsent; /* Number of entries in UNS ring */N unsigned int lsb$l_unssiz; /* Number of bytes in UNS entry */N void *lsb$a_smtrng; /* Address of SMT ring */N unsigned int lsb$l_smtent; /* Number of entries in SMT ring */N unsigned int lsb$lk7_smtsiz; /* Number of bytes in SMT entry */N/* These scratch fields are not "extra" fields. They are fields that are */N/* used as temporary storage by any piece of the LAN drivers. */N unsigned int lsb$l_scratch1; /* Scratch longword */N unsigned int lsb$l_scratch2; /* Scratch longword */S unsigned int lsb$l_scratch3; /* Reserved for source address filtering */N unsigned int lsb$l_scratch4; /*l7 Scratch longword */N unsigned int lsb$l_scratch5; /* Scratch longword */N/* Fields that describe the driver and device version */N unsigned int lsb$l_lan_code; /* Address of LAN code */N unsigned int lsb$l_drv_code; /* Address of Driver code */N unsigned int lsb$l_dev1_code; /* Address of Device code */N unsigned int lsb$l_dev2_code; /* Address of Device code m7 */N unsigned __int64 lsb$q_lan_version; /* LAN version number */N unsigned __int64 lsb$q_drv_version; /* DRV version number */N unsigned __int64 lsb$q_dev1_version; /* Device version number */N unsigned __int64 lsb$q_dev2_version; /* Device version number */N char lsb$t_hw_serial [12]; /* Hardware serial number (12 char) */N unsigned int lsb$l_hw_version; /* Hardware version number */N unsigned _n7_int64 lsb$q_hw_bvc; /* Hardware boot verification code */N/* Fields that describe the station */ char lsb$g_ldc [40];N/* The structure for the LAN */N/* device characteristics */N unsigned int lsb$l_device; /* The DT$_ value for this device */N unsigned int lsb$l_next_lsb; /* Linked list of LSBs */N void *lsb$ o7a_baselsb; /* Parent LSB pointer */N unsigned int lsb$l_tso_mtu; /* Max mtu for TSO */ __union {! unsigned int lsb$l_flags; __struct {N unsigned lsb$v_created : 1; /* Station is created */N unsigned lsb$v_enabled : 1; /* Station is enabled */N unsigned lsb$v_benabled : 1; /* Station has been enabled */N unsigned lsb$v_nmdis : 1; /* Netp7 Man disable in progress */N unsigned lsb$v_elan : 1; /* Station is for an Emulated LAN */N unsigned lsb$v_clip : 1; /* Station is for Classical IP */N unsigned lsb$v_timer : 1; /* One-second timer enabled */N unsigned lsb$v_llan : 1; /* Station is for a Logical LAN */N unsigned lsb$v_faildev : 1; /* Station can be in a failover set */N unsigned lsb$v_fast_timer : 1; /* Transmit timer is faster q7 */V unsigned lsb$v_fail_nvalid : 1; /* Station is down in LAN FAILOVER set */( unsigned lsb$v_fill_46_ : 5; } lsb$r_fill_21_; } lsb$r_fill_20_;N/* Related data structure pointers */N unsigned int lsb$l_adp; /* Address of the ADP */N unsigned int lsb$l_idb; /* Address of the IDB */N unsigned int lsb$l_ucb0; /* Address of UCB #0 r7 */N/* Network management fields */N void *lsb$a_eib; /* Entity Instance Block address */N unsigned int lsb$l_events; /* Number of events logged */N void *lsb$a_nm_llb; /* Pointer to LLB (LAN Link Block) */P void *lsb$a_nm_lhb; /* Pointer to LHB (LAN PHYPort Block) */N unsigned __int64 lsb$q_nm_lpb; /* LPB (LAN Port Block) queue head */N int lsb$s7l_nm_snm_len; /* Size of station name item list */O void *lsb$a_nm_snm; /* Pointer to station name item list */N unsigned int lsb$l_nm_last_port; /* Last used port name extension */ __union {N unsigned int lsb$l_nm_flags; /* Flags - */ __struct {N unsigned lsb$v_nm_mac_addr : 1; /* 0 = no address specified */N/* 1 = address specified */ t7( unsigned lsb$v_fill_47_ : 7; } lsb$r_fill_23_; } lsb$r_fill_22_;N unsigned int lsb$l_nm_min_tid; /* Lowest SMT Transaction ID in the */N/* Network Management TID range, */N/* initialized by driver. */O unsigned int lsb$l_nm_max_tid; /* Highest SMT Transaction ID in the */N/* Network Management TID range, */Nu7/* initialized by driver. */N unsigned __int64 lsb$q_nm_desc; /* Generic descriptor */N unsigned int lsb$l_station_buf; /* Station buffer parameter */N unsigned int lsb$l_nm_scratch; /* Scratch field for calling C code */N/* Medium specific LAN routines available through the LSB. */N void *lsb$a_init_vcib; /* Init VCIB for this medium */N void *lsb$a_allocate_vv7crp; /* Allocate VCRP for this medium */N/* Time stamp fields (all values stored from ABSTIMTICS) */N unsigned int lsb$l_cretim; /* Time the module was last created */N unsigned int lsb$l_deltim; /* Time the module was last deleted */N unsigned int lsb$l_enatim; /* Time the module was last enabled */O unsigned int lsb$l_distim; /* Time the module was last disabled */N unsigned int lsb$l_lstrcvtim; /* Time ofw7 last station receive */N unsigned int lsb$l_lstxmttim; /* Time of last transmit complete */N unsigned int lsb$l_lstftltim; /* Time of last fatal error */N unsigned int lsb$l_prvftltim; /* Time of previous fatal error */N unsigned int lsb$l_lstexctim; /* Time of last excessive collision */P unsigned int lsb$l_lstcartim; /* Time of last loss of carrier error */O unsigned int lsb$l_lstcoltim; /* Time of last late collision errx7or */N unsigned int lsb$l_lstcrctim; /* Time of last receive CRC error */N unsigned int lsb$l_lstlentim; /* Time of last length error */N unsigned int lsb$l_lstusbtim; /* Time of last USB error */N unsigned int lsb$l_lstuubtim; /* Time of last UUB error */Q unsigned int lsb$l_lstxertim; /* Time of last generic transmit error */P unsigned int lsb$l_lstrertim; /* Time of last generic receive error */N unsignedy7 int lsb$l_datxmttim; /* Time a DAT transmit completed */N unsigned int lsb$l_datrcvtim; /* Time a DAT receive was found */N unsigned int lsb$l_lstrnatim; /* Time of last ring not available */N unsigned int lsb$l_lstravtim; /* Time of last ring available */Y unsigned int lsb$l_lstriitim; /* Time of last Ring Inits initiated (locally) */Z unsigned int lsb$l_lstrirtim; /* Time of last Ring Inits initiated (remotely) */P unsigned iz7nt lsb$l_lstrbitim; /* Time of last Ring Beacon initiated */N unsigned int lsb$l_lstdattim; /* Time of last DAT failure */S unsigned int lsb$l_lstdtdtim; /* Time of last Duplicate Token received */N unsigned int lsb$l_lstrprtim; /* Time of last Ring Purger error */N unsigned int lsb$l_lstfcitim; /* Time of last FCI strip errors */N unsigned int lsb$l_lsttritim; /* Time of last PC Trace initiated */N unsigned int lsb$l_lsttrrtim{7; /* Time of last PC Trace received */S unsigned int lsb$l_lstdbctim; /* Time of last Directed beacon received */R unsigned int lsb$l_lstebetim; /* Time of last Elasticity buffer error */N unsigned int lsb$l_lstlcttim; /* Time of last LCT Reject error */N unsigned int lsb$l_lstlemtim; /* Time of last LEM Reject error */N unsigned int lsb$l_lstlnktim; /* Time of last Link error */P unsigned int lsb$l_lstcnctim; /* Time |7of last Connections Completed */N unsigned int lsb$l_lsteentim; /* Time of last ELAN enable */N unsigned int lsb$l_lsteditim; /* Time of Last ELAN disable */N unsigned int lsb$l_lsteactim; /* Time of Last ELAN active */N unsigned int lsb$l_lsteuntim; /* Time of Last ELAN unavailable */N/* Timer fields */N unsigned int lsb$l_ctltim; /* Control timer }7 */N unsigned int lsb$l_xmttim; /* Transmit timer */N unsigned int lsb$l_sidtim; /* Periodic SYSID timer */N unsigned int lsb$l_unatim; /* Ring unavailable timer */P unsigned int lsb$l_usbtim; /* Seconds remaining for no USB - for */N/* adjusting receive buffers */N unsigned int lsb$l_usbsav; /* Saved USB value for checking for */N/* a change in U~7SB since last second */N/* Receive buffer fields */N unsigned int lsb$l_rcvmnr; /* Minimum buffers request by mgmt */N unsigned int lsb$l_rcvmxr; /* Maximum buffers request by mgmt */N unsigned int lsb$l_rcvmin; /* Minimum limit for RCVFIL */N unsigned int lsb$l_rcvmax; /* Maximum limit for RCVFIL */N unsigned int lsb$l_rcvcur; /*7 Current number of buffers */N unsigned int lsb$l_rcvfil; /* Desired number of buffers */N unsigned int lsb$l_rcvadd; /* Number of buffers allowed when */N/* adding buffers from upper layers */N/* Generic counters (all counters wrap) (end all names in CTR) */P unsigned int lsb$l_crectr; /* Number of times module was created */P unsigned int lsb$l_enactr; /* Number of times module 7was enabled */N unsigned int lsb$l_prtctr; /* Number of ports */N unsigned int lsb$l_excctr; /* Number of excessive collisions */N unsigned int lsb$l_ftlctr; /* Number of fatal errors detected */N unsigned int lsb$l_xmttmo; /* Number of transmit timeouts */N unsigned int lsb$l_ctltmo; /* Number of control timeouts */N unsigned int lsb$l_rsfctr; /* Number of restart failures */N unsign7ed int lsb$l_powerf; /* Number of powerfailures */N unsigned int lsb$l_xnwctr; /* Number of no work transmits */N unsigned int lsb$l_xbpctr; /* Number of Bad PTE transmits */N unsigned int lsb$l_xgpctr; /* Number of Global Page transmits */N unsigned int lsb$l_xsbctr; /* Number of SVAPTE/BOFF transmits */P unsigned int lsb$l_xbactr; /* Number of BUFFER_ADDRESS transmits */N unsigned int lsb$l_arpctr; 7 /* Number of auto restarts pending */N/* Duplicate address test fields */N unsigned int lsb$l_dat_inictr; /* Number of times DAT was started */N unsigned int lsb$l_dat_errctr; /* Number of times DAT failed */N unsigned int lsb$l_dat_stage; /* The DAT stage */N unsigned int lsb$l_dat_vcrp; /* VCRP to xmt the LOOPBACK request */N unsigned __int64 lsb$q_dat_xmtsts; /* Status of the LOO7PBACK transmit */N unsigned int lsb$l_dat_reqnum; /* DAT request number */N void *lsb$a_dat_ucb; /* For TR only -- DATing UCB */N/* Internal diagnostic fields */N unsigned int lsb$l_devdepend; /* Extra status flags */P unsigned int lsb$l_lsterrcsr; /* Value of CSR afer last fatal error */N unsigned int lsb$l_lstftlcod; /* Fatal error code */N 7unsigned int lsb$l_prvftlcod; /* Previous Fatal error code */N unsigned __int64 lsb$q_lstcrcsrc; /* Last source address of CRC error */N/* Trace fields. */N void *lsb$a_trace; /* Trace buffer address */N/* (skips the 32-bytes of trace header) */c unsigned int lsb$l_trclen; /* Trace buffer allocated length (bytes)(multiple of 32) */N/* (incl7udes the trace header chunk) */N unsigned __int64 lsb$q_trcmask; /* Trace mask */X unsigned __int64 lsb$q_trcmask_save; /* Trace mask (saved during trace data read) */N unsigned __int64 lsb$q_trcstop; /* Trace stop mask */y unsigned int lsb$l_trcindex; /* Trace current index (8..TRCCOUNT-1)(index for trace entry about to be made) */[ unsigned int lsb$l_trccount; /* Trace buffer entr7y count ((TRCLEN - 32) / 32) */N/* (excludes the first trace buffer entry reserved as the trace header) */l unsigned int lsb$l_trcseq; /* Trace data sequence number (1..n)(next sequence number to use) */R unsigned int lsb$l_trcintp; /* Trace data interrupt producer (0..7) */R unsigned int lsb$l_trcintc; /* Trace data interrupt consumer (0..7) */k unsigned int lsb$l_trcafter; /* Trace entries to record after stop condition has been reached */X 7unsigned int lsb$l_trcnextrd; /* Trace index next to read (8..TRCCOUNT - 1) */N unsigned int lsb$l_trcversion; /* Trace version 1 or 2 */N unsigned int lsb$l_trcmaskdrv; /* Trace mask default driver bits */N void *lsb$a_trcmaskdef; /* Trace mask definition */N/* Queues for holding requests. Note that the ABORT queues cannot be */N/* queues that hold requests that have set the BLKCTL flag. If so, there */N/* will be a hang wh7en the request that blocked the CTLHLD queue is aborted */N/* because the flag is not cleared by the abort process. The flags that */N/* can hold control requests that have set the BLKCTL flag include CTLREQ, */N/* CTLPND, XMTPND, POST, and DELAY. */N/* */N/* CTLHLD queue was moved to be non-abortable due to an existing dependency */N/* by the DAT process. 7 */N unsigned __int64 lsb$q_xmtreq; /* Transmit request queue */N/* abort requests */N unsigned __int64 lsb$q_ctlhld; /* Control hold queue */N unsigned __int64 lsb$q_ctlreq; /* Control request queue */N unsigned __int64 lsb$q_ctlpnd; /* Control pending queue */N unsigned __int64 lsb$q_post; /* Post process queue 7 */N unsigned __int64 lsb$q_delay; /* Delay queue (must be last) */N unsigned __int64 lsb$q_xmtpnd; /* Transmit pending queue */N/* the device remains active */N unsigned __int64 lsb$q_rcvpnd; /* Receive pending queue */N/* the device is inactive */N/* The autorestart queue should not be part of the regular queues because */N/* it should not b7e emptied when there is a fatal error. */N unsigned __int64 lsb$q_autors; /* Automatic restart queue */N unsigned __int64 lsb$q_nmhold; /* Network management hold queue */N/* The RCVBUF queue is a single linked list and hence does not need to */N/* be initialized as a queue. */N unsigned __int64 lsb$q_rcvbuf; /* Receive buffer list */N/* Chaining information 7 */N unsigned int lsb$l_min_chain; /* Minimum number of bytes in the */N/* first entry of a transmit chain */N unsigned int lsb$l_min_xmt; /* Minimum number of bytes that can */N/* be transmitted (either 0 or 60) */N unsigned int lsb$l_align_phy; /* Physically contiguous flag */N/* (zero if not requested, bit number 7 */N/* of alignment if so) */O unsigned int lsb$l_align_mask; /* Receive buffer alignment mask (if */N/* ALIGN_PHY set then it is the offset */N/* into VCRP for VCRP$T_LAN_DATA) */N unsigned int lsb$l_bsz; /* Size of receive buffer data area */P unsigned int lsb$l_devhdr_len; /* Device specific xmit header length */N int lsb$7l_svapte_fill; /* Obsolete */N unsigned int lsb$l_sva; /* SVA of first byte of first page */N/* Non-architected counters */N unsigned __int64 lsb$q_lbuctr; /* Link buffer unavailable (FDDI) */N/* Note: This "CTR" section must match the clear ("CLR") section that */N/* follows this section. */N/* Architected Phase V counter section 7 (These must match the MOP V4 */N/* counter response packet format) */ __union {N unsigned __int64 lsb$q_quad_ctrsect; /* Start of quadword counters */N unsigned __int64 lsb$q_zerctr; /* Seconds since last zeroed */% } lsb$r_lsb_quad_ctr_overlay;N unsigned __int64 lsb$q_ocrctr; /* Octets received */N unsigned __int64 lsb$q_octctr; /* Octets sent */N unsi7gned __int64 lsb$q_pdrctr; /* PDUs received */N unsigned __int64 lsb$q_pdtctr; /* PDUs sent */N unsigned __int64 lsb$q_morctr; /* Multicast octets received */N unsigned __int64 lsb$q_mprctr; /* Multicast PDUs received */N unsigned __int64 lsb$q_defctr; /* Initially deferred PDUs sent */N unsigned __int64 lsb$q_sinctr; /* Single collision PDUs sent */N unsigned __int64 lsb$q_mulctr;7 /* Multiple collision PDUs sent */N unsigned __int64 lsb$q_excctr; /* Excessive collisions */N unsigned __int64 lsb$q_ccfctr; /* Carrier check failures */N unsigned __int64 lsb$q_shcctr; /* MOP ONLY Short circuit failure */N unsigned __int64 lsb$q_opcctr; /* MOP ONLY Open circuit failure */N unsigned __int64 lsb$q_ttlctr; /* MOP ONLY Transmit too long */N unsigned __int64 lsb$q_latctr; /* Late collisions 7 */N unsigned __int64 lsb$q_fcectr; /* Frame check errors */N unsigned __int64 lsb$q_alictr; /* Alignment errors */N unsigned __int64 lsb$q_ftlctr; /* Frames too long */O unsigned __int64 lsb$q_uidctr; /* Unrecognized individual dest PDUs */N unsigned __int64 lsb$q_dorctr; /* Data overruns */N unsigned __int64 lsb$q_usbctr; /* Unavailable station buffers */N 7unsigned __int64 lsb$q_uubctr; /* Unavailable user buffers */N unsigned __int64 lsb$q_cdcctr; /* Collision detect check failures */N/* not part of the MOP V4 Counter Response packet format so they do not */N/* have to be in any special order and they cannot be included with the */N/* counters above this comment. */N unsigned __int64 lsb$q_motctr; /* Multicast octets sent */N unsigned __int64 lsb$q_mpt7ctr; /* Multicast PDUs sent */N unsigned __int64 lsb$q_fsectr; /* Frame size errors */N unsigned __int64 lsb$q_slectr; /* Send data length errors */N unsigned __int64 lsb$q_rdlctr; /* Receive data length errors */N unsigned __int64 lsb$q_umdctr; /* Unrecognized multicast dest PDUs */N unsigned __int64 lsb$q_stfctr; /* Station failures */N/* to some of the counters above. 7 */N unsigned __int64 lsb$q_turctr; /* Transmit underrun */N unsigned __int64 lsb$q_tflctr; /* Transmit failure */N unsigned __int64 lsb$q_rsectr; /* Frame status error */N unsigned __int64 lsb$q_rlectr; /* Frame length error */N unsigned __int64 lsb$q_mfcctr; /* MAC frame count */N unsigned __int64 lsb$q_mecctr; /* MAC error count */N 7 unsigned __int64 lsb$q_mlcctr; /* MAC lost count */N unsigned __int64 lsb$q_riictr; /* Ring initializations initiated */N unsigned __int64 lsb$q_rirctr; /* Ring initializations received */N unsigned __int64 lsb$q_rbictr; /* Ring beacons initiated */N unsigned __int64 lsb$q_datctr; /* Duplicate address test failures */N unsigned __int64 lsb$q_dtdctr; /* Duplicate tokens detected */N unsigned __int64 lsb$q_r7prctr; /* Ring purge errors */N unsigned __int64 lsb$q_fcictr; /* FCI strip errors */N unsigned __int64 lsb$q_trictr; /* Traces initiated */N unsigned __int64 lsb$q_trrctr; /* Traces received */N unsigned __int64 lsb$q_dbcctr; /* Directed beacons received */N unsigned __int64 lsb$q_ebectr; /* Elasticity buffer error */N unsigned __int64 lsb$q_lctctr; /* LCT rejects7 */N unsigned __int64 lsb$q_lemctr; /* LEM rejects */N unsigned __int64 lsb$q_lnkctr; /* Link errors */N unsigned __int64 lsb$q_cncctr; /* Connections completed */N/* Token Ring Specific Counters. */N/* */N/* The following counters are used from FDDI. */N7/* TURCTR */N/* TFLCTR */N/* RBICTR */N unsigned __int64 lsb$q_berctr; /* Burst Errors */N unsigned __int64 lsb$q_raectr; /* Ring Poll errors */N unsigned __int64 lsb$q_lerctr; /* Line Errors */N unsigned __int64 lsb$q7_tlfctr; /* Lost Frames Errors */N unsigned __int64 lsb$q_fcpctr; /* Frame Copied Errors */N unsigned __int64 lsb$q_terctr; /* Token Errors */N unsigned __int64 lsb$q_sigctr; /* Signal Loss */N unsigned __int64 lsb$q_rbectr; /* Ring Beaconing */N unsigned __int64 lsb$q_serctr; /* Soft Errors Reported */N unsigned __int64 lsb$q_lwfctr; /* Lobe Wire7 Fault */N unsigned __int64 lsb$q_arectr; /* Auto Removal Error */N unsigned __int64 lsb$q_rmrctr; /* Remove Received */N unsigned __int64 lsb$q_sstctr; /* Single Station Detected */N unsigned __int64 lsb$q_rrectr; /* Ring Recovery */N unsigned __int64 lsb$q_adsctr; /* Abort Delimiters sent (transmit) */N unsigned __int64 lsb$q_ierctr; /* Internal Errors */7N/* Phase IV clear counter section (This section must match the Phase V */N/* counter section above) */N unsigned __int64 lsb$q_zerclr; /* Seconds since last zeroed */N unsigned __int64 lsb$q_ocrclr; /* Octets received */N unsigned __int64 lsb$q_octclr; /* Octets sent */N unsigned __int64 lsb$q_pdrclr; /* PDUs received */N unsigned __int64 lsb7$q_pdtclr; /* PDUs sent */N unsigned __int64 lsb$q_morclr; /* Multicast octets received */N unsigned __int64 lsb$q_mprclr; /* Multicast PDUs received */N unsigned __int64 lsb$q_defclr; /* Initially deferred PDUs sent */N unsigned __int64 lsb$q_sinclr; /* Single collision PDUs sent */N unsigned __int64 lsb$q_mulclr; /* Multiple collision PDUs sent */N unsigned __int64 lsb$q_excclr; /* Excessi7ve collisions */N unsigned __int64 lsb$q_ccfclr; /* Carrier check failures */N unsigned __int64 lsb$q_shcclr; /* MOP ONLY Short circuit failure */N unsigned __int64 lsb$q_opcclr; /* MOP ONLY Open circuit failure */N unsigned __int64 lsb$q_ttlclr; /* MOP ONLY Transmit too long */N unsigned __int64 lsb$q_latclr; /* Late collisions */N unsigned __int64 lsb$q_fceclr; /* Frame check errors 7*/N unsigned __int64 lsb$q_aliclr; /* Alignment errors */N unsigned __int64 lsb$q_ftlclr; /* Frames too long */O unsigned __int64 lsb$q_uidclr; /* Unrecognized individual dest PDUs */N unsigned __int64 lsb$q_dorclr; /* Data overruns */N unsigned __int64 lsb$q_usbclr; /* Unavailable station buffers */N unsigned __int64 lsb$q_uubclr; /* Unavailable user buffers */N unsigned __int647 lsb$q_cdcclr; /* Collision detect check failures */N unsigned __int64 lsb$q_motclr; /* Multicast octets sent */N unsigned __int64 lsb$q_mptclr; /* Multicast PDUs sent */N unsigned __int64 lsb$q_fseclr; /* Frame size errors */N unsigned __int64 lsb$q_sleclr; /* Send data length errors */N unsigned __int64 lsb$q_rdlclr; /* Receive data length errors */N unsigned __int64 lsb$q_umdclr; /* Unr7ecognized multicast dest PDUs */N unsigned __int64 lsb$q_stfclr; /* Station failures */N unsigned __int64 lsb$q_turclr; /* Transmit underrun */N unsigned __int64 lsb$q_tflclr; /* Transmit failure */N unsigned __int64 lsb$q_rseclr; /* Frame status error */N unsigned __int64 lsb$q_rleclr; /* Frame length error */N unsigned __int64 lsb$q_mfcclr; /* MAC frame count 7 */N unsigned __int64 lsb$q_mecclr; /* MAC error count */N unsigned __int64 lsb$q_mlcclr; /* MAC lost count */N unsigned __int64 lsb$q_riiclr; /* Ring initializations initiated */N unsigned __int64 lsb$q_rirclr; /* Ring initializations received */N unsigned __int64 lsb$q_rbiclr; /* Ring beacons initiated */N unsigned __int64 lsb$q_datclr; /* Duplicate address test failures */N unsigned __int764 lsb$q_dtdclr; /* Duplicate tokens detected */N unsigned __int64 lsb$q_rprclr; /* Ring purge errors */N unsigned __int64 lsb$q_fciclr; /* FCI strip errors */N unsigned __int64 lsb$q_triclr; /* Traces initiated */N unsigned __int64 lsb$q_trrclr; /* Traces received */N unsigned __int64 lsb$q_dbcclr; /* Directed beacons received */N unsigned __int64 lsb$q_ebeclr; /* E7lasticity buffer error */N unsigned __int64 lsb$q_lctclr; /* LCT rejects */N unsigned __int64 lsb$q_lemclr; /* LEM rejects */N unsigned __int64 lsb$q_lnkclr; /* Link errors */N unsigned __int64 lsb$q_cncclr; /* Connections completed */N unsigned __int64 lsb$q_berclr; /* Burst Errors */N unsigned __int64 lsb$q_raeclr; /* Ring Poll errors 7 */N unsigned __int64 lsb$q_lerclr; /* Line Errors */N unsigned __int64 lsb$q_tlfclr; /* Lost Frames Errors */N unsigned __int64 lsb$q_fcpclr; /* Frame Copied Errors */N unsigned __int64 lsb$q_terclr; /* Token Errors */N unsigned __int64 lsb$q_sigclr; /* Signal Loss */N unsigned __int64 lsb$q_rbeclr; /* Ring Beaconing */N unsigned __i7nt64 lsb$q_serclr; /* Soft Errors Reported */N unsigned __int64 lsb$q_lwfclr; /* Lobe Wire Fault */N unsigned __int64 lsb$q_areclr; /* Auto Removal Error */N unsigned __int64 lsb$q_rmrclr; /* Remove Received */N unsigned __int64 lsb$q_sstclr; /* Single Station Detected */N unsigned __int64 lsb$q_rreclr; /* Ring Recovery */N unsigned __int64 lsb$q_adsclr; /*7 Abort Delimiters sent (transmit) */N unsigned __int64 lsb$q_ierclr; /* Internal Errors */N short int lsb$w_extra_w_0; /* Preserve quadword alignment */N unsigned short int lsb$w_zerctr; /* Seconds since last zeroed */N unsigned int lsb$l_brcctr; /* Bytes received */N unsigned int lsb$l_bsnctr; /* Bytes sent */N unsigned int lsb$l_dbrctr; /* Frames received 7 */N unsigned int lsb$l_dbsctr; /* Frames sent */N unsigned int lsb$l_mbyctr; /* Multicast bytes received */N unsigned int lsb$l_mblctr; /* Multicast frames received */N unsigned int lsb$l_bidctr; /* Frames sent, initially deferred */N unsigned int lsb$l_bs1ctr; /* Frames sent, single collision */N unsigned int lsb$l_bsmctr; /* Frames sent, multiple collisions */N unsigned s 7hort int lsb$w_sflctr; /* Send failure */ __union {N unsigned short int lsb$w_sflmap; /* Send failure reason bitmap */ __struct {N unsigned lsb$v_sfl_exc : 1; /* Excessive collisions */N unsigned lsb$v_sfl_ccf : 1; /* Carrier check failure */N unsigned lsb$v_sfl_shc : 1; /* Short Circuit */N unsigned lsb$v_sfl_opc : 1; /* Open Circuit */N 7 unsigned lsb$v_sfl_ftl : 1; /* Frame too long */N unsigned lsb$v_sfl_rfd : 1; /* Remote failure to defer */N unsigned lsb$v_sfl_tur : 1; /* Transmit underrun */N unsigned lsb$v_sfl_tfl : 1; /* Transmit failure */ } lsb$r_fill_25_; } lsb$r_fill_24_;N unsigned short int lsb$w_rflctr; /* Receive failure */ __union {N unsigned short int lsb$w7_rflmap; /* Receive failure reason bitmap */ __struct {N unsigned lsb$v_rfl_bce : 1; /* Block Check error */N unsigned lsb$v_rfl_fme : 1; /* Framing error */N unsigned lsb$v_rfl_ftl : 1; /* Frame too long */N unsigned lsb$v_rfl_rse : 1; /* Frame status error */N unsigned lsb$v_rfl_rle : 1; /* Frame length error */( unsigned lsb$v_fill_48_ 7: 3; } lsb$r_fill_27_; } lsb$r_fill_26_;N unsigned short int lsb$w_ufdctr; /* No protocol type counter */N unsigned short int lsb$w_ovrctr; /* Data overrun */N unsigned short int lsb$w_sbuctr; /* System buffer unavailable */N unsigned short int lsb$w_ubuctr; /* No buffer available on all PTs */N unsigned int lsb$l_mbsctr; /* Multicast messages sent */N unsigned int lsb$l_msnctr; 7/* Multicast bytes sent */N/* Phase IV FDDI counters */N unsigned int lsb$l_mfcctr; /* MAC frame count */N unsigned int lsb$l_mecctr; /* MAC error count */N unsigned int lsb$l_mlcctr; /* MAC lost count */N unsigned int lsb$l_riictr; /* Ring initializations initiated */N unsigned int lsb$l_rirctr; /* Ring initializations re7ceived */N unsigned int lsb$l_rbictr; /* Ring beacons initiated */N unsigned int lsb$l_datctr; /* Duplicate address test failures */N unsigned int lsb$l_dtdctr; /* Duplicate tokens detected */N unsigned int lsb$l_rprctr; /* Ring purge errors */N unsigned int lsb$l_fcictr; /* FCI strip errors */N unsigned int lsb$l_trictr; /* Traces initiated */N unsigned7 int lsb$l_trrctr; /* Traces received */N unsigned int lsb$l_dbcctr; /* Directed beacons received */N unsigned int lsb$l_ebectr; /* Elasticity buffer error */N unsigned int lsb$l_lctctr; /* LCT rejects */N unsigned int lsb$l_lemctr; /* LEM rejects */N unsigned int lsb$l_lnkctr; /* Link errors */N unsigned int lsb$l_cncctr; 7 /* Connections completed */N/* Phase IV Token Ring Counters */N unsigned int lsb$l_sfrctr; /* Send Failures */ __union {$ unsigned int lsb$l_trsflmap; __struct {N unsigned lsb$v_trsfl_tur : 1; /* Transmit Underrun */N unsigned lsb$v_trsfl_le : 1; /* Line Error */N unsigned lsb$v_trsfl_abs : 1; /* Abort Delimiter Sent 7 */N unsigned lsb$v_trsfl_lf : 1; /* Lost Frame */N unsigned lsb$v_trsfl_te : 1; /* Token Error */N unsigned lsb$v_trsfl_uf : 1; /* Unrecognized Frame */N unsigned lsb$v_trsfl_rc : 1; /* Remote Congestion */( unsigned lsb$v_fill_49_ : 1; } lsb$r_fill_29_; } lsb$r_fill_28_;N unsigned int lsb$l_rfrctr; /* Receive Failures 7 */ __union {$ unsigned int lsb$l_trrflmap; __struct {N unsigned lsb$v_trrfl_rc : 1; /* Receiver Congested */N unsigned lsb$v_trrfl_fce : 1; /* Frame Copied Error */( unsigned lsb$v_fill_50_ : 6; } lsb$r_fill_31_; } lsb$r_fill_30_;N unsigned int lsb$l_ifrctr; /* Insertion Failures */ __union {$ unsigned int lsb$l_triflmap; __struct {N 7 unsigned lsb$v_trifl_lwf : 1; /* Lobe Wire Fault */N unsigned lsb$v_trifl_sle : 1; /* Signal Loss Error */N unsigned lsb$v_trifl_tmo : 1; /* Timeout */N unsigned lsb$v_trifl_rpt : 1; /* Ring Purge Timeout */N unsigned lsb$v_trifl_bcn : 1; /* Beaconing */N unsigned lsb$v_trifl_dad : 1; /* Duplicate Address Detected */N unsigned lsb$v_tri 7fl_psf : 1; /* Parameter Server Failure */N unsigned lsb$v_trifl_rr : 1; /* Remove Received */ } lsb$r_fill_33_; } lsb$r_fill_32_;N unsigned int lsb$l_rgfctr; /* Ring Failures ('R' already used) */ __union {$ unsigned int lsb$l_trtflmap; __struct {N unsigned lsb$v_trtfl_lwf : 1; /* Lobe Wire Fault */N unsigned lsb$v_trtfl_ssd : 1; /* Single Station Detected */N 7 unsigned lsb$v_trtfl_arf : 1; /* Auto Removal Failure */N unsigned lsb$v_trtfl_rr : 1; /* Remove Received */( unsigned lsb$v_fill_51_ : 4; } lsb$r_fill_35_; } lsb$r_fill_34_;N unsigned int lsb$l_rpgctr; /* Ring Purges */N unsigned int lsb$l_mncctr; /* Monitor Conention */N unsigned int lsb$l_bcnctr; /* Beaconing Conditions */N 7unsigned int lsb$l_lerctr; /* Line Errors */N unsigned int lsb$l_ierctr; /* Internal Errors */N unsigned int lsb$l_berctr; /* Burst Errors */N unsigned int lsb$l_raectr; /* Ring Poll AC errors */N unsigned int lsb$l_adsctr; /* Abort Delimiters sent */N unsigned int lsb$l_piectr; /* Private Isolating Errors */N unsigned int lsb$l_tlfctr;7 /* Transmit Lost Frames */N unsigned int lsb$l_rcectr; /* Receiver Congestion Errors */N unsigned int lsb$l_fcectr; /* Frame Copied Errors */N unsigned int lsb$l_ferctr; /* Frequency Errors */N unsigned int lsb$l_terctr; /* Token Errors */N unsigned int lsb$l_pnectr; /* Private Non-Isolating Errors */N/* Miscellaneous counters returned in QIO 7 */N unsigned short int lsb$w_cdcctr; /* Transmit collision check failure */N short int lsb$w_extra_w_1; /* Preserve longword alignment */N/* Miscellaneous internal counters */N unsigned int lsb$l_chlmsg; /* Number of Channel Loopbacks sent */Q unsigned int lsb$l_chlerr; /* Number of Channel Loopback failures */N unsigned int lsb$l_sidmsg; /* Number of System IDs sent */7N unsigned int lsb$l_siderr; /* Number of System ID failures */Q unsigned int lsb$l_rqcmsg; /* Number of Request Counters msg sent */Q unsigned int lsb$l_rqcerr; /* Number of Request Counters msg fail */N unsigned int lsb$l_ravctr; /* Number of ring avail transitions */P unsigned int lsb$l_rnactr; /* Number of ring unavail transitions */ __union {N unsigned int lsb$l_char; /* Device characteristics word */7 __struct {N unsigned lsb$v_devctr : 1; /* When set, the device maintains */N/* some of the counters */Q unsigned lsb$v_devxidtest : 1; /* When set, the device responds to */N/* XID/TEST directed to the NULL or */N/* SNAP SAP */N unsigned lsb$v_mulseg : 1; /* When set, the device allows */7N/* multiple chain segments per transmit */O unsigned lsb$v_rcvmgt : 1; /* When set, the driver does its own */N/* buffer management for receive */N unsigned lsb$v_vlan : 1; /* Device is VLAN capable */N unsigned lsb$v_virtual : 1; /* Device is virtual */N unsigned lsb$v_linkvalid : 1; /* Link state is valid */W unsigned l7sb$v_autovalid : 1; /* Auto-negotiation enable status is valid */T unsigned lsb$v_jumbovalid : 1; /* Jumbo frames enable status is valid */N unsigned lsb$v_tso : 1; /* Hw can do IP/IPV6 TSO */N unsigned lsb$v_lro : 1; /* Hw can do IP/IPV6 LRO */N unsigned lsb$v_ip_csum : 1; /* Hw can do CKO ip/tcp-udp */N unsigned lsb$v_ipv6_csum : 1; /* Hw can do CKO ipv6/tcp-udp */N unsigned lsb$v_sctp_ 7csum : 1; /* Hw can do CKO SCTP */O unsigned lsb$v_ip_rxcsum : 1; /* Hw can do CKO on receive frames */N unsigned lsb$v_txmbuf : 1; /* Driver can handle BSD TX mbufs */ } lsb$r_fill_37_; } lsb$r_fill_36_; __union {N unsigned int lsb$l_sts; /* Driver status */ __struct {N unsigned lsb$v_run : 1; /* Device is running */N unsigned lsb$v_inited : 1;7 /* Initialization has begun in LAN */N unsigned lsb$v_mca_ovf : 1; /* The LSB multicast table has */N/* overflowed, so enable software */N/* filtering */N unsigned lsb$v_fat_err : 1; /* When set, we are in the LAN */N/* cleanup routine for fatal errors */O unsigned lsb$v_blkctl : 1; /* When set, we are bloc7king control */N/* requests */N unsigned lsb$v_pchact : 1; /* When set, we are in the */N/* PROCESS_CTLHLD routine */P unsigned lsb$v_need_dat_lock : 1; /* When set, we are waiting for */N/* another LSB to complete its DAT */N/* so we can start ours */S 7 unsigned lsb$v_got_dat_lock : 1; /* When set, we are holding the DAT */N/* LOCK because we are doing a DAT */P unsigned lsb$v_ring_avail : 1; /* When set, the ring is available */N/* indicating that PORT USABLE events */N/* should be reported to all VCI users */N/* who start successfully */R unsigned lsb7$v_full_duplex : 1; /* When set, the adapter is in full */N/* duplex mode */] unsigned lsb$v_hot_replace_drvr : 1; /* When set, the driver is being replaced */^ unsigned lsb$v_hot_replace_adap : 1; /* When set, the adapter is being replaced */g unsigned lsb$v_fp_cpuaff : 1; /* When set, adapter is fast path enabled for CPU affinity */N unsigned lsb$v_auto_ena : 1; /* Auto-negotiation is enab 7led */N unsigned lsb$v_jumbo_ena : 1; /* Jumbo frames are enabled */N unsigned lsb$v_sts_filler : 17; /* force longword */ } lsb$r_fill_39_; } lsb$r_fill_38_;N unsigned int lsb$l_mlt; /* Multicast (all) address state */N unsigned int lsb$l_prm; /* Promiscuous mode */N unsigned int lsb$l_prmuser; /* Promiscuous user's UCB address */N unsigned int lsb$l_media; 7 /* Media selection */N unsigned int lsb$l_speed; /* Line speed in megabits/sec */N unsigned int lsb$l_jumbo; /* Jumbo frame mode flag */N unsigned int lsb$l_autoneg; /* Auto-negotiation mode flag */N unsigned int lsb$l_flowcnt; /* Flow control mode flag */N/* Start of the parameters that must match for all users. */N unsigned int lsb$l_con; /* Controller mode 7 */N unsigned int lsb$l_ilp; /* Internal loopback mode */N unsigned int lsb$l_crc; /* CRC generation mode */N int lsb$l_extra_l_3; /* Preserve quadword alignment */U unsigned short int lsb$g_pha [4]; /* User defined physical address (6 bytes) */N unsigned short int lsb$g_hwa [4]; /* Hardware address (6 bytes) */[ unsigned short int lsb$g_nmpha [4]; /* Network management assigned address7 (6 bytes) */X unsigned int lsb$l_line_param; /* Address of line parameter validation table */[ unsigned int lsb$l_circuit_param; /* Address of circuit parameter validation table */N/* Miscellaneous */N unsigned int lsb$l_untcnt; /* Number of active units (UCB's) */Z unsigned int lsb$l_gen_multi; /* Address of a driver specific multicast table */b unsigned int lsb$l_mca_max; /* Maximum num 7ber of entries allowed in multicast table */^ unsigned int lsb$l_mca_cur; /* Number of entries enabled in the multicast table */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 lsb$g_mca_table [512]; /* Multicast Table */#pragma __nomember_alignmentN unsigned int lsb$l_dev_opr; /* Current device operat7ional state */N unsigned int lsb$l_fdx_ena; /* Full Duplex Enable */N unsigned int lsb$l_fdx_opr; /* Full Duplex Operational */P unsigned int lsb$l_maxfsz; /* Maximum Frame Size (excluding CRC) */N unsigned int lsb$l_qos; /* Quality of Service specifier */N/* Driver entry points */Z unsigned int lsb$l_reg_hwa; /* Address of Register Hardware Address Routine 7*/O unsigned int lsb$l_valid_cnm; /* Address of CNM validation routine */O unsigned int lsb$l_valid_fmt; /* Address of FMT validation routine */O unsigned int lsb$l_valid_gsp; /* Address of GSP validation routine */O unsigned int lsb$l_valid_mca; /* Address of MCA validation routine */O unsigned int lsb$l_valid_src; /* Address of SRC validation routine */O unsigned int lsb$l_valid_pha; /* Address of PHA validation routine */O unsign7ed int lsb$l_valid_pid; /* Address of PID validation routine */O unsigned int lsb$l_valid_prm; /* Address of PRM validation routine */O unsigned int lsb$l_valid_pty; /* Address of PTY validation routine */O unsigned int lsb$l_valid_sap; /* Address of SAP validation routine */N unsigned int lsb$l_set_cnm; /* Address of CNM set routine */N unsigned int lsb$l_set_des; /* Address of DES set routine */N unsigned int lsb$l_set_m7ca; /* Address of MCA set routine */N unsigned int lsb$l_set_src; /* Address of SRC set routine */N unsigned int lsb$l_set_pha; /* Address of PHA set routine */P unsigned int lsb$l_set_mnr; /* Address of set min receive routine */P unsigned int lsb$l_set_mxr; /* Address of set max receive routine */Y unsigned int lsb$l_set_80ns; /* Address of driver's set 80 ns timer routine */f unsigned int lsb$l_set_rtto; 7 /* Address of driver's set Restricted Token Timeout Routine */Z unsigned int lsb$l_sho_80ns; /* Address of driver's show 80 ns timer routine */g unsigned int lsb$l_sho_rtto; /* Address of driver's show Restricted Token Timeout Routine */O unsigned int lsb$l_sysid_msg; /* Address of driver's SYSID message */V unsigned int lsb$l_dev_timer; /* Address of device specific timer routine */O unsigned int lsb$l_process_ctl; /* Address of PROCESS_CTLHLD rou7tine */Y unsigned int lsb$l_dev_transmit; /* Address of device specific transmit routine */W unsigned int lsb$l_sho_lnk; /* Address of dev specific Show Link routine */N void (*lsb$a_fork_proc)(); /* Address of dev FORK-PROC routine */N void (*lsb$a_chngpro)(); /* Address of dev$ CHNGPRO routine */N void (*lsb$a_counter)(); /* Address of dev$ COUNTER routine */N void (*lsb$a_diag)(); /* Address of dev$ DIAG routine 7 */N void (*lsb$a_init)(); /* Address of dev$ INIT routine */N void (*lsb$a_port)(); /* Address of dev$ PORT routine */P void (*lsb$a_power_fail)(); /* Address of dev$ POWER_FAIL routine */N void (*lsb$a_receive)(); /* Address of dev$ RECEIVE routine */O void (*lsb$a_sense_mac)(); /* Address of dev$ SENSE_MAC routine */N void (*lsb$a_set_mac)(); /* Address of dev$ SET_MAC routine */N void (*lsb$a7_stop)(); /* Address of dev$ STOP routine */N void (*lsb$a_stoppro)(); /* Address of dev$ STOPPRO routine */N void (*lsb$a_strtpro)(); /* Address of dev$ STRTPRO routine */P void (*lsb$a_strtpropha)(); /* Address of dev$ STRTPROPHA routine */N void (*lsb$a_timer)(); /* Address of dev$ TIMER routine */N int (*lsb$a_transmit)(); /* Address of dev$ TRANSMIT routine */O void (*lsb$a_unit_init)(); 7/* Address of dev$ UNIT_INIT routine */N void (*lsb$a_mask)(); /* Address of dev$ MASK routine */ __union {N void *lsb$a_elan_lsbs; /* linked list of ELAN LSBs */N void *lsb$a_port_lsbs; /* linked list of Ports LSBs */N void *lsb$a_clip_lsbs; /* linked list of CLIP LSBs */ } lsb$r_lsb_ptr_overlay;N/* The following fields are used by LAN to find the Driver's internal */N/* counter are7a and internal counter area size. This is to allow the */N/* LAN module ACCESS FDT routine to return the Driver internal counters. */N unsigned int lsb$l_internal_ctrs; /* Address of internal counter area */N unsigned int lsb$l_internal_ctrsize; /* Size of internal counter area */N unsigned int lsb$l_internal_ctrstr; /* Address of counter ASCIZ strings */N/* Filtering Fields */Q/* MON is set/cleared upon monitor user 7startup/stop or device initialization. */U/* PRM is set/cleared upon promiscuous user startup/stop or device initialization. */N/* MONPRM is the OR of MON and PRM which is done after each user startup, */N/* change, stop or device initialization. */P/* These fields maintain the same state as other device parameters, ie. 'set' */N/* or 'on' is NMA$C_STATE_ON and 'cleared' or 'off' is NMA$C_STATE_OFF. */N unsigned int lsb$l_mon; /* Monitor u7ser flag (0 if exists) */Q unsigned int lsb$l_monprm; /* Monitor or prom user flag (0 if so) */N void *lsb$a_mon_user1; /* Address of monitoring routine 1 */N void *lsb$a_mon_user2; /* Address of monitoring routine 2 */N int lsb$l_extra_l_4; /* Preserve quadword alignment */N/* This is used during 802 filtered to record whether we have already */N/* taken care of the promiscuous user (since we can deliver multiple 7 */N/* copies due to GSAPs). Also, to indicate whether we have actually */N/* delivered a copy of the packet yet (to detect true 'no user'). */N unsigned int lsb$l_prm_done; /* Promiscuous user done */N unsigned int lsb$l_delivered; /* Packet was delivered to a user */N unsigned int lsb$l_next_802; /* Next 'real' 802 user */W unsigned int lsb$l_rsp_802; /* Response (XID/TEST) needed for this frame */N/* These a7re set to -1 during initialization and when a user is stopped, */O/* changed or started. Thereafter, the LAST field records the last protocol */P/* value and the UCB records the user who owned that value (zero if not owned */N/* by anyone). */O unsigned int lsb$l_pty_ucb; /* UCB for 'last' protocol type seen */N unsigned int lsb$l_pty_last; /* Last protocol type seen */N unsigned int lsb$l_sap_ucb7; /* UCB for 'last' SAP seen */N unsigned int lsb$l_sap_last; /* Last SAP seen */N unsigned int lsb$l_pid_ucb; /* UCB for 'last' PID seen */N unsigned __int64 lsb$q_pid_last; /* Last PID seen */N/* Mailbox area. This area consists of a count of the number of mailboxes */N/* in use, the physical base address of the CSRs for the device, the CRAM */N/* command opcode for a read and a write, followed by a 7list of mailbox */N/* addresses (each one pointing to a 64-byte mailbox CRAM). For drivers */N/* that need both mailbox and CSR support in the same image, the MBX_ENABLE */N/* flag is used to indicate that mailbox operation is enabled. */N __int64 lsb$q_mbx_base; /* Physical address of CSR base */O unsigned int lsb$l_mbx_read; /* CRAM command opcode for a lw read */P unsigned int lsb$l_mbx_write; /* CRAM command opcode for a lw write */7N unsigned int lsb$l_mbx_num; /* Number of mailboxes in use */N unsigned int lsb$l_mbx_enable; /* LBC if mbx operation is enabled */& unsigned int lsb$g_mbx_array [12];N/* Port driver's spinlock and timer queue element. */O void *lsb$a_portlock; /* Address of LAN's port driver lock */N void *lsb$a_portlock_orig; /* Address of original port lock */ char lsb$t_tqe [64];N/* TQE for the one second timer 7 */N/* Logical LAN driver fields. */N/* The LSB$C_LLAN_FSET_MAX must be the same size as the maximum */N/* Failover set structure defined in LLAN_LANCP.H */N unsigned int lsb$l_llan_state; /* State of Logical LAN */N unsigned int lsb$l_llan_state_req; /* Requested state of Logical LAN */" char lsb$t_llan_failset [136];N unsigned int lsb$l_lla7n_set_failset; /* Logical LAN's set failset info. */O unsigned int lsb$l_llan_sho_failset; /* Logical LAN's show failset info. */N void *lsb$a_llan_lsb; /* Logical LAN's LSB address */N int lsb$l_priority; /* Priority (used for LAN Failover) */S unsigned short int lsb$w_nif_timeout; /* NIF timeout (used for LAN failover) */U unsigned short int lsb$w_nif_interval; /* NIF interval (used for LAN failover) */N char lsb$g_nif_node_name [64]; 7 /* Node name list for NIF settings */Q char lsb$g_nif_node_addr [64]; /* Node address list for NIF settings */N void *lsb$a_testmsg_rcv_addr; /* ll$rcv_test_msg routine address */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_point 7er_size __long /* And set ptr size default to 64-bit pointers */N struct _vlan *lsb$pq_vlan; /* Pointer to VLAN block */#else unsigned __int64 lsb$pq_vlan;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _vlan *lsb$pq_vlan_orig; /* Pointer to VLAN block */#else# unsigned __int64 lsb$pq_vlan_orig;#endif 7#pragma __nomember_alignmentN char lsb$t_vlandata [32]; /* VLAN set/show info */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif^ unsigned int (*lsb$a_service_rtn)(); /* Address of dev$service_rtn, generic entry point */N unsigned int lsb$l_first_rcv_tm; /* Timestamp - first frame received */ unsigned int lsb$l_vmtu;N 7struct _lsbdef *lsb$ps_udplsb; /* UDPDRIVER LSB */N/* Bandwidth fields. */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-b 7it pointers */ void *lsb$pq_bw_buffer;#else# unsigned __int64 lsb$pq_bw_buffer;#endifN/* Base of S2 buffer */#pragma __nomember_alignmentN unsigned int lsb$l_bw_length; /* Size of S2 buffer */s unsigned int lsb$l_bw_threshold; /* Threshold when to record interval (0-no compression, >n bytes needed) */R unsigned int lsb$l_bw_offset; /* Offset to current entry in S2 buffer */R unsigned i7nt lsb$l_bw_start_time; /* Time monitoring started (abstimtics) */N unsigned __int64 lsb$q_bw_xmt_pk; /* Xmt packets at start of interval */N unsigned __int64 lsb$q_bw_xmt_by; /* Xmt bytes at start of interval */N unsigned __int64 lsb$q_bw_rcv_pk; /* Rcv packets at start of interval */N unsigned __int64 lsb$q_bw_rcv_by; /* Rcv bytes at start of interval */N unsigned __int64 lsb$q_bw_last_time; /* Time of last entry */N/* Unrecognized unicast packet time 7and packet header */a unsigned int lsb$l_lstuidtim; /* Time of Last Unrecognized Unicast Destiation packet */ char lsb$g_uid_header [24];N/* Unrecognized multicast packet time and packet header */c unsigned int lsb$l_lstumdtim; /* Time of Last Unrecognized Multicast Destiation packet */ char lsb$g_umd_header [24];N/* These are spare fields for debugging */c#if !defined(__NOBASEALIGN_SUPPO 7RT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment( __int64 lsb$q_lan_qreserved [8];$ int lsb$l_lan_reserved [16]; } lsb$r_spare_u;P/* two drivers that have two modules that need a common section defined here. */P/* The two sections will be a union so that they are overlayed on top of each */N/* other. 7 */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {O/*************************************************************************** */N/* Define the CSMACD common section of the LSB. */O/*************************************************************************** */#pragma 7__nomember_alignment __struct {N unsigned int lsb$l_csmacd_elan_state_req; /* ELAN state request */ __union {N unsigned int lsb$l_csmacd_elan_state; /* ELAN state */ __struct {V unsigned lsb$v_csmacd_elan_active : 1; /* ELAN is joined/active */S unsigned lsb$v_csmacd_elan_start : 1; /* startup in progress */S unsigned lsb$v_csmacd_elan_shut : 1; /* shutdown in pr 7ogress */^ unsigned lsb$v_csmacd_elan_unavailable : 1; /* NIPG signalled elan down */0 unsigned lsb$v_fill_52_ : 4;% } lsb$r_fill_41_;! } lsb$r_fill_40_;N unsigned int lsb$l_csmacd_event_mask_req; /* Event mask request */N unsigned int lsb$l_csmacd_event_mask; /* Event mask */Q unsigned int lsb$l_csmacd_ext_sense_req; /* Extended sense request */N unsigned int lsb7$l_csmacd_ext_sense; /* Extended sense */N unsigned int lsb$l_csmacd_pvc_req; /* PVC request */N unsigned int lsb$l_csmacd_pvc; /* PVC identifer */N unsigned int lsb$l_csmacd_pvc_num; /* Number of PVC */N unsigned int lsb$l_csmacd_max_pktsize; /* MAX transmit size */N unsigned int lsb$l_csmacd_medium; /* LAN media type */N char lsb$t_csmacd_elan_name [64]; /* Name 7string */N char lsb$t_csmacd_elan_desc [64]; /* Desc string */N char lsb$t_csmacd_parent_dev [8]; /* Device name string */N __struct { /* LES_ADDR */Q unsigned char lsb$b_csmacd_les_prefix [13]; /* LES_ADDR prefix */N unsigned char lsb$b_csmacd_les_esi [6]; /* LES_ADDR esi */O unsigned char lsb$b_csmacd_les_sel [1]; /* LES_ADDR selector 7 */( } lsb$t_csmacd_les_addr;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *lsb$a_csmacd_lec_attr; /* Address of LEC attribute buffer */S unsigned int lsb$l_csmacd_lec_len; /* Length of LEC attribute buffer */O/*************************************************************************** */N/* Define the CSMACD com7mon section of the LSB for Classical IP (CLIP) */O/*************************************************************************** */N unsigned int lsb$l_csmacd_clip_state_req; /* CLIP state request */ __union {O unsigned int lsb$l_csmacd_clip_state; /* Classical IP state */ __struct {T unsigned lsb$v_csmacd_lis_active : 1; /* LIS is joined/active */R unsigned lsb$v_csmacd_lis_start : 1; /* Startu 7p in progress */R unsigned lsb$v_csmacd_lis_shut : 1; /* Shutdown in progress */\ unsigned lsb$v_csmacd_lis_unavailable : 1; /* NIPG signalled LIS down */0 unsigned lsb$v_fill_53_ : 4;% } lsb$r_fill_43_;! } lsb$r_fill_42_;P void *lsb$a_csmacd_clip_attr; /* Address of CLIP attribute buffer */U unsigned int lsb$l_csmacd_clip_len; /* Length of CLIP attribute buffer */Q un7signed int lsb$l_csmacd_clip_user_type; /* CLIP Client or Server */N __struct { /* LIS_ADDR */R unsigned char lsb$b_csmacd_clip_prefix [13]; /* LIS_ADDR prefix */N unsigned char lsb$b_csmacd_clip_esi [6]; /* LIS_ADDR esi */P unsigned char lsb$b_csmacd_clip_sel [1]; /* LIS_ADDR selector */0 } lsb$t_csmacd_clip_server_addr;N __struct { /* Client (our) ATM 7Address */Y unsigned char lsb$b_csmacd_clip_atm_prefix [13]; /* Client addr prefix */R unsigned char lsb$b_csmacd_clip_atm_esi [6]; /* Client addr esi */W unsigned char lsb$b_csmacd_clip_atm_sel [1]; /* Client addr selector */- } lsb$t_csmacd_clip_atm_addr;S unsigned char lsb$t_csmacd_clip_proto_addr [6]; /* Client IP Address */N char lsb$b_csmacd_clip_pad1 [2]; /* Pad to longword */X 7 unsigned char lsb$t_csmacd_clip_subnet_mask [6]; /* Client IP Subnet Mask */N char lsb$b_csmacd_clip_pad2 [2]; /* Pad to longword */N char lsb$t_csmacd_clip_name [64]; /* Name string */N void *lsb$g_clip_pvc; /* Driver's copy of PVC info */N unsigned int lsb$l_csmacd_get_pvc; /* Sense pvc state */N unsigned int lsb$l_csmacd_set_pvc; /* Address of set clip pvc */N unsigned i7nt lsb$l_csmacd_sho_pvc; /* Address of show clip pvc */N unsigned int lsb$l_reserved; /* For longword alignment */O/*************************************************************************** */N/* Define the CSMACD common section of the LSB for Fore Thought */O/*************************************************************************** */N void *lsb$a_csmacd_lecs_cfg_handle; /* LECS config handle */N void *lsb$a_csmacd_lec_cfg_handl 7e; /* LEC config handle */N void *lsb$a_csmacd_cbrock_handle; /* Context for ConfigCallback */N void *lsb$a_csmacd_elan_handle; /* ELAN handle */N void *lsb$a_csmacd_lec_iface_handle; /* LEC interface handle */1 unsigned int lsb$l_csmacd_reserved_1;1 unsigned int lsb$l_csmacd_reserved_2;1 unsigned int lsb$l_csmacd_reserved_3;1 unsigned int lsb$l_csmacd_reserved_4;1 unsigned i 7nt lsb$l_csmacd_reserved_5;1 unsigned int lsb$l_csmacd_reserved_6;N void *lsb$a_csmacd_clip_handle; /* CLIP handle */N void *lsb$a_csmacd_clip_cfg_handle; /* CLIP config handle */N void *lsb$a_csmacd_clip_iface_handle; /* CLIP interface handle */1 unsigned int lsb$l_csmacd_reserved_7;1 unsigned int lsb$l_csmacd_reserved_8;1 unsigned int lsb$l_csmacd_reserved_9;2 unsigned int lsb 7$l_csmacd_reserved_10;2 unsigned int lsb$l_csmacd_reserved_11;2 unsigned int lsb$l_csmacd_reserved_12; } lsb$t_csmacd;O/*************************************************************************** */N/* Define the FDDI common section of the LSB. */O/*************************************************************************** */ __struct {N unsigned int lsb$l_fddi_dlver; /* Data Link Arch version */N 7 unsigned int lsb$l_fddi_t_max; /* Max token rotation time */N unsigned int lsb$l_fddi_t_neg; /* Negotiated TRT */N unsigned int lsb$l_fddi_t_req; /* Requested TRT */N unsigned int lsb$l_fddi_tvx; /* Valid transmission time */N unsigned int lsb$l_fddi_rtto; /* Restricted Token Timeout */N unsigned int lsb$l_fddi_rpe; /* Ring Purger Enable */N unsigned int lsb7$l_fddi_lem; /* LEM threshold */N unsigned int lsb$l_fddi_rer; /* Ring Error Reason */N unsigned int lsb$l_fddi_rjr; /* Reject Reason */N unsigned int lsb$l_fddi_lee; /* Link Error Estimate */N unsigned int lsb$l_fddi_una_dat; /* Upstream Neighbor DAT flag */2 unsigned short int lsb$g_fddi_una [4];N/* Upstream neighbor address */6 7 unsigned short int lsb$g_fddi_old_una [4];N/* Old Upstream neighbor address */< unsigned short int lsb$g_fddi_sif_conf_targ [4];N/* SIF Configuration Target */: unsigned short int lsb$g_fddi_sif_op_targ [4];N/* SIF Operational Target */7 unsigned short int lsb$g_fddi_nif_targ [4];N/* NIF Target 7 */8 unsigned short int lsb$g_fddi_echo_targ [4];N/* ECHO Target */2 unsigned short int lsb$g_fddi_dna [4];N/* Downstream neighbor address */6 unsigned short int lsb$g_fddi_old_dna [4];N/* Old Downstream neighbor addr. */R unsigned int lsb$l_fddi_echo_dat; /* ECH7O data, low byte valid only */N unsigned int lsb$l_fddi_echo_len; /* ECHO (data) packet length */N unsigned int lsb$l_fddi_phy_state; /* PHY state */N unsigned int lsb$l_fddi_link_state; /* Link state */N unsigned int lsb$l_fddi_rp_state; /* Ring Purger state */N unsigned int lsb$l_fddi_port_type; /* Port type (SAS=0) */N unsigned int lsb$l_fddi_nbr_phy; /* Neighbor PHY PORT type 7 */N unsigned int lsb$l_fddi_dat; /* DAT results */ __union {. unsigned int lsb$l_fddi_flags; __struct {N unsigned lsb$v_fddi_boo : 1; /* Boot enable */N unsigned lsb$v_fddi_cty : 1; /* Claim token yield */R unsigned lsb$v_fddi_unto : 1; /* Upstream Neighbor time out */0 unsigned lsb$v_fill_54_ : 5;% } ls 7b$r_fill_45_;! } lsb$r_fill_44_;N unsigned int lsb$l_fddi_smt; /* Address of SMT user's UCB */X unsigned int lsb$l_fddi_smt_prm; /* Address of promiscuous SMT user's UCB */N unsigned int lsb$l_fddi_smt_type; /* Station type */ } lsb$t_fddi;O/*************************************************************************** */N/* Define the Token Ring common section of the LSB. */O/************* 7************************************************************** */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __struct {#pragma __nomember_alignmentN unsigned int lsb$l_tr_speed; /* Ring Speed */N unsigned int lsb$l_tr_etr; /* Early Token release enabled */N unsigned int lsb$l_tr_mo 7ncon; /* Monitor Contender enabled */$ char lsb$b_fill_55_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 lsb$q_tr_naun; /* Nearest upstream neighbor */#pragma __nomember_alignmentN unsigned int lsb$l_tr_rer; /* Ring Error Reason */N unsigned int lsb$l_tr_ier; /* I7nsert Error Reason */N unsigned int lsb$l_tr_pdn; /* Physical Drop number */N unsigned int lsb$l_tr_rgn; /* Ring number */N unsigned int lsb$l_tr_maxac; /* Max AC for this station */N unsigned int lsb$l_tr_fcfield; /* Enabled FC mask for station */N unsigned int lsb$l_tr_srcatmo; /* Source Routing cache age tmr */N unsigned int lsb$l_tr_srdtmo; /* Source Routing discovery 7tmr */N unsigned int lsb$l_tr_sr; /* Source Routing enabled */N void *lsb$a_tr_sr_tab; /* Pointer to SR xlation table */N unsigned int lsb$l_tr_sr_size; /* Entries in SR table */N unsigned int lsb$l_tr_sr_tabsiz; /* Real entries in SR table */N unsigned int lsb$l_tr_sr_tabbyte; /* Byte size of SR table */N unsigned int lsb$l_tr_sr_inuse; /* SR Entries currently in use */O unsi7gned int lsb$l_tr_sr_garbage; /* Time till next garbage coll */N unsigned int lsb$l_tr_sr_deleted; /* Number of entries deleted */S unsigned __int64 lsb$q_tr_sr_xplorq; /* Que of pending Explore VCRPs */O unsigned int lsb$l_tr_sr_xplorb; /* Number of Explore VCRPs allo */N unsigned int lsb$l_tr_sr_xplorc; /* Count of Explore ops done */N void *lsb$a_tr_fca; /* Pointer to FCA xlation table */N unsigned int lsb$l_t7r_fca_used; /* Count of FCA entries in use */N unsigned int lsb$l_tr_fcmask; /* Current Func Addr mask */N void *lsb$a_tr_hdr; /* Pointer to header */N unsigned int lsb$l_tr_hdrsize; /* Size of header */N unsigned int lsb$l_tr_lnkstate; /* Link State */ } lsb$t_tr;O/*************************************************************************** */N/* Define the ATM common secti7on of the LSB. (None at this time.) */O/*************************************************************************** */ __struct {N void *lsb$a_atm_drv_cm_vc_setup; /* */N void *lsb$a_atm_drv_cm_vc_teardown; /* */N void *lsb$a_atm_drv_cm_vc_flush; /* Flush transmit path */R void *lsb$a_atm_drv_cm_tm_command; /* Traffic Manager callback rtn. */P void *lsb$a_atm_7drv_clip_xmt_done; /* CLIP Transmit complete rtn. */N void *lsb$a_atm_drv_clip_rcv; /* CLIP Receive rtn. */N void *lsb$a_atm_drv_handles; /* Pointer to Driver handles */N void *lsb$a_atm_usr_handles; /* Pointer to User handles */N void *lsb$a_atm_amm_handle; /* NIPG connection mgr AMM handle */N void *lsb$a_atm_addr_reg_handle; /* ADDR_REG handle adr */N void *lsb$a_atm_tm_an2_handle; /* NIPG T8raffic Mgr handle adr */N void *lsb$a_atm_clip_handle; /* NIPG Classical IP handle */N void *lsb$a_atm_lec_handle; /* NIPG LAN emulation handle */N void *lsb$a_atm_rcv_handle; /* NIPG rcv pool/buffer handle */N void *lsb$a_atm_xmt_handle; /* NIPG xmt pool/buffer handle */R unsigned int lsb$l_atm_tqe_alloc; /* Number of TQE allocations done */N unsigned int lsb$l_atm_tqe_used; /* Number of active TQEs 8 */U unsigned int lsb$l_atm_mem_alloc; /* Number of memory allocations done */Z unsigned int lsb$l_atm_mem_used; /* Number of bytes in "active" allocations */N unsigned int lsb$l_atm_hwanum; /* Number of HWA available */N unsigned int lsb$l_atm_hwanum_used; /* Mask of HWA used */N/* FORE common code */N void *lsb$a_atm_cd_handle; /* Card driver handle */N8 void *lsb$a_atm_cd_callbacks; /* Card driver's entry points */N void *lsb$a_atm_module_profilep; /* */N unsigned int lsb$l_atm_max_vc; /* Max # of VCs */N unsigned int lsb$l_atm_reserved_1; /* For longword alignment */N unsigned int lsb$l_atm_reserved_2; /* For longword alignment */N unsigned int lsb$l_atm_reserved_3; /* For longword alignment */N unsigned int l 8sb$l_atm_reserved_4; /* For longword alignment */N unsigned int lsb$l_atm_reserved_5; /* For longword alignment */ } lsb$t_atm; } lsb$r_medium_specific;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long8 /* And set ptr size default to 64-bit pointers */N void *lsb$pq_svapte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else$ unsigned __int64 lsb$pq_svapte_sva;#endif#pragma __nomember_alignment char lsb$b_fill_56_ [16]; } LSBDEF; #if !defined(__VAXC).#define lsb$l_flags lsb$r_fill_20_.lsb$l_flagsA#define lsb$v_created lsb$r_fill_20_.lsb$r_fill_21_.lsb$v_createdA#define lsb$v_enabled lsb$r_fill_20_.lsb$r_fill_21_.lsb$v_enabledC#define lsb$v_benabled lsb$r_f 8ill_20_.lsb$r_fill_21_.lsb$v_benabled=#define lsb$v_nmdis lsb$r_fill_20_.lsb$r_fill_21_.lsb$v_nmdis;#define lsb$v_elan lsb$r_fill_20_.lsb$r_fill_21_.lsb$v_elan;#define lsb$v_clip lsb$r_fill_20_.lsb$r_fill_21_.lsb$v_clip=#define lsb$v_timer lsb$r_fill_20_.lsb$r_fill_21_.lsb$v_timer;#define lsb$v_llan lsb$r_fill_20_.lsb$r_fill_21_.lsb$v_llanA#define lsb$v_faildev lsb$r_fill_20_.lsb$r_fill_21_.lsb$v_faildevG#define lsb$v_fast_timer lsb$r_fill_20_.lsb$r_fill_21_.lsb$v_fast_timerI#define ls8b$v_fail_nvalid lsb$r_fill_20_.lsb$r_fill_21_.lsb$v_fail_nvalid4#define lsb$l_nm_flags lsb$r_fill_22_.lsb$l_nm_flagsI#define lsb$v_nm_mac_addr lsb$r_fill_22_.lsb$r_fill_23_.lsb$v_nm_mac_addrH#define lsb$q_quad_ctrsect lsb$r_lsb_quad_ctr_overlay.lsb$q_quad_ctrsect<#define lsb$q_zerctr lsb$r_lsb_quad_ctr_overlay.lsb$q_zerctr0#define lsb$w_sflmap lsb$r_fill_24_.lsb$w_sflmapA#define lsb$v_sfl_exc lsb$r_fill_24_.lsb$r_fill_25_.lsb$v_sfl_excA#define lsb$v_sfl_ccf lsb$r_fill_24_.lsb$r_fill_25_.lsb$ 8v_sfl_ccfA#define lsb$v_sfl_shc lsb$r_fill_24_.lsb$r_fill_25_.lsb$v_sfl_shcA#define lsb$v_sfl_opc lsb$r_fill_24_.lsb$r_fill_25_.lsb$v_sfl_opcA#define lsb$v_sfl_ftl lsb$r_fill_24_.lsb$r_fill_25_.lsb$v_sfl_ftlA#define lsb$v_sfl_rfd lsb$r_fill_24_.lsb$r_fill_25_.lsb$v_sfl_rfdA#define lsb$v_sfl_tur lsb$r_fill_24_.lsb$r_fill_25_.lsb$v_sfl_turA#define lsb$v_sfl_tfl lsb$r_fill_24_.lsb$r_fill_25_.lsb$v_sfl_tfl0#define lsb$w_rflmap lsb$r_fill_26_.lsb$w_rflmapA#define lsb$v_rfl_bce lsb$r_fill_26_ 8.lsb$r_fill_27_.lsb$v_rfl_bceA#define lsb$v_rfl_fme lsb$r_fill_26_.lsb$r_fill_27_.lsb$v_rfl_fmeA#define lsb$v_rfl_ftl lsb$r_fill_26_.lsb$r_fill_27_.lsb$v_rfl_ftlA#define lsb$v_rfl_rse lsb$r_fill_26_.lsb$r_fill_27_.lsb$v_rfl_rseA#define lsb$v_rfl_rle lsb$r_fill_26_.lsb$r_fill_27_.lsb$v_rfl_rle4#define lsb$l_trsflmap lsb$r_fill_28_.lsb$l_trsflmapE#define lsb$v_trsfl_tur lsb$r_fill_28_.lsb$r_fill_29_.lsb$v_trsfl_turC#define lsb$v_trsfl_le lsb$r_fill_28_.lsb$r_fill_29_.lsb$v_trsfl_leE#defin 8e lsb$v_trsfl_abs lsb$r_fill_28_.lsb$r_fill_29_.lsb$v_trsfl_absC#define lsb$v_trsfl_lf lsb$r_fill_28_.lsb$r_fill_29_.lsb$v_trsfl_lfC#define lsb$v_trsfl_te lsb$r_fill_28_.lsb$r_fill_29_.lsb$v_trsfl_teC#define lsb$v_trsfl_uf lsb$r_fill_28_.lsb$r_fill_29_.lsb$v_trsfl_ufC#define lsb$v_trsfl_rc lsb$r_fill_28_.lsb$r_fill_29_.lsb$v_trsfl_rc4#define lsb$l_trrflmap lsb$r_fill_30_.lsb$l_trrflmapC#define lsb$v_trrfl_rc lsb$r_fill_30_.lsb$r_fill_31_.lsb$v_trrfl_rcE#define lsb$v_trrfl_fce lsb$r_fill_3 80_.lsb$r_fill_31_.lsb$v_trrfl_fce4#define lsb$l_triflmap lsb$r_fill_32_.lsb$l_triflmapE#define lsb$v_trifl_lwf lsb$r_fill_32_.lsb$r_fill_33_.lsb$v_trifl_lwfE#define lsb$v_trifl_sle lsb$r_fill_32_.lsb$r_fill_33_.lsb$v_trifl_sleE#define lsb$v_trifl_tmo lsb$r_fill_32_.lsb$r_fill_33_.lsb$v_trifl_tmoE#define lsb$v_trifl_rpt lsb$r_fill_32_.lsb$r_fill_33_.lsb$v_trifl_rptE#define lsb$v_trifl_bcn lsb$r_fill_32_.lsb$r_fill_33_.lsb$v_trifl_bcnE#define lsb$v_trifl_dad lsb$r_fill_32_.lsb$r_fill_33_.ls 8b$v_trifl_dadE#define lsb$v_trifl_psf lsb$r_fill_32_.lsb$r_fill_33_.lsb$v_trifl_psfC#define lsb$v_trifl_rr lsb$r_fill_32_.lsb$r_fill_33_.lsb$v_trifl_rr4#define lsb$l_trtflmap lsb$r_fill_34_.lsb$l_trtflmapE#define lsb$v_trtfl_lwf lsb$r_fill_34_.lsb$r_fill_35_.lsb$v_trtfl_lwfE#define lsb$v_trtfl_ssd lsb$r_fill_34_.lsb$r_fill_35_.lsb$v_trtfl_ssdE#define lsb$v_trtfl_arf lsb$r_fill_34_.lsb$r_fill_35_.lsb$v_trtfl_arfC#define lsb$v_trtfl_rr lsb$r_fill_34_.lsb$r_fill_35_.lsb$v_trtfl_rr,#define  8lsb$l_char lsb$r_fill_36_.lsb$l_char?#define lsb$v_devctr lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_devctrG#define lsb$v_devxidtest lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_devxidtest?#define lsb$v_mulseg lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_mulseg?#define lsb$v_rcvmgt lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_rcvmgt;#define lsb$v_vlan lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_vlanA#define lsb$v_virtual lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_virtualE#define lsb$v_linkvalid lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_linkva 8lidE#define lsb$v_autovalid lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_autovalidG#define lsb$v_jumbovalid lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_jumbovalid9#define lsb$v_tso lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_tso9#define lsb$v_lro lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_lroA#define lsb$v_ip_csum lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_ip_csumE#define lsb$v_ipv6_csum lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_ipv6_csumE#define lsb$v_sctp_csum lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_sctp_csumE#define lsb$v_ip_rxcsu 8m lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_ip_rxcsum?#define lsb$v_txmbuf lsb$r_fill_36_.lsb$r_fill_37_.lsb$v_txmbuf*#define lsb$l_sts lsb$r_fill_38_.lsb$l_sts9#define lsb$v_run lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_run?#define lsb$v_inited lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_initedA#define lsb$v_mca_ovf lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_mca_ovfA#define lsb$v_fat_err lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_fat_err?#define lsb$v_blkctl lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_blkctl?#define lsb$v_pcha8ct lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_pchactM#define lsb$v_need_dat_lock lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_need_dat_lockK#define lsb$v_got_dat_lock lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_got_dat_lockG#define lsb$v_ring_avail lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_ring_availI#define lsb$v_full_duplex lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_full_duplexS#define lsb$v_hot_replace_drvr lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_hot_replace_drvrS#define lsb$v_hot_replace_adap lsb$r_fill_38_.lsb$r_fill_39_.lsb 8$v_hot_replace_adapE#define lsb$v_fp_cpuaff lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_fp_cpuaffC#define lsb$v_auto_ena lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_auto_enaE#define lsb$v_jumbo_ena lsb$r_fill_38_.lsb$r_fill_39_.lsb$v_jumbo_ena=#define lsb$a_elan_lsbs lsb$r_lsb_ptr_overlay.lsb$a_elan_lsbs=#define lsb$a_port_lsbs lsb$r_lsb_ptr_overlay.lsb$a_port_lsbs=#define lsb$a_clip_lsbs lsb$r_lsb_ptr_overlay.lsb$a_clip_lsbs=#define lsb$q_lan_qreserved lsb$r_spare_u.lsb$q_lan_qreserved;#define lsb$l_8lan_reserved lsb$r_spare_u.lsb$l_lan_reserved7#define lsb$t_csmacd lsb$r_medium_specific.lsb$t_csmacdL#define lsb$l_csmacd_elan_state_req lsb$t_csmacd.lsb$l_csmacd_elan_state_reqS#define lsb$l_csmacd_elan_state lsb$t_csmacd.lsb$r_fill_40_.lsb$l_csmacd_elan_stated#define lsb$v_csmacd_elan_active lsb$t_csmacd.lsb$r_fill_40_.lsb$r_fill_41_.lsb$v_csmacd_elan_activeb#define lsb$v_csmacd_elan_start lsb$t_csmacd.lsb$r_fill_40_.lsb$r_fill_41_.lsb$v_csmacd_elan_start`#define lsb$v_csmacd_elan_shut lsb8$t_csmacd.lsb$r_fill_40_.lsb$r_fill_41_.lsb$v_csmacd_elan_shutn#define lsb$v_csmacd_elan_unavailable lsb$t_csmacd.lsb$r_fill_40_.lsb$r_fill_41_.lsb$v_csmacd_elan_unavailableL#define lsb$l_csmacd_event_mask_req lsb$t_csmacd.lsb$l_csmacd_event_mask_reqD#define lsb$l_csmacd_event_mask lsb$t_csmacd.lsb$l_csmacd_event_maskJ#define lsb$l_csmacd_ext_sense_req lsb$t_csmacd.lsb$l_csmacd_ext_sense_reqB#define lsb$l_csmacd_ext_sense lsb$t_csmacd.lsb$l_csmacd_ext_sense>#define lsb$l_csmacd_pvc_req lsb$t_csm 8acd.lsb$l_csmacd_pvc_req6#define lsb$l_csmacd_pvc lsb$t_csmacd.lsb$l_csmacd_pvc>#define lsb$l_csmacd_pvc_num lsb$t_csmacd.lsb$l_csmacd_pvc_numF#define lsb$l_csmacd_max_pktsize lsb$t_csmacd.lsb$l_csmacd_max_pktsize<#define lsb$l_csmacd_medium lsb$t_csmacd.lsb$l_csmacd_mediumB#define lsb$t_csmacd_elan_name lsb$t_csmacd.lsb$t_csmacd_elan_nameB#define lsb$t_csmacd_elan_desc lsb$t_csmacd.lsb$t_csmacd_elan_descD#define lsb$t_csmacd_parent_dev lsb$t_csmacd.lsb$t_csmacd_parent_dev@#define lsb$t_csmacd8_les_addr lsb$t_csmacd.lsb$t_csmacd_les_addrM#define lsb$b_csmacd_les_prefix lsb$t_csmacd_les_addr.lsb$b_csmacd_les_prefixG#define lsb$b_csmacd_les_esi lsb$t_csmacd_les_addr.lsb$b_csmacd_les_esiG#define lsb$b_csmacd_les_sel lsb$t_csmacd_les_addr.lsb$b_csmacd_les_sel@#define lsb$a_csmacd_lec_attr lsb$t_csmacd.lsb$a_csmacd_lec_attr>#define lsb$l_csmacd_lec_len lsb$t_csmacd.lsb$l_csmacd_lec_lenL#define lsb$l_csmacd_clip_state_req lsb$t_csmacd.lsb$l_csmacd_clip_state_reqS#define lsb$l_csmacd_cli8p_state lsb$t_csmacd.lsb$r_fill_42_.lsb$l_csmacd_clip_stateb#define lsb$v_csmacd_lis_active lsb$t_csmacd.lsb$r_fill_42_.lsb$r_fill_43_.lsb$v_csmacd_lis_active`#define lsb$v_csmacd_lis_start lsb$t_csmacd.lsb$r_fill_42_.lsb$r_fill_43_.lsb$v_csmacd_lis_start^#define lsb$v_csmacd_lis_shut lsb$t_csmacd.lsb$r_fill_42_.lsb$r_fill_43_.lsb$v_csmacd_lis_shutl#define lsb$v_csmacd_lis_unavailable lsb$t_csmacd.lsb$r_fill_42_.lsb$r_fill_43_.lsb$v_csmacd_lis_unavailableB#define lsb$a_csmacd_clip_attr lsb$t_csm8acd.lsb$a_csmacd_clip_attr@#define lsb$l_csmacd_clip_len lsb$t_csmacd.lsb$l_csmacd_clip_lenL#define lsb$l_csmacd_clip_user_type lsb$t_csmacd.lsb$l_csmacd_clip_user_typeP#define lsb$t_csmacd_clip_server_addr lsb$t_csmacd.lsb$t_csmacd_clip_server_addrW#define lsb$b_csmacd_clip_prefix lsb$t_csmacd_clip_server_addr.lsb$b_csmacd_clip_prefixQ#define lsb$b_csmacd_clip_esi lsb$t_csmacd_clip_server_addr.lsb$b_csmacd_clip_esiQ#define lsb$b_csmacd_clip_sel lsb$t_csmacd_clip_server_addr.lsb$b_csmacd_clip_8selJ#define lsb$t_csmacd_clip_atm_addr lsb$t_csmacd.lsb$t_csmacd_clip_atm_addr\#define lsb$b_csmacd_clip_atm_prefix lsb$t_csmacd_clip_atm_addr.lsb$b_csmacd_clip_atm_prefixV#define lsb$b_csmacd_clip_atm_esi lsb$t_csmacd_clip_atm_addr.lsb$b_csmacd_clip_atm_esiV#define lsb$b_csmacd_clip_atm_sel lsb$t_csmacd_clip_atm_addr.lsb$b_csmacd_clip_atm_selN#define lsb$t_csmacd_clip_proto_addr lsb$t_csmacd.lsb$t_csmacd_clip_proto_addrB#define lsb$b_csmacd_clip_pad1 lsb$t_csmacd.lsb$b_csmacd_clip_pad1P#defin8e lsb$t_csmacd_clip_subnet_mask lsb$t_csmacd.lsb$t_csmacd_clip_subnet_maskB#define lsb$b_csmacd_clip_pad2 lsb$t_csmacd.lsb$b_csmacd_clip_pad2B#define lsb$t_csmacd_clip_name lsb$t_csmacd.lsb$t_csmacd_clip_name2#define lsb$g_clip_pvc lsb$t_csmacd.lsb$g_clip_pvc>#define lsb$l_csmacd_get_pvc lsb$t_csmacd.lsb$l_csmacd_get_pvc>#define lsb$l_csmacd_set_pvc lsb$t_csmacd.lsb$l_csmacd_set_pvc>#define lsb$l_csmacd_sho_pvc lsb$t_csmacd.lsb$l_csmacd_sho_pvc2#define lsb$l_reserved lsb$t_csmacd.lsb$l_reserved8N#define lsb$a_csmacd_lecs_cfg_handle lsb$t_csmacd.lsb$a_csmacd_lecs_cfg_handleL#define lsb$a_csmacd_lec_cfg_handle lsb$t_csmacd.lsb$a_csmacd_lec_cfg_handleJ#define lsb$a_csmacd_cbrock_handle lsb$t_csmacd.lsb$a_csmacd_cbrock_handleF#define lsb$a_csmacd_elan_handle lsb$t_csmacd.lsb$a_csmacd_elan_handleP#define lsb$a_csmacd_lec_iface_handle lsb$t_csmacd.lsb$a_csmacd_lec_iface_handleD#define lsb$l_csmacd_reserved_1 lsb$t_csmacd.lsb$l_csmacd_reserved_1D#define lsb$l_csmacd_reserved_2 lsb$t_csmacd.l8sb$l_csmacd_reserved_2D#define lsb$l_csmacd_reserved_3 lsb$t_csmacd.lsb$l_csmacd_reserved_3D#define lsb$l_csmacd_reserved_4 lsb$t_csmacd.lsb$l_csmacd_reserved_4D#define lsb$l_csmacd_reserved_5 lsb$t_csmacd.lsb$l_csmacd_reserved_5D#define lsb$l_csmacd_reserved_6 lsb$t_csmacd.lsb$l_csmacd_reserved_6F#define lsb$a_csmacd_clip_handle lsb$t_csmacd.lsb$a_csmacd_clip_handleN#define lsb$a_csmacd_clip_cfg_handle lsb$t_csmacd.lsb$a_csmacd_clip_cfg_handleR#define lsb$a_csmacd_clip_iface_handle lsb$t_csmac8d.lsb$a_csmacd_clip_iface_handleD#define lsb$l_csmacd_reserved_7 lsb$t_csmacd.lsb$l_csmacd_reserved_7D#define lsb$l_csmacd_reserved_8 lsb$t_csmacd.lsb$l_csmacd_reserved_8D#define lsb$l_csmacd_reserved_9 lsb$t_csmacd.lsb$l_csmacd_reserved_9F#define lsb$l_csmacd_reserved_10 lsb$t_csmacd.lsb$l_csmacd_reserved_10F#define lsb$l_csmacd_reserved_11 lsb$t_csmacd.lsb$l_csmacd_reserved_11F#define lsb$l_csmacd_reserved_12 lsb$t_csmacd.lsb$l_csmacd_reserved_123#define lsb$t_fddi lsb$r_medium_specific.lsb$t 8_fddi4#define lsb$l_fddi_dlver lsb$t_fddi.lsb$l_fddi_dlver4#define lsb$l_fddi_t_max lsb$t_fddi.lsb$l_fddi_t_max4#define lsb$l_fddi_t_neg lsb$t_fddi.lsb$l_fddi_t_neg4#define lsb$l_fddi_t_req lsb$t_fddi.lsb$l_fddi_t_req0#define lsb$l_fddi_tvx lsb$t_fddi.lsb$l_fddi_tvx2#define lsb$l_fddi_rtto lsb$t_fddi.lsb$l_fddi_rtto0#define lsb$l_fddi_rpe lsb$t_fddi.lsb$l_fddi_rpe0#define lsb$l_fddi_lem lsb$t_fddi.lsb$l_fddi_lem0#define lsb$l_fddi_rer lsb$t_fddi.lsb$l_fddi_rer0#define lsb$l_fddi_rjr lsb$t_f 8ddi.lsb$l_fddi_rjr0#define lsb$l_fddi_lee lsb$t_fddi.lsb$l_fddi_lee8#define lsb$l_fddi_una_dat lsb$t_fddi.lsb$l_fddi_una_dat0#define lsb$g_fddi_una lsb$t_fddi.lsb$g_fddi_una8#define lsb$g_fddi_old_una lsb$t_fddi.lsb$g_fddi_old_unaD#define lsb$g_fddi_sif_conf_targ lsb$t_fddi.lsb$g_fddi_sif_conf_targ@#define lsb$g_fddi_sif_op_targ lsb$t_fddi.lsb$g_fddi_sif_op_targ:#define lsb$g_fddi_nif_targ lsb$t_fddi.lsb$g_fddi_nif_targ<#define lsb$g_fddi_echo_targ lsb$t_fddi.lsb$g_fddi_echo_targ0#define lsb$ 8g_fddi_dna lsb$t_fddi.lsb$g_fddi_dna8#define lsb$g_fddi_old_dna lsb$t_fddi.lsb$g_fddi_old_dna:#define lsb$l_fddi_echo_dat lsb$t_fddi.lsb$l_fddi_echo_dat:#define lsb$l_fddi_echo_len lsb$t_fddi.lsb$l_fddi_echo_len<#define lsb$l_fddi_phy_state lsb$t_fddi.lsb$l_fddi_phy_state>#define lsb$l_fddi_link_state lsb$t_fddi.lsb$l_fddi_link_state:#define lsb$l_fddi_rp_state lsb$t_fddi.lsb$l_fddi_rp_state<#define lsb$l_fddi_port_type lsb$t_fddi.lsb$l_fddi_port_type8#define lsb$l_fddi_nbr_phy lsb$t_fddi.lsb$ 8l_fddi_nbr_phy0#define lsb$l_fddi_dat lsb$t_fddi.lsb$l_fddi_datC#define lsb$l_fddi_flags lsb$t_fddi.lsb$r_fill_44_.lsb$l_fddi_flagsN#define lsb$v_fddi_boo lsb$t_fddi.lsb$r_fill_44_.lsb$r_fill_45_.lsb$v_fddi_booN#define lsb$v_fddi_cty lsb$t_fddi.lsb$r_fill_44_.lsb$r_fill_45_.lsb$v_fddi_ctyP#define lsb$v_fddi_unto lsb$t_fddi.lsb$r_fill_44_.lsb$r_fill_45_.lsb$v_fddi_unto0#define lsb$l_fddi_smt lsb$t_fddi.lsb$l_fddi_smt8#define lsb$l_fddi_smt_prm lsb$t_fddi.lsb$l_fddi_smt_prm:#define lsb$l_fddi_s 8mt_type lsb$t_fddi.lsb$l_fddi_smt_type/#define lsb$t_tr lsb$r_medium_specific.lsb$t_tr.#define lsb$l_tr_speed lsb$t_tr.lsb$l_tr_speed*#define lsb$l_tr_etr lsb$t_tr.lsb$l_tr_etr0#define lsb$l_tr_moncon lsb$t_tr.lsb$l_tr_moncon,#define lsb$q_tr_naun lsb$t_tr.lsb$q_tr_naun*#define lsb$l_tr_rer lsb$t_tr.lsb$l_tr_rer*#define lsb$l_tr_ier lsb$t_tr.lsb$l_tr_ier*#define lsb$l_tr_pdn lsb$t_tr.lsb$l_tr_pdn*#define lsb$l_tr_rgn lsb$t_tr.lsb$l_tr_rgn.#define lsb$l_tr_maxac lsb$t_tr.lsb$l_tr_maxac2#def !8ine lsb$l_tr_fcfield lsb$t_tr.lsb$l_tr_fcfield2#define lsb$l_tr_srcatmo lsb$t_tr.lsb$l_tr_srcatmo0#define lsb$l_tr_srdtmo lsb$t_tr.lsb$l_tr_srdtmo(#define lsb$l_tr_sr lsb$t_tr.lsb$l_tr_sr0#define lsb$a_tr_sr_tab lsb$t_tr.lsb$a_tr_sr_tab2#define lsb$l_tr_sr_size lsb$t_tr.lsb$l_tr_sr_size6#define lsb$l_tr_sr_tabsiz lsb$t_tr.lsb$l_tr_sr_tabsiz8#define lsb$l_tr_sr_tabbyte lsb$t_tr.lsb$l_tr_sr_tabbyte4#define lsb$l_tr_sr_inuse lsb$t_tr.lsb$l_tr_sr_inuse8#define lsb$l_tr_sr_garbage lsb$t_tr.lsb$l_t "8r_sr_garbage8#define lsb$l_tr_sr_deleted lsb$t_tr.lsb$l_tr_sr_deleted6#define lsb$q_tr_sr_xplorq lsb$t_tr.lsb$q_tr_sr_xplorq6#define lsb$l_tr_sr_xplorb lsb$t_tr.lsb$l_tr_sr_xplorb6#define lsb$l_tr_sr_xplorc lsb$t_tr.lsb$l_tr_sr_xplorc*#define lsb$a_tr_fca lsb$t_tr.lsb$a_tr_fca4#define lsb$l_tr_fca_used lsb$t_tr.lsb$l_tr_fca_used0#define lsb$l_tr_fcmask lsb$t_tr.lsb$l_tr_fcmask*#define lsb$a_tr_hdr lsb$t_tr.lsb$a_tr_hdr2#define lsb$l_tr_hdrsize lsb$t_tr.lsb$l_tr_hdrsize4#define lsb$l_tr_lnkst#8ate lsb$t_tr.lsb$l_tr_lnkstate1#define lsb$t_atm lsb$r_medium_specific.lsb$t_atmE#define lsb$a_atm_drv_cm_vc_setup lsb$t_atm.lsb$a_atm_drv_cm_vc_setupK#define lsb$a_atm_drv_cm_vc_teardown lsb$t_atm.lsb$a_atm_drv_cm_vc_teardownE#define lsb$a_atm_drv_cm_vc_flush lsb$t_atm.lsb$a_atm_drv_cm_vc_flushI#define lsb$a_atm_drv_cm_tm_command lsb$t_atm.lsb$a_atm_drv_cm_tm_commandI#define lsb$a_atm_drv_clip_xmt_done lsb$t_atm.lsb$a_atm_drv_clip_xmt_done?#define lsb$a_atm_drv_clip_rcv lsb$t_atm.lsb$a_a $8tm_drv_clip_rcv=#define lsb$a_atm_drv_handles lsb$t_atm.lsb$a_atm_drv_handles=#define lsb$a_atm_usr_handles lsb$t_atm.lsb$a_atm_usr_handles;#define lsb$a_atm_amm_handle lsb$t_atm.lsb$a_atm_amm_handleE#define lsb$a_atm_addr_reg_handle lsb$t_atm.lsb$a_atm_addr_reg_handleA#define lsb$a_atm_tm_an2_handle lsb$t_atm.lsb$a_atm_tm_an2_handle=#define lsb$a_atm_clip_handle lsb$t_atm.lsb$a_atm_clip_handle;#define lsb$a_atm_lec_handle lsb$t_atm.lsb$a_atm_lec_handle;#define lsb$a_atm_rcv_handle lsb %8$t_atm.lsb$a_atm_rcv_handle;#define lsb$a_atm_xmt_handle lsb$t_atm.lsb$a_atm_xmt_handle9#define lsb$l_atm_tqe_alloc lsb$t_atm.lsb$l_atm_tqe_alloc7#define lsb$l_atm_tqe_used lsb$t_atm.lsb$l_atm_tqe_used9#define lsb$l_atm_mem_alloc lsb$t_atm.lsb$l_atm_mem_alloc7#define lsb$l_atm_mem_used lsb$t_atm.lsb$l_atm_mem_used3#define lsb$l_atm_hwanum lsb$t_atm.lsb$l_atm_hwanum=#define lsb$l_atm_hwanum_used lsb$t_atm.lsb$l_atm_hwanum_used9#define lsb$a_atm_cd_handle lsb$t_atm.lsb$a_atm_cd_handle? &8#define lsb$a_atm_cd_callbacks lsb$t_atm.lsb$a_atm_cd_callbacksE#define lsb$a_atm_module_profilep lsb$t_atm.lsb$a_atm_module_profilep3#define lsb$l_atm_max_vc lsb$t_atm.lsb$l_atm_max_vc;#define lsb$l_atm_reserved_1 lsb$t_atm.lsb$l_atm_reserved_1;#define lsb$l_atm_reserved_2 lsb$t_atm.lsb$l_atm_reserved_2;#define lsb$l_atm_reserved_3 lsb$t_atm.lsb$l_atm_reserved_3;#define lsb$l_atm_reserved_4 lsb$t_atm.lsb$l_atm_reserved_4;#define lsb$l_atm_reserved_5 lsb$t_atm.lsb$l_atm_reserved_5"#end'8if /* #if !defined(__VAXC) */ P#define LSB$C_LSBDEF_LEN 8160 /* For compilation time size checking */N/* Source routing table entry */N#define SR$C_LOCAL 0 /* Node on local ring */N#define SR$C_UNKNOWN 2 /* Node is unknown (use STE) */N#define SR$C_KNOWN 4 /* Node has a known Route */N#define SR$C_STALE 1 /* Cached route info is stal (8e */N#define SR$C_DELETED 3 /* Entry is deleted */N#define SR$C_EXPLORING 5 /* Currently Exploring Route */N#define SR$C_SR_SIZE 64 /* Size of entry */N#define SR$C_SR_SHIFT 6 /* Bits to shift for SR_SIZE */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember )8_alignment#endiftypedef struct _sr {#pragma __nomember_alignmentN unsigned __int64 sr$g_addr; /* Mac Address (canonical) */N unsigned int sr$l_state; /* State of entry */N unsigned int sr$l_ri_s; /* Size of RI field */ unsigned char sr$g_ri [32];N/* RI field */N unsigned int sr$l_lstxmttim; /* Stale xmit timer */N*8 unsigned int sr$l_lstrcvtim; /* Stale recv timer */N unsigned int sr$l_staletim; /* Stale timer (time to delete) */N unsigned int sr$l_discvtim; /* Discovery timer */N/* State Values */ } SR;N/* Functional address translation table entry */N#define FCA$C_FCA_ENTRIES 200 /* Entries in table */N#define FCA$C_ +8FCA_SIZE 16 /* Size of entry */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fca {#pragma __nomember_alignmentN unsigned __int64 fca$g_addr; /* Multicast address (canonical) */N unsigned int fca$l_fc_mask; /* Functional Address Mask */N unsigned int fca$l_fc_fill; ,8 /* Filler to make QW aligned */ } FCA;N/* Trace entry */#define TRC$Q_PK_DATA 0#define TRC$G_PK_DATA 12N#define TRC$V_CPU_SHIFT 22 /* CurCPU is <31:22> (V2) */N#define TRC$V_DRV_SHIFT 18 /* DrvState is <21:18> (V2) */N#define TRC$V_TYP_SHIFT 12 /* Type is <17:12> (V2) */N#define TRC$V_LEN_SHIFT 0 /* EntryLen is <11:0> (V2) -8 */V#define TRC$M_CPU_MASK 1023 /* CurCPU is <31:22> 10 bits, 0..1024 (V2) */T#define TRC$M_DRV_MASK 15 /* DrvState is <21:18> 4 bits, 0..15 (V2) */T#define TRC$M_TYP_MASK 63 /* Type is <17:12> 6 bits, 0..63 (V2) */V#define TRC$M_LEN_MASK 4095 /* EntryLen is <11:0> 12 bits, 0..4095 (V2) */O#define TRC$C_INIT_ENTRIES 512 /* Number of init time trace entries */N#define TRC$C_DEF_ENTRIES 2048 /* Number of default trace ent.8ries */N#define TRC$C_NUM_INT 8 /* Number of interrupt entries */N#define TRC$C_LENGTH 32 /* Entry length */V/* Trace entries go from 1-32 for common types and 33-64 for driver specific types. */N#define TRC$C_EXTENSION 128 /* Entry extension */N/* Common trace entries, 1-32. */N#define TRC$C_INVALID 0 /* 0 0 Invalid entry */U#define /8TRC$C_TIMER 1 /* 1 1 00000001 One-second timer */N#define TRC$C_INTR 2 /* 2 2 00000002 Interrupt */Y#define TRC$C_FRK_START 3 /* 3 3 00000004 Fork process started */V#define TRC$C_FRK_DONE 4 /* 4 4 00000008 Fork process done */O#define TRC$C_FRK_ERROR 5 /* 5 5 00000010 Fork error */T#define TRC$C_FRK_SOFT 6 /* 6 6 00000020 Fork soft error */08Q#define TRC$C_STATE 7 /* 7 7 00000040 State change */W#define TRC$C_INIT 8 /* 8 8 00000080 First user startup */[#define TRC$C_CHNGPRO 9 /* 9 9 00000100 User start/change/stop */S#define TRC$C_STOP 10 /* 10 A 00000200 Last user stop */U#define TRC$C_SHUTDOWN 11 /* 11 B 00000400 Device shutdown */T#define TRC$C_RCV_ISS 12 /* 12 C 00000800 Receive issued */R#define TRC$C_RCV_DONE 13 /* 13 D 00001000 Receive done */S#define TRC$C_RCV_ERR 14 /* 14 E 00002000 Receive error */_#define TRC$C_RCV_PKT 15 /* 15 F 00004000 Receive packet (32 bytes) */c#define TRC$C_RCV_PKT1 16 /* 16 10 00008000 Receive packet (33..64 bytes) */c#define TRC$C_RCV_PKT2 17 /* 17 11 00010000 Receive packet (65..96 bytes) */f#define TR28C$C_RCV_PKT3 18 /* 18 12 00020000 Receive packet (complete packet) */U#define TRC$C_XMT_ISS 19 /* 19 13 00040000 Transmit issued */U#define TRC$C_XMT_QUE 20 /* 20 14 00080000 Transmit queued */S#define TRC$C_XMT_DONE 21 /* 21 15 00100000 Transmit done */T#define TRC$C_XMT_ERR 22 /* 22 16 00200000 Transmit error */`#define TRC$C_XMT_PKT 23 /* 23 17 00400000 Transmit packet (32 bytes) */d#define TRC$C_XMT_PKT1 24 /* 24 18 00800000 Transmit packet (33..64 bytes) */d#define TRC$C_XMT_PKT2 25 /* 25 19 01000000 Transmit packet (65..96 bytes) */g#define TRC$C_XMT_PKT3 26 /* 26 1A 02000000 Transmit packet (complete packet) */P#define TRC$C_VCI_ACTION 27 /* 27 1B 04000000 VCI action */P#define TRC$C_LAN_ACTION 28 /* 28 1C 08000000 LAN action */ 48O#define TRC$C_LAN_OTHER 29 /* 29 1D 10000000 LAN other */O#define TRC$C_RDL_ERROR 30 /* 30 1E 20000000 RDL error */U#define TRC$C_SEGMENT 31 /* 31 1F 40000000 Segment context */V#define TRC$C_BW_ACTION 32 /* 32 20 80000000 Bandwidth action */#define TRC$C_LAN32 32$#define TRC$M_ALL_COMMON -1132691457$#define TRC$M_DEF_COMMON -1675614224#define TRC$C_SIZE_STOP 0#define TRC$C_SIZE_PAUSE -1#defin 58e TRC$C_SIZE_NOCHANGE -2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _trc {#pragma __nomember_alignmentN unsigned __int64 trc$q_time; /* Trace entry RSCC timestamp */N unsigned int trc$l_sequence; /* Sequence number */ __union {r unsigned int trc$l_type_len; /* CPU, Driver S 68tate, Entry Type, Entry Length (in 32-byte chunks) (V2) */ __struct {N unsigned char trc$b_type; /* Entry type (V1) */R unsigned char trc$b_xmtcnt; /* Number of outstanding transmits (V1) */Q unsigned char trc$b_rcvcnt; /* Number of outstanding receives (V1) */P unsigned char trc$b_misc; /* Driver state <3:0>, CPU <7:4> (V1) */# } trc$r_type_len_bytes; } trc$r_type_len;N unsigned int trc$l_param 781; /* Parameter 1 */N unsigned int trc$l_param2; /* Parameter 2 */N unsigned int trc$l_param3; /* Parameter 3 */N unsigned int trc$l_param4; /* Parameter 4 */Q/* Type <7> is set if this entry is an extension entry (trace version 1 only). */ } TRC; #if !defined(__VAXC)4#define trc$l_type_len trc$r_type_len.trc$l_type_lenA#define trc$b_type trc$r_type_len.trc$ 88r_type_len_bytes.trc$b_typeE#define trc$b_xmtcnt trc$r_type_len.trc$r_type_len_bytes.trc$b_xmtcntE#define trc$b_rcvcnt trc$r_type_len.trc$r_type_len_bytes.trc$b_rcvcntA#define trc$b_misc trc$r_type_len.trc$r_type_len_bytes.trc$b_misc"#endif /* #if !defined(__VAXC) */    $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr98 size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __LSBDEF_LOADED */ ww0mx[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed:8 to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **;8/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:10 by OpenVMS SDL V3 <8.7 */E/* Source: 01-APR-2004 15:42:12 $1$DGA8345:[LIB_H.SRC]MADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MADEF ***/#ifndef __MADEF_LOADED#define __MADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragma=8s supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#end>8if#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Definitions for Memory Attributes */N/* */N#define MA$C_WBU 0 /* Write back, unordered */Z#define MA$C_UC 4 /* Non?8-coalescing, sequential & non-speculative */Y#define MA$C_UCE 5 /* Non-coalescing, sequential, non-speculative */N/* & fetchadd exported */U#define MA$C_WC 6 /* Non-cached, Coalescing, non-seq., spec. */N#define MA$C_NAT 7 /* NaT page */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporte@8d */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MADEF_LOADED */ wwPx[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard EnA8terprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., andB8 is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************* C8*******************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 19-MAY-1993 09:30:16 $1$DGA8345:[LIB_H.SRC]MBADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MBADEF ***/#ifndef __MBADEF_LOADED#define __MBADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __saveD8#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __stE8ruct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* MASSBUS ADAPTER REGISTER OFFSET DEFINITIONS */N/*- */#define MBA$M_CSR_OT 0x200F8000#define MBA$M_CSR_PU 0x400000#define MBA$M_CSR_PD 0x800000!#define MBA$M_CSR_XMFLT 0x4000000#define MBA$M_CSR_MT 0x8000000 #define MBA$M_CSR_URD 0x20000000#define MBA$M_CSR_WS 0x40000000#define MBA$M_CSR_PE 0x80000000#define MBA$M_CR_INIT 0x1#define MBA$M_CR_ABORT 0x2#define MBA$M_CR_IE 0x4#define MBA$M_SR_RDTO 0x1#define MBA$M_SR_ISTO 0x2#define MBA$M_SR_RDS 0x4#define MBA$M_SR_ERCONF 0x8#define MBA$M_SR_INVMAP 0x10#define MBA$M_SR_MAPPE 0x20#define MBA$G8M_SR_MDPE 0x40#define MBA$M_SR_MBEXC 0x80#define MBA$M_SR_MXF 0x100#define MBA$M_SR_WCKLWR 0x200#define MBA$M_SR_WCKUPR 0x400#define MBA$M_SR_DLT 0x800#define MBA$M_SR_DTABT 0x1000#define MBA$M_SR_DTCOMP 0x2000#define MBA$M_SR_SPE 0x4000#define MBA$M_SR_ATTN 0x10000#define MBA$M_SR_MCPE 0x20000#define MBA$M_SR_NED 0x40000#define MBA$M_SR_PGE 0x80000 #define MBA$M_SR_CBHUNG 0x800000#define MBA$M_SR_CRD 0x20000000"#define MBA$M_SR_NRCONF 0x40000000"#define MBA$M_SR_D H8TBUSY 0x80000000N#define MBA$M_ERROR 942079 /* PROGRAM ERROR */N#define MBA$S_MBADEF 3072 /* Old size name - synonym */ typedef struct _mba { __union {N unsigned int mba$l_csr; /*CONFIGURATION STATUS REGISTER */ __struct {N unsigned mba$v_csr_adcod : 8; /* ADAPTER CODE FIELD */N unsigned mbadef$$_fill_1 : 13; /* RESERVED BITS */N unsigned mI8ba$v_csr_ot : 1; /* OVER TEMPERATURE */N unsigned mba$v_csr_pu : 1; /* ADAPTER POWER UP */N unsigned mba$v_csr_pd : 1; /* ADAPTER POWER DOWN */N unsigned mbadef$$_fill_2 : 2; /* RESERVED BITS */N unsigned mba$v_csr_xmflt : 1; /* TRANSMITTER FAULT */N unsigned mba$v_csr_mt : 1; /* MULTIPLE TRANSMITTERS */N unsigned mbadef$$_fill_3 : 1; /* RES J8ERVED BIT */N unsigned mba$v_csr_urd : 1; /* UNEXPECTED READ DATA */N unsigned mba$v_csr_ws : 1; /* WRITE SEQUENCE DATA */N unsigned mba$v_csr_pe : 1; /* SBI PARITY ERROR */ } mba$r_csr_bits; } mba$r_csr_overlay; __union {N unsigned int mba$l_cr; /*CONTROL REGISTER */ __struct {N unsigned mba$v_cr_init : 1; /* ADAPTER INI K8TIALIZATION */N unsigned mba$v_cr_abort : 1; /* ABORT OPERATION */N unsigned mba$v_cr_ie : 1; /* INTERRUPT ENABLE */' unsigned mba$v_fill_0_ : 5; } mba$r_cr_bits; } mba$r_cr_overlay; __union {N unsigned int mba$l_sr; /*STATUS REGISTER */ __struct {N unsigned mba$v_sr_rdto : 1; /* READ DATA TIMEOUT */N unsignedL8 mba$v_sr_isto : 1; /* INTERFACE SEQUENCE TIMEOUT */N unsigned mba$v_sr_rds : 1; /* READ DATA SUBSTITUTE */N unsigned mba$v_sr_erconf : 1; /* ERROR CONFIRMATION */N unsigned mba$v_sr_invmap : 1; /* INVALID MAP REGISTER */N unsigned mba$v_sr_mappe : 1; /* MAP PARITY ERROR */N unsigned mba$v_sr_mdpe : 1; /* MASSBUS DATA PARITY ERROR */N unsigned mba$v_sr_mbexc : 1; /* MAM8SSBUS EXCEPTION */N unsigned mba$v_sr_mxf : 1; /* MISSED TRANSFER ERROR */N unsigned mba$v_sr_wcklwr : 1; /* WRITE CHECK ERROR LOWER BYTE */N unsigned mba$v_sr_wckupr : 1; /* WRITE CHECK ERROR UPPER BYTE */N unsigned mba$v_sr_dlt : 1; /* DATA LATE ERROR */N unsigned mba$v_sr_dtabt : 1; /* DATA TRANSFER ABORTED */N unsigned mba$v_sr_dtcomp : 1; /* DATA TRANSFER COMPLETE N8 */N unsigned mba$v_sr_spe : 1; /* SILO PARITY ERROR */N unsigned mbadef$$_fill_4 : 1; /* RESERVED BITS */N unsigned mba$v_sr_attn : 1; /* MASSBUS ATTENTION */N unsigned mba$v_sr_mcpe : 1; /* MASSBUS COMTROL PARITY ERROR */N unsigned mba$v_sr_ned : 1; /* NONEXISTENT DRIVE */N unsigned mba$v_sr_pge : 1; /* PROGRAM ERROR */N unsignO8ed mbadef$$_fill_5 : 3; /* RESERVED BITS */N unsigned mba$v_sr_cbhung : 1; /* CB HUNG */N unsigned mbadef$$_fill_6 : 5; /* RESERVED BITS */N unsigned mba$v_sr_crd : 1; /* CORRECTED READ DATA */N unsigned mba$v_sr_nrconf : 1; /* NO RESPONSE CONFIRMATION */N unsigned mba$v_sr_dtbusy : 1; /* DATA TRANSFER BUSY */ } mba$r_sr_bits;N/* ERROR BITS P8 */ } mba$r_sr_overlay;N void *mba$l_var; /*VIRTUAL ADDRESS REGISTER */N unsigned int mba$l_bcr; /*BYTE COUNT REGISTER */N unsigned int mba$l_dr; /*DIAGNOSTIC REGISTER */N unsigned int mba$l_selmr; /*SELECTED MAP REGISTER */N char mbadef$$_fill_7 [996]; /* VALUE IS 1024-<4*7> */ __unio Q8n {P void *mba$l_erb; /*BASE ADDRESS OF EXTERNAL REGISTERS */ __struct {N unsigned mbadef$$_fill_8 : 7; /* REGISTER OFFSET ADDRESS BITS */N unsigned mba$v_erb_unit : 3; /* DRIVE UNIT NUMBER */' unsigned mba$v_fill_1_ : 6; } mba$r_erb_bits; } mba$r_erb_overlay;N char mbadef$$_fill_9 [12]; /* DRIVE REGISTER ADDRESS SPACE */N unsigned int mba$l_as; /*ATTENTION R8SUMMARY REGISTER */N char mbadef$$_fill_10 [1004]; /* VALUE IS 2048-. */N/* TO POSITION TO 2048 */N unsigned int mba$l_map [256]; /*MAP REGISTERS */ } MBA; #if !defined(__VAXC)-#define mba$l_csr mba$r_csr_overlay.mba$l_csrH#define mba$v_csr_adcod mba$r_csr_overlay.mba$r_csr_bits.mba$v_csr_adcodB#define mba$v_csr_ot mba$r_csr_overlay.mba$r_csr_bits.mba$v_csr_otB#define mbS8a$v_csr_pu mba$r_csr_overlay.mba$r_csr_bits.mba$v_csr_puB#define mba$v_csr_pd mba$r_csr_overlay.mba$r_csr_bits.mba$v_csr_pdH#define mba$v_csr_xmflt mba$r_csr_overlay.mba$r_csr_bits.mba$v_csr_xmfltB#define mba$v_csr_mt mba$r_csr_overlay.mba$r_csr_bits.mba$v_csr_mtD#define mba$v_csr_urd mba$r_csr_overlay.mba$r_csr_bits.mba$v_csr_urdB#define mba$v_csr_ws mba$r_csr_overlay.mba$r_csr_bits.mba$v_csr_wsB#define mba$v_csr_pe mba$r_csr_overlay.mba$r_csr_bits.mba$v_csr_pe*#define mba$l_cr mba$r_cr_overla T8y.mba$l_crB#define mba$v_cr_init mba$r_cr_overlay.mba$r_cr_bits.mba$v_cr_initD#define mba$v_cr_abort mba$r_cr_overlay.mba$r_cr_bits.mba$v_cr_abort>#define mba$v_cr_ie mba$r_cr_overlay.mba$r_cr_bits.mba$v_cr_ie*#define mba$l_sr mba$r_sr_overlay.mba$l_srB#define mba$v_sr_rdto mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_rdtoB#define mba$v_sr_isto mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_isto@#define mba$v_sr_rds mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_rdsF#define mba$v_sr_erconf mba$r_sr_overlay.mba$rU8_sr_bits.mba$v_sr_erconfF#define mba$v_sr_invmap mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_invmapD#define mba$v_sr_mappe mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_mappeB#define mba$v_sr_mdpe mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_mdpeD#define mba$v_sr_mbexc mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_mbexc@#define mba$v_sr_mxf mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_mxfF#define mba$v_sr_wcklwr mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_wcklwrF#define mba$v_sr_wckupr mba$r_sr_overlay.mba$r_sr_bits.mba$v_s V8r_wckupr@#define mba$v_sr_dlt mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_dltD#define mba$v_sr_dtabt mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_dtabtF#define mba$v_sr_dtcomp mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_dtcomp@#define mba$v_sr_spe mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_speB#define mba$v_sr_attn mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_attnB#define mba$v_sr_mcpe mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_mcpe@#define mba$v_sr_ned mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_ned@#define mba$v_sr_pge W8 mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_pgeF#define mba$v_sr_cbhung mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_cbhung@#define mba$v_sr_crd mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_crdF#define mba$v_sr_nrconf mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_nrconfF#define mba$v_sr_dtbusy mba$r_sr_overlay.mba$r_sr_bits.mba$v_sr_dtbusy-#define mba$l_erb mba$r_erb_overlay.mba$l_erbF#define mba$v_erb_unit mba$r_erb_overlay.mba$r_erb_bits.mba$v_erb_unit"#endif /* #if !defined(__VAXC) */  $#pragma __membX8er_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MBADEF_LOADED */ wwp y[UM/***************************************************************************/M/** **/M/** HPE CONFY8IDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. TZ8his software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************************************** [8************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */G/* Source: 30-MAR-2006 11:53:41 $1$DGA8345:[LIB_H.SRC]MBOXDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MBOXDEF ***/#ifndef __MBOXDEF_LOADED#define __MBOXDEF_LOADED 1 G#p \8ragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __option]8al_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/*- */ ^8 N#define MBOX$K_MAX_MSGSIZE 65535 /* Maximum mailbox message size */N#define MBOX_MSG$K_LENGTH 56 /*LENGTH OF STRUCTURE */N#define MBOX_MSG$C_LENGTH 56 /*LENGTH OF STRUCTURE */ typedef struct _mbox_msg { __union {N int mbox_msg$ps_addr; /* Address of Data in packet */N int mbox_msg$l_flink; /* Message flink for queue write */# } mbox_msg$r_mbox1_overlay; __union {U_8 int mbox_msg$ps_uva32; /* Contains BUFIO$K_64 to for use of uva64 */N int mbox_msg$l_blink; /* Message blink for queued write */# } mbox_msg$r_mbox2_overlay;N unsigned short int mbox_msg$w_mbz; /* Must be Zero */N unsigned char mbox_msg$b_type; /* Block type DYN$C_MISC */N unsigned char mbox_msg$b_subtype; /* Block subtype DYN$C_MBX_MSG */N unsigned int mbox_msg$l_function; /* Function code `8 */N __int64 mbox_msg$pq_uva64; /* 64-bit Address of user buffer */N unsigned int mbox_msg$l_size; /* Block size */N int mbox_msg$l_irp; /* IRP */N int mbox_msg$l_noreaderwaitqfl; /* Queue to wait for */N int mbox_msg$l_noreaderwaitqbl; /* */T unsigned int mbox_msg$l_pid; /* PID (Will be zero for WRITE IO$M_NOWs) */Na8 int mbox_msg$l_datastart; /* Start of Data in packet */N unsigned short int mbox_msg$w_datasize; /* Data size */N unsigned short int mbox_msg$w_bufquocharge; /* BUFQUO charged */` unsigned int mbox_msg$l_thread_pid; /* Kernel thread EPID (will be 0 for WRITE IO$M_NOWs) */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomembb8er_alignment#endif#if defined(__VAXC) char mbox_msg$r_data[];#elseV/* Warning: empty char[] member for mbox_msg$r_data at end of structure not created */"#endif /* #if defined(__VAXC) */ } MBOX_MSG; #if !defined(__VAXC)B#define mbox_msg$ps_addr mbox_msg$r_mbox1_overlay.mbox_msg$ps_addrB#define mbox_msg$l_flink mbox_msg$r_mbox1_overlay.mbox_msg$l_flinkD#define mbox_msg$ps_uva32 mbox_msg$r_mbox2_overlay.mbox_msg$ps_uva32B#define mbox_msg$l_blink mbox_msg$r_mbox2_overlay. c8mbox_msg$l_blink"#endif /* #if !defined(__VAXC) */ N#define MBOX_BUF$K_LENGTH 40 /*LENGTH OF STRUCTURE */N#define MBOX_BUF$C_LENGTH 40 /*LENGTH OF STRUCTURE */ #pragma __nomember_alignmenttypedef struct _mbox_buf {N int mbox_buf$ps_addr; /* Address of Data in packet */U int mbox_buf$ps_uva32; /* Contains BUFIO$K_64 to for use of uva64 */N unsigned short int mbox_buf$w_mbz; /* Must be Zero d8 */N unsigned char mbox_buf$b_type; /* Block type DYN$C_MISC */N unsigned char mbox_buf$b_subtype; /* Block subtype DYN$C_MBX_MSG */N int mbox_buf$l_datastart; /* Start of Data in packet */N __int64 mbox_buf$pq_uva64; /* 64-bit Address of user buffer */N unsigned int mbox_buf$l_size; /* Block size */N unsigned short int mbox_buf$w_datasize; /* Data size */N e8unsigned short int mbox_buf$w_reqsize; /* Data size requested */N unsigned short int mbox_buf$w_bufquocharge; /* BUFQUO charged? */ char mbox_buf$b_fill_0_ [6];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif#if defined(__VAXC) char mbox_buf$r_data[];#elseV/* Warning: empty char[] member for mbox_buf$r_data at end of struf8cture not created */"#endif /* #if defined(__VAXC) */ } MBOX_BUF; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MBOXDEF_LOADED */ wwy[UM/***************************************************************************g8/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** h8 **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** i8 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */K/* Source: 02-APR-1998 16:28:12 $1$DGA8345:[LIB_H.SRC]MBR_INFODEF.SDL;1 *//*********************************************************************************************************************** j8*********//*** MODULE $mbr_infodef ***/#ifndef __MBR_INFODEF_LOADED#define __MBR_INFODEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bik8t pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* l8 */N/* Ident X-5 */N/* */I/* MEM_INFODEF.SDL -- Membership info return structure and membership */;/* callback mask bits. */N/* */I/* Copyright Digital Equipment Corporation, 1998. */I/* All rights reservm8ed. */N/* */I/* The software contained on this media is proprietary to and */I/* embodies the confidential technology of Digital Equipment */I/* Corporation. Possession, use, duplication, or dissemination */I/* of the software and media is authorized only pursuant to a */I/* valid written license from Digital Equipment Corporation. n8 */N/* */I/* RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure */I/* by the U.S. Government is subject to restrictions as set */I/* forth in Subparagraph (c) (1) (ii) of DFARS 252.227-7013, */I/* or in FAR 52.227-19, as applicable. */N/* */O/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-o8=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */N/* */N/* */N/* Description: This file contains the definition of the values and */B/* structures needed for the Galaxy get_member_info call */B/* and the membership callback call. */N/* */Np8/* Environment: OpenVMS Operating System, privileged kernel-mode */N/* */I/* Author: Paul Harter */N/* */N/* Modifications: */N/* */:/* X-5 PKH-G027 Paul K. Harter q8, Jr. 2-Apr-1998 */B/* Add constants for membership status values. */N/* */1/* X-4 AHM039 Drew Mason 16-Feb-1998 */B/* Add mask bits for join/leave parameter to membership */B/* callbacks. */N/* */:/* X-3 PKH-G012 Paul K. Harter, Jr. 13-Feb-1998 */Br8/* Add node state to return structure. Define constant */B/* MIREQ$_ALL_NODES for "*" node_id. */N/* */:/* X-2 PKH-G009 Paul K. Harter, Jr. 2-Feb-1998 */B/* Fix alignment of name field. */N/* */:/* X-1 PKH-G008 Paul K. Harter, Jr. 2-Feb-1998 */B/* Initial entry. s8 */N/* */ N/* Get member information requests */#define MIREQ$_ALL 0#define MIREQ$_NAME 1#define MIREQ$_STATE 2#define MIREQ$_GXY_MEMBER 3#define MIREQ$_INCARNATION 4#define MIREQ$_HEARTBEAT 5#define MIREQ$_TIME 6#define MIREQ$_TOO_BIG 7N/* galaxy membership status values */#define t8MIGMS$_NOT_MEMBER 0#define MIGMS$_MEMBER 1#define MIGMS$_BEING_REMOVED 2#define MIGMS$_TOO_BIG 3N#define MIREQ$_ALL_NODES -1 /* request for info on all nodes */N#define MINFO$C_LENGTH 48 /* length of mbr_info struct */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mbr_info {#pragma __nomember u8_alignmentN unsigned int minfo$l_node_id; /* node_id of node described */P unsigned int minfo$l_state; /* current node state from node block */R unsigned int minfo$l_gxy_member; /* galaxy membership status (see above) */ char minfo$b_fill_0_ [4]; N unsigned __int64 minfo$q_name; /* node's SCS node name */N unsigned __int64 minfo$q_incarnation; /* incarnation at last join */N unsigned __int64 minfo$q_heartbeat; /* node's cu v8rrent heartbeat value */N unsigned __int64 minfo$q_time; /* time of last join (systime) */ } MBR_INFO;N/* Mask bits for join/leave parameter to membership callbacks. */N#define GLXCBK$M_NODE_LEFT 1 /* some node left the Galaxy */N#define GLXCBK$M_NODE_JOINED 2 /* some node joined */N/* the Galaxy */ #ifdef __INITIAL_POINTER_SIZEI #pragma __required_po w8inter_size __save /* Save current pointer size */C #pragma __required_pointer_size __long /* Pointers are 64-bit */? typedef MBR_INFO *MBR_INFO_PQ; /* Long ptr to a MBR_INFO */D typedef MBR_INFO **MBR_INFO_PPQ; /* Long ptr to a long ptr to */% /* MBR_INFO structure. */L #pragma __required_pointer_size __restore /* Restore prev. pointer size*/#else( typedef unsigned __int64 MBR_INFO_PQ;) typedef unsigned __int64 MBR_INFO_PPQ;##endif /* __INITIAL_POINTER_SIZE */x8 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __MBR_INFODEF_LOADED */ wwz[UM/***************************************************************************/M/** y8 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTz8WARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************{8**************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 22-APR-1993 11:32:24 $1$DGA8345:[LIB_H.SRC]MBXDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MBXDEF ***/#ifndef __MBXDEF_LOADED#define __MB |8XDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params}8 ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SHARED MEMORY MAILBOX CONTROL BLOCK DEFINITIONS ~8 */N/* */N/* THERE IS ONE MAILBOX CONTROL BLOCK FOR EACH MAILBOX IN SHARED */N/* MEMORY. ANY PROCESSOR THAT WANTS TO ACCESS THE MAILBOX CREATES */N/* A UCB TO CONTROL ACCESS TO THE MAILBOX. */N/*- */#define MBX$M_ALLOC 0x1#define MBX$M_VALID 0x2#define MBX$M_DELPEND 0x4#def 8ine MBX$M_QUOTALCK 0x8N#define MBX$K_LENGTH 48 /*LENGTH OF STRUCTURE */N#define MBX$C_LENGTH 48 /*LENGTH OF STRUCTURE */#define MBX$S_MBXDEF 48 typedef struct _mbx {N unsigned __int64 mbx$q_msg; /*MESSAGE QUEUE LISTHEAD */ __union {N unsigned char mbx$b_flags; /*FLAGS */ __struct {N unsigned mbx$v_alloc : 1; /* MAILBOX ALLOCATED 8 */N unsigned mbx$v_valid : 1; /* MAILBOX INITIALIZED AND USEABLE */N unsigned mbx$v_delpend : 1; /* DELETE PENDING */N unsigned mbx$v_quotalck : 1; /* QUOTA/COUNT MODIFICATION LOCK */' unsigned mbx$v_fill_0_ : 4; } mbx$r_flags_bits; } mbx$r_flags_overlay;N unsigned char mbx$b_creatport; /*PORT NUMBER OF MAILBOX CREATOR */N unsigned short int mbx$w_unit; /*MAILBOX UNIT NUMBER 8 */N unsigned short int mbx$w_ref; /*REFERENCE FLAGS (1 BIT/PORT) */N unsigned short int mbx$w_reader; /*WAITING READER (1 BIT/PORT) */N unsigned short int mbx$w_readast; /*WAITING READ AST (1 BIT/PORT) */N unsigned short int mbx$w_writast; /*WAITING WRITE AST (1 BIT/PORT) */N unsigned short int mbx$w_maxmsg; /*MAXIMUM MESSAGE SIZE */N unsigned short int mbx$w_msgcnt; /*CURRENT NUMBER OF MESSAGES */N unsigned s 8hort int mbx$w_buffquo; /*BUFFER QUOTA */N unsigned short int mbx$w_prot; /*PROTECTION MASK */N unsigned int mbx$l_ownuic; /*OWNER UIC */N char mbx$t_name [16]; /*MAILBOX NAME (COUNTED STRING) */N/* *** THE LENGTH OF THIS STRUCTURE MUST BE AN EVEN MULTIPLE OF 8 *** */N/* *** BECAUSE THE MESSAGE QUEUE HEADER MUST BE QUADWORD ALIGNED *** */ } MBX; #if !defined(__VAXC)3#d 8efine mbx$b_flags mbx$r_flags_overlay.mbx$b_flagsD#define mbx$v_alloc mbx$r_flags_overlay.mbx$r_flags_bits.mbx$v_allocD#define mbx$v_valid mbx$r_flags_overlay.mbx$r_flags_bits.mbx$v_validH#define mbx$v_delpend mbx$r_flags_overlay.mbx$r_flags_bits.mbx$v_delpendJ#define mbx$v_quotalck mbx$r_flags_overlay.mbx$r_flags_bits.mbx$v_quotalck"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */8b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MBXDEF_LOADED */ ww`S{[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterp8rise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is 8not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************************** 8***************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 16-DEC-1993 14:32:54 $1$DGA8345:[LIB_H.SRC]MCBDEF.SDL;1 *//********************************************************************************************************************************/!/*** MODULE MCBDEF IDENT X-2 ***/#ifndef __MCBDEF_LOADED#define __MCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment _8_save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifnde8f __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  9#ifdef __cplusplus /* Define structure prototypes */ struct _vcb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword 8#else#pragma __nomember_alignment#endiftypedef struct _mcb {#pragma __nomember_alignmentN struct _mcb *mcb$l_flink; /* Queue forward link */N struct _mcb *mcb$l_blink; /* Queue backward link */N unsigned short int mcb$w_size; /* Size of data structure */N unsigned char mcb$b_type; /* Type DYN$C_SM */N unsigned char mcb$b_subtype; /* Subtype DYN$C_SM_MCB */N st 8ruct _vcb *mcb$l_vcb; /* Address of VCB for mount */N unsigned int mcb$l_imcv; /* Internal mount context value */N unsigned int mcb$l_emcv; /* External mount context value */ } MCB;R#define MCB$S_MCBDEF 24 /* Old size name, synonym for MCB$S_MCB */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Res8tore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MCBDEF_LOADED */ ww{[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** author8ized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicate8d or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created 8: 7-Oct-2024 15:22:13 by OpenVMS SDL V3.7 */H/* Source: 09-FEB-1998 14:37:36 $1$DGA8345:[LIB_H.SRC]MCBUSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MCBUSDEF ***/#ifndef __MCBUSDEF_LOADED#define __MCBUSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL8_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct str8uct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mc_pci {#pragma __nomember_alignment" unsigned int mc_pci$l_pci_rev;$ unsigned char mc_pci$b_f00 [860];! unsigned int mc_pci$l_whoami;$ unsigned char mc_pci$b_f01 [60];" unsigned int mc_pci$l_pci_lat;% unsigned char mc_pci$b_f02 [124];# unsigned int mc_pci$l_cap_ctrl;% unsigned char mc_pci$b_f03 [508];# unsigned int mc_pci$l_perf_mon;$ unsigned char mc_pci$b_f04 [60];$ unsigned int mc_pci$l_perf_cont;% unsigned char mc_pci$b_f05 [188];" unsigned int mc_pci$l_hae_mem;$ unsigned char mc_pci$b_f06 [60];! unsigned int mc_pci$l_hae_io;$ unsi8gned char mc_pci$b_f07 [60];" unsigned int mc_pci$l_iack_sc;$ unsigned char mc_pci$b_f08 [60];$ unsigned int mc_pci$l_hae_dense;$ unsigned char mc_pci$b_f09 [60];" unsigned int mc_pci$l_int_ctl;$ unsigned char mc_pci$b_f10 [60];" unsigned int mc_pci$l_int_req;$ unsigned char mc_pci$b_f11 [60];# unsigned int mc_pci$l_int_targ;$ unsigned char mc_pci$b_f12 [60];" unsigned int mc_pci$l_int_adr;$ unsigned char mc_pci$b_f13 [60];& unsigned int mc_pci$l_in8t_adr_ext;$ unsigned char mc_pci$b_f14 [60];$ unsigned int mc_pci$l_int_mask0;$ unsigned char mc_pci$b_f15 [60];$ unsigned int mc_pci$l_int_mask1;% unsigned char mc_pci$b_f16 [124];# unsigned int mc_pci$l_cap_diag;$ unsigned char mc_pci$b_f17 [60];" unsigned int mc_pci$l_scratch;% unsigned char mc_pci$b_f18 [188];" unsigned int mc_pci$l_mc_err0;$ unsigned char mc_pci$b_f19 [60];" unsigned int mc_pci$l_mc_err1;$ unsigned char mc_pci$b_f20 [60];" 8 unsigned int mc_pci$l_cap_err;& unsigned char mc_pci$b_f21 [1980];# unsigned int mc_pci$l_pci_err1;% unsigned char mc_pci$b_f22 [700];" unsigned int mc_pci$l_sg_tbia;$ unsigned char mc_pci$b_f23 [60]; unsigned int mc_pci$l_hbase;% unsigned char mc_pci$b_f24 [188];" unsigned int mc_pci$l_w0_base;$ unsigned char mc_pci$b_f25 [60];" unsigned int mc_pci$l_w0_mask;$ unsigned char mc_pci$b_f26 [60];" unsigned int mc_pci$l_t0_base;% unsigned char mc_p8ci$b_f27 [124];" unsigned int mc_pci$l_w1_base;$ unsigned char mc_pci$b_f28 [60];" unsigned int mc_pci$l_w1_mask;$ unsigned char mc_pci$b_f29 [60];" unsigned int mc_pci$l_t1_base;% unsigned char mc_pci$b_f30 [124];" unsigned int mc_pci$l_w2_base;$ unsigned char mc_pci$b_f31 [60];" unsigned int mc_pci$l_w2_mask;$ unsigned char mc_pci$b_f32 [60];" unsigned int mc_pci$l_t2_base;% unsigned char mc_pci$b_f33 [124];" unsigned int mc_pci$l_w3_base;$ 8unsigned char mc_pci$b_f34 [60];" unsigned int mc_pci$l_w3_mask;$ unsigned char mc_pci$b_f35 [60];" unsigned int mc_pci$l_t3_base;$ unsigned char mc_pci$b_f36 [60]; unsigned int mc_pci$l_w_dac;$ unsigned char mc_pci$b_f37 [60];" unsigned int mc_pci$l_tb_tag0;$ unsigned char mc_pci$b_f38 [60];" unsigned int mc_pci$l_tb_tag1;$ unsigned char mc_pci$b_f39 [60];" unsigned int mc_pci$l_tb_tag2;$ unsigned char mc_pci$b_f40 [60];" unsigned int mc_pci$l_tb_t8ag3;$ unsigned char mc_pci$b_f41 [60];" unsigned int mc_pci$l_tb_tag4;$ unsigned char mc_pci$b_f42 [60];" unsigned int mc_pci$l_tb_tag5;$ unsigned char mc_pci$b_f43 [60];" unsigned int mc_pci$l_tb_tag6;$ unsigned char mc_pci$b_f44 [60];" unsigned int mc_pci$l_tb_tag7;& unsigned char mc_pci$b_f45 [1596];$ unsigned int mc_pci$l_tb0_page0;$ unsigned char mc_pci$b_f46 [60];$ unsigned int mc_pci$l_tb0_page1;$ unsigned char mc_pci$b_f47 [60];$ unsigned8 int mc_pci$l_tb0_page2;$ unsigned char mc_pci$b_f48 [60];$ unsigned int mc_pci$l_tb0_page3;$ unsigned char mc_pci$b_f49 [60];$ unsigned int mc_pci$l_tb1_page0;$ unsigned char mc_pci$b_f50 [60];$ unsigned int mc_pci$l_tb1_page1;$ unsigned char mc_pci$b_f51 [60];$ unsigned int mc_pci$l_tb1_page2;$ unsigned char mc_pci$b_f52 [60];$ unsigned int mc_pci$l_tb1_page3;$ unsigned char mc_pci$b_f53 [60];$ unsigned int mc_pci$l_tb2_page0;$ unsigned char mc_pci8$b_f54 [60];$ unsigned int mc_pci$l_tb2_page1;$ unsigned char mc_pci$b_f55 [60];$ unsigned int mc_pci$l_tb2_page2;$ unsigned char mc_pci$b_f56 [60];$ unsigned int mc_pci$l_tb2_page3;$ unsigned char mc_pci$b_f57 [60];$ unsigned int mc_pci$l_tb3_page0;$ unsigned char mc_pci$b_f58 [60];$ unsigned int mc_pci$l_tb3_page1;$ unsigned char mc_pci$b_f59 [60];$ unsigned int mc_pci$l_tb3_page2;$ unsigned char mc_pci$b_f60 [60];$ unsigned int mc_pci$l_tb3_page3;8$ unsigned char mc_pci$b_f61 [60];$ unsigned int mc_pci$l_tb4_page0;$ unsigned char mc_pci$b_f62 [60];$ unsigned int mc_pci$l_tb4_page1;$ unsigned char mc_pci$b_f63 [60];$ unsigned int mc_pci$l_tb4_page2;$ unsigned char mc_pci$b_f64 [60];$ unsigned int mc_pci$l_tb4_page3;$ unsigned char mc_pci$b_f65 [60];$ unsigned int mc_pci$l_tb5_page0;$ unsigned char mc_pci$b_f66 [60];$ unsigned int mc_pci$l_tb5_page1;$ unsigned char mc_pci$b_f67 [60];$ unsign8ed int mc_pci$l_tb5_page2;$ unsigned char mc_pci$b_f68 [60];$ unsigned int mc_pci$l_tb5_page3;$ unsigned char mc_pci$b_f69 [60];$ unsigned int mc_pci$l_tb6_page0;$ unsigned char mc_pci$b_f70 [60];$ unsigned int mc_pci$l_tb6_page1;$ unsigned char mc_pci$b_f71 [60];$ unsigned int mc_pci$l_tb6_page2;$ unsigned char mc_pci$b_f72 [60];$ unsigned int mc_pci$l_tb6_page3;$ unsigned char mc_pci$b_f73 [60];$ unsigned int mc_pci$l_tb7_page0;$ unsigned char mc_p8ci$b_f74 [60];$ unsigned int mc_pci$l_tb7_page1;$ unsigned char mc_pci$b_f75 [60];$ unsigned int mc_pci$l_tb7_page2;$ unsigned char mc_pci$b_f76 [60];$ unsigned int mc_pci$l_tb7_page3;& unsigned char mc_pci$b_f77 [6204];$ unsigned int mc_pci$l_mdpa_stat;$ unsigned char mc_pci$b_f78 [60];# unsigned int mc_pci$l_mdpa_syn;$ unsigned char mc_pci$b_f79 [60];$ unsigned int mc_pci$l_mdpa_diag;' unsigned char mc_pci$b_f80 [16252];$ unsigned int mc_pci$l_md8pb_stat;$ unsigned char mc_pci$b_f81 [60];# unsigned int mc_pci$l_mdpb_syn;$ unsigned char mc_pci$b_f82 [60];$ unsigned int mc_pci$l_mdpb_diag; char mc_pci$b_fill_0_ [4]; } MC_PCI; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _int_ack {#pragma __nomember_alignment# unsigned int mc_pci$l_int_ack0;$ un8signed char mc_pci$b_f83 [60];# unsigned int mc_pci$l_int_ack1; char mc_pci$b_fill_1_ [4]; } INT_ACK; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MCBUSDEF_LOADED */ ww{[UM/*********************************8******************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development,8 LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 8 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */I/* Source: 11-MAY-1993 15:20:14 $1$DGA8345:[LIB_H.SRC]KA0302DEF.SDL;1 *//******************************************************************************* 8*************************************************//*** MODULE $MCHECK0302DEF ***/#ifndef __MCHECK0302DEF_LOADED #define __MCHECK0302DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size 8__short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif )#d 8efine MCHECK0302$M_GBUS_HALT_PHALT 0x40)#define MCHECK0302$M_GBUS_HALT_NHALT 0x80/#define MCHECK0302$M_GBUS_INTR_UARTINT0 0x10000/#define MCHECK0302$M_GBUS_INTR_UARTINT1 0x20000+#define MCHECK0302$M_GBUS_INTR_LSB0 0x40000,#define MCHECK0302$M_GBUS_INTR_LSB2 0x200000*#define MCHECK0302$M_GBUS_INTR_IP 0x400000-#define MCHECK0302$M_GBUS_INTR_INTIM 0x8000002#define MCHECK0302$M_GBUS_PMASK_HALTEN 0x1000000003#define MCHECK0302$M_GBUS_PMASK_SELTERM 0x6000000003#define MCHECK0302$M_GBUS_WHAM 8I_NID 0x70000000000003#define MCHECK0302$M_GBUS_WHAMI_MFG 0x80000000000008#define MCHECK0302$M_GBUS_WHAMI_LSB_BAD 0x10000000000000 typedef struct _gbus { __union { __struct {1 unsigned mcheck0302$v_gbus_fill1 : 6;6 unsigned mcheck0302$v_gbus_halt_phalt : 1;6 unsigned mcheck0302$v_gbus_halt_nhalt : 1;1 unsigned mcheck0302$v_gbus_fill2 : 8;9 unsigned mcheck0302$v_gbus_intr_uartint0 : 1;9 unsigned mcheck0 8302$v_gbus_intr_uartint1 : 1;5 unsigned mcheck0302$v_gbus_intr_lsb0 : 1;6 unsigned mcheck0302$v_gbus_intr_fill1 : 2;5 unsigned mcheck0302$v_gbus_intr_lsb2 : 1;3 unsigned mcheck0302$v_gbus_intr_ip : 1;6 unsigned mcheck0302$v_gbus_intr_intim : 1;6 unsigned mcheck0302$v_gbus_intr_fill2 : 8;8 unsigned mcheck0302$v_gbus_pmask_halten : 1;9 unsigned mcheck0302$v_gbus_pmask_selterm : 2;8 unsigned m 8check0302$v_gbus_pmask_fill1 : 13;5 unsigned mcheck0302$v_gbus_whami_nid : 3;5 unsigned mcheck0302$v_gbus_whami_mfg : 1;9 unsigned mcheck0302$v_gbus_whami_lsb_bad : 1;. unsigned mcheck0302$v_fill_3_ : 3;% } mcheck0302$r_gbus_bits;$ } mcheck0302$r_gbus_overlay; } GBUS; #if !defined(__VAXC)r#define mcheck0302$v_gbus_halt_phalt mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_halt_phaltr#define mcheck03802$v_gbus_halt_nhalt mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_halt_nhaltx#define mcheck0302$v_gbus_intr_uartint0 mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_intr_uartint0x#define mcheck0302$v_gbus_intr_uartint1 mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_intr_uartint1p#define mcheck0302$v_gbus_intr_lsb0 mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_intr_lsb0p#define mcheck0302$v_gbus_intr_lsb2 mcheck0302$r8_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_intr_lsb2l#define mcheck0302$v_gbus_intr_ip mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_intr_ipr#define mcheck0302$v_gbus_intr_intim mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_intr_intimv#define mcheck0302$v_gbus_pmask_halten mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_pmask_haltenx#define mcheck0302$v_gbus_pmask_selterm mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mchec 8k0302$v_gbus_pmask_seltermp#define mcheck0302$v_gbus_whami_nid mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_whami_nidp#define mcheck0302$v_gbus_whami_mfg mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_whami_mfgx#define mcheck0302$v_gbus_whami_lsb_bad mcheck0302$r_gbus_overlay.mcheck0302$r_gbus_bits.mcheck0302$v_gbus_whami_lsb_bad"#endif /* #if !defined(__VAXC) */  typedef struct _lmode { __union {( unsigned int mcheck0302$l_lmode;8 __struct {3 unsigned mcheck0302$v_lmode_fill1 : 32;& } mcheck0302$r_lmode_bits;% } mcheck0302$r_lmode_overlay; } LMODE; #if !defined(__VAXC)H#define mcheck0302$l_lmode mcheck0302$r_lmode_overlay.mcheck0302$l_lmode"#endif /* #if !defined(__VAXC) */  typedef struct _lmerr { __union {( unsigned int mcheck0302$l_lmerr; __union {, __int64 mcheck0302$q_lmerr_bits; __struct {< 8unsigned mcheck0302$v_lmerr_pmap_dlowpe : 1;; unsigned mcheck0302$v_lmerr_pmap_dhipe : 1;: unsigned mcheck0302$v_lmerr_pmap_i0pe : 1;: unsigned mcheck0302$v_lmerr_pmap_i1pe : 1;O unsigned mcheck0302$v_lmerr_btagpe : 1; /* BTAG Parity Error */S unsigned mcheck0302$v_lmerr_bstatpe : 1; /* BSTATUS Parity Error */O unsigned mcheck0302$v_lmerr_bmappe : 1; /* BMAP Parity Error */] unsigned mch8eck0302$v_lmerr_bdatasbe : 1; /* Bcache Data Single Bit error */] unsigned mcheck0302$v_lmerr_bdatadbe : 1; /* Bcache Data Double Bit error */T unsigned mcheck0302$v_lmerr_arbcol : 1; /* Arbitration COllision */O unsigned mcheck0302$v_lmerr_arbdrop : 1; /* Arbitration Drop */N unsigned mcheck0302$v_lmerr_edalto : 1; /* EDAL Timeout. */2 unsigned mcheck0302$v_fill_6_ : 4;' } mcheck0302$r_fill_5_;# 8 } mcheck0302$r_fill_4_;% } mcheck0302$r_lmerr_overlay; } LMERR; #if !defined(__VAXC)H#define mcheck0302$l_lmerr mcheck0302$r_lmerr_overlay.mcheck0302$l_lmerr#define mcheck0302$v_lmerr_pmap_dlowpe mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_5_.mcheck0302$v_lmerr_pmap\_dlowpe#define mcheck0302$v_lmerr_pmap_dhipe mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_5_.mcheck0302$v_lmerr_pmap_\dhipe#define mcheck0302$v_lmerr_p8map_i0pe mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_5_.mcheck0302$v_lmerr_pmap_i\0pe#define mcheck0302$v_lmerr_pmap_i1pe mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_5_.mcheck0302$v_lmerr_pmap_i\1pe#define mcheck0302$v_lmerr_btagpe mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_5_.mcheck0302$v_lmerr_btagpe#define mcheck0302$v_lmerr_bstatpe mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_5_.mcheck0302$v_lmerr_b8statpe#define mcheck0302$v_lmerr_bmappe mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_5_.mcheck0302$v_lmerr_bmappe#define mcheck0302$v_lmerr_bdatasbe mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_5_.mcheck0302$v_lmerr_bdatasbe#define mcheck0302$v_lmerr_bdatadbe mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_5_.mcheck0302$v_lmerr_bdatadbe#define mcheck0302$v_lmerr_arbcol mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_ 85_.mcheck0302$v_lmerr_arbcol#define mcheck0302$v_lmerr_arbdrop mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_5_.mcheck0302$v_lmerr_arbdrop#define mcheck0302$v_lmerr_edalto mcheck0302$r_lmerr_overlay.mcheck0302$r_fill_4_.mcheck0302$r_fill_5_.mcheck0302$v_lmerr_edalto"#endif /* #if !defined(__VAXC) */  typedef struct _llock { __union {( unsigned int mcheck0302$l_llock; __struct {3 unsigned mcheck0302$v_llock_fill1 : 32;& 8 } mcheck0302$r_llock_bits;% } mcheck0302$r_llock_overlay; } LLOCK; #if !defined(__VAXC)H#define mcheck0302$l_llock mcheck0302$r_llock_overlay.mcheck0302$l_llock"#endif /* #if !defined(__VAXC) */ #define MCHECK0302$M_LBER_E 0x1!#define MCHECK0302$M_LBER_UCE 0x2"#define MCHECK0302$M_LBER_UCE2 0x4 #define MCHECK0302$M_LBER_CE 0x8"#define MCHECK0302$M_LBER_CE2 0x10"#define MCHECK0302$M_LBER_CPE 0x20##define MCHECK0302$M_LBER_CPE2 0x40##define MCHECK0302$M_LBER_CDPE 08x80%#define MCHECK0302$M_LBER_CDPE2 0x100##define MCHECK0302$M_LBER_TDE 0x200##define MCHECK0302$M_LBER_STE 0x400$#define MCHECK0302$M_LBER_CNFE 0x800%#define MCHECK0302$M_LBER_NXAE 0x1000$#define MCHECK0302$M_LBER_CAE 0x2000$#define MCHECK0302$M_LBER_SHE 0x4000$#define MCHECK0302$M_LBER_DIE 0x8000&#define MCHECK0302$M_LBER_DTCE 0x10000&#define MCHECK0302$M_LBER_CTCE 0x20000&#define MCHECK0302$M_LBER_NSES 0x40000 typedef struct _lber { __union {' unsigned int mcheck0 8302$l_lber; __struct {- unsigned mcheck0302$v_lber_e : 1;/ unsigned mcheck0302$v_lber_uce : 1;0 unsigned mcheck0302$v_lber_uce2 : 1;. unsigned mcheck0302$v_lber_ce : 1;/ unsigned mcheck0302$v_lber_ce2 : 1;/ unsigned mcheck0302$v_lber_cpe : 1;0 unsigned mcheck0302$v_lber_cpe2 : 1;0 unsigned mcheck0302$v_lber_cdpe : 1;1 unsigned mcheck0302$v_lber_cdpe2 : 1;/ unsigned m 8check0302$v_lber_tde : 1;/ unsigned mcheck0302$v_lber_ste : 1;0 unsigned mcheck0302$v_lber_cnfe : 1;0 unsigned mcheck0302$v_lber_nxae : 1;/ unsigned mcheck0302$v_lber_cae : 1;/ unsigned mcheck0302$v_lber_she : 1;/ unsigned mcheck0302$v_lber_die : 1;0 unsigned mcheck0302$v_lber_dtce : 1;0 unsigned mcheck0302$v_lber_ctce : 1;0 unsigned mcheck0302$v_lber_nses : 1;2 unsigned mcheck0 8302$v_lber_fill1 : 13;% } mcheck0302$r_lber_bits;$ } mcheck0302$r_lber_overlay; } LBER; #if !defined(__VAXC)E#define mcheck0302$l_lber mcheck0302$r_lber_overlay.mcheck0302$l_lber`#define mcheck0302$v_lber_e mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_ed#define mcheck0302$v_lber_uce mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_ucef#define mcheck0302$v_lber_uce2 mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v8_lber_uce2b#define mcheck0302$v_lber_ce mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_ced#define mcheck0302$v_lber_ce2 mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_ce2d#define mcheck0302$v_lber_cpe mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_cpef#define mcheck0302$v_lber_cpe2 mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_cpe2f#define mcheck0302$v_lber_cdpe mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck80302$v_lber_cdpeh#define mcheck0302$v_lber_cdpe2 mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_cdpe2d#define mcheck0302$v_lber_tde mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_tded#define mcheck0302$v_lber_ste mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_stef#define mcheck0302$v_lber_cnfe mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_cnfef#define mcheck0302$v_lber_nxae mcheck0302$r_lber_overlay.mcheck0302$r_lber8_bits.mcheck0302$v_lber_nxaed#define mcheck0302$v_lber_cae mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_caed#define mcheck0302$v_lber_she mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_shed#define mcheck0302$v_lber_die mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_dief#define mcheck0302$v_lber_dtce mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_dtcef#define mcheck0302$v_lber_ctce mcheck0302$r_lber_overlay.mcheck03082$r_lber_bits.mcheck0302$v_lber_ctcef#define mcheck0302$v_lber_nses mcheck0302$r_lber_overlay.mcheck0302$r_lber_bits.mcheck0302$v_lber_nses"#endif /* #if !defined(__VAXC) */ "#define MCHECK0302$M_LCNR_CEEN 0x1,#define MCHECK0302$M_LCNR_RSTSTAT 0x10000000*#define MCHECK0302$M_LCNR_NHALT 0x20000000)#define MCHECK0302$M_LCNR_NRST 0x40000000(#define MCHECK0302$M_LCNR_STF 0x80000000 typedef struct _lcnr { __union {' unsigned int mcheck0302$l_lcnr; __struct {0 8 unsigned mcheck0302$v_lcnr_ceen : 1;2 unsigned mcheck0302$v_lcnr_fill1 : 27;3 unsigned mcheck0302$v_lcnr_rststat : 1;1 unsigned mcheck0302$v_lcnr_nhalt : 1;0 unsigned mcheck0302$v_lcnr_nrst : 1;/ unsigned mcheck0302$v_lcnr_stf : 1;% } mcheck0302$r_lcnr_bits;$ } mcheck0302$r_lcnr_overlay; } LCNR; #if !defined(__VAXC)E#define mcheck0302$l_lcnr mcheck0302$r_lcnr_overlay.mcheck0302$l_lcnrf#define mche8ck0302$v_lcnr_ceen mcheck0302$r_lcnr_overlay.mcheck0302$r_lcnr_bits.mcheck0302$v_lcnr_ceenl#define mcheck0302$v_lcnr_rststat mcheck0302$r_lcnr_overlay.mcheck0302$r_lcnr_bits.mcheck0302$v_lcnr_rststath#define mcheck0302$v_lcnr_nhalt mcheck0302$r_lcnr_overlay.mcheck0302$r_lcnr_bits.mcheck0302$v_lcnr_nhaltf#define mcheck0302$v_lcnr_nrst mcheck0302$r_lcnr_overlay.mcheck0302$r_lcnr_bits.mcheck0302$v_lcnr_nrstd#define mcheck0302$v_lcnr_stf mcheck0302$r_lcnr_overlay.mcheck0302$r_lcnr_bits.mcheck0302$v_lc8nr_stf"#endif /* #if !defined(__VAXC) */ &#define MCHECK0302$M_LDEV_DTYPE 0xFFFF)#define MCHECK0302$M_LDEV_DREV 0xFFFF0000 typedef struct _ldev { __union {' unsigned int mcheck0302$l_ldev; __struct {2 unsigned mcheck0302$v_ldev_dtype : 16;1 unsigned mcheck0302$v_ldev_drev : 16;% } mcheck0302$r_ldev_bits;$ } mcheck0302$r_ldev_overlay; } LDEV; #if !defined(__VAXC)E#define mcheck0302$l_ldev mcheck0302$r_ldev_ 8overlay.mcheck0302$l_ldevh#define mcheck0302$v_ldev_dtype mcheck0302$r_ldev_overlay.mcheck0302$r_ldev_bits.mcheck0302$v_ldev_dtypef#define mcheck0302$v_ldev_drev mcheck0302$r_ldev_overlay.mcheck0302$r_ldev_bits.mcheck0302$v_ldev_drev"#endif /* #if !defined(__VAXC) */ )#define MCHECK0302$M_LBESR0_SYNDROME 0x7F typedef struct _lbesr0 { __union {) unsigned int mcheck0302$l_lbesr0; __struct {6 unsigned mcheck0302$v_lbesr0_syndrome : 7;4 unsi8gned mcheck0302$v_lbesr0_fill1 : 25;' } mcheck0302$r_lbesr0_bits;& } mcheck0302$r_lbesr0_overlay; } LBESR0; #if !defined(__VAXC)K#define mcheck0302$l_lbesr0 mcheck0302$r_lbesr0_overlay.mcheck0302$l_lbesr0v#define mcheck0302$v_lbesr0_syndrome mcheck0302$r_lbesr0_overlay.mcheck0302$r_lbesr0_bits.mcheck0302$v_lbesr0_syndrome"#endif /* #if !defined(__VAXC) */ )#define MCHECK0302$M_LBESR1_SYNDROME 0x7F typedef struct _lbesr1 { __union {) unsigned 8 int mcheck0302$l_lbesr1; __struct {6 unsigned mcheck0302$v_lbesr1_syndrome : 7;4 unsigned mcheck0302$v_lbesr1_fill1 : 25;' } mcheck0302$r_lbesr1_bits;& } mcheck0302$r_lbesr1_overlay; } LBESR1; #if !defined(__VAXC)K#define mcheck0302$l_lbesr1 mcheck0302$r_lbesr1_overlay.mcheck0302$l_lbesr1v#define mcheck0302$v_lbesr1_syndrome mcheck0302$r_lbesr1_overlay.mcheck0302$r_lbesr1_bits.mcheck0302$v_lbesr1_syndrome"#endif /* #if !defined(8__VAXC) */ )#define MCHECK0302$M_LBESR2_SYNDROME 0x7F typedef struct _lbesr2 { __union {) unsigned int mcheck0302$l_lbesr2; __struct {6 unsigned mcheck0302$v_lbesr2_syndrome : 7;4 unsigned mcheck0302$v_lbesr2_fill1 : 25;' } mcheck0302$r_lbesr2_bits;& } mcheck0302$r_lbesr2_overlay; } LBESR2; #if !defined(__VAXC)K#define mcheck0302$l_lbesr2 mcheck0302$r_lbesr2_overlay.mcheck0302$l_lbesr2v#define mcheck0302$v_l8besr2_syndrome mcheck0302$r_lbesr2_overlay.mcheck0302$r_lbesr2_bits.mcheck0302$v_lbesr2_syndrome"#endif /* #if !defined(__VAXC) */ )#define MCHECK0302$M_LBESR3_SYNDROME 0x7F typedef struct _lbesr3 { __union {) unsigned int mcheck0302$l_lbesr3; __struct {6 unsigned mcheck0302$v_lbesr3_syndrome : 7;4 unsigned mcheck0302$v_lbesr3_fill1 : 25;' } mcheck0302$r_lbesr3_bits;& } mcheck0302$r_lbesr3_overlay; } LBESR3; 8#if !defined(__VAXC)K#define mcheck0302$l_lbesr3 mcheck0302$r_lbesr3_overlay.mcheck0302$l_lbesr3v#define mcheck0302$v_lbesr3_syndrome mcheck0302$r_lbesr3_overlay.mcheck0302$r_lbesr3_bits.mcheck0302$v_lbesr3_syndrome"#endif /* #if !defined(__VAXC) */  typedef struct _lbecr0 { __union {) unsigned int mcheck0302$l_lbecr0; __struct {0 unsigned int mcheck0302$l_lbecr0_ca;' } mcheck0302$r_lbecr0_bits;& } mcheck0302$r_lbecr0_overlay; 8 } LBECR0; #if !defined(__VAXC)K#define mcheck0302$l_lbecr0 mcheck0302$r_lbecr0_overlay.mcheck0302$l_lbecr0j#define mcheck0302$l_lbecr0_ca mcheck0302$r_lbecr0_overlay.mcheck0302$r_lbecr0_bits.mcheck0302$l_lbecr0_ca"#endif /* #if !defined(__VAXC) */ "#define MCHECK0302$M_LBECR1_CA 0x7$#define MCHECK0302$M_LBECR1_CMD 0x38&#define MCHECK0302$M_LBECR1_RSVD 0x780&#define MCHECK0302$M_LBECR1_CID 0x7800&#define MCHECK0302$M_LBECR1_CNF 0x8000*#define MCHECK0302$M_LBECR1_SHARED 0x10000)#d 8efine MCHECK0302$M_LBECR1_DIRTY 0x20000*#define MCHECK0302$M_LBECR1_DCYCLE 0xC0000 typedef struct _lbecr1 { __union {) unsigned int mcheck0302$l_lbecr1; __struct {0 unsigned mcheck0302$v_lbecr1_ca : 3;1 unsigned mcheck0302$v_lbecr1_cmd : 3;1 unsigned mcheck0302$v_lbecr1_par : 1;2 unsigned mcheck0302$v_lbecr1_rsvd : 4;1 unsigned mcheck0302$v_lbecr1_cid : 4;1 unsigned mcheck0302$v_lbecr1_cnf : 1; 84 unsigned mcheck0302$v_lbecr1_shared : 1;3 unsigned mcheck0302$v_lbecr1_dirty : 1;4 unsigned mcheck0302$v_lbecr1_dcycle : 2;4 unsigned mcheck0302$v_lbecr1_fill1 : 12;' } mcheck0302$r_lbecr1_bits;& } mcheck0302$r_lbecr1_overlay; } LBECR1; #if !defined(__VAXC)K#define mcheck0302$l_lbecr1 mcheck0302$r_lbecr1_overlay.mcheck0302$l_lbecr1j#define mcheck0302$v_lbecr1_ca mcheck0302$r_lbecr1_overlay.mcheck0302$r_lbecr1_bits.mc8heck0302$v_lbecr1_cal#define mcheck0302$v_lbecr1_cmd mcheck0302$r_lbecr1_overlay.mcheck0302$r_lbecr1_bits.mcheck0302$v_lbecr1_cmdl#define mcheck0302$v_lbecr1_par mcheck0302$r_lbecr1_overlay.mcheck0302$r_lbecr1_bits.mcheck0302$v_lbecr1_parn#define mcheck0302$v_lbecr1_rsvd mcheck0302$r_lbecr1_overlay.mcheck0302$r_lbecr1_bits.mcheck0302$v_lbecr1_rsvdl#define mcheck0302$v_lbecr1_cid mcheck0302$r_lbecr1_overlay.mcheck0302$r_lbecr1_bits.mcheck0302$v_lbecr1_cidl#define mcheck0302$v_lbecr1_cnf mcheck03028$r_lbecr1_overlay.mcheck0302$r_lbecr1_bits.mcheck0302$v_lbecr1_cnfr#define mcheck0302$v_lbecr1_shared mcheck0302$r_lbecr1_overlay.mcheck0302$r_lbecr1_bits.mcheck0302$v_lbecr1_sharedp#define mcheck0302$v_lbecr1_dirty mcheck0302$r_lbecr1_overlay.mcheck0302$r_lbecr1_bits.mcheck0302$v_lbecr1_dirtyr#define mcheck0302$v_lbecr1_dcycle mcheck0302$r_lbecr1_overlay.mcheck0302$r_lbecr1_bits.mcheck0302$v_lbecr1_dcycle"#endif /* #if !defined(__VAXC) */ "#define MCHECK0302$M_MCR_DTYPE 0x1!#define MCHECK03 802$M_MCR_STRN 0xC`#define MCHECK0302$S_MCR 4 /* Old size name, synonym for MCHECK0302$S_KA0302MCR */ typedef struct _ka0302mcr { __union {& unsigned int mcheck0302$l_mcr; __struct {0 unsigned mcheck0302$v_mcr_dtype : 1;0 unsigned mcheck0302$v_mcr_fill1 : 1;/ unsigned mcheck0302$v_mcr_strn : 2;1 unsigned mcheck0302$v_mcr_fill2 : 28;$ } mcheck0302$r_mcr_bits;# } mcheck0302$r_mcr_overlay; 8 } KA0302MCR; #if !defined(__VAXC)B#define mcheck0302$l_mcr mcheck0302$r_mcr_overlay.mcheck0302$l_mcrd#define mcheck0302$v_mcr_dtype mcheck0302$r_mcr_overlay.mcheck0302$r_mcr_bits.mcheck0302$v_mcr_dtypeb#define mcheck0302$v_mcr_strn mcheck0302$r_mcr_overlay.mcheck0302$r_mcr_bits.mcheck0302$v_mcr_strn"#endif /* #if !defined(__VAXC) */ #define MCHECK0302$M_AMR_E 0x1!#define MCHECK0302$M_AMR_INTL 0x6 #define MCHECK0302$M_AMR_IA 0x18!#define MCHECK0302$M_AMR_AW 0x1E0%#define MCHE 8CK0302$M_AMR_NBANKS 0x600(#define MCHECK0302$M_AMR_MADR 0xFFFE0000`#define MCHECK0302$S_AMR 4 /* Old size name, synonym for MCHECK0302$S_KA0302AMR */ typedef struct _ka0302amr { __union {& unsigned int mcheck0302$l_amr; __struct {, unsigned mcheck0302$v_amr_e : 1;/ unsigned mcheck0302$v_amr_intl : 2;- unsigned mcheck0302$v_amr_ia : 2;- unsigned mcheck0302$v_amr_aw : 4;1 unsigned mcheck0302$v_ 8amr_nbanks : 2;0 unsigned mcheck0302$v_amr_fill1 : 6;0 unsigned mcheck0302$v_amr_madr : 15;$ } mcheck0302$r_amr_bits;# } mcheck0302$r_amr_overlay; } KA0302AMR; #if !defined(__VAXC)B#define mcheck0302$l_amr mcheck0302$r_amr_overlay.mcheck0302$l_amr\#define mcheck0302$v_amr_e mcheck0302$r_amr_overlay.mcheck0302$r_amr_bits.mcheck0302$v_amr_eb#define mcheck0302$v_amr_intl mcheck0302$r_amr_overlay.mcheck0302$r_amr_bits.mcheck0302$v_amr_intl^#defin 8e mcheck0302$v_amr_ia mcheck0302$r_amr_overlay.mcheck0302$r_amr_bits.mcheck0302$v_amr_ia^#define mcheck0302$v_amr_aw mcheck0302$r_amr_overlay.mcheck0302$r_amr_bits.mcheck0302$v_amr_awf#define mcheck0302$v_amr_nbanks mcheck0302$r_amr_overlay.mcheck0302$r_amr_bits.mcheck0302$v_amr_nbanksb#define mcheck0302$v_amr_madr mcheck0302$r_amr_overlay.mcheck0302$r_amr_bits.mcheck0302$v_amr_madr"#endif /* #if !defined(__VAXC) */  typedef struct _mstr0 { __union {( unsigned int mcheck03082$l_mstr0; __struct {3 unsigned mcheck0302$v_mstr0_fill1 : 32;& } mcheck0302$r_mstr0_bits;% } mcheck0302$r_mstr0_overlay; } MSTR0; #if !defined(__VAXC)H#define mcheck0302$l_mstr0 mcheck0302$r_mstr0_overlay.mcheck0302$l_mstr0"#endif /* #if !defined(__VAXC) */  typedef struct _mstr1 { __union {( unsigned int mcheck0302$l_mstr1; __struct {3 unsigned mcheck0302$v_mstr1_fill1 : 32;& } mcheck80302$r_mstr1_bits;% } mcheck0302$r_mstr1_overlay; } MSTR1; #if !defined(__VAXC)H#define mcheck0302$l_mstr1 mcheck0302$r_mstr1_overlay.mcheck0302$l_mstr1"#endif /* #if !defined(__VAXC) */  typedef struct _fadr { __union {' unsigned int mcheck0302$l_fadr; __struct {2 unsigned mcheck0302$v_fadr_fill1 : 32;% } mcheck0302$r_fadr_bits;$ } mcheck0302$r_fadr_overlay; } FADR; #if !defined(__VAXC)E#define mcheck80302$l_fadr mcheck0302$r_fadr_overlay.mcheck0302$l_fadr"#endif /* #if !defined(__VAXC) */ !#define MCHECK0302$M_MERA_CER 0x1"#define MCHECK0302$M_MERA_UCER 0x2"#define MCHECK0302$M_MERA_MULE 0x4"#define MCHECK0302$M_MERA_APER 0x8##define MCHECK0302$M_MERA_CERA 0x10##define MCHECK0302$M_MERA_CERB 0x20$#define MCHECK0302$M_MERA_FSTR 0x1C0%#define MCHECK0302$M_MERA_BNKER 0x200%#define MCHECK0302$M_MERA_UCERA 0x400%#define MCHECK0302$M_MERA_UCERB 0x800 typedef struct _mera { 8 __union {' unsigned int mcheck0302$l_mera; __struct {/ unsigned mcheck0302$v_mera_cer : 1;0 unsigned mcheck0302$v_mera_ucer : 1;0 unsigned mcheck0302$v_mera_mule : 1;0 unsigned mcheck0302$v_mera_aper : 1;0 unsigned mcheck0302$v_mera_cera : 1;0 unsigned mcheck0302$v_mera_cerb : 1;0 unsigned mcheck0302$v_mera_fstr : 3;1 unsigned mcheck0302$v_mera_bnker : 1;1 unsigned mchec 8k0302$v_mera_ucera : 1;1 unsigned mcheck0302$v_mera_ucerb : 1;2 unsigned mcheck0302$v_mera_fill1 : 20;% } mcheck0302$r_mera_bits;$ } mcheck0302$r_mera_overlay; } MERA; #if !defined(__VAXC)E#define mcheck0302$l_mera mcheck0302$r_mera_overlay.mcheck0302$l_merad#define mcheck0302$v_mera_cer mcheck0302$r_mera_overlay.mcheck0302$r_mera_bits.mcheck0302$v_mera_cerf#define mcheck0302$v_mera_ucer mcheck0302$r_mera_overlay.mcheck0302$r_mera_bits.mche8ck0302$v_mera_ucerf#define mcheck0302$v_mera_mule mcheck0302$r_mera_overlay.mcheck0302$r_mera_bits.mcheck0302$v_mera_mulef#define mcheck0302$v_mera_aper mcheck0302$r_mera_overlay.mcheck0302$r_mera_bits.mcheck0302$v_mera_aperf#define mcheck0302$v_mera_cera mcheck0302$r_mera_overlay.mcheck0302$r_mera_bits.mcheck0302$v_mera_ceraf#define mcheck0302$v_mera_cerb mcheck0302$r_mera_overlay.mcheck0302$r_mera_bits.mcheck0302$v_mera_cerbf#define mcheck0302$v_mera_fstr mcheck0302$r_mera_overlay.mcheck0302$r_ 8mera_bits.mcheck0302$v_mera_fstrh#define mcheck0302$v_mera_bnker mcheck0302$r_mera_overlay.mcheck0302$r_mera_bits.mcheck0302$v_mera_bnkerh#define mcheck0302$v_mera_ucera mcheck0302$r_mera_overlay.mcheck0302$r_mera_bits.mcheck0302$v_mera_ucerah#define mcheck0302$v_mera_ucerb mcheck0302$r_mera_overlay.mcheck0302$r_mera_bits.mcheck0302$v_mera_ucerb"#endif /* #if !defined(__VAXC) */ %#define MCHECK0302$M_MSYNDA_SYND 0xFF typedef struct _msynda { __union {) unsigned int mcheck08302$l_msynda; __struct {2 unsigned mcheck0302$v_msynda_synd : 8;4 unsigned mcheck0302$v_msynda_fill1 : 24;' } mcheck0302$r_msynda_bits;& } mcheck0302$r_msynda_overlay; } MSYNDA; #if !defined(__VAXC)K#define mcheck0302$l_msynda mcheck0302$r_msynda_overlay.mcheck0302$l_msyndan#define mcheck0302$v_msynda_synd mcheck0302$r_msynda_overlay.mcheck0302$r_msynda_bits.mcheck0302$v_msynda_synd"#endif /* #if !defined(__VAXC) */ "#define 8MCHECK0302$M_MDRA_FCBS 0x1"#define MCHECK0302$M_MDRA_DRDC 0x2"#define MCHECK0302$M_MDRA_DWDC 0x4"#define MCHECK0302$M_MDRA_BPAS 0x8##define MCHECK0302$M_MDRA_EXST 0x10##define MCHECK0302$M_MDRA_STPM 0x20##define MCHECK0302$M_MDRA_MODE 0x40##define MCHECK0302$M_MDRA_IGSB 0x80$#define MCHECK0302$M_MDRA_FRPE 0x100$#define MCHECK0302$M_MDRA_FCPE 0x200(#define MCHECK0302$M_MDRA_DCRD 0x8000000(#define MCHECK0302$M_MDRA_RFR 0x30000000*#define MCHECK0302$M_MDRA_BRFSH 0x40000000*#define MCHECK80302$M_MDRA_DRFSH 0x80000000 typedef struct _mdra { __union {' unsigned int mcheck0302$l_mdra; __struct {0 unsigned mcheck0302$v_mdra_fcbs : 1;0 unsigned mcheck0302$v_mdra_drdc : 1;0 unsigned mcheck0302$v_mdra_dwdc : 1;0 unsigned mcheck0302$v_mdra_bpas : 1;0 unsigned mcheck0302$v_mdra_exst : 1;0 unsigned mcheck0302$v_mdra_stpm : 1;0 unsigned mcheck0302$v_mdra_mode : 1;0 unsign8ed mcheck0302$v_mdra_igsb : 1;0 unsigned mcheck0302$v_mdra_frpe : 1;0 unsigned mcheck0302$v_mdra_fcpe : 1;2 unsigned mcheck0302$v_mdra_fill1 : 17;0 unsigned mcheck0302$v_mdra_dcrd : 1;/ unsigned mcheck0302$v_mdra_rfr : 2;1 unsigned mcheck0302$v_mdra_brfsh : 1;1 unsigned mcheck0302$v_mdra_drfsh : 1;% } mcheck0302$r_mdra_bits;$ } mcheck0302$r_mdra_overlay; } MDRA; #if !defined(__VAXC)E8#define mcheck0302$l_mdra mcheck0302$r_mdra_overlay.mcheck0302$l_mdraf#define mcheck0302$v_mdra_fcbs mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_fcbsf#define mcheck0302$v_mdra_drdc mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_drdcf#define mcheck0302$v_mdra_dwdc mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_dwdcf#define mcheck0302$v_mdra_bpas mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_bpasf#define mcheck03028$v_mdra_exst mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_exstf#define mcheck0302$v_mdra_stpm mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_stpmf#define mcheck0302$v_mdra_mode mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_modef#define mcheck0302$v_mdra_igsb mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_igsbf#define mcheck0302$v_mdra_frpe mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_frpef#def8ine mcheck0302$v_mdra_fcpe mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_fcpef#define mcheck0302$v_mdra_dcrd mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_dcrdd#define mcheck0302$v_mdra_rfr mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_rfrh#define mcheck0302$v_mdra_brfsh mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_mdra_brfshh#define mcheck0302$v_mdra_drfsh mcheck0302$r_mdra_overlay.mcheck0302$r_mdra_bits.mcheck0302$v_8mdra_drfsh"#endif /* #if !defined(__VAXC) */ ##define MCHECK0302$M_MCBSA_SCB 0xFF typedef struct _mcbsa { __union {( unsigned int mcheck0302$l_mcbsa; __struct {0 unsigned mcheck0302$v_mcbsa_scb : 8;3 unsigned mcheck0302$v_mcbsa_fill1 : 24;& } mcheck0302$r_mcbsa_bits;% } mcheck0302$r_mcbsa_overlay; } MCBSA; #if !defined(__VAXC)H#define mcheck0302$l_mcbsa mcheck0302$r_mcbsa_overlay.mcheck0302$l_mcbsah#define 8mcheck0302$v_mcbsa_scb mcheck0302$r_mcbsa_overlay.mcheck0302$r_mcbsa_bits.mcheck0302$v_mcbsa_scb"#endif /* #if !defined(__VAXC) */ !#define MCHECK0302$M_MERB_CER 0x1"#define MCHECK0302$M_MERB_UCER 0x2"#define MCHECK0302$M_MERB_MULE 0x4"#define MCHECK0302$M_MERB_APER 0x8 typedef struct _merb { __union {' unsigned int mcheck0302$l_merb; __struct {/ unsigned mcheck0302$v_merb_cer : 1;0 unsigned mcheck0302$v_merb_ucer : 1;0 unsi 8gned mcheck0302$v_merb_mule : 1;0 unsigned mcheck0302$v_merb_aper : 1;2 unsigned mcheck0302$v_merb_fill1 : 28;% } mcheck0302$r_merb_bits;$ } mcheck0302$r_merb_overlay; } MERB; #if !defined(__VAXC)E#define mcheck0302$l_merb mcheck0302$r_merb_overlay.mcheck0302$l_merbd#define mcheck0302$v_merb_cer mcheck0302$r_merb_overlay.mcheck0302$r_merb_bits.mcheck0302$v_merb_cerf#define mcheck0302$v_merb_ucer mcheck0302$r_merb_overlay.mcheck0302$r_merb_bit 8s.mcheck0302$v_merb_ucerf#define mcheck0302$v_merb_mule mcheck0302$r_merb_overlay.mcheck0302$r_merb_bits.mcheck0302$v_merb_mulef#define mcheck0302$v_merb_aper mcheck0302$r_merb_overlay.mcheck0302$r_merb_bits.mcheck0302$v_merb_aper"#endif /* #if !defined(__VAXC) */ %#define MCHECK0302$M_MSYNDB_SYND 0xFF typedef struct _msyndb { __union {) unsigned int mcheck0302$l_msyndb; __struct {2 unsigned mcheck0302$v_msyndb_synd : 8;4 unsigned mcheck08302$v_msyndb_fill1 : 24;' } mcheck0302$r_msyndb_bits;& } mcheck0302$r_msyndb_overlay; } MSYNDB; #if !defined(__VAXC)K#define mcheck0302$l_msyndb mcheck0302$r_msyndb_overlay.mcheck0302$l_msyndbn#define mcheck0302$v_msyndb_synd mcheck0302$r_msyndb_overlay.mcheck0302$r_msyndb_bits.mcheck0302$v_msyndb_synd"#endif /* #if !defined(__VAXC) */ "#define MCHECK0302$M_MDRB_FCBS 0x1"#define MCHECK0302$M_MDRB_DRDC 0x2"#define MCHECK0302$M_MDRB_DWDC 0x4"#define MCHECK03028$M_MDRB_BPAS 0x8##define MCHECK0302$M_MDRB_EXST 0x10##define MCHECK0302$M_MDRB_STPM 0x20##define MCHECK0302$M_MDRB_MODE 0x40##define MCHECK0302$M_MDRB_IGSB 0x80 typedef struct _mdrb { __union {' unsigned int mcheck0302$l_mdrb; __struct {0 unsigned mcheck0302$v_mdrb_fcbs : 1;0 unsigned mcheck0302$v_mdrb_drdc : 1;0 unsigned mcheck0302$v_mdrb_dwdc : 1;0 unsigned mcheck0302$v_mdrb_bpas : 1;0 unsigned mcheck0 8302$v_mdrb_exst : 1;0 unsigned mcheck0302$v_mdrb_stpm : 1;0 unsigned mcheck0302$v_mdrb_mode : 1;0 unsigned mcheck0302$v_mdrb_igsb : 1;2 unsigned mcheck0302$v_mdrb_fill1 : 24;% } mcheck0302$r_mdrb_bits;$ } mcheck0302$r_mdrb_overlay; } MDRB; #if !defined(__VAXC)E#define mcheck0302$l_mdrb mcheck0302$r_mdrb_overlay.mcheck0302$l_mdrbf#define mcheck0302$v_mdrb_fcbs mcheck0302$r_mdrb_overlay.mcheck0302$r_mdrb_bits.mcheck0302$v8_mdrb_fcbsf#define mcheck0302$v_mdrb_drdc mcheck0302$r_mdrb_overlay.mcheck0302$r_mdrb_bits.mcheck0302$v_mdrb_drdcf#define mcheck0302$v_mdrb_dwdc mcheck0302$r_mdrb_overlay.mcheck0302$r_mdrb_bits.mcheck0302$v_mdrb_dwdcf#define mcheck0302$v_mdrb_bpas mcheck0302$r_mdrb_overlay.mcheck0302$r_mdrb_bits.mcheck0302$v_mdrb_bpasf#define mcheck0302$v_mdrb_exst mcheck0302$r_mdrb_overlay.mcheck0302$r_mdrb_bits.mcheck0302$v_mdrb_exstf#define mcheck0302$v_mdrb_stpm mcheck0302$r_mdrb_overlay.mcheck0302$r_mdrb_bit 8s.mcheck0302$v_mdrb_stpmf#define mcheck0302$v_mdrb_mode mcheck0302$r_mdrb_overlay.mcheck0302$r_mdrb_bits.mcheck0302$v_mdrb_modef#define mcheck0302$v_mdrb_igsb mcheck0302$r_mdrb_overlay.mcheck0302$r_mdrb_bits.mcheck0302$v_mdrb_igsb"#endif /* #if !defined(__VAXC) */ ##define MCHECK0302$M_MCBSB_SCB 0xFF typedef struct _mcbsb { __union {( unsigned int mcheck0302$l_mcbsb; __struct {0 unsigned mcheck0302$v_mcbsb_scb : 8;3 unsigned mcheck0302$v_ 8mcbsb_fill1 : 24;& } mcheck0302$r_mcbsb_bits;% } mcheck0302$r_mcbsb_overlay; } MCBSB; #if !defined(__VAXC)H#define mcheck0302$l_mcbsb mcheck0302$r_mcbsb_overlay.mcheck0302$l_mcbsbh#define mcheck0302$v_mcbsb_scb mcheck0302$r_mcbsb_overlay.mcheck0302$r_mcbsb_bits.mcheck0302$v_mcbsb_scb"#endif /* #if !defined(__VAXC) */ "#define CPU0302$K_ECC_MAX_COUNT 32N/* Note that %xB2D05E00 equals 5 minutes in 100 nanosecond units */+#define CPU0302$K_ECC_THRESHOL8D -1294967296 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard ##endif /* __MCHECK0302DEF_LOADED */ ww (}[UM/***************************************************************************/M/** g8MCBUSDEF8 MCHECK0302DEF8jMCHKDEF8MCJDEF8 MDBOOTDEF 9MFADEF`DMGT$C_ROUTINES9MGTDEF MGT_MACROS9MMAPDEF9MMECBDEF9*MMGDEF9 MMG_CONSTANTS MMG_FUNCTIONSiL MMG_ROUTINES9MODDEF9MONDEF:MPDEVDEF>MPDEV_ROUTINES:MPMDEF:MPWDEF:MSCPDEF;MSLGDEF;MTLDEF;MTXDEFR MT_ROUTINES;MULTIDEF;MUTEXDEF;MVLDEF;nMVMSLDEF;NAFDEFOSLVMS8 **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **8/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********************8******************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:14 by OpenVMS SDL V3.7 */G/* Source: 09-JUN-1993 15:33:59 $1$DGA8345:[LIB_H.SRC]MCHKDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MCHKDEF ***/#ifndef __MCHKDEF_8LOADED#define __MCHKDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#def8ine __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* MACHINE CHECK ERROR RECOVERY BLOCK 8MASK BIT DEFFINITIONS */N/* BITS USED TO FILTER AND TEST FOR ERROR TYPES */N/*- */#define MCHK$M_LOG 0x1#define MCHK$M_MCK 0x2#define MCHK$M_NEXM 0x4#define MCHK$M_SYSLOA 0x8N#define MCHK$S_MCHKBITDEF 1 /* Old size name - synonym */ typedef struct _mchkbit { __struct {N unsigned mchk$v_log : 1; /* Inhibit error log for the err 8or */N unsigned mchk$v_mck : 1; /* Protect against machine checks */R unsigned mchk$v_nexm : 1; /* Protect against non-existent memory */X unsigned mchk$v_sysloa : 1; /* Protect against recursive entry to handler */$ unsigned mchk$v_fill_0_ : 4; } mchk$r_mchkdef_bits; } MCHKBIT; #if !defined(__VAXC)1#define mchk$v_log mchk$r_mchkdef_bits.mchk$v_log1#define mchk$v_mck mchk$r_mchkdef_bits.mchk$v_mck3#define mchk$v_nexm mchk$r_m 8chkdef_bits.mchk$v_nexm7#define mchk$v_sysloa mchk$r_mchkdef_bits.mchk$v_sysloa"#endif /* #if !defined(__VAXC) */ N/* Offset to state saved on the stack by EXE$MCHECK_PROTECT */N#define MCHK$K_LEN 224 /* Length of structure */N#define MCHK$S_MCHKSAVDEF 224 /* Old size name - synonym */ typedef struct _mchksav {' unsigned __int64 mchk$iq_saved_ipl;+ unsigned __int64 mchk$iq_saved_mask_sp;' unsigned __int64 m 8chk$iq_saved_r02;' unsigned __int64 mchk$iq_saved_r03;' unsigned __int64 mchk$iq_saved_r04;' unsigned __int64 mchk$iq_saved_r05;' unsigned __int64 mchk$iq_saved_r06;' unsigned __int64 mchk$iq_saved_r07;' unsigned __int64 mchk$iq_saved_r08;' unsigned __int64 mchk$iq_saved_r09;' unsigned __int64 mchk$iq_saved_r10;' unsigned __int64 mchk$iq_saved_r11;' unsigned __int64 mchk$iq_saved_r12;' unsigned __int64 mchk$iq_saved_r13;' unsigned __int64 mch 8k$iq_saved_r14;' unsigned __int64 mchk$iq_saved_r15;' unsigned __int64 mchk$iq_saved_r16;' unsigned __int64 mchk$iq_saved_r17;' unsigned __int64 mchk$iq_saved_r26;' unsigned __int64 mchk$iq_saved_r29;' unsigned __int64 mchk$iq_saved_f02;' unsigned __int64 mchk$iq_saved_f03;' unsigned __int64 mchk$iq_saved_f04;' unsigned __int64 mchk$iq_saved_f05;' unsigned __int64 mchk$iq_saved_f06;' unsigned __int64 mchk$iq_saved_f07;' unsigned __int64 mchk$8iq_saved_f08;' unsigned __int64 mchk$iq_saved_f09; } MCHKSAV; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MCHKDEF_LOADED */ wwP}[UM/***************************************************************************/8M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** 8 **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 8 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:15 by OpenVMS SDL V3.7 */F/* Source: 01-FEB-1994 11:48:34 $1$DGA8345:[LIB_H.SRC]MCJDEF.SDL;1 *//******************************************************************************************************************************* 8*//*** MODULE $MCJDEF ***/#ifndef __MCJDEF_LOADED#define __MCJDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif8 #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* 8 */N/* Magic Cookie Jar (to contain platform independent mapping IOHANDLES) */N/* */ #define MCJ$K_HEADER_LEN 16  9#ifdef __cplusplus /* Define structure prototypes */ struct _idb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment 8#endiftypedef struct _mcj {#pragma __nomember_alignmentN struct _idb *mcj$ps_idb; /* back pointer to IDB */N unsigned int mcj$l_crumb_count; /* number of handles MCJ will hold */N unsigned short int mcj$w_size; /* size of MCJ */N unsigned char mcj$b_type; /* DYN$C_MISC */N unsigned char mcj$b_subtype; /* DYN$C_MCJ */ int mcj$l_spare; __union {N 8 unsigned __int64 mcj$q_cookies [2]; /* Minimum sized list */U unsigned __int64 mcj$q_entries [2]; /* minimum sized list (preferred name) */ } mcj$r_crummy_overlay; } MCJ; #if !defined(__VAXC)8#define mcj$q_cookies mcj$r_crummy_overlay.mcj$q_cookies8#define mcj$q_entries mcj$r_crummy_overlay.mcj$q_entries"#endif /* #if !defined(__VAXC) */ #define MCJ$K_LENGTH 32 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined when8ever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MCJDEF_LOADED */ ww~[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** 8licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licen8sed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************* 8*************************************************************************/=/* Created: 7-Oct-2024 15:22:17 by OpenVMS SDL V3.7 */I/* Source: 12-OCT-2021 13:20:46 $1$DGA8345:[LIB_H.SRC]MDBOOTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MDBOOTDEF ***/#ifndef __MDBOOTDEF_LOADED#define __MDBOOTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard featur9es */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __opti9onal_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _mdboot_extent {9#pragma __nomember_alignmentf unsigned int mdboot$l_blocks; /* Size (blocks) of an extent of memory disk container file */b unsigned __int64 mdboot$q_start; /* Start LBN of an extent of memory disk container file */ } MDBOOT_EXTENT;N#define MDBOOT$K_VMS_SIGNATURE 609439062 /* The string "VMS$" */Y#define MDBOOT$K_MAJOR_ID 2 /* One or both of these need to be updated ... */Y#define MDBOOT$K_MINOR_ID 0 /* ... if the layout of this structure 9 changes */a#define MDBOOT$K_MAX_EXTENTS 24 /* The maximum number of extents allowed in SYS$MD.DSK */R#define MDBOOT$K_BLOCK_LENGTH 512 /* If this isn't 512, we're in trouble! */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mdboot {#pragma __nomember_alignmentr unsigned char mdboot$x_fat16_fat32_bpb [90]; /* See [E9FI]MSFATDEF.SDL: size of FATBPB before MSFAT$X_JUNQUE */O short int mdboot$x_filler1; /* To make our data longword aligned */ __union {m unsigned char mdboot$t_mdboot_data [400]; /* This is the space we can use for the memory disk data */ __struct {S unsigned int mdboot$l_signature; /* The identifying signature "VMS$" */j unsigned int mdboot$l_length; /* Length of MDBOOT data from SIGNATURE to CHECKSUM inclusive */ __union {9] unsigned int mdboot$l_version; /* Version of structure (Major & Minor IDs) */ __struct {W unsigned short int mdboot$w_minor_id; /* Minor ID in low 16 bits */X unsigned short int mdboot$w_major_id; /* Major ID in high 16 bits */) } mdboot$r_majmin_id;) } mdboot$r_version_union;O char mdboot$t_sysdisk_label [12]; /* Volume label of system disk */O char mdboot$t_me9mdisk_label [12]; /* Volume label of memory disk */o unsigned int mdboot$l_memdisk_blocks; /* Size (in 512-byte blocks) of memory disk container file */s unsigned int mdboot$l_bootfile_blocks; /* Size (blocks) of SYSBOOT.EXE in memory disk container file */n unsigned int mdboot$l_bootfile_start; /* Start LBN of SYSBOOT.EXE in memory disk container file */N MDBOOT_EXTENT mdboot$t_extents [24]; /* 24 sets of blocks+start */i unsigned int mdb 9oot$l_checksum; /* Negative of sum of all longwords from SIGNATURE to here */N unsigned char mdboot$t_spare [60]; /* For future use */# } mdboot$r_mdboot_info; } mdboot$r_mdboot_union;S short int mdboot$x_filler2; /* To align to the end of MSFAT$X_JUNQUE */p unsigned char mdboot$x_eficp_markers [18]; /* See [EFI]MSFATDEF.SDL: size of markers after MSFAT$X_JUNQUE */ } MDBOOT; #if !defined(__VAXC)G#define mdboot$t_mdboot_data mdb9oot$r_mdboot_union.mdboot$t_mdboot_dataG#define mdboot$r_mdboot_info mdboot$r_mdboot_union.mdboot$r_mdboot_infoB#define mdboot$l_signature mdboot$r_mdboot_info.mdboot$l_signature<#define mdboot$l_length mdboot$r_mdboot_info.mdboot$l_lengthJ#define mdboot$r_version_union mdboot$r_mdboot_info.mdboot$r_version_union@#define mdboot$l_version mdboot$r_version_union.mdboot$l_versionD#define mdboot$r_majmin_id mdboot$r_version_union.mdboot$r_majmin_id>#define mdboot$w_minor_id mdboot$r_majmin_id.mdb 9oot$w_minor_id>#define mdboot$w_major_id mdboot$r_majmin_id.mdboot$w_major_idJ#define mdboot$t_sysdisk_label mdboot$r_mdboot_info.mdboot$t_sysdisk_labelJ#define mdboot$t_memdisk_label mdboot$r_mdboot_info.mdboot$t_memdisk_labelL#define mdboot$l_memdisk_blocks mdboot$r_mdboot_info.mdboot$l_memdisk_blocksN#define mdboot$l_bootfile_blocks mdboot$r_mdboot_info.mdboot$l_bootfile_blocksL#define mdboot$l_bootfile_start mdboot$r_mdboot_info.mdboot$l_bootfile_start>#define mdboot$t_extents mdboot$r_mdbo 9ot_info.mdboot$t_extents@#define mdboot$l_checksum mdboot$r_mdboot_info.mdboot$l_checksum:#define mdboot$t_spare mdboot$r_mdboot_info.mdboot$t_spare"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MDBOOTDE 9F_LOADED */ ww~[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE.  9 **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 9 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:18 by OpenVMS SDL V3.7 */F/* Source: 19-APR-1993 14:41:35 $1$DGA8345:[LIB_H.SRC]MFADEF.SDL;1 *//******* 9*************************************************************************************************************************//*** MODULE $MFADEF ***/#ifndef __MFADEF_LOADED#define __MFADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined re9quired ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#d 9efine __union variant_union#endif#endif N/*+ */N/* MFA - MESSAGE FILE ARRAY */N/* */N/* There is one Message File Array on any system. The array is a set of */N/* pointers to message files, both SYSMSG and file used by exec-lets. */N/*- 9 */N#define MFA$K_LENGTH 8 /* Length of MFA header */N#define MFA$C_LENGTH 8 /* Length of MFA header */#define MFA$S_MFADEF 12 typedef struct _mfa {N unsigned short int mfa$w_size; /* Size of the array in bytes */N unsigned short int mfa$w_filcnt; /* Number of file pointers stored */R unsigned short int mfa$w_bugcnt; /* Count of events that shouldnt happen */O unsigned short int m9fa$w_rsrvd; /* Reserved, lonword align structure */N unsigned int mfa$l_ptr_base; /* Offset to first address */ } MFA; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MFADEF_LOADED */ ww [UM/***9************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-P9ackard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. 9 **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:18 by OpenVMS SDL V3.7 */F/* Source: 12-FEB-2022 06:18:59 $1$DGA8345:[LIB_H.SRC]MGTDEF.SDL;1 *//***************************************************** 9***************************************************************************//*** MODULE $MGTDEF ***/#ifndef __MGTDEF_LOADED#define __MGTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer9_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif9 N/* */N/* MGTHDR -- V1 Management header for managed object packets. */N/* */N#define MGTHDR$K_ACT_HDR_MAJOR 1 /* Major Rev. */N#define MGTHDR$K_ACT_HDR_MINOR 1 /* Minor Rev. */N#define MGTHDR$K_RSP_HDR_MAJOR 1 /* Major Rev. */N#define MGTHDR$K_RSP_H9DR_MINOR 1 /* Minor Rev. */N#define MGTHDR$K_REG_REQ_MAJOR 1 /* Major Rev. */N#define MGTHDR$K_REG_REQ_MINOR 2 /* Minor Rev. */N#define MGTHDR$K_REG_RSP_MAJOR 1 /* Major Rev. */N#define MGTHDR$K_REG_RSP_MINOR 1 /* Minor Rev. */N#define MGTHDR$K_DEREG_REQ_MAJOR 1 /* Major Rev. */N#define MGTHDR$K_DEREG_REQ_MINOR 1 /* Minor 9 Rev. */N#define MGTHDR$K_DEREG_RSP_MAJOR 1 /* Major Rev. */N#define MGTHDR$K_DEREG_RSP_MINOR 1 /* Minor Rev. */N#define MGTHDR$K_RIGHTS_MAJOR 1 /* Major Rev. */N#define MGTHDR$K_RIGHTS_MINOR 1 /* Minor Rev. */#define MGTHDR$M_V 0x1#define MGTHDR$M_MORE 0x2!#define MGTHDR$M_CONTINUATION 0x4N#define MGTHDR$K_BASE_HDR_LENGTH 16 /* Base Header length 9 */N#define MGTHDR$C_BASE_HDR_LENGTH 16 /* Old VAX style length */N#define MGTHDR$K_ACT_HDR_V1_1_LEN 24 /* V1.1 Action header length */N#define MGTHDR$C_ACT_HDR_V1_1_LEN 24 /* V1.1 Action header length */N#define MGTHDR$K_ACT_HDR_LEN 24 /* Action header length */N#define MGTHDR$C_ACT_HDR_LEN 24 /* Old VAX style length */S#define MGTHDR$R_ACT_PAR 24 /* Beginning of Action parameters block */N#defin9e MGTHDR$K_ACT_PAR_V1_1_LEN 0 /* V1.1 Action parameter length */N#define MGTHDR$C_ACT_PAR_V1_1_LEN 0 /* V1.1 Action parameter length */N#define MGTHDR$K_ACT_PAR_LEN 0 /* Action parameter length */N#define MGTHDR$C_ACT_PAR_LEN 0 /* Action parameter length */N#define MGTHDR$K_ACT_V1_1_LEN 24 /* V1.1 Action length */N#define MGTHDR$C_ACT_V1_1_LEN 24 /* V1.1 Action length */N#define MGTHDR$K_ACT_LEN 24 9 /* Action length */N#define MGTHDR$C_ACT_LEN 24 /* Action length */N#define MGTHDR$K_RSP_HDR_V1_1_LEN 24 /* V1.1 Response header length */N#define MGTHDR$C_RSP_HDR_V1_1_LEN 24 /* V1.1 Response header length */N#define MGTHDR$K_RSP_HDR_LEN 24 /* Response header length */N#define MGTHDR$C_RSP_HDR_LEN 24 /* Old VAX style length */U#define MGTHDR$R_RSP_PAR 24 /* Beginning of Re9sponse parameters block */N#define MGTHDR$K_RSP_PAR_V1_1_LEN 0 /* V1.1 Response parameter length */N#define MGTHDR$C_RSP_PAR_V1_1_LEN 0 /* V1.1 Response parameter length */N#define MGTHDR$K_RSP_PAR_LEN 0 /* Response parameter length */N#define MGTHDR$C_RSP_PAR_LEN 0 /* Response parameter length */N#define MGTHDR$K_RSP_V1_1_LEN 24 /* V1.1 Response length */N#define MGTHDR$C_RSP_V1_1_LEN 24 /* V1.1 Response length 9*/N#define MGTHDR$K_RSP_LEN 24 /* Response length */N#define MGTHDR$C_RSP_LEN 24 /* Response length */N#define MGTHDR$K_CONT_HDR_V1_1_LEN 24 /* V1.1 Continuation header length */N#define MGTHDR$C_CONT_HDR_V1_1_LEN 24 /* V1.1 Continuation header length */N#define MGTHDR$K_CONT_HDR_LEN 24 /* Continuation header length */N#define MGTHDR$C_CONT_HDR_LEN 24 /* Old VAX style length */Y#define MGTHDR$R_CONT_ 9PAR 24 /* Beginning of Continuation parameters block */P#define MGTHDR$K_CONT_PAR_V1_1_LEN 0 /* V1.1 Continuation parameter length */P#define MGTHDR$C_CONT_PAR_V1_1_LEN 0 /* V1.1 Continuation parameter length */N#define MGTHDR$K_CONT_PAR_LEN 0 /* Continuation parameter length */N#define MGTHDR$C_CONT_PAR_LEN 0 /* Continuation parameter length */N#define MGTHDR$K_CONT_V1_1_LEN 24 /* V1.1 Continuation length */N#define MGTHDR$C_CONT_V1_1_LEN 2!94 /* V1.1 Continuation length */N#define MGTHDR$K_CONT_LEN 24 /* Continuation length */N#define MGTHDR$C_CONT_LEN 24 /* Continuation length */N#define MGTHDR$K_EVENT_HDR_V1_1_LEN 24 /* V1.1 Event header length */N#define MGTHDR$C_EVENT_HDR_V1_1_LEN 24 /* V1.1 Event header length */N#define MGTHDR$K_EVENT_HDR_LEN 24 /* Event header length */N#define MGTHDR$C_EVENT_HDR_LEN 24 /* Old VAX style l"9ength */R#define MGTHDR$R_EVENT_PAR 24 /* Beginning of Event parameters block */N#define MGTHDR$K_EVENT_PAR_V1_1_LEN 0 /* V1.1 Event parameter length */N#define MGTHDR$C_EVENT_PAR_V1_1_LEN 0 /* V1.1 Event parameter length */N#define MGTHDR$K_EVENT_PAR_LEN 0 /* Event parameter length */N#define MGTHDR$C_EVENT_PAR_LEN 0 /* Event parameter length */N#define MGTHDR$K_EVENT_V1_1_LEN 24 /* V1.1 Event length */N#9#define MGTHDR$C_EVENT_V1_1_LEN 24 /* V1.1 Event length */N#define MGTHDR$K_EVENT_LEN 24 /* Event length */N#define MGTHDR$C_EVENT_LEN 24 /* Event length */Z#define MGTHDR$K_DEREG_REQ_HDR_V1_1_LEN 24 /* V1.1 Deregistration request header length */Z#define MGTHDR$C_DEREG_REQ_HDR_V1_1_LEN 24 /* V1.1 Deregistration request header length */R#define MGTHDR$K_DEREG_REQ_HDR_LEN 24 /* Deregistration request header length */$9R#define MGTHDR$C_DEREG_REQ_HDR_LEN 24 /* Deregistration request header length */V#define MGTHDR$R_DEREG_REQ_PAR 24 /* Deregistration request parameters block */\#define MGTHDR$K_DEREG_REQ_PAR_V1_1_LEN 0 /* V1.1 Deregistration request parameter length */\#define MGTHDR$C_DEREG_REQ_PAR_V1_1_LEN 0 /* V1.1 Deregistration request parameter length */U#define MGTHDR$K_DEREG_REQ_PAR_LEN 0 /* Deregistration request parameter length */U#define MGTHDR$C_DEREG_REQ_PAR_LEN 0 /* Deregistratio%9n request parameter length */P#define MGTHDR$K_DEREG_REQ_V1_1_LEN 24 /* V1.1 Deregistration request length */P#define MGTHDR$C_DEREG_REQ_V1_1_LEN 24 /* V1.1 Deregistration request length */N#define MGTHDR$K_DEREG_REQ_LEN 24 /* Deregistration request length */N#define MGTHDR$C_DEREG_REQ_LEN 24 /* Deregistration request length */[#define MGTHDR$K_DEREG_RSP_HDR_V1_1_LEN 24 /* V1.1 Deregistration response header length */[#define MGTHDR$C_DEREG_RSP_HDR_V1_1_LEN 24 /* V1.1 Dereg&9istration response header length */S#define MGTHDR$K_DEREG_RSP_HDR_LEN 24 /* Deregistration response header length */S#define MGTHDR$C_DEREG_RSP_HDR_LEN 24 /* Deregistration response header length */S#define MGTHDR$R_DEREG_RSP_OUTPUT 24 /* Deregistration response output block */Z#define MGTHDR$K_DEREG_RSP_OUT_V1_1_LEN 0 /* V1.1 Deregistration response output length */Z#define MGTHDR$C_DEREG_RSP_OUT_V1_1_LEN 0 /* V1.1 Deregistration response output length */S#define MGTHDR$K_DEREG_RSP'9_OUT_LEN 0 /* Deregistration response output length */S#define MGTHDR$C_DEREG_RSP_OUT_LEN 0 /* Deregistration response output length */Q#define MGTHDR$K_DEREG_RSP_V1_1_LEN 24 /* V1.1 Deregistration response length */Q#define MGTHDR$C_DEREG_RSP_V1_1_LEN 24 /* V1.1 Deregistration response length */N#define MGTHDR$K_DEREG_RSP_LEN 24 /* Deregistration response length */N#define MGTHDR$C_DEREG_RSP_LEN 24 /* Deregistration response length */N#define MGTHDR$K_RIGHTS_HDR_V1_1 (9_LEN 24 /* V1.1 Access Rights header length */N#define MGTHDR$C_RIGHTS_HDR_V1_1_LEN 24 /* V1.1 Access Rights header length */N#define MGTHDR$K_RIGHTS_HDR_LEN 24 /* Access Rights header length */N#define MGTHDR$C_RIGHTS_HDR_LEN 24 /* Access Rights header length */N#define MGTHDR$R_RIGHTS_PAR 24 /* Access Rights parameters block */ #define MGTHDR$M_READ_ACCESS 0x1!#define MGTHDR$M_WRITE_ACCESS 0x2##define MGTHDR$M_CONTROL_ACCESS 0x4Q#define MGTHDR$K_RIGHTS_PAR_V1)9_1_LEN 8 /* V1.1 Access Rights parameter length */Q#define MGTHDR$C_RIGHTS_PAR_V1_1_LEN 8 /* V1.1 Access Rights parameter length */N#define MGTHDR$K_RIGHTS_PAR_LEN 8 /* Access Rights parameter length */N#define MGTHDR$C_RIGHTS_PAR_LEN 8 /* Access Rights parameter length */N#define MGTHDR$K_RIGHTS_V1_1_LEN 32 /* V1.1 Access Rights length */N#define MGTHDR$C_RIGHTS_V1_1_LEN 32 /* V1.1 Access Rights length */N#define MGTHDR$K_RIGHTS_LEN 32 /* Acces*9s Rights length */N#define MGTHDR$C_RIGHTS_LEN 32 /* Access Rights length */V#define MGTHDR$K_REG_REQ_HDR_V1_1_LEN 24 /* V1.1 Registration request header length */V#define MGTHDR$C_REG_REQ_HDR_V1_1_LEN 24 /* V1.1 Registration request header length */V#define MGTHDR$K_REG_REQ_HDR_V1_2_LEN 24 /* V1.2 Registration request header length */V#define MGTHDR$C_REG_REQ_HDR_V1_2_LEN 24 /* V1.2 Registration request header length */P#define MGTHDR$K_REG_REQ_HDR_LEN 24 /*+9 Registration request header length */P#define MGTHDR$C_REG_REQ_HDR_LEN 24 /* Registration request header length */T#define MGTHDR$R_REG_REQ_PAR 24 /* Registration request parameters block */Y#define MGTHDR$K_REG_REQ_PAR_V1_1_LEN 56 /* V1.1 Registration request parameter length */Y#define MGTHDR$C_REG_REQ_PAR_V1_1_LEN 56 /* V1.1 Registration request parameter length */Y#define MGTHDR$K_REG_REQ_PAR_V1_2_LEN 56 /* V1.1 Registration request parameter length */Y#define MGTHDR$C_REG_R,9EQ_PAR_V1_2_LEN 56 /* V1.1 Registration request parameter length */S#define MGTHDR$K_REG_REQ_PAR_LEN 56 /* Registration request parameter length */S#define MGTHDR$C_REG_REQ_PAR_LEN 56 /* Registration request parameter length */N#define MGTHDR$K_REG_REQ_V1_1_LEN 80 /* V1.1 Registration request length */N#define MGTHDR$C_REG_REQ_V1_1_LEN 80 /* V1.1 Registration request length */N#define MGTHDR$K_REG_REQ_V1_2_LEN 80 /* V1.1 Registration request length */N#define MGTHDR$C_REG_REQ-9_V1_2_LEN 80 /* V1.1 Registration request length */N#define MGTHDR$K_REG_REQ_LEN 80 /* Registration request length */N#define MGTHDR$C_REG_REQ_LEN 80 /* Registration request length */W#define MGTHDR$K_REG_RSP_HDR_V1_1_LEN 24 /* V1.1 Registration response header length */W#define MGTHDR$C_REG_RSP_HDR_V1_1_LEN 24 /* V1.1 Registration response header length */Q#define MGTHDR$K_REG_RSP_HDR_LEN 24 /* Registration response header length */Q#define MGTHDR$C_REG_RSP_H.9DR_LEN 24 /* Registration response header length */Q#define MGTHDR$R_REG_RSP_OUTPUT 24 /* Registration response output block */W#define MGTHDR$K_REG_RSP_OUT_V1_1_LEN 16 /* V1.1 Registration response output length */W#define MGTHDR$C_REG_RSP_OUT_V1_1_LEN 16 /* V1.1 Registration response output length */Q#define MGTHDR$K_REG_RSP_OUT_LEN 16 /* Registration response output length */Q#define MGTHDR$C_REG_RSP_OUT_LEN 16 /* Registration response output length */O#define MGTHDR$K /9_REG_RSP_V1_1_LEN 40 /* V1.1 Registration response length */O#define MGTHDR$C_REG_RSP_V1_1_LEN 40 /* V1.1 Registration response length */N#define MGTHDR$K_REG_RSP_LEN 40 /* Registration response length */N#define MGTHDR$C_REG_RSP_LEN 40 /* Registration response length */ typedef struct _mgthdr { __union {N unsigned char mgthdr$b_hdr_len; /* Header Len in bytes */ __struct {) unsigned mgthdr$v_rsvd_1 : 3;V 09 unsigned mgthdr$v_hdr_len_qw : 5; /* Length of data header in quadwords */N/* Also offset to object specific data */# } mgthdr$r_hdr1_fields;# } mgthdr$r_hdr_len_overlay; __union {N unsigned char mgthdr$b_flags; /* Header flags */ __struct {N unsigned mgthdr$v_v : 1; /* Data Header is valid */N unsigned mgthdr$v_more : 1; /* Another mgt data header fol 19lows */Z unsigned mgthdr$v_continuation : 1; /* Header for continuation data follows */, unsigned mgthdr$v_flags_mbz : 5;" } mgthdr$r_flags_bits;! } mgthdr$r_flags_overlay;N unsigned char mgthdr$b_hdr_minor; /* Header Minor Revision */N unsigned char mgthdr$b_hdr_major; /* Header Major Revision */N unsigned char mgthdr$b_mgt_func; /* Record type code: */N/* (see MGT_FUNC constant section for codes) 29 */N unsigned char mgthdr$b_rsp_status; /* Action: SBZ */N/* Response: status of performing action. */a unsigned short int mgthdr$w_par_len; /* Total length of REC_TYP records following in bytes */S unsigned int mgthdr$l_obj_handle; /* Registration Handle of destination MO */P unsigned int mgthdr$l_src_obj_handle; /* Registration Handle of source MO */ __union {N/* Action, Response, and inf39o Headers */N __struct { /* Action & Response headers */N unsigned char mgthdr$b_action; /* Managed Object action codes */R unsigned char mgthdr$b_num_par_recs; /* Number of Parameter Records */Y unsigned char mgthdr$b_par_minor; /* Minor Rev. of object specific params. */` unsigned char mgthdr$b_par_major; /* Major Rev. of object specific action_params. */ __union 49 {c unsigned int mgthdr$l_action_seq; /* Mgt station assigned action sequence number */[ unsigned int mgthdr$l_action_ctx; /* Mgt station assigned action context */2 } mgthdr$r_action_seq_ctx_overlay;] __union { /* All structures need at least one member. Until */N/* the time that a structure has a member, it is defined */N/* before the structures that have members so that the */59N/* "." operand has the right value. */ __struct { __union {j unsigned int mgthdr$l_access_rights; /* Security access rights of the requestor */# __struct {d unsigned mgthdr$v_read_access : 1; /* Able to request monitoring data */h unsigned mgthdr$v_write_access : 1; /* Able to request execution of fixes */o 69 unsigned mgthdr$v_control_access : 1; /* Able to configure/change Managed Object */8 unsigned mgthdr$v_rsvd : 29;3 } mgthdr$r_access_bits;2 } mgthdr$r_access_overlay;P unsigned int mgthdr$l_src_obj_type; /* Source Object type */N/* (see SRC_OBJ_TYPE constant section for codes) */. } mgthdr$r_access_rts_hdr; __struct 79{Z unsigned char mgthdr$t_obj_name [32]; /* Node unique ASCIZ obj name */X unsigned char mgthdr$b_obj_minor; /* Managed Object minor version */X unsigned char mgthdr$b_obj_major; /* Managed Object major version */O char mgthdr$t_obj_fill [6]; /* Fill to quadword boundary */ __union {# __struct {N/* Kernel Mode objects: */89` unsigned __int64 mgthdr$q_action_addr; /* $MGT_ACTION routine for */N/* kernel mode objects */Z unsigned __int64 mgthdr$q_req_ctx; /* Request context value */; } mgthdr$r_reg_req_kernel_info;# __struct {N/* Process objects: */N/* MGT_AST information for process mode objects 99 */O unsigned int mgthdr$l_ast_epid; /* EPID for ASTs */a unsigned int mgthdr$l_ast_rsvd; /* Reserved for quadword alignment */9 } mgthdr$r_reg_req_user_info;# __struct {N/* Process Data Analyzers: */N/* DA_AST information for process mode data analyzers */R unsigned int:9 mgthdr$l_da_ast_epid; /* EPID for ASTs */d unsigned int mgthdr$l_da_ast_rsvd; /* Reserved for quadword alignment */U unsigned char mgthdr$t_da_password [8]; /* AM Password */= } mgthdr$r_reg_req_local_da_info;= } mgthdr$r_reg_req_kernel_user_da_ov;0 } mgthdr$r_reg_req_par_data; __struct {W unsigned char mgthdr$b_rm_obj_minor; /* RMDr;9iver's minor version */W unsigned char mgthdr$b_rm_obj_major; /* RMDriver's major version */R char mgthdr$t_rm_obj_fill [6]; /* Fill to quadword boundary */ __union {# __struct {N/* Kernel Mode objects: */t unsigned __int64 mgthdr$a_rm_mgt_action_addr; /* RMDriver's Management Action routine */N/* kernel mode objects <9 */; } mgthdr$r_reg_rsp_kernel_info;= } mgthdr$r_reg_rsp_kernel_user_da_ov;3 } mgthdr$r_reg_rsp_output_data;' } mgthdr$r_par_overlay;% } mgthdr$r_mgtactrspinfo;& } mgthdr$r_actrspinfo_overlay; } MGTHDR; #if !defined(__VAXC)B#define mgthdr$b_hdr_len mgthdr$r_hdr_len_overlay.mgthdr$b_hdr_len]#define mgthdr$v_hdr_len_qw mgthdr$r_hdr_len_overlay=9.mgthdr$r_hdr1_fields.mgthdr$v_hdr_len_qw<#define mgthdr$b_flags mgthdr$r_flags_overlay.mgthdr$b_flagsH#define mgthdr$v_v mgthdr$r_flags_overlay.mgthdr$r_flags_bits.mgthdr$v_vN#define mgthdr$v_more mgthdr$r_flags_overlay.mgthdr$r_flags_bits.mgthdr$v_more^#define mgthdr$v_continuation mgthdr$r_flags_overlay.mgthdr$r_flags_bits.mgthdr$v_continuationX#define mgthdr$v_flags_mbz mgthdr$r_flags_overlay.mgthdr$r_flags_bits.mgthdr$v_flags_mbzZ#define mgthdr$b_action mgthdr$r_actrspinfo_overlay.mgthdr$r>9_mgtactrspinfo.mgthdr$b_actionf#define mgthdr$b_num_par_recs mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$b_num_par_recs`#define mgthdr$b_par_minor mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$b_par_minor`#define mgthdr$b_par_major mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$b_par_major#define mgthdr$l_action_seq mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_action_seq_ctx_overlay.mgthdr$l_action_seq#define mgthdr$l_action_ctx mgthdr$r_actrs?9pinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_action_seq_ctx_overlay.mgthdr$l_action_ctx#define mgthdr$l_access_rights mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_access_rts_hdr.mgth\*dr$r_access_overlay.mgthdr$l_access_rights#define mgthdr$v_read_access mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_access_rts_hdr.mgthdr\;$r_access_overlay.mgthdr$r_access_bits.mgthdr$v_read_access#define mgthdr$v_write_access mgthdr$r_act@9rspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_access_rts_hdr.mgthd\=r$r_access_overlay.mgthdr$r_access_bits.mgthdr$v_write_access#define mgthdr$v_control_access mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_access_rts_hdr.mgt\Ahdr$r_access_overlay.mgthdr$r_access_bits.mgthdr$v_control_access#define mgthdr$l_src_obj_type mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_access_rts_hdr.mgthd\r$l_src_obj_tyA9pe#define mgthdr$t_obj_name mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_req_par_data.mgthdr$\ t_obj_name#define mgthdr$b_obj_minor mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_req_par_data.mgthdr\ $b_obj_minor#define mgthdr$b_obj_major mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_req_par_data.mgthdr\ $b_obj_major#define mgthdr$q_action_addr mgthdr$r_actrspinfo_overlay.mgtB9hdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_req_par_data.mgth\Pdr$r_reg_req_kernel_user_da_ov.mgthdr$r_reg_req_kernel_info.mgthdr$q_action_addr#define mgthdr$q_req_ctx mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_req_par_data.mgthdr$r\H_reg_req_kernel_user_da_ov.mgthdr$r_reg_req_kernel_info.mgthdr$q_req_ctx#define mgthdr$l_ast_epid mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_req_par_data.mgthdr$\Hr_reg_reC9q_kernel_user_da_ov.mgthdr$r_reg_req_user_info.mgthdr$l_ast_epid#define mgthdr$l_ast_rsvd mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_req_par_data.mgthdr$\Hr_reg_req_kernel_user_da_ov.mgthdr$r_reg_req_user_info.mgthdr$l_ast_rsvd#define mgthdr$l_da_ast_epid mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_req_par_data.mgth\Rdr$r_reg_req_kernel_user_da_ov.mgthdr$r_reg_req_local_da_info.mgthdr$l_da_ast_epid#define mgthdrD9$l_da_ast_rsvd mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_req_par_data.mgth\Rdr$r_reg_req_kernel_user_da_ov.mgthdr$r_reg_req_local_da_info.mgthdr$l_da_ast_rsvd#define mgthdr$t_da_password mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_req_par_data.mgth\Rdr$r_reg_req_kernel_user_da_ov.mgthdr$r_reg_req_local_da_info.mgthdr$t_da_password#define mgthdr$b_rm_obj_minor mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgt E9hdr$r_par_overlay.mgthdr$r_reg_rsp_output_data.\mgthdr$b_rm_obj_minor#define mgthdr$b_rm_obj_major mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_rsp_output_data.\mgthdr$b_rm_obj_major#define mgthdr$a_rm_mgt_action_addr mgthdr$r_actrspinfo_overlay.mgthdr$r_mgtactrspinfo.mgthdr$r_par_overlay.mgthdr$r_reg_rsp_output\a_data.mgthdr$r_reg_rsp_kernel_user_da_ov.mgthdr$r_reg_rsp_kernel_info.mgthdr$a_rm_mgt_action_addr"#endif /* #if !defined(__VAXC) */ NF9/* */N/* MGTHDRV2 -- V2 Management header for managed object packets. */N/* */N#define MGTHDRV2$K_REQ_HDR_MAJOR 2 /* Major Rev. */N#define MGTHDRV2$K_REQ_HDR_MINOR 1 /* Minor Rev. */N#define MGTHDRV2$K_RSP_HDR_MAJOR 2 /* Major Rev. */N#define MGTHDRV2$K_RSP_HDRG9_MINOR 1 /* Minor Rev. */N#define MGTHDRV2$K_CONT_HDR_MAJOR 2 /* Major Rev. */N#define MGTHDRV2$K_CONT_HDR_MINOR 1 /* Minor Rev. */N#define MGTHDRV2$K_EVENT_HDR_MAJOR 2 /* Major Rev. */N#define MGTHDRV2$K_EVENT_HDR_MINOR 1 /* Minor Rev. */N#define MGTHDRV2$K_RIGHTS_HDR_MAJOR 2 /* Major Rev. */N#define MGTHDRV2$K_RIGHTS_HDR_MINOR 1 /* Minor Rev H9. */N#define MGTHDRV2$K_CTX_HDR_MAJOR 2 /* Major Rev. */N#define MGTHDRV2$K_CTX_HDR_MINOR 1 /* Minor Rev. */N#define MGTHDRV2$K_EOD_HDR_MAJOR 2 /* Major Rev. */N#define MGTHDRV2$K_EOD_HDR_MINOR 1 /* Minor Rev. */"#define MGTHDRV2$K_OBJ_NAME_LEN 32"#define MGTHDRV2$C_OBJ_NAME_LEN 32#define MGTHDRV2$M_V 0x1#define MGTHDRV2$M_MORE 0x2##define MGTHDRV2$M_CONTINUATIO I9N 0x4#define MGTHDRV2$M_CONTEXT 0x8#define MGTHDRV2$M_EOD 0x10N#define MGTHDRV2$K_MINI_HDR_V2_1_LENGTH 8 /* V2.1 Mini-Header length */N#define MGTHDRV2$C_MINI_HDR_V2_1_LENGTH 8 /* V2.1 Old VAX style length */N#define MGTHDRV2$K_MINI_HDR_LENGTH 8 /* Mini-Header length */N#define MGTHDRV2$C_MINI_HDR_LENGTH 8 /* Old VAX style length */N#define MGTHDRV2$K_EOD_HDR_V2_1_LEN 8 /* V2.1 EOD header length */N#define MGTHDRV2$C_EOD_HDR_V2_1_LEN J98 /* V2.1 Old VAX EOD header length */N#define MGTHDRV2$K_EOD_HDR_LEN 8 /* EOD header length */N#define MGTHDRV2$C_EOD_HDR_LEN 8 /* EOD header Old VAX style length */N#define MGTHDRV2$K_BASE_HDR_V2_1_LENGTH 16 /* V2.1 Base Header length */N#define MGTHDRV2$C_BASE_HDR_V2_1_LENGTH 16 /* V2.1 Old VAX style length */N#define MGTHDRV2$K_BASE_HDR_LENGTH 16 /* Base Header length */N#define MGTHDRV2$C_BASE_HDR_LENGTH 16 /* Old VAX style lengtK9h */N#define MGTHDRV2$K_ACT_HDR_V2_1_LEN 24 /* V2.1 Action header length */N#define MGTHDRV2$C_ACT_HDR_V2_1_LEN 24 /* V2.1 Action header length */N#define MGTHDRV2$K_ACT_HDR_LEN 24 /* Action header length */N#define MGTHDRV2$C_ACT_HDR_LEN 24 /* Old VAX style length */S#define MGTHDRV2$R_ACT_PAR 24 /* Beginning of Action parameters block */N#define MGTHDRV2$K_RSP_HDR_V2_1_LEN 24 /* V2.1 Response header length */N#dL9efine MGTHDRV2$C_RSP_HDR_V2_1_LEN 24 /* V2.1 Response header length */N#define MGTHDRV2$K_RSP_HDR_LEN 24 /* Response header length */N#define MGTHDRV2$C_RSP_HDR_LEN 24 /* Old VAX style length */U#define MGTHDRV2$R_RSP_PAR 24 /* Beginning of Response parameters block */N#define MGTHDRV2$K_CONT_HDR_V2_1_LEN 24 /* V2.1 Continuation header length */N#define MGTHDRV2$C_CONT_HDR_V2_1_LEN 24 /* V2.1 Continuation header length */N#define MGTHDRV2$K_CM9ONT_HDR_LEN 24 /* Continuation header length */N#define MGTHDRV2$C_CONT_HDR_LEN 24 /* Old VAX style length */Y#define MGTHDRV2$R_CONT_PAR 24 /* Beginning of Continuation parameters block */N#define MGTHDRV2$K_EVENT_HDR_V2_1_LEN 24 /* V2.1 Event header length */N#define MGTHDRV2$C_EVENT_HDR_V2_1_LEN 24 /* V2.1 Event header length */N#define MGTHDRV2$K_EVENT_HDR_LEN 24 /* Event header length */N#define MGTHDRV2$C_EVENT_HDR_LEN 2N94 /* Old VAX style length */R#define MGTHDRV2$R_EVENT_PAR 24 /* Beginning of Event parameters block */P#define MGTHDRV2$K_RIGHTS_HDR_V2_1_LEN 24 /* V2.1 Access Rights header length */P#define MGTHDRV2$C_RIGHTS_HDR_V2_1_LEN 24 /* V2.1 Access Rights header length */N#define MGTHDRV2$K_RIGHTS_HDR_LEN 24 /* Access Rights header length */N#define MGTHDRV2$C_RIGHTS_HDR_LEN 24 /* Access Rights header length */N#define MGTHDRV2$R_RIGHTS_PAR 24 /* Access RiO9ghts parameters block */X#define MGTHDRV2$K_REG_REQ_HDR_V2_1_LEN 24 /* V2.1 Registration request header length */X#define MGTHDRV2$C_REG_REQ_HDR_V2_1_LEN 24 /* V2.1 Registration request header length */X#define MGTHDRV2$K_REG_REQ_HDR_V2_2_LEN 24 /* V2.1 Registration request header length */X#define MGTHDRV2$C_REG_REQ_HDR_V2_2_LEN 24 /* V2.1 Registration request header length */P#define MGTHDRV2$K_REG_REQ_HDR_LEN 24 /* Registration request header length */P#define MGTHDRV2$C_REG_REQ_HDR_LEN 2P94 /* Registration request header length */T#define MGTHDRV2$R_REG_REQ_PAR 24 /* Registration request parameters block */Y#define MGTHDRV2$K_REG_RSP_HDR_V2_1_LEN 24 /* V2.1 Registration response header length */Y#define MGTHDRV2$C_REG_RSP_HDR_V2_1_LEN 24 /* V2.1 Registration response header length */Q#define MGTHDRV2$K_REG_RSP_HDR_LEN 24 /* Registration response header length */Q#define MGTHDRV2$C_REG_RSP_HDR_LEN 24 /* Registration response header length */Q#define MGTHDRV2$R_REG Q9_RSP_PAR 24 /* Registration response output block */ typedef struct _mgthdrv2 { __union {N unsigned char mgthdrv2$b_hdr_len; /* Header Len in bytes */ __struct {+ unsigned mgthdrv2$v_rsvd_1 : 3;X unsigned mgthdrv2$v_hdr_len_qw : 5; /* Length of data header in quadwords */N/* Also offset to object specific data */% } mgthdrv2$r_hdr1_fields;% } mgthdrv2$r_hdr_len_overlay;R9 __union {N unsigned char mgthdrv2$b_flags; /* Header flags */ __struct {N unsigned mgthdrv2$v_v : 1; /* Data Header is valid */O unsigned mgthdrv2$v_more : 1; /* Another mgt data header follows */\ unsigned mgthdrv2$v_continuation : 1; /* Header for continuation data follows */N/* Flags defined for V2.1 headers */R unsigned mgthdrv2$v_context : 1; /* HeS9ader for context data follows */Q unsigned mgthdrv2$v_eod : 1; /* Mini-header for EOD record follows */N unsigned mgthdrv2$v_rsvd1 : 1; /* Reserved */N unsigned mgthdrv2$v_rsvd2 : 1; /* Reserved */N unsigned mgthdrv2$v_rsvd3 : 1; /* Reserved */$ } mgthdrv2$r_flags_bits;# } mgthdrv2$r_flags_overlay;N unsigned char mgthdrv2$b_hdr_minor; /* Header Minor Revision T9 */N unsigned char mgthdrv2$b_hdr_major; /* Header Major Revision */N unsigned char mgthdrv2$b_mgt_func; /* Record type code: */N/* (see MGT_FUNC constant section for codes) */N unsigned char mgthdrv2$b_rsp_status; /* Action: SBZ */N/* Response: status of performing action. */g unsigned short int mgthdrv2$w_par_len; /* Total length of REC_TYP records following in quadworU9ds */S unsigned int mgthdrv2$l_obj_handle; /* Registration Handle of destination MO */R unsigned int mgthdrv2$l_src_obj_handle; /* Registration Handle of source MO */ __union {N/* Action, Response, and info Headers */N __struct { /* Action & Response headers */N unsigned char mgthdrv2$b_action; /* Managed Object action codes */N/* (see ACTION constant section for codes) V9 */T unsigned char mgthdrv2$b_num_par_recs; /* Number of Parameter Records */[ unsigned char mgthdrv2$b_par_minor; /* Minor Rev. of object specific params. */b unsigned char mgthdrv2$b_par_major; /* Major Rev. of object specific action_params. */ __union {e unsigned int mgthdrv2$l_action_seq; /* Mgt station assigned action sequence number */] unsigned int mgthdrv2$l_action_ctx; /* Mgt station assigned action context W9 */4 } mgthdrv2$r_action_seq_ctx_overlay;N/* the time that a structure has a member, it is defined */N/* before the structures that have members so that the */N/* "." operand has the right value. */' } mgthdrv2$r_mgtactrspinfo;( } mgthdrv2$r_actrspinfo_overlay; } MGTHDRV2; #if !defined(__VAXC)H#define mgthdrv2$b_hdr_len mgthdrv2$r_hdr_len_overlay.mgthdrv2$b_hdr_lene#defX9ine mgthdrv2$v_hdr_len_qw mgthdrv2$r_hdr_len_overlay.mgthdrv2$r_hdr1_fields.mgthdrv2$v_hdr_len_qwB#define mgthdrv2$b_flags mgthdrv2$r_flags_overlay.mgthdrv2$b_flagsP#define mgthdrv2$v_v mgthdrv2$r_flags_overlay.mgthdrv2$r_flags_bits.mgthdrv2$v_vV#define mgthdrv2$v_more mgthdrv2$r_flags_overlay.mgthdrv2$r_flags_bits.mgthdrv2$v_moref#define mgthdrv2$v_continuation mgthdrv2$r_flags_overlay.mgthdrv2$r_flags_bits.mgthdrv2$v_continuation\#define mgthdrv2$v_context mgthdrv2$r_flags_overlay.mgthdrv2$r_fY9lags_bits.mgthdrv2$v_contextT#define mgthdrv2$v_eod mgthdrv2$r_flags_overlay.mgthdrv2$r_flags_bits.mgthdrv2$v_eodb#define mgthdrv2$b_action mgthdrv2$r_actrspinfo_overlay.mgthdrv2$r_mgtactrspinfo.mgthdrv2$b_actionn#define mgthdrv2$b_num_par_recs mgthdrv2$r_actrspinfo_overlay.mgthdrv2$r_mgtactrspinfo.mgthdrv2$b_num_par_recsh#define mgthdrv2$b_par_minor mgthdrv2$r_actrspinfo_overlay.mgthdrv2$r_mgtactrspinfo.mgthdrv2$b_par_minorh#define mgthdrv2$b_par_major mgthdrv2$r_actrspinfo_overlay.mgthdrv2$r_mg Z9tactrspinfo.mgthdrv2$b_par_major#define mgthdrv2$l_action_seq mgthdrv2$r_actrspinfo_overlay.mgthdrv2$r_mgtactrspinfo.mgthdrv2$r_action_seq_ctx_overlay.mgthdrv2$l_a\ ction_seq#define mgthdrv2$l_action_ctx mgthdrv2$r_actrspinfo_overlay.mgthdrv2$r_mgtactrspinfo.mgthdrv2$r_action_seq_ctx_overlay.mgthdrv2$l_a\ ction_ctx"#endif /* #if !defined(__VAXC) */ N/* */N/* MGT_FUNC constant section [9 */N/* */b#define MGTHDR$K_REC_TYPE_RESERVED 0 /* 0 - Keep reserved to detect failure to fill in field */R#define MGTHDR$K_REC_TYPE_ACT_REQ 1 /* 1 - Request to act on managed object */N#define MGTHDR$K_REC_TYPE_ACT_RSP 2 /* 2 - Response to ACT_REQ request */l#define MGTHDR$K_REC_TYPE_ACT_CONT 3 /* 3 - Continuation info for preceeding action or response record */P#define MGTHDR$K_REC_TYPE_EVENT \94 /* 4 - Unsolicited event notification */N#define MGTHDR$K_REC_TYPE_ACCESS_RIGHTS 5 /* 5 - Requestor access rights */N/* End of codes defined in the MGTHDR V1.1 timeframe */N#define MGTHDR$K_REC_TYPE_ACT_CTX 6 /* 6 - Context info for request */U#define MGTHDR$K_REC_TYPE_EOD 7 /* 7 - End of data (uses mini-header only) */U#define MGTHDR$K_REC_TYPE_FIRST_UNUSED 8 /* Insert new constants ahead of this one */N#define MGTHDR$K_REC_TYPE_FIRST_CODE 0 ]9/* First Management record type */\#define MGTHDR$K_REC_TYPE_V1_1_LASTCODE 5 /* Last Management record type for V1.1 headers */N#define MGTHDR$K_REC_TYPE_LAST_CODE 7 /* Last Management record type */N/* */N/* ACTION constant section */N/* */N/* RMDriver request codes for all other Managed Obje^9cts to process */c#define MOACT$K_MO_RESERVED 0 /* 0 - Keep reserved to detect failure to fill in field */N/* Last 15 codes are common between all Managed Objects */N/* RMDriver request codes for all other Managed Objects to process */a#define MOACT$K_MO_DRIVER_STOPPED 241 /* 241 - RMDriver has been stopped (informational) */a#define MOACT$K_MO_DRIVER_STARTED 242 /* 242 - RMDriver has been (re)started (informational) */N/* End of codes _9defined in the MGTHDR V1.1 timeframe */N/* NOTE! Can not have more than MO_num_common_codes entries! */N#define MOACT$K_MO_FIRST_CODE 0 /* First MO action code */N#define MOACT$K_MO_FIRST_COMMON_CODE 241 /* First MO common action code */N#define MOACT$K_MO_NUM_COMMON_CODES 15 /* Number of MO common action codes */N/* */N/* SRC_OBJ_TYPE constant section `9 */N/* */N#define RMOBJ$K_RESERVED 0 /* Reserved for error checking */N#define RMOBJ$K_RMDRIVER 1 /* RMDRIVER itself */N#define RMOBJ$K_KERNEL_MO 2 /* Kernel-mode Managed Object */N#define RMOBJ$K_USER_MO 3 /* User-mode Managed Object */N#define RMOBJ$K_NETWORK_DA 4 /* Network Data Analyzer a9 */N#define RMOBJ$K_LOCAL_DA 5 /* Local Data Analyzer */N/* End of codes defined in the MGTHDR V1.1 timeframe */T#define RMOBJ$K_FIRST_UNUSED 6 /* Insert new constants ahead of this one */ #define RMOBJ$K_FIRST_OBJ_TYPE 0$#define RMOBJ$K_V1_1_LAST_OBJ_TYPE 5#define RMOBJ$K_LAST_OBJ_TYPE 5#define RMOBJ$K_NUM_OBJ_TYPES 6N/* */N/* Standard Management functb9ion request and response data */N/* */N/* As of V2 of the Management Headers, the request and response data */N/* fields will be based off of the start of the parameter section, and */N/* not the beginning of the Management Header. */N/* */N/* c9 */N/* Access rights parameter section */N/* */"#define MGTRTSV2$M_READ_ACCESS 0x1##define MGTRTSV2$M_WRITE_ACCESS 0x2%#define MGTRTSV2$M_CONTROL_ACCESS 0x4R#define MGTRTSV2$K_RIGHTS_PAR_V2_1_LEN 8 /* V2.1 Access Rights parameter length */R#define MGTRTSV2$C_RIGHTS_PAR_V2_1_LEN 8 /* V2.1 Access Rights parameter length */N#define MGTRTSV2$K_RIGHTS_PAR_LEN 8 d9 /* Access Rights parameter length */N#define MGTRTSV2$C_RIGHTS_PAR_LEN 8 /* Access Rights parameter length */ typedef struct _mgtrtsv2 { __union {\ unsigned int mgtrtsv2$l_access_rights; /* Security access rights of the requestor */ __struct {V unsigned mgtrtsv2$v_read_access : 1; /* Able to request monitoring data */Z unsigned mgtrtsv2$v_write_access : 1; /* Able to request execution of fixes */a unsigned mgtrtsv2$v_control_ e9access : 1; /* Able to configure/change Managed Object */* unsigned mgtrtsv2$v_rsvd : 29;% } mgtrtsv2$r_access_bits;$ } mgtrtsv2$r_access_overlay;N unsigned int mgtrtsv2$l_src_obj_type; /* Source Object type */N/* (see SRC_OBJ_TYPE constant section for codes) */ } MGTRTSV2; #if !defined(__VAXC)S#define mgtrtsv2$l_access_rights mgtrtsv2$r_access_overlay.mgtrtsv2$l_access_rightsf#define mgtrtsv2$v_read_access mgtf9rtsv2$r_access_overlay.mgtrtsv2$r_access_bits.mgtrtsv2$v_read_accessh#define mgtrtsv2$v_write_access mgtrtsv2$r_access_overlay.mgtrtsv2$r_access_bits.mgtrtsv2$v_write_accessl#define mgtrtsv2$v_control_access mgtrtsv2$r_access_overlay.mgtrtsv2$r_access_bits.mgtrtsv2$v_control_access"#endif /* #if !defined(__VAXC) */ N/* */U/* RMDAT -- RMDRIVER Managed Object and driver data for local Data Analyzers, etc. */N/* g9 */N#define RMDAT$K_PAR_VER_MAJOR 1 /* Minor Rev. */N#define RMDAT$K_PAR_VER_MINOR 2 /* Major Rev. */ #define RMDAT$K_NODE_NAME_LEN 16!#define RMDAT$K_GROUP_NAME_LEN 16Q#define RMDAT$K_PAR_V1_1_LEN 48 /* V1.1 RMDRIVER data parameter length */Q#define RMDAT$C_PAR_V1_1_LEN 48 /* V1.1 RMDRIVER data parameter length */N#define RMDAT$K_PAR_LEN 48 h9/* RMDRIVER data parameter length */N#define RMDAT$C_PAR_LEN 48 /* RMDRIVER data parameter length */ typedef struct _rmdat {X/* Size (bytes) for NODENAME, GROUP NAME and GALAXY NAME (see [DECAMDS]SPARCDEFS.SDL) */T unsigned int rmdat$l_obj_handle; /* RMDRIVER's Managed Object registration */U unsigned char rmdat$b_obj_minor; /* RMDRIVER's Managed Object minor version */U unsigned char rmdat$b_obj_major; /* RMDRIVER's Managed Object major version */N i9unsigned short int rmdat$w_cap_ver; /* RMDRIVER's capability version */N char rmdat$t_node_name [16]; /* OpenVMS node name */N char rmdat$t_group_name [16]; /* AM group name */P unsigned __int64 rmdat$q_self_mac_addr; /* MAC address for local RMDRIVER */ } RMDAT;N/* */N/* Managed Object Registration parameter structures */N/* j9 */N/* The next two structures are used by the MGT$REGISTER_KERNEL_MO */N/* One is for the input data to the routine, and the other is the */N/* output data from the routine. */N/* */"#define MGTKRREQ$K_OBJ_NAME_LEN 32N#define MGTKRREQ$K_OBJ_HDR_VER_MAX 8 /* Number of header versions */N/* k9 handled by the Managed Object */N#define MGTKRREQ$K_V1_1_DATA_LEN 72 /* Reg req data length */N#define MGTKRREQ$C_V1_1_DATA_LEN 72 /* Old VAX style length */ typedef struct _mgtkrreq {+ unsigned char mgtkrreq$t_obj_name [32];N/* Node unique ASCIZ obj name */N unsigned char mgtkrreq$b_obj_minor; /* Managed Object minor version */N unsigned char mgtkrreq$b_obj l9_major; /* Managed Object major version */N char mgtkrreq$t_obj_fill [6]; /* Fill to quadword boundary */N/* Length to make quadword multiple */Y unsigned short int mgtkrreq$w_obj_hdr_ver [8]; /* Array of header versions handled */N/* by Managed Object, terminated */N/* by 0x0000 */ __union { __struct {N/* Kernem9l Mode objects on 64-bit processors: */R unsigned __int64 mgtkrreq$q_action_addr; /* $MGT_ACTION routine for */N/* kernel mode Managed Objects */N unsigned __int64 mgtkrreq$q_req_ctx; /* Request context value */0 } mgtkrreq$r_reg_req_kernel_info_qw; __struct {N/* Kernel Mode objects on 32-bit processors: */N unsigned int mgtkrreq$l_ac n9tion_addr; /* $MGT_ACTION routine for */N/* kernel mode Managed Objects */] unsigned int mgtkrreq$l_action_addr_rsvd; /* Keep same spacing as QW structure */N unsigned int mgtkrreq$l_req_ctx; /* Request context value */Y unsigned int mgtkrreq$l_req_ctx_rsvd; /* Keep same spacing as QW structure */0 } mgtkrreq$r_reg_req_kernel_info_lw;- } mgtkrreq$r_reg_req_kernel_info_ove; } MGTKRREQ;o9 #if !defined(__VAXC)z#define mgtkrreq$q_action_addr mgtkrreq$r_reg_req_kernel_info_ove.mgtkrreq$r_reg_req_kernel_info_qw.mgtkrreq$q_action_addrr#define mgtkrreq$q_req_ctx mgtkrreq$r_reg_req_kernel_info_ove.mgtkrreq$r_reg_req_kernel_info_qw.mgtkrreq$q_req_ctxz#define mgtkrreq$l_action_addr mgtkrreq$r_reg_req_kernel_info_ove.mgtkrreq$r_reg_req_kernel_info_lw.mgtkrreq$l_action_addr#define mgtkrreq$l_action_addr_rsvd mgtkrreq$r_reg_req_kernel_info_ove.mgtkrreq$r_reg_req_kernel_info_lw.mgtkrreq$l_ p9action_addr_rsvdr#define mgtkrreq$l_req_ctx mgtkrreq$r_reg_req_kernel_info_ove.mgtkrreq$r_reg_req_kernel_info_lw.mgtkrreq$l_req_ctx|#define mgtkrreq$l_req_ctx_rsvd mgtkrreq$r_reg_req_kernel_info_ove.mgtkrreq$r_reg_req_kernel_info_lw.mgtkrreq$l_req_ctx_rsvd"#endif /* #if !defined(__VAXC) */ N#define MGTKRRSP$K_V1_1_DATA_LEN 32 /* Reg rsp data length */N#define MGTKRRSP$C_V1_1_DATA_LEN 32 /* Old VAX style length */ typedef struct _mgtkrrsp {X unsigned cq9har mgtkrrsp$b_rm_obj_minor; /* RMDriver's Managed Object minor version */X unsigned char mgtkrrsp$b_rm_obj_major; /* RMDriver's Managed Object major version */N char mgtkrrsp$t_obj_fill [6]; /* Fill to quadword boundary */c unsigned __int64 mgtkrrsp$q_rm_sec_token; /* Security token for accessing RMDriver functions */ __union { __struct {N/* Kernel Mode objects on 64-bit processors: */Y unsigned __int64 mgtkrrsp$q_r9action_addr; /* RMDriver's $MGT_ACTION routine */N/* for kernel mode objects */0 } mgtkrrsp$r_reg_rsp_kernel_info_qw; __struct {N/* Kernel Mode objects on 32-bit processors: */U unsigned int mgtkrrsp$l_action_addr; /* RMDriver's $MGT_ACTION routine */N/* for kernel mode objects */] unsigned int mgtkrrsp$l_action_addr_rsvd; s9/* Keep same spacing as QW structure */0 } mgtkrrsp$r_reg_rsp_kernel_info_lw;- } mgtkrrsp$r_reg_rsp_kernel_info_ove;R unsigned int mgtkrrsp$l_obj_handle; /* Newly assigned Managed Object handle */Q unsigned int mgtkrrsp$l_rm_obj_handle; /* RMDriver's Managed Object handle */ } MGTKRRSP; #if !defined(__VAXC)z#define mgtkrrsp$q_action_addr mgtkrrsp$r_reg_rsp_kernel_info_ove.mgtkrrsp$r_reg_rsp_kernel_info_qw.mgtkrrsp$q_action_addrz#define mgtkrrsp$l_action_addrt9 mgtkrrsp$r_reg_rsp_kernel_info_ove.mgtkrrsp$r_reg_rsp_kernel_info_lw.mgtkrrsp$l_action_addr#define mgtkrrsp$l_action_addr_rsvd mgtkrrsp$r_reg_rsp_kernel_info_ove.mgtkrrsp$r_reg_rsp_kernel_info_lw.mgtkrrsp$l_action_addr_rsvd"#endif /* #if !defined(__VAXC) */ N/* */N/* Management common error codes */V/* Note: Managed Object specific codes start at 128 (MGT$K_STS_FIRST_PRIVATE_u9CODE) */N/* */O#define MGT$K_STS_RESERVED 0 /* Detect if this field has been set */N#define MGT$K_STS_SUCCESS 1 /* Make equal to SS$_NORMAL */]#define MGT$K_STS_HDR_NOT_ALIGNED 2 /* Request or response buffer not quadword aligned */N#define MGT$K_STS_HDR_NOT_VALID 3 /* Management header not valid */N#define MGT$K_STS_HDR_INCOMPAT 4 /* Incompatible header version */v9N#define MGT$K_STS_PAR_INCOMPAT 5 /* Incompatible parameter version */N#define MGT$K_STS_PAR_INVALID 6 /* Invalid parameter(s) */N#define MGT$K_STS_RSP_NO_ROOM 7 /* No room in response buffer */i#define MGT$K_STS_RSP_NOSAMEBUF 8 /* Using request buffer for response buffer is not implemented */N#define MGT$K_STS_RSP_RSVD2 9 /* Reserved response buffer error */a#define MGT$K_STS_REQ_NO_ROOM 10 /* No room in request buffer to quadw9word-align request */f#define MGT$K_STS_REQ_ACT_INVALID 11 /* Management Request action code is invalid (out of range) */^#define MGT$K_STS_REQ_ILLEGAL_DEST 12 /* Management Request for destination MO is illegal */_#define MGT$K_STS_REQ_RESERVED_DEST 13 /* Management Request for destination MO is reserved */_#define MGT$K_STS_REQ_UNIMPLEMENTED 14 /* Management Request action code is not implemented */X#define MGT$K_STS_REQ_NOPRIV 15 /* No privilege to execute Management Request x9*/p#define MGT$K_STS_REQ_INVALID_PAR_LEN 16 /* Management Request parameter length invalid for particular action */f#define MGT$K_STS_REQ_INVALID_PAR_RECS 17 /* Management Request invalid number of parameter records */N#define MGT$K_STS_REQ_RSVD1 18 /* Reserved request buffer error */N#define MGT$K_STS_REQ_RSVD2 19 /* Reserved request buffer error */N#define MGT$K_STS_REQ_RSVD3 20 /* Reserved request buffer error */N#define MGT$K_STS_REQ_RSVD4 21 /* Ry9eserved request buffer error */P#define MGT$K_STS_OBJ_HANDLE_INVALID 22 /* Managed Object handle is not valid */h#define MGT$K_STS_OBJ_HANDLE_NOTFOUND 23 /* Managed Object handle is not in the registration database */l#define MGT$K_STS_OBJ_HANDLE_STALE 24 /* Managed Object has reregistered, giving it a new object handle */t#define MGT$K_STS_OBJ_HANDLE_UPDATED 25 /* Managed Object just reregistered, updating the handle (success status) */N#define MGT$K_STS_OBJ_HANDLE_RSVD1 26 /* Reserved obz9ject handle error */]#define MGT$K_STS_OBJ_TYPE_INVALID 27 /* Managed Object type is not valid (out of range) */N#define MGT$K_STS_OBJ_TYPE_RESERVED 28 /* Managed Object type is reserved */N#define MGT$K_STS_OBJ_TYPE_RSVD1 29 /* Managed Object type error */N#define MGT$K_STS_OBJ_TYPE_RSVD2 30 /* Managed Object type error */N#define MGT$K_STS_OBJ_TYPE_RSVD3 31 /* Managed Object type error */N#define MGT$K_STS_OBJ_TYPE_RSVD4 32 /* Managed Object type e{9rror */t#define MGT$K_STS_CONT_INVALIDADD 33 /* Adding a continuation header to a Mgt packet set with a context header */w#define MGT$K_STS_CONT_INVALIDATT 34 /* Attaching a continuation packet to a Mgt packet set with a context header */#define MGT$K_STS_CONT_INVALIDADR 35 /* Continuation packet address given for attach is not in at the end of the MO packet set */c#define MGT$K_STS_CONT_INVALIDHDR 36 /* Continuation header at the given address is not valid */N#define MGT$K_|9STS_CONT_RSVD1 37 /* Reserved cont header error */N#define MGT$K_STS_CONT_RSVD2 38 /* Reserved cont header error */n#define MGT$K_STS_CONT_DATA_INVALIDCOPY 39 /* Continuation data packet already found for dest MO packet set */n#define MGT$K_STS_CONT_DATA_INVALIDREPL 40 /* Continuation data packet doesn't exist for dest MO packet set */R#define MGT$K_STS_CONT_DATA_BADFORMAT 41 /* Continuation data format is invalid */Y#define MGT$K_STS_CONT_DATA_INVALID 42 /* Continuat}9ion data value(s) is/are not valid */N/* */N/* The next three statuses indicate the result of trying to continue */N/* a data request. Basically, here is how the statuses relate */N/* to one another: */N/* */0/* STS_SUCCESS Continuation succeeded */F/* STS_CONT_DATA~9_CTX_FOUND_W Continuation continued with a warning */E/* STS_CONT_DATA_CTX_FOUND_E Continuation continued with an error */</* STS_CONT_DATA_CTX_NOT_FND Continuation failed */N/* */j#define MGT$K_STS_CONT_DATA_CTX_FOUND_W 43 /* Context for using this continuation data has changed, but */N/* the place to continue the data collection has been found */N/* with some certainty. This is a "warning"-l9evel status. */N/* This warning status would signal to the data collector of */N/* the possibility of these data collection irregularities. */N/* It is up to the data collector whether to continue this */N/* data collection or start a new one. */j#define MGT$K_STS_CONT_DATA_CTX_FOUND_E 44 /* Context for using this continuation data has changed, but */N/* the place to continue the data collection9 is a last-ditch */N/* effort. This is an "error"-level status. */N/* This error status would signal to the data collector that */N/* there is possibility of these data collection irregularities. */N/* It is up to the data collector whether to continue this */N/* data collection or start a new one. */m#define MGT$K_STS_CONT_DATA_CTX_NOT_FND 45 /* Context for using this con9tinuation data is no longer valid, */N/* and cannot be recovered. A new request must be started */N/* to collect data. This is a "fatal error"-level status. */N#define MGT$K_STS_CONT_DATA_RSVD1 46 /* Continuation data error */N#define MGT$K_STS_CONT_DATA_RSVD2 47 /* Continuation data error */N#define MGT$K_STS_CONT_DATA_RSVD3 48 /* Continuation data error */i#define MGT$K_STS_SEC_INCOMPAT_PAR 49 /* Management Security buf9fer - incompatible parameter version */_#define MGT$K_STS_SEC_INVALID_PAR 50 /* Management Security buffer - invalid parameter(s) */^#define MGT$K_STS_SEC_ILLEGAL_PAR 51 /* Management Security buffer - illegal settings or */N/* combination of settings for the request */S#define MGT$K_STS_SEC_RSVD1 52 /* Management Security buffer - reserved */S#define MGT$K_STS_SEC_RSVD2 53 /* Management Security buffer - reserved */N#define MGT$K_STS_9PKT_REP_INVSIZE 54 /* MO packet lengths != for replace */N#define MGT$K_STS_PKT_RSVD1 55 /* MO packet reserved */N#define MGT$K_STS_PKT_RSVD2 56 /* MO packet reserved */N#define MGT$K_STS_PKT_RSVD3 57 /* MO packet reserved */N#define MGT$K_STS_PKT_RSVD4 58 /* MO packet reserved */p#define MGT$K_STS_EOD_INVALIDADD 59 /* Adding an EOD header to a MO packet set with a continuation header */N/* or 9a context header */N#define MGT$K_STS_EOD_RSVD1 60 /* Reserved EOD header error */N#define MGT$K_STS_EOD_RSVD2 61 /* Reserved EOD header error */N#define MGT$K_STS_HDR_INFO_INVALID 62 /* MO header info is invalid */W#define MGT$K_STS_HDR_INFO_UNEXPECTED 63 /* MO header info is in an unexpected state */N#define MGT$K_STS_HDR_INFO_RSVD1 64 /* Reserved MO header info error */N#define MGT$K_STS_HDR_INFO9_RSVD2 65 /* Reserved MO header info error */f#define MGT$K_STS_FIRST_PRIVATE_CODE 128 /* First code value for Managed Object private error codes */N/* */N/* Older constants for compatibility */N/* */]#define MGT$K_STS_NOT_ALIGNED 2 /* Request or response buffer not quadword aligned */N#define MGT$9K_STS_INCOMPAT_HDR 4 /* Incompatible header version */N#define MGT$K_STS_INCOMPAT_PAR 5 /* Incompatible parameter version */N#define MGT$K_STS_INVALID_PAR 6 /* Invalid parameter(s) */N#define MGTHDR$K_OBJ_NAME_LEN 32 /* V1.1 header era definition */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-de9fined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MGTDEF_LOADED */ ww`5[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, dupli9cated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyo9ne without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:28 9 by OpenVMS SDL V3.7 */G/* Source: 06-APR-2017 15:21:02 $1$DGA8345:[LIB_H.SRC]MMAPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MMAPDEF ***/#ifndef __MMAPDEF_LOADED#define __MMAPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Define9d whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __st9ruct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Memory Map Definitions. The memory map structure contains memory */N/* mapping data for a shared memory region. */N/* */ #define MMAP$M_V9ALID 0x1##define MMAP$M_INIT_IN_PROGRESS 0x2##define MMAP$M_RESERVED_2_15 0xFFFCN#define MMAP$C_LENGTH 64 /* Length of MMAP */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mmap {#pragma __nomember_alignmentN unsigned __int64 mmap$q_virt_size; /* Virtual size in bytes */N unsigned 9 short int mmap$w_size; /* Size of the structure */N unsigned char mmap$b_type; /* Dynamic structure type */N unsigned char mmap$b_subtype; /* Dynamic structure subtype */N short int mmap$w_level_count; /* Number of PFNLST levels */ __union {N unsigned short int mmap$w_flags; /* FLAGS word */ __struct {N unsigned mmap$v_valid : 1; /* MMAP is valid */U9 unsigned mmap$v_init_in_progress : 1; /* Initialization is in progress *// unsigned mmap$v_reserved_2_15 : 14; } mmap$r_flags_bits; } mmap$r_flags_overlay;N/* Verified for x86 port - Clair Grant */N unsigned __int64 mmap$i_first_pfn; /* First page in a contiguous range */N int mmap$l_top_page_count; /* Number of pages at the top level */N int mmap$l_pfnlst_page_count; /* Number of PFNLST 9pages */N int mmap$l_data_page_count; /* Number of data pages */N/* Pad to 64 byte boundary */% unsigned int mmap$l_spares_1 [7]; } MMAP; #if !defined(__VAXC)6#define mmap$w_flags mmap$r_flags_overlay.mmap$w_flagsH#define mmap$v_valid mmap$r_flags_overlay.mmap$r_flags_bits.mmap$v_valid^#define mmap$v_init_in_progress mmap$r_flags_overlay.mmap$r_flags_bits.mmap$v_init_in_progressX#define mmap$v_reser 9ved_2_15 mmap$r_flags_overlay.mmap$r_flags_bits.mmap$v_reserved_2_15"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Ltypedef struct _mmap * MMAP_PQ; /* Long pointer to an MMAP structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else!typedef unsigned __int64 MMAP_PQ;##endif9 /* __INITIAL_POINTER_SIZE */#define PFNLST$M_VALID 0x1#define PFNLST$M_UNUSED1 0x1E#define PFNLST$M_GH 0x60##define PFNLST$M_UNUSED2 0xFFFFFF80'#define PFNLST$M_PFN 0xFFFFFFFF00000000N#define PFNLST$C_LENGTH 8 /* Length of PFNLST */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pfnlst {#pragma 9__nomember_alignmentN unsigned pfnlst$v_valid : 1; /* Valid Bit */N unsigned pfnlst$v_unused1 : 4; /* Bits Unused */N unsigned pfnlst$v_gh : 2; /* Granularity Hint */N unsigned pfnlst$v_unused2 : 25; /* Bits Unused */N unsigned pfnlst$v_pfn : 32; /* Page Frame Number */ } PFNLST; #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size 9__save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Ptypedef struct _pfnlst * PFNLST_PQ; /* Long pointer to a PFNLST structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else#typedef unsigned __int64 PFNLST_PQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __requ9ired_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MMAPDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Developme9nt, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/9M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************************************* 9*************************/=/* Created: 7-Oct-2024 15:22:18 by OpenVMS SDL V3.7 */H/* Source: 07-MAR-1994 22:37:28 $1$DGA8345:[LIB_H.SRC]MMECBDEF.SDL;1 *//********************************************************************************************************************************/#/*** MODULE MMECBDEF IDENT X-4 ***/#ifndef __MMECBDEF_LOADED#define __MMECBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save9#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __st9ruct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define MMECB$M_UNLOAD 0x1#define MMECB$M_ALLOC 0x2#define MMECB$M_BACKUP_FILE 0x4#define MMECB$M_CLOSE_READ 0x8 #define MMECB$M_CLOSE_WRITE 0x10(#define MMECB$M_CONTINUATION_VOLUME 0x20#define MMECB$M_DEALLOCATE 0x40!#define MMECB$M_DEVICE_AVAIL 0x809$#define MMECB$M_DEVICE_UNAVAIL 0x100#define MMECB$M_DISMOUNT 0x200%#define MMECB$M_DISPLAY_MESSAGE 0x400#define MMECB$M_EOV_READ 0x800 #define MMECB$M_EOV_WRITE 0x1000!#define MMECB$M_INITIALIZE 0x2000#define MMECB$M_MOUNT 0x4000$#define MMECB$M_MOUNT_REQUEST 0x8000&#define MMECB$M_NEWVOL_REQUEST 0x10000%#define MMECB$M_NOTIFY_DEVICE 0x20000!#define MMECB$M_OPCOM_ACP 0x40000##define MMECB$M_OPCOM_MOUNT 0x80000"#define MMECB$M_OPEN_READ 0x100000##define MMECB$M_OPEN_WRITE 0x2000090&#define MMECB$M_VOLUME_ONLINE 0x400000##define MMECB$M_BACKUP_END 0x800000&#define MMECB$M_BACKUP_START 0x1000000'#define MMECB$M_WRITE_REQUEST 0x2000000##define MMECB$M_MOUNT_END 0x4000000"#define MMECB$M_INIT_END 0x8000000%#define MMECB$M_NEWVOL_END 0x10000000$#define MMECB$M_DMTPRCDEL 0x20000000  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; struct _mcl; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplus 9plus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mmecb {#pragma __nomember_alignmentN unsigned short int mmecb$w_facility; /* TMS facility code */N unsigned short int mmecb$w_mbunit; /* Mailbox unit number */N unsigned int mmecb$l_pid; /* Pid of TMS process */N unsigned short int mmecb$w_size; /* Control block size 9*/N unsigned char mmecb$b_type; /* BLOCK TYPE CODE */N unsigned char mmecb$b_subtype; /* BLOCK SUBTYPE CODE */N struct _ucb *mmecb$l_mbxucb; /* Mailbox UCB address */N __union { /* Bitmask of interesting routines */. unsigned __int64 mmecb$q_routine_mask; __struct {( unsigned mmecb$v_unload : 1;' unsigned mmecb$v_alloc : 1;- unsigned mmecb$v 9_backup_file : 1;, unsigned mmecb$v_close_read : 1;- unsigned mmecb$v_close_write : 1;5 unsigned mmecb$v_continuation_volume : 1;, unsigned mmecb$v_deallocate : 1;. unsigned mmecb$v_device_avail : 1;0 unsigned mmecb$v_device_unavail : 1;* unsigned mmecb$v_dismount : 1;1 unsigned mmecb$v_display_message : 1;* unsigned mmecb$v_eov_read : 1;+ unsigned mmecb$v_eov_write : 1;, 9 unsigned mmecb$v_initialize : 1;' unsigned mmecb$v_mount : 1;/ unsigned mmecb$v_mount_request : 1;0 unsigned mmecb$v_newvol_request : 1;/ unsigned mmecb$v_notify_device : 1;+ unsigned mmecb$v_opcom_acp : 1;- unsigned mmecb$v_opcom_mount : 1;+ unsigned mmecb$v_open_read : 1;, unsigned mmecb$v_open_write : 1;/ unsigned mmecb$v_volume_online : 1;, unsigned mmecb$v_backup_en 9d : 1;. unsigned mmecb$v_backup_start : 1;/ unsigned mmecb$v_write_request : 1;+ unsigned mmecb$v_mount_end : 1;* unsigned mmecb$v_init_end : 1;, unsigned mmecb$v_newvol_end : 1;+ unsigned mmecb$v_dmtprcdel : 1;) unsigned mmecb$v_fill_0_ : 2;# } mmecb$r_routine_bits;# } mmecb$r_routines_overlay;N struct _mcl *mmecb$l_mcl_flink; /* Mount context list forward link */N struct _mcl *m 9mecb$l_mcl_blink; /* Mount context list backward link */ } MMECB; #if !defined(__VAXC)J#define mmecb$q_routine_mask mmecb$r_routines_overlay.mmecb$q_routine_maskS#define mmecb$v_unload mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_unloadQ#define mmecb$v_alloc mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_alloc]#define mmecb$v_backup_file mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_backup_file[#define mmecb$v_close_read mmecb$r_routines_overlay.mmecb$r_ro9utine_bits.mmecb$v_close_read]#define mmecb$v_close_write mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_close_writem#define mmecb$v_continuation_volume mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_continuation_volume[#define mmecb$v_deallocate mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_deallocate_#define mmecb$v_device_avail mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_device_availc#define mmecb$v_device_unavail mmecb$r_routines_overlay.mmecb$r_routine_bi9ts.mmecb$v_device_unavailW#define mmecb$v_dismount mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_dismounte#define mmecb$v_display_message mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_display_messageW#define mmecb$v_eov_read mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_eov_readY#define mmecb$v_eov_write mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_eov_write[#define mmecb$v_initialize mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_initializeQ#define 9mmecb$v_mount mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_mounta#define mmecb$v_mount_request mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_mount_requestc#define mmecb$v_newvol_request mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_newvol_requesta#define mmecb$v_notify_device mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_notify_deviceY#define mmecb$v_opcom_acp mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_opcom_acp]#define mmecb$v_opcom_mount mmecb$r_9routines_overlay.mmecb$r_routine_bits.mmecb$v_opcom_mountY#define mmecb$v_open_read mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_open_read[#define mmecb$v_open_write mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_open_writea#define mmecb$v_volume_online mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_volume_online[#define mmecb$v_backup_end mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_backup_end_#define mmecb$v_backup_start mmecb$r_routines_overlay.mmecb$r_rout9ine_bits.mmecb$v_backup_starta#define mmecb$v_write_request mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_write_requestY#define mmecb$v_mount_end mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_mount_endW#define mmecb$v_init_end mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_init_end[#define mmecb$v_newvol_end mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_newvol_endY#define mmecb$v_dmtprcdel mmecb$r_routines_overlay.mmecb$r_routine_bits.mmecb$v_dmtprcdel"#endif9 /* #if !defined(__VAXC) */ V#define MMECB$S_MMECBDEF 32 /* Old size name, synonym for MMECB$S_MMECB */#define MME$M_WAS_RUNNING 0x1 typedef struct _mmeflags {N __union { /* */' unsigned char mme$b_flags_mask; __struct {+ unsigned mme$v_was_running : 1;' unsigned mme$v_fill_1_ : 7; } mme$r_flags_bits; } mme$r_flags_overlay; } MMEFLAGS; 9#if !defined(__VAXC)=#define mme$b_flags_mask mme$r_flags_overlay.mme$b_flags_maskP#define mme$v_was_running mme$r_flags_overlay.mme$r_flags_bits.mme$v_was_running"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #end 9if /* __MMECBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. 9 **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **9/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */F/* Source: 24-JUN-2024 12:43:30 $1$DGA8345:[LIB_H.SRC]MMGDEF.SDL; 91 *//********************************************************************************************************************************//*** MODULE $MMGDEF ***/#ifndef __MMGDEF_LOADED#define __MMGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previou9sly-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union unio 9n#else#define __union variant_union#endif#endif P#define MMG$M_NO_MPL_FLUSH 4 /* Don't flush MPL on SVAPTE requests */N#define MMG$V_NO_MPL_FLUSH 2 /* (MMG$GL_FREWFLGS) */R#define MMG$M_NOWAIT 2 /* Don't allow FREWSLE to resource wait */N#define MMG$V_NOWAIT 1 /* on modified list back pressure */R#define MMG$M_NOLASTUPD 1 /* Don't allow FREWSLE to update WSLAST */S#define MMG$V_NOLASTUPD 0 9 /* (prevent WSLAST/WSSIZE interactions) */N#define MMG$M_TICK_ENABLE 1 /* TICKING enable bit (used by RSE) */N#define MMG$V_TICK_ENABLE 0 /* (MMG$GB_CTLFLAGS) */c#define MMG$M_TROLL_ENABLE 2 /* TROLLING enable bit (used by RSE, OSWPSCHED, SWAPPER) */N#define MMG$V_TROLL_ENABLE 1 /* (MMG$GB_CTLFLAGS) */^#define MMG$M_BOOTIME_MEMTEST 4 /* Test all memory at boot time flag (used by INIT) */N#define MMG$V_9BOOTIME_MEMTEST 2 /* (MMG$GB_CTLFLAGS) */k#define MMG$M_NO_MB 8 /* Set NO_MB bit in PTE (used by INIT, IOCIOPST, PAGEFAULT, etc) */N#define MMG$V_NO_MB 3 /* (MMG$GB_CTLFLAGS) */u#define MMG$M_GH_LIMITED 16 /* If set, GH regions cannot span page (used by SYS_GSZRO_64, SYS_REGIONS) */N#define MMG$V_GH_LIMITED 4 /* table pages (MMG$GB_CTLFLAGS) */n#define MMG$M_NO_PTCG 32 /* If set,9 IA64 TBI invalidates will not use (used by TBI_ROUTINES) */S#define MMG$V_NO_PTCG 5 /* ptc.g instructions (MMG$GB_CTLFLAGS) */d#define MMG$M_ALT_ALGO 64 /* If set take new algorithm in SYSCREDEL (DEL_SHPT_PAGE) */S#define MMG$V_ALT_ALGO 6 /* (MMG$GB_CTLFLAGS) (CLDNOTE 7855) */^#define MMG$M_SECTRC 128 /* Section Table tracing used by PHDUTL & SYSCREDEL */_#define MMG$V_SECTRC 7 /* (MMG$GB_CTLFLAGS) (CLDNOTE9 7206, 7855, 7935) */d#define MMG$M_EXEC_GH_LIMIT 256 /* If set, limit max GH for VMS Exec data huge page to 6. */P#define MMG$V_EXEC_GH_LIMIT 8 /* (MMG$GB_CTLFLAGS) (CLDNOTE 7983) */O#define MMG$M_DELCONPFN 512 /* Workaround for DELCONPFN bugcheck */Q#define MMG$V_DELCONPFN 9 /* (MMG$GB_CTLFLAGS) (QXCM1001354561) */O#define MMG$M_MULTI_PAGE 1024 /* Workaround for PAGOWNVIO bugcheck */W#define MMG$V_MULTI_PAGE 10 /* (MMG$G9B_CTLFLAGS) (Jira BO-1649, NS6705) */N#define MMG$M_TICK_ACT 1 /* TICKING activate bit */N#define MMG$V_TICK_ACT 0 /* (MMG$GL_RECLAIM_FLAGS) */O/* Define the limit beyond which an MPL flush must not be delayed. This MUST */N/* be less than MPW$C_MAXREQCNT (32), which is defined in WRTMFYPAG. */#define MMG$C_MPL_FLUSH_LIM 16N/* Define the maximum size of an object name string for a global section: */I/* []$ */I/* 1 + 5 + 1 + 23 + 1 + 43 bytes = 74; round to quad */#define MMG$C_SECOBJNAM_SIZE 80Y/* -F ,B,0 /* ending address of negated structure */N/* (needed to obtain length definition) */N#define MMG$K_LENGTH -40 /* size of scratch area */N#define MMG$C_LENGTH -40 /* size of scratch area */#define MMG$M_DELGBL9DON 0x1+#define MMG$M_RWAST_AT_IPL0_OCCURRED_PP 0x2#define MMG$M_CHGPAGFIL 0x1#define MMG$M_NOWAIT_IPL0 0x2#define MMG$M_NO_OVERMAP 0x4#define MMG$M_PARTIAL_FIRST 0x8#define MMG$M_PARTIAL_LAST 0x10 #define MMG$M_NO_IRP_DELETE 0x20#define MMG$M_DELPAG_NOP 0x40#define MMG$M_CLUSTER_DEL 0x80#define MMG$M_WINDOW 0x100 #define MMG$M_SHARED_L3PTS 0x200)#define MMG$M_RWAST_AT_IPL0_ALLOWED 0x400*#define MMG$M_RWAST_AT_IPL0_OCCURRED 0x800N#define MMG$S_MMGDEF 41 /* 9 Old size name - synonym */ @typedef struct _mmg { /* WARNING: aggregate has origin of -40 */< /* WARNING: aggregate element "mmg$l_pgflcnt" ignored */C /* WARNING: aggregate element "mmg$r_bufobj_overlay" ignored */= /* WARNING: aggregate element "mmg$l_vfyflags" ignored *// /* WARNING: aggregate element "" ignored */> /* WARNING: aggregate element "mmg$l_svstartva" ignored */= /* WARNING: aggregate element "mmg$l_pagesubr" ignored */> /* WARNING: aggregat 9e element "mmg$l_savretadr" ignored */> /* WARNING: aggregate element "mmg$l_calledipl" ignored */E /* WARNING: aggregate element "mmg$r_per_page_overlay" ignored */@ /* WARNING: aggregate element "mmg$l_access_mode" ignored */F /* WARNING: aggregate element "mmg$r_mmg_flags_overlay" ignored */ char mmgdef$$_fill_2; } MMG; #if !defined(__VAXC)6#define mmg$l_pagcnt mmg$r_bufobj_overlay.mmg$l_pagcnt4#define mmg$l_efblk mmg$r_bufobj_overlay.mmg$l_efblk<#define mmg$l_pe9r_page mmg$r_per_page_overlay.mmg$l_per_pageR#define mmg$v_delgbldon mmg$r_per_page_overlay.mmg$r_per_page_bits.mmg$v_delgbldonr#define mmg$v_rwast_at_ipl0_occurred_pp mmg$r_per_page_overlay.mmg$r_per_page_bits.mmg$v_rwast_at_ipl0_occurred_pp?#define mmg$l_mmg_flags mmg$r_mmg_flags_overlay.mmg$l_mmg_flagsT#define mmg$v_chgpagfil mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bits.mmg$v_chgpagfilX#define mmg$v_nowait_ipl0 mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bits.mmg$v_nowait_ipl0V#define mmg$v_no_o9vermap mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bits.mmg$v_no_overmap\#define mmg$v_partial_first mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bits.mmg$v_partial_firstZ#define mmg$v_partial_last mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bits.mmg$v_partial_last\#define mmg$v_no_irp_delete mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bits.mmg$v_no_irp_deleteV#define mmg$v_delpag_nop mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bits.mmg$v_delpag_nopX#define mmg$v_cluster_del mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bi 9ts.mmg$v_cluster_delN#define mmg$v_window mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bits.mmg$v_windowZ#define mmg$v_shared_l3pts mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bits.mmg$v_shared_l3ptsl#define mmg$v_rwast_at_ipl0_allowed mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bits.mmg$v_rwast_at_ipl0_allowedn#define mmg$v_rwast_at_ipl0_occurred mmg$r_mmg_flags_overlay.mmg$r_mmg_flags_bits.mmg$v_rwast_at_ipl0_occurred"#endif /* #if !defined(__VAXC) */ #define MMG$M_RES_MEM_ZERO 0x1#define MMG$M_RES_ 9MEM_GROUP 0x2#define MMG$M_RES_MEM_PTS 0x4 #define MMG$M_RES_MEM_GBLSEC 0x8 typedef struct _res_mem { __union {N unsigned int mmg$l_res_mem_flags; /* Reserved memory flags */ __struct {N unsigned mmg$v_res_mem_zero : 1; /* Pages need to be zeroed */O unsigned mmg$v_res_mem_group : 1; /* Group number match required */T unsigned mmg$v_res_mem_pts : 1; /* Reserved memory is for page tables */m unsigned mmg$v 9_res_mem_gblsec : 1; /* Reserved memory is for (group or system) global section. */' unsigned mmg$v_fill_2_ : 4;! } mmg$r_res_mem_bits; } mmg$r_res_mem_overlay; } RES_MEM; #if !defined(__VAXC)E#define mmg$l_res_mem_flags mmg$r_res_mem_overlay.mmg$l_res_mem_flagsV#define mmg$v_res_mem_zero mmg$r_res_mem_overlay.mmg$r_res_mem_bits.mmg$v_res_mem_zeroX#define mmg$v_res_mem_group mmg$r_res_mem_overlay.mmg$r_res_mem_bits.mmg$v_res_mem_groupT#define mmg$v_re 9s_mem_pts mmg$r_res_mem_overlay.mmg$r_res_mem_bits.mmg$v_res_mem_ptsZ#define mmg$v_res_mem_gblsec mmg$r_res_mem_overlay.mmg$r_res_mem_bits.mmg$v_res_mem_gblsec"#endif /* #if !defined(__VAXC) */ #define MMG$M_COLOR_MUST 0x1#define MMG$M_COLOR_RANDOM 0x2#define MMG$M_ZEROED 0x4#define MMG$M_CONTIG 0x8N#define MMG$K_NO_VPN -1 /* No VPN specified (-1) */N#define MMG$K_NO_RAD -1 /* No RAD specified (-1) */N#define MMG$K_BASE_RAD -2 9 /* Use the OS base RAD (-2) */ typedef struct _allocpfn_flags { __union {N unsigned int mmg$l_allocpfn_flags; /* Page flags */ __struct {N unsigned mmg$v_color_must : 1; /* Must return color specified */N unsigned mmg$v_color_random : 1; /* Return a random color */N unsigned mmg$v_zeroed : 1; /* Allocate zeroed page */R unsigned mmg$v_contig : 1; /* Allocate contiguo 9us PFNs for mapping */' unsigned mmg$v_fill_3_ : 4;' } mmg$r_allocpfn_flag_bits;' } mmg$r_allocpfn_flags_overlay; } ALLOCPFN_FLAGS; #if !defined(__VAXC)N#define mmg$l_allocpfn_flags mmg$r_allocpfn_flags_overlay.mmg$l_allocpfn_flags_#define mmg$v_color_must mmg$r_allocpfn_flags_overlay.mmg$r_allocpfn_flag_bits.mmg$v_color_mustc#define mmg$v_color_random mmg$r_allocpfn_flags_overlay.mmg$r_allocpfn_flag_bits.mmg$v_color_randomW#define mmg$v_zeroed mmg$r 9_allocpfn_flags_overlay.mmg$r_allocpfn_flag_bits.mmg$v_zeroedW#define mmg$v_contig mmg$r_allocpfn_flags_overlay.mmg$r_allocpfn_flag_bits.mmg$v_contig"#endif /* #if !defined(__VAXC) */ N/* */N/* values for "which list" constants returned by PTE/PFN checking routines */N/* */#define MMG$C_PRIVATE 1#define MMG$C_SHARED 2#define MMG$C_IO 3 9N/* WARNING: the various pooltypes are declared differently for different */N/* languages, and there are values already defined between 0 and 7. When */N/* adding a pooltype, make sure to not use an existing value and also */N/* make sure that all relevant languages are covered. */ !#if defined(__DoNotDefineThisQQ_)?/* For C we will use the ENUM below rather than these defines*/#define MMG$K_POOLTYPE_NPP 0#define MMG$K_POOLTYPE_BAP 1 #define MMG$K_POOL 9TYPE_MAXIMUM 2 #endif /*__DoNotDefineThisQQ_*/ typedef enum {, MMG$K_POOLTYPE_NPP=0,MMG$K_POOLTYPE_BAP, MMG$K_POOLTYPE_MAXIMUM,[ MMG$K_POOLTYPE_S2_NPP = 6, /* X86 only usage but cross compiler can not use condition 9/* The following constant is only used by USB drivers: */ MMG$K_POOLTYPE_UAP } MMG$POOL_TYPE;N/* */N/* The following constants are only used by SDA: 9 */N/* */I/* MMG$K_POOLTYPE_PAGED is the same as MMG$K_POOLTYPE_MAXIMUM */I/* MMG$K_POOLTYPE_P0 is MMG$K_POOLTYPE_PAGED + 1 */I/* MMG$K_POOLTYPE_P1 is MMG$K_POOLTYPE_P0 + 1 */I/* MMG$K_POOLTYPE_IMAGE is MMG$K_POOLTYPE_P1 + 1 */N/* */N/* If new pool types are added withi 9n MMG$K_POOLTYPE_MAXIMUM, these */N/* constants should be moved down and a corresponding change made to */N/* [SDA]EVAX_SDADEF.SDL */N/* */#define MMG$K_POOLTYPE_PAGED 2#define MMG$K_POOLTYPE_P0 3#define MMG$K_POOLTYPE_P1 4#define MMG$K_POOLTYPE_IMAGE 5N/* */N/* Return bitmask 9definitions for mmg$check_va_access */N/* */#define MMG$M_VA_VALID 0x1#define MMG$M_PTE_VALID 0x2#define MMG$M_K_READ 0x4#define MMG$M_K_WRITE 0x8#define MMG$M_K_EXEC 0x10#define MMG$M_PHYS_MEM 0x20#define MMG$M_IO_MEM 0x40#define MMG$M_UNK_MEM 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __l 9ongword#else#pragma __nomember_alignment#endiftypedef struct _check_va {#pragma __nomember_alignment __union {N unsigned int mmg$l_check_va_flags; /* Flags longword */ __struct {N unsigned mmg$v_va_valid : 1; /* VA is valid (not in any gaps) */N unsigned mmg$v_pte_valid : 1; /* VA's PTE is valid */N unsigned mmg$v_k_read : 1; /* VA is kernel readable */N unsigned mmg$v_k_write9 : 1; /* VA is kernel writable */N unsigned mmg$v_k_exec : 1; /* VA is kernel executable */N unsigned mmg$v_phys_mem : 1; /* VA maps real physical mem */N unsigned mmg$v_io_mem : 1; /* VA maps I/O space */Y unsigned mmg$v_unk_mem : 1; /* VA map unkonwn memory. If set, there is no */N/* I/O space data, so the VA could map I/O space. */" } mmg$r_check_va_bits;! } mm 9g$r_check_va_overlay; } CHECK_VA; #if !defined(__VAXC)H#define mmg$l_check_va_flags mmg$r_check_va_overlay.mmg$l_check_va_flagsP#define mmg$v_va_valid mmg$r_check_va_overlay.mmg$r_check_va_bits.mmg$v_va_validR#define mmg$v_pte_valid mmg$r_check_va_overlay.mmg$r_check_va_bits.mmg$v_pte_validL#define mmg$v_k_read mmg$r_check_va_overlay.mmg$r_check_va_bits.mmg$v_k_readN#define mmg$v_k_write mmg$r_check_va_overlay.mmg$r_check_va_bits.mmg$v_k_writeL#define mmg$v_k_exec mmg$r_check_va_over 9lay.mmg$r_check_va_bits.mmg$v_k_execP#define mmg$v_phys_mem mmg$r_check_va_overlay.mmg$r_check_va_bits.mmg$v_phys_memL#define mmg$v_io_mem mmg$r_check_va_overlay.mmg$r_check_va_bits.mmg$v_io_memN#define mmg$v_unk_mem mmg$r_check_va_overlay.mmg$r_check_va_bits.mmg$v_unk_mem"#endif /* #if !defined(__VAXC) */ N#define MMG$C_STACK_PROCESS 0 /* Process default stack */N#define MMG$C_STACK_KP 1 /* KP stack */N#define MMG$C_STACK_KTHREAD 92 /* Kernel thread stack */N#define MMG$C_JUST_I 1 /* Just instruction */N#define MMG$C_JUST_D 2 /* Just data */N#define MMG$C_BOTH_I_AND_D 3 /* Both instruction and data */N/* */N/* This structure is used by MMG$DELPAG_64 in SYSCREDEL to throttle the */N/* number of processes that are tearing down virtual a 9ddress space. */N/* */N/* It is recommended that this structure be allocated on a cache line */N/* boundary - 64 bytes for Alpha and 128 for IPF. */N/* */ typedef struct _delpag_mem {Q int mmg_del$l_throttle; /* Number of processes in the throttle */ int mmg_del$l_filler0;N unsigned s 9hort int mmg_del$w_size; /* STRUCTURE SIZE IN BYTES */N unsigned char mmg_del$b_type; /* STRUCTURE TYPE CODE */N unsigned char mmg_del$b_subtype; /* STRUCTURE SUB-TYPE CODE */ char mmg_del$b_fill_4_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif1 unsigned __int64 mmg_del$q_delpag_iterations;#pra9gma __nomember_alignmentN unsigned __int64 mmg_del$q_drop_avoided; /* MMG Drop Avoided */N unsigned __int64 mmg_del$q_timedout; /* Delpag MMG Hold Time Exceeded */S unsigned __int64 mmg_del$q_last_entered; /* Time (abstim_tics) of last entry */N unsigned __int64 mmg_del$q_throttled; /* Throttled entries to DELPAG */R unsigned __int64 mmg_del$q_nonthrottled; /* Non-Throttled entries to DELPAG */N/* Offset to next cache line 9 */ char mmg_del$b_filler1 [64];Q int mmg_del$l_waiters; /* Number of processes in the RW state */ char mmg_del$b_fill_5_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 mmg_del$q_total_waits; /* Total resource waits */#pragma __nomember_alignmentQ unsigned __int64 mmg_del$q_last_stall; /9* Time (abstim_tics) of last stall */Q int mmg_del$l_max_waiters; /* largest number of stalled processes */N/* offset to next cache line */! char mmg_del$b_filler2 [100];S int mmg_del$l_mmg_hold; /* MMG Hold time in 10 microsecond units */N int mmg_del$l_throttle_limit; /* Max allowed into DELPAG */N/* offset to next cache line */! char mmg_del$b_f9iller3 [120]; } DELPAG_MEM;N#define MMG_DEL$C_THROTTLE_VAS 256 /* VA count needed for throttling */N#define MMG_DEL$C_HOLD_MAX 100 /* Max MMG hold in 10us Units */N#define MMG_DEL$C_THROTTLE_DFLT 4 /* Default Throttle count */N#define MMG_DEL$C_HOLD_DFLT 7 /* Default MMG hold in 10us Units */N/* S2 NPP expansion state constants- allows SQA test to */N/* to read pms$gl_npagdynexpst_s2 to determine the state of S2 expansi 9on. */f#define MMG$C_EXP_UNAVAILABLE_S2 0 /* Expansion is NOT available in S2. No where to expand to. */d#define MMG$C_EXP_AVAIL_S2 1 /* S2 expansion is available and there is room to expand. */N#define MMG$C_EXP_MAXED_S2 2 /* S2 expansion is maxed out. */##define MMG$M_DISABLE_BP_BOOTMD 0x1"#define MMG$M_DISABLE_BP_SYSMD 0x2"#define MMG$M_DISABLE_BP_PFNDB 0x4$#define MMG$M_DISABLE_BP_REGIONS 0x8!#define MMG$M_DISABLE_BP_XFC 0x10!#define MMG$M_DISABLE_BP_G 9PT 0x20$#define MMG$M_DISABLE_BP_LCKMGR 0x40'#define MMG$M_UNDEFINED_7_30 0x7FFFFF80-#define MMG$M_ENABLE_TEST_GIGAPAGE 0x80000000N#define MMG$K_DISABLE_BP_ALL -1 /* Fully disable big page support */ typedef struct _big_page_flags { __union {N unsigned int mmg$l_big_page_flags; /* Big Page flags */ __struct {b unsigned mmg$v_disable_bp_bootmd : 1; /* Disable big pages for the boot memory disk */c unsigned mmg$v_disab9le_bp_sysmd : 1; /* Disable big pages for the system memory disk */] unsigned mmg$v_disable_bp_pfndb : 1; /* Disable big pages for the PFN database */] unsigned mmg$v_disable_bp_regions : 1; /* Disable big pages for the GH regions */R unsigned mmg$v_disable_bp_xfc : 1; /* Disable big pages for the XFC */` unsigned mmg$v_disable_bp_gpt : 1; /* Disable big pages for the global page table */^ unsigned mmg$v_disable_bp_lckmgr : 1; /* Disable b 9ig pages for the lock manager */N unsigned mmg$v_undefined_7_30 : 24; /* Unused bits */P unsigned mmg$v_enable_test_gigapage : 1; /* Enable a test gigapge */' } mmg$r_big_page_flag_bits;' } mmg$r_big_page_flags_overlay; } BIG_PAGE_FLAGS; #if !defined(__VAXC)N#define mmg$l_big_page_flags mmg$r_big_page_flags_overlay.mmg$l_big_page_flagsm#define mmg$v_disable_bp_bootmd mmg$r_big_page_flags_overlay.mmg$r_big_page_flag_bits.mmg$v_disa9ble_bp_bootmdk#define mmg$v_disable_bp_sysmd mmg$r_big_page_flags_overlay.mmg$r_big_page_flag_bits.mmg$v_disable_bp_sysmdk#define mmg$v_disable_bp_pfndb mmg$r_big_page_flags_overlay.mmg$r_big_page_flag_bits.mmg$v_disable_bp_pfndbo#define mmg$v_disable_bp_regions mmg$r_big_page_flags_overlay.mmg$r_big_page_flag_bits.mmg$v_disable_bp_regionsg#define mmg$v_disable_bp_xfc mmg$r_big_page_flags_overlay.mmg$r_big_page_flag_bits.mmg$v_disable_bp_xfcg#define mmg$v_disable_bp_gpt mmg$r_big_page_flags_ 9overlay.mmg$r_big_page_flag_bits.mmg$v_disable_bp_gptm#define mmg$v_disable_bp_lckmgr mmg$r_big_page_flags_overlay.mmg$r_big_page_flag_bits.mmg$v_disable_bp_lckmgrs#define mmg$v_enable_test_gigapage mmg$r_big_page_flags_overlay.mmg$r_big_page_flag_bits.mmg$v_enable_test_gigapage"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore9 the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MMGDEF_LOADED */ wwm[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized9 to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or9 disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7 9-Oct-2024 15:23:39 by OpenVMS SDL V3.7 */M/* Source: 02-NOV-2022 16:47:19 $1$DGA8345:[LIB_H.SRC]MMG_CONSTANTS.SDL;1 *//********************************************************************************************************************************/)/*** MODULE MMG_CONSTANTS IDENT X-20 ***/#ifndef __MMG_CONSTANTS_LOADED #define __MMG_CONSTANTS_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_a9lignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__V9AXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* There are three fundamental variables about the paging data structures: */I/* - size of a page in bytes */I/* - number of bytes in a PTE */I/* - number of levels of page table in a full translatio 9n */N/* Given these numbers, we can calculate many of the other values needed */N/* by memory management. */N/* */N/* These constants may be of general interest to VMS code. */#define MMG$C_BITS_PER_BYTE 8##define MMG$C_BITS_PER_BYTE_SHIFT 3##define MMG$C_BYTES_PER_PAGELET 512'#define MMG$C_BYTES_PER_PAGELET_SHIFT 9"#define MMG$C_BI 9TS_PER_QUADWORD 64'#define MMG$C_BITS_PER_QUADWORD_SHIFT 6"#define MMG$C_BYTES_PER_QUADWORD 8(#define MMG$C_BYTES_PER_QUADWORD_SHIFT 3N/* This next set of constants are specific to memory management. */#define MMG$$C_BYTES_PER_PTE 8$#define MMG$$C_BYTES_PER_PTE_SHIFT 3$#define MMG$$C_OFFSET_TO_PFN_SHIFT 3$#define MMG$$C_PFN_TO_OFFSET_SHIFT 3N/* Calculation conversion from Mbytes to 8K Pages */$#define MMG$$C_BYTES_PER_1MB 1048576%#define MMG$$C_BYTES_P 9ER_1MB_SHIFT 20 #define MMG$$C_PAGE8K_PER_MB 128$#define MMG$$C_PAGE8K_PER_MB_SHIFT 7$#define MMG$$C_BYTES_PER_2MB 2097152%#define MMG$$C_BYTES_PER_2MB_SHIFT 21N/* On x86, the number of levels of page tables is not an architectural */N/* constant: it can be either 4 or 5. So, some of the numbers we want */N/* must continue to be run-time "constants" calculated at boot time. */N/* This last set of constants are specific to x86 memory management. */ a#define MMG$$C9_BOFF_MASK_4K 0xFFFull /* mask for just the byte-offset bits on a 4-kB PFN */`#define MMG$$C_BOFF_MASK 0x1FFFull /* mask for just the byte-offset bits on an 8-kB page */c#define MMG$$C_BOFF_MASK_8K 0x1FFFull /* mask for just the byte-offset bits on an 8-kB page */a#define MMG$$C_BOFF_MASK_2M 0x1FFFFFull /* mask for just the byte-offset bits on a 2-MB PFN */b#define MMG$$C_BOFF_MASK_4M 0x3FFFFFull /* mask for just the byte-offset bits on a 4-MB page */a#define MMG$$C_BOFF_9MASK_1G 0x3FFFFFFFull /* mask for just the byte-offset bits on a 1-GB PFN */b#define MMG$$C_BOFF_MASK_2G 0x7FFFFFFFull /* mask for just the byte-offset bits on a 2-GB page */p#define MMG$$C_NON_BOFF_MASK_4K 0xFFFFFFFFFFFFF000ull /* mask for everything except byte offset on a 4-kB PFN */o#define MMG$$C_NON_BOFF_MASK 0xFFFFFFFFFFFFE000ull /* mask for everything except byte offset on an 8-kB page */r#define MMG$$C_NON_BOFF_MASK_8K 0xFFFFFFFFFFFFE000ull /* mask for everything except byte offset on9 an 8-kB page */p#define MMG$$C_NON_BOFF_MASK_2M 0xFFFFFFFFFFE00000ull /* mask for everything except byte offset on a 2-MB PFN */q#define MMG$$C_NON_BOFF_MASK_4M 0xFFFFFFFFFFC00000ull /* mask for everything except byte offset on a 4-MB page */p#define MMG$$C_NON_BOFF_MASK_1G 0xFFFFFFFFC0000000ull /* mask for everything except byte offset on a 1-GB PFN */q#define MMG$$C_NON_BOFF_MASK_2G 0xFFFFFFFF80000000ull /* mask for everything except byte offset on a 2-GB page */;#define MMG$$C_BYTES_PER_HW_9PAGE 4096ull /* HW PFN Size */  N/* These are commonly used symbols. Note, the PA/PFN shift is NOT EQUAL */N/* to the VA/VPN shift. */#define MMG$$C_BOFF_SIZE 13#define MMG$$C_BWP_WIDTH 13"#define MMG$$C_BYTES_PER_PAGE 8192!#define MMG$$C_PTE_SEGMENT_SIZE 9!#define MMG$$C_PA_TO_PFN_SHIFT 12#define MMG$$C_PAGE_SIZE 8192##define MMG$$C_PAGELETS_PER_PAGE 16!#define MMG$$C_PFN_TO_PA_SHIFT 12N#define MMG$$C_PTES_PER_PAGE 5 912 /* page table pages are always 4K */!#define MMG$$C_VA_TO_VPN_SHIFT 13!#define MMG$$C_VPN_TO_VA_SHIFT 13N/* This set is for the x86 architectural PFN size of 4 kB. */)#define MMG$$C_BYTES_PER_HW_PAGE_SHIFT 12#define MMG$$C_HW_BOFF_SIZE 12#define MMG$$C_HW_BWP_WIDTH 12 #define MMG$$C_HW_PAGE_SIZE 4096%#define MMG$$C_PAGELETS_PER_HW_PAGE 8$#define MMG$$C_VA_TO_HW_VPN_SHIFT 12$#define MMG$$C_HW_VPN_TO_VA_SHIFT 12N/* This set is for the page allocation size of 9 8 kB. */'#define MMG$$C_PA_TO_ALLOC_PFN_SHIFT 13'#define MMG$$C_ALLOC_PFN_TO_PA_SHIFT 13N/* This set is for a PFN size of 2 MB. */)#define MMG$$C_BYTES_PER_2MB_PAGE 2097152*#define MMG$$C_BYTES_PER_2MB_PAGE_SHIFT 21$#define MMG$$C_PAGE_SIZE_2MB 2097152)#define MMG$$C_PAGELETS_PER_2MB_PAGE 4096#define MMG$$C_BWP_WIDTH_2MB 21%#define MMG$$C_PA_TO_2MB_PFN_SHIFT 21%#define MMG$$C_PFN_2MB_TO_PA_SHIFT 21%#define MMG$$C_VA_TO_2MB 9_VPN_SHIFT 21%#define MMG$$C_VPN_2MB_TO_VA_SHIFT 21N/* This set is for a page size of 4 MB. */)#define MMG$$C_BYTES_PER_4MB_PAGE 4194304*#define MMG$$C_BYTES_PER_4MB_PAGE_SHIFT 22$#define MMG$$C_PAGE_SIZE_4MB 4194304)#define MMG$$C_PAGELETS_PER_4MB_PAGE 8192#define MMG$$C_BWP_WIDTH_4MB 22%#define MMG$$C_PA_TO_4MB_PFN_SHIFT 22%#define MMG$$C_PFN_4MB_TO_PA_SHIFT 22%#define MMG$$C_VA_TO_4MB_VPN_SHIFT 22%#define MMG$$C_VPN_4MB_TO_VA_SHIFT 22N/* Thi 9s set is for a PFN size of 1 GB. */,#define MMG$$C_BYTES_PER_1GB_PAGE 1073741824*#define MMG$$C_BYTES_PER_1GB_PAGE_SHIFT 30'#define MMG$$C_PAGE_SIZE_1GB 1073741824,#define MMG$$C_PAGELETS_PER_1GB_PAGE 2097152#define MMG$$C_BWP_WIDTH_1GB 30%#define MMG$$C_PA_TO_1GB_PFN_SHIFT 30%#define MMG$$C_PFN_1GB_TO_PA_SHIFT 30%#define MMG$$C_VA_TO_1GB_VPN_SHIFT 30%#define MMG$$C_VPN_1GB_TO_VA_SHIFT 30N/* This set is for a page size of 2 GB. 9 */,#define MMG$$C_BYTES_PER_2GB_PAGE 2147483648*#define MMG$$C_BYTES_PER_2GB_PAGE_SHIFT 31'#define MMG$$C_PAGE_SIZE_2GB 2147483648,#define MMG$$C_PAGELETS_PER_2GB_PAGE 4194304#define MMG$$C_BWP_WIDTH_2GB 31%#define MMG$$C_PA_TO_2GB_PFN_SHIFT 31%#define MMG$$C_PFN_2GB_TO_PA_SHIFT 31%#define MMG$$C_VA_TO_2GB_VPN_SHIFT 31%#define MMG$$C_VPN_2GB_TO_VA_SHIFT 31O/* The PFN_TO_PFNDBIDX constants are the number of bit positions a PFN needs */N/* to be shifted to produce an i9ndex into the PFNDB. The PFNDB */R/* operates on 8K increments. Note that for a 4 kB x86 PFN, the shift is right */N/* and for a 2 MB and 1 GB PFN, the shift is a left shift. */N#define MMG$$C_PFN_TO_PFNDBIDX_4K 1 /* Right Shift */N#define MMG$$C_PFN_TO_PFNDBIDX_2M 8 /* Left Shift */N#define MMG$$C_PFN_TO_PFNDBIDX_2MB 8 /* Left Shift, to be retired */N#define MMG$$C_PFN_TO_PFNDBIDX_1G 17 /* Left Shift 9 */N/* Starting (low-order) bit number of PT segments */N/* Equivalently, the number of bits to shift RIGHT to place the indicated */N/* PT INDEX so that it starts at bit 0. This number can be used as */N/* an index into a page table typed as PTE_PQ. */#define MMG$$C_BPT_BITPOS 12#define MMG$$C_PD_BITPOS 21#define MMG$$C_PDPT_BITPOS 30#define MMG$$C_PML4_BITPOS 39#define MMG$$C_PML5_BITPOS 48N/* T 9he number of bits to shift RIGHT to place the indicated PT OFFSET */N/* so that it starts at bit 3, thus making it an offset into a page */N/* table typed as INT64, PTE_PQ, or equivalent. Caller must make sure */N/* the low 3 bits are zero. */#define MMG$$C_BPT_OFFPOS 9#define MMG$$C_PD_OFFPOS 18#define MMG$$C_PDPT_OFFPOS 27#define MMG$$C_PML4_OFFPOS 36#define MMG$$C_PML5_OFFPOS 45N/* Masks to extract the indicated 9PT segment from an address. */N/* Typical usage is to apply the mask to get the segment value */N/* then shift it as needed. */W/* In order to get the masks to appear to generate as hex values vs. decimal values, */N/* the masks have been placed into a structure as bitfield masks. */ $#define MMG$$C_SEGMENT_MASK 0x1FFullC#define MMG$$C_BPT_MASK (MMG$$C_SEGMENT_MASK << MMG$$C_BPT_BITPOS)B#define MMG$$C_PD_ 9MASK (MMG$$C_SEGMENT_MASK << MMG$$C_PD_BITPOS)D#define MMG$$C_PDPT_MASK (MMG$$C_SEGMENT_MASK << MMG$$C_PDPT_BITPOS)D#define MMG$$C_PML4_MASK (MMG$$C_SEGMENT_MASK << MMG$$C_PML4_BITPOS)D#define MMG$$C_PML5_MASK (MMG$$C_SEGMENT_MASK << MMG$$C_PML5_BITPOS)  N/* Masks to extract combined fields for indexing into a page table from */N/* its base address cannot be defined as compile-time constants since */N/* their values depend on whether 4- or 5-level paging is enabled. */9N/* This is only known at boot time. */\/* Create constants with the number of entries and the size of 4 and 5 level page tables. */N/* These values are not available in in bliss32. */ N/*+ */N/* Define constants to assist walking the per mode X86 page tables. */N/*- */N/* 4 l9evels of 512 segments */N/* 5 levels of 512 segments */,#define MMG$$C_LEVEL4_PT_ENTRIES 68719476736/#define MMG$$C_LEVEL5_PT_ENTRIES 35184372088832*#define MMG$$C_LEVEL4_PT_SIZE 549755813888-#define MMG$$C_LEVEL5_PT_SIZE 281474976710656N/*+ */X/* Add an X86 constant for the end of S0S1 space. The S0S1 region ends 64KB short o 9f */N/* the end of the region so that it matches Alpha/IA64. */N/*- */ i#define MMG$$C_MAX_S0S1 0xFFFFFFFFFFFF0000ull /* mask for everything except byte offset on a 2-GB page */  N/*+ */N/* The x86 constant for the number of 8KB global pages when GBLPAGES (the */N/* number of 512B pagelets) is the maximum of -1. The value 9is 0x10000000. */N/*- */)#define MMG$$C_MAX_GLOBAL_PAGES 268435456 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard ##endif /* __MMG_CONSTANTS_LOADED */ ww[UM/*9**************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett9-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. 9 **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */I/* Source: 23-JUN-2004 13:16:13 $1$DGA8345:[LIB_H.SRC]RMSPUBSTR.SDL;1 *//*********************************************** 9*********************************************************************************//*** MODULE $MODDEF ***/#ifndef __MODDEF_LOADED#define __MODDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_p9ointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#e 9ndif N/* */N/* RMS MODify definitions */N/* */N/* The following values identify various requests for non-standard rms */N/* functions. They are currently input to the $modify function in the */N/* ctx field of the fab only if the esc bit is set in fop (rab functions */N/* are also acc9epted). Incorrect use of these capabilties could cause */N/* RMS to fail, hence great caution should be exercised in their use. */N/* */N/* These functions are also called RME$C_xxxx. They are defined */N/* in the public module [STARLET]RMSUSR.SDL and cannot be changed. */N/* Any addition made to $MODDEF in this module should also be made to */N/* $RMEDEF in that module. 9 */N/* */N/* FAB function calls */]#define MOD$C_SETRFM 1 /* change rfm, mrs, and fsz (if vfc) in ifab only */T#define MOD$C_PPFECHO 2 /* enable echo of SYS$INPUT to SYS$OUTPUT */N#define MOD$C_SETRCF 3 /* change recovery mode */N#define MOD$C_KEEP_LOCK_ON 4 /* Tur9n on Keep Lock behavior */N#define MOD$C_KEEP_LOCK_OFF 5 /* Turn off Keep Lock behavior */N#define MOD$C_RU_ACE_ON 6 /* Turn on RU ACE locking */N#define MOD$C_RU_ACE_OFF 7 /* Turn off RU ACE locking */g#define MOD$C_SET_RECATTR 8 /* change rfm, org, rat, mrs, and fsz (if vfc) in ifab only */N/* RAB function calls */N#define MOD$C_LOCK_RECORD 1 /* Loc9k a record */S#define MOD$C_ASSOCIATE 2 /* Associate a stream with a transaction */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MODDEF_LOADED */ ww01[UM/*********************************9******************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development,9 LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 9 **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */F/* Source: 22-JAN-2009 08:07:03 $1$DGA8345:[LIB_H.SRC]MONDEF.SDL;1 *//*********************************************************************************** :*********************************************//*** MODULE $mondef ***/#ifndef __MONDEF_LOADED#define __MONDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr: size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* Monitor Recording File :Definitions */ #include N#define MON$C_MAX_CPUS 1024 /* maximum number of CPUs possible */#define MON$K_CBB_SIZE 176^/****************************************************************************************** */N/* */I/* FILE header record format */N/* : */N/* Max length of user comment string */#define MNR_HDR$K_CLASSBITS 128#define MNR_HDR$K_REVLEVELS 144#define MNR_HDR$K_SIZE 272S#define MNR_HDR$K_MAXCOMLEN 60 /* constant for user comment string size */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _file_hdr {#p:ragma __nomember_alignmentN unsigned char mnr_hdr$b_type; /* Unsigned record type */N __struct { /* Flags */] unsigned mnr_hdr$v_rewrite : 1; /* YES -> Rewrite operation completed successfully */N unsigned mnr_hdr$v_filler : 31; /* Fill out rest of longword */ } mnr_hdr$l_flags; char mnr_hdr$b_fill_0_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre :DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif\ __int64 mnr_hdr$q_beginning; /* Beginning time of request in system time units */#pragma __nomember_alignmentY __int64 mnr_hdr$q_ending; /* Ending time of request in system time units */N int mnr_hdr$l_interval; /* Interval value in seconds */ char mnr_hdr$b_fill_1_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* : If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endif/ unsigned __int64 mnr_hdr$o_rev0clsbits [2];N/* Bit string of recorded classes which are at rev 0 */N/* NOTE -- The above item is included for compatibility with */N/* MONITOR structure levels MONSL001 and MONBA001 */#pragma __nomember_alignment\ int mnr_hdr$l_recct; /* Count of all record:s in the file (incl header) */ __union {c char mnr_hdr$t_level [8]; /* MONITOR Recording File structure level identification */c char mnr_hdr$t_ident [8]; /* MONITOR Recording File structure level identification */" } mnr_hdr$r_ident_overlay;N char mnr_hdr$t_comment [60]; /* User comment string */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longw:ord#else#pragma __nomember_alignment#endifR short int mnr_hdr$w_comlen; /* Actual length of user comment string */#pragma __nomember_alignment char mnr_hdr$b_fill_2_ [6];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned int mnr_hdr$o_classbits [4]; /* Bit string of recorded classes */#pragma __nomember_alignmentO ch :ar mnr_hdr$t_revlevels [128]; /* Rev level for each recorded class */ } FILE_HDR; #if !defined(__VAXC);#define mnr_hdr$v_rewrite mnr_hdr$l_flags.mnr_hdr$v_rewrite9#define mnr_hdr$v_filler mnr_hdr$l_flags.mnr_hdr$v_filler?#define mnr_hdr$t_level mnr_hdr$r_ident_overlay.mnr_hdr$t_level?#define mnr_hdr$t_ident mnr_hdr$r_ident_overlay.mnr_hdr$t_ident"#endif /* #if !defined(__VAXC) */ "#define MNR_OLDHDR$K_CLASSBITS 115"#define MNR_OLDHDR$K_REVLEVELS 131#define MNR_OLDHDR$K :_SIZE 259S#define MNR_OLDHDR$K_MAXCOMLEN 60 /* constant for user comment string size */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _file_hdr_old {#pragma __nomember_alignmentN unsigned char mnr_oldhdr$b_type; /* Unsigned record type */N __struct { /* Flags  : */` unsigned mnr_oldhdr$v_rewrite : 1; /* YES -> Rewrite operation completed successfully */N unsigned mnr_oldhdr$v_filler : 31; /* Fill out rest of longword */ } mnr_oldhdr$l_flags;\ __int64 mnr_oldhdr$q_beginning; /* Beginning time of request in system time units */Y __int64 mnr_oldhdr$q_ending; /* Ending time of request in system time units */N int mnr_oldhdr$l_interval; /* Interval value in seconds */2 unsigned __int64 m :nr_oldhdr$o_rev0clsbits [2];N/* Bit string of recorded classes which are at rev 0 */N/* NOTE -- The above item is included for compatibility with */N/* MONITOR structure levels MONSL001 and MONBA001 */\ int mnr_oldhdr$l_recct; /* Count of all records in the file (incl header) */ __union {c char mnr_oldhdr$t_level [8]; /* MONITOR Recording File structure level identification */c char mnr_oldhdr$ :t_ident [8]; /* MONITOR Recording File structure level identification */% } mnr_oldhdr$r_ident_overlay;N char mnr_oldhdr$t_comment [60]; /* User comment string */R short int mnr_oldhdr$w_comlen; /* Actual length of user comment string */Q unsigned int mnr_oldhdr$o_classbits [4]; /* Bit string of recorded classes */O char mnr_oldhdr$t_revlevels [128]; /* Rev level for each recorded class */" char mnr_oldhdr$b_fill_3_ [5]; } FILE_HDR_OLD; : #if !defined(__VAXC)D#define mnr_oldhdr$v_rewrite mnr_oldhdr$l_flags.mnr_oldhdr$v_rewriteB#define mnr_oldhdr$v_filler mnr_oldhdr$l_flags.mnr_oldhdr$v_fillerH#define mnr_oldhdr$t_level mnr_oldhdr$r_ident_overlay.mnr_oldhdr$t_levelH#define mnr_oldhdr$t_ident mnr_oldhdr$r_ident_overlay.mnr_oldhdr$t_ident"#endif /* #if !defined(__VAXC) */ ^/****************************************************************************************** */N/* : */I/* SYSTEM information record format */N/* */#define MNR_SYI$K_SIZE 244 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sys_info {#pragma __nomember_alignmentN unsigned char mnr_syi$b_type; /* Unsig:ned record type */N char mnr_syi$b_spare2; /* */N __struct { /* Flags */W unsigned mnr_syi$v_clusmem : 1; /* YES => this node is a member of a cluster */N unsigned mnr_syi$v_reserved1 : 1; /* Reserved bit */N unsigned mnr_syi$v_vm : 1; /* YES => this node is vm */N unsigned mnr_syi$v_ht : 1; /* YES => hyper thread e :nabled */N unsigned mnr_syi$v_filler : 12; /* Fill out rest of word */ } mnr_syi$w_flags; char mnr_syi$b_fill_4_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif\ __int64 mnr_syi$q_boottime; /* Absolute system boot time in system time units */#pragma __nomember_alignmentN short int mnr_syi$w_maxprcct; : /* MAXPROCESSCNT SYSGEN parameter */ __union {N short int mnr_syi$w_mpcpus; /* Number of multiprocessing CPUs */N char mnr_syi$b_mpcpus; /* Number of multiprocessing CPUs */# } mnr_syi$r_mpcpus_overlay; char mnr_syi$b_fill_5_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif! char mnr_syi$t_nod :ename [16];N/* DECnet node name of data source node */#pragma __nomember_alignmentN int mnr_syi$l_balsetmem; /* Balance set memory (in pages) */V int mnr_syi$l_mpwhilim; /* Modified Page List high limit (in pages) */N int mnr_syi$l_cputype; /* CPU type code (in binary) */N char mnr_syi$b_index; /* Node table index for this node */ char mnr_syi$b_fill_6_ [3];c#if !defined(__NOBAS :EALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB mnr_syi$cbb_cpuconf; /* Embedded CBB block */N __struct { /* Compatability offset cells */- __int64 mnr_syi$q_cbb_fill_1 [6]; __union {N unsigned int mnr_syi$l_cpuconf; /* Active :CPU mask */1 } mnr_syi$r_cpuconf_data_overlay;' char mnr_syi$b_fill_7_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif. __int64 mnr_syi$q_cbb_fill_2 [15];/ } mnr_syi$r_cpuconf_compat_overlay;$ } mnr_syi$r_cpuconf_overlay;#pragma __nomember_alignmentN char mnr_syi$b_vpcpus; : /* Number of vector processor CPUs */ char mnr_syi$b_fill_8_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifb int mnr_syi$l_vpconf; /* Bitmask representing the system VP CPU configuration */#pragma __nomember_alignment int mnr_syi$l_spare1; char mnr_syi$b_fill_9_ [4]; } SYS_INFO; #if !defined(__VAXC); :#define mnr_syi$v_clusmem mnr_syi$w_flags.mnr_syi$v_clusmem?#define mnr_syi$v_reserved1 mnr_syi$w_flags.mnr_syi$v_reserved11#define mnr_syi$v_vm mnr_syi$w_flags.mnr_syi$v_vm1#define mnr_syi$v_ht mnr_syi$w_flags.mnr_syi$v_ht9#define mnr_syi$v_filler mnr_syi$w_flags.mnr_syi$v_fillerB#define mnr_syi$w_mpcpus mnr_syi$r_mpcpus_overlay.mnr_syi$w_mpcpusB#define mnr_syi$b_mpcpus mnr_syi$r_mpcpus_overlay.mnr_syi$b_mpcpusI#define mnr_syi$cbb_cpuconf mnr_syi$r_cpuconf_overlay.mnr_syi$cbb_cpuconf#d:efine mnr_syi$l_cpuconf mnr_syi$r_cpuconf_overlay.mnr_syi$r_cpuconf_compat_overlay.mnr_syi$r_cpuconf_data_overlay.mnr_syi$l_cpuco\nf"#endif /* #if !defined(__VAXC) */ #define MNR_OLDSYI$K_SIZE 52 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sys_info_old {#pragma __nomember_alignmentN unsigned char mnr_oldsyi$b_type; /* U:nsigned record type */N __struct { /* Flags */Z unsigned mnr_oldsyi$v_clusmem : 1; /* YES => this node is a member of a cluster */N unsigned mnr_oldsyi$v_reserved1 : 1; /* Reserved bit */N unsigned mnr_oldsyi$v_filler : 14; /* Fill out rest of word */ } mnr_oldsyi$w_flags;\ __int64 mnr_oldsyi$q_boottime; /* Absolute system boot time in system time units */N short in:t mnr_oldsyi$w_maxprcct; /* MAXPROCESSCNT SYSGEN parameter */N char mnr_oldsyi$b_mpcpus; /* Number of multiprocessing CPUs */R char mnr_oldsyi$t_nodename [16]; /* DECnet node name of data source node */N int mnr_oldsyi$l_balsetmem; /* Balance set memory (in pages) */V int mnr_oldsyi$l_mpwhilim; /* Modified Page List high limit (in pages) */N int mnr_oldsyi$l_cputype; /* CPU type code (in binary) */N char mnr_oldsyi$b_inde :x; /* Node table index for this node */& unsigned int mnr_oldsyi$l_cpuconf;N char mnr_oldsyi$b_vpcpus; /* Number of vector processor CPUs */b int mnr_oldsyi$l_vpconf; /* Bitmask representing the system VP CPU configuration */# char mnr_oldsyi$b_fill_10_ [4]; } SYS_INFO_OLD; #if !defined(__VAXC)D#define mnr_oldsyi$v_clusmem mnr_oldsyi$w_flags.mnr_oldsyi$v_clusmemH#define mnr_oldsyi$v_reserved1 mnr_oldsyi$w_flags.mnr_oldsyi$v_reserved1B#d :efine mnr_oldsyi$v_filler mnr_oldsyi$w_flags.mnr_oldsyi$v_filler"#endif /* #if !defined(__VAXC) */ ^/****************************************************************************************** */N/* */I/* NODE transition record format */N/* */#define MNR_NTR$K_SIZE 8 c#if !defined(__NOBASEALIGN_SUPPORT) & :& !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _node_trans {#pragma __nomember_alignmentN unsigned char mnr_ntr$b_type; /* record type identifier */N char mnr_ntr$b_index; /* node index */N short int mnr_ntr$w_spare1; /* */N int mnr_ntr$l_spare2; /* : */ } NODE_TRANS;^/****************************************************************************************** */N/* */I/* RMS file record format */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_ali :gnment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rms_file {#pragma __nomember_alignmentN unsigned char mnr_fil$b_type; /* Record type identifier */" char mnr_fil$t_filename [256]; char mnr_fil$b_fill_11_ [7]; } RMS_FILE;^/****************************************************************************************** */N/* */I/* CLASS header and prefix record form :at */N/* */#define MNR_CLS$K_SIZE 16#define MNR_CLS$K_HSIZE 16#define MNR_CLS$K_PROCESSES 0#define MNR_CLS$K_STATES 1#define MNR_CLS$K_MODES 2#define MNR_CLS$K_PAGE 3#define MNR_CLS$K_IO 4#define MNR_CLS$K_FCP 5#define MNR_CLS$K_POOL 6#define MNR_CLS$K_LOCK 7#define MNR_CLS$K_DECNET 8#define MNR_CLS$K_VMS2 9#define MNR_CLS$K_VMS3 10&#define MNR_CLS$K_FILE_SYSTEM_CACH!:E 11#define MNR_CLS$K_DISK 12#define MNR_CLS$K_JDEVICE 13#define MNR_CLS$K_DLOCK 14#define MNR_CLS$K_SCS 15#define MNR_CLS$K_VMS1 16#define MNR_CLS$K_SYSTEM 17#define MNR_CLS$K_ETHERNET 18#define MNR_CLS$K_CLUSTER 19#define MNR_CLS$K_RMS 20 #define MNR_CLS$K_MSCP_SERVER 21 #define MNR_CLS$K_TRANSACTION 22#define MNR_CLS$K_VECTOR 23#define MNR_CLS$K_VBS 24#define MNR_CLS$K_MVBS 25#define MNR_CLS$K_TIMER 26#define MNR_CLS$K_RLOCK 27#define MNR_CLS$K_ALIGN 28#defin ":e MNR_CLS$K_MAX_CLSNO 28#define MNR_CLS$K_ALL_CLSNO 29 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _class_hdr {#pragma __nomember_alignmentN char mnr_cls$b_type; /* Unsigned record type */N __struct { /* Flags */a unsigned mnr_cls$v_cont : #:1; /* The data for this interval continues in next record */N unsigned mnr_cls$v_filler : 7; /* Fill out rest of byte */ } mnr_cls$b_flags;N char mnr_cls$b_index; /* Node table index */ char mnr_cls$b_fill_12_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */##pragma __nomember_alignment __word#else#pragma __nomember_alignment#endifN short int mnr_cls$w_reserved; $: /* Reserved field */#pragma __nomember_alignment char mnr_cls$b_fill_13_ [2];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 mnr_cls$q_stamp; /* System time of collection */ } CLASS_HDR; #if !defined(__VAXC)5#define mnr_cls$v_cont mnr_cls$b_flags.mnr_cls$v_cont9#define mnr_cls$v_filler mnr %:_cls$b_flags.mnr_cls$v_filler"#endif /* #if !defined(__VAXC) */ #define MNR_OLDCLS$K_SIZE 13#define MNR_OLDCLS$K_HSIZE 13 typedef struct _class_hdr_old {#pragma __nomember_alignmentN char mnr_oldcls$b_type; /* Unsigned record type */N __struct { /* Flags */a unsigned mnr_oldcls$v_cont : 1; /* The data for this interval continues in next record */N unsigned mnr_oldcls$v_filler : 7; /* &: Fill out rest of byte */ } mnr_oldcls$b_flags;N char mnr_oldcls$b_index; /* Node table index */N __int64 mnr_oldcls$q_stamp; /* System time of collection */N short int mnr_oldcls$w_reserved; /* Reserved field */# char mnr_oldcls$b_fill_14_ [3]; } CLASS_HDR_OLD; #if !defined(__VAXC)>#define mnr_oldcls$v_cont mnr_oldcls$b_flags.mnr_oldcls$v_contB#define mnr_oldcls$v_filler mnr_oldcls$b_flags.m':nr_oldcls$v_filler"#endif /* #if !defined(__VAXC) */ #define MNR_CMP$K_SIZE 8#define MNR_CMP$K_PSIZE 8 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _class_pre {#pragma __nomember_alignmentN int mnr_cmp$l_eltct; /* count of elements in this record */q int mnr_cmp$l_pctint; /* count of proces(:ses for this interval (only valid for PROCESS class) */ } CLASS_PRE;#define MNR_HOM$K_SIZE 8#define MNR_HOM$K_PSIZE 8 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _class_hom {#pragma __nomember_alignmentN int mnr_hom$l_eltct; /* count of elements in this record */N int mnr_hom$l_reserved; /* ): reserved */ } CLASS_HOM;^/****************************************************************************************** */N/* */I/* ALIGN class record format */N/* */#define MNR_ALI$K_SIZE 16 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V *:4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _align_class {#pragma __nomember_alignmentN int mnr_ali$l_align_kernel; /* kernel mode alignment faults */N int mnr_ali$l_align_exec; /* exec mode alignment faults */N int mnr_ali$l_align_super; /* super mode alignment faults */N int mnr_ali$l_align_user; /* user mode alignment faults */ } ALIGN_CLASS;^+:/****************************************************************************************** */N/* */I/* CLUSTER class record format */N/* */#define MNR_CLU$K_SIZE 52 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword ,:#else#pragma __nomember_alignment#endiftypedef struct _cluster_class {#pragma __nomember_alignmentN int mnr_clu$l_cpu_busy; /* CPU busy */N int mnr_clu$l_frlist; /* number of pages on freelist */N int mnr_clu$l_reserved; /* reserved field */N int mnr_clu$l_total_locks; /* total lock requests */N int mnr_clu$l_enqnewloc; /* enqueue requests (local) -: */N int mnr_clu$l_enqnewin; /* enqueue requests (incoming) */N int mnr_clu$l_enqnewout; /* enqueue requests (outgoing) */N int mnr_clu$l_enqcvtloc; /* conversion requests (local) */N int mnr_clu$l_enqcvtin; /* conversion requests (incoming) */N int mnr_clu$l_enqcvtout; /* conversion requests (outgoing) */N int mnr_clu$l_deqloc; /* dequeue requests (local) */N int mnr_clu$l_de.:qin; /* dequeue requests (incoming) */N int mnr_clu$l_deqout; /* dequeue requests (outgoing) */ char mnr_clu$b_fill_15_ [4]; } CLUSTER_CLASS;^/****************************************************************************************** */N/* */I/* DECNET class record format */N/* /: */#define MNR_NET$K_SIZE 20 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _decnet_class {#pragma __nomember_alignmentN int mnr_net$l_arrlocpk; /* arriving local packets */N int mnr_net$l_deplocpk; /* departing local packets */N int mnr_net$l_arrtrapk; 0:/* arriving transit packets */N int mnr_net$l_trcnglos; /* transit packet lost */N int mnr_net$l_rcvbuffl; /* receive buffer failures */ char mnr_net$b_fill_16_ [4]; } DECNET_CLASS;^/****************************************************************************************** */N/* */I/* DISK class record format */ 1:N/* */N#define MNR_DSK$C_DISK_REV 6 /* current revision is 6 */#define MNR_DSK$K_SIZE 44 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _disk_class {#pragma __nomember_alignmentN short int mnr_dsk$w_allocls; /* Allocation class 2: */N short int mnr_dsk$w_unitno; /* Unit number */N int mnr_dsk$t_ctrlr; /* Device name */X char mnr_dsk$b_flags; /* Flags byte (low bit indicates served disk) */N char mnr_dsk$b_rev; /* revision */N short int mnr_dsk$w_mbz; /* must-be-zero */N int mnr_dsk$l_spare1; /* spare */ 3:c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 mnr_dsk$t_nodename; /* Nodename */#pragma __nomember_alignment __union {N char mnr_dsk$t_volname [12]; /* Volume name */ __struct {N __int64 mnr_dsk$q_volnamel; /* Volume name (low) */N 4: int mnr_dsk$l_volnameh; /* Volume name (high) */' } mnr_dsk$r_volname_fields;$ } mnr_dsk$r_volname_overlay;N int mnr_dsk$l_opcnt; /* Operation count */N int mnr_dsk$l_ioqueln; /* Queue length accumulator */ char mnr_dsk$b_fill_17_ [4]; } DISK_CLASS; #if !defined(__VAXC)E#define mnr_dsk$t_volname mnr_dsk$r_volname_overlay.mnr_dsk$t_volname`#define mnr_dsk$q_volnamel mnr_dsk$r_vol 5:name_overlay.mnr_dsk$r_volname_fields.mnr_dsk$q_volnamel`#define mnr_dsk$l_volnameh mnr_dsk$r_volname_overlay.mnr_dsk$r_volname_fields.mnr_dsk$l_volnameh"#endif /* #if !defined(__VAXC) */ N#define MNR_OLDDSK$C_DISK_REV 5 /* old format revision is 5 */#define MNR_OLDDSK$K_SIZE 37 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypede6:f struct _olddisk_class {#pragma __nomember_alignmentN short int mnr_olddsk$w_allocls; /* Allocation class */N int mnr_olddsk$t_ctrlr; /* Device name */N short int mnr_olddsk$w_unitno; /* Unit number */X char mnr_olddsk$b_flags; /* Flags byte (low bit indicates served disk) */N __int64 mnr_olddsk$t_nodename; /* Nodename */N __int64 mnr_olddsk$t_volnamel; 7: /* Volume name (low) */N int mnr_olddsk$t_volnameh; /* Volume name (high) */N int mnr_olddsk$l_opcnt; /* Operation count */N int mnr_olddsk$l_ioqueln; /* Queue length accumulator */# char mnr_olddsk$b_fill_18_ [3]; } OLDDISK_CLASS;^/****************************************************************************************** */N/* 8: */I/* DLOCK class record format */N/* */#define MNR_DLO$K_SIZE 60 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _dlock_class {#pragma __nomember_alignmentN int mnr_dlo$l_enqnewloc; /* enqueue req9:uests (local) */N int mnr_dlo$l_enqnewin; /* enqueue requests (incoming) */N int mnr_dlo$l_enqnewout; /* enqueue requests (outgoing) */N int mnr_dlo$l_enqcvtloc; /* conversion requests (local) */N int mnr_dlo$l_enqcvtin; /* conversion requests (incoming) */N int mnr_dlo$l_enqcvtout; /* conversion requests (outgoing) */N int mnr_dlo$l_deqloc; /* dequeue requests (local) */N:: int mnr_dlo$l_deqin; /* dequeue requests (incoming) */N int mnr_dlo$l_deqout; /* dequeue requests (outgoing) */N int mnr_dlo$l_blkloc; /* blocking ASTs (local) */N int mnr_dlo$l_blkin; /* blocking ASTs (incoming) */N int mnr_dlo$l_blkout; /* blocking ASTs (outgoing) */N int mnr_dlo$l_dirin; /* directory functions (incoming) */N int mnr_dlo$l_dirout; ;: /* directory functions (outgoing) */N int mnr_dlo$l_dlckmsg; /* deadlock message rate */ char mnr_dlo$b_fill_19_ [4]; } DLOCK_CLASS;^/****************************************************************************************** */N/* */I/* FCP class record format */N/* <: */#define MNR_FCP$K_SIZE 48 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _fcp_class {#pragma __nomember_alignmentN int mnr_fcp$l_fcpcalls; /* FCP calls */N int mnr_fcp$l_alloc; /* disk allocation requests */N int mnr_fcp$l_fcpcreate; /* new fil=:es */N int mnr_fcp$l_fcpread; /* read I/Os */N int mnr_fcp$l_fcpwrite; /* write I/Os */N int mnr_fcp$l_volwait; /* volume lock waits */N int mnr_fcp$l_fcpcpu; /* CPU time spent in file system */Q int mnr_fcp$l_fcpfault; /* count of pagefaults for file system */N int mnr_fcp$l_fcpturn; /* window turns >: */R int mnr_fcp$l_access; /* count of file name lookup operations */N int mnr_fcp$l_opens; /* files opened */N int mnr_fcp$l_erase; /* count of erase I/O operations */ } FCP_CLASS;^/****************************************************************************************** */N/* */I/* FILE_SYSTEM_CACHE class record format ?: */N/* */#define MNR_FIL$K_SIZE 56 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _file_sys_class {#pragma __nomember_alignmentN int mnr_fil$l_dirfcb_hit; /* directory FCB cache hits */N int mnr_fil$l_dirfcb_tries; /* d@:irectory FCB cache attempts */N int mnr_fil$l_dirdata_hit; /* directory data cache hits */N int mnr_fil$l_dirdata_tries; /* directory data cache attempts */N int mnr_fil$l_filhdr_hit; /* file header cache hits */N int mnr_fil$l_filhdr_tries; /* file header cache attempts */ __union {N int mnr_fil$l_fidhit; /* file ID cache hits */N int mnr_fil$l_fid_hit; /* A: */ } mnr_fil$r_fid_overlay;N int mnr_fil$l_fid_tries; /* file ID cache attempts */ __union {N int mnr_fil$l_exthit; /* extent cache hits */N int mnr_fil$l_ext_hit; /* */ } mnr_fil$r_ext_overlay;N int mnr_fil$l_ext_tries; /* extent cache attempts */ __union {N int mnr_fil$l_quohit; /* quota cache hits B: */N int mnr_fil$l_quo_hit; /* */ } mnr_fil$r_quo_overlay;N int mnr_fil$l_quo_tries; /* quota cache attempts */N int mnr_fil$l_storagmap_hit; /* storage bitmap cache hits */N int mnr_fil$l_storagmap_tries; /* storage bitmap cache attempts */ } FILE_SYS_CLASS; #if !defined(__VAXC)?#define mnr_fil$l_fidhit mnr_fil$r_fid_overlay.mnr_fil$l_fidhitA#define mnr_fil$ C:l_fid_hit mnr_fil$r_fid_overlay.mnr_fil$l_fid_hit?#define mnr_fil$l_exthit mnr_fil$r_ext_overlay.mnr_fil$l_exthitA#define mnr_fil$l_ext_hit mnr_fil$r_ext_overlay.mnr_fil$l_ext_hit?#define mnr_fil$l_quohit mnr_fil$r_quo_overlay.mnr_fil$l_quohitA#define mnr_fil$l_quo_hit mnr_fil$r_quo_overlay.mnr_fil$l_quo_hit"#endif /* #if !defined(__VAXC) */ ^/****************************************************************************************** */N/* D: */I/* I/O class record format */N/* */#define MNR_IO$K_SIZE 56 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _io_class {#pragma __nomember_alignmentN int mnr_io$l_dirio; /*E: count of direct I/O requests */N int mnr_io$l_bufio; /* count of buffered I/O requests */N int mnr_io$l_mbwrites; /* mailbox writes */N int mnr_io$l_spltrans; /* count of split transfers */P int mnr_io$l_lognam; /* count of logical name translations */N int mnr_io$l_opens; /* count of files opened */N int mnr_io$l_faults; /* total pagefaults F: */N int mnr_io$l_preads; /* count of pages read from disk */O int mnr_io$l_preadio; /* count of page read I/Os from disk */P int mnr_io$l_pwrites; /* count of pages written to pagefile */R int mnr_io$l_pwritio; /* count of page write I/Os to pagefile */N int mnr_io$l_iswpcnt; /* count of inswap operations */N int mnr_io$l_freecnt; /* number of pages on freelist */N G:int mnr_io$l_mfycnt; /* number of pages on modified list */ } IO_CLASS;^/****************************************************************************************** */N/* */I/* LOCK class record format */N/* */#define MNR_LCK$K_SIZE 40 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined H:(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _lock_class {#pragma __nomember_alignmentN int mnr_lck$l_enqnew; /* enqueue requests */N int mnr_lck$l_enqcvt; /* conversion requests */N int mnr_lck$l_deq; /* dequeue requests */N int mnr_lck$l_blkast; /* blocking ASTs I: */N int mnr_lck$l_enqwait; /* ENQ waits */N int mnr_lck$l_enqnotqd; /* ENQs not queued */N int mnr_lck$l_dlcksrch; /* deadlock searches */N int mnr_lck$l_dlckfnd; /* deadlocks found */N int mnr_lck$l_numlocks; /* total number of locks */N int mnr_lck$l_numres; /* total number of resources */ } LOCK J:_CLASS;^/****************************************************************************************** */N/* */I/* MODES class record format */N/* */#define MNR_MOD$K_SIZE 36 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment _ K:_quadword#else#pragma __nomember_alignment#endiftypedef struct _modes_class {#pragma __nomember_alignment __union {N int mnr_mod$l_cpuid; /* CPU id */ char mnr_mod$b_cpuid;" } mnr_mod$r_cpuid_overlay;N int mnr_mod$l_inter; /* Interrupt stack time */N int mnr_mod$l_mpsync; /* Multi-processor sync time */N int mnr_mod$l_kernel; /* Kernel mode time L: */N int mnr_mod$l_exec; /* exec mode time */N int mnr_mod$l_super; /* Supervisor mode time */N int mnr_mod$l_user; /* User mode time */N int mnr_mod$l_compat; /* Compatibility mode time */N int mnr_mod$l_idle; /* Idle time */ char mnr_mod$b_fill_20_ [4]; } MODES_CLASS; #if !defined(__VAXC)?#define M:mnr_mod$l_cpuid mnr_mod$r_cpuid_overlay.mnr_mod$l_cpuid?#define mnr_mod$b_cpuid mnr_mod$r_cpuid_overlay.mnr_mod$b_cpuid"#endif /* #if !defined(__VAXC) */ #define MNR_OLDMOD$K_SIZE 33 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _oldmodes_class {#pragma __nomember_alignment char mnr_oldmod$b_cpuid;N int mnr_oldmod$l_intN:er; /* Interrupt stack time */N int mnr_oldmod$l_mpsync; /* Multi-processor sync time */N int mnr_oldmod$l_kernel; /* Kernel mode time */N int mnr_oldmod$l_exec; /* exec mode time */N int mnr_oldmod$l_super; /* Supervisor mode time */N int mnr_oldmod$l_user; /* User mode time */N int mnr_oldmod$l_compat; /* Compati O:bility mode time */N int mnr_oldmod$l_idle; /* Idle time */# char mnr_oldmod$b_fill_21_ [7]; } OLDMODES_CLASS;^/****************************************************************************************** */N/* */I/* MSCP_SERVER class record format */N/* */#d P:efine MNR_MSC$K_SIZE 52 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mscp_class {#pragma __nomember_alignmentN int mnr_msc$l_request; /* count of I/O transfer requests */N int mnr_msc$l_read; /* count of read requests */N int mnr_msc$l_write; /* count of write requestsQ: */N int mnr_msc$l_fragment; /* count of extra fragments */N int mnr_msc$l_split; /* count of fragmented requests */b int mnr_msc$l_bufwait; /* count of requests that had to wait for buffer memory */N int mnr_msc$l_size1; /* count of 1 block I/O requests */N int mnr_msc$l_size2; /* count of 2-3 block requests */N int mnr_msc$l_size3; /* count of 4-7 block requests R: */N int mnr_msc$l_size4; /* count of 8-15 block requests */N int mnr_msc$l_size5; /* count of 16-31 block requests */N int mnr_msc$l_size6; /* count of 32-63 block requests */N int mnr_msc$l_size7; /* count of 64+ block requests */ char mnr_msc$b_fill_22_ [4]; } MSCP_CLASS;^/****************************************************************************************** */N/* S: */I/* PAGE class record format */N/* */#define MNR_PAG$K_SIZE 52 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _page_class {#pragma __nomember_alignmentN int mnr_pag$T:l_faults; /* page faults */N int mnr_pag$l_preads; /* page reads from disk */N int mnr_pag$l_preadio; /* page read I/Os */N int mnr_pag$l_pwrites; /* page writes to pagefile */N int mnr_pag$l_pwritio; /* page write I/Os */N int mnr_pag$l_freflts; /* faults from freelist */N int mnr_pag$l_mfyflts; /*U: faults from modified list */N int mnr_pag$l_dzroflts; /* demand-zero faults */N int mnr_pag$l_gvalid; /* global valid faults */N int mnr_pag$l_wrtinprog; /* write-in-progress faults */N int mnr_pag$l_sysfaults; /* system faults */N int mnr_pag$l_freecnt; /* free page count */N int mnr_pag$l_mfycnt; /* modified page count V: */ char mnr_pag$b_fill_23_ [4]; } PAGE_CLASS;^/****************************************************************************************** */N/* */I/* PROCESS class record format */N/* */N/* Number of bytes for FAO stack (display buffer) */N/* for a single process (P W:ROCESSES class) */#define MNR_PRO$K_PSIZE 8 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pro_class_pre {#pragma __nomember_alignmentO int mnr_pro$l_pctrec; /* Count of processes in this record */R int mnr_pro$l_pctint; /* Count of processes for this interval */ X: } PRO_CLASS_PRE;N#define MNR_PRO$K_REV3DSIZE 72 /* Revision Level 3 boundary */N#define MNR_PRO$K_REV4DSIZE 96 /* Revision Level 4 boundary */N#define MNR_PRO$C_PRO_REV 4 /* current revision is 4 */#define MNR_PRO$K_SIZE 96#define MNR_PRO$K_DSIZE 96#define MNR_PRO$K_FSIZE 64 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragm Y:a __nomember_alignment#endiftypedef struct _process_class {#pragma __nomember_alignmentN int mnr_pro$l_ipid; /* Internal PID */N int mnr_pro$l_uic; /* UIC (Member is low-order word) */N short int mnr_pro$w_state; /* State value */N char mnr_pro$b_pri; /* Priority (negative value) */ char mnr_pro$b_fill_24_ [5];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplus Z:plus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifN int mnr_pro$t_lname [4]; /* Process name (counted string) */#pragma __nomember_alignmentN int mnr_pro$l_gpgcnt; /* Global page count */N int mnr_pro$l_ppgcnt; /* Process page count */d int mnr_pro$l_sts; /* PCB Status Vector (PCB$V_RES bit clear => swapped out) */N[: int mnr_pro$l_diocnt; /* Direct I/O count */N int mnr_pro$l_pageflts; /* Page fault count */N int mnr_pro$l_cputim; /* Accumulated CPU time (in ticks) */N int mnr_pro$l_biocnt; /* Buffered I/O count */N int mnr_pro$l_epid; /* Extended PID */O int mnr_pro$l_efwm; /* Event flag wait mask (for MWAITs) */W int mnr_pro$l_rbstra\:n; /* Real balance slot transitions (or faults) */R int mnr_pro$l_kernel_counter; /* kernel mode counter for this process */U int mnr_pro$l_executive_counter; /* executive mode counter for this process */W int mnr_pro$l_supervisor_counter; /* supervisor mode counter for this process */P int mnr_pro$l_user_counter; /* user mode counter for this process */O int mnr_pro$l_reserved2; /* Reserved # 2 for future expansion */O int mnr_pr ]:o$l_reserved1; /* Reserved # 1 for future expansion */ } PROCESS_CLASS;N#define MNR_OLDPRO$K_REV0DSIZE 55 /* Revision Level 0 boundary */N#define MNR_OLDPRO$K_REV1DSIZE 63 /* Revision Level 1 boundary */N#define MNR_OLDPRO$K_REV2DSIZE 67 /* Revision Level 2 boundary */N#define MNR_OLDPRO$C_PRO_REV 2 /* old format revision is 2 */#define MNR_OLDPRO$K_SIZE 67#define MNR_OLDPRO$K_DSIZE 67 c#if !defined(__NOBASEALIGN_SUP ^:PORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif"typedef struct _oldprocess_class {#pragma __nomember_alignmentN int mnr_oldpro$l_ipid; /* Internal PID */N int mnr_oldpro$l_uic; /* UIC (Member is low-order word) */N short int mnr_oldpro$w_state; /* State value */N char mnr_oldpro$b_pri; _:/* Priority (negative value) */N int mnr_oldpro$t_lname [4]; /* Process name (counted string) */N int mnr_oldpro$l_gpgcnt; /* Global page count */N int mnr_oldpro$l_ppgcnt; /* Process page count */d int mnr_oldpro$l_sts; /* PCB Status Vector (PCB$V_RES bit clear => swapped out) */N int mnr_oldpro$l_diocnt; /* Direct I/O count */N int mnr_oldpro$l_pageflts; /* P`:age fault count */N int mnr_oldpro$l_cputim; /* Accumulated CPU time (in ticks) */N int mnr_oldpro$l_biocnt; /* Buffered I/O count */N int mnr_oldpro$l_epid; /* Extended PID */O int mnr_oldpro$l_efwm; /* Event flag wait mask (for MWAITs) */W int mnr_oldpro$l_rbstran; /* Real balance slot transitions (or faults) */# char mnr_oldpro$b_fill_25_ [5]; } OLDPROCESS_CLA a:SS;^/****************************************************************************************** */N/* */I/* RLOCK class record format */N/* */#define MNR_RLO$K_SIZE 28 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __qua b:dword#else#pragma __nomember_alignment#endiftypedef struct _rlock_class {#pragma __nomember_alignment\ int mnr_rlo$l_rm_unload; /* count of trees moved from this node (outbound) */T int mnr_rlo$l_rm_more_act; /* trees moved because of higher activity */U int mnr_rlo$l_rm_better; /* trees moved because of higher LOCKDIRWT */Z int mnr_rlo$l_rm_single; /* trees moved to node because of sole interest */N int mnr_rlo$l_rm_msg_sent;c: /* remaster messages sent */Y int mnr_rlo$l_rm_acquire; /* count of trees moved to this node (inbound) */N int mnr_rlo$l_rm_msg_rcv; /* remaster messages received */ char mnr_rlo$b_fill_26_ [4]; } RLOCK_CLASS;^/****************************************************************************************** */N/* */I/* RMS class record format d: */N/* */#define MNR_RMS$K_SIZE 276 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rms_class {#pragma __nomember_alignment __union {N int mnr_rms$l_filnum; /* sequential number of the file */ char mnr_rms$b_file:num;# } mnr_rms$r_filnum_overlay;N int mnr_rms$l_org; /* file organization */N int mnr_rms$l_reserved1; /* */N int mnr_rms$l_seqgets; /* count of sequential $GETs */N int mnr_rms$l_keygets; /* count of keyed $GETs */S int mnr_rms$l_rfagets; /* count of $GETs by record-file-address */Z __int64 mnr_rms$q_getbytes; /* total number f:of bytes required for all $GETs */N int mnr_rms$l_seqputs; /* count of sequential $PUTs */N int mnr_rms$l_keyputs; /* count of keyed $PUTs */Z __int64 mnr_rms$q_putbytes; /* total number of bytes required for all $PUTs */N int mnr_rms$l_updates; /* count of $UPDATEs */] __int64 mnr_rms$q_updatebytes; /* total number of bytes required for all $UPDATEs */N int mnr_rms$l_deletes; /*g: count of $DELETEs */N int mnr_rms$l_truncates; /* count of $TRUNCATEs */V int mnr_rms$l_truncblks; /* total blocks required for all $TRUNCATEs */N int mnr_rms$l_seqfinds; /* count of sequential $FINDs */N int mnr_rms$l_keyfinds; /* count of keyed $FINDS */T int mnr_rms$l_rfafinds; /* count of $FINDs by record-file-address */N int mnr_rms$l_reads; /* count of $Rh:EADS */Q __int64 mnr_rms$q_readbytes; /* total bytes required for all $READs */N int mnr_rms$l_connects; /* count of $CONNECTs */N int mnr_rms$l_disconnects; /* count of $DISCONNECTs */N int mnr_rms$l_extends; /* count of $EXTENDs */T int mnr_rms$l_extblocks; /* total blocks required for all $EXTENDs */N int mnr_rms$l_flushes; /* count of $FLUSHes i: */N int mnr_rms$l_rewinds; /* count of $REWINDs */N int mnr_rms$l_writes; /* count of $WRITEs */\ __int64 mnr_rms$q_writebytes; /* total number of bytes required for all $WRITEs */N int mnr_rms$l_flckenqs; /* file lock $ENQs */N int mnr_rms$l_flckdeqs; /* file lock $DEQs */N int mnr_rms$l_flckcnvs; /* file lock conversions */N j: int mnr_rms$l_lblckenqs; /* local buffer $ENQs */N int mnr_rms$l_lblckdeqs; /* local buffer $DEQs */N int mnr_rms$l_lblckcnvs; /* local buffer conversions */N int mnr_rms$l_gblckenqs; /* global buffer $ENQs */N int mnr_rms$l_gblckdeqs; /* global buffer $DEQs */N int mnr_rms$l_gblckcnvs; /* global buffer conversions */N int mnr_rms$l_gslckenqs;k: /* global section $ENQs */N int mnr_rms$l_gslckdeqs; /* global section $DEQs */N int mnr_rms$l_gslckcnvs; /* global section conversions */N int mnr_rms$l_rllckenqs; /* record lock $ENQs */N int mnr_rms$l_rllckdeqs; /* record lock $DEQs */N int mnr_rms$l_rllckcnvs; /* record lock conversions */N int mnr_rms$l_applckenqs; /* append lockl: $ENQs */N int mnr_rms$l_applckdeqs; /* append lock $DEQs */N int mnr_rms$l_applckcnvs; /* append lock conversions */N int mnr_rms$l_flblkasts; /* file lock blocking ASTs */N int mnr_rms$l_lblblkasts; /* local buffer blocking ASTs */N int mnr_rms$l_gblblkasts; /* global buffer blocking ASTs */N int mnr_rms$l_appblkasts; /* append lock blocking ASTs */Nm: int mnr_rms$l_lcachehits; /* local cache hits */N int mnr_rms$l_lcacheatt; /* local cache attempts */N int mnr_rms$l_gcachehits; /* global cache hits */N int mnr_rms$l_gcacheatt; /* global cache attempts */N int mnr_rms$l_gbrdirios; /* global buffer read I/Os */N int mnr_rms$l_gbwdirios; /* global buffer write I/Os */N int mnr_rms$l_lbrdirion:s; /* local buffer read I/Os */N int mnr_rms$l_lbwdirios; /* local buffer write I/Os */N int mnr_rms$l_bktsplt; /* bucket splits */N int mnr_rms$l_mbktsplt; /* multi-bucket splits */N int mnr_rms$l_opens; /* count of $CLOSEs */N int mnr_rms$l_closes; /* count of $OPENs */N int mnr_rms$l_reserved2; /* o: */N int mnr_rms$l_reserved3; /* */ char mnr_rms$b_fill_27_ [4]; } RMS_CLASS; #if !defined(__VAXC)B#define mnr_rms$l_filnum mnr_rms$r_filnum_overlay.mnr_rms$l_filnumB#define mnr_rms$b_filnum mnr_rms$r_filnum_overlay.mnr_rms$b_filnum"#endif /* #if !defined(__VAXC) */ #define MNR_OLDRMS$K_SIZE 273 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragm p:a __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _oldrms_class {#pragma __nomember_alignmentN char mnr_oldrms$b_filnum; /* sequential number of the file */N int mnr_oldrms$l_org; /* file organization */N int mnr_oldrms$l_reserved1; /* */N int mnr_oldrms$l_seqgets; /* count of sequential $GETs */N int mnr_oldrms$l_keygets; /*q: count of keyed $GETs */S int mnr_oldrms$l_rfagets; /* count of $GETs by record-file-address */Z __int64 mnr_oldrms$q_getbytes; /* total number of bytes required for all $GETs */N int mnr_oldrms$l_seqputs; /* count of sequential $PUTs */N int mnr_oldrms$l_keyputs; /* count of keyed $PUTs */Z __int64 mnr_oldrms$q_putbytes; /* total number of bytes required for all $PUTs */N int mnr_oldrms$l_updates; r: /* count of $UPDATEs */] __int64 mnr_oldrms$q_updatebytes; /* total number of bytes required for all $UPDATEs */N int mnr_oldrms$l_deletes; /* count of $DELETEs */N int mnr_oldrms$l_truncates; /* count of $TRUNCATEs */V int mnr_oldrms$l_truncblks; /* total blocks required for all $TRUNCATEs */N int mnr_oldrms$l_seqfinds; /* count of sequential $FINDs */N int mnr_oldrms$l_keyfinds; s:/* count of keyed $FINDS */T int mnr_oldrms$l_rfafinds; /* count of $FINDs by record-file-address */N int mnr_oldrms$l_reads; /* count of $READS */Q __int64 mnr_oldrms$q_readbytes; /* total bytes required for all $READs */N int mnr_oldrms$l_connects; /* count of $CONNECTs */N int mnr_oldrms$l_disconnects; /* count of $DISCONNECTs */N int mnr_oldrms$l_extends; /* count of $EXTt:ENDs */T int mnr_oldrms$l_extblocks; /* total blocks required for all $EXTENDs */N int mnr_oldrms$l_flushes; /* count of $FLUSHes */N int mnr_oldrms$l_rewinds; /* count of $REWINDs */N int mnr_oldrms$l_writes; /* count of $WRITEs */\ __int64 mnr_oldrms$q_writebytes; /* total number of bytes required for all $WRITEs */N int mnr_oldrms$l_flckenqs; /* file lock $ENQs u: */N int mnr_oldrms$l_flckdeqs; /* file lock $DEQs */N int mnr_oldrms$l_flckcnvs; /* file lock conversions */N int mnr_oldrms$l_lblckenqs; /* local buffer $ENQs */N int mnr_oldrms$l_lblckdeqs; /* local buffer $DEQs */N int mnr_oldrms$l_lblckcnvs; /* local buffer conversions */N int mnr_oldrms$l_gblckenqs; /* global buffer $ENQs */N int v:mnr_oldrms$l_gblckdeqs; /* global buffer $DEQs */N int mnr_oldrms$l_gblckcnvs; /* global buffer conversions */N int mnr_oldrms$l_gslckenqs; /* global section $ENQs */N int mnr_oldrms$l_gslckdeqs; /* global section $DEQs */N int mnr_oldrms$l_gslckcnvs; /* global section conversions */N int mnr_oldrms$l_rllckenqs; /* record lock $ENQs */N int mnr_oldrms$l_rllckdeqs; w: /* record lock $DEQs */N int mnr_oldrms$l_rllckcnvs; /* record lock conversions */N int mnr_oldrms$l_applckenqs; /* append lock $ENQs */N int mnr_oldrms$l_applckdeqs; /* append lock $DEQs */N int mnr_oldrms$l_applckcnvs; /* append lock conversions */N int mnr_oldrms$l_flblkasts; /* file lock blocking ASTs */N int mnr_oldrms$l_lblblkasts; /* local buffer blocx:king ASTs */N int mnr_oldrms$l_gblblkasts; /* global buffer blocking ASTs */N int mnr_oldrms$l_appblkasts; /* append lock blocking ASTs */N int mnr_oldrms$l_lcachehits; /* local cache hits */N int mnr_oldrms$l_lcacheatt; /* local cache attempts */N int mnr_oldrms$l_gcachehits; /* global cache hits */N int mnr_oldrms$l_gcacheatt; /* global cache attempts */N iny:t mnr_oldrms$l_gbrdirios; /* global buffer read I/Os */N int mnr_oldrms$l_gbwdirios; /* global buffer write I/Os */N int mnr_oldrms$l_lbrdirios; /* local buffer read I/Os */N int mnr_oldrms$l_lbwdirios; /* local buffer write I/Os */N int mnr_oldrms$l_bktsplt; /* bucket splits */N int mnr_oldrms$l_mbktsplt; /* multi-bucket splits */N int mnr_oldrms$l_opens; z: /* count of $CLOSEs */N int mnr_oldrms$l_closes; /* count of $OPENs */N int mnr_oldrms$l_reserved2; /* */N int mnr_oldrms$l_reserved3; /* */# char mnr_oldrms$b_fill_28_ [7]; } OLDRMS_CLASS;^/****************************************************************************************** */N/* {: */I/* SCS class record format */N/* */#define MNR_SCS$K_SIZE 56 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _scs_class {#pragma __nomember_alignmentN __int64 mnr_scs$t_nodename; /* node na|:me */N int mnr_scs$l_dgsent; /* datagrams sent */N int mnr_scs$l_dgrcvd; /* datagrams received */N int mnr_scs$l_dgdiscard; /* datagrams discarded */N int mnr_scs$l_msgsent; /* sequenced messages sent */N int mnr_scs$l_msgrcvd; /* sequenced messages received */N int mnr_scs$l_sndats; /* block transfer send commands }:*/O int mnr_scs$l_kbytsent; /* KBytes sent by send-data commands */N int mnr_scs$l_reqdats; /* block transfer request commands */V int mnr_scs$l_kbytreqd; /* KBytes received by request-data commands */N int mnr_scs$l_kbytmapd; /* block transfer KBytes mapped */Q int mnr_scs$l_qcrcnt; /* connections queued for send credits */W int mnr_scs$l_qbdtcnt; /* connections queued for buffer descriptors */ ~: } SCS_CLASS;^/****************************************************************************************** */N/* */I/* STATES class record format */N/* */#define MNR_STA$K_SIZE 56 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_a :lignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _states_class {#pragma __nomember_alignmentN int mnr_sta$l_colpg; /* collided page wait */N int mnr_sta$l_mwait; /* misc resource wait */N int mnr_sta$l_cef; /* common event flag wait */N int mnr_sta$l_pfw; /* pagefault wait */N int mnr_sta$l_lef; /* local event f:lag */N int mnr_sta$l_lefo; /* local event flag (outswapped) */N int mnr_sta$l_hib; /* hibernate */N int mnr_sta$l_hibo; /* hibernate (outswapped) */N int mnr_sta$l_susp; /* suspended */N int mnr_sta$l_suspo; /* suspended (outswapped) */N int mnr_sta$l_fpg; /* free page wait */N : int mnr_sta$l_com; /* compute state */N int mnr_sta$l_como; /* compute state (outswapped) */N int mnr_sta$l_cur; /* current */ } STATES_CLASS;^/****************************************************************************************** */N/* */I/* SYSTEM class record format : */N/* */#define MNR_SYS$K_SIZE 36 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _system_class {#pragma __nomember_alignmentN int mnr_sys$l_busy; /* CPU busy */N int mnr_sys$l_othstat; /* other states : */N int mnr_sys$l_procs; /* process count */N int mnr_sys$l_faults; /* page faults */N int mnr_sys$l_preadio; /* page read I/Os */N int mnr_sys$l_freecnt; /* number of pages on freelist */N int mnr_sys$l_mfycnt; /* number of pages on modified list */N int mnr_sys$l_dirio; /* total direct I/O count */N : int mnr_sys$l_bufio; /* total buffered I/O count */ char mnr_sys$b_fill_29_ [4]; } SYSTEM_CLASS;^/****************************************************************************************** */N/* */I/* TIMER class record format */N/* */#define MNR_TMR$K_SIZE 16 c#if !def :ined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _timer_class {#pragma __nomember_alignmentN int mnr_tmr$l_tqe_total; /* total TQEs */N int mnr_tmr$l_tqe_sysub; /* system subroutine TQEs */N int mnr_tmr$l_tqe_timer; /* timer TQEs */N int mnr_tmr$l_tqe_ :wakeup; /* wakeup TQEs */ } TIMER_CLASS;^/****************************************************************************************** */N/* */I/* TRANSACTION class record format */N/* */#define MNR_TRA$K_SIZE 56 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) :/* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _trans_class {#pragma __nomember_alignmentN int mnr_tra$l_starts; /* count of start transactions */[ int mnr_tra$l_prepares; /* count of transactions that have been prepared */N int mnr_tra$l_one_phase; /* count of one-phase commits */N int mnr_tra$l_commits; /* count of transactions: committed */N int mnr_tra$l_aborts; /* count of aborted transactions */N int mnr_tra$l_ends; /* count of end transactions */S int mnr_tra$l_branchs; /* count of transaction branches started */Q int mnr_tra$l_adds; /* count of transaction branches added */N int mnr_tra$l_buckets1; /* 0-1 second transactions */N int mnr_tra$l_buckets2; /* 1-2 second transactions */N : int mnr_tra$l_buckets3; /* 2-3 second transactions */N int mnr_tra$l_buckets4; /* 3-4 second transactions */N int mnr_tra$l_buckets5; /* 4-5 second transactions */N int mnr_tra$l_buckets6; /* 5+ second transactions */ } TRANS_CLASS; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restor:e /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MONDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M:/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used,: duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/= :/* Created: 7-Oct-2024 15:23:29 by OpenVMS SDL V3.7 */H/* Source: 06-APR-2017 15:31:17 $1$DGA8345:[LIB_H.SRC]MPDEVDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MPDEVDEF ***/#ifndef __MPDEVDEF_LOADED#define __MPDEVDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef: __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __:struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* Include base definitions */N/* Verified for x86 port - Clair Grant */ #include #include #include #include N/* Verified for x86 port - Clair Grant : */#define MPDEV$M_ENABLE 0x1#define MPDEV$M_REMOTE 0x2#define MPDEV$M_POLLER 0x4##define MPDEV$M_SCSI_ERROR_POLL 0x8 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif typedef struct _mpdev_sgn_flgs {N/* Definition for Multipath sysgen */N/* parameters. : */#pragma __nomember_alignment __union { char mpdev$b_bits; __struct {N unsigned mpdev$v_enable : 1; /* enable Multipath */P unsigned mpdev$v_remote : 1; /* enable Multipath for remote paths */N unsigned mpdev$v_poller : 1; /* enable Multipath poller */[ unsigned mpdev$v_scsi_error_poll : 1; /* enable polling to flush SCSI errors */) unsigned mpdev$v_fill_2_: : 4; } mpdev$r_fill_1_; } mpdev$r_fill_0_; char mpdev$b_fill_3_ [3]; } MPDEV_SGN_FLGS; #if !defined(__VAXC)E#define mpdev$v_enable mpdev$r_fill_0_.mpdev$r_fill_1_.mpdev$v_enableE#define mpdev$v_remote mpdev$r_fill_0_.mpdev$r_fill_1_.mpdev$v_remoteE#define mpdev$v_poller mpdev$r_fill_0_.mpdev$r_fill_1_.mpdev$v_pollerW#define mpdev$v_scsi_error_poll mpdev$r_fill_0_.mpdev$r_fill_1_.mpdev$v_scsi_error_poll"#endif /* #if !defined(__VAXC) */ #define MP:DEV$M_ERRORLOG 0x1##define MPDEV$M_INHIBIT_PATHBAL 0x2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _mpdev_d1_flgs {N/* Definition for Multipath sysgen */N/* debugging parameters. */#pragma __nomember_alignment __union { char m :pdev$b_bits; __struct {N unsigned mpdev$v_errorlog : 1; /* enable error logging */N unsigned mpdev$v_inhibit_pathbal : 1; /* inhibit path balancing */) unsigned mpdev$v_fill_6_ : 6; } mpdev$r_fill_5_; } mpdev$r_fill_4_; char mpdev$b_fill_7_ [3]; } MPDEV_D1_FLGS; #if !defined(__VAXC)I#define mpdev$v_errorlog mpdev$r_fill_4_.mpdev$r_fill_5_.mpdev$v_errorlogW#define mpdev$v_inhibit_pathbal mpdev$r_fill_4_.mp :dev$r_fill_5_.mpdev$v_inhibit_pathbal"#endif /* #if !defined(__VAXC) */  N/* Multipath specific data structure */#define MPDEV$M_CP_MANUAL 0x1!#define MPDEV$M_PV_IRP_ACTIVE 0x2&#define MPDEV$M_PV_PACKACK_SUCCESS 0x4#define MPDEV$M_WAS_FNDACT 0x8 #define MPDEV$M_PVIRP_SRVIO 0x10'#define MPDEV$M_DEVICE_POLL_ACTIVE 0x20S#define MPDEV$K_IO_ERROR 1 /* I/O error initiated path verification */N#define MPDEV$K_MANUAL_SWITCH 2 :/* Manual switch requested */N#define MPDEV$K_FIND_ACTIVE 3 /* Proactive search for active path */N#define MPDEV$K_ST_STABLE 1 /* Path is stable */N#define MPDEV$K_ST_DRAINING 2 /* Draining I/O from current path */R#define MPDEV$K_ST_SWLCLCON 3 /* Path switching is being attempted to */N/* only local path that are connected */R#define MPDEV$K_ST_SWLCLANY 4 /* Path switching is b:eing attempted to */N/* any local path */[#define MPDEV$K_ST_SWANY 5 /* Path switching is being attempted to any path */N#define MPDEV$K_ST_STACP 6 /* Attempt to stay on current path */`#define MPDEV$K_ST_RESIDUAL 7 /* Waiting for "leftover" PVIRP from earlier path ver */N/* ..can't go to STABLE until that PVIRP completes */N#define MPDEV$K_PACKACK_TIMLIM_SECS 5 /* Default: time limit (seconds) */  9#ifdef __cplusplus /* Define structure prototypes */ struct _irp$r_acb64_ast_overlay; struct _fdt;struct _irp$r_iobd; struct _cucb;struct _mpdev_acb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mpdev {#pragma __nomember_alignmentN struct _mpdev *m:pdev$ps_flink; /* Forward pointer */N struct _mpdev *mpdev$ps_blink; /* Backward pointer */N unsigned short int mpdev$w_size; /* Size of the data buffer */N unsigned char mpdev$b_type; /* Data structure type */N unsigned char mpdev$b_subtype; /* Data structure sub-type */N struct _ucb *mpdev$ps_primary_ucb; /* Pointer to the primary ucb */^ struct _ucb *mpdev$ps_current_ucb; /* Poi :nter to the current UCB in the multipath set. */X struct _fdt *mpdev$ps_primary_fdt; /* Saved value of primary path's UCB$PS_FDT_2 */N/* Verified for x86 port - Clair Grant */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB mpdev$r_cbb_primary_affinity; /* Embed :ded CBB block */N __struct { /* Compatability offset cells */' __int64 mpdev$q_fill_1 [6]; __union {i unsigned int mpdev$l_primary_affinity; /* Saved value of primary path's UCB$L_AFFINITY */m unsigned __int64 mpdev$q_primary_affinity; /* Saved value of primary path's UCB$L_AFFINITY */2 } mpdev$r_cbb_priaff_data_overlay;( __int64 mpdev$q_fill_2 [15];0 } mp :dev$r_cbb_priaff_compat_overlay;% } mpdev$r_cbb_priaff_overlay; __union {N unsigned int mpdev$l_set_flags; /* Status flags for whole set */ __struct {] unsigned mpdev$v_cp_manual : 1; /* Current path selected via a manual switch */N unsigned mpdev$v_pv_irp_active : 1; /* A PV IRP is active */j unsigned mpdev$v_pv_packack_success : 1; /* Most recent PV packack completed successfully */Y unsigned mpdev$v_w:as_fndact : 1; /* Event started out as "find active" */[ unsigned mpdev$v_pvirp_srvio : 1; /* Current PV IRP was originally a SRVIO */q unsigned mpdev$v_device_poll_active : 1; /* Search for a working path in this set is in progress */* unsigned mpdev$v_fill_10_ : 2; } mpdev$r_fill_9_; } mpdev$r_fill_8_;N struct _ddt *mpdev$ps_ddt; /* Pointer to the newly created DDT */X struct _ucb *mpdev$ps_pv_ucb; /* Pointer: to the path UCB last issued a path */N/* verification IRP */N unsigned int mpdev$l_eb_type_code; /* Multipath event block codes */V unsigned int mpdev$l_eb_state; /* Multipath automatic path switching state */N/* Values are 1,2,3,... */ char mpdev$b_fill_11_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pra :gma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 mpdev$q_eb_start_time; /* Time this event started */#pragma __nomember_alignmentW struct _ucb *mpdev$ps_eb_start_ucb; /* UCB of current path at start of the event */\ int mpdev$l_eb_lclcon_retries; /* Number of scans of the multipath set when path */N/* verification is in progress and MPDEV$L_EB_STATE */N/* is MPDEV$K_ST_SWLCLCON : */e unsigned int mpdev$l_eb_saved_mvirp_func; /* Saved value of the MVIRP's IRP$L_FUNC field while */N/* the IRP is being used as a path verification IRP */c unsigned int mpdev$l_eb_saved_mvirp_pid; /* Saved value of the MVIRP's IRP$L_PID field while */N/* the IRP is being used as a path verification IRP */c unsigned int mpdev$l_eb_saved_mvirp_sts; /* Saved value of the MVIRP's IRP$L_STS field while */N/* the: IRP is being used as a path verification IRP */e unsigned int mpdev$l_eb_saved_mvirp_sts2; /* Saved value of the MVIRP's IRP$L_STS2 field while */N/* the IRP is being used as a path verification IRP */ __union {N unsigned int mpdev$l_driver1; /* Driver-specific field */N struct _cucb *mpdev$ps_cucb; /* DK uses it as a CUCB field */" } mpdev$r_driver1_overlay;N unsigned int mpdev$l_driver2; : /* Driver-specific field */N unsigned int mpdev$l_driver3; /* Driver-specific field */N unsigned int mpdev$l_driver4; /* Driver-specific field */N struct _mpdev_acb *mpdev$ps_notify_mpdev_acb; /* Address of mpdev_acb */a int mpdev$l_eb_packack_rescans_left; /* Number of path/state rescans left for this packack */e unsigned int mpdev$l_eb_packack_timlim; /* Path verification packack time limit (ABSTIM value) */ char mpdev$b_f :ill_12_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 mpdev$q_eb_end_time; /* Time this event ended */#pragma __nomember_alignmentN struct _irp *mpdev$ps_eb_saved_mvirp; /* MVIRP whose values are saved */N unsigned int mpdev$l_eb_st_at_path_switch; /* State at last path switch */R unsigned int mpdev$l_num_pat:h_ver; /* Number of path verifications started */V unsigned int mpdev$l_num_path_switch_auto; /* Number of automatic path switches */R unsigned int mpdev$l_num_path_switch_man; /* Number of manual path switches */h unsigned int mpdev$l_num_mvirp_ok; /* Number of times a MVIRP packack was completed successfully */Y unsigned int mpdev$l_num_mvirp_fail; /* Number of times a MVIRP packack was failed */i unsigned int mpdev$l_num_mvirp_conc; /* Number of times a concurrent MVIRP packa :ck was intercepted */c unsigned int mpdev$l_num_find_active; /* Number of times a "find active path" scan initiated */Y struct _ucb *mpdev$ps_switch_to_ucb; /* New path selected during path verification */N unsigned int mpdev$l_failback_time; /* abstim of last failback attempt */ char mpdev$b_fill_13_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_align :ment#endif* struct _irp *mpdev$ps_conc_packack_fl;#pragma __nomember_alignmentU struct _irp *mpdev$ps_conc_packack_bl; /* list of IRP's of concurrent packacks */! unsigned int mpdev$l_spare_1;! unsigned int mpdev$l_spare_2; } MPDEV; #if !defined(__VAXC)\#define mpdev$r_cbb_primary_affinity mpdev$r_cbb_priaff_overlay.mpdev$r_cbb_primary_affinity#define mpdev$l_primary_affinity mpdev$r_cbb_priaff_overlay.mpdev$r_cbb_priaff_compat_overlay.mpdev$r_cbb_priaff_data_overla:y.mpdev\$l_primary_affinity#define mpdev$q_primary_affinity mpdev$r_cbb_priaff_overlay.mpdev$r_cbb_priaff_compat_overlay.mpdev$r_cbb_priaff_data_overlay.mpdev\$q_primary_affinity;#define mpdev$l_set_flags mpdev$r_fill_8_.mpdev$l_set_flagsK#define mpdev$v_cp_manual mpdev$r_fill_8_.mpdev$r_fill_9_.mpdev$v_cp_manualS#define mpdev$v_pv_irp_active mpdev$r_fill_8_.mpdev$r_fill_9_.mpdev$v_pv_irp_active]#define mpdev$v_pv_packack_success mpdev$r_fill_8_.mpdev$r_fill_9_.mpdev$v_pv_packack_succes :sM#define mpdev$v_was_fndact mpdev$r_fill_8_.mpdev$r_fill_9_.mpdev$v_was_fndactO#define mpdev$v_pvirp_srvio mpdev$r_fill_8_.mpdev$r_fill_9_.mpdev$v_pvirp_srvio]#define mpdev$v_device_poll_active mpdev$r_fill_8_.mpdev$r_fill_9_.mpdev$v_device_poll_active?#define mpdev$l_driver1 mpdev$r_driver1_overlay.mpdev$l_driver1;#define mpdev$ps_cucb mpdev$r_driver1_overlay.mpdev$ps_cucb"#endif /* #if !defined(__VAXC) */ N#define MPDEV$C_LENGTH 360 /* Length of a MPDEV :*/N#define MPDEV$K_LENGTH 360 /* Length of a MPDEV */N/* Poller path block data structure */&#define MPDEV_PPB$M_PATH_AVAILABLE 0x1*#define MPDEV_PPB$M_ALL_PATHS_DISABLED 0x2$#define MPDEV_PPB$M_NORMAL_TIMER 0x4"#define MPDEV_PPB$M_FAIL_TIMER 0x8)#define MPDEV_PPB$M_FAILBACK_PENDING 0x10+#define MPDEV_PPB$M_POLLING_IRP_ACTIVE 0x20$#define MPDEV_PPB$M_SCAN_ACTIVE 0x40+#define MPDEV_PPB$M_PATH_VERIFY_FAILED 0x80'#define MP:DEV_PPB$M_ENABLED_FOUND 0x100)#define MPDEV_PPB$M_PVIP_RESPONDING 0x200)#define MPDEV_PPB$M_POLLING_STARTED 0x400'#define MPDEV_PPB$M_POLLING_ENABLED 0x1'#define MPDEV_PPB$M_PATH_IS_DISTANT 0x2  9#ifdef __cplusplus /* Define structure prototypes */ struct _irp$r_acb64_ast_overlay; struct _sud; #endif /* #ifdef __cplusplus */ #pragma __member_alignmenttypedef struct _mpdev_ppb {N struct _mpdev_ppb *mpdev_ppb$ps_flink; /* Forward link */#pragma __ :member_alignmentN struct _mpdev_ppb *mpdev_ppb$ps_blink; /* Backward link */#pragma __member_alignmentN unsigned short int mpdev_ppb$w_size; /* Structure size */N unsigned char mpdev_ppb$b_type; /* Structure type */N unsigned char mpdev_ppb$b_subtype; /* Structure subtype */ __union {V unsigned int mpdev_ppb$l_status1; /* Statuses modified via polling routines */ __struct {^ un:signed mpdev_ppb$v_path_available : 1; /* Path was available at last poll (D) */v unsigned mpdev_ppb$v_all_paths_disabled : 1; /* All devices on this path were not testable at last poll */n unsigned mpdev_ppb$v_normal_timer : 1; /* Poller is waiting using "working path" timer interval */k unsigned mpdev_ppb$v_fail_timer : 1; /* Poller is waiting using "failed path" timer interval */ unsigned mpdev_ppb$v_failback_pending : 1; /* A device has failed over: from local to remote; when a local path becomes \*/N/* available, check to see if it can be failed back to the local path */T unsigned mpdev_ppb$v_polling_irp_active : 1; /* Polling IRP is active */l unsigned mpdev_ppb$v_scan_active : 1; /* A poller scan of devices on this path is in progress */w unsigned mpdev_ppb$v_path_verify_failed : 1; /* In this scan: At least one poller path verify has failed */c unsigned mpdev_ppb$v_enabled_found : 1; :/* In this scan: An enabled device was found */| unsigned mpdev_ppb$v_pvip_responding : 1; /* In this scan: Found a device in PVIP with "not responding" clear */a unsigned mpdev_ppb$v_polling_started : 1; /* Polling has been started on this path *// unsigned mpdev_ppb$v_fill_14_ : 21;' } mpdev_ppb$r_status1_bits;& } mpdev_ppb$r_status1_overlay; __union {P unsigned int mpdev_ppb$l_status2; /* Statuses modified via SET DEVICE */ : __struct {R unsigned mpdev_ppb$v_polling_enabled : 1; /* Path check enabled (D) */\ unsigned mpdev_ppb$v_path_is_distant : 1; /* Path is not local to this system *// unsigned mpdev_ppb$v_fill_15_ : 30;' } mpdev_ppb$r_status2_bits;& } mpdev_ppb$r_status2_overlay;g struct _ucb *mpdev_ppb$ps_path_test_ucb; /* UCB most recently used to test the path (never zero) */#pragma __member_alignment struct _ucb *mpdev_ppb$ps_path_test_:ucb_cp; /* Current path on device when polling IRP issued (valid only if POLLING_IRP_ACTIVE\) */#pragma __member_alignment` struct _sud *mpdev_ppb$ps_sud_list; /* List head of SUDs for devices that share this path */#pragma __member_alignmenti unsigned __int64 mpdev_ppb$q_transition_time; /* Time of most recent change to PATH_AVAILABLE flag */p unsigned __int64 mpdev_ppb$q_time_user_disabled; /* Time of most recent change to ALL_PATHS_DISABLED flag */Z unsigned int mpdev_ppb$l_c :urrent_ucb_count; /* number of current UCB's on this path */" char mpdev_ppb$b_fill_16_ [4];N TQE mpdev_ppb$r_tqe; /* Timer Queue Entry */N IRP mpdev_ppb$r_irp; /* I/O Request Packet */ } MPDEV_PPB; #if !defined(__VAXC)K#define mpdev_ppb$l_status1 mpdev_ppb$r_status1_overlay.mpdev_ppb$l_status1r#define mpdev_ppb$v_path_available mpdev_ppb$r_status1_overlay.mpdev_ppb$r_status1_bits.mpdev_ppb$v_path_availablez#define mp:dev_ppb$v_all_paths_disabled mpdev_ppb$r_status1_overlay.mpdev_ppb$r_status1_bits.mpdev_ppb$v_all_paths_disabledn#define mpdev_ppb$v_normal_timer mpdev_ppb$r_status1_overlay.mpdev_ppb$r_status1_bits.mpdev_ppb$v_normal_timerj#define mpdev_ppb$v_fail_timer mpdev_ppb$r_status1_overlay.mpdev_ppb$r_status1_bits.mpdev_ppb$v_fail_timerv#define mpdev_ppb$v_failback_pending mpdev_ppb$r_status1_overlay.mpdev_ppb$r_status1_bits.mpdev_ppb$v_failback_pendingz#define mpdev_ppb$v_polling_irp_active mpdev_ppb$r_s:tatus1_overlay.mpdev_ppb$r_status1_bits.mpdev_ppb$v_polling_irp_activel#define mpdev_ppb$v_scan_active mpdev_ppb$r_status1_overlay.mpdev_ppb$r_status1_bits.mpdev_ppb$v_scan_activez#define mpdev_ppb$v_path_verify_failed mpdev_ppb$r_status1_overlay.mpdev_ppb$r_status1_bits.mpdev_ppb$v_path_verify_failedp#define mpdev_ppb$v_enabled_found mpdev_ppb$r_status1_overlay.mpdev_ppb$r_status1_bits.mpdev_ppb$v_enabled_foundt#define mpdev_ppb$v_pvip_responding mpdev_ppb$r_status1_overlay.mpdev_ppb$r_status1_bi:ts.mpdev_ppb$v_pvip_respondingt#define mpdev_ppb$v_polling_started mpdev_ppb$r_status1_overlay.mpdev_ppb$r_status1_bits.mpdev_ppb$v_polling_startedK#define mpdev_ppb$l_status2 mpdev_ppb$r_status2_overlay.mpdev_ppb$l_status2t#define mpdev_ppb$v_polling_enabled mpdev_ppb$r_status2_overlay.mpdev_ppb$r_status2_bits.mpdev_ppb$v_polling_enabledt#define mpdev_ppb$v_path_is_distant mpdev_ppb$r_status2_overlay.mpdev_ppb$r_status2_bits.mpdev_ppb$v_path_is_distant"#endif /* #if !defined(__VAXC) */ N#d :efine MPDEV_PPB$C_LENGTH 976 /* Length of a MPDEV_PPB */N#define MPDEV_PPB$K_LENGTH 976 /* Length of a MPDEV_PPB */N/* List header data structure */ typedef struct _mpdev_quehdr {N struct _mpdev *mpdev_quehdr$ps_flink; /* Forward link */#pragma __member_alignmentN struct _mpdev *mpdev_quehdr$ps_blink; /* Backward link */ } MPDEV_QUEHDR;N#define MPDEV_QUEHDR$C :_LENGTH 8 /* Length of a MPDEV_QUEHDR */N#define MPDEV_QUEHDR$K_LENGTH 8 /* Length of a MPDEV_QUEHDR */N/* Mpdev acb to deliver completion AST in multipath system services */  9#ifdef __cplusplus /* Define structure prototypes */ struct _irp$r_acb64_ast_overlay; struct _iosb; #endif /* #ifdef __cplusplus */ #pragma __member_alignmenttypedef struct _mpdev_acb {N ACB64 mpdev_acb$r_base_acb; /* Imbeded ACB64 structure : */N struct _ucb *mpdev_acb$ps_desired_path; /* Pointer to desired path UCB */#pragma __member_alignment] unsigned int mpdev_acb$l_spare_1; /* spare (we'd get a filler longword here, anyway) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _iosb *mpdev_acb$pq_iosb_address; /* Pointer to IOSB */#else, unsigned __int64 mpdev_acb$pq_i :osb_address;#endif#pragma __member_alignmentN unsigned int mpdev_acb$l_efn; /* Event flag */N unsigned int mpdev_acb$l_status; /* Status */N unsigned int mpdev_acb$l_imgcnt; /* Image count */d unsigned int mpdev_acb$l_spare_2; /* another spare (again, we'd get a filler longword here) */N unsigned __int64 mpdev_acb$q_flags; /* flags */ } MPDEV_ACB;N#define MPDEV_AC:B$C_LENGTH 104 /* Length of a MPDEV_ACB */N#define MPDEV_ACB$K_LENGTH 104 /* Length of a MPDEV_ACB */P/**************************************************************************** */N/* */N/* Miscellaneous Multipath-related constants that are not public */N/* */N/* Note: Constants that are used in a sp:ecific cell of a data structure are */N/* defined inside the definition of the structure. */N/* Define constants used by the "bent pin" heuristic in MPDEV$PV_TRACK_PVS. */O/* If in the current tracking interval of MPDEV$K_TRACKING_INTERVAL seconds */S/* we've successfully successfully completed at least MPDEV$K_TRACKING_THRESHOLD */N/* MVIRP packacks, then fail any additional MVIRP packacks on this path for */N/* the remainder of the tracking interval. : */N/* */S/* These value were chosen so that this heuristic could come into play if a path */S/* were to enter into mount verification repeatedly due to frequent SCSI command */N/* timeouts, which are 24 seconds for disk commands. */N#define MPDEV$K_TRACKING_INTERVAL 300 /* Time in seconds */N#define MPDEV$K_TRACKING_THRESHOLD 10 /* Number of invocations : */[/* Constant used in [CLIUTL]SETDEVICE.B32 to check for the maximum displayable path name */N#define MPDEV$K_MAX_DSPLYPATH_SIZE 292 /* X-38 */P/* Symbolic constant for the time-limit, in seconds, for the deferral of path */N/* balancing when a newly configured path is not yet available for use. */$#define MPDEV$K_PATHBAL_AVAIL_WAIT 5  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporte:d */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MPDEVDEF_LOADED */ wwi[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard :Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., a:nd is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************************************** :*********************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */F/* Source: 12-MAY-1993 17:06:29 $1$DGA8345:[LIB_H.SRC]MPMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MPMDEF ***/#ifndef __MPMDEF_LOADED#define __MPMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __sav:e#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __:struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* MULTIPORT MEMORY (MA780/MA750) ADAPTER REGISTER OFFSET DEFINITIONS */N/*- */N/* : */R/* The UETP for the MA780 depends on some of the following definitions. Please */N/* let someone in that group know if the definitions change substantially. */N/* */P#define MPM$C_PORTS 4 /*MAXIMUM NUMBER OF PORTS PER MEMORY */#define MPM$M_CSR_PORT 0x3#define MPM$M_CSR_ADCOD 0xFF#define MPM$M_CSR_PU 0x400000#define MPM$M_CSR_PD 0x800000!#d:efine MPM$M_CSR_XMFLT 0x4000000#define MPM$M_CSR_MT 0x8000000#define MPM$M_CSR_IS 0x10000000#define MPM$M_CSR_WS 0x40000000#define MPM$M_CSR_PE 0x80000000N#define MPM$C_CSR_TYPE 64 /* MULTIPORT ADAPTER TYPE CODE */#define MPM$M_CR_MIE 0x1#define MPM$M_CR_EIE 0x2 #define MPM$M_CR_ERRS 0xFF000000#define MPM$M_SR_EIE 0x2#define MPM$M_SR_SS 0x2000#define MPM$M_SR_IDL 0x4000#define MPM$M_SR_IT 0x8000#define MPM$M_SR_AGP 0x10000000#define MPM$M_SR_XDF 0x200:00000#define MPM$M_SR_MXF 0x40000000#define MPM$M_SR_ACA 0x80000000#define MPM$M_INV_ID 0xFFFF#define MPM$M_INV_MEMSZ 0x70000"#define MPM$M_INV_STADR 0x7FF00000"#define MPM$M_INV_CACHF 0x80000000 #define MPM$M_ERR_ELR 0x10000000#define MPM$M_ERR_HI 0x20000000!#define MPM$M_ERR_ICRD 0x40000000 #define MPM$M_ERR_IMP 0x80000000#define MPM$M_CSR1_MIA 0x400N#define MPM$S_MPMDEF 40 /* Old size name - synonym */ typedef struct _mpm { __union {N : unsigned int mpm$l_csr; /*CONFIGURATION STATUS REGISTER */ __struct {N unsigned mpm$v_csr_port : 2; /* PORT NUMBER */' unsigned mpm$v_fill_0_ : 6; } mpm$r_csr_bits0; __struct {N unsigned mpm$v_csr_adcod : 8; /* ADAPTER CODE FIELD */N unsigned mpmdef$$_fill_1 : 14; /* RESERVED BITS */N unsigned mpm$v_csr_pu : 1; /* ADAPTER POWER UP : */N unsigned mpm$v_csr_pd : 1; /* ADAPTER POWER DOWN */N unsigned mpmdef$$_fill_2 : 2; /* RESERVED BITS */N unsigned mpm$v_csr_xmflt : 1; /* TRANSMITTER FAULT */N unsigned mpm$v_csr_mt : 1; /* MULTIPLE TRANSMITTERS */N unsigned mpm$v_csr_is : 1; /* INTERLOCK SEQUENCE */N unsigned mpmdef$$_fill_3 : 1; /* RESERVED BIT */N unsi :gned mpm$v_csr_ws : 1; /* WRITE SEQUENCE DATA */N unsigned mpm$v_csr_pe : 1; /* SBI PARITY ERROR */ } mpm$r_csr_bits1; } mpm$r_csr_overlay; __union {N unsigned int mpm$l_cr; /*CONTROL REGISTER */ __struct {N unsigned mpm$v_cr_mie : 1; /* MASTER INTERRUPT ENABLE */N unsigned mpm$v_cr_eie : 1; /* ERROR INTERRUPT ENABLE */N unsigned m :pmdef$$_fill_4 : 22; /* */N unsigned mpm$v_cr_errs : 8; /* PORT INTERFACE ERRORS */ } mpm$r_cr_bits; } mpm$r_cr_overlay; __union {N unsigned int mpm$l_sr; /*STATUS REGISTER */ __struct {N unsigned mpmdef$$_fill_5 : 1; /* (UNUSED) */N unsigned mpm$v_sr_eie : 1; /* ERROR INTERRUPT ENABLE */N unsigned mpmdef$$_:fill_6 : 11; /* */N unsigned mpm$v_sr_ss : 1; /* SINGLE STEP */N unsigned mpm$v_sr_idl : 1; /* INVALIDATE DATA LOST IN MPC */N unsigned mpm$v_sr_it : 1; /* INTERLOCK TIMEOUT */N unsigned mpmdef$$_fill_7 : 12; /* */N unsigned mpm$v_sr_agp : 1; /* ADMI GRANT PARITY ERROR */N unsigned mpm$v_sr_xdf : 1; /* XMIT DURING F :AULT */N unsigned mpm$v_sr_mxf : 1; /* MULTIPLE XMITTER FAULT */N unsigned mpm$v_sr_aca : 1; /* ADMI COMMAND ABORT */ } mpm$r_sr_bits; } mpm$r_sr_overlay; __union {N unsigned int mpm$l_inv; /*INVALIDATION CONTROL REGISTER */ __struct {N unsigned mpm$v_inv_id : 16; /* CACHED DEVICE NEXUS ID'S */N unsigned mpm$v_inv_memsz : 3; /* MEMORY SIZE (256KB :BOARDS) */N unsigned mpmdef$$_fill_8 : 1; /* (UNUSED) */N unsigned mpm$v_inv_stadr : 11; /* STARTING SBI ADDR OF MEMORY */N unsigned mpm$v_inv_cachf : 1; /* CACHED FORCE (IGNORE ID'S) */ } mpm$r_inv_bits; } mpm$r_inv_overlay; __union {N unsigned int mpm$l_err; /*ARRAY ERROR REGISTER */ __struct {N unsigned mpmdef$$_fill_9 : 28; /* : */N unsigned mpm$v_err_elr : 1; /* ERROR LOG REQUEST */N unsigned mpm$v_err_hi : 1; /* HIGH ERROR RATE */N unsigned mpm$v_err_icrd : 1; /* INHIBIT CRD ERRORS */N unsigned mpm$v_err_imp : 1; /* INVALIDATE MAP PARITY ERROR */ } mpm$r_err_bits; } mpm$r_err_overlay; __union {N unsigned int mpm$l_csr0; /*CONFIGURATION STATUS REGISTER 0 */ __struct :{N unsigned mpmdef$$_fill_10 : 4; /* */N unsigned mpm$v_csr0_pow : 4; /* PER PORT POWER STATUS */N unsigned mpm$v_csr0_err : 4; /* PER PORT ERROR STATUS */N unsigned mpm$v_csr0_onl : 4; /* PER PORT ONLINE STATUS */ } mpm$r_csr0_bits; } mpm$r_csr0_overlay; __union {N unsigned int mpm$l_csr1; /*CONFIGURATION STATUS REGISTER 1 */ __struct {N : unsigned mpmdef$$_fill_11 : 10; /* */N unsigned mpm$v_csr1_mia : 1; /* MULTIPLE INTERLOCK ACCEPTED */' unsigned mpm$v_fill_1_ : 5; } mpm$r_csr1_bits; } mpm$r_csr1_overlay; __union {N unsigned int mpm$l_mr; /*MAINTENANCE REGISTER */ __struct {N unsigned mpmdef$$_fill_12 : 14; /* (ERROR BITS) */N unsigned mpm$v_mr_unit : 2; /* : MEMORY UNIT NUMBER */ } mpm$r_mr_bits; } mpm$r_mr_overlay; __union {R unsigned int mpm$l_iir; /*INTERPORT INTERRUPT REQUEST REGISTER */ __struct {N unsigned mpm$v_iir_sts : 16; /* STATUS BITS (WRITE TO CLEAR) */W unsigned mpm$v_iir_ctl : 16; /* CONTROL BITS (WRITE TO SET STATUS BITS) */ } mpm$r_iir_bits; } mpm$r_iir_overlay; __union {Q unsigned int mpm$l_iie; : /*INTERPORT INTERRUPT ENABLE REGISTER */ __struct {N unsigned mpm$v_iie_sts : 16; /* CONTROL BITS (WRITE TO CLEAR) */V unsigned mpm$v_iie_ctl : 16; /* STATUS BITS (WRITE TO SET STATUS BITS) */ } mpm$r_iie_bits; } mpm$r_iie_overlay; } MPM; #if !defined(__VAXC)-#define mpm$l_csr mpm$r_csr_overlay.mpm$l_csrG#define mpm$v_csr_port mpm$r_csr_overlay.mpm$r_csr_bits0.mpm$v_csr_portI#define mpm$v_csr_adcod mpm$r_csr_overlay.mpm$r_:csr_bits1.mpm$v_csr_adcodC#define mpm$v_csr_pu mpm$r_csr_overlay.mpm$r_csr_bits1.mpm$v_csr_puC#define mpm$v_csr_pd mpm$r_csr_overlay.mpm$r_csr_bits1.mpm$v_csr_pdI#define mpm$v_csr_xmflt mpm$r_csr_overlay.mpm$r_csr_bits1.mpm$v_csr_xmfltC#define mpm$v_csr_mt mpm$r_csr_overlay.mpm$r_csr_bits1.mpm$v_csr_mtC#define mpm$v_csr_is mpm$r_csr_overlay.mpm$r_csr_bits1.mpm$v_csr_isC#define mpm$v_csr_ws mpm$r_csr_overlay.mpm$r_csr_bits1.mpm$v_csr_wsC#define mpm$v_csr_pe mpm$r_csr_overlay.mpm$r_csr_bit :s1.mpm$v_csr_pe*#define mpm$l_cr mpm$r_cr_overlay.mpm$l_cr@#define mpm$v_cr_mie mpm$r_cr_overlay.mpm$r_cr_bits.mpm$v_cr_mie@#define mpm$v_cr_eie mpm$r_cr_overlay.mpm$r_cr_bits.mpm$v_cr_eieB#define mpm$v_cr_errs mpm$r_cr_overlay.mpm$r_cr_bits.mpm$v_cr_errs*#define mpm$l_sr mpm$r_sr_overlay.mpm$l_sr@#define mpm$v_sr_eie mpm$r_sr_overlay.mpm$r_sr_bits.mpm$v_sr_eie>#define mpm$v_sr_ss mpm$r_sr_overlay.mpm$r_sr_bits.mpm$v_sr_ss@#define mpm$v_sr_idl mpm$r_sr_overlay.mpm$r_sr_bits.mpm$v_sr_idl>#def:ine mpm$v_sr_it mpm$r_sr_overlay.mpm$r_sr_bits.mpm$v_sr_it@#define mpm$v_sr_agp mpm$r_sr_overlay.mpm$r_sr_bits.mpm$v_sr_agp@#define mpm$v_sr_xdf mpm$r_sr_overlay.mpm$r_sr_bits.mpm$v_sr_xdf@#define mpm$v_sr_mxf mpm$r_sr_overlay.mpm$r_sr_bits.mpm$v_sr_mxf@#define mpm$v_sr_aca mpm$r_sr_overlay.mpm$r_sr_bits.mpm$v_sr_aca-#define mpm$l_inv mpm$r_inv_overlay.mpm$l_invB#define mpm$v_inv_id mpm$r_inv_overlay.mpm$r_inv_bits.mpm$v_inv_idH#define mpm$v_inv_memsz mpm$r_inv_overlay.mpm$r_inv_bits.mpm$v_inv :_memszH#define mpm$v_inv_stadr mpm$r_inv_overlay.mpm$r_inv_bits.mpm$v_inv_stadrH#define mpm$v_inv_cachf mpm$r_inv_overlay.mpm$r_inv_bits.mpm$v_inv_cachf-#define mpm$l_err mpm$r_err_overlay.mpm$l_errD#define mpm$v_err_elr mpm$r_err_overlay.mpm$r_err_bits.mpm$v_err_elrB#define mpm$v_err_hi mpm$r_err_overlay.mpm$r_err_bits.mpm$v_err_hiF#define mpm$v_err_icrd mpm$r_err_overlay.mpm$r_err_bits.mpm$v_err_icrdD#define mpm$v_err_imp mpm$r_err_overlay.mpm$r_err_bits.mpm$v_err_imp0#define mpm$l_csr0 mpm :$r_csr0_overlay.mpm$l_csr0H#define mpm$v_csr0_pow mpm$r_csr0_overlay.mpm$r_csr0_bits.mpm$v_csr0_powH#define mpm$v_csr0_err mpm$r_csr0_overlay.mpm$r_csr0_bits.mpm$v_csr0_errH#define mpm$v_csr0_onl mpm$r_csr0_overlay.mpm$r_csr0_bits.mpm$v_csr0_onl0#define mpm$l_csr1 mpm$r_csr1_overlay.mpm$l_csr1H#define mpm$v_csr1_mia mpm$r_csr1_overlay.mpm$r_csr1_bits.mpm$v_csr1_mia*#define mpm$l_mr mpm$r_mr_overlay.mpm$l_mrB#define mpm$v_mr_unit mpm$r_mr_overlay.mpm$r_mr_bits.mpm$v_mr_unit-#define mpm$l_iir mp :m$r_iir_overlay.mpm$l_iirD#define mpm$v_iir_sts mpm$r_iir_overlay.mpm$r_iir_bits.mpm$v_iir_stsD#define mpm$v_iir_ctl mpm$r_iir_overlay.mpm$r_iir_bits.mpm$v_iir_ctl-#define mpm$l_iie mpm$r_iie_overlay.mpm$l_iieD#define mpm$v_iie_sts mpm$r_iie_overlay.mpm$r_iie_bits.mpm$v_iie_stsD#define mpm$v_iie_ctl mpm$r_iie_overlay.mpm$r_iie_bits.mpm$v_iie_ctl"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragma:s supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MPMDEF_LOADED */ wwз[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-:Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software,: Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************** :*****************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */F/* Source: 25-MAR-2004 10:31:49 $1$DGA8345:[LIB_H.SRC]MPWDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MPWDEF ***/#ifndef __MPWDEF_LOADED#define __MPWDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignme:nt __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #i:fndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define MPW$C_MAINTAIN 1#define MPW$C_SVAPTE 2#define MPW$C_OPCCRASH 3#define MPW$C_PAGE_TABLE 4#define MPW$C_IDLE 0#define MPW$C_MAINT_STATE 1#define MPW$C_SELECTIVE 2#define MPW$C_CRASH_STATE 3#define MPW$C_MAXSTATE 4#define MPW$C_DP:TSCAN 0#define MPW$C_DGBLSC 1#define MPW$C_RELPHD 2#define MPW$C_FREELIM 3#define MPW$C_MPWCHECK 4#define MPW$C_CRASH 5#define MPW$C_MAXID 6#define MPW$M_RCODE 0xFF#define MPW$M_RMODIFIERS 0xFF00#define MPW$M_RESERVED 0xFF0000#define MPW$M_IDCODE 0xFF000000#define MPW$M_LOLIMIT 0x100N#define MPW$S_MPWDEF 4 /* Old size name - synonym */ typedef struct _mpw {N/* Basic request code/modifiers structure */Z : __union { /* Union to generate appropriate $S_ size field */N int mpw$l_mpw_arg; /* Entire MPW structure */ __struct {N unsigned mpw$v_rcode : 8; /* Request Code Field */N unsigned mpw$v_rmodifiers : 8; /* Request Modifiers Field */( unsigned mpw$v_reserved : 8;N unsigned mpw$v_idcode : 8; /* Requestor ID code Field */$ } mpw$r_rcode_struct :ure;N/* Request modifiers for MAINTAIN request */ __struct {* unsigned mpw$v_rcode_fill : 8;O unsigned mpw$v_lolimit : 1; /* New MPL low limit specified in R1 */' unsigned mpw$v_fill_0_ : 7;' } mpw$r_maintain_modifiers; } mpw$r_fill_union; } MPW; #if !defined(__VAXC)4#define mpw$l_mpw_arg mpw$r_fill_union.mpw$l_mpw_argF#define mpw$v_rcode mpw$r_fill_union.mpw$r_rcode_structure.mpw$v_r :codeP#define mpw$v_rmodifiers mpw$r_fill_union.mpw$r_rcode_structure.mpw$v_rmodifiersL#define mpw$v_reserved mpw$r_fill_union.mpw$r_rcode_structure.mpw$v_reservedH#define mpw$v_idcode mpw$r_fill_union.mpw$r_rcode_structure.mpw$v_idcodeM#define mpw$v_lolimit mpw$r_fill_union.mpw$r_maintain_modifiers.mpw$v_lolimit"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_p:ointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MPWDEF_LOADED */ ww-[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, :and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** au:thorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************************************************** :*****************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */G/* Source: 08-DEC-2016 23:33:20 $1$DGA8345:[LIB_H.SRC]MSCPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MSCPDEF ***/#ifndef __MSCPDEF_LOADED#define __MSCPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_a:lignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__V:AXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* MSCP (Mass Storage Control Protocol) Definitions */N/* */K/* These definitions describe the format of the :command and end message */I/* packets exchanged under MSCP between the host and the controller. */N/*-- */ #define MSCP$M_EU_NO 0xFF#define MSCP$M_EU_SUBU 0x7#define MSCP$M_EU_SUBC 0xF8#define MSCP$K_EMS_CNSL 0#define MSCP$K_EMS_RP 1#define MSCP$K_EMS_RM 2#define MSCP$K_EMS_RK 3#define MSCP$K_EMS_RL 4#define MSCP$K_EMS_RX 5#define MSCP$K_EMS_FD1 6#define MSCP$K_EMS_FD2 7#define MSCP$K_EMS_F:D3 8#define MSCP$K_EMS_FD4 9#define MSCP$K_EMS_FD5 10#define MSCP$K_EMS_FD6 11#define MSCP$K_EMS_FD7 12#define MSCP$K_EMS_FD8 13#define MSCP$M_EU_CTYPE 0xF00#define MSCP$K_EMD_OLD 0#define MSCP$K_EMD_UDA 1#define MSCP$K_EMD_HSC 2#define MSCP$K_EMD_AZT 3#define MSCP$K_EMD_RDRX 4#define MSCP$K_EMD_EMUL 5#define MSCP$M_EU_DESIG 0x7000#define MSCP$M_SHADOW 0x8000#define MSCP$M_OP_ATTN 0x40#define MSCP$M_OP_END 0x80#define MSCP$M_MD_SEREC 0x100#define MSCP$M_MD_:SECOR 0x200#define MSCP$M_MD_CLSEX 0x2000#define MSCP$M_MD_COMP 0x4000#define MSCP$M_MD_WRSEQ 0x10#define MSCP$M_MD_WBKVL 0x20#define MSCP$M_MD_WBKNV 0x40#define MSCP$M_MD_SSHDW 0x80#define MSCP$M_MD_SCCHL 0x400#define MSCP$M_MD_SCCHH 0x800#define MSCP$M_MD_ERROR 0x1000#define MSCP$M_MD_EXPRS 0x8000#define MSCP$M_MD_REWND 0x2#define MSCP$M_MD_OBJCT 0x4#define MSCP$M_MD_REVRS 0x8#define MSCP$M_MD_UNLOD 0x10#define MSCP$M_MD_IMMED 0x40#define MSCP$M_MD_DLEOT 0x80 :#define MSCP$M_MD_INHERLOG 0x200#define MSCP$M_MD_CDATL 0x1000#define MSCP$M_MD_SPNDW 0x1#define MSCP$M_MD_ALLCD 0x2#define MSCP$M_MD_DSOLV 0x10#define MSCP$M_MD_FLENU 0x1#define MSCP$M_MD_VOLTL 0x2#define MSCP$M_MD_NXUNT 0x1#define MSCP$M_MD_RIP 0x1#define MSCP$M_MD_IGNMF 0x2#define MSCP$M_MD_STWRP 0x4#define MSCP$M_MD_CLWBL 0x8#define MSCP$M_MD_SHDSP 0x10#define MSCP$M_MD_EXCAC 0x20#define MSCP$M_MD_PRIMR 0x1#define MSCP$M_MD_CRNPR 0x1#define MSCP$M_MD_ENRW:R 0x10#define MSCP$M_MD_TBC 0x8000#define MSCP$M_MD_HISLO 0x8#define MSCP$M_MD_SUPWL 0x10#define MSCP$M_MD_REUSE 0x80#define MSCP$M_MD_LOCSU 0x1#define MSCP$M_MD_ESTCP 0x2#define MSCP$M_MD_RETCP 0x4U#define MSCP$S_MSCP_MODIFIERS 12 /* MSCP_MODIFIERS used to be an aggregate. */N/* We need to generate the old size field */#define MSCP$M_EF_CPRET 0x1#define MSCP$M_EF_DLS 0x2#define MSCP$M_EF_PLS 0x4#define MSCP$M_EF_EOT 0x8#defin:e MSCP$M_EF_SEREX 0x10#define MSCP$M_EF_ERLOG 0x20#define MSCP$M_EF_BBLKU 0x40#define MSCP$M_EF_BBLKR 0x80#define MSCP$M_EF_HISLO 0x4#define MSCP$M_EF_ALLOF 0x8$#define MSCP$M_EF_FASTSKIP_USED 0x80#define MSCP$M_ST_MASK 0x1F#define MSCP$K_ST_SUCC 0#define MSCP$K_ST_ICMD 1#define MSCP$K_ST_ABRTD 2#define MSCP$K_ST_OFFLN 3#define MSCP$K_ST_AVLBL 4#define MSCP$K_ST_MFMTE 5#define MSCP$K_ST_WRTPR 6#define MSCP$K_ST_COMP 7#define MSCP$K_ST_DATA 8#define MSCP$K_ST_HS:TBF 9#define MSCP$K_ST_CNTLR 10#define MSCP$K_ST_DRIVE 11#define MSCP$K_ST_FMTER 12#define MSCP$K_ST_BOT 13#define MSCP$K_ST_TAPEM 14#define MSCP$K_ST_SHST 12#define MSCP$K_ST_WHEAE 13#define MSCP$K_ST_RDTRN 16#define MSCP$K_ST_PLOST 17#define MSCP$K_ST_PRESE 18#define MSCP$K_ST_LED 19#define MSCP$K_ST_BBR 20#define MSCP$K_ST_IPARM 21#define MSCP$K_ST_INFO 22#define MSCP$K_ST_LOADR 23#define MSCP$K_ST_HOST 24#define MSCP$K_ST_UNREC 20#define MSCP$K_ST_SBCERR 30 :#define MSCP$K_ST_DIAG 31#define MSCP$K_ST_SBCOD 32#define MSCP$M_ST_SBCOD 0xFFE0N#define MSCP$K_SC_NORML 0 /* Normal */N#define MSCP$K_SC_SDIGN 1 /* Spin Down IGNored */N#define MSCP$K_SC_STCON 2 /* STill CONnected */N#define MSCP$K_SC_DUPUN 4 /* DUPlicate UNit number */N#define MSCP$K_SC_ALONL 8 /* ALready ONLine */N#define MSCP$K_S :C_STONL 16 /* STill ONLine */N#define MSCP$K_SC_EOT 32 /* EOT encountered (tapes only) */Q#define MSCP$K_SC_INREP 32 /* INcomplete REPlacement (disks only) */N#define MSCP$K_SC_IVRCT 64 /* InValid RCT (disks only) */N#define MSCP$K_SC_RDONY 128 /* ReaD ONlY volume format */#define MSCP$M_SC_SDIGN 0x20#define MSCP$M_SC_STCON 0x40#define MSCP$M_SC_DUPUN 0x80#define MSCP$M_SC_ALONL 0x10 :0#define MSCP$M_SC_STONL 0x200#define MSCP$M_SC_EOT 0x400#define MSCP$M_SC_INREP 0x400#define MSCP$M_SC_IVRCT 0x800#define MSCP$M_SC_RDONY 0x1000N#define MSCP$K_SC_INVML 0 /* INValid Message Length */N/* Unit-Offline Subcode Values */[#define MSCP$K_SC_UNKNO 0 /* UNKoNOwn unit or online to another controller */\#define MSCP$K_SC_NOVOL 1 /* NO VOLume mounted or drive disabled (RUN/STOP) :*/N#define MSCP$K_SC_INOPR 2 /* unit is INOPeRative */Z#define MSCP$K_SC_UDSBL 8 /* Unit disabled by field service or diagnostic */N#define MSCP$K_SC_EXUSE 16 /* Exclusive use */N#define MSCP$K_SC_LDR 32 /* Loader cycle error */#define MSCP$M_SC_NOVOL 0x20#define MSCP$M_SC_INOPR 0x40#define MSCP$M_SC_UDSBL 0x100#define MSCP$M_SC_EXUSE 0x200#define MSCP$M_SC_LDR 0x400N#define MSCP$K_S :C_CPYIP 2 /* Copy in progress */N#define MSCP$K_SC_NOMEM 4 /* No members in shadow set */N#define MSCP$K_SC_ALUSE 32 /* Already in use */#define MSCP$M_SC_CPYIP 0x40#define MSCP$M_SC_NOMEM 0x80#define MSCP$M_SC_ALUSE 0x400#define MSCP$K_SC_IVHD 2#define MSCP$K_SC_NOSYNC 3#define MSCP$K_SC_SSCM 4#define MSCP$K_SC_NO512 5#define MSCP$K_SC_NOFMT 6#define MSCP$K_SC_ECCER 7#define MSCP$K_SC_RCTBD 8 :#define MSCP$K_SC_NORBL 9N/* Write-Protected Subcode Values */]#define MSCP$K_SC_DATAL 8 /* Unit is DATA Loss write protected (data safety) */N#define MSCP$K_SC_SOFTW 128 /* Unit is SOFTWare protected */N#define MSCP$K_SC_HARDW 256 /* Unit is HARDWare protected */#define MSCP$M_SC_DATAL 0x100#define MSCP$M_SC_SOFTW 0x1000#define MSCP$M_SC_HARDW 0x2000N#define MSCP$K_SC_FRCER 0 /* F :orced Error (disks) */N#define MSCP$K_SC_LGE 0 /* Long Gap Encountered (tapes) */N#define MSCP$K_SC_MEDIA 3 /* Media error. */N/* Host Buffer Access Error Subcode Values */#define MSCP$K_SC_ODDTA 1#define MSCP$K_SC_ODDBC 2#define MSCP$K_SC_NXM 3#define MSCP$K_SC_MPAR 4#define MSCP$K_SC_IVPTE 5#define MSCP$K_SC_IVBFN 6#define MSCP$K_SC_BLENV 7#define MSCP$K_SC_ACVIO 8N/* Control:ler Error Subcode Values */#define MSCP$K_SC_DLATE 1#define MSCP$K_SC_EDCER 2#define MSCP$K_SC_DTSTR 3#define MSCP$K_SC_IEDC 4#define MSCP$K_SC_LACIN 5#define MSCP$K_SC_LACOU 6#define MSCP$K_SC_LACCB 7#define MSCP$K_SC_OVRUN 8#define MSCP$K_SC_MEMER 9#define MSCP$K_SC_REMRSRC 10#define MSCP$K_SC_RCONL 20#define MSCP$K_SC_RCONF 21#define MSCP$K_SC_BADSA 22#define MSCP$K_SC_NOSER 23#define MSCP$K_SC_NORES 24#define MSCP$K_S:C_NOCRE 25#define MSCP$K_SC_BADPR 26#define MSCP$K_SC_NEGAK 27#define MSCP$K_SC_TMOUT 28#define MSCP$K_SC_LCONF 29#define MSCP$K_SC_DISCN 30N/* Bad Block Replacement Subcode Values */#define MSCP$K_SC_BBROK 0#define MSCP$K_SC_NOTRP 1#define MSCP$K_SC_RPLFL 2#define MSCP$K_SC_ICRCT 3#define MSCP$K_SC_DRVER 4#define MSCP$K_SC_RCTFULL 5#define MSCP$K_SC_RECURFAIL 6N/* Unrecognized Media Subcode Values : */#define MSCP$K_SC_NOTAPEFMT 1N/* Invalid Parameter Subcode Values */#define MSCP$K_SC_IVKLN 1#define MSCP$K_SC_IVKTY 2#define MSCP$K_SC_IVKVL 3N/* Media Loader Error Subcode Values */#define MSCP$K_SC_ML_TMO 1#define MSCP$K_SC_ML_TXERR 2#define MSCP$K_SC_ML_PRTCL 3#define MSCP$K_SC_ML_ERROR 4N/* Host Error Subcode Values */#define MSCP$K_SC_SEGUND:R 1N/* Write History Entry Access Error Subcode Values */#define MSCP$K_SC_ALLOF 1#define MSCP$K_SC_TABFU 2#define MSCP$K_SC_NOENT 8#define MSCP$M_SC_ALLOF 0x2#define MSCP$M_SC_TABFU 0x4#define MSCP$M_SC_NOENT 0x10#define MSCP$K_SC_DCDC 3N/* Subcommand Error Status or Event Subcode Values */#define MSCP$K_SC_DST_TIMOUT 1#define MSCP$K_SC_DST_INCSTA 2#define MSCP$K_SC_DST_UNRCOV 4!#define MSCP$K_SC_SRC_TIMOUT 1025!#define :MSCP$K_SC_SRC_INCSTA 1026!#define MSCP$K_SC_SRC_UNRCOV 1028#define MSCP$S_MSCP_SUBCODES 12 typedef struct _mscp_basic_pkt {N unsigned int mscp$l_cmd_ref; /* Command reference number */ __union { __union {N unsigned short int mscp$w_unit; /* Unit number */ __struct { __union {N unsigned mscp$v_eu_no : 8; /* Emulated unit number */ __struct {P : unsigned mscp$v_eu_subu : 3; /* Old-style unit number */W unsigned mscp$v_eu_subc : 5; /* Old-style controller subtype */+ } mscp$r_eu_sub_no;+ } mscp$r_eu_no_overlay;N unsigned mscp$v_eu_ctype : 4; /* Emulated controller type */R unsigned mscp$v_eu_desig : 3; /* Emulated controller designator */N unsigned mscp$v_shadow : 1; /* Shadow unit */! : } mscp$r_fill_1_; } mscp$r_fill_0_;& unsigned char mscp$b_cnt_alcs; } mscp$r_unit_overlay;N unsigned short int mscp$w_seq_num; /* Sequence number (LAST error log) */ __union {N unsigned char mscp$b_opcode; /* MSCP operation code */ __struct {% unsigned mscp$v_code : 3;% unsigned mscp$v_type : 3;N unsigned mscp$v_op_attn : 1; /* Attention message */N :unsigned mscp$v_op_end : 1; /* End message */ } mscp$r_fill_3_; } mscp$r_fill_2_; __union { __struct {! char mscp$b_reserved; __union {P unsigned short int mscp$w_modifier; /* MSCP command modifiers */N/* Generic MSCP Modifiers */ __struct {0 unsigned mscp$v_filler1 : 8;Q unsigned mscp$v_md :_serec : 1; /* Suppress error recovery */S unsigned mscp$v_md_secor : 1; /* Suppress error correction */0 unsigned mscp$v_filler2 : 3;Q unsigned mscp$v_md_clsex : 1; /* Clear serious exception */N unsigned mscp$v_md_comp : 1; /* Compare */1 unsigned mscp$v_fill_10_ : 1;/ } mscp$r_generic_modifiers; __struct {0 unsigned: mscp$v_filler1 : 4;[ unsigned mscp$v_md_wrseq : 1; /* Write shadow set 1 unit at a time */O unsigned mscp$v_md_wbkvl : 1; /* Write-back (volatile) */S unsigned mscp$v_md_wbknv : 1; /* Write-back (non-volatile) */N unsigned mscp$v_md_sshdw : 1; /* Suppress Shadowing */0 unsigned mscp$v_filler2 : 2;V unsigned mscp$v_md_scchl : 1; /* Suppress caching (low speed) */W ; unsigned mscp$v_md_scchh : 1; /* Suppress caching (high speed) */N unsigned mscp$v_md_error : 1; /* Force error */0 unsigned mscp$v_filler3 : 2;N unsigned mscp$v_md_exprs : 1; /* Express request */, } mscp$r_disk_modifiers; __struct {0 unsigned mscp$v_filler1 : 1;N unsigned mscp$v_md_rewnd : 1; /* Rewind */N ; unsigned mscp$v_md_objct : 1; /* Object count */N unsigned mscp$v_md_revrs : 1; /* Reverse */N unsigned mscp$v_md_unlod : 1; /* Unload */0 unsigned mscp$v_filler2 : 1;V unsigned mscp$v_md_immed : 1; /* Request immediate completion */N unsigned mscp$v_md_dleot : 1; /* Request detect LEOT */0 unsigned mscp$v_filler3 : 1;R ; unsigned mscp$v_md_inherlog : 1; /* Inhibit error logging */0 unsigned mscp$v_filler4 : 2;P unsigned mscp$v_md_cdatl : 1; /* Clear Cached Data Lost */1 unsigned mscp$v_fill_11_ : 3;, } mscp$r_tape_modifiers; __struct {N unsigned mscp$v_md_spndw : 1; /* Spin down */N unsigned mscp$v_md_allcd : 1; /* All class drivers */1 ; unsigned mscp$v_reserved : 2;N unsigned mscp$v_md_dsolv : 1; /* Disolve shadow set */. unsigned mscp$v_excac : 1;1 unsigned mscp$v_fill_12_ : 2;- } mscp$r_avail_modifiers; __struct {N unsigned mscp$v_md_flenu : 1; /* Flush entire unit */N unsigned mscp$v_md_voltl : 1; /* Flush volitile only */1 unsigned mscp$v_fill ;_13_ : 6;- } mscp$r_flush_modifiers; __struct {N unsigned mscp$v_md_nxunt : 1; /* Next unit */1 unsigned mscp$v_fill_14_ : 7;- } mscp$r_gtunt_modifiers; __struct {Y unsigned mscp$v_md_rip : 1; /* Allow self-destruct (online only) */a unsigned mscp$v_md_ignmf : 1; /* Ignore media format error (online only) */R ; unsigned mscp$v_md_stwrp : 1; /* Enable Set Write Protect */T unsigned mscp$v_md_clwbl : 1; /* Clear Write-Back Data Lost */O unsigned mscp$v_md_shdsp : 1; /* Shadow Unit Specified */N unsigned mscp$v_md_excac : 1; /* Exclusive access */1 unsigned mscp$v_fill_15_ : 2;3 } mscp$r_onlin_stunt_modifiers; __struct {S unsigned mscp$v_md_primr : 1; /* ; Primary replacement block */1 unsigned mscp$v_fill_16_ : 7;- } mscp$r_replc_modifiers; __struct {^ unsigned mscp$v_md_crnpr : 1; /* Connection Reference Number Present */1 unsigned mscp$v_fill_17_ : 7;- } mscp$r_stcon_modifiers; __struct {/ unsigned mscp$v_filler : 4;` unsigned mscp$v_md_enrwr : 1; /* Enable Re-W ;rite Error Recovery (tapes) */1 unsigned mscp$v_fill_18_ : 3;- } mscp$r_write_modifiers; __struct {0 unsigned mscp$v_filler : 15;Y unsigned mscp$v_md_tbc : 1; /* To-be-continued (segmented tapes) */0 } mscp$r_seg_xfer_modifiers; __struct {/ unsigned mscp$v_fill_2 : 3;N unsigned mscp$v_md_hislo : 1; /* History Log ; */Q unsigned mscp$v_md_supwl : 1; /* Supplementary Write Log *// unsigned mscp$v_fill_1 : 2;N unsigned mscp$v_md_reuse : 1; /* Reuse Entry */7 } mscp$r_erase_write_dcd_modifiers; __struct {N unsigned mscp$v_md_locsu : 1; /* Local Source Unit */Y unsigned mscp$v_md_estcp : 1; /* Establish Communications Paths */U unsi ;gned mscp$v_md_retcp : 1; /* Retain Communications Paths */1 unsigned mscp$v_fill_19_ : 5;+ } mscp$r_dcd_modifiers;( } mscp$r_mscp_modifiers;N/* to keep the output compatible. */ } mscp$r_modifiers; __struct { __union { __union {N unsigned char mscp$b_flags; /* End message flags */ __struct {X ; unsigned mscp$v_ef_cpret : 1; /* Communication Paths Retained */W unsigned mscp$v_ef_dls : 1; /* Cached Data Lost (tapes only) */T unsigned mscp$v_ef_pls : 1; /* Position Lost (tapes only) */^ unsigned mscp$v_ef_eot : 1; /* End of Tape Encountered (tapes only) */Z unsigned mscp$v_ef_serex : 1; /* Serious exception (tapes only) */O unsigned mscp$v_ef_erlog : 1 ;; /* Error log generated */] unsigned mscp$v_ef_bblku : 1; /* Bad block unreported (disks only) */[ unsigned mscp$v_ef_bblkr : 1; /* Bad block reported (disks only) */) } mscp$r_fill_5_;% } mscp$r_fill_4_; __union {0 unsigned char mscp$b_flags1; __struct {4 unsigned mscp$v_filler1 : 2;N unsigned msc ;p$v_ef_hislo : 1; /* History Logged */N unsigned mscp$v_ef_allof : 1; /* Allocation Failure */4 unsigned mscp$v_filler2 : 3;x unsigned mscp$v_ef_fastskip_used : 1; /* MT$M_FASTSKIP_USED was set (TMSCP served tapes only) */) } mscp$r_fill_7_;% } mscp$r_fill_6_;' } mscp$r_flags_overlay; __union { __union {N unsigned ; short int mscp$w_status; /* End message status */ __struct {N unsigned mscp$v_st_mask : 5; /* Status code bits */N unsigned mscp$v_st_sbcod : 11; /* Subcode bits */) } mscp$r_fill_9_;% } mscp$r_fill_8_;N/* Success Subcode Values */ __struct { __union {# __struct ;{7 unsigned mscp$v_filler : 5;Q unsigned mscp$v_sc_sdign : 1; /* Spin Down IGNored */O unsigned mscp$v_sc_stcon : 1; /* STill CONnected */U unsigned mscp$v_sc_dupun : 1; /* DUPlicate UNit number */N unsigned mscp$v_sc_alonl : 1; /* ALready ONLine */N unsigned mscp$v_sc_stonl : 1; /* STill ONLine */Z un;signed mscp$v_sc_eot : 1; /* EOT encountered (tapes only) */9 unsigned mscp$v_fill_20_ : 5;. } mscp$r_fields_1;# __struct {8 unsigned mscp$v_filler : 10;c unsigned mscp$v_sc_inrep : 1; /* INcomplete REPlacement (disks only) */X unsigned mscp$v_sc_ivrct : 1; /* InValid RCT (disks only) */W unsigned mscp$v_sc_r ;dony : 1; /* ReaD ONlY volume format */9 unsigned mscp$v_fill_21_ : 3;- } mscp$r_field_2;, } mscp$r_bit_fields;% } mscp$r_sc_succ;N/* Invalid Command Subcode Values */ __struct {/ unsigned mscp$v_filler : 5;f unsigned mscp$v_sc_novol : 1; /* NO VOLume mounted or drive disabled (RUN/STOP) */N ; unsigned mscp$v_sc_inopr : 1; /* unit is INOPeRative */. unsigned mscp$v_dupun : 1;d unsigned mscp$v_sc_udsbl : 1; /* Unit disabled by field service or diagnostic */N unsigned mscp$v_sc_exuse : 1; /* Exclusive use */N unsigned mscp$v_sc_ldr : 1; /* Loader cycle error */1 unsigned mscp$v_fill_22_ : 5;& } mscp$r_sc_offln;N/* Unit-Available Subcode Valu ;es */ __struct {/ unsigned mscp$v_filler : 5;2 unsigned mscp$v_reserved1 : 1;N unsigned mscp$v_sc_cpyip : 1; /* Copy in progress */P unsigned mscp$v_sc_nomem : 1; /* No members in shadow set */2 unsigned mscp$v_reserved2 : 2;N unsigned mscp$v_sc_aluse : 1; /* Already in use */1 unsigned m ;scp$v_fill_23_ : 5;& } mscp$r_sc_avlbl;N/* Media Format Error Subcode Values */ __struct {0 unsigned mscp$v_filler1 : 8;g unsigned mscp$v_sc_datal : 1; /* Unit is DATA Loss write protected (data safety) */0 unsigned mscp$v_filler2 : 3;S unsigned mscp$v_sc_softw : 1; /* Unit is SOFTWare protected */S unsigned mscp$v_sc_har ;dw : 1; /* Unit is HARDWare protected */1 unsigned mscp$v_fill_24_ : 2;& } mscp$r_sc_wrtpr;N/* Data Error Subcode Values */ __struct { __struct {4 unsigned mscp$v_filler1 : 1;5 unsigned mscp$v_sc_allof : 1;5 unsigned mscp$v_sc_tabfu : 1;4 unsigned mscp$v_filler2 : 1;5 ; unsigned mscp$v_sc_noent : 1;5 unsigned mscp$v_fill_25_ : 3;( } mscp$r_fields;& } mscp$r_sc_wheae;N/* Informational Event Subcode */' } mscp$r_mscp_subcodes;" } mscp$r_flags_status;" } mscp$r_modifiers_status; } MSCP_BASIC_PKT; #if !defined(__VAXC)B#define mscp$w_unit mscp$r_unit_overlay.mscp$r_fill_0_.mscp$w_unith#defin;e mscp$v_eu_no mscp$r_unit_overlay.mscp$r_fill_0_.mscp$r_fill_1_.mscp$r_eu_no_overlay.mscp$v_eu_no}#define mscp$v_eu_subu mscp$r_unit_overlay.mscp$r_fill_0_.mscp$r_fill_1_.mscp$r_eu_no_overlay.mscp$r_eu_sub_no.mscp$v_eu_subu}#define mscp$v_eu_subc mscp$r_unit_overlay.mscp$r_fill_0_.mscp$r_fill_1_.mscp$r_eu_no_overlay.mscp$r_eu_sub_no.mscp$v_eu_subcY#define mscp$v_eu_ctype mscp$r_unit_overlay.mscp$r_fill_0_.mscp$r_fill_1_.mscp$v_eu_ctypeY#define mscp$v_eu_desig mscp$r_unit_overlay.mscp$r_fill_0_;.mscp$r_fill_1_.mscp$v_eu_desigU#define mscp$v_shadow mscp$r_unit_overlay.mscp$r_fill_0_.mscp$r_fill_1_.mscp$v_shadow;#define mscp$b_cnt_alcs mscp$r_unit_overlay.mscp$b_cnt_alcs2#define mscp$b_opcode mscp$r_fill_2_.mscp$b_opcodeC#define mscp$v_op_attn mscp$r_fill_2_.mscp$r_fill_3_.mscp$v_op_attnA#define mscp$v_op_end mscp$r_fill_2_.mscp$r_fill_3_.mscp$v_op_endf#define mscp$w_modifier mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$w_modifier#define mscp$v_md_serec mscp;$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_generic_modifiers.mscp$v_md_serec#define mscp$v_md_secor mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_generic_modifiers.mscp$v_md_secor#define mscp$v_md_clsex mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_generic_modifiers.mscp$v_md_clsex}#define mscp$v_md_comp mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_generic_modifiers.mscp$v_md_comp|#define mscp$v_m;d_wrseq mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_disk_modifiers.mscp$v_md_wrseq|#define mscp$v_md_wbkvl mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_disk_modifiers.mscp$v_md_wbkvl|#define mscp$v_md_wbknv mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_disk_modifiers.mscp$v_md_wbknv|#define mscp$v_md_sshdw mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_disk_modifiers.mscp$v_md_sshdw|#define mscp$v_md_;scchl mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_disk_modifiers.mscp$v_md_scchl|#define mscp$v_md_scchh mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_disk_modifiers.mscp$v_md_scchh|#define mscp$v_md_error mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_disk_modifiers.mscp$v_md_error|#define mscp$v_md_exprs mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_disk_modifiers.mscp$v_md_exprs|#define mscp$v_md_re;wnd mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_tape_modifiers.mscp$v_md_rewnd|#define mscp$v_md_objct mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_tape_modifiers.mscp$v_md_objct|#define mscp$v_md_revrs mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_tape_modifiers.mscp$v_md_revrs|#define mscp$v_md_unlod mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_tape_modifiers.mscp$v_md_unlod|#define mscp$v_md_imme;d mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_tape_modifiers.mscp$v_md_immed|#define mscp$v_md_dleot mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_tape_modifiers.mscp$v_md_dleot#define mscp$v_md_inherlog mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_tape_modifiers.mscp$v_md_inherlog|#define mscp$v_md_cdatl mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_tape_modifiers.mscp$v_md_cdatl}#define mscp$v_md_;spndw mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_avail_modifiers.mscp$v_md_spndw}#define mscp$v_md_allcd mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_avail_modifiers.mscp$v_md_allcd}#define mscp$v_md_dsolv mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_avail_modifiers.mscp$v_md_dsolv}#define mscp$v_md_flenu mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_flush_modifiers.mscp$v_md_flenu}#define mscp;$v_md_voltl mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_flush_modifiers.mscp$v_md_voltl}#define mscp$v_md_nxunt mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_gtunt_modifiers.mscp$v_md_nxunt#define mscp$v_md_rip mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_onlin_stunt_modifiers.mscp$v_md_rip#define mscp$v_md_ignmf mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_onlin_stunt_modifiers.mscp$v_md_ignmf;#define mscp$v_md_stwrp mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_onlin_stunt_modifiers.mscp$v_md_stwrp#define mscp$v_md_clwbl mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_onlin_stunt_modifiers.mscp$v_md_clwbl#define mscp$v_md_shdsp mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_onlin_stunt_modifiers.mscp$v_md_shdsp#define mscp$v_md_excac mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_onlin_st ;unt_modifiers.mscp$v_md_excac}#define mscp$v_md_primr mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_replc_modifiers.mscp$v_md_primr}#define mscp$v_md_crnpr mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_stcon_modifiers.mscp$v_md_crnpr}#define mscp$v_md_enrwr mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_write_modifiers.mscp$v_md_enrwr|#define mscp$v_md_tbc mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$!;r_seg_xfer_modifiers.mscp$v_md_tbc#define mscp$v_md_hislo mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_erase_write_dcd_modifiers.mscp$v_md_h\islo#define mscp$v_md_supwl mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_erase_write_dcd_modifiers.mscp$v_md_s\upwl#define mscp$v_md_reuse mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_erase_write_dcd_modifiers.mscp$v_md_r\euse{#define mscp$v_md_locsu mscp$r_modifiers_status.ms";cp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_dcd_modifiers.mscp$v_md_locsu{#define mscp$v_md_estcp mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_dcd_modifiers.mscp$v_md_estcp{#define mscp$v_md_retcp mscp$r_modifiers_status.mscp$r_modifiers.mscp$r_mscp_modifiers.mscp$r_dcd_modifiers.mscp$v_md_retcpq#define mscp$b_flags mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_flags_overlay.mscp$r_fill_4_.mscp$b_flags#define mscp$v_ef_cpret mscp$r_modifiers_status.mscp$r_flags_s#;tatus.mscp$r_flags_overlay.mscp$r_fill_4_.mscp$r_fill_5_.mscp$v_ef_cp\ret#define mscp$v_ef_dls mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_flags_overlay.mscp$r_fill_4_.mscp$r_fill_5_.mscp$v_ef_dls#define mscp$v_ef_pls mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_flags_overlay.mscp$r_fill_4_.mscp$r_fill_5_.mscp$v_ef_pls#define mscp$v_ef_eot mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_flags_overlay.mscp$r_fill_4_.mscp$r_fill_5_.mscp$v_ef_eot#define mscp$v_ef_serex mscp$r_m$;odifiers_status.mscp$r_flags_status.mscp$r_flags_overlay.mscp$r_fill_4_.mscp$r_fill_5_.mscp$v_ef_se\rex#define mscp$v_ef_erlog mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_flags_overlay.mscp$r_fill_4_.mscp$r_fill_5_.mscp$v_ef_er\log#define mscp$v_ef_bblku mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_flags_overlay.mscp$r_fill_4_.mscp$r_fill_5_.mscp$v_ef_bb\lku#define mscp$v_ef_bblkr mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_flags_overlay.mscp$r_fill_4_.mscp$r_fill_5_ %;.mscp$v_ef_bb\lkr#define mscp$v_ef_hislo mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_flags_overlay.mscp$r_fill_6_.mscp$r_fill_7_.mscp$v_ef_hi\slo#define mscp$v_ef_allof mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_flags_overlay.mscp$r_fill_6_.mscp$r_fill_7_.mscp$v_ef_al\lof#define mscp$v_ef_fastskip_used mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_flags_overlay.mscp$r_fill_6_.mscp$r_fill_7_.mscp\$v_ef_fastskip_useds#define mscp$w_status mscp$r_modifiers_status.ms&;cp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_fill_8_.mscp$w_status#define mscp$v_st_mask mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_fill_8_.mscp$r_fill_9_.mscp$v_st_mask#define mscp$v_st_sbcod mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_fill_8_.mscp$r_fill_9_.mscp$v_st_sb\cod#define mscp$v_sc_sdign mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_succ.mscp$r_bit_fields.mscp$r_fi\elds_1.mscp$v_sc_sdign#def';ine mscp$v_sc_stcon mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_succ.mscp$r_bit_fields.mscp$r_fi\elds_1.mscp$v_sc_stcon#define mscp$v_sc_dupun mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_succ.mscp$r_bit_fields.mscp$r_fi\elds_1.mscp$v_sc_dupun#define mscp$v_sc_alonl mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_succ.mscp$r_bit_fields.mscp$r_fi\elds_1.mscp$v_sc_alonl#define mscp$v_sc_stonl mscp$r_modif(;iers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_succ.mscp$r_bit_fields.mscp$r_fi\elds_1.mscp$v_sc_stonl#define mscp$v_sc_eot mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_succ.mscp$r_bit_fields.mscp$r_fiel\ds_1.mscp$v_sc_eot#define mscp$v_sc_inrep mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_succ.mscp$r_bit_fields.mscp$r_fi\eld_2.mscp$v_sc_inrep#define mscp$v_sc_ivrct mscp$r_modifiers_status.mscp$r_flags_status.mscp);$r_mscp_subcodes.mscp$r_sc_succ.mscp$r_bit_fields.mscp$r_fi\eld_2.mscp$v_sc_ivrct#define mscp$v_sc_rdony mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_succ.mscp$r_bit_fields.mscp$r_fi\eld_2.mscp$v_sc_rdonyx#define mscp$v_sc_novol mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_offln.mscp$v_sc_novolx#define mscp$v_sc_inopr mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_offln.mscp$v_sc_inoprx#define mscp$v_sc_*;udsbl mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_offln.mscp$v_sc_udsblx#define mscp$v_sc_exuse mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_offln.mscp$v_sc_exuset#define mscp$v_sc_ldr mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_offln.mscp$v_sc_ldrx#define mscp$v_sc_cpyip mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_avlbl.mscp$v_sc_cpyipx#define mscp$v_sc_nomem mscp$r_modifiers+;_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_avlbl.mscp$v_sc_nomemx#define mscp$v_sc_aluse mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_avlbl.mscp$v_sc_alusex#define mscp$v_sc_datal mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_wrtpr.mscp$v_sc_datalx#define mscp$v_sc_softw mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_wrtpr.mscp$v_sc_softwx#define mscp$v_sc_hardw mscp$r_modifiers_status.mscp$r_fla,;gs_status.mscp$r_mscp_subcodes.mscp$r_sc_wrtpr.mscp$v_sc_hardw#define mscp$v_sc_allof mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_wheae.mscp$r_fields.mscp$v_sc_al\lof#define mscp$v_sc_tabfu mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_wheae.mscp$r_fields.mscp$v_sc_ta\bfu#define mscp$v_sc_noent mscp$r_modifiers_status.mscp$r_flags_status.mscp$r_mscp_subcodes.mscp$r_sc_wheae.mscp$r_fields.mscp$v_sc_no\ent"#endif /* #if !define -;d(__VAXC) */ N#define MSCP$K_OP_ABORT 1 /* Abort */N#define MSCP$K_OP_ACCES 16 /* Access */N#define MSCP$K_OP_ACCNM 5 /* Access non-volatile memory */N#define MSCP$K_OP_AVAIL 8 /* Available */N#define MSCP$K_OP_CMPCD 17 /* Compare Controller Data */N#define MSCP$K_OP_COMP 32 /* Compare Host Data */N#define .;MSCP$K_OP_COMP64 36 /* Compare Host Data (64 bit LBN) */N#define MSCP$K_OP_DSPLY 6 /* Display */N#define MSCP$K_OP_DTACP 11 /* Determine Access Paths */N#define MSCP$K_OP_DCD 13 /* Disk Copy Data */N#define MSCP$K_OP_ERASE 18 /* Erase */N#define MSCP$K_OP_ERASE64 23 /* Erase (64 bit LBN) */N#define MSCP$K_OP_ERGAP 22 /; /* Erase Gap (tapes only) */N#define MSCP$K_OP_FLUSH 19 /* Flush */N#define MSCP$K_OP_FMT 24 /* Format (as in floppy disks) */N#define MSCP$K_OP_GTCMD 2 /* Get Command Status */N#define MSCP$K_OP_GTUNM 7 /* Get Unit Name */N#define MSCP$K_OP_GTUNT 3 /* Get Unit Status */N#define MSCP$K_OP_GTLDR 7 /* Get Loader Status0; */N#define MSCP$K_OP_MOVE 12 /* Move Media */N#define MSCP$K_OP_ONLIN 9 /* Online */X#define MSCP$K_OP_RCEDC 35 /* Read Controller Encryption/Decryption Code */N#define MSCP$K_OP_READ 33 /* Read */N#define MSCP$K_OP_READ64 37 /* Read (64 bit LBN) */N#define MSCP$K_OP_REPLC 20 /* Replace 1;*/N#define MSCP$K_OP_REPOS 37 /* Reposition (tapes only) */N#define MSCP$K_OP_STCON 4 /* Set Controller Characteristics */N#define MSCP$K_OP_STUNT 10 /* Set Unit Characteristics */V#define MSCP$K_OP_TERCO 48 /* Terminate Class Driver/Server Connection */N#define MSCP$K_OP_WRITE 34 /* Write */N#define MSCP$K_OP_WRITE64 38 /* Write (64 bit LBN) */N#define MSCP$K2;_OP_WRITM 36 /* Write Tape Mark */N#define MSCP$K_OP_WRHIM 25 /* Write History Management */N/* MSCP End Message Codes */N#define MSCP$K_OP_END 128 /* End Message Flag */N/* MSCP Attention Message Codes (listed in alphabetical order) */N#define MSCP$K_OP_ACPTH 66 /* Access Path */N#define MSCP$K_OP_AVATN 64 3;/* Available */N#define MSCP$K_OP_DUPUN 65 /* Duplicate Unit Number */#define MSCP$M_SLUN 0x4000]#define MSCP$K_SLUN_RSVP 32767 /* SLUN to request unit number for this controller */ typedef struct _generic_mscp {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt;N/* MSCP Command Operation Codes (defined in alphabetical order) */ __struct {) unsigned mscp$v_slun_unused : 14;N unsigned mscp$v_slun : 1; 4;/* Server Local Unit Number flag */% unsigned mscp$v_fill_26_ : 1; } mscp$r_slun_unit_bit; } GENERIC_MSCP; #if !defined(__VAXC)4#define mscp$v_slun mscp$r_slun_unit_bit.mscp$v_slun"#endif /* #if !defined(__VAXC) */ N/* Aggregates MSCP_MODIFIERS and MSCP_SUBCODES have been */N/* incorporated into the GENERIC_MSCP aggregate. */N/* Definitions for MSCP Transfer Commands */N/* 5; */N/* Also the FORMAT command, which includes a */N/* buffer descriptor just like transfer commands. */I#define MSCP$K_FMT_DFLT 0 /* device's default */I#define MSCP$K_FMT_SING 1 /* single density */I#define MSCP$K_FMT_DOUB 2 /* double density */I#define MSCP$K_FMT_RX33 282 /* RX33 6;- ISO DIS8630-1985 */ #typedef struct _transfer_commands {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt;N unsigned int mscp$l_byte_cnt; /* Byte count */N unsigned char mscp$b_buffer [12]; /* Buffer descriptor */ __union { __struct { __union {, unsigned __int64 mscp$q_lbn; __struct { __union {N unsigned int mscp$l_lbn; /* Logical 7;block number */N unsigned int mscp$l_frst_bad; /* First bad block */N unsigned int mscp$l_fmt_func; /* Format function */. } mscp$r_lbn_longword;& } mscp$r_fill_28_;" } mscp$r_fill_27_; } mscp$r_disk; __struct {N unsigned int mscp$l_position; /* Position (object count) */N unsigned int mscp$l_taperec; /* Tape record byte count 8; */ } mscp$r_tape; } mscp$r_disk_tape; } TRANSFER_COMMANDS; #if !defined(__VAXC)J#define mscp$q_lbn mscp$r_disk_tape.mscp$r_disk.mscp$r_fill_27_.mscp$q_lbnn#define mscp$l_lbn mscp$r_disk_tape.mscp$r_disk.mscp$r_fill_27_.mscp$r_fill_28_.mscp$r_lbn_longword.mscp$l_lbnx#define mscp$l_frst_bad mscp$r_disk_tape.mscp$r_disk.mscp$r_fill_27_.mscp$r_fill_28_.mscp$r_lbn_longword.mscp$l_frst_badx#define mscp$l_fmt_func mscp$r_disk_tape.mscp$r_disk.mscp$r_fill_27_.mscp$r_fill 9;_28_.mscp$r_lbn_longword.mscp$l_fmt_funcD#define mscp$l_position mscp$r_disk_tape.mscp$r_tape.mscp$l_positionB#define mscp$l_taperec mscp$r_disk_tape.mscp$r_tape.mscp$l_taperec"#endif /* #if !defined(__VAXC) */ N/* Definitions for Abort and Get Command Status Commands and End Messages */ typedef struct _abort_gtcmd {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt;N unsigned int mscp$l_out_ref; /* Outstanding reference number */N unsigned int mscp$l_cmd_sts; /* Com :;mand status */ } ABORT_GTCMD;N/* Definitions for the Access Non-Volatile Memory Command and End Message */#define MSCP$K_ANM_READ 0#define MSCP$K_ANM_EXCG 1#define MSCP$K_ANM_TSST 2 typedef struct _accnm {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt;N unsigned int mscp$l_anm_size; /* Non-Volatile Memory Size */N unsigned int mscp$l_anm_offs; /* Offset into Non-Volatile Memory */R unsigned short int mscp$w_anm_oper; /* Non-Volatil ;;e Memory Access Operation */N unsigned short int mscp$w_anm_dlgh; /* Data Length */N char mscp$t_anm_memd [32]; /* Memory Data */ } ACCNM;N/* Definitions for Display Command and End Message */ typedef struct _display_cmd {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt;N unsigned short int mscp$w_ditem; /* Item code */N unsigned short int mscp$w_dmode; /* Mode <; */N char mscp$t_dtext [16]; /* Display text */ } DISPLAY_CMD;N/* Definitions for the Get Unit Status Command and End Message */#define MSCP$M_UF_CMPRD 0x1#define MSCP$M_UF_CMPWR 0x2#define MSCP$M_UF_WBKNV 0x40#define MSCP$M_UF_WRTPD 0x100#define MSCP$M_UF_EXACC 0x400#define MSCP$M_UF_SCCHH 0x800#define MSCP$M_UF_WRTPS 0x1000#define MSCP$M_UF_WRTPH 0x2000#define MSCP$M_UF_576 0x4#define MSCP$M_UF_WHL 0x8#d=;efine MSCP$M_UF_64LBN 0x10#define MSCP$M_UF_RMVBL 0x80#define MSCP$M_UF_SSMST 0x200#define MSCP$M_UF_SSMEM 0x4000#define MSCP$M_UF_REPLC 0x8000#define MSCP$M_UF_CACFL 0x4#define MSCP$M_UF_EWRER 0x8#define MSCP$M_UF_VARSP 0x10#define MSCP$M_UF_VSMSU 0x20#define MSCP$M_UF_LOADR 0x200#define MSCP$M_UF_CACH 0x8000#define MSCP$M_MTD_ENH 0x1#define MSCP$M_COMP_SUP 0x2#define MSCP$M_COMP_ENA 0x4#define MSCP$M_SLUN_C 0x1F#define MSCP$M_SLUN_D1 0x3E0#define MSCP$M_SLUN_D0>; 0x7C00#define MSCP$M_MTYP_N 0x7F#define MSCP$M_MTYP_A2 0xF80#define MSCP$M_MTYP_A1 0x1F000#define MSCP$M_MTYP_A0 0x3E0000 #define MSCP$M_MTYP_D1 0x7C00000!#define MSCP$M_MTYP_D0 0xF8000000#define MSCP$K_CM_NOCPY 0#define MSCP$K_CM_COPY 1#define MSCP$K_CM_MGCPY 2#define MSCP$K_CM_MMRG 3#define MSCP$K_CM_HB_MMRG 4#define MSCP$M_TF_800 0x1#define MSCP$M_TF_PE 0x2#define MSCP$M_TF_GCR 0x4#define MSCP$M_TF_BLK 0x8#define MSCP$M_TF_NOR 0x1#define MSCP$M_TF_BHD 0x2?;#define MSCP$M_TF_DN2 0x4#define MSCP$M_TF_DN3 0x8#define MSCP$M_TF_T87 0x10#define MSCP$M_TF_T87C 0x20#define MSCP$M_TF_ENH 0x2#define MSCP$M_TF_NDC 0x4#define MSCP$M_TF_EDC 0x8#define MSCP$M_TF_DCP 0x2#define MSCP$M_TF_X82 0x1#define MSCP$M_TF_X85 0x2#define MSCP$M_TF_X5C 0x4#define MSCP$K_TC_OLD 0#define MSCP$K_TC_9TR 256#define MSCP$K_TC_CTP 512#define MSCP$K_TC_HPC 768#define MSCP$K_TC_WOD 1024#define MSCP$K_TC_DAT 1280#define MSCP$K_TC_8MM 1536 @;#define MSCP$K_TC_QIC 1792N#define MSCP$M_TF_MASK 255 /* Density field mask */N#define MSCP$K_TF_CODE 256 /* Format code multiplier */]#define MSCP$S_ONLIN_STUNT 52 /* DISK_TAPE was previously contained in aggregate */N/* ONLIN_STUNT. Although,the aggregate was deleted, */ typedef struct _gtunt {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt;N unsigned short int mscp$w_mult_unt; /* Multi-unit code A; */ __union {N unsigned short int mscp$w_unt_flgs; /* Unit flags */ __struct {N unsigned mscp$v_uf_cmprd : 1; /* Compare reads */N unsigned mscp$v_uf_cmpwr : 1; /* Compare writes */' unsigned mscp$v_fill_1 : 4;X unsigned mscp$v_uf_wbknv : 1; /* Write-back (non-volatile) [disks only] */' unsigned mscp$v_fill_2 : 1;N unsigned mscp$v_uf_wrtpd : 1; B;/* Write protect (data safety) */' unsigned mscp$v_fill_3 : 1;N unsigned mscp$v_uf_exacc : 1; /* Exclusive access */P unsigned mscp$v_uf_scchh : 1; /* Suppress caching (High speed) */N unsigned mscp$v_uf_wrtps : 1; /* Write protect (software) */N unsigned mscp$v_uf_wrtph : 1; /* Write protect (hardware) */) unsigned mscp$v_fill_49_ : 2;# } mscp$r_unt_flgs_both; __struct {'C; unsigned mscp$v_fill_4 : 2;N unsigned mscp$v_uf_576 : 1; /* 576 byte sectors */N unsigned mscp$v_uf_whl : 1; /* Write History Logging Support */N unsigned mscp$v_uf_64lbn : 1; /* 64 bit LBN disk (>2TB) */' unsigned mscp$v_fill_5 : 2;N unsigned mscp$v_uf_rmvbl : 1; /* Removeable media */' unsigned mscp$v_fill_6 : 1;N unsigned mscp$v_uf_ssmst : 1; /* Shadow set ma D;ster */' unsigned mscp$v_fill_7 : 4;N unsigned mscp$v_uf_ssmem : 1; /* Shadow set member */\ unsigned mscp$v_uf_replc : 1; /* Controller initiated bad block replacement */# } mscp$r_unt_flgs_disk; __struct {' unsigned mscp$v_fill_8 : 2;N unsigned mscp$v_uf_cacfl : 1; /* Cache flushed */O unsigned mscp$v_uf_ewrer : 1; /* Enhanced Write Error Recovery */N E; unsigned mscp$v_uf_varsp : 1; /* Variable speed unit */Q unsigned mscp$v_uf_vsmsu : 1; /* Variable speed mode suppression */' unsigned mscp$v_fill_9 : 3;N unsigned mscp$v_uf_loadr : 1; /* Media Loader Present */( unsigned mscp$v_fill_10 : 5;N unsigned mscp$v_uf_cach : 1; /* Write-back Caching */# } mscp$r_unt_flgs_tape;" } mscp$r_unt_flgs_overlay; __union {N unsign F;ed short int mscp$w_tape_char; /* Propagate Tape unit chars. */ __struct {T unsigned mscp$v_mtd_enh : 1; /* VMS-TMSCP SERVER MTD ENHANCED (V7.2) */N unsigned mscp$v_comp_sup : 1; /* Tape unit supports compaction */N unsigned mscp$v_comp_ena : 1; /* Compaction enabled/disabled */) unsigned mscp$v_fill_50_ : 5; } mscp$r_fill_30_; } mscp$r_fill_29_; short int mscp$w_reserved; __union { __union {N G; unsigned __int64 mscp$q_unit_id; /* Unit identifier */ __struct {T void *mscp$l_excl_lba; /* Excluded LBN area address [disks only] */Y unsigned int mscp$l_excl_lbc; /* Excluded LBN block count [disks only] */" } mscp$r_fill_32_; } mscp$r_fill_31_; __union {( __int64 mscp$q_slun_overlay; __struct {1 unsigned int mscp$l_slun_allocls;4 H; unsigned short int mscp$w_slun_unit; __union {; unsigned short int mscp$w_slun_devname; __struct {3 unsigned mscp$v_slun_c : 5;4 unsigned mscp$v_slun_d1 : 5;4 unsigned mscp$v_slun_d0 : 5;5 unsigned mscp$v_reserved : 1;* } mscp$r_fill_36_;& } mscp$r_fill_35_;" } mscp$r_fill_34_; I; } mscp$r_fill_33_;! } mscp$r_unit_id_overlay; __union {N unsigned int mscp$l_dev_parm; /* Device dependent parameters */ __union {N unsigned int mscp$l_media_id; /* Media type identifier */ __struct {N unsigned mscp$v_mtyp_n : 7; /* Media # (i.e. 7 of RK07) */N unsigned mscp$v_mtyp_a2 : 5; /* Media name char. */N unsigned mscp$v_mtyp_a1 : 5; /* Media name J; continued */N unsigned mscp$v_mtyp_a0 : 5; /* " " " */N unsigned mscp$v_mtyp_d1 : 5; /* Dev mnemonic char. */N unsigned mscp$v_mtyp_d0 : 5; /* Mnemonic continued */" } mscp$r_fill_38_; } mscp$r_fill_37_;" } mscp$r_dev_parm_overlay; __union { __union { __struct {N unsigned short int mscp$w_shdw_unt; /* Shadow unit */ K; __union {N unsigned short int mscp$w_copy_mod; /* Copy mode */P unsigned short int mscp$w_shdw_sts; /* Shadow unit status */% } mscp$r_spd_sts;" } mscp$r_disk_cmd;N unsigned int mscp$l_dmaxbcnt; /* Unit MAXBCNT */$ } mscp$r_disk_shdw_bcnt; __struct { __union { __union {Q unsigned short int mscp$w_fo L;rmat; /* Original (Old) format */ __struct {N unsigned mscp$v_tf_800 : 1; /* NRZI 800 bpi */P unsigned mscp$v_tf_pe : 1; /* Phase encoded 1600 bpi */X unsigned mscp$v_tf_gcr : 1; /* Group code recording 6250 bpi */N unsigned mscp$v_tf_blk : 1; /* Block format (TK50) */5 unsigned mscp$v_fill_51_ : 4;* } mscp$r_fill_40_;& M; } mscp$r_fill_39_; __union {c unsigned short int mscp$w_format_ctp; /* Block mode format (Cartridge Tapes) */ __struct {^ unsigned mscp$v_tf_nor : 1; /* Normal (low) density (833 bpi TK50) */b unsigned mscp$v_tf_bhd : 1; /* Block mode High Density (1250 bpi TK70) */a unsigned mscp$v_tf_dn2 : 1; /* Block mode Density 2 (TF85 compatible) */a N; unsigned mscp$v_tf_dn3 : 1; /* Block mode Density 3 (TF86 compatible) */N unsigned mscp$v_tf_t87 : 1; /* Tx87 compatible */V unsigned mscp$v_tf_t87c : 1; /* Tx87 compatible compressed */5 unsigned mscp$v_fill_52_ : 2;* } mscp$r_fill_42_;& } mscp$r_fill_41_; __union {a unsigned short int mscp$w_format_hpc; /* High Performance Ca O;rtridge format */ __struct {Q unsigned mscp$v_fill_10 : 1; /* TF_NOR already defined */N unsigned mscp$v_tf_enh : 1; /* Enhanced density */N unsigned mscp$v_tf_ndc : 1; /* NOR with data comp. */N unsigned mscp$v_tf_edc : 1; /* ENH with data comp. */5 unsigned mscp$v_fill_53_ : 4;* } mscp$r_fill_44_;& } mscp$r P;_fill_43_; __union {T unsigned short int mscp$w_format_dat; /* DAT cartridge format */ __struct {Q unsigned mscp$v_fill_11 : 1; /* TF_NOR already defined */O unsigned mscp$v_tf_dcp : 1; /* DAT compacted density */5 unsigned mscp$v_fill_54_ : 6;* } mscp$r_fill_46_;& } mscp$r_fill_45_; __union {T Q; unsigned short int mscp$w_format_8mm; /* 8MM cartridge format */ __struct {Z unsigned mscp$v_tf_x82 : 1; /* EXABYTE-8200 Compatible Density */Z unsigned mscp$v_tf_x85 : 1; /* EXABYTE-8500 Compatible Density */Y unsigned mscp$v_tf_x5c : 1; /* EXABYTE-8500 Compacted Density */5 unsigned mscp$v_fill_55_ : 5;* } mscp$r_fill_48_;& } R;mscp$r_fill_47_;( } mscp$r_format_overlay;N unsigned short int mscp$w_speed; /* Speed */ } mscp$r_tape_cmd; } mscp$r_disk_tape_cmd; __union { __union { __struct {N unsigned short int mscp$w_track; /* Track size */N unsigned short int mscp$w_group; /* Group size */N unsigned short int mscp$w_cylinder; /* Cylinder size */S;N unsigned char mscp$b_unit_svr; /* Unit software version */N unsigned char mscp$b_unit_hvr; /* Unit hardware version */N unsigned short int mscp$w_rct_size; /* RCT size */N unsigned char mscp$b_rbns; /* RBNs per track */N unsigned char mscp$b_rct_cpys; /* Number of RCT copies */q unsigned short int mscp$w_load_avail; /* Controller load available (VMS server load bala T;ncing) */" } mscp$r_disk_end; __struct {N unsigned short int mscp$w_formenu; /* Format menu */N unsigned char mscp$b_freecap; /* Free capacity */" } mscp$r_tape_end;# } mscp$r_disk_tape_end;R/* Definitions for Online and Set Unit Characteristics Command and End Messages */ __union { __struct {N unsigned int mscp$l_unt_size; /* Unit size U; */N unsigned int mscp$l_vol_ser; /* Volume serial number */N unsigned __int64 mscp$q_maxblock_64; /* 64 bit Unit Size */ } mscp$r_disk; __struct {N unsigned int mscp$l_maxwtrec; /* Maximum write record size */N unsigned short int mscp$w_noiserec; /* Noise record */ } mscp$r_tape; } mscp$r_disk_tape;N/* we still have to generate the size field. V; */ } mscp$r_online_stunt; } GTUNT; #if !defined(__VAXC)?#define mscp$w_unt_flgs mscp$r_unt_flgs_overlay.mscp$w_unt_flgsT#define mscp$v_uf_cmprd mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_both.mscp$v_uf_cmprdT#define mscp$v_uf_cmpwr mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_both.mscp$v_uf_cmpwrT#define mscp$v_uf_wbknv mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_both.mscp$v_uf_wbknvT#define mscp$v_uf_wrtpd mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_both.mscp$v_uf_wW;rtpdT#define mscp$v_uf_exacc mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_both.mscp$v_uf_exaccT#define mscp$v_uf_scchh mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_both.mscp$v_uf_scchhT#define mscp$v_uf_wrtps mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_both.mscp$v_uf_wrtpsT#define mscp$v_uf_wrtph mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_both.mscp$v_uf_wrtphP#define mscp$v_uf_576 mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_disk.mscp$v_uf_576P#define mscp$v_uf_whl mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_disk.mscp$v_X;uf_whlT#define mscp$v_uf_64lbn mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_disk.mscp$v_uf_64lbnT#define mscp$v_uf_rmvbl mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_disk.mscp$v_uf_rmvblT#define mscp$v_uf_ssmst mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_disk.mscp$v_uf_ssmstT#define mscp$v_uf_ssmem mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_disk.mscp$v_uf_ssmemT#define mscp$v_uf_replc mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_disk.mscp$v_uf_replcT#define mscp$v_uf_cacfl mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_tapeY;.mscp$v_uf_cacflT#define mscp$v_uf_ewrer mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_tape.mscp$v_uf_ewrerT#define mscp$v_uf_varsp mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_tape.mscp$v_uf_varspT#define mscp$v_uf_vsmsu mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_tape.mscp$v_uf_vsmsuT#define mscp$v_uf_loadr mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_tape.mscp$v_uf_loadrR#define mscp$v_uf_cach mscp$r_unt_flgs_overlay.mscp$r_unt_flgs_tape.mscp$v_uf_cach9#define mscp$w_tape_char mscp$r_fill_29_.mscp$w_tape_charEZ;#define mscp$v_mtd_enh mscp$r_fill_29_.mscp$r_fill_30_.mscp$v_mtd_enhG#define mscp$v_comp_sup mscp$r_fill_29_.mscp$r_fill_30_.mscp$v_comp_supG#define mscp$v_comp_ena mscp$r_fill_29_.mscp$r_fill_30_.mscp$v_comp_enaL#define mscp$q_unit_id mscp$r_unit_id_overlay.mscp$r_fill_31_.mscp$q_unit_id^#define mscp$l_excl_lba mscp$r_unit_id_overlay.mscp$r_fill_31_.mscp$r_fill_32_.mscp$l_excl_lba^#define mscp$l_excl_lbc mscp$r_unit_id_overlay.mscp$r_fill_31_.mscp$r_fill_32_.mscp$l_excl_lbcf#define mscp$l_s[;lun_allocls mscp$r_unit_id_overlay.mscp$r_fill_33_.mscp$r_fill_34_.mscp$l_slun_allocls`#define mscp$w_slun_unit mscp$r_unit_id_overlay.mscp$r_fill_33_.mscp$r_fill_34_.mscp$w_slun_unitv#define mscp$w_slun_devname mscp$r_unit_id_overlay.mscp$r_fill_33_.mscp$r_fill_34_.mscp$r_fill_35_.mscp$w_slun_devnamez#define mscp$v_slun_c mscp$r_unit_id_overlay.mscp$r_fill_33_.mscp$r_fill_34_.mscp$r_fill_35_.mscp$r_fill_36_.mscp$v_slun_c|#define mscp$v_slun_d1 mscp$r_unit_id_overlay.mscp$r_fill_33_.mscp$r_fill_34\;_.mscp$r_fill_35_.mscp$r_fill_36_.mscp$v_slun_d1|#define mscp$v_slun_d0 mscp$r_unit_id_overlay.mscp$r_fill_33_.mscp$r_fill_34_.mscp$r_fill_35_.mscp$r_fill_36_.mscp$v_slun_d0?#define mscp$l_dev_parm mscp$r_dev_parm_overlay.mscp$l_dev_parmO#define mscp$l_media_id mscp$r_dev_parm_overlay.mscp$r_fill_37_.mscp$l_media_id[#define mscp$v_mtyp_n mscp$r_dev_parm_overlay.mscp$r_fill_37_.mscp$r_fill_38_.mscp$v_mtyp_n]#define mscp$v_mtyp_a2 mscp$r_dev_parm_overlay.mscp$r_fill_37_.mscp$r_fill_38_.mscp$v_mt];yp_a2]#define mscp$v_mtyp_a1 mscp$r_dev_parm_overlay.mscp$r_fill_37_.mscp$r_fill_38_.mscp$v_mtyp_a1]#define mscp$v_mtyp_a0 mscp$r_dev_parm_overlay.mscp$r_fill_37_.mscp$r_fill_38_.mscp$v_mtyp_a0]#define mscp$v_mtyp_d1 mscp$r_dev_parm_overlay.mscp$r_fill_37_.mscp$r_fill_38_.mscp$v_mtyp_d1]#define mscp$v_mtyp_d0 mscp$r_dev_parm_overlay.mscp$r_fill_37_.mscp$r_fill_38_.mscp$v_mtyp_d0b#define mscp$w_shdw_unt mscp$r_disk_tape_cmd.mscp$r_disk_shdw_bcnt.mscp$r_disk_cmd.mscp$w_shdw_untq#define mscp$w^;_copy_mod mscp$r_disk_tape_cmd.mscp$r_disk_shdw_bcnt.mscp$r_disk_cmd.mscp$r_spd_sts.mscp$w_copy_modq#define mscp$w_shdw_sts mscp$r_disk_tape_cmd.mscp$r_disk_shdw_bcnt.mscp$r_disk_cmd.mscp$r_spd_sts.mscp$w_shdw_stsR#define mscp$l_dmaxbcnt mscp$r_disk_tape_cmd.mscp$r_disk_shdw_bcnt.mscp$l_dmaxbcntn#define mscp$w_format mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_39_.mscp$w_format~#define mscp$v_tf_800 mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_;_39_.mscp$r_fill_40_.mscp$v_tf_800|#define mscp$v_tf_pe mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_39_.mscp$r_fill_40_.mscp$v_tf_pe~#define mscp$v_tf_gcr mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_39_.mscp$r_fill_40_.mscp$v_tf_gcr~#define mscp$v_tf_blk mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_39_.mscp$r_fill_40_.mscp$v_tf_blk~#define mscp$v_tf_nor mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_`;fill_41_.mscp$r_fill_42_.mscp$v_tf_nor~#define mscp$v_tf_bhd mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_41_.mscp$r_fill_42_.mscp$v_tf_bhd~#define mscp$v_tf_dn2 mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_41_.mscp$r_fill_42_.mscp$v_tf_dn2~#define mscp$v_tf_dn3 mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_41_.mscp$r_fill_42_.mscp$v_tf_dn3~#define mscp$v_tf_t87 mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.ma;scp$r_fill_41_.mscp$r_fill_42_.mscp$v_tf_t87#define mscp$v_tf_t87c mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_41_.mscp$r_fill_42_.mscp$v_tf_t87c~#define mscp$v_tf_enh mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_43_.mscp$r_fill_44_.mscp$v_tf_enh~#define mscp$v_tf_ndc mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_43_.mscp$r_fill_44_.mscp$v_tf_ndc~#define mscp$v_tf_edc mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_ob;verlay.mscp$r_fill_43_.mscp$r_fill_44_.mscp$v_tf_edc~#define mscp$v_tf_dcp mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_45_.mscp$r_fill_46_.mscp$v_tf_dcp~#define mscp$v_tf_x82 mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_47_.mscp$r_fill_48_.mscp$v_tf_x82~#define mscp$v_tf_x85 mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_format_overlay.mscp$r_fill_47_.mscp$r_fill_48_.mscp$v_tf_x85~#define mscp$v_tf_x5c mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$r_foc;rmat_overlay.mscp$r_fill_47_.mscp$r_fill_48_.mscp$v_tf_x5cF#define mscp$w_speed mscp$r_disk_tape_cmd.mscp$r_tape_cmd.mscp$w_speedZ#define mscp$w_track mscp$r_online_stunt.mscp$r_disk_tape_end.mscp$r_disk_end.mscp$w_trackZ#define mscp$w_group mscp$r_online_stunt.mscp$r_disk_tape_end.mscp$r_disk_end.mscp$w_group`#define mscp$w_cylinder mscp$r_online_stunt.mscp$r_disk_tape_end.mscp$r_disk_end.mscp$w_cylinder`#define mscp$b_unit_svr mscp$r_online_stunt.mscp$r_disk_tape_end.mscp$r_disk_end.mscp$b_unitd;_svr`#define mscp$b_unit_hvr mscp$r_online_stunt.mscp$r_disk_tape_end.mscp$r_disk_end.mscp$b_unit_hvr`#define mscp$w_rct_size mscp$r_online_stunt.mscp$r_disk_tape_end.mscp$r_disk_end.mscp$w_rct_sizeX#define mscp$b_rbns mscp$r_online_stunt.mscp$r_disk_tape_end.mscp$r_disk_end.mscp$b_rbns`#define mscp$b_rct_cpys mscp$r_online_stunt.mscp$r_disk_tape_end.mscp$r_disk_end.mscp$b_rct_cpysd#define mscp$w_load_avail mscp$r_online_stunt.mscp$r_disk_tape_end.mscp$r_disk_end.mscp$w_load_avail^#define mscp$we;_formenu mscp$r_online_stunt.mscp$r_disk_tape_end.mscp$r_tape_end.mscp$w_formenu^#define mscp$b_freecap mscp$r_online_stunt.mscp$r_disk_tape_end.mscp$r_tape_end.mscp$b_freecapX#define mscp$l_unt_size mscp$r_online_stunt.mscp$r_disk_tape.mscp$r_disk.mscp$l_unt_sizeV#define mscp$l_vol_ser mscp$r_online_stunt.mscp$r_disk_tape.mscp$r_disk.mscp$l_vol_ser^#define mscp$q_maxblock_64 mscp$r_online_stunt.mscp$r_disk_tape.mscp$r_disk.mscp$q_maxblock_64X#define mscp$l_maxwtrec mscp$r_online_stunt.mscp$r_dis f;k_tape.mscp$r_tape.mscp$l_maxwtrecX#define mscp$w_noiserec mscp$r_online_stunt.mscp$r_disk_tape.mscp$r_tape.mscp$w_noiserec"#endif /* #if !defined(__VAXC) */ V/* Definitions for the Read Controller Encrypt/Decrypt Code Command and End Message */ typedef struct _rcedc {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt; int mscp$l_filler [5];N unsigned int mscp$l_code; /* Encrypt/Decrypt Code Length */ } RCEDC;N/* Definitions for the Replace Command and End Message (g;disks only) */ typedef struct _replc {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt;N unsigned int mscp$l_rbn; /* Replacement block number */ } REPLC;N/* Definitions for the Reposition Command and End Message (tapes only) */ typedef struct _repos {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt; __union { __struct {N unsigned int mscp$l_rec_cnt; /* Record/Object count */N unsigned int mscp$l_tmgp_cnt; h;/* Tape mark count */ } mscp$r_cmd; __struct {N unsigned int mscp$l_rcskiped; /* Records skipped */N unsigned int mscp$l_tmskiped; /* Tape markes skipped */ } mscp$r_endmsg; } mscp$r_cmdend; } REPOS; #if !defined(__VAXC)>#define mscp$l_rec_cnt mscp$r_cmdend.mscp$r_cmd.mscp$l_rec_cnt@#define mscp$l_tmgp_cnt mscp$r_cmdend.mscp$r_cmd.mscp$l_tmgp_cntC#define mscp$l_rcskiped mscp$r_ci;mdend.mscp$r_endmsg.mscp$l_rcskipedC#define mscp$l_tmskiped mscp$r_cmdend.mscp$r_endmsg.mscp$l_tmskiped"#endif /* #if !defined(__VAXC) */ P/* Definitions for the Set Controller Characteristics Command and End Message */#define MSCP$M_CF_576 0x1#define MSCP$M_CF_SHADW 0x2#define MSCP$M_CF_MLTHS 0x4#define MSCP$M_CF_LDCD 0x8#define MSCP$M_CF_THIS 0x10#define MSCP$M_CF_OTHER 0x20#define MSCP$M_CF_MISC 0x40#define MSCP$M_CF_ATTN 0x80#define MSCP$M_CF_RDCD 0x100#define MSj;CP$M_CF_WHL 0x200#define MSCP$M_CF_RDO 0x400#define MSCP$M_CF_NFESC 0x800#define MSCP$M_CF_64LBN 0x1000#define MSCP$M_CF_LOAD 0x2000#define MSCP$M_CF_EDCRP 0x4000#define MSCP$M_CF_REPLC 0x8000#define MSCP$M_CF_MTDEN 0x4000#define MSCP$M_CF_SRT 0x8000#define MSCP$K_CL_CNTRL 1#define MSCP$K_CL_DISK 2#define MSCP$K_CL_TAPE 3#define MSCP$K_CL_D144 4#define MSCP$K_CL_LDR 5N/* MSCP Controller Model */#define MSCP$K_CM_HSC5k;0 1#define MSCP$K_CM_UDA50 2#define MSCP$K_CM_RC25 3#define MSCP$K_CM_EMULA 4#define MSCP$K_CM_TU81 5#define MSCP$K_CM_UDA52 6#define MSCP$K_CM_UDA50A 6#define MSCP$K_CM_RDRX 7#define MSCP$K_CM_TOPS 8#define MSCP$K_CM_TK50 9#define MSCP$K_CM_TQK50 9#define MSCP$K_CM_RUX50 10#define MSCP$K_CM_AIO 12#define MSCP$K_CM_KFBTA 12#define MSCP$K_CM_KDA50 13#define MSCP$K_CM_TK70 14#define MSCP$K_CM_TQK70 14#define MSCP$K_CM_RV20 15#define MSCP$K_CM_RRD50 16#define l;MSCP$K_CM_RRD50Q 16#define MSCP$K_CM_KDB50 18#define MSCP$K_CM_RQDX3 19#define MSCP$K_CM_RQDX4 20#define MSCP$K_CM_DSSI_DISK 21#define MSCP$K_CM_DSSI_TAPE 22 #define MSCP$K_CM_DSSI_DSKTAP 23#define MSCP$K_CM_DSSI_OTHER 24#define MSCP$K_CM_TUK50 25#define MSCP$K_CM_RRD50U 26#define MSCP$K_CM_KDM70 27#define MSCP$K_CM_TQL70 28#define MSCP$K_CM_TM32 29#define MSCP$K_CM_HSC70 32#define MSCP$K_CM_HSC40 33#define MSCP$K_CM_HSC60 34#define MSCP$K_CM_HSC90 35#define MSCP$Km;_CM_RN20 36#define MSCP$K_CM_ENE10 37#define MSCP$K_CM_TN10 38#define MSCP$K_CM_HSJ40 40#define MSCP$K_CM_HSC65 41#define MSCP$K_CM_HSC95 42#define MSCP$K_CM_HSJ80 46#define MSCP$K_CM_KSB50 64#define MSCP$K_CM_TK50_DEBNT 65#define MSCP$K_CM_TBK70 66#define MSCP$K_CM_TBK7L 68#define MSCP$K_CM_RF30 96#define MSCP$K_CM_RF71 97#define MSCP$K_CM_TF85 98#define MSCP$K_CM_TF70 99#define MSCP$K_CM_RF31 100#define MSCP$K_CM_RF72 101#define MSCP$K_CM_RF73 102#define MSn;CP$K_CM_RF32 103#define MSCP$K_CM_RF35 104#define MSCP$K_CM_RF36 108#define MSCP$K_CM_RF74 109#define MSCP$K_CM_TF86 110#define MSCP$K_CM_HSD20 111#define MSCP$K_CM_RF75 112#define MSCP$K_CM_RF37 114#define MSCP$K_CM_HSX50 128#define MSCP$K_CM_ULTRIX 248#define MSCP$K_CM_SVS 249 typedef struct _stcon {N/* Allocation class (CNT_ALCS) is now part of union */N/* with UNIT structure in MSCP_BASIC_PKT */) MSCP_BAS o;IC_PKT mscp$r_mscp_basic_pkt;N unsigned short int mscp$w_version; /* MSCP version */ __union { __union {N unsigned short int mscp$w_cnt_flgs; /* Controller flags */ __struct {Q unsigned mscp$v_cf_576 : 1; /* 576 byte sectors [disks only] */N unsigned mscp$v_cf_shadw : 1; /* Shadowing [disks only] */N unsigned mscp$v_cf_mlths : 1; /* Multi-Host */N p; unsigned mscp$v_cf_ldcd : 1; /* Local Disk Copy Data */Q unsigned mscp$v_cf_this : 1; /* Enable this host's error log */S unsigned mscp$v_cf_other : 1; /* Enable other host's error log */S unsigned mscp$v_cf_misc : 1; /* Enable miscellaneous error log */N unsigned mscp$v_cf_attn : 1; /* Enable attention messages */N unsigned mscp$v_cf_rdcd : 1; /* Remote Disk Copy Data */Q unq;signed mscp$v_cf_whl : 1; /* Write History Logging Support */X unsigned mscp$v_cf_rdo : 1; /* Restricted DISK COPY DATA Operations */^ unsigned mscp$v_cf_nfesc : 1; /* Class driver supports NOFE state changes */\ unsigned mscp$v_cf_64lbn : 1; /* Class driver supports 64 bit disk LBNs */b unsigned mscp$v_cf_load : 1; /* Controller returns load available information */T unsigned mscp$v_cf_edcrp : 1; /* Data Encr r;ypt/Decrypt Supported */m unsigned mscp$v_cf_replc : 1; /* Controller Initiated Bad Block Replacement [disks only] */" } mscp$r_fill_57_; } mscp$r_fill_56_; __union {P unsigned short int mscp$w_tu_cnt_flgs; /* Tape controller flags */ __struct {, unsigned mscp$v_filler : 14;e unsigned mscp$v_cf_mtden : 1; /* Class driver supports MTD (multi tape density) */O unsign s;ed mscp$v_cf_srt : 1; /* Segemented Record Transfer */" } mscp$r_fill_59_; } mscp$r_fill_58_;" } mscp$r_cnt_flgs_overlay; __union {N unsigned short int mscp$w_hst_tmo; /* Host timeout */ __struct {N unsigned short int mscp$w_cnt_tmo; /* Controller timeout */ } mscp$r_fill_61_; } mscp$r_fill_60_;N unsigned char mscp$b_cnt_svr; /* Controller software version */N t;unsigned char mscp$b_cnt_hvr; /* Controller hardware version */ __union {N unsigned __int64 mscp$q_time; /* Quad-word date-time */ __struct {N unsigned __int64 mscp$q_cnt_id; /* Controller ID */ } mscp$r_fill_63_; } mscp$r_fill_62_;N unsigned int mscp$l_maxbcnt; /* Maximum supported byte count */N unsigned short int mscp$w_conn_ref; /* Connection reference number */N/* Controll u;er and Unit identifier Classes. (Device Class) */ } STCON; #if !defined(__VAXC)O#define mscp$w_cnt_flgs mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$w_cnt_flgs[#define mscp$v_cf_576 mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_576_#define mscp$v_cf_shadw mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_shadw_#define mscp$v_cf_mlths mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_mlths]#define mscp$v_cf_ldcd mscv;p$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_ldcd]#define mscp$v_cf_this mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_this_#define mscp$v_cf_other mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_other]#define mscp$v_cf_misc mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_misc]#define mscp$v_cf_attn mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_attn]#define mscp$v_cf_rdcd mscp$r_cnt_flgs_overlay.mscw;p$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_rdcd[#define mscp$v_cf_whl mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_whl[#define mscp$v_cf_rdo mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_rdo_#define mscp$v_cf_nfesc mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_nfesc_#define mscp$v_cf_64lbn mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_64lbn]#define mscp$v_cf_load mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_5x;7_.mscp$v_cf_load_#define mscp$v_cf_edcrp mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_edcrp_#define mscp$v_cf_replc mscp$r_cnt_flgs_overlay.mscp$r_fill_56_.mscp$r_fill_57_.mscp$v_cf_replc_#define mscp$v_cf_mtden mscp$r_cnt_flgs_overlay.mscp$r_fill_58_.mscp$r_fill_59_.mscp$v_cf_mtden[#define mscp$v_cf_srt mscp$r_cnt_flgs_overlay.mscp$r_fill_58_.mscp$r_fill_59_.mscp$v_cf_srt5#define mscp$w_hst_tmo mscp$r_fill_60_.mscp$w_hst_tmoE#define mscp$w_cnt_tmo mscp$r_fill_60_.msc y;p$r_fill_61_.mscp$w_cnt_tmo/#define mscp$q_time mscp$r_fill_62_.mscp$q_timeC#define mscp$q_cnt_id mscp$r_fill_62_.mscp$r_fill_63_.mscp$q_cnt_id"#endif /* #if !defined(__VAXC) */ N/* Definitions for Disk Data Copy Commands and End Messages */N#define MSCP$K_MIN_SIZ 12 /* Shortest Command */N#define MSCP$C_MIN_SIZ 12 /* Shortest Command */N#define MSCP$K_MXCMDLEN 36 /* Longest Command z;*/N#define MSCP$C_MXCMDLEN 36 /* Longest Command */N#define MSCP$K_DCDCMDLEN 60 /* DCD Command */N#define MSCP$C_DCDCMDLEN 60 /* DCD Command */N#define MSCP$K_LEN 52 /* Longest End Message */N#define MSCP$C_LEN 52 /* Longest End Message */ typedef struct _dcd {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt; __union { __stru{;ct {N unsigned int mscp$l_lbcount; /* Logical block count */N unsigned short int mscp$w_src_unum; /* Source unit number */N short int mscp$w_reserved; /* Reserved */N unsigned __int64 mscp$q_src_uid; /* Source unit identifier */N unsigned int mscp$l_dest_lbn; /* Destination LBN */N unsigned short int mscp$w_hrn; /* HRN or Entloc */N unsign |;ed short int mscp$w_ent_id; /* Entry ID */N int mscp$l_reserved; /* Reserved */N unsigned int mscp$l_src_lbn; /* Source LBN */X unsigned __int64 mscp$q_port_adr; /* Source unit's subsystem port address */Y unsigned __int64 mscp$q_sys_adr; /* Source unit's subsystem system address */' } mscp$r_lbcount_structure; __struct { int mscp$l_filler;N }; unsigned char mscp$z_sbc_sts [16]; /* Subcommand status */N unsigned short int mscp$w_ent_loc; /* Entry locator */+ } mscp$r_lbcount_end_structure;! } mscp$r_lbcount_overlay; } DCD; #if !defined(__VAXC)U#define mscp$l_lbcount mscp$r_lbcount_overlay.mscp$r_lbcount_structure.mscp$l_lbcountW#define mscp$w_src_unum mscp$r_lbcount_overlay.mscp$r_lbcount_structure.mscp$w_src_unumU#define mscp$q_src_uid mscp$r_lbcount_overlay.mscp$r_l~;bcount_structure.mscp$q_src_uidW#define mscp$l_dest_lbn mscp$r_lbcount_overlay.mscp$r_lbcount_structure.mscp$l_dest_lbnM#define mscp$w_hrn mscp$r_lbcount_overlay.mscp$r_lbcount_structure.mscp$w_hrnS#define mscp$w_ent_id mscp$r_lbcount_overlay.mscp$r_lbcount_structure.mscp$w_ent_idU#define mscp$l_src_lbn mscp$r_lbcount_overlay.mscp$r_lbcount_structure.mscp$l_src_lbnW#define mscp$q_port_adr mscp$r_lbcount_overlay.mscp$r_lbcount_structure.mscp$q_port_adrU#define mscp$q_sys_adr mscp$r_lbcount_ ;overlay.mscp$r_lbcount_structure.mscp$q_sys_adrY#define mscp$z_sbc_sts mscp$r_lbcount_overlay.mscp$r_lbcount_end_structure.mscp$z_sbc_stsY#define mscp$w_ent_loc mscp$r_lbcount_overlay.mscp$r_lbcount_end_structure.mscp$w_ent_loc"#endif /* #if !defined(__VAXC) */ N/* Definitions for Write History Management Commands and End Messages */#define MSCP$K_WHM_DALL 1#define MSCP$K_WHM_DHRN 2#define MSCP$K_WHM_DELO 3#define MSCP$K_WHM_RALL 4#define MSCP$K_WHM_RHRN 5#define MSCP ;$K_WHM_DAFC 6 typedef struct _wrhim {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt;N int mscp$l_reserved; /* Reserved */ __union {Q unsigned char mscp$b_wrhis_bd [12]; /* Write history buffer descriptor */ __struct {N unsigned short int mscp$w_unit_al; /* Unit allocated */N unsigned short int mscp$w_serv_al; /* Server allocated */N unsigned short int mscp$w_serv_unal; /* Se ;rver unallocated */' } mscp$r_unit_al_structure;" } mscp$r_wrhis_bd_overlay; __union {N unsigned short int mscp$w_oper; /* Operation */N unsigned short int mscp$w_count; /* Count */ } mscp$r_oper_overlay;N unsigned short int mscp$w_offset; /* Offset */ } WRHIM; #if !defined(__VAXC)?#define mscp$b_wrhis_bd mscp$r_wrhis_bd_overlay.mscp$b_wrhis_bdV#define ;mscp$w_unit_al mscp$r_wrhis_bd_overlay.mscp$r_unit_al_structure.mscp$w_unit_alV#define mscp$w_serv_al mscp$r_wrhis_bd_overlay.mscp$r_unit_al_structure.mscp$w_serv_alZ#define mscp$w_serv_unal mscp$r_wrhis_bd_overlay.mscp$r_unit_al_structure.mscp$w_serv_unal3#define mscp$w_oper mscp$r_oper_overlay.mscp$w_oper5#define mscp$w_count mscp$r_oper_overlay.mscp$w_count"#endif /* #if !defined(__VAXC) */ N/* Definitions for Write History Entry */#define WHIS$M_E ;T_TLIB 0x4000#define WHIS$M_ET_ERR 0x8000N#define WHIS$K_WRITELOGLEN 16 /* Write log length */N#define WHIS$C_WRITELOGLEN 16 /* */ !typedef struct _write_log_entry {N unsigned short int whis$w_elo; /* Entry Locator */N unsigned short int whis$w_unit; /* Unit Number */N unsigned int whis$l_length; /* Transfer Length */N unsigned int whi;s$l_lbn; /* Starting Logical Block Number */N unsigned short int whis$w_hrn; /* Host Reference Number */ __union {N unsigned short int whis$w_entflgs; /* Entry Flags */ __struct {( unsigned whis$v_filler : 14;( unsigned whis$v_et_tlib : 1;' unsigned whis$v_et_err : 1; } whis$r_fill_65_; } whis$r_fill_64_; } WRITE_LOG_ENTRY; #if !defined(__VAXC)5#define whis ;$w_entflgs whis$r_fill_64_.whis$w_entflgsE#define whis$v_et_tlib whis$r_fill_64_.whis$r_fill_65_.whis$v_et_tlibC#define whis$v_et_err whis$r_fill_64_.whis$r_fill_65_.whis$v_et_err"#endif /* #if !defined(__VAXC) */ N/* Definitions for GET UNIT NAME command and end message */ typedef struct _get_unit_name {) MSCP_BASIC_PKT mscp$r_mscp_basic_pkt;N unsigned int mscp$l_ddr_namelen; /* Length of dynamic name */N char mscp$t_ddr_name [28]; ; /* Dynamic name string */ } GET_UNIT_NAME; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MSCPDEF_LOADED */ ww`[UM/***************************************************************************/M/** ; **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** ; **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** ; **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */G/* Source: 07-JUN-1993 13:21:25 $1$DGA8345:[LIB_H.SRC]MSLGDEF.SDL;1 *//********************************************************************************************************************************//*** ; MODULE $MSLGDEF ***/#ifndef __MSLGDEF_LOADED#define __MSLGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif ;#ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ ;*/N/* MSLG, MScp error LoG message definitions */J/* These definitions describe the format of the error log messages */J/* generated by MSCP and TMSCP devices. */N/*- */N/* */I/* Generic MSCP/TMSCP error log entry format */N/* ; */#define MSLG$M_LF_SQNRS 0x1#define MSLG$M_LF_RPLER 0x10#define MSLG$M_LF_BBR 0x20#define MSLG$M_LF_CONT 0x40#define MSLG$M_LF_SUCC 0x80#define MSLG$K_CNT_ERR 0#define MSLG$K_BUS_ADDR 1#define MSLG$K_DISK_TRN 2#define MSLG$K_SDI 3#define MSLG$K_SML_DSK 4#define MSLG$K_TAPE_TRN 5#define MSLG$K_STI_ERR 6#define MSLG$K_STI_DEL 7#define MSLG$K_STI_FEL 8#define MSLG$K_REPLACE 9#define MSLG$K_LDR_ERR 10V#define MSLG$S_MSLG_CN ;T_ERR 23 /* Old size name for MSLG_CNT_ERR aggregate */Y#define MSLG$S_MSLG_BUS_ADDR 28 /* Old size name for MSLG_BUS_ADDR aggregate */#define MSLG$M_LFR_BR 0x400#define MSLG$M_LFR_RI 0x800#define MSLG$M_LFR_RF 0x1000#define MSLG$M_LFR_TE 0x2000#define MSLG$M_LFR_FE 0x4000#define MSLG$M_LFR_RP 0x8000W#define MSLG$S_MSLG_SML_DSK 41 /* Old size name for MSLG_SML_DSK aggregate. */ %typedef struct _generic_mscp_errlog {N unsigned int mslg$l_cmd_ref; ; /* Command reference number */N unsigned short int mslg$w_unit; /* Unit number */N unsigned short int mslg$w_seq_num; /* Sequence Number */N unsigned char mslg$b_format; /* Format */ __union {N unsigned char mslg$b_flags; /* Error Log Message Flags */ __struct {N unsigned mslg$v_lf_sqnrs : 1; /* Sequence Number Reset */' unsigned m ;slg$v_filler : 3;N unsigned mslg$v_lf_rpler : 1; /* Error during replacement */N unsigned mslg$v_lf_bbr : 1; /* Bad block replacement request */N unsigned mslg$v_lf_cont : 1; /* Operation continuing */N unsigned mslg$v_lf_succ : 1; /* Operation successful */ } mslg$r_fill_1_; } mslg$r_fill_0_;N unsigned short int mslg$w_event; /* Event Code */N unsigned __int64 mslg$;q_cnt_id; /* Controller ID */N unsigned char mslg$b_cnt_svr; /* Controller software version */N unsigned char mslg$b_cnt_hvr; /* Controller hardware version */ __union {N unsigned short int mslg$w_mult_unt; /* Multi-unit Code */^ char mslg$z_cnt_err; /* Controller dependent data - previously contained */N/* in MSLG_CNT_ERR aggregate */N/* Controller Error ;(MSLG$K_CNT_ERR) */" } mslg$r_mult_unt_overlay; __union {N unsigned __int64 mslg$q_unit_id; /* Unit ID */Y void *mslg$l_bus_addr; /* Host Memory Access Error (MSLG$K_BUS_ADDR) */N/* Bus Address - previously contained in */N/* MSLG_BUS_ADDR aggregate */! } mslg$r_unit_id_overlay;N unsigned char mslg$b_u ;nit_svr; /* Unit software version */N unsigned char mslg$b_unit_hvr; /* Unit hardware version */ __union { __struct {N unsigned char mslg$b_level; /* Level */N unsigned char mslg$b_retry; /* Retry */! } mslg$r_level_retry;c unsigned short int mslg$w_sde_cyl; /* Cylinder - used in MSLG_SML_DSK for MSLG$K_SML_DSK */ __union {m unsi;gned short int mslg$w_rpl_flgs; /* Replace Flags - used in MSLG_REPLACE for MSLG$K_REPLACE */ __struct {. unsigned mslg$v_bit_fill : 10;N unsigned mslg$v_lfr_br : 1; /* Bad RBN */N unsigned mslg$v_lfr_ri : 1; /* RCT inconsistent */N unsigned mslg$v_lfr_rf : 1; /* Reformat error */N unsigned mslg$v_lfr_te : 1; /* Tertiary revector */T ;unsigned mslg$v_lfr_fe : 1; /* Forced error (data not recovered) */W unsigned mslg$v_lfr_rp : 1; /* Replace attempted (block really bad) */! } mslg$r_fill_3_; } mslg$r_fill_2_; } mslg$r_fmt_dependent; __union { __struct { __union {O unsigned int mslg$l_vol_ser; /* Volume Serial Number (disks) */R unsigned int mslg$l_gap_cnt; /* Position - object count (tapes) */' ;} mslg$r_volser_gapcnt; __union { __struct {S unsigned char mslg$b_fmtr_svr; /* Formatter software version */S unsigned char mslg$b_fmtr_hvr; /* Formatter hardware version */. short int mslg$w_reserved;* } mslg$r_fmtr_version;b unsigned int mslg$l_hdr_code; /* Header Code - from MSLG_DISK_TRN aggregate for */B/* Disk Transfer Error (MSLG$K_DISK_TRN) ; */] unsigned int mslg$l_bad_lbn; /* Bad LBN - from MSLG_REPLACE aggregate for */B/* Bad Block Replacement Attempted (MSLG$K_REPLACE */c char mslg$z_sml_dsk; /* Controller or device dependent - used in MSLG_SML_DSK */) } mslg$r_version_overlay;$ } mslg$r_volser_version;N unsigned __int64 mslg$q_ml_id; /* Media loader identifier - */N/* used in MSLG_LDR_ERR for MSLG$K_LDR_ERR ; */# } mslg$r_media_ldr_overlay; } GENERIC_MSCP_ERRLOG; #if !defined(__VAXC)0#define mslg$b_flags mslg$r_fill_0_.mslg$b_flagsE#define mslg$v_lf_sqnrs mslg$r_fill_0_.mslg$r_fill_1_.mslg$v_lf_sqnrsE#define mslg$v_lf_rpler mslg$r_fill_0_.mslg$r_fill_1_.mslg$v_lf_rplerA#define mslg$v_lf_bbr mslg$r_fill_0_.mslg$r_fill_1_.mslg$v_lf_bbrC#define mslg$v_lf_cont mslg$r_fill_0_.mslg$r_fill_1_.mslg$v_lf_contC#define mslg$v_lf_succ mslg$r_fill_0_.mslg$r_fill_1_.mslg$v_lf_succ?#def;ine mslg$w_mult_unt mslg$r_mult_unt_overlay.mslg$w_mult_unt=#define mslg$z_cnt_err mslg$r_mult_unt_overlay.mslg$z_cnt_err<#define mslg$q_unit_id mslg$r_unit_id_overlay.mslg$q_unit_id>#define mslg$l_bus_addr mslg$r_unit_id_overlay.mslg$l_bus_addrI#define mslg$b_level mslg$r_fmt_dependent.mslg$r_level_retry.mslg$b_levelI#define mslg$b_retry mslg$r_fmt_dependent.mslg$r_level_retry.mslg$b_retry:#define mslg$w_sde_cyl mslg$r_fmt_dependent.mslg$w_sde_cylK#define mslg$w_rpl_flgs mslg$r_fmt_depende;nt.mslg$r_fill_2_.mslg$w_rpl_flgsV#define mslg$v_lfr_br mslg$r_fmt_dependent.mslg$r_fill_2_.mslg$r_fill_3_.mslg$v_lfr_brV#define mslg$v_lfr_ri mslg$r_fmt_dependent.mslg$r_fill_2_.mslg$r_fill_3_.mslg$v_lfr_riV#define mslg$v_lfr_rf mslg$r_fmt_dependent.mslg$r_fill_2_.mslg$r_fill_3_.mslg$v_lfr_rfV#define mslg$v_lfr_te mslg$r_fmt_dependent.mslg$r_fill_2_.mslg$r_fill_3_.mslg$v_lfr_teV#define mslg$v_lfr_fe mslg$r_fmt_dependent.mslg$r_fill_2_.mslg$r_fill_3_.mslg$v_lfr_feV#define mslg$v_lfr_rp mslg$r_f;mt_dependent.mslg$r_fill_2_.mslg$r_fill_3_.mslg$v_lfr_rpi#define mslg$l_vol_ser mslg$r_media_ldr_overlay.mslg$r_volser_version.mslg$r_volser_gapcnt.mslg$l_vol_seri#define mslg$l_gap_cnt mslg$r_media_ldr_overlay.mslg$r_volser_version.mslg$r_volser_gapcnt.mslg$l_gap_cnt#define mslg$b_fmtr_svr mslg$r_media_ldr_overlay.mslg$r_volser_version.mslg$r_version_overlay.mslg$r_fmtr_version.mslg$b_fmtr_svr#define mslg$b_fmtr_hvr mslg$r_media_ldr_overlay.mslg$r_volser_version.mslg$r_version_overlay.mslg$r;_fmtr_version.mslg$b_fmtr_hvrm#define mslg$l_hdr_code mslg$r_media_ldr_overlay.mslg$r_volser_version.mslg$r_version_overlay.mslg$l_hdr_codek#define mslg$l_bad_lbn mslg$r_media_ldr_overlay.mslg$r_volser_version.mslg$r_version_overlay.mslg$l_bad_lbnk#define mslg$z_sml_dsk mslg$r_media_ldr_overlay.mslg$r_volser_version.mslg$r_version_overlay.mslg$z_sml_dsk:#define mslg$q_ml_id mslg$r_media_ldr_overlay.mslg$q_ml_id"#endif /* #if !defined(__VAXC) */ N/* ; */N/* Controller Error (MSLG$K_CNT_ERR) */N/* */N/* Aggregate MSLG_CNT_ERR has been removed and it's fields have been */N/* incorporated into GENERIC_MSCP_ERRLOG. The following fields are */N/* specific to this error: */h/* CNT_ERR byte tag Z; /* Controller de;pendent data - this field is now */N/* */N/* Host Memory Access Error (MSLG$K_BUS_ADDR) */N/* */N/* Aggregate MSLG_BUS_ADDR has been removed and it's fields have been */N/* incorporated into GENERIC_MSCP_ERRLOG. The following fields are */N/* specific to this error: ; */N/* BUS_ADDR longword unsigned; /* Bus Address */N/* */N/* Disk Transfer Error (MSLG$K_DISK_TRN) */N/* */N#define MSLG$K_DISK_TRN_MSGSIZ 44 /* Size of DISK_TRN_ERROR msg. */ typedef struct _mslg_disk_trn {& GENERIC_MSCP_ERRLOG mslg$r_filler;N/* HDR_CODE - is ; now located in GENERIC_MSCP_ERRLOG */O char mslg$z_disk_trn; /* Controller or disk dependent data */ } MSLG_DISK_TRN;N/* */N/* SDI Error (MSLG$K_SDI) */N/* */ typedef struct _mslg_sdi {3 GENERIC_MSCP_ERRLOG mslg$r_generic_mscp_errlog;N unsigned; char mslg$z_sdi [12]; /* SDI Information */ } MSLG_SDI;N/* */N/* Small Disk Error (MSLG$K_SML_DSK) */N/* */N/* Aggregate MSLG_SML_DSK has been removed and it's fields have been */N/* incorporated into GENERIC_MSCP_ERRLOG. The following fields are */N/* specific to this; error: */N/* SDE_CYL word unsigned; /* Cylinder */S/* SML_DSK byte tag Z; /* Controller or device dependent */N/* */N/* Tape Transfer Error (MSLG$K_STI_ERR) */N/* */S/* There are no special field definition ;s for tape transfer errors at this time. */N/* */N/* STI communication or command failure (MSLG$K_STI_ERR) */N/* STI drive error log (MSLG$K_STI_DEL) */N/* STI formatter error log (MSLG$K_STI_FEL) */N/* */ typedef struct _mslg_sti_err {3 GENERIC_MSCP_ERRLOG ;mslg$r_generic_mscp_errlog;N unsigned char mslg$z_sti [20]; /* STI Information */ } MSLG_STI_ERR;N/* */N/* Bad Block Replacement Attempted (MSLG$K_REPLACE) */N/* */W#define MSLG$K_REPLACE_MSGSIZ 54 /* Size of REPLACE msg for BBR error logging */ typedef struct _mslg_replace {3 GENE;RIC_MSCP_ERRLOG mslg$r_generic_mscp_errlog;N/* Replace Flags now located in GENERIC_MSCP_ERRLOG */N unsigned int mslg$l_old_rbn; /* Previous RBN */N unsigned int mslg$l_new_rbn; /* New RBN */N unsigned short int mslg$w_cause; /* Event code causing replacement */ } MSLG_REPLACE;N/* */N/* Media Loader Errors (MSLG$K_LDR_ER ;R) */N/* */ typedef struct _mslg_ldr_err {3 GENERIC_MSCP_ERRLOG mslg$r_generic_mscp_errlog;N/*The following fields have been moved to GENERIC_MSCP_ERRLOG */N unsigned char mslg$b_ml_svr; /* Media loader software version */N unsigned char mslg$b_ml_hvr; /* Media loader hardware version */N unsigned short int mslg$w_ml_unit; /* Media loade;r unit number */N char mslg$z_ldr_err; /* Controller dependent data */ } MSLG_LDR_ERR; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MSLGDEF_LOADED */ wwe[UM/***********************;****************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise De;velopment, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **;/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */F/* Source: 31-AUG-1999 14:39:09 $1$DGA8345:[LIB_H.SRC]MTLDEF.SDL;1 *//************************************************************************* ;*******************************************************//*** MODULE $MTLDEF ***/#ifndef __MTLDEF_LOADED#define __MTLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* A;nd set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ ; */N/* MOUNTED VOLUME LIST ENTRY. ONE SUCH ENTRY APPEARS IN THE PROCESS MOUNTED */O/* VOLUME LIST FOR EACH VOLUME MOUNTED BY THE PROCESS AS /SHARE OR /NOSHARE. */N/* IN ADDITION, EACH VOLUME MOUNTED /SYSTEM OR /GROUP HAS AN ENTRY IN THE */N/* SYSTEM WIDE MOUNTED VOLUME LIST. */N/*- */ N#define MTL$K_LENGTH 32 ; /* LENGTH OF STRUCTURE */N#define MTL$C_LENGTH 32 /* LENGTH OF STRUCTURE */#define MTL$S_MTLDEF 32  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; #endif /* #ifdef __cplusplus */ typedef struct _mtl {N struct _mtl *mtl$l_mtlfl; /* FORWARD LIST POINTER */N struct _mtl *mtl$l_mtlbl; /* BACK LIST POINTER */N unsigned short int mtl$w_size; /* STRUCTURE ; SIZE IN BYTES */N unsigned char mtl$b_type; /* STRUCTURE TYPE CODE */ __union {N unsigned char mtl$b_status; /* STATUS BYTE */ __struct {N unsigned mtl$v_volset : 1; /* ENTRY IS FOR A VOLUME SET */O unsigned mtl$v_rvtvcb : 1; /* Entry is for a RVT/VCB volume set */' unsigned mtl$v_fill_0_ : 6; } mtl$r_status_bits; } mtl$r_status_overlay;N stru ;ct _ucb *mtl$l_ucb; /* POINTER TO DEVICE UCB */P void *mtl$l_logname; /* POINTER TO ASSOCIATED LOGICAL NAME */P void *mtl$l_lognam2; /* POINTER TO ALTERNATE LOGICAL NAME */N int mtldef$$_fill_1; /* RESERVED LONGWORD */N unsigned int mtl$l_uic; /* Owner UIC */ } MTL; #if !defined(__VAXC)6#define mtl$b_status mtl$r_status_overlay.mtl$b_statusH#define mtl$v_vo;lset mtl$r_status_overlay.mtl$r_status_bits.mtl$v_volsetH#define mtl$v_rvtvcb mtl$r_status_overlay.mtl$r_status_bits.mtl$v_rvtvcb"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MTLDEF_LOADED */ ww;[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 20;24 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software,; Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:37 by OpenVMS SDL V3.7 */F/* Source: 29-JUL-2005 13:32:25 $1$DGA8345:[LIB_H.SRC]MTXDEF.SDL;1 *//******************************* ;*************************************************************************************************//*** MODULE $MTXDEF ***/#ifndef __MTXDEF_LOADED#define __MTXDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pra;gma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_un;ion#endif#endif N/*+ */N/* LONGWORD MUTEX DEFINITIONS (OLD STYLE) */N/*- */ R#define MTX$S_MTXDEF 4 /* Old size name, synonym for MTX$S_MTX */ typedef struct _mtx { __union { int mtxdef$$_fill_1; __struct {* unsigned mtxdef$$_fill_2 : 16;N ;unsigned mtx$v_wrt : 1; /* WRITE PENDING OR IN PROGRESS */N unsigned mtx$v_interlock : 1; /* INTERLOCK ACCESS TO MUTEX */' unsigned mtx$v_fill_5_ : 6; } mtx$r_fill_1_bits; __struct {N unsigned short int mtx$w_owncnt; /*OWNERSHIP COUNT */N unsigned short int mtx$w_sts; /*STATUS BITS */" } mtx$r_fill_1_fields; } mtx$r_mtx_overlay; } MTX; #if !defined(__VAX ;C)?#define mtx$v_wrt mtx$r_mtx_overlay.mtx$r_fill_1_bits.mtx$v_wrtK#define mtx$v_interlock mtx$r_mtx_overlay.mtx$r_fill_1_bits.mtx$v_interlockG#define mtx$w_owncnt mtx$r_mtx_overlay.mtx$r_fill_1_fields.mtx$w_owncntA#define mtx$w_sts mtx$r_mtx_overlay.mtx$r_fill_1_fields.mtx$w_sts"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Res;tore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MTXDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** author;ized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicate;d or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created ;: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MULTIDEF ***/#ifndef __MULTIDEF_LOADED#define __MULTIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL;_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct str;uct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* Multicast table buffer header definition. One of these structures is */N/* embedded in the UCB. If more than one table is needed, memory is */N/* allocated and a linked list is formed. ; */N/*-- */S#define MULTI$C_HDR_LENGTH 16 /* Size of multicast table buffer header */N#define MULTI$T_START_ENTRIES 16 /* Start of entries */N#define MULTI$C_SIZE_ADDR 8 /* Size of the multicast address */N#define MULTI$C_SIZE_FCA 4 /* Size of FCA mask */N#define MULTI$C_ENTRIES_EMBEDED 6 /* # entries in embedded table */O#define MULTI$ ;C_ENTRIES_ALLOC 10 /* # entries to allocate a block for */#define MULTI$C_FCA_MASK 64 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _multidef {#pragma __nomember_alignmentS unsigned int multi$l_next_table; /* Pointer to next table 0 if last table */N unsigned int multi$l_reserved; /* Reserved ; */V unsigned short int multi$w_size; /* Size of multicast table buffer allocated */N unsigned char multi$b_type; /* Type of structure */! unsigned char multi$b_unused;N unsigned int multi$l_no_entries; /* Number of enabled entries */ } MULTIDEF;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previ;ously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MULTIDEF_LOADED */ ww([UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be u;sed, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclos;ed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-202 ;4 15:23:37 by OpenVMS SDL V3.7 */F/* Source: 29-JUL-2005 13:32:25 $1$DGA8345:[LIB_H.SRC]MTXDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MUTEXDEF ***/#ifndef __MUTEXDEF_LOADED#define __MUTEXDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE ; /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else;#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* QUADWORD MUTEX DEFINITIONS */N/*- */   #include #define MUTEX$M_WRT 0x1#define MUTEX$M_PRER;LS_CBK 0x2#define MUTEX$M_INTERLOCK 0x1V#define MUTEX$S_MUTEXDEF 8 /* Old size name, synonym for MUTEX$S_MUTEX */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mutex {#pragma __nomember_alignment __union {* unsigned __int64 mutex$q_quadword; __struct { __union {N un;signed short int mutex$w_sts; /* STATUS BITS */N __struct { /* Mutex status bit */Q unsigned mutex$v_wrt : 1; /* WRITE PENDING OR IN PROGRESS */Q unsigned mutex$v_prerls_cbk : 1; /* Pre release call back */1 unsigned mutex$v_fill_0_ : 6;- } mutex$r_mutex_sts_bits;N __struct { /* Interlock access to mutex */S ; unsigned mutex$v_interlock : 1; /* INTERLOCK ACCESS TO MUTEX */1 unsigned mutex$v_fill_1_ : 7;2 } mutex$r_mutex_sts_interlock;! } mutex$r_fill_1;N unsigned short int mutex$w_fill_2; /* FILL WORD */N unsigned int mutex$l_owncnt; /* OWNERSHIP COUNT */ } mutex$r_mutex_str; } mutex$r_fill_0; } MUTEX; #if !defined(__VAXC)8#define mutex$q_quadword mutex$r_f;ill_0.mutex$q_quadwordO#define mutex$w_sts mutex$r_fill_0.mutex$r_mutex_str.mutex$r_fill_1.mutex$w_stsf#define mutex$v_wrt mutex$r_fill_0.mutex$r_mutex_str.mutex$r_fill_1.mutex$r_mutex_sts_bits.mutex$v_wrtt#define mutex$v_prerls_cbk mutex$r_fill_0.mutex$r_mutex_str.mutex$r_fill_1.mutex$r_mutex_sts_bits.mutex$v_prerls_cbkw#define mutex$v_interlock mutex$r_fill_0.mutex$r_mutex_str.mutex$r_fill_1.mutex$r_mutex_sts_interlock.mutex$v_interlockF#define mutex$l_owncnt mutex$r_fill_0.mutex$r_mutex_str.;mutex$l_owncnt"#endif /* #if !defined(__VAXC) */ #define MTXDBG$K_REV1 1#define MTXDBG$K_REV2 2#define MTXDBG$K_REVISION 2#define MTXDBG$K_MUTEX 1#define MTXDBG$K_INFO 2#define MTXDBG$K_MAX_FLAG 2#define MTXDBG$K_LOCKR 1#define MTXDBG$K_LOCKW 2#define MTXDBG$K_UNLOCK 3#define MTXDBG$K_LOCKREXEC 4#define MTXDBG$K_LOCKWEXEC 5#define MTXDBG$K_UNLOCKEXEC 6#define MTXDBG$K_LOCKR_QUAD 7#define MTXDBG$K_LOCKW_QUAD 8#define MTXDBG$K_UNLOCK_QUAD 9"#define MTXDBG$K_L;OCKREXEC_QUAD 10"#define MTXDBG$K_LOCKWEXEC_QUAD 11##define MTXDBG$K_UNLOCKEXEC_QUAD 12#define MTXDBG$K_LOCKWNOWAIT 13$#define MTXDBG$K_LOCKWNOWAIT_QUAD 14#define MTXDBG$K_LOCKR_WAIT 15#define MTXDBG$K_LOCKW_WAIT 16#define MTXDBG$K_UNLOCK_REL 17##define MTXDBG$K_LOCKREXEC_INUSE 18##define MTXDBG$K_LOCKWEXEC_INUSE 19"#define MTXDBG$K_UNLOCKEXEC_REL 20##define MTXDBG$K_LOCKR_QUAD_WAIT 21##define MTXDBG$K_LOCKW_QUAD_WAIT 22##define MTXDBG$K_UNLOCK_QUAD_REL 23(#define MTXDBG$K_LOC ;KREXEC_QUAD_INUSE 24(#define MTXDBG$K_LOCKWEXEC_QUAD_INUSE 25'#define MTXDBG$K_UNLOCKEXEC_QUAD_REL 26%#define MTXDBG$K_LOCKWNOWAIT_INUSE 27*#define MTXDBG$K_LOCKWNOWAIT_QUAD_INUSE 28#define MTXDBG$K_MAX_MODE 28#define MTXDBG$M_MUTEX 0x1#define MTXDBG$M_MUTEX_WAIT 0x2N#define MTXDBG$K_LENGTH 108 /* Structure size */N#define MTXDBG$C_LENGTH 108 /* Structure size */  9#ifdef __cplusplus /* Define structure prototypes *;/struct _mtxtrh; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mtxdbg {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _mtxtrh *mtxd ;bg$q_trace_buffer; /* pointer to trace buffer */#else( unsigned __int64 mtxdbg$q_trace_buffer;#endifN unsigned short int mtxdbg$w_mbo; /* must-be-one field */N unsigned char mtxdbg$b_type; /* Structure type */N unsigned char mtxdbg$b_subtype; /* and subtype */N unsigned int mtxdbg$l_revision; /* revision field */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If us ;ing pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 mtxdbg$q_size; /* Size */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN int (*mtxdbg$l_start_trace)(); /* ptr to start trace routine */N int (*mt ;xdbg$l_stop_trace)(); /* ptr to stop trace routine */N void (*mtxdbg$l_trace_mutex)(); /* ptr to mutex trace routine */N void (*mtxdbg$l_trace_mutex_wait)(); /* ptr to mutex wait trace routine */# void (*mtxdbg$l_debug_print)(); __union {N unsigned int mtxdbg$l_trace_flags; /* trace flags */ __struct {( unsigned mtxdbg$v_mutex : 1;- unsigned mtxdbg$v_mutex_wait : 1;* unsigned mtxdbg$v_fi ;ll_2_ : 6;( } mtxdbg$r_trace_flags_bits;' } mtxdbg$r_trace_flags_overlay;N unsigned int mtxdbg$l_mtx_flags; /* trace specific mutex */N int mtxdbg$l_cpu_flags; /* trace specific CPU */N unsigned int mtxdbg$l_trace_run; /* trace run index */ char mtxdbg$b_fill_3_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadw;ord#else#pragma __nomember_alignment#endif( unsigned __int64 mtxdbg$q_reserved1;#pragma __nomember_alignment( unsigned __int64 mtxdbg$q_reserved2;( unsigned __int64 mtxdbg$q_reserved3;( unsigned __int64 mtxdbg$q_reserved4;_ unsigned __int64 *mtxdbg$pq_scc; /* pointer to array of cycle counts per possible CPU */` unsigned __int64 *mtxdbg$pq_systime; /* pointer to array of systime info per possible CPU */ int mtxdbg$l_max_cpus; char mtxdbg$b_fill_4_ [4]; ; } MTXDBG; #if !defined(__VAXC)N#define mtxdbg$l_trace_flags mtxdbg$r_trace_flags_overlay.mtxdbg$l_trace_flags\#define mtxdbg$v_mutex mtxdbg$r_trace_flags_overlay.mtxdbg$r_trace_flags_bits.mtxdbg$v_mutexf#define mtxdbg$v_mutex_wait mtxdbg$r_trace_flags_overlay.mtxdbg$r_trace_flags_bits.mtxdbg$v_mutex_wait"#endif /* #if !defined(__VAXC) */ N#define MTXTRE$K_LENGTH 40 /* Structure size */  9#ifdef __cplusplus /* Define structure prototypes */ ; struct _ktb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mtxtre {#pragma __nomember_alignmentO unsigned __int64 mtxtre$q_timestamp; /* timestamp in system cycle counts */N unsigned __int64 mtxtre$q_pc; /* callers PC */Q unsigned int mtxtre$l_cpuid; /* c ;urrent CPU id or address of CPU db */N unsigned int mtxtre$l_mode; /* general trace category */N unsigned int mtxtre$l_flag; /* which event was traced */N unsigned int mtxtre$l_mutex; /* address of mutex */N struct _pcb *mtxtre$l_pcb; /* current process during trace */! unsigned int mtxtre$l_spare1; } MTXTRE;N#define MTXTRH$K_LENGTH 72 /* Structure size */ c#if !defin ;ed(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mtxtrh {#pragma __nomember_alignmentN int mtxtrh$l_idx; /* current index into trace buffer */N unsigned int mtxtrh$l_max_idx; /* maximum trace index */N unsigned short int mtxtrh$w_mbo; /* must-be-one field */N unsigned char mtxtrh$b_typ ;e; /* Structure type */N unsigned char mtxtrh$b_subtype; /* and subtype */ unsigned int mtxtrh$l_fill1;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 mtxtrh$q_size; /* Size */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Define;d whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _mtxtre *mtxtrh$q_entry_ptr; /* pointer to first trace entry */#else% unsigned __int64 mtxtrh$q_entry_ptr;#endifN MTXTRE mtxtrh$r_entry [1]; /* array of trace entries */ } MTXTRH;   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragm;a __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MUTEXDEF_LOADED */ wwv[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise D;evelopment, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not ; **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************************************************** ;*********************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */F/* Source: 23-APR-1993 14:24:33 $1$DGA8345:[LIB_H.SRC]MVLDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MVLDEF ***/#ifndef __MVLDEF_LOADED#define __MVLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma ;__nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if ;!defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* MAGNETIC TAPE VOLUME LIST */N/* THIS STRUCTURE DESCRIBES THE VOLUMES IN A VOLUME SET */N/*- ; */O#define MVL$K_FIXLEN 36 /*LENGTH OF FIXED AREA OF STRUCTURE */O#define MVL$C_FIXLEN 36 /*LENGTH OF FIXED AREA OF STRUCTURE */#define MVL$S_MVLDEF 36  9#ifdef __cplusplus /* Define structure prototypes */ struct _vcb; #endif /* #ifdef __cplusplus */ typedef struct _mvl {N struct _vcb *mvl$l_vcb; /*ADDRESS OF VCB */N int mvldef$$_fill_1; /*SPARE ; */N unsigned short int mvl$w_size; /*SIZE OF STRUCTURE */N unsigned char mvl$b_type; /*TYPE OF STRUCTURE */N unsigned char mvl$b_nvols; /*NUMBER OF VOLUMES IN VOLUME SET */N char mvl$t_set_id [6]; /*FILE SET ID FOR THE VOLUME SET */S unsigned char mvl$b_vol_acc; /*VOLUME ACCESSIBILTY CHARACTER DEFAULT */ __union {N unsigned char mvl$b_mou_prv; /*USER'S MOU ;NT TIME PRIVILEGES */ __struct {N unsigned mvl$v_volpro : 1; /*VOLPRO PRIVILEGE */W unsigned mvl$v_ovrpro : 1; /*OVERRIDE PRIVILEGE (BYPASS,SYSPRV,VOLPRO) */N unsigned mvl$v_oper : 1; /*OPER PRIVILEDGE */' unsigned mvl$v_fill_0_ : 5;! } mvl$r_mou_prv_bits; } mvl$r_mou_prv_overlay;N char mvl$t_volowner [14]; /* VOL1 ONER IDENTIFIER FIELD */N unsigned c ;har mvl$b_stdver; /* ANSI VERSION OF VOLUME SET */N char mvldef$$_fill_2; /* SPARE */ } MVL; #if !defined(__VAXC)9#define mvl$b_mou_prv mvl$r_mou_prv_overlay.mvl$b_mou_prvJ#define mvl$v_volpro mvl$r_mou_prv_overlay.mvl$r_mou_prv_bits.mvl$v_volproJ#define mvl$v_ovrpro mvl$r_mou_prv_overlay.mvl$r_mou_prv_bits.mvl$v_ovrproF#define mvl$v_oper mvl$r_mou_prv_overlay.mvl$r_mou_prv_bits.mvl$v_oper"#endif /* #if !defined(__VAXC) */ ;N/* THE FOLLOWING STRUCTURE IN REPEATED IN MVL FOR EACH REEL IN VOLUME SET */N#define MVL$K_LENGTH 8 /*LENGTH OF STRUCTURE */N#define MVL$C_LENGTH 8 /*LENGTH OF STRUCTURE */#define MVL$S_MVLDEF1 8 typedef struct _mvl1 {N char mvl$t_vollbl [6]; /*VOLUME LABEL */N unsigned char mvl$b_rvn; /*RELATIVE UNIT NUMBER */ __union {N unsigned char mvl$b_status ;; /*STATUS OF VOLUME */ __struct {N unsigned mvl$v_mounted : 1; /*REEL IS MOUNTED */N unsigned mvl$v_unused : 1; /*IS THIS ENTRY IN USE */R unsigned mvl$v_overide : 1; /*CAN OVERRIDE PROTECTION ON THIS REEL */' unsigned mvl$v_fill_1_ : 5; } mvl$r_status_bits; } mvl$r_status_overlay; } MVL1; #if !defined(__VAXC)6#define mvl$b_status mvl$r_status_overlay.mv ;l$b_statusJ#define mvl$v_mounted mvl$r_status_overlay.mvl$r_status_bits.mvl$v_mountedH#define mvl$v_unused mvl$r_status_overlay.mvl$r_status_bits.mvl$v_unusedJ#define mvl$v_overide mvl$r_status_overlay.mvl$r_status_bits.mvl$v_overide"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#e;ndif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MVLDEF_LOADED */ wwņ[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone w;ithout the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the ;prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */ ;H/* Source: 20-APR-1993 14:23:13 $1$DGA8345:[LIB_H.SRC]MVMSLDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $MVMSLDEF ***/#ifndef __MVMSLDEF_LOADED#define __MVMSLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragma;s supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#end;if#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* $MVMSLDEF - mount verification messages list structure definition */N/* */I/* The MVMSL provides a mechanism for communicating information about */I/* mount verification messages to device driver sp ;ecial mount */I/* verification processing routines. */N/*-- */#define MVMSL$M_NOSUFFIX 0x1#define MVMSL$M_SUPRESS 0x2N#define MVMSL$K_LENGTH 8 /* Length of a MVMSL entry. */#define MVMSL$S_MVMSLDEF 13 Atypedef struct _mvmsl { /* WARNING: aggregate has origin of -5 */= /* WARNING: aggregate element "mvmsl$b_maxidx" ignored */@ /* WARNING: ag ;gregate element "mvmsl$l_sndmsgoff" ignored */N unsigned short int mvmsl$w_msg_code; /* The MSG$_ code for this entry. */ __union {N unsigned short int mvmsl$w_flags; /* Processing flags: */ __struct {L unsigned mvmsl$v_nosuffix : 1; /* Do not add suffix. */K unsigned mvmsl$v_supress : 1; /* May be suppressed. */) unsigned mvmsl$v_fill_2_ : 6; } mvmsl$r_fill_1_; } mvmsl$r_fill_0_;[ ; int mvmsl$l_textoff; /* Offset from MVMSL base to ASCIC message text. */ } MVMSL; #if !defined(__VAXC)3#define mvmsl$w_flags mvmsl$r_fill_0_.mvmsl$w_flagsI#define mvmsl$v_nosuffix mvmsl$r_fill_0_.mvmsl$r_fill_1_.mvmsl$v_nosuffixG#define mvmsl$v_supress mvmsl$r_fill_0_.mvmsl$r_fill_1_.mvmsl$v_supress"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#p;ragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __MVMSLDEF_LOADED */ ww0[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterpri;se Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is no;t **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************************* ;*************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 19-APR-1993 14:43:48 $1$DGA8345:[LIB_H.SRC]NAFDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $NAFDEF ***/#ifndef __NAFDEF_LOADED#define __NAFDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pra;gma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct;#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* */N/* Structure for network proxy login file, NETUAF.DAT (VMS version 4.x) */N/* ; */N/*-- */#define NAF$M_TASK 0x1#define NAF$M_BATCH 0x2#define NAF$M_INTERACTIVE 0x4N#define NAF$K_LENGTH 100 /* Length of record */N#define NAF$C_LENGTH 100 /* Length of record */#define NAF$S_NAFDEF 100 typedef struct _naf { __union {T char naf$t_remname [64]; /* Combined nodename and r ;emote username */ __struct {N char naf$t_node [32]; /* Node name */N char naf$t_remuser [32]; /* Remote username */ } naf$r_fill_1_; } naf$r_fill_0_;N char naf$t_localuser [32]; /* Local username */ __union {N int naf$l_flags; /* Flags longword */ __struct {N unsigned naf$v_task : 1; /* Allow t ;ask=0 access */N unsigned naf$v_batch : 1; /* Allow batch jobs */N unsigned naf$v_interactive : 1; /* Allow interactive login */' unsigned naf$v_fill_4_ : 5; } naf$r_fill_3_; } naf$r_fill_2_; } NAF; #if !defined(__VAXC)1#define naf$t_remname naf$r_fill_0_.naf$t_remname9#define naf$t_node naf$r_fill_0_.naf$r_fill_1_.naf$t_node?#define naf$t_remuser naf$r_fill_0_.naf$r_fill_1_.naf$t_remuser-#d ;efine naf$l_flags naf$r_fill_2_.naf$l_flags9#define naf$v_task naf$r_fill_2_.naf$r_fill_3_.naf$v_task;#define naf$v_batch naf$r_fill_2_.naf$r_fill_3_.naf$v_batchG#define naf$v_interactive naf$r_fill_2_.naf$r_fill_3_.naf$v_interactive"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */;#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NAFDEF_LOADED */ ww@:[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyo;ne without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** ;the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 ; */H/* Source: 13-MAY-1993 17:16:34 $1$DGA8345:[LIB_H.SRC]NAFV5DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $NAFV5DEF ***/#ifndef __NAFV5DEF_LOADED#define __NAFV5DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pr<agmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct<#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* */N/* Structure for network proxy login file, NETPROXY.DAT */N/* */N/*-- < */ #define NAFV5$C_PROXY_FIXEDLEN 4 #define NAFV5$K_PROXY_FIXEDLEN 4N#define NAFV5$C_DEFPROXY 1 /* Default proxy account */N#define NAFV5$C_PROXY 2 /* NONdefault proxy account */N#define NAFV5$C_MAXPROXY 15 /* Max number of proxy accounts */N#define NAFV5$K_MAXPROXY 15 /* Max number of proxy accounts */N#define NAFV5$C_MAXPROXYLEN 32 /* Max length of proxy string */N <#define NAFV5$K_MAXPROXYLEN 32 /* Max length of proxy string */ typedef struct _nafv5proxy {N unsigned short int nafv5$w_proxylen; /* String length */N unsigned short int nafv5$w_type; /* Type field */#if defined(__VAXC) char nafv5$t_proxy[];#elseT/* Warning: empty char[] member for nafv5$t_proxy at end of structure not created */"#endif /* #if defined(__VAXC) */ } NAFV5PROXY;#define NAFV5$M_TASK 0x1#defin <e NAFV5$M_BATCH 0x2#define NAFV5$M_INTERACTIVE 0x4#define NAFV5$M_UIC 0x8N#define NAFV5$K_FIXEDLEN 76 /* Length of fixed part of record */N#define NAFV5$C_FIXEDLEN 76 /* Length of fixed part of record */N#define NAFV5$C_FORMAT1 1 /* format version # */N#define NAFV5$K_FORMAT1 1 /* format version # */N/* Define the max record size */#define NAFV5$C_MAXREC 6 <56#define NAFV5$K_MAXREC 656N#define NAFV5$S_NAFV5DEF 76 /* Old size name - synonym */ typedef struct _nafv5 {N unsigned short int nafv5$w_format; /* Record format version */N unsigned short int nafv5$w_reclen; /* Record length */N unsigned short int nafv5$w_nodelen; /* Length of remote node string */N unsigned short int nafv5$w_remuserlen; /* Length of remote user string */ __union {N int nafv5$l_flags; < /* Flags longword */ __struct {N unsigned nafv5$v_task : 1; /* Allow task=0 access */N unsigned nafv5$v_batch : 1; /* Allow batch jobs */N unsigned nafv5$v_interactive : 1; /* Allow interactive login */Q unsigned nafv5$v_uic : 1; /* Remote user uses UIC authentication */) unsigned nafv5$v_fill_6_ : 4; } nafv5$r_fill_1_; } nafv5$r_fill_0_; <__union {T char nafv5$t_remname [64]; /* Combined nodename and remote username */ __struct {N char nafv5$t_node [32]; /* Node name */ __union {N char nafv5$t_remuser [32]; /* Remote username */ __union {N unsigned int nafv5$l_remuic; /* Remote UIC */ __struct {R unsigned short int nafv5$w_remuic_me <m; /* Member number */Q unsigned short int nafv5$w_remuic_grp; /* Group number */* } nafv5$r_fill_5_;& } nafv5$r_fill_4_;# } nafv5$r_userovly; } nafv5$r_fill_3_; } nafv5$r_fill_2_; } NAFV5; #if !defined(__VAXC)3#define nafv5$l_flags nafv5$r_fill_0_.nafv5$l_flagsA#define nafv5$v_task nafv5$r_fill_0_.nafv5$r_fill_1_.nafv5$v_taskC#define nafv5$v_batch nafv5$r_fill_0_.nafv5$r_fill_1_. <nafv5$v_batchO#define nafv5$v_interactive nafv5$r_fill_0_.nafv5$r_fill_1_.nafv5$v_interactive?#define nafv5$v_uic nafv5$r_fill_0_.nafv5$r_fill_1_.nafv5$v_uic7#define nafv5$t_remname nafv5$r_fill_2_.nafv5$t_remnameA#define nafv5$t_node nafv5$r_fill_2_.nafv5$r_fill_3_.nafv5$t_nodeX#define nafv5$t_remuser nafv5$r_fill_2_.nafv5$r_fill_3_.nafv5$r_userovly.nafv5$t_remuserf#define nafv5$l_remuic nafv5$r_fill_2_.nafv5$r_fill_3_.nafv5$r_userovly.nafv5$r_fill_4_.nafv5$l_remuic~#define nafv5$w_remuic <_mem nafv5$r_fill_2_.nafv5$r_fill_3_.nafv5$r_userovly.nafv5$r_fill_4_.nafv5$r_fill_5_.nafv5$w_remuic_mem~#define nafv5$w_remuic_grp nafv5$r_fill_2_.nafv5$r_fill_3_.nafv5$r_userovly.nafv5$r_fill_4_.nafv5$r_fill_5_.nafv5$w_remuic_grp"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif <#ifdef __cplusplus }#endif#pragma __standard #endif /* __NAFV5DEF_LOADED */ ww`[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone wit;MTLDEF;MTXDEFR MT_ROUTINES;MULTIDEF;MUTEXDEF;MVLDEF;nMVMSLDEF;NAFDEF;rNAFV5DEF <lNDTDEF2<(NFBDEF<NMADEF)>NMBDEF7>dNPHDEFP>Z NPOOL_DATA}> NSAARGDEF>BNSABDEF> NSAEVTDEF> NSAFAIDEF>$ NSAIDTDEF> NSAIFPDEF>NSASDEF ?fNTEDEF?vOCBDEF)?OLCKDEF4?ORBDEFOSLVMS <hout the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the pr<ior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F </* Source: 24-APR-2003 13:24:17 $1$DGA8345:[LIB_H.SRC]NDTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $NDTDEF ***/#ifndef __NDTDEF_LOADED#define __NDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporte<d */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif< #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* NEXUS DEVICE AND ADAPTER TYPE CODES */N/*- */N/*DEFINE CONSTANT TYPE CODES */N#define NDT$_MEM4NI 8 /*MEMORY, 4K NOT< INTERLEAVED */N#define NDT$_MEM4I 9 /*MEMORY, 4K INTERLEAVED */N#define NDT$_MEM16NI 16 /*MEMORY, 16K NOT INTERLEAVED */N#define NDT$_MEM16I 17 /*MEMORY, 16K INTERLEAVED */N#define NDT$_MEM1664NI 18 /*MEMORY, 16K AND 64K MIXED */N#define NDT$_MB 32 /*MBA 0,1,2, OR 3 */N#define NDT$_UB0 40 /*UB ADAPTER OR INTERCONNECT 0, */N#d<efine NDT$_UB1 41 /* 1, */N#define NDT$_UB2 42 /* 2, */N#define NDT$_UB3 43 /* OR 3 */N#define NDT$_DR32 48 /*DR32 0,1,2,... */N#define NDT$_CI 56 /*CI780'S, CI750'S */N#define NDT$_MPM0 64 /*MULTIPORT MEMORY 0, */N#define NDT$_MPM1 65 < /* 1, */N#define NDT$_MPM2 66 /* 2, */N#define NDT$_MPM3 67 /* OR 3 */N#define NDT$_DISK9 81 /* Disk on 009 */N#define NDT$_TERM9 82 /* Terminal on 009 */N#define NDT$_TAPE9 83 /* Tape on 009 */N#define NDT$_PRTR9 84 /* Printer on <009 */N#define NDT$_SFUN9 85 /* Spec. func. ctrllr. on 009 */N#define NDT$_USER9 86 /* User-defined device on 009 */V#define NDT$_MEM64NIL 104 /*64K NON-INTERLEAVED MEM, LOWER CONTROLLER */R#define NDT$_MEM64EIL 105 /*64K EXTERNALLY INTERLEAVED MEM, LOWER */V#define NDT$_MEM64NIU 106 /*64K NON-INTERLEAVED MEM, UPPER CONTROLLER */R#define NDT$_MEM64EIU 107 /*64K EXTERNALLY INT<ERLEAVED MEM, UPPER */N#define NDT$_MEM64I 108 /*64K INTERNALLY INTERLEAVED MEMORY */W#define NDT$_MEM256NIL 112 /*256K NON-INTERLEAVED MEM, LOWER CONTROLLER */S#define NDT$_MEM256EIL 113 /*256K EXTERNALLY INTERLEAVED MEM, LOWER */W#define NDT$_MEM256NIU 114 /*256K NON-INTERLEAVED MEM, UPPER CONTROLLER */S#define NDT$_MEM256EIU 115 /*256K EXTERNALLY INTERLEAVED MEM, UPPER */O#define NDT$_MEM256I 116 /*256K INT <ERNALLY INTERLEAVED MEMORY */N#define NDT$_KA410 128 /*VAXstar system */N#define NDT$_KA420 128 /*PVAX system */N#define NDT$_KA640 129 /*MAYFAIR II system */#define NDT$_SHAC 130#define NDT$_SGEC 131N#define NDT$_KA520CIO 132 /* CIRRUS CIO module */N#define NDT$_KA520COMM 133 /* CIRRUS COMM module */#define NDT$_KA43 134#d<efine NDT$_KA440 135#define NDT$_KA46 135N/* BI node device types. Note low word is hardware device type on BI. */N/* High order word (i.e. the 8000) distinguishes device as a BI device. */N/* First BI memory nodes */N#define NDT$_SCORMEM -2147483647 /* Scorpio Memory */N/* Then other BI devices */N#define NDT$_BIMFA -2147483391 /* BI Multi-Function< Adapter */N#define NDT$_BUA -2147483390 /* BI UNIBUS adapter */N#define NDT$_BLA -2147483389 /* BI LESI adapter */N#define NDT$_KDZ11 -2147483387 /* KDZ11 processor */N#define NDT$_KA810 -2147483387 /* KA810 processor */N#define NDT$_NBI -2147483386 /* BI-NMI Adapter */N#define NDT$_XBIB -2147475193 /* BI-XMI Adapter */N#defin<e NDT$_XBIB_PLUS -2147475185 /* BI-XMI Plus Adapter */N#define NDT$_BCA -2147483384 /* BI-CI Adapter */N#define NDT$_BICOMBO -2147483383 /* BI Combo Board */N#define NDT$_BCI750 -2147483381 /* Interim BI-CI Adapter */N#define NDT$_BIACP -2147483380 /* Aurora Processor Module */N#define NDT$_BDA -2147483378 /* BI-to-Disk Adapter */N#define NDT$_BSA -2147467004 < /* BI-to-SI Adapter */N#define NDT$_KSB50 -2147467004 /* BI-to-SI Adapter */N#define NDT$_AIO -2147466995 /* Aurora I/O Module */N#define NDT$_KFBTA -2147466995 /* Aurora I/O Module */N#define NDT$_AIE_TK -2147466997 /* Aurora I/O Extension Module */N#define NDT$_AIE_TKNI -2147466994 /* Aurora I/O Extension Module */N#define NDT$_AIE_NI -2147466993 /* Aurora I/O Exte<nsion Module */N#define NDT$_DEBNT -2147466993 /* Aurora I/O Extension Module */N#define NDT$_DSB32 -2147483382 /* BI-Hi speed sync comm adapter */Q#define NDT$_LACP -2147466996 /* BI-VAXstation 8000 graphics adapter */N#define NDT$_DEBNI -2147483368 /* AIE varient */N#define NDT$_KWB -2147450853 /* BI_KWB32 module */N/* XMI node device types. Note low word is hardware device type on XMI. */N<#define NDT$_CIXCD 3077 /* CI port CIXCD adapter */N#define NDT$_KFMSA 2064 /* DSSI port KFMSA adapter */N#define NDT$_XCP 32769 /* Calypso/CVAX CPU */N#define NDT$_XRP 32898 /* RIGEL CPU */N#define NDT$_XMA 16385 /* XMI Memory */N#define NDT$_XBI 8193 /* XBI Adapter */N#define NDT$_XWATCH 3076 < /* XWATCH Adapter */N#define NDT$_XJA 4097 /* XJA Adapter */N#define NDT$_AXA 4098 /* AXA Adapter */#define NDT$_HSX50 3106#define NDT$_KDM70 3106N#define NDT$_XBI_PLUS 8194 /* XBI-Plus adapter */N#define NDT$_X1202 32896 /* Mariah CPU */N#define NDT$_DEMNA 3075 /* NI port - DEMNA adapter */N<#define NDT$_XSA 2085 /* XMI-SCSI adapter */N#define NDT$_LAMB 4138 /* Laser-XMI adapter */N#define NDT$_XZA_SCSI 3126 /* XMI-SCSI adapter */N#define NDT$_XZA_DSSI 3121 /* XMI-DSSI adapter */N#define NDT$_CIMNA 3119 /* XMI-CI adapter */N#define NDT$_DEMFA 2083 /* XMI-FDDI adapter */N/* MBUS node devices.  < */N#define NDT$_MBUS_FTAM -1878982655 /*Tape adapter */N#define NDT$_MBUS_FQAM -1878982399 /*QBUS adapter */N#define NDT$_MBUS_LEGSS -1878982654 /*LEGSS graphics */N#define NDT$_MBUS_FWIOM -1878982652 /*I/O module */N#define NDT$_MBUS_KA60 -1878982392 /*Dual CVAX CPU */N#define NDT$_MBUS_8MB -1878917104 /*8MB memory!< */N#define NDT$_MBUS_16MB -1878916848 /*16MB memory */N#define NDT$_MBUS_32MB -1878916336 /*32MB memory */N#define NDT$_MBUS_32MBA -1878916080 /*32MB memory */N#define NDT$_MBUS_64MB -1878915824 /*64MB memory */N#define NDT$_MBUS_128MB -1878915312 /*128MB memory */N#define NDT$_MBUS_8MBFS -1862402032 /*8MB Firestarter */"<N/* (TYC0002) keep UCODE constants for CI boot adapters here */#define UCODE_CI780 1#define UCODE_BCA 2#define UCODE_BCA_ONBOARD 3#define UCODE_ONBOARD 4#define NDT$_IOP 8192!#define NDT$_KA0302_EV5_CPU 49152!#define NDT$_KA0302_EV3_4MB 32768!#define NDT$_KA0302_EV4_4MB 32769 #define NDT$_KA0302_NV_4MB 32770!#define NDT$_KA0302_EV3_1MB 32771!#define NDT$_KA0302_EV4_1MB 32772 #define NDT$_KA0302_NV_1MB 32773 #define NDT$_KA0302_LEPMEM 16385#define NDT$_KA0#<302_MEM 16384#define NDT$_KA0302_IOP 8192#define NDT$_KA0C05_TLEP 32784&#define NDT$_KA0C05_TLEP_EV5_1MB 32784&#define NDT$_KA0C05_TLEP_EV5_4MB 32785'#define NDT$_KA0C05_TLEP_EV5_16MB 32786'#define NDT$_KA0C05_TLEP_2EV5_1MB 32787'#define NDT$_KA0C05_TLEP_2EV5_4MB 32788(#define NDT$_KA0C05_TLEP_2EV5_16MB 32789'#define NDT$_KA0C05_TLEP_EV56_4MB 32800'#define NDT$_KA0C05_TLEP_EV56_8MB 32801(#define NDT$_KA0C05_TLEP_2EV56_4MB 32802(#define NDT$_KA0C05_TLEP_2EV56_8MB 32803'#define NDT$ $<_KA0C08_TLEP_2EV6_4MB 32805 #define NDT$_KA0C05_NV_MEM 17408#define NDT$_KA0C05_TMEM 20480#define NDT$_KA0C05_TIOP 8192#define NDT$_KA0C05_ITIOP 8224#define NDT$_FLAG 12032#define NDT$_HPC 61184N#define NDT$_FVME_VENDOR_ID 50336627 /* Vendor ID, FBUS-VME adapter */O#define NDT$_FVME 100663297 /* FBUS-VME adapter software version */N#define NDT$_DEANA 100745216 /* Module number = B2005 */N#define NDT$_FCA 100728832 /* Module numb%<er = B2004 */N#define NDT$_FZA 100777984 /* Module number = B2007 */N#define NDT$_FFA 100761600 /* Module number = B2006 */N#define NDT$_FBE 101711872 /* FBE is an exception */N#define NDT$_KA0202_FBUS 842022912 /* Cobra Fbus bridge */N#define NDT$_KA0302_FBUS 858800128 /* Laser Fbus bridge */N#define NDT$_KA0C05_FBUS 875577344 /* TLaser Fbus bridge */&<#define NDT$_PMAD 1145130320 #define NDT$_PMAD_AA_H 541147437#define NDT$_PMAF 1178684752 #define NDT$_PMAF_AA_H 541147437 #define NDT$_PMAF_CA_H 541147949 #define NDT$_PMAF_FA_H 541148717 #define NDT$_PMAF_FD_H 541345325 #define NDT$_PMAF_FS_H 542328365 #define NDT$_PMAF_FU_H 542459437#define NDT$_PMAZ 1514229072"#define NDT$_PMAZB_AA_H 1094790466"#define NDT$_PMAZC_AA_H 1094790467#define NDT$_PMAB 1111575888"#define NDT$_PMABV_AA_H 1094790486#define NDT$_AV01 825251393"#define ND'<T$_AV01B_AA_H 1094790466#define NDT$_PMAG 1195461968 #define NDT$_PMAG_JA_H 541149741 #define NDT$_PMAG_FA_H 541148717"#define NDT$_PMAGB_BA_H 1094856002"#define NDT$_PMAGD_AA_H 1094790468#define NDT$_PMAGC_H 538976323"#define NDT$_PMAGC_AA_H 1094790467"#define NDT$_PMAGC_BA_H 1094856003"#define NDT$_PMAGC_DA_H 1094987075#define NDT$_PMAGD_H 538976324"#define NDT$_PMAGC_EA_H 1095052611 #define NDT$_PMAG_CA_H 541147949 #define NDT$_PMAG_DA_H 541148205#define NDT$_DELTA 1414284612#d(<efine NDT$_DELTA_H 538976321#define NDT$_KZTS 1398037067"#define NDT$_KZTSA_AA_H 1094790465"#define NDT$_KZTSA_BA_H 1094856001#define NDT$_PMAT 1413565776 #define NDT$_PMAT_AA_H 541147437#define NDT$_OTTO 1330926671#define NDT$_OTTO_H 538976288#define NDT$_DGLTA 1414285124#define NDT$_DGLTA_H 1095118145!#define NDT$_EISA_SYSTEM_BOARD 22#define NDT$_AHA1742A 33591300#define NDT$_AHA1740 16814084#define NDT$_DEPCA 541238032#define NDT$_CPQ3011 288362766#define NDT$_CPQ3021)< 556798222#define NDT$_CPQ3111 288428302#define NDT$_CPQ3112 305205518#define NDT$_CPQ3121 556863758#define NDT$_CPQ3122 573640974#define NDT$_CPQ3201 20058382#define NDT$_CPQ3202 36835598#define NDT$_CPQ3231 825364750#define NDT$_CPQ3232 842141966#define NDT$_PRO6000 6311746#define NDT$_PRO6001 23088962#define NDT$_PRO6002 39866178#define NDT$_DEFEA 19964688#define NDT$_DEFEA_2 36741904#define NDT$_KFESA 3056400#define NDT$_KFESB 19833616#define NDT$_KFESC 36610*<832#define NDT$_KFESD 53388048#define NDT$_MLX0075 1962973237#define NDT$_MLX0077 1996527669#define NDT$_DEC4250 1346544400#define NDT$_DEC3003 53519120'#define NDT$_AHA1742A_FLOPPY 1347374150#define NDT$_NS16450 91216$#define NDT$_PC4XD_SERIAL 1395934032&#define NDT$_PC4XD_PARALLEL 1278493520!#define NDT$_DIGIBOARD 1229408580%#define NDT$_PARALLEL_PORT 1414680656##define NDT$_SERIAL_PORT 1414680659#define NDT$_DE200 808600900#define NDT$_AHA_1540 808727857##define ND+<T$_SOUND_BOARD 1314213715#define NDT$_WD90C24 809059415#define NDT$_KBD 4473419#define NDT$_MOUS 1398099789#define NDT$_COM1 827150147#define NDT$_COM2 843927363#define NDT$_FLOP 1347374150#define NDT$_DE20 808600900#define NDT$_LPT1 827609164#define NDT$_DW11 825317188#define NDT$_DT20 808604740#define NDT$_PCXB 1113080656#define NDT$_IDEM 1296385097#define NDT$_IDES 1397048393#define NDT$_USBC 1128420181#define NDT$_CYPRESS -963440512'#define NDT$_DIGITAL_PCI_V,<ENDOR_ID 4113#define NDT$_PBB 69649#define NDT$_TULIP 135185#define NDT$_FOCUS 200721#define NDT$_TGA 266257#define NDT$_MFPCI 331793#define NDT$_PVIC 397329#define NDT$_ZEPHYR 462865#define NDT$_KZPSA 528401#define NDT$_DC21140 593937#define NDT$_DC21143 1642513#define NDT$_TGA2 856081#define NDT$_PFI 987153#define NDT$_DC21041 1314833#define NDT$_DGLPB 1445905#define NDT$_PVPCI 1511441#define NDT$_PCIRM 1576977#define NDT$_PPB0 2101265#define NDT$_PPB1 21-<66801#define NDT$_PPB2 2232337#define NDT$_PPB3 2363409#define NDT$_PPB4 2428945#define NDT$_PPB5 2494481#define NDT$_DEGPA_SA 70318#define NDT$_DEGPA_TA 135854#define NDT$_DEGXA 380048612#define NDT$_DEGX2_SA 373822692#define NDT$_DEGX2_TA 373888228#define NDT$_CIPCA 106958997#define NDT$_TC4048 84414682#define NDT$_RACORE -2125197073#define NDT$_NCR53C810 69632#define NDT$_NCR53C810A 331776#define NDT$_NCR53C825 200704#define NDT$_KFPSA -2147282944#define .<NDT$_SATURN 75792518#define NDT$_MERCURY 75661446#define NDT$_I82558 304709766#define NDT$_QLOGIC 270536823$#define NDT$_PCMCIA_PD6729 285216787#define NDT$_MYLEX 69737#define NDT$_PCI1280 808586769!#define NDT$_HOT_PLUG -1594421743#define NDT$_MACH32 1096290306#define NDT$_MACH64 1196953602#define NDT$_MACH64C 1129844738#define NDT$_DEC864 -2000661709#define NDT$_S3TRIO -2012130509#define NDT$_METEOR 2101295#define NDT$_FAX_MODEM 5783878#define NDT$_XIRCOM 5128524/<#define NDT$_NCR53C710 1#define NDT$_DC253 2#define NDT$_SCRIPT_RAM 3#define NDT$_DS1287 4#define NDT$_Z85C30 5#define NDT$_EEROM 6#define NDT$_NIADRROM 7#define NDT$_FEPROM 8#define NDT$_PCD8584 9#define NDT$_NCR53C710_DSSI 10#define NDT$_TC_INTERFACE 11#define NDT$_SCSI_INTERFACE 12#define NDT$_CXTURBO 13#define NDT$_COREIO 14#define NDT$_NCR53C94 15#define NDT$_LANCE 16#define NDT$_AMD79C30 17#define NDT$_KA0202_CPU 18#define NDT$_KA0202_MEM 19#define 0<NDT$_KA0202_IO 20#define NDT$_VTI82C106_PP 21#define NDT$_KA0902_CPU 23#define NDT$_KA0902_MEM 24#define NDT$_KA0902_IIO 25#define NDT$_KA0902_EIO 26#define NDT$_KA1605_PCI 27#define NDT$_KA1605_CPU 28#define NDT$_KA1605_MEMORY 29#define NDT$_KA1605_GCD 30#define NDT$_HPC_PCI 541282632#define NDT$_KA2308_QSA 49#define NDT$_KA2308_QSD 50#define NDT$_KA2308_DIR 51#define NDT$_KA2308_IOP 52#define NDT$_KA2308_PCA 53#define NDT$_KA2308_PCI 54#define NDT$_KA2308_GP 551<#define NDT$_KA2308_HS 56#define NDT$_KA2308_MEM 57#define NDT$_KA2308_DTAG 58#define NDT$_KA270F_PCI 59#define NDT$_MCD 4473677$#define NDT$_COREIO_HW_ID_MASK_LO -1##define NDT$_COREIO_HW_ID_MASK_HI 0"#define NDT$_EISA_HW_ID_MASK_LO -1"#define NDT$_EISA_HW_ID_MASK_HI -1&#define NDT$_FBUS_HW_ID_MASK_LO -16384(#define NDT$_FBUS_HW_ID_MASK_HI 16777215"#define NDT$_LBUS_HW_ID_MASK_LO -1!#define NDT$_LBUS_HW_ID_MASK_HI 0!#define NDT$_PCI_HW_ID_MASK_LO -1 #define NDT$_PCI_HW_ID_MASK_2<HI 0$#define NDT$_PCMCIA_HW_ID_MASK_LO -1##define NDT$_PCMCIA_HW_ID_MASK_HI 0##define NDT$_TURBO_HW_ID_MASK_LO -1##define NDT$_TURBO_HW_ID_MASK_HI -1"#define NDT$_XBUS_HW_ID_MASK_LO -1!#define NDT$_XBUS_HW_ID_MASK_HI 0$#define NDT$_XMI_HW_ID_MASK_LO 65535 #define NDT$_XMI_HW_ID_MASK_HI 0'#define NDT$_VTI_COMBO_HW_ID_MASK_LO -1&#define NDT$_VTI_COMBO_HW_ID_MASK_HI 0'#define NDT$_TLASER_HW_ID_MASK_LO 65535##define NDT$_TLASER_HW_ID_MASK_HI 0 $#pragma __member_alignment __restoreR3<#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NDTDEF_LOADED */ ww$[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software 4<is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confiden5<tial **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******* 6<*************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 15-JUN-2005 11:31:28 $1$DGA8345:[LIB_H.SRC]NETUSR.SDL;1 *//********************************************************************************************************************************//*** MODULE $NFBDEF ***/#ifndef __NFBDEF_LOADED#define __NFBDEF_LOADED 1 G#pragma __nostandard /* Thi7<s file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#def8<ine __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */L/* The following generic field identifiers are defined for all databases. */N/* 9< */O#define NFB$C_ENDOFLIST 0 /* Used to terminate the field i.d. */`#define NFB$C_WILDCARD 1 /* Field i.d. used for "match all" database searches */R#define NFB$C_CTX_SIZE 64 /* Length of context area in P2 buffer */N/* */K/* The following codes are passed in the second IOSB longword to qualify */I/* as SS$_ILLCNTRFUNC error. :< */N/* */N/* The high order word of these error codes must be 0 */N/* so that they won't be confused with field i.d.s */N#define NFB$_ERR_FCT 1 /* Unrecognized NFB$B_FCT value. */Q#define NFB$_ERR_DB 2 /* Unrecognized NFB$B_DATABASE value. */N#define NFB$_ERR_P1 3 /* The P1 buffer is ;<invalid. */N#define NFB$_ERR_P2 4 /* The P2 buffer is invalid. */N#define NFB$_ERR_P3 5 /* The P3 buffer is invalid. */N#define NFB$_ERR_P4 6 /* The P4 buffer is invalid. */\#define NFB$_ERR_P5 7 /* The P5 buffer should not have been specified. */\#define NFB$_ERR_P6 8 /* The P6 buffer should not have been specified. */N#define NFB$_ERR_CELL 9 /* Unrecognized NF<<B$B_CELL value. */N#define NFB$_ERR_OPER 10 /* Unrecognized NFB$B_OPER value. */S#define NFB$_ERR_SRCH 11 /* Unrecognized NFB$L_SRCH_KEY field ID */T#define NFB$_ERR_SRCH2 12 /* Unrecognized NFB$L_SRCH2_KEY field ID */N#define NFB$_ERR_OPER2 13 /* Unrecognized NFB$B_OPER2 value. */[#define NFB$_ERR_FLAGS 14 /* Undefined bits in NFB$B_FLAGS were not zero. */N#define NFB$_ERR_LOCK 15 /* Lock was not gr=<anted */N/* */I/* Define the P1 buffer format */N/* */N#define NFB$C_DECLNAME 21 /* Declare name */N#define NFB$C_DECLOBJ 22 /* Declare object */O#define NFB$C_DECLSERV 23 /* Declare server process available */N/* Res><ume defining function codes */N#define NFB$C_LOGEVENT 28 /* Log a network event */^#define NFB$C_READEVENT 29 /* Read current raw event queue (used by EVL only) */N/* Resume defining function codes */R#define NFB$C_FC_DELETE 33 /* Remove an entry from the data base. */N#define NFB$C_FC_SHOW 34 /* Return specified field values. */N#define NFB$?<C_FC_SET 35 /* Set/modify the field values. */N#define NFB$C_FC_CLEAR 36 /* Clear specified field values. */R#define NFB$C_FC_ZERCOU 37 /* Zero (and optionally read) counters */[#define NFB$C_FC_LOOP 38 /* Loop (used only to PSI to loop an X.25 line) */N#define NFB$C_REBUILD_PROXY 39 /* Rebuild the proxy data base */N#define NFB$C_ADD_PROXY 40 /* Add/Modify proxy DB entry */N#define NFB$C_DELETE @<_PROXY 41 /* Remove/Delete proxy access */N/* Maximum FCT value */N#define NFB$C_FC_MAX 41 /* Maximum FCT value */#define NFB$M_ERRUPD 0x1#define NFB$M_MULT 0x2#define NFB$M_NOCTX 0x4#define NFB$M_LOCAL 0x8N#define NFB$C_DB_LNI 1 /* Local node */N#define NFB$C_DB_NDI 2 /* Common nodes */N#define NFB$C_DB_OBI 3 A< /* Network objects */N#define NFB$C_DB_CRI 4 /* Circuits */N#define NFB$C_DB_PLI 5 /* Lines */N#define NFB$C_DB_EFI 6 /* Event logging filters */N#define NFB$C_DB_ESI 7 /* Event logging sinks */N#define NFB$C_DB_LLI 8 /* Logical-links */N#define NFB$C_DB_XNI 9 /* X.25 neB<tworks */N#define NFB$C_DB_XGI 10 /* X.25 groups */N#define NFB$C_DB_XDI 11 /* X.25 DTEs */N#define NFB$C_DB_XS5 12 /* X.25 server */N#define NFB$C_DB_XD5 13 /* X.25 destinations */N#define NFB$C_DB_XS9 14 /* X.29 server */N#define NFB$C_DB_XD9 15 /* X.29 destinations C<*/N#define NFB$C_DB_XTI 16 /* X.25 trace facility */N#define NFB$C_DB_XTT 17 /* X.25 tracepoints */N#define NFB$C_DB_SPI 18 /* Server Process */N#define NFB$C_DB_AJI 19 /* Adjacency information */N#define NFB$C_DB_ARI 20 /* Area information */N/* (The following codes are reserved for future PSIACP */N/* databases. These D<codes should only be used in the */N/* event PSIACP needs a database code before a new */N/* new NETACP can be supplied to support it). */N#define NFB$C_DB_XDTE 21 /* PSI reserved database */N#define NFB$C_DB_PSI2 22 /* PSI reserved database */N#define NFB$C_DB_PSI3 23 /* PSI reserved database */N#define NFB$C_DB_PSI4 24 /* PSI rE<eserved database */N#define NFB$C_DB_PSI5 25 /* PSI reserved database */N#define NFB$C_DB_SDI 26 /* Service (DLE) information */N#define NFB$C_DB_XAI 27 /* X.25 access database */N#define NFB$C_DB_PROXY 28 /* Proxy data base */^#define NFB$C_DB_XXX 29 /* Last database definition for NFB$C_DB_MAX calc. */N/* Maximum DATABASE value F< */N#define NFB$C_DB_MAX 28 /* Maximum DATABASE value */a#define NFB$C_OP_EQL 0 /* Match if SEARCH_KEY value EQL database entry field */b#define NFB$C_OP_GTRU 1 /* Match if SEARCH_KEY value GTRU database entry field */b#define NFB$C_OP_LSSU 2 /* Match if SEARCH_KEY value LSSU database entry field */a#define NFB$C_OP_NEQ 3 /* Match if SEARCH_KEY value NEQ database entry field */N/* TG<he following may only be used internally by NETACP */P#define NFB$C_OP_FNDMIN 4 /* Find entry with minimum key value */P#define NFB$C_OP_FNDMAX 5 /* Find entry with maximum key value */N#define NFB$C_OP_FNDPOS 6 /* Find entry position in database */N/* Maximum operator function */N#define NFB$C_OP_MAXFCT 3 /* Maximum operator function */N#define NFB$C_OP_MAXINT 6 H< /* Maximum internal function */N#define NFB$K_LENGTH 16 /* Minimum structure size. */N#define NFB$C_LENGTH 16 /* Minimum structure size. */N/* counted strings. If the "cell size" is non-zero, it */N#define NFB$S_NFBDEF 20 /* Old size name - synonym */ typedef struct _nfb {N unsigned char nfb$b_fct; /* A function code as follows: */N/* Function codes for th I<e NFB */N/* (leaving room for 20 obsolete function codes) */N/* (leave room for 4 obsolete function codes) */N/* (leave room for 3 obsolete function codes) */ __union {N unsigned char nfb$b_flags; /* Miscellaneous control flags */ __struct {U unsigned nfb$v_errupd : 1; /* Update position context, even on error */\ J< unsigned nfb$v_mult : 1; /* Process as many entries as can be fit into P4 */` unsigned nfb$v_noctx : 1; /* Don't update position context, even if successful */N/* (used to stay on an entry for a while). This */N/* flag Overrides the ERRUPD flag. */V unsigned nfb$v_local : 1; /* Signal that REBUILD_PROXY should only be */N/* performed locally K< */' unsigned nfb$v_fill_0_ : 4; } nfb$r_flags_bits; } nfb$r_flags_overlay;Z unsigned char nfb$b_database; /* A code identifying the database as follows: */N/* ZERO is an illegal value for this field */a unsigned char nfb$b_oper; /* Specifies the sense of the search (e.g. EQL, GEQU) */N/* when comparing against the SRCH_KEY field. */b unsigned int nfb$l_srch_key; L< /* Search key field identifier specifying the key used */N/* to locate the entry in the database. This search is */N/* controlled by the sense of the NFB$B_OPER field. */N/* */N/* If this field has the value "NFB$C_WILDCARD", then */N/* the very next entry in the list is assumed to be the */N/* target of the search. M< */N/* */N/* If this field is not specified (zero), then it */N/* is assumed to be NFB$C_WILDCARD (no search key). */N/* */d unsigned int nfb$l_srch2_key; /* Secondary search key field ID specifying the key used */N/* to locate the entry in the database. This N<search is */N/* controlled by the sense of the NFB$B_OPER2 field. */N/* */N/* If both SRCH_KEY and SRCH2_KEY are specified, then */N/* only those database entries matching both search keys */N/* will be processed. */N/* O< */N/* If this field is not specified (zero), then it */N/* is assumed to be NFB$C_WILDCARD (no search key). */N/* */a unsigned char nfb$b_oper2; /* Specifies the sense of the search (e.g. EQL, GEQU) */N/* when comparing against the SRCH2_KEY field. */N unsigned char nfb$b_mbz1; /* Reserved. MBZ. */P<b unsigned short int nfb$w_cell_size; /* Some of the field values found in the P4 buffer are */N/* indicates the number of bytes which each string in */N/* the P4 buffer occupies. If it is zero then strings */N/* fields are stored as variable lengthed strings. */] unsigned int nfb$l_fldid; /* Cell containing the first field ID -- the list */N/* of field IDs begins here and continues to the Q< */N/* end of the structure. */N/* */N/* The list may be terminated before the end of the */N/* structure by placing the value NFB$C_ENDOFLIST */N/* in the longword following the last field ID. */N/* */N/* R< */I/* Define the "field i.d." format. */N/* */ } NFB; #if !defined(__VAXC)3#define nfb$b_flags nfb$r_flags_overlay.nfb$b_flagsF#define nfb$v_errupd nfb$r_flags_overlay.nfb$r_flags_bits.nfb$v_errupdB#define nfb$v_mult nfb$r_flags_overlay.nfb$r_flags_bits.nfb$v_multD#define nfb$v_noctx nfb$r_flags_overlay.nfb$r_flags_ S<bits.nfb$v_noctxD#define nfb$v_local nfb$r_flags_overlay.nfb$r_flags_bits.nfb$v_local"#endif /* #if !defined(__VAXC) */ #define NFB$M_INX 0xFFFF#define NFB$M_TYP 0x30000#define NFB$M_SPARE 0xFC0000#define NFB$M_DB 0xFF000000N#define NFB$C_TYP_BIT 0 /* Field type for bits */N#define NFB$C_TYP_V 0 /* Field type for bits */N#define NFB$C_TYP_LNG 1 /* Field type for longwords */N#define NFB$C_TYP_L 1 T< /* Field type for longwords */N#define NFB$C_TYP_STR 2 /* Field type for strings */N#define NFB$C_TYP_S 2 /* Field type for strings */N/* */I#define NFB$S_NFBDEF1 4 /* Old size name - synonym */ typedef struct _nfb1 { __union {N unsigned int nfb$l_param_id; /* Define parameter ID longword */ __U<struct {N unsigned nfb$v_inx : 16; /* Index into semantic table */N unsigned nfb$v_typ : 2; /* Field type (string, bit, etc.) */N unsigned nfb$v_spare : 6; /* Reserved, MBZ */N unsigned nfb$v_db : 8; /* Data-base i.d. */" } nfb$r_param_id_bits;N/* Define useful symbols for storing and retreiving binary and string */N/* values from the P2 and P4 buffers V< */N/* */! } nfb$r_param_id_overlay; } NFB1; #if !defined(__VAXC)<#define nfb$l_param_id nfb$r_param_id_overlay.nfb$l_param_idF#define nfb$v_inx nfb$r_param_id_overlay.nfb$r_param_id_bits.nfb$v_inxF#define nfb$v_typ nfb$r_param_id_overlay.nfb$r_param_id_bits.nfb$v_typJ#define nfb$v_spare nfb$r_param_id_overlay.nfb$r_param_id_bits.nfb$v_spareD#define nfb$v_db nfb$r_param_id_overlay.nfb$r_W<param_id_bits.nfb$v_db"#endif /* #if !defined(__VAXC) */ N#define NFB$S_NFBDEF2 4 /* old size name - synonym */ typedef struct _nfb2 {N unsigned int nfb$l_lng_value; /* Longword value */ } NFB2;N#define NFB$S_NFBDEF3 4 /* old size name - synonym */ typedef struct _nfb3 {N unsigned int nfb$l_bit_value; /* Boolean value */ } NFB3;d#define NFB$C_NDI_LCK 33554433 X< /* Set if conditionally writable fields are not writable */R#define NFB$C_NDI_LOO 33554434 /* Set if CNF is for a "loopback" node */N#define NFB$C_NDI_REA 33554435 /* Set if node is reachable */N/* */^#define NFB$C_NDI_TAD 33619984 /* "transformed address" - uses local node address */N/* for the local NDI (instead of zero as does ADD) */U#define NFB$C_NDI_CTA Y<33619985 /* Absolute due time for logging counters */N#define NFB$C_NDI_ADD 33619986 /* Address */N#define NFB$C_NDI_CTI 33619987 /* Counter timer */N#define NFB$C_NDI_ACL 33619988 /* Active links */N#define NFB$C_NDI_DEL 33619989 /* Delay */N#define NFB$C_NDI_DTY 33619990 /* Destination Type */N#define NFB$C_NDI_DCO 33619991 Z</* Destination Cost */N#define NFB$C_NDI_DHO 33619992 /* Destination Hops */N#define NFB$C_NDI_SDV 33619993 /* Service Device */N#define NFB$C_NDI_CPU 33619994 /* CPU type */N#define NFB$C_NDI_STY 33619995 /* Software type */N#define NFB$C_NDI_DAD 33619996 /* Dump address */N#define NFB$C_NDI_DCT 33619997 /* Dump count [< */N#define NFB$C_NDI_OHO 33619998 /* Host */N#define NFB$C_NDI_IHO 33619999 /* Host */U#define NFB$C_NDI_ACC 33620000 /* Access switch (inbound, outbound, etc) */T#define NFB$C_NDI_PRX 33620001 /* ** obsolete ** (Node proxy parameter) */N#define NFB$C_NDI_NND 33620002 /* Next node address */N#define NFB$C_NDI_SNV 33620003 /* Service Node Version */\<N#define NFB$C_NDI_INB 33620004 /* Async Line - Inbound node type */N/* */N#define NFB$C_NDI_COL 33685568 /* Collating field */U#define NFB$C_NDI_HAC 33685569 /* Node address/loop linename combination */N#define NFB$C_NDI_CNT 33685570 /* Counters */N#define NFB$C_NDI_NNA 33685571 /* Name */N#define NFB$C_ND]<I_SLI 33685572 /* Service line */N#define NFB$C_NDI_SPA 33685573 /* Service password */N#define NFB$C_NDI_LOA 33685574 /* Load file */N#define NFB$C_NDI_SLO 33685575 /* Secondary loader */N#define NFB$C_NDI_TLO 33685576 /* Tertiary loader */N#define NFB$C_NDI_SID 33685577 /* Software ID */N#define NFB$C_NDI_DUM 33685578 /*^< Dump file */N#define NFB$C_NDI_SDU 33685579 /* Secondary dumper */N#define NFB$C_NDI_NLI 33685580 /* Loopback Line */N#define NFB$C_NDI_DLI 33685581 /* Destination Line */N#define NFB$C_NDI_PUS 33685582 /* Privileged user id */N#define NFB$C_NDI_PAC 33685583 /* Privileged account */N#define NFB$C_NDI_PPW 33685584 /* Privileged password _< */N#define NFB$C_NDI_NUS 33685585 /* Non-privileged user id */N#define NFB$C_NDI_NAC 33685586 /* Non-privileged account */N#define NFB$C_NDI_NPW 33685587 /* Non-privileged password */N#define NFB$C_NDI_RPA 33685588 /* Receive password */N#define NFB$C_NDI_TPA 33685589 /* Transmit password */N#define NFB$C_NDI_DFL 33685590 /* Diagnostic load file */P#define NFB$C_`<NDI_HWA 33685591 /* Hardware NI address (ROM address) */N#define NFB$C_NDI_LPA 33685592 /* Loop assistant NI address */\#define NFB$C_NDI_NNN 33685593 /* Next node name to destination (goes with NND) */N#define NFB$C_NDI_LAA 33685594 /* Load Assist Agent */N#define NFB$C_NDI_LAP 33685595 /* Load Assist Parameter */N#define NFB$C_NDI_MFL 33685596 /* Management File */N/* a< */d#define NFB$C_LNI_LCK 16777217 /* Set if conditionally writable fields are not writable */S#define NFB$C_LNI_ALI 16777218 /* Set if ALIAS INBOUND has been enabled */N#define NFB$C_LNI_IPR 16777219 /* Incoming proxy enabled/disabled */N#define NFB$C_LNI_OPR 16777220 /* Outgoing proxy enabled/disabled */N#define NFB$C_LNI_DNS 16777221 /* DNS interface enabled/disabled */N/* b< */N#define NFB$C_LNI_ADD 16842768 /* Address */N#define NFB$C_LNI_ACL 16842769 /* Total number of active links */N#define NFB$C_LNI_ITI 16842770 /* Incoming timer */N#define NFB$C_LNI_OTI 16842771 /* Outgoing timer */N#define NFB$C_LNI_STA 16842772 /* State */N#define NFB$C_LNI_MLK 16842773 /* Maximc<um links */N#define NFB$C_LNI_DFA 16842774 /* Delay factor */N#define NFB$C_LNI_DWE 16842775 /* Delay weight */N#define NFB$C_LNI_IAT 16842776 /* Inactivity timer */N#define NFB$C_LNI_RFA 16842777 /* Retransmit factor */N#define NFB$C_LNI_ETY 16842778 /* Executor Type */N#define NFB$C_LNI_RTI 16842779 /* Routing timer d< */N#define NFB$C_LNI_RSI 16842780 /* Routing suppression timer */N#define NFB$C_LNI_SAD 16842781 /* Subaddress */N/* (lower word = lower limit, upper word = upper limit) */N#define NFB$C_LNI_MAD 16842782 /* Maximum address */N#define NFB$C_LNI_MLN 16842783 /* Maximum lines */N#define NFB$C_LNI_MCO 16842784 /* Maximum cost */N#define NFB$C_LNI_MHe<O 16842785 /* Maximum hops */N#define NFB$C_LNI_MVI 16842786 /* Maximum visits */N#define NFB$C_LNI_MBU 16842787 /* Maximum buffers */N#define NFB$C_LNI_BUS 16842788 /* Forwarding buffer size */N#define NFB$C_LNI_LPC 16842789 /* Loop count */N#define NFB$C_LNI_LPL 16842790 /* Loop length */N#define NFB$C_LNI_LPD 16842791 /* Loof<p Data type */]#define NFB$C_LNI_DAC 16842792 /* Default access switch (inbound, outbound, etc) */u#define NFB$C_LNI_FILL1 16842793 /* Place holder, used to be Default proxy access (inbound, outbound, etc) */N#define NFB$C_LNI_PIQ 16842794 /* Pipeline quota */d#define NFB$C_LNI_LPH 16842795 /* Loop help type of assistance given to loop requestors */N#define NFB$C_LNI_BRT 16842796 /* Broadcast routing timer g< */N#define NFB$C_LNI_MAR 16842797 /* Maximum areas */N#define NFB$C_LNI_MBE 16842798 /* Maximum nonrouters on NI */N#define NFB$C_LNI_MBR 16842799 /* Maximum routers on NI */N#define NFB$C_LNI_AMC 16842800 /* Area maximum cost */N#define NFB$C_LNI_AMH 16842801 /* Area maximum hops */N#define NFB$C_LNI_SBS 16842802 /* Segment buffer size */Y#define NFB$C_LNI_ALh<A 16842803 /* Alias local node address (cluster address) */N#define NFB$C_LNI_ALM 16842804 /* Alias maximum links */N#define NFB$C_LNI_PSP 16842805 /* Path split policy normal/interim */N#define NFB$C_LNI_MPS 16842806 /* Maximum path split */N#define NFB$C_LNI_MDO 16842807 /* Maximum Declared Object */N/* */N#define NFB$C_LNI_COL 16908352 i< /* Collating field */N#define NFB$C_LNI_NAM 16908353 /* Local node name */N#define NFB$C_LNI_CNT 16908354 /* Counters */N#define NFB$C_LNI_IDE 16908355 /* Identification */N#define NFB$C_LNI_MVE 16908356 /* Management version */N#define NFB$C_LNI_NVE 16908357 /* Nsp version */N#define NFB$C_LNI_RVE 16908358 /* Routing version j< */S#define NFB$C_LNI_PHA 16908359 /* Physical NI address (current address) */N#define NFB$C_LNI_IDP 16908360 /* IDP of ISO address */N#define NFB$C_LNI_DNM 16908361 /* DNS namespace */N/* */d#define NFB$C_OBI_LCK 50331649 /* Set if conditionally writable fields are not writable */_#define NFB$C_OBI_SET 50331650 /* Set if a "set" k<QIO has ever modified the CNF. If */N/* not then the CNF was due to a "declare name/obect" */N/* only and may be deleted when the declaring process */N/* breaks the channel over which the object was declared */N#define NFB$C_OBI_ALO 50331651 /* Alias Outgoing enabled/disabled */N#define NFB$C_OBI_ALI 50331652 /* Alias Incoming enabled/disabled */N/* l< */N#define NFB$C_OBI_LPR 50397200 /* Low order privileges */N#define NFB$C_OBI_HPR 50397201 /* High order privileges */N#define NFB$C_OBI_DOV 50397202 /* Point to Owners UCB */N#define NFB$C_OBI_CHN 50397203 /* Owner's channel */N#define NFB$C_OBI_NUM 50397204 /* Number */N#define NFB$C_OBI_PID 50397205 /* Process id */Z#define NFB$m<C_OBI_PRX 50397206 /* Proxy login switch (inbound, outbound, etc) */N/* */N#define NFB$C_OBI_COL 50462784 /* Collating field */N#define NFB$C_OBI_ZNA 50462785 /* Zero obj+name identifier */N#define NFB$C_OBI_SFI 50462786 /* Parsed file i.d. */]#define NFB$C_OBI_IAC 50462787 /* Default inbound combined access control string */N#define NFn<B$C_OBI_NAM 50462788 /* Name */N#define NFB$C_OBI_FID 50462789 /* File id */N#define NFB$C_OBI_USR 50462790 /* User id */N#define NFB$C_OBI_ACC 50462791 /* Account */N#define NFB$C_OBI_PSW 50462792 /* Password */N#define NFB$C_OBI_OCPRV 50462793 /* Outgoing Connect Privileges */N/* o< */Y#define NFB$C_CRI_LCK 67108865 /* D Set if conditionally writable fields are */I/* not writable */U#define NFB$C_CRI_SER 67108866 /* D Set if Service functions not allowed */N#define NFB$C_CRI_BLK_FILL 67108867 /* Filler (BLK retired) */N#define NFB$C_CRI_VER_FILL 67108868 /* Filler (VER retired) */\#define NFB$C_CRI_DLM 67108869 /* E Cp<ircuit to be used as X.25 datalink, if set */I/* If clear, circuit is for X.25 native use */[#define NFB$C_CRI_OWPID 67174416 /* D PID of temp owner of line in service state */V#define NFB$C_CRI_CTA 67174417 /* D Absolute due time for counter logging */N#define NFB$C_CRI_SRV 67174418 /* D Service substate qualifier */N#define NFB$C_CRI_STA 67174419 /* C State */N#define NFB$C_CRI_SUB 67174420 q</* C Substate */N#define NFB$C_CRI_LCT 67174421 /* C Counter timer */N#define NFB$C_CRI_PNA 67174422 /* E Adjacent node address */N#define NFB$C_CRI_BLO 67174423 /* E Partner's receive block size */N#define NFB$C_CRI_COS 67174424 /* E Cost */N#define NFB$C_CRI_HET 67174425 /* E Hello timer */N#define NFB$C_CRI_LIT 67174426 /* E Listen timer r< */N#define NFB$C_CRI_MRC 67174427 /* E Maximum recalls */N#define NFB$C_CRI_RCT 67174428 /* E Recall timer */N#define NFB$C_CRI_POL 67174429 /* D Polling state */N#define NFB$C_CRI_PLS 67174430 /* D Polling substate */N#define NFB$C_CRI_USE 67174431 /* X Usage */N#define NFB$C_CRI_TYP 67174432 /* C Type */N#define NFB$s<C_CRI_CHN 67174433 /* X X.25 Channel */N#define NFB$C_CRI_MBL 67174434 /* X Maximum block */N#define NFB$C_CRI_MWI 67174435 /* X Maximum window */N#define NFB$C_CRI_TRI 67174436 /* D Tributary */N#define NFB$C_CRI_BBT 67174437 /* D Babble timer */N#define NFB$C_CRI_TRT 67174438 /* D Transmit timer */N#define NFB$C_CRI_MRB 67174439 t< /* D Maximum receive buffers */N#define NFB$C_CRI_MTR 67174440 /* D Maximum transmits */N#define NFB$C_CRI_ACB 67174441 /* D Active base */N#define NFB$C_CRI_ACI 67174442 /* D Active increment */N#define NFB$C_CRI_IAB 67174443 /* D Inactive base */N#define NFB$C_CRI_IAI 67174444 /* D Inactive increment */N#define NFB$C_CRI_IAT 67174445 /* D Inactive threshold u< */N#define NFB$C_CRI_DYB 67174446 /* D Dying base */N#define NFB$C_CRI_DYI 67174447 /* D Dying increment */N#define NFB$C_CRI_DYT 67174448 /* D Dying threshold */N#define NFB$C_CRI_DTH 67174449 /* D Dead threshold */[#define NFB$C_CRI_MST 67174450 /* D Maintenance mode state (0 => On, 1 => Off> */N#define NFB$C_CRI_XPT 67174451 /* E Transport protocol to use v<*/N#define NFB$C_CRI_MRT 67174452 /* E Maximum routers on this NI */N#define NFB$C_CRI_RPR 67174453 /* E Router priority */W#define NFB$C_CRI_DRT 67174454 /* E Designated router on NI (node address) */`#define NFB$C_CRI_VER 67174455 /* D Verification Enabled/Disabled/Inbound on circuit */N/* */N#define NFB$C_CRI_COL 67240000 /* D Collating field w< */N#define NFB$C_CRI_NAM 67240001 /* C Circuit name */N#define NFB$C_CRI_VMSNAM 67240002 /* D Device name in VMS format */_#define NFB$C_CRI_CHR 67240003 /* D Characteristics buffer for startup control QIO */N#define NFB$C_CRI_CNT 67240004 /* C Counters */[#define NFB$C_CRI_P2P 67240005 /* D Line's PhaseII partner name (for loopback) */N#define NFB$C_CRI_LOO 67240006 /* E Loopback name x< */N#define NFB$C_CRI_PNN 67240007 /* E Adjacent node name */N#define NFB$C_CRI_NUM 67240008 /* X Call Number */N#define NFB$C_CRI_DTE 67240009 /* X DTE */^#define NFB$C_CRI_DEVNAM 67240010 /* D Device name in VMS format, with unit included */N#define NFB$C_CRI_NET 67240011 /* XD Network name */N/* */y<Y#define NFB$C_PLI_LCK 83886081 /* D Set if conditionally writable fields are */I/* not writable */N#define NFB$C_PLI_SER 83886082 /* D Service */N#define NFB$C_PLI_DUP 83886083 /* C Duplex (set if half) */N#define NFB$C_PLI_CON 83886084 /* C Controller (set if loopback) */N#define NFB$C_PLI_CLO 83886085 /* C Clock mode (set if internal) */N#define NFB$C_PLz<I_SWI 83886086 /* D Async Line - Switch */N#define NFB$C_PLI_HNG 83886087 /* D Async Line - Hangup */N/* */Y#define NFB$C_PLI_CTA 83951632 /* D Absolute time for counter read and clear */N#define NFB$C_PLI_STA 83951633 /* C State */N#define NFB$C_PLI_SUB 83951634 /* C Substate */N#define NFB$C_PLI_LCT 83951635{< /* D Counter timer */N#define NFB$C_PLI_PRO 83951636 /* C Protocol */N#define NFB$C_PLI_STI 83951637 /* D Service timer */N#define NFB$C_PLI_HTI 83951638 /* L Holdback timer */N#define NFB$C_PLI_MBL 83951639 /* L Maximum block */N#define NFB$C_PLI_MRT 83951640 /* L Maximum retransmits */N#define NFB$C_PLI_MWI 83951641 /* L Maximum win|<dow */N#define NFB$C_PLI_SLT 83951642 /* D Scheduling timer */N#define NFB$C_PLI_DDT 83951643 /* D Dead timer */N#define NFB$C_PLI_DLT 83951644 /* D Delay timer */N#define NFB$C_PLI_SRT 83951645 /* D Stream timer */N#define NFB$C_PLI_BFN 83951646 /* D Receive buffers */\#define NFB$C_PLI_BUS 83951647 /* D Action routine returns bufsiz used fo}<r line */N#define NFB$C_PLI_PLVEC 83951648 /* D PLVEC i.d. */N#define NFB$C_PLI_RTT 83951649 /* D Retransmit timer */N#define NFB$C_PLI_MOD 83951650 /* L X.25 mode (DCE, DTE, etc). */N#define NFB$C_PLI_LPC 83951651 /* L Loop count */N#define NFB$C_PLI_LPL 83951652 /* L Loop length */N#define NFB$C_PLI_LPD 83951653 /* L Loop Data type */T#define NFB$C_~<PLI_EPT 83951654 /* E Ethernet protocol type for datalink */N#define NFB$C_PLI_LNS 83951655 /* D Async Line - Line speed */]#define NFB$C_PLI_BFS 83951656 /* C Line buffer size (overrides executor bufsiz) */N#define NFB$C_PLI_TPI 83951657 /* D Transmit Pipeline */N#define NFB$C_PLI_TREQ 83951658 /* F Requested TRT */N#define NFB$C_PLI_TVX 83951659 /* F Valid transmission time */N#define NFB$C_PLI_<REST_TTO 83951660 /* F Restricted token timeout */N#define NFB$C_PLI_RPE 83951661 /* F Ring purger enable */N#define NFB$C_PLI_ECHO_DAT 83951662 /* F Echo data */N#define NFB$C_PLI_ECHO_LEN 83951663 /* F Echo length */N#define NFB$C_PLI_T_NEG 83951664 /* F Negotiated TRT */N#define NFB$C_PLI_DAT 83951665 /* F Duplicate address flag */N#define NFB$C_PLI_UN_DAT 83951666 /* F< Upstream neighbor DA flag */N#define NFB$C_PLI_RPS 83951667 /* F Ring purger state */N#define NFB$C_PLI_RER 83951668 /* F Ring error reason */N#define NFB$C_PLI_NBR_PHY 83951669 /* F Neighbor PHY type */N#define NFB$C_PLI_LEE 83951670 /* F Link error estimate */N#define NFB$C_PLI_RJR 83951671 /* F Reject reason */N/* < */N#define NFB$C_PLI_COL 84017216 /* D Collating field */N#define NFB$C_PLI_NAM 84017217 /* C Line name */N#define NFB$C_PLI_VMSNAM 84017218 /* D Device name in VMS format */Z#define NFB$C_PLI_CHR 84017219 /* D Set-mode $QIO line Characteristics buffer */N#define NFB$C_PLI_CNT 84017220 /* C Counters */]#define NFB$C_PLI_MCD 84017221 /* L Filespec for microcode dump (initiates <dump) */R#define NFB$C_PLI_HWA 84017222 /* D NI hardware address (ROM address) */^#define NFB$C_PLI_DEVNAM 84017223 /* D Device name in VMS format, with unit included */N#define NFB$C_PLI_NET 84017224 /* L Network name */N#define NFB$C_PLI_NIF_TARG 84017225 /* F NIF target */N#define NFB$C_PLI_SIF_CONF_TARG 84017226 /* F SIF configuration target */N#define NFB$C_PLI_SIF_OP_TARG 84017227 /* F SIF operation target < */N#define NFB$C_PLI_ECHO_TARG 84017228 /* F Echo target */]#define NFB$C_PLI_MAC_CHR 84017229 /* F Set-mode $QIO MAC line characteristics buffer */N#define NFB$C_PLI_UNA 84017230 /* F Upstream neighbor */N#define NFB$C_PLI_OLD_UNA 84017231 /* F Old upstream neighbor */N#define NFB$C_PLI_DNA 84017232 /* F Downstream neighbor */N#define NFB$C_PLI_OLD_DNA 84017233 /* F Old downstream neighbor */N/* < */d#define NFB$C_EFI_LCK 100663297 /* Set if conditionally writable fields are not writable */N/* */#define NFB$C_EFI_SIN 100728848#define NFB$C_EFI_SP1 100728849#define NFB$C_EFI_B1 100728850#define NFB$C_EFI_B2 100728851N/* */N#define NFB$C_EFI_COL 100794432 < /* Collating field */#define NFB$C_EFI_EVE 100794433#define NFB$C_EFI_SB1 100794434#define NFB$C_EFI_SB2 100794435#define NFB$C_EFI_SB3 100794436N/* */d#define NFB$C_ESI_LCK 117440513 /* Set if conditionally writable fields are not writable */N/* */#define NFB$C_ESI_SNK 117506064#define NFB$C_ESI_STA 11750606 <5#define NFB$C_ESI_SP1 117506066#define NFB$C_ESI_B1 117506067#define NFB$C_ESI_B2 117506068N/* */N#define NFB$C_ESI_COL 117571648 /* Collating field */#define NFB$C_ESI_LNA 117571649#define NFB$C_ESI_SB1 117571650#define NFB$C_ESI_SB2 117571651#define NFB$C_ESI_SB3 117571652N/* */d#define NFB$C_LLI_LCK 134217<729 /* Set if conditionally writable fields are not writable */N/* */N#define NFB$C_LLI_DLY 134283280 /* Round trip delay time */N#define NFB$C_LLI_STA 134283281 /* State */N#define NFB$C_LLI_LLN 134283282 /* Local link number */N#define NFB$C_LLI_RLN 134283283 /* Remote link number */N#define NFB$C_LLI_PNA 134283284 < /* Partner's node address */N#define NFB$C_LLI_PID 134283285 /* External Process I.D. */N#define NFB$C_LLI_IPID 134283286 /* Internal Process I.D. */N#define NFB$C_LLI_XWB 134283287 /* Pointer to XWB */N#define NFB$C_LLI_CNT 134283288 /* Counters */N/* */N#define NFB$C_LLI_COL 134348864 /* Collating field< */N#define NFB$C_LLI_USR 134348865 /* User name */N#define NFB$C_LLI_PRC 134348866 /* Process name */N#define NFB$C_LLI_PNN 134348867 /* Partner's node name */N#define NFB$C_LLI_RID 134348868 /* Partner's process i.d. */N/* */d#define NFB$C_XNI_LCK 150994945 /* Set if conditionally writable fields are <not writable */j#define NFB$C_XNI_MNS_FILL 150994946 /* X.25 multi-network support (set if enabled) [No longer used] */N/* */N#define NFB$C_XNI_CAT 151060496 /* Call timer */N#define NFB$C_XNI_CLT 151060497 /* Clear timer */N#define NFB$C_XNI_DBL 151060498 /* Default data */N#define NFB$C_XNI_DWI 151060499 /* Default window < */N#define NFB$C_XNI_MBL 151060500 /* Maximum data */N#define NFB$C_XNI_MCL 151060501 /* Maximum clears */N#define NFB$C_XNI_MRS 151060502 /* Maximum resets */N#define NFB$C_XNI_MST 151060503 /* Maximum restarts */N#define NFB$C_XNI_MWI 151060504 /* Maximum window */N#define NFB$C_XNI_RST 151060505 /* Reset timer */N#defin<e NFB$C_XNI_STT 151060506 /* Restart timer */N/* */N#define NFB$C_XNI_COL 151126080 /* Collating field */N#define NFB$C_XNI_NETENT 151126081 /* Network */N#define NFB$C_XNI_PROF 151126082 /* Profile name */N/* */d#define NFB$C_XDI_LCK 184549377 < /* Set if conditionally writable fields are not writable */N/* */N#define NFB$C_XDI_ACH 184614928 /* Active channels */N#define NFB$C_XDI_ASW 184614929 /* Active switched */N#define NFB$C_XDI_CTM 184614930 /* Counter timer */N#define NFB$C_XDI_MCH 184614931 /* Maximum channels */N#define NFB$C_XDI_STA 184614932 < /* State */N#define NFB$C_XDI_SUB 184614933 /* Substate */N#define NFB$C_XDI_MCI 184614934 /* Maximum circuits [VMS only] */N#define NFB$C_XDI_CAT 184614935 /* Call timer */N#define NFB$C_XDI_CLT 184614936 /* Clear timer */N#define NFB$C_XDI_DBL 184614937 /* Default data */N#define NFB$C_XDI_DWI 184614938 /* Default window < */N#define NFB$C_XDI_MBL 184614939 /* Maximum data */N#define NFB$C_XDI_MCL 184614940 /* Maximum clears */N#define NFB$C_XDI_MRS 184614941 /* Maximum resets */N#define NFB$C_XDI_MST 184614942 /* Maximum restarts */N#define NFB$C_XDI_MWI 184614943 /* Maximum window */N#define NFB$C_XDI_RST 184614944 /* Reset timer */N#define <NFB$C_XDI_STT 184614945 /* Restart timer */N#define NFB$C_XDI_MODE 184614946 /* DTE Mode */N#define NFB$C_XDI_ITT 184614947 /* Interrupt timer */N/* */N#define NFB$C_XDI_COL 184680512 /* Collating field */N#define NFB$C_XDI_DTE 184680513 /* DTE address */N#define NFB$C_XDI_CHN 184680514 < /* Channels */N#define NFB$C_XDI_LIN 184680515 /* Line */N#define NFB$C_XDI_DNT 184680516 /* Network */N#define NFB$C_XDI_CNT 184680517 /* Counters */N/* */d#define NFB$C_XGI_LCK 167772161 /* Set if conditionally writable fields are not writable */N/* < */N#define NFB$C_XGI_GNM 167837712 /* Group number */N#define NFB$C_XGI_GTY 167837713 /* Group type */N/* */`#define NFB$C_XGI_COL 167903296 /* Collating field. This field must be unique across */N/* all entries in this database. It consists of the */N/* group-name string followed by the DTE addre<ss. */N#define NFB$C_XGI_GRP 167903297 /* Group name */N#define NFB$C_XGI_GDT 167903298 /* Group DTE address */N#define NFB$C_XGI_GNT 167903299 /* Group Network */N/* */d#define NFB$C_XS5_LCK 201326593 /* Set if conditionally writable fields are not writable */N/* < */N#define NFB$C_XS5_MCI 201392144 /* Maximum circuits allowed */N#define NFB$C_XS5_STA 201392145 /* State */N#define NFB$C_XS5_ACI 201392146 /* Active circuits */N#define NFB$C_XS5_CTM 201392147 /* Counter timer */N/* */`#define NFB$C_XS5_COL 201457728 /* Collating field. This field must <be unique across */N/* all entries in this database. */N#define NFB$C_XS5_CNT 201457729 /* Counters */N/* */d#define NFB$C_XD5_LCK 218103809 /* Set if conditionally writable fields are not writable */N/* */N#define NFB$C_XD5_PRI 218169360 /* Priority < */N#define NFB$C_XD5_SAD 218169361 /* Subaddress range */N/* (lower word = lower limit, upper word = upper limit) */d#define NFB$C_XD5_NOD 218169362 /* Remote node address containing server (gateways only) */N#define NFB$C_XD5_RED 218169363 /* Redirect reason */N/* */`#define NFB$C_XD5_COL 218234944 /* Collating field. This f<ield must be unique across */N/* all entries in this database. */N#define NFB$C_XD5_DST 218234945 /* Destination DTE address */N#define NFB$C_XD5_CMK 218234946 /* Call mask */N#define NFB$C_XD5_CVL 218234947 /* Call value */N#define NFB$C_XD5_GRP 218234948 /* Group name */S#define NFB$C_XD5_SDTE 218234949 /* Sending DTE address (formally n<umber) */N#define NFB$C_XD5_OBJ 218234950 /* && Object name */`#define NFB$C_XD5_FIL 218234951 /* Command procedure to execute when starting object */N#define NFB$C_XD5_USR 218234952 /* User name */N#define NFB$C_XD5_PSW 218234953 /* Password */N#define NFB$C_XD5_ACC 218234954 /* Account */N#define NFB$C_XD5_CDTE 218234955 /* Called DTE <*/N#define NFB$C_XD5_RDTE 218234956 /* Receiving DTE */N#define NFB$C_XD5_NET 218234957 /* Network */N#define NFB$C_XD5_EMK 218234958 /* Extension mask */N#define NFB$C_XD5_EVL 218234959 /* Extension value */X#define NFB$C_XD5_ACL 218234960 /* ACL, a list of ACE'structure, parto of ORB */N#define NFB$C_XD5_IDTE 218234961 /* Incoming address */N/* < */d#define NFB$C_XS9_LCK 234881025 /* Set if conditionally writable fields are not writable */N/* */N#define NFB$C_XS9_MCI 234946576 /* Maximum circuits allowed */N#define NFB$C_XS9_STA 234946577 /* State */N#define NFB$C_XS9_ACI 234946578 /* Active circuits */N#define NFB$C_XS<9_CTM 234946579 /* Counter timer */N/* */`#define NFB$C_XS9_COL 235012160 /* Collating field. This field must be unique across */N/* all entries in this database. */N#define NFB$C_XS9_CNT 235012161 /* Counters */N/* */d#define NFB$C_XD9_LCK 25<1658241 /* Set if conditionally writable fields are not writable */N/* */N#define NFB$C_XD9_PRI 251723792 /* Priority */N#define NFB$C_XD9_SAD 251723793 /* Subaddress range */N/* (lower word = lower limit, upper word = upper limit) */d#define NFB$C_XD9_NOD 251723794 /* Remote node address containing server (gateways only) */N#defin<e NFB$C_XD9_RED 251723795 /* Redirect reason */N/* */`#define NFB$C_XD9_COL 251789376 /* Collating field. This field must be unique across */N/* all entries in this database. */N#define NFB$C_XD9_DST 251789377 /* Destination DTE address */N#define NFB$C_XD9_CMK 251789378 /* Call mask */N#define NFB$C_<XD9_CVL 251789379 /* Call value */N#define NFB$C_XD9_GRP 251789380 /* Group name */N#define NFB$C_XD9_SDTE 251789381 /* Sending DTE */N#define NFB$C_XD9_OBJ 251789382 /* && Object name */`#define NFB$C_XD9_FIL 251789383 /* Command procedure to execute when starting object */N#define NFB$C_XD9_USR 251789384 /* User name */N#define NFB$C_XD9_PSW <251789385 /* Password */N#define NFB$C_XD9_ACC 251789386 /* Account */N#define NFB$C_XD9_CDTE 251789387 /* Caller DTE */N#define NFB$C_XD9_RDTE 251789388 /* Receiving DTE */N#define NFB$C_XD9_NET 251789389 /* Network */N#define NFB$C_XD9_EMK 251789390 /* Extension mask */N#define NFB$C_XD9_EVL 251789391 /* Exten<sion value */X#define NFB$C_XD9_ACL 251789392 /* ACL, a list of ACE'structure, parto of ORB */N#define NFB$C_XD9_IDTE 251789393 /* Incoming address */N/* */d#define NFB$C_XTI_LCK 268435457 /* Set if conditionally writable fields are not writable */N/* */N#define NFB$C_XTI_STA 268501008 /*< State */N#define NFB$C_XTI_BFZ 268501009 /* Buffer size */N#define NFB$C_XTI_CPL 268501010 /* Capture limit */N#define NFB$C_XTI_MBK 268501011 /* Maximum blocks/file */N#define NFB$C_XTI_MBF 268501012 /* Maximum number of buffers */P#define NFB$C_XTI_MVR 268501013 /* Maximum trace file version number */N/* < */`#define NFB$C_XTI_COL 268566592 /* Collating field. This field must be unique across */N/* all entries in this database. */N#define NFB$C_XTI_FNM 268566593 /* Trace file name */N/* */d#define NFB$C_XTT_LCK 285212673 /* Set if conditionally writable fields are not writable */N/* < */N#define NFB$C_XTT_TST 285278224 /* State */N#define NFB$C_XTT_CPS 285278225 /* Capture size */N/* */`#define NFB$C_XTT_COL 285343808 /* Collating field. This field must be unique across */N/* all entries in this database. */N#define NFB$C_XTT_TPT 285343809 /* Tracepoint name < */N/* */d#define NFB$C_XAI_LCK 452984833 /* Set if conditionally writable fields are not writable */N/* */N#define NFB$C_XAI_NDA 453050384 /* Node address */N/* */N#define NFB$C_XAI_COL 453115968 /* Collating field < */N#define NFB$C_XAI_NET 453115969 /* Network */N#define NFB$C_XAI_USR 453115970 /* User id */N#define NFB$C_XAI_PSW 453115971 /* Password */N#define NFB$C_XAI_ACC 453115972 /* Account */N#define NFB$C_XAI_NOD 453115973 /* Node id */N/* */c#define NF<B$C_XDTE_LCK 352321537 /* Set if conditionally writable fields are not writable */N/* C(,$C_XDTE_,(((NFB$C_DB_XDTE@24)+(NFB$C_TYP_LNG@16)+16)),1 */N#define NFB$C_XDTE_COL 352452672 /* Collating field */N#define NFB$C_XDTE_NET 352452673 /* Network */N#define NFB$C_XDTE_DTE 352452674 /* DTE address */N#define NFB$C_XDTE_ID 352452675 /* ID list, ARB rights list */O#define NFB$C_<XDTE_ACL 352452676 /* ACL, a list of ACE's, part of ORB */N/* */d#define NFB$C_SPI_LCK 301989889 /* Set if conditionally writable fields are not writable */`#define NFB$C_SPI_PRL 301989890 /* Proxy flag which initially started server process */N/* */N#define NFB$C_SPI_PID 302055440 /* Server PID */<`#define NFB$C_SPI_IRP 302055441 /* IRP of waiting DECLSERV QIO (0 if process active) */S#define NFB$C_SPI_CHN 302055442 /* Channel associated with DECLSERV IRP */a#define NFB$C_SPI_RNA 302055443 /* Remote node address which initially started server */N/* */N#define NFB$C_SPI_COL 302121024 /* Collating field */X#define NFB$C_SPI_ACS 302121025 /* ACS used to inita<lly start server process */\#define NFB$C_SPI_RID 302121026 /* Remote user ID which initially started server */Y#define NFB$C_SPI_SFI 302121027 /* Last (current) SFI given to server process */Y#define NFB$C_SPI_NCB 302121028 /* Last (current) NCB given to server process */Z#define NFB$C_SPI_PNM 302121029 /* Last (current) process name given to server */N/* */d#define NFB$C_AJI_LCK 3187<67105 /* Set if conditionally writable fields are not writable */c#define NFB$C_AJI_REA 318767106 /* Reachable (set if two-way communication established) */N#define NFB$C_AJI_RRA 318767107 /* Reachable Routing Adjacency */N/* */N#define NFB$C_AJI_ADD 318832656 /* Node address */N#define NFB$C_AJI_TYP 318832657 /* Node type */N#define <NFB$C_AJI_LIT 318832658 /* Listen timer for this adjacency */N#define NFB$C_AJI_BLO 318832659 /* Partner's block size */P#define NFB$C_AJI_RPR 318832660 /* Partner's router priority (on NI) */N/* */N#define NFB$C_AJI_COL 318898240 /* Collating field */N#define NFB$C_AJI_NNA 318898241 /* Node name */N#define NFB$C_AJI_CIR 318898242 < /* Circuit name */N/* */d#define NFB$C_SDI_LCK 436207617 /* Set if conditionally writable fields are not writable */N/* */N#define NFB$C_SDI_SUB 436273168 /* Service substate */R#define NFB$C_SDI_PID 436273169 /* PID of process owning this DLE link */N/* < */N#define NFB$C_SDI_COL 436338752 /* Collating field */N#define NFB$C_SDI_CIR 436338753 /* Circuit name */Q#define NFB$C_SDI_PHA 436338754 /* Service physical address (BC only) */S#define NFB$C_SDI_PRC 436338755 /* Name of process owning this DLE link */N/* */d#define NFB$C_ARI_LCK 335544321 /* Set i<f conditionally writable fields are not writable */N#define NFB$C_ARI_REA 335544322 /* Set if node is reachable */N/* */N#define NFB$C_ARI_ADD 335609872 /* Address */N#define NFB$C_ARI_DCO 335609873 /* Destination Cost */N#define NFB$C_ARI_DHO 335609874 /* Destination Hops */N#define NFB$C_ARI_NND 335609875 /* Next node< address */N/* */N#define NFB$C_ARI_COL 335675456 /* Collating field */V#define NFB$C_ARI_DLI 335675457 /* Circuit used for normal traffic to area */N/* */d#define NFB$C_PROXY_LCK 469762049 /* Set if conditionally writable fields are not writable */N/* < */N#define NFB$C_PROXY_RUIC 469827600 /* Remote UIC */N/* */N#define NFB$C_PROXY_RNODE 469893184 /* Remote node */N#define NFB$C_PROXY_RNAME 469893185 /* Remote user name */N#define NFB$C_PROXY_DEFACCOUNT 469893186 /* Default local proxy account */N#define NFB$C_PROXY_ACCOUNT1 469893187 /* Local proxy account < */N#define NFB$C_PROXY_ACCOUNT2 469893188 /* Local proxy account */N#define NFB$C_PROXY_ACCOUNT3 469893189 /* Local proxy account */N#define NFB$C_PROXY_ACCOUNT4 469893190 /* Local proxy account */N#define NFB$C_PROXY_ACCOUNT5 469893191 /* Local proxy account */N#define NFB$C_PROXY_ACCOUNT6 469893192 /* Local proxy account */N#define NFB$C_PROXY_ACCOUNT7 469893193 /* Local proxy account */N#define NFB$C_PROXY_<ACCOUNT8 469893194 /* Local proxy account */N#define NFB$C_PROXY_ACCOUNT9 469893195 /* Local proxy account */N#define NFB$C_PROXY_ACCOUNT10 469893196 /* Local proxy account */N#define NFB$C_PROXY_ACCOUNT11 469893197 /* Local proxy account */N#define NFB$C_PROXY_ACCOUNT12 469893198 /* Local proxy account */N#define NFB$C_PROXY_ACCOUNT13 469893199 /* Local proxy account */N#define NFB$C_PROXY_ACCOUNT14 469893200 /* Loc<al proxy account */N#define NFB$C_PROXY_ACCOUNT15 469893201 /* Local proxy account */N#define NFB$C_PROXY_HASHKEY 469893202 /* Hash key lookup string */N#define NFB$C_PROXY_COL 469893184 /* Collating field */T#define NFB$C_PROXY_MAXACC 15 /* Maximum numver of local proxy accounts */N/* including the default */N#define NFB$S_NFBDEF4 2 /* old size name - synonym< */ typedef struct _nfb4 { __union {N unsigned short int nfb$w_str_count; /* String count field */ __struct {" char nfb$$_fill_1 [2];#if defined(__VAXC)" char nfb$b_str_text[];#elseU/* Warning: empty char[] member for nfb$b_str_text at end of structure not created */"#endif /* #if defined(__VAXC) */N/* */N/* Define identifiers for each paramete<r in all database */N/* */N/* ** The low order 16 bits for each parameter must be unique ** */N/* *** with respect to all other parameters in its particular *** */&/* ** database. ** */N/* */N/* Define a field identifier index for each parameter in the NDI database. */N/* < */N/* */N/* Boolean parameters */N/* */N/* "Longword" Parameters */N/* */N/* String parameters < */N/* */N/* Define a field identifier index for each parameter in the LNI database. */N/* */N/* */N/* Boolean parameters */N/* */<N/* "Longword parameters */N/* */N/* String parameters */N/* */N/* Define a field identifier index for each parameter in the OBI database. */N/* */N/* < */N/* Boolean Parameters */N/* */N/* Longword Parameters */N/* */N/* String Parameters */N/* < */N/* Define a field identifier index for each parameter in the CRI database. */N/* */N/* */;/* /* Use */;/* /* ---- */;/* C = common */;/* E = Executor (used by Transport) < */;/* X = Native X.25 network management */;/* D = DECnet (not X.25) */N/* */N/* */N/* Boolean Parameters */N/* */N/* < */N/* "Longword" parameters */N/* */N/* String Parameters */N/* */N/* Define a field identifier index for each parameter in the PLI database. */N/* <*/;/* C = common */;/* L = LAPB (X.25) */;/* D = DDCMP (not X.25) */;/* E = Ethernet */;/* F = FDDI */;/* T = Token Ring */N/* */;/* /* Use < */N/* ---- */N/* */N/* Boolean Parameters */N/* */N/* "Longword" Parameters */N/* */N/* String Pa<rameters */N/* */N/* Define a field identifier index for each parameter in the EFI database. */N/* */N/* */N/* Boolean Parameters */N/* < */N/* "Longword" Parameters */N/* */N/* String Parameters */N/* */N/* Define a field identifier index for each parameter in the ESI database. */N/* < */N/* */N/* Boolean Parameters */N/* */N/* "Longword" Parameters */N/* */N/* String Parameters */N/* < */N/* Define a field identifier index for each parameter in the LLI database. */N/* */N/* */N/* Boolean Parameters */N/* */N/* Longword Parameters < */N/* */N/* String Parameters */N/* */N/* X.25 network parameters (part of MODULE X25-PROTOCOL) */N/* */N/* Define a field identifier index for each parameter in the XNI< database. */N/* */N/* */N/* Boolean Parameters */N/* */N/* "Longword" Parameters */N/* */N/* Strin<g Parameters */N/* */N/* X.25 DTE parameters (qualified by a given network) */N/* */N/* Define a field identifier index for each parameter in the XDI database. */N/* */N/* < */N/* Boolean Parameters */N/* */N/* "Longword" Parameters */N/* */N/* String Parameters */N/* < */N/* X.25 group parameters (qualified by a given DTE) */N/* */N/* Define a field identifier index for each parameter in the XGI database. */N/* */N/* */N/* Boolean Parameters */N/* < */N/* "Longword" Parameters */N/* */N/* String Parameters */N/* */N/* X.25 server parameters (global parameters for all destinations) */N/* < */N/* Define a field identifier index for each parameter in the XS5 database. */N/* */N/* */N/* Boolean Parameters */N/* */N/* "Longword" Parameters < */N/* */N/* String Parameters */N/* */N/* X.25 destination parameters (part of MODULE X25-SERVER) */N/* */N/* Define a field identifier index for each parameter in the XD5 database. */N/* < */N/* */N/* Boolean Parameters */N/* */N/* "Longword" Parameters */N/* */N/* String Parameters < */N/* */N/* X.29 server parameters (global parameters for all destinations) */N/* */N/* Define a field identifier index for each parameter in the XS9 database. */N/* */N/* < */N/* Boolean Parameters */N/* */N/* "Longword" Parameters */N/* */N/* String Parameters */N/* */N/* X<.29 destination parameters (part of MODULE X29-SERVER) */N/* */N/* Define a field identifier index for each parameter in the XD9 database. */N/* */N/* */N/* Boolean Parameters */N/* < */N/* "Longword" Parameters */N/* */N/* String Parameters */N/* */N/* X.25 tracing facility (global) parameters. */N/* < */N/* Define a field identifier index for each parameter in the XTI database. */N/* */N/* */N/* Boolean Parameters */N/* */N/* "Longword" Parameters */N/*< */N/* String Parameters */N/* */N/* X.25 tracpoint (local) parameters. */N/* */N/* Define a field identifier index for each parameter in the XTT database. */N/* < */N/* */N/* Boolean Parameters */N/* */N/* "Longword" Parameters */N/* */N/* String Parameters < */N/* */N/* X.25 Access (qualified by a given network) */N/* */N/* Define a field identifier index for each parameter in the XAI database. */N/* */N/* */N</* Boolean Parameters */N/* */N/* "Longword" Parameters */N/* */N/* String Parameters */N/* */N/* X.25 Security (qualifie<d by a given network) */N/* */N/* Define a field identifier index for each parameter in the XDTE database. */N/* */N/* */N/* Boolean Parameters */N/* < */N/* */N/* "Longword" Parameters */N/* */N/* ) */N/* */N/* String Parameters */<N/* */N/* Define SPI (Server Process) parameters */N/* */N/* */N/* Boolean Parameters */N/* */N/* Longword Parameters< */N/* */N/* String Parameters */N/* */N/* Define AJI (Adjacency) parameters */N/* */N/* < */N/* Boolean Parameters */N/* */N/* Longword Parameters */N/* */N/* String Parameters */N/* <*/N/* Define SDI (Service DLE) parameters */N/* */N/* */N/* Boolean Parameters */N/* */N/* Longword Parameters */N/* < */N/* String Parameters */N/* */N/* Define the AREA database (read only) for level 2 Phase IV routers only. */N/* */N/* */N/* Boolean parameters < */N/* */N/* "Longword" Parameters */N/* */N/* String parameters */N/* */N/* Define the PROXY database < */N/* */N/* */N/* Boolean parameters */N/* */N/* "Longword" Parameters */N/* */N/* String paramete<rs */N/* */% } nfb$r_str_count_fields;" } nfb$r_str_count_overlay; } NFB4; #if !defined(__VAXC)?#define nfb$w_str_count nfb$r_str_count_overlay.nfb$w_str_countT#define nfb$b_str_text nfb$r_str_count_overlay.nfb$r_str_count_fields.nfb$b_str_text"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL<_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NFBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential <proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/<M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************** <*********************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 22-JUL-2022 11:22:18 $1$DGA8345:[LIB_H.SRC]NMADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $NMADEF ***/#ifndef __NMADEF_LOADED#define __NMADEF_LOADED 1 G#pragma __nostandard /* This file uses non-<ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_pa<rams#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Object type */N/* < */N#define NMA$C_OBJ_NIC 19 /* Nice listener */N/* */N/* Function codes */N/* */N#define NMA$C_FNC_LOA 15 /* Request down-line load */N#define NMA$C_FNC_DUM 16 /* Request up-line dump < */N#define NMA$C_FNC_TRI 17 /* Trigger bootstrap */N#define NMA$C_FNC_TES 18 /* Test */N#define NMA$C_FNC_CHA 19 /* Change parameter */N#define NMA$C_FNC_REA 20 /* Read information */N#define NMA$C_FNC_ZER 21 /* Zero counters */N#define NMA$C_FNC_SYS 22 /* System-specific function */N/* < */N/* Option byte */N/* */N/* common to change parameter, read information and zero counters */N/* */#define NMA$M_OPT_ENT 0x7#define NMA$M_OPT_CLE 0x40#define NMA$M_OPT_PER 0x80#define NMA$M_OPT_INF 0x70N#define NM<A$C_OPINF_SUM 0 /* Summary */N#define NMA$C_OPINF_STA 1 /* Status */N#define NMA$C_OPINF_CHA 2 /* Characteristics */N#define NMA$C_OPINF_COU 3 /* Counters */N#define NMA$C_OPINF_EVE 4 /* Events */N/* */#define NMA$M_OPT_ACC 0x80#define <NMA$M_OPT_REA 0x80N#define NMA$C_SYS_RST 1 /* Rsts */N#define NMA$C_SYS_RSX 2 /* Rsx family */N#define NMA$C_SYS_TOP 3 /* Tops-20 */N#define NMA$C_SYS_VMS 4 /* Vms */N#define NMA$C_SYS_RT 5 /* RT-11 */N/* */N#defin<e NMA$C_ENT_NOD 0 /* Node */N#define NMA$C_ENT_LIN 1 /* Line */N#define NMA$C_ENT_LOG 2 /* Logging */N#define NMA$C_ENT_CIR 3 /* Circuit */N#define NMA$C_ENT_MOD 4 /* Module */N#define NMA$C_ENT_ARE 5 /* Area */N/* < */N#define NMA$C_SENT_PROXY 2 /* Proxies */N#define NMA$C_SENT_ALI 3 /* Alias */N#define NMA$C_SENT_OBJ 4 /* Object */N#define NMA$C_SENT_PRO 5 /* Process */N#define NMA$C_SENT_SYS 6 /* System */N#define NMA$C_SENT_LNK 7 /* Links < */N#define NMA$C_SENT_WLD -30 /* Wildcarded entity */#define NMA$M_ENT_EXE 0x80N#define NMA$C_ENT_WAR -7 /* Wildcarded area */N#define NMA$C_ENT_WAD -6 /* Wildcarded address */N#define NMA$C_ENT_ADJ -4 /* Adjacent */N#define NMA$C_ENT_ACT -2 /* Active */N#define NMA$C_ENT_KNO -1 /* Known < */N#define NMA$C_ENT_ADD 0 /* Node address */N#define NMA$C_ENT_ALL -3 /* All */N#define NMA$C_ENT_LOO -3 /* Loop */N/* */N#define NMA$C_SNK_CON 1 /* Console */N#define NMA$C_SNK_FIL 2 /* File */N#d<efine NMA$C_SNK_MON 3 /* Monitor */N/* */#define NMA$M_CNT_TYP 0xFFF#define NMA$M_CNT_MAP 0x1000#define NMA$M_CNT_WID 0x6000#define NMA$M_CNT_COU 0x8000#define NMA$M_CNT_WIL 0x2000#define NMA$M_CNT_WIH 0x4000N#define NMA$S_NMADEF 2 /* Old size name - synonym */ typedef struct _nma { __union { __struct {N unsigned n<ma$v_opt_ent : 3; /* Entity type */& unsigned nma$$_fill_1 : 3;N/* */N/* change parameter */N/* */N unsigned nma$v_opt_cle : 1; /* Clear parameter */N/* */N/* co<mmon to change parameter or read information */N/* */N unsigned nma$v_opt_per : 1; /* Permanent parameters */! } nma$r_nmadef_bits0;N/* */N/* read information */N/* */ < __struct {& unsigned nma$$_fill_2 : 4;N unsigned nma$v_opt_inf : 3; /* Information type mask */' unsigned nma$v_fill_0_ : 1;! } nma$r_nmadef_bits1;N/* test */N/* */ __struct {& unsigned nma$$_fill_3 : 7;N unsigned nma$v_opt_acc : 1; /* Access control incl <uded */! } nma$r_nmadef_bits2;N/* */N/* zero */N/* */ __struct {& unsigned nma$$_fill_4 : 7;N unsigned nma$v_opt_rea : 1; /* Read and zero */! } nma$r_nmadef_bits3;N/* < */N/* System types */N/* */N/* Entity types. This numbering scheme must be used in non-system-specific */N/* NICE messages. (See below for conflicting system-specific entities). */N/* */N/* System-specific (function 22) entity types. This numberi <ng scheme */N/* for objects must be used in any entity type in system-specific NICE */N/* messages. */N/* */ __struct {& unsigned nma$$_fill_5 : 7;\ unsigned nma$v_ent_exe : 1; /* Executor indicator flag for response messages */! } nma$r_nmadef_bits4;N/* < */N/* Entity identification format types */N/* */N/* Logging sink types */N/* */N/* Counter data type values */N/* */ < __struct {N unsigned nma$v_cnt_typ : 12; /* Type mask */N unsigned nma$v_cnt_map : 1; /* Bitmapped indicator */N unsigned nma$v_cnt_wid : 2; /* Width field mask */N unsigned nma$v_cnt_cou : 1; /* Counter indicator */! } nma$r_nmadef_bits5; __struct {' unsigned nma$$_fill_6 : 13;N unsigned nma$v_cnt_wil : 1; /* Width field low bit < */N unsigned nma$v_cnt_wih : 1; /* Width field high bit */' unsigned nma$v_fill_1_ : 1;! } nma$r_nmadef_bits6;N/* */N/* Node area and address extraction */N/* */ } nma$r_nma_fill_union; } NMA; #if !defined(__VAXC)K#define nma$v_opt_en<t nma$r_nma_fill_union.nma$r_nmadef_bits0.nma$v_opt_entK#define nma$v_opt_cle nma$r_nma_fill_union.nma$r_nmadef_bits0.nma$v_opt_cleK#define nma$v_opt_per nma$r_nma_fill_union.nma$r_nmadef_bits0.nma$v_opt_perK#define nma$v_opt_inf nma$r_nma_fill_union.nma$r_nmadef_bits1.nma$v_opt_infK#define nma$v_opt_acc nma$r_nma_fill_union.nma$r_nmadef_bits2.nma$v_opt_accK#define nma$v_opt_rea nma$r_nma_fill_union.nma$r_nmadef_bits3.nma$v_opt_reaK#define nma$v_ent_exe nma$r_nma_fill_union.nma$r_nmadef_bi<ts4.nma$v_ent_exeK#define nma$v_cnt_typ nma$r_nma_fill_union.nma$r_nmadef_bits5.nma$v_cnt_typK#define nma$v_cnt_map nma$r_nma_fill_union.nma$r_nmadef_bits5.nma$v_cnt_mapK#define nma$v_cnt_wid nma$r_nma_fill_union.nma$r_nmadef_bits5.nma$v_cnt_widK#define nma$v_cnt_cou nma$r_nma_fill_union.nma$r_nmadef_bits5.nma$v_cnt_couK#define nma$v_cnt_wil nma$r_nma_fill_union.nma$r_nmadef_bits6.nma$v_cnt_wilK#define nma$v_cnt_wih nma$r_nma_fill_union.nma$r_nmadef_bits6.nma$v_cnt_wih"#endif /* #if !de<fined(__VAXC) */ #define NMA$M_PTY_TYP 0x7FFFS#define NMA$C_PTY_MAX 15 /* Maximum fields within coded multiple */#define NMA$M_PTY_CLE 0x3F#define NMA$M_PTY_MUL 0x40#define NMA$M_PTY_COD 0x80#define NMA$M_PTY_CMU 0xC0#define NMA$M_PTY_NLE 0xF#define NMA$M_PTY_NTY 0x30#define NMA$M_PTY_ASC 0x40N#define NMA$C_NTY_DU 0 /* Unsigned decimal */N#define NMA$C_NTY_DS 1 /* Signed decimal */N#define NMA$<C_NTY_H 2 /* Hexidecimal */N#define NMA$C_NTY_O 3 /* Octal */N/* NLE values (length of number): */N#define NMA$C_NLE_IMAGE 0 /* Image field (byte-counted) */N#define NMA$C_NLE_BYTE 1 /* Byte */N#define NMA$C_NLE_WORD 2 /* Word */N#define NMA$C_NLE_LONG 4 < /* Longword */N#define NMA$C_NLE_QUAD 8 /* Quadword */N/* */N#define NMA$C_PTY_AI 64 /* ASCII image (ASC=1) */N#define NMA$C_PTY_HI 32 /* Hex image (NTY=H, NLE=IMAGE) */N#define NMA$C_PTY_H1 33 /* Hex byte (NTY=H, NLE=BYTE) */N#define NMA$C_PTY_H2 34 /* Hex word (NTY=H, NLE=<WORD) */N#define NMA$C_PTY_H4 36 /* Hex byte (NTY=H, NLE=LONG) */V#define NMA$C_PTY_DU1 1 /* Decimal unsigned byte (NTY=DU,NLE=BYTE) */V#define NMA$C_PTY_DU2 2 /* Decimal unsigned word (NTY=DU,NLE=WORD) */Q#define NMA$C_PTY_CD1 129 /* Coded decimal byte (COD=1, 1 byte) */N#define NMA$C_PTY_CM2 194 /* Coded multiple, 2 fields */N#define NMA$C_PTY_CM3 195 /* Coded multiple, 3 fields < */N#define NMA$C_PTY_CM4 196 /* Coded multiple, 4 fields */N#define NMA$C_PTY_CM5 197 /* Coded multiple, 5 fields */N/* */N#define NMA$C_CTLVL_UI 3 /* User interface */N#define NMA$C_CTLVL_XID 175 /* */N#define NMA$C_CTLVL_XID_P 191 /* */N#define NMA$C_CT<LVL_TEST 227 /* */N#define NMA$C_CTLVL_TEST_P 243 /* */N/* */Q#define NMA$C_PCCI_STA 0 /* State (coded byte of NMA$C_STATE_) */T#define NMA$C_PCCI_SUB 1 /* Substate (coded byte of NMA$C_LINSS_) */S#define NMA$C_PCCI_SER 100 /* Service (coded byte of NMA$C_LINSV_) */N#define NMA$C_PCCI_LCT 110= /* Counter timer (word) */T#define NMA$C_PCCI_SPY 120 /* Service physical address (NI address) */\#define NMA$C_PCCI_SSB 121 /* Service substate (coded byte of NMA$C_LINSS_) */N#define NMA$C_PCCI_CNO 200 /* Connected node */N#define NMA$C_PCCI_COB 201 /* Connected object */N#define NMA$C_PCCI_LOO 400 /* Loopback name (ascic) */N#define NMA$C_PCCI_ADJ 800 = /* Adjacent node */N#define NMA$C_PCCI_DRT 801 /* Designated router on NI */N#define NMA$C_PCCI_BLO 810 /* Block size (word) */N#define NMA$C_PCCI_COS 900 /* Cost (byte) */N#define NMA$C_PCCI_MRT 901 /* Maximum routers on NI (byte) */N#define NMA$C_PCCI_RPR 902 /* Router priority on NI (byte) */N#define NMA$C_PCCI_HET 906 /* Hello timer (wo=rd) */N#define NMA$C_PCCI_LIT 907 /* Listen timer (word) */U#define NMA$C_PCCI_BLK 910 /* Blocking (coded byte of NMA$C_CIRBLK_) */N#define NMA$C_PCCI_MRC 920 /* Maximum recalls (byte) */N#define NMA$C_PCCI_RCT 921 /* Recall timer (word) */N#define NMA$C_PCCI_NUM 930 /* Number (ascic) */N#define NMA$C_PCCI_USR 1000 /* User entity identification =*/Z#define NMA$C_PCCI_POL 1010 /* Polling state (coded byte of NMA$C_CIRPST_) */N#define NMA$C_PCCI_PLS 1011 /* Polling substate (coded byte) */N#define NMA$C_PCCI_OWN 1100 /* Owner entity identification */N#define NMA$C_PCCI_LIN 1110 /* Line (ascic) */Q#define NMA$C_PCCI_USE 1111 /* Usage (coded byte of NMA$C_CIRUS_) */P#define NMA$C_PCCI_TYP 1112 /* Type (coded byte of NMA$C_CIRTY_) */N#def=ine NMA$C_PCCI_NET 1119 /* Network (ascic) */N#define NMA$C_PCCI_DTE 1120 /* DTE (ascic) */N#define NMA$C_PCCI_CHN 1121 /* Channel (word) */N#define NMA$C_PCCI_MBL 1122 /* Maximum data (word) */N#define NMA$C_PCCI_MWI 1123 /* Maximum window (byte) */N#define NMA$C_PCCI_TRI 1140 /* Tributary (byte) */N#define NMA$C_PCCI_BBT 1141 = /* Babble timer (word) */N#define NMA$C_PCCI_TRT 1142 /* Transmit timer (word) */N#define NMA$C_PCCI_RTT 1143 /* Retransmit timer (word) */S#define NMA$C_PCCI_MRB 1145 /* Maximum receive buffers (coded byte) */N/* 0-254 is value, 255 = UNLIMITED */N#define NMA$C_PCCI_MTR 1146 /* Maximum transmits (byte) */N#define NMA$C_PCCI_ACB 1150 /* Active =base (byte) */N#define NMA$C_PCCI_ACI 1151 /* Active increment (byte) */N#define NMA$C_PCCI_IAB 1152 /* Inactive base (byte) */N#define NMA$C_PCCI_IAI 1153 /* Inactive increment (byte) */N#define NMA$C_PCCI_IAT 1154 /* Inactive threshold (byte) */N#define NMA$C_PCCI_DYB 1155 /* Dying base (byte) */N#define NMA$C_PCCI_DYI 1156 /* Dying increment (byte) =*/N#define NMA$C_PCCI_DYT 1157 /* Dying threshold (byte) */N#define NMA$C_PCCI_DTH 1158 /* Dead threshold (byte) */N/* */N#define NMA$C_PCCI_RSX_MAC 2320 /* Multipoint active ratio */N#define NMA$C_PCCI_RSX_LOG 2380 /* Logical name */N#define NMA$C_PCCI_RSX_DLG 2385 /* Designated name */N#define NMA$C_PCCI_RSX=_ACT 2390 /* Actual name */N/* */X#define NMA$C_PCCI_VER 2700 /* Verification (coded byte of NMA$C_CIRVE_) */[#define NMA$C_PCCI_XPT 2720 /* Transport type (coded byte of NMA$C_CIRXPT_) */N/* VMS Specific codes that are used for the X21 project */N#define NMA$C_PCCI_IRC 2750 /*Incoming Reverse */N#define NMA$C_PCCI_ORC 2 =751 /*Outgoing Reverse */N#define NMA$C_PCCI_GRP 2752 /*Cug */N#define NMA$C_PCCI_NOP 2753 /*National Facility Data */N#define NMA$C_PCCI_CAL 2754 /*Call request "Now/Clear" */N#define NMA$C_PCCI_INA 2755 /*Inactive */N#define NMA$C_PCCI_RED 2756 /*Redirected status */O#define NMA$C_PCCI_MOD 2757 /*Time-cut = Mode status "Auto/Noauto" */N#define NMA$C_PCCI_REQ 2758 /*Request timer T1 */N#define NMA$C_PCCI_DTW 2759 /*Dte waiting timer t2 */N#define NMA$C_PCCI_PRO 2760 /*Progress timer t3a */N#define NMA$C_PCCI_INF 2761 /*Information timer t4a */N#define NMA$C_PCCI_ACC 2762 /*Accepted timer t4b */N#define NMA$C_PCCI_CLR 2763 /*Request timer t5  = */N#define NMA$C_PCCI_DTC 2764 /*Dte clear timer t6 */N#define NMA$C_PCCI_CCG 2765 /*Charging timer t7 */N#define NMA$C_PCCI_ESA 2766 /*Enhanced Subaddress */N#define NMA$C_PCCI_DTI 2767 /*DTE provided info */N#define NMA$C_PCCI_SWC 2768 /*Switched - set line leased */N#define NMA$C_PCCI_TIC 2769 /*Timecutting on/off */N#define NMA$C_PCCI_C =SG 2770 /*Send signal-data enable/disable */N#define NMA$C_PCCI_AAS 2771 /*Abbreviated address. */N#define NMA$C_PCCI_DTS 2772 /*DTE Status */N#define NMA$C_PCCI_CAS 2773 /*Call Status */N#define NMA$C_PCCI_CPS 2774 /*Call-Progress Status */N#define NMA$C_PCCI_CNT 2775 /*Counter . */N#define NMA$C_PCCI_RAT 2776 /*Rate = item read only for show */N#define NMA$C_PCCI_PRD 2777 /*Period hh:mm-hh:mm */N#define NMA$C_PCCI_DAY 2778 /*day of week */R#define NMA$C_PCCI_BFN 2779 /*number of buffers for driver to issue */N#define NMA$C_PCCI_BSZ 2780 /*size of buffer to allocate. */N#define NMA$C_PCCI_MDM 2781 /*Modem signals on/off */N#define NMA$C_PCCI_DTL 2782 /*DTE-List element. = */N#define NMA$C_PCCI_IDL 2783 /*Idle time */N#define NMA$C_PCCI_IMT 2784 /*Initial Minimum timer */N#define NMA$C_PCCI_CAC 2785 /*Call accept control */N#define NMA$C_PCCI_ORD 2786 /*Outgoing request Delay */N#define NMA$C_PCCI_CID 2787 /*Calling DTE id */N/* */N#define NMA$C_=PCCI_MST 2810 /* Maintenance state */N/* */N#define NMA$C_PCCI_SRV_LOG 3380 /* Logical name */N#define NMA$C_PCCI_SRV_DLG 3385 /* Designated name */N#define NMA$C_PCCI_SRV_ACT 3390 /* Actual name */N/* */Q#define NMA$C_PCLI_STA 0 =/* State (coded byte of NMA$C_STATE_) */T#define NMA$C_PCLI_SUB 1 /* Substate (coded byte of NMA$C_LINSS_) */S#define NMA$C_PCLI_SER 100 /* Service (coded byte of NMA$C_LINSV_) */N#define NMA$C_PCLI_LCT 110 /* Counter timer (word) */N#define NMA$C_PCLI_LOO 400 /* Loopback name (ascic) [V2 only] */N#define NMA$C_PCLI_ADJ 800 /* Adjacent node [V2 only] */N#define NMA$C_PCLI_BLO 810 /* Block s=ize (word) [V2 only] */N#define NMA$C_PCLI_COS 900 /* Cost (byte) [V2 only] */N#define NMA$C_PCLI_DEV 1100 /* Device (ascic) */N#define NMA$C_PCLI_BFN 1105 /* Receive buffers */V#define NMA$C_PCLI_CON 1110 /* Controller (coded byte of NMA$C_LINCN_) */P#define NMA$C_PCLI_DUP 1111 /* Duplex (coded byte of NMA$C_DPX_) */T#define NMA$C_PCLI_PRO 1112 /* Protocol (coded byte of= NMA$C_LINPR_) */Z#define NMA$C_PCLI_LTY 1112 /* Type (coded byte of NMA$C_LINTY_) [V2 only] */Q#define NMA$C_PCLI_CLO 1113 /* Clock (coded byte of NMA$C_LINCL_) */N#define NMA$C_PCLI_STI 1120 /* Service timer (word) */N#define NMA$C_PCLI_NTI 1121 /* Normal timer (word) [V2 only] */N#define NMA$C_PCLI_RTT 1121 /* Retransmit timer (word) */N#define NMA$C_PCLI_HTI 1122 /* Holdback timer (word) = */N#define NMA$C_PCLI_MBL 1130 /* Maximum block (word) */N#define NMA$C_PCLI_MRT 1131 /* Maximum retransmits (byte) */N#define NMA$C_PCLI_MWI 1132 /* Maximum window (byte) */N#define NMA$C_PCLI_TRI 1140 /* Tributary (byte) [V2 only] */N#define NMA$C_PCLI_SLT 1150 /* Scheduling timer (word) */N#define NMA$C_PCLI_DDT 1151 /* Dead timer (word) */N#define NMA$C_PC=LI_DLT 1152 /* Delay timer (word) */N#define NMA$C_PCLI_SRT 1153 /* Stream timer (word) */N#define NMA$C_PCLI_HWA 1160 /* Hardware address (NI address) */N/* */N#define NMA$C_PCLI_TREQ 1161 /* Requested TRT */N#define NMA$C_PCLI_TVX 1162 /* Valid transmission time */N#define NMA$C_PCLI_REST_TTO 1163 /*= Restricted token timeout */N#define NMA$C_PCLI_RPE 1164 /* Ring purger enable */N#define NMA$C_PCLI_NIF_TARG 1165 /* NIF target */N#define NMA$C_PCLI_SIF_CONF_TARG 1166 /* SIF configuration target */N#define NMA$C_PCLI_SIF_OP_TARG 1167 /* SIF operation target */N#define NMA$C_PCLI_ECHO_TARG 1168 /* Echo target */N#define NMA$C_PCLI_ECHO_DAT 1169 /* Echo data = */N/* */N#define NMA$C_PCLI_STN_ADR 1170 /* Station address */N#define NMA$C_PCLI_FNC_ADR 1171 /* Functional address */N#define NMA$C_PCLI_GRP_ADR 1172 /* Group address */U#define NMA$C_PCLI_UNA 1173 /* Upstream neighbor (in common with FDDI) */N#define NMA$C_PCLI_RNG_NUM 1174 /* Ring number */N#defin=e NMA$C_PCLI_AUTH_PR 1175 /* Authorized access priority */N#define NMA$C_PCLI_RNG_SPD 1176 /* Ring speed */N#define NMA$C_PCLI_ETR 1177 /* Early token release */N#define NMA$C_PCLI_SRC_ROU 1178 /* Source routing */N#define NMA$C_PCLI_ADR_TYP 1179 /* Address type */N#define NMA$C_PCLI_A_TIM 1400 /* Aging timer */N/* = */N#define NMA$C_PCLI_ECHO_LEN 1180 /* Echo length */N#define NMA$C_PCLI_LAST_NIF 1181 /* Last NIF */N#define NMA$C_PCLI_LAST_SIF 1182 /* Last SIF */N#define NMA$C_PCLI_LAST_ECHO 1183 /* Last echo */N#define NMA$C_PCLI_T_NEG 1184 /* Negotiated TRT */N#define NMA$C_PCLI_DAT 1185 /* Duplicate addre=ss flag */N#define NMA$C_PCLI_OLD_UNA 1187 /* Old upstream neighbor */N#define NMA$C_PCLI_UN_DAT 1188 /* Upstream neighbor DA flag */N#define NMA$C_PCLI_DNA 1189 /* Downstream neighbor */N#define NMA$C_PCLI_OLD_DNA 1192 /* Old downstream neighbor */N#define NMA$C_PCLI_RPS 1193 /* Ring purger state */N#define NMA$C_PCLI_RER 1194 /* Ring error reason */N#def=ine NMA$C_PCLI_FDE 1198 /* Full duplex enable */N#define NMA$C_PCLI_NBR_PHY 1300 /* Neighbor PHY type */N#define NMA$C_PCLI_LEE 1301 /* Link error estimate */N#define NMA$C_PCLI_RJR 1302 /* Reject reason */N#define NMA$C_PCLI_NET 1190 /* Network name (ascic) */Z#define NMA$C_PCLI_XMD 1191 /* X.25 line mode (coded byte of NMA$C_X25MD_) */N/* = */N#define NMA$C_PCLI_RSX_OWN 2300 /* Owner */N#define NMA$C_PCLI_RSX_CCS 2310 /* Controller CSR */N#define NMA$C_PCLI_RSX_UCS 2311 /* Unit CSR */N#define NMA$C_PCLI_RSX_VEC 2312 /* Vector */N#define NMA$C_PCLI_RSX_PRI 2313 /* Priority */N#define NMA$C_PCLI_RSX_MDE 2321 /* D=ead polling ratio */N#define NMA$C_PCLI_RSX_LLO 2330 /* Location */N/* 0, Firstfit */N#define NMA$C_PCLI_RSX_LOG 2380 /* Logical name */N#define NMA$C_PCLI_RSX_DLG 2385 /* Designated name */N#define NMA$C_PCLI_RSX_ACT 2390 /* Actual name */N/* = */O#define NMA$C_PCLI_MCD 2701 /* Micro-code dump filespec (ascic) */P#define NMA$C_PCLI_EPT 2720 /* Ethernet Protocol Type (hex word) */N#define NMA$C_PCLI_LNS 2730 /* Line speed (word) */R#define NMA$C_PCLI_SWI 2740 /* SWITCH (coded byte of nma$c_linswi_) */R#define NMA$C_PCLI_HNG 2750 /* HANGUP (coded byte of NMA$C_LINHNG_) */N#define NMA$C_PCLI_TPI 2760 /* Transmit pipeline */N#def=ine NMA$C_PCLI_NRZI 2761 /* NRZI bit encoding */O#define NMA$C_PCLI_CODE 2762 /* Character code (encoded as CODE_) */N/* This section are parameters for 802 support. */N#define NMA$C_PCLI_FMT 2770 /* Packet format(coded of linfm_) */N#define NMA$C_PCLI_SRV 2771 /* Driver service coded of linsr */N#define NMA$C_PCLI_SAP 2772 /* SAP */N#define NMA$C_PCLI_GSP 2773 = /* GSP */N#define NMA$C_PCLI_PID 2774 /* PID */N#define NMA$C_PCLI_CNM 2775 /* Client name */N#define NMA$C_PCLI_CCA 2776 /* Can change address */N#define NMA$C_PCLI_APC 2777 /* Allow promiscuous client */N#define NMA$C_PCLI_MED 2778 /* Communication medium */N#define NMA$C_PCLI_PNM 2779 /* Port name  = */N#define NMA$C_PCLI_SNM 2780 /* Station name */N/* This section for Token Ring-specific line parameters */N#define NMA$C_PCLI_MONCONTEND 2781 /* Monitor Contendor */N#define NMA$C_PCLI_CACHE_ENT 2782 /* SR Cache Entr */N#define NMA$C_PCLI_ROUTEDIS 2783 /* SR Discover Tmr */N/* This includes generic parameters for LAN devices */R!=#define NMA$C_PCLI_LINEMEDIA 2784 /* UTP, STP, AUI, TP, AUTO, UNSPECIFIED */N#define NMA$C_PCLI_LINESPEED 2785 /* 10,100,4,16,1000,10000 */N/* This section for ATM and Emulated LAN specific line parameters */N#define NMA$C_PCLI_LES_HWA 2786 /* LAN Emulation Server Address */N#define NMA$C_PCLI_PVC_REQ 2787 /* PVC Request */N#define NMA$C_PCLI_PVC 2788 /* PVC List */N#define NMA$C_PCLI_ELA"=N_STATE_REQ 2789 /* Emulated LAN State request */N#define NMA$C_PCLI_ELAN_STATE_RSP 2790 /* Emulated LAN State response */N#define NMA$C_PCLI_EVENT_REQ 2791 /* Set ATM Event Mask */N#define NMA$C_PCLI_EVENT 2792 /* ATM Event Mask */N#define NMA$C_PCLI_EXT_SENSE_REQ 2793 /* ATM Extended Sense Request */N#define NMA$C_PCLI_EXT_SENSE 2794 /* ATM Extended Sense Response */N#define NMA$C_PCLI_ELAN_BUS 2795 /* ELAN #=Brdcst Server ATM Address */N#define NMA$C_PCLI_ELAN_PAR 2796 /* ELAN Parent ATM Device */N#define NMA$C_PCLI_ELAN_DESC 2797 /* ELAN Description String */N#define NMA$C_PCLI_NUM_PVC 2798 /* Number of PVC */N#define NMA$C_PCLI_MAXPVC 64 /* Maximum number of PVC */I/* This section for ATM Classical IP specific line parameters */N#define NMA$C_PCLI_CLIP_LIS_HWA 2702 /* CLIP LIS ATM Address */$=N#define NMA$C_PCLI_CLIP_STATE_REQ 2703 /* CLIP LIS State Request */N#define NMA$C_PCLI_CLIP_STATE_RSP 2704 /* CLIP LIS State Response */N#define NMA$C_PCLI_CLIP_IP_ADDR 2705 /* CLIP Client IP Address */N#define NMA$C_PCLI_CLIP_IP_SUBNET 2706 /* CLIP Client IP Subnet */N#define NMA$C_PCLI_CLIP_NAME 2707 /* CLIP LIS Name */N#define NMA$C_PCLI_CLIP_USER_TYPE 2708 /* CLIP User type */N#define NMA$C_PCLI_CLIP_%=ATM_ADDR 2709 /* CLIP Client ATM Address */N#define NMA$C_PCLI_CLIP_PAR 2711 /* CLIP Parent Device */N#define NMA$C_PCLI_CLIP_PVC_IP_ADDR 2712 /* CLIP Parent Device */N#define NMA$C_PCLI_CLIP_PVC_STATUS 2713 /* CLIP Parent Device */N#define NMA$C_PCLI_CLIP_GET_PVC 2714 /* Sense PVC state */I/* This section is for Logical LAN specific line parameters */N#define NMA$C_PCLI_LLAN_STATE_REQ 2715 /* LLAN State &=Request */N#define NMA$C_PCLI_LLAN_STATE_RSP 2716 /* LLAN State Response */N#define NMA$C_PCLI_LLAN_FAILSET 2717 /* LLAN Failset */N#define NMA$C_PCLI_FAIL_PRI 2718 /* Failover Priority */I/* This section is for VLAN specific line parameters */N#define NMA$C_PCLI_VLAN_DATA 2719 /* VLAN DATA */N/* */N#def'=ine NMA$C_PCLI_BUS 2801 /* Buffer size (word) */S#define NMA$C_PCLI_NMS 2810 /* Number of DMP/DMF synch chars (word) */V#define NMA$C_PCLI_PHA 2820 /* Physical NI address of UNA (hex string) */h#define NMA$C_PCLI_DPA 2821 /* (same as HWA) ; Default UNA physical address (hex string) */N#define NMA$C_PCLI_PTY 2830 /* Ethernet Protocol type (word) */S#define NMA$C_PCLI_MCA 2831 /* UNA Multicast address list (=(special) */N/* (See NMA$C_LINMC_) */N#define NMA$C_PCLI_JUMBO 2832 /* Jumbo frames mode */N#define NMA$C_PCLI_FLOW 2833 /* Flow control mode */N#define NMA$C_PCLI_AUTONEG 2834 /* Auto-negotiation mode */N#define NMA$C_PCLI_ILP 2839 /* DELUA Internal Loopback mode */N/* (coded byte of NMA$C_STATE_) */`#define NM)=A$C_PCLI_PRM 2840 /* UNA Promiscuous mode (coded byte of NMA$C_STATE_) */f#define NMA$C_PCLI_MLT 2841 /* UNA Multicast address mode (coded byte of NMA$C_STATE_) */\#define NMA$C_PCLI_PAD 2842 /* UNA Padding mode (coded byte of NMA$C_STATE_) */b#define NMA$C_PCLI_DCH 2843 /* UNA Data chaining mode (coded byte of NMA$C_STATE_) */X#define NMA$C_PCLI_CRC 2844 /* UNA CRC mode (coded byte of NMA$C_STATE_) */O#define NMA$C_PCLI_HBQ 2845 *= /* UNA Hardware Buffer Quota (word) */b#define NMA$C_PCLI_ACC 2846 /* UNA protocol access mode (coded byte of NMA$C_ACC_) */Y#define NMA$C_PCLI_EKO 2847 /* UNA Echo mode (coded byte of NMA$C_STATE_) */N#define NMA$C_PCLI_BSZ 2848 /* UNA Device Buffer size */O#define NMA$C_PCLI_DES 2849 /* UNA destination Ethernet address */N#define NMA$C_PCLI_RET 2850 /* PCL number of retries (word) */\#define NMA$C_PCLI_M+=OD 2851 /* PCL address mode (coded byte of NMA$C_LINMO_) */c#define NMA$C_PCLI_RIB 2852 /* PCL retry-if-busy state (coded byte of NMA$C_STATE_) */T#define NMA$C_PCLI_MNTL 2860 /* Maintenance loopback mode for devices */N/* which support several different loop back modes */N#define NMA$C_PCLI_INTL0 2861 /* Internal loopback level 0 */N#define NMA$C_PCLI_INTL1 2862 /* Internal loopback level 1 */N#def,=ine NMA$C_PCLI_INTL2 2863 /* Internal loopback level 2 */N#define NMA$C_PCLI_INTL3 2864 /* Internal loopback level 3 */N#define NMA$C_PCLI_FRA 2865 /* Framing address for Bisync */N#define NMA$C_PCLI_STI1 2866 /* State info 1st longword */N#define NMA$C_PCLI_STI2 2867 /* State info 2st longword */c#define NMA$C_PCLI_TMO 2868 /* Wait for CTS time out value for DMF sync half duplex */Q#define -=NMA$C_PCLI_MCL 2869 /* Clear modem on deassign of channel */N#define NMA$C_PCLI_SYC 2870 /* BISYNC protocol sync char */N#define NMA$C_PCLI_BPC 2871 /* Number of bits per character */N#define NMA$C_PCLI_MBS 2872 /* Maximum buffer size */S#define NMA$C_PCLI_RES 2873 /* Restart value (coded byte of LINRES_) */V#define NMA$C_PCLI_XFC 2874 /* Transmit FC (coded byte of NMA$C_STATE_) */V#define NMA$C_PC.=LI_RFC 2875 /* Receive FC (coded byte of NMA$C_STATE_) */N/* IO$M_UPDATE_MAP I/O Subfunction parameters (Token Ring) */N#define NMA$C_PCLI_MAP 2876 /* FCA Map Functions */N#define NMA$C_MAP_ADD 0 /* Add Entry */N#define NMA$C_MAP_CHANGE 1 /* Change Entry */N#define NMA$C_MAP_DELETE 2 /* Delete Entry */P#define NMA$C_PCLI_MRB 2877 /= /* Maximum Receive Buffers (for user) */S#define NMA$C_PCLI_MINRCV 2878 /* Minimum Receive Buffers (for netman) */R#define NMA$C_PCLI_MAXRCV 2879 /* Maximum Receive Buffers (for netman) */N/* IO$M_ROUTE I/O Subfunction parameters (Token Ring) */N#define NMA$C_PCLI_ROUTE 2880 /* SR Functions */N#define NMA$C_SR_ADD 0 /* Add route */N#define NMA$C_SR_DEL 1 /* Delet0=e route */N#define NMA$C_PCLI_SRC 2881 /* Source address list */N/* Regular IO$M_SENSEMODE/IO$M_STARTUP parameters (Token Ring) */N#define NMA$C_PCLI_FCA 2883 /* FCA list (RO) */N#define NMA$C_PCLI_XAC 2884 /* Xmit AC */N#define NMA$C_PCLI_RAC 2885 /* Recv AC */N#define NMA$C_PCLI_FAMODE 2886 /* Func. Addr. Mode 1= */N#define NMA$C_PCLI_SRMODE 2887 /* SR mode */N#define NMA$C_SR_TRANSPARENT 0 /* Xparent SR mode */N#define NMA$C_SR_SELF 1 /* SR done by self */N/* */N#define NMA$C_PCLI_SRV_OWN 3300 /* Owner */N#define NMA$C_PCLI_SRV_UCS 3311 /* Unit CSR */N#define NMA$C_PCLI_S2=RV_VEC 3312 /* Vector */N#define NMA$C_PCLI_SRV_PRI 3313 /* Priority */N#define NMA$C_PCLI_SRV_LOG 3380 /* Logical name */N#define NMA$C_PCLI_SRV_DLG 3385 /* Designated name */N#define NMA$C_PCLI_SRV_ACT 3390 /* Actual name */N/* */N#define NMA$C_LINMD_CSMACD 10 /* 3= */N#define NMA$C_LINMD_FDDI 11 /* */N#define NMA$C_LINMD_CI 12 /* */N#define NMA$C_LINMD_TR 13 /* */N#define NMA$C_LINMD_ATM 14 /* */N/* */N#define NMA$C_PCCO_RTR 110 /* Reservation timer (word) 4= */N/* */Y#define NMA$C_PCLD_ASS 10 /* Assistance flag (coded byte of NMA$C_ASS_) */N/* */Y#define NMA$C_PCLP_ASS 10 /* Assistance flag (coded byte of NMA$C_ASS_) */N/* */N#define NMA$C_PCCN_CIR 100 /* NI circuit name (ascic) 5= */[#define NMA$C_PCCN_SUR 110 /* Surveillance flag (coded byte of NMA$C_SUR_) */N#define NMA$C_PCCN_ELT 111 /* Elapsed time */N#define NMA$C_PCCN_PHA 120 /* Physical address (NI address) */N#define NMA$C_PCCN_LRP 130 /* Time of last report */N#define NMA$C_PCCN_MVR 20001 /* Maintenance version */N#define NMA$C_PCCN_FCT 20002 /* Function list */P#defin6=e NMA$C_PCCN_CUS 20003 /* Current console user (NI address) */N#define NMA$C_PCCN_RTR 20004 /* Reservation timer (word) */N#define NMA$C_PCCN_CSZ 20005 /* Command buffer size (word) */N#define NMA$C_PCCN_RSZ 20006 /* Response buffer size (word) */N#define NMA$C_PCCN_HWA 20007 /* Hardware address (NI address) */V#define NMA$C_PCCN_DTY 20100 /* Device type (coded byte of NMA$C_SOFD_) */N#define NMA$C_PCCN_SFI7= 20200 /* Software ID */N#define NMA$C_PCCN_SPR 20300 /* System processor (coded word) */N#define NMA$C_PCCN_DLK 20400 /* Data link type (coded word) */N/* */Q#define NMA$C_PCLO_STA 0 /* State (coded byte of NMA$C_STATE_) */N#define NMA$C_PCLO_LNA 100 /* System/name (ascic) */N#define NMA$C_PCLO_SIN 200 /* S8=ink node */N#define NMA$C_PCLO_EVE 201 /* Events */N/* */N#define NMA$C_PCXA_NOD 320 /* Node */N#define NMA$C_PCXA_USR 330 /* User (ascic) */N#define NMA$C_PCXA_SPW 331 /* Password to set (ascic) */\#define NMA$C_PCXA_RPW 331 /* Password to read (coded byt9=e of NMA$C_NODPW_) */N#define NMA$C_PCXA_ACC 332 /* Account (ascic) */N#define NMA$C_PCXA_NET 1110 /* Network (ascic) */N/* */N#define NMA$C_PCXA_RSX_ADS 2310 /* Destination */N#define NMA$C_PCXA_RSX_ANB 2320 /* Number */N#define NMA$C_PCXA_RSX_ASC 2330 /* Scope */N/*:= */N#define NMA$C_PCXA_SRV_ADS 3310 /* Destination */N#define NMA$C_PCXA_SRV_ANB 3320 /* Number */N#define NMA$C_PCXA_SRV_ASC 3330 /* Scope */N/* */Q#define NMA$C_PCXP_STA 0 /* State (coded byte of NMA$C_STATE_) */f#define NMA$C_PCXP_SBS 1;= /* Substate, qualified by DTE (coded byte of NMA$C_XPRSB_) */N#define NMA$C_PCXP_CTM 100 /* Counter timer (word) */N#define NMA$C_PCXP_ACH 1000 /* Active channels (word) */N#define NMA$C_PCXP_ASW 1010 /* Active switched (word) */N#define NMA$C_PCXP_DTE 1100 /* DTE (ascic) */N#define NMA$C_PCXP_GRP 1101 /* Group (ascic) */N#define NMA$C_PCXP_NETENT <=1110 /* Network entity (ascic) */N#define NMA$C_PCXP_DNT 1111 /* DTE Network (ascic) */N#define NMA$C_PCXP_LIN 1120 /* Line (ascic) */N#define NMA$C_PCXP_CHN 1130 /* Channels */N#define NMA$C_PCXP_MCH 1131 /* Maximum channels (word) */N#define NMA$C_PCXP_DBL 1140 /* Default data (word) */N#define NMA$C_PCXP_DWI 1141 /* Default w==indow (byte) */N#define NMA$C_PCXP_MBL 1150 /* Maximum data (word) */N#define NMA$C_PCXP_MWI 1151 /* Maximum window (byte) */N#define NMA$C_PCXP_MCL 1152 /* Maximum clears (byte) */N#define NMA$C_PCXP_MRS 1153 /* Maximum resets (byte) */N#define NMA$C_PCXP_MST 1154 /* Maximum restarts (byte) */N#define NMA$C_PCXP_CAT 1160 /* Call timer (byte) */>=N#define NMA$C_PCXP_CLT 1161 /* Clear timer (byte) */N#define NMA$C_PCXP_RST 1162 /* Reset timer (byte) */N#define NMA$C_PCXP_STT 1163 /* Restart timer (byte) */N#define NMA$C_PCXP_ITT 1164 /* Interrupt timer (byte) */N#define NMA$C_PCXP_GDT 1170 /* Group DTE (ascic) */N#define NMA$C_PCXP_GNM 1171 /* Group number (word) */V#define NMA$C_PCXP_GTY 1?=172 /* Group type (coded byte of NMA$C_XPRTY_) */N#define NMA$C_PCXP_GNT 1173 /* Group Network name (ascic) */S#define NMA$C_PCXP_MODE 1180 /* DTE mode (coded byte of NMA$C_X25MD_) */N#define NMA$C_PCXP_PROF 1190 /* Profile (ascic) */N/* */N#define NMA$C_PCXP_RSX_PMC 2300 /* Maximum circuits */N/* @= */Q#define NMA$C_PCXP_MCI 2710 /* Maximum circuits, qualified by DTE */N/* */N#define NMA$C_PCXP_SRV_PMC 3300 /* Maximum circuits */N/* */P#define NMA$C_PCXS_STA 1 /* State (coded byte of NMA$C_STATE_) */N#define NMA$C_PCXS_CTM 100 /* Counter timerA= (word) */N#define NMA$C_PCXS_ACI 200 /* Active circuits (word) */N#define NMA$C_PCXS_DST 300 /* Destination (ascic) */N#define NMA$C_PCXS_MCI 310 /* Maximum circuits (word) */N#define NMA$C_PCXS_NOD 320 /* Node */N#define NMA$C_PCXS_USR 330 /* Username */N#define NMA$C_PCXS_SPW 331 /* Password to set (ascic) */\#dB=efine NMA$C_PCXS_RPW 331 /* Password to read (coded byte of NMA$C_NODPW_) */N#define NMA$C_PCXS_ACC 332 /* Account (ascic) */N#define NMA$C_PCXS_OBJ 340 /* Object */N#define NMA$C_PCXS_PRI 350 /* Priority (byte) */N#define NMA$C_PCXS_CMK 351 /* Call mask (byte-counted hex) */N#define NMA$C_PCXS_CVL 352 /* Call value (byte-counted hex) */N#define NMA$C_C=PCXS_GRP 353 /* Group (ascic) */U#define NMA$C_PCXS_SDTE 354 /* Sending DTE, formally "Number" (ascic) */N#define NMA$C_PCXS_SAD 355 /* Subaddresses */X#define NMA$C_PCXS_RED 390 /* Redirect reason (coded byte nma$c_x25red_) */N#define NMA$C_PCXS_CDTE 391 /* Called DTE (ascic) */N#define NMA$C_PCXS_RDTE 392 /* Receiving DTE (ascic) */N#define NMA$C_PCXS_NETD= 393 /* Network (ascic) */N#define NMA$C_PCXS_EMK 394 /* Extension mask (ascic) */N#define NMA$C_PCXS_EVL 395 /* Extension value (ascic) */N#define NMA$C_PCXS_IDTE 396 /* Incoming address (ascii) */N/* */N#define NMA$C_PCXS_RSX_5ST 2310 /* State */N/* 0, On E= */N#define NMA$C_PCXS_FIL 2710 /* Object filespec (ascic) */N/* */N#define NMA$C_PCXS_SRV_5ST 3310 /* State */N/* 0, On */Q#define NMA$C_PCXT_STA 0 /* State (coded byte of NMA$C_STATE_) */N#define NMA$C_PCXT_BSZ 100 /* Buffer size (word) F= */N#define NMA$C_PCXT_MBK 101 /* Maximum blocks/file (word) */N#define NMA$C_PCXT_FNM 102 /* Filename (ascic) */O#define NMA$C_PCXT_MBF 103 /* Maximum number of buffers (word) */O#define NMA$C_PCXT_CPL 104 /* Global data capture limit (word) */P#define NMA$C_PCXT_MVR 105 /* Maximum trace file version (word) */N#define NMA$C_PCXT_TPT 106 /* Trace point name (ascic) */N#define NMG=A$C_PCXT_CPS 110 /* Per-trace capture size (word) */[#define NMA$C_PCXT_TST 111 /* Per-trace state (coded byte of NMA$C_STATE_) */N/* */Q#define NMA$C_PCNO_STA 0 /* State (coded byte of NMA$C_STATE_) */N#define NMA$C_PCNO_PHA 10 /* Physical address (NI address) */N#define NMA$C_PCNO_IDE 100 /* Identification (ascic) */N#define NMA$C_PCNOH=_MVE 101 /* Management version (3 bytes) */N#define NMA$C_PCNO_SLI 110 /* Service circuit (ascic) */N#define NMA$C_PCNO_SPA 111 /* Service password (8 bytes) */Y#define NMA$C_PCNO_SDV 112 /* Service device (coded byte of NMA$C_SOFD_) */R#define NMA$C_PCNO_CPU 113 /* CPU type (coded byte of NMA$C_CPU_) */N#define NMA$C_PCNO_HWA 114 /* Hardware address (NI address) */^#define NMA$C_PCNO_SNV 115 I= /* Service node version (coded byte of NMA$C_SVN_) */N#define NMA$C_PCNO_LOA 120 /* Load file (ascic) */N#define NMA$C_PCNO_SLO 121 /* Secondary loader (ascic) */N#define NMA$C_PCNO_TLO 122 /* Tertiary loader (ascic) */N#define NMA$C_PCNO_DFL 123 /* Diagnostic file (ascic) */X#define NMA$C_PCNO_STY 125 /* Software type (coded byte of NMA$C_SOFT_) */N#define NMA$C_PCNO_SID 126 J= /* Software ID (ascic) */N#define NMA$C_PCNO_MFL 127 /* Management File (ascic) */N#define NMA$C_PCNO_DUM 130 /* Dump file (ascic) */N#define NMA$C_PCNO_SDU 131 /* Secondary dumper (ascic) */N#define NMA$C_PCNO_DAD 135 /* Dump address (longword) */N#define NMA$C_PCNO_DCT 136 /* Dump count (longword) */N#define NMA$C_PCNO_OHO 140 /* Host (read K=only parameter) */N#define NMA$C_PCNO_IHO 141 /* Host (write only parameter) */N#define NMA$C_PCNO_LPC 150 /* Loop count (word) */N#define NMA$C_PCNO_LPL 151 /* Loop length (word) */Y#define NMA$C_PCNO_LPD 152 /* Loop Data type (coded byte of NMA$C_LOOP_) */[#define NMA$C_PCNO_LPA 153 /* Loop assistant physical address (NI address) */N#define NMA$C_PCNO_LPH 154 /* Loop help tL=ype (coded byte) */N#define NMA$C_PCNO_LPN 155 /* Loop circuit node */N#define NMA$C_PCNO_LAN 156 /* Loop circuit assistant node */N#define NMA$C_PCNO_CTI 160 /* Counter timer (word) */N#define NMA$C_PCNO_NNA 500 /* Name */N#define NMA$C_PCNO_NLI 501 /* Circuit (ascic) */N#define NMA$C_PCNO_ADD 502 /* Address */NM=#define NMA$C_PCNO_ITI 510 /* Incoming timer (word) */N#define NMA$C_PCNO_OTI 511 /* Outgoing timer (word) */N#define NMA$C_PCNO_IPR 522 /* Incoming Proxy */N#define NMA$C_PCNO_OPR 523 /* Outgoing Proxy */N#define NMA$C_PCNO_ACL 600 /* Active links (word) */N#define NMA$C_PCNO_DEL 601 /* Delay (word) */N#define NMA$C_PCNO_NVE 700N= /* Nsp version (3 bytes) */N#define NMA$C_PCNO_MLK 710 /* Maximum links (word) */N#define NMA$C_PCNO_DFA 720 /* Delay factor (byte) */N#define NMA$C_PCNO_DWE 721 /* Delay weight (byte) */N#define NMA$C_PCNO_IAT 722 /* Inactivity timer (word) */N#define NMA$C_PCNO_RFA 723 /* Retransmit factor (word) */\#define NMA$C_PCNO_DTY 810 /* DestinatiO=on Type (coded byte of NMA$C_XPRTY_) */N#define NMA$C_PCNO_DCO 820 /* Destination Cost (word) */N#define NMA$C_PCNO_DHO 821 /* Destination Hops (byte) */N#define NMA$C_PCNO_DLI 822 /* Destination circuit (ascic) */N#define NMA$C_PCNO_NND 830 /* Next node to destination */N#define NMA$C_PCNO_RVE 900 /* Routing version (3 bytes) */Y#define NMA$C_PCNO_ETY 901 /* Executor Type (coded P=byte of NMA$C_NODTY_) */N#define NMA$C_PCNO_RTI 910 /* Routing timer (word) */N#define NMA$C_PCNO_SAD 911 /* Subaddress (2 words) */N#define NMA$C_PCNO_BRT 912 /* Broadcast routing timer (word) */N#define NMA$C_PCNO_MAD 920 /* Maximum address (word) */N#define NMA$C_PCNO_MLN 921 /* Maximum circuits (word) */N#define NMA$C_PCNO_MCO 922 /* Maximum cost (word) */Q=N#define NMA$C_PCNO_MHO 923 /* Maximum hops (byte) */N#define NMA$C_PCNO_MVI 924 /* Maximum visits (byte) */N#define NMA$C_PCNO_MAR 925 /* Maximum areas (byte) */R#define NMA$C_PCNO_MBE 926 /* Maximum broadcast nonrouters (word) */O#define NMA$C_PCNO_MBR 927 /* Maximum broadcast routers (word) */N#define NMA$C_PCNO_AMC 928 /* Area maximum cost (word) */N#define NMA$C_PCNOR=_AMH 929 /* Area maximum hops (byte) */N#define NMA$C_PCNO_MBU 930 /* Maximum buffers (word) */N#define NMA$C_PCNO_BUS 931 /* Executor buffer size (word) */N#define NMA$C_PCNO_SBS 932 /* Segment buffer size (word) */N#define NMA$C_PCNO_MPS 933 /* Maximum path splits */N#define NMA$C_PCNO_FBS 933 /* Forwarding buffer size (word) */N/* S= */N#define NMA$C_PCNO_RSX_RPA 2300 /* Receive password */N/* 0, Password set */N#define NMA$C_PCNO_RSX_TPA 2301 /* Transmit password */N/* 0, Password set */N#define NMA$C_PCNO_RSX_VER 2310 /* Verification state */N/* 0, On T= */N#define NMA$C_PCNO_PUS 2704 /* Privileged user id */N#define NMA$C_PCNO_PAC 2705 /* Privileged account */N#define NMA$C_PCNO_PPW 2706 /* Privileged password */N#define NMA$C_PCNO_NUS 2712 /* Non-privileged user id */N#define NMA$C_PCNO_NAC 2713 /* Non-privileged account */N#define NMA$C_PCNO_NPW 2714 /* Non-privileged password */N#define NMA$C_PCU=NO_RPA 2720 /* Receive password */N#define NMA$C_PCNO_TPA 2721 /* Transmit password */Q#define NMA$C_PCNO_ACC 2730 /* Access (coded byte of NMA$C_ACES_) */Y#define NMA$C_PCNO_DAC 2731 /* Default access (coded byte of NMA$C_ACES_) */N#define NMA$C_PCNO_PIQ 2740 /* Pipeline quota (word) */T#define NMA$C_PCNO_ALI 2742 /* Alias incoming (coded byte of ALIINC)) */N#define NMA$C_PCNO_AV=LM 2743 /* Alias Maximum links */N#define NMA$C_PCNO_ALN 2744 /* Alias node */x#define NMA$C_PCNO_PRX 2750 /* Proxy access (coded byte of NMA$C_ACES_) !! Obsolete: Only for LIST/PURGE */_#define NMA$C_PCNO_DPX 2751 /* Default proxy access (coded byte of NMA$C_ACES_) */N#define NMA$C_PCNO_COP 2760 /* Remote nodefor COPY command */N#define NMA$C_PCNO_INB 2765 /* Inbound for async DECneW=t. */N#define NMA$C_PCNO_LAA 2770 /* Load Assist Agent */N#define NMA$C_PCNO_LAP 2771 /* Load Assist Parameter */N#define NMA$C_PCNO_PSP 2780 /* Path Splits Policy */N/* (Coded byte f PSPCY) */N#define NMA$C_PCNO_MDO 2785 /* Maximum Declared Objects */N#define NMA$C_PCNO_DNS 2790 /* DNS interface */N#define NMA$X=C_PCNO_IDP 2791 /* IDP of ISO address */N#define NMA$C_PCNO_DNM 2792 /* DNS namespace */N/* */N#define NMA$C_PCNO_SRV_RPA 3300 /* Receive password */N/* 0, Password set */N#define NMA$C_PCNO_SRV_TPA 3301 /* Transmit password */N/* 0, Password set Y= */N#define NMA$C_PCNO_SRV_VER 3310 /* Verification state */N/* 0, On */N#define NMA$C_PCNO_SRV_ACB 3402 /* Active control buffers */N#define NMA$C_PCNO_SRV_ASB 3404 /* Active small buffers */N#define NMA$C_PCNO_SRV_ALB 3406 /* Active large buffers */N#define NMA$C_PCNO_SRV_MCB 3410 /* Maximum control buffeZ=rs */N#define NMA$C_PCNO_SRV_MSB 3420 /* Maximum small buffers */N#define NMA$C_PCNO_SRV_MLB 3430 /* Maximum large buffers */N#define NMA$C_PCNO_SRV_LBS 3431 /* Large buffer size */N#define NMA$C_PCNO_SRV_NRB 3440 /* Minimum receive buffers */N#define NMA$C_PCNO_SRV_CPT 3450 /* CEX pool: total bytes */N#define NMA$C_PCNO_SRV_CPF 3452 /* CEX pool: number of segments */N#define NM[=A$C_PCNO_SRV_CPL 3454 /* CEX pool: largest segment */N#define NMA$C_PCNO_SRV_XPT 3460 /* Extended pool: total bytes */P#define NMA$C_PCNO_SRV_XPF 3462 /* Extended pool: number of segments */N#define NMA$C_PCNO_SRV_XPL 3464 /* Extended pool: largest segment */N/* */Q#define NMA$C_PCAR_STA 0 /* State (coded byte of NMA$C_STATE_) */N#define NMA$C_PCAR_COS 820 \= /* Cost (word) */N#define NMA$C_PCAR_HOP 821 /* Hops (byte) */N#define NMA$C_PCAR_CIR 822 /* Circuit (ascic) */N#define NMA$C_PCAR_NND 830 /* Next node to area */N/* */N#define NMA$C_PCOB_OAN 400 /* Active name */N#define NMA$C_PCOB_OAC 410 /* Active links ]= */N#define NMA$C_PCOB_ONA 500 /* Name */N#define NMA$C_PCOB_OCO 510 /* Copies */N#define NMA$C_PCOB_OUS 511 /* User */N#define NMA$C_PCOB_OVE 520 /* Verification */N#define NMA$C_PCOB_NAM 500 /* Name */N#define NMA$C_PCOB_NUM 513 /* Number */N#d^=efine NMA$C_PCOB_FID 530 /* File id */N#define NMA$C_PCOB_PID 535 /* Process id */N#define NMA$C_PCOB_PRV 540 /* Privilege list */N#define NMA$C_PCOB_OCPRV 542 /* Outgoing connect privilege list */N#define NMA$C_PCOB_USR 550 /* User id */N#define NMA$C_PCOB_ACC 551 /* Account */N#define NMA$C_PCOB_PSW 552 _= /* Password */W#define NMA$C_PCOB_PRX 560 /* Proxy access (coded byte of NMA$C_ACES_) */W#define NMA$C_PCOB_ALO 565 /* Alias outgoing- coded byte of nma$c_alout */W#define NMA$C_PCOB_ALI 566 /* Alias incoming- coded byte of nma$c_alinc */N/* */N#define NMA$C_PCLK_STA 0 /* State */N#define NMA$C_PCLK_PID 1`=01 /* Process id */N#define NMA$C_PCLK_NID 102 /* Partner Node */N#define NMA$C_PCLK_LAD 105 /* Link address [V2 only] */N/* entity is node rather than link ! */N#define NMA$C_PCLK_DLY 110 /* Round trip delay time (word) */N#define NMA$C_PCLK_RLN 120 /* Remote link number (word) */]#define NMA$C_PCLK_RID 121 /* Remote a=identification, PID or username (ascic) */N#define NMA$C_PCLK_USR 130 /* Username of link owner (ascic) */Q#define NMA$C_PCLK_PRC 131 /* Process name of link owner (ascic) */N/* */N#define NMA$C_CTCIR_ZER 0 /* Seconds since last zeroed */N#define NMA$C_CTCIR_APR 800 /* Terminating packets received */N#define NMA$C_CTCIR_DPS 801 /* Originating pb=ackets sent */N#define NMA$C_CTCIR_ACL 802 /* Terminating congestion loss */N#define NMA$C_CTCIR_CRL 805 /* Corruption loss */N#define NMA$C_CTCIR_TPR 810 /* Transit packets received */N#define NMA$C_CTCIR_TPS 811 /* Transit packets sent */N#define NMA$C_CTCIR_TCL 812 /* Transit congestion loss */N#define NMA$C_CTCIR_LDN 820 /* Circuit down */N#dc=efine NMA$C_CTCIR_IFL 821 /* Initialization failure */N#define NMA$C_CTCIR_AJD 822 /* Adjacency down events */N#define NMA$C_CTCIR_PAJ 900 /* Peak adjacencies */N#define NMA$C_CTCIR_BRC 1000 /* Bytes received */N#define NMA$C_CTCIR_BSN 1001 /* Bytes sent */N#define NMA$C_CTCIR_MBY 1002 /* Multicast bytes received */N#define NMA$C_CTCIR_DBR 1010d= /* Data blocks received */N#define NMA$C_CTCIR_DBS 1011 /* Data blocks sent */N#define NMA$C_CTCIR_DEI 1020 /* Data errors inbound */N#define NMA$C_CTCIR_DEO 1021 /* Data errors outbound */N#define NMA$C_CTCIR_RRT 1030 /* Remote reply timeouts */N#define NMA$C_CTCIR_LRT 1031 /* Local reply timeouts */N#define NMA$C_CTCIR_RBE 1040 /* Remote buffe=er errors */N#define NMA$C_CTCIR_LBE 1041 /* Local buffer errors */N#define NMA$C_CTCIR_SIE 1050 /* Selection intervals elapsed */N#define NMA$C_CTCIR_SLT 1051 /* Selection timeouts */N#define NMA$C_CTCIR_UBU 1065 /* NI user buffer unavailable */N#define NMA$C_CTCIR_RPE 1100 /* Remote process errors [V2 only] */N#define NMA$C_CTCIR_LPE 1101 /* Local process errors [V2 only] */Nf=#define NMA$C_CTCIR_LIR 1240 /* Locally initiated resets */N#define NMA$C_CTCIR_RIR 1241 /* Remotely initiated resets */N#define NMA$C_CTCIR_NIR 1242 /* Network initiated resets */N/* */N#define NMA$C_CTCIR_MNE 2701 /* Multicast received for protocol */N/* type, but not enabled */N#define NMA$C_CTCIR_ERI 27g=50 /* PCL Errors inbound, bit-mapped */N/* 0 CRC error on receive */N#define NMA$C_CTCIR_ERO 2751 /* PCL Errors outbound, bit-mapped */N/* 1 CRC on transmit */N#define NMA$C_CTCIR_RTO 2752 /* PCL Remote timeouts, bit-mapped */N/* 0 Receiver busy */N#define NMA$C_CTCIR_LTO 2753 /* PCL Localh= timeouts */N#define NMA$C_CTCIR_BER 2754 /* PCL Remote buffer errors */N#define NMA$C_CTCIR_BEL 2755 /* PCL Local buffer errors */N/* */N#define NMA$C_CTLIN_ZER 0 /* Seconds since last zeroed */R#define NMA$C_CTLIN_APR 800 /* Arriving packets received [V2 only] */O#define NMA$C_CTLIN_DPS 801 /* Departing packets sent [V2 onlyi=] */Q#define NMA$C_CTLIN_ACL 802 /* Arriving congestion loss [V2 only] */Q#define NMA$C_CTLIN_TPR 810 /* Transit packets received [V2 only] */N#define NMA$C_CTLIN_TPS 811 /* Transit packets sent [V2 only] */P#define NMA$C_CTLIN_TCL 812 /* Transit congestion loss [V2 only] */N#define NMA$C_CTLIN_LDN 820 /* Line down [V2 only] */O#define NMA$C_CTLIN_IFL 821 /* Initialization failure [V2 only] */N#definj=e NMA$C_CTLIN_BRC 1000 /* Bytes received */N#define NMA$C_CTLIN_BSN 1001 /* Bytes sent */N#define NMA$C_CTLIN_MBY 1002 /* Multicast bytes received */N#define NMA$C_CTLIN_DBR 1010 /* Data blocks received */N#define NMA$C_CTLIN_DBS 1011 /* Data blocks sent */N#define NMA$C_CTLIN_MBL 1012 /* Multicast blocks received */N#define NMA$C_CTLIN_BID 1013 k= /* Blocks sent, initially deferred */N#define NMA$C_CTLIN_BS1 1014 /* Blocks sent, single collision */O#define NMA$C_CTLIN_BSM 1015 /* Blocks sent, multiple collisions */N#define NMA$C_CTLIN_MFC 1016 /* MAC frame count */N#define NMA$C_CTLIN_MEC 1017 /* MAC error count */N#define NMA$C_CTLIN_MLC 1018 /* MAC lost count */N#define NMA$C_CTLIN_DEI 1020 /* Data errors il=nbound */N#define NMA$C_CTLIN_DEO 1021 /* Data errors outbound */N#define NMA$C_CTLIN_RRT 1030 /* Remote reply timeouts */N#define NMA$C_CTLIN_LRT 1031 /* Local reply timeouts */N#define NMA$C_CTLIN_RII 1032 /* Ring initializations initiated */N#define NMA$C_CTLIN_RIR 1033 /* Ring initializations received */N#define NMA$C_CTLIN_RBI 1034 /* Ring beacons initiated */N#dm=efine NMA$C_CTLIN_DAT 1035 /* Duplicate address test failures */N#define NMA$C_CTLIN_DTD 1036 /* Duplicate tokens detected */N#define NMA$C_CTLIN_RPR 1037 /* Ring purge errors */N#define NMA$C_CTLIN_FSE 1038 /* FCI strip errors */N#define NMA$C_CTLIN_TRI 1039 /* Traces initiated */N#define NMA$C_CTLIN_RBE 1040 /* Remote buffer errors */N#define NMA$C_CTLIN_LBE 1041n= /* Local buffer errors */N#define NMA$C_CTLIN_TRR 1042 /* Traces initiated */N#define NMA$C_CTLIN_DBC 1043 /* Directed beacons received */T#define NMA$C_CTLIN_SIE 1050 /* Selection intervals elapsed [V2 only] */N#define NMA$C_CTLIN_SLT 1051 /* Selection timeouts [V2 only] */N#define NMA$C_CTLIN_SFL 1060 /* Send failure */N#define NMA$C_CTLIN_CDC 1061 /* Collio=sion detect check failure */N#define NMA$C_CTLIN_RFL 1062 /* Receive failure */N#define NMA$C_CTLIN_UFD 1063 /* Unrecognized frame destination */N#define NMA$C_CTLIN_OVR 1064 /* Data overrun */N#define NMA$C_CTLIN_SBU 1065 /* System buffer unavailable */N#define NMA$C_CTLIN_UBU 1066 /* User buffer unavailable */N#define NMA$C_CTLIN_SFR 1070 /* Send failures (Token Ring) p= */N#define NMA$C_CTLIN_RFR 1071 /* Receive failures (Token Ring) */N#define NMA$C_CTLIN_IFR 1072 /* Insertion failures */N#define NMA$C_CTLIN_RGF 1073 /* Ring failures */N#define NMA$C_CTLIN_RPG 1074 /* Ring purges */N#define NMA$C_CTLIN_MNC 1075 /* Monitor contention */N#define NMA$C_CTLIN_BCN 1076 /* Beaconing conditions */N#define NMA$C_CTLIN_q=LER 1080 /* Line errors */N#define NMA$C_CTLIN_IER 1081 /* Internal errors */N#define NMA$C_CTLIN_BER 1082 /* Burst errors */N#define NMA$C_CTLIN_RAE 1083 /* Ring poll AC errors */N#define NMA$C_CTLIN_ADS 1084 /* Abort delimiters sent */#define NMA$C_CTLIN_PIE 1085 /* Private isolating errors r= \ */N#define NMA$C_CTLIN_TLF 1086 /* Transmit lost frames */N#define NMA$C_CTLIN_RCE 1087 /* Receiver congestion errors */N#define NMA$C_CTLIN_FCE 1088 /* Frame copied errors */b#define NMA$C_CTLIN_FER 1089 /* Frequency errors (802.5 defined but not implemented) */N#define NMA$C_CTLIN_TER 1090 /* Token errors */N#define NMA$C_CTLIN_PNE 1091 /* Private non-isolatis=ng errors */N#define NMA$C_CTLIN_RPE 1100 /* Remote process errors */N#define NMA$C_CTLIN_LPE 1101 /* Local process errors */J#define NMA$C_CTLIN_EBE 1200 /* Elasticity buffer errors */N#define NMA$C_CTLIN_LCT 1201 /* LCT rejects */N#define NMA$C_CTLIN_LEM 1202 /* LEM rejects */N#define NMA$C_CTLIN_LNK 1203 /* Link errors */N#define NMA$ t=C_CTLIN_CNC 1204 /* Connections completed */N/* */N#define NMA$S_NMADEF1 2 /* Old size name - synonym */ typedef struct _nma1 { __union {& unsigned short int nma$w_node; __struct {% unsigned nma$v_addr : 10;$ unsigned nma$v_area : 6; } nma$r_node_bits0;N/* u= */N/* Parameter ID word (DATA ID) */N/* */ __struct {N unsigned nma$v_pty_typ : 15; /* Type mask */' unsigned nma$v_fill_2_ : 1; } nma$r_node_bits1;N/* */N/* Parameter data type byte (DATA TYPE) v= */N/* */ __struct {N unsigned nma$v_pty_cle : 6; /* Coded length mask */N unsigned nma$v_pty_mul : 1; /* Coded multiple indicator */N unsigned nma$v_pty_cod : 1; /* Coded indicator */ } nma$r_node_bits2; __struct {& unsigned nma$$_fill_7 : 6;N unsigned nma$v_pty_cmu : 2; /* Coded multipl w=e */ } nma$r_node_bits3; __struct {N unsigned nma$v_pty_nle : 4; /* Number length mask */N unsigned nma$v_pty_nty : 2; /* Number type mask */N unsigned nma$v_pty_asc : 1; /* Ascii image indicator */' unsigned nma$v_fill_3_ : 1; } nma$r_node_bits4;N/* NTY values (how to display number): */N/* Define standard values for x=the DATA TYPE byte */N/* */N/* Parameters for 802 control support */N/* */N/* Circuit parameters */N/* */N/* RSX-specific circuit parameters y= */N/* */N/* VMS-specific circuit NICE parameters [2700 - 2799] */N/* */N/* */N/* VMS-specific datalink only circuit parameters [2800 - 2899] */N/* */N/*z= (these will never be used in NICE messages). */N/* */N/* Server Base specific Circuit parameters */N/* */N/* Line parameters */N/* */N/* FDDI-specific line parame{=ters */N/* */N/* Token Ring specific line parameters */N/* (Upstream Neighbor Address used by both FDDI and Token Ring) */N/* */N/* FDDI-specific line parameters continued */N/* |= */N/* RSX-specific line parameters */N/* */N/* 1, Topdown */N/* VMS-specific line NICE parameters [2700 - 2799] */N/* */N/* VMS-specific datalink only line parameters [2800 - 2899] */N}=/* */N/* (these will never be used in NICE messages). */N/* */N/* Server Base specific line parameters */N/* */N/* Communication Medium parameters */N/* ~= */N/* Console module parameters */N/* */N/* Loader module parameters */N/* */N/* Looper module parameters */N/* = */N/* Configurator module parameters */N/* */N/* Logging parameters */N/* */N/* X.25 Access module parameters */N/* */=N/* RSX-specific X.25-Access module parameters */N/* */N/* Server Base specific X.25-Access module parameters */N/* */N/* X.25 Protocol module parameters */N/* */N/* RSX-specific X.2=5-Protocol Module parameters */N/* */N/* VMS-specific X25-PROTOCOL NICE parameters [2700 - 2799] */N/* */N/* Server Base specific X.25-Protocol Module parameters */N/* */N/* X.25 server module parameters = */N/* */N/* RSX-specific X.25-Server Module parameters */N/* */N/* 1, Off */N/* */N/* VMS-specific X25-SERVER NICE parameters [2700 - 2799] =*/N/* */N/* Server Base specific X.25-Server Module parameters */N/* */N/* 1, Off */N/* */N/* X.25 trace module parameters (VMS-specific) */N/* = */N/* Node parameters */N/* */N/* RSX-Specific Node (Executor) parameters */N/* */N/* 1, Off */N/* = */N/* VMS-specific node parameters */N/* */N/* Server Base specific Node (Executor) parameters */N/* */N/* 1, Off */N/* Area parameters = */N/* */N/* VMS-specific object parameters */N/* */N/* VMS-specific link parameters */N/* */N/* CM-1/2, DU-2 (link !), HI-4 (pid) */N/* Circuit counte=rs */N/* */N/* VMS-specific circuit counters */N/* */N/* 2 Timeout on word */N/* 1 Transmitter offline */N/* 2 Receiver offline = */N/* Line counters */N/* */N/* Line counter flags (byte offset will be 0) */N/* */ } nma$r_nma1_fill_union; } NMA1; #if !defined(__VAXC)3#define nma$w_node nma$r_nma1_fill_union.nma$w_nodeD#define nma$v_addr nma$r=_nma1_fill_union.nma$r_node_bits0.nma$v_addrD#define nma$v_area nma$r_nma1_fill_union.nma$r_node_bits0.nma$v_areaJ#define nma$v_pty_typ nma$r_nma1_fill_union.nma$r_node_bits1.nma$v_pty_typJ#define nma$v_pty_cle nma$r_nma1_fill_union.nma$r_node_bits2.nma$v_pty_cleJ#define nma$v_pty_mul nma$r_nma1_fill_union.nma$r_node_bits2.nma$v_pty_mulJ#define nma$v_pty_cod nma$r_nma1_fill_union.nma$r_node_bits2.nma$v_pty_codJ#define nma$v_pty_cmu nma$r_nma1_fill_union.nma$r_node_bits3.nma$v_pty_cmuJ#define nm =a$v_pty_nle nma$r_nma1_fill_union.nma$r_node_bits4.nma$v_pty_nleJ#define nma$v_pty_nty nma$r_nma1_fill_union.nma$r_node_bits4.nma$v_pty_ntyJ#define nma$v_pty_asc nma$r_nma1_fill_union.nma$r_node_bits4.nma$v_pty_asc"#endif /* #if !defined(__VAXC) */ #define NMA$M_CTLIN_BTL 0x8#define NMA$M_CTLIN_FCS 0x10#define NMA$M_CTLIN_TRJ 0x20N#define NMA$S_NMADEF2 1 /* Old size name - synonym */ typedef struct _nma2 { __union {N char nma$$_fill_8; = /* byte of flags */ __struct {N unsigned nma$$_fill_9 : 3; /* skip bits 0,1,2 */N unsigned nma$v_ctlin_btl : 1; /* block too long */N unsigned nma$v_ctlin_fcs : 1; /* frame check */N unsigned nma$v_ctlin_trj : 1; /* REJ sent */' unsigned nma$v_fill_4_ : 2; } nma$r_fill_8_bits; } nma$r_nma2_fill_union; } NM=A2; #if !defined(__VAXC)O#define nma$v_ctlin_btl nma$r_nma2_fill_union.nma$r_fill_8_bits.nma$v_ctlin_btlO#define nma$v_ctlin_fcs nma$r_nma2_fill_union.nma$r_fill_8_bits.nma$v_ctlin_fcsO#define nma$v_ctlin_trj nma$r_nma2_fill_union.nma$r_fill_8_bits.nma$v_ctlin_trj"#endif /* #if !defined(__VAXC) */ #define NMA$M_CTLIN_RRJ 0x8N#define NMA$S_NMADEF3 1 /* Old size name - synonym */ typedef struct _nma3 { __union {N char nma$$_fill_10; = /* byte of flags */ __struct {N unsigned nma$$_fill_11 : 3; /* skip bits 0,1,2 */N unsigned nma$v_ctlin_rrj : 1; /* REJ received */' unsigned nma$v_fill_5_ : 4;! } nma$r_fill_10_bits; } nma$r_nma3_fill_union; } NMA3; #if !defined(__VAXC)P#define nma$v_ctlin_rrj nma$r_nma3_fill_union.nma$r_fill_10_bits.nma$v_ctlin_rrj"#endif /* #if !defined(__VAXC) */ #def =ine NMA$M_CTLIN_RRN 0x4N#define NMA$S_NMADEF4 1 /* Old size name - synonym */ typedef struct _nma4 { __union {N char nma$$_fill_12; /* byte of flags */ __struct {N unsigned nma$$_fill_13 : 2; /* skip bits 0,1 */N unsigned nma$v_ctlin_rrn : 1; /* RNR received */' unsigned nma$v_fill_6_ : 5;! } nma$r_fill_12_bits; } nma$r_=nma4_fill_union; } NMA4; #if !defined(__VAXC)P#define nma$v_ctlin_rrn nma$r_nma4_fill_union.nma$r_fill_12_bits.nma$v_ctlin_rrn"#endif /* #if !defined(__VAXC) */ #define NMA$M_CTLIN_TRN 0x4N#define NMA$S_NMADEF5 1 /* Old size name - synonym */ typedef struct _nma5 { __union {N char nma$$_fill_14; /* byte of flags */ __struct {N unsigned nma$$_fill_15 : 2; /* skip bits 0,1 = */N unsigned nma$v_ctlin_trn : 1; /* RNR sent */' unsigned nma$v_fill_7_ : 5;! } nma$r_fill_14_bits; } nma$r_nma5_fill_union; } NMA5; #if !defined(__VAXC)P#define nma$v_ctlin_trn nma$r_nma5_fill_union.nma$r_fill_14_bits.nma$v_ctlin_trn"#endif /* #if !defined(__VAXC) */ #define NMA$M_CTLIN_INR 0x10#define NMA$M_CTLIN_FMS 0x20N#define NMA$S_NMADEF6 1 /* Old size name - synonym */ =typedef struct _nma6 { __union {N char nma$$_fill_16; /* byte of flags */ __struct {N unsigned nma$$_fill_17 : 4; /* skip bits 0,1,2,3 */N unsigned nma$v_ctlin_inr : 1; /* invalid N(R) received */N unsigned nma$v_ctlin_fms : 1; /* FRMR sent */' unsigned nma$v_fill_8_ : 2;! } nma$r_fill_16_bits; } nma$r_nma6_fill_union; } NMA6 =; #if !defined(__VAXC)P#define nma$v_ctlin_inr nma$r_nma6_fill_union.nma$r_fill_16_bits.nma$v_ctlin_inrP#define nma$v_ctlin_fms nma$r_nma6_fill_union.nma$r_fill_16_bits.nma$v_ctlin_fms"#endif /* #if !defined(__VAXC) */ #define NMA$M_CTLIN_TUN 0x4#define NMA$M_CTLIN_RUN 0x10#define NMA$M_CTLIN_FMR 0x20N#define NMA$C_CTLIN_MBS 2701 /* Multicast packets transmitted */N#define NMA$C_CTLIN_MSN 2702 /* Multicast bytes transmitted */N#define NMA$C_CTLIN_RM=E 2750 /* PCL Remote errors, bit-mapped */N/* 0 TDM bus busy */N#define NMA$C_CTLIN_LCE 2751 /* PCL Local errors, bit-mapped */N/* 0 Transmitter overrun */V#define NMA$C_CTLIN_MSE 2752 /* PCL master/secondary errors, bit-mapped */N/* 1 Master down */N#define NMA$C_CTNOD_ZER 0 =/* Seconds since last zeroed */N#define NMA$C_CTNOD_BRC 600 /* Bytes received */N#define NMA$C_CTNOD_BSN 601 /* Bytes sent */N#define NMA$C_CTNOD_MRC 610 /* Messages received */N#define NMA$C_CTNOD_MSN 611 /* Messages sent */N#define NMA$C_CTNOD_CRC 620 /* Connects received */N#define NMA$C_CTNOD_CSN 621 /* Connects sent = */N#define NMA$C_CTNOD_RTO 630 /* Response timeouts */O#define NMA$C_CTNOD_RSE 640 /* Received connect resource errors */N#define NMA$C_CTNOD_BUN 650 /* Buffer unavailable */N#define NMA$C_CTNOD_MLL 700 /* Maximum logical links active */N#define NMA$C_CTNOD_APL 900 /* Aged packet loss */N#define NMA$C_CTNOD_NUL 901 /* Node unreachable packet loss */N#define NM=A$C_CTNOD_NOL 902 /* Node out-of-range packet loss */N#define NMA$C_CTNOD_OPL 903 /* Oversized packet loss */N#define NMA$C_CTNOD_PFE 910 /* Packet format error */N#define NMA$C_CTNOD_RUL 920 /* Partial routing update loss */N#define NMA$C_CTNOD_VER 930 /* Verification reject */N/* */N#define NMA$C_CTNOD_SRV_SYC 3310 = /* Control buffer failures */N#define NMA$C_CTNOD_SRV_SYS 3320 /* Small buffer failures */N#define NMA$C_CTNOD_SRV_SYL 3330 /* Large buffer failures */N#define NMA$C_CTNOD_SRV_SYR 3340 /* Receive buffer failures */N/* */N#define NMA$C_CTXP_ZER 0 /* Seconds since last zeroed */N#define NMA$C_CTXP_BRC 1000 /* Bytes received = */N#define NMA$C_CTXP_BSN 1001 /* Bytes sent */N#define NMA$C_CTXP_BLR 1010 /* Data blocks received */N#define NMA$C_CTXP_BLS 1011 /* Data blocks sent */N#define NMA$C_CTXP_CRC 1200 /* Calls received */N#define NMA$C_CTXP_CSN 1201 /* Calls sent */N#define NMA$C_CTXP_FSR 1210 /* Fast selects received */N#define =NMA$C_CTXP_FSS 1211 /* Fast selects sent */O#define NMA$C_CTXP_MSA 1220 /* Maximum switched circuits active */N#define NMA$C_CTXP_MCA 1221 /* Maximum channels active */N#define NMA$C_CTXP_RSE 1230 /* Received call resource errors */N#define NMA$C_CTXP_LIR 1240 /* Locally initiated resets */N#define NMA$C_CTXP_RIR 1241 /* Remotely initiated resets */N#define NMA$C_CTXP_NIR 1242 = /* Network initiated resets */N#define NMA$C_CTXP_RST 1250 /* Restarts */N/* */N#define NMA$C_CTXS_ZER 0 /* Seconds since last zeroed */N#define NMA$C_CTXS_MCA 200 /* Maximum circuits active */T#define NMA$C_CTXS_ICR 210 /* Incoming calls rejected, no resources */S#define NMA$C_CTXS_LLR 211 /* Logical l=inks rejected, no resources */N/* */N#define NMA$C_LOOP_MIX 2 /* Mixed */N#define NMA$C_LOOP_ONE 1 /* Ones */N#define NMA$C_LOOP_ZER 0 /* Zeroes */N/* */N#define NMA$C_LOOP_DCNT 1 /* Default count = */N#define NMA$C_LOOP_DSIZ 40 /* Default message size */N/* */N#define NMA$C_LOOP_XMIT 0 /* Transmit */N#define NMA$C_LOOP_RECV 1 /* Receive */O#define NMA$C_LOOP_FULL 2 /* Full (both transmit and receive) */N/* */N#define NMA$C_ST=ATE_ON 0 /* On */N#define NMA$C_STATE_OFF 1 /* Off */N/* */N#define NMA$C_DNS_ENA 0 /* Enabled */N#define NMA$C_DNS_DIS 1 /* Disabled */N/* */N#define NMA$C_STATE_SER 2 /*= Service (circuit/line only) */N#define NMA$C_STATE_CLE 3 /* Cleared */N/* */N#define NMA$C_STATE_HOL 2 /* Hold */N/* */N#define NMA$C_STATE_SHU 2 /* Shut */N#define NMA$C_STATE_RES 3 /* Restricted = */N#define NMA$C_STATE_REA 4 /* Reachable */N#define NMA$C_STATE_UNR 5 /* Unreachable */I/* PVM0001+ */N#define NMA$C_PCNO_DMAD 1023 /* */B/* PVM0001- */N#define NMA$C_ASS_ENA 0 /* Enabled */N#define NMA$C_ASS_DIS 1 = /* Disabled */N/* */N#define NMA$C_SUR_ENA 0 /* Enabled */N#define NMA$C_SUR_DIS 1 /* Disabled */N/* */N#define NMA$C_LINSS_STA 0 /* Starting */N#define NMA$C_LINSS_REF 1 /* Reflecting = */N#define NMA$C_LINSS_LOO 2 /* Looping */N#define NMA$C_LINSS_LOA 3 /* Loading */N#define NMA$C_LINSS_DUM 4 /* Dumping */N#define NMA$C_LINSS_TRI 5 /* Triggering */N#define NMA$C_LINSS_ASE 6 /* Autoservice */N#define NMA$C_LINSS_ALO 7 /* Autoloading */N#d=efine NMA$C_LINSS_ADU 8 /* Autodumping */N#define NMA$C_LINSS_ATR 9 /* Autotriggering */N#define NMA$C_LINSS_SYN 10 /* Synchronizing */N#define NMA$C_LINSS_FAI 11 /* Failed */N#define NMA$C_LINSS_RUN 12 /* Running */N#define NMA$C_LINSS_UNS 13 /* Unsyncronised */N#define NMA$C_LINSS_IDL 14 = /* Idle (PSI-only) */N/* */N#define NMA$C_CIRTY_POI 0 /* DDCMP Point */N#define NMA$C_CIRTY_CON 1 /* DDCMP Controller */N#define NMA$C_CIRTY_TRI 2 /* DDCMP Tributary */N#define NMA$C_CIRTY_X25 3 /* X25 */Q#define NMA$C_CIRTY_DMC 4 /* DDCMP DMC c=ompatibility mode (DMP) */q/*/* CIRTY_LAPB, 5 /* LAPB *** remove once all references have been changed to LAPB *** */N#define NMA$C_CIRTY_NI 6 /* NI */N#define NMA$C_CIRTY_TRNG 11 /* Token Ring */N#define NMA$C_CIRTY_FDDI 12 /* FDDI */N/* */N#define NMA$C_LINSV_ENA 0 =/* Enabled */N#define NMA$C_LINSV_DIS 1 /* Disabled */N/* */N#define NMA$C_CIRPST_AUT 1 /* Automatic */N#define NMA$C_CIRPST_ACT 2 /* Active */N#define NMA$C_CIRPST_INA 3 /* Inactive */N#define NMA$C_CIRPST_DIE 4 /* Dying = */N#define NMA$C_CIRPST_DED 5 /* Dead */N/* */N#define NMA$C_CIRBLK_ENA 0 /* Enabled */N#define NMA$C_CIRBLK_DIS 1 /* Disabled */N/* */N#define NMA$C_CIRUS_PER 0 /* Permanent */N#define NMA$=C_CIRUS_INC 1 /* Incoming */N#define NMA$C_CIRUS_OUT 2 /* Outgoing */N/* */N#define NMA$C_CIRHS_ENA 0 /* Enabled */N#define NMA$C_CIRHS_DIS 1 /* Disabled */N/* */N#define NMA$C_CIRBF_UNL 255 = /* Unlimited */N/* */N#define NMA$C_CIRVE_ENA 0 /* Enabled */N#define NMA$C_CIRVE_DIS 1 /* Disabled */N#define NMA$C_CIRVE_INB 2 /* Inbound */N/* */N#define NMA$C_CIRXPT_ZND 1 /* Z-node = */N#define NMA$C_CIRXPT_PH2 2 /* Force Phase II on this circuit */N#define NMA$C_CIRXPT_PH3 3 /* Routing III */N#define NMA$C_CIRXPT_RO3 3 /* Routing III */N#define NMA$C_CIRXPT_NR4 4 /* Nonrouting Phase IV */N/* */N#define NMA$C_DPX_FUL 0 /* Full */N#define NM=A$C_DPX_HAL 1 /* Half */N#define NMA$C_DPX_MPT 4 /* Multipoint */N/* */N#define NMA$C_LINCN_NOR 0 /* Normal */N#define NMA$C_LINCN_LOO 1 /* Loop */N/* */N#define NMA$C_LINPR_POI 0 = /* DDCMP Point */N#define NMA$C_LINPR_CON 1 /* DDCMP Controller */N#define NMA$C_LINPR_TRI 2 /* DDCMP Tributary */Q#define NMA$C_LINPR_DMC 4 /* DDCMP DMC compatibility mode (DMP) */N#define NMA$C_LINPR_LAPB 5 /* LAPB */N#define NMA$C_LINPR_NI 6 /* NI */P#define NMA$C_LINPR_BSY 9 /* BISYNC (not rea=lly - just Genbyte) */N#define NMA$C_LINPR_GENBYTE 9 /* Genbyte (real name) */N#define NMA$C_LINPR_LAPBE 10 /* LAPBE */N#define NMA$C_LINPR_TRNG 11 /* Token Ring */N#define NMA$C_LINPR_FDDI 12 /* FDDI */N#define NMA$C_LINPR_EA_HDLC 20 /* Extended addressing HDLC */N#define NMA$C_LINPR_SDLC 21 /* SDLC */S#d=efine NMA$C_LINPR_BISYNC 22 /* IBM Bisync protocol (not BSY framing) */N#define NMA$C_LINPR_SWIFT 23 /* SWIFT Bisync variant */N#define NMA$C_LINPR_CHIPS 24 /* CHIPS Bisync variant */N#define NMA$M_LINPR_MOP 128 /* MOP support */N/* */N#define NMA$C_CODE_ASCII 1 /* ASCII character code */N#define NMA$C_CODE_EBC=DIC 2 /* EBCDIC character code */N/* */N#define NMA$C_LINPR_MAS 1 /* Master (controls clock signals) */T#define NMA$C_LINPR_NEU 2 /* Neutral (uses master's clock signals) */T#define NMA$C_LINPR_SEC 0 /* Secondary (backup for master failure) */N/* */N#define NMA$C_LINCL_EXT 0 = /* External */N#define NMA$C_LINCL_INT 1 /* Internal */N/* */N#define NMA$C_LINFM_802E 0 /* 802 Extended */N#define NMA$C_LINFM_ETH 1 /* Ethernet */N#define NMA$C_LINFM_802 2 /* 802 */N#define NMA$C_LINFM_SMT 4 /* SMT (FDDI) = */N#define NMA$C_LINFM_ATM 6 /* ATM (native) */N/* */N#define NMA$C_LINCN_LEN 0 /* Local Entity Name */N#define NMA$C_LINCN_NAM 1 /* Ascii Name */N/* */N#define NMA$C_LINSR_USR 1 /* User supplied */N#define =NMA$C_LINSR_CLI 2 /* Class I */N/* */N#define NMA$C_LINSWI_DIS 1 /* Switch disabled */N#define NMA$C_LINSWI_ENA 0 /* Switch enabled */N/* */N#define NMA$C_LINRPE_ON 1 /* Ring purge on */N#define NMA$C_LINRPE_OFF 0 = /* Ring purge off */N/* */N#define NMA$C_LINATY_HIORD 0 /* DECnet address */N#define NMA$C_LINATY_HW 1 /* Hardware address */N#define NMA$C_LINATY_USER 2 /* User supplied address */N/* */N#define NMA$C_LINRNG_FOUR 0 /* 4 Mbps = */N#define NMA$C_LINRNG_SIXTN 1 /* 16 Mbps */N/* */N#define NMA$C_LINETR_ENA 0 /* Enabled */N#define NMA$C_LINETR_DIS 1 /* Disabled */N/* */N#define NMA$C_LINSRC_ENA 0 /* Enabled */N#defin=e NMA$C_LINSRC_DIS 1 /* Disabled */N/* */N#define NMA$C_MEDIA_STP 0 /* STP */N#define NMA$C_MEDIA_UTP 1 /* UTP */N#define NMA$C_MEDIA_AUI 2 /* AUI */N#define NMA$C_MEDIA_TP 3 /* TP */N#define NMA$C_MEDIA_AUTO 4 = /* Auto-sense */N#define NMA$C_MEDIA_UNSPECIFIED 5 /* Unspecified */N#define NMA$C_MEDIA_BNC 6 /* BNC */N#define NMA$C_MEDIA_MULTI 7 /* Fiber - multimode */N#define NMA$C_MEDIA_SINGLE 8 /* Fiber - singlemode */N#define NMA$C_MEDIA_ANY 65535 /* Any */I/* = */N#define NMA$C_LINHNG_DIS 1 /* Hangup disabled */N#define NMA$C_LINHNG_ENA 0 /* Hangup enabled */I/* */N#define NMA$C_LINRES_DIS 1 /* Restart disabled */N#define NMA$C_LINRES_ENA 0 /* Restart enabled */N/* */N#define NMA$=C_LINTY_POI 0 /* DDCMP Point */N#define NMA$C_LINTY_CON 1 /* DDCMP Controller */N#define NMA$C_LINTY_TRI 2 /* DDCMP Tributary */Q#define NMA$C_LINTY_DMC 3 /* DDCMP DMC compatibility mode (DMP) */N/* */N#define NMA$C_LINMC_SET 1 /* Set address(es) */N#define NMA$C_LINMC_CLR 2 = /* Clear address(es) */W#define NMA$C_LINMC_CAL 3 /* Clear entire list of multicast addresses */U#define NMA$C_LINMC_SDF 4 /* Set physical address to DECnet default */N/* */N#define NMA$C_LINDAT_UNK 0 /* Unknown */N#define NMA$C_LINDAT_SUC 1 /* Success */N#define NMA$C_LINDAT_DUP 2 /*= Duplicate */N/* */N#define NMA$C_LINUN_DAT_UNK 0 /* Unknown */N#define NMA$C_LINUN_DAT_SUC 1 /* Success */N#define NMA$C_LINUN_DAT_DUP 2 /* Duplicate */N/* */N#define NMA$C_LINRPS_OFF 0 /* Off = */N#define NMA$C_LINRPS_CAN 1 /* Candidate */N#define NMA$C_LINRPS_NON 2 /* Non-purger */N#define NMA$C_LINRPS_PUR 3 /* Purger */N/* */N#define NMA$C_LINRER_NOE 0 /* No error */N#define NMA$C_LINRER_RII 5 /* Ring init initiated */N#define NMA$C_=LINRER_RIR 6 /* Ring init received */N#define NMA$C_LINRER_RBI 7 /* Ring beaconing initiated */N#define NMA$C_LINRER_DAD 8 /* Duplicate address detected */N#define NMA$C_LINRER_DTD 9 /* Duplicate token detected */N#define NMA$C_LINRER_RPE 10 /* Ring purge error */N#define NMA$C_LINRER_FSE 11 /* FCI strip error */N#define NMA$C_LINRER_ROC 12 =/* Ring OP oscillation */N#define NMA$C_LINRER_DBR 13 /* Directed beacon received */N#define NMA$C_LINRER_PCTI 14 /* PC trace initiated */N#define NMA$C_LINRER_PCTR 15 /* PC trace received */N/* */N#define NMA$C_LINNBR_PHY_A 0 /* A */N#define NMA$C_LINNBR_PHY_B 1 /* B = */N#define NMA$C_LINNBR_PHY_S 2 /* S */N#define NMA$C_LINNBR_PHY_M 3 /* M */N#define NMA$C_LINNBR_PHY_U 4 /* Unknown */N/* */N#define NMA$C_LINRJR_NON 0 /* None */N#define NMA$C_LINRJR_LLCT 1 /* Local LCT */N#define NMA$=C_LINRJR_RLCT 2 /* Remote LCT */N#define NMA$C_LINRJR_LCTB 3 /* LCT both sides */N#define NMA$C_LINRJR_LEM 4 /* LEM reject */N#define NMA$C_LINRJR_TOP 5 /* Topology error */N#define NMA$C_LINRJR_NRJ 6 /* Noise reject */N#define NMA$C_LINRJR_RRJ 7 /* Remote reject */N#define NMA$C_LINRJR_TIP 8 = /* Trace in progress */N#define NMA$C_LINRJR_TRD 9 /* Trace received-disabled */N#define NMA$C_LINRJR_STA 10 /* Standby */N#define NMA$C_LINRJR_LCTE 11 /* LCT protocol error */N/* */S#define NMA$C_ACC_SHR 1 /* Shared access (default protocol user) */S#define NMA$C_ACC_LIM 2 /* Limited access =(point-to-point conn.) */P#define NMA$C_ACC_EXC 3 /* Exclusive access (allow no others) */Y#define NMA$C_ACC_SEL 4 /* Selective access (source address filtering) */N/* */N#define NMA$C_LINMO_AUT 1 /* Auto address mode */N#define NMA$C_LINMO_SIL 2 /* Silo address mode */N/* = */N#define NMA$C_X25MD_DTE 1 /* line operates as DTE */N#define NMA$C_X25MD_DCE 2 /* line operates as DCE */N#define NMA$C_X25MD_DTL 3 /* line is a DTE in loopback */N#define NMA$C_X25MD_DCL 4 /* line is a DCE in loopback */O#define NMA$C_X25MD_NEG 5 /* line negotiates mode of operation */N/* */N#define =NMA$C_X25RED_BUSY 0 /* redirected beacuse DTE was Busy */U#define NMA$C_X25RED_OUT_OF_ORDER 1 /* redirected beacuse DTE was out of order */N#define NMA$C_X25RED_SYSTEMATIC 2 /* redirected systematically */N/* */N#define NMA$C_NODTY_ROU 0 /* Routing Phase III */N#define NMA$C_NODTY_NON 1 /* Nonrouting Phase III */N#define NMA$C_NODTY_PHA 2 = /* Phase II */N#define NMA$C_NODTY_AREA 3 /* Area */N#define NMA$C_NODTY_RT4 4 /* Routing Phase IV */N#define NMA$C_NODTY_NR4 5 /* Nonrouting Phase IV */N#define NMA$C_NODTY_AREAP 6 /* Area Phase IV' */N#define NMA$C_NODTY_RT4P 7 /* Routing Phase IV' */N#define NMA$C_NODTY_NR4P 8 /* Nonroutin=g Phase IV' */N/* */N#define NMA$C_NODINB_ROUT 1 /* Router */N#define NMA$C_NODINB_ENDN 2 /* Endnode */N/* */N#define NMA$C_NODPW_SET 0 /* Password set */N/* */=N#define NMA$C_CPU_8 0 /* PDP-8 processor */N#define NMA$C_CPU_11 1 /* PDP-11 processor */N#define NMA$C_CPU_1020 2 /* Decsystem 10/20 processor */N#define NMA$C_CPU_VAX 3 /* Vax processor */N/* */N#define NMA$C_NODSNV_PH3 0 /* Phase III */N#define NMA$C_NODSNV_PH4= 1 /* Phase IV */N/* */N#define NMA$C_SOFT_SECL 0 /* Secondary loader */N#define NMA$C_SOFT_TERL 1 /* Tertiary loader */N#define NMA$C_SOFT_OSYS 2 /* Operating system */N#define NMA$C_SOFT_DIAG 3 /* Diagnostics */N/* = */N#define NMA$C_ACES_NONE 0 /* None */N#define NMA$C_ACES_INCO 1 /* Incoming */N#define NMA$C_ACES_OUTG 2 /* Outgoing */N#define NMA$C_ACES_BOTH 3 /* Both */N#define NMA$C_ACES_REQU 4 /* Required */N/* =*/N#define NMA$C_ALIINC_ENA 0 /* Enabled */N#define NMA$C_ALIINC_DIS 1 /* Disabled */N/* */N#define NMA$C_ALOUT_ENA 0 /* Enabled */N#define NMA$C_ALOUT_DIS 1 /* Disabled */N/* */N#define NMA$C_ALINC_EN=A 0 /* Enabled */N#define NMA$C_ALINC_DIS 1 /* Disabled */N/* */N#define NMA$C_PRXY_ENA 0 /* Enabled */N#define NMA$C_PRXY_DIS 1 /* Disabled */N/* */N#define NMA$C_PSPCY_NOR 0 /* Norma=l */N#define NMA$C_PSPCY_INT 1 /* Interim */N/* */N#define NMA$C_XPRTY_BIL 1 /* Bilateral */N/* */N#define NMA$C_XPRST_ON 0 /* On */N#define NMA$C_XPRST_OFF 1 /* Off = */N#define NMA$C_XPRST_SHU 2 /* Shut */N/* */N#define NMA$C_XPRMN_ENA 0 /* Enabled */N#define NMA$C_XPRMN_DIS 1 /* Disabled */N/* */N#define NMA$C_XPRSB_RUN 12 /* Running */N#define NMA$C_XPRSB_=UNS 13 /* Unsynchronized */N#define NMA$C_XPRSB_SYN 10 /* Synchronizing */N/* */N#define NMA$C_CLEAR_STRING 0 /*Clear string value */N#define NMA$C_CLEAR_LONGWORD -1 /*Clear longword value */N#define NMA$C_CAL_CLR 0 /*Call clear */N#define NMA$C_CAL_NOW 1 /*Call = now */#define NMA$C_DAY_ALL 0#define NMA$C_DAY_MON 1#define NMA$C_DAY_TUE 2#define NMA$C_DAY_WED 3#define NMA$C_DAY_THU 4#define NMA$C_DAY_FRI 5#define NMA$C_DAY_SAT 6#define NMA$C_DAY_SUN 7N#define NMA$C_TIC_NO_CUT 0 /*Inhibit timecutting */N#define NMA$C_TIC_CUT 1 /*Perform Timecutting */N#define NMA$C_CSG_NO_SIGNAL 0 /*Inhibit call-signal data */N#define NMA$C_CSG_SIGNAL= 1 /*Send call-signal data */N#define NMA$C_IRC_DIS 0 /*Incoming Reverse Disable */N#define NMA$C_IRC_ENA 1 /*Incoming Reverse Enable */N#define NMA$C_ORC_DIS 0 /*Outgoing Reverse Enable */N#define NMA$C_ORC_ENA 1 /*Outgoing Reverse Disable */N#define NMA$C_RED_DIS 0 /*Redirect Enable */N#define NMA$C_RED_ENA 1 /*Redirect= Disable */N#define NMA$C_MOD_NOAUTO 0 /*Mode AUTO time-cutting */N#define NMA$C_MOD_AUTO 1 /*Mode non-auto time-cutting */N#define NMA$C_SWC_DIS 0 /*Enable switched mode */N#define NMA$C_SWC_ENA 1 /*Set line for Leased operation */N#define NMA$C_MDM_OFF 0 /*Enable modem signals */N#define NMA$C_MDM_ON 1 /*Disable modem signals =*/N#define NMA$C_DTS_NO_CABLE 1 /*DTE does not have X21 cable */N#define NMA$C_DTS_NO_X21_CABLE 2 /*DTE has none-X21 cable. */N#define NMA$C_DTS_READY 3 /*DCE is not ready */T#define NMA$C_DTS_NOT_READY 4 /*DTE is signalling Not-Ready to network. */N#define NMA$C_DTS_ACTIVE 5 /*DTE in normal working mode. */]#define NMA$C_DTS_NO_OUTGOING 6 /*Outgoing calls prohibitedin normal working mode. */N=#define NMA$C_CAS_NONE 1 /*Call-Status - No call active */N#define NMA$C_CAS_OUT 2 /*Outgoing call active */N#define NMA$C_CAS_IN 3 /*Incoming call active */N#define NMA$C_CAS_OUT_R 4 /*Outgoing reverse active */N#define NMA$C_CAS_IN_R 5 /*Incoming reverse active */N#define NMA$C_DTL_ACCEPT 1 /*Accept call from */N#define NMA$C_DTL_REJECT 2 = /*Reject call from */N#define NMA$C_CAC_MAN 1 /*X21 controls connect/accept */N#define NMA$C_CAC_AUTO_CONNECT 2 /*Driver connects automatically */N#define NMA$C_CAC_AUTO_ACCEPT 3 /*Enhanced subaddressing */N/* */#define NMA$C_JAN 1#define NMA$C_FEB 2#define NMA$C_MAR 3#define NMA$C_APR 4#define NMA$C_MAY 5#define NMA$C_JUN 6 =#define NMA$C_JUL 7#define NMA$C_AUG 8#define NMA$C_SEP 9#define NMA$C_OCT 10#define NMA$C_NOV 11#define NMA$C_DEC 12N/* */N#define NMA$C_SOFD_DP 0 /* DP11-DA (OBSOLETE) */U#define NMA$C_SOFD_UNA 1 /* DEUNA UNIBUS CSMA/CD communication link */P#define NMA$C_SOFD_DU 2 /* DU11-DA synchronous line interface */N#define NMA$C_SOFD_CNA 3 /* D=ECNA CSMA/CD communication link */[#define NMA$C_SOFD_DL 4 /* DL11-C, -E, or -WA synchronous line interface */N#define NMA$C_SOFD_QNA 5 /* DEQNA CSMA/CD communication link */N#define NMA$C_SOFD_DQ 6 /* DQ11-DA (OBSOLETE) */N#define NMA$C_SOFD_CI 7 /* Computer Interconnect Interface */N#define NMA$C_SOFD_DA 8 /* DA11-B or -AL UNIBUS link */N#define NMA$C_SOFD_PCL 9 /* PCL11-B multi=ple CPU link */Q#define NMA$C_SOFD_DUP 10 /* DUP11-DA synchronous line interface */N#define NMA$C_SOFD_LUA 11 /* DELUA CSMA/CD communication link */g#define NMA$C_SOFD_DMC 12 /* DMC11-DA/AR, -FA/AR, -MA/AL or -MD/AL interprocessor link */Z#define NMA$C_SOFD_LNA 13 /* MicroServer Lance CSMA/CD communication link */S#define NMA$C_SOFD_DN 14 /* DN11-BA or -AA automatic calling unit */^#define NMA$C_SOFD_DLV 16 = /* DLV11-E, -F, -J, MXV11-A or -B asynchronous line */\#define NMA$C_SOFD_LCS 17 /* Lance/Decserver 100 CSMA/CD communication link */R#define NMA$C_SOFD_DMP 18 /* DMP11 multipoint interprocessor link */N#define NMA$C_SOFD_AMB 19 /* AMBER (OBSOLETE) */N#define NMA$C_SOFD_DTE 20 /* DTE20 PDP-11 to KL10 interface */N#define NMA$C_SOFD_DBT 21 /* DEBET CSMA/CD communication link */U#define NMA$C_SOFD_DV 22 = /* DV11-AA/BA synchronous line multiplexer */Q#define NMA$C_SOFD_BNA 23 /* DEBNA BI CSMA/CD communication link */N#define NMA$C_SOFD_BNT 23 /* DEBNT **obsolete** */^#define NMA$C_SOFD_DZ 24 /* DZ11-A, -B, -C, -D asynchronous line multiplexer */S#define NMA$C_SOFD_LPC 25 /* LANCE/PCXX CSMA/CD communication link */N#define NMA$C_SOFD_DSV 26 /* DSV11 Q-bus synchronous link */U#define NMA$C_SOFD=_CEC 27 /* 3-COM/IBM-PC CSMA/CD communication link */Y#define NMA$C_SOFD_KDP 28 /* KMC11/DUP11-DA synchronous line multiplexer */X#define NMA$C_SOFD_IEC 29 /* Interlan/IBM-PC CSMA/CD communication link */g#define NMA$C_SOFD_KDZ 30 /* KMC11/DZ11-A, -B, -C, or -D asynchronous line multiplexer */^#define NMA$C_SOFD_UEC 31 /* Univation/RAINBOW-100 CSMA/CD communication link */N#define NMA$C_SOFD_KL8 32 /* KL8-J (OB=SOLETE) */\#define NMA$C_SOFD_DS2 33 /* LANCE/DECserver 200 CSMA/CD communication link */N#define NMA$C_SOFD_DMV 34 /* DMV11 interprocessor link */V#define NMA$C_SOFD_DS5 35 /* DECserver 500 CSMA/CD communication link */N#define NMA$C_SOFD_DPV 36 /* DPV11 synchronous line interface */N#define NMA$C_SOFD_LQA 37 /* DELQA CSMA/CD communication link */N#define NMA$C_SOFD_DMF 38 /* DMF32 synchro=nous line unit */N#define NMA$C_SOFD_SVA 39 /* DESVA CSMA/CD communication link */\#define NMA$C_SOFD_DMR 40 /* DMR11-AA, -AB, -AC, or -AE interprocessor link */V#define NMA$C_SOFD_MUX 41 /* MUXserver 100 CSMA/CD communication link */m#define NMA$C_SOFD_KMY 42 /* KMS11-PX synchronous line interface with X.25 Level 2 microcode */Z#define NMA$C_SOFD_DEP 43 /* DEPCA PCSG/IBM-PC CSMA/CD communication link */p#define NMA$C_SO=FD_KMX 44 /* KMS11-BD/BE synchronous line interface with X.25 Level 2 microcode */N#define NMA$C_SOFD_LTM 45 /* LTM (911) Ethernet monitor */T#define NMA$C_SOFD_DMB 46 /* DMB-32 BI synchronous line multiplexer */N#define NMA$C_SOFD_DES 47 /* DESNC Ethernet Encryption Module */O#define NMA$C_SOFD_KCP 48 /* KCP synchronous/asynchronous line */W#define NMA$C_SOFD_MX3 49 /* MUXServer 300 CSMA/CD communication l=ink */T#define NMA$C_SOFD_SYN 50 /* MicroServer synchronous line interface */`#define NMA$C_SOFD_MEB 51 /* DEMEB multiport bridge CSMA/CD communication link */Q#define NMA$C_SOFD_DSB 52 /* DSB32 BI synchronous line interface */N#define NMA$C_SOFD_BAM 53 /* DEBAM LANBridge-200 Data Link */a#define NMA$C_SOFD_DST 54 /* DST-32 TEAMmate synchronous line interface (DEC423) */^#define NMA$C_SOFD_FAT 55 /* DEFAT= DataKit Server CSMA/CD communication link */N#define NMA$C_SOFD_RSM 56 /* DERSM - Remote Segment Monitor */R#define NMA$C_SOFD_RES 57 /* DERES - Remote Environmental Sensor */T#define NMA$C_SOFD_3C2 58 /* 3COM Etherlink II (part number 3C503) */T#define NMA$C_SOFD_3CM 59 /* 3COM Etherlink/MC (part number 3C523) */W#define NMA$C_SOFD_DS3 60 /* DECServer 300 CSMA/CD communication link */S#define NMA$C_SOFD_MF2 61 = /* Mayfair-2 CSMA/CD communication link */[#define NMA$C_SOFD_MMR 62 /* DEMMR Ethernet Multiport Manageable Repeater */U#define NMA$C_SOFD_VIT 63 /* Vitalink TransLAN III/IV (NP3A) Bridge */S#define NMA$C_SOFD_VT5 64 /* Vitalink TransLAN 350 (NPC25) Bridge */R#define NMA$C_SOFD_BNI 65 /* DEBNI BI CSMA/CD communication link */S#define NMA$C_SOFD_MNA 66 /* DEMNA XMI CSMA/CD communication link */U#define NMA$C_=SOFD_PMX 67 /* PMAX (KN01) CSMA/CD communication link */c#define NMA$C_SOFD_NI5 68 /* Interlan NI5210-8 CSMA/CD comm link for IBM PC XT/AT */]#define NMA$C_SOFD_NI9 69 /* Interlan NI9210 CSMA/CD comm link for IBM PS/2 */N#define NMA$C_SOFD_KMK 70 /* KMS11-K DataKit UNIBUS adapter */Q#define NMA$C_SOFD_3CP 71 /* Etherlink Plus (part number 3C505) */W#define NMA$C_SOFD_DP2 72 /* DPNserver-200 CSMA/CD commu=nication link */N#define NMA$C_SOFD_ISA 73 /* SGEC CSMA/CD communication link */N#define NMA$C_SOFD_DIV 74 /* DIV-32 DEC WAN controller-100 */N#define NMA$C_SOFD_QTA 75 /* DEQTA CSMA/CD communication link */V#define NMA$C_SOFD_B15 76 /* LANbridge-150 CSMA/CD communication link */V#define NMA$C_SOFD_WD8 77 /* WD8003 Family CSMA/CD communication link */a#define NMA$C_SOFD_ILA 78 /* BICC ISOLAN 4110-2 PC/AT CS=MA/CD communication link */b#define NMA$C_SOFD_ILM 79 /* BICC ISOLAN 4110-3 PC MicroChannel CSMA/CD comm link */R#define NMA$C_SOFD_APR 80 /* Apricot Xen-S and Qi CSMA/CD adapter */V#define NMA$C_SOFD_ASN 81 /* AST EtherNode CSMA/CD communication link */U#define NMA$C_SOFD_ASE 82 /* AST Ethernet CSMA/CD communication link */T#define NMA$C_SOFD_TRW 83 /* TRW HC-2001 CSMA/CD communication link */W#define NMA$C_SOFD_EDX 84 = /* Ethernet-XT/AT CSMA/CD communication link */T#define NMA$C_SOFD_EDA 85 /* Ethernet-AT CSMA/CD communication link */V#define NMA$C_SOFD_DR2 86 /* DECrouter-250 CSMA/CD communication link */b#define NMA$C_SOFD_SCC 87 /* DECrouter-250 DUSCC serial comm link (DDCMP or HDLC) */e#define NMA$C_SOFD_DCA 88 /* DCA Series 300 Net Processor CSMA/CD communication link */N#define NMA$C_SOFD_TIA 89 /* LANcard/E CSMA/CD control=lers */\#define NMA$C_SOFD_FBN 90 /* DEFEB DECbridge-500 CSMA/CD communication link */Y#define NMA$C_SOFD_FEB 91 /* DEFEB DECbridge-500 FDDI communication link */j#define NMA$C_SOFD_FCN 92 /* DEFCN DECconcentrator-500 wiring concentrator FDDI comm link */N#define NMA$C_SOFD_MFA 93 /* DEMFA FDDI communication link */a#define NMA$C_SOFD_MXE 94 /* MIPS workstation family CSMA/CD communication links */l#define NMA$C_SOFD_C=ED 95 /* Cabletron Ethernet Desktop Network Interface CSMA/CD comm link */[#define NMA$C_SOFD_C20 96 /* 3Com CS/200 terminal server CSMA/CD comm link */Y#define NMA$C_SOFD_CS1 97 /* 3Com CS/1 terminal server CSMA/CD comm link */m#define NMA$C_SOFD_C2M 98 /* 3Com CS/210, CS/2000, CS/2100 terminal server CSMA/CD comm link */P#define NMA$C_SOFD_ACA 99 /* ACA/32000 system CSMA/CD comm link */R#define NMA$C_SOFD_GSM 100 = /* Gandalf StarMaster CSMA/CD comm link */T#define NMA$C_SOFD_DSF 101 /* DSF32 2 line sync comm link for Cirrus */Z#define NMA$C_SOFD_CS5 102 /* 3Com CS/50 terminal server CSMA/CD comm link */N#define NMA$C_SOFD_XIR 103 /* XIRCOM PE10B2 CSMA/CD comm link */P#define NMA$C_SOFD_KFE 104 /* KFE52 CSMA/CD comm link for Cirrus */T#define NMA$C_SOFD_RT3 105 /* rtVAX-300 SGEC-based CSMA/CD comm link */_#define NMA$C_SOFD_SPI 106 = /* Spiderport M250 terminal server CSMA/CD comm link */N#define NMA$C_SOFD_FOR 107 /* LAT gateway CSMA/CD comm link */P#define NMA$C_SOFD_MER 108 /* Meridian CSMA/CD comm link drivers */O#define NMA$C_SOFD_PER 109 /* Persoft CSMA/CD comm link drivers */T#define NMA$C_SOFD_STR 110 /* AT&T StarLan-10 twisted pair comm link */N#define NMA$C_SOFD_MPS 111 /* MIPSfair SGEC CSMA/CD comm link */R#define NMA$C_SOFD_L20 112 = /* LPS20 print server CSMA/CD comm link */N#define NMA$C_SOFD_VT2 113 /* Vitalink TransLAN 320 Bridge */N#define NMA$C_SOFD_DWT 114 /* VT-1000 DECwindows terminal */W#define NMA$C_SOFD_WGB 115 /* DEWGB Work Group Bridge CSMA/CD comm link */f#define NMA$C_SOFD_ZEN 116 /* Zenith Z-LAN4000 XT, AT and MicroChannel Z-LAN comm link */`#define NMA$C_SOFD_TSS 117 /* Thursby Software Systems CSMA/CD comm link drivers */W=#define NMA$C_SOFD_MNE 118 /* 3MIN (KN02-BA) integral CSMA/CD comm link */O#define NMA$C_SOFD_FZA 119 /* DEFZA TurboChannel FDDI comm link */U#define NMA$C_SOFD_90L 120 /* DS90L terminal server CSMA/CD comm link */^#define NMA$C_SOFD_CIS 121 /* Cisco Systems terminal servers CSMA/CD comm link */N#define NMA$C_SOFD_STC 122 /* STRTC terminal servers */]#define NMA$C_SOFD_UBE 123 /* Ungermann-Bass PC2030, PC30=30 CSMA/CD comm link */V#define NMA$C_SOFD_DW2 124 /* DECwindows terminal II CSMA/CD comm link */Y#define NMA$C_SOFD_FUE 125 /* Fujitsu Etherstar MB86950 CSMA/CD comm link */N#define NMA$C_SOFD_M38 126 /* MUXServer 380 CSMA/CD comm link */Z#define NMA$C_SOFD_NTI 127 /* NTI Group PC Ethernet Card CSMA/CD comm link */S#define NMA$C_SOFD_RAD 130 /* RADLINX LAN Gateway CSMA/CD comm link */f#define NMA$C_SOFD_INF 131 /*= Infotron Commix series terminal server CSMA/CD comm link */g#define NMA$C_SOFD_XMX 132 /* Xyplex MAXserver series terminal server CSMA/CD comm link */h#define NMA$C_SOFD_NDI 133 /* NDIS data link driver for MS/DOS systems CSMA/CD comm link */f#define NMA$C_SOFD_ND2 134 /* NDIS data link driver for OS/2 systems CSMA/CD comm link */Y#define NMA$C_SOFD_TRN 135 /* DEC LANcontroller 520 Token Ring comm link */e#define NMA$C_SOFD_DEV 136 = /* Develcon Electronics Ltd. LAT gateway CSMA/CD comm link */W#define NMA$C_SOFD_ACE 137 /* Acer 5220, 5270 adapter CSMA/CD comm link */O#define NMA$C_SOFD_PNT 138 /* ProNet-4/18 #1390 802.5 comm link */^#define NMA$C_SOFD_ISE 139 /* Network Integration Server 600 CSMA/CD line card */^#define NMA$C_SOFD_IST 140 /* Network Integration Server 600 T1 sync line card */]#define NMA$C_SOFD_ISH 141 /* Network Integration Server 64 k=b HDLC line card */[#define NMA$C_SOFD_ISF 142 /* Network Integration Server 600 FDDI line card */Q#define NMA$C_SOFD_DSW 149 /* DSW-21 single line serial comm link */Y#define NMA$C_SOFD_DW4 150 /* DSW-41/42 single/dual line serial comm link */N#define NMA$C_SOFD_ITC 154 /* DEC 4000 TGEC CSMA/CD adapter */N#define NMA$C_SOFD_FTA 160 /* DEFTA FDDI adapter */N#define NMA$C_SOFD_FAA 161 /* Futurebus F=DDI */N#define NMA$C_SOFD_FEA 162 /* EISAbus FDDI */N#define NMA$C_SOFD_FQA 169 /* DEFQA Q-bus FDDI adapter */N#define NMA$C_SOFD_A35 170 /* DEC 3000-400/500 CSMA/CD adapter */P#define NMA$C_SOFD_V49 172 /* VAXstation 4000-90 CSMA/CD adapter */^#define NMA$C_SOFD_TRA 175 /* DETRA-AA Turbochannel 802.5 token ring comm link */V#define NMA$C_SOFD_TRB 176 /* DETRA-BA Turbochann=el token ring adapter */Q#define NMA$C_SOFD_ERA 182 /* DE422 EISA-bus PC CSMA/CD comm link */N#define NMA$C_SOFD_A33 188 /* DEC 3000-300 CSMA/CD adapter */N#define NMA$C_SOFD_TRE 189 /* DW300 EISA Token Ring */N#define NMA$C_SOFD_ETA 202 /* TULIP EISA bus CSMA/CD adapter */N#define NMA$C_SOFD_EWA 203 /* TULIP PCI bus CSMA/CD adapter */Z#define NMA$C_SOFD_FWA 204 /* FOCUS PCI bus FDDI adapter (no su=ch product) */N#define NMA$C_SOFD_EIA 204 /* 8255X PCI bus Ethernet adapter */N#define NMA$C_SOFD_AZA 213 /* OTTO Turbochannel ATM adapter */N#define NMA$C_SOFD_FPA 216 /* DEFPA PCI bus FDDI adapter */T#define NMA$C_SOFD_GPA 217 /* DEGPA PCI bus Gigabit Ethernet adapter */N#define NMA$C_SOFD_5719 218 /* x86 LAN 1GB (Broadcom 5719) */N#define NMA$C_SOFD_5720 219 /* x86 LAN 1GB (Broadcom 5720) */N#def=ine NMA$C_SOFD_210 220 /* x86 LAN 1GB (Intel I210) */N#define NMA$C_SOFD_211 221 /* x86 LAN 1GB (Intel I211) */N#define NMA$C_SOFD_350 222 /* x86 LAN 1GB (Intel I350) */N#define NMA$C_SOFD_540 223 /* x86 LAN 10GB (Intel X540) */N#define NMA$C_SOFD_550 224 /* x86 LAN 10GB (Intel X550) */N#define NMA$C_SOFD_710 225 /* x86 LAN 10GB (Intel X710) */N#define NMA$C_SOFD_VIO 226 = /* x86 LAN VIRTIO */N#define NMA$C_SOFD_VBUS 227 /* x86 LAN Hyper-V VMbus */N#define NMA$C_SOFD_EGA 249 /* Fibre Channel LAN driver */N#define NMA$C_SOFD_VLA 250 /* VLAN driver */n#define NMA$C_SOFD_GP3 250 /* Broadcom 5700, 5701, 5703 PCI/PCI-X bus Gigabit Ethernet adapter */R#define NMA$C_SOFD_EIG 251 /* Intel 82540 Gigabit Ethernet adapter */N#define NMA$C_SOFD_L=LA 252 /* Logical LAN */N#define NMA$C_SOFD_TRP 253 /* TC4048 PCI TR adapter */N#define NMA$C_SOFD_ELA 254 /* Emulated LAN over ATM */N#define NMA$C_SOFD_EBA 255 /* Shared Memory LAN */N/* */N#define NMA$_SUCCESS 1 /* Unqualified success */N#define NMA$_SUCCFLDRPL 9 /* Suc=cess with field replaced */N#define NMA$_BADFID 0 /* Invalid field id code */N#define NMA$_BADDAT 8 /* Invalid data format */N#define NMA$_BADOPR 16 /* Invalid operation */N#define NMA$_BUFTOOSMALL 24 /* Buffer too small */N#define NMA$_FLDNOTFND 32 /* Field not found */N/* = */N#define NMA$C_OPN_MIN 0 /* Minimum ! */N#define NMA$C_OPN_NODE 0 /* Nodes */N#define NMA$C_OPN_LINE 1 /* Lines */N#define NMA$C_OPN_LOG 2 /* Logging */N#define NMA$C_OPN_OBJ 3 /* Object */N#define NMA$C_OPN_CIR 4 /* Circuit */N#define NMA$C_OPN_=X25 5 /* Module X25 */N#define NMA$C_OPN_X29 6 /* Module X29 */N#define NMA$C_OPN_CNF 7 /* Module Configurator */Q#define NMA$C_OPN_MAX 7 /* Maximum ! permanent database files */N#define NMA$C_OPN_ALL 127 /* All opened files */N/* */N#define NMA$C_OPN_AC_RO 0 =/* Read Only */N#define NMA$C_OPN_AC_RW 1 /* Read write */N/* */N#define NMA$C_FN2_DLL 2 /* Down line load */N#define NMA$C_FN2_ULD 3 /* Upline Dump */N#define NMA$C_FN2_TRI 4 /* Trigger remote bootstrap */N#define NMA$C_FN2_LOO 5 /* Loop back test = */N#define NMA$C_FN2_TES 6 /* Send test message to be looped */N#define NMA$C_FN2_SET 7 /* Set parameter */N#define NMA$C_FN2_REA 8 /* Read Parameter */N#define NMA$C_FN2_ZER 9 /* Zero counters */N#define NMA$C_FN2_LNS 14 /* Line service */N/* */N#define NMA$=C_OP2_CHNST 5 /* Node operational status */N#define NMA$C_OP2_CHLST 8 /* Line operational status */N/* */N#define NMA$C_OP2_RENCT 0 /* Local node counters */N#define NMA$C_OP2_RENST 1 /* local node status */N#define NMA$C_OP2_RELCT 4 /* Line counters */N#define NMA$C_OP2_RELST 5 = /* Line status */N/* */N#define NMA$C_OP2_ZENCT 0 /* Local Node counters */N#define NMA$C_OP2_ZELCT 2 /* Line counters */N/* */N#define NMA$C_EN2_KNO 0 /* Known lines */N#define NMA$C_EN2_LID 1 /* Line id = */N#define NMA$C_EN2_LCN 2 /* Line convenience name */N/* */N#define NMA$C_STS_SUC 1 /* Success */N#define NMA$C_STS_MOR 2 /* Request accepted, more to come */N#define NMA$C_STS_PAR 3 /* Partial reply */N/* */N#define NM=A$C_STS_DON -128 /* Done */N/* */N#define NMA$C_STS_FUN -1 /* Unrecognized function or option */N#define NMA$C_STS_INV -2 /* Invalid message format */N#define NMA$C_STS_PRI -3 /* Privilege violation */S#define NMA$C_STS_SIZ -4 /* Oversized management command message */O#define NMA$C_STS_MPR -5 = /* Network management program error */N#define NMA$C_STS_PTY -6 /* Unrecognized parameter type */N#define NMA$C_STS_MVE -7 /* Incompatible management version */N#define NMA$C_STS_CMP -8 /* Unrecognised component */N#define NMA$C_STS_IDE -9 /* Invalid identification format */N#define NMA$C_STS_LCO -10 /* Line communication error */N#define NMA$C_STS_STA -11 /* Component i=n wrong state */N#define NMA$C_STS_FOP -13 /* File open error */N#define NMA$C_STS_FCO -14 /* Invalid file contents */N#define NMA$C_STS_RES -15 /* Resource error */N#define NMA$C_STS_PVA -16 /* Invalid parameter value */N#define NMA$C_STS_LPR -17 /* Line protocol error */N#define NMA$C_STS_FIO -18 /* File i/o error */N=#define NMA$C_STS_MLD -19 /* Mirror link disconnected */N#define NMA$C_STS_ROO -20 /* No room for new entry */N#define NMA$C_STS_MCF -21 /* Mirror connect failed */N#define NMA$C_STS_PNA -22 /* Parameter not applicable */N#define NMA$C_STS_PLO -23 /* Parameter value too long */N#define NMA$C_STS_HAR -24 /* Hardware failure */N#define NMA$C_STS_OPE -25 = /* Operation failure */N#define NMA$C_STS_SYS -26 /* System-specific management */N/* function not supported */N#define NMA$C_STS_PGP -27 /* Invalid parameter grouping */N#define NMA$C_STS_BLR -28 /* Bad loopback response */N#define NMA$C_STS_PMS -29 /* Parameter missing */N/* > */N#define NMA$C_STS_ALI -127 /* Invalid alias identification */N#define NMA$C_STS_OBJ -126 /* Invalid object identification */N#define NMA$C_STS_PRO -125 /* Invalid process identification */N#define NMA$C_STS_LNK -124 /* Invalid link identification */N/* */N#define NMA$C_FOPDTL_PDB 0 /* Permanent database */>N#define NMA$C_FOPDTL_LFL 1 /* Load file */N#define NMA$C_FOPDTL_DFL 2 /* Dump file */N#define NMA$C_FOPDTL_SLF 3 /* Secondary loader */N#define NMA$C_FOPDTL_TLF 4 /* Tertiary loader */N#define NMA$C_FOPDTL_SDF 5 /* Secondary dumper */O#define NMA$C_FOPDTL_PDR 6 /* Permanent Database,on remote node */N#define NMA$C_FOPDTL_M>FL 7 /* Management file */N/* */N#define NMA$C_NCEDTL_NNA 0 /* No node name set */N#define NMA$C_NCEDTL_INN 1 /* Invalid node name format */N#define NMA$C_NCEDTL_UNA 2 /* Unrecognised node name */N#define NMA$C_NCEDTL_UNR 3 /* Node unreachable */N#define NMA$C_NCEDTL_RSC 4 /* Netwo>rk resources */N#define NMA$C_NCEDTL_RJC 5 /* Rejected by object */N#define NMA$C_NCEDTL_ONA 6 /* Invalid object name format */N#define NMA$C_NCEDTL_OBJ 7 /* Unrecognised object */N#define NMA$C_NCEDTL_ACC 8 /* Access control rejected */N#define NMA$C_NCEDTL_BSY 9 /* Object too busy */N#define NMA$C_NCEDTL_NRS 10 /* No response from object > */N#define NMA$C_NCEDTL_NSD 11 /* Node shut down */N#define NMA$C_NCEDTL_DIE 12 /* Node or object failed */N#define NMA$C_NCEDTL_DIS 13 /* Disconnect by object */N#define NMA$C_NCEDTL_ABO 14 /* Abort by object */N#define NMA$C_NCEDTL_ABM 15 /* Abort by management */N/* */I#define NMA$C_OPEDTL>_DCH 0 /* Data check */I#define NMA$C_OPEDTL_TIM 1 /* Timeout */I#define NMA$C_OPEDTL_ORN 2 /* Data overrun */I#define NMA$C_OPEDTL_ACT 3 /* Unit is active */I#define NMA$C_OPEDTL_BAF 4 /* Buffer allocation failure */I#define NMA$C_OPEDTL_RUN 5 /* Protocol running */I#define NMA$C_OPEDTL_DSC 6 /* Line disconnected > */I#define NMA$C_OPEDTL_FTL 8 /* Fatal hardware error */Q#define NMA$C_OPEDTL_MNT 11 /* DDCMP maintainance message received */S#define NMA$C_OPEDTL_LST 12 /* Data lost due to buffer size mismatch */I#define NMA$C_OPEDTL_THR 13 /* Threshold error */I#define NMA$C_OPEDTL_TRB 14 /* Tributary malfunction */J#define NMA$C_OPEDTL_STA 15 /* DDCMP start message received */I#define NMA$S_NMADEF7 1 > /* Old size name - synonym */ typedef struct _nma7 { __union {N char nma$$_fill_18; /* byte of flags */ __struct {N unsigned nma$$_fill_19 : 2; /* skip bits 0,1 */N unsigned nma$v_ctlin_tun : 1; /* transmit underrun */N unsigned nma$$_fill_20 : 1; /* skip bit 3 */N unsigned nma$v_ctlin_run : 1; /* receive underrun > */N unsigned nma$v_ctlin_fmr : 1; /* FRMR received */' unsigned nma$v_fill_9_ : 2;! } nma$r_fill_18_bits;N/* */N/* VMS-specific line counters */N/* */N/* 1 Message rejected */N/* 2 Messa >ge truncated */N/* 3 Receiver offline */N/* 4 Receiver busy */N/* 5 Transmitter offline */N/* 1 CRC error on transmit */N/* 2 CRC error on receive */N/* 3 Timeouts  > */N/* 4 Non-existant memory transmit */N/* 5 Non-existant memory receive */N/* 6 Buffer to small */N/* 7 Failed to open channel */N/* 8 Memory overflow */N/* 2 Now master  > */N/* */N/* Node counters */N/* */N/* Server Base Specific Executor Node Counters */N/* */N/* X.25 Protocol module counters */N/*  > */N/* X.25 Server module counters */N/* */N/* Coded parameter values */N/* */N/* */N/* Loop test block type coded values  > */N/* */N/* Default values for loop functions */N/* */N/* Values for LOOP HELP */N/* */N/* State coded values > */N/* */N/* DNS interface */N/* */N/* circuit/line/process specific state values */N/* */N/* logging specific state values */N/* > */N/* node specific state values */N/* */I/* */I/* Default value for EXECUTOR MAXIMUM ADDRESS. */I/* Note: DNA Network Management does not specify a default. */I/* This is defined for VMS only, for compatibi>lity with */I/* previous releases that used a hard coded value in */I/* [NETACP.SRC]NETCONFIG.MAR. */N/* */N/* */N/* */N/* Looper/loader assistance coded values */N/* > */N/* Configurator surveillance coded values */N/* */N/* Circuit/Line substate coded values */N/* */N/* Circuit type coded values [In V2, line type coded values] */N/* > */N/* Circuit/Line Service */N/* */N/* Circuit polling state */N/* */N/* Circuit blocking values */N/* > */N/* Circuit usage values */N/* */N/* Circuit parameter, Handshake Required */N/* */N/* Circuit maximum receive buffers */N/* */N/* Circu>it verification [VMS only] */N/* */N/* Circuit (desired) transport type [VMS only] */N/* */N/* Line duplex coded values */N/* */N/* Line controller mode > */N/* */N/* Line protocol values (same as CIRTY_) */N/* */I/* Character encoding */N/* */N/* Line protocol values for the PCL-11B > */N/* */N/* Line clock values */N/* */N/* Line packet format types. Note that only the Ethernet format is */N/* allowed to be odd. All other format values must be even. */N/* */N/* Line cl>ient name types. */N/* */N/* Line services */N/* */N/* Line Switch states */N/* */N/* Ring purger enable states (FDDI) > */N/* */N/* Address type (Token Ring) */N/* */N/* Ring speed (Token Ring) */N/* */N/* Early token release (Token Ring) > */N/* */N/* Source routing (Token Ring) */N/* */N/* Line Media (LAN) */N/* */N/* Line Hangup state */N/* > */N/* Line Restart state */N/* */N/* Line type coded values [V2 only] */N/* */N/* Line multicast address function code [VMS datalink only]. */N/* Destination and physical addres>s function codes too [VMS datalink only]. */N/* */N/* Duplicate address flag states (FDDI) */N/* */N/* Upstream neighbor DA flag states (FDDI) */N/* */N/* Ring purger states (FDDI) > */N/* */N/* Ring error reason states (FDDI) */N/* */N/* Neighbor PHY type states (FDDI) */N/* */N/* Reject reason states (FDDI) */N/* > */N/* NI line protocol access mode [VMS datalink only] */N/* */N/* PCL-11B address mode */N/* */N/* X.25 line mode */N/* > */N/* X.25 server redirect reason */N/* */N/* Node type values */N/* */N/* Node inbound states */N/* > */N/* Node password values */N/* */N/* Node CPU type codes */N/* */N/* Service node version coded values */N/* */N/* N >ode software type code */N/* */N/* Node access (and default access) codes */N/* */N/* Executor Alias incoming values */N/* */N/* Object alias outgoing !> */N/* */N/* Object alias incoming */N/* */N/* Executor Proxy */N/* */N/* Path Split Policy "> */N/* */N/* X.25 Protocol type values */N/* */N/* X.25 protocol state values */N/* */N/* X.25 protocol multi-network support flag */N/*#> */N/* X.25 protocol DTE substate values */N/* */N/* X21 literals */I/* */N/* Months of the Year Codes */N/* $> */N/* Service device codes (MOP) */N/* */N/* Status codes for field support routines */N/* */N/* Permanent database file ID codes */N/* %> */N/* Open access codes */N/* */N/* Define Phase II NICE function codes */N/* */N/* Change parameters (volatile only) */N/* */N/* &> Read Information (Status and Counters only) */N/* */N/* Zero counters */N/* */N/* Line entity codes */N/* */N/* NML Return codes '> */N/* */N/* Error details */N/* */N/* */N/* STS_FOP and STS_FIO */N/* (> */N/* STS_MLD, STS_MCF */N/* */N/* STS_OPE */N/* */ } nma$r_nma7_fill_union; } NMA7; #if !defined(__VAXC)P#define nma$v_ctlin_tun nma$r_nma7_fill_union.nma$r_fill_18_bits.nma$v_ctlin_tunP#defin)>e nma$v_ctlin_run nma$r_nma7_fill_union.nma$r_fill_18_bits.nma$v_ctlin_runP#define nma$v_ctlin_fmr nma$r_nma7_fill_union.nma$r_fill_18_bits.nma$v_ctlin_fmr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NM *>ADEF_LOADED */ wwG[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. +> **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 20,>24 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */F/* Source: 21-APR-1993 16:22:29 $1$DGA8345:[LIB_H.SRC]NMBDEF.SDL;1 *//***** ->***************************************************************************************************************************//*** MODULE $NMBDEF ***/#ifndef __NMBDEF_LOADED#define __NMBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined .>required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else />#define __union variant_union#endif#endif N/*+ */N/* */O/* FORMAT OF THE FILE NAME BLOCK. THE FILE NAME BLOCK IS USED AS AN INTERNAL */N/* INTERFACE TO THE DIRECTORY SCAN ROUTINE, AND IS ALSO THE FORMAT OF A */N/* DIRECTORY RECORD. */N/* 0> */N/*- */ N#define NMB$K_DIRENTRY 16 /* LENGTH OF DIRECTORY ENTRY */N#define NMB$C_DIRENTRY 16 /* LENGTH OF DIRECTORY ENTRY */#define NMB$M_ALLVER 0x8#define NMB$M_ALLTYP 0x10#define NMB$M_ALLNAM 0x20#define NMB$M_WILD 0x100#define NMB$M_NEWVER 0x200#define NMB$M_SUPERSEDE 0x400#define NMB$M_FINDFID 0x800#define NMB$M_LOWVER 0x4000#defin 1>e NMB$M_HIGHVER 0x8000N#define NMB$K_LENGTH 40 /* LENGTH OF NAME BLOCK */N#define NMB$C_LENGTH 40 /* LENGTH OF NAME BLOCK */#define NMB$S_NMBDEF 40 typedef struct _nmb { __union {N unsigned short int nmb$w_fid [3]; /* FILE ID */ __struct {N unsigned short int nmb$w_fid_num; /* FID - FILE NUMBER */O unsigned short int nmb$w_fid_seq; /* FID - FILE SEQUENCE N 2>UMBER */Q unsigned short int nmb$w_fid_rvn; /* FID - RELATIVE VOLUME NUMBER */ } nmb$r_fid_fields; } nmb$r_fid_overlay;N unsigned short int nmb$w_name [3]; /* FILE NAME (RAD-50) */N unsigned short int nmb$w_type; /* FILE TYPE (RAD-50) */N short int nmb$w_version; /* VERSION NUMBER */ __union {N unsigned short int nmb$w_flags; /* NAME STATUS FLAGS */ __ 3>struct {) unsigned nmbdef$$_fill_1 : 3;N unsigned nmb$v_allver : 1; /* MATCH ALL VERSIONS */N unsigned nmb$v_alltyp : 1; /* MATCH ALL TYPES */N unsigned nmb$v_allnam : 1; /* MATCH ALL NAMES */) unsigned nmbdef$$_fill_2 : 2;N unsigned nmb$v_wild : 1; /* WILD CARDS IN FILE NAME */N unsigned nmb$v_newver : 1; /* MAXIMIZE VERSION NUMBER */N 4> unsigned nmb$v_supersede : 1; /* SUPERSEDE EXISTING FILE */N unsigned nmb$v_findfid : 1; /* SEARCH FOR FILE ID */) unsigned nmbdef$$_fill_3 : 2;N unsigned nmb$v_lowver : 1; /* LOWER VERSION OF FILE EXISTS */N unsigned nmb$v_highver : 1; /* HIGHER VERSION OF FILE EXISTS */ } nmb$r_flags_bits; } nmb$r_flags_overlay; __struct {& unsigned char nmb$b_ascnamsiz;" char nmb$t_ascna 5>mtxt [19]; } nmb$r_ascname;N unsigned short int nmb$w_context; /* START POINT FOR NEXT FIND */ } NMB; #if !defined(__VAXC)-#define nmb$w_fid nmb$r_fid_overlay.nmb$w_fidF#define nmb$w_fid_num nmb$r_fid_overlay.nmb$r_fid_fields.nmb$w_fid_numF#define nmb$w_fid_seq nmb$r_fid_overlay.nmb$r_fid_fields.nmb$w_fid_seqF#define nmb$w_fid_rvn nmb$r_fid_overlay.nmb$r_fid_fields.nmb$w_fid_rvn3#define nmb$w_flags nmb$r_flags_overlay.nmb$w_flagsF#define nmb$v_allver nmb$r_flags6>_overlay.nmb$r_flags_bits.nmb$v_allverF#define nmb$v_alltyp nmb$r_flags_overlay.nmb$r_flags_bits.nmb$v_alltypF#define nmb$v_allnam nmb$r_flags_overlay.nmb$r_flags_bits.nmb$v_allnamB#define nmb$v_wild nmb$r_flags_overlay.nmb$r_flags_bits.nmb$v_wildF#define nmb$v_newver nmb$r_flags_overlay.nmb$r_flags_bits.nmb$v_newverL#define nmb$v_supersede nmb$r_flags_overlay.nmb$r_flags_bits.nmb$v_supersedeH#define nmb$v_findfid nmb$r_flags_overlay.nmb$r_flags_bits.nmb$v_findfidF#define nmb$v_lowver nmb$r_fla 7>gs_overlay.nmb$r_flags_bits.nmb$v_lowverH#define nmb$v_highver nmb$r_flags_overlay.nmb$r_flags_bits.nmb$v_highver5#define nmb$b_ascnamsiz nmb$r_ascname.nmb$b_ascnamsiz5#define nmb$t_ascnamtxt nmb$r_ascname.nmb$t_ascnamtxt"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifd8>ef __cplusplus }#endif#pragma __standard #endif /* __NMBDEF_LOADED */ ww1[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the9> **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior writ:>ten permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */J/* Sourc ;>e: 18-MAY-2022 12:05:25 $1$DGA8345:[LIB_H.SRC]NPOOL_DATA.SDL;1 *//********************************************************************************************************************************//*** MODULE $NPHDEF ***/#ifndef __NPHDEF_LOADED#define __NPHDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */<>\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif =>#ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DEFINITION OF NON-PAGED POOL HISTORY RECORD IN RING BUFFER */N/*- */ N#define NPH$C_ALONONPAGED 0 /* Caller was EXE$ALONONPAGED */N#define NPH$C_ALONPAGVAR 1 /* Caller was EX>>E$ALONPAGVAR */N#define NPH$C_DEANONPAGED 2 /* Caller was EXE$DEANONPAGED */N#define NPH$C_DEANONPGDSIZ 3 /* Caller was EXE$DEANONPGDSIZ */\#define NPH$C_ALLOCATE_POOL_NPP 4 /* Caller was EXE$ALLOCATE_POOL with NPP pooltype */r#define NPH$C_ALLOCATE_POOL_NPP_ALIGNED 5 /* Caller was EXE$ALLOCATE_POOL with NPP pooltype and non-0 alignment */q#define NPH$C_DEALLOCATE_POOL_NPP 6 /* Caller was EXE$DEALLOCATE_POOL with NPP pooltype and size in memory *?>/s#define NPH$C_DEALLOCATE_POOL_NPP_SIZED 7 /* Caller was EXE$DEALLOCATE_POOL with NPP pooltype and size specified */\#define NPH$C_ALLOCATE_POOL_BAP 8 /* Caller was EXE$ALLOCATE_POOL with BAP pooltype */r#define NPH$C_ALLOCATE_POOL_BAP_ALIGNED 9 /* Caller was EXE$ALLOCATE_POOL with BAP pooltype and non-0 alignment */q#define NPH$C_DEALLOCATE_POOL_BAP 10 /* Caller was EXE$DEALLOCATE_POOL with BAP pooltype and size in memory */t#define NPH$C_DEALLOCATE_POOL_BAP_SIZED 11 /* Caller was E@>XE$DEALLOCATE_POOL with BAP pooltype and size specified */N#define NPH$C_POOLZONE_ALLOCATE 12 /* Caller was EXE$POOL_ALLOCATE */N#define NPH$C_POOLZONE_DEALLOCATE 13 /* Caller was EXE$POOL_DEALLOCATE */b#define NPH$C_BAP_NOT_CONTIGUOUS 14 /* Failure of BAP due to non-contiguous physical memory */S#define NPH$C_ALLOCATE_POOL_NPP_VAR 15 /* Allocating NPP from the variable pool */S#define NPH$C_ALLOCATE_POOL_BAP_VAR 16 /* Allocating BAP from the variable pool */Q#define NPH$C_A>ALONONPAGED_ALN 17 /* Allocating with EXE$ALONONPAGED_ALN */N#define NPH$C_EXPAND_NPP 18 /* Pool expansion */N#define NPH$C_EXPAND_BAP 19 /* Pool expansion */T#define NPH$C_MAX_FUNC_TYPE 20 /* Maximum expected function type for SDA */N/* X86 only for S2 nonpaged pool order here matters with SDA */N#define NPH$C_ALONPAGED_S2 100 /* Caller was EXE$ALONONPAGED_S2 */Y#define NPH$C_ALONPAGED_BC_S2 B>101 /* Caller was a bugcheck in EXE$ALONONPAGED_S2 */_#define NPH$C_ALONPAGED_FAIL_S2 102 /* Caller was a failed request in EXE$ALONONPAGED_S2 */N#define NPH$C_ALONPAGED_VAR_S2 103 /* Caller was MMG$ALONPAGED_VAR_S2 */[#define NPH$C_ALONPAGED_VAR_BC_S2 104 /* Caller was a bugcheck in MMG$ALONPAGED_VAR_S2 */a#define NPH$C_ALONPAGED_VAR_FAIL_S2 105 /* Caller was a failed request in MMG$ALONPAGED_VAR_S2 */N#define NPH$C_ALONPAGED_LIST_S2 106 /* Caller was MMG$ALONPAGED_LISTC>_S2 */a#define NPH$C_ALONPAGED_LIST_FAIL_S2 107 /* Caller was failed request in MMG$ALONPAGED_LIST_S2 */N#define NPH$C_DEALONPAGED_S2 108 /* Caller was EXE$DEALONPAGED_S2 */Y#define NPH$C_DEALONPAGED_BC_S2 109 /* Caller was a bugcheck in EXE$DEALONPAGED_S2 */]#define NPH$C_DEALONPAGED_FAIL_S2 110 /* Caller was failed request in EXE$DEALONPAGED_S2 */P#define NPH$C_DEALONPAGED_LIST_S2 111 /* Caller was MMG$DEALONPAGED_LIST_S2 */e#define NPH$C_DEALONPAGED_LIST_FAIL_S2 112 /* CaD>ller was failed request in MMG$DEALONPAGED_LIST_S2 */T#define NPH$C_NPAGED_ALLOC_S2 113 /* Caller was MMG$NPAGED_ALLOCATE_BASE_S2 */b#define NPH$C_NPAGED_ALLOC_BC_S2 114 /* Caller was a bugcheck in MMG$NPAGED_ALLOCATE_BASE_S2 */h#define NPH$C_NPAGED_ALLOC_FAIL_S2 115 /* Caller was a failed request in MMG$NPAGED_ALLOCATE_BASE_S2 */f#define NPH$C_NPAGED_DEALLOC_S2 116 /* Caller was from/based from MMG$NPAGED_DEALLOCATE_BASE_S2 */d#define NPH$C_NPAGED_DEALLOC_BC_S2 117 /* Caller was E>a bugcheck in MMG$NPAGED_DEALLOCATE_BASE_S2 */X/* If the expansion order is changed, also change poolalc_base_s2.c and possibly sda */#define NPH$C_NPAG_EXP_PASS_S2 118 /* Caller was expand_pool_map_s2 ended with success and must be first function name for exp\ and s2. */]#define NPH$C_NPAG_EXP_FORK_S2 119 /* Caller was expand_pool_map_s2 and fork required */}#define NPH$C_NPAG_EXP_INSUF_POOL_S2 120 /* Caller was expand_pool_map_s2 the available pool exp does not meet the min req *F>/e#define NPH$C_NPAG_EXP_FLUCHK_FAIL_S2 121 /* Called was Pool_expand_fork_s2 and fluid check failed */t#define NPH$C_NPAG_EXP_ALLO_PFN_FAIL_S2 122 /* Called was Pool_expand_fork_s2 and mmg$allocate_sva_and_pfn failed */#define NPH$C_NPAG_EXP_FAIL_S2 123 /* Called was expand_pool_map_s2 general expand failure catch all and the last function nam\e for S2 expand */q#define NPH$C_NPAG_FLUSH_PASS_S2 124 /* Called flush_lookaside_list_s2 successfully flushed pool (mon only) */n#define NPG>H$C_NPAG_FLUSH_FAIL_S2 125 /* Called flush_lookaside_list_s2 catch all failure to find a match */m#define NPH$C_NPAG_FLUSH_TMOUT_S2 126 /* Called flush_lookaside_list_s2 timed out before finding a match */|#define NPH$C_NPAG_FLUSH_NOMTCH_S2 127 /* Called flush_lookaside_list_s2 failed as no match found in the list (Mon only) */Q#define NPH$C_MAX_FUNC_TYPE_S2 128 /* X86 Maximum secondary function type */N/* give S0 NPP functions a place to expand to */N#d H>efine NPH$S_NPHDEF 40 /* Old size name - synonym */ typedef struct _nph {N/* These constants have a 31 size limit. SDA will not build if larger */N/* NOTE - IF the increment count changes here, SO must the increment in */N/* [SDA]POOL.MAR and [SDA]SHOWPOOL.C for the ring_names */ __union {N unsigned __int64 nph$q_addr; /* Address of packet */ __struct {N unsigned int nph$l_addr_low; / I>* low longword of pkt addr */N unsigned int nph$l_addr_high; /* high longword of pkt addr */ } nph$r_fill_4_; } nph$r_fill_3_;N unsigned __int64 nph$q_rip; /* Instruction Pointer */N unsigned int nph$l_unused2; /* Maintain alignment */N unsigned short int nph$w_function; /* Function of caller */N unsigned char nph$b_type; /* Pkt. type */N unsignedJ> char nph$b_rmod; /* Pkt. RMOD or subtype */N unsigned int nph$l_size; /* Size of pkt. being manip. */N unsigned char nph$b_ipl; /* IPL of caller */O unsigned char nph$b_cpu; /* CPU number function was called on */N unsigned short int nph$w_unused; /* Round up to quadword */ __union {N unsigned __int64 nph$q_time; /* System time of operation */ __struct { K>N unsigned int nph$l_time_low; /* low longword of time */N unsigned int nph$l_time_high; /* high longword of time */ } nph$r_fill_6_; } nph$r_fill_5_; } NPH; #if !defined(__VAXC)+#define nph$q_addr nph$r_fill_3_.nph$q_addrA#define nph$l_addr_low nph$r_fill_3_.nph$r_fill_4_.nph$l_addr_lowC#define nph$l_addr_high nph$r_fill_3_.nph$r_fill_4_.nph$l_addr_high+#define nph$q_time nph$r_fill_5_.nph$q_timeA#define nph$l_time_l L>ow nph$r_fill_5_.nph$r_fill_6_.nph$l_time_lowC#define nph$l_time_high nph$r_fill_5_.nph$r_fill_6_.nph$l_time_high"#endif /* #if !defined(__VAXC) */ N/* */N/* X86 structure for S2 nonpaged pool history buffer */N/* */#define NPH_S2$S_NPH_SIZE 48 typedef struct _nph_s2 { __union {N unsigned __int64 nph_s2$ M>q_addr; /* Address of packet */ __struct {N unsigned int nph_s2$l_addr_low; /* low longword of pkt addr */N unsigned int nph_s2$l_addr_high; /* high longword of pkt addr */ } nph_s2$r_fill_8_; } nph_s2$r_fill_7_;N unsigned __int64 nph_s2$q_rip; /* Instruction Pointer */N unsigned int nph_s2$l_unused1; /* Maintain alignment */N unsigned short int nph_s2$w_function; /* FunctioN>n of caller */N unsigned char nph_s2$b_type; /* Pkt. type */N unsigned char nph_s2$b_rmod; /* Pkt. RMOD or subtype */N/* size location same as NPH for SDA */N unsigned __int64 nph_s2$q_size; /* Size of pkt. being manip. */N unsigned int nph_s2$l_unused2; /* quad alignment */N unsigned char nph_s2$b_ipl; /* IPL of caller */ O>O unsigned char nph_s2$b_cpu; /* CPU number function was called on */N unsigned short int nph_s2$w_unused3; /* Round up to quadword */ __union {N unsigned __int64 nph_s2$q_time; /* System time of operation */ __struct {N unsigned int nph_s2$l_time_low; /* low longword of time */N unsigned int nph_s2$l_time_high; /* high longword of time */ } nph_s2$r_fill_10_; } nph_s2$r_fill_9_; P> } NPH_S2; #if !defined(__VAXC)4#define nph_s2$q_addr nph_s2$r_fill_7_.nph_s2$q_addrM#define nph_s2$l_addr_low nph_s2$r_fill_7_.nph_s2$r_fill_8_.nph_s2$l_addr_lowO#define nph_s2$l_addr_high nph_s2$r_fill_7_.nph_s2$r_fill_8_.nph_s2$l_addr_high4#define nph_s2$q_time nph_s2$r_fill_9_.nph_s2$q_timeN#define nph_s2$l_time_low nph_s2$r_fill_9_.nph_s2$r_fill_10_.nph_s2$l_time_lowP#define nph_s2$l_time_high nph_s2$r_fill_9_.nph_s2$r_fill_10_.nph_s2$l_time_high"#endif /* #if !defined(__VAXC) Q>*/  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NPHDEF_LOADED */ ww ΋[UM/***************************************************************************/M/** R> **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTS>WARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************T>**************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */J/* Source: 18-MAY-2022 12:05:25 $1$DGA8345:[LIB_H.SRC]NPOOL_DATA.SDL;1 *//********************************************************************************************************************************//*** MODULE NPOOL_DATA ***/#ifndef __NPOOL_DATA_LOADED U>#define __NPOOL_DATA_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define V>__unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DEFINITION OF SYSTEM PRIMITIVES LOCAL NW>ON-PAGED POOL DATA */N/*- */N#define IOC_C_INVALID_ADDRESS -8388608 /* 4G - 8M */Y#define IOC_C_NUMLISTS 160 /* No. of lookaside lists for all system pools */N/* *** See warning above *** */N#define IOC_C_NPAGGRNMSK 63 /* Mask for rounding */N#define IOC_C_NPAGGRNBITS 6 /* Granularity =X> 2^6 */N#define IOC_C_MAXLISTPKT 10240 /* Max. lookaside list size */N#define IOC_C_PAGGRNMSK 15 /* Mask for rounding */N#define IOC_C_PAGGRNBITS 4 /* Granularity = 2^4 */N#define IOC_C_PAGMAXLISIZ 2560 /* Max. lookaside list size */N/* X86 only S2 NONPAGED POOL LOOKASIDE list related constants */U#define IOC_C_NUMLISTS_S2 40 /* No. of lookaside lists S2 nonpaged poolY> */R#define IOC_C_NPAGGRNMSK_S2 255 /* Mask for rounding granularity at 256 */_#define IOC_C_NPAGGRNBITS_S2 8 /* Granularity = 2^8 or 256 and is used for shifting */N#define IOC_C_MAXLISTPKT_S2 10240 /* Max. lookaside list siz */   9#ifdef __cplusplus /* Define structure prototypes */struct _npool_data; #endif /* #ifdef __cplusplus */ typedef struct _lsthds {N unsigned int lsthds$l_filler0; /* Formerly IRPLIST */ZZ> unsigned int lsthds$l_varallocbytes; /* How many bytes allocated from variable list */k unsigned int lsthds$l_variablelist_unused; /* Historically important: What EXE$GL_NONPAGED points to */U void *lsthds$ps_variablelist; /* Pointer to next packet on variable list */Y unsigned int lsthds$l_variablelist_high; /* For future use if we have 64-bit lists */X unsigned int lsthds$l_expansions; /* How many times this pool has been expanded */N unsigned int lsthds$l_filler2;[> /* Formerly SRPLIST */T unsigned int *lsthds$ar_listattempts; /* Ptr to array of lookaside list tries */U unsigned int *lsthds$ar_listfails; /* Ptr to array of lookaside list failures */\ unsigned int *lsthds$ar_listdeallocs; /* Ptr to array of lookaside list deallocations */ unsigned int lsthds$l_rad;# unsigned int lsthds$l_pooltype;e struct _npool_data *lsthds$ps_npool_data; /* Pointer to the NPOOL data structure for this pool *// unsigned int l \>sthds$l_disable_pool_exp_msg;j __int64 lsthds$q_listheads [161]; /*The actual lookaside lists. Must be 56 bytes from beginning. */o unsigned __int64 lsthds$q_filler4; /* Don't change offset to LISTCOUNTERS till major VMS version change */& unsigned __int64 lsthds$q_filler5;1 unsigned __int64 lsthds$q_listcounters [161]; } LSTHDS;#define LSTHDS$K_LENGTH 2648#define LSTHDS$C_LENGTH 2648 #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save ]>current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Ptypedef struct _lsthds * LSTHDS_PQ; /* Long pointer to a LSTHDS structure. */]typedef struct _lsthds ** LSTHDS_PPQ; /* Long pointer to a pointer to a LSTHDS structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else#typedef unsigned __int64 LSTHDS_PQ;$typedef unsigned __int64 LSTHDS_PPQ;##endif /* __INITIAL_POINTER_SIZE */ typedef struct _po ^>ol_map {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */& void *pool_map$pq_segment_address;#else. unsigned __int64 pool_map$pq_segment_address;#endif/ unsigned __int64 pool_map$q_segment_length;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit poi_>nters */* void *pool_map$pq_segment_end_address;#else2 unsigned __int64 pool_map$pq_segment_end_address;#endif unsigned int pool_map$l_rad; int pool_map$l_filler1; } POOL_MAP;#define POOL_MAP$K_LENGTH 32#define NPOOL$M_NOT_NPP 0x1!#define NPOOL$M_POOL_SEPARATE 0x2##define NPOOL$M_POOL_WITHIN_NPP 0x4 #define NPOOL$M_MINIMUM_MODE 0x8 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment `> __quadword#else#pragma __nomember_alignment#endiftypedef struct _npool_data {#pragma __nomember_alignmentT unsigned int npool$l_on_rad_dealloc; /* Count deallocs from same RAD as alloc */N unsigned int npool$l_total_dealloc; /* Count total deallocs to get % */N unsigned __int64 npool$q_per_pool_diag; /* Use for diagnostic info */N/* The following are only used in the NPP NPOOL structure for now. */S/* Some other time, we could have one for each pool and sequ a>ence tag each entry. */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *npool$ps_ringbuf; /* Pointer to the ring buffer */` void *npool$ps_nextnph; /* Pointer to next element to write to in ring buffer */N unsigned int npool$l_ringbufcnt; /* How many entries in ring buffer? */! char npool_da$$b_fill_0_ [4];c b>#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 npool$q_ringbuflock; /* Lock access to the ringbuffer */N/* The filler forces mostly-read stuff beyond a 128-byte */`/* boundary and hopefully into a different cache block from the frequently-written list heads */#pragma __nomember_alignment char filler6 [88];N/* A c>fter this point, we have read-mostly information. */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */V struct _lsthds (*(*npool$ar_lsthds)); /*Pointer to the array of pool list heads */#else" unsigned __int64 npool$ar_lsthds;#endifN unsigned int npool$l_max_lsthds; /* Number of Rads */N unsigned int npool$l_gran_maskd>; /*Granularity of the pool in bytes */P unsigned int npool$l_num_lookaside; /*How many lookaside lists in LSTHDS? */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifa void *npool$ps_variable_list; /* Pointer to the pool's variable list (compatibility) */( struct _pool_map *npool$ps_pool_map;S unsigned int npool$l_pool_map_size; /*Number o e>f bytes allcoated for POOL_MAP */] unsigned int npool$l_pool_map_segments; /*Number of segments in POOL_MAP actually used */ __union {[ __struct { /*This part used for non-paged pool's npool_data */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */; struct _npool_data *npool$ar_pool_data [2];#e f>lse) unsigned __int64 npool$ar_pool_data [2];#endifN/*Dimension should be MMG$K_POOLTYPE_MAXIMUM; */ __struct {N/*This are mainly for SDA format. Most uses should index using POOL_TYPE. */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */1 void *npool$ar_npp_pool_data;#else) unsigned __int64 npoo g>l$ar_npp_pool_data;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */1 void *npool$ar_bap_pool_data;#else) unsigned __int64 npool$ar_bap_pool_data;#endif, } npool$r_sda_pool_data;$ } pool_data_overlay; } non_paged;d __struct { /*This part used for new pool types be h>yond non-paged pool */ __union {0 unsigned int npool$l_pool_flags; __struct {y unsigned npool$v_not_npp : 1; /* Note: If this NPOOL *does* represent non-paged pool, there is an */N/* address here, which will not have bit 0 set. Thus, this flag is */N/* valid in all cases */7 unsigned npool$v_pool_separate : 1;9 unsigned npool$vi>_pool_within_npp : 1;6 unsigned npool$v_minimum_mode : 1;1 unsigned npool$v_fill_1_ : 4;- } npool$r_pool_flag_bits;- } npool$r_pool_flags_overlay;) unsigned int npool$l_filler3;- unsigned __int64 npool$q_filler4; } new_pools; } npool_overlay;! char npool_da$$b_fill_2_ [4]; } NPOOL_DATA; #if !defined(__VAXC)W#define npool$ar_pool_data npool_overlay.non_paged.pj>ool_data_overlay.npool$ar_pool_datau#define npool$ar_npp_pool_data npool_overlay.non_paged.pool_data_overlay.npool$r_sda_pool_data.npool$ar_npp_pool_datau#define npool$ar_bap_pool_data npool_overlay.non_paged.pool_data_overlay.npool$r_sda_pool_data.npool$ar_bap_pool_data`#define npool$l_pool_flags npool_overlay.new_pools.npool$r_pool_flags_overlay.npool$l_pool_flagsq#define npool$v_not_npp npool_overlay.new_pools.npool$r_pool_flags_overlay.npool$r_pool_flag_bits.npool$v_not_npp}#define npool$ k>v_pool_separate npool_overlay.new_pools.npool$r_pool_flags_overlay.npool$r_pool_flag_bits.npool$v_pool_separate#define npool$v_pool_within_npp npool_overlay.new_pools.npool$r_pool_flags_overlay.npool$r_pool_flag_bits.npool$v_pool_within_npp{#define npool$v_minimum_mode npool_overlay.new_pools.npool$r_pool_flags_overlay.npool$r_pool_flag_bits.npool$v_minimum_mode"#endif /* #if !defined(__VAXC) */ #define NPOOL$K_LENGTH 184#define NPOOL$C_LENGTH 184 N/* l> */N/* X86 only - S2 nonpaged support */N/* The LISTHEAD_S2 combines the forward link and the sequence number */N/* This pair is used for synchronization for allocation/deallocation */N/* for the look aside list. See the code that implements */N/* lookaside list for more information. */N/* m> */N/* listhead must be 16 byte aligned as per cmpxchg16b instructions */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endiftypedef struct _listhead_s2 {#pragma __nomember_alignment) unsigned __int64 listhead_s2$q_flink;+ unsigned __int64 listhead_s2$q_seq_num; } LISTHEAD_S2;#define LISTHEAD_S2$K_LENGTH 16#definn>e LISTHEAD_S2$C_LENGTH 16N/* */N/* Listhead data structure for S2 nonpaged pool */N/* Listhead gets its pool allocation when variable pool within */N/* IOC_C_MAXLISTPKT_S2 is deallocated. */N/* The LISTHEADS is a pointer to a list of IOC_C_NUMLISTS_S2 +1 */N/* lists with pool size incrementally starting at 256 */o>N/* Listhead starts index 1 - this aids with calculations. */N/* */  9#ifdef __cplusplus /* Define structure prototypes */struct _npool_data_s2; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endiftypedef struct _lsthds_sp>2 {#pragma __nomember_alignmentN unsigned int lsthds_s2$l_rad; /* rad number */N unsigned int lsthds_s2$l_pooltype; /* pool type from mmgdef */N unsigned int lsthds_s2$l_exp_count; /* Number of times pool is expanded */N unsigned int lsthds_s2$l_filler; /* Alignment filler */b unsigned __int64 lsthds_s2$q_varallocbytes; /* Number of bytes allocated from variable list */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenev q>er ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */W unsigned int *lsthds_s2$ar_listattempts; /* Ptr to array of lookaside list tries */#else, unsigned __int64 lsthds_s2$ar_listattempts;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */W unsigned int *lsthds_s2$ar_listfails; /* Ptr to r>array of lookaside list failures */#else) unsigned __int64 lsthds_s2$ar_listfails;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Z unsigned int *lsthds_s2$ar_listdeallocs; /* Ptr to array of lookaside list deallocs */#else, unsigned __int64 lsthds_s2$ar_listdeallocs;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporte s>d */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */] void *lsthds_s2$pq_varlistnxt; /* Pointer to the next packet on the variable list */#else* unsigned __int64 lsthds_s2$pq_varlistnxt;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */3 struct _npool_data_s2 *lsthds_s2$pq_npool_data;#else* unsigned __in t>t64 lsthds_s2$pq_npool_data;#endifU LISTHEAD_S2 lsthds_s2$r_listheads [41]; /* address/sequence number pair */b unsigned __int64 lsthds_s2$q_listcounters [41]; /* cnt of packets on the corresponding list */N unsigned __int64 lsthds_s2$q_filler2; /* octaword alignment filler */N unsigned __int64 lsthds_s2$q_filler3; /* octaword alignment filler */N unsigned __int64 lsthds_s2$q_filler4; /* filler cushion */ } LSTHDS_S2;#define LSTHDS_S2$K_LEu>NGTH 1072#define LSTHDS_S2$C_LENGTH 1072 #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */##pragma __required_pointer_size 64 *typedef struct _lsthds_s2 * LSTHDS_PQ_S2; 1typedef struct _lsthds_s2 ** LSTHDS_PPQ_S2; Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else&typedef unsigned __int64 LSTHDS_PQ_S2;'typedef unsigned __int64 LSTHDS_PPQ_S2;#endifN/* v> */N/* X86 only S2 nonpaged pool for NPOOL data structure */N/* NPOOL data structures has both history ring buffer and RAD related data */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endiftypedef struct _npool_da w>ta_s2 {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *npool_s2$pq_rb_start; /* Pointer to the ring buffer */#else' unsigned __int64 npool_s2$pq_rb_start;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default x> to 64-bit pointers */W void *npool_s2$pq_nextnph; /* Pointer to next element in the ringbuffer */#else& unsigned __int64 npool_s2$pq_nextnph;#endif# unsigned int npool_s2$l_filler;N unsigned int npool_s2$l_total_dealloc; /* count total deallocs to get % */N unsigned int npool_s2$l_filler1; /* filler for aligment */N unsigned int npool_s2$l_ringbufcnt; /* How many entries in ring buffer */P unsigned __int64 npool_s2$q_ringbuflock; /* Lock accesy>s to the ringbuffer */[ unsigned __int64 npool_s2$q_on_rad_dealloc; /* Count deallocs from same RAD as alloc */N unsigned __int64 npool_s2$q_per_pool_diag; /* Use for diagnostic info */N/* after this point, we have mostly read only data */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *npool_s2$pq_variable_list; /* variable z>list */#else, unsigned __int64 npool_s2$pq_variable_list;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Q struct _pool_map *npool_s2$pq_pool_map; /* pointer to pool's variable list */#else' unsigned __int64 npool_s2$pq_pool_map;#endifN unsigned __int64 npool_s2$q_filler2; /* filler for aligment */N/* Change fixed ar {>ray once rads are implemented */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */R struct _lsthds_s2 (*(*npool_s2$ar_lsthds)); /* Rad usage and needed for sda */#else% unsigned __int64 npool_s2$ar_lsthds;#endifN unsigned __int64 npool_s2$q_max_lsthds; /* Number of Rads. */_ unsigned int npool_s2$l_num_lookaside; /* Nu|>mber in lookaside list == IOC_C_NUMLISTS_S2 */U unsigned int npool_s2$l_gran_mask; /* granularity mask == IOC_C_NPAGGRNMSK_S2 */_ unsigned int npool_s2$l_pool_map_size; /* number of bytes allocated for POOL_MAP for SDA */i unsigned int npool_s2$l_pool_map_segments; /* number of segments in POOL_MAP actually used for SDA */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit}> pointers */N struct _npool_data_s2 *npool_s2$pq_npool_data; /* required for SDA */#else) unsigned __int64 npool_s2$pq_npool_data;#endifN unsigned __int64 npool_s2$q_filler3; /* octaword alignment filler */ } NPOOL_DATA_S2;"#define NPOOL_DATA_S2$C_LENGTH 128"#define NPOOL_DATA_S2$K_LENGTH 128  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* R~>estore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NPOOL_DATA_LOADED */ wwPC[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** >authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, dup>licated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* C >reated: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */I/* Source: 17-MAY-1993 17:08:13 $1$DGA8345:[LIB_H.SRC]NSAARGDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $NSAARGDEF ***/#ifndef __NSAARGDEF_LOADED#define __NSAARGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef> __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __>struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* Security Auditing argument list definitions */N/*- */N/*+ > */N/* Argument list header offset definitions */N/*- */ #define NSA$M_ARG_FLAG_ALARM 0x1 #define NSA$M_ARG_FLAG_JOURN 0x2 #define NSA$M_ARG_FLAG_MANDY 0x4#define NSA$C_ARGHDR_LENGTH 12#define NSA$K_ARGHDR_LENGTH 12N#define NSA$S_NSAARGHDRDEF 12 /* Old size name - synonym */ typedef struct _nsaarghdr {N unsigned int nsa$l_arg_count; /* Argumen >t list count */ __union {N unsigned int nsa$l_arg_id; /* Record identification longword */ __struct {N unsigned short int nsa$w_arg_type; /* Record type */N unsigned short int nsa$w_arg_subtype; /* Record subtype */" } nsa$r_arg_id_fields; } nsa$r_arg_id_overlay; __union {N unsigned char nsa$b_arg_flag; /* Flags byte */ __struct {S > unsigned nsa$v_arg_flag_alarm : 1; /* Generate alarm for this record */N unsigned nsa$v_arg_flag_journ : 1; /* Journal this record */N unsigned nsa$v_arg_flag_mandy : 1; /* Mandatory auditing */' unsigned nsa$v_fill_0_ : 5; } nsa$r_flag_bits;! } nsa$r_arg_flag_overlay;N unsigned char nsa$b_arg_pktnum; /* Number of packets */N char nsa$t_arg_spare [2]; /* Spare bytes */ >#if defined(__VAXC) char nsa$t_arg_list[];#elseU/* Warning: empty char[] member for nsa$t_arg_list at end of structure not created */"#endif /* #if defined(__VAXC) */ } NSAARGHDR; #if !defined(__VAXC)6#define nsa$l_arg_id nsa$r_arg_id_overlay.nsa$l_arg_idN#define nsa$w_arg_type nsa$r_arg_id_overlay.nsa$r_arg_id_fields.nsa$w_arg_typeT#define nsa$w_arg_subtype nsa$r_arg_id_overlay.nsa$r_arg_id_fields.nsa$w_arg_subtype<#define nsa$b_arg_flag nsa$r_arg_flag_overlay.nsa$b_arg_fl >agX#define nsa$v_arg_flag_alarm nsa$r_arg_flag_overlay.nsa$r_flag_bits.nsa$v_arg_flag_alarmX#define nsa$v_arg_flag_journ nsa$r_arg_flag_overlay.nsa$r_flag_bits.nsa$v_arg_flag_journX#define nsa$v_arg_flag_mandy nsa$r_arg_flag_overlay.nsa$r_flag_bits.nsa$v_arg_flag_mandy"#endif /* #if !defined(__VAXC) */ N/*+ */N/* Data packet argument passing mechanism definitions */N/*- > */N#define NSA$K_ARG_MECH_BYTE 0 /* Byte value */N#define NSA$K_ARG_MECH_WORD 1 /* Word value */N#define NSA$K_ARG_MECH_LONG 2 /* Longword value */N#define NSA$K_ARG_MECH_QUAD 3 /* Quadword value */N#define NSA$K_ARG_MECH_DESCR 4 /* Descriptor */N#define NSA$K_ARG_MECH_ADESCR 5 /* Address of desc >riptor */#define NSA$K_ARG_MECHNUM 6N/*+ */N/* Argument list definitions */N/*- */N/* File access */#define NSA$C_ARG1_LENGTH 52#define NSA$K_ARG1_LENGTH 52N#define NSA$S_NSAARG1DEF 52 /* Old size name - synonym > */ typedef struct _nsaarg1 { NSAARGHDR nsa$r_nsaarghdr;N unsigned int nsa$l_arg1_facmod_tm; /* FACMOD type and mechanism */N unsigned int nsa$l_arg1_facmod; /* File access mode */N unsigned int nsa$l_arg1_filnam_tm; /* FILNAM type and mechanism */N unsigned int nsa$l_arg1_filnam_siz; /* File name size */N unsigned int nsa$l_arg1_filnam_ptr; /* File name address */N unsigned int nsa$l_arg1_imgnam_t >m; /* IMGNAM type and mechanism */N unsigned __int64 nsa$q_arg1_imgnam; /* Image name */N unsigned int nsa$l_arg1_privused_tm; /* PRIVUSED type and mechanism */N unsigned int nsa$l_arg1_privused; /* Privileges used for access */ } NSAARG1;N/* Volume mount */#define NSA$C_ARG2_LENGTH 96#define NSA$K_ARG2_LENGTH 96N#define NSA$S_NSAARG2DEF 96 /* Old size name - synonym > */ typedef struct _nsaarg2 { NSAARGHDR nsa$r_nsaarghdr;N unsigned int nsa$l_arg2_uic_tm; /* UIC type and mechanism */N unsigned int nsa$l_arg2_uic; /* Volume UIC */N unsigned int nsa$l_arg2_volpro_tm; /* VOLPRO type and mechanism */N unsigned int nsa$l_arg2_volpro; /* Volume protection */N unsigned int nsa$l_arg2_mouflg_tm; /* MOUFLG type and mechanism */N unsigned int nsa$l_arg2_>mouflg; /* Mount flags */N unsigned int nsa$l_arg2_imgnam_tm; /* IMGNAM type and mechanism */N unsigned __int64 nsa$q_arg2_imgnam; /* Image name */N unsigned int nsa$l_arg2_devnam_tm; /* DEVNAM type and mechanism */N unsigned int nsa$l_arg2_devnam_siz; /* Device name size */N unsigned int nsa$l_arg2_devnam_ptr; /* Device name address */N unsigned int nsa$l_arg2_lognam_tm; /* LOGNAM type> and mechanism */N unsigned int nsa$l_arg2_lognam_siz; /* Logical name size */N unsigned int nsa$l_arg2_lognam_ptr; /* Logical name address */N unsigned int nsa$l_arg2_volnam_tm; /* VOLNAM type and mechanism */N unsigned int nsa$l_arg2_volnam_siz; /* Volume name size */N unsigned int nsa$l_arg2_volnam_ptr; /* Volume name address */N unsigned int nsa$l_arg2_volsnam_tm; /* VOLSNAM type and mechanism */N > unsigned int nsa$l_arg2_volsnam_siz; /* Volume set name size */N unsigned int nsa$l_arg2_volsnam_ptr; /* Volume set name address */ } NSAARG2;N/* Volume dismount */#define NSA$C_ARG3_LENGTH 80#define NSA$K_ARG3_LENGTH 80N#define NSA$S_NSAARG3DEF 80 /* Old size name - synonym */ typedef struct _nsaarg3 { NSAARGHDR nsa$r_nsaarghdr;N unsigned int nsa$l_arg3_dmouflg_tm; /* DMO>UFLG type and mechanism */N unsigned int nsa$l_arg3_dmouflg; /* Dismount flags */N unsigned int nsa$l_arg3_imgnam_tm; /* IMGNAM type and mechanism */N unsigned __int64 nsa$q_arg3_imgnam; /* Image name */N unsigned int nsa$l_arg3_devnam_tm; /* DEVNAM type and mechanism */N unsigned int nsa$l_arg3_devnam_siz; /* Device name size */N unsigned int nsa$l_arg3_devnam_ptr; /* Device name address > */N unsigned int nsa$l_arg3_lognam_tm; /* LOGNAM type and mechanism */N unsigned int nsa$l_arg3_lognam_siz; /* Logical name size */N unsigned int nsa$l_arg3_lognam_ptr; /* Logical name address */N unsigned int nsa$l_arg3_volnam_tm; /* VOLNAM type and mechanism */N unsigned int nsa$l_arg3_volnam_siz; /* Volume name size */N unsigned int nsa$l_arg3_volnam_ptr; /* Volume name address */N unsigned int n >sa$l_arg3_volsnam_tm; /* VOLSNAM type and mechanism */N unsigned int nsa$l_arg3_volsnam_siz; /* Volume set name size */N unsigned int nsa$l_arg3_volsnam_ptr; /* Volume set name address */ } NSAARG3;N/* Global section access */#define NSA$C_ARG4_LENGTH 64#define NSA$K_ARG4_LENGTH 64N#define NSA$S_NSAARG4DEF 64 /* Old size name - synonym */ typedef struct _nsaarg4 { NSAARGHDR ns>a$r_nsaarghdr;N unsigned int nsa$l_arg4_facmod_tm; /* FACMOD type and mechanism */N unsigned int nsa$l_arg4_facmod; /* File access mode */N unsigned int nsa$l_arg4_filnam_tm; /* FILNAM type and mechanism */N unsigned int nsa$l_arg4_filnam_siz; /* File name size */N unsigned int nsa$l_arg4_filnam_ptr; /* File name address */N unsigned int nsa$l_arg4_imgnam_tm; /* IMGNAM type and mechanism */N unsign >ed __int64 nsa$q_arg4_imgnam; /* Image name */N unsigned int nsa$l_arg4_secnam_tm; /* SECNAM type and mechanism */N unsigned int nsa$l_arg4_secnam_siz; /* File name size */N unsigned int nsa$l_arg4_secnam_ptr; /* File name address */N unsigned int nsa$l_arg4_privused_tm; /* PRIVUSED type and mechanism */N unsigned int nsa$l_arg4_privused; /* Privileges used for access */ } NSAARG4; $#pragma __member>_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NSAARGDEF_LOADED */ wwp[UM/***************************************************************************/M/** **/M/** HPE CO>NFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL.> This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/************************************************************* >**************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */G/* Source: 24-FEB-1997 09:42:02 $1$DGA8345:[LIB_H.SRC]NSABDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $NSABDEF ***/#ifndef __NSABDEF_LOADED#define __NSABDEF_LOADED 1 G >#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __opti>onal_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Define the layout of the Non-discretionary Security Audit Block. */ >N/* */N/* The NSAB is the structure which is passed to the internal auditing entry */N/* point (NSA$AUDIT_EVENT) and contains a list of audit packets along with */N/* a couple of flags. */N/* */#define NSAB$M_NONPAGED 0x1#define NSAB$M_NUKENSAB 0x2#define NSAB$C_HDR_LENGTH 72#define NSAB$K >_HDR_LENGTH 72#define NSAB$S_NSABDEF 72 typedef struct _nsab {N struct _nsab *nsab$l_flink; /* FLINK */N struct _nsab *nsab$l_blink; /* BLINK */N unsigned short int nsab$w_size; /* size of NSAB buffer */N unsigned char nsab$b_type; /* type of structure (DYN$C_NSAB) */N unsigned char nsab$b_subtype; /* subtype field (not used) */S int nsab$l_fill_1; > /* Keep offsets compatible with previous */N/* incarnations */ __union {N unsigned int nsab$l_flags; /* miscellaneous flags */ __struct {O unsigned nsab$v_nonpaged : 1; /* message entry is non-paged pool */N unsigned nsab$v_nukensab : 1; /* force NSAB deallocation */( unsigned nsab$v_fill_2_ : 6; } nsab$r_fill_1_; } nsab$r_fil >l_0_;N unsigned int nsab$l_supplied; /* supplied packet mask */N struct _nsab *nsab$l_baseaddr; /* address of NSAB to deallocate */N void *nsab$l_audit_block; /* address of audit buffer */N unsigned char nsab$b_acb [36]; /* ACB used to wake audit server */N unsigned int nsab$l_sender_epid; /* sender's EPID */ } NSAB; #if !defined(__VAXC)0#define nsab$l_flags nsab$r_fill_0_.nsab$l_flagsE#define >nsab$v_nonpaged nsab$r_fill_0_.nsab$r_fill_1_.nsab$v_nonpagedE#define nsab$v_nukensab nsab$r_fill_0_.nsab$r_fill_1_.nsab$v_nukensab"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NSABDEF_LOADED */  >wwT[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/*>* 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Sof>tware, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */I/* Source: 12-DEC-1995 10:13:13 $1$DGA8345:[LIB_H.SRC]NSAEVTDEF.SDL;1 *//********************* >***********************************************************************************************************//*** MODULE $NSAEVTDEF ***/#ifndef __NSAEVTDEF_LOADED#define __NSAEVTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required> ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define >__union variant_union#endif#endif N/*+ */P/* Non-Discretionary Security Auditing event definitions. This macro defines */P/* the bits which are used to enable alarm and audit events for each class of */Q/* system security relevant event. This definition also defines the format of */N/* the mandatory process auditing event vectors. */N/*- > */N#define NSA$S_NSAAXPDEF 40 /* Old size name - synonym */ typedef struct _nsa$r_nsaaxp {N char nsa$b_evt_axp_fill [8]; /* preserve pre-V6.0 layout */N unsigned int nsa$l_evt_failure; /* Access failures event mask */N unsigned int nsa$l_evt_success; /* Successful access event mask */N unsigned int nsa$l_evt_sysprv; /* Success due to SYSPRV event mask */N unsigned int nsa$l_evt_bypass; /* S >uccess due to BYPASS event mask */O unsigned int nsa$l_evt_upgrade; /* Success due to UPGRADE event mask */Q unsigned int nsa$l_evt_downgrade; /* Success due to DOWNGRADE event mask */N unsigned int nsa$l_evt_grpprv; /* Success due to GRPPRV event mask */O unsigned int nsa$l_evt_readall; /* Success due to READALL event mask */ } NSA$R_NSAAXP;P#define NSA$K_NUM_OBJECT_ACCESS 8 /* number of privileged access arrays */#define NSA$M_EVT_CREATION 0x1#defin >e NSA$M_EVT_DEACCESS 0x2#define NSA$M_EVT_DELETION 0x4N#define NSA$K_NUM_ACC_OTHER 3 /* number of "other" bits */N#define NSA$K_ACCESS_LENGTH 36 /* size of object access event mask */N#define NSA$S_NSAACCDEF 36 /* Old size name - synonym */ typedef struct _nsa$r_nsaacc {N unsigned int nsa$l_acc_failure; /* Access failures event mask */N unsigned int nsa$l_acc_success; /* Successful access event mask */N unsigned> int nsa$l_acc_sysprv; /* Success due to SYSPRV event mask */N unsigned int nsa$l_acc_bypass; /* Success due to BYPASS event mask */O unsigned int nsa$l_acc_upgrade; /* Success due to UPGRADE event mask */Q unsigned int nsa$l_acc_downgrade; /* Success due to DOWNGRADE event mask */N unsigned int nsa$l_acc_grpprv; /* Success due to GRPPRV event mask */O unsigned int nsa$l_acc_readall; /* Success due to READALL event mask */ __union {N unsign >ed int nsa$l_acc_other; /* other object-specific events */ __struct {N unsigned nsa$v_evt_creation : 1; /* object creation */N unsigned nsa$v_evt_deaccess : 1; /* object deaccess */N unsigned nsa$v_evt_deletion : 1; /* object delete (devices) */' unsigned nsa$v_fill_0_ : 5;$ } nsa$r_evt_object_bits;" } nsa$r_acc_other_overlay; } NSA$R_NSAACC; #if !defined(__VAXC)?#define nsa$l_ >acc_other nsa$r_acc_other_overlay.nsa$l_acc_other[#define nsa$v_evt_creation nsa$r_acc_other_overlay.nsa$r_evt_object_bits.nsa$v_evt_creation[#define nsa$v_evt_deaccess nsa$r_acc_other_overlay.nsa$r_evt_object_bits.nsa$v_evt_deaccess[#define nsa$v_evt_deletion nsa$r_acc_other_overlay.nsa$r_evt_object_bits.nsa$v_evt_deletion"#endif /* #if !defined(__VAXC) */ #define NSA$M_EVT_ACL 0x1#define NSA$M_EVT_MOUNT 0x2#define NSA$M_EVT_UAF 0x4#define NSA$M_EVT_INSTAL 0x8#define NSA$M_EV >T_AUDIT 0x10#define NSA$M_EVT_CUSTOMER 0x20#define NSA$M_EVT_CSS 0x40#define NSA$M_EVT_LP 0x80#define NSA$M_EVT_SYSTIME 0x100#define NSA$M_EVT_SYSGEN 0x200"#define NSA$M_EVT_IDENTIFIER 0x400"#define NSA$M_EVT_CONNECTION 0x800#define NSA$M_EVT_NCP 0x1000'#define NSA$M_EVT_AUTHENTICATION 0x2000N#define NSA$K_NUM_SYS_EVENTS 14 /* number of system event types */N#define NSA$K_NUM_LOGIN_EVENTS 4 /* number of login event types */N#define NSA$K_NUM_PRIV_EVENTS 2 > /* number of priv audit event types */#define NSA$M_PRC_CREPRC 0x1#define NSA$M_PRC_DELPRC 0x2#define NSA$M_PRC_SCHDWK 0x4#define NSA$M_PRC_CANWAK 0x8#define NSA$M_PRC_WAKE 0x10#define NSA$M_PRC_SUSPND 0x20#define NSA$M_PRC_RESUME 0x40#define NSA$M_PRC_GRANTID 0x80#define NSA$M_PRC_REVOKID 0x100#define NSA$M_PRC_GETJPI 0x200#define NSA$M_PRC_FORCEX 0x400#define NSA$M_PRC_SIGPRC 0x800#define NSA$M_PRC_SETPRI 0x1000 #define NSA$M_PRC_PRCTERM 0x2000)#define NSA$M_ >PRC_CPU_CAPABILITIES 0x4000-#define NSA$M_PRC_PROCESS_CAPABILITIES 0x8000*#define NSA$M_PRC_PROCESS_AFFINITY 0x10000/#define NSA$M_PRC_SET_IMPLICIT_AFFINITY 0x20000N#define NSA$K_NUM_PROCESS_EVENTS 18 /* number of process control bits */#define NSA$M_EVT_ILLFORMED 0x1N#define NSA$K_NUM_AUDIT_EVENTS 1 /* number of audit event types */#define NSA$M_PSB_CREATE 0x1#define NSA$M_PSB_DELETE 0x2#define NSA$M_PSB_MODIFY 0x4N#define NSA$K_NUM_PERSONA_EVENTS 3 /* number >of persona control bits */O#define NSA$C_EVT_LENGTH 40 /* size of alarm or audit event mask */O#define NSA$K_EVT_LENGTH 40 /* size of alarm or audit event mask */N#define NSA$S_NSAEVTDEF 40 /* Old size name - synonym */ typedef struct _nsa$r_nsaevt { __union {N unsigned int nsa$l_evt_sys; /* miscellaneous system event mask */ __struct {N unsigned nsa$v_evt_acl : 1; /* ACL requested alarms and audits */>N unsigned nsa$v_evt_mount : 1; /* MOUNT and DISMOUNT requests */N/* modifications made to the system */N unsigned nsa$v_evt_uaf : 1; /* or network authorization files */N unsigned nsa$v_evt_instal : 1; /* INSTALL operations */O unsigned nsa$v_evt_audit : 1; /* SET AUDIT operations (obsolete) */N unsigned nsa$v_evt_customer : 1; /* Customer events */N unsigned n>sa$v_evt_css : 1; /* CSS events */N unsigned nsa$v_evt_lp : 1; /* LP events */N unsigned nsa$v_evt_systime : 1; /* System time modification */N unsigned nsa$v_evt_sysgen : 1; /* SYSGEN parameter modification */W unsigned nsa$v_evt_identifier : 1; /* Identifier auditing (as privilege) */N unsigned nsa$v_evt_connection : 1; /* Connection auditing */N unsigned nsa$v_evt_ncp : 1 >; /* NCP command line auditing */N unsigned nsa$v_evt_authentication : 1; /* DAS auditing */' unsigned nsa$v_fill_1_ : 2;! } nsa$r_evt_sys_bits; } nsa$r_evt_sys_overlay;N unsigned char nsa$b_evt_logb; /* breakin detection event mask */N unsigned char nsa$b_evt_logi; /* login event mask */N unsigned char nsa$b_evt_logf; /* login failure event mask */N unsigned char nsa$b_evt_logo >; /* logout event mask */ __struct {U unsigned __int64 nsa$q_prvaud_success; /* successfull privilege audit mask */U unsigned __int64 nsa$q_prvaud_failure; /* successfull privilege audit mask */ } nsa$r_privilege_masks; __union {N unsigned int nsa$l_evt_process; /* process control auditing */ __struct {N unsigned nsa$v_prc_creprc : 1; /* Create process */N unsigned nsa$v_prc_d>elprc : 1; /* Delete process */N unsigned nsa$v_prc_schdwk : 1; /* Schedule process wakeup */N unsigned nsa$v_prc_canwak : 1; /* Cancel process wakeup */N unsigned nsa$v_prc_wake : 1; /* Wake process */N unsigned nsa$v_prc_suspnd : 1; /* Suspend process */N unsigned nsa$v_prc_resume : 1; /* Resume process */N unsigned nsa$v_prc_grantid : 1; /* Grant ident>ifier */N unsigned nsa$v_prc_revokid : 1; /* Revoke identifier */O unsigned nsa$v_prc_getjpi : 1; /* Get job or process information */N unsigned nsa$v_prc_forcex : 1; /* Force image exit */N unsigned nsa$v_prc_sigprc : 1; /* Signal process (undocumented) */N unsigned nsa$v_prc_setpri : 1; /* Set process priority */[ unsigned nsa$v_prc_prcterm : 1; /* Detect process termination (undocum >ented) */S unsigned nsa$v_prc_cpu_capabilities : 1; /* Change in CPU capability */[ unsigned nsa$v_prc_process_capabilities : 1; /* Change in process capability */U unsigned nsa$v_prc_process_affinity : 1; /* Change in process affinity */[ unsigned nsa$v_prc_set_implicit_affinity : 1; /* Change in implicit affinity */' unsigned nsa$v_fill_2_ : 6;$ } nsa$r_evt_prcctl_bits;# } nsa$r_evt_prcctl_overlay; __union { >N unsigned int nsa$l_evt_audit; /* miscellaneous audit event mask */ __struct {N unsigned nsa$v_evt_illformed : 1; /* Ill-formed TCB audit */' unsigned nsa$v_fill_3_ : 7;# } nsa$r_evt_audit_bits;" } nsa$r_evt_audit_overlay; __union {N unsigned int nsa$l_evt_persona; /* persona auditing */ __struct {N unsigned nsa$v_psb_create : 1; /* Create persona */N > unsigned nsa$v_psb_delete : 1; /* Delete persona */N unsigned nsa$v_psb_modify : 1; /* Modify persona */' unsigned nsa$v_fill_4_ : 5;% } nsa$r_evt_persona_bits;$ } nsa$r_evt_persona_overlay;N unsigned int nsa$l_evt_spare_l3; /* spare longword */ } NSA$R_NSAEVT; #if !defined(__VAXC)9#define nsa$l_evt_sys nsa$r_evt_sys_overlay.nsa$l_evt_sysL#define nsa$v_evt_acl nsa$r_evt_sys_overlay.ns>a$r_evt_sys_bits.nsa$v_evt_aclP#define nsa$v_evt_mount nsa$r_evt_sys_overlay.nsa$r_evt_sys_bits.nsa$v_evt_mountL#define nsa$v_evt_uaf nsa$r_evt_sys_overlay.nsa$r_evt_sys_bits.nsa$v_evt_uafR#define nsa$v_evt_instal nsa$r_evt_sys_overlay.nsa$r_evt_sys_bits.nsa$v_evt_instalP#define nsa$v_evt_audit nsa$r_evt_sys_overlay.nsa$r_evt_sys_bits.nsa$v_evt_auditV#define nsa$v_evt_customer nsa$r_evt_sys_overlay.nsa$r_evt_sys_bits.nsa$v_evt_customerL#define nsa$v_evt_css nsa$r_evt_sys_overlay.nsa$r_evt_sys_bi>ts.nsa$v_evt_cssJ#define nsa$v_evt_lp nsa$r_evt_sys_overlay.nsa$r_evt_sys_bits.nsa$v_evt_lpT#define nsa$v_evt_systime nsa$r_evt_sys_overlay.nsa$r_evt_sys_bits.nsa$v_evt_systimeR#define nsa$v_evt_sysgen nsa$r_evt_sys_overlay.nsa$r_evt_sys_bits.nsa$v_evt_sysgenZ#define nsa$v_evt_identifier nsa$r_evt_sys_overlay.nsa$r_evt_sys_bits.nsa$v_evt_identifierZ#define nsa$v_evt_connection nsa$r_evt_sys_overlay.nsa$r_evt_sys_bits.nsa$v_evt_connectionL#define nsa$v_evt_ncp nsa$r_evt_sys_overlay.nsa$r_evt_sys_>bits.nsa$v_evt_ncpb#define nsa$v_evt_authentication nsa$r_evt_sys_overlay.nsa$r_evt_sys_bits.nsa$v_evt_authenticationG#define nsa$q_prvaud_success nsa$r_privilege_masks.nsa$q_prvaud_successG#define nsa$q_prvaud_failure nsa$r_privilege_masks.nsa$q_prvaud_failureD#define nsa$l_evt_process nsa$r_evt_prcctl_overlay.nsa$l_evt_processX#define nsa$v_prc_creprc nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_creprcX#define nsa$v_prc_delprc nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_>prc_delprcX#define nsa$v_prc_schdwk nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_schdwkX#define nsa$v_prc_canwak nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_canwakT#define nsa$v_prc_wake nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_wakeX#define nsa$v_prc_suspnd nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_suspndX#define nsa$v_prc_resume nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_resumeZ#define nsa$v_prc_grantid nsa$r_evt_prcctl_overl>ay.nsa$r_evt_prcctl_bits.nsa$v_prc_grantidZ#define nsa$v_prc_revokid nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_revokidX#define nsa$v_prc_getjpi nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_getjpiX#define nsa$v_prc_forcex nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_forcexX#define nsa$v_prc_sigprc nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_sigprcX#define nsa$v_prc_setpri nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_setpriZ#define ns>a$v_prc_prcterm nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_prcterml#define nsa$v_prc_cpu_capabilities nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_cpu_capabilitiest#define nsa$v_prc_process_capabilities nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_process_capabilitiesl#define nsa$v_prc_process_affinity nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits.nsa$v_prc_process_affinityv#define nsa$v_prc_set_implicit_affinity nsa$r_evt_prcctl_overlay.nsa$r_evt_prcctl_bits>.nsa$v_prc_set_implicit_affinity?#define nsa$l_evt_audit nsa$r_evt_audit_overlay.nsa$l_evt_audit\#define nsa$v_evt_illformed nsa$r_evt_audit_overlay.nsa$r_evt_audit_bits.nsa$v_evt_illformedE#define nsa$l_evt_persona nsa$r_evt_persona_overlay.nsa$l_evt_personaZ#define nsa$v_psb_create nsa$r_evt_persona_overlay.nsa$r_evt_persona_bits.nsa$v_psb_createZ#define nsa$v_psb_delete nsa$r_evt_persona_overlay.nsa$r_evt_persona_bits.nsa$v_psb_deleteZ#define nsa$v_psb_modify nsa$r_evt_persona_overlay.nsa$r>_evt_persona_bits.nsa$v_psb_modify"#endif /* #if !defined(__VAXC) */ #define NSA$M_EVT_LOG_BAT 0x1#define NSA$M_EVT_LOG_DIA 0x2#define NSA$M_EVT_LOG_LOC 0x4#define NSA$M_EVT_LOG_REM 0x8#define NSA$M_EVT_LOG_NET 0x10#define NSA$M_EVT_LOG_SUB 0x20#define NSA$M_EVT_LOG_DET 0x40#define NSA$M_EVT_LOG_SRV 0x80N#define NSA$K_NUM_JOB_TYPES 8 /* number of job types */ %typedef struct _nsa$r_nsaevtlogbits {N unsigned nsa$v_evt_log_bat : 1; /* batch > */N unsigned nsa$v_evt_log_dia : 1; /* dialup */N unsigned nsa$v_evt_log_loc : 1; /* local */N unsigned nsa$v_evt_log_rem : 1; /* remote */N unsigned nsa$v_evt_log_net : 1; /* network */N unsigned nsa$v_evt_log_sub : 1; /* subprocess */N unsigned nsa$v_evt_log_det : 1; /* detached process >*/N unsigned nsa$v_evt_log_srv : 1; /* server thread */ } NSA$R_NSAEVTLOGBITS;#define NSA$C_OLD_EVT_LENGTH 40#define NSA$K_OLD_EVT_LENGTH 40N#define NSA$S_NSAOLDEVTDEF 40 /* Old size name - synonym */ typedef struct _nsaoldevt {N unsigned int nsa$l_dummy_evt_1; /* System bits are still the same */N unsigned int nsa$l_dummy_evt_2; /* Breakin/Login/Logout bytes */Q/***************************************************>************************** */Q/* The following file access masks must be contiguous and in the current order */Q/***************************************************************************** */N unsigned int nsa$l_old_evt_failure; /* Access failures event mask */N unsigned int nsa$l_old_evt_success; /* Successful access event mask */N unsigned int nsa$l_old_evt_sysprv; /* Success due to SYSPRV event mask */N unsigned int nsa$l_old_evt_bypass; /* Success due to BYPASS e>vent mask */O unsigned int nsa$l_old_evt_upgrade; /* Success due to UPGRADE event mask */S unsigned int nsa$l_old_evt_downgrade; /* Success due to DOWNGRADE event mask */N unsigned int nsa$l_old_evt_grpprv; /* Success due to GRPPRV event mask */O unsigned int nsa$l_old_evt_readall; /* Success due to READALL event mask */Q/***************************************************************************** */N/* End of file access masks */>Q/***************************************************************************** */ } NSAOLDEVT;N#define NSA$S_ALARM_NAME 32 /* maximum length of an alarm name */N#define NSA$S_AUDIT_NAME 65 /* maximum length of an audit name */Q#define NSA$S_IMAGE_NAME 1022 /* maximum size of an image name (XQP) */S#define NSA$S_JOURNAL_NAME 65 /* maximum length of alarm or audit name */W#define NSA$K_MAX_JOURNALS 1 /* maximum number of alarm or au >dit journals */O#define NSA$S_MSGFILNAM 32 /* maximum size of message file name */X#define NSA$K_SCRATCH_PAGES 10 /* number of scratch P1 pages (NSA$A_SCRATCH) */N#define NSA$K_SCRATCH_LENGTH 5120 /* byte length of P1 scratch space */N#define NSA$S_NSACONDEF 4 /* Old size name - synonym */ typedef struct _nsa$r_nsacon {T unsigned int nsa$l_dummy; /* dummy structure to pick up NSA$ prefix */ } NSA$R_NSACON; %typedef >struct _nsa$r_sysuaf_fields { __union {N unsigned __int64 nsa$q_sysuaf_fields; /* SYSUAF flags: */ __struct {O unsigned nsa$v_sysuaf_access : 1; /* ACCESS modified (obsolete) */N unsigned nsa$v_sysuaf_account : 1; /* ACCOUNT modified */N unsigned nsa$v_sysuaf_astlm : 1; /* ASTLM modified */N unsigned nsa$v_sysuaf_batch : 1; /* BATCH modified */N unsigned nsa$v_sysuaf_>biolm : 1; /* BIOLM modified */N unsigned nsa$v_sysuaf_bytlm : 1; /* BYTLM modified */N unsigned nsa$v_sysuaf_cli : 1; /* CLI modified */N unsigned nsa$v_sysuaf_clitables : 1; /* CLITABLES modified */N unsigned nsa$v_sysuaf_cputime : 1; /* CPUTIME modified */R unsigned nsa$v_sysuaf_defprivileges : 1; /* DEFPRIVILEGES modified */N unsigned nsa$v_sysuaf_device : 1; /* DEVICE> modified */N unsigned nsa$v_sysuaf_dialup : 1; /* DIALUP modified */N unsigned nsa$v_sysuaf_diolm : 1; /* DIOLM modified */N unsigned nsa$v_sysuaf_directory : 1; /* DIRECTORY modified */N unsigned nsa$v_sysuaf_enqlm : 1; /* ENQLM modified */N unsigned nsa$v_sysuaf_expiration : 1; /* EXPIRATION modified */N unsigned nsa$v_sysuaf_fillm : 1; /* FILLM modified */N > unsigned nsa$v_sysuaf_flags : 1; /* FLAGS modified */Y unsigned nsa$v_sysuaf_interactive : 1; /* INTERACTIVE modified (obsolete) */N unsigned nsa$v_sysuaf_jtquota : 1; /* JTQUOTA modified */N unsigned nsa$v_sysuaf_lgicmd : 1; /* LGICMD modified */N unsigned nsa$v_sysuaf_local : 1; /* LOCAL modified */N unsigned nsa$v_sysuaf_maxdetach : 1; /* MAXDETACH modified */N unsi>gned nsa$v_sysuaf_maxjobs : 1; /* MAXJOBS modified */N unsigned nsa$v_sysuaf_maxacctjobs : 1; /* MAXACCTJOBS modified */N unsigned nsa$v_sysuaf_network : 1; /* NETWORK modified */N unsigned nsa$v_sysuaf_owner : 1; /* OWNER modified */N unsigned nsa$v_sysuaf_password : 1; /* PASSWORD modified */N unsigned nsa$v_sysuaf_pbytlm : 1; /* PBYTLM modified */O unsigned nsa$v_sysuaf_pflags :> 1; /* PFLAGS modified (obsolete) */W unsigned nsa$v_sysuaf_p_restrict : 1; /* P_RESTRICT modified (obsolete) */N unsigned nsa$v_sysuaf_pgflquota : 1; /* PGFLQUOTA modified */N unsigned nsa$v_sysuaf_prclm : 1; /* PRCLM modified */N unsigned nsa$v_sysuaf_primedays : 1; /* PRIMEDAYS modified */N unsigned nsa$v_sysuaf_priority : 1; /* PRIORITY modified */N unsigned nsa$v_sysuaf_privileges : 1; /* PR>IVILEGES modified */N unsigned nsa$v_sysuaf_pwdlifetime : 1; /* PWDLIFETIME modified */N unsigned nsa$v_sysuaf_pwdminimum : 1; /* PWDMINIMUM modified */N unsigned nsa$v_sysuaf_quepriority : 1; /* QUEPRIORITY modified */N unsigned nsa$v_sysuaf_remote : 1; /* REMOTE modified */O unsigned nsa$v_sysuaf_sflags : 1; /* SFLAGS modified (obsolete) */W unsigned nsa$v_sysuaf_s_restrict : 1; /* S_RESTRICT modified (obsol>ete) */N unsigned nsa$v_sysuaf_shrfillm : 1; /* SHRFILLM modified */N unsigned nsa$v_sysuaf_tqelm : 1; /* TQELM modified */N unsigned nsa$v_sysuaf_uic : 1; /* UIC modified */N unsigned nsa$v_sysuaf_wsdefault : 1; /* WSDEFAULT modified */N unsigned nsa$v_sysuaf_wsextent : 1; /* WSEXTENT modified */N unsigned nsa$v_sysuaf_wsquota : 1; /* WSQUOTA modified */^ unsi>gned nsa$v_sysuaf_encrypt : 1; /* PRIMARY password hash algorithm modified */a unsigned nsa$v_sysuaf_encrypt2 : 1; /* SECONDARY password hash algorithm modified */N unsigned nsa$v_sysuaf_salt : 1; /* SALT modified */S unsigned nsa$v_sysuaf_password2 : 1; /* Secondary PASSWORD modified */O unsigned nsa$v_sysuaf_pwd_date : 1; /* Password expiration date */Z unsigned nsa$v_sysuaf_pwd2_date : 1; /* Secondary password expira>tion date */N unsigned nsa$v_sysuaf_logfails : 1; /* LOGFAILS modified */N unsigned nsa$v_sysuaf_lastlogin_i : 1; /* LASTLOGIN_I modified */N unsigned nsa$v_sysuaf_lastlogin_n : 1; /* LASTLOGIN_N modified */N unsigned nsa$v_sysuaf_min_class : 1; /* MIN_CLASS modified */N unsigned nsa$v_sysuaf_max_class : 1; /* MAX_CLASS modified */O unsigned nsa$v_sysuaf_user_data : 1; /* user data area modified */N > unsigned nsa$v_sysuaf_def_class : 1; /* DEF_CLASS modified */' unsigned nsa$v_fill_7_ : 3; } nsa$r_fill_6_; } nsa$r_fill_5_; } NSA$R_SYSUAF_FIELDS; #if !defined(__VAXC)=#define nsa$q_sysuaf_fields nsa$r_fill_5_.nsa$q_sysuaf_fieldsK#define nsa$v_sysuaf_access nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_accessM#define nsa$v_sysuaf_account nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_accountI#define nsa$v_sysuaf_astlm nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_s>ysuaf_astlmI#define nsa$v_sysuaf_batch nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_batchI#define nsa$v_sysuaf_biolm nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_biolmI#define nsa$v_sysuaf_bytlm nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_bytlmE#define nsa$v_sysuaf_cli nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_cliQ#define nsa$v_sysuaf_clitables nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_clitablesM#define nsa$v_sysuaf_cputime nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_cputimeY#define nsa$v_sysuaf_defpriv>ileges nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_defprivilegesK#define nsa$v_sysuaf_device nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_deviceK#define nsa$v_sysuaf_dialup nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_dialupI#define nsa$v_sysuaf_diolm nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_diolmQ#define nsa$v_sysuaf_directory nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_directoryI#define nsa$v_sysuaf_enqlm nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_enqlmS#define nsa$v_sysuaf_expiration nsa$r_fill_5_.nsa$>r_fill_6_.nsa$v_sysuaf_expirationI#define nsa$v_sysuaf_fillm nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_fillmI#define nsa$v_sysuaf_flags nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_flagsU#define nsa$v_sysuaf_interactive nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_interactiveM#define nsa$v_sysuaf_jtquota nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_jtquotaK#define nsa$v_sysuaf_lgicmd nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_lgicmdI#define nsa$v_sysuaf_local nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_loca>lQ#define nsa$v_sysuaf_maxdetach nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_maxdetachM#define nsa$v_sysuaf_maxjobs nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_maxjobsU#define nsa$v_sysuaf_maxacctjobs nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_maxacctjobsM#define nsa$v_sysuaf_network nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_networkI#define nsa$v_sysuaf_owner nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_ownerO#define nsa$v_sysuaf_password nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_passwordK#define nsa$>v_sysuaf_pbytlm nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_pbytlmK#define nsa$v_sysuaf_pflags nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_pflagsS#define nsa$v_sysuaf_p_restrict nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_p_restrictQ#define nsa$v_sysuaf_pgflquota nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_pgflquotaI#define nsa$v_sysuaf_prclm nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_prclmQ#define nsa$v_sysuaf_primedays nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_primedaysO#define nsa$v_sysuaf_priority ns>a$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_priorityS#define nsa$v_sysuaf_privileges nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_privilegesU#define nsa$v_sysuaf_pwdlifetime nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_pwdlifetimeS#define nsa$v_sysuaf_pwdminimum nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_pwdminimumU#define nsa$v_sysuaf_quepriority nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_quepriorityK#define nsa$v_sysuaf_remote nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_remoteK#define nsa$v_sysuaf_sflags ns>a$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_sflagsS#define nsa$v_sysuaf_s_restrict nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_s_restrictO#define nsa$v_sysuaf_shrfillm nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_shrfillmI#define nsa$v_sysuaf_tqelm nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_tqelmE#define nsa$v_sysuaf_uic nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_uicQ#define nsa$v_sysuaf_wsdefault nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_wsdefaultO#define nsa$v_sysuaf_wsextent nsa$r_fill_5_.nsa$r_fill_6_.>nsa$v_sysuaf_wsextentM#define nsa$v_sysuaf_wsquota nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_wsquotaM#define nsa$v_sysuaf_encrypt nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_encryptO#define nsa$v_sysuaf_encrypt2 nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_encrypt2G#define nsa$v_sysuaf_salt nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_saltQ#define nsa$v_sysuaf_password2 nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_password2O#define nsa$v_sysuaf_pwd_date nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_pwd_dateQ>#define nsa$v_sysuaf_pwd2_date nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_pwd2_dateO#define nsa$v_sysuaf_logfails nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_logfailsU#define nsa$v_sysuaf_lastlogin_i nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_lastlogin_iU#define nsa$v_sysuaf_lastlogin_n nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_lastlogin_nQ#define nsa$v_sysuaf_min_class nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_min_classQ#define nsa$v_sysuaf_max_class nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_max_clas >sQ#define nsa$v_sysuaf_user_data nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_user_dataQ#define nsa$v_sysuaf_def_class nsa$r_fill_5_.nsa$r_fill_6_.nsa$v_sysuaf_def_class"#endif /* #if !defined(__VAXC) */  'typedef struct _nsa$r_field_tbl_entry {N unsigned int nsa$l_fld_name; /* Address of ascid field name */N unsigned short int nsa$w_fld_offset; /* Offset into record */N unsigned short int nsa$w_fld_size; /* Size of field */N int >(*nsa$l_fld_fmt_rtn)(); /* Format routine */N unsigned int nsa$l_fld_fmt_p1; /* Parameter to format rtn */ } NSA$R_FIELD_TBL_ENTRY;#define NSA$M_SUM_FILE 0x1#define NSA$M_SUM_PRIV 0x2##define NSA$M_SUM_DEJAVU 0x80000000 &typedef struct _nsa$r_nsasummarybits {N unsigned nsa$v_sum_file : 1; /* file access auditing enabled */N unsigned nsa$v_sum_priv : 1; /* privilege auditing enabled */ unsigned nsa$v_fill_1 >: 29;N unsigned nsa$v_sum_dejavu : 1; /* auditing running in past */ } NSA$R_NSASUMMARYBITS; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NSAEVTDEF_LOADED */ wwɍ[UM/*******************************>********************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Developmen>t, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** > **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */I/* Source: 20-APR-1993 14:21:57 $1$DGA8345:[LIB_H.SRC]NSAFAIDEF.SDL;1 *//***************************************************************************** >***************************************************//*** MODULE $NSAFAIDEF ***/#ifndef __NSAFAIDEF_LOADED#define __NSAFAIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short >/* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* > */N/* Define the security auditing failure mode vectors. */N/* */#define NSA$M_FAIL_WAIT 0x1#define NSA$M_FAIL_CRASH 0x2#define NSA$M_FAIL_IGNORE 0x4#define NSA$M_MSG_LOST 0x1#define NSA$C_FAI_LENGTH 12#define NSA$K_FAI_LENGTH 12#define NSA$S_NSAFAIDEF 12 typedef struct _nsafai { __union {. unsigned short i >nt nsa$w_failure_mode; __struct {N unsigned nsa$v_fail_wait : 1; /* Wait for resources */N unsigned nsa$v_fail_crash : 1; /* Crash the system */N unsigned nsa$v_fail_ignore : 1; /* Drop failed audits */' unsigned nsa$v_fill_4_ : 5; } nsa$r_fill_1_; } nsa$r_fill_0_; __union {/ unsigned short int nsa$w_failure_flags; __struct {N unsigned nsa$v_msg_los >t : 1; /* Alarms lost message written? */' unsigned nsa$v_fill_5_ : 7; } nsa$r_fill_3_; } nsa$r_fill_2_;N unsigned int nsa$l_lost_count; /* Failure count */N unsigned short int nsa$w_size; /* Stucture size */N unsigned char nsa$b_type; /* Structure type (DYN$C_NSA) */S unsigned char nsa$b_subtype; /* Structure subtype (DYN$C_NSA_FAILURE) */ } NSAFAI; #if !defined(__V >AXC);#define nsa$w_failure_mode nsa$r_fill_0_.nsa$w_failure_modeC#define nsa$v_fail_wait nsa$r_fill_0_.nsa$r_fill_1_.nsa$v_fail_waitE#define nsa$v_fail_crash nsa$r_fill_0_.nsa$r_fill_1_.nsa$v_fail_crashG#define nsa$v_fail_ignore nsa$r_fill_0_.nsa$r_fill_1_.nsa$v_fail_ignore=#define nsa$w_failure_flags nsa$r_fill_2_.nsa$w_failure_flagsA#define nsa$v_msg_lost nsa$r_fill_2_.nsa$r_fill_3_.nsa$v_msg_lost"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef _>_INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NSAFAIDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is c>onfidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential> **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********** >*********************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */I/* Source: 22-APR-1993 13:30:15 $1$DGA8345:[LIB_H.SRC]NSAIDTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $NSAIDTDEF ***/#ifndef __NSAIDTDEF_LOADED#define __NSAIDTDEF_LOADED 1 G#pragma __nostandard > /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#els>e#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* Security Auditing Impure Data Table offset definitions */N/*- > */#define NSA$C_IDT_LENGTH 4794#define NSA$K_IDT_LENGTH 4794N#define NSA$K_IDT_PAGES 10 /* Number of pages for IDT */#define NSA$S_NSAIDTDEF 4794 typedef struct _nsaidt {N char nsa$t_idt_alarm_hdr [46]; /* Alarm header buffer */N char nsa$t_idt_record_buf [1024]; /* Record buffer */N unsigned __int64 nsa$q_idt_record_descr; /* Record buffer descriptor */N > char nsa$t_idt_record_dt [128]; /* Record descriptor table */[ int nsa$$_fill_1; /* Spare (was obsolete CJF field; IDT_AUDIT_CHAN */N/* audit journal channel number) */N char nsa$b_fill_2 [3584]; /* expand to 10 5120 bytes */ } NSAIDT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size >__restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NSAIDTDEF_LOADED */ ww ?[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is n>ot **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized> to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************************************************************************** >*********/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */I/* Source: 18-JUL-1997 11:01:56 $1$DGA8345:[LIB_H.SRC]NSAIFPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $NSAIFPDEF ***/#ifndef __NSAIFPDEF_LOADED#define __NSAIFPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_a>lignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__V>AXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define NSAP$M_MANDATORY 0x1#define NSAP$M_PRIVMASK 0x2#define NSAP$M_PROCPRIV 0x4#define NSAP$M_AUTHPRIV 0x8#define NSAP$M_AUDIT 0x10#define NSAP$M_ALTPRIV 0x20#define NSAP$M_IDENTIFIER 0x40#define NSAP$M_INTERNAL 0x80#define NSAP$M_IMAGEID 0x100#define NSAP$M_ONE>BIT 0x200#define NSAP$M_NOPROBE 0x400#define NSAP$M_FLUSH 0x800#define NSAP$M_SERVER 0x1000#define NSAP$M_NOFAILAUD 0x2000#define NSAP$M_NOSUCCAUD 0x4000#define NSAP$M_KTBVALID 0x8000#define NSAP$M_PSBVALID 0x10000S#define NSAP$K_LENGTH 28 /* size of input potion of control block */#define NSAP$S_NSAIFPDEF 28 typedef struct _nsaifp {N __union { /* control flags overlay */" unsigned int nsap$l_flags; __>struct {N unsigned nsap$v_mandatory : 1; /* force privilege audit */Y unsigned nsap$v_privmask : 1; /* caller supplied address of privilege mask */N unsigned nsap$v_procpriv : 1; /* check permanent privilege mask */O unsigned nsap$v_authpriv : 1; /* check authorized privilege mask */N unsigned nsap$v_audit : 1; /* privilege audit required */V unsigned nsap$v_altpriv : 1; /* check alternate mask supplied by cal>ler */W unsigned nsap$v_identifier : 1; /* check identifier instead of privilege */` unsigned nsap$v_internal : 1; /* privilege check being performed on behalf of TCB */b unsigned nsap$v_imageid : 1; /* identifier was located in image rights list segment */X unsigned nsap$v_onebit : 1; /* privilege mask contained only a single bit */N unsigned nsap$v_noprobe : 1; /* do not probe item list */N unsigned nsap$v_flush : 1; >/* force audit server buffer flush */N unsigned nsap$v_server : 1; /* audit from trusted (TCB) server */N unsigned nsap$v_nofailaud : 1; /* do not audit failures */N unsigned nsap$v_nosuccaud : 1; /* do not audit success */N unsigned nsap$v_ktbvalid : 1; /* KTB address in R4 is accurate */N/* (reflects the applicable KTB when PCB) */P unsigned nsap$v_psbvalid : 1; /* PSB referenced by KTB > is current */N/* (no need to perform a lazy assume or import ARB) */( unsigned nsap$v_fill_0_ : 7; } nsap$r_flags_bits; } nsap$r_flags_overlay;N unsigned int nsap$l_audit_mask; /* audit mask (NSA$W_FLAGS) */X void *nsap$l_audit_list; /* address of optional audit message itemlist */ __union {Q unsigned int nsap$l_message; /* privilege audit message code ($NSA) */N unsigned int nsap$l_au>dsts; /* privilege audit return status */ } nsap$r_msg_overlay;N __union { /* quadword mask overlay */P unsigned __int64 nsap$q_altpriv; /* alternate privilege mask to check */\ unsigned __int64 nsap$q_priv; /* mask of privileges that were checked (success) */\ unsigned __int64 nsap$q_audpriv; /* mask of privileges to audit (success/failure) */_ unsigned __int64 nsap$q_failpriv; /* mask of privileges that calle >r lacked (failure) */ __struct {N unsigned int nsap$l_identifier; /* identifier to check */ } nsap$r_id_over; } nsap$r_mask_overlay;N void *nsap$l_reply_mailbox; /* reply mailbox descriptor address */ } NSAIFP; #if !defined(__VAXC)6#define nsap$l_flags nsap$r_flags_overlay.nsap$l_flagsP#define nsap$v_mandatory nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_mandatoryN#define nsap$v_privmask nsap$r_flags_overlay.nsap$r_flag>s_bits.nsap$v_privmaskN#define nsap$v_procpriv nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_procprivN#define nsap$v_authpriv nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_authprivH#define nsap$v_audit nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_auditL#define nsap$v_altpriv nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_altprivR#define nsap$v_identifier nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_identifierN#define nsap$v_internal nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_internalL#defin>e nsap$v_imageid nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_imageidJ#define nsap$v_onebit nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_onebitL#define nsap$v_noprobe nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_noprobeH#define nsap$v_flush nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_flushJ#define nsap$v_server nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_serverP#define nsap$v_nofailaud nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_nofailaudP#define nsap$v_nosuccaud nsap$r_flags_overlay.ns >ap$r_flags_bits.nsap$v_nosuccaudN#define nsap$v_ktbvalid nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_ktbvalidN#define nsap$v_psbvalid nsap$r_flags_overlay.nsap$r_flags_bits.nsap$v_psbvalid8#define nsap$l_message nsap$r_msg_overlay.nsap$l_message6#define nsap$l_audsts nsap$r_msg_overlay.nsap$l_audsts9#define nsap$q_altpriv nsap$r_mask_overlay.nsap$q_altpriv3#define nsap$q_priv nsap$r_mask_overlay.nsap$q_priv9#define nsap$q_audpriv nsap$r_mask_overlay.nsap$q_audpriv;#define nsap$q_failpriv ?nsap$r_mask_overlay.nsap$q_failprivN#define nsap$l_identifier nsap$r_mask_overlay.nsap$r_id_over.nsap$l_identifier"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NSAIFPDEF_LOADED */ ww@?[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyrig?ht Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. ? **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */G/* Source: 18-MAY-1993 16:08:22 $1$DGA8345:[LIB_H.SRC]NSASDEF.SDL;1 *//*************************************** ?*****************************************************************************************//*** MODULE $NSASDEF ***/#ifndef __NSASDEF_LOADED#define __NSASDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __?required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union?#endif#endif N/* Define the layout of the structure returned by NSA$SIZE_NSAB. */#define NSAS$M_NOALARM 0x1#define NSAS$M_NOAUDIT 0x2#define NSAS$M_NOPROBE 0x4!#define NSAS$M_PRIVS_SUPPLIED 0x8W#define NSAS$K_MAX_JOURNALS 1 /* maximum number of alarm or audit journals */N#define NSAS$K_LENGTH 76 /* define length of structure */N#define NSAS$S_NSASDEF 76 /* Old size name - synonym */ typedef struct _nsas {N unsi ?gned int nsas$l_size; /* size of required packet list */N unsigned int nsas$l_supplied; /* supplied packet mask */ __union {N unsigned int nsas$l_event; /* event type/subtype as longword */ __struct {N unsigned short int nsas$w_event_type; /* event type */N unsigned short int nsas$w_event_subtype; /* event subtype */% } nsas$r_event_overlay_2; } nsas$r_event_overlay;N ? unsigned int nsas$l_facility; /* event facility */ __union {N unsigned int nsas$l_flags; /* flags */ __struct {N unsigned nsas$v_noalarm : 1; /* do not copy alarm packets */N unsigned nsas$v_noaudit : 1; /* do not copy audit packets */N unsigned nsas$v_noprobe : 1; /* do not probe item list */W unsigned nsas$v_privs_supplied : 1; /* did the caller supp ?ly a priv mask */N/* or identifier list? */( unsigned nsas$v_fill_2_ : 4; } nsas$r_fill_1_; } nsas$r_fill_0_;N unsigned int nsas$l_access_desired; /* actual access desired */ __union {N unsigned int nsas$l_privs_used; /* actual privs used (as longword) */Q unsigned __int64 nsas$q_privs_used; /* actual privs used (as quadword) */$ } nsas$r_privs_used_overlay;N un ?signed int nsas$l_alarm_count; /* number of alarm journals present */N unsigned int nsas$l_audit_count; /* number of audit journals present */N void *nsas$l_min_class_addr; /* address of min. class mask */N void *nsas$l_max_class_addr; /* address of max. class mask */ __union {P unsigned __int64 nsas$q_object_class; /* object class name descriptor */ __struct {R unsigned short int nsas$w_class_length; /* object class name ? length */$ short int nsas$w_fill_1;N void *nsas$l_class_addr; /* object class name buffer address */ } nsas$r_class_desc; } nsas$r_object_overlay;U unsigned __int64 nsas$q_alarm_list [1]; /* array of alarm journals descriptors */U unsigned __int64 nsas$q_audit_list [1]; /* array of audit journals descriptors */N unsigned int nsas$l_final_status; /* actual final status */ } NSAS; #if !defined(__VAXC)6#define nsas ?$l_event nsas$r_event_overlay.nsas$l_eventW#define nsas$w_event_type nsas$r_event_overlay.nsas$r_event_overlay_2.nsas$w_event_type]#define nsas$w_event_subtype nsas$r_event_overlay.nsas$r_event_overlay_2.nsas$w_event_subtype0#define nsas$l_flags nsas$r_fill_0_.nsas$l_flagsC#define nsas$v_noalarm nsas$r_fill_0_.nsas$r_fill_1_.nsas$v_noalarmC#define nsas$v_noaudit nsas$r_fill_0_.nsas$r_fill_1_.nsas$v_noauditC#define nsas$v_noprobe nsas$r_fill_0_.nsas$r_fill_1_.nsas$v_noprobeQ#define nsas$v_p ?rivs_supplied nsas$r_fill_0_.nsas$r_fill_1_.nsas$v_privs_suppliedE#define nsas$l_privs_used nsas$r_privs_used_overlay.nsas$l_privs_usedE#define nsas$q_privs_used nsas$r_privs_used_overlay.nsas$q_privs_usedE#define nsas$q_object_class nsas$r_object_overlay.nsas$q_object_classA#define nsas$r_class_desc nsas$r_object_overlay.nsas$r_class_descA#define nsas$w_class_length nsas$r_class_desc.nsas$w_class_length=#define nsas$l_class_addr nsas$r_class_desc.nsas$l_class_addr"#endif /* #if !define?d(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NSASDEF_LOADED */ ww`ێ[UM/***************************************************************************/M/** ? **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M?/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************?**************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */F/* Source: 22-APR-1993 13:34:38 $1$DGA8345:[LIB_H.SRC]NTEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $NTEDEF ***/#ifndef __NTEDEF_LOADED ?#define __NTEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __un?known_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* NOTIFICATION TABLE ENTRY DEFINITIONS ? */N/* */O/* NOTIFICATION TABLE ENTRIES ARE USED BY THE NOTIFICATION MODULE ROUTINES. */N/* EACH ENTRY STORES THE INFORMATION NEEDED FOR A SINGLE NOTIFICATION. THE */Q/* SYSTEM MAINTAINS TWO TABLES OF SUCH ENTRIES, ONE EACH FOR JOIN NOTIFICATION */N/* AND REMOVAL NOTIFICATION. */N/* ? */N/*- */N#define NTE$K_LENGTH 12 /* LENGTH OF AN ENTRY */N#define NTE$C_LENGTH 12 /* LENGTH OF AN ENTRY */#define NTE$S_NTEDEF 12 typedef struct _nte { __union { __union {/ unsigned int nte$l_notifn_list_hdr; __struct {h unsigned short int nte$w_notifnefl; /* INDEX OF FIRST NOTIFICATION ENT ?RY ON THE TABLE */V unsigned short int nte$w_noofent; /* NUMBER OF ENTRIES IN THE TABLE */ } nte$r_fill_1_; } nte$r_fill_0_; __union {) unsigned int nte$l_notifn_id; __struct {W unsigned short int nte$w_link; /* LINK TO THE NEXT ENTRY ON THE LIST */S unsigned short int nte$w_seqno; /* SEQUENCE NUMBER OF THIS ENTRY */ } nte$r_fill_3_; } nte$r_fill_2_;$ ? } nte$r_notifn_list_overlay; __union {b int (*nte$l_routine_address)(); /* ADDRESS OF ROUTINE TO BE CALLED DURING NOTIFICATION */ __union {- unsigned int nte$l_free_list_hdr; __struct {] unsigned short int nte$w_freefl; /* INDEX OF FIRST FREE ENTRY ON THE TABLE */' short int nte$w_fill_1; } nte$r_fill_5_; } nte$r_fill_4_;" } nte$r_free_list_overlay; __union {T ?unsigned int nte$l_notifn_param; /* PARAMETER TO BE PASSED TO THE ROUTINE */ __union {) unsigned int nte$l_type_defn; __struct {N unsigned short int nte$w_size; /* SIZE OF THE TABLE */N unsigned char nte$b_type; /* TYPE OF THE DATA STRUCTURE */P unsigned char nte$b_subtype; /* SUBTYPE OF THE DATA STRUCTURE */ } nte$r_fill_7_; } nte$r_fill_6_;% } nte$r_notifn_param_ove ?rlay; } NTE; #if !defined(__VAXC)[#define nte$l_notifn_list_hdr nte$r_notifn_list_overlay.nte$r_fill_0_.nte$l_notifn_list_hdr]#define nte$w_notifnefl nte$r_notifn_list_overlay.nte$r_fill_0_.nte$r_fill_1_.nte$w_notifneflY#define nte$w_noofent nte$r_notifn_list_overlay.nte$r_fill_0_.nte$r_fill_1_.nte$w_noofentO#define nte$l_notifn_id nte$r_notifn_list_overlay.nte$r_fill_2_.nte$l_notifn_idS#define nte$w_link nte$r_notifn_list_overlay.nte$r_fill_2_.nte$r_fill_3_.nte$w_linkU#define nt?e$w_seqno nte$r_notifn_list_overlay.nte$r_fill_2_.nte$r_fill_3_.nte$w_seqnoK#define nte$l_routine_address nte$r_free_list_overlay.nte$l_routine_addressU#define nte$l_free_list_hdr nte$r_free_list_overlay.nte$r_fill_4_.nte$l_free_list_hdrU#define nte$w_freefl nte$r_free_list_overlay.nte$r_fill_4_.nte$r_fill_5_.nte$w_freeflH#define nte$l_notifn_param nte$r_notifn_param_overlay.nte$l_notifn_paramP#define nte$l_type_defn nte$r_notifn_param_overlay.nte$r_fill_6_.nte$l_type_defnT#define nte$w_size ? nte$r_notifn_param_overlay.nte$r_fill_6_.nte$r_fill_7_.nte$w_sizeT#define nte$b_type nte$r_notifn_param_overlay.nte$r_fill_6_.nte$r_fill_7_.nte$b_typeZ#define nte$b_subtype nte$r_notifn_param_overlay.nte$r_fill_6_.nte$r_fill_7_.nte$b_subtype"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr siz?e */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __NTEDEF_LOADED */ ww)[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to ?anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M?/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 ? */F/* Source: 26-JUL-2000 12:42:51 $1$DGA8345:[LIB_H.SRC]OCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $OCBDEF ***/#ifndef __OCBDEF_LOADED#define __OCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragma ?s supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#end!?if#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* OCB - Object Class Block */N/* */N/* This structures contains information about a security Object */N/* Class Block. "? */N/* */N/*- */ #define OCB$M_ACC_BITS_ALLOC 0x1 #define OCB$M_IMP_GRP_NAMING 0x2#define OCB$M_CREATE 0x4#define OCB$M_DEACCESS 0x8#define OCB$M_DELETE 0x10N#define OCB$K_LENGTH 203 /* Length of structure */N#define OCB$S_OCBDEF 203 /* Old size name - synonym */ #? 9#ifdef __cplusplus /* Define structure prototypes */ struct _ocb; #endif /* #ifdef __cplusplus */ typedef struct _ocb$r_ocb {N struct _ocb *ocb$l_flink; /* Forward link */N struct _ocb *ocb$l_blink; /* Backward link */N unsigned short int ocb$w_size; /* Allocation size */N unsigned char ocb$b_type; /* Structure type */N unsigned char ocb$b_subtype; $? /* Subtype */N __int64 ocb$q_reserved; /* TYPE/SUBTYPE longwords from X-1 */ __union {N unsigned int ocb$l_flags; /* Processing flags */ __struct {N unsigned ocb$v_acc_bits_alloc : 1; /* Bitname XLATE allocated */N unsigned ocb$v_imp_grp_naming : 1; /* Implicit group namespace */U unsigned ocb$v_create : 1; /* Object class supports creation auditing */V unsign%?ed ocb$v_deaccess : 1; /* Object class supports deaccess auditing */_ unsigned ocb$v_delete : 1; /* Object class supports deletion auditing (devices) */' unsigned ocb$v_fill_0_ : 3; } ocb$r_flags_bits; } ocb$r_flags_overlay;N unsigned int ocb$l_object_type; /* Object type value */N unsigned int ocb$l_class_orb; /* Class rights block */N unsigned int ocb$l_default_orb; /* Default rights block &? */N void *ocb$l_access_bitnames; /* Ptr to access bitnames */N int (*ocb$l_support_rtns)(); /* Ptr to support rtns dispatch */N void *ocb$ar_acc_audits; /* Ptr to access audits */N void *ocb$ar_acc_alarms; /* Ptr to access alarms */N unsigned int ocb$l_access_modes; /* Mask of valid access modes */N unsigned int ocb$l_resv_2; /* Reserved for future use */N unsigned int'? ocb$l_acc_bitname_size; /* Size of pool for bitname table */O unsigned int ocb$l_acc_bitname_length; /* Length of access bitname table */N/* */N char ocb$t_access_audits [48]; /* Access audits */N char ocb$t_access_alarms [48]; /* Access alarms */N/* */N unsigned int ocb$l_name_length; (?/* Length of class name */N unsigned int ocb$l_resv_6; /* to quadword */N void *ocb$ar_class_prot_alarms; /* Ptr to class alarms */N void *ocb$ar_class_prot_audits; /* Ptr to class audits */N char ocb$t_name [23]; /* Class name string */ } OCB$R_OCB; #if !defined(__VAXC)3#define ocb$l_flags ocb$r_flags_overlay.ocb$l_flagsV#define ocb$v_acc_bits_alloc ocb$r_flags_overlay )?.ocb$r_flags_bits.ocb$v_acc_bits_allocV#define ocb$v_imp_grp_naming ocb$r_flags_overlay.ocb$r_flags_bits.ocb$v_imp_grp_namingF#define ocb$v_create ocb$r_flags_overlay.ocb$r_flags_bits.ocb$v_createJ#define ocb$v_deaccess ocb$r_flags_overlay.ocb$r_flags_bits.ocb$v_deaccessF#define ocb$v_delete ocb$r_flags_overlay.ocb$r_flags_bits.ocb$v_delete"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas suppor*?ted */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __OCBDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard +?Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., a,?nd is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************************************** -?*********************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */G/* Source: 18-MAY-1993 16:19:43 $1$DGA8345:[LIB_H.SRC]OLCKDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $OLCKDEF ***/#ifndef __OLCKDEF_LOADED#define __OLCKDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment _.?_save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifnde/?f __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* OLCK - ORB LOCK */N/* */N/* This structures c0?ontains information about an outstanding LOCK */N/* on the Object Rights Block of a specific resourse. It is */N/* maintained in a per process database (CTL$GQ_ORB_LOCKDB) used */N/* to control ACL modifications through $CHANGE_ACL. */N/* */N/*- */#define OLCK$M_RESV_1 0x1N#define OLCK$K_FIX 1?ED_LEN 30 /* Fixed length */N#define OLCK$K_MAX_RSN 33 /* Maximum resource name */N#define OLCK$S_OLCKDEF 30 /* Old size name - synonym */ typedef struct _olck {N void *olck$l_flink; /* Forward link */N void *olck$l_blink; /* Backward link */N unsigned short int olck$w_size; /* Allocation size */N unsigned cha 2?r olck$b_type; /* Structure type */N unsigned char olck$b_stype; /* Subtype */N unsigned int olck$l_lockid; /* Lockid */N unsigned char olck$b_prv_lkmode; /* Previous lock mode */N unsigned char olck$b_cur_lkmode; /* Current lock mode */ __union {N unsigned short int olck$w_flags; /* Processing flags */ __struct {N 3? unsigned olck$v_resv_1 : 1; /* reserved for future */( unsigned olck$v_fill_0_ : 7; } olck$r_flags_bits; } olck$r_flags_overlay;N unsigned int olck$l_resv_1; /* Reserved */N unsigned int olck$l_resv_2; /* for future use */N unsigned short int olck$w_rsn_size; /* Size of resource name */#if defined(__VAXC) char olck$t_rsn[];#elseQ/* Warning: empty char[] m 4?ember for olck$t_rsn at end of structure not created */"#endif /* #if defined(__VAXC) */ } OLCK; #if !defined(__VAXC)6#define olck$w_flags olck$r_flags_overlay.olck$w_flagsJ#define olck$v_resv_1 olck$r_flags_overlay.olck$r_flags_bits.olck$v_resv_1"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defi5?ned required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __OLCKDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, dupli6?cated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyo7?ne without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 8? by OpenVMS SDL V3.7 */F/* Source: 17-MAR-1995 07:57:43 $1$DGA8345:[LIB_H.SRC]ORBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $ORBDEF ***/#ifndef __ORBDEF_LOADED#define __ORBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined wh9?enever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct:? variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Object's Rights Block - structure defining the protection information */N/* for various objects within the system. */N/* ;? */N/*- */#define ORB$M_PROT_16 0x1#define ORB$M_ACL_QUEUE 0x2#define ORB$M_MODE_VECTOR 0x4#define ORB$M_NOACL 0x8#define ORB$M_CLASS_PROT 0x10#define ORB$M_NOAUDIT 0x20#define ORB$M_MODE_VALID 0x80"#define ORB$M_PROFILE_LOCKED 0x100 #define ORB$M_INDIRECT_ACL 0x200#define ORB$M_BOOTTIME 0x400#define ORB$M_UNMODIFIED 0x800#define ORB$M_DAMAGED 0x1000 ?nt orb$l_acl_mutex; /* Mutex for this ACL */N unsigned short int orb$w_size; /* Size of the ORB in bytes */N unsigned char orb$b_type; /* Structure type */N unsigned char orb$b_subtype; /* Subtype of ORB block: */N/* 0 - normal ORB */N/* 1 - block used to contain a name (only) */ __union { __union {N ?? unsigned short int orb$w_flags; /* System protection field */ __struct {N unsigned char orb$b_flags_1; /* first byte of flags */N unsigned char orb$b_flags_2; /* second byte of flags */ } orb$r_fill_3_; } orb$r_fill_2_;N unsigned char orb$b_flags; /* first byte of flags */ __union {/ unsigned short int orb$w_flag_bits; __struct {P @? unsigned orb$v_prot_16 : 1; /* Use word not vector protection */Q unsigned orb$v_acl_queue : 1; /* (*temp*) remove at later time */Y unsigned orb$v_mode_vector : 1; /* Use vector not byte mode protection */N unsigned orb$v_noacl : 1; /* Object cannot have an ACL */U unsigned orb$v_class_prot : 1; /* Security classification is valid */Q unsigned orb$v_noaudit : 1; /* Do not perform $CHKPRO auditing */NA? unsigned orb$v_reserved_1 : 1; /* */T unsigned orb$v_mode_valid : 1; /* Access mode protection is valid */_ unsigned orb$v_profile_locked : 1; /* Object locked, no modification allowed */N/* The PROFILE_LOCKED flag is intended to be set when the profile cannot */O/* reasonably be modified. I.e., the protection of a volume set may only be */R/* altered if the root volume of the set is mounted, though mounting a selected B?*/N/* volume from a volume set is supported. */T unsigned orb$v_indirect_acl : 1; /* Use the ACL from the template */N/* ORB (ORB$L_TEMPLATE) */\ unsigned orb$v_boottime : 1; /* ORB created prior to securty object init. */Y unsigned orb$v_unmodified : 1; /* ORB has not been explicitly modified */X unsigned orb$v_damaged : 1; /* Deny access to all but C?system (BADACL) */N unsigned orb$v_template : 1; /* This orb is a template */Q unsigned orb$v_transition : 1; /* Profile content uncertain -- */N/* eg. cluster instantiation */c unsigned orb$v_ext_nameblock : 1; /* ORB name is store in a separate 'ORB' block */ } orb$r_fill_5_; } orb$r_fill_4_; } orb$r_flags_overlay;N/* D? */N unsigned short int orb$w_refcount; /* Reference count */ __union { __union {N unsigned __int64 orb$q_mode_prot; /* Mode protection vector */ __struct {N unsigned int orb$l_mode_protl; /* Low longword of vector */N unsigned int orb$l_mode_proth; /* High longword of vector */ } orb$r_fill_7_; } orb$r_fill_6_;N unsigned int orb E?$l_mode; /* Simple access mode */ } orb$r_mode_overlay; __union {N unsigned int orb$l_sys_prot; /* System protection field */N unsigned short int orb$w_prot; /* Standard SOGW protection */! } orb$r_sys_prot_overlay;N unsigned int orb$l_own_prot; /* Owner protection field */N unsigned int orb$l_grp_prot; /* Group protection field */N unsigned int orb$l_wor_prot; /* Wor F?ld protection field */ __union {N struct _ace *orb$l_aclfl; /* ACL queue forward link */N unsigned int orb$l_acl_count; /* Count of ACL segments */ } orb$r_acl_1_overlay; __union {N struct _ace *orb$l_aclbl; /* ACL queue backward link */T void *orb$l_acl_desc; /* Address of ACL segment descriptor list */ } orb$r_acl_2_overlay; __struct {N char orb$b_fill_2 [20]; G? /* Minimum classification mask */ } orb$r_min_class; __struct {N char orb$b_fill_3 [20]; /* Maximum classification mask */ } orb$r_max_class;N unsigned short int orb$w_name_length; /* Length of object name */N short int orb$w_fill_3; /* Unused (MBZ) */N void *orb$l_name_pointer; /* Pointer to object name */N struct _ocb *orb$l_ocb; /* Pointer to Object ClaH?ss Block */N struct _orb *orb$l_template_orb; /* Pointer to template ORB */N int orb$l_object_specific; /* Object class specific usage cell */N struct _orb *orb$l_original_orb; /* Pointer to another ORB */N unsigned int orb$l_updseq; /* Update sequence number */N void *orb$l_mutex_address; /* Address of mutex for CHKPRO */N int orb$l_reserve2; /* for future use */N char o I?rb$t_object_name; /* Start of object name */ } ORB; #if !defined(__VAXC)-#define orb$l_owner orb$r_fill_0_.orb$l_ownerC#define orb$w_uicmember orb$r_fill_0_.orb$r_fill_1_.orb$w_uicmemberA#define orb$w_uicgroup orb$r_fill_0_.orb$r_fill_1_.orb$w_uicgroupA#define orb$w_flags orb$r_flags_overlay.orb$r_fill_2_.orb$w_flagsS#define orb$b_flags_1 orb$r_flags_overlay.orb$r_fill_2_.orb$r_fill_3_.orb$b_flags_1S#define orb$b_flags_2 orb$r_flags_overlay.orb$r_fill_2_.orJ?b$r_fill_3_.orb$b_flags_23#define orb$b_flags orb$r_flags_overlay.orb$b_flagsS#define orb$v_prot_16 orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_prot_16W#define orb$v_acl_queue orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_acl_queue[#define orb$v_mode_vector orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_mode_vectorO#define orb$v_noacl orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_noaclY#define orb$v_class_prot orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_K?.orb$v_class_protS#define orb$v_noaudit orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_noauditY#define orb$v_mode_valid orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_mode_valida#define orb$v_profile_locked orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_profile_locked]#define orb$v_indirect_acl orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_indirect_aclU#define orb$v_boottime orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_boottimeY#define orb$v_unmodifiedL? orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_unmodifiedS#define orb$v_damaged orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_damagedU#define orb$v_template orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_templateY#define orb$v_transition orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_transition_#define orb$v_ext_nameblock orb$r_flags_overlay.orb$r_fill_4_.orb$r_fill_5_.orb$v_ext_nameblockH#define orb$q_mode_prot orb$r_mode_overlay.orb$r_fill_6_.orb$q_mode_protXM?#define orb$l_mode_protl orb$r_mode_overlay.orb$r_fill_6_.orb$r_fill_7_.orb$l_mode_protlX#define orb$l_mode_proth orb$r_mode_overlay.orb$r_fill_6_.orb$r_fill_7_.orb$l_mode_proth0#define orb$l_mode orb$r_mode_overlay.orb$l_mode<#define orb$l_sys_prot orb$r_sys_prot_overlay.orb$l_sys_prot4#define orb$w_prot orb$r_sys_prot_overlay.orb$w_prot3#define orb$l_aclfl orb$r_acl_1_overlay.orb$l_aclfl;#define orb$l_acl_count orb$r_acl_1_overlay.orb$l_acl_count3#define orb$l_aclbl orb$r_acl_2_overlay.orb$N?l_aclbl9#define orb$l_acl_desc orb$r_acl_2_overlay.orb$l_acl_desc"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __ORBDEF_LOADED */ ww[UM/*******************************************O?********************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP P? **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** Q? **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */F/* Source: 18-MAY-1993 16:26:10 $1$DGA8345:[LIB_H.SRC]OSRDEF.SDL;1 *//********************************************************************************************* R?***********************************//*** MODULE $OSRDEF ***/#ifndef __OSRDEF_LOADED#define __OSRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size defaS?ult to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ T? */N/* Object Support Routine flag definitions. */N/* */N/* This structure contains the flag definitions that are used */N/* to control processing between the security object management */N/* services and the Object Support Routines. These are internal */N/* flags used within the services and should not be used in thU?e */N/* system service interfaces. */N/*- */ #define OSR$M_ACCESS_CHECKED 0x1#define OSR$M_MOD_MAC 0x2#define OSR$M_NO_LOCK_RSN 0x4#define OSR$M_RUNDOWN 0x8#define OSR$M_WRITE 0x10#define OSR$M_MOD_ORB 0x20#define OSR$M_MOD_ACL 0x40#define OSR$M_MOD_FOR 0x80!#define OSR$M_KERNEL_SETITM 0x100(#define OSR$M_KERNEL_CLONE_PROFILE 0x200)#define OSR$M_KERNV?EL_UPDATE_PROFILE 0x400"#define OSR$M_KERNEL_RUNDOWN 0x800(#define OSR$M_KERNEL_CHECK_ACCESS 0x1000'#define OSR$M_KERNEL_TRANQUILITY 0x2000,#define OSR$M_KERNEL_FIXUP_BTIME_ORBS 0x4000#define OSR$M_RELCTX 0x8000!#define OSR$M_SELECT_NAME 0x10000##define OSR$M_SELECT_HANDLE 0x20000"#define OSR$M_EMBED_OBJNAM 0x40000$#define OSR$M_CLUSTER_OBJECT 0x80000##define OSR$M_CONTEXT_NAME 0x100000%#define OSR$M_CLUSTER_NOTIFY 0x200000 #define OSR$M_TEMPORARY 0x400000 #define OSR$M_PERMANENT W?0x800000"#define OSR$M_NEW_OBJECT 0x1000000!#define OSR$M_NO_CREATE 0x2000000"#define OSR$M_NO_MAC_DAC 0x4000000$#define OSR$M_NO_MAC_AUDIT 0x8000000%#define OSR$M_MO_MAC_RANGE 0x10000000#define OSR$M_NO_MAC 0x20000000N#define OSR$S_OSRDEF 4 /* Old size name - synonym */ typedef struct _osr { __struct {N unsigned osr$v_access_checked : 1; /* Bypass chkpro in $xETSOI */N unsigned osr$v_mod_mac : 1; /* Secrecy/integrity hanged X? */Y unsigned osr$v_no_lock_rsn : 1; /* No need to build lock rsn in preprocess OSR */T unsigned osr$v_rundown : 1; /* Rundown OSR call required for $xETSOI */N unsigned osr$v_write : 1; /* Write operation $SETSOI */N unsigned osr$v_mod_orb : 1; /* ORB (proper) was modified */N unsigned osr$v_mod_acl : 1; /* ORB ACL was modified */N unsigned osr$v_mod_for : 1; /* Foreign char was modified */Y?X unsigned osr$v_kernel_setitm : 1; /* Process set itmlist processing in k_mode */W unsigned osr$v_kernel_clone_profile : 1; /* Call clone_profile OSR in k_mode */Y unsigned osr$v_kernel_update_profile : 1; /* Call update_profile OSR in k_mode */N unsigned osr$v_kernel_rundown : 1; /* Call rundown OSR in k_mode */U unsigned osr$v_kernel_check_access : 1; /* Call check_access OSR in k_mode */W unsigned osr$v_kernel_tranquility : 1; /* Call set/clearZ? trauility in K-mode */] unsigned osr$v_kernel_fixup_btime_orbs : 1; /* Call fixup_btime_orbs OSR in k_mode */N unsigned osr$v_relctx : 1; /* Release OSR context */N unsigned osr$v_select_name : 1; /* Select object by name */N unsigned osr$v_select_handle : 1; /* Select object by handle */N unsigned osr$v_embed_objnam : 1; /* Embed object name in ORB */N unsigned osr$v_cluster_object : 1; /* Cluster visible ob[?ject */N unsigned osr$v_context_name : 1; /* Use object name from context */N/* for cluster distribution */N unsigned osr$v_cluster_notify : 1; /* Cluster notification */N/* (for volumes) */N unsigned osr$v_temporary : 1; /* Temporary object */N/* eg. foreign monted disk */N un\?signed osr$v_permanent : 1; /* Not temporary */N unsigned osr$v_new_object : 1; /* Any existing profile is stale */N unsigned osr$v_no_create : 1; /* Don't create a new profile. */N unsigned osr$v_no_mac_dac : 1; /* Concurrent MAC/DAC modifications */N/* not supported */P unsigned osr$v_no_mac_audit : 1; /* Suppress $SET_SECURITY MAC audits */N unsigned osr$v_mo_mac_rang ]?e : 1; /* MAC range not supported */N unsigned osr$v_no_mac : 1; /* MAC modifications not supported */# unsigned osr$v_fill_0_ : 2; } osr$r_flag_bits; } OSR; #if !defined(__VAXC)A#define osr$v_access_checked osr$r_flag_bits.osr$v_access_checked3#define osr$v_mod_mac osr$r_flag_bits.osr$v_mod_mac;#define osr$v_no_lock_rsn osr$r_flag_bits.osr$v_no_lock_rsn3#define osr$v_rundown osr$r_flag_bits.osr$v_rundown/#define osr$v_write osr$r_flag_bits.os ^?r$v_write3#define osr$v_mod_orb osr$r_flag_bits.osr$v_mod_orb3#define osr$v_mod_acl osr$r_flag_bits.osr$v_mod_acl3#define osr$v_mod_for osr$r_flag_bits.osr$v_mod_for?#define osr$v_kernel_setitm osr$r_flag_bits.osr$v_kernel_setitmM#define osr$v_kernel_clone_profile osr$r_flag_bits.osr$v_kernel_clone_profileO#define osr$v_kernel_update_profile osr$r_flag_bits.osr$v_kernel_update_profileA#define osr$v_kernel_rundown osr$r_flag_bits.osr$v_kernel_rundownK#define osr$v_kernel_check_access os_?r$r_flag_bits.osr$v_kernel_check_accessI#define osr$v_kernel_tranquility osr$r_flag_bits.osr$v_kernel_tranquilityS#define osr$v_kernel_fixup_btime_orbs osr$r_flag_bits.osr$v_kernel_fixup_btime_orbs1#define osr$v_relctx osr$r_flag_bits.osr$v_relctx;#define osr$v_select_name osr$r_flag_bits.osr$v_select_name?#define osr$v_select_handle osr$r_flag_bits.osr$v_select_handle=#define osr$v_embed_objnam osr$r_flag_bits.osr$v_embed_objnamA#define osr$v_cluster_object osr$r_flag_bits.osr$v_cluster `?_object=#define osr$v_context_name osr$r_flag_bits.osr$v_context_nameA#define osr$v_cluster_notify osr$r_flag_bits.osr$v_cluster_notify7#define osr$v_temporary osr$r_flag_bits.osr$v_temporary7#define osr$v_permanent osr$r_flag_bits.osr$v_permanent9#define osr$v_new_object osr$r_flag_bits.osr$v_new_object7#define osr$v_no_create osr$r_flag_bits.osr$v_no_create9#define osr$v_no_mac_dac osr$r_flag_bits.osr$v_no_mac_dac=#define osr$v_no_mac_audit osr$r_flag_bits.osr$v_no_mac_audit=#defin a?e osr$v_mo_mac_range osr$r_flag_bits.osr$v_mo_mac_range1#define osr$v_no_mac osr$r_flag_bits.osr$v_no_mac"#endif /* #if !defined(__VAXC) */ N/*+ */N/* The OSR context area is an overlay of the UNC$S/T_OSR_CONTEXT area */N/* in the universal context area structure ($UNCDEF). If the size of */N/* this area is larger then UNC$S_OSR_CONTEXT, you must enlarge the */N/* universal context area defintion b?. There are ASSUMEs in the ROUTINES */N/* that allocate the context structure. */N/*- */#define OSRCTX$M_CLS_INIT 0x1#define OSRCTX$M_CLS_TMPNAM 0x2#define OSRCTX$M_LNT_INIT 0x1$#define OSRCTX$M_LNT_ACCESS_QUAL 0x2#define OSRCTX$M_DEV_CHAN 0x1!#define OSRCTX$M_DEV_TEMPLATE 0x2#define OSRCTX$M_DEV_ALL 0x4!#define OSRCTX$M_FIL_DEACCESS 0x1!#define OSRCTX$M_VOL_DEACCESS 0xc?1N#define OSRCTX$S_OSR_CTXDEF 16 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ocb; struct _orb; #endif /* #ifdef __cplusplus */ typedef struct _osr_ctx { __union { __struct {N struct _ocb *osrctx$l_cls_ocb; /* Original OCB */ __union {N int osrctx$l_cls_flags; /* Processing flags */ __struct {N d? unsigned osrctx$v_cls_init : 1; /* Initialized */N unsigned osrctx$v_cls_tmpnam : 1; /* Template present */3 unsigned osrctx$v_fill_11_ : 6;' } osrctx$r_fill_2_;# } osrctx$r_fill_1_;O unsigned int osrctx$l_cls_tmpnam_length; /* Template name length */N unsigned int osrctx$l_cls_tmpnam; /* Template name */# } osrctx$r_cls_context; __struct { e? __union {N int osrctx$l_lnt_flags; /* Processing flags */ __struct {N unsigned osrctx$v_lnt_init : 1; /* Initialized */Y unsigned osrctx$v_lnt_access_qual : 1; /* Access qualifier present */3 unsigned osrctx$v_fill_12_ : 6;' } osrctx$r_fill_4_;# } osrctx$r_fill_3_;N unsigned char osrctx$b_lnt_access_mode; /* Access mo f?de */N unsigned char osrctx$b_lnt_resv_1; /* Reserved for future */\ unsigned short int osrctx$w_lnt_objnam_len; /* LNT name (without access mode) */N unsigned int osrctx$l_lnt_resv_2; /* Reserved for future */N unsigned int osrctx$l_lnt_resv_3; /* Reserved for future */# } osrctx$r_lnt_context; __struct {N unsigned int osrctx$l_cef_resv_1; /* Reserved */N unsig?gned int osrctx$l_cef_resv_2; /* */N unsigned int osrctx$l_cef_resv_3; /* for */N unsigned short int osrctx$w_cef_resv_4; /* */N unsigned short int osrctx$w_cef_resv_5; /* future use */# } osrctx$r_cef_context; __struct {N struct _orb *osrctx$l_dev_orb; /* Active device ORB */N unsigned int osrctx$l_dev_resv_2; /* h? */N unsigned int osrctx$l_dev_resv_3; /* */N unsigned short int osrctx$w_dev_chan; /* channel # */ __union {N short int osrctx$w_dev_flags; /* processing flags */ __struct {R unsigned osrctx$v_dev_chan : 1; /* channel assigned by OSRs */Z unsigned osrctx$v_dev_template : 1; /* dealing with template device */Q i? unsigned osrctx$v_dev_all : 1; /* devcie allocated by OSRs */3 unsigned osrctx$v_fill_13_ : 5;' } osrctx$r_fill_6_;# } osrctx$r_fill_5_;# } osrctx$r_dev_context; __struct {N unsigned int osrctx$l_fil_resv_1; /* Reserved */N unsigned int osrctx$l_fil_resv_2; /* for */N unsigned int osrctx$l_fil_resv_3; /* future use */N j? unsigned short int osrctx$w_fil_channel; /* */ __union {N short int osrctx$w_fil_flags; /* File context flags */ __struct {Z unsigned osrctx$v_fil_deaccess : 1; /* Deaccess file at OSR rundown */3 unsigned osrctx$v_fill_14_ : 7;' } osrctx$r_fill_8_;# } osrctx$r_fill_7_;# } osrctx$r_fil_context; __struct {N k?unsigned int osrctx$l_que_resv_1; /* Reserved */N unsigned int osrctx$l_que_resv_2; /* */N unsigned int osrctx$l_que_resv_3; /* for */N unsigned short int osrctx$w_que_resv_4; /* */N unsigned short int osrctx$w_que_resv_5; /* future use */# } osrctx$r_que_context; __struct {N unsigned int osrctx$l_prc_resv_1; /* Reserved l? */N unsigned int osrctx$l_prc_resv_2; /* */N unsigned int osrctx$l_prc_resv_3; /* for */N unsigned short int osrctx$w_prc_resv_4; /* */N unsigned short int osrctx$w_prc_resv_5; /* future use */# } osrctx$r_prc_context; __struct {N unsigned int osrctx$l_sec_tranq_cnt; /* Tranquility count (MAC) */N unsigned intm? osrctx$l_sec_resv_2; /* Reserved */N unsigned int osrctx$l_sec_resv_3; /* for */N unsigned short int osrctx$w_sec_resv_4; /* */N unsigned short int osrctx$w_sec_resv_5; /* future use */# } osrctx$r_sec_context; __struct {N unsigned int osrctx$l_vol_resv_1; /* Reserved */N unsigned int osrctx$l_vol_resv_2; /* for n? */N unsigned int osrctx$l_vol_resv_3; /* future use */N unsigned short int osrctx$w_vol_channel; /* */ __union {N short int osrctx$w_vol_flags; /* Volume context flags */ __struct {] unsigned osrctx$v_vol_deaccess : 1; /* Deassign channel at OSR rundown */3 unsigned osrctx$v_fill_15_ : 7;( } osrctx$r_fill_10_;# o? } osrctx$r_fill_9_;# } osrctx$r_vol_context; __struct {N unsigned int osrctx$l_rsdm_domain; /* Domain number */N unsigned int osrctx$l_rsdm_lockid; /* Tranquility lock id (MAC) */N unsigned int osrctx$l_rsdm_resv_3; /* Reserved */N unsigned short int osrctx$w_rsdm_resv_4; /* for */N unsigned short int osrctx$w_rsdm_resv_5; /* future use */$ } osrc p?tx$r_rsdm_context;" } osrctx$r_object_overlay; } OSR_CTX; #if !defined(__VAXC)V#define osrctx$l_cls_ocb osrctx$r_object_overlay.osrctx$r_cls_context.osrctx$l_cls_ocbk#define osrctx$l_cls_flags osrctx$r_object_overlay.osrctx$r_cls_context.osrctx$r_fill_1_.osrctx$l_cls_flagsz#define osrctx$v_cls_init osrctx$r_object_overlay.osrctx$r_cls_context.osrctx$r_fill_1_.osrctx$r_fill_2_.osrctx$v_cls_init~#define osrctx$v_cls_tmpnam osrctx$r_object_overlay.osrctx$r_cls_context.osrctx$r_fillq?_1_.osrctx$r_fill_2_.osrctx$v_cls_tmpnamj#define osrctx$l_cls_tmpnam_length osrctx$r_object_overlay.osrctx$r_cls_context.osrctx$l_cls_tmpnam_length\#define osrctx$l_cls_tmpnam osrctx$r_object_overlay.osrctx$r_cls_context.osrctx$l_cls_tmpnamk#define osrctx$l_lnt_flags osrctx$r_object_overlay.osrctx$r_lnt_context.osrctx$r_fill_3_.osrctx$l_lnt_flagsz#define osrctx$v_lnt_init osrctx$r_object_overlay.osrctx$r_lnt_context.osrctx$r_fill_3_.osrctx$r_fill_4_.osrctx$v_lnt_init#define osrctx$v_lnt_access_r?qual osrctx$r_object_overlay.osrctx$r_lnt_context.osrctx$r_fill_3_.osrctx$r_fill_4_.osrctx$v_lnt_access\_qualf#define osrctx$b_lnt_access_mode osrctx$r_object_overlay.osrctx$r_lnt_context.osrctx$b_lnt_access_mode\#define osrctx$b_lnt_resv_1 osrctx$r_object_overlay.osrctx$r_lnt_context.osrctx$b_lnt_resv_1d#define osrctx$w_lnt_objnam_len osrctx$r_object_overlay.osrctx$r_lnt_context.osrctx$w_lnt_objnam_len\#define osrctx$l_lnt_resv_2 osrctx$r_object_overlay.osrctx$r_lnt_context.osrctx$l_lnt_resv_2s?\#define osrctx$l_lnt_resv_3 osrctx$r_object_overlay.osrctx$r_lnt_context.osrctx$l_lnt_resv_3\#define osrctx$l_cef_resv_1 osrctx$r_object_overlay.osrctx$r_cef_context.osrctx$l_cef_resv_1\#define osrctx$l_cef_resv_2 osrctx$r_object_overlay.osrctx$r_cef_context.osrctx$l_cef_resv_2\#define osrctx$l_cef_resv_3 osrctx$r_object_overlay.osrctx$r_cef_context.osrctx$l_cef_resv_3\#define osrctx$w_cef_resv_4 osrctx$r_object_overlay.osrctx$r_cef_context.osrctx$w_cef_resv_4\#define osrctx$w_cef_resv_5 osrctxt?$r_object_overlay.osrctx$r_cef_context.osrctx$w_cef_resv_5V#define osrctx$l_dev_orb osrctx$r_object_overlay.osrctx$r_dev_context.osrctx$l_dev_orb\#define osrctx$l_dev_resv_2 osrctx$r_object_overlay.osrctx$r_dev_context.osrctx$l_dev_resv_2\#define osrctx$l_dev_resv_3 osrctx$r_object_overlay.osrctx$r_dev_context.osrctx$l_dev_resv_3X#define osrctx$w_dev_chan osrctx$r_object_overlay.osrctx$r_dev_context.osrctx$w_dev_chank#define osrctx$w_dev_flags osrctx$r_object_overlay.osrctx$r_dev_context.osrctx$ru?_fill_5_.osrctx$w_dev_flagsz#define osrctx$v_dev_chan osrctx$r_object_overlay.osrctx$r_dev_context.osrctx$r_fill_5_.osrctx$r_fill_6_.osrctx$v_dev_chan#define osrctx$v_dev_template osrctx$r_object_overlay.osrctx$r_dev_context.osrctx$r_fill_5_.osrctx$r_fill_6_.osrctx$v_dev_templatex#define osrctx$v_dev_all osrctx$r_object_overlay.osrctx$r_dev_context.osrctx$r_fill_5_.osrctx$r_fill_6_.osrctx$v_dev_all\#define osrctx$l_fil_resv_1 osrctx$r_object_overlay.osrctx$r_fil_context.osrctx$l_fil_resv_1\#defv?ine osrctx$l_fil_resv_2 osrctx$r_object_overlay.osrctx$r_fil_context.osrctx$l_fil_resv_2\#define osrctx$l_fil_resv_3 osrctx$r_object_overlay.osrctx$r_fil_context.osrctx$l_fil_resv_3^#define osrctx$w_fil_channel osrctx$r_object_overlay.osrctx$r_fil_context.osrctx$w_fil_channelk#define osrctx$w_fil_flags osrctx$r_object_overlay.osrctx$r_fil_context.osrctx$r_fill_7_.osrctx$w_fil_flags#define osrctx$v_fil_deaccess osrctx$r_object_overlay.osrctx$r_fil_context.osrctx$r_fill_7_.osrctx$r_fill_8_.osrctx$w?v_fil_deaccess\#define osrctx$l_que_resv_1 osrctx$r_object_overlay.osrctx$r_que_context.osrctx$l_que_resv_1\#define osrctx$l_que_resv_2 osrctx$r_object_overlay.osrctx$r_que_context.osrctx$l_que_resv_2\#define osrctx$l_que_resv_3 osrctx$r_object_overlay.osrctx$r_que_context.osrctx$l_que_resv_3\#define osrctx$w_que_resv_4 osrctx$r_object_overlay.osrctx$r_que_context.osrctx$w_que_resv_4\#define osrctx$w_que_resv_5 osrctx$r_object_overlay.osrctx$r_que_context.osrctx$w_que_resv_5\#define osrctx$l_prcx?_resv_1 osrctx$r_object_overlay.osrctx$r_prc_context.osrctx$l_prc_resv_1\#define osrctx$l_prc_resv_2 osrctx$r_object_overlay.osrctx$r_prc_context.osrctx$l_prc_resv_2\#define osrctx$l_prc_resv_3 osrctx$r_object_overlay.osrctx$r_prc_context.osrctx$l_prc_resv_3\#define osrctx$w_prc_resv_4 osrctx$r_object_overlay.osrctx$r_prc_context.osrctx$w_prc_resv_4\#define osrctx$w_prc_resv_5 osrctx$r_object_overlay.osrctx$r_prc_context.osrctx$w_prc_resv_5b#define osrctx$l_sec_tranq_cnt osrctx$r_object_overlay.oy?srctx$r_sec_context.osrctx$l_sec_tranq_cnt\#define osrctx$l_sec_resv_2 osrctx$r_object_overlay.osrctx$r_sec_context.osrctx$l_sec_resv_2\#define osrctx$l_sec_resv_3 osrctx$r_object_overlay.osrctx$r_sec_context.osrctx$l_sec_resv_3\#define osrctx$w_sec_resv_4 osrctx$r_object_overlay.osrctx$r_sec_context.osrctx$w_sec_resv_4\#define osrctx$w_sec_resv_5 osrctx$r_object_overlay.osrctx$r_sec_context.osrctx$w_sec_resv_5\#define osrctx$l_vol_resv_1 osrctx$r_object_overlay.osrctx$r_vol_context.osrctx$l_vol_z?resv_1\#define osrctx$l_vol_resv_2 osrctx$r_object_overlay.osrctx$r_vol_context.osrctx$l_vol_resv_2\#define osrctx$l_vol_resv_3 osrctx$r_object_overlay.osrctx$r_vol_context.osrctx$l_vol_resv_3^#define osrctx$w_vol_channel osrctx$r_object_overlay.osrctx$r_vol_context.osrctx$w_vol_channelk#define osrctx$w_vol_flags osrctx$r_object_overlay.osrctx$r_vol_context.osrctx$r_fill_9_.osrctx$w_vol_flags#define osrctx$v_vol_deaccess osrctx$r_object_overlay.osrctx$r_vol_context.osrctx$r_fill_9_.osrctx$r_fil{?l_10_.osrctx$v_vol_deaccess_#define osrctx$l_rsdm_domain osrctx$r_object_overlay.osrctx$r_rsdm_context.osrctx$l_rsdm_domain_#define osrctx$l_rsdm_lockid osrctx$r_object_overlay.osrctx$r_rsdm_context.osrctx$l_rsdm_lockid_#define osrctx$l_rsdm_resv_3 osrctx$r_object_overlay.osrctx$r_rsdm_context.osrctx$l_rsdm_resv_3_#define osrctx$w_rsdm_resv_4 osrctx$r_object_overlay.osrctx$r_rsdm_context.osrctx$w_rsdm_resv_4_#define osrctx$w_rsdm_resv_5 osrctx$r_object_overlay.osrctx$r_rsdm_context.osrctx$w_|?rsdm_resv_5"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __OSRDEF_LOADED */ wwb[UM/***************************************************************************/M/** }? **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** ~? **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** ? **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */G/* Source: 12-DEC-1995 10:14:43 $1$DGA8345:[LIB_H.SRC]OSRVDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $OSR ?VDEF ***/#ifndef __OSRVDEF_LOADED#define __OSRVDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cpl?usplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* OSRV ?- Object Support Routine Vectors */N/* */N/* This structures contains information about the security Object */N/* Support Routine dispatch Vectors. It is through these dispatch */N/* vectors that the various security subsystem components callout */N/* to the object class specific functions. */N/*- ? */N#define OSRV$K_LENGTH 68 /* Size of the vectors */#define OSRV$S_OSRVDEF 68 typedef struct _osrv {N unsigned int osrv$l_access_exception; /* $CHKPRO access exception */N unsigned int osrv$l_clone_profile; /* Clone object profile */N unsigned int osrv$l_get_item; /* Get foreign item processing */N unsigned int osrv$l_preprocess; /* Preprocess (setup) */N ?unsigned int osrv$l_rundown; /* Postprocessing (cleanup) */N unsigned int osrv$l_set_item; /* Get foreign item processing */N unsigned int osrv$l_update_profile; /* Update the object profile */N unsigned int osrv$l_check_access; /* $CHECK_ACCESS routine */N unsigned int osrv$l_fixup_btime_orbs; /* Fixup any boot time ORBs */N unsigned int osrv$l_resolve_acl; /* Fixup ACL indirection */N unsigned int osrv$l_read_p?rofile; /* re-read profile from */N/* backing store (volume support) */N unsigned int osrv$l_set_tranquility; /* establish tranquility */N unsigned int osrv$l_clear_tranquility; /* relinquish tranquility */N unsigned int osrv$l_check_access_psb; /* */N unsigned int osrv$l_reserved_2; /* reserved */N unsigned int osrv$l_reserved_3; /* reserved ? */N unsigned int osrv$l_reserved_4; /* reserved */ } OSRV; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __OSRVDEF_LOADED */ ww [UM/*********************************?******************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development,? LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** ? **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */I/* Source: 19-APR-1993 14:45:38 $1$DGA8345:[LIB_H.SRC]OSSFLGDEF.SDL;1 *//******************************************************************************* ?*************************************************//*** MODULE $OSSFLGDEF ***/#ifndef __OSSFLGDEF_LOADED#define __OSSFLGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /*? And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ ? */N/* Security Object Information context flags definitions. */N/* */N/* This structure contains the flag definitions that are used */N/* in ctl$gl_oss_flags */N/* */N/*- ? */#define OSSFLG$M_RNDWN_DCLR 0x1#define OSSFLG$S_OSSFLGDEF 1 typedef struct _ossflg { __struct {N unsigned ossflg$v_rndwn_dclr : 1; /* Rundown handler declared */& unsigned ossflg$v_fill_0_ : 7; } ossflg$r_flags_bits; } OSSFLG; #if !defined(__VAXC)C#define ossflg$v_rndwn_dclr ossflg$r_flags_bits.ossflg$v_rndwn_dclr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef _?_INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __OSSFLGDEF_LOADED */ wwP%[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is c?onfidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential? **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********** ?*********************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */G/* Source: 25-JUN-2004 13:26:54 $1$DGA8345:[LIB_H.SRC]P1PLDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $P1PLDEF ***/#ifndef __P1PLDEF_LOADED#define __P1PLDEF_LOADED 1 G#pragma __nostandard /* Thi?s file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#def?ine __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* Process pool log entry */N/*- ? */ N#define P1PLE$K_LENGTH 32 /* Size of structure */N#define P1PLE$C_LENGTH 32 /* Size of structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _p1ple {#pragma __nomember_alignment$ unsigned __int64 p1ple$q_dea_pc;$ ? unsigned __int64 p1ple$q_alo_pc; unsigned int p1ple$l_size; unsigned int p1ple$l_va;" unsigned __int64 p1ple$q_time; } P1PLE;#define P1PL$M_MATCH 0x1#define P1PL$M_COMPRESS 0x2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _p1pl {#pragma __nomember_alignment unsigned int p1pl$l_size; unsigned int p1pl$ ?l_next;& unsigned __int64 p1pl$q_region_id; __union {" unsigned int p1pl$l_flags; __struct {\ unsigned p1pl$v_match : 1; /* Mark deallocation in matching allocation entry */m unsigned p1pl$v_compress : 1; /* Compress if log full: eliminate matched alloc/dealloc records */( unsigned p1pl$v_fill_0_ : 6; } p1pl$r_flags_bits; } p1pl$r_flags_overlay;' unsigned int p1pl$l_compress_count;& unsigned int p1pl$l_?dealloc_count;$ unsigned int p1pl$l_alloc_count;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN P1PLE p1pl$a_entry []; /* Beginn of log entries */ } P1PL; #if !defined(__VAXC)6#define p1pl$l_flags p1pl$r_flags_overlay.p1pl$l_flagsH#define p1pl$v_match p1pl$r_flags_overlay.p1pl$r_flags_bits.p1pl$v_matchN#define p1pl?$v_compress p1pl$r_flags_overlay.p1pl$r_flags_bits.p1pl$v_compress"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __P1PLDEF_LOADED */ ww`L[UM/*******************************************?********************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP ? **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** ? **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//******************************************************************************************* ?*************************************//*** MODULE $P2BDEF ***/#ifndef __P2BDEF_LOADED#define __P2BDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size de?fault to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ ? */N/* P2 buffer header definition */N/*-- */N#define P2B$C_LENGTH 12 /* Size of P2 buffer header */N#define P2B$T_DATA 12 /* Start of data */ typedef struct _p2bdef {N unsigned int p2b$l_pointr; /* Pointer to start of data */N unsigned int p2b$l_buffer; ? /* Address of user's data buffer */N unsigned short int p2b$w_size; /* Size of P2 buffer */N unsigned char p2b$b_type; /* Type of structure */N unsigned char p2b$b_spare; /* Spare byte */ } P2BDEF; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defi?ned required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __P2BDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplica?ted OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone? without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 b ?y OpenVMS SDL V3.7 */F/* Source: 24-OCT-1995 08:39:36 $1$DGA8345:[LIB_H.SRC]PACDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PACDEF ***/#ifndef __PACDEF_LOADED#define __PACDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined when?ever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct v?ariant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* PACDEF */N/*- */ #define PAC$K_LENGTH 16#define PAC$C_LENGTH 16 c#if !defined(__NOBASEALIGN_SUPPORT) && !defin ?ed(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pac {#pragma __nomember_alignmentN char pac$t_name [4]; /* Port name */N unsigned int pac$l_spare; /* Possible expansion */ __union {N int pac$l_flags; /* Flag bits */ __struct {N unsigned pac$v_fil?ler : 32; /* (there are no flag bits) */ } pac$r_fill_1_; } pac$r_fill_0_;P unsigned int pac$l_allocls; /* The allocation class for this port */ } PAC; #if !defined(__VAXC)"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef? __cplusplus }#endif#pragma __standard #endif /* __PACDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the ?**/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior writte?n permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: ? 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PBBDEF ***/#ifndef __PBBDEF_LOADED#define __PBBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pra?gma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifn ?def __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Pending bad block file record format. Each record describes a disk block */N/* on which an error has occurred which has not been turned over to the bad */N/* block file. ? */N/* */N/*- */ #define PBB$M_READERR 0x1#define PBB$M_WRITERR 0x2N#define PBB$K_LENGTH 16 /* length of entry */N#define PBB$C_LENGTH 16 /* length of entry */N#define PBB$S_PBBDEF 16 /* Old size name - synonym */ typedef struct _pbb {N ?unsigned short int pbb$w_fid [3]; /* File ID of containing file */ __union {N unsigned char pbb$b_flags; /* status flags */ __struct {N unsigned pbb$v_readerr : 1; /* read error occurred */N unsigned pbb$v_writerr : 1; /* write error occurred */( unsigned pbb$v_fill_12_ : 6; } pbb$r_flags_bits; } pbb$r_flags_overlay;N unsigned char pbb$b_count; /* e?rror count */N unsigned int pbb$l_vbn; /* virtual block in file */N unsigned int pbb$l_lbn; /* logical block number */ } PBB; #if !defined(__VAXC)3#define pbb$b_flags pbb$r_flags_overlay.pbb$b_flagsH#define pbb$v_readerr pbb$r_flags_overlay.pbb$r_flags_bits.pbb$v_readerrH#define pbb$v_writerr pbb$r_flags_overlay.pbb$r_flags_bits.pbb$v_writerr"#endif /* #if !defined(__VAXC) */   $#pragma __member_align?ment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PBBDEF_LOADED */ ww][UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL?. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This soft?ware is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********************************************************************** ?****//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */E/* Source: 23-JUL-2003 15:22:43 $1$DGA8345:[LIB_H.SRC]PBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PBDEF ***/#ifndef __PBDEF_LOADED#define __PBDEF_LOADED 1 G#pragma __nostanda ?rd /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...?#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* PB - SCS PATH BLOCK */N/* ? */N/* THE PB HAS INFORMATION ABOUT THE PHYSICAL PATH TO ANOTHER */N/* SYSTEM IN A CLUSTER. PATH BLOCKS TO THE SAME SYSTEM ARE */N/* LINKED TOGETHER TO THE SYSTEM BLOCK (SB). */N/*- */ N#define PB$C_CLOSED 0 /* NEWLY CREATED PATHBLOCK */N#define PB$C_ST_SENT 1 ? /* START SENT */N#define PB$C_ST_REC 2 /* START RECEIVED */N#define PB$C_OPEN 3 /* OPEN PORT-PORT VIRTUAL CIRCUIT */N/* CI port virtual circuit failure states */N#define PB$C_STALL_SETCKT 4 /* SETCKT stalled by pool problem */N#define PB$C_CLOSE_CKT 5 /* SETCKT in progress */[#define PB$C_NOTIFY_VCFAIL 6 /* SYSAP notification f?or failed VC in progress */R#define PB$C_STALL_CACHE 7 /* Cache Clear stalled by pool problem */N#define PB$C_CACHE_CLEAR 8 /* Cache Clear in progress */]#define PB$C_NOTIFY_PWFAIL 9 /* SYSAP notification for failed port in progress */N/* */c#define PB$C_VC_FAIL 32768 /* VC FAILURE IN PROGRESS STATE (No longer used for CI) */i#define PB$C_PWR_FAIL 16384 ? /* PWR FAIL RECOVERY IN PROGRESS STATE (No longer used for CI) */ #define PB$M_DUALPATH 0x80000000N#define PB$C_CI780 2 /* CI780 PORT */N#define PB$C_CI750 2 /* CI750 PORT (=CI780) */N#define PB$C_HSC 4 /* HSC PORT */N#define PB$C_KL10 6 /* KLIPA PORT */N#define PB$C_CINT 7 /* CI NODE TESTER */?N#define PB$C_NI 8 /* NI-SCA (LAVC) PORT */N#define PB$C_PS 9 /* PASSTHRU PORT */N#define PB$C_BCA 11 /* BI-CI PORT */N#define PB$C_BVPSSP 12 /* BVP STORAGE PORT */N#define PB$C_BVPNI 13 /* BVP NI PORT */N#define PB$C_CIXCD 14 /* XMI-CI PORT CIXCD */N#define PB$C_CIXCDAC 16 ? /* XMI-CI N_PORT ALPHA CIXCD */#define PB$C_CITCA 17#define PB$C_CIPCA 18#define PB$C_MC 19#define PB$C_SMCI 20#define PB$C_SII 32#define PB$C_KFQSA 33#define PB$C_SHAC 34#define PB$C_XON 35#define PB$C_SWIFT 36#define PB$C_KFMSA 37#define PB$C_N710 38#define PB$C_KFMSB 39#define PB$C_RF70 48#define PB$C_RF71 48#define PB$C_RF30 49#define PB$C_RF31 50#define PB$C_RF72 51#define PB$C_RF32 52#define PB$C_RF73 53#define PB$C_RF31F 54?#define PB$C_RF35 55#define PB$C_RF36 58#define PB$C_RF37 59#define PB$C_RF74 60#define PB$C_RF75 61#define PB$C_TF70 64#define PB$C_TF30 65#define PB$C_TF85 65#define PB$C_TF86 66#define PB$C_HSJ 80#define PB$C_HSD 81#define PB$C_HSF 82#define PB$C_HSJ80 83#define PB$C_EF51 96#define PB$C_EF52 97#define PB$C_EF53 98#define PB$C_EF54 99#define PB$C_EF58 100#define PB$M_SRSNTDATWM 0x80#define PB$M_MAINT 0x1N#define PB$C_UNINIT 0 /* UNINITI?ALIZED, */N#define PB$C_DISAB 1 /* DISABLED */N#define PB$C_ENAB 2 /* ENABLED */N/* */#define PB$M_CUR_CBL 0x1#define PB$M_CUR_PS 0x1#define PB$M_TIM 0x1#define PB$M_VCCHK_ENB 0x2#define PB$M_SCS_EXP 0x4#define PB$M_NEW_MSG 0x8#define PB$M_UNUSED 0x10#define PB$M_CREDIT 0x20#define PB$M_DISC 0x40#defin?e PB$M_STORAGE 0x80#define PB$M_CLONE 0x100N#define PB$C_SMCI_LOAD_CLASS 2147483647 /* SMCI Load Class */N#define PB$C_MC_LOAD_CLASS 800 /* Memory Channel Load Class */N#define PB$C_CI_LOAD_CLASS 140 /* CI Load Class */N#define PB$C_DSSI_LOAD_CLASS 48 /* DSSI Load Class */N#define PB$C_NI_LOAD_CLASS 10 /* NI Default Load Class */N#define PB$K_LENGTH 172 /*LENGTH OF A PATH? BLOCK */N#define PB$C_LENGTH 172 /*LENGTH OF A PATH BLOCK */N#define PB$S_PBDEF 172 /*Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _sb; struct _cdt; #endif /* #ifdef __cplusplus */ typedef struct _pb {N struct _pb *pb$l_flink; /*FWD LINK TO NEXT PB */N struct _pb *pb$l_blink; /*BACK LINK TO PREVIOUS PB */N unsi?gned short int pb$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char pb$b_type; /*SCS STRUCTURE TYPE */N unsigned char pb$b_subtyp; /*SCS STRUCT SUBTYPE FOR PB */N unsigned char pb$b_rstation [6]; /*REMOTE STATION ADDRESS */N unsigned short int pb$w_state; /*PATH STATE */N/*STATE DEFINITIONS: */N/* 0 ORIGIN, INCREMENTS OF 1 ? */ __union {N unsigned int pb$l_rport_typ; /*HARDWARE PORT TYPE CODE */ __struct {N unsigned pb$v_port_typ : 31; /* HARDWARE PORT TYPE, */Q unsigned pb$v_dualpath : 1; /* 0/1 FOR SINGLE PATH/DUAL PATH PORT */" } pb$r_rport_typ_bits;! } pb$r_rport_typ_overlay; __union {N unsigned int pb$l_rport_rev; /*REMOTE PORT HW REV LEVEL */ __ ?struct {N unsigned pb$v_rport_rev_spare : 30; /* Spare */N unsigned pb$v_rport_spc_rev : 1; /* 0 = -A / 1 = -B */N unsigned pb$v_rport_rev_resv1 : 1; /* Reserved */" } pb$r_rport_rev_bits;! } pb$r_rport_rev_overlay; __union {N unsigned int pb$l_rport_fcn; /*REMOTE PORT FUNCTION MASK */ __struct {N unsigned pb$v_mbz : 7; /* reserved MBZ ? */X unsigned pb$v_srsntdatwm : 1; /*Send/Rec SNTDATWM (*not* in CI Port Arch) */" } pb$r_rport_fcn_bits;! } pb$r_rport_fcn_overlay;Q unsigned char pb$b_rst_port; /*OWNING PORT WHICH RESET REMOTE PORT */ __union {N unsigned char pb$b_rstate; /*REMOTE PORT STATUS: */ __struct {N unsigned pb$v_maint : 1; /* 0/1 FOR MAINTENANCE MODE NO/YES */N unsigned pb$v_state : 2; /* REM ?OTE PORT STATE: */& unsigned pb$v_fill_0_ : 5; } pb$r_rstate_bits;N/* DEFINE REMOTE STATES, 0 ORIGIN */ } pb$r_rstate_overlay;N unsigned short int pb$w_retry; /*START HANDSHAKE RETRY COUNT */N char pb$t_lport_name [4]; /*LOCAL PORT DEVICE NAME */ __union {N unsigned char pb$b_cbl_sts; /*CABLE STATUS TO THE REMOTE */ __struct {N ? unsigned pb$v_cur_cbl : 1; /* 1/0 FOR CURRENT STATUS OK/BAD */& unsigned pb$v_fill_1_ : 7; } pb$r_cbl_sts_bits; } pb$r_cbl_sts_overlay;N unsigned char pb$b_p0_sts; /*PATH 0 STATUS */ __union {N unsigned char pb$b_p1_sts; /*PATH 1 STATUS */ __struct {O unsigned pb$v_cur_ps : 1; /* 1/0 FOR CURRENT STATUS OK/BROKEN */& unsigned pb$v_fill_2_ : 7; ? } pb$r_p1_sts_bits; } pb$r_p1_sts_overlay;N char pb$$_fill_1; /*RESERVED BYTE */O void *pb$l_pdt; /*ADDR OF PORT DESCRIPTOR TABLE FOR */N/* LOCAL PORT */N struct _sb *pb$l_sblink; /*LINK TO SYSTEM BLOCK */N struct _cdt *pb$l_cdtlst; /*LINK TO FIRST CDT OVER THIS PATH */N/* (0 IF NO CDT'S) ? */N void *pb$l_waitqfl; /* SCS SEND MSG WAIT QUEUE FLINK */ __union {N void *pb$l_waitqbl; /*SCS SEND MSG WAIT QUEUE BLINK */N unsigned int pb$l_duetime; /*START HANDSHAKE TIMER */ } pb$r_waitqbl_overlay;N void *pb$l_scsmsg; /*ADDR OF SCS MESSAGE BUFFER */ __union {N unsigned short int pb$w_sts; /*PATH BLOCK STATUS */ ? __struct {N unsigned pb$v_tim : 1; /* HANDSHAKE TIMEOUT IN PROGRESS */N unsigned pb$v_vcchk_enb : 1; /* VC timeout checking enabled */X unsigned pb$v_scs_exp : 1; /* SCS message expected during timeout period */W unsigned pb$v_new_msg : 1; /* New message arrived during timeout period */N unsigned pb$v_unused : 1; /* Unused bit */N unsigned pb$v_credit : 1; /* SCS receive credit on fre ?e queue */S unsigned pb$v_disc : 1; /* SCS disconnect request is in progress */N unsigned pb$v_storage : 1; /* Storage only port (A DSSA port) */N unsigned pb$v_clone : 1; /* Clone (duplicate) node detected */& unsigned pb$v_fill_3_ : 7; } pb$r_sts_bits; } pb$r_sts_overlay;N unsigned short int pb$w_vcfail_rsn; /*VC FAILURE REASON (VMS */N/*STATUS CODE ? */N unsigned char pb$b_protocol; /*PPD PROTOCOL LEVEL */N char pb$$_fill_2 [3]; /*RESERVED BYTES */a unsigned int pb$l_rport_mult; /*LARGEST PACKET MULTIPLE OF THE REMOTE PORT (CI ONLY) */N/* SHIFTED TO BIT POSITION <30:28> */b unsigned int pb$l_time_stamp; /* (TYC 9-Mar-89) PB INSERTION TO CONFIG. DB TIME STAMP */e struct _pb *pb$l_share_flink; /* (TYC 15-Feb?-89) FWD LINK TO NEXT PB IN LOAD SHARE QUEUE */j struct _pb *pb$l_share_blink; /* (TYC 15-Feb-89) BACK LINK TO PREVIOUS PB IN LOAD SHARE QUEUE */\ __union { /* Temporary overlay until VC_COST can be removed */X int pb$l_load_class; /* VC's Load class - set by port to indicate */N/* max performance of underlying hardware. */N/* Interconnect load class values (Raw HW BW in Mb/S): */N ? __struct { /* Also temporary */h unsigned int pb$l_vc_cost; /* Load Sharing Cost for this Virtual Circuit (to be removed) */" } pb$r_cost_load_tmp2; } pb$r_cost_load_tmp;] int pb$l_priority; /* VC's current priority for connection selection, */N/* Includes both PB$ & PDT$ management priorities */\ int pb$l_mgt_priority; /* Management priority value assigned to? this VC. */] unsigned int pb$l_vc_addr; /* Address of Interconnect specific VC state block */N/* (eg: a PEdriver VC$ structure). SBZ if port doesn't have any. */N int pb$$_fill_3 [2]; /*RESERVED LONGWDS */N char pb$t_lport_name_alias [16]; /* copy of LOCAL PORT DEVICE NAME */N/* */N/* Tracing cells ?*/N/* */N unsigned int pb$l_cont_id; /* Current continuation ID mask */N/* Trace buffer address. */N/* 0 - tracing deselected for this pb */N/* 1 - trace buffer to be allocated */N/* other - allocated and selected */N void *pb$a_trace_b?uffer; /* Trace buffer adddress */N/* Debug fields */ unsigned int pb$l_dbg0; unsigned int pb$l_dbg1; unsigned int pb$l_dbg2; unsigned int pb$l_dbg3; unsigned int pb$l_dbg4; unsigned int pb$l_dbg5; unsigned int pb$l_dbg6; unsigned int pb$l_dbg7; } PB; #if !defined(__VAXC)<#define pb$l_rport_typ pb$r_rport_typ_overlay.pb$l_rport_typN#define pb$v_port_typ pb$r_r?port_typ_overlay.pb$r_rport_typ_bits.pb$v_port_typN#define pb$v_dualpath pb$r_rport_typ_overlay.pb$r_rport_typ_bits.pb$v_dualpath<#define pb$l_rport_rev pb$r_rport_rev_overlay.pb$l_rport_rev\#define pb$v_rport_rev_spare pb$r_rport_rev_overlay.pb$r_rport_rev_bits.pb$v_rport_rev_spareX#define pb$v_rport_spc_rev pb$r_rport_rev_overlay.pb$r_rport_rev_bits.pb$v_rport_spc_rev\#define pb$v_rport_rev_resv1 pb$r_rport_rev_overlay.pb$r_rport_rev_bits.pb$v_rport_rev_resv1<#define pb$l_rport_fcn pb$r_rport_ ?fcn_overlay.pb$l_rport_fcnD#define pb$v_mbz pb$r_rport_fcn_overlay.pb$r_rport_fcn_bits.pb$v_mbzR#define pb$v_srsntdatwm pb$r_rport_fcn_overlay.pb$r_rport_fcn_bits.pb$v_srsntdatwm3#define pb$b_rstate pb$r_rstate_overlay.pb$b_rstateB#define pb$v_maint pb$r_rstate_overlay.pb$r_rstate_bits.pb$v_maintB#define pb$v_state pb$r_rstate_overlay.pb$r_rstate_bits.pb$v_state6#define pb$b_cbl_sts pb$r_cbl_sts_overlay.pb$b_cbl_stsH#define pb$v_cur_cbl pb$r_cbl_sts_overlay.pb$r_cbl_sts_bits.pb$v_cur_cbl3#def ?ine pb$b_p1_sts pb$r_p1_sts_overlay.pb$b_p1_stsD#define pb$v_cur_ps pb$r_p1_sts_overlay.pb$r_p1_sts_bits.pb$v_cur_ps6#define pb$l_waitqbl pb$r_waitqbl_overlay.pb$l_waitqbl6#define pb$l_duetime pb$r_waitqbl_overlay.pb$l_duetime*#define pb$w_sts pb$r_sts_overlay.pb$w_sts8#define pb$v_tim pb$r_sts_overlay.pb$r_sts_bits.pb$v_timD#define pb$v_vcchk_enb pb$r_sts_overlay.pb$r_sts_bits.pb$v_vcchk_enb@#define pb$v_scs_exp pb$r_sts_overlay.pb$r_sts_bits.pb$v_scs_exp@#define pb$v_new_msg pb$r_sts_overla ?y.pb$r_sts_bits.pb$v_new_msg>#define pb$v_unused pb$r_sts_overlay.pb$r_sts_bits.pb$v_unused>#define pb$v_credit pb$r_sts_overlay.pb$r_sts_bits.pb$v_credit:#define pb$v_disc pb$r_sts_overlay.pb$r_sts_bits.pb$v_disc@#define pb$v_storage pb$r_sts_overlay.pb$r_sts_bits.pb$v_storage<#define pb$v_clone pb$r_sts_overlay.pb$r_sts_bits.pb$v_clone:#define pb$l_load_class pb$r_cost_load_tmp.pb$l_load_classH#define pb$l_vc_cost pb$r_cost_load_tmp.pb$r_cost_load_tmp2.pb$l_vc_cost"#endif /* #if !defined(__?VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PBDEF_LOADED */ ww[UM/***************************************************************************/M/** ? **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VM?S SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*******************************?********************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 20-APR-1993 14:30:34 $1$DGA8345:[LIB_H.SRC]PBHDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PBHDEF ***/#ifndef __PBHDEF_LOADED#defin ?e __PBHDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_?params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DEFINE PERFORMANCE BUFFER HEADER ? */N/*- */N#define PBH$K_START 13 /*START OF DATA AREA */N#define PBH$C_START 13 /*START OF DATA AREA */O#define PBH$K_LENGTH 512 /*LENGTH OF PERFORMANCE DATA BUFFER */O#define PBH$C_LENGTH 512 /*LENGTH OF PERFORMANCE DATA BUFFER */#define PBH$S_PBHDEF 512 typedef struct _pbh {N struct _pbh *pbh ?$l_bufrfl; /*BUFFER FORWARD LINK */N struct _pbh *pbh$l_bufrbl; /*BUFFER BACKWARD LINK */N unsigned short int pbh$w_size; /*SIZE OF PERFORMANCE DATA BUFFER */N unsigned char pbh$b_type; /*DATA STRUCTURE TYPE */N unsigned short int pbh$w_msgcnt; /*COUNT OF MESSAGES IN BUFFER */N char pbhdef$$_fill_1 [499]; /*DATA AREA */ } PBH; $#pragma __member_alignment __r?estoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PBHDEF_LOADED */ wwӒ[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This s?oftware is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is ?confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************/ ?/********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 19-MAY-1993 13:53:31 $1$DGA8345:[LIB_H.SRC]PBODEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PBODEF ***/#ifndef __PBODEF_LOADED#define __PBODEF_LOADED 1 G#pragma __nostandard ? /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#els?e#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* PBO - SCS$CONFIG_PTH CALL OUTPUT ARRAY FORMAT */N/* ? */T/* THE OUTPUT ARRAY RETURNED FROM THE SCS$CONFIG_PTH CALL. DATA IS MOSTLY COPIED */N/* FROM THE PATH BLOCK (PB) BEING LOOKED UP. */N/*- */ #define PBO$M_SRSNTDATWM 0x80N#define PBO$C_NXT_VC 32 /*SPECIFIER OF NEXT VC (PB) */N#define PBO$K_NXT_VC 32 /* TO THIS SYSTEM (12 BYTE */N/* S ?PECIFIER FOLLOWS:) */N#define PBO$C_LENGTH 52 /*LENGTH OF PBO */N#define PBO$K_LENGTH 52 /*LENGTH OF PBO */N#define PBO$S_PBODEF 52 /* Old size name - synonym */ typedef struct _pbo {N unsigned char pbo$b_rstation [6]; /*REMOTE STATION ADDR */N unsigned short int pbo$w_state; /*PATH STATE */N ? unsigned int pbo$l_rport_typ; /*REMOTE PORT HW PORT TYPE */N unsigned int pbo$l_rport_rev; /*REMOTE PORT REV LEVEL */ __union {N unsigned int pbo$l_rport_fcn; /*REMOTE PORT FUNCTION MASK */ __struct {N unsigned pbo$v_mbz : 7; /* reserved MBZ */Y unsigned pbo$v_srsntdatwm : 1; /*Send/Rec SNTDATWM (*not* in CI Port Arch) */# } pbo$r_rport_fcn_bits;" } pbo$r_rpor?t_fcn_overlay;N unsigned char pbo$b_rst_port; /*OWNING PORT WHICH LAST */N/* RESET THIS REMOTE */N unsigned char pbo$b_rstate; /*REMOTE PORT STATE */N unsigned short int pbo$w_retry; /*START HANDSHAKE RETRIES LEFT */N char pbo$t_lport_name [4]; /*LOCAL PORT DEVICE NAME */N unsigned char pbo$b_cbl_sts; /*CURRENT CABLE STATUS */N unsign?ed char pbo$b_p0_sts; /*PATH 0 STATUS */N unsigned char pbo$b_p1_sts; /*PATH 1 STATUS */N char pbo$$_fill_1; /*RESERVED BYTE */N unsigned char pbo$b_nxt_rstat [6]; /* REMOTE STATION ADDR */N short int pbo$$_fill_2; /* RESERVED WORD */N char pbo$t_nxt_lport [4]; /* LOCAL PORT NAME ON NXT PB */N unsigned char pbo$b_systemid [6] ?; /*ID OF SYSTEM ASSOC WITH */N/* THIS PB */N short int pbo$$_fill_3; /*RESERVED WORD */ } PBO; #if !defined(__VAXC)?#define pbo$l_rport_fcn pbo$r_rport_fcn_overlay.pbo$l_rport_fcnH#define pbo$v_mbz pbo$r_rport_fcn_overlay.pbo$r_rport_fcn_bits.pbo$v_mbzV#define pbo$v_srsntdatwm pbo$r_rport_fcn_overlay.pbo$r_rport_fcn_bits.pbo$v_srsntdatwm"#endif /* #if !defined(__VAXC) */?  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PBODEF_LOADED */ ww ![UM/***************************************************************************/M/** ? **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE?, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*****************************************?**********************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:30 by OpenVMS SDL V3.7 */F/* Source: 30-NOV-2017 16:36:09 $1$DGA8345:[LIB_H.SRC]PCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PCBDEF ***/#ifndef __PCBDEF_LOADED#define __PCBDEF ?_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...?#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Software Process Control Block Definitions ? */N/* */  Y#include /* Define the FKB type; embedded FKB used for deferred SCHED work */#include #define PCB$M_RES 0x1#define PCB$M_DELPEN 0x2#define PCB$M_FORCPEN 0x4#define PCB$M_INQUAN 0x8#define PCB$M_PSWAPM 0x10#define PCB$M_RESPEN 0x20#define PCB$M_SSFEXC 0x40#define PCB$M_SSFEXCE 0x80#define PCB$M_SSFEXCS 0x100#define PCB$M_SSFEXCU 0x200#def?ine PCB$M_SSRWAIT 0x400#define PCB$M_SUSPEN 0x800#define PCB$M_WALL 0x2000#define PCB$M_BATCH 0x4000#define PCB$M_NOACNT 0x8000#define PCB$M_NOSUSPEND 0x10000#define PCB$M_ASTPEN 0x20000#define PCB$M_PHDRES 0x40000#define PCB$M_HIBER 0x80000#define PCB$M_LOGIN 0x100000#define PCB$M_NETWRK 0x200000#define PCB$M_PWRAST 0x400000#define PCB$M_NODELET 0x800000#define PCB$M_DISAWS 0x1000000#define PCB$M_INTER 0x2000000#define PCB$M_RECOVER 0x4000000 #define PCB$M_HARD?AFF 0x10000000#define PCB$M_ERDACT 0x20000000!#define PCB$M_SOFTSUSP 0x40000000"#define PCB$M_PREEMPTED 0x80000000!#define PCB$M_QUANTUM_RESCHED 0x1+#define PCB$M_DISABLE_PREEMPT_PKTA_LOCK 0x2#define PCB$M_FREDLOCK 0x4#define PCB$M_PHDLOCK 0x8#define PCB$M_TCB 0x10$#define PCB$M_TBS_STATE_PENDING 0x20$#define PCB$M_SS_LOGGING_ENABLE 0x40"#define PCB$M_SS_LOGGING_PERM 0x80&#define PCB$M_BRK_RUNDOWN_LOADED 0x100%#define PCB$M_CLASS_SCHED_PERM 0x8000!#define PCB$M_TERM_NOTIFY 0x10?000 #define PCB$M_BYTLM_LOAN 0x20000%#define PCB$M_DISABLE_PREEMPT 0x40000 #define PCB$M_NOUNSHELVE 0x80000(#define PCB$M_SHELVING_RESERVED 0x100000&#define PCB$M_CLASS_SCHEDULED 0x200000%#define PCB$M_CLASS_SUPPLIED 0x400000##define PCB$M_IN_TBS_STATE 0x800000 #define PCB$M_WINDFALL 0x1000000#define PCB$M_NOTIFY 0x2000000(#define PCB$M_SINGLE_THREADED 0x3C000000#define PCB$M_RWAST 0x40000000+#define PCB$M_SOFT_SINGLE_THREAD 0x80000000"#define PCB$M_EPID_WILD 0x80000000#define PC?B$M_FORK 0x1N#define PCB$K_SCHED_OTHER 0 /* Native VMS policy (MBZ) */N#define PCB$K_SCHED_FIFO 1 /* POSIX FIFO policy */N#define PCB$K_SCHED_RR 2 /* POSIX Round-Robbin policy */N/* [1..10] for POSIX */N#define PCB$K_SCHED_POLICY_CNT 3 /* # legal sched policies */O#define PCB$K_ALL_THREADS -2147483648 /* policy affects all kernel threads */W#define PC?B$K_MAX_KT_COUNT 256 /* Absolute maximum number of kernel threads */#define PCB$M_EVENT_NO_FLAG 0x1#define PCB$M_IN_DELPAG 0x1#define PCB$M_WAKEPEN 0x1000 #define PCB$M_SECAUDIT 0x8000000+#define PCB$M_UPCALL_AST_BLOCKED 0x80000000#define PCB$M_SUGID_IMAGE 0x1#define PCB$M_SUGID_PROCESS 0x2  9#ifdef __cplusplus /* Define structure prototypes */ struct _acb; struct _phd; struct _jib; struct _arb; struct _orb; struct _pmb; struct _pdb; struct _xscb; stru?ct _rmcb; struct _cde; struct _rdpb; struct _psb; struct _ktb; struct _lkb; struct _spl; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pcb {#pragma __nomember_alignmentN struct _pcb *pcb$l_sqfl; /* State queue forward link */N struct _pcb *pcb$l_sqbl; /* Sta ?te queue backward link */N unsigned short int pcb$w_size; /* Size, in bytes */N unsigned char pcb$b_type; /* Structure type code for PCB */ unsigned char pcb$b_fill_1;N unsigned int pcb$l_ast_pending; /* AST pending mask */N unsigned __int64 pcb$q_phypcb; /* Physical address of HWPCB */ __union {N unsigned __int64 pcb$q_lefc_swapped; /* Local event flags - swapped */ __struct {N? unsigned int pcb$l_lefc_0_swapped; /* Cluster 0 */N unsigned int pcb$l_lefc_1_swapped; /* Cluster 1 */* } pcb$r_lefc_clusters_swapped;% } pcb$r_lefc_overlay_swapped;[ struct _acb *pcb$l_astqfl_spk; /* Special kernel AST queue forward link (head) */X struct _acb *pcb$l_astqbl_spk; /* Special kernel AST queue back link (tail) */R struct _acb *pcb$l_astqfl_k; /* Kernel AST queue forward link (head?) */O struct _acb *pcb$l_astqbl_k; /* Kernel AST queue back link (tail) */U struct _acb *pcb$l_astqfl_e; /* Executive AST queue forward link (head) */R struct _acb *pcb$l_astqbl_e; /* Executive AST queue back link (tail) */V struct _acb *pcb$l_astqfl_s; /* Supervisor AST queue forward link (head) */S struct _acb *pcb$l_astqbl_s; /* Supervisor AST queue back link (tail) */P struct _acb *pcb$l_astqfl_u; /* User AST queue forward link (?head) */N struct _acb *pcb$l_astqbl_u; /* User AST queue back link (tail) */N int pcb$l_prvcpu; /* Previous CPU (not current CPU) */T int pcb$l_cpu_id; /* Current CPU (last one to load context) */Q unsigned __int64 pcb$q_prvasn; /* Previous Address Space Number (ASN) */N unsigned __int64 pcb$q_prvasnseq; /* Previous ASN/RID Sequence Number */N unsigned __int64 pcb$q_oncpucnt; /* Count of threads in CUR state */N un?signed int pcb$l_astact; /* Access modes with active ASTs */N unsigned int pcb$l_state; /* Process state */K unsigned int pcb$l_pri; /* Process current priority */N unsigned int pcb$l_prib; /* Base priority */N unsigned int pcb$l_affinity_skip; /* Affinity skip count */N unsigned int pcb$l_owner; /* EPID of owner, if a subprocess */ __union {N unsigned i?nt pcb$l_sts; /* Process status flags */ __struct {N unsigned pcb$v_res : 1; /* Resident, in balance set */N unsigned pcb$v_delpen : 1; /* Delete pending */N unsigned pcb$v_forcpen : 1; /* Force exit pending */N unsigned pcb$v_inquan : 1; /* Initial quantum in progress */N unsigned pcb$v_pswapm : 1; /* Process swap mode, 1=NOSWAP */N unsigned p?cb$v_respen : 1; /* Resume pending, skip suspend */R unsigned pcb$v_ssfexc : 1; /* System service exception enable (K) */R unsigned pcb$v_ssfexce : 1; /* System service exception enable (E) */R unsigned pcb$v_ssfexcs : 1; /* System service exception enable (S) */R unsigned pcb$v_ssfexcu : 1; /* System service exception enable (U) */S unsigned pcb$v_ssrwait : 1; /* System service resource wait disable */N unsigned pcb$v?_suspen : 1; /* Suspend pending */W unsigned pcb$v_reserved_1 : 1; /* reserved bit, overlays WAKEPEN in STS3 */N unsigned pcb$v_wall : 1; /* Wait for all events in mask */N unsigned pcb$v_batch : 1; /* Process is a batch job */N unsigned pcb$v_noacnt : 1; /* No accounting for process */N unsigned pcb$v_nosuspend : 1; /* Process cannot be suspended */N unsigned pcb$v_astpen : 1; /*? AST pending */N unsigned pcb$v_phdres : 1; /* Process header resident */U unsigned pcb$v_hiber : 1; /* Hibernate after initial image activate */N unsigned pcb$v_login : 1; /* Login without reading UAF */N unsigned pcb$v_netwrk : 1; /* Network connect job */N unsigned pcb$v_pwrast : 1; /* Power fail AST */N unsigned pcb$v_nodelet : 1; /* No delete ? */N unsigned pcb$v_disaws : 1; /* Disable automatic WS adjustment */N unsigned pcb$v_inter : 1; /* Process is an interactive job */N unsigned pcb$v_recover : 1; /* Process can recover locks */X unsigned pcb$v_reserved_4 : 1; /* reserved bit, overlays SECAUDIT in STS3 */P unsigned pcb$v_hardaff : 1; /* Process is bound to particular CPU */N unsigned pcb$v_erdact : 1; /* Exec mode rundown active @ */N unsigned pcb$v_softsusp : 1; /* Process is in "soft" suspend */O unsigned pcb$v_preempted : 1; /* Hard suspend has preempted soft */ } pcb$r_fill_1_; } pcb$r_fill_0_; __union {N unsigned int pcb$l_sts2; /* Process status flags (2nd LW) */ __struct {Y unsigned pcb$v_quantum_resched : 1; /* Quantum-oriented process reschedule */_ unsigned pcb$v_disable_preempt_pkta_lock : 1; /* Disable pre@empt locked the PKTA */W unsigned pcb$v_fredlock : 1; /* Don't swap PHD -- process has FRED pages */Y unsigned pcb$v_phdlock : 1; /* Don't swap PHD -- process has $LCKPAG pages */N unsigned pcb$v_tcb : 1; /* TCB process */^ unsigned pcb$v_tbs_state_pending : 1; /* Going to TBS, but not on the queue yet */U unsigned pcb$v_ss_logging_enable : 1; /* Enable system service logging */[ unsigned pcb$v_ss_logg@ing_perm : 1; /* Logging persists across image rundown */a unsigned pcb$v_brk_rundown_loaded : 1; /* image rundown handler loaded by $BRKTHRU */& unsigned pcb$v_fill_3 : 6;d unsigned pcb$v_class_sched_perm : 1; /* process is part of permanent scheduling class */N unsigned pcb$v_term_notify : 1; /* termination notification */Y unsigned pcb$v_bytlm_loan : 1; /* Process has received rundown BYTLIM loan */Y unsigned pcb$v_disab@le_preempt : 1; /* Allow process to prevent preemption */N unsigned pcb$v_nounshelve : 1; /* if set, don't auto-unshelve */V unsigned pcb$v_shelving_reserved : 1; /* Reserved for shelving facility */U unsigned pcb$v_class_scheduled : 1; /* This process is class scheduled */\ unsigned pcb$v_class_supplied : 1; /* This process has been assigned a class, */N/* or an explicit "No class" (happens only */N/* when CLASS_SC@HEDULED is cleared) */O unsigned pcb$v_in_tbs_state : 1; /* This process is in TBS state */N unsigned pcb$v_windfall : 1; /* Process eligible for windfall */R unsigned pcb$v_notify : 1; /* Send process termination msg. to CSP */V unsigned pcb$v_single_threaded : 4; /* single threaded bits, 1 per mode */N unsigned pcb$v_rwast : 1; /* A thread is in RWAST */[ unsigned pcb$v_s@oft_single_thread : 1; /* ASTs allowed during $single_thread */ } pcb$r_fill_3_; } pcb$r_fill_2_;I unsigned int pcb$l_prisav; /* Saved current priority */F unsigned int pcb$l_pribsav; /* Saved base priority */N unsigned int pcb$l_authpri; /* Initial process priority */U unsigned int pcb$l_onqtime; /* Abs time when placed on COM/COMO queue, */N/* adjusted for process wait time @ */N unsigned int pcb$l_waitime; /* Abs time of last process event */N unsigned int pcb$l_astcnt; /* AST count remaining */N unsigned int pcb$l_biocnt; /* Buffered I/O count remaining */N unsigned int pcb$l_biolm; /* Buffered I/O limit */N int pcb$l_diocnt; /* Direct I/O count remaining */N int pcb$l_diolm; /* Direct I/O count limit */N unsigned i@nt pcb$l_prccnt; /* Subprocess count */Y void *pcb$ps_ibrvec; /* Instruction break register array ptr (IA64) */R void *pcb$ps_dbrvec; /* Data break register array ptr (IA64) */N unsigned int pcb$l_wefc; /* Waiting EF cluster number */N unsigned int pcb$l_efwm; /* Event flag wait mask */O unsigned int pcb$l_efcs; /* Local event flag cluster, system */N unsigned int pcb$l @_efcu; /* Local event flag cluster, user */ __union { __struct {N int pcb$l_efc2p; /* Pointer to global cluster #2 */N int pcb$l_efc3p; /* Pointer to global cluster #3 */# } pcb$r_cefc_overlay_1;N __struct { /* (used only until SHELL runs) */N unsigned short int pcb$w_pgflchar; /* Page file characteristics */O unsigned char pcb$b_pgflindex; /* Desire @d SYSTEM page file index */# } pcb$r_cefc_overlay_2; } pcb$r_cefc_overlay;X unsigned int pcb$l_pid; /* Process ID used by exec on local node only */N/* */Z/**** WARNING - THE INTERNAL STRUCTURE OF THE EPID IS SUBJECT TO RADICAL CHANGE BETWEEN */X/**** VERSIONS OF VMS. NO ASSUMPTIONS SHOULD EVER BE MADE ABOUT ITS FORMAT */N/*  @ */ __union {W unsigned int pcb$l_epid; /* Cluster-wide process ID seen by the world */ __struct {[ unsigned pcb$v_epid_proc : 21; /* Process ID field, can convert to PCB$l_pid */` unsigned pcb$v_epid_node_idx : 8; /* IDX - index to table of node identifications */d unsigned pcb$v_epid_node_seq : 2; /* SEQ - sequence number for node table entry reuse */` unsigned pcb$v_epid_wild : 1; /* Flag that EPI @D is wildcard context for $GETJPI, */ } pcb$r_fill_5_; } pcb$r_fill_4_;N/* and not a valid EPID */N unsigned int pcb$l_eowner; /* EPID of process owner */P unsigned int pcb$l_aptcnt; /* Active page table count on outswap */N unsigned int pcb$l_mtxcnt; /* Count of mutex semaphores owned */N unsigned int pcb$l_gpgcnt; /* Global page count in WS */N unsi @gned int pcb$l_ppgcnt; /* Process page count in WS */N void *pcb$l_wsswp; /* Swap file disk address */N unsigned int pcb$l_swapsize; /* Swap block allocation */N struct _phd *pcb$l_phd; /* Address of Process Header */O struct _jib *pcb$l_jib; /* Address of Job Information Block */ __struct {N unsigned __int64 pcb$q_priv; /* Current privilege mask */N struct @ _arb *pcb$l_arb; /* Address of Access Rights Block */N char pcb$$$_arb_fill_1 [48]; /* Rights list descriptors, etc. */ __union {N unsigned int pcb$l_uic; /* Logon UIC of process */ __struct {N unsigned short int pcb$w_mem; /* Member number in UIC */N unsigned short int pcb$w_grp; /* Group number in UIC */ } pcb$r_fill_7_; } pcb$r_fill_6_;N ch@ar pcb$$$_arb_fill_2 [60]; /* Remainder of ARB */ } pcb$r_pcbarb;N struct _orb *pcb$l_orb; /* Address of process ORB */N unsigned int pcb$l_tmbu; /* Termination mailbox unit number */a unsigned int pcb$l_home_rad; /* Number of the RAD that contains most process memory */N char pcb$b_ktb_padding_0 [4]; /* Used in the KTB */N int pcb$l_dlckpri; /* Deadlock resolution priorit@y */N unsigned int pcb$l_defprot; /* Process default protection */N struct _pmb *pcb$l_pmb; /* PMB address */N int pcb$l_affinity; /* CPU ID for affinity */N unsigned int pcb$l_capability; /* CPU capability selection bitmask */R unsigned int pcb$l_cputim; /* Accumulated CPU time at last outswap */N char pcb$t_lname [16]; /* Process name */W struct _@pdb *pcb$l_prcpdb; /* Address of process Performance Data Block */N/***** For DIGITAL software use only ***** */R unsigned int pcb$l_pixhist; /* PIXSCAN history summary LW (bitmask) */N int pcb$l_affinity_callback; /* Callback for breaking affinity */N unsigned int pcb$l_permanent_capability; /* Permanent capability mask */W int pcb$l_cbb_reserved_1; /* $l_permanent_cpu_affinity moves to bottom */N unsigned _@_int64 pcb$q_cwpssrv_queue; /* CWPS service block queue */Q int pcb$l_cbb_reserved_2; /* $l_current_affinity moves to bottom */N int pcb$l_capability_seq; /* Copy of last sequence number */O unsigned __int64 pcb$q_bufobj_list; /* Defined buffer objects queue head */N unsigned int pcb$l_ast_blocked; /* AST blocked bits */V void *pcb$l_class_quant; /* Address of cell containing class quantum */g unsigned short int pcb@$w_class_extra_ticks; /* if class scheduled, extra ticks given to this KTB */Q unsigned char pcb$b_pkta_lock; /* Number of lockers of PKTA structure */ unsigned char pcb$b_fill_2;T void *pcb$a_current_tx; /* Pointer to process default transaction */V void *pcb$a_current_cd; /* Pointer to process default commit domain */Y void *pcb$a_current_vertex; /* Pointer to process default execution vertex */ __union {N unsigned __int64 p@cb$q_xscb_que; /* Transaction Segment list */ __struct {+ struct _xscb *pcb$a_xscb_flink;+ struct _xscb *pcb$a_xscb_blink; } pcb$r_fill_9_; } pcb$r_fill_8_; __union {N unsigned __int64 pcb$q_rmcb_que; /* Declared resource manager list */ __struct {+ struct _rmcb *pcb$a_rmcb_flink;+ struct _rmcb *pcb$a_rmcb_blink; } pcb$r_fill_11_; } pcb$r_fill_10_; __union @ {N unsigned __int64 pcb$q_cd_que; /* Commit domain membership list */ __struct {( struct _cde *pcb$a_cd_flink;( struct _cde *pcb$a_cd_blink; } pcb$r_fill_13_; } pcb$r_fill_12_;N unsigned int pcb$l_dpc; /* Delete pending count */N unsigned int pcb$l_cputime_ref; /* CPUTIME at last TICK time */N unsigned int pcb$l_acc_waitime; /* Accumulated wait time */N int pcb$l_pr @cstr; /* alternate procstrt */O void *pcb$l_xpcb; /* address of the POSIX extended PCB */N unsigned int pcb$l_psx_fork_status; /* POSIX fork status cell */ __union {N unsigned int pcb$l_psx_flags; /* POSIX flags */ __struct {N unsigned pcb$v_fork : 1; /* In fork synchronization *// unsigned pcb$v_psx_flags_fill : 31; } pcb$r_fill_15_;@ } pcb$r_fill_14_;N void (*pcb$l_psx_actrtn)(); /* POSIX fork action routine */Q unsigned __int64 pcb$q_psx_actprm; /* POSIX fork action routine parameter */N unsigned int pcb$l_kernel_counter; /* Per-process kernel mode counters */N unsigned int pcb$l_exec_counter; /* Per-process exec mode counters */N unsigned int pcb$l_super_counter; /* Per-process super mode counters */N unsigned int pcb$l_user_counter; /* Per-process user mode counters @ */N unsigned int pcb$l_sched_policy; /* POSIX sched policy */[ int (*pcb$a_frewsle_callout)(); /* Routine to notify of WSLE about to be removed */ __union {\ unsigned int pcb$l_frewsle_param; /* Parameter to pass to FREWSLE_CALLOUT routine */N int pcb$l_pqb; /* Pointer to Process Quota Block */N/* (process creation only) */ } pcb$r_pqb_overlay;Q unsigned int pcb$l_buf @obj_cnt; /* Buffer object page count on outswap */N unsigned int pcb$l_noaudit; /* count of reasons not to audit */N unsigned int pcb$l_source_epid; /* Impersonation EPID */ __union {N unsigned __int64 pcb$q_rdpb_que; /* Resource Domain pointer block */ __struct {+ struct _rdpb *pcb$a_rdpb_flink;+ struct _rdpb *pcb$a_rdpb_blink; } pcb$r_fill_17_; } pcb$r_fill_16_;N unsigned __int@64 pcb$q_files_64; /* s-64 bits and bobs */N __int64 pcb$q_keep_in_ws; /* Base of range */N __int64 pcb$q_keep_in_ws2; /* End of range */N int pcb$l_cbb_reserved_3; /* $l_active_cpus moves to bottom */N unsigned int pcb$l_tquantum; /* Per user thread quantum */N unsigned int pcb$l_multithread; /* Max Kthread count */N unsigned int pcb$l_kt_count; /* K @thread count */N unsigned int pcb$l_kt_high; /* highest ktb vector entry used */N void *pcb$l_ktbvec; /* KTB vector adddress */N struct _acb *pcb$l_wake_acb; /* WAKE upcall ACB address */P unsigned int pcb$l_st_ack_count; /* Thread ACK cnt for $single_thread */ __union {a unsigned int pcb$l_thread_events; /* Events to pass notification to the thread manager */ __struct {N @ unsigned pcb$v_event_no_flag : 1; /* The no-flag event */( unsigned pcb$v_fill_26_ : 7; } pcb$r_fill_19_; } pcb$r_fill_18_;N struct _acb *pcb$l_postef_acb; /* Postef upcall ACB */ __union {N unsigned __int64 pcb$q_postef; /* SET local event flags */ __struct {N unsigned int pcb$l_postef1; /* Cluster 0 */N unsigned int pcb$l_postef2; /* Cluster 1 @ */$ } pcb$r_postef_clusters; } pcb$r_postef_overlay;N unsigned int pcb$l_swp_seq; /* Outswap seq number */N unsigned int pcb$l_swp_kt; /* Outswappable kt count */[ struct _acb *pcb$l_im_astqfl_spk; /* Special kernel AST queue forward link (head) */X struct _acb *pcb$l_im_astqbl_spk; /* Special kernel AST queue back link (tail) */R struct _acb *pcb$l_im_astqfl_k; /* Kernel AST queue forwar@d link (head) */O struct _acb *pcb$l_im_astqbl_k; /* Kernel AST queue back link (tail) */U struct _acb *pcb$l_im_astqfl_e; /* Executive AST queue forward link (head) */R struct _acb *pcb$l_im_astqbl_e; /* Executive AST queue back link (tail) */N void *pcb$ps_ccbsva; /* SVA of CCB for Fast-IO users */N unsigned int pcb$l_maxfix; /* Maximum fandle index */N void *pcb$ps_fandle; /* Fandle vector for Fast-IO users @ */ char pcb$b_fill_27_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifV unsigned __int64 pcb$q_st_kt_array; /* Single thread array of kernel thread ids */#pragma __nomember_alignmentN struct _psb *pcb$ar_natural_psb; /* Pointer to Natural Persona */ __union {N unsigned int pcb$l_sts3; /* Process status flags @ */ __struct {V unsigned pcb$v_in_delpag : 1; /* Process has entered MMG$DELPAG_64_WORK */\ unsigned pcb$v_reserved_2 : 11; /* Reserved bits, overlays with fields in STS */N unsigned pcb$v_wakepen : 1; /* Wake pending, skip hibernate */\ unsigned pcb$v_reserved_3 : 14; /* Reserved bits, overlays with fields in STS */R unsigned pcb$v_secaudit : 1; /* Mandatory security auditing enabled */[ unsigned pcb$v_res @erved_5 : 3; /* Reserved bits, overlays with fields in STS */_ unsigned pcb$v_upcall_ast_blocked : 1; /* indicates that upcall ASTs are blocked */ } pcb$r_fill_21_; } pcb$r_fill_20_; __union {N struct _ktb *pcb$l_initial_ktb; /* Initial KTB, overlays KTB$L_PCB */N struct _pcb *pcb$l_pcb; /* PCB, overlays PCB$L_INITIAL_KTB */! } pcb$r_pcb_iktb_overlay;N char pcb$b_ktb_padding_1 [4]; /* Pad to match KTB !@ */N int pcb$l_deadlock_wait; /* per-process deadlock wait */N char pcb$b_ktb_padding_11 [108]; /* Pad to match KTB */O void *pcb$l_ctx_waitq; /* list of synch/context wait blocks */ char pcb$b_fill_28_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* "@Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _lkb *pcb$q_lockqfl; /* Lock queue forward link */#else unsigned __int64 pcb$q_lockqfl;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _lkb *pcb$q_lockqbl #@; /* Lock queue backward link */#else unsigned __int64 pcb$q_lockqbl;#endifN char pcb$b_ktb_padding_2 [40]; /* Pad to match KTB */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _pcb *pcb$l_class_link; /* Link PCB into scheduling class */O void *pcb$l_session_id; /* Pointer to POSIX $@Session ID block */R void *pcb$l_process_group; /* Pointer to POSIX Process Group block */Y unsigned int pcb$l_creator; /* EPID of creator process (Unix-style parent) */N unsigned int pcb$l_lckrq; /* pointer to LCKRQ packet */N char pcb$b_ktb_padding_3 [4]; /* Space for comq head */X char pcb$b_ktb_padding_4 [16]; /* Space for ktb sched count and FRED overlay */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cpluspl%@us) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN unsigned __int64 pcb$q_tqe_flags; /* TQE flags */ __struct {N unsigned int pcb$l_timer; /* Timer Request info */N unsigned int pcb$l_wakeup; /* Wakeup Call info */ } pcb$r_fill_23_; } pcb$r_fill_22_;N st&@ruct _acb *pcb$l_acb_stall_queue; /* Address of ACB stall queue */R struct _spl *pcb$l_spinlock; /* Address of the PCB specific spinlock */b unsigned int pcb$l_delprc_forced; /* Mask of modes for which DELPRC forced exit is active */S unsigned int pcb$l_image_persona; /* Index of persona granted by an image, */N/* or of the POSIX/COE "Real" persona. */O unsigned int pcb$l_saved_uid; /* UID saved from a SETUID operation */S '@ unsigned int pcb$l_saved_gid; /* GID saved from a SETGID operation */ __union {Z unsigned int pcb$l_image_flags; /* process state determined by image activation */ __struct {N unsigned pcb$v_sugid_image : 1; /* Running a SUID or SGID image */c unsigned pcb$v_sugid_process : 1; /* subprocess, decended from running a SGUID image */1 unsigned pcb$v_image_flags_fill : 30; } pcb$r_fill_25_; } pcb$r_fill_24_(@; char pcb$b_fill_29_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB pcb$r_cbb_perm_cpu_affinity; /* Embedded CBB block */N __struct { /* Compatability offset cells */) __int64 pcb$q_cbb_fill_1 [6]; __union {W )@ unsigned int pcb$l_permanent_cpu_affinity; /* Permanent CPU affinity */[ unsigned __int64 pcb$q_permanent_cpu_affinity; /* Permanent CPU affinity */. } pcb$r_cbb_perm_data_overlay;* __int64 pcb$q_cbb_fill_2 [15];, } pcb$r_cbb_perm_compat_overlay;! } pcb$r_cbb_perm_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pra *@gma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB pcb$r_cbb_current_affinity; /* Embedded CBB block */N __struct { /* Compatability offset cells */) __int64 pcb$q_cbb_fill_3 [6]; __union {N unsigned int pcb$l_current_affinity; /* Current CPU mask */O unsigned __int64 pcb$q_current_affinity; /* Current CPU mask */1 } pcb$r_cbb_curraff_ +@data_overlay;* __int64 pcb$q_cbb_fill_4 [15];. } pcb$r_cbb_curaff_compat_overlay;# } pcb$r_cbb_curaff_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB pcb$r_cbb_active_cpus; /* Embedded CBB block */N __struct { /* C ,@ompatability offset cells */) __int64 pcb$q_cbb_fill_5 [6]; __union {P unsigned int pcb$l_active_cpus; /* CPUs owned by this process */T unsigned __int64 pcb$q_active_cpus; /* CPUs owned by this process */0 } pcb$r_cbb_actcpu_data_overlay;* __int64 pcb$q_cbb_fill_6 [15];. } pcb$r_cbb_actcpu_compat_overlay;# } pcb$r_cbb_actcpu_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cpl -@usplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB pcb$r_cbb_affinities; /* Embedded CBB block */N __struct { /* Compatability offset cells */) __int64 pcb$q_cbb_fill_7 [6]; __union {N unsigned int pcb$l_affinities; /* Thread affinity mask */N .@unsigned __int64 pcb$q_affinities; /* Thread affinity mask */. } pcb$r_cbb_affs_data_overlay;* __int64 pcb$q_cbb_fill_8 [15];, } pcb$r_cbb_affs_compat_overlay;! } pcb$r_cbb_affs_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB pcb$r_cbb_permanent_ /@affinities; /* Embedded CBB block */N __struct { /* Compatability offset cells */) __int64 pcb$q_cbb_fill_9 [6]; __union {] unsigned int pcb$l_permanent_affinities; /* Thread permanent affinity mask */a unsigned __int64 pcb$q_permanent_affinities; /* Thread permanent affinity mask */2 } pcb$r_cbb_permaffs_data_overlay;+ __int64 pcb$q_cbb_fill_10 [15];0 } pc 0@b$r_cbb_permaffs_compat_overlay;% } pcb$r_cbb_permaffs_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB pcb$r_cbb_saved_affinities; /* Embedded CBB block */N __struct { /* Compatability offset cells */* __int64 pcb$q_cbb_fill_1 1@1 [6]; __union {U unsigned int pcb$l_saved_affinities; /* Thread saved affinity mask */Y unsigned __int64 pcb$q_saved_affinities; /* Thread saved affinity mask */3 } pcb$r_cbb_savedaffs_data_overlay;+ __int64 pcb$q_cbb_fill_12 [15];1 } pcb$r_cbb_savedaffs_compat_overlay;& } pcb$r_cbb_savedaffs_overlay;N char pcb$t_terminal [16]; /* Terminal device name string */N/* for interactive jo2@bs */N char pcb$b_ktb_padding_5 [8]; /* Space for ktb fp_disabled action */Q unsigned int pcb$l_kt_deleted_thread_count; /* Deleted kernel thread count */N char pcb$b_ktb_padding_6 [12]; /* Alignment space */U unsigned __int64 pcb$q_kernel_counter_frac; /* Fractional tick for kernel mode */Q unsigned __int64 pcb$q_exec_counter_frac; /* Fractional tick for exec mode */S unsigned __int64 pcb$q_super3@_counter_frac; /* Fractional tick for super mode */Q unsigned __int64 pcb$q_user_counter_frac; /* Fractional tick for user mode */N char pcb$b_ktb_padding_7 [16]; /* pad to match KTB */N char pcb$b_ktb_padding_8 [32]; /* pad to match KTB */ int pcb$l_kt_limit;^ int pcb$l_spare; /* Pad to quadword; available for either KTB or PCB */R char pcb$b_ktb_padding_10 [8]; /* pad to match KTB$PQ_POWER_ACCOUNTING */N 4@ char pcb$t_align2 [96]; /* Assure 128 byte alignment */# char pcb$b_ktb_padding_12 [48]; } PCB; #if !defined(__VAXC)H#define pcb$q_lefc_swapped pcb$r_lefc_overlay_swapped.pcb$q_lefc_swappedh#define pcb$l_lefc_0_swapped pcb$r_lefc_overlay_swapped.pcb$r_lefc_clusters_swapped.pcb$l_lefc_0_swappedh#define pcb$l_lefc_1_swapped pcb$r_lefc_overlay_swapped.pcb$r_lefc_clusters_swapped.pcb$l_lefc_1_swapped)#define pcb$l_sts pcb$r_fill_0_.pcb$l_sts7#define pcb$v_res pcb$ 5@r_fill_0_.pcb$r_fill_1_.pcb$v_res=#define pcb$v_delpen pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_delpen?#define pcb$v_forcpen pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_forcpen=#define pcb$v_inquan pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_inquan=#define pcb$v_pswapm pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_pswapm=#define pcb$v_respen pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_respen=#define pcb$v_ssfexc pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_ssfexc?#define pcb$v_ssfexce pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_ssfexce?#define pcb$v_ssfe 6@xcs pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_ssfexcs?#define pcb$v_ssfexcu pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_ssfexcu?#define pcb$v_ssrwait pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_ssrwait=#define pcb$v_suspen pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_suspen9#define pcb$v_wall pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_wall;#define pcb$v_batch pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_batch=#define pcb$v_noacnt pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_noacntC#define pcb$v_nosuspend pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_nosuspend=#defin 7@e pcb$v_astpen pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_astpen=#define pcb$v_phdres pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_phdres;#define pcb$v_hiber pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_hiber;#define pcb$v_login pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_login=#define pcb$v_netwrk pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_netwrk=#define pcb$v_pwrast pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_pwrast?#define pcb$v_nodelet pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_nodelet=#define pcb$v_disaws pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_disaws;#d8@efine pcb$v_inter pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_inter?#define pcb$v_recover pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_recover?#define pcb$v_hardaff pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_hardaff=#define pcb$v_erdact pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_erdactA#define pcb$v_softsusp pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_softsuspC#define pcb$v_preempted pcb$r_fill_0_.pcb$r_fill_1_.pcb$v_preempted+#define pcb$l_sts2 pcb$r_fill_2_.pcb$l_sts2O#define pcb$v_quantum_resched pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_qu9@antum_reschedc#define pcb$v_disable_preempt_pkta_lock pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_disable_preempt_pkta_lockA#define pcb$v_fredlock pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_fredlock?#define pcb$v_phdlock pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_phdlock7#define pcb$v_tcb pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_tcbS#define pcb$v_tbs_state_pending pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_tbs_state_pendingS#define pcb$v_ss_logging_enable pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_ss_logging_enableO#define pcb$v_ss_logging:@_perm pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_ss_logging_permU#define pcb$v_brk_rundown_loaded pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_brk_rundown_loadedQ#define pcb$v_class_sched_perm pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_class_sched_permG#define pcb$v_term_notify pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_term_notifyE#define pcb$v_bytlm_loan pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_bytlm_loanO#define pcb$v_disable_preempt pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_disable_preemptE#define pcb$v_nounshelve pcb$r_fill_2_.pcb$r_fil;@l_3_.pcb$v_nounshelveS#define pcb$v_shelving_reserved pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_shelving_reservedO#define pcb$v_class_scheduled pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_class_scheduledM#define pcb$v_class_supplied pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_class_suppliedI#define pcb$v_in_tbs_state pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_in_tbs_stateA#define pcb$v_windfall pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_windfall=#define pcb$v_notify pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_notifyO#define pcb$v_single_threa<@ded pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_single_threaded;#define pcb$v_rwast pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_rwastU#define pcb$v_soft_single_thread pcb$r_fill_2_.pcb$r_fill_3_.pcb$v_soft_single_threadG#define pcb$l_efc2p pcb$r_cefc_overlay.pcb$r_cefc_overlay_1.pcb$l_efc2pG#define pcb$l_efc3p pcb$r_cefc_overlay.pcb$r_cefc_overlay_1.pcb$l_efc3pM#define pcb$w_pgflchar pcb$r_cefc_overlay.pcb$r_cefc_overlay_2.pcb$w_pgflcharO#define pcb$b_pgflindex pcb$r_cefc_overlay.pcb$r_cefc_overlay_2.pcb$b_pg =@flindex+#define pcb$l_epid pcb$r_fill_4_.pcb$l_epidC#define pcb$v_epid_proc pcb$r_fill_4_.pcb$r_fill_5_.pcb$v_epid_procK#define pcb$v_epid_node_idx pcb$r_fill_4_.pcb$r_fill_5_.pcb$v_epid_node_idxK#define pcb$v_epid_node_seq pcb$r_fill_4_.pcb$r_fill_5_.pcb$v_epid_node_seqC#define pcb$v_epid_wild pcb$r_fill_4_.pcb$r_fill_5_.pcb$v_epid_wild*#define pcb$q_priv pcb$r_pcbarb.pcb$q_priv(#define pcb$l_arb pcb$r_pcbarb.pcb$l_arb6#define pcb$l_uic pcb$r_pcbarb.pcb$r_fill_6_.pcb$l_uicD#define pcb$>@w_mem pcb$r_pcbarb.pcb$r_fill_6_.pcb$r_fill_7_.pcb$w_memD#define pcb$w_grp pcb$r_pcbarb.pcb$r_fill_6_.pcb$r_fill_7_.pcb$w_grp3#define pcb$q_xscb_que pcb$r_fill_8_.pcb$q_xscb_queE#define pcb$a_xscb_flink pcb$r_fill_8_.pcb$r_fill_9_.pcb$a_xscb_flinkE#define pcb$a_xscb_blink pcb$r_fill_8_.pcb$r_fill_9_.pcb$a_xscb_blink4#define pcb$q_rmcb_que pcb$r_fill_10_.pcb$q_rmcb_queG#define pcb$a_rmcb_flink pcb$r_fill_10_.pcb$r_fill_11_.pcb$a_rmcb_flinkG#define pcb$a_rmcb_blink pcb$r_fill_10_.pcb$r_fill_1 ?@1_.pcb$a_rmcb_blink0#define pcb$q_cd_que pcb$r_fill_12_.pcb$q_cd_queC#define pcb$a_cd_flink pcb$r_fill_12_.pcb$r_fill_13_.pcb$a_cd_flinkC#define pcb$a_cd_blink pcb$r_fill_12_.pcb$r_fill_13_.pcb$a_cd_blink6#define pcb$l_psx_flags pcb$r_fill_14_.pcb$l_psx_flags;#define pcb$v_fork pcb$r_fill_14_.pcb$r_fill_15_.pcb$v_forkA#define pcb$l_frewsle_param pcb$r_pqb_overlay.pcb$l_frewsle_param-#define pcb$l_pqb pcb$r_pqb_overlay.pcb$l_pqb4#define pcb$q_rdpb_que pcb$r_fill_16_.pcb$q_rdpb_queG#defin@@e pcb$a_rdpb_flink pcb$r_fill_16_.pcb$r_fill_17_.pcb$a_rdpb_flinkG#define pcb$a_rdpb_blink pcb$r_fill_16_.pcb$r_fill_17_.pcb$a_rdpb_blink>#define pcb$l_thread_events pcb$r_fill_18_.pcb$l_thread_eventsM#define pcb$v_event_no_flag pcb$r_fill_18_.pcb$r_fill_19_.pcb$v_event_no_flag6#define pcb$q_postef pcb$r_postef_overlay.pcb$q_postefN#define pcb$l_postef1 pcb$r_postef_overlay.pcb$r_postef_clusters.pcb$l_postef1N#define pcb$l_postef2 pcb$r_postef_overlay.pcb$r_postef_clusters.pcb$l_postef2,#defA@ine pcb$l_sts3 pcb$r_fill_20_.pcb$l_sts3E#define pcb$v_in_delpag pcb$r_fill_20_.pcb$r_fill_21_.pcb$v_in_delpagA#define pcb$v_wakepen pcb$r_fill_20_.pcb$r_fill_21_.pcb$v_wakepenC#define pcb$v_secaudit pcb$r_fill_20_.pcb$r_fill_21_.pcb$v_secauditW#define pcb$v_upcall_ast_blocked pcb$r_fill_20_.pcb$r_fill_21_.pcb$v_upcall_ast_blockedB#define pcb$l_initial_ktb pcb$r_pcb_iktb_overlay.pcb$l_initial_ktb2#define pcb$l_pcb pcb$r_pcb_iktb_overlay.pcb$l_pcb6#define pcb$q_tqe_flags pcb$r_fill_22_.pcb$qB@_tqe_flags=#define pcb$l_timer pcb$r_fill_22_.pcb$r_fill_23_.pcb$l_timer?#define pcb$l_wakeup pcb$r_fill_22_.pcb$r_fill_23_.pcb$l_wakeup:#define pcb$l_image_flags pcb$r_fill_24_.pcb$l_image_flagsI#define pcb$v_sugid_image pcb$r_fill_24_.pcb$r_fill_25_.pcb$v_sugid_imageM#define pcb$v_sugid_process pcb$r_fill_24_.pcb$r_fill_25_.pcb$v_sugid_processV#define pcb$r_cbb_perm_cpu_affinity pcb$r_cbb_perm_overlay.pcb$r_cbb_perm_cpu_affinity#define pcb$l_permanent_cpu_affinity pcb$r_cbb_perm_overlay.C@pcb$r_cbb_perm_compat_overlay.pcb$r_cbb_perm_data_overlay.pcb$l_permane\nt_cpu_affinity#define pcb$q_permanent_cpu_affinity pcb$r_cbb_perm_overlay.pcb$r_cbb_perm_compat_overlay.pcb$r_cbb_perm_data_overlay.pcb$q_permane\nt_cpu_affinityV#define pcb$r_cbb_current_affinity pcb$r_cbb_curaff_overlay.pcb$r_cbb_current_affinity#define pcb$l_current_affinity pcb$r_cbb_curaff_overlay.pcb$r_cbb_curaff_compat_overlay.pcb$r_cbb_curraff_data_overlay.pcb$l_curren\ t_affinity#define pcb$q_current_affiniD@ty pcb$r_cbb_curaff_overlay.pcb$r_cbb_curaff_compat_overlay.pcb$r_cbb_curraff_data_overlay.pcb$q_curren\ t_affinityL#define pcb$r_cbb_active_cpus pcb$r_cbb_actcpu_overlay.pcb$r_cbb_active_cpus#define pcb$l_active_cpus pcb$r_cbb_actcpu_overlay.pcb$r_cbb_actcpu_compat_overlay.pcb$r_cbb_actcpu_data_overlay.pcb$l_active_cpus#define pcb$q_active_cpus pcb$r_cbb_actcpu_overlay.pcb$r_cbb_actcpu_compat_overlay.pcb$r_cbb_actcpu_data_overlay.pcb$q_active_cpusH#define pcb$r_cbb_affinities pcb$r_cbb_affs_ovE@erlay.pcb$r_cbb_affinitiesz#define pcb$l_affinities pcb$r_cbb_affs_overlay.pcb$r_cbb_affs_compat_overlay.pcb$r_cbb_affs_data_overlay.pcb$l_affinitiesz#define pcb$q_affinities pcb$r_cbb_affs_overlay.pcb$r_cbb_affs_compat_overlay.pcb$r_cbb_affs_data_overlay.pcb$q_affinities`#define pcb$r_cbb_permanent_affinities pcb$r_cbb_permaffs_overlay.pcb$r_cbb_permanent_affinities#define pcb$l_permanent_affinities pcb$r_cbb_permaffs_overlay.pcb$r_cbb_permaffs_compat_overlay.pcb$r_cbb_permaffs_data_overlay.pcb\F@$l_permanent_affinities#define pcb$q_permanent_affinities pcb$r_cbb_permaffs_overlay.pcb$r_cbb_permaffs_compat_overlay.pcb$r_cbb_permaffs_data_overlay.pcb\$q_permanent_affinitiesY#define pcb$r_cbb_saved_affinities pcb$r_cbb_savedaffs_overlay.pcb$r_cbb_saved_affinities#define pcb$l_saved_affinities pcb$r_cbb_savedaffs_overlay.pcb$r_cbb_savedaffs_compat_overlay.pcb$r_cbb_savedaffs_data_overlay.pcb$\l_saved_affinities#define pcb$q_saved_affinities pcb$r_cbb_savedaffs_overlay.pcb$r_cbb_sav G@edaffs_compat_overlay.pcb$r_cbb_savedaffs_data_overlay.pcb$\q_saved_affinities"#endif /* #if !defined(__VAXC) */ N#define PCB$K_LENGTH 2352 /* Length of PCB */N#define PCB$C_LENGTH 2352 /* Length of PCB */N#define PCB$S_PCBDEF 2352 /* Old PCB size for compatibility */#define KTB$M_RES 0x1#define KTB$M_DELPEN 0x2#define KTB$M_FORCPEN 0x4#define KTB$M_INQUAN 0x8#define KTB$M_PSWAPM 0x10#define KTB$H@M_RESPEN 0x20#define KTB$M_SSFEXC 0x40#define KTB$M_SSFEXCE 0x80#define KTB$M_SSFEXCS 0x100#define KTB$M_SSFEXCU 0x200#define KTB$M_SSRWAIT 0x400#define KTB$M_SUSPEN 0x800#define KTB$M_WALL 0x2000#define KTB$M_BATCH 0x4000#define KTB$M_NOACNT 0x8000#define KTB$M_NOSUSPEND 0x10000#define KTB$M_ASTPEN 0x20000#define KTB$M_PHDRES 0x40000#define KTB$M_HIBER 0x80000#define KTB$M_LOGIN 0x100000#define KTB$M_NETWRK 0x200000#define KTB$M_PWRAST 0x400000#define KTB$I@M_NODELET 0x800000#define KTB$M_DISAWS 0x1000000#define KTB$M_INTER 0x2000000#define KTB$M_RECOVER 0x4000000 #define KTB$M_HARDAFF 0x10000000#define KTB$M_ERDACT 0x20000000!#define KTB$M_SOFTSUSP 0x40000000"#define KTB$M_PREEMPTED 0x80000000!#define KTB$M_QUANTUM_RESCHED 0x1#define KTB$M_PHDLOCK 0x8#define KTB$M_TCB 0x10$#define KTB$M_TBS_STATE_PENDING 0x20%#define KTB$M_CLASS_SCHED_PERM 0x8000!#define KTB$M_TERM_NOTIFY 0x10000 #define KTB$M_BYTLM_LOAN 0x20000 #define KTB$ J@M_NOUNSHELVE 0x80000(#define KTB$M_SHELVING_RESERVED 0x100000&#define KTB$M_CLASS_SCHEDULED 0x200000%#define KTB$M_CLASS_SUPPLIED 0x400000##define KTB$M_IN_TBS_STATE 0x800000 #define KTB$M_WINDFALL 0x1000000#define KTB$M_NOTIFY 0x2000000(#define KTB$M_SINGLE_THREADED 0x3C000000"#define KTB$M_EPID_WILD 0x80000000N#define KTB$K_SCHED_OTHER 0 /* Native VMS policy (MBZ) */N#define KTB$K_SCHED_FIFO 1 /* POSIX FIFO policy */N#define KTB$K_SCHED_ K@RR 2 /* POSIX Round-Robbin policy */N/* [1..10] for POSIX */N#define KTB$K_SCHED_POLICY_CNT 3 /* # legal sched policies */#define KTB$M_WAKEPEN 0x1000 #define KTB$M_SECAUDIT 0x8000000+#define KTB$M_UPCALL_AST_BLOCKED 0x80000000 #define KTB$M_DELETE_PENDING 0x1%#define KTB$M_SCHED_CONTEXT_SAVED 0x2$#define KTB$M_SINGLE_THREAD_ACT 0x3C#define KTB$M_TOLERANT 0x40$#define KTB$M_SOFT_RAD_AFFINITY 0xL@80  9#ifdef __cplusplus /* Define structure prototypes */ struct _acb; struct _phd; struct _jib; struct _psb; struct _fred; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ktb {#pragma __nomember_alignmentN struct _ktb *ktb$l_sqfl; /* State queue forward link */NM@ struct _ktb *ktb$l_sqbl; /* State queue backward link */N unsigned short int ktb$w_size; /* Size, in bytes */N unsigned char ktb$b_type; /* Structure type code for KTB */ unsigned char ktb$b_fill_1;N unsigned int ktb$l_ast_pending; /* AST pending mask */N unsigned __int64 ktb$q_phypcb; /* Physical address of HWPCB */N char ktb$b_pcb_padding_1 [8]; /* pad to match PCB N@ */[ struct _acb *ktb$l_astqfl_spk; /* Special kernel AST queue forward link (head) */X struct _acb *ktb$l_astqbl_spk; /* Special kernel AST queue back link (tail) */R struct _acb *ktb$l_astqfl_k; /* Kernel AST queue forward link (head) */O struct _acb *ktb$l_astqbl_k; /* Kernel AST queue back link (tail) */U struct _acb *ktb$l_astqfl_e; /* Executive AST queue forward link (head) */R struct _acb *ktb$l_astqbl_e; /* Executive AST queO@ue back link (tail) */V struct _acb *ktb$l_astqfl_s; /* Supervisor AST queue forward link (head) */S struct _acb *ktb$l_astqbl_s; /* Supervisor AST queue back link (tail) */P struct _acb *ktb$l_astqfl_u; /* User AST queue forward link (head) */N struct _acb *ktb$l_astqbl_u; /* User AST queue back link (tail) */N char ktb$b_pcb_padding_2 [4]; /* pad to match PCB */T int ktb$l_cpu_id; /* Current CPU (last one tP@o load context) */N char ktb$b_pcb_padding_3 [24]; /* pad to match PCB */N unsigned int ktb$l_astact; /* Access modes with active ASTs */N unsigned int ktb$l_state; /* Process state */K unsigned int ktb$l_pri; /* Process current priority */N unsigned int ktb$l_prib; /* Base priority */N unsigned int ktb$l_affinity_skip; /* Affinity skip count */N unsiQ@gned int ktb$l_owner; /* PID of creator */ __union {N unsigned int ktb$l_sts; /* Process status flags */ __struct {N unsigned ktb$v_res : 1; /* Resident, in balance set */N unsigned ktb$v_delpen : 1; /* Delete pending */N unsigned ktb$v_forcpen : 1; /* Force exit pending */N unsigned ktb$v_inquan : 1; /* Initial quantum in progress R@*/N unsigned ktb$v_pswapm : 1; /* Process swap mode, 1=NOSWAP */N unsigned ktb$v_respen : 1; /* Resume pending, skip suspend */R unsigned ktb$v_ssfexc : 1; /* System service exception enable (K) */R unsigned ktb$v_ssfexce : 1; /* System service exception enable (E) */R unsigned ktb$v_ssfexcs : 1; /* System service exception enable (S) */R unsigned ktb$v_ssfexcu : 1; /* System service exception enable (U) */S S@ unsigned ktb$v_ssrwait : 1; /* System service resource wait disable */N unsigned ktb$v_suspen : 1; /* Suspend pending */W unsigned ktb$v_reserved_1 : 1; /* reserved bit, overlays WAKEPEN in STS3 */N unsigned ktb$v_wall : 1; /* Wait for all events in mask */N unsigned ktb$v_batch : 1; /* Process is a batch job */N unsigned ktb$v_noacnt : 1; /* No accounting for process */N unsiT@gned ktb$v_nosuspend : 1; /* Process cannot be suspended */N unsigned ktb$v_astpen : 1; /* AST pending */N unsigned ktb$v_phdres : 1; /* Process header resident */U unsigned ktb$v_hiber : 1; /* Hibernate after initial image activate */N unsigned ktb$v_login : 1; /* Login without reading UAF */N unsigned ktb$v_netwrk : 1; /* Network connect job */N unsigned ktb$v_pwrast U@: 1; /* Power fail AST */N unsigned ktb$v_nodelet : 1; /* No delete */N unsigned ktb$v_disaws : 1; /* Disable automatic WS adjustment */N unsigned ktb$v_inter : 1; /* Process is an interactive job */N unsigned ktb$v_recover : 1; /* Process can recover locks */X unsigned ktb$v_reserved_4 : 1; /* reserved bit, overlays SECAUDIT in STS3 */P unsigned ktb$v_hardaff : 1; /* Process V@ is bound to particular CPU */N unsigned ktb$v_erdact : 1; /* Exec mode rundown active */N unsigned ktb$v_softsusp : 1; /* Process is in "soft" suspend */O unsigned ktb$v_preempted : 1; /* Hard suspend has preempted soft */ } ktb$r_fill_31_; } ktb$r_fill_30_; __union {N unsigned int ktb$l_sts2; /* Process status flags (2nd LW) */ __struct {Y unsigned ktb$v_quantum_resched : 1; /* QuaW@ntum-oriented process reschedule */& unsigned ktb$v_fill_2 : 2;Y unsigned ktb$v_phdlock : 1; /* Don't swap PHD -- process has $LCKPAG pages */N unsigned ktb$v_tcb : 1; /* TCB process */^ unsigned ktb$v_tbs_state_pending : 1; /* Going to TBS, but not on the queue yet */& unsigned ktb$v_fill_3 : 9;d unsigned ktb$v_class_sched_perm : 1; /* process is part of permanent scheduling class */N unsignX@ed ktb$v_term_notify : 1; /* termination notification */Y unsigned ktb$v_bytlm_loan : 1; /* Process has received rundown BYTLIM loan */& unsigned ktb$v_fill_4 : 1;N unsigned ktb$v_nounshelve : 1; /* if set, don't auto-unshelve */V unsigned ktb$v_shelving_reserved : 1; /* Reserved for shelving facility */U unsigned ktb$v_class_scheduled : 1; /* This process is class scheduled */\ unsigned ktb$v_class_supplied : 1; /* This pY@rocess has been assigned a class, */N/* or an explicit "No class" (happens only */N/* when CLASS_SCHEDULED is cleared) */O unsigned ktb$v_in_tbs_state : 1; /* This process is in TBS state */N unsigned ktb$v_windfall : 1; /* Process eligible for windfall */R unsigned ktb$v_notify : 1; /* Send process termination msg. to CSP */V unsigned ktb$v_single_threaded : 4; /* single thre Z@aded bits, 1 per mode */( unsigned ktb$v_fill_48_ : 2; } ktb$r_fill_33_; } ktb$r_fill_32_;I unsigned int ktb$l_prisav; /* Saved current priority */F unsigned int ktb$l_pribsav; /* Saved base priority */N unsigned int ktb$l_authpri; /* Initial process priority */U unsigned int ktb$l_onqtime; /* Abs time when placed on COM/COMO queue, */N/* adjusted for process wait time [@ */N unsigned int ktb$l_waitime; /* Abs time of last process event */N char ktb$b_pcb_padding_4 [32]; /* pad to match PCB */N unsigned int ktb$l_wefc; /* Waiting EF cluster number */N unsigned int ktb$l_efwm; /* Event flag wait mask */N char ktb$b_pcb_padding_5 [16]; /* pad to match PCB */X unsigned int ktb$l_pid; /* Process ID used by exec on local node only */\@N/* */Z/**** WARNING - THE INTERNAL STRUCTURE OF THE EPID IS SUBJECT TO RADICAL CHANGE BETWEEN */X/**** VERSIONS OF VMS. NO ASSUMPTIONS SHOULD EVER BE MADE ABOUT ITS FORMAT */N/* */ __union {W unsigned int ktb$l_epid; /* Cluster-wide process ID seen by the world */ __struct {[ unsigned ktb$v_epid_pr]@oc : 21; /* Process ID field, can convert to KTB$l_pid */` unsigned ktb$v_epid_node_idx : 8; /* IDX - index to table of node identifications */d unsigned ktb$v_epid_node_seq : 2; /* SEQ - sequence number for node table entry reuse */` unsigned ktb$v_epid_wild : 1; /* Flag that EPID is wildcard context for $GETJPI, */ } ktb$r_fill_35_; } ktb$r_fill_34_;N/* and not a valid EPID */N char^@ ktb$b_pcb_padding_6 [8]; /* pad to match PCB */N unsigned int ktb$l_mtxcnt; /* Count of mutex semaphores owned */N char ktb$b_pcb_padding_7 [16]; /* pad to match PCB */N struct _phd *ktb$l_phd; /* Address of Process Header */O struct _jib *ktb$l_jib; /* Address of Job Information Block */N char ktb$b_pcb_padding_8 [132]; /* pad to match PCB */Q unsigned int ktb$l_home_rad;_@ /* Which RAD is most of our memory in? */n unsigned int ktb$l_sra_skip_count; /* How many times has KT been skipped because of soft RAD affinity? */N char ktb$b_pcb_padding_81 [12]; /* pad to match PCB */N int ktb$l_affinity; /* CPU ID for affinity */N unsigned int ktb$l_capability; /* CPU capability selection bitmask */N char ktb$b_pcb_padding_9 [32]; /* pad to match PCB */N unsigned int ktb$l`@_permanent_capability; /* Permanent capability mask */W int ktb$l_cbb_reserved_1; /* $l_permanent_cpu_affinity moves to bottom */N char ktb$b_pcb_padding_10 [8]; /* pad to match PCB */Q int ktb$l_cbb_reserved_2; /* $l_current_affinity moves to bottom */N int ktb$l_capability_seq; /* Copy of last sequence number */N char ktb$b_pcb_padding_11 [8]; /* pad to match PCB */N unsigned int ktb$l_ast_blockeda@; /* AST blocked bits */V void *ktb$l_class_quant; /* Address of cell containing class quantum */g unsigned short int ktb$w_class_extra_ticks; /* If class scheduled, extra ticks given to this KTB */N char ktb$b_pcb_padding_12 [94]; /* pad to match PCB */N unsigned int ktb$l_sched_policy; /* POSIX sched policy */N char ktb$b_pcb_padding_13 [160]; /* pad to match PCB */ __union {N unb@signed int ktb$l_sts3; /* Process status flags */ __struct {\ unsigned ktb$v_reserved_2 : 12; /* Reserved bits, overlays with fields in STS */N unsigned ktb$v_wakepen : 1; /* Wake pending, skip hibernate */\ unsigned ktb$v_reserved_3 : 14; /* Reserved bits, overlays with fields in STS */R unsigned ktb$v_secaudit : 1; /* Mandatory security auditing enabled */[ unsigned ktb$v_reserved_5 : 3; /* Reserved bits, o c@verlays with fields in STS */_ unsigned ktb$v_upcall_ast_blocked : 1; /* indicates that upcall ASTs are blocked */ } ktb$r_fill_37_; } ktb$r_fill_36_; __union {N struct _pcb *ktb$l_pcb; /* PCB, overlays PCB$L_INITIAL_KTB */N struct _ktb *ktb$l_initial_ktb; /* Initial KTB, overlays KTB$L_PCB */! } ktb$r_pcb_iktb_overlay; __union {N unsigned int ktb$l_flags; /* Kernel thread flags */ d@__struct {S unsigned ktb$v_delete_pending : 1; /* Delete pending */P unsigned ktb$v_sched_context_saved : 1; /* Saved scheduling state */] unsigned ktb$v_single_thread_act : 4; /* single thread active bits, 1 per mode */\ unsigned ktb$v_tolerant : 1; /* Thread is executing a tolerant system service */b unsigned ktb$v_soft_rad_affinity : 1; /* Soft RAD affinity is in effect for this KT */ } ktb$r_fill_39_; e@ } ktb$r_fill_38_;N char ktb$b_pcb_padding_18 [4]; /* pad to match PCB */N void *ktb$l_per_kt_area; /* Address of kthread p1 area */N struct _acb *ktb$l_tquant_acb; /* Tquantum upcall ACB */O unsigned int ktb$l_tquant; /* Remaining per user thread quantum */Q unsigned int ktb$l_quant; /* Remaining per kernel thread quantum */N void *ktb$l_tm_callbacks; /* Address of callback vector f@ */N unsigned int ktb$l_callback_err; /* Error bits if callback fails */ char ktb$b_fill_49_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentU unsigned __int64 ktb$q_capabilities; /* Thread capabilities and affinities */ __struct {Y unsigned int ktb$l_capabilities; g@ /* Thread system and user capability mask */N int ktb$l_cbb_reserved_4; /* $l_affinities moves to bottom */ } ktb$r_fill_41_; } ktb$r_fill_40_; __union {i unsigned __int64 ktb$q_permanent_capabilities; /* Thread permanent capabilities and affinities */ __struct {m unsigned int ktb$l_permanent_capabilities; /* Thread permanent system and user capability mask */U int ktb$l_cbb_reserved_5; /* $l_permanent_affi h@nities moves to bottom */ } ktb$r_fill_43_; } ktb$r_fill_42_; __union {[ unsigned __int64 ktb$q_saved_capabilities; /* Thread capabilities and affinities */ __struct {_ unsigned int ktb$l_saved_capabilities; /* Thread system and user capability mask */Q int ktb$l_cbb_reserved_6; /* $l_saved_affinities moves to bottom */ } ktb$r_fill_45_; } ktb$r_fill_44_;N unsigned int ktb$l_bias_cell; /* Ii@mplicit affinity CPU bias */N unsigned int ktb$l_persona_id; /* Unique Persona Identifier */N struct _psb *ktb$ar_psb; /* Pointer to active Persona */N unsigned int ktb$l_swp_seq; /* Current swapper's sequence */W __int64 ktb$q_vol_waits; /* # of voluntary waits over a specific time */] int ktb$l_curr_vol_waits; /* current # of voluntary waits (...and counting) */N int ktb$l_qend_count; /* #j@ of quantum ends incurred */Z unsigned __int64 ktb$q_comq_wait; /* SCC at the time the thread was placed on the */N/* COM queue */X unsigned __int64 ktb$q_runtime_start; /* SCC at time thread placed into execution */^ unsigned __int64 ktb$q_inttime_start; /* current # of interrupt ticks (hard ticks) when */N/* thread placed into execution */V int ktb$l_soft_broken; k@ /* # of times soft affinity has been broken */N char ktb$b_pcb_padding_14 [20]; /* pad to match PCB */N unsigned __int64 ktb$q_acc_run; /* Accumulated run time. */N unsigned __int64 ktb$q_acc_wait; /* Accumulated wait time. */N unsigned __int64 ktb$q_acc_interrupt; /* Accumulated interrupt time. */N int ktb$l_run_count; /* # of times run on this s.a. CPU. */N unsigned int ktb$l_glock_wait_status; /* Statul@s of glock wait */N unsigned __int64 ktb$q_glock; /* Galaxy lock handle */N char ktb$b_pcb_padding_15 [16]; /* pad to match PCB */N unsigned int ktb$l_lckrq; /* pointer to LCKRQ packet */N unsigned int ktb$l_comq_head; /* If in COM, what queue are we in? */X unsigned __int64 ktb$q_sched_count; /* How many times has this KTB been scheduled */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenev m@er ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _fred *ktb$q_fred; /* Address of FRED block */#else unsigned __int64 ktb$q_fred;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _fred *ktb$q_virpcb; /* VA of HWPCB n@*/#else unsigned __int64 ktb$q_virpcb;#endif } ktb$r_fred_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN unsigned __int64 ktb$q_tqe_flags; /* TQE flags */ __struct {N unsigned int ktb$l_timer; /* Timer Request info */N o@ unsigned int ktb$l_wakeup; /* Wakeup Call info */ } ktb$r_fill_47_; } ktb$r_fill_46_;N char ktb$b_pcb_padding_16 [28]; /* pad to match PCB */ char ktb$b_fill_50_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB ktb$r_cbb_ p@perm_cpu_affinity; /* Embedded CBB block */N __struct { /* Compatability offset cells */) __int64 ktb$q_cbb_fill_1 [6]; __union {W unsigned int ktb$l_permanent_cpu_affinity; /* Permanent CPU affinity */[ unsigned __int64 ktb$q_permanent_cpu_affinity; /* Permanent CPU affinity */. } ktb$r_cbb_perm_data_overlay;* __int64 ktb$q_cbb_fill_2 [15];, } ktb$r_cbb_ q@perm_compat_overlay;! } ktb$r_cbb_perm_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB ktb$r_cbb_current_affinity; /* Embedded CBB block */N __struct { /* Compatability offset cells */) __int64 ktb$q_cbb_fill_3 [6]; r@ __union {N unsigned int ktb$l_current_affinity; /* Current CPU mask */O unsigned __int64 ktb$q_current_affinity; /* Current CPU mask */1 } ktb$r_cbb_curraff_data_overlay;* __int64 ktb$q_cbb_fill_4 [15];. } ktb$r_cbb_curaff_compat_overlay;# } ktb$r_cbb_curaff_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#e s@lse#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB ktb$r_cbb_active_cpus; /* Embedded CBB block */N __struct { /* Compatability offset cells */) __int64 ktb$q_cbb_fill_5 [6]; __union {P unsigned int ktb$l_active_cpus; /* CPUs owned by this process */T unsigned __int64 ktb$q_active_cpus; /* CPUs owned by this process */0 } kt t@b$r_cbb_actcpu_data_overlay;* __int64 ktb$q_cbb_fill_6 [15];. } ktb$r_cbb_actcpu_compat_overlay;# } ktb$r_cbb_actcpu_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB ktb$r_cbb_affinities; /* Embedded CBB block */N __struct { u@ /* Compatability offset cells */) __int64 ktb$q_cbb_fill_7 [6]; __union {N unsigned int ktb$l_affinities; /* Thread affinity mask */N unsigned __int64 ktb$q_affinities; /* Thread affinity mask */. } ktb$r_cbb_affs_data_overlay;* __int64 ktb$q_cbb_fill_8 [15];, } ktb$r_cbb_affs_compat_overlay;! } ktb$r_cbb_affs_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cpl v@usplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN CBB ktb$r_cbb_permanent_affinities; /* Embedded CBB block */N __struct { /* Compatability offset cells */) __int64 ktb$q_cbb_fill_9 [6]; __union {] unsigned int ktb$l_permanent_affinities; /* Thread permanent affinity mask */a w@ unsigned __int64 ktb$q_permanent_affinities; /* Thread permanent affinity mask */2 } ktb$r_cbb_permaffs_data_overlay;+ __int64 ktb$q_cbb_fill_10 [15];0 } ktb$r_cbb_permaffs_compat_overlay;% } ktb$r_cbb_permaffs_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __no x@member_alignmentN CBB ktb$r_cbb_saved_affinities; /* Embedded CBB block */N __struct { /* Compatability offset cells */* __int64 ktb$q_cbb_fill_11 [6]; __union {U unsigned int ktb$l_saved_affinities; /* Thread saved affinity mask */Y unsigned __int64 ktb$q_saved_affinities; /* Thread saved affinity mask */3 } ktb$r_cbb_savedaffs_data_overlay;+ __int64 ktb$q_ y@cbb_fill_12 [15];1 } ktb$r_cbb_savedaffs_compat_overlay;& } ktb$r_cbb_savedaffs_overlay;N char ktb$b_pcb_padding_17 [16]; /* pad to match PCB */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Y void *ktb$pq_fp_disabled_action; /* If we get float disabled fault, what to do? */#else, unsigned __int64 ktb$pq_fp_disabled_a z@ction;#endifN char ktb$b_pcb_padding_19 [16]; /* pad to match PCB */N char ktb$b_pcb_padding_20 [32]; /* pad to match PCB */P unsigned int ktb$l_kt_kernel_counter; /* Per-kthread kernel mode counters */N unsigned int ktb$l_kt_exec_counter; /* Per-kthread exec mode counters */N unsigned int ktb$l_kt_super_counter; /* Per-kthread super mode counters */N unsigned int ktb$l_kt_user_counter; /* Per-kthread user mode counters */X unsi{@gned __int64 ktb$q_kt_kernel_counter_frac; /* Fractional tick for kernel mode */T unsigned __int64 ktb$q_kt_exec_counter_frac; /* Fractional tick for exec mode */V unsigned __int64 ktb$q_kt_super_counter_frac; /* Fractional tick for super mode */T unsigned __int64 ktb$q_kt_user_counter_frac; /* Fractional tick for user mode */T char ktb$b_pcb_padding_21 [4]; /* for PCB$L_KT_LIMIT and pad to quadword */N unsigned int ktb$l_spare; /* Available for either KTB or PCB */ |@R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */R void *ktb$pq_power_accounting; /* Power/performance accounting pointer */#else* unsigned __int64 ktb$pq_power_accounting;#endifN char ktb$t_align2 [96]; /* Assure 128 byte alignment */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#p}@ragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif" char ktb$l_def_sched_fkb [48]; } KTB; #if !defined(__VAXC)*#define ktb$l_sts ktb$r_fill_30_.ktb$l_sts9#define ktb$v_res ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_res?#define ktb$v_delpen ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_delpenA#define ktb$v_forcpen ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_forcpen?#define ktb$v_inquan ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_inquan?#define ktb$v_pswapm ktb$r_fill_30_.ktb$r_ ~@fill_31_.ktb$v_pswapm?#define ktb$v_respen ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_respen?#define ktb$v_ssfexc ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_ssfexcA#define ktb$v_ssfexce ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_ssfexceA#define ktb$v_ssfexcs ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_ssfexcsA#define ktb$v_ssfexcu ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_ssfexcuA#define ktb$v_ssrwait ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_ssrwait?#define ktb$v_suspen ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_suspen;#define ktb$@v_wall ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_wall=#define ktb$v_batch ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_batch?#define ktb$v_noacnt ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_noacntE#define ktb$v_nosuspend ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_nosuspend?#define ktb$v_astpen ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_astpen?#define ktb$v_phdres ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_phdres=#define ktb$v_hiber ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_hiber=#define ktb$v_login ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_lo @gin?#define ktb$v_netwrk ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_netwrk?#define ktb$v_pwrast ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_pwrastA#define ktb$v_nodelet ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_nodelet?#define ktb$v_disaws ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_disaws=#define ktb$v_inter ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_interA#define ktb$v_recover ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_recoverA#define ktb$v_hardaff ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_hardaff?#define ktb$v_erdact ktb$r_fill_30@_.ktb$r_fill_31_.ktb$v_erdactC#define ktb$v_softsusp ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_softsuspE#define ktb$v_preempted ktb$r_fill_30_.ktb$r_fill_31_.ktb$v_preempted,#define ktb$l_sts2 ktb$r_fill_32_.ktb$l_sts2Q#define ktb$v_quantum_resched ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_quantum_reschedA#define ktb$v_phdlock ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_phdlock9#define ktb$v_tcb ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_tcbU#define ktb$v_tbs_state_pending ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_tbs_st@ate_pendingS#define ktb$v_class_sched_perm ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_class_sched_permI#define ktb$v_term_notify ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_term_notifyG#define ktb$v_bytlm_loan ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_bytlm_loanG#define ktb$v_nounshelve ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_nounshelveU#define ktb$v_shelving_reserved ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_shelving_reservedQ#define ktb$v_class_scheduled ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_class_scheduledO#define kt@b$v_class_supplied ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_class_suppliedK#define ktb$v_in_tbs_state ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_in_tbs_stateC#define ktb$v_windfall ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_windfall?#define ktb$v_notify ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_notifyQ#define ktb$v_single_threaded ktb$r_fill_32_.ktb$r_fill_33_.ktb$v_single_threaded,#define ktb$l_epid ktb$r_fill_34_.ktb$l_epidE#define ktb$v_epid_proc ktb$r_fill_34_.ktb$r_fill_35_.ktb$v_epid_procM#define ktb$v_epid@_node_idx ktb$r_fill_34_.ktb$r_fill_35_.ktb$v_epid_node_idxM#define ktb$v_epid_node_seq ktb$r_fill_34_.ktb$r_fill_35_.ktb$v_epid_node_seqE#define ktb$v_epid_wild ktb$r_fill_34_.ktb$r_fill_35_.ktb$v_epid_wild,#define ktb$l_sts3 ktb$r_fill_36_.ktb$l_sts3A#define ktb$v_wakepen ktb$r_fill_36_.ktb$r_fill_37_.ktb$v_wakepenC#define ktb$v_secaudit ktb$r_fill_36_.ktb$r_fill_37_.ktb$v_secauditW#define ktb$v_upcall_ast_blocked ktb$r_fill_36_.ktb$r_fill_37_.ktb$v_upcall_ast_blocked2#define ktb$l_pcb @ktb$r_pcb_iktb_overlay.ktb$l_pcbB#define ktb$l_initial_ktb ktb$r_pcb_iktb_overlay.ktb$l_initial_ktb.#define ktb$l_flags ktb$r_fill_38_.ktb$l_flagsO#define ktb$v_delete_pending ktb$r_fill_38_.ktb$r_fill_39_.ktb$v_delete_pendingY#define ktb$v_sched_context_saved ktb$r_fill_38_.ktb$r_fill_39_.ktb$v_sched_context_savedU#define ktb$v_single_thread_act ktb$r_fill_38_.ktb$r_fill_39_.ktb$v_single_thread_actC#define ktb$v_tolerant ktb$r_fill_38_.ktb$r_fill_39_.ktb$v_tolerantU#define ktb$v_soft_rad_a@ffinity ktb$r_fill_38_.ktb$r_fill_39_.ktb$v_soft_rad_affinity<#define ktb$q_capabilities ktb$r_fill_40_.ktb$q_capabilitiesK#define ktb$l_capabilities ktb$r_fill_40_.ktb$r_fill_41_.ktb$l_capabilitiesP#define ktb$q_permanent_capabilities ktb$r_fill_42_.ktb$q_permanent_capabilities_#define ktb$l_permanent_capabilities ktb$r_fill_42_.ktb$r_fill_43_.ktb$l_permanent_capabilitiesH#define ktb$q_saved_capabilities ktb$r_fill_44_.ktb$q_saved_capabilitiesW#define ktb$l_saved_capabilities ktb$r_fill_44_.@ktb$r_fill_45_.ktb$l_saved_capabilities0#define ktb$q_fred ktb$r_fred_overlay.ktb$q_fred4#define ktb$q_virpcb ktb$r_fred_overlay.ktb$q_virpcb6#define ktb$q_tqe_flags ktb$r_fill_46_.ktb$q_tqe_flags=#define ktb$l_timer ktb$r_fill_46_.ktb$r_fill_47_.ktb$l_timer?#define ktb$l_wakeup ktb$r_fill_46_.ktb$r_fill_47_.ktb$l_wakeupV#define ktb$r_cbb_perm_cpu_affinity ktb$r_cbb_perm_overlay.ktb$r_cbb_perm_cpu_affinity#define ktb$l_permanent_cpu_affinity ktb$r_cbb_perm_overlay.ktb$r_cbb_perm_compat_over@lay.ktb$r_cbb_perm_data_overlay.ktb$l_permane\nt_cpu_affinity#define ktb$q_permanent_cpu_affinity ktb$r_cbb_perm_overlay.ktb$r_cbb_perm_compat_overlay.ktb$r_cbb_perm_data_overlay.ktb$q_permane\nt_cpu_affinityV#define ktb$r_cbb_current_affinity ktb$r_cbb_curaff_overlay.ktb$r_cbb_current_affinity#define ktb$l_current_affinity ktb$r_cbb_curaff_overlay.ktb$r_cbb_curaff_compat_overlay.ktb$r_cbb_curraff_data_overlay.ktb$l_curren\ t_affinity#define ktb$q_current_affinity ktb$r_cbb_curaff_overla@y.ktb$r_cbb_curaff_compat_overlay.ktb$r_cbb_curraff_data_overlay.ktb$q_curren\ t_affinityL#define ktb$r_cbb_active_cpus ktb$r_cbb_actcpu_overlay.ktb$r_cbb_active_cpus#define ktb$l_active_cpus ktb$r_cbb_actcpu_overlay.ktb$r_cbb_actcpu_compat_overlay.ktb$r_cbb_actcpu_data_overlay.ktb$l_active_cpus#define ktb$q_active_cpus ktb$r_cbb_actcpu_overlay.ktb$r_cbb_actcpu_compat_overlay.ktb$r_cbb_actcpu_data_overlay.ktb$q_active_cpusH#define ktb$r_cbb_affinities ktb$r_cbb_affs_overlay.ktb$r_cbb_affinities@z#define ktb$l_affinities ktb$r_cbb_affs_overlay.ktb$r_cbb_affs_compat_overlay.ktb$r_cbb_affs_data_overlay.ktb$l_affinitiesz#define ktb$q_affinities ktb$r_cbb_affs_overlay.ktb$r_cbb_affs_compat_overlay.ktb$r_cbb_affs_data_overlay.ktb$q_affinities`#define ktb$r_cbb_permanent_affinities ktb$r_cbb_permaffs_overlay.ktb$r_cbb_permanent_affinities#define ktb$l_permanent_affinities ktb$r_cbb_permaffs_overlay.ktb$r_cbb_permaffs_compat_overlay.ktb$r_cbb_permaffs_data_overlay.ktb\$l_permanent_affinities@#define ktb$q_permanent_affinities ktb$r_cbb_permaffs_overlay.ktb$r_cbb_permaffs_compat_overlay.ktb$r_cbb_permaffs_data_overlay.ktb\$q_permanent_affinitiesY#define ktb$r_cbb_saved_affinities ktb$r_cbb_savedaffs_overlay.ktb$r_cbb_saved_affinities#define ktb$l_saved_affinities ktb$r_cbb_savedaffs_overlay.ktb$r_cbb_savedaffs_compat_overlay.ktb$r_cbb_savedaffs_data_overlay.ktb$\l_saved_affinities#define ktb$q_saved_affinities ktb$r_cbb_savedaffs_overlay.ktb$r_cbb_savedaffs_compat_overlay.ktb$ @r_cbb_savedaffs_data_overlay.ktb$\q_saved_affinities"#endif /* #if !defined(__VAXC) */ N#define KTB$K_LENGTH 2352 /* Length of KTB */N#define KTB$C_LENGTH 2352 /* Length of KTB */N#define KTB$S_KTBDEF 2352 /* Old KTB size for compatibility */ #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */F#pragma __required_pointer_size __long /* Pointers are 64@-bits */=typedef PCB * PCB_PQ; /* Pointer to a PCB structure */Itypedef PCB ** PCB_PPQ; /* Pointer to a pointer to a PCB structure */=typedef KTB * KTB_PQ; /* Pointer to a KTB structure */Itypedef KTB ** KTB_PPQ; /* Pointer to a pointer to a KTB structure */G#pragma __required_pointer_size __short /* Pointers are 32-bits */=typedef PCB * PCB_PL; /* Pointer to a PCB structure */Itypedef PCB ** PCB_PPL; /* Pointer to a pointer to a PCB structure */ @=typedef KTB * KTB_PL; /* Pointer to a KTB structure */Itypedef KTB ** KTB_PPL; /* Pointer to a pointer to a KTB structure */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 PCB_PQ;!typedef unsigned __int64 PCB_PPQ; typedef unsigned __int64 KTB_PQ;!typedef unsigned __int64 KTB_PPQ; typedef unsigned __int32 PCB_PL;!typedef unsigned __int32 PCB_PPL; typedef unsigned __int32 KTB_PL;!typedef unsigned __int32 KTB@_PPL;##endif /* __INITIAL_POINTER_SIZE */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PCBDEF_LOADED */ ww2[UM/***************************************************************************/M/** @ **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** @ **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **@/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 14-JUN-2019 15:59:45 $1$DGA8345:[LIB_H.SRC]PCIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PCIDEF **@*/#ifndef __PCIDEF_LOADED#define __PCIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus@ extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* @ */R/* ============================================================================ */N/* PCI Type-0 Configuration Space */R/* ============================================================================ */N/* */#define PCI$K_VENDOR_ID 0#define PCI$K_DEVICE_ID 2#define PCI$K_COMMAND 4#define PCI$M_IO_ENABLE 0x1#d@efine PCI$M_MEM_ENABLE 0x2##define PCI$M_BUS_MASTER_ENABLE 0x4&#define PCI$M_SPECIAL_CYCLE_ENABLE 0x8#define PCI$M_INVAL_ENABLE 0x10'#define PCI$M_PALETTE_SNOOP_ENABLE 0x20 #define PCI$M_PARITY_ENABLE 0x40$#define PCI$M_WAIT_CYCLE_ENABLE 0x80#define PCI$M_SERR_ENABLE 0x100'#define PCI$M_BACK_TO_BACK_ENABLE 0x200#define PCI$M_INT_DISABLE 0x400#define PCI$K_STATUS 6#define PCI$M_INT_STATUS 0x8#define PCI$M_CAP_LIST 0x10#define PCI$M_SPEED_66MHZ 0x20#define PCI$M_RSVD_1 0x40@"#define PCI$M_FAST_BB_CAPABLE 0x80&#define PCI$M_DATA_PARITY_DETECT 0x100!#define PCI$M_DEVSEL_TIMING 0x600'#define PCI$M_SIGNAL_TARGET_ABORT 0x800%#define PCI$M_RCV_TARGET_ABORT 0x1000%#define PCI$M_RCV_MASTER_ABORT 0x2000 #define PCI$M_SIGNAL_SERR 0x4000#define PCI$M_DETECT_PE 0x8000#define PCI$K_REVISION_ID 8#define PCI$K_PROGRAMMING_IF 9#define PCI$K_SUB_CLASS 10#define PCI$K_BASE_CLASS 11 #define PCI$K_CACHE_LINE_SIZE 12#define PCI$K_LATENCY_TIMER 13#define PCI$K_HEAD@ER_TYPE 14#define PCI$K_BIST 15#define PCI$K_BASE_ADDRESS_0 16#define PCI$K_BASE_ADDRESS_1 20#define PCI$K_BASE_ADDRESS_2 24#define PCI$K_BASE_ADDRESS_3 28#define PCI$K_BASE_ADDRESS_4 32#define PCI$K_BASE_ADDRESS_5 36#define PCI$K_CARDBUS_CIS 40#define PCI$K_SUB_VNDR 44#define PCI$K_SUB_ID 46#define PCI$K_EXP_ROM_BASE 48%#define PCI$K_CAPABILITIES_POINTER 52#define PCI$K_INTR_LINE 60#define PCI$K_INTR_PIN 61#define PCI$K_MIN_GNT 62#define PCI$K_MAX_LAT 63N#d @efine PCI$S_PCIDEF 64 /* Old PCI size for compatibility */U/* The following constants apply to the DEVSEL timing field in the STATUS register */#define PCI$K_DEVSEL_FAST 0#define PCI$K_DEVSEL_MEDIUM 1#define PCI$K_DEVSEL_SLOW 2N/* The following constants apply to the BASE_CLASS byte */#define PCI$K_NOT_IMPLEMENTED 0"#define PCI$K_MASS_STORAGE_CTRLR 1#define PCI$K_NETWORK_CTRLR 2#define PCI$K_DISPLAY_CTRLR 3!#define PCI$K_MULTIMEDIA_DEVICE 4@#define PCI$K_MEMORY_CTRLR 5#define PCI$K_BRIDGE_DEVICE 6#define PCI$K_UNDEFINED 255N/* The following sub class definitions apply to the Mass Storage Base Class */#define PCI$K_SCSI_CTRLR 0#define PCI$K_IDE_CTRLR 1#define PCI$K_FLOPPY_CTRLR 2#define PCI$K_IPI_CTRLR 3##define PCI$K_OTHER_MASS_STORAGE 80T/* The following sub class definitions apply to the Network Controller Base Class */#define PCI$K_NI_CTRLR 0#define PCI$K_TOKEN_CTRLR 1#define PCI$K_FDDI_CTRLR 2#define PC @I$K_OTHER_NETWORK 80T/* The following sub class definitions apply to the Display Controller Base Class */#define PCI$K_VGA_CTRLR 0#define PCI$K_XGA_CTRLR 1#define PCI$K_OTHER_DISPLAY 80S/* The following sub class definitions apply to the Multimedia Device Base Class */#define PCI$K_VIDEO_CTRLR 0#define PCI$K_AUDIO_CTRLR 1!#define PCI$K_OTHER_MULTIMEDIA 80S/* The following sub class definitions apply to the Memory Controller Base Class */#define PCI$K_RAM 0#define PCI$K_FLASH @1#define PCI$K_OTHER_MEMORY 80O/* The following sub class definitions apply to the Bridge Device Base Class */#define PCI$K_HOST_BRIDGE 0#define PCI$K_ISA_BRIDGE 1#define PCI$K_EISA_BRIDGE 2#define PCI$K_MC_BRIDGE 3#define PCI$K_PCI_PCI_BRIDGE 4#define PCI$K_PCMCIA_BRIDGE 5#define PCI$K_OTHER_BRIDGE 80N/* The following constants apply to the Interrupt Pin byte */!#define PCI$K_INTR_PIN_NOT_USED 0#define PCI$K_INTR_PIN_INTA 1#define PCI$K_INTR_PIN_INTB @2#define PCI$K_INTR_PIN_INTC 3#define PCI$K_INTR_PIN_INTD 4#define PCI$K_MAX_DEVICES 32#define PCI$K_LENGTH 64 typedef struct _pci { short int pci$w_vendor_id; short int pci$w_device_id; __union { short int pci$w_command; __struct {N unsigned pci$v_io_enable : 1; /* 0 */N unsigned pci$v_mem_enable : 1; /* 1 */N unsigned pci$v_bus_master_enable : 1; /* 2 @ */N unsigned pci$v_special_cycle_enable : 1; /* 3 */N unsigned pci$v_inval_enable : 1; /* 4 */N unsigned pci$v_palette_snoop_enable : 1; /* 5 */N unsigned pci$v_parity_enable : 1; /* 6 */N unsigned pci$v_wait_cycle_enable : 1; /* 7 */N unsigned pci$v_serr_enable : 1; /* 8 */N @ unsigned pci$v_back_to_back_enable : 1; /* 9 */N unsigned pci$v_int_disable : 1; /* 10 PCI Spec V2.3 */N unsigned pci$v_command_fill : 5; /* 15:11 */! } pci$r_command_bits; } pci$r_command_overlay; __union { short int pci$w_status; __struct {N unsigned pci$v_status_fill : 3; /* 2:0 */N unsigned pci$v_int_status : 1; /* 3@ */N unsigned pci$v_cap_list : 1; /* 4 */N unsigned pci$v_speed_66mhz : 1; /* 5 */N unsigned pci$v_rsvd_1 : 1; /* 6 */N unsigned pci$v_fast_bb_capable : 1; /* 7 */N unsigned pci$v_data_parity_detect : 1; /* 8 */N unsigned pci$v_devsel_timing : 2; /* 10:9 @ */N unsigned pci$v_signal_target_abort : 1; /* 11 */N unsigned pci$v_rcv_target_abort : 1; /* 12 */N unsigned pci$v_rcv_master_abort : 1; /* 13 */N unsigned pci$v_signal_serr : 1; /* 14 */N unsigned pci$v_detect_pe : 1; /* 15 */ } pci$r_status_bits; } pci$r_status_overlay; char pci$b_revision_id; @ char pci$b_programming_if; char pci$b_sub_class; char pci$b_base_class; char pci$b_cache_line_size; char pci$b_latency_timer; char pci$b_header_type; char pci$b_bist; int pci$l_base_address_0; int pci$l_base_address_1; int pci$l_base_address_2; int pci$l_base_address_3; int pci$l_base_address_4; int pci$l_base_address_5; int pci$l_cardbus_cis; short int pci$w_sub_vndr; short int pci$w_sub_id; int pci$l_exp_ro@m_base; __union { __struct {, char pci$b_capabilities_pointer;# } pci$r_lw_0x34_struct; int pci$l_reserved_3; } pci$r_lw_0x34_overlay; int pci$l_reserved_4; char pci$b_intr_line; char pci$b_intr_pin; char pci$b_min_gnt; char pci$b_max_lat; } PCI; #if !defined(__VAXC)9#define pci$w_command pci$r_command_overlay.pci$w_commandP#define pci$v_io_enable pci$r_command_overlay.pci$r_command_bits.pci$v_io_en@ableR#define pci$v_mem_enable pci$r_command_overlay.pci$r_command_bits.pci$v_mem_enable`#define pci$v_bus_master_enable pci$r_command_overlay.pci$r_command_bits.pci$v_bus_master_enablef#define pci$v_special_cycle_enable pci$r_command_overlay.pci$r_command_bits.pci$v_special_cycle_enableV#define pci$v_inval_enable pci$r_command_overlay.pci$r_command_bits.pci$v_inval_enablef#define pci$v_palette_snoop_enable pci$r_command_overlay.pci$r_command_bits.pci$v_palette_snoop_enableX#define pci$v_parity_e@nable pci$r_command_overlay.pci$r_command_bits.pci$v_parity_enable`#define pci$v_wait_cycle_enable pci$r_command_overlay.pci$r_command_bits.pci$v_wait_cycle_enableT#define pci$v_serr_enable pci$r_command_overlay.pci$r_command_bits.pci$v_serr_enabled#define pci$v_back_to_back_enable pci$r_command_overlay.pci$r_command_bits.pci$v_back_to_back_enableT#define pci$v_int_disable pci$r_command_overlay.pci$r_command_bits.pci$v_int_disable6#define pci$w_status pci$r_status_overlay.pci$w_statusP#define pc@i$v_int_status pci$r_status_overlay.pci$r_status_bits.pci$v_int_statusL#define pci$v_cap_list pci$r_status_overlay.pci$r_status_bits.pci$v_cap_listR#define pci$v_speed_66mhz pci$r_status_overlay.pci$r_status_bits.pci$v_speed_66mhzH#define pci$v_rsvd_1 pci$r_status_overlay.pci$r_status_bits.pci$v_rsvd_1Z#define pci$v_fast_bb_capable pci$r_status_overlay.pci$r_status_bits.pci$v_fast_bb_capable`#define pci$v_data_parity_detect pci$r_status_overlay.pci$r_status_bits.pci$v_data_parity_detectV#define @pci$v_devsel_timing pci$r_status_overlay.pci$r_status_bits.pci$v_devsel_timingb#define pci$v_signal_target_abort pci$r_status_overlay.pci$r_status_bits.pci$v_signal_target_abort\#define pci$v_rcv_target_abort pci$r_status_overlay.pci$r_status_bits.pci$v_rcv_target_abort\#define pci$v_rcv_master_abort pci$r_status_overlay.pci$r_status_bits.pci$v_rcv_master_abortR#define pci$v_signal_serr pci$r_status_overlay.pci$r_status_bits.pci$v_signal_serrN#define pci$v_detect_pe pci$r_status_overlay.pci$r_sta @tus_bits.pci$v_detect_peh#define pci$b_capabilities_pointer pci$r_lw_0x34_overlay.pci$r_lw_0x34_struct.pci$b_capabilities_pointer?#define pci$l_reserved_3 pci$r_lw_0x34_overlay.pci$l_reserved_3"#endif /* #if !defined(__VAXC) */ N/* */N/* */R/* ============================================================================ */N/* PCI Capabilities Iden@tifiers */R/* ============================================================================ */N/* These constants apply to the CAPABILITIES field identified by the */N/* CAPABILITIES POINTER. For more details, see Appendix H of the */N/* PCI 3.0 spec. */N/* */N#define PCI$K_PMI_CAP 1 /* 1 @Power Management Interface */N#define PCI$K_AGP_CAP 2 /* 2 see http://www.agpforum.org */N#define PCI$K_VPD_CAP 3 /* 3 see sec. 6.4 of PCI 2.3 spec */N#define PCI$K_SID_CAP 4 /* 4 Slot ID, see PPB spec */N#define PCI$K_MSI_CAP 5 /* 5 see sec. 6.8 of PCI 2.3 spec */N#define PCI$K_PHS_CAP 6 /* 6 see http://www.picmg.org */N#define PCI$K_PCIX_CAP 7 /* 7 see PCI-X addendum @ */N#define PCI$K_AMD_CAP 8 /* 8 reserved for AMD */N#define PCI$K_VSID_CAP 9 /* 9 Vendor-specific */N#define PCI$K_DBG_CAP 10 /* A Debug port */N#define PCI$K_CRC_CAP 11 /* B see http://www.picmg.org */N#define PCI$K_HP_CAP 12 /* C Hot Plug Controller */S#define PCI$K_PPB_VID 13 /* D PCI-PCI Bridge Subsystem Vendor ID */N#define PCI$@K_AGP_8X 14 /* E see http://www.agpforum.org */N#define PCI$K_SECURE_CAP 15 /* F secure device */N#define PCI$K_PCIE_CAP 16 /* 10 PCI Express */N#define PCI$K_MSIX_CAP 17 /* 11 MSI-X Capability */N/* */N/* */R/* =================================== @========================================= */N/* Base Address Register */R/* ============================================================================ */N/* */%#define PCI$M_BASE_ADDRESS_MEM_IO 0x1##define PCI$M_BASE_ADDRESS_TYPE 0x6+#define PCI$M_BASE_ADDRESS_PREFETCHABLE 0x8/#define PCI$M_BASE_ADDRESS_BITS_31_4 0xFFFFFFF0 c#if !defined(__NOBASEALIGN_SUPPORT) &@& !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _base_address {#pragma __nomember_alignment __union { int pci$l_base_address; __struct {3 unsigned pci$v_base_address_mem_io : 1;1 unsigned pci$v_base_address_type : 2;9 unsigned pci$v_base_address_prefetchable : 1;7 unsigned pci$v_base_address_bits_31_4 : 28 @;& } pci$r_base_address_bits;% } pci$r_base_address_overlay; } BASE_ADDRESS; #if !defined(__VAXC)H#define pci$l_base_address pci$r_base_address_overlay.pci$l_base_addressn#define pci$v_base_address_mem_io pci$r_base_address_overlay.pci$r_base_address_bits.pci$v_base_address_mem_ioj#define pci$v_base_address_type pci$r_base_address_overlay.pci$r_base_address_bits.pci$v_base_address_typez#define pci$v_base_address_prefetchable pci$r_base_address_overlay.pci$r_base_ad @dress_bits.pci$v_base_address_prefetchablet#define pci$v_base_address_bits_31_4 pci$r_base_address_overlay.pci$r_base_address_bits.pci$v_base_address_bits_31_4"#endif /* #if !defined(__VAXC) */ #define BASE_ADDR_32 0#define BASE_ADDR_BELOW_1MB 1#define BASE_ADDR_64 2#define BASE_ADDR_RESERVED 3N/* */N/* */R/* =============================== @============================================= */N/* PCI_NODE_NUMBER */R/* ============================================================================ */N/* */N/* Verified for X86, Dave Fairbanks */*#define PCI$M_PCI_NODE_NUMBER_FUNCTION 0x7)#define PCI$M_PCI_NODE_NUMBER_DEVICE 0xF8(#define PCI$M_PCI_NODE_NUMBER_BUS 0xFF00/#d@efine PCI$M_PCI_NODE_NUMBER_OFFSET 0xFFFF0000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif!typedef struct _pci_node_number {#pragma __nomember_alignment __union {( __int64 pci$q_pci_node_number_q; __struct { __union {, int pci$l_pci_node_number_l;* int pci$l_pci_node_number;- @ } pci$r_pci_low_long_overlay;( int pci$l_pci_node_number_h;) } pci$r_pci_node_long_struct; __struct {8 unsigned pci$v_pci_node_number_function : 3;6 unsigned pci$v_pci_node_number_device : 5;3 unsigned pci$v_pci_node_number_bus : 8;7 unsigned pci$v_pci_node_number_offset : 16;8 unsigned pci$v_pci_node_number_segment : 16;9 unsigned pci$v_pci_node_number_reserved : 16;) @ } pci$r_pci_node_number_bits;( } pci$r_pci_node_number_overlay; } PCI_NODE_NUMBER; #if !defined(__VAXC)U#define pci$q_pci_node_number_q pci$r_pci_node_number_overlay.pci$q_pci_node_number_q#define pci$l_pci_node_number_l pci$r_pci_node_number_overlay.pci$r_pci_node_long_struct.pci$r_pci_low_long_overlay.pci$l_pci_node_\number_l#define pci$l_pci_node_number pci$r_pci_node_number_overlay.pci$r_pci_node_long_struct.pci$r_pci_low_long_overlay.pci$l_pci_node_nu\mberp#define @pci$l_pci_node_number_h pci$r_pci_node_number_overlay.pci$r_pci_node_long_struct.pci$l_pci_node_number_h~#define pci$v_pci_node_number_function pci$r_pci_node_number_overlay.pci$r_pci_node_number_bits.pci$v_pci_node_number_functionz#define pci$v_pci_node_number_device pci$r_pci_node_number_overlay.pci$r_pci_node_number_bits.pci$v_pci_node_number_devicet#define pci$v_pci_node_number_bus pci$r_pci_node_number_overlay.pci$r_pci_node_number_bits.pci$v_pci_node_number_busz#define pci$v_pci_node_number_ @offset pci$r_pci_node_number_overlay.pci$r_pci_node_number_bits.pci$v_pci_node_number_offset|#define pci$v_pci_node_number_segment pci$r_pci_node_number_overlay.pci$r_pci_node_number_bits.pci$v_pci_node_number_segment~#define pci$v_pci_node_number_reserved pci$r_pci_node_number_overlay.pci$r_pci_node_number_bits.pci$v_pci_node_number_reserved"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save&#pragma __required_pointer_size __long-ty @pedef PCI_NODE_NUMBER * PCI_NODE_NUMBER_PQ;)#pragma __required_pointer_size __restore#else,typedef unsigned __int64 PCI_NODE_NUMBER_PQ;$#endif /* __INITIAL_POINTER_SIZE */N/* */N/* */R/* ============================================================================ */N/* Hardware ID field */R @/* ============================================================================ */N/* */ *typedef struct _pci_busarray_hardware_id { __union {& __int64 pci$q_pci_hardware_id; __struct {3 short int pci$w_pci_hardware_id_vendor;3 short int pci$w_pci_hardware_id_device; __union {/ int pci$l_pci_hardware_id_fill; __struct {= @ short int pci$w_pci_hardware_id_sub_vndr;; short int pci$w_pci_hardware_id_sub_id;7 } pci$r_pci_hardware_id_fill_names;) } pci$r_pci_hardware_v21;) } pci$r_pci_hardware_id_bits;( } pci$r_pci_hardware_id_overlay; } PCI_BUSARRAY_HARDWARE_ID; #if !defined(__VAXC)Q#define pci$q_pci_hardware_id pci$r_pci_hardware_id_overlay.pci$q_pci_hardware_idz#define pci$w_pci_hardware_id_vendor pci$r_pci_hardw@are_id_overlay.pci$r_pci_hardware_id_bits.pci$w_pci_hardware_id_vendorz#define pci$w_pci_hardware_id_device pci$r_pci_hardware_id_overlay.pci$r_pci_hardware_id_bits.pci$w_pci_hardware_id_device#define pci$w_pci_hardware_id_sub_vndr pci$r_pci_hardware_id_overlay.pci$r_pci_hardware_id_bits.pci$r_pci_hardware_v21.pci$r_pci_ha\3rdware_id_fill_names.pci$w_pci_hardware_id_sub_vndr#define pci$w_pci_hardware_id_sub_id pci$r_pci_hardware_id_overlay.pci$r_pci_hardware_id_bits.pci$r_pci_hardware_v21.pci$r @_pci_hard\/ware_id_fill_names.pci$w_pci_hardware_id_sub_id"#endif /* #if !defined(__VAXC) */ N/* */N/* */R/* ============================================================================ */N/* PCIERR Structure */R/* ============================================================================ @*/N/* */#define PCIERR$K_LENGTH 72 typedef struct _pcierr {! unsigned pcierr$v_fill1 : 11;( unsigned pcierr$v_device_number : 5;& unsigned char pcierr$b_bus_number;! unsigned char pcierr$b_fill2;% unsigned int pcierr$l_frame_size; PCI pcierr$r_pci; } PCIERR;N/* */N/* @ */R/* ============================================================================ */N/* PCIFLAGS structure */R/* ============================================================================ */N/* */##define PCIFLAGS$M_FILL1 0xFFFFFF00)#define PCIFLAGS$M_DATA_PARITY_DETECT 0x1*#define PCIFLAGS$M_SIGNAL_TARGET_ABORT 0x2'#define PCIFLAGS$M_RCV@_TARGET_ABORT 0x4'#define PCIFLAGS$M_RCV_MASTER_ABORT 0x8##define PCIFLAGS$M_SIGNAL_SERR 0x10!#define PCIFLAGS$M_DETECT_PE 0x20#define PCIFLAGS$M_FILL2 0xC0##define PCIFLAGS$M_FILL3 0xFFFFFF00 typedef struct _pciflags { __union { __struct {. unsigned char pciflags$b_pciflags;+ unsigned pciflags$v_fill1 : 24;# } pciflags$r_pci_bits1; __struct {N unsigned pciflags$v_data_parity_detect : 1; /* From PCI stat<8> @*/R unsigned pciflags$v_signal_target_abort : 1; /* Same as stat<11:15> */5 unsigned pciflags$v_rcv_target_abort : 1;5 unsigned pciflags$v_rcv_master_abort : 1;0 unsigned pciflags$v_signal_serr : 1;. unsigned pciflags$v_detect_pe : 1;* unsigned pciflags$v_fill2 : 2;+ unsigned pciflags$v_fill3 : 24;# } pciflags$r_pci_bits2;! } pciflags$r_pciflags_ov; } PCIFLAGS; #if !defined(__VAXC)[@#define pciflags$b_pciflags pciflags$r_pciflags_ov.pciflags$r_pci_bits1.pciflags$b_pciflagso#define pciflags$v_data_parity_detect pciflags$r_pciflags_ov.pciflags$r_pci_bits2.pciflags$v_data_parity_detectq#define pciflags$v_signal_target_abort pciflags$r_pciflags_ov.pciflags$r_pci_bits2.pciflags$v_signal_target_abortk#define pciflags$v_rcv_target_abort pciflags$r_pciflags_ov.pciflags$r_pci_bits2.pciflags$v_rcv_target_abortk#define pciflags$v_rcv_master_abort pciflags$r_pciflags_ov.pciflags$r_pc @i_bits2.pciflags$v_rcv_master_aborta#define pciflags$v_signal_serr pciflags$r_pciflags_ov.pciflags$r_pci_bits2.pciflags$v_signal_serr]#define pciflags$v_detect_pe pciflags$r_pciflags_ov.pciflags$r_pci_bits2.pciflags$v_detect_pe"#endif /* #if !defined(__VAXC) */ #define ERRTAG$K_PCIERR 16N/* */N/* */R/* =========================================@=================================== */N/* Generic PCI capabilities header fields */R/* ============================================================================ */N/* */N/* See PCI Local Bus Specification Revision 3.0 Section 6.8 */N/* */N/* This definition creates constants that are offsets into a P@CI Capabiltiy */N/* block for a given device. These offsets are the same for any Capability */N/* block. */N/* */N/* PCICAP$K_ID - offset to the field containing the ID of this */N/* capability. */N/* */P/* PCICA@P$K_NEXT - offset to field contianing the offset into the device's */P/* PCI Config Space of the next Capability Block. Contains */N/* zero if this is the last block. */N/* */N/* PCICAP$K_CONTROL - offset to the field containing the control word for */N/* this capability */N/* @ */#define PCICAP$K_ID 0#define PCICAP$K_NEXT 1#define PCICAP$K_CONTROL 2 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifstruct pcicap {#pragma __nomember_alignment unsigned char pcicap$b_id; unsigned char pcicap$b_next;( unsigned short int pcicap$w_control; } ;N/* @ */N/* */R/* ============================================================================ */N/* MSI Control Register definition */R/* ============================================================================ */N/* */N/* See PCI Local Bus Specification R@evision 3.0 Section 6.8.2 */N/* */O/* msi$v_enable - RW if set, the device will deliver interrupts as MSI. */N/* */N/* msi$v_multi_cap - RO encodes the number of vectors requested by this */N/* device. */N/* @ */N/* msi$v_multi_ena - RW encodes the number of vectors assigned to this */N/* device by configuration code. */N/* */N/* msi$v_addr64_cap - RO if set, the device writes its message to a 64-bit */N/* physical address. */N/* */P/* msi @$v_per_vec_cap - RO if set, this device supports per-vector MSI masking */N/* capability. */N/* */#define MSI$M_ENABLE 0x1#define MSI$M_MULTI_CAP 0xE#define MSI$M_MULTI_ENA 0x70#define MSI$M_ADDR64_CAP 0x80#define MSI$M_PER_VEC_CAP 0x100 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */##pragma __no@member_alignment __word#else#pragma __nomember_alignment#endiftypedef struct _msi_control {#pragma __nomember_alignment __union {) unsigned short int msi$w_control; __struct {& unsigned msi$v_enable : 1;) unsigned msi$v_multi_cap : 3;) unsigned msi$v_multi_ena : 3;* unsigned msi$v_addr64_cap : 1;+ unsigned msi$v_per_vec_cap : 1;' unsigned msi$v_fill_0_ : 7;! } msi$r_control_bi @ts; } msi$r_control_overlay; } MSI_CONTROL; #if !defined(__VAXC)9#define msi$w_control msi$r_control_overlay.msi$w_controlJ#define msi$v_enable msi$r_control_overlay.msi$r_control_bits.msi$v_enableP#define msi$v_multi_cap msi$r_control_overlay.msi$r_control_bits.msi$v_multi_capP#define msi$v_multi_ena msi$r_control_overlay.msi$r_control_bits.msi$v_multi_enaR#define msi$v_addr64_cap msi$r_control_overlay.msi$r_control_bits.msi$v_addr64_capT#define msi$v_per_vec_cap msi$r_cont @rol_overlay.msi$r_control_bits.msi$v_per_vec_cap"#endif /* #if !defined(__VAXC) */ N/* */N/* */R/* ============================================================================ */N/* Generic MSI */R/* ============================================================================ */N/* @ */N/* This definition creates constants that are offsets into the MSI PCI */N/* Capabiltiy block for a given device. */N/* */N/* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */N/* */N/*************** @ */N/** IMPORTANT ** */N/*************** */N/* */N/* 1. If the ADDR64_CAP bit is set, you must use the MSI64 structure to */N/* access the following fields: */N/* . upper 32 bits of address @ */N/* . MESSAGE */N/* . VEC_MASK */N/* . VEC_PENDING */N/* */O/* 2. VEC_MASK and VEC_PENDING are only valid for access if the PER_VEC_CAP */N/* bit is set. */N/* @ */#define MSICAP$K_CAP_ID 0#define MSICAP$K_NEXT_CAP 1#define MSICAP$K_CONTROL 2#define MSICAP$K_ADDRESS 4#define MSICAP$K_MESSAGE 8#define MSICAP$K_RESERVED 10 #define MSICAP$K_BASIC_LENGTH 12#define MSICAP$K_VEC_MASK 12#define MSICAP$K_VEC_PENDING 16#define MSICAP$K_VEC_LENGTH 20#define MSICAP$K_VEC_AREA 8 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C@++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifstruct msicap {#pragma __nomember_alignment" unsigned char msicap$b_cap_id;$ unsigned char msicap$b_next_cap;! MSI_CONTROL msicap$r_control;" unsigned int msicap$l_address;( unsigned short int msicap$w_message;) unsigned short int msicap$w_reserved;# unsigned int msicap$l_vec_mask;& unsigned int msicap$l_vec_pending; } ;N/* @ */N/* */R/* ============================================================================ */N/* MSI64 - MSI with 64 bit message address */R/* ============================================================================ */N/* */N/* This definition creates constants that are offsets into t@he MSI PCI */N/* Capabiltiy block for a given device. */N/* */N/* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */N/* */N/*************** */N/** IMPORTANT ** */N/*****@********** */N/* */N/* 1. This structure is valid ONLY if the ADDR64_CAP bit is set. */N/* */O/* 2. VEC_MASK and VEC_PENDING are only valid for access if the PER_VEC_CAP */N/* bit is set. */N/* @ */#define MSI64CAP$K_CAP_ID 0#define MSI64CAP$K_NEXT_CAP 1#define MSI64CAP$K_CONTROL 2#define MSI64CAP$K_ADDRESS_LO 4#define MSI64CAP$K_ADDRESS_HI 8#define MSI64CAP$K_MESSAGE 12#define MSI64CAP$K_RESERVED 14"#define MSI64CAP$K_BASIC_LENGTH 16#define MSI64CAP$K_VEC_MASK 16!#define MSI64CAP$K_VEC_PENDING 20 #define MSI64CAP$K_VEC_LENGTH 24#define MSI64CAP$K_VEC_AREA 8 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cpluspl@us) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifstruct msi64cap {#pragma __nomember_alignment$ unsigned char msi64cap$b_cap_id;& unsigned char msi64cap$b_next_cap;# MSI_CONTROL msi64cap$r_control;' unsigned int msi64cap$l_address_lo;' unsigned int msi64cap$l_address_hi;* unsigned short int msi64cap$w_message;+ unsigned short int msi64cap$w_reserved;% unsigned int msi64cap$l_vec_ma @sk;( unsigned int msi64cap$l_vec_pending; } ;N/* */N/* */R/* ============================================================================ */N/* MSI 32-Bit Address Format */R/* ============================================================================ */N/* @ */R/* The definition of the Message Interrupt Message Address for x86 was obtained */N/* from The Intel 64 and IA-32 Software Developer's Manual, Volume 3, */N/* Figure 10-24 and section 10.11.1. */N/* */#define MSIADDR$M_RESERVED1 0x3#define MSIADDR$M_DM 0x4#define MSIADDR$M_RM 0x8!#define MSIADDR$M_RESERVED2 0xFF0!#define MSIADDR$M_DE@ST_ID 0xFF000"#define MSIADDR$M_FIXED 0xFFF00000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _msiaddr {#pragma __nomember_alignment __union {' unsigned int msiaddr$l_address; __struct {- unsigned msiaddr$v_reserved1 : 2;& unsigned msiaddr$v_dm : 1;& unsigned msiaddr$v_rm @: 1;- unsigned msiaddr$v_reserved2 : 8;+ unsigned msiaddr$v_dest_id : 8;Q unsigned msiaddr$v_fixed : 12; /* Contains the fixed hex value FEE */ } msiaddr$r_bits;! } msiaddr$r_addr_overlay; } MSIADDR; #if !defined(__VAXC)B#define msiaddr$l_address msiaddr$r_addr_overlay.msiaddr$l_addressG#define msiaddr$v_dm msiaddr$r_addr_overlay.msiaddr$r_bits.msiaddr$v_dmG#define msiaddr$v_rm msiaddr$r_addr_overlay.msiaddr$r_bits.msiaddr$v_r @mQ#define msiaddr$v_dest_id msiaddr$r_addr_overlay.msiaddr$r_bits.msiaddr$v_dest_idM#define msiaddr$v_fixed msiaddr$r_addr_overlay.msiaddr$r_bits.msiaddr$v_fixed"#endif /* #if !defined(__VAXC) */ N/* */N/* */R/* ============================================================================ */N/* MSI 64-Bit Address Format @ */R/* ============================================================================ */N/* */R/* The definition of the Message Interrupt Message Address for x86 was obtained */N/* from The Intel 64 and IA-32 Software Developer's Manual, Volume 3, */N/* Figure 10-24 and section 10.11.1. */N/* @ */!#define MSIADDR64$M_RESERVED1 0x3#define MSIADDR64$M_DM 0x4#define MSIADDR64$M_RM 0x8##define MSIADDR64$M_RESERVED2 0xFF0##define MSIADDR64$M_DEST_ID 0xFF000$#define MSIADDR64$M_FIXED 0xFFF00000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _msiaddr64 {#pragma __nomember_alignment __union {- unsigned __int @64 msiaddr64$q_address; __struct { __union {+ int msiaddr64$l_address_lo; __struct {7 unsigned msiaddr64$v_reserved1 : 2;0 unsigned msiaddr64$v_dm : 1;0 unsigned msiaddr64$v_rm : 1;7 unsigned msiaddr64$v_reserved2 : 8;5 unsigned msiaddr64$v_dest_id : 8;[ unsigned msiaddr64$v_fixed : 12; /* Contains the fixed hex value F @EE */* } msiaddr64$r_lo_bits;+ } msiaddr64$r_lo_addr_ovly;' int msiaddr64$l_address_hi;$ } msiaddr64$r_addr_ovly;# } msiaddr64$r_addr_overlay; } MSIADDR64; #if !defined(__VAXC)H#define msiaddr64$q_address msiaddr64$r_addr_overlay.msiaddr64$q_address}#define msiaddr64$l_address_lo msiaddr64$r_addr_overlay.msiaddr64$r_addr_ovly.msiaddr64$r_lo_addr_ovly.msiaddr64$l_address_lo#define msiaddr64$v_dm msiaddr64$r_addr_over@lay.msiaddr64$r_addr_ovly.msiaddr64$r_lo_addr_ovly.msiaddr64$r_lo_bits.msiaddr64$v_dm#define msiaddr64$v_rm msiaddr64$r_addr_overlay.msiaddr64$r_addr_ovly.msiaddr64$r_lo_addr_ovly.msiaddr64$r_lo_bits.msiaddr64$v_rm#define msiaddr64$v_dest_id msiaddr64$r_addr_overlay.msiaddr64$r_addr_ovly.msiaddr64$r_lo_addr_ovly.msiaddr64$r_lo_bits.msiaddr64$v\_dest_id#define msiaddr64$v_fixed msiaddr64$r_addr_overlay.msiaddr64$r_addr_ovly.msiaddr64$r_lo_addr_ovly.msiaddr64$r_lo_bits.msiaddr64$v_f\ixedd#d@efine msiaddr64$l_address_hi msiaddr64$r_addr_overlay.msiaddr64$r_addr_ovly.msiaddr64$l_address_hi"#endif /* #if !defined(__VAXC) */ N/* */N/* */R/* ============================================================================ */N/* MSI Message Format */R/* =======================================@===================================== */N/* */N/* Verified for x86 port - Michael Winiarski */N/* This definition of the Interrupt Message format was obtained from the */N/* Intel 64 and IA-32 Architecture Software Developer's Manual, Volume 3A */N/* Section 10.6.1 Figure 10-12 */N/* @ */#define MSIMSG$M_VECTOR 0xFF#define MSIMSG$M_DELMODE 0x700#define MSIMSG$M_DESTMODE 0x800#define MSIMSG$M_DELSTAT 0x1000#define MSIMSG$M_RESV_1 0x2000#define MSIMSG$M_LEVEL 0x4000 #define MSIMSG$M_TRIGMODE 0x8000#define MSIMSG$M_RESV_2 0x30000"#define MSIMSG$M_DESTSHORT 0xC0000(#define MSIMSG$M_RESV_3 0xFFFFFFFFF00000-#define MSIMSG$M_DESTFIELD 0xFF00000000000000 #define MSIMSG_DELMODE$K_FIXED 0!#define MSIMSG_DELMODE$K_LOWPRI 1#define MSIMSG_DELMODE$K_SMI 2!@#define MSIMSG_DELMODE$K_RESV_1 3#define MSIMSG_DELMODE$K_NMI 4#define MSIMSG_DELMODE$K_INIT 5"#define MSIMSG_DELMODE$K_STARTUP 6!#define MSIMSG_DELMODE$K_RESV_2 7$#define MSIMSG_DESTMODE$K_PHYSICAL 0##define MSIMSG_DESTMODE$K_LOGICAL 2#define MSIMSG_DELSTAT$K_IDLE 0##define MSIMSG_DELSTAT$K_SENDPEND 1!#define MSIMSG_LEVEL$K_DEASSERT 0#define MSIMSG_LEVEL$K_ASSERT 1 #define MSIMSG_TRIGMODE$K_EDGE 0!#define MSIMSG_TRIGMODE$K_LEVEL 1$#define MSIMSG_DESTSHORT$K_NOSHORT 0!#defin@e MSIMSG_DESTSHORT$K_SELF 1$#define MSIMSG_DESTSHORT$K_ALLINCL 2$#define MSIMSG_DESTSHORT$K_ALLEXCL 3 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _msimsg {#pragma __nomember_alignment __union {" unsigned int msimsg$l_msg;( unsigned short int msimsg$w_msg; __struct {) unsigned msimsg$v_vect@or : 8;* unsigned msimsg$v_delmode : 3;+ unsigned msimsg$v_destmode : 1;* unsigned msimsg$v_delstat : 1;) unsigned msimsg$v_resv_1 : 1;( unsigned msimsg$v_level : 1;+ unsigned msimsg$v_trigmode : 1;) unsigned msimsg$v_resv_2 : 2;, unsigned msimsg$v_destshort : 2;#if defined(__VAXC), unsigned msimsg$v_resv_3_1 : 32;+ unsigned msimsg$v_resv_3_2 : 4;#else2 unsign @ed __int64 msimsg$v_resv_3 : 36;#endif, unsigned msimsg$v_destfield : 8; } msimsg$r_bits; } msimsg$r_msg_overlay; } MSIMSG; #if !defined(__VAXC)6#define msimsg$l_msg msimsg$r_msg_overlay.msimsg$l_msg6#define msimsg$w_msg msimsg$r_msg_overlay.msimsg$w_msgJ#define msimsg$v_vector msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_vectorL#define msimsg$v_delmode msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_delmodeN#define msimsg$v_destmode msimsg$r_msg_overlay@.msimsg$r_bits.msimsg$v_destmodeL#define msimsg$v_delstat msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_delstatJ#define msimsg$v_resv_1 msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_resv_1H#define msimsg$v_level msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_levelN#define msimsg$v_trigmode msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_trigmodeJ#define msimsg$v_resv_2 msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_resv_2P#define msimsg$v_destshort msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_destshortJ#defin@e msimsg$v_resv_3 msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_resv_3P#define msimsg$v_destfield msimsg$r_msg_overlay.msimsg$r_bits.msimsg$v_destfield"#endif /* #if !defined(__VAXC) */ N/* */N/* */R/* ============================================================================ */N/* MSI-X Control Register Format @ */R/* ============================================================================ */N/* */N/* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */N/* */N/* msix$v_table_size - number of entries in the Vector Table, which is */N/* also the number of bits in the Pending Bit Array, */N/* @ maximum 2048. */N/* */N/* msix$v_function_mask - Masks all messages from this device */N/* */N/* msix$v_enable - Enables MSI-X interrupt delivery for this device. */N/* */#define MSIX$M_TABLE_SIZE 0x7FF#def@ine MSIX$M_RESERVED 0x3800##define MSIX$M_FUNCTION_MASK 0x4000#define MSIX$M_ENABLE 0x8000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */##pragma __nomember_alignment __word#else#pragma __nomember_alignment#endiftypedef struct _msix_control {#pragma __nomember_alignment __union {* unsigned short int msix$w_control; __struct {N unsigned msix$v_table_size : 11; /* 10:0 @*/N unsigned msix$v_reserved : 3; /* 13:11 */N unsigned msix$v_function_mask : 1; /* 14 */N unsigned msix$v_enable : 1; /* 15 */" } msix$r_control_bits; } msix$r_control_ovly; } MSIX_CONTROL; #if !defined(__VAXC)9#define msix$w_control msix$r_control_ovly.msix$w_controlS#define msix$v_table_size msix$r_control_ovly.msix$r_control_bits.msix$v_table_sizeO@#define msix$v_reserved msix$r_control_ovly.msix$r_control_bits.msix$v_reservedY#define msix$v_function_mask msix$r_control_ovly.msix$r_control_bits.msix$v_function_maskK#define msix$v_enable msix$r_control_ovly.msix$r_control_bits.msix$v_enable"#endif /* #if !defined(__VAXC) */ N/* */N/* */R/* ===================================================@========================= */N/* MSI-X Offset Register Format */R/* ============================================================================ */N/* */N/* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */N/* */O/* msix$v_bir - Three-bit field that encodes the offset into the devi@ce's */N/* PCI config space of the BAR that has the base address in */O/* of the Vector Table or Pending Bit Array, as the case may */N/* be. */N/* */N/* msix$v_offset - The 29-bit field containing the offset into the base */N/* address identified by the BAR of the Table or PBA. */N/* @ */#define MSIX$M_BIR 0x7 #define MSIX$M_OFFSET 0xFFFFFFF8 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif!typedef struct _msix_offset_reg {#pragma __nomember_alignment __union {# unsigned int msix$l_offset; __struct {N unsigned msix$v_bir : 3; /* 2: @0 */N unsigned msix$v_offset : 29; /* 31:3 */! } msix$r_offset_bits; } msix$r_offset_ovly; } MSIX_OFFSET_REG; #if !defined(__VAXC)6#define msix$l_offset msix$r_offset_ovly.msix$l_offsetC#define msix$v_bir msix$r_offset_ovly.msix$r_offset_bits.msix$v_birI#define msix$v_offset msix$r_offset_ovly.msix$r_offset_bits.msix$v_offset"#endif /* #if !defined(__VAXC) */ N/* @ */N/* */R/* ============================================================================ */N/* MSI-X Capability Format */R/* ============================================================================ */N/* */N/* See PCI Local Bus Specification Revision 3.0 Se@ction 6.8.2 */N/* */N/* The constants generated by this definition are byte offsets into the */N/* MSI-X Capability Block in PCI Config space. */N/* */N/* MSIXCAP$K_CAP_ID - Offset to field contianing the ID of this */N/* Capability, for MSI-X, 0x11. @*/N/* */N/* MSIXCAP$K_NEXT_CAP - Offset to field containing the offset from the */N/* base of PCI config space fof the device to the */N/* next Capability block of the device. Contains */N/* zero if no more Capability blocks. */N/* */N/* MSIXCAP$K_CONTROL @ - Offset to field containing the MSI-X Capability */N/* control bits. */N/* */N/* MSIXCAP$K_TABLE_OFFSET - Offset to field whose low three bits encode the */O/* offset into PCI Config space of the BAR that has */N/* the base address of the Vector Table, and whose */N/* upper 29 bits cont@ain the offset of the Vector */N/* Table into the space identified by the BAR. */N/* */N/* MSIXCAP$K_PBA_OFFSET - Offset to field whose low three bits encode the */O/* offset into PCI Config space of the BAR that has */N/* the base address of the Pending Bit Array, and */N/* whose upper 29 bits contain the offset of @the */N/* Pending Bit Array into the space identified by */N/* the BAR. */N/* */#define MSIXCAP$K_CAP_ID 0#define MSIXCAP$K_NEXT_CAP 1#define MSIXCAP$K_CONTROL 2 #define MSIXCAP$K_TABLE_OFFSET 4#define MSIXCAP$K_PBA_OFFSET 8#define MSIXCAP$K_LENGTH 12#define MSIXCAP$K_SIZE 12 c#if !defined(__NOBASEALIGN_SUPPORT) && @!defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifstruct msixcap {#pragma __nomember_alignment# unsigned char msixcap$b_cap_id;% unsigned char msixcap$b_next_cap;# MSIX_CONTROL msixcap$r_control;+ MSIX_OFFSET_REG msixcap$r_table_offset;) MSIX_OFFSET_REG msixcap$r_pba_offset; } ;N/* */N/* @ */R/* ============================================================================ */N/* MSI-X Table Entry Control Register */R/* ============================================================================ */N/* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */N/* */O/* msix_entry$v_mask - mask @s the vector of the corresponding Vector Table */N/* MSIX_ENTRY$M_MASK Entry */N/* */#define MSIX_ENTRY$M_MASK 0x1(#define MSIX_ENTRY$M_RESERVED 0xFFFFFFFE c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif$typedef struct _msix_entry@_control {#pragma __nomember_alignment __union {* unsigned int msix_entry$l_control; __struct {+ unsigned msix_entry$v_mask : 1;0 unsigned msix_entry$v_reserved : 31;( } msix_entry$r_control_bits;$ } msix_entry$r_control_ovly; } MSIX_ENTRY_CONTROL; #if !defined(__VAXC)K#define msix_entry$l_control msix_entry$r_control_ovly.msix_entry$l_control_#define msix_entry$v_mask msix_entry$r_control_ovly.msix_entry$r_control_b @its.msix_entry$v_maskg#define msix_entry$v_reserved msix_entry$r_control_ovly.msix_entry$r_control_bits.msix_entry$v_reserved"#endif /* #if !defined(__VAXC) */ N/* */N/* */R/* ============================================================================ */N/* MSI-X Table Entry */R/* =========@=================================================================== */N/* */N/* See PCI Local Bus Specification Revision 3.0 Section 6.8.2 */N/* */N/* This definition generates constants that are offsets into the MSI-X */N/* Vector Table. */N/* @ */N/* MSIX_ENTRY$K_ADDRESS - offset of the MSI-X Address field in the MSI-X */N/* Table Entry */O/* msix_entry$q_address - quadword displacement to next field in Table Entry */N/* */N/* */N/* MSIX_ENTRY$K_DATA - offset of the MSI-X Data field iAn the MSI-X Table */N/* Entry. */O/* msix_entry$l_data - longword displacement to next field in Table Entry */N/* */N/* */N/* MSIX_ENTRY$K_CONTROL - offset of the MSI-X Control field in the MSI-X */N/* Table Entry. */N/* A msix_entry$r_control - displacement of the MSI-X Control field formatted */N/* as MSIX_ENTRY_CONTROL (see above). */N/* */#define MSIX_ENTRY$K_ADDRESS 0#define MSIX_ENTRY$K_DATA 8#define MSIX_ENTRY$K_CONTROL 12#define MSIX_ENTRY$K_LENGTH 16#define MSIX_ENTRY$K_SIZE 16 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pra Agma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _msix_entry {#pragma __nomember_alignment* unsigned __int64 msix_entry$q_address;# unsigned int msix_entry$l_data;, MSIX_ENTRY_CONTROL msix_entry$r_control; } MSIX_ENTRY;N/* */N/* */N/* ===================================================A=============== */N/* MSI and MSI-X Abstracted Data Structures for System Use */N/* ================================================================== */N/* */N/* These abstracted data areas are used to store the information */N/* obtained from the PCI Config Header MSI and MSI-X capability */N/* blocks, making it unnecessary to spin any more PCI config access */NA/* cycles to obtain it again. For drivers, this information will */N/* be made available through ioc$node_data() calls. */N/* */N/*------------------------------------------------------------------- */N/* MSI Abstracted Data Area */N/*------------------------------------------------------------------- */N/* A */N/* msi$r_address - Target Physical Address for the MSI Message */N/* formatted as MSIADDR64 (see above). */N/* */N/* msi$r_message - Message sent to Target Address formatted as */N/* MSIMSG (see above). */N/* A */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _msi {N/* */N/* Target Physical Address */N/* */#pragma __nomember_a Alignment MSIADDR64 msi$r_address;N/* */N/* The Message */N/* */ MSIMSG msi$r_message; } MSI;N/* */N/* */N/*------------------------A-------------------------------------------- */N/* MSIX Abstracted Data Area */N/*-------------------------------------------------------------------- */N/* */N/* The MSIX area, because it is a system level data area, is */N/* permanently, mapped and the IOHANDLEs for it are stored here. */N/*  A */N/* msix$q_table_iohandle - IO Handle for access to the MSIX */N/* Vector Table. */N/* */N/* msix$q_pba_iohandle - IO Handle for access to the Pending */N/* Bit Array. */N/* */ AN/* msix$w_entry_count - number of entries in the Vector Table */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _msix {N/* */N/* IOHANDLE of the MSI-X Vector Table A */N/* */#pragma __nomember_alignment+ unsigned __int64 msix$q_table_iohandle;N/* */N/* IOHANDLE of the Pending Bit Array */N/* */) unsigned __int64 msix$q_pba_iohandle;* unsigned short int msix$w_en Atry_count; char msix$b_fill_1_ [6]; } MSIX;N/* */N/* */N/*-------------------------------------------------------------------- */N/* MSIDATA Abstracted MSI Union */N/*-------------------------------------------------------------------- */N/* A */N/* msidata$r_msi - space required for MSI data block format */N/* msidata$r_msix - space required for MSI-X data block format */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _msidata {#pragma __nomemb Aer_alignment MSI msidata$r_msi; MSIX msidata$r_msix; } MSIDATA;N/* */N/* */N/*-------------------------------------------------------------------- */N/* MSIABS Abstracted MSI Data Block */N/*-------------------------------------------------------------------- */N/* A */N/* This structure abstracts the fields of the MSI or MSI-X Capabilty. */N/* Only one of these capabilities will be enabled. OpenVMS will enable */N/* the MSI-X capability of a device if it supports both MSI and MSI-X. */N/* */N/* The salient information about the MSI or MSI-X capability is */N/* stored and updated in this structure for the systAem-level interface */N/* to driver code provided by ioc$node_data() and ioc$node_function */N/* routines. */N/* */N/* msiabs$l_cfg_offset - Offset into the device's PCI Config space */N/* of its MSI or MSI-X Capabilitly Block. */N/* */AN/* msiabs$w_control - Copy of the most recent write to the control */N/* register of the MSI or MSI-X capability. */N/* */N/* msiabs$w_type - contains one of: */N/* IOC$K_INTDEL_IOSAPIC - not MSI or MSI-X capable */N/* IOC$K_INTDEL_MSI - MSI enabled */N/* A IOC$K_INTDEL_MSIX - MSI-X enabled */N/* The contents of this field tell the user how */N/* to format the data areas of this structure, */N/* whetehr for MSI or MSI-X. */N/* */N/* msiabs$r_data - MSI or MSI-X specific data area formatted */N/* according to the content As of msiabs$w_type */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _msiabs {#pragma __nomember_alignmentP unsigned int msiabs$l_cfg_offset; /* PCI Config Offset of MSI Cap Block */P unsigned short int msiabs$w_control; /* Copy of the MSI* Con Atrol Register */N/* */N/* The msiabs$w_type field indicates how to format the msiabs$r_data */N/* field, in C terms, whether to cast it as MSI or MSIX. */N/* */% unsigned short int msiabs$w_type; MSIDATA msiabs$r_data; } MSIABS; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* DefineAd whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PCIDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/AM/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary softwareA licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************* A*******************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */I/* Source: 19-SEP-1994 09:15:32 $1$DGA8345:[LIB_H.SRC]PCMCIADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PCMCIADEF ***/#ifndef __PCMCIADEF_LOADED#define __PCMCIADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard Afeatures */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define A__optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define TPLCODE$K_CISTPL_NULL 0!#define TPLCODE$K_CISTPL_DEVICE 1$#define TPLCODE$K_CISTPL_CHECKSUM 16&#define TPLCODE$K_CISTPL_LONGLINK_A 17&#define TPLCODE$K_CISTPL_LONGLINK_C 18'#define TPLCODE$K_CISTPL_LLINKATARGET 19##define TPLCODE$K_CISTPL_NO_LINK 20"#define TPLCODE$K_CISTPL_VERS_1 21"#define TPLCODE$K_CISTPL_ALTSTR 22$#define TPLCODE$K_CISTPL_DEVICE_A 23##define TPLCODE$K_CISTPL_JEDEC_C 24##define TPLCODE$K_CISTPL_JEDEC_A 25"#define TPLCODE$K_CISTPL_CONFIG 26)#define TPLCODE$K_CISTPL_CFTABLE_ENTRY 27%#define TPLCODE$K_CISTPL_DEVICE_OC 28%#define TPLCODE$K_CISTPL_DEVCIE_OA 29&#define TPLCODE$K_CISTPL_DEVICE_GEO 30(#define TPLCODE$K_CISTPL_DEVICE_GEO_A 31"#define TPLCODE$K_CISTPL_MANAFID 32"#define TPLCODE$K_CISTPL_FUNCID 33!#define TPLCODE$K_CISTPL_FUNCE 34 #define TPLCODE$K_CISTPL_SWIL 35"#define TPLCODE$K_CISTPL_VERS_2 64"#define TPLCODE$K_CISTPL_FORMAT 65$#define TPLCODE$K_CISTPL_GEOMETRY 66%#define TPLCODE$K_CISTPL_BYTEORDER 67 #define TPLCODE$K_CISTPL_DATE 68##define TPLCODE$K_CISTPL_BATTERY 69#define TPLCODE$K_CISTPL_ORG 70 #define TPLCODE$K_CISTPL_END 255#define TPLDID$K_DSPEED_NULL 0#define TPLDID$K_DSPEED_250NS 1#define TPLDID$K_DSPEED_200NS 2#dAefine TPLDID$K_DSPEED_150NS 3#define TPLDID$K_DSPEED_100NS 4#define TPLDID$K_DSPEED_EXT 7#define TPLDID$K_DTYPE_NULL 0#define TPLDID$K_DTYPE_ROM 1#define TPLDID$K_DTYPE_OTPROM 2#define TPLDID$K_DTYPE_EPROM 3#define TPLDID$K_DTYPE_EEPROM 4#define TPLDID$K_DTYPE_FLASH 5#define TPLDID$K_DTYPE_SRAM 6#define TPLDID$K_DTYPE_DRAM 7"#define TPLDID$K_DTYPE_FUNCSPEC 13 #define TPLDID$K_DTYPE_EXTEND 14#define TPLDID$K_SIZE_512B 0#define TPLDID$K_SIZE_2K 1#define TPLDID$K_SIZE_A8K 2#define TPLDID$K_SIZE_32K 3#define TPLDID$K_SIZE_128K 4#define TPLDID$K_SIZE_512K 5#define TPLDID$K_SIZE_2M 6#define TPLFID$K_MULTI_FUNC 0#define TPLFID$K_MEMORY 1#define TPLFID$K_SERIAL_PORT 2 #define TPLFID$K_PARALLEL_PORT 3#define TPLFID$K_FIXED_DISK 4 #define TPLFID$K_VIDEO_ADAPTER 5#define TPLFID$K_NETWORK_LAN 6#define TPLFID$K_AIMS 7#define TPLFID_SYSINIT$K_POST 1#define TPLFID_SYSINIT$K_ROM 2 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTERA_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PCMCIADEF_LOADED */ wwD[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential prop Arietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/*!A* proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************** "A*****************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */K/* Source: 19-MAY-1993 14:01:22 $1$DGA8345:[LIB_H.SRC]PCSAMPLEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE PCSAMPLEDEF ***/#ifndef __PCSAMPLEDEF_LOADED#define __PCSAMPLEDEF_LOADED 1 G#pragma __nostandard /* This #Afile uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#defin$Ae __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif ##define PCBUF$C_STRUCTURE_VERSION 2N/* */N/* Slot constraining values %A */N/* */N#define PCBUF$C_MAX_SLOT_CNT 32768 /* Maximum number of slots */N#define PCBUF$C_MIN_SLOT_CNT 128 /* Minimum number of slots */N/* */N/* Slot structure definition */N/* */#define PCSLT$C_LE &ANGTH 16N#define PCSLT$S_PCSLTDEF 16 /* Old size name - synonym */ typedef struct _pcslt {N void *pcslt$l_pc; /* Program counter */N unsigned int pcslt$l_ps; /* Process status */N unsigned int pcslt$l_counter; /* Indicates which counter fired */N unsigned int pcslt$l_pid; /* ID of current process */ } PCSLT;N/* 'A */N/* Buffer descriptor structure */N/* */#define PCDSC$C_LENGTH 20N#define PCDSC$S_PCDSCDEF 20 /* Old size name - synonym */ typedef struct _pcdsc {N void *pcdsc$l_buffer; /* Pointer to buffer in use */ __union { __struct {N unsigned int pcdsc$l_cur_slot; /* Index of next sl (Aot */N unsigned int pcdsc$l_slot_cnt; /* Number of slots in the buffer */ } pcdsc$r_slot_info; __struct {+ unsigned int pcdsc$l_counter_0;+ unsigned int pcdsc$l_counter_1;# } pcdsc$r_counter_info; } pcdsc$r_over_1;Q unsigned int pcdsc$l_buff_size; /* Size of memory block for descriptor */P void *pcdsc$l_ring_ptr; /* Fake buffer pointer to next buffer */ } PCDSC; #if !defin )Aed(__VAXC):#define pcdsc$r_slot_info pcdsc$r_over_1.pcdsc$r_slot_info;#define pcdsc$l_cur_slot pcdsc$r_slot_info.pcdsc$l_cur_slot;#define pcdsc$l_slot_cnt pcdsc$r_slot_info.pcdsc$l_slot_cnt@#define pcdsc$r_counter_info pcdsc$r_over_1.pcdsc$r_counter_info@#define pcdsc$l_counter_0 pcdsc$r_counter_info.pcdsc$l_counter_0@#define pcdsc$l_counter_1 pcdsc$r_counter_info.pcdsc$l_counter_1"#endif /* #if !defined(__VAXC) */ N/* *A */N/* Buffer structure */N/* */N#define PCBUF$C_HDR_SIZE 32 /* Buffer header size */N#define PCBUF$C_MAX_LENGTH 524320 /* Maximum buffer size */N#define PCBUF$S_PCBUFDEF 524320 /* Old size name - synonym */ typedef struct _pcbuf {N void *pcbuf$l_next_buff; /* Pointer to next buffer +A */R unsigned int pcbuf$l_buff_size; /* Size of memory block used for buffer */N unsigned int pcbuf$l_full_flag; /* Buffer is full */N unsigned int pcbuf$l_cpu_id; /* CPU index */N unsigned __int64 pcbuf$q_begin_time; /* Time buffer was started */N char pcbuf$b_scratch [8]; /* Used to force slot alignment */N char pcbuf$b_data_area [524288]; /* Data slots */ } PCBU,AF;N#define PCBUF$C_MIN_LENGTH 2080 /* Minimum buffer size */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __PCSAMPLEDEF_LOADED */ ww@[UM/***************************************************************-A************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** .A **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** /A **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */G/* Source: 01-DEC-2017 11:35:54 $1$DGA8345:[LIB_H.SRC]PCTXDEF.SDL;1 *//*************************************************************************************************************** 0A*****************//*** MODULE $PCTXDEF ***/#ifndef __PCTXDEF_LOADED#define __PCTXDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit po1Ainters */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ 2A */N/* */I/* Define: FCLE_MBD (FCLE API Mapped Buffer Descriptor) */N/* */N/* */N/*- */  9#ifdef __cplusplus /* Define structure prototypes */ struct _mbd; 3A#endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endiftypedef struct _fcle_mbd {N/* Flink and Blink pointers */#pragma __nomember_alignment! struct _mbd *fcle_mbd$ps_qfl;! struct _mbd *fcle_mbd$ps_qbl;N/* Size, type and subtype in standard OpenVMS structure locations 4A */ short int fcle_mbd$w_size; char fcle_mbd$b_type; char fcle_mbd$b_subtype;" unsigned int fcle_mbd$l_flags;N/* Quadword available for whatever the user wants */* unsigned __int64 fcle_mbd$q_user_data;N/* Logical Size - this is the number of leading bytes of this buffer which */T/* will be read or written the next time this MBD is used. It will be initialized */S/* to the number of bytes mapped. It can be changed by a caller prior to use a5And */O/* read by a caller after use. Again: this size always refers to the leading */N/* bytes of the buffer */! int fcle_mbd$is_logical_size;P/* This is only used to store a VA if the caller mapping a buffer passes in a */O/* VA, and it's only so the caller can always find a VA from an MBD. If they */N/* want to use it for something else that's OK with the Kernel, because it */N/* never references the address of a buffer mapped by an 6A MBD */ __int64 fcle_mbd$q_va;N/* Buffer byte offset */ int fcle_mbd$is_boff;N/* Mapped size, the absolute maximum number of bytes which can be */N/* addressed by this MBD. */ int fcle_mbd$is_bcnt;N/* Buffer SVAPTE */N int fcle_mbd$l_svapte_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */ 7AN/* Number of physical pages spanned (and MRs allocated) */ int fcle_mbd$is_pages;N/* Number of bytes transferred */" int fcle_mbd$is_transfer_bcnt;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragm 8Aa __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *fcle_mbd$pq_svapte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else) unsigned __int64 fcle_mbd$pq_svapte_sva;#endif } FCLE_MBD;N/* */N/* There is one PCBVEC for each protocol (PCTX) so protocol specific */N/* data is unioned in the PCBVEC to save space. */N/* 9A */!#define PCBVEC$K_FORMAT_VERSION 2 typedef struct _pcbvec {N/* */N/* Only bump this version number if the PCBVEC is changed in */N/* such a way that all drivers will need to be recompiled */N/* */#pragma __nomember_alignment! int pcbvec$is_format_version:A;N/* */N/* Unused entries have been added in the middle of the common vectors */N/* at the end of the protocol specific vectors. Use these unused */N/* entries add new vectors. This will save us from */N/* having to compile all drivers when only one protocol is */N/* affected. */N/* ;A */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif, int (*pcbvec$ps_vector_array [1])(); __struct {0 int (*pcbvec$ps_exchange_aborted)();( int (*pcbvec$ps_prli_ind)();( int (*pcbvec$ps_prlo_ind)();- int (*pcbvec$ps_buffer_wanted)() A */N/* */ __union { __struct {1 int (*pcbvec$ps_rbun_init)();- } pcbvec$r_fcp_structure; __struct {4 int (*pcbvec$ps_confirmation)();2 int (*pcbvec$ps_indication)();4 int (*pcbvec$ps_get_preq_buf)();4 int (*pcbvec$ps_ret_preq_buf)();/ ?A int (*pcbvec$ps_unused6)();/ int (*pcbvec$ps_unused7)();/ int (*pcbvec$ps_unused8)();/ int (*pcbvec$ps_unused9)();0 int (*pcbvec$ps_unused10)();. } pcbvec$r_fcle_structure;1 } pcbvec$r_protocol_vector_union;) } pcbvec$r_vectors_structure; } pcbvec$r_vector_union; char pcbvec$b_fill_0_ [4]; } PCBVEC; #if !defined(__VAXC)K#define pcbvec@A$ps_vector_array pcbvec$r_vector_union.pcbvec$ps_vector_arrayS#define pcbvec$r_vectors_structure pcbvec$r_vector_union.pcbvec$r_vectors_structureX#define pcbvec$ps_exchange_aborted pcbvec$r_vectors_structure.pcbvec$ps_exchange_abortedH#define pcbvec$ps_prli_ind pcbvec$r_vectors_structure.pcbvec$ps_prli_indH#define pcbvec$ps_prlo_ind pcbvec$r_vectors_structure.pcbvec$ps_prlo_indR#define pcbvec$ps_buffer_wanted pcbvec$r_vectors_structure.pcbvec$ps_buffer_wantedR#define pcbvec$ps_buffer_filled pcAAbvec$r_vectors_structure.pcbvec$ps_buffer_filledV#define pcbvec$ps_buffer_released pcbvec$r_vectors_structure.pcbvec$ps_buffer_releasedB#define pcbvec$ps_pause pcbvec$r_vectors_structure.pcbvec$ps_pauseD#define pcbvec$ps_resume pcbvec$r_vectors_structure.pcbvec$ps_resumeL#define pcbvec$ps_link_state pcbvec$r_vectors_structure.pcbvec$ps_link_stateN#define pcbvec$ps_pause_fc_la pcbvec$r_vectors_structure.pcbvec$ps_pause_fc_laP#define pcbvec$ps_resume_fc_la pcbvec$r_vectors_structure.pcbvec$ps_resuBAme_fc_laN#define pcbvec$ps_cmd_timeout pcbvec$r_vectors_structure.pcbvec$ps_cmd_timeoutF#define pcbvec$ps_els_ind pcbvec$r_vectors_structure.pcbvec$ps_els_indF#define pcbvec$ps_els_cnf pcbvec$r_vectors_structure.pcbvec$ps_els_cnfL#define pcbvec$ps_port_state pcbvec$r_vectors_structure.pcbvec$ps_port_stateX#define pcbvec$ps_change_preferred pcbvec$r_vectors_structure.pcbvec$ps_change_preferredR#define pcbvec$ps_create_target pcbvec$r_vectors_structure.pcbvec$ps_create_targetF#define pcbvec$ps_unCAused2 pcbvec$r_vectors_structure.pcbvec$ps_unused2F#define pcbvec$ps_unused3 pcbvec$r_vectors_structure.pcbvec$ps_unused3F#define pcbvec$ps_unused4 pcbvec$r_vectors_structure.pcbvec$ps_unused4F#define pcbvec$ps_unused5 pcbvec$r_vectors_structure.pcbvec$ps_unused5`#define pcbvec$r_protocol_vector_union pcbvec$r_vectors_structure.pcbvec$r_protocol_vector_unionT#define pcbvec$r_fcp_structure pcbvec$r_protocol_vector_union.pcbvec$r_fcp_structureF#define pcbvec$ps_rbun_init pcbvec$r_fcp_structure.pcbDAvec$ps_rbun_initV#define pcbvec$r_fcle_structure pcbvec$r_protocol_vector_union.pcbvec$r_fcle_structureM#define pcbvec$ps_confirmation pcbvec$r_fcle_structure.pcbvec$ps_confirmationI#define pcbvec$ps_indication pcbvec$r_fcle_structure.pcbvec$ps_indicationM#define pcbvec$ps_get_preq_buf pcbvec$r_fcle_structure.pcbvec$ps_get_preq_bufM#define pcbvec$ps_ret_preq_buf pcbvec$r_fcle_structure.pcbvec$ps_ret_preq_bufC#define pcbvec$ps_unused6 pcbvec$r_fcle_structure.pcbvec$ps_unused6C#define pcbvec EA$ps_unused7 pcbvec$r_fcle_structure.pcbvec$ps_unused7C#define pcbvec$ps_unused8 pcbvec$r_fcle_structure.pcbvec$ps_unused8C#define pcbvec$ps_unused9 pcbvec$r_fcle_structure.pcbvec$ps_unused9E#define pcbvec$ps_unused10 pcbvec$r_fcle_structure.pcbvec$ps_unused10"#endif /* #if !defined(__VAXC) */ N/* */N/* There is only one ULPVEC per system */N/* FA */!#define ULPVEC$K_FORMAT_VERSION 3#define ULP$K_DEBUG 0#define ULP$K_FCP_SCSI 1#define ULP$K_LAN 2#define ULP$K_ELS 3N/* Define buffer context values for ULP$MAP */#define ULP$K_GENERAL_DATA 1#define ULP$K_FCP_DATA 2#define ULP$K_FCP_CMD_RSP 3#define ULP$K_ELS_REQ_RSP 4#define ULP$K_QUEUE_BUFFER 5 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#p GAragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ulpvec {N/* */N/* Only bump this version number if the ULPVEC is changed in */N/* such a way that all drivers will need to be recompiled */N/* */#pragma __nomember_alignment! int ulpvec$is_format_version; __un HAion {, int (*ulpvec$ps_vector_array [1])(); __struct {N/* ************************************************** */N/* ULP (Upper Level Protocol) Vectors */N/* ************************************************** */* int (*ulpvec$ps_disconnect)();, int (*ulpvec$ps_get_requests)();0 int (*ulpvec$ps_get_request_data)();- int (*ulpvec$ps_get_exchanges)();1 IA int (*ulpvec$ps_get_exchange_data)();# int (*ulpvec$ps_map)();% int (*ulpvec$ps_unmap)();% int (*ulpvec$ps_reset)();0 int (*ulpvec$ps_queue_buffer_ulp)();5 int (*ulpvec$ps_queue_buffer_exchange)();- int (*ulpvec$ps_send_sequence)();- int (*ulpvec$ps_open_exchange)();- int (*ulpvec$ps_abort_request)();. int (*ulpvec$ps_abort_exchange)();/ int (*ulpvec$ps_broadcast_fr JAame)();) int (*ulpvec$ps_alloc_mbd)();( int (*ulpvec$ps_free_mbd)();) int (*ulpvec$ps_clone_mbd)();. int (*ulpvec$ps_deleted_vector)();( int (*ulpvec$ps_get_fcla)();- int (*ulpvec$ps_validate_fcla)();) int (*ulpvec$ps_init_link)();- int (*ulpvec$ps_get_port_wwid)();. int (*ulpvec$ps_cancel_request)();3 int (*ulpvec$ps_alloc_mapped_buffer)();2 int (*ulpvec$ps_free_m KAapped_buffer)();- int (*ulpvec$ps_get_link_data)();* int (*ulpvec$ps_fp_request)();' int (*ulpvec$ps_fp_send)();) int (*ulpvec$ps_free_rbun)();+ int (*ulpvec$ps_bus_address)();' int (*ulpvec$ps_unused1)();' int (*ulpvec$ps_unused2)();' int (*ulpvec$ps_unused3)();' int (*ulpvec$ps_unused4)();N/* *************************************************** */N/* ELS (Extended LA Link Service) Vectors */N/* *************************************************** */2 int (*ulpvec$ps_els_alloc_payloads)();4 int (*ulpvec$ps_els_dealloc_payloads)();( int (*ulpvec$ps_els_send)();, int (*ulpvec$ps_els_send_cmd)();, int (*ulpvec$ps_els_send_rsp)();, int (*ulpvec$ps_alloc_ls_rjt)();, int (*ulpvec$ps_alloc_ls_acc)();' int (*ulpvec$ps_un MAused5)();' int (*ulpvec$ps_unused6)();' int (*ulpvec$ps_unused7)();N/* */N/* The following data are specific to particular */N/* protocols but we can't union then together because */N/* there is only one ULPVEC per system. */N/* */N/* ******* NA************************************************* */N/* FCP (SCSI FibreChannel Protocol) Vectors */N/* ******************************************************** */2 int (*ulpvec$ps_fcp_alloc_payloads)();4 int (*ulpvec$ps_fcp_dealloc_payloads)();( int (*ulpvec$ps_fcp_send)();5 int (*ulpvec$ps_completion_processing)();* int (*ulpvec$ps_write_data)();) int (*ulpvec$ps_ OAread_data)();, int (*ulpvec$ps_fcp_send_rsp)();3 int (*ulpvec$ps_set_connection_char)();) int (*ulpvec$ps_fcp_abort)();% int (*ulpvec$ps_event)();N int (*ulpvec$ps_trigger)(); /* X-8 */' int (*ulpvec$ps_unused9)();( int (*ulpvec$ps_unused10)();N/* ********************************************************* */N/* FCLE (LAN over Fibre Channel) Vectors PA */N/* ********************************************************* */. int (*ulpvec$ps_get_fc_la_data)();) int (*ulpvec$ps_broadcast)();( int (*ulpvec$ps_sequence)();* int (*ulpvec$ps_fcle_abort)();. int (*ulpvec$ps_close_exchange)();, int (*ulpvec$ps_ret_mbd_list)();* int (*ulpvec$ps_hard_reset)();) } ulpvec$r_vectors_structure; } ulpvec$r_vector_union;N/* Define ULP_ QAID values */ } ULPVEC; #if !defined(__VAXC)K#define ulpvec$ps_vector_array ulpvec$r_vector_union.ulpvec$ps_vector_arrayS#define ulpvec$r_vectors_structure ulpvec$r_vector_union.ulpvec$r_vectors_structureL#define ulpvec$ps_disconnect ulpvec$r_vectors_structure.ulpvec$ps_disconnectP#define ulpvec$ps_get_requests ulpvec$r_vectors_structure.ulpvec$ps_get_requestsX#define ulpvec$ps_get_request_data ulpvec$r_vectors_structure.ulpvec$ps_geRAt_request_dataR#define ulpvec$ps_get_exchanges ulpvec$r_vectors_structure.ulpvec$ps_get_exchangesZ#define ulpvec$ps_get_exchange_data ulpvec$r_vectors_structure.ulpvec$ps_get_exchange_data>#define ulpvec$ps_map ulpvec$r_vectors_structure.ulpvec$ps_mapB#define ulpvec$ps_unmap ulpvec$r_vectors_structure.ulpvec$ps_unmapB#define ulpvec$ps_reset ulpvec$r_vectors_structure.ulpvec$ps_resetX#define ulpvec$ps_queue_buffer_ulp ulpvec$r_vectors_structure.ulpvec$ps_queue_buffer_ulpb#define ulpvec$ps_queue_SAbuffer_exchange ulpvec$r_vectors_structure.ulpvec$ps_queue_buffer_exchangeR#define ulpvec$ps_send_sequence ulpvec$r_vectors_structure.ulpvec$ps_send_sequenceR#define ulpvec$ps_open_exchange ulpvec$r_vectors_structure.ulpvec$ps_open_exchangeR#define ulpvec$ps_abort_request ulpvec$r_vectors_structure.ulpvec$ps_abort_requestT#define ulpvec$ps_abort_exchange ulpvec$r_vectors_structure.ulpvec$ps_abort_exchangeV#define ulpvec$ps_broadcast_frame ulpvec$r_vectors_structure.ulpvec$ps_broadcast_frameJ#defTAine ulpvec$ps_alloc_mbd ulpvec$r_vectors_structure.ulpvec$ps_alloc_mbdH#define ulpvec$ps_free_mbd ulpvec$r_vectors_structure.ulpvec$ps_free_mbdJ#define ulpvec$ps_clone_mbd ulpvec$r_vectors_structure.ulpvec$ps_clone_mbdT#define ulpvec$ps_deleted_vector ulpvec$r_vectors_structure.ulpvec$ps_deleted_vectorH#define ulpvec$ps_get_fcla ulpvec$r_vectors_structure.ulpvec$ps_get_fclaR#define ulpvec$ps_validate_fcla ulpvec$r_vectors_structure.ulpvec$ps_validate_fclaJ#define ulpvec$ps_init_link ulpvec$r_vecUAtors_structure.ulpvec$ps_init_linkR#define ulpvec$ps_get_port_wwid ulpvec$r_vectors_structure.ulpvec$ps_get_port_wwidT#define ulpvec$ps_cancel_request ulpvec$r_vectors_structure.ulpvec$ps_cancel_request^#define ulpvec$ps_alloc_mapped_buffer ulpvec$r_vectors_structure.ulpvec$ps_alloc_mapped_buffer\#define ulpvec$ps_free_mapped_buffer ulpvec$r_vectors_structure.ulpvec$ps_free_mapped_bufferR#define ulpvec$ps_get_link_data ulpvec$r_vectors_structure.ulpvec$ps_get_link_dataL#define ulpvec$ps_fp_requeVAst ulpvec$r_vectors_structure.ulpvec$ps_fp_requestF#define ulpvec$ps_fp_send ulpvec$r_vectors_structure.ulpvec$ps_fp_sendJ#define ulpvec$ps_free_rbun ulpvec$r_vectors_structure.ulpvec$ps_free_rbunN#define ulpvec$ps_bus_address ulpvec$r_vectors_structure.ulpvec$ps_bus_addressF#define ulpvec$ps_unused1 ulpvec$r_vectors_structure.ulpvec$ps_unused1F#define ulpvec$ps_unused2 ulpvec$r_vectors_structure.ulpvec$ps_unused2F#define ulpvec$ps_unused3 ulpvec$r_vectors_structure.ulpvec$ps_unused3F#define ulWApvec$ps_unused4 ulpvec$r_vectors_structure.ulpvec$ps_unused4\#define ulpvec$ps_els_alloc_payloads ulpvec$r_vectors_structure.ulpvec$ps_els_alloc_payloads`#define ulpvec$ps_els_dealloc_payloads ulpvec$r_vectors_structure.ulpvec$ps_els_dealloc_payloadsH#define ulpvec$ps_els_send ulpvec$r_vectors_structure.ulpvec$ps_els_sendP#define ulpvec$ps_els_send_cmd ulpvec$r_vectors_structure.ulpvec$ps_els_send_cmdP#define ulpvec$ps_els_send_rsp ulpvec$r_vectors_structure.ulpvec$ps_els_send_rspP#define ulpvecXA$ps_alloc_ls_rjt ulpvec$r_vectors_structure.ulpvec$ps_alloc_ls_rjtP#define ulpvec$ps_alloc_ls_acc ulpvec$r_vectors_structure.ulpvec$ps_alloc_ls_accF#define ulpvec$ps_unused5 ulpvec$r_vectors_structure.ulpvec$ps_unused5F#define ulpvec$ps_unused6 ulpvec$r_vectors_structure.ulpvec$ps_unused6F#define ulpvec$ps_unused7 ulpvec$r_vectors_structure.ulpvec$ps_unused7\#define ulpvec$ps_fcp_alloc_payloads ulpvec$r_vectors_structure.ulpvec$ps_fcp_alloc_payloads`#define ulpvec$ps_fcp_dealloc_payloads ulpvec$YAr_vectors_structure.ulpvec$ps_fcp_dealloc_payloadsH#define ulpvec$ps_fcp_send ulpvec$r_vectors_structure.ulpvec$ps_fcp_sendb#define ulpvec$ps_completion_processing ulpvec$r_vectors_structure.ulpvec$ps_completion_processingL#define ulpvec$ps_write_data ulpvec$r_vectors_structure.ulpvec$ps_write_dataJ#define ulpvec$ps_read_data ulpvec$r_vectors_structure.ulpvec$ps_read_dataP#define ulpvec$ps_fcp_send_rsp ulpvec$r_vectors_structure.ulpvec$ps_fcp_send_rsp^#define ulpvec$ps_set_connection_char ulpvecZA$r_vectors_structure.ulpvec$ps_set_connection_charJ#define ulpvec$ps_fcp_abort ulpvec$r_vectors_structure.ulpvec$ps_fcp_abortB#define ulpvec$ps_event ulpvec$r_vectors_structure.ulpvec$ps_eventF#define ulpvec$ps_trigger ulpvec$r_vectors_structure.ulpvec$ps_triggerF#define ulpvec$ps_unused9 ulpvec$r_vectors_structure.ulpvec$ps_unused9H#define ulpvec$ps_unused10 ulpvec$r_vectors_structure.ulpvec$ps_unused10T#define ulpvec$ps_get_fc_la_data ulpvec$r_vectors_structure.ulpvec$ps_get_fc_la_dataJ#defin[Ae ulpvec$ps_broadcast ulpvec$r_vectors_structure.ulpvec$ps_broadcastH#define ulpvec$ps_sequence ulpvec$r_vectors_structure.ulpvec$ps_sequenceL#define ulpvec$ps_fcle_abort ulpvec$r_vectors_structure.ulpvec$ps_fcle_abortT#define ulpvec$ps_close_exchange ulpvec$r_vectors_structure.ulpvec$ps_close_exchangeP#define ulpvec$ps_ret_mbd_list ulpvec$r_vectors_structure.ulpvec$ps_ret_mbd_listL#define ulpvec$ps_hard_reset ulpvec$r_vectors_structure.ulpvec$ps_hard_reset"#endif /* #if !defined(__VAXC) */ \AN/*+ */N/* */I/* Define: PCTX (Protocol Context) */N/* */N/* One Protocol Context is created for each ULP which connects to the Shell */I/* */N/*- ]A */#define PCTX$M_BROADCAST 0x1"#define PCTX$M_INITIAL_PREEMPT 0x2#define PCTX$K_FORMAT_VERSION 2N/* format of the PCTX */#define PCTX$M_CLASS2 4#define PCTX$M_CLASS3 8#define PCTX$V_CLASS2 2#define PCTX$V_CLASS3 3  9#ifdef __cplusplus /* Define structure prototypes */ struct _sctx; struct _uctx; struct _ucb; struct _kpb; struct _tqe;struct _fcp_rbun;struct _crct^Ax; struct _fccd; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pctx {N/* Forward link */#pragma __nomember_alignment void *pctx$ps_qfl;N/* Backward link */ void *pctx$ps_qb _Al;N/* Structure (allocation) size */ short int pctx$w_size;N/* Structure type (DYN$C_MISC) */ char pctx$b_type;N/* Structure subtype (DYN$C_PCTX) */ char pctx$b_subtype;N/* Define some flags */ __union {N/* All flags */ `Aint pctx$l_flags;N/* Individual flags */ __union {0 unsigned int pctx$l_flags_structure; __struct {_ unsigned pctx$v_broadcast : 1; /* Boolean: true if protocol can do broadcast */e unsigned pctx$v_initial_preempt : 1; /* Boolean: true if initial preemptive target */N/* creation has taken place. */, unsigned pct aAx$v_fill_3_ : 6;! } pctx$r_fill_2_; } pctx$r_fill_1_; } pctx$r_flags_overlay;N/* */N/* Only bump this version number if the PCTX is changed in */N/* such a way that all drivers will need to be recompiled */N/* */ int pctx$is_format_version;N/* Shell Context pointer bA */ struct _sctx *pctx$ps_sctx;N/* Unit Context pointer */ struct _uctx *pctx$ps_uctx;N/* Ring on which this protocol is enabled */ int pctx$is_ring;N/* Return the UCB to the ULP */# struct _ucb *pctx$ps_fc_ad_ucb;N/* ULP fork lock index */ unsi cAgned int pctx$is_flck;N/* Protocol Callback Context to be passed to each callback */# unsigned __int64 pctx$q_pcbctx;N/* ULP KPB (this does not need to be specified and it may be NULL) */! struct _kpb *pctx$ps_ulp_kpb;N/* Protocol ID given to the adapter ( FCPH$K_ ) */" unsigned int pctx$is_protocol;N/* Protocol specified when ULP connected ( ULP$K_ ) */% unsigned int pctx$is_protocol_id;N/* Load PCI dAaddress space for adapter ID information */ void *pctx$ps_chs;N/* Pointer used to define a protocol port specific data */N/* for the Fibre Channel adapter. */ void *pctx$ps_protodef;N/* ULP vector pointer */# struct _ulpvec *pctx$ps_ulpvec;N/* PCB vector structure */c#if !defined(__NOBASEALIGN eA_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif PCBVEC pctx$r_pcbvec;N/* */N/* This union is for protocol specific data cells */N/* */ __union {N/* fA */N/* FCP protocol specific */N/* */#pragma __nomember_alignment __struct {N/* Resource Bundle Lookaside List pointer */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif# gA void *pctx$ps_rbun_lal;N/* Sequence number to allow LAL to be used with EXE$LAL_INSERT/REMOVE_FIRST */#pragma __nomember_alignment0 unsigned int pctx$l_rbun_lal_seqnum;N/* Prebuilt READ IOCB command longword (i.e. FCP_IREAD for FCP protocol) */1 unsigned int pctx$l_fp_iocb_read_icb;N/* Maximum data buffer byte count in an RBUN */% int pctx$l_max_rbun_bcnt;N/* Prebuilt WRITE IOCB command longword (i.e. FCP_IWRITE f hAor FCP protocol) */2 unsigned int pctx$l_fp_iocb_write_icb;N/* Value at which we'll start drain TQE */, int pctx$l_rbun_drain_threshold;N/* Total number of RBUNs, free and in use */# int pctx$l_total_rbuns;N/* Number of unhandled RBUN allocation failures */+ int pctx$l_rbun_alloc_failures;N/* TQE used to check & drain RBUNs iA */0 struct _tqe *pctx$ps_rbun_drain_tqe;$ char pctx$b_fill_4_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment: unsigned __int64 pctx$q_rbun_drain_active; __struct {= struct _fcp_rbun *pctx$ps_rbun_drain_lal;9 jA unsigned int pctx$l_rbun_drain_count;/ } pctx$r_rbun_drain_struct;* } pctx$r_rbun_drain_union;N/* */N/* These two values are pointers to the SPDT data */N/* */" void *pctx$l_spl_port;. unsigned int *pctx$ps_max_fp_bcnt;N void *pctx$l_spl_d kAyn; /* X-7 */ } pctx$r_fcpdef;N/* */N/* FCLE protocol specific */N/* */ __struct {N/* */3 struct _crctx *pctx$ps_fcle_load_crctx;N/* lA */4 struct _crctx *pctx$ps_fcle_alloc_crctx;N/* size of the pre-queued adapter buffers for the fcle ring */3 unsigned int pctx$l_fcle_preq_buf_size;N/* list of available FCCDs */1 struct _fccd *pctx$ps_fcle_fccd_list;N/* A count of mbd_list arrays passed up the LAN ULP. */N/* The count is decremented as the ULP returns each mbd_ mAlist. */6 unsigned int pctx$l_outstanding_mbd_lists;N/* Number of FCCDs to preallocate */& int pctx$l_fcle_max_fccds;N/* */N/* LAN Driver private data */N/* */' unsigned int pctx$l_lan_p1;' unsigned int nA pctx$l_lan_p2;' unsigned int pctx$l_lan_p3;' unsigned int pctx$l_lan_p4;' unsigned int pctx$l_lan_p5;' unsigned int pctx$l_lan_p6;N/* */N/* unspecified reserved data */N/* */( unsigned int pctx$l_fcle_p1;( unsigned int pctx$l_fcle_p oA2;( unsigned int pctx$l_fcle_p3;( unsigned int pctx$l_fcle_p4;( unsigned int pctx$l_fcle_p5;( unsigned int pctx$l_fcle_p6; } pctx$r_fcledef;( } pctx$r_protocol_specific_data;N/* */N/* These constants define the Fibre Channel class of service */N/* capabilities of the connection */N/* pA */ } PCTX; #if !defined(__VAXC)6#define pctx$l_flags pctx$r_flags_overlay.pctx$l_flagsY#define pctx$l_flags_structure pctx$r_flags_overlay.pctx$r_fill_1_.pctx$l_flags_structure\#define pctx$v_broadcast pctx$r_flags_overlay.pctx$r_fill_1_.pctx$r_fill_2_.pctx$v_broadcasth#define pctx$v_initial_preempt pctx$r_flags_overlay.pctx$r_fill_1_.pctx$r_fill_2_.pctx$v_initial_preemptA#define pctx$r_fcpdef pctx$r_protocol_specific_data.pctx$r qA_fcpdef7#define pctx$ps_rbun_lal pctx$r_fcpdef.pctx$ps_rbun_lalC#define pctx$l_rbun_lal_seqnum pctx$r_fcpdef.pctx$l_rbun_lal_seqnumE#define pctx$l_fp_iocb_read_icb pctx$r_fcpdef.pctx$l_fp_iocb_read_icb?#define pctx$l_max_rbun_bcnt pctx$r_fcpdef.pctx$l_max_rbun_bcntG#define pctx$l_fp_iocb_write_icb pctx$r_fcpdef.pctx$l_fp_iocb_write_icbM#define pctx$l_rbun_drain_threshold pctx$r_fcpdef.pctx$l_rbun_drain_threshold;#define pctx$l_total_rbuns pctx$r_fcpdef.pctx$l_total_rbunsK#define pctx$lrA_rbun_alloc_failures pctx$r_fcpdef.pctx$l_rbun_alloc_failuresC#define pctx$ps_rbun_drain_tqe pctx$r_fcpdef.pctx$ps_rbun_drain_tqeE#define pctx$r_rbun_drain_union pctx$r_fcpdef.pctx$r_rbun_drain_unionQ#define pctx$q_rbun_drain_active pctx$r_rbun_drain_union.pctx$q_rbun_drain_activeQ#define pctx$r_rbun_drain_struct pctx$r_rbun_drain_union.pctx$r_rbun_drain_structN#define pctx$ps_rbun_drain_lal pctx$r_rbun_drain_struct.pctx$ps_rbun_drain_lalP#define pctx$l_rbun_drain_count pctx$r_rbun_drain_st sAruct.pctx$l_rbun_drain_count5#define pctx$l_spl_port pctx$r_fcpdef.pctx$l_spl_port=#define pctx$ps_max_fp_bcnt pctx$r_fcpdef.pctx$ps_max_fp_bcnt3#define pctx$l_spl_dyn pctx$r_fcpdef.pctx$l_spl_dynC#define pctx$r_fcledef pctx$r_protocol_specific_data.pctx$r_fcledefF#define pctx$ps_fcle_load_crctx pctx$r_fcledef.pctx$ps_fcle_load_crctxH#define pctx$ps_fcle_alloc_crctx pctx$r_fcledef.pctx$ps_fcle_alloc_crctxJ#define pctx$l_fcle_preq_buf_size pctx$r_fcledef.pctx$l_fcle_preq_buf_sizeD#define pc tAtx$ps_fcle_fccd_list pctx$r_fcledef.pctx$ps_fcle_fccd_listP#define pctx$l_outstanding_mbd_lists pctx$r_fcledef.pctx$l_outstanding_mbd_listsB#define pctx$l_fcle_max_fccds pctx$r_fcledef.pctx$l_fcle_max_fccds2#define pctx$l_lan_p1 pctx$r_fcledef.pctx$l_lan_p12#define pctx$l_lan_p2 pctx$r_fcledef.pctx$l_lan_p22#define pctx$l_lan_p3 pctx$r_fcledef.pctx$l_lan_p32#define pctx$l_lan_p4 pctx$r_fcledef.pctx$l_lan_p42#define pctx$l_lan_p5 pctx$r_fcledef.pctx$l_lan_p52#define pctx$l_lan_p6 pctx$r_fcledef uA.pctx$l_lan_p64#define pctx$l_fcle_p1 pctx$r_fcledef.pctx$l_fcle_p14#define pctx$l_fcle_p2 pctx$r_fcledef.pctx$l_fcle_p24#define pctx$l_fcle_p3 pctx$r_fcledef.pctx$l_fcle_p34#define pctx$l_fcle_p4 pctx$r_fcledef.pctx$l_fcle_p44#define pctx$l_fcle_p5 pctx$r_fcledef.pctx$l_fcle_p54#define pctx$l_fcle_p6 pctx$r_fcledef.pctx$l_fcle_p6"#endif /* #if !defined(__VAXC) */ N/* */N/* LNK$K_UP and LNK$K_DOWN are returned in pcb vAvec$ps_link_state */N/* */a#define LNK$K_INITIAL 0 /* Initial link state (suppresses initial report, MBZ) */N#define LNK$K_UP 1 /* Link is up */N#define LNK$K_DOWN 2 /* Link is down */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragmwAa __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PCTXDEF_LOADED */ wwpU[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise DxAevelopment, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not yA **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************************************************** zA*********************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */I/* Source: 23-SEP-1994 08:47:19 $1$DGA8345:[LIB_H.SRC]PD6729DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PD6729DEF ***/#ifndef __PD6729DEF_LOADED#define __PD6729DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __sav{Ae#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __|Astruct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define PD6729$K_CHIP_REVISION 0##define PD6729$K_INTERFACE_STATUS 1 #define PD6729$K_POWER_CONTROL 2##define PD6729$K_INTR_AND_CONTROL 3##define PD6729$K_CARD_STAT_CHANGE 4!#define PD6729$K_MGMT_INTR_CNFG 5!#define PD6729$K_MAPPING_ENABLE 6!#define PD}A6729$K_IO_WINDOW_CTRL 7"#define PD6729$K_MISC_CONTROL_1 22 #define PD6729$K_FIFO_CONTROL 23"#define PD6729$K_MISC_CONTROL_2 30#define PD6729$K_CHIP_INFO 31#define PD6729$K_ATA_CONTROL 38#define PD6729$K_EXT_INDEX 46#define PD6729$K_EXT_DATA 47 #define PD6729$K_SETUP_TIME_0 58#define PD6729$K_CMD_TIME_0 59##define PD6729$K_RECOVERY_TIME_0 60 #define PD6729$K_SETUP_TIME_1 61#define PD6729$K_CMD_TIME_1 62##define PD6729$K_RECOVERY_TIME_1 63!#define PD6729$K_IO_START_LOW_0 8"#d~Aefine PD6729$K_IO_START_HIGH_0 9 #define PD6729$K_IO_END_LOW_0 10!#define PD6729$K_IO_END_HIGH_0 11##define PD6729$K_IO_OFFSET_LOW_0 54$#define PD6729$K_IO_OFFSET_HIGH_0 55"#define PD6729$K_IO_START_LOW_1 12##define PD6729$K_IO_START_HIGH_1 13 #define PD6729$K_IO_END_LOW_1 14!#define PD6729$K_IO_END_HIGH_1 15##define PD6729$K_IO_OFFSET_LOW_1 56$#define PD6729$K_IO_OFFSET_HIGH_1 57##define PD6729$K_MEM_START_LOW_0 16$#define PD6729$K_MEM_START_HIGH_0 17!#define PD6729$K_MEM_END_LOW_0A 18"#define PD6729$K_MEM_END_HIGH_0 19$#define PD6729$K_MEM_OFFSET_LOW_0 20%#define PD6729$K_MEM_OFFSET_HIGH_0 21##define PD6729$K_MEM_START_LOW_1 24$#define PD6729$K_MEM_START_HIGH_1 25!#define PD6729$K_MEM_END_LOW_1 26"#define PD6729$K_MEM_END_HIGH_1 27$#define PD6729$K_MEM_OFFSET_LOW_1 28%#define PD6729$K_MEM_OFFSET_HIGH_1 29##define PD6729$K_MEM_START_LOW_2 32$#define PD6729$K_MEM_START_HIGH_2 33!#define PD6729$K_MEM_END_LOW_2 34"#define PD6729$K_MEM_END_HIGH_2 35$#define PD67A29$K_MEM_OFFSET_LOW_2 36%#define PD6729$K_MEM_OFFSET_HIGH_2 37##define PD6729$K_MEM_START_LOW_4 48$#define PD6729$K_MEM_START_HIGH_4 49!#define PD6729$K_MEM_END_LOW_4 50"#define PD6729$K_MEM_END_HIGH_4 51$#define PD6729$K_MEM_OFFSET_LOW_4 52%#define PD6729$K_MEM_OFFSET_HIGH_4 53 #define PD6729$K_EXT_CONTROL_1 3#define PD6729$K_MEM_UPPER_0 5#define PD6729$K_MEM_UPPER_1 6#define PD6729$K_MEM_UPPER_2 7#define PD6729$K_MEM_UPPER_3 8#define PD6729$K_MEM_UPPER_4 9!#define PD6729$K_EXTAERNAL_DATA 10!#define PD6729$K_EXT_CONTROL_2 11#define PD6729$K_SOCKET_SHIFT 6!#define PD6729$K_SOCKET_OFFSET 64#define PD6729$K_INDEX 0#define PD6729$K_DATA 1$#define PD6729$K_LOW_POWER_DYNAMIC 2 #define PD6729$K_CARD_ENABLE 128#define PD6729$K_AUTO_POWER 32#define PD6729$K_VCC 16!#define PD6729$K_DATA_PATH_16 128#define PD6729$K_REG_ACTIVE 64#define PD6729$K_NOT_RESET 64#define PD6729$K_IO 32!#define PD6729$K_BATTERY_STATUS 1#define PD6729$K_BATTERY_WARN 2#define APD6729$K_READY_ENABLE 4%#define PD6729$K_CARD_DETECT_ENABLE 8##define PD6729$K_MEM_MAP_ENABLE_0 1##define PD6729$K_MEM_MAP_ENABLE_1 2##define PD6729$K_MEM_MAP_ENABLE_2 4##define PD6729$K_MEM_MAP_ENABLE_3 8$#define PD6729$K_MEM_MAP_ENABLE_4 16##define PD6729$K_IO_MAP_ENABLE_0 64$#define PD6729$K_IO_MAP_ENABLE_1 128$#define PD6729$K_CARD_DETECT_MASK 12#define PD6729$K_NO_CARD 0#define PD6729$K_CARD_DETECT 12#define PD6729$K_PD6729_INTA 3#define PD6729$K_PD6729_INTB 4#define PDA6729$K_PD6729_INTC 5#define PD6729$K_PD6729_INTD 7 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PD6729DEF_LOADED */ ww|[UM/***************************************************************************/M/** A **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** A **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** A **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:38 by OpenVMS SDL V3.7 */F/* Source: 16-FEB-2007 09:40:25 $1$DGA8345:[LIB_H.SRC]PDBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $P ADBDEF ***/#ifndef __PDBDEF_LOADED#define __PDBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplAusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DEFINAE DEVICE PERFORMANCE DATA BLOCK */N/*- */   #include #define PDB$K_ABORT_RQ 1#define PDB$K_END_IO 2#define PDB$K_END_RQ 3#define PDB$K_START_IO 4#define PDB$K_START_RQ 5#define PDB$K_DIRIO 6#define PDB$K_BUFIO 7#define PDB$K_MAX_MODE 7#define PDB$M_ALL 0x1#define PDB$M_ABORT_RQ 0x2#define PDB$M_END_IO 0x4#define PDB$M_END_RQ 0x8#define APDB$M_START_IO 0x10#define PDB$M_START_RQ 0x20#define PDB$M_XFER 0x40#define PDB$M_DIRIO 0x80#define PDB$M_BUFIO 0x100#define PDB$M_XQP 0x200N#define PDB$K_LENGTH 156 /*LENGTH OF DATA CONTROL BLOCK */N#define PDB$C_LENGTH 156 /*LENGTH OF DATA CONTROL BLOCK */#define PDB$S_PDBDEF 156  9#ifdef __cplusplus /* Define structure prototypes */struct _iotrh; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && A!defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pdb {#pragma __nomember_alignmentO void *pdb$l_freefl; /*FREE BUFFER LISTHEAD FORWARD LINK */N void *pdb$l_freebl; /*FREE BUFFER LISTHEAD BACKLINK */N unsigned short int pdb$w_size; /*SIZE OF DATA STRUCTURE */N unsigned char pdb$b_type; /*TYPE OF DATA STRUCATURE */N unsigned char pdb$b_overrun; /*OVERRUN INDICATOR */Q void *pdb$l_fillfl; /*FILLED BUFFER LISTHEAD FORWARD LINK */R void *pdb$l_fillbl; /*FILLED BUFFER LISTHEAD BACKWARD LINK */N void *pdb$l_curbuf; /*ADDRESS OF CURRENT BUFFER */P void *pdb$l_nxtbuf; /*ADDRESS OF NEXT LOCATION IN BUFFER */N void *pdb$l_endbuf; /*ADDRESS OF END OF BUFFER A*/S unsigned int pdb$l_pid; /*PROCESS ID OF DATA COLLECTION PROCESS */N unsigned char pdb$b_devclass; /*DEVICE CLASS SELECTION */N unsigned char pdb$b_devtype; /*DEVICE TYPE SELECTION */N unsigned short int pdb$w_andm; /*STATUS SELECTION 'AND' MASK */N unsigned short int pdb$w_xorm; /*STATUS SELECTION 'XOR' MASK */N unsigned short int pdb$w_bufcnt; /*COUNT OF FILLED BUFFERS */N unsigned __i Ant64 pdb$q_func; /*SELECTION FUNCTION MASK */ char pdb$b_fill_0_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 pdb$q_data; /* pointer to data area */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_s Aize __long /* And set ptr size default to 64-bit pointers */N struct _iotrh *pdb$q_trace_buffer; /* pointer to trace buffer */#else% unsigned __int64 pdb$q_trace_buffer;#endif __union {N unsigned int pdb$l_flags; /* trace flags */ __struct {# unsigned pdb$v_all : 1;( unsigned pdb$v_abort_rq : 1;& unsigned pdb$v_end_io : 1;& unsigned pdb$v_end_rq : 1;( unsigned pdb$v_s Atart_io : 1;( unsigned pdb$v_start_rq : 1;$ unsigned pdb$v_xfer : 1;% unsigned pdb$v_dirio : 1;% unsigned pdb$v_bufio : 1;# unsigned pdb$v_xqp : 1;' unsigned pdb$v_fill_1_ : 6; } pdb$r_flags_bits; } pdb$r_flags_overlay;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifNA int (*pdb$l_start_trace)(); /* ptr to start trace routine */N int (*pdb$l_stop_trace)(); /* ptr to stop trace routine */N void (*pdb$l_abort_rq)(); /* abort I/O request */N void (*pdb$l_end_io)(); /* end I/O transaction */N void (*pdb$l_end_rq)(); /* end I/O request */N void (*pdb$l_start_io)(); /* start I/O transaction */N void (*pdb$l_start_rq) A(); /* start I/O request */N void (*pdb$l_dio_bio)(); /* direct and buffered I/O */ char pdb$b_fill_2_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 pdb$q_reserved1; /* reserved */N __int64 pdb$q_reserved2; /* reserved A */N __int64 pdb$q_reserved3; /* reserved */\ __int64 pdb$q_last_wake; /* The ABSTIM_TIC value when collector last woken */#pragma __nomember_alignment_ unsigned __int64 *pdb$pq_scc; /* pointer to array of cycle counts per possible CPU */_ unsigned __int64 *pdb$pq_systime; /* pointer to array of systime info per possible CPU */ int pdb$l_max_cpus; char pdb$b_fill_3_ [4]; } PDB; #if !defined(__VAXC)3#defAine pdb$l_flags pdb$r_flags_overlay.pdb$l_flags@#define pdb$v_all pdb$r_flags_overlay.pdb$r_flags_bits.pdb$v_allJ#define pdb$v_abort_rq pdb$r_flags_overlay.pdb$r_flags_bits.pdb$v_abort_rqF#define pdb$v_end_io pdb$r_flags_overlay.pdb$r_flags_bits.pdb$v_end_ioF#define pdb$v_end_rq pdb$r_flags_overlay.pdb$r_flags_bits.pdb$v_end_rqJ#define pdb$v_start_io pdb$r_flags_overlay.pdb$r_flags_bits.pdb$v_start_ioJ#define pdb$v_start_rq pdb$r_flags_overlay.pdb$r_flags_bits.pdb$v_start_rqB#define pdb$v_xferA pdb$r_flags_overlay.pdb$r_flags_bits.pdb$v_xferD#define pdb$v_dirio pdb$r_flags_overlay.pdb$r_flags_bits.pdb$v_dirioD#define pdb$v_bufio pdb$r_flags_overlay.pdb$r_flags_bits.pdb$v_bufio@#define pdb$v_xqp pdb$r_flags_overlay.pdb$r_flags_bits.pdb$v_xqp"#endif /* #if !defined(__VAXC) */ N#define IOTRE$K_LENGTH 56 /* Structure size */  9#ifdef __cplusplus /* Define structure prototypes */ struct _irp; struct _ucb; struct _ktb; #endif /* #ifdef __ Acplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _iotre {#pragma __nomember_alignmentN unsigned __int64 iotre$q_timestamp; /* timestamp in system cycle counts */N unsigned int iotre$l_cpuid; /* current CPU id */N unsigned int iotre$l_mode; /* general trace category */N A unsigned int iotre$l_seqnum; /* sequence number */N unsigned int iotre$l_func; /* function code */N struct _irp *iotre$l_irp; /* address of IRP */N struct _ucb *iotre$l_ucb; /* address of UCB */N unsigned int iotre$l_bcnt; /* byte count */N unsigned int iotre$l_lbn; /* starting LBN */N struct _pcb *iotre$l_pcb A; /* address of PCB */N unsigned int iotre$l_reserved1; /* reserved */N unsigned int iotre$l_reserved2; /* reserved */N unsigned int iotre$l_reserved3; /* reserved */ } IOTRE;N#define IOTRH$K_LENGTH 88 /* Structure size */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nome Amber_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _iotrh {#pragma __nomember_alignmentN int iotrh$l_idx; /* current index into trace buffer */N unsigned int iotrh$l_max_idx; /* maximum trace index */N unsigned short int iotrh$w_mbo; /* must-be-one field */N unsigned char iotrh$b_type; /* Structure type */N unsigned char iotrh$b_subtype; /* subtype A */ unsigned int iotrh$l_fill1;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 iotrh$q_size; /* Size */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size def Aault to 64-bit pointers */N struct _iotre *iotrh$q_entry_ptr; /* pointer to first trace entry */#else$ unsigned __int64 iotrh$q_entry_ptr;#endifN IOTRE iotrh$r_entry [1]; /* array of trace entries */ } IOTRH; #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Ctypedef struct _pdb *PDB_PQ; /* Pointer to a PDB structure. *A/Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 PDB_PQ;##endif /* __INITIAL_POINTER_SIZE */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PDBDEF_LOADED */ wwAʖ[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 20A24 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software,A Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:09 by OpenVMS SDL V3.7 */D/* Source: 01-DEC-2017 13:04:34 $1$DGA8345:[LIB.SRC]PDTDEF.SDL;1 *//********************************* A***********************************************************************************************//*** MODULE $PDTDEF ***/#ifndef __PDTDEF_LOADED#define __PDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragmAa __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_unio An#endif#endif N/*+ */N/* DEFINE PORT-INDEPENDENT OFFSETS IN A PORT DESCRIPTOR TABLE. */N/* */N/* THERE IS ONE PDT PER PORT ACCESSED VIA SCS. THESE PORTS INCLUDE */N/* CI'S AND UDA'S. THE PDT CONTAINS A PORT-INDEPENDENT PIECE (DEFINED */N/* HERE) FOLLOWED BY AN OPTIONAL PORT-SPECIFIC PIECE DEFINED IN THE */N/*A PORT DRIVER. PDT'S ARE CREATED BY THE CONTROLLER INIT ROUTINES */N/* OF THE INDIVIDUAL PORT DRIVERS. */N/*- */ #define PDT$M_SNGLHOST 0x1N#define PDT$C_PA 1 /* CI PORT */N#define PDT$C_PU 2 /* UDA PORT */N#define PDT$C_PE 3 /* NI PORT A*/N#define PDT$C_PS 4 /* PASSTHRU PORT */H/* constant PB equals 5 prefix PDT tag $C; /* VAX:BVP storage port */N#define PDT$C_PI 6 /* DSSI PORT */N#define PDT$C_PL 7 /* Gapless tape port */N#define PDT$C_PW 8 /* SWIFT port */N#define PDT$C_PN 9 /* NPORT */N#define PDT$C_PC 10 A /* PCI-NPORT */N#define PDT$C_PB 11 /* Galaxy SMCI Port */N#define PDT$C_PM 12 /* Memory Channel Port */#define PDT$M_CNTBSY 0x1#define PDT$M_CNTRLS 0x2#define PDT$M_XCNTRS 0x4 #define PDT$M_NON_CI_BHANDLE 0x8#define PDT$M_AFFINITY 0x10N#define PDT$C_BASEVER 0 /*V4.0 drivers */b#define PDT$C_LISTENVER 1 /*V5.0 redesigned listener conneAction state transitions */N#define PDT$C_BALANCEVER 2 /*Dynamic load balancing version */N#define PDT$C_REORGVER 1 /*V5.0 reorganized PDT format */P#define PDT$C_CREDITVER 2 /*Optimistic credit allocation format */X#define PDT$C_NI_CLASS 10 /* NI/SCA performance level port/interconnect */V#define PDT$C_DSSI_MEDIUM_CLASS 48 /* DSSI performance level port/interconnect */Y#define PDT$C_CI_CLASS 140 /* CI performAance level port/interconnect */X#define PDT$C_MC_CLASS 800 /* MC performance level port/interconnect */`#define PDT$C_SM_CLASS 32767 /* Shared Memory performance level port/interconnect */N/* */N#define PDT$C_YELLOW 4 /* Port is in YELLOW zone */N#define PDT$C_RED 6 /* Port is in RED zone */U#define PDT$C_UNEQUAL_PATH 7 /* UAnequal path load sharing (i.e. NI->CI) */N#define PDT$C_CTRSTART 636 /* start of pdt counter area a */P#define PDT$C_STD_CTREND 668 /* end of standard pdt counter area a */N#define PDT$C_STDNO_CTR 7 /* 7 standard counters */S#define PDT$C_EXT_CTRSTART 668 /* start of pdt extended counter area a */P#define PDT$C_EXT_CTREND 776 /* end of standard pdt counter area a */N#define PDT$C_EXTNO_CTR 26 /* 26 extendAed counters */#define SCS$C_EB_MAX_INDEX 9N#define PDT$K_LENGTH 1064 /*SIZE OF PORT-INDEPENDENT PIECE */N#define PDT$C_LENGTH 1064 /*SIZE OF PORT-INDEPENDENT PIECE */N/* OF PDT. */N#define PDT$S_PDTDEF 1064 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _rbun; struct _cdrp; struct _ucb; struct _adp; A#endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pdt {#pragma __nomember_alignmentN struct _pdt *pdt$l_flink; /*LINK TO NEXT SCS PDT */ __union {N unsigned short int pdt$w_portchar; /*Port Characteristics */ __struct {N unsigned pdt$v A_snglhost : 1; /* Port to single host bus */' unsigned pdt$v_fill_0_ : 7;" } pdt$r_portchar_bits;! } pdt$r_portchar_overlay;N char pdtdef$$_fill_2; /* UNUSED BYTE */N unsigned char pdt$b_pdt_type; /* TYPE OF PDT */N unsigned short int pdt$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char pdt$b_type; /*STRUCTURE TYPE = SCS */N unsigned char Apdt$b_subtyp; /*STRUCTURE SUBTYPE */N/* */O/* SCS accesses routines in the port driver via dispatch vectors in the PDT. */P/* There are two sets of vectors, Required entries (must be supplied by every */N/* port driver) and Optional entries (allow port drivers that must do so */N/* to supplant SCS supplied routines). */N/* A */N/* The required entries are defined below, they must have the prefix */N/* PDTVEC and tag L for the INIT_PORT_VECTORS macro to work correctly */N int (*pdtvec$l_allocdg)(); /* ALLOCATE A DG BUFFER */N int (*pdtvec$l_allocmsg)(); /* ALLOCATE A MESSAGE BUFFER */N int (*pdtvec$l_deallocdg)(); /* DEALLOCATE DG BUFFER */N int (*pdtvec$l_deallomsg)(); /* DEALLOCATE MSG BUFFER A */W int (*pdtvec$l_ins_pes_mfreeq)(); /* return MSG buf to port free buffer supply */d int (*pdtvec$l_ins_opt_mfreeq)(); /* return MSG buf to port free buffer supply (optimistic) */d int (*pdtvec$l_rem_opt_mfreeq)(); /* take MSG buf from port free buffer supply (optimistic) */e int (*pdtvec$l_rem_pes_mfreeq)(); /* take MSG buf from port free buffer supply (pessimistic) */S int (*pdtvec$l_add_free_dg)(); /* Give Receive DG buffer to port driver */S int A(*pdtvec$l_rem_free_dg)(); /* take receive DG buffer to port driver */N int (*pdtvec$l_queue_dg)(); /* Queue DG buffer to port driver */N int (*pdtvec$l_reqdata)(); /* REQUEST BLK DATA XFER */N int (*pdtvec$l_senddata)(); /* SEND BLK DATA XFER */N int (*pdtvec$l_senddatawmsg)(); /* send data w/piggyback message */N int (*pdtvec$l_senddg)(); /* SEND A DATAGRAM */N int (*pdtvec$l_sendmsg)(A); /* SEND A MESSAGE */N int (*pdtvec$l_sendmsgl)(); /* SEND A MESSAGE (low priority) */V int (*pdtvec$l_trnmsgh)(); /* return message to sender (high priority) */V int (*pdtvec$l_trnmsgl)(); /* return message to sender (low priority) */P int (*pdtvec$l_readcount)(); /* READ COUNTERS (FMT PORT SPECIFIC) */S int (*pdtvec$l_rlscount)(); /* RELEASE COUNTERS (FMT PORT SPECIFIC) */N int (*pdtvec$l_mreset)(); A /* MAINT RESET OF REMOTE */N int (*pdtvec$l_mstart)(); /* MAINT START OF REMOTE */N int (*pdtvec$l_stop_vcs)(); /* SEND STOP DGS ON ALL VCS */N int (*pdtvec$l_shut_all_vc)(); /* Shutdown all VCs on a port */N int (*pdtvec$l_crash_vc)(); /* Crash (Shut off) a single VC */N int (*pdtvec$l_crash_port)(); /* Shutdown the port */N int (*pdtvec$l_reinit_port)(); /* REINIT A PORTA */S int (*pdtvec$l_flush_vc)(); /* complete outstanding requests on a VC */N int (*pdtvec$l_log_error_scs)(); /* log Packet error for SCS */O int (*pdtvec$l_cleanup_pkt)(); /* return outstanding pakcets to SCS */N int (*pdtvec$l_pb_from_msg)(); /* return PB for message */W int (*pdtvec$l_chk_lost_ack)(); /* check if circuit handshake could complete */N int (*pdtvec$l_remove_pb)(); /* Remove PB if no conneActions */N/* Optional port driver entry point vectors (and reserved vectors). */N/* If these entries are not set by the port driver SCS defaults are used. */N int (*pdt$l_connect)(); /* REQUEST CONNECTION TO REMOTE */N int (*pdt$l_dconnect)(); /* BREAK CONNECTION */V int (*pdt$l_add_scs_hdr)(); /* Add SCS session header to a send message */w int (*pdt$l_cancel_wait)(); /* Cancel a stalled CDRP waiting for a SCSA resource. This vector is required */N/* if port driver stalls for any resource. */e int (*pdt$l_map)(); /* Port-dependent Mapping of a Buffer for a Block Transfer */g int (*pdt$l_unmap)(); /* Port-dependent Unmapping of a Buffer for a Block Transfer */o int (*pdt$l_fast_sendmsg_request)(); /* Port routine to check if Fast Path can be used to send a message */{ int (*pdt$l_fast_sendmsg_ass_res_pm)(); /* Port routine toA associate allocated resources to a Fast Path send message */Z int (*pdt$l_fast_sendmsg_pm)(); /* Port routine to send a message via Fast Path */a int (*pdt$l_alloc_rbun)(); /* Port routine to create port-specific RBUN resources */e int (*pdt$l_dealloc_rbun)(); /* Port routine to deallocate port-specific RBUN resources */d int (*pdt$l_fast_recvmsg_chk_res)(); /* Port routine to check port-specific resources to see */N/* if Fast Path can be used for a received Amessage */O int (*pdt$l_test_crash_port)(); /* Port-dependent Crash Port routine */T int (*pdt$l_test_ins_comqh)(); /* Port-dependent Command Queue Insertion */N int (*pdt$l_test_1_port)(); /* Port-dependent Test 1 vector */N int (*pdt$l_test_2_port)(); /* Port-dependent Test 2 vector */N int (*pdtdef$$_fill_4 [7])(); /*RESERVED VECTORS */N struct _fkb *pdt$l_waitqfl; /*LISTHEAD FOR FORK BLAOCKS WAITING */N struct _fkb *pdt$l_waitqbl; /* FOR NONPAGED POOL */N void *pdt$l_pm_portlock; /* PM portlock data structure */T struct _rbun *pdt$l_rbun_list; /* Singly linked list of resource bundles */N unsigned int pdt$l_rbun_length; /* Port-specific length of a RBUN */N unsigned int pdt$l_rbun_pooltype; /* Port-specific pooltype for RBUN */N/* allocation/deallocation */^ A unsigned int pdt$l_non_fp_sendmsgs; /* Counter of number of non-Fast Path send messages */a unsigned int pdt$l_non_fp_rcvdmsgs; /* Counter of number of non-Fast Path receive messages */V/* FILL_10 longword fill prefix PDTDEF tag $$; /* Filler for quadword alignment */N/* Keep QUADWORD aligned: */ __union {N unsigned int pdt$l_dghdrsz; /*DATAGRAM HEADER SIZE */N unsigned int pdt$l_msghdrsz; /*MESSAG AE HEADER SIZE */ } pdt$r_hdrsz_overlay;N unsigned int pdt$l_dgovrhd; /*DATAGRAM HEADER SIZE */N/* ^^^ Obsolete field */N unsigned int pdt$l_maxbcnt; /*MAXIMUM TRANSFER BCNT */ __union {N unsigned short int pdt$w_flags; /*PORT FLAGS */ __struct {N unsigned pdt$v_cntbsy : 1; /* COUNTERS IN USE */N A unsigned pdt$v_cntrls : 1; /* RELEASE COUNTERS */O unsigned pdt$v_xcntrs : 1; /* port supports block xfer counters */T unsigned pdt$v_non_ci_bhandle : 1; /* Port uses non-CI buffer handles */_ unsigned pdt$v_affinity : 1; /* Set if user has specified affinity for this port */' unsigned pdt$v_fill_1_ : 3; } pdt$r_flags_bits; } pdt$r_flags_overlay;N short int pdtdef$$_fill_5; /*RESERVED WORD A */N char pdt$t_cntowner [16]; /*NAME OF SYSAP USING COUNTERS */N struct _cdrp *pdt$l_cntcdrp; /*CDRP OF SYSAP READING COUNTERS */N unsigned int pdt$l_pollsweep; /*# SECONDS TO DO A POLLER SWEEP */N struct _ucb *pdt$l_ucb0; /*ADDR OF UCB. */N struct _adp *pdt$l_adp; /*ADDR OF ADP. */N unsigned int pdt$l_max_vctmo; /*Maximum VC timeout */N A unsigned short int pdt$w_scsversion; /*SCSLOA version */N unsigned short int pdt$w_ppdversion; /*PPD driver version */N int (*pdt$l_load_vector)(); /*Load vector */w unsigned short int pdt$w_load_class; /*Load class (higher arbitrary numbers for higher interconnect performance) */N/* class = 0 for default lowest performance level */N/* Interconnect specific load class values (~= Raw HW BW in Mb/S):A */X/* (TYC 15-Feb-89) Dynamic Load Sharing Specific Counters and Fields */N/* */X short int pdtdef$$_fill_6; /* (TYC 24-Mar-89) quadword align queues here */N unsigned __int64 pdt$q_pb; /* Queue header for path blocks */\ unsigned __int64 pdt$q_conn_wait; /* Queue header for CDTs in Load Share Wait Queue */^ unsigned __int64 pdt$q_yellow; /* Queue header foAr CDTs in Load Share Yellow Queue */[ unsigned __int64 pdt$q_red; /* Queue header for CDTs in Load Share Red Queue */` unsigned __int64 pdt$q_disabled; /* Queue header for CDTs in Load Share Disabled Queue */P unsigned int pdt$l_port_map; /* 32-bit load sharing domain bit map */N int pdt$l_avail_thruput; /* Port's available throughput */N unsigned int pdt$l_load_rating; /* Port load share rating */N unsigned int pdt$l_time_stamp;A /* Load sharing port time stamp */N/* Load share thresholds */N unsigned int pdt$l_saturation_pt; /* Port saturation point */U unsigned int pdt$l_max_thruput_threshold; /* Port maximum throughput threshold */U unsigned int pdt$l_min_thruput_threshold; /* Port minimum throughput threshold */O unsigned int pdt$l_tolerance_threshold; /* Port load tolerance threshold */N/* Filler for quadword alignment: A */ N/* Load sharing data transfer counters */U unsigned int pdt$l_bytes_dg_xmt; /* Total bytes xmitted by port for DG only */S unsigned int pdt$l_bytes_dg_rcv; /* Total bytes rcv'd by port for DG only */V unsigned int pdt$l_bytes_msg_xmt; /* Total bytes xmitted by port for MSG only */T unsigned int pdt$l_bytes_msg_rcv; /* Total bytes rcv'd by port for MSG only */T unsigned int pdt$l_bytes_mapped;A /* Total bytes mapped by port for BT only */N unsigned int pdt$l_dg_xmt; /* Total DGs xmitted by port */N unsigned int pdt$l_dg_rcv; /* Total DGs rcv'd by port */N unsigned int pdt$l_msg_xmt; /* Total MSGs xmitted by port */N unsigned int pdt$l_msg_rcv; /* Total MSGs rcv'd by port */] unsigned __int64 pdt$q_bytes_xfer; /* Total bytes xferred by port (both XMIT and RCV) */U unsigned int pdt$l_num_map; A/* (TYC0001) # of map operations completed */P unsigned int pdt$l_port_cmd; /* Total # of port commands placed on */N/* queue when the queue is not empty */N/* (this is a conditional counter) */N/* Filler for quadword alignment: */ char pdtdef$$_fill_55 [4];W unsigned int pdt$l_bytes_dg_xmt_last; /* Total bytes xmitted by port for DG only */N/* up to lastA load sharing interval */U unsigned int pdt$l_bytes_dg_rcv_last; /* Total bytes rcv'd by port for DG only */N/* up to last load sharing interval */Y unsigned int pdt$l_bytes_msg_xmt_last; /* Total bytes xmitted by port for MSG only */N/* up to last load sharing interval */W unsigned int pdt$l_bytes_msg_rcv_last; /* Total bytes rcv'd by port for MSG only */N/* up to Alast load sharing interval */V unsigned int pdt$l_bytes_mapped_last; /* Total bytes mapped by port for BT only */N/* up to last load sharing interval */N unsigned int pdt$l_dg_xmt_last; /* Total DGs xmitted by port */N/* up to last load sharing interval */N unsigned int pdt$l_dg_rcv_last; /* Total DGs rcv'd by port */N/* up to last load sharing Ainterval */N unsigned int pdt$l_msg_xmt_last; /* Total MSGs xmitted by port */N/* up to last load sharing interval */N unsigned int pdt$l_msg_rcv_last; /* Total MSGs rcv'd by port */N/* up to last load sharing interval */N unsigned __int64 pdt$q_bytes_xfer_last; /* Total bytes xferred by port */N/* up to last load sharing interval A */U unsigned int pdt$l_num_map_last; /* (TYC0001) # of map operations completed */N/* by port up to last load sharing interval */P unsigned int pdt$l_port_cmd_last; /* Total # of port commands placed on */N/* queue when the queue is not empty */N/* up to last load sharing interval */N/* (this is a conditional counter) A */N int pdtdef$$_fill_66; /* Filler for quadword alignment */Q unsigned int pdt$l_bytes_xfer_int; /* (TYC 31-AUG-89) TOTAL BYTES XFERRED */N/* DURING LAST LOAD SHARING INTERVAL */[ unsigned int pdt$l_equal_path_call_count; /* Number of equal path move requests made */N/* to connections on this port */_ unsigned int pdt$l_unequal_path_call_count; /* Number of unequal path moveA requests made */N/* to connections on this port */] unsigned int pdt$l_connection_move_count; /* Number of connection moves from this port */N/* */N/* (TYC 27-Feb-89) peak counters used with conditional assembly */R unsigned int pdt$l_bytes_dg_xmt_peak; /* Peak value of total bytes xmitted */N/* by port for DG only A */P unsigned int pdt$l_bytes_dg_rcv_peak; /* Peak value of total bytes rcv'd */N/* by port for DG only */S unsigned int pdt$l_bytes_msg_xmt_peak; /* Peak value of total bytes xmitted */N/* by port for MSG only */Q unsigned int pdt$l_bytes_msg_rcv_peak; /* Peak value of total bytes rcv'd */N/* by port for MSG only */QA unsigned int pdt$l_bytes_mapped_peak; /* Peak value of total bytes mapped */N/* by port for BT only */U unsigned int pdt$l_dg_xmt_peak; /* Peak value of total DGs xmitted by port */S unsigned int pdt$l_dg_rcv_peak; /* Peak value of total DGs rcv'd by port */V unsigned int pdt$l_msg_xmt_peak; /* Peak value of total MSGs xmitted by port */T unsigned int pdt$l_msg_rcv_peak; /* Peak value of total MSGs rcv'd by porAt */T unsigned __int64 pdt$q_bytes_xfer_peak; /* Peak value of total bytes xferred */N/* by port (both XMIT and RCV) */^ unsigned int pdt$l_port_cmd_peak; /* Peak value of total # of port commands placed on */N/* queue when the queue is not empty */N/* */N/* (TYC 27-Feb-89) average counters used with conditional assembly */AT unsigned int pdt$l_bytes_dg_xmt_avg; /* Average value of total bytes xmitted */N/* by port for DG only */R unsigned int pdt$l_bytes_dg_rcv_avg; /* Average value of total bytes rcv'd */N/* by port for DG only */U unsigned int pdt$l_bytes_msg_xmt_avg; /* Average value of total bytes xmitted */N/* by port for MSG only */S unAsigned int pdt$l_bytes_msg_rcv_avg; /* Average value of total bytes rcv'd */N/* by port for MSG only */S unsigned int pdt$l_bytes_mapped_avg; /* Average value of total bytes mapped */N/* by port for BT only */X unsigned int pdt$l_dg_xmt_avg; /* Average value of total DGs xmitted by port */V unsigned int pdt$l_dg_rcv_avg; /* Average value of total DGs rcv'd by port */Y A unsigned int pdt$l_msg_xmt_avg; /* Average value of total MSGs xmitted by port */W unsigned int pdt$l_msg_rcv_avg; /* Average value of total MSGs rcv'd by port */V unsigned __int64 pdt$q_bytes_xfer_avg; /* Average value of total bytes xferred */N/* by port (both XMIT and RCV) */a unsigned int pdt$l_port_cmd_avg; /* Average value of total # of port commands placed on */N/* queue when the queue is not empty A */N/* (TYC 22-Jun-89) Moved down here to longword-align */d unsigned char pdt$b_ls_flag; /* Load share flag, if set, load sharing disabled for now */N char pdt$t_fill_0 [3]; /* align long. */R unsigned int pdt$l_stdno_ctr; /* Total number of standard of counters */N unsigned int pdt$l_path0_ack; /* Total Acks received on path 0. */N unsigned int pdt$l_path0_nak; /* Total Naks receAived on path 0. */N unsigned int pdt$l_path0_nrsp; /* Total NRSPs received on path 0. */N unsigned int pdt$l_path1_ack; /* Total Acks received on path 1. */N unsigned int pdt$l_path1_nak; /* Total Naks received on path 1. */N unsigned int pdt$l_path1_nrsp; /* Total NRSPs received on path 1. */N unsigned int pdt$l_dg_disc; /* Total Datagrams discarded. */N unsigned int pdt$l_extno_ctr; /* Total number of port extended */N Aunsigned int pdt$l_spare1_cnt; /* Spare counter 1. */N unsigned int pdt$l_spare2_cnt; /* Spare counter 2. */N unsigned int pdt$l_spare3_cnt; /* Spare counter 3. */N unsigned int pdt$l_spare4_cnt; /* Spare counter 4. */ __union { __struct {U unsigned int pdt$l_snddat_oper_snt; /* Send Data operations completed. */a unsigned int pdt$l_snddat_data_snt; /* Bytes of SNDDAAT sent by Send Data commands. */Z unsigned int pdt$l_snddat_bodies_snt; /* SNDDAT Data bodies sent from host. */R unsigned int pdt$l_reqdat_oper_snt; /* REQDAT operations completed. */f unsigned int pdt$l_retdat_data_rcv; /* Bytes of data received by host in RETDAT bodies. */\ unsigned int pdt$l_retdat_bodies_rcv; /* RETDAT Data bodies received by host. */e unsigned int pdt$l_sntdat_bodies_rec; /* SNTDAT bodies received and delivered to hos At. */` unsigned int pdt$l_sntdat_data_rec; /* Bytes of 'DATA' received in SNTDAT bodies. */N unsigned int pdt$l_cnf_snt; /* Block Data confirmations sent. */O unsigned int pdt$l_datreq_bodies_rcv; /* DATREQ bodies received. */Z unsigned int pdt$l_retdat_bodies_snt; /* RETDAT Data bodies sent from host. */S unsigned int pdt$l_retdat_data_snt; /* Bytes of data sent by RETDAT. */ } pdt$r_ext_std; __struct {P A unsigned int pdt$l_np_sntdat_bodies_snt; /* Sent Data bodies sent */U unsigned int pdt$l_np_sntdat_data_snt; /* No. of data bytes via SNDDAT */T unsigned int pdt$l_np_cnf_bodies_rcv; /* No. Confirm bodies received */U unsigned int pdt$l_np_reqdat_oper_cmp; /* REQDAT operations completed. */_ unsigned int pdt$l_np_retdat_bodies_rcv; /* RETDAT Data bodies received by host. */i unsigned int pdt$l_np_retdat_data_rcv; /* Bytes of data receAived by host in RETDAT bodies. */h unsigned int pdt$l_np_sntdat_bodies_rcv; /* SNTDAT bodies received and delivered to host. */c unsigned int pdt$l_np_sntdat_data_rcv; /* Bytes of 'DATA' received in SNTDAT bodies. */V unsigned int pdt$l_np_cnf_bodies_snt; /* Block Data confirmations sent. */R unsigned int pdt$l_np_reqdat_bodies_rcv; /* DATREQ bodies received. */] unsigned int pdt$l_np_retdat_bodies_snt; /* RETDAT Data bodies sent from host. A */V unsigned int pdt$l_np_retdat_data_snt; /* Bytes of data sent by RETDAT. */ } pdt$r_ext_np;% } pdt$r_ext_counters_overlay;N unsigned int pdt$l_dgsnt; /* DG bodies sent */N unsigned int pdt$l_dg_txt_snt; /* Bytes of DG TEXT Sent */N unsigned int pdt$l_msg_snt; /* MSG bodies sent */N unsigned int pdt$l_msg_txt_snt; /* Bytes of MSG TEXT Sent */N unsigned int pdt$lA_misc_snt; /* All other opcode bodies sent */W unsigned int pdt$l_dg_rec; /* DG bodies received and delivered to host. */Y unsigned int pdt$l_dg_txtrec; /* Bytes of dg received and delivered to host. */N unsigned int pdt$l_msg_rec; /* MSG bodies received. */_ unsigned int pdt$l_msg_txt_rec; /* Bytes of msg text received and delivered to host. */N unsigned int pdt$l_misc_rec; /* All other bodies received. */P unsiAgned int pdt$l_snddat_data_snt_last; /* Bytes of SNDDAT sent by Send */N/* Data commands up to last load */N/* sharing interval */V unsigned int pdt$l_snddat_oper_snt_last; /* # of Send Data operations from host */N/* up to last load sharing interval */T unsigned int pdt$l_retdat_data_rcv_last; /* Bytes of data received by host in */N/* RETDAT bodies Aup to last load */N/* sharing interval */W unsigned int pdt$l_reqdat_oper_snt_last; /* # of REQDAT operations completed by */N/* host up to last load share interval */Q unsigned int pdt$l_cnf_snt_last; /* # of Block Data confirmations sent */N/* up to last load share interval */\ unsigned int pdt$l_sntdat_Adata_rec_last; /* Bytes of 'DATA' received in SNTDAT bodies */N/* up to last load sharing interval */P unsigned int pdt$l_datreq_bodies_rcv_last; /* # of DATREQ bodies received */N/* up to last load sharing interval */U unsigned int pdt$l_retdat_data_snt_last; /* Bytes of data sent by RETDAT up to */N/* last load sharing interval */N unsigned int pdt$l_avg_xfer_Asize; /* Average transfer size used in */N/* calculating port's effective bandwidth */U unsigned int pdt$l_eb_table; /* address of Ports Effec. Bandwidth table */N int pdtdef$$_fill_77; /* Filler for quadword alignment */W void *pdt$q_formpb [2]; /* Listhead of formative PB's from this port */^ unsigned short int pdt$w_pbcount; /* # PB's (non-formative) associated with this PDT */N short int pdtdef$$_f Aill_7; /* Ensure longword alignment */ __union {N unsigned char pdt$b_port_num; /* Local port number */) unsigned char pdt$t_port_num [6];! } pdt$r_port_num_overlay; __union {N unsigned char pdt$b_max_port; /* Maximum port number */) unsigned char pdt$t_max_port [6];! } pdt$r_max_port_overlay;N unsigned int pdt$l_curcnt; /* time (secs) till next RDCNT */[ unsigned int pAdt$l_pooldue; /* time when message buffer should be available */] void *pdt$l_bdlt; /* addr. or port independent portion of ports BDLT */ N/* be quadword aligned: */U unsigned char pdt$b_scs_maint_block [16]; /*Add a Maintenance block to the CDT */N/* which must be quadword aligned */ N unsigned int pdt$l_tqeaddr; /* Address store for VC check TQE */ AY unsigned int pdt$l_timvcfail; /* Value for previous value of G^SGN$TIMVCFAIL */ __union {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifT unsigned __int64 pdt$q_mgt_handles; /* Managed & Managing object handles. */#pragma __nomember_alignment __struct {N unsigned int pdt$l_mgt_handle; /* Managed object handle A */N unsigned int pdt$l_mgt_mgr_handle; /* Managing object handle */& } pdt$r_mgt_handles_struc;$ } pdt$r_mgt_handles_overlay;V int pdt$l_mgt_priority; /* Management assigned port priority value. */N unsigned int pdt$l_mgt_req; /* Count of management requests */N unsigned int pdt$l_mgt_req_bytes; /* Cout of management request bytes */N unsigned int pdt$l_mgt_err; /* Mgt error count */N unsiAgned int pdt$l_mgt_rsp; /* Mgt responses */N unsigned int pdt$l_mgt_rsp_bytes; /* Bytes of response data */N unsigned int pdt$l_mgt_cont; /* Continuation flag */Q unsigned int pdt$a_last_rsp_hdr; /* Address of last management response */R unsigned int pdt$l_return_func; /* Function code returned in a response */ unsigned int pdt$l_num_ret;$ unsigned int pdt$l_return_major;$ unsigned int pdt$l_return_minoAr;" unsigned int pdt$l_cont_trace; unsigned int pdt$l_cont_seq;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN char pdt$r_trace [120]; /* TRACE CONTEXT */ } PDT; #if !defined(__VAXC)<#define pdt$w_portchar pdt$r_portchar_overlay.pdt$w_portcharP#define pdt$v_snglhost pdt$r_portchar_overlay.pdt$r_portchar_b Aits.pdt$v_snglhost7#define pdt$l_dghdrsz pdt$r_hdrsz_overlay.pdt$l_dghdrsz9#define pdt$l_msghdrsz pdt$r_hdrsz_overlay.pdt$l_msghdrsz3#define pdt$w_flags pdt$r_flags_overlay.pdt$w_flagsF#define pdt$v_cntbsy pdt$r_flags_overlay.pdt$r_flags_bits.pdt$v_cntbsyF#define pdt$v_cntrls pdt$r_flags_overlay.pdt$r_flags_bits.pdt$v_cntrlsF#define pdt$v_xcntrs pdt$r_flags_overlay.pdt$r_flags_bits.pdt$v_xcntrsV#define pdt$v_non_ci_bhandle pdt$r_flags_overlay.pdt$r_flags_bits.pdt$v_non_ci_bhandleJ#define pdAt$v_affinity pdt$r_flags_overlay.pdt$r_flags_bits.pdt$v_affinity\#define pdt$l_snddat_oper_snt pdt$r_ext_counters_overlay.pdt$r_ext_std.pdt$l_snddat_oper_snt\#define pdt$l_snddat_data_snt pdt$r_ext_counters_overlay.pdt$r_ext_std.pdt$l_snddat_data_snt`#define pdt$l_snddat_bodies_snt pdt$r_ext_counters_overlay.pdt$r_ext_std.pdt$l_snddat_bodies_snt\#define pdt$l_reqdat_oper_snt pdt$r_ext_counters_overlay.pdt$r_ext_std.pdt$l_reqdat_oper_snt\#define pdt$l_retdat_data_rcv pdt$r_ext_counters_overlay.pdtA$r_ext_std.pdt$l_retdat_data_rcv`#define pdt$l_retdat_bodies_rcv pdt$r_ext_counters_overlay.pdt$r_ext_std.pdt$l_retdat_bodies_rcv`#define pdt$l_sntdat_bodies_rec pdt$r_ext_counters_overlay.pdt$r_ext_std.pdt$l_sntdat_bodies_rec\#define pdt$l_sntdat_data_rec pdt$r_ext_counters_overlay.pdt$r_ext_std.pdt$l_sntdat_data_recL#define pdt$l_cnf_snt pdt$r_ext_counters_overlay.pdt$r_ext_std.pdt$l_cnf_snt`#define pdt$l_datreq_bodies_rcv pdt$r_ext_counters_overlay.pdt$r_ext_std.pdt$l_datreq_bodies_rcv`#definAe pdt$l_retdat_bodies_snt pdt$r_ext_counters_overlay.pdt$r_ext_std.pdt$l_retdat_bodies_snt\#define pdt$l_retdat_data_snt pdt$r_ext_counters_overlay.pdt$r_ext_std.pdt$l_retdat_data_snte#define pdt$l_np_sntdat_bodies_snt pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_sntdat_bodies_snta#define pdt$l_np_sntdat_data_snt pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_sntdat_data_snt_#define pdt$l_np_cnf_bodies_rcv pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_cnf_bodies_rcva#define pdt$l_np_rAeqdat_oper_cmp pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_reqdat_oper_cmpe#define pdt$l_np_retdat_bodies_rcv pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_retdat_bodies_rcva#define pdt$l_np_retdat_data_rcv pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_retdat_data_rcve#define pdt$l_np_sntdat_bodies_rcv pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_sntdat_bodies_rcva#define pdt$l_np_sntdat_data_rcv pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_sntdat_data_rcv_#define pdt$l_npA_cnf_bodies_snt pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_cnf_bodies_snte#define pdt$l_np_reqdat_bodies_rcv pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_reqdat_bodies_rcve#define pdt$l_np_retdat_bodies_snt pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_retdat_bodies_snta#define pdt$l_np_retdat_data_snt pdt$r_ext_counters_overlay.pdt$r_ext_np.pdt$l_np_retdat_data_snt<#define pdt$b_port_num pdt$r_port_num_overlay.pdt$b_port_num<#define pdt$t_port_num pdt$r_port_num_overlay.pdt$t_po Art_num<#define pdt$b_max_port pdt$r_max_port_overlay.pdt$b_max_port<#define pdt$t_max_port pdt$r_max_port_overlay.pdt$t_max_portE#define pdt$q_mgt_handles pdt$r_mgt_handles_overlay.pdt$q_mgt_handles[#define pdt$l_mgt_handle pdt$r_mgt_handles_overlay.pdt$r_mgt_handles_struc.pdt$l_mgt_handlec#define pdt$l_mgt_mgr_handle pdt$r_mgt_handles_overlay.pdt$r_mgt_handles_struc.pdt$l_mgt_mgr_handle"#endif /* #if !defined(__VAXC) */ #define PDT$C_PAMAC_VER 2N/* A */#define PDT$M_PWF_CLNUP 0x1#define PDT$M_PUP 0x2#define PDT$M_LBDG 0x4#define PDT$M_NEW_RSP 0x8#define PDT$M_REQID_SNT 0x10#define PDT$M_INSTR_SNT 0x20#define PDT$M_CLSCKT 0x40#define PDT$M_LOCAL 0x80#define PDT$M_LOOK_ASIDE 0x100N#define PDT$C_PQB 1096 /* Base of PQB */N#define PDT$Q_COMQBASE 1096 /* Base of queue headers */#define PDT$C_QELOGEND 1480#define PDT$C_PAPQBENDA 1608#define PDT$C_RESP_CNT 100 #define PDT$C_MFQ_THRESHOLD -100#define PDT$C_MFQ_INCREMENT 30N#define PDT$C_HSHUT_SIZ 28 /* Shutdown DG itself */#define PDT$C_LASTGASP_DG 1784N#define PDT$C_SETCKT_SIZ 36 /* SETCKT DG itself */#define PDT$M_M 0x70000000#define PDT$C_DEFCNTR 60#define PDT$C_ERLCNTR 86400 #define PDT$C_SPEC_CTRSTART 2164#define PDT$C_SPECNO_CTR 14#define PDT$C_SPEC_CTREND 2224 #define PDT$C_SPEC_CTR_LENGTH 60A#define PDT$C_SCSLENGTH 2224#define PDT$C_PAREGBASE 2224#define PDT$C_PAREGEND 2340#define PDT$C_PALENGTH 2352N#define PDT$S_PAPDTDEF 2352 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _adp; #endif /* #ifdef __cplusplus */ #pragma __nomember_alignmenttypedef struct _papdt {N/* */N/* Skip the common PDT A */N/* */( unsigned char pdt$b_pdt_fill [1064];N/* */N/* Define private PA fields */N/* */N/* All bits in PDT$L_IPORT_STS and PDT$W_LPORT_STS are uniquely defined */N/* to test for coding errors! A */N/* */N __union { /* Interlocked (SMP) Port status */ __struct {O unsigned pdt$v_pwf_clnup : 1; /* Power fail cleanup in progress */N unsigned pdt$v_pup : 1; /* Power up has occurred */' unsigned pdt$v_fill_6_ : 6;# } pdt$r_iport_sts_bits;% unsigned int pdt$l_iport_s Ats;" } pdt$r_iport_sts_overlay;N __union { /* Port status (SCS lock) */ __struct {% unsigned pdt$v_fill1 : 2;N unsigned pdt$v_lbdg : 1; /* 0/1 for LB dg's disabled/ */N/* enabled on this port */N unsigned pdt$v_new_rsp : 1; /* New Response timeout check */N/* Cleared every polling */N/*A interval and set when a */N/* response is dequeued from */N/* the response queue. */N unsigned pdt$v_reqid_snt : 1; /* Polling activity check -- */N/* Set when the poller sends */N/* a REQID to enable the port */N/* timeout mechanism. A */N unsigned pdt$v_instr_snt : 1; /* BVP instruction in progress */N unsigned pdt$v_clsckt : 1; /* PB stalled because a close */N/* circuit datagram is in use */N unsigned pdt$v_local : 1; /* This is a local (BVP) port */N/* This bit is used for */N/* interpretation of the MSTART A */N/* and MRESET functions. */P unsigned pdt$v_look_aside : 1; /* This port can allocate message */N/* packets directly from the */N/* lookaside list */' unsigned pdt$v_fill_7_ : 7;# } pdt$r_lport_sts_bits;+ unsigned short int pdt$w_lport_sts;" } pdt$r_lport_sts_overlaAy; short int pdt$w_fill2;N unsigned int pdt$l_clsckt_dg; /* Close circuit datagram */N/* stored here to guarantee */N/* circuit shutdown even though */N/* there is no pool. */N unsigned int pdt$l_adapter; /* Base of register space -- */N/* used because the CNF is A */N/* not at the base for the */N/* BCI750. */N/* be quadword aligned: */ N/* be quadword aligned: */ __union {N unsigned __int64 pdt$q_dfreeq; /* Datagram free queue header */ __struct {% void *pdt$l_dfreeq_flink;% void * Apdt$l_dfreeq_blink; } pdt$r_fill_3_; } pdt$r_fill_2_; __union {N unsigned __int64 pdt$q_mfreeq; /* Message free queue header */ __struct {% void *pdt$l_mfreeq_flink;% void *pdt$l_mfreeq_blink; } pdt$r_fill_5_; } pdt$r_fill_4_;N unsigned __int64 pdt$q_comql; /* Listhead for command */N/* queue 0, low priority */N unsigned _A_int64 pdt$q_comqh; /* Listhead for command */N/* queue 1, high priority */N unsigned __int64 pdt$q_comq2; /* Listhead for command */N/* queue 2 */N unsigned __int64 pdt$q_comq3; /* Listhead for command */N/* queue 3 */N unsigned __int64 pdt$q_rspq; A/* Listhead for response */N/* queue */N void *pdt$l_dfqhdr; /* Addr of DG free queue */N/* listhead */N void *pdt$l_mfqhdr; /* Addr of MSG free queue */N/* listhead */N unsigned short int pdt$w_dqelen; /* DG free Q entry length A */N short int pdt$w_fill3; /* MBZ word */N unsigned short int pdt$w_mqelen; /* MSG free Q entry length */N short int pdt$w_fill4; /* MBZ word */N void *pdt$l_vpqb; /* VA of PQB base */N void *pdt$l_vbdt; /* VA of BDT base */N unsigned short int pdt$w_bdtlen; /* # of entries in BDT */N short inAt pdt$w_fill5; /* MBZ word */N void *pdt$l_sptbase; /* PA of base of SPT */N unsigned int pdt$l_sptlen; /* # of entries in SPT */N void *pdt$l_gptbase; /* VA of base of GPT */N unsigned int pdt$l_gptlen; /* # of entries in GPT */ __union {N unsigned int pdt$l_keepalive; /* Port keepalive interval */N unsigned int pAdt$l_vc_check; /* Virtual circuit checking */N/* interval */ } pdt$r_fill6;N unsigned int pdt$l_func_mask; /* Function mask */ char pdt$b_fill7 [164];N unsigned int pdt$l_dqelogout [16]; /* DGs held by port on */N/* powerfailure */N unsigned int pdt$l_mqelogout [16]; /* MSGs held by port on A */N/* powerfailure */ char pdt$b_fill8 [128];N unsigned __int64 pdt$q_uninit_timeout; /* Timeout value to use during */N/* intialization sequeunces */N unsigned __int64 pdt$q_crrr_cache_que; /* Carrier queue cache */N unsigned __int64 pdt$q_qbuf_cache_que; /* QBufqueue cache */N unsigned __int64 pdt$q_type1_cache_que; /* Type 1 array queue cachAe */N unsigned int pdt$l_ins_comql; /* Notify port of non-empty CMDQ0 */N unsigned int pdt$l_ins_comqh; /* Notify port of non-empty CMDQ1 */N unsigned int pdt$l_ins_dfreq; /* Notify port of non-empty DFQ */N unsigned int pdt$l_ins_mfreq; /* Notify port of non-empty MFQ */N unsigned int pdt$l_trc_flag; /* Control bits for tracing */N void *pdt$l_trc_buf; /* Pointer to allocated trace */H/* buffer A */N int (*pdt$l_trc_cmdql)(); /* Vector for tracing CMDQL */N int (*pdt$l_trc_cmdqm)(); /* Vector for tracing CMDQM */N int (*pdt$l_trc_cmdqh)(); /* Vector for tracing CMDQH */N int (*pdt$l_trc_rsp)(); /* Vector for tracing PROC_RSP */N int (*pdt$l_proc_rsp)(); /* Runtime vector for processing */N/* responses. A */N unsigned int pdt$l_debugcheck; /* Debugging bugcheck flags */N unsigned int pdt$l_resp_cnt; /* Number of responses to be */N/* removed from the response */N/* queue before reforking */N unsigned int pdt$l_mfq_deficit; /* Dynamic message free queue */N/* deficit. If negative, one A */N/* message free queue entry has */N/* been allocated for each SCA */N/* credit. If positive, then */N/* represents the number of */N/* SCA-required credits which */N/* have not been allocated to */N/* the message freeA queue. */N unsigned int pdt$l_mfq_threshold; /* Dynamic message threshold */N/* increment. This value */N/* is the change in */N/* PDT$L_MFQ_THRESHOLD whenever */N/* a message free queue empty */N/* interrupt indicates that the B */N/* optimistic credit allocation */N/* has been too optimistic. */N unsigned int pdt$l_mfq_increment; /* Number to change the threshold */N/* by. Make this large to */N/* avoid a cascade of MFQE */N/* interrupts and a possible B */N/* port timeout during the */N/* handling of these interrupts */N unsigned int pdt$l_mfqe_count; /* Count of MFQE interrupts */N unsigned int pdt$l_dgnethd; /* Network header size */N unsigned int pdt$l_dgallocsz; /* Datagram allocation size */N unsigned int pdt$l_scs_offset; /* Offset of SCS header */T unsigned int pBdt$l_sprt_offset; /* Offset into PPD of source port address */Y unsigned int pdt$l_dprt_offset; /* Offset into PPD of destination port address */N/* Normally zero except for ports */N/* which support subnode addressing */N unsigned int pdt$l_ppd_sub; /* Extension for subnode addressing */N/* Zero for nonsubnode type ports */N/* B */N/* Host shutdown datagram fields -- used by both CI and BVP ports to short- */N/* circuit cluster and disk timeouts. As part of shutting down a system */N/* all VCs must be closed with a setckt DG before issuing the last gasp DG. */N/* This prevents data corruption problems from occurring in a multiple port */N/* system. The setckt DG and last gasp DG use the same area of memory to */N/* guarantee they are sent out B */N/* */N unsigned __int64 pdt$q_temp_rspq; /* Temporary response queue to */N/* hold responses dequeued */N/* during send of host */N/* shutdown datagram */ char pdt$b_octa_fill2 [4];& unsigned char pdt$b_hshut_dg [28]; inBt pdt$l_fill9 [3];' unsigned char pdt$b_setckt_dg [36];N/* */N/* Maximum packet multiple which may be used by the local port. This field */Q/* is minimized with the maximum packet multiple supported by the remote port. */N/* For performance reasons, the actual packet multiple is shifted to bits */N/* 30:28 to correspond with their positions in the message body. */N/* B */ __union { __struct {' unsigned pdt$v_fill10 : 28;! unsigned pdt$v_m : 3;& unsigned pdt$v_fill11 : 1;$ } pdt$r_lport_mult_bits;& unsigned int pdt$l_lport_mult;# } pdt$r_lport_mult_overlay; int pdt$l_fill12 [10];N unsigned int pdt$l_vc_chkdue; /* Next due time for VC checking */N unsigned int pdt$l_pollerdue; /* Due time for configuration */N/* poBller */N unsigned char pdt$b_portmap [32]; /* Bitmap of ports */N/* we've heard from */N unsigned char pdt$b_plogmap [32]; /* Bitmap of ports we've logged */N/* with improper nodename and/or */N/* SYSID, to whom we won't talk */N unsigned char pdt$b_dqimap [B32]; /* Datagram inhibit mask */N unsigned char pdt$b_fsnmap [32]; /* Full sequence number mask */N unsigned char pdt$b_samap [32]; /* Subnode addressing mask */N unsigned char pdt$b_nadpmap [32]; /* Non Alternating Dual Path mask */N unsigned char pdt$b_rdpmap [32]; /* RDP mask */N unsigned int pdt$l_setcktmsk; /* SETCKT bit mask */N unsigned char pdt$b_nxt_port; /* # of next port  Bto poll */N unsigned char pdt$b_reqidps; /* Path select value for */N/* configuration poller */N unsigned char pdt$b_p0_lbsts; /* Status of current */N unsigned char pdt$b_p1_lbsts; /* and previous LB DG */N/* tests for paths 0/1 */N/* FILL13 word fill; */N/*  BKeep QW aligned: */N void *pdt$l_lbdg; /* Addr of template loopback */N/* datagram */N unsigned short int pdt$w_stdgdyn; /* # DGs queued for IDREQc */N/* used in start handshakes and */N/* finding out about bad paths */N unsigned short int pdt$w_s Btdgused; /* # ports that we know of that */N/* will be sending IDRECs */ short int pdt$w_fill14;N char pdt$b_align2 [6]; /* QUADWORD ALIGN */N void *pdt$l_rdcntdg; /* Address of RDCNT Datagram */N unsigned int pdt$l_spare5; /* Spare entry */T unsigned int pdt$l_defcntr; /* Default Counter update rate in seconds */T unsigned int pdt B$l_curcntr; /* Current Counter update rate in seconds */U unsigned int pdt$l_erlcntr; /* Errorlog Counter update rate in seconds */{ unsigned int pdt$l_curerlcnt; /* Current Error log count (how many sec left till report counters to error log) */V unsigned int pdt$l_cntusers; /* Number of users requesting counters addr */O unsigned __int64 pdt$q_last_err; /* Time of last port corrected error */R unsigned __int64 pdt$q_time_rdcnt; /* Time of last  BRDCNT response returned */N/* */N/* CIXCD port-specific counters */N/* */W unsigned int pdt$l_specno_ctr; /* Total number of port specific of counters */^ unsigned int pdt$l_pckt_rcrc; /* Total number of packets received with CRC errors */X unsigned int pdt$l_port_idle; /* Amount ofB time time port is idle (seconds) */N unsigned int pdt$l_rspr_wpe; /* Responder Register write PEs */N unsigned int pdt$l_mbpb_wpe; /* Mover B Packet Buffer PEs */N unsigned int pdt$l_cmdr_wpe; /* Commander Register write PEs */N unsigned int pdt$l_intr_wpe; /* Interrupt Register write PEs */N unsigned int pdt$l_mar_wpe; /* Mover A Register write PEs */N unsigned int pdt$l_mbr_wpe; /* Mover B Register write PEBs */N unsigned int pdt$l_mpb_rpe; /* MCWI Packet Buffer Read PEs */N unsigned int pdt$l_tbuf_pe; /* Transmit Buffer parity error */N unsigned int pdt$l_mib_pe; /* MCDP Internal Bus PEs */N unsigned int pdt$l_mcwi_pe; /* MCWI PEs */N unsigned int pdt$l_yreg_pe; /* MCDP YREG PEs */N unsigned int pdt$l_xreg_pe; /* MCDP XREG PEs */N unsigned iBnt pdt$l_cnf; /* Configuration register */O unsigned int pdt$l_pmc; /* Port maintenance/control register */O unsigned int pdt$l_madr; /* Port maintenance address register */N unsigned int pdt$l_mdatr; /* Port maintenance data register */N unsigned int pdt$l_ps; /* Port status register */N unsigned int pdt$l_pqbbr; /* Port queue block base register */N unsigned int pdt$l_cq0; B /* Command queue 0 control register */N unsigned int pdt$l_cq1; /* Command queue 1 control register */N unsigned int pdt$l_psr; /* Port status release register */N unsigned int pdt$l_pec; /* Port enable control register */N unsigned int pdt$l_pic; /* Port initialize control register */N unsigned int pdt$l_dfq; /* DG free queue control register */N unsigned int pdt$l_mfq; /* MSG free queue contBrol register */P unsigned int pdt$l_mtc; /* Maintenance timer control register */N unsigned int pdt$l_pfar; /* Port failing address register */N unsigned int pdt$l_ppr; /* Port parameter register */N unsigned int pdt$l_psnr; /* Port serial number register */N unsigned int pdt$l_fadrl; /* Failing address low register */N unsigned int pdt$l_fadrh; /* Failing address high register */N unBsigned int pdt$l_pesr; /* Port error status register */Q unsigned int pdt$l_pidr; /* Port interrupt destination register */N unsigned int pdt$l_pvr; /* Port vector register */N unsigned int pdt$l_pevr; /* Port error vector register */N unsigned int pdt$l_prvr; /* Port response vector register */N unsigned int pdt$l_xcomm; /* XMI command register */N unsigned int pdt$l_pdcsrB; /* Port diagnostic control register */N unsigned int pdt$l_pscr; /* Port scan control register */N unsigned int pdt$l_psdr; /* Port scan data register */N unsigned int pdt$l_psernum; /* Port serial number */N struct _adp *pdt$l_altadp; /* The other port's ADP */N struct _pdt *pdt$l_altpdt; /* The other port's PDT */N unsigned char pdt$b_port1; /* 1 if port 1 B, 0 if port 2 */ char pdt$b_align3 [3]; } PAPDT; #if !defined(__VAXC)T#define pdt$v_pwf_clnup pdt$r_iport_sts_overlay.pdt$r_iport_sts_bits.pdt$v_pwf_clnupH#define pdt$v_pup pdt$r_iport_sts_overlay.pdt$r_iport_sts_bits.pdt$v_pup?#define pdt$l_iport_sts pdt$r_iport_sts_overlay.pdt$l_iport_stsJ#define pdt$v_lbdg pdt$r_lport_sts_overlay.pdt$r_lport_sts_bits.pdt$v_lbdgP#define pdt$v_new_rsp pdt$r_lport_sts_overlay.pdt$r_lport_sts_bits.pdt$v_new_rspT#define pdt$v_reqid_snt pdt$Br_lport_sts_overlay.pdt$r_lport_sts_bits.pdt$v_reqid_sntT#define pdt$v_instr_snt pdt$r_lport_sts_overlay.pdt$r_lport_sts_bits.pdt$v_instr_sntN#define pdt$v_clsckt pdt$r_lport_sts_overlay.pdt$r_lport_sts_bits.pdt$v_clscktL#define pdt$v_local pdt$r_lport_sts_overlay.pdt$r_lport_sts_bits.pdt$v_localV#define pdt$v_look_aside pdt$r_lport_sts_overlay.pdt$r_lport_sts_bits.pdt$v_look_aside?#define pdt$w_lport_sts pdt$r_lport_sts_overlay.pdt$w_lport_sts/#define pdt$q_dfreeq pdt$r_fill_2_.pdt$q_dfreeqIB#define pdt$l_dfreeq_flink pdt$r_fill_2_.pdt$r_fill_3_.pdt$l_dfreeq_flinkI#define pdt$l_dfreeq_blink pdt$r_fill_2_.pdt$r_fill_3_.pdt$l_dfreeq_blink/#define pdt$q_mfreeq pdt$r_fill_4_.pdt$q_mfreeqI#define pdt$l_mfreeq_flink pdt$r_fill_4_.pdt$r_fill_5_.pdt$l_mfreeq_flinkI#define pdt$l_mfreeq_blink pdt$r_fill_4_.pdt$r_fill_5_.pdt$l_mfreeq_blink3#define pdt$l_keepalive pdt$r_fill6.pdt$l_keepalive1#define pdt$l_vc_check pdt$r_fill6.pdt$l_vc_checkF#define pdt$v_m pdt$r_lport_mult_overlay.pdt$rB_lport_mult_bits.pdt$v_mB#define pdt$l_lport_mult pdt$r_lport_mult_overlay.pdt$l_lport_mult"#endif /* #if !defined(__VAXC) */ #define PDT$M_PI_CQ3 0x1#define PDT$M_PI_CQ2 0x2#define PDT$M_PI_CQ1 0x4#define PDT$M_PI_CQ0 0x8#define PDT$C_PILENGTH 2488N#define PDT$S_PIPDTDEF 2488 /* Old size name - synonym */ typedef struct _pipdt {N/* */N/* Skip the common PDT plus the PA extension B */N/* */( unsigned char pdt$b_pdt_fill [2352];N/* */N/* Define private PI fields */N/* */ __union {( unsigned __int64 pdt$q_pi_cmdq0; __struct {' void *pdt$l_pi_cmdq0B_flink;' void *pdt$l_pi_cmdq0_blink; } pdt$r_fill_9_; } pdt$r_fill_8_; __union {( unsigned __int64 pdt$q_pi_cmdq1; __struct {' void *pdt$l_pi_cmdq1_flink;' void *pdt$l_pi_cmdq1_blink; } pdt$r_fill_11_; } pdt$r_fill_10_; __union {( unsigned __int64 pdt$q_pi_cmdq2; __struct {' void *pdt$l_pi_cmdq2_flink;' void *pdt$l_pi_cmdq2_blink; B } pdt$r_fill_13_; } pdt$r_fill_12_; __union {( unsigned __int64 pdt$q_pi_cmdq3; __struct {' void *pdt$l_pi_cmdq3_flink;' void *pdt$l_pi_cmdq3_blink; } pdt$r_fill_15_; } pdt$r_fill_14_; __union {' unsigned __int64 pdt$q_pi_ripq; __struct {& void *pdt$l_pi_ripq_flink;& void *pdt$l_pi_ripq_blink; } pdt$r_fill_17_; } pdt$r_fill_16_; void *pdBt$l_pi_sva; unsigned int pdt$l_pi_ppd; unsigned int pdt$l_pi_ini;! unsigned int pdt$l_pi_random;! unsigned int pdt$l_pi_dg_max;" unsigned int pdt$l_pi_msg_max;! unsigned int pdt$l_pi_nr [8];! unsigned int pdt$l_pi_ns [8];" unsigned char pdt$b_pi_cstmap;" unsigned char pdt$b_pi_ripmap;" unsigned char pdt$b_pi_pipmap; __union { __struct {& unsigned pdt$v_pi_cq3 : 1;& unsigned pdt$v_pi_cq2 : 1;& unsigned pBdt$v_pi_cq1 : 1;& unsigned pdt$v_pi_cq0 : 1;( unsigned pdt$v_fill_18_ : 4;! } pdt$r_pi_work_bits;$ unsigned char pdt$b_pi_work; } pdt$r_pi_work_overlay; char pdt$b_pi_align [4]; } PIPDT; #if !defined(__VAXC)3#define pdt$q_pi_cmdq0 pdt$r_fill_8_.pdt$q_pi_cmdq0M#define pdt$l_pi_cmdq0_flink pdt$r_fill_8_.pdt$r_fill_9_.pdt$l_pi_cmdq0_flinkM#define pdt$l_pi_cmdq0_blink pdt$r_fill_8_.pdt$r_fill_9_.pdt$l_pi_cmdq0_blink4#define pdt$q_Bpi_cmdq1 pdt$r_fill_10_.pdt$q_pi_cmdq1O#define pdt$l_pi_cmdq1_flink pdt$r_fill_10_.pdt$r_fill_11_.pdt$l_pi_cmdq1_flinkO#define pdt$l_pi_cmdq1_blink pdt$r_fill_10_.pdt$r_fill_11_.pdt$l_pi_cmdq1_blink4#define pdt$q_pi_cmdq2 pdt$r_fill_12_.pdt$q_pi_cmdq2O#define pdt$l_pi_cmdq2_flink pdt$r_fill_12_.pdt$r_fill_13_.pdt$l_pi_cmdq2_flinkO#define pdt$l_pi_cmdq2_blink pdt$r_fill_12_.pdt$r_fill_13_.pdt$l_pi_cmdq2_blink4#define pdt$q_pi_cmdq3 pdt$r_fill_14_.pdt$q_pi_cmdq3O#define pdt$l_pi_cmdq3_flink pBdt$r_fill_14_.pdt$r_fill_15_.pdt$l_pi_cmdq3_flinkO#define pdt$l_pi_cmdq3_blink pdt$r_fill_14_.pdt$r_fill_15_.pdt$l_pi_cmdq3_blink2#define pdt$q_pi_ripq pdt$r_fill_16_.pdt$q_pi_ripqM#define pdt$l_pi_ripq_flink pdt$r_fill_16_.pdt$r_fill_17_.pdt$l_pi_ripq_flinkM#define pdt$l_pi_ripq_blink pdt$r_fill_16_.pdt$r_fill_17_.pdt$l_pi_ripq_blinkJ#define pdt$v_pi_cq3 pdt$r_pi_work_overlay.pdt$r_pi_work_bits.pdt$v_pi_cq3J#define pdt$v_pi_cq2 pdt$r_pi_work_overlay.pdt$r_pi_work_bits.pdt$v_pi_cq2J#define  Bpdt$v_pi_cq1 pdt$r_pi_work_overlay.pdt$r_pi_work_bits.pdt$v_pi_cq1J#define pdt$v_pi_cq0 pdt$r_pi_work_overlay.pdt$r_pi_work_bits.pdt$v_pi_cq09#define pdt$b_pi_work pdt$r_pi_work_overlay.pdt$b_pi_work"#endif /* #if !defined(__VAXC) */ #define PDT$M_CUR_LBS 0x1#define PDT$M_PRV_LBS 0x2#define PDT$M_X_LBS 0x4 typedef struct _lbsts { __union { __struct {N unsigned pdt$v_cur_lbs : 1; /* Current LB status */N unsigned pdt$v_prv_l !Bbs : 1; /* Previous LB status */N unsigned pdt$v_x_lbs : 1; /* Previous LB crossed status */( unsigned pdt$v_fill_19_ : 5; } pdt$r_lbsts_bits;" unsigned char pdt$b_lbsts; } pdt$r_lbsts_overlay; } LBSTS; #if !defined(__VAXC)H#define pdt$v_cur_lbs pdt$r_lbsts_overlay.pdt$r_lbsts_bits.pdt$v_cur_lbsH#define pdt$v_prv_lbs pdt$r_lbsts_overlay.pdt$r_lbsts_bits.pdt$v_prv_lbsD#define pdt$v_x_lbs pdt$r_lbsts_overlay.pdt$r_ "Blbsts_bits.pdt$v_x_lbs3#define pdt$b_lbsts pdt$r_lbsts_overlay.pdt$b_lbsts"#endif /* #if !defined(__VAXC) */ N#define PDT$L_CRCTXWQFL 2352 /* CRCTX wait queue */N#define PDT$L_CRCTXWQBL 2356 /* */N#define PDT$L_CRCTX_WAITS 2360 /* count CRCTX waits */N#define PDT$C_CUNIN 0 /* Channel in UNINITIALIZED state */]#define PDT$C_CIC 1 /* Channel Initialization Co #Bmpleted/DISABLED state */T#define PDT$C_CEC 2 /* Channel Enable Completed/ENABLED state */#define PDT$M_ONLINE 0x40000000##define PDT$M_CHNL_CLNUP 0x80000000N#define PDT$C_TQE_IOTO_TIMEOUT 100000000 /* 10 sec t/o (100ns) */N#define PDT$C_TQE_INIT_TIMEOUT 10000 /* 1 msec t/o (100ns) */#define PDT$C_PNLENGTH 3032N#define PDT$S_PNPDTDEF 3032 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structur $Be prototypes */ struct _cram; struct _kpb; #endif /* #ifdef __cplusplus */ typedef struct _pnpdt {N/* */N/* Skip the common and PA PDT to define NPORT-specific PDT fields */N/* */( unsigned char pdt$b_pdt_fill [2352]; N/* multiplex one wait queue for either type0 Arrays or CRCTXs */N/* this is justified because%B map routines useing two resources are */N/* mutually exclusive. */] void *pdt$l_typ1waitqfl; /* Listhead for Fork Block waiting for TYP1 Arrays */N void *pdt$l_typ1waitqbl; /* */N void *pdt$l_freetyp1; /* Free Type 1 array list */N unsigned int pdt$l_dlck; /* Fork Lock */P unsigned __int64 pdt$q_ablk; &B /* Address of adpater block - virtual */Q unsigned __int64 pdt$q_ablkp; /* Address of adpater block - physical */U unsigned __int64 pdt$q_crrr; /* Carriers used with channel queue header */Z unsigned __int64 pdt$q_qbuf; /* Queue buffers used with channel queue header */G void *pdt$l_crrr_cacheqfl; /* Carriers Cache Queue */N void *pdt$l_crrr_cacheqbl; /* Carriers Cache Queue */G void *pdt$l_qbuf_cacheqfl; /* Q'BBuffers Cache Queue */N void *pdt$l_qbuf_cacheqbl; /* QBuffers Cache Queue */N unsigned __int64 pdt$q_spare1; /* Spare quadword */N unsigned __int64 pdt$q_spare2; /* Spare quadword */N unsigned __int64 pdt$q_spare3; /* Spare quadword */N __union { /* Overlay FT & SPARE4 cells */N unsigned __int64 pdt$q_spare4; /* Spare quadword (B*/N __struct { /* Overlay Faulty-Towers */N unsigned int pdt$l_rsrvd_for_ft_1; /* Reserved Test 1 */N unsigned int pdt$l_rsrvd_for_ft_2; /* Reserved Test 2 */% } pdt$r_spare4_ft_struct;" } pdt$r_spare4_ft_overlay;N unsigned int pdt$l_cntdis; /* RDCNT dispatch */N void *pdt$l_hshut_qbuf; /* Address of Host Shutdown QBUF */N void *pdt$l_setckt_qbu)Bf; /* Address of SETCKT QBUF */N void *pdt$l_spare_qbuf; /* Address of spare QBUF */N unsigned int pdt$l_initialize; /* Initialize adapter */N unsigned int pdt$l_enable; /* Enable adapter */N unsigned int pdt$l_init_ablk; /* Init adapter block */N unsigned int pdt$l_ins_comqm; /* Notify port of non-empty CMDQ1 */N struct _cram *pdt$l_abbr; /* adapter b*Block CRAM Address */N struct _cram *pdt$l_cq2; /* Command que 2 CRAM Address */N struct _cram *pdt$l_nre; /* emulation CRAM Address */N struct _cram *pdt$l_qir; /* QIR CRAM Address */N struct _cram *pdt$l_xber; /* XBER CRAM Address */N struct _cram *pdt$l_xdev; /* XDEV CRAM Address */Q void *pdt$l_r_afar0; /* Read CRAM mailbox address - AFAR0 +B */Q void *pdt$l_r_afar1; /* Read CRAM mailbox address - AFAR1 */Q void *pdt$l_r_amcsr; /* Read CRAM mailbox address - AMCSR */O void *pdt$l_r_asr; /* Read CRAM mailbox address - ASR */P void *pdt$l_r_casr; /* Read CRAM mailbox address - CASR */P void *pdt$l_r_pesr; /* Read CRAM mailbox address - PESR */P void *pdt$l_r_pfar; /* Read CRAM mailbox address - PFAR */Q ,Bvoid *pdt$l_r_spare; /* Read CRAM mailbox address - SPARE */O void *pdt$l_r_xbe; /* Read CRAM mailbox address - XBE */P void *pdt$l_r_xdev; /* Read CRAM mailbox address - XDEV */Q void *pdt$l_r_xfadr; /* Read CRAM mailbox address - XFADR */Q void *pdt$l_r_xfaer; /* Read CRAM mailbox address - XFAER */P void *pdt$l_r_xpd1; /* Read CRAM mailbox address - XPD1 */P void *pd-Bt$l_w_abbr; /* Write CRAM mailbox address - ABBR */U void *pdt$l_w_acivr; /* Write CRAM mailbox address - ACIVR */T void *pdt$l_w_aidr; /* Write CRAM mailbox address - AIDR */U void *pdt$l_w_amcsr; /* Write CRAM mailbox address - AMCSR */U void *pdt$l_w_amivr; /* Write CRAM mailbox address - AMIVR */U void *pdt$l_w_amtcr; /* Write CRAM mailbox address - AMTCR */.BU void *pdt$l_w_casrcr; /* Write CRAM mailbox address - CASRCR */T void *pdt$l_w_compirr; /* Write CRAM mailbox address - COMPIRR */S void *pdt$l_w_cq0; /* Write CRAM mailbox address - CQ0 */S void *pdt$l_w_cq1; /* Write CRAM mailbox address - CQ1 */N void *pdt$l_w_cq2; /* Write CRAM mailbox address - CQ2 */S void *pdt$l_w_dfq; /* Write CRAM mailbox address - DFQ /B */T void *pdt$l_w_init; /* Write CRAM mailbox address - INIT */T void *pdt$l_w_cicr; /* Write CRAM mailbox address - CICR */T void *pdt$l_w_cecr; /* Write CRAM mailbox address - CECR */S void *pdt$l_w_mfq; /* Write CRAM mailbox address - MFQ */S void *pdt$l_w_nre; /* Write CRAM mailbox address - NRE */S void *pdt$l_w_qir; /* Write CRAM mailbox addres0Bs - QIR */S void *pdt$l_w_xbe; /* Write CRAM mailbox address - XBE */T void *pdt$l_w_xpd1; /* Write CRAM mailbox address - XPD1 */T void *pdt$l_w_xpd2; /* Write CRAM mailbox address - XPD2 */Z void *pdt$l_r_qcmdf; /* Fwd link of currently outstanding Cmd qbuffs */Z void *pdt$l_r_qcmdb; /* Bkd link of currently outstanding Cmd qbuffs */Y void *pdt$l_r_rspf; /* Fwd1B link of response qbuffs to be processed */Y void *pdt$l_r_rspb; /* Bkd link of response qbuffs to be processed */f void *pdt$l_r_dafqf; /* Fwd link of free qbuffs in the Driver-Adapter Free Queue */f void *pdt$l_r_dafqb; /* Bkd link of free qbuffs in the Driver-Adapter Free Queue */] void *pdt$l_r_wcmdfl; /* DSSI command completion wait queue forward link */^ void *pdt$l_r_wcmdbl; /* DSSI command completi2Bon wait queue backward link */] void *pdt$l_r_pcmdfl; /* Port command completion wait queue forward link */^ void *pdt$l_r_pcmdbl; /* Port command completion wait queue backward link */u void *pdt$l_r_ab; /* Pointer to the shared Adapter Block *already defined, may use this one* */N struct _pdt *pdt$l_r_pdt; /* PDT address of the other channel */t void *pdt$ps_gcqir; /*Mailbox address of Channel's "greased" c3Bommand queue insertion register */T unsigned int pdt$l_chanstate; /* Channel specific state transition code */Y void *pdt$l_r_dccq2t; /* Driver-Adapter Command queue 2 tail pointer */Y void *pdt$l_r_dccq1t; /* Driver-Adapter Command queue 1 tail pointer */Y void *pdt$l_r_dccq0t; /* Driver-Adapter Command queue 0 tail pointer */T void *pdt$l_r_cntrs; /* Pointer to the port counter block area */N/* in the Adapter Bloc4Bk free memory space */O unsigned int pdt$il_initmr; /* Port initialization timeout value */N unsigned int pdt$il_enabtmr; /* Port re-enable timeout value */W struct _kpb *pdt$l_r_kpb; /* Adapter-wide Kernel Process Block address */N char pdt$b_align_busreset_fkblk [4]; /* QUADWORD ALIGN */[ char pdt$ib_busreset_fkblk [32]; /* Fork block used for getting KPB for BUS RESET */Y struct _kpb *pdt$l5B_r_busreset_kpb; /* KPB used for SCSI BUS RESET operation which */N/* is triggered by the port driver */a struct _kpb *pdt$l_r_chnl_kpb; /* KPB used for cleaning up resources and re-enabling */N/* a channel */ ] char pdt$ib_chnl_fkblk [32]; /* Fork block used for getting KPB for re-enabling */ X char pdt$ib_chnl_int_fkblk [32]; /* Fork block used for channel s 6Bpecific error */N unsigned int pdt$il_chnl_int_fklck; /* CHNL_INT fork block lock field */R unsigned int pdt$il_channel; /* Channel number (0 or 1) of this port */$ struct _cram *pdt$l_r_port_cram; __union {N unsigned int pdt$l_sts; /* port device status */ __struct {' unsigned pdt$v_filler : 30;U unsigned pdt$v_online : 1; /* ONLINE bit is used when we are cleaning */N/* up the adapter buffers after powerf 7Bail/crash */] unsigned pdt$v_chnl_clnup : 1; /* This bit is used when we are cleaning up the */N/* channel resources after the BUS RESET */ } pdt$r_fill_21_; } pdt$r_fill_20_; char pdt$b_dipl [1]; char pdt$b_fill_1 [3];N char pdt$b_align4 [4]; /* QUADWORD ALIGN */N char pdt$b_tqe_ioto [64]; /* TQE for I/O timeout */N char pdt$b 8B_tqe_init [64]; /* TQE for init forks */ N unsigned int pdt$l_known_nodes; /* Map of known nodes */N unsigned int pdt$l_pb_map; /* Map of nodes to track failed VCs */ N unsigned __int64 pdt$q_dma_base; /* DDMA window base BA */N unsigned __int64 pdt$q_ddma_base_pa; /* PA DDMA window base maps to */N unsigned __int64 pdt$q_monster_win_base; /* MONSTER_WINDOW base BA */N unsigned __int64 pdt$q_dma_s 9Bize; /* DDMA window size in bytes */N unsigned __int64 pdt$q_mem_size; /* system memory size in bytes */ } PNPDT; #if !defined(__VAXC)9#define pdt$q_spare4 pdt$r_spare4_ft_overlay.pdt$q_spare4`#define pdt$l_rsrvd_for_ft_1 pdt$r_spare4_ft_overlay.pdt$r_spare4_ft_struct.pdt$l_rsrvd_for_ft_1`#define pdt$l_rsrvd_for_ft_2 pdt$r_spare4_ft_overlay.pdt$r_spare4_ft_struct.pdt$l_rsrvd_for_ft_2*#define pdt$l_sts pdt$r_fill_20_.pdt$l_sts?#define pdt$v_online pdt$r_fill_20_.pd:Bt$r_fill_21_.pdt$v_onlineG#define pdt$v_chnl_clnup pdt$r_fill_20_.pdt$r_fill_21_.pdt$v_chnl_clnup"#endif /* #if !defined(__VAXC) */ N#define PDT$L_ARG 3080 /* scratch LW/QW */ #define PDT$L_CFG_VENDOR_ID 3120#define PDT$L_CFG_COMMAND 3124"#define PDT$L_CFG_REVISION_ID 3128&#define PDT$L_CFG_CACHE_LINE_SIZE 3132#define PDT$R_CIPCA_CTRS 3384#define PDT$S_CIPCA_CTRS 80#define PDT$C_CIPCA_CTRS_MAX 20#define PDT$C_PCLENGTH 3464N#define PDT$S_PC ;BPDTDEF 3464 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _crab; #endif /* #ifdef __cplusplus */ typedef struct _pcpdt {N/* */N/* Skip the common, PA and PN PDT to define PCI-specific PDT fields */N/* */( unsigned char pdt$b_pdt_fill [3032];N unsignedB */N unsigned int pdt$l_crctx_high; /* highwater mark for RESERVE */N/* rpn: assume 8KB pages */K/* NPPG_OFFSET_MASK longword unsigned ; /* NPort Page offset in Phys pg */ N unsigned __int64 pdt$q_arg; /* for CALL ret'd values */N unsigned __int64 pdt$q_missed_ints; /* count of 'missed' interrupts */N unsigned int pdt$l_iohandle_br0; /* IO Handle for Base Reg 0 */N unsi?Bgned int pdt$l_iohandle_br1; /* IO Handle for Base Reg 1 */N unsigned int pdt$l_iohandle_br2; /* IO Handle for Base Reg 2 */N unsigned int pdt$l_iohandle_br3; /* IO Handle for Base Reg 3 */N unsigned int pdt$l_iohandle_br4; /* IO Handle for Base Reg 4 */N unsigned int pdt$l_iohandle_br5; /* IO Handle for Base Reg 5 */N/* PCI Register Copies for staging register I/O */N/* Configuration Space Registers ( @BRef: NPort Spec) */+ unsigned short int pdt$w_cfg_vendor_id;+ unsigned short int pdt$w_cfg_device_id;) unsigned short int pdt$w_cfg_command;( unsigned short int pdt$w_cfg_status;( unsigned char pdt$b_cfg_revision_id;+ unsigned char pdt$b_cfg_programming_if;& unsigned char pdt$b_cfg_sub_class;' unsigned char pdt$b_cfg_base_class;, unsigned char pdt$b_cfg_cache_line_size;* unsigned char pdt$b_cfg_latency_timer;( unsigned char pdt$ ABb_cfg_header_type;! unsigned char pdt$b_cfg_bist; * unsigned int pdt$l_cfg_base_address_0;+ unsigned int pdt$l_cfg_base_address_0h;* unsigned int pdt$l_cfg_base_address_1;+ unsigned int pdt$l_cfg_base_address_1h;* unsigned int pdt$l_cfg_base_address_2;+ unsigned int pdt$l_cfg_base_address_2h;* unsigned int pdt$l_cfg_base_address_3;+ unsigned int pdt$l_cfg_base_address_3h;* unsigned int pdt$l_cfg_base_address_4;+ unsigned int pdt$l_cfg_base_address_4h BB;* unsigned int pdt$l_cfg_base_address_5;+ unsigned int pdt$l_cfg_base_address_5h; N unsigned int pdt$l_mio_adprst; /* Adapter Reset */N unsigned int pdt$l_mio_adprst2; /* */N unsigned int pdt$l_mio_clrinta; /* Clear Interrupt A */N unsigned int pdt$l_mio_clrinta2; /* */N unsigned int pdt$l_mio_clrintb; /* Clear Interrupt B */N unsiCBgned int pdt$l_mio_clrintb2; /* */N unsigned int pdt$l_mio_aitcr; /* Interrupt Holdoff */N unsigned int pdt$l_mio_aitcr2; /* */N unsigned int pdt$l_mio_nodests; /* Node Status */N unsigned int pdt$l_mio_nodests2; /* */N unsigned int pdt$l_mio_intena; /* Interrupt Enable */N unsigned int pdt$l_mio_intena2 DB; /* */N __union { /* Overlay 32 and 64 bit fields */R unsigned __int64 pdt$q_mio_abbr; /* 64 bit Adapter Block Base Register */ __struct {N unsigned int pdt$l_mio_abbr; /* Adapter Block Base Register */) unsigned int pdt$l_mio_abbr2; } pdt$r_abbr_struct;! } pdt$r_mio_abbr_overlay; __union {N unsigned __int64 pdt$q_mio_ccq2ir; /* 64 bit Chan Cmd Q EB2 Insertion */ __struct {N unsigned int pdt$l_mio_ccq2ir; /* Chan Cmd Queue 2 Insertion */N unsigned int pdt$l_mio_ccq2ir2; /* */" } pdt$r_ccq2ir_struct;# } pdt$r_mio_ccq2ir_overlay; __union {N unsigned __int64 pdt$q_mio_ccq1ir; /* 64 bit Chan Cmd Q 1 Insertion */ __struct {N unsigned int pdt$l_mio_ccq1ir; /* Chan Cmd Queue 1 Insertion */N unsigned int pdt$l_mio_c FBcq1ir2; /* */" } pdt$r_ccq1ir_struct;# } pdt$r_mio_ccq1ir_overlay; __union {N unsigned __int64 pdt$q_mio_ccq0ir; /* 64 bit Chan Cmd Q 0 Insertion */ __struct {N unsigned int pdt$l_mio_ccq0ir; /* Chan Cmd Queue 0 Insertion */N unsigned int pdt$l_mio_ccq0ir2; /* */" } pdt$r_ccq0ir_struct;# } pdt$r_mio_ccq0ir_overlay; __union {N unsigned __i GBnt64 pdt$q_mio_adfqir; /* 64 bit D.gram Fr. Q Insertion */ __struct {O unsigned int pdt$l_mio_adfqir; /* Adap D.gram Fr.Queue Insertion */N unsigned int pdt$l_mio_adfqir2; /* */" } pdt$r_adfqir_struct;# } pdt$r_mio_adfqir_overlay; __union {O unsigned __int64 pdt$q_mio_amfqir; /* 64 bit Message Fr. Q Insertion */ __struct {P unsigned int pdt$l_mio_amfqir; /* Adap Message Fr.Queue HBInsertion */N unsigned int pdt$l_mio_amfqir2; /* */" } pdt$r_amfqir_struct;# } pdt$r_mio_amfqir_overlay;N unsigned int pdt$l_mio_casr; /* Chan/Adap Status (low LW) */N unsigned int pdt$l_mio_casr2; /* */ __union {P unsigned __int64 pdt$q_mio_cafar; /* 64 bit Chan/Adap Failing Address */ __struct {N unsigned int pdt$l_mio_cafar; /* Chan/Adap Fai IBling Address */N unsigned int pdt$l_mio_cafar2; /* */! } pdt$r_cafar_struct;" } pdt$r_mio_cafar_overlay;Q unsigned int pdt$l_mio_casrcr; /* Channel/Adapter Status Release Ctrl */N unsigned int pdt$l_mio_casrcr2; /* */N unsigned int pdt$l_mio_cicr; /* Channel Initialize Control */N unsigned int pdt$l_mio_cicr2; /* */N unsiJBgned int pdt$l_mio_cecr; /* Channel Enable Control */N unsigned int pdt$l_mio_cecr2; /* */S unsigned int pdt$l_mio_amtcr; /* Adapter Maintenance/Sanity Timer Ctrl */N unsigned int pdt$l_mio_amtcr2; /* */S unsigned int pdt$l_mio_amtecr; /* Adapter Maintenance/Sanity Timer Expr */N unsigned int pdt$l_mio_amtecr2; /* */R unsigned int pdt$lKB_mio_amcsr; /* Adapter Maintenance Control & Status */N unsigned int pdt$l_mio_amcsr2; /* */O unsigned int pdt$l_mio_accx; /* Abnormal Condition Code eXtension */N unsigned int pdt$l_mio_accx2; /* */N unsigned int pdt$l_mio_mrev; /* Microcode Revision */N unsigned int pdt$l_mio_mrev2; /* */N unsigned int pdt$l_mio_musr; /*LB Microcode Update Status */N unsigned int pdt$l_mio_musr2; /* */N unsigned int pdt$l_mio_mucr; /* Microcode Update Control & Addr */N unsigned int pdt$l_mio_mucr2; /* */N unsigned int pdt$l_mio_altintena; /* Alternate Interrupt Enable */N unsigned int pdt$l_mio_altintena2; /* */N/* CIPCA port-dependent counters MB */N unsigned int pdt$l_p0_rxcrc; /* Receive packet CRC error */N unsigned int pdt$l_p1_rxcrc; /* Receive packet CRC error */N unsigned int pdt$l_p0_rxdstmismatch; /* DEST matched but DESTC did not */N unsigned int pdt$l_p1_rxdstmismatch; /* DEST matched but DESTC did not */N unsigned int pdt$l_p0_rxbuffull; /* Fifo went full during receive */N unsigned int pdt$l_p1_rxbuffull; /* Fifo went full during receive */R unsigned iNBnt pdt$l_p0_rxdattrunc; /* RX pkt length greater than DMA count */R unsigned int pdt$l_p1_rxdattrunc; /* RX pkt length greater than DMA count */R unsigned int pdt$l_p0_idreqnorsp; /* NORSP cnt from IDREQs to closed VC's */R unsigned int pdt$l_p1_idreqnorsp; /* NORSP cnt from IDREQs to closed VC's */N unsigned int pdt$l_p0_total_rx_pkts; /* Total Received Packets Path A */N unsigned int pdt$l_p1_total_rx_pkts; /* Total Received Packets Path B */N unsigned int pdt$l_pOB0_impl_ctr_rsv1; /* reserved */N unsigned int pdt$l_p1_impl_ctr_rsv1; /* reserved */N unsigned int pdt$l_p0_impl_ctr_rsv2; /* reserved */N unsigned int pdt$l_p1_impl_ctr_rsv2; /* reserved */N unsigned int pdt$l_p0_impl_ctr_rsv3; /* reserved */N unsigned int pdt$l_p1_impl_ctr_rsv3; /* reserved */N unsigned int pdt$l_p0_impl_ctr_rsv4; /* reserv PBed */N unsigned int pdt$l_p1_impl_ctr_rsv4; /* reserved */ } PCPDT; #if !defined(__VAXC)<#define pdt$q_mio_abbr pdt$r_mio_abbr_overlay.pdt$q_mio_abbrN#define pdt$l_mio_abbr pdt$r_mio_abbr_overlay.pdt$r_abbr_struct.pdt$l_mio_abbrP#define pdt$l_mio_abbr2 pdt$r_mio_abbr_overlay.pdt$r_abbr_struct.pdt$l_mio_abbr2B#define pdt$q_mio_ccq2ir pdt$r_mio_ccq2ir_overlay.pdt$q_mio_ccq2irV#define pdt$l_mio_ccq2ir pdt$r_mio_ccq2ir_overlay.pdt$r_ccq2ir_sQBtruct.pdt$l_mio_ccq2irX#define pdt$l_mio_ccq2ir2 pdt$r_mio_ccq2ir_overlay.pdt$r_ccq2ir_struct.pdt$l_mio_ccq2ir2B#define pdt$q_mio_ccq1ir pdt$r_mio_ccq1ir_overlay.pdt$q_mio_ccq1irV#define pdt$l_mio_ccq1ir pdt$r_mio_ccq1ir_overlay.pdt$r_ccq1ir_struct.pdt$l_mio_ccq1irX#define pdt$l_mio_ccq1ir2 pdt$r_mio_ccq1ir_overlay.pdt$r_ccq1ir_struct.pdt$l_mio_ccq1ir2B#define pdt$q_mio_ccq0ir pdt$r_mio_ccq0ir_overlay.pdt$q_mio_ccq0irV#define pdt$l_mio_ccq0ir pdt$r_mio_ccq0ir_overlay.pdt$r_ccq0ir_struct.pdt$l_miRBo_ccq0irX#define pdt$l_mio_ccq0ir2 pdt$r_mio_ccq0ir_overlay.pdt$r_ccq0ir_struct.pdt$l_mio_ccq0ir2B#define pdt$q_mio_adfqir pdt$r_mio_adfqir_overlay.pdt$q_mio_adfqirV#define pdt$l_mio_adfqir pdt$r_mio_adfqir_overlay.pdt$r_adfqir_struct.pdt$l_mio_adfqirX#define pdt$l_mio_adfqir2 pdt$r_mio_adfqir_overlay.pdt$r_adfqir_struct.pdt$l_mio_adfqir2B#define pdt$q_mio_amfqir pdt$r_mio_amfqir_overlay.pdt$q_mio_amfqirV#define pdt$l_mio_amfqir pdt$r_mio_amfqir_overlay.pdt$r_amfqir_struct.pdt$l_mio_amfqirX#def SBine pdt$l_mio_amfqir2 pdt$r_mio_amfqir_overlay.pdt$r_amfqir_struct.pdt$l_mio_amfqir2?#define pdt$q_mio_cafar pdt$r_mio_cafar_overlay.pdt$q_mio_cafarR#define pdt$l_mio_cafar pdt$r_mio_cafar_overlay.pdt$r_cafar_struct.pdt$l_mio_cafarT#define pdt$l_mio_cafar2 pdt$r_mio_cafar_overlay.pdt$r_cafar_struct.pdt$l_mio_cafar2"#endif /* #if !defined(__VAXC) */ #define PDT$M_WORKQ_BUSY 0x1 typedef struct _pbpdt {( unsigned char pdt$b_pdt_fill [2488]; __union {( unsigned __int64 pTBdt$q_pb_comql; __struct {' void *pdt$l_pb_comql_flink;' void *pdt$l_pb_comql_blink; } pdt$r_fill_pb_11; } pdt$r_fill_pb_10; __union {( unsigned __int64 pdt$q_pb_comqh; __struct {' void *pdt$l_pb_comqh_flink;' void *pdt$l_pb_comqh_blink; } pdt$r_fill_pb_9; } pdt$r_fill_pb_8; unsigned int pdt$v_pb_comqh; unsigned int pdt$v_pb_comql;! unsigned int pdt$v_pb_onUBline; unsigned int pdt$v_pb_stall;( unsigned int pdt$l_pb_stall_counter;/ unsigned int pdt$l_pb_cumulative_stall_ctr;% unsigned int pdt$l_pb_was_online;- unsigned int pdt$l_pb_blk_data_xfer_size;' unsigned int pdt$l_pb_max_msg_size;+ unsigned __int64 pdt$q_adapter_version; int pdt$l_outbufs; unsigned int pdt$l_crash; unsigned int pdt$l_attempts; unsigned int pdt$l_sendcopy;" unsigned int pdt$l_sendnocopy; unsigned int pdt$l_fud; un VBsigned int pdt$l_fud1; unsigned int pdt$l_fud2; unsigned int pdt$l_fud3;P unsigned int pdt$l_ppd_bdxfer_maxlen; /* ppd block data transfer max. len */U unsigned __int64 pdt$q_pfn_bdxfer_maxlen; /* pfn block data transfer max. len. */Q unsigned __int64 pdt$q_bdxfer_maxlen; /* pfn block data transfer max. len. */N unsigned int pdt$l_poller_tqe; /* poller tqe */N/* If you add a bit, please update the bit symbols just bellow */ __un WBion { __struct {O unsigned pdt$v_workq_busy : 1; /* work queue fork block busy bit */( unsigned pdt$v_fill_22_ : 7; } pdt$r_fkb_bits;N unsigned int pdt$l_pb_flags; /* flag longword */ } pdt$r_fkb_bitfield;N unsigned char pdt$b_wq_fkb [48]; /* work queue fork block */N unsigned int pdt$l_workq [2]; /* local end work queue pointer */N unsigned int pdt$l_maxpfnpkt; /* max n XBumber of pfn packets */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *pdt$pq_pktsva; /* pfn pass buffer */#else unsigned __int64 pdt$pq_pktsva;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size defaul YBt to 32-bit pointers */#endifN void *pdt$pl_pktsva; /* pfn pass buffer */ } pdt$r_pkt_va;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N ZB void *pdt$pq_pktpte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else$ unsigned __int64 pdt$pq_pktpte_sva;#endif } PBPDT; #if !defined(__VAXC)6#define pdt$q_pb_comql pdt$r_fill_pb_10.pdt$q_pb_comql:#define pdt$r_fill_pb_11 pdt$r_fill_pb_10.pdt$r_fill_pb_11B#define pdt$l_pb_comql_flink pdt$r_fill_pb_11.pdt$l_pb_comql_flinkB#define pdt$l_pb_comql_blink pdt$r_fill_pb_11.pdt$l_pb_comql_blink5#define pdt$q_pb_comqh pdt$r_fill_pb_8.pdt$q_pb_comqh7#define pdt$r_fill_pb_9 [Bpdt$r_fill_pb_8.pdt$r_fill_pb_9A#define pdt$l_pb_comqh_flink pdt$r_fill_pb_9.pdt$l_pb_comqh_flinkA#define pdt$l_pb_comqh_blink pdt$r_fill_pb_9.pdt$l_pb_comqh_blinkK#define pdt$v_workq_busy pdt$r_fkb_bitfield.pdt$r_fkb_bits.pdt$v_workq_busy8#define pdt$l_pb_flags pdt$r_fkb_bitfield.pdt$l_pb_flags0#define pdt$pq_pktsva pdt$r_pkt_va.pdt$pq_pktsva0#define pdt$pl_pktsva pdt$r_pkt_va.pdt$pl_pktsva"#endif /* #if !defined(__VAXC) */   N/* \B */N/* PORT Structure */N/* -------------- */N/* */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifd]Bef __cplusplus }#endif#pragma __standard #endif /* __PDTDEF_LOADED */ ww0*[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the^B **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior writ_Bten permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */J/* Sourc `Be: 20-APR-1993 14:37:51 $1$DGA8345:[LIB_H.SRC]PDTLISTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PDTLISTDEF ***/#ifndef __PDTLISTDEF_LOADED#define __PDTLISTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas aBsupported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endifbB#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SCS PDT LIST (TYC 15-Feb-89) */N/* */N/* THIS DATA STRUCTURE CONTAINS A VECTOR LISTING UP TO 32 PDT ADDRESSES OF */N/* DYNAMIC LOAD SHARING PORTS. THE INDEX IS MAI cBNTAINED IN THE SCS */N/* LOAD SHARING PORT BIT MAP. */N/*- */ #define PDTLIST$C_MAX_INDEX 32#define PDTLIST$K_LENGTH 140#define PDTLIST$C_LENGTH 140#define PDTLIST$S_PDTLISTDEF 16 Dtypedef struct _pdtlist { /* WARNING: aggregate has origin of -12 */> /* WARNING: aggregate element "pdtlist$l_flink" ignored */> /* WARNING: aggregate element "pdtlist$l_b dBlink" ignored */= /* WARNING: aggregate element "pdtlist$w_size" ignored */= /* WARNING: aggregate element "pdtlist$b_type" ignored */? /* WARNING: aggregate element "pdtlist$b_subtyp" ignored */N void *pdtlist$l_pdtaddr; /*FIRST PDT ADDRESS */ } PDTLIST; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-deeBfined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PDTLISTDEF_LOADED */ wwPx[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, dfBuplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to gBanyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:2 hB3:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PDUDEF ***/#ifndef __PDUDEF_LOADED#define __PDUDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* DefiiBned whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __jBstruct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* DNA CSMA/CD Frame formats and constants */N/* */N#define PDU$S_CRC_ETH 4 /* Size of pdu$l_crc_eth field */N#define PDU$S_LEN_kBETH 2 /* Size of pdu$w_len_eth field */N#define PDU$C_ETH_HEADER 14 /* Size of Ethernet Header */ typedef struct _csma_cd_frame { unsigned char pdu$g_des [6]; unsigned char pdu$g_src [6]; __union { __struct {) unsigned short int pdu$w_pty; } pdu$r_field3_eth; __struct {- unsigned short int pdu$w_len_802; } pdu$r_field3_802; } pdu$r_field3; __union lB { __struct {' char pdu$g_data_eth [1500];' unsigned int pdu$l_crc_eth; } pdu$r_field4_eth; __struct {- unsigned short int pdu$w_len_eth;+ char pdu$g_data_eth_pad [1498];+ unsigned int pdu$l_crc_eth_pad;# } pdu$r_field4_eth_pad; __struct {% unsigned char pdu$b_dsap;% unsigned char pdu$b_ssap; __union { __struct { mB __union {# __struct {: unsigned short int pdu$w_ctl2;8 char pdu$g_data_ctl2 [1496];- } pdu$r_ctl_fmt1;# __struct {5 unsigned char pdu$b_ctl1;8 char pdu$g_data_ctl1 [1497];- } pdu$r_ctl_fmt2;, } pdu$r_ctl_fmt_802;/ unsigned inBnt pdu$l_crc_802;$ } pdu$x_ctl_802; __struct {+ unsigned char pdu$b_ui;0 unsigned char pdu$g_pid [5];0 char pdu$g_data_802e [1492];0 unsigned int pdu$l_crc_802e;) } pdu$r_field_ui_802;# } pdu$r_field5_802; } pdu$r_field4_802; } pdu$r_field4; } CSMA_CD_FRAME; #if !defined(__VAXC)6#define pdu$r_field3_eth pdu$r_f oBield3.pdu$r_field3_eth,#define pdu$w_pty pdu$r_field3_eth.pdu$w_pty6#define pdu$r_field3_802 pdu$r_field3.pdu$r_field3_8024#define pdu$w_len_802 pdu$r_field3_802.pdu$w_len_8026#define pdu$r_field4_eth pdu$r_field4.pdu$r_field4_eth6#define pdu$g_data_eth pdu$r_field4_eth.pdu$g_data_eth4#define pdu$l_crc_eth pdu$r_field4_eth.pdu$l_crc_eth>#define pdu$r_field4_eth_pad pdu$r_field4.pdu$r_field4_eth_pad8#define pdu$w_len_eth pdu$r_field4_eth_pad.pdu$w_len_ethB#define pdu$g_data_eth_pad pdu$r_field pB4_eth_pad.pdu$g_data_eth_pad@#define pdu$l_crc_eth_pad pdu$r_field4_eth_pad.pdu$l_crc_eth_pad6#define pdu$r_field4_802 pdu$r_field4.pdu$r_field4_802.#define pdu$b_dsap pdu$r_field4_802.pdu$b_dsap.#define pdu$b_ssap pdu$r_field4_802.pdu$b_ssap:#define pdu$r_field5_802 pdu$r_field4_802.pdu$r_field5_8024#define pdu$x_ctl_802 pdu$r_field5_802.pdu$x_ctl_8029#define pdu$r_ctl_fmt_802 pdu$x_ctl_802.pdu$r_ctl_fmt_8027#define pdu$r_ctl_fmt1 pdu$r_ctl_fmt_802.pdu$r_ctl_fmt1,#define pdu$w_ctl2 pdu$r_c qBtl_fmt1.pdu$w_ctl26#define pdu$g_data_ctl2 pdu$r_ctl_fmt1.pdu$g_data_ctl27#define pdu$r_ctl_fmt2 pdu$r_ctl_fmt_802.pdu$r_ctl_fmt2,#define pdu$b_ctl1 pdu$r_ctl_fmt2.pdu$b_ctl16#define pdu$g_data_ctl1 pdu$r_ctl_fmt2.pdu$g_data_ctl11#define pdu$l_crc_802 pdu$x_ctl_802.pdu$l_crc_802>#define pdu$r_field_ui_802 pdu$r_field5_802.pdu$r_field_ui_802,#define pdu$b_ui pdu$r_field_ui_802.pdu$b_ui.#define pdu$g_pid pdu$r_field_ui_802.pdu$g_pid:#define pdu$g_data_802e pdu$r_field_ui_802.pdu$g_data_802e8 rB#define pdu$l_crc_802e pdu$r_field_ui_802.pdu$l_crc_802e"#endif /* #if !defined(__VAXC) */ N#define PDU$C_SID_DATA 2 /* Start of sysid data */ typedef struct _sid_frame {N unsigned short int pdu$w_sid_charcnt; /* Character count of message */N unsigned char pdu$b_sid_code; /* Function code */N unsigned char pdu$b_sid_zeropad; /* Pad of zero */N unsigned short int pdu$w_sid_receipt; /* Receipt nsBumber */ __struct {1 unsigned short int pdu$w_sid_mopver_func;+ unsigned char pdu$b_sid_mopver_len;+ unsigned char pdu$b_sid_mopver_ver;+ unsigned char pdu$b_sid_mopver_eco;, unsigned char pdu$b_sid_mopver_ueco; } pdu$r_mopver; __struct {/ unsigned short int pdu$w_sid_mfct_func;) unsigned char pdu$b_sid_mfct_len;* unsigned char pdu$b_sid_mfct_val1;* unsigned char pdu$b_sid_mfct_val2;tB } pdu$r_mfct; __struct {. unsigned short int pdu$w_sid_hwa_func;( unsigned char pdu$b_sid_hwa_len;( unsigned char pdu$g_sid_hwa [6]; } pdu$r_hwa; __struct {/ unsigned short int pdu$w_sid_sofd_func;) unsigned char pdu$b_sid_sofd_len;% unsigned char pdu$b_sid_sofd; } pdu$r_sofd; __struct {/ unsigned short int pdu$w_sid_dlty_func;) unsigned char pdu$b_sid_dlty_len;% unsigned char uBpdu$b_sid_dlty; } pdu$r_dlty; __struct {/ unsigned short int pdu$w_sid_sfid_func;) unsigned char pdu$b_sid_sfid_len;% unsigned char pdu$b_sid_sfid; } pdu$r_sfid; __struct {4 unsigned short int pdu$w_sid_lan_stype_func;. unsigned char pdu$b_sid_lan_stype_len;) unsigned int pdu$l_sid_lan_stype; } pdu$r_lan_stype; __struct {3 unsigned short int pdu$w_sid_lan_sver_func;- unsigned char pdvBu$b_sid_lan_sver_len;, unsigned __int64 pdu$q_sid_lan_sver; } pdu$r_lan_sver; __struct {3 unsigned short int pdu$w_sid_lan_name_func;- unsigned char pdu$b_sid_lan_name_len;- unsigned char pdu$g_sid_lan_name [8]; } pdu$r_lan_name; __struct {2 unsigned short int pdu$w_sid_lan_cpu_func;, unsigned char pdu$b_sid_lan_cpu_len;' unsigned int pdu$l_sid_lan_cpu; } pdu$r_lan_cpu; __struct {3 un wBsigned short int pdu$w_sid_lan_dver_func;- unsigned char pdu$b_sid_lan_dver_len;, unsigned __int64 pdu$q_sid_lan_dver; } pdu$r_lan_dver; __struct {3 unsigned short int pdu$w_sid_lan_lver_func;- unsigned char pdu$b_sid_lan_lver_len;, unsigned __int64 pdu$q_sid_lan_lver; } pdu$r_lan_lver; __struct {3 unsigned short int pdu$w_sid_lan_nver_func;- unsigned char pdu$b_sid_lan_nver_len;, unsigned __int64 p xBdu$q_sid_lan_nver; } pdu$r_lan_nver; __struct {3 unsigned short int pdu$w_sid_lan_hver_func;- unsigned char pdu$b_sid_lan_hver_len;( unsigned int pdu$l_sid_lan_hver; } pdu$r_lan_hver; __struct {5 unsigned short int pdu$w_sid_lan_status_func;/ unsigned char pdu$b_sid_lan_status_len;1 unsigned int pdu$l_sid_lan_status_abstim;1 unsigned int pdu$l_sid_lan_status_errcnt;. unsigned int pdu$l_sid_lan_statu yBs_sts;. unsigned int pdu$l_sid_lan_status_rcv;. unsigned int pdu$l_sid_lan_status_num; } pdu$r_lan_status; } SID_FRAME; #if !defined(__VAXC)@#define pdu$w_sid_mopver_func pdu$r_mopver.pdu$w_sid_mopver_func>#define pdu$b_sid_mopver_len pdu$r_mopver.pdu$b_sid_mopver_len>#define pdu$b_sid_mopver_ver pdu$r_mopver.pdu$b_sid_mopver_ver>#define pdu$b_sid_mopver_eco pdu$r_mopver.pdu$b_sid_mopver_eco@#define pdu$b_sid_mopver_ueco pdu$r_mopver.pdu$b_sid_mopver_ueco:#def zBine pdu$w_sid_mfct_func pdu$r_mfct.pdu$w_sid_mfct_func8#define pdu$b_sid_mfct_len pdu$r_mfct.pdu$b_sid_mfct_len:#define pdu$b_sid_mfct_val1 pdu$r_mfct.pdu$b_sid_mfct_val1:#define pdu$b_sid_mfct_val2 pdu$r_mfct.pdu$b_sid_mfct_val27#define pdu$w_sid_hwa_func pdu$r_hwa.pdu$w_sid_hwa_func5#define pdu$b_sid_hwa_len pdu$r_hwa.pdu$b_sid_hwa_len-#define pdu$g_sid_hwa pdu$r_hwa.pdu$g_sid_hwa:#define pdu$w_sid_sofd_func pdu$r_sofd.pdu$w_sid_sofd_func8#define pdu$b_sid_sofd_len pdu$r_sofd.pdu$b_sid_so {Bfd_len0#define pdu$b_sid_sofd pdu$r_sofd.pdu$b_sid_sofd:#define pdu$w_sid_dlty_func pdu$r_dlty.pdu$w_sid_dlty_func8#define pdu$b_sid_dlty_len pdu$r_dlty.pdu$b_sid_dlty_len0#define pdu$b_sid_dlty pdu$r_dlty.pdu$b_sid_dlty:#define pdu$w_sid_sfid_func pdu$r_sfid.pdu$w_sid_sfid_func8#define pdu$b_sid_sfid_len pdu$r_sfid.pdu$b_sid_sfid_len0#define pdu$b_sid_sfid pdu$r_sfid.pdu$b_sid_sfidI#define pdu$w_sid_lan_stype_func pdu$r_lan_stype.pdu$w_sid_lan_stype_funcG#define pdu$b_sid_lan_stype_len pdu$|Br_lan_stype.pdu$b_sid_lan_stype_len?#define pdu$l_sid_lan_stype pdu$r_lan_stype.pdu$l_sid_lan_stypeF#define pdu$w_sid_lan_sver_func pdu$r_lan_sver.pdu$w_sid_lan_sver_funcD#define pdu$b_sid_lan_sver_len pdu$r_lan_sver.pdu$b_sid_lan_sver_len<#define pdu$q_sid_lan_sver pdu$r_lan_sver.pdu$q_sid_lan_sverF#define pdu$w_sid_lan_name_func pdu$r_lan_name.pdu$w_sid_lan_name_funcD#define pdu$b_sid_lan_name_len pdu$r_lan_name.pdu$b_sid_lan_name_len<#define pdu$g_sid_lan_name pdu$r_lan_name.pdu$g_sid_lan_ }BnameC#define pdu$w_sid_lan_cpu_func pdu$r_lan_cpu.pdu$w_sid_lan_cpu_funcA#define pdu$b_sid_lan_cpu_len pdu$r_lan_cpu.pdu$b_sid_lan_cpu_len9#define pdu$l_sid_lan_cpu pdu$r_lan_cpu.pdu$l_sid_lan_cpuF#define pdu$w_sid_lan_dver_func pdu$r_lan_dver.pdu$w_sid_lan_dver_funcD#define pdu$b_sid_lan_dver_len pdu$r_lan_dver.pdu$b_sid_lan_dver_len<#define pdu$q_sid_lan_dver pdu$r_lan_dver.pdu$q_sid_lan_dverF#define pdu$w_sid_lan_lver_func pdu$r_lan_lver.pdu$w_sid_lan_lver_funcD#define pdu$b_sid_lan_lver~B_len pdu$r_lan_lver.pdu$b_sid_lan_lver_len<#define pdu$q_sid_lan_lver pdu$r_lan_lver.pdu$q_sid_lan_lverF#define pdu$w_sid_lan_nver_func pdu$r_lan_nver.pdu$w_sid_lan_nver_funcD#define pdu$b_sid_lan_nver_len pdu$r_lan_nver.pdu$b_sid_lan_nver_len<#define pdu$q_sid_lan_nver pdu$r_lan_nver.pdu$q_sid_lan_nverF#define pdu$w_sid_lan_hver_func pdu$r_lan_hver.pdu$w_sid_lan_hver_funcD#define pdu$b_sid_lan_hver_len pdu$r_lan_hver.pdu$b_sid_lan_hver_len<#define pdu$l_sid_lan_hver pdu$r_lan_hver.pdu$l_sid_laBn_hverL#define pdu$w_sid_lan_status_func pdu$r_lan_status.pdu$w_sid_lan_status_funcJ#define pdu$b_sid_lan_status_len pdu$r_lan_status.pdu$b_sid_lan_status_lenP#define pdu$l_sid_lan_status_abstim pdu$r_lan_status.pdu$l_sid_lan_status_abstimP#define pdu$l_sid_lan_status_errcnt pdu$r_lan_status.pdu$l_sid_lan_status_errcntJ#define pdu$l_sid_lan_status_sts pdu$r_lan_status.pdu$l_sid_lan_status_stsJ#define pdu$l_sid_lan_status_rcv pdu$r_lan_status.pdu$l_sid_lan_status_rcvJ#define pdu$l_sid_lan_status B_num pdu$r_lan_status.pdu$l_sid_lan_status_num"#endif /* #if !defined(__VAXC) */ N#define PDU$C_RID_COUNT 4 /*size of request ID message */ typedef struct _rid_frame {N unsigned short int pdu$w_rid_charcnt; /* Character count of message */N unsigned char pdu$b_rid_code; /* Function code */N unsigned char pdu$b_rid_zeropad; /* Pad of zero */N unsigned short int pdu$w_rid_receipt; /* Receipt number B */ } RID_FRAME;N#define PDU$C_RID_802_COUNT 4 /*size of request ID message */ typedef struct _rid_802_frame {N unsigned char pdu$b_rid_802_code; /* Function code */N unsigned char pdu$b_rid_802_zeropad; /* Pad of zero */N unsigned short int pdu$w_rid_802_receipt; /* Receipt number */ } RID_802_FRAME;N#define PDU$G_CTR_DATA 5 /* start of counters */#define PDU$BM_SFL_EXC 0x1#define PDU$M_SFL_CCF 0x2#define PDU$M_SFL_SHC 0x4#define PDU$M_SFL_OPC 0x8#define PDU$M_SFL_FTL 0x10#define PDU$M_SFL_RFD 0x20#define PDU$M_RFL_BCE 0x1#define PDU$M_RFL_FME 0x2#define PDU$M_RFL_FTL 0x4 typedef struct _ctr_frame {N unsigned short int pdu$w_ctr_charcnt; /* Character count of message */N unsigned char pdu$b_ctr_code; /* Function code */N unsigned short int pdu$w_ctr_receipt; /* Receipt number B */N unsigned short int pdu$w_zerctr; /* Seconds since last zeroed */N unsigned int pdu$l_brcctr; /* Bytes received */N unsigned int pdu$l_bsnctr; /* Bytes sent */N unsigned int pdu$l_dbrctr; /* Frames received */N unsigned int pdu$l_dbsctr; /* Frames sent */N unsigned int pdu$l_mbyctr; /* Multicast bytes received */N unsigned int p Bdu$l_mblctr; /* Multicast frames received */N unsigned int pdu$l_bidctr; /* Frames sent, initially deferred */N unsigned int pdu$l_bs1ctr; /* Frames sent, single collision */N unsigned int pdu$l_bsmctr; /* Frames sent, multiple collisions */N unsigned short int pdu$w_sflctr; /* Send failure */ __union {N unsigned short int pdu$w_sflmap; /* Send failure reason bitmap */ __struct {N B unsigned pdu$v_sfl_exc : 1; /* Excessive collisions */N unsigned pdu$v_sfl_ccf : 1; /* Carrier check failure */N unsigned pdu$v_sfl_shc : 1; /* Short Circuit */N unsigned pdu$v_sfl_opc : 1; /* Open Circuit */N unsigned pdu$v_sfl_ftl : 1; /* Frame too long */N unsigned pdu$v_sfl_rfd : 1; /* Remote failure to defer */( unsigned pdu$v_fill_ B61_ : 2; } pdu$r_fill_58_; } pdu$r_fill_57_;N unsigned short int pdu$w_rflctr; /* Receive failure */ __union {N unsigned short int pdu$w_rflmap; /* Receive failure reason bitmap */ __struct {N unsigned pdu$v_rfl_bce : 1; /* Block Check error */N unsigned pdu$v_rfl_fme : 1; /* Framing error */N unsigned pdu$v_rfl_ftl : 1; /* Frame too long */ B( unsigned pdu$v_fill_62_ : 5; } pdu$r_fill_60_; } pdu$r_fill_59_;N unsigned short int pdu$w_ufdctr; /* No protocol type counter */N unsigned short int pdu$w_ovrctr; /* Data overrun */N unsigned short int pdu$w_sbuctr; /* System buffer unavailable */N unsigned short int pdu$w_ubuctr; /* No buffer available on all PTs */ } CTR_FRAME; #if !defined(__VAXC)0#define pdu$w_sflmap pdu$r_fill_57_.pd Bu$w_sflmapA#define pdu$v_sfl_exc pdu$r_fill_57_.pdu$r_fill_58_.pdu$v_sfl_excA#define pdu$v_sfl_ccf pdu$r_fill_57_.pdu$r_fill_58_.pdu$v_sfl_ccfA#define pdu$v_sfl_shc pdu$r_fill_57_.pdu$r_fill_58_.pdu$v_sfl_shcA#define pdu$v_sfl_opc pdu$r_fill_57_.pdu$r_fill_58_.pdu$v_sfl_opcA#define pdu$v_sfl_ftl pdu$r_fill_57_.pdu$r_fill_58_.pdu$v_sfl_ftlA#define pdu$v_sfl_rfd pdu$r_fill_57_.pdu$r_fill_58_.pdu$v_sfl_rfd0#define pdu$w_rflmap pdu$r_fill_59_.pdu$w_rflmapA#define pdu$v_rfl_bce pdu$r_fill_59_ B.pdu$r_fill_60_.pdu$v_rfl_bceA#define pdu$v_rfl_fme pdu$r_fill_59_.pdu$r_fill_60_.pdu$v_rfl_fmeA#define pdu$v_rfl_ftl pdu$r_fill_59_.pdu$r_fill_60_.pdu$v_rfl_ftl"#endif /* #if !defined(__VAXC) */ N#define PDU$G_CTR_802_DATA 19 /* Start of counters */ typedef struct _ctr_802_frame {N unsigned char pdu$b_ctr_802_code; /* Function code */N unsigned short int pdu$w_ctr_802_receipt; /* Receipt number */N unsigned __int64B pdu$q_date_802; /* Date (in 100 nsec units) */N unsigned __int64 pdu$q_misc_802; /* Inaccuracy fields et al */N unsigned __int64 pdu$q_ocrctr_802; /* Octets received */N unsigned __int64 pdu$q_octctr_802; /* Octets sent */N unsigned __int64 pdu$q_pdrctr_802; /* PDUs received */N unsigned __int64 pdu$q_pdtctr_802; /* PDUs sent */N unsigned __int64 pdu$q_morctr_802; /* MulBticast octets received */N unsigned __int64 pdu$q_mprctr_802; /* Multicast PDUs received */N unsigned __int64 pdu$q_defctr_802; /* Initially deferred PDUs sent */N unsigned __int64 pdu$q_sinctr_802; /* Single collision PDUs sent */N unsigned __int64 pdu$q_mulctr_802; /* Multiple collision PDUs sent */N unsigned __int64 pdu$q_excctr_802; /* Excessive collisions */N unsigned __int64 pdu$q_ccfctr_802; /* Carrier check failures B */N unsigned __int64 pdu$q_shcctr_802; /* MOP ONLY Short circuit failure */N unsigned __int64 pdu$q_opcctr_802; /* MOP ONLY Open circuit failure */N unsigned __int64 pdu$q_ttlctr_802; /* MOP ONLY Transmit too long */N unsigned __int64 pdu$q_latctr_802; /* Late collisions */N unsigned __int64 pdu$q_fcectr_802; /* Frame check errors */N unsigned __int64 pdu$q_alictr_802; /* Alignment errors */N unsigned __intB64 pdu$q_ftlctr_802; /* Frames too long */O unsigned __int64 pdu$q_uidctr_802; /* Unrecognized individual dest PDUs */N unsigned __int64 pdu$q_dorctr_802; /* Data overruns */N unsigned __int64 pdu$q_usbctr_802; /* Unavailable station buffers */N unsigned __int64 pdu$q_uubctr_802; /* Unavailable user buffers */N unsigned __int64 pdu$q_cdcctr_802; /* Collision detect check failures */ } CTR_802_FRAME;N#define PDU$G_CTR_OT BH_DATA 20 /* Start of counters */ typedef struct _ctr_oth_frame {N unsigned char pdu$b_ctr_oth_code; /* Function code */N unsigned char pdu$b_ctr_oth_dlink; /* Datalink type */N unsigned short int pdu$w_ctr_oth_receipt; /* Receipt number */N unsigned __int64 pdu$q_date_oth; /* Date (in 100 nsec units) */N unsigned __int64 pdu$q_misc_oth; /* Inaccuracy fields et al */N unsiBgned __int64 pdu$q_ocrctr_oth; /* Octets received */N unsigned __int64 pdu$q_octctr_oth; /* Octets sent */N unsigned __int64 pdu$q_pdrctr_oth; /* PDUs received */N unsigned __int64 pdu$q_pdtctr_oth; /* PDUs sent */N unsigned __int64 pdu$q_morctr_oth; /* Multicast octets received */N unsigned __int64 pdu$q_motctr_oth; /* Multicast octets sent */N unsigned __int64 pdu$q_mprctr_Both; /* Multicast PDUs received */N unsigned __int64 pdu$q_mptctr_oth; /* Multicast PDUs sent */N unsigned __int64 pdu$q_turclr_oth; /* Transmit underrun */N unsigned __int64 pdu$q_tflclr_oth; /* Transmit failure */N unsigned __int64 pdu$q_fcectr_oth; /* Frame check errors */N unsigned __int64 pdu$q_rseclr_oth; /* Frame status error */N unsigned __int64 pdu$q_alictr_oth; /* Alignment errors B */N unsigned __int64 pdu$q_ftlctr_oth; /* Frames too long */O unsigned __int64 pdu$q_uidctr_oth; /* Unrecognized individual dest PDUs */N unsigned __int64 pdu$q_umdctr_oth; /* Unrecognized multicast dest PDUs */N unsigned __int64 pdu$q_dorctr_oth; /* Data overruns */N unsigned __int64 pdu$q_usbctr_oth; /* Unavailable station buffers */N unsigned __int64 pdu$q_uubctr_oth; /* Unavailable user buffers */N Bunsigned __int64 pdu$q_mfcclr_oth; /* MAC frame count */N unsigned __int64 pdu$q_mecclr_oth; /* MAC error count */N unsigned __int64 pdu$q_mlcclr_oth; /* MAC lost count */N unsigned __int64 pdu$q_riiclr_oth; /* Ring initializations initiated */N unsigned __int64 pdu$q_rirclr_oth; /* Ring initializations received */N unsigned __int64 pdu$q_rbiclr_oth; /* Ring beacons initiated */N unsigned __int64 pdu$q_datBclr_oth; /* Duplicate address test failures */N unsigned __int64 pdu$q_dtdclr_oth; /* Duplicate tokens detected */N unsigned __int64 pdu$q_rprclr_oth; /* Ring purge errors */N unsigned __int64 pdu$q_fciclr_oth; /* FCI strip errors */N unsigned __int64 pdu$q_triclr_oth; /* Traces initiated */N unsigned __int64 pdu$q_lnkclr_oth; /* Link errors */ } CTR_OTH_FRAME;N#define PDU$C_RQC_COUNT 3 B /* Size of counters request message */ typedef struct _rqc_frame {N unsigned short int pdu$w_rqc_charcnt; /* Character count of message */N unsigned char pdu$b_rqc_code; /* Function code */N unsigned short int pdu$w_rqc_receipt; /* Receipt number */ } RQC_FRAME;N#define PDU$C_RQC_802_COUNT 3 /* Size of counters request message */ typedef struct _rqc_802_frame {N unsigned char pdu$b_rqc_802_code; /* FunctioBn code */N unsigned short int pdu$w_rqc_802_receipt; /* Receipt number */ } RQC_802_FRAME; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PDUDEF_LOADED */ ww[UM/*********************B******************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise BDevelopment, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. B**/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */F/* Source: 20-APR-1993 14:37:17 $1$DGA8345:[LIB_H.SRC]PFBDEF.SDL;1 *//*********************************************************************** B*********************************************************//*** MODULE $PFBDEF ***/#ifndef __PFBDEF_LOADED#define __PFBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /*B And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ B */N/* PAGE FAULT MONITOR BUFFER */N/*- */ #define PFB$B_USER_BUFFER 12N#define PFB$B_BUFFER 20 /*Beginning of PC/VA pairs */N#define PFB$K_LENGTH 524 /*Length of PFB */N#define PFB$C_LENGTH 524 /*Length of PFB */#defin Be PFB$S_PFBDEF 524 typedef struct _pfb {N struct _pfb *pfb$l_flink; /*Forward link */N struct _pfb *pfb$l_blink; /*Back link */N unsigned short int pfb$w_size; /*Structure size */N unsigned char pfb$b_type; /*Dynamic structure type (PFB) */N char pfbdef$$_spare_1; /*SPARE */N __struct { /*Buffer returned Bto user */N unsigned int pfb$l_reccnt; /*Record count */N unsigned int pfb$l_overflow; /*Overflow count */# char pfbdef$$_fill_1 [504]; } pfb$r_user_buffer; } PFB; #if !defined(__VAXC)3#define pfb$l_reccnt pfb$r_user_buffer.pfb$l_reccnt7#define pfb$l_overflow pfb$r_user_buffer.pfb$l_overflow"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTERB_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PFBDEF_LOADED */ ww;[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietBary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** prBoprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************* B*************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */F/* Source: 16-MAR-2004 09:59:05 $1$DGA8345:[LIB_H.SRC]PFLDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PFLDEF ***/#ifndef __PFLDEF_LOADED#define __PFLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-StaBndard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#dBefine __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* PAGE FILE CONTROL BLOCK */N/*- B */N/* */N/* ***** L_VBN, L_WINDOW, and L_PFC must be the same offset values as the */N/* ***** equivalently named offsets in $SECDEF */N/* */#define PFL$M_INITED 0x1#define PFL$M_PAGFILFUL 0x2#define PFL$M_SWPFILFUL 0x4#define PFL$M_SWAP_FILE 0x8#define PFL$M_DINSPEN 0x10 #define PFL$M_BSTOPPER 0x80000000Y#define PFL$K_MAX_EXPO_INDEX 6 /* Length of DIR_CLUSTERS array; in a quad are */N#define PFL$C_MAX_EXPO_INDEX 6 /* at most 2@6 = 64 bits set... */N#define PFL$K_ALLOC2DIR_SHIFT 4 /* Shift right to get */N#define PFL$C_ALLOC2DIR_SHIFT 4 /* directory bit count */N#define PFL$K_ALLOC2DIR_SIZE 16 /* Number of bits covered */N#define PFL$C_ALLOC2DIR_SIZE 16 /* by 1 directory bit B */N#define PFL$M_ALLOC2DIR_MASK 65535 /* Bitmask covering bits */N/* per dir bit */N#define PFL$K_LENGTH 156 /*SIZE OF PAGE FILE CONTROL BLOCK */N#define PFL$C_LENGTH 156 /*SIZE OF PAGE FILE CONTROL BLOCK */N#define PFL$S_PFLDEF 164 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _wcb; #endif /* #ifdef B__cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pfl {#pragma __nomember_alignmentN struct _pfl *pfl$l_flink; /*Forward link to next PFL */N struct _pfl *pfl$l_blink; /*Back link to previous PFL */N unsigned short int pfl$w_size; /*SIZE OF PAGE FILE CONTROL BLOCK */O B unsigned char pfl$b_type; /*PAGE FILE CONTROL BLOCK TYPE CODE */ unsigned char pfl$b_fill_3;O unsigned int pfl$l_pfc; /*PAGE FAULT CLUSTER FOR PAGE READS */N __union { /*BASE VBN */ unsigned int pfl$l_vbn;# unsigned __int64 pfl$q_vbn; } pfl$r_vbn_overlay;N struct _wcb *pfl$l_window; /*WINDOW ADDRESS */N unsigned int pfl$l_bitmapsiz; /*SIZE I BN BYTES OF PAGE FILE */W unsigned int pfl$l_frepagcnt; /*COUNT - 1 OF PAGES WHICH MAY BE ALLOCATED */N/*BIT = 1 MEANS AVAILABLE */ char pfl$b_fill_0_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* De Bfined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */ void *pfl$pq_bitmap;#else unsigned __int64 pfl$pq_bitmap;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *pfl$l_bitmap; /*ADDRESS OF START OF BIT MAP */) B unsigned int pfl$l_bitmap_hi;% } pfl$r_bitmap_short_ptr; } pfl$r_bitmap_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *pfl$pq_bitma Bp_dir; /* Pointer to bitmap "directory" */#else$ unsigned __int64 pfl$pq_bitmap_dir;#endifY unsigned __int64 pfl$q_last_dir_quad; /* Save initial value of last directory quad */#pragma __nomember_alignmentN unsigned int pfl$l_allocsiz; /*CURRENT ALLOCATION REQUEST SIZE */R unsigned int pfl$l_rsrvpagcnt; /* Count of pages which may be reserved */[ unsigned int pfl$l_swprefcnt; /* No. of processes using this file for swapping */O int pfl$l_Bpoolbytes; /* Save actually allocated pool size */W int pfl$l_s2pages; /* and number of S2 pages for deallocation */N unsigned int pfl$l_minfrepagcnt; /* Minimum free page count */N unsigned int pfl$l_pgflx; /* Page file vector index */ __union {N unsigned int pfl$l_flags; /*FLAGS FOR THIS PAGE FILE */ __struct {N unsigned pfl$v_inited : 1; /*THIS PAGE FILE IS USABLE B */S unsigned pfl$v_pagfilful : 1; /*REQUEST FOR PAGING SPACE HAS FAILED */U unsigned pfl$v_swpfilful : 1; /*REQUEST FOR SWAPPING SPACE HAS FAILED */N unsigned pfl$v_swap_file : 1; /* This is a swap file */N unsigned pfl$v_dinspen : 1; /* File deinstall pending */N unsigned pfl$$_fill_1 : 26; /*SPARE BITS FOR EXPANSION */W unsigned pfl$v_stopper : 1; /*RESERVED FOR ALL TIME (MUST NEVER BE SET B) */ } pfl$r_flags_bits; } pfl$r_flags_overlay;P unsigned int pfl$l_refcnt; /* No. of pages used in this pagefile */R unsigned int pfl$l_maxvbn; /*MASK APPLIED TO PTE WITH PAGING FILE */N/* BACKING STORE ADDRESS */P int pfl$l_startbyte; /* Starting byte offset for next scan */[ int pfl$l_max_alloc_expo; /* Look for 2**"this" consecutive directory bits */N int pf Bl$l_cur_alloc_expo; /* Current allocation size exponent */N int pfl$l_bitmap_quads; /* Bitmap size in quadwords */N int pfl$l_dir_quads; /* Directory size in quadwords */T int pfl$l_dir_cluster [8]; /* Counters of directory clusters by size */ char pfl$b_fill_1_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma B__nomember_alignment#endifT unsigned int pfl$l_bitmaploc; /*BITMAP MUST be at last and quad aligned */N/* if it's included here */#pragma __nomember_alignment char pfl$b_fill_2_ [4]; } PFL; #if !defined(__VAXC)-#define pfl$l_vbn pfl$r_vbn_overlay.pfl$l_vbn-#define pfl$q_vbn pfl$r_vbn_overlay.pfl$q_vbn8#define pfl$pq_bitmap pfl$r_bitmap_overlay.pfl$pq_bitmapM#define pfl$l_bitmap pfl$r_bitmap_overlay.pfl$r_bitmap_shoBrt_ptr.pfl$l_bitmapS#define pfl$l_bitmap_hi pfl$r_bitmap_overlay.pfl$r_bitmap_short_ptr.pfl$l_bitmap_hi3#define pfl$l_flags pfl$r_flags_overlay.pfl$l_flagsF#define pfl$v_inited pfl$r_flags_overlay.pfl$r_flags_bits.pfl$v_initedL#define pfl$v_pagfilful pfl$r_flags_overlay.pfl$r_flags_bits.pfl$v_pagfilfulL#define pfl$v_swpfilful pfl$r_flags_overlay.pfl$r_flags_bits.pfl$v_swpfilfulL#define pfl$v_swap_file pfl$r_flags_overlay.pfl$r_flags_bits.pfl$v_swap_fileH#define pfl$v_dinspen pfl$r_flags_over Blay.pfl$r_flags_bits.pfl$v_dinspenH#define pfl$v_stopper pfl$r_flags_overlay.pfl$r_flags_bits.pfl$v_stopper"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Ctypedef struct PFL * PFL_PQ; /* Pointer to a PFL structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unBsigned __int64 PFL_PQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PFLDEF_LOADED */ wwа[UM/***************************************************************************/M/** B **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** B **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** B **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */I/* Source: 01-MAR-2021 07:44:48 $1$DGA8345:[LIB_H.SRC]PFLMAPDEF.SDL;1 *//********************************************************************************************************************************//*** M BODULE $PFLMAPDEF ***/#ifndef __PFLMAPDEF_LOADED#define __PFLMAPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifB #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ B */N/* PAGE FILE MAPPING WINDOW BLOCK */N/*- */ !#define PFLMAP$M_PGFLPAG 0xFFFFFF!#define PFLMAP$M_PGFLX 0xFF000000*#define PFLMAP$M_PAGCNT 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pflmapenBtry {#pragma __nomember_alignment __union {( unsigned __int64 pflmap$q_entry; __struct {N unsigned pflmap$v_pgflpag : 24; /*Page file page number */N unsigned pflmap$v_pgflx : 8; /*Page file index */N unsigned pflmap$v_pagcnt : 32; /*Pages in this pointer */* } pflmap$r_pflmapentry_fields;' } pflmap$r_pflmapentry_overlay; } PFLMAPENTRY; #if !defined(__VAXC)B#define pflmap$q B_entry pflmap$r_pflmapentry_overlay.pflmap$q_entryb#define pflmap$v_pgflpag pflmap$r_pflmapentry_overlay.pflmap$r_pflmapentry_fields.pflmap$v_pgflpag^#define pflmap$v_pgflx pflmap$r_pflmapentry_overlay.pflmap$r_pflmapentry_fields.pflmap$v_pgflx`#define pflmap$v_pagcnt pflmap$r_pflmapentry_overlay.pflmap$r_pflmapentry_fields.pflmap$v_pagcnt"#endif /* #if !defined(__VAXC) */ #define PFLMAP$C_SHIFT_COUNT 6#define PFLMAP$C_MAXPTRS 64N#define PFLMAP$K_LENGTH 536 /*Size of structurBe */N#define PFLMAP$C_LENGTH 536 /*Size of structure */#define PFLMAP$S_PFLMAPDEF 536 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pflmap {#pragma __nomember_alignmentN unsigned int pflmap$l_pagecnt; /*Total pages in all pointers */ int pflmap$$_fill_2;N unsigned shoBrt int pflmap$w_size; /*Size of structure */N unsigned char pflmap$b_type; /*Structure type (DYN$C_PFLMAP) */N unsigned char pflmap$b_actptrs; /*No. of active pointers in window */N int pflmap$$_fill_3; /* Align to long */N/*Allow for 2**sc pointers */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_aBlignment __quadword#else#pragma __nomember_alignment#endifN PFLMAPENTRY pflmap$q_ptr [65]; /*Beginning of mapping pointers */ } PFLMAP; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PFLMAPDEF_LOADED */ wwBP˟[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 CBopyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, IncB. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:34 by OpenVMS SDL V3.7 */F/* Source: 19-OCT-2022 11:26:01 $1$DGA8345:[LIB_H.SRC]PFNDEF.SDL;1 *//*********************************** B*********************************************************************************************//*** MODULE $PFNDEF ***/#ifndef __PFNDEF_LOADED#define __PFNDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma B__required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union B#endif#endif  X#include /* Define the SHM_ID type; PFN contains embedded SHM_ID types */N/*+ */Q/* PFN memory data structure definition. This structure is used to access the */N/* fields within the PFN memory maps. In Galaxy systems, there is a PFN */N/* memory map for I/O space, private and shared memory. */N/* B */O/* In non-Galaxy systems, there is only a PFN memory map for private memory. */N/* */N/*- */N/* Verified for x86 port--Drew Mason */#define PMAP$M_CONSOLE 0x1#define PMAP$M_OPENVMS 0x2#define PMAP$M_AVAILABLE 0x4!#define PMAP$M_UNDEFINED_3_4 0x18#define PMAP$M_MEMORY_DISK 0x20##define PMAP$M B_UEFI_PAGE_TABLE 0x40#define PMAP$M_KERNEL_BASE 0x80#define PMAP$M_HWRPB 0x100$#define PMAP$M_UNDEFINED_9_15 0xFE00N#define PMAP$C_LENGTH 32 /* Length of PMAP */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */#else#pragma __nomember_alignment#endifNtypedef struct _pmap { /* 32-byte alignment */#pragma __nomember_alignment' unsigned __int64 pmap$iq_start_pfn; B' unsigned __int64 pmap$iq_pfn_count;. unsigned __int64 pmap$iq_memory_attribute;$ unsigned int pmap$l_memory_type;" unsigned short int pmap$w_rad; __union {( unsigned short int pmap$w_flags; __struct {( unsigned pmap$v_console : 1;( unsigned pmap$v_openvms : 1;* unsigned pmap$v_available : 1;. unsigned pmap$v_undefined_3_4 : 2;Y unsigned pmap$v_memory_disk : 1; /* boot memory disk, console bit also s Bet */N unsigned pmap$v_uefi_page_table : 1; /* console bit also set */N unsigned pmap$v_kernel_base : 1; /* console bit also set */N unsigned pmap$v_hwrpb : 1; /* console bit also set *// unsigned pmap$v_undefined_9_15 : 7; } pmap$r_flag_bits; } pmap$r_flags_overlay; } PMAP; #if !defined(__VAXC)6#define pmap$w_flags pmap$r_flags_overlay.pmap$w_flagsK#define pmap$v_console pmap$r_flags_overlay.Bpmap$r_flag_bits.pmap$v_consoleK#define pmap$v_openvms pmap$r_flags_overlay.pmap$r_flag_bits.pmap$v_openvmsO#define pmap$v_available pmap$r_flags_overlay.pmap$r_flag_bits.pmap$v_availableS#define pmap$v_memory_disk pmap$r_flags_overlay.pmap$r_flag_bits.pmap$v_memory_disk[#define pmap$v_uefi_page_table pmap$r_flags_overlay.pmap$r_flag_bits.pmap$v_uefi_page_tableS#define pmap$v_kernel_base pmap$r_flags_overlay.pmap$r_flag_bits.pmap$v_kernel_baseG#define pmap$v_hwrpb pmap$r_flags_overlay.pmap B$r_flag_bits.pmap$v_hwrpb"#endif /* #if !defined(__VAXC) */ N/*+ */N/* In Galaxy shared memory, PLNKs are used as the structure that links PFN */N/* database entries in the free page list (and other lists). */N/* */N/*- */N/* Verified for x86 port - Clair GrantB */N#define PLNK$C_LENGTH 16 /* Length of PLNK */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _plnk {#pragma __nomember_alignment __union { __struct {] unsigned __int64 plnk$i_next_pfn; /* Next PFN in this list, -1 terminates list */S B unsigned __int64 plnk$i_pfn_count; /* Number of PFNs in this cluster */& } plnk$r_plnk_i_quadwords; } plnk$r_link_union; } PLNK; #if !defined(__VAXC)I#define plnk$r_plnk_i_quadwords plnk$r_link_union.plnk$r_plnk_i_quadwords?#define plnk$i_next_pfn plnk$r_plnk_i_quadwords.plnk$i_next_pfnA#define plnk$i_pfn_count plnk$r_plnk_i_quadwords.plnk$i_pfn_count"#endif /* #if !defined(__VAXC) */ N/*+ B */N/* PFN Data Base Definitions */N/*- */N/* */N/* Define the PFN database record offsets. */N/* */[/* XDELTA provides embedded command strings for displaying the PFN database records. Any B */^/* change to the PFN database record here must be implemented in the XDELTA command strings */N/* as well to avoid breaking them. */N/* */#define PFN$M_PAGTYP 0x7#define PFN$M_LOC 0xF0#define PFN$M_BUFOBJ 0x100#define PFN$M_COLLISION 0x200#define PFN$M_BADPAG 0x400#define PFN$M_RPTEVT 0x800#define PFN$M_DELCON 0x1000#define PFN$M_MODIFY 0x2000 #define PFN$M_UNAVBAILABLE 0x4000!#define PFN$M_SWPPAG_VALID 0x8000"#define PFN$M_TOP_LEVEL_PT 0x10000#define PFN$M_SLOT 0x20000#define PFN$M_SHARED 0x40000#define PFN$M_ZEROED 0x80000%#define PFN$M_OUTER_MODE_BPT 0x100000##define PFN$M_BIG_PAGE_PTE 0x200000 #define PFN$M_PAGE_SIZE 0xC00000##define PFN$M_GHOST_ENTRY 0x1000000'#define PFN$M_PTE_INDEX1 0x7FFFFFFFFFFF!#define PFN$M_VRNX 0x800000000000#define PFN$S_VRNX_WIDTH 1#define PFN$S_INDEX_WIDTH 47#define PFN$M_GBLBAK 0x2$#define PFN$M_TYP0B 0x100000000000000/#define PFN$M_PARTIAL_SECTION 0x200000000000000#define PFN$M_STX 0xFFFF000#define PFN$M_CRF 0x10000000#define PFN$M_DZRO 0x20000000#define PFN$M_WRT 0x40000000"#define PFN$M_STX_HIBIT 0x80000000!#define PFN$M_PGFLPAG 0xFFFFFF000!#define PFN$M_PGFLX 0xFF000000000##define PFN$M_PGFLMAP 0xFFFFFFFF000"#define PFN$M_BAKX 0xFFFFFFFFFF000 #define PFN$M_GPTX 0xFFFFFFFF000#define PFN$C_ENTRY_SIZE 64N/* B */N#define PFN$C_FREPAGLST 0 /* On FREE page list */N#define PFN$C_MFYPAGLST 1 /* On MODIFIED page list */N#define PFN$C_BADPAGLST 2 /* On BAD page list */N#define PFN$C_RELPEND 3 /* RELease PENDing */N/* (when REFCNT=0 release PFN) */N#define PFN$C_UNTESTED 3 /* On UNTESTED memory list */N#define PFN$C_BRDERR 4 /* Read error while paging in */S#define PFN$C_WRTINPROG 5 /* Write in progress (by MFY PAG WRITER) */N#define PFN$C_RDINPROG 6 /* Read in progress (page in) */N#define PFN$C_ZERO_LIST 7 /* On ZEROED page list */N#define PFN$C_PRVPFN 8 /* On private PFN list */N#define PFN$C_ACTIVE 15 /* Page is ACTIVE and VALID */N/* B */N#define PFN$C_PROCESS 0 /* Process page */N#define PFN$C_SYSTEM 1 /* System page */N#define PFN$C_GLOBAL 2 /* Global page (read only) */N#define PFN$C_GBLWRT 3 /* Global Writable page */N#define PFN$C_PPGTBL 4 /* Process Page Table */N#define PFN$C_GPGTBL 5 /* Global Page TableB */N#define PFN$C_RESERVED 6 /* reserved */N#define PFN$C_UNKNOWN 7 /* Uninitialized db for this PFN */N#define PFN$C_PFNLST 1 /* Shared memory PFNLST page */N#define PFN$C_SHM_REG 3 /* Shared memory region page */N/* Verified for x86 port--Drew Mason */T#define PFN$C_PAGE_SIZE_8KB 0 /* PFN for 8-kB page (pair of 4-kB pages) */N B#define PFN$C_PAGE_SIZE_2MB 1 /* PFN for 4-MB page */N#define PFN$C_PAGE_SIZE_4MB 1 /* PFN for 4-MB page */N#define PFN$C_PAGE_SIZE_1GB 2 /* PFN for 2-GB page */N#define PFN$C_PAGE_SIZE_2GB 2 /* PFN for 2-GB page */#define PFN$S_PFNDEF 64  9#ifdef __cplusplus /* Define structure prototypes */ struct _phd; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && B!defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pfn {#pragma __nomember_alignment __union {! PLNK pfn$r_shm_list_link;N SHM_ID pfn$r_shm_reg_id; /* Shared memory region ID */ __struct {N/* Verified for x86 port - Clair Grant */ __union {N unsigned __int64 pfn$i_flinkB; /* Forward PFN link index */] unsigned int pfn$l_shrcnt; /* Number of process PTEs mapped to global page */& } pfn$r_flink_overlay;N/* Verified for x86 port - Clair Grant */ __union {N unsigned __int64 pfn$i_blink; /* Backward PFN link index */g unsigned int pfn$l_wslx_qw; /* Working Set List Index for valid page, quadword index */[ unsigned int pfn$l_gbl_lck_c Bnt; /* Count of memory locks for global page */& } pfn$r_blink_overlay;' } pfn$r_flink_blink_struct;" } pfn$r_flink_blink_union; __union {N unsigned int pfn$l_page_state; /* Page state information */N/* */N/* VIELD definitions in PFN$AL_PAGE_STATE */N/* */ B __struct {N unsigned pfn$v_pagtyp : 3; /* Page type */N unsigned pfndef$$_fill_1 : 1; /* Reserved */N unsigned pfn$v_loc : 4; /* Location of page */Z unsigned pfn$v_bufobj : 1; /* Set if any buffer objects reference this PFN */] unsigned pfn$v_collision : 1; /* Empty collision queue when page read complete */N unsigned pfn$v_badpag : 1; /* Bad page bit B */N unsigned pfn$v_rptevt : 1; /* Report event on I/O complete */N unsigned pfn$v_delcon : 1; /* Delete PFN contents when REF=0 */Q unsigned pfn$v_modify : 1; /* Modify bit, indicates page is dirty */f unsigned pfn$v_unavailable : 1; /* PFN is unavailable to software (such as for console) */\ unsigned pfn$v_swppag_valid : 1; /* Set if SWPPAG contains a swap page number */u unsigned pfn$v_top_level_pt : B1; /* Denotes a page table at the highest level of translation hierarchy */a unsigned pfn$v_slot : 1; /* Donotes a page mapped into a process's balance slot */N unsigned pfn$v_shared : 1; /* Shared memory page */N unsigned pfn$v_zeroed : 1; /* SHMGS page is zeroed */N/* Verified for x86 port - Greg Jordan */\ unsigned pfn$v_outer_mode_bpt : 1; /* PFN is for an outer mode Bottom PT PagBe */X unsigned pfn$v_big_page_pte : 1; /* PFN is for a PTE that maps a big page */V unsigned pfn$v_page_size : 2; /* Size of page represented by this entry */N/* 0 = 8 kB, 1 = 4 MB, 2 = 2 GB, 3 = Reserved */e unsigned pfn$v_ghost_entry : 1; /* PFN is part of a big page and does not really exist */N unsigned pfndef$$_fill_3 : 7; /* Reserved */! } pfn$r_pfndef_bits0;# } pfn$r_page_s Btate_overlay;N/* Alpha */N/* Verified for x86 port - Clair Grant */! unsigned int pfn$l_reserved1; __union {f unsigned __int64 pfn$i_pt_pfn; /* PFN of the PT that contains the PTE that maps target PFN */e unsigned int pfn$l_shm_cpp_id; /* SHM_CPP id that this page belongs to (if shared memory) */ } pfn$r_pt_pfn_overlay;N/* IA64 B */N/* X86 VRNX width is 1 */N/* IA64 */ __union {` unsigned __int64 pfn$q_pte_index; /* Container QW for the PTE index, vrnx, and refcnt */N/* PTE Index must occupies low 48 bits of this QW */ __struct {#if defined(__VAXC)- unsigned pfn$v_pte_index1_1 : 32;- unsi Bgned pfn$v_pte_index1_2 : 15;#elseN unsigned __int64 pfn$v_pte_index1 : 47; /* PTE Index */#endifN unsigned pfn$v_vrnx : 1; /* Virtual address space number */Y short int pfn$w_refcnt; /* Number of references to this PFN's contents */N/* Must be SIGNED so that the decref macro in */N/* pfn_macros.h works properly */$ } pfn$r_refcnt1_overlay;" B} pfn$r_pte_index_overlay; __union {Q unsigned __int64 pfn$q_bak; /* Backing store address for this page */N struct _phd *pfn$l_phd; /* PHD VA (L1PT PFN only) */N/* Verified for x86 port - Clair Grant */X unsigned __int64 pfn$i_color_flink; /* Forward PFN link for page's color list */ __struct {& unsigned pfn$v_fill_5 : 1;V unsigned pfn$v_gblbak : 1; /* Global backing store ad Bdress (GPTX form) */) unsigned pfn$v_fill_6_1 : 32;) unsigned pfn$v_fill_6_2 : 22;U unsigned pfn$v_typ0 : 1; /* Backing store in section (not pagefile) */X unsigned pfn$v_partial_section : 1; /* Page only partially maps a section */' unsigned pfn$v_fill_0_ : 6;! } pfn$r_pfndef_bits2; __struct {N unsigned pfn$v_fill_13 : 12; /* [0-11] skip to PFN field */N unsigned pfn$v_stx : 16; B /* Section Table Index */N unsigned pfn$v_crf : 1; /* Copy on Reference */N unsigned pfn$v_dzro : 1; /* Demand Zero */N unsigned pfn$v_wrt : 1; /* Section file accessed for write */) unsigned pfn$v_stx_hibit : 1; } pfn$r_bak_stx; __struct {N unsigned pfn$v_fill_9 : 12; /* [0-11] skip to PGFLPAG field */N unsigned pfn$v_pgflpag : 24; /* Page B file page (not a VBN) */N unsigned pfn$v_pgflx : 8; /* SYSTEM page file index */' unsigned pfn$v_fill_1_ : 4; } pfn$r_bak_pgfl; __struct {N unsigned pfn$v_fill_10 : 12; /* [0-11] skip to PGFLMAP field */N unsigned pfn$v_pgflmap : 32; /* PGFLPAG/PGFLX combination */' unsigned pfn$v_fill_2_ : 4; } pfn$r_bak_pgflmap; __struct {N unsigned pfn$v_fill_11 : 12; B /* [0-11] skip to PFN field */#if defined(__VAXC)' unsigned pfn$v_bakx_1 : 32;& unsigned pfn$v_bakx_2 : 8;#elseR unsigned __int64 pfn$v_bakx : 40; /* Backup Address (uninterpreted) */#endif' unsigned pfn$v_fill_3_ : 4; } pfn$r_bakx_bits; __struct {N unsigned pfn$v_fill_12 : 12; /* [0-11] skip to GPTX field */N unsigned pfn$v_gptx : 32; /* Global Page Table Index */' B unsigned pfn$v_fill_4_ : 4; } pfn$r_bak_gptx;` unsigned __int64 pfn$q_bak_prvpfn; /* Pointer to "owning" private list of (free) PFNs */ } pfn$r_bak_overlay;N/* Verified for x86 port - Clair Grant */ __union {Y unsigned __int64 pfn$i_color_blink; /* Backward PFN link for page's color list */U unsigned __int64 pfn$i_top_pt; /* Top level Page Table (for PROCESS PFNs) */" } pfn$r_color_blink_union; B __union {\ unsigned short int pfn$w_swppag; /* Page number in swap area to receive this page */` unsigned short int pfn$w_bo_refc; /* Buffer Object reference count (no swap possible) */( unsigned short int pfn$w_io_sts; } pfn$r_swppag_overlay;( unsigned short int pfn$w_pt_val_cnt;( unsigned short int pfn$w_pt_lck_cnt;( unsigned short int pfn$w_pt_win_cnt;N/* Location VIELD values */N/* B */N/* Page Type VIELD definitions */N/* */ } PFN; #if !defined(__VAXC)G#define pfn$r_shm_list_link pfn$r_flink_blink_union.pfn$r_shm_list_linkA#define pfn$r_shm_reg_id pfn$r_flink_blink_union.pfn$r_shm_reg_idd#define pfn$i_flink pfn$r_flink_blink_union.pfn$r_flink_blink_struct.pfn$r_flink_overlay.pfn$i_flinkBf#define pfn$l_shrcnt pfn$r_flink_blink_union.pfn$r_flink_blink_struct.pfn$r_flink_overlay.pfn$l_shrcntd#define pfn$i_blink pfn$r_flink_blink_union.pfn$r_flink_blink_struct.pfn$r_blink_overlay.pfn$i_blinkh#define pfn$l_wslx_qw pfn$r_flink_blink_union.pfn$r_flink_blink_struct.pfn$r_blink_overlay.pfn$l_wslx_qwp#define pfn$l_gbl_lck_cnt pfn$r_flink_blink_union.pfn$r_flink_blink_struct.pfn$r_blink_overlay.pfn$l_gbl_lck_cntB#define pfn$l_page_state pfn$r_page_state_overlay.pfn$l_page_stateM#define pfBn$v_pagtyp pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_pagtypG#define pfn$v_loc pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_locM#define pfn$v_bufobj pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_bufobjS#define pfn$v_collision pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_collisionM#define pfn$v_badpag pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_badpagM#define pfn$v_rptevt pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_rptevtM#define pfn$v_delcon pfn$r_page_statBe_overlay.pfn$r_pfndef_bits0.pfn$v_delconM#define pfn$v_modify pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_modifyW#define pfn$v_unavailable pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_unavailableY#define pfn$v_swppag_valid pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_swppag_validY#define pfn$v_top_level_pt pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_top_level_ptI#define pfn$v_slot pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_slotM#define pfn$v_shared pfn$r_page_Bstate_overlay.pfn$r_pfndef_bits0.pfn$v_sharedM#define pfn$v_zeroed pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_zeroed]#define pfn$v_outer_mode_bpt pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_outer_mode_bptY#define pfn$v_big_page_pte pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_big_page_pteS#define pfn$v_page_size pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_page_sizeW#define pfn$v_ghost_entry pfn$r_page_state_overlay.pfn$r_pfndef_bits0.pfn$v_ghost_entry6#define pfn$i_Bpt_pfn pfn$r_pt_pfn_overlay.pfn$i_pt_pfn>#define pfn$l_shm_cpp_id pfn$r_pt_pfn_overlay.pfn$l_shm_cpp_id?#define pfn$q_pte_index pfn$r_pte_index_overlay.pfn$q_pte_indexW#define pfn$v_pte_index1 pfn$r_pte_index_overlay.pfn$r_refcnt1_overlay.pfn$v_pte_index1K#define pfn$v_vrnx pfn$r_pte_index_overlay.pfn$r_refcnt1_overlay.pfn$v_vrnxO#define pfn$w_refcnt pfn$r_pte_index_overlay.pfn$r_refcnt1_overlay.pfn$w_refcnt-#define pfn$q_bak pfn$r_bak_overlay.pfn$q_bak-#define pfn$l_phd pfn$r_bak_overlay. Bpfn$l_phd=#define pfn$i_color_flink pfn$r_bak_overlay.pfn$i_color_flinkF#define pfn$v_gblbak pfn$r_bak_overlay.pfn$r_pfndef_bits2.pfn$v_gblbakB#define pfn$v_typ0 pfn$r_bak_overlay.pfn$r_pfndef_bits2.pfn$v_typ0X#define pfn$v_partial_section pfn$r_bak_overlay.pfn$r_pfndef_bits2.pfn$v_partial_section;#define pfn$v_stx pfn$r_bak_overlay.pfn$r_bak_stx.pfn$v_stx;#define pfn$v_crf pfn$r_bak_overlay.pfn$r_bak_stx.pfn$v_crf=#define pfn$v_dzro pfn$r_bak_overlay.pfn$r_bak_stx.pfn$v_dzro;#define pfn$Bv_wrt pfn$r_bak_overlay.pfn$r_bak_stx.pfn$v_wrtG#define pfn$v_stx_hibit pfn$r_bak_overlay.pfn$r_bak_stx.pfn$v_stx_hibitD#define pfn$v_pgflpag pfn$r_bak_overlay.pfn$r_bak_pgfl.pfn$v_pgflpag@#define pfn$v_pgflx pfn$r_bak_overlay.pfn$r_bak_pgfl.pfn$v_pgflxG#define pfn$v_pgflmap pfn$r_bak_overlay.pfn$r_bak_pgflmap.pfn$v_pgflmap?#define pfn$v_bakx pfn$r_bak_overlay.pfn$r_bakx_bits.pfn$v_bakx>#define pfn$v_gptx pfn$r_bak_overlay.pfn$r_bak_gptx.pfn$v_gptx;#define pfn$q_bak_prvpfn pfn$r_bak_overlay B.pfn$q_bak_prvpfnC#define pfn$i_color_blink pfn$r_color_blink_union.pfn$i_color_blink9#define pfn$i_top_pt pfn$r_color_blink_union.pfn$i_top_pt6#define pfn$w_swppag pfn$r_swppag_overlay.pfn$w_swppag8#define pfn$w_bo_refc pfn$r_swppag_overlay.pfn$w_bo_refc6#define pfn$w_io_sts pfn$r_swppag_overlay.pfn$w_io_sts"#endif /* #if !defined(__VAXC) */ N/* PRVPFN - head of a private list of free PFNs */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) B /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _prvpfn {#pragma __nomember_alignmentN struct _prvpfn *prvpfn$l_sqfl; /* PRVPFN queue flink */N struct _prvpfn *prvpfn$l_sqbl; /* PRVPFN queue blink */N unsigned short int prvpfn$w_size; /* structure size */N unsigned char prvpfn$b_type; /* structure type code (MISC) */N B unsigned char prvpfn$b_subtype; /* structure type subcode (PRVPFN) */N/* Verified for x86 port - Clair Grant */N unsigned int prvpfn$l_rsrvd; /* Filler for alignment */N unsigned __int64 prvpfn$i_count; /* number of elements in list */N/* Verified for x86 port - Clair Grant */N unsigned __int64 prvpfn$i_head; /* PFN of first element in queue */N/* Verified for x86 port - CBlair Grant */N unsigned __int64 prvpfn$i_tail; /* PFN of last element in queue */N unsigned int prvpfn$l_reclaimable; /* # PFNs attributed to this list */S unsigned int prvpfn$l_reclaimed; /* # PFNs reclaimed but not yet returned */O int prvpfn$l_priority; /* priority of elements on this list */N void (*prvpfn$a_callback)(); /* callback routine */ } PRVPFN;N#define PRVPFN$K_LENGTH 56 B /* length of block */N#define PRVPFN$C_LENGTH 56 /* length of block */ #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Dtypedef PFN * PFN_PQ; /* Long pointer to a PFN structure. */Ptypedef PFN ** PFN_PPQ; /* Long pointer to a pointer to a PFN structure. */Jtypedef PRVPFN * PRVPFN_PQ; /* Long pBointer to a PRVPFN structure. */Vtypedef PRVPFN ** PRVPFN_PPQ; /* Long pointer to a pointer to a PRVPFN structure. */Etypedef PMAP * PMAP_PQ; /* Long pointer to a PMAP structure */Qtypedef PMAP ** PMAP_PPQ; /* Long pointer to a pointer to a PMAP structure */Etypedef PLNK * PLNK_PQ; /* Long pointer to a PLNK structure */F#pragma __required_pointer_size __short /* Pointers are 32-bit */Etypedef PFN * PFN_PL; /* Short pointer to a PFN structure. */Qtypedef PFBN ** PFN_PPL; /* Short pointer to a pointer to a PFN structure. */Ktypedef PRVPFN * PRVPFN_PL; /* Short pointer to a PRVPFN structure. */Wtypedef PRVPFN ** PRVPFN_PPL; /* Short pointer to a pointer to a PRVPFN structure. */Ftypedef PMAP * PMAP_PL; /* Short pointer to a PMAP structure */Rtypedef PMAP ** PMAP_PPL; /* Short pointer to a pointer to a PMAP structure */Ftypedef PLNK * PLNK_PL; /* Short pointer to a PLNK structure */Q#pragma __required_pointer_size __reBstore /* Return to previous pointer size */#else typedef unsigned __int64 PFN_PQ;!typedef unsigned __int64 PFN_PPQ;#typedef unsigned __int64 PRVPFN_PQ;$typedef unsigned __int64 PRVPFN_PPQ;!typedef unsigned __int64 PMAP_PQ;"typedef unsigned __int64 PMAP_PPQ;!typedef unsigned __int64 PLNK_PQ; typedef unsigned __int32 PFN_PL;!typedef unsigned __int32 PFN_PPL;#typedef unsigned __int32 PRVPFN_PL;$typedef unsigned __int32 PRVPFN_PPL;!typedef unsigned __int32 PMAP_PL;"typedef unsignBed __int32 PMAP_PPL;!typedef unsigned __int32 PLNK_PL;##endif /* __INITIAL_POINTER_SIZE */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PFNDEF_LOADED */ ww@[UM/*****************************************************B**********************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/MB/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** B **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */H/* Source: 26-MAR-2021 17:31:57 $1$DGA8345:[LIB_H.SRC]PFREEDEF.SDL;1 *//***************************************************************************************************** B***************************//*** MODULE $PFREEDEF ***/#ifndef __PFREEDEF_LOADED#define __PFREEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size defaulBt to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ B */N/* PFREE - Pool free block */N/* */O/* This defines the common layout of a pool free block. Some fields are used */P/* only by pool checking code. NOTE WELL: Some of these fields must be at the */N/* same offsets as in the fork block. */N/*- B */ N#define PFREE$K_LENGTH 40 /* Length of poisoned block header */#define PFREE$S_PFREEDEF 40 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pfree {#pragma __nomember_alignmentN struct _pfree *pfree$l_flink; /* Forward link */ __union {N struct _pfree *pfrCee$l_blink; /* Queue backward link */N unsigned int pfree$l_free_size; /* Free block size */ } pfree$r_blink_overlay;N unsigned short int pfree$w_size; /* Standard size field */N unsigned char pfree$b_type; /* Standard type field */N __union { /* Common uses for this field */N unsigned char pfree$b_flck; /* Fork lock index */N unsigned c Char pfree$b_rmod; /* Request mode */N unsigned char pfree$b_subtype; /* Block subtype */ } pfree$r_misc_overlay; __union {N unsigned int pfree$l_checksum; /* Pool poisoning checksum */N void *pfree$l_fpc; /* Fork PC */ } pfree$r_fpc_overlay; __union {N unsigned int pfree$l_ipl; /* COM$DRVDEALMEM IPL */N __int64 pfree$q_fr C3; /* Fork R3 */ } pfree$r_ipl_overlay; __union {N void *pfree$l_cddm_pc; /* COM$DRVDEALMEM return PC */N __int64 pfree$q_fr4; /* Fork R4 */ } pfree$r_r4_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *pfree$ Cq_deal_pc; /* Deallocater return PC */#else" unsigned __int64 pfree$q_deal_pc;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *pfree$l_deal_pc; /* Deallocater return PC */ } pfree$r_pc_overlay; } PFREE; #if !defined(__VAXC)9#define pfree$l_blink pfree$r_blink_overlay.pfree$l_blin CkA#define pfree$l_free_size pfree$r_blink_overlay.pfree$l_free_size6#define pfree$b_flck pfree$r_misc_overlay.pfree$b_flck6#define pfree$b_rmod pfree$r_misc_overlay.pfree$b_rmod<#define pfree$b_subtype pfree$r_misc_overlay.pfree$b_subtype=#define pfree$l_checksum pfree$r_fpc_overlay.pfree$l_checksum3#define pfree$l_fpc pfree$r_fpc_overlay.pfree$l_fpc3#define pfree$l_ipl pfree$r_ipl_overlay.pfree$l_ipl3#define pfree$q_fr3 pfree$r_ipl_overlay.pfree$q_fr3:#define pfree$l_cddm_pc pfree$r_r4 C_overlay.pfree$l_cddm_pc2#define pfree$q_fr4 pfree$r_r4_overlay.pfree$q_fr4:#define pfree$q_deal_pc pfree$r_pc_overlay.pfree$q_deal_pc:#define pfree$l_deal_pc pfree$r_pc_overlay.pfree$l_deal_pc"#endif /* #if !defined(__VAXC) */ N/*+ */N/* PFREE_S2 - Pool free block */N/* */N/* This defines the common l Cayout of a pool free block for S2 nonpaged pool */N/* for X86 only. Some fields are used only by pool checking code. */N/* This data structure supports 64 bit addresses and removes unused fields */N/* from existing PFREE data structure */N/*- */#define PFREE_S2$C_LENGTH 40#define PFREE_S2$S_PFREEDEF 40 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* ICf using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pfree_s2 {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pfree_s2 *pfree_s2$q_flink; /* Forward link to next free packet */#else# unsigned __int64 pfree_s2$q_flink;#endifh unsigned shoCrt int pfree_s2$w_s2_tag; /* Reserved for S2. Set to MMG$POOL_TYPE: MMG$K_POOLTYPE_S2 */N unsigned char pfree_s2$b_type; /* Standard type field */N unsigned char pfree_s2$b_subtype; /* standard subtype */N unsigned int pfree_s2$l_filler0; /* alignment filler */N __int64 pfree_s2$q_free_size; /* Available space including header */N unsigned __int64 pfree_s2$q_checksum; /* Pool poisoning checksum */R#ifdef __INITIAL C_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */E void *pfree_s2$q_deal_pc; /* Deallocater return PC */#else% unsigned __int64 pfree_s2$q_deal_pc;#endif } PFREE_S2;N/* end x86 */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporte Cd */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PFREEDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard  CEnterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., a Cnd is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************************************** C*********************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */F/* Source: 26-AUG-2002 13:25:26 $1$DGA8345:[LIB_H.SRC]PFSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PFSDEF ***/#ifndef __PFSDEF_LOADED#define __PFSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __savCe#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __Cstruct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define PFS$M_PFM 0x3FFFFFFFFF##define PFS$M_PEC 0x3F0000000000000$#define PFS$M_PPL 0xC000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else C#pragma __nomember_alignment#endiftypedef struct _pfs {N/* */N/* Previous Function State Register */N/**************************************** */#pragma __nomember_alignment __union {0 unsigned __int64 pfs$iq_prev_func_state; __struct {#if defined(__VAXC)& unsigned pfs$v_pfm_1 : 32;% unsigned pfs C$v_pfm_2 : 6;#elseN unsigned __int64 pfs$v_pfm : 38; /* Previous frame marker */#endifN unsigned pfs$v_rv1 : 14; /* Reserved */N unsigned pfs$v_pec : 6; /* Previous epilog count */N unsigned pfs$v_rv2 : 4; /* Reserved */N unsigned pfs$v_ppl : 2; /* Previous Privilege Level */ } pfs$r_fields; } pfs$r_pfs_overlay; } PFS; C#if !defined(__VAXC)G#define pfs$iq_prev_func_state pfs$r_pfs_overlay.pfs$iq_prev_func_state:#define pfs$v_pfm pfs$r_pfs_overlay.pfs$r_fields.pfs$v_pfm:#define pfs$v_rv1 pfs$r_pfs_overlay.pfs$r_fields.pfs$v_rv1:#define pfs$v_pec pfs$r_pfs_overlay.pfs$r_fields.pfs$v_pec:#define pfs$v_rv2 pfs$r_pfs_overlay.pfs$r_fields.pfs$v_rv2:#define pfs$v_ppl pfs$r_pfs_overlay.pfs$r_fields.pfs$v_ppl"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SCIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PFSDEF_LOADED */ wwܠ[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietarbB PFN_MACROSBPFREEDEF CPFSDEFCPHDDEF]CPIBDEFnCPIPPDDEFCBPKBDEFCPKTADEFCPPLDEFCPLGDEFC<PLVDEFCPLVECDEFDvPMBDEF PMS_ROUTINESD POOLCHECKDEF POOL_ZONESDXPOSIXDEF2D POSIXVECDEF=DlPQBDEFODPRBDEFZD> PRCEVTDEFcD PRCPOLDEFkD PRCSTRDEFxD&PRIDEFDPRMDEFD PROCSTATED`PROC_READ_WRITEDRPROTODEFb PTE_FUNCTIONS RAD_MACROS SCH_ROUTINES. SCS_ROUTINESCy software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** propCrietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************* C***********************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */F/* Source: 31-MAY-2022 08:13:06 $1$DGA8345:[LIB_H.SRC]PHDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PHDDEF ***/#ifndef __PHDDEF_LOADED#define __PHDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-StandCard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#defCine __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Process Header Definitions. The process header contains the swappable */R/* scheduler and memory management data bases for a prCocess in the balance set. */N/* */ #define PHD$M_ASTEN 0xF#define PHD$M_ASTSR 0xF0#define PHD$M_ASTEN_KEN 0x1#define PHD$M_ASTEN_EEN 0x2#define PHD$M_ASTEN_SEN 0x4#define PHD$M_ASTEN_UEN 0x8#define PHD$M_ASTSR_KPD 0x10#define PHD$M_ASTSR_EPD 0x20#define PHD$M_ASTSR_SPD 0x40#define PHD$M_ASTSR_UPD 0x80N#define PHD$C_HWPCBLEN 216 /* Length of HWPCB */N#define PHD$K_HWPCBLCEN 216 /* Length of HWPCB */N/* */#define PHD$M_SW_FEN 0x1$#define PHD$M_AST_PENDING 0x80000000#define PHD$M_PFMFLG 0x1#define PHD$M_DALCSTX 0x2#define PHD$M_WSPEAKCHK 0x4#define PHD$M_NOACCVIO 0x8#define PHD$M_IWSPEAKCK 0x10#define PHD$M_IMGDMP 0x20#define PHD$M_NO_WS_CHNG 0x40#define PHD$M_SPARE_8 0x80#define PHD$M_LOCK_HEADER 0x100"#define PHD$M_FREWSLE_ACTIVE 0x200Y#dCefine PHD$K_LENGTH 904 /* Length of fixed part of the process header */Y#define PHD$C_LENGTH 904 /* Length of fixed part of the process header */  9#ifdef __cplusplus /* Define structure prototypes */ struct _wsl; struct _rde;struct _rights; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_a Clignment#endiftypedef struct _phd {#pragma __nomember_alignmentN unsigned __int64 phd$q_privmsk; /* Privilege mask */N unsigned short int phd$w_size; /* Structure size */N unsigned char phd$b_type; /* Dynamic structure type (PHD) */N char phd$$_spare_1; /* Spare */N/* */S/* Working set list pointers - theCse contain longword offsets from the beginning */N/* of the process header. */N/* */N unsigned int phd$l_wslist; /* 1st working set list entry */P unsigned int phd$l_wslock; /* 1st locked working set list entry */Q unsigned int phd$l_wsdyn; /* 1st dynamic working set list entry */N unsigned int phd$l_wsnext; /* Last CWSL entry replaced */N unsigned int phd$l_wslast; /* Last WSL entry in list */N/* */O/* The following three longwords specify the maximum and initial working set */N/* sizes for the process. Rather than containing the count of pages, they */S/* contains the longword index to what would be the last working set list entry. */N/*  C */U unsigned int phd$l_wsextent; /* Max working set size against borrowing */N unsigned int phd$l_wsquota; /* Quota on working set size */N unsigned int phd$l_dfwscnt; /* Default working set size */N unsigned int phd$l_cpulim; /* Limit on CPU time for process */N/* */N/* Process Section Table data base - PST_BASE_OFFSET is the byte offset */N/* f!Crom the beginning of the process header to the first longword beyond */N/* the process section table. PST_LAST and PST_FREE are section table */N/* indices to section table entries. */N/* */N unsigned int phd$l_pst_base_offset; /* Byte offset to base of PST */N/* First longword not in PST */N/* PST grows backwards from h"Cere */N unsigned int phd$l_pst_last; /* End of process section table */N/* (index of last PSTE allocated) */N unsigned int phd$l_pst_free; /* Head of free PSTE list */N/* (index of first free PSTE) */N/* */N/* MMG Context #C */N/* */j unsigned int phd$l_iorefc; /* Num reasons to keep PHD resident due to pages locked for I/O */N unsigned __int64 phd$q_next_region_id; /* Next user-defined region id */N int phd$l_pst_base_max; /* section index of top PST */O unsigned int phd$l_emptpg; /* Count of empty working set pages */N unsigned int phd$l_dfpfc; /* Default p$Cage fault cluster */N unsigned int phd$l_pgtbpfc; /* Page table cluster factor */N/* */N/* Quotas and Limits */N/* */N unsigned int phd$l_astlm; /* AST limit */N unsigned int phd$l_pshared; /* process shared object flag */%CO unsigned int phd$l_wssize; /* Current allowed working set size */P unsigned int phd$l_diocnt; /* Count of all direct I/O operations */R unsigned int phd$l_biocnt; /* Count of all buffered I/O operations */N unsigned int phd$l_phvindex; /* Process header vector index */N __int64 phd$q_fredptr; /* pointer to first FRED page */ __union {N unsigned __int64 phd$q_lefc; /* Local event flags */ &C __struct {N unsigned int phd$l_lefc_0; /* Cluster 0 */N unsigned int phd$l_lefc_1; /* Cluster 1 */" } phd$r_lefc_clusters; } phd$r_lefc_overlay;N/* */S/* Hardware Privileged Context Block (HWPCB) - This structure must be aligned to */S/* a 128 byte boundary. Natural alignment prevents the structure from crossing a */N/* p'Cage boundary. */N/* */R/* NOTE WELL: There are bit symbols defined here for accessing the saved ASTEN, */U/* ASTSR, FEN and DATFX values in the HWPCB. These symbols are NOT to be used when */Z/* interfacing to the ASTEN, ASTSR, FEN or DATFX internal processor registers directly. */O/* See the specific internal register definitions for bitmasks and constants */I/* t(Co be used when interfacing to the IPRs directly. */N/* */ __union {N unsigned __int64 phd$q_hwpcb; /* Base of HWPCB */N unsigned __int64 phd$q_ksp; /* Kernel stack pointer */ } phd$r_hwpcb_overlay;N unsigned __int64 phd$q_esp; /* Executive stack pointer */N unsigned __int64 phd$q_ssp; /* Supervisor stack pointe )Cr */N unsigned __int64 phd$q_usp; /* User stack pointer */N unsigned __int64 phd$q_ptbr [4]; /* Page table base for each mode */U unsigned __int64 phd$q_asn; /* ASN (to be combined with mode for PCID) */ __union {N unsigned __int64 phd$q_astsr_asten; /* ASTSR / ASTEN quadword */ __struct {N unsigned phd$v_asten : 4; /* AST Enable Register */N unsigned phd$v_astsr : 4; /* AST *C Pending Summary Register */ } phd$r_ast_bits0; __struct {N unsigned phd$v_asten_ken : 1; /* Kernel AST Enable = 1 */N unsigned phd$v_asten_een : 1; /* Executive AST Enable = 1 */N unsigned phd$v_asten_sen : 1; /* Supervisor AST Enable = 1 */N unsigned phd$v_asten_uen : 1; /* User AST Enable = 1 */N unsigned phd$v_astsr_kpd : 1; /* Kernel AST Pending = 1 */N unsign+Ced phd$v_astsr_epd : 1; /* Executive AST Pending = 1 */N unsigned phd$v_astsr_spd : 1; /* Supervisor AST Pending = 1 */N unsigned phd$v_astsr_upd : 1; /* User AST Pending = 1 */ } phd$r_ast_bits1; } phd$r_ast_overlay;N unsigned __int64 phd$q_perf_ctrl; /* Perfomance monitoring control */N unsigned __int64 phd$q_cc; /* Cycle Counter */\ unsigned __int64 phd$q_unq; /* Process Unique Valu ,Ce (X86_64 FSBASE, IA64 R13) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */` void *phd$pq_alphareg [4]; /* Pointers to emulated Alpha registers for each mode */#else& unsigned __int64 phd$pq_alphareg [4];#endifN unsigned char phd$b_pmod; /* Previous mode */Q unsigned char phd$b_was_scheduled; /* Process was scheduled -C at least once */ char phd$b_reserved_1 [6];N unsigned int phd$l_interrupt_depth; /* Interrupt depth */N int phd$l_cur_frame_mode; /* Mode of currently active frame */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *phd$pq_cur_frame; /* Currently active frame */#else# unsigned __int64 phd$pq_cur_f .Crame;#endif& unsigned __int64 phd$q_kstack_top;) unsigned __int64 phd$q_kstack_bottom;N __int64 phd$q_pal_rsvd [5]; /* Reserved for PAL Scratch */N/* End of Hardware Privileged Context Block (HWPCB). */N/* */N/* */N/* XSAVE area for X86 processor context */N/* /C */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *phd$pq_xsave_area; /* Pointer to XSAVE area */#else$ unsigned __int64 phd$pq_xsave_area;#endifN/* X86_64, IA64, Alpha */N/* 0C */N/* Note: The Alpha architecture defines that the FEN bit in HWPCB cannot */N/* be read, so a separate software FEN bit must be kept. For performance */N/* reasons, we make this bit the low-bit. */N/* */N/* Note2: This field must immediately follow the floating point register */J/* save area. Do not move this field. By placing this field af 1Cter */I/* the FPR save area, this field can be referenced using $FREDDEF */I/* as well as this data structure. */N/* */ __union {N unsigned int phd$l_flags2; /* Flags2 longword */ __struct {N unsigned phd$v_sw_fen : 1; /* Software FEN bit */, unsigned phd$v_fill_flags2 : 30;N unsigned p2Chd$v_ast_pending : 1; /* AST pending optimization */ } phd$r_flags2_bits; } phd$r_flags2_overlay;S unsigned int phd$l_extracpu; /* Accumulated CPU time limit extension */W unsigned __int64 phd$q_asnseq; /* Address Space Number (Region ID) Sequence */U unsigned int phd$l_extdynws; /* Extra dynamic working set list entries */N/* above required WSFLUID minimum */N unsigned int phd$l_pageflts; 3C /* Count of page faults */U unsigned int phd$l_fow_flts; /* Count of Fault On Write faults incurred */T unsigned int phd$l_for_flts; /* Count of Fault On Read faults incurred */W unsigned int phd$l_foe_flts; /* Count of Fault On Execute faults incurred */N unsigned int phd$l_cputim; /* Accumulated CPU time charged */R unsigned int phd$l_cpumode; /* Access mode to notify about cputime */O unsigned int phd$l_awsmode; 4C /* Access mode flag for auto WS AST */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _wsl *phd$q_wsl; /* pointer to WSL */#else uns 5Cigned __int64 phd$q_wsl;#endifN/* */N/* Page Table Statistics */N/* */#pragma __nomember_alignmentN unsigned int phd$l_ptcntlck; /* Count of page tables containing */N/* 1 or more locked WSLEs */N unsigned int phd$l_ptcntval; /*6C Count of page tables containing */N/* 1 or more valid WSLEs */N unsigned int phd$l_ptcntact; /* Count of active page tables */N unsigned int phd$l_ptcntmax; /* Max count of page tables */N/* which have non-zero PTEs */N unsigned __int64 phd$q_login; /* system time at process creation */N unsigned __int64 phd$q_virtpeak; /* peak virtual size 7C */N unsigned int phd$l_wspeak; /* peak workingset size */R int phd$l_wsfluid; /* Guaranteed number of fluid WS pages */N unsigned int phd$l_wsauth; /* Authorized working set size */N unsigned int phd$l_wsauthext; /* Authorized WS extent */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointe 8Crs */#endifN void *phd$l_reslsth; /* Pointer to resource list */N unsigned int phd$l_authpri; /* Initial process priority */N unsigned __int64 phd$q_authpriv; /* Authorized privileges mask */N unsigned __int64 phd$q_imagpriv; /* Installed image privileges mask */P unsigned int phd$l_imgcnt; /* Image counter bumped by SYSRUNDWN */N unsigned int phd$l_pfltrate; /* Page fault rate */R unsi9Cgned int phd$l_pflref; /* Page faults at end of last interval */N unsigned int phd$l_timref; /* Time at end of last interval */N unsigned int phd$l_pgfltio; /* Count of pagefault I/O */S __struct { /* Minimum authorized security clearance */) unsigned char phd$$$_fill_3 [20]; } phd$r_min_class;S __struct { /* Maximum authorized security clearance */) unsigned char phd$ :C$$_fill_4 [20]; } phd$r_max_class;N unsigned int phd$l_volumes; /* count of volumes mounted */O __int64 phd$q_wsl_next; /* VA of next page for WSL Expansion */O __int64 phd$q_wsl_last; /* VA of last page for WSL Expansion */ __union {N __int64 phd$q_pagefile_refs; /* process references to pagefiles */ __struct {N int phd$l_pagefile_refs_lo; /* lo longword */N int ph;Cd$l_pagefile_refs_hi; /* hi longword */( } phd$r_pagefile_refs_longs;& } phd$r_pagefile_refs_overlay;N unsigned __int64 phd$q_istart; /* image activation time */N/* */N/* ***** BE CAREFUL ABOUT SYNCHRONIZING ACCESS TO THESE FLAGS !! ***** */N/* */R/* Before adding new flags to this longworChe lower IPL */Y/* write to be reexecuted. Writes at IPL$_MMG need not be interlocked since the writes */I/* are synchronized by virtue of occurring at the synchronization IPL. */N/* */N/* EXCEPTION !! */N/* */O/* If the flags are for the system PHD, then being at IPL$_MMG is not enough */?CP/* protection. In this case only, even the writes that occur at this IPL must */P/* be done as interlocked sequences since this is not a case of being limited */I/* to process context only. */N/* */ __union {N unsigned int phd$l_flags; /* Flags longword */ __struct {N unsigned phd$v_pfmflg : 1; /* Page fault monitoring e@Cnabled */Q unsigned phd$v_dalcstx : 1; /* Need to deallocate section indices */V unsigned phd$v_wspeakchk : 1; /* Check for new working set size (proc) */R unsigned phd$v_noaccvio : 1; /* Set after inswap of process header */W unsigned phd$v_iwspeakck : 1; /* Check for new working set size (image) */N unsigned phd$v_imgdmp : 1; /* Take image dump on error exit */U unsigned phd$v_no_ws_chng : 1; /* No change to workingAC set or swapping */N/* (Transient use by MMG code only) */N unsigned phd$$_spare_8 : 1; /* was: PGFLACC */N unsigned phd$v_lock_header : 1; /* Do not swap process header */N/* (Transient use by MMG code only) */[ unsigned phd$v_frewsle_active : 1; /* FREWSLE critical section is active for */N/* a specific process context BC */' unsigned phd$v_fill_0_ : 6; } phd$r_flags_bits; } phd$r_flags_overlay;N/* */N/* Cluster-Wide Process Services */N/* */N unsigned int phd$l_pscanctx_seqnum; /* PSCAN sequence number */N unsigned __int64 phd$q_pscanctx_queue; /* Queue of PSCAN blocks CC */N unsigned int phd$l_icputim; /* initial image CPU time */N unsigned int phd$l_ifaults; /* initial image fault count */N unsigned int phd$l_ifaultio; /* initial image fault I/O count */N unsigned int phd$l_iwspeak; /* image workingset peak */N unsigned int phd$l_ipagefl; /* image pagefile peak usage */N unsigned int phd$l_idiocnt; /* initial image direct I/O count */N unsigned iDCnt phd$l_ibiocnt; /* initial image buffered I/O count */N unsigned int phd$l_ivolumes; /* initial image volume mount count */N/* */P/* PTE Backpointer range for process page table pages which cannot be deleted */N/* by the modified page writer due to VA space creation in progress. */N/* */R#ifdef __INITIAL_POINTER_SIZE /* De ECfined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *phd$pq_pt_no_delete1; /* Low PTE backpointer */#else' unsigned __int64 phd$pq_pt_no_delete1;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *phd$pq_pt_no_delete2; /* High PTE ba FCckpointer */#else' unsigned __int64 phd$pq_pt_no_delete2;#endifN unsigned __int64 phd$q_free_pte_count; /* Count of free PTEs */N/* */N/* Beginning of process permanent region descriptors for P0, P1 and P2 */N/* ** Warning *** */N/* The layout of the following fields must match rdedef.sdl */N/* ************** GC */N/* */ __union {N __int64 phd$q_p0_rde; /* RDE for P0 space */ __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifS struct _rde *phd$ps_p0_va_list_flink; /* Pointer to HCfirst RDE in P0 */R struct _rde *phd$ps_p0_va_list_blink; /* Pointer to last RDE in P0 */ } phd$r_p0_va_list; } phd$r_p0_rde_overlay;O unsigned int phd$$$_p0_rde_fields [2]; /* SIZE, TYPE, SUBTYP, TABLE_LINK */N unsigned int phd$l_p0_flags; /* P0 RDE flags */N unsigned int phd$l_p0_region_prot; /* Region protection */N unsigned __int64 phd$q_p0_region_id; /* P0 region id */R#ifdef __I ICNITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *phd$pq_p0_start_va; /* Starting address of P0 region */#else% unsigned __int64 phd$pq_p0_start_va;#endifN unsigned __int64 phd$q_p0_region_size; /* Size of P0 region */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_point JCer_size __long /* And set ptr size default to 64-bit pointers */N void *phd$pq_p0_first_free_va; /* 1st free VA at end of P0 space */#else* unsigned __int64 phd$pq_p0_first_free_va;#endifN int phd$l_frep0va; /* 1st free VA at end of P0 space */ } phd$r_frep0va_overlay; __union {N __int64 phd$q_p1_rde; /* RDE for P0 space */ __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size prag KCmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifS struct _rde *phd$ps_p1_va_list_flink; /* Pointer to first RDE in P0 */R struct _rde *phd$ps_p1_va_list_blink; /* Pointer to last RDE in P0 */ } phd$r_p1_va_list; } phd$r_p1_rde_overlay;O unsigned int phd$$$_p1_rde_fields [2]; /* SIZE, TYPE, SUBTYP, TABLE_LINK */N unsigned int phd$l_p1_flags; /* P1 RDE flags LC */N unsigned int phd$l_p1_region_prot; /* Region protection */N unsigned __int64 phd$q_p1_region_id; /* P1 region id */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *phd$pq_p1_start_va; /* Starting address of P1 region */#else% unsigned __int64 phd$pq_p1_start_va;#endifN unsigned __int64 MC phd$q_p1_region_size; /* Size of P1 region */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *phd$pq_p1_first_free_va; /* 1st free VA at end of P1 space */#else* unsigned __int64 phd$pq_p1_first_free_va;#endifN int phd$l_frep1va; /* 1st free VA at end of P1 space */ } phd$r_frep1va_overlay; NC __union {N __int64 phd$q_p2_rde; /* RDE for P0 space */ __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifS struct _rde *phd$ps_p2_va_list_flink; /* Pointer to first RDE in P0 */R struct _rde *phd$ps_p2_va_list_blink; /* Pointer to last RDE in P0 */ } phd$r_p2_va_list;OC } phd$r_p2_rde_overlay;O unsigned int phd$$$_p2_rde_fields [2]; /* SIZE, TYPE, SUBTYP, TABLE_LINK */N unsigned int phd$l_p2_flags; /* P2 RDE flags */N unsigned int phd$l_p2_region_prot; /* Region protection */N unsigned __int64 phd$q_p2_region_id; /* P2 region id */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size def PCault to 64-bit pointers */N void *phd$pq_p2_start_va; /* Starting address of P2 region */#else% unsigned __int64 phd$pq_p2_start_va;#endifN unsigned __int64 phd$q_p2_region_size; /* Size of P2 region */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *phd$pq_p2_first_free_va; /* 1st free VA at end of P2 space */#elseQC* unsigned __int64 phd$pq_p2_first_free_va;#endifN/* */N/* End of process permanent region descriptors for P0, P1 and P2 */N/* */Q unsigned __int64 phd$q_image_authpriv; /* Installed image authorized privs */N unsigned __int64 phd$q_image_permpriv; /* Installed image initial privs */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenRCever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifT struct _rights *phd$ar_image_authrights; /* Installed image authorized rights */N struct _rights *phd$ar_image_rights; /* Installed image initial rights */R struct _rights *phd$ar_subsystem_authrights; /* Subsystem authorized rights */N struct _rights *phd$ar_subsystem_rights; /* Subsystem initial rights */N/* SC */P/* For threaded processors, we have a field to hold fractional CPU time ticks */N/* */N/* Temporary for xbuild, needs x86 review - Clair Grant */e unsigned __int64 phd$q_partial_cputim_ticks; /* Count up partial ticks for threaded processors */ __int64 phd$$_spare_3;N/* */N/* Other fTCields */N/* */N/* Verified for x86 port, Camiel Vanderhoeven */U unsigned __int64 phd$q_xsave_area_region; /* Region to allocate XSAVE areas in */P unsigned __int64 phd$q_pgfltreads; /* Page fault pages read for read IOs */U unsigned __int64 phd$q_biobytes; /* Bytes involved in the BIOBCNT statistic */U unsigned __intUC64 phd$q_diobytes; /* Bytes involved in the DIOBCNT statistic */U unsigned int phd$l_biobcnt; /* Count of IO$_READxBLK and IO$_WRITExBLK */N/* function codes processed */U unsigned int phd$l_diobcnt; /* Count of IO$_READxBLK and IO$_WRITExBLK */N/* function codes processed */N/* */N/* End of the fixed VCportion of the process header. */N/* */ } PHD; #if !defined(__VAXC)0#define phd$q_lefc phd$r_lefc_overlay.phd$q_lefcH#define phd$l_lefc_0 phd$r_lefc_overlay.phd$r_lefc_clusters.phd$l_lefc_0H#define phd$l_lefc_1 phd$r_lefc_overlay.phd$r_lefc_clusters.phd$l_lefc_13#define phd$q_hwpcb phd$r_hwpcb_overlay.phd$q_hwpcb/#define phd$q_ksp phd$r_hwpcb_overlay.phd$q_ksp=#define phd$q_astsr_asten WCphd$r_ast_overlay.phd$q_astsr_astenA#define phd$v_asten phd$r_ast_overlay.phd$r_ast_bits0.phd$v_astenA#define phd$v_astsr phd$r_ast_overlay.phd$r_ast_bits0.phd$v_astsrI#define phd$v_asten_ken phd$r_ast_overlay.phd$r_ast_bits1.phd$v_asten_kenI#define phd$v_asten_een phd$r_ast_overlay.phd$r_ast_bits1.phd$v_asten_eenI#define phd$v_asten_sen phd$r_ast_overlay.phd$r_ast_bits1.phd$v_asten_senI#define phd$v_asten_uen phd$r_ast_overlay.phd$r_ast_bits1.phd$v_asten_uenI#define phd$v_astsr_kpd phd$XCr_ast_overlay.phd$r_ast_bits1.phd$v_astsr_kpdI#define phd$v_astsr_epd phd$r_ast_overlay.phd$r_ast_bits1.phd$v_astsr_epdI#define phd$v_astsr_spd phd$r_ast_overlay.phd$r_ast_bits1.phd$v_astsr_spdI#define phd$v_astsr_upd phd$r_ast_overlay.phd$r_ast_bits1.phd$v_astsr_upd6#define phd$l_flags2 phd$r_flags2_overlay.phd$l_flags2H#define phd$v_sw_fen phd$r_flags2_overlay.phd$r_flags2_bits.phd$v_sw_fenR#define phd$v_ast_pending phd$r_flags2_overlay.phd$r_flags2_bits.phd$v_ast_pendingK#define phd$q_paYCgefile_refs phd$r_pagefile_refs_overlay.phd$q_pagefile_refsk#define phd$l_pagefile_refs_lo phd$r_pagefile_refs_overlay.phd$r_pagefile_refs_longs.phd$l_pagefile_refs_lok#define phd$l_pagefile_refs_hi phd$r_pagefile_refs_overlay.phd$r_pagefile_refs_longs.phd$l_pagefile_refs_hi3#define phd$l_flags phd$r_flags_overlay.phd$l_flagsF#define phd$v_pfmflg phd$r_flags_overlay.phd$r_flags_bits.phd$v_pfmflgH#define phd$v_dalcstx phd$r_flags_overlay.phd$r_flags_bits.phd$v_dalcstxL#define phd$v_wspeakchk ZCphd$r_flags_overlay.phd$r_flags_bits.phd$v_wspeakchkJ#define phd$v_noaccvio phd$r_flags_overlay.phd$r_flags_bits.phd$v_noaccvioL#define phd$v_iwspeakck phd$r_flags_overlay.phd$r_flags_bits.phd$v_iwspeakckF#define phd$v_imgdmp phd$r_flags_overlay.phd$r_flags_bits.phd$v_imgdmpN#define phd$v_no_ws_chng phd$r_flags_overlay.phd$r_flags_bits.phd$v_no_ws_chngP#define phd$v_lock_header phd$r_flags_overlay.phd$r_flags_bits.phd$v_lock_headerV#define phd$v_frewsle_active phd$r_flags_overlay.phd$r_flags_bit[Cs.phd$v_frewsle_active6#define phd$q_p0_rde phd$r_p0_rde_overlay.phd$q_p0_rde]#define phd$ps_p0_va_list_flink phd$r_p0_rde_overlay.phd$r_p0_va_list.phd$ps_p0_va_list_flink]#define phd$ps_p0_va_list_blink phd$r_p0_rde_overlay.phd$r_p0_va_list.phd$ps_p0_va_list_blinkM#define phd$pq_p0_first_free_va phd$r_frep0va_overlay.phd$pq_p0_first_free_va9#define phd$l_frep0va phd$r_frep0va_overlay.phd$l_frep0va6#define phd$q_p1_rde phd$r_p1_rde_overlay.phd$q_p1_rde]#define phd$ps_p1_va_list_flink phd$r_\Cp1_rde_overlay.phd$r_p1_va_list.phd$ps_p1_va_list_flink]#define phd$ps_p1_va_list_blink phd$r_p1_rde_overlay.phd$r_p1_va_list.phd$ps_p1_va_list_blinkM#define phd$pq_p1_first_free_va phd$r_frep1va_overlay.phd$pq_p1_first_free_va9#define phd$l_frep1va phd$r_frep1va_overlay.phd$l_frep1va6#define phd$q_p2_rde phd$r_p2_rde_overlay.phd$q_p2_rde]#define phd$ps_p2_va_list_flink phd$r_p2_rde_overlay.phd$r_p2_va_list.phd$ps_p2_va_list_flink]#define phd$ps_p2_va_list_blink phd$r_p2_rde_overlay.phd$r_p]C2_va_list.phd$ps_p2_va_list_blink"#endif /* #if !defined(__VAXC) */ N#define PHD$S_PHDDEF 904 /* Old size name - synonym */ "#pragma required_pointer_size save"#pragma required_pointer_size longtypedef PHD * PHD_PQ;##pragma required_pointer_size shorttypedef PHD * PHD_PL;%#pragma required_pointer_size restore $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_poi^Cnter_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PHDDEF_LOADED */ wwQ[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, an_Cd is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** auth`Corized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************************************************** aC***************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */F/* Source: 16-JUN-1993 10:44:58 $1$DGA8345:[LIB_H.SRC]PIBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PIBDEF ***/#ifndef __PIBDEF_LOADED#define __PIBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmebCntR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)cC#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* PERFORMANCE I/O INFORMATION BLOCK */N/*- */N#define PIB$S_PIBDEF 1 /* Old size na dCme - synonym */ typedef struct _pib {N unsigned char pib$b_type; /*TYPE OF ENTRY */N/* */N/* START OF I/O REQUEST TRANSACTION MESSAGE BLOCK */N/* */ } PIB;N#define PIB$K_SRQ_SIZE 32 /*LENGTH OF START I/O MESSAGE */N#define PIB$C_SRQ_SIZE 32 eC/*LENGTH OF START I/O MESSAGE */N/* */N#define PIB$S_PIBDEF1 32 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; #endif /* #ifdef __cplusplus */ typedef struct _pib1 { char pib$$_fill_5;N unsigned char pib$b_srq_pri; /*BASE PRIORITY OF PROCESS */N unsigned short int pib$w_srq_acon; /*Access control ifCnfo from WCB or 0 */N unsigned __int64 pib$q_srq_time; /*TIME OF I/O TRANSACTION */P unsigned int pib$l_srq_seqn; /*SEQUENCE NUMBER OF I/O TRANSACTION */N unsigned int pib$l_srq_pid; /*REQUESTER PID */N struct _ucb *pib$l_srq_ucb; /*ADDRESS OF DEVICE UCB */N unsigned short int pib$w_srq_func; /*I/O FUNCTION CODE */N unsigned short int pib$w_srq_sts; /*I/O PACKET STATUS */N gC unsigned char pib$b_srq_access; /*Access control info from WCB or 0 */N char pib$$_fill_1 [3]; /*SPARE UNUSED BYTES */N/* START OF I/O TRANSACTION MESSAGE BLOCK */N/* */ } PIB1;O#define PIB$K_SIO_SIZE 24 /*LENGTH OF I/O TRANSACTION MESSAGE */O#define PIB$C_SIO_SIZE 24 /*LENGTH OF I/O TRANSACTION MESSAGE */N/* hC */N#define PIB$S_PIBDEF2 24 /* Old size name - synonym */ typedef struct _pib2 { char pib$$_fill_6;N char pib$$_fill_2; /*SPARE UNUSED BYTE */N short int pib$$_fill_9; /*SPARE UNUSED WORD */N unsigned __int64 pib$q_sio_time; /*TIME OF TRANSACTION */N unsigned int pib$l_sio_seqn; /*SEQUENCE NUMBER OF TRAiCNSACTION */N void *pib$l_sio_media; /*TRANSFER MEDIA ADDRESS */N unsigned int pib$l_sio_bcnt; /*TRANSFER BYTE COUNT */N/* END OF I/O TRANSACTION MESSAGE BLOCK */N/* */ } PIB2;N#define PIB$K_EIO_SIZE 24 /*LENGTH OF END OF I/O TRANSACTION */N#define PIB$C_EIO_SIZE 24 /*LENGTH OF END OF I/O TRANSACTION jC*/N/* */N#define PIB$S_PIBDEF3 24 /* Old size name - synonym */ typedef struct _pib3 { char pib$$_fill_7;N char pib$$_fill_3 [3]; /*SPARE UNUSED BYTES */N unsigned __int64 pib$q_eio_time; /*TIME OF TRANSACTION */N unsigned int pib$l_eio_seqn; /*SEQUENCE NUMBER OF TRANSACTION */N unsigned __int64 pib$q_eio_iosb; /*FINAL I/kCO STATUS */N/* END OF I/O REQUEST MESSAGE BLOCK */N/* */ } PIB3;V#define PIB$K_ERQ_SIZE 16 /*LENGTH OF END OF I/O REQUEST TRANSACTION */V#define PIB$C_ERQ_SIZE 16 /*LENGTH OF END OF I/O REQUEST TRANSACTION */N/* */N#define PIB$K_SRQ 0 /*STAR lCT OF I/O REQUEST */N#define PIB$K_SIO 1 /*START OF I/O TRANSACTION */N#define PIB$K_EIO 2 /*END OF I/O TRANSACTION */N#define PIB$K_ERQ 3 /*END OF I/O REQUEST */N#define PIB$K_ARQ 4 /*ABORTED I/O REQUEST */N#define PIB$S_PIBDEF4 16 /* Old size name - synonym */ typedef struct _pib4 { char pib$$_fill_8;N char pib$$_fill_mC4 [3]; /*SPARE UNUSED BYTES */N unsigned __int64 pib$q_erq_time; /*TIME OF TRANSACTION */N unsigned int pib$l_erq_seqn; /*SEQUENCE NUMBER OF TRANSACTION */N/* I/O MESSAGE BLOCK ENTRY TYPE CODES */N/* */ } PIB4;N#define PIB$K_ARQ_SIZE 16 /*LENGTH OF ABORTED I/O TRANSACTION */O#define PIB$C_ARQ_SIZE 16 nC /*LENGTH OF ABORTED I/O TRANSACTION */N/* */N#define PIB$S_PIBDEF5 16 /* Old size name - synonym */ typedef struct _pib5 { char pib$$_fill_10;N char pib$$_fill_11 [3]; /*SPARE UNUSED BYTES */N unsigned __int64 pib$q_arq_time; /*TIME OF TRANSACTION */N unsigned int pib$l_arq_seqn; /*SEQUENCE NUMBER OF TRANSACTION */N/*oC ABORTED I/O REQUEST MESSAGE BLOCK */N/* */ } PIB5; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PIBDEF_LOADED */ wwpC[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 20qC24 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software,rC Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */H/* Source: 18-JUN-1997 14:21:06 $1$DGA8345:[LIB_H.SRC]PIPPDDEF.SDL;1 *//***************************** sC***************************************************************************************************//*** MODULE $PIPPDDEF ***/#ifndef __PIPPDDEF_LOADED#define __PIPPDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size tC*/[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union vauCriant_union#endif#endif #define PIPPD$C_OK 0#define PIPPD$C_VCC 1#define PIPPD$C_INVBN 2#define PIPPD$C_BLV 3#define PIPPD$C_ACCV 4#define PIPPD$C_NP 5#define PIPPD$C_PSV 6#define PIPPD$C_URP 7#define PIPPD$C_INVDP 8#define PIPPD$C_OSEQ 9#define PIPPD$C_DG 1#define PIPPD$C_MSG 2#define PIPPD$C_CNF 3#define PIPPD$C_IDREQ 5#define PIPPD$C_RST 6#define PIPPD$C_STRT 7#define PIPPD$C_DATREQ0 8#define PIPPD$C_DATREQ1 9#define PIPPD$C_DATREQ2 10#defvCine PIPPD$C_ID 11#define PIPPD$C_LB 13#define PIPPD$C_SNTDAT 16#define PIPPD$C_RETDAT 17#define PIPPD$C_DGREC 33#define PIPPD$C_MSGREC 34#define PIPPD$C_CNFREC 35#define PIPPD$C_IDREC 43#define PIPPD$C_DATREC 49#define PIPPD$M_OPCODE 0x1F#define PIPPD$M_LP 0x100#define PIPPD$M_NS 0xE00#define PIPPD$M_M 0x7000#define PIPPD$M_DATA 0x10#define PIPPD$M_NR 0xE00#define PIPPD$C_P0 1#define PIPPD$C_P1 2#define PIPPD$M_RP 0x600#define PIPPD$M_SP 0x3000#define PIwCPPD$M_FR 0x8000#define PIPPD$M_DSA 0x8000#define PIPPD$M_RSP 0x1#define PIPPD$M_DISP 0x2#define PIPPD$M_VC 0x4#define PIPPD$M_Q 0x18#define PIPPD$C_TEXT1 24#define PIPPD$C_LENGTH 26#define PIPPD$C_START 0#define PIPPD$C_STACK 1#define PIPPD$C_ACK 2#define PIPPD$C_SCS_DG 3#define PIPPD$C_SCS_MSG 4#define PIPPD$C_ELOG 5#define PIPPD$C_HOSTSHUT 6#define PIPPD$C_FU_DG 7#define PIPPD$C_CACHECLR 32768#define PIPPD$C_CKTCLSD 32769#define PIPPD$C_CNF_LEN 8#definxCe PIPPD$C_CNFREC_LEN 8#define PIPPD$C_DATREC_LEN 8#define PIPPD$C_IDREQ_LEN 8#define PIPPD$C_RST_LEN 8#define PIPPD$M_MAINT 0x1#define PIPPD$C_UNINIT 0#define PIPPD$C_DISAB 1#define PIPPD$C_ENAB 2#define PIPPD$M_STATE 0x6#define PIPPD$M_AST 0x700#define PIPPD$M_XRPE 0x800#define PIPPD$M_AARB 0x1000#define PIPPD$M_XNR 0x2000'#define PIPPD$M_MAX_BODY_LEN 0x1FFF0000#define PIPPD$M_CSZ 0xE0000000#define PIPPD$M_NUM_MEMS 0xFF#define PIPPD$M_SMV 0x1000#define PIPPD$yCM_RDP_SUP 0x2000#define PIPPD$M_FSN_SUP 0x4000#define PIPPD$M_SA_SUP 0x8000#define PIPPD$C_ID_LEN 48#define PIPPD$C_IDREC_LEN 48#define PIPPD$C_DATREQ_LEN 28#define PIPPD$C_SNTDAT_LEN 16#define PIPPD$C_RETDAT_LEN 16#define PIPPD$C_XXXDAT_LEN 16#define PIPPD$C_STRT_LEN 12 typedef struct _pippd { void *pippd$ps_flink; void *pippd$ps_blink;$ unsigned short int pippd$w_size; unsigned char pippd$b_type;" unsigned char pippd$b_subtype; void *pippzCd$ps_c710d; unsigned char pippd$b_port;! unsigned char pippd$b_status; __union { __struct {( unsigned pippd$v_opcode : 5;' unsigned pippd$v_fill2 : 3;$ unsigned pippd$v_lp : 1;$ unsigned pippd$v_ns : 3;# unsigned pippd$v_m : 3;' unsigned pippd$v_fill3 : 1;, } pippd$r_opcode_bits_msg_data1; __struct {' unsigned pippd$v_fill4 : 4;& unsigned pippd$v_data {C: 1;' unsigned pippd$v_fill5 : 4;$ unsigned pippd$v_nr : 3;' unsigned pippd$v_fill6 : 4;, } pippd$r_opcode_bits_msg_data2; __struct {' unsigned pippd$v_fill7 : 9;$ unsigned pippd$v_rp : 2;' unsigned pippd$v_fill8 : 1;$ unsigned pippd$v_sp : 2;' unsigned pippd$v_fill9 : 2;% } pippd$r_opcode_bits_id; __struct {) unsigned pippd$v_fill10 : 15;$ |C unsigned pippd$v_fr : 1;& } pippd$r_opcode_bits_rst; __struct {) unsigned pippd$v_fill11 : 15;% unsigned pippd$v_dsa : 1;' } pippd$r_opcode_bits_strt;* unsigned short int pippd$w_opcode;! } pippd$r_opcode_overlay; __union { __struct {% unsigned pippd$v_rsp : 1;& unsigned pippd$v_disp : 1;$ unsigned pippd$v_vc : 1;# unsigned pippd$v_q : 2;) }C unsigned pippd$v_fill_0_ : 3;! } pippd$r_flags_bits;) unsigned short int pippd$w_flags; } pippd$r_flags_overlay;' unsigned short int pippd$w_length1; __union {$ unsigned char pippd$b_text1; __struct {/ unsigned short int pippd$w_length2; __union {, unsigned char pippd$b_text2;1 unsigned short int pippd$w_mtype;& } pippd$r_pippd_text2;# } pippd$r_pipp ~Cd_dg_msg; __struct {, unsigned __int64 pippd$q_xct_id; __union { __struct {3 unsigned int pippd$l_rport_typ;3 unsigned int pippd$l_rport_rev;3 unsigned int pippd$l_rport_fcn;5 unsigned char pippd$b_reset_port; __union {# __struct {7 unsigned pippd$v_maint : 1;7 C unsigned pippd$v_state : 2;9 unsigned pippd$v_fill_1_ : 5;7 } pippd$r_rport_state_bits;5 char pippd$b_rport_state [3];6 } pippd$r_rport_state_overlay; __union {# __struct {8 unsigned pippd$v_fill12 : 8;5 unsigned pippd$v_ast : 3;6 unsigned pippd$v_xrpe : 1;6 C unsigned pippd$v_aarb : 1;5 unsigned pippd$v_xnr : 1;8 unsigned pippd$v_fill13 : 2;? unsigned pippd$v_max_body_len : 13;5 unsigned pippd$v_csz : 3;9 } pippd$r_port_fcn_ext1_bits;; unsigned int pippd$l_port_fcn_ext1;8 } pippd$r_port_fcn_ext1_overlay; __union {# C __struct {: unsigned pippd$v_num_mems : 8;8 unsigned pippd$v_fill14 : 4;5 unsigned pippd$v_smv : 1;9 unsigned pippd$v_rdp_sup : 1;9 unsigned pippd$v_fsn_sup : 1;8 unsigned pippd$v_sa_sup : 1;9 } pippd$r_port_fcn_ext2_bits;; unsigned int pippd$l_port_fcn_ext2;8 C } pippd$r_port_fcn_ext2_overlay;5 unsigned __int64 pippd$q_sub_map;7 unsigned char pippd$b_unusedid [8];' } pippd$r_pippd_id; __struct {1 unsigned int pippd$l_xct_len; __union {# __struct {: unsigned int pippd$l_snd_name;: unsigned int pippd$l_snd_boff;4 C } pippd$r_snd_buff_bits;: unsigned __int64 pippd$q_snd_buff;3 } pippd$r_snd_buff_overlay; __union {# __struct {: unsigned int pippd$l_rec_name;: unsigned int pippd$l_rec_boff;4 } pippd$r_rec_buff_bits;: unsigned __int64 pippd$q_rec_buff;3 } pippd$r_rec_buff_overlay;+C } pippd$r_pippd_datreq; __struct {2 unsigned __int64 pippd$q_buff;/ unsigned char pippd$b_data;+ } pippd$r_pippd_xxxdat; __struct {* void *pippd$l_st_addr;) } pippd$r_pippd_strt;/ } pippd$r_pippd_xct_id_overlay;# } pippd$r_pippd_xct_id; } pippd$r_pippd_text1; } PIPPD; #if !defined(__VAXC)Z#defCine pippd$v_opcode pippd$r_opcode_overlay.pippd$r_opcode_bits_msg_data1.pippd$v_opcodeR#define pippd$v_lp pippd$r_opcode_overlay.pippd$r_opcode_bits_msg_data1.pippd$v_lpR#define pippd$v_ns pippd$r_opcode_overlay.pippd$r_opcode_bits_msg_data1.pippd$v_nsP#define pippd$v_m pippd$r_opcode_overlay.pippd$r_opcode_bits_msg_data1.pippd$v_mV#define pippd$v_data pippd$r_opcode_overlay.pippd$r_opcode_bits_msg_data2.pippd$v_dataR#define pippd$v_nr pippd$r_opcode_overlay.pippd$r_opcode_bits_msg_data2.pippd$v_CnrK#define pippd$v_rp pippd$r_opcode_overlay.pippd$r_opcode_bits_id.pippd$v_rpK#define pippd$v_sp pippd$r_opcode_overlay.pippd$r_opcode_bits_id.pippd$v_spL#define pippd$v_fr pippd$r_opcode_overlay.pippd$r_opcode_bits_rst.pippd$v_frO#define pippd$v_dsa pippd$r_opcode_overlay.pippd$r_opcode_bits_strt.pippd$v_dsa<#define pippd$w_opcode pippd$r_opcode_overlay.pippd$w_opcodeH#define pippd$v_rsp pippd$r_flags_overlay.pippd$r_flags_bits.pippd$v_rspJ#define pippd$v_disp pippd$r_flags_overlay.pippd$rC_flags_bits.pippd$v_dispF#define pippd$v_vc pippd$r_flags_overlay.pippd$r_flags_bits.pippd$v_vcD#define pippd$v_q pippd$r_flags_overlay.pippd$r_flags_bits.pippd$v_q9#define pippd$w_flags pippd$r_flags_overlay.pippd$w_flags7#define pippd$b_text1 pippd$r_pippd_text1.pippd$b_text1P#define pippd$w_length2 pippd$r_pippd_text1.pippd$r_pippd_dg_msg.pippd$w_length2`#define pippd$b_text2 pippd$r_pippd_text1.pippd$r_pippd_dg_msg.pippd$r_pippd_text2.pippd$b_text2`#define pippd$w_mtype pippd$r_pippd_textC1.pippd$r_pippd_dg_msg.pippd$r_pippd_text2.pippd$w_mtypeN#define pippd$q_xct_id pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$q_xct_id#define pippd$l_rport_typ pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$l_rport_typ#define pippd$l_rport_rev pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$l_rport_rev#define pippd$l_rport_fcn pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_Cpippd_id.pippd$l_rport_fcn#define pippd$b_reset_port pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$b_reset_port#define pippd$v_maint pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_rport_state_ov\,erlay.pippd$r_rport_state_bits.pippd$v_maint#define pippd$v_state pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_rport_state_ov\,erlay.pippd$r_rport_state_bitsC.pippd$v_state#define pippd$b_rport_state pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_rport_st\ate_overlay.pippd$b_rport_state#define pippd$v_ast pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_fcn_ext1_ov\,erlay.pippd$r_port_fcn_ext1_bits.pippd$v_ast#define pippd$v_xrpe pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_fcn_ext1_o\.verlay.pCippd$r_port_fcn_ext1_bits.pippd$v_xrpe#define pippd$v_aarb pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_fcn_ext1_o\.verlay.pippd$r_port_fcn_ext1_bits.pippd$v_aarb#define pippd$v_xnr pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_fcn_ext1_ov\,erlay.pippd$r_port_fcn_ext1_bits.pippd$v_xnr#define pippd$v_max_body_len pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippdC$r_pippd_id.pippd$r_port_fc\>n_ext1_overlay.pippd$r_port_fcn_ext1_bits.pippd$v_max_body_len#define pippd$v_csz pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_fcn_ext1_ov\,erlay.pippd$r_port_fcn_ext1_bits.pippd$v_csz#define pippd$l_port_fcn_ext1 pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_f\%cn_ext1_overlay.pippd$l_port_fcn_ext1#define pippd$v_num_mems pippd$r_pippd_text1.pippd$r_pippdC_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_fcn_ex\6t2_overlay.pippd$r_port_fcn_ext2_bits.pippd$v_num_mems#define pippd$v_smv pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_fcn_ext2_ov\,erlay.pippd$r_port_fcn_ext2_bits.pippd$v_smv#define pippd$v_rdp_sup pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_fcn_ext\42_overlay.pippd$r_port_fcn_ext2_bits.pippd$v_rdp_sup#definCe pippd$v_fsn_sup pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_fcn_ext\42_overlay.pippd$r_port_fcn_ext2_bits.pippd$v_fsn_sup#define pippd$v_sa_sup pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_fcn_ext2\2_overlay.pippd$r_port_fcn_ext2_bits.pippd$v_sa_sup#define pippd$l_port_fcn_ext2 pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$r_port_f\%cn_eCxt2_overlay.pippd$l_port_fcn_ext2~#define pippd$q_sub_map pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$q_sub_map#define pippd$b_unusedid pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_id.pippd$b_unusedid#define pippd$l_xct_len pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_datreq.pippd$l_xct_len#define pippd$l_snd_name pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_Cxct_id_overlay.pippd$r_pippd_datreq.pippd$r_snd_buf\0f_overlay.pippd$r_snd_buff_bits.pippd$l_snd_name#define pippd$l_snd_boff pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_datreq.pippd$r_snd_buf\0f_overlay.pippd$r_snd_buff_bits.pippd$l_snd_boff#define pippd$q_snd_buff pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_datreq.pippd$r_snd_buf\f_overlay.pippd$q_snd_buff#define pippd$l_rec_name pippd$r_pippd_text1.pippd$r_pipCpd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_datreq.pippd$r_rec_buf\0f_overlay.pippd$r_rec_buff_bits.pippd$l_rec_name#define pippd$l_rec_boff pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_datreq.pippd$r_rec_buf\0f_overlay.pippd$r_rec_buff_bits.pippd$l_rec_boff#define pippd$q_rec_buff pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_datreq.pippd$r_rec_buf\f_overlay.pippd$q_rec_buff|#define pippd$q_buff pippd$r_pip Cpd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_xxxdat.pippd$q_buff|#define pippd$b_data pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_xxxdat.pippd$b_data#define pippd$l_st_addr pippd$r_pippd_text1.pippd$r_pippd_xct_id.pippd$r_pippd_xct_id_overlay.pippd$r_pippd_strt.pippd$l_st_addr"#endif /* #if !defined(__VAXC) */ #define DSSI$C_STS_GOOD 97#define DSSI$C_MAX_PKT 4114#define DSSI$C_NUM_PAGES 8#define DSSI$C_RETRY_IMMED 8C#define DSSI$C_RETRY_DELAY 512#define DSSI$C_TIMER 100000#define DSSI$C_CMD_DSSI 224#define DSSI$M_MBZ 0xF#define DSSI$M_REQ_ACK 0xF0 typedef struct _dssi_cmd { unsigned char dssi$b_opcode; __union { __struct {$ unsigned dssi$v_mbz : 4;( unsigned dssi$v_req_ack : 4; } dssi$r_flags_bits;# unsigned char dssi$b_flags; } dssi$r_flags_overlay;" unsigned char dssi$b_dst_port;" unsigned char dssi$b_src_port;C# unsigned short int dssi$w_size; } DSSI_CMD; #if !defined(__VAXC)D#define dssi$v_mbz dssi$r_flags_overlay.dssi$r_flags_bits.dssi$v_mbzL#define dssi$v_req_ack dssi$r_flags_overlay.dssi$r_flags_bits.dssi$v_req_ack6#define dssi$b_flags dssi$r_flags_overlay.dssi$b_flags"#endif /* #if !defined(__VAXC) */ #define DSSI$C_DG 1#define DSSI$C_MSG 2#define DSSI$C_CNF 3#define DSSI$C_IDREQ 5#define DSSI$C_RST 6#define DSSI$C_STRT 7#define DSSI$C_DATREQ0 8#define DSSI$C_DCATREQ1 9#define DSSI$C_DATREQ2 10#define DSSI$C_ID 11#define DSSI$C_LB 13#define DSSI$C_SNTDAT 16#define DSSI$C_RETDAT 17#define DSSI$M_OPCODE 0x1F#define DSSI$M_LP 0x100#define DSSI$M_NS 0xE00#define DSSI$M_M 0x7000#define DSSI$M_DATA 0x10#define DSSI$M_NR 0xE00#define DSSI$C_P0 1#define DSSI$C_P1 2#define DSSI$M_RP 0x600#define DSSI$M_SP 0x3000#define DSSI$M_FR 0x8000#define DSSI$M_DSA 0x8000#define DSSI$C_START 0#define DSSI$C_STACK 1#define DSSI$C_ACCK 2#define DSSI$C_SCS_DG 3#define DSSI$C_SCS_MSG 4#define DSSI$C_ELOG 5#define DSSI$C_HOSTSHUT 6#define DSSI$C_FU_DG 7#define DSSI$C_CNF_LEN 10#define DSSI$C_CNFREC_LEN 10#define DSSI$C_DATREC_LEN 10#define DSSI$C_IDREQ_LEN 10#define DSSI$C_RST_LEN 10#define DSSI$M_MAINT 0x1#define DSSI$C_UNINIT 0#define DSSI$C_DISAB 1#define DSSI$C_ENAB 2#define DSSI$M_STATE 0x6#define DSSI$M_AST 0x700#define DSSI$M_XRPE 0x800#define DSSI$M_AARB 0x1000#define DSSI$M_XNRC 0x2000&#define DSSI$M_MAX_BODY_LEN 0x1FFF0000#define DSSI$M_CSZ 0xE0000000#define DSSI$M_NUM_MEMS 0xFF#define DSSI$M_SMV 0x1000#define DSSI$M_RDP_SUP 0x2000#define DSSI$M_FSN_SUP 0x4000#define DSSI$M_SA_SUP 0x8000#define DSSI$C_ID_LEN 50#define DSSI$C_IDREC_LEN 50#define DSSI$C_DATREQ_LEN 30#define DSSI$C_SNTDAT_LEN 18#define DSSI$C_RETDAT_LEN 18#define DSSI$C_XXXDAT_LEN 18#define DSSI$C_STRT_LEN 14 typedef struct _dssi_dat { __union { __struct {C' unsigned dssi$v_opcode : 5;& unsigned dssi$v_fill2 : 3;# unsigned dssi$v_lp : 1;# unsigned dssi$v_ns : 3;" unsigned dssi$v_m : 3;& unsigned dssi$v_fill3 : 1;+ } dssi$r_opcode_bits_msg_data1; __struct {& unsigned dssi$v_fill4 : 4;% unsigned dssi$v_data : 1;& unsigned dssi$v_fill5 : 4;# unsigned dssi$v_nr : 3;& unsigned dssi$v_fill6 : 4;+ C } dssi$r_opcode_bits_msg_data2; __struct {& unsigned dssi$v_fill7 : 9;# unsigned dssi$v_rp : 2;& unsigned dssi$v_fill8 : 1;# unsigned dssi$v_sp : 2;& unsigned dssi$v_fill9 : 2;$ } dssi$r_opcode_bits_id; __struct {( unsigned dssi$v_fill10 : 15;# unsigned dssi$v_fr : 1;% } dssi$r_opcode_bits_rst; __struct {( unsigned dssi$v_fill11 : 15;$ C unsigned dssi$v_dsa : 1;& } dssi$r_opcode_bits_strt;) unsigned short int dssi$w_opcode; } dssi$r_opcode_overlay; __union { __struct {& unsigned char dssi$b_text; } dssi$r_dssi_text; __struct {, unsigned short int dssi$w_mtype;! } dssi$r_dssi_dg_msg; __struct {+ unsigned __int64 dssi$q_xct_id; __union { __struct {2 C unsigned int dssi$l_rport_typ;2 unsigned int dssi$l_rport_rev;2 unsigned int dssi$l_rport_fcn;4 unsigned char dssi$b_reset_port; __union {# __struct {6 unsigned dssi$v_maint : 1;6 unsigned dssi$v_state : 2;8 unsigned dssi$v_fill_2_ : 5;6 } dssi$r_rport_state_bits;4 C char dssi$b_rport_state [3];5 } dssi$r_rport_state_overlay; __union {# __struct {7 unsigned dssi$v_fill12 : 8;4 unsigned dssi$v_ast : 3;5 unsigned dssi$v_xrpe : 1;5 unsigned dssi$v_aarb : 1;4 unsigned dssi$v_xnr : 1;7 unsigned dssi$v_fill13 : 2;> C unsigned dssi$v_max_body_len : 13;4 unsigned dssi$v_csz : 3;8 } dssi$r_port_fcn_ext1_bits;: unsigned int dssi$l_port_fcn_ext1;7 } dssi$r_port_fcn_ext1_overlay; __union {# __struct {9 unsigned dssi$v_num_mems : 8;7 unsigned dssi$v_fill14 : 4;4 Cunsigned dssi$v_smv : 1;8 unsigned dssi$v_rdp_sup : 1;8 unsigned dssi$v_fsn_sup : 1;7 unsigned dssi$v_sa_sup : 1;8 } dssi$r_port_fcn_ext2_bits;: unsigned int dssi$l_port_fcn_ext2;7 } dssi$r_port_fcn_ext2_overlay;4 unsigned __int64 dssi$q_sub_map;6 unsigned char dssi$b_unusedid [8];% C} dssi$r_dssi_id; __struct {0 unsigned int dssi$l_xct_len; __union {# __struct {9 unsigned int dssi$l_snd_name;9 unsigned int dssi$l_snd_boff;3 } dssi$r_snd_buff_bits;9 unsigned __int64 dssi$q_snd_buff;2 } dssi$r_snd_buff_overlay; __union {# C __struct {9 unsigned int dssi$l_rec_name;9 unsigned int dssi$l_rec_boff;3 } dssi$r_rec_buff_bits;9 unsigned __int64 dssi$q_rec_buff;2 } dssi$r_rec_buff_overlay;) } dssi$r_dssi_datreq; __struct {1 unsigned __int64 dssi$q_buff;. unsigned char dssi$b_data;) } dssi C$r_dssi_xxxdat; __struct {) void *dssi$l_st_addr;' } dssi$r_dssi_strt;- } dssi$r_dssi_xct_id_overlay;! } dssi$r_dssi_xct_id; } dssi$r_dssi_data; } DSSI_DAT; #if !defined(__VAXC)V#define dssi$v_opcode dssi$r_opcode_overlay.dssi$r_opcode_bits_msg_data1.dssi$v_opcodeN#define dssi$v_lp dssi$r_opcode_overlay.dssi$r_opcode_bits_msg_data1.dssi$v_lpN#define dssi$v_ns dssi$r_opcode_overlay.dssi$rC_opcode_bits_msg_data1.dssi$v_nsL#define dssi$v_m dssi$r_opcode_overlay.dssi$r_opcode_bits_msg_data1.dssi$v_mR#define dssi$v_data dssi$r_opcode_overlay.dssi$r_opcode_bits_msg_data2.dssi$v_dataN#define dssi$v_nr dssi$r_opcode_overlay.dssi$r_opcode_bits_msg_data2.dssi$v_nrG#define dssi$v_rp dssi$r_opcode_overlay.dssi$r_opcode_bits_id.dssi$v_rpG#define dssi$v_sp dssi$r_opcode_overlay.dssi$r_opcode_bits_id.dssi$v_spH#define dssi$v_fr dssi$r_opcode_overlay.dssi$r_opcode_bits_rst.dssi$v_frK#define Cdssi$v_dsa dssi$r_opcode_overlay.dssi$r_opcode_bits_strt.dssi$v_dsa9#define dssi$w_opcode dssi$r_opcode_overlay.dssi$w_opcodeA#define dssi$b_text dssi$r_dssi_data.dssi$r_dssi_text.dssi$b_textE#define dssi$w_mtype dssi$r_dssi_data.dssi$r_dssi_dg_msg.dssi$w_mtypeG#define dssi$q_xct_id dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$q_xct_idw#define dssi$l_rport_typ dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$l_rport_typw#define dssi$l_rport_rev dssi$r_dssi_datCa.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$l_rport_revw#define dssi$l_rport_fcn dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$l_rport_fcny#define dssi$b_reset_port dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$b_reset_port#define dssi$v_maint dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_rport_state_overlay.dssi$\r_rport_state_bits.dssi$v_maint#define dsCsi$v_state dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_rport_state_overlay.dssi$\r_rport_state_bits.dssi$v_state#define dssi$b_rport_state dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_rport_state_overlay\.dssi$b_rport_state#define dssi$v_ast dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext1_overlay.dssi$\r_port_fcn_ext1_bits.dssi$v_ast#define dssi$v_xrpe dssiC$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext1_overlay.dssi\!$r_port_fcn_ext1_bits.dssi$v_xrpe#define dssi$v_aarb dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext1_overlay.dssi\!$r_port_fcn_ext1_bits.dssi$v_aarb#define dssi$v_xnr dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext1_overlay.dssi$\r_port_fcn_ext1_bits.dssi$v_xnr#define dssi$v_max_bodCy_len dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext1_over\1lay.dssi$r_port_fcn_ext1_bits.dssi$v_max_body_len#define dssi$v_csz dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext1_overlay.dssi$\r_port_fcn_ext1_bits.dssi$v_csz#define dssi$l_port_fcn_ext1 dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext1_ove\rlay.dssi$l_port_fcn_ext1#define dssiC$v_num_mems dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext2_overlay.\)dssi$r_port_fcn_ext2_bits.dssi$v_num_mems#define dssi$v_smv dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext2_overlay.dssi$\r_port_fcn_ext2_bits.dssi$v_smv#define dssi$v_rdp_sup dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext2_overlay.d\'ssi$r_port_fcn_ext2_bits.dssi$v_rdp_suCp#define dssi$v_fsn_sup dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext2_overlay.d\'ssi$r_port_fcn_ext2_bits.dssi$v_fsn_sup#define dssi$v_sa_sup dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext2_overlay.ds\%si$r_port_fcn_ext2_bits.dssi$v_sa_sup#define dssi$l_port_fcn_ext2 dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$r_port_fcn_ext2_ove\rlay.dssi$l_port_fCcn_ext2s#define dssi$q_sub_map dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$q_sub_mapu#define dssi$b_unusedid dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_id.dssi$b_unusedidw#define dssi$l_xct_len dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_datreq.dssi$l_xct_len#define dssi$l_snd_name dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_datreq.dssi$r_snd_buff_overlay.d\#ssCi$r_snd_buff_bits.dssi$l_snd_name#define dssi$l_snd_boff dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_datreq.dssi$r_snd_buff_overlay.d\#ssi$r_snd_buff_bits.dssi$l_snd_boff#define dssi$q_snd_buff dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_datreq.dssi$r_snd_buff_overlay.d\ssi$q_snd_buff#define dssi$l_rec_name dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_datreq.dssi$r_rec_buff_overlay.d\#ssi$r_rec_buffC_bits.dssi$l_rec_name#define dssi$l_rec_boff dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_datreq.dssi$r_rec_buff_overlay.d\#ssi$r_rec_buff_bits.dssi$l_rec_boff#define dssi$q_rec_buff dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_datreq.dssi$r_rec_buff_overlay.d\ssi$q_rec_buffq#define dssi$q_buff dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_xxxdat.dssi$q_buffq#define dssi$b_data dssi$r_dssi_data.dssi$r_ Cdssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_xxxdat.dssi$b_datau#define dssi$l_st_addr dssi$r_dssi_data.dssi$r_dssi_xct_id.dssi$r_dssi_xct_id_overlay.dssi$r_dssi_strt.dssi$l_st_addr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pra Cgma __standard #endif /* __PIPPDDEF_LOADED */ ww@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permissiCon of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, InCc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 24-OCT-1995 10:19:15 $1$DGA834 C5:[LIB_H.SRC]PKBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PKBDEF ***/#ifndef __PKBDEF_LOADED#define __PKBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __saCve /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXCC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* PKBDEF */N/*- */ #define PKB$K_LENGTH 80#define PKB$C_LENGTH 80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomemb Cer_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pkb {N/* The fork block */#pragma __nomember_alignmentN void *pkb$ps_fqfl; /* Fork queue forward link */N void *pkb$ps_fqbl; /* Fork queue backward link */N unsigned short int pkb$w_size; /* Size of PKB in bytes */P unsigned char pkb$b_type; /* Structure type (uCse DYN$C_FKB here */N/* and use SIZE field to see if PKB). */N unsigned char pkb$b_flck; /* Fork lock number */N void (*pkb$ps_fpc)(); /* Fork PC */N __int64 pkb$q_fr3; /* Fork R3 */N __int64 pkb$q_fr4; /* Fork R4 */N/* The LKSB or IOSB */N Cunsigned short int pkb$w_status; /* Status */N unsigned short int pkb$w_count; /* Unused (if IOSB, byte count) */O unsigned int pkb$l_lockid; /* Lock ID (if IOSB, DEVDEPEND bits) */N/* The resource descriptor */ __union {N int pkb$l_resnam_d; /* Descriptor */ __struct {N unsigned short int pkb$w_resnam_length; /* Length C */N unsigned char pkb$b_resnam_type; /* Type */N unsigned char pkb$b_resnam_subtype; /* Subtype */ } pkb$r_fill_1_; } pkb$r_fill_0_;N void *pkb$ps_resnam_p; /* Pointer to resource */N/* The resource name */ __union {N char pkb$t_resnam [32]; /* Resource name text */ __struct {N C char pkb$t_resnam_text; /* First character of text */N char pkb$t_filler [31]; /* Pad */ } pkb$r_fill_3_; } pkb$r_fill_2_; } PKB; #if !defined(__VAXC)3#define pkb$l_resnam_d pkb$r_fill_0_.pkb$l_resnam_dK#define pkb$w_resnam_length pkb$r_fill_0_.pkb$r_fill_1_.pkb$w_resnam_lengthG#define pkb$b_resnam_type pkb$r_fill_0_.pkb$r_fill_1_.pkb$b_resnam_typeM#define pkb$b_resnam_subtype pkb$r_fill_0_.pkb$rC_fill_1_.pkb$b_resnam_subtype/#define pkb$t_resnam pkb$r_fill_2_.pkb$t_resnamG#define pkb$t_resnam_text pkb$r_fill_2_.pkb$r_fill_3_.pkb$t_resnam_text"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PKBD CEF_LOADED */ ww`c[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. C **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024C Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */G/* Source: 20-NOV-2006 15:52:45 $1$DGA8345:[LIB_H.SRC]PKTADEF.SDL;1 *//***** C***************************************************************************************************************************//*** MODULE $PKTADEF ***/#ifndef __PKTADEF_LOADED#define __PKTADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defineCd required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#elseC#define __union variant_union#endif#endif #define PKTA$M_TM_ACTIVE 0x1 #define PKTA$M_AVOID_PREEMPT 0x2#define PKTA$M_IMF_PENDING 0x4 #define PKTA$M_EVENT_NO_FLAG 0x1  9#ifdef __cplusplus /* Define structure prototypes */ struct _ktb; struct _phd; struct _fred; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_a Clignment#endiftypedef struct _pkta {#pragma __nomember_alignment __union {N unsigned __int64 pkta$q_tm_flags; /* Threads manager flags */ __struct {N unsigned pkta$v_tm_active : 1; /* Threads manager is active */N unsigned pkta$v_avoid_preempt : 1; /* Try to avoid preemption */N unsigned pkta$v_imf_pending : 1; /* IMSEM-free upcall is coming */( unsigned pkta$v_fill_6_ : 5; } pkta$r_fill_1_; C } pkta$r_fill_0_; __union {N unsigned __int64 pkta$q_persona_handle; /* Security persona handle */ __struct {N unsigned int pkta$l_persona_id; /* */N unsigned int pkta$l_security_reserved; /* */ } pkta$r_fill_3_; } pkta$r_fill_2_;N/* */S unsigned __int64 pkta$q_ieee_fp_control; /* IEEE exception Cs control register */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void (*pkta$q_ast_address)(); /* User AST routine */#else% unsigned __int64 pkta$q_ast_address;#endifN unsigned __int64 pkta$q_iosa; /* start of embedded iosa */N unsigned __int64 pkta$q_iosb; /* start of embedded iosa C */N unsigned int pkta$l_iosa_status; /* iosa$l_status */ } pkta$r_iosa1; __union {N unsigned __int64 pkta$q_ast_parameter; /* User AST parameter */N unsigned __int64 pkta$q_iosa_count; /* IOSA$Q_COUNT */ } pkta$r_iosa_2; __union {O unsigned __int64 pkta$q_ast_thread_id; /* Target user mode thread ID */N unsigned __int64 pkta$q_iosa_context_q; /* IOSA$Q_CONTEXT_Q */ } pkta C$r_iosa_3; __union {N unsigned __int64 pkta$q_postef; /* Posted event flags */N unsigned __int64 pkta$q_iosa_context_id; /* IOSA$Q_CONTEXT_ID */ } pkta$r_iosa_4; __union {b unsigned __int64 pkta$q_thread_events; /* Other events to be reported to thread manager */ __struct {N unsigned pkta$v_event_no_flag : 1; /* The no-flag event */( unsigned pkta$v_fill_7_ : 7; } pkta$r_fill_5_;C } pkta$r_fill_4_;b unsigned __int64 pkta$q_sw_fen_u; /* Don't use for other flags because of synchronization */h unsigned __int64 pkta$q_fp_restore_area; /* Pointer to register save area to restore FP regs from */O/* It should be ponter_quad (FLOAT), but I don't think SDL understands that. */r unsigned __int64 pkta$q_rpcc_64_context; /* Context to allow returning a 64-bit time value with SYS$RPCC_64 */' unsigned __int64 pkta$q_uw_spare_1;' unsigned __int64 pkta$q_uw_s Cpare_2;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _ktb *pkta$q_ktb; /* Address of KTB for this thread */#else unsigned __int64 pkta$q_ktb;#endifN unsigned int pkta$l_pid; /* PID for this thread */N unsigned int pkta$l_epid; /* EPID for this thread */R#ifdef __INITIAL_POINTER_SIZE C /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _phd *pkta$q_phd; /* Address of PHD */#else unsigned __int64 pkta$q_phd;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *pkta$q_kstack_base; /* Kstack base add Cress */#else% unsigned __int64 pkta$q_kstack_base;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *pkta$q_stack [4]; /* STACK pointer array */#else# unsigned __int64 pkta$q_stack [4];#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __ Clong /* And set ptr size default to 64-bit pointers */N void *pkta$q_stacklim [4]; /* STACK limit pointer */#else& unsigned __int64 pkta$q_stacklim [4];#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _fred *pkta$q_fred; /* Address of FRED */#else unsigned __int64 pkta$q_fred;#endifR#ifdef _ C_INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *pkta$q_regstack [4]; /* Register stack pointer array */#else& unsigned __int64 pkta$q_regstack [4];#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *pkta$q_regstackl Cim [4]; /* Register stack limit array */#else) unsigned __int64 pkta$q_regstacklim [4];#endifN unsigned __int64 pkta$q_stack_peak [4]; /* Memory stack peak array */N unsigned __int64 pkta$q_regstack_peak [4]; /* Register stack peak array */ } PKTA; #if !defined(__VAXC)6#define pkta$q_tm_flags pkta$r_fill_0_.pkta$q_tm_flagsG#define pkta$v_tm_active pkta$r_fill_0_.pkta$r_fill_1_.pkta$v_tm_activeO#define pkta$v_avoid_preempt pkta$r_fill_0_.pkta$r_fill_1_.pkt Ca$v_avoid_preemptK#define pkta$v_imf_pending pkta$r_fill_0_.pkta$r_fill_1_.pkta$v_imf_pendingB#define pkta$q_persona_handle pkta$r_fill_2_.pkta$q_persona_handleI#define pkta$l_persona_id pkta$r_fill_2_.pkta$r_fill_3_.pkta$l_persona_idW#define pkta$l_security_reserved pkta$r_fill_2_.pkta$r_fill_3_.pkta$l_security_reserved:#define pkta$q_ast_address pkta$r_iosa1.pkta$q_ast_address,#define pkta$q_iosa pkta$r_iosa1.pkta$q_iosa,#define pkta$q_iosb pkta$r_iosa1.pkta$q_iosb:#define pkta$l_iosa_st Catus pkta$r_iosa1.pkta$l_iosa_status?#define pkta$q_ast_parameter pkta$r_iosa_2.pkta$q_ast_parameter9#define pkta$q_iosa_count pkta$r_iosa_2.pkta$q_iosa_count?#define pkta$q_ast_thread_id pkta$r_iosa_3.pkta$q_ast_thread_idA#define pkta$q_iosa_context_q pkta$r_iosa_3.pkta$q_iosa_context_q1#define pkta$q_postef pkta$r_iosa_4.pkta$q_postefC#define pkta$q_iosa_context_id pkta$r_iosa_4.pkta$q_iosa_context_id@#define pkta$q_thread_events pkta$r_fill_4_.pkta$q_thread_eventsO#define pkta$v_event C_no_flag pkta$r_fill_4_.pkta$r_fill_5_.pkta$v_event_no_flag"#endif /* #if !defined(__VAXC) */ N#define PKTA$S_URUW 104 /* Length URUW section */N#define PKTA$S_UREW 232 /* Length UREW section */N#define PKTA$C_LENGTH 336 /* Length PKTA */N#define PKTA$K_LENGTH 336 /* Length PKTA */N#define PKTA$S_PKTADEF 336 /* Old size name - synonym */ $C#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PKTADEF_LOADED */ ww[UM/***************************************************************************/M/** **C/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC.C CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************************************C****************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */E/* Source: 06-FEB-2002 10:23:35 $1$DGA8345:[LIB_H.SRC]PLDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PLDEF ***/#ifndef __PLDEF_LOADED#define __PLDEF_LOADED 1 C G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define C__optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Definitions for IPF Privilege Levels C */N/* */N#define PL$C_KERNEL 0 /* Kernel */N#define PL$C_EXEC 1 /* Executive */N#define PL$C_SUPER 2 /* Supervisor */N#define PL$C_USER 3 /* User */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptrC size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PLDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensedC by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VCMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************** C*****************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */I/* Source: 09-JUN-1993 15:42:57 $1$DGA8345:[LIB_H.SRC]RMSFILSTR.SDL;1 *//********************************************************************************************************************************//*** MODULE $PLGDEF ***/#ifndef __PLGDEF_LOADED#define __PLGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma C__member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...C#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define PLG$M_NOEXTEND 0x1N#define PLG$C_VER_NO 1 /* current prolog version number */N#define PLG$C_VER_IDX 2 /* new plg for indexed files */a#define PLG$C_VER_3 3 /* new plg f Cor compression, space reclamation (plg 3) */#define PLG$K_BLN 122#define PLG$C_BLN 122N#define PLG$S_PLGDEF 122 /* Old size name - synonym */ typedef struct _plg {R char plg$$_fill_1 [11]; /* leave space for indexed file things */N unsigned char plg$b_dbktsiz; /* data bucket size */N int plg$$_fill_2; /* filler */ __union {N unsigned char plg$b_flags; /* C flag bits */ __struct {N unsigned plg$v_noextend : 1; /* no extend allowed (rel) */' unsigned plg$v_fill_2_ : 7; } plg$r_fill_1_; } plg$r_fill_0_;N char plg$$_fill_3 [85]; /* space filler */N unsigned char plg$b_avbn; /* vbn of first area descriptor */N unsigned char plg$b_amax; /* maximum number of areas */N unsigned short int plg$wC_dvbn; /* first data bucket vbn */N short int plg$$_fill_4; /* spare */N unsigned int plg$l_mrn; /* maximum record number (rel) */N unsigned int plg$l_eof; /* eof vbn (rel) */N unsigned short int plg$w_ver_no; /* version number */N unsigned short int plg$w_gbc; /* default global buffer count */U unsigned short int plg$w_colvbn; /* VBN where cCollate tables begin (if any) */ } PLG; #if !defined(__VAXC)-#define plg$b_flags plg$r_fill_0_.plg$b_flagsA#define plg$v_noextend plg$r_fill_0_.plg$r_fill_1_.plg$v_noextend"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma C__standard #endif /* __PLGDEF_LOADED */ wwM[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of CHPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. C **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */F/* Source: 17-JUL-2023 07:13:42 $1$DGA8345:[LIB C_H.SRC]PLVDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PLVDEF ***/#ifndef __PLVDEF_LOADED#define __PLVDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /C* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#d Cefine __union union#else#define __union variant_union#endif#endif N/*+ */N/* PRIVILEGED LIBRARY VECTOR DEFINITION */N/*- */N/* */N/* ********* NOTE WELL ********* */N/* C */N/* The following masks must EXACTLY EQUAL the SSFLAG masks defined in */Q/* [LIB]VECTORS.SDL. The system service dispatcher assumes, for example, that */P/* PLV$M_WAIT_CALLERS_MODE equals SSFLAG_K_WCM. Ensure that any additions to */N/* the PLVFLG structure are reflected in [LIB]VECTORS.SDL (and vice versa). */N/* */P/* Also note that although PLVFLG is definedC to be a quadword, the dispatcher */N/* treats the array of kernel flags and exec flags as an array of LONGWORD */N/* flags. Another interesting point is that the flags value for regular */N/* system services is limited to a byte. */N/* */N/* ********* END NOTE WELL ********* */N/* C */##define PLV$M_WAIT_CALLERS_MODE 0x1(#define PLV$M_WAIT_CALLERS_NO_REEXEC 0x2#define PLV$M_CLRREG 0x4#define PLV$M_RETURN_ANY 0x8#define PLV$M_WCM_NO_SAVE 0x10#define PLV$M_STACK_ARGS 0x20#define PLV$M_THREAD_SAFE 0x40#define PLV$M_64_BIT_ARGS 0x80 #define PLV$M_CHECK_UPCALL 0x100#define PLV$M_EXCLUSIVE 0x200#define PLV$M_TOLERANT 0x400!#define PLV$M_IMSEM_RELEASE 0x800 #define PLV$M_RESET_ASTEN 0x1000 typedef union _fill_0_ { __int64 plv$q_plvflg; __Cstruct {N unsigned plv$v_wait_callers_mode : 1; /* equals SSFLAG_K_WCM */V unsigned plv$v_wait_callers_no_reexec : 1; /* equals SSFLAG_K_WCM_NO_REEXEC */N unsigned plv$v_clrreg : 1; /* equals SSFLAG_K_CLRREG */N unsigned plv$v_return_any : 1; /* equals SSFLAG_K_RETURN_ANY */N unsigned plv$v_wcm_no_save : 1; /* equals SSFLAG_K_WCM_NO_SAVE */N unsigned plv$v_stack_args : 1; /* equals SSFLAG_K_STACK_ARGS */N C unsigned plv$v_thread_safe : 1; /* equals SSFLAG_K_THREAD_SAFE */N unsigned plv$v_64_bit_args : 1; /* equals SSFLAG_K_64_BIT_ARGS */N unsigned plv$v_check_upcall : 1; /* equals SSFLAG_K_CHECK_UPCALL */N unsigned plv$v_exclusive : 1; /* equals SSFLAG_K_EXCLUSIVE */N unsigned plv$v_tolerant : 1; /* equals SSFLAG_K_TOLERANT */N unsigned plv$v_imsem_release : 1; /* equals SSFLAG_K_IMSEM_RELEASE */N unsigned plv$v_reset_ast Cen : 1; /* equals SSFLAG_K_RESET_ASTEN */# unsigned plv$v_fill_2_ : 3; } plv$r_fill_1_; } FILL_0_; #if !defined(__VAXC)E#define plv$v_wait_callers_mode plv$r_fill_1_.plv$v_wait_callers_modeO#define plv$v_wait_callers_no_reexec plv$r_fill_1_.plv$v_wait_callers_no_reexec/#define plv$v_clrreg plv$r_fill_1_.plv$v_clrreg7#define plv$v_return_any plv$r_fill_1_.plv$v_return_any9#define plv$v_wcm_no_save plv$r_fill_1_.plv$v_wcm_no_save7#define plv$v_stack_args plv$r C_fill_1_.plv$v_stack_args9#define plv$v_thread_safe plv$r_fill_1_.plv$v_thread_safe9#define plv$v_64_bit_args plv$r_fill_1_.plv$v_64_bit_args;#define plv$v_check_upcall plv$r_fill_1_.plv$v_check_upcall5#define plv$v_exclusive plv$r_fill_1_.plv$v_exclusive3#define plv$v_tolerant plv$r_fill_1_.plv$v_tolerant=#define plv$v_imsem_release plv$r_fill_1_.plv$v_imsem_release9#define plv$v_reset_asten plv$r_fill_1_.plv$v_reset_asten"#endif /* #if !defined(__VAXC) */ N#define PLV$C_LENGTH 4C4 /* Size of fixed portion */#define PLV$S_PLVDEF 44  9#ifdef __cplusplus /* Define structure prototypes */struct _symbol_vector_entry; #endif /* #ifdef __cplusplus */ typedef struct _plv {N unsigned int plv$l_type; /*TYPE CODE FOR VECTOR FORMAT */N unsigned int plv$l_version; /*SYSTEM VERSION NUMBER */ __union {N __struct { /* CMOD specific data */O C unsigned int plv$l_kernel_routine_count; /* # of kernel routines */N unsigned int plv$l_exec_routine_count; /* # of exec routines */N void *plv$ps_kernel_routine_list; /* addr of kernel list */N void *plv$ps_exec_routine_list; /* addr of exec list */N int (*plv$ps_kernel_rundown_handler)(); /* kern rundown routine */N int (*plv$ps_exec_rundown_handler)(); /* exec rundown routine */N int (*plv$ps_rms_dCispatcher)(); /* RMS dispatch routine */N int *plv$ps_kernel_routine_flags; /* flags vector */N int *plv$ps_exec_routine_flags; /* flags vector */ } plv$r_cmod_data;N __struct { /* MSG type specific data */Q int plv$l_msgdsp; /* self-rel ptr to message dispatcher */N unsigned int plv$l_msg_entry; /* message dispatcher code */N int plv$ Cl_msg_section; /* self-rel ptr to msg section */ } plv$r_msg_data;N __struct { /* SSI type specific data */ __union {) unsigned int plv$l_flags; __struct {R unsigned plv$v_main_image : 1; /* Closest to system service *// unsigned plv$v_fill_5_ : 7;$ } plv$r_fill_4_; } plv$r_fill_3_;S unsigned int plv$l C_ssi_routine_count; /* Count of SSI symbol vectors */c struct _symbol_vector_entry *plv$ps_vector_address; /* Private symbol vector address */ } plv$r_ssi_data; } plv$r_type_specific; } PLV; #if !defined(__VAXC)a#define plv$l_kernel_routine_count plv$r_type_specific.plv$r_cmod_data.plv$l_kernel_routine_count]#define plv$l_exec_routine_count plv$r_type_specific.plv$r_cmod_data.plv$l_exec_routine_counta#define plv$ps_kernel_routine_list plv$r_type_specCific.plv$r_cmod_data.plv$ps_kernel_routine_list]#define plv$ps_exec_routine_list plv$r_type_specific.plv$r_cmod_data.plv$ps_exec_routine_listg#define plv$ps_kernel_rundown_handler plv$r_type_specific.plv$r_cmod_data.plv$ps_kernel_rundown_handlerc#define plv$ps_exec_rundown_handler plv$r_type_specific.plv$r_cmod_data.plv$ps_exec_rundown_handlerW#define plv$ps_rms_dispatcher plv$r_type_specific.plv$r_cmod_data.plv$ps_rms_dispatcherc#define plv$ps_kernel_routine_flags plv$r_type_specific.plv$r_Ccmod_data.plv$ps_kernel_routine_flags_#define plv$ps_exec_routine_flags plv$r_type_specific.plv$r_cmod_data.plv$ps_exec_routine_flagsD#define plv$l_msgdsp plv$r_type_specific.plv$r_msg_data.plv$l_msgdspJ#define plv$l_msg_entry plv$r_type_specific.plv$r_msg_data.plv$l_msg_entryN#define plv$l_msg_section plv$r_type_specific.plv$r_msg_data.plv$l_msg_sectionP#define plv$l_flags plv$r_type_specific.plv$r_ssi_data.plv$r_fill_3_.plv$l_flagsh#define plv$v_main_image plv$r_type_specific.plv$r_ssi_data. Cplv$r_fill_3_.plv$r_fill_4_.plv$v_main_imageZ#define plv$l_ssi_routine_count plv$r_type_specific.plv$r_ssi_data.plv$l_ssi_routine_countV#define plv$ps_vector_address plv$r_type_specific.plv$r_ssi_data.plv$ps_vector_address"#endif /* #if !defined(__VAXC) */  U#ifdef __INITIAL_POINTER_SIZE U#pragma __required_pointer_size __save C U#pragma __required_pointer_size __long Utypedef PLV * PLV_PQ; U#pragma __required_pointer_size __short Utypedef PLV * PLV_PL; U#pragma __ Crequired_pointer_size __restore U#else Utypedef __int64 PLV_PQ; Utypedef __int32 PLV_PL; U#endif /* __INITIALC_POINTER_SIZE */ N/*+ */N/* TYPE CODES FOR PRIVILEGE VECTORS */N/*- */N#define PLV$C_TYP_CMOD 1 /* CHANGE MODE VECTOR TYPE */N#define PLV$C_TYP_MSG 2 /* MESSAGE VECTOR TYPE */N#define PLV$CC_TYP_SSI 3 /* SYSTEM SERVICE INTERCEPT TYPE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PLVDEF_LOADED */ ww[UM/***************************************************************************/M/** C **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** C **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** C **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */H/* Source: 20-APR-1993 14:48:46 $1$DGA8345:[LIB_H.SRC]PLVECDEF.SDL;1 *//********************************************************************************************************************************//* C** MODULE $PLVECDEF ***/#ifndef __PLVECDEF_LOADED#define __PLVECDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifC #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ C */N/* PLVEC - SCS PORT LOAD VECTOR */N/* */N/* THIS DATA STRUCTURE CONTAINS A VECTOR LISTING THE ACTIVE CONNECTIONS BY */N/* TYPE ON A PORT. THE INDEX IS CONTAINED IN THE SBNB (SCS LOAD SHARE */N/* NAME BLOCK and in the CDT$L_ */N/* */N/*- C */#define PLVEC$C_MAX_INDEX 10N#define PLVEC$K_LENGTH 60 /* (TYC 15-Feb-89) */#define PLVEC$C_LENGTH 60#define PLVEC$S_PLVECDEF 16 Btypedef struct _plvec { /* WARNING: aggregate has origin of -12 */< /* WARNING: aggregate element "plvec$l_flink" ignored */< /* WARNING: aggregate element "plvec$l_blink" ignored */; /* WARNING: aggregate element "plvec$w_size" ignored */; /* WARNING: Daggregate element "plvec$b_type" ignored */= /* WARNING: aggregate element "plvec$b_subtyp" ignored */N unsigned int plvec$l_tot_connect; /*TOTAL NUMBER OF CONNECTIONS ON */N/* THIS PORT */ } PLVEC; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size D*/#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PLVECDEF_LOADED */ ww£[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to Danyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/MD/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 D */F/* Source: 20-MAY-1993 13:12:48 $1$DGA8345:[LIB_H.SRC]PMBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PMBDEF ***/#ifndef __PMBDEF_LOADED#define __PMBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmaDs supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endDif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* PAGE FAULT MONITOR CONTROL BLOCK */N/*- */ #define PMB$M_MODE 0x1N#define PMB$K_SUBPROC 0 /*Subprocess mode */N#define PMB$K_IMAGDE 1 /*Image mode */#define PMB$M_ASTIP 0x2#define PMB$M_QAST 0x4N#define PMB$K_LENGTH 76 /*Length of PMB */N#define PMB$C_LENGTH 76 /*Length of PMB */N#define PMB$S_PMBDEF 76 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _acb; #endif /* #ifdef __cplusplus */ typedef struct _pmb {N void *Dpmb$l_curbuf; /*Current buffer pointer */N void *pmb$l_bufbase; /*Current buffer base address */N unsigned short int pmb$w_size; /*Block size field */N unsigned char pmb$b_type; /*Dynamic structure type (PMB) */ __union {N unsigned char pmb$b_flags; /*Processing flags */ __struct {N unsigned pmb$v_mode : 1; /*Mode of operation */ DN unsigned pmb$v_astip : 1; /*AST in progress flag */P unsigned pmb$v_qast : 1; /*Imbedded ACB is enqueued on the PCB */' unsigned pmb$v_fill_2_ : 5; } pmb$r_fill_1_; } pmb$r_fill_0_;N unsigned int pmb$l_lastcpu; /*Last recorded CPU time */Q unsigned int pmb$l_overflow; /*Buffer overflow counter (both modes) */ int pmb$l_spare_4;N unsigned __int64 pmb$q_hdr; /*Free buffer  Dqueue header */N unsigned __int64 pmb$q_sbphdr; /*Filled buffer queue header */ __union {N __struct { /*Used as AST block in image mode */N struct _acb *pmb$l_astqfl; /*ACB flink */N struct _acb *pmb$l_astqbl; /*ACB blink */N char pmb$$_spare_1 [2]; /*SPARE */N unsigned char pmb$b_acmode; /*Owner access mode  D */N unsigned char pmb$b_rmod; /*AST delivery mode/flags */N unsigned int pmb$l_pid; /*PID for AST delivery */N void (*pmb$l_ast)(); /*AST routine address */N unsigned int pmb$l_astprm; /*AST parameter */P int pmb$l_fkb_fill [2]; /*fill to allow overlay of fork block */U void (*pmb$l_kast)(); /*Address of piggy-back kernel AST routine */  D } pmb$r_ast_block;O __struct { /*Utility storage in subprocess mode */N int pmb$$_spare_2 [2]; /*SPARE */N unsigned short int pmb$w_mbxchn; /*Subprocess mailbox channel */T unsigned char pmb$b_oacmode; /*Owner access mode (Synonym for ACMODE) */N char pmb$$_spare_3 [1]; /*SPARE */Q unsigned int pmb$l_ipid; /*IPID of subprocess (Synony Dm for PID) */N unsigned int pmb$l_epid; /*EPID of subprocess */N int pmb$$_spare_4 [2]; /*SPARE */ } pmb$r_subp_block; } pmb$r_acb_overlay; } PMB; #if !defined(__VAXC)-#define pmb$b_flags pmb$r_fill_0_.pmb$b_flags9#define pmb$v_mode pmb$r_fill_0_.pmb$r_fill_1_.pmb$v_mode;#define pmb$v_astip pmb$r_fill_0_.pmb$r_fill_1_.pmb$v_astip9#define pmb$v_qast pmb$r_fill_0_.pmb$r_fill_1_.pmb$v_qastDC#define pmb$l_astqfl pmb$r_acb_overlay.pmb$r_ast_block.pmb$l_astqflC#define pmb$l_astqbl pmb$r_acb_overlay.pmb$r_ast_block.pmb$l_astqblC#define pmb$b_acmode pmb$r_acb_overlay.pmb$r_ast_block.pmb$b_acmode?#define pmb$b_rmod pmb$r_acb_overlay.pmb$r_ast_block.pmb$b_rmod=#define pmb$l_pid pmb$r_acb_overlay.pmb$r_ast_block.pmb$l_pid=#define pmb$l_ast pmb$r_acb_overlay.pmb$r_ast_block.pmb$l_astC#define pmb$l_astprm pmb$r_acb_overlay.pmb$r_ast_block.pmb$l_astprm?#define pmb$l_kast pmb$r_acb_o Dverlay.pmb$r_ast_block.pmb$l_kastD#define pmb$w_mbxchn pmb$r_acb_overlay.pmb$r_subp_block.pmb$w_mbxchnF#define pmb$b_oacmode pmb$r_acb_overlay.pmb$r_subp_block.pmb$b_oacmode@#define pmb$l_ipid pmb$r_acb_overlay.pmb$r_subp_block.pmb$l_ipid@#define pmb$l_epid pmb$r_acb_overlay.pmb$r_subp_block.pmb$l_epid"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_sizDe __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PMBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is notD **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized tDo be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************************************************* D*******/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */L/* Source: 08-NOV-2017 14:51:38 $1$DGA8345:[LIB_H.SRC]POOLCHECKDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $POOLCHECKDEF ***/#ifndef __POOLCHECKDEF_LOADED#define __POOLCHECKDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __Dnomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !dDefined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* POOLCHECK - Poolcheck SYSGEN parameter layout */N/*- */ #define PCHECK$M_POISON 0x1#defDine PCHECK$M_CHECK 0x2#define PCHECK$M_RINGBUF 0x4#define PCHECK$M_IRP_FREE 0x8#define PCHECK$M_LRP_FREE 0x10#define PCHECK$M_XRP_ALIGN 0x20!#define PCHECK$M_DEALLO_SIZE 0x40#define PCHECK$M_P1 0x80#define PCHECK$S_POOLCHECKDEF 4 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _poolcheck {#pragma __nomember_alignment D__union { int pcheck$l_poolcheck; __struct { __union {N unsigned char pcheck$b_flags; /* Flag bits */ __struct {N unsigned pcheck$v_poison : 1; /* Poison on deallocation */N/* Enable other features */T unsigned pcheck$v_check : 1; /* Check poisoning on allocation */N/* and poison with allo pattern D */b unsigned pcheck$v_ringbuf : 1; /* Enable the ring buffer in the MIN version */N/* ...it is always enabled in MON. */` unsigned pcheck$v_irp_free : 1; /* Poison IRPs on deallocation (obsolete) */` unsigned pcheck$v_lrp_free : 1; /* Poison LRPs on deallocation (obsolete) */d unsigned pcheck$v_xrp_align : 1; /* Check xRP alignment on deallocation (obs) */p D unsigned pcheck$v_deallo_size : 1; /* Check deallocation length against allocation length */U unsigned pcheck$v_p1 : 1; /* Do poisoning/checking on P1 space */* } pcheck$r_flags_bits;) } pcheck$r_flags_overlay;h unsigned char pcheck$b_size_to_check; /* What deallo size to check if DEALO_LENGTH is set */N unsigned char pcheck$b_free; /* Free pattern */N unsigned char pcheck$b_a Dllo; /* Allocated pattern */ } pcheck$r_fill_1_; } pcheck$r_fill_0_; } POOLCHECK; #if !defined(__VAXC)>#define pcheck$l_poolcheck pcheck$r_fill_0_.pcheck$l_poolcheck^#define pcheck$b_flags pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$r_flags_overlay.pcheck$b_flagst#define pcheck$v_poison pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$r_flags_overlay.pcheck$r_flags_bits.pcheck$v_poisonr#define pcheck$v_check pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$r_flags_overDlay.pcheck$r_flags_bits.pcheck$v_checkv#define pcheck$v_ringbuf pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$r_flags_overlay.pcheck$r_flags_bits.pcheck$v_ringbufx#define pcheck$v_irp_free pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$r_flags_overlay.pcheck$r_flags_bits.pcheck$v_irp_freex#define pcheck$v_lrp_free pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$r_flags_overlay.pcheck$r_flags_bits.pcheck$v_lrp_freez#define pcheck$v_xrp_align pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$r_flags_overlay.pcheck$r_flags_bitDs.pcheck$v_xrp_align~#define pcheck$v_deallo_size pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$r_flags_overlay.pcheck$r_flags_bits.pcheck$v_deallo_sizel#define pcheck$v_p1 pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$r_flags_overlay.pcheck$r_flags_bits.pcheck$v_p1W#define pcheck$b_size_to_check pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$b_size_to_checkE#define pcheck$b_free pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$b_freeE#define pcheck$b_allo pcheck$r_fill_0_.pcheck$r_fill_1_.pcheck$b_allo"#endif /* # Dif !defined(__VAXC) */  N/*+ */N/* PCHK_REASON - Poolcheck bugcheck reason codes */N/* */N/* This defines the poolcheck bugcheck codes pushed on the stack when a */N/* poolcheck bugcheck is declared. */N/* D */N/*- */N#define PCHK_REASON$_CORRUPT 0 /* Corrupted packet */N#define PCHK_REASON$_ALIGN 1 /* Bad alignment (obsolete) */T#define PCHK_REASON$_XRP_ALIGN 2 /* Bad alignment of xRP packet (obsolete) */N#define PCHK_REASON$_PAGED 3 /* Paged block is partially outside */O#define PCHK_REASON$_NPAGED 4 /* Npaged block is partially outside */R#define PCHK D_REASON$_IPL 5 /* Called P1 routines with IPL too high */N#define PCHK_REASON$_AGGLOM 6 /* Agglomeration not done */`#define PCHK_REASON$_UNBALANCED 7 /* Deallocation and allocation were not the same size */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus  D }#endif#pragma __standard "#endif /* __POOLCHECKDEF_LOADED */ ww0_[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** !Dprior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permissi"Don of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */H/* Source: 14-DEC-2 #D000 08:15:54 $1$DGA8345:[LIB_H.SRC]POSIXDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $POSIXDEF ***/#ifndef __POSIXDEF_LOADED#define __POSIXDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragm$Da __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifnde%Df __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define PSXHDR$M_SID 0x1#define PSXHDR$M_PGID 0x2)#define PSXHDR$M_INITIAL_ALLOC 0x80000000!#define PSXHDR$K_HEADER_LENGTH 28 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifstruct psxhdr {#pragma __nomember_alignmentN void *ps&Dxhdr$l_flink; /* Standard listhead forward link */N void *psxhdr$l_blink; /* Standard listhead backward link */O unsigned short int psxhdr$w_size; /* Standard structure size, in bytes */X unsigned char psxhdr$b_type; /* Standard type code for POSIXID (DYN$C_PSX) */Y unsigned char psxhdr$b_subtype; /* Standard subtype code (DYN$C_PSX_ID_HEADER) */ __union {N unsigned int psxhdr$l_flags; /* Generic FLAGS longword */ 'D __struct {N unsigned psxhdr$v_sid : 1; /* Header for Session_ID structure */S unsigned psxhdr$v_pgid : 1; /* Header for Process_Group_ID structure */* unsigned psxhdr$v_fill_1 : 29;P unsigned psxhdr$v_initial_alloc : 1; /* Initial member structure */ } psxhdr$r_fill_1_; } psxhdr$r_fill_0_;N unsigned int psxhdr$l_leader; /* Leader of this Session or Group */T void *psxhdr$l_parent_link; /* Poi (Dnter back to owner parent (SESSION) */N void *psxhdr$l_member_ptr; /* Pointer to a PSXMEM structure */ char psxhdr$b_fill_2_ [4]; } ; #if !defined(__VAXC)6#define psxhdr$l_flags psxhdr$r_fill_0_.psxhdr$l_flagsC#define psxhdr$v_sid psxhdr$r_fill_0_.psxhdr$r_fill_1_.psxhdr$v_sidE#define psxhdr$v_pgid psxhdr$r_fill_0_.psxhdr$r_fill_1_.psxhdr$v_pgidW#define psxhdr$v_initial_alloc psxhdr$r_fill_0_.psxhdr$r_fill_1_.psxhdr$v_initial_alloc"#endif /* #if !defined(__VAXC)D) */ #define PSXMEM$M_SID 0x1#define PSXMEM$M_PGID 0x2)#define PSXMEM$M_INITIAL_ALLOC 0x80000000!#define PSXMEM$K_HEADER_LENGTH 36 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifstruct psxmem {#pragma __nomember_alignmentN void *psxmem$l_flink; /* Standard listhead forward link */N void *psxmem$l_blink; *D/* Standard listhead backward link */O unsigned short int psxmem$w_size; /* Standard structure size, in bytes */X unsigned char psxmem$b_type; /* Standard type code for POSIXID (DYN$C_PSX) */Y unsigned char psxmem$b_subtype; /* Standard subtype code (DYN$C_PSX_ID_MEMBER) */ __union {N unsigned int psxmem$l_flags; /* Generic FLAGS longword */ __struct {N unsigned psxmem$v_sid : 1; /* Member for Session_ID structure */S +D unsigned psxmem$v_pgid : 1; /* Member for Process_Group_ID structure */* unsigned psxmem$v_fill_2 : 29;P unsigned psxmem$v_initial_alloc : 1; /* Initial member structure */ } psxmem$r_fill_4_; } psxmem$r_fill_3_;N void *psxmem$l_header_ptr; /* Pointer back to header structure */N __int64 psxmem$q_fill_3; /* Reserved for furture use. */U unsigned int psxmem$l_capacity; /* Number of array slots in this s,Dtructure */N unsigned int psxmem$l_used; /* Number of array slots in use */#if defined(__VAXC) char psxmem$t_members[];#else)#define psxmem$t_members psxmem$b_fill_5_"#endif /* #if defined(__VAXC) */ char psxmem$b_fill_5_ [4]; } ; #if !defined(__VAXC)6#define psxmem$l_flags psxmem$r_fill_3_.psxmem$l_flagsC#define psxmem$v_sid psxmem$r_fill_3_.psxmem$r_fill_4_.psxmem$v_sidE#define psxmem$v_pgid psxmem$r_fill_3_.psxmem$r_fill_4_.psxmem$v_pgidW#defin-De psxmem$v_initial_alloc psxmem$r_fill_3_.psxmem$r_fill_4_.psxmem$v_initial_alloc"#endif /* #if !defined(__VAXC) */ #define PSXCTL$M_ADD_MEMBER 0x1"#define PSXCTL$M_REMOVE_MEMBER 0x2"#define PSXCTL$M_SID_STRUCTURE 0x4##define PSXCTL$M_PGID_STRUCTURE 0x8!#define PSXCTL$M_MEMBER_ONLY 0x10 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifstruct p .Dsxctl {#pragma __nomember_alignment __union {Z unsigned int psxctl$l_control; /* Define the control bits for SET_POSIX_MEMBER */ __struct {Z unsigned psxctl$v_add_member : 1; /* Add to exsiting or newly created group */Q unsigned psxctl$v_remove_member : 1; /* Remove from existing group */[ unsigned psxctl$v_sid_structure : 1; /* Group is a collection of SESSION IDs */\ unsigned psxctl$v_pgid_structure : 1; /* Group is a co /Dllection of Process IDs */U unsigned psxctl$v_member_only : 1; /* Create only the member structure */* unsigned psxctl$v_fill_8_ : 3; } psxctl$r_fill_7_; } psxctl$r_fill_6_; char psxctl$b_fill_9_ [4]; } ; #if !defined(__VAXC):#define psxctl$l_control psxctl$r_fill_6_.psxctl$l_controlQ#define psxctl$v_add_member psxctl$r_fill_6_.psxctl$r_fill_7_.psxctl$v_add_memberW#define psxctl$v_remove_member psxctl$r_fill_6_.psxctl$r_fill_7_.psxct 0Dl$v_remove_memberW#define psxctl$v_sid_structure psxctl$r_fill_6_.psxctl$r_fill_7_.psxctl$v_sid_structureY#define psxctl$v_pgid_structure psxctl$r_fill_6_.psxctl$r_fill_7_.psxctl$v_pgid_structureS#define psxctl$v_member_only psxctl$r_fill_6_.psxctl$r_fill_7_.psxctl$v_member_only"#endif /* #if !defined(__VAXC) */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_ali1Dgnment#endifstruct leaderless {#pragma __nomember_alignment void *leaderless$l_flink; void *leaderless$l_blink; } ; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifstruct session_id {#pragma __nomember_alignment void *session_id$l_flink; void *session_id$l_blink; } ;#define PSXMEM$S_MEMBER_SIZE 4 #define PSXM 2DEM$K_EXPAND_COUNT 16N#define POSIX$_SET_RUID 512 /* Set Real UserID */N#define POSIX$_SET_EUID 513 /* Set Effective UserID */N#define POSIX$_SET_RGID 514 /* Set Real GroupID */N#define POSIX$_SET_EGID 515 /* Set Effective GroupID */N#define POSIX$_SET_MODE 516 /* Mode of resulting personae */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Define3Dd whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __POSIXDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **4D/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary softwa5Dre licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************** 6D*********************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JAN-2004 07:50:02 $1$DGA8345:[LIB_H.SRC]TTYDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $POSIXVECDEF ***/#ifndef __POSIXVECDEF_LOADED#define __POSIXVECDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Stand7Dard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#def8Dine __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* */N/* POSIX driver vectors 9D */J/* These values are used by TTDRIVER to dispatch to Posix */I/* driver routines. The pointer to the Posix vector table is */I/* contained in TTY$A_POSIX in TTDRIVER. The Posix driver wil */I/* use the $VECINI and $VEC macros to generate its table based */I/* on these offsets. */N/* */N/*__ :D */N#define POSIX_LENGTH 88 /* must be at end. */Z#define POSIXS_POSIX_DEF 88 /* Old size name, synonym for POSIX$S_POSIX_FDT */ typedef struct _posix_fdt {N int (*posix_putnxt)(); /* POSIX VECTORS */N int (*posix_getnxt)(); /* */N int (*posix_writing)(); /* Getnxt entry for POSIXWRITE */N;D int (*posix_do_setm)(); /* Startio SET MODE */N int (*posix_interrupt)(); /* Send SIGINT */N int (*posix_break)(); /* Handle BREAK condition */N int (*posix_parity)(); /* Handle PARITY error */N int (*posix_sighup)(); /* Send SIGHUP */N int (*posix_fdt_read)(); /* */N int (*posix_fdt_write)D } POSIX_FDT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __POSIXVECDEF_LOADED */ ww`Ԥ[UM/***************************************************************************/M/** ?D **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** @D**/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*******************AD********************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */F/* Source: 10-MAR-2008 13:58:50 $1$DGA8345:[LIB_H.SRC]PQBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PQBDEF ***/#ifndef __PQBDEF_LOABDDED#define __PQBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#definCDe __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* PROCESS QUOTA BLOCK DEFINITION DD */N/*- */ #define PQB$M_IMGDMP 0x1#define PQB$M_DEBUG 0x2#define PQB$M_DBGTRU 0x4 #define PQB$M_PARSE_EXTENDED 0x8!#define PQB$M_CASE_SENSITIVE 0x10 #define PQB$M_MEDDLE_ENABLE 0x20#define PQB$M_MEDDLE 0x40"#define PQB$M_SEARCH_SYMLINK 0x180N#define PQB$K_LENGTH 2276 /* LENGTH OF PROCESS QUOTA BLOCK */N#define PQB$C_LENGTH 2276 /* LENGTH OF PRO EDCESS QUOTA BLOCK */N#define PQB$S_PQBDEF 2276 /* Old size name - synonym */ typedef struct _pqb {N unsigned __int64 pqb$q_prvmsk; /* PRIVILEGE MASK */N unsigned short int pqb$w_size; /* SIZE OF PQB IN BYTES */N unsigned char pqb$b_type; /* STRUCTURE TYPE CODE */N unsigned char pqb$b_sts; /* STATUS FLAGS */N unsigned int pqb$l_astlm; /* AST LIMIT FD */N unsigned int pqb$l_biolm; /* BUFFERED I/O LIMIT */N unsigned int pqb$l_bytlm; /* BUFFERED I/O LIMIT */N unsigned int pqb$l_cpulm; /* CPU TIME LIMIT */N unsigned int pqb$l_diolm; /* DIRECT I/O LIMIT */N unsigned int pqb$l_fillm; /* OPEN FILE LIMIT */N unsigned int pqb$l_pgflquota; /* PAGING FILE QUOTA */NGD unsigned int pqb$l_prclm; /* SUB-PROCESS LIMIT */N unsigned int pqb$l_tqelm; /* TIMER QUEUE ENTRY LIMIT */N unsigned int pqb$l_wsquota; /* WORKING SET QUOTA */N unsigned int pqb$l_wsdefault; /* WORKING SET DEFAULT */N unsigned int pqb$l_enqlm; /* ENQUEUE LIMIT */N unsigned int pqb$l_wsextent; /* MAXIMUM WORKING SET SIZE */X unsigned int pqb$l_jtqHDuota; /* JOB-WIDE LOGICAL NAME TABLE CREATION QUOTA */ __union {N unsigned short int pqb$w_flags; /* MISC FLAGS */ __struct {N unsigned pqb$v_imgdmp : 1; /* TAKE IMAGE DUMP ON SERIOUS ERROR */N unsigned pqb$v_debug : 1; /* /DEBUG startup desired */N unsigned pqb$v_dbgtru : 1; /* debugger present */a unsigned pqb$v_parse_extended : 1; /* Set if process is to be parse_styl IDe extended */X unsigned pqb$v_case_sensitive : 1; /* set process CASE_LOOKUP = SENSITIVE */l unsigned pqb$v_meddle_enable : 1; /* Record fact of process logical name & symbol alterations */` unsigned pqb$v_meddle : 1; /* Process logical names or symbols have been altered */P unsigned pqb$v_search_symlink : 2; /* Process symlink search mode */' unsigned pqb$v_fill_2_ : 7; } pqb$r_fill_1_; } pqb$r_fill_0_;N unsignedJD char pqb$b_msgmask; /* MESSAGE FLAGS */N unsigned char pqb$b_fill_1; /* Spare */N unsigned int pqb$l_uaf_flags; /* FLAGS FROM UAF RECORD */N unsigned int pqb$l_creprc_flags; /* FLAGS FROM $CREPRC ARGUMENT LIST */S __struct { /* MINIMUM AUTHORIZED SECURITY CLEARANCE */) unsigned char pqb$$$_fill_2 [20]; } pqb$r_min_class;S __struct { KD/* MAXIMUM AUTHORIZED SECURITY CLEARANCE */) unsigned char pqb$$$_fill_3 [20]; } pqb$r_max_class;N unsigned int pqb$l_input_att; /* SYS$INPUT attributes */N unsigned int pqb$l_output_att; /* SYS$OUTPUT attributes */N unsigned int pqb$l_error_att; /* SYS$ERROR attributes */N unsigned int pqb$l_disk_att; /* SYS$DISK attributes */N char pqb$t_cli_name [32]; /* CLI name LD */N char pqb$t_cli_table [256]; /* CLI table name */N char pqb$t_spawn_cli [32]; /* Spawn CLI name */N char pqb$t_spawn_table [256]; /* Spawn CLI table name */N char pqb$t_input [256]; /* LOGICAL NAME FOR INPUT */N char pqb$t_output [256]; /* LOGICAL NAME FOR OUTPUT */N char pqb$t_error [256]; /* LOGICAL NAME FOR ERROR OUTPUT */N char pqb$tMD_disk [256]; /* LOGICAL NAME FOR SYS$DISK */N char pqb$t_ddstring [256]; /* DEFAULT DIRECTORY STRING */N char pqb$t_image [256]; /* IMAGE NAME FOR NEW PROCESS */N char pqb$t_account [8]; /* ACCOUNT NAME FOR NEW PROCESS */U unsigned int pqb$l_arb_support; /* ARB SUPPORT BACKWARD COMPATIBILITY FLAG */N unsigned int pqb$l_rms_lcs; /* LOCAL CODE-SET FOR RMS FILENAME */N unsigned int pqb$l_sslog_fla NDgs; /* Flags for system service logging */O unsigned int pqb$l_sslog_bufsize; /* Size of system service log buffer */R unsigned int pqb$l_sslog_bufcnt; /* Number of system service log buffers */ } PQB; #if !defined(__VAXC)-#define pqb$w_flags pqb$r_fill_0_.pqb$w_flags=#define pqb$v_imgdmp pqb$r_fill_0_.pqb$r_fill_1_.pqb$v_imgdmp;#define pqb$v_debug pqb$r_fill_0_.pqb$r_fill_1_.pqb$v_debug=#define pqb$v_dbgtru pqb$r_fill_0_.pqb$r_fill_1_.pqb$v_dbgtruM#define pqb$v_pa ODrse_extended pqb$r_fill_0_.pqb$r_fill_1_.pqb$v_parse_extendedM#define pqb$v_case_sensitive pqb$r_fill_0_.pqb$r_fill_1_.pqb$v_case_sensitiveK#define pqb$v_meddle_enable pqb$r_fill_0_.pqb$r_fill_1_.pqb$v_meddle_enable=#define pqb$v_meddle pqb$r_fill_0_.pqb$r_fill_1_.pqb$v_meddleM#define pqb$v_search_symlink pqb$r_fill_0_.pqb$r_fill_1_.pqb$v_search_symlink"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr sPDize pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PQBDEF_LOADED */ ww"[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed bQDy Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMSRD Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************** SD***************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */F/* Source: 20-APR-1993 14:46:44 $1$DGA8345:[LIB_H.SRC]PRBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PRBDEF ***/#ifndef __PRBDEF_LOADED#define __PRBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __membTDer_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endUDif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* Protection block definition. The protection block is used to specify */N/* pro VDtection on objects internal to the system (e.g., devices, logical */N/* name tables, etc.) It is used as input to the EXE$CHECKACCESS routine. */N/* */N/*- */#define PRB$M_UIC 0x1#define PRB$M_ACL 0x2#define PRB$M_CLASS 0x4#define PRB$M_CLASSMAX 0x8#define PRB$S_PRBDEF 8N/* WD */ typedef struct _prb { __union {N unsigned short int prb$w_flags; /* Presence flag bits */ __struct {N unsigned prb$v_uic : 1; /* Set for simple UIC protection */N unsigned prb$v_acl : 1; /* Set for access control list */N unsigned prb$v_class : 1; /* Set for security classification */N unsigned prb$v_classmax : 1; /* Set for security class range */' unsigned prb$v XD_fill_2_ : 4; } prb$r_fill_1_; } prb$r_fill_0_;N unsigned short int prb$w_protection; /* SOGW protection mask */N unsigned int prb$l_owner; /* Owner UIC */N/* The remaining items in the protection block are optional and therefore */N/* do not have fixed offsets. The description given below is for a */N/* hypothetical fully configured protection block. */N/* YD */:/* ACL quadword; /* ACL listhead */=/* CLASS structure; /* Classification mask */I/* FILL_1 long dimension 5 fill; */I/* end CLASS; */@/* CLASSMAX structure; /* Maximum class mask for range */I/* FILL_2 long dimension 5 fill; */I/* end CLASSMAX; ZD */N/* */ } PRB; #if !defined(__VAXC)-#define prb$w_flags prb$r_fill_0_.prb$w_flags7#define prb$v_uic prb$r_fill_0_.prb$r_fill_1_.prb$v_uic7#define prb$v_acl prb$r_fill_0_.prb$r_fill_1_.prb$v_acl;#define prb$v_class prb$r_fill_0_.prb$r_fill_1_.prb$v_classA#define prb$v_classmax prb$r_fill_0_.prb$r_fill_1_.prb$v_classmax"#endif /* #if !defined(__VAXC) */  $#pragma __member[D_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PRBDEF_LOADED */ wwp[UM/***************************************************************************/M/** **/M/** HPE CONFID\DENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. Thi]Ds software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************** ^D**********//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 20-MAY-1993 14:46:27 $1$DGA8345:[LIB_H.SRC]PRCEVTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PRCEVTDEF ***/#ifndef __PRCEVTDEF_LOADED#define __PRCEVTDEF_LOADED 1 _D G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __`Doptional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* PRCEVTDEF aD */N/* */N/* This module defines the Process Event constants and structure */N/* offsets. */N/* */N#define PRCEVT$K_LENGTH 16 /* Length of PRCEVT */N#define PRCEVT$C_LENGTH 16 /* Length of PRCEVT */N#define PRCEVT$S_PRC bDEVTDEF 16 /* Old size name - synonym */ typedef struct _prcevt {N void *prcevt$l_flink; /* Foward link */N void *prcevt$l_blink; /* Backward link */N unsigned short int prcevt$w_size; /* Size, in bytes */N unsigned char prcevt$b_type; /* Structure type code */N unsigned char prcevt$b_subtype; /* Structure subtype */N int (*prcevtcD$l_handler)(); /* Handler address */ } PRCEVT;N#define PRCEVT$C_USRUNDWN_EXEC 0 /* Exec mode image rundown */N#define PRCEVT$C_USRUNDWN 1 /* Image rundown */N#define PRCEVT$C_DELPRC_RUNDWN 2 /* Process rundown */N#define PRCEVT$C_DELPRC_DELTVA 3 /* Process address space deletion */N#define PRCEVT$C_CRE_MIN_PROCESS 4 /* Minimal process creation */N#define PRCEVT$C_FORK_PROCdDSTRT 5 /* Child's fork() procstrt */N#define PRCEVT$C_MAX_EVENT 6 /* Maximum number of process events */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PRCEVTDEF_LOADED */ ww[UM/***************eD************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard EnterfDprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. gD **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 20-APR-1993 14:48:17 $1$DGA8345:[LIB_H.SRC]PRCPOLDEF.SDL;1 *//************************************************************* hD*******************************************************************//*** MODULE $PRCPOLDEF ***/#ifndef __PRCPOLDEF_LOADED#define __PRCPOLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointeriD_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif jD N/*+ */N/* PROCESS POLLER MAILBOX MESSAGE DEFINITIONS */N/*- */ H#define PRCPOL$C_SIZ 56 /*SIZE OF MESSAGE */#define PRCPOL$S_PRCPOLDEF 56 typedef struct _prcpol {N unsigned int prcpol$l_sysidl; /*LOW ORDER SYSTEM ID */N unsigned short int prcpol$w_sysidh; /* kDHIGH ORDER SYSTEM ID */N unsigned short int prcpol$w_fill_1; /* (UNUSED) */N char prcpol$t_nodnam [16]; /*SCA NODE NAME (COUNTED ASCII) */N unsigned char prcpol$b_prcnam [16]; /*PROCESS NAME */N unsigned char prcpol$b_dirinf [16]; /*DIRECTORY INFORMATION */ } PRCPOL; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragmlDa __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PRCPOLDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard EnterprisemD Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not nD **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************* oD***********************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 12-APR-2023 04:32:58 $1$DGA8345:[LIB_H.SRC]PRCSTRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PRCSTRDEF ***/#ifndef __PRCSTRDEF_LOADED#define __PRCSTRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __spDave#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef qD__struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* PRCSTRDEF */N/* */N/* This module definesrD the alternate procstrt structure offsets. */N/* */N#define PRCSTR$K_LENGTH 96 /* Length of PRCSTR */N#define PRCSTR$C_LENGTH 96 /* Length of PRCSTR */#define PRCSTR$S_PRCSTRDEF 96  9#ifdef __cplusplus /* Define structure prototypes */ struct _pcb; struct _phd; struct _va; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_S sDUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endiftypedef struct _prcstr {#pragma __nomember_alignmentN struct _prcstr *prcstr$l_flink; /* Foward link */N struct _prcstr *prcstr$l_blink; /* Backward link */N unsigned short int prcstr$w_size; /* Size, in bytes */N unsigned char prcstr$b_type; /* StructDture type code */N unsigned char prcstr$b_subtype; /* Structure subtype */N struct _pcb *prcstr$l_parent_pcb; /* Address of parent/creator's PCB */S int (*prcstr$l_procstrt)(); /* Address of alternate procstrt routine */N void *prcstr$l_ctx_buffer; /* Address of context buffer */N struct _phd *prcstr$l_phd_buffer; /* Address of PHD data buffer */N struct _va *prcstr$l_p1pointer_sva; /* System VA of P1 Pointer puDage */N int prcstr$l_p1pointer_svapte_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */N struct _va *prcstr$l_pio_sva; /* Syetem VA of PIO page */N/* Verified for x86 port - Clair Grant */T unsigned __int64 prcstr$q_p1pointer_pfn_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */N unsigned __int64 prcstr$q_pio_pfn_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */N int prcstr$l_pio_svapte_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */ char vD prcstr$b_fill_0_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *prcstr$pq_p1pointer_svapte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else1 unsigned __int64 prcstr$pq_ wDp1pointer_svapte_sva;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *prcstr$pq_pio_svapte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else+ unsigned __int64 prcstr$pq_pio_svapte_sva;#endifN __int64 prcstr$q_p1ptr_pfn_phys_addr; /* NOSVAPTE_V9.0 Dave Fairbanks */N __int64 prcstr$q_pio_pfn_phys_addr; /* NOSxDVAPTE_V9.0 Dave Fairbanks */ } PRCSTR; struct prcstrtrc {( unsigned int prcstrtrc$l_checkpoint;$ unsigned int prcstrtrc$l_retval;$ char prcstrtrc$b_padding [8184]; } ; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* yD__PRCSTRDEF_LOADED */ ww3[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. zD **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M{D/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */F/* Source: 08-JUL-1992 14:11:54 $1$DGA8345:[LIB_H.SRC]PRIDEF.SDL;1 */ |D/********************************************************************************************************************************//*** MODULE $PRIDEF ***/#ifndef __PRIDEF_LOADED#define __PRIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-}Ddefined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union ~D#else#define __union variant_union#endif#endif N/*+ */N/* PRIORITY INCREMENT CLASS DEFINITIONS */N/*- */X#define PRI$_NULL 0 /* NO PRIORITY INCREMENT (must be equal to 0) */N#define PRI$_IOCOM 1 /* DIRECT I/O COMPLETION */N#define PRI$_RESAVL 2 D /* RESOURCE AVAIL */N#define PRI$_TOCOM 3 /* TERMINAL OUTPUT COMPLETE */N#define PRI$_TICOM 4 /* TERMINAL INPUT COMPLETE */N#define PRI$_TIMER 5 /* TIMER INTERVAL COMPLETION */O#define PRI$_PINC_CNT 6 /* No. of priority increment classes */#define PRI$C_NUM_PRI 64#define PRI$C_NUM_NORMAL 16#define PRI$C_NUM_REALTIME 48N/* Realtime threshold D */#define PRI$C_RT_THRESHOLD 16N/* Priority interval for VMS native sched policy */#define PRI$C_MIN_VMS_PRIO 0#define PRI$C_MAX_VMS_PRIO 63N/* Priority interval for POSIX RT policies */#define PRI$C_MIN_PSXRT_PRIO 16#define PRI$C_MAX_PSXRT_PRIO 63 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_sizDe __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PRIDEF_LOADED */ ww[[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is notD **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized tDo be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************************************************* D*******/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */F/* Source: 30-SEP-2019 13:26:06 $1$DGA8345:[LIB_H.SRC]PRMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PRMDEF ***/#ifndef __PRMDEF_LOADED#define __PRMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdDef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define D__struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DEFINE PARAMETER DESCRIPTOR BLOCK */N/*- */#define PRM$M_DYNAMIC 0x1#define PRM$M_STATIC 0x2#define DPRM$M_SYSGEN 0x4#define PRM$M_ACP 0x8#define PRM$M_JBC 0x10#define PRM$M_RMS 0x20#define PRM$M_SYS 0x40#define PRM$M_SPECIAL 0x80#define PRM$M_DISPLAY 0x100#define PRM$M_CONTROL 0x200#define PRM$M_MAJOR 0x400#define PRM$M_PQL 0x800#define PRM$M_NEG 0x1000#define PRM$M_TTY 0x2000#define PRM$M_SCS 0x4000#define PRM$M_CLUSTER 0x8000#define PRM$M_ASCII 0x10000#define PRM$M_LGI 0x20000%#define PRM$M_MULTIPROCESSING 0x40000"#define PRM$M_CONVERT_PAGE 0x80000#define DPRM$M_MODIFIED 0x100000#define PRM$M_GALAXY 0x200000#define PRM$M_OBSOLETE 0x400000#define PRM$M_BITMAP 0x800000N#define PRM$C_BYTE 8 /* */N#define PRM$C_WORD 16 /* */N#define PRM$C_LONG 32 /* */N#define PRM$C_QUAD 64 /* */N#define PRM$C_OCTA 128 /* D */N#define PRM$C_BIT1024 1024 /* */O#define PRM$C_MAXNAMLEN 15 /*MAXIMUM LENGTH FOR PARAMETER NAME */N#define PRM$C_MAXUNILEN 11 /*MAXIMUM LENGTH FOR UNIT NAME */N#define PRM$K_LENGTH 64 /*SIZE OF DESCRIPTOR BLOCK */N#define PRM$C_LENGTH 64 /*SIZE OF DESCRIPTOR BLOCK */N#define PRM$S_PRM_DEF 64 /* Old size name - synonym */ tyDpedef struct _prm {N void *prm$l_addr; /*ADDRESS OF PARAMETER */N void *prm$l_int_addr; /*ADDRESS OF INTERAL VAL */N unsigned int prm$l_default; /*DEFAULT VALUE */N unsigned int prm$l_min; /*MINIMUM VALUE (-1)=>NONE */N unsigned int prm$l_max; /*MAXIMUM VALUE (-1)=>NONE */N unsigned int prm$l_int_min; /*POST-CONVERSION MIN */ D__union {N unsigned int prm$l_flags; /*TYPE FLAGS */ __struct {N unsigned prm$v_dynamic : 1; /* DYNAMIC PARAMETER */N unsigned prm$v_static : 1; /* STATIC PARAMETER */N unsigned prm$v_sysgen : 1; /* SYSGEN PARAMETER */N unsigned prm$v_acp : 1; /* ACP CONTROL PARAMETER */N unsigned prm$v_jbc : 1; /* JOB CONTROL PARAMETER D */N unsigned prm$v_rms : 1; /* RMS CONTROL PARAMETER */N unsigned prm$v_sys : 1; /* GENERAL SYSTEM PARAMETER */N unsigned prm$v_special : 1; /* SPECIAL PARAMETER */N unsigned prm$v_display : 1; /* DISPLAY ONLY (NO CHANGE) */N unsigned prm$v_control : 1; /* CONTROL PARAMETER */N unsigned prm$v_major : 1; /* MAJOR PARAMETER */N unsignDed prm$v_pql : 1; /* PROCESS QUOTA LIST */N unsigned prm$v_neg : 1; /* NEGATIVE */N unsigned prm$v_tty : 1; /* TERMINAL CONTROL PARAMETER */N unsigned prm$v_scs : 1; /* SCS CONTROL PARAMETERS */N unsigned prm$v_cluster : 1; /* CLUSTER CONTROL PARAMETERS */N unsigned prm$v_ascii : 1; /* ASCII PARAMETER */N unsigned prm$v_lgi : 1; /* LDOGIN PARAMETER */N unsigned prm$v_multiprocessing : 1; /* MULTIPROCESSING control */X unsigned prm$v_convert_page : 1; /* Pagelets externally, pages internally */N unsigned prm$v_modified : 1; /* Parameter modified (auditing) */N unsigned prm$v_galaxy : 1; /* GALAXY parameters */N unsigned prm$v_obsolete : 1; /* OBSOLETE parmeter */P unsigned prm$v_bitmap : 1; /* Parameter is a bi Dtmap ( > 32 bits) */ } prm$r_flags_bits; } prm$r_flags_overlay;N unsigned int prm$l_size; /*SIZE CODE FOR DATUM */N unsigned int prm$l_pos; /*BIT POSITION */N char prm$t_name [16]; /*ASCIC NAME STRING */N char prm$t_unit [12]; /*ASCIC UNIT STRING */ } PRM; #if !defined(__VAXC)3#define prm$l_flags prm$r_flags_overlay.prm$l_flagsH#definDe prm$v_dynamic prm$r_flags_overlay.prm$r_flags_bits.prm$v_dynamicF#define prm$v_static prm$r_flags_overlay.prm$r_flags_bits.prm$v_staticF#define prm$v_sysgen prm$r_flags_overlay.prm$r_flags_bits.prm$v_sysgen@#define prm$v_acp prm$r_flags_overlay.prm$r_flags_bits.prm$v_acp@#define prm$v_jbc prm$r_flags_overlay.prm$r_flags_bits.prm$v_jbc@#define prm$v_rms prm$r_flags_overlay.prm$r_flags_bits.prm$v_rms@#define prm$v_sys prm$r_flags_overlay.prm$r_flags_bits.prm$v_sysH#define prm$v_special prm$r_flDags_overlay.prm$r_flags_bits.prm$v_specialH#define prm$v_display prm$r_flags_overlay.prm$r_flags_bits.prm$v_displayH#define prm$v_control prm$r_flags_overlay.prm$r_flags_bits.prm$v_controlD#define prm$v_major prm$r_flags_overlay.prm$r_flags_bits.prm$v_major@#define prm$v_pql prm$r_flags_overlay.prm$r_flags_bits.prm$v_pql@#define prm$v_neg prm$r_flags_overlay.prm$r_flags_bits.prm$v_neg@#define prm$v_tty prm$r_flags_overlay.prm$r_flags_bits.prm$v_tty@#define prm$v_scs prm$r_flags_overlay.prm$r_flDags_bits.prm$v_scsH#define prm$v_cluster prm$r_flags_overlay.prm$r_flags_bits.prm$v_clusterD#define prm$v_ascii prm$r_flags_overlay.prm$r_flags_bits.prm$v_ascii@#define prm$v_lgi prm$r_flags_overlay.prm$r_flags_bits.prm$v_lgiX#define prm$v_multiprocessing prm$r_flags_overlay.prm$r_flags_bits.prm$v_multiprocessingR#define prm$v_convert_page prm$r_flags_overlay.prm$r_flags_bits.prm$v_convert_pageJ#define prm$v_modified prm$r_flags_overlay.prm$r_flags_bits.prm$v_modifiedF#define prm$v_galaxy prm$r D_flags_overlay.prm$r_flags_bits.prm$v_galaxyJ#define prm$v_obsolete prm$r_flags_overlay.prm$r_flags_bits.prm$v_obsoleteF#define prm$v_bitmap prm$r_flags_overlay.prm$r_flags_bits.prm$v_bitmap"#endif /* #if !defined(__VAXC) */ [#define PRM$K_BLOCKS 23 /* PRM$K_BLOCKS is the length of ALPHAVMSSYS.PAR */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* RestoDre the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PRMDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorizDed to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated Dor disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: D 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */I/* Source: 20-MAY-1993 16:52:15 $1$DGA8345:[LIB_H.SRC]PSTATEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PROCSTATE ***/#ifndef __PROCSTATE_LOADED#define __PROCSTATE_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIDAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct sDtruct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define PSTATE$K_LENGTH 272 /* Length of process state */ typedef struct _procstate {N unsigned __int64 pstate$q_r8; /* register R8 */N unsigned __int64 pstate$q_r9; /* register R9 */N unsigned __int64 pstate$q_r10; D /* register R10 */N unsigned __int64 pstate$q_r11; /* register R11 */N unsigned __int64 pstate$q_r12; /* register R12 */N unsigned __int64 pstate$q_r13; /* register R13 */N unsigned __int64 pstate$q_r14; /* register R14 */N unsigned __int64 pstate$q_r15; /* register R15 */N unsigned __int64 pstate$q_r29; /* register R29 D */N unsigned __int64 pstate$q_align_0; /* for alignment */N unsigned __int64 pstate$q_r0; /* register R0 */N unsigned __int64 pstate$q_r1; /* register R1 */N unsigned __int64 pstate$q_r16; /* register R16 */N unsigned __int64 pstate$q_r17; /* register R17 */N unsigned __int64 pstate$q_r18; /* register R18 */N unsignDed __int64 pstate$q_r19; /* register R19 */N unsigned __int64 pstate$q_r20; /* register R20 */N unsigned __int64 pstate$q_r21; /* register R21 */N unsigned __int64 pstate$q_r22; /* register R22 */N unsigned __int64 pstate$q_r23; /* register R23 */N unsigned __int64 pstate$q_r24; /* register R24 */N unsigned __int64 pstate$q_r25; D /* register R25 */N unsigned __int64 pstate$q_r26; /* register R26 */N unsigned __int64 pstate$q_r27; /* register R27 */N unsigned __int64 pstate$q_r28; /* register R28 */N unsigned __int64 pstate$q_align_1; /* for alignment */N unsigned __int64 pstate$q_r2; /* register R2 */N unsigned __int64 pstate$q_r3; /* register R3 D */N unsigned __int64 pstate$q_r4; /* register R4 */N unsigned __int64 pstate$q_r5; /* register R5 */N unsigned __int64 pstate$q_r6; /* register R6 */N unsigned __int64 pstate$q_r7; /* register R7 */N unsigned __int64 pstate$q_pc; /* register PC */N unsigned __int64 pstate$q_ps; /* register PS */ } PRDOCSTATE; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PROCSTATE_LOADED */ ww@[UM/***************************************************************************/M/** D **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMDS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*******************************D********************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */O/* Source: 30-JUN-2020 06:26:52 $1$DGA8345:[LIB_H.SRC]PROC_READ_WRITE.SDL;1 *//********************************************************************************************************************************/ /*** MODULE proc_read_write ***/ #ifndef __PROC D_READ_WRITE_LOADED"#define __PROC_READ_WRITE_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus D extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* Facility: D */N/* */I/* SYS */N/* */N/* Abstract: */N/* */I/* This module defines all the constants and datDa structures for */N/* PROC_READ_WRITE.BLI which are specific to that module. */N/* */N/* Environment: */N/* */I/* Kernel mode at IPL = 0 */N/* */G/*D Author: Steve DiPirro , Creation date: 30-JAN-1991 */N/* */N/* Modified by: */N/* */2/* X-14 HB Hartmut Becker 30-Jun-2020 */B/* Fix constant for Alpha pseudo register size. */B/* For X86, remove (Alpha/IA64?) floating point registers. */N/* D */5/* X-13 RAB Richard A. Bishop 16-Jul-2019 */B/* Change RIP cell name from PC to RIP (x86 only) */N/* */4/* X-12 CEG0495 Clair Grant 16-May-2018 */B/* Fix multiple definition of float_regs_length */N/* */4/* X-11 CEG0494 Clair Gra Dnt 15-May-2018 */B/* A couple more build bugs */N/* */4/* X-10 CEG0492 Clair Grant 15-May-2018 */B/* Fix a couple build bugs */N/* */:/* X-9 CV-0174 Camiel Vanderhoeven 11-May-2018 */B/* Provide X86 specifics. */ND/* */3/* X-8 CEG0133 Clair Grant 11-May-2017 */B/* Verified conditionals for x86 port. */B/* Updated copyright to VSI. */N/* */N/* X-7 PM Pramod Mangalore 02-Feb-2010 */B/* PTR 75-13-2205/QXCM1000976519 */B/* Add Da new constant EACB$K_PC_PSL. */N/* */4/* X-6 RAB Richard A. Bishop 11-Jun-2004 */B/* Add a cell for the actual size of the extended ACB. */B/* If it's over 65K, the size won't fit in the ACB$W_SIZE */B/* field. */N/* */./* X-5 CAD Chip Dancy 20-J Dun-2003 */B/* Increase IA64 memory pool size to 16384. */N/* */./* X-4 CAD Chip Dancy 16-May-2003 */B/* Add IPF fields. */N/* */4/* X-3 RAB Richard A. Bishop 06-Dec-2002 */B/* Add IA64 register set */N/* D */4/* X-2 RAB Richard A. Bishop 07-Feb-2000 */B/* Add new class of processor registers */N/* */I/* (fix audit trail - idents are out of step) */N/* */5/* X-2 RS00178 Richard Sayde 28-Oct-1991 */B/* Add definitions to be able tDo read and write registers. */N/* */5/* X-1 RS00175 Richard Sayde 22-Oct-1991 */B/* Put module into CMS - made some changes based on the */B/* way SDA solved the problem. */N/*--- */N/* */N/* D */N/* */N/* ACB extensions to accommodate various additional pieces of information */N/* needed to complete process read/write operations. */N/* */N#define EACB$K_MEMORY 1 /* virtual memory */N#define EACB$K_GENERAL_REGISTER 2 /* RAX..R15,PC,RFLADGS */K#define EACB$K_PSEUDO_REGISTER 3 /* In-memory Alpha/VAX registers */I#define EACB$K_MMX_REGISTER 4 /* MM0..7 */I#define EACB$K_XMM_REGISTER 5 /* XMM0..31 */I#define EACB$K_YMM_REGISTER 6 /* YMM0..31 */I#define EACB$K_ZMM_REGISTER 7 /* ZMM0..31 */N#define EACB$K_INTERNAL_REGISTER 8 /* VIRBND,SYSPTBR etc */N#define EACB$K_INVOCATION_CODNTEXT 9 /* ICB */N#define EACB$K_PC_PSL 10 /* PC,PS */N#define EACB$K_GEN_REGISTER_SIZE 8 /* Number of bytes in a general */N/* register */#define EACB$K_RAX 0#define EACB$K_RCX 1#define EACB$K_RDX 2#define EACB$K_RBX 3#define EACB$K_RSI 4#define EACB$K_RDI 5#define EACB$K_RSP 6#define EACB$K_RBP 7#define EACB$K_R8 8#define EACB$K_RD9 9#define EACB$K_R10 10#define EACB$K_R11 11#define EACB$K_R12 12#define EACB$K_R13 13#define EACB$K_R14 14#define EACB$K_R15 15#define EACB$K_PC 16#define EACB$K_RFLAGS 17!#define EACB$K_GEN_REGS_LENGTH 18%#define EACB$K_PSEUDO_REGISTER_SIZE 8#define EACB$K_PR0 0#define EACB$K_PR1 1#define EACB$K_PR2 2#define EACB$K_PR3 3#define EACB$K_PR4 4#define EACB$K_PR5 5#define EACB$K_PR6 6#define EACB$K_PR7 7#define EACB$K_PR8 8#define EACB$K_PR9 9#define EACBD$K_PR10 10#define EACB$K_PR11 11#define EACB$K_PR12 12#define EACB$K_PR13 13#define EACB$K_PR14 14#define EACB$K_PR15 15#define EACB$K_PR16 16#define EACB$K_PR17 17#define EACB$K_PR18 18#define EACB$K_PR19 19#define EACB$K_PR20 20#define EACB$K_PR21 21#define EACB$K_PR22 22#define EACB$K_PR23 23#define EACB$K_PR24 24#define EACB$K_PR25 25#define EACB$K_PR26 26#define EACB$K_PR27 27#define EACB$K_PR28 28#define EACB$K_PR29 29#define EACB$K_PR30 30#define EACB$KD_PR31 31$#define EACB$K_PSEUDO_REGS_LENGTH 32N/* Verified for x86 port - Camiel Vanderhoeven */"#define EACB$K_MMX_REGISTER_SIZE 8#define EACB$K_MM0 0#define EACB$K_MM1 1#define EACB$K_MM2 2#define EACB$K_MM3 3#define EACB$K_MM4 4#define EACB$K_MM5 5#define EACB$K_MM6 6#define EACB$K_MM7 7 #define EACB$K_MMX_REGS_LENGTH 8##define EACB$K_XMM_REGISTER_SIZE 16#define EACB$K_XMM0 0#define EACB$K_XMM1 1#define EACB$K_XMM2 2#define EACB$K_XMM3 3D#define EACB$K_XMM4 4#define EACB$K_XMM5 5#define EACB$K_XMM6 6#define EACB$K_XMM7 7#define EACB$K_XMM8 8#define EACB$K_XMM9 9#define EACB$K_XMM10 10#define EACB$K_XMM11 11#define EACB$K_XMM12 12#define EACB$K_XMM13 13#define EACB$K_XMM14 14#define EACB$K_XMM15 15#define EACB$K_XMM16 16#define EACB$K_XMM17 17#define EACB$K_XMM18 18#define EACB$K_XMM19 19#define EACB$K_XMM20 20#define EACB$K_XMM21 21#define EACB$K_XMM22 22#define EACB$K_XMM23 2D3#define EACB$K_XMM24 24#define EACB$K_XMM25 25#define EACB$K_XMM26 26#define EACB$K_XMM27 27#define EACB$K_XMM28 28#define EACB$K_XMM29 29#define EACB$K_XMM30 30#define EACB$K_XMM31 31!#define EACB$K_XMM_REGS_LENGTH 32##define EACB$K_YMM_REGISTER_SIZE 32#define EACB$K_YMM0 0#define EACB$K_YMM1 1#define EACB$K_YMM2 2#define EACB$K_YMM3 3#define EACB$K_YMM4 4#define EACB$K_YMM5 5#define EACB$K_YMM6 6#define EACB$K_YMM7 7#define EACB$K_YMM8 8#defDine EACB$K_YMM9 9#define EACB$K_YMM10 10#define EACB$K_YMM11 11#define EACB$K_YMM12 12#define EACB$K_YMM13 13#define EACB$K_YMM14 14#define EACB$K_YMM15 15#define EACB$K_YMM16 16#define EACB$K_YMM17 17#define EACB$K_YMM18 18#define EACB$K_YMM19 19#define EACB$K_YMM20 20#define EACB$K_YMM21 21#define EACB$K_YMM22 22#define EACB$K_YMM23 23#define EACB$K_YMM24 24#define EACB$K_YMM25 25#define EACB$K_YMM26 26#define EACB$K_YMM27 27#define EACB$K_YMMD28 28#define EACB$K_YMM29 29#define EACB$K_YMM30 30#define EACB$K_YMM31 31!#define EACB$K_YMM_REGS_LENGTH 32##define EACB$K_ZMM_REGISTER_SIZE 64#define EACB$K_ZMM0 0#define EACB$K_ZMM1 1#define EACB$K_ZMM2 2#define EACB$K_ZMM3 3#define EACB$K_ZMM4 4#define EACB$K_ZMM5 5#define EACB$K_ZMM6 6#define EACB$K_ZMM7 7#define EACB$K_ZMM8 8#define EACB$K_ZMM9 9#define EACB$K_ZMM10 10#define EACB$K_ZMM11 11#define EACB$K_ZMM12 12#define EACB$K_ZMM13 13#dDefine EACB$K_ZMM14 14#define EACB$K_ZMM15 15#define EACB$K_ZMM16 16#define EACB$K_ZMM17 17#define EACB$K_ZMM18 18#define EACB$K_ZMM19 19#define EACB$K_ZMM20 20#define EACB$K_ZMM21 21#define EACB$K_ZMM22 22#define EACB$K_ZMM23 23#define EACB$K_ZMM24 24#define EACB$K_ZMM25 25#define EACB$K_ZMM26 26#define EACB$K_ZMM27 27#define EACB$K_ZMM28 28#define EACB$K_ZMM29 29#define EACB$K_ZMM30 30#define EACB$K_ZMM31 31!#define EACB$K_ZMM_REGS_LENGTH 32"#def Dine EACB$K_INT_REGISTER_SIZE 8#define EACB$K_VIRBND 0#define EACB$K_SYSPTBR 1N#define EACB$K_SCC 2 /* VIRBND,SYSPTBR etc */ #define EACB$K_INT_REGS_LENGTH 3N/*Invocation Context size is in ICBDEF */N#define EACB$K_MEMORY_POOL_SIZE 16384 /* Memory pool size following EACB */#define EACB$M_DONE 0x1#define EACB$M_HALF_DONE 0x2#define EACB$M_SUSPEND 0x4N#define EACB$K_BLOCK_SIZE 68 /*Length of data block D */ struct acb_extend {N unsigned __int64 eacb$q_local_adr; /*Local process address */N unsigned __int64 eacb$q_target_adr_type; /*target type, one of: */N/* Verified for x86 port - Camiel Vanderhoeven */N unsigned __int64 eacb$q_target_adr; /*Target process address */N/* Verified for x86 port - Camiel Vanderhoeven */N/* Temporary for xbuild, needs x86 review - Clair Grant D */S unsigned __int64 eacb$q_status_adr; /*Address of src process status longword */N/* Temporary for xbuild, needs x86 review - Clair Grant */X unsigned __int64 eacb$q_memory_pool_addr; /*Address of memory pool following EACB */N unsigned int eacb$l_status_icb_alert_code; /*ICB error status or zero */N unsigned int eacb$l_status; /*Operation completion status */N unsigned int eacb$l_buffer_size; /*Buffer size to transfer D */N unsigned int eacb$l_local_pid; /*Local process PID */N unsigned int eacb$l_image_count; /*Process image count */N __union { /* */N unsigned int eacb$l_flags; /*For references to whole thing */N __struct { /*For individual bits */N unsigned eacb$v_done : 1; /*Operation complete flag */N unsigned D eacb$v_half_done : 1; /*Operation partly complete flag */R unsigned eacb$v_suspend : 1; /*Set if target process should suspend */( unsigned eacb$v_fill_0_ : 5; } eacb$r_flags_bits;N/* */ } eacb$r_flags_field;N/* */U unsigned int eacb$l_acb_extend_size; /*Size of extended ACB actually allocated */ } D; #if !defined(__VAXC)4#define eacb$l_flags eacb$r_flags_field.eacb$l_flags>#define eacb$r_flags_bits eacb$r_flags_field.eacb$r_flags_bits1#define eacb$v_done eacb$r_flags_bits.eacb$v_done;#define eacb$v_half_done eacb$r_flags_bits.eacb$v_half_done7#define eacb$v_suspend eacb$r_flags_bits.eacb$v_suspend"#endif /* #if !defined(__VAXC) */ ##define PRCSTK$K_NOFP_SAVE_SIZE 144 struct proc_save_regs {N/* Verified for x86 port - Camiel Vanderhoeven */DN unsigned __int64 prcstk$q_rax; /* Saved RAX */N unsigned __int64 prcstk$q_rcx; /* Saved RCX */N unsigned __int64 prcstk$q_rdx; /* Saved RDX */N unsigned __int64 prcstk$q_rbx; /* Saved RBX */N unsigned __int64 prcstk$q_rsi; /* Saved RSI */N unsigned __int64 prcstk$q_rdi; /* Saved RDI */N unsigned __int64 prcDstk$q_rsp; /* Saved RSP */N unsigned __int64 prcstk$q_rbp; /* Saved RBP */N unsigned __int64 prcstk$q_r8; /* Saved R8 */N unsigned __int64 prcstk$q_r9; /* Saved R9 */N unsigned __int64 prcstk$q_r10; /* Saved R10 */N unsigned __int64 prcstk$q_r11; /* Saved R11 */N unsigned __int64 prcstk$q_r12; /* Saved R D12 */N unsigned __int64 prcstk$q_r13; /* Saved R13 */N unsigned __int64 prcstk$q_r14; /* Saved R14 */N unsigned __int64 prcstk$q_r15; /* Saved R15 */N unsigned __int64 prcstk$q_rip; /* Saved RIP */N unsigned __int64 prcstk$q_rflags; /* Saved RFLAGS */ } ;$#define PRCSTK$K_INTREG_SAVE_SIZE 24 struct proc_save_int_reg Ds {N unsigned __int64 prcstk$q_virbnd; /* Saved VIRBND */N unsigned __int64 prcstk$q_sysptbr; /* Saved SYSPTBR */N unsigned __int64 prcstk$q_scc; /* Saved SCC */ } ;N/* */N/* End of module proc_read_write */N/* */ $#pragmDa __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard %#endif /* __PROC_READ_WRITE_LOADED */ wwV[UM/***************************************************************************/M/** D**/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INDC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********************************************D******************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */G/* Source: 26-JAN-2022 23:16:38 $1$DGA8345:[LIB_H.SRC]LANUDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PROTODEF ***/#ifndef __PROTODEF_LOADED#define __PROT DODEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_paramsD ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* LAN FRAME/PACKET DEFINITONS */N/* FRAME TYPES: D */N/* Token Ring */N/* FDDI */N/* ATM */N/* CSMA/CD */N/* Ethernet */N/* IEEE 802.3 */N/* PDACKET TYPES */N/* Mapped Ethernet (FDDI and TR only) */N/* 802.2 */N/* 802E */N/* Token Ring Frame Header */N#define TR$C_HDR_LEN 14 /* Size of Token Ring Header */ Ntypedef struct _tr_hdr { D /* Token Ring Frame hdr struct */N unsigned char tr$b_ac; /* Access Control field */N unsigned char tr$b_fc; /* Frame Control field */N unsigned char tr$g_da [6]; /* Destination Address field */N unsigned char tr$g_sa [6]; /* Source Address field */ } TR_HDR;N/* Token Ring Maximum Frame length including all fields from AC through CRC */#define TR$C_MAX_FRM_LEN 4462N/* TDoken Ring Source Routing fields */c#define TR$M_SA_RI 1 /* Bit in byte 0 of SA that indicates packet is a Source */N/* Routing packet. */N#define TR$C_MAX_SR_LEN 30 /* Max size of SR Field */#define TR$C_MAX_TR_HDR 44N/* Maximum header size */N#define TR$C_SRF 0 /* Bits 0-2 are Rout Ding Type */#define TR$C_ARE 12418#define TR$C_STE 12514#define TR$M_EXPL 128#define TR$M_SR_RT 224N#define TR$M_SR_LTH 31 /* Bits 3-7 are Length bits */N/* Must be even... */N#define TR$M_SR_D 128 /* Bit 0 is Direction */N#define TR$M_SR_D_ASC 0 /* Ascending (rd1, rd2, etc.) */N#define TR$M_SR_D_DSC 1 /* Descending (rdn, rdn-1, etc D.) */N#define TR$M_SR_LF 14 /* Bits 1-3 are Longest Frame */N#define TR$M_SR_LF_4442 6 /* Longest frame = 4442 */ Ntypedef struct _tr_sr_rc { /* Routing Control fields */ unsigned char tr$b_rc0; unsigned char tr$b_rc1; } TR_SR_RC;N#define TR$C_SR_RC 14 /* Location of RC fields */N#define TR$C_SR_RD 16 /* Location of RD fields */N/* All RD fielDds are shorts... */N#define TR$M_SR_LI 4095 /* LAN Information bits in RD */N#define TR$M_SR_BN 61440 /* Bridge Number bits in RD */N/* Token Ring Constants for AC/FC definitions */N#define TR$M_AC_PPP 7 /* AC PPP field is low 3 bits */N#define TR$M_AC_T 8 /* Token Bit (0=token, 1=SFS) */N/* M-bit used by monitor D */N#define TR$M_AC_RRR 224 /* Reservation bits */N#define TR$M_FC_MAC 0 /* FC for MAC Frames (unused) */N#define TR$M_FC_LLC 2 /* FC for LLC Users */N#define TR$M_FC_UNDEF 1 /* FC for Undefined purposes */N#define TR$M_FC_CTL 252 /* CTL field in FC (MAC only) */N#define TR$C_AC_DEF 16 /* Default AC D */N#define TR$C_FC_DEF 64 /* Default FC */N/* FDDI Frame Header */N#define FDDI$C_HDR_LEN 13 /* Size of FDDI Header */ Ntypedef struct _fddi_hdr { /* FDDI Frame header structure */N unsigned char fddi$b_fc; /* Frame Control field */N unsigned char fddi$g_da [6]; /* Destination Address field */N unsiDgned char fddi$g_sa [6]; /* Source Address field */ } FDDI_HDR;N/* Maximum Frame length for FDDI including all fields from FC through CRC */#define FDDI$C_MAX_FRM_LEN 4495N/* Constants for FC definitions */N#define FDDI$V_FC_PPP 0 /* FC PPP field starts at bit 0 */R#define FDDI$M_FC_PPP 7 /* FC PPP field is low order three bits */N#define FDDI$S_FC_PPP 3 /* FC PPP field isD 3 bits wide */N#define FDDI$C_FC_LLC_MIN 80 /* FC for LLC Users (minimum) */N#define FDDI$C_FC_LLC_DEF 80 /* FC for LLC Users (default) */N#define FDDI$C_FC_LLC_MAX 87 /* FC for LLC Users (maximum) */N#define FDDI$C_FC_SMT_MIN 65 /* FC for LLC Users (minimum) */N#define FDDI$C_FC_SMT_DEF 65 /* FC for LLC Users (default) */N#define FDDI$C_FC_SMT_MAX 79 /* FC for LLC Users (maximum) */N/* ADTM Frame Header */N#define ATM$C_HDR_LEN 12 /* Size of ATM Header */ Ntypedef struct _atm_hdr { /* ATM Frame header structure */N unsigned char atm$g_da [6]; /* Destination Address field */N unsigned char atm$g_sa [6]; /* Source Address field */ } ATM_HDR;Y/* Maximum Frame length for ATM including all fields in header (even 2 bytes for LEH) */ DN/* Does not include padding or trailer */#define ATM$C_MAX_FRM_LEN 9234N/* CSMACD (Ethernet/IEEE 802.3) Frame Header */N#define CSMACD$C_HDR_LEN 14 /* Size of CSMACD Header */N#define CSMACD$C_PAD_LEN 16 /* Size of CSMACD Header */ typedef struct _csmacd_hdr {N unsigned char csmacd$g_da [6]; /* Destination Address field */N unsigned char csmacd$g_sa [6]; D /* Source Address field */ __union { __struct {O unsigned short int csmacd$w_pty; /* Ethernet Protocol Type field */" } csmacd$r_field3_eth; __struct {O unsigned short int csmacd$w_len_8023; /* IEEE 802.3 Length field */" } csmacd$r_field3_802; } csmacd$r_field3;Q unsigned short int csmacd$w_pad; /* optional Ethenet Length (PAD) field */ } CSMACD_HDR; #if !defined(__VAXC)?#define cs Dmacd$r_field3_eth csmacd$r_field3.csmacd$r_field3_eth5#define csmacd$w_pty csmacd$r_field3_eth.csmacd$w_pty?#define csmacd$r_field3_802 csmacd$r_field3.csmacd$r_field3_802?#define csmacd$w_len_8023 csmacd$r_field3_802.csmacd$w_len_8023"#endif /* #if !defined(__VAXC) */ N/* Maximum Frame length for FDDI including all fields from FC through CRC */!#define CSMACD$C_MAX_FRM_LEN 1518N/* Packet Header Definitions */N/* D */N/* Packet headers begin at the byte following the FDDI or CSCMACD */N/* frame header. (at offsets FDDI$C_HDR_LEN/CSMACD$C_HDR_LEN) */N/* */N/* Packet types supported: */N/* - FDDI mapped ethernet (for FDDI only) */N/* - IEEE 802.1 SNAP SAP (802E/802PID) D */N/* - IEEE 802.2, Class I, including (Type 1 packets only): */I/* - UI */I/* - XID */I/* - TEST */N/* FDDI Mapped Ethernet packet header */\#define MPDETH$C_LEN 8 /* Size of Mapped Ethernet Header without Padding D*/T#define MPDETH$C_PAD_LEN 10 /* Size of Mapped Eth Header with Padding */ typedef struct _mpdeth_hdr {N unsigned char mpdeth$g_snap_sap [3]; /* SNAP-SAP hex */N unsigned char mpdeth$g_map_pid [3]; /* SNAP PID <00-00-00> */N unsigned short int mpdeth$w_pty; /* Ethernet Protocol Type field */U unsigned short int mpdeth$w_pad; /* PAD (length) field (If User enables it) */ } MPDETH_HDR;N/* IEEE Standard 802.2 (LLC), pack Det header */R#define LLC$C_ONEBYTCTL_LEN 3 /* Size of 802.2 Header with 1 byte CTL */P#define LLC$G_ONEBYT_DATA 3 /* Start of User Data with 1 byte CTL */R#define LLC$C_TWOBYTCTL_LEN 4 /* Size of 802.2 Header with 2 byte CTL */P#define LLC$G_TWOBYT_DATA 4 /* Start of User Data with 2 byte CTL */ typedef struct _hdr_802 {N unsigned char llc$b_dsap; /* Destination Service Access Point */N unsigned cha Dr llc$b_ssap; /* Source Service Access Point */N unsigned char llc$b_ctl1; /* Control field */N unsigned char llc$b_ctl2; /* optional second byte of CTL */ } HDR_802;N/* IEEE 802.1 SNAP SAP packet header (802E/802PID) */N#define SNAP$C_LEN 8 /* Size of 802 SNAP Header */ typedef struct _snap_hdr {N unsigned char snap$g_sap [3]; /* SNAP-SAP hex D */N unsigned char snap$g_pid [5]; /* Protocol Identifier (PID) */ } SNAP_HDR; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PROTODEF_LOADED */ ww[UM/***********************************************D****************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP D**/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** D **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */F/* Source: 22-APR-1993 13:43:14 $1$DGA8345:[LIB_H.SRC]PRQDEF.SDL;1 *//************************************************************************************************* D*******************************//*** MODULE $PRQDEF ***/#ifndef __PRQDEF_LOADED#define __PRQDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default Dto 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ D */N/* INTER-PROCESSOR REQUEST BLOCK DEFINITIONS */N/* */N/* THIS IS THE BASIC FORMAT FOR AN EXECUTIVE OR DRIVER REQUEST FROM */N/* ONE PROCESSOR TO ANOTHER PROCESSOR. */N/*- */N#define PRQ$C_EXEC 0 /* EXECUTIVE REQUEST ID D */N#define PRQ$C_MAILBOX 1 /* MAILBOX REQUEST ID */N#define PRQ$C_REMDISK 2 /* REMOTE DISK REQUEST ID */N#define PRQ$C_HSC50 3 /* HSC-50 REQUEST ID */P#define PRQ$C_SETEF 0 /* COPY COMMON EVENT FLAG REQUEST ID */N#define PRQ$C_RESAVL 1 /* REPORT RESOURCE AVAILABLE */N#define PRQ$C_MINLENGTH 64 /*MINIMUM REQUEST BLOCK LENGTH */#define PR DQ$S_PRQDEF 40 typedef struct _prq {N struct _prq *prq$l_flink; /*FORWARD LINK TO NEXT BLOCK */N struct _prq *prq$l_blink; /*BACKWARD LINK TO PREVIOUS BLOCK */N int prqdef$$_fill_1 [4]; /* (RESERVED FOR FORK CONTEXT) */N unsigned short int prq$w_to_port; /*PORT NUMBER TO SEND REQUEST TO */N unsigned short int prq$w_fr_port; /*PORT NUMBER REQUEST IS FROM */N unsigned short int prq$w_dispatch; /*MESSAGE DISPATCHER IDD */N/* MESSAGE DISPATCHER ID'S */N short int prqdef$$_fill_2; /*(UNUSED) */N/* */N unsigned short int prq$w_reqtype; /*REQUEST TYPE */N/* MESSAGE DISPATCHER REQUEST SUB-TYPES */N unsigned short int prq$w_unit; /*UNIT NUMBER */N unsiDgned int prq$l_param; /*FIRST PARAMETER */ } PRQ; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PRQDEF_LOADED */ ww̨[UM/*********************************************************************gDPRMDEFD PROCSTATED`PROC_READ_WRITEDRPROTODEFDPRQDEFDPSBDEFET PSCANCTXDEF/EPSHDEFdEDPSMDEFyEdPSRDEFE PSXFCBDEFE. PSXFDBDEFEX PSXROODEFEPTEDEFb PTE_FUNCTIONSEPTRDEFE\ PWDHISDEFFPXBDEF&F PXDSRRDEF7FPXMLDEFRF\PYXISDEFG@PZDEFGRADDEF RAD_MACROSHRBFDEFHhRBUNDEF&HRCTDEF5HRDABDEF>H^RDDBDEFGHRDDEFPHRDEDEF SCH_ROUTINES. SCS_ROUTINESD******/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** D **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** D **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */F/* Source: 03-DEC-2021 08:51:22 $1$DGA8345:[LIB_H.SRC]PSBDEF.SDL;1 *//*********************************************************************************************************************** D*********//*** MODULE $PSBDEF ***/#ifndef __PSBDEF_LOADED#define __PSBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */D#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  1#include /* Define the prvdef type */N/* D */N/* The following constants apply to members of the PSB structure */N/* */N#define PSB$K_SIZE_ACCOUNT 32 /* */N#define PSB$K_SIZE_USERNAME 32 /* */N#define PSB$K_COUNT_PERSONAE 8 /* */N#define PSB$K_COUNT_RIGHTS 10 D /* */N/* */N/* The following constants apply to members of the PSB structure */N/* PSB$AR_RIGHTS and PSB$AR_AUTHRIGHTS and should match their bitwise */N/* counterparts. */N/* */N/* NOTE : Any changes to the constants here must be refle Dcted in */I/* bitfields in the RIGHTS_ENABLED field. */N/* */#define PSB$K_RIGHTS_PERSONA 0#define PSB$K_RIGHTS_SYSTEM 1 #define PSB$K_RIGHTS_INSTALLED 2 #define PSB$K_RIGHTS_SUBSYSTEM 3 #define PSB$K_RIGHTS_TEMPORARY 4#define PSB$K_RIGHTS_CHKPRO 9N/* */N/* Persona Security Block definitions D */N/* */ #define PSB$M_PERMANENT 0x1#define PSB$M_SECAUDIT 0x2#define PSB$M_CLONE 0x8#define PSB$M_RMS 0x10#define PSB$M_IO 0x20#define PSB$M_TCB 0x40#define PSB$M_DEBIT 0x80#define PSB$M_RESERVE 0x100#define PSB$M_DELEGATE 0x200#define PSB$M_CREATE_USER 0x400#define PSB$M_CREATE_TLV 0x800"#define PSB$M_CREATE_ITMLST 0x1000N#define PSB$K_FLAGS_BIT_COUNT 13 /* NumbeDr of flags */'#define PSB$M_DELETE_PENDING 0x20000000&#define PSB$M_DP_PROCESSING 0x40000000$#define PSB$M_DEALLOCATED 0x80000000'#define PSB$K_RESERVE_PERSONA_LENGTH 56#define PSB$M_PERSONA 0x1#define PSB$M_SYSTEM 0x2#define PSB$M_INSTALLED 0x4#define PSB$M_SUBSYSTEM 0x8#define PSB$M_TEMPORARY 0x10#define PSB$M_CHKPRO 0x200##define PSB$K_CLONE_REGION_SIZE 228  9#ifdef __cplusplus /* Define structure prototypes */struct _rights;struct _class; D#endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _psb {#pragma __nomember_alignmentN struct _psb *psb$l_flink; /* Standard listhead forward link */N struct _psb *psb$l_blink; /* Standard listhead backward link */O unsigned short int psb$w_size; /* Standard structure si Dze, in bytes */] unsigned char psb$b_type; /* Standard type code for PSB (DYN$C_SECURITY) */` unsigned char psb$b_subtype; /* Standard subtype code (DYN$C_SECURITY_PSB) */ __union {N unsigned int psb$l_debug_data_1; /* First of 2 debug data cells */S struct _psb *psb$l_debug_flink; /* Forward link to previous PSB (DEBUG) */ } psb$r_debug_1_overlay; __union {N unsigned int psb$l_debug_data_2; /* Second of 2 debug Ddata cells */S struct _psb *psb$l_debug_blink; /* Backward link to previous PSB (DEBUG) */ } psb$r_debug_2_overlay;\ unsigned int psb$l_debug_pid; /* PID of process that allocated this PSB (DEBUG) */ __union {V unsigned int psb$l_flags; /* Every structure needs a set of flags :-) */ __struct {N unsigned psb$v_permanent : 1; /* This PSB is permanent */N unsigned psb$v_secaudit : 1; /* Security audit MandatoryD */_ unsigned psb$v_fill_2 : 1; /* available for reuse (old DELETE_PENDING location) */N unsigned psb$v_clone : 1; /* PSB created via Clone operation. */N unsigned psb$v_rms : 1; /* PSB created in RMS */N unsigned psb$v_io : 1; /* PSB created in IO */N unsigned psb$v_tcb : 1; /* This PSB is part of the TCB */S unsigned psb$v_debit : 1; /* Debit BYTLM/BYTCNT for this strucDture */` unsigned psb$v_reserve : 1; /* Dummy PSB ("Runt") to hold persona index in server */Q unsigned psb$v_delegate : 1; /* PSB created via Delegate operation */i unsigned psb$v_create_user : 1; /* PSB created via $PERSONA_CREATE with username parameter */m unsigned psb$v_create_tlv : 1; /* PSB created via $PERSONA_CREATE with profile (tlv) parameter */k unsigned psb$v_create_itmlst : 1; /* PSB created via $PERSONA_CREATE with itemlist D parameter */+ unsigned psb$v_flags_rsvd : 16;[ unsigned psb$v_delete_pending : 1; /* Request for persona delete pending ... */_ unsigned psb$v_dp_processing : 1; /* PSB in process od DELETE_PENDING processing */\ unsigned psb$v_deallocated : 1; /* PSB has been deallocated (pool monitoring) */ } psb$r_fill_1_; } psb$r_fill_0_;N unsigned int psb$l_persona_id; /* Persona id assigned to this PSB */_ unsigned int psb$l D_refcount; /* Number of attached execution contexts to this PSB */V unsigned int psb$o_uid [4]; /* Universal identifier assigned to persona */#if defined(__VAXC) char psb$t_clone_region[];#else%#define psb$t_clone_region psb$l_mode"#endif /* #if defined(__VAXC) */e unsigned int psb$l_mode; /* Access level for this PSB (User,Supervisor,Exec,Kernel) */N/* End of the reserve PSB (runt). */N char psb$t_usern Dame [32]; /* Persona Username */N char psb$t_account [32]; /* Persona Account name */N unsigned int psb$l_noaudit; /* Non-zero implies no audit status */ __union {N unsigned int psb$l_uic; /* UIC of persona */ __struct {N unsigned short int psb$w_mem; /* Member number in UIC */N unsigned short int psb$w_grp; /* Group number in UIC */ D } psb$r_fill_3_; } psb$r_fill_2_;N/* UIC_FLAGS must always follow UIC */N unsigned int psb$l_uic_flags; /* UIC identifier flags longword */N/* (should always be zero) */N unsigned int psb$l_concealed_count; /* Hidden reference tracking */N void *psb$l_off_process_ptr; /* Ptr to off_process ringbuffer */N int psb$l_reserved; /* Used for quadwo Drd alignment */ __union {N unsigned __int64 psb$q_doi; /* Domain Of Interpretation */ __struct {# unsigned int psb$l_doi;' unsigned int psb$l_doi_pid; } psb$r_fill_5_; } psb$r_fill_4_;N PRVDEF psb$q_authpriv; /* Allowable privileges */N PRVDEF psb$q_permpriv; /* Permanent privileges */N PRVDEF psb$q_workpriv; /* Current working privileges D */N PRVDEF psb$q_image_workpriv; /* Image working privileges */ __union {[ unsigned int psb$l_rights_enabled; /* Bitmap of enabled/disabled rights pointers */ __struct {N unsigned psb$v_persona : 1; /* in rights array */N unsigned psb$v_system : 1; /* */N unsigned psb$v_installed : 1; /* */N unsigned psb$v_subsystem : 1; /* D */N unsigned psb$v_temporary : 1; /* */N unsigned psb$v_fill_1 : 4; /* */X unsigned psb$v_chkpro : 1; /* Rights slot reserved for CHKPRO processing */' unsigned psb$v_fill_8_ : 6; } psb$r_fill_7_; } psb$r_fill_6_;_ struct _rights *psb$ar_authrights [10]; /* Array of pointers to authorized rights chains */W struct _rights *psb$Ear_rights [10]; /* Array of pointers to active rights chains */R struct _class *psb$ar_class; /* Pointer to classification data block */N unsigned int psb$l_posix_uid; /* POSIX UID field */N unsigned int psb$l_posix_gid; /* POSIX GID field */k unsigned int psb$l_pxb_count; /* Number of extensions registered when this persona is created. */j void *psb$ar_pxb_array; /* Pointer to array of pointers to this PSB's Eextension blocks. */X unsigned __int64 psb$q_pxb_mutex; /* Mutex to sych access to this PSB's fields. */ } PSB; #if !defined(__VAXC)C#define psb$l_debug_data_1 psb$r_debug_1_overlay.psb$l_debug_data_1A#define psb$l_debug_flink psb$r_debug_1_overlay.psb$l_debug_flinkC#define psb$l_debug_data_2 psb$r_debug_2_overlay.psb$l_debug_data_2A#define psb$l_debug_blink psb$r_debug_2_overlay.psb$l_debug_blink-#define psb$l_flags psb$r_fill_0_.psb$l_flagsC#define psb$v_permanent psb$r_fi Ell_0_.psb$r_fill_1_.psb$v_permanentA#define psb$v_secaudit psb$r_fill_0_.psb$r_fill_1_.psb$v_secaudit;#define psb$v_clone psb$r_fill_0_.psb$r_fill_1_.psb$v_clone7#define psb$v_rms psb$r_fill_0_.psb$r_fill_1_.psb$v_rms5#define psb$v_io psb$r_fill_0_.psb$r_fill_1_.psb$v_io7#define psb$v_tcb psb$r_fill_0_.psb$r_fill_1_.psb$v_tcb;#define psb$v_debit psb$r_fill_0_.psb$r_fill_1_.psb$v_debit?#define psb$v_reserve psb$r_fill_0_.psb$r_fill_1_.psb$v_reserveA#define psb$v_delegate psb$r_fill_0_.pEsb$r_fill_1_.psb$v_delegateG#define psb$v_create_user psb$r_fill_0_.psb$r_fill_1_.psb$v_create_userE#define psb$v_create_tlv psb$r_fill_0_.psb$r_fill_1_.psb$v_create_tlvK#define psb$v_create_itmlst psb$r_fill_0_.psb$r_fill_1_.psb$v_create_itmlstM#define psb$v_delete_pending psb$r_fill_0_.psb$r_fill_1_.psb$v_delete_pendingK#define psb$v_dp_processing psb$r_fill_0_.psb$r_fill_1_.psb$v_dp_processingG#define psb$v_deallocated psb$r_fill_0_.psb$r_fill_1_.psb$v_deallocated)#define psb$l_uic ps Eb$r_fill_2_.psb$l_uic7#define psb$w_mem psb$r_fill_2_.psb$r_fill_3_.psb$w_mem7#define psb$w_grp psb$r_fill_2_.psb$r_fill_3_.psb$w_grp)#define psb$q_doi psb$r_fill_4_.psb$q_doi7#define psb$l_doi psb$r_fill_4_.psb$r_fill_5_.psb$l_doi?#define psb$l_doi_pid psb$r_fill_4_.psb$r_fill_5_.psb$l_doi_pid?#define psb$l_rights_enabled psb$r_fill_6_.psb$l_rights_enabled?#define psb$v_persona psb$r_fill_6_.psb$r_fill_7_.psb$v_persona=#define psb$v_system psb$r_fill_6_.psb$r_fill_7_.psb$v_systemC#d Eefine psb$v_installed psb$r_fill_6_.psb$r_fill_7_.psb$v_installedC#define psb$v_subsystem psb$r_fill_6_.psb$r_fill_7_.psb$v_subsystemC#define psb$v_temporary psb$r_fill_6_.psb$r_fill_7_.psb$v_temporary=#define psb$v_chkpro psb$r_fill_6_.psb$r_fill_7_.psb$v_chkpro"#endif /* #if !defined(__VAXC) */ N#define PSB$K_LENGTH 296 /* Length of PSB structure */   9#ifdef __cplusplus /* Define structure prototypes */ struct _psa; #endif /* #ifdef __cplusplu Es */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _psb_array {#pragma __nomember_alignmentN struct _psa *psa$l_flink; /* Standard listhead forward link */N struct _psa *psa$l_blink; /* Standard listhead backward link */O unsigned short int psa$w_size; /* Standard structure size, in bytes */] Eunsigned char psa$b_type; /* Standard type code for PSB (DYN$C_SECURITY) */` unsigned char psa$b_subtype; /* Standard subtype code (DYN$C_SECURITY_PSB) */N int psa$l_reserved; /* Keep array quad aligned ... */#if defined(__VAXC) char psa$t_elements[];#elseU/* Warning: empty char[] member for psa$t_elements at end of structure not created */"#endif /* #if defined(__VAXC) */ } PSB_ARRAY; N/* E */N/* The following constants are used in TLV conversion of PSB structures */N/* The first 6 items are positioned for backward compatibility the */N/* older CHP$_ item codes and should not be changed. */N/* */N/* The ADD_RIGHTS and ADD_AUTHRIGHTS codes below should not be used. They */N/* are here to be compatible with the item codes found in  EISSDEF. */N/* */N/* Any changes to the list below should also be reflected in the */N/* module [STARLET] ISSDEF.SDL */N#define PSB$_TLV_FLAGS 1 /* 1 */f#define PSB$_TLV_ARBFLAGS 2 /* 2 CHP$_FLAGS Placeholder to avoid conflict with ARB TLVs */f#define PSB$_TLV_ARBPRIV 3 /* 3 CHP$_PRIVS Plac Eeholder to avoid conflict with ARB TLVs */N#define PSB$_TLV_MODE 4 /* 4 */N#define PSB$_TLV_WORKCLASS 5 /* 5 */N#define PSB$_TLV_RIGHTS 6 /* 6 */N/* 7 ISS$_ADD_RIGHTS placeholder */N/* 8 ISS$_ADD_AUTHRIGHTS placeholder */N#define PSB$_TLV_USERNAME 9 /* 9  E */N#define PSB$_TLV_ACCOUNT 10 /* 10 */N#define PSB$_TLV_NOAUDIT 11 /* 11 */N#define PSB$_TLV_AUTHPRIV 12 /* 12 */N#define PSB$_TLV_PERMPRIV 13 /* 13 */N#define PSB$_TLV_IMAGE_WORKPRIV 14 /* 14 */N#define PSB$_TLV_RIGHTS_ENABLED 15 /* 15 */N#define  EPSB$_TLV_AUTHRIGHTS 16 /* 16 */N#define PSB$_TLV_MINCLASS 17 /* 17 */N#define PSB$_TLV_MAXCLASS 18 /* 18 */N#define PSB$_TLV_UID 19 /* 19 */N/* 20 */N/* 21 */N#define PSB$_TLV_UIC 22  E /* 22 */N#define PSB$_TLV_WORKPRIV 23 /* 23 */N#define PSB$_TLV_POSIX_UID 24 /* 24 */N#define PSB$_TLV_POSIX_GID 25 /* 25 */#define PSB$_TLV_MIN_CODE 1#define PSB$_TLV_MAX_CODE 25N/* */^/* The following PSB RingBuffer structure is employed for recording recent perso Ena activity */N/* for a given process. P1 storage is allocated during process creation for */N/* this purpose. */N/* */N/* */N/* */#define PSBRB$M_CLONE_PSB 0x1##define PSBRB$M_DEREFERENCE_PSB 0x2"#define PSBRB$M_DELEETE_PERSONA 0x4#define PSBRB$M_FREE_PSB 0x8"#define PSBRB$M_REFERENCE_PSB 0x10##define PSBRB$M_ASSUME_PERSONA 0x20 #define PSBRB$M_SET_NATURAL 0x40 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _psbrb {#pragma __nomember_alignmentN struct _psb *psbrb$l_flink; /* Standard listhead forward link */N struct _psb *psbrbE$l_blink; /* Standard listhead backward link */O unsigned short int psbrb$w_size; /* Standard structure size, in bytes */] unsigned char psbrb$b_type; /* Standard type code for PSB (DYN$C_SECURITY) */` unsigned char psbrb$b_subtype; /* Standard subtype code (DYN$C_SECURITY_PRB) */O unsigned int psbrb$l_max_index; /* Maximum number of records in ring */a unsigned int psbrb$l_current_index; /* Index of nex record to be written in the RingBu Effer */#if defined(__VAXC) char psbrb$t_records[];#else'#define psbrb$t_records psbrb$r_fill_9_"#endif /* #if defined(__VAXC) */ __union {c unsigned int psbrb$l_function; /* Define which support routine is reporting this record */ __struct {N unsigned psbrb$v_clone_psb : 1; /* NSA$CLONE_PSB */N unsigned psbrb$v_dereference_psb : 1; /* NSA$DEREFERENCE_PSB */N unsigned psbrb$v_delete_persona : 1; /* NSA$DE ELETE_PERSONA */N unsigned psbrb$v_free_psb : 1; /* NSA$FREE_PSB */N unsigned psbrb$v_reference_psb : 1; /* NSA$REFERENCE_PSB */N unsigned psbrb$v_assume_persona : 1; /* NSA$ASSUME_PERSONA */N unsigned psbrb$v_set_natural : 1; /* NSA$SET_NATURAL */* unsigned psbrb$v_fill_11_ : 1; } psbrb$r_fill_10_; } psbrb$r_fill_9_;^ unsigned int psbrb$l_psb; /* Address of PSB Ebeing acted upon by the function */T unsigned int psbrb$l_refcnt; /* Current reference count the above PSB */N unsigned int psbrb$l_flags; /* Contents of PSB flags */N unsigned int psbrb$l_mode; /* Access mode of current PSB */ __union {X unsigned __int64 psbrb$q_pc; /* Address from where the function was called */ __struct {$ unsigned int psbrb$l_pc;) unsigned int psbrb$l_pc_high; E} psbrb$r_pc_longs; } psbrb$r_pc_overlay;O unsigned int psbrb$l_psl; /* PSL at the time of the operation */P unsigned int psbrb$l_uthread_id; /* Current active DECthread (if any) */N unsigned int psbrb$l_ktb; /* Current KTB */N unsigned int psbrb$l_cpu; /* CPU ID from current KTB */N/* Function specific information */N unsigned int psbrb$l_aux_1; /* $Assu Eme = previous PSB */N/* $Clone = PSB being created */T unsigned int psbrb$l_aux_2; /* $Assume = previous PSB reference count */N unsigned int psbrb$l_aux_3; /* debug_data_1 */N unsigned int psbrb$l_aux_4; /* debug_data_2 */N unsigned int psbrb$l_spare; /* spare - */ char psbrb$b_fill_12_ [4]; } PSBRB; #if !defined(__VAXEC)9#define psbrb$l_function psbrb$r_fill_9_.psbrb$l_functionL#define psbrb$v_clone_psb psbrb$r_fill_9_.psbrb$r_fill_10_.psbrb$v_clone_psbX#define psbrb$v_dereference_psb psbrb$r_fill_9_.psbrb$r_fill_10_.psbrb$v_dereference_psbV#define psbrb$v_delete_persona psbrb$r_fill_9_.psbrb$r_fill_10_.psbrb$v_delete_personaJ#define psbrb$v_free_psb psbrb$r_fill_9_.psbrb$r_fill_10_.psbrb$v_free_psbT#define psbrb$v_reference_psb psbrb$r_fill_9_.psbrb$r_fill_10_.psbrb$v_reference_psbV#define psbrb$v_assume_p Eersona psbrb$r_fill_9_.psbrb$r_fill_10_.psbrb$v_assume_personaP#define psbrb$v_set_natural psbrb$r_fill_9_.psbrb$r_fill_10_.psbrb$v_set_natural0#define psbrb$q_pc psbrb$r_pc_overlay.psbrb$q_pcA#define psbrb$l_pc psbrb$r_pc_overlay.psbrb$r_pc_longs.psbrb$l_pcK#define psbrb$l_pc_high psbrb$r_pc_overlay.psbrb$r_pc_longs.psbrb$l_pc_high"#endif /* #if !defined(__VAXC) */ )#define PSBRB$K_RINGBUFFER_RECORD_SIZE 64'#define PSBRB$K_RINGBUFFER_RECORDS 1000%#define PSBRB$K_RINGBUFFER_SIZE 64020 E # ifdef __INITIAL_POINTER_SIZEM# pragma __required_pointer_size __save /* Save current pointer size */_# pragma __required_pointer_size 32 /* And set ptr size default to 32-bit pointers */R typedef struct _psb * PSB_ps; /* 32-bit pointer signed to a PSB */S# pragma __required_pointer_size __restore /* Return to previous pointer size */# elsea typedef signed __int32 PSB_ps; /* Same size as a 32-bit pointer signed to a PSB */# endifE $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PSBDEF_LOADED */ ww0A[UM/***************************************************************************/M/** E **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, EINC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*******************************************E********************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */K/* Source: 01-NOV-2019 17:23:16 $1$DGA8345:[LIB_H.SRC]PSCANCTXDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PSCANCTXDEF ***/#ifndef __PSCANCTXDEF_LOADED#d Eefine __PSCANCTXDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __Eunknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */R/* The PSCANCTX$ structure is exchanged with E remote nodes. Any updates to this */N/* structure must take mixed-version operation into account. */N/* */#define PSCANCTX$M_SUPER 0x1#define PSCANCTX$M_CSID_VEC 0x2#define PSCANCTX$M_LOCKED 0x4!#define PSCANCTX$M_MULTI_NODE 0x8#define PSCANCTX$M_BUSY 0x10#define PSCANCTX$M_RELOCK 0x20#define PSCANCTX$M_THREAD 0x40'#define PSCANCTX$M_NEED_THREAD_CAP 0x80(#define PSCANCTX$M_SCHED_CLASS_CAP 0x1 E00N#define PSCANCTX$K_LENGTH 72 /* length of data structure */N#define PSCANCTX$M_THREAD_ITEM 1073741824 /* item code references a node */N#define PSCANCTX$V_THREAD_ITEM 30 /* item code references a node */N#define PSCANCTX$M_NODE_ITEM -2147483648 /* item code references a node */N#define PSCANCTX$V_NODE_ITEM 31 /* item code references a node */N#define PSCANCTX$S_$PSCANCTXDEF 72 /* Old size name - synonym */  9#ifdef __cplus !Eplus /* Define structure prototypes */struct _cwpssrv; #endif /* #ifdef __cplusplus */ typedef struct _pscanctx {N void *pscanctx$l_flink; /* forward link */N void *pscanctx$l_blink; /* back link */N unsigned short int pscanctx$w_size; /* size of structure */N unsigned char pscanctx$b_type; /* structure type code */N unsigned char pscanctx$b_subtype; /* structure sub "Etype */N unsigned short int pscanctx$w_maj_vers; /* incompatible level */N unsigned short int pscanctx$w_min_vers; /* upwards-compatible level */ __union {& unsigned int pscanctx$l_flags; __struct {O unsigned pscanctx$v_super : 1; /* allocated from supervisor mode */N unsigned pscanctx$v_csid_vec : 1; /* csid vector is present */N unsigned pscanctx$v_locked : 1; /* cell is locked in memory */T #E unsigned pscanctx$v_multi_node : 1; /* scan is for more than one node */N unsigned pscanctx$v_busy : 1; /* scan in progress on this block */R unsigned pscanctx$v_relock : 1; /* ignore BUSY flag, allow a "lock" */\ unsigned pscanctx$v_thread : 1; /* PSCAN$M_THREAD specified - include threads */b unsigned pscanctx$v_need_thread_cap : 1; /* remote node needs kernel thread support */e unsigned pscanctx$v_sched_class_cap : 1; /* remote n $Eode needs class scheduling support */, unsigned pscanctx$v_fill_2_ : 7;! } pscanctx$r_fill_1_; } pscanctx$r_fill_0_;N unsigned int pscanctx$l_cur_csid; /* CSID for scan in progress */O unsigned int pscanctx$l_cur_ipid; /* initial IPID for scan in progress */O unsigned int pscanctx$l_next_ipid; /* updated IPID for scan in progress */N unsigned int pscanctx$l_cur_epid; /* EPID for scan in progress */N unsigned short int pscan%Ectx$w_itmlstoff; /* offset to item list */N unsigned short int pscanctx$w_bufferoff; /* offset to buffer area */N unsigned short int pscanctx$w_csidoff; /* offset to csid vector */N unsigned short int pscanctx$w_csididx; /* index of current csid */N unsigned int pscanctx$l_orig_ctx; /* original pscanctx record */N struct _cwpssrv *pscanctx$l_cwpssrv; /* address of CWPSSRV structure */N void *pscanctx$l_jpibufadr; /* address of &E$GETJPI buffer */N unsigned short int pscanctx$w_seqnum; /* sequence number */N unsigned char pscanctx$b_acmode; /* access mode of original call */N unsigned char pscanctx$b_spare0; /* just a little extra */N unsigned int pscanctx$l_spare1; /* just a little extra */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma 'E__nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *pscanctx$pq_svapte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else) unsigned __int64 pscanctx$pq_svapte_sva;#endif } PSCANCTX; #if !defined(__VAXC)<#define pscanctx$l_flags pscanctx$r_fill_0_.pscanctx$l_flagsO#define pscanctx$v_super pscanctx$r_fill_0_.pscanctx$r(E_fill_1_.pscanctx$v_superU#define pscanctx$v_csid_vec pscanctx$r_fill_0_.pscanctx$r_fill_1_.pscanctx$v_csid_vecQ#define pscanctx$v_locked pscanctx$r_fill_0_.pscanctx$r_fill_1_.pscanctx$v_lockedY#define pscanctx$v_multi_node pscanctx$r_fill_0_.pscanctx$r_fill_1_.pscanctx$v_multi_nodeM#define pscanctx$v_busy pscanctx$r_fill_0_.pscanctx$r_fill_1_.pscanctx$v_busyQ#define pscanctx$v_relock pscanctx$r_fill_0_.pscanctx$r_fill_1_.pscanctx$v_relockQ#define pscanctx$v_thread pscanctx$r_fill_0_.pscan)Ectx$r_fill_1_.pscanctx$v_threadc#define pscanctx$v_need_thread_cap pscanctx$r_fill_0_.pscanctx$r_fill_1_.pscanctx$v_need_thread_capc#define pscanctx$v_sched_class_cap pscanctx$r_fill_0_.pscanctx$r_fill_1_.pscanctx$v_sched_class_cap"#endif /* #if !defined(__VAXC) */ N/* */R/* The PSCANBUF$ structure is exchanged with remote nodes. Any updates to this */N/* structure must take mixed-version operation into account. *E */N/* */#define PSCANBUF$M_SPARE0 0x1N#define PSCANBUF$K_LENGTH 32 /* length of data structure */N#define PSCANBUF$S_$PSCANBUFDEF 32 /* Old size name - synonym */ #pragma __nomember_alignmenttypedef struct _pscanbuf {N unsigned int pscanbuf$l_buflen; /* length of data area */N unsigned int pscanbuf$l_spare0; /* spare0 +E*/N unsigned short int pscanbuf$w_size; /* size of structure */N unsigned char pscanbuf$b_type; /* structure type code */N unsigned char pscanbuf$b_subtype; /* structure subtype */N unsigned short int pscanbuf$w_maj_vers; /* incompatible level */N unsigned short int pscanbuf$w_min_vers; /* upwards-compatible level */ __union {& unsigned int pscanbuf$l_flags; __struct {N unsigned psc ,Eanbuf$v_spare0 : 1; /* filler */, unsigned pscanbuf$v_fill_5_ : 7;! } pscanbuf$r_fill_4_; } pscanbuf$r_fill_3_;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *pscanbuf$l_itmlstadr; /* address of copy of JPI item list */N unsigned int pscanbuf$l_buffer_offset; /* offset to start of buffe -Er */N unsigned int pscanbuf$l_free_offset; /* offset to next free byte */ } PSCANBUF; #if !defined(__VAXC)<#define pscanbuf$l_flags pscanbuf$r_fill_3_.pscanbuf$l_flagsQ#define pscanbuf$v_spare0 pscanbuf$r_fill_3_.pscanbuf$r_fill_4_.pscanbuf$v_spare0"#endif /* #if !defined(__VAXC) */ N/* */Q/* The PSCANITM$ structure is a local structure. If modified, you do not need */Q/* to take mixed-versi .Eon operation into account, however you must be sure that */P/* all modules and images which reference the structure are updated together. */N/* */N#define PSCANITM$K_LENGTH 12 /* length of data structure */N#define PSCANITM$S_$PSCANITMDEF 13 /* Old size name - synonym */ typedef struct _pscanitm {N unsigned int pscanitm$l_alloc_length; /* allocated length */N unsign /Eed int pscanitm$l_itmlen; /* length of item list */N unsigned short int pscanitm$w_size; /* size of header */N unsigned char pscanitm$b_type; /* structure type code */N unsigned char pscanitm$b_subtype; /* structure subtype */N unsigned char pscanitm$b_itmlst; /* start of the item list */ } PSCANITM; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr0E size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __PSCANCTXDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** li1Ecensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software license2Ed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************* 3E***********************************************************************/=/* Created: 7-Oct-2024 15:23:38 by OpenVMS SDL V3.7 */F/* Source: 18-AUG-2005 03:59:32 $1$DGA8345:[LIB_H.SRC]PSHDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PSHDEF ***/#ifndef __PSHDEF_LOADED#define __PSHDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragm4Ea __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ..5E.#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  #include #include N/* */N/* Pshared Data Tag Structure */N/* 6E */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pshared_data {#pragma __nomember_alignmentN unsigned char pshdat$b_type; /* data tag type */N unsigned char pshdat$b_op; /* data tag operation */N unsigned short int pshdat$w_offset; /* 7E offset */N unsigned int pshdat$l_modifiers; /* modifiers */ } PSHARED_DATA;N/* */N/* Pshared Lock Structure */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_a 8Elignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pshared_lock {#pragma __nomember_alignment __union {N __int64 pshlck$q_lock_state; /* lock state */ __struct {N unsigned pshlck$v_mutex_lock : 1; /* mutex lock bit */N unsigned pshlck$v_mutex_waiters : 31; /* mutex waiters count */N unsigned pshlck$v_mutex_waiters_high : 32; /* not used */" } pshl 9Eck$r_mutex_bits; __struct {N unsigned pshlck$v_write_lock : 1; /* write lock bit */N unsigned pshlck$v_write_waiters : 31; /* number of writers */R unsigned pshlck$v_readers_waiting : 1; /* number of readers waiting */N unsigned pshlck$v_readers : 31; /* number of readers */ } pshlck$r_rwl_bits;& } pshlck$r_lock_state_overlay; } PSHARED_LOCK; #if !defined(__VAXC)K#define pshlck$q_loc:Ek_state pshlck$r_lock_state_overlay.pshlck$q_lock_state_#define pshlck$v_mutex_lock pshlck$r_lock_state_overlay.pshlck$r_mutex_bits.pshlck$v_mutex_locke#define pshlck$v_mutex_waiters pshlck$r_lock_state_overlay.pshlck$r_mutex_bits.pshlck$v_mutex_waiterso#define pshlck$v_mutex_waiters_high pshlck$r_lock_state_overlay.pshlck$r_mutex_bits.pshlck$v_mutex_waiters_high]#define pshlck$v_write_lock pshlck$r_lock_state_overlay.pshlck$r_rwl_bits.pshlck$v_write_lockc#define pshlck$v_write_waiters pshlc;Ek$r_lock_state_overlay.pshlck$r_rwl_bits.pshlck$v_write_waitersg#define pshlck$v_readers_waiting pshlck$r_lock_state_overlay.pshlck$r_rwl_bits.pshlck$v_readers_waitingW#define pshlck$v_readers pshlck$r_lock_state_overlay.pshlck$r_rwl_bits.pshlck$v_readers"#endif /* #if !defined(__VAXC) */ N/* */N/* Pshared State Structure */N/* E_quadword#else#pragma __nomember_alignment#endiftypedef struct _pshared_owner {#pragma __nomember_alignmentU int pshown$l_owner_pid; /* process identification (PID) of process */N int pshown$l_owner_type; /* owner type */N unsigned __int64 pshown$q_owner_id; /* thread environment block (TEB) */ } PSHARED_OWNER;N/* */N/* Pshared Global Structure ?E */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pshared_gbl {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long @E /* And set ptr size default to 64-bit pointers */U struct _pshared_gbl *pshgbl$q_flink; /* flink to next pshared global structure */#else! unsigned __int64 pshgbl$q_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Y struct _pshared_gbl *pshgbl$q_blink; /* blink to previous pshared global structure */#else! unsigned __int64 pshgbl$q_blink;#eAEndifT int pshgbl$l_pid; /* process identification of this process */N int pshgbl$l_imgcnt; /* image count for this process */\ unsigned __int64 pshgbl$q_start_va; /* starting VA of global section in process space */ } PSHARED_GBL;N/* */N/* Pshared Wait Structure */N/* BE */  9#ifdef __cplusplus /* Define structure prototypes */ struct _pcb;struct _pshared_timout;struct _pshared_master; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pshared_wait {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size CEpragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pshared_wait *pshwt$q_flink; /* flink to next wait structure */#else unsigned __int64 pshwt$q_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */O struct _pshared_wait *pshwt$q_blink; /* blink to previous wait structure */#els DEe unsigned __int64 pshwt$q_blink;#endifN int pshwt$l_type; /* wait type */N int pshwt$l_priority; /* thread priority */N int pshwt$l_pid; /* process or thread identification */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifT struct _pcb *pshwt$l_pcb; EE /* short pointer to process control block */N int pshwt$l_ctx; /* thread context pointer */N int pshwt$l_imgcnt; /* image count for this process */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */S struct _pshared_timout *pshwt$q_timeout_ele; /* pointer to timeout structure */#else& unsigned __int64 pshwt$ FEq_timeout_ele;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pshared_master *pshwt$q_master; /* pointer to pshared master */#else! unsigned __int64 pshwt$q_master;#endif } PSHARED_WAIT;N/* */N/* Pshared Timout Structure GE */N/* */  9#ifdef __cplusplus /* Define structure prototypes */struct _pshared_object;struct _pshared_master; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _pshared_timout {#pragma __nomember_alignmentR#ifdef HE __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Q struct _pshared_timout *pshtim$q_flink; /* flink to next timeout structure */#else! unsigned __int64 pshtim$q_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */U struct _pshared_timo IEut *pshtim$q_blink; /* blink to previous timeout structure */#else! unsigned __int64 pshtim$q_blink;#endifN int pshtim$l_type; /* timeout type */N int pshtim$l_spare1; /* spare field */N unsigned __int64 pshtim$q_timeout; /* timeout value for this structure */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size defau JElt to 64-bit pointers */Z struct _pshared_object *pshtim$q_object; /* pointer to pshared object (CV or mutex) */#else" unsigned __int64 pshtim$q_object;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pshared_wait *pshtim$q_wait_ele; /* pointer to wait structure */#else$ unsigned __int64 pshtim$q_wait_ele;#endifR#ifdef __INITIAL_POINTER_S KEIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pshared_master *pshtim$q_master; /* pointer to pshared master */#else" unsigned __int64 pshtim$q_master;#endif } PSHARED_TIMOUT;N/* */N/* Pshared Object Structure */N/* LE */  9#ifdef __cplusplus /* Define structure prototypes */struct _pshared_master; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _pshared_object {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported ME*/Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pshared_object *pshobj$q_flink; /* flink to next pshared object */#else! unsigned __int64 pshobj$q_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */R struct _pshared_object *pshobj$q_blink; /* blink to previous pshared object */#else! unsigned NE__int64 pshobj$q_blink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pshared_state *pshobj$q_state; /* state of pshared object */#else! unsigned __int64 pshobj$q_state;#endifO int pshobj$l_type; /* pshared object type (CV or mutex) */N int pshobj$l_status; /* status of this pshared object */N OE int pshobj$l_waiters; /* count number of waiters */N int pshobj$l_recc; /* recursion depth */N unsigned __int64 pshobj$q_name; /* pointer to name */N PSHARED_OWNER pshobj$r_owner; /* embedded owner structure */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers PE*/^ struct _pshared_object *pshobj$q_cv_friend; /* pointer to associated pshared object */#else% unsigned __int64 pshobj$q_cv_friend;#endifN unsigned __int64 pshobj$q_obj_ref; /* reference counter */# } pshobj$r_ref_obj_overlay;N int pshobj$l_abandoned; /* abandoned flag */O int pshobj$l_gstx; /* global section table index (GSTX) */Y unsigned __int64 pshobj$q_gstx_offset; /* offset within global sec QEtion table (GST) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */e struct _pshared_wait *pshobj$q_wait_flink; /* flink to queue of waiters on this pshared object */#else& unsigned __int64 pshobj$q_wait_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size def REault to 64-bit pointers */e struct _pshared_wait *pshobj$q_wait_blink; /* blink to queue of waiters on this pshared object */#else& unsigned __int64 pshobj$q_wait_blink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pshared_master *pshobj$q_master; /* pointer to pshared master */#else" unsigned __int64 pshobj$q_master;#endif } PSHA SERED_OBJECT; #if !defined(__VAXC)F#define pshobj$q_cv_friend pshobj$r_ref_obj_overlay.pshobj$q_cv_friendB#define pshobj$q_obj_ref pshobj$r_ref_obj_overlay.pshobj$q_obj_ref"#endif /* #if !defined(__VAXC) */ N/* */N/* Pshared Hash Structure */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !d TEefined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pshared_hash {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pshared_object *pshhsh$q_flink; /* flink to pshared object */#else! unsigned __int64 pshhsh$q_flink UE;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pshared_object *pshhsh$q_blink; /* blink to pshared object */#else! unsigned __int64 pshhsh$q_blink;#endif } PSHARED_HASH;N/* */N/* Pshared Master Structure */N/* VE */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _pshared_master {#pragma __nomember_alignmentN int pshmas$l_status; /* pshared master status */N int pshmas$l_gstx; /* global section table index */N unsigned WE short int pshmas$w_mbo; /* must-be-one field */N unsigned char pshmas$b_type; /* structure type (DYN$C_PSH) */O unsigned char pshmas$b_subtype; /* structure subtype (DYN$C_PSH_MAS) */N int pshmas$l_obj_count; /* total number of pshared objects */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __XEint64 pshmas$q_size; /* size */#pragma __nomember_alignmentN int pshmas$l_cv_count; /* number of pshared CV's */N int pshmas$l_mutex_count; /* number of pshared mutexes */f PZ_REGION pshmas$r_poolzone; /* embedded poolzone region structure (includes 1 poolzone) */[ PZ_ZONE pshmas$r_zone [2]; /* embedded additional poolzone structures (two) */N TQE pshmas$r_tqe; /* e YEmbedded TQE structure */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */S struct _pshared_object *pshmas$q_obj_flink; /* flink to pshared object queue */#else% unsigned __int64 pshmas$q_obj_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default ZE to 64-bit pointers */S struct _pshared_object *pshmas$q_obj_blink; /* blink to pshared object queue */#else% unsigned __int64 pshmas$q_obj_blink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */O struct _pshared_timout *pshmas$q_timout_flink; /* flink to timeout queue */#else( unsigned __int64 pshmas$q_timout_flink;#endifR#ifdef __INITIAL_POINTER [E_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */O struct _pshared_timout *pshmas$q_timout_blink; /* blink to timeout queue */#else( unsigned __int64 pshmas$q_timout_blink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */^ struct _pshared_gbl *pshmas$q_gbl_ \Eflink; /* flink to queue of pshared global structures */#else% unsigned __int64 pshmas$q_gbl_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */^ struct _pshared_gbl *pshmas$q_gbl_blink; /* blink to queue of pshared global structures */#else% unsigned __int64 pshmas$q_gbl_blink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pr ]Eagmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */S struct _pshared_hash *pshmas$q_obj_hash_tbl; /* pointer to object hash table */#else( unsigned __int64 pshmas$q_obj_hash_tbl;#endif } PSHARED_MASTER;N/* */N/* Pshared Array Structure */N/* ^E */  9#ifdef __cplusplus /* Define structure prototypes */ struct _spl; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pshared_array {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __ _Elong /* And set ptr size default to 64-bit pointers */[ struct _pshared_master *pshary$q_master; /* long pointer to pshared master structure */#else" unsigned __int64 pshary$q_master;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifY struct _spl *pshary$l_spinlock; /* short pointer to dynamic spinlock structure */N int pshary$l_spare; `E /* spare field */ } PSHARED_ARRAY;N/* */N/* Pshared Constant Definitions */N/* */#define PSH$C_BAD 0#define PSH$C_MUTEX 1#define PSH$C_CV 2#define PSH$C_RWL 3#define PSH$C_STATE_BAD 0#define PSH$C_STATE_ACTIVE 1#define PSH$C_STATE_DELETING 2#define PSaEH$C_THREAD_AWAKENED 0"#define PSH$C_THREAD_INTERRUPTED 1'#define PSH$C_THREAD_SHOULD_TERMINATE 2 #define PSH$C_THREAD_TIMED_OUT 3#define PSH$C_THREAD_RESTART 4$#define PSH$C_THREAD_FIRST_ATTEMPT 5#define PSH$C_HOLDER_BAD 0#define PSH$C_HOLDER_MUTEX 1#define PSH$C_HOLDER_READ 2#define PSH$C_HOLDER_WRITE 3 #define PSH$C_HOLDER_MUTEXWAIT 4 #define PSH$C_HOLDER_WRITEWAIT 5#define PSH$C_HOLDER_CONDWAIT 6#define PSH$C_RWM_LOCK 0#define PSH$C_RWM_UNLOCK 0#define PSH$C_RWM_TRY 1bE#define PSH$C_RWM_READ 2#define PSH$C_RWM_WRITE 4#define PSH$C_RWM_FORCE 8#define PSH$C_CV_WAIT 0#define PSH$C_CV_SIGNAL 0#define PSH$C_CV_BROADCAST 1#define PSH$C_MOD_ABSTIME 1#define PSH$C_MOD_FASTPATH 2#define PSH$C_MOD_RECURSIVE 4#define PSH$C_MOD_ERRORCHECK 8##define PSH$C_OBJ_HASH_ENTRIES 1024 #define PSH$M_OBJ_HASH_MASK 1023 &#pragma __required_pointer_size __save&#pragma __required_pointer_size __longWtypedef PSHARED_DATA *PSHARED_DATA_PQ; /* long pointer to cEa pshared data structure */Wtypedef PSHARED_LOCK *PSHARED_LOCK_PQ; /* long pointer to a pshared lock structure */Ztypedef PSHARED_STATE *PSHARED_STATE_PQ; /* long pointer to a pshared state structure */Ztypedef PSHARED_OWNER *PSHARED_OWNER_PQ; /* long pointer to a pshared owner structure */Wtypedef PSHARED_GBL *PSHARED_GBL_PQ; /* long pointer to a pshared global structure */Wtypedef PSHARED_WAIT *PSHARED_WAIT_PQ; /* long pointer to a pshared wait structure */^typedef PSHARED_TIMOUTdE *PSHARED_TIMOUT_PQ; /* long pointer to a pshared timeout structure */]typedef PSHARED_OBJECT *PSHARED_OBJECT_PQ; /* long pointer to a pshared object structure */Wtypedef PSHARED_HASH *PSHARED_HASH_PQ; /* long pointer to a pshared hash structure */]typedef PSHARED_MASTER *PSHARED_MASTER_PQ; /* long pointer to a pshared master structure */Ztypedef PSHARED_ARRAY *PSHARED_ARRAY_PQ; /* long pointer to a pshared array structure */)#pragma __required_pointer_size __restore $#pragma __eEmember_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PSHDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE fECONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAgEL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********************************************************** hE****************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */F/* Source: 10-FEB-1994 15:05:23 $1$DGA8345:[LIB_H.SRC]PSMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PSMDEF ***/#ifndef __PSMDEF_LOADED#define __PSMDEF_LOADED 1 G#p iEragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optionjEal_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* Print symbiont definitions */N/*+ */NkE/* Symbolic definitions for print symbionts. */N/* */I/* Public definition of various constants and data structures */I/* used by the standard VMS print symbiont, and by user modified */I/* print symbionts. */N/* */N/*- lE */N/* */I/* Service routine function codes */N/* */N/* */N/* IO functions */N/* mE */N#define PSM$K_CANCEL 1 /* Cancel pending operations */N#define PSM$K_CLOSE 2 /* Release resources */N#define PSM$K_FORMAT 3 /* Format buffer */N#define PSM$K_OPEN 4 /* Obtain resources */N#define PSM$K_READ 5 /* Read */N#define PSM$K_GET_KEY 6 /* Read record key */N#define PSM$K_nEPOSITION_TO_KEY 7 /* Read by record context */N#define PSM$K_REWIND 8 /* Rewind file */N#define PSM$K_WRITE 9 /* Write */S#define PSM$K_WRITE_NOFORMAT 10 /* Write with driver formatting disabled */N#define PSM$K_WRITE_SUPPRESSED 11 /* Write but suppress output */N/* */N/* Message notification functions oE */N/* */N#define PSM$K_PAUSE_TASK 12 /* STOP /QUEUE */N#define PSM$K_RESET_STREAM 13 /* STOP /QUEUE /RESET */N#define PSM$K_RESUME_TASK 14 /* START /QUEUE (when paused) */N#define PSM$K_START_STREAM 15 /* START /QUEUE (when stopped) */N#define PSM$K_START_TASK 16 /* (ofiginated by jopEb controller) */N#define PSM$K_STOP_TASK 17 /* STOP /QUEUE /ABORT or /REQUEUE */N#define PSM$K_STOP_STREAM 18 /* STOP /QUEUE /NEXT */N/* */I/* Replacement routines */N/* */N/* */N/* Task seqErvices -- where applicable the ordering of these literals */N/* determines the sequence of the corresponding service routines. */N/* */N/* */N/* Page services */N/* */Q#define PSM$K_PAGE_SETUP 1 rE /* Page setup - page setup modules */N#define PSM$K_PAGE_HEADER 2 /* Page separation - page headers */N/* */N/* Library module service */N/* */N#define PSM$K_LIBRARY_INPUT 3 /* Module services */N/* sE */N/* Filter services */N/* */N#define PSM$K_INPUT_FILTER 4 /* Filter service - input */Q#define PSM$K_MAIN_FORMAT 5 /* Format service - carriage control */N#define PSM$K_OUTPUT_FILTER 6 /* Filter service - output */N/* */NtE/* Output services */N/* */N#define PSM$K_OUTPUT 7 /* Main output routine */N/* */N/* General input services */N/* */O#define PSM$K_JOB_SETUP 8 uE /* Job setup - job reset modules */Q#define PSM$K_FORM_SETUP 9 /* Form setup - form setup modules */N#define PSM$K_JOB_FLAG 10 /* Job separation - flag page */N#define PSM$K_JOB_BURST 11 /* Job separation - burst page */Q#define PSM$K_FILE_SETUP 12 /* File setup - file setup modules */N#define PSM$K_FILE_FLAG 13 /* File separation - flag page */N#define PSM$K_FILE_BURST 14 /*vE File separation - burst page */L#define PSM$K_FILE_SETUP_2 15 /* File setup - top of form */N#define PSM$K_MAIN_INPUT 16 /* File service - main routine */N#define PSM$K_FILE_INFORMATION 17 /* Additional information print */N#define PSM$K_FILE_ERRORS 18 /* Errors during task processing */N#define PSM$K_FILE_TRAILER 19 /* File separation - trailer page */O#define PSM$K_JOB_RESET 20 /* Job reset - job reset mwEodules */N#define PSM$K_JOB_TRAILER 21 /* Job separation - trailer page */N#define PSM$K_JOB_COMPLETION 22 /* Job completion - top of form */N#define PSM$K_PAGE_FOOTER 23 /* Page separation - page footers */N#define PSM$K_MAX 24 /* MUST BE LAST */N/* */I/* Carriage control types */N/* xE */N#define PSM$K_CC_INTERNAL 1 /* - imbedded */N#define PSM$K_CC_IMPLIED 2 /* - implied */N#define PSM$K_CC_FORTRAN 3 /* - fortran */N#define PSM$K_CC_PRINT 4 /* - print file (PRN) */N#define PSM$K_CC_MAX 5 /* MUST BE LAST */#define PSM$M_LAT_PROTOCOL 0x1 Nstruct pyE5_flags { /* PSM$PRINT PaRAMETER 5 */ __union {! unsigned int psm$l_flags; __struct {N unsigned psm$v_lat_protocol : 1; /* */' unsigned psm$v_filler : 31; } psm$r_fill_1_; } psm$r_fill_0_; } ; #if !defined(__VAXC)-#define psm$l_flags psm$r_fill_0_.psm$l_flagsI#define psm$v_lat_protocol psm$r_fill_0_.psm$r_fill_1_.psm$v_lat_protocol"#endif /* #if !definezEd(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PSMDEF_LOADED */ wwR[UM/***************************************************************************/M/** {E **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/*|E* VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************}E************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */F/* Source: 06-FEB-2002 10:24:28 $1$DGA8345:[LIB_H.SRC]PSRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PSRDEF ***/#ifndef __PSRDEF_LOADED#d ~Eefine __PSRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknEown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Definitions for Processor Status Register E */N/* */#define PSR$M_USER_MASK 0x3F"#define PSR$M_SYSTEM_MASK 0xFFFFFF#define PSR$M_RV0 0x1#define PSR$M_BE 0x2#define PSR$M_UP 0x4#define PSR$M_AC 0x8#define PSR$M_MFL 0x10#define PSR$M_MFH 0x20#define PSR$M_MBZ0 0x1FC0#define PSR$M_IC 0x2000#define PSR$M_I 0x4000#define PSR$M_PK 0x8000#define PSR$M_MBZ1 0x10000#define PSR$M_DT 0x20000#define PSR$M_DFL 0x40000#defEine PSR$M_DFH 0x80000#define PSR$M_SP 0x100000#define PSR$M_PP 0x200000#define PSR$M_DI 0x400000#define PSR$M_SI 0x800000#define PSR$M_DB 0x1000000#define PSR$M_LP 0x2000000#define PSR$M_TB 0x4000000#define PSR$M_RT 0x8000000#define PSR$M_MBZ2 0xF0000000#define PSR$M_CPL 0x300000000#define PSR$M_IS 0x400000000#define PSR$M_MC 0x800000000#define PSR$M_IT 0x1000000000#define PSR$M_ID 0x2000000000#define PSR$M_DA 0x4000000000#define PSR$M_DD 0x8000000000#definEe PSR$M_SS 0x10000000000#define PSR$M_RI 0x60000000000#define PSR$M_ED 0x80000000000#define PSR$M_BN 0x100000000000#define PSR$M_IA 0x200000000000%#define PSR$M_MBZ3 0xFFFFC00000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _psr {#pragma __nomember_alignment __union {a unsigned __int64 psr$q_processor_staEtus; /* Processor status register - entire 64-bits */N unsigned psr$v_user_mask : 6; /* User mask bits PSR{5:0} */N unsigned psr$v_system_mask : 24; /* System mask bits PSR{23:0} */ __struct {N unsigned psr$v_rv0 : 1; /* 0 Reserved bit PSR{0:0} */N unsigned psr$v_be : 1; /* 1 Big-Endian */Q unsigned psr$v_up : 1; /* 2 User Performance monitor enabled */N unsigned psrE$v_ac : 1; /* 3 Alignment Check */` unsigned psr$v_mfl : 1; /* 4 Lower (f2..f31) floating-point registers written */b unsigned psr$v_mfh : 1; /* 5 Upper (f32..f127) floating-point registers written */P unsigned psr$v_mbz0 : 7; /* 6-12 Reserved bits PSR{12:6} (MBZ) */N unsigned psr$v_ic : 1; /* 13 Interruption Collection */N unsigned psr$v_i : 1; /* 14 Interrupt bit */N E unsigned psr$v_pk : 1; /* 15 Protection Key enable */N unsigned psr$v_mbz1 : 1; /* 16 Reserved bit PSR{16:16} (MBZ) */N unsigned psr$v_dt : 1; /* 17 Data address Translation */Y unsigned psr$v_dfl : 1; /* 18 Disabled Floating-point Low register set */Z unsigned psr$v_dfh : 1; /* 19 Disabled Floating-point High register set */N unsigned psr$v_sp : 1; /* 20 Secure Performance monitors */V Eunsigned psr$v_pp : 1; /* 21 Privileged Performance monitor enable */S unsigned psr$v_di : 1; /* 22 Disable Instruction set transition */N unsigned psr$v_si : 1; /* 23 Secure Interval timer */N unsigned psr$v_db : 1; /* 24 Debug Breakpoint fault */N unsigned psr$v_lp : 1; /* 25 Lower Privilege transfer trap */N unsigned psr$v_tb : 1; /* 26 Taken Branch trap */N unsigned psrE$v_rt : 1; /* 27 Register stack Translation */R unsigned psr$v_mbz2 : 4; /* 28-31 Reserved bits PSR{31:28} (MBZ) */N unsigned psr$v_cpl : 2; /* 32-33 Current Privilege Level */N unsigned psr$v_is : 1; /* 34 Instruction Set */N unsigned psr$v_mc : 1; /* 35 Machine Check abort mask */P unsigned psr$v_it : 1; /* 36 Instruction address Translation */P unsigned psr$v_id : 1; /* 3E7 Instruction Debug fault disable */Y unsigned psr$v_da : 1; /* 38 Disable Data Access and Dirty-bit faults */N unsigned psr$v_dd : 1; /* 39 Data Debug fault disable */N unsigned psr$v_ss : 1; /* 40 Single Step enable */N unsigned psr$v_ri : 2; /* 41-42 Restart Instruction */N unsigned psr$v_ed : 1; /* 43 Exception Deferral */N unsigned psr$v_bn : 1; /* 44 Register b Eank */V unsigned psr$v_ia : 1; /* 45 Disable Instruction Access-bit faults */N unsigned psr$v_mbz3 : 18; /* 46-63 Reserved bits PSR{63:46} */ } psr$r_psrdef_bits; } psr$r_psr_union; } PSR; #if !defined(__VAXC)E#define psr$q_processor_status psr$r_psr_union.psr$q_processor_status7#define psr$v_user_mask psr$r_psr_union.psr$v_user_mask;#define psr$v_system_mask psr$r_psr_union.psr$v_system_mask=#define psr$v_rv0 psr$ Er_psr_union.psr$r_psrdef_bits.psr$v_rv0;#define psr$v_be psr$r_psr_union.psr$r_psrdef_bits.psr$v_be;#define psr$v_up psr$r_psr_union.psr$r_psrdef_bits.psr$v_up;#define psr$v_ac psr$r_psr_union.psr$r_psrdef_bits.psr$v_ac=#define psr$v_mfl psr$r_psr_union.psr$r_psrdef_bits.psr$v_mfl=#define psr$v_mfh psr$r_psr_union.psr$r_psrdef_bits.psr$v_mfh?#define psr$v_mbz0 psr$r_psr_union.psr$r_psrdef_bits.psr$v_mbz0;#define psr$v_ic psr$r_psr_union.psr$r_psrdef_bits.psr$v_ic9#define psr$v_i psr$r_ Epsr_union.psr$r_psrdef_bits.psr$v_i;#define psr$v_pk psr$r_psr_union.psr$r_psrdef_bits.psr$v_pk?#define psr$v_mbz1 psr$r_psr_union.psr$r_psrdef_bits.psr$v_mbz1;#define psr$v_dt psr$r_psr_union.psr$r_psrdef_bits.psr$v_dt=#define psr$v_dfl psr$r_psr_union.psr$r_psrdef_bits.psr$v_dfl=#define psr$v_dfh psr$r_psr_union.psr$r_psrdef_bits.psr$v_dfh;#define psr$v_sp psr$r_psr_union.psr$r_psrdef_bits.psr$v_sp;#define psr$v_pp psr$r_psr_union.psr$r_psrdef_bits.psr$v_pp;#define psr$v_di psr$r_psr E_union.psr$r_psrdef_bits.psr$v_di;#define psr$v_si psr$r_psr_union.psr$r_psrdef_bits.psr$v_si;#define psr$v_db psr$r_psr_union.psr$r_psrdef_bits.psr$v_db;#define psr$v_lp psr$r_psr_union.psr$r_psrdef_bits.psr$v_lp;#define psr$v_tb psr$r_psr_union.psr$r_psrdef_bits.psr$v_tb;#define psr$v_rt psr$r_psr_union.psr$r_psrdef_bits.psr$v_rt?#define psr$v_mbz2 psr$r_psr_union.psr$r_psrdef_bits.psr$v_mbz2=#define psr$v_cpl psr$r_psr_union.psr$r_psrdef_bits.psr$v_cpl;#define psr$v_is psr$r_psr_uni Eon.psr$r_psrdef_bits.psr$v_is;#define psr$v_mc psr$r_psr_union.psr$r_psrdef_bits.psr$v_mc;#define psr$v_it psr$r_psr_union.psr$r_psrdef_bits.psr$v_it;#define psr$v_id psr$r_psr_union.psr$r_psrdef_bits.psr$v_id;#define psr$v_da psr$r_psr_union.psr$r_psrdef_bits.psr$v_da;#define psr$v_dd psr$r_psr_union.psr$r_psrdef_bits.psr$v_dd;#define psr$v_ss psr$r_psr_union.psr$r_psrdef_bits.psr$v_ss;#define psr$v_ri psr$r_psr_union.psr$r_psrdef_bits.psr$v_ri;#define psr$v_ed psr$r_psr_union.psr$r_p Esrdef_bits.psr$v_ed;#define psr$v_bn psr$r_psr_union.psr$r_psrdef_bits.psr$v_bn;#define psr$v_ia psr$r_psr_union.psr$r_psrdef_bits.psr$v_ia?#define psr$v_mbz3 psr$r_psr_union.psr$r_psrdef_bits.psr$v_mbz3"#endif /* #if !defined(__VAXC) */ N#define IS$C_IA64 0 /* IA64 */N#define IS$C_IA32 1 /* IA32 */ #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current po Einter size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Dtypedef struct _psr * PSR_PQ; /* Pointer to a PSR structure. */Qtypedef struct _psr ** PSR_PPQ; /* Pointer to a pointer to a PSR structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 PSR_PQ;!typedef unsigned __int64 PSR_PPQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POIENTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PSRDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential propErietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/*E* proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************** E*****************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */I/* Source: 23-APR-1993 14:31:40 $1$DGA8345:[LIB_H.SRC]PSXFCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PSXFCBDEF ***/#ifndef __PSXFCBDEF_LOADED#define __PSXFCBDEF_LOADED 1 G#pragma __nostandard /* This file uEses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unEknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* amount of space reserved to save kernel stack */N/* during callbacks */N/* and the exec stack E */N/* */K/* The following structure contains data about the process's use of fork */I/* callbacks. There is at most one of these per process and it is */I/* referenced through the P1 space cell CTL$GL_FORK_CONTROL_BLOCK */N/* */#define PSXFCB$M_DISABLED 0x1##define PSXFCB$C_KERN_SAVE_SIZE 384##d Eefine PSXFCB$K_KERN_SAVE_SIZE 384%#define PSXFCB$C_EXEC_STACK_SAVE 1280%#define PSXFCB$K_EXEC_STACK_SAVE 1280 typedef struct _psxfcb {N struct _psxfcb *psxfcb$l_flink; /* forward link (unused) */N struct _psxfcb *psxfcb$l_blink; /* backeard link (unused) */N unsigned short int psxfcb$w_size; /* size allocated */N unsigned char psxfcb$b_type; /* block type */N unsigned char psxfcb$b_subtype; E/* sub type */N __struct { /* flags longword */N unsigned psxfcb$v_disabled : 1; /* callbacks are diabled */% unsigned psxfcb$v_spare : 31; } psxfcb$r_flags;N int psxfcb$l_block_count [4]; /* per-mode block counters */N int psxfcb$l_handler_count [4]; /* count of handlers */N int psxfcb$l_wait [4]; /* wait counters (unused */EN int psxfcb$l_when; /* when callbacks are being call */N int psxfcb$l_failed_when; /* state of when bits on failure */N int psxfcb$l_cancel_state; /* mode (+1) of failure */N int psxfcb$l_callback_state; /* mode (+1) of current callbacks */N unsigned int psxfcb$l_pid; /* pid of 'other' process */N unsigned int psxfcb$l_failing_disp; /* psxdisp address of failing cb */N void *psxfcb$l_imageE_list; /* pointer to first image fdb */N void *psxfcb$l_process_list; /* pointer to first process fdb */N unsigned int psxfcb$l_outer_stack; /* saved outer mode stack for cbs */N unsigned int psxfcb$l_save_ap; /* saved AP during callbacks */N unsigned int psxfcb$l_save_fp; /* saved FP during cbs */N unsigned int psxfcb$l_save_sp; /* saved sp during cbs */N unsigned int psxfcb$l_save_psl; /* saved pEsl during cbs */N unsigned int psxfcb$l_save_exec_sp; /* saved exec stack pointer */N/* */J/* The area below is used to save the kernel mode stack contents while */I/* callbacks are being made */I/* */0 unsigned int psxfcb$l_stack_save_area [384];1 unsigned int psxfcb$l_exec_stack_aErea [1280]; } PSXFCB; #if !defined(__VAXC):#define psxfcb$v_disabled psxfcb$r_flags.psxfcb$v_disabled4#define psxfcb$v_spare psxfcb$r_flags.psxfcb$v_spare"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #e Endif /* __PSXFCBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. E **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. E **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */I/* Source: 19-APR-1993 16:20:59 $1$DGA8345:[LIB_H.SRC]PSXFDBD EEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PSXFDBDEF ***/#ifndef __PSXFDBDEF_LOADED#define __PSXFDBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* ESave the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#defEine __union union#else#define __union variant_union#endif#endif N/* */N/* PSXDISP is the format of a callback dispatch. there is an array of */N/* callback dispatched in each PSXFDB structure. */N/* */#define PSXDISP$M_DISABLED 0x1 typedef struct _psxdisp {N __struct { /*E flag word */N unsigned psxdisp$v_disabled : 1; /* this callback is disabled */N unsigned psxdisp$v_spare : 31; /* fill out the longword */ } psxdisp$r_flags;N/* */N unsigned int psxdisp$l_when; /* when the callback are to be made */N unsigned int psxdisp$l_acmode; /* access mode of the callback */N void *psxdisp$l_handler; E/* address of the callback handler */N unsigned int psxdisp$l_arg; /* argument to pass to the handler */ } PSXDISP; #if !defined(__VAXC)=#define psxdisp$v_disabled psxdisp$r_flags.psxdisp$v_disabled7#define psxdisp$v_spare psxdisp$r_flags.psxdisp$v_spare"#endif /* #if !defined(__VAXC) */ N/* stack */N/* */I/* This structure is u Esed to make lists of callbacks routines */N/* */N/* */#define PSXFDB$C_NUMCALLS 10#define PSXFDB$K_NUMCALLS 10 typedef struct _psxfdb {N struct _psxfdb *psxfdb$l_sqfl; /* link to next fdb */N struct _psxfdb *psxfdb$l_sqbl; /* link to prev fdb */N unsigned short int psxfdb$w_size; /* E size */N unsigned char psxfdb$b_type; /* type */# unsigned char psxfdb$b_subtype;N char psxfdb$b_calls [200]; /* array of dispatches */ } PSXFDB; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplusE }#endif#pragma __standard #endif /* __PSXFDBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** Eprior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permissiEon of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */I/* Source: 23-JUL-2 E004 08:41:20 $1$DGA8345:[LIB_H.SRC]PSXROODEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PSXROODEF ***/#ifndef __PSXROODEF_LOADED#define __PSXROODEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pEragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #i Efndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Definition of the structures for storing POSIX root */N/* information. Also used the the current working directory */I/* (CWD), which functions for relative pathnames much like the */I/* root does for absolute names. E */N/* */ N#define PSXROO$K_DVISIZ 16 /* size of DVI */N#define PSXROO$C_BLN 32 /* structure length (with C tag) */N#define PSXROO$K_BLN 32 /* structure length (with K tag) */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember E_alignment#endiftypedef struct _psxroo {#pragma __nomember_alignment __union { __struct {N unsigned short int psxroo$w_fid_num; /* FID NUM */N unsigned short int psxroo$w_fid_seq; /* FID SEQ */N unsigned short int psxroo$w_fid_rvn; /* FID RVN */ } psxroo$r_fill_fid;N unsigned __int64 psxroo$q_fid; /* FID as a single field */" } psxroo$r_fill_1_overlay;N E unsigned short int psxroo$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char psxroo$b_type; /*STRUCTURE TYPE CODE */N unsigned char psxroo$b_subtype; /*REQUEST ACCESS MODE */_ unsigned short int psxroo$w_chan; /* for CWD, we keep a channel to the directory file. */N short int psxroo$w_fill_2; /* align to quadword for DVI */N char psxroo$t_dvibuf [16]; /* device (DVI) string buffer */ } PSXR EOO; #if !defined(__VAXC)S#define psxroo$w_fid_num psxroo$r_fill_1_overlay.psxroo$r_fill_fid.psxroo$w_fid_numS#define psxroo$w_fid_seq psxroo$r_fill_1_overlay.psxroo$r_fill_fid.psxroo$w_fid_seqS#define psxroo$w_fid_rvn psxroo$r_fill_1_overlay.psxroo$r_fill_fid.psxroo$w_fid_rvn9#define psxroo$q_fid psxroo$r_fill_1_overlay.psxroo$q_fid"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas suppEorted */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PSXROODEF_LOADED */ wwd[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-PaEckard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, IEnc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************** E***************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 12-JAN-2021 13:06:59 $1$DGA8345:[LIB_H.SRC]PTEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PTEDEF ***/#ifndef __PTEDEF_LOADED#define __PTEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignmentE __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifnEdef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* Define page table entry vields and values */N/*- */N#define PTE$C_BYTEES_PER_PTE 8 /* Byte length of Page Table Entry */N#define PTE$C_SHIFT_SIZE 3 /* PTE size as a power of 2 */N/* */N/* Vield definition for "valid" PTEs */N/* */N/* PFN fields are intentionally aligned so that they can be used directly */N/* after masking off all of the other fieldsE in a PTE. */#define PTE$M_P 0x1#define PTE$M_RW 0x2#define PTE$M_US 0x4#define PTE$M_PWT 0x8#define PTE$M_PCD 0x10#define PTE$M_A 0x20#define PTE$M_D 0x40#define PTE$M_PS 0x80#define PTE$M_G 0x100"#define PTE$M_IGN9_11_COMMON 0xE00*#define PTE$M_PER_PTE_UNIQ 0xFFFFFFFFFF000/#define PTE$M_IGN52_58_COMMON 0x7F0000000000000)#define PTE$M_VMS_PROT 0x7800000000000000##define PTE$M_XD 0x8000000000000000 #define PTE$M_COMMON_PML5E 0xFFF&#define PTE$M_PML4 E_PFN 0xFFFFFFFFFF0000#define PTE$M_IGNPROTXD_PML45 0xFFF0000000000000 #define PTE$M_COMMON_PML4E 0xFFF&#define PTE$M_PDPT_PFN 0xFFFFFFFFFF0000#define PTE$M_IGNPROTXD_PML4E 0xFFF0000000000000"#define PTE$M_COMMON_PDPTE1G 0xFFF #define PTE$M_PAT_PDPTE1G 0x1000$#define PTE$M_MBZ_PDPTE1G 0x3FFFE000$#define PTE$M_PFN_1G 0xFFFFFC00000002#define PTE$M_IGNPROTXD_PDPTE1G 0xFFF0000000000000 #define PTE$M_COMMON_PDPTE 0xFFF$#define PTE$M_PD_PFN 0xFFFFFFFFFF0000#define PTE$M_IGNPROTXD_PDPTE 0xFFF00000E00000000!#define PTE$M_COMMON_PDE2MB 0xFFF#define PTE$M_PAT_PDE2MB 0x1000!#define PTE$M_MBZ_PDE2MB 0x1FE000%#define PTE$M_PFN_2MB 0xFFFFFFFE000001#define PTE$M_IGNPROTXD_PDE2MB 0xFFF0000000000000#define PTE$M_COMMON_PDE 0xFFF$#define PTE$M_PT_PFN 0xFFFFFFFFFF000.#define PTE$M_IGNPROTXD_PDE 0xFFF0000000000000#define PTE$M_COMMON_PTE_1 0x7F#define PTE$M_PAT_PTE 0x80 #define PTE$M_COMMON_PTE_2 0xF00$#define PTE$M_PFN_4K 0xFFFFFFFFFF000.#define PTE$M_IGNPROTXD_PTE 0xFFF0000000000000E#define PTE$M_VALID 0x1 #define PTE$M_COMMON_PFN_1 0x1FE#define PTE$M_FOR 0x200#define PTE$M_FOW 0x400#define PTE$M_FOE 0x800%#define PTE$M_NOT_PFN 0xFFFFFFFFFF000(#define PTE$M_SOFTWARE 0x7F0000000000000-#define PTE$M_COMMON_PFN_2 0xF800000000000000%#define PTE$M_PROT 0xF800000000000000#define PTE$M_ASM 0x1#define PTE$M_FILLER_1 0x3E#define PTE$M_MODIFY 0x40#define PTE$M_FILLER_2 0x180&#define PTE$M_FILLER_3 0xFFFFFFFFFF000"#define PTE$M_OWN 0x30000000000000"#define EPTE$M_CPY 0xC0000000000000&#define PTE$M_WINDOW 0x100000000000000(#define PTE$M_FILLER_4 0x600000000000000*#define PTE$M_READ_ONLY 0x1800000000000000$#define PTE$M_TYP0 0x100000000000000/#define PTE$M_PARTIAL_SECTION 0x200000000000000$#define PTE$M_TYP1 0x400000000000000#define PTE$M_STX 0xFFFF000#define PTE$M_CRF 0x10000000#define PTE$M_DZRO 0x20000000#define PTE$M_WRT 0x40000000!#define PTE$M_PGFLPAG 0xFFFFFF000!#define PTE$M_PGFLX 0xFF000000000##define PTE$M_PGFLMAP 0xFFFFFFFFE000 #define PTE$M_GPTX 0xFFFFFFFF000"#define PTE$M_BAKX 0xFFFFFFFFFF000#define PTE$C_NOPGFLPAG 255N/*+ */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pte {#pragma __nomember_alignment __union { __struct {F unsigned pte$v_p : 1; E /* 1 => VALID [0] */H unsigned pte$v_rw : 1; /* 1 => writeable [1] */M unsigned pte$v_us : 1; /* 1 => User, 0 => Sys [2] */I unsigned pte$v_pwt : 1; /* Pg-lvl wrt-thru [3] */L unsigned pte$v_pcd : 1; /* pg-lvl cache dsabl [4] */C unsigned pte$v_a : 1; /* Accessed [5] */@ unsigned pte$v_d : 1; /* Dirty [6] */D unsigned pteE$v_ps : 1; /* Page Size [7] */K unsigned pte$v_g : 1; /* Global some forms [8] */N unsigned pte$v_ign9_11_common : 3; /* Ignored most forms [9-11] *// unsigned pte$v_per_pte_uniq_1 : 32;N unsigned pte$v_per_pte_uniq_2 : 8; /* Varies by PTE [12-51] */P unsigned pte$v_ign52_58_common : 7; /* Ignored (Software) [52-58] */H unsigned pte$v_vms_prot : 4; /* VMS prot code [59-62] */I unsi Egned pte$v_xd : 1; /* Execute disable [63] */ } pte$r_common_bits; __struct {J unsigned pte$v_common_pml5e : 12; /* Commmon overlay [0-11] */N/* Note: Bit 7 MBZ in this form */#if defined(__VAXC)+ unsigned pte$v_pml4_pfn_1 : 32;* unsigned pte$v_pml4_pfn_2 : 8;#elseU unsigned __int64 pte$v_pml4_pfn : 40; /* PFN of 4K pg for PML4 [12-51] */#endifM unsign Eed pte$v_ignprotxd_pml45 : 12; /* Common overlay [52-63] */ } pte$r_pml5e_bits; __struct {J unsigned pte$v_common_pml4e : 12; /* Commmon overlay [0-11] */N/* Note: Bit 7 MBZ in this form */#if defined(__VAXC)+ unsigned pte$v_pdpt_pfn_1 : 32;* unsigned pte$v_pdpt_pfn_2 : 8;#else_ unsigned __int64 pte$v_pdpt_pfn : 40; /* PFN of 4K pg for PDPT or 1GB pg [12-51] */#endifM E unsigned pte$v_ignprotxd_pml4e : 12; /* Common overlay [52-63] */ } pte$r_pml4e_bits; __struct {L unsigned pte$v_common_pdpte1g : 12; /* Commmon overlay [0-11] */N/* Note: Bit 7 (PS) = 1 in this form */< unsigned pte$v_pat_pdpte1g : 1; /* PAT [12] */H unsigned pte$v_mbz_pdpte1g : 17; /* Must Be Zero [13-29] */G unsigned pte$v_pfn_1g : 22; /* PFN of 1GB pg [30-51] */O E unsigned pte$v_ignprotxd_pdpte1g : 12; /* Common overlay [52-63] */! } pte$r_pdpte1g_bits; __struct {J unsigned pte$v_common_pdpte : 12; /* Commmon overlay [0-11] */N/* Note: Bit 6 (D) ignored in this form */N/* Note: Bit 7 (PS) = 0 in this form */N/* Note: Bit 8 (G) ignored in this form */#if defined(__VAXC)) unsigned pte$v_pd_pfn_1 E: 32;( unsigned pte$v_pd_pfn_2 : 8;#else[ unsigned __int64 pte$v_pd_pfn : 40; /* PFN of 4K pg for PD or 2MB pg [12-51] */#endifM unsigned pte$v_ignprotxd_pdpte : 12; /* Common overlay [52-63] */ } pte$r_pdpte_bits; __struct {K unsigned pte$v_common_pde2mb : 12; /* Commmon overlay [0-11] */N/* Note: Bit 7 (PS) = 1 in this form */; unsigned pte$v_pat_pde2mb : 1; /* PAT E[12] */F unsigned pte$v_mbz_pde2mb : 8; /* Must Be Zero [13-20] */H unsigned pte$v_pfn_2mb : 31; /* PFN of 2MB pg [21-51] */N unsigned pte$v_ignprotxd_pde2mb : 12; /* Common overlay [52-63] */ } pte$r_pde2mb_bits; __struct {M unsigned pte$v_common_pde : 12; /* Commmon overlay [0-11] */N/* Note: Bit 6 (D) ignored in this form */N/* Note: Bit 7 (PS) = 0 in this form E */N/* Note: Bit 8 (G) ignored in this form */#if defined(__VAXC)) unsigned pte$v_pt_pfn_1 : 32;( unsigned pte$v_pt_pfn_2 : 8;#elseR unsigned __int64 pte$v_pt_pfn : 40; /* PFN of 4KB pg for PT [12-51] */#endifK unsigned pte$v_ignprotxd_pde : 12; /* Common overlay [52-63] */ } pte$r_pde_bits; __struct {N unsigned pte$v_common_pte_1 : 7; /* Commmon over Elay [0-6] */? unsigned pte$v_pat_pte : 1; /* PAT [7] */N unsigned pte$v_common_pte_2 : 4; /* Commmon overlay [8-11] */#if defined(__VAXC)) unsigned pte$v_pfn_4k_1 : 32;( unsigned pte$v_pfn_4k_2 : 8;#elseK unsigned __int64 pte$v_pfn_4k : 40; /* PFN of 4KB pg [12-51] */#endifK unsigned pte$v_ignprotxd_pte : 12; /* Common overlay [52-63] */ } pte$r_pte_bits; __struct {N E unsigned pte$v_valid : 1; /* [0] VALID bit = Present */N unsigned pte$v_common_pfn_1 : 8; /* [1-8] */N unsigned pte$v_for : 1; /* [9] Fault On Read */N unsigned pte$v_fow : 1; /* [10] Fault On Write */N unsigned pte$v_foe : 1; /* [11] Fault On Execute */* unsigned pte$v_not_pfn_1 : 32;R unsigned pte$v_not_pfn_2 : 8; /* [12-51] Must know what Ekind of PTE */N/* to know size of PFN. Use */N/* specific PFN fields declared */N/* above. */N unsigned pte$v_software : 7; /* [52-58] */N unsigned pte$v_common_pfn_2 : 5; /* [59-63] PROT and XD */! } pte$r_ptedef_bits0; __struct {+ unsigned pte$v_fille Er_1_1 : 32;+ unsigned pte$v_filler_1_2 : 27;N unsigned pte$v_prot : 5; /* Protection code and XD bit */ } pte$r_ptedef_prot; __struct {N unsigned pte$v_asm : 1; /* [0] Obsolete on x86 */N/* (ASM can only be set if valid is set */N/* so, we use this trick for porting) */N/* This came from IA64. Do we need this for x86? E */N unsigned pte$v_filler_1 : 5; /* [1-5] */N unsigned pte$v_modify : 1; /* [6] hardware dirty bit */N unsigned pte$v_filler_2 : 2; /* [7-8] */N unsigned pte$v_fault_bits : 3; /* [9-11] For SDA */+ unsigned pte$v_filler_3_1 : 32;N unsigned pte$v_filler_3_2 : 8; /* [12-51] */N unsigned pte$v_own : 2; /* [52-53]E Page Owner Mode */N unsigned pte$v_cpy : 2; /* [54-55] Copy characteristic */N unsigned pte$v_window : 1; /* [56] Windowed Page Bit */N unsigned pte$v_filler_4 : 2; /* [57-58] */Y unsigned pte$v_read_only : 2; /* [59-60] Read only prot if low 2 bits set. */' unsigned pte$v_fill_0_ : 3;" } pte$r_ptedef_swbits;N/* E */N/* Vield definitions for various invalid forms of PTE */N/* */ __struct {, unsigned pte$v_filler_22_1 : 32;N unsigned pte$v_filler_22_2 : 24; /* [0-55] skip hardware bits */N unsigned pte$v_typ0 : 1; /* [56] TYP0 Bit */\ unsigned pte$v_partial_section : 1; /* [57] Only part of page maps to section */N E unsigned pte$v_typ1 : 1; /* [58] TYP1 Bit */' unsigned pte$v_fill_1_ : 5;! } pte$r_ptedef_bits1; __union { __struct {g unsigned pte$v_filler_5 : 12; /* [0-11] skip to PFN field. Not marked 'fill' for SDA */Y unsigned pte$v_stx : 16; /* [A/I=32-47, x86=12-27] Section Table Index */P unsigned pte$v_crf : 1; /* [A/I=48, x86=28] Copy on Reference */N unsigned pte$v_dEzro : 1; /* [A/I=49, x86=29] Demand Zero */^ unsigned pte$v_wrt : 1; /* [A/I=50, x86=30] Section file accessed for write */V unsigned pte$v_filler_17 : 21; /* [31-51] Not marked 'fill' for SDA */U unsigned pte$v_filler_18 : 12; /* [52-63] Overlays protection etc. */! } pte$r_stx_bits; __struct {k unsigned pte$v_filler_6 : 12; /* [0-11] skip to PGFLPAG field. Not marked 'fill' for SDA */k E unsigned pte$v_pgflpag : 24; /* [A/I=32-55, x86=12-35] Page File Page Number (not a VBN) */] unsigned pte$v_pgflx : 8; /* [A/I=56-63, x86=36-43] System page file index */V unsigned pte$v_filler_19 : 20; /* [44-63] Not marked 'fill' for SDA */! } pte$r_bak_pgfl; __struct {Q unsigned pte$v_filler_16 : 12; /* [0-11] skip to PGFLMAP field */R unsigned pte$v_pgflmap : 32; /* Page file page number and index E*/+ unsigned pte$v_fill_2_ : 4;$ } pte$r_bak_pgflmap; __struct {N unsigned pte$v_filler_8 : 12; /* [0-11] skip to GPTX field */N unsigned pte$v_gptx : 32; /* Global Page Table Index */+ unsigned pte$v_fill_3_ : 4;% } pte$r_gptx_overlay; __struct {N unsigned pte$v_filler_7 : 12; /* [0-11] skip to PFN field */#if defined(__VAXC)+ un Esigned pte$v_bakx_1 : 32;* unsigned pte$v_bakx_2 : 8;#elseV unsigned __int64 pte$v_bakx : 40; /* Backup Address (uninterpreted) */#endif+ unsigned pte$v_fill_4_ : 4;" } pte$r_bakx_bits; } pte$r_ptedef_pfn; __union {N unsigned __int64 pte$q_entry; /* The entire page table entry */$ } pte$r_ptedef_entry_qw; __struct {N unsigned int pte$l_entry_l; /* The low lon Egword of the PTE */N unsigned int pte$l_entry_h; /* The high longword of the PTE */$ } pte$r_ptedef_entry_lw; } pte$r_pte_union;N/*+ */U/* Define a constant indicating "no pagefile page assigned": all bits set in PGFLX */N/*- */N/* Protection field definitions. These protection encodings provide */N/* a wEay to express page protection using VAX-like protection symbols. */N/*- */N/*+ */N/* OWNer mode field definitions */N/* */N/* These constants are not meant to be shifted into the owner field. They */N/* incorporate ownership informaEtion as a bitmask relative to the start of */N/* a PTE already. */N/*_ */N/*+ */N/* CoPY field definitions */N/* */N/* These constants are not meant to be shifted into the coEpy characteristic */N/* field. They incorporate copy characteristic information relative to the */N/* start of a PTE already. */N/*_ */N/*+ */N/* Demand zero PTE defintions for L1 and L2 PTEs */N/*- */ E} PTE; #if !defined(__VAXC)9#define pte$v_p pte$r_pte_union.pte$r_common_bits.pte$v_p;#define pte$v_rw pte$r_pte_union.pte$r_common_bits.pte$v_rw;#define pte$v_us pte$r_pte_union.pte$r_common_bits.pte$v_us=#define pte$v_pwt pte$r_pte_union.pte$r_common_bits.pte$v_pwt=#define pte$v_pcd pte$r_pte_union.pte$r_common_bits.pte$v_pcd9#define pte$v_a pte$r_pte_union.pte$r_common_bits.pte$v_a9#define pte$v_d pte$r_pte_union.pte$r_common_bits.pte$v_d;#define pte$v_ps pte$r_pte_union.pte$r_cEommon_bits.pte$v_ps9#define pte$v_g pte$r_pte_union.pte$r_common_bits.pte$v_gG#define pte$v_vms_prot pte$r_pte_union.pte$r_common_bits.pte$v_vms_prot;#define pte$v_xd pte$r_pte_union.pte$r_common_bits.pte$v_xdF#define pte$v_pml4_pfn pte$r_pte_union.pte$r_pml5e_bits.pte$v_pml4_pfnF#define pte$v_pdpt_pfn pte$r_pte_union.pte$r_pml4e_bits.pte$v_pdpt_pfnN#define pte$v_pat_pdpte1g pte$r_pte_union.pte$r_pdpte1g_bits.pte$v_pat_pdpte1gN#define pte$v_mbz_pdpte1g pte$r_pte_union.pte$r_pdpte1g_bits.pteE$v_mbz_pdpte1gD#define pte$v_pfn_1g pte$r_pte_union.pte$r_pdpte1g_bits.pte$v_pfn_1gB#define pte$v_pd_pfn pte$r_pte_union.pte$r_pdpte_bits.pte$v_pd_pfnK#define pte$v_pat_pde2mb pte$r_pte_union.pte$r_pde2mb_bits.pte$v_pat_pde2mbK#define pte$v_mbz_pde2mb pte$r_pte_union.pte$r_pde2mb_bits.pte$v_mbz_pde2mbE#define pte$v_pfn_2mb pte$r_pte_union.pte$r_pde2mb_bits.pte$v_pfn_2mb@#define pte$v_pt_pfn pte$r_pte_union.pte$r_pde_bits.pte$v_pt_pfnB#define pte$v_pat_pte pte$r_pte_union.pte$r_pte_bits.pte$v E_pat_pte@#define pte$v_pfn_4k pte$r_pte_union.pte$r_pte_bits.pte$v_pfn_4kB#define pte$v_valid pte$r_pte_union.pte$r_ptedef_bits0.pte$v_valid>#define pte$v_for pte$r_pte_union.pte$r_ptedef_bits0.pte$v_for>#define pte$v_fow pte$r_pte_union.pte$r_ptedef_bits0.pte$v_fow>#define pte$v_foe pte$r_pte_union.pte$r_ptedef_bits0.pte$v_foeH#define pte$v_software pte$r_pte_union.pte$r_ptedef_bits0.pte$v_software?#define pte$v_prot pte$r_pte_union.pte$r_ptedef_prot.pte$v_prot?#define pte$v_asm pte$r_pte_unEion.pte$r_ptedef_swbits.pte$v_asmE#define pte$v_modify pte$r_pte_union.pte$r_ptedef_swbits.pte$v_modifyM#define pte$v_fault_bits pte$r_pte_union.pte$r_ptedef_swbits.pte$v_fault_bits?#define pte$v_own pte$r_pte_union.pte$r_ptedef_swbits.pte$v_own?#define pte$v_cpy pte$r_pte_union.pte$r_ptedef_swbits.pte$v_cpyE#define pte$v_window pte$r_pte_union.pte$r_ptedef_swbits.pte$v_windowK#define pte$v_read_only pte$r_pte_union.pte$r_ptedef_swbits.pte$v_read_only@#define pte$v_typ0 pte$r_pte_union.pEte$r_ptedef_bits1.pte$v_typ0V#define pte$v_partial_section pte$r_pte_union.pte$r_ptedef_bits1.pte$v_partial_section@#define pte$v_typ1 pte$r_pte_union.pte$r_ptedef_bits1.pte$v_typ1U#define pte$v_filler_5 pte$r_pte_union.pte$r_ptedef_pfn.pte$r_stx_bits.pte$v_filler_5K#define pte$v_stx pte$r_pte_union.pte$r_ptedef_pfn.pte$r_stx_bits.pte$v_stxK#define pte$v_crf pte$r_pte_union.pte$r_ptedef_pfn.pte$r_stx_bits.pte$v_crfM#define pte$v_dzro pte$r_pte_union.pte$r_ptedef_pfn.pte$r_stx_bits.pte$v_dzroEK#define pte$v_wrt pte$r_pte_union.pte$r_ptedef_pfn.pte$r_stx_bits.pte$v_wrtW#define pte$v_filler_17 pte$r_pte_union.pte$r_ptedef_pfn.pte$r_stx_bits.pte$v_filler_17U#define pte$v_filler_6 pte$r_pte_union.pte$r_ptedef_pfn.pte$r_bak_pgfl.pte$v_filler_6S#define pte$v_pgflpag pte$r_pte_union.pte$r_ptedef_pfn.pte$r_bak_pgfl.pte$v_pgflpagO#define pte$v_pgflx pte$r_pte_union.pte$r_ptedef_pfn.pte$r_bak_pgfl.pte$v_pgflxW#define pte$v_filler_19 pte$r_pte_union.pte$r_ptedef_pfn.pte$r_bak_pgfl.pte$v_fiEller_19V#define pte$v_pgflmap pte$r_pte_union.pte$r_ptedef_pfn.pte$r_bak_pgflmap.pte$v_pgflmapQ#define pte$v_gptx pte$r_pte_union.pte$r_ptedef_pfn.pte$r_gptx_overlay.pte$v_gptxN#define pte$v_bakx pte$r_pte_union.pte$r_ptedef_pfn.pte$r_bakx_bits.pte$v_bakxE#define pte$q_entry pte$r_pte_union.pte$r_ptedef_entry_qw.pte$q_entryI#define pte$l_entry_l pte$r_pte_union.pte$r_ptedef_entry_lw.pte$l_entry_lI#define pte$l_entry_h pte$r_pte_union.pte$r_ptedef_entry_lw.pte$l_entry_h"#endif /* #if !defiEned(__VAXC) */  [#if defined(__alpha) || defined(__ia64) /* Verified for x86 port - Gregory H. Jordan */ctypedef int PROTO_PTE; /* Maintain PROTO_PTE as an int for compatibility on Alpha and IA64 */#elseOtypedef unsigned __int64 PROTO_PTE; /* Proto PTE must be 64 bits on X86 */#endif#define PTE$M_FREE_PTE_MBZ1 0x1,#define PTE$M_FREE_PTE_MBZ2 0x30000000000000)#define PTE$M_SINGLE_PTE 0x40000000000000.#define PTE$M_FREE_PTE_MBZ3 0xFF80000000000000 c#if !definedE(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _va_pte_free {#pragma __nomember_alignment __union {l unsigned __int64 pte$iq_index; /* PTE index field. For historic reasons, index field is defined */ __struct {) unsigned pte$v_filler_20 : 1;#if defined(__VAXC)) unsigned pte$v_index1_1 : 32;) E unsigned pte$v_index1_2 : 19;#elseN unsigned __int64 pte$v_index1 : 51; /* Bits <1:51> Is the Index */#endif' unsigned pte$v_fill_5_ : 4;( } pte$r_va_pte_index_struct;g __struct { /* as a quadword. Actual index lives in bits <63:19> of the */N unsigned pte$v_free_pte_mbz1 : 1; /* Bit <0:0> are MBZ. */#if defined(__VAXC), unsigned pte$v_filler_x2_1 : 32;, unsigned pte$v_filler_x2 E_2 : 19;#else2 unsigned __int64 pte$v_filler_x2 : 51;#endifs unsigned pte$v_free_pte_mbz2 : 2; /* Bits <52:53> are MBZ in order for code to distinguish between a */h unsigned pte$v_single_pte : 1; /* Bit <54> denotes that the element contains a single PTE */N unsigned pte$v_free_pte_mbz3 : 9; /* Bits <55:63> are MBZ */' } pte$r_va_pte_free_struct;N/* free PTE and a GPTE */" E } pte$r_va_pte_free_union; __union {R unsigned __int64 pte$iq_free_count_qw; /* Quadword containg free count. */Y __struct { /* Counts lives in bits <63:8> of the quadword */) unsigned pte$v_filler_14 : 8;#if defined(__VAXC)- unsigned pte$v_free_count_1 : 32;- unsigned pte$v_free_count_2 : 24;#else3 unsigned __int64 pte$v_free_count : 56;#endif( } pte$r_va_pte_free_struct2;N/* fre Ee PTE and a GPTE */# } pte$r_va_pte_free_union2; } VA_PTE_FREE; #if !defined(__VAXC)9#define pte$iq_index pte$r_va_pte_free_union.pte$iq_indexS#define pte$v_index1 pte$r_va_pte_free_union.pte$r_va_pte_index_struct.pte$v_index1`#define pte$v_free_pte_mbz1 pte$r_va_pte_free_union.pte$r_va_pte_free_struct.pte$v_free_pte_mbz1X#define pte$v_filler_x2 pte$r_va_pte_free_union.pte$r_va_pte_free_struct.pte$v_filler_x2`#define pte$v_Efree_pte_mbz2 pte$r_va_pte_free_union.pte$r_va_pte_free_struct.pte$v_free_pte_mbz2Z#define pte$v_single_pte pte$r_va_pte_free_union.pte$r_va_pte_free_struct.pte$v_single_pte`#define pte$v_free_pte_mbz3 pte$r_va_pte_free_union.pte$r_va_pte_free_struct.pte$v_free_pte_mbz3J#define pte$iq_free_count_qw pte$r_va_pte_free_union2.pte$iq_free_count_qw\#define pte$v_free_count pte$r_va_pte_free_union2.pte$r_va_pte_free_struct2.pte$v_free_count"#endif /* #if !defined(__VAXC) */ U#define PTE$S_PTEDEF 1E6 /* Old PTE size constant for compatibility */N/* */N/* */N/* Define a constant that's used to shift the index value into the */N/* appropriate bits of the index quadword of the VA_PTE_FREE structure. */N/* */!#define PTE$C_INDEX_SHIFT_VALUE 1O#def Eine PTE$C_FREE_BLOCK 16 /* Byte length of VA_PTE free block. */N/* Head of a private list of free PTEs */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ptelist {#pragma __nomember_alignmentP unsigned __int64 ptelist$q_head; /* PTE index of head and tail element */Z unsigned _E_int64 ptelist$q_tail; /* in free list; same format as in VA_PTE_FREE */N __int64 ptelist$q_count; /* count of free PTEs in this list */ } PTELIST;N#define PTELIST$K_LENGTH 24 /* length of block; */N#define PTELIST$C_LENGTH 24 /* length of block; */N/*+ */N/* These constants are not meant to be shifted into the PROT position. */N/* They incoErporate protection information as bitmasks relative to the */N/* start of a PTE already. In other words, they can be ORed into a */N/* zeroed PROT field. */N/* */N/* SDL does not have support for constants larger than 32 bits. So we */N/* have to drop down into language-specific coding. C, MACRO, and */N/* BLISS-64 handle them. For BLISS-32 E, they are defined relative */N/* to the upper longword of a PTE. */N/*- */ 4#define PTE$C_NA (0x00ull << 59) /* No Access */E#define PTE$C_KR (0x03ull << 59) /* Kernel Read only (execute) */C#define PTE$C_ER (0x07ull << 59) /* Exec Read only (execute) */D#define PTE$C_SR (0x0Bull << 59) /* Super Read only (execute) */C#define PTE$C_UR (0x0Full << 59E) /* User Read only (execute) */D#define PTE$C_KW (0x12ull << 59) /* Kernel Write (no execute) */B#define PTE$C_EW (0x15ull << 59) /* Exec Write (no execute) */C#define PTE$C_SW (0x18ull << 59) /* Super Write (no execute) */B#define PTE$C_UW (0x14ull << 59) /* User Write (no execute) */N#define PTE$C_ERKW (0x16ull << 59) /* Exec Read Kernel Write (no execute) */O#define PTE$C_SRKW (0x1Aull << 59) /* Super Read Kernel Write (no execute) */M#define PTE$C_SREW (0x19ull << E59) /* Super Read Exec Write (no execute) */N#define PTE$C_URKW (0x1Eull << 59) /* User Read Kernel Write (no execute) */L#define PTE$C_UREW (0x1Dull << 59) /* User Read Exec Write (no execute) */M#define PTE$C_URSW (0x1Cull << 59) /* User Read Super Write (no execute) */H#define PTE$C_KRO (0x13ull << 59) /* Kernel Read only (no execute) */F#define PTE$C_ERO (0x17ull << 59) /* Exec Read only (no execute) */G#define PTE$C_SRO (0x1Bull << 59) /* Super Read only (no execute) */FE#define PTE$C_URO (0x1Full << 59) /* User Read only (no execute) */A#define PTE$C_KWX (0x02ull << 59) /* Kernel Write (execute) */?#define PTE$C_EWX (0x05ull << 59) /* Exec Write (execute) */@#define PTE$C_SWX (0x08ull << 59) /* Super Write (execute) */?#define PTE$C_UWX (0x04ull << 59) /* User Write (execute) */K#define PTE$C_ERKWX (0x06ull << 59) /* Exec Read Kernel Write (execute) */L#define PTE$C_SRKWX (0x0Aull << 59) /* Super Read Kernel Write (execute) */J#define PTE$EC_SREWX (0x09ull << 59) /* Super Read Exec Write (execute) */K#define PTE$C_URKWX (0x0Eull << 59) /* User Read Kernel Write (execute) */I#define PTE$C_UREWX (0x0Dull << 59) /* User Read Exec Write (execute) */J#define PTE$C_URSWX (0x0Cull << 59) /* User Read Super Write (execute) */:#define PTE$C_KOWN (0x0ull << 52) /* Kernel Owner Mode */=#define PTE$C_EOWN (0x1ull << 52) /* Executive Owner Mode */>#define PTE$C_SOWN (0x2ull << 52) /* Supervisor Owner Mode */8#define PTE$C_UOWN (0x3u Ell << 52) /* User Owner Mode *//#define PTE$C_COPY (0x0ull << 54) /* Copy */2#define PTE$C_NOCOPY (0x1ull << 54) /* No copy */7#define PTE$C_DZRO (0x2ull << 54) /* Copy as DZRO */A#define PTE$C_DZRO_PT_PTE PTE$C_KW /* Kernel write, no execute */C#define PTE$C_DZRO_PDPT_PTE PTE$C_KW /* Kernel write, no execute */    #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* PointerEs are 64-bit */Dtypedef struct _pte * PTE_PQ; /* Pointer to a PTE structure. */Qtypedef struct _pte ** PTE_PPQ; /* Pointer to a pointer to a PTE structure. */Ntypedef struct _ptelist * PTELIST_PQ; /* Pointer to a PTELIST structure. */\typedef struct _ptelist ** PTELIST_PPQ; /* Pointer to a pointer to a PTELIST structure. */Ytypedef struct _va_pte_free * VA_PTE_FREE_PQ; /* Pointer to a free VA_PTE structure. */ftypedef struct _va_pte_free ** VA_PTE_FREE_PPQ; /* Pointer to a Epointer to a free VA_PTE structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 PTE_PQ;!typedef unsigned __int64 PTE_PPQ;$typedef unsigned __int64 PTELIST_PQ;%typedef unsigned __int64 PTELIST_PPQ;(typedef unsigned __int64 VA_PTE_FREE_PQ;)typedef unsigned __int64 VA_PTE_FREE_PPQ;##endif /* __INITIAL_POINTER_SIZE */N/* We need a PTE$S_PFN for C... */#define PTE$S_PFN 40NE/* Size of page tables on X86 */N/* */N/* The sizes can not be expressed in bliss32 and will be equated to zero. */N/*+ */T/* Define constant to with the number of PTEs and the PFN incremetns for 8K pages */N/*- */T#define PTE$C_PFN_INECR 2 /* Increment PFNs by 2 on X86 per 8k page */N#define PTE$C_PAGE_INCR 2 /* 2 PTEs per 8K page on X86 */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PTEDEF_LOADED */ ww@٫[UM/*******E********************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-PackaErd Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. E **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Source: 17-NOV-1999 13:28:56 $1$DGA8345:[LIB_H.SRC]PTRDEF.SDL;1 *//********************************************************* E***********************************************************************//*** MODULE $PTRDEF ***/#ifndef __PTRDEF_LOADED#define __PTRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_sizEe __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif NE/*+ */N/* POINTER CONTROL BLOCK */N/* THIS IS A STRUCTURE OF POINTERS TO OTHER DYNAMIC STRUCTURES */N/* OF LIKE KIND. TYPICALLY THE STRUCTURES POINTED TO ARE KNOWN */O/* BY THEIR LONG WORD INDEX INTO THE TABLE AND TO FACILITATE FETCHING */N/* THESE, IT IS CONVENTIONAL TO KEEP A POINTER TO THE BASE OF THE */N/* STRUCTURE POIN ETERS RATHER THAN (OR IN ADDITION TO) THE POINTER */O/* TO THE FRONT OF THE POINTER CONTROL BLOCK. THE NUMBER OF POINTERS */N/* IN THE ARRAY PRECEEDS THE FIRST POINTER IN THE ARRAY. */N/*- */N#define PTR$K_LENGTH 16 /*LENGTH OF FIXED PORTION */N#define PTR$C_LENGTH 16 /*LENGTH OF FIXED PORTION */#define PTR$S_PTRDEF 20 c#if !defined(__NOBEASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ptr {#pragma __nomember_alignmentN __union { /* Generic header info */) unsigned __int64 ptr$q_info_quad; __struct {* unsigned int ptr$l_info_long0;* unsigned int ptr$l_info_long1;% } ptr$r_info_long_struct; E } ptr$r_info_overlay;N unsigned short int ptr$w_size; /*SIZE OF DYNAMIC CONTROL BLOCK */N unsigned char ptr$b_type; /*TYPE OF DYNAMIC CONTROL BLOCK */N unsigned char ptr$b_ptrtype; /*TYPE OF CONTROL BLOCK POINTED TO */N unsigned int ptr$l_ptrcnt; /*COUNT OF ENTRIES */N void *ptr$l_ptr0; /*PTR NUMBER 0 */ char ptr$b_fill_0_ [4]; } PTR; #if !defined(__VAXC):#define ptr$ Eq_info_quad ptr$r_info_overlay.ptr$q_info_quadS#define ptr$l_info_long0 ptr$r_info_overlay.ptr$r_info_long_struct.ptr$l_info_long0S#define ptr$l_info_long1 ptr$r_info_overlay.ptr$r_info_long_struct.ptr$l_info_long1"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplEusplus }#endif#pragma __standard #endif /* __PTRDEF_LOADED */ ww`'[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/ME/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permFission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */I/* Source: 11-M FAR-1998 06:08:10 $1$DGA8345:[LIB_H.SRC]PWDHISDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PWDHISDEF ***/#ifndef __PWDHISDEF_LOADED#define __PWDHISDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */F\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif F#ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif O/* Password History Record - This structure defines the layout of the system */R/* password history file. This is a variable record length indexed file (keyed */S/* by username) where each record contains the last "n" quadword hash values for */N/* the user's last "n" passwords. */N#define PWDHIS$C_ENTRY_LENGTH 16 /* size Fof one entry */N#define PWDHIS$K_ENTRY_LENGTH 16 /* size of one entry */#define PWDHIS$S_PWDENTDEF 16 typedef struct _pwdent {N __int64 pwdhis$q_entry; /* the quadword hash */N __int64 pwdhis$q_change; /* password change date */ } PWDENT;N#define PWDHIS$C_FIXED 32 /* fixed part of record */N#define PWDHIS$K_FIXED 32 /* fixed part of record F*/N#define PWDHIS$C_DEFAULT_LIFETIME 365 /* default history lifetime (days) */N#define PWDHIS$K_DEFAULT_LIFETIME 365 /* default history lifetime (days) */S#define PWDHIS$C_DEFAULT_LIMIT 60 /* default # of history entries per user */S#define PWDHIS$K_DEFAULT_LIMIT 60 /* default # of history entries per user */S#define PWDHIS$C_MAXIMUM_LIMIT 2000 /* maximum # of history entries per user */S#define PWDHIS$K_MAXIMUM_LIMIT 2000 /* maximum # of history entries per user */F #define PWDHIS$S_PWDHISDEF 32032 typedef struct _pwdhis {N char pwdhis$t_username [32]; /* username (KEY0) */N __struct { /* offset to start of list */& PWDENT pwdhis$r_history_entry;" } pwdhis$r_history [2000]; } PWDHIS; #if !defined(__VAXC)5#define pwdhis$r_history_entry pwdhis$r_history_entry"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTERF_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PWDHISDEF_LOADED */ wwu[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential propFrietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/* F* proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************** F*****************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Source: 08-JUL-1998 11:03:45 $1$DGA8345:[LIB_H.SRC]PXBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PXBDEF ***/#ifndef __PXBDEF_LOADED#define __PXBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI F-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params F#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct F _pxb {#pragma __nomember_alignmentN struct _pxb *pxb$l_flink; /* forward link */N struct _pxb *pxb$l_blink; /* backward link */N unsigned short int pxb$w_size; /* size */N unsigned char pxb$b_type; /* type code */N unsigned char pxb$b_subtype; /* subtype code */ } PXB;N#define PXB$K_LENGTH 12 /* Length of h Feader */N/* */N/* PXB Array (Persona Extension Block Array) */N/* */ #define PXB_ARRAY_ELEMENTS 16'#define PXB_ARRAY$K_PXB_ARRAY_HEADER 12 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragm Fa __nomember_alignment#endiftypedef struct _pxb_array {#pragma __nomember_alignmentN struct _pxb_array *pxb_array$l_flink; /* forward link */N struct _pxb_array *pxb_array$l_blink; /* backward link */N unsigned short int pxb_array$w_size; /* size */N unsigned char pxb_array$b_type; /* type code */N unsigned char pxb_array$b_subtype; /* subtype code */N unsigned i Fnt pxb_array$ar_elements [16]; /* The array cells */ } PXB_ARRAY;N/* */N/* delegate block */N/* */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_ali Fgnment#endiftypedef struct _delbk {#pragma __nomember_alignmentN struct _delbk *delbk$l_flink; /* forward link */N struct _delbk *delbk$l_blink; /* backward link */N unsigned short int delbk$w_size; /* size */N unsigned char delbk$b_type; /* type code */N unsigned char delbk$b_subtype; /* subtype cod */N unsigned int delbk$l_persona_iFd; /* Persona ID */N unsigned int delbk$l_persona_address; /* Persona address */N unsigned int delbk$l_client_epid; /* Client's EPID */N unsigned int delbk$l_client_tpid; /* Client's Thread PID */X unsigned int delbk$l_bytcnt; /* BYTCNT/BYTLM to be debited upon delegation */S unsigned int delbk$l_imgcnt; /* Value of PHD$L_IMGCNT when we started */N unsigned int delbk$l_status; /* s Ftatus */ } DELBK;N#define DELBK$C_DELEGATE_BLOCK_SIZE 40 /* Length of DELBK struct */N/* */N/* Persona Security Extension Registration Block definitions */N/* */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignme Fnt __quadword#else#pragma __nomember_alignment#endiftypedef struct _pxrb {#pragma __nomember_alignmentN struct _pxrb *pxrb$l_flink; /* forward link */N struct _pxrb *pxrb$l_blink; /* backward link */N unsigned short int pxrb$w_size; /* size */N unsigned char pxrb$b_type; /* type code */N unsigned char pxrb$b_subtype; /* subtype cod F */N unsigned int pxrb$l_flags; /* */N unsigned int pxrb$l_eid; /* Extension ID */N unsigned int pxrb$l_name_desc [2]; /* Extension name descriptor */N char pxrb$ar_name [32]; /* Extension name string */N void *pxrb$a_create; /* Pointer to CREATE routine */N void *pxrb$a_clone; /* Pointer to CLONE routine */N void *pxrb$a F_delegate; /* Pointer to DELEGATE routine */N void *pxrb$a_delete; /* Pointer to DELETE routine */N void *pxrb$a_modify; /* Pointer to MODIFY routine */N void *pxrb$a_query; /* Pointer to QUERY routine */N void *pxrb$a_make_tlv; /* Pointer to MAKE_TLV routine */ } PXRB;N#define PXRB$K_LENGTH 88 /* Length of PXRB struct */ N/* F */N/* Persona Security Extension Dispatch Vector Block definitions */N/* */ #define PXDV$K_VERSION 1#define PXDV$K_MIN_VERSION 1#define PXDV$K_MAX_VERSION 1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedeFf struct _pxdv {#pragma __nomember_alignmentN unsigned int pxdv$l_version; /* Version of dispatch vector */N unsigned int pxdv$l_flags; /* */N void *pxdv$a_create; /* Address to CREATE routine */N void *pxdv$a_clone; /* Address to CLONE routine */N void *pxdv$a_delegate; /* Address to DELEGATE routine */N void *pxdv$a_delete; /* Address to DELE FTE routine */N void *pxdv$a_modify; /* Address to MODIFY routine */N void *pxdv$a_query; /* Address to QUERY routine */N void *pxdv$a_make_tlv; /* Address to MAKE_TLV routine */ char pxdv$b_fill_0_ [4]; } PXDV; N/* */N/* Persona Security Extension Block definitions for NT */N/* F */ N#define PXBNT$K_VERSION_1 1 /* version number 1 */N#define PXBNT$K_CURRENT_VERSION 1 /* current protocol */#define PXBNT$M_CLONE 0x1#define PXBNT$M_DELEGATE 0x2#define PXBNT$M_FILL_3 0x4#define PXBNT$M_FILL_4 0x8#define PXBNT$M_FILL_5 0x10#define PXBNT$M_FILL_6 0x20#define PXBNT$M_FILL_7 0x40#define PXBNT$M_DEBIT 0x80N#define PXBNT$K_LENGTH 88 /* Length of PXBNT structu Fre */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pxbnt {#pragma __nomember_alignmentN struct _pxbnt *pxbnt$l_flink; /* forward link */N struct _pxbnt *pxbnt$l_blink; /* backward link */N unsigned short int pxbnt$w_size; /* size, in bytes */V F unsigned char pxbnt$b_type; /* type code for PXBNT (DYN$C_SECURITY) */W unsigned char pxbnt$b_subtype; /* subtype code (DYN$C_SECURITY_PSB) */N unsigned int pxbnt$l_version; /* version number */ __union {N unsigned int pxbnt$l_flags; /* flags */ __struct {N unsigned pxbnt$v_clone : 1; /* Clone operation */N unsigned pxbnt$v_delegate : 1; /* Delega Fte operation */( unsigned pxbnt$v_fill_3 : 1;( unsigned pxbnt$v_fill_4 : 1;( unsigned pxbnt$v_fill_5 : 1;( unsigned pxbnt$v_fill_6 : 1;( unsigned pxbnt$v_fill_7 : 1;N unsigned pxbnt$v_debit : 1; /* DEBIT */N/* This bit must be in */N/* synch with PSB flag. */ } pxbnt$r_fill_2F_; } pxbnt$r_fill_1_; __union {% unsigned __int64 pxbnt$q_doi; __struct {% unsigned int pxbnt$l_doi;) unsigned int pxbnt$l_doi_pid; } pxbnt$r_fill_4_; } pxbnt$r_fill_3_;' unsigned int pxbnt$l_user_refcount;6 unsigned short int pxbnt$w_nt_owf_password_length;6 unsigned short int pxbnt$w_lm_owf_password_length;& char pxbnt$t_nt_owf_password [16];& char pxbnt$t_lm_owf_password [16];* unsigned short F int pxbnt$w_username_o;* unsigned short int pxbnt$w_username_s;( unsigned short int pxbnt$w_domain_o;( unsigned short int pxbnt$w_domain_s;2 unsigned short int pxbnt$w_user_session_key_o;2 unsigned short int pxbnt$w_user_session_key_s;0 unsigned short int pxbnt$w_lm_session_key_o;0 unsigned short int pxbnt$w_lm_session_key_s;N unsigned int pxbnt$l_data_size; /* size of data area */#if defined(__VAXC) char pxbnt$t_data[];#elseS/* Warning: Fempty char[] member for pxbnt$t_data at end of structure not created */"#endif /* #if defined(__VAXC) */ } PXBNT; #if !defined(__VAXC)3#define pxbnt$l_flags pxbnt$r_fill_1_.pxbnt$l_flagsC#define pxbnt$v_clone pxbnt$r_fill_1_.pxbnt$r_fill_2_.pxbnt$v_cloneI#define pxbnt$v_delegate pxbnt$r_fill_1_.pxbnt$r_fill_2_.pxbnt$v_delegateE#define pxbnt$v_fill_3 pxbnt$r_fill_1_.pxbnt$r_fill_2_.pxbnt$v_fill_3E#define pxbnt$v_fill_4 pxbnt$r_fill_1_.pxbnt$r_fill_2_.pxbnt$v_fill_4E#define pxbn !Ft$v_fill_5 pxbnt$r_fill_1_.pxbnt$r_fill_2_.pxbnt$v_fill_5E#define pxbnt$v_fill_6 pxbnt$r_fill_1_.pxbnt$r_fill_2_.pxbnt$v_fill_6E#define pxbnt$v_fill_7 pxbnt$r_fill_1_.pxbnt$r_fill_2_.pxbnt$v_fill_7C#define pxbnt$v_debit pxbnt$r_fill_1_.pxbnt$r_fill_2_.pxbnt$v_debit/#define pxbnt$q_doi pxbnt$r_fill_3_.pxbnt$q_doi?#define pxbnt$l_doi pxbnt$r_fill_3_.pxbnt$r_fill_4_.pxbnt$l_doiG#define pxbnt$l_doi_pid pxbnt$r_fill_3_.pxbnt$r_fill_4_.pxbnt$l_doi_pid"#endif /* #if !defined(__VAXC) */  "FN/* */N/* PXB_FLAGS - These are generic PXB flags common to all Extensions. */N/* */#define PXB$M_FILL_1 0x1#define PXB$M_FILL_2 0x2#define PXB$M_FILL_3 0x4#define PXB$M_FILL_4 0x8#define PXB$M_FILL_5 0x10#define PXB$M_FILL_6 0x20#define PXB$M_FILL_7 0x40#define PXB$M_DEBIT 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defin #Fed(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifNtypedef struct _pxb_flags { /* flags */#pragma __nomember_alignmentN unsigned pxb$v_fill_1 : 1; /* Clone operation */N unsigned pxb$v_fill_2 : 1; /* Delegate operation */ unsigned pxb$v_fill_3 : 1; unsigned pxb$v_fill_4 : 1; unsigned pxb$v_fill_5 : $F1; unsigned pxb$v_fill_6 : 1; unsigned pxb$v_fill_7 : 1;N unsigned pxb$v_debit : 1; /* DEBIT */N/* This bit must be in */N/* synch with PSB flag. */ char pxb$b_fill_5_ [3]; } PXB_FLAGS;N/* */N/* CREATE_FLAGS - Flags used for calls to CREATE_EXTENSION. %F */N/* */##define PXB$M_PRIMARY_EXTENSION 0x1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifNtypedef struct _create_flags { /* flags */#pragma __nomember_alignmentN unsigned pxb$v_primary_extension : 1; /* Clone operation &F */ unsigned pxb$v_fill_6_ : 31; } CREATE_FLAGS;N/* */N/* define the offset and size for user session key and lm session key */N/* */N#define TOKEN$K_USERSESSIONKEY_OFFSET 120 /* user session key offset */N#define TOKEN$K_USERSESSIONKEY_SIZE 16 /* user session key size */N#define TOKEN$K_LMSESSIONKEY_OFFSET 136 /* L'FM session key offset */N#define TOKEN$K_LMSESSIONKEY_SIZE 8 /* LM session key offset */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PXBDEF_LOADED */ wwì[UM/*************************************(F**************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP )F **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** *F **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */I/* Source: 01-MAY-1995 04:53:32 $1$DGA8345:[LIB_H.SRC]PXDSRRDEF.SDL;1 *//*********************************************************************************** +F*********************************************/%/*** MODULE $PXDSRRDEF IDENT X-8 ***/#ifndef __PXDSRRDEF_LOADED#define __PXDSRRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __shor,Ft /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define -FPSX$_PSX$SPARE_VMS_1 0#define PSX$_PSX$SET_MASKS 1#define PSX$_PSX$SAME_SESSION 2##define PSX$_PSX$VIP_ASTEXIT_CHMK 3#define PSX$_PSX$CHECK_CPULIM 4#define PSX$_PSX$GET_CPULIM 5#define PSX$_PSX$RDC_CPULIM 6!#define PSX$_PSX$ALLOC_P1_PAGES 7#define PSX$_PSX$TIME_MODE 8!#define PSX$_PSX$MAKE_CALLBACKS 9(#define PSX$_PSX$SYSTEM_CALLBACK_LIST 10#define PSX$_PSX$FORK_CHECK 11$#define PSX$_PSX$CALLBACK_SERVICE 12#define PSX$_PSX$SENDSEGV 13!#define PSX$_PSX$CHECK_NEW_PID 14 #d.Fefine PSX$_PSX$SPARE_VMS_16 15 #define PSX$_PSX$SPARE_VMS_17 16 #define PSX$_PSX$SPARE_VMS_18 17 #define PSX$_PSX$SPARE_VMS_19 18 #define PSX$_PSX$SPARE_VMS_20 19 #define PSX$_PSX$SPARE_VMS_21 20 #define PSX$_PSX$SPARE_VMS_22 21 #define PSX$_PSX$SPARE_VMS_23 22 #define PSX$_PSX$SPARE_VMS_24 23 #define PSX$_PSX$SPARE_VMS_25 24 #define PSX$_PSX$SPARE_VMS_26 25 #define PSX$_PSX$SPARE_VMS_27 26 #define PSX$_PSX$SPARE_VMS_28 27 #define PSX$_PSX$SPARE_VMS_29 28 #define PSX$_PSX$SPARE_VMS_30 29/F #define PSX$_PSX$SPARE_VMS_31 30 #define PSX$_PSX$SPARE_VMS_32 31 #define PSX$_PSX$SPARE_VMS_33 32 #define PSX$_PSX$SPARE_VMS_34 33 #define PSX$_PSX$SPARE_VMS_35 34 #define PSX$_PSX$SPARE_VMS_36 35 #define PSX$_PSX$SPARE_VMS_37 36 #define PSX$_PSX$SPARE_VMS_38 37 #define PSX$_PSX$SPARE_VMS_39 38 #define PSX$_PSX$SPARE_VMS_40 39#define PSX$_PSX$SEND_SIGNAL 40(#define PSX$_PSX$SEND_SIGNAL_TO_GROUP 41*#define PSX$_PSX$SEND_SIGNAL_TO_SESSION 42#define PSX$_PSX$RUNDOWN 43 #define PSX$_P0FSX$RUNDOWN_EXEC 44#define PSX$_PSX$GA_CFS_BASE 45!#define PSX$_PSX$GL_NEXT_RNDWN 46&#define PSX$_PSX$GL_NEXT_RNDWN_EXEC 47 #define PSX$_PSX$GA_SPG_TABLE 48#define PSX$_PSX$GL_SPG_SIZE 49#define PSX$_PSX$GL_SPG_HASH 50&#define PSX$_PSX$GL_MAX_FORK_IN_PRG 51'#define PSX$_PSX$GL_MAX_FORK_PERPROC 52'#define PSX$_PSX$GL_MAX_SESS_PERPROC 53$#define PSX$_PSX$GL_EXEC_ARG_SIZE 54##define PSX$_PSX$GL_FS_BUFF_SIZE 55"#define PSX$_PSX$GL_FORK_IN_PRG 56(#define PSX$_PSX$GL_DEF_PROCESS_FLAGS 1F57$#define PSX$_PSX$LOOKUP_SPG_TABLE 58&#define PSX$_PSX$GA_DEFAULT_TERMIOS 59&#define PSX$_PSX$GL_MAX_SEMS_PERPRC 60&#define PSX$_PSX$GL_MAX_SEMS_PERSYS 61#define PSX$_PSX$SPARE_15 62#define PSX$_PSX$SPARE_16 63#define PSX$_PSX$SPARE_17 64#define PSX$_PSX$SPARE_18 65#define PSX$_PSX$SPARE_19 66#define PSX$_PSX$SPARE_20 67#define PSX$_PSX$SPARE_21 68#define PSX$_PSX$SPARE_22 69#define PSX$_PSX$SPARE_23 70#define PSX$_PSX$SPARE_24 71#define PSX$_PSX$SPARE_25 72#define PSX$_P2FSX$SPARE_26 73#define PSX$_PSX$SPARE_27 74#define PSX$_PSX$SPARE_28 75#define PSX$_PSX$SPARE_29 76 #define PSX$_SUB_TOTAL_NUMBER 77#define PXDSRR$K_LENGTH 308#define PXDSRR$C_LENGTH 308 typedef struct _pxdsrr {, unsigned int pxdsrr$l_global_cells [77]; } PXDSRR;N#define PSXFRK$K_LENGTH 248 /*LENGTH OF FORK CONTEXT BLOCK */N#define PSXFRK$C_LENGTH 248 /*LENGTH OF FORK CONTEXT BLOCK */ typedef struct _psxfrk {N __int64 psxfrk$q_r2;3F /*R2 */N __int64 psxfrk$q_r3; /*R3 */N __int64 psxfrk$q_r4; /*R4 */N __int64 psxfrk$q_r5; /*R5 */N __int64 psxfrk$q_r6; /*R6 */N __int64 psxfrk$q_r7; /*R7 */N __int64 psxfrk$q_r8; /*R8 4F */N __int64 psxfrk$q_r9; /*R9 */N __int64 psxfrk$q_r10; /*R10 */N __int64 psxfrk$q_r11; /*R11 */N __int64 psxfrk$q_r12; /*R12 */N __int64 psxfrk$q_r13; /*R13 */N __int64 psxfrk$q_r14; /*R14 5F*/N __int64 psxfrk$q_r15; /*R15 */N __int64 psxfrk$q_fp; /*FP */N __int64 psxfrk$q_ra; /*RA */N __int64 psxfrk$q_esp; /*ESP */N __int64 psxfrk$q_ssp; /*SSP */N __int64 psxfrk$q_usp; /*USP */N __int64 psxfrk$q_u6Fnq; /*PROCESS UNQ */N __int64 psxfrk$q_asten; /*ASTEN */L __int64 psxfrk$q_fen_datfx; /*FEN & DATFX */N __int64 psxfrk$q_f2; /*F2 */N __int64 psxfrk$q_f3; /*F3 */N __int64 psxfrk$q_f4; /*F4 */N __int64 psxfrk$q_f5; /*F5 7F */N __int64 psxfrk$q_f6; /*F6 */N __int64 psxfrk$q_f7; /*F7 */N __int64 psxfrk$q_f8; /*F8 */N __int64 psxfrk$q_f9; /*F9 */N __int64 psxfrk$q_fpcr; /*FPCR */ } PSXFRK; $#pragma __member_alignment __restoreR#ifdef __INITIAL_P8FOINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PXDSRRDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidentia9Fl proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **:F/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************* ;F***********************************************************************************************************/=/* Created: 7-Oct-2024 15:23:38 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2021 10:16:55 $1$DGA8345:[LIB_H.SRC]PXMLDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PXMLDEF ***/#ifndef __PXMLDEF_LOADED#define __PXMLDEF_LOADED 1 G#pragma __nostandard /* This file useFation for setting up RADs. */A/* The structures must be defined in "reverse" order because */;/* of the way they reference each other. */N/* */J/* PXML_MEMORY: One per memory fragment within each locality. Contains */;/* start and end address of the fragment. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !d ?Fefined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pxml_memory {#pragma __nomember_alignmentO unsigned __int64 pxml$q_base; /* Physical base address of fragment */N unsigned __int64 pxml$q_end; /* Physical end address of fragment */ } PXML_MEMORY;N/* */J/* PXML_LOCALITY: One per populate@Fd locality. Contains locality and RAD */?/* numbers, count of CPUs (both real and ghost) and memory */>/* fragments, bitmap of CPUs, plus the calculated average */?/* & best costs and spread/variance (across all localities */A/* that contain CPUs) for access to memory in this fragment. */N/* */;/* An array of memory fragments is appended to each */=/* locality structure (first fragment is built in to the AF */;/* structure). */N/* */?/* Note 1: The spread is not a true standard deviation: no */=/* square root is taken and a multiplier (32) is used to */@/* increase accuracy because all calculations are performed */;/* on unsigned 32-bit integer values. */N/* */?/* Note 2: The MEMBF_COUNT quadword must immediately precede */B/* the first MEM_FRAGMENTS quadword pair and must be quadword */;/* aligned. */N/* */@/* Note 3: "Real" CPUs are those that actually exist in the */=/* locality. "Ghost" CPUs are those considered part of a */?/* locality because its memory is interleaved (CLM or ILM) */A/* and the CPU exists in one of the contributing loc CFalities. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pxml_locality {#pragma __nomember_alignmentN unsigned int pxml$l_locality; /* The locality number */e unsigned int pxml$l_cost; /* Offset of this locality in the DFLOCALITIES_BY_COST array */N unsigned int pxml$l_rad; /* The RAD number */h unsigned int pxml$l_locality_length; /* Length of this structure (including all memory fragments) */\ unsigned int pxml$l_average; /* Average cost to access memory in this locality */_ unsigned int pxml$l_spread; /* Spread of costs to access memory in this locality */S unsigned int pxml$l_cpu_count; /* Count of actual CPUs in this locality */g unsignedEF int pxml$l_ghost_cpus; /* Count of CPUs considered as part of this non-CPU locality */^ unsigned int pxml$l_rad_list_offset; /* Offset (from PXML base) to RAD preference array */a unsigned int pxml$l_fragment_offset; /* Offset (from PXML base) to optimized fragment list */N/* (Where holes are ignored unless there's an */N/* intervening fragment from another locality) */N/* Also used to count the number of fragments in optimiz FFed list */[ int pxml$l_base_rads [2]; /* Best ILM or CLM RAD(s) to be used by this RAD */#if defined(__VAXC) char pxml$t_fill_1[];#else'#define pxml$t_fill_1 pxml$t_cpu_bitmap"#endif /* #if defined(__VAXC) */, unsigned __int64 pxml$t_cpu_bitmap [16];N/* Bitmap of all CPUs (actual & ghost) in this locality */N unsigned __int64 pxml$q_mem_total; /* Total memory in this locality */N/* Keep the next two lines together **** GF */Y unsigned __int64 pxml$q_mem_count; /* Number of memory fragments in this locality */V PXML_MEMORY pxml$t_mem_fragments [1]; /* First memory fragment in this locality */N/* Keep the last two lines together **** */ } PXML_LOCALITY;N/* */F/* PXML: The main structure containing pointers to the saved SLIT, */B/* SRAT, and LID array, various counHFts and internal pointers. */=/* One or more pages are allocated (in S2 space) for the */R/* structure, the saved SLIT, SRAT, and LID array, and all */;/* the additional bitmaps, arrays of pointers, the */;/* PXML_LOCALITY and their PXML_MEMORY substructures, */?/* and the PA-to-RAD conversion array. All the pointers in */B/* this structure point to locations following the structure. */N/* IF */N#define PXML$C_LENGTH 112 /* Length of base PXML structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pxml {#pragma __nomember_alignmentN unsigned int pxml$l_slit_offset; /* Offset to saved SLIT */N unsigned int pxml$l_srat_offset; /* Offset to saved SRAT */N unsiJFgned int pxml$l_lid_offset; /* Offset to LID array */[ unsigned int pxml$l_locality_bitmap; /* Offset to bitmap of all populated localities */_ unsigned int pxml$l_locality_cpumap; /* Offset to bitmap of localities that contain CPUs */a unsigned int pxml$l_locality_memmap; /* Offset to bitmap of localities that contain memory */o unsigned int pxml$l_localities_by_loc; /* Three offsets to arrays of offsets to PXML_LOCALITY structures */g unsigned int pxml$l_locaKFlities_by_cost; /* ... first ordered by locality, second by spread/cost, */r unsigned int pxml$l_localities_by_rad; /* ... third in best RAD order (localities with CPUs then increasing */N/* ... spread/cost for the remainder) */V unsigned int pxml$l_pa_rad_array; /* Offset to array of PA-to-RAD conversions */U unsigned int pxml$l_next_free; /* Offset to next free location in page(s) */p unsigned int pxml$l_pxml_length; /* Length of avaLFilable area allocated (rounded up to a complete page) */N unsigned int pxml$l_slit_size; /* Size of saved SLIT */N unsigned int pxml$l_srat_size; /* Size of saved SRAT */b unsigned int pxml$l_lid_count; /* Number of entries in LID array (from HWRPB$IQ_NPROC) */T unsigned int pxml$l_localities; /* Total number of localities (from SLIT) */N unsigned int pxml$l_rads; /* Number of populated localities */N unsigned int pxml$MFl_cpus; /* Total number of CPUs */N unsigned int pxml$l_fragments; /* Total number of memory fragments */Z unsigned int pxml$l_bitmap_length; /* Length of each of the three locality bitmaps */T unsigned int pxml$l_cpu_rad_shift; /* CPU-to-RAD shift value (or 0xFFFFFFFF) */_ unsigned int pxml$l_pa_rad_entries; /* Eventual number of entries in the PA-to-RAD array */X unsigned int pxml$l_syimap_offset; /* Offset to the saved copy of the memory map */V NF unsigned int pxml$l_syimap_entries; /* Number of entries used in the memory map */^ unsigned int pxml$l_syimap_allocated; /* Number of entries allocated for the memory map */V int pxml$l_base_rad; /* Best ILM or CLM RAD (first in cost list) */O int pxml$l_alt_base_rad; /* Second base RAD (if there is one) */g char pxml$t_fill_2 [4]; /* Ensure the base structure is an exact number of quadwords */ } PXML;N/* All calculations of average andOF spread/deviation are done as 32-bit */N/* unsigned integers. Therefore, in order to improve the accuracy */N/* (or granularity) we apply a shift factor to the raw values. If set */N/* too low, we don't gain enough accuracy. If set too large, the squared */N/* sums will exceed a longword. Right now we're using 5 (i.e. multiply */N/* by 32). */#define PXML$C_SPREAD_SHIFT 5N/* The initial space used toPF build the PXML and its substructures is */N/* allocated within the module that initializes it (in SYSBOOT or */N/* EXEC_INIT). Later it is copied to pages in "fair" memory for use */N/* by the running system. Right now we're allocating eight pages. */#define PXML$C_PXML_SIZE 65536R/* If a RAD has little memory (less than or equal to PXML$C_MINIMUM_RAD_MEMORY) */P/* then it probably only has firmware-reserved space. If there's only one RAD */N/* with more tha QFn this amount of memory, consider the system to be all-ILM */Q/* and don't set up RADs. PXML$C_MINIMUM_RAD_MEMORY is currently set at 256MB. */+#define PXML$C_MINIMUM_RAD_MEMORY 268435456 #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */@typedef PXML * PXML_PQ; /* Pointer to a PXML structure. */Vtypedef PXML_LOCALITY * PXML_LOCALITY_PQ; /* Pointer to a PXML RF_LOCALITY structure. */dtypedef PXML_LOCALITY ** PXML_LOCALITY_PPQ; /* Pointer to a pointer to a PXML_LOCALITY structure. */Rtypedef PXML_MEMORY * PXML_MEMORY_PQ; /* Pointer to a PXML_MEMORY structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else!typedef unsigned __int64 PXML_PQ;*typedef unsigned __int64 PXML_LOCALITY_PQ;+typedef unsigned __int64 PXML_LOCALITY_PPQ;(typedef unsigned __int64 PXML_MEMORY_PQ;##endif /* __INITIAL_POINTER_SIZE *SF/  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PXMLDEF_LOADED */ ww[UM/***************************************************************************/M/** TF **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOUFFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************************VF****************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */H/* Source: 31-MAR-1998 13:28:17 $1$DGA8345:[LIB_H.SRC]PYXISDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PYXISDEF ***/#ifndef __PYXISDEF_LOADED#def WFine __PYXISDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknXFown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define PYXIS$L_NODE_PA_H 135 /* High order word */*#define PYXIS$L_PYXIS_CONTROL_L 1073741824(#def YFine PYXIS$L_PYXIS_ERROR_L 1073774592)#define PYXIS$L_PYXIS_MEMORY_L 1342177280+#define PYXIS$L_PYXIS_PCI_ADDR_L 1610612736/#define PYXIS$L_PYXIS_CLOCK_RESET_L -2147483648/#define PYXIS$L_PYXIS_SERVER_MGMT_L -1879048192-#define PYXIS$L_PYXIS_INTERRUPT_L -1610612736##define PYXIS$L_CUSCO_L -1072693248N#define PYXIS$K_PCI_REV 128 /*PCI revision */N#define PYXIS$K_PCI_LAT 192 /*PCI Latency */N#define PYXIS$K_PYXIS_CTRL 256 ZF /*PYXIS COntrol */N#define PYXIS$K_PYXIS_CTRL1 320 /*PYXIS COntrol */N#define PYXIS$K_PYXIS_FLASH_CTRL 512 /*Flash COntrol */N#define PYXIS$K_HAE_MEM 1024 /*HAE memory */N#define PYXIS$K_HAE_IO 1088 /*HAE I/O */N#define PYXIS$K_HAE_CFG 1152 /*COnfig */N#define PYXIS$K_PYXIS_DIAG 8192 /*Diag control [F */N#define PYXIS$K_PYXIS_CHECK 12288 /*Diag check */N#define PYXIS$K_PERF_MON 16384 /*Perf monitor */N#define PYXIS$K_PERF_CNTR 16448 /*Perf control */N#define PYXIS$K_PYXIS_ERR_REG 512 /*PYXIS status */N#define PYXIS$K_PYXIS_STAT 576 /*PYXIS status */N#define PYXIS$K_PYXIS_ERR_MSK 640 /*PYXIS err mask */N#def\Fine PYXIS$K_PYXIS_SYN 768 /*PYXIS syndrome */N#define PYXIS$K_PYXIS_ERR_DATA 776 /*PYXIS error data */N#define PYXIS$K_CPU_MEAR 1024 /*Mem Error Address */N#define PYXIS$K_CPU_MESR 1088 /*Mem Error Status */N#define PYXIS$K_PCI_ERR0 2048 /*PCI Err 0 */N#define PYXIS$K_PCI_ERR1 2112 /*PCI Err 1 */N#define PYXIS$K_PCI_ERR2 2176 ]F /*PCI Err 1 */N#define PYXIS$K_MEM_CONTROL 0 /*Memory config */!#define PYXIS$K_MEM_CLOCK_MASK 64#define PYXIS$K_MEM_GTR 512#define PYXIS$K_MEM_RTR 768#define PYXIS$K_MEM_RHPR 1024#define PYXIS$K_MEM_MDR1 1280#define PYXIS$K_MEM_MDR2 1344N#define PYXIS$K_MEM_BA0 1536 /*Mem base addr0 */N#define PYXIS$K_MEM_BA1 1600 /*Mem base addr2 */N#define PYXIS$K_MEM_BA2 ^F1664 /*Mem base addr4 */N#define PYXIS$K_MEM_BA3 1728 /*Mem base addr6 */N#define PYXIS$K_MEM_BA4 1792 /*Mem base addr8 */N#define PYXIS$K_MEM_BA5 1856 /*Mem base addrA */N#define PYXIS$K_MEM_BA6 1920 /*Mem base addrC */N#define PYXIS$K_MEM_BA7 1984 /*Mem base addrE */N#define PYXIS$K_MEM_BC0 2048 /*Mem base_F contr0 */N#define PYXIS$K_MEM_BC1 2112 /*Mem base contr2 */N#define PYXIS$K_MEM_BC2 2176 /*Mem base contr4 */N#define PYXIS$K_MEM_BC3 2240 /*Mem base contr6 */N#define PYXIS$K_MEM_BC4 2304 /*Mem base contr8 */N#define PYXIS$K_MEM_BC5 2368 /*Mem base contrA */N#define PYXIS$K_MEM_BC6 2432 /*Mem base contrC `F*/N#define PYXIS$K_MEM_BC7 2496 /*Mem base contrE */N#define PYXIS$K_MEM_BTR0 2560 /*Mem base timing0 */N#define PYXIS$K_MEM_BTR1 2624 /*Mem base timing2 */N#define PYXIS$K_MEM_BTR2 2688 /*Mem base timing4 */N#define PYXIS$K_MEM_BTR3 2752 /*Mem base timing6 */N#define PYXIS$K_MEM_BTR4 2816 /*Mem base timing8 */N#define PYXIS$K_MEM_BTaFR5 2880 /*Mem base timingA */N#define PYXIS$K_MEM_BTR6 2944 /*Mem base timingC */N#define PYXIS$K_MEM_BTR7 3008 /*Mem base timingE */N#define PYXIS$K_MEM_CVM 3072 /*cache valid mask */N#define PYXIS$K_MEM_TBIA 3072 /*cache valid mask */N#define PYXIS$K_MEM_TMG0 2816 /*Mem timing 0 */N#define PYXIS$K_MEM_TMG1 2880 /*Mem tibFming 1 */N#define PYXIS$K_MEM_TMG2 2944 /*Mem timing 2 */N#define PYXIS$K_PCI_TBIA 256 /*SG TB inval */N#define PYXIS$K_PCI_W0_BASE 1024 /*Window base0 */N#define PYXIS$K_PCI_W0_MASK 1088 /*Window mask0 */N#define PYXIS$K_PCI_T0_BASE 1152 /*Trans base0 */N#define PYXIS$K_PCI_W1_BASE 1280 /*Window base1 cF */N#define PYXIS$K_PCI_W1_MASK 1344 /*Window mask1 */N#define PYXIS$K_PCI_T1_BASE 1408 /*Trans base1 */N#define PYXIS$K_PCI_W2_BASE 1536 /*Window base2 */N#define PYXIS$K_PCI_W2_MASK 1600 /*Window mask2 */N#define PYXIS$K_PCI_T2_BASE 1664 /*Trans base2 */N#define PYXIS$K_PCI_W3_BASE 1792 /*Window base3 */N#define PYXIS$K_PCI_dFW3_MASK 1856 /*Window mask3 */N#define PYXIS$K_PCI_T3_BASE 1920 /*Trans base3 */N#define PYXIS$K_PCI_DAC_BASE 1984 /*DAC Base */N#define PYXIS$K_PCI_LTB_TAG0 2048 /*Lock TB tag0 */N#define PYXIS$K_PCI_LTB_TAG1 2112 /*Lock TB tag1 */N#define PYXIS$K_PCI_LTB_TAG2 2176 /*Lock TB tag2 */N#define PYXIS$K_PCI_LTB_TAG3 2240 /*LockeF TB tag3 */N#define PYXIS$K_PCI_TB_TAG0 2304 /* TB tag0 */N#define PYXIS$K_PCI_TB_TAG1 2368 /* TB tag1 */N#define PYXIS$K_PCI_TB_TAG2 2432 /* TB tag2 */N#define PYXIS$K_PCI_TB_TAG3 2496 /* TB tag3 */N#define PYXIS$K_PCI_TB0_PAGE0 4096 /* TB0 page0 */N#define PYXIS$K_PCI_TB0_PAGE1 4160 /* TB0 page1 fF */N#define PYXIS$K_PCI_TB0_PAGE2 4224 /* TB0 page2 */N#define PYXIS$K_PCI_TB0_PAGE3 4288 /* TB0 page3 */N#define PYXIS$K_PCI_TB1_PAGE0 4352 /* TB1 page0 */N#define PYXIS$K_PCI_TB1_PAGE1 4416 /* TB1 page1 */N#define PYXIS$K_PCI_TB1_PAGE2 4480 /* TB1 page2 */N#define PYXIS$K_PCI_TB1_PAGE3 4544 /* TB1 page3 */N#define PYXIS$K_PCgFI_TB2_PAGE0 4608 /* TB2 page0 */N#define PYXIS$K_PCI_TB2_PAGE1 4672 /* TB2 page1 */N#define PYXIS$K_PCI_TB2_PAGE2 4736 /* TB2 page2 */N#define PYXIS$K_PCI_TB2_PAGE3 4800 /* TB2 page3 */N#define PYXIS$K_PCI_TB3_PAGE0 4864 /* TB3 page0 */N#define PYXIS$K_PCI_TB3_PAGE1 4928 /* TB3 page1 */N#define PYXIS$K_PCI_TB3_PAGE2 4992 /* ThFB3 page2 */N#define PYXIS$K_PCI_TB3_PAGE3 5056 /* TB3 page3 */N#define PYXIS$K_PCI_TB4_PAGE0 5120 /* TB4 page0 */N#define PYXIS$K_PCI_TB4_PAGE1 5184 /* TB4 page1 */N#define PYXIS$K_PCI_TB4_PAGE2 5248 /* TB4 page2 */N#define PYXIS$K_PCI_TB4_PAGE3 5312 /* TB4 page3 */N#define PYXIS$K_PCI_TB5_PAGE0 5376 /* TB5 page0 iF */N#define PYXIS$K_PCI_TB5_PAGE1 5440 /* TB5 page1 */N#define PYXIS$K_PCI_TB5_PAGE2 5504 /* TB5 page2 */N#define PYXIS$K_PCI_TB5_PAGE3 5568 /* TB5 page3 */N#define PYXIS$K_PCI_TB6_PAGE0 5632 /* TB6 page0 */N#define PYXIS$K_PCI_TB6_PAGE1 5696 /* TB6 page1 */N#define PYXIS$K_PCI_TB6_PAGE2 5760 /* TB6 page2 */N#define PYXIS$K_ jFPCI_TB6_PAGE3 5824 /* TB6 page3 */N#define PYXIS$K_PCI_TB7_PAGE0 5888 /* TB7 page0 */N#define PYXIS$K_PCI_TB7_PAGE1 5952 /* TB7 page1 */N#define PYXIS$K_PCI_TB7_PAGE2 6016 /* TB7 page2 */N#define PYXIS$K_PCI_TB7_PAGE3 6080 /* TB7 page3 */#define PYXIS$K_CLOCK_CONFIG 0#define PYXIS$K_RESET 2304#define PYXIS$K_FAN_ACCUM 0#define PYXIS$K_FAN_CTL 64#defkFine PYXIS$K_FAN_THRESH 128#define PYXIS$K_POWER_CTL 192#define PYXIS$K_PWRDWN_TIM 256#define PYXIS$K_POWER_STATE 320#define PYXIS$K_INT_REQ 0#define PYXIS$K_INT_MASK 64#define PYXIS$K_INT_HILO 192#define PYXIS$K_INT_ROUTE 320#define PYXIS$K_GPO 384#define PYXIS$K_INT_CNFG 448#define PYXIS$K_RT_COUNT 512#define PYXIS$K_INT_TIME 576#define PYXIS$K_IIC_CTRL 704#define PYXIS$K_CLOCK_1286 64#define PYXIS$K_COMMAND_1286 75#define PYXIS$K_WDOG_1286 76#define PYXIS$K_VDlFIVR 128#define PYXIS$K_V1ISR 129#define PYXIS$K_V2ISR 130#define PYXIS$K_V3ISR 131#define PYXIS$K_VDIER 132#define PYXIS$K_V1IER 133#define PYXIS$K_V2IER 134#define PYXIS$K_V3IER 135#define PYXIS$K_VMCSR 136#define PYXIS$K_VACSR 138#define PYXIS$K_BIDR 139#define PYXIS$K_VSICSR0 160#define PYXIS$K_VSICSR1 161#define PYXIS$K_VSICSR2 162#define PYXIS$K_VSICSR3 163#define PYXIS$K_VSICSR4 164#define PYXIS$K_VSICSR5 165#define PYXIS$K_VSICSR6 166#define mFPYXIS$K_VSICSR9 169#define PYXIS$K_VSICSRA 170#define PYXIS$K_VSICSRB 171#define PYXIS$K_VSICSRC 172#define PYXIS$K_VSICSR11 177#define PYXIS$K_VSICSR12 178#define PYXIS$K_VSICSR13 179#define PYXIS$K_VSICSR14 180#define PYXIS$K_VSICSR15 181#define PYXIS$K_VSICSR16 182#define PYXIS$K_VSICSR17 183%#define PYXIS$M_PYXIS_CTRL_PCI_EN 0x1*#define PYXIS$M_PYXIS_CTRL_PCI_LOCK_EN 0x2*#define PYXIS$M_PYXIS_CTRL_PCI_LOOP_EN 0x4(#define PYXIS$M_PYXIS_CTRL_FST_BB_EN 0x8&#define PYXIS$ nFM_PYXIS_CTRL_MST_EN 0x10&#define PYXIS$M_PYXIS_CTRL_MEM_EN 0x20(#define PYXIS$M_PYXIS_CTRL_REQ64_EN 0x40(#define PYXIS$M_PYXIS_CTRL_ACK64_EN 0x80+#define PYXIS$M_PYXIS_CTRL_ADDR_PE_EN 0x100(#define PYXIS$M_PYXIS_CTRL_PERR_EN 0x200,#define PYXIS$M_PYXIS_CTRL_FILL_ERR_EN 0x400,#define PYXIS$M_PYXIS_CTRL_ECC_CHK_EN 0x1000,#define PYXIS$M_PYXIS_CTRL_CACK_EN_PE 0x2000-#define PYXIS$M_PYXIS_CTRL_CON_IDLE_BC 0x4000-#define PYXIS$M_PYXIS_CTRL_CSR_IOA_BYP 0x8000/#define PYXIS$M_PYXIS_CTRL_IO_FLUS oFH_REQ 0x100000#define PYXIS$M_PYXIS_CTRL_CPU_FLUSH_REQ 0x20000-#define PYXIS$M_PYXIS_CTRL_ARB_EV5_EN 0x40000.#define PYXIS$M_PYXIS_CTRL_EN_ARB_LINK 0x80000*#define PYXIS$M_PYXIS_CTRL_RD_TYP 0x300000+#define PYXIS$M_PYXIS_CTRL_RL_TYP 0x3000000,#define PYXIS$M_PYXIS_CTRL_RM_TYP 0x30000000'#define PYXIS$M_PYXIS_CTRL1_IOA_BEN 0x1-#define PYXIS$M_PYXIS_CTRL1_PCI_MWIN_ENA 0x10.#define PYXIS$M_PYXIS_CTRL1_PCI_LINK_ENA 0x100.#define PYXIS$M_PYXIS_CTRL1_LW_PAR_MODE 0x1000*#define PYXIS$M_PYXIS_pFCNFG_PCI_WIDTH 0x100,#define PYXIS$M_PYXIS_CNFG_IOD_WIDTH 0x10000"#define PYXIS$M_HAE_MEM_REG_3 0xFC$#define PYXIS$M_HAE_MEM_REG_2 0xF800(#define PYXIS$M_HAE_MEM_REG_1 0xE0000000!#define PYXIS$M_HAE_IO 0xFE000000#define PYXIS$M_FROM_EN 0x1#define PYXIS$M_USE_CHECK 0x2"#define PYXIS$M_FPE_PCI 0x30000000%#define PYXIS$M_FPE_TO_EV5 0x80000000 #define PYXIS$M_ERR_CORR_ECC 0x1#define PYXIS$M_ERR_UNC_ECC 0x2#define PYXIS$M_ERR_CPU_PE 0x4#define PYXIS$M_ERR_MEM_NEM 0x8!#define PYXIS$qFM_ERR_PCI_SERR 0x10!#define PYXIS$M_ERR_PCI_PERR 0x20##define PYXIS$M_ERR_PCI_ADR_PE 0x40 #define PYXIS$M_ERR_M_ABORT 0x80!#define PYXIS$M_ERR_T_ABORT 0x100$#define PYXIS$M_ERR_PA_PTE_INV 0x200%#define PYXIS$M_ERR_IOA_TIMEOUT 0x800)#define PYXIS$M_ERR_LOST_CORR_ECC 0x10000(#define PYXIS$M_ERR_LOST_UNC_ECC 0x20000'#define PYXIS$M_ERR_LOST_CPU_PE 0x40000(#define PYXIS$M_ERR_LOST_MEM_NEM 0x80000*#define PYXIS$M_ERR_LOST_PCI_PERR 0x200000,#define PYXIS$M_ERR_LOST_PCI_ADR_PE 0x400000)#drFefine PYXIS$M_ERR_LOST_M_ABORT 0x800000*#define PYXIS$M_ERR_LOST_T_ABORT 0x1000000-#define PYXIS$M_ERR_LOST_PA_PTE_INV 0x2000000.#define PYXIS$M_ERR_LOST_IOA_TIMEOUT 0x8000000$#define PYXIS$M_ERR_VALID 0x80000000#define PYXIS$M_STAT_PCI_0 0x1#define PYXIS$M_STAT_PCI_1 0x2##define PYXIS$M_STAT_IOA_VALID 0xF0##define PYXIS$M_STAT_TLB_MISS 0x800%#define PYXIS$M_MASK_CORR_ECC_ERR 0x1$#define PYXIS$M_MASK_UNC_ECC_ERR 0x2#define PYXIS$M_MASK_CPU_PE 0x4 #define PYXIS$M_MASK_MEM_NEM 0x8" sF#define PYXIS$M_MASK_PCI_SERR 0x10"#define PYXIS$M_MASK_PCI_PERR 0x20$#define PYXIS$M_MASK_PCI_ADR_PE 0x40!#define PYXIS$M_MASK_M_ABORT 0x80"#define PYXIS$M_MASK_T_ABORT 0x100%#define PYXIS$M_MASK_PA_PTE_INV 0x200&#define PYXIS$M_MASK_IOA_TIMEOUT 0x800$#define PYXIS$M_PYXIS_SYNDROME0 0xFF&#define PYXIS$M_PYXIS_SYNDROME1 0xFF00-#define PYXIS$M_PYXIS_RAW_CHECK_BITS 0xFF0000(#define PYXIS$M_PYXIS_SYND_CE0 0x1000000(#define PYXIS$M_PYXIS_SYND_CE1 0x2000000)#define PYXIS$M_PYXIS_SYND_UCE0 0xtF4000000)#define PYXIS$M_PYXIS_SYND_UCE1 0x8000000&#define PYXIS$M_MEAR_ADDR_H 0xFFFFFFF0##define PYXIS$M_MESR_ADDR_3932 0xFF%#define PYXIS$M_MESR_DMA_RD_NXM 0x100%#define PYXIS$M_MESR_DMA_WR_NXM 0x200%#define PYXIS$M_MESR_CPU_RD_NXM 0x400%#define PYXIS$M_MESR_CPU_WR_NXM 0x800%#define PYXIS$M_MESR_IO_RD_NXM 0x1000%#define PYXIS$M_MESR_IO_WR_NXM 0x2000&#define PYXIS$M_MESR_VICTIM_NXM 0x4000'#define PYXIS$M_MESR_TLBFILL_NXM 0x8000(#define PYXIS$M_MESR_OWORD_INDEX 0x30000-#define PYuFXIS$M_MESR_DATA_CYCLE_TYP 0x1F00000&#define PYXIS$M_MESR_SEQ_ST 0xFE000000 #define PYXIS$M_PCIE_DMA_CMD 0xF!#define PYXIS$M_PCIE_DMA_DAC 0x20!#define PYXIS$M_PCIE_WINDOW 0xF00'#define PYXIS$M_PCIE_MSTR_STATE 0xF0000(#define PYXIS$M_PCIE_TRGT_STATE 0xF00000&#define PYXIS$M_PCIE_PCI_CMD 0xF000000'#define PYXIS$M_PCIE_PCI_DAC 0x10000000 #define PYXIS$M_MCR_MODE_REQ 0x1%#define PYXIS$M_MCR_SERVER_MODE 0x100%#define PYXIS$M_MCR_BCACHE_STAT 0x200##define PYXIS$M_MCR_BCACHE_EN 0x400)#def vFine PYXIS$M_MCR_PIPELINED_CACHE 0x800&#define PYXIS$M_MCR_OVERLAP_DIS 0x1000$#define PYXIS$M_MCR_SEQ_TRACE 0x2000##define PYXIS$M_MCR_CKE_AUTO 0x4000(#define PYXIS$M_MCR_DRAM_CLK_AUTO 0x8000(#define PYXIS$M_MCR_DRAM_MODE 0x3FFF0000+#define PYXIS$M_MCMR_DRAM_CLOCK_MASK 0xFFFF$#define PYXIS$M_MGTR_MIN_RAS_PRE 0x7!#define PYXIS$M_MGTR_CAS_LAT 0x30(#define PYXIS$M_MGTR_IDLE_BC_WIDTH 0x700##define PYXIS$M_MRTR_REF_WIDTH 0x70##define PYXIS$M_MRTR_REF_INT 0x1F80%#define PYXIS$M_MRTR_FORCE_RwFEF 0x8000(#define PYXIS$M_MRPHR_POLICY_MASK 0xFFFF#define PYXIS$M_MDR1_SEL0 0x3F #define PYXIS$M_MDR1_SEL1 0x3F00"#define PYXIS$M_MDR1_SEL2 0x3F0000$#define PYXIS$M_MDR1_SEL3 0x3F000000&#define PYXIS$M_MDR1_ENABLE 0x80000000#define PYXIS$M_MDR2_SEL0 0x3F #define PYXIS$M_MDR2_SEL1 0x3F00"#define PYXIS$M_MDR2_SEL2 0x3F0000$#define PYXIS$M_MDR2_SEL3 0x3F000000&#define PYXIS$M_MDR2_ENABLE 0x80000000+#define PYXIS$M_BBAR0_BASE_ADDR_3324 0xFFC0+#define PYXIS$M_BBAR1_BASE_ADDR_3324 0xFFC0+ xF#define PYXIS$M_BBAR2_BASE_ADDR_3324 0xFFC0+#define PYXIS$M_BBAR3_BASE_ADDR_3324 0xFFC0+#define PYXIS$M_BBAR4_BASE_ADDR_3324 0xFFC0+#define PYXIS$M_BBAR5_BASE_ADDR_3324 0xFFC0+#define PYXIS$M_BBAR6_BASE_ADDR_3324 0xFFC0+#define PYXIS$M_BBAR7_BASE_ADDR_3324 0xFFC0%#define PYXIS$M_MBCR0_BANK_ENABLE 0x1$#define PYXIS$M_MBCR0_BANK_SIZE 0x1E)#define PYXIS$M_MBCR0_SUBBANK_ENABLE 0x20!#define PYXIS$M_MBCR0_COLSEL 0x40 #define PYXIS$M_MBCR0_4BANK 0x80%#define PYXIS$M_MBCR1_BANK_ENABLE 0x1yF$#define PYXIS$M_MBCR1_BANK_SIZE 0x1E)#define PYXIS$M_MBCR1_SUBBANK_ENABLE 0x20!#define PYXIS$M_MBCR1_COLSEL 0x40 #define PYXIS$M_MBCR1_4BANK 0x80%#define PYXIS$M_MBCR2_BANK_ENABLE 0x1$#define PYXIS$M_MBCR2_BANK_SIZE 0x1E)#define PYXIS$M_MBCR2_SUBBANK_ENABLE 0x20!#define PYXIS$M_MBCR2_COLSEL 0x40 #define PYXIS$M_MBCR2_4BANK 0x80%#define PYXIS$M_MBCR3_BANK_ENABLE 0x1$#define PYXIS$M_MBCR3_BANK_SIZE 0x1E)#define PYXIS$M_MBCR3_SUBBANK_ENABLE 0x20!#define PYXIS$M_MBCR3_COLSEL 0x40 #dzFefine PYXIS$M_MBCR3_4BANK 0x80%#define PYXIS$M_MBCR4_BANK_ENABLE 0x1$#define PYXIS$M_MBCR4_BANK_SIZE 0x1E)#define PYXIS$M_MBCR4_SUBBANK_ENABLE 0x20!#define PYXIS$M_MBCR4_COLSEL 0x40 #define PYXIS$M_MBCR4_4BANK 0x80%#define PYXIS$M_MBCR5_BANK_ENABLE 0x1$#define PYXIS$M_MBCR5_BANK_SIZE 0x1E)#define PYXIS$M_MBCR5_SUBBANK_ENABLE 0x20!#define PYXIS$M_MBCR5_COLSEL 0x40 #define PYXIS$M_MBCR5_4BANK 0x80%#define PYXIS$M_MBCR6_BANK_ENABLE 0x1$#define PYXIS$M_MBCR6_BANK_SIZE 0x1E)#define PYXI{FS$M_MBCR6_SUBBANK_ENABLE 0x20!#define PYXIS$M_MBCR6_COLSEL 0x40 #define PYXIS$M_MBCR6_4BANK 0x80%#define PYXIS$M_MBCR7_BANK_ENABLE 0x1$#define PYXIS$M_MBCR7_BANK_SIZE 0x1E)#define PYXIS$M_MBCR7_SUBBANK_ENABLE 0x20!#define PYXIS$M_MBCR7_COLSEL 0x40 #define PYXIS$M_MBCR7_4BANK 0x80'#define PYXIS$M_MBTR0_ROW_ADDR_HOLD 0x7"#define PYXIS$M_MBTR0_TOSHIBA 0x10&#define PYXIS$M_MBTR0_SLOW_CHARGE 0x20'#define PYXIS$M_MBTR1_ROW_ADDR_HOLD 0x7"#define PYXIS$M_MBTR1_TOSHIBA 0x10&#define PYXIS$M_|FMBTR1_SLOW_CHARGE 0x20'#define PYXIS$M_MBTR2_ROW_ADDR_HOLD 0x7"#define PYXIS$M_MBTR2_TOSHIBA 0x10&#define PYXIS$M_MBTR2_SLOW_CHARGE 0x20'#define PYXIS$M_MBTR3_ROW_ADDR_HOLD 0x7"#define PYXIS$M_MBTR3_TOSHIBA 0x10&#define PYXIS$M_MBTR3_SLOW_CHARGE 0x20'#define PYXIS$M_MBTR4_ROW_ADDR_HOLD 0x7"#define PYXIS$M_MBTR4_TOSHIBA 0x10&#define PYXIS$M_MBTR4_SLOW_CHARGE 0x20'#define PYXIS$M_MBTR5_ROW_ADDR_HOLD 0x7"#define PYXIS$M_MBTR5_TOSHIBA 0x10&#define PYXIS$M_MBTR5_SLOW_CHARGE 0x20'#define PY}FXIS$M_MBTR6_ROW_ADDR_HOLD 0x7"#define PYXIS$M_MBTR6_TOSHIBA 0x10&#define PYXIS$M_MBTR6_SLOW_CHARGE 0x20'#define PYXIS$M_MBTR7_ROW_ADDR_HOLD 0x7"#define PYXIS$M_MBTR7_TOSHIBA 0x10&#define PYXIS$M_MBTR7_SLOW_CHARGE 0x20/#define PYXIS$M_CVM_CACHE_VALID_MASK 0x7FFFFFFF$#define PYXIS$M_TBIA_CSR_WR_DATA 0x3#define PYXIS$M_WBASE0_W_EN 0x1 #define PYXIS$M_WBASE0_SG_EN 0x2##define PYXIS$M_WBASE0_MEMCS_EN 0x4!#define PYXIS$M_WBASE0_DAC_EN 0x8&#define PYXIS$M_WBASE0_BASE 0xFFF00000&#define PY~FXIS$M_WMASK0_MASK 0xFFF00000&#define PYXIS$M_TBASE0_BASE 0xFFFFFF00#define PYXIS$M_WBASE1_W_EN 0x1 #define PYXIS$M_WBASE1_SG_EN 0x2##define PYXIS$M_WBASE1_MEMCS_EN 0x4!#define PYXIS$M_WBASE1_DAC_EN 0x8&#define PYXIS$M_WBASE1_BASE 0xFFF00000&#define PYXIS$M_WMASK1_MASK 0xFFF00000&#define PYXIS$M_TBASE1_BASE 0xFFFFFF00#define PYXIS$M_WBASE2_W_EN 0x1 #define PYXIS$M_WBASE2_SG_EN 0x2##define PYXIS$M_WBASE2_MEMCS_EN 0x4!#define PYXIS$M_WBASE2_DAC_EN 0x8&#define PYXIS$M_WBASE2_BASE 0xFFFF00000&#define PYXIS$M_WMASK2_MASK 0xFFF00000&#define PYXIS$M_TBASE2_BASE 0xFFFFFF00#define PYXIS$M_WBASE3_W_EN 0x1 #define PYXIS$M_WBASE3_SG_EN 0x2##define PYXIS$M_WBASE3_MEMCS_EN 0x4!#define PYXIS$M_WBASE3_DAC_EN 0x8&#define PYXIS$M_WBASE3_BASE 0xFFF00000&#define PYXIS$M_WMASK3_MASK 0xFFF00000&#define PYXIS$M_TBASE3_BASE 0xFFFFFF00#define PYXIS$M_DAC_BASE 0xFF#define PYXIS$M_LTB0_VALID 0x1#define PYXIS$M_LTB0_LOCKED 0x2#define PYXIS$M_LTB0_DAC 0x4##define PYXIS$M_LTB0_TAG 0xFFFFF8000#define PYXIS$M_LTB1_VALID 0x1#define PYXIS$M_LTB1_LOCKED 0x2#define PYXIS$M_LTB1_DAC 0x4##define PYXIS$M_LTB1_TAG 0xFFFF8000#define PYXIS$M_LTB2_VALID 0x1#define PYXIS$M_LTB2_LOCKED 0x2#define PYXIS$M_LTB2_DAC 0x4##define PYXIS$M_LTB2_TAG 0xFFFF8000#define PYXIS$M_LTB3_VALID 0x1#define PYXIS$M_LTB3_LOCKED 0x2#define PYXIS$M_LTB3_DAC 0x4##define PYXIS$M_LTB3_TAG 0xFFFF8000#define PYXIS$M_TB0_VALID 0x1#define PYXIS$M_TB0_DAC 0x4"#define PYXIS$M_TB0_TAG 0xFFFF80F00#define PYXIS$M_TB1_VALID 0x1#define PYXIS$M_TB1_DAC 0x4"#define PYXIS$M_TB1_TAG 0xFFFF8000#define PYXIS$M_TB2_VALID 0x1#define PYXIS$M_TB2_DAC 0x4"#define PYXIS$M_TB2_TAG 0xFFFF8000#define PYXIS$M_TB3_VALID 0x1#define PYXIS$M_TB3_DAC 0x4"#define PYXIS$M_TB3_TAG 0xFFFF8000##define PYXIS$M_TB0_PAGE0_VALID 0x1'#define PYXIS$M_TB0_PAGE0_ADDR 0x3FFFFE##define PYXIS$M_TB0_PAGE1_VALID 0x1'#define PYXIS$M_TB0_PAGE1_ADDR 0x3FFFFE##define PYXIS$M_TB0_PAGE2_VALID 0x1'#define PY FXIS$M_TB0_PAGE2_ADDR 0x3FFFFE##define PYXIS$M_TB0_PAGE3_VALID 0x1'#define PYXIS$M_TB0_PAGE3_ADDR 0x3FFFFE##define PYXIS$M_TB1_PAGE0_VALID 0x1'#define PYXIS$M_TB1_PAGE0_ADDR 0x3FFFFE##define PYXIS$M_TB1_PAGE1_VALID 0x1'#define PYXIS$M_TB1_PAGE1_ADDR 0x3FFFFE##define PYXIS$M_TB1_PAGE2_VALID 0x1'#define PYXIS$M_TB1_PAGE2_ADDR 0x3FFFFE##define PYXIS$M_TB1_PAGE3_VALID 0x1'#define PYXIS$M_TB1_PAGE3_ADDR 0x3FFFFE##define PYXIS$M_TB2_PAGE0_VALID 0x1'#define PYXIS$M_TB2_PAGE0_ADDR 0x3FFFFFE##define PYXIS$M_TB2_PAGE1_VALID 0x1'#define PYXIS$M_TB2_PAGE1_ADDR 0x3FFFFE##define PYXIS$M_TB2_PAGE2_VALID 0x1'#define PYXIS$M_TB2_PAGE2_ADDR 0x3FFFFE##define PYXIS$M_TB2_PAGE3_VALID 0x1'#define PYXIS$M_TB2_PAGE3_ADDR 0x3FFFFE##define PYXIS$M_TB3_PAGE0_VALID 0x1'#define PYXIS$M_TB3_PAGE0_ADDR 0x3FFFFE##define PYXIS$M_TB3_PAGE1_VALID 0x1'#define PYXIS$M_TB3_PAGE1_ADDR 0x3FFFFE##define PYXIS$M_TB3_PAGE2_VALID 0x1'#define PYXIS$M_TB3_PAGE2_ADDR 0x3FFFFE##define PYXIS$M_TB3_FPAGE3_VALID 0x1'#define PYXIS$M_TB3_PAGE3_ADDR 0x3FFFFE##define PYXIS$M_TB4_PAGE0_VALID 0x1'#define PYXIS$M_TB4_PAGE0_ADDR 0x3FFFFE##define PYXIS$M_TB4_PAGE1_VALID 0x1'#define PYXIS$M_TB4_PAGE1_ADDR 0x3FFFFE##define PYXIS$M_TB4_PAGE2_VALID 0x1'#define PYXIS$M_TB4_PAGE2_ADDR 0x3FFFFE##define PYXIS$M_TB4_PAGE3_VALID 0x1'#define PYXIS$M_TB4_PAGE3_ADDR 0x3FFFFE##define PYXIS$M_TB5_PAGE0_VALID 0x1'#define PYXIS$M_TB5_PAGE0_ADDR 0x3FFFFE##define PYXIS$M_TB5_PAGE1_VALID 0x1'#define FPYXIS$M_TB5_PAGE1_ADDR 0x3FFFFE##define PYXIS$M_TB5_PAGE2_VALID 0x1'#define PYXIS$M_TB5_PAGE2_ADDR 0x3FFFFE##define PYXIS$M_TB5_PAGE3_VALID 0x1'#define PYXIS$M_TB5_PAGE3_ADDR 0x3FFFFE##define PYXIS$M_TB6_PAGE0_VALID 0x1'#define PYXIS$M_TB6_PAGE0_ADDR 0x3FFFFE##define PYXIS$M_TB6_PAGE1_VALID 0x1'#define PYXIS$M_TB6_PAGE1_ADDR 0x3FFFFE##define PYXIS$M_TB6_PAGE2_VALID 0x1'#define PYXIS$M_TB6_PAGE2_ADDR 0x3FFFFE##define PYXIS$M_TB6_PAGE3_VALID 0x1'#define PYXIS$M_TB6_PAGE3_ADDR 0x3FFFFFE##define PYXIS$M_TB7_PAGE0_VALID 0x1'#define PYXIS$M_TB7_PAGE0_ADDR 0x3FFFFE##define PYXIS$M_TB7_PAGE1_VALID 0x1'#define PYXIS$M_TB7_PAGE1_ADDR 0x3FFFFE##define PYXIS$M_TB7_PAGE2_VALID 0x1'#define PYXIS$M_TB7_PAGE2_ADDR 0x3FFFFE##define PYXIS$M_TB7_PAGE3_VALID 0x1'#define PYXIS$M_TB7_PAGE3_ADDR 0x3FFFFE$#define PYXIS$M_CCR_CLOCK_DIVIDE 0x3%#define PYXIS$M_CCR_PCLK_DIVIDE 0x380!#define PYXIS$M_CCR_SEL_CFG 0x800##define PYXIS$M_CCR_DCLK_INV 0x8000&#define PYXIS$M_CCR_DCLK_FFORCE 0x10000)#define PYXIS$M_CCR_DCLK_DELAY 0xFF000000!#define PYXIS$M_FAR_HEAT 0xFFFFFF #define PYXIS$M_FCR_ON_HEAT 0xFF!#define PYXIS$M_FCR_SAMPLE 0xFF00'#define PYXIS$M_FCR_OFF_DELAY 0xFFF0000(#define PYXIS$M_FCR_FORCE_FAN 0x10000000+#define PYXIS$M_FCR_FORCE_FAN_HI 0x20000000%#define PYXIS$M_FCR_FAN_ON 0x40000000(#define PYXIS$M_FCR_FAN_ON_HI 0x80000000#define PYXIS$M_FTR_FAN_ON 0xFF!#define PYXIS$M_FTR_FAN_HI 0xFF00&#define PYXIS$M_FTR_FAN_HI_LO 0xFF0000&#define PYXIS$M_FTR_ FFAN_OFF 0xFF000000"#define PYXIS$M_PCR_POWER_DOWN 0x1!#define PYXIS$M_PCR_ABUS_DIS 0x10"#define PYXIS$M_PCR_IINT_DIS 0x100##define PYXIS$M_PCR_DO_RESET 0x1000"#define PYXIS$M_PTR_PLL_DELAY 0xFF$#define PYXIS$M_PTR_OFF_DELAY 0xFF00.#define PYXIS$M_PTR_RESET_PULSE_WIDTH 0xFF0000+#define PYXIS$M_PTR_MIN_OFF_TIME 0xFF000000'#define PYXIS$M_INT_REQ_31_0 0xFFFFFFFF0#define PYXIS$M_INT_REQ_61_32 0x3FFFFFFF000000003#define PYXIS$M_INT_REQ_CLK_PEND 0x40000000000000002#define PYXIS$M_INT_REQ_ERFR_INT 0x8000000000000000(#define PYXIS$M_INT_MASK_31_0 0xFFFFFFFF1#define PYXIS$M_INT_MASK_61_32 0x3FFFFFFF00000000"#define PYXIS$M_INT_HILO_BYTE 0xFF#define PYXIS$M_INT_RTE 0x7F!#define PYXIS$M_ICNFG_CLK_DIV 0xF"#define PYXIS$M_ICNFG_IRQ_CNT 0x70$#define PYXIS$M_ICNFG_IRQ_CFG 0x7F00'#define PYXIS$M_ICNFG_DRIVE_IRQ 0x10000!#define PYXIS$M_IIC_READ_DATA 0x1 #define PYXIS$M_IIC_READ_CLK 0x2#define PYXIS$M_IIC_DATA_EN 0x4#define PYXIS$M_IIC_DATA 0x8#define PYXIS$M_IIC_CLK_EN 0x10F#define PYXIS$M_IIC_CLK 0x20#define PYXIS$M_SEC_01 0xF#define PYXIS$M_SEC_1 0xF0#define PYXIS$M_SECOND 0xF#define PYXIS$M_SEC_10 0x70#define PYXIS$M_MINUTE 0xF#define PYXIS$M_MIN_10 0x70#define PYXIS$M_ALARM_MIN 0xF!#define PYXIS$M_ALARM_MIN_10 0x70"#define PYXIS$M_SET_MIN_ALARM 0x80#define PYXIS$M_HOUR 0xF#define PYXIS$M_HOUR_10 0x10#define PYXIS$M_AP_10HR 0x20#define PYXIS$M_TWELVE 0x40#define PYXIS$M_ALARM_HOUR 0xF"#define PYXIS$M_ALARM_HOUR_10 0x10"#define PYXIS$M_FALARM_AP_10HR 0x20!#define PYXIS$M_ALARM_TWELVE 0x40##define PYXIS$M_SET_HOUR_ALARM 0x80#define PYXIS$M_DAY 0x7#define PYXIS$M_DAY_ALARM 0x7"#define PYXIS$M_DAY_ALARM_MBZ 0x78"#define PYXIS$M_SET_DAY_ALARM 0x80#define PYXIS$M_DATE 0xF#define PYXIS$M_DATE_10 0x30#define PYXIS$M_MONTH 0xF#define PYXIS$M_MONTH_10 0x10#define PYXIS$M_MONTH_MBZ 0x20#define PYXIS$M_ESQW 0x40#define PYXIS$M_EOSC 0x80#define PYXIS$M_YEAR 0xF#define PYXIS$M_YEAR_10 0xF0#define PYXIS$M_TDF 0xF1#define PYXIS$M_WAF 0x2#define PYXIS$M_TDM 0x4#define PYXIS$M_WAM 0x8#define PYXIS$M_PU_LVL 0x10#define PYXIS$M_IBH_LO 0x20#define PYXIS$M_IPSW 0x40#define PYXIS$M_TE 0x80#define PYXIS$M_WDOG_01_SEC 0xF#define PYXIS$M_WDOG_1_SEC 0xF0#define PYXIS$M_WDOG_SEC 0xF#define PYXIS$M_WDOG_10SEC 0xF0 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_aliFgnment#endiftypedef struct _pyxis {N/* PYXIS ASIC revision 8740000080 */#pragma __nomember_alignment' unsigned char pyxis$b_fill00 [128]; __union {" int pyxis$l_pci_pyxis_rev; __struct {N char pyxis$b_pyxis_rev; /* PYXIS revision */) unsigned pyxis$v_fill01 : 24; } pyxis$r_rev_bits;% } pyxis$r_pci_pyxis_revision;& unsigned char pyxis$b_fill02 [60];N F/* PCI master latency timeout 87400000C0 */ __union { int pyxis$l_pci_lat; __struct { char pyxis$b_fill10;N char pyxis$b_pci_latency; /* PYXIS revision */) unsigned pyxis$v_fill11 : 16;# } pyxis$r_latency_bits; } pyxis$r_pci_latency;& unsigned char pyxis$b_fill20 [60];H/* PYXIS Control register 8740000100 */ __union {F int pyxis$l_pyxis_ctl; __struct {\ unsigned pyxis$v_pyxis_ctrl_pci_en : 1; /*PYXIS disable/enable resets to PCI */Y unsigned pyxis$v_pyxis_ctrl_pci_lock_en : 1; /*PYXIS locks from PCI enable */T unsigned pyxis$v_pyxis_ctrl_pci_loop_en : 1; /*PYXIS loopback enable */[ unsigned pyxis$v_pyxis_ctrl_fst_bb_en : 1; /*PYXIS fast back-to-back enable */V unsigned pyxis$v_pyxis_ctrl_mst_en : 1; /*PYXIS is a PCI master enable */FU unsigned pyxis$v_pyxis_ctrl_mem_en : 1; /*PYXIS is a PCI target enable */a unsigned pyxis$v_pyxis_ctrl_req64_en : 1; /*PYXIS will request 64bit PCI txactions */a unsigned pyxis$v_pyxis_ctrl_ack64_en : 1; /*PYXIS will accept 64bit PCI txactions */c unsigned pyxis$v_pyxis_ctrl_addr_pe_en : 1; /*PYXIS will check address parity enable */Z unsigned pyxis$v_pyxis_ctrl_perr_en : 1; /*PYXIS will check PCI data enable */_ unsigned pFyxis$v_pyxis_ctrl_fill_err_en : 1; /*PYXIS will assert fill_err enable */( unsigned pyxis$v_fill20 : 1;Y unsigned pyxis$v_pyxis_ctrl_ecc_chk_en : 1; /*PYXIS checks IOD data enable */\ unsigned pyxis$v_pyxis_ctrl_cack_en_pe : 1; /*PYXIS checks c/a parity on CACK */] unsigned pyxis$v_pyxis_ctrl_con_idle_bc : 1; /*PYXIS generated contig. IDLE_BC */[ unsigned pyxis$v_pyxis_ctrl_csr_ioa_byp : 1; /*PYXIS bypasses I/O addr queue */a Funsigned pyxis$v_pyxis_ctrl_io_flush_req : 1; /*Controls response to PCI FLUSH_REQ */b unsigned pyxis$v_pyxis_ctrl_cpu_flush_req : 1; /*Controls response to PCI FLUSH_REQ */] unsigned pyxis$v_pyxis_ctrl_arb_ev5_en : 1; /*Enable bypass path ev5 to mem/io */8 unsigned pyxis$v_pyxis_ctrl_en_arb_link : 1;V unsigned pyxis$v_pyxis_ctrl_rd_typ : 2; /*Control prefetch algorithm RD */( unsigned pyxis$v_fill21 : 2;V unsigned pyxis$v_pyxis F_ctrl_rl_typ : 2; /*Control prefetch algorithm RL */( unsigned pyxis$v_fill22 : 2;V unsigned pyxis$v_pyxis_ctrl_rm_typ : 2; /*Control prefetch algorithm RM */( unsigned pyxis$v_fill23 : 2;) } pyxis$r_pyxis_control_bits; } pyxis$r_pyxis_ctrl;& unsigned char pyxis$b_fill30 [60];G/* PYXIS CTRL1 register 8740000140 */ __union { int pyxis$l_pyxis_ctl1; __struct {P unsign Fed pyxis$v_pyxis_ctrl1_ioa_ben : 1; /*PYXIS disable/enable */( unsigned pyxis$v_fillaa : 3;c unsigned pyxis$v_pyxis_ctrl1_pci_mwin_ena : 1; /*PYXIS disable/enable Monster window */( unsigned pyxis$v_fillab : 3;T unsigned pyxis$v_pyxis_ctrl1_pci_link_ena : 1; /*PYXIS disable/enable */( unsigned pyxis$v_fillac : 3;N unsigned pyxis$v_pyxis_ctrl1_lw_par_mode : 1; /*PYXIS */) unsigned pyxis$v_fill_0_ : 3;* F } pyxis$r_pyxis_control1_bits; } pyxis$r_pyxis_ctrl1;( unsigned char pyxis$b_fill30i [188];N/* PYXIS Config => Size information of the two busses 8740000200 */ __union {! int pyxis$l_pyxis_config; __struct {! char pyxis$b_fill30a;T unsigned pyxis$v_pyxis_cnfg_pci_width : 1; /* Bit is set -> 64bit PCI */( unsigned pyxis$v_fill31 : 7;T unsigned pyxis$v_pyxis_cnfg_iod_width : 1; /* Bit is set -> 64 Fbit IOD */) unsigned pyxis$v_fill32 : 15;( } pyxis$r_pyxis_config_bits;' } pyxis$r_pyxis_config_overlay;' unsigned char pyxis$b_fill40 [508];N/* HAE MEM => Extends sparse space addr to full 32 bits 8740000400 */ __union { int pyxis$l_hae_mem; __struct {) unsigned pyxis$v_fill40a : 2;N unsigned pyxis$v_hae_mem_reg_3 : 6; /* High order sparse bits */( unsigned pyxis$v_fill41 : 3;N F unsigned pyxis$v_hae_mem_reg_2 : 5; /* High order sparse bits */) unsigned pyxis$v_fill42 : 13;N unsigned pyxis$v_hae_mem_reg_1 : 3; /* High order sparse bits */# } pyxis$r_hae_mem_bits;" } pyxis$r_hae_mem_overlay;& unsigned char pyxis$b_fill50 [60];N/* HAE IO => Extends sparse space addr to full 32 bits 8740000440 */ __union { int pyxis$l_hae_io; __struct {) unsigned pyxis$v_fill51 : 25;N F unsigned pyxis$v_hae_io : 7; /* High order sparse bits */" } pyxis$r_hae_io_bits;! } pyxis$r_hae_io_overlay;& unsigned char pyxis$b_fill60 [60];N/* CFG => Low two address bits during access to PCI COnfig space 8740000480 */ __union { int pyxis$l_cfg; __struct {S unsigned pyxis$v_cfg_bits : 2; /* Low order bits of config space ref */) unsigned pyxis$v_fill61 : 29;) unsigned pyxis$v_fill_1_ : 1;' F } pyxis$r_cgf_bits_overlay; } pyxis$r_cfg_overlay;( unsigned char pyxis$b_fill70 [7036];N/* PYXIS_DIAG Diagnostic control enable 840002000 */ __union { int pyxis$l_pyxis_diag; __struct {N unsigned pyxis$v_from_en : 1; /* FROM write enable */U unsigned pyxis$v_use_check : 1; /* USed with DIA_CHECK for ECC testing */) unsigned pyxis$v_fill81 : 26;N unsigned pyxis$v F_fpe_pci : 2; /* Force bad parity on PCI */( unsigned pyxis$v_fill82 : 1;N unsigned pyxis$v_fpe_to_ev5 : 1; /* Force parity error */& } pyxis$r_pyxis_diag_bits;% } pyxis$r_pyxis_diag_overlay;( unsigned char pyxis$b_fill90 [4092];N/* DIAG_CHECK Diagnostic used to write a known ECC pattern 840003000 */ __union { int pyxis$l_diag_check; __struct {N char pyxis$b_diag_check_ecc; /* ECC to be used F */) unsigned pyxis$v_fill91 : 24;& } pyxis$r_diag_check_bits;% } pyxis$r_diag_check_overlay;) unsigned char pyxis$b_fill100 [4092];N/* Perf Monitor counts 8740004000 */ __union {! int pyxis$l_perf_monitor;' } pyxis$r_perf_monitor_overlay;' unsigned char pyxis$b_fill110 [60];N/* Perf Monitor control 8740004040 */ __union {! F int pyxis$l_perf_control;' } pyxis$r_perf_control_overlay;) unsigned char pyxis$b_fill120 [8124];N/* PYXIS Error register 8740008200 */) unsigned char pyxis$b_fill120a [512]; __union { int pyxis$l_pyxis_err; __struct {N unsigned pyxis$v_err_corr_ecc : 1; /* [0] */N unsigned pyxis$v_err_unc_ecc : 1; /* [1] */N unsigned pyxis$v_err_cFpu_pe : 1; /* [2] */N unsigned pyxis$v_err_mem_nem : 1; /* [3] */N unsigned pyxis$v_err_pci_serr : 1; /* [4] */N unsigned pyxis$v_err_pci_perr : 1; /* [5] */N unsigned pyxis$v_err_pci_adr_pe : 1; /* [6] */N unsigned pyxis$v_err_m_abort : 1; /* [7] */N unsigned pyxis$v_err_t_abort : 1; /* [8] F */N unsigned pyxis$v_err_pa_pte_inv : 1; /* [9] */N unsigned pyxis$v_err_fill : 1; /* [10] */N unsigned pyxis$v_err_ioa_timeout : 1; /* [11] */N unsigned pyxis$v_err_ioa_reserved_0 : 4; /* [15:12] */3 unsigned pyxis$v_err_lost_corr_ecc : 1;2 unsigned pyxis$v_err_lost_unc_ecc : 1;1 unsigned pyxis$v_err_lost_cpu_pe : 1;2 F unsigned pyxis$v_err_lost_mem_nem : 1;3 unsigned pyxis$v_err_lost_pci_fill : 1;3 unsigned pyxis$v_err_lost_pci_perr : 1;5 unsigned pyxis$v_err_lost_pci_adr_pe : 1;2 unsigned pyxis$v_err_lost_m_abort : 1;2 unsigned pyxis$v_err_lost_t_abort : 1;5 unsigned pyxis$v_err_lost_pa_pte_inv : 1;< unsigned pyxis$v_err_lost_from_wrt_err_fill : 1;6 unsigned pyxis$v_err_lost_ioa_timeout : 1;N unsigned F pyxis$v_err_lost_reserved_1 : 3; /* */+ unsigned pyxis$v_err_valid : 1;% } pyxis$r_pyxis_err_bits;$ } pyxis$r_pyxis_err_overlay;' unsigned char pyxis$b_fill150 [60];N/* */N/* PYXIS Error status register - 0x8740008240 */N/* */ __union { int pyxis$l_pyxiFs_stat; __struct {N unsigned pyxis$v_stat_pci_0 : 1; /* [0] */N unsigned pyxis$v_stat_pci_1 : 1; /* [1] */N unsigned pyxis$v_stat_fill : 2; /* [3:2] */N unsigned pyxis$v_stat_ioa_valid : 4; /* [7:4] */N unsigned pyxis$v_stat_fill2 : 3; /* [10:8] */N unsigned pyxis$v_stat_tlb_miss : 1; /* [11] F */N unsigned pyxis$v_stat_reserved_0 : 20; /* [31:12] */& } pyxis$r_pyxis_stat_bits;% } pyxis$r_pyxis_stat_overlay;' unsigned char pyxis$b_fill160 [60];N/* */N/* */N/* PYXIS Error mask register - 0x8740008280 */N/* F */ __union {% int pyxis$l_pyxis_error_mask; __struct {N unsigned pyxis$v_mask_corr_ecc_err : 1; /* [0] */N unsigned pyxis$v_mask_unc_ecc_err : 1; /* [1] */N unsigned pyxis$v_mask_cpu_pe : 1; /* [2] */N unsigned pyxis$v_mask_mem_nem : 1; /* [3] */N unsigned pyxis$v_mask_pci_serr : 1; /* [4] */N F unsigned pyxis$v_mask_pci_perr : 1; /* [5] */N unsigned pyxis$v_mask_pci_adr_pe : 1; /* [6] */N unsigned pyxis$v_mask_m_abort : 1; /* [7] */N unsigned pyxis$v_mask_t_abort : 1; /* [8] */N unsigned pyxis$v_mask_pa_pte_inv : 1; /* [9] */N unsigned pyxis$v_mask_fill : 1; /* [10] */N unsigned pyxis$v_mas Fk_ioa_timeout : 1; /* [11] */N unsigned pyxis$v_mask_reserved_1 : 20; /* [30:12] */, } pyxis$r_pyxis_error_mask_bits;+ } pyxis$r_pyxis_error_mask_overlay;( unsigned char pyxis$b_fill170 [124];N/* */N/* PYXIS Error Syndrome register - 0x8740008300 */N/* */ F__union { int pyxis$l_pyxis_synd; __struct {1 unsigned pyxis$v_pyxis_syndrome0 : 8;1 unsigned pyxis$v_pyxis_syndrome1 : 8;6 unsigned pyxis$v_pyxis_raw_check_bits : 8;N unsigned pyxis$v_pyxis_synd_ce0 : 1; /* [24] */N unsigned pyxis$v_pyxis_synd_ce1 : 1; /* [25] */N unsigned pyxis$v_pyxis_synd_uce0 : 1; /* [26] */N unsigned pyxis$v_pyxis_syn Fd_uce1 : 1; /* [27] */& unsigned pyxis$v_fill : 4;& } pyxis$r_pyxis_synd_bits;! } pyxis$r_pyxis_syndrome;& unsigned char pyxis$b_fill171 [4];N/* */N/* PYXIS Error data register - 0x8740008308 */N/* */ __union {& __int64 pyxis$q_pyxis_errdata;' } py Fxis$r_pyxis_errdat_overlay;( unsigned char pyxis$b_fill180 [240];N/* */N/* PYXIS Memory Error Address register 0 - 0x8740008400 */N/* */ __union { int pyxis$l_pyxis_mear; __struct {* unsigned pyxis$v_unused_0 : 4;. unsigned pyxis$v_mear_addr_h : 28;& } pyxis$r_pyxis_me Far_bits;% } pyxis$r_pyxis_mear_overlay;' unsigned char pyxis$b_fill190 [60];N/* */N/* PYXIS Memory Error status register 1 - 0x8740008440 */N/* */ __union { int pyxis$l_pyxis_mesr; __struct {N unsigned pyxis$v_mesr_addr_3932 : 8; /* [7:0] */N unsigned pFyxis$v_mesr_dma_rd_nxm : 1; /* [8] */N unsigned pyxis$v_mesr_dma_wr_nxm : 1; /* [9] */N unsigned pyxis$v_mesr_cpu_rd_nxm : 1; /* [10] */N unsigned pyxis$v_mesr_cpu_wr_nxm : 1; /* [11] */N unsigned pyxis$v_mesr_io_rd_nxm : 1; /* [12] */N unsigned pyxis$v_mesr_io_wr_nxm : 1; /* [13] */N unsigned pyxis$v_mesr_victim_nxm : 1F; /* [14] */N unsigned pyxis$v_mesr_tlbfill_nxm : 1; /* [15] */N unsigned pyxis$v_mesr_oword_index : 2; /* [17:16] */N unsigned pyxis$v_mesr_reserved_2 : 2; /* [19:18] */N unsigned pyxis$v_mesr_data_cycle_typ : 5; /* [24:20] */N unsigned pyxis$v_mesr_seq_st : 7; /* [31:25] */& } pyxis$r_pyxis_mesr_bits;% } pyxis$r_pyxis_mesr_overl Fay;( unsigned char pyxis$b_fill200 [956];N/* */N/* PCI Error register 0 - 0x8740008800 */N/* */ __union { int pyxis$l_pyxis_pcie0; __struct {N unsigned pyxis$v_pcie_dma_cmd : 4; /* [3:0] */N unsigned pyxis$v_pcie_reserved0 : 1; /* [4] F */N unsigned pyxis$v_pcie_dma_dac : 1; /* [5] */N unsigned pyxis$v_pcie_reserved : 2; /* [7:6] */N unsigned pyxis$v_pcie_window : 4; /* [11:8] */N unsigned pyxis$v_pcie_reserved_2 : 4; /* [15:12] */N unsigned pyxis$v_pcie_mstr_state : 4; /* [19:16] */N unsigned pyxis$v_pcie_trgt_state : 4; /* [23:20] */N Funsigned pyxis$v_pcie_pci_cmd : 4; /* [27:24] */N unsigned pyxis$v_pcie_pci_dac : 1; /* [28] */N unsigned pyxis$v_pcie_unused_2 : 3; /* [31:29] */& } pyxis$r_pyxis_pcie_bits;& } pyxis$r_pyxis_pcie0_overlay;' unsigned char pyxis$b_fill210 [60];N/* */N/* PYXIS PCI error register 1 - 0x8740008840 F*/N/* */ __union {% int pyxis$l_pcie1_dma_addr_h;& } pyxis$r_pyxis_pcie1_overlay;' unsigned char pyxis$b_fill220 [60];N/* */N/* PYXIS PCI error register 2 - 0x8740008880 */N/* */ __union {% int pyxis$l_pcie2_pc Fi_addr_h;& } pyxis$r_pyxis_pcie2_overlay;) unsigned char pyxis$b_fill221 [6012];N/* */N/* Memory Configuration Register - 0x8750000000 */N/* */ __union { int pyxis$l_mem_mcr; __struct {N unsigned pyxis$v_mcr_mode_req : 1; /* 0 */N unsigned pFyxis$v_mcr_reserved : 7; /* */N unsigned pyxis$v_mcr_server_mode : 1; /* 8 */N unsigned pyxis$v_mcr_bcache_stat : 1; /* 9 */N unsigned pyxis$v_mcr_bcache_en : 1; /* 10 */N unsigned pyxis$v_mcr_pipelined_cache : 1; /* 11 */N unsigned pyxis$v_mcr_overlap_dis : 1; /* 12 */N unsigned pyxis$v_mcr_seq_trace : 1; F/* 13 */N unsigned pyxis$v_mcr_cke_auto : 1; /* 14 */N unsigned pyxis$v_mcr_dram_clk_auto : 1; /* 15 */N unsigned pyxis$v_mcr_dram_mode : 14; /* 29:16 */N unsigned pyxis$v_mcr_reserved_2 : 2; /* 31:30 */# } pyxis$r_mem_mcr_bits;" } pyxis$r_mem_mcr_overlay;' unsigned char pyxis$b_fill230 [60];N/* F */N/* Memory Clock Mask Register - 0x8750000040 */N/* */ __union { int pyxis$l_mem_mcmr; __struct {N unsigned pyxis$v_mcmr_dram_clock_mask : 16; /* 15:0 */N unsigned pyxis$v_mcmr_reserved_1 : 16; /* 31:16 */$ } pyxis$r_mem_mcmr_data;# } pyxis$r_mem_mcmr_overlay; F( unsigned char pyxis$b_fill231 [444];N/* */N/* Memory Global Timing Register - 0x8750000200 */N/* */ __union { int pyxis$l_mem_mgtr; __struct {N unsigned pyxis$v_mgtr_min_ras_pre : 3; /* 2:0 */N unsigned pyxis$v_mgtr_reserved_1 : 1; /* 3 F */N unsigned pyxis$v_mgtr_cas_lat : 2; /* 5:4 */N unsigned pyxis$v_mgtr_reserved_2 : 2; /* 7:6 */N unsigned pyxis$v_mgtr_idle_bc_width : 3; /* 10:8 */N unsigned pyxis$v_mgtr_reserved_3 : 21; /* 31:11 */$ } pyxis$r_mem_mgtr_data;# } pyxis$r_mem_mgtr_overlay;( unsigned char pyxis$b_fill232 [252];N/* F */N/* Memory Refresh Timing Register - 0x8750000300 */N/* */ __union { int pyxis$l_mem_mrtr; __struct {N unsigned pyxis$v_mrtr_reserved_1 : 4; /* 3:0 */N unsigned pyxis$v_mrtr_ref_width : 3; /* 6:4 */N unsigned pyxis$v_mrtr_ref_int : 6; /* 12:7 */N unsi Fgned pyxis$v_mrtr_reserved_2 : 2; /* 14:13 */N unsigned pyxis$v_mrtr_force_ref : 1; /* 15 */N unsigned pyxis$v_mrtr_reserved_3 : 16; /* 31:16 */$ } pyxis$r_mem_mrtr_data;# } pyxis$r_mem_mrtr_overlay;( unsigned char pyxis$b_fill233 [252];N/* */N/* Memory Row History Policy Register - 0x8750000400 */N/* F */ __union { int pyxis$l_mem_mrphr; __struct {N unsigned pyxis$v_mrphr_policy_mask : 16; /* 15:0 */N unsigned pyxis$v_mrphr_reserved_3 : 16; /* 31:16 */% } pyxis$r_mem_mrphr_data;$ } pyxis$r_mem_mrphr_overlay;( unsigned char pyxis$b_fill234 [252];N/* */N F/* Memory Debug Register 1 - 0x8750000500 */N/* */ __union { int pyxis$l_mem_mdr1; __struct {N unsigned pyxis$v_mdr1_sel0 : 6; /* 5:0 */N unsigned pyxis$v_mdr1_reserved_1 : 2; /* 7:6 */N unsigned pyxis$v_mdr1_sel1 : 6; /* 13:8 */N unsigned pyxis$v_mdr1_reFserved_2 : 2; /* 15:14 */N unsigned pyxis$v_mdr1_sel2 : 6; /* 21:16 */N unsigned pyxis$v_mdr1_reserved_3 : 2; /* 23:22 */N unsigned pyxis$v_mdr1_sel3 : 6; /* 29:24 */N unsigned pyxis$v_mdr1_reserved_4 : 1; /* 30 */N unsigned pyxis$v_mdr1_enable : 1; /* 31 */$ } pyxis$r_mem_mdr1_data;# } pyxis$r_mem_md Fr1_overlay;' unsigned char pyxis$b_fill235 [60];N/* */N/* Memory Debug Register 2 - 0x8750000540 */N/* */ __union { int pyxis$l_mem_mdr2; __struct {N unsigned pyxis$v_mdr2_sel0 : 6; /* 5:0 */N unsigned pyxis$v_mdr2_reserved_1 : 2; /* 7:6 F */N unsigned pyxis$v_mdr2_sel1 : 6; /* 13:8 */N unsigned pyxis$v_mdr2_reserved_2 : 2; /* 15:14 */N unsigned pyxis$v_mdr2_sel2 : 6; /* 21:16 */N unsigned pyxis$v_mdr2_reserved_3 : 2; /* 23:22 */N unsigned pyxis$v_mdr2_sel3 : 6; /* 29:24 */N unsigned pyxis$v_mdr2_reserved_4 : 1; /* 30 */N F unsigned pyxis$v_mdr2_enable : 1; /* 31 */$ } pyxis$r_mem_mdr2_data;# } pyxis$r_mem_mdr2_overlay;( unsigned char pyxis$b_fill236 [188];N/* */N/* Memory Base Address Register 0 - 0x8750000600 */N/* */ __union { int pyxis$l_mem_bbar0; __struct {N F unsigned pyxis$v_bbar0_reserved_1 : 6; /* 5:0 */N unsigned pyxis$v_bbar0_base_addr_3324 : 10; /* 15:6 */N unsigned pyxis$v_bbar0_reserved_2 : 16; /* 31:16 */% } pyxis$r_mem_bbar0_data;$ } pyxis$r_mem_bbar0_overlay;( unsigned char pyxis$b_fill237a [60];N/* */N/* Memory Base Address Register 1 - 0x8750000640 F */N/* */ __union { int pyxis$l_mem_bbar1; __struct {N unsigned pyxis$v_bbar1_reserved_1 : 6; /* 5:0 */N unsigned pyxis$v_bbar1_base_addr_3324 : 10; /* 15:6 */N unsigned pyxis$v_bbar1_reserved_2 : 16; /* 31:16 */% } pyxis$r_mem_bbar1_data;$ } pyxis$r_mem_bbar1_overlay;( unsigned char pyxis$b_fi Fll237b [60];N/* */N/* Memory Base Address Register 2 - 0x8750000680 */N/* */ __union { int pyxis$l_mem_bbar2; __struct {N unsigned pyxis$v_bbar2_reserved_1 : 6; /* 5:0 */N unsigned pyxis$v_bbar2_base_addr_3324 : 10; /* 15:6 */N unsigned p Fyxis$v_bbar2_reserved_2 : 16; /* 31:16 */% } pyxis$r_mem_bbar2_data;$ } pyxis$r_mem_bbar2_overlay;( unsigned char pyxis$b_fill237c [60];N/* */N/* Memory Base Address Register 3 - 0x87500006c0 */N/* */ __union { int pyxis$l_mem_bbar3; __struct {N unsign Fed pyxis$v_bbar3_reserved_1 : 6; /* 5:0 */N unsigned pyxis$v_bbar3_base_addr_3324 : 10; /* 15:6 */N unsigned pyxis$v_bbar3_reserved_2 : 16; /* 31:16 */% } pyxis$r_mem_bbar3_data;$ } pyxis$r_mem_bbar3_overlay;( unsigned char pyxis$b_fill237d [60];N/* */N/* Memory Base Address Register 4 - 0x8750000700 */N/* F */ __union { int pyxis$l_mem_bbar4; __struct {N unsigned pyxis$v_bbar4_reserved_1 : 6; /* 5:0 */N unsigned pyxis$v_bbar4_base_addr_3324 : 10; /* 15:6 */N unsigned pyxis$v_bbar4_reserved_2 : 16; /* 31:16 */% } pyxis$r_mem_bbar4_data;$ } pyxis$r_mem_bbar4_overlay;( unsigned char pyxis$b_fill237e [60];N F/* */N/* Memory Base Address Register 5 - 0x8750000740 */N/* */ __union { int pyxis$l_mem_bbar5; __struct {N unsigned pyxis$v_bbar5_reserved_1 : 6; /* 5:0 */N unsigned pyxis$v_bbar5_base_addr_3324 : 10; /* 15:6 */N unsigned pyxis$v_bbar5_r Feserved_2 : 16; /* 31:16 */% } pyxis$r_mem_bbar5_data;$ } pyxis$r_mem_bbar5_overlay;( unsigned char pyxis$b_fill237f [60];N/* */N/* Memory Base Address Register 6 - 0x8750000780 */N/* */ __union { int pyxis$l_mem_bbar6; __struct {N unsigned pyxis$v_bba Fr6_reserved_1 : 6; /* 5:0 */N unsigned pyxis$v_bbar6_base_addr_3324 : 10; /* 15:6 */N unsigned pyxis$v_bbar6_reserved_2 : 16; /* 31:16 */% } pyxis$r_mem_bbar6_data;$ } pyxis$r_mem_bbar6_overlay;( unsigned char pyxis$b_fill237g [60];N/* */N/* Memory Base Address Register 7 - 0x87500007c0 */N/* F */ __union { int pyxis$l_mem_bbar7; __struct {N unsigned pyxis$v_bbar7_reserved_1 : 6; /* 5:0 */N unsigned pyxis$v_bbar7_base_addr_3324 : 10; /* 15:6 */N unsigned pyxis$v_bbar7_reserved_2 : 16; /* 31:16 */% } pyxis$r_mem_bbar7_data;$ } pyxis$r_mem_bbar7_overlay;( unsigned char pyxis$b_fill237h [60];N/* F */N/* Start of Bank Config */N/* */N/* Memory Bank Configuration Register 0 - 0x8750000800 */N/* */ __union { int pyxis$l_mem_mbcr0; __struct {N unsigned pyxis$v_mbcr0_bank_enable : 1F; /* 0 */N unsigned pyxis$v_mbcr0_bank_size : 4; /* 4:1 */N unsigned pyxis$v_mbcr0_subbank_enable : 1; /* 5 */N unsigned pyxis$v_mbcr0_colsel : 1; /* 6 */N unsigned pyxis$v_mbcr0_4bank : 1; /* 7 */N unsigned pyxis$v_mbcr0_reserved_2 : 24; /* 31:8 */% } pyxis$r_mem_mbcr0_data;$ } pyxis$r_mem_mbcr0_overlay; F( unsigned char pyxis$b_fill238a [60];N/* */N/* Memory Bank Configuration Register 1 - 0x8750000840 */N/* */ __union { int pyxis$l_mem_mbcr1; __struct {N unsigned pyxis$v_mbcr1_bank_enable : 1; /* 0 */N unsigned pyxis$v_mbcr1_bank_size : 4; /* 4:1 F */N unsigned pyxis$v_mbcr1_subbank_enable : 1; /* 5 */N unsigned pyxis$v_mbcr1_colsel : 1; /* 6 */N unsigned pyxis$v_mbcr1_4bank : 1; /* 7 */N unsigned pyxis$v_mbcr1_reserved_2 : 24; /* 31:8 */% } pyxis$r_mem_mbcr1_data;$ } pyxis$r_mem_mbcr1_overlay;( unsigned char pyxis$b_fill238b [60];N/* F */N/* Memory Bank Configuration Register 2 - 0x8750000880 */N/* */ __union { int pyxis$l_mem_mbcr2; __struct {N unsigned pyxis$v_mbcr2_bank_enable : 1; /* 0 */N unsigned pyxis$v_mbcr2_bank_size : 4; /* 4:1 */N unsigned pyxis$v_mbcr2_subbank_enable : 1; /* 5 */N un Fsigned pyxis$v_mbcr2_colsel : 1; /* 6 */N unsigned pyxis$v_mbcr2_4bank : 1; /* 7 */N unsigned pyxis$v_mbcr2_reserved_2 : 24; /* 31:8 */% } pyxis$r_mem_mbcr2_data;$ } pyxis$r_mem_mbcr2_overlay;( unsigned char pyxis$b_fill238c [60];N/* */N/* Memory Bank Configuration Register 3 - 0x87500008c0 */N F/* */ __union { int pyxis$l_mem_mbcr3; __struct {N unsigned pyxis$v_mbcr3_bank_enable : 1; /* 0 */N unsigned pyxis$v_mbcr3_bank_size : 4; /* 4:1 */N unsigned pyxis$v_mbcr3_subbank_enable : 1; /* 5 */N unsigned pyxis$v_mbcr3_colsel : 1; /* 6 */N unsigned pyxis$v_mbcr3_4 Fbank : 1; /* 7 */N unsigned pyxis$v_mbcr3_reserved_2 : 24; /* 31:8 */% } pyxis$r_mem_mbcr3_data;$ } pyxis$r_mem_mbcr3_overlay;( unsigned char pyxis$b_fill238d [60];N/* */N/* Memory Bank Configuration Register 4 - 0x8750000900 */N/* */ __union { F int pyxis$l_mem_mbcr4; __struct {N unsigned pyxis$v_mbcr4_bank_enable : 1; /* 0 */N unsigned pyxis$v_mbcr4_bank_size : 4; /* 4:1 */N unsigned pyxis$v_mbcr4_subbank_enable : 1; /* 5 */N unsigned pyxis$v_mbcr4_colsel : 1; /* 6 */N unsigned pyxis$v_mbcr4_4bank : 1; /* 7 */N unsigned pyxis$v_mbcr4_reserved_2 : 24; /* 31: F8 */% } pyxis$r_mem_mbcr4_data;$ } pyxis$r_mem_mbcr4_overlay;( unsigned char pyxis$b_fill238e [60];N/* */N/* Memory Bank Configuration Register 5 - 0x8750000940 */N/* */ __union { int pyxis$l_mem_mbcr5; __struct {N unsigned pyxis$v_mbcr5_bank_enable : 1; /* F 0 */N unsigned pyxis$v_mbcr5_bank_size : 4; /* 4:1 */N unsigned pyxis$v_mbcr5_subbank_enable : 1; /* 5 */N unsigned pyxis$v_mbcr5_colsel : 1; /* 6 */N unsigned pyxis$v_mbcr5_4bank : 1; /* 7 */N unsigned pyxis$v_mbcr5_reserved_2 : 24; /* 31:8 */% } pyxis$r_mem_mbcr5_data;$ } pyxis$r_mem_mbcr5_overlay;( F unsigned char pyxis$b_fill238f [60];N/* */N/* Memory Bank Configuration Register 6 - 0x8750000980 */N/* */ __union { int pyxis$l_mem_mbcr6; __struct {N unsigned pyxis$v_mbcr6_bank_enable : 1; /* 0 */N unsigned pyxis$v_mbcr6_bank_size : 4; /* 4:1 F*/N unsigned pyxis$v_mbcr6_subbank_enable : 1; /* 5 */N unsigned pyxis$v_mbcr6_colsel : 1; /* 6 */N unsigned pyxis$v_mbcr6_4bank : 1; /* 7 */N unsigned pyxis$v_mbcr6_reserved_2 : 24; /* 31:8 */% } pyxis$r_mem_mbcr6_data;$ } pyxis$r_mem_mbcr6_overlay;( unsigned char pyxis$b_fill238g [60];N/* F */N/* Memory Bank Configuration Register 7 - 0x87500009c0 */N/* */ __union { int pyxis$l_mem_mbcr7; __struct {N unsigned pyxis$v_mbcr7_bank_enable : 1; /* 0 */N unsigned pyxis$v_mbcr7_bank_size : 4; /* 4:1 */N unsigned pyxis$v_mbcr7_subbank_enable : 1; /* 5 */N unsign Fed pyxis$v_mbcr7_colsel : 1; /* 6 */N unsigned pyxis$v_mbcr7_4bank : 1; /* 7 */N unsigned pyxis$v_mbcr7_reserved_2 : 24; /* 31:8 */% } pyxis$r_mem_mbcr7_data;$ } pyxis$r_mem_mbcr7_overlay;( unsigned char pyxis$b_fill238h [60];N/* */N/* Start of Bank TIming Registers */N/* M Femory Bank TIming Register 0 - 0x8750000A00 */N/* */ __union { int pyxis$l_mem_mbtr0; __struct {N unsigned pyxis$v_mbtr0_row_addr_hold : 3; /* 2:0 */N unsigned pyxis$v_mbtr0_reserved_1 : 1; /* 3 */N unsigned pyxis$v_mbtr0_toshiba : 1; /* 4 */N unsigned pyxis$v_mbtr0_slow_ Fcharge : 1; /* 5 */N unsigned pyxis$v_mbtr0_reserved_2 : 26; /* 31:6 */% } pyxis$r_mem_mbtr0_data;$ } pyxis$r_mem_mbtr0_overlay;( unsigned char pyxis$b_fill239a [60];N/* */N/* Memory Bank TIming Register 1 - 0x8750000A40 */N/* */ __union { in Ft pyxis$l_mem_mbtr1; __struct {N unsigned pyxis$v_mbtr1_row_addr_hold : 3; /* 2:0 */N unsigned pyxis$v_mbtr1_reserved_1 : 1; /* 3 */N unsigned pyxis$v_mbtr1_toshiba : 1; /* 4 */N unsigned pyxis$v_mbtr1_slow_charge : 1; /* 5 */N unsigned pyxis$v_mbtr1_reserved_2 : 26; /* 31:6 */% } pyxis$r_mem_mbtr1_data;$ } pyxis$r_mem_ Fmbtr1_overlay;( unsigned char pyxis$b_fill239b [60];N/* */N/* Memory Bank TIming Register 2 - 0x8750000A80 */N/* */ __union { int pyxis$l_mem_mbtr2; __struct {N unsigned pyxis$v_mbtr2_row_addr_hold : 3; /* 2:0 */N unsigned pyxis$v_mbtr2_reserved_1 : 1; /* 3 F */N unsigned pyxis$v_mbtr2_toshiba : 1; /* 4 */N unsigned pyxis$v_mbtr2_slow_charge : 1; /* 5 */N unsigned pyxis$v_mbtr2_reserved_2 : 26; /* 31:6 */% } pyxis$r_mem_mbtr2_data;$ } pyxis$r_mem_mbtr2_overlay;( unsigned char pyxis$b_fill239c [60];N/* */N/* Memory Bank TIming Register 3 - 0x8750000 FAc0 */N/* */ __union { int pyxis$l_mem_mbtr3; __struct {N unsigned pyxis$v_mbtr3_row_addr_hold : 3; /* 2:0 */N unsigned pyxis$v_mbtr3_reserved_1 : 1; /* 3 */N unsigned pyxis$v_mbtr3_toshiba : 1; /* 4 */N unsigned pyxis$v_mbtr3_slow_charge : 1; /* 5 */N F unsigned pyxis$v_mbtr3_reserved_2 : 26; /* 31:6 */% } pyxis$r_mem_mbtr3_data;$ } pyxis$r_mem_mbtr3_overlay;( unsigned char pyxis$b_fill239d [60];N/* */N/* Memory Bank TIming Register 4 - 0x8750000B00 */N/* */ __union { int pyxis$l_mem_mbtr4; __struct F{N unsigned pyxis$v_mbtr4_row_addr_hold : 3; /* 2:0 */N unsigned pyxis$v_mbtr4_reserved_1 : 1; /* 3 */N unsigned pyxis$v_mbtr4_toshiba : 1; /* 4 */N unsigned pyxis$v_mbtr4_slow_charge : 1; /* 5 */N unsigned pyxis$v_mbtr4_reserved_2 : 26; /* 31:6 */% } pyxis$r_mem_mbtr4_data;$ } pyxis$r_mem_mbtr4_overlay;( unsigned char pyxis$ Fb_fill239e [60];N/* */N/* Memory Bank TIming Register 5 - 0x8750000B40 */N/* */ __union { int pyxis$l_mem_mbtr5; __struct {N unsigned pyxis$v_mbtr5_row_addr_hold : 3; /* 2:0 */N unsigned pyxis$v_mbtr5_reserved_1 : 1; /* 3 */N unsign Fed pyxis$v_mbtr5_toshiba : 1; /* 4 */N unsigned pyxis$v_mbtr5_slow_charge : 1; /* 5 */N unsigned pyxis$v_mbtr5_reserved_2 : 26; /* 31:6 */% } pyxis$r_mem_mbtr5_data;$ } pyxis$r_mem_mbtr5_overlay;( unsigned char pyxis$b_fill239f [60];N/* */N/* Memory Bank TIming Register 6 - 0x8750000B80 */N/* F */ __union { int pyxis$l_mem_mbtr6; __struct {N unsigned pyxis$v_mbtr6_row_addr_hold : 3; /* 2:0 */N unsigned pyxis$v_mbtr6_reserved_1 : 1; /* 3 */N unsigned pyxis$v_mbtr6_toshiba : 1; /* 4 */N unsigned pyxis$v_mbtr6_slow_charge : 1; /* 5 */N unsigned pyxis$v_mbtr6_reser Fved_2 : 26; /* 31:6 */% } pyxis$r_mem_mbtr6_data;$ } pyxis$r_mem_mbtr6_overlay;( unsigned char pyxis$b_fill239g [60];N/* */N/* Memory Bank TIming Register 7 - 0x8750000BC0 */N/* */ __union { int pyxis$l_mem_mbtr7; __struct {N unsigned pyxis$v_mbtr7_r Fow_addr_hold : 3; /* 2:0 */N unsigned pyxis$v_mbtr7_reserved_1 : 1; /* 3 */N unsigned pyxis$v_mbtr7_toshiba : 1; /* 4 */N unsigned pyxis$v_mbtr7_slow_charge : 1; /* 5 */N unsigned pyxis$v_mbtr7_reserved_2 : 26; /* 31:6 */% } pyxis$r_mem_mbtr7_data;$ } pyxis$r_mem_mbtr7_overlay;( unsigned char pyxis$b_fill239h [60];N/* F */N/* Memory Cache Valid Mask - 0x8750000C00 */N/* */ __union { int pyxis$l_mem_cvm; __struct {N unsigned pyxis$v_cvm_cache_valid_mask : 31; /* 31:0 */) unsigned pyxis$v_fill_2_ : 1;# } pyxis$r_mem_cvm_data;" } pyxis$r_mem_cvm_overlay;* unsigned char pyxi Fs$b_fill239i [5116];N/* */N/* PCI Scatter/Gather TBIA - 0x8760000100 */N/* */( unsigned char pyxis$b_fill345 [256]; __union { int pyxis$l_pci_tbia; __struct {N unsigned pyxis$v_tbia_csr_wr_data : 2; /* */N unsigned pyxis$v_tbia_reserved : 29; /* F */) unsigned pyxis$v_fill_3_ : 1;$ } pyxis$r_pci_tbia_bits;# } pyxis$r_pci_tbia_overlay;( unsigned char pyxis$b_fill350 [764];N/* */N/* PCI Window Base 0 - 0x8760000400 */N/* */ __union { int pyxis$l_pci_wbase0; __struct {N F unsigned pyxis$v_wbase0_w_en : 1; /* */N unsigned pyxis$v_wbase0_sg_en : 1; /* enable scatter/gather */N unsigned pyxis$v_wbase0_memcs_en : 1; /* enable MEMCS */N unsigned pyxis$v_wbase0_dac_en : 1; /* enable 64BIT PCI */N unsigned pyxis$v_wbase0_reserved : 16; /* */. unsigned pyxis$v_wbase0_base : 12;& } pyxis$r_pci_wbase0_bits;% } pyxis$r_pci_ Fwbase0_overlay;' unsigned char pyxis$b_fill360 [60];N/* */N/* PCI Window Mask 0 - 0x8760000440 */N/* */ __union { int pyxis$l_pci_wmask0; __struct {N unsigned pyxis$v_wmask0_reserved : 20; /* */. unsigned pyxis$v_wmask0_mask : 12;& F } pyxis$r_pci_wmask0_bits;% } pyxis$r_pci_wmask0_overlay;' unsigned char pyxis$b_fill370 [60];N/* */N/* PCI Window Translated Base 0 - 0x8760000480 */N/* */ __union { int pyxis$l_pci_tbase0; __struct {N unsigned pyxis$v_tbase0_reserved : 8; /* */ F. unsigned pyxis$v_tbase0_base : 24;& } pyxis$r_pci_tbase0_bits;% } pyxis$r_pci_tbase0_overlay;( unsigned char pyxis$b_fill380 [124];N/****** */N/* */N/* PCI Window Base 1 - 0x8760000500 */N/* */ __union { F int pyxis$l_pci_wbase1; __struct {N unsigned pyxis$v_wbase1_w_en : 1; /* */N unsigned pyxis$v_wbase1_sg_en : 1; /* enable scatter/gather */N unsigned pyxis$v_wbase1_memcs_en : 1; /* enable MEMCS */N unsigned pyxis$v_wbase1_dac_en : 1; /* enable 64BIT PCI */N unsigned pyxis$v_wbase1_reserved : 16; /* */. unsigned pyxis$v_wbase1_base : 12;& F } pyxis$r_pci_wbase1_bits;% } pyxis$r_pci_wbase1_overlay;' unsigned char pyxis$b_fill390 [60];N/* */N/* PCI Window Mask 1 - 0x8760000540 */N/* */ __union { int pyxis$l_pci_wmask1; __struct {N unsigned pyxis$v_wmask1_reserved : 20; /* F */. unsigned pyxis$v_wmask1_mask : 12;& } pyxis$r_pci_wmask1_bits;% } pyxis$r_pci_wmask1_overlay;' unsigned char pyxis$b_fill400 [60];N/* */N/* PCI Window Translated Base 1 - 0x8760000580 */N/* */ __union { int pyxis$l_pci_tbase1; __struct {N unsi Fgned pyxis$v_tbase1_reserved : 8; /* */. unsigned pyxis$v_tbase1_base : 24;& } pyxis$r_pci_tbase1_bits;% } pyxis$r_pci_tbase1_overlay;( unsigned char pyxis$b_fill410 [124];N/* */N/* PCI Window Base 2 - 0x8760000600 */N/* */ __union { int pyxi Fs$l_pci_wbase2; __struct {N unsigned pyxis$v_wbase2_w_en : 1; /* */N unsigned pyxis$v_wbase2_sg_en : 1; /* enable scatter/gather */N unsigned pyxis$v_wbase2_memcs_en : 1; /* enable MEMCS */N unsigned pyxis$v_wbase2_dac_en : 1; /* enable 64BIT PCI */N unsigned pyxis$v_wbase2_reserved : 16; /* */. unsigned pyxis$v_wbase2_base : 12;& } pyxi Fs$r_pci_wbase2_bits;% } pyxis$r_pci_wbase2_overlay;' unsigned char pyxis$b_fill420 [60];N/* */N/* PCI Window Mask 2 - 0x8760000640 */N/* */ __union { int pyxis$l_pci_wmask2; __struct {N unsigned pyxis$v_wmask2_reserved : 20; /* */. F unsigned pyxis$v_wmask2_mask : 12;& } pyxis$r_pci_wmask2_bits;% } pyxis$r_pci_wmask2_overlay;' unsigned char pyxis$b_fill430 [60];N/* */N/* PCI Window Translated Base 2 - 0x8760000680 */N/* */ __union { int pyxis$l_pci_tbase2; __struct {N unsigned pyxis$v_tbase F2_reserved : 8; /* */. unsigned pyxis$v_tbase2_base : 24;& } pyxis$r_pci_tbase2_bits;% } pyxis$r_pci_tbase2_overlay;( unsigned char pyxis$b_fill440 [124];N/* */N/* PCI Window Base 3 - 0x8760000700 */N/* */ __union { int pyxis$l_pci_wbase3;F __struct {N unsigned pyxis$v_wbase3_w_en : 1; /* */N unsigned pyxis$v_wbase3_sg_en : 1; /* enable scatter/gather */N unsigned pyxis$v_wbase3_memcs_en : 1; /* enable MEMCS */N unsigned pyxis$v_wbase3_dac_en : 1; /* enable 64BIT PCI */N unsigned pyxis$v_wbase3_reserved : 16; /* */. unsigned pyxis$v_wbase3_base : 12;& } pyxis$r_pci_wbase3_bit Fs;% } pyxis$r_pci_wbase3_overlay;' unsigned char pyxis$b_fill450 [60];N/* */N/* PCI Window Mask 3 - 0x8760000740 */N/* */ __union { int pyxis$l_pci_wmask3; __struct {N unsigned pyxis$v_wmask3_reserved : 20; /* */. unsigned pyxis$v F_wmask3_mask : 12;& } pyxis$r_pci_wmask3_bits;% } pyxis$r_pci_wmask3_overlay;' unsigned char pyxis$b_fill460 [60];N/* */N/* PCI Window Translated Base 3 - 0x8760000780 */N/* */ __union { int pyxis$l_pci_tbase3; __struct {N unsigned pyxis$v_tbase3_reserved : 8; /* F */. unsigned pyxis$v_tbase3_base : 24;& } pyxis$r_pci_tbase3_bits;% } pyxis$r_pci_tbase3_overlay;' unsigned char pyxis$b_fill470 [60];N/* */N/* PCI DAC Base Register - 0x87600007C0 */N/* */ __union { int pyxis$l_pci_dac; __struct {* F unsigned pyxis$v_dac_base : 8;N unsigned pyxis$v_dac_reserved : 24; /* */# } pyxis$r_pci_dac_bits;" } pyxis$r_pci_dac_overlay;' unsigned char pyxis$b_fill480 [60];N/* */N/* PCI Lockable TB Tag 0- 0x8760000800 */N/* */ __union { in Ft pyxis$l_pci_ltb0; __struct {N unsigned pyxis$v_ltb0_valid : 1; /* */N unsigned pyxis$v_ltb0_locked : 1; /* enable scatter/gather */N unsigned pyxis$v_ltb0_dac : 1; /* enable 64BIT PCI */N unsigned pyxis$v_ltb0_reserved : 12; /* */+ unsigned pyxis$v_ltb0_tag : 17;$ } pyxis$r_pci_ltb0_bits;# } pyxis$r_pci_ltb0_overlay;' unsigned char py Fxis$b_fill490 [60];N/* */N/* PCI Lockable TB Tag 1- 0x8760000840 */N/* */ __union { int pyxis$l_pci_ltb1; __struct {N unsigned pyxis$v_ltb1_valid : 1; /* */N unsigned pyxis$v_ltb1_locked : 1; /* enable scatter/gather */N un Fsigned pyxis$v_ltb1_dac : 1; /* enable 64BIT PCI */N unsigned pyxis$v_ltb1_reserved : 12; /* */+ unsigned pyxis$v_ltb1_tag : 17;$ } pyxis$r_pci_ltb1_bits;# } pyxis$r_pci_ltb1_overlay;' unsigned char pyxis$b_fill500 [60];N/* */N/* PCI Lockable TB Tag 2- 0x8760000880 */N/* F */ __union { int pyxis$l_pci_ltb2; __struct {N unsigned pyxis$v_ltb2_valid : 1; /* */N unsigned pyxis$v_ltb2_locked : 1; /* enable scatter/gather */N unsigned pyxis$v_ltb2_dac : 1; /* enable 64BIT PCI */N unsigned pyxis$v_ltb2_reserved : 12; /* */+ unsigned pyxis$v_ltb2_tag : 17;$ } pyxis$r_pci_ Fltb2_bits;# } pyxis$r_pci_ltb2_overlay;' unsigned char pyxis$b_fill510 [60];N/* */N/* PCI Lockable TB Tag 3- 0x87600008C0 */N/* */ __union { int pyxis$l_pci_ltb3; __struct {N unsigned pyxis$v_ltb3_valid : 1; /* */N unsigned pyx Fis$v_ltb3_locked : 1; /* enable scatter/gather */N unsigned pyxis$v_ltb3_dac : 1; /* enable 64BIT PCI */N unsigned pyxis$v_ltb3_reserved : 12; /* */+ unsigned pyxis$v_ltb3_tag : 17;$ } pyxis$r_pci_ltb3_bits;# } pyxis$r_pci_ltb3_overlay;' unsigned char pyxis$b_fill520 [60];N/* */N/* PCI TB Tag 0- 0x8760000900 F */N/* */ __union { int pyxis$l_pci_tb0; __struct {N unsigned pyxis$v_tb0_valid : 1; /* */N unsigned pyxis$v_reserved : 1; /* */N unsigned pyxis$v_tb0_dac : 1; /* enable 64BIT PCI */N unsigned pyxis$v_tb0_reserved2 : 12; /* */* F unsigned pyxis$v_tb0_tag : 17;# } pyxis$r_pci_tb0_bits;" } pyxis$r_pci_tb0_overlay;' unsigned char pyxis$b_fill530 [60];N/* */N/* PCI TB Tag 1 - 0x8760000940 */N/* */ __union { int pyxis$l_pci_tb1; __struct {N unsigned pyxis$v_tb1_valid : 1 G; /* */N unsigned pyxis$v_tb1_reserved : 1; /* */N unsigned pyxis$v_tb1_dac : 1; /* enable 64BIT PCI */N unsigned pyxis$v_tb1_reserved2 : 12; /* */* unsigned pyxis$v_tb1_tag : 17;# } pyxis$r_pci_tb1_bits;" } pyxis$r_pci_tb1_overlay;' unsigned char pyxis$b_fill540 [60];N/* G */N/* PCI TB Tag 2 - 0x8760000980 */N/* */ __union { int pyxis$l_pci_tb2; __struct {N unsigned pyxis$v_tb2_valid : 1; /* */N unsigned pyxis$v_tb2_reserved : 1; /* */N unsigned pyxis$v_tb2_dac : 1; /* enable 64BIT PCI */N unsigned pyxis G$v_tb2_reserved2 : 12; /* */* unsigned pyxis$v_tb2_tag : 17;# } pyxis$r_pci_tb2_bits;" } pyxis$r_pci_tb2_overlay;' unsigned char pyxis$b_fill550 [60];N/* */N/* PCI TB Tag 3- 0x87600009C0 */N/* */ __union { int pyxis$l_pci_tb3; G __struct {N unsigned pyxis$v_tb3_valid : 1; /* */N unsigned pyxis$v_tb3_reserved : 1; /* */N unsigned pyxis$v_tb3_dac : 1; /* enable 64BIT PCI */N unsigned pyxis$v_tb3_reserved2 : 12; /* */* unsigned pyxis$v_tb3_tag : 17;# } pyxis$r_pci_tb3_bits;" } pyxis$r_pci_tb3_overlay;) unsigned char pyxis$b_fill560 [1596];N/* G */N/* PCI TB0 Page 0- 0x8760001000 */N/* */ __union {" int pyxis$l_pci_tb0_page0; __struct {N unsigned pyxis$v_tb0_page0_valid : 1; /* */1 unsigned pyxis$v_tb0_page0_addr : 21;N unsigned pyxis$v_fill : 10; /* G */) } pyxis$r_pci_tb0_page0_bits;( } pyxis$r_pci_tb0_page0_overlay;' unsigned char pyxis$b_fill570 [60];N/* */N/* PCI TB0 Page 1 - 0x8760001040 */N/* */ __union {" int pyxis$l_pci_tb0_page1; __struct {N unsigned pyxis$v_tb0_page1_valid : 1; /* G */1 unsigned pyxis$v_tb0_page1_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb0_page1_bits;( } pyxis$r_pci_tb0_page1_overlay;' unsigned char pyxis$b_fill580 [60];N/* */N/* PCI TB0 Page 2 - 0x8760001080 */N/* G */ __union {" int pyxis$l_pci_tb0_page2; __struct {N unsigned pyxis$v_tb0_page2_valid : 1; /* */1 unsigned pyxis$v_tb0_page2_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb0_page2_bits;( } pyxis$r_pci_tb0_page2_overlay;' unsigned char pyxis$b_fill590 [60];N/* G */N/* PCI TB0 Page 3- 0x87600010C0 */N/* */ __union {" int pyxis$l_pci_tb0_page3; __struct {N unsigned pyxis$v_tb0_page3_valid : 1; /* */1 unsigned pyxis$v_tb0_page3_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb0_page3_bits;( G } pyxis$r_pci_tb0_page3_overlay;' unsigned char pyxis$b_fill600 [60];N/* */N/* PCI TB1 Page 0- 0x8760001100 */N/* */ __union {" int pyxis$l_pci_tb1_page0; __struct {N unsigned pyxis$v_tb1_page0_valid : 1; /* */1 unsigned pyxis$v_tb1_p Gage0_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb1_page0_bits;( } pyxis$r_pci_tb1_page0_overlay;' unsigned char pyxis$b_fill610 [60];N/* */N/* PCI TB1 Page 1 - 0x8760001140 */N/* */ __union {" int pyxis$l_pci_ Gtb1_page1; __struct {N unsigned pyxis$v_tb1_page1_valid : 1; /* */1 unsigned pyxis$v_tb1_page1_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb1_page1_bits;( } pyxis$r_pci_tb1_page1_overlay;' unsigned char pyxis$b_fill620 [60];N/* */N/* PCI TB1 Page 2 - 0x8760001180 G */N/* */ __union {" int pyxis$l_pci_tb1_page2; __struct {N unsigned pyxis$v_tb1_page2_valid : 1; /* */1 unsigned pyxis$v_tb1_page2_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb1_page2_bits;( } pyxis$r_pci_tb1_page2_overlay;' unsigned char pyxis$b_ Gfill630 [60];N/* */N/* PCI TB1 Page 3- 0x87600011C0 */N/* */ __union {" int pyxis$l_pci_tb1_page3; __struct {N unsigned pyxis$v_tb1_page3_valid : 1; /* */1 unsigned pyxis$v_tb1_page3_addr : 21;N unsigned pyxis$v_fill : 10; /* G */) } pyxis$r_pci_tb1_page3_bits;( } pyxis$r_pci_tb1_page3_overlay;' unsigned char pyxis$b_fill640 [60];N/* */N/* PCI TB2 Page 0- 0x8760001200 */N/* */ __union {" int pyxis$l_pci_tb2_page0; __struct {N unsigned pyxis$v G_tb2_page0_valid : 1; /* */1 unsigned pyxis$v_tb2_page0_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb2_page0_bits;( } pyxis$r_pci_tb2_page0_overlay;' unsigned char pyxis$b_fill650 [60];N/* */N/* PCI TB2 Page 1 - 0x8760001240 */N/* G */ __union {" int pyxis$l_pci_tb2_page1; __struct {N unsigned pyxis$v_tb2_page1_valid : 1; /* */1 unsigned pyxis$v_tb2_page1_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb2_page1_bits;( } pyxis$r_pci_tb2_page1_overlay;' unsigned char pyxis$b_fill660 [60];N/* G */N/* PCI TB2 Page 2 - 0x8760001280 */N/* */ __union {" int pyxis$l_pci_tb2_page2; __struct {N unsigned pyxis$v_tb2_page2_valid : 1; /* */1 unsigned pyxis$v_tb2_page2_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_ Gtb2_page2_bits;( } pyxis$r_pci_tb2_page2_overlay;' unsigned char pyxis$b_fill670 [60];N/* */N/* PCI TB2 Page 3- 0x87600012C0 */N/* */ __union {" int pyxis$l_pci_tb2_page3; __struct {N unsigned pyxis$v_tb2_page3_valid : 1; /* */1 G unsigned pyxis$v_tb2_page3_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb2_page3_bits;( } pyxis$r_pci_tb2_page3_overlay;' unsigned char pyxis$b_fill680 [60];N/* */N/* PCI TB3 Page 0- 0x8760001300 */N/* */ __union {" G int pyxis$l_pci_tb3_page0; __struct {N unsigned pyxis$v_tb3_page0_valid : 1; /* */1 unsigned pyxis$v_tb3_page0_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb3_page0_bits;( } pyxis$r_pci_tb3_page0_overlay;' unsigned char pyxis$b_fill690 [60];N/* */N/* PCI TB3 Page 1 - 0x876000 G1340 */N/* */ __union {" int pyxis$l_pci_tb3_page1; __struct {N unsigned pyxis$v_tb3_page1_valid : 1; /* */1 unsigned pyxis$v_tb3_page1_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb3_page1_bits;( } pyxis$r_pci_tb3_page1_overlay;' G unsigned char pyxis$b_fill700 [60];N/* */N/* PCI TB3 Page 2 - 0x8760001380 */N/* */ __union {" int pyxis$l_pci_tb3_page2; __struct {N unsigned pyxis$v_tb3_page2_valid : 1; /* */1 unsigned pyxis$v_tb3_page2_addr : 21;N unsigned G pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb3_page2_bits;( } pyxis$r_pci_tb3_page2_overlay;' unsigned char pyxis$b_fill710 [60];N/* */N/* PCI TB3 Page 3- 0x87600013C0 */N/* */ __union {" int pyxis$l_pci_tb3_page3; __struct {N G unsigned pyxis$v_tb3_page3_valid : 1; /* */1 unsigned pyxis$v_tb3_page3_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb3_page3_bits;( } pyxis$r_pci_tb3_page3_overlay;' unsigned char pyxis$b_fill720 [60];N/* */N/* PCI TB4 Page 0- 0x8760001400 */N/* G */ __union {" int pyxis$l_pci_tb4_page0; __struct {N unsigned pyxis$v_tb4_page0_valid : 1; /* */1 unsigned pyxis$v_tb4_page0_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb4_page0_bits;( } pyxis$r_pci_tb4_page0_overlay;' unsigned char pyxis$b_fill730 [60];N/* G */N/* PCI TB4 Page 1 - 0x8760001440 */N/* */ __union {" int pyxis$l_pci_tb4_page1; __struct {N unsigned pyxis$v_tb4_page1_valid : 1; /* */1 unsigned pyxis$v_tb4_page1_addr : 21;N unsigned pyxis$v_fill : 10; /* */) G } pyxis$r_pci_tb4_page1_bits;( } pyxis$r_pci_tb4_page1_overlay;' unsigned char pyxis$b_fill740 [60];N/* */N/* PCI TB4 Page 2 - 0x8760001480 */N/* */ __union {" int pyxis$l_pci_tb4_page2; __struct {N unsigned pyxis$v_tb4_page2_valid : 1; /* G */1 unsigned pyxis$v_tb4_page2_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb4_page2_bits;( } pyxis$r_pci_tb4_page2_overlay;' unsigned char pyxis$b_fill750 [60];N/* */N/* PCI TB4 Page 3- 0x87600014C0 */N/* G */ __union {" int pyxis$l_pci_tb4_page3; __struct {N unsigned pyxis$v_tb4_page3_valid : 1; /* */1 unsigned pyxis$v_tb4_page3_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb4_page3_bits;( } pyxis$r_pci_tb4_page3_overlay;' unsigned char pyxis$b_fill760 [60];N/* */N/* P GCI TB5 Page 0- 0x8760001500 */N/* */ __union {" int pyxis$l_pci_tb5_page0; __struct {N unsigned pyxis$v_tb5_page0_valid : 1; /* */1 unsigned pyxis$v_tb5_page0_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb5_page0_bits;( } pyxis$r_pc Gi_tb5_page0_overlay;' unsigned char pyxis$b_fill770 [60];N/* */N/* PCI TB5 Page 1 - 0x8760001540 */N/* */ __union {" int pyxis$l_pci_tb5_page1; __struct {N unsigned pyxis$v_tb5_page1_valid : 1; /* */1 unsigned pyxis$v_tb5_page1_addr : 21 G;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb5_page1_bits;( } pyxis$r_pci_tb5_page1_overlay;' unsigned char pyxis$b_fill780 [60];N/* */N/* PCI TB5 Page 2 - 0x8760001580 */N/* */ __union {" int pyxis$l_pci_tb5_page2; !G __struct {N unsigned pyxis$v_tb5_page2_valid : 1; /* */1 unsigned pyxis$v_tb5_page2_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb5_page2_bits;( } pyxis$r_pci_tb5_page2_overlay;' unsigned char pyxis$b_fill790 [60];N/* */N/* PCI TB5 Page 3- 0x87600015C0 "G */N/* */ __union {" int pyxis$l_pci_tb5_page3; __struct {N unsigned pyxis$v_tb5_page3_valid : 1; /* */1 unsigned pyxis$v_tb5_page3_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb5_page3_bits;( } pyxis$r_pci_tb5_page3_overlay;' unsigned char pyxis$b_fill800 [60]; #GN/* */N/* PCI TB6 Page 0- 0x8760001600 */N/* */ __union {" int pyxis$l_pci_tb6_page0; __struct {N unsigned pyxis$v_tb6_page0_valid : 1; /* */1 unsigned pyxis$v_tb6_page0_addr : 21;N unsigned pyxis$v_fill : 10; /* $G */) } pyxis$r_pci_tb6_page0_bits;( } pyxis$r_pci_tb6_page0_overlay;' unsigned char pyxis$b_fill810 [60];N/* */N/* PCI TB6 Page 1 - 0x8760001640 */N/* */ __union {" int pyxis$l_pci_tb6_page1; __struct {N unsigned pyxis$v_tb6_page1_val %Gid : 1; /* */1 unsigned pyxis$v_tb6_page1_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb6_page1_bits;( } pyxis$r_pci_tb6_page1_overlay;' unsigned char pyxis$b_fill820 [60];N/* */N/* PCI TB6 Page 2 - 0x8760001680 */N/* &G */ __union {" int pyxis$l_pci_tb6_page2; __struct {N unsigned pyxis$v_tb6_page2_valid : 1; /* */1 unsigned pyxis$v_tb6_page2_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb6_page2_bits;( } pyxis$r_pci_tb6_page2_overlay;' unsigned char pyxis$b_fill830 [60];N/* 'G */N/* PCI TB6 Page 3- 0x87600016C0 */N/* */ __union {" int pyxis$l_pci_tb6_page3; __struct {N unsigned pyxis$v_tb6_page3_valid : 1; /* */1 unsigned pyxis$v_tb6_page3_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb6_page3_bits (G;( } pyxis$r_pci_tb6_page3_overlay;' unsigned char pyxis$b_fill840 [60];N/* */N/* PCI TB7 Page 0- 0x8760001700 */N/* */ __union {" int pyxis$l_pci_tb7_page0; __struct {N unsigned pyxis$v_tb7_page0_valid : 1; /* */1 unsigned pyx )Gis$v_tb7_page0_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb7_page0_bits;( } pyxis$r_pci_tb7_page0_overlay;' unsigned char pyxis$b_fill850 [60];N/* */N/* PCI TB7 Page 1 - 0x8760001740 */N/* */ __union {" int py *Gxis$l_pci_tb7_page1; __struct {N unsigned pyxis$v_tb7_page1_valid : 1; /* */1 unsigned pyxis$v_tb7_page1_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb7_page1_bits;( } pyxis$r_pci_tb7_page1_overlay;' unsigned char pyxis$b_fill860 [60];N/* */N/* PCI TB7 Page 2 - 0x8760001780 +G */N/* */ __union {" int pyxis$l_pci_tb7_page2; __struct {N unsigned pyxis$v_tb7_page2_valid : 1; /* */1 unsigned pyxis$v_tb7_page2_addr : 21;N unsigned pyxis$v_fill : 10; /* */) } pyxis$r_pci_tb7_page2_bits;( } pyxis$r_pci_tb7_page2_overlay;' unsigned cha ,Gr pyxis$b_fill870 [60];N/* */N/* PCI TB7 Page 3- 0x87600017C0 */N/* */ __union {" int pyxis$l_pci_tb7_page3; __struct {N unsigned pyxis$v_tb7_page3_valid : 1; /* */1 unsigned pyxis$v_tb7_page3_addr : 21;N unsigned pyxis$v_fill -G: 10; /* */) } pyxis$r_pci_tb7_page3_bits;( } pyxis$r_pci_tb7_page3_overlay;) unsigned char pyxis$b_fill880 [2108];N/* */N/* Clock Configuration register - 0x8780000000 */N/* */ __union {! int pyxis$l_clock_config; __struct {N unsi.Ggned pyxis$v_ccr_clock_divide : 2; /* 1:0 */0 unsigned pyxis$v_ccr_reserved_1 : 5;N unsigned pyxis$v_ccr_pclk_divide : 3; /* 10:8 */0 unsigned pyxis$v_ccr_reserved_2 : 1;N unsigned pyxis$v_ccr_sel_cfg : 1; /* 12 */0 unsigned pyxis$v_ccr_reserved_3 : 3;N unsigned pyxis$v_ccr_dclk_inv : 1; /* 16 */N unsigned pyxis$v_ccr_dclk_force : 1; /* /G17 */0 unsigned pyxis$v_ccr_reserved_4 : 7;N unsigned pyxis$v_ccr_dclk_delay : 8; /* 31:24 */ } pyxis$r_ccr_bits;' } pyxis$r_clock_config_overlay;) unsigned char pyxis$b_fill890 [2300];N/* */N/* RESET register - 0x8780000900 */N/* 0G */ __union { int pyxis$l_reset; } pyxis$r_reset_overlay;) unsigned char pyxis$b_fill892 [5884];N/* */N/* Fan Accumulation register - 0x8790000000 */N/* */ __union { int pyxis$l_far_reg; __struct {N unsigned pyxis$v_far_heat : 24; /* 23:0 1G */0 unsigned pyxis$v_far_reserved_1 : 7;) unsigned pyxis$v_fill_4_ : 1; } pyxis$r_far_bits; } pyxis$r_far_overlay;( unsigned char pyxis$b_fillaa00 [60];N/* */N/* Fan Control register - 0x8790000040 */N/* */ __union { int pyxis$l_fcr_reg; 2G __struct {N unsigned pyxis$v_fcr_on_heat : 8; /* 7:0 */N unsigned pyxis$v_fcr_sample : 8; /* 15:8 */N unsigned pyxis$v_fcr_off_delay : 12; /* 27:16 */N unsigned pyxis$v_fcr_force_fan : 1; /* 28 */N unsigned pyxis$v_fcr_force_fan_hi : 1; /* 29 */N unsigned pyxis$v_fcr_fan_on : 1; /* 30 */N 3G unsigned pyxis$v_fcr_fan_on_hi : 1; /* 31 */ } pyxis$r_fcr_bits; } pyxis$r_fcr_overlay;( unsigned char pyxis$b_fillaa01 [60];N/* */N/* Fan THRESHOLD register - 0x8790000080 */N/* */ __union { int pyxis$l_ftr_reg; __struct {N unsi 4Ggned pyxis$v_ftr_fan_on : 8; /* 7:0 */N unsigned pyxis$v_ftr_fan_hi : 8; /* 15:8 */N unsigned pyxis$v_ftr_fan_hi_lo : 8; /* 23:16 */N unsigned pyxis$v_ftr_fan_off : 8; /* 31:24 */ } pyxis$r_ftr_bits; } pyxis$r_ftr_overlay;( unsigned char pyxis$b_fillaa02 [60];N/* */N/* Power Contr 5Gol register - 0x87900000C0 */N/* */ __union { int pyxis$l_pcr_reg; __struct {N unsigned pyxis$v_pcr_power_down : 1; /* 0 */+ unsigned pyxis$v_pcr_fill1 : 3;N unsigned pyxis$v_pcr_abus_dis : 1; /* 4 */+ unsigned pyxis$v_pcr_fill2 : 3;N unsigned pyxis$v_pcr_iint_di 6Gs : 1; /* 8 */+ unsigned pyxis$v_pcr_fill3 : 3;N unsigned pyxis$v_pcr_do_reset : 1; /* 12 */, unsigned pyxis$v_pcr_fill4 : 19; } pyxis$r_pcr_bits; } pyxis$r_pcr_overlay;( unsigned char pyxis$b_fillaa03 [60];N/* */N/* Powerdown Timing register - 0x8790000100 */N/* 7G */ __union { int pyxis$l_ptr_reg; __struct {N unsigned pyxis$v_ptr_pll_delay : 8; /* 7:0 */N unsigned pyxis$v_ptr_off_delay : 8; /* 15:8 */N unsigned pyxis$v_ptr_reset_pulse_width : 8; /* 23:16 */N unsigned pyxis$v_ptr_min_off_time : 8; /* 31:24 */ } pyxis$r_ptr_bits; } pyxis$r_ptr_overlay; 8G( unsigned char pyxis$b_fillaa04 [60];N/* */N/* Power Management register - 0x8790000140 */N/* */ __union { int pyxis$l_psr_reg; } pyxis$r_psr_overlay;* unsigned char pyxis$b_fillaa05 [7868];N/* */N/* Int Request Regis 9Gter - 0x87A0000000 */N/* */ __union { __int64 pyxis$q_int_req; __struct {N unsigned pyxis$v_int_req_31_0 : 32; /* 31:0 */N unsigned pyxis$v_int_req_61_32 : 30; /* 61:32 */N unsigned pyxis$v_int_req_clk_pend : 1; /* 62 */N unsigned pyxis$v_int_req_err_int : 1; /* 6 :G3 */# } pyxis$r_int_req_bits;" } pyxis$r_int_req_overlay;( unsigned char pyxis$b_fillab00 [56];N/* */N/* Int Mask Register - 0x87A0000040 */N/* */ __union {! __int64 pyxis$q_int_mask; __struct {N unsigned pyxis$v_int_mask_31_0 : 32; / ;G* 31:0 */N unsigned pyxis$v_int_mask_61_32 : 30; /* 61:32 */N unsigned pyxis$v_int_mask_fill : 2; /* 63 */$ } pyxis$r_int_mask_bits;# } pyxis$r_int_mask_overlay;) unsigned char pyxis$b_fillab01 [120];N/* */N/* Interrupt High/Low select register - 0x87A00000C0 */N/* G */N/* General Purpose Output register - 0x87A0000180 */N/* */ __union {% __int64 pyxis$q_gpo_register; } pyxis$r_gpo_overlay;( unsigned char pyxis$b_fillab04 [56];N/* */N/* Interrupt Config register - 0x87A00001C0 */N/* ?G */ __union { int pyxis$l_int_config; __struct {N unsigned pyxis$v_icnfg_clk_div : 4; /* */N unsigned pyxis$v_icnfg_irq_cnt : 3; /* */- unsigned pyxis$v_icnfg_fill1 : 1;N unsigned pyxis$v_icnfg_irq_cfg : 7; /* */- unsigned pyxis$v_icnfg_fill2 : 1;N unsigned pyxis$v_icnfg_drive_irq : 1; /* @G */) unsigned pyxis$v_fill_6_ : 7;$ } pyxis$r_int_cnfg_bits;% } pyxis$r_int_config_overlay;( unsigned char pyxis$b_fillab05 [60];N/* */N/* Real Time Counter - 0x87A0000200 */N/* */ __union {* __int64 pyxis$q_real_time_counter;, } pyxis$r_real_time_co AGunter_overlay;( unsigned char pyxis$b_fillab06 [56];N/* */N/* Interrupt Timer - 0x87A0000240 */N/* */ __union {( __int64 pyxis$q_interrupt_timer;# } pyxis$r_int_time_overlay;) unsigned char pyxis$b_fillab07 [120];N/* BG */N/* IIC Control register - 0x87A00002C0 */N/* */ __union { int pyxis$l_iic_control; __struct {N unsigned pyxis$v_iic_read_data : 1; /* */N unsigned pyxis$v_iic_read_clk : 1; /* */N unsigned pyxis$v_iic_data_en : 1; /* */N unsigned p CGyxis$v_iic_data : 1; /* */N unsigned pyxis$v_iic_clk_en : 1; /* */N unsigned pyxis$v_iic_clk : 1; /* */+ unsigned pyxis$v_iic_fill : 26;$ } pyxis$r_iic_ctrl_bits;& } pyxis$r_iic_control_overlay;* unsigned char pyxis$b_fillab08 [7484];N/* */N/* CUSCO CPU CSR Registers 87C0100000 DG */N/* */ char pyxis$b_cpu_csr0; char pyxis$b_cpu_csr1;* unsigned char pyxis$b_fillab09 [4094];N/* */N/* CUSCO Clock registers 87.C010.1000 */N/* */ __union {" char pyxis$b_fraction_EGsec; __struct {( unsigned pyxis$v_sec_01 : 4;' unsigned pyxis$v_sec_1 : 4;( } pyxis$r_fraction_sec_bits;' } pyxis$r_fraction_sec_overlay; __union {! char pyxis$b_second_byte; __struct {( unsigned pyxis$v_second : 4;( unsigned pyxis$v_sec_10 : 3;) unsigned pyxis$v_fill_7_ : 1;" } pyxis$r_second_bits;! } pyxis$r_second_overlay; __union {! char pyxis$bFG_minute_byte; __struct {( unsigned pyxis$v_minute : 4;( unsigned pyxis$v_min_10 : 3;) unsigned pyxis$v_fill_8_ : 1;" } pyxis$r_minute_bits;! } pyxis$r_minute_overlay; __union {$ char pyxis$b_min_alarm_byte; __struct {+ unsigned pyxis$v_alarm_min : 4;. unsigned pyxis$v_alarm_min_10 : 3;/ unsigned pyxis$v_set_min_alarm : 1;% } pyxis$r_min_alarm_bits;$ GG} pyxis$r_min_alarm_overlay; __union { char pyxis$b_hour_byte; __struct {& unsigned pyxis$v_hour : 4;) unsigned pyxis$v_hour_10 : 1;) unsigned pyxis$v_ap_10hr : 1;( unsigned pyxis$v_twelve : 1;) unsigned pyxis$v_fill_9_ : 1; } pyxis$r_hour_bits; } pyxis$r_hour_overlay; __union {% char pyxis$b_hour_alarm_byte; __struct {, unsigned pyxis$v_alarm_hour : 4;HG/ unsigned pyxis$v_alarm_hour_10 : 1;/ unsigned pyxis$v_alarm_ap_10hr : 1;. unsigned pyxis$v_alarm_twelve : 1;0 unsigned pyxis$v_set_hour_alarm : 1;& } pyxis$r_hour_alarm_bits;% } pyxis$r_hour_alarm_overlay; __union { char pyxis$b_day_byte; __struct {% unsigned pyxis$v_day : 3;* unsigned pyxis$v_fill_10_ : 5; } pyxis$r_day_bits; } pyxis$r_day_overlay; __IGunion {$ char pyxis$b_day_alarm_byte; __struct {+ unsigned pyxis$v_day_alarm : 3;/ unsigned pyxis$v_day_alarm_mbz : 4;/ unsigned pyxis$v_set_day_alarm : 1;% } pyxis$r_day_alarm_bits;$ } pyxis$r_day_alarm_overlay; __union { char pyxis$b_date_byte; __struct {& unsigned pyxis$v_date : 4;) unsigned pyxis$v_date_10 : 2;* unsigned pyxis$v_fill_11_ : 2; JG} pyxis$r_date_bits; } pyxis$r_date_overlay; __union { char pyxis$b_month_byte; __struct {' unsigned pyxis$v_month : 4;* unsigned pyxis$v_month_10 : 1;+ unsigned pyxis$v_month_mbz : 1;& unsigned pyxis$v_esqw : 1;& unsigned pyxis$v_eosc : 1;! } pyxis$r_month_bits; } pyxis$r_month_overlay; __union { char pyxis$b_year_byte; __struct {& unsigned pyx KGis$v_year : 4;) unsigned pyxis$v_year_10 : 4; } pyxis$r_year_bits; } pyxis$r_year_overlay;N/* */N/* The CUSCO Clock Command Register 87.C010.000B */N/* */ __union {' char pyxis$b_command_1286_byte; __struct {% unsigned pyxis$v_tdf : 1;% unsign LGed pyxis$v_waf : 1;% unsigned pyxis$v_tdm : 1;% unsigned pyxis$v_wam : 1;( unsigned pyxis$v_pu_lvl : 1;( unsigned pyxis$v_ibh_lo : 1;& unsigned pyxis$v_ipsw : 1;$ unsigned pyxis$v_te : 1;( } pyxis$r_command_1286_bits;' } pyxis$r_command_1286_overlay;N/* */N/* The CUSCO Watchdog Alarm Register 87.C010.000C */MGN/* */ __union {! char pyxis$b_wdog_c_byte; __struct {- unsigned pyxis$v_wdog_01_sec : 4;, unsigned pyxis$v_wdog_1_sec : 4;" } pyxis$r_wdog_c_bits;& } pyxis$r_wdog_1286_c_overlay; __union {! char pyxis$b_wdog_d_byte; __struct {* unsigned pyxis$v_wdog_sec : 4;, unsigned pyxis$v_wdog_10sec : 4;" } py NGxis$r_wdog_d_bits;& } pyxis$r_wdog_1286_d_overlay;N/* */N/* 0x32 (50) unused User Registers */N/* */( unsigned char pyxis$b_fillab10 [50];N/* */N/* A bunch more fill to get up to the PASS 2 base, */N/* OG 87.C010.2000 */N/* */* unsigned char pyxis$b_fillab11 [8128];N/* */N/* CUSCO Vintage Interrupt Registers 87.C010.2000 */N/* */N/* PG */N/* VDIVR - Device Interrupt Vector Register - 87.C010.2000 */N/* */ __union { char pyxis$b_vdivr; } pyxis$r_vdivr_overlay;( unsigned char pyxis$b_fillab12 [31];N/* */N/* V1ISR - IPL 1 Interrupt Summary Register - 87.C010.2020 */N/* QG */ __union { char pyxis$b_v1isr; } pyxis$r_v1isr_overlay;( unsigned char pyxis$b_fillab13 [31];N/* */N/* V2ISR - IPL 2 Interrupt Summary Register - 87.C010.2040 */N/* */ __union { char pyxis$b_v2isr; } pyxis$r_v2isr_overlay;( unsigned char pyxis$b_fillab14 RG [31];N/* */N/* V3ISR - IPL 3 Interrupt Summary Register - 87.C010.2060 */N/* */ __union { char pyxis$b_v3isr; } pyxis$r_v3isr_overlay;( unsigned char pyxis$b_fillab15 [31];N/* */N/* VDIER - Device Interrupt Enable Register - 87C010.20 SG80 */N/* */ __union { char pyxis$b_vdier; } pyxis$r_vdier_overlay;( unsigned char pyxis$b_fillab16 [31];N/* */N/* V1IER - IPL1 Interrupt Enable Register - 87.C010.20A0 */N/* */ __union { char pyxis$b_v1i TGer; } pyxis$r_v1ier_overlay;( unsigned char pyxis$b_fillab17 [31];N/* */N/* V2IER - IPL2 Interrupt Enable Register - 87.C010.20C0 */N/* */ __union { char pyxis$b_v2ier; } pyxis$r_v2ier_overlay;( unsigned char pyxis$b_fillab18 [31];N/* UG */N/* V3IER - IPL3 Interrupt Enable Register - 87.C010.20E0 */N/* */ __union { char pyxis$b_v3ier; } pyxis$r_v3ier_overlay;( unsigned char pyxis$b_fillab19 [31];N/* */N/* VMCSR - Master Control and Status Register - 87.C010.2100 */N/* VG */ __union { char pyxis$b_vmcsr; } pyxis$r_vmcsr_overlay;( unsigned char pyxis$b_fillab20 [63];N/* */N/* VACSR - Agent Control and Status Register - 87.C010.2140 */N/* */ __union { char pyxis$b_vacsr; } pyxis$r_vacsr_overlay;( unsigned char pyxis$b_fill WGab21 [31];N/* */N/* BIDR- Backplane ID - 87.C010.2160 */N/* */ __union { char pyxis$b_bidr; } pyxis$r_bidr_overlay;) unsigned char pyxis$b_fillab22 [671];N/* */N/* Following are the interrupt control and status reXGgisters. They */N/* all have the same format, except for VSICSR0 which only has one */N/* active control and one active status bit. That format is: */N/* */N/* bit <0> INTA# Enable */N/* bit <1> INTB# Enable */N/* bit <2> INTC# Enable */YGN/* bit <3> INTC# Enable */N/* bit <4> INTA# Status */N/* bit <5> INTB# Status */N/* bit <6> INTC# Status */N/* bit <7> INTD# Status */N/* 0: Disabled */N/* ZG 1: Enabled */N/* */N/* I have not defined the bits for each register, since the code will */N/* not use them. The code simply sets the bit indicated by the int */N/* portion of the INT_LINE register. */N/* */N/* [G */R/* VSICSR0 - Bus 0 I/O Slot 0 Interrupt Control and Status Reg. - 87.C010.2400 */N/* */ __union { char pyxis$b_vsicsr0;" } pyxis$r_vsicsr0_overlay;( unsigned char pyxis$b_fillab23 [31];N/* */R/* VSICSR1 - Bus 0 I/O Slot 1 Interrupt Control and Status Reg. - 87.C010.2420 */N/* \G */ __union { char pyxis$b_vsicsr1;" } pyxis$r_vsicsr1_overlay;( unsigned char pyxis$b_fillab24 [31];N/* */R/* VSICSR2 - Bus 0 I/O Slot 2 Interrupt Control and Status Reg. - 87.C010.2440 */N/* */ __union { char pyxis$b_vsicsr2;" } pyxis$r_vsicsr2_over ]Glay;( unsigned char pyxis$b_fillab25 [31];N/* */R/* VSICSR3 - Bus 0 I/O Slot 3 Interrupt Control and Status Reg. - 87.C010.2460 */N/* */ __union { char pyxis$b_vsicsr3;" } pyxis$r_vsicsr3_overlay;( unsigned char pyxis$b_fillab26 [31];N/* */R/* VSIC ^GSR4 - Bus 0 I/O Slot 4 Interrupt Control and Status Reg. - 87.C010.2480 */N/* */ __union { char pyxis$b_vsicsr4;" } pyxis$r_vsicsr4_overlay;( unsigned char pyxis$b_fillab27 [31];N/* */R/* VSICSR5 - Bus 0 I/O Slot 5 Interrupt Control and Status Reg. - 87.C010.24A0 */N/* _G */ __union { char pyxis$b_vsicsr5;" } pyxis$r_vsicsr5_overlay;( unsigned char pyxis$b_fillab28 [31];N/* */R/* VSICSR6 - Bus 0 I/O Slot 6 Interrupt Control and Status Reg. - 87.C010.24C0 */N/* */ __union { char pyxis$b_vsicsr6;" } pyxis$r_vsicsr6_overlay;( unsigned char pyxis$b_fillab `G29 [95];N/* */R/* VSICSR9 - Bus 1 I/O Slot 1 Interrupt Control and Status Reg. - 87.C010.2520 */N/* */ __union { char pyxis$b_vsicsr9;" } pyxis$r_vsicsr9_overlay;( unsigned char pyxis$b_fillab30 [31];N/* */R/* VSICSRA - Bus 1 I/O Slot 2 Interrupt Contr aGol and Status Reg. - 87.C010.2540 */N/* */ __union { char pyxis$b_vsicsra;" } pyxis$r_vsicsra_overlay;( unsigned char pyxis$b_fillab31 [31];N/* */R/* VSICSRB - Bus 1 I/O Slot 3 Interrupt Control and Status Reg. - 87.C010.2560 */N/* */ __union { bG char pyxis$b_vsicsrb;" } pyxis$r_vsicsrb_overlay;( unsigned char pyxis$b_fillab32 [31];N/* */R/* VSICSRC - Bus 1 I/O Slot 4 Interrupt Control and Status Reg. - 87.C010.2580 */N/* */ __union { char pyxis$b_vsicsrc;" } pyxis$r_vsicsrc_overlay;) unsigned char pyxis$b_fillab33 [159];N/* cG */S/* VSICSR11 - Bus 2 I/O Slot 1 Interrupt Control and Status Reg. - 87.C010.2620 */N/* */ __union { char pyxis$b_vsicsr11;# } pyxis$r_vsicsr11_overlay;( unsigned char pyxis$b_fillab34 [31];N/* */S/* VSICSR12 - Bus 2 I/O Slot 2 Interrupt Control and Status Reg. - 87.C010.26 dG40 */N/* */ __union { char pyxis$b_vsicsr12;# } pyxis$r_vsicsr12_overlay;( unsigned char pyxis$b_fillab35 [31];N/* */S/* VSICSR13 - Bus 2 I/O Slot 3 Interrupt Control and Status Reg. - 87.C010.2660 */N/* */ __union { char pyxis$b_vsicsr1 eG3;# } pyxis$r_vsicsr13_overlay;( unsigned char pyxis$b_fillab36 [31];N/* */S/* VSICSR14 - Bus 2 I/O Slot 4 Interrupt Control and Status Reg. - 87.C010.2680 */N/* */ __union { char pyxis$b_vsicsr14;# } pyxis$r_vsicsr14_overlay;( unsigned char pyxis$b_fillab37 [31];N/* fG */S/* VSICSR15 - Bus 2 I/O Slot 5 Interrupt Control and Status Reg. - 87.C010.26A0 */N/* */ __union { char pyxis$b_vsicsr15;# } pyxis$r_vsicsr15_overlay;( unsigned char pyxis$b_fillab38 [31];N/* */S/* VSICSR16 - Bus 2 I/O Slot 6 Interrupt Control and Status Reg. - 87.C010.26C0 */N/* gG */ __union { char pyxis$b_vsicsr16;# } pyxis$r_vsicsr16_overlay;( unsigned char pyxis$b_fillab39 [31];N/* */S/* VSICSR17 - Bus 2 I/O Slot 7 Interrupt Control and Status Reg. - 87.C010.26E0 */N/* */ __union { char pyxis$b_vsicsr17;# } pyxis$r_ hGvsicsr17_overlay; char pyxis$b_fill_12_ [7]; } PYXIS; #if !defined(__VAXC)N#define pyxis$l_pci_pyxis_rev pyxis$r_pci_pyxis_revision.pyxis$l_pci_pyxis_revW#define pyxis$b_pyxis_rev pyxis$r_pci_pyxis_revision.pyxis$r_rev_bits.pyxis$b_pyxis_rev;#define pyxis$l_pci_lat pyxis$r_pci_latency.pyxis$l_pci_latX#define pyxis$b_pci_latency pyxis$r_pci_latency.pyxis$r_latency_bits.pyxis$b_pci_latency>#define pyxis$l_pyxis_ctl pyxis$r_pyxis_ctrl.pyxis$l_pyxis_ctli#define pyxis$v_pyxis_ctrl_piGci_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_pci_ens#define pyxis$v_pyxis_ctrl_pci_lock_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_pci_lock_ens#define pyxis$v_pyxis_ctrl_pci_loop_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_pci_loop_eno#define pyxis$v_pyxis_ctrl_fst_bb_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_fst_bb_eni#define pyxis$v_pyxis_ctrl_mst_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bjGits.pyxis$v_pyxis_ctrl_mst_eni#define pyxis$v_pyxis_ctrl_mem_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_mem_enm#define pyxis$v_pyxis_ctrl_req64_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_req64_enm#define pyxis$v_pyxis_ctrl_ack64_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_ack64_enq#define pyxis$v_pyxis_ctrl_addr_pe_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_addr_pe_enk#define pyxis$v_pyxis_ctrlkG_perr_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_perr_ens#define pyxis$v_pyxis_ctrl_fill_err_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_fill_err_enq#define pyxis$v_pyxis_ctrl_ecc_chk_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_ecc_chk_enq#define pyxis$v_pyxis_ctrl_cack_en_pe pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_cack_en_pes#define pyxis$v_pyxis_ctrl_con_idle_bc pyxis$r_pyxis_ctrl.pyxis$r_pyxis_lGcontrol_bits.pyxis$v_pyxis_ctrl_con_idle_bcs#define pyxis$v_pyxis_ctrl_csr_ioa_byp pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_csr_ioa_bypu#define pyxis$v_pyxis_ctrl_io_flush_req pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_io_flush_reqw#define pyxis$v_pyxis_ctrl_cpu_flush_req pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_cpu_flush_reqq#define pyxis$v_pyxis_ctrl_arb_ev5_en pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctmGrl_arb_ev5_ens#define pyxis$v_pyxis_ctrl_en_arb_link pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_en_arb_linki#define pyxis$v_pyxis_ctrl_rd_typ pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_rd_typi#define pyxis$v_pyxis_ctrl_rl_typ pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_rl_typi#define pyxis$v_pyxis_ctrl_rm_typ pyxis$r_pyxis_ctrl.pyxis$r_pyxis_control_bits.pyxis$v_pyxis_ctrl_rm_typA#define pyxis$l_pyxis_ctl1 pyxis$r_pyxis_ctrl1.pnGyxis$l_pyxis_ctl1o#define pyxis$v_pyxis_ctrl1_ioa_ben pyxis$r_pyxis_ctrl1.pyxis$r_pyxis_control1_bits.pyxis$v_pyxis_ctrl1_ioa_beny#define pyxis$v_pyxis_ctrl1_pci_mwin_ena pyxis$r_pyxis_ctrl1.pyxis$r_pyxis_control1_bits.pyxis$v_pyxis_ctrl1_pci_mwin_enay#define pyxis$v_pyxis_ctrl1_pci_link_ena pyxis$r_pyxis_ctrl1.pyxis$r_pyxis_control1_bits.pyxis$v_pyxis_ctrl1_pci_link_enaw#define pyxis$v_pyxis_ctrl1_lw_par_mode pyxis$r_pyxis_ctrl1.pyxis$r_pyxis_control1_bits.pyxis$v_pyxis_ctrl1_lw_par_modeN#doGefine pyxis$l_pyxis_config pyxis$r_pyxis_config_overlay.pyxis$l_pyxis_configx#define pyxis$v_pyxis_cnfg_pci_width pyxis$r_pyxis_config_overlay.pyxis$r_pyxis_config_bits.pyxis$v_pyxis_cnfg_pci_widthx#define pyxis$v_pyxis_cnfg_iod_width pyxis$r_pyxis_config_overlay.pyxis$r_pyxis_config_bits.pyxis$v_pyxis_cnfg_iod_width?#define pyxis$l_hae_mem pyxis$r_hae_mem_overlay.pyxis$l_hae_mem`#define pyxis$v_hae_mem_reg_3 pyxis$r_hae_mem_overlay.pyxis$r_hae_mem_bits.pyxis$v_hae_mem_reg_3`#define pyxis$v_hae_pGmem_reg_2 pyxis$r_hae_mem_overlay.pyxis$r_hae_mem_bits.pyxis$v_hae_mem_reg_2`#define pyxis$v_hae_mem_reg_1 pyxis$r_hae_mem_overlay.pyxis$r_hae_mem_bits.pyxis$v_hae_mem_reg_1<#define pyxis$l_hae_io pyxis$r_hae_io_overlay.pyxis$l_hae_ioP#define pyxis$v_hae_io pyxis$r_hae_io_overlay.pyxis$r_hae_io_bits.pyxis$v_hae_io3#define pyxis$l_cfg pyxis$r_cfg_overlay.pyxis$l_cfgV#define pyxis$v_cfg_bits pyxis$r_cfg_overlay.pyxis$r_cgf_bits_overlay.pyxis$v_cfg_bitsH#define pyxis$l_pyxis_diag pyxis$r_pyxis_diaqGg_overlay.pyxis$l_pyxis_diagZ#define pyxis$v_from_en pyxis$r_pyxis_diag_overlay.pyxis$r_pyxis_diag_bits.pyxis$v_from_en^#define pyxis$v_use_check pyxis$r_pyxis_diag_overlay.pyxis$r_pyxis_diag_bits.pyxis$v_use_checkZ#define pyxis$v_fpe_pci pyxis$r_pyxis_diag_overlay.pyxis$r_pyxis_diag_bits.pyxis$v_fpe_pci`#define pyxis$v_fpe_to_ev5 pyxis$r_pyxis_diag_overlay.pyxis$r_pyxis_diag_bits.pyxis$v_fpe_to_ev5H#define pyxis$l_diag_check pyxis$r_diag_check_overlay.pyxis$l_diag_checkh#define pyxis$b_diag_cherGck_ecc pyxis$r_diag_check_overlay.pyxis$r_diag_check_bits.pyxis$b_diag_check_eccN#define pyxis$l_perf_monitor pyxis$r_perf_monitor_overlay.pyxis$l_perf_monitorN#define pyxis$l_perf_control pyxis$r_perf_control_overlay.pyxis$l_perf_controlE#define pyxis$l_pyxis_err pyxis$r_pyxis_err_overlay.pyxis$l_pyxis_errb#define pyxis$v_err_corr_ecc pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_corr_ecc`#define pyxis$v_err_unc_ecc pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_uncsG_ecc^#define pyxis$v_err_cpu_pe pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_cpu_pe`#define pyxis$v_err_mem_nem pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_mem_nemb#define pyxis$v_err_pci_serr pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_pci_serrb#define pyxis$v_err_pci_perr pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_pci_perrf#define pyxis$v_err_pci_adr_pe pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_pci_adr_pe`#dtGefine pyxis$v_err_m_abort pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_m_abort`#define pyxis$v_err_t_abort pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_t_abortf#define pyxis$v_err_pa_pte_inv pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_pa_pte_invh#define pyxis$v_err_ioa_timeout pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_ioa_timeoutl#define pyxis$v_err_lost_corr_ecc pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_couGrr_eccj#define pyxis$v_err_lost_unc_ecc pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_unc_ecch#define pyxis$v_err_lost_cpu_pe pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_cpu_pej#define pyxis$v_err_lost_mem_nem pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_mem_neml#define pyxis$v_err_lost_pci_perr pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_pci_perrp#define pyxis$v_err_lost_pci_adr_pe pyxis$r_pyxis_err_overlay.pyxivGs$r_pyxis_err_bits.pyxis$v_err_lost_pci_adr_pej#define pyxis$v_err_lost_m_abort pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_m_abortj#define pyxis$v_err_lost_t_abort pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_t_abortp#define pyxis$v_err_lost_pa_pte_inv pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_pa_pte_invr#define pyxis$v_err_lost_ioa_timeout pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_lost_ioa_timeout\#define pyxiwGs$v_err_valid pyxis$r_pyxis_err_overlay.pyxis$r_pyxis_err_bits.pyxis$v_err_validH#define pyxis$l_pyxis_stat pyxis$r_pyxis_stat_overlay.pyxis$l_pyxis_stat`#define pyxis$v_stat_pci_0 pyxis$r_pyxis_stat_overlay.pyxis$r_pyxis_stat_bits.pyxis$v_stat_pci_0`#define pyxis$v_stat_pci_1 pyxis$r_pyxis_stat_overlay.pyxis$r_pyxis_stat_bits.pyxis$v_stat_pci_1h#define pyxis$v_stat_ioa_valid pyxis$r_pyxis_stat_overlay.pyxis$r_pyxis_stat_bits.pyxis$v_stat_ioa_validf#define pyxis$v_stat_tlb_miss pyxis$r_pyxis_statxG_overlay.pyxis$r_pyxis_stat_bits.pyxis$v_stat_tlb_missZ#define pyxis$l_pyxis_error_mask pyxis$r_pyxis_error_mask_overlay.pyxis$l_pyxis_error_maskz#define pyxis$v_mask_corr_ecc_err pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_corr_ecc_errx#define pyxis$v_mask_unc_ecc_err pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_unc_ecc_errn#define pyxis$v_mask_cpu_pe pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_cpu_pepyG#define pyxis$v_mask_mem_nem pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_mem_nemr#define pyxis$v_mask_pci_serr pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_pci_serrr#define pyxis$v_mask_pci_perr pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_pci_perrv#define pyxis$v_mask_pci_adr_pe pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_pci_adr_pep#define pyxis$v_mask_m_abort pyxis$r_pyxzGis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_m_abortp#define pyxis$v_mask_t_abort pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_t_abortv#define pyxis$v_mask_pa_pte_inv pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_pa_pte_invx#define pyxis$v_mask_ioa_timeout pyxis$r_pyxis_error_mask_overlay.pyxis$r_pyxis_error_mask_bits.pyxis$v_mask_ioa_timeoutD#define pyxis$l_pyxis_synd pyxis$r_pyxis_syndrome.pyxis$l_pyxis_syndN#defin{Ge pyxis$r_pyxis_synd_bits pyxis$r_pyxis_syndrome.pyxis$r_pyxis_synd_bitsO#define pyxis$v_pyxis_syndrome0 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_syndrome0O#define pyxis$v_pyxis_syndrome1 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_syndrome1Y#define pyxis$v_pyxis_raw_check_bits pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_raw_check_bitsM#define pyxis$v_pyxis_synd_ce0 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_synd_ce0M#define pyxis$v_pyxis_synd_ce1 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_synd_ce1O#define pyxis$v_|Gpyxis_synd_uce0 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_synd_uce0O#define pyxis$v_pyxis_synd_uce1 pyxis$r_pyxis_synd_bits.pyxis$v_pyxis_synd_uce1P#define pyxis$q_pyxis_errdata pyxis$r_pyxis_errdat_overlay.pyxis$q_pyxis_errdataH#define pyxis$l_pyxis_mear pyxis$r_pyxis_mear_overlay.pyxis$l_pyxis_mearb#define pyxis$v_mear_addr_h pyxis$r_pyxis_mear_overlay.pyxis$r_pyxis_mear_bits.pyxis$v_mear_addr_hH#define pyxis$l_pyxis_mesr pyxis$r_pyxis_mesr_overlay.pyxis$l_pyxis_mesrh#define pyxis$v_mesr_addr_39}G32 pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_addr_3932j#define pyxis$v_mesr_dma_rd_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_dma_rd_nxmj#define pyxis$v_mesr_dma_wr_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_dma_wr_nxmj#define pyxis$v_mesr_cpu_rd_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_cpu_rd_nxmj#define pyxis$v_mesr_cpu_wr_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_cpu_wr_n~Gxmh#define pyxis$v_mesr_io_rd_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_io_rd_nxmh#define pyxis$v_mesr_io_wr_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_io_wr_nxmj#define pyxis$v_mesr_victim_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_victim_nxml#define pyxis$v_mesr_tlbfill_nxm pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_tlbfill_nxml#define pyxis$v_mesr_oword_index pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxiGs_mesr_bits.pyxis$v_mesr_oword_indexr#define pyxis$v_mesr_data_cycle_typ pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_data_cycle_typb#define pyxis$v_mesr_seq_st pyxis$r_pyxis_mesr_overlay.pyxis$r_pyxis_mesr_bits.pyxis$v_mesr_seq_stK#define pyxis$l_pyxis_pcie0 pyxis$r_pyxis_pcie0_overlay.pyxis$l_pyxis_pcie0e#define pyxis$v_pcie_dma_cmd pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_dma_cmde#define pyxis$v_pcie_dma_dac pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxisG_pcie_bits.pyxis$v_pcie_dma_dacc#define pyxis$v_pcie_window pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_windowk#define pyxis$v_pcie_mstr_state pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_mstr_statek#define pyxis$v_pcie_trgt_state pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_trgt_statee#define pyxis$v_pcie_pci_cmd pyxis$r_pyxis_pcie0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_pci_cmde#define pyxis$v_pcie_pci_dac pyxis$r_pyxis_pciGe0_overlay.pyxis$r_pyxis_pcie_bits.pyxis$v_pcie_pci_dacU#define pyxis$l_pcie1_dma_addr_h pyxis$r_pyxis_pcie1_overlay.pyxis$l_pcie1_dma_addr_hU#define pyxis$l_pcie2_pci_addr_h pyxis$r_pyxis_pcie2_overlay.pyxis$l_pcie2_pci_addr_h?#define pyxis$l_mem_mcr pyxis$r_mem_mcr_overlay.pyxis$l_mem_mcr^#define pyxis$v_mcr_mode_req pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_mode_reqd#define pyxis$v_mcr_server_mode pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_server_moded#define Gpyxis$v_mcr_bcache_stat pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_bcache_stat`#define pyxis$v_mcr_bcache_en pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_bcache_enl#define pyxis$v_mcr_pipelined_cache pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_pipelined_cached#define pyxis$v_mcr_overlap_dis pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_overlap_dis`#define pyxis$v_mcr_seq_trace pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_seq_trace^#defGine pyxis$v_mcr_cke_auto pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_cke_autoh#define pyxis$v_mcr_dram_clk_auto pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_dram_clk_auto`#define pyxis$v_mcr_dram_mode pyxis$r_mem_mcr_overlay.pyxis$r_mem_mcr_bits.pyxis$v_mcr_dram_modeB#define pyxis$l_mem_mcmr pyxis$r_mem_mcmr_overlay.pyxis$l_mem_mcmrp#define pyxis$v_mcmr_dram_clock_mask pyxis$r_mem_mcmr_overlay.pyxis$r_mem_mcmr_data.pyxis$v_mcmr_dram_clock_maskB#define pyxis$l_mem_mgtr pyxGis$r_mem_mgtr_overlay.pyxis$l_mem_mgtrh#define pyxis$v_mgtr_min_ras_pre pyxis$r_mem_mgtr_overlay.pyxis$r_mem_mgtr_data.pyxis$v_mgtr_min_ras_pre`#define pyxis$v_mgtr_cas_lat pyxis$r_mem_mgtr_overlay.pyxis$r_mem_mgtr_data.pyxis$v_mgtr_cas_latl#define pyxis$v_mgtr_idle_bc_width pyxis$r_mem_mgtr_overlay.pyxis$r_mem_mgtr_data.pyxis$v_mgtr_idle_bc_widthB#define pyxis$l_mem_mrtr pyxis$r_mem_mrtr_overlay.pyxis$l_mem_mrtrd#define pyxis$v_mrtr_ref_width pyxis$r_mem_mrtr_overlay.pyxis$r_mem_mrtr_data.pyxis$Gv_mrtr_ref_width`#define pyxis$v_mrtr_ref_int pyxis$r_mem_mrtr_overlay.pyxis$r_mem_mrtr_data.pyxis$v_mrtr_ref_intd#define pyxis$v_mrtr_force_ref pyxis$r_mem_mrtr_overlay.pyxis$r_mem_mrtr_data.pyxis$v_mrtr_force_refE#define pyxis$l_mem_mrphr pyxis$r_mem_mrphr_overlay.pyxis$l_mem_mrphrl#define pyxis$v_mrphr_policy_mask pyxis$r_mem_mrphr_overlay.pyxis$r_mem_mrphr_data.pyxis$v_mrphr_policy_maskB#define pyxis$l_mem_mdr1 pyxis$r_mem_mdr1_overlay.pyxis$l_mem_mdr1Z#define pyxis$v_mdr1_sel0 pyxis$r_mem_Gmdr1_overlay.pyxis$r_mem_mdr1_data.pyxis$v_mdr1_sel0Z#define pyxis$v_mdr1_sel1 pyxis$r_mem_mdr1_overlay.pyxis$r_mem_mdr1_data.pyxis$v_mdr1_sel1Z#define pyxis$v_mdr1_sel2 pyxis$r_mem_mdr1_overlay.pyxis$r_mem_mdr1_data.pyxis$v_mdr1_sel2Z#define pyxis$v_mdr1_sel3 pyxis$r_mem_mdr1_overlay.pyxis$r_mem_mdr1_data.pyxis$v_mdr1_sel3^#define pyxis$v_mdr1_enable pyxis$r_mem_mdr1_overlay.pyxis$r_mem_mdr1_data.pyxis$v_mdr1_enableB#define pyxis$l_mem_mdr2 pyxis$r_mem_mdr2_overlay.pyxis$l_mem_mdr2Z#define pyxiGs$v_mdr2_sel0 pyxis$r_mem_mdr2_overlay.pyxis$r_mem_mdr2_data.pyxis$v_mdr2_sel0Z#define pyxis$v_mdr2_sel1 pyxis$r_mem_mdr2_overlay.pyxis$r_mem_mdr2_data.pyxis$v_mdr2_sel1Z#define pyxis$v_mdr2_sel2 pyxis$r_mem_mdr2_overlay.pyxis$r_mem_mdr2_data.pyxis$v_mdr2_sel2Z#define pyxis$v_mdr2_sel3 pyxis$r_mem_mdr2_overlay.pyxis$r_mem_mdr2_data.pyxis$v_mdr2_sel3^#define pyxis$v_mdr2_enable pyxis$r_mem_mdr2_overlay.pyxis$r_mem_mdr2_data.pyxis$v_mdr2_enableE#define pyxis$l_mem_bbar0 pyxis$r_mem_bbar0_overlay.pyGxis$l_mem_bbar0r#define pyxis$v_bbar0_base_addr_3324 pyxis$r_mem_bbar0_overlay.pyxis$r_mem_bbar0_data.pyxis$v_bbar0_base_addr_3324E#define pyxis$l_mem_bbar1 pyxis$r_mem_bbar1_overlay.pyxis$l_mem_bbar1r#define pyxis$v_bbar1_base_addr_3324 pyxis$r_mem_bbar1_overlay.pyxis$r_mem_bbar1_data.pyxis$v_bbar1_base_addr_3324E#define pyxis$l_mem_bbar2 pyxis$r_mem_bbar2_overlay.pyxis$l_mem_bbar2r#define pyxis$v_bbar2_base_addr_3324 pyxis$r_mem_bbar2_overlay.pyxis$r_mem_bbar2_data.pyxis$v_bbar2_base_addr_33G24E#define pyxis$l_mem_bbar3 pyxis$r_mem_bbar3_overlay.pyxis$l_mem_bbar3r#define pyxis$v_bbar3_base_addr_3324 pyxis$r_mem_bbar3_overlay.pyxis$r_mem_bbar3_data.pyxis$v_bbar3_base_addr_3324E#define pyxis$l_mem_bbar4 pyxis$r_mem_bbar4_overlay.pyxis$l_mem_bbar4r#define pyxis$v_bbar4_base_addr_3324 pyxis$r_mem_bbar4_overlay.pyxis$r_mem_bbar4_data.pyxis$v_bbar4_base_addr_3324E#define pyxis$l_mem_bbar5 pyxis$r_mem_bbar5_overlay.pyxis$l_mem_bbar5r#define pyxis$v_bbar5_base_addr_3324 pyxis$r_mem_bbar5G_overlay.pyxis$r_mem_bbar5_data.pyxis$v_bbar5_base_addr_3324E#define pyxis$l_mem_bbar6 pyxis$r_mem_bbar6_overlay.pyxis$l_mem_bbar6r#define pyxis$v_bbar6_base_addr_3324 pyxis$r_mem_bbar6_overlay.pyxis$r_mem_bbar6_data.pyxis$v_bbar6_base_addr_3324E#define pyxis$l_mem_bbar7 pyxis$r_mem_bbar7_overlay.pyxis$l_mem_bbar7r#define pyxis$v_bbar7_base_addr_3324 pyxis$r_mem_bbar7_overlay.pyxis$r_mem_bbar7_data.pyxis$v_bbar7_base_addr_3324E#define pyxis$l_mem_mbcr0 pyxis$r_mem_mbcr0_overlay.pyxis$l_mem_mbcrG0l#define pyxis$v_mbcr0_bank_enable pyxis$r_mem_mbcr0_overlay.pyxis$r_mem_mbcr0_data.pyxis$v_mbcr0_bank_enableh#define pyxis$v_mbcr0_bank_size pyxis$r_mem_mbcr0_overlay.pyxis$r_mem_mbcr0_data.pyxis$v_mbcr0_bank_sizer#define pyxis$v_mbcr0_subbank_enable pyxis$r_mem_mbcr0_overlay.pyxis$r_mem_mbcr0_data.pyxis$v_mbcr0_subbank_enableb#define pyxis$v_mbcr0_colsel pyxis$r_mem_mbcr0_overlay.pyxis$r_mem_mbcr0_data.pyxis$v_mbcr0_colsel`#define pyxis$v_mbcr0_4bank pyxis$r_mem_mbcr0_overlay.pyxis$r_mem_mbcrG0_data.pyxis$v_mbcr0_4bankE#define pyxis$l_mem_mbcr1 pyxis$r_mem_mbcr1_overlay.pyxis$l_mem_mbcr1l#define pyxis$v_mbcr1_bank_enable pyxis$r_mem_mbcr1_overlay.pyxis$r_mem_mbcr1_data.pyxis$v_mbcr1_bank_enableh#define pyxis$v_mbcr1_bank_size pyxis$r_mem_mbcr1_overlay.pyxis$r_mem_mbcr1_data.pyxis$v_mbcr1_bank_sizer#define pyxis$v_mbcr1_subbank_enable pyxis$r_mem_mbcr1_overlay.pyxis$r_mem_mbcr1_data.pyxis$v_mbcr1_subbank_enableb#define pyxis$v_mbcr1_colsel pyxis$r_mem_mbcr1_overlay.pyxis$r_mem_mbcr1_dGata.pyxis$v_mbcr1_colsel`#define pyxis$v_mbcr1_4bank pyxis$r_mem_mbcr1_overlay.pyxis$r_mem_mbcr1_data.pyxis$v_mbcr1_4bankE#define pyxis$l_mem_mbcr2 pyxis$r_mem_mbcr2_overlay.pyxis$l_mem_mbcr2l#define pyxis$v_mbcr2_bank_enable pyxis$r_mem_mbcr2_overlay.pyxis$r_mem_mbcr2_data.pyxis$v_mbcr2_bank_enableh#define pyxis$v_mbcr2_bank_size pyxis$r_mem_mbcr2_overlay.pyxis$r_mem_mbcr2_data.pyxis$v_mbcr2_bank_sizer#define pyxis$v_mbcr2_subbank_enable pyxis$r_mem_mbcr2_overlay.pyxis$r_mem_mbcr2_data.pyxis$v_Gmbcr2_subbank_enableb#define pyxis$v_mbcr2_colsel pyxis$r_mem_mbcr2_overlay.pyxis$r_mem_mbcr2_data.pyxis$v_mbcr2_colsel`#define pyxis$v_mbcr2_4bank pyxis$r_mem_mbcr2_overlay.pyxis$r_mem_mbcr2_data.pyxis$v_mbcr2_4bankE#define pyxis$l_mem_mbcr3 pyxis$r_mem_mbcr3_overlay.pyxis$l_mem_mbcr3l#define pyxis$v_mbcr3_bank_enable pyxis$r_mem_mbcr3_overlay.pyxis$r_mem_mbcr3_data.pyxis$v_mbcr3_bank_enableh#define pyxis$v_mbcr3_bank_size pyxis$r_mem_mbcr3_overlay.pyxis$r_mem_mbcr3_data.pyxis$v_mbcr3_bank_sizeGr#define pyxis$v_mbcr3_subbank_enable pyxis$r_mem_mbcr3_overlay.pyxis$r_mem_mbcr3_data.pyxis$v_mbcr3_subbank_enableb#define pyxis$v_mbcr3_colsel pyxis$r_mem_mbcr3_overlay.pyxis$r_mem_mbcr3_data.pyxis$v_mbcr3_colsel`#define pyxis$v_mbcr3_4bank pyxis$r_mem_mbcr3_overlay.pyxis$r_mem_mbcr3_data.pyxis$v_mbcr3_4bankE#define pyxis$l_mem_mbcr4 pyxis$r_mem_mbcr4_overlay.pyxis$l_mem_mbcr4l#define pyxis$v_mbcr4_bank_enable pyxis$r_mem_mbcr4_overlay.pyxis$r_mem_mbcr4_data.pyxis$v_mbcr4_bank_enableh#define Gpyxis$v_mbcr4_bank_size pyxis$r_mem_mbcr4_overlay.pyxis$r_mem_mbcr4_data.pyxis$v_mbcr4_bank_sizer#define pyxis$v_mbcr4_subbank_enable pyxis$r_mem_mbcr4_overlay.pyxis$r_mem_mbcr4_data.pyxis$v_mbcr4_subbank_enableb#define pyxis$v_mbcr4_colsel pyxis$r_mem_mbcr4_overlay.pyxis$r_mem_mbcr4_data.pyxis$v_mbcr4_colsel`#define pyxis$v_mbcr4_4bank pyxis$r_mem_mbcr4_overlay.pyxis$r_mem_mbcr4_data.pyxis$v_mbcr4_4bankE#define pyxis$l_mem_mbcr5 pyxis$r_mem_mbcr5_overlay.pyxis$l_mem_mbcr5l#define pyxis$v_mbcr5_Gbank_enable pyxis$r_mem_mbcr5_overlay.pyxis$r_mem_mbcr5_data.pyxis$v_mbcr5_bank_enableh#define pyxis$v_mbcr5_bank_size pyxis$r_mem_mbcr5_overlay.pyxis$r_mem_mbcr5_data.pyxis$v_mbcr5_bank_sizer#define pyxis$v_mbcr5_subbank_enable pyxis$r_mem_mbcr5_overlay.pyxis$r_mem_mbcr5_data.pyxis$v_mbcr5_subbank_enableb#define pyxis$v_mbcr5_colsel pyxis$r_mem_mbcr5_overlay.pyxis$r_mem_mbcr5_data.pyxis$v_mbcr5_colsel`#define pyxis$v_mbcr5_4bank pyxis$r_mem_mbcr5_overlay.pyxis$r_mem_mbcr5_data.pyxis$v_mbcr5_4bankGE#define pyxis$l_mem_mbcr6 pyxis$r_mem_mbcr6_overlay.pyxis$l_mem_mbcr6l#define pyxis$v_mbcr6_bank_enable pyxis$r_mem_mbcr6_overlay.pyxis$r_mem_mbcr6_data.pyxis$v_mbcr6_bank_enableh#define pyxis$v_mbcr6_bank_size pyxis$r_mem_mbcr6_overlay.pyxis$r_mem_mbcr6_data.pyxis$v_mbcr6_bank_sizer#define pyxis$v_mbcr6_subbank_enable pyxis$r_mem_mbcr6_overlay.pyxis$r_mem_mbcr6_data.pyxis$v_mbcr6_subbank_enableb#define pyxis$v_mbcr6_colsel pyxis$r_mem_mbcr6_overlay.pyxis$r_mem_mbcr6_data.pyxis$v_mbcr6_colsel`G#define pyxis$v_mbcr6_4bank pyxis$r_mem_mbcr6_overlay.pyxis$r_mem_mbcr6_data.pyxis$v_mbcr6_4bankE#define pyxis$l_mem_mbcr7 pyxis$r_mem_mbcr7_overlay.pyxis$l_mem_mbcr7l#define pyxis$v_mbcr7_bank_enable pyxis$r_mem_mbcr7_overlay.pyxis$r_mem_mbcr7_data.pyxis$v_mbcr7_bank_enableh#define pyxis$v_mbcr7_bank_size pyxis$r_mem_mbcr7_overlay.pyxis$r_mem_mbcr7_data.pyxis$v_mbcr7_bank_sizer#define pyxis$v_mbcr7_subbank_enable pyxis$r_mem_mbcr7_overlay.pyxis$r_mem_mbcr7_data.pyxis$v_mbcr7_subbank_enableb#defGine pyxis$v_mbcr7_colsel pyxis$r_mem_mbcr7_overlay.pyxis$r_mem_mbcr7_data.pyxis$v_mbcr7_colsel`#define pyxis$v_mbcr7_4bank pyxis$r_mem_mbcr7_overlay.pyxis$r_mem_mbcr7_data.pyxis$v_mbcr7_4bankE#define pyxis$l_mem_mbtr0 pyxis$r_mem_mbtr0_overlay.pyxis$l_mem_mbtr0p#define pyxis$v_mbtr0_row_addr_hold pyxis$r_mem_mbtr0_overlay.pyxis$r_mem_mbtr0_data.pyxis$v_mbtr0_row_addr_holdd#define pyxis$v_mbtr0_toshiba pyxis$r_mem_mbtr0_overlay.pyxis$r_mem_mbtr0_data.pyxis$v_mbtr0_toshibal#define pyxis$v_mbtr0_slGow_charge pyxis$r_mem_mbtr0_overlay.pyxis$r_mem_mbtr0_data.pyxis$v_mbtr0_slow_chargeE#define pyxis$l_mem_mbtr1 pyxis$r_mem_mbtr1_overlay.pyxis$l_mem_mbtr1p#define pyxis$v_mbtr1_row_addr_hold pyxis$r_mem_mbtr1_overlay.pyxis$r_mem_mbtr1_data.pyxis$v_mbtr1_row_addr_holdd#define pyxis$v_mbtr1_toshiba pyxis$r_mem_mbtr1_overlay.pyxis$r_mem_mbtr1_data.pyxis$v_mbtr1_toshibal#define pyxis$v_mbtr1_slow_charge pyxis$r_mem_mbtr1_overlay.pyxis$r_mem_mbtr1_data.pyxis$v_mbtr1_slow_chargeE#define pyxis$l_mem_mbGtr2 pyxis$r_mem_mbtr2_overlay.pyxis$l_mem_mbtr2p#define pyxis$v_mbtr2_row_addr_hold pyxis$r_mem_mbtr2_overlay.pyxis$r_mem_mbtr2_data.pyxis$v_mbtr2_row_addr_holdd#define pyxis$v_mbtr2_toshiba pyxis$r_mem_mbtr2_overlay.pyxis$r_mem_mbtr2_data.pyxis$v_mbtr2_toshibal#define pyxis$v_mbtr2_slow_charge pyxis$r_mem_mbtr2_overlay.pyxis$r_mem_mbtr2_data.pyxis$v_mbtr2_slow_chargeE#define pyxis$l_mem_mbtr3 pyxis$r_mem_mbtr3_overlay.pyxis$l_mem_mbtr3p#define pyxis$v_mbtr3_row_addr_hold pyxis$r_mem_mbtr3_overGlay.pyxis$r_mem_mbtr3_data.pyxis$v_mbtr3_row_addr_holdd#define pyxis$v_mbtr3_toshiba pyxis$r_mem_mbtr3_overlay.pyxis$r_mem_mbtr3_data.pyxis$v_mbtr3_toshibal#define pyxis$v_mbtr3_slow_charge pyxis$r_mem_mbtr3_overlay.pyxis$r_mem_mbtr3_data.pyxis$v_mbtr3_slow_chargeE#define pyxis$l_mem_mbtr4 pyxis$r_mem_mbtr4_overlay.pyxis$l_mem_mbtr4p#define pyxis$v_mbtr4_row_addr_hold pyxis$r_mem_mbtr4_overlay.pyxis$r_mem_mbtr4_data.pyxis$v_mbtr4_row_addr_holdd#define pyxis$v_mbtr4_toshiba pyxis$r_mem_mbtr4_overGlay.pyxis$r_mem_mbtr4_data.pyxis$v_mbtr4_toshibal#define pyxis$v_mbtr4_slow_charge pyxis$r_mem_mbtr4_overlay.pyxis$r_mem_mbtr4_data.pyxis$v_mbtr4_slow_chargeE#define pyxis$l_mem_mbtr5 pyxis$r_mem_mbtr5_overlay.pyxis$l_mem_mbtr5p#define pyxis$v_mbtr5_row_addr_hold pyxis$r_mem_mbtr5_overlay.pyxis$r_mem_mbtr5_data.pyxis$v_mbtr5_row_addr_holdd#define pyxis$v_mbtr5_toshiba pyxis$r_mem_mbtr5_overlay.pyxis$r_mem_mbtr5_data.pyxis$v_mbtr5_toshibal#define pyxis$v_mbtr5_slow_charge pyxis$r_mem_mbtr5_overlaGy.pyxis$r_mem_mbtr5_data.pyxis$v_mbtr5_slow_chargeE#define pyxis$l_mem_mbtr6 pyxis$r_mem_mbtr6_overlay.pyxis$l_mem_mbtr6p#define pyxis$v_mbtr6_row_addr_hold pyxis$r_mem_mbtr6_overlay.pyxis$r_mem_mbtr6_data.pyxis$v_mbtr6_row_addr_holdd#define pyxis$v_mbtr6_toshiba pyxis$r_mem_mbtr6_overlay.pyxis$r_mem_mbtr6_data.pyxis$v_mbtr6_toshibal#define pyxis$v_mbtr6_slow_charge pyxis$r_mem_mbtr6_overlay.pyxis$r_mem_mbtr6_data.pyxis$v_mbtr6_slow_chargeE#define pyxis$l_mem_mbtr7 pyxis$r_mem_mbtr7_overlay.pyxiGs$l_mem_mbtr7p#define pyxis$v_mbtr7_row_addr_hold pyxis$r_mem_mbtr7_overlay.pyxis$r_mem_mbtr7_data.pyxis$v_mbtr7_row_addr_holdd#define pyxis$v_mbtr7_toshiba pyxis$r_mem_mbtr7_overlay.pyxis$r_mem_mbtr7_data.pyxis$v_mbtr7_toshibal#define pyxis$v_mbtr7_slow_charge pyxis$r_mem_mbtr7_overlay.pyxis$r_mem_mbtr7_data.pyxis$v_mbtr7_slow_charge?#define pyxis$l_mem_cvm pyxis$r_mem_cvm_overlay.pyxis$l_mem_cvmn#define pyxis$v_cvm_cache_valid_mask pyxis$r_mem_cvm_overlay.pyxis$r_mem_cvm_data.pyxis$v_cvm_cachGe_valid_maskB#define pyxis$l_pci_tbia pyxis$r_pci_tbia_overlay.pyxis$l_pci_tbiah#define pyxis$v_tbia_csr_wr_data pyxis$r_pci_tbia_overlay.pyxis$r_pci_tbia_bits.pyxis$v_tbia_csr_wr_dataH#define pyxis$l_pci_wbase0 pyxis$r_pci_wbase0_overlay.pyxis$l_pci_wbase0b#define pyxis$v_wbase0_w_en pyxis$r_pci_wbase0_overlay.pyxis$r_pci_wbase0_bits.pyxis$v_wbase0_w_end#define pyxis$v_wbase0_sg_en pyxis$r_pci_wbase0_overlay.pyxis$r_pci_wbase0_bits.pyxis$v_wbase0_sg_enj#define pyxis$v_wbase0_memcs_en pyxis$r_pcGi_wbase0_overlay.pyxis$r_pci_wbase0_bits.pyxis$v_wbase0_memcs_enf#define pyxis$v_wbase0_dac_en pyxis$r_pci_wbase0_overlay.pyxis$r_pci_wbase0_bits.pyxis$v_wbase0_dac_enb#define pyxis$v_wbase0_base pyxis$r_pci_wbase0_overlay.pyxis$r_pci_wbase0_bits.pyxis$v_wbase0_baseH#define pyxis$l_pci_wmask0 pyxis$r_pci_wmask0_overlay.pyxis$l_pci_wmask0b#define pyxis$v_wmask0_mask pyxis$r_pci_wmask0_overlay.pyxis$r_pci_wmask0_bits.pyxis$v_wmask0_maskH#define pyxis$l_pci_tbase0 pyxis$r_pci_tbase0_overlay.pyxis$l_Gpci_tbase0b#define pyxis$v_tbase0_base pyxis$r_pci_tbase0_overlay.pyxis$r_pci_tbase0_bits.pyxis$v_tbase0_baseH#define pyxis$l_pci_wbase1 pyxis$r_pci_wbase1_overlay.pyxis$l_pci_wbase1b#define pyxis$v_wbase1_w_en pyxis$r_pci_wbase1_overlay.pyxis$r_pci_wbase1_bits.pyxis$v_wbase1_w_end#define pyxis$v_wbase1_sg_en pyxis$r_pci_wbase1_overlay.pyxis$r_pci_wbase1_bits.pyxis$v_wbase1_sg_enj#define pyxis$v_wbase1_memcs_en pyxis$r_pci_wbase1_overlay.pyxis$r_pci_wbase1_bits.pyxis$v_wbase1_memcs_enf#define pyGxis$v_wbase1_dac_en pyxis$r_pci_wbase1_overlay.pyxis$r_pci_wbase1_bits.pyxis$v_wbase1_dac_enb#define pyxis$v_wbase1_base pyxis$r_pci_wbase1_overlay.pyxis$r_pci_wbase1_bits.pyxis$v_wbase1_baseH#define pyxis$l_pci_wmask1 pyxis$r_pci_wmask1_overlay.pyxis$l_pci_wmask1b#define pyxis$v_wmask1_mask pyxis$r_pci_wmask1_overlay.pyxis$r_pci_wmask1_bits.pyxis$v_wmask1_maskH#define pyxis$l_pci_tbase1 pyxis$r_pci_tbase1_overlay.pyxis$l_pci_tbase1b#define pyxis$v_tbase1_base pyxis$r_pci_tbase1_overlay.pyxis$r_pGci_tbase1_bits.pyxis$v_tbase1_baseH#define pyxis$l_pci_wbase2 pyxis$r_pci_wbase2_overlay.pyxis$l_pci_wbase2b#define pyxis$v_wbase2_w_en pyxis$r_pci_wbase2_overlay.pyxis$r_pci_wbase2_bits.pyxis$v_wbase2_w_end#define pyxis$v_wbase2_sg_en pyxis$r_pci_wbase2_overlay.pyxis$r_pci_wbase2_bits.pyxis$v_wbase2_sg_enj#define pyxis$v_wbase2_memcs_en pyxis$r_pci_wbase2_overlay.pyxis$r_pci_wbase2_bits.pyxis$v_wbase2_memcs_enf#define pyxis$v_wbase2_dac_en pyxis$r_pci_wbase2_overlay.pyxis$r_pci_wbase2_bits.pyxisG$v_wbase2_dac_enb#define pyxis$v_wbase2_base pyxis$r_pci_wbase2_overlay.pyxis$r_pci_wbase2_bits.pyxis$v_wbase2_baseH#define pyxis$l_pci_wmask2 pyxis$r_pci_wmask2_overlay.pyxis$l_pci_wmask2b#define pyxis$v_wmask2_mask pyxis$r_pci_wmask2_overlay.pyxis$r_pci_wmask2_bits.pyxis$v_wmask2_maskH#define pyxis$l_pci_tbase2 pyxis$r_pci_tbase2_overlay.pyxis$l_pci_tbase2b#define pyxis$v_tbase2_base pyxis$r_pci_tbase2_overlay.pyxis$r_pci_tbase2_bits.pyxis$v_tbase2_baseH#define pyxis$l_pci_wbase3 pyxis$r_pci_wGbase3_overlay.pyxis$l_pci_wbase3b#define pyxis$v_wbase3_w_en pyxis$r_pci_wbase3_overlay.pyxis$r_pci_wbase3_bits.pyxis$v_wbase3_w_end#define pyxis$v_wbase3_sg_en pyxis$r_pci_wbase3_overlay.pyxis$r_pci_wbase3_bits.pyxis$v_wbase3_sg_enj#define pyxis$v_wbase3_memcs_en pyxis$r_pci_wbase3_overlay.pyxis$r_pci_wbase3_bits.pyxis$v_wbase3_memcs_enf#define pyxis$v_wbase3_dac_en pyxis$r_pci_wbase3_overlay.pyxis$r_pci_wbase3_bits.pyxis$v_wbase3_dac_enb#define pyxis$v_wbase3_base pyxis$r_pci_wbase3_overlay.pyxGis$r_pci_wbase3_bits.pyxis$v_wbase3_baseH#define pyxis$l_pci_wmask3 pyxis$r_pci_wmask3_overlay.pyxis$l_pci_wmask3b#define pyxis$v_wmask3_mask pyxis$r_pci_wmask3_overlay.pyxis$r_pci_wmask3_bits.pyxis$v_wmask3_maskH#define pyxis$l_pci_tbase3 pyxis$r_pci_tbase3_overlay.pyxis$l_pci_tbase3b#define pyxis$v_tbase3_base pyxis$r_pci_tbase3_overlay.pyxis$r_pci_tbase3_bits.pyxis$v_tbase3_base?#define pyxis$l_pci_dac pyxis$r_pci_dac_overlay.pyxis$l_pci_dacV#define pyxis$v_dac_base pyxis$r_pci_dac_overlay.pGyxis$r_pci_dac_bits.pyxis$v_dac_baseB#define pyxis$l_pci_ltb0 pyxis$r_pci_ltb0_overlay.pyxis$l_pci_ltb0\#define pyxis$v_ltb0_valid pyxis$r_pci_ltb0_overlay.pyxis$r_pci_ltb0_bits.pyxis$v_ltb0_valid^#define pyxis$v_ltb0_locked pyxis$r_pci_ltb0_overlay.pyxis$r_pci_ltb0_bits.pyxis$v_ltb0_lockedX#define pyxis$v_ltb0_dac pyxis$r_pci_ltb0_overlay.pyxis$r_pci_ltb0_bits.pyxis$v_ltb0_dacX#define pyxis$v_ltb0_tag pyxis$r_pci_ltb0_overlay.pyxis$r_pci_ltb0_bits.pyxis$v_ltb0_tagB#define pyxis$l_pci_ltb1 pyxisG$r_pci_ltb1_overlay.pyxis$l_pci_ltb1\#define pyxis$v_ltb1_valid pyxis$r_pci_ltb1_overlay.pyxis$r_pci_ltb1_bits.pyxis$v_ltb1_valid^#define pyxis$v_ltb1_locked pyxis$r_pci_ltb1_overlay.pyxis$r_pci_ltb1_bits.pyxis$v_ltb1_lockedX#define pyxis$v_ltb1_dac pyxis$r_pci_ltb1_overlay.pyxis$r_pci_ltb1_bits.pyxis$v_ltb1_dacX#define pyxis$v_ltb1_tag pyxis$r_pci_ltb1_overlay.pyxis$r_pci_ltb1_bits.pyxis$v_ltb1_tagB#define pyxis$l_pci_ltb2 pyxis$r_pci_ltb2_overlay.pyxis$l_pci_ltb2\#define pyxis$v_ltb2_valid pyxGis$r_pci_ltb2_overlay.pyxis$r_pci_ltb2_bits.pyxis$v_ltb2_valid^#define pyxis$v_ltb2_locked pyxis$r_pci_ltb2_overlay.pyxis$r_pci_ltb2_bits.pyxis$v_ltb2_lockedX#define pyxis$v_ltb2_dac pyxis$r_pci_ltb2_overlay.pyxis$r_pci_ltb2_bits.pyxis$v_ltb2_dacX#define pyxis$v_ltb2_tag pyxis$r_pci_ltb2_overlay.pyxis$r_pci_ltb2_bits.pyxis$v_ltb2_tagB#define pyxis$l_pci_ltb3 pyxis$r_pci_ltb3_overlay.pyxis$l_pci_ltb3\#define pyxis$v_ltb3_valid pyxis$r_pci_ltb3_overlay.pyxis$r_pci_ltb3_bits.pyxis$v_ltb3_valid^#defGine pyxis$v_ltb3_locked pyxis$r_pci_ltb3_overlay.pyxis$r_pci_ltb3_bits.pyxis$v_ltb3_lockedX#define pyxis$v_ltb3_dac pyxis$r_pci_ltb3_overlay.pyxis$r_pci_ltb3_bits.pyxis$v_ltb3_dacX#define pyxis$v_ltb3_tag pyxis$r_pci_ltb3_overlay.pyxis$r_pci_ltb3_bits.pyxis$v_ltb3_tag?#define pyxis$l_pci_tb0 pyxis$r_pci_tb0_overlay.pyxis$l_pci_tb0X#define pyxis$v_tb0_valid pyxis$r_pci_tb0_overlay.pyxis$r_pci_tb0_bits.pyxis$v_tb0_validT#define pyxis$v_tb0_dac pyxis$r_pci_tb0_overlay.pyxis$r_pci_tb0_bits.pyxis$v_tGb0_dacT#define pyxis$v_tb0_tag pyxis$r_pci_tb0_overlay.pyxis$r_pci_tb0_bits.pyxis$v_tb0_tag?#define pyxis$l_pci_tb1 pyxis$r_pci_tb1_overlay.pyxis$l_pci_tb1X#define pyxis$v_tb1_valid pyxis$r_pci_tb1_overlay.pyxis$r_pci_tb1_bits.pyxis$v_tb1_validT#define pyxis$v_tb1_dac pyxis$r_pci_tb1_overlay.pyxis$r_pci_tb1_bits.pyxis$v_tb1_dacT#define pyxis$v_tb1_tag pyxis$r_pci_tb1_overlay.pyxis$r_pci_tb1_bits.pyxis$v_tb1_tag?#define pyxis$l_pci_tb2 pyxis$r_pci_tb2_overlay.pyxis$l_pci_tb2X#define pyxis$v_tbG2_valid pyxis$r_pci_tb2_overlay.pyxis$r_pci_tb2_bits.pyxis$v_tb2_validT#define pyxis$v_tb2_dac pyxis$r_pci_tb2_overlay.pyxis$r_pci_tb2_bits.pyxis$v_tb2_dacT#define pyxis$v_tb2_tag pyxis$r_pci_tb2_overlay.pyxis$r_pci_tb2_bits.pyxis$v_tb2_tag?#define pyxis$l_pci_tb3 pyxis$r_pci_tb3_overlay.pyxis$l_pci_tb3X#define pyxis$v_tb3_valid pyxis$r_pci_tb3_overlay.pyxis$r_pci_tb3_bits.pyxis$v_tb3_validT#define pyxis$v_tb3_dac pyxis$r_pci_tb3_overlay.pyxis$r_pci_tb3_bits.pyxis$v_tb3_dacT#define pyxis$v_tb3_Gtag pyxis$r_pci_tb3_overlay.pyxis$r_pci_tb3_bits.pyxis$v_tb3_tagQ#define pyxis$l_pci_tb0_page0 pyxis$r_pci_tb0_page0_overlay.pyxis$l_pci_tb0_page0p#define pyxis$v_tb0_page0_valid pyxis$r_pci_tb0_page0_overlay.pyxis$r_pci_tb0_page0_bits.pyxis$v_tb0_page0_validn#define pyxis$v_tb0_page0_addr pyxis$r_pci_tb0_page0_overlay.pyxis$r_pci_tb0_page0_bits.pyxis$v_tb0_page0_addrQ#define pyxis$l_pci_tb0_page1 pyxis$r_pci_tb0_page1_overlay.pyxis$l_pci_tb0_page1p#define pyxis$v_tb0_page1_valid pyxis$r_pci_tbG0_page1_overlay.pyxis$r_pci_tb0_page1_bits.pyxis$v_tb0_page1_validn#define pyxis$v_tb0_page1_addr pyxis$r_pci_tb0_page1_overlay.pyxis$r_pci_tb0_page1_bits.pyxis$v_tb0_page1_addrQ#define pyxis$l_pci_tb0_page2 pyxis$r_pci_tb0_page2_overlay.pyxis$l_pci_tb0_page2p#define pyxis$v_tb0_page2_valid pyxis$r_pci_tb0_page2_overlay.pyxis$r_pci_tb0_page2_bits.pyxis$v_tb0_page2_validn#define pyxis$v_tb0_page2_addr pyxis$r_pci_tb0_page2_overlay.pyxis$r_pci_tb0_page2_bits.pyxis$v_tb0_page2_addrQ#define pyxis$l_Gpci_tb0_page3 pyxis$r_pci_tb0_page3_overlay.pyxis$l_pci_tb0_page3p#define pyxis$v_tb0_page3_valid pyxis$r_pci_tb0_page3_overlay.pyxis$r_pci_tb0_page3_bits.pyxis$v_tb0_page3_validn#define pyxis$v_tb0_page3_addr pyxis$r_pci_tb0_page3_overlay.pyxis$r_pci_tb0_page3_bits.pyxis$v_tb0_page3_addrQ#define pyxis$l_pci_tb1_page0 pyxis$r_pci_tb1_page0_overlay.pyxis$l_pci_tb1_page0p#define pyxis$v_tb1_page0_valid pyxis$r_pci_tb1_page0_overlay.pyxis$r_pci_tb1_page0_bits.pyxis$v_tb1_page0_validn#define pyxis$Gv_tb1_page0_addr pyxis$r_pci_tb1_page0_overlay.pyxis$r_pci_tb1_page0_bits.pyxis$v_tb1_page0_addrQ#define pyxis$l_pci_tb1_page1 pyxis$r_pci_tb1_page1_overlay.pyxis$l_pci_tb1_page1p#define pyxis$v_tb1_page1_valid pyxis$r_pci_tb1_page1_overlay.pyxis$r_pci_tb1_page1_bits.pyxis$v_tb1_page1_validn#define pyxis$v_tb1_page1_addr pyxis$r_pci_tb1_page1_overlay.pyxis$r_pci_tb1_page1_bits.pyxis$v_tb1_page1_addrQ#define pyxis$l_pci_tb1_page2 pyxis$r_pci_tb1_page2_overlay.pyxis$l_pci_tb1_page2p#define pyxis$Gv_tb1_page2_valid pyxis$r_pci_tb1_page2_overlay.pyxis$r_pci_tb1_page2_bits.pyxis$v_tb1_page2_validn#define pyxis$v_tb1_page2_addr pyxis$r_pci_tb1_page2_overlay.pyxis$r_pci_tb1_page2_bits.pyxis$v_tb1_page2_addrQ#define pyxis$l_pci_tb1_page3 pyxis$r_pci_tb1_page3_overlay.pyxis$l_pci_tb1_page3p#define pyxis$v_tb1_page3_valid pyxis$r_pci_tb1_page3_overlay.pyxis$r_pci_tb1_page3_bits.pyxis$v_tb1_page3_validn#define pyxis$v_tb1_page3_addr pyxis$r_pci_tb1_page3_overlay.pyxis$r_pci_tb1_page3_bits.pyxis$v_Gtb1_page3_addrQ#define pyxis$l_pci_tb2_page0 pyxis$r_pci_tb2_page0_overlay.pyxis$l_pci_tb2_page0p#define pyxis$v_tb2_page0_valid pyxis$r_pci_tb2_page0_overlay.pyxis$r_pci_tb2_page0_bits.pyxis$v_tb2_page0_validn#define pyxis$v_tb2_page0_addr pyxis$r_pci_tb2_page0_overlay.pyxis$r_pci_tb2_page0_bits.pyxis$v_tb2_page0_addrQ#define pyxis$l_pci_tb2_page1 pyxis$r_pci_tb2_page1_overlay.pyxis$l_pci_tb2_page1p#define pyxis$v_tb2_page1_valid pyxis$r_pci_tb2_page1_overlay.pyxis$r_pci_tb2_page1_bits.pyxis$vG_tb2_page1_validn#define pyxis$v_tb2_page1_addr pyxis$r_pci_tb2_page1_overlay.pyxis$r_pci_tb2_page1_bits.pyxis$v_tb2_page1_addrQ#define pyxis$l_pci_tb2_page2 pyxis$r_pci_tb2_page2_overlay.pyxis$l_pci_tb2_page2p#define pyxis$v_tb2_page2_valid pyxis$r_pci_tb2_page2_overlay.pyxis$r_pci_tb2_page2_bits.pyxis$v_tb2_page2_validn#define pyxis$v_tb2_page2_addr pyxis$r_pci_tb2_page2_overlay.pyxis$r_pci_tb2_page2_bits.pyxis$v_tb2_page2_addrQ#define pyxis$l_pci_tb2_page3 pyxis$r_pci_tb2_page3_overlay.pyxis$Gl_pci_tb2_page3p#define pyxis$v_tb2_page3_valid pyxis$r_pci_tb2_page3_overlay.pyxis$r_pci_tb2_page3_bits.pyxis$v_tb2_page3_validn#define pyxis$v_tb2_page3_addr pyxis$r_pci_tb2_page3_overlay.pyxis$r_pci_tb2_page3_bits.pyxis$v_tb2_page3_addrQ#define pyxis$l_pci_tb3_page0 pyxis$r_pci_tb3_page0_overlay.pyxis$l_pci_tb3_page0p#define pyxis$v_tb3_page0_valid pyxis$r_pci_tb3_page0_overlay.pyxis$r_pci_tb3_page0_bits.pyxis$v_tb3_page0_validn#define pyxis$v_tb3_page0_addr pyxis$r_pci_tb3_page0_overlay.pyxGis$r_pci_tb3_page0_bits.pyxis$v_tb3_page0_addrQ#define pyxis$l_pci_tb3_page1 pyxis$r_pci_tb3_page1_overlay.pyxis$l_pci_tb3_page1p#define pyxis$v_tb3_page1_valid pyxis$r_pci_tb3_page1_overlay.pyxis$r_pci_tb3_page1_bits.pyxis$v_tb3_page1_validn#define pyxis$v_tb3_page1_addr pyxis$r_pci_tb3_page1_overlay.pyxis$r_pci_tb3_page1_bits.pyxis$v_tb3_page1_addrQ#define pyxis$l_pci_tb3_page2 pyxis$r_pci_tb3_page2_overlay.pyxis$l_pci_tb3_page2p#define pyxis$v_tb3_page2_valid pyxis$r_pci_tb3_page2_overlay.pyGxis$r_pci_tb3_page2_bits.pyxis$v_tb3_page2_validn#define pyxis$v_tb3_page2_addr pyxis$r_pci_tb3_page2_overlay.pyxis$r_pci_tb3_page2_bits.pyxis$v_tb3_page2_addrQ#define pyxis$l_pci_tb3_page3 pyxis$r_pci_tb3_page3_overlay.pyxis$l_pci_tb3_page3p#define pyxis$v_tb3_page3_valid pyxis$r_pci_tb3_page3_overlay.pyxis$r_pci_tb3_page3_bits.pyxis$v_tb3_page3_validn#define pyxis$v_tb3_page3_addr pyxis$r_pci_tb3_page3_overlay.pyxis$r_pci_tb3_page3_bits.pyxis$v_tb3_page3_addrQ#define pyxis$l_pci_tb4_page0 pyxiGs$r_pci_tb4_page0_overlay.pyxis$l_pci_tb4_page0p#define pyxis$v_tb4_page0_valid pyxis$r_pci_tb4_page0_overlay.pyxis$r_pci_tb4_page0_bits.pyxis$v_tb4_page0_validn#define pyxis$v_tb4_page0_addr pyxis$r_pci_tb4_page0_overlay.pyxis$r_pci_tb4_page0_bits.pyxis$v_tb4_page0_addrQ#define pyxis$l_pci_tb4_page1 pyxis$r_pci_tb4_page1_overlay.pyxis$l_pci_tb4_page1p#define pyxis$v_tb4_page1_valid pyxis$r_pci_tb4_page1_overlay.pyxis$r_pci_tb4_page1_bits.pyxis$v_tb4_page1_validn#define pyxis$v_tb4_page1_addr pGyxis$r_pci_tb4_page1_overlay.pyxis$r_pci_tb4_page1_bits.pyxis$v_tb4_page1_addrQ#define pyxis$l_pci_tb4_page2 pyxis$r_pci_tb4_page2_overlay.pyxis$l_pci_tb4_page2p#define pyxis$v_tb4_page2_valid pyxis$r_pci_tb4_page2_overlay.pyxis$r_pci_tb4_page2_bits.pyxis$v_tb4_page2_validn#define pyxis$v_tb4_page2_addr pyxis$r_pci_tb4_page2_overlay.pyxis$r_pci_tb4_page2_bits.pyxis$v_tb4_page2_addrQ#define pyxis$l_pci_tb4_page3 pyxis$r_pci_tb4_page3_overlay.pyxis$l_pci_tb4_page3p#define pyxis$v_tb4_page3_valid Gpyxis$r_pci_tb4_page3_overlay.pyxis$r_pci_tb4_page3_bits.pyxis$v_tb4_page3_validn#define pyxis$v_tb4_page3_addr pyxis$r_pci_tb4_page3_overlay.pyxis$r_pci_tb4_page3_bits.pyxis$v_tb4_page3_addrQ#define pyxis$l_pci_tb5_page0 pyxis$r_pci_tb5_page0_overlay.pyxis$l_pci_tb5_page0p#define pyxis$v_tb5_page0_valid pyxis$r_pci_tb5_page0_overlay.pyxis$r_pci_tb5_page0_bits.pyxis$v_tb5_page0_validn#define pyxis$v_tb5_page0_addr pyxis$r_pci_tb5_page0_overlay.pyxis$r_pci_tb5_page0_bits.pyxis$v_tb5_page0_addrQ#dGefine pyxis$l_pci_tb5_page1 pyxis$r_pci_tb5_page1_overlay.pyxis$l_pci_tb5_page1p#define pyxis$v_tb5_page1_valid pyxis$r_pci_tb5_page1_overlay.pyxis$r_pci_tb5_page1_bits.pyxis$v_tb5_page1_validn#define pyxis$v_tb5_page1_addr pyxis$r_pci_tb5_page1_overlay.pyxis$r_pci_tb5_page1_bits.pyxis$v_tb5_page1_addrQ#define pyxis$l_pci_tb5_page2 pyxis$r_pci_tb5_page2_overlay.pyxis$l_pci_tb5_page2p#define pyxis$v_tb5_page2_valid pyxis$r_pci_tb5_page2_overlay.pyxis$r_pci_tb5_page2_bits.pyxis$v_tb5_page2_validnG#define pyxis$v_tb5_page2_addr pyxis$r_pci_tb5_page2_overlay.pyxis$r_pci_tb5_page2_bits.pyxis$v_tb5_page2_addrQ#define pyxis$l_pci_tb5_page3 pyxis$r_pci_tb5_page3_overlay.pyxis$l_pci_tb5_page3p#define pyxis$v_tb5_page3_valid pyxis$r_pci_tb5_page3_overlay.pyxis$r_pci_tb5_page3_bits.pyxis$v_tb5_page3_validn#define pyxis$v_tb5_page3_addr pyxis$r_pci_tb5_page3_overlay.pyxis$r_pci_tb5_page3_bits.pyxis$v_tb5_page3_addrQ#define pyxis$l_pci_tb6_page0 pyxis$r_pci_tb6_page0_overlay.pyxis$l_pci_tb6_page0pG#define pyxis$v_tb6_page0_valid pyxis$r_pci_tb6_page0_overlay.pyxis$r_pci_tb6_page0_bits.pyxis$v_tb6_page0_validn#define pyxis$v_tb6_page0_addr pyxis$r_pci_tb6_page0_overlay.pyxis$r_pci_tb6_page0_bits.pyxis$v_tb6_page0_addrQ#define pyxis$l_pci_tb6_page1 pyxis$r_pci_tb6_page1_overlay.pyxis$l_pci_tb6_page1p#define pyxis$v_tb6_page1_valid pyxis$r_pci_tb6_page1_overlay.pyxis$r_pci_tb6_page1_bits.pyxis$v_tb6_page1_validn#define pyxis$v_tb6_page1_addr pyxis$r_pci_tb6_page1_overlay.pyxis$r_pci_tb6_page1G_bits.pyxis$v_tb6_page1_addrQ#define pyxis$l_pci_tb6_page2 pyxis$r_pci_tb6_page2_overlay.pyxis$l_pci_tb6_page2p#define pyxis$v_tb6_page2_valid pyxis$r_pci_tb6_page2_overlay.pyxis$r_pci_tb6_page2_bits.pyxis$v_tb6_page2_validn#define pyxis$v_tb6_page2_addr pyxis$r_pci_tb6_page2_overlay.pyxis$r_pci_tb6_page2_bits.pyxis$v_tb6_page2_addrQ#define pyxis$l_pci_tb6_page3 pyxis$r_pci_tb6_page3_overlay.pyxis$l_pci_tb6_page3p#define pyxis$v_tb6_page3_valid pyxis$r_pci_tb6_page3_overlay.pyxis$r_pci_tb6_pageG3_bits.pyxis$v_tb6_page3_validn#define pyxis$v_tb6_page3_addr pyxis$r_pci_tb6_page3_overlay.pyxis$r_pci_tb6_page3_bits.pyxis$v_tb6_page3_addrQ#define pyxis$l_pci_tb7_page0 pyxis$r_pci_tb7_page0_overlay.pyxis$l_pci_tb7_page0p#define pyxis$v_tb7_page0_valid pyxis$r_pci_tb7_page0_overlay.pyxis$r_pci_tb7_page0_bits.pyxis$v_tb7_page0_validn#define pyxis$v_tb7_page0_addr pyxis$r_pci_tb7_page0_overlay.pyxis$r_pci_tb7_page0_bits.pyxis$v_tb7_page0_addrQ#define pyxis$l_pci_tb7_page1 pyxis$r_pci_tb7_page1_Goverlay.pyxis$l_pci_tb7_page1p#define pyxis$v_tb7_page1_valid pyxis$r_pci_tb7_page1_overlay.pyxis$r_pci_tb7_page1_bits.pyxis$v_tb7_page1_validn#define pyxis$v_tb7_page1_addr pyxis$r_pci_tb7_page1_overlay.pyxis$r_pci_tb7_page1_bits.pyxis$v_tb7_page1_addrQ#define pyxis$l_pci_tb7_page2 pyxis$r_pci_tb7_page2_overlay.pyxis$l_pci_tb7_page2p#define pyxis$v_tb7_page2_valid pyxis$r_pci_tb7_page2_overlay.pyxis$r_pci_tb7_page2_bits.pyxis$v_tb7_page2_validn#define pyxis$v_tb7_page2_addr pyxis$r_pci_tb7_pagGe2_overlay.pyxis$r_pci_tb7_page2_bits.pyxis$v_tb7_page2_addrQ#define pyxis$l_pci_tb7_page3 pyxis$r_pci_tb7_page3_overlay.pyxis$l_pci_tb7_page3p#define pyxis$v_tb7_page3_valid pyxis$r_pci_tb7_page3_overlay.pyxis$r_pci_tb7_page3_bits.pyxis$v_tb7_page3_validn#define pyxis$v_tb7_page3_addr pyxis$r_pci_tb7_page3_overlay.pyxis$r_pci_tb7_page3_bits.pyxis$v_tb7_page3_addrN#define pyxis$l_clock_config pyxis$r_clock_config_overlay.pyxis$l_clock_configg#define pyxis$v_ccr_clock_divide pyxis$r_clock_config_Goverlay.pyxis$r_ccr_bits.pyxis$v_ccr_clock_dividee#define pyxis$v_ccr_pclk_divide pyxis$r_clock_config_overlay.pyxis$r_ccr_bits.pyxis$v_ccr_pclk_divide]#define pyxis$v_ccr_sel_cfg pyxis$r_clock_config_overlay.pyxis$r_ccr_bits.pyxis$v_ccr_sel_cfg_#define pyxis$v_ccr_dclk_inv pyxis$r_clock_config_overlay.pyxis$r_ccr_bits.pyxis$v_ccr_dclk_invc#define pyxis$v_ccr_dclk_force pyxis$r_clock_config_overlay.pyxis$r_ccr_bits.pyxis$v_ccr_dclk_forcec#define pyxis$v_ccr_dclk_delay pyxis$r_clock_config_ovGerlay.pyxis$r_ccr_bits.pyxis$v_ccr_dclk_delay9#define pyxis$l_reset pyxis$r_reset_overlay.pyxis$l_reset;#define pyxis$l_far_reg pyxis$r_far_overlay.pyxis$l_far_regN#define pyxis$v_far_heat pyxis$r_far_overlay.pyxis$r_far_bits.pyxis$v_far_heat;#define pyxis$l_fcr_reg pyxis$r_fcr_overlay.pyxis$l_fcr_regT#define pyxis$v_fcr_on_heat pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_on_heatR#define pyxis$v_fcr_sample pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_sampleX#define pyxis$v_fcr_off_Gdelay pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_off_delayX#define pyxis$v_fcr_force_fan pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_force_fan^#define pyxis$v_fcr_force_fan_hi pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_force_fan_hiR#define pyxis$v_fcr_fan_on pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_fan_onX#define pyxis$v_fcr_fan_on_hi pyxis$r_fcr_overlay.pyxis$r_fcr_bits.pyxis$v_fcr_fan_on_hi;#define pyxis$l_ftr_reg pyxis$r_ftr_overlay.pyxis$l_ftr_regR#define pyxis$v_ftGr_fan_on pyxis$r_ftr_overlay.pyxis$r_ftr_bits.pyxis$v_ftr_fan_onR#define pyxis$v_ftr_fan_hi pyxis$r_ftr_overlay.pyxis$r_ftr_bits.pyxis$v_ftr_fan_hiX#define pyxis$v_ftr_fan_hi_lo pyxis$r_ftr_overlay.pyxis$r_ftr_bits.pyxis$v_ftr_fan_hi_loT#define pyxis$v_ftr_fan_off pyxis$r_ftr_overlay.pyxis$r_ftr_bits.pyxis$v_ftr_fan_off;#define pyxis$l_pcr_reg pyxis$r_pcr_overlay.pyxis$l_pcr_regZ#define pyxis$v_pcr_power_down pyxis$r_pcr_overlay.pyxis$r_pcr_bits.pyxis$v_pcr_power_downV#define pyxis$v_pcr_abus_dGis pyxis$r_pcr_overlay.pyxis$r_pcr_bits.pyxis$v_pcr_abus_disV#define pyxis$v_pcr_iint_dis pyxis$r_pcr_overlay.pyxis$r_pcr_bits.pyxis$v_pcr_iint_disV#define pyxis$v_pcr_do_reset pyxis$r_pcr_overlay.pyxis$r_pcr_bits.pyxis$v_pcr_do_reset;#define pyxis$l_ptr_reg pyxis$r_ptr_overlay.pyxis$l_ptr_regX#define pyxis$v_ptr_pll_delay pyxis$r_ptr_overlay.pyxis$r_ptr_bits.pyxis$v_ptr_pll_delayX#define pyxis$v_ptr_off_delay pyxis$r_ptr_overlay.pyxis$r_ptr_bits.pyxis$v_ptr_off_delayh#define pyxis$v_ptr_reset_Gpulse_width pyxis$r_ptr_overlay.pyxis$r_ptr_bits.pyxis$v_ptr_reset_pulse_width^#define pyxis$v_ptr_min_off_time pyxis$r_ptr_overlay.pyxis$r_ptr_bits.pyxis$v_ptr_min_off_time;#define pyxis$l_psr_reg pyxis$r_psr_overlay.pyxis$l_psr_reg?#define pyxis$q_int_req pyxis$r_int_req_overlay.pyxis$q_int_req^#define pyxis$v_int_req_31_0 pyxis$r_int_req_overlay.pyxis$r_int_req_bits.pyxis$v_int_req_31_0`#define pyxis$v_int_req_61_32 pyxis$r_int_req_overlay.pyxis$r_int_req_bits.pyxis$v_int_req_61_32f#define Gpyxis$v_int_req_clk_pend pyxis$r_int_req_overlay.pyxis$r_int_req_bits.pyxis$v_int_req_clk_pendd#define pyxis$v_int_req_err_int pyxis$r_int_req_overlay.pyxis$r_int_req_bits.pyxis$v_int_req_err_intB#define pyxis$q_int_mask pyxis$r_int_mask_overlay.pyxis$q_int_maskb#define pyxis$v_int_mask_31_0 pyxis$r_int_mask_overlay.pyxis$r_int_mask_bits.pyxis$v_int_mask_31_0d#define pyxis$v_int_mask_61_32 pyxis$r_int_mask_overlay.pyxis$r_int_mask_bits.pyxis$v_int_mask_61_32B#define pyxis$l_int_hilo pyxis$r_int_hGilo_overlay.pyxis$l_int_hilob#define pyxis$v_int_hilo_byte pyxis$r_int_hilo_overlay.pyxis$r_int_hilo_bits.pyxis$v_int_hilo_byteE#define pyxis$l_int_route pyxis$r_int_route_overlay.pyxis$l_int_routeX#define pyxis$v_int_rte pyxis$r_int_route_overlay.pyxis$r_int_route_bits.pyxis$v_int_rteb#define pyxis$v_int_rte_fill pyxis$r_int_route_overlay.pyxis$r_int_route_bits.pyxis$v_int_rte_fillE#define pyxis$q_gpo_register pyxis$r_gpo_overlay.pyxis$q_gpo_registerH#define pyxis$l_int_config pyxis$r_int_conGfig_overlay.pyxis$l_int_configd#define pyxis$v_icnfg_clk_div pyxis$r_int_config_overlay.pyxis$r_int_cnfg_bits.pyxis$v_icnfg_clk_divd#define pyxis$v_icnfg_irq_cnt pyxis$r_int_config_overlay.pyxis$r_int_cnfg_bits.pyxis$v_icnfg_irq_cnt`#define pyxis$v_icnfg_fill1 pyxis$r_int_config_overlay.pyxis$r_int_cnfg_bits.pyxis$v_icnfg_fill1d#define pyxis$v_icnfg_irq_cfg pyxis$r_int_config_overlay.pyxis$r_int_cnfg_bits.pyxis$v_icnfg_irq_cfg`#define pyxis$v_icnfg_fill2 pyxis$r_int_config_overlay.pyxis$r_int_cnfGg_bits.pyxis$v_icnfg_fill2h#define pyxis$v_icnfg_drive_irq pyxis$r_int_config_overlay.pyxis$r_int_cnfg_bits.pyxis$v_icnfg_drive_irq]#define pyxis$q_real_time_counter pyxis$r_real_time_counter_overlay.pyxis$q_real_time_counterP#define pyxis$q_interrupt_timer pyxis$r_int_time_overlay.pyxis$q_interrupt_timerK#define pyxis$l_iic_control pyxis$r_iic_control_overlay.pyxis$l_iic_controle#define pyxis$v_iic_read_data pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_read_datac#define pyxiGs$v_iic_read_clk pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_read_clka#define pyxis$v_iic_data_en pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_data_en[#define pyxis$v_iic_data pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_data_#define pyxis$v_iic_clk_en pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_clk_enY#define pyxis$v_iic_clk pyxis$r_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_clk[#define pyxis$v_iic_fill pyxis$rG_iic_control_overlay.pyxis$r_iic_ctrl_bits.pyxis$v_iic_fillN#define pyxis$b_fraction_sec pyxis$r_fraction_sec_overlay.pyxis$b_fraction_sec\#define pyxis$v_sec_01 pyxis$r_fraction_sec_overlay.pyxis$r_fraction_sec_bits.pyxis$v_sec_01Z#define pyxis$v_sec_1 pyxis$r_fraction_sec_overlay.pyxis$r_fraction_sec_bits.pyxis$v_sec_1F#define pyxis$b_second_byte pyxis$r_second_overlay.pyxis$b_second_byteP#define pyxis$v_second pyxis$r_second_overlay.pyxis$r_second_bits.pyxis$v_secondP#define pyxis$v_sec_10 pGyxis$r_second_overlay.pyxis$r_second_bits.pyxis$v_sec_10F#define pyxis$b_minute_byte pyxis$r_minute_overlay.pyxis$b_minute_byteP#define pyxis$v_minute pyxis$r_minute_overlay.pyxis$r_minute_bits.pyxis$v_minuteP#define pyxis$v_min_10 pyxis$r_minute_overlay.pyxis$r_minute_bits.pyxis$v_min_10O#define pyxis$b_min_alarm_byte pyxis$r_min_alarm_overlay.pyxis$b_min_alarm_byte\#define pyxis$v_alarm_min pyxis$r_min_alarm_overlay.pyxis$r_min_alarm_bits.pyxis$v_alarm_minb#define pyxis$v_alarm_min_10 pyxis$rG_min_alarm_overlay.pyxis$r_min_alarm_bits.pyxis$v_alarm_min_10d#define pyxis$v_set_min_alarm pyxis$r_min_alarm_overlay.pyxis$r_min_alarm_bits.pyxis$v_set_min_alarm@#define pyxis$b_hour_byte pyxis$r_hour_overlay.pyxis$b_hour_byteH#define pyxis$v_hour pyxis$r_hour_overlay.pyxis$r_hour_bits.pyxis$v_hourN#define pyxis$v_hour_10 pyxis$r_hour_overlay.pyxis$r_hour_bits.pyxis$v_hour_10N#define pyxis$v_ap_10hr pyxis$r_hour_overlay.pyxis$r_hour_bits.pyxis$v_ap_10hrL#define pyxis$v_twelve pyxis$r_hour_overGlay.pyxis$r_hour_bits.pyxis$v_twelveR#define pyxis$b_hour_alarm_byte pyxis$r_hour_alarm_overlay.pyxis$b_hour_alarm_byte`#define pyxis$v_alarm_hour pyxis$r_hour_alarm_overlay.pyxis$r_hour_alarm_bits.pyxis$v_alarm_hourf#define pyxis$v_alarm_hour_10 pyxis$r_hour_alarm_overlay.pyxis$r_hour_alarm_bits.pyxis$v_alarm_hour_10f#define pyxis$v_alarm_ap_10hr pyxis$r_hour_alarm_overlay.pyxis$r_hour_alarm_bits.pyxis$v_alarm_ap_10hrd#define pyxis$v_alarm_twelve pyxis$r_hour_alarm_overlay.pyxis$r_hour_alarm_bitGs.pyxis$v_alarm_twelveh#define pyxis$v_set_hour_alarm pyxis$r_hour_alarm_overlay.pyxis$r_hour_alarm_bits.pyxis$v_set_hour_alarm=#define pyxis$b_day_byte pyxis$r_day_overlay.pyxis$b_day_byteD#define pyxis$v_day pyxis$r_day_overlay.pyxis$r_day_bits.pyxis$v_dayO#define pyxis$b_day_alarm_byte pyxis$r_day_alarm_overlay.pyxis$b_day_alarm_byte\#define pyxis$v_day_alarm pyxis$r_day_alarm_overlay.pyxis$r_day_alarm_bits.pyxis$v_day_alarmd#define pyxis$v_day_alarm_mbz pyxis$r_day_alarm_overlay.pyxis$r_daGy_alarm_bits.pyxis$v_day_alarm_mbzd#define pyxis$v_set_day_alarm pyxis$r_day_alarm_overlay.pyxis$r_day_alarm_bits.pyxis$v_set_day_alarm@#define pyxis$b_date_byte pyxis$r_date_overlay.pyxis$b_date_byteH#define pyxis$v_date pyxis$r_date_overlay.pyxis$r_date_bits.pyxis$v_dateN#define pyxis$v_date_10 pyxis$r_date_overlay.pyxis$r_date_bits.pyxis$v_date_10C#define pyxis$b_month_byte pyxis$r_month_overlay.pyxis$b_month_byteL#define pyxis$v_month pyxis$r_month_overlay.pyxis$r_month_bits.pyxis$v_monthRG#define pyxis$v_month_10 pyxis$r_month_overlay.pyxis$r_month_bits.pyxis$v_month_10T#define pyxis$v_month_mbz pyxis$r_month_overlay.pyxis$r_month_bits.pyxis$v_month_mbzJ#define pyxis$v_esqw pyxis$r_month_overlay.pyxis$r_month_bits.pyxis$v_esqwJ#define pyxis$v_eosc pyxis$r_month_overlay.pyxis$r_month_bits.pyxis$v_eosc@#define pyxis$b_year_byte pyxis$r_year_overlay.pyxis$b_year_byteH#define pyxis$v_year pyxis$r_year_overlay.pyxis$r_year_bits.pyxis$v_yearN#define pyxis$v_year_10 pyxis$r_year_overlayG.pyxis$r_year_bits.pyxis$v_year_10X#define pyxis$b_command_1286_byte pyxis$r_command_1286_overlay.pyxis$b_command_1286_byteV#define pyxis$v_tdf pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_tdfV#define pyxis$v_waf pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_wafV#define pyxis$v_tdm pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_tdmV#define pyxis$v_wam pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_wam\#define pyxis$v_pu_lvl pyxisG$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_pu_lvl\#define pyxis$v_ibh_lo pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_ibh_loX#define pyxis$v_ipsw pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_ipswT#define pyxis$v_te pyxis$r_command_1286_overlay.pyxis$r_command_1286_bits.pyxis$v_teK#define pyxis$b_wdog_c_byte pyxis$r_wdog_1286_c_overlay.pyxis$b_wdog_c_byte_#define pyxis$v_wdog_01_sec pyxis$r_wdog_1286_c_overlay.pyxis$r_wdog_c_bits.pyxis$v_wdog_01_Gsec]#define pyxis$v_wdog_1_sec pyxis$r_wdog_1286_c_overlay.pyxis$r_wdog_c_bits.pyxis$v_wdog_1_secK#define pyxis$b_wdog_d_byte pyxis$r_wdog_1286_d_overlay.pyxis$b_wdog_d_byteY#define pyxis$v_wdog_sec pyxis$r_wdog_1286_d_overlay.pyxis$r_wdog_d_bits.pyxis$v_wdog_sec]#define pyxis$v_wdog_10sec pyxis$r_wdog_1286_d_overlay.pyxis$r_wdog_d_bits.pyxis$v_wdog_10sec9#define pyxis$b_vdivr pyxis$r_vdivr_overlay.pyxis$b_vdivr9#define pyxis$b_v1isr pyxis$r_v1isr_overlay.pyxis$b_v1isr9#define pyxis$b_v2 Gisr pyxis$r_v2isr_overlay.pyxis$b_v2isr9#define pyxis$b_v3isr pyxis$r_v3isr_overlay.pyxis$b_v3isr9#define pyxis$b_vdier pyxis$r_vdier_overlay.pyxis$b_vdier9#define pyxis$b_v1ier pyxis$r_v1ier_overlay.pyxis$b_v1ier9#define pyxis$b_v2ier pyxis$r_v2ier_overlay.pyxis$b_v2ier9#define pyxis$b_v3ier pyxis$r_v3ier_overlay.pyxis$b_v3ier9#define pyxis$b_vmcsr pyxis$r_vmcsr_overlay.pyxis$b_vmcsr9#define pyxis$b_vacsr pyxis$r_vacsr_overlay.pyxis$b_vacsr6#define pyxis$b_bidr pyxis$r_bidr_overlay.py Gxis$b_bidr?#define pyxis$b_vsicsr0 pyxis$r_vsicsr0_overlay.pyxis$b_vsicsr0?#define pyxis$b_vsicsr1 pyxis$r_vsicsr1_overlay.pyxis$b_vsicsr1?#define pyxis$b_vsicsr2 pyxis$r_vsicsr2_overlay.pyxis$b_vsicsr2?#define pyxis$b_vsicsr3 pyxis$r_vsicsr3_overlay.pyxis$b_vsicsr3?#define pyxis$b_vsicsr4 pyxis$r_vsicsr4_overlay.pyxis$b_vsicsr4?#define pyxis$b_vsicsr5 pyxis$r_vsicsr5_overlay.pyxis$b_vsicsr5?#define pyxis$b_vsicsr6 pyxis$r_vsicsr6_overlay.pyxis$b_vsicsr6?#define pyxis$b_vsicsr9 pyxis$r_ Gvsicsr9_overlay.pyxis$b_vsicsr9?#define pyxis$b_vsicsra pyxis$r_vsicsra_overlay.pyxis$b_vsicsra?#define pyxis$b_vsicsrb pyxis$r_vsicsrb_overlay.pyxis$b_vsicsrb?#define pyxis$b_vsicsrc pyxis$r_vsicsrc_overlay.pyxis$b_vsicsrcB#define pyxis$b_vsicsr11 pyxis$r_vsicsr11_overlay.pyxis$b_vsicsr11B#define pyxis$b_vsicsr12 pyxis$r_vsicsr12_overlay.pyxis$b_vsicsr12B#define pyxis$b_vsicsr13 pyxis$r_vsicsr13_overlay.pyxis$b_vsicsr13B#define pyxis$b_vsicsr14 pyxis$r_vsicsr14_overlay.pyxis$b_vsicsr14B#d Gefine pyxis$b_vsicsr15 pyxis$r_vsicsr15_overlay.pyxis$b_vsicsr15B#define pyxis$b_vsicsr16 pyxis$r_vsicsr16_overlay.pyxis$b_vsicsr16B#define pyxis$b_vsicsr17 pyxis$r_vsicsr17_overlay.pyxis$b_vsicsr17"#endif /* #if !defined(__VAXC) */ N/* */N/* DS1287A register definitions */N/* */ c#if !defined(__NOBASGEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pyxis_ds1287a {#pragma __nomember_alignment/ unsigned char pyxis_ds1287a$b_fill1 [3584];, unsigned int pyxis_ds1287a$l_port_index;- unsigned char pyxis_ds1287a$b_fill2 [28];+ unsigned int pyxis_ds1287a$l_port_data;& char pyxis_ds1287a$b_fill_13_ [4]; } PYXIS_DS1287A; $#pragma __memberG_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PYXISDEF_LOADED */ ww`z[UM/***************************************************************************/M/** **/M/** HPE CONFGIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. TGhis software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************************************** G************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */E/* Source: 03-FEB-2005 10:55:55 $1$DGA8345:[LIB_H.SRC]PZDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $PZDEF ***/#ifndef __PZDEF_LOADED#define __PZDEF_LOADED 1 G#pragma __ Gnostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_paramGs ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Structure definition for the poolzone header */N/* G */  9#ifdef __cplusplus /* Define structure prototypes */struct _pz_page; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pz_zone {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size Gpragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pz_page *pzzon$q_zonepage_flink; /* flink to next poolzone */#else) unsigned __int64 pzzon$q_zonepage_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pz_page *pzzon$q_zonepage_blink; /* blink to previous poolzone G*/#else) unsigned __int64 pzzon$q_zonepage_blink;#endifP unsigned __int64 pzzon$q_packet_size; /* size of packets in this poolzone */N unsigned __int64 pzzon$q_pages; /* number of pages in this poolzone */N unsigned __int64 pzzon$q_max_pages; /* maximum number of pages allowed */N unsigned __int64 pzzon$q_free_count; /* free page count */N unsigned __int64 pzzon$q_hits; /* counts number of hits */N unsigned __int64 pzzon$q_misses; G/* count number of misses */R unsigned __int64 pzzon$q_expansions; /* count number of poolzone expansions */N unsigned __int64 pzzon$q_failures; /* count allocation failures */S unsigned __int64 pzzon$q_not1stpage; /* count allocation not from first page */N unsigned __int64 pzzon$q_empty_pages; /* count empty pages */ } PZ_ZONE;N/* */N/* Structure definition for the poolzone G page header */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pz_page {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And se Gt ptr size default to 64-bit pointers */N struct _pz_page *pzpag$q_zonepage_flink; /* flink to next poolzone page */#else) unsigned __int64 pzpag$q_zonepage_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */R struct _pz_page *pzpag$q_zonepage_blink; /* blink to previous poolzone page */#else) unsigned __int64 pzpag$q_zonepage_blink;#endifR#ifd Gef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *pzpag$q_freequeue_flink; /* flink to next free packet */#else* unsigned __int64 pzpag$q_freequeue_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *pzpag$q_ Gfreequeue_blink; /* blink to previous free packet */#else* unsigned __int64 pzpag$q_freequeue_blink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _pz_zone *pzpag$q_zone; /* pointer to poolzone */#else unsigned __int64 pzpag$q_zone;#endifU unsigned __int64 pzpag$q_packet_size; /* size of packets in this poolzone Gpage */Y unsigned __int64 pzpag$q_packet_count; /* total number of packets in poolzone page */N unsigned __int64 pzpag$q_free_count; /* free packet counter */N unsigned __int64 pzpag$q_hits; /* count number of hits */N unsigned __int64 pzpag$q_relinks; /* count number of page relinks */N unsigned __int64 pzpag$q_reserved1; /* reserved fields */N unsigned __int64 pzpag$q_reserved2; /* */N Gunsigned __int64 pzpag$q_reserved3; /* */N unsigned __int64 pzpag$q_reserved4; /* */N unsigned __int64 pzpag$q_reserved5; /* */N unsigned __int64 pzpag$q_reserved6; /* */Y unsigned __int64 pzpag$q_first_packet; /* address of first packet in poolzone page */ } PZ_PAGE;N/* */N/* G Structure definition for the poolzone region header */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pz_region {#pragma __nomember_alignmentN unsigned __int64 pzreg$q_fill_1; /* spare field */O unsigned sGhort int pzreg$w_size; /* size of poolzone region structure */N unsigned char pzreg$b_type; /* structure type */N unsigned char pzreg$b_subtype; /* structure subtype */N unsigned int pzreg$l_fill_2; /* spare field */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */X int (*pzreg$q_allo Gc_rtn)(); /* pointer to allocation routine for poolzone */#else$ unsigned __int64 pzreg$q_alloc_rtn;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Z int (*pzreg$q_dealloc_rtn)(); /* pointer to deallocation routine for poolzone */#else& unsigned __int64 pzreg$q_dealloc_rtn;#endifQ unsigned __int64 pzreg$q_zone_count; /* number of poolzoGnes in this region */N unsigned __int64 pzreg$q_fill_3; /* spare field */N unsigned __int64 pzreg$q_reserved_1; /* reserved fields */N unsigned __int64 pzreg$q_reserved_2; /* */N unsigned __int64 pzreg$q_reserved_3; /* */N unsigned __int64 pzreg$q_reserved_4; /* */N PZ_ZONE pzreg$r_zone [1]; /* embedded first poolzone */ G } PZ_REGION; N/* */N/* Poolzone Pointer Declarations */N/* */&#pragma __required_pointer_size __save&#pragma __required_pointer_size __longLtypedef PZ_ZONE *PZ_ZONE_PQ; /* long pointer to a poolzone structure */Ptypedef PZ_PAGE *PZ_PAGE_PQ; /* long pointer to a poolzone page structure */Utypede Gf PZ_REGION *PZ_REGION_PQ; /* long pointer to a poolzone region structure */)#pragma __required_pointer_size __restoreN/* */N/* Poolzone Routine Declarations */N/* */1#define exe$poolzone_create EXE$POOLZONE_CREATE *int exe$poolzone_create(__unknown_params);1#define exe$poolzone_expand EXE$POOLZOGNE_EXPAND *int exe$poolzone_expand(__unknown_params);/#define exe$poolzone_purge EXE$POOLZONE_PURGE )int exe$poolzone_purge(__unknown_params);5#define exe$poolzone_allocate EXE$POOLZONE_ALLOCATE ,int exe$poolzone_allocate(__unknown_params);9#define exe$poolzone_deallocate EXE$POOLZONE_DEALLOCATE .int exe$poolzone_deallocate(__unknown_params);-#define exe$pool_allocate EXE$POOL_ALLOCATE (int exe$pool_allocate(__unknown_params);1#define exe$pool_deallocate EXE$POGOL_DEALLOCATE *int exe$pool_deallocate(__unknown_params); $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __PZDEF_LOADED */ ww಴[UM/***************************************************************************/M/** G **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** G **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** G **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:10 by OpenVMS SDL V3.7 */F/* Source: 31-OCT-2009 05:22:35 $1$DGA8345:[LIB_H.SRC]RADDEF.SDL;1 *//********************************************************************************************************************************//*** MOD GULE $RADDEF ***/#ifndef __RADDEF_LOADED#define __RADDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdefG __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */g/*G RAD Database - Structure containing information about a particular Resource Affinity Domain (RAD) */V/* within a system. This structure also serves as the base for other structures */B/* which are defined for each RAD. */N/* */N/* */#define RAD$M_NO_MEMORY 0x1#define RAD$M_NO_POOL 0x2N#define RAD$C_MAX_RADS 32 G /* Maximum number of RADs possible */  9#ifdef __cplusplus /* Define structure prototypes */ struct _pcb; struct _kpb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rad {#pragma __nomember_alignmentd unsigned int rad$l_rad_id; /* The (0-based) RAD number represen Gted by this structure */ __union {! unsigned int rad$l_flags; __struct {N unsigned rad$v_no_memory : 1; /* indicator if Rad has no memory */N unsigned rad$v_no_pool : 1; /* indicator if Rad has no pool */N unsigned rad$v_reserved : 30; /* Reserved for future use */ } rad$r_flags_bits; } rad$r_flags_overlay;O unsigned short int rad$w_mbo; /* Part of 64-bit header. Must be 1 */N unsigned char Grad$b_type; /* DYN$C_MISC */N unsigned char rad$b_subtype; /* DYN$C_RAD */k int rad$l_cfg_hard_id; /* "Hard" id of CFG node corresponding to or containing this RAD */N/* can go here. */N unsigned __int64 rad$q_size; /* Size of structure in bytes */N/* End of 64-bit header */U unsigned _ G_int64 rad$q_cfg_handle; /* Handle to find node corresponding to or */N/* containing this RAD. */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rad$pq_cpu_cbb; /* Pointer to bitmask of CPUs or 0 */#else! unsigned __int64 rad$pq_cpu_cbb;#endifN unsigned __int64 rad$q_cpu_mask; /* B Gitmask if CBB ptr is 0 */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */^ void *rad$pq_distance_array; /* Pointer to an array of "distances" to other RADs */#else( unsigned __int64 rad$pq_distance_array;#endifN/* (Array length is RIH$L_MAX_RADS) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr siz Ge pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */R void *rad$pq_pfn_array; /* Pointer to an array of PFN begin/end */#else# unsigned __int64 rad$pq_pfn_array;#endifN/* pairs on this RAD. 0 if n/a. (Use shift values from RIH) */n __int64 rad$q_pfn_array_length; /* How many PA pairs in the above list (in Wildfire, it would be 1) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr siz Ge pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _pcb *rad$l_pcb_cache; /* The per-RAD PCB cache */N int rad$l_spare1; /* Fill to quadword boundary */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nome Gmber_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _kpb *rad$q_kpb_cache; /* The per-RAD KPB cache */#else" unsigned __int64 rad$q_kpb_cache;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32- Gbit pointers */#endif* struct _kpb *rad$ps_kpb_cache;( unsigned int rad$l_sequence;) } rad$r_lal_longwords_struct; } rad$r_cache_overlay;N __int64 rad$q_spare2; /* Extra space to debug with */ __int64 rad$q_spare3;N int rad$l_zeroed_list_count; /* Count of zeroed pages */N int rad$l_zero_list_hi_lim; /* Maxumum pages to zero for RAD */X int rad$l_base_rad_1; /* Best IL GM or CLM RAD to be used by this RAD */] int rad$l_base_rad_2; /* Next best ILM or CLM RAD to be used by this RAD */N/* Add new pointers or info here */ } RAD; #if !defined(__VAXC)3#define rad$l_flags rad$r_flags_overlay.rad$l_flagsL#define rad$v_no_memory rad$r_flags_overlay.rad$r_flags_bits.rad$v_no_memoryH#define rad$v_no_pool rad$r_flags_overlay.rad$r_flags_bits.rad$v_no_poolJ#define rad$v_reserved rad$r_flags_overlay.rad G$r_flags_bits.rad$v_reserved;#define rad$q_kpb_cache rad$r_cache_overlay.rad$q_kpb_cacheX#define rad$ps_kpb_cache rad$r_cache_overlay.rad$r_lal_longwords_struct.rad$ps_kpb_cacheT#define rad$l_sequence rad$r_cache_overlay.rad$r_lal_longwords_struct.rad$l_sequence"#endif /* #if !defined(__VAXC) */ N#define RAD$C_LENGTH 120 /* Length of RAD */ #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragm Ha __required_pointer_size __long /* Pointers are 64-bit */Ctypedef struct _rad *RAD_PQ; /* Pointer to a RAD structure. */Ptypedef struct _rad **RAD_PPQ; /* Pointer to a pointer to a RAD structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 RAD_PQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Hb#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RADDEF_LOADED */ ww([UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard EnterpHrise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is Hnot **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************************** H***************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 25-MAY-1993 14:19:41 $1$DGA8345:[LIB_H.SRC]RBFDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RBFDEF ***/#ifndef __RBFDEF_LOADED#define __RBFDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pHragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __structH#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Remote buffer as stored in dynamic memory */N/* */N/* This structure must Hbe identical to the above structure except */N/* for the header, which is the header for a buffered io buffer. */N/* */N/* */N/* Buffered io buffer header */N/* */N#define RBF$K_HEADERLEN 24 /*HEADER LENGTH H */N#define RBF$C_HEADERLEN 24 /*HEADER LENGTH */ typedef struct _rbfhdr {N void *rbf$l_msgdat; /* Address of message data */N void *rbf$l_usrbfr; /* User buffer address */N unsigned short int rbf$w_size; /* Size of structure */N unsigned char rbf$b_type; /* Type of structure, DYN$C_BUFIO */N unsigned char rbf$b_spare; /* Alignment H */N unsigned short int rbf$w_datsize; /* Data size */N unsigned short int rbf$w_opcode; /*OPERATION CODE */N unsigned short int rbf$w_mod; /*OPERATION CODE MODIFIERS */N unsigned int rbf$l_refid; /*REFERENCE ID */N unsigned short int rbf$w_unit; /*DEVICE UNIT NUMBER */U/* S SIZE,0,W /*SIZE OF MESSAGE (ACP/DRIVER USE O HNLY) */ } RBFHDR;N#define RBF$C_ATTN -1 /* ATTENTION */N#define RBF$C_END -2 /* I/O REQUEST COMPLETE */N#define RBF$C_LOG -3 /* ERROR LOG */N#define RBF$S_RBFDEF 48 /* Old size name - synonym */ typedef struct _rbf { RBFHDR rbf$r_rbfhdr;N/* */N/* End of header  H */N/* */N unsigned int rbf$l_param1; /*PARAMETER 1 */N unsigned int rbf$l_param2; /*PARAMETER 2 */N unsigned int rbf$l_param3; /*PARAMETER 3 */N unsigned int rbf$l_param4; /*PARAMETER 4 */N unsigned int rbf$l_param5; /*PARAMETER  H5 */N unsigned int rbf$l_param6; /*PARAMETER 6 */N/* */N/* RESPONSE FROM REMOTE PACKET DEFINITIONS */N/* */N/*RESPONSE PACKET OPCODES */ } RBF;N#define RBF$S_RBFDEF1 32 /* Old size name - synonym H */ typedef struct _rbf1 { RBFHDR rbf$r_rbfhdr;N unsigned __int64 rbf$q_status; /*END PACKET I/O STATUS */N/* */N/* TERMINAL SPECIFIC PARAMETER DEFINITIONS */N/* */N/* READ/WRITE REQUEST */ } RBF1;N#define RBF$S_RBFDEF2 33 H /* Old size name - synonym */ typedef struct _rbf2 { RBFHDR rbf$r_rbfhdr;N unsigned int rbf$l_tt_bcnt; /*BYTE COUNT */ __union {N unsigned int rbf$l_tt_carcon; /*WRITE CARRIAGE CONTROL */N unsigned int rbf$l_tt_timout; /*READ TIMEOUT */" } rbf$r_tt_carcon_overlay; __union {N char rbf$t_tt_wdata; /*WRITE DATA */N Hchar rbf$t_tt_term; /*BYTE OF SIZE + TERMINATOR MASK */N/*WORD OF SIZE + PROMPT STRING */N/* SET MODE/CHARACTERISTICS REQUEST */! } rbf$r_tt_wdata_overlay; } RBF2; #if !defined(__VAXC)?#define rbf$l_tt_carcon rbf$r_tt_carcon_overlay.rbf$l_tt_carcon?#define rbf$l_tt_timout rbf$r_tt_carcon_overlay.rbf$l_tt_timout<#define rbf$t_tt_wdata rbf$r_tt_wdata_overlay.rbf$t_tt_wdata:#def Hine rbf$t_tt_term rbf$r_tt_wdata_overlay.rbf$t_tt_term"#endif /* #if !defined(__VAXC) */ N#define RBF$S_RBFDEF3 48 /* Old size name - synonym */ typedef struct _rbf3 { RBFHDR rbf$r_rbfhdr; __union {N unsigned __int64 rbf$q_tt_char; /*CHARACTERISTICS */N unsigned int rbf$l_tt_astprm; /*AST PARAMETER */ } rbf$r_tt_char_overlay;N unsigned int rbf$l_tt_speed; /*LINE SPEED H */N unsigned int rbf$l_tt_fill; /*FILL SPECIFIER */N unsigned int rbf$l_tt_parity; /*PARITY FLAGS */N unsigned int rbf$l_tt_char2; /* Another longword of characters */N/* READ REQUEST END PACKET */ } RBF3; #if !defined(__VAXC)9#define rbf$q_tt_char rbf$r_tt_char_overlay.rbf$q_tt_char=#define rbf$l_tt_astprm rbf$r_tt_char_overlay.rbf$l_tt_astprm"#endif H/* #if !defined(__VAXC) */ N#define RBF$S_RBFDEF4 33 /* Old size name - synonym */ typedef struct _rbf4 { RBFHDR rbf$r_rbfhdr;N __int64 rbf$$_fill_1; /*I/O STATUS */N char rbf$t_tt_rdata; /*WORD OF SIZE + READ DATA */N/* SENSE MODE/CHARACTERISTICS END PACKET */ } RBF4;N#define RBF$S_RBFDEF5 44 /* Old size name - synonym */ ty Hpedef struct _rbf5 { RBFHDR rbf$r_rbfhdr;N __int64 rbf$$_fill_2; /*I/O STATUS */N unsigned __int64 rbf$q_tt_schar; /*SENSED CHARACTERISTICS */N unsigned int rbf$l_tt_schar2; /* Another longword of characters */N/* Broadcast message attention packet */ } RBF5;N#define RBF$C_TT_BRDNAME 16 /* Size of name field */N#define RBF$S_RBFDEF6 48 /* O Hld size name - synonym */ typedef struct _rbf6 { RBFHDR rbf$r_rbfhdr;N unsigned short int rbf$w_tt_brdtotsize; /* Total size of data */N unsigned short int rbf$w_tt_brdmsg; /* Message code */N unsigned short int rbf$w_tt_brdunit; /* Unit number */N char rbf$t_tt_brdname [16]; /* Device name as counted string */ __union {N unsigned short int rbf$w_tt_brdtxtsize; /* Count for message text */H __struct {" char rbf$$_fill_9 [2];#if defined(__VAXC)$ char rbf$t_tt_brdtext[];#elseW/* Warning: empty char[] member for rbf$t_tt_brdtext at end of structure not created */"#endif /* #if defined(__VAXC) */N/* Out of band attention packet */) } rbf$r_tt_brdtxtsize_fields;& } rbf$r_tt_brdtxtsize_overlay; } RBF6; #if !defined(__VAXC)K#define rbf$w_tt_brdtxtsize rbf$r_tt_brdtxtsize_ov Herlay.rbf$w_tt_brdtxtsize`#define rbf$t_tt_brdtext rbf$r_tt_brdtxtsize_overlay.rbf$r_tt_brdtxtsize_fields.rbf$t_tt_brdtext"#endif /* #if !defined(__VAXC) */ N#define RBF$C_TT_UNSOL 0 /*UNSOLICITED DATA */N#define RBF$C_TT_HANGUP 1 /*MODEM HANGUP */N#define RBF$C_TT_CTRLC 2 /*CONTROL/C */N#define RBF$C_TT_CTRLY 3 /*CONTROL/Y */N#define RBF$C_TT_STA HRTRCV 4 /* Start a receive to the net */N#define RBF$C_TT_BRDCST 5 /* Broadcast message for mailbox */N#define RBF$C_TT_OUTBAND 6 /* Out of band AST */N#define RBF$S_RBFDEF7 25 /* Old size name - synonym */ typedef struct _rbf7 { RBFHDR rbf$r_rbfhdr;N unsigned char rbf$b_tt_outband; /* Out of band character */N/* ATTENTION PACKET MODIFIERS H */ } RBF7; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RBFDEF_LOADED */ ww O[UM/***************************************************************************/M/** H **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/HM/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************H****************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */G/* Source: 15-NOV-2001 14:50:54 $1$DGA8345:[LIB_H.SRC]RBUNDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RBUNDEF ***/#ifndef __RBUNDEF_LOHADED#define __RBUNDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#definHe __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* RBUN - SCS Resource bundle H */N/* */N/* This structure contains a bundle of resources needed to do an I/O over */P/* a SCS port. There is a SCS port-independent resource portion that contains */N/* resources needed by all ports. There is also a port-dependent portion */N/* of the RBUN for port specific resources. */N/*- H */ Z#define RBUN$C_MAX_SIZE 65535 /* Maximum transfer supported by RBUNs is 64K-1 */I/* RBUN port extensions */W#define RBUN$C_NPORT_PAGES 9 /* An unaligned 64K transfer can require the */N/* mapping of up to 9 Alpha 8KB port pages */N#define RBUN$C_TYP1_ARR_SIZE 72 /* Size of Type 1 arrary given */N/* max transfer size  H */N#define RBUN$R_CRCTX 64 /* CRCTX for this bundle */#define RBUN$K_NPORT_LENGTH 208#define RBUN$C_NPORT_LENGTH 208#define RBUN$K_PEM_LENGTH 52#define RBUN$C_PEM_LENGTH 52  9#ifdef __cplusplus /* Define structure prototypes */ struct _bd; struct _pdt; struct _typ1; struct _vcrp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember !H_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rbun {#pragma __nomember_alignmentN struct _rbun *rbun$l_link; /* Singly linked list of RBUNs */N unsigned int rbun$l_reserved; /* Unused longword */N unsigned short int rbun$w_size; /* Size of RBUN in bytes */N unsigned char rbun$b_type; /* Structure Type for RBUN */N unsigned char rbun$b_subtype; /* Structure Subtype f"Hor RBUN */N unsigned int rbun$l_rspid; /* RSPID */N int (*rbun$l_rdte)(); /* RDT entry address for the RSPID */Q unsigned int rbun$l_rdt_seqnum; /* RDT sequence number for this RSPID */N int (*rbun$l_msg_buf)(); /* Message buffer */O unsigned int rbun$l_scs_credits; /* SCS credits sent to remote system */N struct _bd *rbun$l_bd_addr; /* Buffer descriptor */N #H struct _pdt *rbun$l_pdt; /* PDT of port this RBUN belongs to */N unsigned int rbun$l_reserved1; /* Unused */N unsigned int rbun$l_reserved2; /* Unused */  __union {U/* The Nport extension consists of two Type 1 pointer arrays big enough to support */T/* the maximum RBUN transfer size. The array is allocated twice as Type 1 arrays */\/* are not allowed to cross 8KB boundary. Note Type 1 arrays must be hex a$Hligned as well. */ __struct {l struct _typ1 *rbun$l_typ1_addr; /* Virtual address of the Type 1 pointer array in TYP1_ARRAYS */N unsigned int rbun$l_fill1; /* Keep quadword alignment */t unsigned __int64 rbun$q_typ1_phy_addr; /* Physical address of the Type 1 pointer array in TYP1_ARRAYS */ `/* NOTE: the following def for CRCTX assumes (CRCTX$K_LENGTH < RBUN$C_NPORT_PAGES*2*8) 96<144 */e/* this allows us to overlay a CRCTX structure when ma %Hp registers are used instead of TYP1 arrays. */U unsigned __int64 rbun$q_typ1_arrays [18]; /* Two Type 1 pointer arrays */% } rbun$r_nport_extension;I/* PEDRIVER extensions to RBUN */ __struct {& struct _vcrp *rbun$l_vcrp;# } rbun$r_pem_extension;! } rbun$r_rbun_extensions; } RBUN; #if !defined(__VAXC)W#define rbun$l_typ1_addr rbun$r_rbun_extensions.rbun$r_nport_extension.rbun$ &Hl_typ1_addrO#define rbun$l_fill1 rbun$r_rbun_extensions.rbun$r_nport_extension.rbun$l_fill1_#define rbun$q_typ1_phy_addr rbun$r_rbun_extensions.rbun$r_nport_extension.rbun$q_typ1_phy_addr[#define rbun$q_typ1_arrays rbun$r_rbun_extensions.rbun$r_nport_extension.rbun$q_typ1_arraysK#define rbun$l_vcrp rbun$r_rbun_extensions.rbun$r_pem_extension.rbun$l_vcrp"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr s'Hize pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RBUNDEF_LOADED */ ww@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed(H by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by V)HMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************** *H*****************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 24-MAY-1993 10:14:18 $1$DGA8345:[LIB_H.SRC]RCTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RCTDEF ***/#ifndef __RCTDEF_LOADED#define __RCTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __me+Hmber_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#e,Hndif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* RCT - Replacement and Caching Table sector !0 layout. */N/* The RCT is a structure residing on disks controlled by MSCP */Q/* -H speaking disk controllers. The RCT is maintained by the intelligent */Q/* controllers and the disk class driver. The disk class driver mainly */N/* gets involved in RCT manipulations during host initiated bad */N/* block replacement. */ #define RCT$M_WB 0x1#define RCT$M_FE 0x80#define RCT$M_BR 0x2000#define RCT$M_RP2 0x4000#define RCT$M_RP1 0x8000#define RCT$M_LBN 0xFFFFFFF#define RCT$M_CODE 0xF00 .H00000!#define RCT$M_NONPRIME 0x10000000"#define RCT$M_ALLOCATED 0x20000000!#define RCT$M_UNUSABLE 0x40000000#define RCT$M_NULL 0x80000000T#define RCT$K_EMPTY 0 /* Unallocated (empty) replacement block */R#define RCT$K_ALOCPRIME 2 /* Allocated replace blk - primary RBN */V#define RCT$K_ALOCNONP 3 /* Allocated replace blk - non-primary RBN */N#define RCT$K_UNUSABLE 4 /* Unusable replacement block */S#define RCT$K_ALTUNU /HSE 5 /* Alternate unusable replacement block */W#define RCT$K_NULL 8 /* Null entry - no corresponding RBN sector */N#define RCT$S_RCTDEF 44 /* Old size name - synonym */ typedef struct _rct {N unsigned __int64 rct$q_volser; /* Volume serial number */ __union {N unsigned short int rct$w_flags; /* Flags word */ __struct {N unsigned rct$v_wb : 1; /* W 0Hrite back caching in use */& unsigned rct$$_fill_1 : 6;Y unsigned rct$v_fe : 1; /* Forced Error flag for block being replaced */& unsigned rct$$_fill_2 : 5;N unsigned rct$v_br : 1; /* Replacement caused by Bad RBN */N unsigned rct$v_rp2 : 1; /* Replacement in Progress phase 2 */N unsigned rct$v_rp1 : 1; /* Replacement in Progress phase 1 */ } rct$r_flags_bits; } rct$r_flags_ov1Herlay;N short int rct$$_fill_3; /* Reserved word */N unsigned int rct$l_lbn; /* LBN curently being replaced. */N unsigned int rct$l_rbn; /* RBN allocated to replace LBN */W unsigned int rct$l_bad_rbn; /* If BR flag, RBN of bad replacement block */[ unsigned __int64 rct$q_wb_ctrl; /* Serial ! of last controller doing Write back */N unsigned int rct$l_wb_incar; /* Write back incarnation ! 2H */ __union {\ unsigned __int64 rct$q_incartime; /* Date-time of last update of incarnation no. */N/* */N/* Structure of a Replacement Block Descriptor */N/* */ __struct {Q unsigned rct$v_lbn : 28; /* Space for LBN replaced by this RBN */W unsigned rct$v_code : 4; /* D3Hescribes how this descriptor being used */$ } rct$r_incartime_bits0; __struct {N unsigned rct$$_fill_4 : 28; /* LBN */X unsigned rct$v_nonprime : 1; /* Set implies allocated, but not prime RBN */N unsigned rct$v_allocated : 1; /* This RBN allocated */N unsigned rct$v_unusable : 1; /* This RBN unusable */N unsigned rct$v_null : 1; /* This marks a NULL entry 4H */$ } rct$r_incartime_bits1;N/* Values of CODE */" } rct$r_incartime_overlay; } RCT; #if !defined(__VAXC)3#define rct$w_flags rct$r_flags_overlay.rct$w_flags>#define rct$v_wb rct$r_flags_overlay.rct$r_flags_bits.rct$v_wb>#define rct$v_fe rct$r_flags_overlay.rct$r_flags_bits.rct$v_fe>#define rct$v_br rct$r_flags_overlay.rct$r_flags_bits.rct$v_br@#define rct$v_rp2 rct$r_flags_overlay.rct$r_flags_bits.rct5H$v_rp2@#define rct$v_rp1 rct$r_flags_overlay.rct$r_flags_bits.rct$v_rp1?#define rct$q_incartime rct$r_incartime_overlay.rct$q_incartimeI#define rct$v_lbn rct$r_incartime_overlay.rct$r_incartime_bits0.rct$v_lbnK#define rct$v_code rct$r_incartime_overlay.rct$r_incartime_bits0.rct$v_codeS#define rct$v_nonprime rct$r_incartime_overlay.rct$r_incartime_bits1.rct$v_nonprimeU#define rct$v_allocated rct$r_incartime_overlay.rct$r_incartime_bits1.rct$v_allocatedS#define rct$v_unusable rct$r_incartime6H_overlay.rct$r_incartime_bits1.rct$v_unusableK#define rct$v_null rct$r_incartime_overlay.rct$r_incartime_bits1.rct$v_null"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RCTDEF_LOADED */ ww7H`[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Cop8Hyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. 9H **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */G/* Source: 20-APR-1993 15:11:23 $1$DGA8345:[LIB_H.SRC]RDABDEF.SDL;1 *//*********************************** :H*********************************************************************************************//*** MODULE $RDABDEF ***/#ifndef __RDABDEF_LOADED#define __RDABDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragm;Ha __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_unioHdefault : 1; /* RADB created as default */( unsigned rdab$v_fill_2_ : 4; } rdab$r_fill_1_; } rdab$r_fill_0_;N unsigned int rdab$l_acmode; /* access mode (RSDM_ID) */N unsigned int rdab$l_dom_acmode; /* domain access mode */ } RDAB; #if !defined(__VAXC)2#define rdab$l_access rdab$r_fill_0_.rdab$l_accessC#define rdab$v_default rdab$r_fill_0_.rdab$r_fill_1_.rdab$v_default"#endif /* #if !defined(__VAXC?H) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RDABDEF_LOADED */ ww9[UM/***************************************************************************/M/** @H **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS AHSOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********************************BH******************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:12 by OpenVMS SDL V3.7 */G/* Source: 21-APR-1993 10:51:39 $1$DGA8345:[LIB_H.SRC]RDDBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RDDBDEF ***/#ifndef __RDDBDEF_LOADED#def CHine __RDDBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknowDHn_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define RDDB$M_KEEP 0x1#define RDDB$M_NO_PROFILE 0x2N#define RDDB$K_LENGTH 36 /* Length of RDDB EH */N#define RDDB$C_LENGTH 36 /* Length of RDDB */#define RDDB$S_RDDBDEF 36  9#ifdef __cplusplus /* Define structure prototypes */ struct _orb; #endif /* #ifdef __cplusplus */ typedef struct _rddb {N struct _rddb *rddb$l_flink; /* RDDB queue forward link */N struct _rddb *rddb$l_blink; /* RDDB queue backward link */N unsigned int rddb$l_size; /* Size in bytes */N un FHsigned int rddb$l_type; /* Structure type code for RDDB */ __union {" unsigned int rddb$l_flags; __struct {N unsigned rddb$v_keep : 1; /* Domain block is deallocated if */N/* refcnt goes to 0 and KEEP not set */N/* KEEP is set on successful access. */S unsigned rddb$v_no_profile : 1; /* Domain profile being instantiated */( unsigned rddb$v_fill GH_2_ : 6; } rddb$r_fill_1_; } rddb$r_fill_0_;N unsigned int rddb$l_group; /* domain number */N struct _orb *rddb$l_orb; /* Pointer to the ORB */N unsigned int rddb$l_lockid; /* Lock id value (MAC) */N unsigned int rddb$l_refcnt; /* Count of RDs + root locks */ } RDDB; #if !defined(__VAXC)0#define rddb$l_flags rddb$r_fill_0_.rddb$l_flags=#define rddb$v_keep rddb$rHH_fill_0_.rddb$r_fill_1_.rddb$v_keepI#define rddb$v_no_profile rddb$r_fill_0_.rddb$r_fill_1_.rddb$v_no_profile"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RDDBDEF_LOADED */ ww[UIHM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright HewJHlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. KH **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:14 by OpenVMS SDL V3.7 */E/* Source: 26-APR-1993 15:40:30 $1$DGA8345:[LIB_H.SRC]RDDEF.SDL;1 *//*********************************************** LH*********************************************************************************//*** MODULE $RDDEF ***/#ifndef __RDDEF_LOADED#define __RDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointMHer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif NH N/*+ */N/* RD - SCS RESPONSE DESCRIPTOR FORMAT */N/*- */ N#define RD$K_LENGTH 8 /*LENGTH OF RD */N#define RD$C_LENGTH 8 /*LENGTH OF RD */#define RD$S_RDDEF 8  9#ifdef __cplusplus /* Define structure prototypes */ struct OH _rd; #endif /* #ifdef __cplusplus */ typedef struct _scs_rd { __union {N void *rd$l_cdrp; /*ADDR OF ASSOC CDRP OR */N/* OR OTHER CONTEXT BLOCK */N struct _rd *rd$l_link; /* OR LINK TO NEXT FREE RD */ } rd$r_cdrp_overlay; __union {N unsigned short int rd$w_state; /*RD STATE FLAGS */ __struct {N unsigned rd$v_busy PH : 1; /* ALLOCATED IF SET */N unsigned rd$v_perm : 1; /* PERMANENTLY ALLOCATED RD IF SET */& unsigned rd$v_fill_0_ : 6; } rd$r_state_bits; } rd$r_state_overlay;N unsigned short int rd$w_seqnum; /*SEQUENCE NUMBER OF RD */ } SCS_RD; #if !defined(__VAXC)-#define rd$l_cdrp rd$r_cdrp_overlay.rd$l_cdrp-#define rd$l_link rd$r_cdrp_overlay.rd$l_link0#define rd$w_state rd$r_state_overlay.rd$w_state>#defQHine rd$v_busy rd$r_state_overlay.rd$r_state_bits.rd$v_busy>#define rd$v_perm rd$r_state_overlay.rd$r_state_bits.rd$v_perm"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RDDEF_LOADED */ wwRH[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 CopyrSHight Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. TH **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:14 by OpenVMS SDL V3.7 */F/* Source: 27-JUN-1996 13:56:09 $1$DGA8345:[LIB_H.SRC]RDEDEF.SDL;1 *//*************************************** UH*****************************************************************************************//*** MODULE $RDEDEF ***/#ifndef __RDEDEF_LOADED#define __RDEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __reVHquired_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#e WHndif#endif N/* */N/* Region Descriptor Definitions. The region descriptor entry contains */N/* memory management data for a region of virtual address space. */N/* */</* *** WARNING *** */N/* Region Descriptor Entries are embedded into the PHD. Any modification */N/* to this definition fileXH may cause an update in PHDDEF.SDL as well. */</* *************** */ #define REGPRT$M_OWNER_MODE 0xF!#define REGPRT$M_CREATE_MODE 0xF0.#define REGPRT$M_RESERVED_PROT_BITS 0xFFFFFF00 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef union _region_prot {#pragma __nomember_alignment int regprt YH$l_region_prot; __struct {N unsigned regprt$v_owner_mode : 4; /* Region owner mode */N unsigned regprt$v_create_mode : 4; /* Region create mode */2 unsigned regprt$v_reserved_prot_bits : 24;! } regprt$r_region_fields; } REGION_PROT; #if !defined(__VAXC)F#define regprt$v_owner_mode regprt$r_region_fields.regprt$v_owner_modeH#define regprt$v_create_mode regprt$r_region_fields.regprt$v_create_modeV#define regprt$v_reserved_protZH_bits regprt$r_region_fields.regprt$v_reserved_prot_bits"#endif /* #if !defined(__VAXC) */ #define RDE$M_DESCEND 0x1#define RDE$M_P0_SPACE 0x2#define RDE$M_P1_SPACE 0x4#define RDE$M_PERMANENT 0x8##define RDE$M_EXPAND_ON_ACCVIO 0x10#define RDE$M_NO_CLONE 0x20#define RDE$M_SHARED_PTS 0x40'#define RDE$M_RESERVED_FLAGS 0xFFFFFF80N#define RDE$C_LENGTH 56 /* Length of RDE */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* I [Hf using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rde {#pragma __nomember_alignmentN struct _rde *rde$ps_va_list_flink; /* Flink for VA list of RDEs */N struct _rde *rde$ps_va_list_blink; /* Blink for VA list of RDEs */N unsigned short int rde$w_size; /* Structure size (including RDE) */N unsigned char rde$b_type; /* Dynamic structure type */N unsign\Hed char rde$b_subtype; /* Dynamic structore subtype */N struct _rde *rde$ps_table_link; /* Pointer to next RDE in table */ __union {N unsigned int rde$l_flags; /* FLAGS longword */ __struct {N unsigned rde$v_descend : 1; /* Region is descending */N unsigned rde$v_p0_space : 1; /* Region is in P0 space */N unsigned rde$v_p1_space : 1; /* Region is in P1 space */]HN unsigned rde$v_permanent : 1; /* Region is permanent */U unsigned rde$v_expand_on_accvio : 1; /* Expand within region on accvio */N unsigned rde$v_no_clone : 1; /* Do not clone this region */N unsigned rde$v_shared_pts : 1; /* Region is a shared PT region *// unsigned rde$v_reserved_flags : 25; } rde$r_flags_bits; } rde$r_flags_overlay;N REGION_PROT rde$r_regprot; /* Region protection ^H */N unsigned __int64 rde$q_region_id; /* Id of region */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rde$pq_start_va; /* Lowest address in region */#else" unsigned __int64 rde$pq_start_va;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */ _H[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *rde$ps_start_va; /* Lowest address in 32-bit region */ } rde$r_start_va_union; __union {N unsigned __int64 rde$q_region_size; /* Size of region */N unsigned int rde$l_region_size; /* Size of 32-bit region */" } rde$r_region_size_union; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr siz `He pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rde$pq_first_free_va; /* First free VA in region */#else' unsigned __int64 rde$pq_first_free_va;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *rde$ps_first_free_va; /* First free VA in 32-bit aH region */ } rde$r_free_va_union; } RDE; #if !defined(__VAXC)3#define rde$l_flags rde$r_flags_overlay.rde$l_flagsH#define rde$v_descend rde$r_flags_overlay.rde$r_flags_bits.rde$v_descendJ#define rde$v_p0_space rde$r_flags_overlay.rde$r_flags_bits.rde$v_p0_spaceJ#define rde$v_p1_space rde$r_flags_overlay.rde$r_flags_bits.rde$v_p1_spaceL#define rde$v_permanent rde$r_flags_overlay.rde$r_flags_bits.rde$v_permanentZ#define rde$v_expand_on_accvio rde$r_flags_overlay.rde$r_flags_bbHits.rde$v_expand_on_accvioJ#define rde$v_no_clone rde$r_flags_overlay.rde$r_flags_bits.rde$v_no_cloneN#define rde$v_shared_pts rde$r_flags_overlay.rde$r_flags_bits.rde$v_shared_ptsV#define rde$v_reserved_flags rde$r_flags_overlay.rde$r_flags_bits.rde$v_reserved_flags<#define rde$pq_start_va rde$r_start_va_union.rde$pq_start_va<#define rde$ps_start_va rde$r_start_va_union.rde$ps_start_vaC#define rde$q_region_size rde$r_region_size_union.rde$q_region_sizeC#define rde$l_region_size rde$r_region_s cHize_union.rde$l_region_sizeE#define rde$pq_first_free_va rde$r_free_va_union.rde$pq_first_free_vaE#define rde$ps_first_free_va rde$r_free_va_union.rde$ps_first_free_va"#endif /* #if !defined(__VAXC) */ X#define RDE$C_MIN_USER_ID 16 /* Minimum region id for user defined regions */T#define RDE$C_REGION_TABLE_SIZE 16 /* Number of list headers in region table */N/* Internal functions values for $lookup_rde_va function */#define __LOOKUP_RDE_EXACT 0#defindHe __LOOKUP_RDE_HIGHER 1 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RDEDEF_LOADED */ ww[UM/***************************************************************************/M/** eH **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** fH**/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*******************gH********************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:15 by OpenVMS SDL V3.7 */F/* Source: 22-APR-1993 13:47:28 $1$DGA8345:[LIB_H.SRC]RDIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RDIDEF ***/#ifndef __RDIDEF_LOAhHDED#define __RDIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#definiHe __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */O/* Rights Database Identifier Block defijHnitions: This structure contains the */N/* RMS Internal File Identifiers (IFI's) and Internal Stream Identifiers */N/* (ISI's) for the rights database. This structure is allocated from the */N/* process allocation region pool. */N/*-- */Y#define RDI$K_ISI_MAX 10 /* Maximum number of concurrent record streams */#define RDI$M_READ_CHECK 0x1#define RDI$M_READ_ACC kHESS 0x2#define RDI$S_RDIDEF 64 typedef struct _rdi {N unsigned int rdi$l_size; /* Size of allocated block */Z unsigned int rdi$l_ifi_read; /* Internal File Identifier for read operations */[ unsigned int rdi$l_ifi_write; /* Internal File Identifier for write operations */Q unsigned int rdi$l_read_channel; /* Holds channel used for reading RDB. */ __union {N unsigned int rdi$l_flags; /* Flags longword lH*/ __struct {N unsigned rdi$v_read_check : 1; /* Set if read access checked */U unsigned rdi$v_read_access : 1; /* Set if there is read access to RDB */' unsigned rdi$v_fill_0_ : 6; } rdi$r_flags_bits; } rdi$r_flags_overlay;O unsigned int rdi$l_isi_vec [11]; /* Internal Stream Identifier vector */ } RDI; #if !defined(__VAXC)3#define rdi$l_flags rdi$r_flags_overlay.rdi$l_flagsN#define rdi$v_read_check rdi$rnH_flags_overlay.rdi$r_flags_bits.rdi$v_read_checkP#define rdi$v_read_access rdi$r_flags_overlay.rdi$r_flags_bits.rdi$v_read_access"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RDIDEF_LOADED */ wweHRBFDEFHhRBUNDEF&HRCTDEF5HRDABDEF>H^RDDBDEFGHRDDEFPHRDEDEFcHlRDIDEFlHRDPBDEFvHFRDPDEFHRDTDEFHnRGBDEFHRHDRDEFH RIGHTSDEFHJRIHDEFHRJRDEFIRMDDEFIRMMGTDEFI  RMSEDTDEFI RNDBITDEFIRRDEFJRSBDEF+J@RSCDEF6JbRSNDEF@JRVTDEFLJr S0PAGINGDEFSJ SASDEVDEFuJSBDEFJLSBNBDEFJNSBODEFJ. SCAMGTDEFJPSCBDEFJSCDRPDEF SCH_ROUTINES. SCS_ROUTINESoHJ[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 20pH24 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software,qH Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:17 by OpenVMS SDL V3.7 */G/* Source: 10-MAY-1993 09:24:40 $1$DGA8345:[LIB_H.SRC]RDPBDEF.SDL;1 *//***************************** rH***************************************************************************************************//*** MODULE $RDPBDEF ***/#ifndef __RDPBDEF_LOADED#define __RDPBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[sH#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variantHt_union#endif#endif N#define RDPB$K_LENGTH 172 /* Length of RDPB */N#define RDPB$C_LENGTH 172 /* Length of RDPB */N#define RDPB$C_NUM 6 /* # of RDABs/RDPB */#define RDPB$S_RDPBDEF 172  9#ifdef __cplusplus /* Define structure prototypes */ struct _rdab; #endif /* #ifdef __cplusplus */ typedef struct _rdpb {N struct _rdpb *rdpb$l_flink; /* RDPB queue forward uHlink */N struct _rdpb *rdpb$l_blink; /* RDPB queue backward link */N unsigned short int rdpb$w_size; /* Size in bytes */N unsigned char rdpb$b_type; /* Structure type code for RDPB */N unsigned char rdpb$b_fill_1; /* alignment filler */N unsigned int rdpb$l_num; /* Number of RDABs per RDPB */T struct _rdab *rdpb$l_default_rdab; /* address of RDAB for default domain */N vH unsigned int rdpb$l_default_domain; /* domain number for default domain */N unsigned int rdpb$l_default_id; /* RDAB index for default domain */N/*+ */N/* Next 24*6 bytes are for the 6 RDAB fields contained in the RDPB */N/*- */N struct _rdab *rdpb$l_rdab [36]; /* space for 6 RDABs */ } RDPB; $#pragma __wHmember_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RDPBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPxHE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTyHIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/********************************************************* zH******************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:18 by OpenVMS SDL V3.7 */F/* Source: 24-MAY-1993 10:29:06 $1$DGA8345:[LIB_H.SRC]RDPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RDPDEF ***/#ifndef __RDPDEF_LOADED#define __RDPDEF_LOADED 1 G {H#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __opti|Honal_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* REMOTE DEVICE PROTOCOL DEFINITIONS */}HN/* */N#define RDP$K_HEADERLEN 10 /*HEADER LENGTH */N#define RDP$C_HEADERLEN 10 /*HEADER LENGTH */ typedef struct _rdphdr {N unsigned short int rdp$w_opcode; /*OPERATION CODE */N unsigned short int rdp$w_mod; /*OPERATION CODE MODIFIERS */N unsigned int rdp$l_refid; /*REFERENCE ID ~H */ __union {N unsigned short int rdp$w_unit; /*DEVICE UNIT NUMBER */S unsigned short int rdp$w_size; /*SIZE OF MESSAGE (ACP/DRIVER USE ONLY) */ } rdp$r_unit_overlay; } RDPHDR; #if !defined(__VAXC)0#define rdp$w_unit rdp$r_unit_overlay.rdp$w_unit0#define rdp$w_size rdp$r_unit_overlay.rdp$w_size"#endif /* #if !defined(__VAXC) */ N#define RDP$C_ATTN -1 /* ATTENTION */N#define RDP$C_END -2 H /* I/O REQUEST COMPLETE */N#define RDP$C_LOG -3 /* ERROR LOG */N#define RDP$S_RDPDEF 34 /* Old size name - synonym */ typedef struct _rdp { RDPHDR rdp$r_rdphdr;N unsigned int rdp$l_param1; /*PARAMETER 1 */N unsigned int rdp$l_param2; /*PARAMETER 2 */N unsigned int rdp$l_param3; /*PARAMETER 3 H*/N unsigned int rdp$l_param4; /*PARAMETER 4 */N unsigned int rdp$l_param5; /*PARAMETER 5 */N unsigned int rdp$l_param6; /*PARAMETER 6 */N/* */N/* RESPONSE FROM REMOTE PACKET DEFINITIONS */N/* */N/*RESPONSE PACKET OPCO HDES */ } RDP;N#define RDP$S_RDPDEF1 18 /* Old size name - synonym */ typedef struct _rdp1 { RDPHDR rdp$r_rdphdr;N unsigned __int64 rdp$q_status; /*END PACKET I/O STATUS */N/* */N/* TERMINAL SPECIFIC PARAMETER DEFINITIONS */N/* H */N/* READ/WRITE REQUEST */ } RDP1;N#define RDP$S_RDPDEF2 19 /* Old size name - synonym */ typedef struct _rdp2 { RDPHDR rdp$r_rdphdr;N unsigned int rdp$l_tt_bcnt; /*BYTE COUNT */ __union {N unsigned int rdp$l_tt_carcon; /*WRITE CARRIAGE CONTROL */N unsigned int rdp$l_tt_timout; /*READ TIMEOUT */" H } rdp$r_tt_carcon_overlay; __union {N char rdp$t_tt_wdata; /*WRITE DATA */N char rdp$t_tt_term; /*BYTE OF SIZE + TERMINATOR MASK */N/*WORD OF SIZE + PROMPT STRING */N/* SET MODE/CHARACTERISTICS REQUEST */! } rdp$r_tt_wdata_overlay; } RDP2; #if !defined(__VAXC)?#define rdp$l_tt_carcon rdp$r_tt_carcon_overlay.rdp$l_tt_carco Hn?#define rdp$l_tt_timout rdp$r_tt_carcon_overlay.rdp$l_tt_timout<#define rdp$t_tt_wdata rdp$r_tt_wdata_overlay.rdp$t_tt_wdata:#define rdp$t_tt_term rdp$r_tt_wdata_overlay.rdp$t_tt_term"#endif /* #if !defined(__VAXC) */ N#define RDP$S_RDPDEF3 34 /* Old size name - synonym */ typedef struct _rdp3 { RDPHDR rdp$r_rdphdr; __union {N unsigned __int64 rdp$q_tt_char; /*CHARACTERISTICS */N unsigned int rdp$l_tt_astprm; /*AS HT PARAMETER */ } rdp$r_tt_char_overlay;N unsigned int rdp$l_tt_speed; /*LINE SPEED */N unsigned int rdp$l_tt_fill; /*FILL SPECIFIER */N unsigned int rdp$l_tt_parity; /*PARITY FLAGS */O unsigned int rdp$l_tt_char2; /* Remaining longword of characters */N/* READ REQUEST END PACKET */ } RDP3; #if !defined(__V HAXC)9#define rdp$q_tt_char rdp$r_tt_char_overlay.rdp$q_tt_char=#define rdp$l_tt_astprm rdp$r_tt_char_overlay.rdp$l_tt_astprm"#endif /* #if !defined(__VAXC) */ N#define RDP$S_RDPDEF4 19 /* Old size name - synonym */ typedef struct _rdp4 { RDPHDR rdp$r_rdphdr;N __int64 rdp$$_fill_1; /*I/O STATUS */N char rdp$t_tt_rdata; /*WORD OF SIZE + READ DATA */N/* SENSE MODE/CHARACTERISTICS END PACKET H */ } RDP4;N#define RDP$S_RDPDEF5 30 /* Old size name - synonym */ typedef struct _rdp5 { RDPHDR rdp$r_rdphdr;N __int64 rdp$$_fill_2; /*I/O STATUS */N unsigned __int64 rdp$q_tt_schar; /*SENSED CHARACTERISTICS */P unsigned int rdp$l_tt_schar2; /* Additional longword of characters */N/* Broadcast message attention packet */ H } RDP5;N#define RDP$C_TT_BRDNAME 16 /* Size of name field */N#define RDP$S_RDPDEF6 34 /* Old size name - synonym */ typedef struct _rdp6 { RDPHDR rdp$r_rdphdr;N unsigned short int rdp$w_tt_brdtotsize; /* Total size of data */N unsigned short int rdp$w_tt_brdmsg; /* Message code */N unsigned short int rdp$w_tt_brdunit; /* Unit number */N char rdp$t_tt_brdname [16]; H /* Device name as counted string */ __union {N unsigned short int rdp$w_tt_brdtxtsize; /* Count for message text */ __struct {" char rdp$$_fill_9 [2];#if defined(__VAXC)$ char rdp$t_tt_brdtext[];#elseW/* Warning: empty char[] member for rdp$t_tt_brdtext at end of structure not created */"#endif /* #if defined(__VAXC) */N/* Out of band attention packet */) } rdp$r_tt_brdtxtsize_ Hfields;& } rdp$r_tt_brdtxtsize_overlay; } RDP6; #if !defined(__VAXC)K#define rdp$w_tt_brdtxtsize rdp$r_tt_brdtxtsize_overlay.rdp$w_tt_brdtxtsize`#define rdp$t_tt_brdtext rdp$r_tt_brdtxtsize_overlay.rdp$r_tt_brdtxtsize_fields.rdp$t_tt_brdtext"#endif /* #if !defined(__VAXC) */ N#define RDP$C_TT_UNSOL 0 /*UNSOLICITED DATA */N#define RDP$C_TT_HANGUP 1 /*MODEM HANGUP */N#define RDP$C_TT_CTRLC 2 H/*CONTROL/C */N#define RDP$C_TT_CTRLY 3 /*CONTROL/Y */N#define RDP$C_TT_STARTRCV 4 /* Start a receive to the net */N#define RDP$C_TT_BRDCST 5 /* Broadcast message for mailbox */N#define RDP$C_TT_OUTBAND 6 /* Out of band AST */N#define RDP$S_RDPDEF7 11 /* Old size name - synonym */ typedef struct _rdp7 { RDPHDR rdp$r_rdphdr;N unsignedH char rdp$b_tt_outband; /* Out of band character */N/* ATTENTION PACKET MODIFIERS */ } RDP7; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RDPDEF_LOADED */ ww0H[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 CopyrigHht Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. H **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:18 by OpenVMS SDL V3.7 */F/* Source: 22-JUL-1999 15:25:35 $1$DGA8345:[LIB_H.SRC]RDTDEF.SDL;1 *//***************************************** H***************************************************************************************//*** MODULE $RDTDEF ***/#ifndef __RDTDEF_LOADED#define __RDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __requHired_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#end Hif#endif N/*+ */N/* RDT - SCS RESPONSE DESCRIPTOR TABLE */N/* */N/* ONE RESPONSE DESCRIPTOR (RD) IS ALLOCATED FOR EACH SCS MESSAGE */N/* SENT FOR WHICH THE SENDER EXPECTS A MATCHING RESPONSE. */N/*- */ P#defin He RDT$C_LENGTH 40 /*LENGTH OF NEG PORTION OF STRUCTURE */N/* */#define RDT$S_RDTDEF 41 @typedef struct _rdt { /* WARNING: aggregate has origin of -40 */D /* WARNING: aggregate element "rdt$b_scs_maint_block" ignored *// /* WARNING: aggregate element "" ignored */; /* WARNING: aggregate element "rdt$l_waitfl" ignored */; /* WARNING: aggregate element "rdt$l_waitbl" ignored */9 /* WAR HNING: aggregate element "rdt$w_size" ignored */9 /* WARNING: aggregate element "rdt$b_type" ignored */; /* WARNING: aggregate element "rdt$b_subtyp" ignored */; /* WARNING: aggregate element "rdt$l_freerd" ignored */= /* WARNING: aggregate element "rdt$l_maxrdidx" ignored */= /* WARNING: aggregate element "rdt$l_qrdt_cnt" ignored */ char rdtdef$$_fill_2; } RDT;#define CRDT$S_CRDTDEF 40 typedef struct _crdt {V unsigned char crdt$b_scs_maint_block [16]; /H*Add a Maintenance block to the CDT */N/* which must be quadword aligned */N void *crdt$l_waitfl; /*RD WAIT QUEUE FWD LINK */N void *crdt$l_waitbl; /*RD WAIT QUEUE BACK LINK */N unsigned short int crdt$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char crdt$b_type; /*SCS STURCTURE TYPE */N unsigned char crdt$b_subtyp; /*SCS STRUCT SUBTYPE FOR R HDT */N void *crdt$l_freerd; /*ADDR OF 1ST FREE RD */N unsigned int crdt$l_maxrdidx; /*MAXIMUM ! OF DESCRIPTORS */X unsigned int crdt$l_qrdt_cnt; /*Count of stalls because of no response ID's */ } CRDT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#eHndif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RDTDEF_LOADED */ ww@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone wHithout the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the Hprior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:18 by OpenVMS SDL V3.7 */ HF/* Source: 19-APR-1993 14:51:25 $1$DGA8345:[LIB_H.SRC]RGBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RGBDEF ***/#ifndef __RGBDEF_LOADED#define __RGBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporHted */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endHif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* RGB - Range Block */N/* */N/* Range Block is a user defined structure passed by reference to the Lock */R/* Manager $enq, $enqw and $deq system system servicesH via the optional [RANGE] */N/* argument. */P/* The Range Block specifies a relative start and length of a resource range */N/* to be locked, converted or unlocked. */N/*- */N#define RGB$C_LENGTH 16 /*LENGTH OF FIXED PART */N#define RGB$K_LENGTH 16 /*LENGTH OF FIXED PART H */N#define RGB$K_MAXRANGE -1 /*Maximum range of resource */#define RGB$S_RGBDEF 16 typedef struct _rgb {N unsigned __int64 rgb$q_start; /* relative start of range to lock */N unsigned __int64 rgb$q_length; /* length of range to lock */ } RGB; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previouslHy-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RGBDEF_LOADED */ wwP5[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, dHuplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to Hanyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:2 H3:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RHDRDEF ***/#ifndef __RHDRDEF_LOADED#define __RHDRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* DeHfined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define H__struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* Receive buffer header definition. This structure is used by the driver */N/* to fake out the I/O system when the user passes a P5 parameter on a READ */O/* QIO. It will appear as a diagnostic buffer to the I/O system and is used */N/* to return tHhe P5 data to the user. */N/*-- */N#define RHDR$T_DATA_AP 12 /* Start of data (addresses etc..) */N#define RHDR$B_DSAP 24 /* 802 DSAP */N#define RHDR$B_SSAP 25 /* 802 SSAP */N#define RHDR$C_LENGTH_ETH 26 /* Length of ETH structure */#define RHDR$C_DATA_ETH 14N/* Size of EHTH data */N#define RHDR$G_PID 27 /* Protocol Id follows 1-byte CTL */N#define RHDR$C_LENGTH_802 28 /* Length of 802 structure */#define RHDR$C_DATA_802 16N/* Size of 802 data */N#define RHDR$C_LENGTH_802E 32 /* Length of 802E structure */#define RHDR$C_DATA_802E 20N/* Size of 802E data H */ typedef struct _rhdrdef {N unsigned int rhdr$l_data; /* Pointer to start of data */N unsigned int rhdr$l_buffer; /* User buffer address */N unsigned short int rhdr$w_size; /* Size of structure */N unsigned char rhdr$b_type; /* Type of structure */N unsigned char rhdr$b_spare; /* Spare byte */N unsigned short int rhdr$g_dest [3]; /* Destination H address */N unsigned short int rhdr$g_src [3]; /* Source address */N unsigned short int rhdr$w_type; /* Protocol type */N unsigned short int rhdr$w_ctl; /* 802 CTL */R unsigned int rhdr$l_res; /* Push structure size 4 bytes for 802E */ } RHDRDEF; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __requHired_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RHDRDEF_LOADED */ wwp[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise DevelopmeHnt, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/HM/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************************************* H*************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */I/* Source: 16-JUN-2017 10:43:39 $1$DGA8345:[LIB_H.SRC]RIGHTSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RIGHTSDEF ***/#ifndef __RIGHTSDEF_LOADED#define __RIGHTSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#praHgma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __structH#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* RightsList structure definitions */N/* */ N#define ID$K_LENGTH 8 H /* Length of ID$ structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _id {#pragma __nomember_alignmentN unsigned int id$l_value; /* Binary identifier value */N unsigned int id$l_flags; /* Flags associated with identifier */ } ID; c#if !defined(__NOBASEALIGN_SUPPO HRT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rights {#pragma __nomember_alignmentN struct _rights *rights$l_flink; /* Standard listhead forward link */N struct _rights *rights$l_blink; /* Standard listhead backward link */O unsigned short int rights$w_size; /* Standard structure size, in bytes */` unsigned char rights$b_type; /* StandarHd type code for RIGHTS (DYN$C_SECURITY) */_ unsigned char rights$b_subtype; /* Standard subtype code (DYN$C_SECURITY_RIGHTS) */b struct _rights *rights$l_debug_flink; /* Forward link to next Rightslist in system (DEBUG) */b struct _rights *rights$l_debug_blink; /* Backward link to next Rightslist in system (DEBUG) */` unsigned int rights$l_debug_pid; /* PID of process which allocated this PCB (DEBUG) */N unsigned int rights$l_refcount; /* H */W unsigned int rights$l_id_count; /* Number of identifiers that array can hold */] unsigned int rights$l_id_used; /* Number of identifiers currently stored in array */N/* */N/* The following two locations must be kept adjacent, as they are */N/* treated as a descriptor that points at the rights data */N/* H */Q unsigned int rights$l_id_length; /* Number of bytes taken up by ID_USED */N struct _id *rights$a_id_array; /* Address of identifier array */#if defined(__VAXC) char rights$t_identifiers[];#else-#define rights$t_identifiers rights$b_fill_0_"#endif /* #if defined(__VAXC) */ char rights$b_fill_0_ [4]; } RIGHTS;N#define RIGHTS$K_LENGTH 48 /* Length of RIGHTS$ structure */N/* H */N/* The following constants are assigned values chosen for no */N/* reason other than they seemed appropriate at the time. */N/* */N#define RIGHTS$K_INITIAL_IDENTIFIERS 16 /* Initial allocation */N#define RIGHTS$K_COUNT_IDENTIFIERS 64 /* expantion allocation */$#define RIGHTS$K_MAX_IDENTIFIERS 528  # ifdef __INITIAL_POINTER_S HIZEM# pragma __required_pointer_size __save /* Save current pointer size */_# pragma __required_pointer_size 32 /* And set ptr size default to 32-bit pointers */[ typedef struct _rights * RIGHTS_ps; /* 32-bit pointer signed to a rights block */S# pragma __required_pointer_size __restore /* Return to previous pointer size */# elsek typedef signed __int32 RIGHTS_ps; /* Same size as a 32-bit pointer signed to a rights block */# endif $#pragma H__member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RIGHTSDEF_LOADED */ wwѸ[UM/***************************************************************************/M/** **/M/*H* HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIHDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************** H**********************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */F/* Source: 19-NOV-2009 01:21:59 $1$DGA8345:[LIB_H.SRC]RIHDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RIHDEF ***/#ifndef __RIHDEF_LOADED#define __RIHDEF_LOADED 1 H G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __Hoptional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */h/* RAD Information Header - Structure containing information about the Res Hource Affinity Domain (RAD) */R/* characteristics of the current system. This is used for NUMA support. */N/* */N/* */#define RIH$M_RAD_ENABLE 0x1#define RIH$M_AFFINITY 0x2#define RIH$M_SYSTEM_REPL 0x4!#define RIH$M_COPY_SOFT_FAULT 0x8#define RIH$M_SPECIAL 0x10#define RIH$M_FORCE_RAD 0x20#define RIH$M_RAD_POOL 0x40$#define RIH$M_PL HATFORM_DECISION 0x80##define RIH$M_PROCESS_ALLOC 0x30000##define RIH$M_SWAPPER_ALLOC 0xC0000##define RIH$M_GLOBAL_ALLOC 0x300000##define RIH$M_SYSTEM_ALLOC 0xC00000"#define RIH$M_SKIP_COUNT 0xF000000 #define RIH$C_CPU_MASK_OFFSET 64N#define RIH$C_CPU_MASK_BYTES 128 /* CPU Mask size in bytes */N#define RIH$C_CPU_MASK_QUADS 16 /* CPU Mask size in bytes */V#define RIH$C_CPU_MASK_SHIFT 7 /* Shift value to index to a RAD's CPU Mask */N#define RIH$C_HMAX_RAD_COUNT 32 /* Maximum supported RADs */  9#ifdef __cplusplus /* Define structure prototypes */ struct _rha; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rih {#pragma __nomember_alignmentQ unsigned int rih$l_max_rads; /* The maximum RADs possible on syst Hem */ __union {R unsigned int rih$l_flags; /* Copy of RAD_SUPPORT sysgen parameter */ __struct {N unsigned rih$v_rad_enable : 1; /* Enable RAD support */O unsigned rih$v_affinity : 1; /* Enable Soft RAD affinity support */[ unsigned rih$v_system_repl : 1; /* Enable read-only system space replication */O unsigned rih$v_copy_soft_fault : 1; /* Enable copy on soft fault */N unsigned rih$v_special : 1H; /* Enable special allocation flags */_ unsigned rih$v_force_rad : 1; /* Debug: RAD support software on non-RAD machines */N unsigned rih$v_rad_pool : 1; /* Enable per-RAD non-paged pool */i unsigned rih$v_platform_decision : 1; /* if set platform code will decide if RAD is on/off */N unsigned rih$v_reserved_2 : 8; /* Reserved for future use */N unsigned rih$v_process_alloc : 2; /* Process page allocation */N unsignHed rih$v_swapper_alloc : 2; /* Swapper page allocation */N unsigned rih$v_global_alloc : 2; /* Global page allocation */O unsigned rih$v_system_alloc : 2; /* System space page allocation */n unsigned rih$v_skip_count : 4; /* How many times scheduler skips a process before going off-RAD */N/* The actual count is 2**SKIP_COUNT */N unsigned rih$v_reserved_3 : 4; /* Reserved for future use */ H } rih$r_flags_bits; } rih$r_flags_overlay;N unsigned short int rih$w_size; /* Size of structure in bytes */N unsigned char rih$b_type; /* DYN$C_MISC */N unsigned char rih$b_subtype; /* DYN$C_RIH */g int rih$l_cpu_shift_value; /* Shift from CPU ID to RAD, -1 if it does not work that way */d int rih$l_pfn_shift_value; /* Shift from PFN to RAD, -1 if it does not work that way */c H int rih$l_pa_shift_value; /* Shift from PA to RAD, -1 if it does not work that way */X unsigned int rih$l_base_rad; /* The RAD that contains SYS$BASE_IMAGE et al */V unsigned int rih$l_cpu_mask_offset; /* Offset from beginning of RIH to CPU_MASK */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* De Hfined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */V struct _rha *rih$pq_gblsec_rads; /* Pointer to global section RAD hint array */#else% unsigned __int64 rih$pq_gblsec_rads;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifX int H(*rih$l_pa_to_rad)(); /* pointer to routine converting PA to RAD id */\ int (*rih$l_cpu_to_rad)(); /* pointer to routine converting CPU id to RAD id */h void (*rih$l_rad_to_pa_range)(); /* pointer to routine returning a PA range for a given RAD id */p int rih$l_alt_base_rad; /* Will contain a RAD of equal cost to the base RAD if present (IA64) */N char rih$t_align [8]; /* pad to next cache line */ __struct {N unsi Hgned __int64 rih$q_cpu_mask_array [16]; /* array of CPU Masks */ } rih$r_cpu_array [32]; } RIH; #if !defined(__VAXC)3#define rih$l_flags rih$r_flags_overlay.rih$l_flagsN#define rih$v_rad_enable rih$r_flags_overlay.rih$r_flags_bits.rih$v_rad_enableJ#define rih$v_affinity rih$r_flags_overlay.rih$r_flags_bits.rih$v_affinityP#define rih$v_system_repl rih$r_flags_overlay.rih$r_flags_bits.rih$v_system_replX#define rih$v_copy_soft_fault rih$r_flags_overlay.rih$r_flags_bits.rih$v_cHopy_soft_faultH#define rih$v_special rih$r_flags_overlay.rih$r_flags_bits.rih$v_specialL#define rih$v_force_rad rih$r_flags_overlay.rih$r_flags_bits.rih$v_force_radJ#define rih$v_rad_pool rih$r_flags_overlay.rih$r_flags_bits.rih$v_rad_pool\#define rih$v_platform_decision rih$r_flags_overlay.rih$r_flags_bits.rih$v_platform_decisionN#define rih$v_reserved_2 rih$r_flags_overlay.rih$r_flags_bits.rih$v_reserved_2T#define rih$v_process_alloc rih$r_flags_overlay.rih$r_flags_bits.rih$v_process_allocT#d Hefine rih$v_swapper_alloc rih$r_flags_overlay.rih$r_flags_bits.rih$v_swapper_allocR#define rih$v_global_alloc rih$r_flags_overlay.rih$r_flags_bits.rih$v_global_allocR#define rih$v_system_alloc rih$r_flags_overlay.rih$r_flags_bits.rih$v_system_allocN#define rih$v_skip_count rih$r_flags_overlay.rih$r_flags_bits.rih$v_skip_countN#define rih$v_reserved_3 rih$r_flags_overlay.rih$r_flags_bits.rih$v_reserved_31#define rih$q_cpu_mask_array rih$q_cpu_mask_array"#endif /* #if !defined(__VAXC) */ N#dHefine RIH$C_LENGTH 4160 /* Length of RAD info header */Q#define RIH$C_CURRENT_RAD 0 /* Allocate from the current CPU's RAD */N#define RIH$C_RANDOM_RAD 1 /* Allocate randomly from all RADs */N#define RIH$C_BASE_RAD 2 /* Allocate from the BASE RAD */N#define RIH$C_HOME_RAD 3 /* Allocate from the home RAD */N#define RIH$C_DEFAULT_SKIP 16 /* Skip count for soft RAD affinity */Q#define RIH$C_DEFAULT_PR HOCESS_ALLOC 3 /*Default process allocation algorithm */Q#define RIH$C_DEFAULT_SWAPPER_ALLOC 1 /*Default swapper allocation algorithm */P#define RIH$C_DEFAULT_GLOBAL_ALLOC 1 /*Default global allocation algorithm */P#define RIH$C_DEFAULT_SYSTEM_ALLOC 0 /*Default system allocation algorithm */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftype Hdef struct _rha {#pragma __nomember_alignment# unsigned __int64 rha$q_unused1;b unsigned short int rha$w_mbo; /* Must Be One (if 65535 Global Sections, size too big) */N unsigned char rha$b_type; /* DYN$C_MISC */N unsigned char rha$b_subtype; /* DYN$C_RHA */ unsigned int rha$l_unused2;N unsigned __int64 rha$q_size; /* Size of structure */N char rha$t_hint_array [1]; /* T Hhe actual RAD hint array */ char rha$b_fill_0_ [7]; } RHA; #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Dtypedef struct _rih * RIH_PQ; /* Pointer to a RIH structure. */Dtypedef struct _rha * RHA_PQ; /* Pointer to a RHA structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsiHgned __int64 RIH_PQ;##endif /* __INITIAL_POINTER_SIZE */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RIHDEF_LOADED */ ww[UM/***************************************************************************/M/** H **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** H **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** H **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */I/* Source: 09-JUN-1993 15:42:57 $1$DGA8345:[LIB_H.SRC]RMSFILSTR.SDL;1 *//********************************************************************************************************************************//*** H MODULE $RJRDEF ***/#ifndef __RJRDEF_LOADED#define __RJRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #iHfdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */HN/* */N/* definitions for the journal records in RMS journal files */N/* */N/* */N#define RJR$C_RMS_AI 1 /* after-image journal */N#define RJR$C_RMS_BI 2 /* before-image journal */N#define RJR$C_RMS_RU 3 H /* recovery unit */N#define RJR$C_RMS_AT 4 /* audit trail */N#define RJR$C_MAXJNL 4 /* jnl type limit */N#define RJR$C_VER1 1 /* journal version 1 */N#define RJR$C_CURVER 1 /* current version */N#define RJR$C_NULL 0 /* No entry follows the header */N#define RJR$C_LEADER 1 /* leader Hentry */N#define RJR$C_TRAILER 2 /* trailer entry */N#define RJR$C_RECORD 3 /* record entry (AI, BI, RU) */N#define RJR$C_BLOCK 4 /* block entry (AI, BI, RU) */N#define RJR$C_EXTEND 5 /* extend entry (AI, AT) */N#define RJR$C_CREATE 6 /* create entry (AI, AT) */N#define RJR$C_AT_RECORD 7 /* audit trail record (AT) H*/N#define RJR$C_DEFINE_JNL 8 /* Journal creation record */N#define RJR$C_BACKUP 9 /* Backup done entry (AI, BI) */N#define RJR$C_COMMIT 10 /* RU commit entry (AI, BI) */N#define RJR$C_ABORT 11 /* RU abort entry (AI, BI) */N#define RJR$C_PREPARE 12 /* RU prepare entry (AI, BI, RU) */N#define RJR$C_FORCED_COMMIT 13 /* RU forced commit for AI jnls */N#define RJR$C_MAXTYP 1H3 /* entry-type limit */N#define RJR$C_SEQ 0 /* sequential file org */N#define RJR$C_REL 1 /* relative file org */N#define RJR$C_IDX 2 /* indexed file org */N#define RJR$C_HSH 3 /* hashed file org */N#define RJR$C_MAXORG 3 /* org limit */N#define RJR$_CLOSE 1 /* closeH */N#define RJR$_CONNECT 2 /* connect */N#define RJR$_CREATE 3 /* create */N#define RJR$_DELETE 4 /* delete */N#define RJR$_DISCONNECT 5 /* disconnect */N#define RJR$_DISPLAY 6 /* display */N#define RJR$_ENTER 7 /* enter H */N#define RJR$_ERASE 8 /* erase */N#define RJR$_EXTEND 9 /* extend */N#define RJR$_FIND 10 /* find */N#define RJR$_FLUSH 11 /* flush */N#define RJR$_FREE 12 /* free */N#define RJR$_GET 13 /* get */N#define RJR$_MODIFY H14 /* modify */N#define RJR$_NXTVOL 15 /* next volume */N#define RJR$_OPEN 16 /* open */N#define RJR$_PARSE 17 /* parse */N#define RJR$_PUT 18 /* put */N#define RJR$_READ 19 /* block I/O read */N#define RJR$_RELEASE 20 /* relHease */N#define RJR$_REMOVE 21 /* remove */N#define RJR$_RENAME 22 /* rename */N#define RJR$_REWIND 23 /* rewind */N#define RJR$_SEARCH 24 /* search */N#define RJR$_SPACE 25 /* block I/O space */N#define RJR$_TRUNCATE 26 /* truncate H */N#define RJR$_UPDATE 27 /* update */N#define RJR$_WAIT 28 /* wait */N#define RJR$_WRITE 29 /* block I/O write */N#define RJR$_TPT 30 /* truncate on PUT */N#define RJR$_MAXOPER 30 /* oper limit */N#define RJR$C_HDRLEN 72 /* common header len */N#define RJR$K_HDRLHEN 72 /* common header len */N#define RJR$C_COMMITLEN 72 /* commit entry len */N#define RJR$K_COMMITLEN 72 /* commit entry len */N#define RJR$C_ABORTLEN 72 /* abort entry len */N#define RJR$K_ABORTLEN 72 /* abort entry len */N#define RJR$C_FORCED_COMMITLEN 72 /* forced commit entry len */N#define RJR$K_FORCED_COMMITLEN 72 /* fHorced commit entry len */N/* */N#define RJR$C_LDRLEN 169 /* leader entry len */N#define RJR$K_LDRLEN 169 /* leader entry len */N/* the 3 filespec strings above appear here */N#define RJR$C_TRLLEN 107 /* trailer entry len */N#define RJR$K_TRLLEN 107 /* trailer entry len H */N/* filespec of next journal file appears here */N#define RJR$C_RECLEN 100 /* record entry len */N#define RJR$K_RECLEN 100 /* record entry len */N#define RJR$C_BLKLEN 96 /* block i/o entry len */N#define RJR$K_BLKLEN 96 /* block i/o entry len */#define RJR$M_EXT_USE_XAB 0x1N#define RJR$C_EXTLEN 114 /* extend entry len H */N#define RJR$K_EXTLEN 114 /* extend entry len */#define RJR$M_ATR_UCHAR 0x1#define RJR$M_ATR_PROT 0x2#define RJR$M_ATR_UIC 0x4#define RJR$M_ATR_REC 0x8#define RJR$M_ATR_EXPIRE 0x10#define RJR$C_FIBLEN 64#define RJR$K_FIBLEN 64#define RJR$C_RECATRLEN 32#define RJR$K_RECATRLEN 32#define RJR$C_CRELEN 226#define RJR$K_CRELEN 226#define RJR$C_AT_RECLEN 104#define RJR$K_AT_RECLEN 104#define RJR$C_BACKUPLEN 92#define RJR$K_BAHCKUPLEN 92N#define RJR$C_PREPARELEN 112 /* prepare entry len */N#define RJR$K_PREPARELEN 112 /* prepare entry len */N/* actual node name string follows here */W#define RJR$C_BLN 226 /* length of RJR descriptor in the prologue */W#define RJR$K_BLN 226 /* length of RJR descriptor in the prologue */N#define RJR$S_RJRDEF 226 /* Old size name - synonym H */ typedef struct _rjr {N unsigned short int rjr$w_facility; /* facility code (=1) */ __union {N unsigned short int rjr$w_flags; /* flags */ __struct {V unsigned rjr$v_first_ru_record : 1; /* first journal record for this RU */U unsigned rjr$v_ruj_in_ltj : 1; /* this is a RU record written to a LTJ */Y unsigned rjr$v_written_by_recover : 1; /* written during detached reocvery */h H unsigned rjr$v_first_stream_ru_record : 1; /* first journal record for this stream and RU */[ unsigned rjr$v_recovered : 1; /* entries for leader record already recovered */N unsigned rjr$v_nopad : 1; /* Do not pad AI record */( unsigned rjr$v_fill_17_ : 2; } rjr$r_fill_10_; } rjr$r_fill_9_;N unsigned int rjr$l_jnlidx; /* journal stream index */N unsigned char rjr$b_jnl_type; /* journalinHg type */N unsigned char rjr$b_version; /* RMS journal version # */N unsigned char rjr$b_entry_type; /* journal entry type */N unsigned char rjr$b_org; /* file organization */N unsigned char rjr$b_oper; /* RMS operation id */N char rjr$b_fill_c2 [3]; /* spare to longword align */ __union {T char rjr$t_ruid [16]; /* RUID (if operation Hperformed in an RU) */ __struct {N char rjr$t_tid [16]; /* TID is the RUID under DDTM */ } rjr$r_fill_12_; } rjr$r_fill_11_;S unsigned int rjr$l_epid; /* EPID of the process writing the entry */N unsigned __int64 rjr$q_date; /* date/time of record */N unsigned int rjr$l_at_sts; /* status of operation (AT) */N unsigned int rjr$l_at_stv; /* secondary status (AT) H */N unsigned int rjr$l_at_ctx; /* user FAB/RAB CTX field (AT) */ int rjr$l_fill_c4; int rjr$l_fill_c5; int rjr$l_fill_c6; int rjr$l_fill_c7;N/* End of common RJR header. Begin entry-specific definitions. */N/* */ __union {N/* */N/* Leader record. First record in each journal file. H */N/* */N __struct { /* leader entry */u unsigned short int rjr$w_filespec_off; /* offset to filespec of file being journaled (from top of RJR) */c unsigned short int rjr$w_filespec_len; /* length of filespec of file being journaled */N unsigned char rjr$b_volnam_len; /* length of volume name string */Q char rjr$t_volnam [1H2]; /* volume name of file being journaled */N char rjr$t_fid [6]; /* FID of file being journaled */U unsigned __int64 rjr$q_cdate; /* creation date of file being journaled */o unsigned short int rjr$w_j_filespec_off; /* offset to filespec of journal file (from top of RJR) */] unsigned short int rjr$w_j_filespec_len; /* length of filespec of journal file */P unsigned char rjr$b_j_volnam_len; /* length of volume name strinHg */N char rjr$t_j_volnam [12]; /* volume name of journal file */N char rjr$t_j_fid [6]; /* FID of journal file */O unsigned __int64 rjr$q_j_cdate; /* creation date of journal file */y unsigned short int rjr$w_pj_filespec_off; /* offset to filespec of previous journal file (from top of RJR) */g unsigned short int rjr$w_pj_filespec_len; /* length of filespec of previous journal file */Q unsigned char rjHr$b_pj_volnam_len; /* length of volume name string */R char rjr$t_pj_volnam [12]; /* volume name of previous journal file */N char rjr$t_pj_fid [6]; /* FID of previous journal file */Y unsigned __int64 rjr$q_pj_cdate; /* creation date of previous journal file */a unsigned int rjr$l_pj_jnlidx; /* journal stream index of the previous journal file */! } rjr$r_leader_entry;N/* H */P/* Trailer record. This record is only present in AI or BI journal files that */Q/* have newer versions. It is written to the old journal file when a file that */O/* was already marked for journaling is re-marked for journaling to point to */N/* a newer version of a journal file. */N/* */N __struct { /* trailer entry H*/u unsigned short int rjr$w_nj_filespec_off; /* offset to filespec of next journal file (from top of RJR) */c unsigned short int rjr$w_nj_filespec_len; /* length of filespec of next journal file */Q unsigned char rjr$b_nj_volnam_len; /* length of volume name string */N char rjr$t_nj_volnam [12]; /* volume name of next journal file */N char rjr$t_nj_fid [6]; /* FID of next journal file */U unsigned __int64 rjr$q_nHj_cdate; /* creation date of next journal file */] unsigned int rjr$l_nj_jnlidx; /* Journal stream index of the next journal file */" } rjr$r_trailer_entry;N/* */N/* Record entry. Used for AI, BI, and RU to journal record operations. */N/* */N __struct { /* record entry */ H int rjr$l_fill_rec1; int rjr$l_fill_rec2; int rjr$l_fill_rec3; int rjr$l_fill_rec4;N unsigned int rjr$l_chksum; /* checksum of old record */ __union {N unsigned short int rjr$w_rfa [3]; /* RFA of record */ __struct {N unsigned int rjr$l_rfa0; /* alternate RFA def */2 unsigned short int rjr$w_rfa4;' } rjr$ Hr_rfa_fields;N unsigned int rjr$l_rrn; /* relative record number */$ } rjr$r_rfa_overlay;N unsigned short int rjr$w_rsize; /* record size */#if defined(__VAXC) char rjr$t_rimage[];#elseS/* Warning: empty char[] member for rjr$t_rimage at end of structure not created */"#endif /* #if defined(__VAXC) */! } rjr$r_record_entry;N/* H */N/* The block entry is used for ISAM AI/BI bucket entries, $WRITEs, and AT. */N/* */N __struct { /* block entry */ int rjr$l_fill_blk1; int rjr$l_fill_blk2; int rjr$l_fill_blk3; int rjr$l_fill_blk4;N unsigned int rjr$l_block_vbn; /* vbn of block */N unsigned short int rjr$w_blo Hck_size; /* transfer size */N unsigned short int rjr$w_jblock_size; /* actual size of */N/* journaled data */#if defined(__VAXC) char rjr$t_block[];#elseR/* Warning: empty char[] member for rjr$t_block at end of structure not created */"#endif /* #if defined(__VAXC) */N/* */N/* RJR$C_BLKLEN must be a quadword multiplHe or indexed data buffers */N/* will not be quadword aligned!!! This constant is used to size */N/* indexed data buffers which have imbedded AI and BI RJR headers */N/* when long term journaling is used. */N/* */ } rjr$r_block_entry;N/* */N/* The extend entry is common to b Hoth AT and AI journaling. */N/* */N __struct { /* extend entry */ int rjr$l_fill_ext1; int rjr$l_fill_ext2; int rjr$l_fill_ext3; int rjr$l_fill_ext4; __union {- unsigned int rjr$l_ext_flags; __struct {P unsigned rjr$v_ext_use_xab : 1; /* ALL XAB H fields present */0 unsigned rjr$v_fill_18_ : 7;% } rjr$r_fill_14_;! } rjr$r_fill_13_;N/* */O/* Fields EXT_AOP (unused) through EXT_RFI are in same relative locations as */N/* the same fields in allocation XAB. */N/* */N unsigned char rjr$b_ext_aoHp; /* align options */N unsigned char rjr$b_ext_aln; /* alignment boundary */N unsigned short int rjr$w_ext_vol; /* relative volume number */N unsigned int rjr$l_ext_loc; /* location */N unsigned int rjr$l_ext_alq; /* allocation quantity */N unsigned short int rjr$w_ext_deq; /* default extension */N unsigned char rjr$b_ext_bkz; /* bucket size H */N unsigned char rjr$b_ext_aid; /* area ID */N unsigned short int rjr$w_ext_rfi [3]; /* related file IFI */#if defined(__VAXC)$ char rjr$t_ext_endall[];#elseW/* Warning: empty char[] member for rjr$t_ext_endall at end of structure not created */"#endif /* #if defined(__VAXC) */! } rjr$r_extend_entry;N/* */N/* The CREATE entry His used to record the information required to re-create */N/* a file for AI journaling, and to record a create for AT journaling. */N/* */ __struct {# int rjr$l_fill_create1;# int rjr$l_fill_create2;# int rjr$l_fill_create3;# int rjr$l_fill_create4; __union {- unsigned int rjr$l_atr_flags; __struct {O H unsigned rjr$v_atr_uchar : 1; /* UCHAR attribute present */N unsigned rjr$v_atr_prot : 1; /* PROT attribute present */N unsigned rjr$v_atr_uic : 1; /* UIC attribute present */O unsigned rjr$v_atr_rec : 1; /* RECORD attributes present */N unsigned rjr$v_atr_expire : 1; /* EXPIRATION present */0 unsigned rjr$v_fill_19_ : 3;% } rjr$r_fill_16_;! } rjr$Hr_fill_15_;N unsigned int rjr$l_uic; /* owner UIC */N unsigned int rjr$l_prot; /* prot mask */N unsigned int rjr$l_alloc; /* initial allocation (audit) */N unsigned int rjr$l_uchar; /* user characteristics (create) */N unsigned __int64 rjr$q_expire; /* expiration date (create) */N unsigned char rjr$b_fac; /* file access (audit) */N Hunsigned char rjr$b_shr; /* sharing allowed (audit) */Z unsigned short int rjr$w_did [3]; /* directory ID (create, volume recovery) */) short int rjr$w_fill_create6;N char rjr$t_fib [64]; /* FIB (create) */N char rjr$t_rec_attr [32]; /* record attributes (create) */d unsigned short int rjr$w_c_filespec_off; /* offset to full filespec (from top of RJR) */R unsigned short int rjr$w_c_f Hilespec_len; /* length of full filespec */! } rjr$r_create_entry;N/* */N/* The AT record is used for audit-trail journaling. */N/* */ __struct { int rjr$l_fill_at1; int rjr$l_fill_at2; int rjr$l_fill_at3; int rjr$l_fill_at4;N unsigned int rjr H$l_at_rop; /* record options */N unsigned char rjr$b_at_krf; /* key of reference */N unsigned char rjr$b_at_ksz; /* key size */N unsigned char rjr$b_at_rac; /* record access mode */ char rjr$b_fill_at5; __union {N unsigned short int rjr$w_at_rfa [3]; /* RFA of record */ __struct {N unsigned int rjr$l_at_rfa0 H; /* alternate RFA def */5 unsigned short int rjr$w_at_rfa4;* } rjr$r_at_rfa_fields;N unsigned int rjr$l_at_rrn; /* relative record number */' } rjr$r_at_rfa_overlay;% short int rjr$w_fill_at6;#if defined(__VAXC) char rjr$t_at_key[];#elseS/* Warning: empty char[] member for rjr$t_at_key at end of structure not created */"#endif /* #if defined(__VAXC) */ } rjr$r_at_r Hecord;N/* */R/* The BACKUP_ENTRY record is used to flag that a backup has been taken on the */V/* data file being journaled. It provides a known starting point for rollforward. */N/* */ __struct {& int rjr$l_fill_backup [4];N unsigned int rjr$l_backup_seqno; /* Backup sequence number */! } rjr$r_backHup_entry;N/* */O/* The prepare record is written to RU, AI, and BI journals for transactions */N/* that required a two-phase commit protocol. */N/* */N __struct { /* prepare entry */N char rjr$t_ddtm_log_id [16]; /* DDTM log id */N Ichar rjr$t_ruj_log_id [16]; /* RMS RUJ log id */T unsigned short int rjr$w_node_name_off; /* offset to node name string */T unsigned short int rjr$w_node_name_len; /* length of node name string */^ unsigned short int rjr$w_rm_name_off; /* offset to resource manager name string */^ unsigned short int rjr$w_rm_name_len; /* length of resource manager name string */" } rjr$r_prepare_entry; } rjr$r_entry_overlay; } IRJR; #if !defined(__VAXC)-#define rjr$w_flags rjr$r_fill_9_.rjr$w_flagsP#define rjr$v_first_ru_record rjr$r_fill_9_.rjr$r_fill_10_.rjr$v_first_ru_recordF#define rjr$v_ruj_in_ltj rjr$r_fill_9_.rjr$r_fill_10_.rjr$v_ruj_in_ltjV#define rjr$v_written_by_recover rjr$r_fill_9_.rjr$r_fill_10_.rjr$v_written_by_recover^#define rjr$v_first_stream_ru_record rjr$r_fill_9_.rjr$r_fill_10_.rjr$v_first_stream_ru_recordD#define rjr$v_recovered rjr$r_fill_9_.rjr$r_fill_10_.rjr$v_recovered<#define rjr$v_nopaId rjr$r_fill_9_.rjr$r_fill_10_.rjr$v_nopad,#define rjr$t_ruid rjr$r_fill_11_.rjr$t_ruid9#define rjr$t_tid rjr$r_fill_11_.rjr$r_fill_12_.rjr$t_tidT#define rjr$w_filespec_off rjr$r_entry_overlay.rjr$r_leader_entry.rjr$w_filespec_offT#define rjr$w_filespec_len rjr$r_entry_overlay.rjr$r_leader_entry.rjr$w_filespec_lenP#define rjr$b_volnam_len rjr$r_entry_overlay.rjr$r_leader_entry.rjr$b_volnam_lenH#define rjr$t_volnam rjr$r_entry_overlay.rjr$r_leader_entry.rjr$t_volnamB#define rjr$t_fid rjr$r_entrIy_overlay.rjr$r_leader_entry.rjr$t_fidF#define rjr$q_cdate rjr$r_entry_overlay.rjr$r_leader_entry.rjr$q_cdateX#define rjr$w_j_filespec_off rjr$r_entry_overlay.rjr$r_leader_entry.rjr$w_j_filespec_offX#define rjr$w_j_filespec_len rjr$r_entry_overlay.rjr$r_leader_entry.rjr$w_j_filespec_lenT#define rjr$b_j_volnam_len rjr$r_entry_overlay.rjr$r_leader_entry.rjr$b_j_volnam_lenL#define rjr$t_j_volnam rjr$r_entry_overlay.rjr$r_leader_entry.rjr$t_j_volnamF#define rjr$t_j_fid rjr$r_entry_overlay.rjr$r_leadIer_entry.rjr$t_j_fidJ#define rjr$q_j_cdate rjr$r_entry_overlay.rjr$r_leader_entry.rjr$q_j_cdateZ#define rjr$w_pj_filespec_off rjr$r_entry_overlay.rjr$r_leader_entry.rjr$w_pj_filespec_offZ#define rjr$w_pj_filespec_len rjr$r_entry_overlay.rjr$r_leader_entry.rjr$w_pj_filespec_lenV#define rjr$b_pj_volnam_len rjr$r_entry_overlay.rjr$r_leader_entry.rjr$b_pj_volnam_lenN#define rjr$t_pj_volnam rjr$r_entry_overlay.rjr$r_leader_entry.rjr$t_pj_volnamH#define rjr$t_pj_fid rjr$r_entry_overlay.rjr$r_leader_enItry.rjr$t_pj_fidL#define rjr$q_pj_cdate rjr$r_entry_overlay.rjr$r_leader_entry.rjr$q_pj_cdateN#define rjr$l_pj_jnlidx rjr$r_entry_overlay.rjr$r_leader_entry.rjr$l_pj_jnlidx[#define rjr$w_nj_filespec_off rjr$r_entry_overlay.rjr$r_trailer_entry.rjr$w_nj_filespec_off[#define rjr$w_nj_filespec_len rjr$r_entry_overlay.rjr$r_trailer_entry.rjr$w_nj_filespec_lenW#define rjr$b_nj_volnam_len rjr$r_entry_overlay.rjr$r_trailer_entry.rjr$b_nj_volnam_lenO#define rjr$t_nj_volnam rjr$r_entry_overlay.rjr$r_trIailer_entry.rjr$t_nj_volnamI#define rjr$t_nj_fid rjr$r_entry_overlay.rjr$r_trailer_entry.rjr$t_nj_fidM#define rjr$q_nj_cdate rjr$r_entry_overlay.rjr$r_trailer_entry.rjr$q_nj_cdateO#define rjr$l_nj_jnlidx rjr$r_entry_overlay.rjr$r_trailer_entry.rjr$l_nj_jnlidxH#define rjr$l_chksum rjr$r_entry_overlay.rjr$r_record_entry.rjr$l_chksumT#define rjr$w_rfa rjr$r_entry_overlay.rjr$r_record_entry.rjr$r_rfa_overlay.rjr$w_rfag#define rjr$l_rfa0 rjr$r_entry_overlay.rjr$r_record_entry.rjr$r_rfa_overlay.rjIr$r_rfa_fields.rjr$l_rfa0g#define rjr$w_rfa4 rjr$r_entry_overlay.rjr$r_record_entry.rjr$r_rfa_overlay.rjr$r_rfa_fields.rjr$w_rfa4T#define rjr$l_rrn rjr$r_entry_overlay.rjr$r_record_entry.rjr$r_rfa_overlay.rjr$l_rrnF#define rjr$w_rsize rjr$r_entry_overlay.rjr$r_record_entry.rjr$w_rsizeH#define rjr$t_rimage rjr$r_entry_overlay.rjr$r_record_entry.rjr$t_rimageM#define rjr$l_block_vbn rjr$r_entry_overlay.rjr$r_block_entry.rjr$l_block_vbnO#define rjr$w_block_size rjr$r_entry_overlay.rjr$r_block_entIry.rjr$w_block_sizeQ#define rjr$w_jblock_size rjr$r_entry_overlay.rjr$r_block_entry.rjr$w_jblock_sizeE#define rjr$t_block rjr$r_entry_overlay.rjr$r_block_entry.rjr$t_block]#define rjr$l_ext_flags rjr$r_entry_overlay.rjr$r_extend_entry.rjr$r_fill_13_.rjr$l_ext_flagsp#define rjr$v_ext_use_xab rjr$r_entry_overlay.rjr$r_extend_entry.rjr$r_fill_13_.rjr$r_fill_14_.rjr$v_ext_use_xabJ#define rjr$b_ext_aop rjr$r_entry_overlay.rjr$r_extend_entry.rjr$b_ext_aopJ#define rjr$b_ext_aln rjr$r_entry_overlay. Irjr$r_extend_entry.rjr$b_ext_alnJ#define rjr$w_ext_vol rjr$r_entry_overlay.rjr$r_extend_entry.rjr$w_ext_volJ#define rjr$l_ext_loc rjr$r_entry_overlay.rjr$r_extend_entry.rjr$l_ext_locJ#define rjr$l_ext_alq rjr$r_entry_overlay.rjr$r_extend_entry.rjr$l_ext_alqJ#define rjr$w_ext_deq rjr$r_entry_overlay.rjr$r_extend_entry.rjr$w_ext_deqJ#define rjr$b_ext_bkz rjr$r_entry_overlay.rjr$r_extend_entry.rjr$b_ext_bkzJ#define rjr$b_ext_aid rjr$r_entry_overlay.rjr$r_extend_entry.rjr$b_ext_aidJ#define rjr$w_ex It_rfi rjr$r_entry_overlay.rjr$r_extend_entry.rjr$w_ext_rfiP#define rjr$t_ext_endall rjr$r_entry_overlay.rjr$r_extend_entry.rjr$t_ext_endall]#define rjr$l_atr_flags rjr$r_entry_overlay.rjr$r_create_entry.rjr$r_fill_15_.rjr$l_atr_flagsl#define rjr$v_atr_uchar rjr$r_entry_overlay.rjr$r_create_entry.rjr$r_fill_15_.rjr$r_fill_16_.rjr$v_atr_ucharj#define rjr$v_atr_prot rjr$r_entry_overlay.rjr$r_create_entry.rjr$r_fill_15_.rjr$r_fill_16_.rjr$v_atr_proth#define rjr$v_atr_uic rjr$r_entry_overlay.rjr$r_cr Ieate_entry.rjr$r_fill_15_.rjr$r_fill_16_.rjr$v_atr_uich#define rjr$v_atr_rec rjr$r_entry_overlay.rjr$r_create_entry.rjr$r_fill_15_.rjr$r_fill_16_.rjr$v_atr_recn#define rjr$v_atr_expire rjr$r_entry_overlay.rjr$r_create_entry.rjr$r_fill_15_.rjr$r_fill_16_.rjr$v_atr_expireB#define rjr$l_uic rjr$r_entry_overlay.rjr$r_create_entry.rjr$l_uicD#define rjr$l_prot rjr$r_entry_overlay.rjr$r_create_entry.rjr$l_protF#define rjr$l_alloc rjr$r_entry_overlay.rjr$r_create_entry.rjr$l_allocF#define rjr$l_uchar rj Ir$r_entry_overlay.rjr$r_create_entry.rjr$l_ucharH#define rjr$q_expire rjr$r_entry_overlay.rjr$r_create_entry.rjr$q_expireB#define rjr$b_fac rjr$r_entry_overlay.rjr$r_create_entry.rjr$b_facB#define rjr$b_shr rjr$r_entry_overlay.rjr$r_create_entry.rjr$b_shrB#define rjr$w_did rjr$r_entry_overlay.rjr$r_create_entry.rjr$w_didB#define rjr$t_fib rjr$r_entry_overlay.rjr$r_create_entry.rjr$t_fibL#define rjr$t_rec_attr rjr$r_entry_overlay.rjr$r_create_entry.rjr$t_rec_attrX#define rjr$w_c_filespec_off rjr I$r_entry_overlay.rjr$r_create_entry.rjr$w_c_filespec_offX#define rjr$w_c_filespec_len rjr$r_entry_overlay.rjr$r_create_entry.rjr$w_c_filespec_lenE#define rjr$l_at_rop rjr$r_entry_overlay.rjr$r_at_record.rjr$l_at_ropE#define rjr$b_at_krf rjr$r_entry_overlay.rjr$r_at_record.rjr$b_at_krfE#define rjr$b_at_ksz rjr$r_entry_overlay.rjr$r_at_record.rjr$b_at_kszE#define rjr$b_at_rac rjr$r_entry_overlay.rjr$r_at_record.rjr$b_at_racZ#define rjr$w_at_rfa rjr$r_entry_overlay.rjr$r_at_record.rjr$r_at_rfa_Ioverlay.rjr$w_at_rfap#define rjr$l_at_rfa0 rjr$r_entry_overlay.rjr$r_at_record.rjr$r_at_rfa_overlay.rjr$r_at_rfa_fields.rjr$l_at_rfa0p#define rjr$w_at_rfa4 rjr$r_entry_overlay.rjr$r_at_record.rjr$r_at_rfa_overlay.rjr$r_at_rfa_fields.rjr$w_at_rfa4Z#define rjr$l_at_rrn rjr$r_entry_overlay.rjr$r_at_record.rjr$r_at_rfa_overlay.rjr$l_at_rrnE#define rjr$t_at_key rjr$r_entry_overlay.rjr$r_at_record.rjr$t_at_keyT#define rjr$l_backup_seqno rjr$r_entry_overlay.rjr$r_backup_entry.rjr$l_backup_seqnoS#definIe rjr$t_ddtm_log_id rjr$r_entry_overlay.rjr$r_prepare_entry.rjr$t_ddtm_log_idQ#define rjr$t_ruj_log_id rjr$r_entry_overlay.rjr$r_prepare_entry.rjr$t_ruj_log_idW#define rjr$w_node_name_off rjr$r_entry_overlay.rjr$r_prepare_entry.rjr$w_node_name_offW#define rjr$w_node_name_len rjr$r_entry_overlay.rjr$r_prepare_entry.rjr$w_node_name_lenS#define rjr$w_rm_name_off rjr$r_entry_overlay.rjr$r_prepare_entry.rjr$w_rm_name_offS#define rjr$w_rm_name_len rjr$r_entry_overlay.rjr$r_prepare_entry.rjr$w_rm_nIame_len"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RJRDEF_LOADED */ ww[UM/***************************************************************************/M/** I **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** I **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **I/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */F/* Source: 24-FEB-2022 15:34:31 $1$DGA8345:[LIB_H.SRC]RMDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RMDDEF **I*/#ifndef __RMDDEF_LOADED#define __RMDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplusI extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Reserved MemoIry Descriptor Definitions. The reserved memory */N/* descriptor contains memory management data for a memory */ #define RMD$M_ALLOC 0x1#define RMD$M_IN_USE 0x2#define RMD$M_ZERO 0x4#define RMD$M_ZERO_DONE 0x8#define RMD$M_FREED 0x10#define RMD$M_GROUP 0x20#define RMD$M_PAGE_TABLES 0x40#define RMD$M_GBLSEC 0x80!#define RMD$M_RESERVE_ERROR 0x100'#define RMD$M_RESERVED_FLAGS 0xFFFFFE00N#define RMD$C_LENGTH 96 /* Length of RMD I */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rmd {#pragma __nomember_alignmentN struct _rmd *rmd$ps_flink; /* Flink for VA list of RMDs */N struct _rmd *rmd$ps_blink; /* Blink for VA list of RMDs */N unsigned short int rmd$w_size; /* Structure size (including RMD) */NI unsigned char rmd$b_type; /* Dynamic structure type */N unsigned char rmd$b_subtype; /* Dynamic structore subtype */ __union {N unsigned int rmd$l_flags; /* FLAGS longword */ __struct {N unsigned rmd$v_alloc : 1; /* Pages already allocated */N unsigned rmd$v_in_use : 1; /* Pages in use by section */N unsigned rmd$v_zero : 1; /* Pages should be zeroed I */N unsigned rmd$v_zero_done : 1; /* Zeroing of pages finished */N unsigned rmd$v_freed : 1; /* Pages for section freed */N unsigned rmd$v_group : 1; /* For a group global section */N unsigned rmd$v_page_tables : 1; /* For page tables */a unsigned rmd$v_gblsec : 1; /* Reservation is for (group or system) global section */X unsigned rmd$v_reserve_error : 1; /* Reservation got an error Iduring boot *// unsigned rmd$v_reserved_flags : 23; } rmd$r_flags_bits; } rmd$r_flags_overlay;N/* Verified for x86 port - Clair Grant */Z unsigned __int64 rmd$i_first_pfn; /* First PFN of a contiguous set, 0 if no alloc */Y unsigned __int64 rmd$i_zero_pfn; /* Next PFN to zero, meaningful during zeroing */N unsigned int rmd$l_page_count; /* Count of PFNs in the section */ __union {N unsignIed int rmd$l_in_use_count; /* Number of PFNs in use */V unsigned int rmd$l_error_status; /* If RESERVE_ERROR flag set, error status */ } rmd$r_rmd_overlay;N unsigned int rmd$l_group; /* UIC group number (octal value) */N int rmd$l_rad; /* Resource Affinity Domain */N int rmd$l_spare1; /* Spare for future */U __union { /* ASCIC structure for global section name I */T char rmd$t_name [44]; /* GS NAMES never more than 43 characters */N __struct { /* Name as ASCIC structure */N unsigned char rmd$b_name_len; /* Character count */N char rmd$t_name_str [43]; /* Character string */ } rmd$r_name_ascic; } rmd$r_name_overlay; } RMD; #if !defined(__VAXC)3#define rmd$l_flags rmd$r_flags_overlay.rmd$l_flagsD#define rmd$v_alIloc rmd$r_flags_overlay.rmd$r_flags_bits.rmd$v_allocF#define rmd$v_in_use rmd$r_flags_overlay.rmd$r_flags_bits.rmd$v_in_useB#define rmd$v_zero rmd$r_flags_overlay.rmd$r_flags_bits.rmd$v_zeroL#define rmd$v_zero_done rmd$r_flags_overlay.rmd$r_flags_bits.rmd$v_zero_doneD#define rmd$v_freed rmd$r_flags_overlay.rmd$r_flags_bits.rmd$v_freedD#define rmd$v_group rmd$r_flags_overlay.rmd$r_flags_bits.rmd$v_groupP#define rmd$v_page_tables rmd$r_flags_overlay.rmd$r_flags_bits.rmd$v_page_tablesF#define rmd$Iv_gblsec rmd$r_flags_overlay.rmd$r_flags_bits.rmd$v_gblsecT#define rmd$v_reserve_error rmd$r_flags_overlay.rmd$r_flags_bits.rmd$v_reserve_errorV#define rmd$v_reserved_flags rmd$r_flags_overlay.rmd$r_flags_bits.rmd$v_reserved_flags?#define rmd$l_in_use_count rmd$r_rmd_overlay.rmd$l_in_use_count?#define rmd$l_error_status rmd$r_rmd_overlay.rmd$l_error_status0#define rmd$t_name rmd$r_name_overlay.rmd$t_nameI#define rmd$b_name_len rmd$r_name_overlay.rmd$r_name_ascic.rmd$b_name_lenI#define rmd$t_Iname_str rmd$r_name_overlay.rmd$r_name_ascic.rmd$t_name_str"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RMDDEF_LOADED */ ww[UM/*************************************************** I************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/!IM/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** "I **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:35 by OpenVMS SDL V3.7 */H/* Source: 16-FEB-2022 06:55:33 $1$DGA8345:[LIB_H.SRC]RMMGTDEF.SDL;1 *//*************************************************************************************************** #I*****************************//*** MODULE $RMMGTDEF ***/#ifndef __RMMGTDEF_LOADED#define __RMMGTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size defa$Iult to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif  N/* %I */N/* RMDriver status constants */N/* */N#define RMSTS$K_RESERVED 0 /* 0 - Reserved */N#define RMSTS$K_INITIAL 1 /* 1 - Initial driver state */Z#define RMSTS$K_DRIVER_INITED 2 /* 2 - Driver has been inited, but not started */N#define RMSTS$K_DRIVER_STARTED 3 /* 3 &I- Driver has been started */N#define RMSTS$K_DRIVER_STOPPED 4 /* 4 - Driver has been stopped */N/* */N/* Managed Object parameter structure for requests requiring the RMDRIVER */N/* security data. */N/* */N#define RMSECDAT$K_V1_1_SECDAT_LEN 8 /* Reg out data length 'I */N#define RMSECDAT$C_V1_1_SECDAT_LEN 8 /* Old VAX style length */ typedef struct _rmsecdat {c unsigned __int64 rmsecdat$q_rm_sec_token; /* Security token for accessing RMDriver functions */ } RMSECDAT;N/* */N/* Managed Object registration data from GET_REGISTRATION request */N/* */N/* This structure represen(Its data for Managed Object Parameter version 1.1 */N/* */N#define MORGR$K_OBJ_REG_STS_RESERVED 0 /* 0 - Reserved (for debugging) */N#define MORGR$K_OBJ_REG_STS_REGISTERED 1 /* 1 - MO is registered */N#define MORGR$K_OBJ_REG_STS_DREGISTERED 2 /* 2 - MO is deregistered */N#define MORGR$K_OBJ_REG_STS_UNUSED 3 /* Add new constants before here */N#define MORGR$K_OBJ_RUN_STS_RESERVED 0 /* 0 - Reser )Ived (for debugging) */N#define MORGR$K_OBJ_RUN_STS_REQ_ON 1 /* 1 - MO is processing requests */O#define MORGR$K_OBJ_RUN_STS_REQ_OFF 2 /* 2 - MO is not processing requests */N#define MORGR$K_OBJ_RUN_STS_UNUSED 3 /* Add new constants before here */N#define MORGR$K_OBJ_REG_LENGTH 48 /* MO registration data length */N#define MORGR$C_OBJ_REG_LENGTH 48 /* Old VAX style length */ typedef struct _morgr {N unsigned char morgr$t_obj_name [32]; /* Ma*Inaged Object name */N unsigned int morgr$l_obj_handle; /* Managed Object handle */V unsigned short int morgr$w_obj_type; /* Managed Object type (e.g. user, kernel) */N unsigned char morgr$b_obj_reg_status; /* Registration status */N unsigned char morgr$b_obj_run_status; /* Run status */N unsigned char morgr$b_obj_minor; /* Managed Object minor version */N unsigned char morgr$b_obj_major; /* Managed Object major +Iversion */N char morgr$t_obj_fill [6]; /* Fill to quadword boundary */ } MORGR;N/* */N/* Managed Object registration data from GET_MO_STATISTICS request */N/* */N/* This structure represents data for Managed Object Parameter version 1.1 */N/* ,I*/N#define MORGS$K_REG_DATA_LENGTH 40 /* MO registration data length */N#define MORGS$C_REG_DATA_LENGTH 40 /* Old VAX style length */ typedef struct _morgs {N unsigned int morgs$l_obj_handle; /* Managed Object handle */N unsigned int morgs$l_requests; /* Number of requests processed */U unsigned int morgs$l_errors; /* Number of errors in processing requests */` unsigned int morgs$l_resets; /* Number of resets to z-Iero done for these statistics */Q unsigned __int64 morgs$q_reg_time; /* Time when Managed Object registered */Z unsigned __int64 morgs$q_request_bytes; /* Total number of bytes in request packets */\ unsigned __int64 morgs$q_response_bytes; /* Total number of bytes in response packets */ } MORGS;N/* */N/* RMDRIVER configuration data from GET_RM_CONFIGURATION request */N/* .I */N/* This structure represents data for Managed Object Parameter version 3.1 */N/* */N/* Allow for 4 devices for future multiple connections */N#define RMCFGS$K_NUM_LAN_DEVICES 4 /* Number of LAN devices */N#define RMCFGS$K_BR_CALC_LOG_ENTRIES 11 /* Number of calc log entries */ !typedef struct _rmcfgs_dev_name {# char rmcfg /Is$t_dev_name_str [4]; } RMCFGS_DEV_NAME;N/* Keep length of info and info length to quadword multiple */N/* Keep length of info and info length to quadword multiple */ #define RMCFGS$S_DEV_NAME 16 N#define RMCFGS$K_RM_CONFIG_DATA_LENGTH 1104 /* RM configuration data length */N#define RMCFGS$C_RM_CONFIG_DATA_LENGTH 1104 /* Old VAX style length */ typedef struct _rmcfgs {S unsigned char rmcfgs$b_obj_minor; /* RMDriver Managed Object min0Ior version */S unsigned char rmcfgs$b_obj_major; /* RMDriver Managed Object major version */N unsigned short int rmcfgs$w_rsvd; /* Reserved */] unsigned short int rmcfgs$w_max_reg_entries; /* Maximum number of registration entries */] unsigned short int rmcfgs$w_cur_reg_entries; /* Current number of registration entries */[ unsigned __int64 rmcfgs$q_cpu_cycles_sec; /* CPU hardware/software cycles per second */N/* IA64/Alpha HWRPB$IQ_CYCLE_COUNT 1I_FREQ */[ unsigned int rmcfgs$l_cpu_cycles_ohns; /* CPU hardware/software cycles per 100ns tic */N unsigned int rmcfgs$l_reserved; /* Reserved for quadword alignment */. RMCFGS_DEV_NAME rmcfgs$r_req_dev_name [4];N/* LAN device requested from AMDS$DEVICE */* RMCFGS_DEV_NAME rmcfgs$r_dev_name [4];N/* LAN device used for LAN connection */# int rmcfgs$al_dll_hdr_size [4];N2I/* DLL header size */( int rmcfgs$al_max_netw_buf_size [4];N/* Maximum network buffer size */, int rmcfgs$al_default_netw_buf_size [4];N/* Default network buffer size */N unsigned int rmcfgs$l_mc_min_def_sec; /* Minimum default Hello interval */N unsigned int rmcfgs$l_mc_max_def_sec; /* Maximum default Hello interval */N unsigned int r3Imcfgs$l_mc_def_def_sec; /* Default default Hello interval */N unsigned int rmcfgs$l_mc_cur_def_sec; /* Current default Hello interval */Q unsigned int rmcfgs$l_mc_min_scnd_sec; /* Minimum secondary Hello interval */Q unsigned int rmcfgs$l_mc_max_scnd_sec; /* Maximum secondary Hello interval */Q unsigned int rmcfgs$l_mc_def_scnd_sec; /* Default secondary Hello interval */Q unsigned int rmcfgs$l_mc_cur_scnd_sec; /* Current secondary Hello interval */N unsigned int rmcfgs$l_mc4I_sec; /* Current Hello interval */N unsigned int rmcfgs$l_mc_size; /* Size of Hello packet */N unsigned int rmcfgs$l_min_rcv_vcrp_buffers; /* Minimum RCV VCRP buffers */N unsigned int rmcfgs$l_max_rcv_vcrp_buffers; /* Maximum RCV VCRP buffers */N unsigned int rmcfgs$l_def_rcv_vcrp_buffers; /* Default RCV VCRP buffers */N unsigned int rmcfgs$l_cur_rcv_vcrp_buffers; /* Current RCV VCRP buffers */N unsigned int rmcfgs$l_min_xmt_vcrp_buffers; /* Min5Iimum XMT VCRP buffers */N unsigned int rmcfgs$l_max_xmt_vcrp_buffers; /* Maximum XMT VCRP buffers */N unsigned int rmcfgs$l_def_xmt_vcrp_buffers; /* Default XMT VCRP buffers */N unsigned int rmcfgs$l_cur_xmt_vcrp_buffers; /* Current XMT VCRP buffers */N unsigned int rmcfgs$l_min_max_branches; /* Minimum max branches allowed */N unsigned int rmcfgs$l_max_max_branches; /* Maximum max branches allowed */N unsigned int rmcfgs$l_def_max_branches; /* Default max branches allowed */N6I unsigned int rmcfgs$l_cur_max_branches; /* Current max branches allowed */ unsigned int rmcfgs$l_max_branches_allowed; /* Number of branches allowed per MARK opcode after calculation in RM$AM_INIT */- int rmcfgs$al_max_branches_calc_log [11];N/* Log for calculating the max branches aloowed */] unsigned int rmcfgs$l_def_dcp_dump_opt; /* Default Data Collector program dump options */] unsigned int rmcfgs$l_cur_dcp_dump_opt; /* Current Data Collector pr 7Iogram dump options */! char rmcfgs$t_groupname [16];N/* AMDS Group name */ char rmcfgs$t_cluname [16];N/* AMDS Cluster name */" char rmcfgs$t_galaxyname [16];N/* AMDS Galaxy name */\ unsigned __int64 rmcfgs$q_site_info_marker; /* Marks where the site info fields begin */X unsigned short int rmcfgs$w_site_info_8Ilen; /* Length of site-specific information */" char rmcfgs$t_site_info [518];N/* Site-specific information */\ unsigned __int64 rmcfgs$q_node_info_marker; /* Marks where the node info fields begin */X unsigned short int rmcfgs$w_node_info_len; /* Length of node-specific information */" char rmcfgs$t_node_info [262];N/* Node-specific information */T unsigned __int64 rmcfgs$q_end_marker; 9I/* Marks the end of this data structure */ } RMCFGS; N/* */N/* RMDRIVER statistical data from GET_RM_STATISTICS request */N/* */N/* This structure represents data for Managed Object Parameter version 4.1 */N/* */S#define RMSTTS$K_RM_STARTUP_IDX_MAX 4 /*:I Number of startup information entries */R#define RMSTTS$M_RM_STARTUP_INDEX -4 /* Mask for wrapping index back to zero */T#define RMSTTS$K_RM_SHUTDOWN_IDX_MAX 4 /* Number of shutdown information entries */R#define RMSTTS$M_RM_SHUTDOWN_INDEX -4 /* Mask for wrapping index back to zero */Z#define RMSTTS$K_LAN_DLL_EVENT_IDX_MAX 8 /* Number of LAN DLL event information entries */R#define RMSTTS$M_LAN_DLL_EVENT_INDEX -8 /* Mask for wrapping index back to zero */O#define RMSTTS$K_TQE_EXEC_INDEX_ ;IMAX 8 /* Number of TQE information entries */R#define RMSTTS$M_TQE_EXEC_INDEX -8 /* Mask for wrapping index back to zero */N#define RMSTTS$K_RM_STAT_DATA_LENGTH 1256 /* RM statistics data length */N#define RMSTTS$C_RM_STAT_DATA_LENGTH 1256 /* Old VAX style length */ typedef struct _rmstts {W unsigned int rmstts$l_rm_startup_index; /* Point to current entry in ring buffer */X unsigned int rmstts$l_rm_shutdown_index; /* Point to current entry in ring buffer */1 Ir this data */S unsigned __int64 rmstts$q_stat_reset_time; /* Time that the stats were reset */o unsigned __int64 rmstts$q_prev_col_time; /* Time of previous data collection (affects *COLL_* variables) */n unsigned __int64 rmstts$q_curr_col_time; /* Time of current data collection (affects *COLL_* variables) */N unsigned __int64 rmstts$q_sys_boot_time; /* Time the system booted */\ unsigned int rmstts$l_irp_received_cnt; /* Count of IRPs received from local DA or DS */\ ?Iunsigned int rmstts$l_irp_completed_cnt; /* Count of IRPs completed to local DA or DS */z unsigned short int rmstts$w_irp_received_cntco; /* Count of IRPs received from local DA or DS since last collection */z unsigned short int rmstts$w_irp_completed_cntco; /* Count of IRPs completed to local DA or DS since last collection */Z unsigned short int rmstts$w_irp_cancelled_cnt; /* Count of IRPs that were cancelled */r unsigned short int rmstts$w_irp_cancelled_cntco; /* Count of IRPs that w@Iere cancelled since last collection */h unsigned short int rmstts$w_irp_flushed_cnt; /* Count of IRPs that were flushed from RM IRP queue */ unsigned short int rmstts$w_irp_flushed_cntco; /* Count of IRPs that were flushed from RM IRP queue since last collection */V unsigned short int rmstts$w_irp_aborted_cnt; /* Count of IRPs that were aborted */n unsigned short int rmstts$w_irp_aborted_cntco; /* Count of IRPs that were aborted since last collection */N/* AI */N/* -> IRP -------------------+--> UCB$L_RM_IRP -->+----------------->+ */N/* | | \ / ^ | */N/* v | IRP_QUD_UCB | | */N/* VCRP from queue | | - IRP_QUD_UCB | */{/* | v | | Flowchart for IRP and IRP statistic computation */N/* | BI +---> IRP Queue ---->+ | */N/* | - IRP_IMMED_CMPL \ / | */N/* | IRP_QUD_QUE | */N/* v v */N/* <- AM <-----------------------------------------------------------+ */N/* */W unsigned int rmstts$l_irp_immed_CIcmpl_cnt; /* Count of IRPs immediately completed */U unsigned int rmstts$l_irp_qud_ucb_cnt; /* Count of IRPs queued to UCB$L_RM_IRP */V unsigned int rmstts$l_irp_qud_que_cnt; /* Count of IRPs queued to the IRP queue */_ unsigned int rmstts$l_irp_qud_ucb_cmpl_cnt; /* Count of IRPs completed from UCB$L_RM_IRP */j unsigned int rmstts$l_irp_qud_que_ucb_cnt; /* Count of IRPs dequeued from IRP queue to UCB$L_RM_IRP */u unsigned short int rmstts$w_irp_immed_cmpl_cntco; /* Count of IRPsDI immediately completed since last collection */s unsigned short int rmstts$w_irp_qud_ucb_cntco; /* Count of IRPs queued to UCB$L_RM_IRP since last collection */t unsigned short int rmstts$w_irp_qud_que_cntco; /* Count of IRPs queued to the IRP queue since last collection */} unsigned short int rmstts$w_irp_qud_ucb_cmpl_cntco; /* Count of IRPs completed from UCB$L_RM_IRP since last collection */ unsigned short int rmstts$w_irp_qud_que_ucb_cntco; /* Count of IRPs dequeued from IRP quEIeue to UCB$L_RM_IRP since last collecti\on */X unsigned short int rmstts$w_irp_reserved1; /* IRP reserved for quadword alignment */p unsigned char rmstts$b_irp_argerr_nobuf_cnt; /* Count of IRP argument error - no buffer supplied with IRP */w unsigned char rmstts$b_irp_argerr_nolen_cnt; /* Count of IRP argument error - no buffer length supplied with IRP */x unsigned char rmstts$b_irp_nobytcnt_cnt; /* Count of EXQUOTA errors for allocation of system buffer for VCRP data */z unsiFIgned char rmstts$b_irp_diag_insfmem_cnt; /* Count of INSFMEM errors for allocation of diagnostic buffer for IRP */R unsigned int rmstts$l_irp_reserved2; /* IRP reserved for quadword alignment */N unsigned char rmstts$b_irp_qlen_max; /* Maximum size of the IRP queue */f unsigned char rmstts$b_irp_qlen_col_max; /* Maximum size of the IRP queue since last collection */R unsigned short int rmstts$w_irp_qlen_curr; /* Current size of the IRP queue */u unsigned short int rmstts$w_irp_qlGIen_ave2; /* Average IRP queue size using weight of 2 for exponential average */u unsigned short int rmstts$w_irp_qlen_ave4; /* Average IRP queue size using weight of 4 for exponential average */u unsigned short int rmstts$w_irp_qlen_ave8; /* Average IRP queue size using weight of 8 for exponential average */w unsigned short int rmstts$w_irp_qlen_ave16; /* Average IRP queue size using weight of 16 for exponential average */q unsigned int rmstts$l_irp_qlen_ave32; /* Average IRP queueHI size using weight of 32 for exponential average */s unsigned int rmstts$l_irp_qlen_ave128; /* Average IRP queue size using weight of 128 for exponential average */s unsigned int rmstts$l_irp_qlen_ave512; /* Average IRP queue size using weight of 512 for exponential average */s unsigned int rmstts$l_irp_qlen_ave2k; /* Average IRP queue size using weight of 2048 for exponential average */V unsigned int rmstts$l_irp_que_empty; /* Number of times the IRP queue was empty */p unsignIIed int rmstts$l_irp_que_empty_col; /* Number of times the IRP queue was empty since last collection */N unsigned int rmstts$l_irp_que_rsvd; /* Reserved for quadword alignment */ unsigned char rmstts$b_rcv_data_unk_pkt_type; /* Number of unknown packet types going through AMDS$RM_RECEIVE_DATA routine */ unsigned char rmstts$b_rcv_data_ctl_pkt_type; /* Number of control packet type going through AMDS$RM_RECEIVE_DATA routine */+ unsigned char rmstts$b_rcv_data_rsvd03;+ unsigned cJIhar rmstts$b_rcv_data_rsvd04;R unsigned int rmstts$l_rcv_data_reserved; /* Reserved for quadword alignment */\ unsigned int rmstts$l_rcv_vcrp_immed_cnt; /* Receive VCRP immediately processed count */Y unsigned int rmstts$l_rcv_vcrp_qud_cnt; /* Receive VCRP queued to VCRP queue count */a unsigned int rmstts$l_rcv_vcrp_qud_cmpl_cnt; /* Receive VCRP dequeued for processing count */a unsigned int rmstts$l_rcv_vcrp_not_qud_cnt; /* Receive VCRP not queued to VCRP queue count */ KIunsigned short int rmstts$w_rcv_vcrp_immed_cntco; /* Receive VCRP local immediately processed count since last collection */w unsigned short int rmstts$w_rcv_vcrp_qud_cntco; /* Receive VCRP queued to VCRP queue count since last collection */~ unsigned short int rmstts$w_rcv_vcrp_qud_cmplcntco; /* Receive VCRP dequeued for processing count since last collection */ unsigned short int rmstts$w_rcv_vcrp_not_qud_cntco; /* Receive VCRP not queued to VCRP queue count since last collection */gLI unsigned short int rmstts$w_rcv_vcrp_qud_drop_cnt; /* Receive VCRP dropped from VCRP queue count */~ unsigned short int rmstts$w_rcv_vcrp_qud_dropcntco; /* Receive VCRP dropped from VCRP queue count since last collection */f unsigned short int rmstts$w_rcv_vcrp_flushed_cnt; /* Receive VCRP flushed from VCRP queue count */~ unsigned short int rmstts$w_rcv_vcrp_flushed_cntco; /* Receive VCRP flushed from VCRP queue count since last collection */ unsigned char rmstts$b_rcv_vcrp_qlenMI_max; /* Maximum size of the receive VCRP queue when IRPs are supplied from AM DA/DS */ unsigned char rmstts$b_rcv_vcrp_qlen_cmax; /* Maximum size of the receive VCRP queue when IRPs are supplied from AM DA/DS since\ last collection */ unsigned short int rmstts$w_rcv_vcrp_qlen_curr; /* Current size of the receive VCRP queue when IRPs are supplied from AM DA/DS \*/ unsigned short int rmstts$w_rcv_vcrp_qlen_ave2; /* Average receive VCRP queue size using weight of 2 for exponential aNIverage */ unsigned short int rmstts$w_rcv_vcrp_qlen_ave4; /* Average receive VCRP queue size using weight of 4 for exponential average */ unsigned short int rmstts$w_rcv_vcrp_qlen_ave8; /* Average receive VCRP queue size using weight of 8 for exponential average */ unsigned short int rmstts$w_rcv_vcrp_qlen_ave16; /* Average receive VCRP queue size using weight of 16 for exponential average \*/ unsigned int rmstts$l_rcv_vcrp_qlen_ave32; /* Average receive VCRP queue size using OIweight of 32 for exponential average */ unsigned int rmstts$l_rcv_vcrp_qlen_ave128; /* Average receive VCRP queue size using weight of 128 for exponential average */ unsigned int rmstts$l_rcv_vcrp_qlen_ave512; /* Average receive VCRP queue size using weight of 512 for exponential average */ unsigned int rmstts$l_rcv_vcrp_qlen_ave2k; /* Average receive VCRP queue size using weight of 2048 for exponential average */d unsigned int rmstts$l_rcv_vcrp_que_empty; /* Number of times thePI receive VCRP queue was empty */w unsigned int rmstts$l_rcv_vcrp_que_full; /* Number of times the receive VCRP queue was full and VCRP deallocated */ unsigned short int rmstts$w_rcv_vcrp_que_emptyco; /* Number of times the receive VCRP queue was empty since last collection */ unsigned short int rmstts$w_rcv_vcrp_que_fullco; /* Number of times the receive VCRP queue was full and VCRP deallocated since \last collection */ unsigned char rmstts$b_xmt_vcrp_qlen_max; /* Maximum size ofQI the transmit VCRP queue when IRPs are supplied from AM DA/DS */ unsigned char rmstts$b_xmt_vcrp_qlen_cmax; /* Maximum size of the transmit VCRP queue when IRPs are supplied from AM DA/DS sinc\e last collection */ unsigned short int rmstts$w_xmt_vcrp_qlen_curr; /* Current size of the transmit VCRP queue when IRPs are supplied from AM DA/DS\ */ unsigned short int rmstts$w_xmt_vcrp_qlen_ave2; /* Average transmit VCRP queue size using weight of 2 for exponential average */ unsignRIed short int rmstts$w_xmt_vcrp_qlen_ave4; /* Average transmit VCRP queue size using weight of 4 for exponential average */ unsigned short int rmstts$w_xmt_vcrp_qlen_ave8; /* Average transmit VCRP queue size using weight of 8 for exponential average */ unsigned short int rmstts$w_xmt_vcrp_qlen_ave16; /* Average transmit VCRP queue size using weight of 16 for exponential average\ */ unsigned int rmstts$l_xmt_vcrp_qlen_ave32; /* Average transmit VCRP queue size using weight of 32 for exSIponential average */ unsigned int rmstts$l_xmt_vcrp_qlen_ave128; /* Average transmit VCRP queue size using weight of 128 for exponential average */ unsigned int rmstts$l_xmt_vcrp_qlen_ave512; /* Average transmit VCRP queue size using weight of 512 for exponential average */ unsigned int rmstts$l_xmt_vcrp_qlen_ave2k; /* Average transmit VCRP queue size using weight of 2048 for exponential average */x unsigned int rmstts$l_xmt_vcrp_que_empty; /* Number of times the transmit VCRP queueTI was empty and VCRP allocated */x unsigned int rmstts$l_xmt_vcrp_que_full; /* Number of times the transmit VCRP queue was full and VCRP deallocated */ unsigned short int rmstts$w_xmt_vcrp_que_emptyco; /* Number of times the transmit VCRP queue was empty and VCRP allocated since\ last collection */ unsigned short int rmstts$w_xmt_vcrp_que_fullco; /* Number of times the tramsmit VCRP queue was full and VCRP deallocated since\ last collection */l unsigned int rmstts$l_xmt_vcrp_queUI_qued; /* Count of transmit VCRPs queued to the transmit VCRP queue */q unsigned int rmstts$l_xmt_vcrp_que_dqued; /* Count of transmit VCRPs dequeued from the transmit VCRP queue */ unsigned short int rmstts$w_xmt_vcrp_que_quedco; /* Count of transmit VCRPs queued to the transmit VCRP queue since last collec\tion */ unsigned short int rmstts$w_xmt_vcrp_que_dquedco; /* Count of transmit VCRPs dequeued from the transmit VCRP queue since last c\ ollection */R unsigned int rmstts$l_VIxmt_vcrp_que_rsvd; /* Reserved for quadword alignment */y unsigned int rmstts$l_xmt_alo_cl_buf_succ; /* Successful allocations for transmitting CLIST packets to the network */{ unsigned int rmstts$l_xmt_alo_cl_buf_fail; /* Unsuccessful allocations for transmitting CLIST packets to the network */y unsigned int rmstts$l_xmt_alo_hl_buf_succ; /* Successful allocations for transmitting HELLO packets to the network */{ unsigned int rmstts$l_xmt_alo_hl_buf_fail; /* Unsuccessful allocationsWI for transmitting HELLO packets to the network */y unsigned int rmstts$l_xmt_alo_cr_buf_succ; /* Successful allocations for transmitting CRESP packets to the network */{ unsigned int rmstts$l_xmt_alo_cr_buf_fail; /* Unsuccessful allocations for transmitting CRESP packets to the network */ unsigned short int rmstts$w_xmt_alo_cl_buf_succco; /* Successful allocations for transmitting CLIST packets to the network sinc\e last collection */ unsigned short int rmstts$w_xmt_alo_cl_buf_fXIailco; /* Unsuccessful allocations for transmitting CLIST packets to the network si\nce last collection */ unsigned short int rmstts$w_xmt_alo_hl_buf_succco; /* Successful allocations for transmitting HELLO packets to the network sinc\e last collection */ unsigned short int rmstts$w_xmt_alo_hl_buf_failco; /* Unsuccessful allocations for transmitting HELLO packets to the network si\nce last collection */ unsigned short int rmstts$w_xmt_alo_cr_buf_succco; /* Successful allocations fYIor transmitting CRESP packets to the network sinc\e last collection */ unsigned short int rmstts$w_xmt_alo_cr_buf_failco; /* Unsuccessful allocations for transmitting CRESP packets to the network si\nce last collection */Q unsigned int rmstts$l_xmt_alo_reserved; /* Reserved for quadword alignment */ unsigned short int rmstts$w_npp_rm_sec_buf_succ; /* Successful non-paged pool allocations for RMDriver security buffers for sec\urity triplets */ unsigned short int rmstts$w_npp_ZIrm_sec_buf_fail; /* Unsuccessful non-paged pool allocations for RMDriver security buffers for s\ecurity triplets */ unsigned short int rmstts$w_npp_rm_start_buf_succ; /* Successful non-paged pool allocations for RMDriver various misc buffers (\AMDS$RM_ALLOC_START_BUFFERS) */ unsigned short int rmstts$w_npp_rm_start_buf_fail; /* Unsuccessful non-paged pool allocations for RMDriver various misc buffers\! (AMDS$RM_ALLOC_START_BUFFERS) */u unsigned int rmstts$l_npp_rm_xmt_vcrp_succ; [I/* Successful non-paged pool allocations for transmit VXRP packets */w unsigned int rmstts$l_npp_rm_xmt_vcrp_fail; /* Unsuccessful non-paged pool allocations for transmit VXRP packets */ unsigned short int rmstts$w_npp_rm_xmt_vcrp_succco; /* Successful non-paged pool allocations for transmit VXRP packets since la\st collection */ unsigned short int rmstts$w_npp_rm_xmt_vcrp_failco; /* Unsuccessful non-paged pool allocations for transmit VXRP packets since \last collection */P un\Isigned int rmstts$l_npp_rm_reserved; /* Reserved for quadword alignment */l unsigned int rmstts$l_irp_read_and_not_bsy; /* Read IRP put into UCB$L_RM_IRP because busy bit is off */U unsigned int rmstts$l_irp_bsy_after_cancel; /* The busy bit is on after cancel */ unsigned int rmstts$l_no_irp_for_lcl_cresp; /* Number of local CRESP packets queued to receive VCRP queue due to no pending REA\DS from GUI */ unsigned int rmstts$l_dropped_netw_cresps; /* Number of network CRESP packets ]Idropped due to no pending READS from GUI or cance\l I/O */ unsigned int rmstts$l_dropped_local_hellos; /* Number of local HELLO packets dropped due to no pending READS from GUI or cancel\ I/O */ unsigned int rmstts$l_dropped_rem_hellos; /* Number of remote HELLO packets dropped due to no pending READS from GUI or cancel \I/O */P/* Dropped packets are not counted in the packet type and bytes process stats */ unsigned short int rmstts$w_irp_read_and_not_bsyco; /* Read IRP put into^I UCB$L_RM_IRP because busy bit is off since last collec\tion */s unsigned short int rmstts$w_irp_bsy_after_cancelco; /* The busy bit is on after cancel since last collection */ unsigned short int rmstts$w_no_irp_for_lcl_crespco; /* Number of local CRESP packets queued to receive VCRP queue due to no pen\,ding READS from GUI since last collection */ unsigned short int rmstts$w_dropped_netw_crespsco; /* Number of network CRESP packets dropped due to no pending READS from GUI \&or can_Icel I/O since last collection */ unsigned short int rmstts$w_dropped_local_hellosco; /* Number of local HELLO packets dropped due to no pending READS from GUI o\%r cancel I/O since last collection */ unsigned short int rmstts$w_dropped_rem_hellosco; /* Number of remote HELLO packets dropped due to no pending READS from GUI or\$ cancel I/O since last collection */P/* Dropped packets are not counted in the packet type and bytes process stats */N unsigned short int rmstts$w_chk_errs; /*`I Checksum error count */\ unsigned short int rmstts$w_xmt_errs; /* Number of transmit errors (truncated packet) */X unsigned char rmstts$b_chk_errsco; /* Checksum error count since last collection */p unsigned char rmstts$b_xmt_errsco; /* Number of transmit errors (truncated packet) since last collection */Q unsigned char rmstts$b_unknown_pkt_type; /* Unknown AMDS packet type count */~ unsigned char rmstts$b_dropped_local_clists; /* Number of local CLIST packets droppeaId due to device not ready (started) */N unsigned int rmstts$l_misc_reserved; /* Reserved for quadword alignment */R unsigned char rmstts$b_wrt_ios_inprog_max; /* Maximum write IOs in progress */l unsigned char rmstts$b_wrt_ios_inprog_col_max; /* Maximum write IOs in progress since last collection */X unsigned short int rmstts$w_wrt_ios_inprog_curr; /* Current write IOs in progress */ unsigned short int rmstts$w_wrt_ios_inprog_ave2; /* Average write IOs in progress using weight of bI2 for exponential average */ unsigned short int rmstts$w_wrt_ios_inprog_ave4; /* Average write IOs in progress using weight of 4 for exponential average */ unsigned short int rmstts$w_wrt_ios_inprog_ave8; /* Average write IOs in progress using weight of 8 for exponential average */ unsigned short int rmstts$w_wrt_ios_inprog_ave16; /* Average write IOs in progress using weight of 16 for exponential average */~ unsigned int rmstts$l_wrt_ios_inprog_ave32; /* Average write IOs in progrecIss using weight of 32 for exponential average */ unsigned int rmstts$l_wrt_ios_inprog_ave128; /* Average write IOs in progress using weight of 128 for exponential average */ unsigned int rmstts$l_wrt_ios_inprog_ave512; /* Average write IOs in progress using weight of 512 for exponential average */ unsigned int rmstts$l_wrt_ios_inprog_ave2k; /* Average write IOs in progress using weight of 2048 for exponential average */T unsigned int rmstts$l_wrt_ios_inprog_rsvd; /* Reserved for qua dIdword alignment */Y unsigned short int rmstts$w_lan_dll_port_usable; /* Account for various LAN events */6 unsigned short int rmstts$w_lan_dll_port_unusable;/ unsigned char rmstts$b_lan_lan_new_address;2 unsigned char rmstts$b_lan_lan_rcv_congestion;0 unsigned char rmstts$b_lan_lan_rcv_pdu_lost;N unsigned char rmstts$b_lan_syn_statn_deleted; /* SYN_STATION_DELETED */2 unsigned char rmstts$b_lan_x25_incoming_reset;2 unsigned char rmstts$b_lan_x25_incoming_nocom;0 eI unsigned char rmstts$b_lan_lan_restart_fail;N unsigned char rmstts$b_lan_lan_statn_renamed; /* LAN_STATION_RENAMED */1 unsigned char rmstts$b_lan_lan_rcvbuf_change;( unsigned char rmstts$b_lan_dll_last;N unsigned char rmstts$b_lan_dll_pref_cpu_chngd; /* DLL_PREF_CPU_CHANGED */^ unsigned char rmstts$b_lan_dll_unknown_value; /* Catch-all for values not defined above */t unsigned int rmstts$l_lan_dll_last_unk_value; /* Last unknown event code value returned by LAN event calfIlback */N unsigned int rmstts$l_lan_rsvd1; /* Reserve one cells for later use */Z unsigned int rmstts$l_lan_dll_event_index; /* Point to current entry in ring buffer */U unsigned int rmstts$l_tqe_exec_index; /* Point to current entry in ring buffer */2 unsigned int rmstts$al_lan_dll_port_event [8];N/* LAN DLL port event passed into LAN report event callback routine */3 unsigned int rmstts$al_lan_dll_port_reason [8];N/* LAN DLL port reason passed into LAN report even gIt callback routine */2 unsigned int rmstts$al_lan_dll_ucb_devsts [8];N/* RMDriver UCB DEVSTS within LAN callback routine */2 unsigned char rmstts$ab_lan_dll_phy_cpuid [8];N/* CPU physical ID within LAN callback routine */7 unsigned __int64 rmstts$aq_lan_dll_system_time [8];N/* System time within LAN callback routine */3 unsigned int rmstts$al_tqe_exec_ucb_devsts [8];N/* RMDriver UCB DEVShITS within TQE routine */3 unsigned char rmstts$ab_tqe_exec_phy_cpuid [8];N/* CPU physical ID within TQE routine */8 unsigned __int64 rmstts$aq_tqe_exec_system_time [8];N/* System time within TQE routine */\ unsigned short int rmstts$w_fetch_qlen_max; /* Maximum number of fetches in the queue */v unsigned short int rmstts$w_fetch_qlen_col_max; /* Maximum number of fetchesiI in the queue since last collection */] unsigned short int rmstts$w_fetch_qlen_curr; /* Current number of fetches in the queue */ unsigned short int rmstts$w_fetch_qlen_ave2; /* Average number of fetches in the queue using weight of 2 for exponential averag\e */ unsigned short int rmstts$w_fetch_qlen_ave4; /* Average number of fetches in the queue using weight of 4 for exponential averag\e */ unsigned short int rmstts$w_fetch_qlen_ave8; /* Average number of fetches in the queuejI using weight of 8 for exponential averag\e */ unsigned int rmstts$l_fetch_qlen_ave16; /* Average number of fetches in the queue using weight of 16 for exponential average */ unsigned int rmstts$l_fetch_qlen_ave32; /* Average number of fetches in the queue using weight of 32 for exponential average */ unsigned int rmstts$l_fetch_qlen_ave128; /* Average number of fetches in the queue using weight of 128 for exponential average \*/ unsigned int rmstts$l_fetch_qlen_ave512; /* AvkIerage number of fetches in the queue using weight of 512 for exponential average \*/ unsigned int rmstts$l_fetch_qlen_ave2k; /* Average number of fetches in the queue using weight of 2K for exponential average */ unsigned short int rmstts$w_fetch_timeouts; /* Number of TRAP results that timed out before a FETCH was received for the result\s */t unsigned short int rmstts$w_fetch_mismatches; /* Number of FETCHes received that didn't have a valid FETCH ID */N unsigned int rmstts$l_lIfetch_rsvd; /* Reserved for quadword alignment */N unsigned int rmstts$l_fetches_queued; /* Number of fetches queued */Y unsigned int rmstts$l_fetches_executed; /* Number of fetches successfully executed */[ unsigned int rmstts$l_fetches_incomplete; /* Number of fetches for incompleted TRAPs */N unsigned int rmstts$l_fetches_rsvd; /* Reserved for quadword alignment */\ unsigned int rmstts$l_hellos_sent; /* Number of Hello packets sent by local RMDriver */c unsignedmI int rmstts$l_hellos_received; /* Number of Hello packets received by local RMDriver */n unsigned int rmstts$l_hello_local_packets_in; /* Number of Hello packets by local RMDriver to local GUI */m unsigned int rmstts$l_hello_rem_packets_in; /* Number of Hello packets by remote RMDriver to local GUI */j unsigned __int64 rmstts$q_hello_bytes_received; /* Number of Hello bytes received by local RMDriver */w unsigned __int64 rmstts$q_hello_local_bytes_in; /* Number of Hello bytes receivenId by local RMDriver to local GUI */u unsigned __int64 rmstts$q_hello_rem_bytes_in; /* Number of Hello bytes received by local RMDriver to local GUI */t unsigned int rmstts$l_local_clist_packets; /* Number of CLIST packets processed for local GUI (local request) */t unsigned int rmstts$l_netw_clist_packets; /* Number of CLIST packets processed for local GUI (remote request) */c unsigned int rmstts$l_rem_clist_packets; /* Number of CLIST packets processed for remote GUI */t unsignoIed int rmstts$l_local_cresp_packets; /* Number of CRESP packets processed for local GUI (local request) */t unsigned int rmstts$l_netw_cresp_packets; /* Number of CRESP packets processed for local GUI (remote request) */c unsigned int rmstts$l_rem_cresp_packets; /* Number of CRESP packets processed for remote GUI */T unsigned int rmstts$l_control_packets; /* Number of CONTROL packets processed */^ unsigned int rmstts$l_rm_events_sent; /* Number of event notifications sent by RMDriver pI*/ unsigned int rmstts$l_local_packets_in; /* Number of local packets received by RMDriver for local GUI (including HELLOs receive\d) */p unsigned int rmstts$l_local_packets_out; /* Number of local packets transmitted by RMDriver for local GUI */k unsigned __int64 rmstts$q_local_bytes_in; /* Number of bytes received in local packets for local GUI */o unsigned __int64 rmstts$q_local_bytes_out; /* Number of bytes transmitted in local packets for local GUI */m unsigned int rmsttqIs$l_netw_packets_in; /* Number of network packets received by RMDriver for local GUI */q unsigned int rmstts$l_netw_packets_out; /* Number of network packets transmitted by RMDriver for local GUI */l unsigned __int64 rmstts$q_netw_bytes_in; /* Number of bytes received in network packets for local GUI */p unsigned __int64 rmstts$q_netw_bytes_out; /* Number of bytes transmitted in network packets for local GUI */m unsigned int rmstts$l_rem_packets_in; /* Number of network packets receirIved by RMDriver for remote GUI */q unsigned int rmstts$l_rem_packets_out; /* Number of network packets transmitted by RMDriver for remote GUI */l unsigned __int64 rmstts$q_rem_bytes_in; /* Number of bytes received in network packets for remote GUI */p unsigned __int64 rmstts$q_rem_bytes_out; /* Number of bytes transmitted in network packets for remote GUI */W unsigned int rmstts$l_rmo_requests; /* Number of requests via RMDriver interface */n unsigned int rmstts$l_rmo_arg_errorssI; /* Number of argument errors from requests via RMDriver interface */q unsigned int rmstts$l_rmo_align_errors; /* Number of alignment errors from requests via RMDriver interface */l unsigned int rmstts$l_rmo_fmt_errors; /* Number of format errors from requests via RMDriver interface */q unsigned int rmstts$l_rmo_proc_errors; /* Number of processing errors from requests via RMDriver interface */N unsigned int rmstts$l_rmo_rsvd; /* Reserved (quadword alignment) */t unsignedtI __int64 rmstts$q_rmo_request_bytes; /* Number of bytes processed for requests via RMDriver interface */v unsigned __int64 rmstts$q_rmo_response_bytes; /* Number of bytes processed for responses via RMDriver interface */] unsigned int rmstts$l_kmo_requests; /* Number of requests via kernel-mode MO interface */t unsigned int rmstts$l_kmo_arg_errors; /* Number of argument errors from requests via kernel-mode MO interface */w unsigned int rmstts$l_kmo_align_errors; /* Number of alignmentuI errors from requests via kernel-mode MO interface */r unsigned int rmstts$l_kmo_fmt_errors; /* Number of format errors from requests via kernel-mode MO interface */w unsigned int rmstts$l_kmo_proc_errors; /* Number of processing errors from requests via kernel-mode MO interface */N unsigned int rmstts$l_kmo_rsvd; /* Reserved (quadword alignment) */z unsigned __int64 rmstts$q_kmo_request_bytes; /* Number of bytes processed for requests via kernel-mode MO interface */| unsivIgned __int64 rmstts$q_kmo_response_bytes; /* Number of bytes processed for responses via kernel-mode MO interface */[ unsigned int rmstts$l_umo_requests; /* Number of requests via user-mode MO interface */r unsigned int rmstts$l_umo_arg_errors; /* Number of argument errors from requests via user-mode MO interface */u unsigned int rmstts$l_umo_align_errors; /* Number of alignment errors from requests via user-mode MO interface */p unsigned int rmstts$l_umo_fmt_errors; /* Number of forwImat errors from requests via user-mode MO interface */u unsigned int rmstts$l_umo_proc_errors; /* Number of processing errors from requests via user-mode MO interface */N unsigned int rmstts$l_umo_rsvd; /* Reserved (quadword alignment) */x unsigned __int64 rmstts$q_umo_request_bytes; /* Number of bytes processed for requests via user-mode MO interface */z unsigned __int64 rmstts$q_umo_response_bytes; /* Number of bytes processed for responses via user-mode MO interface */Y xIunsigned int rmstts$l_nda_requests; /* Number of requests via network DA interface */p unsigned int rmstts$l_nda_arg_errors; /* Number of argument errors from requests via network DA interface */s unsigned int rmstts$l_nda_align_errors; /* Number of alignment errors from requests via network DA interface */N/* This is not an error in this case, but record the number of adjustments */n unsigned int rmstts$l_nda_fmt_errors; /* Number of format errors from requests via network DA interfacyIe */s unsigned int rmstts$l_nda_proc_errors; /* Number of processing errors from requests via network DA interface */N unsigned int rmstts$l_nds_rsvd; /* Reserved (quadword alignment) */v unsigned __int64 rmstts$q_nda_request_bytes; /* Number of bytes processed for requests via network DA interface */x unsigned __int64 rmstts$q_nda_response_bytes; /* Number of bytes processed for responses via network DA interface */W unsigned int rmstts$l_lda_requests; /* Number of requestzIs via local DA interface */n unsigned int rmstts$l_lda_arg_errors; /* Number of argument errors from requests via local DA interface */q unsigned int rmstts$l_lda_align_errors; /* Number of alignment errors from requests via local DA interface */l unsigned int rmstts$l_lda_fmt_errors; /* Number of format errors from requests via local DA interface */q unsigned int rmstts$l_lda_proc_errors; /* Number of processing errors from requests via local DA interface */N unsigned int rmstt{Is$l_lda_rsvd; /* Reserved (quadword alignment) */t unsigned __int64 rmstts$q_lda_request_bytes; /* Number of bytes processed for requests via local DA interface */v unsigned __int64 rmstts$q_lda_response_bytes; /* Number of bytes processed for responses via local DA interface */T unsigned __int64 rmstts$q_end_marker; /* Marks the end of this data structure */ } RMSTTS;N/* */N/* RMDRIVER performance data|I from GET_RM_PERFORMANCE_STATS request */N/* */N/* This structure represents data for Managed Object Parameter version 1.1 */N/* */N/* */N/* AVEn calculation notes */N/* }I */N/* The AVEn calculation is based on shifted values. */N/* For instance, AVE4 is based on a value that is */N/* shifted left 2 bits for its internal format. */N/* The maximum value for a longword is the number */N/* of bits in the maximum value plus the number of */N/* bits of the left shift. */N~I/* */N/* For all the metrics to fit in a standard */N/* Ethernet packet, the AVEn values must fit */N/* in a longword up to and including AVE128. */N/* To allow AVE128 values to fit in a longword, */N/* the maximum number of bits for the value is */N/* 32 bits for a longworId minus 7 bits for the */N/* left shift amount to get 25 bits. Thus the */N/* maximum value is ^X01FFFFFF. In 100ns tics, */N/* this value is 33,554,431, which is a bit over */N/* 3.3 seconds. This seems long, but it may */N/* have been exceeded, causing the TQE crash in */N/* RM_VCI.MAR edit X-38. The minimum interval I */N/* for the HELLO messages in X-38 is 5 seconds. */N/* Not sure how this affects things like */N/* FORKLOCKs, but account for this possibility */N/* just in case. */N/* *//#define RMPFST$K_RM_AVE_CALC_MAX_VALUE 33554431N/* Collection-related statiIstics */X#define RMPFST$K_RM_PF_STAT_DATA_LENGTH 1408 /* RM performance statistics data length */N#define RMPFST$C_RM_PF_STAT_DATA_LENGTH 1408 /* Old VAX style length */ typedef struct _rmpfst {Z unsigned int rmpfst$l_stat_resets; /* Number of resets to zero on these statistics */P unsigned int rmpfst$l_col_count; /* Count of collections for this data */S unsigned __int64 rmpfst$q_stat_reset_time; /* Time that the stats were resetI */ unsigned int rmpfst$l_prev_col_time_delta; /* Time of previous data collection (affects *COLL_* variables) (delta from curr tim\e) */[ unsigned int rmpfst$l_cpu_cycles_ohns; /* CPU hardware/software cycles per 100ns tic */n unsigned __int64 rmpfst$q_curr_col_time; /* Time of current data collection (affects *COLL_* variables) */~ unsigned __int64 rmpfst$q_cpu_cycles_sec_hwrpb; /* Current CPU cycles per second - IA64/Alpha HWRPB$IQ_CYCLE_COUNT_FREQ */t unsigned __int64 rmpIfst$q_cpu_cycles_sec_slot; /* Current CPU cycles per second - IA64 SLOT$IQ_BASE_PROC_FREQ */m unsigned __int64 rmpfst$q_cpu_cycles_sec_itc; /* Current CPU cycles per second - IA64 SLOT$IQ_ITC_FREQ */N/* Code path performance statistics */I/* Stats for processing Local HELLO packets */N unsigned int rmpfst$l_lcl_hello_count; /* Count included in statistics */g unsigned int rmpfst$l_lcl_hello_col_count; /* Count includedI in statistics since last collection */| unsigned short int rmpfst$w_lcl_hello_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_lcl_hello_ave_col_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value since\ last collection */u unsigned int rmpfst$l_lcl_hello_ohns_min; /* Minimum number of 100ns tics used to process a local HELLO packet */ unsigned int rmpfst$l_lcl_hello_ohns_col_min; /* Minimum nIumber of 100ns tics used to process a local HELLO packet since last c\ ollection */u unsigned int rmpfst$l_lcl_hello_ohns_max; /* Maximum number of 100ns tics used to process a local HELLO packet */ unsigned int rmpfst$l_lcl_hello_ohns_col_max; /* Maximum number of 100ns tics used to process a local HELLO packet since last c\ ollection */v unsigned int rmpfst$l_lcl_hello_ohns_curr; /* Current number of 100ns tics used to process a local HELLO packet */ unsigned int rmpfst$l_lcl_heIllo_ohns_ave2; /* Average number of 100ns tics used to process a local HELLO packet using weight of\ 2 for exponential average */ unsigned int rmpfst$l_lcl_hello_ohns_ave4; /* Average number of 100ns tics used to process a local HELLO packet using weight of\ 4 for exponential average */ unsigned int rmpfst$l_lcl_hello_ohns_ave8; /* Average number of 100ns tics used to process a local HELLO packet using weight of\ 8 for exponential average */ unsigned int rmpfst$l_lcl_hello_ohnsI_ave16; /* Average number of 100ns tics used to process a local HELLO packet using weight o\f 16 for exponential average */ unsigned int rmpfst$l_lcl_hello_ohns_ave32; /* Average number of 100ns tics used to process a local HELLO packet using weight o\f 32 for exponential average */ unsigned int rmpfst$l_lcl_hello_ohns_ave128; /* Average number of 100ns tics used to process a local HELLO packet using weight \!of 128 for exponential average */ unsigned __int64 rmpfst$q_lcl_hello_Iohns_ave512; /* Average number of 100ns tics used to process a local HELLO packet using wei\%ght of 512 for exponential average */ unsigned __int64 rmpfst$q_lcl_hello_ohns_ave2k; /* Average number of 100ns tics used to process a local HELLO packet using weig\%ht of 2048 for exponential average */i unsigned __int64 rmpfst$q_lcl_hello_scc_curr; /* Current SCC value to process a local HELLO packet */[ unsigned __int64 rmpfst$q_lcl_hello_scc_total; /* Total SCC count for this code path *I/r unsigned __int64 rmpfst$q_lcl_hello_scc_ctotal; /* Total SCC count for this code path since last collection */I/* Stats for processing Remote HELLO packets */N unsigned int rmpfst$l_rem_hello_count; /* Count included in statistics */g unsigned int rmpfst$l_rem_hello_col_count; /* Count included in statistics since last collection */| unsigned short int rmpfst$w_rem_hello_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */I unsigned short int rmpfst$w_rem_hello_ave_col_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value since\ last collection */v unsigned int rmpfst$l_rem_hello_ohns_min; /* Minimum number of 100ns tics used to process a remote HELLO packet */ unsigned int rmpfst$l_rem_hello_ohns_col_min; /* Minimum number of 100ns tics used to process a remote HELLO packet since last \ collection */v unsigned int rmpfst$l_rem_hello_ohns_max; /* Maximum number of 100ns tics Iused to process a remote HELLO packet */ unsigned int rmpfst$l_rem_hello_ohns_col_max; /* Maximum number of 100ns tics used to process a remote HELLO packet since last \ collection */w unsigned int rmpfst$l_rem_hello_ohns_curr; /* Current number of 100ns tics used to process a remote HELLO packet */ unsigned int rmpfst$l_rem_hello_ohns_ave2; /* Average number of 100ns tics used to process a remote HELLO packet using weight o\f 2 for exponential average */ unsigned int rmpfst$l_Irem_hello_ohns_ave4; /* Average number of 100ns tics used to process a remote HELLO packet using weight o\f 4 for exponential average */ unsigned int rmpfst$l_rem_hello_ohns_ave8; /* Average number of 100ns tics used to process a remote HELLO packet using weight o\f 8 for exponential average */ unsigned int rmpfst$l_rem_hello_ohns_ave16; /* Average number of 100ns tics used to process a remote HELLO packet using weight \ of 16 for exponential average */ unsigned int rmpfst$l_rem_heIllo_ohns_ave32; /* Average number of 100ns tics used to process a remote HELLO packet using weight \ of 32 for exponential average */ unsigned int rmpfst$l_rem_hello_ohns_ave128; /* Average number of 100ns tics used to process a remote HELLO packet using weight\" of 128 for exponential average */ unsigned __int64 rmpfst$q_rem_hello_ohns_ave512; /* Average number of 100ns tics used to process a remote HELLO packet using we\&ight of 512 for exponential average */ unsigned __int64 rmpfsIt$q_rem_hello_ohns_ave2k; /* Average number of 100ns tics used to process a remote HELLO packet using wei\&ght of 2048 for exponential average */j unsigned __int64 rmpfst$q_rem_hello_scc_curr; /* Current SCC value to process a remote HELLO packet */[ unsigned __int64 rmpfst$q_rem_hello_scc_total; /* Total SCC count for this code path */r unsigned __int64 rmpfst$q_rem_hello_scc_ctotal; /* Total SCC count for this code path since last collection */I/* Stats for transmitting HELLO packets I */N unsigned int rmpfst$l_xmt_hello_count; /* Count included in statistics */g unsigned int rmpfst$l_xmt_hello_col_count; /* Count included in statistics since last collection */| unsigned short int rmpfst$w_xmt_hello_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_xmt_hello_ave_col_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value since\ last collection */p I unsigned int rmpfst$l_xmt_hello_ohns_min; /* Minimum number of 100ns tics used to transmit a HELLO packet */ unsigned int rmpfst$l_xmt_hello_ohns_col_min; /* Minimum number of 100ns tics used to transmit a HELLO packet since last collec\tion */p unsigned int rmpfst$l_xmt_hello_ohns_max; /* Maximum number of 100ns tics used to transmit a HELLO packet */ unsigned int rmpfst$l_xmt_hello_ohns_col_max; /* Maximum number of 100ns tics used to transmit a HELLO packet since last collec\tiIon */q unsigned int rmpfst$l_xmt_hello_ohns_curr; /* Current number of 100ns tics used to transmit a HELLO packet */ unsigned int rmpfst$l_xmt_hello_ohns_ave2; /* Average number of 100ns tics used to transmit a HELLO packet using weight of 2 fo\r exponential average */ unsigned int rmpfst$l_xmt_hello_ohns_ave4; /* Average number of 100ns tics used to transmit a HELLO packet using weight of 4 fo\r exponential average */ unsigned int rmpfst$l_xmt_hello_ohns_ave8; /* Average numbIer of 100ns tics used to transmit a HELLO packet using weight of 8 fo\r exponential average */ unsigned int rmpfst$l_xmt_hello_ohns_ave16; /* Average number of 100ns tics used to transmit a HELLO packet using weight of 16 \for exponential average */ unsigned int rmpfst$l_xmt_hello_ohns_ave32; /* Average number of 100ns tics used to transmit a HELLO packet using weight of 32 \for exponential average */ unsigned int rmpfst$l_xmt_hello_ohns_ave128; /* Average number of 100ns tics useId to transmit a HELLO packet using weight of 12\8 for exponential average */ unsigned __int64 rmpfst$q_xmt_hello_ohns_ave512; /* Average number of 100ns tics used to transmit a HELLO packet using weight o\ f 512 for exponential average */ unsigned __int64 rmpfst$q_xmt_hello_ohns_ave2k; /* Average number of 100ns tics used to transmit a HELLO packet using weight of\ 2048 for exponential average */d unsigned __int64 rmpfst$q_xmt_hello_scc_curr; /* Current SCC value to transmit a HELLOI packet */[ unsigned __int64 rmpfst$q_xmt_hello_scc_total; /* Total SCC count for this code path */r unsigned __int64 rmpfst$q_xmt_hello_scc_ctotal; /* Total SCC count for this code path since last collection */I/* Stats for processing Local CLIST packets */N unsigned int rmpfst$l_lcl_clist_count; /* Count included in statistics */g unsigned int rmpfst$l_lcl_clist_col_count; /* Count included in statistics since last collection */| unsigned short intI rmpfst$w_lcl_clist_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_lcl_clist_ave_col_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value since\ last collection */u unsigned int rmpfst$l_lcl_clist_ohns_min; /* Minimum number of 100ns tics used to process a local CLIST packet */ unsigned int rmpfst$l_lcl_clist_ohns_col_min; /* Minimum number of 100ns tics used to process a local CLIST packet since lIast c\ ollection */u unsigned int rmpfst$l_lcl_clist_ohns_max; /* Maximum number of 100ns tics used to process a local CLIST packet */ unsigned int rmpfst$l_lcl_clist_ohns_col_max; /* Maximum number of 100ns tics used to process a local CLIST packet since last c\ ollection */v unsigned int rmpfst$l_lcl_clist_ohns_curr; /* Current number of 100ns tics used to process a local CLIST packet */ unsigned int rmpfst$l_lcl_clist_ohns_ave2; /* Average number of 100ns tics used to process aI local CLIST packet using weight of\ 2 for exponential average */ unsigned int rmpfst$l_lcl_clist_ohns_ave4; /* Average number of 100ns tics used to process a local CLIST packet using weight of\ 4 for exponential average */ unsigned int rmpfst$l_lcl_clist_ohns_ave8; /* Average number of 100ns tics used to process a local CLIST packet using weight of\ 8 for exponential average */ unsigned int rmpfst$l_lcl_clist_ohns_ave16; /* Average number of 100ns tics used to process a local ICLIST packet using weight o\f 16 for exponential average */ unsigned int rmpfst$l_lcl_clist_ohns_ave32; /* Average number of 100ns tics used to process a local CLIST packet using weight o\f 32 for exponential average */ unsigned int rmpfst$l_lcl_clist_ohns_ave128; /* Average number of 100ns tics used to process a local CLIST packet using weight \!of 128 for exponential average */ unsigned __int64 rmpfst$q_lcl_clist_ohns_ave512; /* Average number of 100ns tics used to process a lIocal CLIST packet using wei\%ght of 512 for exponential average */ unsigned __int64 rmpfst$q_lcl_clist_ohns_ave2k; /* Average number of 100ns tics used to process a local CLIST packet using weig\%ht of 2048 for exponential average */i unsigned __int64 rmpfst$q_lcl_clist_scc_curr; /* Current SCC value to process a local CLIST packet */[ unsigned __int64 rmpfst$q_lcl_clist_scc_total; /* Total SCC count for this code path */r unsigned __int64 rmpfst$q_lcl_clist_scc_ctotal; /* TotalI SCC count for this code path since last collection */I/* Stats for processing Remote CLIST packets */N unsigned int rmpfst$l_rem_clist_count; /* Count included in statistics */g unsigned int rmpfst$l_rem_clist_col_count; /* Count included in statistics since last collection */| unsigned short int rmpfst$w_rem_clist_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_rem_clist_ave_col_ovfl; /* CouInt of current 100ns tics is greater than the AVEn maximum value since\ last collection */v unsigned int rmpfst$l_rem_clist_ohns_min; /* Minimum number of 100ns tics used to process a remote CLIST packet */ unsigned int rmpfst$l_rem_clist_ohns_col_min; /* Minimum number of 100ns tics used to process a remote CLIST packet since last \ collection */v unsigned int rmpfst$l_rem_clist_ohns_max; /* Maximum number of 100ns tics used to process a remote CLIST packet */ unsigned int rmpfsIt$l_rem_clist_ohns_col_max; /* Maximum number of 100ns tics used to process a remote CLIST packet since last \ collection */w unsigned int rmpfst$l_rem_clist_ohns_curr; /* Current number of 100ns tics used to process a remote CLIST packet */ unsigned int rmpfst$l_rem_clist_ohns_ave2; /* Average number of 100ns tics used to process a remote CLIST packet using weight o\f 2 for exponential average */ unsigned int rmpfst$l_rem_clist_ohns_ave4; /* Average number of 100ns tics used to proIcess a remote CLIST packet using weight o\f 4 for exponential average */ unsigned int rmpfst$l_rem_clist_ohns_ave8; /* Average number of 100ns tics used to process a remote CLIST packet using weight o\f 8 for exponential average */ unsigned int rmpfst$l_rem_clist_ohns_ave16; /* Average number of 100ns tics used to process a remote CLIST packet using weight \ of 16 for exponential average */ unsigned int rmpfst$l_rem_clist_ohns_ave32; /* Average number of 100ns tics used to process Ia remote CLIST packet using weight \ of 32 for exponential average */ unsigned int rmpfst$l_rem_clist_ohns_ave128; /* Average number of 100ns tics used to process a remote CLIST packet using weight\" of 128 for exponential average */ unsigned __int64 rmpfst$q_rem_clist_ohns_ave512; /* Average number of 100ns tics used to process a remote CLIST packet using we\&ight of 512 for exponential average */ unsigned __int64 rmpfst$q_rem_clist_ohns_ave2k; /* Average number of 100ns tics used tIo process a remote CLIST packet using wei\&ght of 2048 for exponential average */j unsigned __int64 rmpfst$q_rem_clist_scc_curr; /* Current SCC value to process a remote CLIST packet */[ unsigned __int64 rmpfst$q_rem_clist_scc_total; /* Total SCC count for this code path */r unsigned __int64 rmpfst$q_rem_clist_scc_ctotal; /* Total SCC count for this code path since last collection */I/* Stats for processing Transmit CLIST packets */N unsigned int rmpfst$l_xmIt_clist_count; /* Count included in statistics */g unsigned int rmpfst$l_xmt_clist_col_count; /* Count included in statistics since last collection */| unsigned short int rmpfst$w_xmt_clist_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_xmt_clist_ave_col_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value since\ last collection */p unsigned int rmpfst$l_xmt_clist_ohns_min; /* Minimum number ofI 100ns tics used to transmit a CLIST packet */ unsigned int rmpfst$l_xmt_clist_ohns_col_min; /* Minimum number of 100ns tics used to transmit a CLIST packet since last collec\tion */p unsigned int rmpfst$l_xmt_clist_ohns_max; /* Maximum number of 100ns tics used to transmit a CLIST packet */ unsigned int rmpfst$l_xmt_clist_ohns_col_max; /* Maximum number of 100ns tics used to transmit a CLIST packet since last collec\tion */q unsigned int rmpfst$l_xmt_clist_ohns_curr; /* CurrenIt number of 100ns tics used to transmit a CLIST packet */ unsigned int rmpfst$l_xmt_clist_ohns_ave2; /* Average number of 100ns tics used to transmit a CLIST packet using weight of 2 fo\r exponential average */ unsigned int rmpfst$l_xmt_clist_ohns_ave4; /* Average number of 100ns tics used to transmit a CLIST packet using weight of 4 fo\r exponential average */ unsigned int rmpfst$l_xmt_clist_ohns_ave8; /* Average number of 100ns tics used to transmit a CLIST packet using weight ofI 8 fo\r exponential average */ unsigned int rmpfst$l_xmt_clist_ohns_ave16; /* Average number of 100ns tics used to transmit a CLIST packet using weight of 16 \for exponential average */ unsigned int rmpfst$l_xmt_clist_ohns_ave32; /* Average number of 100ns tics used to transmit a CLIST packet using weight of 32 \for exponential average */ unsigned int rmpfst$l_xmt_clist_ohns_ave128; /* Average number of 100ns tics used to transmit a CLIST packet using weight of 12\8 for exponentIial average */ unsigned __int64 rmpfst$q_xmt_clist_ohns_ave512; /* Average number of 100ns tics used to transmit a CLIST packet using weight o\ f 512 for exponential average */ unsigned __int64 rmpfst$q_xmt_clist_ohns_ave2k; /* Average number of 100ns tics used to transmit a CLIST packet using weight of\ 2048 for exponential average */d unsigned __int64 rmpfst$q_xmt_clist_scc_curr; /* Current SCC value to transmit a CLIST packet */[ unsigned __int64 rmpfst$q_xmt_clist_scc_total; /I* Total SCC count for this code path */r unsigned __int64 rmpfst$q_xmt_clist_scc_ctotal; /* Total SCC count for this code path since last collection */I/* Stats for processing Remote CRESP packets */N unsigned int rmpfst$l_rem_cresp_count; /* Count included in statistics */g unsigned int rmpfst$l_rem_cresp_col_count; /* Count included in statistics since last collection */| unsigned short int rmpfst$w_rem_cresp_ave_ovfl; /* Count of current 100ns tics is Igreater than the AVEn maximum value */ unsigned short int rmpfst$w_rem_cresp_ave_col_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value since\ last collection */v unsigned int rmpfst$l_rem_cresp_ohns_min; /* Minimum number of 100ns tics used to process a remote CRESP packet */ unsigned int rmpfst$l_rem_cresp_ohns_col_min; /* Minimum number of 100ns tics used to process a remote CRESP packet since last \ collection */v unsigned int rmpfst$l_rem_cresp_ohnsI_max; /* Maximum number of 100ns tics used to process a remote CRESP packet */ unsigned int rmpfst$l_rem_cresp_ohns_col_max; /* Maximum number of 100ns tics used to process a remote CRESP packet since last \ collection */w unsigned int rmpfst$l_rem_cresp_ohns_curr; /* Current number of 100ns tics used to process a remote CRESP packet */ unsigned int rmpfst$l_rem_cresp_ohns_ave2; /* Average number of 100ns tics used to process a remote CRESP packet using weight o\f 2 for exponential Iaverage */ unsigned int rmpfst$l_rem_cresp_ohns_ave4; /* Average number of 100ns tics used to process a remote CRESP packet using weight o\f 4 for exponential average */ unsigned int rmpfst$l_rem_cresp_ohns_ave8; /* Average number of 100ns tics used to process a remote CRESP packet using weight o\f 8 for exponential average */ unsigned int rmpfst$l_rem_cresp_ohns_ave16; /* Average number of 100ns tics used to process a remote CRESP packet using weight \ of 16 for exponential averagIe */ unsigned int rmpfst$l_rem_cresp_ohns_ave32; /* Average number of 100ns tics used to process a remote CRESP packet using weight \ of 32 for exponential average */ unsigned int rmpfst$l_rem_cresp_ohns_ave128; /* Average number of 100ns tics used to process a remote CRESP packet using weight\" of 128 for exponential average */ unsigned __int64 rmpfst$q_rem_cresp_ohns_ave512; /* Average number of 100ns tics used to process a remote CRESP packet using we\&ight of 512 for exponential Iaverage */ unsigned __int64 rmpfst$q_rem_cresp_ohns_ave2k; /* Average number of 100ns tics used to process a remote CRESP packet using wei\&ght of 2048 for exponential average */j unsigned __int64 rmpfst$q_rem_cresp_scc_curr; /* Current SCC value to process a remote CRESP packet */[ unsigned __int64 rmpfst$q_rem_cresp_scc_total; /* Total SCC count for this code path */r unsigned __int64 rmpfst$q_rem_cresp_scc_ctotal; /* Total SCC count for this code path since last collection */N/*I Routine performance statistics */I/* Stats for aquiring the RMDriver forklock from all codepaths */N unsigned int rmpfst$l_frkl_count; /* Count included in statistics */b unsigned int rmpfst$l_frkl_col_count; /* Count included in statistics since last collection */w unsigned short int rmpfst$w_frkl_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_frkl_ave_col_ovfl;I /* Count of current 100ns tics is greater than the AVEn maximum value since last\ collection */q unsigned int rmpfst$l_frkl_ohns_min; /* Minimum number of 100ns tics used to acquire the RMDriver forklock */ unsigned int rmpfst$l_frkl_ohns_col_min; /* Minimum number of 100ns tics used to acquire the RMDriver forklock since last colle\ction */q unsigned int rmpfst$l_frkl_ohns_max; /* Maximum number of 100ns tics used to acquire the RMDriver forklock */ unsigned int rmpfst$l_frklI_ohns_col_max; /* Maximum number of 100ns tics used to acquire the RMDriver forklock since last colle\ction */r unsigned int rmpfst$l_frkl_ohns_curr; /* Current number of 100ns tics used to acquire the RMDriver forklock */ unsigned int rmpfst$l_frkl_ohns_ave2; /* Average number of 100ns tics used to acquire the RMDriver forklock using weight of 2 f\or exponential average */ unsigned int rmpfst$l_frkl_ohns_ave4; /* Average number of 100ns tics used to acquire the RMDriver forklock usIing weight of 4 f\or exponential average */ unsigned int rmpfst$l_frkl_ohns_ave8; /* Average number of 100ns tics used to acquire the RMDriver forklock using weight of 8 f\or exponential average */ unsigned int rmpfst$l_frkl_ohns_ave16; /* Average number of 100ns tics used to acquire the RMDriver forklock using weight of 16\ for exponential average */ unsigned int rmpfst$l_frkl_ohns_ave32; /* Average number of 100ns tics used to acquire the RMDriver forklock using weight of 32\I for exponential average */ unsigned int rmpfst$l_frkl_ohns_ave128; /* Average number of 100ns tics used to acquire the RMDriver forklock using weight of 1\28 for exponential average */ unsigned __int64 rmpfst$q_frkl_ohns_ave512; /* Average number of 100ns tics used to acquire the RMDriver forklock using weight \!of 512 for exponential average */ unsigned __int64 rmpfst$q_frkl_ohns_ave2k; /* Average number of 100ns tics used to acquire the RMDriver forklock using weight o\!f 20I48 for exponential average */e unsigned __int64 rmpfst$q_frkl_scc_curr; /* Current SCC value to acquire the RMDriver forklock */V unsigned __int64 rmpfst$q_frkl_scc_total; /* Total SCC count for this code path */m unsigned __int64 rmpfst$q_frkl_scc_ctotal; /* Total SCC count for this code path since last collection */[/* Stats for AMDS$RM_INIT_PASSWORD_PROCESSOR routine for transmiting local CLIST packets */N unsigned int rmpfst$l_xmt_pwinit_count; /* Count included in statistics I*/h unsigned int rmpfst$l_xmt_pwinit_col_count; /* Count included in statistics since last collection */} unsigned short int rmpfst$w_xmt_pwinit_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_xmt_pwinit_ave_covfl; /* Count of current 100ns tics is greater than the AVEn maximum value since l\ast collection */ unsigned int rmpfst$l_xmt_pwinit_ohns_min; /* Minimum number of 100ns tics used in executing AMDS$RM_INIT_PASSIWORD_PROCESSOR */ unsigned int rmpfst$l_xmt_pwinit_ohns_cmin; /* Minimum number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR s\ince last collection */ unsigned int rmpfst$l_xmt_pwinit_ohns_max; /* Maximum number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR */ unsigned int rmpfst$l_xmt_pwinit_ohns_cmax; /* Maximum number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR s\ince last collection */ unsigned int rmpfst$l_xmt_pwIinit_ohns_curr; /* Current number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR */ unsigned int rmpfst$l_xmt_pwinit_ohns_ave2; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR u\+sing weight of 2 for exponential average */ unsigned int rmpfst$l_xmt_pwinit_ohns_ave4; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR u\+sing weight of 4 for exponential average */ unsigned int rmpfst$l_xmt_pwinit_ohns_avIe8; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR u\+sing weight of 8 for exponential average */ unsigned int rmpfst$l_xmt_pwinit_ohns_ave16; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR \-using weight of 16 for exponential average */ unsigned int rmpfst$l_xmt_pwinit_ohns_ave32; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR \-using weight of 32 for exponential average */ unIsigned int rmpfst$l_xmt_pwinit_ohns_ave128; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR\/ using weight of 128 for exponential average */ unsigned __int64 rmpfst$q_xmt_pwinit_ohns_ave512; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCE\3SSOR using weight of 512 for exponential average */ unsigned __int64 rmpfst$q_xmt_pwinit_ohns_ave2k; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCES\3SOR usIing weight of 2048 for exponential average */w unsigned __int64 rmpfst$q_xmt_pwinit_scc_curr; /* Current SCC value in executing AMDS$RM_INIT_PASSWORD_PROCESSOR */\ unsigned __int64 rmpfst$q_xmt_pwinit_scc_total; /* Total SCC count for this code path */s unsigned __int64 rmpfst$q_xmt_pwinit_scc_ctotal; /* Total SCC count for this code path since last collection */Z/* Stats for AMDS$RM_USE_PASSWORD_PROCESSOR routine for transmiting local CLIST packets */N unsigned int rmpfst$l_xmt_pwIproc_count; /* Count included in statistics */h unsigned int rmpfst$l_xmt_pwproc_col_count; /* Count included in statistics since last collection */} unsigned short int rmpfst$w_xmt_pwproc_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_xmt_pwproc_ave_covfl; /* Count of current 100ns tics is greater than the AVEn maximum value since l\ast collection */ unsigned int rmpfst$l_xmt_pwproc_ohns_min; /* Minimum number of 10I0ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR */ unsigned int rmpfst$l_xmt_pwproc_ohns_cmin; /* Minimum number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR si\nce last collection */ unsigned int rmpfst$l_xmt_pwproc_ohns_max; /* Maximum number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR */ unsigned int rmpfst$l_xmt_pwproc_ohns_cmax; /* Maximum number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR si\nce last collection I*/ unsigned int rmpfst$l_xmt_pwproc_ohns_curr; /* Current number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR */ unsigned int rmpfst$l_xmt_pwproc_ohns_ave2; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR us\*ing weight of 2 for exponential average */ unsigned int rmpfst$l_xmt_pwproc_ohns_ave4; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR us\*ing weight of 4 for exponential average */ unsignedI int rmpfst$l_xmt_pwproc_ohns_ave8; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR us\*ing weight of 8 for exponential average */ unsigned int rmpfst$l_xmt_pwproc_ohns_ave16; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR u\,sing weight of 16 for exponential average */ unsigned int rmpfst$l_xmt_pwproc_ohns_ave32; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR u\,sing weight of 32 for expoInential average */ unsigned int rmpfst$l_xmt_pwproc_ohns_ave128; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR \.using weight of 128 for exponential average */ unsigned __int64 rmpfst$q_xmt_pwproc_ohns_ave512; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCES\2SOR using weight of 512 for exponential average */ unsigned __int64 rmpfst$q_xmt_pwproc_ohns_ave2k; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASISWORD_PROCESS\2OR using weight of 2048 for exponential average */v unsigned __int64 rmpfst$q_xmt_pwproc_scc_curr; /* Current SCC value in executing AMDS$RM_USE_PASSWORD_PROCESSOR */\ unsigned __int64 rmpfst$q_xmt_pwproc_scc_total; /* Total SCC count for this code path */s unsigned __int64 rmpfst$q_xmt_pwproc_scc_ctotal; /* Total SCC count for this code path since last collection */Z/* Stats for AMDS$RM_INIT_PASSWORD_PROCESSOR routine for receiving remote CLIST packets */N unsigned iInt rmpfst$l_rcv_pwinit_count; /* Count included in statistics */h unsigned int rmpfst$l_rcv_pwinit_col_count; /* Count included in statistics since last collection */} unsigned short int rmpfst$w_rcv_pwinit_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_rcv_pwinit_ave_covfl; /* Count of current 100ns tics is greater than the AVEn maximum value since l\ast collection */ unsigned int rmpfst$l_rcv_pwinit_ohns_min; /* MiInimum number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR */ unsigned int rmpfst$l_rcv_pwinit_ohns_cmin; /* Minimum number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR s\ince last collection */ unsigned int rmpfst$l_rcv_pwinit_ohns_max; /* Maximum number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR */ unsigned int rmpfst$l_rcv_pwinit_ohns_cmax; /* Maximum number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR Is\ince last collection */ unsigned int rmpfst$l_rcv_pwinit_ohns_curr; /* Current number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR */ unsigned int rmpfst$l_rcv_pwinit_ohns_ave2; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR u\+sing weight of 2 for exponential average */ unsigned int rmpfst$l_rcv_pwinit_ohns_ave4; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR u\+sing weight of 4 for exponenItial average */ unsigned int rmpfst$l_rcv_pwinit_ohns_ave8; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR u\+sing weight of 8 for exponential average */ unsigned int rmpfst$l_rcv_pwinit_ohns_ave16; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR \-using weight of 16 for exponential average */ unsigned int rmpfst$l_rcv_pwinit_ohns_ave32; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCEISSOR \-using weight of 32 for exponential average */ unsigned int rmpfst$l_rcv_pwinit_ohns_ave128; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCESSOR\/ using weight of 128 for exponential average */ unsigned __int64 rmpfst$q_rcv_pwinit_ohns_ave512; /* Average number of 100ns tics used in executing AMDS$RM_INIT_PASSWORD_PROCE\3SSOR using weight of 512 for exponential average */ unsigned __int64 rmpfst$q_rcv_pwinit_ohns_ave2k; /* Average number of 100nIs tics used in executing AMDS$RM_INIT_PASSWORD_PROCES\3SOR using weight of 2048 for exponential average */w unsigned __int64 rmpfst$q_rcv_pwinit_scc_curr; /* Current SCC value in executing AMDS$RM_INIT_PASSWORD_PROCESSOR */\ unsigned __int64 rmpfst$q_rcv_pwinit_scc_total; /* Total SCC count for this code path */s unsigned __int64 rmpfst$q_rcv_pwinit_scc_ctotal; /* Total SCC count for this code path since last collection */Y/* Stats for AMDS$RM_USE_PASSWORD_PROCESSOR routine for receivIing remote CLIST packets */N unsigned int rmpfst$l_rcv_pwproc_count; /* Count included in statistics */h unsigned int rmpfst$l_rcv_pwproc_col_count; /* Count included in statistics since last collection */} unsigned short int rmpfst$w_rcv_pwproc_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_rcv_pwproc_ave_covfl; /* Count of current 100ns tics is greater than the AVEn maximum value since l\ast collection */ unsiIgned int rmpfst$l_rcv_pwproc_ohns_min; /* Minimum number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR */ unsigned int rmpfst$l_rcv_pwproc_ohns_cmin; /* Minimum number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR si\nce last collection */ unsigned int rmpfst$l_rcv_pwproc_ohns_max; /* Maximum number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR */ unsigned int rmpfst$l_rcv_pwproc_ohns_cmax; /* Maximum number of 100ns tics used in execIuting AMDS$RM_USE_PASSWORD_PROCESSOR si\nce last collection */ unsigned int rmpfst$l_rcv_pwproc_ohns_curr; /* Current number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR */ unsigned int rmpfst$l_rcv_pwproc_ohns_ave2; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR us\*ing weight of 2 for exponential average */ unsigned int rmpfst$l_rcv_pwproc_ohns_ave4; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSORI us\*ing weight of 4 for exponential average */ unsigned int rmpfst$l_rcv_pwproc_ohns_ave8; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR us\*ing weight of 8 for exponential average */ unsigned int rmpfst$l_rcv_pwproc_ohns_ave16; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR u\,sing weight of 16 for exponential average */ unsigned int rmpfst$l_rcv_pwproc_ohns_ave32; /* Average number of 100ns tics used in executingI AMDS$RM_USE_PASSWORD_PROCESSOR u\,sing weight of 32 for exponential average */ unsigned int rmpfst$l_rcv_pwproc_ohns_ave128; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESSOR \.using weight of 128 for exponential average */ unsigned __int64 rmpfst$q_rcv_pwproc_ohns_ave512; /* Average number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCES\2SOR using weight of 512 for exponential average */ unsigned __int64 rmpfst$q_rcv_pwproc_ohns_ave2k; /* IAverage number of 100ns tics used in executing AMDS$RM_USE_PASSWORD_PROCESS\2OR using weight of 2048 for exponential average */v unsigned __int64 rmpfst$q_rcv_pwproc_scc_curr; /* Current SCC value in executing AMDS$RM_USE_PASSWORD_PROCESSOR */\ unsigned __int64 rmpfst$q_rcv_pwproc_scc_total; /* Total SCC count for this code path */s unsigned __int64 rmpfst$q_rcv_pwproc_scc_ctotal; /* Total SCC count for this code path since last collection */I/* Stats for RM$AM_RUN, routine that gathersI data for CLIST packets */N unsigned int rmpfst$l_am_dc_count; /* Count included in statistics */c unsigned int rmpfst$l_am_dc_col_count; /* Count included in statistics since last collection */x unsigned short int rmpfst$w_am_dc_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_am_dc_ave_col_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value since las\t collection */w unsigned int rImpfst$l_am_dc_ohns_min; /* Minimum number of 100ns tics used in executing a data collector program */ unsigned int rmpfst$l_am_dc_ohns_col_min; /* Minimum number of 100ns tics used in executing a data collector program since last\ collection */w unsigned int rmpfst$l_am_dc_ohns_max; /* Maximum number of 100ns tics used in executing a data collector program */ unsigned int rmpfst$l_am_dc_ohns_col_max; /* Maximum number of 100ns tics used in executing a data collector program since lasIt\ collection */x unsigned int rmpfst$l_am_dc_ohns_curr; /* Current number of 100ns tics used in executing a data collector program */ unsigned int rmpfst$l_am_dc_ohns_ave2; /* Average number of 100ns tics used in executing a data collector program using weight \of 2 for exponential average */ unsigned int rmpfst$l_am_dc_ohns_ave4; /* Average number of 100ns tics used in executing a data collector program using weight \of 4 for exponential average */ unsigned int rmpfst$l_amI_dc_ohns_ave8; /* Average number of 100ns tics used in executing a data collector program using weight \of 8 for exponential average */ unsigned int rmpfst$l_am_dc_ohns_ave16; /* Average number of 100ns tics used in executing a data collector program using weight\! of 16 for exponential average */ unsigned int rmpfst$l_am_dc_ohns_ave32; /* Average number of 100ns tics used in executing a data collector program using weight\! of 32 for exponential average */ unsigned int rmpfst$l_Iam_dc_ohns_ave128; /* Average number of 100ns tics used in executing a data collector program using weigh\#t of 128 for exponential average */ unsigned __int64 rmpfst$q_am_dc_ohns_ave512; /* Average number of 100ns tics used in executing a data collector program using w\'eight of 512 for exponential average */ unsigned __int64 rmpfst$q_am_dc_ohns_ave2k; /* Average number of 100ns tics used in executing a data collector program using we\'ight of 2048 for exponential average */k unsiIgned __int64 rmpfst$q_am_dc_scc_curr; /* Current SCC value in executing a data collector program */W unsigned __int64 rmpfst$q_am_dc_scc_total; /* Total SCC count for this code path */n unsigned __int64 rmpfst$q_am_dc_scc_ctotal; /* Total SCC count for this code path since last collection */I/* Stats for TRANSPORT$CHECKSUM routine for CLIST packets */N unsigned int rmpfst$l_chksum_count; /* Count included in statistics */d unsigned int rmpfst$l_chksum_col_count; /*I Count included in statistics since last collection */y unsigned short int rmpfst$w_chksum_ave_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value */ unsigned short int rmpfst$w_chksum_ave_col_ovfl; /* Count of current 100ns tics is greater than the AVEn maximum value since la\st collection */r unsigned int rmpfst$l_chksum_ohns_min; /* Minimum number of 100ns tics used in executing TRANSPORT$CHECKSUM */ unsigned int rmpfst$l_chksum_ohns_col_min; /* Minimum Inumber of 100ns tics used in executing TRANSPORT$CHECKSUM since last coll\ ection */r unsigned int rmpfst$l_chksum_ohns_max; /* Maximum number of 100ns tics used in executing TRANSPORT$CHECKSUM */ unsigned int rmpfst$l_chksum_ohns_col_max; /* Maximum number of 100ns tics used in executing TRANSPORT$CHECKSUM since last coll\ ection */s unsigned int rmpfst$l_chksum_ohns_curr; /* Current number of 100ns tics used in executing TRANSPORT$CHECKSUM */ unsigned int rmpfst$l_chksum_ohns_Iave2; /* Average number of 100ns tics used in executing TRANSPORT$CHECKSUM using weight of 2 \for exponential average */ unsigned int rmpfst$l_chksum_ohns_ave4; /* Average number of 100ns tics used in executing TRANSPORT$CHECKSUM using weight of 4 \for exponential average */ unsigned int rmpfst$l_chksum_ohns_ave8; /* Average number of 100ns tics used in executing TRANSPORT$CHECKSUM using weight of 8 \for exponential average */ unsigned int rmpfst$l_chksum_ohns_ave16; /* Average nuImber of 100ns tics used in executing TRANSPORT$CHECKSUM using weight of 1\6 for exponential average */ unsigned int rmpfst$l_chksum_ohns_ave32; /* Average number of 100ns tics used in executing TRANSPORT$CHECKSUM using weight of 3\2 for exponential average */ unsigned int rmpfst$l_chksum_ohns_ave128; /* Average number of 100ns tics used in executing TRANSPORT$CHECKSUM using weight of \128 for exponential average */ unsigned __int64 rmpfst$q_chksum_ohns_ave512; /* Average number ofI 100ns tics used in executing TRANSPORT$CHECKSUM using weight\" of 512 for exponential average */ unsigned __int64 rmpfst$q_chksum_ohns_ave2k; /* Average number of 100ns tics used in executing TRANSPORT$CHECKSUM using weight \"of 2048 for exponential average */f unsigned __int64 rmpfst$q_chksum_scc_curr; /* Current SCC value in executing TRANSPORT$CHECKSUM */X unsigned __int64 rmpfst$q_chksum_scc_total; /* Total SCC count for this code path */o unsigned __int64 rmpfst$q_chksum_scc_cItotal; /* Total SCC count for this code path since last collection */ unsigned short int rmpfst$w_xmt_hello_skip_xmt; /* Number of times a transmit for HELLO packet is skipped because the last one \hasn't finished transmitting */ unsigned short int rmpfst$w_xmt_hello_skip_xmt_col; /* Number of times a transmit for HELLO packet is skipped because the last \9one hasn't finished transmitting since last collection */R unsigned int rmpfst$l_end_marker; /* Marks the end of this data stIructure */ } RMPFST;N/* */N/* RMDRIVER MO and MO status data from GET_STATUS request */N/* */N/* This structure represents data for Managed Object Parameter version 1.1 */N/* */N#define RMSDT$K_OBJ_REG_STS_RESERVED 0 /* 0 - Reserved (for debugging) */IN#define RMSDT$K_OBJ_REG_STS_REGISTERED 1 /* 1 - MO is registered */N#define RMSDT$K_OBJ_REG_STS_DREGISTERED 2 /* 2 - MO is deregistered */N#define RMSDT$K_OBJ_RUN_STS_RESERVED 0 /* 0 - Reserved (for debugging) */N#define RMSDT$K_OBJ_RUN_STS_REQ_ON 1 /* 1 - MO is processing requests */O#define RMSDT$K_OBJ_RUN_STS_REQ_OFF 2 /* 2 - MO is not processing requests */N#define RMSDT$K_V1_1_STSDAT_LEN 8 /* Reg out data length */N#define RMSDT$C_V1_1_S ITSDAT_LEN 8 /* Old VAX style length */ typedef struct _rmsdt {N unsigned char rmsdt$b_obj_reg_status; /* MO Registration status */N unsigned char rmsdt$b_obj_run_status; /* MO Run status */R unsigned char rmsdt$b_rm_obj_reg_status; /* RMDriver MO Registration status */N unsigned char rmsdt$b_rm_obj_run_status; /* RMDriver MO Run status */Z unsigned short int rmsdt$w_rm_drv_status; /* RMDriver run status (RMSTS$ constants) */N I unsigned short int rmsdt$w_rsvd; /* Quadword alignment */ } RMSDT;N/* */N/* RMDriver action codes */N/* Note: Managed Object specific codes start at 16 */h/* Note: Because of early implementations of Managed Object used 0-16, the range of common codes had */d/* to be moved. Will keep the 1-15 entries for RMDriver openI so that the common codes can */N/* be shifted to the 1-15 space. */N/* */N/* Managed Object/Data Analyzer request codes for RMDriver to process */N#define RMACT$K_RM_REGISTER 16 /* 16 - Register Managed Object */N#define RMACT$K_RM_DEREGISTER 17 /* 17 - Deregister Managed Object */\#define RMACT$K_RM_ENABLE_REQ 18 /* 18 - Enable request transfer Ito Managed Object */]#define RMACT$K_RM_DISABLE_REQ 19 /* 19 - Disable request transfer to Managed Object */i#define RMACT$K_RM_GET_STATUS 20 /* 20 - Retrieve RMDriver's status (stopped/started, etc.) and */N/* what RMDriver's status is for the Managed Object */X#define RMACT$K_RM_GET_REGISTRATION 21 /* 21 - Retrieve RMDriver's registration data */d#define RMACT$K_RM_CALLBACK_ROUTINES 22 /* 22 - Retrieve RMDriver's kernel-mode callback routines */W#define IRMACT$K_RM_GET_RM_CONFIGURATION 23 /* 23 - Retrieve RMDriver's configuration */R#define RMACT$K_RM_SET_RM_CONFIGURATION 24 /* 24 - Set RMDriver's configuration */S#define RMACT$K_RM_GET_RM_STATISTICS 25 /* 25 - Get RMDriver-specific statistics */W#define RMACT$K_RM_RESET_RM_STATISTICS 26 /* 26 - Reset RMDriver-specific statistics */X#define RMACT$K_RM_GET_MO_STATISTICS 27 /* 27 - Get a/all Managed Object's statistics */\#define RMACT$K_RM_RESET_MO_STATISTICS 28 /* 28 - Reset a/all Managed ObjeIct's statistics */S#define RMACT$K_RM_GET_RM_PERF_STATS 29 /* 29 - Get RMDriver-specific statistics */W#define RMACT$K_RM_RESET_RM_PERF_STATS 30 /* 30 - Reset RMDriver-specific statistics */N#define RMACT$K_RM_FIRST_UNUSED 31 /* Add new code ahead of this one */N#define RMACT$K_RM_FIRST_CODE 16 /* First RM action code */N#define RMACT$K_RM_LAST_CODE 30 /* Last RM action code */N/* I */N/* Action code constants for backward compatibility */N/* */N/* Managed Object/Data Analyzer request codes for RMDriver to process */T#define RMACT$K_RM_GET_CONFIGURATION 23 /* 23 - Retrieve RMDriver's configuration */O#define RMACT$K_RM_SET_CONFIGURATION 24 /* 24 - Set RMDriver's configuration */N/* */N/* RMDriIver error codes */N/* Note: Managed Object specific codes start at 128 */N/* */\#define RMMGT$K_STS_REG_INSFMEM 128 /* Can't allocate memory for a registration entry */N#define RMMGT$K_STS_REG_DB_FULL 129 /* Registration database is full */Q#define RMMGT$K_STS_OBJ_NAME_NULL 130 /* Managed Object's name field is null */R#define RMMGT$K_ISTS_OBJ_REGISTERED 131 /* Managed Object is already registered */N#define RMMGT$K_STS_OBJ_DEREGISTERED 132 /* Managed Object has deregistered */[#define RMMGT$K_STS_OBJ_ENABLED_REQ 133 /* Managed Object has enabled request processing */]#define RMMGT$K_STS_OBJ_DISABLED_REQ 134 /* Managed Object has disabled request processing */[#define RMMGT$K_STS_OBJ_STS_INVALID 135 /* Managed Object registration status is invalid */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE I /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RMMGTDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary soIftware **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietIary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************* I*******************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */I/* Source: 23-JUN-2004 13:16:13 $1$DGA8345:[LIB_H.SRC]RMSPUBSTR.SDL;1 *//********************************************************************************************************************************//*** MODULE $RMSEDTDEF ***/#ifndef __RMSEDTDEF_LOADED#define __RMSEDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANISI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_paraIms#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */I/* RMS Extension Dispatch Table */N/* I */Q/* The RMS extension dispatch table defines the vector area for RMS processing */I/* callouts. */N/* */#define RMSEDT$K_CURVER 1#define RMSEDT$C_CURVER 1#define RMSEDT$K_XAB_DISPLAY 63#define RMSEDT$K_LENGTH 180#define RMSEDT$C_LENGTH 180N#define RMSEDT$S_RMSEDTDEF 180 /* Old size name - synonym */ tyIpedef struct _rmsedt {% unsigned short int rmsedt$w_size;# unsigned char rmsedt$b_version;! unsigned char rmsedt$b_flags; int (*rmsedt$a_close)(); int (*rmsedt$a_connect)(); int (*rmsedt$a_create)();% int (*rmsedt$a_implied_create)(); int (*rmsedt$a_delete)();! int (*rmsedt$a_disconnect)(); int (*rmsedt$a_display)(); int (*rmsedt$a_erase)();$ int (*rmsedt$a_implied_erase)(); int (*rmsedt$a_extend)();! int (*rmsedt$a_autoextend)();I int (*rmsedt$a_find)(); int (*rmsedt$a_flush)(); int (*rmsedt$a_get)(); int (*rmsedt$a_open)(); int (*rmsedt$a_put)(); int (*rmsedt$a_read)(); int (*rmsedt$a_rename)();% int (*rmsedt$a_implied_rename)(); int (*rmsedt$a_rewind)();& int (*rmsedt$a_init_wcc_search)();' int (*rmsedt$a_next_ecxt_search)();( int (*rmsedt$a_delete_wcc_search)(); int (*rmsedt$a_space)(); int (*rmsedt$a_truncate)(); int (*rmsedt$a_update)(); Iint (*rmsedt$a_write)(); int (*rmsedt$a_open_ltj)(); int (*rmsedt$a_close_ltj)();% int (*rmsedt$a_format_journal)();$ int (*rmsedt$a_write_journal)();$ int (*rmsedt$a_flush_journal)();! int (*rmsedt$a_create_ruj)(); int (*rmsedt$a_close_ruj)();! int (*rmsedt$a_dispose_ru)(); int (*rmsedt$a_write_ruj)(); int (*rmsedt$a_flush_ruj)();" int (*rmsedt$a_lock_record)();$ int (*rmsedt$a_unlock_record)();) int (*rmsedt$a_unlock_all_records)();' Iint (*rmsedt$a_is_record_locked)();- int (*rmsedt$a_is_record_write_locked)();* int (*rmsedt$a_is_record_lock_held)();# int (*rmsedt$a_xab_dispatch)(); } RMSEDT; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RMSEDTDEF_LOADED I */ ww`ͺ[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. I **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 CopyrigIht VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */I/* Source: 31-MAR-2023 17:54:49 $1$DGA8345:[LIB_H.SRC]RNDBITDEF.SDL;1 *//*********** I*********************************************************************************************************************//*** MODULE RNDBITDEF ***/#ifndef __RNDBITDEF_LOADED#define __RNDBITDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined Irequired ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#elseI#define __union variant_union#endif#endif #define RNDBIT$M_CACHED 0x1#define RNDBIT$M_ATTACH 0x2#define RNDBIT$M_PERCPU 0x4#define RNDBIT$M_LCKMGR 0x8#define RNDBIT$M_CLUSTER 0x10#define RNDBIT$M_NET_TUN 0x20#define RNDBIT$M_NET_ETHER 0x40#define RNDBIT$M_INTERRUPT 0x80#define RNDBIT$M_SWI 0x100#define RNDBIT$M_FS_ATIME 0x200#define RNDBIT$M_NPP 0x400#define RNDBIT$M_ACCOUNT 0x800$#define RNDBIT$M_PURE_RDRAND 0x10000$#define RNDBIT$M_PURE_VIRTIO 0x20000  Itypedef struct _rndbits { __union {& unsigned int rndbit$l_rndbits; __struct {N unsigned rndbit$v_cached : 1; /* Data cached at boot */N unsigned rndbit$v_attach : 1; /* Device attach - NI */N unsigned rndbit$v_percpu : 1; /* per-CPU counters */N unsigned rndbit$v_lckmgr : 1; /* Lock Manager */N unsigned rndbit$v_cluster : 1; /* Cluster sources */NI unsigned rndbit$v_net_tun : 1; /* Network - tunnel - NI */N unsigned rndbit$v_net_ether : 1; /* Network packets - NI */N unsigned rndbit$v_interrupt : 1; /* Interrupt sources */N unsigned rndbit$v_swi : 1; /* Software Interrupts */N unsigned rndbit$v_fs_atime : 1; /* File system access time */N unsigned rndbit$v_npp : 1; /* Special - non-paged pool */O unsigned rndbi It$v_account : 1; /* Process termination accounting */, unsigned rndbit$v_env_spare : 4;N unsigned rndbit$v_pure_rdrand : 1; /* X86 RDRAND instruction */N unsigned rndbit$v_pure_virtio : 1; /* VirtIO Random driver */. unsigned rndbit$v_pure_spare : 14;$ } rndbit$r_rndbits_bits;# } rndbit$r_rndbits_overlay; } RNDBITS; #if !defined(__VAXC)B#define rndbit$l_rndbits rndbit$r_rndbits_overlay.rndbit$l_rndbitsV#define rnIdbit$v_cached rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_cachedV#define rndbit$v_attach rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_attachV#define rndbit$v_percpu rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_percpuV#define rndbit$v_lckmgr rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_lckmgrX#define rndbit$v_cluster rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_clusterX#define rndbit$v_net_tun rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rnIdbit$v_net_tun\#define rndbit$v_net_ether rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_net_ether\#define rndbit$v_interrupt rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_interruptP#define rndbit$v_swi rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_swiZ#define rndbit$v_fs_atime rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_fs_atimeP#define rndbit$v_npp rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_nppX#define rndbit$v_account rndbit$r_rndbits_overIlay.rndbit$r_rndbits_bits.rndbit$v_account`#define rndbit$v_pure_rdrand rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_pure_rdrand`#define rndbit$v_pure_virtio rndbit$r_rndbits_overlay.rndbit$r_rndbits_bits.rndbit$v_pure_virtio"#endif /* #if !defined(__VAXC) */ N/* */N/* Use the following constants for the equivalent symbols */N/* from the random_entropy_source enum from non-C code. I */N/* */#define RANDOM$K_CACHED 0#define RANDOM$K_ATTACH 1#define RANDOM$K_PERCPU 2#define RANDOM$K_LCKMGR 3#define RANDOM$K_CLUSTER 4#define RANDOM$K_NET_TUN 5#define RANDOM$K_NET_ETHER 6#define RANDOM$K_INTERRUPT 7#define RANDOM$K_SWI 8#define RANDOM$K_FS_ATIME 9#define RANDOM$K_NPP 10#define RANDOM$K_ACCOUNT 11%#define RANDOM$K_ENVIRONMENTAL_END 11%#define RANDOM$K_RANDOM_PURE_STARTI 16#define RANDOM$K_PURE_RDRAND 16#define RANDOM$K_PURE_VIRTIO 17 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RNDBITDEF_LOADED */ wwM/***************************************************************************I/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** I **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** I **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */E/* Source: 06-NOV-2002 10:54:56 $1$DGA8345:[LIB_H.SRC]RRDEF.SDL;1 *//***************************************************************************************************************************** I***//*** MODULE $RRDEF ***/#ifndef __RRDEF_LOADED#define __RRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifI #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* I */N/* Definitions for Region Register */N/* */#define RR$M_VE 0x1#define RR$M_MBZ0 0x2#define RR$M_PS 0xFC#define RR$M_RID 0xFFFFFF00$#define RR$M_MBZ1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef Istruct _rr {#pragma __nomember_alignment __union {. unsigned __int64 rr$q_region_register; __struct {N unsigned rr$v_ve : 1; /* VHPT walker enabled */N unsigned rr$v_mbz0 : 1; /* Reserved bit RR{1:1} (MBZ) */N unsigned rr$v_ps : 6; /* Preferred page size */N unsigned rr$v_rid : 24; /* Region identifier */N unsigned rr$v_mbz1 : 32; /* Reserved RR{6 J3:32} (MBZ) */ } rr$r_rrdef_bits; } rr$r_rr_union; } RR; #if !defined(__VAXC)?#define rr$q_region_register rr$r_rr_union.rr$q_region_register5#define rr$v_ve rr$r_rr_union.rr$r_rrdef_bits.rr$v_ve9#define rr$v_mbz0 rr$r_rr_union.rr$r_rrdef_bits.rr$v_mbz05#define rr$v_ps rr$r_rr_union.rr$r_rrdef_bits.rr$v_ps7#define rr$v_rid rr$r_rr_union.rr$r_rrdef_bits.rr$v_rid9#define rr$v_mbz1 rr$r_rr_union.rr$r_rrdef_bits.rr$v_mbz1"#endif /* #if !defined(__VAXC J) */ Z#define VRN$C_PROCESS 0 /* Virtual Region Number 0 is for process space */Y#define VRN$C_SYSTEM 7 /* Virtual Region Number 7 is for system space */N#define VRN$C_REGION_COUNT 8 /* Number of regions */N#define RR$C_SIZE 8 /* Number of region registers */ #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long J/* Pointers are 64-bit */Atypedef struct _rr * RR_PQ; /* Pointer to a RR structure. */Ntypedef struct _rr ** RR_PPQ; /* Pointer to a pointer to a RR structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#elsetypedef unsigned __int64 RR_PQ; typedef unsigned __int64 RR_PPQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pJragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RRDEF_LOADED */ wwi[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard EnterpriseJ Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not J **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************* J***********************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */F/* Source: 19-DEC-2017 13:09:43 $1$DGA8345:[LIB_H.SRC]RSBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RSBDEF ***/#ifndef __RSBDEF_LOADED#define __RSBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragmJa __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#iJf !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* RSB - Resource Block */N/* J */P/* Resource blocks represent resources for which there are locks outstanding. */O/* Each resource block may have one or more lock blocks (LKBs) queued to it. */N/* */N/*- */ #define RSB$M_DIRENTRY 0x1#define RSB$M_VALINVLD 0x2#define RSB$M_DIR_RQD 0x4#define RSB$M_RM_PEND 0x8#define RSB$M_RM_IP  J0x10#define RSB$M_RM_ACCEPT 0x20#define RSB$M_RM_RBLD 0x40#define RSB$M_RM_WAIT 0x80#define RSB$M_RM_DEFLECT 0x100#define RSB$M_DIR_IP 0x200#define RSB$M_RBLD_IP 0x400#define RSB$M_RBLD_RQD 0x800#define RSB$M_RBLD_ACT 0x1000#define RSB$M_CHK_BTR 0x2000#define RSB$M_WTFULRNG 0x4000#define RSB$M_WTSUBRNG 0x8000#define RSB$M_BRL 0x10000#define RSB$M_2PC_IP 0x80000 #define RSB$M_CVTFULRNG 0x100000 #define RSB$M_CVTSUBRNG 0x200000#define RSB$M_VALCUR 0x400000#define RS JB$M_INVPEND 0x800000#define RSB$M_DPC 0x1000000$#define RSB$M_GGMODE_VALID 0x2000000"#define RSB$M_XVAL_VALID 0x4000000!#define RSB$M_RM_FREEZE 0x8000000!#define RSB$M_RM_FORCE 0x10000000'#define RSB$M_RM_NO_INTEREST 0x20000000"#define RSB$M_VIRGIN_VB 0x40000000N#define RSB$K_MAXLEN 31 /* Maximum length of Resource Name */N#define RSB$K_LENGTH 328 /* Length of fixed part of RSB */N#define RSB$C_LENGTH 328 /* Length of fixed part of RSB J */N#define RSB$S_RSBDEF 328 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */struct _clurcb; #endif /* #ifdef __cplusplus */ typedef struct _rsb {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporte Jd */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rsb$q_hshchn; /* Hash Chain Pointer */#else unsigned __int64 rsb$q_hshchn;#endif#pragma __nomember_alignmentN unsigned short int rsb$w_size; /* Size of RSB structure */N unsigned char rsb$b_type; /* Structure type */N unsigned char rsb$b_fgmode; /* Full-Range Grant Mode */N unsiJgned char rsb$b_ggmode; /* Group Grant Mode */N unsigned char rsb$b_cgmode; /* Conversion Grant Mode */N unsigned short int rsb$w_blkastcnt; /* Blocking AST count */ __union {N unsigned int rsb$l_status; /* Status longword */ __struct {] unsigned rsb$v_direntry : 1; /* Directory Entry (director system for resource) */N unsigned rsb$v_valinvld : 1; /* Value Block InvaJlid */N unsigned rsb$v_dir_rqd : 1; /* Directory Entry required */Q unsigned rsb$v_rm_pend : 1; /* Resource Remaster Operation Pending */N unsigned rsb$v_rm_ip : 1; /* Resource being Remastered */N unsigned rsb$v_rm_accept : 1; /* New Master accepts */N unsigned rsb$v_rm_rbld : 1; /* Always rebuild tree */N unsigned rsb$v_rm_wait : 1; /* Block local activity */N J unsigned rsb$v_rm_deflect : 1; /* Deflect remote interest */N unsigned rsb$v_dir_ip : 1; /* Directory Entry being created */N unsigned rsb$v_rbld_ip : 1; /* Rebuild in progress */N unsigned rsb$v_rbld_rqd : 1; /* Rebuild required for this tree */N unsigned rsb$v_rbld_act : 1; /* Lock Rebuild active for tree */[ unsigned rsb$v_chk_btr : 1; /* Check for better master (not used as of V8.3) */N unJsigned rsb$v_wtfulrng : 1; /* Full-Range REQs in wait queue */N unsigned rsb$v_wtsubrng : 1; /* Sub-Range REQs in wait queue */N unsigned rsb$v_brl : 1; /* Indicates byte range resource */' unsigned rsb$v_fill_21 : 1;' unsigned rsb$v_fill_22 : 1;N unsigned rsb$v_2pc_ip : 1; /* Two Phase Convert in progress */P unsigned rsb$v_cvtfulrng : 1; /* Full-Range REQs in convert queue */O unsigned rsb$v_cvtsubrJng : 1; /* Sub-Range REQs in convert queue */N unsigned rsb$v_valcur : 1; /* Value Block is current */O unsigned rsb$v_invpend : 1; /* Do Value Block invalidation check */N unsigned rsb$v_dpc : 1; /* Delete pending cache */N unsigned rsb$v_ggmode_valid : 1; /* Group Grant Mode valid */N unsigned rsb$v_xval_valid : 1; /* Last VALBLK was not short */Q unsigned rsb$v_rm_freeze : 1; /* Freeze reso Jurce tree on this node */N unsigned rsb$v_rm_force : 1; /* Forced tree move */^ unsigned rsb$v_rm_no_interest : 1; /* Remaster due to master having no interest */^ unsigned rsb$v_virgin_vb : 1; /* Resource has never initialized the value block */' unsigned rsb$v_fill_0_ : 1; } rsb$r_status_bits; } rsb$r_status_overlay;N unsigned int rsb$l_refcnt; /* Sub RSB reference count */N unsigned int J rsb$l_csid; /* System ID of master system */N unsigned int rsb$l_rm_csid; /* Pending Remaster CSID */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers J*/N void *rsb$q_hshchnbk; /* Hash Chain back pointer */#else! unsigned __int64 rsb$q_hshchnbk;#endif __union {#pragma __nomember_alignmentN unsigned short int rsb$w_rqseqnm; /* Request sequence number */N unsigned __int64 rsb$q_rqseqnm; /* Request sequence number */ } rsb$r_rqseqnm_overlay;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* AJnd set ptr size default to 32-bit pointers */#endifN struct _clurcb *rsb$l_clurcb; /* Remaster Control Block */N unsigned short int rsb$w_activity; /* Resource activity counter */N unsigned short int rsb$w_lckcnt; /* Count of locks on resource */N unsigned short int rsb$w_nact; /* New activity */N unsigned short int rsb$w_oact; /* Old (historical) activity */N unsigned short int rsb$w_nmact; /* New mas Jter's activity */N unsigned char rsb$b_lstcsid_idx; /* Last CSID index */N unsigned char rsb$b_same_cnt; /* Same node counter */N __union { /* Short and long value */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifN unsigned int rsb$q_valblk [4]; /* Sho Jrt Value Block */N char rsb$t_xvalblk [64]; /* Long Value Block */ } rsb$r_valblk_overlay;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rsb$q_grqfl; /* Granted queue forward link */#else unsigned __int64 rsb$q_grqfl;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER J_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rsb$q_grqbl; /* Granted queue backward link */#else unsigned __int64 rsb$q_grqbl;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* JDefined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rsb$q_cvtqfl; /* Conversion queue forward link */#else unsigned __int64 rsb$q_cvtqfl;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rsb$q_cvtqbl; J /* Conversion queue backward link */#else unsigned __int64 rsb$q_cvtqbl;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rsb$q_wtqfl; J/* Wait queue forward link */#else unsigned __int64 rsb$q_wtqfl;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rsb$q_wtqbl; /* Wait queue backward link */#else unsigned __int64 rsb$q_wtqbl;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECCJ V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifN unsigned __int64 rsb$q_2pcqfl; /* Two Phase Converts forward link */#pragma __nomember_alignmentN unsigned __int64 rsb$q_2pcqbl; /* Two Phase Converts backward link */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POI JNTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rsb$q_rrsfl; /* Root list forward link */#else unsigned __int64 rsb$q_rrsfl;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rsb$q_ Jrrsbl; /* Root list backward link */#else unsigned __int64 rsb$q_rrsbl;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rsb$q_srsfl; J /* Tree list forward link */#else unsigned __int64 rsb$q_srsfl;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *rsb$q_srsbl; /* Tree list backward link */#else unsigned __int64 rsb$q_srsbl;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If us !Jing pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _rsb *rsb$q_rtrsb; /* Pointer to Root RSB */#else unsigned __int64 rsb$q_rtrsb;#endif#pragma __nomember_alignmentN unsigned int rsb$l_depth; /* Depth in tr "Jee */T unsigned int rsb$l_oldvalseqnum; /* Old 32-bit Value Block sequence number */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endifN unsigned int rsb$q_lock [4]; /* RSB Synchronization Lock */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_ali#Jgnment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _rsb *rsb$q_parent; /* Address of Parent RSB */#else unsigned __int64 rsb$q_parent;#endif#pragma __nomember_alignment __union {N unsigned int rsb$l_hashval; /* Hash Value (P26 32-bit value) */ $J__struct {% short int rsb$w_fill_103;^ unsigned short int rsb$w_dirhash; /* Directory Hash (Pre-P26 16-bit Hash Value) */$ } rsb$r_dirhash_overlay; } rsb$r_hashval_overlay;N unsigned short int rsb$w_group; /* Group number */N unsigned char rsb$b_rmod; /* Access mode of resource */N unsigned char rsb$b_rsnlen; /* Resource Name length */c#if !defined(__NOBASEALIGN_SUPPORT) && !def %Jined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN char rsb$t_resnam [32]; /* Start of Resource Name */#pragma __nomember_alignmentN unsigned __int64 rsb$q_tot_lckcnt; /* total locks on this tree */N unsigned __int64 rsb$q_loc_lckcnt; /* total local locks on this tree */ __union {R unsigned __int64 rsb$q_valseqnum; /* 64-bit Value Block sequence n &Jumber */P unsigned int rsb$l_valseqnum; /* 32-bit Value Block sequence number */" } rsb$r_valseqnum_overlay; } RSB; #if !defined(__VAXC)6#define rsb$l_status rsb$r_status_overlay.rsb$l_statusL#define rsb$v_direntry rsb$r_status_overlay.rsb$r_status_bits.rsb$v_direntryL#define rsb$v_valinvld rsb$r_status_overlay.rsb$r_status_bits.rsb$v_valinvldJ#define rsb$v_dir_rqd rsb$r_status_overlay.rsb$r_status_bits.rsb$v_dir_rqdJ#define rsb$v_rm_pend rsb$r_status_overlay.rsb$r_sta'Jtus_bits.rsb$v_rm_pendF#define rsb$v_rm_ip rsb$r_status_overlay.rsb$r_status_bits.rsb$v_rm_ipN#define rsb$v_rm_accept rsb$r_status_overlay.rsb$r_status_bits.rsb$v_rm_acceptJ#define rsb$v_rm_rbld rsb$r_status_overlay.rsb$r_status_bits.rsb$v_rm_rbldJ#define rsb$v_rm_wait rsb$r_status_overlay.rsb$r_status_bits.rsb$v_rm_waitP#define rsb$v_rm_deflect rsb$r_status_overlay.rsb$r_status_bits.rsb$v_rm_deflectH#define rsb$v_dir_ip rsb$r_status_overlay.rsb$r_status_bits.rsb$v_dir_ipJ#define rsb$v_rbld_ip (Jrsb$r_status_overlay.rsb$r_status_bits.rsb$v_rbld_ipL#define rsb$v_rbld_rqd rsb$r_status_overlay.rsb$r_status_bits.rsb$v_rbld_rqdL#define rsb$v_rbld_act rsb$r_status_overlay.rsb$r_status_bits.rsb$v_rbld_actJ#define rsb$v_chk_btr rsb$r_status_overlay.rsb$r_status_bits.rsb$v_chk_btrL#define rsb$v_wtfulrng rsb$r_status_overlay.rsb$r_status_bits.rsb$v_wtfulrngL#define rsb$v_wtsubrng rsb$r_status_overlay.rsb$r_status_bits.rsb$v_wtsubrngB#define rsb$v_brl rsb$r_status_overlay.rsb$r_status_bits.rsb$v_b)JrlH#define rsb$v_2pc_ip rsb$r_status_overlay.rsb$r_status_bits.rsb$v_2pc_ipN#define rsb$v_cvtfulrng rsb$r_status_overlay.rsb$r_status_bits.rsb$v_cvtfulrngN#define rsb$v_cvtsubrng rsb$r_status_overlay.rsb$r_status_bits.rsb$v_cvtsubrngH#define rsb$v_valcur rsb$r_status_overlay.rsb$r_status_bits.rsb$v_valcurJ#define rsb$v_invpend rsb$r_status_overlay.rsb$r_status_bits.rsb$v_invpendB#define rsb$v_dpc rsb$r_status_overlay.rsb$r_status_bits.rsb$v_dpcT#define rsb$v_ggmode_valid rsb$r_status_overlay.rs*Jb$r_status_bits.rsb$v_ggmode_validP#define rsb$v_xval_valid rsb$r_status_overlay.rsb$r_status_bits.rsb$v_xval_validN#define rsb$v_rm_freeze rsb$r_status_overlay.rsb$r_status_bits.rsb$v_rm_freezeL#define rsb$v_rm_force rsb$r_status_overlay.rsb$r_status_bits.rsb$v_rm_forceX#define rsb$v_rm_no_interest rsb$r_status_overlay.rsb$r_status_bits.rsb$v_rm_no_interestN#define rsb$v_virgin_vb rsb$r_status_overlay.rsb$r_status_bits.rsb$v_virgin_vb9#define rsb$w_rqseqnm rsb$r_rqseqnm_overlay.rsb$w_rqseqnm9 +J#define rsb$q_rqseqnm rsb$r_rqseqnm_overlay.rsb$q_rqseqnm6#define rsb$q_valblk rsb$r_valblk_overlay.rsb$q_valblk8#define rsb$t_xvalblk rsb$r_valblk_overlay.rsb$t_xvalblk9#define rsb$l_hashval rsb$r_hashval_overlay.rsb$l_hashvalO#define rsb$w_dirhash rsb$r_hashval_overlay.rsb$r_dirhash_overlay.rsb$w_dirhash?#define rsb$q_valseqnum rsb$r_valseqnum_overlay.rsb$q_valseqnum?#define rsb$l_valseqnum rsb$r_valseqnum_overlay.rsb$l_valseqnum"#endif /* #if !defined(__VAXC) */  $#pragma __memb,Jer_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RSBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONF-JIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. T.Jhis software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************************************** /J************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */F/* Source: 14-MAY-2003 11:02:35 $1$DGA8345:[LIB_H.SRC]RSCDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RSCDEF ***/#ifndef __RSCDEF_LOADED#define __RSCDEF_LOADED 1 G#pragm 0Ja __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_p1Jarams ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define RSC$M_MODE 0x3#define RSC$M_PL 0xC#define RSC$M_BE 0x10#define RSC$M_LOADRS 0x3FFF0000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplus 2Jplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rsc {N/* */N/* Register Stack Engine Control Register */N/**************************************** */#pragma __nomember_alignment __union {, unsigned __int64 rsc$iq_rse_control; __struct 3J {N unsigned rsc$v_mode : 2; /* RSE saving mode */N unsigned rsc$v_pl : 2; /* RSE privilege level */N unsigned rsc$v_be : 1; /* RSE endian */N unsigned rsc$v_rv1 : 11; /* Reserved */i unsigned rsc$v_loadrs : 14; /* RSE load distance to tear point..used by loadrs instruction */#if defined(__VAXC)& unsigned rsc$v_rv2_1 : 32;% 4J unsigned rsc$v_rv2_2 : 2;#elseN unsigned __int64 rsc$v_rv2 : 34; /* Reserved */#endif } rsc$r_rsc_fields; } rsc$r_rsc_overlay; } RSC; #if !defined(__VAXC)?#define rsc$iq_rse_control rsc$r_rsc_overlay.rsc$iq_rse_control@#define rsc$v_mode rsc$r_rsc_overlay.rsc$r_rsc_fields.rsc$v_mode<#define rsc$v_pl rsc$r_rsc_overlay.rsc$r_rsc_fields.rsc$v_pl<#define rsc$v_be rsc$r_rsc_overlay.rsc$r_rsc_fields.rsc$v_be>#define rsc$v_rv1 rsc$ 5Jr_rsc_overlay.rsc$r_rsc_fields.rsc$v_rv1D#define rsc$v_loadrs rsc$r_rsc_overlay.rsc$r_rsc_fields.rsc$v_loadrs>#define rsc$v_rv2 rsc$r_rsc_overlay.rsc$r_rsc_fields.rsc$v_rv2"#endif /* #if !defined(__VAXC) */ N/* Constants for MODE field */P#define RSC$C_MODE_ENFORCED_LAZY 0 /* disable eager load and eager store */T#define RSC$C_MODE_LOAD_INTENSIVE 1 /* enable eager load, disable eager store */T#define RSC$C_MODE_STORE_INTENSIVE 2 /* 6J disable eager load, enable eager store */O#define RSC$C_MODE_EAGER 3 /* enable eager load and eager store */N/* Constants for BE field */#define RSC$C_ENDIAN_LITTLE 0#define RSC$C_ENDIAN_BIG 1 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef7J __cplusplus }#endif#pragma __standard #endif /* __RSCDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the 8J**/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior writte9Jn permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: :J 04-APR-2022 09:17:03 $1$DGA8345:[LIB_H.SRC]RSNDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RSNDEF ***/#ifndef __RSNDEF_LOADED#define __RSNDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pra;Jgma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifn Je RSN$_BRKTHRU 6 /*TERMINAL BROADCAST */N#define RSN$_IACLOCK 7 /*IMAGE ACTIVATION INTERLOCK */N#define RSN$_JQUOTA 8 /*JOB POOLED QUOTA */N#define RSN$_LOCKID 9 /*LOCKIDS */N#define RSN$_SWPFILE 10 /*SWAPPING FILE SPACE */N#define RSN$_MPLEMPTY 11 /*MODIFIED PAGE LIST EMPTY */N#define RSN$_MPWBUSY 12 ?J /*MODIFIED PAGE WRITER BUSY */N#define RSN$_SCS 13 /*SYSTEM COMMUNICATION */N#define RSN$_CLUSTRAN 14 /*CLUSTER STATE TRANSITION */N#define RSN$_CPUCAP 15 /*CPU Capability */N#define RSN$_CLUSRV 16 /*CLUSTER SERVER */N#define RSN$_SNAPSHOT 17 /* */N#define RSN$_PSXFRK 18 /*POSIX FORK WAIT @J */N#define RSN$_INNER_MODE 19 /*Inner mode access for Kthreads */N#define RSN$_EXH 20 /*Exit handler for Kthread */N#define RSN$_MMG 21 /*MMG Contention */N#define RSN$_SCMTX 22 /*SSIO SC MUTEX WAIT */c#define RSN$_MAX 23 /*MAXIMUM RESOURCE NUMBER ONLY add new states above here */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POIAJNTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RSNDEF_LOADED */ wwT[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential propBJrietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/*CJ* proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************** DJ*****************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 13-DEC-1994 16:07:23 $1$DGA8345:[LIB_H.SRC]RVTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $RVTDEF ***/#ifndef __RVTDEF_LOADED#define __RVTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSIEJ-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_paramsFJ#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* RVT - RELATIVE VOLUME TABLE */N/* GJ */N/* A RELATIVE VOLUME MAPPING TABLE IS REQUIRED FOR EVERY MULTIVOLUME */N/* STRUCTURE THAT IS MOUNTED IN A SYSTEM. */N/*- */ N#define RVT$K_LENGTH 88 /* LENGTH OF STANDARD RVT */N#define RVT$C_LENGTH 88 /* LENGTH OF STANDARD RVT */P#define RVT$C_UCB_POINTER 0 /* ADDRESSES OF THE RESPECTIVEHJ UCB'S */N#define RVT$C_PHYSICAL_VOLUME 1 /* Physical volume number */N#define RVT$C_VOLUME_LOCK_ID 2 /* Volume Lock ID */N#define RVT$C_VOLUME_IDENTIFIER 3 /* Volume Identifier */N/* Number of overlay elements */N#define RVT$C_RVTVCB 4 /* Number of elements (0 based) */T#define RVT$C_MINSIZE 18 /* MINIMUM NUMBER OF ENTRIES TO ALLOCATE */N#define IJRVT$S_RVTDEF 88 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rvt {#pragma __nomember_alignmentN unsigned int rvt$l_struclkid; /* LOCK ID OF VOLUME SET LOCK.JJ */N unsigned int rvt$l_refc; /* REFERENCE COUNT */N unsigned short int rvt$w_size; /* SIZE OF RVT IN BYTES */N unsigned char rvt$b_type; /* STRUCTURE TYPE OF RVT */N unsigned char rvt$b_nvols; /* NUMBER OF VOLUMES IN SET */N char rvt$t_strucname [12]; /* STRUCTURE (VOLUME SET) NAME */N char rvt$t_vlslcknam [12]; /* Volume set lock name. */N unsigned intKJ rvt$l_blockid; /* Blocking lock id. */N unsigned char rvt$b_acb [36]; /* ACB for blocking ast. */O unsigned int rvt$l_trans; /* Transaction count for volume sets */N unsigned int rvt$l_activity; /* ACTIVITY COUNT/FLAG */ __union {P struct _ucb *rvt$l_ucblst; /* Addresses of the respective UCB'S */V void *rvt$a_rvtvcb; /* Start of RVT/VCB fields for Files-11 C/D */ } rvt$ LJr_rvt_overlay;N/* Files-11 C/D RVT/VCB datums */ } RVT; #if !defined(__VAXC)3#define rvt$l_ucblst rvt$r_rvt_overlay.rvt$l_ucblst3#define rvt$a_rvtvcb rvt$r_rvt_overlay.rvt$a_rvtvcb"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */MJ#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __RVTDEF_LOADED */ ww{[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyoNJne without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** OJthe prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 PJ */K/* Source: 09-JUN-1993 15:43:42 $1$DGA8345:[LIB_H.SRC]S0PAGINGDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE S0PAGINGDEF ***/#ifndef __S0PAGINGDEF_LOADED#define __S0PAGINGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever pQJtr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variantRJ_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define S0PAGING$M_EXEC 0x1#define S0PAGING$M_RMS 0x2N#define S0PAGING$S_S0PAGINGDEF 4 /* Old size name - synonym */ typedef struct _s0paging { __union { int s0paging$l_bits; __struct {S unsigned s0paging$v_exec : 1; /* exec paging (most loadable pieces) */N unsigned s0paginSJg$v_rms : 1; /* RMS paging */, unsigned s0paging$v_fill_2_ : 6;! } s0paging$r_fill_1_; } s0paging$r_fill_0_; } S0PAGING; #if !defined(__VAXC)M#define s0paging$v_exec s0paging$r_fill_0_.s0paging$r_fill_1_.s0paging$v_execK#define s0paging$v_rms s0paging$r_fill_0_.s0paging$r_fill_1_.s0paging$v_rms"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptrTJ size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __S0PAGINGDEF_LOADED */ ww0ɼ[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** liUJcensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licenseVJd by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************* WJ***********************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */I/* Source: 18-JUN-2007 14:04:20 $1$DGA8345:[LIB_H.SRC]SASDEVDEF.SDL;1 *//********************************************************************************************************************************/%/*** MODULE $SASDEVDEF IDENT X-8 ***/#ifndef __SASDEVDEF_LOADED#define __SASDEVDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-StandarXJd features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#definYJe __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* Definitions used by both PKMDRIVER and IOGEN. */ #include 5#define IO$_SASREADCAPACITY IO$_AVAILABLE /* 011 */0#define IO$_SASREADPBLK IO$_REREADP /* 017 */1#def ZJine IO$_SASGETDEVDATA IO$_READRCT /* 009 *//#define IO$_SASID2TARG IO$_DISPLAY /* 013 */;#define IO$_TARG2SASID (IO$_DISPLAY + IO$M_SWAP) /* 113 */0#define IO$_SASGETUDID IO$_READHEAD /* 00E */1#define IO$_SASSETUDID IO$_WRITEHEAD /* 00D */+#define IO$_PORTRESET IO$_DSE /* 015 */!#define SCSI_SAS_HARD_RESET 0x101"#define SAS_PURGE_PERSISTENT 0x102"#define SAS_CLEAR_PERSISTENT 0x103 #define SAS_DISCOVERY_SCAN 0x104 #define SCSI_SAS_BUS_RESET 0x105!#define SCSI_GET_NEGOT [JIATED 0x106#define GET_SAS_UDID 0x1234&#define GET_SATA_END_DEVICE_BIT 0x2345&#define SAS_TARG$M_SAS_DEVICE_TYPE 0xF#define SAS_TARG$M_VALID 0x10!#define SAS_TARG$M_CONNECTED 0x20$#define SAS_TARG$M_UDID_CAPABLE 0x40*#define SAS_TARG$M_NVRAM_UDID_CAPABLE 0x80(#define SAS_TARG$M_DIRECT_ATTACHED 0x100%#define SAS_TARG$M_TARGET_RESET 0x200*#define SAS_TARG$M_DA_WITH_ENCL_MGMT 0x400`#define SAS_TARG$C_SATA_WWNAME_SIZE 60 /* Specified max bytes, minus leading invariant bytes */N#define \JSAS_TARG$C_NO_DEVICE 0 /* No device */N#define SAS_TARG$C_SAS_END_DEVICE 1 /* SAS end device */N#define SAS_TARG$C_SATA_END_DEVICE 2 /* SATA end device */N#define SAS_TARG$C_ATAPI_END_DEVICE 3 /* ATAPI end device */N#define SAS_TARG$C_SEP_END_DEVICE 4 /* SEP end device */N#define SAS_TARG$C_SAS_SATA_DEVICE 13 /* SAS/SATA device */N#define SAS_TARG$C_RAID_PHYS_DISK ]J14 /* Integrated RAID physical disk */N#define SAS_TARG$C_RAID_VOLUME 15 /* Integrated RAID volume */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif)typedef struct _sas_target_device_block {#pragma __nomember_alignment __union {N unsigned __int64 sas_targ$q_sas_address; /* 00h 00 */ __struct ^J {N unsigned int sas_targ$l_sas_address_lo; /* 00h 00 */N unsigned int sas_targ$l_sas_address_hi; /* 04h 04 *// } sas_targ$r_sas_address_longwords;' } sas_targ$r_sas_address_union; __union {N unsigned __int64 sas_targ$q_udid; /* 08h 08 */ __struct {N unsigned int sas_targ$l_udid_lo; /* 08h 08 */N unsigned int sas_targ$l_udid_hi; /* 0C _Jh 12 */( } sas_targ$r_udid_longwords; } sas_targ$r_udid_union;N unsigned __int64 sas_targ$q_highest_lbn; /* 10h 16 */N unsigned char sas_targ$b_wwname [60]; /* 18h 24 */N unsigned char sas_targ$b_wwname_len; /* 54h 84 */N unsigned char sas_targ$b_port; /* 55h 85 */N unsigned char sas_targ$b_target_id; /* 56h 86 */N `J unsigned char sas_targ$b_peripheral_dev_type; /* 57h 87 */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN __union { /* 58h 88 */#pragma __nomember_alignment __struct {N unsigned sas_targ$v_sas_device_type : 4; /* 0 */N unsigned sasaJ_targ$v_valid : 1; /* 4 */N unsigned sas_targ$v_connected : 1; /* 5 */N unsigned sas_targ$v_udid_capable : 1; /* 6 */N unsigned sas_targ$v_nvram_udid_capable : 1; /* 7 */N unsigned sas_targ$v_direct_attached : 1; /* 8 */N unsigned sas_targ$v_target_reset : 1; /* 9 */N unsigned sas_targ$v_da_with_encl_mgmt bJ: 1; /* 10 */, unsigned sas_targ$v_fill_0_ : 5;# } sas_targ$r_info_bits; __struct {N unsigned short int sas_targ$w_info_bitfield; /* 58h 88 */N unsigned short int sas_targ$w_reserved1; /* 5Ah 90 */, } sas_targ$r_bitfield_container;$ } sas_targ$r_bitfield_union;N unsigned short int sas_targ$w_parent; /* 5Ch 92 */N unsigned short int sas_targ$w_enclosure; / cJ* 5Eh 94 */N unsigned short int sas_targ$w_slot; /* 60h 96 */N unsigned short int sas_targ$w_start_slot; /* 62h 98 */N unsigned int sas_targ$l_reserved2; /* 64h 100 */ } SAS_TARGET_DEVICE_BLOCK; #if !defined(__VAXC)R#define sas_targ$q_sas_address sas_targ$r_sas_address_union.sas_targ$q_sas_addressf#define sas_targ$r_sas_address_longwords sas_targ$r_sas_address_union.sas_targ$r_sas_addredJss_longwords\#define sas_targ$l_sas_address_lo sas_targ$r_sas_address_longwords.sas_targ$l_sas_address_lo\#define sas_targ$l_sas_address_hi sas_targ$r_sas_address_longwords.sas_targ$l_sas_address_hi=#define sas_targ$q_udid sas_targ$r_udid_union.sas_targ$q_udidQ#define sas_targ$r_udid_longwords sas_targ$r_udid_union.sas_targ$r_udid_longwordsG#define sas_targ$l_udid_lo sas_targ$r_udid_longwords.sas_targ$l_udid_loG#define sas_targ$l_udid_hi sas_targ$r_udid_longwords.sas_targ$l_udid_hil#define eJsas_targ$v_sas_device_type sas_targ$r_bitfield_union.sas_targ$r_info_bits.sas_targ$v_sas_device_typeX#define sas_targ$v_valid sas_targ$r_bitfield_union.sas_targ$r_info_bits.sas_targ$v_valid`#define sas_targ$v_connected sas_targ$r_bitfield_union.sas_targ$r_info_bits.sas_targ$v_connectedf#define sas_targ$v_udid_capable sas_targ$r_bitfield_union.sas_targ$r_info_bits.sas_targ$v_udid_capabler#define sas_targ$v_nvram_udid_capable sas_targ$r_bitfield_union.sas_targ$r_info_bits.sas_targ$v_nvram_udid_capabfJlel#define sas_targ$v_direct_attached sas_targ$r_bitfield_union.sas_targ$r_info_bits.sas_targ$v_direct_attachedf#define sas_targ$v_target_reset sas_targ$r_bitfield_union.sas_targ$r_info_bits.sas_targ$v_target_resetp#define sas_targ$v_da_with_encl_mgmt sas_targ$r_bitfield_union.sas_targ$r_info_bits.sas_targ$v_da_with_encl_mgmt]#define sas_targ$r_bitfield_container sas_targ$r_bitfield_union.sas_targ$r_bitfield_containerW#define sas_targ$w_info_bitfield sas_targ$r_bitfield_container.sas_targ$w_infogJ_bitfieldO#define sas_targ$w_reserved1 sas_targ$r_bitfield_container.sas_targ$w_reserved1"#endif /* #if !defined(__VAXC) */ N/* Definitions used by both PKMDRIVER and EFI. */ /*< * Definition of SAS UDID record version numbers and format. */=static const char sas_udid_version_01_00[] = { 0x00, 0x01 };:/* LSB MSB; * minor major *//*6 * Storage required hJfor zero-terminated banner string. */Estatic const char efi_sas_udid_banner[] = "EFI SAS/SATA UDID record";Istatic const char vms_sas_udid_banner[] = "OpenVMS SAS/SATA UDID record";L/* 012345678901234567890123456789012I * |J * 29 bytes  *//*& * Disk-resident SAS UDID data record. */#define SAS_UDID_VERSION_SIZE iJ2#define SAS_UDID_BANNER_SIZE 38#define SAS_UDID_SYSTIME_SIZE 8#define SAS_UDID_VALUE_SIZE 8!typedef struct _sas_udid_record {) char version [SAS_UDID_VERSION_SIZE];' char banner [SAS_UDID_BANNER_SIZE];) char systime [SAS_UDID_SYSTIME_SIZE];$ char udid [SAS_UDID_VALUE_SIZE]; unsigned short int checksum;} SAS_UDID_RECORD;/*; * We only store UDIDs on disks with a 512-byte block size. */#define SAS_UDID_BLOCK_SIZE 512/*E * Block boundary and size of hidd jJen on-disk SAS UDID storage region. *M * We are hiding the highest logical blocks on the volume such that our UDID L * records plus the volume's secondary GUID Partition Table. The secondary L * GPT must reside in the volume's highest logical blocks. The size of our M * hidden region must be hard-coded and must never change, or the bitmaps of L * existing volumes would become incompatible with the apparent volume size. *N * The GPT consists of a header that occupies a single 512-byte bl kJock, and an M * array of GUID Partition Entries. Each GUID Partition Entry is either not P * in use, or describes one of the volume's partitions. Our hidden region must M * be large enough that increasing the number of partitions will never cause N * the table to overflow its space in the region. VMS currently provides for M * up to 128 GPTEs of the current GPTE size in the array. We should provide  * for a lot more than that. */@#define SAS_MAX_PARTITIONS 1024 /* Max elements in GPT lJE array */8#define SAS_GPTE_BYTES 128 /* Current size of a GPTE */@#define SAS_MAX_GPTE_BYTES (SAS_MAX_PARTITIONS * SAS_GPTE_BYTES)I#define SAS_MAX_GPTE_BLOCKS ((SAS_MAX_GPTE_BYTES / SAS_UDID_BLOCK_SIZE) \8 + ((SAS_MAX_GPTE_BYTES % SAS_UDID_BLOCK_SIZE) != 0)) #define SAS_GPT_HEADER_BLOCKS 1 H#define SAS_MAX_GPT_BLOCKS (SAS_GPT_HEADER_BLOCKS + SAS_MAX_GPTE_BLOCKS)/*M * Our hidden region consists of consecutive blocks containing UDID records, P * consecutive unused blocks, and the maximu mJm number of consecutive GPT blocks, ? * rounded up in size so it will start on a 2^n block boundary. */J#define SAS_UDID_BLOCK_BOUNDARY 8 /* Start on a 2^n block boundary */G#define SAS_UDID_UDID_BLOCKS 2 /* Blocks of UDID record data */I#define SAS_UDID_UNUSED_BLOCKS 2 /* Unused blocks between UDID and GPT */.#define SAS_UDID_GPT_BLOCKS SAS_MAX_GPT_BLOCKS5#define SAS_UDID_TOTAL_BLOCKS (SAS_UDID_UDID_BLOCKS \ + SAS_UDID_UNUSED_BLOCKS \ + SAS_UDID_GPT_BLOCKS)/*- *nJ Retrieve data from a SAS UDID data record. */C__inline static int sas_get_udid_record_data( void *p_udid_record, d void *p_version, void *p_banner, void *p_systime, void *p_udid, unsigned short int *p_checksum ){ SAS_UDID_RECORD record; char *p_data; unsigned long int checksum; unsigned long int limit; unsigned long int i;% unsigned short int checksum_word; union { unsigned short int word; unsigned char byte [2]; } checksum_data;F memc oJpy( (char *)&record, p_udid_record, sizeof(SAS_UDID_RECORD) );G memcpy( (char *)p_version, record.version, SAS_UDID_VERSION_SIZE );E strncpy( (char *)p_banner, record.banner, SAS_UDID_BANNER_SIZE );6 ((char *)p_banner)[SAS_UDID_BANNER_SIZE-1] = '\0';G memcpy( (char *)p_systime, record.systime, SAS_UDID_SYSTIME_SIZE );? memcpy( (char *)p_udid, record.udid, SAS_UDID_VALUE_SIZE );" *p_checksum = record.checksum;2 limit = offsetof( SAS_UDID_RECORD, checksum ); p_data =pJ (char *)&record; checksum = 0;" for( i = 0; i < limit; i++ ) { if( !(i & 1) ) { checksum_data.word = 0; if( (i + 1) < limit )( checksum_data.byte[1] = p_data[i + 1];' checksum_data.byte[0] = p_data[i];$ checksum += checksum_data.word; } }2 checksum_word = (unsigned short int) checksum;* if( checksum_word == record.checksum ) return 1; else return 0;}/*# * Populate a SAS UDID data record. */A__inline static void sas_build_udid_qJrecord( void *p_udid_record, d void *p_version, void *p_banner, void *p_systime, void *p_udid, unsigned short int *p_checksum ){ SAS_UDID_RECORD record; char *p_data; unsigned long int checksum; unsigned long int limit; unsigned long int i; union { unsigned short int word; unsigned char byte [2]; } checksum_data;G memcpy( record.version, (char *)p_version, SAS_UDID_VERSION_SIZE );E strncpy( record.banner, (char *)p_banner, SAS_UDID_BANNER_SIrJZE );1 record.banner[SAS_UDID_BANNER_SIZE-1] = '\0';G memcpy( record.systime, (char *)p_systime, SAS_UDID_SYSTIME_SIZE );? memcpy( record.udid, (char *)p_udid, SAS_UDID_VALUE_SIZE );2 limit = offsetof( SAS_UDID_RECORD, checksum ); p_data = (char *)&record; checksum = 0;" for( i = 0; i < limit; i++ ) { if( !(i & 1) ) { checksum_data.word = 0; if( (i + 1) < limit )( checksum_data.byte[1] = p_data[i + 1];' checksum_data.byte[0] = p_data[i];$ sJ checksum += checksum_data.word; } }4 record.checksum = (unsigned short int) checksum;" *p_checksum = record.checksum;F memcpy( p_udid_record, (char *)&record, sizeof(SAS_UDID_RECORD) );}/*L * Starting with the last logical block value in the RETURNED LOGICAL BLOCK H * ADDRESS field of the READ CAPACITY data, return the starting logical ? * block of the hidden on-disk SAS UDID and GPT storage region. */d__inline static unsigned long long sas_get_starting_udid_block( un tJsigned long long true_last_block ){+ unsigned long long starting_udid_block;. starting_udid_block = true_last_block + 1;1 starting_udid_block -= SAS_UDID_TOTAL_BLOCKS;3 starting_udid_block /= SAS_UDID_BLOCK_BOUNDARY;3 starting_udid_block *= SAS_UDID_BLOCK_BOUNDARY; return starting_udid_block;}/*L * Starting with the last logical block value in the RETURNED LOGICAL BLOCK J * ADDRESS field of the READ CAPACITY data, return the last logical block = * before the hi uJdden on-disk SAS UDID and GPT storage region. */d__inline static unsigned long long sas_get_last_non_udid_block( unsigned long long true_last_block ){+ unsigned long long last_non_udid_block;M last_non_udid_block = sas_get_starting_udid_block( true_last_block ) - 1; return last_non_udid_block;} $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore tvJhe previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SASDEVDEF_LOADED */ ww`>[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorizwJed to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated xJor disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: yJ 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */E/* Source: 14-JUN-1995 08:01:06 $1$DGA8345:[LIB_H.SRC]SBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SBDEF ***/#ifndef __SBDEF_LOADED#define __SBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE zJ /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else{J#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SB - SCS SYSTEM BLOCK */N/* */N/* THE SB HAS INFORMATION ABOUT KNOWN SYSTEMS IN A CPU CLUSTER. */N/*- |J */ #define SB$M_LOCAL 0x1 #define SB$M_LOCAL_DIRECTORY 0x2  9#ifdef __cplusplus /* Define structure prototypes */ struct _pb; struct _ddb; struct _csb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sb {#pragma __no}Jmember_alignmentN void *sb$l_flink; /*FWD LINK TO NEXT SB */N void *sb$l_blink; /*BACK LINK TO PREVIOUS SB */N unsigned short int sb$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char sb$b_type; /*SCS STRUCTURE TYPE */N unsigned char sb$b_subtyp; /*SCS STRUCT SUBTYPE FOR SB */N struct _pb *sb$l_pbfl; /*LINK TO NEXT PATH BLOCK */N stru~Jct _pb *sb$l_pbbl; /*LINK TO PREVIOUS PATH BLOCK */N struct _pb *sb$l_pbconnx; /*ADDR OF NEXT PB TO USE FOR */N/* A CONNECTION */N int sb$$_fill_2; /*PRESERVE QUADWORD ALIGNMENT */N unsigned char sb$b_systemid [6]; /*SYSTEM ID */N short int sb$$_fill_1; /*RESERVED WORD */N unsigned short int sb$w_maxdg;J /*MAXIMUM DATAGRAM SIZE */N unsigned short int sb$w_maxmsg; /*MAXIMUM MESSAGE SIZE */N char sb$t_swtype [4]; /*SOFTWARE TYPE, 1-4 CHAR */N char sb$t_swvers [4]; /*SOFTWARE VERSION, 1-4 CHAR */N unsigned __int64 sb$q_swincarn; /*SOFTWARE INCARNATION # */N char sb$t_hwtype [4]; /*HW TYPE; 1-4 CHAR, BLANK FILL */N unsigned char sb$b_hwvers [12]; /*HW VERSION # J */O char sb$t_nodename [16]; /*SCS NODENAME, COUNTED ASCII STRING */N struct _ddb *sb$l_ddb; /*DDB LIST HEAD */W short int sb$w_timeout; /*SCA PROCESS POLLER, WAITING TIME REMAINING */T unsigned char sb$b_enbmsk [2]; /*SCA PROCESS POLLER, PROCESS ENABLE MASK */P struct _csb *sb$l_csb; /*LINK TO NEWEST CLUSTER SYSTEM BLOCK */W unsigned int sb$l_port_map; /* (TYC 13-Feb-89) LOAD SH JARING PORT BIT MAP */ __union {N unsigned int sb$l_status; /* System block Status */ __struct {X unsigned sb$v_local : 1; /* System is a Local port, (A BVP or PU port) */q unsigned sb$v_local_directory : 1; /* System is a local port and supports local directory lookups. */& unsigned sb$v_fill_0_ : 6; } sb$r_status_bits; } sb$r_status_overlay;o void *sb$ps_proc_names; /* Pointer t Jo list of SYSAP process names supported by a local port. */N unsigned int sb$l_mount_lkid; /* Reserved */N void *sb$ps_allocls_list; /* Reserved */ } SB; #if !defined(__VAXC)3#define sb$l_status sb$r_status_overlay.sb$l_statusB#define sb$v_local sb$r_status_overlay.sb$r_status_bits.sb$v_localV#define sb$v_local_directory sb$r_status_overlay.sb$r_status_bits.sb$v_local_directory"#endif /* #if !defined(__VAXC) */ J N#define SB$K_LENGTH 120 /*LENGTH OF SB */N#define SB$C_LENGTH 120 /*LENGTH OF SB */N#define SB$S_SBDEF 120 /* Old size name - synonym */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus } J#endif#pragma __standard #endif /* __SBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior writteJn permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS SoJftware, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */G/* Source: 22-JUL-1997 13:39:13 J $1$DGA8345:[LIB_H.SRC]SBNBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SBNBDEF ***/#ifndef __SBNBDEF_LOADED#define __SBNBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_poiJnter_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if J!defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SBNB - SCA LOAD SHARING NAME BLOCK */N/* */N/* THIS DATA STRUCTURE DESCRIBES A PROCESS NAME KNOWN TO THE SCA */N/* DYNAMIC LOAD SHARING CODE. */N/*- J */ #define SBNB$K_LENGTH 36#define SBNB$C_LENGTH 36#define SBNB$S_SBNBDEF 36 typedef struct _sbnb {N struct _sbnb *sbnb$l_flink; /*FWD LINK */N struct _sbnb *sbnb$l_blink; /*BCK LINK */N unsigned short int sbnb$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char sbnb$b_type; /*SCS STRUCTURE TYPE */ JN unsigned char sbnb$b_subtyp; /*SCS STRUCTURE SUBTYPE FOR SBNB */N unsigned int sbnb$l_discon_count; /* # OF DISCONNECT */N/* DUE TO LOAD SHARING ACTIVITY */N unsigned char sbnb$b_procnam [16]; /*ASCII STRING FOR PROCESS NAME */Q unsigned short int sbnb$w_local_index; /*BIT ASSIGNED TO THIS PROCESS NAME */N unsigned short int sbnb$w_unused_1; /*WORD RESERVED FOR EXPANSION */ } SBNB; $#pJragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SBNBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/JM/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CJONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************************J**************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */F/* Source: 24-MAY-1993 14:06:35 $1$DGA8345:[LIB_H.SRC]SBODEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SBODEF ***/#ifndef __SBODEF_LOADED#define __SBODEF_LOADED J1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#definJe __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SBO - SCS CONFIG_SYS OUTPUT ARRAY FORMAT J */N/* */Y/* THE OUTPUT ARRAY RETURNED FROM CALL TO SCS$CONFIG_SYS. DATA IS MOSTLY COPIED FROM */N/* THE SYSTEM BLOCK (SB) BEING LOOKED UP. */N/*- */ N#define SBO$C_VC1 60 /*START OF 12 BYTE SPECIFIER OF */N#define SBO$K_VC1 60 /* 1ST VC (PATH BLK) TO SYSTEM */NJ#define SBO$K_LENGTH 80 /*LENGTH OF SBO ARRAY */N#define SBO$C_LENGTH 80 /*LENGTH OF SBO ARRAY */N#define SBO$S_SBODEF 80 /* Old size name - synonym */ typedef struct _sbo {N unsigned char sbo$b_systemid [6]; /*SYSTEM ID */N short int sbo$$_fill_1; /*RESERVED WORD */N unsigned short int sbo$w_maxdg; /*MAXIMUM DG SIZE */JN unsigned short int sbo$w_maxmsg; /*MAXIMUM MSG SIZE */N char sbo$t_swtype [4]; /*SW TYPE, 1-4 CHAR, BLNK FILL */N char sbo$t_swvers [4]; /*SW VERSION, 1-4 CHAR, BLNK FILL */N unsigned __int64 sbo$q_swincarn; /*SW INCARNATION # */N char sbo$t_hwtype [4]; /*HW TYPE, 1-4 CHAR BLNK FILL */N unsigned char sbo$b_hwvers [12]; /*HW VERSION, 1-4 CHAR BLNK FILL */N char sbo$t_nodename J[16]; /*NODE NAME, COUNTED ASCII STRING */N unsigned char sbo$b_rstation1 [6]; /*REMOTE STATION OF 1ST VC */N short int sbo$$_fill_2; /*RESERVED WORD */N char sbo$t_lport1 [4]; /*LOCAL PORT NAME OF 1ST VC */O unsigned char sbo$b_nxt_sysid [6]; /*ID OF NEXT SYSTEM IN CONFIGURATION */N short int sbo$$_fill_3; /*RESERVED WORD */ } SBO; $#pragma __member_alignment __resJtoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SBODEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This sofJtware is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is coJnfidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//* J*******************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */I/* Source: 04-APR-2008 00:52:47 $1$DGA8345:[LIB_H.SRC]SCAMGTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SCAMGTDEF ***/#ifndef __SCAMGTDEF_LOADED#define __SCAMGTDEF_LOADED 1 G#pragma __no Jstandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params J...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Some common Response Status Codes. */N/* J */N#define PEMGT$K_STS_NO_SUCH_PORT 129 /* No such port (PE_PORT not found) */N#define PEMGT$K_STS_CONT_NOT_VALID 130 /* Continuation data not valid */N#define PEMGT$K_STS_CONT_STALE 131 /* Continuation data stale */[#define PEMGT$K_STS_CONT_WITH_HINT 132 /* Continuation data supplied with non-zero hint */V#define PEMGT$K_STS_CONT_DISALLOWED 133 /* Continuation data disallowed for request */N#define PEMGT$JK_STS_CONT_LOST 134 /* Continuation point not found */b#define PEMGT$K_STS_INCOMP_REQ 135 /* Incomplete request (buffer contains partial request) */N#define PEMGT$K_STS_NAME_NOT_FOUND 136 /* Name (VC, CH, BUS) not found */\#define PEMGT$K_STS_INVALID_NAME 137 /* Invalid name (VC, CH, BUS)(partial name given) */N#define PEMGT$K_STS_PAR_REJECTED 138 /* Parameter change rejected */O#define PEMGT$K_STS_PAR_NOT_IMP 139 /* Parameter setting not implemented */N#defJine PEMGT$K_STS_NO_DATA_FOUND 140 /* No data found */N#define PEMGT$K_STS_IP_NOT_INIT 141 /* IP communication not intialized */N/* */N/* Common SCA driver codes */N/* Here we carve up the SCA object action code space. */N/* We will allow 64 SCA object specific codes and */N/* 64 common SCA codes. So we Jlimit use of the code */N/* space to the first 128 action codes */N/* */N#define SCAMGT$K_PORT_GET 65 /* Get PORT data */N#define SCAMGT$K_CIRC_GET 66 /* Get CIRCUIT data */N#define SCAMGT$K_PORT_SET_PRIORITY 67 /* Set PORT priority */N#define SCAMGT$K_CIRC_SET_PRIORITY 68 /* Set CIRCUIT p Jriority */N/* First SCA common action code */&#define SCAACT$K_SCA_FIRST_SCA_CODE 64N/* Number of SCA common action codes */%#define SCAACT$K_SCA_NUM_SCA_CODES 64N/* */N/* PORTNAM$ -- PORT name - Handle for a PORT structure */N/* */N#d Jefine PORTNAM$K_LENGTH 16 /* PORTNAM$ length */ typedef struct _portnam {N unsigned char portnam$t_portname [8]; /* ASCIC PORT device name */W unsigned char portnam$b_port_sel; /* Selection value: 0 - Include, 1 - Exclude */N char portnam$t_port_fill [7]; /* Fill to lquadword boundary */ } PORTNAM;N/* */N/* CIRCNAM$ -- Circuit name - Handle for a Circuit J (Path) structure */N/* */N#define CIRCNAM$K_LENGTH 48 /* CIRCNAM$ length */ typedef struct _circnam {N unsigned char circnam$t_nodename [16]; /* ASCIC remote system name */N unsigned char circnam$t_portname [16]; /* Handle for circuit port */ __union {V unsigned __int64 circnam$q_rstation_num; /* Remote station ID disambiguator */2 unsigned chaJr circnam$t_rstation_char [8];% } circnam$r_rstation_overlay;W unsigned char circnam$b_circ_sel; /* Selection value: 0 - Include, 1 - Exclude */U unsigned char circnam$b_rstation_set; /* Flag: 0 - Rstation_num is not valid, */N/* 1 - RSTATION_NUM is valid. */N/* Needed because 0 is a valid remote station */N/* number. */N char circnam J$t_circ_fill [6]; /* Fill to quadword boundary */ } CIRCNAM; #if !defined(__VAXC)P#define circnam$q_rstation_num circnam$r_rstation_overlay.circnam$q_rstation_numR#define circnam$t_rstation_char circnam$r_rstation_overlay.circnam$t_rstation_char"#endif /* #if !defined(__VAXC) */ N/* */N/* CIRCACT$ -- Circuit Management action structure */N/* J */N#define CIRCACT$K_MAJOR 1 /* CIRCACT$ minor version */N#define CIRCACT$K_MINOR 1 /* CIRCACT$ major version */N#define CIRCACT$K_ACT_PARAMS_V1_1_LEN 8 /* V1.1 CIRC ACT_PARAMS size */N#define CIRCACT$K_MIN_LEN 8 /* CIRCACT$ length */N/* */N#define CIRCACT$R_SELCIRCS 8 /* Start of the CIRC J names */ typedef struct _circact {Z __struct { /* Parameters describing action to be performed */N unsigned char circact$b_act_par_len; /* Length of ACT_PARAMS record */N char circact$t_act_par_fill [3]; /* Fill to longword boundary */N/* */N/* CIRC parameters. */N/* J */ __union {N unsigned int circact$l_params; /* Force longword minimum size */Y unsigned char circact$b_new_mgt_priority; /* Priority value to be assigned */( } circact$r_act_par_overlay; } circact$r_act_params;N/* CIRC selection array. */N/* */ } CIRCACT; #if !defined(__VAXC)JH#define circact$b_act_par_len circact$r_act_params.circact$b_act_par_lenX#define circact$l_params circact$r_act_params.circact$r_act_par_overlay.circact$l_paramsl#define circact$b_new_mgt_priority circact$r_act_params.circact$r_act_par_overlay.circact$b_new_mgt_priority"#endif /* #if !defined(__VAXC) */ N/* */N/* PORTACT$ -- Port management action structure */N/* J */N#define PORTACT$K_MAJOR 1 /* PORTACT$ minor version */N#define PORTACT$K_MINOR 1 /* PORTACT$ major version */N#define PORTACT$K_ACT_PARAMS_V1_1_LEN 8 /* V1.1 PORT ACT_PARAMS size */N#define PORTACT$K_MIN_LEN 8 /* PORTACT$ length */N/* */N#define PORTACT$R_SELPORTS 8 /* Start of the JPORT identifier */ typedef struct _portact {Z __struct { /* Parameters describing action to be performed */N unsigned char portact$b_act_par_len; /* Length of ACT_PARAMS record */N char portact$t_act_par_fill [3]; /* Fill to longword boundary */N/* */N/* PORT parameters. */N/* J */ __union {N unsigned int portact$l_params; /* Force longword minimum size */Y unsigned char portact$b_new_mgt_priority; /* Priority value to be assigned */( } portact$r_act_par_overlay; } portact$r_act_params;N/* PORT selection array. */N/* */ } PORTACT; #if !defined(__V JAXC)H#define portact$b_act_par_len portact$r_act_params.portact$b_act_par_lenX#define portact$l_params portact$r_act_params.portact$r_act_par_overlay.portact$l_paramsl#define portact$b_new_mgt_priority portact$r_act_params.portact$r_act_par_overlay.portact$b_new_mgt_priority"#endif /* #if !defined(__VAXC) */ N/* *********************************************************************** */N/* */N/* Responses to actions onJ port/path Circuits */N/* */N/* *********************************************************************** */N#define PORTDAT$K_MAJOR 1 /* PORTDAT$ major version */N#define PORTDAT$K_MINOR 1 /* PORTDAT$ minor version */N#define PORTDAT$K_V1_1_LEN 72 /* PORTDAT$ length for: */N/* major version = 1 J */#define PORTDAT$K_LENGTH 72 typedef struct _portdat {- unsigned char portdat$r_port_handle [16];Q int portdat$l_mgt_priority; /* Current management priority setting */" unsigned int portdat$l_dg_xmt;" unsigned int portdat$l_dg_rcv;# unsigned int portdat$l_msg_xmt;# unsigned int portdat$l_msg_rcv;# unsigned int portdat$l_num_map;( unsigned int portdat$l_bytes_mapped; unsigned int portdat$l_pdt;N unsigned int portdJat$l_load_class; /* Port's Load Class */V unsigned int portdat$l_bytes_dg_xmt_peak; /* Peak value of total bytes xmitted */N/* by port for DG only */T unsigned int portdat$l_bytes_dg_rcv_peak; /* Peak value of total bytes rcv'd */N/* by port for DG only */W unsigned int portdat$l_bytes_msg_xmt_peak; /* Peak value of total bytes xmitted */N/* by port for MSG onlyJ */U unsigned int portdat$l_bytes_msg_rcv_peak; /* Peak value of total bytes rcv'd */N/* by port for MSG only */U unsigned int portdat$l_bytes_mapped_peak; /* Peak value of total bytes mapped */N/* by port for BT only */N/* minor version = 1 */W/* NOTE: When making additions to Jthis structure you must do the following to ensure */I/* interoperability with prior AM & SCACP versions: */Z/* - Additional cells must only be added at the end of the currently defined cells. */K/* ie: After the most recent 'constant Vn_n_LEN...' declaration, and */I/* immediately preceding this note. The VCDAT$K_MINOR must be */K/* incremented. Otherwise, the major version (VCDAT$K_MAJOR) must be */I/* incremented, and the minor version reset toJ 0. */T/* A constant defining the end of the cells contained in the new version must */Q/* also be added. The constant's name must be defined using this template: */B/* VCDAT$K_V#major_#minor_LEN */ } PORTDAT;N#define CIRCDAT$K_MAJOR 1 /* CIRCDAT$ minor version */N#define CIRCDAT$K_MINOR 1 /* CIRCDAT$ major version */N/* J */N#define CIRCDAT$K_V1_1_LEN 64 /* CIRCDAT$ length for: */N/* major version = 1 */#define CIRCDAT$K_LENGTH 64 typedef struct _circdat {N/* CIRCUIT name. */N/* */N unsigned char circdat$t_nodename [16]; /* ASCIC remote system name */N unsigned char circdat$t_po Jrtname [16]; /* Handle for circuit port */) unsigned char circdat$b_rstation [6];N char circdat$t_circ_fill1 [2]; /* Fill to longword boundary */' unsigned short int circdat$w_state;N char circdat$t_circ_fill2 [2]; /* Fill to longword boundary */' unsigned int circdat$l_remote_type; int circdat$l_priority;Q int circdat$l_mgt_priority; /* Current management priority setting */N unsigned int circdat$l_load_class; /* Circuit's cJurrent load class. */N unsigned int circdat$l_rstate; /* Remote port's current state. */N/* minor version = 1 */W/* NOTE: When making additions to this structure you must do the following to ensure */I/* interoperability with prior AM & SCACP versions: */Z/* - Additional cells must only be added at the end of the currently defined cells. */K/* ie: After the most recent 'constant Vn_n_LEN...' declar Jation, and */I/* immediately preceding this note. The VCDAT$K_MINOR must be */K/* incremented. Otherwise, the major version (VCDAT$K_MAJOR) must be */I/* incremented, and the minor version reset to 0. */T/* A constant defining the end of the cells contained in the new version must */Q/* also be added. The constant's name must be defined using this template: */B/* VCDAT$K_V#major_#minor_LEN */ } CIRCDAT; $#pJragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SCAMGTDEF_LOADED */ wwO[UM/***************************************************************************/M/** **J/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC.J CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************************************J****************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SCBDEF ***/#ifndef __SCBDEF_LOADED#define __SCBDEF_LOADEJD 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#defJine __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* J */N/* Format of storage control block, Files-11 Structure Level 2 */N/* */N/*- */ N#define SCB$C_LEVEL2 512 /* 1000 octal = structure level 2 */N#define SCB$C_LEVEL5 1280 /* 2400 octal = structure level 5 */N#define SCB$C_LEVEL6 1536 /* 3000 octal = structure level 6 */#define SCJB$M_MAPDIRTY 0x1#define SCB$M_MAPALLOC 0x2#define SCB$M_FILALLOC 0x4#define SCB$M_QUODIRTY 0x8#define SCB$M_HDRWRITE 0x10#define SCB$M_CORRUPT 0x20#define SCB$M_MAPDIRTY2 0x1#define SCB$M_MAPALLOC2 0x2#define SCB$M_FILALLOC2 0x4#define SCB$M_QUODIRTY2 0x8#define SCB$M_HDRWRITE2 0x10#define SCB$M_CORRUPT2 0x20#define SCB$M_NORMAL 0x1#define SCB$M_NEW 0x2#define SCB$M_COPYING 0x20#define SCB$M_MERGING 0x40#define SCB$M_MINIMRG 0x80#define SCB$M_COPY_RESET 0x100J#define SCB$M_BOOTING 0x200#define SCB$M_SCB_WLG 0x400#define SCB$M_MUST_MRG 0x4000#define SCB$M_FAILED 0x8000#define SCB$M_CPY_RESET 0x100#define SCB$M_WLG 0x400#define SCB$M_MBR_FCPY 0x1#define SCB$M_MBR_MERGE 0x2#define SCB$M_MBR_CIP 0x4#define SCB$M_MBR_SRC 0x20#define SCB$M_MBR_MFCPY 0x40#define SCB$M_MBR_VALID 0x80#define SCB$M_INIT_NO_ERASE 0x1#define SCB$M_DVE_ENABLED 0x2)#define SCB$M_HBVS_MEMBERS_MAY_DIFFER 0x4N#define SCB$K_LENGTH 512 /* JLength of Structure */N#define SCB$C_LENGTH 512 /*Length of Structure */ typedef struct _scbdef { __union {N unsigned short int scb$w_struclev; /* file structure level */ __struct {N unsigned char scb$b_strucver; /* file structure version */O unsigned char scb$b_struclev; /* principal file structure level */$ } scb$r_struclev_fields;! } scb$r_struclev_overlay;N Junsigned short int scb$w_cluster; /* storage map cluster factor */N unsigned int scb$l_volsize; /* volume size in logical blocks */Z unsigned int scb$l_blksize; /* number of physical blocks per logical block */N unsigned int scb$l_sectors; /* number of sectors per track */N unsigned int scb$l_tracks; /* number of tracks per cylinder */N unsigned int scb$l_cylinder; /* number of cylinders */ __union {N J unsigned int scb$l_status; /* volume status flags */ __struct {X unsigned scb$v_mapdirty : 1; /* storage map is dirty (partially updated) */Y unsigned scb$v_mapalloc : 1; /* storage map is preallocated (lost blocks) */a unsigned scb$v_filalloc : 1; /* file numbers are preallocated (lost header slots) */W unsigned scb$v_quodirty : 1; /* quota file is dirty (partially updated) */R unsigned scb$v_hdrwrit Je : 1; /* file headers are write back cached */N unsigned scb$v_corrupt : 1; /* file structure is corrupt */' unsigned scb$v_fill_9_ : 2; } scb$r_status_bits; } scb$r_status_overlay; __union {Z unsigned int scb$l_status2; /* backup status - bits must match those above */ __struct {Y unsigned scb$v_mapdirty2 : 1; /* storage map is dirty (partially updated) */Z unsigned scb$v_mapalloc2 : 1; /*J storage map is preallocated (lost blocks) */b unsigned scb$v_filalloc2 : 1; /* file numbers are preallocated (lost header slots) */X unsigned scb$v_quodirty2 : 1; /* quota file is dirty (partially updated) */S unsigned scb$v_hdrwrite2 : 1; /* file headers are write back cached */N unsigned scb$v_corrupt2 : 1; /* file structure is corrupt */( unsigned scb$v_fill_10_ : 2;! } scb$r_status2_bits; } scb$r_status2_Joverlay;N unsigned short int scb$w_writecnt; /* count of write access mounters. */` char scb$t_volockname [12]; /* name used for file system serialization on volume. */N unsigned __int64 scb$q_mounttime; /* time of last initial mount. */N unsigned short int scb$w_backrev; /* BACKUP revision number. */N unsigned __int64 scb$q_genernum; /* shadow set revision number. */N unsigned __int64 scb$q_unit_id; /* Virtual Unit specifier */J __union {N unsigned short int scb$w_shadow_status; /* Volume status: */N unsigned short int scb$w_status; /* Duplicate pointer to status */ __struct {N unsigned scb$v_normal : 1; /* Shadow set populated and online */N unsigned scb$v_new : 1; /* Newly created, no members yet */N unsigned scb$v_filler_sts_1 : 3; /* */N unsigned scb$v_copying : 1; /* Copy State J */N unsigned scb$v_merging : 1; /* Merge State */N unsigned scb$v_minimrg : 1; /* Mini Merge in progress */N unsigned scb$v_copy_reset : 1; /* Reset Shadow Server Copy mode */U unsigned scb$v_booting : 1; /* System Disk shadow set in booting state */N unsigned scb$v_scb_wlg : 1; /* Write Logging Phase 1 enabled */N unsigned scb$v_filler_sts_2 : 3; /* Reserved */N J unsigned scb$v_must_mrg : 1; /* This set requires a full merge */N unsigned scb$v_failed : 1; /* Shadow set not populated */' } scb$r_shadow_status_bits; __struct {+ unsigned scb$v_filler_rfb1 : 8;N unsigned scb$v_cpy_reset : 1; /* Copy mode is reset */+ unsigned scb$v_filler_rfb2 : 1;N unsigned scb$v_wlg : 1; /* Write logging */+ unsigned scb$v_filler_ Jrfb3 : 5;$ } scb$r_status_bits_ing;& } scb$r_shadow_status_overlay; __union {N unsigned char scb$b_member_status; /* Member status bytes */ __struct {N unsigned scb$v_mbr_fcpy : 1; /* Member involved in copy */N unsigned scb$v_mbr_merge : 1; /* Member requires a merge */U unsigned scb$v_mbr_cip : 1; /* Copy (or merge) in progress on this SSM */N unsigned scb$v_spare_mbr_status3 : 1; J/* Reserved */N unsigned scb$v_spare_mbr_status4 : 1; /* Reserved */S unsigned scb$v_mbr_src : 1; /* Member can be used as a source member */N unsigned scb$v_mbr_mfcpy : 1; /* Minimum copy target member */O unsigned scb$v_mbr_valid : 1; /* SSM status information is valid */' } scb$r_member_status_bits;* } scb$r_member_status_overlay [3];N char scb$b_filler_jja [1]; /* Reserved for alignmJent */R unsigned short int scb$w_scb_mbz; /* Historically cleared by UPDATE_DISKS */N unsigned __int64 scb$q_member_ids [3]; /* Unit ID for member */N unsigned int scb$l_scb_lbn; /* Unit Control Block for VU */N unsigned char scb$b_devices; /* Number of devices in SS */N unsigned char scb$b_members; /* Number of source members */N unsigned char scb$b_mast_indx; /* Array index to Master SSM */N Junsigned char scb$b_mrg_targets; /* Active Merge Targets */N unsigned char scb$b_fc_targets; /* Active Copy Targets */N unsigned char scb$b_decram_mbrs; /* Number of DECram devices */N char scb$b_filler_jja1 [10]; /* Reserved for alignment */k unsigned __int64 scb$q_mbz_v731_placeholder; /* WHL_FILE_START quadword unsigned; was the old name */N/* N.B. The low longword of this cell MUST remain */IJ/* defined to prevent latent (HSG80MM) support */I/* that shipped in MOUNT96 for V73-1 from making */I/* the wrong decision */c unsigned __int64 scb$q_hbvs_write_count; /* Count of systems that have set enabled for write */N unsigned int scb$l_valblk_offset; /* Offset for MOS VALBLK */p unsigned __int64 scb$q_consistency_timestamp; /* HBVS - SYSTIME value when a multiple member J virtual unit */N/* is considered to be in that state */W unsigned __int64 scb$q_hbmc_original_gn; /* Mini Copy initial Generation Number */ __union {N unsigned char scb$b_xmember_status; /* XMBRS Project */, } scb$r_xmember_status_overlay [16];, unsigned __int64 scb$q_xmember_ids [16];N char scb$b_reserved [204]; /* reserved */ __union {N unsigned short int scb$w_sJhadowing_status; /* Volume status: */ __struct {Z unsigned scb$v_init_no_erase : 1; /* Shadow set created without INIT /ERASE */N unsigned scb$v_dve_enabled : 1; /* Volume is DVE capable */m unsigned scb$v_hbvs_members_may_differ : 1; /* HBVS virtual unit VOLSIZE has been increased */N unsigned scb$v_filler_shadowing : 13; /* Reserved */* } scb$r_shadowing_status_bits;) } scb$r_shadowing_stat Jus_overlay;N unsigned short int scb$w_checksum; /* block checksum */ } SCBDEF; #if !defined(__VAXC)<#define scb$w_struclev scb$r_struclev_overlay.scb$w_struclevR#define scb$b_strucver scb$r_struclev_overlay.scb$r_struclev_fields.scb$b_strucverR#define scb$b_struclev scb$r_struclev_overlay.scb$r_struclev_fields.scb$b_struclev6#define scb$l_status scb$r_status_overlay.scb$l_statusL#define scb$v_mapdirty scb$r_status_overlay.scb$r_status_bits.scb$v_mapdirtyL#definJe scb$v_mapalloc scb$r_status_overlay.scb$r_status_bits.scb$v_mapallocL#define scb$v_filalloc scb$r_status_overlay.scb$r_status_bits.scb$v_filallocL#define scb$v_quodirty scb$r_status_overlay.scb$r_status_bits.scb$v_quodirtyL#define scb$v_hdrwrite scb$r_status_overlay.scb$r_status_bits.scb$v_hdrwriteJ#define scb$v_corrupt scb$r_status_overlay.scb$r_status_bits.scb$v_corrupt9#define scb$l_status2 scb$r_status2_overlay.scb$l_status2P#define scb$v_mapdirty2 scb$r_status2_overlay.scb$r_status2_bitsJ.scb$v_mapdirty2P#define scb$v_mapalloc2 scb$r_status2_overlay.scb$r_status2_bits.scb$v_mapalloc2P#define scb$v_filalloc2 scb$r_status2_overlay.scb$r_status2_bits.scb$v_filalloc2P#define scb$v_quodirty2 scb$r_status2_overlay.scb$r_status2_bits.scb$v_quodirty2P#define scb$v_hdrwrite2 scb$r_status2_overlay.scb$r_status2_bits.scb$v_hdrwrite2N#define scb$v_corrupt2 scb$r_status2_overlay.scb$r_status2_bits.scb$v_corrupt2K#define scb$w_shadow_status scb$r_shadow_status_overlay.scb$w_shadow_status=#dJefine scb$w_status scb$r_shadow_status_overlay.scb$w_statusV#define scb$v_normal scb$r_shadow_status_overlay.scb$r_shadow_status_bits.scb$v_normalP#define scb$v_new scb$r_shadow_status_overlay.scb$r_shadow_status_bits.scb$v_newX#define scb$v_copying scb$r_shadow_status_overlay.scb$r_shadow_status_bits.scb$v_copyingX#define scb$v_merging scb$r_shadow_status_overlay.scb$r_shadow_status_bits.scb$v_mergingX#define scb$v_minimrg scb$r_shadow_status_overlay.scb$r_shadow_status_bits.scb$v_minimrg^#defJine scb$v_copy_reset scb$r_shadow_status_overlay.scb$r_shadow_status_bits.scb$v_copy_resetX#define scb$v_booting scb$r_shadow_status_overlay.scb$r_shadow_status_bits.scb$v_bootingX#define scb$v_scb_wlg scb$r_shadow_status_overlay.scb$r_shadow_status_bits.scb$v_scb_wlgZ#define scb$v_must_mrg scb$r_shadow_status_overlay.scb$r_shadow_status_bits.scb$v_must_mrgV#define scb$v_failed scb$r_shadow_status_overlay.scb$r_shadow_status_bits.scb$v_failedY#define scb$v_cpy_reset scb$r_shadow_status_overlay.sc Jb$r_status_bits_ing.scb$v_cpy_resetM#define scb$v_wlg scb$r_shadow_status_overlay.scb$r_status_bits_ing.scb$v_wlg/#define scb$b_member_status scb$b_member_status>#define scb$v_mbr_fcpy scb$r_member_status_bits.scb$v_mbr_fcpy@#define scb$v_mbr_merge scb$r_member_status_bits.scb$v_mbr_merge<#define scb$v_mbr_cip scb$r_member_status_bits.scb$v_mbr_cip<#define scb$v_mbr_src scb$r_member_status_bits.scb$v_mbr_src@#define scb$v_mbr_mfcpy scb$r_member_status_bits.scb$v_mbr_mfcpy@#define scb$v_mbr_Jvalid scb$r_member_status_bits.scb$v_mbr_valid1#define scb$b_xmember_status scb$b_xmember_statusT#define scb$w_shadowing_status scb$r_shadowing_status_overlay.scb$w_shadowing_statusj#define scb$v_init_no_erase scb$r_shadowing_status_overlay.scb$r_shadowing_status_bits.scb$v_init_no_erasef#define scb$v_dve_enabled scb$r_shadowing_status_overlay.scb$r_shadowing_status_bits.scb$v_dve_enabled~#define scb$v_hbvs_members_may_differ scb$r_shadowing_status_overlay.scb$r_shadowing_status_bits.scb$v_hbvs_Jmembers_may_differ"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SCBDEF_LOADED */ ww[UM/***************************************************************************/M/** J **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** J **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** J **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */H/* Source: 09-JUL-2022 00:08:55 $1$DGA8345:[LIB_H.SRC]SCDRPDEF.SDL;1 *//********************************************************************************************************************************//*** M JODULE $SCDRPDEF ***/#ifndef __SCDRPDEF_LOADED#define __SCDRPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif J#ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ J */N/* SCDRP - SCSI Class Driver I/O Request Packet */N/* */N/* This structure contains SCSI class driver request packet, which is used */N/* to pass parameters between the SCSI class and port drivers. In addition, */N/* the drivers use it to save information temporarily during the execution */N/* of a SCSI command. */N/* J */N/* Note: Unlike the class driver request packet (CDRP), this structure does */R/* NOT contain an IRP accessed at negative offsets from the base of the packet. */N/* Instead, several IRP fields used in the SCDRP are located at positive */N/* offsets from the base. */N/* */V/* ***NOTE1:**** New SCDRP fields must be Jentered at the end of the data structure. */N/* */N/* ***NOTE:**** If an INCOMPATIBLE CHANGE is made to this structure bump */B/* the version number of this structure. */N/*- */ N#define SCDRP$C_VERSION 8 /* Compatible version number. */#define SCDRP$K_SCDRPBASE 0#define SCDRP$C_SCDRPBASE 0N#define JSCDRP$K_QCHAR_UNORDERED 0 /* Device may reorder in queue */N#define SCDRP$K_QCHAR_ORDERED 1 /* Queue barrier for device */T#define SCDRP$K_QCHAR_HEAD 2 /* Move this I/O to the head of the queue */N#define SCDRP$K_QCHAR_NOT_QUEUED 3 /* Sent untagged as in SCSI-1 */N#define SCDRP$K_QCHAR_ACA 4 /* Automatic Contigent Allegiance */#define SCDRP$M_FLAG_S0BUF 0x1&#define SCDRP$M_FLAG_BUFFER_MAPPED 0x2%#define SCDRP$M_FLAG_DISK_SPUN_UP 0xJ4#define SCDRP$M_FLAG_LOCK 0x8##define SCDRP$M_FLAG_QUEUED_IO 0x10 #define SCDRP$M_FLAG_ACA_IO 0x20'#define SCDRP$M_FLAG_CLEAR_ACA_MSG 0x40&#define SCDRP$M_FLAG_ASENSE_VALID 0x80(#define SCDRP$M_FLAG_ON_PORT_QUEUE 0x100'#define SCDRP$M_FLAG_ON_DEV_QUEUE 0x200(#define SCDRP$M_FLAG_ABORT_THIS_IO 0x400*#define SCDRP$M_FLAG_QUEUE_FULL_INIT 0x800+#define SCDRP$M_FLAG_QUEUE_FULL_SEEN 0x1000'#define SCDRP$M_FLAG_WAIT_FOR_IO 0x2000,#define SCDRP$M_FLAG_INTERNAL_REQUEST 0x4000-#define SCDR JP$M_FLAG_SEND_MESSAGE_ONLY 0x8000.#define SCDRP$M_FLAG_SEND_DEVICE_RESET 0x10000'#define SCDRP$M_FLAG_MODE_SENSE 0x60000,#define SCDRP$M_FLAG_CL_PRIVATE_BUFF 0x80000%#define SCDRP$M_FLAG_TENBYTE 0x100000'#define SCDRP$M_FLAG_BUS_RESET 0x200000*#define SCDRP$M_FLAG_ON_SYS_QUEUE 0x400000)#define SCDRP$M_FLAG_ON_FP_QUEUE 0x800000*#define SCDRP$M_FLAG_RBUN_WANTED 0x1000000&#define SCDRP$M_FLAG_EXT_LUN 0x20000000#define SCDRP$M_FLAG_MEDIUM_NOTPRESENT 0x4000000.#define SCDRP$M_FLAG_ON_CREDIT J_QUEUE 0x8000000/#define SCDRP$M_FLAG_TIME_STAMP_RSCC 0x10000000%#define SCDRP$M_FLAG_READY 0x20000000(#define SCDRP$M_FLAG_FP_SCDRP 0x40000000*#define SCDRP$M_FLAG_CLASS_IOBD 0x80000000N#define SCDRP$S_FP_SCDRP 144 /* Moved for X-36c */N/* */#define SCDRP$M_DSF_NOWAIT 0x1)#define SCDRP$M_DSF_RELEASE_SPDT_LOCK 0x2(#define SCDRP$M_DSF_DEVICE_WAS_RESET 0x4'#define SCDRP$M_DSF_REQUEST_ABORTEJD 0x8(#define SCDRP$M_DSF_REQUEST_FLUSHED 0x10+#define SCDRP$M_DSF_STALL_WFIKPCH_DIPL 0x20!#define SCDRP$M_MSGO_IDENTIFY 0x1"#define SCDRP$M_MSGO_QUEUE_TAG 0x2!#define SCDRP$M_MSGO_SYNC_OUT 0x4)#define SCDRP$M_MSGO_BUS_DEVICE_RESET 0x8*#define SCDRP$M_MSGO_MSG_PARITY_ERROR 0x10"#define SCDRP$M_MSGO_ID_ERROR 0x20#define SCDRP$M_MSGO_ABORT 0x40#define SCDRP$M_MSGO_NOP 0x80)#define SCDRP$M_MSGO_MESSAGE_REJECT 0x100$#define SCDRP$M_MSGO_CLEAR_ACA 0x200##define SCDRP$M_MSGO_LAST_BIT J0x400 #define SCDRP$M_MSGI_SYNC_IN 0x1 #define SCDRP$M_EVENT_PARERR 0x1 #define SCDRP$M_EVENT_BSYERR 0x2 #define SCDRP$M_EVENT_MISPHS 0x4 #define SCDRP$M_EVENT_BADPHS 0x8#define SCDRP$M_EVENT_RST 0x10!#define SCDRP$M_EVENT_CTLERR 0x20!#define SCDRP$M_EVENT_BUSERR 0x40 #define SCDRP$M_EVENT_ABORT 0x80"#define SCDRP$M_EVENT_MSGERR 0x100!#define SCDRP$M_CNX_ABORT_PND 0x1"#define SCDRP$M_CNX_ABORT_CMPL 0x2$#define SCDRP$M_CNX_ABORT_INPROG 0x4##define SCDRP$M_CNX_ABORT_RESEL 0x8"#definJe SCDRP$M_CNX_PND_RESEL 0x10#define SCDRP$M_CNX_DSCN 0x20 #define SCDRP$M_CNX_TMODSCN 0x40!#define SCDRP$M_PHASE_DATAOUT 0x1 #define SCDRP$M_PHASE_DATAIN 0x2#define SCDRP$M_PHASE_CMD 0x4#define SCDRP$M_PHASE_STS 0x8#define SCDRP$M_PHASE_INV1 0x10#define SCDRP$M_PHASE_INV2 0x20!#define SCDRP$M_PHASE_MSGOUT 0x40 #define SCDRP$M_PHASE_MSGIN 0x80#define SCDRP$M_PHASE_ARB 0x100#define SCDRP$M_PHASE_SEL 0x200!#define SCDRP$M_PHASE_RESEL 0x400"#define SCDRP$M_PHASE_DISCON 0x800J%#define SCDRP$M_PHASE_CMD_CMPL 0x1000&#define SCDRP$M_PHASE_TMODISCON 0x2000!#define SCDRP$M_PHASE_FREE 0x4000#define SCDRP$K_SCSI_LEN 464#define SCDRP$C_SCSI_LEN 464#define SCDRP$K_SCSI_V73 1#define SCDRP$C_SCSI_V73 1#define SCDRP$K_LENGTH 584#define SCDRP$C_LENGTH 584  9#ifdef __cplusplus /* Define structure prototypes */ struct _fkb; struct _irp; struct _kpb; struct _spdt;struct _scsi_rbun;struct _fcp_rbun;struct _pkq_rbun; struct _rbun; struct _cdt; Jstruct _scdt; struct _ucb; struct _iobd; struct _ext; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _scdrp {#pragma __nomember_alignmentN struct _fkb *scdrp$l_fqfl; /*O Fork Queue FLINK */N struct _fkb *scdrp$l_fqbl; /*O Fork Queue Blink */U J unsigned short int scdrp$w_scdrpsize; /*I Size field for positive section only */N unsigned char scdrp$b_cd_type; /*I Type, always of interest */N unsigned char scdrp$b_flck; /*O Fork lock index */N void (*scdrp$l_fpc)(); /*O Fork PC */N __int64 scdrp$q_fr3; /*O Fork R3 */N __int64 scdrp$q_fr4; /*O Fork R4 */N/* J */N/* 10-Jul-01 X-29 */N/* */N/* This is the beginning of the abbreviated SCDRP which must be included */N/* in each port-specific Resource Bundle, currently only used by FastPath */N/* code; the goal is to minimize the size of the SCDRP required to perform */N/* a FastPath request J */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN struct _irp *scdrp$l_irp; /* I/O Request Packet address */#pragma __nomember_alignmentN struct _kpb *scdrp$ps_kpb; /* Kernel Process Block address */N unsignedJ int scdrp$is_sts; /* Request status (not SCSI status) */\ char *scdrp$ps_cdb; /* Pointer to SCSI Command Descriptor Block (CDB) */P struct _spdt *scdrp$ps_spdt; /* SCSI Port Descriptor Table address */O void *scdrp$ps_pqfl; /* Port or device queue forward link */P void *scdrp$ps_pqbl; /* Port or device queue backward link */N unsigned int scdrp$l_bcnt; /* Requested transfer byte count */h int *scdrp$l_sJts_ptr; /* SCSI status byte address (low byte of referenced longword) */W char *scdrp$l_cmd_ptr; /* Address of the SCSI command buffer (CBUF) */N unsigned int scdrp$l_pad_bcnt; /* Number of pad bytes */U unsigned int scdrp$l_trans_cnt; /* Number of bytes of user data transfered */T unsigned int scdrp$is_queue_char; /* Queue characteristics for this command */N unsigned int scdrp$l_dma_timeout; /* DMA timeout in seconds J */O unsigned int scdrp$l_cmd_buf_len; /* Number of valid bytes in SCSI CDB */g void *scdrp$ps_sense_buffer; /* Pointer to a buffer containing CHECK CONDITION sense data */Y int (*scdrp$ps_complete_io)(); /* FastPath request completion routine address */N unsigned int scdrp$is_request_status; /* Request completion status */` unsigned int scdrp$is_sense_buffer_len; /* Number of valid bytes in the sense data buffer */N/* These unions simply provide typed or unJtyped access to the same fields */N/* so the structures they point to can be referenced simply by code written */N/* in different languages - for instance, in C it allows us to avoid having */N/* to cast the pointer to keep the compiler happy (quiet) */ __union {Q struct _scsi_rbun *scdrp$ps_scsi_rbun; /* Pointer to generic SCSI RBUN */b struct _fcp_rbun *scdrp$ps_fcp_rbun; /* Pointer to SCSI-over-FibreChannel Protocol RBUN */O struct _pkq_rbun *sc Jdrp$ps_pkq_rbun; /* Pointer to PKQ-specific RBUN */N struct _rbun *scdrp$ps_rbun; /* X-39 Pointer to generic RBUN */ } scdrp$r_rbun_overlay; __union {N struct _cdt *scdrp$l_cdt; /* Leave in place for older drivers */V struct _scdt *scdrp$ps_scdt; /* SCSI Connection Descriptor Table address */! } scdrp$r_cdt_scdt_union;N/* Constants valid for use in the QUEUE_CHAR field */ __union {( unsigned int sJcdrp$l_scsi_flags; __struct {N/* Byte 0 bits */a unsigned scdrp$v_flag_s0buf : 1; /* Buffer allocated by class driver from S0 space */^ unsigned scdrp$v_flag_buffer_mapped : 1; /* Buffer (S0 or user) has been mapped */T unsigned scdrp$v_flag_disk_spun_up : 1; /* Start unit has been issued */N unsigned scdrp$v_flag_lock : 1; /* Fork block in use flag */S unsigned sJcdrp$v_flag_queued_io : 1; /* Optimize code for queued I/O */N unsigned scdrp$v_flag_aca_io : 1; /* ACA command */x unsigned scdrp$v_flag_clear_aca_msg : 1; /* Send clear ACA message and terminate ACA processing when done */k unsigned scdrp$v_flag_asense_valid : 1; /* Set to indicate valid data is in the sense buffer */N/* Byte 1 bits */j unsigned scdrp$v_flag_on_port_queue : J1; /* Set while the SCDRP is queued to the PORT_QUEUE */n unsigned scdrp$v_flag_on_dev_queue : 1; /* Set while the SCDRP is queued to the IN_DEVICE_QUEUE */r unsigned scdrp$v_flag_abort_this_io : 1; /* Set to indicate that this I/O is actively being aborted */h unsigned scdrp$v_flag_queue_full_init : 1; /* Queue full processing should be initialized */X unsigned scdrp$v_flag_queue_full_seen : 1; /* Queue full message was seen */U unsigned scdJrp$v_flag_wait_for_io : 1; /* Must wait for I/O completion */t unsigned scdrp$v_flag_internal_request : 1; /* Internal (port generated) request, skip ACA processing */r unsigned scdrp$v_flag_send_message_only : 1; /* Only send the message byte, there is no CDB to send */N/* Byte 2 bits */Z unsigned scdrp$v_flag_send_device_reset : 1; /* Send a device reset message */R unsigned scdrp$v_flag_moJde_sense : 2; /* MODE_SENSE (private flags) */X unsigned scdrp$v_flag_cl_private_buff : 1; /* Class Driver Private Buffer */Z unsigned scdrp$v_flag_tenbyte : 1; /* 10-byte mode sense commands supported */c unsigned scdrp$v_flag_bus_reset : 1; /* SCDRP was on device queue during a bus reset */s unsigned scdrp$v_flag_on_sys_queue : 1; /* Set while the SCDRP is on a system queue (fork,timer,...) */l unsigned scdrp$v_flag_on_fp_queue : 1; /* SeJt while the SCDRP is on the FastPath active queue */N/* Byte 3 bits */a unsigned scdrp$v_flag_rbun_wanted : 1; /* Set when an RBUN is needed for FastPath */T unsigned scdrp$v_flag_ext_lun : 1; /*F Use LUN from SCDRP, not SCDT */T unsigned scdrp$v_flag_medium_notpresent : 1; /* Medium is not present */o unsigned scdrp$v_flag_on_credit_queue : 1; /* X-36a Request is on SCDT & STDT credit waiJt queues */g unsigned scdrp$v_flag_time_stamp_rscc : 1; /* FibreChannel is using RSCC as a time stamp */` unsigned scdrp$v_flag_ready : 1; /* X-38a SCDRP has been prep'd for issue by port */b unsigned scdrp$v_flag_fp_scdrp : 1; /* X-43a This is a FastPath (abbreviated) SCDRP */] unsigned scdrp$v_flag_class_iobd : 1; /* X-43c Class driver owns SCDRP$PQ_IOBD */ } scdrp$r_fill_1_; } scdrp$r_fill_0_;n unsigned int scdrp$is_sequen Jce; /*O I/O sequence ID assigned by the port driver for error recovery. */ char scdrp$b_fill_16_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifT __int64 scdrp$q_time_stamp; /*O Time stamp for queue full processing. */ __union {#pragma __nomember_alignmentb unsigned int scdrp$is_queue_tag; /*O Tag value allocated by port J driver. Not used by - */N unsigned __int64 scdrp$q_queue_tag; /*O - intelligent ports */$ } scdrp$r_queue_tag_overlay;N/*O Overlay added for high SCSI ID's (wide devices) */N/* Make sure size is an integral number of quadwords */ N/* 10-Jul-01 X-29 */N/* */X/* A comment associated with the folJlowing field says that it must appear right after */Y/* the SCDRP fork block for use by MKDRIVER, but I don't see any evidence that this is */Y/* other than a stale comment; it also referenced use of REQCHAN, but I don't see that */Y/* in any of the drivers either. If any problems show up from breaking this field away */X/* from the fork block it will be restored to it's location immediately following the */N/* fork block */N/* J */N struct _ucb *scdrp$l_port_ucb; /*I Saved UCB address for REQCHAN */N/* Fields that came from IRP portion of the old SCDRP. */S struct _ucb *scdrp$l_ucb; /*I Address of device (class driver) UCB */N unsigned int scdrp$l_func; /*O I/O function code and modifiers */N unsigned int scdrp$l_boff; /*O Byte offset in first page */N int scdrp$l_svapte_fil Jl; /* NOSVAPTE_V9.0 Dave Fairbanks */ __union {' unsigned __int64 scdrp$q_media; __struct {N void *scdrp$l_media; /*O Media address */ } scdrp$r_fill_3_; } scdrp$r_fill_2_;N unsigned int scdrp$l_abcnt; /*O Accumulated bytes transfered */T int (*scdrp$l_savd_rtn)(); /*O Saved return address from level 1 JSB */O void *scdrp$l_msg_buf; /*O Address of allocated M JSCP buffer */N unsigned int scdrp$l_rspid; /*O Allocated Request ID */N short int *scdrp$l_rwcptr; /*O RWAITCNT pointer */I/* SCDRP extensions */ __union {I/* SCSI port/class driver extension */ __struct {P struct _scdrp *scdrp$ps_prev_scdrp; /*I Address of previous SCDRP */V void *scdrp$l_sva_user; /*O S0 address of Jdouble mapped user buffer */N void *scdrp$l_cmd_buf; /*O Address of SCSI command buffer */ __union {Z unsigned int scdrp$is_dipl_scsi_flags; /*S SCSI flags modified at DIPL. */ __struct {p unsigned scdrp$v_dsf_nowait : 1; /*S No wait is necessary in PK$WAIT_FOR_IO_COMPLETION. */w unsigned scdrp$v_dsf_release_spdt_lock : 1; /*S Device lock must be released in stall routine. */r J unsigned scdrp$v_dsf_device_was_reset : 1; /*S Device was reset while request was active. */d unsigned scdrp$v_dsf_request_aborted : 1; /*S Request aborted while active. */h unsigned scdrp$v_dsf_request_flushed : 1; /*S Request was flushed while active. */t unsigned scdrp$v_dsf_stall_wfikpch_dipl : 1; /*S Request stalled, use KP_STALL_WFIKPCH_DIPL */2 unsigned scdrp$v_fill_17_ : 2;& } scdrKp$r_fill_5_;" } scdrp$r_fill_4_;Y void *scdrp$l_datacheck; /*O Address of buffer for datacheck operations */N unsigned int scdrp$l_cl_retry; /*O Retry count */d unsigned int scdrp$l_discon_timeout; /*O Time in seconds for a disconnect to timeout. */R unsigned int scdrp$l_addnl_info; /*O Additional extended sense info */N unsigned char scdrp$b_sense_key; /*O Saved extended sense key */+ char sKcdrp$t_scdrp_align_0 [3];I/* SCSI PORT driver extension */V void *scdrp$l_sva_dma; /*O S0 address of chunk of 128KB DMA buffer */N int scdrp$is_cmd_slot; /*O Command slot information */N int scdrp$l_sva_spte_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */N void *scdrp$ps_port_dma_va; /*O VA of buffer for PORT */N int scdrp$l_port_svapte_fill; /* NOSVAPTE_V9.0 Dave Fairbanks K */N unsigned int scdrp$l_port_boff; /*O BOFF for *PORT* usage */U void *scdrp$ps_mode_args; /*O Pointer to SCSI MODE_SENSE.C arguments */] void *scdrp$l_scsimsgo_ptr; /*O SCSI OUTPUT MSG PTR, required for the SII PORT */\ void *scdrp$l_scsimsgi_ptr; /*O SCSI INPUT MSG PTR, required for the SII PORT */Q char scdrp$b_scsimsgo_buf [8]; /*O SCSI OUTPUT MSG buffer of port. */P char scdrp$b_scsimsgi_buf [8]; /*O SCSI INPUT KMSG buffer of port. */ __union {i unsigned int scdrp$l_msgo_pending; /*O Bit set if corresponding message is to be sent. */ __struct {N unsigned scdrp$v_msgo_identify : 1; /*O */N unsigned scdrp$v_msgo_queue_tag : 1; /*O */N unsigned scdrp$v_msgo_sync_out : 1; /*O */N unsigned scdrp$v_msgo_bus_device_reset : 1; /*O */NK unsigned scdrp$v_msgo_msg_parity_error : 1; /*O */N unsigned scdrp$v_msgo_id_error : 1; /*O */N unsigned scdrp$v_msgo_abort : 1; /*O */N unsigned scdrp$v_msgo_nop : 1; /*O */N unsigned scdrp$v_msgo_message_reject : 1; /*O */N unsigned scdrp$v_msgo_clear_aca : 1; /*O */g unsign Ked scdrp$v_msgo_last_bit : 1; /*O This must be last bit in this structure. */2 unsigned scdrp$v_fill_18_ : 5;& } scdrp$r_fill_7_;" } scdrp$r_fill_6_; __union {g unsigned int scdrp$l_msgi_pending; /*O Bit set if corresponding message is expected. */ __struct {N unsigned scdrp$v_msgi_sync_in : 1; /*O */2 unsigned scdrp$v_fill_19_ : 7;& K } scdrp$r_fill_9_;" } scdrp$r_fill_8_;N unsigned char scdrp$b_last_msgo; /*O Last message sent */+ char scdrp$t_scdrp_align_1 [3];N void *scdrp$l_data_ptr; /*O Current data pointer address. */m unsigned int scdrp$l_save_data_cnt; /*O Running 2's complement count of bytes to be transfered */N unsigned int scdrp$l_save_data_ptr; /*O Running data pointer. */N unsigned int scdrp$l_sdp_dKata_cnt; /*O Storage for SDP */N void *scdrp$l_sdp_data_ptr; /*O Storage for SDP */R unsigned int scdrp$l_duetime; /*O Timeout time for disconnected IO. */T unsigned int scdrp$is_cmd_bcnt; /*O temporary storage for cmd bytecnt */[ unsigned int scdrp$is_busy_retry_cnt; /*O Number retries left, for bus busy. */i unsigned int scdrp$is_arb_retry_cnt; /*O Number of retries left, for arbitration failures. */g Kunsigned int scdrp$is_sel_retry_cnt; /*O Number of retries left, for selection failures. */f unsigned int scdrp$is_cmd_retry_cnt; /*O Number of times the port will retry a command. */o unsigned int scdrp$is_sel_tqe_retry_cnt; /*O Number of TQE retries left, for selection failures. */S unsigned int scdrp$is_dma_long; /*O DMA buffer for 1 byte transfers. */ __union {N unsigned int scdrp$is_events_seen; /*O Mask of events seen. */  K __struct {U unsigned scdrp$v_event_parerr : 1; /*O Parity error occured. */Y unsigned scdrp$v_event_bsyerr : 1; /*O Lost busy during command. */[ unsigned scdrp$v_event_misphs : 1; /*O Missing bus phase detected. */_ unsigned scdrp$v_event_badphs : 1; /*O A bad phase transition occured. */h unsigned scdrp$v_event_rst : 1; /*O The bus has been reset during this command. */j  K unsigned scdrp$v_event_ctlerr : 1; /*O A SCSI controller error has been detected. */b unsigned scdrp$v_event_buserr : 1; /*O A SCSI BUS ERROR HAS BEEN DETECTED */X unsigned scdrp$v_event_abort : 1; /*O This io has been aborted. */` unsigned scdrp$v_event_msgerr : 1; /*O An error was detected during ??? */2 unsigned scdrp$v_fill_20_ : 7;' } scdrp$r_fill_11_;# }  Kscdrp$r_fill_10_; __union {P unsigned int scdrp$is_cnx_sts; /*O Per I/O connection status. */ __struct {] unsigned scdrp$v_cnx_abort_pnd : 1; /*O Abort pending on connection. */` unsigned scdrp$v_cnx_abort_cmpl : 1; /*O Abort completed on connection. */Y unsigned scdrp$v_cnx_abort_inprog : 1; /*O Abort is in progress. */x unsigned scdrp$v_cnx_abort_resel : 1; /*O  KPort has been reselected while abort was in progress. */_ unsigned scdrp$v_cnx_pnd_resel : 1; /*O Reselection interrupt pending. */W unsigned scdrp$v_cnx_dscn : 1; /*O Connection is disconnected. */T unsigned scdrp$v_cnx_tmodscn : 1; /*O Connection timed out. */2 unsigned scdrp$v_fill_21_ : 1;' } scdrp$r_fill_13_;# } scdrp$r_fill_12_;c void *scdrp$ps_class_kpb; /* KO Field used by the queue manager to save KBP address. */N/* Bus phases for phase processing. */ __union {O unsigned int scdrp$is_bus_phase; /*O Current SCSI bus phase. */ __struct {N unsigned scdrp$v_phase_dataout : 1; /*O DATAIN Phase. */N unsigned scdrp$v_phase_datain : 1; /*O DATAIN Phase. */N unsigned scdrp$v_phase_cmd : 1; /*O Command PhasKe. */N unsigned scdrp$v_phase_sts : 1; /*O Status Phase. */N unsigned scdrp$v_phase_inv1 : 1; /*O Invalid Phase 1. */N unsigned scdrp$v_phase_inv2 : 1; /*O Invalid Phase 1. */Q unsigned scdrp$v_phase_msgout : 1; /*O MESSAGEOUT Phase. */O unsigned scdrp$v_phase_msgin : 1; /*O MESSAGEIN Phase. */O unsigned scdrp$v_phase_arb : 1; /*O Arbitration Phase. */N K unsigned scdrp$v_phase_sel : 1; /*O Selection Phase. */Q unsigned scdrp$v_phase_resel : 1; /*O Reselection Phase. */P unsigned scdrp$v_phase_discon : 1; /*O Disconnect seen. */\ unsigned scdrp$v_phase_cmd_cmpl : 1; /*O Command complete received. */b unsigned scdrp$v_phase_tmodiscon : 1; /*O Disconnect operation timed out. */P unsigned scdrp$v_phase_free : 1; /*O The bus went fr Kee. */2 unsigned scdrp$v_fill_22_ : 1;' } scdrp$r_fill_15_;# } scdrp$r_fill_14_;S unsigned int scdrp$is_old_phases; /*O Used to track SCSI bus phases. */N/* Embeded CRCTX (Counted Resource ConTeXt block) */N/* Used in allocating/deallocating mapping resources */X char scdrp$t_crctx_quad_align_fill [4]; /*I Quad align the imbedded CRCTX */ __union {\ K char scdrp$t_crctx_filler [96]; /*O Correct CRCTX length must appear here */N __struct { /*O */N char scdrp$t_crctx_ffill1 [56]; /*O */\ int scdrp$is_item_cnt; /*O Number of mapping resource units allocated */\ int scdrp$is_item_num; /*O Base mapping resource unit index allocated */+ } scdrp$r_crctx_fields;% } scdrp$ Kr_crctx_base;) } scdrp$r_scsi_drv_extension;# } scdrp$r_scdrp_extensions;N/* Define a pointer for DKMK to use during cancels */ void *scdrp$ps_qio_p6;N/* Allocate some per-command space for the port driver */ char scdrp$b_fill_23_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifK+ unsigned __int64 scdrp$q_port_specific;N/* Reserve some space for future expansion. */#pragma __nomember_alignment` int scdrp$l_rsvd_long [11]; /* Adjust array length so following fields don't move */N/* ; count of que full scsi status for SCSI2COMMON */ int scdrp$l_qfull_sts_cnt;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadw Kord#else#pragma __nomember_alignment#endifl unsigned __int64 scdrp$q_credit_sequence; /*O X-38b Order in which credit was granted to this request */N/* Define SCSI FastPath defined constant */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *scdrp$pq_svapte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else& K unsigned __int64 scdrp$pq_svapte_sva;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *scdrp$pq_sva_spte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else( unsigned __int64 scdrp$pq_sva_spte_sva;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_siz Ke __long /* And set ptr size default to 64-bit pointers */N void *scdrp$pq_port_svapte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else+ unsigned __int64 scdrp$pq_port_svapte_sva;#endifN/* X-46 */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _iobd *scdrp$pq_iobd; /* Poi Knter to class driver IOBD */#else unsigned __int64 scdrp$pq_iobd;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */W struct _ext *scdrp$pq_extent; /* Pointer to 1s Kt buffer extent to reference */#else" unsigned __int64 scdrp$pq_extent;#endif#pragma __nomember_alignmentP int scdrp$l_extent_boff; /* Byte offset into 1st buffer extent */N/* Define the structure length. */] char scdrp$t_length_quad_align_fill [4]; /*I Quadword align the data structure length. */ } SCDRP; #if !defined(__VAXC)B#define scdrp$ps_scsi_rbun scdrp$r_rbun_overlay.scdrp$ps_scsi_rbun@#define scdrp$ps_fcp_rbuKn scdrp$r_rbun_overlay.scdrp$ps_fcp_rbun@#define scdrp$ps_pkq_rbun scdrp$r_rbun_overlay.scdrp$ps_pkq_rbun8#define scdrp$ps_rbun scdrp$r_rbun_overlay.scdrp$ps_rbun6#define scdrp$l_cdt scdrp$r_cdt_scdt_union.scdrp$l_cdt:#define scdrp$ps_scdt scdrp$r_cdt_scdt_union.scdrp$ps_scdt=#define scdrp$l_scsi_flags scdrp$r_fill_0_.scdrp$l_scsi_flagsM#define scdrp$v_flag_s0buf scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_s0buf]#define scdrp$v_flag_buffer_mapped scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_Kbuffer_mapped[#define scdrp$v_flag_disk_spun_up scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_disk_spun_upK#define scdrp$v_flag_lock scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_lockU#define scdrp$v_flag_queued_io scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_queued_ioO#define scdrp$v_flag_aca_io scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_aca_io]#define scdrp$v_flag_clear_aca_msg scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_clear_aca_msg[#define scdrp$v_flag_asense_valid scdrp$r_fill_0_.scKdrp$r_fill_1_.scdrp$v_flag_asense_valid]#define scdrp$v_flag_on_port_queue scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_on_port_queue[#define scdrp$v_flag_on_dev_queue scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_on_dev_queue]#define scdrp$v_flag_abort_this_io scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_abort_this_ioa#define scdrp$v_flag_queue_full_init scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_queue_full_inita#define scdrp$v_flag_queue_full_seen scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_fKlag_queue_full_seenY#define scdrp$v_flag_wait_for_io scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_wait_for_ioc#define scdrp$v_flag_internal_request scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_internal_requeste#define scdrp$v_flag_send_message_only scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_send_message_onlye#define scdrp$v_flag_send_device_reset scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_send_device_resetW#define scdrp$v_flag_mode_sense scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_mode_Ksensea#define scdrp$v_flag_cl_private_buff scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_cl_private_buffQ#define scdrp$v_flag_tenbyte scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_tenbyteU#define scdrp$v_flag_bus_reset scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_bus_reset[#define scdrp$v_flag_on_sys_queue scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_on_sys_queueY#define scdrp$v_flag_on_fp_queue scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_on_fp_queueY#define scdrp$v_flag_rbun_wanted scdrp$rK_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_rbun_wantedQ#define scdrp$v_flag_ext_lun scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_ext_lune#define scdrp$v_flag_medium_notpresent scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_medium_notpresenta#define scdrp$v_flag_on_credit_queue scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_on_credit_queuea#define scdrp$v_flag_time_stamp_rscc scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_time_stamp_rsccM#define scdrp$v_flag_ready scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$vK_flag_readyS#define scdrp$v_flag_fp_scdrp scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_fp_scdrpW#define scdrp$v_flag_class_iobd scdrp$r_fill_0_.scdrp$r_fill_1_.scdrp$v_flag_class_iobdG#define scdrp$is_queue_tag scdrp$r_queue_tag_overlay.scdrp$is_queue_tagE#define scdrp$q_queue_tag scdrp$r_queue_tag_overlay.scdrp$q_queue_tag3#define scdrp$q_media scdrp$r_fill_2_.scdrp$q_mediaC#define scdrp$l_media scdrp$r_fill_2_.scdrp$r_fill_3_.scdrp$l_mediac#define scdrp$ps_prev_scdrp scdrp$r_scdrp_exte Knsions.scdrp$r_scsi_drv_extension.scdrp$ps_prev_scdrp]#define scdrp$l_sva_user scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_sva_user[#define scdrp$l_cmd_buf scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_cmd_buf}#define scdrp$is_dipl_scsi_flags scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_4_.scdrp$is_dipl_scsi_flags#define scdrp$v_dsf_nowait scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_4_.scdrp$r_fill_5_.scdrp$v_dsf_nowait!K#define scdrp$v_dsf_release_spdt_lock scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_4_.scdrp$r_fill_5_.scdrp$v_d\sf_release_spdt_lock#define scdrp$v_dsf_device_was_reset scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_4_.scdrp$r_fill_5_.scdrp$v_ds\f_device_was_reset#define scdrp$v_dsf_request_aborted scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_4_.scdrp$r_fill_5_.scdrp$v_dsf\_request_aborted#define scdrp$v_dsf_request_flushed scdrp$r_"Kscdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_4_.scdrp$r_fill_5_.scdrp$v_dsf\_request_flushed#define scdrp$v_dsf_stall_wfikpch_dipl scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_4_.scdrp$r_fill_5_.scdrp$v_\dsf_stall_wfikpch_dipl_#define scdrp$l_datacheck scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_datacheck]#define scdrp$l_cl_retry scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_cl_retryi#define scdrp$l_discon_timeout scdrp$r_scdrp_e#Kxtensions.scdrp$r_scsi_drv_extension.scdrp$l_discon_timeouta#define scdrp$l_addnl_info scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_addnl_info_#define scdrp$b_sense_key scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$b_sense_key[#define scdrp$l_sva_dma scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_sva_dma_#define scdrp$is_cmd_slot scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$is_cmd_slote#define scdrp$ps_port_dma_va scdrp$r_scdrp_extensions.$Kscdrp$r_scsi_drv_extension.scdrp$ps_port_dma_va_#define scdrp$l_port_boff scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_port_boffa#define scdrp$ps_mode_args scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$ps_mode_argse#define scdrp$l_scsimsgo_ptr scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_scsimsgo_ptre#define scdrp$l_scsimsgi_ptr scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_scsimsgi_ptre#define scdrp$b_scsimsgo_buf scdrp$r_scdrp_extensi%Kons.scdrp$r_scsi_drv_extension.scdrp$b_scsimsgo_bufe#define scdrp$b_scsimsgi_buf scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$b_scsimsgi_bufu#define scdrp$l_msgo_pending scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_6_.scdrp$l_msgo_pending#define scdrp$v_msgo_identify scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_6_.scdrp$r_fill_7_.scdrp$v_msgo_iden\tify#define scdrp$v_msgo_queue_tag scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp &K$r_fill_6_.scdrp$r_fill_7_.scdrp$v_msgo_que\ue_tag#define scdrp$v_msgo_sync_out scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_6_.scdrp$r_fill_7_.scdrp$v_msgo_sync\_out#define scdrp$v_msgo_bus_device_reset scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_6_.scdrp$r_fill_7_.scdrp$v_m\sgo_bus_device_reset#define scdrp$v_msgo_msg_parity_error scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_6_.scdrp$r_fill_7_.scdrp$v_m\sgo_msg_parity_error'K#define scdrp$v_msgo_id_error scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_6_.scdrp$r_fill_7_.scdrp$v_msgo_id_e\rror#define scdrp$v_msgo_abort scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_6_.scdrp$r_fill_7_.scdrp$v_msgo_abort}#define scdrp$v_msgo_nop scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_6_.scdrp$r_fill_7_.scdrp$v_msgo_nop#define scdrp$v_msgo_message_reject scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_6_.sc(Kdrp$r_fill_7_.scdrp$v_msg\o_message_reject#define scdrp$v_msgo_clear_aca scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_6_.scdrp$r_fill_7_.scdrp$v_msgo_cle\ar_aca#define scdrp$v_msgo_last_bit scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_6_.scdrp$r_fill_7_.scdrp$v_msgo_last\_bitu#define scdrp$l_msgi_pending scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_8_.scdrp$l_msgi_pending#define scdrp$v_msgi_sync_in scdrp$r_scdrp_extensions.scdr)Kp$r_scsi_drv_extension.scdrp$r_fill_8_.scdrp$r_fill_9_.scdrp$v_msgi_sync_\in_#define scdrp$b_last_msgo scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$b_last_msgo]#define scdrp$l_data_ptr scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_data_ptrg#define scdrp$l_save_data_cnt scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_save_data_cntg#define scdrp$l_save_data_ptr scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_save_data_ptre#define scdrp$l_sdp_*Kdata_cnt scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_sdp_data_cnte#define scdrp$l_sdp_data_ptr scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_sdp_data_ptr[#define scdrp$l_duetime scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$l_duetime_#define scdrp$is_cmd_bcnt scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$is_cmd_bcntk#define scdrp$is_busy_retry_cnt scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$is_busy_retry_cnti#define scdrp$is+K_arb_retry_cnt scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$is_arb_retry_cnti#define scdrp$is_sel_retry_cnt scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$is_sel_retry_cnti#define scdrp$is_cmd_retry_cnt scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$is_cmd_retry_cntq#define scdrp$is_sel_tqe_retry_cnt scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$is_sel_tqe_retry_cnt_#define scdrp$is_dma_long scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdr,Kp$is_dma_longv#define scdrp$is_events_seen scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_10_.scdrp$is_events_seen#define scdrp$v_event_parerr scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_10_.scdrp$r_fill_11_.scdrp$v_event_pa\rerr#define scdrp$v_event_bsyerr scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_10_.scdrp$r_fill_11_.scdrp$v_event_bs\yerr#define scdrp$v_event_misphs scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_f-Kill_10_.scdrp$r_fill_11_.scdrp$v_event_mi\sphs#define scdrp$v_event_badphs scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_10_.scdrp$r_fill_11_.scdrp$v_event_ba\dphs#define scdrp$v_event_rst scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_10_.scdrp$r_fill_11_.scdrp$v_event_rst#define scdrp$v_event_ctlerr scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_10_.scdrp$r_fill_11_.scdrp$v_event_ct\lerr#define scdrp$v_event_buserr scdrp$r_scdrp_e.Kxtensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_10_.scdrp$r_fill_11_.scdrp$v_event_bu\serr#define scdrp$v_event_abort scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_10_.scdrp$r_fill_11_.scdrp$v_event_abo\rt#define scdrp$v_event_msgerr scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_10_.scdrp$r_fill_11_.scdrp$v_event_ms\gerrn#define scdrp$is_cnx_sts scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_12_.scdrp$is_cnx_sts#define scdrp$v_cnx_/Kabort_pnd scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_12_.scdrp$r_fill_13_.scdrp$v_cnx_abo\rt_pnd#define scdrp$v_cnx_abort_cmpl scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_12_.scdrp$r_fill_13_.scdrp$v_cnx_ab\ort_cmpl#define scdrp$v_cnx_abort_inprog scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_12_.scdrp$r_fill_13_.scdrp$v_cnx_\ abort_inprog#define scdrp$v_cnx_abort_resel scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_0Kfill_12_.scdrp$r_fill_13_.scdrp$v_cnx_a\ bort_resel#define scdrp$v_cnx_pnd_resel scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_12_.scdrp$r_fill_13_.scdrp$v_cnx_pnd\_resel#define scdrp$v_cnx_dscn scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_12_.scdrp$r_fill_13_.scdrp$v_cnx_dscn#define scdrp$v_cnx_tmodscn scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_12_.scdrp$r_fill_13_.scdrp$v_cnx_tmods\cna#define scdrp$ps_class_kpb scdrp$r_scdrp_e1Kxtensions.scdrp$r_scsi_drv_extension.scdrp$ps_class_kpbr#define scdrp$is_bus_phase scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$is_bus_phase#define scdrp$v_phase_dataout scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_d\ataout#define scdrp$v_phase_datain scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_da\tain#define scdrp$v_phase_cmd scdrp$r_scdrp_extensions2K.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_cmd#define scdrp$v_phase_sts scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_sts#define scdrp$v_phase_inv1 scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_inv1#define scdrp$v_phase_inv2 scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_inv2#define scdrp$v_phase_ms3Kgout scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_ms\gout#define scdrp$v_phase_msgin scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_msg\in#define scdrp$v_phase_arb scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_arb#define scdrp$v_phase_sel scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_4Kphase_sel#define scdrp$v_phase_resel scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_res\el#define scdrp$v_phase_discon scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_di\scon#define scdrp$v_phase_cmd_cmpl scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_\cmd_cmpl#define scdrp$v_phase_tmodiscon scdrp$r_scdrp_extensions.scdrp$r_scsi_dr5Kv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase\ _tmodiscon#define scdrp$v_phase_free scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_fill_14_.scdrp$r_fill_15_.scdrp$v_phase_freec#define scdrp$is_old_phases scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$is_old_phasesa#define scdrp$r_crctx_base scdrp$r_scdrp_extensions.scdrp$r_scsi_drv_extension.scdrp$r_crctx_baseS#define scdrp$is_item_cnt scdrp$r_crctx_base.scdrp$r_crctx_fields.scdrp$is_item_cntS#define sc6Kdrp$is_item_num scdrp$r_crctx_base.scdrp$r_crctx_fields.scdrp$is_item_num"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SCDRPDEF_LOADED */ ww [UM/***********************************7K****************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, L8KP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** 9K **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */G/* Source: 28-APR-2008 15:22:53 $1$DGA8345:[LIB_H.SRC]SCDTDEF.SDL;1 *//*********************************************************************************** :K*********************************************//*** MODULE $SCDTDEF ***/#ifndef __SCDTDEF_LOADED#define __SCDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set p;Ktr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ Ka structure. */N/* */N/* ***NOTE2:**** If an INCOMPATIBLE CHANGE is made to this structure bump */B/* the version number of this structure. */N/*- */  #include N/* */N/* Performance Matrix (PM) ?K */N/* */N/* Description */N/* */I/* We want to define a 2-dimensional array in which to count commands */Q/* which complete successfully having transferred certain amounts of data */R/* in certain amounts of time. Because the C compiler must know a matrix's */R/* X di@Kmension in order to reference the correct [X][Y] cell, this is most */Q/* easily done with a fixed-sized array; since at this point we don't see */Q/* a need for the time or LBC ranges to be variable, there's no reason we */Q/* can't establish these values now - so the reference will be like this: */N/* */I/* matrix [time-range-index] [lbc-range-index] */N/* AK */N/* Time Slice Ranges (columns) */N/* =========================== */N/* */R/* We're interested in the range of times from 0 to 8 seconds. Because the */R/* time increments are small but the time spread is large (due to the fine */R/* granulatity of our basic unit, whichBK is 1us) we're mapping a big number */P/* of potential time values into a small number of time range slots. The */N/* algorithm chosen to do this is one which we think the compiler can */N/* optimize fairly well, and will yield the following time slices: */N/* */N/* [X] Time >= [X] Time >= */N/* === ======= === ======= CK */N/* [000] 1.000000 us [012] 4.000000 ms */N/* [001] 2.000000 us [013] 8.000000 ms */N/* [002] 4.000000 us [014] 16.000000 ms */N/* [003] 8.000000 us [015] 32.000000 ms */N/* [004] 16.000000 us [016] 64.000000 ms */N/* [005] 32.000000 us [017] 128.000000 ms */N/* DK [006] 64.000000 us [018] 256.000000 ms */N/* [007] 128.000000 us [019] 512.000000 ms */N/* [008] 256.000000 us [020] 1.000000 sec */N/* [009] 512.000000 us [021] 2.000000 sec */N/* [010] 1.000000 ms [022] 4.000000 sec */N/* [011] 2.000000 ms */N/* EK */O/* Each I/O which is counted in a given column took no *less* than that */O/* column's amount of time to complete; for instance, an I/O counted in */O/* column 3 took at least 8 us to complete: 8us <= t < 16us. If we ever */N/* need to see sub-us times we'll have to change this algorithm. Note */O/* that because these are minimums we don't have to have an element for */O/* the highest value - it's implied that I/O counFKted in the last column */N/* all took between 4 s and our maximum (8 seconds) */N/* */N/* Logical Block Count Ranges (rows) */N/* ================================= */N/* */P/* We're interested in LBCs from 1 to 256. There's an assumption that no GK*/P/* request which completes successfully will have a zero transfer count, */Q/* so no special checking will be performed to ensure that we don't count */N/* such a completion. We'll ignore any request which completes with a */N/* transfer count of more than 256d blocks. We're making this maximum */N/* transfer size a constant based on but independent of a port's */O/* maximum I/O size. What we know about an I/O counted in any given row */N/* is thaHKt it transferred no more than the number of blocks shown. For */N/* instance, an I/O counted in row 5 transferred up to 32d blocks, */N/* inclusive: 16 < LBC <= 32. The difference in logic between this and */N/* the time dimension is that we're mapping a fairly small number of */N/* blocks to a smaller number of cells for LBCs, so they can be done */N/* quickly with a table lookup. However, we could adjust the table so */N/* the same logic as the time dimenIKsion holds for LBCs */N/* */C/* [Y] LBC <= [Y] LBC <= */C/* === ====== === ====== */B/* [0] 001 [5] 032 */B/* [1] 002 [6] 064 */B/* [2] 004 [7] 128 */B/* [3] 008 [8] 256 JK */N/* [4] 016 */N/* */$#define PM$C_MAX_TIME_100NS 80000000N/* Maximum time logged, in unadjusted units */ #define PM$C_MAX_TIME_US 8000000N/* Maximum byte count logged, including pad bytes */#define PM$C_MAX_BCNT 131072N/* Maximum block count logged - note assumed block size KK */#define PM$C_MAX_LBC 256N/* Number of columns in the matrix */#define PM$C_TIME_X 23N/* Number of rows in the matrix */#define PM$C_LBC_Y 9N/* Define columns first ... */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomembLKer_alignment#endiftypedef struct _pm {N/* 1s in EXE$GQ_SYSTIME (100ns) ticks */N/* Maximum time logged, in unadjusted units */#pragma __nomember_alignment __struct {N/* ... then define rows */" unsigned int pm$l_lbc [9]; } pm$r_time [23]; char pm$b_fill_0_ [4]; } PM; #if !defined(__VAXC)#define pm$l_lbc pm$l_lbc"#endif /* #if ! MKdefined(__VAXC) */ N/* */T/* We use a pointer to the performance data so that we don't have multiple copies */\/* for a multipath disk. We just want to gather the performance data on a per lun basis. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadw NKord#else#pragma __nomember_alignment#endiftypedef struct _pm_data {a unsigned __int64 pm_data$q_read_time_acc; /*F Read command execution time accumulator (us) */c unsigned __int64 pm_data$q_write_time_acc; /*F Write command execution time accumulator (us) */#pragma __nomember_alignmentT unsigned int pm_data$l_reads; /*F Number of 6- or 10-byte Read commands */U unsigned int pm_data$l_writes; /*F Number of 6- or 10-byte Write commands */N unsigned int pm_OKdata$l_blocks_read; /*F Number of blocks read */N unsigned int pm_data$l_blocks_written; /*F Number of blocks written */h unsigned int pm_data$l_use_rscc; /*F Boolean true if RSCC timer is used, otherwise use systime */N PM pm_data$r_rd_pm; /*F Performance Matrix for reads */N PM pm_data$r_wr_pm; /*F Performance Matrix for writes */ char pm_data$b_fill_1_ [4]; } PM_DATA;N#define SCDT$C_VERSION 10 /* Compati PKble Version Number. */N#define SCDT$C_STATE_CLOSED 0 /*O Closed */N#define SCDT$C_STATE_OPEN 1 /*O Open */N#define SCDT$C_STATE_FAIL 2 /*O Connect Failed */#define SCDT$M_CAP_SCSI_2 0x1#define SCDT$M_CAP_SCSI_3 0x2#define SCDT$M_CAP_CMDQ 0x4#define SCDT$M_CAP_FREEZEQ 0x8#define SCDT$M_CAP_FLUSHQ 0x10(#define SCDT$M_CAP_CLASS_DRIVER_ACA 0x20N#define SCDT$S_FBLOCK 48 QK /* Old FBLOCK size name */N/* */"#define SCDT$M_CFLG_ENA_DISCON 0x1!#define SCDT$M_CFLG_DIS_RETRY 0x2##define SCDT$M_CFLG_TARGET_MODE 0x4!#define SCDT$M_ISTS_SDTR_SENT 0x1*#define SCDT$M_ISTS_DID_RESET_CALLBACK 0x2'#define SCDT$M_ISTS_PORT_GO_CREDITS 0x4##define SCDT$M_ISTS_PORT_SPEC_3 0x8$#define SCDT$M_ISTS_PORT_SPEC_4 0x10$#define SCDT$M_ISTS_PORT_SPEC_5 0x20 #define SCDT$M_QF_QUEUED_ACA 0x1)#d RKefine SCDT$M_QF_QUEUE_TIMER_RUNNING 0x2'#define SCDT$M_QF_NO_DEV_IO_CREDITS 0x4 #define SCDT$M_QF_NOT_QUEUED 0x8!#define SCDT$M_DQF_ACA_ACTIVE 0x1%#define SCDT$M_DQF_FLUSHING_QUEUE 0x2!#define SCDT$M_DQF_QUEUE_FULL 0x4&#define SCDT$M_DQF_QUEUE_FULL_INIT 0x8"#define SCDT$M_DQF_QUEUE_WAIT 0x10+#define SCDT$M_DQF_CLASS_DRVR_FREEZE_Q 0x20*#define SCDT$M_DQF_QUEUE_FLUSH_ACTIVE 0x40T#define SCDT$K_MAX_QUEUE_DEPTH 160 /* Absolute maximum queue depth allowed. */N#define SCDT$K_MAX_TAG 2SK56 /* Number of tags in bit map. */N#define SCDT$C_LENGTH 440 /* Length of SCDT */T#define SCDT$S_SCDTDEF 440 /* Old size name, synonym for SCDT$S_SCDT */  9#ifdef __cplusplus /* Define structure prototypes */ struct _spdt; struct _stdt;struct _inquiry_data; struct _ucb; struct _tqe; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C TK++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _scdt {#pragma __nomember_alignmentN unsigned short int scdt$w_scdt_type; /*O Type of SCDT */N unsigned short int scdt$w_state; /*O Connection State */ __union {N unsigned int scdt$is_capability; /* Connection Capability Mask */ __struct {U unsigned scdt$v_cap_scsi_2 : 1; /* Device reports SCSI-2 compliaUKnce. */U unsigned scdt$v_cap_scsi_3 : 1; /* Device reports SCSI-3 compliance. */R unsigned scdt$v_cap_cmdq : 1; /* Device supports command queuing. */f unsigned scdt$v_cap_freezeq : 1; /* Class driver requests freeze_queue_on_error mode. */d unsigned scdt$v_cap_flushq : 1; /* Class driver requests flush_queue_on_error mode. */n unsigned scdt$v_cap_class_driver_aca : 1; /* Class driver requests control of ACA operations. */) VK unsigned scdt$v_fill_16_ : 2; } scdt$r_fill_3_; } scdt$r_fill_2_;N unsigned short int scdt$w_size; /*I Structure size in bytes */N unsigned char scdt$b_type; /*I SCSI structure type */N unsigned char scdt$b_subtyp; /*I SCSI structure subtype for SCDT */N/* */B/* Define the fork block. */N/* WK */( char scdt$t_fkb_quad_align_fill [4]; __union {S FKB scdt$r_fkb; /*O Embedded quadword aligned fork block */c char scdt$b_flck; /*O For backward compatability with old Bliss/Macro code */ } scdt$r_fkb_overlay;B/* Define the structure references. */N/* */Z struct _spdt *scXKdt$ps_spdt; /*I Address of associated PORT descriptor table */N struct _stdt *scdt$ps_stdt; /*I Pointer to the STDT. */N void *scdt$ps_hash_flink; /*F Forward link on SCDT hash list. */c void *scdt$ps_scdrp_map; /*I List of SCDRPs indexed by tag value for reselection. */N/* */B/* Define the class driver callbacks. */N/* YK */P int (*scdt$l_sel_callback)(); /*I Address of Class driver callback. */Q unsigned int scdt$l_sel_context; /*I Context for Class driver callback. */r int (*scdt$ps_port_state_callback)(); /*I Class driver call back for PORT_STATE specified with SPI$CONNECT. */S unsigned int scdt$l_port_state_context; /*I Context for Port State callback. */N/* */B/*ZK ITL specific information. */N/* */N __union { /*I */N unsigned int scdt$l_scsi_lun; /*I Create quadword overlay for - */O unsigned __int64 scdt$q_scsi_lun; /*I wide devices or high SCSI ID's */" } scdt$r_scsi_lun_overlay;N/*I */X [K __int64 scdt$iq_in_nex; /*I ITL Nexus Descriptor Table Entry contents */Q unsigned int scdt$l_dma_timeout; /*I Time in seconds for a DMA timeout. */[ unsigned int scdt$l_discon_timeout; /*I Time in seconds for a disconnect to timeout. */R unsigned int scdt$is_busy_retry_cnt; /*I Number retries left, for bus busy. */` unsigned int scdt$is_arb_retry_cnt; /*I Number of retries left, for arbitration failures. */^ unsigned int scdt$is_sel_retry_cnt; /*I Number of retr \Kies left, for selection failures. */] unsigned int scdt$is_cmd_retry_cnt; /*I Number of times the port will retry a command. */N/* */B/* Set Connection Characteristic Information */N/* */ __union {N unsigned int scdt$is_con_flags; /*I Connection Specific Flags. */ __struct {N unsigned scdt$ ]Kv_cflg_ena_discon : 1; /*I Enable disconnect */X unsigned scdt$v_cflg_dis_retry : 1; /*I Disable retry on command fail. */Q unsigned scdt$v_cflg_target_mode : 1; /*I Target mode supported */) unsigned scdt$v_fill_17_ : 5; } scdt$r_fill_5_; } scdt$r_fill_4_; __union {U unsigned int scdt$is_impl_sts; /*F Implementation specific connection sts */ __struct {\ unsigned scdt$v_ists_sdtr_sent : 1; ^K/*O If SDTR_SENT bit is set, it means for */N/* this target/LUN, we already sent SDTR */N/* message to negotiate sync. xfer mode */g unsigned scdt$v_ists_did_reset_callback : 1; /*F Used by SCSI2COMMON to remember that we */N/* have already told the class driver that a */N/* reset is in progress. */i unsigned scdt$v_ists_p_Kort_go_credits : 1; /*F Port restarting class driver for I/O credits */g unsigned scdt$v_ists_port_spec_3 : 1; /* Define some bits for port-specific use and name */f unsigned scdt$v_ists_port_spec_4 : 1; /* them so as to make this intention clear. The # */a unsigned scdt$v_ists_port_spec_5 : 1; /* of each bit happens to be it's bit offset */) unsigned scdt$v_fill_18_ : 2; } scdt$r_fill_7_; } scdt$r_fill_6_;N/* `K */B/* Queuing specific data. */N/* */ __union {e unsigned int scdt$is_queue_flags; /*F Bitmap of flags used to manage the port queue state. */ __struct {Q unsigned scdt$v_qf_queued_aca : 1; /*F ACA I/O on head of queue. */] unsigned scdt$v_qf_queue_timer_running : 1; /*F Queue fu aKll timer is running. */s unsigned scdt$v_qf_no_dev_io_credits : 1; /*F The port's device I/O queue has no remaining credits */j unsigned scdt$v_qf_not_queued : 1; /*F At least 1 Not-Queued request is pending or active */) unsigned scdt$v_fill_19_ : 4; } scdt$r_fill_9_; } scdt$r_fill_8_; __union {j unsigned int scdt$is_dipl_queue_flags; /*S Bitmap of flags used to manage the port queue state. */ __struct {j bK unsigned scdt$v_dqf_aca_active : 1; /*S Queued command terminated with a check condition. */j unsigned scdt$v_dqf_flushing_queue : 1; /*F The device and port queues are being flushed. */T unsigned scdt$v_dqf_queue_full : 1; /*S The device's queue is full. */_ unsigned scdt$v_dqf_queue_full_init : 1; /*S Initialize queue full processing. */o unsigned scdt$v_dqf_queue_wait : 1; /*S Queue processing is waiting for device I/O completion. *cK/r unsigned scdt$v_dqf_class_drvr_freeze_q : 1; /*S Class driver requested that the queue be frozen. */] unsigned scdt$v_dqf_queue_flush_active : 1; /*S Queue flush active is active */) unsigned scdt$v_fill_20_ : 1; } scdt$r_fill_11_; } scdt$r_fill_10_;Q unsigned int scdt$is_sequence; /*O Sequence ID assigned to a new I/O. */g unsigned int scdt$is_next_sequence; /*O Next sequence ID expected to be sent by the port driver. *dK/N/* */U/* SCSI-2 Congestion Control information. Used for queue full message processing. */N/* */n unsigned int scdt$is_queued_io_count; /*F The number of SCSI commands queued following the command that */N/* received the queue full condition. */R unsigned int scdt$is_max_queue_depth; /*F Maximum queue de eKpth for the port. */V unsigned int scdt$is_current_queue_depth; /*F Current queue depth for the port. */N/* Fast growth if CURRENT_QUEUE_DEPTH < QUEUE_DEPTH_THRESHOLD */N/* Slow growth if CURRENT_QUEUE_DEPTH > QUEUE_DEPTH_THRESHOLD */N unsigned int scdt$is_queue_depth_threshold; /*F Queue depth threshold. */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#prafKgma __nomember_alignment#endifR __int64 scdt$q_cmd_complete_time; /*F Average time to complete a command. */#pragma __nomember_alignment^ __int64 scdt$q_cmd_complete_deviation; /*F Deviation in the time to complete a command. */s __int64 scdt$q_cmd_complete_delay; /*F The delay required to ensure that an average command could complete. */k unsigned int scdt$is_cmd_success_count; /*F The number of commands that have successfully completed. */N/* if CMD_SUCCESS_COUNT >= CMD_gKSUCCESS_THRESHOLD */I/* Increment CURRENT_QUEUE_DEPTH; */I/* CMD_SUCCESS_COUNT = 0; */w unsigned int scdt$is_cmd_success_threshold; /*F Threshold to be crossed before incrementing CURRENT_QUEUE_DEPTH. */N/* */B/* Queue Manager information. */N/* hK */ ] void *scdt$ps_port_qfl; /*F Forward link of queue of I/O sent to the port. */^ void *scdt$ps_port_qbl; /*F Backward link of queue of I/O sent to the port. */d void *scdt$ps_dev_qfl; /*F Forward link of queue of requests sent to the device. */e void *scdt$ps_dev_qbl; /*F Backward link of queue of requests sent to the device. */\ unsigned int scdt$is_total_io_count; /*F Total outstandingiK I/O count (port & device). */U unsigned int scdt$is_port_io_count; /*F Count of I/Os outstanding on the port. */W unsigned int scdt$is_dev_io_count; /*F Count of I/Os outstanding on the device. */d unsigned int scdt$is_hash_index; /*F Index of this SCDT's root SCDT in the STDT hash table */N/* */B/* Port connection performance and error counters. */N/* jK */N unsigned int scdt$l_arb_fail_cnt; /*S Count of arbitration failures. */N unsigned int scdt$l_sel_fail_cnt; /*S Count of selection failures. */N unsigned int scdt$l_parerr_cnt; /*S Count of parity errors. */N unsigned int scdt$l_misphs_cnt; /*S Count of missing phases errors. */N unsigned int scdt$l_badphs_cnt; /*S Count of bad phase errors. */T unsigned int scdt$l_retry_cnt; /*S Count of retries, this on cokKnnection. */N unsigned int scdt$l_ctlerr_cnt; /*S Count of controller errors */N unsigned int scdt$l_buserr_cnt; /*S Count of bus errors */N unsigned int scdt$l_cmdsent; /*S Number of commands sent */N unsigned int scdt$l_msgsent; /*S Number of messages sent */R unsigned int scdt$l_bytsent; /*S Number of bytes sent during dataout */N/* */B/* AllolKcation bit map for tag values, and associated values. */N/* */^ unsigned int scdt$is_wait_tag; /*F Tag value associated with a non-queued request. */Z unsigned int scdt$is_max_tag_used; /*F Maximum tag value used, performance metric. */N/* Maximum tag value allowed: ( 0 - 255 ) */N/* Maximum longwords for the tag allocation bit map. */h unsigned int smKcdt$is_tag_map [8]; /*F Bitmap of allocated tag values. Bit set => value in use. */N unsigned int scdt$is_last_tag_index; /*F Last tag value allocated */N struct _inquiry_data *scdt$ps_inquiry_data; /* Pointer to Inquiry data */N struct _ucb *scdt$ps_class_ucb; /* Pointer to class driver UCB */N/* */Y/* Save some space for future expansion. Reserved to Digital, ALPHA/VMS development. */N/* nK */d int scdt$l_rsvd_long [5]; /*F Port specific space that may be used for any purpose. */W char scdt$b_quad_fill [4]; /*F Quadword-align the FastPath fields /* FP */W void *scdt$ps_fp_dev_qfl; /*F FastPath device queue forward link /* FP */X void *scdt$ps_fp_dev_qbl; /*F FastPath device queue backward link /* FP */W __int64 scdt$iq_fp_dev_io_count; /*F Number of active oK FastPath requests /* FP */N/* */B/* Save some space for Port specific extensions. */N/* */ __union {d int scdt$l_port_specific [5]; /*F Port specific space that may be used for any purpose. */N __int64 scdt$q_identity; /*F Identity quadword */' } scdt$r_port_specific_overlay;N/* pK */Q/* These fields are first used in Ruby (V7.3-1). Since we do not have the */Q/* option of forcing 3rd-party class driver recompiles in a dash release, */Q/* these fields are being added to the tail of the structure. It would be */J/* a good idea to move them to before the port-specific overlays in the */I/* next dot release */N/* qK */W struct _scdt *scdt$ps_scdt_link; /*F Link to next SCDT connected to same STDT */W unsigned int scdt$l_suspensions; /*F Number of outstanding pauses/suspensions */\ struct _tqe *scdt$ps_busy_tqe; /*F Pointer to TQE used to implement a BUSY stall */N/*F X-27 */^ struct _pm_data *scdt$ps_pm_data; /*F Pointer to common performance data for each LUN */N/* An rKHBA will sometimes require the LUN it uses to be formatted */N/* differently than is expected in the SCSI_LUN field by the OpenVMS */N/* Exec. For instance, the ISP23xx requires the LUN to be shifted */N/* down (right) 8 bits, while the ISP24xx requires the full quadword */N/* LUN but in big-endian order (LSB at high byte). To avoid having */N/* to reformat the LUN for every single SCSI command which is issued */N/* some drivers may choose to do sK the formatting once into this field */N/* when the device is initially configured */N/* X-28 */ char scdt$b_fill_21_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 scdt$q_lun; tK /* LUN as quadword */ __struct {N int scdt$l_lun; /* LUN as longword */N short int scdt$w_lun; /* LUN as word */N char scdt$b_lun; /* LUN as byte */ } scdt$r_fill_13_; } scdt$r_fill_12_;N/* End union */N/* X-28 uK */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN __int64 scdt$q_credit_io_count; /* Credit I/O count as quadword */ __struct {P int scdt$is_credit_io_count; /* Number of I/Os waiting for credit */ } scdt$r_fill_15_; } scdt$r_fill_14_;N vK/* End union */N/* X-28 */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __struct { /* Credit wait queue */#pragma __nomember_alignmentN void *scdt$ps_credit_wqfl; /* Cre wKdit wait queue forward link */N void *scdt$ps_credit_wqbl; /* Credit wait queue backward link */ } scdt$r_credit_wq;N/* */B/* Define the length of this structure. */N/* */ } SCDT; #if !defined(__VAXC)<#define scdt$is_capability scdt$r_fill_2_.scdt$is_capabilityI#define scdt$v_cap_scsi_2 scdt$rxK_fill_2_.scdt$r_fill_3_.scdt$v_cap_scsi_2I#define scdt$v_cap_scsi_3 scdt$r_fill_2_.scdt$r_fill_3_.scdt$v_cap_scsi_3E#define scdt$v_cap_cmdq scdt$r_fill_2_.scdt$r_fill_3_.scdt$v_cap_cmdqK#define scdt$v_cap_freezeq scdt$r_fill_2_.scdt$r_fill_3_.scdt$v_cap_freezeqI#define scdt$v_cap_flushq scdt$r_fill_2_.scdt$r_fill_3_.scdt$v_cap_flushq]#define scdt$v_cap_class_driver_aca scdt$r_fill_2_.scdt$r_fill_3_.scdt$v_cap_class_driver_aca0#define scdt$r_fkb scdt$r_fkb_overlay.scdt$r_fkb2#define scdt$byK_flck scdt$r_fkb_overlay.scdt$b_flck?#define scdt$l_scsi_lun scdt$r_scsi_lun_overlay.scdt$l_scsi_lun?#define scdt$q_scsi_lun scdt$r_scsi_lun_overlay.scdt$q_scsi_lun:#define scdt$is_con_flags scdt$r_fill_4_.scdt$is_con_flagsS#define scdt$v_cflg_ena_discon scdt$r_fill_4_.scdt$r_fill_5_.scdt$v_cflg_ena_disconQ#define scdt$v_cflg_dis_retry scdt$r_fill_4_.scdt$r_fill_5_.scdt$v_cflg_dis_retryU#define scdt$v_cflg_target_mode scdt$r_fill_4_.scdt$r_fill_5_.scdt$v_cflg_target_mode8#define scdt$is_imzKpl_sts scdt$r_fill_6_.scdt$is_impl_stsQ#define scdt$v_ists_sdtr_sent scdt$r_fill_6_.scdt$r_fill_7_.scdt$v_ists_sdtr_sentc#define scdt$v_ists_did_reset_callback scdt$r_fill_6_.scdt$r_fill_7_.scdt$v_ists_did_reset_callback]#define scdt$v_ists_port_go_credits scdt$r_fill_6_.scdt$r_fill_7_.scdt$v_ists_port_go_creditsU#define scdt$v_ists_port_spec_3 scdt$r_fill_6_.scdt$r_fill_7_.scdt$v_ists_port_spec_3U#define scdt$v_ists_port_spec_4 scdt$r_fill_6_.scdt$r_fill_7_.scdt$v_ists_port_spec_4U#define {Kscdt$v_ists_port_spec_5 scdt$r_fill_6_.scdt$r_fill_7_.scdt$v_ists_port_spec_5>#define scdt$is_queue_flags scdt$r_fill_8_.scdt$is_queue_flagsO#define scdt$v_qf_queued_aca scdt$r_fill_8_.scdt$r_fill_9_.scdt$v_qf_queued_acaa#define scdt$v_qf_queue_timer_running scdt$r_fill_8_.scdt$r_fill_9_.scdt$v_qf_queue_timer_running]#define scdt$v_qf_no_dev_io_credits scdt$r_fill_8_.scdt$r_fill_9_.scdt$v_qf_no_dev_io_creditsO#define scdt$v_qf_not_queued scdt$r_fill_8_.scdt$r_fill_9_.scdt$v_qf_not_queuedI#d|Kefine scdt$is_dipl_queue_flags scdt$r_fill_10_.scdt$is_dipl_queue_flagsS#define scdt$v_dqf_aca_active scdt$r_fill_10_.scdt$r_fill_11_.scdt$v_dqf_aca_active[#define scdt$v_dqf_flushing_queue scdt$r_fill_10_.scdt$r_fill_11_.scdt$v_dqf_flushing_queueS#define scdt$v_dqf_queue_full scdt$r_fill_10_.scdt$r_fill_11_.scdt$v_dqf_queue_full]#define scdt$v_dqf_queue_full_init scdt$r_fill_10_.scdt$r_fill_11_.scdt$v_dqf_queue_full_initS#define scdt$v_dqf_queue_wait scdt$r_fill_10_.scdt$r_fill_11_.scdt$v_d}Kqf_queue_waite#define scdt$v_dqf_class_drvr_freeze_q scdt$r_fill_10_.scdt$r_fill_11_.scdt$v_dqf_class_drvr_freeze_qc#define scdt$v_dqf_queue_flush_active scdt$r_fill_10_.scdt$r_fill_11_.scdt$v_dqf_queue_flush_activeN#define scdt$l_port_specific scdt$r_port_specific_overlay.scdt$l_port_specificD#define scdt$q_identity scdt$r_port_specific_overlay.scdt$q_identity-#define scdt$q_lun scdt$r_fill_12_.scdt$q_lun=#define scdt$l_lun scdt$r_fill_12_.scdt$r_fill_13_.scdt$l_lun=#define scdt$w_lun scd ~Kt$r_fill_12_.scdt$r_fill_13_.scdt$w_lun=#define scdt$b_lun scdt$r_fill_12_.scdt$r_fill_13_.scdt$b_lunE#define scdt$q_credit_io_count scdt$r_fill_14_.scdt$q_credit_io_countW#define scdt$is_credit_io_count scdt$r_fill_14_.scdt$r_fill_15_.scdt$is_credit_io_count@#define scdt$ps_credit_wqfl scdt$r_credit_wq.scdt$ps_credit_wqfl@#define scdt$ps_credit_wqbl scdt$r_credit_wq.scdt$ps_credit_wqbl"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POIKNTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SCDTDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential prSJ SASDEVDEFuJSBDEFJLSBNBDEFJNSBODEFJ. SCAMGTDEFJPSCBDEFJSCDRPDEF5KSCDTDEF~KSCHDEF SCH_ROUTINESK,SCQDEFK SCSCMGDEFK,SCSDEFKDSCSIDEFL SCSNETDEF. SCS_ROUTINESKoprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/MK/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************* K*******************************************************************************************************/=/* Created: 7-Oct-2024 15:22:22 by OpenVMS SDL V3.7 */F/* Source: 04-FEB-2019 16:17:34 $1$DGA8345:[LIB_H.SRC]SCHDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SCHDEF ***/#ifndef __SCHDEF_LOADED#define __SCHDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANKSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_paraKms#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define SCH$C_SWPPIX 1 /* PIX for swapper process */N#define SCH$V_SIP 0 /* SWAP IN PROGRESS FLAG */N#define SCH$M_SIP 1 /* SWAKP IN PROGRESS MASK */N#define SCH$V_TCD 1 /* MPL threshold checking disabled */R#define SCH$M_TCD 2 /* MPL threshold checking disabled mask */N#define SCH$V_MPW 2 /* Modify page writer active */N#define SCH$M_MPW 4 /* Modify page writer active mask */P#define SCH$V_REORD 0 /* OSWPSCHED queue reordering occured */N/* Verified for x86 port - Clair Grant K */N#define SCH$C_ASN_MIN 0 /* Minimum RID for process space */"#define SCH$M_DEFERRED_AST_OFF 0x1#define SCH$M_QUEUE_OPT_OFF 0x2%#define SCH$M_SPL_HTHREAD_OPT_OFF 0x4!#define SCH$M_PC_SAMPLING_OFF 0x8(#define SCH$M_PROCESS_IDLE_CW_LOCKS 0x10##define SCH$M_MTX_HERD_OPT_OFF 0x20%#define SCH$M_SPL_PC_SAMPLING_ON 0x40"#define SCH$M_SPL_PC_CPUID_ON 0x80#define SCH$M_FRKSPL 0x100 typedef struct _sched_flags { __union {N unsigned int sch$l_schKed_flags; /* SCHED Control Flags */ __struct {a unsigned sch$v_deferred_ast_off : 1; /* Turn off AST Deferal optimizaton (V84R on) */^ unsigned sch$v_queue_opt_off : 1; /* Turn off AST queue optimization (V84R on) */r unsigned sch$v_spl_hthread_opt_off : 1; /* Turn off SPL Hyper Thread Optimization (V84R POULSON on) */h unsigned sch$v_pc_sampling_off : 1; /* Turn off PC Sampling (V84R POULSON on) */u unsiKgned sch$v_process_idle_cw_locks : 1; /* Enable XFC timeout on CW mode locks (V7.3-2 - POULSON on) */q unsigned sch$v_mtx_herd_opt_off : 1; /* Turn off Mutex Herd handling Algorithm (V83R - POULSON on) */S unsigned sch$v_spl_pc_sampling_on : 1; /* Used by SPINLOCKS (V84 on) */y unsigned sch$v_spl_pc_cpuid_on : 1; /* Used by SPINLOCKS (V84 on, was PERSONA_SECAUDIT in V83R - V83-1H1R) */_ unsigned sch$v_frkspl : 1; /* Used by FORKCNTRL (V83R, V84R, th Ken TEWKSBURY on) */' unsigned sch$v_fill_0_ : 7;$ } sch$r_sched_flag_bits;$ } sch$r_sched_flags_overlay; } SCHED_FLAGS; #if !defined(__VAXC)E#define sch$l_sched_flags sch$r_sched_flags_overlay.sch$l_sched_flagse#define sch$v_deferred_ast_off sch$r_sched_flags_overlay.sch$r_sched_flag_bits.sch$v_deferred_ast_off_#define sch$v_queue_opt_off sch$r_sched_flags_overlay.sch$r_sched_flag_bits.sch$v_queue_opt_offk#define sch$v_spl_hthread_opt_off sch$r_sched_Kflags_overlay.sch$r_sched_flag_bits.sch$v_spl_hthread_opt_offc#define sch$v_pc_sampling_off sch$r_sched_flags_overlay.sch$r_sched_flag_bits.sch$v_pc_sampling_offo#define sch$v_process_idle_cw_locks sch$r_sched_flags_overlay.sch$r_sched_flag_bits.sch$v_process_idle_cw_lockse#define sch$v_mtx_herd_opt_off sch$r_sched_flags_overlay.sch$r_sched_flag_bits.sch$v_mtx_herd_opt_offi#define sch$v_spl_pc_sampling_on sch$r_sched_flags_overlay.sch$r_sched_flag_bits.sch$v_spl_pc_sampling_onc#define sch$v_Kspl_pc_cpuid_on sch$r_sched_flags_overlay.sch$r_sched_flag_bits.sch$v_spl_pc_cpuid_onQ#define sch$v_frkspl sch$r_sched_flags_overlay.sch$r_sched_flag_bits.sch$v_frkspl"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard  K#endif /* __SCHDEF_LOADED */ wwpֿ[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. K **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. K**/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */F/* Source: 24-DEC-1997 09:36:32 $1$DGA8345:[LIB_H.SRC]SCQDEF.SD KL;1 *//********************************************************************************************************************************//*** MODULE $SCQDEF ***/#ifndef __SCQDEF_LOADED#define __SCQDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previKously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union un Kion#else#define __union variant_union#endif#endif N/*+ */I/* $SCQDEF - SCSI Connect reQuest desciptor block */N/* */N/* The SCQ is passed by a SCSI class driver to a SCSI port driver as the */N/* sole argument in to the CONNECT service call. The SCQ contains all */N/* CONNECT service parameters, both input an Kd output. */4/* +-------------------+ */:/* Buffer | 10 or 12 | argument count */4/* +-------------------+ */J/* 1 +04 | disconnects | 1 = supported, 0 = unsupported */4/* +-------------------+ */=/* 2 +08 | synchronous | Port controlled. */4/* +-------------------+ */=/* 3 +0C | Transfer_period | m * 4 nanosec Konds */4/* +-------------------+ */>/* 4 +10 | Reqack_offset | */4/* +-------------------+ */</* 5 +14 | Busy_retry_count | 0 = no retries */4/* +-------------------+ */</* 6 +18 | Arb_retry_count | 0 = no retries */4/* +-------------------+ */</* 7 +1C | Sel_retry_count | 0 = no retries */4/* +-------------------+ K */</* 8 +20 | Cmd_retry_count | 0 = no retries */4/* +-------------------+ */@/* 9 +24 | Dma_timeout | 0 = Phase/Dma Timeout */4/* +-------------------+ */F/* 10 +28 | Disconnect timeout| 0 = Disconnected IO timeout */4/* +-------------------+ */9/* 11 +2C | Flags | SCSI Flags */4/* +-------------------+ */>/* K 12 +30 | Max Queue Depth | Maximum queue depth */4/* +-------------------+ */N/* */B/* The Flags field is defined as follows: */N/* */;/* Bit Description */;/* --- ----------- */</* 0 CMDQ - Device supports command K queuing if set */;/* 1 FLUSHQ - Flush queue on error */;/* 2 FREEZEQ - Freeze queue on error */;/* 3 SCSI-2 - Device is SCSI-2 conformant */B/* 31-4 Reserved MBZ */N/*- */ N#define SCQ$C_VERSION 1 /* Compatible Version Number. */N/* Inputs K */N#define SCQ$K_CLSPOT_SP1 1 /* SP1$ protocol */N#define SCQ$K_CLSPOT_SP2 2 /* SP2$ protocol */  9#ifdef __cplusplus /* Define structure prototypes */struct _scsipath; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _sc Kq {#pragma __nomember_alignmentN unsigned int scq$is_clspot_protocol; /* Class/port protocol */ __union {N unsigned int scq$is_version_nos; /* Data struc. version #s */ __struct {N unsigned char scq$ib_scdrp_vno; /* SCDRP version */N unsigned char scq$ib_spdt_vno; /* SPDT version */N unsigned char scq$ib_scdt_vno; /* SCDT version */N unsigned char scq$ib K_stdt_vno; /* STDT version */ } scq$r_fill_1_; } scq$r_fill_0_; __union {N struct _scsipath *scq$ps_scsipath; /* Pointer to path info */ __union {N unsigned int scq$is_scsi_ids; /* SCSI port/bus IDs */ __struct {N unsigned short int scq$iw_scsi_port_id; /* SCSI port ID */N unsigned short int scq$iw_scsi_bus_id; /* SCSI bus ID */ } sc Kq$r_fill_3_; } scq$r_fill_2_; } scq$r_scsi_id_overlay; __union {N unsigned int scq$is_scsi_lun; /* SCSI LUN (longword) */ __struct {) short int scq$w_lun_reserved;N unsigned short int scq$iw_scsi_lun; /* SCSI_LUN (word) */ } scq$r_fill_5_; } scq$r_fill_4_;N int (*scq$ps_sel_callback)(); /* Target mode callback rout. */N unsigned int scq$is_sel_context; /* TargeKt mode context data */N int (*scq$ps_aen_callback)(); /* AEN callback routine */N unsigned int scq$is_aen_context; /* AEN context data */N int (*scq$ps_port_state_callback)(); /* Port State Callback Routine */N unsigned int scq$is_port_state_context; /* Port State Callback Context */N/* Outputs */N void *scq$ps_spdt; /* Port SPDT address K*/N void *scq$ps_scdt; /* SCDT address */N void *scq$ps_stdt; /* STDT address */N unsigned int scq$is_max_bcnt; /* Maximum BCNT supported */N unsigned int scq$is_port_serv_flags; /* Port service flags */ } SCQ; #if !defined(__VAXC);#define scq$is_version_nos scq$r_fill_0_.scq$is_version_nosE#define scq$ib_scdrp_vno scq$r_fill_0_.scq$r_fill_1_.scq$ib_scdrp_vnoC#define scKq$ib_spdt_vno scq$r_fill_0_.scq$r_fill_1_.scq$ib_spdt_vnoC#define scq$ib_scdt_vno scq$r_fill_0_.scq$r_fill_1_.scq$ib_scdt_vnoC#define scq$ib_stdt_vno scq$r_fill_0_.scq$r_fill_1_.scq$ib_stdt_vno=#define scq$ps_scsipath scq$r_scsi_id_overlay.scq$ps_scsipathK#define scq$is_scsi_ids scq$r_scsi_id_overlay.scq$r_fill_2_.scq$is_scsi_idsa#define scq$iw_scsi_port_id scq$r_scsi_id_overlay.scq$r_fill_2_.scq$r_fill_3_.scq$iw_scsi_port_id_#define scq$iw_scsi_bus_id scq$r_scsi_id_overlay.scq$r_fill_2_.s Kcq$r_fill_3_.scq$iw_scsi_bus_id5#define scq$is_scsi_lun scq$r_fill_4_.scq$is_scsi_lunC#define scq$iw_scsi_lun scq$r_fill_4_.scq$r_fill_5_.scq$iw_scsi_lun"#endif /* #if !defined(__VAXC) */ N#define SCQ$K_LENGTH 60 /* Structure length */#define SCQ$S_SCQDEF 60 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defiKned required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SCQDEF_LOADED */ ww$[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicaKted OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyoneK without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 b Ky OpenVMS SDL V3.7 */I/* Source: 19-APR-1993 14:55:08 $1$DGA8345:[LIB_H.SRC]SCSCMGDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SCSCMGDEF ***/#ifndef __SCSCMGDEF_LOADED#define __SCSCMGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* KDefined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#definKe __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SCSCMG - SCS CONNECTION MANAGEMENT MESSAGE FORMAT */N/* */N/* THIS PORTION OF A CONNECT/ACCEPT MESSAGE IS SEEN BY A */N/* SYSTEM APPL KICATION. */N/*- */#define SCSCMG$S_SCSCMGDEF 48 typedef struct _scscmg {N char scscmg$t_recnam [16]; /*RECEIVE PROCESS NAME */N char scscmg$t_sndnam [16]; /*SENDER PROCESS NAME */N unsigned char scscmg$b_snddat [16]; /*SENDER CONNECT DATA */ } SCSCMG; $#pragma __member_alignment __restoreRK#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SCSCMGDEF_LOADED */ wwK[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This softwKare is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confKidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*** K*****************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */F/* Source: 24-MAY-1993 17:24:25 $1$DGA8345:[LIB_H.SRC]SCSDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SCSDEF ***/#ifndef __SCSDEF_LOADED#define __SCSDEF_LOADED 1 G#pragma __nostandard /*K This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#elseK#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SCS MESSAGE DEFINITIONS */N/* K */N/* THIS STRUCTURE DEFINES OFFSETS AND FIELDS WITHIN THE SCS PORTION OF */N/* A CLUSTER MESSAGE. OFFSETS ARE DEFINED RELATIVE TO THE START OF THE */N/* APPLICATION DATA OR SCS CONTROL MESSAGE DATA. THE FULL MESSAGE FORMAT */N/* CONSISTS OF A PORT DRIVER LAYER HEADER (SEE STRUCTURE PPD) FOLLOWED */N/* BY THE SCS HEADER LAYER FOLLOWED BY THE APPLICATION DATA OR SCS CONTROL */N/* MESSAGE DATA. K */N/*- */ N#define SCS$C_OVHD 14 /* SCS LAYER OVERHEAD */N#define SCS$C_CON_REQL 66 /* CONNECT_REQ LENGTH */Q#define SCS$C_CON_RSPL 22 /* (TYC 20-apr-89) CONNECT_RSP LENGTH */N#define SCS$C_ACCP_REQL 66 /* ACCEPT_REQ LENGTH */N#define SCS$C_ACCP_RSPL 18 /* ACCEPT_RSP LENGTH K */N#define SCS$C_REJ_REQL 18 /* REJECT_REQ LENGTH */N#define SCS$C_REJ_RSPL 14 /* REJECT_RSP LENGTH */N#define SCS$C_DISC_REQL 18 /* DISCONNECT_REQ LENGTH */N#define SCS$C_DISC_RSPL 14 /* DISCONNECT_RSP LENGTH */N#define SCS$C_CR_REQL 14 /* CREDIT_REQ LENGTH */N#define SCS$C_CR_RSPL 14 /* CREDIT_RSP LENGHT */N#define SCS$C_KCON_REQ 0 /* CONNECT_REQ */N#define SCS$C_CON_RSP 1 /* CONNECT_RSP */N#define SCS$C_ACCP_REQ 2 /* ACCEPT_REQ */N#define SCS$C_ACCP_RSP 3 /* ACCEPT_RSP */N#define SCS$C_REJ_REQ 4 /* REJECT_REQ */N#define SCS$C_REJ_RSP 5 /* REJECT_RSP */N#define SCS$C_DISC_REQ 6 K/* DISCONNECT_REQ */N#define SCS$C_DISC_RSP 7 /* DISCONNECT_RSP */N#define SCS$C_CR_REQ 8 /* CREDIT_REQ */N#define SCS$C_CR_RSP 9 /* CREDIT_RSP */N#define SCS$C_APPL_MSG 10 /* APPLICATION MESSAGE */N#define SCS$C_APPL_DG 11 /* APPLICATION DATAGRAM */N#define SCS$K_APPL_BASE 0 /*BASE OF APPLICTION MESSAKGE DATA */N#define SCS$C_APPL_BASE 0 /*BASE OF APPLICTION MESSAGE DATA */#define SCS$M_UAP 0x1N#define SCS$K_STNORMAL 1 /* NORMAL, SUCCESS */N#define SCS$C_STNORMAL 1 /* */N#define SCS$K_STNOMAT 10 /* NO MATCHING LISTENER */N#define SCS$C_STNOMAT 10 /* */N#define SCS$K_STNORS 18 /* NO RESOURCES K */N#define SCS$C_STNORS 18 /* */N#define SCS$K_STDISC 25 /* DISCONNECTED */N#define SCS$C_STDISC 25 /* */N#define SCS$K_STINSFCR 33 /* INSUFF CREDIT */N#define SCS$C_STINSFCR 33 /* */N#define SCS$K_STBALANCE 41 /* LOAD BALANCE */N#define SCS$C_KSTBALANCE 41 /* DISCONNECT */N#define SCS$K_USE_ALTERNATE_PORT 42 /* (TYC 13-Feb-89) Load Share */S#define SCS$C_USE_ALTERNATE_PORT 42 /* Status code for using alternate port */N#define SCS$K_CON_BASE 4 /*BASE OF CONNECT/ACCEPT INFO TO */N#define SCS$C_CON_BASE 4 /*BASE OF CONNECT/ACCEPT INFO TO */N/* GIVE TO SYSAP'S */N#define SCS$S_SCSDEF 84 K /* Old size name - synonym */ @typedef struct _scs { /* WARNING: aggregate has origin of -32 */8 /* WARNING: aggregate element "scs$b_ppd" ignored */; /* WARNING: aggregate element "scs$w_length" ignored *// /* WARNING: aggregate element "" ignored *// /* WARNING: aggregate element "" ignored *// /* WARNING: aggregate element "" ignored *// /* WARNING: aggregate element "" ignored */; /* WARNING: aggregate element "scs$$_fill_1" ignored */: /* W KARNING: aggregate element "scs$w_mtype" ignored *// /* WARNING: aggregate element "" ignored *// /* WARNING: aggregate element "" ignored */; /* WARNING: aggregate element "scs$w_credit" ignored */> /* WARNING: aggregate element "scs$l_dst_conid" ignored */> /* WARNING: aggregate element "scs$l_src_conid" ignored */N unsigned short int scs$w_min_cr; /*MINIMUM SEND CREDIT */N __union { /* (TYC 20-apr-89) overlaid field */N K unsigned short int scs$w_status; /*STATUS/REASON */N __struct { /* */N unsigned scs$v_uap : 1; /* USE ALTERNATE PORT is supported */' unsigned scs$v_fill_0_ : 7; } scs$r_status_bits; } scs$r_status_overlay;N/*DEFINE STATUS/REASON CODES: */N/*FORMAT OF CONNECT/ACCEPT_REQ MSGS: */N K __union { /* (TYC 20-apr-89) overlaid field */N char scs$t_dst_proc [16]; /* DESTINATION PROCESS NAME */ __struct {N unsigned char scs$b_subnode; /* MUST BE ZERO FOR NOW */N unsigned char scs$b_pgrp; /* ALTERNATE PORT'S PPD ADDR */N unsigned short int scs$w_rsv; /* RESERVED FIELD */! } scs$r_con_rsp_flds; } scs$r_dst_overlay;N char scs$t_src K_proc [16]; /* SOURCE PROCESS NAME */N unsigned char scs$b_con_dat [16]; /* CONNECT DATA */ } SCS; #if !defined(__VAXC)6#define scs$w_status scs$r_status_overlay.scs$w_statusB#define scs$v_uap scs$r_status_overlay.scs$r_status_bits.scs$v_uap7#define scs$t_dst_proc scs$r_dst_overlay.scs$t_dst_procH#define scs$b_subnode scs$r_dst_overlay.scs$r_con_rsp_flds.scs$b_subnodeB#define scs$b_pgrp scs$r_dst_overlay.scs$r_con_rsp_flds.scs$b_pgrp@#d Kefine scs$w_rsv scs$r_dst_overlay.scs$r_con_rsp_flds.scs$w_rsv"#endif /* #if !defined(__VAXC) */ N/* */N/* DEFINITION OF THE REQUEST/SEND DATA OFFSETS */N/* */N#define SCS$S_SCSDEF1 28 /* Old size name - synonym */ Atypedef struct _scs1 { /* WARNING: aggregate has origin of -16 */; /* WAR KNING: aggregate element "scs$l_lconid" ignored */: /* WARNING: aggregate element "scs$l_rspid" ignored */< /* WARNING: aggregate element "scs$l_xct_len" ignored */= /* WARNING: aggregate element "scs$l_snd_name" ignored */N unsigned int scs$l_snd_boff; /* AND OFFSET */N unsigned int scs$l_rec_name; /* RECEIVE BUFFER NAME */N unsigned int scs$l_rec_boff; /* AND OFFSET */ } SCS1; $#pragma __Kmember_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SCSDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE KCONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAKL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************************************************K****************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:23 by OpenVMS SDL V3.7 */G/* Source: 19-SEP-2019 08:08:31 $1$DGA8345:[LIB_H.SRC]SCSIDEF.SDL;1 *//********************************************************************************************************************************/$/*** MODULE $SCSIDEF IDENT X-37 ***/#ifndef __SCSIDEF_LOADED#define __SCSIDEF_LOKADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#dKefine __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Bit definitions for FIBRE_SCSI_RSV1 K */N/* */#define SCSI$M_DK_BOOT_LOG 0x1#define SCSI$M_VERBOSE 0x2"#define SCSI$M_DIS_PER_RES_UNK 0x4"#define SCSI$M_DIS_PER_RES_HSG 0x8##define SCSI$M_DIS_PER_RES_HSV 0x10##define SCSI$M_DIS_PER_RES_MSA 0x20$#define SCSI$M_DIS_PER_RES_VERS 0x40$#define SCSI$M_DIS_PER_RES_HPXP 0x80%#define SCSI$M_DIS_PER_RES_BIT8 0x100%#define SCSI$M_DIS_PER_RES_BIT9 0x200%#define SCSI$M_DIS_PER_RES_BITA 0x400%#define KSCSI$M_DIS_PER_RES_BITB 0x800&#define SCSI$M_DIS_PER_RES_BITC 0x1000&#define SCSI$M_DIS_PER_RES_BITD 0x2000&#define SCSI$M_DIS_PER_RES_BITE 0x4000&#define SCSI$M_DIS_PER_RES_BITF 0x8000X#define SCSI$V_RWH 16 /* Base bit offset of Read/Write History bits */#define SCSI$M_RWH_SCSI 0x10000#define SCSI$M_RWH_FC 0x20000##define SCSI$M_RWH_SW_ISCSI 0x40000##define SCSI$M_RWH_HW_ISCSI 0x80000#define SCSI$M_RWH_SAS 0x100000P#define SCSI$M_RWH_ALL 2031616 /* DefinKe all-transport constant mask */##define SCSI$M_FIX_OS_MODE 0x200000-#define SCSI$M_CRASH_ON_RESET_FAIL 0x40000000*#define SCSI$M_ENABLE_PKR_RESET 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif!typedef struct _fibre_scsi_rsv1 {#pragma __nomember_alignmentN unsigned scsi$v_dk_boot_log : 1; /* Enable DKLOG for boot device */N K unsigned scsi$v_verbose : 1; /* Driver is verbose on boot */] unsigned scsi$v_dis_per_res_unk : 1; /* Selective disables for Persistent Reservations */( unsigned scsi$v_dis_per_res_hsg : 1;( unsigned scsi$v_dis_per_res_hsv : 1;( unsigned scsi$v_dis_per_res_msa : 1;) unsigned scsi$v_dis_per_res_vers : 1;) unsigned scsi$v_dis_per_res_hpxp : 1;N unsigned scsi$v_dis_per_res_bit8 : 1; /* Reserved for future devices */) unsigned scsi$v_dis_per_res_bit9 : K 1;) unsigned scsi$v_dis_per_res_bita : 1;) unsigned scsi$v_dis_per_res_bitb : 1;) unsigned scsi$v_dis_per_res_bitc : 1;) unsigned scsi$v_dis_per_res_bitd : 1;) unsigned scsi$v_dis_per_res_bite : 1;) unsigned scsi$v_dis_per_res_bitf : 1;N/* X-33 */N/* Initialize all-transport RWH mask */N/* Add SCSI to mask K*/N unsigned scsi$v_rwh_scsi : 1; /* Enable SCSI R/W History */N/* Add FibreChannel to mask */N unsigned scsi$v_rwh_fc : 1; /* Enable FibreChannel R/W History */N/* Add SW iSCSI to mask */N unsigned scsi$v_rwh_sw_iscsi : 1; /* Enable SW iSCSI R/W History */N/* Add HW iSCSI to mask */N unsigned scsi$v_rw Kh_hw_iscsi : 1; /* Enable HW iSCSI R/W History */N/* Add SAS to mask */N unsigned scsi$v_rwh_sas : 1; /* Enable SAS R/W History */T unsigned scsi$v_fix_os_mode : 1; /* X-34 Allow OS mode bit update (QLogic) */! unsigned scsi$v_reserved : 8;, unsigned scsi$v_crash_on_reset_fail : 1;) unsigned scsi$v_enable_pkr_reset : 1; char scsi$b_fill_0_ [4]; } FIBRE_SCSI_RSV1;N/* K */N/* INQUIRY command */N/* */P/* The Inquiry command is also defined in the class drivers and in SCSI2AUTO. */P/* It is defined here for use by IOGEN$FIBRE_CONFIG and any other module that */N/* might need it. */N/* K */#define INQ_CMD$K_INQ_OPCODE 18 #define INQ_CMD$M_ENABLE_VPD 0x1"#define INQ_CMD$M_COMMAND_DATA 0x2#define INQ_CMD$K_LENGTH 6 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _inq_cmd {#pragma __nomember_alignmentN unsigned char inq_cmd$b_opcode; /* Operation code */ __ Kunion {& unsigned char inq_cmd$b_flags; __struct {X unsigned inq_cmd$v_enable_vpd : 1; /* Enable return of Vital Product Data */\ unsigned inq_cmd$v_command_data : 1; /* Enable return of Command Support Data */N unsigned inq_cmd$v_reserved1 : 6; /* reserved */# } inq_cmd$r_flags_bits;" } inq_cmd$r_flags_overlay;V unsigned char inq_cmd$b_vpd_page; /* VPD page or command support query opcode */N unsi Kgned char inq_cmd$b_reserved2; /* reserved */N unsigned char inq_cmd$b_alloc_length; /* Allocation length */N unsigned char inq_cmd$b_control; /* Control byte */ char inq_cmd$b_fill_1_ [2]; } INQ_CMD; #if !defined(__VAXC)?#define inq_cmd$b_flags inq_cmd$r_flags_overlay.inq_cmd$b_flags^#define inq_cmd$v_enable_vpd inq_cmd$r_flags_overlay.inq_cmd$r_flags_bits.inq_cmd$v_enable_vpdb#define inq_cmd$v_command_data inq_cKmd$r_flags_overlay.inq_cmd$r_flags_bits.inq_cmd$v_command_data"#endif /* #if !defined(__VAXC) */ N/* */N/* Standard INQUIRY data */N/* */S/* The standard inquiry data contains 36 bytes, followed by a variable number of */N/* vendor specific parameters. K*/N/* */##define SCSI$INQ$M_DEVICE_TYPE 0x1F\#define SCSI$C_DISK 0 /* 00: Direct-access device (e.g., magnetic disk) */`#define SCSI$C_TAPE 1 /* 01: Sequential-access device (e.g., magnetic tape) */N#define SCSI$C_PRINTER 2 /* 02: Printer device */N#define SCSI$C_CPU 3 /* 03: Processor device */N#define SCSI$C_WORM 4 K /* 04: Write-once device */N#define SCSI$C_CDROM 5 /* 05: CD-ROM device */N#define SCSI$C_SCANNER 6 /* 06: Scanner device */b#define SCSI$C_OPTICAL 7 /* 07: Optical memory device (e.g., some optical disks) */Y#define SCSI$C_JUKEBOX 8 /* 08: Medium Changer device (e.g., jukeboxes) */N#define SCSI$C_INTERCONNECT 9 /* 09: Communications device */N/* 0A: Reserved K */N/* 0B: Reserved */Q#define SCSI$C_SCC 12 /* 0C: Storage array controller (RAID) */N#define SCSI$C_ENC_SVCS 13 /* 0D: Enclosure services */N#define SCSI$C_RBC 14 /* 0E: Simplified direct-access */N/* 0F-16: Reserved */N/* 17-1E: Reserved K */N#define SCSI$C_UNKNOWN 31 /* 1F: Unknown or no device type */!#define SCSI$INQ$M_QUALIFIER 0xE0S#define SCSI$C_LUN_CONNECTED 0 /* Peripheral device is connected to LUN */W#define SCSI$C_LUN_NOCONNECT 1 /* Peripheral device is not connected to LUN */U#define SCSI$C_LUN_UNAVAILABLE 3 /* Peripheral device does not support LUNs */ #define SCSI$INQ$M_MODIFIER 0x7F#define SCSI$INQ$M_RMB 0x80##define SCSI$INQ$M_ANSI_VERSIOKN 0x7S#define SCSI$C_ANSI_UNKNOWN 0 /* 0: The device ANSI version is unknown */a#define SCSI$C_ANSI_SCSI_1 1 /* 1: The device complies to SCSI-1 (ANSI X3.131-1986) */[#define SCSI$C_ANSI_SCSI_2 2 /* 2: The device complies to SCSI-2 (revision ?) */T#define SCSI$C_ANSI_SCSI_3_SPC1 3 /* 3: The device complies to SCSI-3 SPC-1 */T#define SCSI$C_ANSI_SCSI_3_SPC2 4 /* 4: The device complies to SCSI-3 SPC-2 */T#define SCSI$C_ANSI_SCSI_3_SPC3 5 /* 5: KThe device complies to SCSI-3 SPC-3 */T#define SCSI$C_ANSI_SCSI_3_SPC4 6 /* 6: The device complies to SCSI-3 SPC-4 */N#define SCSI$C_ANSI_SCSI_3 3 /* 3: The device complies to SCSI_3 */$#define SCSI$INQ$M_ECMA_VERSION 0x38##define SCSI$INQ$M_ISO_VERSION 0xC0'#define SCSI$INQ$M_RESP_DATA_FORMAT 0xFN#define SCSI$C_SCSI_1 0 /* INQUIRY data in SCSI-1 format */O#define SCSI$C_OTHER 1 /* INQUIRY data in pre-SCSI-2 format */N#define SCSI$C_SCSI_ K2 2 /* INQUIRY data in SCSI-2 format */(#define SCSI$INQ$M_HIERARCH_SUPPORT 0x10"#define SCSI$INQ$M_NORMAL_ACA 0x20#define SCSI$INQ$M_TRMIOP 0x40#define SCSI$INQ$M_AENC 0x80#define SCSI$INQ$M_PROTECT 0x1#define SCSI$INQ$M_3PC 0x8#define SCSI$INQ$M_TPGS 0x30O#define SCSI$INQ$C_NO_ASYM 0 /* No asymmetric logical unit access */N#define SCSI$INQ$C_IMPLICIT_ASYM_ONLY 1 /* Implicit asymmetric access only */N#define SCSI$INQ$C_EXPLICIT_ASYM_ONLY 2 /* Explicit as Kymmetric access only */d#define SCSI$INQ$C_IMPL_EXPL_ASYM 3 /* Both implicit and explicit asymmetric access supported */#define SCSI$INQ$M_ACC 0x40##define SCSI$INQ$M_SSC_SUPPORT 0x80$#define SCSI$INQ$M_ADDRESS_16BIT 0x1$#define SCSI$INQ$M_ADDRESS_32BIT 0x2$#define SCSI$INQ$M_REQ_ACK_XFERS 0x4%#define SCSI$INQ$M_MEDIUM_CHANGER 0x8"#define SCSI$INQ$M_MULTI_PORT 0x10$#define SCSI$INQ$M_VENDOR_SPEC1 0x20&#define SCSI$INQ$M_ENCLOSURE_SVCS 0x40%#define SCSI$INQ$M_BASIC_QUEUING 0x80#dKefine SCSI$INQ$M_SFTRE 0x1#define SCSI$INQ$M_CMDQUE 0x2##define SCSI$INQ$M_XFER_DISABLE 0x4#define SCSI$INQ$M_LINKED 0x8#define SCSI$INQ$M_SYNC 0x10#define SCSI$INQ$M_WBUS16 0x20#define SCSI$INQ$M_WBUS32 0x40#define SCSI$INQ$M_RELADR 0x80%#define INQ_DATA$K_STANDARD_LENGTH 36#define SCSI$INQ$M_IUS 0x1#define SCSI$INQ$M_QAS 0x2#define SCSI$INQ$M_CLOCKING 0xCN#define SCSI$C_ST_ONLY 0 /* Device server supports only ST */N#define SCSI$C_DT_ONLY 1 K/* Device server supports only DT */N#define SCSI$C_ST_AND_DT 3 /* Device server supports ST and DT */ #define SCSI$INQ$M_RESERVED3 0xF$#define SCSI$INQ$M_OTHER_STATUS 0x10 #define SCSI$INQ$M_MULTIBUS 0x20'#define SCSI$INQ$M_BOOT_PREFERENCE 0x40'#define SCSI$INQ$M_EXT_LUN_SUPPORT 0x80#define INQ_DATA$K_LENGTH 255 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma K__nomember_alignment#endiftypedef struct _inquiry_data {#pragma __nomember_alignmentR __struct { /* Peripheral device types & qualifiers */N unsigned scsi$inq$v_device_type : 5; /* Peripheral device type */N unsigned scsi$inq$v_qualifier : 3; /* Peripheral qualifer */ } scsi$inq$r_peripheral;N __struct { /* Device Type Modifiers */N unsigned scsi$inq$v_modifier : 7; /* SCSI-2: Dev Kice Type Modifiers */N unsigned scsi$inq$v_rmb : 1; /* Removalable media bit */% } scsi$inq$r_device_type_mod;N __struct { /* SCSI Versions */N unsigned scsi$inq$v_ansi_version : 3; /* ANSI Approved Version */N unsigned scsi$inq$v_ecma_version : 3; /* ECMA version number */N unsigned scsi$inq$v_iso_version : 2; /* ISO version number */ } scsi$inq$r_version;N __struKct { /* SCSI INQUIRY Flags */V unsigned scsi$inq$v_resp_data_format : 4; /* Response data (INQUIRY) format */b unsigned scsi$inq$v_hierarch_support : 1; /* SCSI-3: Hierarchical addressing model used */P unsigned scsi$inq$v_normal_aca : 1; /* SCSI-3: CDB NACA bit supported */S unsigned scsi$inq$v_trmiop : 1; /* Device supports terminate I/O process */W unsigned scsi$inq$v_aenc : 1; /* Device supports Asych. Event Notifica Ktion */ } scsi$inq$r_flags_1;W unsigned char scsi$inq$b_add_length; /* Additional length in bytes of parameters */ __struct {] unsigned scsi$inq$v_protect : 1; /* Logical unit supports protection information */N unsigned scsi$inq$v_reserved2 : 2; /* reserved */N unsigned scsi$inq$v_3pc : 1; /* Third-party Copy support */N unsigned scsi$inq$v_tpgs : 2; /* Target port group support */\ unsigned scsKi$inq$v_acc : 1; /* Device contains an access controls coordinator */g unsigned scsi$inq$v_ssc_support : 1; /* SCSI-3: Device has embedded storage array controller */ } scsi$inq$r_sscs;N __struct { /* SCSI-3 Flags */T unsigned scsi$inq$v_address_16bit : 1; /* 16 bit SCSI addresses supported */T unsigned scsi$inq$v_address_32bit : 1; /* 32 bit SCSI addresses supported */[ unsigned scsi$inq$v_req_ack_xfers : 1;K /* Request/Acknowledge transfer supported */Y unsigned scsi$inq$v_medium_changer : 1; /* Device has medium transport element */N unsigned scsi$inq$v_multi_port : 1; /* Device has 2 or more ports */N unsigned scsi$inq$v_vendor_spec1 : 1; /* Defined by vendor */f unsigned scsi$inq$v_enclosure_svcs : 1; /* Device has embedded enclosure services component */` unsigned scsi$inq$v_basic_queuing : 1; /* Basic task management (SAM) model supported */ K } scsi$inq$r_flags_2;N __struct { /* SCSI INQUIRY Flags */n unsigned scsi$inq$v_sftre : 1; /* SCSI-2: Device supports soft resets. (SCSI-3: vendor-specific). */U unsigned scsi$inq$v_cmdque : 1; /* Device supports tagged command queueing */k unsigned scsi$inq$v_xfer_disable : 1; /* SCSI-3: Supports continue task, target transfer disable */N unsigned scsi$inq$v_linked : 1; /* Device supports linked commands */S Kunsigned scsi$inq$v_sync : 1; /* Device supports synchronous data xfer */O unsigned scsi$inq$v_wbus16 : 1; /* Device supports 16-bit data xfers */O unsigned scsi$inq$v_wbus32 : 1; /* Device supports 32-bit data xfers */^ unsigned scsi$inq$v_reladr : 1; /* Device supports relative address for linked cmds */ } scsi$inq$r_flags;N char scsi$inq$b_vendor_id [8]; /* Vendor Identification field */N char scsi$inq$b_product_id [16]; /* Product IdentifKication field */N char scsi$inq$b_product_revision [4]; /* Vendor Product Revision level */W unsigned char scsi$inq$b_this_serial_no [10]; /* This controller's serial number */Y unsigned char scsi$inq$b_other_serial_no [10]; /* Other controller's serial number */W __struct { /* Additional SCSI INQUIRY Flags from SPC-3 */Q unsigned scsi$inq$v_ius : 1; /* Indicates Information Units support */_ unsigned scsi$inq$v_qas : 1; /* IndicKates Quick Arbitration and Selection support */` unsigned scsi$inq$v_clocking : 2; /* Indicates ST and DT synchronous transfer support */N unsigned scsi$inq$v_reserved7 : 4; /* reserved */ } scsi$inq$r_flags_4;N unsigned char scsi$inq$b_reserved2 [39]; /* reserved */N __struct { /* SCSI-3 Flags */N unsigned scsi$inq$v_reserved3 : 4; /* reserved */N K unsigned scsi$inq$v_other_status : 1; /* Other controller is up */Q unsigned scsi$inq$v_multibus : 1; /* In multi-bus failover mode (HCCF) */b unsigned scsi$inq$v_boot_preference : 1; /* Owned by this controller at controller boot */Q unsigned scsi$inq$v_ext_lun_support : 1; /* 32 LUNs per target support */ } scsi$inq$r_flags_3;Y unsigned char scsi$inq$b_preferred_luns [32]; /* LUNs preferred to this controller */N unsigned char scsi$inq$b_reserved4; K/* reserved */R unsigned char scsi$inq$b_node_id [8]; /* Alternate location for node's WWID */N unsigned __int64 scsi$inq$q_reserved5 [13]; /* reserved */N unsigned char scsi$inq$b_allocation_class [4]; /* Allocation class */N unsigned char scsi$inq$b_reserved6 [9]; /* reserved */N unsigned char scsi$inq$b_fill1; /* Fill for alignment */ } INQUIRY_DATA; #if !defined(__VAXC)K#define scsi$iKnq$v_device_type scsi$inq$r_peripheral.scsi$inq$v_device_typeG#define scsi$inq$v_qualifier scsi$inq$r_peripheral.scsi$inq$v_qualifierJ#define scsi$inq$v_modifier scsi$inq$r_device_type_mod.scsi$inq$v_modifier@#define scsi$inq$v_rmb scsi$inq$r_device_type_mod.scsi$inq$v_rmbJ#define scsi$inq$v_ansi_version scsi$inq$r_version.scsi$inq$v_ansi_versionJ#define scsi$inq$v_ecma_version scsi$inq$r_version.scsi$inq$v_ecma_versionH#define scsi$inq$v_iso_version scsi$inq$r_version.scsi$inq$v_iso_versionRK#define scsi$inq$v_resp_data_format scsi$inq$r_flags_1.scsi$inq$v_resp_data_formatR#define scsi$inq$v_hierarch_support scsi$inq$r_flags_1.scsi$inq$v_hierarch_supportF#define scsi$inq$v_normal_aca scsi$inq$r_flags_1.scsi$inq$v_normal_aca>#define scsi$inq$v_trmiop scsi$inq$r_flags_1.scsi$inq$v_trmiop:#define scsi$inq$v_aenc scsi$inq$r_flags_1.scsi$inq$v_aenc=#define scsi$inq$v_protect scsi$inq$r_sscs.scsi$inq$v_protect5#define scsi$inq$v_3pc scsi$inq$r_sscs.scsi$inq$v_3pc7#define scsi$inq$v_tpgKs scsi$inq$r_sscs.scsi$inq$v_tpgs5#define scsi$inq$v_acc scsi$inq$r_sscs.scsi$inq$v_accE#define scsi$inq$v_ssc_support scsi$inq$r_sscs.scsi$inq$v_ssc_supportL#define scsi$inq$v_address_16bit scsi$inq$r_flags_2.scsi$inq$v_address_16bitL#define scsi$inq$v_address_32bit scsi$inq$r_flags_2.scsi$inq$v_address_32bitL#define scsi$inq$v_req_ack_xfers scsi$inq$r_flags_2.scsi$inq$v_req_ack_xfersN#define scsi$inq$v_medium_changer scsi$inq$r_flags_2.scsi$inq$v_medium_changerF#define scsi$inq$v_multi_porKt scsi$inq$r_flags_2.scsi$inq$v_multi_portJ#define scsi$inq$v_vendor_spec1 scsi$inq$r_flags_2.scsi$inq$v_vendor_spec1N#define scsi$inq$v_enclosure_svcs scsi$inq$r_flags_2.scsi$inq$v_enclosure_svcsL#define scsi$inq$v_basic_queuing scsi$inq$r_flags_2.scsi$inq$v_basic_queuing:#define scsi$inq$v_sftre scsi$inq$r_flags.scsi$inq$v_sftre<#define scsi$inq$v_cmdque scsi$inq$r_flags.scsi$inq$v_cmdqueH#define scsi$inq$v_xfer_disable scsi$inq$r_flags.scsi$inq$v_xfer_disable<#define scsi$inq$v_linked scsi$i Knq$r_flags.scsi$inq$v_linked8#define scsi$inq$v_sync scsi$inq$r_flags.scsi$inq$v_sync<#define scsi$inq$v_wbus16 scsi$inq$r_flags.scsi$inq$v_wbus16<#define scsi$inq$v_wbus32 scsi$inq$r_flags.scsi$inq$v_wbus32<#define scsi$inq$v_reladr scsi$inq$r_flags.scsi$inq$v_reladr8#define scsi$inq$v_ius scsi$inq$r_flags_4.scsi$inq$v_ius8#define scsi$inq$v_qas scsi$inq$r_flags_4.scsi$inq$v_qasB#define scsi$inq$v_clocking scsi$inq$r_flags_4.scsi$inq$v_clockingD#define scsi$inq$v_reserved3 scsi$inq$r_flags_3. Kscsi$inq$v_reserved3J#define scsi$inq$v_other_status scsi$inq$r_flags_3.scsi$inq$v_other_statusB#define scsi$inq$v_multibus scsi$inq$r_flags_3.scsi$inq$v_multibusP#define scsi$inq$v_boot_preference scsi$inq$r_flags_3.scsi$inq$v_boot_preferenceP#define scsi$inq$v_ext_lun_support scsi$inq$r_flags_3.scsi$inq$v_ext_lun_support"#endif /* #if !defined(__VAXC) */  b #define inquiry_data _inquiry_data /* Make compatible with former inquiry_data definitionN/* K */N/* Mode Parameter Header (six byte) */N/* */ struct mode_param_hdr_6 {N unsigned char scsi$mph6$b_data_length; /* Mode data Length */N unsigned char scsi$mph6$b_medium_type; /* Medium type */N unsigned char scsi$mph6$b_device_param; /* Device-specific parameter */N unsigned char scsi$mph K6$b_block_length; /* Block descriptor length */ } ;N/* */N/* Mode Parameter Header (ten byte) */N/* */ struct mode_param_hdr_10 {N unsigned short int scsi$mph10$w_data_length; /* Mode data Length */N unsigned char scsi$mph10$b_medium_type; /* Medium type */N unsignKed char scsi$mph10$b_device_param; /* Device-specific parameter */N unsigned char scsi$mph10$b_reserved1 [2]; /* Reserved */O unsigned short int scsi$mph10$w_block_length; /* Block descriptor length */ } ;N/* */N/* Mode Parameters used with direct access devices (DK) */N/* */a#define SCSI$DK$C_DEFAULKT 0 /* Default medium type (currently mounted medium type) */]#define SCSI$DK$C_SS 1 /* Flexible disk, single-sided; unspecified medium */]#define SCSI$DK$C_DS 2 /* Flexible disk, double-sided; unspecified medium */Y#define SCSI$DK$C_DD 3 /* Flexible disk, double-sided; double-density */N/* */N/* Direct-Access params K */N/* */#define SCSI$DK$M_DPOFUA 0x10#define SCSI$DK$M_WP 0x80 struct disk_specific_param {N unsigned scsi$dk$v_reserved1 : 4; /* Reserved */P unsigned scsi$dk$v_dpofua : 1; /* Disable Page Out/Force Unit Access */N unsigned scsi$dk$v_reserved2 : 2; /* Reserved */N unsigned scsi$dk$v_wp : 1; /* Write Protect K*/ } ;N/* */N/* CD-ROM specific parameter */N/* */#define SCSI$CD$M_EBC 0x1#define SCSI$CD$M_CACHE 0x10 struct cdrom_specific_param {N unsigned scsi$cd$v_ebc : 1; /* Enable Blank Check */N unsigned scsi$cd$v_reserved1 : 3; /* Reserved */ KN unsigned scsi$cd$v_cache : 1; /* Device supports cache memory */N unsigned scsi$cd$v_reserved2 : 3; /* Reserved */ } ;N/* */N/* Mode Parameter Block Descriptor */N/* */ struct mode_parameter {N unsigned char scsi$mpbd$b_density; /* Device specific densiKty code */R unsigned char scsi$mpbd$b_block [3]; /* # of logical blocks density applies */N char scsi$mpbd$b_reserved1; /* Reserved */P unsigned char scsi$mpbd$b_length [3]; /* # of bytes in each logical block */ } ;N/* */N/* Identify Message */N/* K */#define SCSI$IDENT$M_LUNTRN 0x7 #define SCSI$IDENT$M_LUNTAR 0x20##define SCSI$IDENT$M_DISC_PRIV 0x40"#define SCSI$IDENT$M_IDENTIFY 0x80 struct identify_message { __struct {N unsigned scsi$ident$v_luntrn : 3; /* Logical Unit Target Routine # */- unsigned scsi$ident$v_reserved_1 : 1;- unsigned scsi$ident$v_reserved_2 : 1;N unsigned scsi$ident$v_luntar : 1; /* Logical Unit Target direction */Z unsigned scsi$ident$v_disc_priv : 1; /* Gran Kt target privilege of disconnecting */P unsigned scsi$ident$v_identify : 1; /* Message is an IDENTIFY message */ } scsi$ident$r_flags; } ; #if !defined(__VAXC)B#define scsi$ident$v_luntrn scsi$ident$r_flags.scsi$ident$v_luntrnB#define scsi$ident$v_luntar scsi$ident$r_flags.scsi$ident$v_luntarH#define scsi$ident$v_disc_priv scsi$ident$r_flags.scsi$ident$v_disc_privF#define scsi$ident$v_identify scsi$ident$r_flags.scsi$ident$v_identify"#endif /* #if !defined(__VAXC) */K N/* */N/* Define SCSI status codes */N/* */N#define SCSI$C_GOOD 0 /* Sucessfull completion of command */N#define SCSI$C_CHECK_CONDITION 2 /* Contingent allegiance condition */N#define SCSI$C_CONDITION_MET 4 /* Requested operation satisfied */N#define SCSI$C_BUSY K8 /* Target busy */P#define SCSI$C_INTERMEDIATE 16 /* Completed linked command in series */N#define SCSI$C_INTERMEDIATE_COND_MET 20 /* INTERMEDIATE and CONDITION_MET */N#define SCSI$C_RESERVATION_CONFLICT 24 /* Conflicting reservation conflict */N#define SCSI$C_COMMAND_TERMINATED 34 /* Target terminates current I/O */N#define SCSI$C_QUEUE_FULL 40 /* Command queue is full */N#define SCSI$M_STATUS_BYTE_RESERVED 193 /* SKtatus byte reserved bits */N/* */N/* Define SCSI Message Codes */N/* */N#define SCSI$C_COMMAND_COMPLETE 0 /* I/O completed */O#define SCSI$C_EXTENDED_MESSAGE 1 /* Start multi-byte extended message */N#define SCSI$C_SAVE_DATA_POINTERS 2 /* Save active pointers K */N#define SCSI$C_RESTORE_POINTERS 3 /* Restore saved pointers */N#define SCSI$C_DISCONNECT 4 /* Connection will disconnect */S#define SCSI$C_INITIATOR_DETECT_ERROR 5 /* Inform target that error have occured */O#define SCSI$C_ABORT 6 /* Clear active I/O, plus queued I/O */N#define SCSI$C_MESSAGE_REJECT 7 /* Last message was inappropriate */N#define SCSI$C_NO_OPERATION 8 /* Reponse when no current command */P#definKe SCSI$C_MESSAGE_PARITY_ERROR 9 /* Last message byte had parity error */N#define SCSI$C_LINKED_COMMAND 10 /* Linked command is complete */T#define SCSI$C_LINKED_COMMAND_FLAGED 11 /* Linked command is complete (with flag) */N#define SCSI$C_BUS_DEVICE_RESET 12 /* Reset device, go to bus free */N#define SCSI$C_ABORT_TAG 13 /* Clear tagged command */N#define SCSI$C_CLEAR_QUEUE 14 /* Clear all queued commands */N#define SCSI$C_INITIATE_KRECOVERY 15 /* Start ECA processing */N#define SCSI$C_RELEASE_RECOVERY 16 /* Finish ECA processing */N#define SCSI$C_TERMINATE_IO_PROCESS 17 /* Terminate I/O process */#define SCSI$C_CLEAR_ACA 22N#define SCSI$C_SIMPLE_QUEUE_TAG 32 /* Queue I/O to queue */N#define SCSI$C_HEAD_OF_QUEUE_TAG 33 /* Queue I/O to head of queue */N#define SCSI$C_ORDERED_QUEUE_TAG 34 /* Queue I/O in order to queue */N#define SCSI$C_IGNORKE_WIDE_RESIDUE 35 /* Ignore residual bytes */N/* */N/* Define SCSI Message Codes */N/* */N#define SCSI$C_MODIFY_DATA_POINTER 0 /* Modify data pointers */O#define SCSI$C_SYNCH_DATA_TRANSFER 1 /* Synchronous Data Transfer Request */N#define SCSI$C_WIDE_DATA_TRANSFER 3 /* W Kide Data Transfer Request */N/* */N/* Sense Data Format */N/* */"#define SCSI$SNS$M_ERROR_CODE 0x7FN#define SCSI$SC1$C_CURRENT 112 /* Current error codes */N#define SCSI$SC1$C_DEFERRED 113 /* Current error codes */#define SCSI$SNS$M_VALID 0x80 #d Kefine SCSI$SNS$M_SENSE_KEY 0xF#define SCSI$SNS$M_ILI 0x20#define SCSI$SNS$M_EOM 0x40 #define SCSI$SNS$M_FILEMARK 0x80N#define SCSI$SNS$R_ADD_INFORMATION_OS 8 /* */N#define SCSI$C_RECOVERED_DATA 23 /* Recovered data... */N/* ^X00 - with no error correction applied */N#define SCSI$C_INVALID_CDB_FIELD 36 /* Invalid field in CDB */N/* ^X00 - invalid field in CDB K */"#define SCSI$SNS$M_BIT_POINTER 0x7#define SCSI$SNS$M_BPV 0x8#define SCSI$SNS$M_C_D 0x40#define SCSI$SNS$M_SKSV 0x80N#define SCSI$SNS$R_ADD_SENSE_OS 18 /* */ struct sense_data { __struct {N unsigned scsi$sns$v_error_code : 7; /* Sense data error codes */N unsigned scsi$sns$v_valid : 1; /* Information Field Valid */& } scsi$sns$r_error_code_field;N unsigned char scsi$sns$b_segement; K /* # of current segement desc. */ __struct {N unsigned scsi$sns$v_sense_key : 4; /* Information field */N unsigned scsi$sns$v_reserved1 : 1; /* Reserved */N unsigned scsi$sns$v_ili : 1; /* Incorrect Length Indicator */N unsigned scsi$sns$v_eom : 1; /* End of Medium Indicator */N unsigned scsi$sns$v_filemark : 1; /* Filemark or Setmark seen */ } scsi$sns$r_flags;N __union { K /* Device/Command specific info. */\ unsigned int scsi$sns$l_lba_address; /* Logical Block Address (Dev. Type 0,4,5,7) */d unsigned int scsi$sns$l_residual_length; /* (requested - actual) length (Dev. Type 1,2,3) */j unsigned int scsi$sns$l_residual_blocks; /* (requested - actual) blocks (COPY, VERIFY, COMPARE) */N unsigned int scsi$sns$l_data_blocks; /* Count of Data Blocks */N unsigned int scsi$sns$l_file_marks; /* Count of Fi Lle Marks */N unsigned int scsi$sns$l_set_marks; /* Count of Set Marks */! } scsi$sns$r_information;N unsigned char scsi$sns$b_add_sense_len; /* Additional Sense Length */N __union { /* Command specific info. */O unsigned char scsi$sns$b_sense_information [4]; /* Sense information */% } scsi$sns$r_add_information;N unsigned char scsi$sns$b_add_sense_code; /* Additional Sense Code */N/* ^X0L1 - with retries */N/* ^X02 - with positive head offset */N/* ^X03 - with negative head offset */N/* ^X04 - with retries and/or circ applied */N/* ^X05 - using previous sector id */N/* ^X06 - without ecc - data auto-reallocated */N/* ^X07 - without ecc - recommenLd reassignment */N unsigned char scsi$sns$b_add_sense_qual; /* Additional Sense Qualifier */N unsigned char scsi$sns$b_fru_code; /* Field Replaceable Unit Code */ __struct {Q unsigned scsi$sns$v_bit_pointer : 3; /* Bitfield pointer to error byte */N unsigned scsi$sns$v_bpv : 1; /* Bit Pointer Valid */N unsigned scsi$sns$v_reserved2 : 2; /* Reserved */N unsigned scsi$sns$v_c_d : 1; L /* Command_Data error indicator */N unsigned scsi$sns$v_sksv : 1; /* Sense Key Specific - Valid */] unsigned short int scsi$sns$w_field_pointer; /* Command or Data byte error pointer */( } scsi$sns$r_sense_key_specific;N __struct { /* Additional Sense data0 */R unsigned char scsi$sns$b_add_sense_bytes [1]; /* Additional Sense Bytes */ } scsi$sns$r_add_sense; } ; #if !defined(__VAXC)O#define scLsi$sns$v_error_code scsi$sns$r_error_code_field.scsi$sns$v_error_codeE#define scsi$sns$v_valid scsi$sns$r_error_code_field.scsi$sns$v_validB#define scsi$sns$v_sense_key scsi$sns$r_flags.scsi$sns$v_sense_key6#define scsi$sns$v_ili scsi$sns$r_flags.scsi$sns$v_ili6#define scsi$sns$v_eom scsi$sns$r_flags.scsi$sns$v_eom@#define scsi$sns$v_filemark scsi$sns$r_flags.scsi$sns$v_filemarkL#define scsi$sns$l_lba_address scsi$sns$r_information.scsi$sns$l_lba_addressT#define scsi$sns$l_residual_length scsLi$sns$r_information.scsi$sns$l_residual_lengthT#define scsi$sns$l_residual_blocks scsi$sns$r_information.scsi$sns$l_residual_blocksL#define scsi$sns$l_data_blocks scsi$sns$r_information.scsi$sns$l_data_blocksJ#define scsi$sns$l_file_marks scsi$sns$r_information.scsi$sns$l_file_marksH#define scsi$sns$l_set_marks scsi$sns$r_information.scsi$sns$l_set_marks\#define scsi$sns$b_sense_information scsi$sns$r_add_information.scsi$sns$b_sense_informationS#define scsi$sns$v_bit_pointer scsi$sns$r_sense_ke Ly_specific.scsi$sns$v_bit_pointerC#define scsi$sns$v_bpv scsi$sns$r_sense_key_specific.scsi$sns$v_bpvC#define scsi$sns$v_c_d scsi$sns$r_sense_key_specific.scsi$sns$v_c_dE#define scsi$sns$v_sksv scsi$sns$r_sense_key_specific.scsi$sns$v_sksvW#define scsi$sns$w_field_pointer scsi$sns$r_sense_key_specific.scsi$sns$w_field_pointerR#define scsi$sns$b_add_sense_bytes scsi$sns$r_add_sense.scsi$sns$b_add_sense_bytes"#endif /* #if !defined(__VAXC) */ N/* L */N/* Define SCSI sense key codes. */N/* */O#define SCSI$C_NO_SENSE 0 /* No sense key information returned */Y#define SCSI$C_RECOVERED_ERROR 1 /* Command completed with some recovery action */N#define SCSI$C_NOT_READY 2 /* Logical unit cannot be accessed */\#define SCSI$C_MEDIUM_ERROR 3 /* Command faileLd with non-recovered medium error */^#define SCSI$C_HARDWARE_ERROR 4 /* Command failed with non-recovered hardware error */_#define SCSI$C_ILLEGAL_REQUEST 5 /* Illegal parameter in the command descriptor block */^#define SCSI$C_UNIT_ATTENTION 6 /* Removable medium change or target has been reset */[#define SCSI$C_DATA_PROTECT 7 /* Read/Write of medium failed due to protection */^#define SCSI$C_BLANK_CHECK 8 /* Read/Write found blank medium, end-of-dat La, etc. */Q#define SCSI$C_VENDOR_SPECIFIC 9 /* Vendor specific conditions reported */_#define SCSI$C_COPY_ABORTED 10 /* Copy, compare or Copy/Verify aborted due to error */N#define SCSI$C_ABORTED_COMMAND 11 /* Targeted aborted current command */V#define SCSI$C_EQUAL 12 /* Search Data command has equal comparison */W#define SCSI$C_VOLUME_OVERFLOW 13 /* Buffered device has reach end of parition */X#define SCSI$C_MISCOMPARE 14 /* Source data L command has unequal comparison */N#define SCSI$C_RESERVED 15 /* Reserved */N/* */N/* Selected SCSI Mode Page Codes */N/* */N#define SCSI$C_AUDIO_CONTROL_PAGE 14 /* CD-ROM Audio Control Page */N#define SCSI$C_MEDIA_CHANGE 40 /* Medium change  L */N/* ^X00 - Not ready to ready transition (medium change) */N#define SCSI$C_MODE_CHANGE 42 /* Mode change */N/* ^X00 - Parameters changed */N/* ^X01 - Mode parameters changed */N/* ^X02 - Log parameters changed */N#define SCSI$C_INCOMPATIBLE_MEDIA 48 /* Unformatted media */N/* ^X00 - Incomp Latible medium installed */N/* ^X01 - Cannot read medium - unknown format */N/* ^X02 - Cannot read medium - incompatible format */N/* ^X03 - Cleaning cartridge installed */N#define SCSI$C_DRIVE_NOT_READY 4 /* Logical unit... */N/* ^X00 - not ready, cause not reportable */N/* ^X01 - is in process of becoming ready  L */N/* ^X02 - not ready, initializing command required */N/* ^X03 - not ready, manual intervention required */N/* ^X04 - not ready, format in progress */N#define SCSI$C_MEDIUM_NOT_PRESENT 58 /* Medium not present */N/* ^X00 - Medium not present ? */N/* L */N/* Type codes for Optical Memory Medium-Type Codes */N/* */V#define SCSI$OPT$C_MEDIA_DEFAULT 0 /* Default (only one medium type supported) */N#define SCSI$OPT$C_MEDIA_RO 1 /* Optical Read Only medium */N#define SCSI$OPT$C_MEDIA_WORM 2 /* Optical Write Once medium */S#define SCSI$OPT$C_MEDIA_ERASE 3 /* Optical Reversible or Erasable medium */\L#define SCSI$OPT$C_MEDIA_RO_WORM 4 /* Combination of Read only and Write Once medium */h#define SCSI$OPT$C_MEDIA_RO_ERASE 5 /* Combination of Read only and Reversible or Erasable medium */i#define SCSI$OPT$C_MEDIA_WORM_ERASE 6 /* Combination of Write Once and Reversible or Erasable medium */N/* */N/* Mode sense page code paramaters */N/* L */\#define SCSI$PGCD$C_VENDOR_SPECIFIC 0 /* Vendor-Specific (does not require page format) */N#define SCSI$PGCD$C_READ_WRITE_ERR 1 /* Read-Write Error Recovery Page */N#define SCSI$PGCD$C_DISCONNECT_REC 2 /* Disconnect-Reconnect Page */N#define SCSI$PGCD$C_FORMAT_DEVICE 3 /* Format Device Page */N#define SCSI$PGCD$C_RIGID_DISK 4 /* Rigid Disk Geometry Page */N#define SCSI$PGCD$C_FLEXIBLE_DISK 5 /* FlexiblLe Disk Page */N#define SCSI$PGCD$C_RESERVED 6 /* Reserved */N#define SCSI$PGCD$C_VERIFY_ERROR 7 /* Verify Error Recovery Page */N#define SCSI$PGCD$C_CACHING 8 /* Caching Page */N#define SCSI$PGCD$C_PERIPHERAL 9 /* Peripheral Device Page */N#define SCSI$PGCD$C_CONTROL_MODE 10 /* Control Mode Page */N#define SCSI$PGCD$C_MEDIUM_TYPES 11 /* Medium Types Supported Page L*/N#define SCSI$PGCD$C_NOTCH_PARTION 12 /* Notch and Partition Page */N#define SCSI$PGCD$C_ALL_PAGES 63 /* Return all pages */N#define SCSI$PGCD$C_MAX_PAGE_CODE 63 /* Maximum Page Code */N#define SCSI$PGCD$M_CURRENT 0 /* Current Values */N#define SCSI$PGCD$M_CHANGEABLE 64 /* Changeable Values */N#define SCSI$PGCD$M_DEFAULT 128 /* Default Values */N#define SCSI$PGCD$M_SA LVED 192 /* Saved Values */N#define SCSI$PGCD$C_PAGE_SIZE 512 /* Initial Page Size */N/* */N/* Audio Control Parameters Page */N/* */!#define SCSI$ACP$M_PAGE_CODE 0x3F#define SCSI$ACP$C_PAGE_CODE 14#define SCSI$ACP$M_PS 0x80[#define SCSI$S_HEADER 2 L /* SCSI Page header size (PAGE_CODE+PAGE_LENGTH) */!#define SCSI$ACP$C_PAGE_LENGTH 14#define SCSI$ACP$M_SOTC 0x2#define SCSI$ACP$M_IMMED 0x4'#define SCSI$ACP$M_LBA_FORMAT 0xF000000 #define SCSI$ACP$M_CHANNEL_0 0x1 #define SCSI$ACP$M_CHANNEL_1 0x2 #define SCSI$ACP$M_CHANNEL_2 0x4 #define SCSI$ACP$M_CHANNEL_3 0x8 struct audio_control {N __struct { /* Page code & save bits */N unsigned scsi$acp$v_page_code : 6; /* Page code L */* unsigned scsi$acp$v_reserved1 : 1;T unsigned scsi$acp$v_ps : 1; /* PS - Parameters Saveable bit in non-VM */% } scsi$acp$r_page_code_field;N unsigned char scsi$acp$b_page_length; /* Page length */N __struct { /* Audio Control Flags */* unsigned scsi$acp$v_reserved2 : 1;N unsigned scsi$acp$v_sotc : 1; /* Stop On Track Crossing */P unsigned scsi$acp$v_imme Ld : 1; /* Send completion status immediately */+ unsigned scsi$acp$v_reserved3 : 21;N unsigned scsi$acp$v_lba_format : 4; /* Format of LBSa / Second */( unsigned scsi$acp$v_fill_4_ : 4;) } scsi$acp$r_audio_control_flags;^ unsigned short int scsi$acp$w_lbs_per_sec; /* Logical blocks per sec. of audio playback */ __union {9 unsigned short int scsi$acp$w_channel_volume [4]; __struct {Y unsigned scsi$acp$v_channel_0 : 1; /* LConnect audio channel 0 to this port */Y unsigned scsi$acp$v_channel_1 : 1; /* Connect audio channel 1 to this port */Y unsigned scsi$acp$v_channel_2 : 1; /* Connect audio channel 2 to this port */Y unsigned scsi$acp$v_channel_3 : 1; /* Connect audio channel 3 to this port */. unsigned scsi$acp$v_reserved4 : 4;` unsigned char scsi$acp$b_volume; /* Channel volume from %X00(muted) to %XFF(full) */! } scsi$acp$r_fill_3_; L } scsi$acp$r_fill_2_; } ; #if !defined(__VAXC)L#define scsi$acp$v_page_code scsi$acp$r_page_code_field.scsi$acp$v_page_code>#define scsi$acp$v_ps scsi$acp$r_page_code_field.scsi$acp$v_psF#define scsi$acp$v_sotc scsi$acp$r_audio_control_flags.scsi$acp$v_sotcH#define scsi$acp$v_immed scsi$acp$r_audio_control_flags.scsi$acp$v_immedR#define scsi$acp$v_lba_format scsi$acp$r_audio_control_flags.scsi$acp$v_lba_formatN#define scsi$acp$w_channel_volume scsi$acp$r_fill_2_.scsi$acp$w_channel_ LvolumeW#define scsi$acp$v_channel_0 scsi$acp$r_fill_2_.scsi$acp$r_fill_3_.scsi$acp$v_channel_0W#define scsi$acp$v_channel_1 scsi$acp$r_fill_2_.scsi$acp$r_fill_3_.scsi$acp$v_channel_1W#define scsi$acp$v_channel_2 scsi$acp$r_fill_2_.scsi$acp$r_fill_3_.scsi$acp$v_channel_2W#define scsi$acp$v_channel_3 scsi$acp$r_fill_2_.scsi$acp$r_fill_3_.scsi$acp$v_channel_3Q#define scsi$acp$b_volume scsi$acp$r_fill_2_.scsi$acp$r_fill_3_.scsi$acp$b_volume"#endif /* #if !defined(__VAXC) */ N/* L */N/* Control Mode Page */N/* */!#define SCSI$CMP$M_PAGE_CODE 0x3F#define SCSI$CMP$C_PAGE_CODE 10#define SCSI$CMP$M_PS 0x80 #define SCSI$CMP$C_PAGE_LENGTH 6#define SCSI$CMP$M_RLEC 0x1#define SCSI$CMP$M_DQUE 0x100#define SCSI$CMP$M_QERR 0x200#define SCSI$CMP$M_QAM 0x7000N#define SCSI$QAM$C_RES LTRICTED 0 /* Restricted Re-ordering */N#define SCSI$QAM$C_UNRESTRICTED 1 /* Unrestricted Re-ordering */#define SCSI$CMP$M_EAENP 0x8000!#define SCSI$CMP$M_UAAENP 0x10000 #define SCSI$CMP$M_RAENP 0x20000 #define SCSI$CMP$M_EECA 0x400000R#define SCSI$CMP$C_LENGTH 8 /* Length of the SCSI Control Mode page */R#define SCSI$CMP$K_LENGTH 8 /* Length of the SCSI Control Mode page */ struct control_mode {N __struct { L /* Page code & save bits */N unsigned scsi$cmp$v_page_code : 6; /* Page code */* unsigned scsi$cmp$v_reserved1 : 1;T unsigned scsi$cmp$v_ps : 1; /* PS - Parameters Saveable bit in non-VM */% } scsi$cmp$r_page_code_field;N unsigned char scsi$cmp$b_page_length; /* Page length */N __struct { /* Control Mode Flags */U unsigned scsi$cmp$v_rlec : 1; /* Targer Lreports log exception conditions */* unsigned scsi$cmp$v_reserved2 : 7;N unsigned scsi$cmp$v_dque : 1; /* Disable tagged queuing */Q unsigned scsi$cmp$v_qerr : 1; /* Abort queue processing on CA or ACA */* unsigned scsi$cmp$v_reserved3 : 2;N unsigned scsi$cmp$v_qam : 3; /* Queue Algorithm Modifier Field */N unsigned scsi$cmp$v_eaenp : 1; /* Error - AEN */N unsigned scsi$cmp$v_uaaenp : 1; /* Unit Attentio Ln - AEN */N unsigned scsi$cmp$v_raenp : 1; /* Ready - AEN */* unsigned scsi$cmp$v_reserved4 : 4;S unsigned scsi$cmp$v_eeca : 1; /* Enable Extended Contingent Allegiance */( unsigned scsi$cmp$v_fill_5_ : 1;( } scsi$cmp$r_control_mode_flags; char scsi$cmp$b_reserved5;N unsigned short int scsi$cmp$w_ready_aen; /* Ready AEN holdoff period */ } ; #if !defined(__VAXC)L#define scsi$cmp$v_page_code scsi$cmp$r_Lpage_code_field.scsi$cmp$v_page_code>#define scsi$cmp$v_ps scsi$cmp$r_page_code_field.scsi$cmp$v_psE#define scsi$cmp$v_rlec scsi$cmp$r_control_mode_flags.scsi$cmp$v_rlecE#define scsi$cmp$v_dque scsi$cmp$r_control_mode_flags.scsi$cmp$v_dqueE#define scsi$cmp$v_qerr scsi$cmp$r_control_mode_flags.scsi$cmp$v_qerrC#define scsi$cmp$v_qam scsi$cmp$r_control_mode_flags.scsi$cmp$v_qamG#define scsi$cmp$v_eaenp scsi$cmp$r_control_mode_flags.scsi$cmp$v_eaenpI#define scsi$cmp$v_uaaenp scsi$cmp$r_control L_mode_flags.scsi$cmp$v_uaaenpG#define scsi$cmp$v_raenp scsi$cmp$r_control_mode_flags.scsi$cmp$v_raenpE#define scsi$cmp$v_eeca scsi$cmp$r_control_mode_flags.scsi$cmp$v_eeca"#endif /* #if !defined(__VAXC) */ N/* */N/* Read-Write Error Recovery Page */N/* */V/* Define the error recover parameters that the !Ltarget shall use during any command */N/* that performs a read-write operation. */N/* */!#define SCSI$ERP$M_PAGE_CODE 0x3F#define SCSI$ERP$C_PAGE_CODE 1#define SCSI$ERP$M_PS 0x80!#define SCSI$ERP$C_PAGE_LENGTH 10#define SCSI$ERP$M_DCR 0x1#define SCSI$ERP$M_DTE 0x2#define SCSI$ERP$M_PER 0x4#define SCSI$ERP$M_EER 0x8#define SCSI$ERP$M_RC 0x10#define SCSI$ERP$M_TB 0x20#defin "Le SCSI$ERP$M_ARRE 0x40#define SCSI$ERP$M_AWRE 0x80T#define SCSI$ERP$C_LENGTH 16 /* Length of the SCSI Error Recovery page */T#define SCSI$ERP$K_LENGTH 16 /* Length of the SCSI Error Recovery page */ struct error_recovery {N __struct { /* Page code & save bits */N unsigned scsi$erp$v_page_code : 6; /* Page code */* unsigned scsi$erp$v_reserved1 : 1;T unsigned scsi$erp$v_ps : 1; /* PS #L- Parameters Saveable bit in non-VM */% } scsi$erp$r_page_code_field;N unsigned char scsi$erp$b_page_length; /* Page length */R __struct { /* Read-Write Error Recovery Page flags */N unsigned scsi$erp$v_dcr : 1; /* Disable error correction */N unsigned scsi$erp$v_dte : 1; /* Disable transfer on error */N unsigned scsi$erp$v_per : 1; /* Post error */N unsigned scsi$$Lerp$v_eer : 1; /* Enable early correction */N unsigned scsi$erp$v_rc : 1; /* Read continuous */N unsigned scsi$erp$v_tb : 1; /* Transfer block */Q unsigned scsi$erp$v_arre : 1; /* Automatic read relocation of blocks */R unsigned scsi$erp$v_awre : 1; /* Automatic write relocation of blocks */$ } scsi$erp$r_recovery_flags;Q unsigned char scsi$erp$b_read_rerty_count; /* Read count of retry attempts */%LZ unsigned char scsi$erp$b_correction_span; /* Bit size of largest data error attempt */^ unsigned char scsi$erp$b_head_offset_count; /* 2's complement of head offset from track */[ unsigned char scsi$erp$b_data_strobe_offset; /* 2's complement of data strobe offset */' unsigned char scsi$erp$b_reserved2;S unsigned char scsi$erp$b_write_retry_count; /* Write count of retry attempts */' unsigned char scsi$erp$b_reserved3;\ unsigned short int scsi$erp$w_recovery_time_limi &Lt; /* ms max. time for error recovery */S char scsi$erp$b_lenfill [4]; /* Fill to a quadword to match basealign */ } ; #if !defined(__VAXC)L#define scsi$erp$v_page_code scsi$erp$r_page_code_field.scsi$erp$v_page_code>#define scsi$erp$v_ps scsi$erp$r_page_code_field.scsi$erp$v_ps?#define scsi$erp$v_dcr scsi$erp$r_recovery_flags.scsi$erp$v_dcr?#define scsi$erp$v_dte scsi$erp$r_recovery_flags.scsi$erp$v_dte?#define scsi$erp$v_per scsi$erp$r_recovery_flags.scsi$erp$v_per?#d 'Lefine scsi$erp$v_eer scsi$erp$r_recovery_flags.scsi$erp$v_eer=#define scsi$erp$v_rc scsi$erp$r_recovery_flags.scsi$erp$v_rc=#define scsi$erp$v_tb scsi$erp$r_recovery_flags.scsi$erp$v_tbA#define scsi$erp$v_arre scsi$erp$r_recovery_flags.scsi$erp$v_arreA#define scsi$erp$v_awre scsi$erp$r_recovery_flags.scsi$erp$v_awre"#endif /* #if !defined(__VAXC) */ N/* */N/* Format Device Page (L */N/* */!#define SCSI$FMT$M_PAGE_CODE 0x3F#define SCSI$FMT$C_PAGE_CODE 3#define SCSI$FMT$M_PS 0x80!#define SCSI$FMT$C_PAGE_LENGTH 22#define SCSI$FMT$M_SURF 0x10#define SCSI$FMT$M_RMB 0x20#define SCSI$FMT$M_HSEC 0x40#define SCSI$FMT$M_SSEC 0x80 struct format_device {N __struct { /* Page code & save bits */N unsigned scsi$fmt$v_page_code : 6; /)L* Page code */* unsigned scsi$fmt$v_reserved1 : 1;T unsigned scsi$fmt$v_ps : 1; /* PS - Parameters Saveable bit in non-VM */% } scsi$fmt$r_page_code_field;N unsigned char scsi$fmt$b_page_length; /* Page length */N unsigned short int scsi$fmt$w_tracks; /* Tracks per Zone */O unsigned short int scsi$fmt$w_alt_sectors; /* Alternate Sectors per Zone */N unsigned short int scsi$fmt$w_alt_tracks; /* Alternate*L Tracks per Zone */Z unsigned short int scsi$fmt$w_alt_tracks_unit; /* Alternate Tracks per Logical Unit */N unsigned short int scsi$fmt$w_sectors; /* Sectors per Track */S unsigned short int scsi$fmt$w_sector_size; /* Data Bytes per Physical Sector */N unsigned short int scsi$fmt$w_interleave; /* Interleave */N unsigned short int scsi$fmt$w_track_skew; /* Track Skew Factor */N unsigned short int scsi$fmt$w_cyl_skew; /* Cylinder Skew Facto +Lr */ __struct {N unsigned scsi$fmt$v_reserved2 : 4; /* Reserved */N unsigned scsi$fmt$v_surf : 1; /* Sector .vs. Cylindar allocation */N unsigned scsi$fmt$v_rmb : 1; /* Removeable */N unsigned scsi$fmt$v_hsec : 1; /* Hard Sector Formatting */N unsigned scsi$fmt$v_ssec : 1; /* Soft Sector Formatting */ } scsi$fmt$r_flags;N char scsi$fmt$b_reserved3 [3]; /* R ,Leserved */ } ; #if !defined(__VAXC)L#define scsi$fmt$v_page_code scsi$fmt$r_page_code_field.scsi$fmt$v_page_code>#define scsi$fmt$v_ps scsi$fmt$r_page_code_field.scsi$fmt$v_ps8#define scsi$fmt$v_surf scsi$fmt$r_flags.scsi$fmt$v_surf6#define scsi$fmt$v_rmb scsi$fmt$r_flags.scsi$fmt$v_rmb8#define scsi$fmt$v_hsec scsi$fmt$r_flags.scsi$fmt$v_hsec8#define scsi$fmt$v_ssec scsi$fmt$r_flags.scsi$fmt$v_ssec"#endif /* #if !defined(__VAXC) */ N/* -L */N/* Rigid Disk Driver Page */N/* */O/* The rigid disk drive geometry page specifies parameters for direct-access */N/* devices employing a rigid disk drive. */N/* */!#define SCSI$RGD$M_PAGE_CODE 0x3F#define SC .LSI$RGD$C_PAGE_CODE 4#define SCSI$RGD$M_PS 0x80!#define SCSI$RGD$C_PAGE_LENGTH 22#define SCSI$RGD$M_RPL 0x3Q#define SCSI$RGD$C_DISABLED 0 /* Spindle Synchronization is disabled */N#define SCSI$RGD$C_SLAVE 1 /* Synchronized-Spindle Slave */N#define SCSI$RGD$C_MASTER 2 /* Synchronized-Spindle Master. */Q#define SCSI$RGD$C_CONTROL 3 /* Synchronized-Spindle Master Control */ struct rigid_disk {N __struct { /L /* Page code & save bits */N unsigned scsi$rgd$v_page_code : 6; /* Page code */* unsigned scsi$rgd$v_reserved1 : 1;T unsigned scsi$rgd$v_ps : 1; /* PS - Parameters Saveable bit in non-VM */% } scsi$rgd$r_page_code_field;N unsigned char scsi$rgd$b_page_length; /* Page length */N char scsi$rgd$b_cylinders [3]; /* Number of cylinders */N unsigned char scsi$rgd$b_heads; /* Number of h0Leads */_ unsigned short int scsi$rgd$w_cylinder_write; /* Starting Cylinder-Write Precompensation */a unsigned short int scsi$rgd$w_cylinder_reduced; /* Starting Cylinder-Reduced Write Current */N unsigned short int scsi$rgd$w_step_rate; /* Drive Step Rate */N unsigned short int scsi$rgd$w_landing_zone; /* Landing Zone Cylinder */N __struct { /* SCSI FLEXIBLE PAGE Flags */N unsigned scsi$rgd$v_rpl : 2; /* 1L Rotational Position Locking */N unsigned scsi$rgd$v_reserved2 : 6; /* Reserved */ } scsi$rgd$r_flags;N unsigned char scsi$rgd$b_rotational_offset; /* Rotational Offset */N unsigned char scsi$rgd$b_reserved3; /* Reserved */N unsigned short int scsi$rgd$w_medium_rotation; /* Medium Rotation Rate */N unsigned short int scsi$rgd$w_rotational_offset; /* Rotational Offset */ } ; #if !defined(__VAXC)L#d 2Lefine scsi$rgd$v_page_code scsi$rgd$r_page_code_field.scsi$rgd$v_page_code>#define scsi$rgd$v_ps scsi$rgd$r_page_code_field.scsi$rgd$v_ps6#define scsi$rgd$v_rpl scsi$rgd$r_flags.scsi$rgd$v_rpl"#endif /* #if !defined(__VAXC) */ N/* */N/* Flexible Disk Page */N/* */N/* The flexible disk page cont 3Lains parameters for control and reporting of */N/* flexible disk drive parameters */N/* */!#define SCSI$FLX$M_PAGE_CODE 0x3F#define SCSI$FLX$C_PAGE_CODE 5#define SCSI$FLX$M_PS 0x80!#define SCSI$FLX$C_PAGE_LENGTH 30N#define SCSI$FLX$C_XFR_250KHZ 64000 /* 250 kbit/second transfer rate */N#define SCSI$FLX$C_XFR_300KHZ 11265 /* 300 kbit/second transfer rate */N#def 4Line SCSI$FLX$C_XFR_500KHZ 62465 /* 500 kbit/second transfer rate */N#define SCSI$FLX$C_XFR_1MHZ 59395 /* 1 megabit/second transfer rate */N#define SCSI$FLX$C_XFR_2MHZ 53255 /* 2 megabit/second transfer rate */N#define SCSI$FLX$C_XFR_5MHZ 34835 /* 5 megabit/second transfer rate */#define SCSI$FLX$M_MO 0x20#define SCSI$FLX$M_SSN 0x40#define SCSI$FLX$M_TRDY 0x80#define SCSI$FLX$M_SPC 0xF00#define SCSI$FLX$M_PIN2 0x1#define SCSI$FLX$M_PIN34 0x2#define SCSI 5L$FLX$M_PIN1 0x4#define SCSI$FLX$M_PIN4 0x8 struct flexible_disk {N __struct { /* Page code & save bits */N unsigned scsi$flx$v_page_code : 6; /* Page code */* unsigned scsi$flx$v_reserved1 : 1;T unsigned scsi$flx$v_ps : 1; /* PS - Parameters Saveable bit in non-VM */% } scsi$flx$r_page_code_field;N unsigned char scsi$flx$b_page_length; /* Page length */N unsigned short i6Lnt scsi$flx$w_transfer_rate; /* Transfer rate KHZ */N/* (Note: Definitions are SCSI Endian) */N unsigned char scsi$flx$b_heads; /* Number of heads */N unsigned char scsi$flx$b_sectors_track; /* Sectors per track */N unsigned short int scsi$flx$w_sector_size; /* Data bytes per sector */N unsigned short int scsi$flx$w_cylinders; /* Number of cylinders */_ unsigned short int scsi$flx$w_cylinder_wri7Lte; /* Starting Cylinder-Write Precompensation */a unsigned short int scsi$flx$w_cylinder_reduced; /* Starting Cylinder-Reduced Write Current */N unsigned short int scsi$flx$w_step_rate; /* Drive Step Rate */N unsigned char scsi$flx$b_step_pulse; /* Drive Step Pulse Width */N unsigned short int scsi$flx$w_head_settle; /* Head Settle Delay */N unsigned char scsi$flx$b_motor_on; /* Motor on Delay */N unsigned char scsi$flx$b_motor8L_off; /* Motor off Delay */N __struct { /* SCSI FLEXIBLE PAGE Flags */N unsigned scsi$flx$v_reserved2 : 5; /* Reserved */N unsigned scsi$flx$v_mo : 1; /* Motor on */N unsigned scsi$flx$v_ssn : 1; /* Starting Sector Number */N unsigned scsi$flx$v_trdy : 1; /* True-Ready, media is accessable */N unsigned scsi$flx$v_spc : 4; /* Step pulse/cylind 9Ler */N unsigned scsi$flx$v_reserved3 : 4; /* Reserved */ } scsi$flx$r_flags;N unsigned char scsi$flx$b_write_comp; /* Write Compensation */N unsigned char scsi$flx$b_head_load; /* Head Load Delay */N unsigned char scsi$flx$b_head_unload; /* Head Unload delay */ __struct {N unsigned scsi$flx$v_pin2 : 1; /* Pin 2 of drive interface */N unsigned scsi$flx$v_pin34 : 1; :L /* Pin 34 of drive interface */N unsigned scsi$flx$v_pin1 : 1; /* Pin 1 of drive interface */N unsigned scsi$flx$v_pin4 : 1; /* Pin 4 of drive interface */( unsigned scsi$flx$v_fill_6_ : 4; } scsi$flx$r_pins;N unsigned short int scsi$flx$w_rotation; /* Medium Rotation Rate */N unsigned short int scsi$flx$w_reserved4; /* Reserved */ } ; #if !defined(__VAXC)L#define scsi$flx$v_page_code scsi$flx$ ;Lr_page_code_field.scsi$flx$v_page_code>#define scsi$flx$v_ps scsi$flx$r_page_code_field.scsi$flx$v_ps4#define scsi$flx$v_mo scsi$flx$r_flags.scsi$flx$v_mo6#define scsi$flx$v_ssn scsi$flx$r_flags.scsi$flx$v_ssn8#define scsi$flx$v_trdy scsi$flx$r_flags.scsi$flx$v_trdy6#define scsi$flx$v_spc scsi$flx$r_flags.scsi$flx$v_spc7#define scsi$flx$v_pin2 scsi$flx$r_pins.scsi$flx$v_pin29#define scsi$flx$v_pin34 scsi$flx$r_pins.scsi$flx$v_pin347#define scsi$flx$v_pin1 scsi$flx$r_pins.scsi$flx$v_pin17#d LSCSI$SUBQ$C_PLAY 1 /* Audio play operation in progress. */N#define SCSI$SUBQ$C_PAUSED 2 /* Audio play operation paused. */Z#define SCSI$SUBQ$C_COMPLETE 3 /* Audio play operation successfully completed. */X#define SCSI$SUBQ$C_ERROR 4 /* Audio play operation stopped due to error. */O#define SCSI$SUBQ$C_ACTIVE 5 /* No current audio status to return */#define SCSI$SUBQ$M_CONTROL 0xFN#define SCSI$SUBQ$C_PRE_EMPHASIS 0 /* Audio with ?Lpre-emphasis */N#define SCSI$SUBQ$C_COPY_PERMITTED 1 /* Digital copy permitted */N#define SCSI$SUBQ$C_DATA_TRACK 2 /* Data verses audio track */N#define SCSI$SUBQ$C_FOUR_CHANNEL 3 /* Four verses two channel audio */#define SCSI$SUBQ$M_ADR 0xF0N#define SCSI$SUBQ$C_UNKNOWN 0 /* mode information not supplied */c#define SCSI$SUBQ$C_CURRENT_POS 1 /* Current position data (track,index,abs-addr,rel-addr) */N#define SCSI$SUBQ$C_MCN 2 @L /* encodes media catalog number */N#define SCSI$SUBQ$C_ISRC 3 /* encodes ISRC */#define SCSI$SUBQ$M_MC_VAL 0x80N#define SCSI$SUBQ$C_MCN_LENGTH 32 /* Length of Subq MCN data */#define SCSI$SUBQ$M_TC_VAL 0x80 struct subq_channel {N char scsi$subq$b_reserved1; /* Reserved */N unsigned char scsi$subq$b_audio_status; /* Audio Status */N unsigned short int scsi$subq$w_dat ALa_length; /* Sub-channel Data Length */N unsigned char scsi$subq$b_format_code; /* Sub-channel data format code */ __struct {N unsigned scsi$subq$v_control : 4; /* Control */N unsigned scsi$subq$v_adr : 4; /* Audio Data Recorded Format */ } scsi$subq$r_field0;N unsigned char scsi$subq$b_track; /* Current Track number */N unsigned char scsi$subq$b_index; /* Current Index number */N unsigned i BLnt scsi$subq$l_abs_address; /* Absolute CD-ROM Address */N unsigned int scsi$subq$l_rel_address; /* Track Relative CD-ROM Address */ __struct {N unsigned scsi$subq$v_reserved2 : 7; /* Reserved */N unsigned scsi$subq$v_mc_val : 1; /* Media Catalog Valid bit */ } scsi$subq$r_field1;Q unsigned char scsi$subq$b_mcn [15]; /* Media Catalog Number (UPC/Bar Code) */ __struct {N unsigned scsi$subq$v_reserved3 : 7; /* R CLeserved */N unsigned scsi$subq$v_tc_val : 1; /* Track ISRC Valid */ } scsi$subq$r_field2;Z unsigned char scsi$subq$b_irrc [15]; /* Track International-Standard-Recording-Code */ } ; #if !defined(__VAXC)B#define scsi$subq$v_control scsi$subq$r_field0.scsi$subq$v_control:#define scsi$subq$v_adr scsi$subq$r_field0.scsi$subq$v_adr@#define scsi$subq$v_mc_val scsi$subq$r_field1.scsi$subq$v_mc_val@#define scsi$subq$v_tc_val scsi$subq$r_f DLield2.scsi$subq$v_tc_val"#endif /* #if !defined(__VAXC) */ N/* */N/* SCSIPATH structure used in sending IOGEN$_DEVPATH information to */N/* SYS$LOAD_DRIVER. Note that TARGET_ID and LUN fields may be assigned a */O/* -1 value so they cannot be unsigned. These two fields should also remain */N/* quadword aligned in this structure. */N/* EL */O#define SCSIPATH$K_VMS 1 /* VMS path identifiers (e.g. FC-LA) */S#define SCSIPATH$K_CONSOLE 2 /* Console path identifiers (e.g. AL-PA) */N#define SCSIPATH$K_QIOSERVER 3 /* QIOServer path identifier */N#define SCSIPATH$C_LENGTH 24 /* Length of the SCSIPATH structure */N#define SCSIPATH$K_LENGTH 24 /* Length of the SCSIPATH structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__c FLplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _scsipath {#pragma __nomember_alignmentN unsigned char scsipath$b_type; /* SCSIPATH type */N unsigned char scsipath$b_reserved1 [3]; /* reserved */N void *scsipath$ps_port_ucb; /* Pointer to port's UCB address */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If GLusing pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 scsipath$q_target_id; /* Target ID */N __int64 scsipath$q_lun; /* Logical Unit Number */ } SCSIPATH;N/* */N/* SCSI-3 Report Changeable Device Identifier command. */N/* HL */N#define DEVID_CMD$K_WR_DEVID_OPCODE 235 /* Write Changeable Device ID */N#define DEVID_CMD$K_RD_DEVID_OPCODE 236 /* Read Changeable Device ID */#define DEVID_CMD$K_LENGTH 10 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _devid_cmd {#pragma __nomember_alignmentN unsigned char devid_cmd$ ILb_opcode; /* Operation code */N unsigned char devid_cmd$b_reserved1 [6]; /* reserved */N unsigned char devid_cmd$b_alloc_length [2]; /* Allocation length */N unsigned char devid_cmd$b_control; /* Control byte */! char devid_cmd$b_fill_7_ [2]; } DEVID_CMD;N/* */N/* SCSI-3 Report Changeable Device Identifier data. */N JL/* */#define DEVID_HDR$K_LENGTH 4#define DEVID$K_LENGTH 255 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _devid {#pragma __nomember_alignmentN unsigned char devid$b_reserved1; /* reserved */N unsigned char devid$b_reserved2; KL /* reserved */ __struct {N unsigned devid$v_valid : 1; /* Identifier is valid */N unsigned devid$v_reserved3 : 7; /* reserved */ } devid$r_valid_field;N unsigned char devid$b_ident_len; /* No. of bytes following this one */N unsigned char devid$b_ident [251]; /* Device identifier */N char devid$b_fill1; /* For alignment */ } DEVID; LL #if !defined(__VAXC)7#define devid$v_valid devid$r_valid_field.devid$v_valid?#define devid$v_reserved3 devid$r_valid_field.devid$v_reserved3"#endif /* #if !defined(__VAXC) */ N/* */N/* SCSI-3 Report_LUNs command. */N/* */&#define RPTLUN_CMD$K_RPTLUN_OPCODE 160#define RPTLUN_CMD$K_LENGTH 12 c ML#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rptlun_cmd {#pragma __nomember_alignmentN unsigned char rptlun_cmd$b_opcode; /* Operation code */N unsigned char rptlun_cmd$b_reserved1 [5]; /* reserved */N unsigned char rptlun_cmd$b_alloc_length [4]; /* Allocation length */N unsigned chaNLr rptlun_cmd$b_reserved2; /* reserved */N unsigned char rptlun_cmd$b_control; /* Control byte */ } RPTLUN_CMD;N/* */O/* The next two structures hold SCSI-3 Report_LUNs return data. There is a */S/* quadword header, RPTLUN_DATAHDR, followed by n quadwords, each holding a LUN. */R/* Each LUN resides in a quadword LUNLIST_ENTRY structure. The number of these */N/* entires OL for an instance of Report_LUNs return data is specified by */N/* LIST_LENGTH. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _lunlist_entry {#pragma __nomember_alignmentN unsigned __int PL64 lunlist_entry$q_lun [1]; /* Entry in the LUN list */ } LUNLIST_ENTRY;#define RPTLUN_HDR$K_LENGTH 8 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rptlun_data {#pragma __nomember_alignmentN unsigned int rptlun_data$l_list_length; /* No. of LUNs * 8 bytes/LUN */N unsigned int rptlun_data$l_reserved1; /* reserved QL */N LUNLIST_ENTRY rptlun_data$r_lun_list; /* Start of the LUN list */ } RPTLUN_DATA;N/* */N/* Identification Descriptor contained in Inquiry Page 83 data - Device */N/* Identification Page. */N/* */N#define PG83_IDENT$K_RESERVED 0 /* 0:Reserved RL */N#define PG83_IDENT$K_BINARY 1 /* 1:Identifier is in binary */N#define PG83_IDENT$K_ASCII 2 /* 2:Identifier is in ASCII */N#define PG83_IDENT$K_FIBRECHANNEL 0 /* 0:Protocol - Fibre Channel */N#define PG83_IDENT$K_PARALLELSCSI 1 /* 1:Protocol - Parallel SCSI */N#define PG83_IDENT$K_SSA 2 /* 2:Protocol - SSA */N#define PG83_IDENT$K_IEEE1394 3 /* 3:Protocol - Firewire */V#definSLe PG83_IDENT$K_RDMA 4 /* 4:Protocol - Remote Direct Memory Access */N#define PG83_IDENT$K_ISCSI 5 /* 5:Protocol - Internet SCSI */O#define PG83_IDENT$K_SAS 6 /* 6:Protocol - Serial Attached SCSI */U#define PG83_IDENT$K_ADT 7 /* 7:Protocol - Automation/Drive Interface */O#define PG83_IDENT$K_ATAPI 8 /* 8:Protocol - ATA Packet Interface */N#define PG83_IDENT$K_VENDOR_SPEC 0 /* 0:Vendor-specific */N#define PG83TL_IDENT$K_VENDOR_ID 1 /* 1:Based on an 8-byte Vendor ID */N#define PG83_IDENT$K_IEEE_EUI64 2 /* 2:IEEE Extended Unique ID */N#define PG83_IDENT$K_FCPH_NAME_ID 3 /* 3:FC-PH Name ID */e#define PG83_IDENT$K_USER_SUPPLIED 4 /* 4:User-supplied Device ID (UDID) - Relative Target Port */N#define PG83_IDENT$K_TP_GROUP 5 /* 5:Target Port Group */N#define PG83_IDENT$K_LU_GROUP 6 /* 6:Logical Unit Group */N#define PG83_IULDENT$K_MD5_STRING 7 /* 7:MD5 Logical Unit Identifier */N#define PG83_IDENT$K_SCSI_NAME 8 /* 8:SCSI Name String */N#define PG83_IDENT$K_DEVICE_ASSOC 0 /* 0:Identifier assoc. with device */N#define PG83_IDENT$K_PORT_ASSOC 1 /* 1:Identifier assoc. with port */a#define PG83_IDENT$K_LUN_ASSOC 2 /* 2:Identifier assoc. contains addressed Logical unit */#define IDENT_HDR$K_LENGTH 4N#define FCPH$C_STD_ID 1 /* Standard IEEE format VL */N#define FCPH$C_EXT_ID 2 /* IEEE Extended format */N#define FCPH$C_REG_ID 5 /* IEEE Registered Name format */N#define FCPH$C_REGEXT_ID 6 /* IEEE Registered Extended format */ typedef struct _pg83_ident { __struct {R unsigned pg83_ident$v_codeset : 4; /* Identifier is in ASCII vs. binary */N unsigned pg83_ident$v_protocol_id : 4; /* Protocol Identifier */% } pg83_ident$r_codeset_field;WL __struct {N unsigned pg83_ident$v_id_type : 4; /* Identifier format */Y unsigned pg83_ident$v_assoc : 2; /* Entity with which IDENTIFIER is associated */N unsigned pg83_ident$v_reserved2 : 1; /* reserved */N unsigned pg83_ident$v_piv : 1; /* Protocol Identifier Value */$ } pg83_ident$r_idtype_field;N unsigned char pg83_ident$b_reserved3; /* reserved */O unsigned char pg83_ident$b_ident_lXLen; /* No. of bytes following this one */ __union {[ unsigned char pg83_ident$b_ident; /* Device identifier (255 - 8 bytes of header) */\ __struct { /* FCPH_ID applies only if ID_TYPE = FCPH_NAME_ID */l unsigned pg83_ident$v_unused : 4; /* Meaning depends on what type of FC-PH identifier this is */N unsigned pg83_ident$v_naa : 4; /* FC-PH Name Address Authority */# } pg83_ident$r_fcph_id;% } pg83_ident$r_ident_o YLverlay; } PG83_IDENT; #if !defined(__VAXC)L#define pg83_ident$v_codeset pg83_ident$r_codeset_field.pg83_ident$v_codesetT#define pg83_ident$v_protocol_id pg83_ident$r_codeset_field.pg83_ident$v_protocol_idK#define pg83_ident$v_id_type pg83_ident$r_idtype_field.pg83_ident$v_id_typeG#define pg83_ident$v_assoc pg83_ident$r_idtype_field.pg83_ident$v_assocO#define pg83_ident$v_reserved2 pg83_ident$r_idtype_field.pg83_ident$v_reserved2C#define pg83_ident$v_piv pg83_ident$r_idtype_field.p ZLg83_ident$v_pivH#define pg83_ident$b_ident pg83_ident$r_ident_overlay.pg83_ident$b_ident_#define pg83_ident$v_unused pg83_ident$r_ident_overlay.pg83_ident$r_fcph_id.pg83_ident$v_unusedY#define pg83_ident$v_naa pg83_ident$r_ident_overlay.pg83_ident$r_fcph_id.pg83_ident$v_naa"#endif /* #if !defined(__VAXC) */ N/* */Q/* Page 83 Inquiry data - Device Identification Page. Contains Identification */N/* Descriptor list s[Ltarting at offset 'IDENT_LIST'. */N/* */#define PAGE83_HDR$K_LENGTH 4#define PAGE83$K_LENGTH 255 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _page83 {#pragma __nomember_alignment __struct {N unsigned page83$v_device_typ\Le : 5; /* Peripheral device type */N unsigned page83$v_qualifier : 3; /* Peripheral qualifer */ } page83$r_peripheral;N unsigned char page83$b_page_code; /* Identifies page as Page 83 */N unsigned char page83$b_reserved1; /* reserved */N unsigned char page83$b_page_len; /* No. of bytes following this one */N unsigned char page83$b_ident_list [251]; /* Start of the Ident list. */N char page83$b_fill1; ]L /* For alignment */ } PAGE83; #if !defined(__VAXC)E#define page83$v_device_type page83$r_peripheral.page83$v_device_typeA#define page83$v_qualifier page83$r_peripheral.page83$v_qualifier"#endif /* #if !defined(__VAXC) */ N/* */N/* Page 00 Inquiry data - Supported VPD Page */N/* ^L */#define PAGE00_HDR$K_LENGTH 4#define PAGE00$K_LENGTH 80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _page00 {#pragma __nomember_alignment __struct {N unsigned page00$v_device_type : 5; /* Peripheral device type */N unsigned page00$v_qualifier : 3; /* Peripheral qualifer */ } pa _Lge00$r_peripheral;N unsigned char page00$b_page_code; /* Identifies page as Page 0 */N unsigned char page00$b_reserved1; /* reserved */N unsigned char page00$b_page_len; /* No. of bytes in page list */N unsigned char page00$b_supported_page [76]; /* List of up to 76 pages */ } PAGE00; #if !defined(__VAXC)E#define page00$v_device_type page00$r_peripheral.page00$v_device_typeA#define page00$v_qualifier page00$r_peripheral.page0 `L0$v_qualifier"#endif /* #if !defined(__VAXC) */ N/* */N/* Page 80 Inquiry data - Unit Serial Number Page. */N/* */#define PAGE80_HDR$K_LENGTH 4#define PAGE80$K_LENGTH 255 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword aL#else#pragma __nomember_alignment#endiftypedef struct _page80 {#pragma __nomember_alignment __struct {N unsigned page80$v_device_type : 5; /* Peripheral device type */N unsigned page80$v_qualifier : 3; /* Peripheral qualifer */ } page80$r_peripheral;N unsigned char page80$b_page_code; /* Identifies page as Page 80 */N unsigned char page80$b_reserved1; /* reserved */N unsigned char page80$b_page_le bLn; /* No. of bytes in serial number */a unsigned char page80$b_serial_no [251]; /* Product serial number (255 - 4 bytes of header) */N char page80$b_fill1; /* For alignment */ } PAGE80; #if !defined(__VAXC)E#define page80$v_device_type page80$r_peripheral.page80$v_device_typeA#define page80$v_qualifier page80$r_peripheral.page80$v_qualifier"#endif /* #if !defined(__VAXC) */ N/* cL */N/* SCSI Poll Thread Block used by IOGEN$SCSI_CONFIG */N/* */#define SPTB$K_LENGTH 299 struct sptbdef {N unsigned int sptb$l_size; /* actual size allocated */N unsigned int sptb$l_lkid; /* thread's SCSIPOLL lock id */O unsigned int sptb$l_channel; /* thread's channel to the SCSI port */Q int sptb$l_retries; dL /* number of retries left on this port */ __union {N __int64 sptb$q_iosb; /* IOSB for polling operation */ __struct {N unsigned short int sptb$w_status; /* completion status */N unsigned short int sptb$w_retlen; /* bytes read from port */! } sptb$r_iosb_fields; } sptb$r_iosb_overlay;O unsigned int sptb$l_scsi_id; /* current SCSI ID to poll in thread */N unsigned int sptb$l_lu eLn; /* current LUN to poll in thread */R void *sptb$ps_busarray; /* address of CRB's busarray entry list */N unsigned int sptb$l_handle; /* autoconfiguration handle */N unsigned int sptb$l_allocls; /* port allocation class */N char sptb$t_inquirybuf [255]; /* buffer for SCSI INQUIRY command */ } ; #if !defined(__VAXC)3#define sptb$q_iosb sptb$r_iosb_overlay.sptb$q_iosbJ#define sptb$w_status sptb$r_iosb_over fLlay.sptb$r_iosb_fields.sptb$w_statusJ#define sptb$w_retlen sptb$r_iosb_overlay.sptb$r_iosb_fields.sptb$w_retlen"#endif /* #if !defined(__VAXC) */ N/* */N/* SCSI-3 REPORT DENSITY command. */N/* */'#define RPTDENS_CMD$K_RPTDENS_OPCODE 68#define RPTDENS_CMD$K_LENGTH 10 c#if !defined(__NOBASEALIGN_SUPPO gLRT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rptdens_cmd {#pragma __nomember_alignmentN unsigned char rptdens_cmd$b_opcode; /* Operation code */N unsigned char rptdens_cmd$b_reserved1 [6]; /* reserved */N unsigned char rptdens_cmd$b_alloc_length [2]; /* Allocation length */N unsigned char rptdens_cmd$b_control; /* Co hLntrol byte */# char rptdens_cmd$b_fill_8_ [2]; } RPTDENS_CMD;N/* */Q/* The next two structures describe SCSI-3 tapes REPORT DENSITY return data. */N/* Each instance of the REPORT DENSITY command returns one RPTDENS_DATA */N/* structure. RPTDENS_DATA contains a quadword header, followed by */N/* n 52-byte entries, each holding a density support data block descriptor */N/* (one fo iLr each different density supported by the tape drive). */N/* The actual number of descriptors is specified by LIST_LENGTH_MSB/LSB. */N/* */!#define DENS_DESC$M_RESERVED1 0x1#define DENS_DESC$M_DEFLT 0x20#define DENS_DESC$M_DUP 0x40#define DENS_DESC$M_WRTOK 0x80N#define DENS_DESC$K_LENGTH 52 /* Length per descriptor */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) jL /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif!typedef struct _dens_descriptor {#pragma __nomember_alignment0 unsigned char dens_desc$b_primary_dens_code;2 unsigned char dens_desc$b_secondary_dens_code; __struct {i unsigned dens_desc$v_reserved1 : 5 /** WARNING: bitfield array has been reduced to a string **/ ;' unsigned dens_desc$v_deflt : 1;% unsigned dens_desc$v_dup : 1;' kL unsigned dens_desc$v_wrtok : 1; } dens_desc$r_flags;( unsigned char dens_desc$b_reserved2;( unsigned char dens_desc$b_reserved3;. unsigned char dens_desc$b_bits_per_mm [3];. unsigned char dens_desc$b_media_width [2];) unsigned char dens_desc$b_tracks [2];+ unsigned char dens_desc$b_capacity [4];0 unsigned char dens_desc$b_assigning_org [8];/ unsigned char dens_desc$b_density_name [8];/ unsigned char dens_desc$b_description [20]; } DENS_DESCR lLIPTOR; #if !defined(__VAXC)E#define dens_desc$v_reserved1 dens_desc$r_flags.dens_desc$v_reserved1=#define dens_desc$v_deflt dens_desc$r_flags.dens_desc$v_deflt9#define dens_desc$v_dup dens_desc$r_flags.dens_desc$v_dup=#define dens_desc$v_wrtok dens_desc$r_flags.dens_desc$v_wrtok"#endif /* #if !defined(__VAXC) */ #define RPTDENS_HDR$K_LENGTH 4 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __qua mLdword#else#pragma __nomember_alignment#endiftypedef struct _rptdens_data {#pragma __nomember_alignmentR unsigned char rptdens$b_list_length_msb; /* 2 + (# of desc * 52 bytes/desc) */R unsigned char rptdens$b_list_length_lsb; /* 2 + (# of desc * 52 bytes/desc) */N unsigned char rptdens$b_reserved1 [2]; /* Reserved */N DENS_DESCRIPTOR rptdens$r_first_desc; /* Start of the descriptor list */ } RPTDENS_DATA;N/* nL */N/* Page x0F -- Data Compression Page. */N/* */#define PAGE_0F$K_PAGE_CODE 15 #define PAGE_0F$K_PAGE_LENGTH 14#define PAGE_0F$M_DCC 0x40#define PAGE_0F$M_DCE 0x80#define PAGE_0F$M_RED 0x60#define PAGE_0F$M_DDE 0x80#define PAGE_0F$K_NOCOMP 0#define PAGE_0F$K_DEFAULT 1 #define PAGE_0F$K_IBM_ALDC_512 3!#define PAGE_0F$K_IBM_ALDC_1024 4!oL#define PAGE_0F$K_IBM_ALDC_2048 5#define PAGE_0F$K_IBM_IDRC 16#define PAGE_0F$K_DCLZ 32 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _datcomp_pg {#pragma __nomember_alignmentN __struct { /* Page code field */( unsigned page_0f$v_pagecode : 6;N unsigned page_0f$v_rsvd1 : pL 1; /* Reserved */R unsigned page_0f$v_ps : 1; /* Parameters savable (Mode sense only) */# } page_0f$r_pagecode_field;N unsigned char page_0f$b_page_len; /* No. of bytes following this one */ __struct {N unsigned page_0f$v_rsvd2 : 6; /* Reserved */N unsigned page_0f$v_dcc : 1; /* Data compression capable */N unsigned page_0f$v_dce : 1; /* Data compression enable */ qL } page_0f$r_flags; __struct {N unsigned page_0f$v_rsvd3 : 5; /* Reserved */O unsigned page_0f$v_red : 2; /* Report exception on decompression */N unsigned page_0f$v_dde : 1; /* Data decompression enable */ } page_0f$r_flags2;N __union { /* Compression algorithm */. unsigned int page_0f$l_comp_algorithm;/ unsigned char page_0f$b_comp_bytes [4];+ } rLpage_0f$r_comp_algorithm_overlay;N __union { /* Decompression algorithm */0 unsigned int page_0f$l_decomp_algorithm;1 unsigned char page_0f$b_decomp_bytes [4];- } page_0f$r_decomp_algorithm_overlay;& unsigned char page_0f$b_rsvd4 [4]; } DATCOMP_PG; #if !defined(__VAXC)F#define page_0f$v_pagecode page_0f$r_pagecode_field.page_0f$v_pagecode@#define page_0f$v_rsvd1 page_0f$r_pagecode_field.page_0f$v_rsvd1:#define page_0f$ sLv_ps page_0f$r_pagecode_field.page_0f$v_ps7#define page_0f$v_rsvd2 page_0f$r_flags.page_0f$v_rsvd23#define page_0f$v_dcc page_0f$r_flags.page_0f$v_dcc3#define page_0f$v_dce page_0f$r_flags.page_0f$v_dce8#define page_0f$v_rsvd3 page_0f$r_flags2.page_0f$v_rsvd34#define page_0f$v_red page_0f$r_flags2.page_0f$v_red4#define page_0f$v_dde page_0f$r_flags2.page_0f$v_ddeZ#define page_0f$l_comp_algorithm page_0f$r_comp_algorithm_overlay.page_0f$l_comp_algorithmR#define page_0f$b_comp_bytes page_0f$r tL_comp_algorithm_overlay.page_0f$b_comp_bytes`#define page_0f$l_decomp_algorithm page_0f$r_decomp_algorithm_overlay.page_0f$l_decomp_algorithmX#define page_0f$b_decomp_bytes page_0f$r_decomp_algorithm_overlay.page_0f$b_decomp_bytes"#endif /* #if !defined(__VAXC) */  N/* */I/* Reading wwiddef.sdi is necessary because the DEV_WWID_DUPLE */I/* structure contains an embedded WWID type. * uL/I/* */P/* It is assumed that wwiddef.sdi has already been created by the build. */N/* */ G #ifndef __NEW_STARLET /* If __NEW_STARLET not currently defined */G #define __NEW_STARLET /* Needed to define uppercase WWID typedef */N #define __NEW_STARLET_LOCALDEF /* __NEW_STARLET now locally defined */ #endifY #include vL /* Define WWID type; DEV_WWID_DUPLE contains an embedded WWID */Q #ifdef __NEW_STARLET_LOCALDEF /* If __NEW_STARLET was locally defined above */7 #undef __NEW_STARLET /* Restore original context */ #undef __NEW_STARLET_LOCALDEF #endifN/* */O/* DEV_WWID_DUPLE used in device naming of (initially) Fibre Channel tapes. */N/* */ c#if wL!defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _dev_wwid_duple {#pragma __nomember_alignmentN struct _dev_wwid_duple *dev_wwid_duple$ps_flink; /* Forward link */N struct _dev_wwid_duple *dev_wwid_duple$ps_blink; /* Backward link */N unsigned short int dev_wwid_duple$w_size; /* Size */N unsigned cha xLr dev_wwid_duple$b_type; /* Type */N unsigned char dev_wwid_duple$b_subtype; /* Subtype */N unsigned int dev_wwid_duple$l_flags; /* Flags (future use) */N char dev_wwid_duple$t_device [16]; /* Device name */N WWID dev_wwid_duple$r_wwid; /* WWID */ } DEV_WWID_DUPLE;##define DEV_WWID_DUPLE$K_LENGTH 312##define DEV_WWID_DUPLE$C_LENGTH 312 N/* yL */N/* PERSISTENT RESERVE OUT command. */N/* */ #define SCSI$K_PER_RES_SUPPORT 1##define PROUT_CMD$K_PROUT_OPCODE 95)#define PROUT_CMD$M_SERVICE_ACTION 0x1F00N#define PROUT_CMD$C_REGISTER 0 /* 00: Register */N#define PROUT_CMD$C_RESERVE 1 /* 01: Reserve */N#define zLPROUT_CMD$C_RELEASE 2 /* 02: Release */N#define PROUT_CMD$C_CLEAR 3 /* 03: Clear */N#define PROUT_CMD$C_PREEMPT 4 /* 04: Preempt */N#define PROUT_CMD$C_PREEMPT_ABORT 5 /* 05: Preempt & Abort */R#define PROUT_CMD$C_REGISTER_IGNORE 6 /* 06: Register and Ignore Existing Key */$#define PROUT_CMD$M_RESERVED1 0xE000 #define PROUT_CMD$M_TYPE 0xF0000N#define PROUT_CMD$C_OBSELETE1 0 {L /* 00: Obselete */N#define PROUT_CMD$C_WRITE_EX 1 /* 01: Write Exclusive */N#define PROUT_CMD$C_OBSELETE2 2 /* 02: Obselete */N#define PROUT_CMD$C_EXCLUSIVE 3 /* 03: Exclusive Access */N#define PROUT_CMD$C_OBSELETE3 4 /* 04: Obselete */R#define PROUT_CMD$C_WRITE_EX_RO 5 /* 05: Write Exclusive Registrants Only */N#define PROUT_CMD$C_EXCLUSIVE_RO 6 /* 06: Exclusive Reg |Listrants Only */"#define PROUT_CMD$M_SCOPE 0xF00000N#define PROUT_CMD$C_LOGICAL_UNIT 0 /* 00: Logical Unit */N#define PROUT_CMD$C_OBSELETE4 1 /* 01: Obselete */N#define PROUT_CMD$C_ELEMENT 2 /* 02: Element */N#define PROUT_CMD$K_PROUT_PLL 24 /* Fixed length of x18 */#define PROUT_CMD$K_LENGTH 10 typedef struct _prout_cmd {N unsigned char prout_cmd$b_opcode; /* Operation code }L */N unsigned prout_cmd$v_service_action : 5; /* Service Action field */N unsigned prout_cmd$v_reserved1 : 3; /* Reserved bits */N unsigned prout_cmd$v_type : 4; /* Reservation Type field */N unsigned prout_cmd$v_scope : 4; /* Scope field */N unsigned int prout_cmd$l_reserved2; /* Reserved */Q unsigned char prout_cmd$b_param_list_len_msb; /* Parameter List Length MSB */Q un ~Lsigned char prout_cmd$b_param_list_len_lsb; /* Parameter List Length LSB */N unsigned char prout_cmd$b_control; /* Control byte */ } PROUT_CMD;N/* */N/* PERSISTENT RESERVE OUT parameter list. */N/* */#define PROUT_PL$M_APTPL 0x0#define PROUT_PL$M_RESERVED 0x0#define PROUT_PL$K_LENGTH L24 typedef struct _prout_pl {N unsigned __int64 prout_pl$q_reservation_key; /* Reservation Key */N unsigned __int64 prout_pl$q_sa_reservation_key; /* Service action key */N unsigned int prout_pl$l_scope_address; /* Scope address */N unsigned prout_pl$v_aptpl : 1; /* APTPL bit */N unsigned prout_pl$v_reserved : 15; /* Reserved bits */N unsigned short int prout_pl$w_obselete; /* Obselete L */ } PROUT_PL;N/* */N/* PERSISTENT RESERVE IN command. */N/* */!#define PRIN_CMD$K_PRIN_OPCODE 94(#define PRIN_CMD$M_SERVICE_ACTION 0x1F00N#define PRIN_CMD$C_READ_KEYS 0 /* 00: Read Keys */N#define PRIN_CMD$C_READ_RESERVATION 1 /* 01: Read Reservation */# L#define PRIN_CMD$M_RESERVED1 0xE000#define PRIN_CMD$K_LENGTH 10 typedef struct _prin_cmd {N unsigned char prin_cmd$b_opcode; /* Operation code */N unsigned prin_cmd$v_service_action : 5; /* Service Action field */N unsigned prin_cmd$v_reserved1 : 3; /* Reserved bits */N unsigned int prin_cmd$l_reserved2; /* Reserved */N unsigned char prin_cmd$b_reserved3; /* Reserved */N un Lsigned short int prin_cmd$w_allocation_len; /* Allocation Length */N unsigned char prin_cmd$b_control; /* Control */ } PRIN_CMD;N/* */N/* PERSISTENT RESERVE IN keys parameter list. */N/* */#define PRIN_KEYS$K_LENGTH 16 typedef struct _prin_keys {N unsigned int prin_keys$l L_generation; /* Generation # */N unsigned int prin_keys$l_additional_len; /* Additional Length */N unsigned __int64 prin_keys$q_key; /* First Key */ } PRIN_KEYS;N/* */N/* PERSISTENT RESERVE IN reservations parameter list. */N/* */#define PRIN_RES$M_TYPE 0x0N#definLe PRIN_RES$C_OBSELETE1 0 /* 00: Obselete */N#define PRIN_RES$C_WRITE_EX 1 /* 01: Write Exclusive */N#define PRIN_RES$C_OBSELETE2 2 /* 02: Obselete */N#define PRIN_RES$C_EXCLUSIVE 3 /* 03: Exclusive Access */N#define PRIN_RES$C_OBSELETE3 4 /* 04: Obselete */R#define PRIN_RES$C_WRITE_EX_RO 5 /* 05: Write Exclusive Registrants Only */N#define PRIN_RES$C_EXCLUSIVE L_RO 6 /* 06: Exclusive Registrants Only */#define PRIN_RES$M_SCOPE 0x0N#define PRIN_RES$C_LOGICAL_UNIT 0 /* 00: Logical Unit */N#define PRIN_RES$C_OBSELETE4 1 /* 01: Obselete */N#define PRIN_RES$C_ELEMENT 2 /* 02: Element */#define PRIN_RES$K_LENGTH 24 typedef struct _prin_res {N unsigned int prin_res$l_generation; /* Generation # */N unsigned int prin_res$l_additional_lenL; /* Additional Length */N unsigned __int64 prin_res$q_key; /* First Key */N unsigned int prin_res$l_scope_address; /* Scope address */N unsigned char prin_res$b_reserved1; /* Reserved byte */N unsigned prin_res$v_type : 4; /* Reservation Type field */N unsigned prin_res$v_scope : 4; /* Scope field */N unsigned short int prin_res$w_obselete; /* Obselete word L */ } PRIN_RES;N/* */N/* 10-byte Read & Write CDBs have same format, differ only in opcode */N/* */ #define SCSI$K_READ_10_OPCODE 40!#define SCSI$K_WRITE_10_OPCODE 42#define RW_10_CMD$M_RELADR 0x1#define RW_10_CMD$M_FUA 0x8#define RW_10_CMD$M_DPO 0x10#define RW_10_CMD$M_LUN 0xE0#define RW_10_CMD$K_LENGTH 10 c#if !def Lined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rw_10_cmd {#pragma __nomember_alignmentN unsigned char rw_10_cmd$b_opcode; /* Operation code */ __union {( unsigned char rw_10_cmd$b_flags; __struct {N unsigned rw_10_cmd$v_reladr : 1; /* Relative addressing */N unsigned rw_L10_cmd$v_reserved1 : 2; /* Reserved bits MBZ */N unsigned rw_10_cmd$v_fua : 1; /* Force Unit Access */N unsigned rw_10_cmd$v_dpo : 1; /* Disable Page Out */N unsigned rw_10_cmd$v_lun : 3; /* Logical Unit Number */% } rw_10_cmd$r_flags_bits;$ } rw_10_cmd$r_flags_overlay;N unsigned int rw_10_cmd$l_lba; /* Logical Block Address */N unsigned char rw_10_cmd$b_reserved2; /* Reserved L byte MBZ */N unsigned short int rw_10_cmd$w_blkcnt; /* Block count */N unsigned char rw_10_cmd$b_control; /* Control byte */! char rw_10_cmd$b_fill_9_ [2]; } RW_10_CMD; #if !defined(__VAXC)E#define rw_10_cmd$b_flags rw_10_cmd$r_flags_overlay.rw_10_cmd$b_flags^#define rw_10_cmd$v_reladr rw_10_cmd$r_flags_overlay.rw_10_cmd$r_flags_bits.rw_10_cmd$v_reladrX#define rw_10_cmd$v_fua rw_10_cmd$r_flags_overlay.rw_10_cmd$r_flags_bi Lts.rw_10_cmd$v_fuaX#define rw_10_cmd$v_dpo rw_10_cmd$r_flags_overlay.rw_10_cmd$r_flags_bits.rw_10_cmd$v_dpoX#define rw_10_cmd$v_lun rw_10_cmd$r_flags_overlay.rw_10_cmd$r_flags_bits.rw_10_cmd$v_lun"#endif /* #if !defined(__VAXC) */ N/* */N/* 16-byte Read & Write CDBs have same format, differ only in opcode */N/* Note: This structure conforms to SBC-4. */N/* L */!#define SCSI$K_READ_16_OPCODE 136"#define SCSI$K_WRITE_16_OPCODE 138#define RW_16_CMD$M_DLD2 0x1#define RW_16_CMD$M_RARC 0x4#define RW_16_CMD$M_FUA 0x8#define RW_16_CMD$M_DPO 0x10##define RW_16_CMD$M_RW_PROTECT 0xE0"#define RW_16_CMD$M_GROUP_NUM 0x3F#define RW_16_CMD$M_DLD0 0x40#define RW_16_CMD$M_DLD1 0x80#define RW_16_CMD$K_LENGTH 16 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC VL4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rw_16_cmd {#pragma __nomember_alignmentN unsigned char rw_16_cmd$b_opcode; /* Operation code */ __union {( unsigned char rw_16_cmd$b_flags; __struct {N unsigned rw_16_cmd$v_dld2 : 1; /* Duration Limit Desc-2 */N unsigned rw_16_cmd$v_reserved1 : 1; /* Reserved bits MBZ */P unsigned rLw_16_cmd$v_rarc : 1; /* Rebuild Assist Recovery Control */N unsigned rw_16_cmd$v_fua : 1; /* Force Unit Access */N unsigned rw_16_cmd$v_dpo : 1; /* Disable Page Out */N unsigned rw_16_cmd$v_rw_protect : 3; /* R/W protect */% } rw_16_cmd$r_flags_bits;$ } rw_16_cmd$r_flags_overlay;N unsigned __int64 rw_16_cmd$q_lba; /* Logical Block Address */N unsigned int rw_16_cmd$l_blkcnt; /* Block L count */ __union {/ unsigned char rw_16_cmd$b_group_number; __struct {N unsigned rw_16_cmd$v_group_num : 6; /* Group Number */N unsigned rw_16_cmd$v_dld0 : 1; /* Duration Limit Desc-0 */N unsigned rw_16_cmd$v_dld1 : 1; /* Duration Limit Desc-1 */) } rw_16_cmd$r_group_num_bits;( } rw_16_cmd$r_group_num_overlay;N unsigned char rw_16_cmd$b_control; /* Control byte L */ } RW_16_CMD; #if !defined(__VAXC)E#define rw_16_cmd$b_flags rw_16_cmd$r_flags_overlay.rw_16_cmd$b_flagsZ#define rw_16_cmd$v_dld2 rw_16_cmd$r_flags_overlay.rw_16_cmd$r_flags_bits.rw_16_cmd$v_dld2Z#define rw_16_cmd$v_rarc rw_16_cmd$r_flags_overlay.rw_16_cmd$r_flags_bits.rw_16_cmd$v_rarcX#define rw_16_cmd$v_fua rw_16_cmd$r_flags_overlay.rw_16_cmd$r_flags_bits.rw_16_cmd$v_fuaX#define rw_16_cmd$v_dpo rw_16_cmd$r_flags_overlay.rw_16_cmd$r_flags_bits.rw_16_cmd$v_dpof#definLe rw_16_cmd$v_rw_protect rw_16_cmd$r_flags_overlay.rw_16_cmd$r_flags_bits.rw_16_cmd$v_rw_protectW#define rw_16_cmd$b_group_number rw_16_cmd$r_group_num_overlay.rw_16_cmd$b_group_numberl#define rw_16_cmd$v_group_num rw_16_cmd$r_group_num_overlay.rw_16_cmd$r_group_num_bits.rw_16_cmd$v_group_numb#define rw_16_cmd$v_dld0 rw_16_cmd$r_group_num_overlay.rw_16_cmd$r_group_num_bits.rw_16_cmd$v_dld0b#define rw_16_cmd$v_dld1 rw_16_cmd$r_group_num_overlay.rw_16_cmd$r_group_num_bits.rw_16_cmd$v_dld1"#endif L/* #if !defined(__VAXC) */ N/* */N/* MAINTENANCE IN/OUT command. */N/* */!#define MAINT_CMD$K_IN_OPCODE 163"#define MAINT_CMD$K_OUT_OPCODE 164)#define MAINT_CMD$M_SERVICE_ACTION 0x1F00U#define MAINT_CMD$C_RPT_P_EXTENT 0 /* 00: Report assigned/unassigned P_EXTENT */N#define MAINT_CMD$C_RPT_CMPNT L1 /* 01: Report Component Device */U#define MAINT_CMD$C_RPT_CMPNT_ATT 2 /* 02: Report Component Device attachments */N#define MAINT_CMD$C_RPT_PRPHRL 3 /* 03: Report Peripheral Device */W#define MAINT_CMD$C_RPT_PRPHRL_ASS 4 /* 04: Report Peripheral Device Associations */a#define MAINT_CMD$C_RPT_PERCMP_ID 5 /* 05: Report Peripheral Device / Component Identifier */N#define MAINT_CMD$C_RPT_STATES 6 /* 06: Report States */N#define MAINT_CMD$LC_RPT_DEV_ID 7 /* 07: Report Device Identification */N#define MAINT_CMD$C_RPT_UNCFG_CAP 8 /* 08: Report Unconfigured Capacity */W#define MAINT_CMD$C_RPT_SUPPORT_CFG 9 /* 09: Report Supported Configuration Method */N#define MAINT_CMD$C_RPT_TGT_PORT_GRPS 10 /* 0A: Report Target Port Groups */N/* Service Actions for MAINTENANCE OUT */S#define MAINT_CMD$C_ADD_PERCMP 0 /* 00: Add Peripheral / Component Device */N#define MAINT_CMD$C_ATT_CMPNLT 1 /* 01: Attach to Component Device */N#define MAINT_CMD$C_EXG_P_EXTENT 2 /* 02: Exchange P_EXTENT */X#define MAINT_CMD$C_EXG_PERCMP 3 /* 03: Exchange Peripheral / Component Device */N#define MAINT_CMD$C_INSTRT_CMPNT 4 /* 04: Instruct Component Device */]#define MAINT_CMD$C_REM_PERCMP 5 /* 05: Remove Peripheral Device / Component Device */U#define MAINT_CMD$C_SET_PERCMP_ID 6 /* 06: Set Peripheral Component Identifier */S#define MAINT_CMD$C_ LBRK_PERCMP 7 /* 07: Break Peripheral Component Device */N#define MAINT_CMD$C_RESERVE8 8 /* 08: Restricted */N#define MAINT_CMD$C_RESERVE9 9 /* 09: Restricted */N#define MAINT_CMD$C_SET_TGT_PORT_GRPS 10 /* 0A: Set Target Port Groups */$#define MAINT_CMD$M_RESERVED1 0xE000&#define MAINT_CMD$M_LUN_TYPE 0xF000000(#define MAINT_CMD$M_RESERVED2 0xF0000000"#define MAINT_CMD$M_SELECT_RPT 0x3O#define MAINT_CMD$SR$C_RPT_ALL 0 /* 0 L0: Report All Peripheral Devices */N#define MAINT_CMD$SR$C_RPT_LUN 1 /* 01: Report only specified */Q#define MAINT_CMD$SR$C_RPT_ALL_UNAVAIL 2 /* 02: Report All Unavailable Devices */#define MAINT_CMD$M_ASSIGN 0x4#define MAINT_CMD$M_RPTMBUS 0x8##define MAINT_CMD$M_RPT_STATES 0x30P#define MAINT_CMD$RS$C_RPT_ALL 0 /* 00: Report All states for all LUNS */Z#define MAINT_CMD$RS$C_RPT_LUN_TYPE 1 /* 01: Report All states for specified LUN TYPE */U#define MAINT_CMD$RS$C_RPT L_LUN 2 /* 02: Report All stated for specified LUN */#define MAINT_CMD$M_SETLUN 0x40"#define MAINT_CMD$M_RESERVED4 0x80#define MAINT_CMD$M_RPTSEL 0x1#define MAINT_CMD$M_PORC 0x2"#define MAINT_CMD$M_RESERVED5 0xFC#define MAINT_CMD$M_IMMED 0x1"#define MAINT_CMD$M_RESERVED6 0xFE#define MAINT_CMD$K_LENGTH 12 typedef struct _maint_cmd {N unsigned char maint_cmd$b_opcode; /* Operation code */N unsigned maint_cmd$v_service_action : 5; /* Service Action L field */N/* Service Actions for MAINTENANCE IN */N unsigned maint_cmd$v_reserved1 : 3; /* Reserved bits */ __union {N unsigned char maint_cmd$b_device_type; /* Device Type */Q unsigned char maint_cmd$b_cmpnt_instr; /* Component Device Instruction */! } maint_cmd$r_b2_overlay;N unsigned maint_cmd$v_lun_type : 4; /* LUN Type field */N unsigned maint_cmd$v_reserve Ld2 : 4; /* Reserved bits */ __union {+ unsigned short int maint_cmd$w_lun; __struct {N unsigned char maint_cmd$b_lun_msb; /* Logical Unit Number MSB */N unsigned char maint_cmd$b_lun_lsb; /* Logical Unit Number LSB */$ } maint_cmd$r_lun_bytes;" } maint_cmd$r_lun_overlay; __union {Z unsigned char maint_cmd$b_alloc_length [4]; /* Allocation/Parameter list length */ __struct {5 L unsigned short int maint_cmd$w_reserved3; __union {7 unsigned short int maint_cmd$w_new_lun; __struct {\ unsigned char maint_cmd$b_new_lun_msb; /* New Logical Unit Number MSB */\ unsigned char maint_cmd$b_new_lun_lsb; /* New Logical Unit Number LSB */0 } maint_cmd$r_new_lun_bytes;. } maint_cmd$r_new_lun_overlay;% } maint_cmd$r_new_lun_st;$ } maint_cmd$r_ Lparam_overlay; __union {N unsigned char maint_cmd$b_cmd_flags; /* Command specific flags */ __struct {N unsigned maint_cmd$v_select_rpt : 2; /* Select report code */P unsigned maint_cmd$v_assign : 1; /* Report Assigned p_extents bit */N unsigned maint_cmd$v_rptmbus : 1; /* Report Multiple Bus bit */N unsigned maint_cmd$v_rpt_states : 2; /* Report States */N unsigned maint_cmd$v_setlun : 1; /* SE LTLUN bit *// unsigned maint_cmd$v_reserved4 : 1;$ } maint_cmd$r_cmd_bits1; __struct {N unsigned maint_cmd$v_rptsel : 1; /* Report Select bit */N unsigned maint_cmd$v_porc : 1; /* Peripheral or Component bit *// unsigned maint_cmd$v_reserved5 : 6;$ } maint_cmd$r_cmd_bits2; __struct {N unsigned maint_cmd$v_immed : 1; /* Immediate bit *// unsi Lgned maint_cmd$v_reserved6 : 7;$ } maint_cmd$r_cmd_bits3;( } maint_cmd$r_cmd_flags_overlay;N unsigned char maint_cmd$b_control; /* Control byte */ } MAINT_CMD; #if !defined(__VAXC)N#define maint_cmd$b_device_type maint_cmd$r_b2_overlay.maint_cmd$b_device_typeN#define maint_cmd$b_cmpnt_instr maint_cmd$r_b2_overlay.maint_cmd$b_cmpnt_instr?#define maint_cmd$w_lun maint_cmd$r_lun_overlay.maint_cmd$w_lunK#define maint_cmd$r_lun_bytes maint_cmd$r_Llun_overlay.maint_cmd$r_lun_bytesE#define maint_cmd$b_lun_msb maint_cmd$r_lun_bytes.maint_cmd$b_lun_msbE#define maint_cmd$b_lun_lsb maint_cmd$r_lun_bytes.maint_cmd$b_lun_lsbS#define maint_cmd$b_alloc_length maint_cmd$r_param_overlay.maint_cmd$b_alloc_lengthO#define maint_cmd$r_new_lun_st maint_cmd$r_param_overlay.maint_cmd$r_new_lun_stV#define maint_cmd$r_new_lun_overlay maint_cmd$r_new_lun_st.maint_cmd$r_new_lun_overlayK#define maint_cmd$w_new_lun maint_cmd$r_new_lun_overlay.maint_cmd$w_neLw_lunW#define maint_cmd$r_new_lun_bytes maint_cmd$r_new_lun_overlay.maint_cmd$r_new_lun_bytesQ#define maint_cmd$b_new_lun_msb maint_cmd$r_new_lun_bytes.maint_cmd$b_new_lun_msbQ#define maint_cmd$b_new_lun_lsb maint_cmd$r_new_lun_bytes.maint_cmd$b_new_lun_lsbQ#define maint_cmd$b_cmd_flags maint_cmd$r_cmd_flags_overlay.maint_cmd$b_cmd_flagsQ#define maint_cmd$r_cmd_bits1 maint_cmd$r_cmd_flags_overlay.maint_cmd$r_cmd_bits1K#define maint_cmd$v_select_rpt maint_cmd$r_cmd_bits1.maint_cmd$v_select_LrptC#define maint_cmd$v_assign maint_cmd$r_cmd_bits1.maint_cmd$v_assignE#define maint_cmd$v_rptmbus maint_cmd$r_cmd_bits1.maint_cmd$v_rptmbusK#define maint_cmd$v_rpt_states maint_cmd$r_cmd_bits1.maint_cmd$v_rpt_statesC#define maint_cmd$v_setlun maint_cmd$r_cmd_bits1.maint_cmd$v_setlunQ#define maint_cmd$r_cmd_bits2 maint_cmd$r_cmd_flags_overlay.maint_cmd$r_cmd_bits2C#define maint_cmd$v_rptsel maint_cmd$r_cmd_bits2.maint_cmd$v_rptsel?#define maint_cmd$v_porc maint_cmd$r_cmd_bits2.maint_cmdL$v_porcQ#define maint_cmd$r_cmd_bits3 maint_cmd$r_cmd_flags_overlay.maint_cmd$r_cmd_bits3A#define maint_cmd$v_immed maint_cmd$r_cmd_bits3.maint_cmd$v_immed"#endif /* #if !defined(__VAXC) */ N/* p_extent descriptor */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _p_extent {#p Lragma __nomember_alignment __union { __struct {N unsigned char scsi$pxt$b_lun_msb; /* Logical Unit Number MSB */N unsigned char scsi$pxt$b_lun_lsb; /* Logical Unit Number LSB */# } scsi$pxt$r_lun_bytes;* unsigned short int scsi$pxt$w_lun;! } scsi$pxt$r_lun_overlay;W unsigned int scsi$pxt$l_start_lba_p; /* First Addressable Block of the p_extent. */P unsigned int scsi$pxt$l_number_lba_p; /* Number of blocks in the p_e Lxtent */R unsigned short int scsi$pxt$w_bytes_lba_p; /* Number of bytes in each block */ } P_EXTENT; #if !defined(__VAXC)H#define scsi$pxt$r_lun_bytes scsi$pxt$r_lun_overlay.scsi$pxt$r_lun_bytesB#define scsi$pxt$b_lun_msb scsi$pxt$r_lun_bytes.scsi$pxt$b_lun_msbB#define scsi$pxt$b_lun_lsb scsi$pxt$r_lun_bytes.scsi$pxt$b_lun_lsb<#define scsi$pxt$w_lun scsi$pxt$r_lun_overlay.scsi$pxt$w_lun"#endif /* #if !defined(__VAXC) */ N/* Assign / Deassign p_extent Descriptor L */#define SCSI$APXT$M_STATE 0x7F_#define SCSI$APXT$C_AVAILABLE 0 /* 00: The accessed device / p_extent is operational */^#define SCSI$APXT$C_BROKEN 1 /* 01: Is capable of being supported but has failed */a#define SCSI$APXT$C_NOT_AVAIL 2 /* 02: Is capable of being supported but not connected */d#define SCSI$APXT$C_NOT_SUPPORT 3 /* 03: Target can not support addressed device / p_extent */i#define SCSI$APXT$C_PRESENT 4 /* 04: Device L/ p_extent is present, no other status available */o#define SCSI$APXT$C_READYING 5 /* 05: The device / p_extent is being initialized, access is limited */X#define SCSI$APXT$C_REBUILD 6 /* 06: The device / p_extent is being rebuilt */"#define SCSI$APXT$M_RESERVED3 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif typedef struct _asLsgn_p_extent {#pragma __nomember_alignmentN P_EXTENT scsi$apxt$r_extent; /* P_EXTENT structure */( unsigned char scsi$apxt$b_reserved1;( unsigned char scsi$apxt$b_reserved2;N unsigned char scsi$apxt$b_dev_type; /* Peripheral Device Type */ __struct {' unsigned scsi$apxt$v_state : 7;+ unsigned scsi$apxt$v_reserved3 : 1;" } scsi$apxt$r_p_ext_state; } ASSGN_P_EXTENT; #if !defined(__VAXC)C#define scsi$apxt$v_stat Le scsi$apxt$r_p_ext_state.scsi$apxt$v_state"#endif /* #if !defined(__VAXC) */ N/* Component and Peripheral Device Descriptors */\#define SCSI$DEV$C_SACL 0 /* 00: Controller electronics that contain a SACL */N#define SCSI$DEV$C_NON_VOL_CACHE 1 /* 01: Non-volatile cache */N#define SCSI$DEV$C_POWER 2 /* 02: Power supply */N#define SCSI$DEV$C_UPS 3 /* 03: Uninterruptable power supply */N#definLe SCSI$DEV$C_DISPLAY 4 /* 04: Display */N#define SCSI$DEV$C_KEY_PAD 5 /* 05: Key pad entry */N#define SCSI$DEV$C_FAN 6 /* 06: Fan */!#define SCSI$DEV$M_DEV_STATE 0x7FT#define SCSI$SPARE$C_AVAILABLE 0 /* 00: The addressed spare is operational */W#define SCSI$SPARE$C_BROKEN 1 /* 01: The spare is supported but has failed */[#define SCSI$SPARE$C_NOT_AVAIL 2 /* 02: The spare is Lsupported but not configured */[#define SCSI$SPARE$C_NOT_SUPPORT 3 /* 03: The spare is not capable of configuration */]#define SCSI$SPARE$C_PRESENT 4 /* 04: The spare is present, no other status known */c#define SCSI$SPARE$C_SPARE_USED 5 /* 05: The spare has been exchanged with a failed object */_#define SCSI$DEV$C_AVAILABLE 0 /* 00: The addressed component device is operational */X#define SCSI$DEV$C_BROKEN 1 /* 01: The device is supported but has faiLled */h#define SCSI$DEV$C_ITTU 3 /* 03: The addressed device is the reporting component device */c#define SCSI$DEV$C_NOT_AVAIL 4 /* 04: The component device is supported but not present */e#define SCSI$DEV$C_NOT_SUPPORT 5 /* 05: Target can not support a component at given address */h#define SCSI$DEV$C_PRESENT 6 /* 06: The component device is present, no other status known */n#define SCSI$DEV$C_READYING 7 /* 07: The component device is being iniLtialized, access is limited */#define SCSI$DEV$M_REPLACE 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _dev_desc {#pragma __nomember_alignment& unsigned char scsi$dev$b_dev_type; __struct {* unsigned scsi$dev$v_dev_state : 7;( unsigned scsi$dev$v_replace : 1; } scsi$dev$r_dev_status; __unio Ln { __struct {N unsigned char scsi$dev$b_lun_msb; /* Logical Unit Number MSB */N unsigned char scsi$dev$b_lun_lsb; /* Logical Unit Number LSB */# } scsi$dev$r_lun_bytes;* unsigned short int scsi$dev$w_lun;! } scsi$dev$r_lun_overlay; } DEV_DESC; #if !defined(__VAXC)G#define scsi$dev$v_dev_state scsi$dev$r_dev_status.scsi$dev$v_dev_stateC#define scsi$dev$v_replace scsi$dev$r_dev_status.scsi$dev$v_replaceH#define scsi L$dev$r_lun_bytes scsi$dev$r_lun_overlay.scsi$dev$r_lun_bytesB#define scsi$dev$b_lun_msb scsi$dev$r_lun_bytes.scsi$dev$b_lun_msbB#define scsi$dev$b_lun_lsb scsi$dev$r_lun_bytes.scsi$dev$b_lun_lsb<#define scsi$dev$w_lun scsi$dev$r_lun_overlay.scsi$dev$w_lun"#endif /* #if !defined(__VAXC) */ #define SCSI$CMPT$M_DEV_TYPE 0xF"#define SCSI$CMPT$M_RESERVED2 0xF0N#define SCSI$CMPT$C_PHYS_LUN 0 /* 00: Physical Logical Unit */N#define SCSI$CMPT$C_VOL_SET 1 /* 01: Volume seLt */N/* 02: Reserved */N/* 03: Reserved */[#define SCSI$CMPT$C_CMPT_LUN 4 /* 04: Component logical unit (component device) */N#define SCSI$CMPT$C_REDUND_GRP 5 /* 05: Redundancy Group */N#define SCSI$CMPT$C_SPARE 6 /* 06: Spare */N#define SCSI$CMPT$C_LUN_Z 7 /* 07: LUN_Z L */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _lun_desc {#pragma __nomember_alignment( unsigned char scsi$cmpt$b_reserved1; __struct {* unsigned scsi$cmpt$v_dev_type : 4;+ unsigned scsi$cmpt$v_reserved2 : 4; } scsi$cmpt$r_dtype; __union { __struct {N unsigned cha Lr scsi$cmpt$b_lun_msb; /* Logical Unit Number MSB */N unsigned char scsi$cmpt$b_lun_lsb; /* Logical Unit Number LSB */$ } scsi$cmpt$r_lun_bytes;+ unsigned short int scsi$cmpt$w_lun;" } scsi$cmpt$r_lun_overlay; } LUN_DESC; #if !defined(__VAXC)C#define scsi$cmpt$v_dev_type scsi$cmpt$r_dtype.scsi$cmpt$v_dev_typeK#define scsi$cmpt$r_lun_bytes scsi$cmpt$r_lun_overlay.scsi$cmpt$r_lun_bytesE#define scsi$cmpt$b_lun_msb scsi$cmpt$r_lun_bytes.scsi$cmpLt$b_lun_msbE#define scsi$cmpt$b_lun_lsb scsi$cmpt$r_lun_bytes.scsi$cmpt$b_lun_lsb?#define scsi$cmpt$w_lun scsi$cmpt$r_lun_overlay.scsi$cmpt$w_lun"#endif /* #if !defined(__VAXC) */ #define SCSI$LUNZ$M_READYING 0x1 #define SCSI$LUNZ$M_NONAFAIL 0x2 #define SCSI$LUNZ$M_ABNORMAL 0x4"#define SCSI$LUNZ$M_RESERVED1 0x38#define SCSI$LUNZ$M_VS 0x40"#define SCSI$LUNZ$M_RESERVED2 0x80 typedef struct _lun_z_states {P unsigned scsi$lunz$v_readying : 1; /* At least one LUN is still ready Ling */N unsigned scsi$lunz$v_nonafail : 1; /* Non Addressable part has failed */U unsigned scsi$lunz$v_abnormal : 1; /* One or more target units is unavailable */' unsigned scsi$lunz$v_reserved1 : 3;N unsigned scsi$lunz$v_vs : 1; /* Vendor Specific */' unsigned scsi$lunz$v_reserved2 : 1; } LUN_Z_STATES;N/* */N/* Report Supported Configuration Method parameter list L */N/* */N#define SCSI$RSCM$C_NOSUPPORT 0 /* 00: Target does not support */U#define SCSI$RSCM$C_MIN_RPT 1 /* 01: Mandatory reporting service actions */W#define SCSI$RSCM$C_SUPPORT 3 /* 03: Mandatory reporting and configuration */#define SCSI$RSCM$M_SIMPLE 0x3!#define SCSI$RSCM$M_RESERVED1 0xC#define SCSI$RSCM$M_BASIC 0x30"#define SCSI$RSCM$M_RESERVED2 0xC0!#define SCSI$RSC LM$M_GENERAL 0x300$#define SCSI$RSCM$M_RESERVED3 0xFC00 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif#typedef struct _rpt_config_method {#pragma __nomember_alignmentN unsigned scsi$rscm$v_simple : 2; /* Simple Configuration Method */' unsigned scsi$rscm$v_reserved1 : 2;N unsigned scsi$rscm$v_basic : 2; /* Basic Configuration L */' unsigned scsi$rscm$v_reserved2 : 2;% unsigned scsi$rscm$v_general : 2;' unsigned scsi$rscm$v_reserved3 : 6;( unsigned char scsi$rscm$b_reserved4;( unsigned char scsi$rscm$b_reserved5; } RPT_CONFIG_METHOD;N/* */N/* Report Unconfigured Capacity parameter list */N/* */#define SCSI$RUCL$M_MOREP 0x1#define SCSI$RUC$M_MOREPS 0x2!#define SCSI$RUC$M_RESERVED1 0xFC c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rpt_uncfg_cap {#pragma __nomember_alignmentN unsigned int scsi$ruc$l_p_extent_cap; /* Unassigned P_EXTENT Capacity */N unsigned int scsi$ruc$l_ps_extent_cap; /* Unassigned PS_EXTENT Capacity */ __ Lstruct {^ unsigned scsi$ruc$v_morep : 1; /* Can not configure all p_extents in single volume */_ unsigned scsi$ruc$v_moreps : 1; /* Can not configure all ps_extents in single volume */* unsigned scsi$ruc$v_reserved1 : 6; } scsi$ruc$r_flags;' unsigned char scsi$ruc$b_reserved2;N unsigned short int scsi$ruc$w_blocksize; /* Bytes per block */ } RPT_UNCFG_CAP; #if !defined(__VAXC):#define scsi$ruc$v_morep scsi$ruc$r_flags.scsi$ruc$v_mor Lep<#define scsi$ruc$v_moreps scsi$ruc$r_flags.scsi$ruc$v_moreps"#endif /* #if !defined(__VAXC) */ N/* */N/* Volume set states */N/* */Y#define SCSI$VSS$C_AVAILABLE 0 /* 00: The addressed volume set is operational */T#define SCSI$VSS$C_BROKEN 1 /* 01: The addressed volume Lset is broken */W#define SCSI$VSS$C_DATA_LOST 2 /* 02: User data has been lost in volume set */V#define SCSI$VSS$C_EXPOSED 3 /* 03: User data is valid but not protected */e#define SCSI$VSS$C_PART_EXPOSED 4 /* 04: One or more units have failed, data still protected */p#define SCSI$VSS$C_PROT_REBUILD 5 /* 05: One or more Redundancy Units are being rebuilt, data protected */i#define SCSI$VSS$C_NOT_AVAIL 6 /* 06: The volume set is capable of support but not Lconfigured */c#define SCSI$VSS$C_NOT_SUPPORT 7 /* 07: The volume set is not capable of being configured */U#define SCSI$VSS$C_READYING 8 /* 08: The volume set is being initialized */t#define SCSI$VSS$C_REBUILD 9 /* 09: One or more Redundancy Units are being rebuilt, data not protected */W#define SCSI$VSS$C_RECALC 10 /* 0A: The volume set is doing a recalculate */b#define SCSI$VSS$C_SPARE_USED 11 /* 0B: The Spare is in use for the addressed Volume Lset */R#define SCSI$VSS$C_PROT_DISABLED 12 /* 0C: Protection of User Data disabled */Z#define SCSI$VSS$C_VERIFY 13 /* 0D: The addressed data set is doing a VERIFY */X#define SCSI$VSS$C_FRACT_EXPOSED 14 /* 0E: Part of the user data is not protected */n#define SCSI$VSS$C_DYN_RECONFIG 15 /* 0F: The address volume set is being reconfigured, data protected */N/* */N/* Redundancy group states L */N/* */^#define SCSI$RGS$C_AVAILABLE 0 /* 00: The addressed redundancy group is configured */X#define SCSI$RGS$C_EXPOSED 1 /* 01: User data is intact, but not protected */N#define SCSI$RGS$C_INV_PROT_SPACE 2 /* 02: User data has been lost */a#define SCSI$RGS$C_NOT_AVAIL 3 /* 03: Group can be supported, has not been configured */Z#define SCSI$RGS$C_NLOT_SUPPORT 4 /* 04: Group is not capable of being configured */e#define SCSI$RGS$C_PART_EXPOSED 5 /* 05: One or more units have failed, data still protected */\#define SCSI$RGS$C_PRESENT 6 /* 06: The group is present, other status unknown */\#define SCSI$RGS$C_PROT_REBUILD 7 /* 07: The group is being rebuilt, data protected */c#define SCSI$RGS$C_REBUILD 8 /* 08: The group is being rebuilt, data is not protected */p#define SCSI$RGS$C_RECALC 9 L/* 09: The redundancy group is in the process of recalulate operation */U#define SCSI$RGS$C_PROT_DISABLED 10 /* 0A: Protection of User Data is disabled */Y#define SCSI$RGS$C_VERIFY 11 /* 0B: The redundancy group is doing a verify. */l#define SCSI$RGS$C_DYN_RECONFIG 12 /* 0C: The redundancy group is being reconfigured, data protected */N/* */N/* Component Device Instruction field L */N/* */T#define SCSI$CDI$C_DEVICE_OFF 0 /* 00: Turn selected component device off */S#define SCSI$CDI$C_DEVICE_ON 1 /* 01: Turn selected component device on */N/* */N/* Target port descriptor format, as defined by SPC-3. */N/* L*/N/* Note: This structure is used to define data returned by the REPORT */N/* TARGET PORT GROUPS command. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _tp {#pragma __nomember_alignmentN unsigned sho Lrt int scsi$tp$w_obsolete; /* Obsolete */N __union { /* Target Port Group */ __struct {Q unsigned char scsi$tp$b_rel_tp_msb; /* Relative Target Port ID MSB */Q unsigned char scsi$tp$b_rel_tp_lsb; /* Relative Target Port ID LSB */! } scsi$tp$r_tp_bytes;, unsigned short int scsi$tp$w_rel_tp; } scsi$tp$r_tp_overlay; } TP; #if !defined(__VAXC)B#define scsi$tp$r_ Ltp_bytes scsi$tp$r_tp_overlay.scsi$tp$r_tp_bytesD#define scsi$tp$b_rel_tp_msb scsi$tp$r_tp_bytes.scsi$tp$b_rel_tp_msbD#define scsi$tp$b_rel_tp_lsb scsi$tp$r_tp_bytes.scsi$tp$b_rel_tp_lsb>#define scsi$tp$w_rel_tp scsi$tp$r_tp_overlay.scsi$tp$w_rel_tp"#endif /* #if !defined(__VAXC) */ N/* */N/* TARGET PORT GROUP descriptor format, as defined by SPC-3. */N/* L */N/* Note: This structure is used to define data returned by the REPORT */N/* TARGET PORT GROUPS command. */N/* */)#define SCSI$RPT_TPG$M_ASYM_ACC_STATE 0xFN#define SCSI$RPT_TPG$C_AO 0 /* 0: Active/optimized */N#define SCSI$RPT_TPG$C_ANO 1 /* 1: Active/non-optimized */N#define SCSI$RPT_TPG$C_STANDBY 2 L /* 2: Standby */N#define SCSI$RPT_TPG$C_UNAVAILABLE 3 /* 3: Unavailable */N#define SCSI$RPT_TPG$C_TRANSIT 15 /* F: Transitioning between states */!#define SCSI$RPT_TPG$M_RSVD1 0x70 #define SCSI$RPT_TPG$M_PREF 0x80!#define SCSI$RPT_TPG$M_AO_SUP 0x1!#define SCSI$RPT_TPG$M_AN_SUP 0x2 #define SCSI$RPT_TPG$M_S_SUP 0x4 #define SCSI$RPT_TPG$M_U_SUP 0x8!#define SCSI$RPT_TPG$M_RSVD2 0x70!#define SCSI$RPT_TPG$M_T_SUP 0x80N#define SCSI$RPT_T LPG$C_NO_STATUS 0 /* 0: No status available */X#define SCSI$RPT_TPG$C_CMD 1 /* 1: Asymm state altered via SET TPG command */Y#define SCSI$RPT_TPG$C_IMPLICIT 2 /* 2: Asymm state altered by implicit behavior */N#define SCSI$RPT_TPG$C_HDR_LENGTH 8 /* Size of RTPG header info */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignme Lnt#endiftypedef struct _rpt_tpg {#pragma __nomember_alignment __struct {Q unsigned scsi$rpt_tpg$v_asym_acc_state : 4; /* Asymmetric access state */N unsigned scsi$rpt_tpg$v_rsvd1 : 3; /* Reserved */N unsigned scsi$rpt_tpg$v_pref : 1; /* Preferred target port */! } scsi$rpt_tpg$r_flags_1; __struct {N unsigned scsi$rpt_tpg$v_ao_sup : 1; /* Active/optimized supported */P unsigned scsi$rpt_tpg$v_an_sup : L 1; /* Active/non-optimized supported */N unsigned scsi$rpt_tpg$v_s_sup : 1; /* Standby supported */N unsigned scsi$rpt_tpg$v_u_sup : 1; /* Unavailable supported */N unsigned scsi$rpt_tpg$v_rsvd2 : 3; /* Reserved */N unsigned scsi$rpt_tpg$v_t_sup : 1; /* Transitioning supported */! } scsi$rpt_tpg$r_flags_2;N __union { /* Target Port Group */ __struct {N L unsigned char scsi$rpt_tpg$b_tpg_msb; /* Target Port Group MSB */N unsigned char scsi$rpt_tpg$b_tpg_lsb; /* Target Port Group LSB */' } scsi$rpt_tpg$r_tpg_bytes;. unsigned short int scsi$rpt_tpg$w_tpg;% } scsi$rpt_tpg$r_tpg_overlay;N unsigned char scsi$rpt_tpg$b_rsvd3; /* Reserved */N unsigned char scsi$rpt_tpg$b_status_code; /* Status code */N unsigned char scsi$rpt_tpg$b_vendor_spec; /* Vendor specif Lic */N unsigned char scsi$rpt_tpg$b_tp_cnt; /* Target port count */P TP scsi$rpt_tpg$r_tp_lst; /* Start of TP list (variable length) */ } RPT_TPG; #if !defined(__VAXC)Z#define scsi$rpt_tpg$v_asym_acc_state scsi$rpt_tpg$r_flags_1.scsi$rpt_tpg$v_asym_acc_stateH#define scsi$rpt_tpg$v_rsvd1 scsi$rpt_tpg$r_flags_1.scsi$rpt_tpg$v_rsvd1F#define scsi$rpt_tpg$v_pref scsi$rpt_tpg$r_flags_1.scsi$rpt_tpg$v_prefJ#define scsi$rpt_tpg$v_ao_sup scsi$rpt_tpg$r_fLlags_2.scsi$rpt_tpg$v_ao_supJ#define scsi$rpt_tpg$v_an_sup scsi$rpt_tpg$r_flags_2.scsi$rpt_tpg$v_an_supH#define scsi$rpt_tpg$v_s_sup scsi$rpt_tpg$r_flags_2.scsi$rpt_tpg$v_s_supH#define scsi$rpt_tpg$v_u_sup scsi$rpt_tpg$r_flags_2.scsi$rpt_tpg$v_u_supH#define scsi$rpt_tpg$v_rsvd2 scsi$rpt_tpg$r_flags_2.scsi$rpt_tpg$v_rsvd2H#define scsi$rpt_tpg$v_t_sup scsi$rpt_tpg$r_flags_2.scsi$rpt_tpg$v_t_supT#define scsi$rpt_tpg$r_tpg_bytes scsi$rpt_tpg$r_tpg_overlay.scsi$rpt_tpg$r_tpg_bytesN#define scsi$rpt_t Lpg$b_tpg_msb scsi$rpt_tpg$r_tpg_bytes.scsi$rpt_tpg$b_tpg_msbN#define scsi$rpt_tpg$b_tpg_lsb scsi$rpt_tpg$r_tpg_bytes.scsi$rpt_tpg$b_tpg_lsbH#define scsi$rpt_tpg$w_tpg scsi$rpt_tpg$r_tpg_overlay.scsi$rpt_tpg$w_tpg"#endif /* #if !defined(__VAXC) */ N/* */N/* REPORT TARGET PORT GROUPS parameter data format, as defined by SPC-3. */N/* */N/* Note: LThis structure is used to define data returned by the REPORT */N/* TARGET PORT GROUPS command. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _rpt_tpg_dat {#pragma __nomember_alignmentN unsigned int scsLi$rpt_tpg_dat$l_return_len; /* Return data length */R RPT_TPG scsi$rpt_tpg_dat$r_tpg_lst; /* Start of TPG list (variable length) */ } RPT_TPG_DAT;N/* */P/* Parameter list for SET TARGET PORT GROUP descriptor, as defined by SPC-3. */N/* */N/* Note: This structure is used to define data sent by the SET */N/* TARGET PORLT GROUPS command. */N/* */)#define SCSI$SET_TPG$M_ASYM_ACC_STATE 0xFN#define SCSI$SET_TPG$C_AO 0 /* 0: Active/optimized */N#define SCSI$SET_TPG$C_ANO 1 /* 1: Active/non-optimized */N#define SCSI$SET_TPG$C_STANDBY 2 /* 2: Standby */N#define SCSI$SET_TPG$C_UNAVAILABLE 3 /* 3: Unavailable */N#d Lefine SCSI$SET_TPG$C_ILLEGAL 15 /* F: Illegal Request */!#define SCSI$SET_TPG$M_RSVD1 0xF0 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _set_tpg {#pragma __nomember_alignment __struct {Q unsigned scsi$set_tpg$v_asym_acc_state : 4; /* Asymmetric access state */N unsigned scsi$set_tpg$v_rsvd1 L: 4; /* Reserved */ } scsi$set_tpg$r_flags;N unsigned char scsi$set_tpg$b_rsvd2; /* Reserved */N __union { /* Target Port Group */ __struct {N unsigned char scsi$set_tpg$b_tpg_msb; /* Target Port Group MSB */N unsigned char scsi$set_tpg$b_tpg_lsb; /* Target Port Group LSB */' } scsi$set_tpg$r_tpg_bytes;. unsigned short int scsi$set_tpg$w_tpg; L% } scsi$set_tpg$r_tpg_overlay; } SET_TPG; #if !defined(__VAXC)X#define scsi$set_tpg$v_asym_acc_state scsi$set_tpg$r_flags.scsi$set_tpg$v_asym_acc_stateF#define scsi$set_tpg$v_rsvd1 scsi$set_tpg$r_flags.scsi$set_tpg$v_rsvd1T#define scsi$set_tpg$r_tpg_bytes scsi$set_tpg$r_tpg_overlay.scsi$set_tpg$r_tpg_bytesN#define scsi$set_tpg$b_tpg_msb scsi$set_tpg$r_tpg_bytes.scsi$set_tpg$b_tpg_msbN#define scsi$set_tpg$b_tpg_lsb scsi$set_tpg$r_tpg_bytes.scsi$set_tpg$b_tpg_lsbH#define scsi$s Let_tpg$w_tpg scsi$set_tpg$r_tpg_overlay.scsi$set_tpg$w_tpg"#endif /* #if !defined(__VAXC) */ N/* */N/* Parameter list for SET TARGET PORT GROUPS, as defined by SPC-3. */N/* */N/* Note: This structure is used to define data sent by the SET */N/* TARGET PORT GROUPS command. Exactly one SET_TPG structure is */I/* r Lepresented in the TPG_LST since that is the most common */I/* usage, but additional SET_TPG's are allowed. */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _set_tpg_dat {#pragma __nomember_alignmentN unsigned int scsi$se Lt_tpg_dat$l_rsvd1; /* Reserved */Q SET_TPG scsi$set_tpg_dat$r_tpg_lst; /* Start of TPG list (varaible length) */ } SET_TPG_DAT;N/* */N/* Other SCSI opcodes */N/* */'#define SCSI$C_TEST_UNIT_READY_OPCODE 0#define SCSI$C_READ_6_OPCODE 8 #define SCSI$C_WRITE_6_OPCODE 10 L #define SCSI$C_INQUIRY_OPCODE 18&#define SCSI$C_MODE_SELECT_6_OPCODE 21%#define SCSI$C_MODE_SENSE_6_OPCODE 26(#define SCSI$C_START_STOP_UNIT_OPCODE 27)#define SCSI$C_READ_CAPACITY_10_OPCODE 37 #define SCSI$C_READ_10_OPCODE 40!#define SCSI$C_WRITE_10_OPCODE 42'#define SCSI$C_MODE_SELECT_10_OPCODE 85&#define SCSI$C_MODE_SENSE_10_OPCODE 90*#define SCSI$C_READ_CAPACITY_16_OPCODE 158N/* */N/* Additional Sense Codes (A LSC) */N/* */'#define SCSI$C_ASCQ_INIT_CMD_REQUIRED 2N/* */N/* Additional Sense Code Qualifiers (ASCQ) */N/* */"#define SCSI$C_ASC_LUN_NOT_READY 4 $#pragma __member_alignment __restoreR#ifdef __INITILAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SCSIDEF_LOADED */ ww` [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidentLial proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential L**/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************* L*************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */I/* Source: 25-MAY-1993 09:17:03 $1$DGA8345:[LIB_H.SRC]SCSNETDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SCSNETDEF ***/#ifndef __SCSNETDEF_LOADED#define __SCSNETDEF_LOADED 1 G#pragma __nostandard /* ThiLs file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#defLine __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SCS CI PPD definitions */N/* L */N/* This structure defines offsets and fields for SCS datagrams used in the */N/* datagram handshake between remote systems. The full format consists of */Q/* a port heder (See Structure PPD) followed by these definitions. The origin */N/* of this field is the beginning of user data for a normal SCS datagram */P/* so that the PDT$L_DGHDRSZ may be used to determine the true origin of the */N/* packet. L */N/*- */ N#define SCSNET$C_START_LEN 62 /* Start dg length */N#define SCSNET$C_STACK_LEN 62 /* Stack dg length */N#define SCSNET$C_ACK_LEN 2 /* Ack dg length */N#define SCSNET$C_HSHUT_LEN 2 /* Host shutdown dg length */N#define SCSNET$C_CACHE_LEN 2 /* Cache clear marker length L */N#define SCSNET$C_START 0 /* START DATAGRAM */N#define SCSNET$C_STACK 1 /* STACK DATAGRAM */N#define SCSNET$C_ACK 2 /* ACK DATAGRAM */N#define SCSNET$C_SCS_DG 3 /* SCS DATAGRAM */N#define SCSNET$C_SCS_MSG 4 /* SCS MESSAGE */N#define SCSNET$C_ELOG 5 /* ERROR LOG DATAGRAM */N#define SCSNET$CL_HOSTSHUT 6 /* HOST SHUTDOWN DATAGRAM */N#define SCSNET$C_CACHECLR 32768 /* CACHE CLEAR MARKER MSG */N/* (8000 hex) */N#define SCSNET$C_PRT_BASE 0 /* 1st PPD Protocol Rev */N#define SCSNET$C_PRT_ELOG 1 /* 2nd rev, supports error */N/* log dgs and host shutdown. */N#define SCSNET$C_MIN_DGSIZ 48 /* LMinimum allowed DG size, */N/* not including the SCS header. */N#define SCSNET$S_SCSNETDEF 80 /* Old size name - synonym */ Ctypedef struct _scsnet { /* WARNING: aggregate has origin of -32 */; /* WARNING: aggregate element "scsnet$b_ppd" ignored */> /* WARNING: aggregate element "scsnet$w_length" ignored *// /* WARNING: aggregate element "" ignored *// /* WARNING: aggregate element "" ignored *// /* WLARNING: aggregate element "" ignored */= /* WARNING: aggregate element "scsnet$w_mtype" ignored */@ /* WARNING: aggregate element "scsnet$b_systemid" ignored */@ /* WARNING: aggregate element "scsnet$b_protocol" ignored */> /* WARNING: aggregate element "scsnet$b_fill_1" ignored */= /* WARNING: aggregate element "scsnet$w_maxdg" ignored */> /* WARNING: aggregate element "scsnet$w_maxmsg" ignored */N char scsnet$t_swtype [4]; /* Software type L*/N char scsnet$t_swvers [4]; /* Software version */N unsigned __int64 scsnet$q_swincarn; /* Software incarnation # */N char scsnet$t_hwtype [4]; /* Hardware type */N unsigned char scsnet$b_hwvers [12]; /* Hardware version */N unsigned __int64 scsnet$q_nodename; /* Node Name */N unsigned __int64 scsnet$q_curtime; /* Current system time measured */N/* in 100 nsec unitsL */ } SCSNET; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SCSNETDEF_LOADED */ wwpG[UM/***************************************************************************L/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** L **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** L **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */F/* Source: 09-APR-2021 11:34:34 $1$DGA8345:[LIB_H.SRC]SDADEF.SDL;1 *//***************************************************************************************************************************** L***//*** MODULE $SDA_CIODEF ***/#ifndef __SDA_CIODEF_LOADED#define __SDA_CIODEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointeLrs */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define SDA_CIO$M_VALID 0x1#define SDA_CIO$M_PROCESS L0x2#define SDA_CIO$M_SLICED 0x4 #define SDA_CIO$M_COMPRESSED 0x8"#define SDA_CIO$M_ISD_INDEX 0xFFF0N#define SDA_CIO$K_FIX 0 /* Dynamic (fixup) */N#define SDA_CIO$K_INIT_CODE 1 /* Initialization (code) */N#define SDA_CIO$K_INIT_DATA 2 /* Initialization (data) */N#define SDA_CIO$K_CODE 3 /* Code */N#define SDA_CIO$K_RW 4 /* Data (read/write) */NL#define SDA_CIO$K_RO 5 /* Data (read only) */N#define SDA_CIO$K_DZERO 6 /* Demand zero */N#define SDA_CIO$K_TR_DZERO 7 /* Trailing demand zero */N#define SDA_CIO$K_UNWIND 8 /* Unwind tables */N#define SDA_CIO$K_UNKNOWN 9 /* Insert new entries before this */ typedef struct _comp_img_off {N unsigned sda_cio$v_valid : 1; /* Set if found an image L */V unsigned sda_cio$v_process : 1; /* Set if this is a process activated image */_ unsigned sda_cio$v_sliced : 1; /* Set if this image is sliced or installed/resident */^ unsigned sda_cio$v_compressed : 1; /* Set if this section is a compressed data section */N unsigned sda_cio$v_isd_index : 12; /* index into ISD table */ } COMP_IMG_OFF; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas Lsupported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SDA_CIODEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by HewletLt-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS SoftwarLe, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************* L*******************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */F/* Source: 09-APR-2021 11:34:34 $1$DGA8345:[LIB_H.SRC]SDADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SDA_FLAGSDEF ***/#ifndef __SDA_FLAGSDEF_LOADED#define __SDA_FLAGSDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#praLgma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params L...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define SDA_FLAGS$M_OVERRIDE 0x1#define SDA_FLAGS$M_CURRENT 0x2#define SDA_FLAGS$M_TARGET 0x4#define SDA_FLAGS$M_PROCESS 0x8#define SDA_FLAGS$M_IA64 0x10#define SDA_FLAGS$M_REMOTE 0x20#define SDA_FLAGS$M_X86_64 0x40#d Lefine SDA_FLAGS$M_PKRNL 0x80N#define SDA_FLAGS$K_VERSION 3 /* SDA version */ typedef struct _sda_flags {N unsigned sda_flags$v_override : 1; /* In override mode */N unsigned sda_flags$v_current : 1; /* Analyzing running system */N unsigned sda_flags$v_target : 1; /* Using SCD/SDD */N unsigned sda_flags$v_process : 1; /* Analyzing a process dump */N unsigned sda_flags$v_ia64 : 1; /*L Analyzing an IA64 dump */N unsigned sda_flags$v_remote : 1; /* Analyzing a remote system */N unsigned sda_flags$v_x86_64 : 1; /* Analyzing an X86 dump */N unsigned sda_flags$v_pkrnl : 1; /* Analyzing primary kernel memory */N/* */M/* Version of SDA extension interface that the extension must match up to. */I/* Platforms must have a different version so that extensions for on Le */K/* platform don't get activated under the cross-platform environment for */I/* the other platform. */N/* */I/* Update SDA_MAJOR_ID for incompatible interface changes */I/* Update SDA_MINOR_ID for upwards-compatible changes */N/* */ } SDA_FLAGS; $#pragma __Lmember_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard "#endif /* __SDA_FLAGSDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/*L* HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFILDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*****************************************************L**********************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:39 by OpenVMS SDL V3.7 */C/* Source: 07-OCT-2024 15:21:09 $1$DGA8345:[SHRLIB]SDAMSG.SDL;1 *//********************************************************************************************************************************//*** MODULE $SDA_MSGDEF ***/#ifndef __SDA_MSGDEF_LOADED#define __SDA_MSGDEF_LLOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...L#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */Q/* This SDL File Generated by VAX-11 Message V04-00 on 7-OCT-20L24 15:21:09.37 */N/* */N/* */J/* VERSION: 'X-41' */N/* */O/* ************************************************************************* */O/* * * */O/* * HLPE CONFIDENTIAL. THIS SOFTWARE IS CONFIDENTIAL PROPRIETARY SOFTWARE * */O/* * LICENSED BY HEWLETT PACKARD ENTERPRISE DEVELOPMENT, LP, AND IS NOT * */O/* * AUTHORIZED TO BE USED, DUPLICATED OR DISCLOSED TO ANYONE WITHOUT THE * */O/* * PRIOR WRITTEN PERMISSION OF HPE. * */O/* * COPYRIGHT 2017 HEWLETT PACKARD ENTERPRISE DEVELOPMENT, LP * */O/* * * */O/* * VMS SOFTWARE, ILNC. CONFIDENTIAL. THIS SOFTWARE IS CONFIDENTIAL * */O/* * PROPRIETARY SOFTWARE LICENSED BY VMS SOFTWARE, INC., AND IS NOT * */O/* * AUTHORIZED TO BE USED, DUPLICATED OR DISCLOSED TO ANYONE WITHOUT * */O/* * THE PRIOR WRITTEN PERMISSION OF VMS SOFTWARE, INC. * */O/* * COPYRIGHT 2017 VMS SOFTWARE, INC. * */O/* * * */O/* *******************************M****************************************** */N/* */N/*++ */N/* */I/* FACILITY */N/* */B/* LIB M */N/* */I/* ABSTRACT */N/* */B/* SYSTEM DUMP ANALYZER MESSAGE FILE DEFINITIONS */N/* */I/* ENVIRONMENT */N/* M */B/* NATIVE MODE, USER MODE */N/* */I/* AUTHOR */A/* RICHARD BISHOP MARCH 1997 */B/* BASED ON ORIGINAL: */>/* MIKE RHODES JUNE 1981 */B/* SEE [SDA]EVAX_SDAMSG.MSG FOR PRIOR AUDMIT TRAIL. */N/* */I/* MODIFIED BY */N/* */5/* X-41 RAB RICHARD A. BISHOP 15-JUL-2019 */B/* ADD NOLEVEL5 AND BADPTINIT */N/* */5/* X-40 RAB RICHARD A. BISHOP 15-NOV-20 M17 */B/* ADD NOTX86DUMP MESSAGE. */N/* */5/* X-39 RAB RICHARD A. BISHOP 15-OCT-2008 */B/* ADD TOOFRAGMENTED (DUMP FILE TOO FRAGMENTED). IT */B/* REPLACES HEADEXT WHICH IS NO LONGER NEEDED. */N/* */5/* X-38 RAB RICHARD A. BISHOP 22-MAY-2008 */B/* TWEAK TEXTM OF NOTSAVED, MAKE DUPLICATE A WARNING */B/* INSTEAD OF INFO, ADD PROCNOACC FOR FILE-ID/UNWIND */B/* DATA COLLECTION */N/* */5/* X-37 RAB RICHARD A. BISHOP 26-MAR-2008 */B/* ADD SEVERAL NEW MESSAGES FOR PARTIAL DUMP COPIES */B/* (AND THEREFORE SDA OPENING MULTIPLE INPUT FILES AT */B/* THE SAME TIME) M */N/* */5/* X-36 RAB RICHARD A. BISHOP 16-MAR-2007 */B/* ADD NOLMBSFOUND FOR PARTIAL DUMP COPIES AND BADCPU */B/* FOR SET|SHOW CPU/NEXT */N/* */5/* X-35 RAB RICHARD A. BISHOP 23-MAR-2006 */B/* ADD ZEROSYM FOR CORRUPTED SYMBOL VECTOR ENTRIES */N/* M */5/* X-34 RAB RICHARD A. BISHOP 03-FEB-2006 */B/* ADD NOTACOLL FOR SHOW DUMP/COLLECTION DRILL-DOWN */N/* */5/* X-33 RAB RICHARD A. BISHOP 27-OCT-2005 */B/* ADD NEW MESSAGES FOR THE SEPARATE COLLECTION FILE, */B/* TWEAK A COUPLE OF OTHERS */N/* M */5/* X-32 RAB RICHARD A. BISHOP 29-SEP-2005 */B/* ADD SPLNOTFOUND, MORE CORRECT THAN NOSPLOWNED IF */B/* /OWNED NOT SPECIFIED. */N/* */5/* X-31 RAB RICHARD A. BISHOP 10-MAY-2005 */B/* ANOTHER COLLECTION MESSAGE...NONEWCOLLECT...OUTPUT */B/* IF A COLLECT COMMAND IS DONE WHEN THERE'S ALREADY */ MB/* A COLLECTION IN THE DUMP BEING ANALYZED. */N/* */5/* X-30 RAB RICHARD A. BISHOP 11-MAR-2005 */B/* ADD A COUPLE MORE COLLECTION MESSAGES */N/* */5/* X-29 RAB RICHARD A. BISHOP 10-FEB-2005 */B/* ADD VARIOUS NEW MESSAGES FOR FILE AND/OR UNWIND */B/* DATA COLLECTIONS  M */N/* */5/* X-28 RAB RICHARD A. BISHOP 04-NOV-2004 */B/* CHANGE "spin lock" TO "spinlock" IN BADSPLNAME AND */B/* NOSPLOWNED */N/* */5/* X-27 RAB RICHARD A. BISHOP 08-OCT-2004 */B/* CHANGE PDRANGE_INVALID TO FDPDRANGE_INVAL TO REFLECT M */B/* FUNCTION DESCRIPTORS ON IA64. */N/* */5/* X-26 RAB RICHARD A. BISHOP 23-AUG-2004 */B/* INITIAL CPU NAMESPACE CHANGES */N/* */5/* X-25 RAB RICHARD A. BISHOP 26-FEB-2004 */B/* TWEAK TEXT OF BADHWM */N/*  M */5/* X-24 RAB RICHARD A. BISHOP 09-OCT-2003 */B/* CHANGE LOSTPROCESS TEXT */N/* */5/* X-23 RAB RICHARD A. BISHOP 01-MAY-2003 */B/* CHANGE IT TO NOTI64DUMP */N/* */5/* X-22 RAB RICHARD A. BISHOP 06-DEC- M2002 */B/* ADD NOTIA64DUMP */N/* */5/* X-21 RAB RICHARD A. BISHOP 14-NOV-2001 */B/* ADD LOSTPROCESS WARNING FOR WHEN CURRENTLY SET */B/* PROCESS GOES AWAY. */N/* */5/* X-20 RAB RICHARD A. BISHOP 31-OCT-2001 */B/* ADD WRONMGCPU WARNING FOR WHEN A SET CPU DOESN'T END */B/* UP AT THE RIGHT CPU. */N/* */5/* X-19 RAB RICHARD A. BISHOP 09-AUG-2001 */B/* ADD NEW MESSAGES FOR SHADOW SET PROCESSING */N/* */5/* X-18 RAB RICHARD A. BISHOP 28-SEP-2000 */B/* CHANGE TEXT OF NOSTATS - NOW ONLY FOR MLACK OF RING BUFFER */N/* */5/* X-17 RAB RICHARD A. BISHOP 13-SEP-2000 */B/* CHANGE NOSUCHPOOL FROM !AC TO !AZ FOR POOL TYPE */N/* */5/* X-16 RAB RICHARD A. BISHOP 30-MAR-2000 */B/* ADD NOPRCDMP AND NODEBUG */N/* M */5/* X-15 RAB RICHARD A. BISHOP 21-FEB-2000 */B/* ADD BADHWM AND NOHWMCHECK */N/* */5/* X-14 RAB RICHARD A. BISHOP 18-FEB-2000 */B/* REINSTATE SHOW POOL/TYPE=UNKNOWN */N/* */5/* X-13 RAB RICHARD A. BISHOP 28-JAN-2000 */B/* ADD REGNOTACC FOR PROCESSOR REMGISTERS THAT AREN'T ON */B/* ALL PLATFORMS. */N/* */5/* X-12 RAB RICHARD A. BISHOP 14-DEC-1999 */B/* ADD EXCLUDED DATA MESSAGE FOR PROCESS DUMPS */N/* */5/* X-11 RAB RICHARD A. BISHOP 17-DEC-1998 */B/* ADD NOTATQE FOR SHOW TQE AND NOTAUCB FOR THE EXTENSION M*/B/* ROUTINE SDA$GET_DEVICE_NAME. */N/* */5/* X-10 RAB RICHARD A. BISHOP 11-JUN-1998 */B/* ADD NOIOMEMMAP FOR WHEN SHOW PAGE/INVALID_PFN IS */B/* USED ON A SYSTEM THAT CAN'T SUPPORT IT. */N/* */4/* X-9 RAB RICHARD A. BISHOP 8-JUN-1998 */B/* ADD CPUNOTAVAIL & PROCNOMTAVAIL, TO BE OUTPUT WHEN */B/* A SET CPU OR SET PROCESS (EXPLICIT OR IMPLICIT) IS */B/* ENTERED AND SDA HAS BEEN INVOKED WITHIN SCD/SDD, */B/* WHERE SUCH SWITCHING IS NOT CURRENTLY POSSIBLE. */N/* */4/* X-8 RAB RICHARD A. BISHOP 12-MAY-1998 */B/* MAKE ADDRESSES IN UNALIGNED AND NOTINIMAGE BE 64-BIT. */B/* ADD FOUR MORE GALAXY MESSAGES (NOTNODEB, NODEBNOTFND, M */B/* NOTGCTTYPE, NOTGCTNODE) */N/* */4/* X-7 RAB RICHARD A. BISHOP 29-APR-1998 */B/* REDO PREVIOUS. X-5 CHECKED BACK IN BY MISTAKE. */N/* */4/* X-6 RAB RICHARD A. BISHOP 23-APR-1998 */B/* ANOTHER GALAXY MESSAGE - NOGCT */N/* M */4/* X-5 RAB RICHARD A. BISHOP 9-APR-1998 */B/* ANOTHER GALAXY MESSAGE - NOGMDB */N/* */4/* X-4 RAB RICHARD A. BISHOP 15-JAN-1998 */B/* MORE GALAXY MESSAGES */N/* */4/* X-3 RAB RICHARD A. BISHOP 18-DEC-1997 M */B/* ADD FIRST CROP OF GALAXY-RELATED MESSAGES FOR SHARED */B/* MEMORY DUMPS AND FOR THE NEW SHOW SHM_CPP COMMAND */N/* */4/* X-2 RAB RICHARD A. BISHOP 24-MAR-1997 */B/* MERGE IN RMS AND TPPSDA MESSAGES. ENSURE ALL MESSAGES */B/* HAVE TEXT */N/* */4/* X-1 RAB RIMCHARD A. BISHOP 20-MAR-1997 */B/* INITIAL VERSION */N/* */N/*-- */#define SDA$_FACILITY 244N/* */I/* BEGIN SYMBOL DEFINITIONS... */N/* M */N/*NOTE: PLEASE ADD ALL NEW MESSAGES AT THE END OF THIS FILE AND */I/* INSERT PLACEHOLDERS FOR ALL MESSAGES WHICH ARE REMOVED. */I/* THIS WILL PREVENT INCORRECT MESSAGES FROM BEING DISPLAYED */I/* WHEN USING OLD VERSIONS OF SDA TO ANALYZE CRASH DUMPS FROM */I/* PREVIOUS BASELEVELS. */N/* */U#define SDA$_SUCMCESS 16023561 /*NOTE: THIS IS AN INTERNALLY USED SIGNAL */N/*AND SHOULD NEVER BE OUTPUT */#define SDA$_NORESOURC 16023571#define SDA$_NOLOCKS 16023579#define SDA$_NOPRLOCK 16023587#define SDA$_SHORTDUMP 16023592#define SDA$_NOREQ 16023600#define SDA$_BADGSD 16023608#define SDA$_NOLDRIMG 16023616#define SDA$_NOREAD 16023624"#define SDA$_NOREADLDRIMG 16023632#define SDA$_INSKIPPED 16023640#define SDA$_SYNTAX 16023648 M#define SDA$_NOIMGRMS 16023656#define SDA$_NOTCOPIED 16023664N/* */G/* NOTE: THE FOLLOWING WARNING MESSAGES ARE INTERNALLY SIGNALLED */B/* CONDITIONS AND SHOULD NEVER BE OUTPUT */N/* */#define SDA$_BACKUP 16023672#define SDA$_EOF 16023680#define SDA$_EXITCMD 16023688#define SDA$_NOTVALID 16023698#define SDA$_DUMMPEMPTY 16023706#define SDA$_BADSYM 16023714#define SDA$_NOTINPHYS 16023722#define SDA$_BADPROC 16023730#define SDA$_INVBLKTYP 16023738#define SDA$_NOSYMBOLS 16023746#define SDA$_NOACCESS 16023754#define SDA$_SPTNOTFND 16023762#define SDA$_NOINSTRAN 16023770#define SDA$_RMSTERM 16023778#define SDA$_LOCKIDZER 16023786#define SDA$_OUTOFRANG 16023794#define SDA$_NOLKB 16023802#define SDA$_INVRANGE 16023810#define SDA$_NOQUEUE 16023818#define SDA$_OUTSIDPT 16023826M#define SDA$_PFNNOTMPD 16023834#define SDA$_BLKSNRLSD 16023842#define SDA$_EXPTOOLRG 16023850#define SDA$_ATTFAIL 16023858#define SDA$_SPWNFAIL 16023866#define SDA$_OPENIN 16023876#define SDA$_NOTPAGFIL 16023882#define SDA$_NOTFOUND 16023888#define SDA$_HDRERRS 16023896#define SDA$_MEMERRS 16023904 #define SDA$_OBSOLETE_2 16023912#define SDA$_DUMPERRS 16023920 #define SDA$_SCSNODNFND 16023928#define SDA$_CPUNOTVLD 16023938#define SDA$_CMDNOTVLD 16023946#define SDMA$_NOBUGCHK 16023954 #define SDA$_BADSPLNAME 16023962!#define SDA$_BADSPLINDEX 16023970 #define SDA$_NOTSPLADDR 16023978!#define SDA$_DUMPINCOMPL 16023988#define SDA$_INSUFFMEM 16023996!#define SDA$_INCDUMPFORM 16024004#define SDA$_NOREQSYM 16024012#define SDA$_READSYM 16024019#define SDA$_CPUIDLE 16024027##define SDA$_SYMFILENOTSTB 16024035 #define SDA$_NOSPLOWNED 16024043#define SDA$_FMTACLERR 16024048#define SDA$_BDBLNKBRK 16024056#define SDA$_NOITMTRM 16024064#definMe SDA$_FAOERR 16024072!#define SDA$_INVLDPEPORT 16024080#define SDA$_NOTSAVED 16024088#define SDA$_INCOMPL 16024096#define SDA$_MEMNOTSVD 16024104#define SDA$_INCCTXT 16024112#define SDA$_INVLDADR 16024122#define SDA$_RESTOOBIG 16024130#define SDA$_NORSBNAM 16024138#define SDA$_NOLKBNAM 16024146#define SDA$_REGNOTVLD 16024154!#define SDA$_NOMCHKFRAME 16024163 #define SDA$_BADCPUTYPE 16024170%#define SDA$_BADMCHKFRAMEREV 16024178#define SDA$_INVSUBTYP 16024186#define MSDA$_MINVERMIS 16024192#define SDA$_IMGNOTACT 16024200#define SDA$_VERSMISM 16024210#define SDA$_FORMATDS 16024219#define SDA$_NOSUCHTP 16024226#define SDA$_CNFLTARGS 16024234 #define SDA$_SUPPNOTINS 16024242N#define SDA$_NOSTATS 16024250 /* */N/* */N/*NOTE : THE FOLLOWING MESSAGE AREA IS RESERVED FOR THE DEFINITION OF */J/* MESSAGES DEFINED WITHIN THE TP SERVICES M SDA SUPPORT SHAREABLE IMAGE. */N/* */K/* CURRENTLY THE PRECEEDING MESSAGES NUMBER SOME 100 IN TOTAL, HENCE THE */L/* MESSAGES FOR TP SERVICES SDA SUPPORT HAVE BEEN BASED AT 100 WITH SPACE */I/* FOR SOME 50 ERROR/WARNING/INFORMATION AND SUCCESS MESSAGES. */N/* */#define SDA$_NOSYSTPS 16024352#define SDA$_NOPROCTPS 16024360#define SDA$_N !MOSYSCLF 16024368#define SDA$_NOSYSIPC 16024376 #define SDA$_NOTIDSTRUC 16024384#define SDA$_TPSFAOERR 16024392#define SDA$_TPSACLERR 16024400#define SDA$_TPSNOTRM 16024408#define SDA$_TPSUTCERR 16024416#define SDA$_TPSTERM 16024514#define SDA$_TPSINVBLK 16024522I/* MESSAGES FROM LIB$ASCII_TO_UID, LIB$COMPARE_UID, LIB$UID_TO_ASCII */N/* */#define SDA$_UNSUPVER 16024530I/* MESSAGE FROM LIB$ASCII_TO_UID "M */N/* */#define SDA$_BADFORMAT 16024538N/* FORCE A BUFFER ZONE */N/* */N/*NOTE: THE FOLLOWING MESSAGE AREA IS RESERVED FOR THE DEFINITIONS OF */I/* MESSAGES DEFINED WITHING THE RMS SDA SUPPORT SHAREABLE IMAGE. */N/* #M */I/* CURRENTLY THE PRECEEDING MESSAGES NUMBER SOME 150 IN TOTAL, HENCE */I/* THE MESSAGES FOR RMS SDA SUPPORT HAVE BEEN BASED AT 150 WITH SPACE */I/* FOR SOME 50 ERROR/WARNING/INFORMATION AND SUCCESS MESSAGES. */N/* */ #define SDA$_NORMSSHARE 16024752N/* FORCE A BUFFER ZONE */N/* $M */N/* */;/* *************************** */O/* ALL NEW SDA MESSAGES SHOULD BE ADDED FOLLOWING THE ".BASE 200" DIRECTIVE. */;/* *************************** */N/* */N/* */#define SDA$_EMPTY%MNEST 16025152 #define SDA$_OBSOLETE_1 16025160#define SDA$_UNALIGNED 16025168 #define SDA$_STACKNTFND 16025176#define SDA$_INVSTACK 16025184##define SDA$_IDENTMISMATCH 16025192%#define SDA$_FDPDRANGE_INVAL 16025202 #define SDA$_OBSOLETE_3 16025210#define SDA$_NOSYMVECT 16025218 #define SDA$_NOPAGESIZE 16025226 #define SDA$_NOTINIMAGE 16025234#define SDA$_HWRPB_NF 16025242##define SDA$_RD_SYSIMG_ERR 16025250"#define SDA$_RD_IMAGE_ERR 16025258#define SDA$_IMAGENF 16025266#def&Mine SDA$_INCONPOOL 16025274#define SDA$_NOCLUSTER 16025282#define SDA$_BADPAGE 16025288##define SDA$_INVALID_HWRPB 16025296#define SDA$_CTRLC_ACK 16025307#define SDA$_NOIMSEM 16025315#define SDA$_INVREGID 16025320N/* TEMPORARY MESSAGE */!#define SDA$_GLOBNOTIMPL 16025330 #define SDA$_FPNOTFOUND 16025338#define SDA$_NOLOCKID 16025346 #define SDA$_NOFILENAME 16025352!#define SDA$_REGNOTAVAIL 16025360#define SDA$_NOCBMAP 1'M6025372#define SDA$_ALRDYCOMP 16025379#define SDA$_ALRDYDCMP 16025387#define SDA$_DEFLATE 16025395#define SDA$_INFLATE 16025403#define SDA$_COPYFAIL 16025408#define SDA$_OPENOUT 16025416##define SDA$_HWRPB_SUSPECT 16025424 #define SDA$_NOSAVEDUMP 16025434"#define SDA$_NOTALPHADUMP 16025442 #define SDA$_BADOVER4GB 16025448!#define SDA$_BADPSBARRAY 16025456"#define SDA$_LINKTIMEMISM 16025464!#define SDA$_SDALINKMISM 16025472!#define SDA$_ERRLOGSONLY 16025482#define SDA$_B(MADCHKSUM 16025488##define SDA$_PROCNOTDUMPED 16025496$#define SDA$_PROCPARTDUMPED 16025504 #define SDA$_NOSUCHPOOL 16025512 #define SDA$_NOPOOLTYPE 16025522"#define SDA$_MISSINGQUALS 16025530#define SDA$_MEMNOTACC 16025538 #define SDA$_CNFLTQUALS 16025546#define SDA$_NOCHANGE 16025554#define SDA$_NOMATCH 16025562#define SDA$_NOTANLMB 16025570##define SDA$_TOOMANYERLBUF 16025576"#define SDA$_ERLBUFTOOBIG 16025584#define SDA$_DUMPMOD 16025592%#define SDA$_CBLOCKMAPTOOBIG 1602560)M0 #define SDA$_PHYNOTIMPL 16025610#define SDA$_NOMODIFY 16025618"#define SDA$_SHORTERLDUMP 16025624 #define SDA$_STUBNOCOMP 16025632!#define SDA$_DUMPBLKSREL 16025642 #define SDA$_DMPRELEXIT 16025651 #define SDA$_VECNOTINIT 16025658#define SDA$_SHMDUMP 16025666 #define SDA$_NOTSHMDUMP 16025674#define SDA$_NOTSHMCPP 16025682#define SDA$_NOSHMCPP 16025690#define SDA$_NOTSHMREG 16025698#define SDA$_NOSHMREG 16025706"#define SDA$_SHMREGNOTFND 16025714#define SDA$_NOGMDB 16025722*M#define SDA$_NOGCT 16025730#define SDA$_NOTNODEB 16025738!#define SDA$_NODEBNOTFND 16025746 #define SDA$_NOTGCTTYPE 16025754 #define SDA$_NOTGCTNODE 16025762!#define SDA$_CPUNOTAVAIL 16025770"#define SDA$_PROCNOTAVAIL 16025778 #define SDA$_NOIOMEMMAP 16025786#define SDA$_NOTATQE 16025794#define SDA$_NOTAUCB 16025802#define SDA$_REGNOTACC 16025810#define SDA$_EXCLDATA 16025816#define SDA$_BADHWM 16025824 #define SDA$_NOHWMCHECK 16025832#define SDA$_NOPRCDMP 16025842#defin+Me SDA$_NODEBUG 16025850#define SDA$_NOTMEMBER 16025858#define SDA$_SHADFAIL 16025866#define SDA$_NEEDPHYIO 16025874#define SDA$_NOPHYIO 16025883#define SDA$_SINGLEMEM 16025891##define SDA$_TOOFRAGMENTED 16025899#define SDA$_USEMASTER 16025907"#define SDA$_NOTSYSERLDMP 16025912#define SDA$_WRONGCPU 16025920!#define SDA$_LOSTPROCESS 16025928 #define SDA$_NOTI64DUMP 16025938#define SDA$_NOCOLLECT 16025946#define SDA$_BADELF 16025954 #define SDA$_STUBNOCOLL 16025960#defin,Me SDA$_DISKNOACC 16025968#define SDA$_FILENOACC 16025976 #define SDA$_COLLECTING 16025987 #define SDA$_COLLECTION 16025995"#define SDA$_NONETCOLLECT 16026003"#define SDA$_NOTCOLLECTED 16026011"#define SDA$_NONEWCOLLECT 16026019!#define SDA$_SPLNOTFOUND 16026027 #define SDA$_WRONGCRASH 16026035!#define SDA$_COLLECTONLY 16026042##define SDA$_NOCOLLECTFILE 16026050 #define SDA$_BADCOLLECT 16026056#define SDA$_NOTACOLL 16026066#define SDA$_ZEROSYM 16026072!#define SDA$_NOLMBSFOUND 1-M6026080#define SDA$_BADCPU 16026090!#define SDA$_PARTIALDUMP 16026098"#define SDA$_TOOMANYFILES 16026106 #define SDA$_BADFILENUM 16026114!#define SDA$_PRIMARYDUMP 16026120#define SDA$_OPENTWICE 16026128"#define SDA$_NOTSAMECRASH 16026136!#define SDA$_NOTSAMECOMP 16026144 #define SDA$_UNEXPECTED 16026152#define SDA$_CORRUPT 16026160#define SDA$_LMBEMPTY 16026168 #define SDA$_LMBMISSING 16026176#define SDA$_OPENED 16026187#define SDA$_DUPLICATE 16026192#define SDA$_PROCNOACC .M 16026200 #define SDA$_NOTX86DUMP 16026210#define SDA$_NOLEVEL5 16026218#define SDA$_BADPTINIT 16026226N/* */I/* END SYMBOL DEFINITIONS...AND THIS MESSAGE FILE! */N/* */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size /M__restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SDA_MSGDEF_LOADED */ ww1[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is n0Mot **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized1M to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************************************************************************** 2M*********/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */F/* Source: 09-APR-2021 11:34:34 $1$DGA8345:[LIB_H.SRC]SDADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SDA_OPTDEF ***/#ifndef __SDA_OPTDEF_LOADED#define __SDA_OPTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_a3MlignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__V4MAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define SDA_OPT$M_QUEUE_SELF 0x1$#define SDA_OPT$M_QUEUE_QUADLINK 0x2$#define SDA_OPT$M_QUEUE_SINGLINK 0x4%#define SDA_OPT$M_QUEUE_LISTQUEUE 0x8%#define SDA_OPT$M_QUEUE_BACKLINK 0x10)#define SDA_OPT$M_QUEUE_MAX_VALIDATE 0x20 #define SDA_OPT$M_READ_FORCE 0x1 #define SDA_OPT$M_RE 5MAD_IMAGE 0x2 #define SDA_OPT$M_READ_SYMVA 0x4#define SDA_OPT$M_READ_RELO 0x8 #define SDA_OPT$M_READ_EXEC 0x10!#define SDA_OPT$M_READ_NOLOG 0x20$#define SDA_OPT$M_READ_FILESPEC 0x40$#define SDA_OPT$M_READ_NOSIGNAL 0x80(#define SDA_OPT$M_READ_MAX_SYMFILE 0x100!#define SDA_OPT$M_FORMAT_TYPE 0x1"#define SDA_OPT$M_SPARE1 0xFFFFFFF%#define SDA_OPT$M_PHYSICAL 0x10000000N#define SDA_OPT$K_PARSE_SAVE 0 /* save this command for recall */N#define SDA_OPT$K_PARSE_DONT_SAVE 1 /* d 6Mo not save this command */ union optdef { __struct {N unsigned sda_opt$v_queue_self : 1; /* SELF RELATIVE QUEUE */N unsigned sda_opt$v_queue_quadlink : 1; /* QUEUE with QUADWORD links */N unsigned sda_opt$v_queue_singlink : 1; /* Singly linked queue */O unsigned sda_opt$v_queue_listqueue : 1; /* Display elements of queue */N unsigned sda_opt$v_queue_backlink : 1; /* Scan backwards */2 unsigned sda_opt$v_que 7Mue_max_validate : 1;' unsigned sda_opt$v_fill_0_ : 2; } sda_opt$r_validate; __struct {N unsigned sda_opt$v_read_force : 1; /* READ/FORCE */N unsigned sda_opt$v_read_image : 1; /* READ/IMAGE */N unsigned sda_opt$v_read_symva : 1; /* READ/SYMVA */N unsigned sda_opt$v_read_relo : 1; /* READ/RELO */N unsigned sda_opt$v_read_exec : 1; /* READ/EXEC [] 8M */N unsigned sda_opt$v_read_nolog : 1; /* /NOLOG */N unsigned sda_opt$v_read_filespec : 1; /* or given */[ unsigned sda_opt$v_read_nosignal : 1; /* just return status, don't signal errors */0 unsigned sda_opt$v_read_max_symfile : 1;' unsigned sda_opt$v_fill_1_ : 7;! } sda_opt$r_read_symfile; __struct {N unsigned sda_opt$v_format_type : 1; /* FORMAT/TYPE=name */' unsigned s 9Mda_opt$v_fill_2_ : 7; } sda_opt$r_format; __struct {' unsigned sda_opt$v_spare1 : 28;N unsigned sda_opt$v_physical : 1; /* Physical address */' unsigned sda_opt$v_fill_3_ : 3; } sda_opt$r_misc; } ; #if !defined(__VAXC)D#define sda_opt$v_queue_self sda_opt$r_validate.sda_opt$v_queue_selfL#define sda_opt$v_queue_quadlink sda_opt$r_validate.sda_opt$v_queue_quadlinkL#define sda_opt$v_queue_singlink sda_opt$r_validate.sda_op:Mt$v_queue_singlinkN#define sda_opt$v_queue_listqueue sda_opt$r_validate.sda_opt$v_queue_listqueueL#define sda_opt$v_queue_backlink sda_opt$r_validate.sda_opt$v_queue_backlinkT#define sda_opt$v_queue_max_validate sda_opt$r_validate.sda_opt$v_queue_max_validateH#define sda_opt$v_read_force sda_opt$r_read_symfile.sda_opt$v_read_forceH#define sda_opt$v_read_image sda_opt$r_read_symfile.sda_opt$v_read_imageH#define sda_opt$v_read_symva sda_opt$r_read_symfile.sda_opt$v_read_symvaF#define sda_opt$v_re;Mad_relo sda_opt$r_read_symfile.sda_opt$v_read_reloF#define sda_opt$v_read_exec sda_opt$r_read_symfile.sda_opt$v_read_execH#define sda_opt$v_read_nolog sda_opt$r_read_symfile.sda_opt$v_read_nologN#define sda_opt$v_read_filespec sda_opt$r_read_symfile.sda_opt$v_read_filespecN#define sda_opt$v_read_nosignal sda_opt$r_read_symfile.sda_opt$v_read_nosignalT#define sda_opt$v_read_max_symfile sda_opt$r_read_symfile.sda_opt$v_read_max_symfileD#define sda_opt$v_format_type sda_opt$r_format.sda_opt$v_formaM **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** ?M **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */G/* Source: 20-APR-1993 15:20:44 $1$DGA8345:[LIB_H.SRC]SDIRDEF.SDL;1 *//*************************************************************************************** @M*****************************************//*** MODULE $SDIRDEF ***/#ifndef __SDIRDEF_LOADED#define __SDIRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr sAMize default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ BM */N/* SDIR - SCS DIRECTORY ENTRY */N/* */N/* THIS DATA STRUCTURE IS ALLOCATED FOR EACH LOCAL PROCESS THAT WANTS */N/* TO BE KNOWN TO SCS. */N/*- */ #define SDIR$K_LENGTH 48#define SDIR$C_LENGTH 48 CM#define SDIR$S_SDIRDEF 48 typedef struct _sdir {N struct _sdir *sdir$l_flink; /*FWD LINK */N struct _sdir *sdir$l_blink; /*BCK LINK */N unsigned short int sdir$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char sdir$b_type; /*SCS STRUCTURE TYPE */N unsigned char sdir$b_subtyp; /*SCS STRUCTURE SUBTYPE FOR SDIR */N unsigned char sdir$b_procnam [16]; /*ASCII DMSTRING FOR PROCESS NAME */N unsigned char sdir$b_procinf [16]; /*ASCII STRING FOR PROCESS INFO */N unsigned int sdir$l_conid; /*CONNECTION ID */ } SDIR; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif EM /* __SDIRDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. FM **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/GMM/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */F/* Source: 15-NOV-2017 12:53:29 $1$DGA8345:[LIB_H.SRC]SDPDEF.SDL;1 HM*//********************************************************************************************************************************//*** MODULE $SDPDEF ***/#ifndef __SDPDEF_LOADED#define __SDPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previouslIMy-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union unionJM#else#define __union variant_union#endif#endif #define SDP$M_LENGTH 0x7F#define SDP$M_WILDCARD 0x80 typedef struct _sdp_data { __union { __struct {) unsigned short int sdp$w_mem;) unsigned short int sdp$w_grp;" } sdp$r_uic_structure; unsigned int sdp$l_uic; } sdp$r_uic_overlay; __union { __struct {& unsigned sdp$v_length : 7;( unsigned sdp$v_wildcard : 1;# KM char sdp$t_string [15];# } sdp$r_name_structure; char sdp$t_name [16]; } sdp$r_name_overlay; } SDP_DATA; #if !defined(__VAXC)A#define sdp$w_mem sdp$r_uic_overlay.sdp$r_uic_structure.sdp$w_memA#define sdp$w_grp sdp$r_uic_overlay.sdp$r_uic_structure.sdp$w_grp-#define sdp$l_uic sdp$r_uic_overlay.sdp$l_uicI#define sdp$v_length sdp$r_name_overlay.sdp$r_name_structure.sdp$v_lengthM#define sdp$v_wildcard sdp$r_name_overlay.sdp$r_name_structure.sdp$v_wLMildcardI#define sdp$t_string sdp$r_name_overlay.sdp$r_name_structure.sdp$t_string0#define sdp$t_name sdp$r_name_overlay.sdp$t_name"#endif /* #if !defined(__VAXC) */  typedef struct _sdp { unsigned int sdp$l_count; unsigned int sdp$l_checksum;" unsigned short int sdp$w_size; unsigned char sdp$b_type; unsigned char sdp$b_subtype; SDP_DATA sdp$r_process; } SDP; #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current MMpointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Itypedef struct _sdp * SDP_PQ; /* Long pointer to an SDP structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 SDP_PQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* RNMestore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SDPDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authOMorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicaPMted or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Creat QMed: 7-Oct-2024 15:22:24 by OpenVMS SDL V3.7 */I/* Source: 24-FEB-2004 17:01:45 $1$DGA8345:[LIB_H.SRC]SECLIBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SECLIBDEF ***/#ifndef __SECLIBDEF_LOADED#define __SECLIBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __IRMNITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struSMct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* PROCESS OR GLOBAL SECTION DEFINITIONS */N/*- */N/* TM */N/* ***** L_VBN, L_WINDOW, and L_PFC must be the same offset values as the */N/* ***** equivalently named offsets in $PFLDEF. */N/* */ #define SEC$K_SECLIBDEF 1#define SEC$C_SECLIBDEF 1 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previouslUMy-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SECLIBDEF_LOADED */ ww0[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be useVMd, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosedWM to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 XM15:22:24 by OpenVMS SDL V3.7 */F/* Source: 11-NOV-1999 10:41:06 $1$DGA8345:[LIB_H.SRC]SGNDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SGNDEF ***/#ifndef __SGNDEF_LOADED#define __SGNDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* DeYMfined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define ZM__struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SYSGEN PARAMETER DEFINITIONS */N/*- */N/* */Q#define SGN$C_BA[MLSETCNT 24 /* NUMBER OF PROCESSES IN BALANCE SET */N#define SGN$C_DFWSCNT 100 /* DEFAULT WORKING SET COUNT */N#define SGN$C_DFWSQUOTA 120 /* DEFAULT WORKING SET QUOTA */N#define SGN$C_GBLSECCNT 40 /* GLOBAL SECTION COUNT */N#define SGN$C_MAXGPGCNT 2048 /* GLOBAL PAGE COUNT (GPT SIZE) */N#define SGN$C_MAXPAGCNT 16384 /* PHYSICAL MEMORY SIZE IN PAGES */N#define SGN$C_MAXPGFL 4096 \M /* DEFAULT MAXIMUM PAGING FILE */N#define SGN$C_MAXPSTCNT 5 /* MAX NUMBER OF PST ENTRIES */O#define SGN$C_MAXVPGCNT 8192 /* MAX PROCESS VIRTUAL SIZE (PAGES) */N#define SGN$C_MAXWSCNT 1024 /* MAX WORKING SET SIZE (PAGES) */N#define SGN$C_MINWSCNT 10 /* MIN WORKING SET SIZE (PAGES) */N#define SGN$C_NPAGEDYN 26624 /* NON-PAGED DYNAMIC POOL SIZE */N#define SGN$C_NPROCS 64 /* MAX NUMBER OF PROCE]MSSES */O#define SGN$C_PAGEDYN 16384 /* PAGED DYNAMIC POOL SIZE IN BYTES */N#define SGN$C_PHYPAGCNT 4096 /* ACTUAL PHYSICAL PAGE COUNT */O#define SGN$C_SYSDWSCNT 40 /* DEFAULT SYSTEM WORKING SET COUNT */U#define SGN$C_SYSVECPGS 5 /* NO. OF PAGES OF SYSTEM SERVICE VECTORS */N#define SGN$C_SYSWSCNT 96 /* SYSTEM WORKING SET COUNT */N/* ^M*/]/* The preceeding may be obsolete as of 11-Nov-1999. I don't see them being used anywhere */S/* However, the following will be used in SYSPARAM.MAR and possibly other places */N/* */N#define SGN$C_NPAGEDYN_MIN 163840 /* Minimum value for NPAGEDYN */N#define SGN$C_NPAGEVIR_MIN 163840 /* Minimum value for NPAGEVIR */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* De_Mfined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SGNDEF_LOADED */ wwPj[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software `M**/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary softaMware licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************* bM***********************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */G/* Source: 26-MAR-2008 16:33:45 $1$DGA8345:[LIB_H.SRC]SHADDEF.SDL;1 *//********************************************************************************************************************************/$/*** MODULE $SHADDEF IDENT X-72 ***/#ifndef __SHADDEF_LOADED#define __SHADDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-StacMndard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#ddMefine __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* VOLUME SHADOWING STRUCTURE DEFINITIONS */N/*-- eM */N/* Minimum number of devices */#define SHAD$K_MINDEVS 1#define SHAD$C_MINDEVS 1N/* Minimum number of members */#define SHAD$K_MINMBRS 1#define SHAD$C_MINMBRS 1N/* Maximum number of members in this version */#define SHAD$K_MAXMBRS 3#define SHAD$C_MAXMBRS 3N/* Duplicate the above */N/* fM for SDL local purposes */N/* Maximum number of members in this version */#define SHAD$K_XMAXMBRS 16#define SHAD$C_XMAXMBRS 16N/* Duplicate the above */N/* for SDL local purposes */N/* */#define SHAD$K_MBRSIZ 16#define SHAD$C_MBRSIZ 16N gM/* Number of seconds to wait between identical messages */#define SHAD$K_MSGWAIT 60#define SHAD$C_MSGWAIT 60N/* Number of I/Os to wait before blasting out an UPDATE_THRESHOLD */#define SHAD$K_UPDATE_IO 10#define SHAD$C_UPDATE_IO 10N/* Number of seconds to wait before blasting out an UPDATE_THRESHOLD */#define SHAD$K_UPDATE_S 2#define SHAD$C_UPDATE_S 2N/* Number of seconds to retry merge signal locking protocol */#define SHAD$K hM_MRGSIG_RETRY 100#define SHAD$C_MRGSIG_RETRY 100N/* */N/* For SHD_INIT use. */N/* */N/* $SET specified value for V.U. and the the members */#define SHADIO$K_TIMEOUT 11181#define SHADIO$C_TIMEOUT 11181N/* $SET specified value for the Virtual Unit iM */ #define SHADIO$K_WLG_STATE 43962 #define SHADIO$C_WLG_STATE 43962N/* $SET specified value intended for the Fibre Channel devices */!#define SHADIO$K_SITE_VALUE 44252!#define SHADIO$C_SITE_VALUE 44252N/* $SET specified value for Read Bias */#define SHADIO$K_READ_BIAS 142#define SHADIO$C_READ_BIAS 142N/* N.B. 143 through 147 are in use, see SHD_INIT module. */N/* $SET specified value for ODS5 VU jM */#define SHADIO$K_ODS5_VU 242#define SHADIO$C_ODS5_VU 242N/* $SET specified value for Force Removal */!#define SHADIO$K_FORCE_REMOVE 342!#define SHADIO$C_FORCE_REMOVE 342P/* $SET specified value for making a mix of DECram and non-DECram - VOLATILE */#define SHADIO$K_VOLATILE 442#define SHADIO$C_VOLATILE 442d/* $SET specified value for forcing copy operation to use master or specific member for read I/O */ #define SHADIO$K kM_COPY_SOURCE 542 #define SHADIO$C_COPY_SOURCE 542N/* */#define SHADIO$K_ABORT_VU 642#define SHADIO$C_ABORT_VU 642N/* */#define SHADIO$K_USE_NCA 742#define SHADIO$C_USE_NCA 742N/* */#define SHADIO$K_LOCAL_DCD 842#define SHADIO$C_LOCAL_DCD 842N/* lM */#define SHADIO$K_REMOTE_DCD 942#define SHADIO$C_REMOTE_DCD 942N/* */$#define SHADIO$K_THRESHOLD_BIAS 1042$#define SHADIO$C_THRESHOLD_BIAS 1042N/* */'#define SHADIO$K_THRESHOLD_SECONDS 1142'#define SHADIO$C_THRESHOLD_SECONDS 1142N/* mM */(#define SHADIO$K_THRESHOLD_IO_COUNT 1242(#define SHADIO$C_THRESHOLD_IO_COUNT 1242N/* */'#define SHADIO$K_STOP_MERGE_AT_LBN 1342'#define SHADIO$C_STOP_MERGE_AT_LBN 1342N/* */"#define SHADIO$K_DEMAND_MERGE 1442"#define SHADIO$C_DEMAND_MERGE 1442N/* */$#define SH nMADIO$K_NOSTALL_WRITES 1542$#define SHADIO$C_NOSTALL_WRITES 1542N/* */"#define SHADIO$K_STALL_WRITES 1642"#define SHADIO$C_STALL_WRITES 1642N/* */(#define SHADIO$K_TOGGLE_SPLIT_READS 1742(#define SHADIO$C_TOGGLE_SPLIT_READS 1742N/* */$#define SHADIO$K_UPDATE_SCB_LBA 1842$#defin oMe SHADIO$C_UPDATE_SCB_LBA 1842N/* */ #define SHADIO$K_MOUNT_DONE 1942 #define SHADIO$C_MOUNT_DONE 1942N/* */"#define SHADIO$K_LOAD_TRPRINT 2042"#define SHADIO$C_LOAD_TRPRINT 2042N/* $SET specified value for V.U. and the the members */#define SHADIO$K_FCODE_21 2142#define SHADIO$C_FCODE_21 2142N/* pM */!#define SHADIO$K_QTV_TESTING 2242!#define SHADIO$C_QTV_TESTING 2242N/* */!#define SHADIO$K_DSA_TRPRINT 2342!#define SHADIO$C_DSA_TRPRINT 2342N/* */%#define SHADIO$K_VUCHAR_SL2_HBMM 2442%#define SHADIO$C_VUCHAR_SL2_HBMM 2442N/* qM */#define SHADIO$K_FCODE_25 2542#define SHADIO$C_FCODE_25 2542N/* */'#define SHADIO$K_VU_PRIORITY_LEVEL 2642'#define SHADIO$C_VU_PRIORITY_LEVEL 2642N/* */#define SHADIO$K_VU_DELAY 2742#define SHADIO$C_VU_DELAY 2742N/* */(#define SHADIO$K_EVALUATE_RESOURCES 2842(#def rMine SHADIO$C_EVALUATE_RESOURCES 2842N/* */(#define SHADIO$K_SRVED_PATH_SSM_DLY 2942(#define SHADIO$C_SRVED_PATH_SSM_DLY 2942N/* */,#define SHADIO$K_SRVED_PATH_SSM_DLY_ALL 3042,#define SHADIO$C_SRVED_PATH_SSM_DLY_ALL 3042N/* */&#define SHADIO$K_VUCHAR_SL2_AMCVP 3142&#define SHAD sMIO$C_VUCHAR_SL2_AMCVP 3142$#define SHADIO$K_RESET_COUNTERS 3242$#define SHADIO$C_RESET_COUNTERS 3242#define SHADIO$K_FCODE_33 3342#define SHADIO$C_FCODE_33 3342)#define SHADIO$K_VUCHAR_SL2_HBMM_DMT 3442)#define SHADIO$C_VUCHAR_SL2_HBMM_DMT 3442&#define SHADIO$K_VUCHAR_SL2_XMBRS 3542&#define SHADIO$C_VUCHAR_SL2_XMBRS 3542N#define SH$C_TRANSIENT_STATE_MIGRATION 268435522 /* 10000042 */N#define SH$C_DSC_RECOVERY_PENDING 66 /* 00000042 */N#define SH tM$C_SEARCH_FOR_MM_VU 16962 /* 00004242 */N#define SH$C_SEARCH_FOR_ANY_VU 4342338 /* 00424242 */ #define SH$C_PLAY_IT_AGAIN_SAM 8 #define SH$C_PLAY_IT_ONCE_SAM 16N/* */#define SHADIO$K_TRACE_1 4201#define SHADIO$C_TRACE_1 4201N/* */#define SHADIO$K_TRACE_2 4202#define SHADIO$C_TRACE_2 4202N uM/* */#define SHADIO$K_TRACE_3 4203#define SHADIO$C_TRACE_3 4203N/* */#define SHADIO$K_TRACE_4 4204#define SHADIO$C_TRACE_4 4204N/* */#define SHADIO$K_TRACE_5 4205#define SHADIO$C_TRACE_5 4205N/* vM */#define SHADIO$K_TRACE_6 4206#define SHADIO$C_TRACE_6 4206N/* */#define SHADIO$K_TRACE_7 4207#define SHADIO$C_TRACE_7 4207N/* */#define SHADIO$K_TRACE_8 4208#define SHADIO$C_TRACE_8 4208N/* */#define SHADIO$K_TRACE_9 4209#define SHADIO$C_TRACE_9 4209N/* N wMumber of bits in the member status */N/* fields used to determine copy type */N/* CLU$C_MAX_NODES */ N/* For Alpha */#define LOCK$M_DEQUEUE 0x1#define LOCK$M_WATCHER 0x2#define LOCK$M_VALUE_UPDATE 0x4"#define LOCK$M_MBR_CHANGE_HERE 0x8#define LOCK$M_COPY_ACTIVE 0x10#define LOCK$M_STALL 0x20xM#define LOCK$M_STALL_IP 0x40#define LOCK$M_LOCAL 0x80(#define LOCK$M_RELEASE_COPIER_LOCK 0x100 #define LOCK$M_WATCHR_DONE 0x200!#define LOCK$M_SSM_EXPELLED 0x400#define LOCK$M_BIT11 0x800#define LOCK$M_BIT12 0x1000)#define LOCK$M_WLG_FINI_RTN_NORMAL 0x2000*#define LOCK$M_HBMM_FINI_RTN_NORMAL 0x4000#define LOCK$M_SKIP 0x8000/#define LOCK$M_OPTIMAL_HBMM_DELAY_DUE 0x1000000#define LOCK$M_BIT25 0x2000000-#define LOCK$M_COPIER_LOCK_RELEASED 0x4000000)#define LOCK$M_DCL_DEMAND_MERG yME 0x80000000#define LOCK$M_REQUEST_VUCHAR_INQUIRY 0x100000002#define LOCK$M_TRANSIENT_SET_DISMOUNTED 0x200000001#define LOCK$M_EVALUATE_PRIORITY_QUEUE 0x40000000.#define LOCK$M_MERGE_SIGNAL_REQUEST 0x80000000N#define LOCK$K_LENGTH 136 /*Length of Structure */N#define LOCK$C_LENGTH 136 /*Length of Structure */  9#ifdef __cplusplus /* Define structure prototypes */ struct _shad; struct _ctxb; #endif /* #ifdef __cplusplus zM*/ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _lock {N/* Lock substructure */#pragma __nomember_alignmentN unsigned char lock$b_resnam_str [32]; /* Resource name string */N unsigned __int64 lock$q_resnam; /* Resource name descriptor */N unsigned i{Mnt lock$l_flink; /* CDRP queue Forward link */N unsigned int lock$l_blink; /* CDRP Queue Backward link */N unsigned int lock$l_blkadr; /* Blocking address for function */N unsigned int lock$l_lksb; /* Lock status block base */N unsigned int lock$l_lkid; /* Lock ID */N unsigned int lock$l_lkvalblk [16]; /* Lock value block */ __union {N unsigned int loc |Mk$l_lock_state; /* */N unsigned char lock$b_state; /* Lock state semaphore */$ } lock$r_lock_state_overlay;X struct _shad *lock$l_shad; /* Points to the shad for this lock structure */ __union {N struct _ctxb *lock$l_ctxb; /* Pointer to context block */ __struct {N unsigned lock$v_dequeue : 1; /* DEQUEUE in progress */N unsigned lock$v_watcher : 1; /* }MWatcher node */N unsigned lock$v_value_update : 1; /* Watcher value update node */N unsigned lock$v_mbr_change_here : 1; /* Set change in progress */N unsigned lock$v_copy_active : 1; /* EX mode on copier lock */N unsigned lock$v_stall : 1; /* Lock does stalls */N unsigned lock$v_stall_ip : 1; /* Stall new requests until NL */N unsigned lock$v_local : 1; /* Local validation in progres~Ms */N/* */z unsigned lock$v_release_copier_lock : 1; /* Causes merge or copy thread to return _CANCEL to Shadow Server */N/* which will release the COPIER lock on this system */N unsigned lock$v_watchr_done : 1; /* */N unsigned lock$v_ssm_expelled : 1; /*( %X00000400 ) */N unsigned lock$v_bit11 : 1; /*( %X000008M00 ) */N unsigned lock$v_bit12 : 1; /*( %X00001000 ) */ unsigned lock$v_wlg_fini_rtn_normal : 1; /*( %X00002000 ) Causes thread to return mini merge state,,SS$_NORMAL to Shado\ w Server */N/* which will release the _COPIER lock on this system */ unsigned lock$v_hbmm_fini_rtn_normal : 1; /*( %X00004000 ) Causes thread to return mini merge state,,SS$_NORMAL to Shad\ ow Server */N/* which will releaMse the _COPIER lock on this system */R unsigned lock$v_skip : 1; /*( %X00008000 ) Skip tracing this lock */r unsigned lock$v_count_do_not_use : 8; /* Used to trace number of times a lock has called grant_lock */N unsigned lock$v_optimal_hbmm_delay_due : 1; /*( %X01000000 ) */N unsigned lock$v_bit25 : 1; /*( %X02000000 ) */j unsigned lock$v_copier_lock_released : 1; /* Tell other nodes copier lock Mhas been released */l unsigned lock$v_dcl_demand_merge : 1; /* User requests a demand merge be done on a shadowset */i unsigned lock$v_request_vuchar_inquiry : 1; /* See if requested characteristic is possible */ unsigned lock$v_transient_set_dismounted : 1; /* Used by a system that is managing a VU in a transient state to */N/* notify other systems that they are DISMOUNTing it */z unsigned lock$v_evaluate_priority_queue : 1; M /* Used by systems when they need to manage the priority queue */u unsigned lock$v_merge_signal_request : 1; /* Used by merge signal to request a VU be put into a merge */N/* transient state ... when they abort a VU */% } lock$r_lock_state_bits; } lock$r_state_overlay; } LOCK; #if !defined(__VAXC)E#define lock$l_lock_state lock$r_lock_state_overlay.lock$l_lock_state;#define lock$b_state lock$r_lock_state_overlay.lock$Mb_state4#define lock$l_ctxb lock$r_state_overlay.lock$l_ctxbQ#define lock$v_dequeue lock$r_state_overlay.lock$r_lock_state_bits.lock$v_dequeueQ#define lock$v_watcher lock$r_state_overlay.lock$r_lock_state_bits.lock$v_watcher[#define lock$v_value_update lock$r_state_overlay.lock$r_lock_state_bits.lock$v_value_updatea#define lock$v_mbr_change_here lock$r_state_overlay.lock$r_lock_state_bits.lock$v_mbr_change_hereY#define lock$v_copy_active lock$r_state_overlay.lock$r_lock_state_bits.lock$v_coMpy_activeM#define lock$v_stall lock$r_state_overlay.lock$r_lock_state_bits.lock$v_stallS#define lock$v_stall_ip lock$r_state_overlay.lock$r_lock_state_bits.lock$v_stall_ipM#define lock$v_local lock$r_state_overlay.lock$r_lock_state_bits.lock$v_locali#define lock$v_release_copier_lock lock$r_state_overlay.lock$r_lock_state_bits.lock$v_release_copier_lockY#define lock$v_watchr_done lock$r_state_overlay.lock$r_lock_state_bits.lock$v_watchr_done[#define lock$v_ssm_expelled lock$r_state_overlayM.lock$r_lock_state_bits.lock$v_ssm_expelledM#define lock$v_bit11 lock$r_state_overlay.lock$r_lock_state_bits.lock$v_bit11M#define lock$v_bit12 lock$r_state_overlay.lock$r_lock_state_bits.lock$v_bit12i#define lock$v_wlg_fini_rtn_normal lock$r_state_overlay.lock$r_lock_state_bits.lock$v_wlg_fini_rtn_normalk#define lock$v_hbmm_fini_rtn_normal lock$r_state_overlay.lock$r_lock_state_bits.lock$v_hbmm_fini_rtn_normalK#define lock$v_skip lock$r_state_overlay.lock$r_lock_state_bits.lock$v_skipo#defMine lock$v_optimal_hbmm_delay_due lock$r_state_overlay.lock$r_lock_state_bits.lock$v_optimal_hbmm_delay_dueM#define lock$v_bit25 lock$r_state_overlay.lock$r_lock_state_bits.lock$v_bit25k#define lock$v_copier_lock_released lock$r_state_overlay.lock$r_lock_state_bits.lock$v_copier_lock_releasedc#define lock$v_dcl_demand_merge lock$r_state_overlay.lock$r_lock_state_bits.lock$v_dcl_demand_mergeo#define lock$v_request_vuchar_inquiry lock$r_state_overlay.lock$r_lock_state_bits.lock$v_request_vuchar_Minquirys#define lock$v_transient_set_dismounted lock$r_state_overlay.lock$r_lock_state_bits.lock$v_transient_set_dismountedq#define lock$v_evaluate_priority_queue lock$r_state_overlay.lock$r_lock_state_bits.lock$v_evaluate_priority_queuek#define lock$v_merge_signal_request lock$r_state_overlay.lock$r_lock_state_bits.lock$v_merge_signal_request"#endif /* #if !defined(__VAXC) */ N/* For Alpha */##define SH$M_SHADOW_SYSTEM_DISK M0x1'#define SH$M_MINI_MERGE_SYSTEM_DISK 0x2(#define SH$M_HOST_COMPARE_ALL_WRITES 0x4#define SH$M_IF_3_IS_SET 0x8#define SH$M_IF_4_IS_SET 0x10#define SH$M_IF_5_IS_SET 0x20#define SH$M_IF_6_IS_SET 0x40#define SH$M_IF_7_IS_SET 0x80#define SH$M_IF_8_IS_SET 0x100#define SH$M_IF_9_IS_SET 0x200#define SH$M_IF_10_IS_SET 0x400%#define SH$M_SYSGEN_DISABLE_WLG 0x800)#define SH$M_MINIMERGE_SYSTEM_DISK 0x1000)#define SH$M_NO_BAD_BLOCK_RECOVERY 0x2000!#define SH$M_ENABLE_LOG_IT 0x400M0%#define SH$M_SET_INHIBIT_RETRY 0x8000'#define SH$M_ENFORCE_LOCAL_READ 0x10000%#define SH$M_DONOT_ENFORCE_MC 0x20000)#define SH$M_ENABLE_HBVSTRACE_ALL 0x40000'#define SH$M_USE_VU_UNIT_NUMBER 0x80000#define SH$M_BIT20 0x100000#define SH$M_BIT21 0x200000#define SH$M_BIT22 0x400000#define SH$M_BIT23 0x800000##define SH$M_IF_24_IS_SET 0x1000000##define SH$M_IF_25_IS_SET 0x2000000%#define SH$M_BUGCHECK_ABORT 0x4000000)#define SH$M_BUGCHECK_INCSHAMEM 0x8000000-#define SH$M_BMUGCHECK_IF_28_IS_SET 0x10000000-#define SH$M_BUGCHECK_IF_29_IS_SET 0x20000000)#define SH$M_BUGCHECK_ABORT_VP 0x40000000*#define SH$M_BUGCHECK_NEG_RWAIT 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _sysdisk {N/* SHADOW_SYS_DISK Bit Mask definitions */#pragma __nomember_alignment M__union {+ unsigned int sh$l_system_disk_mask; __struct {] unsigned sh$v_shadow_system_disk : 1; /* ( %X00000001 ) The historical request */m unsigned sh$v_mini_merge_system_disk : 1; /* ( %X00000002 ) DOSD makes this possible new bit */b unsigned sh$v_host_compare_all_writes : 1; /* ( %X00000004 ) for the truly paranoid */N unsigned sh$v_if_3_is_set : 1; /* ( %X00000008 ) */N unsigned sh$v_if_4_is_set M: 1; /* ( %X00000010 ) */N unsigned sh$v_if_5_is_set : 1; /* ( %X00000020 ) */N unsigned sh$v_if_6_is_set : 1; /* ( %X00000040 ) */N unsigned sh$v_if_7_is_set : 1; /* ( %X00000080 ) */N unsigned sh$v_if_8_is_set : 1; /* ( %X00000100 ) */C unsigned sh$v_if_9_is_set : 1; /* ( %X00000200 ) */N unsigned sh$v_if_10_is_set : 1; /* ( %X00000400 ) M */y unsigned sh$v_sysgen_disable_wlg : 1; /* ( %X00000800 ) Don't allow phase 1 write logging on this system */C/* The next three bits MUST maintain these positions */B/* to maintain historical definitions */v unsigned sh$v_minimerge_system_disk : 1; /* ( %X00001000 ) DOSD makes this possible ... historical bit */d unsigned sh$v_no_bad_block_recovery : 1; /* ( %X00002000 ) Aggressive member removal */W unsiMgned sh$v_enable_log_it : 1; /* ( %X00004000 ) Enable LOG_IT macro */c unsigned sh$v_set_inhibit_retry : 1; /* ( %X00008000 ) For special application I/Os */l unsigned sh$v_enforce_local_read : 1; /* ( %X00010000 ) Force local reads, for FDDI clusters */N unsigned sh$v_donot_enforce_mc : 1; /* ( %X00020000 ) */N unsigned sh$v_enable_hbvstrace_all : 1; /* ( %X00040000 ) */N unsigned sh$v_use_vu_unit_number : 1; /* ( %X000M80000 ) */N unsigned sh$v_bit20 : 1; /* ( %X00100000 ) */N unsigned sh$v_bit21 : 1; /* ( %X00200000 ) */N unsigned sh$v_bit22 : 1; /* ( %X00400000 ) */N unsigned sh$v_bit23 : 1; /* ( %X00800000 ) */N unsigned sh$v_if_24_is_set : 1; /* ( %X01000000 ) */N unsigned sh$v_if_25_is_set : 1; /* ( %X02000000 ) */Z M unsigned sh$v_bugcheck_abort : 1; /* ( %X04000000 ) On ss$_abort crash now */N unsigned sh$v_bugcheck_incshamem : 1; /* ( %X08000000 ) */N unsigned sh$v_bugcheck_if_28_is_set : 1; /* ( %X10000000 ) */N unsigned sh$v_bugcheck_if_29_is_set : 1; /* ( %X20000000 ) */\ unsigned sh$v_bugcheck_abort_vp : 1; /* ( %X40000000 ) On ABORT_VP crash now */l unsigned sh$v_bugcheck_neg_rwait : 1; /* ( %X80000000 ) If RWAITCNT goes n Megative, crash now */) } sh$r_system_disk_mask_bits;( } sh$r_system_disk_mask_overlay; } SYSDISK; #if !defined(__VAXC)Q#define sh$l_system_disk_mask sh$r_system_disk_mask_overlay.sh$l_system_disk_maskp#define sh$v_shadow_system_disk sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_shadow_system_diskx#define sh$v_mini_merge_system_disk sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_mini_merge_system_diskz#define sh$v_host_compare_all_writMes sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_host_compare_all_writesb#define sh$v_if_3_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_if_3_is_setb#define sh$v_if_4_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_if_4_is_setb#define sh$v_if_5_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_if_5_is_setb#define sh$v_if_6_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_if_6_is_setb#define sh$v_if_M7_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_if_7_is_setb#define sh$v_if_8_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_if_8_is_setb#define sh$v_if_9_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_if_9_is_setd#define sh$v_if_10_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_if_10_is_setp#define sh$v_sysgen_disable_wlg sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_sysgen_disable_wlgv#definMe sh$v_minimerge_system_disk sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_minimerge_system_diskv#define sh$v_no_bad_block_recovery sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_no_bad_block_recoveryf#define sh$v_enable_log_it sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_enable_log_itn#define sh$v_set_inhibit_retry sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_set_inhibit_retryp#define sh$v_enforce_local_read sh$r_system_disk_mask_ovMerlay.sh$r_system_disk_mask_bits.sh$v_enforce_local_readl#define sh$v_donot_enforce_mc sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_donot_enforce_mct#define sh$v_enable_hbvstrace_all sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_enable_hbvstrace_allp#define sh$v_use_vu_unit_number sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_use_vu_unit_numberV#define sh$v_bit20 sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_bit20V#define sh$v_bit21M sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_bit21V#define sh$v_bit22 sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_bit22V#define sh$v_bit23 sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_bit23d#define sh$v_if_24_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_if_24_is_setd#define sh$v_if_25_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_if_25_is_seth#define sh$v_bugcheck_abort sh$r_system_disk_mask_overlaMy.sh$r_system_disk_mask_bits.sh$v_bugcheck_abortp#define sh$v_bugcheck_incshamem sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_bugcheck_incshamemv#define sh$v_bugcheck_if_28_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_bugcheck_if_28_is_setv#define sh$v_bugcheck_if_29_is_set sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_bugcheck_if_29_is_setn#define sh$v_bugcheck_abort_vp sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_bugcheck_ Mabort_vpp#define sh$v_bugcheck_neg_rwait sh$r_system_disk_mask_overlay.sh$r_system_disk_mask_bits.sh$v_bugcheck_neg_rwait"#endif /* #if !defined(__VAXC) */ N/* */N/* Shadow set VU characteristics ($VUCHAR) lock value block definitions */N/* */O/* Each set bit represents a per-VU characteristic that is currently enabled */N/* on that VU. A cluMster member is not allowed to MOUNT a VU unless it has */N/* support for all the currently enabled characteristics on that VU. */N/* The mask of characteristics that are supported by this node is in */N/* EXE$GQ_SHADOW_CAPABILITIES. */N/* */N/* Any change in the enabled VU characteristics on a mounted VU requires */R/* unanimous consent of all the nodes where thMe VU is mounted. This is obtained */N/* using the VU characteristics voting protocol. */N/* */N/* NOTE: Prior versions used the SHMASK$M_MINI_COPY, DVE_DDS, and HBMM bit */R/* masks to set the VU characteristics lock value block. Therefore, to maintain */N/* cluster compatibility, the definitions of each of the corresponding */N/* SHAD_VUCHAR$M_ bits must have the same value. M */N/* */*#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT0 0x1*#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT1 0x2*#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT2 0x4*#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT3 0x8$#define SHAD_VUCHAR$M_MINI_COPY 0x10+#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT5 0x20"#define SHAD_VUCHAR$M_DVE_DDS 0x40+#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT7 0x80 #define SHAD_VUCHAR$M_HBMM 0x100,#define SHAD_VUCHAR$M_SHADOW_CHAR_ MBIT9 0x200!#define SHAD_VUCHAR$M_AMCVP 0x400-#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT11 0x800.#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT12 0x1000.#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT13 0x2000%#define SHAD_VUCHAR$M_HBMM_DMT 0x4000+#define SHAD_VUCHAR$M_VERIFY_NEW_MBR 0x8000##define SHAD_VUCHAR$M_XMBRS 0x10000/#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT17 0x20000/#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT18 0x40000/#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT19 0x800000#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT20 M0x1000000#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT21 0x2000000#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT22 0x4000000#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT23 0x8000001#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT24 0x10000001#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT25 0x20000001#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT26 0x40000001#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT27 0x80000002#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT28 0x100000002#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT29 0x200000002#define SHAD_VUCHAR$M_SHADOW_CHAR_MBIT30 0x400000002#define SHAD_VUCHAR$M_SHADOW_CHAR_BIT31 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _shad_vuchar {#pragma __nomember_alignment __union {[ unsigned int shad_vuchar$l_shadow_char_mask; /* SHADOW_CHAR Bit Mask definitions */ __struct {N unsigned shad_vuchar$v_shadow_char_bMit0 : 1; /* ( %X00000001 ) */N unsigned shad_vuchar$v_shadow_char_bit1 : 1; /* ( %X00000002 ) */N unsigned shad_vuchar$v_shadow_char_bit2 : 1; /* ( %X00000004 ) */N unsigned shad_vuchar$v_shadow_char_bit3 : 1; /* ( %X00000008 ) */N unsigned shad_vuchar$v_mini_copy : 1; /* ( %X00000010 ) */N unsigned shad_vuchar$v_shadow_char_bit5 : 1; /* ( %X00000020 ) */N unsigned shad_vuchar$v_dve_dds : 1; /* ( %X00000040 ) M */N unsigned shad_vuchar$v_shadow_char_bit7 : 1; /* ( %X00000080 ) */N unsigned shad_vuchar$v_hbmm : 1; /* ( %X00000100 ) */N unsigned shad_vuchar$v_shadow_char_bit9 : 1; /* ( %X00000200 ) */N unsigned shad_vuchar$v_amcvp : 1; /* ( %X00000400 ) */N unsigned shad_vuchar$v_shadow_char_bit11 : 1; /* ( %X00000800 ) */N unsigned shad_vuchar$v_shadow_char_bit12 : 1; /* ( %X00001000 ) */N unsignedM shad_vuchar$v_shadow_char_bit13 : 1; /* ( %X00002000 ) */N unsigned shad_vuchar$v_hbmm_dmt : 1; /* ( %X00004000 ) */N unsigned shad_vuchar$v_verify_new_mbr : 1; /* ( %X00008000 ) */N unsigned shad_vuchar$v_xmbrs : 1; /* ( %X00010000 ) */N/* */N/* All of the rest of the character bits may already be used by */N/* SHD_RELEASE_FLAG.MAR - so use these carefulMly! */N/* */O unsigned shad_vuchar$v_shadow_char_bit17 : 1; /* ( %X00020000 ) */O unsigned shad_vuchar$v_shadow_char_bit18 : 1; /* ( %X00040000 ) */O unsigned shad_vuchar$v_shadow_char_bit19 : 1; /* ( %X00080000 ) */O unsigned shad_vuchar$v_shadow_char_bit20 : 1; /* ( %X00100000 ) */O unsigned shad_vuchar$v_shadow_char_bit21 : 1; /* ( %MX00200000 ) */O unsigned shad_vuchar$v_shadow_char_bit22 : 1; /* ( %X00400000 ) */O unsigned shad_vuchar$v_shadow_char_bit23 : 1; /* ( %X00800000 ) */N unsigned shad_vuchar$v_shadow_char_bit24 : 1; /* ( %X01000000 ) */N unsigned shad_vuchar$v_shadow_char_bit25 : 1; /* ( %X02000000 ) */N unsigned shad_vuchar$v_shadow_char_bit26 : 1; /* ( %X04000000 ) */N unsigned shad_vuchar$v_shadow_char_bit27 : 1; /* ( %X08000000 ) */N M unsigned shad_vuchar$v_shadow_char_bit28 : 1; /* ( %X10000000 ) */N unsigned shad_vuchar$v_shadow_char_bit29 : 1; /* ( %X20000000 ) */N unsigned shad_vuchar$v_shadow_char_bit30 : 1; /* ( %X40000000 ) */N unsigned shad_vuchar$v_shadow_char_bit31 : 1; /* ( %X80000000 ) */$ } shad_vuchar$r_fill_1_; } shad_vuchar$r_fill_0_; } SHAD_VUCHAR; #if !defined(__VAXC)[#define shad_vuchar$l_shadow_char_mask shad_vuchar$r_fill_0_.shad_vucharM$l_shadow_char_maskq#define shad_vuchar$v_shadow_char_bit0 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit0q#define shad_vuchar$v_shadow_char_bit1 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit1q#define shad_vuchar$v_shadow_char_bit2 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit2q#define shad_vuchar$v_shadow_char_bit3 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit3c#define shad_vuchar$Mv_mini_copy shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_mini_copyq#define shad_vuchar$v_shadow_char_bit5 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit5_#define shad_vuchar$v_dve_dds shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_dve_ddsq#define shad_vuchar$v_shadow_char_bit7 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit7Y#define shad_vuchar$v_hbmm shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_hbmmq#dMefine shad_vuchar$v_shadow_char_bit9 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit9[#define shad_vuchar$v_amcvp shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_amcvps#define shad_vuchar$v_shadow_char_bit11 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit11s#define shad_vuchar$v_shadow_char_bit12 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit12s#define shad_vuchar$v_shadow_char_bit13 shad_vuchar$r_fill_0_.Mshad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit13a#define shad_vuchar$v_hbmm_dmt shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_hbmm_dmtm#define shad_vuchar$v_verify_new_mbr shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_verify_new_mbr[#define shad_vuchar$v_xmbrs shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_xmbrss#define shad_vuchar$v_shadow_char_bit17 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit17s#define shad_vuchar$v_shadMow_char_bit18 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit18s#define shad_vuchar$v_shadow_char_bit19 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit19s#define shad_vuchar$v_shadow_char_bit20 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit20s#define shad_vuchar$v_shadow_char_bit21 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit21s#define shad_vuchar$v_shadow_char_bit22 shad_vuchar$r_fill_0M_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit22s#define shad_vuchar$v_shadow_char_bit23 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit23s#define shad_vuchar$v_shadow_char_bit24 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit24s#define shad_vuchar$v_shadow_char_bit25 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit25s#define shad_vuchar$v_shadow_char_bit26 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchaMr$v_shadow_char_bit26s#define shad_vuchar$v_shadow_char_bit27 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit27s#define shad_vuchar$v_shadow_char_bit28 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit28s#define shad_vuchar$v_shadow_char_bit29 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit29s#define shad_vuchar$v_shadow_char_bit30 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit30s#define shMad_vuchar$v_shadow_char_bit31 shad_vuchar$r_fill_0_.shad_vuchar$r_fill_1_.shad_vuchar$v_shadow_char_bit31"#endif /* #if !defined(__VAXC) */ N/* For NotVAX */#define SHADD1$M_BIT0 0x1#define SHADD1$M_BIT1 0x2#define SHADD1$M_BIT2 0x4#define SHADD1$M_BIT3 0x8#define SHADD1$M_BIT4 0x10#define SHADD1$M_BIT5 0x20#define SHADD1$M_BIT6 0x40#define SHADD1$M_BIT7 0x80#define SHADD1$M_BIT8 0x100#define SHADD1$M_BIT9 0xM200#define SHADD1$M_BIT10 0x400#define SHADD1$M_BIT11 0x800#define SHADD1$M_BIT12 0x1000#define SHADD1$M_BIT13 0x2000#define SHADD1$M_BIT14 0x4000#define SHADD1$M_BIT15 0x8000'#define SHADD1$M_IF_16_IS_CLEAR 0x10000'#define SHADD1$M_IF_17_IS_CLEAR 0x20000'#define SHADD1$M_IF_18_IS_CLEAR 0x40000'#define SHADD1$M_IF_19_IS_CLEAR 0x80000(#define SHADD1$M_IF_20_IS_CLEAR 0x100000(#define SHADD1$M_IF_21_IS_CLEAR 0x200000(#define SHADD1$M_IF_22_IS_CLEAR 0x400000(#define SHADD1$M_I MF_23_IS_CLEAR 0x800000'#define SHADD1$M_IF_24_IS_SET 0x1000000'#define SHADD1$M_IF_25_IS_SET 0x2000000'#define SHADD1$M_IF_26_IS_SET 0x4000000'#define SHADD1$M_IF_27_IS_SET 0x8000000(#define SHADD1$M_IF_28_IS_SET 0x10000000(#define SHADD1$M_IF_29_IS_SET 0x20000000(#define SHADD1$M_IF_30_IS_SET 0x40000000(#define SHADD1$M_IF_31_IS_SET 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword M#else#pragma __nomember_alignment#endiftypedef struct _shadowd1 {N/* SHADOW_D1 Bit Mask definitions */#pragma __nomember_alignment __union {- unsigned int shadd1$l_shadow_d1_mask; __struct {N unsigned shadd1$v_bit0 : 1; /* ( %X00000001 ) */N unsigned shadd1$v_bit1 : 1; /* ( %X00000002 ) */N unsigned shadd1$v_bit2 : 1; /* ( %X00000004 ) M */N unsigned shadd1$v_bit3 : 1; /* ( %X00000008 ) */N unsigned shadd1$v_bit4 : 1; /* ( %X00000010 ) */N unsigned shadd1$v_bit5 : 1; /* ( %X00000020 ) */N unsigned shadd1$v_bit6 : 1; /* ( %X00000040 ) */N unsigned shadd1$v_bit7 : 1; /* ( %X00000080 ) */N unsigned shadd1$v_bit8 : 1; /* ( %X00000100 ) */N unsignedM shadd1$v_bit9 : 1; /* ( %X00000200 ) */N unsigned shadd1$v_bit10 : 1; /* ( %X00000400 ) */N unsigned shadd1$v_bit11 : 1; /* ( %X00000800 ) */N unsigned shadd1$v_bit12 : 1; /* ( %X00001000 ) */N unsigned shadd1$v_bit13 : 1; /* ( %X00002000 ) */N unsigned shadd1$v_bit14 : 1; /* ( %X00004000 ) */N unsigned shadd1$v_bit15 : 1; /* ( M%X00008000 ) */N unsigned shadd1$v_if_16_is_clear : 1; /* ( %X00010000 ) */N unsigned shadd1$v_if_17_is_clear : 1; /* ( %X00020000 ) */N unsigned shadd1$v_if_18_is_clear : 1; /* ( %X00040000 ) */N unsigned shadd1$v_if_19_is_clear : 1; /* ( %X00080000 ) */N unsigned shadd1$v_if_20_is_clear : 1; /* ( %X00100000 ) */N unsigned shadd1$v_if_21_is_clear : 1; /* ( %X00200000 ) M */N unsigned shadd1$v_if_22_is_clear : 1; /* ( %X00400000 ) */N unsigned shadd1$v_if_23_is_clear : 1; /* ( %X00800000 ) */N unsigned shadd1$v_if_24_is_set : 1; /* ( %X01000000 ) */N unsigned shadd1$v_if_25_is_set : 1; /* ( %X02000000 ) */N unsigned shadd1$v_if_26_is_set : 1; /* ( %X04000000 ) */N unsigned shadd1$v_if_27_is_set : 1; /* ( %X08000000 ) */N unsign Med shadd1$v_if_28_is_set : 1; /* ( %X10000000 ) */N unsigned shadd1$v_if_29_is_set : 1; /* ( %X20000000 ) */N unsigned shadd1$v_if_30_is_set : 1; /* ( %X40000000 ) */N unsigned shadd1$v_if_31_is_set : 1; /* ( %X80000000 ) */* } shadd1$r_shadowd1_mask_bits;) } shadd1$r_shadowd1_mask_overlay; } SHADOWD1; #if !defined(__VAXC)V#define shadd1$l_shadow_d1_mask shadd1$r_shadowd1_mask_overlay.shadd1$l_Mshadow_d1_mask^#define shadd1$v_bit0 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit0^#define shadd1$v_bit1 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit1^#define shadd1$v_bit2 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit2^#define shadd1$v_bit3 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit3^#define shadd1$v_bit4 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit4^#define shMadd1$v_bit5 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit5^#define shadd1$v_bit6 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit6^#define shadd1$v_bit7 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit7^#define shadd1$v_bit8 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit8^#define shadd1$v_bit9 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit9`#define shadd1$v_bit10 shadd1$r_shadMowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit10`#define shadd1$v_bit11 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit11`#define shadd1$v_bit12 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit12`#define shadd1$v_bit13 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit13`#define shadd1$v_bit14 shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_bit14`#define shadd1$v_bit15 shadd1$r_shadowd1_mask_overlaMy.shadd1$r_shadowd1_mask_bits.shadd1$v_bit15r#define shadd1$v_if_16_is_clear shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_16_is_clearr#define shadd1$v_if_17_is_clear shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_17_is_clearr#define shadd1$v_if_18_is_clear shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_18_is_clearr#define shadd1$v_if_19_is_clear shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_19_is_cleMarr#define shadd1$v_if_20_is_clear shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_20_is_clearr#define shadd1$v_if_21_is_clear shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_21_is_clearr#define shadd1$v_if_22_is_clear shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_22_is_clearr#define shadd1$v_if_23_is_clear shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_23_is_clearn#define shadd1$v_if_24_is_set shadd1$rM_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_24_is_setn#define shadd1$v_if_25_is_set shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_25_is_setn#define shadd1$v_if_26_is_set shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_26_is_setn#define shadd1$v_if_27_is_set shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_27_is_setn#define shadd1$v_if_28_is_set shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$ Mv_if_28_is_setn#define shadd1$v_if_29_is_set shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_29_is_setn#define shadd1$v_if_30_is_set shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_30_is_setn#define shadd1$v_if_31_is_set shadd1$r_shadowd1_mask_overlay.shadd1$r_shadowd1_mask_bits.shadd1$v_if_31_is_set"#endif /* #if !defined(__VAXC) */ (#define SHADD5$M_ENABLE_TRACING_BIT0 0x1(#define SHADD5$M_ENABLE_TRACING_BIT1 0x2(#define SHADD5$M_ENABLE_TRACINMG_BIT2 0x4(#define SHADD5$M_ENABLE_TRACING_BIT3 0x8)#define SHADD5$M_ENABLE_TRACING_BIT4 0x10)#define SHADD5$M_ENABLE_TRACING_BIT5 0x20)#define SHADD5$M_ENABLE_TRACING_BIT6 0x40)#define SHADD5$M_ENABLE_TRACING_BIT7 0x80#define SHADD5$M_BIT8 0x100#define SHADD5$M_BIT9 0x200#define SHADD5$M_BIT10 0x400#define SHADD5$M_BIT11 0x800#define SHADD5$M_BIT12 0x1000#define SHADD5$M_BIT13 0x2000#define SHADD5$M_BIT14 0x4000#define SHADD5$M_BIT15 0x8000'#define SHADD5$M_IF_16_IS_CL MEAR 0x10000'#define SHADD5$M_IF_17_IS_CLEAR 0x20000'#define SHADD5$M_IF_18_IS_CLEAR 0x40000'#define SHADD5$M_IF_19_IS_CLEAR 0x80000(#define SHADD5$M_IF_20_IS_CLEAR 0x100000(#define SHADD5$M_IF_21_IS_CLEAR 0x200000(#define SHADD5$M_IF_22_IS_CLEAR 0x400000(#define SHADD5$M_IF_23_IS_CLEAR 0x800000'#define SHADD5$M_IF_24_IS_SET 0x1000000'#define SHADD5$M_IF_25_IS_SET 0x2000000'#define SHADD5$M_IF_26_IS_SET 0x4000000'#define SHADD5$M_IF_27_IS_SET 0x8000000(#define SHADD5$M_IF_28_IS_SET M0x10000000(#define SHADD5$M_IF_29_IS_SET 0x20000000(#define SHADD5$M_IF_30_IS_SET 0x40000000(#define SHADD5$M_IF_31_IS_SET 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _shadowd5 {N/* SHADOW_D5 Bit Mask definitions */#pragma __nomember_alignment __union {- unsigned intM shadd5$l_shadow_d5_mask; __struct {N unsigned shadd5$v_enable_tracing_bit0 : 1; /* ( %X00000001 ) */N unsigned shadd5$v_enable_tracing_bit1 : 1; /* ( %X00000002 ) */N unsigned shadd5$v_enable_tracing_bit2 : 1; /* ( %X00000004 ) */N unsigned shadd5$v_enable_tracing_bit3 : 1; /* ( %X00000008 ) */N unsigned shadd5$v_enable_tracing_bit4 : 1; /* ( %X00000010 ) */N unsigned shadd5$v_enable_tracing_bit5 : 1; /M* ( %X00000020 ) */N unsigned shadd5$v_enable_tracing_bit6 : 1; /* ( %X00000040 ) */N unsigned shadd5$v_enable_tracing_bit7 : 1; /* ( %X00000080 ) */N unsigned shadd5$v_bit8 : 1; /* ( %X00000100 ) */N unsigned shadd5$v_bit9 : 1; /* ( %X00000200 ) */N unsigned shadd5$v_bit10 : 1; /* ( %X00000400 ) */N unsigned shadd5$v_bit11 : 1; /* ( %X00000800 ) */N M unsigned shadd5$v_bit12 : 1; /* ( %X00001000 ) */N unsigned shadd5$v_bit13 : 1; /* ( %X00002000 ) */N unsigned shadd5$v_bit14 : 1; /* ( %X00004000 ) */N unsigned shadd5$v_bit15 : 1; /* ( %X00008000 ) */N unsigned shadd5$v_if_16_is_clear : 1; /* ( %X00010000 ) */N unsigned shadd5$v_if_17_is_clear : 1; /* ( %X00020000 ) */N unsigned shadd5$Mv_if_18_is_clear : 1; /* ( %X00040000 ) */N unsigned shadd5$v_if_19_is_clear : 1; /* ( %X00080000 ) */N unsigned shadd5$v_if_20_is_clear : 1; /* ( %X00100000 ) */N unsigned shadd5$v_if_21_is_clear : 1; /* ( %X00200000 ) */N unsigned shadd5$v_if_22_is_clear : 1; /* ( %X00400000 ) */N unsigned shadd5$v_if_23_is_clear : 1; /* ( %X00800000 ) */N unsigned shadd5$v_if_24_is_set : 1; /* ( %MX01000000 ) */N unsigned shadd5$v_if_25_is_set : 1; /* ( %X02000000 ) */N unsigned shadd5$v_if_26_is_set : 1; /* ( %X04000000 ) */N unsigned shadd5$v_if_27_is_set : 1; /* ( %X08000000 ) */N unsigned shadd5$v_if_28_is_set : 1; /* ( %X10000000 ) */N unsigned shadd5$v_if_29_is_set : 1; /* ( %X20000000 ) */N unsigned shadd5$v_if_30_is_set : 1; /* ( %X40000000 ) */N M unsigned shadd5$v_if_31_is_set : 1; /* ( %X80000000 ) */* } shadd5$r_shadowd5_mask_bits;) } shadd5$r_shadowd5_mask_overlay; } SHADOWD5; #if !defined(__VAXC)V#define shadd5$l_shadow_d5_mask shadd5$r_shadowd5_mask_overlay.shadd5$l_shadow_d5_mask|#define shadd5$v_enable_tracing_bit0 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_enable_tracing_bit0|#define shadd5$v_enable_tracing_bit1 shadd5$r_shadowd5_mask_overlay.shadd5$r_shaMdowd5_mask_bits.shadd5$v_enable_tracing_bit1|#define shadd5$v_enable_tracing_bit2 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_enable_tracing_bit2|#define shadd5$v_enable_tracing_bit3 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_enable_tracing_bit3|#define shadd5$v_enable_tracing_bit4 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_enable_tracing_bit4|#define shadd5$v_enable_tracing_bit5 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadoMwd5_mask_bits.shadd5$v_enable_tracing_bit5|#define shadd5$v_enable_tracing_bit6 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_enable_tracing_bit6|#define shadd5$v_enable_tracing_bit7 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_enable_tracing_bit7^#define shadd5$v_bit8 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_bit8^#define shadd5$v_bit9 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_bit9`#define shadd5$v_bMit10 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_bit10`#define shadd5$v_bit11 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_bit11`#define shadd5$v_bit12 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_bit12`#define shadd5$v_bit13 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_bit13`#define shadd5$v_bit14 shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_bit14`#define shadd5$v_bit15 shadd5$r_shMadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_bit15r#define shadd5$v_if_16_is_clear shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_16_is_clearr#define shadd5$v_if_17_is_clear shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_17_is_clearr#define shadd5$v_if_18_is_clear shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_18_is_clearr#define shadd5$v_if_19_is_clear shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shaMdd5$v_if_19_is_clearr#define shadd5$v_if_20_is_clear shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_20_is_clearr#define shadd5$v_if_21_is_clear shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_21_is_clearr#define shadd5$v_if_22_is_clear shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_22_is_clearr#define shadd5$v_if_23_is_clear shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_23_is_clearn#define shadd5$v_if_M24_is_set shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_24_is_setn#define shadd5$v_if_25_is_set shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_25_is_setn#define shadd5$v_if_26_is_set shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_26_is_setn#define shadd5$v_if_27_is_set shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_27_is_setn#define shadd5$v_if_28_is_set shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5 M_mask_bits.shadd5$v_if_28_is_setn#define shadd5$v_if_29_is_set shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_29_is_setn#define shadd5$v_if_30_is_set shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_30_is_setn#define shadd5$v_if_31_is_set shadd5$r_shadowd5_mask_overlay.shadd5$r_shadowd5_mask_bits.shadd5$v_if_31_is_set"#endif /* #if !defined(__VAXC) */ )#define SHADEN$M_NEW_WBM_NAMES_IN_USE 0x1#define SHADEN$M_BIT1 0x2#define SHADEN$M_BIT2 0xM4#define SHADEN$M_BIT3 0x8#define SHADEN$M_BIT4 0x10#define SHADEN$M_BIT5 0x20#define SHADEN$M_BIT6 0x40#define SHADEN$M_BIT7 0x80#define SHADEN$M_BIT8 0x100#define SHADEN$M_BIT9 0x200#define SHADEN$M_BIT10 0x400#define SHADEN$M_BIT11 0x800#define SHADEN$M_BIT12 0x1000#define SHADEN$M_BIT13 0x2000#define SHADEN$M_BIT14 0x4000#define SHADEN$M_BIT15 0x8000#define SHADEN$M_BIT16 0x10000#define SHADEN$M_BIT17 0x20000#define SHADEN$M_BIT18 0x40000#define SHADEN$M_BMIT19 0x80000#define SHADEN$M_BIT20 0x100000#define SHADEN$M_BIT21 0x200000#define SHADEN$M_BIT22 0x400000#define SHADEN$M_BIT23 0x800000 #define SHADEN$M_BIT24 0x1000000 #define SHADEN$M_BIT25 0x2000000 #define SHADEN$M_BIT26 0x4000000 #define SHADEN$M_BIT27 0x8000000!#define SHADEN$M_BIT28 0x10000000!#define SHADEN$M_BIT29 0x20000000!#define SHADEN$M_BIT30 0x40000000!#define SHADEN$M_BIT31 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If usMing pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _shadowen {N/* SHADOW_ENABLE Bit Mask definitions */#pragma __nomember_alignment __union {- unsigned int shaden$l_shadow_en_mask; __struct {N unsigned shaden$v_new_wbm_names_in_use : 1; /* ( %X00000001 ) */N unsigned shaden$v_bit1 : 1; /* ( %X00000002 ) */N M unsigned shaden$v_bit2 : 1; /* ( %X00000004 ) */N unsigned shaden$v_bit3 : 1; /* ( %X00000008 ) */N unsigned shaden$v_bit4 : 1; /* ( %X00000010 ) */N unsigned shaden$v_bit5 : 1; /* ( %X00000020 ) */N unsigned shaden$v_bit6 : 1; /* ( %X00000040 ) */N unsigned shaden$v_bit7 : 1; /* ( %X00000080 ) */N unsigned shaden$v_Mbit8 : 1; /* ( %X00000100 ) */N unsigned shaden$v_bit9 : 1; /* ( %X00000200 ) */N unsigned shaden$v_bit10 : 1; /* ( %X00000400 ) */N unsigned shaden$v_bit11 : 1; /* ( %X00000800 ) */N unsigned shaden$v_bit12 : 1; /* ( %X00001000 ) */N unsigned shaden$v_bit13 : 1; /* ( %X00002000 ) */N unsigned shaden$v_bit14 : 1; /* ( %X00004000M ) */N unsigned shaden$v_bit15 : 1; /* ( %X00008000 ) */N unsigned shaden$v_bit16 : 1; /* ( %X00010000 ) */N unsigned shaden$v_bit17 : 1; /* ( %X00020000 ) */N unsigned shaden$v_bit18 : 1; /* ( %X00040000 ) */N unsigned shaden$v_bit19 : 1; /* ( %X00080000 ) */N unsigned shaden$v_bit20 : 1; /* ( %X00100000 ) */N M unsigned shaden$v_bit21 : 1; /* ( %X00200000 ) */N unsigned shaden$v_bit22 : 1; /* ( %X00400000 ) */N unsigned shaden$v_bit23 : 1; /* ( %X00800000 ) */N unsigned shaden$v_bit24 : 1; /* ( %X01000000 ) */N unsigned shaden$v_bit25 : 1; /* ( %X02000000 ) */N unsigned shaden$v_bit26 : 1; /* ( %X04000000 ) */N unsigned shaden$ Mv_bit27 : 1; /* ( %X08000000 ) */N unsigned shaden$v_bit28 : 1; /* ( %X10000000 ) */N unsigned shaden$v_bit29 : 1; /* ( %X20000000 ) */N unsigned shaden$v_bit30 : 1; /* ( %X40000000 ) */N unsigned shaden$v_bit31 : 1; /* ( %X80000000 ) */* } shaden$r_shadowen_mask_bits;) } shaden$r_shadowen_mask_overlay; } SHADOWEN; #if !defined(__VAXC)V#dMefine shaden$l_shadow_en_mask shaden$r_shadowen_mask_overlay.shaden$l_shadow_en_mask~#define shaden$v_new_wbm_names_in_use shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_new_wbm_names_in_use^#define shaden$v_bit1 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit1^#define shaden$v_bit2 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit2^#define shaden$v_bit3 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit3^#defMine shaden$v_bit4 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit4^#define shaden$v_bit5 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit5^#define shaden$v_bit6 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit6^#define shaden$v_bit7 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit7^#define shaden$v_bit8 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit8^#define shaden$v_bit9 shaden$rM_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit9`#define shaden$v_bit10 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit10`#define shaden$v_bit11 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit11`#define shaden$v_bit12 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit12`#define shaden$v_bit13 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit13`#define shaden$v_bit14 shaden$r_shadowen_mask_ovMerlay.shaden$r_shadowen_mask_bits.shaden$v_bit14`#define shaden$v_bit15 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit15`#define shaden$v_bit16 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit16`#define shaden$v_bit17 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit17`#define shaden$v_bit18 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit18`#define shaden$v_bit19 shaden$r_shadowen_mask_overlay.shaden$r_sMhadowen_mask_bits.shaden$v_bit19`#define shaden$v_bit20 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit20`#define shaden$v_bit21 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit21`#define shaden$v_bit22 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit22`#define shaden$v_bit23 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit23`#define shaden$v_bit24 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bitMs.shaden$v_bit24`#define shaden$v_bit25 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit25`#define shaden$v_bit26 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit26`#define shaden$v_bit27 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit27`#define shaden$v_bit28 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit28`#define shaden$v_bit29 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit29 M`#define shaden$v_bit30 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit30`#define shaden$v_bit31 shaden$r_shadowen_mask_overlay.shaden$r_shadowen_mask_bits.shaden$v_bit31"#endif /* #if !defined(__VAXC) */ N/* For Alpha */#define MC_WBM$C_HEADER 12#define MC_WBM$C_DDS_SIZE 27#define MC_WBM$C_I_LIST_BFR 128##define MC_WBM$C_CONVERT_BUFFER 256N#define MC_WBM$K_LENGTH 512 /*Length of Struct Mure */N#define MC_WBM$C_LENGTH 512 /*Length of Structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _mcwbm {#pragma __nomember_alignmentN unsigned int mc_wbm$l_flink; /* Forward link FIELD */N unsigned int mc_wbm$l_blink; /* Backward link FIELD M */N unsigned int mc_wbm$l_size_type; /* Size/Type of structure */N/* */N/* Name of buffer as derived from the SCB meta data. */N/* */N unsigned int mc_wbm$l_dds; /* Size of string passed here */Q unsigned int mc_wbm$l_addr_of_string; /* Address of the string passed here */N unsigned chaMr mc_wbm$b_the_string; /* */N unsigned int mc_wbm$l_string_prefix; /* */N unsigned int mc_wbm$l_scb_string; /* */N char mc_wbm$b_reserved_scb_buf [99]; /* Reserved for alignment */N/* */N/* Item List buffer. */N/* M */N unsigned int mc_wbm$l_flink1; /* Forward link FIELD */N unsigned int mc_wbm$l_blink1; /* Backward link FIELD */N unsigned int mc_wbm$l_size_type1; /* Size/Type of structure */N unsigned short int mc_wbm$w_item_list_bfr_size; /* In number of Bytes */N unsigned short int mc_wbm$w_item_list_arg; /* #3 returns the handle */T unsigned int mc_wbm$l_addr_of_item_list; /* Address of the buffeMr passed here */N unsigned int mc_wbm$l_addr_of_bcnt_rtn; /* */N unsigned int mc_wbm$l_end_of_item_list; /* */N unsigned int mc_wbm$l_item_list_bcnt_rtn; /* */N unsigned int mc_wbm$l_item_list; /* */N char mc_wbm$b_reserved_item_list [92]; /* reserved */N/* */N/* ConveMrt Device Name */N/* */N unsigned int mc_wbm$l_flink2; /* Forward link FIELD */N unsigned int mc_wbm$l_blink2; /* Backward link FIELD */N unsigned int mc_wbm$l_size_type2; /* Size/Type of structure */_ unsigned short int mc_wbm$w_convert_bfr_size; /* Descriptor data size in number of Bytes */N unsigned sho Mrt int mc_wbm$w_convert_type; /* */N unsigned int mc_wbm$l_convert_ptr; /* */N unsigned int mc_wbm$l_convert_bfr; /* 24 Bytes */N char mc_wbm$b_convert [232]; /* reserved */ } MCWBM;N/* For Alpha */#define SHADIO$M_FCODE 0xFFFF&#define SHADIO$M_FMODIFIERS 0xFFFF0000&#define SHADIO$M_FCODE_WAS_SET 0x100 M00 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _shadio {N/* SETCHAR SHADOWING function code/modifiers structure */#pragma __nomember_alignment __struct {N unsigned shadio$v_fcode : 16; /* Function Code Field */N unsigned shadio$v_fmodifiers : 16; /* Function Modifiers Field M */# } shadio$r_fcode_structure; __struct {, unsigned shadio$v_fcode_fill_1 : 16;N unsigned shadio$v_fcode_was_set : 1; /* */( unsigned shadio$v_filler_1 : 15;$ } shadio$r_shadio_modifiers; } SHADIO; #if !defined(__VAXC)>#define shadio$v_fcode shadio$r_fcode_structure.shadio$v_fcodeH#define shadio$v_fmodifiers shadio$r_fcode_structure.shadio$v_fmodifiersO#define shadio$v_fcode_was_set shadio$r_shadio_modifiers.sMhadio$v_fcode_was_set"#endif /* #if !defined(__VAXC) */ N/* For Alpha */##define SHAD$M_SNAPSHOT_PENDING 0x1$#define SHAD$M_SNAPSHOT_COMPLETE 0x2#define SHAD$M_READ_MASTER 0x4#define SHAD$M_FLUSH_WLT 0x8&#define SHAD$M_ENFORCE_LOCAL_READ 0x10&#define SHAD$M_LOCAL_STATUS_BIT05 0x20$#define SHAD$M_NO_SINGLE_DECRAM 0x40$#define SHAD$M_HBMM_RECOVERY_IP 0x80-#define SHAD$M_HBMM_EVAL_POLICY_ENABLED 0x100+#define SHAD$M_HBMM_ MNO_MASTER_BITMAPS 0x200'#define SHAD$M_CLEAR_SCB_WRITECNT 0x400.#define SHAD$M_HOST_COMPARE_ALL_WRITES 0x10000,#define SHAD$M_BUGCHECK_ON_DATACHECK 0x20000,#define SHAD$M_AVAILABLE_IN_PROGRESS 0x40000)#define SHAD$M_LOCAL_STATUS_BIT19 0x80000#define SHAD$M_WBM 0x100000"#define SHAD$M_WBM_WRTLCK 0x200000+#define SHAD$M_USE_MASTER_FOR_READ 0x400000 #define SHAD$M_ABORT_VU 0x800000(#define SHAD$M_SPLIT_READ_LBNS 0x1000000+#define SHAD$M_LOCAL_STATUS_BIT25 0x2000000+#define SHAD$M_LOCALM_STATUS_BIT26 0x4000000*#define SHAD$M_SCB_UPDATE_FAILED 0x80000001#define SHAD$M_SKIP_IF_HBMM_IS_ENABLED 0x40000000(#define SHAD$M_MUST_BE_MERGED 0x80000000#define SHAD$M_NORMAL 0x1#define SHAD$M_NEW 0x2#define SHAD$M_COPYING 0x20#define SHAD$M_MERGING 0x40#define SHAD$M_MINIMRG 0x80#define SHAD$M_COPY_RESET 0x100#define SHAD$M_BOOTING 0x200#define SHAD$M_SCB_WLG 0x400#define SHAD$M_MUST_MRG 0x4000#define SHAD$M_FAILED 0x8000#define SHAD$M_MBR_COPY 0x1#define SHAD$M M_MBR_MERGE 0x2#define SHAD$M_MBR_CIP 0x4#define SHAD$M_MBR_SRC 0x20#define SHAD$M_MBR_MCPY 0x40#define SHAD$M_MBR_VALID 0x80#define SHAD$M_MBR_FCPY 0x1N#define SH$C_CIP_MASK 263172 /* 00040404 */N#define SH$C_MCPY_MASK 4210752 /* 00404040 */N#define SH$C_MBR_MCPY_MASK 4210752 /* 00404040 */N#define SH$C_VALID_CIP_COPY_MBR0 133 /* 00000085 */N#define SH$C_VALID_C MIP_COPY_MBR1 34048 /* 00008500 */N#define SH$C_VALID_CIP_COPY_MBR2 8716288 /* 00850000 */N#define SH$C_VALID_SRC_MBR0 160 /* 000000A0 */N#define SH$C_VALID_SRC_MBR1 40960 /* 0000A000 */N#define SH$C_VALID_SRC_MBR2 10485760 /* 00A00000 */$#define SHAD$M_CA_COPY_ACTIVATED 0x1 #define SHAD$M_CA_LOCAL_COPY 0x2!#define SHAD$M_CA_REMOTE_COPY 0x4##define SHAD$M_CA_MCOPY_PATH_EST 0x8!#define SHAD$M_CA_COPY_RETRY 0x10##define SHAD$M_CA_COPY_DISABLE 0x20$#define SHAD$M_CA_LDCD_DISABLED 0x40$#define SHAD$M_CA_RDCD_DISABLED 0x80-#define SHAD$M_CA_CHECK_BITMAP_ERR 0x80000000#define SHAD$M_IN_PROG 0x1#define SHAD$M_INITING 0x2#define SHAD$M_MMB_VALID 0x4(#define SHAD$M_MMB_ALLOCATION_FAILED 0x8#define SHAD$M_LOST_CNID 0x10$#define SHAD$M_TABLE_GENERATION 0x20#define SHAD$M_SWITCHING 0x40&#define SHAD$M_FLUSH_RATE_EXCEEDED 0x1##define SHAD$M_BOO MT_DEVICE_GONE 0x1&#define SHAD$M_MASTER_EQL_BOOT_DEV 0x2'#define SHAD$M_ORIBOOTDEV_SRC_VALID 0x8*#define SHAD$M_MASTER_ON_BAD_ADP_PATH 0x10+#define SHAD$M_BOOTED_ON_EMULATED_PATH 0x20+#define SHAD$M_MASTER_ON_EMULATED_PATH 0x40,#define SHAD$M_DUMP_UNIT_NUMBER_WRITTEN 0x80#define SHAD$M_NODMPDISK 0x8000"#define SHAD$M_EXTENDED_INVWLG 0x1*#define SHAD$M_EXTENDED_INVWLG_PENDING 0x2+#define SHAD$M_EXTENDED_RESTARTED_TRIGR 0x4%#define SHAD$M_EXTENDED_WLG_TO_ON 0x8*#define SHAD$M_EXTENDE MD_EP_INPROGRESS 0x10$#define SHAD$M_EXTENDED_EP_DONE 0x20,#define SHAD$M_EXTENDED_SHDCPY_GTLK_ACT 0x40*#define SHAD$M_EXTENDED_INVWLG_NEEDED 0x80-#define SHAD$M_EXTENDED_COPY_COLLISIONS 0x200,#define SHAD$M_EXTENDED_COPY_HOTBLOCKS 0x400+#define SHAD$M_EXTENDED_DO_PASSIVE_MV 0x800.#define SHAD$M_COPY_MERGE_COMPLETE_TIME 0x1000##define SHAD$M_EXTENDED_MBR_CIP 0x1)#define SHAD$M_HOMEBLOCK_CHECKSUM_BAD 0x4"#define SHAD$M_ODSII_CHECK_BAD 0x8$#define SHAD$M_SCB_CHECKSUM_BAD 0x10 #define SHADM$M_SCB_WRONG_VU 0x20)#define SHAD$M_SCB_NOMATCH_MOUNTTIME 0x40)#define SHAD$M_SCB_BAD_VOL_LOCK_NAME 0x80#define SHAD$M_BIT16 0x10000'#define SHAD$M_COPY_FROM_MASTER 0x20000##define SHAD$M_HANDLE_VALID 0x40000&#define SHAD$M_REMOVE_THIS_MBR 0x80000'#define SHAD$M_USE_ONE_SRC_MBR 0x100000"#define SHAD$M_DECRAM_MBR 0x200000(#define SHAD$M_INCOMPATIBLE_SCB 0x400000%#define SHAD$M_SHD_WAS_CLEAR 0x800000#define SHAD$M_BIT24 0x1000000#define SHAD$M_BIT25 0x2000000#define SHAD$M_BIT26 0 Mx4000000#define SHAD$M_BIT27 0x8000000!#define SHAD$M_IOERROR 0x100000001#define SHAD$M_USER_SUPPLIED_READ_BIAS 0x20000000(#define SHAD$M_SOURCE_DCD_MBR 0x40000000#define SHAD$M_BIT31 0x80000000#define SHAD$C_ID_BIAS 100000N/* */(#define SHAD$M_QUIESCENT_POINT_EVENT 0x1%#define SHAD$M_SEQUENTIAL_COMMAND 0x2$#define SHAD$M_MEMBERSHIP_CHANGE 0x4%#define SHAD$M_PREVENT_MBR_CHANGE 0x8!#define SHAD$M_LOCAL_QUIESCEM 0x10$#define SHAD$M_TRIGGER_VALIDATE 0x20"#define SHAD$M_SEQUENTIAL_NOP 0x40#define SHAD$M_LOCAL_WLG 0x1+#define SHAD$M_EVALUATION_THREAD_ACTIVE 0x2'#define SHAD$M_WLG_THRESHOLD_ACTIVE 0x4'#define SHAD$M_WHM_DEAL_TIMR_ACTIVE 0x8##define SHAD$M_PENDING_WLG_OFF 0x10"#define SHAD$M_PENDING_WLG_ON 0x20'#define SHAD$M_PENDING_WLG_OFF_SCB 0x40&#define SHAD$M_PENDING_WLG_ON_SCB 0x80##define SHAD$M_DELETE_ENTRIES 0x100$#define SHAD$M_NF_TMP_IN_USE 0x10000-#define SHAD$M_CONT_ID_CHECK_DISMABLED 0x20000(#define SHAD$M_WLGPRM_BAD_STATUS 0x40000(#define SHAD$M_WLG100_BAD_STATUS 0x80000)#define SHAD$M_WLGLCK_BAD_STATUS 0x100000+#define SHAD$M_GET_LOCK_MAP_FAILED 0x200000#define SHAD$M_DISABLE_WLG 0x1#define SHAD$M_ENABLE_WLG 0x2#define SHAD$M_DRAIN_IO_0 0x1#define SHAD$M_DRAIN_IO_1 0x2#define SHAD$M_DRAIN_IO_2 0x4#define SHAD$M_DRAIN_IO_3 0x8#define SHAD$M_DRAIN_IO_4 0x10#define SHAD$M_DRAIN_IO_5 0x20#define SHAD$M_DRAIN_IO_6 0x40#define SHAD$M_DRAIN_IO_7 0xM80#define SHAD$M_DRAIN_IO_8 0x100#define SHAD$M_DRAIN_IO_9 0x200#define SHAD$M_DRAIN_IO_A 0x400#define SHAD$M_DRAIN_IO_B 0x800 #define SHAD$M_DRAIN_IO_C 0x1000 #define SHAD$M_DRAIN_IO_D 0x2000 #define SHAD$M_DRAIN_IO_E 0x4000 #define SHAD$M_DRAIN_IO_F 0x8000Y#define SHAD$K_VETO_NEW_CHAR 11181 /* Value used to veto proposed NEW_CHAR change */'#define SHAD$M_SHADOWING_LEVEL_BIT0 0x1'#define SHAD$M_SHADOWING_LEVEL_BIT1 0x2'#define SHAD$M_SHADOWING_LEVEL_BIT2 0x4'#define SHADM$M_SHADOWING_LEVEL_BIT3 0x8N#define SHAD$K_LENGTH 7424 /*Length of Structure */N#define SHAD$C_LENGTH 7424 /*Length of Structure */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; struct _vcb; struct _irp; struct _wbmb; struct _tqe;struct _hbmm_ep; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember M_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _shad {#pragma __nomember_alignment __union {N struct _shad *shad$l_flink; /* Used for offset determination */N struct _shad *shad$l_priority_fl; /* Priority Level Linked List */$ } shad$r_shad_start_overlay;N struct _shad *shad$l_priority_bl; /* Backward link */N unsigned short int shad$w_size; /* Size of this structure */N unsiMgned char shad$b_type; /* Standard fields */N unsigned char shad$b_subtyp; /* ... */N struct _ucb *shad$l_vu_ucb; /* Unit Control Block for VU */N struct _vcb *shad$l_vu_vcb; /* Volume Control Block for VU */N __union { /* */N unsigned int shad$l_old_driver_mode; /* */N struct _irp *shad$l_activeM_irps; /* Obsolete Active "Master" IRPs */# } shad$r_shadspare_overlay;V struct _irp *shad$l_perm_irp; /* Volume Processing always needs one .... */N unsigned int shad$l_notification_id; /* Notification ID */d LOCK shad$b_membership_permission; /* ($MBRPRM) Shadow set membership change permission lock */R LOCK shad$b_membership_lock; /* ($MBRSHP) Shadow set membership lock */Y LOCK shad$b_member_of_set; /* ($IN_SET) Shadow set guarManteed member lock */_ LOCK shad$b_watcher_lock; /* ($WATCHR) Shadow set membership lock watcher lock */e LOCK shad$b_seq_cmd_permission; /* ($SEQPRM) Shadow set sequential command permission lock */N/* */^/* The following definitions are to allow DPDRIVER to work correctly, on older versions. */h/* We do this by defining multiple locations to contain "GENERATION Numbers" ... the only item that */ Mn/* the DPDriver was extracting. Older versions of SHD_RELEASE_FLAG.MAR have the specifics and the assume */S/* statements. Spares added to insure that the HOLE is in the correct location */N/* */" unsigned int shad$l_lookahead;! unsigned int shad$l_max_mbrs;# unsigned int shad$l_spare4 [3];* unsigned char shad$b_wbm_bitmap_group; unsigned char shad$b_spare1;% unsigned short int shad$w_spare3; M __union {' unsigned char shad$b_hole [96]; __struct {N unsigned int shad$l_track_wbm; /* Last WBM call locator */7 unsigned int shad$l_scp_merge_repair_count;7 unsigned int shad$l_app_merge_repair_count;+ unsigned __int64 shad$q_dpgen1;9 unsigned int shad$l_recoverable_err_ctr [16];: unsigned int shad$l_recoverable_err_time [16];0 unsigned char shad$b_node_map2 [32];+ Munsigned __int64 shad$q_dpgen2;e unsigned int shad$l_stop_merge_at_lbn; /* Suspend full merge after xyzzy lbn is passed */+ unsigned __int64 shad$q_dpgen3;0 } shad$r_reserved_storage_overlay_2;* } shad$r_reserved_storage_overlay;N/* End of DPDRIVER specific change */Z LOCK shad$b_seq_cmd_lock; /* ($SEQCMD) Shadow set sequential command lock */N LOCK shad$b_copier_lock; /* ($COPIER) ShaMdow set copier lock */N unsigned char shad$b_node_map [32]; /* Mounted node bit map */Q __union { /* Align the following queues properly */N/* and create a status longword which isn't completely zeroed by certain */N/* state changes. */H unsigned int shad$l_local_status; /* Node specific status */ __struct {[ unsigned shad$v_snapshot_pending : 1; /* Snapshot Mshutdown/restart initiated */[ unsigned shad$v_snapshot_complete : 1; /* Snapshot shutdown/restart complete */Q unsigned shad$v_read_master : 1; /* Read only from the master disk */N unsigned shad$v_flush_wlt : 1; /* Flush write log table */a unsigned shad$v_enforce_local_read : 1; /* Bias the READ I/O to best local members */N unsigned shad$v_local_status_bit05 : 1; /* */Y unsigned shad$v_no_singlMe_decram : 1; /* Permanent Storage device required */ unsigned shad$v_hbmm_recovery_ip : 1; /* Host Based Mini Merge is actively calling WBM to determine which LBAs must be \ merged */ unsigned shad$v_hbmm_eval_policy_enabled : 1; /* HBMM "evaluate policy" for master bitmap creation is enabled on server\ */ unsigned shad$v_hbmm_no_master_bitmaps : 1; /* HBMM the last Pending Write "evaluate policy" for master bitmap creation\ is enabled on server */v M unsigned shad$v_clear_scb_writecnt : 1; /* If the VU is _SWL and a full merge is completed ... do this. */6 unsigned shad$v_filler_local_status_0 : 1;6 unsigned shad$v_filler_local_status_1 : 4;b unsigned shad$v_host_compare_all_writes : 1; /* Force host compare every write I/O */` unsigned shad$v_bugcheck_on_datacheck : 1; /* If host compare on write I/O fails */N unsigned shad$v_available_in_progress : 1; /* */NM unsigned shad$v_local_status_bit19 : 1; /* */N unsigned shad$v_wbm : 1; /* WBM call active for Mini Copy */N unsigned shad$v_wbm_wrtlck : 1; /* Mini Copy */O unsigned shad$v_use_master_for_read : 1; /* NCA Copy Read Source */N unsigned shad$v_abort_vu : 1; /* Requested Via User Interface */N unsigned shad$v_split_read_lbns : 1; /* */N unsigned shaMd$v_local_status_bit25 : 1; /* */N unsigned shad$v_local_status_bit26 : 1; /* */N unsigned shad$v_scb_update_failed : 1; /* */6 unsigned shad$v_filler_local_status_2 : 2; unsigned shad$v_skip_if_hbmm_is_enabled : 1; /* Used after VU successfully completes MV when scanning the priority queu\e for VUs to bump */Z unsigned shad$v_must_be_merged : 1; /* For NPW to require a merge Moperation */' } shad$r_local_status_bits;& } shad$r_local_status_overlay;N struct _irp *shad$l_active_fl; /* FL for Active Queue */N struct _irp *shad$l_active_bl; /* BL for Active Queue */N struct _irp *shad$l_restart_fl; /* FL for restart wait queue */N struct _irp *shad$l_restart_bl; /* BL for restart wait queue */N unsigned short int shad$w_wasclr_count; /* Mini Copy counter */Q unsignNed short int shad$w_delay_start_of_copy; /* Copy startup delay count */N/* */N/* define the LAST_RINDX so that it can be used as a byte and yet maintain */N/* longword alignment. */N/* */ __union {N unsigned int shad$l_last_rindx; /* Index of last read SSM */N unsignedN char shad$b_last_rindx; /* */ } shad$r_indx_structure; __struct {N unsigned int shad$l_copy_vector; /* Address of COPY routine */V unsigned int shad$l_merge_vector; /* Address of full MERGE or HBMM routine */Q unsigned int shad$l_write_vector; /* Address of WRITE Startio routine */N unsigned int shad$l_read_vector; /* Address of DSE Startio routine */N unsigned int shad$l_spare_vector; /* Spare N */ } shad$r_vector;( unsigned int shad$l_spare_array [7];N/* */N/* The following fields, up to the next comment are placed contiguously in */N/* this data structure so that they can be copied from the SCB in one */N/* instruction. */N/* */N unsigned __i Nnt64 shad$q_genernum; /* Shadow Set generation number */N unsigned __int64 shad$q_unit_id; /* unique cluster-wide identifier */ __union {N unsigned short int shad$w_status; /* Volume status: */ __struct {N unsigned shad$v_normal : 1; /* Shadow set populated and online */N unsigned shad$v_new : 1; /* Newly created, no members yet */N unsigned shad$v_filler_sts_1 : 3; /* */N N unsigned shad$v_copying : 1; /* Copy State */N unsigned shad$v_merging : 1; /* Merge State */N unsigned shad$v_minimrg : 1; /* Mini Merge in progress */O unsigned shad$v_copy_reset : 1; /* Reset Shadow Server Copy mode */N unsigned shad$v_booting : 1; /* Shadow set in booting state */N unsigned shad$v_scb_wlg : 1; /* Write Logging Phase 1 enabled */N unsigned shad$v_ Nfiller_sts_2 : 3; /* Reserved */N unsigned shad$v_must_mrg : 1; /* This set requires a full merge */N unsigned shad$v_failed : 1; /* Shadow set not populated */! } shad$r_status_bits; } shad$r_status_overlay; __union {N unsigned char shad$b_member_status; /* Member status bits */ __struct {N unsigned shad$v_mbr_copy : 1; /* Member involved in copy */N unsigned shad$Nv_mbr_merge : 1; /* Member being merged */P unsigned shad$v_mbr_cip : 1; /* Cluster wide copy in progress bit */, unsigned shad$v_filler_jja3 : 1;, unsigned shad$v_filler_jja5 : 1;N unsigned shad$v_mbr_src : 1; /* Member can be used for source */N unsigned shad$v_mbr_mcpy : 1; /* Mini Copy candidate */N unsigned shad$v_mbr_valid : 1; /* Status information is valid */( } shad$r_member_status_bit Ns; __struct {N unsigned shad$v_mbr_fcpy : 1; /* Member involved in copy */, unsigned shad$v_filler_jja1 : 7;, } shad$r_member_status_bits_ing;, } shad$r_member_status_overlay [16];R unsigned short int shad$w_scb_mbz; /* Historically cleared by UPDATE_DISKS */ unsigned int shad$l_spare7;N unsigned __int64 shad$q_member_ids [16]; /* Unit ID for member */N unsigned int shad$l_scb_lbn; /* Unit Control Block fo Nr VU */N unsigned char shad$b_devices; /* Number of devices in SS */N unsigned char shad$b_members; /* Number of full members */ __union {N unsigned char shad$b_master_index; /* Array index to master UCB */N unsigned char shad$b_mast_indx; /* Array index to master UCB */% } shad$r_masterindex_overlay;N unsigned char shad$b_mrg_targets; /* Merge Copy Targets */ __union {N unsigned c Nhar shad$b_fc_targets; /* Full Copy Targets */N unsigned char shad$b_copy_targets; /* Full or MINI Copy Targets */$ } shad$r_copytarget_overlay;N unsigned char shad$b_decram_mbrs; /* Number of DECram devices */N char shad$b_filler_4 [6]; /* Reserved for alignment */N/* */N/* Maintain the following array as the last part of this data structure */N/* in  Norder to maintain the longword alignment of fields preceding it. */N/* */N struct _ucb *shad$l_member_ucb [16]; /* UCB for member */% struct _ucb *shad$l_filler7 [10];N struct _wbmb *shad$l_wbmb; /* For Mini Copy */N struct _vcb *shad$l_member_vcb [16]; /* VCB for member */ __union {N unsigned int shad$l_copy_lbn [16]; /* Last LBN C Nopied */N unsigned int shad$l_copy_or_merge_lbn [16]; /* Last or either LBN */N unsigned int shad$l_merge_lbn [16]; /* Last LBN Merged */$ } shad$r_copy_merge_overlay;N unsigned int shad$l_perd_lckid [16]; /* sublock id for */N/* perdisk licensing */N/* Command Assist Information is added at the end of the shad to be */N/* backward compatible. N */N struct _irp *shad$l_vp_irp; /* Volume processing master. */ unsigned int shad$l_spare2;N unsigned int shad$l_wlg [16]; /* Array of table indicators. */ unsigned int shad$l_spare5;N LOCK shad$b_copier_threshold; /* ($THRHLD) Copier threshold lock */N LOCK shad$b_wlg_inv; /* ($SHDINV) Invalidate WLG lock */ __union {N unsigned int shad$l_ca_copy_status; /* Command Assisted Co Npy Status */ __struct {N unsigned shad$v_ca_copy_activated : 1; /* Copy activated. */N unsigned shad$v_ca_local_copy : 1; /* Local copy. */N unsigned shad$v_ca_remote_copy : 1; /* Remote copy. */X unsigned shad$v_ca_copy_path_est : 1; /* Communication path established. */V unsigned shad$v_ca_copy_retry : 1; /* Retrying last I/O on a diff disk */N unsigned shad$v_ca_copy_disable : 1; /* N Disable assisted copy. */T unsigned shad$v_ca_ldcd_disabled : 1; /* Disable local assisted copy */U unsigned shad$v_ca_rdcd_disabled : 1; /* Disable remote assisted copy */N unsigned shad$v_filler_copy_status : 23; /* */^ unsigned shad$v_ca_check_bitmap_err : 1; /* WBM CHECK BITMAP returned an error */) } shad$r_ca_copy_status_bits;( } shad$r_ca_copy_status_overlay;N unsigned int shad$l_ca_source_index; /N* Command Assisted Copy Source */N unsigned int shad$l_ca_target_index; /* Command Assisted Copy Target */S struct _tqe *shad$l_wlg_threshold_tqe; /* Pointer to [SHADOWING] TQE Phase I */N unsigned short int shad$w_failed_cnid; /* */N unsigned short int shad$w_remove_mbr_err; /* */O unsigned int shad$l_mmb; /* Pointer to Merge Management Block */N struct _irp *shad$l_srvr_irp; /* Shadow server I/O N PTR */ __union {N unsigned int shad$l_mm_sts; /* Longword boundary */ __struct {N unsigned shad$v_in_prog : 1; /* In-progress */N unsigned shad$v_initing : 1; /* Table generation phase */N unsigned shad$v_mmb_valid : 1; /* mmb valid */O unsigned shad$v_mmb_allocation_failed : 1; /* allocation failed */N unsigned shad$v_lost_cnid : 1; /* N lost one or more cnids */N unsigned shad$v_table_generation : 1; /* mmb in use for table */N unsigned shad$v_switching : 1; /* mini-merge to merge switch */( unsigned shad$v_fill_2_ : 1;! } shad$r_mm_sts_bits; } shad$r_mm_sts_overlay;N/* */N/* Additional count to track how many seqcmd threads are queued. */N/* N */R unsigned int shad$l_seqcmd_thread_count; /* Count concurrent seqcmd threads */ __union {N unsigned char shad$b_wlginv_map [32]; /* Nodes with WLG Lock */' } shad$r_write_logging_overlay;N unsigned int shad$l_flush_count; /* Flush count */N unsigned int shad$l_flush_tick_count; /* Heart beat counter. */ __union {N unsigned int shad$l_flush_sts; /* Longword boundary N */N __struct { /* WLG on Off. */O unsigned shad$v_flush_rate_exceeded : 1; /* Flush rate exceeded */( unsigned shad$v_fill_3_ : 7;$ } shad$r_flush_sts_bits;# } shad$r_flush_sts_overlay;I/* SNAPSHOT_IRP longword unsigned; /* Pointer to the fastboot IRP */M/* SNAPSHOT_EXT longword unsigned; /* Pointer to the shadow extension */G/* SNAPSHOT_UCB longword unsigned; /* Pointer to the Nmaster UCB */D/* SNAPSHOT_STS longword unsigned; /* Saved master UCB$L_STS */N unsigned int shad$l_virtual_unit_timeout; /* */N/* Member array */3 unsigned int shad$l_shadow_member_timeout [16];N unsigned short int shad$w_rwaitcntctr; /* Count of negative decrements */R unsigned char shad$b_rwaitcntlog; /* Number of error log entries to write */N unsigned char shad$b_rwaitcntbug; /* N If sign bit is set, crash */ __union {R unsigned int shad$l_wlg_preference; /* Write Logging PREFERENCE Phase 1 */% } shad$r_wrt_logging_overlay;N/* */N/* DCD copy fence and some reserved longwords */N/* */S unsigned int shad$l_dcd_copy_lbn; /* DCD Copy Fence for Assisted Full Copy */N N unsigned int shad$l_dcd_multiplier; /* DCD Multiplier */N unsigned int shad$l_dcd_wbm_target_mbr; /* Mini Copy member using DCD */N unsigned short int shad$w_abortvpctr; /* Count of negative decrements */R unsigned char shad$b_abortvplog; /* Number of error log entries to write */N unsigned char shad$b_abortvpbug; /* If sign bit is set, crash */N unsigned int shad$l_abort_incshamem; /* */N unsigned short int sNhad$w_incshamemctr; /* */N unsigned char shad$b_incshamemlog; /* */N unsigned char shad$b_incshamembug; /* */N/* */N/* Warning : Must be quadword aligned */N/* */ __union {N unsigned short int shad$w_Nsdd_status; /* Master switching status: */ __struct {N unsigned shad$v_boot_device_gone : 1; /* */N unsigned shad$v_master_eql_boot_dev : 1; /* */N unsigned shad$v_filler_7 : 1; /* */N unsigned shad$v_oribootdev_src_valid : 1; /* */N unsigned shad$v_master_on_bad_adp_path : 1; /* */N unsigned shad$v_booted_on_Nemulated_path : 1; /* */N unsigned shad$v_master_on_emulated_path : 1; /* */N unsigned shad$v_dump_unit_number_written : 1; /* */N unsigned shad$v_filler_6 : 7; /* Reserve one last field */N unsigned shad$v_nodmpdisk : 1; /* */' } shad$r_switchboot_status;$ } shad$r_sdd_status_overlay;N unsigned short int shad$w_wbm_has_io; /* For Mini Copy N *// unsigned int shad$l_vu_recoverable_err_cnt;0 unsigned int shad$l_vu_recoverable_err_time;a LOCK shad$b_watcher_member_of_set; /* ($IN_SET) Shadow set guaranteed member WATCHER lock */R unsigned int shad$l_old_threshold_updatetime; /* For UPDATE_THRESHOLD's use */ __union {P unsigned int shad$l_extended_status; /* Extended shadow volume status */ __struct {0 unsigned shad$v_extended_invwlg : 1;8 unsigned shad$v_extended N_invwlg_pending : 1;9 unsigned shad$v_extended_restarted_trigr : 1;3 unsigned shad$v_extended_wlg_to_on : 1;7 unsigned shad$v_extended_ep_inprogress : 1;1 unsigned shad$v_extended_ep_done : 1;9 unsigned shad$v_extended_shdcpy_gtlk_act : 1;7 unsigned shad$v_extended_invwlg_needed : 1;2 unsigned shad$v_filler_extended_1 : 1;9 unsigned shad$v_extended_copy_collisions : 1;8 unsigned shad$v_ex Ntended_copy_hotblocks : 1;7 unsigned shad$v_extended_do_passive_mv : 1;9 unsigned shad$v_copy_merge_complete_time : 1;4 unsigned shad$v_filler_extended_12 : 19;* } shad$r_extended_status_bits;) } shad$r_extended_status_overlay;7 unsigned short int shad$w_devsts_mscp_mtverip_cntr;7 unsigned short int shad$w_devsts_seqcmd_there_cntr;5 unsigned short int shad$w_devsts_passive_mv_cntr;7 unsigned short int shad$w_devsts_node_fail Nure_cntr;5 unsigned short int shad$w_devsts_wlgsta_cha_cntr;2 unsigned short int shad$w_devsts_wlg_inv_cntr;/ struct _irp *shad$l_trigger_validate_flink;/ struct _irp *shad$l_trigger_validate_blink;& unsigned int shad$l_seq_cmd_flink;& unsigned int shad$l_seq_cmd_blink;+ unsigned int shad$l_node_failure_flink;+ unsigned int shad$l_node_failure_blink;+ unsigned int shad$l_node_failure_queue;3 unsigned short int shad$w_node_failure_status1;3 unsigned sNhort int shad$w_node_failure_status2;N/* CONTROLLER_WLG longword unsigned dimension #XMAXMBRS; */N/* CONTROLLER_WLG_IOSB quadword unsigned; */N/* */N/* NOTE: The EXTENDED_MEMBER_STATUS byte is a local extension of the */I/* MEMBER_STATUS byte that resides in the SCB. Therefore, the */I/* MBR_VALID bit in MEMBER_STATUS is used to determine validity N */I/* of the bits in EXTENDED_MEMBER_STATUS. */N/* */ __union {4 unsigned char shad$b_extended_member_status; __struct {` unsigned shad$v_extended_mbr_cip : 1; /*( %X00000001 ) Local copy in progress bit */N unsigned shad$v_filler_extsts1 : 1; /*( %X00000002 ) */N unsigned shad$v_homeblock_checksum_bad : 1; /*( %X00000004 )  N */N unsigned shad$v_odsii_check_bad : 1; /*( %X00000008 ) */N unsigned shad$v_scb_checksum_bad : 1; /*( %X00000010 ) */N unsigned shad$v_scb_wrong_vu : 1; /*( %X00000020 ) */N unsigned shad$v_scb_nomatch_mounttime : 1; /*( %X00000040 ) */N unsigned shad$v_scb_bad_vol_lock_name : 1; /*( %X00000080 ) */1 } shad$r_extended_member_status_bits;2 } shad$r_extended_member_status_over [16 !N];N char shad$b_filler_8 [4]; /* Alignment filler */ __union {' unsigned int shad$l_mbr_status;I __struct { /* */a unsigned shad$v_filler_do_not_use_1 : 8; /* Overlay of the byte member status bits */N/* Do not use these bits */j unsigned shad$v_filler_do_not_use_2 : 8; /* Overlay of the extended byte member status bits */N"N/* Do not use these bits */N unsigned shad$v_bit16 : 1; /*( %X00010000 ) */X unsigned shad$v_copy_from_master : 1; /*( %X00020000 ) for Write Bit Map */R unsigned shad$v_handle_valid : 1; /*( %X00040000 ) for " " " */N unsigned shad$v_remove_this_mbr : 1; /*( %X00080000 ) */a unsigned shad$v_use_one_src_mbr : 1; /*( %X00100000 ) as read source on full cop#Ny */f unsigned shad$v_decram_mbr : 1; /*( %X00200000 ) DECram, a potentially volatile member */N unsigned shad$v_incompatible_scb : 1; /*( %X00400000 ) */N unsigned shad$v_shd_was_clear : 1; /*( %X00800000 ) */N unsigned shad$v_bit24 : 1; /*( %X01000000 ) */N unsigned shad$v_bit25 : 1; /*( %X02000000 ) */N unsigned shad$v_bit26 : 1; /*( %X04000000 ) $N */N unsigned shad$v_bit27 : 1; /*( %X08000000 ) */N unsigned shad$v_ioerror : 1; /*( %X10000000 ) */N unsigned shad$v_user_supplied_read_bias : 1; /*( %X20000000 ) */_ unsigned shad$v_source_dcd_mbr : 1; /*( %X40000000 ) Assisted copy source member */N unsigned shad$v_bit31 : 1; /*( %X80000000 ) */% } shad$r_mbr_status_bits;) } shad$r_mbr_status_overlay [16];%NN unsigned int shad$l_filler_5 [1]; /* For alignment */N/* The following are referenced in SHSB$MATCH_MASTER_SCB only. */N unsigned int shad$l_vp_time; /* Time OUT Time */N unsigned int shad$l_vp_mbridx; /* Member Index */N unsigned int shad$l_vp_valcnt; /* Count of Reads */N unsigned int shad$l_vp_valscb; /* Count of Valid SCBs */N unsigned int shad$l_&Nvp_mtch; /* Count matched */N unsigned int shad$l_vp_case; /* SET_CASE case */N unsigned int shad$l_vp_setcase; /* CHK_SET case */N unsigned int shad$l_vp_shadval; /* Valid SHAD Mbrs */N unsigned int shad$l_vp_scbmbr; /* Valid SCB Mbrs */N unsigned int shad$l_vp_mbrm; /* Matched Mbrs */N unsigned __int64 shad$q_vp_scr1; /* Temp. 'Nspace */N unsigned int shad$l_vp_bufarray [16]; /* SCB Buffer Array */N struct _irp *shad$l_vp_irparray [16]; /* IRP Array */N unsigned int shad$l_vp_idxarray [16]; /* Index Array */N/* The following are referenced in SHDR$START_ADDSHAD only. */N unsigned __int64 shad$q_add_scr1; /* Temporary Space. */N/* The following are referenced in SHLK$NODE_FAILURE only. (N*/N unsigned int shad$l_nf_tmp1_01; /* Temporary Space. */N unsigned int shad$l_nf_tmp1_02; /* Temporary Space */N/* The following constant is used by the SCSI Naming changes */N/* it is the bias used to ensure that an SCSSYTEMID cannot */N/* be mistaken for an allocation class. */N/* Added for threads package */N/* )N */N unsigned int shad$l_active_ctxb_fl; /* Thread active queue */' unsigned int shad$l_active_ctxb_bl;N unsigned int shad$l_stalled_ctxb_fl; /* Thread stall queue */( unsigned int shad$l_stalled_ctxb_bl;N unsigned int shad$l_intlio_ctxb_fl; /* Internal I/O queue */' unsigned int shad$l_intlio_ctxb_bl;N unsigned int shad$l_fork_ctxb_fl; /* Forking queue */% *N unsigned int shad$l_fork_ctxb_bl;N unsigned int shad$l_lock_ctxb_fl; /* Locking queue */% unsigned int shad$l_lock_ctxb_bl;S unsigned int shad$l_special_event_fl; /* Threads waiting to do special event */) unsigned int shad$l_special_event_bl;N unsigned int shad$l_unstoppable_ctxb_fl; /* Unstoppable threads */, unsigned int shad$l_unstoppable_ctxb_bl;N unsigned __int64 shad$q_seqcmd_seqnum; /* Sequence number */N __union +N { /* Significant events */+ unsigned int shad$l_special_events; __struct {S unsigned shad$v_quiescent_point_event : 1; /* Quiescent Point active */N unsigned shad$v_sequential_command : 1; /* Sequential command */N unsigned shad$v_membership_change : 1; /* Membership change */P unsigned shad$v_prevent_mbr_change : 1; /* Prevent members change */N unsigned shad$v_local_quiesce ,N: 1; /* Local quiesce. */U unsigned shad$v_trigger_validate : 1; /* Trigger validate blocking ast */S unsigned shad$v_sequential_nop : 1; /* Emulation of sequential NOP's */( unsigned shad$v_fill_4_ : 1;) } shad$r_special_events_bits;( } shad$r_special_events_overlay;. struct _tqe *shad$l_evaluation_thread_tqe;* struct _tqe *shad$l_whm_deal_timr_tqe; __union {N unsigned int shad$l_wlg_status; /* -N */N __struct { /* */N unsigned shad$v_local_wlg : 1; /* */N unsigned shad$v_evaluation_thread_active : 1; /* */N unsigned shad$v_wlg_threshold_active : 1; /* */N unsigned shad$v_whm_deal_timr_active : 1; /* */N unsigned shad$v_pending_wlg_off : 1; /* */N .N unsigned shad$v_pending_wlg_on : 1; /* */N unsigned shad$v_pending_wlg_off_scb : 1; /* */N unsigned shad$v_pending_wlg_on_scb : 1; /* */N unsigned shad$v_delete_entries : 1; /* */3 unsigned shad$v_filler_wlg_status1 : 7;N unsigned shad$v_nf_tmp_in_use : 1; /* */N unsigned shad$v_cont_id_check_disabled : 1; /N/* */N unsigned shad$v_wlgprm_bad_status : 1; /* */N unsigned shad$v_wlg100_bad_status : 1; /* */N unsigned shad$v_wlglck_bad_status : 1; /* */N unsigned shad$v_get_lock_map_failed : 1; /* */4 unsigned shad$v_filler_wlg_status2 : 10;% } shad$r_wlg_status_bits;$ } shad$r_wlg_status_overlay; __union {. unsign 0Ned short int shad$w_wlg_control; __struct {, unsigned shad$v_disable_wlg : 1;+ unsigned shad$v_enable_wlg : 1;( unsigned shad$v_fill_5_ : 6;& } shad$r_wlg_control_bits;% } shad$r_wlg_control_overlay; __union {a unsigned short int shad$w_drain_io_flag; /* RWAITCNT Bump flags Reserved for alignment */ __struct {+ unsigned shad$v_drain_io_0 : 1;+ unsigned shad$v_drain_io_1 : 1;+ 1N unsigned shad$v_drain_io_2 : 1;+ unsigned shad$v_drain_io_3 : 1;+ unsigned shad$v_drain_io_4 : 1;+ unsigned shad$v_drain_io_5 : 1;+ unsigned shad$v_drain_io_6 : 1;+ unsigned shad$v_drain_io_7 : 1;+ unsigned shad$v_drain_io_8 : 1;+ unsigned shad$v_drain_io_9 : 1;+ unsigned shad$v_drain_io_a : 1;+ unsigned shad$v_drain_io_b : 1;+ unsigned shad$v_drain_io_c : 1;+ 2N unsigned shad$v_drain_io_d : 1;+ unsigned shad$v_drain_io_e : 1;+ unsigned shad$v_drain_io_f : 1;( } shad$r_drain_io_flag_bits;' } shad$r_drain_io_flag_overlay;N unsigned int shad$l_ca_wasset_ctr; /* Count these */$ unsigned int shad$l_spare6 [26];N LOCK shad$b_vu_char; /* ($VUCHAR) VU Characteristics */V LOCK shad$b_wlg_inv_permission; /* ($WLGPRM) Invalidate WLG permission lock */Z 3NLOCK shad$b_copier_thrhld_permission; /* ($THRPRM) Copier threshold permission lock */N __union { /* Per V.U. */N unsigned int shad$l_threshold_bias; /* Both referenced */ __struct {N unsigned short int shad$w_threshold_io_count; /* */N unsigned short int shad$w_threshold_seconds; /* */) } shad$r_threshold_overlay_2;# } shad$r_threshold_overl 4Nay;N unsigned int shad$l_noctx_restrt_fl; /* User IRPs queued for */N unsigned int shad$l_noctx_restrt_bl; /* Retry. */N __union { /* */O unsigned int shad$l_wbm_handle [16]; /* Per Member Mini Copy Storage */ } shad$r_wbm_overlay; unsigned int shad$l_spare8;' unsigned __int64 shad$q_reserved_1;' unsigned __int64 shad$q_reserved_2;O unsigned int shad$l_thre5Nshold_update_time; /* For UPDATE_THRESHOLD's use */P unsigned int shad$l_threshold_update_count; /* For UPDATE_THRESHOLD's use */Q unsigned int shad$l_threshold_updateseconds; /* For UPDATE_THRESHOLD's use */N unsigned int shad$l_threshold_update_io; /* For UPDATE_THRESHOLD's use */' unsigned __int64 shad$q_vu_volsize;' unsigned __int64 shad$q_reserved_3;N unsigned int shad$l_hbmm_preference; /* */N/* 6N */N/* For Fibre Channel locally remote device determination */N/* KEEP this QUADWORD Aligned */N/* */N unsigned int shad$l_vu_site_value; /* *// unsigned int shad$l_member_site_value [16];$ unsigned int shad$l_bitmap_size;N/* 7N */N/* Merge Signal Stuff */N/* */N LOCK shad$b_mrgprm; /* ($MRGPRM) */N LOCK shad$b_mrgsig; /* ($MRGSIG) */N LOCK shad$b_mrgval; /* ($MRGVAL) */N unsigned int shad$l_trace1; /* SHAD$L_EXTENDED_STATUS */N un8Nsigned int shad$l_trace2; /* SHAD$W_STATUS, R0 (low word) */N unsigned int shad$l_trace3; /* Trace Number */N unsigned int shad$l_trace4; /* Trace Number */N unsigned int shad$l_log_cmdref; /* Tmp Storage for LOG_IT */P unsigned int shad$l_nolog_cnt; /* Count of LOG_IT calls that failed. */S unsigned int shad$l_pool_addr; /* Location for Chaining Allocated POOL. */N/* 9N */J/* N.B. The high word for each member in this array MUST remain unused */B/* to optimize the selection login in find_read_ucb. */N/* */N/* Read Bias - Setup by SHSB$SET_BIAS A.K.A. Read Cost */N/* Referenced by FIND_READ_UCB */' unsigned int shad$l_read_bias [16];N/* :N */J/* DDS SHAD Support */N/* */l LOCK shad$b_received_vu_char; /* ($RCVUCH) All received resultant VU characteristics after vote */[ LOCK shad$b_new_char; /* ($NEWCHR) Proposed change to VU characterics */N unsigned int shad$l_mos_valblk_offset; /* Offset into MOS value block */ __stru;Nct {m unsigned shad$v_shadowing_level_bit0 : 1; /* Prevents older versions from mounting the shadow set */m unsigned shad$v_shadowing_level_bit1 : 1; /* Prevents older versions from mounting the shadow set */m unsigned shad$v_shadowing_level_bit2 : 1; /* Prevents older versions from mounting the shadow set */m unsigned shad$v_shadowing_level_bit3 : 1; /* Prevents older versions from mounting the shadow set */2 unsigned shad$v_filler_valblk_offset : 28; N*/N LOCK shad$b_index4_id_gen_num; /* ($LGNIN4) Last GN for Index 1 */N LOCK shad$b_index5_id_gen_num; /* ($LGNIN5) Last GN for Index 2 */N LOCK shad$b_index6_id_gen_num; /* ($LGNIN6) Last GN for Index 0 */N LOCK shad$b_index7_id_gen_num; /* ($LGNIN7) Last GN for Index 1 */N LOCK shad$b_index8_id_gen_num; /* ($LGNIN8) Last GN for Index 2 */N LOCK shad$b_index9_id_gen_num; /* ($LGNIN9) Last GN for Index 0 */N LOCK shad$b_index1?N0_id_gen_num; /* ($LGNIN10) Last GN for Index 1 */N LOCK shad$b_index11_id_gen_num; /* ($LGNIN11) Last GN for Index 2 */N LOCK shad$b_index12_id_gen_num; /* ($LGNIN12) Last GN for Index 0 */N LOCK shad$b_index13_id_gen_num; /* ($LGNIN13) Last GN for Index 1 */N LOCK shad$b_index14_id_gen_num; /* ($LGNIN14) Last GN for Index 2 */N LOCK shad$b_index15_id_gen_num; /* ($LGNIN15) Last GN for Index 0 */N unsigned int shad$l_copy_merge_priority; /* @NFor HBMM */P unsigned int shad$l_do_shadow_copies_active; /* For priority level thread */N __union { /* */o unsigned int shad$l_hbmm_wbm_mst_hndl; /* HBMM master bitmap handle for VU on this node (if nonzero) */t unsigned int shad$l_hbmm_wbm_master_handle; /* HBMM master bitmap handle for VU on this node (if nonzero) */& } shad$r_shad_wbm_mst_overlay;x struct _hbmm_ep *shad$ps_hbmm_ep; AN/* If nonzero, pointer to HBMM_EP structure used to trigger "evaluate policy" */b unsigned __int64 shad$q_hbmm_reset_time_of; /* Time of most recent HBMM bitmap reset for VU */g unsigned int shad$l_mini_copy_ip_cnid; /* This contains the CNID of the system that WAS doing it */X unsigned int shad$l_hbmm_reset_count; /* Count of times HBMM bitmaps reset for VU */h unsigned int shad$l_hbmm_lbns_merged; /* This contains count of LBNs merged while HBMM is running */p unsigned int shad$BNl_hbmm_lbns_not_merged; /* This contains count of LBNs not merged while HBMM is running */ unsigned int shad$l_rec_dly_per_srv_ssm; /* This contains the seconds of delay per SSM before this system attempts to obtain */N/* the copier lock */i unsigned int shad$l_served_path_delay_due; /* This contains aggregate due time for the served SSMs */| unsigned __int64 shad$q_consistency_timestamp; /* Copy of time stamp from SCB read of a CNMBR_SRC SSM contains systime */N/* when last transient state completed that left the VU in that state */r unsigned int shad$l_scb_shadowing_status; /* Contains SCB$w_SHADOWING_STATUS from SCB read of a MBR_SRC SSM */ unsigned int shad$l_spare9;N unsigned __int64 shad$q_trace1; /* */N unsigned __int64 shad$q_trace2; /* */N unsigned __int64 shad$q_trace3; /* */N DN unsigned __int64 shad$q_trace4; /* */N unsigned __int64 shad$q_trace5; /* */N unsigned __int64 shad$q_trace6; /* */N unsigned __int64 shad$q_trace7; /* */N unsigned __int64 shad$q_trace8; /* */N unsigned __int64 shad$q_trace9; /* */N __union { EN /* */N unsigned int shad$l_copy_hotblocks; /* */N unsigned short int shad$w_copy_hotblocks; /* */ } shad$r_copy_hot;N __union { /* */N unsigned int shad$l_copy_collisions; /* */N unsigned short int shad$w_copy_collisions; /* */ } shad$r_copy_col;FNg unsigned int shad$l_hbmc_lbns_updated; /* Contains count of LBNs updated while mini copy is used */ unsigned int shad$l_optimal_hbmm_delay_due; /* Delay to allow systems that have a "pure" HBMM bitmap to obtain the _COPIER lock\ */. unsigned __int64 shad$q_ssm_gn_value [16];r unsigned __int64 shad$q_mounttime; /* Virtual Units current value, needed for Mini Copy Restart validation */| unsigned int shad$l_gn_update_active; /* Count number of blossomed generation numbers thatGN ware waiting to be updated */ int shad$l_fill_gn [1];N LOCK shad$b_add_member; /* ($ADDMBR) VU Characteristics */N LOCK shad$b_new_member; /* ($NEWMBR) VU Characteristics */N LOCK shad$b_add_result; /* ($ADDRES) VU Characteristics */N/* */N/* Preserve quadword alignment for IRP */N/* HN */ __union {N struct _irp *shad$l_irp; /* Pointer to shadow IRP */N unsigned int shad$l_shadend_plus; /* Reserved Storage */# } shad$r_shadend_structure; } SHAD; #if !defined(__VAXC);#define shad$l_flink shad$r_shad_start_overlay.shad$l_flinkG#define shad$l_priority_fl shad$r_shad_start_overlay.shad$l_priority_flN#define shad$l_old_driver_mode shad$r_shadspare_overlay.shad$l_old_driver_modeFIN#define shad$l_active_irps shad$r_shadspare_overlay.shad$l_active_irps?#define shad$b_hole shad$r_reserved_storage_overlay.shad$b_holek#define shad$l_track_wbm shad$r_reserved_storage_overlay.shad$r_reserved_storage_overlay_2.shad$l_track_wbm#define shad$l_scp_merge_repair_count shad$r_reserved_storage_overlay.shad$r_reserved_storage_overlay_2.shad$l_scp_merge_repair_cou\nt#define shad$l_app_merge_repair_count shad$r_reserved_storage_overlay.shad$r_reserved_storage_overlay_2.shad$l_app_mergeJN_repair_cou\nte#define shad$q_dpgen1 shad$r_reserved_storage_overlay.shad$r_reserved_storage_overlay_2.shad$q_dpgen1#define shad$l_recoverable_err_ctr shad$r_reserved_storage_overlay.shad$r_reserved_storage_overlay_2.shad$l_recoverable_err_ctr#define shad$l_recoverable_err_time shad$r_reserved_storage_overlay.shad$r_reserved_storage_overlay_2.shad$l_recoverable_err_timek#define shad$b_node_map2 shad$r_reserved_storage_overlay.shad$r_reserved_storage_overlay_2.shad$b_node_map2e#define shadKN$q_dpgen2 shad$r_reserved_storage_overlay.shad$r_reserved_storage_overlay_2.shad$q_dpgen2{#define shad$l_stop_merge_at_lbn shad$r_reserved_storage_overlay.shad$r_reserved_storage_overlay_2.shad$l_stop_merge_at_lbne#define shad$q_dpgen3 shad$r_reserved_storage_overlay.shad$r_reserved_storage_overlay_2.shad$q_dpgen3K#define shad$l_local_status shad$r_local_status_overlay.shad$l_local_statusl#define shad$v_snapshot_pending shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_snapshot_pendiLNngn#define shad$v_snapshot_complete shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_snapshot_completeb#define shad$v_read_master shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_read_master^#define shad$v_flush_wlt shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_flush_wltp#define shad$v_enforce_local_read shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_enforce_local_readp#define shad$v_local_status_bit05 shad$r_local_status_overlay.shad$r_local_statuMNs_bits.shad$v_local_status_bit05l#define shad$v_no_single_decram shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_no_single_decraml#define shad$v_hbmm_recovery_ip shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_hbmm_recovery_ip|#define shad$v_hbmm_eval_policy_enabled shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_hbmm_eval_policy_enabledx#define shad$v_hbmm_no_master_bitmaps shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_hbmm_no_master_bitmapsp#defNNine shad$v_clear_scb_writecnt shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_clear_scb_writecntz#define shad$v_host_compare_all_writes shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_host_compare_all_writesv#define shad$v_bugcheck_on_datacheck shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_bugcheck_on_datacheckv#define shad$v_available_in_progress shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_available_in_progressp#define shad$v_local_status_bit1ON9 shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_local_status_bit19R#define shad$v_wbm shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_wbm`#define shad$v_wbm_wrtlck shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_wbm_wrtlckr#define shad$v_use_master_for_read shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_use_master_for_read\#define shad$v_abort_vu shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_abort_vuj#define shad$v_split_read_lbns sPNhad$r_local_status_overlay.shad$r_local_status_bits.shad$v_split_read_lbnsp#define shad$v_local_status_bit25 shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_local_status_bit25p#define shad$v_local_status_bit26 shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_local_status_bit26n#define shad$v_scb_update_failed shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_scb_update_failedz#define shad$v_skip_if_hbmm_is_enabled shad$r_local_status_overlay.shad$r_local_status_bitQNs.shad$v_skip_if_hbmm_is_enabledh#define shad$v_must_be_merged shad$r_local_status_overlay.shad$r_local_status_bits.shad$v_must_be_mergedA#define shad$l_last_rindx shad$r_indx_structure.shad$l_last_rindxA#define shad$b_last_rindx shad$r_indx_structure.shad$b_last_rindx;#define shad$l_copy_vector shad$r_vector.shad$l_copy_vector=#define shad$l_merge_vector shad$r_vector.shad$l_merge_vector=#define shad$l_write_vector shad$r_vector.shad$l_write_vector;#define shad$l_read_vector shad$r_vectorRN.shad$l_read_vector=#define shad$l_spare_vector shad$r_vector.shad$l_spare_vector9#define shad$w_status shad$r_status_overlay.shad$w_statusL#define shad$v_normal shad$r_status_overlay.shad$r_status_bits.shad$v_normalF#define shad$v_new shad$r_status_overlay.shad$r_status_bits.shad$v_newN#define shad$v_copying shad$r_status_overlay.shad$r_status_bits.shad$v_copyingN#define shad$v_merging shad$r_status_overlay.shad$r_status_bits.shad$v_mergingN#define shad$v_minimrg shad$r_status_overlay.shad$SNr_status_bits.shad$v_minimrgT#define shad$v_copy_reset shad$r_status_overlay.shad$r_status_bits.shad$v_copy_resetN#define shad$v_booting shad$r_status_overlay.shad$r_status_bits.shad$v_bootingN#define shad$v_scb_wlg shad$r_status_overlay.shad$r_status_bits.shad$v_scb_wlgP#define shad$v_must_mrg shad$r_status_overlay.shad$r_status_bits.shad$v_must_mrgL#define shad$v_failed shad$r_status_overlay.shad$r_status_bits.shad$v_failed1#define shad$b_member_status shad$b_member_statusA#define shad$v_mbrTN_copy shad$r_member_status_bits.shad$v_mbr_copyC#define shad$v_mbr_merge shad$r_member_status_bits.shad$v_mbr_merge?#define shad$v_mbr_cip shad$r_member_status_bits.shad$v_mbr_cip?#define shad$v_mbr_src shad$r_member_status_bits.shad$v_mbr_srcA#define shad$v_mbr_mcpy shad$r_member_status_bits.shad$v_mbr_mcpyC#define shad$v_mbr_valid shad$r_member_status_bits.shad$v_mbr_validE#define shad$v_mbr_fcpy shad$r_member_status_bits_ing.shad$v_mbr_fcpyJ#define shad$b_master_index shad$r_masterindUNex_overlay.shad$b_master_indexD#define shad$b_mast_indx shad$r_masterindex_overlay.shad$b_mast_indxE#define shad$b_fc_targets shad$r_copytarget_overlay.shad$b_fc_targetsI#define shad$b_copy_targets shad$r_copytarget_overlay.shad$b_copy_targetsA#define shad$l_copy_lbn shad$r_copy_merge_overlay.shad$l_copy_lbnS#define shad$l_copy_or_merge_lbn shad$r_copy_merge_overlay.shad$l_copy_or_merge_lbnC#define shad$l_merge_lbn shad$r_copy_merge_overlay.shad$l_merge_lbnQ#define shad$l_ca_copy_status shVNad$r_ca_copy_status_overlay.shad$l_ca_copy_statusr#define shad$v_ca_copy_activated shad$r_ca_copy_status_overlay.shad$r_ca_copy_status_bits.shad$v_ca_copy_activatedj#define shad$v_ca_local_copy shad$r_ca_copy_status_overlay.shad$r_ca_copy_status_bits.shad$v_ca_local_copyl#define shad$v_ca_remote_copy shad$r_ca_copy_status_overlay.shad$r_ca_copy_status_bits.shad$v_ca_remote_copyp#define shad$v_ca_copy_path_est shad$r_ca_copy_status_overlay.shad$r_ca_copy_status_bits.shad$v_ca_copy_path_estj#definWNe shad$v_ca_copy_retry shad$r_ca_copy_status_overlay.shad$r_ca_copy_status_bits.shad$v_ca_copy_retryn#define shad$v_ca_copy_disable shad$r_ca_copy_status_overlay.shad$r_ca_copy_status_bits.shad$v_ca_copy_disablep#define shad$v_ca_ldcd_disabled shad$r_ca_copy_status_overlay.shad$r_ca_copy_status_bits.shad$v_ca_ldcd_disabledp#define shad$v_ca_rdcd_disabled shad$r_ca_copy_status_overlay.shad$r_ca_copy_status_bits.shad$v_ca_rdcd_disabledv#define shad$v_ca_check_bitmap_err shad$r_ca_copy_status_overlayXN.shad$r_ca_copy_status_bits.shad$v_ca_check_bitmap_err9#define shad$l_mm_sts shad$r_mm_sts_overlay.shad$l_mm_stsN#define shad$v_in_prog shad$r_mm_sts_overlay.shad$r_mm_sts_bits.shad$v_in_progN#define shad$v_initing shad$r_mm_sts_overlay.shad$r_mm_sts_bits.shad$v_initingR#define shad$v_mmb_valid shad$r_mm_sts_overlay.shad$r_mm_sts_bits.shad$v_mmb_validj#define shad$v_mmb_allocation_failed shad$r_mm_sts_overlay.shad$r_mm_sts_bits.shad$v_mmb_allocation_failedR#define shad$v_lost_cnid shad$r_mm_stsYN_overlay.shad$r_mm_sts_bits.shad$v_lost_cnid`#define shad$v_table_generation shad$r_mm_sts_overlay.shad$r_mm_sts_bits.shad$v_table_generationR#define shad$v_switching shad$r_mm_sts_overlay.shad$r_mm_sts_bits.shad$v_switchingH#define shad$b_wlginv_map shad$r_write_logging_overlay.shad$b_wlginv_mapB#define shad$l_flush_sts shad$r_flush_sts_overlay.shad$l_flush_stsl#define shad$v_flush_rate_exceeded shad$r_flush_sts_overlay.shad$r_flush_sts_bits.shad$v_flush_rate_exceededN#define shad$l_wlg_prefereZNnce shad$r_wrt_logging_overlay.shad$l_wlg_preferenceE#define shad$w_sdd_status shad$r_sdd_status_overlay.shad$w_sdd_statusj#define shad$v_boot_device_gone shad$r_sdd_status_overlay.shad$r_switchboot_status.shad$v_boot_device_gonep#define shad$v_master_eql_boot_dev shad$r_sdd_status_overlay.shad$r_switchboot_status.shad$v_master_eql_boot_devr#define shad$v_oribootdev_src_valid shad$r_sdd_status_overlay.shad$r_switchboot_status.shad$v_oribootdev_src_validv#define shad$v_master_on_bad_adp_path shad[N$r_sdd_status_overlay.shad$r_switchboot_status.shad$v_master_on_bad_adp_pathx#define shad$v_booted_on_emulated_path shad$r_sdd_status_overlay.shad$r_switchboot_status.shad$v_booted_on_emulated_pathx#define shad$v_master_on_emulated_path shad$r_sdd_status_overlay.shad$r_switchboot_status.shad$v_master_on_emulated_pathz#define shad$v_dump_unit_number_written shad$r_sdd_status_overlay.shad$r_switchboot_status.shad$v_dump_unit_number_written\#define shad$v_nodmpdisk shad$r_sdd_status_overlay.shad$r_sw\Nitchboot_status.shad$v_nodmpdiskT#define shad$l_extended_status shad$r_extended_status_overlay.shad$l_extended_statusp#define shad$v_extended_invwlg shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_extended_invwlg#define shad$v_extended_invwlg_pending shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_extended_invwlg_pending#define shad$v_extended_restarted_trigr shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_extended_restarted_trigrv#define sh]Nad$v_extended_wlg_to_on shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_extended_wlg_to_on~#define shad$v_extended_ep_inprogress shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_extended_ep_inprogressr#define shad$v_extended_ep_done shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_extended_ep_done#define shad$v_extended_shdcpy_gtlk_act shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_extended_shdcpy_gtlk_act~#define shad$v_exten^Nded_invwlg_needed shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_extended_invwlg_needed#define shad$v_extended_copy_collisions shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_extended_copy_collisions#define shad$v_extended_copy_hotblocks shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_extended_copy_hotblocks~#define shad$v_extended_do_passive_mv shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_extended_do_passive_mv#define _Nshad$v_copy_merge_complete_time shad$r_extended_status_overlay.shad$r_extended_status_bits.shad$v_copy_merge_complete_timeC#define shad$b_extended_member_status shad$b_extended_member_statusZ#define shad$v_extended_mbr_cip shad$r_extended_member_status_bits.shad$v_extended_mbr_cipf#define shad$v_homeblock_checksum_bad shad$r_extended_member_status_bits.shad$v_homeblock_checksum_badX#define shad$v_odsii_check_bad shad$r_extended_member_status_bits.shad$v_odsii_check_badZ#define shad$v_scb_checksu`Nm_bad shad$r_extended_member_status_bits.shad$v_scb_checksum_badR#define shad$v_scb_wrong_vu shad$r_extended_member_status_bits.shad$v_scb_wrong_vud#define shad$v_scb_nomatch_mounttime shad$r_extended_member_status_bits.shad$v_scb_nomatch_mounttimed#define shad$v_scb_bad_vol_lock_name shad$r_extended_member_status_bits.shad$v_scb_bad_vol_lock_name+#define shad$l_mbr_status shad$l_mbr_status8#define shad$v_bit16 shad$r_mbr_status_bits.shad$v_bit16N#define shad$v_copy_from_master shad$r_mbr_statuaNs_bits.shad$v_copy_from_masterF#define shad$v_handle_valid shad$r_mbr_status_bits.shad$v_handle_validL#define shad$v_remove_this_mbr shad$r_mbr_status_bits.shad$v_remove_this_mbrL#define shad$v_use_one_src_mbr shad$r_mbr_status_bits.shad$v_use_one_src_mbrB#define shad$v_decram_mbr shad$r_mbr_status_bits.shad$v_decram_mbrN#define shad$v_incompatible_scb shad$r_mbr_status_bits.shad$v_incompatible_scbH#define shad$v_shd_was_clear shad$r_mbr_status_bits.shad$v_shd_was_clear8#define shad$v_bit24 sha bNd$r_mbr_status_bits.shad$v_bit248#define shad$v_bit25 shad$r_mbr_status_bits.shad$v_bit258#define shad$v_bit26 shad$r_mbr_status_bits.shad$v_bit268#define shad$v_bit27 shad$r_mbr_status_bits.shad$v_bit27<#define shad$v_ioerror shad$r_mbr_status_bits.shad$v_ioerror\#define shad$v_user_supplied_read_bias shad$r_mbr_status_bits.shad$v_user_supplied_read_biasJ#define shad$v_source_dcd_mbr shad$r_mbr_status_bits.shad$v_source_dcd_mbr8#define shad$v_bit31 shad$r_mbr_status_bits.shad$v_bit31Q#define cNshad$l_special_events shad$r_special_events_overlay.shad$l_special_eventsz#define shad$v_quiescent_point_event shad$r_special_events_overlay.shad$r_special_events_bits.shad$v_quiescent_point_eventt#define shad$v_sequential_command shad$r_special_events_overlay.shad$r_special_events_bits.shad$v_sequential_commandr#define shad$v_membership_change shad$r_special_events_overlay.shad$r_special_events_bits.shad$v_membership_changet#define shad$v_prevent_mbr_change shad$r_special_events_overlay.shad$r_sdNpecial_events_bits.shad$v_prevent_mbr_changej#define shad$v_local_quiesce shad$r_special_events_overlay.shad$r_special_events_bits.shad$v_local_quiescep#define shad$v_trigger_validate shad$r_special_events_overlay.shad$r_special_events_bits.shad$v_trigger_validatel#define shad$v_sequential_nop shad$r_special_events_overlay.shad$r_special_events_bits.shad$v_sequential_nopE#define shad$l_wlg_status shad$r_wlg_status_overlay.shad$l_wlg_statusZ#define shad$v_local_wlg shad$r_wlg_status_overlay.shad$eNr_wlg_status_bits.shad$v_local_wlgx#define shad$v_evaluation_thread_active shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_evaluation_thread_activep#define shad$v_wlg_threshold_active shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_wlg_threshold_activep#define shad$v_whm_deal_timr_active shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_whm_deal_timr_activef#define shad$v_pending_wlg_off shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_pending_wlg_offd#define shad$v_pfNending_wlg_on shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_pending_wlg_onn#define shad$v_pending_wlg_off_scb shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_pending_wlg_off_scbl#define shad$v_pending_wlg_on_scb shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_pending_wlg_on_scbd#define shad$v_delete_entries shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_delete_entriesb#define shad$v_nf_tmp_in_use shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_nf_tmp_in_ugNset#define shad$v_cont_id_check_disabled shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_cont_id_check_disabledj#define shad$v_wlgprm_bad_status shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_wlgprm_bad_statusj#define shad$v_wlg100_bad_status shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_wlg100_bad_statusj#define shad$v_wlglck_bad_status shad$r_wlg_status_overlay.shad$r_wlg_status_bits.shad$v_wlglck_bad_statusn#define shad$v_get_lock_map_failed shad$r_wlg_status_overlayhN.shad$r_wlg_status_bits.shad$v_get_lock_map_failedH#define shad$w_wlg_control shad$r_wlg_control_overlay.shad$w_wlg_control`#define shad$v_disable_wlg shad$r_wlg_control_overlay.shad$r_wlg_control_bits.shad$v_disable_wlg^#define shad$v_enable_wlg shad$r_wlg_control_overlay.shad$r_wlg_control_bits.shad$v_enable_wlgN#define shad$w_drain_io_flag shad$r_drain_io_flag_overlay.shad$w_drain_io_flagb#define shad$v_drain_io_0 shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_0b#definiNe shad$v_drain_io_1 shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_1b#define shad$v_drain_io_2 shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_2b#define shad$v_drain_io_3 shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_3b#define shad$v_drain_io_4 shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_4b#define shad$v_drain_io_5 shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_5b#define shadjN$v_drain_io_6 shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_6b#define shad$v_drain_io_7 shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_7b#define shad$v_drain_io_8 shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_8b#define shad$v_drain_io_9 shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_9b#define shad$v_drain_io_a shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_ab#define shad$v_drakNin_io_b shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_bb#define shad$v_drain_io_c shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_cb#define shad$v_drain_io_d shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_db#define shad$v_drain_io_e shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_eb#define shad$v_drain_io_f shad$r_drain_io_flag_overlay.shad$r_drain_io_flag_bits.shad$v_drain_io_fL#define shad$l_thresholdlN_bias shad$r_threshold_overlay.shad$l_threshold_biaso#define shad$w_threshold_io_count shad$r_threshold_overlay.shad$r_threshold_overlay_2.shad$w_threshold_io_countm#define shad$w_threshold_seconds shad$r_threshold_overlay.shad$r_threshold_overlay_2.shad$w_threshold_seconds>#define shad$l_wbm_handle shad$r_wbm_overlay.shad$l_wbm_handleY#define shad$v_shadowing_level_bit0 shad$r_valblk_offset_bits.shad$v_shadowing_level_bit0Y#define shad$v_shadowing_level_bit1 shad$r_valblk_offset_bits.shad$v_smNhadowing_level_bit1Y#define shad$v_shadowing_level_bit2 shad$r_valblk_offset_bits.shad$v_shadowing_level_bit2Y#define shad$v_shadowing_level_bit3 shad$r_valblk_offset_bits.shad$v_shadowing_level_bit3U#define shad$l_hbmm_wbm_mst_hndl shad$r_shad_wbm_mst_overlay.shad$l_hbmm_wbm_mst_hndl_#define shad$l_hbmm_wbm_master_handle shad$r_shad_wbm_mst_overlay.shad$l_hbmm_wbm_master_handleC#define shad$l_copy_hotblocks shad$r_copy_hot.shad$l_copy_hotblocksC#define shad$w_copy_hotblocks shad$r_copy_ho nNt.shad$w_copy_hotblocksE#define shad$l_copy_collisions shad$r_copy_col.shad$l_copy_collisionsE#define shad$w_copy_collisions shad$r_copy_col.shad$w_copy_collisions6#define shad$l_irp shad$r_shadend_structure.shad$l_irpH#define shad$l_shadend_plus shad$r_shadend_structure.shad$l_shadend_plus"#endif /* #if !defined(__VAXC) */ N/*++ */N/* Volume Shadowing Host-Based Mini Merge "Evaluate Policy" structure. */N/* oN */Q/* The HBMM_EP is used to trigger a cluster-wide "evaluate policy" event for a */N/* specific VU. This structure is allocated and deallocate by SHDRIVER as */N/* its needed. When it exists, SHAD$PS_HBMM_EP contains a pointer to it. */N/* */N/*-- */ N#define HBMM_EP$K_LENGTHpN 424 /* Length of Structure */N#define HBMM_EP$C_LENGTH 424 /* Length of Structure */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _hbmm_ep {#pragma __nomember_alignmentN qN struct _ucb *hbmm_ep$ps_vu_ucb; /* Unit Control Block for VU */N struct _shad *hbmm_ep$ps_shad; /* SHAD for the VU */N unsigned short int hbmm_ep$w_size; /* Size of this structure, bytes */N unsigned char hbmm_ep$b_type; /* Structure type: DYN$C_MISC */N unsigned char hbmm_ep$b_subtype; /* Structure subtype: DYN$C_HBMM_EP */N unsigned int hbmm_ep$l_flags; /* Miscellaneous flags */c#if !defined(__NOBASEALIGN_S rNUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifP LOCK hbmm_ep$r_pc_lock; /* ($HBMMpc) Policy Change mutex lock */g LOCK hbmm_ep$r_sc_lock; /* ($HBMMsc) Serialize Create lock, summary status in valblk */U LOCK hbmm_ep$r_ep_lock; /* ($HBMMep) Evaluate Policy doorbell lock */ } HBMM_EP;#define ANLSHAD$M_BRIEF 0x1 #define ANLSHAD$M_STATsNISTICS 0x2#define ANLSHAD$M_IGNORE 0x4!#define ANLSHAD$M_FILE_SYSTEM 0x8#define ANLSHAD$M_ALL 0x10#define ANLSHAD$M_SCB 0x20%#define ANLSHAD$M_NOT_CONSISTENT 0x40 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _anlflags {#pragma __nomember_alignment __union { int anlshad$l_bits; __struct {N tNunsigned anlshad$v_brief : 1; /* /Brief */N unsigned anlshad$v_statistics : 1; /* /Statistics */N unsigned anlshad$v_ignore : 1; /* /Ignore */N unsigned anlshad$v_file_system : 1; /* /BLOCK=FILE */N unsigned anlshad$v_all : 1; /* /BLOCK=ALL */N unsigned anlshad$v_scb : 1; /* Block is an SCB */R unsigned anlshad$v_not_con uNsistent : 1; /* Set may not be consistent */+ unsigned anlshad$v_fill_8_ : 1; } anlshad$r_fill_7_; } anlshad$r_fill_6_; } ANLFLAGS; #if !defined(__VAXC)K#define anlshad$v_brief anlshad$r_fill_6_.anlshad$r_fill_7_.anlshad$v_briefU#define anlshad$v_statistics anlshad$r_fill_6_.anlshad$r_fill_7_.anlshad$v_statisticsM#define anlshad$v_ignore anlshad$r_fill_6_.anlshad$r_fill_7_.anlshad$v_ignoreW#define anlshad$v_file_system anlshad$r_fill_6_.anlshad$r_fi vNll_7_.anlshad$v_file_systemG#define anlshad$v_all anlshad$r_fill_6_.anlshad$r_fill_7_.anlshad$v_allG#define anlshad$v_scb anlshad$r_fill_6_.anlshad$r_fill_7_.anlshad$v_scb]#define anlshad$v_not_consistent anlshad$r_fill_6_.anlshad$r_fill_7_.anlshad$v_not_consistent"#endif /* #if !defined(__VAXC) */ N/* */N/* This is the end of the SDL file. */N/* wN */ #define shaddef _shad $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SHADDEF_LOADED */ ww0[UM/***************************************************************************xN/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** yN **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** zN **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 10-JUL-2023 18:09:06 $1$DGA8345:[LIB_H.SRC]SHLDEF.SDL;1 *//***************************************************************************************************************************** {N***//*** MODULE $SHLDEF ***/#ifndef __SHLDEF_LOADED#define __SHLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#end|Nif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ }N */N/* SHL - SHAREABLE IMAGE LIST */N/* */N/* THIS LIST IS CREATED IN THE IMAGE FIXUP SECTION BY THE LINKER AND */N/* USED BY THE IMAGE ACTIVATOR FOR DOING SHAREABLE IMAGE FIXUPS. */N/*- */#define SHL$M_FIXUP 0x1N#define SHL$C_OLD_SHL_SIZE 56 /* Size of "old" SHL ~N */N#define SHL$C_MAXNAMLNG 39 /* Maximum length of image name */U#define SHL$K_LENGTH 68 /* Length of shareable image list element */U#define SHL$C_LENGTH 68 /* Length of shareable image list element */#define SHL$S_SHLDEF 68 typedef struct _shl {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */S void N *shl$q_baseva; /* Base address of this shareable image */#else unsigned __int64 shl$q_baseva;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifR struct _shl *shl$l_shlptr; /* Pointer from SHL in shareable image */N/* to associated SHL in executable image */N unsigned int shl$l_ident N; /* GSMATCH */O void *shl$l_permctx; /* Permanent sharable image context */N char shl$b_shl_size; /* Size of SHL elements */N short int shldef$$_fill_1; /* Spare for extensions */ __union {N unsigned char shl$b_flags; /* Flags */ __struct {Z unsigned shl$v_fixup : 1; /* Fixups against this shareable have been done */' N unsigned shl$v_fill_2_ : 7; } shl$r_fill_1_; } shl$r_fill_0_;P void *shl$l_icb; /* Address of the image control block */ __union {R char shl$t_imgnam [40]; /* Shareable image name (ASCIC string) */N char shl$b_namlng; /* Synonym for name count */ } shl$r_imgnam_overlay; } SHL; #if !defined(__VAXC)-#define shl$b_flags shl$r_fill_0_.shl$b_flags;#define shl$v_fixup shl$r_fi Nll_0_.shl$r_fill_1_.shl$v_fixup6#define shl$t_imgnam shl$r_imgnam_overlay.shl$t_imgnam6#define shl$b_namlng shl$r_imgnam_overlay.shl$b_namlng"#endif /* #if !defined(__VAXC) */ N/* Generic names for common fields with different sizes. */N/* x86, c macros */ !#define shl$$_baseva shl$q_basevaN/* x86, bliss macros */ $#pragma __member_alignment __restoreNR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SHLDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This softwarNe is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidNential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***** N***************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:34 by OpenVMS SDL V3.7 */H/* Source: 22-OCT-1998 13:27:49 $1$DGA8345:[LIB_H.SRC]SHMEMDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SHMEMDEF ***/#ifndef __SHMEMDEF_LOADED#define __SHMEMDEF_LOADED 1 G#pragma __nostandard N /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#eNlse#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Shared Memory Management Definitions. The shared memory management */N/* structure conta Nins the data needed to manage shared memory in a Galaxy. */N/* */  Z#include /* Define the SHM_ID type; SHMEM contains embedded SHM_ID types */#define SHMEM$M_SHMEM_VALID 0x1$#define SHMEM$M_INIT_IN_PROGRESS 0x2#define SHMEM$M_SHMEM_DEBUG 0x4"#define SHMEM$M_SHM_CPP_TESTED 0x8(#define SHMEM$M_RESERVED_BITS 0xFFFFFFF0N#define SHMEM$C_LENGTH 256 /* Length of SHMEM */ N c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _shmem {#pragma __nomember_alignmentN unsigned __int64 shmem$q_init_time; /* Time of shared memory init */N unsigned short int shmem$w_mbo; /* Must be one */N unsigned char shmem$b_type; /* Dynamic structure type */N unsigned chaNr shmem$b_subtype; /* Dynamic structure subtype */N unsigned int shmem$l_version; /* Structure version number */N unsigned __int64 shmem$q_size; /* Size of the structure */ __union {N unsigned int shmem$l_flags; /* FLAGS longword */ __struct {N unsigned shmem$v_shmem_valid : 1; /* SHMEM is valid */V unsigned shmem$v_init_in_progress : 1; /* Initialization is in progress N*/O unsigned shmem$v_shmem_debug : 1; /* Debug structures are in use */a unsigned shmem$v_shm_cpp_tested : 1; /* All pages in all SHM_CPPs have been tested */0 unsigned shmem$v_reserved_bits : 28;! } shmem$r_flags_bits; } shmem$r_flags_overlay;N unsigned int shmem$l_creator_gnode; /* Creator's gNode id */N unsigned __int64 shmem$q_spare0; /* Unused */N unsigned __int64 shmem$q_spare1; N/* Unused */N unsigned __int64 shmem$q_spare2; /* Unused */N unsigned __int64 shmem$q_spare3; /* Unused */N unsigned int shmem$l_max_cpp_count; /* Maximum number of SHM_CPPs */N unsigned int shmem$l_valid_cpp_count; /* Total number of valid SHM_CPPs */R unsigned __int64 shmem$q_shm_cpp_size; /* Size of one SHM_CPP array element */N unsigned __int64 shmem$q_cpp_array_off; /* Offset to the SNHM_CPP array */N unsigned __int64 shmem$q_spare10; /* Unused */N unsigned __int64 shmem$q_spare11; /* Unused */N unsigned __int64 shmem$q_spare12; /* Unused */N unsigned __int64 shmem$q_spare13; /* Unused */N unsigned __int64 shmem$q_spare14; /* Unused */N unsigned __int64 shmem$q_spare15; /* Unused */N unsiNgned __int64 shmem$q_spare16; /* Unused */N unsigned __int64 shmem$q_spare17; /* Unused */N unsigned __int64 shmem$q_spare18; /* Unused */N unsigned __int64 shmem$q_glock_off; /* Offset to gLock structure */N unsigned __int64 shmem$q_glock_handle; /* GLock handle */N unsigned int shmem$l_max_reg_count; /* Maximum number of SHM_REGs */Q unsigned int shmem$l_valid_regN_count; /* Total number of valid regions */R unsigned __int64 shmem$q_shm_reg_size; /* Size of one SHM_REG array element */N unsigned __int64 shmem$q_tag_array_off; /* Offset to the SHM_TAG array */N unsigned __int64 shmem$q_reg_array_off; /* Offset to the SHM_REG array */N unsigned __int64 shmem$q_spare20; /* Unused */N unsigned __int64 shmem$q_spare21; /* Unused */N unsigned __int64 shmem$q_spare22; /* Unused N */N unsigned __int64 shmem$q_spare23; /* Unused */N unsigned __int64 shmem$q_spare24; /* Unused */N unsigned __int64 shmem$q_spare25; /* Unused */ } SHMEM; #if !defined(__VAXC)9#define shmem$l_flags shmem$r_flags_overlay.shmem$l_flagsX#define shmem$v_shmem_valid shmem$r_flags_overlay.shmem$r_flags_bits.shmem$v_shmem_validb#define shmem$v_init_in_progress shmem$r_flags_oNverlay.shmem$r_flags_bits.shmem$v_init_in_progressX#define shmem$v_shmem_debug shmem$r_flags_overlay.shmem$r_flags_bits.shmem$v_shmem_debug^#define shmem$v_shm_cpp_tested shmem$r_flags_overlay.shmem$r_flags_bits.shmem$v_shm_cpp_tested\#define shmem$v_reserved_bits shmem$r_flags_overlay.shmem$r_flags_bits.shmem$v_reserved_bits"#endif /* #if !defined(__VAXC) */ N/* */N/* Shared Memory Management Flags (not to be confused Nwith SHMEM_FLAGS in */N/* GLXDEF). These flags are stored in GLX$GL_SHMEM_FLAGS. */N/* */#define SHMEM$M_VALID 0x1#define SHMEM$M_SUSPECT 0x2'#define SHMEM$M_RECOVER_IN_PROGRESS 0x4$#define SHMEM$M_EXIT_IN_PROGRESS 0x8)#define SHMEM$M_FLAGS_RESERVED 0xFFFFFFF0 !typedef struct _glx_shmem_flags { __union {) unsigned int shmem$l_shmem_flags; __struct {N unsi Ngned shmem$v_valid : 1; /* Shared memory is valid */N unsigned shmem$v_suspect : 1; /* Shared memory is suspect */^ unsigned shmem$v_recover_in_progress : 1; /* Shared memory recovery in progress */W unsigned shmem$v_exit_in_progress : 1; /* Shared memory exit in progress */1 unsigned shmem$v_flags_reserved : 28;' } shmem$r_shmem_flags_bits;& } shmem$r_shmem_flags_overlay; } GLX_SHMEM_FLAGS; #if !defined(_N_VAXC)K#define shmem$l_shmem_flags shmem$r_shmem_flags_overlay.shmem$l_shmem_flagsX#define shmem$v_valid shmem$r_shmem_flags_overlay.shmem$r_shmem_flags_bits.shmem$v_valid\#define shmem$v_suspect shmem$r_shmem_flags_overlay.shmem$r_shmem_flags_bits.shmem$v_suspectt#define shmem$v_recover_in_progress shmem$r_shmem_flags_overlay.shmem$r_shmem_flags_bits.shmem$v_recover_in_progressn#define shmem$v_exit_in_progress shmem$r_shmem_flags_overlay.shmem$r_shmem_flags_bits.shmem$v_exit_in_progressj#defin Ne shmem$v_flags_reserved shmem$r_shmem_flags_overlay.shmem$r_shmem_flags_bits.shmem$v_flags_reserved"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Mtypedef struct _shmem * SHMEM_PQ; /* Long pointer to a SHMEM structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else"typedef Nunsigned __int64 SHMEM_PQ;##endif /* __INITIAL_POINTER_SIZE */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SHMEMDEF_LOADED */ ww[UM/***************************************************************************/M/*N* **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** N **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** N **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:34 by OpenVMS SDL V3.7 */J/* Source: 27-JUL-2005 15:03:05 $1$DGA8345:[LIB_H.SRC]SHM_CPPDEF.SDL;1 *//******************************************************************************************************************************* N*//*** MODULE $SHM_CPPDEF ***/#ifndef __SHM_CPPDEF_LOADED#define __SHM_CPPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointersN */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* N */O/* Shared Memory CPP Definitions. The shared memory CPP structure contains */N/* the data needed to manage the physical pages within a shared memory CPP. */N/* */  U#include /* Define the PMAP type; SHM_CPP contains embedded PMAP types */#define SHM_CPP$M_VALID 0x1&#define SHM_CPP$M_INIT_IN_PROGRESS 0x2*#define SHM_CPP$M_RESERVED_2_31 0xFFFFFFFCN#define SHM_CPP$C_LENGTH 192 N /* Length of SHM_CPP */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _shm_cpp {#pragma __nomember_alignmentN unsigned __int64 shm_cpp$q_spare1; /* Spare */N unsigned short int shm_cpp$w_mbo; /* Must be one */N unsigned char shm_cpp$b_type; /* Dyn Namic structure type */N unsigned char shm_cpp$b_subtype; /* Dynamic structure subtype */N unsigned int shm_cpp$l_version; /* Structure version number */N unsigned __int64 shm_cpp$q_size; /* Size of the structure */ __union {N unsigned int shm_cpp$l_flags; /* FLAGS longword */ __struct {N unsigned shm_cpp$v_valid : 1; /* SHM_CPP is valid */X unsigned shm_cpp$v_iniNt_in_progress : 1; /* Initialization is in progress */2 unsigned shm_cpp$v_reserved_2_31 : 30;# } shm_cpp$r_flags_bits;" } shm_cpp$r_flags_overlay;R unsigned int shm_cpp$l_max_fragments; /* Maximum number of memory fragments */N unsigned int shm_cpp$l_fragment_count; /* Number of memory fragments */N unsigned __int64 shm_cpp$q_pmap_off; /* Offset to PMAP array */W unsigned __int64 shm_cpp$q_pfndb_pmap_off; /* Offset to PFNDB PMAP array N */N unsigned __int64 shm_cpp$q_spare2; /* Spare */N unsigned __int64 shm_cpp$q_spare3; /* Spare */N unsigned __int64 shm_cpp$q_spare4; /* Spare */N unsigned __int64 shm_cpp$q_spare5; /* Spare */N unsigned __int64 shm_cpp$q_glock_off; /* Offset to gLock structure */N unsigned __int64 shm_cpp$q_glock_handle; /* Handle for gLock */N unsigned __i Nnt64 shm_cpp$q_gnode_off; /* Offset to gNode bitmask block */N unsigned __int64 shm_cpp$q_spare10; /* Spare */ char shm_cpp$b_fill_0_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifZ PLNK shm_cpp$r_free_list; /* First PFN in free page list/total free pages */X PLNK shm_cpp$r_bad_list; /* Fir Nst PFN in bad page list/total bad pages */b PLNK shm_cpp$r_untested_list; /* First PFN in untested page list/total untested pages */#pragma __nomember_alignmentN unsigned __int64 shm_cpp$q_spare12; /* Spare */N unsigned __int64 shm_cpp$q_spare13; /* Spare */N unsigned __int64 shm_cpp$q_spare14; /* Spare */ } SHM_CPP; #if !defined(__VAXC)?#define shm_cpp$l_flags shm_cpp$r_flags_overlay.sh Nm_cpp$l_flagsT#define shm_cpp$v_valid shm_cpp$r_flags_overlay.shm_cpp$r_flags_bits.shm_cpp$v_validj#define shm_cpp$v_init_in_progress shm_cpp$r_flags_overlay.shm_cpp$r_flags_bits.shm_cpp$v_init_in_progressd#define shm_cpp$v_reserved_2_31 shm_cpp$r_flags_overlay.shm_cpp$r_flags_bits.shm_cpp$v_reserved_2_31"#endif /* #if !defined(__VAXC) */  =typedef unsigned int SHM_CPP_ID; /* Shared memory CPP id */#ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save curren Nt pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Stypedef struct _shm_cpp * SHM_CPP_PQ; /* Long pointer to a SHM_CPP structure. */Ltypedef unsigned int * SHM_CPP_ID_PQ; /* Long pointer to a SHM_CPP_ID */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else$typedef unsigned __int64 SHM_CPP_PQ;'typedef unsigned __int64 SHM_CPP_ID_PQ;##endif /* __INITIAL_POINTER_SIZE */  $#pragma __member_alignment __rNestoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SHM_CPPDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. Thb THREAD_MACROS*SpTIEDEF0STITANDEFITTLBDEFVTTLVDEF_TTMCDEFlTTQEDEFT TQEIDXDEFT:TRDDEFT>TSRVDEFT TSUNAMIDEFU TTYDEFU TTYDIALTYPU8TTYILDEFUTTYISDEFU TTYMDMDEFVTTYRBDEFV TTYSYMDEF3VhTTYTADEF=V TTYUCBDEFV TTYVECDEFVUAFDEFVUASDEFWUBMDDEFWUCBDEFVCONS_ROUTINESL VMS_CONSOLE VMS_DRIVERS^ VMS_MACROSF VMS_RANDOMX86_CPUID_INFO YMF262_REGNis software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This softwareN is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************************************************** N//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:33 by OpenVMS SDL V3.7 */K/* Source: 22-OCT-1998 13:27:36 $1$DGA8345:[LIB_H.SRC]SHM_DESCDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SHM_DESCDEF ***/#ifndef __SHM_DESCDEF_LOADED#define __SHM_DESCDEF_LOADED 1 NG#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __opNtional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Shared Memory Region Descriptor Definitions -- The shared memory region N*/N/* descriptor structure contains node private needed to manage the shared */N/* memory regions that this node is attached to. */N/* */  \#include /* Define the SHM_ID type; SHM_REG contains embedded SHM_ID types */L#include /* Define PTE type; SHM_REG contains an embedded PTE */#define SHM_DESC$M_ATTACHED 0x1!#define SHM_DESC$M_GLX_GBLSEC 0x2##define SHM_ NDESC$M_SYS_VA_VALID 0x4$#define SHM_DESC$M_ATTACH_DETACH 0x8+#define SHM_DESC$M_RESERVED_4_31 0xFFFFFFF0N#define SHM_DESC$C_LENGTH 128 /* Length of SHM_DESC */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _shm_desc {#pragma __nomember_alignmentN unsigned __int64 shm_desc$q_spare1; /* Spare N */N unsigned short int shm_desc$w_mbo; /* Must be one */N unsigned char shm_desc$b_type; /* Dynamic structure type */N unsigned char shm_desc$b_subtype; /* Dynamic structure subtype */N unsigned int shm_desc$l_version; /* Structure version number */N unsigned __int64 shm_desc$q_size; /* Size of the structure */ __union {N unsigned int shm_desc$l_flags; /* FLAGS longword N */ __struct {T unsigned shm_desc$v_attached : 1; /* Node is attached to this SHM_REG */P unsigned shm_desc$v_glx_gblsec : 1; /* Region is a global section */Z unsigned shm_desc$v_sys_va_valid : 1; /* Region is mapped into system space */f unsigned shm_desc$v_attach_detach : 1; /* Callback routine called for attach and detach */3 unsigned shm_desc$v_reserved_4_31 : 28;$ } shm_desc$r_flags_bits;# } shm_desc$r_fNlags_overlay;N unsigned int shm_desc$l_spare2; /* Spare */] __int64 shm_desc$q_io_refcnt; /* Node private I/O reference count for the region */g __int64 shm_desc$q_bo_refcnt; /* Node private buffer object reference count for the region */N SHM_ID shm_desc$r_shm_id; /* SHM_ID of this region */N unsigned __int64 shm_desc$q_virt_length; /* Virtual length in bytes */R#ifdef __INITIAL_POINTER_SIZE /* Defined when Never ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N int (*shm_desc$pq_callback_routine)(); /* Address of callback routine */#else/ unsigned __int64 shm_desc$pq_callback_routine;#endifU unsigned __int64 shm_desc$q_context; /* Additional context specified by caller */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size N default to 64-bit pointers */S void *shm_desc$pq_gblsec_map_list; /* Pointer to list of GBL_MAP structures */#else. unsigned __int64 shm_desc$pq_gblsec_map_list;#endifN/* (Change to proper type when GBL_MAP is defined) */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *shm_desc$pq_sys_va; /* Address m Napped to this region */#else% unsigned __int64 shm_desc$pq_sys_va;#endifU unsigned int shm_desc$l_gstx; /* GSTX if this region is a global section */ } shm_desc$r_va_overlay;S PTE shm_desc$r_proto_pte; /* Prototype PTE used to map this region */N unsigned int shm_desc$l_spare3; /* Spare */N unsigned int shm_desc$l_spare4; /* Spare */N unsigned int shm_desc$l_spare5; /* Spare N */N unsigned int shm_desc$l_spare6; /* Spare */N unsigned int shm_desc$l_spare7; /* Spare */N unsigned int shm_desc$l_spare8; /* Spare */ } SHM_DESC; #if !defined(__VAXC)B#define shm_desc$l_flags shm_desc$r_flags_overlay.shm_desc$l_flags^#define shm_desc$v_attached shm_desc$r_flags_overlay.shm_desc$r_flags_bits.shm_desc$v_attachedb#define shm_desc$v_glx_gblsec shNm_desc$r_flags_overlay.shm_desc$r_flags_bits.shm_desc$v_glx_gblsecf#define shm_desc$v_sys_va_valid shm_desc$r_flags_overlay.shm_desc$r_flags_bits.shm_desc$v_sys_va_validh#define shm_desc$v_attach_detach shm_desc$r_flags_overlay.shm_desc$r_flags_bits.shm_desc$v_attach_detachh#define shm_desc$v_reserved_4_31 shm_desc$r_flags_overlay.shm_desc$r_flags_bits.shm_desc$v_reserved_4_31C#define shm_desc$pq_sys_va shm_desc$r_va_overlay.shm_desc$pq_sys_va=#define shm_desc$l_gstx shm_desc$r_va_overlay.shm_deNsc$l_gstx"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Utypedef struct _shm_desc * SHM_DESC_PQ; /* Long pointer to a SHM_DESC structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else%typedef unsigned __int64 SHM_DESC_PQ;##endif /* __INITIAL_POINTER_SIZE */  $#praNgma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __SHM_DESCDEF_LOADED */ ww[UM/***************************************************************************/M/** **N/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC.N CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************************************N****************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:28 by OpenVMS SDL V3.7 */I/* Source: 18-DEC-1997 10:35:09 $1$DGA8345:[LIB_H.SRC]SHM_IDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SHM_IDDEF ***/#ifndef __SHM_IDDEF_LOADED#define __SH NM_IDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_paraNms ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Shared Memory ID Definition. The shared memory regioNn ID is the */N/* handle used to identify a shared memory region. */N/* */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _shm_id {#pragma __nomember_alignment __union { __struct { __union {N N unsigned int shm_id$l_short_id; /* Index and extent only */ __struct {U unsigned short int shm_id$w_index; /* Index into SHM_REG array */N unsigned short int shm_id$w_extent; /* Unused for V1.0 */, } shm_id$r_index_extent;( } shm_id$r_low_longword;N unsigned int shm_id$l_seq_num; /* Sequence number */! } shm_id$r_id_fields;( unsigned __int64 shm_i Nd$q_ident; } shm_id$r_quad_id; } SHM_ID; #if !defined(__VAXC)e#define shm_id$l_short_id shm_id$r_quad_id.shm_id$r_id_fields.shm_id$r_low_longword.shm_id$l_short_idu#define shm_id$w_index shm_id$r_quad_id.shm_id$r_id_fields.shm_id$r_low_longword.shm_id$r_index_extent.shm_id$w_indexw#define shm_id$w_extent shm_id$r_quad_id.shm_id$r_id_fields.shm_id$r_low_longword.shm_id$r_index_extent.shm_id$w_extentM#define shm_id$l_seq_num shm_id$r_quad_id.shm_id$r_id_fields.shm_id$l_seq_nu Nm6#define shm_id$q_ident shm_id$r_quad_id.shm_id$q_ident"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Qtypedef struct _shm_id * SHM_ID_PQ; /* Long pointer to a SHM_ID structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else#typedef unsigned __int64 SHM_ID_PQ;##endif /N* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SHM_IDDEF_LOADED */ ww:[UM/***************************************************************************/M/** N **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** N **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********N****************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:34 by OpenVMS SDL V3.7 */J/* Source: 22-OCT-1998 13:28:14 $1$DGA8345:[LIB_H.SRC]SHM_REGDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SHM_REGDEF ***/#ifn Ndef __SHM_REGDEF_LOADED#define __SHM_REGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplusN extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Shared Memory N Region Definitions. The shared memory region structure */N/* contains the data needed to manage the pages within a shared memory */N/* region. */N/* */  X#include /* Define the MMAP type; SHM_REG contains an embedded MMAP type */\#include /* Define the SHM_ID type; SHM_REG contains embedded SHM_ID types */#define SH NM_REG$M_VALID 0x1&#define SHM_REG$M_INIT_IN_PROGRESS 0x2*#define SHM_REG$M_SHARED_CONTEXT_VALID 0x4##define SHM_REG$M_ATTACH_DETACH 0x8#define SHM_REG$M_DELETED 0x10)#define SHM_REG$M_DELETE_IN_PROGRESS 0x20*#define SHM_REG$M_RESERVED_6_31 0xFFFFFFC0N#define SHM_REG$C_LENGTH 288 /* Length of SHM_REG */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma N__nomember_alignment#endiftypedef struct _shm_reg {#pragma __nomember_alignmentN unsigned __int64 shm_reg$q_spare1; /* Spare */N unsigned short int shm_reg$w_mbo; /* Must be one */N unsigned char shm_reg$b_type; /* Dynamic structure type */N unsigned char shm_reg$b_subtype; /* Dynamic structure subtype */N unsigned int shm_reg$l_version; /* Structure version number */N unsigned __intN64 shm_reg$q_size; /* Size of the structure */ __union {N unsigned int shm_reg$l_flags; /* FLAGS longword */ __struct {N unsigned shm_reg$v_valid : 1; /* SHM_REG is valid */X unsigned shm_reg$v_init_in_progress : 1; /* Initialization is in progress */Z unsigned shm_reg$v_shared_context_valid : 1; /* Context in SHM_REG is valid */\ unsigned shm_reg$v_attach_detach : 1; /* Nodes expec Nt attach/detach callbacks */N unsigned shm_reg$v_deleted : 1; /* The region is deleted */X unsigned shm_reg$v_delete_in_progress : 1; /* The region is being deleted */2 unsigned shm_reg$v_reserved_6_31 : 26;# } shm_reg$r_flags_bits;" } shm_reg$r_flags_overlay;V unsigned int shm_reg$l_spare2; /* To make everything else quadword aligned */N char shm_reg$t_tag [64]; /* "Name" of region */N SHM_ID sNhm_reg$r_shm_id; /* SHM_ID of this region */N unsigned __int64 shm_reg$q_create_time; /* Time of region creation */g unsigned __int64 shm_reg$q_shared_context; /* Shared context (global section ident, for example) */N unsigned __int64 shm_reg$q_spare2; /* Unused */Y MMAP shm_reg$r_mmap; /* Embedded MMAP to describe mapping of region */N unsigned __int64 shm_reg$q_glock_off; /* Offset to gLock structure */NN unsigned __int64 shm_reg$q_glock_handle; /* GLock handle */_ unsigned __int64 shm_reg$q_att_gnode_off; /* Offset to the attached gNode bitmask block */_ unsigned __int64 shm_reg$q_io_gnode_off; /* Offset to the I/O in progress bitmask block */T unsigned __int64 shm_reg$q_cpp_bitmask_off; /* Offset to the CPP bitmask lock */N unsigned __int64 shm_reg$q_spare3; /* Unused */N unsigned __int64 shm_reg$q_spare4; /* Unused N */N unsigned __int64 shm_reg$q_spare5; /* Unused */N unsigned __int64 shm_reg$q_spare6; /* Unused */N unsigned __int64 shm_reg$q_spare7; /* Unused */N unsigned __int64 shm_reg$q_spare8; /* Unused */N unsigned __int64 shm_reg$q_spare9; /* Unused */ } SHM_REG; #if !defined(__VAXC)?#define shm_reg$l_flags shm_reg$r_flags_overlay.Nshm_reg$l_flagsT#define shm_reg$v_valid shm_reg$r_flags_overlay.shm_reg$r_flags_bits.shm_reg$v_validj#define shm_reg$v_init_in_progress shm_reg$r_flags_overlay.shm_reg$r_flags_bits.shm_reg$v_init_in_progressr#define shm_reg$v_shared_context_valid shm_reg$r_flags_overlay.shm_reg$r_flags_bits.shm_reg$v_shared_context_validd#define shm_reg$v_attach_detach shm_reg$r_flags_overlay.shm_reg$r_flags_bits.shm_reg$v_attach_detachX#define shm_reg$v_deleted shm_reg$r_flags_overlay.shm_reg$r_flags_bits.shm_r Neg$v_deletedn#define shm_reg$v_delete_in_progress shm_reg$r_flags_overlay.shm_reg$r_flags_bits.shm_reg$v_delete_in_progressd#define shm_reg$v_reserved_6_31 shm_reg$r_flags_overlay.shm_reg$r_flags_bits.shm_reg$v_reserved_6_31"#endif /* #if !defined(__VAXC) */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _shm_msg {#pragma __nomemb Ner_alignmentN int shm_msg$l_reason; /* Reason for callback */N unsigned int shm_msg$l_gnode_id; /* Node initiating message */N SHM_ID shm_msg$r_shm_id; /* SHM_ID of this region */ } SHM_MSG; #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Stypedef struct _shm_reg * SHM_REG_PQ; /* Long point Ner to a SHM_REG structure. */etypedef struct _shm_reg ** SHM_REG_PPQ; /* Long pointer to a long pointer to a SHM_REG structure. */Rtypedef struct _shm_msg * SHM_MSG_PQ; /* Long pointer to a SHM_MSG structure */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else$typedef unsigned __int64 SHM_REG_PQ;%typedef unsigned __int64 SHM_REG_PPQ;$typedef unsigned __int64 SHM_MSG_PQ;##endif /* __INITIAL_POINTER_SIZE */  $#pragma __member_alignment __rNestoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SHM_REGDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. ThNis software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This softwareN is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************************************************************** N//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 23-APR-1993 14:38:51 $1$DGA8345:[LIB_H.SRC]SLVDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SLVDEF ***/#ifndef __SLVDEF_LOADED#define __SLVDEF_LOADED 1 G#pragma __nostanda Nrd /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...N#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* */N/* Define symbolNic offsets for System Loadable Vectors. These symbols */N/* are used by the various pieces of the loadable EXEC, notably SCSVEC, */N/* to create a list of vectors in system space and a corresponding image */N/* that will be loaded into pool and connected to the system vectors. */N/* */N/* */N#define SLV$K_LENGTH 676 /* N SLV$K_LENGTH */ typedef struct _slv {N unsigned int slv$l_codesize; /* Loadable image size (in bytes) */N unsigned int slv$l_initrtn; /* Offset to init. routine */N unsigned short int slv$w_size; /* Same as SLV$L_CODESIZE */N unsigned char slv$b_type; /* Structure type (DYN$C_LOADCODE) */N unsigned char slv$b_subtyp; /* Sturcture Subtype */N unsigned char slv$b_prot_r; N/* writeable protection for image */N unsigned char slv$b_prot_w; /* read-only protection for image */N unsigned short int slv$w_spare; /* spare field for future use */N void *slv$a_sysvecs; /* address of vectors in SYS.EXE */N char slv$t_facility [16]; /* facility name (.ASCIC) */N char slv$t_list [640]; /* Start of vector list (MAXVEC*5) */ } SLV;N/* N */N/* */N/* Define vector type codes. The codes LODUMMY and HIDUMMY are */N/* used as placeholders, to make the definition of the upper and */N/* lower bound vector type symbols automatic. New vector type codes */N/* should be added at the end of the list, but before HIDUMMY. */N/* */NN/* */N#define SLV$K_LODUMMY 0 /* */N#define SLV$K_LDATA 1 /* Longword pointer to data */N#define SLV$K_AJUMP 2 /* Aligned jump */N#define SLV$K_UJUMP 3 /* Unaligned jump */N#define SLV$K_SDATA 4 /* Specified data */N#define SLV$K_SJUMP 5 N /* Specified jump */N#define SLV$K_HIDUMMY 6 /* */N#define SLV$K_MINTYPE 1 /* Lower bound of vector type codes */N#define SLV$K_MAXTYPE 5 /* Upper bount of vector type codes */N#define SLV$K_MAXVEC 128 /* Max. # of vectors in list. */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragmNa __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SLVDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise DevNelopment, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not N **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************************* N*******************************/=/* Created: 7-Oct-2024 15:22:25 by OpenVMS SDL V3.7 */F/* Source: 21-FEB-1995 13:44:00 $1$DGA8345:[LIB_H.SRC]SMBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SMBDEF ***/#ifndef __SMBDEF_LOADED#define __SMBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __Nnomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !dNefined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* Symbiont interface definitions */N/*+ */N/* Symbolic definitions for the symbiont to job controller interface. */N/* N */I/* Public definitions of message types, item codes, and */I/* other constants utilied by the symbiont to job controller */I/* interface facility. */N/* */N/*- */N/* N*/I/* Structure level */N/* */N#define SMBMSG$K_STRUCTURE_LEVEL 1 /* Current structure level */N#define SMBMSG$K_STRUCTURE_LEVEL_1 1 /* Structure level 1 */V#define SMBMSG$K_ARCH_MAX_STREAMS 32 /* Architected maximum streams per symbiont */N/* */I/* Request header N */N/* */N#define SMBMSG$K_PAUSE_TASK 1 /* - STOP /QUEUE */N#define SMBMSG$K_RESET_STREAM 2 /* - STOP /QUEUE /RESET */N#define SMBMSG$K_RESUME_TASK 3 /* - START /QUEUE (when paused) */N#define SMBMSG$K_START_STREAM 4 /* - START /QUEUE (when stopped) */N#define SMBMSG$K_START_TASK 5 /* - taNsk available */N#define SMBMSG$K_STOP_STREAM 6 /* - STOP /QUEUE /NEXT */O#define SMBMSG$K_STOP_TASK 7 /* - STOP /QUEUE /ABORT or /REQUEUE */N#define SMBMSG$K_TASK_COMPLETE 8 /* - stream is idle */N#define SMBMSG$K_TASK_STATUS 9 /* - asynchronous status update */O#define SMBMSG$K_START_SYMBIONT 10 /* - symbiont creation confirmation */N#define SMBMSG$K_JOB_REQUEST 11 /* - request a job to be exec Nuted */N#define SMBMSG$K_MAX_REQUEST_CODE 12 /* MUST BE LAST */ typedef struct _request_header {N unsigned short int smbmsg$w_request_code; /* Request code */N/* Define request codes */N unsigned char smbmsg$b_structure_level; /* Message structure level */N unsigned char smbmsg$b_stream_index; /* Stream index */N unsigned int smbmsg$l_symbiont_id; /* Symbiont identiNfication */[ unsigned int smbmsg$l_job_id; /* Job number (or 0 if a queue-oriented request) */ } REQUEST_HEADER;N/* */I/* Item header */N/* */N#define SMBMSG$K_ACCOUNTING_DATA 1 /* - accounting information */N#define SMBMSG$K_ACCOUNT_NAME 2 /* - accoNunt name */N#define SMBMSG$K_AFTER_TIME 3 /* - /AFTER value */N#define SMBMSG$K_ALIGNMENT_PAGES 4 /* - /ALIGN count */N#define SMBMSG$K_BOTTOM_MARGIN 5 /* - trailing blank lines */N#define SMBMSG$K_CHARACTERISTICS 6 /* - /CHARACTERISTICS value */N#define SMBMSG$K_CHECKPOINT_DATA 7 /* - checkpoint information */N#define SMBMSG$K_CONDITION_VECTOR 8 /* - task error messages N*/N#define SMBMSG$K_DEVICE_NAME 9 /* - /ON value */N#define SMBMSG$K_DEVICE_STATUS 10 /* - device status */N#define SMBMSG$K_ENTRY_NUMBER 11 /* - job entry number */N#define SMBMSG$K_EXECUTOR_QUEUE 12 /* - this output queue */N#define SMBMSG$K_FILE_COPIES 13 /* - /COPIES value */N#define SMBMSG$K_FILE_COUNT 14 /* - current file copy number */N#define SMBMSG$K_FILE_NSETUP_MODULES 15 /* - file setup module list */N#define SMBMSG$K_FIRST_PAGE 16 /* - first page to print */N#define SMBMSG$K_FORM_LENGTH 17 /* - lines per page */N#define SMBMSG$K_FORM_NAME 18 /* - name of physical form */N#define SMBMSG$K_FORM_SETUP_MODULES 19 /* - form setup module list */N#define SMBMSG$K_FORM_WIDTH 20 /* - columns per line */N#define SMBMSG$K_FILE_IDENTIFICATION 21 /* - deNvice, fid, and did */N#define SMBMSG$K_FILE_SPECIFICATION 22 /* - file name */N#define SMBMSG$K_JOB_COPIES 23 /* - /JOB_COUNT value */N#define SMBMSG$K_JOB_COUNT 24 /* - current job copy number */N#define SMBMSG$K_JOB_NAME 25 /* - /NAME value */N#define SMBMSG$K_JOB_RESET_MODULES 26 /* - job reset module list */N#define SMBMSG$K_LAST_PAGE 27 /* - last page to print N */N#define SMBMSG$K_LEFT_MARGIN 28 /* - leading blank columns */N#define SMBMSG$K_LIBRARY_SPECIFICATION 29 /* - library name */N#define SMBMSG$K_MAXIMUM_STREAMS 30 /* - maximum supported symbiont */N#define SMBMSG$K_MESSAGE_VECTOR 31 /* - error messages to print */N#define SMBMSG$K_NOTE 32 /* - /NOTE value */N#define SMBMSG$K_PAGE_SETUP_MODULES 33 /* - page setup module list */N#define SMBMSG$K_PARNAMETER_1 34 /* - user parameter 1 */N#define SMBMSG$K_PARAMETER_2 35 /* - user parameter 2 */N#define SMBMSG$K_PARAMETER_3 36 /* - user parameter 3 */N#define SMBMSG$K_PARAMETER_4 37 /* - user parameter 4 */N#define SMBMSG$K_PARAMETER_5 38 /* - user parameter 5 */N#define SMBMSG$K_PARAMETER_6 39 /* - user parameter 6 */N#define SMBMSG$K_PARAMETER_7 40 /* - Nuser parameter 7 */N#define SMBMSG$K_PARAMETER_8 41 /* - user parameter 8 */N#define SMBMSG$K_PRINT_CONTROL 42 /* - printing control */N#define SMBMSG$K_PRIORITY 43 /* - queue priority */N#define SMBMSG$K_QUEUE 44 /* - generic queue name */N#define SMBMSG$K_REFUSE_REASON 45 /* - reason task refused */N#define SMBMSG$K_RELATIVE_PAGE 46 /* - /BACKWARD, /FORWARD valuesN */N#define SMBMSG$K_REQUEST_CONTROL 47 /* - request control */P#define SMBMSG$K_REQUEST_RESPONSE 48 /* - request code being responded to */N#define SMBMSG$K_RIGHT_MARGIN 49 /* - trailing blank columns */N#define SMBMSG$K_SEARCH_STRING 50 /* - /SEARCH value */N#define SMBMSG$K_SEPARATION_CONTROL 51 /* - separation control */N#define SMBMSG$K_STOP_CONDITION 52 /* - reason for print abort */N#define SMBMSG$KN_TIME_QUEUED 53 /* - time queued */N#define SMBMSG$K_TOP_MARGIN 54 /* - leading blank lines */N#define SMBMSG$K_UIC 55 /* - UIC of submittor */N#define SMBMSG$K_USER_NAME 56 /* - username */N#define SMBMSG$K_CHECKPOINT_FREQUENCY 57 /* - pages per checkpoint */N#define SMBMSG$K_QUEUING_CONTROL 58 /* - queuing control */^#define SMBMSG$K_RETRY_TIME 59 /* N - delta time at which symbiont should retry job */N#define SMBMSG$K_DEVICE_CONDITION 60 /* - device error messages */N#define SMBMSG$K_MESSAGE_FILE 61 /* - symbiont's message file */N#define SMBMSG$K_AGENT_PROFILE 62 /* - security info */#define SMBMSG$K_CPU_LIMIT 63##define SMBMSG$K_FILE_SEPARATION 64#define SMBMSG$K_LOG_QUEUE 65%#define SMBMSG$K_LOG_SPECIFICATION 66#define SMBMSG$K_LOG_SPOOL 67$#define SMBMSG$K_OPERATOR_REQUEST 68 N#define SMBMSG$K_WSDEFAULT 69#define SMBMSG$K_WSEXTENT 70#define SMBMSG$K_WSQUOTA 71##define SMBMSG$K_FILE_ATTRIBUTES 72(#define SMBMSG$K_FILE_ATTRIBUTES_SIZE 73"#define SMBMSG$K_JOB_ATTRIBUTES 74'#define SMBMSG$K_JOB_ATTRIBUTES_SIZE 75$#define SMBMSG$K_QUEUE_ATTRIBUTES 76)#define SMBMSG$K_QUEUE_ATTRIBUTES_SIZE 77"#define SMBMSG$K_SUBMITTER_EPID 78N/* */N#define SMBMSG$K_MAX_ITEM_CODE 79 /* MUST BE LAST N */ $typedef struct _smbmsg_item_header {N unsigned short int smbmsg$w_item_size; /* Item size */N unsigned short int smbmsg$w_item_code; /* Item code */N/* Define item codes */ } SMBMSG_ITEM_HEADER;O#define SMBMSG$S_ITEM_HEADER 4 /* Size (using prior aggregate name) */N/* */I/* ACCOUNTIN NG_DATA item */N/* */ !typedef struct _accounting_data {N unsigned int smbmsg$l_pages_printed; /* Pages printed */N unsigned int smbmsg$l_qio_puts; /* Lines printed */N unsigned int smbmsg$l_rms_gets; /* File reads */N unsigned int smbmsg$l_cpu_time; /* Processor time */ N } ACCOUNTING_DATA;N/* */I/* CHECKPOINT_DATA item */N/* */ !typedef struct _checkpoint_data {N unsigned char smbmsg$b_filler; /* Reserved */N unsigned char smbmsg$b_checkpoint_level; /* Checkpoint structure level */N unsigned short int smbmsg$w_offset; /* OffseNt into record */N unsigned int smbmsg$l_carcon; /* Carriage control */N unsigned int smbmsg$l_page; /* Page number */N unsigned int smbmsg$l_record_number; /* Record number */N __int64 smbmsg$q_user_key; /* User positioning key */ } CHECKPOINT_DATA;N/* */I/* DEVICE_STATUS item N */N/* */#define SMBMSG$M_LOWERCASE 0x1#define SMBMSG$M_PAUSE_TASK 0x2#define SMBMSG$M_REMOTE 0x4#define SMBMSG$M_SERVER 0x8#define SMBMSG$M_STALLED 0x10!#define SMBMSG$M_STOP_STREAM 0x20#define SMBMSG$M_TERMINAL 0x40!#define SMBMSG$M_UNAVAILABLE 0x80##define SMBMSG$M_SYM_NOTIFIES 0x100(#define SMBMSG$M_SYM_REQUESTS_OPER 0x200&#define SMBMSG$M_SYM_COPIES_FILE 0x400%#define SMBMSG$M_S NYM_COPIES_JOB 0x800-#define SMBMSG$M_SYM_ACCEPTS_ALL_FORMS 0x1000-#define SMBMSG$M_SYM_NO_JOB_CHECKPOINT 0x2000.#define SMBMSG$M_SYM_ALL_CHARACTERISTIC 0x4000+#define SMBMSG$M_NOTIFY_ON_INTERRUPT 0x8000 typedef struct _device_status { __union {N unsigned int smbmsg$l_device_flags; /* Device flags */ __struct {N unsigned smbmsg$v_lowercase : 1; /* - supports lowercase */O unsigned smbmsg$v_pause_task : 1; /* - symbioNnt initiated pause */N unsigned smbmsg$v_remote : 1; /* - device is remote */N unsigned smbmsg$v_server : 1; /* - server symbiont */N unsigned smbmsg$v_stalled : 1; /* - task stalled */W unsigned smbmsg$v_stop_stream : 1; /* - symbiont requesting stop stream */N unsigned smbmsg$v_terminal : 1; /* - device is a terminal */N unsigned smbmsg$v_unavailable : 1; /* - device unavailable N */^ unsigned smbmsg$v_sym_notifies : 1; /* - Symbiont notifies for job completions */b unsigned smbmsg$v_sym_requests_oper : 1; /* - Symbiont generates operator messages */c unsigned smbmsg$v_sym_copies_file : 1; /* - Symbiont generates multiple file copies */a unsigned smbmsg$v_sym_copies_job : 1; /* - Symbiont generates multiple job copies */c unsigned smbmsg$v_sym_accepts_all_forms : 1; /* - Symbiont processes all form types */ Nh unsigned smbmsg$v_sym_no_job_checkpoint : 1; /* - Always reprocess full job on a restart */i unsigned smbmsg$v_sym_all_characteristic : 1; /* - Symbiont processes all characteristics */g unsigned smbmsg$v_notify_on_interrupt : 1; /* - Symbiont notifies user on job interrupt */N unsigned smbmsg$v_filler : 16; /* - force longword */ } smbmsg$r_fill_1_; } smbmsg$r_fill_0_; } DEVICE_STATUS; #if !defined(_O_VAXC)D#define smbmsg$l_device_flags smbmsg$r_fill_0_.smbmsg$l_device_flagsO#define smbmsg$v_lowercase smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_lowercaseQ#define smbmsg$v_pause_task smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_pause_taskI#define smbmsg$v_remote smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_remoteI#define smbmsg$v_server smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_serverK#define smbmsg$v_stalled smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_stalledS#define smbmsg$v_stop_stream smbOmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_stop_streamM#define smbmsg$v_terminal smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_terminalS#define smbmsg$v_unavailable smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_unavailableU#define smbmsg$v_sym_notifies smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_sym_notifies_#define smbmsg$v_sym_requests_oper smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_sym_requests_oper[#define smbmsg$v_sym_copies_file smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_sym_copies_fileY#definOe smbmsg$v_sym_copies_job smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_sym_copies_jobg#define smbmsg$v_sym_accepts_all_forms smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_sym_accepts_all_formsg#define smbmsg$v_sym_no_job_checkpoint smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_sym_no_job_checkpointi#define smbmsg$v_sym_all_characteristic smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_sym_all_characteristicc#define smbmsg$v_notify_on_interrupt smbmsg$r_fill_0_.smbmsg$r_fill_1_.smbmsg$v_notify_on_interrupt O"#endif /* #if !defined(__VAXC) */ N/* */I/* PRINT_CONTROL item */N/* */!#define SMBMSG$M_DOUBLE_SPACE 0x1 #define SMBMSG$M_PAGE_HEADER 0x2#define SMBMSG$M_PAGINATE 0x4#define SMBMSG$M_PASSALL 0x8#define SMBMSG$M_SEQUENCED 0x10 #define SMBMSG$M_SHEET_FEED 0x20#define SMBMSG$M_TRUNCATE 0xO40#define SMBMSG$M_WRAP 0x80&#define SMBMSG$M_RECORD_BLOCKING 0x100"#define SMBMSG$M_PAGE_FOOTER 0x200"#define SMBMSG$M_DELETE_FILE 0x400)#define SMBMSG$M_LOWERCASE_EXPLICIT 0x800#define SMBMSG$M_NOTIFY 0x1000#define SMBMSG$M_RESTART 0x2000"#define SMBMSG$M_JOB_RETAIN 0x4000(#define SMBMSG$M_JOB_ERROR_RETAIN 0x8000&#define SMBMSG$M_NO_INITIAL_FF 0x10000 typedef struct _print_control { __union {N unsigned int smbmsg$l_print_flags; /* Print flags */O __struct {N unsigned smbmsg$v_double_space : 1; /* - double space */N unsigned smbmsg$v_page_header : 1; /* - print page headers */N unsigned smbmsg$v_paginate : 1; /* - insert 's */N unsigned smbmsg$v_passall : 1; /* - binary print file */N unsigned smbmsg$v_sequenced : 1; /* - print sequence numbers */N unsigned smbmsg$v_sheet_feed : 1; /* - pause at every TOF */N O unsigned smbmsg$v_truncate : 1; /* - truncate on overflow */N unsigned smbmsg$v_wrap : 1; /* - wrap on overflow */Z unsigned smbmsg$v_record_blocking : 1; /* - block records in output buffer */N unsigned smbmsg$v_page_footer : 1; /* - print page footers */R unsigned smbmsg$v_delete_file : 1; /* - delete file after printing */f unsigned smbmsg$v_lowercase_explicit : 1; /* - job for printer that supports loweOrcase */Q unsigned smbmsg$v_notify : 1; /* - notify user when job completes */V unsigned smbmsg$v_restart : 1; /* - restart job after crash or requeue */N unsigned smbmsg$v_job_retain : 1; /* - per job retain */T unsigned smbmsg$v_job_error_retain : 1; /* - per job retain on error */Y unsigned smbmsg$v_no_initial_ff : 1; /* - output form feed on START/QUEUE */N unsigned smbmsg$v_filler : 15; /* - force longword O */ } smbmsg$r_fill_3_; } smbmsg$r_fill_2_; } PRINT_CONTROL; #if !defined(__VAXC)B#define smbmsg$l_print_flags smbmsg$r_fill_2_.smbmsg$l_print_flagsU#define smbmsg$v_double_space smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_double_spaceS#define smbmsg$v_page_header smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_page_headerM#define smbmsg$v_paginate smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_paginateK#define smbmsg$v_passall smbmsg$r_fill_2_.smbmsg$r_fill_3_ O.smbmsg$v_passallO#define smbmsg$v_sequenced smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_sequencedQ#define smbmsg$v_sheet_feed smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_sheet_feedM#define smbmsg$v_truncate smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_truncateE#define smbmsg$v_wrap smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_wrap[#define smbmsg$v_record_blocking smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_record_blockingS#define smbmsg$v_page_footer smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_pa Oge_footerS#define smbmsg$v_delete_file smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_delete_filea#define smbmsg$v_lowercase_explicit smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_lowercase_explicitI#define smbmsg$v_notify smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_notifyK#define smbmsg$v_restart smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_restartQ#define smbmsg$v_job_retain smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_job_retain]#define smbmsg$v_job_error_retain smbmsg$r_fill_2_.smbmsg$r_fill_3_.sm Obmsg$v_job_error_retainW#define smbmsg$v_no_initial_ff smbmsg$r_fill_2_.smbmsg$r_fill_3_.smbmsg$v_no_initial_ff"#endif /* #if !defined(__VAXC) */ N/* */I/* REQUEST_CONTROL item */N/* */##define SMBMSG$M_ALIGNMENT_MASK 0x1##define SMBMSG$M_PAUSE_COMPLETE 0x2#define SMBMSG$M_RESTARTING 0x4 #def Oine SMBMSG$M_TOP_OF_FILE 0x8 typedef struct _request { __union {N unsigned int smbmsg$l_request_flags; /* Print flags */ __struct {N unsigned smbmsg$v_alignment_mask : 1; /* - print A's and 9's */V unsigned smbmsg$v_pause_complete : 1; /* - pause when request complete */N unsigned smbmsg$v_restarting : 1; /* - job is restarting */N unsigned smbmsg$v_top_of_file : 1; /* - rewind before resume */ ON unsigned smbmsg$v_filler : 28; /* - force longword */ } smbmsg$r_fill_5_; } smbmsg$r_fill_4_; } REQUEST; #if !defined(__VAXC)F#define smbmsg$l_request_flags smbmsg$r_fill_4_.smbmsg$l_request_flagsY#define smbmsg$v_alignment_mask smbmsg$r_fill_4_.smbmsg$r_fill_5_.smbmsg$v_alignment_maskY#define smbmsg$v_pause_complete smbmsg$r_fill_4_.smbmsg$r_fill_5_.smbmsg$v_pause_completeQ#define smbmsg$v_restarting smbmsg$r_fill_4_.smbmsg$r_fill_5_. Osmbmsg$v_restartingS#define smbmsg$v_top_of_file smbmsg$r_fill_4_.smbmsg$r_fill_5_.smbmsg$v_top_of_file"#endif /* #if !defined(__VAXC) */ N/* */I/* SEPARATION_CONTROL item */N/* */#define SMBMSG$M_FILE_BURST 0x1#define SMBMSG$M_FILE_FLAG 0x2!#define SMBMSG$M_FILE_TRAILER 0x4'#define SMBMSG$M_FILOE_TRAILER_ABORT 0x8#define SMBMSG$M_JOB_FLAG 0x10#define SMBMSG$M_JOB_BURST 0x20#define SMBMSG$M_JOB_RESET 0x40%#define SMBMSG$M_JOB_RESET_ABORT 0x80"#define SMBMSG$M_JOB_TRAILER 0x100(#define SMBMSG$M_JOB_TRAILER_ABORT 0x200(#define SMBMSG$M_FIRST_FILE_OF_JOB 0x400'#define SMBMSG$M_LAST_FILE_OF_JOB 0x800 $typedef struct _separation_control { __union {N unsigned int smbmsg$l_separation_flags; /* Print flags */ __struct {N unsigned sOmbmsg$v_file_burst : 1; /* - print file burst page */N unsigned smbmsg$v_file_flag : 1; /* - print file flag page */P unsigned smbmsg$v_file_trailer : 1; /* - print file trailer page */V unsigned smbmsg$v_file_trailer_abort : 1; /* - print file trailer page */N unsigned smbmsg$v_job_flag : 1; /* - print job flag page */N unsigned smbmsg$v_job_burst : 1; /* - print job burst page */P unsigned smbmsg$v_job_reseOt : 1; /* - execute job reset sequence */V unsigned smbmsg$v_job_reset_abort : 1; /* - execute job reset sequence */N unsigned smbmsg$v_job_trailer : 1; /* - print job trailer page */T unsigned smbmsg$v_job_trailer_abort : 1; /* - print job trailer page */g unsigned smbmsg$v_first_file_of_job : 1; /* - this is the first file of the current job */e unsigned smbmsg$v_last_file_of_job : 1; /* - this is the last file of the current job */ ON unsigned smbmsg$v_filler : 20; /* - force longword */ } smbmsg$r_fill_7_; } smbmsg$r_fill_6_; } SEPARATION_CONTROL; #if !defined(__VAXC)L#define smbmsg$l_separation_flags smbmsg$r_fill_6_.smbmsg$l_separation_flagsQ#define smbmsg$v_file_burst smbmsg$r_fill_6_.smbmsg$r_fill_7_.smbmsg$v_file_burstO#define smbmsg$v_file_flag smbmsg$r_fill_6_.smbmsg$r_fill_7_.smbmsg$v_file_flagU#define smbmsg$v_file_trailer smbmsg$r_fill_6_.smbmsg$r_fill_7O_.smbmsg$v_file_trailera#define smbmsg$v_file_trailer_abort smbmsg$r_fill_6_.smbmsg$r_fill_7_.smbmsg$v_file_trailer_abortM#define smbmsg$v_job_flag smbmsg$r_fill_6_.smbmsg$r_fill_7_.smbmsg$v_job_flagO#define smbmsg$v_job_burst smbmsg$r_fill_6_.smbmsg$r_fill_7_.smbmsg$v_job_burstO#define smbmsg$v_job_reset smbmsg$r_fill_6_.smbmsg$r_fill_7_.smbmsg$v_job_reset[#define smbmsg$v_job_reset_abort smbmsg$r_fill_6_.smbmsg$r_fill_7_.smbmsg$v_job_reset_abortS#define smbmsg$v_job_trailer smbmsg$r_fillO_6_.smbmsg$r_fill_7_.smbmsg$v_job_trailer_#define smbmsg$v_job_trailer_abort smbmsg$r_fill_6_.smbmsg$r_fill_7_.smbmsg$v_job_trailer_abort_#define smbmsg$v_first_file_of_job smbmsg$r_fill_6_.smbmsg$r_fill_7_.smbmsg$v_first_file_of_job]#define smbmsg$v_last_file_of_job smbmsg$r_fill_6_.smbmsg$r_fill_7_.smbmsg$v_last_file_of_job"#endif /* #if !defined(__VAXC) */ N/* */I/* QUEUING_CONTROL item O */N/* */#define SMBMSG$M_RETAIN_JOB 0x1 !typedef struct _queuing_control { __union {N unsigned int smbmsg$l_queuing_flags; /* Queuing flags */ __struct {_ unsigned smbmsg$v_retain_job : 1; /* - symbiont retained job on "fixable" error */N unsigned smbmsg$v_filler : 31; /* - force longword */ } smbmsg$r_fill_9_O; } smbmsg$r_fill_8_; } QUEUING_CONTROL; #if !defined(__VAXC)F#define smbmsg$l_queuing_flags smbmsg$r_fill_8_.smbmsg$l_queuing_flagsQ#define smbmsg$v_retain_job smbmsg$r_fill_8_.smbmsg$r_fill_9_.smbmsg$v_retain_job"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */O#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SMBDEF_LOADED */ ww@%[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyoneO without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** thOe prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:35 by OpenVMS SDL V3.7 * O/G/* Source: 25-FEB-2004 17:37:42 $1$DGA8345:[LIB_H.SRC]SMCIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SMCIDEF ***/#ifndef __SMCIDEF_LOADED#define __SMCIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas Osupported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endifO#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* PBTQE - PB TQE */N/* */I/* PB TQE is a standard TQE with some extention fields added */I/* at the end. O */N/*- */  #include  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pb_tqe {#pragma __nomember_alignment TQE pbtqe$r_tqe_p;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 orO C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif" void *pbtqe$ps_dispatch_table;#pragma __nomember_alignment char pbtqe$b_fill_0_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif int pbtqe$l_next_step;#pragma __nomember_alignment int pbtqe$l_soft_errcnt; } PB_TQE;N/*+ O */N/* SMCH$ - Shared Memory Channel Block */N/* */N/*- */N#define SMCH$K_LENGTH 52 /*Length of structure */N#define SMCH$C_LENGTH 52 /*Length of structure */ c#if !defined(__NOBASEALIGN_SUPPORT) & O& !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _smch {#pragma __nomember_alignmentN unsigned __int64 smch$q_creation_time; /* time of creation */N unsigned short int smch$w_size; /* Size of SMCH$ in bytes */N unsigned char smch$b_type; /* Structure type DYN$C_SMCI */P unsigned char smch$b_subtype; /* Structure sub-typ!Oe DYN$C_SMCI_SMCH */N unsigned int smch$l_creator_node; /* gNode ID of creator */N unsigned __int64 smch$q_virtual_size; /* Max bytes for region */N unsigned __int64 smch$q_physical_size; /* Physical bytes for region */N int smch$l_node_block [2]; /* Offset to A's SMND$ structure */O unsigned int smch$l_buffer_start; /* offset to head of entries section */N unsigned int smch$l_buffer_end; /* offset to end of entries section */N "O unsigned int smch$l_total_buffers; /* Number of carved channels */ char smch$b_fill_1_ [4]; } SMCH;N/*+ */N/* */N/* */N/* SMND$ - Shared Memory Node Specific Data */N/* #O */N/* */N/*- */#define SMCI$K_VERSION 2#define SMCI$K_ECO 0N#define SMND$K_V1 0 /* V1 capabilities */#define SMND$M_OPEN 0x1#define SMND$M_NORM_SHTDWN 0x2N#define SMND$K_MAXPRIO_IDX 1 /* max. prio index */N#define SMND$C_MAXPRIO_IDX 1 /* max. prio index $O */N#define SMND$K_MAXPRIO 2 /* number of priorities */N#define SMND$C_MAXPRIO 2 /* number of priorities */N#define SMND$K_LENGTH 192 /*Length of structure */N#define SMND$C_LENGTH 192 /*Length of structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nome %Omber_alignment#endiftypedef struct _smnd {N/* constant VERSION equals 1 prefix SMCI$ tag K; */#pragma __nomember_alignment __union {N unsigned __int64 smnd$q_version; /* SMCH$ Structure Version */ __struct {N unsigned int smnd$l_eco_level; /* SMCH$ ECO Level */N unsigned int smnd$l_version; /* SMCH$ Structure Version */! } smnd$r_channel_ver;! } smnd$r_channel_version;&ON unsigned short int smnd$w_size; /* Size of SMND$ in bytes */N unsigned char smnd$b_type; /* Structure type DYN$C_SMCI */P unsigned char smnd$b_subtype; /* Structure sub-type DYN$C_SMCI_SMND */N int smnd$l_chan_char; /* Node Capabilites */N int smnd$l_filler; /* Node Capabilites */N unsigned int smnd$l_gnode; /* gNode ID */ __union {N 'O unsigned __int64 smnd$q_status; /* status quadword */ __struct {N unsigned smnd$v_open : 1; /* node ready */N unsigned smnd$v_norm_shtdwn : 1; /* normal shutdown */( unsigned smnd$v_fill_2_ : 6;! } smnd$r_status_bits; } smnd$r_status_flags;N unsigned int smnd$l_free_head; /* head of the Harter list */N unsigned int smnd$l_mapped; /* number of pages m(Oapped */N unsigned __int64 smnd$q_npings; /* Number of pings */P unsigned __int64 smnd$q_npings_skipped; /* Number of times we didn't ping */N __int64 smnd$q_nallocated; /* Number of allocated buffers */N/* */N/* We use a structure instead of just a quad/long-word because */N/* insqti - remqti lock 64 bytes at a time, and we don't want to */N/* )Olock a queue that other node is trying to access */N/* */ __struct { __union {N unsigned __int64 smnd$q_work_queue; /* */N unsigned int smnd$l_work_queue; /* */- unsigned char smnd$b_qbytes [64]; } smnd$r_wq_cl; } smnd$r_wq_cls [2]; } SMND; #if !defined(__VAXC)<#def*Oine smnd$q_version smnd$r_channel_version.smnd$q_versionS#define smnd$l_eco_level smnd$r_channel_version.smnd$r_channel_ver.smnd$l_eco_levelO#define smnd$l_version smnd$r_channel_version.smnd$r_channel_ver.smnd$l_version7#define smnd$q_status smnd$r_status_flags.smnd$q_statusF#define smnd$v_open smnd$r_status_flags.smnd$r_status_bits.smnd$v_openT#define smnd$v_norm_shtdwn smnd$r_status_flags.smnd$r_status_bits.smnd$v_norm_shtdwn8#define smnd$q_work_queue smnd$r_wq_cl.smnd$q_work_queue8#defin +Oe smnd$l_work_queue smnd$r_wq_cl.smnd$l_work_queue0#define smnd$b_qbytes smnd$r_wq_cl.smnd$b_qbytes"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */N/* SMWE$ - Work entry header */N/* */N/*- ,O */#define SMWE$K_FREE 0#define SMWE$K_SENDING 1#define SMWE$K_ALLOCATED 2 #define SMWE$K_INSTANCE_OFFSET 2N#define SMWE$K_LENGTH 24 /*Length of structure */N#define SMWE$C_LENGTH 24 /*Length of structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftype -Odef struct _smwe {#pragma __nomember_alignmentN unsigned int smwe$l_link [2]; /* A and B forward link */N unsigned short int smwe$w_size; /* Size of SMND$ in bytes */N unsigned char smwe$b_type; /* Structure type DYN$C_SMCI */P unsigned char smwe$b_subtype; /* Structure sub-type DYN$C_SMCI_SMWE */N unsigned int smwe$l_offset; /* offset from channel block */ __union {N unsigned int smwe$l_status; .O /* Longword for clearing */ __struct {, unsigned short int smwe$w_state;Q unsigned short int smwe$w_instance; /* Will be 2 plus instance 0/1 */N/* (2 flags new usage) */" } smwe$r_status_words; } smwe$r_work_status;N unsigned int smwe$l_seq; /* sequential number */N unsigned int smwe$l_body; /* dummy, pointer to SCS buffer */ /Ochar smwe$b_fill_3_ [4]; } SMWE; #if !defined(__VAXC)6#define smwe$l_status smwe$r_work_status.smwe$l_statusH#define smwe$w_state smwe$r_work_status.smwe$r_status_words.smwe$w_stateN#define smwe$w_instance smwe$r_work_status.smwe$r_status_words.smwe$w_instance"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */N/* Negotiation block 0O */N/* */N/*- */#define NB$M_READY 0x1#define NB$M_AGREE_H 0x2N#define NB$K_LENGTH 240 /* Length of structure */N#define NB$C_LENGTH 240 /* Length of structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DE 1OCC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _nb {#pragma __nomember_alignmentN unsigned __int64 nb$q_reserved; /* padding */N unsigned short int nb$w_size; /* Size of NB$ in bytes */N unsigned char nb$b_type; /* Structure type DYN$C_SMCI */N unsigned char nb$b_subtype; /* Structure sub-type DYN$C_SMCI_NB */N unsigned int nb$l_rese 2Orved; /* padding */ __union { __struct {N unsigned nb$v_ready : 1; /* node ready writing */N unsigned nb$v_agree_h : 1; /* node agreed */& unsigned nb$v_fill_4_ : 6; } nb$r_nb_sts_bits;N unsigned __int64 nb$q_nbsts; /* negotiation status quadword */ } nb$r_nbsts_flags [2];N unsigned __int64 nb$q_password [2]; /* password 3O */N unsigned __int64 nb$q_nworkq [2]; /* number of work queues ??? */N unsigned __int64 nb$q_buffers [2]; /* number of buffers */N unsigned __int64 nb$q_netsize [2]; /* decnet header size */N unsigned __int64 nb$q_msg_dg_size [2]; /* buffer size */N unsigned __int64 nb$q_scshdr_size [2]; /* scs/ppd buffer header size */N unsigned __int64 nb$q_smwe_size [2]; /* channel buffer header size */N unsigned 4O __int64 nb$q_smch_size [2]; /* channel header size */N unsigned __int64 nb$q_smnd_size [2]; /* node block size */N unsigned __int64 nb$q_chanchar [2]; /* channel characteristic */N unsigned __int64 nb$q_channel_add [2]; /* number of channels to expand */N unsigned __int64 nb$q_version [2]; /* number of channels to expand */N unsigned __int64 nb$q_eco_level [2]; /* number of channels to expand */ } NB; #if !defined(__VAXC). 5O#define nb$v_ready nb$r_nb_sts_bits.nb$v_ready2#define nb$v_agree_h nb$r_nb_sts_bits.nb$v_agree_h#define nb$q_nbsts nb$q_nbsts"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */>typedef NB * NB_PQ; /* Long pointer to a NB structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#e 6Olsetypedef unsigned __int64 NB_PQ;##endif /* __INITIAL_POINTER_SIZE */N/*+ */N/* */N/* Channel Handle */N/* */N/*- */N#define SMH$C_MAX_BUFFERS 107O00 /* Number of buffers */N#define SMH$K_MAX_BUFFERS 1000 /* Number of buffers */N#define SMH$C_BUFFERS 20 /* Number of buffers */N#define SMH$K_BUFFERS 20 /* Number of buffers */N#define SMH$K_ADD_CHANNELS 1 /* */N#define SMH$C_ADD_CHANNELS 1 /* */N#define SMH$K_A_END 0 /* A_end node 8Oindex */N#define SMH$K_B_END 1 /* B_end node index */N#define SMH$K_LENGTH 212 /* Length of structure */N#define SMH$C_LENGTH 212 /* Length of structure */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _smh {#pragma __nomember_ali9OgnmentN __int64 smh$q_filler; /* filler */N unsigned short int smh$w_size; /* Size of SMH$ in bytes */N unsigned char smh$b_type; /* Structure type DYN$C_SMCI */O unsigned char smh$b_subtype; /* Structure sub-type DYN$C_SMCI_SMH */N char smh$b_tag [64]; /* section name descriptor */N unsigned int smh$l_chn_size; /* channel entry size */N unsigned int:O smh$l_buffers; /* Number of buffers */N unsigned int smh$l_hdr_size; /* SMCH header */N unsigned int smh$l_ndh_size; /* SMND header */N unsigned int smh$l_chb_size; /* channel size */N unsigned int smh$l_virtual_size; /* virtual size */N unsigned int smh$l_physical_size; /* physical size */N unsigned int smh$l_expand; /* ;O channel expansion in bytes */ char smh$b_fill_5_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN SHM_ID smh$r_reg_id; /* Channel region id */#pragma __nomember_alignment __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long O */ char smh$b_fill_6_ [4]; } SMH; #if !defined(__VAXC)6#define smh$pq_channel smh$r_channel_va.smh$pq_channel6#define smh$pl_channel smh$r_channel_va.smh$pl_channel"#endif /* #if !defined(__VAXC) */ N/*+ */N/* */N/* Channel pfn packet */N/* ?O */N/*- */N#define SMPFN$K_LENGTH 4 /* Length of structure */N#define SMPFN$C_LENGTH 4 /* Length of structure */N#define SMPFN$K_DIVF 3 /* shift factor for division */N#define SMPFN$C_DIVF 3 /* shift factor for division */N/* @O */N#define SMPFN$K_MAXPKT 9 /* max number of packets */N#define SMPFN$C_MAXPKT 9 /* max number of packets */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _smpfn {#pragma __nomember_alignmentN unsigned short int smpfn$w_length; /* data length AO */N unsigned short int smpfn$w_boffset; /* byte offset from beg. page */N/* The maximun number of pfn packets cannot be lower than 2. */N/* The maximun is limited by the lowest of this constant or whatever the */N/* the channel packet can hold */N/* */ char smpfn$b_fill_7_ [4]; } SMPFN;N/*+ BO */N/* */N/* SMCI_FLAGS Sysgen Parameter Flags */N/* */N/*- */#define SMFL$M_ALLOW_SELF 0x1#define SMFL$M_ALWAYS_LOAD 0x2#define SMFL$M_VERBOSE 0x4 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined CO(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _smfl {#pragma __nomember_alignment __union { __struct {N unsigned smfl$v_allow_self : 1; /* Allow local communications */N unsigned smfl$v_always_load : 1; /* Load regardless of cluster */N unsigned smfl$v_verbose : 1; /* Output more info to the console */( unsigned smfl$v_fill DO_8_ : 5; } smfl$r_smfl_bits;N unsigned int smfl$l_smfl_flags; /* Flags longword */ } smfl$r_smfl_union; char smfl$b_fill_9_ [4]; } SMFL; #if !defined(__VAXC)N#define smfl$v_allow_self smfl$r_smfl_union.smfl$r_smfl_bits.smfl$v_allow_selfP#define smfl$v_always_load smfl$r_smfl_union.smfl$r_smfl_bits.smfl$v_always_loadH#define smfl$v_verbose smfl$r_smfl_union.smfl$r_smfl_bits.smfl$v_verbose=#define smfl$l_smfl_flags smfl$r_smfl_union.smEOfl$l_smfl_flags"#endif /* #if !defined(__VAXC) */ #define PBFKB$M_FKB_BUSY 0x1 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pb_fkb {#pragma __nomember_alignmentN void *pbfkb$ps_flink; /* flink */N void *pbfkb$ps_blink; /* blink */N unsi FOgned short int pbfkb$w_size; /* Size of SMH$ in bytes */N unsigned char pbfkb$b_type; /* Structure type DYN$C_SMCI */Q unsigned char pbfkb$b_subtype; /* Structure sub-type DYN$C_SMCI_PBFKB */ __union { __struct {N unsigned pbfkb$v_fkb_busy : 1; /* Fork block busy */* unsigned pbfkb$v_fill_10_ : 7;! } pbfkb$r_pbfkb_bits;N unsigned int pbfkb$l_flags; /* Flags longword GO */ } pbfkb$r_pbfkb_union;N FKB pbfkb$r_fkb_p; /* The embedded fork block */ } PB_FKB; #if !defined(__VAXC)P#define pbfkb$v_fkb_busy pbfkb$r_pbfkb_union.pbfkb$r_pbfkb_bits.pbfkb$v_fkb_busy7#define pbfkb$l_flags pbfkb$r_pbfkb_union.pbfkb$l_flags"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __HOrestore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SMCIDEF_LOADED */ ww`s[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not IO **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to JObe used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************************************************************** KO*****/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SMTDEF ***/#ifndef __SMTDEF_LOADED#define __SMTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdLOef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define MO__struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* FDDI MAC Header SMT Frame Control field constants */N/*-- */N/* SMT frame type with the following associated control functiNOons: */N/* o Frame Class bit = Asynchronous (0) */N/* o Address Length bit = 48 bit address (0) */N/* o Frame Format bits = SMT frame (00) */N/* o Frame Control bits = 0001 */ #define LAN$K_SMT_FC_SMTFRAME 65N/* LLC frame type with the following associated control functions: */N/* o Frame Class bit = Asynchronous (0) OO */N/* o Address Length bit = 48 bit address (0) */N/* o Frame Format bits = LLC frame (01) */N/* o Reserved bit = 0 */N/* o Priority bits = lowest priority (000) */ #define LAN$K_SMT_FC_LLCFRAME 80N/* Define the SMT Frame Header */ typedef struct _smt_hdrdef {Z unsignedPO char smt_hdr$b_f_cl; /* Frame Class for the SMT frame based protocol */Y unsigned char smt_hdr$b_f_ty; /* Frame Type for the SMT frame based protocol */N unsigned short int smt_hdr$w_ver; /* SMT frame's Version ID field */ __union {N unsigned int smt_hdr$l_l; /* SMT frame's Transaction ID field */N unsigned char smt_hdr$b_b1 [4]; /* Byte view of Transaction ID */ } smt_hdr$r_t_id;N unsigned char smt_hdr$b_s_id [8]; /* Station QO ID for an FDDI station */N unsigned short int smt_hdr$w_s_p; /* Two octet pad field */ __union {W unsigned short int smt_hdr$w_w; /* Information length field (info to follow) */N unsigned char smt_hdr$b_b2 [2]; /* Byte view of Information length */ } smt_hdr$r_ilen; } SMT_HDRDEF; #if !defined(__VAXC).#define smt_hdr$l_l smt_hdr$r_t_id.smt_hdr$l_l0#define smt_hdr$b_b1 smt_hdr$r_t_id.smt_hdr$b_b1.#define smt_hdr$w_w smt_hdr$r_ilen.smt RO_hdr$w_w0#define smt_hdr$b_b2 smt_hdr$r_ilen.smt_hdr$b_b2"#endif /* #if !defined(__VAXC) */ N/* SMT Frame Header Frame Class (F_CL) field constants */N/* */N/* The SMT Frame Class identifies the FUNCTION of the frame */N#define LAN$K_SMT_HDR_F_CL_NIF 1 /* NIF */N#define LAN$K_SMT_HDR_F_CL_SIFCON 2 /* SIF - Configuration */N#definSOe LAN$K_SMT_HDR_F_CL_SIFOPR 3 /* SIF - Operation */N#define LAN$K_SMT_HDR_F_CL_ECF 4 /* Echo */N#define LAN$K_SMT_HDR_F_CL_RAF 5 /* Resource Allocation */N#define LAN$K_SMT_HDR_F_CL_RDF 6 /* Request Denied */N#define LAN$K_SMT_HDR_F_CL_SRF 7 /* Status Report */N#define LAN$K_SMT_HDR_F_CL_PMFGET 8 /* Get PMF */N#define LAN$K_SMT_HDR_F_CL_PMFCHTOG 9 /* ChangePMF */N#define LAN$K_SMT_HDR_F_CL_PMFADD 10 /* Add PMF */N#define LAN$K_SMT_HDR_F_CL_PMFREM 11 /* Remove PMF */N/* SMT Frame Header Frame Type (F_TY) field constants */N/* */N/* The SMT Frame Type identifies the frame as an */N/* announcement, request or response. UO */)#define LAN$K_SMT_HDR_F_TY_ANNOUNCEMENT 1$#define LAN$K_SMT_HDR_F_TY_REQUEST 2%#define LAN$K_SMT_HDR_F_TY_RESPONSE 3N/* SMT Frame Header Frame Version ID (VER) field constants */N/* */N/* The SMT Frame Versin ID identifies the structure of the */N/* SMT information field by identifing the version of the */N/* SMT standard that is supported. VO */N/* */I/* !!!!!! MSB Format !!!!!! */!#define LAN$K_SMT_HDR_VERSION 256N/* Define the SMT Information field format */N/* */P/* The SMT Information field consists of an array of the following structures */N/* which describe a parameter. Ea WOch of the structures is followed by a */N/* variable length data field containing the parameter data. */ typedef struct _smt_infodef {N unsigned short int smt_info$w_parm_typ; /* Parameter type */N unsigned short int smt_info$w_parm_len; /* Parameter length */ } SMT_INFODEF;N/* Define the SMT Information field Parameter Types */N/* */I/* !XO!!!!! MSB Format !!!!!! */N/* For NIF */N#define LAN$K_SMT_PARM_TYP_UNA 256 /* Upstream Neighbor Addr */N#define LAN$K_SMT_PARM_TYP_STATDESC 512 /* Station Description */N#define LAN$K_SMT_PARM_TYP_STATSTATE 768 /* Station State */N#define LAN$K_SMT_PARM_TYP_STATUSCAP 2848 /* MACFrameStatusCapability */N/* For Echo YO */N#define LAN$K_SMT_PARM_TYP_ECHODATA 4352 /* Echo Data */N/* For RDF */N#define LAN$K_SMT_PARM_TYP_RDFREASON 4608 /* Request Denied Reason */N/* Define the NIF SMT Information field format */ typedef struct _smt_nifdef {P unsigned short int smt_nif$w_una_typ; /* Upstream Neighbor parameter type */R unsigned short int sZOmt_nif$w_una_len; /* Upstream Neighbor parameter length */N unsigned char smt_nif$b_una_value [8]; /* Upstream Neighbor value */O unsigned short int smt_nif$w_sd_typ; /* Station Descriptor parmeter type */R unsigned short int smt_nif$w_sd_len; /* Station Descriptor parameter length */P unsigned int smt_nif$l_sd_value; /* Station Descriptor parameter value */N unsigned short int smt_nif$w_ss_typ; /* Station State parmeter type */N unsigned short int smt_nif$w_ss_le [On; /* Station State parameter length */N unsigned int smt_nif$l_ss_value; /* Station State parameter value */S unsigned short int smt_nif$w_cap_typ; /* fddiMACFrameStatusCapabilities type */U unsigned short int smt_nif$w_cap_len; /* fddiMACFrameStatusCapabilities length */O unsigned char smt_nif$b_cap_value [8]; /* fddiMACFrameStatusCapabilities */ } SMT_NIFDEF; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size prag\Omas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SMTDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlet]Ot-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Softwar^Oe, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************* _O*******************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */L/* Source: 20-APR-1993 15:24:11 $1$DGA8345:[LIB_H.SRC]SNAPFKVECDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE SNAPFKVECDEF ***/#ifndef __SNAPFKVECDEF_LOADED#define __SNAPFKVECDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */`O!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_paOarams ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define SNAPFKVEC$K_TIMEOUT 15 /* MAXIMUM DELAY TIME */N#define SNAPFKVEC$K_LENGTH 32 /*LENGTH OF OVERHEAD AREA */N#define SNAPFKVEC$C_LENGTH 32 /*LENGTH OF OVERHEAD AREA bO */##define SNAPFKVEC$S_SNAPFKVECDEF 32 typedef struct _snapfkvec {N void *snapfkvec$l_fqfl; /*FORK QUEUE FORWARD LINK */N void *snapfkvec$l_fqbl; /*FORK QUEUE BACKWARD LINK */N unsigned short int snapfkvec$w_size; /*SIZE OF BLOCK IN BYTES */N unsigned short int snapfkvec$w_type; /*STRUCTURE TYPE */N unsigned int snapfkvec$l_refcnt; /*REFERENCE COUNT */N unsigned int snapfkv cOec$l_count; /*MAXIMUM VECTOR INDEX */N unsigned short int snapfkvec$w_event; /*CURRENT EVENT CODE */N unsigned short int snapfkvec$w_seed; /*SEQUENCE SEED */N unsigned int snapfkvec$l_status; /*ABORT STATUS */N void *snapfkvec$l_vector; /*BEGINNING OF VECTOR AREA */N/*THE VECTOR AREA SIZE IS "COUNT" LONGWORDS */ } SNAPFKVEC; $#pragma __member_alignment _dO_restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard "#endif /* __SNAPFKVECDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIALeO. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This softfOware is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************************************************************gO****//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */L/* Source: 09-JUN-1993 16:37:08 $1$DGA8345:[LIB_H.SRC]SNAPSTATEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE SNAPSTATEDEF ***/#ifndef __SNAPSTATEDEF_LOADED#define __SNAPSTATEDEF_LOADEhOD 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#defiOine __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define SNAPSTATE$M_ACTIVE 0x1 #define SNAPSTATE$M_NORETURN 0x2#define SNAPSTATE$M_ABORT 0x4#define SNAPSTATE$M_RESUME 0x8#define SNAPSTATE$jOM_POWER 0x10!#define SNAPSTATE$M_WATCHDOG 0x20$#define SNAPSTATE$M_ENABLEWATCH 0x40#define SNAPSTATE$M_DEBUG 0x80!#define SNAPSTATE$M_CLEANUP 0x100"#define SNAPSTATE$S_SNAPSTATEDEF 4 typedef struct _snapstate { __union { int snapstate$l_bits; __struct {N unsigned snapstate$v_active : 1; /* Snapshot process is active */g unsigned snapstate$v_noreturn : 1; /* Snapshot is committed and an abort is not possible */N unsigned snakOpstate$v_abort : 1; /* Snapshot being aborted */R unsigned snapstate$v_resume : 1; /* O.K. to resume other processes. */Q unsigned snapstate$v_power : 1; /* Powerfail exception in progress */n unsigned snapstate$v_watchdog : 1; /* Snapshot watchdog is active (set by the watchdog process) */r unsigned snapstate$v_enablewatch : 1; /* Snapshot watchdog is enabled (set by the snapshot process) */x unsigned snapstate$v_debug : 1; /* Snapsho lOt watchdog may detect erroneous timeouts caused by the debugger */] unsigned snapstate$v_cleanup : 1; /* Snapshot cleanup process has been started */- unsigned snapstate$v_fill_2_ : 7;" } snapstate$r_fill_1_; } snapstate$r_fill_0_; } SNAPSTATE; #if !defined(__VAXC)U#define snapstate$v_active snapstate$r_fill_0_.snapstate$r_fill_1_.snapstate$v_activeY#define snapstate$v_noreturn snapstate$r_fill_0_.snapstate$r_fill_1_.snapstate$v_noreturnS#dmOefine snapstate$v_abort snapstate$r_fill_0_.snapstate$r_fill_1_.snapstate$v_abortU#define snapstate$v_resume snapstate$r_fill_0_.snapstate$r_fill_1_.snapstate$v_resumeS#define snapstate$v_power snapstate$r_fill_0_.snapstate$r_fill_1_.snapstate$v_powerY#define snapstate$v_watchdog snapstate$r_fill_0_.snapstate$r_fill_1_.snapstate$v_watchdog_#define snapstate$v_enablewatch snapstate$r_fill_0_.snapstate$r_fill_1_.snapstate$v_enablewatchS#define snapstate$v_debug snapstate$r_fill_0_.snapstate$r_oOfill_1_.snapstate$v_debugW#define snapstate$v_cleanup snapstate$r_fill_0_.snapstate$r_fill_1_.snapstate$v_cleanup"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard "#endif /* __SNAPSTATEDEF_LOADED */ wwaGOSMTDEF[O SNAPFKVECDEFcO8 SNAPSTATEDEFmO SOURCEDEFwOSPDTDEFOSPIDEFO SPLCODDEFPSPLDEF/PSPNBDEF8PSPPADEFgPSPPBDEFpPSQEDEFzP SRVBUFDEFP*SSCDEFPSSCTDEFP SSDESCRDEFP6SSDISPPSSIDEFP.SSLOGDEFPSSVECDEFP&STATDEFQSTATEDEF QSTDTDEF:Q& SVAPTEDEFAQSWISDEF SWIS_ROUTINES`QfSWRPBDEFQSYSAPDEF SYSAP_MACROSSYSTEM_SERVICE_SETUP SYS_FUNCTIONSjTFDEFpO6[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 CopyrqOight Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. rO **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//************************************* sO*******************************************************************************************//*** MODULE $SOURCEDEF ***/#ifndef __SOURCEDEF_LOADED#define __SOURCEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#ptOragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_ uOunion#endif#endif N/*++ */N/* Source address table buffer definition. */N/*-- */R#define SOURCE$C_HDR_LENGTH 16 /* Size of source address buffer header */N#define SOURCE$T_START_ENTRIES 16 /* Start of entries */N#define SOURCE$C_SIZE_ADDR 8 /* Size of the source addresses vO */N#define SOURCE$C_SIZE_INCR 128 /* Size of table allocation chunks */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sourcedef {#pragma __nomember_alignmentN unsigned int source$l_no_alloc; /* Number of allocated entries */N unsigned int source$l_no_entries; /* Number of used entries */U un wOsigned short int source$w_size; /* Size of source address buffer allocated */N unsigned char source$b_type; /* Type of structure */N unsigned char source$b_unused; /* Fill to longword boundary */N int source$l_unused1; /* Fill to quadword boundary */ } SOURCEDEF;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __rexOstore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SOURCEDEF_LOADED */ ww@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not yO **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to zObe used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************************************************************** {O*****/=/* Created: 7-Oct-2024 15:23:29 by OpenVMS SDL V3.7 */G/* Source: 24-JUN-2022 09:23:00 $1$DGA8345:[LIB_H.SRC]SPDTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SPDTDEF ***/#ifndef __SPDTDEF_LOADED#define __SPDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#i|Ofdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#defin}Oe __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SPDT - SCSI Port Descriptor Table */N/* */N/* There is one SPDT per port. The SPDT contains the SCSI po~Ort information */N/* for one SCSI port. SPDT's are created by the unit init routines */N/* of the individual port drivers. During initialization the port driver's */N/* port routine entry points are initialized in the SPDT. The class drivers */O/* execute these entry points to interact with the underlying port hardware. */N/* */N/* This structure is read accessable to the class driver and readable and */N/* wOriteable by the port driver. */N/* */U/* ***NOTE1:**** New SPDT fields must be entered at the end of the data structure. */N/* */N/* ***NOTE2:**** If an INCOMPATIBLE CHANGE is made to this structure bump */B/* the version number of this structure. */N/*- O */  #include N#define SPDT$C_VERSION 13 /* NOSVAPTE_V9.0 Dave Fairbanks */N#define SPDT$C_TYPE_PKS 1 /* SCSI KZTSA/KZPSA (SimPort) */N#define SPDT$C_TYPE_PKC 2 /* SCSI NCR 53C94 Port */N#define SPDT$C_TYPE_PKZ 3 /* SCSI KZXZA NCR 53C710 Port */N#define SPDT$C_TYPE_PKT 4 /* SCSI NCR 53C710 Port */N#define SPDT$C_TYPE_PKJ 5 O /* SCSI ADAPTEC 1742A Port */N#define SPDT$C_TYPE_PKE 6 /* SCSI NCR 53C810 Port */N#define SPDT$C_TYPE_PKQ 7 /* SCSI QLogic ISP1020 Port */N#define SPDT$C_TYPE_PG 8 /* FCP port driver */N#define SPDT$C_TYPE_PKW 9 /* SCSI SYMBIOS 53C8XX Port */N#define SPDT$C_TYPE_PKA 10 /* SCSI Adaptec 7895/7899 port */N#define SPDT$C_TYPE_PKR 11 /* Ramanujan CISOS controller */N#define SPDT$C_TYPE_PKM 12 /* SCSI LSI Logic 1030 Port */N#define SPDT$C_TYPE_PGQ 13 /* QLogic ISP23xx FibreChannel port */N#define SPDT$C_TYPE_DE 14 /* iSCSI port driver */Q#define SPDT$C_TYPE_GSP 15 /* X-54 HPVM Guest Storage Port (AVIO) */N#define SPDT$C_TYPE_PKD 16 /* AHCI SATA controller */N#define SPDT$C_TYPE_PQI 17 /* PQI SCSI Port */ON#define SPDT$C_TYPE_VSP 18 /* VIRTIO SCSI Port */#define SPDT$C_TYPE_PGA 8#define SPDT$M_PFLG_SYNCH 0x1#define SPDT$M_PFLG_ASYNCH 0x2##define SPDT$M_PFLG_MAPPING_REG 0x4#define SPDT$M_PFLG_BUF_DMA 0x8 #define SPDT$M_PFLG_DIR_DMA 0x10#define SPDT$M_PFLG_AEN 0x20#define SPDT$M_PFLG_LUNS 0x40#define SPDT$M_PFLG_CMDQ 0x80##define SPDT$M_PFLG_AUTOSENSE 0x100(#define SPDT$M_PFLG_PORT_AUTOSENSE 0x200$#define SPDT$M_PFLG_SMART_PORT 0x400#define SPDT$M O_PFLG_DIPL 0x800%#define SPDT$M_PFLG_64BIT_LUNS 0x1000$#define SPDT$M_PFLG_TRANSPORT 0xE000#define SPDT$K_PARALLEL 0#define SPDT$K_FIBRE_CHANNEL 1#define SPDT$K_ISCSI 2N#define SPDT$K_SW_ISCSI 2 /* X-52 */N#define SPDT$K_HW_ISCSI 3 /* X-52 */N#define SPDT$K_SAS 4 /* X-52 */N/*F Bits 19:16 */%#defin Oe SPDT$M_PFLG_PATH_INFO 0x10000,#define SPDT$M_PFLG_MAXBCNT_OVERRIDE 0x20000##define SPDT$M_PFLG_EXT_LUN 0x40000%#define SPDT$M_PFLG_IMP_QFULL 0x80000$#define SPDT$M_PFLG_SPL_CTX 0x100000&#define SPDT$M_PFLG_PERF_DATA 0x200000*#define SPDT$M_PFLG_GO_IO_CREDITS 0x400000%#define SPDT$M_PFLG_HBA_MODE 0x800000.#define SPDT$M_PFLG_FIRMWARE_VERSION 0x1000000-#define SPDT$M_PFLG_VIRTUAL_MACHINE 0x2000000#define SPDT$M_STS_ONLINE 0x1#define SPDT$M_STS_TIMOUT 0x2#define SPDT$M_STS_ERLOGIPO 0x4#define SPDT$M_STS_CANCEL 0x8#define SPDT$M_STS_POWER 0x10#define SPDT$M_STS_BSY 0x20#define SPDT$M_STS_FAILED 0x40#define SPDT$M_STS_FIFOLCK 0x80##define SPDT$M_STS_QWORK_TODO 0x100%#define SPDT$M_STS_RESET_ISSUED 0x200#define SPDT$M_SPARE 0x400"#define SPDT$M_STS_MULTIHOST 0x800&#define SPDT$M_STS_TIMEOUT_SOON 0x1000%#define SPDT$M_STS_TIMEOUT_NOW 0x2000"#define SPDT$M_STS_SAW_TAPE 0x4000&#define SPDT$M_STS_FIRST_CONFIG 0x8000)#define SPDT$M_DIPL_RESET_IN_PROGRESS 0x1O(#define SPDT$M_DIPL_RESET_FORK_INUSE 0x2+#define SPDT$M_DIPL_RESET_DETECTED_WAIT 0x4!#define SPDT$M_DIPL_STDT_SCDT 0x8,#define SPDT$M_DIPL_RESET_CU_FORK_INUSE 0x10\#define SPDT$C_VEC_START 88 /** Start of SCSI Vector Table; used by SCSIDEBUG */Q#define SPDT$C_CD_ABORT_COMMAND 0 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_BUFFER_MAP 1 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_BUFFER_UNMAP 2 /*I Index in Class Driver vectorO table */Q#define SPDT$C_CD_CMD_BUFFER_ALLOC 3 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_CMD_BUFFER_DEALLOC 4 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_CONNECT 5 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_CONNECTION_CHAR_GET 6 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_CONNECTION_CHAR_SET 7 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_DISCONNECT 8 /*I Index in Class Driver vector tOable */Q#define SPDT$C_CD_QUEUE_FLUSH 9 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_QUEUE_FREEZE 10 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_QUEUE_RELEASE 11 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_RESET_DEVICE 12 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_RESET_SCSI_BUS 13 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_SEND_COMMAND 14 /*I Index in Class Driver vector tabOle */Q#define SPDT$C_CD_INITIAL_PROCESSING 15 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_GET_PATH_INFO 16 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_SCSIPATH_CONNECT 17 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_GET_PORT_WWID 18 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_FP_REQUEST 19 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_FP_SEND 20 /*I Index in Class Driver vector table O */Q#define SPDT$C_CD_FP_FREE_RBUN 21 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_CANCEL 21 /*I Index in Class Driver vector table */Q#define SPDT$C_CD_VECTOR_RESERVED 22 /*I Index in Class Driver vector table */!#define SPDT$C_PK_ABORT_COMMAND 0$#define SPDT$C_PK_CMD_BUFFER_ALLOC 1&#define SPDT$C_PK_CMD_BUFFER_DEALLOC 2'#define SPDT$C_PK_CMD_WAIT_COMPLETION 3#define SPDT$C_PK_CONNECT 4'#define SPDT$C_PK_CONNECTION_CHAR_SET 5#define SPDT$C_PK_INOIT_SPDT 6#define SPDT$C_PK_INIT_STDT 7##define SPDT$C_PK_NEGOTIATE_SYNCH 8#define SPDT$C_PK_QUEUE_FLUSH 9!#define SPDT$C_PK_QUEUE_FREEZE 10"#define SPDT$C_PK_QUEUE_RELEASE 11##define SPDT$C_PK_RESET_SCSI_BUS 12!#define SPDT$C_PK_SEND_COMMAND 13"#define SPDT$C_PK_GET_PATH_INFO 14#define SPDT$C_PK_FP_REQUEST 15#define SPDT$C_PK_FP_SEND 16!#define SPDT$C_PK_FP_FREE_RBUN 17%#define SPDT$C_PK_FP_CMD_WAIT_COMP 18%#define SPDT$C_PK_FP_KP_COMPLETION 19#define SPDT$C_PK_ALLOC_POOL O 20#define SPDT$C_PK_FREE_POOL 21!#define SPDT$C_PK_SCSI_COMMAND 22#define SPDT$C_PK_CANCEL 23#define SPDT$C_PK_TRIGGER 24&#define SPDT$C_PK_TARGET_DISCONNECT 25$#define SPDT$C_PK_VECTOR_RESERVED 26N#define SPDT$K_STDT_HASH_SIZE 16 /* Size of STDT_HASH_TABLE. */N#define SPDT$K_STDT_HASH_BITBASE 0 /* Start bit of hash mask. */N#define SPDT$K_STDT_HASH_BITCNT 4 /* Number of bits in hash mask. */N#define SPDT$K_STDT_HASH_BITMASK 15 /* Bit mask fOor the hash value. */N/* */\#define SPDT$K_CMD_SLOTS 255 /* Total number of command slot allocation bits. */c#define SPDT$S_CMD_BITS 32 /* Total byte count of command slot allocation bit map. */N#define SPDT$C_PKSLENGTH 968 /* SIZE OF SPDT */N#define SPDT$C_PKCLENGTH 968 /* SIZE OF SPDT */N#define SPDT$C_PKNLENGTH 968 /* OSIZE OF SPDT */U#define SPDT$S_SPDTDEF 968 /* Old size name, synonym for SPDT$S_SPDT */  9#ifdef __cplusplus /* Define structure prototypes */ struct _spl; struct _adp; struct _crab; struct _cram; struct _idb; struct _ucb; struct _scdt; struct _sdbg;struct _scsi_rbun;struct _scdrp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember O_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _spdt {#pragma __nomember_alignmentN struct _spdt *spdt$l_flink; /*O Link to next SCSI SPDT */R unsigned int spdt$l_version_check; /*I Value used to check driver versions */N unsigned short int spdt$w_size; /*I Structure size in bytes */N unsigned char spdt$b_type; /*I Structure type */N unsigned char spdt$b_subtyp; /*I Structure subtOype */N/* */B/* SCSI Port Identification. */N/* */N unsigned short int spdt$w_spdt_type; /*I Type of SPDT */$ char spdt$t_spdtdef_align_1 [2];N unsigned int spdt$l_scsi_port_id; /*I SCSI port ID. (A..Z) */T unsigned int spdt$l_scsi_bus_id; /*I Mask value of Ohost ID (parallel only) */ __union {N unsigned int spdt$is_scsi_id_num; /*I SCSI bus ID numeric value */S unsigned __int64 spdt$q_scsi_id_num; /*I SCSI bus ID for wide devices, - */! } spdt$r_scsi_id_overlay;N/*I or high SCSI ID's */N/* */B/* Define the port characteristics and status. */N/* O */ __union {N unsigned int spdt$l_port_flags; /*F Port specific flags. */ __struct {N/*F Bits 03:00 */N unsigned spdt$v_pflg_synch : 1; /*F Supports synchronous mode. */O unsigned spdt$v_pflg_asynch : 1; /*F Supports asynchronous mode. */T unsigned spdt$v_pflg_mapping_reg : 1; /*F Supports mapping registers. */N Ounsigned spdt$v_pflg_buf_dma : 1; /*F Supports buffered DMA. */N/*F Bits 07:04 */N unsigned spdt$v_pflg_dir_dma : 1; /*F Supports direct DMA. */R unsigned spdt$v_pflg_aen : 1; /*F Supports Async Event Notification */N unsigned spdt$v_pflg_luns : 1; /*F Supports LUNS */X unsigned spdt$v_pflg_cmdq : 1; /*F Set if port supports command queueing. */N/*F Bits 11:08 O */z unsigned spdt$v_pflg_autosense : 1; /*F Set if the port driver supports autosense. Tested by class drivers. */v unsigned spdt$v_pflg_port_autosense : 1; /*F Set if port specific hardware/software supports autosense. */p unsigned spdt$v_pflg_smart_port : 1; /*F Set if the port hardware is an intelligent SCSI adapter. */Z unsigned spdt$v_pflg_dipl : 1; /*F Set if the port stalls at DIPL .vs. FORK */NO/*F Bits 15:12 */N unsigned spdt$v_pflg_64bit_luns : 1; /*F Supports 64-bit LUNs. */g unsigned spdt$v_pflg_transport : 3; /*F Physical transport (parallel, FC etc) */_ unsigned spdt$v_pflg_path_info : 1; /*F Accepts connects via sc$scsipath_connect */^ unsigned spdt$v_pflg_maxbcnt_override : 1; /*F Port override for max byte count */N unsigned spdt$v_pflg_ext_lun : 1; O/*F Supports external LUNs */o unsigned spdt$v_pflg_imp_qfull : 1; /*F Improved (over SCSI-2 Queue Manager) Queue Full handling */N/*F Bits 23:20 */c unsigned spdt$v_pflg_spl_ctx : 1; /*F Port uses Fork-Port-Dyn spinlock context model */U unsigned spdt$v_pflg_perf_data : 1; /*F Port collects performance data */e unsigned spdt$v_pflg_go_io_credits : 1; /*F Port restarts class driver for IO/O credits */V unsigned spdt$v_pflg_hba_mode : 1; /*F Port RAID Controller in HBA Mode */N/*F Bits 27:24 */t unsigned spdt$v_pflg_firmware_version : 1; /*F X-57 SPDT$B_FIRMWARE_VERSION[] available & initialized */f unsigned spdt$v_pflg_virtual_machine : 1; /*F X-59 Port is running on a virtual machine */N unsigned spdt$v_pflg_bit_26 : 1; /*F Placeholder */N unsignedO spdt$v_pflg_bit_27 : 1; /*F Placeholder */N/*F Bits 31:28 */N unsigned spdt$v_pflg_bit_28 : 1; /*F Placeholder */N unsigned spdt$v_pflg_bit_29 : 1; /*F Placeholder */N unsigned spdt$v_pflg_bit_30 : 1; /*F Placeholder */N unsigned spdt$v_pflg_bit_31 : 1; /*F Placeholder */ } spdt$r_fill_1_; } spdt O$r_fill_0_; __union {N unsigned int spdt$l_sts; /*F Port device status */ __struct {N unsigned spdt$v_sts_online : 1; /*F Unit online (1=yes) */N unsigned spdt$v_sts_timout : 1; /*F Unit timed out (1=yes) */Y unsigned spdt$v_sts_erlogip : 1; /*F Error log in progress on unit (1=yes) */N unsigned spdt$v_sts_cancel : 1; /*F Cancel I/O on unit (1=yes) */V unsigned spdt$v_sts_power : 1;O /*F Power failed while unit busy (1=yes) */N unsigned spdt$v_sts_bsy : 1; /*F Unit is busy (1=yes) */[ unsigned spdt$v_sts_failed : 1; /*F Port failed operation or initialization. */N unsigned spdt$v_sts_fifolck : 1; /*F N53C94 FIFO in use */b unsigned spdt$v_sts_qwork_todo : 1; /*F Set when queue manager has more work to do. */V unsigned spdt$v_sts_reset_issued : 1; /*F Set when PORT issues a reset. */O unsignOed spdt$v_spare : 1; /*F placeholder for obsolete field */X unsigned spdt$v_sts_multihost : 1; /*F Multiple hosts (for SCSI clusters) */f unsigned spdt$v_sts_timeout_soon : 1; /*F I/O's to SCSI Port adapter will time out soon */e unsigned spdt$v_sts_timeout_now : 1; /*F I/O's to SCSI Port adapter are timing out now */` unsigned spdt$v_sts_saw_tape : 1; /*F At one time (and maybe now) a tape was seen */V unsigned spdt$v_sts_first_config : O 1; /*F IOGEN$SCS_CONFIG has run once */ } spdt$r_fill_3_; } spdt$r_fill_2_; __union {U unsigned int spdt$l_dipl_sts; /*D Port device status manipulated at DIPL */ __struct {T unsigned spdt$v_dipl_reset_in_progress : 1; /*D Bus Reset in progress */Y unsigned spdt$v_dipl_reset_fork_inuse : 1; /*D Bus Reset fork block in use */` unsigned spdt$v_dipl_reset_detected_wait : 1; /*D External reset wait in progress */Z O unsigned spdt$v_dipl_stdt_scdt : 1; /*D Deallocation of either SCDT or STDT */d unsigned spdt$v_dipl_reset_cu_fork_inuse : 1; /*D Bus Reset Cleanup fork block in use */( unsigned spdt$v_fill_8_ : 3; } spdt$r_fill_5_; } spdt$r_fill_4_;N unsigned int spdt$is_flck; /*I Fork lock index */N struct _spl *spdt$l_dlck; /*I Device lock address */N unsigned char spdt$b_dipl; /*I Device IOPL */$ char spdt$t_spdtdef_align_2 [3];N unsigned int spdt$is_savipl; /*I Saved IPL */P unsigned short int spdt$iw_erl_type; /*I ERL$DEVICEATN type/subtype codes */$ char spdt$t_spdtdef_align_3 [2];S unsigned int spdt$is_crctx_shift; /*F Counted res. size, as a shift factor */P unsigned int spdt$is_crctx_bwp_mask; /*F Counted res. size, as a BWP mask */N unsigned int spdt$is_scsi_int_msk; /*F Port-specific interrupt maskO */Q unsigned int spdt$l_maxbytecnt; /*I Maximum byte count for a transfer. */Z unsigned int spdt$l_max_fp_bcnt; /*F Maximum byte count for a FastPath transfer. */Q unsigned int spdt$l_timeout_count; /*F Counted of I/O's about to time out */N/* */B/* The SCSI Port Interface entry points follow. These entry */B/* points are fork entry points that the class driver envokes */B/* to execute port sp Oecific functions. */N/* */B/* Vectors are now also identified by a constant index so they */C/* can be referenced in a table of copied pointers, whether the */B/* pointers are longword or quadword */N/* */ __union { __struct {N int (*spdt$ps_cd_abort_command)(); /*I AbortO outstanding cmd. */Z int (*spdt$ps_cd_buffer_map)(); /*I Map a buffer for read or write transfer */N int (*spdt$ps_cd_buffer_unmap)(); /*I Unmap a buffer */R int (*spdt$ps_cd_cmd_buffer_alloc)(); /*I Allocate a message buffer */N int (*spdt$ps_cd_cmd_buffer_dealloc)(); /*I Deallocate buffer */N int (*spdt$ps_cd_connect)(); /*I Request connection to target. */N int (*spdt$ps_cd_connection_char_get)(); /*I Get conneOct char. */N int (*spdt$ps_cd_connection_char_set)(); /*I Set connect char. */N int (*spdt$ps_cd_disconnect)(); /*I Break connection. */a int (*spdt$ps_cd_queue_flush)(); /*I Address of SC$FLUSH_QUEUE in the port driver. */c int (*spdt$ps_cd_queue_freeze)(); /*I Address of SC$FREEZE_QUEUE in the port driver. */e int (*spdt$ps_cd_queue_release)(); /*I Address of SC$RELEASE_QUEUE in the port driver. */N int (*spdt$ps_Ocd_reset_device)(); /*I Perform a device reset. */O int (*spdt$ps_cd_reset_scsi_bus)(); /*I Maintenace reset of port */c int (*spdt$ps_cd_send_command)(); /*I Start processing a SCSI command on the device. */] int (*spdt$ps_cd_initial_processing)(); /*I Perform a tolerant INQUIRY command */N int (*spdt$ps_cd_get_path_info)(); /*I Fetch target and LUN */P int (*spdt$ps_cd_scsipath_connect)(); /*I Connect using path info */Z O int (*spdt$ps_cd_get_port_wwid)(); /*I Request a given port's World Wide ID */V int (*spdt$ps_cd_fp_request)(); /*I Get permission to FastPath request. */c int (*spdt$ps_cd_fp_send)(); /*I Start processing a FastPath SCSI command on device. */O int (*spdt$ps_cd_fp_free_rbun)(); /*I Deallocate FastPath buffer */N int (*spdt$ps_cd_cancel)(); /*I Cancel I/O on port */Z/* If you add a vector here, update the symbol used to define CD_VECTOR_ ORESERVED below */c int (*spdt$ps_cd_vector_reserved [9])(); /*I Reserved class driver interface vectors */' } spdt$r_cd_vectors_struct;) int (*spdt$ps_cd_vectors [23])();" } spdt$r_cd_vectors_union;N/* */B/* The SCSI Port Interface entry points follow. These entry */F/* points are the entry points from SCSI2COMMON and SCSI2SUBS into */B/* the port specific routines. O */N/* */ __union { __struct {U int (*spdt$ps_pk_abort_command)(); /*I Abort the outstanding requests. */S int (*spdt$ps_pk_cmd_buffer_alloc)(); /*I Allocate a command buffer. */W int (*spdt$ps_pk_cmd_buffer_dealloc)(); /*I Deallocate a command buffer. */b int (*spdt$ps_pk_cmd_wait_completion)(); /*I Wait for the SCSI request to complete. */O\ int (*spdt$ps_pk_connect)(); /*I Complete connection and SCDT initialization. */j int (*spdt$ps_pk_connection_char_set)(); /*I Finish setting the connection characteristics. */O int (*spdt$ps_pk_init_spdt)(); /*I Complete SPDT initialization. */O int (*spdt$ps_pk_init_stdt)(); /*I Complete STDT initialization. */V int (*spdt$ps_pk_negotiate_synch)(); /*I Re-negotiate the transfer mode */N int (*spdt$ps_pk_queue_flush)(); /*I FOlush the device queue. */N int (*spdt$ps_pk_queue_freeze)(); /*I Freeze the device queue. */O int (*spdt$ps_pk_queue_release)(); /*I Release the device queue. */N int (*spdt$ps_pk_reset_scsi_bus)(); /*I Reset the SCSI bus. */O int (*spdt$ps_pk_send_command)(); /*I Initiate the SCSI request. */N int (*spdt$ps_pk_get_path_info)(); /*I Fetch target and LUN. */V int (*spdt$ps_pk_fp_request)(); /*I Get permission to FastPaOth request. */c int (*spdt$ps_pk_fp_send)(); /*I Start processing a FastPath SCSI command on device. */O int (*spdt$ps_pk_fp_free_rbun)(); /*I Deallocate FastPath buffer */c int (*spdt$ps_pk_fp_cmd_wait_comp)(); /*I Wait for the FastPath request to complete. */h void (*spdt$ps_pk_fp_kp_completion)(); /*I Complete FastPath request in KP context [X-37] */S void *(*spdt$ps_pk_alloc_pool)(); /*I Allocate non-paged pool (X-46) */T Ovoid *(*spdt$ps_pk_free_pool)(); /*I Deallocate non-paged pool (X-46) */N int (*spdt$ps_pk_scsi_command)(); /*I SCSI command (X-46) */N int (*spdt$ps_pk_cancel)(); /*I Cancel I/O on port */N int (*spdt$ps_pk_trigger)(); /*I Trigger analyzer */N/* X-46A1a */T int (*spdt$ps_pk_target_disconnect)(); /*I Disconnect a target (STDT) */Z/* If you add a vector herOe, update the symbol used to define PK_VECTOR_RESERVED below */N/* Dimension decremented from 10 to 9 for PK_FP_COMPLETION in X-37 */N/* Dimension decremented from 9 to 6 for PK_ALLOC_POOL, PK_FREE_POOL, and */N/* PK_SCSI_COMMAND in X-46 */N/* Dimension decremented from 6 to 5 for PK_CANCEL in X-47 */N/* Dimension decremented from 5 to 4 for PK_TRIGGER in X-50 */P/* Dimension decremented from 4 to 3 for O PK_TARGET_DISCONNECT in X-50/X-46A1b */b int (*spdt$ps_pk_vector_reserved [3])(); /*I Reserved port driver interface vectors */' } spdt$r_pk_vectors_struct;) int (*spdt$ps_pk_vectors [27])();" } spdt$r_pk_vectors_union;N/* */H/* The "runtime library" entry point interface follows. These entry */H/* points are called by the port specific driver routines to perform */B/* support fuOnctions. */N/* */N int (*spdt$ps_rl_check_cmdq_status)(); /*I Check CMDQ status processing */S int (*spdt$ps_rl_check_ondeck_blocked)(); /*I Check if ONDECK_KPB is blocked */N int (*spdt$ps_rl_cmd_slot_alloc)(); /*I Allocate a command slot */N int (*spdt$ps_rl_cmd_slot_dealloc)(); /*I Deallocate a command slot */T int (*spdt$ps_rl_create_port)(); /*I CrOeate a new SPDT for a new SCSI port */N int (*spdt$ps_rl_pool_alloc)(); /*I Allocate non-paged pool */j int (*spdt$ps_rl_pool_alloc_physical)(); /*I Allocate non-paged pool of physically contigous memory */N int (*spdt$ps_rl_pool_dealloc)(); /*I Deallocate non-paged pool */N int (*spdt$ps_rl_init_scdrp)(); /*I Initialize SCDRP for port usage */N int (*spdt$ps_rl_timeout_setup_tqe)(); /*I Initialize port timer */N int (*spdt$ps_rl_queue_reset_dipl)O(); /*I Queue device reset from DIPL */N int (*spdt$ps_rl_queue_reset_fork)(); /*I Queue device reset from FORK */P int (*spdt$ps_rl_reset_detected_dipl)(); /*I Bus reset detected from DIPL */P int (*spdt$ps_rl_reset_detected_fork)(); /*I Bus reset detected from FORK */S int (*spdt$ps_rl_reset_detected_wait)(); /*I Bus reset detected wait request */W int (*spdt$ps_rl_vector_reserved [10])(); /*I Reserved "Runtime Library" vectors */N/* O */B/* Wait queues */N/* */N void *spdt$l_port_wqfl; /*F Port wait queue forward link */N void *spdt$l_port_wqbl; /*F Port wait queue backward link */O struct _fkb *spdt$l_waitqfl; /*F Listhead for fork blocks waiting */N struct _fkb *spdt$l_waitqbl; /*F For nonpaged pool */WO void *spdt$ps_reset_wait_list; /*D Single-Linked-List for bus reset waiters */N/* */B/* Related Port Data Structures. */N/* */N struct _adp *spdt$l_adp; /*I Address of ADP */N struct _crab *spdt$ps_crab; /*I Address of CRAB */N struct _cram *spdt$ps_poOrt_cram; /*I Address of CRAM */N struct _idb *spdt$l_port_idb; /*I Address of port IDB. */N struct _ucb *spdt$l_port_ucb; /*I Address of port UCB. */W struct _scdt *spdt$ps_erl_scdt; /*F SCDT address for error logging operation */O struct _sdbg *spdt$l_scsi_debug; /*F SCSIDEBUG data structure pointer */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_a Olignment __quadword#else#pragma __nomember_alignment#endifQ struct _scsi_rbun *spdt$ps_rbun_lal; /*P X-48 Listhead for available RBUNs */#pragma __nomember_alignmentN unsigned int spdt$l_rbun_lal_seqnum; /*P Sequence number for RBUN_LAL */N void *spdt$ps_qman_kpb; /*F Queue manager's KPB address. */S void *spdt$ps_chip_kpb; /*S KPB address that owns the SCSI chip. */] void *spdt$ps_ondeck_kpb; /*S KPB address that is waiting for thOe SCSI chip. */N struct _spl *spdt$ps_spl_port; /*I Port spinlock address */N/* */O/* This TQE is used by the port driver to timeout pending disconnected IO's */Q/* When this TQE expires, the timer thread will timeout expired pending IO's. */N/* */ N unsigned char spdt$b_tqe [64]; /*F Timer queue entry */ON unsigned int spdt$l_tqe_delay; /*F Delay time for next TQE delay. */N/* */I/* Define the reset fork block */N/* */( char spdt$t_fkb_quad_align_fill [4];Y FKB spdt$r_reset_fkb; /*I Embedded quadword aligned reset fork block */N/* O */I/* Define a SCSI bus-reset-cleanup fork block */N/* */ a FKB spdt$r_reset_cleanup_fkb; /*I Embedded quadword aligned reset cleanup fork block */N/* */B/* Port specific DMA information. */N/* O */N void *spdt$l_dma_base; /*F Base address of DMA buffer */N int spdt$l_spte_base_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */N int spdt$l_spte_svapte_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */Q unsigned int spdt$is_extmapreg; /*F Extra (guard etc.) map regs needed */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_ali Ognment#endifN unsigned __int64 spdt$q_read_pad_ba; /*F Bus address of black hole page */N unsigned __int64 spdt$q_write_pad_ba; /*F Bus address of erase page */N/* */B/* SCSI port event counters */N/* */C/* These counters are for events that are characteristic of the */B/* port not a connection and thOat don't need to be recorded on */B/* a connection by connection basis. */N/* */#pragma __nomember_alignmentT unsigned int spdt$l_tarrst_cnt; /*F Count of target initiated bus resets. */W unsigned int spdt$l_retry_cnt; /*F Count of total number of retry attempts. */Y unsigned int spdt$l_stray_int_cnt; /*F Count of interrupts when no owner of chan. */^ unsigned int spdt$l_Ounexp_int_cnt; /*F Count of unexpected interrupts when chan owned. */[ unsigned int spdt$l_nodiscon_cnt; /*F Count of reselections when not disconnected. */U unsigned int spdt$is_event_cnt; /*F Count number of events this interrupt. */g int spdt$is_total_io_count; /*F Total outstanding I/O count (DEVICE_QUEUE & PORT_QUEUE). */Z int spdt$is_port_io_count; /*F Count of I/Os currently on all PORT_QUEUEs. */\ int spdt$is_dev_io_count; /*F Count of IO/Os currently on all DEVICE_QUEUEs. */Y int spdt$is_queue_spins; /*F Number of loops through the queue manager. */\ int spdt$is_queue_exits; /*F Number of times the queue manager has exited. */N/* */B/* STDT hash table information. */N/* */N/* Number of bits in the hash value O */N/* Changed from 3 to 4 for high SCSI Id's */N/* Starting position of those bits. */N void *spdt$ps_stdt_hash_table [16]; /*F STDT hash table. */B/* Command buffer slot information. */N/* */D/* The following fields are used to manage allocation of command */B/* buffer slots, foOr port drivers that require that concept. */N/* */N void *spdt$ps_cmd_base; /*I Base address of CMD buffers */R struct _spdt *spdt$ps_cmd_spdt; /*I The SPDT that manages command slots */N void *spdt$ps_cmdwtfl; /*F Wait queue forward pointer */N void *spdt$ps_cmdwtbl; /*F Wait queue backward pointer */N/* Total number of command slots. O */N/* Total longwords for command slot allocation bit map. */O unsigned int spdt$il_cmd_bits [8]; /*F Command slot allocation bit map. */N/* Create max bus & bus config width for - */N/* high SCSI ID's */ __union {Q unsigned int spdt$l_scsi_bus_widths; /*F SCSI bus width related values */ __struct {Y unsigned short int spdt$Oiw_max_bus_width; /*F Maximum supported by adapter */_ unsigned short int spdt$iw_config_bus_width; /*F Maximum supported as configured */ } spdt$r_fill_7_; } spdt$r_fill_6_;N/*F */f unsigned int spdt$l_scsi_auto_id; /*F SCSI ID of device for which LUN autoconfig is inhibited */N struct _spl *spdt$ps_spl_fork; /*I Fork spinlock address */] int spdt$l_fp_cdb_lengthO; /* CDB length supported on FastPath, 0 if variable */d struct _fkb *spdt$ps_fp_kpb_fkb; /* Fork/wait block used to allocate & start FastPath KPBs */R struct _scdrp *spdt$ps_fp_kpb_wqfl; /* FastPath KPB Wait Queue forward link */S struct _scdrp *spdt$ps_fp_kpb_wqbl; /* FastPath KPB Wait Queue backward link */N/* */Y/* Save some space for future expansion. Reserved to Digital, ALPHA/VMS development.O */N/* */d int spdt$l_rsvd_long [3]; /*F Port specific space that may be used for any purpose. */N/* */B/* Save some space for Port specific extensions. */N/* */d int spdt$l_port_specific [3]; /*F Port specific space that may be used for any pOurpose. */N/* */B/* Define the length of this structure. */N/* */Y void *spdt$ps_first_stdt; /*F First STDT on which to to try to start I/O */[ void *spdt$ps_qdepth_table; /*F Address of a port-specific queue depth table */O int ((*(*spdt$ps_pk_intercept)))(); /*I Intercepted class driver vectors */ON int ((*(*spdt$ps_cd_intercept)))(); /*I Intercepted port driver vectors */N int spdt$l_def_spl_ctx; /*I Default spinlock context */N struct _spl *spdt$ps_spl_dyn; /*I Dynamic spinlock address */N/* X-57 Add ASCIZ firmware version buffer */& char spdt$b_firmware_version [16];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword O#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *spdt$pq_spte_base_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else( unsigned __int64 spdt$pq_spte_base_sva;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size d Oefault to 64-bit pointers */N void *spdt$pq_spte_svapte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else* unsigned __int64 spdt$pq_spte_svapte_sva;#endif } SPDT; #if !defined(__VAXC)F#define spdt$is_scsi_id_num spdt$r_scsi_id_overlay.spdt$is_scsi_id_numD#define spdt$q_scsi_id_num spdt$r_scsi_id_overlay.spdt$q_scsi_id_num:#define spdt$l_port_flags spdt$r_fill_0_.spdt$l_port_flagsI#define spdt$v_pflg_synch spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_synchK#define spdt$v_pflOg_asynch spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_asynchU#define spdt$v_pflg_mapping_reg spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_mapping_regM#define spdt$v_pflg_buf_dma spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_buf_dmaM#define spdt$v_pflg_dir_dma spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_dir_dmaE#define spdt$v_pflg_aen spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_aenG#define spdt$v_pflg_luns spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_lunsG#define spdt$v_pflg_cmdq spdt$r_fill_0_.spdt$r_fill_O1_.spdt$v_pflg_cmdqQ#define spdt$v_pflg_autosense spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_autosense[#define spdt$v_pflg_port_autosense spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_port_autosenseS#define spdt$v_pflg_smart_port spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_smart_portG#define spdt$v_pflg_dipl spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_diplS#define spdt$v_pflg_64bit_luns spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_64bit_lunsQ#define spdt$v_pflg_transport spdt$r_fill_0_.spdt$r_fill_1_.Ospdt$v_pflg_transportQ#define spdt$v_pflg_path_info spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_path_info_#define spdt$v_pflg_maxbcnt_override spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_maxbcnt_overrideM#define spdt$v_pflg_ext_lun spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_ext_lunQ#define spdt$v_pflg_imp_qfull spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_imp_qfullM#define spdt$v_pflg_spl_ctx spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_spl_ctxQ#define spdt$v_pflg_perf_data spdt$r_fill_0_.spdt$r_fillO_1_.spdt$v_pflg_perf_dataY#define spdt$v_pflg_go_io_credits spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_go_io_creditsO#define spdt$v_pflg_hba_mode spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_hba_mode_#define spdt$v_pflg_firmware_version spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_firmware_version]#define spdt$v_pflg_virtual_machine spdt$r_fill_0_.spdt$r_fill_1_.spdt$v_pflg_virtual_machine,#define spdt$l_sts spdt$r_fill_2_.spdt$l_stsI#define spdt$v_sts_online spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sOts_onlineI#define spdt$v_sts_timout spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_timoutK#define spdt$v_sts_erlogip spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_erlogipI#define spdt$v_sts_cancel spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_cancelG#define spdt$v_sts_power spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_powerC#define spdt$v_sts_bsy spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_bsyI#define spdt$v_sts_failed spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_failedK#define spdt$v_sts_fifolck spdt$r_fill_2_.spOdt$r_fill_3_.spdt$v_sts_fifolckQ#define spdt$v_sts_qwork_todo spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_qwork_todoU#define spdt$v_sts_reset_issued spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_reset_issued?#define spdt$v_spare spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_spareO#define spdt$v_sts_multihost spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_multihostU#define spdt$v_sts_timeout_soon spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_timeout_soonS#define spdt$v_sts_timeout_now spdt$r_fill_2_.spdt$r_fill_3_.spdOt$v_sts_timeout_nowM#define spdt$v_sts_saw_tape spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_saw_tapeU#define spdt$v_sts_first_config spdt$r_fill_2_.spdt$r_fill_3_.spdt$v_sts_first_config6#define spdt$l_dipl_sts spdt$r_fill_4_.spdt$l_dipl_stsa#define spdt$v_dipl_reset_in_progress spdt$r_fill_4_.spdt$r_fill_5_.spdt$v_dipl_reset_in_progress_#define spdt$v_dipl_reset_fork_inuse spdt$r_fill_4_.spdt$r_fill_5_.spdt$v_dipl_reset_fork_inusee#define spdt$v_dipl_reset_detected_wait spdt$r_fill_4_.spdt$r_Ofill_5_.spdt$v_dipl_reset_detected_waitQ#define spdt$v_dipl_stdt_scdt spdt$r_fill_4_.spdt$r_fill_5_.spdt$v_dipl_stdt_scdte#define spdt$v_dipl_reset_cu_fork_inuse spdt$r_fill_4_.spdt$r_fill_5_.spdt$v_dipl_reset_cu_fork_inuseQ#define spdt$r_cd_vectors_struct spdt$r_cd_vectors_union.spdt$r_cd_vectors_structR#define spdt$ps_cd_abort_command spdt$r_cd_vectors_struct.spdt$ps_cd_abort_commandL#define spdt$ps_cd_buffer_map spdt$r_cd_vectors_struct.spdt$ps_cd_buffer_mapP#define spdt$ps_cd_buffer_unmaOp spdt$r_cd_vectors_struct.spdt$ps_cd_buffer_unmapX#define spdt$ps_cd_cmd_buffer_alloc spdt$r_cd_vectors_struct.spdt$ps_cd_cmd_buffer_alloc\#define spdt$ps_cd_cmd_buffer_dealloc spdt$r_cd_vectors_struct.spdt$ps_cd_cmd_buffer_deallocF#define spdt$ps_cd_connect spdt$r_cd_vectors_struct.spdt$ps_cd_connect^#define spdt$ps_cd_connection_char_get spdt$r_cd_vectors_struct.spdt$ps_cd_connection_char_get^#define spdt$ps_cd_connection_char_set spdt$r_cd_vectors_struct.spdt$ps_cd_connection_char_setL#definOe spdt$ps_cd_disconnect spdt$r_cd_vectors_struct.spdt$ps_cd_disconnectN#define spdt$ps_cd_queue_flush spdt$r_cd_vectors_struct.spdt$ps_cd_queue_flushP#define spdt$ps_cd_queue_freeze spdt$r_cd_vectors_struct.spdt$ps_cd_queue_freezeR#define spdt$ps_cd_queue_release spdt$r_cd_vectors_struct.spdt$ps_cd_queue_releaseP#define spdt$ps_cd_reset_device spdt$r_cd_vectors_struct.spdt$ps_cd_reset_deviceT#define spdt$ps_cd_reset_scsi_bus spdt$r_cd_vectors_struct.spdt$ps_cd_reset_scsi_busP#define spdt$ps_cd_sOend_command spdt$r_cd_vectors_struct.spdt$ps_cd_send_command\#define spdt$ps_cd_initial_processing spdt$r_cd_vectors_struct.spdt$ps_cd_initial_processingR#define spdt$ps_cd_get_path_info spdt$r_cd_vectors_struct.spdt$ps_cd_get_path_infoX#define spdt$ps_cd_scsipath_connect spdt$r_cd_vectors_struct.spdt$ps_cd_scsipath_connectR#define spdt$ps_cd_get_port_wwid spdt$r_cd_vectors_struct.spdt$ps_cd_get_port_wwidL#define spdt$ps_cd_fp_request spdt$r_cd_vectors_struct.spdt$ps_cd_fp_requestF#define spdt$pOs_cd_fp_send spdt$r_cd_vectors_struct.spdt$ps_cd_fp_sendP#define spdt$ps_cd_fp_free_rbun spdt$r_cd_vectors_struct.spdt$ps_cd_fp_free_rbunD#define spdt$ps_cd_cancel spdt$r_cd_vectors_struct.spdt$ps_cd_cancelE#define spdt$ps_cd_vectors spdt$r_cd_vectors_union.spdt$ps_cd_vectorsQ#define spdt$r_pk_vectors_struct spdt$r_pk_vectors_union.spdt$r_pk_vectors_structR#define spdt$ps_pk_abort_command spdt$r_pk_vectors_struct.spdt$ps_pk_abort_commandX#define spdt$ps_pk_cmd_buffer_alloc spdt$r_pk_vectors_stOruct.spdt$ps_pk_cmd_buffer_alloc\#define spdt$ps_pk_cmd_buffer_dealloc spdt$r_pk_vectors_struct.spdt$ps_pk_cmd_buffer_dealloc^#define spdt$ps_pk_cmd_wait_completion spdt$r_pk_vectors_struct.spdt$ps_pk_cmd_wait_completionF#define spdt$ps_pk_connect spdt$r_pk_vectors_struct.spdt$ps_pk_connect^#define spdt$ps_pk_connection_char_set spdt$r_pk_vectors_struct.spdt$ps_pk_connection_char_setJ#define spdt$ps_pk_init_spdt spdt$r_pk_vectors_struct.spdt$ps_pk_init_spdtJ#define spdt$ps_pk_init_stdt spdt$r_pkO_vectors_struct.spdt$ps_pk_init_stdtV#define spdt$ps_pk_negotiate_synch spdt$r_pk_vectors_struct.spdt$ps_pk_negotiate_synchN#define spdt$ps_pk_queue_flush spdt$r_pk_vectors_struct.spdt$ps_pk_queue_flushP#define spdt$ps_pk_queue_freeze spdt$r_pk_vectors_struct.spdt$ps_pk_queue_freezeR#define spdt$ps_pk_queue_release spdt$r_pk_vectors_struct.spdt$ps_pk_queue_releaseT#define spdt$ps_pk_reset_scsi_bus spdt$r_pk_vectors_struct.spdt$ps_pk_reset_scsi_busP#define spdt$ps_pk_send_command spdt$r_pk_vectorOs_struct.spdt$ps_pk_send_commandR#define spdt$ps_pk_get_path_info spdt$r_pk_vectors_struct.spdt$ps_pk_get_path_infoL#define spdt$ps_pk_fp_request spdt$r_pk_vectors_struct.spdt$ps_pk_fp_requestF#define spdt$ps_pk_fp_send spdt$r_pk_vectors_struct.spdt$ps_pk_fp_sendP#define spdt$ps_pk_fp_free_rbun spdt$r_pk_vectors_struct.spdt$ps_pk_fp_free_rbunX#define spdt$ps_pk_fp_cmd_wait_comp spdt$r_pk_vectors_struct.spdt$ps_pk_fp_cmd_wait_compX#define spdt$ps_pk_fp_kp_completion spdt$r_pk_vectors_struct.spdt$Ops_pk_fp_kp_completionL#define spdt$ps_pk_alloc_pool spdt$r_pk_vectors_struct.spdt$ps_pk_alloc_poolJ#define spdt$ps_pk_free_pool spdt$r_pk_vectors_struct.spdt$ps_pk_free_poolP#define spdt$ps_pk_scsi_command spdt$r_pk_vectors_struct.spdt$ps_pk_scsi_commandD#define spdt$ps_pk_cancel spdt$r_pk_vectors_struct.spdt$ps_pk_cancelF#define spdt$ps_pk_trigger spdt$r_pk_vectors_struct.spdt$ps_pk_triggerZ#define spdt$ps_pk_target_disconnect spdt$r_pk_vectors_struct.spdt$ps_pk_target_disconnectE#define spdtO$ps_pk_vectors spdt$r_pk_vectors_union.spdt$ps_pk_vectorsD#define spdt$l_scsi_bus_widths spdt$r_fill_6_.spdt$l_scsi_bus_widthsQ#define spdt$iw_max_bus_width spdt$r_fill_6_.spdt$r_fill_7_.spdt$iw_max_bus_widthW#define spdt$iw_config_bus_width spdt$r_fill_6_.spdt$r_fill_7_.spdt$iw_config_bus_width"#endif /* #if !defined(__VAXC) */ O/* X-57 - SDL automatically defines a $S_ symbol for any aggregate. Bliss is */P/* pretty intolerant of duplicate symbol definitions, so we'll iflanguage it */ OP/* out. Macro would actually be OK with the duplicate, but since we have this */Q/* conditional anyway we'll avoid generating it. It would be nice to have this */O/* at the array definition, but iflanguage doesn't work within an aggregate. */ "#define SPDT$S_FIRMWARE_VERSION 16  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined requiredO ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SPDTDEF_LOADED */ ww2[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disOclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without O **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS OSDL V3.7 */F/* Source: 14-OCT-1999 15:51:51 $1$DGA8345:[LIB_H.SRC]SPIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SPIDEF ***/#ifndef __SPIDEF_LOADED#define __SPIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr sOize pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_strOuct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */I/* $SPIDEF - SCSI CLASS/PORT DRIVER INTERFACE DEFINITIONS. */N/*- */ N#define SPI$K_PBCB_STOP_BUSY -1 /* Port is busy */W#define SPI$K_PBCB_STOP_CHECK_CONDITOION -2 /* Port has seen a check condition event. */R#define SPI$K_PBCB_STOP_QUEUE_FULL_EVNT -3 /* Port has seen a queue full event. */N#define SPI$K_PBCB_STOP_BUS_RESET -4 /* Port has seen a bus reset */R#define SPI$K_PBCB_STOP_NO_SEND_CREDITS -5 /* Port has run out of send credits. */N#define SPI$K_PBCB_STOP_NO_CMD_BITS -6 /* Port has run out of cmd bits */N#define SPI$K_PBCB_STOP_LINK -7 /* FibreChannel link is unavailable */N#define SPI$K_PBCB_GO_READY 0 /* POort is no longer busy */S#define SPI$K_PBCB_GO_ACA_COMPLETE 1 /* Port has finished the ACA processing. */u#define SPI$K_PBCB_GO_QUEUE_STARTING 2 /* Port is attempting to restart the queue following the queue full event. */V#define SPI$K_PBCB_GO_BUS_FREE 3 /* Port has finished bus reset, bus is free */N#define SPI$K_PBCB_GO_SEND_CREDITS 4 /* Port has send credits available */N#define SPI$K_PBCB_GO_CMD_BITS 5 /* Port has cmd bits available */N#define SPI$K_PBOCB_GO_LINK 6 /* FibreChannel link is available */N/* */N/* SPI$K_PCB_CHANGE_AFFINITY has a value of 127, make sure */N/* that the entry you're adding does't conflict with that! */N/* */P#define SPI$K_PCB_AFFINITY 127 /* Port has set affinity to a new CPU */N/* Structure used by SPI$GET_CONNECTION_ OCHAR and SPI$SET_CONNECTION_CHAR */N#define SPI$K_CC_NUM_ARGS 10 /* Current required count */N#define SPI$K_CC_QNUM_ARGS 12 /* TCQ adds 2 longword arguments */#define SPI$M_CC_ENA_DISCON 0x1#define SPI$M_CC_DIS_RETRY 0x2##define SPI$M_CC_CLASS_REQ_SDTR 0x8##define SPI$M_CC_SUPPRESS_SDTR 0x10N#define SPI$K_CC_DEF_FLAGS 0 /* Default connection flags */N#define SPI$K_CC_DEF_SYNCH 0 /* Default synch xfer support */N#defOine SPI$K_CC_DEF_XFERPERIOD 64 /* Default REQ/ACK tick count */N#define SPI$K_CC_DEF_REQACKOFF 3 /* Default REQs before ACK */N#define SPI$K_CC_DEF_BSYRTY 2000 /* Default bus free retry cnt */N#define SPI$K_CC_DEF_ARBRTY 5 /* Default arb retry count */N#define SPI$K_CC_DEF_SELRTY 3 /* Default sel retry count */N#define SPI$K_CC_DEF_CMDRTY 3 /* Default cmd retry count */N#define SPI$K_CC_DEF_DMATMO 4 O /* Default DMA/Phase timeout */N#define SPI$K_CC_DEF_DISCTMO 4 /* Default Disconnect timeout */#define SPI$M_CC_CMDQ 0x1#define SPI$M_CC_FLUSHQ 0x2#define SPI$M_CC_FREEZEQ 0x4#define SPI$M_CC_SCSI_2 0x8#define SPI$M_CC_SCSI_3 0x10"#define SPI$M_CC_CLS_DRVR_ACA 0x20N#define SPI$K_CC_DEF_MAX_QDEPTH 1 /* Default maximum queue depth */N#define SPI$K_CC_LENGTH 52 /* Length of SPI_CC structure */R#define SPI$S_SPI_CC_DEF 52 O /* Old size name, synonym for SPI$S_SPI */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _spi {#pragma __nomember_alignmentN int spi$il_cc_count; /* Count of longword arguments */ __union {N unsigned int spi$il_cc_con_flags; /* Connection flags */ __struct {N O unsigned spi$v_cc_ena_discon : 1; /* Discon/Resel enabled */N unsigned spi$v_cc_dis_retry : 1; /* Disable command retry */N unsigned spi$v_cc_target_mode : 1; /* Target Mode (reserved) */X unsigned spi$v_cc_class_req_sdtr : 1; /* Class driver is requesting SDTR */X unsigned spi$v_cc_suppress_sdtr : 1; /* Class driver is suppressing SDTR */' unsigned spi$v_fill_4_ : 3; } spi$r_fill_1_; } spi$r_fill_0O_;N int spi$il_cc_synchronous; /* Sychronous transfer support */N int spi$il_cc_transfer_period; /* Ticks between REQ & ACK */N int spi$il_cc_reqack_offset; /* REQs before ACK */N int spi$il_cc_busy_retry_cnt; /* Retries before bus free */N int spi$il_cc_arb_retry_cnt; /* Retries before arbitration */N int spi$il_cc_sel_retry_cnt; /* Retries on selections */N int spi$il_cc_cmd_ Oretry_cnt; /* Retries on command send */N int spi$il_cc_dma_timeout; /* DMA/Phase timeout */N int spi$il_cc_disc_timeout; /* Disconnect timeout */ __union {N unsigned int spi$il_cc_scsi_flags; /* SCSI flags, including TCQ */ __struct {N unsigned spi$v_cc_cmdq : 1; /* Device supports TCQ */N unsigned spi$v_cc_flushq : 1; /* Flush queue on error */N/* MBZ, Oreserved for SCSI-3 */N unsigned spi$v_cc_freezeq : 1; /* Freeze queue on error */N/* MBZ, reserved for SCSI-3 */N unsigned spi$v_cc_scsi_2 : 1; /* Device is SCSI-2 conformant */N unsigned spi$v_cc_scsi_3 : 1; /* Device is SCSI-3 conformant */N unsigned spi$v_cc_cls_drvr_aca : 1; /* Class Driver needs ACA */' unsigned spi$v_fill_5_ : O 2; } spi$r_fill_3_; } spi$r_fill_2_;N int spi$il_cc_max_qdepth; /* Maximum queue depth if TCQ */ char spi$b_fill_6_ [4]; } SPI; #if !defined(__VAXC)=#define spi$il_cc_con_flags spi$r_fill_0_.spi$il_cc_con_flagsK#define spi$v_cc_ena_discon spi$r_fill_0_.spi$r_fill_1_.spi$v_cc_ena_disconI#define spi$v_cc_dis_retry spi$r_fill_0_.spi$r_fill_1_.spi$v_cc_dis_retryS#define spi$v_cc_class_req_sdtr spi$r_fill_0_.spi$r_fill_1_.spi$v_cc_class_req O_sdtrQ#define spi$v_cc_suppress_sdtr spi$r_fill_0_.spi$r_fill_1_.spi$v_cc_suppress_sdtr?#define spi$il_cc_scsi_flags spi$r_fill_2_.spi$il_cc_scsi_flags?#define spi$v_cc_cmdq spi$r_fill_2_.spi$r_fill_3_.spi$v_cc_cmdqC#define spi$v_cc_flushq spi$r_fill_2_.spi$r_fill_3_.spi$v_cc_flushqE#define spi$v_cc_freezeq spi$r_fill_2_.spi$r_fill_3_.spi$v_cc_freezeqC#define spi$v_cc_scsi_2 spi$r_fill_2_.spi$r_fill_3_.spi$v_cc_scsi_2C#define spi$v_cc_scsi_3 spi$r_fill_2_.spi$r_fill_3_.spi$v_cc_scsi_3OO#define spi$v_cc_cls_drvr_aca spi$r_fill_2_.spi$r_fill_3_.spi$v_cc_cls_drvr_aca"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SPIDEF_LOADED */ ww[UM/*******************************O********************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise DevelopmenOt, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** O **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */I/* Source: 29-APR-2021 17:27:35 $1$DGA8345:[LIB_H.SRC]SPLCODDEF.SDL;1 *//***************************************************************************** O***************************************************//*** MODULE $SPLCODDEF ***/#ifndef __SPLCODDEF_LOADED#define __SPLCODDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short O/* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ O */N/* */N/* SPINLOCK INDEX DEFINITIONS */N/* */N/*- */N/* */N/* DEFINE THE HARDWARE LEVEL LOCKS (INODICES 0-F) */N/* */N#define SPL$C_EMB 32 /* EMB spinlock index */N#define SPL$C_MCHECK 33 /* Machine Check spinlock index */N#define SPL$C_MEGA 34 /* Kitchen sink of spinlocks */N#define SPL$C_HWCLK 36 /* HWCLK spinlock index */N#define SPL$C_INVALIDATE 38 /* INVALIDATE spinlock iOndex */N#define SPL$C_PERFMON 40 /* PERFMON spinlock index */N#define SPL$C_POOL 42 /* POOL spinlock index */N#define SPL$C_POOL_S2 43 /* S2 POOL spinlock index */N#define SPL$C_MAILBOX 44 /* MAILBOX spinlock index */N#define SPL$C_IOLOCK11 46 /* IPL 11 I/O spinlock index */N#define SPL$C_IOLOCK10 47 /* IPL 10 I/O spinlock index */N#define SPOL$C_IOLOCK9 48 /* IPL 9 I/O spinlock index */N#define SPL$C_SCHED 50 /* SCHED spinlock index */N#define SPL$C_MMG 52 /* Memory management spinlock index */Y#define SPL$C_IO_MISC 54 /* Miscellaneous short time I/O spinlock index */N#define SPL$C_PORT 55 /* Multiple device ports index */N#define SPL$C_TIMER 56 /* TIMER spinlock index */N#define SPL$C_TX_SYNCH 5O7 /* Transaction processing lock */N#define SPL$C_IOLOCK8 58 /* IPL 8 I/O spinlock index */N#define SPL$C_LCKMGR 59 /* Lock Manager lock */N#define SPL$C_FILSYS 60 /* File system spinlock index */N#define SPL$C_QUEUEAST 62 /* QUEUEAST spinlock index */N#define SPL$C_SCS 58 /* SCS spinlock index */N/* Define dynamic spinlock symbol O */N#define SPL$C_DYNAMIC 255 /* DYNAMIC spinlock non-index */N#define SPL$_MIN_INDEX 32 /* Min spinlock index */N#define SPL$_MAX_INDEX 62 /* Max spinlock index */N#define SPL$_NUM_LOCKS 31 /* Max number of spinlocks (ever) */N/* */N/* Define some system-wide multiprocessing control flags O*/N/* */#define SMP$M_ENABLED 0x1#define SMP$M_START_CPU 0x2#define SMP$M_CRASH_CPU 0x4#define SMP$M_TODR 0x8#define SMP$M_UNMOD_DRIVER 0x10#define SMP$M_TODR_ACK 0x20#define SMP$M_SYNCH 0x40#define SMP$M_BENIGN 0x80##define SMP$M_MINIMUM_ACQUIRE 0x100#define SMP$M_READ_SCC 0x200 #define SMP$M_READ_SCC_ACK 0x400 #define SMP$M_CLOCKS_SYNCH 0x800(#define SMP$M_DISPLAY_TRANSITIONS 0x1000##define SMP$M_OFW_STATE_CHECK 0x2000##define SMP$M_MULTIQUAD_NMSP 0x4000#define SMP$M_OVERRIDE 0x1#define SMP$M_FOREVER 0x2 #define SMP$M_FKB_FRU_CHANGE 0x1#define SMP$M_FKB_DOORBELL 0x2S#define SMP$S_SMPDEF 4 /* Old size name, synonym for SMP$S_SMP */#define SMP$M_PORTLOCK 0x1#define SMP$M_INIT_ONLY 0x2#define SMP$M_KNOWN_BY_SDA 0x4 typedef struct _smp {N __struct { /* SMP$GL_FLAGS */N unsigned smp$v_enabled : 1; O /* SMP operation is enabled */N unsigned smp$v_start_cpu : 1; /* PRIMARY CPU has finished INIT */N unsigned smp$v_crash_cpu : 1; /* A CPU is initiating BUGCHECK */N unsigned smp$v_todr : 1; /* SMP$GL_PROPOSED_TODR in use */N unsigned smp$v_unmod_driver : 1; /* Unmodified driver is loaded */N unsigned smp$v_todr_ack : 1; /* SMP TODR operation complete */N unsigned smp$v_synch : 1; /* SMP SYNCHRONIZATION IOMAGE LOADED */N unsigned smp$v_benign : 1; /* BENIGN STATE REQUESTED */O unsigned smp$v_minimum_acquire : 1; /* Least overhead in acquisition */Q unsigned smp$v_read_scc : 1; /* Request PRIMARY CPU to read its SCC */V unsigned smp$v_read_scc_ack : 1; /* PRIMARY CPU has recorded its SCC value. */S unsigned smp$v_clocks_synch : 1; /* Clocks are synchronized....therefore */N/* soft affinity is supported on this system. O */U unsigned smp$v_display_transitions : 1; /* Display verbose transition text */[ unsigned smp$v_fw_state_check : 1; /* Toggle 1-second timer check for migrations */e unsigned smp$v_multiquad_nmsp : 1; /* Bitmaps of more than 1 quadword needed for namespace */# unsigned smp$v_fill_0_ : 1; } smp$r_flags;N __struct { /* Input to STOP/CPU */N unsigned smp$v_override : 1; /* Skip checks before stoppi Ong CPU */N unsigned smp$v_forever : 1; /* FOREVER means remove from */N/* available set after stopping. */# unsigned smp$v_fill_1_ : 6; } smp$r_stop_cpu_flags; __struct {Z unsigned smp$v_fkb_fru_change : 1; /* FKB to indicate config tree change in use */W unsigned smp$v_fkb_doorbell : 1; /* FKB for doorbell console callback in use */# unsigned smp$v_fill_2_ : 6; } smp$r_cfg_fkb_ Oflags;] __struct { /* input flag parameters for smp$create_spinlock() */W unsigned smp$v_portlock : 1; /* set rank and subtype to portlock defaults */^ unsigned smp$v_init_only : 1; /* initialize spinlocks only--don't allocate memory */] unsigned smp$v_known_by_sda : 1; /* note that SDA already recognizes this spinlock */# unsigned smp$v_fill_3_ : 5; } smp$r_creation_flags; } SMP; #if !defined(__VAXC)/#define sm Op$v_enabled smp$r_flags.smp$v_enabled3#define smp$v_start_cpu smp$r_flags.smp$v_start_cpu3#define smp$v_crash_cpu smp$r_flags.smp$v_crash_cpu)#define smp$v_todr smp$r_flags.smp$v_todr9#define smp$v_unmod_driver smp$r_flags.smp$v_unmod_driver1#define smp$v_todr_ack smp$r_flags.smp$v_todr_ack+#define smp$v_synch smp$r_flags.smp$v_synch-#define smp$v_benign smp$r_flags.smp$v_benign?#define smp$v_minimum_acquire smp$r_flags.smp$v_minimum_acquire1#define smp$v_read_scc smp$r_flags.smp$v_r Pead_scc9#define smp$v_read_scc_ack smp$r_flags.smp$v_read_scc_ack9#define smp$v_clocks_synch smp$r_flags.smp$v_clocks_synchG#define smp$v_display_transitions smp$r_flags.smp$v_display_transitions=#define smp$v_fw_state_check smp$r_flags.smp$v_fw_state_check=#define smp$v_multiquad_nmsp smp$r_flags.smp$v_multiquad_nmsp:#define smp$v_override smp$r_stop_cpu_flags.smp$v_override8#define smp$v_forever smp$r_stop_cpu_flags.smp$v_foreverE#define smp$v_fkb_fru_change smp$r_cfg_fkb_flags.smp$v_f Pkb_fru_changeA#define smp$v_fkb_doorbell smp$r_cfg_fkb_flags.smp$v_fkb_doorbell:#define smp$v_portlock smp$r_creation_flags.smp$v_portlock<#define smp$v_init_only smp$r_creation_flags.smp$v_init_onlyB#define smp$v_known_by_sda smp$r_creation_flags.smp$v_known_by_sda"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previouPsly-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SPLCODDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be uPsed, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosPed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-202 P4 15:23:30 by OpenVMS SDL V3.7 */F/* Source: 01-JUN-2009 19:57:52 $1$DGA8345:[LIB_H.SRC]SPLDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SPLDEF ***/#ifndef __SPLDEF_LOADED#define __SPLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* PDefined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#definPe __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif   #include N/* */N/* SPINLOCK Control Block */N/* */N#define SPL$C_SPL_SPINLOCK 1 /* Static system P spinlock */N#define SPL$C_SPL_FORKLOCK 2 /* Spinlock used for FORKLOCK */N#define SPL$C_SPL_DEVICELOCK 3 /* Dynamic spinlock (devicelock) */N#define SPL$C_SPL_PORTLOCK_TEMPLATE 4 /* Static portlock template */N#define SPL$C_SPL_PORTLOCK 5 /* Dynamic ranked portlock */#define SPL$M_INTERLOCK 0x1##define SPL$M_DYNAMIC_THRESHOLD 0x10#define SPL$M_BITMAP_POINTERS 0x8000000000000000N#define SPL$K_PC_VEC_CNT 8 /* S Pize of PC vector */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _spl {#pragma __nomember_alignmentO int spl$l_own_cpu; /* Owner CPU's per-cpu database addr */N int spl$l_own_cnt; /* Count of concurrent acquires */N unsigned short int spl$w_size; /* Structure size P */N unsigned char spl$b_type; /* Structure type */N unsigned char spl$b_subtype; /* Spinlock subtype */ __union {N unsigned int spl$l_spinlock; /* Structure lock semaphore */ __struct {N unsigned spl$v_interlock : 1; /* Spinlock access interlock */' unsigned spl$v_fill_4_ : 7; } spl$r_fill_1_; } spl$r_fill_0_;N void *spl$ps_share_array; P /* Pointer for Share array */N void *spl$ps_share_link; /* Pointer to the first Share */N/* array element */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 spl$q_release_count; /* Count of spinlock releases */#pragma __nomember_alignme PntQ unsigned __int64 spl$q_history_bitmask; /* CPU bitmask of acqs in sequence */N unsigned int spl$l_spares_1 [6]; /* pad to next 64-byte boundary */N int spl$l_rank; /* RANK of spinlock */N __union { /* Lock IPL defined for spinlock */N unsigned int spl$l_ipl; /* Lock IPL */ __struct {N unsigned char spl$b_ipl; /* Defined for first byte only P*/N char spl$b_fill1 [3]; /* */ } spl$r_ipl_fields; } spl$r_ipl_overlay;N unsigned int spl$l_timo_int; /* Busywait timeout interval */N char spl$t_name [12]; /* Spinlock name */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR unsi Pgned __int64 spl$q_abuse_threshold; /* Lock releases before abuse state */#pragma __nomember_alignmentU unsigned __int64 spl$q_abuse_bitmask; /* CPU bitmask that are currently abused */ __union {N unsigned __int64 spl$q_flags; /* Behavioral flags */ __struct {S unsigned spl$v_dynamic_threshold : 1; /* Set if threshold is dynamic */- unsigned spl$v_reserved_1_1 : 32;- unsigned spl$v_reserved_1_2 : 30;g Punsigned spl$v_bitmap_pointers : 1; /* Set if abuse/history bitmasks are bitmap pointers */ } spl$r_fill_3_; } spl$r_fill_2_;N unsigned int spl$l_spares_2 [4]; /* pad to next 64-byte boundary */ __union {O int spl$l_rls_pc; /* PC of nested acquisition releaser */O __int64 spl$q_rls_pc; /* PC of nested acquisition releaser */ } spl$r_rls_pc_overlay;N int spl$l_wait_cpus; /* Count of waiting CPPUs */N/* */N/* After much consultation, we think that BUSY_WAITS should be unsigned. */N/* The MACRO-32 source treats it as an unsigned longword integer, and */N/* tests for overflow by testing if the value is zero. */N/* */N unsigned int spl$l_busy_waits; /* Count of failed acquisitions */N __inPt64 spl$q_spins; /* Count number of spins */N unsigned __int64 spl$q_acq_count; /* Count of actual acquisitions */N/* */S/* Que header for singly linked deferred work. This queue header is synchronized */N/* by atomic updates. FKB type structures are queued to this header. If */P/* the queue is non-empty, the FPC routine in each FKB will be called passing */N/* fr3 and fr4. Note that P the FLCK field is ignored. */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif+ struct _fkb *spl$l_deferred_work_flink;#pragma __nomember_alignmentN char spl$t_align [24]; /* Assure 128 byte alignment */N int spl$l_vec_inx; P /* PC vector index */ __union {X int spl$l_own_pc_vec; /* 8 double longword PCs of acquires/releases */Q __int64 spl$q_own_pc_vec [8]; /* 8 PCs of quadword acquires/releases */ } spl$r_pc_vec_overlay; } SPL; #if !defined(__VAXC)3#define spl$l_spinlock spl$r_fill_0_.spl$l_spinlockC#define spl$v_interlock spl$r_fill_0_.spl$r_fill_1_.spl$v_interlock-#define spl$l_ipl spl$r_ipl_overlay.spl$l_ipl>#define spl$b_ipl Pspl$r_ipl_overlay.spl$r_ipl_fields.spl$b_ipl-#define spl$q_flags spl$r_fill_2_.spl$q_flagsS#define spl$v_dynamic_threshold spl$r_fill_2_.spl$r_fill_3_.spl$v_dynamic_thresholdO#define spl$v_bitmap_pointers spl$r_fill_2_.spl$r_fill_3_.spl$v_bitmap_pointers6#define spl$l_rls_pc spl$r_rls_pc_overlay.spl$l_rls_pc6#define spl$q_rls_pc spl$r_rls_pc_overlay.spl$q_rls_pc>#define spl$l_own_pc_vec spl$r_pc_vec_overlay.spl$l_own_pc_vec>#define spl$q_own_pc_vec spl$r_pc_vec_overlay.spl$q_own_pc_vec"#endPif /* #if !defined(__VAXC) */ N#define SPL$K_LENGTH 256 /* Structure size */N#define SPL$C_LENGTH 256 /* Structure size */T#define SPL$S_SPLDEF 256 /* Old size name, synonym for SPL$S_SPL */N/* */S/* The SPL_SHR structure is utilized for spinlocks being accessed as sharelocks. */P/* An array of SPL_SHR structure is allocated when a lock Pis going to be used */Q/* as a sharelock by the SMP$MAKE_LOCK routine. Enough elements are allocated */P/* for the maximum number of CPUs possible in the system. The SPL$ structure */N/* will point the array via SPL$L_SHARE_ARRAY. */N/* */N/* These elements are 128 bytes to avoid CPU cache contention. */N/* P*/N#define SPL_SHR$K_LENGTH 128 /* Structure size */N#define SPL_SHR$C_LENGTH 128 /* Structure size */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _spl_shr {#pragma __nomember_alignmentN unsigned int spl_shr$l_link; /* Link to next Share Array Element */N int spPl_shr$l_share_count; /* Number of Shared Acquires */N unsigned short int spl_shr$w_mbo; /* must-be-one field */N unsigned char spl_shr$b_type; /* Structure type (DYN$C_SPL_SHR) */N unsigned char spl_shr$b_subtype; /* Spinlock subtype (0) */Q int spl_shr$l_cpu_id; /* CPU ID associated with this element */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __Pnomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 spl_shr$q_size; /* Size */#pragma __nomember_alignmentP __int64 spl_shr$q_timeout_int; /* Busywait timeout interval (in ns.) */N char spl_shr$t_align [96]; /* Assure 128 byte alignment */ } SPL_SHR;#define SPLDBG$K_REV1 1#define SPLDBG$K_REVISION 1#define SPLDBG$K_ACQ 1#define SPLDBG$K_REL 2#define SPLDBG$K_SPIN 3#define SPPLDBG$K_FORKDSPTH 4#define SPLDBG$K_FORKEND 5#define SPLDBG$K_MAX_FLAG 5#define SPLDBG$K_ACQNOIPL 1#define SPLDBG$K_ACQUIRE 2#define SPLDBG$K_ACQUIREL 3#define SPLDBG$K_ACQNOIPL_OWN 4#define SPLDBG$K_ACQUIRE_OWN 5#define SPLDBG$K_ACQUIREL_OWN 6"#define SPLDBG$K_ACQUIRE_SHR_OWN 7!#define SPLDBG$K_ACQ_NOSPIN_OWN 8%#define SPLDBG$K_ACQ_SHR_NOSPIN_OWN 9!#define SPLDBG$K_ACQNOIPL_SPIN 10 #define SPLDBG$K_ACQUIRE_SPIN 11!#define SPLDBG$K_ACQUIREL_SPIN 12#define SPLDBG$K_RESTOPRE 13#define SPLDBG$K_RESTOREL 14#define SPLDBG$K_RELEASE 15#define SPLDBG$K_RELEASEL 16#define SPLDBG$K_ACQUIRE_SHR 17$#define SPLDBG$K_ACQUIRE_SHR_SPIN 18#define SPLDBG$K_RELEASE_SHR 19#define SPLDBG$K_RESTORE_SHR 20#define SPLDBG$K_ACQ_NOSPIN 21$#define SPLDBG$K_ACQ_NOSPIN_INUSE 22"#define SPLDBG$K_ACQ_SHR_NOSPIN 23(#define SPLDBG$K_ACQ_SHR_NOSPIN_INUSE 24!#define SPLDBG$K_ACQ_CVT_TO_EX 25'#define SPLDBG$K_ACQ_CVT_TO_EX_INUSE 26&#define SPLDBG$K_ACQ_CVT_TO_EX_SPIN 27"#dPefine SPLDBG$K_ACQ_CVT_TO_SHR 28#define SPLDBG$K_MAX_MODE 28#define SPLDBG$M_ACQUIRE 0x1#define SPLDBG$M_RELEASE 0x2#define SPLDBG$M_SPINWAIT 0x4#define SPLDBG$M_LCKMGR 0x8#define SPLDBG$M_FORKDSPTH 0x10#define SPLDBG$M_FORKEND 0x20N#define SPLDBG$K_LENGTH 116 /* Structure size */N#define SPLDBG$C_LENGTH 116 /* Structure size */  9#ifdef __cplusplus /* Define structure prototypes */struct _spltrh; #endif P/* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _spldbg {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _spltrh *spldbg$q_trace_buffer; /* pointer Pto trace buffer */#else( unsigned __int64 spldbg$q_trace_buffer;#endifN unsigned short int spldbg$w_mbo; /* must-be-one field */N unsigned char spldbg$b_type; /* Structure type (DYN$C_SPLX) */N unsigned char spldbg$b_subtype; /* Spinlock subtype (DYN$C_SPLDBG) */N unsigned int spldbg$l_revision; /* revision field */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */' P#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 spldbg$q_size; /* Size */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN int (*spldbg$l_start_trace)(); /* ptr to start trace routine */N int (*spldbg$l_stop_trace)(); /* P ptr to stop trace routine */N void (*spldbg$l_trace_acquire)(); /* ptr to trace acquire routine */N void (*spldbg$l_trace_release)(); /* ptr to trace release routine */N void (*spldbg$l_trace_spinwait)(); /* ptr to trace spinwait routine */P void (*spldbg$l_trace_forkdspth)(); /* ptr to trace fork dispatch routine */N void (*spldbg$l_trace_forkend)(); /* ptr to trace end fork routine */ __union {N unsigned int spldbg$l_trace_flags; /* trac !Pe flags */ __struct {* unsigned spldbg$v_acquire : 1;* unsigned spldbg$v_release : 1;+ unsigned spldbg$v_spinwait : 1;) unsigned spldbg$v_lckmgr : 1;, unsigned spldbg$v_forkdspth : 1;* unsigned spldbg$v_forkend : 1;* unsigned spldbg$v_fill_5_ : 2;( } spldbg$r_trace_flags_bits;' } spldbg$r_trace_flags_overlay;N unsigned int spldbg$l_spl_flags; /* trace specific "Pspinlock */N int spldbg$l_cpu_flags; /* trace specific CPU */N unsigned int spldbg$l_frk_flags; /* trace specific forklock */N unsigned int spldbg$l_trace_run; /* trace run index */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif( unsigned __int64 spldbg$q_reserved1;#pragma __no #Pmember_alignment( unsigned __int64 spldbg$q_reserved2;( unsigned __int64 spldbg$q_reserved3;( unsigned __int64 spldbg$q_reserved4;_ unsigned __int64 *spldbg$pq_scc; /* pointer to array of cycle counts per possible CPU */` unsigned __int64 *spldbg$pq_systime; /* pointer to array of systime info per possible CPU */ int spldbg$l_max_cpus; char spldbg$b_fill_6_ [4]; } SPLDBG; #if !defined(__VAXC)N#define spldbg$l_trace_flags spldbg$r_trace_flags_overlay.spldbg$P$l_trace_flags`#define spldbg$v_acquire spldbg$r_trace_flags_overlay.spldbg$r_trace_flags_bits.spldbg$v_acquire`#define spldbg$v_release spldbg$r_trace_flags_overlay.spldbg$r_trace_flags_bits.spldbg$v_releaseb#define spldbg$v_spinwait spldbg$r_trace_flags_overlay.spldbg$r_trace_flags_bits.spldbg$v_spinwait^#define spldbg$v_lckmgr spldbg$r_trace_flags_overlay.spldbg$r_trace_flags_bits.spldbg$v_lckmgrd#define spldbg$v_forkdspth spldbg$r_trace_flags_overlay.spldbg$r_trace_flags_bits.spldbg$v_forkdsp%Pth`#define spldbg$v_forkend spldbg$r_trace_flags_overlay.spldbg$r_trace_flags_bits.spldbg$v_forkend"#endif /* #if !defined(__VAXC) */ N#define SPLTRE$K_LENGTH 40 /* Structure size */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ktb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __no &Pmember_alignment#endiftypedef struct _spltre {#pragma __nomember_alignmentO unsigned __int64 spltre$q_timestamp; /* timestamp in system cycle counts */N __int64 spltre$q_pc; /* callers PC or fork PC */Q unsigned int spltre$l_cpuid; /* current CPU id or address of CPU db */N unsigned int spltre$l_mode; /* general trace category */N unsigned int spltre$l_flag; /* which event was traced */N struct _pcb *s 'Ppltre$l_pcb; /* current process during trace */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */S struct _spl *spltre$q_spl_addr; /* spinlock tracing: address of spinlock */#else$ unsigned __int64 spltre$q_spl_addr;#endifN unsigned int spltre$l_flck; /* fork tracing: fork lock index */ } spltre$r_overlay1; (P } SPLTRE; #if !defined(__VAXC)=#define spltre$q_spl_addr spltre$r_overlay1.spltre$q_spl_addr5#define spltre$l_flck spltre$r_overlay1.spltre$l_flck"#endif /* #if !defined(__VAXC) */ N#define SPLTRH$K_LENGTH 72 /* Structure size */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _spltrh {#pragm)Pa __nomember_alignmentN int spltrh$l_idx; /* current index into trace buffer */N unsigned int spltrh$l_max_idx; /* maximum trace index */N unsigned short int spltrh$w_mbo; /* must-be-one field */N unsigned char spltrh$b_type; /* Structure type (DYN$C_SPLX) */N unsigned char spltrh$b_subtype; /* Spinlock subtype (DYN$C_SPLTRH) */ unsigned int spltrh$l_fill1;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined *P(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 spltrh$q_size; /* Size */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _spltre *spltrh$q_entry_ptr; /* pointer to first trace entry */ +P#else% unsigned __int64 spltrh$q_entry_ptr;#endifN SPLTRE spltrh$r_entry [1]; /* array of trace entries */ } SPLTRH;N/* */I/* NPP data structure to hold a list of spinlock addresses */I/* that are not in one of SDA's known lists (static, device, */I/* port, mailbox, PCB, cached PCB, Pshared). */I/* Note that size of structure (and number o ,Pf entries) can */I/* be changed by altering #splptr_size below. */N/* */N#define SPLPTR$C_ENTRIES 125 /* the maximum number of addresses */N#define SPLPTR$C_LENGTH 512 /* Structure size */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#p -Pragma __nomember_alignment#endiftypedef struct _splptr {N/* Size of SPLPTR structure */#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _splptr *splptr$ps_flink; /* Pointer to next array */R unsigned int splptr$l_count; /* Number of entries used in .P this block */N unsigned short int splptr$w_size; /* Structure size (SPLPTR$C_LENGTH) */N unsigned char splptr$b_type; /* Structure type (DYN$C_SPLX) */N unsigned char splptr$b_subtype; /* Structure subtype (DYN$C_SPLPTR) */N/* Number of longword entries that will fit */N struct _spl *splptr$ps_spinlock [125]; /* Up to n spinlock addresses */ } SPLPTR; N/* /P */N/* Spinlock Pointer Declarations */N/* */&#pragma __required_pointer_size __save&#pragma __required_pointer_size __long\typedef SPL *SPL_PQ; /* long pointer to a spinlock structure */)#pragma __required_pointer_size __restore $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas suppor0Pted */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SPLDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard 1PEnterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., a2Pnd is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************************************** 3P*********************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */G/* Source: 21-APR-1993 10:53:55 $1$DGA8345:[LIB_H.SRC]SPNBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SPNBDEF ***/#ifndef __SPNBDEF_LOADED#define __SPNBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment _4P_save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifnde5Pf __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SPNB - SCA POLLER NAME BLOCK */N/* */N/* THIS DATA STRUCTU 6PRE CONTAINS A LIST OF PROCESS NAMES WHICH WILL */N/* BE SEARCHED FOR ON THE GIVEN REMOTE NODE. */N/*- */ N#define SPNB$C_HDRSIZ 24 /*SIZE OF HEADER */#define SPNB$S_SPNBDEF 25 typedef struct _spnb {N struct _spnb *spnb$l_flink; /*FWD LINK */N struct _spnb *spnb$l_blink; /*BCK LINK 7P */N unsigned short int spnb$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char spnb$b_type; /*SCS STRUCTURE TYPE */N unsigned char spnb$b_subtyp; /*SCS STRUCTURE SUBTYPE FOR SPNB */N unsigned int spnb$l_sb; /*SYSTEM BLOCK OF REMOTE NOTE */_ int (*spnb$l_routine)(); /*ADDRESS OF ROUTINE TO BE CALLED WHEN PROCESS FOUND */b unsigned char spnb$b_index; /*INDEX INTO PROCESS LIST OF NEXT 8PPROCESS TO SEARCH FOR */N unsigned short int spnb$w_refc; /*NUMBER OF REFERENCES TO SPNB */N unsigned char spnb$b_free [1]; /*FREE BYTE */h unsigned char spnb$b_namlst; /*START OF VARIABLE LENGTH LIST OF ADDRESSES OF PROCESS NAMES */N/*LIST IS ZERO TERMINATED */ } SPNB; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporte9Pd */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SPNBDEF_LOADED */ wwk[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard :PEnterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., a;Pnd is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************************************** Pf __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define PDIR$M_VINDEX 0xFF#define PDIR$M_SV 0x800##define PDIR$M_V 0x8000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __no ?Pmember_alignment#endiftypedef struct _sppa_io_pdir {#pragma __nomember_alignmentN unsigned pdir$v_vindex : 8; /* Virtual index 0xFF on Itanium */N unsigned pdir$v_reserved_pdir_1 : 3; /* Reserved */N unsigned pdir$v_sv : 1; /* Swap control field is valid */#if defined(__VAXC) unsigned pdir$v_ppn_1 : 32; unsigned pdir$v_ppn_2 : 11;#elseN unsigned __int64 pdir$v_ppn : 43; /* Physical Page number (PFN) */@P#endifQ unsigned pdir$v_swap_ctrl : 8; /* Swap control field (documentation?) */N unsigned pdir$v_v : 1; /* Valid PDIR entry */ } SPPA_IO_PDIR; c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sppa_func_hdr {#pragma __nomember_alignment __union {N unsigned __int64 sppa$q_func_iAPd; /* 000 Function Id */ __struct {N __struct { /* v- PCI Config Space Offset */N unsigned short int sppa$w_vendor_id; /* 00 HP is 103C */S unsigned short int sppa$w_function_id; /* 02 Unique w/in Vendor */N unsigned short int sppa$w_control; /* 04 See PCI Spec */N unsigned short int sppa$w_status; /* 06 See PCI spec */& } sppa$r_fill_func_i BPd; } sppa$r_fill_1_; } sppa$r_fill_0_; __union {N unsigned __int64 sppa$q_func_class; /* 008 Function Class */ __struct {N __struct { /* v- PCI Config Space Offset */N unsigned char sppa$b_revision; /* 08 Rev w/in Function ID */P unsigned char sppa$b_interface; /* 09 Class Code - Interface */O unsigned char sppa$b_sub_class; /* 0A Class Code - Subclass */R CP unsigned char sppa$b_base_class; /* 0B Class Code - Base Class */) } sppa$r_fill_func_class; } sppa$r_fill_3_; } sppa$r_fill_2_; } SPPA_FUNC_HDR; #if !defined(__VAXC)4#define sppa$q_func_id sppa$r_fill_0_.sppa$q_func_id[#define sppa$w_vendor_id sppa$r_fill_0_.sppa$r_fill_1_.sppa$r_fill_func_id.sppa$w_vendor_id_#define sppa$w_function_id sppa$r_fill_0_.sppa$r_fill_1_.sppa$r_fill_func_id.sppa$w_function_idW#define sppa$w_control sDPppa$r_fill_0_.sppa$r_fill_1_.sppa$r_fill_func_id.sppa$w_controlU#define sppa$w_status sppa$r_fill_0_.sppa$r_fill_1_.sppa$r_fill_func_id.sppa$w_status:#define sppa$q_func_class sppa$r_fill_2_.sppa$q_func_class\#define sppa$b_revision sppa$r_fill_2_.sppa$r_fill_3_.sppa$r_fill_func_class.sppa$b_revision^#define sppa$b_interface sppa$r_fill_2_.sppa$r_fill_3_.sppa$r_fill_func_class.sppa$b_interface^#define sppa$b_sub_class sppa$r_fill_2_.sppa$r_fill_3_.sppa$r_fill_func_class.sppa$b_sub_class`#definEPe sppa$b_base_class sppa$r_fill_2_.sppa$r_fill_3_.sppa$r_fill_func_class.sppa$b_base_class"#endif /* #if !defined(__VAXC) */ #define SPPA$M_IM 0x8000#define SPPA$M_CONTROL_RF 0x1#define SPPA$M_CONTROL_FF 0x2#define SPPA$M_CONTROL_RV 0x4#define SPPA$M_CONTROL_CL 0x8#define SPPA$M_CONTROL_CE 0x10#define SPPA$M_CONTROL_HF 0x20##define SPPA$M_STATUS_RC 0x80000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __no FPmember_alignment __quadword#else#pragma __nomember_alignment#endif!typedef struct _sppa_mod_status {#pragma __nomember_alignment __union {N unsigned __int64 sppa$q_mod_info; /* 100 Module Information */ __struct { __struct {N unsigned sppa$v_physical_id : 15; /* Unique Module ID */N unsigned sppa$v_im : 1; /* Implementation-dependent */b unsigned short int sppa$w_functions_present; GP /* Functions present mask; F0 MBO */N char sppa$b_reserved_mod_info_1 [4]; /* Reserved */' } sppa$r_fill_mod_info; } sppa$r_fill_5_; } sppa$r_fill_4_; __union {N unsigned __int64 sppa$q_status_control; /* 108 Status/Control Info */ __struct { __struct {N unsigned sppa$v_control_rf : 1; /* Resets Function */U unsigned sppa$v_control_ff : 1; /* ForwardsHP Firmware Xactions (?) */N unsigned sppa$v_control_rv : 1; /* Reserved */N unsigned sppa$v_control_cl : 1; /* Clear Error Logging */P unsigned sppa$v_control_ce : 1; /* Enable Error Log Clearing */N unsigned sppa$v_control_hf : 1; /* Hard Fail Enable */N unsigned sppa$v_reserved_hdr_2 : 25; /* Reserved */P unsigned sppa$v_status_rc : 1; /* Reset-in-progress if set IP */N unsigned sppa$v_reserved_hdr_3 : 31; /* Reserved */, unsigned sppa$v_fill_8_ : 1;- } sppa$r_fill_status_control; } sppa$r_fill_7_; } sppa$r_fill_6_; } SPPA_MOD_STATUS; #if !defined(__VAXC)6#define sppa$q_mod_info sppa$r_fill_4_.sppa$q_mod_info`#define sppa$v_physical_id sppa$r_fill_4_.sppa$r_fill_5_.sppa$r_fill_mod_info.sppa$v_physical_idN#define sppa$v_im sppa$r_fill_4_.sppa$r_fill_5_.sppa$r_fill_moJPd_info.sppa$v_iml#define sppa$w_functions_present sppa$r_fill_4_.sppa$r_fill_5_.sppa$r_fill_mod_info.sppa$w_functions_presentB#define sppa$q_status_control sppa$r_fill_6_.sppa$q_status_controld#define sppa$v_control_rf sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_rfd#define sppa$v_control_ff sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_ffd#define sppa$v_control_rv sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_rvd#defKPine sppa$v_control_cl sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_cld#define sppa$v_control_ce sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_ced#define sppa$v_control_hf sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_control_hfb#define sppa$v_status_rc sppa$r_fill_6_.sppa$r_fill_7_.sppa$r_fill_status_control.sppa$v_status_rc"#endif /* #if !defined(__VAXC) */  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplusLP) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sppa_sba_map {#pragma __nomember_alignment SPPA_FUNC_HDR sba$r_sba_hdr;N char sba$b_reserved_sba_1 [240]; /* */" SPPA_MOD_STATUS sba$r_sba_mod;N char sba$b_reserved_sba_end [3824]; /* Pad to 4K */ } SPPA_SBA_MAP;'#define SPPA$S_SPPA_SBA_MAP_LENGTH 4096#define IOC$M_RE 0x1 MPN#define IOC$K_TS_4K 0 /* 4K Page Size */N#define IOC$K_TS_8K 1 /* 8K Page Size */N#define IOC$K_TS_16K 2 /* 16K Page Size */N#define IOC$K_TS_64K 3 /* 64K Page Size */$#define IOC$M_CTRL_FLUSH_CACHE 0x400##define IOC$M_CTRL_IOCB_EMPTY 0x800#define IOC$M_FLUSH_CACHE 0x1#define IOC$M_FLUSH_2_CLEAN 0x2##define IOC$M_FLUSH_ALL_CURRENT 0x4#defNPine IOC$M_PR_PLUNGE 0x8#define IOC$M_FIP_SNAP 0x10 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sppa_ioc_map {#pragma __nomember_alignment# unsigned __int64 ioc$q_func_id;N char ioc$b_reserved_ioc_0 [248]; /* */$ unsigned __int64 ioc$q_mod_info;$ char ioc$b_reserved_ioc_1 [248];NOP unsigned __int64 ioc$q_lba_port0_cntrl; /* 200 LBA 0 Port Control */N unsigned __int64 ioc$q_lba_port1_cntrl; /* 208 LBA 1 Port Control */N unsigned __int64 ioc$q_lba_port2_cntrl; /* 210 LBA 2 Port Control */N unsigned __int64 ioc$q_lba_port3_cntrl; /* 218 LBA 3 Port Control */N unsigned __int64 ioc$q_lba_port4_cntrl; /* 220 LBA 4 Port Control */N unsigned __int64 ioc$q_lba_port5_cntrl; /* 228 LBA 5 Port Control */N unsigned __int64 ioc$q PP_lba_port6_cntrl; /* 230 LBA 6 Port Control */N unsigned __int64 ioc$q_lba_port7_cntrl; /* 238 LBA 7 Port Control */$ char ioc$b_reserved_ioc_2 [192]; __union {N unsigned __int64 ioc$q_ibase; /* 300 Base of IOV Space */ __struct { __struct {N unsigned ioc$v_re : 1; /* Enable Mapping on Range */, unsigned ioc$v_fill_21_ : 7;( } ioc$r_fill_ibase_bits; } ioc$r_fi QPll_10_; } ioc$r_fill_9_;N unsigned __int64 ioc$q_imask; /* 308 Mask/Size of IOV Space */ __union {N unsigned __int64 ioc$q_pcom; /* 310 Purge Command */ __struct { __struct {N unsigned ioc$v_size : 5; /* Naturally Aligned Purge Size */7 unsigned ioc$v_pcom_reserved_ioc_1 : 7;Q unsigned ioc$v_purge_addr : 20; /* Address Range to be Purged */' } ioc$r_RPfill_pcom_bits; } ioc$r_fill_12_; } ioc$r_fill_11_; __union {N unsigned __int64 ioc$q_tcnfg; /* 318 IOTLB Configuration */ __struct { __struct {N unsigned ioc$v_ts : 2; /* TLB Page Size Code */, unsigned ioc$v_fill_22_ : 6;( } ioc$r_fill_tcnfg_bits; } ioc$r_fill_14_; } ioc$r_fill_13_; __union {N unsigned __int64 ioc$q_pdir; SP/* 320 Physical Addr of IOTLB */ __struct { __struct {8 unsigned ioc$v_pdir_reserved_ioc_1 : 12;N unsigned ioc$v_pdir_base : 32; /* IOTLB PA bit extent */, unsigned ioc$v_fill_23_ : 4;' } ioc$r_fill_pdir_bits; } ioc$r_fill_16_; } ioc$r_fill_15_;$ char ioc$b_reserved_ioc_3 [216]; __union {N unsigned __int64 ioc$q_flush_ctrl; /* 400 Flush/IKE compatibility */ TP __struct { __struct {> unsigned ioc$v_flush_ctrl_reserved_ioc_1 : 10;Z unsigned ioc$v_ctrl_flush_cache : 1; /* Flush entire cache, then reset */W unsigned ioc$v_ctrl_iocb_empty : 1; /* Set when IOC buffer is empty */, unsigned ioc$v_fill_24_ : 4;- } ioc$r_fill_flush_ctrl_bits; } ioc$r_fill_18_; } ioc$r_fill_17_;# char ioc$b_reserved_ioc_4 [32]; __union {N UP unsigned __int64 ioc$q_flush_command; /* 428 Flush Command */ __struct { __struct {U unsigned ioc$v_flush_cache : 1; /* Flush entire cache, then reset */\ unsigned ioc$v_flush_2_clean : 1; /* Flush dirty cache lines, then reset */e unsigned ioc$v_flush_all_current : 1; /* Flush all read_current lines, then reset */N unsigned ioc$v_pr_plunge : 1; /* Kinky */N VP unsigned ioc$v_fip_snap : 1; /* Snapshot */, unsigned ioc$v_fill_25_ : 3;0 } ioc$r_fill_flush_command_bits; } ioc$r_fill_20_; } ioc$r_fill_19_;# char ioc$b_reserved_ioc_5 [40];N unsigned __int64 ioc$q_cache_fip_snap; /* 458 Fetch-In-Progress Mask */% char ioc$b_reserved_ioc_6 [1520];N unsigned __int64 ioc$q_lba_port8_cntrl; /* A50 LBA 8 Port Control */N unsigned __int64 ioc$q_lba_port9_cntrl; /*WP A58 LBA 9 Port Control */N unsigned __int64 ioc$q_lba_port10_cntrl; /* A60 LBA 10 Port Control */N unsigned __int64 ioc$q_lba_port11_cntrl; /* A68 LBA 11 Port Control */N unsigned __int64 ioc$q_lba_port12_cntrl; /* A70 LBA 12 Port Control */N unsigned __int64 ioc$q_lba_port13_cntrl; /* A78 LBA 13 Port Control */N unsigned __int64 ioc$q_lba_port14_cntrl; /* A80 LBA 14 Port Control */N unsigned __int64 ioc$q_lba_port15_cntrl; /* A88 LBA 15 Port Control XP */N char ioc$b_reserved_ioc_end [1392]; /* Pad to 4K */ } SPPA_IOC_MAP; #if !defined(__VAXC)-#define ioc$q_ibase ioc$r_fill_9_.ioc$q_ibaseL#define ioc$v_re ioc$r_fill_9_.ioc$r_fill_10_.ioc$r_fill_ibase_bits.ioc$v_re,#define ioc$q_pcom ioc$r_fill_11_.ioc$q_pcomP#define ioc$v_size ioc$r_fill_11_.ioc$r_fill_12_.ioc$r_fill_pcom_bits.ioc$v_size\#define ioc$v_purge_addr ioc$r_fill_11_.ioc$r_fill_12_.ioc$r_fill_pcom_bits.ioc$v_purge_addr.#define ioc$q_tcnfg ioYPc$r_fill_13_.ioc$q_tcnfgM#define ioc$v_ts ioc$r_fill_13_.ioc$r_fill_14_.ioc$r_fill_tcnfg_bits.ioc$v_ts,#define ioc$q_pdir ioc$r_fill_15_.ioc$q_pdirZ#define ioc$v_pdir_base ioc$r_fill_15_.ioc$r_fill_16_.ioc$r_fill_pdir_bits.ioc$v_pdir_base8#define ioc$q_flush_ctrl ioc$r_fill_17_.ioc$q_flush_ctrln#define ioc$v_ctrl_flush_cache ioc$r_fill_17_.ioc$r_fill_18_.ioc$r_fill_flush_ctrl_bits.ioc$v_ctrl_flush_cachel#define ioc$v_ctrl_iocb_empty ioc$r_fill_17_.ioc$r_fill_18_.ioc$r_fill_flush_ctrl_bits.ioc$vZP_ctrl_iocb_empty>#define ioc$q_flush_command ioc$r_fill_19_.ioc$q_flush_commandg#define ioc$v_flush_cache ioc$r_fill_19_.ioc$r_fill_20_.ioc$r_fill_flush_command_bits.ioc$v_flush_cachek#define ioc$v_flush_2_clean ioc$r_fill_19_.ioc$r_fill_20_.ioc$r_fill_flush_command_bits.ioc$v_flush_2_cleans#define ioc$v_flush_all_current ioc$r_fill_19_.ioc$r_fill_20_.ioc$r_fill_flush_command_bits.ioc$v_flush_all_currentc#define ioc$v_pr_plunge ioc$r_fill_19_.ioc$r_fill_20_.ioc$r_fill_flush_command_bits.ioc$v_[Ppr_plungea#define ioc$v_fip_snap ioc$r_fill_19_.ioc$r_fill_20_.ioc$r_fill_flush_command_bits.ioc$v_fip_snap"#endif /* #if !defined(__VAXC) */ '#define SPPA$S_SPPA_IOC_MAP_LENGTH 4096#define SPPA$M_ENABLE_ARB 0x1#define SPPA$M_MASK_A 0x2#define SPPA$M_MASK_B 0x4#define SPPA$M_MASK_C 0x8#define SPPA$M_MASK_D 0x10#define SPPA$M_MASK_E 0x20#define SPPA$M_MASK_F 0x40#define SPPA$M_MASK_G 0x80#define SPPA$M_RE 0x1!#define SPPA$M_ERR_CONFIG_CM 0x10 #define SPPA$M_ERR_CONFI\PG_S 0x20!#define SPPA$M_ERR_CONFIG_FS 0x40"#define SPPA$M_ERR_CONFIG_CT 0x400"#define SPPA$M_ERR_CONFIG_IM 0x800##define SPPA$M_ERR_CONFIG_IT 0x1000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sppa_lba_map {#pragma __nomember_alignment! SPPA_FUNC_HDR sppa$r_lba_hdr;$ char sppa$b_reserved_lba_1 [72]; __union {N ]P unsigned __int64 sppa$q_bus_number; /* 058 LBA Bus Number Range */ __struct {N unsigned char sppa$b_lowest; /* Lowest bus number in LBA */N unsigned char sppa$b_highest; /* HIghest bus number in LBA */+ char sppa$b_reserved_lba_2 [6]; } sppa$r_fill_27_; } sppa$r_fill_26_;$ char sppa$b_reserved_lba_3 [32]; __union {N unsigned __int64 sppa$q_arb_mask; /* 080 Arbitration Mask */ ^P__struct {N __struct { /* Enables arbitration on PCI/X */O unsigned sppa$v_enable_arb : 1; /* Disable all requests if 0 */P unsigned sppa$v_mask_a : 1; /* Enable arbitration on device A */P unsigned sppa$v_mask_b : 1; /* Enable arbitration on device B */P unsigned sppa$v_mask_c : 1; /* Enable arbitration on device C */P unsigned sppa$v_mask_d : 1; /* Enable arbitration on device D */P _P unsigned sppa$v_mask_e : 1; /* Enable arbitration on device E */P unsigned sppa$v_mask_f : 1; /* Enable arbitration on device F */P unsigned sppa$v_mask_g : 1; /* Enable arbitration on device G */' } sppa$r_arb_mask_bits; } sppa$r_fill_29_; } sppa$r_fill_28_;N char sppa$b_reserved_lba_4 [120]; /* */# SPPA_MOD_STATUS sppa$r_lba_mod;% char sppa$b_reserved_lba_5 [496]; `P __union {N unsigned __int64 sppa$q_ibase; /* 300 Base of IOV Space */ __struct { __struct {N unsigned sppa$v_re : 1; /* Enable Mapping on Range */- unsigned sppa$v_fill_34_ : 7;) } sppa$r_fill_ibase_bits; } sppa$r_fill_31_; } sppa$r_fill_30_;N unsigned __int64 sppa$q_imask; /* 308 Mask/Size of IOV Space */% char sppa$b_reserved_lba_6 [880]; __union aP {W unsigned __int64 sppa$q_err_config; /* 680 Define handling of various errors */ __struct { __struct {S unsigned sppa$v_err_config_ip_1 : 4; /* Implementation dependent */Z unsigned sppa$v_err_config_cm : 1; /* Config: master abort fatal if set */N unsigned sppa$v_err_config_s : 1; /* Smart bus if set */N unsigned sppa$v_err_config_fs : 1; /* SERR# fatal if set */S unsigned sbPppa$v_err_config_ip_2 : 3; /* Implementation dependent */Z unsigned sppa$v_err_config_ct : 1; /* Config: target abort fatal if set */\ unsigned sppa$v_err_config_im : 1; /* I/O port: master abort fatal if set */\ unsigned sppa$v_err_config_it : 1; /* I/O port: target abort fatal if set */T unsigned sppa$v_err_config_ip_3 : 19; /* Implementation dependent */N unsigned sppa$v_reserved_lba_7 : 32; /* Reserved */) cP } sppa$r_fill_err_config; } sppa$r_fill_33_; } sppa$r_fill_32_;N char sppa$b_reserved_lba_end [2424]; /* Pad to 4K */ } SPPA_LBA_MAP; #if !defined(__VAXC);#define sppa$q_bus_number sppa$r_fill_26_.sppa$q_bus_numberC#define sppa$b_lowest sppa$r_fill_26_.sppa$r_fill_27_.sppa$b_lowestE#define sppa$b_highest sppa$r_fill_26_.sppa$r_fill_27_.sppa$b_highest7#define sppa$q_arb_mask sppa$r_fill_28_.sppa$q_arb_mask`#define sppadP$v_enable_arb sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_enable_arbX#define sppa$v_mask_a sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_aX#define sppa$v_mask_b sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_bX#define sppa$v_mask_c sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_cX#define sppa$v_mask_d sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_dX#define sppa$v_mask_e sppa$r_fill_28_.sppa$r_fill_29_.sppa$reP_arb_mask_bits.sppa$v_mask_eX#define sppa$v_mask_f sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_fX#define sppa$v_mask_g sppa$r_fill_28_.sppa$r_fill_29_.sppa$r_arb_mask_bits.sppa$v_mask_g1#define sppa$q_ibase sppa$r_fill_30_.sppa$q_ibaseR#define sppa$v_re sppa$r_fill_30_.sppa$r_fill_31_.sppa$r_fill_ibase_bits.sppa$v_re;#define sppa$q_err_config sppa$r_fill_32_.sppa$q_err_configl#define sppa$v_err_config_ip_1 sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_cfPonfig_ip_1h#define sppa$v_err_config_cm sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_cmf#define sppa$v_err_config_s sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_sh#define sppa$v_err_config_fs sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_fsl#define sppa$v_err_config_ip_2 sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_ip_2h#define sppa$v_err_config_ct sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_gPfill_err_config.sppa$v_err_config_cth#define sppa$v_err_config_im sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_imh#define sppa$v_err_config_it sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_itl#define sppa$v_err_config_ip_3 sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_err_config_ip_3j#define sppa$v_reserved_lba_7 sppa$r_fill_32_.sppa$r_fill_33_.sppa$r_fill_err_config.sppa$v_reserved_lba_7"#endif /* #if !defined(__VAXC) */ hP'#define SPPA$S_SPPA_LBA_MAP_LENGTH 4096 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SPPADEF_LOADED */ ww0[UM/***************************************************************************/M/** iP **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** jP **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/MkP/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:26 by OpenVMS SDL V3.7 */G/* Source: 21-APR-1993 09:59:36 $1$DGA8345:[LIB_H.SRC]SPPBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SPPBDEF ***lP/#ifndef __SPPBDEF_LOADED#define __SPPBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplusmP extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SPPB - SCA PO nPLLER PROCESS BLOCK */N/* */N/* THIS DATA STRUCTURE DESCRIBES A PROCESS NAME KNOWN */N/* TO THE SCA DIRECTORY POLLER. */N/*- */ #define SPPB$K_LENGTH 40#define SPPB$C_LENGTH 40#define SPPB$S_SPPBDEF 40 typedef struct _sppb {N structoP _sppb *sppb$l_flink; /*FWD LINK */N struct _sppb *sppb$l_blink; /*BCK LINK */N unsigned short int sppb$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char sppb$b_type; /*SCS STRUCTURE TYPE */N unsigned char sppb$b_subtyp; /*SCS STRUCTURE SUBTYPE FOR SPPB */N unsigned char sppb$b_procnam [16]; /*ASCII STRING FOR PROCESS NAME */N int (*sppb$l_rtn)(); pP /*ADDRESS OF NOTIFICATION ROUTINE */N unsigned int sppb$l_ctx; /*CONTEXT FOR NOTIFICATION ROUTINE */N unsigned short int sppb$w_bit; /*BIT ASSIGNED TO THIS PROCESS NAME */N unsigned short int sppb$w_unused_1; /*WORD RESERVED FOR EXPANSION */ } SPPB; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined requqPired ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SPPBDEF_LOADED */ ww@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated ORrP disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone withosPut **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by Open tPVMS SDL V3.7 */F/* Source: 22-APR-1993 14:06:57 $1$DGA8345:[LIB_H.SRC]SQEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SQEDEF ***/#ifndef __SQEDEF_LOADED#define __SQEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever puPtr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variantvP_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* Serialisation Queue Element Definitions */N/* */N/* SQEs are put on the extent/FID cache serialisation queues within */N/* the XQP. wP */N/* */N/*- */N#define SQE$K_ACB 16 /*OFFSET INTO ACB AREA */#define SQE$C_ACB 16N#define SQE$K_LENGTH 44 /* LENGTH OF BLOCK */N#define SQE$C_LENGTH 44 /* LENGTH OF BLOCK */#define SQE$S_SQEDEF 44 typedexPf struct _sqe {N struct _sqe *sqe$l_sqeqfl; /*SQE QUEUE FORWARD LINK */N struct _sqe *sqe$l_sqeqbl; /*SQE QUEUE BACKWARD LINK */N unsigned short int sqe$w_sqesize; /*STRUCTURE SIZE IN BYTES */N unsigned char sqe$b_sqetype; /*STRUCTURE TYPE CODE */N unsigned char sqe$b_sqesubtype; /*STRUCTURE SUBTYPE CODE */N unsigned int sqe$l_sqepid; /*PID OWNER OF SQE */N/*DONT AyPDD ANYTHING HERE - ACB IS QUAD ALIGNED */N void *sqe$l_astqfl; /*AST QUEUE FORWARD LINK */N void *sqe$l_astqbl; /*AST QUEUE BACKWARD LINK */N unsigned short int sqe$w_size; /*STRUCTURE SIZE IN BYTES */N unsigned char sqe$b_type; /*STRUCTURE TYPE CODE */N unsigned char sqe$b_rmod; /*REQUEST ACCESS MODE */N unsigned int sqe$l_pid; zP /*PROCESS ID OF REQUEST */N int (*sqe$l_ast)(); /*AST ROUTINE ADDRESS */N unsigned int sqe$l_astprm; /*AST PARAMETER */O unsigned int sqe$l_kast; /*INTERNAL KERNEL MODE XFER ADDRESS */ } SQE; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined re{Pquired ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SQEDEF_LOADED */ ww`U[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR|P disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone witho}Put **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by Open ~PVMS SDL V3.7 */I/* Source: 25-MAY-1993 10:12:21 $1$DGA8345:[LIB_H.SRC]SRVBUFDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SRVBUFDEF ***/#ifndef __SRVBUFDEF_LOADED#define __SRVBUFDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* DefinePd whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __stPruct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SRVBUF Definitions -- MSCP Server local buffer */N/* */J/* This module defines the fields used in the data structure */I/* that keeps track of tPhe local buffer pool. This local pool */I/* is used for buffering data between the client host and the */I/* local disk driver. The size field is stored after the type */I/* and subtype fields so that it can be larger and still retain */I/* the type and subtype convention. */N/*- */ N#define SRVBUF$S_SRVBUFDEF 24 /* Old size name - synonym P */ typedef struct _srvbuf {N void *srvbuf$l_flink; /* Field maintained for */N void *srvbuf$l_blink; /* compatability */Z unsigned short int srvbuf$w_debits; /* Number of requestors memory has been lent to */N unsigned char srvbuf$b_type; /* MSCP type structure */N unsigned char srvbuf$b_subtype; /* with a SRVBUF subtype (4) */N unsigned int srvbuf$l_size; /* Total bPuffer area size */N void *srvbuf$l_buff_start; /* List head for buffer free list */N unsigned int srvbuf$l_free_size; /* Buffer size for free list */ } SRVBUF; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif P /* __SRVBUFDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. P **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **P/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */F/* Source: 22-APR-1993 14:15:46 $1$DGA8345:[LIB_H.SRC]SSCDEF.SDL; P1 *//********************************************************************************************************************************//*** MODULE $SSCDEF ***/#ifndef __SSCDEF_LOADED#define __SSCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previouPsly-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union unio Pn#else#define __union variant_union#endif#endif N/*++ */I/* SSC definitions */N/*-- */N/* The BASE register is at physical address %X2014000. It is loaded with */N/* a value at which to locate all the other registers. All other registers */N/* are at @BASE+offset. P */N#define SSC$AL_BASE 538181632 /*Base address */N#define SSC$L_CONFIG 16 /*Configuration */N#define SSC$L_TODR 108 /*Time-of-year */N#define SSC$L_TCR0 256 /*Timer 0 control */N#define SSC$L_TIR0 260 /*Timer 0 interval */N#define SSC$L_TNIR0 264 /*Timer 0 next interval P */N#define SSC$L_TIVR0 268 /*Timer 0 interrupt vector */N#define SSC$L_TCR1 272 /*Timer 1 control */N#define SSC$L_TIR1 276 /*Timer 1 interval */N#define SSC$L_TNIR1 264 /*Timer 1 next interval */N#define SSC$L_TIVR1 268 /*Timer 1 interrupt vector */N#define SSC$B_RAM_START 1024 /*Start of SSC RAM */N#define SSC$B_RAM_PEND 2047 /*End of SSC RAM */#define SSC$M_TCR_RUN 0x1#define SSC$M_TCR_STP 0x4#define SSC$M_TCR_XFR 0x10#define SSC$M_TCR_SGL 0x20#define SSC$M_TCR_IE 0x40#define SSC$M_TCR_INT 0x80 #define SSC$M_TCR_ERR 0x80000000 typedef struct _tcr { unsigned ssc$v_tcr_run : 1;! unsigned ssc$v_tcr_mbz_0 : 1; unsigned ssc$v_tcr_stp : 1;! unsigned ssc$v_tcr_mbz_1 : 1; unsigned ssc$v_tcr_xfr : 1; unsigned ssc$v_tcr_sgl : 1; unPsigned ssc$v_tcr_ie : 1; unsigned ssc$v_tcr_int : 1;" unsigned ssc$v_tcr_mbz_2 : 23; unsigned ssc$v_tcr_err : 1; } TCR; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SSCDEF_LOADED */ ww[UM/***********P****************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard EPnterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. P **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */G/* Source: 23-APR-1993 14:41:38 $1$DGA8345:[LIB_H.SRC]SSCTDEF.SDL;1 *//*********************************************************** P*********************************************************************//*** MODULE $SSCTDEF ***/#ifndef __SSCTDEF_LOADED#define __SSCTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_sizPe __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N P/*+ */P/* This file contains offset definitions for SSC timer registers accessible */N/* through XMI private space on the XMI-based processors. */N/*- */#define SSCT_TCR0$M_RUN 0x1#define SSCT_TCR0$M_STP 0x4#define SSCT_TCR0$M_XFR 0x10#define SSCT_TCR0$M_SGL 0x20#define SSCT_TCR0$M_IE 0x40#define SSCT_TCR0$M_INT 0x80"#defPine SSCT_TCR0$M_ERR 0x80000000!#define SSCT_TIVR0$M_VECTOR 0x3FC#define SSCT_TCR1$M_RUN 0x1#define SSCT_TCR1$M_STP 0x4#define SSCT_TCR1$M_XFR 0x10#define SSCT_TCR1$M_SGL 0x20#define SSCT_TCR1$M_IE 0x40#define SSCT_TCR1$M_INT 0x80"#define SSCT_TCR1$M_ERR 0x80000000!#define SSCT_TIVR1$M_VECTOR 0x3FC#define SSCT$S_SSCTDEF 32 typedef struct _ssct {N __union { /* Timer Control Register 0 */! unsigned int ssct$l_tcr0; __stru Pct {N unsigned ssct_tcr0$v_run : 1; /* Enables timer */- unsigned ssct_tcr0$v_fill_27 : 1;N unsigned ssct_tcr0$v_stp : 1; /* Stop on overflow */- unsigned ssct_tcr0$v_fill_28 : 1;N unsigned ssct_tcr0$v_xfr : 1; /* 1=copy TNIRn to TIRn */N unsigned ssct_tcr0$v_sgl : 1; /* Increment counter by one */N unsigned ssct_tcr0$v_ie : 1; /* Interrupt Enable */N P unsigned ssct_tcr0$v_int : 1; /* Set on timer overflow *// unsigned ssct_tcr0$v_fill_28a : 23;N unsigned ssct_tcr0$v_err : 1; /* Indicates missed overflow */! } ssct$r_tcr0_fields; } ssct$r_tcr0_overlay;N unsigned int ssct$l_tir0; /* Timer Interval Register 0 */N unsigned int ssct$l_tnir0; /* Timer Next Interval Reg. 0 */N __union { /* Timer Interval Vector Reg. P0 */" unsigned int ssct$l_tivr0; __struct {. unsigned ssct_tivr0$v_fill_29 : 2;O unsigned ssct_tivr0$v_vector : 8; /* Longword aligned SCB vector */. unsigned ssct_tivr0$v_fill_0_ : 6;" } ssct$r_tivr0_fields; } ssct$r_tivr0_overlay;N __union { /* Timer Control Register 1 */! unsigned int ssct$l_tcr1; __struct {N unsigned ssct_tcr1$v_run : 1; /* EnablesP timer */- unsigned ssct_tcr1$v_fill_27 : 1;N unsigned ssct_tcr1$v_stp : 1; /* Stop on overflow */- unsigned ssct_tcr1$v_fill_28 : 1;N unsigned ssct_tcr1$v_xfr : 1; /* 1=copy TNIRn to TIRn */N unsigned ssct_tcr1$v_sgl : 1; /* Increment counter by one */N unsigned ssct_tcr1$v_ie : 1; /* Interrupt Enable */N unsigned ssct_tcr1$v_int : 1; /* Set on timer over Pflow *// unsigned ssct_tcr1$v_fill_28a : 23;N unsigned ssct_tcr1$v_err : 1; /* Indicates missed overflow */! } ssct$r_tcr1_fields; } ssct$r_tcr1_overlay;N unsigned int ssct$l_tir1; /* Timer Interval Register 1 */N unsigned int ssct$l_tnir1; /* Timer Next Interval Reg. 1 */N __union { /* Timer Interval Vector Reg. 1 */" unsigned int ssct$l_tivr1; __stru Pct {. unsigned ssct_tivr1$v_fill_30 : 2;O unsigned ssct_tivr1$v_vector : 8; /* Longword aligned SCB vector */. unsigned ssct_tivr1$v_fill_1_ : 6;" } ssct$r_tivr1_fields; } ssct$r_tivr1_overlay; } SSCT; #if !defined(__VAXC)3#define ssct$l_tcr0 ssct$r_tcr0_overlay.ssct$l_tcr0N#define ssct_tcr0$v_run ssct$r_tcr0_overlay.ssct$r_tcr0_fields.ssct_tcr0$v_runN#define ssct_tcr0$v_stp ssct$r_tcr0_overlay.ssct$r_tcr0_fields.ssct_tcr0$v_sPtpN#define ssct_tcr0$v_xfr ssct$r_tcr0_overlay.ssct$r_tcr0_fields.ssct_tcr0$v_xfrN#define ssct_tcr0$v_sgl ssct$r_tcr0_overlay.ssct$r_tcr0_fields.ssct_tcr0$v_sglL#define ssct_tcr0$v_ie ssct$r_tcr0_overlay.ssct$r_tcr0_fields.ssct_tcr0$v_ieN#define ssct_tcr0$v_int ssct$r_tcr0_overlay.ssct$r_tcr0_fields.ssct_tcr0$v_intN#define ssct_tcr0$v_err ssct$r_tcr0_overlay.ssct$r_tcr0_fields.ssct_tcr0$v_err6#define ssct$l_tivr0 ssct$r_tivr0_overlay.ssct$l_tivr0X#define ssct_tivr0$v_vector ssct$r_tivr0_overlayP.ssct$r_tivr0_fields.ssct_tivr0$v_vector3#define ssct$l_tcr1 ssct$r_tcr1_overlay.ssct$l_tcr1N#define ssct_tcr1$v_run ssct$r_tcr1_overlay.ssct$r_tcr1_fields.ssct_tcr1$v_runN#define ssct_tcr1$v_stp ssct$r_tcr1_overlay.ssct$r_tcr1_fields.ssct_tcr1$v_stpN#define ssct_tcr1$v_xfr ssct$r_tcr1_overlay.ssct$r_tcr1_fields.ssct_tcr1$v_xfrN#define ssct_tcr1$v_sgl ssct$r_tcr1_overlay.ssct$r_tcr1_fields.ssct_tcr1$v_sglL#define ssct_tcr1$v_ie ssct$r_tcr1_overlay.ssct$r_tcr1_fields.ssct_tcr1$v_ieN#define ssct P_tcr1$v_int ssct$r_tcr1_overlay.ssct$r_tcr1_fields.ssct_tcr1$v_intN#define ssct_tcr1$v_err ssct$r_tcr1_overlay.ssct$r_tcr1_fields.ssct_tcr1$v_err6#define ssct$l_tivr1 ssct$r_tivr1_overlay.ssct$l_tivr1X#define ssct_tivr1$v_vector ssct$r_tivr1_overlay.ssct$r_tivr1_fields.ssct_tivr1$v_vector"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /*P Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SSCTDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** Pauthorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, dupPlicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* C Preated: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */G/* Source: 05-MAR-2003 17:04:52 $1$DGA8345:[LIB_H.SRC]VECTORS.SDL;1 *//********************************************************************************************************************************//*** MODULE SSDESCRDEF ***/#ifndef __SSDESCRDEF_LOADED#define __SSDESCRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdPef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define P__struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define EXIT_K_NORMAL_EXIT 0 /* Default exit code */N#define EXIT_K_RMS_STALL 1 /* RMS wait for I/O completion */N#define EXIT_K_RMS_WAIT 2 /* RMS $WAIT eit code */V#define EXIT_K_ASSIGN_EXIT 3 /* Special exit code f Por $ASSIGN to perform */N/* assign to network object in caller's mode. */#define SSDESCR_M_CLASS_0 0x1#define SSDESCR_M_CLASS_1 0x2#define SSDESCR_M_CLASS_2 0x4#define SSDESCR_M_CLASS_3 0x8#define SSDESCR_M_CLASS_4 0x10#define SSDESCR_M_CLASS_5 0x20#define SSDESCR_M_CLASS_6 0x40#define SSDESCR_M_CLASS_7 0x80N#define MODE_K_KERNEL 0 /* Service executes in KERNEL mode */P#define MODE_K_EXEC 1 /* Service executes in EPXECUTIVE mode */Q#define MODE_K_SUPER 2 /* Service executes in SUPERVISOR mode */N#define MODE_K_USER 3 /* Service executes in USER mode */X#define MODE_K_CALLERS_MODE 4 /* Service executes in the mode of the caller */N#define TYPE_K_NORMAL 0 /* No composite type, default value */N#define TYPE_K_QIOW 1 /* Composite type QIOW */N#define TYPE_K_ENQW 2 /* Composite type ENQW P */N#define TYPE_K_GETDVIW 3 /* Composite type GETDVIW */N#define TYPE_K_GETJPIW 4 /* Composite type GETJPIW */N#define TYPE_K_GETSYIW 5 /* Composite type GETSYIW */N#define TYPE_K_SNDJBCW 6 /* Composite type SNDJBCW */N#define TYPE_K_GETLKIW 7 /* Composite type GETLKIW */N#define TYPE_K_BRKTHRUW 8 /* Composite type BRKTHRUW */N#define TYPE_K_GETQUPIW 9 /* Composite type GETQUIW */N#define TYPE_K_END_RU 10 /* Composite type END_RU */N#define TYPE_K_START_TRANSW 11 /* Composite type START_TRANS */N#define TYPE_K_END_TRANSW 12 /* Composite type END_TRANS */N#define TYPE_K_ABORT_TRANSW 13 /* Composite type ABORT_TRANS */N#define TYPE_K_DECLARE_RMW 14 /* Composite type DECLARE_RM */N#define TYPE_K_FORGET_RMW 15 /* ComPposite type FORGET_RM */N#define TYPE_K_JOIN_RMW 16 /* Composite type JOIN_RM */N#define TYPE_K_FINISH_RMOPW 17 /* Composite type FINISH_RMOP */N#define TYPE_K_ADD_BRANCHW 18 /* Composite type ADD_BRANCH */N#define TYPE_K_START_BRANCHW 19 /* Composite type START_BRANCH */N#define TYPE_K_IPCW 20 /* Composite type IPCW */N#define TYPE_K_END_BRANCHW 21 /* Composite type END_BRANCHW P */N#define TYPE_K_AUDIT_EVENTW 22 /* Composite type AUDIT_EVENTW */N#define TYPE_K_CHECK_PRIVILEGEW 23 /* Composite type CHECK_PRIVILEGE */N#define TYPE_K_MAXIMUM 24 /* Maximum number of types */H#define SSFLAG_K_WCM 1 /* May return WCM */N#define SSFLAG_K_WCM_NO_REEXEC 2 /* Don't reexecute */N#define SSFLAG_K_CLRREG 4 /* Clear scratch regs */N#define SSFLAG_K_RETURN_PANY 8 /* May return any val */N#define SSFLAG_K_WCM_NO_SAVE 16 /* Don't save regs */N#define SSFLAG_K_STACK_ARGS 32 /* pointer->stack args */N#define SSFLAG_K_THREAD_SAFE 64 /* no inner-mode synchronization */R#define SSFLAG_K_64_BIT_ARGS 128 /* No sign-extension checking necessary */N#define SSFLAG_K_CHECK_UPCALL 256 /* Inner mode semaphore waits can */N/* potentially be done by thread manager P */]#define SSFLAG_K_EXCLUSIVE 512 /* service requires exclusive access to inner mode */a#define SSFLAG_K_TOLERANT 1024 /* thread-safe service which blocks exclusive services */N#define SSFLAG_K_IMSEM_RELEASE 2048 /* must release semaphore */N#define SSFLAG_K_RESET_ASTEN 4096 /* dispatcher must reenable ASTs */N#define SSFLAG_K_NOPCB 8192 /* no pcb in R4 */ c#if !defined(__NOBASEALIGN_SUPPO PRT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _ssdescr {#pragma __nomember_alignmentN void *ssdescr_a_vector_address; /* Address of vector in S0 space */R void *ssdescr_a_entry_address; /* Self-relative pointer to .ENTRY mask */N unsigned char ssdescr_b_synch_type; /* Composite service type */N unsigned char ssdescr_b_flags; /* Fla Pgs byte, see FLAGS32 */ __union {O unsigned char ssdescr_b_inhibit_mask; /* System service inhibit mask */ __struct {+ unsigned ssdescr_v_class_0 : 1;+ unsigned ssdescr_v_class_1 : 1;+ unsigned ssdescr_v_class_2 : 1;+ unsigned ssdescr_v_class_3 : 1;+ unsigned ssdescr_v_class_4 : 1;+ unsigned ssdescr_v_class_5 : 1;+ unsigned ssdescr_v_class_6 : 1;+ unsigned ssdescr_v P_class_7 : 1; } ssdescr_r_fill_1_; } ssdescr_r_fill_0_;S unsigned char ssdescr_b_mode; /* Access mode in which service executes */N unsigned int ssdescr_l_flags32; /* Longword to allow for 32 flags */N/* copy of FLAGS byte plus */N/* additional bits greater than 8 */N/* */N/* ********* NOTE WEPLL ********* */N/* */N/* The following masks must EXACTLY EQUAL the PLV masks defined in */P/* [LIB]PLVDEF.SDL. The system service dispatcher assumes, for example, that */P/* PLV$M_WAIT_CALLERS_MODE equals SSFLAG_K_WCM. Ensure that any additions to */N/* the SSFLAG flags are reflected in [LIB]VECTORS.SDL (and vice versa). */N/* P */P/* Also note that although PLVFLG is defined to be a quadword, the dispatcher */N/* treats the array of kernel flags and exec flags as an array of LONGWORD */N/* flags. */N/* */N/* ********* END NOTE WELL ********* */N/* P */ } SSDESCR; #if !defined(__VAXC)G#define ssdescr_b_inhibit_mask ssdescr_r_fill_0_.ssdescr_b_inhibit_maskO#define ssdescr_v_class_0 ssdescr_r_fill_0_.ssdescr_r_fill_1_.ssdescr_v_class_0O#define ssdescr_v_class_1 ssdescr_r_fill_0_.ssdescr_r_fill_1_.ssdescr_v_class_1O#define ssdescr_v_class_2 ssdescr_r_fill_0_.ssdescr_r_fill_1_.ssdescr_v_class_2O#define ssdescr_v_class_3 ssdescr_r_fill_0_.ssdescr_r_fill_1_.ssdescr_v_class_3O#define ssdescr_v_class_4 ssdescr_r_fill_0_.ssde Pscr_r_fill_1_.ssdescr_v_class_4O#define ssdescr_v_class_5 ssdescr_r_fill_0_.ssdescr_r_fill_1_.ssdescr_v_class_5O#define ssdescr_v_class_6 ssdescr_r_fill_0_.ssdescr_r_fill_1_.ssdescr_v_class_6O#define ssdescr_v_class_7 ssdescr_r_fill_0_.ssdescr_r_fill_1_.ssdescr_v_class_7"#endif /* #if !defined(__VAXC) */ N#define SSDESCR_K_LENGTH 16 /* Size of list element */N#define SSDESCR_S_SSDESCRDEF 16 /* Old size name - synonym */ N#define FASTSS$K_CLRAS PT 1 /* CLRAST change mode code */N#define FASTSS$K_WTAMI 2 /* WTAMI change mode code */N#define FASTSS$K_UNWIND_CLRAST 3 /* UNWIND_CLRAST change mode code */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard P #endif /* __SSDESCRDEF_LOADED */ wwf[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. P **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. P **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */F/* Source: 21-AUG-2017 05:33:04 $1$DGA8345:[LIB_H.SRC P]SSDISP.SDL;1 *//********************************************************************************************************************************//*** MODULE SSDISP ***/#ifndef __SSDISP_LOADED#define __SSDISP_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* SaveP the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define P__union union#else#define __union variant_union#endif#endif  c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ssdisp {#pragma __nomember_alignmentN unsigned __int64 ssd$q_procedure; /* Pointer to the actual procedure */N unsigned int ssd$l_flags; /* System Service flags */S unsigned char ssPd$b_mode; /* Execution mode for the system service */ char ssd$b_filler [3]; } SSDISP; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SSDISP_LOADED */ ww[UM/*******************************************P********************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP P **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** P **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:27 by OpenVMS SDL V3.7 */F/* Source: 01-AUG-2005 15:38:17 $1$DGA8345:[LIB_H.SRC]SSIDEF.SDL;1 *//********************************************************************************************* P***********************************//*** MODULE $SSIDEF ***/#ifndef __SSIDEF_LOADED#define __SSIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size defaPult to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* P */N/* System Service Intercept Control Block Definitions */N/* */ $#define SSID$M_DOUBLE_MAP_FAILED 0x1!#define SSID$M_PROMOTE_COPIED 0x2 Ntypedef struct _ssi_data { /* Definitions for flags in */N/* CTL$GQ_SSI_DATA */ __union { __int64 ssid$q_bits; __stru Pct {N unsigned ssid$v_double_map_failed : 1; /* Attempt to doublemap */N/* S2 promote area failed */P unsigned ssid$v_promote_copied : 1; /* Process has a private copy */N/* of the promote area */( unsigned ssid$v_fill_2_ : 6; } ssid$r_fill_1_; } ssid$r_fill_0_; } SSI_DATA; #if !defined(__VAXC)W#define ssid$v_double_map_fail Ped ssid$r_fill_0_.ssid$r_fill_1_.ssid$v_double_map_failedQ#define ssid$v_promote_copied ssid$r_fill_0_.ssid$r_fill_1_.ssid$v_promote_copied"#endif /* #if !defined(__VAXC) */  #define SSI$M_CLOSEST 0x1N#define SSI$C_LENGTH 28 /* Length of SSI_BLOCK */ typedef struct _ssi_block { __union {N struct _ssi_block *ssi$ps_flink; /* Forward link */Y struct _ssi_block *ssi$ps_pre_next; /* Pointer to next pre-processing ro Putine */ } ssi$r_flink_overlay; __union {N struct _ssi_block *ssi$ps_blink; /* Backward link */Z struct _ssi_block *ssi$ps_post_next; /* Pointer to next post-processing routine */ } ssi$r_blink_overlay;N unsigned short int ssi$w_size; /* Size, in bytes */O unsigned char ssi$b_type; /* Structure type code for SSI_BLOCK */N unsigned char ssi$b_subtype; /* Structure subtype code */N P unsigned int ssi$l_version; /* Version number */ __union {N unsigned int ssi$l_flags; /* Flags longword */ __struct {N unsigned ssi$v_closest : 1; /* Closest to system service */' unsigned ssi$v_fill_5_ : 7; } ssi$r_fill_4_; } ssi$r_fill_3_;O void (*ssi$ps_pre_routine)(); /* Address of pre-processing routine */P void (*ssi$ps_post_routine)(); /* AddrePss of post-processing routine */ } SSI_BLOCK; #if !defined(__VAXC)5#define ssi$ps_flink ssi$r_flink_overlay.ssi$ps_flink;#define ssi$ps_pre_next ssi$r_flink_overlay.ssi$ps_pre_next5#define ssi$ps_blink ssi$r_blink_overlay.ssi$ps_blink=#define ssi$ps_post_next ssi$r_blink_overlay.ssi$ps_post_next-#define ssi$l_flags ssi$r_fill_3_.ssi$l_flags?#define ssi$v_closest ssi$r_fill_3_.ssi$r_fill_4_.ssi$v_closest"#endif /* #if !defined(__VAXC) */  N/* P */N/* Definition for System Service Intercept Specific Service Control Block */N/* */ #define SSISP$M_NOT_AVAIL 0x1N#define SSISP$C_LENGTH 48 /* Length of SSI_SPEC_BLOCK */ typedef struct _ssi_spec_block {N struct _ssi_block *ssisp$ps_pre_next; /* Forward link */N int ssisp$l_pre_proc_count; /* Number of SSIs on lisPt */N struct _ssi_block *ssisp$ps_post_next; /* Forward link */N int ssisp$l_post_proc_count; /* Number of SSIs on list */Q unsigned int ssisp$o_original_bundle [4]; /* On I64, orig. bundle contents */N/* before replacement */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit poi Pnters */N int (*ssisp$pq_replacement)(); /* On I64, code entry of */#else' unsigned __int64 ssisp$pq_replacement;#endifN/* replacement routine */ __union {N unsigned int ssisp$l_flags; /* Service-specific flags longword */ __struct {Q unsigned ssisp$v_not_avail : 1; /* Service may not be intercepted: */N/* e.g., SYS$SRCHANDLER, etc. P*/) unsigned ssisp$v_fill_8_ : 7; } ssisp$r_fill_7_; } ssisp$r_fill_6_;R int ssisp$l_reserved_1; /* Pad to integral number of quadwords */ } SSI_SPEC_BLOCK; #if !defined(__VAXC)3#define ssisp$l_flags ssisp$r_fill_6_.ssisp$l_flagsK#define ssisp$v_not_avail ssisp$r_fill_6_.ssisp$r_fill_7_.ssisp$v_not_avail"#endif /* #if !defined(__VAXC) */  N/* */N/* Exten Psions to bound procedure descriptors for System Service Intercept */N/* */ typedef struct _ssi_pdsc {N __int64 ssi_pdsc$q_fill_1; /* Quadword which contains flags */S __int64 ssi_pdsc$q_fill_2; /* Quadword which contains entry address */[ __int64 ssi_pdsc$q_fill_3; /* Quadword which contains bound procedure value */ __union {W __int64 ssi_pdsc$q_ss_ssadr; /* Add Press of system service in system space */ __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif* int (*ssi_pdsc$ps_ss_ssadr)();" } ssi_pdsc$r_fill_10_; } ssi_pdsc$r_fill_9_; __union {] __int64 ssi_pdsc$q_replacement_routine; /* Address of replacement routine */ __struct {5 P int (*ssi_pdsc$ps_replacement_routine)();" } ssi_pdsc$r_fill_12_; } ssi_pdsc$r_fill_11_; } SSI_PDSC; #if !defined(__VAXC)B#define ssi_pdsc$q_ss_ssadr ssi_pdsc$r_fill_9_.ssi_pdsc$q_ss_ssadrX#define ssi_pdsc$ps_ss_ssadr ssi_pdsc$r_fill_9_.ssi_pdsc$r_fill_10_.ssi_pdsc$ps_ss_ssadrY#define ssi_pdsc$q_replacement_routine ssi_pdsc$r_fill_11_.ssi_pdsc$q_replacement_routineo#define ssi_pdsc$ps_replacement_routine ssi_pdsc$r_fill_11_.ssi_pdsc$r_fill_12_.ssi_pdsc$ps_repl Pacement_routine"#endif /* #if !defined(__VAXC) */ N/* */N/* Function prototypes */N/* */7#define ssi$get_intercept_main SSI$GET_INTERCEPT_MAIN!int ssi$get_intercept_main(void);5#define ssi$declare_intercept SSI$DECLARE_INTERCEPT  9#ifdef __cplusplus /* Define structure prototPypes */struct _ssi_block; #endif /* #ifdef __cplusplus */ ,int ssi$declare_intercept(__unknown_params);3#define ssi$cancel_intercept SSI$CANCEL_INTERCEPT  9#ifdef __cplusplus /* Define structure prototypes */struct _ssi_block; #endif /* #ifdef __cplusplus */ +int ssi$cancel_intercept(__unknown_params);9#define ssi$declare_replacement SSI$DECLARE_REPLACEMENT .int ssi$declare_replacement(__unknown_params);7#define ssi$cancel_replacement SSI$CANCEL_REPLACEMENPT -int ssi$cancel_replacement(__unknown_params);?#define ssi$declare_spec_intercept SSI$DECLARE_SPEC_INTERCEPT  9#ifdef __cplusplus /* Define structure prototypes */struct _ssi_pdsc;struct _ssi_block; #endif /* #ifdef __cplusplus */ 1int ssi$declare_spec_intercept(__unknown_params);=#define ssi$cancel_spec_intercept SSI$CANCEL_SPEC_INTERCEPT  9#ifdef __cplusplus /* Define structure prototypes */struct _ssi_pdsc;struct _ssi_block; #endif /* #if Pdef __cplusplus */ 0int ssi$cancel_spec_intercept(__unknown_params); N/* */Q/* Define a constant to be placed in the SSI$L_VERSION field of the SSI block. */O/* SYS$SSISHR will verify that the contents of the SSI$L_VERSION field match */Q/* the constant below. If for any reason a change in the SSI interface occurs */R/* (as it did because of the 64-Bit Project) the version number must change, as */P/* must the na Pme of this constant. A change of the symbol name enables users */N/* of SSI to realize at compile-time that SSI has changed. If the value */N/* of the constant changed without an accompanying symbol name change, SSI */P/* cannot determine whether its callers are aware of an SSI interface change. */N/* */%#define SSI$C_VERSION_QUAD_LIST 65536%#define SSI$K_VERSION_QUAD_LIST 65536 $#pragma __member_alignment __resPtoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SSIDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This sofPtware is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is coPnfidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//* P*******************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */H/* Source: 13-DEC-2004 14:55:18 $1$DGA8345:[LIB_H.SRC]SSLOGDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SSLOGDEF ***/#ifndef __SSLOGDEF_LOADED#define __SSLOGDEF_LOADED 1 G#pragma __nostan Pdard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...P#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Log System Service system space pointer Block */N/* P */#define SSLB$M_IOINPROG 0x1#define SSLB$M_UNLOAD 0x2#define SSLB$M_NOARGS 0x4#define SSLB$M_NOFILE 0x8N#define SSLB$K_LENGTH 60 /*Length of SSLB */N#define SSLB$C_LENGTH 60 /*Length of SSLB */  9#ifdef __cplusplus /* Define structure prototypes */struct _ssbuf;struct _fibdef; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN P_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sslb {#pragma __nomember_alignment __union {N unsigned __int64 sslb$q_flags; /*Global logging flags */ __struct {N unsigned sslb$v_ioinprog : 1; /*I/O in progress */N unsigned sslb$v_unload : 1; /*Unload issued */N P unsigned sslb$v_noargs : 1; /*Don't record service arguments */N unsigned sslb$v_nofile : 1; /*Don't write log buffers to file */( unsigned sslb$v_fill_4_ : 4; } sslb$r_fill_1_; } sslb$r_fill_0_;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *sslb$pq_buffers; /*Pointer to buffers */ P#else" unsigned __int64 sslb$pq_buffers;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _ssbuf *sslb$pq_bufhdrs; /*Pointer to SSBUFs */#else" unsigned __int64 sslb$pq_bufhdrs;#endifN unsigned __int64 sslb$q_region_id; /*ID of perm. region */ __union {N unsigned __int64 sslb$q_iosb; /*IOSB f Por logfile extend */ __struct {O unsigned short int sslb$w_iosb_status; /*Status of completed I/O */N unsigned short int sslb$w_iosb_bcnt; /*Bytecount */N unsigned int sslb$l_iosb_pid; /*PID */ } sslb$r_fill_3_; } sslb$r_fill_2_;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size defa Pult to 32-bit pointers */#endifN struct _fibdef *sslb$l_logfib; /*Logfile FIB */N unsigned int sslb$l_curblk; /*Logfile VBN */N unsigned int sslb$l_maxblk; /*Max logfile VBN */N unsigned int sslb$l_channel; /*Log file channel number */N unsigned int sslb$l_status; /*General saved failure status */ char sslb$b_fill_5_ [4]; } SSLB; #if !defined(__VAXC)0P#define sslb$q_flags sslb$r_fill_0_.sslb$q_flagsE#define sslb$v_ioinprog sslb$r_fill_0_.sslb$r_fill_1_.sslb$v_ioinprogA#define sslb$v_unload sslb$r_fill_0_.sslb$r_fill_1_.sslb$v_unloadA#define sslb$v_noargs sslb$r_fill_0_.sslb$r_fill_1_.sslb$v_noargsA#define sslb$v_nofile sslb$r_fill_0_.sslb$r_fill_1_.sslb$v_nofile.#define sslb$q_iosb sslb$r_fill_2_.sslb$q_iosbK#define sslb$w_iosb_status sslb$r_fill_2_.sslb$r_fill_3_.sslb$w_iosb_statusG#define sslb$w_iosb_bcnt sslb$r_fill_2_.sslb$r_fill_3_ P.sslb$w_iosb_bcntE#define sslb$l_iosb_pid sslb$r_fill_2_.sslb$r_fill_3_.sslb$l_iosb_pid"#endif /* #if !defined(__VAXC) */ N/* */N/* Log System Service Buffer Header */N/* */#define SSBUF$M_FULL 0x1P#define SSBUF$K_LENGTH 56 /*Length of allocation buffer header */P#define SSBUF$C_LENGTH 56 P /*Length of allocation buffer header */#define SSBUF$S_SSBUFDEF 56 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ssbuf {#pragma __nomember_alignmentO unsigned int ssbuf$l_busy; /*Number of busy messages in buffer */T unsigned int ssbuf$l_msgcnt; /*Number of completed messages in buffer */N P unsigned int ssbuf$l_bufind; /*Buffer number */ __union {N unsigned int ssbuf$l_flags; /*Buffer control flags */ __struct {N unsigned ssbuf$v_full : 1; /*Buffer full and needs to be */N/* written. No more allocs. */* unsigned ssbuf$v_fill_10_ : 7; } ssbuf$r_fill_7_; } ssbuf$r_fill_6_;R#ifdef __INITIAL_POINTER_SIZE /* Defined wh Penever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ssbuf$pq_start_buf; /*Addr beginning of buffer */#else% unsigned __int64 ssbuf$pq_start_buf;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ssbuf$pq_next_entry; /*Addr next avail entry Pin buff */#else& unsigned __int64 ssbuf$pq_next_entry;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ssbuf$pq_end_buf; /*Addr end of buffer */#else# unsigned __int64 ssbuf$pq_end_buf;#endifN unsigned int ssbuf$l_seqnum; /*Sequence num for buff contents */P int ssbuf$l_reserved_1; /*Pa Pd to integral number of quadwords */ __union {N unsigned __int64 ssbuf$q_iosb; /*IOSB for logfile extend */ __struct {N unsigned short int ssbuf$w_status; /*Status of completed I/O */N unsigned short int ssbuf$w_bcnt; /*Bytecount */N unsigned int ssbuf$l_pid; /*PID */ } ssbuf$r_fill_9_; } ssbuf$r_fill_8_; } SSBUF; #if !defined(__VAXC)3#define ss Pbuf$l_flags ssbuf$r_fill_6_.ssbuf$l_flagsA#define ssbuf$v_full ssbuf$r_fill_6_.ssbuf$r_fill_7_.ssbuf$v_full1#define ssbuf$q_iosb ssbuf$r_fill_8_.ssbuf$q_iosbE#define ssbuf$w_status ssbuf$r_fill_8_.ssbuf$r_fill_9_.ssbuf$w_statusA#define ssbuf$w_bcnt ssbuf$r_fill_8_.ssbuf$r_fill_9_.ssbuf$w_bcnt?#define ssbuf$l_pid ssbuf$r_fill_8_.ssbuf$r_fill_9_.ssbuf$l_pid"#endif /* #if !defined(__VAXC) */ N/* */N/* Log System Se Prvice Buffer Entry */N/* */"#define SSLOG$M_ENTRY_COMPLETE 0x1P#define SSLOG$K_STOP_LENGTH 20 /*Length of allocation buffer header */P#define SSLOG$C_STOP_LENGTH 20 /*Length of allocation buffer header */#define SSLOG$K_IMAGE_START 32 #define SSLOG$K_IMGNAM_LENGTH 40#define SSLOG$K_PIMAGE_START 72!#define SSLOG$K_PIMGNAM_LENGTH 40P#define SSLOG$K_START_LENGPTH 112 /*Length of allocation buffer header */P#define SSLOG$C_START_LENGTH 112 /*Length of allocation buffer header */P#define SSLOG$K_LENGTH 144 /*Length of allocation buffer header */P#define SSLOG$C_LENGTH 144 /*Length of allocation buffer header */N#define SSLOG$C_IDH 1 /* Version major ident */N#define SSLOG$C_IDH_IDS 1 /* Version major ident */N#define SSLOG$C_IDL 2 /* V Persion minor ident */N#define SSLOG$C_IDL_IDS 2 /* Version minor ident */N/* associated with ID additions */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sslog {#pragma __nomember_alignmentN unsigned int sslog$l_size; /*Size in bytes of e Pntire entry */N char sslog$b_entry_type; /*Type of entry LOGTYP$C_mumble */ __union {N unsigned char sslog$b_flags; /*Buffer control flags */ __struct {Q unsigned sslog$v_entry_complete : 1; /*Sys. service status written */* unsigned sslog$v_fill_13_ : 7; } sslog$r_fill_12_; } sslog$r_fill_11_;N unsigned char sslog$b_acmode; /*Access mode of service requestor */N unsigned chaPr sslog$b_bufind; /*Log buffer indicator */N unsigned __int64 sslog$q_timestamp; /*EXE$GQ_SYSTIME contents */N unsigned int sslog$l_entry_number; /*Number associated with this entry */ __union {N __struct { /*In a standard log entry */O unsigned int sslog$l_vector_index; /*Symbol vector entry number */$ } sslog$r_vec__overlay1;N __struct { /*In a startup logging ent Pry */N unsigned short int sslog$w_version_idh; /* Version ID */N unsigned short int sslog$w_version_idl; /*Rest of version ID */# } sslog$r_vec_overlay2;N __struct { /*In a prot. shareable image entry */U unsigned int sslog$l_chm_number; /*CHMx number for prot. image service */# } sslog$r_vec_overlay3; } sslog$r_vec_overlay;S unsigned int sslog$l_image_offset; /*Image offset o Pf system service request */N unsigned int sslog$l_status; /*Service completion status */ __union {N __struct { /*In standard or prot. log entry */N char sslog$t_image_name [40]; /*Of system service request ASCIZ */* } sslog$r_image_name_overlay1;N __struct { /*In startup entry */O char sslog$t_username [32]; /*User name of current process ASCIZ */N un Psigned int sslog$l_buffer_count; /*Number of buffers */N unsigned int sslog$l_start_flags; /*SSL startup flags */* } sslog$r_image_name_overlay2;% } sslog$r_image_name_overlay; __union {N __struct { /*In a standard log entry */S char sslog$t_ssname [32]; /*System service name (currently unused) */& } sslog$r_ssname_overlay1;N __struct { /*In a protectPed image log entry */W char sslog$t_prot_image_name [40]; /*Name of protected image containing */& } sslog$r_ssname_overlay2;N/* service ASCIZ */N __struct { /*In a startup entry */N unsigned int sslog$l_epid; /*Current process ID */S unsigned int sslog$l_buffer_size; /*Length in bytes of entire buffer */N char sslog$tP_scsnode [7]; /*Cluster node name ASCIZ */P unsigned char sslog$b_platform; /*SSLOG$C_PLATFORM_ALPHA or _IA64 */N char sslog$t_procname [16]; /*Current process name ASCIZ */& } sslog$r_ssname_overlay3;! } sslog$r_ssname_overlay;V unsigned int sslog$l_arg_offset; /*Byte offset to ARGCOUNT from entry start */N/* allows upward compatibility for fields */N/* added between this and ARGCOUNT P */U unsigned int sslog$l_status_entry_number; /*Number at time status was written */N unsigned int sslog$l_ktid; /*Kernel thread ID */W unsigned int sslog$l_cpuid; /*CPU ID at 1st entry to $LOG_SYSTEM_SERVICE */N unsigned __int64 sslog$q_tid; /*Pthreads ID */T unsigned __int64 sslog$q_argcount; /*Number of quadwords of args that follow */ } SSLOG; #if !defined(__VAXC)4#definPe sslog$b_flags sslog$r_fill_11_.sslog$b_flagsW#define sslog$v_entry_complete sslog$r_fill_11_.sslog$r_fill_12_.sslog$v_entry_complete[#define sslog$l_vector_index sslog$r_vec_overlay.sslog$r_vec__overlay1.sslog$l_vector_indexX#define sslog$w_version_idh sslog$r_vec_overlay.sslog$r_vec_overlay2.sslog$w_version_idhX#define sslog$w_version_idl sslog$r_vec_overlay.sslog$r_vec_overlay2.sslog$w_version_idlV#define sslog$l_chm_number sslog$r_vec_overlay.sslog$r_vec_overlay3.sslog$l_chm_numberd#definPe sslog$t_image_name sslog$r_image_name_overlay.sslog$r_image_name_overlay1.sslog$t_image_name`#define sslog$t_username sslog$r_image_name_overlay.sslog$r_image_name_overlay2.sslog$t_usernameh#define sslog$l_buffer_count sslog$r_image_name_overlay.sslog$r_image_name_overlay2.sslog$l_buffer_countf#define sslog$l_start_flags sslog$r_image_name_overlay.sslog$r_image_name_overlay2.sslog$l_start_flagsT#define sslog$t_ssname sslog$r_ssname_overlay.sslog$r_ssname_overlay1.sslog$t_ssnamef#define sslog$t_Pprot_image_name sslog$r_ssname_overlay.sslog$r_ssname_overlay2.sslog$t_prot_image_nameP#define sslog$l_epid sslog$r_ssname_overlay.sslog$r_ssname_overlay3.sslog$l_epid^#define sslog$l_buffer_size sslog$r_ssname_overlay.sslog$r_ssname_overlay3.sslog$l_buffer_sizeV#define sslog$t_scsnode sslog$r_ssname_overlay.sslog$r_ssname_overlay3.sslog$t_scsnodeX#define sslog$b_platform sslog$r_ssname_overlay.sslog$r_ssname_overlay3.sslog$b_platformX#define sslog$t_procname sslog$r_ssname_overlay.sslog$r_ssnameP_overlay3.sslog$t_procname"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SSLOGDEF_LOADED */ ww0Q[UM/***************************************************************************/M/** P **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** P **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** P **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */G/* Source: 05-MAR-2003 17:04:52 $1$DGA8345:[LIB_H.SRC]VECTORS.SDL;1 *//********************************************************************************************************************************/ P/*** MODULE SSVECDEF ***/#ifndef __SSVECDEF_LOADED#define __SSVECDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endPif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define SSVEC_K_LENGTH 16 /* Size of list element P */N#define SSVEC_S_SSVECDEF 16 /* Old size name - synonym */ typedef struct _ssvec {N void *ssvec_l_touch_stack; /* Touch user's stack */N void *ssvec_l_savesp; /* Save Caller's SP */N unsigned int ssvec_l_lda_code; /* Load CHM code into R0 */N unsigned int ssvec_l_chmx; /* CHMx instruction */ } SSVEC;  $#pragma __member_alignment __restoreR#ifdPef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SSVECDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software isP confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidentiPal **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********* P***********************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */G/* Source: 22-APR-1993 14:17:57 $1$DGA8345:[LIB_H.SRC]STATDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE STATDEF ***/#ifndef __STATDEF_LOADED#define __STATDEF_LOADED 1 G#pragma __nostandard /* ThiPs file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#defQine __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define STAT_M_INPOOL 0x1#define STAT_M_NOIMGHDR 0x2#define STAT_M_OPEN 0x4 #define STAT_M_NOLOAD_SA_APP 0x8!#define STAT_M_OPTIONAL_LOAD 0x10 #define STAT_M_INHIBIT_LOAD 0x20N Q#define STAT_C_SIZE 16 /* Size of statistics block */#define STAT_S_STATDEF 16 typedef struct _stat {N unsigned int stat_l_length; /* Length of ASCII file name */N void *stat_l_name; /* Address of ASCII file name */ __union {N unsigned int stat_l_flags; /* Loading flags for INIT */ __struct {' unsigned stat_v_inpool : 1;) unsigned stat_v_noimghdr : 1;% Q unsigned stat_v_open : 1;Q unsigned stat_v_noload_sa_app : 1; /* Don't load image if SA_APP=1 */N unsigned stat_v_optional_load : 1; /* Image may not be present */N unsigned stat_v_inhibit_load : 1; /* Don't load image if set */( unsigned stat_v_fill_0_ : 2; } stat_r_flag_bits; } stat_r_flags_overlay;N unsigned int stat_l_ldr_flags; /* Flags passed to exec loader */ } STAT; #if !defined(__VAXC)Q6#define stat_l_flags stat_r_flags_overlay.stat_l_flagsI#define stat_v_inpool stat_r_flags_overlay.stat_r_flag_bits.stat_v_inpoolM#define stat_v_noimghdr stat_r_flags_overlay.stat_r_flag_bits.stat_v_noimghdrE#define stat_v_open stat_r_flags_overlay.stat_r_flag_bits.stat_v_openW#define stat_v_noload_sa_app stat_r_flags_overlay.stat_r_flag_bits.stat_v_noload_sa_appW#define stat_v_optional_load stat_r_flags_overlay.stat_r_flag_bits.stat_v_optional_loadU#define stat_v_inhibit_load stat_r_flagsQ_overlay.stat_r_flag_bits.stat_v_inhibit_load"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __STATDEF_LOADED */ wwp[UM/***************************************************************Q************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** Q **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** Q **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */H/* Source: 02-MAY-1991 13:54:27 $1$DGA8345:[LIB_H.SRC]STATEDEF.SDL;1 *//*************************************************************************************************************** Q*****************//*** MODULE $STATEDEF ***/#ifndef __STATEDEF_LOADED#define __STATEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bi Qt pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+  Q */N/* SCHEDULING STATES */N/*- */N/* DEFINITIONS START AT 1 */N#define SCH$C_COLPG 1 /*COLLIDED PAGE WAIT */S#define SCH$C_MWAIT 2 /*MUTEX AND MISCELLANEOUS RESOURCE WAIT */N#define SCH$C_CEF 3 /*COMMON EVENT FLAG WAIT STA QTE */N#define SCH$C_PFW 4 /*PAGE FAULT WAIT */N#define SCH$C_LEF 5 /*LOCAL EVENT FLAG WAIT */V#define SCH$C_LEFO 6 /*LOCAL EVENT FLAG WAIT OUT OF BALANCE SET */N#define SCH$C_HIB 7 /*HIBERNATE WAIT */O#define SCH$C_HIBO 8 /*HIBERNATE WAIT OUT OF BALANCE SET */N#define SCH$C_SUSP 9 /*SUSPENDED */N#def Qine SCH$C_SUSPO 10 /*SUSPENDED OUT OF THE BALANCE SET */N#define SCH$C_FPG 11 /*FREEPAGE WAIT */N#define SCH$C_COM 12 /*COMPUTE, IN BALANCE SET STATE */O#define SCH$C_COMO 13 /*COMPUTE, OUT OF BALANCE SET STATE */N#define SCH$C_CUR 14 /*CURRENT PROCESS STATE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size prag Qmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __STATEDEF_LOADED */ ww;[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by HewlQett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS SoftwQare, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************************** Q*********************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */G/* Source: 22-AUG-2005 16:11:30 $1$DGA8345:[LIB_H.SRC]STDTDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $STDTDEF ***/#ifndef __STDTDEF_LOADED#define __STDTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __memberQ_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endifQ #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* STDT - SCSI Target Descriptor Table */N/* */N/* ThereQ is one STDT per target. The STDT contains the SCSI information */N/* for each SCSI target. STDT's are created during the configuration of */N/* the SCSI bus. */N/* */N/* This structure is read accessable to the class driver and readable and */N/* writeable by the PORT driver. */N/* Q */U/* ***NOTE1:**** New STDT fields must be entered at the end of the data structure. */N/* */N/* ***NOTE2:**** If an INCOMPATIBLE CHANGE is made to this structure bump */B/* the version number of this structure. */N/*- */ N#define STDT$C_VERSION 6 /*COMPATIBLE VERSION Q NUMBER. */(#define STDT$M_DFLG_RENEGOTIATE_SYNC 0x1&#define STDT$M_DFLG_CLASS_REQ_SDTR 0x2%#define STDT$M_DFLG_SUPPRESS_SDTR 0x4N#define STDT$K_SCDT_HASH_SIZE 8 /* Size of SCDT_HASH_TABLE. */N#define STDT$K_SCDT_HASH_BITBASE 0 /* Start bit of hash mask. */N#define STDT$K_SCDT_HASH_BITCNT 3 /* Number of bits in hash mask. */N#define STDT$K_SCDT_HASH_BITMASK 7 /* Bit mask for the hash value. */#define STDT$M_CNF_PENDING 0x1%#define STDTQ$M_CLASS_UNITS_PAUSED 0x2 #define STDT$M_UNTESTED_PRLI 0x4"#define STDT$M_TARGET_RESET_IP 0x8#define STDT$M_PRLO_IND_IP 0x10 #define STDT$M_KEEP_NO_LUNS 0x20#define STDT$C_SPAREQ 10#define STDT$C_SPAREL 20#define STDT$C_SPAREW 40#define STDT$C_SPAREB 80N#define STDT$C_LENGTH 512 /* Length of STDT */  9#ifdef __cplusplus /* Define structure prototypes */ struct _mbd; struct _fccd; struct _tqe; struct _spdt; struct _scdt; struct _fkb; Q struct _kpb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _stdt {#pragma __nomember_alignmentN void *stdt$ps_hash_flink; /*I STDT hash list forward link */N void *stdt$ps_hash_blink; /*I STDT hash list backward link */Z unsigned short int stdt$w_size; /*I StanQdard pool header - data structure size. */Z unsigned char stdt$b_type; /*I Standard pool header - data structure type. */] unsigned char stdt$b_subtype; /*I Standard pool header - data structure subtype. */N/* */B/* Target Specific Information */N/* */N unsigned int stdt$is_target_id; /*I IDQ (bit#) of this SCSI target. */ __union {Q unsigned int stdt$is_scsi_id_num; /*I ID (number) of this SCSI target. */a unsigned __int64 stdt$q_scsi_id_num; /*I ID (number) of SCSI target for wide devices. */! } stdt$r_scsi_id_overlay;N/*I */N/*I */N unsigned int stdt$is_reqack_offset; /*S reqack offset for sync IO Q*/N unsigned int stdt$is_transfer_period; /*S m*4 nanoseconds */N unsigned int stdt$is_xferpd_data; /*S Port transfer period data */R unsigned int stdt$is_fast_data; /*S Port fast SCSI data (port specific) */X unsigned int stdt$is_wide; /*S Flag set enables WIDE data transfer mode. */N unsigned int stdt$is_bus_width; /*S Width of WIDE bus (8, 16, 32). */ __union {N unsigned int stdt$is_dipl_flags; /*S Flags manipulated at DIPL. Q */ __struct {o unsigned stdt$v_dflg_renegotiate_sync : 1; /* Re-negotiate asynchronous/synchronous operation. */] unsigned stdt$v_dflg_class_req_sdtr : 1; /* Class driver has requested SDTR. */] unsigned stdt$v_dflg_suppress_sdtr : 1; /* Class driver is suppressing SDTR. */( unsigned stdt$v_fill_4_ : 5; } stdt$r_fill_1_; } stdt$r_fill_0_;i unsigned int stdt$is_requested_reqack_offset; /*S ack offset reqQuested by class driver for sync IO */m unsigned int stdt$is_requested_xfer_period; /*S transfer period requested by class driver for synch IO */N/* */B/* Performance and sanity counters */N/* */X unsigned int stdt$is_scdt_count; /*F Count of SCDTs associated with this STDT. */` unsigned int stdt$is_dev_io_counQt; /*F Outstanding device queue I/O count for the target */^ unsigned int stdt$is_port_io_count; /*F Outstanding port queue I/O count for the target */Z unsigned int stdt$is_total_io_count; /*F Outstanding total I/O count for the target */N unsigned int stdt$is_reset_cnt; /*S Count of bus resets. */N/* */B/* Hash table for the SCDTs */N/* Q */N/* Number of bits in the hash value. */N/* Starting position of those bits. */N void *stdt$ps_scdt_hash_table [8]; /*F SCDT hash table. */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __int64 stdt$q_identQity; /*F Identity quadword */#pragma __nomember_alignmentN unsigned int stdt$l_status; /*F Target/ID/FC-LA status */R unsigned int stdt$l_hash_index; /*F Hash index of this STDT's root STDT */N/*F in the SPDT's STDT hash table */N/* */R/* PGADRIVER needs more room in the STDT than the stock structure allowed. I've */P/* overlaid Qthe port-specific extension which was already here with PGADRIVER */I/* specific data and created a symbol to define the number of long */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifd __union { /*F Port specific space that may be used for any p !Qurpose. */N/* Save starting port-specific offset */#pragma __nomember_alignment __struct {^ unsigned __int64 stdt$q_suspended_time; /*F Low longword of time when suspended */N/*F High longword of time when suspended */N int stdt$l_prli_status; /*F PRLI status of this FC-LA */N int stdt$l_prli_retries; /*F PRLI retries left */R struct _mbd *s"Qtdt$ps_prli_rsp_mbd; /*F Pointer to PRLI response MBD */N struct _fccd *stdt$ps_prli_fccd; /*F Pointer to PRLI FCCD */R int stdt$l_suspensions; /*F Number of reasons to stay suspended */] int stdt$l_suspended_commands; /*F Number of suspensions due to command status */N int stdt$l_target_resets; /*F Number of Target Resets issued */c struct _tqe *stdt$ps_queue_full_tqe; /*F Pointer to TQE used for QUEUE FULL recovery */ #Q __union {! int stdt$l_flags; __struct {a unsigned stdt$v_cnf_pending : 1; /*F Boolean: pending an ELS confirmation? */f unsigned stdt$v_class_units_paused : 1; /*F Boolean: class driver units paused? */` unsigned stdt$v_untested_prli : 1; /*F Boolean: PRLI issued but untested? */b unsigned stdt$v_target_reset_ip : 1; /*F Boolean: Target Reset in progress? */a $Qunsigned stdt$v_prlo_ind_ip : 1; /*F Boolean: PRLO Indication in progress? */f unsigned stdt$v_keep_no_luns : 1; /*F Boolean: Keep even if LUN count goes to 0 */0 unsigned stdt$v_fill_5_ : 2;% } stdt$r_fill_3_;! } stdt$r_fill_2_;^ char stdt$b_fill [4]; /*F Fill out out to an integral number of quadwords */' } stdt$r_pga_port_specific;N/* Save ending port-specific offset %Q */ __union {N/* Bliss complains about the duplicate definitions of size symbols for */N/* each of the following arrays. Until I can figure out how to work */N/* around that we'll get by with the one symbol which is actually */N/* referenced in checked-in code. There's no way that I know of to */N/* get SDL to skip some of it's input stream for specific languages, */N/* ("iflanguage" doesn't seem to work within an aggregate) &Q */N/* PORT_SPECIFIC byte dimension #PORT_SPECIFIC_BYTES; */N/* PORT_SPECIFIC word dimension #PORT_SPECIFIC_WORDS; */+ int stdt$is_port_specific [12];N/* PORT_SPECIFIC longword dimension #PORT_SPECIFIC_LONGS; */N/* PORT_SPECIFIC quadword dimension #PORT_SPECIFIC_QUADS; */* } stdt$r_port_specific_arrays;' } stdt$r_port_specific_overlay;N/*F End of port specific space that ma'Qy be used for any purpose */N/* */M/* The following fields are reserved to Digital OpenVMS/Alpha development. */L/* They are not normally used in released code, so are available for test */I/* and debug code - however, the developer assumes responsibility for */L/* ensuring that the fields are available to the port driver being worked */I/* on at the time of use *(Q/N/* */N int stdt$is_rsvd_long [5]; /*F Port-independent symbols */O/* These fields are newly defined in Ruby (V7.3-1). Since we don't have */I/* the option of forcing 3rd-party class driver recompiles in a dash */J/* release, they are being added to the tail of the structure; it would */I/* be a good idea to move them to before the port-specific overlays in */I/* the next dot release )Q */N struct _spdt *stdt$ps_spdt; /*F Pointer to this STDT's SPDT */Y struct _scdt *stdt$ps_first_scdt; /*F First SCDT on which to to try to start I/O */W struct _stdt *stdt$ps_stdt_link; /*F Link to next STDT connected to same SPDT */V/* Note that the following fields are not marked with "F" to indicate that they are */V/* synchronized with the fork spinlock - this is because they are synchronized with */Y/* the credit semaphore *Qindependent of spinlock context; however, there is an implicit */N/* assumption that the credit semaphore is acquired & released at fork IPL */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN void *stdt$ps_credit_wqfl; /* First SCDRP on credit wait queue */#pragma __nomember_alignmentN void *stdt$ps_credit_wqbl; /* Last SCDRP on c+Qredit wait queue */S __int64 stdt$q_credit_io_count; /* Number of SCDRPs on credit wait queue */U __int64 stdt$q_drain_to_divisor; /* Divisor used to calculate the number of */N/* active requests to drain to after seeing */N/* a new Queue Full */N unsigned __int64 stdt$q_credit_lock; /* Queue Full field semaphore */W __int64 stdt$q_low_depth_recovery; /* Number of active requests b,Qelow which the */N/* driver will perform a time, rather than load, */N/* based Queue Full recovery */P unsigned __int64 stdt$q_lock_cpu; /* CPU which currently owns semaphore */W __int64 stdt$q_probation; /* Boolean telling whether or not the active */N/* queue depth is currently being tested with a */N/* probationary I/O -Q */Y __int64 stdt$q_credit_limit; /* Maximum number of I/Os which will be issued */N/* without waiting for a request to complete */S __int64 stdt$q_credit_available; /* Number of credits currently available */^ __int64 stdt$q_queue_fulls; /* New (non-latent) Queue Fulls seen on this target */g __union { /*F Target-specific sequence used to order requests on retry */l unsigned int stdt$l_sequence; .Q/*F Longword (but quadword aligned) sequence (treat as read-only) */g unsigned __int64 stdt$q_sequence; /*F Quadword sequence, always the one which is incremented */" } stdt$r_sequence_overlay;N/*F End overlay */_ __int64 stdt$q_fp_dev_io_count; /*P Number of FastPath requests active on the target */h __int64 stdt$q_fp_credits; /*P Number of credits to be freed by the FastPath fork thread */r struct/Q _fkb *stdt$ps_fp_credit_fkb; /*F Pointer to FKB used by successful FastPath requests to free credits */N int stdt$l_illegal_frames; /*F Illegal Frame error counter */N int stdt$l_sequence_timeouts; /*F Sequence Timeout counter */m unsigned int stdt$l_pause_fc_la; /*F Incremented on all calls to pga$pause_fc_la and decremented in */N/*F in pga$resume_fc_la if it is nonzero. If pga$resume_fc_la see */N/*F that it is non-zero, it decrements it and re 0Qsumes the stdt. */N/* Port WWID (X-19) */& unsigned __int64 stdt$q_port_wwid;N/* Node WWID (X-19) */& unsigned __int64 stdt$q_node_wwid;N/* Pointer to initialization WWID_TID (X-19) */# void *stdt$ps_initial_wwid_tid;N/* Pointer to associated WWID_TID (X-19) */ void *stdt$ps_wwid_tid;N/* Poi 1Qnter to the next STDT associated with this STDT's WTID (X-19) */) struct _stdt *stdt$ps_next_wtid_stdt;N/* Number of STDT/WTID configuration failures (X-19) *// unsigned __int64 stdt$q_wtid_stat_fail_cnt;N/* Last STDT/WTID configuration failure status code (X-19) */+ unsigned __int64 stdt$q_last_wtid_stat;N/* Number of times a NULL WTID was detected during IO processing (X-19) */* unsigned __int64 stdt$q_wtid_null_cnt;N/* WWID_ 2QTID allocation failure counter (X-19) */# __int64 stdt$q_wtid_alloc_fail;N/* Pointer to Inquiry Server KPB - FibreChannel only (X-20) */% struct _kpb *stdt$ps_inquiry_kpb;N/* Normal Path IO approved but not yet in-flight (X-20) */ __int64 stdt$q_io_approved;N/* Fast Path IO approved but not yet in-flight (X-20) */" __int64 stdt$q_fp_io_approved;N/* Initial sequence timeout timestamp (X-20) 3Q */) __int64 stdt$q_init_seq_timeout_time;N/* Last sequence timeout timestamp (X-20) */) __int64 stdt$q_last_seq_timeout_time;N/* Sequence timeouts in the monitored sequence timeout window (X-20) */& int stdt$l_seq_timeouts_in_window;N/* Spares fields for future growth (X-20/X-21) */N/* Number of spare quadwords */ char stdt$b_fill_6_ 4Q[4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment, unsigned __int64 stdt$q_spareq [10];( unsigned int stdt$l_sparel [20];. unsigned short int stdt$w_sparew [40];) unsigned char stdt$b_spareb [80]; } stdt$r_rsvd1;N/* 5Q */B/* Define the length of this structure. */N/* */ } STDT; #if !defined(__VAXC)F#define stdt$is_scsi_id_num stdt$r_scsi_id_overlay.stdt$is_scsi_id_numD#define stdt$q_scsi_id_num stdt$r_scsi_id_overlay.stdt$q_scsi_id_num<#define stdt$is_dipl_flags stdt$r_fill_0_.stdt$is_dipl_flags_#define stdt$v_dflg_renegotiate_sync stdt$r_fill_0_.stdt$r_fill_1_.stdt$v_dflg_renegotiate_s6Qync[#define stdt$v_dflg_class_req_sdtr stdt$r_fill_0_.stdt$r_fill_1_.stdt$v_dflg_class_req_sdtrY#define stdt$v_dflg_suppress_sdtr stdt$r_fill_0_.stdt$r_fill_1_.stdt$v_dflg_suppress_sdtrV#define stdt$r_pga_port_specific stdt$r_port_specific_overlay.stdt$r_pga_port_specificL#define stdt$q_suspended_time stdt$r_pga_port_specific.stdt$q_suspended_timeF#define stdt$l_prli_status stdt$r_pga_port_specific.stdt$l_prli_statusH#define stdt$l_prli_retries stdt$r_pga_port_specific.stdt$l_prli_retriesJ#d7Qefine stdt$ps_prli_rsp_mbd stdt$r_pga_port_specific.stdt$ps_prli_rsp_mbdD#define stdt$ps_prli_fccd stdt$r_pga_port_specific.stdt$ps_prli_fccdF#define stdt$l_suspensions stdt$r_pga_port_specific.stdt$l_suspensionsT#define stdt$l_suspended_commands stdt$r_pga_port_specific.stdt$l_suspended_commandsJ#define stdt$l_target_resets stdt$r_pga_port_specific.stdt$l_target_resetsN#define stdt$ps_queue_full_tqe stdt$r_pga_port_specific.stdt$ps_queue_full_tqeI#define stdt$l_flags stdt$r_pga_port_specific.st8Qdt$r_fill_2_.stdt$l_flagsd#define stdt$v_cnf_pending stdt$r_pga_port_specific.stdt$r_fill_2_.stdt$r_fill_3_.stdt$v_cnf_pendingr#define stdt$v_class_units_paused stdt$r_pga_port_specific.stdt$r_fill_2_.stdt$r_fill_3_.stdt$v_class_units_pausedh#define stdt$v_untested_prli stdt$r_pga_port_specific.stdt$r_fill_2_.stdt$r_fill_3_.stdt$v_untested_prlil#define stdt$v_target_reset_ip stdt$r_pga_port_specific.stdt$r_fill_2_.stdt$r_fill_3_.stdt$v_target_reset_ipd#define stdt$v_prlo_ind_ip stdt$r_pga_port_s9Qpecific.stdt$r_fill_2_.stdt$r_fill_3_.stdt$v_prlo_ind_ipf#define stdt$v_keep_no_luns stdt$r_pga_port_specific.stdt$r_fill_2_.stdt$r_fill_3_.stdt$v_keep_no_luns\#define stdt$r_port_specific_arrays stdt$r_port_specific_overlay.stdt$r_port_specific_arraysO#define stdt$is_port_specific stdt$r_port_specific_arrays.stdt$is_port_specific?#define stdt$l_sequence stdt$r_sequence_overlay.stdt$l_sequence?#define stdt$q_sequence stdt$r_sequence_overlay.stdt$q_sequence0#define stdt$q_spareq stdt$r_rsvd1.s:Qtdt$q_spareq0#define stdt$l_sparel stdt$r_rsvd1.stdt$l_sparel0#define stdt$w_sparew stdt$r_rsvd1.stdt$w_sparew0#define stdt$b_spareb stdt$r_rsvd1.stdt$b_spareb"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif / ;Q* __STDTDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. Q *//********************************************************************************************************************************//*** MODULE $SVAPTEDEF ***/#ifndef __SVAPTEDEF_LOADED#define __SVAPTEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the?Q previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __un@Qion union#else#define __union variant_union#endif#endif N/*+ */N/*- */   #include  #include  #include  #include  #include  #include  #include + #define bd$$svapte bd$pq_svapte_sva0 #define cdrp$$cnxsvapte cdrp$pq_cnxsvapte_sva/ #define AQ cdrp$$mysvapte cdrp$pq_mysvapte_sva) #define cdrp$$svapte cdrp$pq_svapte_sva0 #define cdrp$$vcnxsvapte cdrp$pq_vcnxsvapte_sva- #define dcbe$$svapte dcbe$pq_svapte_sva, #define hrb$$svapte hrb$pq_svapte_sva& #define irp$$svapte irp$pq_bufio_pkt) #define vcrp$$svapte vcrp$pq_svapte_sva $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previouBQsly-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SVAPTEDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be uCQsed, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosDQed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-202 EQ4 15:22:29 by OpenVMS SDL V3.7 */G/* Source: 31-MAY-2022 07:49:05 $1$DGA8345:[LIB_H.SRC]SWISDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SWISDEF ***/#ifndef __SWISDEF_LOADED#define __SWISDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE FQ /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#dGQefine __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* DEFINITION OF SWIS Data Structure */N/*- */ #include E#if defined(__ia64) /* Verified for X86 port - Camiel VanderhoHQeven */#include /#define SWIS$A_DATA_ADDRESS 0xE000000000000000L#endif /* __IA64 */  #define SWIS$K_SWISDATA_OFFSET 0#define SWIS$K_IDT_OFFSET 8#define SWIS$K_SISR_OFFSET 16$#define SWIS$K_ASTSR_ASTEN_OFFSET 24#define SWIS$M_HWPCB_MASK 0xFF#define SWIS$M_ASTEN 0xF#define SWIS$M_ASTSR 0xF0#define SWIS$K_IPL_OFFSET 32!#define SWIS$K_PREVMODE_OFFSET 36%#define SWIS$K_CURSTACKMODE_OFFSET 40 #define SWIS$K_CURMODE_OFFSET 44'#define SWIS$K_CUR_FRAME_MODE_OFFSIQET 48"#define SWIS$K_CUR_FRAME_OFFSET 52(#define SWIS$K_INTERRUPT_DEPTH_OFFSET 60#define SWIS$K_KT_ID_OFFSET 64#define SWIS$K_FLAGS_OFFSET 68#define SWIS$M_DISABLE_LOG 0x1#define SWIS$M_INHIBIT_LOG 0x2"#define SWIS$M_ENABLE_REG_TEST 0x4%#define SWIS$M_REG_ERROR_DETECTED 0x8##define SWIS$M_VIRTUAL_MACHINE 0x10(#define SWIS$K_RFLAGS_SET_MASK_OFFSET 72*#define SWIS$K_RFLAGS_CLEAR_MASK_OFFSET 80#define SWIS$K_CPUID_OFFSET 88!#define SWIS$K_HWPCB_VA_OFFSET 96&#define SWIS$K_APIC_BASEJQ_VA_OFFSET 104 #define SWIS$K_PCB_VA_OFFSET 112"#define SWIS$K_ALPHAREG_OFFSET 120#define SWIS$K_CR3_OFFSET 280!#define SWIS$K_SLOT_VA_OFFSET 344"#define SWIS$K_CPUDB_VA_OFFSET 352#define SWIS$K_GDT_OFFSET 368#define SWIS$K_GDT_LIMIT 55#define SWIS$K_TSS_OFFSET 432#define SWIS$K_RSP_OFFSET 432#define SWIS$K_IOMAP_OFFSET 104#define SWIS$K_TSS_LIMIT 107(#define SWIS$K_SCRATCH_HWPCB_OFFSET 1024%#define SWIS$K_XSAVE_SIZE_OFFSET 1536  9#ifdef __cplusplus /* Define stKQructure prototypes */struct _hwpcb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _swis {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void LQ *swis$pq_swisdata; /* VA of this structure */#else# unsigned __int64 swis$pq_swisdata;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *swis$pq_idt; /* Interruption dispatch table */#else unsigned __int64 swis$pq_idt;#endifN unsigned int swis$l_sisr; /* SISR MQ*/N unsigned int swis$l_filler_1; /* Align to quadword */ __union {e unsigned __int64 swis$q_astsr_asten; /* ASTSR and ASTEN (quadword because of previous use) */ __struct { __union {N unsigned swis$v_swis_astsr_asten : 8; /* ASTSR and ASTEN */_ unsigned swis$v_hwpcb_mask : 8; /* To be removed when we get it out of code. */ __struct {N unsigned swis$v_asten : 4; / NQ* AST Enable Register */Q unsigned swis$v_astsr : 4; /* AST Pending Summary Register */' } swis$r_ast_bits0;% } swis$r_ast_overlay;+ } swis$r_swis_astsr_asten_fill;# } swis$r_hwpcb_ast_overlay; unsigned int swis$l_ipl;! unsigned int swis$l_prevmode;% unsigned int swis$l_curstackmode;N unsigned int swis$l_curmode; /* Curent mode */f int swis$l_cur_frame_mode; OQ /* Mode interrupted by current frame, if the emulated Alpha */N/* registers have not been saved yet. Otherwise -1 */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */d void *swis$pq_cur_frame; /* Pointer to currently active interrupt or SSENTRY frame */#else$ unsigned __int64 swis$pq_cur_frame;#endif( unsigned int swis$l_inte PQrrupt_depth; unsigned int swis$l_kt_id; __union { int swis$l_flags; __struct {, unsigned swis$v_disable_log : 1;, unsigned swis$v_inhibit_log : 1;0 unsigned swis$v_enable_reg_test : 1;3 unsigned swis$v_reg_error_detected : 1;i unsigned swis$v_virtual_machine : 1; /*This should get same value as exe$v_virtual_machine */( unsigned swis$v_fill_0_ : 3; } swis$r_bits; } swis$r_flaQQg_union;N unsigned __int64 swis$q_rflags_set_mask; /* RFLAGS set template mask */O unsigned __int64 swis$q_rflags_clear_mask; /* RFLAGS clear template mask */N unsigned __int64 swis$q_cpuid; /* Current CPU Id */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _hwpcb *swis$pq_hwpcb_va; /* pointer to HWPCB */RQ#else# unsigned __int64 swis$pq_hwpcb_va;#endifn unsigned __int64 swis$q_local_apic_base_va; /* Base address of local xAPIC, 0 if x2APIC mode (use MSRs) */N unsigned __int64 swis$q_pcb_va; /* Pointer to PCB */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */` void *swis$pq_alphareg [4]; /* Pointers to emulated Alpha registers fo SQr each mode */#else' unsigned __int64 swis$pq_alphareg [4];#endif) unsigned __int64 swis$q_scratch [16];N unsigned __int64 swis$q_cr3 [4]; /* CR3 values for each mode */e unsigned __int64 swis$q_knv_good_sp; /* Here is where we get an SP to use when we get a KSTINV */_ unsigned __int64 swis$q_knv_trap_type; /* Trap type we entered with when KSTINV detected */N unsigned __int64 swis$q_knv_ksp; /* SP at the time of the KSTINV */N unsigned __int64 swis$TQq_knv_count; /* Count to detect recursive KSTINV */N unsigned __int64 swis$q_slot_va; /* A pointer to the CPU slot */Q unsigned __int64 swis$q_cpudb_va; /* A pointer to the CPUDB for this CPU */N/* pad to next 16 byte boundary */ char swis$t_filler_gdt [8];R unsigned __int64 swis$q_gdt [7]; /* Global Descriptor Table for this CPU */N/* pad to next 16 byte boundary */ char sUQwis$t_filler_tss [8];X/* Here follows the Task State Segment for this CPU. We embed it here, because - like */Y/* the SWIS data structure, it is a per-cpu structure, and it contains one field - the */V/* kernel-mode stack pointer - that was part of the SWIS data structure on Itanium. */N unsigned int swis$l_tss_mbz0; /* Reserved Must Be Zero */Z/* The following overlay bears a little explanation. When an interrupt occurs while the */X/* system is not in kernel mode, the proVQcessor gets the ring 0 stack pointer from the */W/* TSS. There are also slots for the ring 1 and ring 2 stack pointers, which are not */Z/* used by any of the mechanisms we use in VMS. The ring 0, 1, and 2 stack pointers are */T/* followed by a reserved quadword, and is then followed by the 7 interrupt stack */U/* IST1 .. IST7. For VMS, we co-opt the reserved quadword for the user-mode stack */[/* pointer. We use an overlay to present the stack pointers as either KSP, ESP, SSP, and */V/* USP WQ, or as RSP[0..3]. Since arrays are 0-based, we also use the overlay to have */P/* IST[0..7], of which IST[0] should never be used, as it's aliased with USP. */ __union { __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *swis$pq_cur_rsp [4]; /* RSP[mode] */#else& unsigned __int64 swis$pq_cur_rsp [4]; XQ#endifN __int64 swis$q_rsp_fill [7]; /* IST 1 - 7 */ } swis$r_rsp_rsp; __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */a void *swis$pq_cur_ksp; /* KSP stored here when process current, not using KSP */#else" unsigned __int64 swis$pq_cur_ksp;#endifR#ifdef __INITIAL_POINTER_SIZE /* YQDefined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */d void *swis$pq_cur_esp; /* ESP stored here when process current, not in exec mode */#else" unsigned __int64 swis$pq_cur_esp;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */e void *swis$pq_cur_ssp; ZQ /* SSP stored here when process current, not in super mode */#else" unsigned __int64 swis$pq_cur_ssp;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */d void *swis$pq_cur_usp; /* USP stored here when process current, not in user mode */#else" unsigned __int64 swis$pq_cur_usp;#endifN __int64 swis$q_ksp_fill [7]; /* IST 1 - 7 [Q */ } swis$r_rsp_ksp; __struct {N __int64 swis$q_ist_fill [3]; /* RSP 0 - 2 */O unsigned __int64 swis$q_tss_ist [8]; /* Interrupt Stack Pointers */ } swis$r_rsp_ist; } swis$r_rsp_overlay;N unsigned __int64 swis$q_tss_mbz92; /* Reserved Must Be Zero */N unsigned short int swis$w_tss_mbz100; /* Still More MBZ */b unsigned short int swis$w_tss_iomap_ba\Qse; /* I/O map base address The 16-bit offset to the */N/* I/O permission bit map from the 64-bit TSS base. */N unsigned int swis$l_tss_iomap; /* Very short IO map (ask Camiel) */' unsigned __int64 swis$q_next_timer;N unsigned __int64 swis$q_intr_flag; /* Used only by AMOVRR, AMOVRM, RS */N/* pad to next 512 byte boundary */ char swis$t_filler_5 [468];X char swis$iq_scratch_hwpcb [512]; /* Scratch a ]Qrea at least the size of a HWPCB */N/* Note: HWPCB defined in HWRPBDEF.SDL */N unsigned __int64 swis$q_xsave_area_size; /* Size of XSAVE area */' unsigned __int64 swis$q_kstack_top;* unsigned __int64 swis$q_kstack_bottom;' char swis$q_low_level_trace [6632]; } SWIS; #if !defined(__VAXC)F#define swis$q_astsr_asten swis$r_hwpcb_ast_overlay.swis$q_astsr_asten#define swis$v_swis_astsr_asten swis$r_hwpcb_ast_overlay.swis$r_swis^Q_astsr_asten_fill.swis$r_ast_overlay.swis$v_swis_astsr_astent#define swis$v_hwpcb_mask swis$r_hwpcb_ast_overlay.swis$r_swis_astsr_asten_fill.swis$r_ast_overlay.swis$v_hwpcb_mask{#define swis$v_asten swis$r_hwpcb_ast_overlay.swis$r_swis_astsr_asten_fill.swis$r_ast_overlay.swis$r_ast_bits0.swis$v_asten{#define swis$v_astsr swis$r_hwpcb_ast_overlay.swis$r_swis_astsr_asten_fill.swis$r_ast_overlay.swis$r_ast_bits0.swis$v_astsr3#define swis$l_flags swis$r_flag_union.swis$l_flagsK#define swis$v_disab_Qle_log swis$r_flag_union.swis$r_bits.swis$v_disable_logK#define swis$v_inhibit_log swis$r_flag_union.swis$r_bits.swis$v_inhibit_logS#define swis$v_enable_reg_test swis$r_flag_union.swis$r_bits.swis$v_enable_reg_testY#define swis$v_reg_error_detected swis$r_flag_union.swis$r_bits.swis$v_reg_error_detectedS#define swis$v_virtual_machine swis$r_flag_union.swis$r_bits.swis$v_virtual_machineI#define swis$pq_cur_rsp swis$r_rsp_overlay.swis$r_rsp_rsp.swis$pq_cur_rspI#define swis$pq_cur_ksp swis$r `Q_rsp_overlay.swis$r_rsp_ksp.swis$pq_cur_kspI#define swis$pq_cur_esp swis$r_rsp_overlay.swis$r_rsp_ksp.swis$pq_cur_espI#define swis$pq_cur_ssp swis$r_rsp_overlay.swis$r_rsp_ksp.swis$pq_cur_sspI#define swis$pq_cur_usp swis$r_rsp_overlay.swis$r_rsp_ksp.swis$pq_cur_uspG#define swis$q_tss_ist swis$r_rsp_overlay.swis$r_rsp_ist.swis$q_tss_ist"#endif /* #if !defined(__VAXC) */ #define SWIS$K_LENGTH 8192#define SWIS$C_LENGTH 8192N#define SWIS$C_PAGE_SIZE 8192 /* Map with 8KB page saQize */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SWISDEF_LOADED */ wwM[UM/***************************************************************************/M/** bQ **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/McQ/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************************dQ**************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:28 by OpenVMS SDL V3.7 */H/* Source: 03-JAN-2023 14:11:30 $1$DGA8345:[LIB_H.SRC]SWRPBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SWRPBDEF ***/#ifndef __SWRPBDEF_LOAeQDED#define __SWRPBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#deffQine __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif (#define SWRPB_BOOT_FLAGS$M_SYSPROMPT 0x1%#define SWRPB_BOOT_FLAGS$M_XDELTA 0x2)#define SWRPB_BOOT_FLAGS$M_BREAKPOIN gQT 0x4%#define SWRPB_BOOT_FLAGS$M_DK_SDA 0x8(#define SWRPB_BOOT_FLAGS$M_PROGRESS 0x10'#define SWRPB_BOOT_FLAGS$M_SYSBOOT 0x20(#define SWRPB_BOOT_FLAGS$M_EXECINIT 0x40'#define SWRPB_BOOT_FLAGS$M_SYSINIT 0x80'#define SWRPB_BOOT_FLAGS$M_DRIVER 0x100'#define SWRPB_BOOT_FLAGS$M_SHADOW 0x200(#define SWRPB_BOOT_FLAGS$M_NETBOOT 0x400)#define SWRPB_BOOT_FLAGS$M_SYSDEBUG 0x800&#define SWRPB_BOOT_FLAGS$M_ACPI 0x1000+#define SWRPB_BOOT_FLAGS$M_HW_CONFIG 0x2000-#define SWRPB_BOOT_FLAGS$M_PAGE_FA hQULTS 0x4000&#define SWRPB_BOOT_FLAGS$M_HALT 0x8000,#define SWRPB_BOOT_FLAGS$M_DK_NOSYSD 0x10000)#define SWRPB_BOOT_FLAGS$M_X20000 0x20000)#define SWRPB_BOOT_FLAGS$M_X40000 0x40000)#define SWRPB_BOOT_FLAGS$M_X80000 0x80000+#define SWRPB_BOOT_FLAGS$M_X100000 0x100000+#define SWRPB_BOOT_FLAGS$M_X200000 0x200000+#define SWRPB_BOOT_FLAGS$M_X400000 0x400000-#define SWRPB_BOOT_FLAGS$M_OPDISPLAY 0x800000,#define SWRPB_BOOT_FLAGS$M_BOOTMGR 0x1000000-#define SWRPB_BOOT_FLAGS$M_MEMCHECK 0x2000iQ000-#define SWRPB_BOOT_FLAGS$M_DEVCHECK 0x4000000.#define SWRPB_BOOT_FLAGS$M_DEVELOPER 0x8000000-#define SWRPB_BOOT_FLAGS$M_MDCHECK 0x10000000.#define SWRPB_BOOT_FLAGS$M_CPUCHECK 0x20000000/#define SWRPB_BOOT_FLAGS$M_X40000000 0x40000000-#define SWRPB_BOOT_FLAGS$M_VERBOSE 0x80000000*#define SWRPB_BOOT_FLAGS$M_ROOT 0xFFFF0000#define SWRPB$M_LOAD_SCS 0x1#define SWRPB$M_TAKENODMP 0x2#define SWRPB$M_DUMP_DEV_OK 0x4#define SWRPB$M_MCHECK 0x8#define SWRPB$M_MEMTEST 0x10##define SWRP jQB$M_SATELLITE_BOOT 0x20+#define SWRPB_LAVC_FLAGS$M_CONV_BOOT_OK 0x1N#define SWRPB$C_LENGTH 356 /* Length of SWRPB */N#define SWRPB$K_LENGTH 356 /* Length of SWRPB */N#define SWRPB$S_SWRPBDEF 356 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */struct _btadp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If uskQing pre DECC V4.0 or C++ */'#pragma __nomember_alignment __octaword#else#pragma __nomember_alignment#endiftypedef struct _swrpb {#pragma __nomember_alignment __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *swrpb$pq_iovec_flink; /* IOVEC forward link */#else' unsigned __int64 swrpb$pq_iovec_flink;#endif lQ __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif) void *swrpb$pl_iovec_flink_l;0 unsigned int swrpb$il_iovec_flink_h;) } swrpb$r_iovec_flink_fields;& } swrpb$r_iovec_flink_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_poi mQnter_size __long /* And set ptr size default to 64-bit pointers */N void *swrpb$pq_iovec_blink; /* IOVEC backward link */#else' unsigned __int64 swrpb$pq_iovec_blink;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif) void *swrpb$pl_iovec_blink_l;0 unsigned int swrpb$il_iovec_blink_ nQh;) } swrpb$r_iovec_blink_fields;& } swrpb$r_iovec_blink_overlay;N/* Verified for x86 port--Drew Mason */N/* Copy of boot flags in HWRPB. These can be modified; leave the */N/* ones in the HWRPB as set by the boot manager. */ __union {- unsigned __int64 swrpb$iq_boot_flags; __struct { __union {3 unsigned int swrpb$il_boot_flags_l; oQ __struct {_ unsigned swrpb_boot_flags$v_sysprompt : 1; /* <0>0 SYSBOOT> Conversation */Z unsigned swrpb_boot_flags$v_xdelta : 1; /* <1>2 Load XDELTA execlet */b unsigned swrpb_boot_flags$v_breakpoint : 1; /* <2>4 Breakpoint in X(L)DELTA */e unsigned swrpb_boot_flags$v_dk_sda : 1; /* <3>8 Dump Kernel only: activate SDA */` unsigned swrpb_boot_flags$v_progress : 1; /* <4>10 Boot Progress Messages */pQY unsigned swrpb_boot_flags$v_sysboot : 1; /* <5>20 SYSBOOT Messages */[ unsigned swrpb_boot_flags$v_execinit : 1; /* <6>40 EXECINIT Messages */Y unsigned swrpb_boot_flags$v_sysinit : 1; /* <7>80 SYSINIT Messages */X unsigned swrpb_boot_flags$v_driver : 1; /* <8>100 DRIVER Messages */] unsigned swrpb_boot_flags$v_shadow : 1; /* <9>200 Boot from shadow set */c unsigned swrpb_boot_qQflags$v_netboot : 1; /* <10>400 Boot from network device */i unsigned swrpb_boot_flags$v_sysdebug : 1; /* <11>800 Load the System Code Debugger */] unsigned swrpb_boot_flags$v_acpi : 1; /* <12>1000 ACPI Config Messages */` unsigned swrpb_boot_flags$v_hw_config : 1; /* <13>2000 HW Config Messages */o unsigned swrpb_boot_flags$v_page_faults : 1; /* <14>4000 issue TR_PRINTs for page faults */h unsignedrQ swrpb_boot_flags$v_halt : 1; /* <15>8000 Halt before transfer to SYSBOOT */r unsigned swrpb_boot_flags$v_dk_nosysd : 1; /* <16>10000 Dump Kernel only: avoid System Disk */Q unsigned swrpb_boot_flags$v_x20000 : 1; /* <17>20000 Spare */Q unsigned swrpb_boot_flags$v_x40000 : 1; /* <18>40000 Spare */Q unsigned swrpb_boot_flags$v_x80000 : 1; /* <19>80000 Spare */S unsigned swrpb_boot_flags$v_x100000 : 1;sQ /* <20>100000 Spare */S unsigned swrpb_boot_flags$v_x200000 : 1; /* <21>200000 Spare */S unsigned swrpb_boot_flags$v_x400000 : 1; /* <22>400000 Spare */p unsigned swrpb_boot_flags$v_opdisplay : 1; /* <23>800000 Display OPA0 messages after boot */d unsigned swrpb_boot_flags$v_bootmgr : 1; /* <24>1000000 BOOTMGR> Conversation */c unsigned swrpb_boot_flags$v_memcheck : 1; /* <25>2000000 BootMgr Memory tQInfo */c unsigned swrpb_boot_flags$v_devcheck : 1; /* <26>4000000 BootMgr Device Info */d unsigned swrpb_boot_flags$v_developer : 1; /* <27>8000000 Developer Functions */e unsigned swrpb_boot_flags$v_mdcheck : 1; /* <28>10000000 MemoryDisk Diagnostic */d unsigned swrpb_boot_flags$v_cpucheck : 1; /* <29>20000000 CPU Init Diagnostic */W unsigned swrpb_boot_flags$v_x40000000 : 1; /* <30>40000000 Spare *uQ/` unsigned swrpb_boot_flags$v_verbose : 1; /* <31>80000000 Verbose Messages */N/* */N/* symbol names with the swrpb_boot_flags$m or swrpb_boot_flags$v prefix */N/* cannot exceed 31 characters total. */N/* */1 } swrpb$r_boot_flags_field_l;' } swrpb$r_boot_f vQlags_l; __union {3 unsigned int swrpb$il_boot_flags_h; __struct {y unsigned swrpb_boot_flags$v_fill1 : 16 /** WARNING: bitfield array has been reduced to a string **/ ;N unsigned swrpb_boot_flags$v_root : 16; /* System root */1 } swrpb$r_boot_flags_field_h;' } swrpb$r_boot_flags_h;( } swrpb$r_boot_flags_fields;% } swrpb$r_boot_flags_overlay;N/* Verif wQied for x86 port--Drew Mason */( unsigned __int64 swrpb$iq_verbosity; __union {* unsigned __int64 swrpb$iq_scb_lbn;c unsigned int swrpb$l_scb_lbn; /* LBN of the storage control block (SCB) on system disk */ } swrpb$r_scb_lbn_ovl;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */Q void *swrpb$pq_con xQio_base_va; /* Address of boot manager CONIO_TABLE */#else) unsigned __int64 swrpb$pq_conio_base_va;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */O void *swrpb$pq_hpet_base_va; /* Virtual address of HPET registers */#else( unsigned __int64 swrpb$pq_hpet_base_va;#endifb unsigned __int64 swrpb$iq_hpet_minimum_ticks; /* Minimum tick coyQunt without lost interrupts */X unsigned __int64 swrpb$iq_tsc_frequency; /* Nominal Frequency of the TSC in Hertz */` unsigned __int64 swrpb$iq_uefi_cr3; /* Value at boot time of CR3 (PTBR) passed in by UEFI */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */[ void *swrpb$pq_lapic_base_va; /* Virtual address of the processor's local APIC */#else) unsignezQd __int64 swrpb$pq_lapic_base_va;#endifN unsigned __int64 swrpb$iq_min_bitmap_pfn; /* Low PFN in bitmap 1 */N unsigned __int64 swrpb$iq_max_bitmap_pfn; /* High PFN in bitmap 1 */N unsigned __int64 swrpb$iq_min_bitmap_pfn2; /* Low PFN in bitmap 2 */N unsigned __int64 swrpb$iq_max_bitmap_pfn2; /* High PFN in bitmap 2 */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr si {Qze default to 64-bit pointers */N void *swrpb$pq_pfn_map; /* Address of bitmap 1 */#else# unsigned __int64 swrpb$pq_pfn_map;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *swrpb$pq_pfn_map2; /* Address of bitmap 2 */#else$ unsigned __int64 swrpb$pq_pfn_map2;#endif __union {R#ifdef __INI |QTIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N struct _btadp *swrpb$pq_btadp; /* BOOT ADAPTER BLOCK */#else! unsigned __int64 swrpb$pq_btadp;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif, }Q struct _btadp *swrpb$pl_btadp_l;* unsigned int swrpb$il_btadp_h;# } swrpb$r_btadp_fields; } swrpb$r_btadp_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *swrpb$pq_booparam; /* EXEC_INIT Param block */#else$ unsigned __int64 swrpb$pq_booparam;#endif __struct { ~QR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif& void *swrpb$pl_booparam_l;- unsigned int swrpb$il_booparam_h;& } swrpb$r_booparam_fields;# } swrpb$r_booparam_overlay;N/* Verified for x86 port--Drew Mason */P __int64 swrpb$iq_pcieconfigurationbase; /* PA of PCIe configuration Qspace */N __int64 swrpb$iq_memdiskaddress; /* PA or VA of boot memory disk */N __int64 swrpb$iq_memdisksize; /* size of memory disk in bytes */T __int64 swrpb$iq_asn_max; /* maximum ASN supported by the hardware, */N/* zero if ASNs not supported */ __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default t Qo 64-bit pointers */N void *swrpb$pq_iochan; /* IOCHAN of boot driver */#else" unsigned __int64 swrpb$pq_iochan;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif$ void *swrpb$pl_iochan_l;+ unsigned int swrpb$il_iochan_h;$ } swrpb$r_iochan_fields;! } swrpb$r_iochQan_overlay; __union {N unsigned __int64 swrpb$iq_boot_time; /* Time that system was booted */ __struct {. unsigned int swrpb$il_boot_time_l;. unsigned int swrpb$il_boot_time_h;' } swrpb$r_boot_time_fields;$ } swrpb$r_boot_time_overlay; __union {N unsigned __int64 swrpb$iq_flags; /* Other bootstrap flags */ __struct { __union {. unsigned int swrpb$il_flags_l; Q __struct {N unsigned swrpb$v_load_scs : 1; /* Load SCS code */R unsigned swrpb$v_takenodmp : 1; /* Do not take dump, master */N/* changed for shadowed system */N/* disk. Note: On VAX, */N/* TAKENODMP was added to RPB */N/* to pass to console reboot */NQ/* logic. */S unsigned swrpb$v_dump_dev_ok : 1; /* Take the dump device is */N/* under dump_dev E.V. control */[ unsigned swrpb$v_mcheck : 1; /* Set when a hard memory error occurs. */^ unsigned swrpb$v_memtest : 1; /* Set when memory testing is in progress */] unsigned swrpb$v_satellite_boot : 1; /* This is an Q IA64 satellite boot */N/* currently not set on Alpha */n unsigned swrpb$v_fill1 : 26 /** WARNING: bitfield array has been reduced to a string **/ ;+ } swrpb$r_flags_field1;/ } swrpb$r_flags_fields_overlay;* unsigned int swrpb$il_flags_h;# } swrpb$r_flags_fields; } swrpb$r_flags_overlay; __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr siz Qe pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *swrpb$pq_port_chan; /* PORT_CHAN of port boot driver */#else% unsigned __int64 swrpb$pq_port_chan;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif' void *swrpb$pl_port_chan_l;. Q unsigned int swrpb$il_port_chan_h;' } swrpb$r_port_chan_fields;$ } swrpb$r_port_chan_overlay; __union {N unsigned __int64 swrpb$iq_scb_size; /* Size of the runtime SCB */ __struct {- unsigned int swrpb$il_scb_size_l;- unsigned int swrpb$il_scb_size_h;& } swrpb$r_scb_size_fields;# } swrpb$r_scb_size_overlay;N/* The following fields are filled in by APB if a NISCA */N/* boot iQs being performed on a LAVc satellite. These */N/* fields are cluster specific fields. */N char swrpb$t_scsnode [8]; /* System's SCS node name. */N unsigned __int64 swrpb$iq_scssystemid; /* System's SCSSYSTEMID value. */N/* The following fields are filled in by APB if a NISCA */N/* boot is being performed on a LAVc satellite. */N unsigned __int64 swrpb$iq_lavc_a Quth; /* LAVc authorization code. */N unsigned int swrpb$il_lavc_group; /* LAVc group number. */N unsigned int swrpb$il_lavc_port_services; /* NISCA port services. */ __union {N unsigned int swrpb$il_lavc_flags; /* LAVc boot control flags. */ __struct {[ unsigned swrpb_lavc_flags$v_conv_boot_ok : 1; /* Allow converstational boot. */4 unsigned swrpb_lavc_flags$v_fill_0_ : 7;' } swrpb$r_lavc_flags_fieQld;% } swrpb$r_lavc_flags_overlay;N int swrpb$l_lavc_fill; /* Preserve quadword alignment. */N/* End of fields used for LAVc satellite booting. */N/* Define the file system data. */` char swrpb$t_sysroot [40]; /* Root directory on the system disk. Counted string */N/* End of the file system data. */N/* Verified for x86 port--Drew Mason Q */Z unsigned __int64 (*swrpb$ps_sva_to_pa)(); /* Vector to routine converting SVA to PA */N/* Verified for x86 port--Drew Mason */N/* */N/* These fields are filled in by SYSBOOT and are used by SYSBOOT to do */N/* console I/O. */N/* Q */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *swrpb$pq_con_input_chan; /* Console terminal's input channel */#else* unsigned __int64 swrpb$pq_con_input_chan;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit poi Qnters */O void *swrpb$pq_con_output_chan; /* Console terminal's output channel */#else+ unsigned __int64 swrpb$pq_con_output_chan;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *swrpb$pq_cpuid_info; /* Pointer to all CPUID leaves */#else& unsigned __int64 swrpb$pq_cpuid_info;#endifN __int64 swrpb$iq_xsave_area_size; Q/* Size of XSAVE area */N/* New for x86 - Gary Newsted */N __int64 swrpb$iq_system_memdisk_va; /* VA of ISO Kit memory disk */T __int64 swrpb$iq_system_memdisk_size; /* size of ISO Kit memory disk in bytes */ char swrpb$b_fill_1_ [12]; } SWRPB; #if !defined(__VAXC)M#define swrpb$pq_iovec_flink swrpb$r_iovec_flink_overlay.swrpb$pq_iovec_flinkl#define swrpb$pl_iovec_flink_l swrpb$r_iovec_flink_overlay.swrpb$r_iQovec_flink_fields.swrpb$pl_iovec_flink_ll#define swrpb$il_iovec_flink_h swrpb$r_iovec_flink_overlay.swrpb$r_iovec_flink_fields.swrpb$il_iovec_flink_hM#define swrpb$pq_iovec_blink swrpb$r_iovec_blink_overlay.swrpb$pq_iovec_blinkl#define swrpb$pl_iovec_blink_l swrpb$r_iovec_blink_overlay.swrpb$r_iovec_blink_fields.swrpb$pl_iovec_blink_ll#define swrpb$il_iovec_blink_h swrpb$r_iovec_blink_overlay.swrpb$r_iovec_blink_fields.swrpb$il_iovec_blink_hJ#define swrpb$iq_boot_flags swrpb$r_boot_flags_overlayQ.swrpb$iq_boot_flags}#define swrpb$il_boot_flags_l swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$il_boot_flags_l#define swrpb_boot_flags$v_sysprompt swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_f\#ield_l.swrpb_boot_flags$v_sysprompt#define swrpb_boot_flags$v_xdelta swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fiel\d_l.swrpb_boot_flags$v_xdelta#define swrpb_bootQ_flags$v_breakpoint swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_\%field_l.swrpb_boot_flags$v_breakpoint#define swrpb_boot_flags$v_dk_sda swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fiel\d_l.swrpb_boot_flags$v_dk_sda#define swrpb_boot_flags$v_progress swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fi\!eld_l.swrpb_boot_flags$v_progress#define swrpb_Qboot_flags$v_sysboot swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fie\ld_l.swrpb_boot_flags$v_sysboot#define swrpb_boot_flags$v_execinit swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fi\!eld_l.swrpb_boot_flags$v_execinit#define swrpb_boot_flags$v_sysinit swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fie\ld_l.swrpb_boot_flags$v_sysinit#define swrpb_Qboot_flags$v_driver swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fiel\d_l.swrpb_boot_flags$v_driver#define swrpb_boot_flags$v_shadow swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fiel\d_l.swrpb_boot_flags$v_shadow#define swrpb_boot_flags$v_netboot swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fie\ld_l.swrpb_boot_flags$v_netboot#define swrpb_boot_fQlags$v_sysdebug swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fi\!eld_l.swrpb_boot_flags$v_sysdebug#define swrpb_boot_flags$v_acpi swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_field_\l.swrpb_boot_flags$v_acpi#define swrpb_boot_flags$v_hw_config swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_f\#ield_l.swrpb_boot_flags$v_hw_config#define swrpb_boot_flaQgs$v_page_faults swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags\'_field_l.swrpb_boot_flags$v_page_faults#define swrpb_boot_flags$v_halt swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_field_\l.swrpb_boot_flags$v_halt#define swrpb_boot_flags$v_dk_nosysd swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_f\#ield_l.swrpb_boot_flags$v_dk_nosysd#define swrpb_bootQ_flags$v_x20000 swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fiel\d_l.swrpb_boot_flags$v_x20000#define swrpb_boot_flags$v_x40000 swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fiel\d_l.swrpb_boot_flags$v_x40000#define swrpb_boot_flags$v_x80000 swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fiel\d_l.swrpb_boot_flags$v_x80000#define swrpb_boot_flags$vQ_x100000 swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fie\ld_l.swrpb_boot_flags$v_x100000#define swrpb_boot_flags$v_x200000 swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fie\ld_l.swrpb_boot_flags$v_x200000#define swrpb_boot_flags$v_x400000 swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fie\ld_l.swrpb_boot_flags$v_x400000#define swrpb_boot_flags$v_oQpdisplay swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_f\#ield_l.swrpb_boot_flags$v_opdisplay#define swrpb_boot_flags$v_bootmgr swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fie\ld_l.swrpb_boot_flags$v_bootmgr#define swrpb_boot_flags$v_memcheck swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fi\!eld_l.swrpb_boot_flags$v_memcheck#define swrpb_boot_flagsQ$v_devcheck swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fi\!eld_l.swrpb_boot_flags$v_devcheck#define swrpb_boot_flags$v_developer swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_f\#ield_l.swrpb_boot_flags$v_developer#define swrpb_boot_flags$v_mdcheck swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fie\ld_l.swrpb_boot_flags$v_mdcheck#define swrpb_boot_fQlags$v_cpucheck swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fi\!eld_l.swrpb_boot_flags$v_cpucheck#define swrpb_boot_flags$v_x40000000 swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_f\#ield_l.swrpb_boot_flags$v_x40000000#define swrpb_boot_flags$v_verbose swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_l.swrpb$r_boot_flags_fie\ld_l.swrpb_boot_flags$v_verbose}#define swrpb$ilQ_boot_flags_h swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_h.swrpb$il_boot_flags_h#define swrpb_boot_flags$v_root swrpb$r_boot_flags_overlay.swrpb$r_boot_flags_fields.swrpb$r_boot_flags_h.swrpb$r_boot_flags_field_\h.swrpb_boot_flags$v_root=#define swrpb$iq_scb_lbn swrpb$r_scb_lbn_ovl.swrpb$iq_scb_lbn;#define swrpb$l_scb_lbn swrpb$r_scb_lbn_ovl.swrpb$l_scb_lbn;#define swrpb$pq_btadp swrpb$r_btadp_overlay.swrpb$pq_btadpT#define swrpb$pl_btadp_l swrpb$r_btadp_overlQay.swrpb$r_btadp_fields.swrpb$pl_btadp_lT#define swrpb$il_btadp_h swrpb$r_btadp_overlay.swrpb$r_btadp_fields.swrpb$il_btadp_hD#define swrpb$pq_booparam swrpb$r_booparam_overlay.swrpb$pq_booparam`#define swrpb$pl_booparam_l swrpb$r_booparam_overlay.swrpb$r_booparam_fields.swrpb$pl_booparam_l`#define swrpb$il_booparam_h swrpb$r_booparam_overlay.swrpb$r_booparam_fields.swrpb$il_booparam_h>#define swrpb$pq_iochan swrpb$r_iochan_overlay.swrpb$pq_iochanX#define swrpb$pl_iochan_l swrpb$r_iochan_overlayQ.swrpb$r_iochan_fields.swrpb$pl_iochan_lX#define swrpb$il_iochan_h swrpb$r_iochan_overlay.swrpb$r_iochan_fields.swrpb$il_iochan_hG#define swrpb$iq_boot_time swrpb$r_boot_time_overlay.swrpb$iq_boot_timed#define swrpb$il_boot_time_l swrpb$r_boot_time_overlay.swrpb$r_boot_time_fields.swrpb$il_boot_time_ld#define swrpb$il_boot_time_h swrpb$r_boot_time_overlay.swrpb$r_boot_time_fields.swrpb$il_boot_time_h;#define swrpb$iq_flags swrpb$r_flags_overlay.swrpb$iq_flagsq#define swrpb$il_flags_l swrpb$r_fQlags_overlay.swrpb$r_flags_fields.swrpb$r_flags_fields_overlay.swrpb$il_flags_l#define swrpb$v_load_scs swrpb$r_flags_overlay.swrpb$r_flags_fields.swrpb$r_flags_fields_overlay.swrpb$r_flags_field1.swrpb$v_load_\scs#define swrpb$v_takenodmp swrpb$r_flags_overlay.swrpb$r_flags_fields.swrpb$r_flags_fields_overlay.swrpb$r_flags_field1.swrpb$v_take\nodmp#define swrpb$v_dump_dev_ok swrpb$r_flags_overlay.swrpb$r_flags_fields.swrpb$r_flags_fields_overlay.swrpb$r_flags_field1.swrpb$v_du\ mp_dev_oQk#define swrpb$v_mcheck swrpb$r_flags_overlay.swrpb$r_flags_fields.swrpb$r_flags_fields_overlay.swrpb$r_flags_field1.swrpb$v_mcheck#define swrpb$v_memtest swrpb$r_flags_overlay.swrpb$r_flags_fields.swrpb$r_flags_fields_overlay.swrpb$r_flags_field1.swrpb$v_memtest#define swrpb$v_satellite_boot swrpb$r_flags_overlay.swrpb$r_flags_fields.swrpb$r_flags_fields_overlay.swrpb$r_flags_field1.swrpb$v\_satellite_bootT#define swrpb$il_flags_h swrpb$r_flags_overlay.swrpb$r_flags_fields.swrpb$il_flags_hQG#define swrpb$pq_port_chan swrpb$r_port_chan_overlay.swrpb$pq_port_chand#define swrpb$pl_port_chan_l swrpb$r_port_chan_overlay.swrpb$r_port_chan_fields.swrpb$pl_port_chan_ld#define swrpb$il_port_chan_h swrpb$r_port_chan_overlay.swrpb$r_port_chan_fields.swrpb$il_port_chan_hD#define swrpb$iq_scb_size swrpb$r_scb_size_overlay.swrpb$iq_scb_size`#define swrpb$il_scb_size_l swrpb$r_scb_size_overlay.swrpb$r_scb_size_fields.swrpb$il_scb_size_l`#define swrpb$il_scb_size_h swrpb$r_scb_size_overlay.swrpb Q$r_scb_size_fields.swrpb$il_scb_size_hJ#define swrpb$il_lavc_flags swrpb$r_lavc_flags_overlay.swrpb$il_lavc_flags{#define swrpb_lavc_flags$v_conv_boot_ok swrpb$r_lavc_flags_overlay.swrpb$r_lavc_flags_field.swrpb_lavc_flags$v_conv_boot_ok"#endif /* #if !defined(__VAXC) */  $#pragma __required_pointer_size longtypedef SWRPB * SWRPB_PQ;%#pragma __required_pointer_size shorttypedef SWRPB * SWRPB_PL; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined Qwhenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SWRPBDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/QM/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary softwareQ licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************* Q*******************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */H/* Source: 02-SEP-1989 10:56:14 $1$DGA8345:[LIB_H.SRC]SYSAPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SYSAPDEF ***/#ifndef __SYSAPDEF_LOADED#define __SYSAPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard featQures */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __opQtional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* SYSAP - FLAGS USED IN THE SYSAP-SCS INTERFACE */N/*- Q */N/*OPTIONS FOR DISPOSING OF */N/* SENT DATAGRAM: */N/* 0 ORIGIN, INCR OF 1: */N#define SYSAP$C_DISPQ 0 /* DISPOSE ON DG FREE QUEUE */N#define SYSAP$C_DISPRET 1 /* DISPOSE BY RETURN TO SYSAP */N#define SYSAP$C_DISPPO 2 /* DISPOSE BY RETURN TO POOL */N/*FLAGS QSPECIFYING TYPE OF DG */N/* REC'D FROM REMOTE SYSAP: */N/* 0 ORIGIN, INCR OF 1: */N#define SYSAP$C_DGREC 0 /* DG REC'D FROM REMOTE */N#define SYSAP$C_DGSNT 1 /* DG SENT */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas suQpported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SYSAPDEF_LOADED */ ww@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-PaQckard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, IQnc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************************************** Q***************************************************/=/* Created: 7-Oct-2024 15:23:33 by OpenVMS SDL V3.7 */J/* Source: 22-DEC-1999 13:36:39 $1$DGA8345:[LIB_H.SRC]SYSEVTIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SYSEVTIDEF ***/#ifndef __SYSEVTIDEF_LOADED#define __SYSEVTIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __Qmember_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...Q#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* get the ACB def */N/* get the spinlock definitions */ #include #include N/* This system ACB structure is cr Qeated when the $SET_SYSTEM_EVENT system */N/* service is invoked. */N/* */N#define SYSEVT_ACB$K_LENGTH 84 /* Length of block. */N#define SYSEVT_ACB$C_LENGTH 84 /* Length of block. */ typedef struct _sysevt_acb {& ACB64 sysevt_acb$r_imbedded_acb64; __union {- unsigned __int64 sysevt_acb$q_handle; Q __struct {( int sysevt_acb$l_sysevt_acb;% int sysevt_acb$l_seq_num;# } sysevt_acb$r_fill_1_; } sysevt_acb$r_fill_0_;` unsigned int sysevt_acb$l_events; /* mask of events for which process is to be notified */a unsigned int sysevt_acb$l_local_queue; /* set indicates SYSEVT_ACB on SYSEVT private queue */N unsigned int sysevt_acb$l_imgcnt; /* image count taken from the PHD */ } SYSEVT_ACB; #if !defined(__VAXC)D#define Qsysevt_acb$q_handle sysevt_acb$r_fill_0_.sysevt_acb$q_handlea#define sysevt_acb$l_sysevt_acb sysevt_acb$r_fill_0_.sysevt_acb$r_fill_1_.sysevt_acb$l_sysevt_acb[#define sysevt_acb$l_seq_num sysevt_acb$r_fill_0_.sysevt_acb$r_fill_1_.sysevt_acb$l_seq_num"#endif /* #if !defined(__VAXC) */ &#define SYSEVT$M_GALAXY_REGISTERED 0x1N#define SYSEVT$K_LENGTH 40 /* Length of block. */N#define SYSEVT$C_LENGTH 40 /* Length of block. */ typedeQf struct _sysevt {N/* */N/* This is the system event data structure. This data struture contains */N/* an AST queue listhead, a lock to synchronize access to the queue, and a */S/* sequence number field. Each time a process requests notification of a system */R/* event (or set of events), an AST is queued. Then when the event occurs, the */N/* AST is removed from this queue and delivered to the target process. Q*/N/* */U unsigned __int64 sysevt$q_event_mask; /* Bitmask of events which indicate that */N/* something may be in the queue for this event. */N unsigned short int sysevt$w_size; /* Size of data structure */N unsigned char sysevt$b_type; /* Type is DYN$C_SYSEVT */S unsigned char sysevt$b_subtype; /* Subtype field to further qualify type */N stru Qct _spl *sysevt$ps_lock; /* Pointer to dynamic spinlock */ __union {N unsigned __int64 sysevt$q_flags; /* interlocked flags */ __struct {h unsigned sysevt$v_galaxy_registered : 1; /* Galaxy membership callback routine registered */* unsigned sysevt$v_fill_2_ : 7;! } sysevt$r_flag_bits;! } sysevt$r_flags_overlay;N unsigned __int64 sysevt$q_seq_num; /* ever increasing counter */N struct _sy Qsevt_acb *sysevt$l_ast_qfl; /* queued SYSEVT_ACBs */) struct _sysevt_acb *sysevt$l_ast_qbl; } SYSEVT; #if !defined(__VAXC)<#define sysevt$q_flags sysevt$r_flags_overlay.sysevt$q_flagsg#define sysevt$v_galaxy_registered sysevt$r_flags_overlay.sysevt$r_flag_bits.sysevt$v_galaxy_registered"#endif /* #if !defined(__VAXC) */  M #define sysevt_acb$l_astqfl sysevt_acb$r_imbedded_acb64.acb64$l_astqfl;M #define sysevt_acb$l_astqbl sysevt_acb$r_imbedded_acb64.Qacb64$l_astqbl;J #define sysevt_acb$w_size sysevt_acb$r_imbedded_acb64.acb64$w_sizeJ #define sysevt_acb$b_type sysevt_acb$r_imbedded_acb64.acb64$b_typeJ #define sysevt_acb$b_rmod sysevt_acb$r_imbedded_acb64.acb64$b_rmodJ #define sysevt_acb$v_mode sysevt_acb$r_imbedded_acb64.acb64$v_modeN #define sysevt_acb$v_nodelete sysevt_acb$r_imbedded_acb64.acb64$v_nodeleteK #define sysevt_acb$v_pkast sysevt_acb$r_imbedded_acb64.acb64$v_pkastK #define sysevt_acb$v_qQuota sysevt_acb$r_imbedded_acb64.acb64$v_quotaK #define sysevt_acb$l_flags sysevt_acb$r_imbedded_acb64.acb64$l_flagsW #define sysevt_acb$v_flags_valid sysevt_acb$r_imbedded_acb64.acb64$v_flags_validI #define sysevt_acb$l_pid sysevt_acb$r_imbedded_acb64.acb64$l_pidL #define sysevt_acb$l_acb64x sysevt_acb$r_imbedded_acb64.acb64$l_acb64xK #define sysevt_acb$pq_ast sysevt_acb$r_imbedded_acb64.acb64$pq_astL #define sysevt_acb$q_astprm sysevt_acb$r_imbeddeQd_acb64.acb64$q_astprmJ #define sysevt_acb$l_kast sysevt_acb$r_imbedded_acb64.acb64$l_kastL #define sysevt_acb$v_64bits sysevt_acb$r_imbedded_acb64.acb64$v_64bits $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SYSEVTIDEF_LOADED */ Q ww`7[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/AQSWISDEF SWIS_ROUTINES`QfSWRPBDEFQSYSAPDEF SYSAP_MACROSQ SYSEVTIDEFQSYSGDEFQSYSMDDEFQ SYSPARDEFSYSTEM_SERVICE_SETUP SYS_FUNCTIONS.R>T10DEFSTASTDEFjTFDEFQM/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMSQ Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */G/* Source: 26-FEB-2024 10:38:06 $1$DGA8345:[LIB_H.SRC]SYSGDEF.SDL;1 *//******************* Q*************************************************************************************************************//*** MODULE $SYSGDEF ***/#ifndef __SYSGDEF_LOADED#define __SYSGDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptrQ size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __unQion variant_union#endif#endif "#define SYSG$M_UCB_CONFIG_CONS 0x1##define SYSG$M_UCB_CONFIG_PPORT 0x2"#define SYSG$M_UCB_CONFIG_KBIO 0x4&#define SYSG$M_WORKSTATION_PRESENT 0x1"#define SYSG$M_WIND_SYS_ACTIVE 0x2#define SYSG$M_ALT_CONSOLE 0x4##define SYSG$M_WIND_SYS_CONSOLE 0x8(#define SYSG$M_GUEST_CONSOLE_ACTIVE 0x10#define SYSG$M_UNIT0_TX 0x1#define SYSG$M_UNIT0_RX 0x2#define SYSG$M_UNIT1_TX 0x4#define SYSG$M_UNIT1_RX 0x8#define SYSG$M_UNIT2_TX 0x10#define SYSG$M_UNIQT2_RX 0x20#define SYSG$M_UNIT3_TX 0x40#define SYSG$M_UNIT3_RX 0x80#define SYSG$M_UNIT4_TX 0x100#define SYSG$M_UNIT4_RX 0x200%#define SYSG$M_IPF_CONSOLE_POLLED 0x1'#define SYSG$M_IPF_CON_POLLED_INPUT 0x2(#define SYSG$M_IPF_CON_POLLED_OUTPUT 0x4(#define SYSG$M_IPF_SETCHAR_SUPPORTED 0x8*#define SYSG$M_IPF_INTERRUPTS_ALLOWED 0x10##define SYSG$M_IPF_VGA_CONSOLE 0x20  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; struct _ctb; #endif /* #ifdef __cpluspQlus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sysg {#pragma __nomember_alignment __union {T unsigned __int64 sysg$iq_kb_ucb; /* Address of UCB for the workstation KB */ __struct {* struct _ucb *sysg$il_kb_ucb_l;* unsigned int sysg$il_kb_ucb_h;# } sysg$r_kb_ucb_fields; Q } sysg$r_kb_ucb_overlay; __union {Z unsigned __int64 sysg$iq_mouse_ucb; /* Address of UCB for the workstation mouse */ __struct {- struct _ucb *sysg$il_mouse_ucb_l;- unsigned int sysg$il_mouse_ucb_h;& } sysg$r_mouse_ucb_fields;# } sysg$r_mouse_ucb_overlay;N unsigned int sysg$il_sysg_size; /* Length of structure. */N unsigned int sysg$il_spare1; /* Spare use */ __un Qion {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *sysg$pq_ctb_ptr; /* Console Terminal Block pointer. */#else" unsigned __int64 sysg$pq_ctb_ptr;#endif __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit poin Qters */#endif+ struct _ctb *sysg$pl_ctb_ptr_l;+ unsigned int sysg$il_ctb_ptr_h;$ } sysg$r_ctb_ptr_fields;! } sysg$r_ctb_ptr_overlay; __union {d unsigned int sysg$il_ucb_config; /* Tells autoconfig which opa lines should be configured */ __struct {O unsigned sysg$v_ucb_config_cons : 1; /* OPA0 (always configured) */N unsigned sysg$v_ucb_config_pport : 1; /* Printer port (unit 1) */R unsigned Q sysg$v_ucb_config_kbio : 1; /* KB I/O for windows (unit 2) */( unsigned sysg$v_fill_0_ : 5;% } sysg$r_ucb_config_bits; } sysg$r_ucb_config_def; __union {N unsigned int sysg$il_flags; /* Flags for the window system */ __struct {R unsigned sysg$v_workstation_present : 1; /* System is a workstation */N/* */Z unsigned sysg$v_wind_sys_active Q: 1; /* Windowing system has been activated */N/* (Bit set by server) */N unsigned sysg$v_alt_console : 1; /* alternate console in use. */T unsigned sysg$v_wind_sys_console : 1; /* Use windowing system console */N/* (Bit set by server) */V unsigned sysg$v_guest_console_active : 1; /* X86 Guest Console Term Rdy */( unsigned sysg$v_fill_1_ : 3; Q } sysg$r_flags_bits; } sysg$r_flagsdef;N __union { /* This used to be OPWIN UP */Q unsigned __int64 sysg$iq_opwin_updown_pd; /* Console Visibility Toggle */- unsigned __int64 sysg$iq_opwin_up_pd; __struct {/ unsigned int sysg$il_opwin_up_pd_l;/ unsigned int sysg$il_opwin_up_pd_h;( } sysg$r_opwin_up_pd_fields;% } sysg$r_opwin_up_pd_overlay;N __union { Q /* This used to be OPWIN RESIZE */N unsigned __int64 sysg$iq_opwin_resize_pd; /* Console Window Resize *// unsigned __int64 sysg$iq_opwin_down_pd; __struct {1 unsigned int sysg$il_opwin_down_pd_l;1 unsigned int sysg$il_opwin_down_pd_h;* } sysg$r_opwin_down_pd_fields;' } sysg$r_opwin_down_pd_overlay; __union {N unsigned __int64 sysg$iq_unit_int; /* Unit interrupt bits */ __struct Q{) unsigned sysg$v_unit0_tx : 1;) unsigned sysg$v_unit0_rx : 1;) unsigned sysg$v_unit1_tx : 1;) unsigned sysg$v_unit1_rx : 1;) unsigned sysg$v_unit2_tx : 1;) unsigned sysg$v_unit2_rx : 1;) unsigned sysg$v_unit3_tx : 1;) unsigned sysg$v_unit3_rx : 1;) unsigned sysg$v_unit4_tx : 1;) unsigned sysg$v_unit4_rx : 1;( unsigned sysg$v_fill_2_ : 6; } sysg$r Q_unit_bits; } sysg$r_unit_int_def; __union {N unsigned __int64 sysg$iq_opwin_reset_pd; /* Reset console */ __struct {2 unsigned int sysg$il_opwin_reset_pd_l;2 unsigned int sysg$il_opwin_reset_pd_h;+ } sysg$r_opwin_reset_pd_fields;( } sysg$r_opwin_reset_pd_overlay; __union {N unsigned __int64 sysg$iq_opwin_puts_pd; /* Put string to console */ __struct {1 unsigned int sysg$il Q_opwin_puts_pd_l;1 unsigned int sysg$il_opwin_puts_pd_h;* } sysg$r_opwin_puts_pd_fields;' } sysg$r_opwin_puts_pd_overlay; __union {N unsigned __int64 sysg$iq_opwin_visible_pd; /* Test visibility */ __struct {4 unsigned int sysg$il_opwin_visible_pd_l;4 unsigned int sysg$il_opwin_visible_pd_h;- } sysg$r_opwin_visible_pd_fields;* } sysg$r_opwin_visible_pd_overlay; __union {N unsign Qed __int64 sysg$iq_opwin_halt_pd; /* Handle HALT */ __struct {1 unsigned int sysg$il_opwin_halt_pd_l;1 unsigned int sysg$il_opwin_halt_pd_h;* } sysg$r_opwin_halt_pd_fields;' } sysg$r_opwin_halt_pd_overlay; __union {N unsigned __int64 sysg$iq_opwin_continue_pd; /* Handle CONTINUE */ __struct {5 unsigned int sysg$il_opwin_comtinue_pd_l;5 unsigned int sysg$il_opwin_continue_pd_h; Q. } sysg$r_opwin_continue_pd_fields;+ } sysg$r_opwin_continue_pd_overlay; __union {P unsigned __int64 sysg$iq_console_language_pd; /* Get console language */ __struct {7 unsigned int sysg$il_console_language_pd_l;7 unsigned int sysg$il_console_language_pd_h;0 } sysg$r_console_language_pd_fields;- } sysg$r_console_language_pd_overlay;N unsigned __int64 sysg$iq_spare_1_pd; /* Reserved Q*/N unsigned __int64 sysg$iq_spare_2_pd; /* Reserved */N unsigned __int64 sysg$iq_spare_3_pd; /* Reserved */N unsigned __int64 sysg$iq_spare_4_pd; /* Reserved */ __union {- unsigned __int64 sysg$iq_kbd_getc_pd; __struct {( void *sysg$il_kbd_getc_pd_l;/ unsigned int sysg$il_kbd_getc_pd_h;% } sysg$r_kbd_getc_fields;" } sysg$r_kbd_getc_overlay;N __unQion { /* IPF CONSOLE flags */. unsigned int sysg$l_ipf_console_flags; __struct {O unsigned sysg$v_ipf_console_polled : 1; /* Polled mode requested */R unsigned sysg$v_ipf_con_polled_input : 1; /* Polled input supported */T unsigned sysg$v_ipf_con_polled_output : 1; /* Polled output supported */\ unsigned sysg$v_ipf_setchar_supported : 1; /* Can change line characteristics */e unsign Qed sysg$v_ipf_interrupts_allowed : 1; /* System now capable of taking interrupts */N unsigned sysg$v_ipf_vga_console : 1; /* Indicates VGA Console */( unsigned sysg$v_fill_3_ : 2;+ } sysg$r_ipf_console_flag_bits;+ } sysg$r_ifp_console_flags_overlay; __union {a unsigned __int64 sysg$iq_ipf_conin_ucb; /* Address of UCB for the console input device */ __struct {1 struct _ucb *sysg$il_ipf_conin_ucb_l;1 unsi Qgned int sysg$il_ipf_conin_ucb_h;* } sysg$r_ipf_conin_ucb_fields;' } sysg$r_ipf_conin_ucb_overlay; __union {b unsigned __int64 sysg$iq_ipf_conout_ucb; /* Address of UCB for the console input device */ __struct {2 struct _ucb *sysg$il_ipf_conout_ucb_l;2 unsigned int sysg$il_ipf_conout_ucb_h;+ } sysg$r_ipf_conout_ucb_fields;( } sysg$r_ipf_conout_ucb_overlay; __union { unsigned __int64 sysg$iq_ipf_s Qetchar_ucb; /* Address of UCB for the console device that supports characteristics changing */ __struct {3 struct _ucb *sysg$il_ipf_setchar_ucb_l;3 unsigned int sysg$il_ipf_setchar_ucb_h;, } sysg$r_ipf_setchar_ucb_fields;) } sysg$r_ipf_setchar_ucb_overlay;N __union { /* OPDRIVER pseudo-input interrupt */N unsigned __int64 sysg$iq_ipf_con_intin; /* routine. */ __struct {* Q void *sysg$il_ipf_con_intin_l;1 unsigned int sysg$il_ipf_con_intin_h;* } sysg$r_ipf_con_intin_fields;' } sysg$r_ipf_con_intin_overlay;N __union { /* OPDRIVER pseudo-output interrupt */N unsigned __int64 sysg$iq_ipf_con_intout; /* routine. */ __struct {+ void *sysg$il_ipf_con_intout_l;2 unsigned int sysg$il_ipf_con_intout_h;+ } sysg$r_ipf_con_intout_fields;( Q } sysg$r_ipf_con_intout_overlay;N __union { /* Routine OPDRIVER calls to get */S unsigned __int64 sysg$iq_ipf_con_getchar; /* characters from the console */ __struct {, void *sysg$il_ipf_con_getchar_l;3 unsigned int sysg$il_ipf_con_getchar_h;, } sysg$r_ipf_con_getchar_fields;) } sysg$r_ipf_con_getchar_overlay;N __union { /* Routine OPDRIVER calls to send */Q unsi Qgned __int64 sysg$iq_ipf_con_outchar; /* characters to the console */ __struct {, void *sysg$il_ipf_con_putchar_l;3 unsigned int sysg$il_ipf_con_putchar_h;, } sysg$r_ipf_con_putchar_fields;) } sysg$r_ipf_con_putchar_overlay;N __union { /* Routine OPDRIVER calls to */Q unsigned __int64 sysg$iq_ipf_con_setchar; /* change console line speed */N __struct { /* only meaningful Q for serial */N void *sysg$il_ipf_con_setchar_l; /* consoles */3 unsigned int sysg$il_ipf_con_setchar_h;, } sysg$r_ipf_con_setchar_fields;) } sysg$r_ipf_con_setchar_overlay;N __union { /* Routine OPDRIVER calls to */P unsigned __int64 sysg$iq_ipf_set_intin_state; /* change console input */N __struct { /* interrupt state */0 void * Qsysg$il_ipf_set_intin_state_l;7 unsigned int sysg$il_ipf_set_intin_state_h;0 } sysg$r_ipf_set_intin_state_fields;- } sysg$r_ipf_set_intin_state_overlay;N __union { /* Routine OPDRIVER calls to */R unsigned __int64 sysg$iq_ipf_set_intout_state; /* change console output */N __struct { /* interrupt state */1 void *sysg$il_ipf_set_intout_state_l;8 unsigned i Qnt sysg$il_ipf_set_intout_state_h;1 } sysg$r_ipf_set_intout_state_fields;- } sysg$r_ipf_set_intout_state_overla; char sysg$b_fill_4_ [4]; } SYSG; #if !defined(__VAXC);#define sysg$iq_kb_ucb sysg$r_kb_ucb_overlay.sysg$iq_kb_ucbT#define sysg$il_kb_ucb_l sysg$r_kb_ucb_overlay.sysg$r_kb_ucb_fields.sysg$il_kb_ucb_lT#define sysg$il_kb_ucb_h sysg$r_kb_ucb_overlay.sysg$r_kb_ucb_fields.sysg$il_kb_ucb_hD#define sysg$iq_mouse_ucb sysg$r_mouse_ucb_overlay.sysg$iq_mouse_uQcb`#define sysg$il_mouse_ucb_l sysg$r_mouse_ucb_overlay.sysg$r_mouse_ucb_fields.sysg$il_mouse_ucb_l`#define sysg$il_mouse_ucb_h sysg$r_mouse_ucb_overlay.sysg$r_mouse_ucb_fields.sysg$il_mouse_ucb_h>#define sysg$pq_ctb_ptr sysg$r_ctb_ptr_overlay.sysg$pq_ctb_ptrX#define sysg$pl_ctb_ptr_l sysg$r_ctb_ptr_overlay.sysg$r_ctb_ptr_fields.sysg$pl_ctb_ptr_lX#define sysg$il_ctb_ptr_h sysg$r_ctb_ptr_overlay.sysg$r_ctb_ptr_fields.sysg$il_ctb_ptr_hC#define sysg$il_ucb_config sysg$r_ucb_config_def.sysg$il_ucb_cQonfigb#define sysg$v_ucb_config_cons sysg$r_ucb_config_def.sysg$r_ucb_config_bits.sysg$v_ucb_config_consd#define sysg$v_ucb_config_pport sysg$r_ucb_config_def.sysg$r_ucb_config_bits.sysg$v_ucb_config_pportb#define sysg$v_ucb_config_kbio sysg$r_ucb_config_def.sysg$r_ucb_config_bits.sysg$v_ucb_config_kbio3#define sysg$il_flags sysg$r_flagsdef.sysg$il_flags_#define sysg$v_workstation_present sysg$r_flagsdef.sysg$r_flags_bits.sysg$v_workstation_presentW#define sysg$v_wind_sys_active sysg$r_flagsdQef.sysg$r_flags_bits.sysg$v_wind_sys_activeO#define sysg$v_alt_console sysg$r_flagsdef.sysg$r_flags_bits.sysg$v_alt_consoleY#define sysg$v_wind_sys_console sysg$r_flagsdef.sysg$r_flags_bits.sysg$v_wind_sys_consolea#define sysg$v_guest_console_active sysg$r_flagsdef.sysg$r_flags_bits.sysg$v_guest_console_activeR#define sysg$iq_opwin_updown_pd sysg$r_opwin_up_pd_overlay.sysg$iq_opwin_updown_pdJ#define sysg$iq_opwin_up_pd sysg$r_opwin_up_pd_overlay.sysg$iq_opwin_up_pdh#define sysg$il_opwin_up_pQd_l sysg$r_opwin_up_pd_overlay.sysg$r_opwin_up_pd_fields.sysg$il_opwin_up_pd_lh#define sysg$il_opwin_up_pd_h sysg$r_opwin_up_pd_overlay.sysg$r_opwin_up_pd_fields.sysg$il_opwin_up_pd_hT#define sysg$iq_opwin_resize_pd sysg$r_opwin_down_pd_overlay.sysg$iq_opwin_resize_pdP#define sysg$iq_opwin_down_pd sysg$r_opwin_down_pd_overlay.sysg$iq_opwin_down_pdp#define sysg$il_opwin_down_pd_l sysg$r_opwin_down_pd_overlay.sysg$r_opwin_down_pd_fields.sysg$il_opwin_down_pd_lp#define sysg$il_opwin_down_pd_h sysg$rQ_opwin_down_pd_overlay.sysg$r_opwin_down_pd_fields.sysg$il_opwin_down_pd_h=#define sysg$iq_unit_int sysg$r_unit_int_def.sysg$iq_unit_intL#define sysg$v_unit0_tx sysg$r_unit_int_def.sysg$r_unit_bits.sysg$v_unit0_txL#define sysg$v_unit0_rx sysg$r_unit_int_def.sysg$r_unit_bits.sysg$v_unit0_rxL#define sysg$v_unit1_tx sysg$r_unit_int_def.sysg$r_unit_bits.sysg$v_unit1_txL#define sysg$v_unit1_rx sysg$r_unit_int_def.sysg$r_unit_bits.sysg$v_unit1_rxL#define sysg$v_unit2_tx sysg$r_unit_int_def.sysg$r_uniQt_bits.sysg$v_unit2_txL#define sysg$v_unit2_rx sysg$r_unit_int_def.sysg$r_unit_bits.sysg$v_unit2_rxL#define sysg$v_unit3_tx sysg$r_unit_int_def.sysg$r_unit_bits.sysg$v_unit3_txL#define sysg$v_unit3_rx sysg$r_unit_int_def.sysg$r_unit_bits.sysg$v_unit3_rxL#define sysg$v_unit4_tx sysg$r_unit_int_def.sysg$r_unit_bits.sysg$v_unit4_txL#define sysg$v_unit4_rx sysg$r_unit_int_def.sysg$r_unit_bits.sysg$v_unit4_rxS#define sysg$iq_opwin_reset_pd sysg$r_opwin_reset_pd_overlay.sysg$iq_opwin_reset_pdt#definQe sysg$il_opwin_reset_pd_l sysg$r_opwin_reset_pd_overlay.sysg$r_opwin_reset_pd_fields.sysg$il_opwin_reset_pd_lt#define sysg$il_opwin_reset_pd_h sysg$r_opwin_reset_pd_overlay.sysg$r_opwin_reset_pd_fields.sysg$il_opwin_reset_pd_hP#define sysg$iq_opwin_puts_pd sysg$r_opwin_puts_pd_overlay.sysg$iq_opwin_puts_pdp#define sysg$il_opwin_puts_pd_l sysg$r_opwin_puts_pd_overlay.sysg$r_opwin_puts_pd_fields.sysg$il_opwin_puts_pd_lp#define sysg$il_opwin_puts_pd_h sysg$r_opwin_puts_pd_overlay.sysg$r_opwin_puts_pQd_fields.sysg$il_opwin_puts_pd_hY#define sysg$iq_opwin_visible_pd sysg$r_opwin_visible_pd_overlay.sysg$iq_opwin_visible_pd|#define sysg$il_opwin_visible_pd_l sysg$r_opwin_visible_pd_overlay.sysg$r_opwin_visible_pd_fields.sysg$il_opwin_visible_pd_l|#define sysg$il_opwin_visible_pd_h sysg$r_opwin_visible_pd_overlay.sysg$r_opwin_visible_pd_fields.sysg$il_opwin_visible_pd_hP#define sysg$iq_opwin_halt_pd sysg$r_opwin_halt_pd_overlay.sysg$iq_opwin_halt_pdp#define sysg$il_opwin_halt_pd_l sysg$r_opwin_hQalt_pd_overlay.sysg$r_opwin_halt_pd_fields.sysg$il_opwin_halt_pd_lp#define sysg$il_opwin_halt_pd_h sysg$r_opwin_halt_pd_overlay.sysg$r_opwin_halt_pd_fields.sysg$il_opwin_halt_pd_h\#define sysg$iq_opwin_continue_pd sysg$r_opwin_continue_pd_overlay.sysg$iq_opwin_continue_pd#define sysg$il_opwin_comtinue_pd_l sysg$r_opwin_continue_pd_overlay.sysg$r_opwin_continue_pd_fields.sysg$il_opwin_comtinue_pd_l#define sysg$il_opwin_continue_pd_h sysg$r_opwin_continue_pd_overlay.sysg$r_opwin_continue_pd_fieldsQ.sysg$il_opwin_continue_pd_hb#define sysg$iq_console_language_pd sysg$r_console_language_pd_overlay.sysg$iq_console_language_pd#define sysg$il_console_language_pd_l sysg$r_console_language_pd_overlay.sysg$r_console_language_pd_fields.sysg$il_console_language\_pd_l#define sysg$il_console_language_pd_h sysg$r_console_language_pd_overlay.sysg$r_console_language_pd_fields.sysg$il_console_language\_pd_hG#define sysg$iq_kbd_getc_pd sysg$r_kbd_getc_overlay.sysg$iq_kbd_getc_pdb#define sysg$il_kbQd_getc_pd_l sysg$r_kbd_getc_overlay.sysg$r_kbd_getc_fields.sysg$il_kbd_getc_pd_lb#define sysg$il_kbd_getc_pd_h sysg$r_kbd_getc_overlay.sysg$r_kbd_getc_fields.sysg$il_kbd_getc_pd_hZ#define sysg$l_ipf_console_flags sysg$r_ifp_console_flags_overlay.sysg$l_ipf_console_flagsy#define sysg$v_ipf_console_polled sysg$r_ifp_console_flags_overlay.sysg$r_ipf_console_flag_bits.sysg$v_ipf_console_polled}#define sysg$v_ipf_con_polled_input sysg$r_ifp_console_flags_overlay.sysg$r_ipf_console_flag_bits.sysg$v_ipfQ_con_polled_input#define sysg$v_ipf_con_polled_output sysg$r_ifp_console_flags_overlay.sysg$r_ipf_console_flag_bits.sysg$v_ipf_con_polled_output#define sysg$v_ipf_setchar_supported sysg$r_ifp_console_flags_overlay.sysg$r_ipf_console_flag_bits.sysg$v_ipf_setchar_supported#define sysg$v_ipf_interrupts_allowed sysg$r_ifp_console_flags_overlay.sysg$r_ipf_console_flag_bits.sysg$v_ipf_interrupts_alloweds#define sysg$v_ipf_vga_console sysg$r_ifp_console_flags_overlay.sysg$r_ipf_console_flag_bits.sQysg$v_ipf_vga_consoleP#define sysg$iq_ipf_conin_ucb sysg$r_ipf_conin_ucb_overlay.sysg$iq_ipf_conin_ucbp#define sysg$il_ipf_conin_ucb_l sysg$r_ipf_conin_ucb_overlay.sysg$r_ipf_conin_ucb_fields.sysg$il_ipf_conin_ucb_lp#define sysg$il_ipf_conin_ucb_h sysg$r_ipf_conin_ucb_overlay.sysg$r_ipf_conin_ucb_fields.sysg$il_ipf_conin_ucb_hS#define sysg$iq_ipf_conout_ucb sysg$r_ipf_conout_ucb_overlay.sysg$iq_ipf_conout_ucbt#define sysg$il_ipf_conout_ucb_l sysg$r_ipf_conout_ucb_overlay.sysg$r_ipf_conout_ucb_fQields.sysg$il_ipf_conout_ucb_lt#define sysg$il_ipf_conout_ucb_h sysg$r_ipf_conout_ucb_overlay.sysg$r_ipf_conout_ucb_fields.sysg$il_ipf_conout_ucb_hV#define sysg$iq_ipf_setchar_ucb sysg$r_ipf_setchar_ucb_overlay.sysg$iq_ipf_setchar_ucbx#define sysg$il_ipf_setchar_ucb_l sysg$r_ipf_setchar_ucb_overlay.sysg$r_ipf_setchar_ucb_fields.sysg$il_ipf_setchar_ucb_lx#define sysg$il_ipf_setchar_ucb_h sysg$r_ipf_setchar_ucb_overlay.sysg$r_ipf_setchar_ucb_fields.sysg$il_ipf_setchar_ucb_hP#define sysg$iq_ipf_con_Qintin sysg$r_ipf_con_intin_overlay.sysg$iq_ipf_con_intinp#define sysg$il_ipf_con_intin_l sysg$r_ipf_con_intin_overlay.sysg$r_ipf_con_intin_fields.sysg$il_ipf_con_intin_lp#define sysg$il_ipf_con_intin_h sysg$r_ipf_con_intin_overlay.sysg$r_ipf_con_intin_fields.sysg$il_ipf_con_intin_hS#define sysg$iq_ipf_con_intout sysg$r_ipf_con_intout_overlay.sysg$iq_ipf_con_intoutt#define sysg$il_ipf_con_intout_l sysg$r_ipf_con_intout_overlay.sysg$r_ipf_con_intout_fields.sysg$il_ipf_con_intout_lt#define sysg$il_Qipf_con_intout_h sysg$r_ipf_con_intout_overlay.sysg$r_ipf_con_intout_fields.sysg$il_ipf_con_intout_hV#define sysg$iq_ipf_con_getchar sysg$r_ipf_con_getchar_overlay.sysg$iq_ipf_con_getcharx#define sysg$il_ipf_con_getchar_l sysg$r_ipf_con_getchar_overlay.sysg$r_ipf_con_getchar_fields.sysg$il_ipf_con_getchar_lx#define sysg$il_ipf_con_getchar_h sysg$r_ipf_con_getchar_overlay.sysg$r_ipf_con_getchar_fields.sysg$il_ipf_con_getchar_hV#define sysg$iq_ipf_con_outchar sysg$r_ipf_con_putchar_overlay.sysg$iq_iQpf_con_outcharx#define sysg$il_ipf_con_putchar_l sysg$r_ipf_con_putchar_overlay.sysg$r_ipf_con_putchar_fields.sysg$il_ipf_con_putchar_lx#define sysg$il_ipf_con_putchar_h sysg$r_ipf_con_putchar_overlay.sysg$r_ipf_con_putchar_fields.sysg$il_ipf_con_putchar_hV#define sysg$iq_ipf_con_setchar sysg$r_ipf_con_setchar_overlay.sysg$iq_ipf_con_setcharx#define sysg$il_ipf_con_setchar_l sysg$r_ipf_con_setchar_overlay.sysg$r_ipf_con_setchar_fields.sysg$il_ipf_con_setchar_lx#define sysg$il_ipf_con_setchar_h syQsg$r_ipf_con_setchar_overlay.sysg$r_ipf_con_setchar_fields.sysg$il_ipf_con_setchar_hb#define sysg$iq_ipf_set_intin_state sysg$r_ipf_set_intin_state_overlay.sysg$iq_ipf_set_intin_state#define sysg$il_ipf_set_intin_state_l sysg$r_ipf_set_intin_state_overlay.sysg$r_ipf_set_intin_state_fields.sysg$il_ipf_set_intin_st\ate_l#define sysg$il_ipf_set_intin_state_h sysg$r_ipf_set_intin_state_overlay.sysg$r_ipf_set_intin_state_fields.sysg$il_ipf_set_intin_st\ate_hd#define sysg$iq_ipf_set_intout_state Q sysg$r_ipf_set_intout_state_overla.sysg$iq_ipf_set_intout_state#define sysg$il_ipf_set_intout_state_l sysg$r_ipf_set_intout_state_overla.sysg$r_ipf_set_intout_state_fields.sysg$il_ipf_set_intout\_state_l#define sysg$il_ipf_set_intout_state_h sysg$r_ipf_set_intout_state_overla.sysg$r_ipf_set_intout_state_fields.sysg$il_ipf_set_intout\_state_h"#endif /* #if !defined(__VAXC) */ N#define SYSG$K_LENGTH 240 /* Length */N#define SYSG$C_LENGTH 240 Q /* Length (with a C!) */N#define S_SYSG$ 240 /* Old size name - synonym */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SYSGDEF_LOADED */ ww[UM/***********************Q****************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise DeQvelopment, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **Q/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:17 by OpenVMS SDL V3.7 */I/* Source: 12-OCT-2021 13:20:46 $1$DGA8345:[LIB_H.SRC]MDBOOTDEF.SDL;1 *//********************************************************************* Q***********************************************************//*** MODULE $SYSMDDEF ***/#ifndef __SYSMDDEF_LOADED#define __SYSMDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __shQort /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ Q */N/* */N/* System Memory disk data block: a copy of the contents of SYS$MD.FID */O/* for use when connecting to the memory disk container file during SYSINIT. */N/* */N/*- */ N#define SYSMD$C_LENGTH 24 Q /* Length of structure (rounded up) */ typedef struct _sysmd {N unsigned short int sysmd$w_orig_unitnum; /* Unit number from SYS$MD.FID */k unsigned short int sysmd$w_used_unitnum; /* Unit number from LD CONNECT if original is not available */b unsigned short int sysmd$w_controller; /* Controller letter for memory disk (should be 'M') */^ unsigned short int sysmd$w_alloclass; /* Allocation class to be used (from system disk) */N unsigned short int sysmd$w_size; Q /* Structure size */N unsigned char sysmd$b_type; /* Structure type (DYN$C_MISC) */N unsigned char sysmd$b_subtype; /* Structure subtype (DYN$C_SYSMD) */N unsigned int sysmd$l_spare; /* Spare */S char sysmd$t_info [8]; /* Start of ASCIZ string from SYS$MD.FID */ } SYSMD; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported Q*/b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __SYSMDDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard EnQterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., andQ is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************* Q*******************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */I/* Source: 13-MAY-2024 12:22:02 $1$DGA8345:[LIB_H.SRC]SYSPARDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $SYSPARDEF ***/#ifndef __SYSPARDEF_LOADED#define __SYSPARDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignQment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif Q#ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif [#define ACP$S_DATACHK 1 /* Old size name, synonym for ACP$S_SYS_DATACHK */ Ntypedef struct _sys_datachk { /* Definition for ACP$GB_DATACHK */ __union { char acp$b_bits; __struct {N Qunsigned acp$v_readchk : 1; /* do datachecks on reads */N unsigned acp$v_writechk : 1; /* do datachecks on writes */' unsigned acp$v_fill_2_ : 6; } acp$r_fill_1_; } acp$r_fill_0_; } SYS_DATACHK; #if !defined(__VAXC)?#define acp$v_readchk acp$r_fill_0_.acp$r_fill_1_.acp$v_readchkA#define acp$v_writechk acp$r_fill_0_.acp$r_fill_1_.acp$v_writechk"#endif /* #if !defined(__VAXC) */ ]#define ACP$S_SWAPFLAGS 1 Q/* Old size name, synonym for ACP$S_SYS_SWAPFLAGS */ Ntypedef struct _sys_swapflags { /* Definition for ACP$GB_SWAPFLGS */ __union { char acp$b_bits; __struct {N unsigned acp$v_swapsys : 1; /* /SYSTEM */N unsigned acp$v_swapgrp : 1; /* /GROUP */N unsigned acp$v_swapprv : 1; /* other (private mount) */N unsigned acp$v_swapmag : 1; /* magtape Q */' unsigned acp$v_fill_5_ : 4; } acp$r_fill_4_; } acp$r_fill_3_; } SYS_SWAPFLAGS; #if !defined(__VAXC)?#define acp$v_swapsys acp$r_fill_3_.acp$r_fill_4_.acp$v_swapsys?#define acp$v_swapgrp acp$r_fill_3_.acp$r_fill_4_.acp$v_swapgrp?#define acp$v_swapprv acp$r_fill_3_.acp$r_fill_4_.acp$v_swapprv?#define acp$v_swapmag acp$r_fill_3_.acp$r_fill_4_.acp$v_swapmag"#endif /* #if !defined(__VAXC) */ ]#define CLU$S_SGN_FLAGS 4 Q /* Old size name, synonym for CLU$S_SYS_SGN_FLAGS */ Ntypedef struct _sys_sgn_flags { /* Definition for CLU$GL_SGN_FLAGS */ __union {M int clu$l_bits; /* Bit Definition */ __struct {N unsigned clu$v_niscs_load_pea0 : 1; /* <0> Load PEA0 for NISCS */Z unsigned clu$v_niscs_conv_boot : 1; /* <1> Allow remote conversational boot */N unsigned clu$v_niscs_use_lan : 1; /* <2> Allow NISCS use of LA QN */N unsigned clu$v_niscs_use_udp : 1; /* <3> Allow NISCS use of UDP */' unsigned clu$v_fill_8_ : 4; } clu$r_fill_7_; } clu$r_fill_6_; } SYS_SGN_FLAGS; #if !defined(__VAXC)O#define clu$v_niscs_load_pea0 clu$r_fill_6_.clu$r_fill_7_.clu$v_niscs_load_pea0O#define clu$v_niscs_conv_boot clu$r_fill_6_.clu$r_fill_7_.clu$v_niscs_conv_bootK#define clu$v_niscs_use_lan clu$r_fill_6_.clu$r_fill_7_.clu$v_niscs_use_lanK#define clu$v_niscs_use_udp clu$ Rr_fill_6_.clu$r_fill_7_.clu$v_niscs_use_udp"#endif /* #if !defined(__VAXC) */ #define EXE$M_FATAL_BUG 0x100X#define EXE$S_FLAGS 4 /* Old size name, synonym for EXE$S_SYS_FLAGS */ Ntypedef struct _sys_flags { /* DEFINITION FOR EXE$GL_FLAGS */ __union { int exe$l_bits; __struct {T unsigned exe$v_syswrtabl : 1; /* LEAVE SYSTEM READ ONLY CODE WRITABLE */Q unsigned exe$v_noautocnf : 1; /* NO AUTOMATIC CONFIGRURATION OF UBA */N unsigned exe$v_poolpging : 1; /* ENABLE DYNAMIC POOL PAGING */N unsigned exe$v_simulator : 1; /* RUNNING ON SIMULATOR */N unsigned exe$v_crdenabl : 1; /* ENABLE CRD ERROR DETECTION */N unsigned exe$v_sbierr : 1; /* ENABLE SBI ERROR INTERRUPT */N unsigned exe$v_init : 1; /* RMS AND FILE SYSTEM INITIALIZED */N unsigned exe$v_settime : 1; /* FORCE SOLICITATION OF TIME */N R unsigned exe$v_fatal_bug : 1; /* FORCE ALL BUG CHECKS FATAL */N unsigned exe$v_multacp : 1; /* USE MULTIPLE FILE ACP'S */N unsigned exe$v_nocluster : 1; /* TURN OFF PAGE FAULT CLUSTERING */N unsigned exe$v_bugreboot : 1; /* AUTO REBOOT ON BUGCHECK */Q unsigned exe$v_sysuafalt : 1; /* ALTERNATE LOGICAL NAME FOR SYSUAF */Q unsigned exe$v_shrf11acp : 1; /* MAKE F11ACP SHARABLE AT BOOT TIME */N unsigned exeR$v_bugdump : 1; /* TAKE SYSTEM DUMP ON BUGCHECK */P unsigned exe$v_resalloc : 1; /* ENABLE RESOURCE ALLOCATION CHECKS */O unsigned exe$v_concealed : 1; /* ENABLE USE OF CONCEALED DEVICES */S unsigned exe$v_ssinhibit : 1; /* INHIBIT SYSTEM SERVICES PER-PROCESS */R unsigned exe$v_explicitp : 1; /* IF SET TODAY IS CONSIDERED PRIMARY */T unsigned exe$v_explicits : 1; /* IF SET TODAY IS CONSIDERED SECONDARY */U unsigned exe$v_pgfRlfrag : 1; /* SET IF PAGE FILE FRAGMENTED MSG ISSUED */O unsigned exe$v_pgflcrit : 1; /* SET IF PAGE FILE FULL MSG ISSUED */U unsigned exe$v_tbchk : 1; /* SET IF PROCESSOR REGISTER TBCHK PRESENT */N unsigned exe$v_pagfildmp : 1; /* SET IF DUMP IS IN PAGE FILE */N unsigned exe$v_savedump : 1; /* SET TO SAVE DUMP UNTIL ANALYZED */N unsigned exe$v_jobqueues : 1; /* Set if JOBCTL to enable queues */W unsigned exe$v_reinitque : R 1; /* Set if JOBCTL to reinitialize JBCSYSQUE */R unsigned exe$v_wlksysdsk : 1; /* Set if system disk is write locked */N unsigned exe$v_poweroff : 1; /* Enable software power-off */N unsigned exe$v_virtual_machine : 1; /* Running on HPVM */( unsigned exe$v_fill_11_ : 2; } exe$r_fill_10_; } exe$r_fill_9_; } SYS_FLAGS; #if !defined(__VAXC)D#define exe$v_syswrtabl exe$r_fill_9_.exe$r_fill_10_.exe$v_syswrta RblD#define exe$v_noautocnf exe$r_fill_9_.exe$r_fill_10_.exe$v_noautocnfD#define exe$v_poolpging exe$r_fill_9_.exe$r_fill_10_.exe$v_poolpgingD#define exe$v_simulator exe$r_fill_9_.exe$r_fill_10_.exe$v_simulatorB#define exe$v_crdenabl exe$r_fill_9_.exe$r_fill_10_.exe$v_crdenabl>#define exe$v_sbierr exe$r_fill_9_.exe$r_fill_10_.exe$v_sbierr:#define exe$v_init exe$r_fill_9_.exe$r_fill_10_.exe$v_init@#define exe$v_settime exe$r_fill_9_.exe$r_fill_10_.exe$v_settimeD#define exe$v_fatal_bug exe$r_fillR_9_.exe$r_fill_10_.exe$v_fatal_bug@#define exe$v_multacp exe$r_fill_9_.exe$r_fill_10_.exe$v_multacpD#define exe$v_nocluster exe$r_fill_9_.exe$r_fill_10_.exe$v_noclusterD#define exe$v_bugreboot exe$r_fill_9_.exe$r_fill_10_.exe$v_bugrebootD#define exe$v_sysuafalt exe$r_fill_9_.exe$r_fill_10_.exe$v_sysuafaltD#define exe$v_shrf11acp exe$r_fill_9_.exe$r_fill_10_.exe$v_shrf11acp@#define exe$v_bugdump exe$r_fill_9_.exe$r_fill_10_.exe$v_bugdumpB#define exe$v_resalloc exe$r_fill_9_.exe$r_fill_10_.exe$v_ RresallocD#define exe$v_concealed exe$r_fill_9_.exe$r_fill_10_.exe$v_concealedD#define exe$v_ssinhibit exe$r_fill_9_.exe$r_fill_10_.exe$v_ssinhibitD#define exe$v_explicitp exe$r_fill_9_.exe$r_fill_10_.exe$v_explicitpD#define exe$v_explicits exe$r_fill_9_.exe$r_fill_10_.exe$v_explicitsB#define exe$v_pgflfrag exe$r_fill_9_.exe$r_fill_10_.exe$v_pgflfragB#define exe$v_pgflcrit exe$r_fill_9_.exe$r_fill_10_.exe$v_pgflcrit<#define exe$v_tbchk exe$r_fill_9_.exe$r_fill_10_.exe$v_tbchkD#define exe$v_pagf Rildmp exe$r_fill_9_.exe$r_fill_10_.exe$v_pagfildmpB#define exe$v_savedump exe$r_fill_9_.exe$r_fill_10_.exe$v_savedumpD#define exe$v_jobqueues exe$r_fill_9_.exe$r_fill_10_.exe$v_jobqueuesD#define exe$v_reinitque exe$r_fill_9_.exe$r_fill_10_.exe$v_reinitqueD#define exe$v_wlksysdsk exe$r_fill_9_.exe$r_fill_10_.exe$v_wlksysdskB#define exe$v_poweroff exe$r_fill_9_.exe$r_fill_10_.exe$v_poweroffP#define exe$v_virtual_machine exe$r_fill_9_.exe$r_fill_10_.exe$v_virtual_machine"#endif /* #if !defined(__ RVAXC) */ #define EXE$M_NOCLOCK 0x1#define EXE$M_NOSMPSANITY 0x2#define EXE$M_NOSPINWAIT 0x4#define EXE$M_SPCTL_BIT_3 0x8#define EXE$M_SPCTL_BIT_4 0x10_#define EXE$S_TIME_CONTROL 4 /* Old size name, synonym for EXE$S_SYS_TIME_CONTROL */ Ptypedef struct _sys_time_control { /* DEFINITION FOR EXE$GL_TIME_CONTROL */ __union { int exe$l_bits; __struct {N unsigned exe$v_noclock : 1; /* DO NOT TURN ON CLOCK */S R unsigned exe$v_nosmpsanity : 1; /* DISABLE SMP SANITY TIMER TIMEOUTS */S unsigned exe$v_nospinwait : 1; /* DISABLE SMP SPIN/BUSYWAIT TIMEOUTS */^ unsigned exe$v_spctl_bit_3 : 1; /* SPECIAL CONTROL BITS FOR BBW_ROUTINES_DS1287 */N unsigned exe$v_spctl_bit_4 : 1; /* AND POSSIBLY TIMESCHDL */( unsigned exe$v_fill_14_ : 3; } exe$r_fill_13_; } exe$r_fill_12_; } SYS_TIME_CONTROL; #if !defined(__VAXC)A#define exe$v_ Rnoclock exe$r_fill_12_.exe$r_fill_13_.exe$v_noclockI#define exe$v_nosmpsanity exe$r_fill_12_.exe$r_fill_13_.exe$v_nosmpsanityG#define exe$v_nospinwait exe$r_fill_12_.exe$r_fill_13_.exe$v_nospinwaitI#define exe$v_spctl_bit_3 exe$r_fill_12_.exe$r_fill_13_.exe$v_spctl_bit_3I#define exe$v_spctl_bit_4 exe$r_fill_12_.exe$r_fill_13_.exe$v_spctl_bit_4"#endif /* #if !defined(__VAXC) */ !#define EXE$M_SYSSER_LOGGING 0x80`#define EXE$S_DYNAMIC_FLAGS 4 /* Old size name, synonym for EXE$ RS_SYS_DYNAMIC_FLAGS */ Qtypedef struct _sys_dynamic_flags { /* DEFINITION FOR EXE$GL_DYNAMIC_FLAGS */ __union { int exe$l_bits; __struct {Z unsigned exe$v_class_prot : 1; /* Do non-discretionary classification check */h unsigned exe$v_writesysparams : 1; /* Write the active parameters to the system .PAR file */Y unsigned exe$v_brk_term : 1; /* Associate on terminal in breakin detection */Q unsigned exe$v_brk_disuser : R 1; /* Disable user account on breakin */Q unsigned exe$v_nopgflswp : 1; /* Disallow swapping into page files */_ unsigned exe$v_load_pwd_policy : 1; /* Load site-specific password change policy */_ unsigned exe$v_persistent_res : 1; /* Enable Fibre SCSI Persistent reservations. */R unsigned exe$v_sysser_logging : 1; /* Enable system service logging */ } exe$r_fill_16_; } exe$r_fill_15_; } SYS_DYNAMIC_FLAGS; #if !defRined(__VAXC)G#define exe$v_class_prot exe$r_fill_15_.exe$r_fill_16_.exe$v_class_protO#define exe$v_writesysparams exe$r_fill_15_.exe$r_fill_16_.exe$v_writesysparamsC#define exe$v_brk_term exe$r_fill_15_.exe$r_fill_16_.exe$v_brk_termI#define exe$v_brk_disuser exe$r_fill_15_.exe$r_fill_16_.exe$v_brk_disuserE#define exe$v_nopgflswp exe$r_fill_15_.exe$r_fill_16_.exe$v_nopgflswpQ#define exe$v_load_pwd_policy exe$r_fill_15_.exe$r_fill_16_.exe$v_load_pwd_policyO#define exe$v_persistent_res exe$r R_fill_15_.exe$r_fill_16_.exe$v_persistent_resO#define exe$v_sysser_logging exe$r_fill_15_.exe$r_fill_16_.exe$v_sysser_logging"#endif /* #if !defined(__VAXC) */ #define EXE$M_SSI_ENABLE 0x10_#define EXE$S_STATIC_FLAGS 4 /* Old size name, synonym for EXE$S_SYS_STATIC_FLAGS */ Ptypedef struct _sys_static_flags { /* DEFINITION FOR EXE$GL_STATIC_FLAGS */ __union { int exe$l_bits; __struct {N unsigned exe$v_xqp_resident : 1; /* MEMORY R RESIDENT XQP */O unsigned exe$v_rebldsysd : 1; /* REBUILD SYSTEM DISK IN SYSMOUNT */N unsigned exe$v_obsshad : 1; /* Skip obsolete SHADOWING bit */Y unsigned exe$v_sa_app : 1; /* Booting stand-alone application (SA-BACKUP) */Z unsigned exe$v_ssi_enable : 1; /* Enable system service interception on I64 */( unsigned exe$v_fill_19_ : 3; } exe$r_fill_18_; } exe$r_fill_17_; } SYS_STATIC_FLAGS; #if R!defined(__VAXC)K#define exe$v_xqp_resident exe$r_fill_17_.exe$r_fill_18_.exe$v_xqp_residentE#define exe$v_rebldsysd exe$r_fill_17_.exe$r_fill_18_.exe$v_rebldsysdA#define exe$v_obsshad exe$r_fill_17_.exe$r_fill_18_.exe$v_obsshad?#define exe$v_sa_app exe$r_fill_17_.exe$r_fill_18_.exe$v_sa_appG#define exe$v_ssi_enable exe$r_fill_17_.exe$r_fill_18_.exe$v_ssi_enable"#endif /* #if !defined(__VAXC) */ #define EXE$M_MOUNTMSG 0x1#define EXE$M_DISMOUMSG 0x2[#define EXE$S_MSGFLAGS 4 R /* Old size name, synonym for EXE$S_SYS_MSGFLAGS */ Ntypedef struct _sys_msgflags { /* DEFINITION FOR EXE$GL_MSGFLAGS */ __union { int exe$l_bits; __struct {N unsigned exe$v_mountmsg : 1; /* ENABLE MOUNT NOTIFICATION */N unsigned exe$v_dismoumsg : 1; /* ENABLE DISMOUNT NOTIFICATION */( unsigned exe$v_fill_22_ : 6; } exe$r_fill_21_; } exe$r_fill_20_; } SYS_MSGFLAGS; #if !def Rined(__VAXC)C#define exe$v_mountmsg exe$r_fill_20_.exe$r_fill_21_.exe$v_mountmsgE#define exe$v_dismoumsg exe$r_fill_20_.exe$r_fill_21_.exe$v_dismoumsg"#endif /* #if !defined(__VAXC) */ Z#define EXE$S_WSFLAGS 4 /* Old size name, synonym for EXE$S_SYS_WSFLAGS */ Ntypedef struct _sys_wsflags { /* DEFINITION FOR EXE$GL_WSFLAGS */ __union { int exe$l_bits; __struct {N unsigned exe$v_opa0 : 1; /* Reserve a window for OPA0 R */( unsigned exe$v_fill_25_ : 7; } exe$r_fill_24_; } exe$r_fill_23_; } SYS_WSFLAGS; #if !defined(__VAXC);#define exe$v_opa0 exe$r_fill_23_.exe$r_fill_24_.exe$v_opa0"#endif /* #if !defined(__VAXC) */ \#define SGN$S_LOADFLAGS 4 /* Old size name, synonym for SGN$S_SYS_LOADFLAGS */ Ntypedef struct _sys_loadflags { /* DEFINITION FOR SGN$GL_LOADFLAGS */ __union { int sgn$l_bits; __struct {R R unsigned sgn$v_load_sys_images : 1; /* Alternate load system images */N unsigned sgn$v_exec_slicing : 1; /* Slice system images */P unsigned sgn$v_release_pfns : 1; /* Release PFNs in the huge page */( unsigned sgn$v_fill_28_ : 5; } sgn$r_fill_27_; } sgn$r_fill_26_; } SYS_LOADFLAGS; #if !defined(__VAXC)Q#define sgn$v_load_sys_images sgn$r_fill_26_.sgn$r_fill_27_.sgn$v_load_sys_imagesK#define sgn$v_exec_slicing sgnR$r_fill_26_.sgn$r_fill_27_.sgn$v_exec_slicingK#define sgn$v_release_pfns sgn$r_fill_26_.sgn$r_fill_27_.sgn$v_release_pfns"#endif /* #if !defined(__VAXC) */ #define SGN$M_SDH 0x1#define SGN$M_EVENT_MSG_MAJ 0x2#define SGN$M_EVENT_MSG_ALL 0x4#define SGN$M_UNI_V30 0x8#define SGN$M_UNI_V31 0x10##define SGN$M_DISABLE_GBE_AUTO 0x20##define SGN$M_ENABLE_GBE_JUMBO 0x40"#define SGN$M_ENABLE_MORE_RCV 0x80$#define SGN$M_DISABLE_FLOW_CTL 0x100 #define SGN$M_BANDWIDTH_MB 0xE00&#define RSGN$M_ENABLE_FAST_TIMER 0x1000&#define SGN$M_DEFAULT_XMT_ERROR 0x2000'#define SGN$M_PORT_USABLE_ALWAYS 0x4000##define SGN$M_PORT_USABLE_UP 0x8000$#define SGN$M_DISABLE_ERRLOG 0x10000##define SGN$M_VCI_LIMIT_OFF 0x20000 #define SGN$M_RESERVED2 0x3C0000!#define SGN$M_FORCE_IPCI 0x400000'#define SGN$M_ENABLE_DEBUG_MSG 0x800000'#define SGN$M_STOP_TRACE_FULL 0x1000000(#define SGN$M_ENABLE_ALT_FUNC2 0x2000000(#define SGN$M_ENABLE_ALT_FUNC3 0x4000000'#define SGN$M_DISABLE_MAP_REG 0x8000000 R(#define SGN$M_DISABLE_ALL_MSG 0x10000000*#define SGN$M_ENABLE_DEBUG_MODE 0x20000000)#define SGN$M_ENABLE_ALL_TRACE 0x40000000'#define SGN$M_ENABLE_ALL_MSG 0x80000000\#define SGN$S_LAN_FLAGS 4 /* Old size name, synonym for SGN$S_SYS_LAN_FLAGS */ Ntypedef struct _sgn_lan_flags { /* Definition for SGN$GL_LAN_FLAGS */ __union { int sgn$l_bits; __struct {S unsigned sgn$v_sdh : 1; /* 00000001 0 ATM device is in SDH mode */n R unsigned sgn$v_event_msg_maj : 1; /* 00000002 1 Enable a subset of the ATM/NIPG event messages */b unsigned sgn$v_event_msg_all : 1; /* 00000004 2 Enable all ATM/NIPG event messages */P unsigned sgn$v_uni_v30 : 1; /* 00000008 3 Enable UNI version 3.0 */` unsigned sgn$v_uni_v31 : 1; /* 00000010 4 Enable UNI version 3.1 (overrides 3.0) */` unsigned sgn$v_disable_gbe_auto : 1; /* 00000020 5 Disable GBE autoconfiguration */a unsignedR sgn$v_enable_gbe_jumbo : 1; /* 00000040 6 Enable GBE use of jumbo frames */] unsigned sgn$v_enable_more_rcv : 1; /* 00000080 7 Enable more receive buffers */W unsigned sgn$v_disable_flow_ctl : 1; /* 00000100 8 Disable flow control */Q unsigned sgn$v_bandwidth_mb : 3; /* 00000E00 9,10,11 BW size bits */^ unsigned sgn$v_enable_fast_timer : 1; /* 00001000 12 Enable fast transmit timer */r unsigned sgn$v_default_xmt_error : 1; /* 0000200R0 13 Default to transmit error on aborted transmits */i unsigned sgn$v_port_usable_always : 1; /* 00004000 14 Report port usable after enable_port */` unsigned sgn$v_port_usable_up : 1; /* 00008000 15 Report port usable when link up */Z unsigned sgn$v_disable_errlog : 1; /* 00010000 16 Disable LAN error logging */N unsigned sgn$v_vci_limit_off : 1; /* 00020000 17 VCI limit off */N unsigned sgn$v_reserved2 : 4; /* 003C0000 18..21 Unused bitsR */N unsigned sgn$v_force_ipci : 1; /* 00400000 22 Force use of IPCI */X unsigned sgn$v_enable_debug_msg : 1; /* 00800000 23 Enable debug messages */_ unsigned sgn$v_stop_trace_full : 1; /* 01000000 24 Stop tracing when buffer full */d unsigned sgn$v_enable_alt_func2 : 1; /* 02000000 25 Enable alternate functionality #2 */d unsigned sgn$v_enable_alt_func3 : 1; /* 04000000 26 Enable alternate functionality #3 */^ unsigned sgn$v R_disable_map_reg : 1; /* 08000000 27 Disable use of map registers */V unsigned sgn$v_disable_all_msg : 1; /* 10000000 28 Disable all messages */U unsigned sgn$v_enable_debug_mode : 1; /* 20000000 29 Enable debug mode */U unsigned sgn$v_enable_all_trace : 1; /* 40000000 30 Enable all tracing */T unsigned sgn$v_enable_all_msg : 1; /* 80000000 31 Enable all messages */ } sgn$r_fill_30_; } sgn$r_fill_29_; } SGN_LAN_FLAGS; R#if !defined(__VAXC)9#define sgn$v_sdh sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_sdhM#define sgn$v_event_msg_maj sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_event_msg_majM#define sgn$v_event_msg_all sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_event_msg_allA#define sgn$v_uni_v30 sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_uni_v30A#define sgn$v_uni_v31 sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_uni_v31S#define sgn$v_disable_gbe_auto sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_disable_gbe_autoS#define sgn$v_enable_gbe_jumbo sgn$r_fill_ R29_.sgn$r_fill_30_.sgn$v_enable_gbe_jumboQ#define sgn$v_enable_more_rcv sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_enable_more_rcvS#define sgn$v_disable_flow_ctl sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_disable_flow_ctlK#define sgn$v_bandwidth_mb sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_bandwidth_mbU#define sgn$v_enable_fast_timer sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_enable_fast_timerU#define sgn$v_default_xmt_error sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_default_xmt_errorW#define sgn$v_port_usable_always sgn$r!R_fill_29_.sgn$r_fill_30_.sgn$v_port_usable_alwaysO#define sgn$v_port_usable_up sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_port_usable_upO#define sgn$v_disable_errlog sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_disable_errlogM#define sgn$v_vci_limit_off sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_vci_limit_offE#define sgn$v_reserved2 sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_reserved2G#define sgn$v_force_ipci sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_force_ipciS#define sgn$v_enable_debug_msg sgn$r_fill_29_.sgn$r_fill_30_.sgn"R$v_enable_debug_msgQ#define sgn$v_stop_trace_full sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_stop_trace_fullS#define sgn$v_enable_alt_func2 sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_enable_alt_func2S#define sgn$v_enable_alt_func3 sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_enable_alt_func3Q#define sgn$v_disable_map_reg sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_disable_map_regQ#define sgn$v_disable_all_msg sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_disable_all_msgU#define sgn$v_enable_debug_mode sgn$r_fill_29_.sgn$r_fill_30 #R_.sgn$v_enable_debug_modeS#define sgn$v_enable_all_trace sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_enable_all_traceO#define sgn$v_enable_all_msg sgn$r_fill_29_.sgn$r_fill_30_.sgn$v_enable_all_msg"#endif /* #if !defined(__VAXC) */ N/* */N/* values for sysgen parameter: SGN$GL_GALAXY */N/* */#define GLX$C_NOJOIN 0#defin$Re GLX$C_JOIN_NOW 1#define GLX$C_JOIN_LATER 2$#define EXE$M_CLASS_SCHED_ACTIVE 0x1 Otypedef struct _sys_sched_flags { /* DEFINITION FOR EXE$GL_SCHED_FLAGS */ __union { int exe$l_bits; __struct {S unsigned exe$v_class_sched_active : 1; /* Class scheduling is active */( unsigned exe$v_fill_33_ : 7; } exe$r_fill_32_; } exe$r_fill_31_; } SYS_SCHED_FLAGS; #if !defined(__VAXC)W#define exe$v_class_sched_active%R exe$r_fill_31_.exe$r_fill_32_.exe$v_class_sched_active"#endif /* #if !defined(__VAXC) */ #define EXE$M_XSAVEOPT 0x1#define EXE$M_FSGSBASE 0x2#define EXE$M_MDS 0x4#define EXE$C_NUM_X86_FT 3 Rtypedef struct _sys_disable_x86_ft { /* DEFINITION FOR EXE$GL_DISABLE_X86_FT */ __union { int exe$l_bits; __struct {X unsigned exe$v_xsaveopt : 1; /* Set = disable use of XSAVEOPT instruction */c unsigned exe$v_fsgsbase : 1; /* Set = disable &Ruse of [RD/WR][FS/GS]BASE instructions */N unsigned exe$v_mds : 1; /* Set = disable MDS Mitigation */( unsigned exe$v_fill_36_ : 5; } exe$r_fill_35_; } exe$r_fill_34_; } SYS_DISABLE_X86_FT; #if !defined(__VAXC)C#define exe$v_xsaveopt exe$r_fill_34_.exe$r_fill_35_.exe$v_xsaveoptC#define exe$v_fsgsbase exe$r_fill_34_.exe$r_fill_35_.exe$v_fsgsbase9#define exe$v_mds exe$r_fill_34_.exe$r_fill_35_.exe$v_mds"#endif /* #if !defined(__'RVAXC) */  P // Define the names of the features, so that we can report missing features.W // Also define the order in which to consider disabling features to find a matching> // variant. More important features should be listed later#define GEN_X86_FT_CONSTS \0 const char* ft_name[EXE$C_NUM_X86_FT] = { \ "XSAVEOPT", \ "FSGSBASE", \ "MDS"}; \ \0 const int ft_order[EXE$C_NUM_X86_FT] = { \0 1, /* FSGSBASE - modest performance impact */ \/ 0(R, /* XSAVEOPT - large performance impact */ \ 2 /* MDS - mitigation */ \ }; #define SGN$M_PKQ_FP_DISABLE 0x1 #define SGN$M_FGE_FP_DISABLE 0x2 #define SGN$M_PKA_FP_DISABLE 0x4 #define SGN$M_LAN_FP_DISABLE 0x8!#define SGN$M_PKR_FP_DISABLE 0x10!#define SGN$M_PKM_FP_DISABLE 0x20!#define SGN$M_PGQ_FP_DISABLE 0x40 #define SGN$M_DE_FP_DISABLE 0x80b#define SGN$S_FAST_PATH_PORTS 4 /* Old size name, synonym for SGN$S_SYS_FAST_PATH_PORTS */ Stypedef struct _sgn_fast_path_ports )R{ /* DEFINITION FOR SGN$GL_FAST_PATH_PORTS */ __union { int sgn$l_bits; __struct {Y unsigned sgn$v_pkq_fp_disable : 1; /* Set = disable PKQ (QLogic) Fast Path */` unsigned sgn$v_fge_fp_disable : 1; /* Set = disable Emulex FiberChannel Fast Path */P unsigned sgn$v_pka_fp_disable : 1; /* Set = disable PKA Fast Path */P unsigned sgn$v_lan_fp_disable : 1; /* Set = disable LAN Fast Path */Q unsigned sgn$v_pkr_fp_disa *Rble : 1; /* Set = disable PKR Fast Path */P unsigned sgn$v_pkm_fp_disable : 1; /* Set = disable PKM Fast Path */\ unsigned sgn$v_pgq_fp_disable : 1; /* Set = disable PGQ (QLogic FC) Fast Path */\ unsigned sgn$v_de_fp_disable : 1; /* X-33 Set = disable DE (iSCSI) Fast Path */N unsigned sgn$v_rsrvd1 : 24; /* Align to next byte */ } sgn$r_fill_38_; } sgn$r_fill_37_; } SGN_FAST_PATH_PORTS; #if !defined(__VAX+RC)O#define sgn$v_pkq_fp_disable sgn$r_fill_37_.sgn$r_fill_38_.sgn$v_pkq_fp_disableO#define sgn$v_fge_fp_disable sgn$r_fill_37_.sgn$r_fill_38_.sgn$v_fge_fp_disableO#define sgn$v_pka_fp_disable sgn$r_fill_37_.sgn$r_fill_38_.sgn$v_pka_fp_disableO#define sgn$v_lan_fp_disable sgn$r_fill_37_.sgn$r_fill_38_.sgn$v_lan_fp_disableO#define sgn$v_pkr_fp_disable sgn$r_fill_37_.sgn$r_fill_38_.sgn$v_pkr_fp_disableO#define sgn$v_pkm_fp_disable sgn$r_fill_37_.sgn$r_fill_38_.sgn$v_pkm_fp_disableO#define sg ,Rn$v_pgq_fp_disable sgn$r_fill_37_.sgn$r_fill_38_.sgn$v_pgq_fp_disableM#define sgn$v_de_fp_disable sgn$r_fill_37_.sgn$r_fill_38_.sgn$v_de_fp_disable"#endif /* #if !defined(__VAXC) */ #define SGN$M_PAC_ENABLE 0x1#define SGN$M_DEPTH_FIRST 0x2#define SGN$M_MAX_UNITS 0xC\#define SGN$S_DEVICE_NAMING 4 /* Old size name, synonym for SGN$S_DEVICE_NAMING */ Ntypedef struct _sgn_device_naming { /* DEFINITION FOR IOC$GL_NAMING */ __union { int sgn$l_bits; -R __struct {b unsigned sgn$v_pac_enable : 1; /* set to enable port allocation class naming scheme */f unsigned sgn$v_depth_first : 1; /* set to enable depth-first adapter enumeration scheme */Y unsigned sgn$v_max_units : 2; /* set to limit maximum device units to 9999 */( unsigned sgn$v_fill_41_ : 4; } sgn$r_fill_40_; } sgn$r_fill_39_; } SGN_DEVICE_NAMING; #if !defined(__VAXC)G#define sgn$v_pac_enable sgn$r_fill_.R39_.sgn$r_fill_40_.sgn$v_pac_enableI#define sgn$v_depth_first sgn$r_fill_39_.sgn$r_fill_40_.sgn$v_depth_firstE#define sgn$v_max_units sgn$r_fill_39_.sgn$r_fill_40_.sgn$v_max_units"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __ /Rstandard #endif /* __SYSPARDEF_LOADED */ wwo[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission o0Rf HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. 1R **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:29 by OpenVMS SDL V3.7 */F/* Source: 16-MAY-2006 22:21:09 $1$DGA8345:[L 2RIB_H.SRC]T10DEF.SDL;1 *//********************************************************************************************************************************/"/*** MODULE $T10DEF IDENT X-4 ***/#ifndef __T10DEF_LOADED#define __T10DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_siz3Re __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined4R(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define SCSI$C_OCRW 15#define SCSI$C_BE 17#define SCSI$C_OSD 17#define SCSI$C_ADI 18#define SCSI$C_WLU 30#define SCSI$C_MAXCDB 16#define SCSI$K_MAXCDB 16 struct scsidef1 {- unsigned int scsi$l_scsidef_sdl_pacifier; } ;#define DQ$K_DQ_OPCODE 1#define DQ$K_DQ_FLAGS 0#define DQ$M_DQ_READ 1 struct dqcmd { unsigned int dq$l_dq_opcode; unsigned int dq$l_dq_flags5R; void *dq$a_dq_cmdadr; unsigned int dq$l_dq_cmdlen; void *dq$a_dq_datadr; unsigned int dq$l_dq_datlen; unsigned int dq$l_dq_padlen;" unsigned int dq$l_dq_phasetmo;# unsigned int dq$l_dq_discontmo; unsigned int dq$l_dq_res_1; unsigned int dq$l_dq_res_2; unsigned int dq$l_dq_res_3; unsigned int dq$l_dq_res_4; unsigned int dq$l_dq_res_5; unsigned int dq$l_dq_res_6; } ; struct txc00 {% unsigned char t10$b_txc00_opcode6R;$ unsigned char t10$b_txc00_rsvd1;$ unsigned char t10$b_txc00_rsvd2;$ unsigned char t10$b_txc00_rsvd3;$ unsigned char t10$b_txc00_rsvd4;& unsigned char t10$b_txc00_control; } ; struct txc03 {% unsigned char t10$b_txc03_opcode;$ unsigned char t10$b_txc03_rsvd1;$ unsigned char t10$b_txc03_rsvd2;$ unsigned char t10$b_txc03_rsvd3;% unsigned char t10$b_txc03_length;& unsigned char t10$b_txc03_control; } ;#define T10$K_SKEY_NOSENS 0#defin7Re T10$K_SKEY_FIXERR 1#define T10$K_SKEY_NOTRDY 2#define T10$K_SKEY_MEDERR 3#define T10$K_SKEY_HDWERR 4#define T10$K_SKEY_ILLREQ 5#define T10$K_SKEY_UNITAT 6#define T10$K_SKEY_DATPRT 7#define T10$K_SKEY_BLKCHK 8#define T10$K_SKEY_VENDOR 9#define T10$K_SKEY_RSVD 10#define T10$K_SKEY_CMDABT 11 struct txr03 { __struct {& unsigned t10$v_txr03_code : 7;' unsigned t10$v_txr03_valid : 1; } t10$r_txr03s_code;' unsigned char t10$b_txr03_obso8Rlete; __struct {& unsigned t10$v_txr03_skey : 4;' unsigned t10$v_txr03_rsvd4 : 1;% unsigned t10$v_txr03_ili : 1;% unsigned t10$v_txr03_eom : 1;* unsigned t10$v_txr03_filemark : 1; } t10$r_txr03s_skey;" unsigned int t10$l_txr03_info;% unsigned char t10$b_txr03_addlen;% unsigned int t10$l_txr03_cmdinfo;" unsigned char t10$b_txr03_asc;# unsigned char t10$b_txr03_ascq;" unsigned char t10$b_txr03_fru;) unsigned char 9Rt10$b_txr03_junque [3]; } ; #if !defined(__VAXC);#define t10$v_txr03_code t10$r_txr03s_code.t10$v_txr03_code=#define t10$v_txr03_valid t10$r_txr03s_code.t10$v_txr03_valid;#define t10$v_txr03_skey t10$r_txr03s_skey.t10$v_txr03_skey9#define t10$v_txr03_ili t10$r_txr03s_skey.t10$v_txr03_ili9#define t10$v_txr03_eom t10$r_txr03s_skey.t10$v_txr03_eomC#define t10$v_txr03_filemark t10$r_txr03s_skey.t10$v_txr03_filemark"#endif /* #if !defined(__VAXC) */ "#define T10$K_TXC04_PLFMT_:RLEGACY 7##define T10$K_TXC04_PLFMT_CURRENT 1 struct txc04 {% unsigned char t10$b_txc04_opcode; __struct {- unsigned t10$v_txc04_format_code : 3;( unsigned t10$v_txc04_cmplst : 1;) unsigned t10$v_txc04_fmtdata : 1;, unsigned t10$v_txc04_flags_fill : 3; } t10$r_txc04_flags;' unsigned char t10$b_txc04_reserved;. unsigned short int t10$w_txc04_interleave;& unsigned char t10$b_txc04_control; } ; #if !defined(__VAXC)I#def;Rine t10$v_txc04_format_code t10$r_txc04_flags.t10$v_txc04_format_code?#define t10$v_txc04_cmplst t10$r_txc04_flags.t10$v_txc04_cmplstA#define t10$v_txc04_fmtdata t10$r_txc04_flags.t10$v_txc04_fmtdata"#endif /* #if !defined(__VAXC) */ #define T10$K_TXP04_FIXED 4 struct txp04 {$ unsigned char t10$b_txp04_fill0; __struct {$ unsigned t10$v_txp04_vs : 1;' unsigned t10$v_txp04_immed : 1;( unsigned t10$v_txp04_tryout : 1;$ unsigned t10$v_txp04_ip R t10$v_txp04ip_si : 1;/ unsigned t10$v_txp04ip_ip_modifier : 2; } t10$r_txp04ip_flags;- unsigned char t10$b_txp04ip_pattern_type;4 unsigned short int t10$w_txp04ip_pattern_length;( unsigned char t10$x_txp04ip_pattern; } ; #if !defined(__VAXC)=#define t10$v_txp04ip_si t10$r_txp04ip_flags.t10$v_txp04ip_siO#define t10$v_txp04ip_ip_modifier t10$r_txp04ip_flags.t10$v_txp04ip_ip_modifier"#endif /* #if !defined(__VAXC) */ #define T10$K_TXP04FC111_FDLEN 4!?R#define T10$K_TXP04FC111_LENGTH 8%#define T10$K_TXP04FC001_MAXBLOCKS -1!#define T10$K_TXP04FC001_RWFULL 0##define T10$K_TXP04FC001_MRWFULL 16##define T10$K_TXP04FC001_PRWFULL 38 #define T10$K_TXP04FC001_FDLEN 4!#define T10$K_TXP04FC001_LENGTH 8 struct txp04fd { __union { __struct { __struct {: unsigned t10$v_txp04fc111_flags_fill1 : 6;3 unsigned t10$v_txp04fc111_grow : 1;3 unsigned t10$v_txp04fc111_sess : @R 1;) } t10$r_txp04fc111_flags;1 unsigned char t10$b_txp04fc111_fill1;1 unsigned char t10$b_txp04fc111_fill2;1 unsigned char t10$b_txp04fc111_fill3;6 unsigned int t10$l_txp04fc111_format_size; } t10$r_txp04fc111; __struct {1 unsigned int t10$l_txp04fc001_blocks; __struct {: unsigned t10$v_txp04fc001_flags_fill1 : 2;5 unsigned t10$v_txp04fc001_fmttyp : AR 6;) } t10$r_txp04fc001_flags; __union { __struct {= unsigned char t10$b_txp04fc001ft00_fill0;= unsigned char t10$b_txp04fc001ft00_fill1;= unsigned char t10$b_txp04fc001ft00_fill2;+ } t10$r_txp04fc001ft00; __struct {= unsigned char t10$b_txp04fc001ft26_fill0;= unsigned char t10$b_txp04fc001ft26_fill1; BR __struct {> unsigned t10$v_txp04fc001ft26_rst : 1;> unsigned t10$v_txp04fc001ft26_qst : 1;? unsigned t10$v_txp04fc001ft26_fill : 6;5 } t10$r_txp04fc001ft26_flags;+ } t10$r_txp04fc001ft26;( } t10$r_txp04fc001ftovl; } t10$r_txp04fc001; } t10$r_txp04_fcoverlay; } ; #if !defined(__VAXC)?#define t10$r_txp04fc111 t10$r_txp04CR_fcoverlay.t10$r_txp04fc111F#define t10$r_txp04fc111_flags t10$r_txp04fc111.t10$r_txp04fc111_flagsJ#define t10$v_txp04fc111_grow t10$r_txp04fc111_flags.t10$v_txp04fc111_growJ#define t10$v_txp04fc111_sess t10$r_txp04fc111_flags.t10$v_txp04fc111_sessF#define t10$b_txp04fc111_fill1 t10$r_txp04fc111.t10$b_txp04fc111_fill1F#define t10$b_txp04fc111_fill2 t10$r_txp04fc111.t10$b_txp04fc111_fill2F#define t10$b_txp04fc111_fill3 t10$r_txp04fc111.t10$b_txp04fc111_fill3R#define t10$l_txp04fc111_format_sizeDR t10$r_txp04fc111.t10$l_txp04fc111_format_size?#define t10$r_txp04fc001 t10$r_txp04_fcoverlay.t10$r_txp04fc001H#define t10$l_txp04fc001_blocks t10$r_txp04fc001.t10$l_txp04fc001_blocksF#define t10$r_txp04fc001_flags t10$r_txp04fc001.t10$r_txp04fc001_flagsN#define t10$v_txp04fc001_fmttyp t10$r_txp04fc001_flags.t10$v_txp04fc001_fmttypX#define t10$r_txp04fc001ft00 t10$r_txp04fc001.t10$r_txp04fc001ftovl.t10$r_txp04fc001ft00X#define t10$r_txp04fc001ft26 t10$r_txp04fc001.t10$r_txp04fc001ftovl.t10$r_txERp04fc001ft26R#define t10$r_txp04fc001ft26_flags t10$r_txp04fc001ft26.t10$r_txp04fc001ft26_flagsT#define t10$v_txp04fc001ft26_rst t10$r_txp04fc001ft26_flags.t10$v_txp04fc001ft26_rstT#define t10$v_txp04fc001ft26_qst t10$r_txp04fc001ft26_flags.t10$v_txp04fc001ft26_qst"#endif /* #if !defined(__VAXC) */  struct txc08 {% unsigned char t10$b_txc08_opcode; __struct {& unsigned t10$v_txc08_lba1 : 5;' unsigned t10$v_txc08_fill1 : 3; } t10$r_txc08_lba;' unsiFRgned short int t10$w_txc08_lba;% unsigned char t10$b_txc08_blocks;& unsigned char t10$b_txc08_control; } ; #if !defined(__VAXC)9#define t10$v_txc08_lba1 t10$r_txc08_lba.t10$v_txc08_lba1"#endif /* #if !defined(__VAXC) */ #define T10$K_VPD_SUPPORTED 0#define T10$K_VPD_SERIAL 128 struct txc12 {% unsigned char t10$b_txc12_opcode; __struct {& unsigned t10$v_txc12_evpd : 1;' unsigned t10$v_txc12_cmddt : 1;+ unsigned t10$v_txc12_flag_GRfill : 6; } t10$r_txc12_flags;* unsigned char t10$b_txc12_page_opcode;. unsigned short int t10$w_txc12_max_length;& unsigned char t10$b_txc12_control; } ; #if !defined(__VAXC);#define t10$v_txc12_evpd t10$r_txc12_flags.t10$v_txc12_evpd=#define t10$v_txc12_cmddt t10$r_txc12_flags.t10$v_txc12_cmddt"#endif /* #if !defined(__VAXC) */ #define T10$K_DTYP_DIRATT 0#define T10$K_DTYP_SEQDEV 1#define T10$K_DTYP_PRINTER 2#define T10$K_DTYP_CPU 3#define T10$K_HRDTYP_WRTONCE 4#define T10$K_DTYP_CDROM 5#define T10$K_DTYP_SCANNER 6#define T10$K_DTYP_OPTICAL 7#define T10$K_DTYP_CHANGER 8#define T10$K_DTYP_COMMDEV 9#define T10$K_DTYP_ASCIT8A 10#define T10$K_DTYP_ASCIT8B 11#define T10$K_DTYP_STORARR 12#define T10$K_DTYP_ENCSERV 13#define T10$K_DTYP_SDIRATT 14#define T10$K_DTYP_CARDRDR 15#define T10$K_DTYP_OBJDEV 16#define T10$K_DTYP_AUTOMAT 17#define T10$K_DTYP_WELLKNOWN 30#define T10$K_DTYP_UNKNOWN 31#define T10$K_DEVQ_CONIRNECT 0#define T10$K_DEVQ_DISCONN 1#define T10$K_DEVQ_RSVD010 2#define T10$K_DEVQ_NOPHYDEV 3#define T10$K_DEVQ_VENDOR 4#define T10$K_SPCVA_NOCLAIMS 0#define T10$K_SPCVA_OBS1 1#define T10$K_SPCVA_SCSI2 2#define T10$K_SPCVA_SPC 3#define T10$K_SPCVA_SPC2 4#define T10$K_SPCVA_SPC3 5#define T10$K_ATAPI_UNK0 0#define T10$K_ATAPI_UNK1 1#define T10$K_ATAPI_SFF8020 2#define T10$K_ATAPI_SFF8090 3#define T10$K_SPCVA_UNK4 4!#define T10$K_TXR12_BASE_LENGTH 5#define T10$K_TXR1JR2_VERS_DESC 8!#define T10$K_TXR12_VDSC_MMC1 348%#define T10$K_TXR12_VDSC_MMC1_10A 347!#define T10$K_TXR12_VDSC_MMC2 576&#define T10$K_TXR12_VDSC_MMC2_2000 604%#define T10$K_TXR12_VDSC_MMC2_11A 603!#define T10$K_TXR12_VDSC_MMC3 672&#define T10$K_TXR12_VDSC_MMC3_200X 696%#define T10$K_TXR12_VDSC_MMC3_10G 694##define T10$K_TXR12_VDSC_MMC3_9 693!#define T10$K_TXR12_VDSC_MMC4 928&#define T10$K_TXR12_GENERIC_LENGTH 255 struct txr12 { __struct {) unsigned t10$v_txr12_dKRevtype : 5;) unsigned t10$v_txr12_devqual : 3;! } t10$r_txr12_peripheral; __struct {1 unsigned t10$v_txr12_removable_fill1 : 7;+ unsigned t10$v_txr12_removable : 1; } t10$r_txr12_removable; __struct {. unsigned t10$v_txr12_ansi_version : 3;. unsigned t10$v_txr12_ecma_version : 3;0 unsigned t10$v_txr12_isoiec_version : 2; } t10$r_txr12_version; __union { __struct {. unsigned t10$v_t LRxr12_scsi_rdf : 4;+ unsigned t10$v_txr12_hisup : 1;- unsigned t10$v_txr12_normaca : 1;2 unsigned t10$v_txr12_addrsupp_obs : 1;* unsigned t10$v_txr12_aerc : 1;# } t10$r_txr12_addrscsi; __struct {/ unsigned t10$v_txr12_atapi_rdf : 4;3 unsigned t10$v_txr12_atapi_version : 4;$ } t10$r_txr12_addratapi;" } t10$r_txr12_addroverlay;+ unsigned char t10$b_txr12_extra_length; __structMR {. unsigned t10$v_txr12_flags1_fill1 : 3;% unsigned t10$v_txr12_3pc : 1;& unsigned t10$v_txr12_alua : 2;% unsigned t10$v_txr12_acc : 1;& unsigned t10$v_txr12_sccs : 1; } t10$r_txr12_flags1; __struct {( unsigned t10$v_txr12_addr16 : 1;. unsigned t10$v_txr12_flags2_fill1 : 2;( unsigned t10$v_txr12_mchngr : 1;( unsigned t10$v_txr12_multip : 1;% unsigned t10$v_txr12_vs1 : 1;) unsigned t10$v_txr12NR_encserv : 1;& unsigned t10$v_txr12_bque : 1; } t10$r_txr12_flags2; __struct {% unsigned t10$v_txr12_vs2 : 1;( unsigned t10$v_txr12_cmdque : 1;. unsigned t10$v_txr12_flags3_fill1 : 1;( unsigned t10$v_txr12_linked : 1;& unsigned t10$v_txr12_sync : 1;( unsigned t10$v_txr12_wbus16 : 1;. unsigned t10$v_txr12_flags3_fill2 : 1;( unsigned t10$v_txr12_reladr : 1; } t10$r_txr12_flags3;" char t10$t_txr12_venORdname [8];# char t10$t_txr12_prodname [16];! char t10$t_txr12_prodrev [4];/ unsigned char t10$x_txr12_vendor_data [20]; __struct {% unsigned t10$v_txr12_ius : 1;% unsigned t10$v_txr12_qas : 1;* unsigned t10$v_txr12_clocking : 2;) unsigned t10$v_txr12_fill564 : 4; } t10$r_txr12_tx_flags4;& unsigned char t10$b_txr12_fill570;1 unsigned short int t10$w_txr12_vers_desc [8];2 unsigned char t10$b_txr12_reserved75255 [181]; } PR; #if !defined(__VAXC)F#define t10$v_txr12_devtype t10$r_txr12_peripheral.t10$v_txr12_devtypeF#define t10$v_txr12_devqual t10$r_txr12_peripheral.t10$v_txr12_devqualI#define t10$v_txr12_removable t10$r_txr12_removable.t10$v_txr12_removableM#define t10$v_txr12_ansi_version t10$r_txr12_version.t10$v_txr12_ansi_versionM#define t10$v_txr12_ecma_version t10$r_txr12_version.t10$v_txr12_ecma_versionQ#define t10$v_txr12_isoiec_version t10$r_txr12_version.t10$v_txr12_isoiec_versionI#define t10$QRr_txr12_addrscsi t10$r_txr12_addroverlay.t10$r_txr12_addrscsiF#define t10$v_txr12_scsi_rdf t10$r_txr12_addrscsi.t10$v_txr12_scsi_rdf@#define t10$v_txr12_hisup t10$r_txr12_addrscsi.t10$v_txr12_hisupD#define t10$v_txr12_normaca t10$r_txr12_addrscsi.t10$v_txr12_normaca>#define t10$v_txr12_aerc t10$r_txr12_addrscsi.t10$v_txr12_aercK#define t10$r_txr12_addratapi t10$r_txr12_addroverlay.t10$r_txr12_addratapiI#define t10$v_txr12_atapi_rdf t10$r_txr12_addratapi.t10$v_txr12_atapi_rdfQ#define t10$v_txRRr12_atapi_version t10$r_txr12_addratapi.t10$v_txr12_atapi_version:#define t10$v_txr12_3pc t10$r_txr12_flags1.t10$v_txr12_3pc<#define t10$v_txr12_alua t10$r_txr12_flags1.t10$v_txr12_alua:#define t10$v_txr12_acc t10$r_txr12_flags1.t10$v_txr12_acc<#define t10$v_txr12_sccs t10$r_txr12_flags1.t10$v_txr12_sccs@#define t10$v_txr12_addr16 t10$r_txr12_flags2.t10$v_txr12_addr16@#define t10$v_txr12_mchngr t10$r_txr12_flags2.t10$v_txr12_mchngr@#define t10$v_txr12_multip t10$r_txr12_flags2.t10$v_txr12_mult SRip:#define t10$v_txr12_vs1 t10$r_txr12_flags2.t10$v_txr12_vs1B#define t10$v_txr12_encserv t10$r_txr12_flags2.t10$v_txr12_encserv<#define t10$v_txr12_bque t10$r_txr12_flags2.t10$v_txr12_bque:#define t10$v_txr12_vs2 t10$r_txr12_flags3.t10$v_txr12_vs2@#define t10$v_txr12_cmdque t10$r_txr12_flags3.t10$v_txr12_cmdque@#define t10$v_txr12_linked t10$r_txr12_flags3.t10$v_txr12_linked<#define t10$v_txr12_sync t10$r_txr12_flags3.t10$v_txr12_sync@#define t10$v_txr12_wbus16 t10$r_txr12_flags3.t10$v_txr12_TRwbus16@#define t10$v_txr12_reladr t10$r_txr12_flags3.t10$v_txr12_reladr=#define t10$v_txr12_ius t10$r_txr12_tx_flags4.t10$v_txr12_ius=#define t10$v_txr12_qas t10$r_txr12_tx_flags4.t10$v_txr12_qasG#define t10$v_txr12_clocking t10$r_txr12_tx_flags4.t10$v_txr12_clocking"#endif /* #if !defined(__VAXC) */ #define T10$K_VPD00_FIXED 4 struct vpd00 { __struct {) unsigned t10$v_vpd00_devtype : 5;) unsigned t10$v_vpd00_devqual : 3;! } t10$r_vpd00_peripheral;UR( unsigned char t10$b_vpd00_page_code;% unsigned char t10$b_vpd00_rsvd02;% unsigned char t10$b_vpd00_length; } ; #if !defined(__VAXC)F#define t10$v_vpd00_devtype t10$r_vpd00_peripheral.t10$v_vpd00_devtypeF#define t10$v_vpd00_devqual t10$r_vpd00_peripheral.t10$v_vpd00_devqual"#endif /* #if !defined(__VAXC) */ #define T10$K_VPD80_FIXED 4 struct vpd80 { __struct {) unsigned t10$v_vpd80_devtype : 5;) unsigned t10$v_vpd80_devqual : 3;! VR } t10$r_vpd80_peripheral;( unsigned char t10$b_vpd80_page_code;% unsigned char t10$b_vpd80_rsvd02;% unsigned char t10$b_vpd80_length; } ; #if !defined(__VAXC)F#define t10$v_vpd80_devtype t10$r_vpd80_peripheral.t10$v_vpd80_devtypeF#define t10$v_vpd80_devqual t10$r_vpd80_peripheral.t10$v_vpd80_devqual"#endif /* #if !defined(__VAXC) */  #define T10$S_TXR12_PRODREV 4"#define T10$S_TXR12_VENDOR_DATA 20#define T10$S_TXR12_VENDNAME 8#define T10$S_TXR12_PRODNAME 1WR6 struct txr12a {( short int t10$w_txr12a_sdl_pacifier; } ; struct txc15 {% unsigned char t10$b_txc15_opcode; __struct {$ unsigned t10$v_txc15_sp : 1;( unsigned t10$v_txc15_fill11 : 3;$ unsigned t10$v_txc15_pf : 1;( unsigned t10$v_txc15_fill15 : 3; } t10$r_txc15_flags;% unsigned char t10$b_txc15_fill20;% unsigned char t10$b_txc15_fill30;% unsigned char t10$b_txc15_length;& unsigned char t10$b_txc15_control;XR } ; #if !defined(__VAXC)7#define t10$v_txc15_sp t10$r_txc15_flags.t10$v_txc15_sp7#define t10$v_txc15_pf t10$r_txc15_flags.t10$v_txc15_pf"#endif /* #if !defined(__VAXC) */ #define T10$K_TXC1A_PC_CURR 0#define T10$K_TXC1A_PC_CHNG 1#define T10$K_TXC1A_PC_DFLT 2#define T10$K_TXC1A_PC_SAVE 3 struct txc1a {% unsigned char t10$b_txc1a_opcode; __struct {' unsigned t10$v_txc1a_fill0 : 3;% unsigned t10$v_txc1a_dbd : 1;' unsigned t10$v_txcYR1a_fill4 : 4; } t10$r_txc1a_flags; __struct {& unsigned t10$v_txc1a_page : 6;& unsigned t10$v_txc1a_ctrl : 2; } t10$r_txc1a_pagectrl;& unsigned char t10$b_txc1a_subpage;% unsigned char t10$b_txc1a_length;& unsigned char t10$b_txc1a_control; } ; #if !defined(__VAXC)9#define t10$v_txc1a_dbd t10$r_txc1a_flags.t10$v_txc1a_dbd=#define t10$v_txc1a_fill4 t10$r_txc1a_flags.t10$v_txc1a_fill4>#define t10$v_txc1a_page t10$r_txc1a_pagectrl.t1ZR0$v_txc1a_page>#define t10$v_txc1a_ctrl t10$r_txc1a_pagectrl.t10$v_txc1a_ctrl"#endif /* #if !defined(__VAXC) */ #define T10$K_OPC_STOPDISK 0#define T10$K_OPC_STARTDISK 1#define T10$K_OPC_EJECTDISK 2#define T10$K_OPC_LOADDISK 3#define T10$K_PWR_NOCHANGE 0#define T10$K_PWR_RSVD1 1#define T10$K_PWR_IDLE 2#define T10$K_PWR_STANDBY 3#define T10$K_PWR_RSVD4 4#define T10$K_PWR_SLEEP 5#define T10$K_PWR_RSVD6 6#define T10$K_PWR_RSVD7 7#define T10$K_PWR_RSVD8 8#define [RT10$K_PWR_RSVD9 9#define T10$K_PWR_RSVDA 10#define T10$K_PWR_RSVDB 11#define T10$K_PWR_RSVDC 12#define T10$K_PWR_RSVDD 13#define T10$K_PWR_RSVDE 14#define T10$K_PWR_RSVDF 15 struct txc1b {% unsigned char t10$b_txc1b_opcode; __struct {' unsigned t10$v_txc1b_immed : 1;( unsigned t10$v_txc1b_fill11 : 7; } t10$r_txc1b_flags;% unsigned char t10$b_txc1b_fill20;% unsigned char t10$b_txc1b_fill30; __struct {( unsigned t10$v_txc1b \R_action : 2;( unsigned t10$v_txc1b_fill42 : 2;' unsigned t10$v_txc1b_state : 4; } t10$r_txc1b_power;& unsigned char t10$b_txc1b_control; } ; #if !defined(__VAXC)=#define t10$v_txc1b_immed t10$r_txc1b_flags.t10$v_txc1b_immed?#define t10$v_txc1b_fill11 t10$r_txc1b_flags.t10$v_txc1b_fill11?#define t10$v_txc1b_action t10$r_txc1b_power.t10$v_txc1b_action?#define t10$v_txc1b_fill42 t10$r_txc1b_power.t10$v_txc1b_fill42=#define t10$v_txc1b_state t10$r_txc1b_po]Rwer.t10$v_txc1b_state"#endif /* #if !defined(__VAXC) */  struct txc23 {% unsigned char t10$b_txc23_opcode;$ unsigned char t10$b_txc23_fill1;$ unsigned char t10$b_txc23_fill2;$ unsigned char t10$b_txc23_fill3;$ unsigned char t10$b_txc23_fill4;$ unsigned char t10$b_txc23_fill5;$ unsigned char t10$b_txc23_fill6;* unsigned short int t10$w_txc23_length;& unsigned char t10$b_txc23_control; } ;"#define T10$K_TXR23FL_DT_RSVDMED 0##define T10$K_TXR23FL_DT^R_UNFMTMED 1!#define T10$K_TXR23FL_DT_FMTMED 2"#define T10$K_TXR23FL_DT_NOMEDIA 3#define T10$K_FMTTYP_WHOLE 0#define T10$K_FMTTYP_EXPAND 1#define T10$K_FMTTYP_RSVD02 2#define T10$K_FMTTYP_RSVD03 3#define T10$K_FMTTYP_ZONE 4#define T10$K_FMTTYP_HIZONE 5#define T10$K_FMTTYP_RSVD06 6#define T10$K_FMTTYP_RSVD07 7#define T10$K_FMTTYP_RSVD08 8#define T10$K_FMTTYP_RSVD09 9#define T10$K_FMTTYP_RSVD0A 10#define T10$K_FMTTYP_RSVD0B 11#define T10$K_FMTTYP_RSVD0C 12#define _RT10$K_FMTTYP_RSVD0D 13#define T10$K_FMTTYP_RSVD0E 14#define T10$K_FMTTYP_RSVD0F 15#define T10$K_FMTTYP_MAXRW 16 #define T10$K_FMTTYP_GROWSESS 17#define T10$K_FMTTYP_ADDSESS 18"#define T10$K_FMTTYP_GROWSESINT 19"#define T10$K_FMTTYP_ADDSESSINT 20 #define T10$K_FMTTYP_MAXRWINT 21#define T10$K_FMTTYP_RSVD16 22#define T10$K_FMTTYP_RSVD17 23#define T10$K_FMTTYP_RSVD18 24#define T10$K_FMTTYP_RSVD19 25#define T10$K_FMTTYP_RSVD1A 26#define T10$K_FMTTYP_RSVD1B 27#define T10$K_FMTTYP`R_RSVD1C 28#define T10$K_FMTTYP_RSVD1D 29#define T10$K_FMTTYP_RSVD1E 30#define T10$K_FMTTYP_RSVD1F 31#define T10$K_FMTTYP_RSVD20 32#define T10$K_FMTTYP_RSVD21 33#define T10$K_FMTTYP_RSVD22 34#define T10$K_FMTTYP_RSVD23 35!#define T10$K_FMTTYP_MRWDMAADD 36#define T10$K_FMTTYP_RSVD25 37#define T10$K_FMTTYP_PLUSRW 38#define T10$K_FMTTYP_RSVD27 39 struct txr23fl {& unsigned char t10$b_txr23fl_fill0;& unsigned char t10$b_txr23fl_fill1;& unsigned char t10$b_txr23fl_fillaR2;' unsigned char t10$b_txr23fl_length;& unsigned int t10$l_txr23fl_blocks; __struct {+ unsigned t10$v_txr23fl_dsctype : 2;. unsigned t10$v_txr23fl_flags_fill : 6; } t10$r_txr23fl_flags;/ unsigned char t10$x_txr23fl_block_size [3]; __struct {, unsigned int t10$l_txr23flfc_blocks; __struct {. unsigned t10$v_txr23flfc_rsvd : 2;1 unsigned t10$v_txr23flfc_fmttype : 2;' unsigned t10$v_fill_0_ : 4; bR& } t10$r_txr23flfc_fcflags;1 unsigned char t10$x_txr23flfc_typdep [3]; } t10$r_txr23flfc [32]; } ; #if !defined(__VAXC)G#define t10$v_txr23fl_dsctype t10$r_txr23fl_flags.t10$v_txr23fl_dsctype5#define t10$l_txr23flfc_blocks t10$l_txr23flfc_blocks7#define t10$r_txr23flfc_fcflags t10$r_txr23flfc_fcflagsI#define t10$v_txr23flfc_rsvd t10$r_txr23flfc_fcflags.t10$v_txr23flfc_rsvdO#define t10$v_txr23flfc_fmttype t10$r_txr23flfc_fcflags.t10$v_txr23flfc_fmttypcRe5#define t10$x_txr23flfc_typdep t10$x_txr23flfc_typdep"#endif /* #if !defined(__VAXC) */  struct txc25 {% unsigned char t10$b_txc25_opcode; __struct {( unsigned t10$v_txc25_reladr : 1;' unsigned t10$v_txc25_fill1 : 7; } t10$r_txc25_flags;! unsigned int t10$l_txc25_lba;$ unsigned char t10$b_txc25_fill6;$ unsigned char t10$b_txc25_fill7; __struct {) unsigned t10$v_txc25_fill100 : 7;% unsigned t10$v_txc25_pmi : 1;dR } t10$r_txc25_flags10;& unsigned char t10$b_txc25_control; } ; #if !defined(__VAXC)?#define t10$v_txc25_reladr t10$r_txc25_flags.t10$v_txc25_reladr;#define t10$v_txc25_pmi t10$r_txc25_flags10.t10$v_txc25_pmi"#endif /* #if !defined(__VAXC) */  struct txr25 {% unsigned int t10$l_txr25_max_lba;( unsigned int t10$l_txr25_block_size; } ; struct txc28 {% unsigned char t10$b_txc28_opcode; __struct {( unsigned t10$v_txc28_reladr : 1;eR' unsigned t10$v_txc28_fill1 : 2;% unsigned t10$v_txc28_fua : 1;% unsigned t10$v_txc28_dpo : 1;' unsigned t10$v_txc28_fill2 : 3; } t10$r_txc28_flags;! unsigned int t10$l_txc28_lba;$ unsigned char t10$b_txc28_fill6;* unsigned short int t10$w_txc28_blocks;& unsigned char t10$b_txc28_control; } ; #if !defined(__VAXC)?#define t10$v_txc28_reladr t10$r_txc28_flags.t10$v_txc28_reladr9#define t10$v_txc28_fua t10$r_txc28_flags.t10$v_txfRc28_fua9#define t10$v_txc28_dpo t10$r_txc28_flags.t10$v_txc28_dpo"#endif /* #if !defined(__VAXC) */  struct txc2a {% unsigned char t10$b_txc2a_opcode; __struct {( unsigned t10$v_txc2a_reladr : 1;' unsigned t10$v_txc2a_fill1 : 1;% unsigned t10$v_txc2a_ebp : 1;% unsigned t10$v_txc2a_fua : 1;% unsigned t10$v_txc2a_dpo : 1;' unsigned t10$v_txc2a_fill2 : 3; } t10$r_txc2a_flags;! unsigned int t10$l_txc2a_lba;$ ungRsigned char t10$b_txc2a_fill6;* unsigned short int t10$w_txc2a_blocks;& unsigned char t10$b_txc2a_control; } ; #if !defined(__VAXC)?#define t10$v_txc2a_reladr t10$r_txc2a_flags.t10$v_txc2a_reladr9#define t10$v_txc2a_ebp t10$r_txc2a_flags.t10$v_txc2a_ebp9#define t10$v_txc2a_fua t10$r_txc2a_flags.t10$v_txc2a_fua9#define t10$v_txc2a_dpo t10$r_txc2a_flags.t10$v_txc2a_dpo"#endif /* #if !defined(__VAXC) */  struct txc2e {% unsigned char t10$b_txc2e_opcode; __sthRruct {( unsigned t10$v_txc2e_reladr : 1;( unsigned t10$v_txc2e_bytchk : 1;' unsigned t10$v_txc2e_fill1 : 2;% unsigned t10$v_txc2e_dpo : 1;' unsigned t10$v_txc2e_fill2 : 3; } t10$r_txc2e_flags;! unsigned int t10$l_txc2e_lba;$ unsigned char t10$b_txc2e_fill6;* unsigned short int t10$w_txc2e_blocks;& unsigned char t10$b_txc2e_control; } ; #if !defined(__VAXC)?#define t10$v_txc2e_reladr t10$r_txc2e_flags.t10$v_txc2e_reladriR?#define t10$v_txc2e_bytchk t10$r_txc2e_flags.t10$v_txc2e_bytchk9#define t10$v_txc2e_dpo t10$r_txc2e_flags.t10$v_txc2e_dpo"#endif /* #if !defined(__VAXC) */  struct txc35 {% unsigned char t10$b_txc35_opcode; __struct {( unsigned t10$v_txc35_reladr : 1;' unsigned t10$v_txc35_immed : 1;& unsigned t10$v_txc35_fill : 6; } t10$r_txc35_flags;! unsigned int t10$l_txc35_lba;$ unsigned char t10$b_txc35_fill6;* unsigned short int t10$w_txcjR35_blocks;& unsigned char t10$b_txc35_control; } ; #if !defined(__VAXC)?#define t10$v_txc35_reladr t10$r_txc35_flags.t10$v_txc35_reladr=#define t10$v_txc35_immed t10$r_txc35_flags.t10$v_txc35_immed"#endif /* #if !defined(__VAXC) */ !#define T10$K_TXC43_FMT_ALLTRKS 0!#define T10$K_TXC43_FMT_LASTTRK 1!#define T10$K_TXC43_FMT_QSUBTOC 2!#define T10$K_TXC43_FMT_QSUBPMA 3#define T10$K_TXC43_FMT_ATIP 4#define T10$K_TXC43_FMT_TEXT 5 struct txc43 {% unsigned char t1kR0$b_txc43_opcode; __struct {, unsigned t10$v_txc43_time_rsvd0 : 1;- unsigned t10$v_txc43_time_or_lba : 1;, unsigned t10$v_txc43_time_rsvd3 : 6; } t10$r_txc43_flags; __struct {( unsigned t10$v_txc43_format : 4;+ unsigned t10$v_txc43_fmt_rsvd5 : 4; } t10$r_txc43s_format;$ unsigned char t10$b_txc43_fill3;$ unsigned char t10$b_txc43_fill4;$ unsigned char t10$b_txc43_fill5;& unsigned char t10$b_txc43_trksess;* unlRsigned short int t10$w_txc43_length;& unsigned char t10$b_txc43_control; } ; #if !defined(__VAXC)I#define t10$v_txc43_time_or_lba t10$r_txc43_flags.t10$v_txc43_time_or_lbaA#define t10$v_txc43_format t10$r_txc43s_format.t10$v_txc43_format"#endif /* #if !defined(__VAXC) */  struct txr43 {/ unsigned short int t10$w_txr43_data_length;( unsigned char t10$b_txr43_1st_track;) unsigned char t10$b_txr43_last_track; } ;#define T10$K_TX43ADRTD_NO 0#define T10$mRK_TX43ADRTD_PS 1#define T10$K_TX43ADRTD_CT 2#define T10$K_TX43ADRTD_IS 3 struct txr43td {& unsigned char t10$b_txr43td_fill0; __struct {+ unsigned t10$v_txr43td_control : 4;' unsigned t10$v_txr43td_adr : 4; } t10$r_txr43td_flags;& unsigned char t10$b_txr43td_track;& unsigned char t10$b_txr43td_fill3;+ unsigned int t10$l_txr43td_track_start; } ; #if !defined(__VAXC)G#define t10$v_txr43td_control t10$r_txr43td_flags.t10$v_txr43td_conRntrol?#define t10$v_txr43td_adr t10$r_txr43td_flags.t10$v_txr43td_adr"#endif /* #if !defined(__VAXC) */ #define T10$K_TXC46_RT_ALL 0 #define T10$K_TXC46_RT_CURRENT 1#define T10$K_TXC46_RT_ONE 2!#define T10$K_TXC46_RT_RESERVED 3#define T10$K_FCOD_LIST 0#define T10$K_FCOD_CORE 1#define T10$K_FCOD_MORPH 2#define T10$K_FCOD_REMOVABLE 3#define T10$K_FCOD_WRPROT 4#define T10$K_FCOD_RSVD05 5#define T10$K_FCOD_RSVD06 6#define T10$K_FCOD_RSVD07 7#define T10$K_FCOD_RSVD08 oR8#define T10$K_FCOD_RSVD09 9#define T10$K_FCOD_RSVD0A 10#define T10$K_FCOD_RSVD0B 11#define T10$K_FCOD_RSVD0C 12#define T10$K_FCOD_RSVD0D 13#define T10$K_FCOD_RSVD0E 14#define T10$K_FCOD_RSVD0F 15#define T10$K_FCOD_RANDRD 16#define T10$K_FCOD_RSVD11 17#define T10$K_FCOD_RSVD12 18#define T10$K_FCOD_RSVD13 19#define T10$K_FCOD_RSVD14 20#define T10$K_FCOD_RSVD15 21#define T10$K_FCOD_RSVD16 22#define T10$K_FCOD_RSVD17 23#define T10$K_FCOD_RSVD18 24#define T10$K_FCOD_RSVpRD19 25#define T10$K_FCOD_RSVD1A 26#define T10$K_FCOD_RSVD1B 27#define T10$K_FCOD_RSVD1C 28#define T10$K_FCOD_MULTIREAD 29#define T10$K_FCOD_CDREAD 30#define T10$K_FCOD_DVDREAD 31#define T10$K_FCOD_RANDWR 32#define T10$K_FCOD_INCSTRMWR 33!#define T10$K_FCOD_SECTORERASE 34!#define T10$K_FCOD_FORMATTABLE 35!#define T10$K_FCOD_DEFECTMGMT1 36#define T10$K_FCOD_WRITEONCE 37!#define T10$K_FCOD_RESTROVRWR1 38#define T10$K_FCOD_CDRWCAV 39#define T10$K_FCOD_MRW 40!#define T1qR0$K_FCOD_DEFECTMGMT2 41#define T10$K_FCOD_DVDPLUSRW 42#define T10$K_FCOD_DVDPLUSR 43 #define T10$K_FCOD_RESTOVRWR2 44#define T10$K_FCOD_CDTAO 45#define T10$K_FCOD_CDMASTER 46 #define T10$K_FCOD_DVDMINUSRW 47#define T10$K_FCOD_DDCD 48#define T10$K_FCOD_DDCDR 49#define T10$K_FCOD_DDCDRW 50#define T10$K_FCOD_LAYERJMP 51#define T10$K_FCOD_RSVD34 52#define T10$K_FCOD_RSVD35 53#define T10$K_FCOD_RSVD36 54 #define T10$K_FCOD_CDRWMEDRPT 55#define T10$K_FCOD_BDPOW 56#define T1rR0$K_FCOD_RSVD39 57!#define T10$K_FCOD_DVDPLUSRWDL 58 #define T10$K_FCOD_DVDPLUSRDL 59#define T10$K_FCOD_RSVD3C 60#define T10$K_FCOD_RSVD3D 61#define T10$K_FCOD_RSVD3E 62#define T10$K_FCOD_RSVD3F 63#define T10$K_FCOD_BDR 64#define T10$K_FCOD_BDW 65#define T10$K_FCOD_TSR 66#define T10$K_FCOD_RSVD43 67#define T10$K_FCOD_RSVD44 68#define T10$K_FCOD_RSVD45 69#define T10$K_FCOD_RSVD46 70#define T10$K_FCOD_RSVD47 71#define T10$K_FCOD_RSVD48 72#define T10$K_FCOD_RSVD49 73#dsRefine T10$K_FCOD_RSVD4A 74#define T10$K_FCOD_RSVD4B 75#define T10$K_FCOD_RSVD4C 76#define T10$K_FCOD_RSVD4D 77#define T10$K_FCOD_RSVD4E 78#define T10$K_FCOD_RSVD4F 79#define T10$K_FCOD_HDR 80#define T10$K_FCOD_HDW 81#define T10$K_FCOD_PWRMGMT 256#define T10$K_FCOD_RSVD101 257#define T10$K_FCOD_EMBCHNGR 258#define T10$K_FCOD_CDAUDIO 259#define T10$K_FCOD_FWUPGR 260#define T10$K_FCOD_TIMEOUT 261#define T10$K_FCOD_DVDCSS 262#define T10$K_FCOD_RTSTREAM 263 #define T10$tRK_FCOD_SERIALNUM 264#define T10$K_FCOD_RSVD109 265#define T10$K_FCOD_CNTLBLKS 266#define T10$K_FCOD_DVDCPRM 267#define T10$K_FCOD_FWINFO 268#define T10$K_FCOD_AACS 269#define T10$K_FCOD_RSVD10E 270#define T10$K_FCOD_RSVD10F 271#define T10$K_FCOD_VCPS 272#define T10$K_FCOD_FWDATE 511 struct txc46 {% unsigned char t10$b_txc46_opcode; __struct {( unsigned t10$v_txc46_reqtyp : 2;, unsigned t10$v_txc46_flags_fill : 6; } t10$r_txc46_flags;, uR unsigned short int t10$w_txc46_1st_feat;$ unsigned char t10$b_txc46_fill4;$ unsigned char t10$b_txc46_fill5;$ unsigned char t10$b_txc46_fill6;. unsigned short int t10$w_txc46_rsp_length;& unsigned char t10$b_txc46_control; } ; #if !defined(__VAXC)?#define t10$v_txc46_reqtyp t10$r_txc46_flags.t10$v_txc46_reqtyp"#endif /* #if !defined(__VAXC) */ #define T10$K_TXR46FH_LENGTH 8 struct txr46fh {& unsigned int t10$l_txr46fh_length;& unsigned char t10$b_vRtxr46fh_fill4;& unsigned char t10$b_txr46fh_fill5;2 unsigned short int t10$w_txr46fh_curr_profile; } ;#define T10$K_TXR46FD_MRW 40#define T10$K_TXR46FD_DVDPRW 42#define T10$K_TXR46FD_DVDPR 43#define T10$K_TXR46FD_LENGTH 4#define T10$K_TXR46FD00_SIZE 64#define T10$K_PROF_RSVD00 0#define T10$K_PROF_FIXEDDISK 1#define T10$K_PROF_REMOVABLE 2#define T10$K_PROF_MOERASABLE 3#define T10$K_PROF_WORMDISK 4#define T10$K_PROF_ASMO 5#define T10$K_PROF_RSVD06 6#define wRT10$K_PROF_RSVD07 7#define T10$K_PROF_CDROM 8#define T10$K_PROF_CDR 9#define T10$K_PROF_CDRW 10#define T10$K_PROF_RSVD0B 11#define T10$K_PROF_RSVD0C 12#define T10$K_PROF_RSVD0D 13#define T10$K_PROF_RSVD0E 14#define T10$K_PROF_RSVD0F 15#define T10$K_PROF_DVDROM 16"#define T10$K_PROF_DVDMINUSRSEQ 17#define T10$K_PROF_DVDRAM 18"#define T10$K_PROF_DVDMINUSRWRO 19##define T10$K_PROF_DVDMINUSRWSEQ 20$#define T10$K_PROF_DVDMINUSRDLSEQ 21$#define T10$K_PROF_DVDMINUSRDLJMP 22#definxRe T10$K_PROF_RSVD17 23#define T10$K_PROF_RSVD18 24#define T10$K_PROF_RSVD19 25#define T10$K_PROF_DVDPLUSRW 26#define T10$K_PROF_DVDPLUSR 27#define T10$K_PROF_RSVD1C 28#define T10$K_PROF_RSVD1D 29#define T10$K_PROF_RSVD1E 30#define T10$K_PROF_RSVD1F 31#define T10$K_PROF_DDCDROM 32#define T10$K_PROF_DDCDR 33#define T10$K_PROF_DDCDRW 34#define T10$K_PROF_RSVD23 35#define T10$K_PROF_RSVD24 36#define T10$K_PROF_RSVD25 37#define T10$K_PROF_RSVD26 38#define T10$K_PROF_RSVD2yR7 39#define T10$K_PROF_RSVD28 40#define T10$K_PROF_RSVD29 41!#define T10$K_PROF_DVDPLUSRWDL 42 #define T10$K_PROF_DVDPLUSRDL 43#define T10$K_PROF_RSVD2C 44#define T10$K_PROF_RSVD2D 45#define T10$K_PROF_RSVD2E 46#define T10$K_PROF_RSVD2F 47#define T10$K_PROF_RSVD30 48#define T10$K_PROF_RSVD31 49#define T10$K_PROF_RSVD32 50#define T10$K_PROF_RSVD33 51#define T10$K_PROF_RSVD34 52#define T10$K_PROF_RSVD35 53#define T10$K_PROF_RSVD36 54#define T10$K_PROF_RSVD37 55#define T1zR0$K_PROF_RSVD38 56#define T10$K_PROF_RSVD39 57#define T10$K_PROF_RSVD3A 58#define T10$K_PROF_RSVD3B 59#define T10$K_PROF_RSVD3C 60#define T10$K_PROF_RSVD3D 61#define T10$K_PROF_RSVD3E 62#define T10$K_PROF_RSVD3F 63#define T10$K_PROF_BDROM 64#define T10$K_PROF_BDRSRM 65#define T10$K_PROF_BDRRRM 66#define T10$K_PROF_BDRE 67#define T10$K_PROF_RSVD44 68#define T10$K_PROF_RSVD45 69#define T10$K_PROF_RSVD46 70#define T10$K_PROF_RSVD47 71#define T10$K_PROF_RSVD48 72#define {RT10$K_PROF_RSVD49 73#define T10$K_PROF_RSVD4A 74#define T10$K_PROF_RSVD4B 75#define T10$K_PROF_RSVD4C 76#define T10$K_PROF_RSVD4D 77#define T10$K_PROF_RSVD4E 78#define T10$K_PROF_RSVD4F 79#define T10$K_PROF_HDDVDROM 80#define T10$K_PROF_HDDVDR 81#define T10$K_PROF_HDDVDRW 82#define T10$K_PROF_RSVD53 83#define T10$K_PROF_RSVD54 84#define T10$K_PROF_RSVD55 85#define T10$K_PROF_RSVD56 86#define T10$K_PROF_RSVD57 87#define T10$K_PROF_RSVD58 88#define T10$K_PROF_RSVD59 89|R#define T10$K_PROF_RSVD5A 90#define T10$K_PROF_RSVD5B 91#define T10$K_PROF_RSVD5C 92#define T10$K_PROF_RSVD5D 93#define T10$K_PROF_RSVD5E 94#define T10$K_PROF_RSVD5F 95##define T10$K_PROF_NONCONFORM 65535#define T10$M_TXR46_MEDV1 1#define T10$M_TXR46_MEDV2 2#define T10$M_TXR46_MEDV3 4#define T10$M_TXR46_MEDVX 248 struct txr46fd {2 unsigned short int t10$w_txr46fd_feature_code; __struct {+ unsigned t10$v_txr46fd_current : 1;. unsigned t10$v_txr46 }Rfd_persistent : 1;+ unsigned t10$v_txr46fd_version : 4;. unsigned t10$v_txr46fd_flags_fill : 2; } t10$r_txr46fd_flags;- unsigned char t10$b_txr46fd_extra_length; __union { __struct {< unsigned short int t10$w_txr46fd00_feature_code; __struct {5 unsigned t10$v_txr46fd00_current : 1;8 unsigned t10$v_txr46fd00_persistent : 1;5 unsigned t10$v_txr46fd00_version : 4;8 ~Runsigned t10$v_txr46fd00_flags_fill : 2;( } t10$r_txr46fd00_flags;7 unsigned char t10$b_txr46fd00_extra_length;# } t10$r_txr46fd00 [64]; __struct { __struct {3 unsigned t10$v_txr46fd2a_write : 1;4 unsigned t10$v_txr46fd2a_fill41 : 7;7 unsigned t10$v_txr46fd2a_closeonly : 1;5 unsigned t10$v_txr46fd2a_quickst : 1;4 unsigned t10$v_txr46fd2a_fill52 : 6;( R } t10$r_txr46fd2a_flags;/ unsigned char t10$b_txr46fd_fill60;/ unsigned char t10$b_txr46fd_fill70; __union {: unsigned char t10$b_txr46fd2a_suppmedvers; __struct {; unsigned t10$v_txr46fd2a_suppvers1 : 1;; unsigned t10$v_txr46fd2a_suppvers2 : 1;; unsigned t10$v_txr46fd2a_suppvers3 : 1;; unsigned t10$v_txr46fd2a_suppother : 5;2 R } t10$r_txr46fd2a_suppmedvers;+ } t10$r_txr46fd2a_smvunion;1 unsigned char t10$b_txr46fd2a_fill90;1 unsigned char t10$b_txr46fd2a_filla0;1 unsigned char t10$b_txr46fd2a_fillb0; __union {: unsigned char t10$b_txr46fd2a_currmedvers; __struct {; unsigned t10$v_txr46fd2a_currvers1 : 1;; unsigned t10$v_txr46fd2a_currvers2 : 1;; R unsigned t10$v_txr46fd2a_currvers3 : 1;; unsigned t10$v_txr46fd2a_currother : 5;2 } t10$r_txr46fd2a_currmedvers;+ } t10$r_txr46fd2a_cmvunion;1 unsigned char t10$b_txr46fd2a_filld0;1 unsigned char t10$b_txr46fd2a_fille0;1 unsigned char t10$b_txr46fd2a_fillf0; } t10$r_txr46fd2a; __struct { __struct {3 unsigned t10$v_txr46fd2b_write : 1;4 R unsigned t10$v_txr46fd2b_fill41 : 7;( } t10$r_txr46fd2b_flags;1 unsigned char t10$b_txr46fd2b_fill50;1 unsigned char t10$b_txr46fd2b_fill60;1 unsigned char t10$b_txr46fd2b_fill70; __union {: unsigned char t10$b_txr46fd2b_suppmedvers; __struct {; unsigned t10$v_txr46fd2b_suppvers1 : 1;; unsigned t10$v_txr46fd2b_suppvers2 : 1;; unsigned R t10$v_txr46fd2b_suppvers3 : 1;8 unsigned t10$v_txr46fd2b_fill83 : 5;2 } t10$r_txr46fd2b_suppmedvers;+ } t10$r_txr46fd2b_smvunion;1 unsigned char t10$b_txr46fd2b_fill90;1 unsigned char t10$b_txr46fd2b_filla0;1 unsigned char t10$b_txr46fd2b_fillb0; __union {: unsigned char t10$b_txr46fd2b_currmedvers; __struct {; unsigned t10$v_txr46fd2b_c Rurrvers1 : 1;; unsigned t10$v_txr46fd2b_currvers2 : 1;; unsigned t10$v_txr46fd2b_currvers3 : 1;8 unsigned t10$v_txr46fd2b_fillb3 : 5;2 } t10$r_txr46fd2b_currmedvers;+ } t10$r_txr46fd2b_cmvunion;1 unsigned char t10$b_txr46fd2b_filld0;1 unsigned char t10$b_txr46fd2b_fille0;1 unsigned char t10$b_txr46fd2b_fillf0; } t10$r_txr46fd2b; __struct {9 R unsigned char t10$b_txr46fd2f_additional_len; __struct {4 unsigned t10$v_txr46fd2f_rsvd40 : 1;0 unsigned t10$v_txr46fd2f_rw : 1;5 unsigned t10$v_txr46fd2f_test_wr : 1;4 unsigned t10$v_txr46fd2f_fill43 : 3;1 unsigned t10$v_txr46fd2f_buf : 1;4 unsigned t10$v_txr46fd2f_fill47 : 1;( } t10$r_txr46fd2f_flags;1 unsigned char t10$b_txr46fd2f_fill50;1 R unsigned char t10$b_txr46fd2f_fill60;1 unsigned char t10$b_txr46fd2f_fill70; } t10$r_txr46fd2f; } t10$r_txr46fd_overlay; } ; #if !defined(__VAXC)G#define t10$v_txr46fd_current t10$r_txr46fd_flags.t10$v_txr46fd_currentM#define t10$v_txr46fd_persistent t10$r_txr46fd_flags.t10$v_txr46fd_persistentG#define t10$v_txr46fd_version t10$r_txr46fd_flags.t10$v_txr46fd_version=#define t10$r_txr46fd00 t10$r_txr46fd_overlay.t10$r_txr46fd00A#define t10$w_Rtxr46fd00_feature_code t10$w_txr46fd00_feature_code3#define t10$r_txr46fd00_flags t10$r_txr46fd00_flagsM#define t10$v_txr46fd00_current t10$r_txr46fd00_flags.t10$v_txr46fd00_currentS#define t10$v_txr46fd00_persistent t10$r_txr46fd00_flags.t10$v_txr46fd00_persistentM#define t10$v_txr46fd00_version t10$r_txr46fd00_flags.t10$v_txr46fd00_versionA#define t10$b_txr46fd00_extra_length t10$b_txr46fd00_extra_length=#define t10$r_txr46fd2a t10$r_txr46fd_overlay.t10$r_txr46fd2aC#define t10$r_txr46fRd2a_flags t10$r_txr46fd2a.t10$r_txr46fd2a_flagsI#define t10$v_txr46fd2a_write t10$r_txr46fd2a_flags.t10$v_txr46fd2a_writeQ#define t10$v_txr46fd2a_closeonly t10$r_txr46fd2a_flags.t10$v_txr46fd2a_closeonlyM#define t10$v_txr46fd2a_quickst t10$r_txr46fd2a_flags.t10$v_txr46fd2a_quicksth#define t10$b_txr46fd2a_suppmedvers t10$r_txr46fd2a.t10$r_txr46fd2a_smvunion.t10$b_txr46fd2a_suppmedversh#define t10$r_txr46fd2a_suppmedvers t10$r_txr46fd2a.t10$r_txr46fd2a_smvunion.t10$r_txr46fd2a_suppmedversW#defRine t10$v_txr46fd2a_suppvers1 t10$r_txr46fd2a_suppmedvers.t10$v_txr46fd2a_suppvers1W#define t10$v_txr46fd2a_suppvers2 t10$r_txr46fd2a_suppmedvers.t10$v_txr46fd2a_suppvers2W#define t10$v_txr46fd2a_suppvers3 t10$r_txr46fd2a_suppmedvers.t10$v_txr46fd2a_suppvers3W#define t10$v_txr46fd2a_suppother t10$r_txr46fd2a_suppmedvers.t10$v_txr46fd2a_suppotherh#define t10$b_txr46fd2a_currmedvers t10$r_txr46fd2a.t10$r_txr46fd2a_cmvunion.t10$b_txr46fd2a_currmedversh#define t10$r_txr46fd2a_currmedvers t10$r_txRr46fd2a.t10$r_txr46fd2a_cmvunion.t10$r_txr46fd2a_currmedversW#define t10$v_txr46fd2a_currvers1 t10$r_txr46fd2a_currmedvers.t10$v_txr46fd2a_currvers1W#define t10$v_txr46fd2a_currvers2 t10$r_txr46fd2a_currmedvers.t10$v_txr46fd2a_currvers2W#define t10$v_txr46fd2a_currvers3 t10$r_txr46fd2a_currmedvers.t10$v_txr46fd2a_currvers3W#define t10$v_txr46fd2a_currother t10$r_txr46fd2a_currmedvers.t10$v_txr46fd2a_currother=#define t10$r_txr46fd2b t10$r_txr46fd_overlay.t10$r_txr46fd2bC#define t10$r_txr46fRd2b_flags t10$r_txr46fd2b.t10$r_txr46fd2b_flagsI#define t10$v_txr46fd2b_write t10$r_txr46fd2b_flags.t10$v_txr46fd2b_writeh#define t10$b_txr46fd2b_suppmedvers t10$r_txr46fd2b.t10$r_txr46fd2b_smvunion.t10$b_txr46fd2b_suppmedversh#define t10$r_txr46fd2b_suppmedvers t10$r_txr46fd2b.t10$r_txr46fd2b_smvunion.t10$r_txr46fd2b_suppmedversW#define t10$v_txr46fd2b_suppvers1 t10$r_txr46fd2b_suppmedvers.t10$v_txr46fd2b_suppvers1W#define t10$v_txr46fd2b_suppvers2 t10$r_txr46fd2b_suppmedvers.t10$v_txr46fd2b_Rsuppvers2W#define t10$v_txr46fd2b_suppvers3 t10$r_txr46fd2b_suppmedvers.t10$v_txr46fd2b_suppvers3h#define t10$b_txr46fd2b_currmedvers t10$r_txr46fd2b.t10$r_txr46fd2b_cmvunion.t10$b_txr46fd2b_currmedversh#define t10$r_txr46fd2b_currmedvers t10$r_txr46fd2b.t10$r_txr46fd2b_cmvunion.t10$r_txr46fd2b_currmedversW#define t10$v_txr46fd2b_currvers1 t10$r_txr46fd2b_currmedvers.t10$v_txr46fd2b_currvers1W#define t10$v_txr46fd2b_currvers2 t10$r_txr46fd2b_currmedvers.t10$v_txr46fd2b_currvers2W#define t10$Rv_txr46fd2b_currvers3 t10$r_txr46fd2b_currmedvers.t10$v_txr46fd2b_currvers3=#define t10$r_txr46fd2f t10$r_txr46fd_overlay.t10$r_txr46fd2fU#define t10$b_txr46fd2f_additional_len t10$r_txr46fd2f.t10$b_txr46fd2f_additional_lenC#define t10$r_txr46fd2f_flags t10$r_txr46fd2f.t10$r_txr46fd2f_flagsC#define t10$v_txr46fd2f_rw t10$r_txr46fd2f_flags.t10$v_txr46fd2f_rwM#define t10$v_txr46fd2f_test_wr t10$r_txr46fd2f_flags.t10$v_txr46fd2f_test_wrE#define t10$v_txr46fd2f_buf t10$r_txr46fd2f_flags.t10$v_Rtxr46fd2f_buf"#endif /* #if !defined(__VAXC) */  struct txr46fl {2 unsigned short int t10$w_txr46fl_feature_code; __struct {+ unsigned t10$v_txr46fl_current : 1;. unsigned t10$v_txr46fl_persistent : 1;+ unsigned t10$v_txr46fl_version : 4;. unsigned t10$v_txr46fl_flags_fill : 2; } t10$r_txr46fl_flags;/ unsigned char t10$b_txr46fl_additional_len; __struct {8 unsigned short int t10$w_txr46flpd_feature_code; __st Rruct {1 unsigned t10$v_txr46flpd_current : 1;/ unsigned t10$v_txr46flpd_fill1 : 7;$ } t10$r_txr46flpd_flags;/ unsigned char t10$b_txr46flpd_reserved;" } t10$r_txr46flpd [65536]; } ; #if !defined(__VAXC)G#define t10$v_txr46fl_current t10$r_txr46fl_flags.t10$v_txr46fl_currentM#define t10$v_txr46fl_persistent t10$r_txr46fl_flags.t10$v_txr46fl_persistentG#define t10$v_txr46fl_version t10$r_txr46fl_flags.t10$v_txr46fl_versionA#definRe t10$w_txr46flpd_feature_code t10$w_txr46flpd_feature_code3#define t10$r_txr46flpd_flags t10$r_txr46flpd_flagsM#define t10$v_txr46flpd_current t10$r_txr46flpd_flags.t10$v_txr46flpd_current"#endif /* #if !defined(__VAXC) */ #define T10$K_TXR46PD_LENGTH 4 struct txr46pd {- unsigned short int t10$w_txr46pd_profile; __struct {+ unsigned t10$v_txr46pd_current : 1;* unsigned t10$v_txr46pd_fill21 : 7; } t10$r_txr46pd_flags;' unsigned char t10$b_txr4R6pd_fill30; } ; #if !defined(__VAXC)G#define t10$v_txr46pd_current t10$r_txr46pd_flags.t10$v_txr46pd_current"#endif /* #if !defined(__VAXC) */  struct txc4a {% unsigned char t10$b_txc4a_opcode; __struct {( unsigned t10$v_txc4a_polled : 1;- unsigned t10$v_txc4a_flags_rsvd1 : 7; } t10$r_txc4a_flags;$ unsigned char t10$b_txc4a_fill2;$ unsigned char t10$b_txc4a_fill3; __struct {, unsigned t10$v_txc4a_gesn_rsvd0 : 1;/ R unsigned t10$v_txc4a_gesn_opchange : 1;, unsigned t10$v_txc4a_gesn_power : 1;- unsigned t10$v_txc4a_gesn_extreq : 1;, unsigned t10$v_txc4a_gesn_media : 1;, unsigned t10$v_txc4a_gesn_multi : 1;. unsigned t10$v_txc4a_gesn_devbusy : 1;, unsigned t10$v_txc4a_gesn_rsvd7 : 1;" } t10$r_txc4a_req_classes;$ unsigned char t10$b_txc4a_fill5;$ unsigned char t10$b_txc4a_fill6;* unsigned short int t10$w_txc4a_length;& unsigned char t10$b_ Rtxc4a_control; } ; #if !defined(__VAXC)?#define t10$v_txc4a_polled t10$r_txc4a_flags.t10$v_txc4a_polledS#define t10$v_txc4a_gesn_opchange t10$r_txc4a_req_classes.t10$v_txc4a_gesn_opchangeM#define t10$v_txc4a_gesn_power t10$r_txc4a_req_classes.t10$v_txc4a_gesn_powerO#define t10$v_txc4a_gesn_extreq t10$r_txc4a_req_classes.t10$v_txc4a_gesn_extreqM#define t10$v_txc4a_gesn_media t10$r_txc4a_req_classes.t10$v_txc4a_gesn_mediaM#define t10$v_txc4a_gesn_multi t10$r_txc4a_req_classes.t10$vR_txc4a_gesn_multiQ#define t10$v_txc4a_gesn_devbusy t10$r_txc4a_req_classes.t10$v_txc4a_gesn_devbusy"#endif /* #if !defined(__VAXC) */ #define T10$K_TXR4A_GESN_NONE 0##define T10$K_TXR4A_GESN_OPCHANGE 1 #define T10$K_TXR4A_GESN_POWER 2!#define T10$K_TXR4A_GESN_EXTREQ 3 #define T10$K_TXR4A_GESN_MEDIA 4 #define T10$K_TXR4A_GESN_MULTI 5$#define T10$K_TXR4A_GESN_DEVBUSY 272$#define T10$K_TXR4ANC001_EVT_NOCHG 0%#define T10$K_TXR4ANC001_EVT_CHGING 1$#define T10$K_TXR4ANC001_EVT_CHGED 2R$#define T10$K_TXR4ANC001_STS_AVAIL 0##define T10$K_TXR4ANC001_STS_BUSY 1##define T10$K_TXR4ANC001_STS_RSVD 2$#define T10$K_TXR4ANC001_CHG_NOCHG 0$#define T10$K_TXR4ANC001_CHG_CFEAT 1$#define T10$K_TXR4ANC001_CHG_NFEAT 2$#define T10$K_TXR4ANC001_CHG_RESET 3$#define T10$K_TXR4ANC001_CHG_CFIRM 4$#define T10$K_TXR4ANC001_CHG_CINQD 5$#define T10$K_TXR4ANC010_EVT_NOCHG 0$#define T10$K_TXR4ANC010_EVT_CHGOK 1$#define T10$K_TXR4ANC010_EVT_CHGNG 2##define T10$K_TXR4ANC010_STS_RSVD 0%#define T1R0$K_TXR4ANC010_STS_ACTIVE 1##define T10$K_TXR4ANC010_STS_IDLE 2%#define T10$K_TXR4ANC010_STS_STNDBY 3$#define T10$K_TXR4ANC010_STS_SLEEP 4$#define T10$K_TXR4ANC011_EVT_NOCHG 0$#define T10$K_TXR4ANC011_EVT_KEYDN 1$#define T10$K_TXR4ANC011_EVT_KEYUP 2%#define T10$K_TXR4ANC011_EVT_EXTREQ 3$#define T10$K_TXR4ANC011_STS_READY 0%#define T10$K_TXR4ANC011_STS_OTHPRV 1$#define T10$K_TXR4ANC011_EXT_NOREQ 0$#define T10$K_TXR4ANC011_EXT_OVRUN 1%#define T10$K_TXR4ANC011_EXT_PLAY 257$#define T10$RK_TXR4ANC011_EXT_REW 258%#define T10$K_TXR4ANC011_EXT_FFWD 259%#define T10$K_TXR4ANC011_EXT_PAUS 260%#define T10$K_TXR4ANC011_EXT_STOP 262%#define T10$K_TXR4ANC011_EXT_ASCL 512%#define T10$K_TXR4ANC011_EXT_ASCH 767'#define T10$K_TXR4ANC011_EXT_VNDL 61440'#define T10$K_TXR4ANC011_EXT_VNDH 65535$#define T10$K_TXR4ANC100_MED_NOCHG 0$#define T10$K_TXR4ANC100_MED_EJECT 1"#define T10$K_TXR4ANC100_MED_NEW 2"#define T10$K_TXR4ANC100_MED_REM 3"#define T10$K_TXR4ANC100_MED_CHG 4%#define T10$RK_TXR4ANC100_MED_BGFDON 5%#define T10$K_TXR4ANC100_MED_BGFRES 6$#define T10$K_TXR4ANC110_BSY_NOCHG 0"#define T10$K_TXR4ANC110_BSY_CHG 1"#define T10$K_TXR4ANC110_BSY_NOT 0##define T10$K_TXR4ANC110_BSY_BUSY 1 struct txr4a {/ unsigned short int t10$w_txr4a_data_length; __struct {1 unsigned t10$v_txr4a_gesn_curr_event : 3;- unsigned t10$v_txc4a_flags_rsvd4 : 4;% unsigned t10$v_txr4a_nea : 1; } t10$r_txr4a_flags; __struct {, unsign Red t10$v_txr4a_gesn_rsvd0 : 1;/ unsigned t10$v_txr4a_gesn_opchange : 1;, unsigned t10$v_txr4a_gesn_power : 1;- unsigned t10$v_txr4a_gesn_extreq : 1;, unsigned t10$v_txr4a_gesn_media : 1;, unsigned t10$v_txr4a_gesn_multi : 1;. unsigned t10$v_txr4a_gesn_devbusy : 1;, unsigned t10$v_txr4a_gesn_rsvd7 : 1;# } t10$r_txr4a_supp_classes; __union { __struct { __struct {4 unsigned t10$v_txr4anc001_ Revent : 4;4 unsigned t10$v_txr4anc001_rsvd4 : 4;) } t10$r_txr4anc001_flags; __struct {5 unsigned t10$v_txr4anc001_status : 4;4 unsigned t10$v_txr4anc001_rsvd4 : 3;7 unsigned t10$v_txr4anc001_persprev : 1;) } t10$r_txr4anc001_state;7 unsigned short int t10$w_txr4anc001_change; } t10$r_txr4anc001; __struct { __struct {4 un Rsigned t10$v_txr4anc010_event : 4;4 unsigned t10$v_txr4anc010_rsvd4 : 4;) } t10$r_txr4anc010_flags;2 unsigned char t10$b_txr4anc010_status;1 unsigned char t10$b_txr4anc010_rsvd2;1 unsigned char t10$b_txr4anc010_rsvd3; } t10$r_txr4anc010; __struct { __struct {4 unsigned t10$v_txr4anc011_event : 4;4 unsigned t10$v_txr4anc011_rsvd4 : 4;) } t10$r_tx Rr4anc011_flags; __struct {5 unsigned t10$v_txr4anc011_status : 4;4 unsigned t10$v_txr4anc011_rsvd4 : 3;7 unsigned t10$v_txr4anc011_persprev : 1;) } t10$r_txr4anc011_state;7 unsigned short int t10$w_txr4anc011_extreq; } t10$r_txr4anc011; __struct { __struct {4 unsigned t10$v_txr4anc100_event : 4;4 unsigned t10$v_txr4anc100_rsvd4 : 4;) R } t10$r_txr4anc100_flags; __struct {8 unsigned t10$v_txr4anc100_door_open : 1;< unsigned t10$v_txr4anc100_media_present : 1;4 unsigned t10$v_txr4anc100_rsvd3 : 6;* } t10$r_txr4anc100_status;1 unsigned char t10$b_txr4anc100_rsvd2;1 unsigned char t10$b_txr4anc100_rsvd3; } t10$r_txr4anc100; __struct { __struct {4 unsigned t10$v_txr R4anc110_event : 4;4 unsigned t10$v_txr4anc110_rsvd4 : 4;) } t10$r_txr4anc110_flags;6 unsigned char t10$b_txr4anc110_bsy_status;5 unsigned short int t10$w_txr4anc110_time; } t10$r_txr4anc110; } t10$r_txr4a_ncoverlay; } ; #if !defined(__VAXC)Q#define t10$v_txr4a_gesn_curr_event t10$r_txr4a_flags.t10$v_txr4a_gesn_curr_event9#define t10$v_txr4a_nea t10$r_txr4a_flags.t10$v_txr4a_neaT#define t10$v_txr4a_gesn_opcRhange t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_opchangeN#define t10$v_txr4a_gesn_power t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_powerP#define t10$v_txr4a_gesn_extreq t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_extreqN#define t10$v_txr4a_gesn_media t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_mediaN#define t10$v_txr4a_gesn_multi t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_multiR#define t10$v_txr4a_gesn_devbusy t10$r_txr4a_supp_classes.t10$v_txr4a_gesn_devbusy?#define t10$r_txr4anc001 t10$r_txr4a_ncoveRrlay.t10$r_txr4anc001F#define t10$r_txr4anc001_flags t10$r_txr4anc001.t10$r_txr4anc001_flagsL#define t10$v_txr4anc001_event t10$r_txr4anc001_flags.t10$v_txr4anc001_eventF#define t10$r_txr4anc001_state t10$r_txr4anc001.t10$r_txr4anc001_stateN#define t10$v_txr4anc001_status t10$r_txr4anc001_state.t10$v_txr4anc001_statusR#define t10$v_txr4anc001_persprev t10$r_txr4anc001_state.t10$v_txr4anc001_persprevH#define t10$w_txr4anc001_change t10$r_txr4anc001.t10$w_txr4anc001_change?#define t10$r_txr4anc0R10 t10$r_txr4a_ncoverlay.t10$r_txr4anc010F#define t10$r_txr4anc010_flags t10$r_txr4anc010.t10$r_txr4anc010_flagsL#define t10$v_txr4anc010_event t10$r_txr4anc010_flags.t10$v_txr4anc010_eventH#define t10$b_txr4anc010_status t10$r_txr4anc010.t10$b_txr4anc010_statusF#define t10$b_txr4anc010_rsvd2 t10$r_txr4anc010.t10$b_txr4anc010_rsvd2F#define t10$b_txr4anc010_rsvd3 t10$r_txr4anc010.t10$b_txr4anc010_rsvd3?#define t10$r_txr4anc011 t10$r_txr4a_ncoverlay.t10$r_txr4anc011F#define t10$r_txr4anc011_flaRgs t10$r_txr4anc011.t10$r_txr4anc011_flagsL#define t10$v_txr4anc011_event t10$r_txr4anc011_flags.t10$v_txr4anc011_eventF#define t10$r_txr4anc011_state t10$r_txr4anc011.t10$r_txr4anc011_stateN#define t10$v_txr4anc011_status t10$r_txr4anc011_state.t10$v_txr4anc011_statusR#define t10$v_txr4anc011_persprev t10$r_txr4anc011_state.t10$v_txr4anc011_persprevH#define t10$w_txr4anc011_extreq t10$r_txr4anc011.t10$w_txr4anc011_extreq?#define t10$r_txr4anc100 t10$r_txr4a_ncoverlay.t10$r_txr4anc100F#define Rt10$r_txr4anc100_flags t10$r_txr4anc100.t10$r_txr4anc100_flagsL#define t10$v_txr4anc100_event t10$r_txr4anc100_flags.t10$v_txr4anc100_eventH#define t10$r_txr4anc100_status t10$r_txr4anc100.t10$r_txr4anc100_statusU#define t10$v_txr4anc100_door_open t10$r_txr4anc100_status.t10$v_txr4anc100_door_open]#define t10$v_txr4anc100_media_present t10$r_txr4anc100_status.t10$v_txr4anc100_media_presentF#define t10$b_txr4anc100_rsvd2 t10$r_txr4anc100.t10$b_txr4anc100_rsvd2F#define t10$b_txr4anc100_rsvd3 t10 R$r_txr4anc100.t10$b_txr4anc100_rsvd3?#define t10$r_txr4anc110 t10$r_txr4a_ncoverlay.t10$r_txr4anc110F#define t10$r_txr4anc110_flags t10$r_txr4anc110.t10$r_txr4anc110_flagsL#define t10$v_txr4anc110_event t10$r_txr4anc110_flags.t10$v_txr4anc110_eventP#define t10$b_txr4anc110_bsy_status t10$r_txr4anc110.t10$b_txr4anc110_bsy_statusD#define t10$w_txr4anc110_time t10$r_txr4anc110.t10$w_txr4anc110_time"#endif /* #if !defined(__VAXC) */  struct txc51 {% unsigned char t10$b_txc51_opcode;$R unsigned char t10$b_txc51_rsvd1;$ unsigned char t10$b_txc51_rsvd2;$ unsigned char t10$b_txc51_rsvd3;$ unsigned char t10$b_txc51_rsvd4;$ unsigned char t10$b_txc51_rsvd5;$ unsigned char t10$b_txc51_rsvd6;* unsigned short int t10$w_txc51_length;& unsigned char t10$b_txc51_control; } ;#define T10$K_TXR51_DSTAT_EMP 0#define T10$K_TXR51_DSTAT_INC 1#define T10$K_TXR51_DSTAT_FIN 2#define T10$K_TXR51_DSTAT_OTH 3#define T10$K_TXR51_SSTAT_EMP 0#define T10$K_RTXR51_SSTAT_INC 1#define T10$K_TXR51_SSTAT_RSV 2#define T10$K_TXR51_SSTAT_OK 3#define T10$K_TXR51_BGFS_UNF 0#define T10$K_TXR51_BGFS_PAUS 1#define T10$K_TXR51_BGFS_UNDW 2#define T10$K_TXR51_BGFS_FMTD 3!#define T10$K_TXR51_CDTYP_CDROM 0 #define T10$K_TXR51_CDTYP_CDI 16!#define T10$K_TXR51_CDTYP_CDXA 32##define T10$K_TXR51_CDTYP_OTHER 255 struct txr51 {* unsigned short int t10$w_txr51_length; __struct {- unsigned t10$v_txr51_disk_status : 2;- unsi Rgned t10$v_txr51_sess_status : 2;* unsigned t10$v_txr51_erasable : 1;( unsigned t10$v_txr51_rsvd25 : 1;# unsigned t10$v_fill_1_ : 2; } t10$r_txr51_state;( unsigned char t10$b_txr51_1st_track;' unsigned char t10$b_txr51_sess_lsb;, unsigned char t10$b_txr51_1st_track_lsb;- unsigned char t10$b_txr51_last_track_lsb; __struct {, unsigned t10$v_txr51_bgf_status : 2;& unsigned t10$v_txr51_dbit : 1;( unsigned t10$v_txr51_rsvd7 R3 : 1;% unsigned t10$v_txr51_uru : 1;' unsigned t10$v_txr51_dbc_v : 1;' unsigned t10$v_txr51_did_v : 1;# unsigned t10$v_fill_2_ : 1; } t10$r_txr51_format;' unsigned char t10$b_txr51_disktype;' unsigned char t10$b_txr51_sess_msb;, unsigned char t10$b_txr51_1st_track_msb;- unsigned char t10$b_txr51_last_track_msb;% unsigned int t10$l_txr51_disk_id;) unsigned int t10$l_txr51_leadin_addr;* unsigned int t10$l_txr51_leadout_addr; R% unsigned int t10$l_txr51_barcode;% unsigned char t10$b_txr51_rsvd32;) unsigned char t10$b_txr51_opc_tables; __struct {- unsigned short int t10$w_txr51_speed;6 unsigned char t10$x_txr51_opc_vendor_data [6]; } t10$r_txr51opc [32]; } ; #if !defined(__VAXC)I#define t10$v_txr51_disk_status t10$r_txr51_state.t10$v_txr51_disk_statusI#define t10$v_txr51_sess_status t10$r_txr51_state.t10$v_txr51_sess_statusC#define t10$v_txr51_erasable t10$r_txr R51_state.t10$v_txr51_erasableH#define t10$v_txr51_bgf_status t10$r_txr51_format.t10$v_txr51_bgf_status<#define t10$v_txr51_dbit t10$r_txr51_format.t10$v_txr51_dbit:#define t10$v_txr51_uru t10$r_txr51_format.t10$v_txr51_uru>#define t10$v_txr51_dbc_v t10$r_txr51_format.t10$v_txr51_dbc_v>#define t10$v_txr51_did_v t10$r_txr51_format.t10$v_txr51_did_v+#define t10$w_txr51_speed t10$w_txr51_speed?#define t10$x_txr51_opc_vendor_data t10$x_txr51_opc_vendor_data"#endif /* #if !defined(__VAXC) */ R#define T10$K_TXC52_LBA 0!#define T10$K_TXC52_TRACK_RZONE 1#define T10$K_TXC52_SESSION 2#define T10$K_TXC52_RSVD 3 struct txc52 {% unsigned char t10$b_txc52_opcode; __struct {* unsigned t10$v_txc52_addr_num : 2;+ unsigned t10$v_txc52_flag_fill : 6; } t10$r_txc52_flags;% unsigned int t10$l_txc52_address;$ unsigned char t10$b_txc52_rsvd6;- unsigned short int t10$w_txc52_alloc_len;& unsigned char t10$b_txc52_control; } ; #iRf !defined(__VAXC)C#define t10$v_txc52_addr_num t10$r_txc52_flags.t10$v_txc52_addr_num"#endif /* #if !defined(__VAXC) */ #define T10$M_QSUB_AUD_MASK 13#define T10$M_QSUB_DATA_MASK 4#define T10$M_QSUB_COPY_MASK 2#define T10$K_QSUB_00X0 0#define T10$K_QSUB_00X1 1#define T10$K_QSUB_10X0 8#define T10$K_QSUB_10X1 9#define T10$K_QSUB_01X0 4#define T10$K_QSUB_01X1 5#define T10$K_QSUB_DDCD 4#define T10$K_TX52_SESSION 2#define T10$K_TX52_RSVD 3#define T10$K_DATA_MODE1 1R#define T10$K_DATA_MODE2 2#define T10$K_DATA_UNKNOWN 15 struct txr52 {/ unsigned short int t10$w_txr52_data_length;( unsigned char t10$b_txr52_track_lsb;' unsigned char t10$b_txr52_sess_lsb;$ unsigned char t10$b_txr52_fill4; __struct {* unsigned t10$v_txr52_trk_mode : 4;& unsigned t10$v_txr52_copy : 1;( unsigned t10$v_txr52_damage : 1;' unsigned t10$v_txr52_rsvd6 : 2; } t10$r_txr52_flags5; __struct {+ unsignedR t10$v_txr52_data_mode : 4;$ unsigned t10$v_txr52_fp : 1;) unsigned t10$v_txr52_pck_inc : 1;' unsigned t10$v_txr52_blank : 1;$ unsigned t10$v_txr52_rt : 1; } t10$r_txr52_flags6; __struct {' unsigned t10$v_txr52_nwa_v : 1;' unsigned t10$v_txr52_lra_v : 1;. unsigned t10$v_txr52_flags7_rsvd6 : 6; } t10$r_txr52_flags7;) unsigned int t10$l_txr52_track_start;( unsigned int t10$l_txr52_next_write;) unsigned i Rnt t10$l_txr52_free_blocks;* unsigned int t10$l_txr52_block_factor;( unsigned int t10$l_txr52_track_size;* unsigned int t10$l_txr52_last_address;( unsigned char t10$b_txr52_track_msb;' unsigned char t10$b_txr52_sess_msb;* unsigned short int t10$w_txr52_fill34; } ; #if !defined(__VAXC)D#define t10$v_txr52_trk_mode t10$r_txr52_flags5.t10$v_txr52_trk_mode<#define t10$v_txr52_copy t10$r_txr52_flags5.t10$v_txr52_copy@#define t10$v_txr52_damage t10$r_txr52_flags5.t10$ Rv_txr52_damageF#define t10$v_txr52_data_mode t10$r_txr52_flags6.t10$v_txr52_data_mode8#define t10$v_txr52_fp t10$r_txr52_flags6.t10$v_txr52_fpB#define t10$v_txr52_pck_inc t10$r_txr52_flags6.t10$v_txr52_pck_inc>#define t10$v_txr52_blank t10$r_txr52_flags6.t10$v_txr52_blank8#define t10$v_txr52_rt t10$r_txr52_flags6.t10$v_txr52_rt>#define t10$v_txr52_nwa_v t10$r_txr52_flags7.t10$v_txr52_nwa_v>#define t10$v_txr52_lra_v t10$r_txr52_flags7.t10$v_txr52_lra_v"#endif /* #if !defined(__VAXC) */  Rstruct txc53 {% unsigned char t10$b_txc53_opcode;$ unsigned char t10$b_txc53_rsvd1;$ unsigned char t10$b_txc53_rsvd2;$ unsigned char t10$b_txc53_rsvd3;$ unsigned char t10$b_txc53_rsvd4;% unsigned int t10$l_txc53_sectors;& unsigned char t10$b_txc53_control; } ; struct txc55 {% unsigned char t10$b_txc55_opcode; __struct {$ unsigned t10$v_txc55_sp : 1;( unsigned t10$v_txc55_fill11 : 3;$ unsigned t10$v_txc55_pf : 1;( unRsigned t10$v_txc55_fill15 : 3; } t10$r_txc55_flags;% unsigned char t10$b_txc55_fill20;% unsigned char t10$b_txc55_fill30;% unsigned char t10$b_txc55_fill40;% unsigned char t10$b_txc55_fill50;% unsigned char t10$b_txc55_fill60;* unsigned short int t10$w_txc55_length;& unsigned char t10$b_txc55_control; } ; #if !defined(__VAXC)7#define t10$v_txc55_sp t10$r_txc55_flags.t10$v_txc55_sp7#define t10$v_txc55_pf t10$r_txc55_flags.t10$v_txc55_pf"#endif R/* #if !defined(__VAXC) */ #define T10$K_TXC5B_FUNC_FMT 0#define T10$K_TXC5B_FUNC_TRK 1#define T10$K_TXC5B_FUNC_SES 2#define T10$K_TXC5B_FUNC_SPC 3 #define T10$K_TXC5B_FUNC_SESFD 5 #define T10$K_TXC5B_FINALIZE 154 struct txc5b {% unsigned char t10$b_txc5b_opcode; __struct {* unsigned t10$v_txc5b_fl_immed : 1;) unsigned t10$v_txc5b_fl_fill : 7; } t10$r_txc5b_flags; __struct {, unsigned t10$v_txc5b_func_close : 3;+ unsigned tR10$v_txc5b_func_fill : 5; } t10$r_txc5b_func;% unsigned char t10$b_txc5b_rsvd30;) unsigned short int t10$w_txc5b_track;$ unsigned char t10$b_txc5b_rsvd6;$ unsigned char t10$b_txc5b_rsvd7;$ unsigned char t10$b_txc5b_rsvd8;& unsigned char t10$b_txc5b_control; } ; #if !defined(__VAXC)C#define t10$v_txc5b_fl_immed t10$r_txc5b_flags.t10$v_txc5b_fl_immedF#define t10$v_txc5b_func_close t10$r_txc5b_func.t10$v_txc5b_func_close"#endif /* #if !defined(__VAXC) R*/ #define T10$K_MP_MMCAP 42#define T10$K_MP_WRITEPARAM 5#define T10$K_MP_TMO_PROT 5#define T10$K_TXC5A_PC_CURR 0#define T10$K_TXC5A_PC_CHNG 1#define T10$K_TXC5A_PC_DFLT 2#define T10$K_TXC5A_PC_SAVE 3 struct txc5a {% unsigned char t10$b_txc5a_opcode; __struct {( unsigned t10$v_txc5a_fill10 : 3;% unsigned t10$v_txc5a_dbd : 1;& unsigned t10$v_txc5a_llba : 1;( unsigned t10$v_txc5a_fill15 : 3; } t10$r_txc5a_flags; __stRruct {& unsigned t10$v_txc5a_page : 6;& unsigned t10$v_txc5a_ctrl : 2; } t10$r_txc5a_pagectrl;& unsigned char t10$b_txc5a_subpage;% unsigned char t10$b_txc5a_fill40;% unsigned char t10$b_txc5a_fill50;% unsigned char t10$b_txc5a_fill60;* unsigned short int t10$w_txc5a_length;& unsigned char t10$b_txc5a_control; } ; #if !defined(__VAXC)9#define t10$v_txc5a_dbd t10$r_txc5a_flags.t10$v_txc5a_dbd;#define t10$v_txc5a_llba t10$r_txc5a_flagsR.t10$v_txc5a_llba?#define t10$v_txc5a_fill15 t10$r_txc5a_flags.t10$v_txc5a_fill15>#define t10$v_txc5a_page t10$r_txc5a_pagectrl.t10$v_txc5a_page>#define t10$v_txc5a_ctrl t10$r_txc5a_pagectrl.t10$v_txc5a_ctrl"#endif /* #if !defined(__VAXC) */  struct txca8 {% unsigned char t10$b_txca8_opcode; __struct {( unsigned t10$v_txca8_reladr : 1;' unsigned t10$v_txca8_fill1 : 2;% unsigned t10$v_txca8_fua : 1;% unsigned t10$v_txca8_dpo : 1;' unRsigned t10$v_txca8_fill2 : 3; } t10$r_txca8_flags1;! unsigned int t10$l_txca8_lba;$ unsigned int t10$l_txca8_blocks; __struct {) unsigned t10$v_txca8_fill100 : 7;( unsigned t10$v_txca8_stream : 1; } t10$r_txca8_flags10;& unsigned char t10$b_txca8_control; } ; #if !defined(__VAXC)@#define t10$v_txca8_reladr t10$r_txca8_flags1.t10$v_txca8_reladr:#define t10$v_txca8_fua t10$r_txca8_flags1.t10$v_txca8_fua:#define t10$v_txca8_dpo t10$r_Rtxca8_flags1.t10$v_txca8_dpoA#define t10$v_txca8_stream t10$r_txca8_flags10.t10$v_txca8_stream"#endif /* #if !defined(__VAXC) */ #define T10$K_BT_FULL 0#define T10$K_BT_QUICK 1#define T10$K_BT_TRACK 2#define T10$K_BT_UNRES_TRACK 3#define T10$K_BT_TAIL_TRACK 4#define T10$K_BT_UNCLOSE_SESS 5#define T10$K_BT_ERASE_SESS 6 struct txca1 {% unsigned char t10$b_txca1_opcode; __struct {+ unsigned t10$v_txca1_blanktype : 3;( unsigned t10$v_txca1_fill13 R: 1;' unsigned t10$v_txca1_immed : 1;( unsigned t10$v_txca1_fill15 : 3; } t10$r_txca1_flags1;# unsigned int t10$l_txca1_start;% unsigned char t10$b_txca1_fill60;% unsigned char t10$b_txca1_fill70;% unsigned char t10$b_txca1_fill80;% unsigned char t10$b_txca1_fill90;% unsigned char t10$b_txca1_filla0;& unsigned char t10$b_txca1_control; } ; #if !defined(__VAXC)F#define t10$v_txca1_blanktype t10$r_txca1_flags1.t10$v_txca1_blanktypeR>#define t10$v_txca1_immed t10$r_txca1_flags1.t10$v_txca1_immed"#endif /* #if !defined(__VAXC) */  struct txcaa {% unsigned char t10$b_txcaa_opcode; __struct {' unsigned t10$v_txcaa_fill1 : 3;% unsigned t10$v_txcaa_fua : 1;' unsigned t10$v_txcaa_fill2 : 4; } t10$r_txcaa_flags;! unsigned int t10$l_txcaa_lba;$ unsigned int t10$l_txcaa_blocks; __struct {) unsigned t10$v_txcaa_fill100 : 7;( unsigned t10$v_txcaa_strReam : 1; } t10$r_txcaa_flags10;& unsigned char t10$b_txcaa_control; } ; #if !defined(__VAXC)9#define t10$v_txcaa_fua t10$r_txcaa_flags.t10$v_txcaa_fuaA#define t10$v_txcaa_stream t10$r_txcaa_flags10.t10$v_txcaa_stream"#endif /* #if !defined(__VAXC) */ #define T10$K_TXCAD_FMT_PHY 0 struct txcad {% unsigned char t10$b_txcad_opcode;$ unsigned char t10$b_txcad_fill1;" unsigned int t10$l_txcad_addr;$ unsigned char t10$b_txcad_layer;% unsigned chaRr t10$b_txcad_format;* unsigned short int t10$w_txcad_length; __struct {& unsigned t10$v_txcad_rsvd : 6;& unsigned t10$v_txcad_agid : 2; } t10$r_txcad_flags;& unsigned char t10$b_txcad_control; } ; #if !defined(__VAXC);#define t10$v_txcad_agid t10$r_txcad_flags.t10$v_txcad_agid"#endif /* #if !defined(__VAXC) */ #define T10$K_TXRAD_FIXED 4#define T10$K_BKT_DVDROM 0#define T10$K_BKT_DVDRAM 1#define T10$K_BKT_DVDMR 2#define T10$K_BKT_RDVDMRW 3#define T10$K_BKT_DVDRW 9#define T10$K_BKT_DVDPR 10#define T10$K_MXR_1X 0#define T10$K_MXR_2X 1#define T10$K_MXR_4X 2#define T10$K_MXR_8X 3#define T10$K_MXR_NOTSPEC 15#define T10$K_DSZ_120MM 0#define T10$K_DSZ_80MM 0#define T10$K_TXRAD_LENGTH 2052 struct txrad {/ unsigned short int t10$w_txrad_data_length;# unsigned char t10$b_txab_rsvd1;# unsigned char t10$b_txab_rsvd2; __union { __struct { __struct {6 Runsigned t10$v_txrad_fc00_partver : 4;5 unsigned t10$v_txrad_fc00_bktype : 4;6 unsigned t10$v_txrad_fc00_maxrate : 4;6 unsigned t10$v_txrad_fc00_dvdsize : 4;7 unsigned t10$v_txrad_fc00_romlayer : 1;6 unsigned t10$v_txrad_fc00_r_layer : 1;7 unsigned t10$v_txrad_fc00_rw_layer : 1;7 unsigned t10$v_txrad_fc00_unklayer : 1;5 unsigned t10$v_txrad_fc00_tkpath : 1;5 R unsigned t10$v_txrad_fc00_layers : 2;5 unsigned t10$v_txrad_fc00_rsvd27 : 1;5 unsigned t10$v_txrad_fc00_tkdens : 4;6 unsigned t10$v_txrad_fc00_lndense : 4;' } t10$r_txrad_fc00_hdr;1 unsigned int t10$l_txrad_fc00_datalo;1 unsigned int t10$l_txrad_fc00_datahi;1 unsigned int t10$l_txrad_fc00_zerohi; __struct {6 unsigned t10$v_txrad_fc00_fill100 : 7;2 R unsigned t10$v_txrad_fc00_bca : 4;+ unsigned t10$v_fill_3_ : 5;( } t10$r_txrads_fc00_bca;9 unsigned char t10$b_txrad_fc00_junque [2030]; } t10$r_txrad_fc00; } t10$r_txrad_fcoverlay; } ; #if !defined(__VAXC)?#define t10$r_txrad_fc00 t10$r_txrad_fcoverlay.t10$r_txrad_fc00B#define t10$r_txrad_fc00_hdr t10$r_txrad_fc00.t10$r_txrad_fc00_hdrN#define t10$v_txrad_fc00_partver t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_partverL#dRefine t10$v_txrad_fc00_bktype t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_bktypeN#define t10$v_txrad_fc00_maxrate t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_maxrateN#define t10$v_txrad_fc00_dvdsize t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_dvdsizeP#define t10$v_txrad_fc00_romlayer t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_romlayerN#define t10$v_txrad_fc00_r_layer t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_r_layerP#define t10$v_txrad_fc00_rw_layer t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_rw_layerP#define t10$v_txrad_fc00_uRnklayer t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_unklayerL#define t10$v_txrad_fc00_tkpath t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_tkpathL#define t10$v_txrad_fc00_layers t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_layersL#define t10$v_txrad_fc00_tkdens t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_tkdensN#define t10$v_txrad_fc00_lndense t10$r_txrad_fc00_hdr.t10$v_txrad_fc00_lndenseH#define t10$l_txrad_fc00_datalo t10$r_txrad_fc00.t10$l_txrad_fc00_dataloH#define t10$l_txrad_fc00_datahi t10$r_txrad_fc00.t10$l_txrad_f Rc00_datahiH#define t10$l_txrad_fc00_zerohi t10$r_txrad_fc00.t10$l_txrad_fc00_zerohiD#define t10$r_txrads_fc00_bca t10$r_txrad_fc00.t10$r_txrads_fc00_bcaG#define t10$v_txrad_fc00_bca t10$r_txrads_fc00_bca.t10$v_txrad_fc00_bcaH#define t10$b_txrad_fc00_junque t10$r_txrad_fc00.t10$b_txrad_fc00_junque"#endif /* #if !defined(__VAXC) */ #define T10$K_STRM_PERFORM 0#define T10$K_STRM_UNUSABLE 1#define T10$K_STRM_DEFECT 2#define T10$K_STRM_WRITE 3#define T10$K_STRM_DBI 4#define T10$K_STRRM_DBI_CACHE 5 struct txcb6 {% unsigned char t10$b_txcb6_opcode;$ unsigned char t10$b_txcb6_fill1;$ unsigned char t10$b_txcb6_fill2;$ unsigned char t10$b_txcb6_fill3;$ unsigned char t10$b_txcb6_fill4;$ unsigned char t10$b_txcb6_fill5;$ unsigned char t10$b_txcb6_fill6;$ unsigned char t10$b_txcb6_fill7;# unsigned char t10$b_txcb6_type;* unsigned short int t10$w_txcb6_length;& unsigned char t10$b_txcb6_control; } ; struct txpb6 { __structR {$ unsigned t10$v_txpb6_ra : 1;' unsigned t10$v_txpb6_exact : 1;% unsigned t10$v_txpb6_rdd : 1;% unsigned t10$v_txpb6_wrc : 2;( unsigned t10$v_txpb6_rsvd05 : 3; } t10$r_txpb6_flags;$ unsigned char t10$b_txpb6_fill1;$ unsigned char t10$b_txpb6_fill2;$ unsigned char t10$b_txpb6_fill3;' unsigned int t10$l_txpb6_start_lba;% unsigned int t10$l_txpb6_end_lba;' unsigned int t10$l_txpb6_read_size;' unsigned int t10$l_txpb6_rRead_time;( unsigned int t10$l_txpb6_write_size;( unsigned int t10$l_txpb6_write_time; } ; #if !defined(__VAXC)7#define t10$v_txpb6_ra t10$r_txpb6_flags.t10$v_txpb6_ra=#define t10$v_txpb6_exact t10$r_txpb6_flags.t10$v_txpb6_exact9#define t10$v_txpb6_rdd t10$r_txpb6_flags.t10$v_txpb6_rdd9#define t10$v_txpb6_wrc t10$r_txpb6_flags.t10$v_txpb6_wrc"#endif /* #if !defined(__VAXC) */ #define T10$K_TXCBB_RC_CLV 0#define T10$K_TXCBB_RC_CAV 1 struct txcbb {% unsignedR char t10$b_txcbb_opcode; __struct {( unsigned t10$v_txcbb_rotcon : 2;' unsigned t10$v_txcbb_fill1 : 3;% unsigned t10$v_txcbb_lun : 3; } t10$r_txcbb_flags1;. unsigned short int t10$w_txcbb_read_speed;/ unsigned short int t10$w_txcbb_write_speed;% unsigned char t10$b_txcbb_rsvd06;% unsigned char t10$b_txcbb_rsvd07;% unsigned char t10$b_txcbb_rsvd08;% unsigned char t10$b_txcbb_rsvd09;% unsigned char t10$b_txcbb_rsvd10;& unRsigned char t10$b_txcbb_control; } ; #if !defined(__VAXC)@#define t10$v_txcbb_rotcon t10$r_txcbb_flags1.t10$v_txcbb_rotcon:#define t10$v_txcbb_lun t10$r_txcbb_flags1.t10$v_txcbb_lun"#endif /* #if !defined(__VAXC) */  struct dqiosb {) unsigned short int t13$w_dqio_status; __union { __struct {* unsigned int t13$l_dqio_bytes;. unsigned char t13$b_dqio_rsvd_xfr;. unsigned char t13$b_dqio_sensekey;" } t13$r_dqio_tRransfer; __struct {3 unsigned short int t13$w_dqio_rsvd_rst;+ unsigned int t13$l_dqio_resets; } t13$r_dqio_reset; } t13$r_dqio_overlay; } ; #if !defined(__VAXC)B#define t13$r_dqio_transfer t13$r_dqio_overlay.t13$r_dqio_transfer=#define t13$l_dqio_bytes t13$r_dqio_transfer.t13$l_dqio_bytesC#define t13$b_dqio_rsvd_xfr t13$r_dqio_transfer.t13$b_dqio_rsvd_xfrC#define t13$b_dqio_sensekey t13$r_dqio_transfer.t13$b_dqio_sensekey<R#define t13$r_dqio_reset t13$r_dqio_overlay.t13$r_dqio_reset@#define t13$w_dqio_rsvd_rst t13$r_dqio_reset.t13$w_dqio_rsvd_rst<#define t13$l_dqio_resets t13$r_dqio_reset.t13$l_dqio_resets"#endif /* #if !defined(__VAXC) */ #define T13$K_T13_NOP 0#define T13$K_T13_SOFT_RESET 8 #define T13$K_T13_RECALIBRATE 16#define T13$K_T13_READ_SECS 32%#define T13$K_T13_READ_SECS_WO_RET 33#define T13$K_T13_READ_LONG 34%#define T13$K_T13_READ_LONG_WO_RET 35#define T13$K_T13_WRITE_SECS 48&#definRe T13$K_T13_WRITE_SECS_WO_RET 49#define T13$K_T13_WRITE_LONG 50&#define T13$K_T13_WRITE_LONG_WO_RET 51#define T13$K_T13_WRITE_VFY 60"#define T13$K_T13_READ_VFY_SECS 64)#define T13$K_T13_READ_VFY_SECS_WO_RET 65!#define T13$K_T13_FORMAT_TRACK 80#define T13$K_T13_SEEK 112#define T13$K_T13_80 128$#define T13$K_T13_EXEC_DEV_DIAGS 144%#define T13$K_T13_INIT_DEV_PARAMS 145$#define T13$K_T13_DOWNLOAD_UCODE 146&#define T13$K_T13_STANDBY_IMMED_94 148##define T13$K_T13_IDLE_IMMED_95 149 #dRefine T13$K_T13_STANDBY_96 150#define T13$K_T13_IDLE_97 151%#define T13$K_T13_CHK_PWR_MODE_98 152#define T13$K_T13_SLEEP_99 153 #define T13$K_T13_PACKET_CMD 160%#define T13$K_T13_PACKET_IDENTIFY 161$#define T13$K_T13_SMART_DSBL_OPS 176%#define T13$K_T13_SMART_ATTR_AUTO 176%#define T13$K_T13_SMART_ENBL_OPER 176'#define T13$K_T13_SMART_ATTR_THRESH 176)#define T13$K_T13_SMART_RETURN_STATUS 176&#define T13$K_T13_SEC_SET_PSWD_OBS 186$#define T13$K_T13_SEC_UNLOCK_OBS 187(#define T13$K_RT13_SEC_ERASE_PREP_OBS 188(#define T13$K_T13_SEC_ERASE_UNIT_OBS 189)#define T13$K_T13_SEC_FREEZE_LOCK_OBS 190'#define T13$K_T13_SEC_DSBL_PSWD_OBS 191##define T13$K_T13_READ_MULTIPLE 196!#define T13$K_T13_WRITE_MULTI 197$#define T13$K_T13_SET_MULTI_MODE 198#define T13$K_T13_READ_DMA 200%#define T13$K_T13_READ_DMA_WO_RET 201#define T13$K_T13_WRITE_DMA 202&#define T13$K_T13_WRITE_DMA_WO_RET 203#define T13$K_T13_DOOR_LOCK 222!#define T13$K_T13_DOOR_UNLOCK 223&#define T13$K_T13_STANRDBY_IMMED_E0 224##define T13$K_T13_IDLE_IMMED_E1 225 #define T13$K_T13_STANDBY_E2 226#define T13$K_T13_IDLE_E3 227!#define T13$K_T13_READ_BUFFER 228%#define T13$K_T13_CHK_PWR_MODE_E5 229#define T13$K_T13_SLEEP_E6 230"#define T13$K_T13_WRITE_BUFFER 232"#define T13$K_T13_IDENTIFY_DEV 236!#define T13$K_T13_MEDIA_EJECT 237&#define T13$K_T13_IDENTIFY_DEV_DMA 238"#define T13$K_T13_SET_FEATURES 239$#define T13$K_T13_SECUR_SET_PSWD 241"#define T13$K_T13_SECUR_UNLOCK 242)#define T13$K_T13_RSECUR_ERASE_PREPARE 243&#define T13$K_T13_SECUR_ERASE_UNIT 244'#define T13$K_T13_SECUR_FREEZE_LOCK 245%#define T13$K_T13_SECUR_DSBL_PSWD 246 struct atacmd {% unsigned char t13$b_cmd_features;) unsigned char t13$b_cmd_sector_count;* unsigned char t13$b_cmd_sector_number;* unsigned short int t13$w_cmd_cylinder; __struct {$ unsigned t13$v_cmd_na03 : 4;# unsigned t13$v_cmd_dev : 1;$ unsigned t13$v_cmd_na57 : 3; } t13$r_cmd_device_head;R$ unsigned char t13$b_cmd_command; } ; #if !defined(__VAXC)9#define t13$v_cmd_dev t13$r_cmd_device_head.t13$v_cmd_dev"#endif /* #if !defined(__VAXC) */ #define T10$K_BLK_SIZE_512 512 #define T10$K_BLK_SIZE_2048 2048 #define T10$K_BLK_SIZE_2352 2352##define T10$K_T10_TEST_UNIT_READY 0!#define T10$K_T10_REQUEST_SENSE 3#define T10$K_T10_FORMAT_UNIT 4#define T10$K_T10_READ_6 8#define T10$K_T10_WRITE_6 10#define T10$K_T10_INQUIRY 18"#define T10$K_T10_MODE_SELECT_6 21R!#define T10$K_T10_MODE_SENSE_6 26$#define T10$K_T10_START_STOP_UNIT 27"#define T10$K_T10_PREVENT_ALLOW 30$#define T10$K_T10_READ_FORMAT_CAP 35"#define T10$K_T10_READ_CAPACITY 37#define T10$K_T10_READ_10 40#define T10$K_T10_WRITE_10 42#define T10$K_T10_SEEK 43$#define T10$K_T10_WRITE_VERIFY_10 46&#define T10$K_T10_SYNCHRONIZE_CACHE 53!#define T10$K_T10_WRITE_BUFFER 59$#define T10$K_T10_READ_SUBCHANNEL 66&#define T10$K_T10_READ_TOC_PMA_ATIP 67 #define T10$K_T10_READ_HEADER 68"#defRine T10$K_T10_PLAY_AUDIO_10 69#define T10$K_T10_GET_CONFIG 70##define T10$K_T10_PLAY_AUDIO_MSF 71%#define T10$K_T10_GET_EVENT_STATUS 74!#define T10$K_T10_PAUSE_RESUME 75##define T10$K_T10_STOP_PLAY_SCAN 78##define T10$K_T10_READ_DISK_INFO 81$#define T10$K_T10_READ_TRACK_INFO 82"#define T10$K_T10_RESERVE_TRACK 83"#define T10$K_T10_SEND_OPC_INFO 84##define T10$K_T10_MODE_SELECT_10 85!#define T10$K_T10_REPAIR_TRACK 88$#define T10$K_T10_READ_MASTER_CUE 89"#define T10$K_T10_MODE_SENSER_10 90 #define T10$K_T10_CLOSE_TRACK 91$#define T10$K_T10_READ_BUFFER_CAP 92##define T10$K_T10_SEND_CUE_SHEET 93#define T10$K_T10_60 96#define T10$K_T10_70 112#define T10$K_T10_80 128#define T10$K_T10_90 144#define T10$K_T10_BLANK 161#define T10$K_T10_SEND_KEY 163##define T10$K_T10_PLAY_AUDIO_12 165$#define T10$K_T10_LOAD_UNLOAD_CD 166#define T10$K_T10_READ_12 168#define T10$K_T10_WRITE_12 170%#define T10$K_T10_READ_DVD_STRUCT 173##define T10$K_T10_SET_STREAMING 182!#defRine T10$K_T10_READ_CD_MSF 185#define T10$K_T10_SCAN 186"#define T10$K_T10_SET_CD_SPEED 187#define T10$K_T10_PLAY_CD 188&#define T10$K_T10_MECHANISM_STATUS 189#define T10$K_T10_READ_CD 190%#define T10$K_T10_SEND_DVD_STRUCT 191#define T10$K_T10_C0 192#define T10$K_T10_D0 208#define T10$K_T10_E0 224#define T10$K_T10_F0 240 struct atapicmd {% unsigned char t10$b_sdl_pacifier; } ; struct atar {# unsigned char t13$b_atar_error;* unsigned char t13$b_atar_sRector_count;+ unsigned char t13$b_atar_sector_number;+ unsigned short int t13$w_atar_cylinder; __struct {% unsigned t13$v_atar_na03 : 4;$ unsigned t13$v_atar_dev : 1;% unsigned t13$v_atar_na57 : 3;! } t13$r_atar_device_head; __struct {$ unsigned t13$v_atar_err : 1;% unsigned t13$v_atar_na12 : 2;$ unsigned t13$v_atar_drq : 1;$ unsigned t13$v_atar_na4 : 1;# unsigned t13$v_atar_df : 1;% unsigned t R13$v_atar_drdy : 1;$ unsigned t13$v_atar_bsy : 1; } t13$r_atar_status; } ; #if !defined(__VAXC)<#define t13$v_atar_dev t13$r_atar_device_head.t13$v_atar_dev7#define t13$v_atar_err t13$r_atar_status.t13$v_atar_err7#define t13$v_atar_drq t13$r_atar_status.t13$v_atar_drq5#define t13$v_atar_df t13$r_atar_status.t13$v_atar_df9#define t13$v_atar_drdy t13$r_atar_status.t13$v_atar_drdy7#define t13$v_atar_bsy t13$r_atar_status.t13$v_atar_bsy"#endif /* #if !defined(__VARXC) */ #define T13$K_IPDPS_12BYTE 0#define T13$K_IPDPS_16BYTE 1#define T13$K_IPDPS_RSVD10 2#define T13$K_IPDPS_RSVD11 3#define T13$K_IPDDRQ_3MS 0#define T13$K_IPDDRQ_RSVD01 1#define T13$K_IPDDRQ_50US 2#define T13$K_IPDDRQ_RSVD11 3#define T13$K_IPDA_RSVD00 0#define T13$K_IPDA_RSVD01 1#define T13$K_IPDA_ATAPI 2#define T13$K_IPDA_RSVD11 3##define T13$K_SCFG_SETFSU_INC 14280##define T13$K_SCFG_SETFSU_CMP 14220##define T13$K_SCFG_AUTOSU_INC 35955##define T13$K_SCFG_ARUTOSU_CMP 51255#define T13$V_MAJV_ATA3 3#define T13$M_MAJV_ATA3 8#define T13$V_MAJV_ATAPI4 4#define T13$M_MAJV_ATAPI4 16#define T13$V_MAJV_ATAPI5 5#define T13$M_MAJV_ATAPI5 32#define T13$V_MAJV_ATAPI6 6#define T13$M_MAJV_ATAPI6 64#define T13$V_MAJV_ATAPI7 7#define T13$M_MAJV_ATAPI7 128#define T13$V_MAJV_ATAPI8 8#define T13$M_MAJV_ATAPI8 256#define T13$V_MAJV_ATAPI9 9#define T13$M_MAJV_ATAPI9 512#define T13$V_MAJV_ATAPI10 10#define T13$M_MAJV_ATAPI10 1024R#define T13$V_MAJV_ATAPI11 11#define T13$M_MAJV_ATAPI11 2048#define T13$V_MAJV_ATAPI12 12#define T13$M_MAJV_ATAPI12 4096#define T13$V_MAJV_ATAPI13 13#define T13$M_MAJV_ATAPI13 8192#define T13$V_MAJV_ATAPI14 14 #define T13$M_MAJV_ATAPI14 16384#define T13$K_HRR_UNIT_RSVD 0#define T13$K_HRR_UNIT_PLUG 1#define T13$K_HRR_UNIT_CSEL 2#define T13$K_HRR_UNIT_OTHR 3#define T13$K_SIGNATURE 165 struct atapira1 { __union { __struct {) unsigned t R13$v_id_rsvd00 : 1;, unsigned t13$v_id_retired01 : 1;- unsigned t13$v_id_incomplete : 1;. unsigned t13$v_id_retired0305 : 3;- unsigned t13$v_id_obsolete06 : 1;, unsigned t13$v_id_removable : 1;. unsigned t13$v_id_retired0814 : 7;& unsigned t13$v_id_ata : 1; } t13$r_id_general; __struct {/ unsigned t13$v_ipd_packet_size : 2;. unsigned t13$v_ipd_incomplete : 1;* R unsigned t13$v_ipd_rsvd34 : 2;' unsigned t13$v_ipd_drq : 2;- unsigned t13$v_ipd_removable : 1;- unsigned t13$v_ipd_cmdpktset : 5;* unsigned t13$v_ipd_rsvd13 : 1;) unsigned t13$v_ipd_atapi : 2; } t13$r_ipd_general; } t13$r_id_ipd_overlay;+ unsigned short int t13$w_chs_cylinders;- unsigned short int t13$w_specific_config;' unsigned short int t13$w_chs_heads;' unsigned short int t13$w_retired04R;' unsigned short int t13$w_retired05;3 unsigned short int t13$w_chs_sectors_per_track;' unsigned short int t13$w_retired07;' unsigned short int t13$w_retired08;' unsigned short int t13$w_retired09;" char t13$t_serial_number [20];' unsigned short int t13$w_retired20;' unsigned short int t13$w_retired21;( unsigned short int t13$w_obsolete22;& char t13$t_firmware_revision [20];! char t13$t_model_number [40]; __struct {+ unsigned t13$v_sRector_transfer : 8;! unsigned t13$v_hex80 : 8; } t13$r_multiple47;( unsigned short int t13$w_reserved48; __struct {' unsigned t13$v_retired0007 : 8;) unsigned t13$v_dma_supported : 1;) unsigned t13$v_lba_supported : 1;, unsigned t13$v_iordy_selectable : 1;+ unsigned t13$v_iordy_supported : 1;% unsigned t13$v_ata_reset : 1;+ unsigned t13$v_timer_compliant : 1;+ unsigned t13$v_command_queuing : 1;+ R unsigned t13$v_interleaved_dma : 1; } t13$r_capabilities49; __struct {' unsigned t13$v_local_timer : 1;) unsigned t13$v_reserved0113 : 13;# unsigned t13$v_c50_mb1 : 1;# unsigned t13$v_c50_mb0 : 1; } t13$r_capabilities50;' unsigned short int t13$w_retired51;' unsigned short int t13$w_retired52; __struct {% unsigned t13$v_valid5458 : 1;% unsigned t13$v_valid6470 : 1;# unsigned t13$v_valid88 : 1R;) unsigned t13$v_reserved0315 : 13; } t13$r_field_status53;' unsigned short int t13$w_retired54;' unsigned short int t13$w_retired55;' unsigned short int t13$w_retired56;' unsigned short int t13$w_retired57;' unsigned short int t13$w_retired58; __struct {1 unsigned t13$v_sectors_per_interrupt : 8;! unsigned t13$v_valid : 1;' unsigned t13$v_reserved915 : 7;$ } t13$r_interrupt_sectors59;$ unsigned int t13$l_user_Rsectors;( unsigned short int t13$w_obsolete62; __struct {, unsigned t13$v_mw_dma_mode_0_ok : 1;, unsigned t13$v_mw_dma_mode_1_ok : 1;, unsigned t13$v_mw_dma_mode_2_ok : 1;( unsigned t13$v_reserved0307 : 5;, unsigned t13$v_mw_dma_mode_0_on : 1;, unsigned t13$v_mw_dma_mode_1_on : 1;, unsigned t13$v_mw_dma_mode_2_on : 1;( unsigned t13$v_reserved1115 : 5; } t13$r_mw_dma_mode63; __struct {* unsigned t13$v_pio R_modes_supp : 8;( unsigned t13$v_reserved0815 : 8; } t13$r_adv_pio_mode64;. unsigned short int t13$w_min_mw_dma_cycle;. unsigned short int t13$w_rec_mw_dma_cycle;+ unsigned short int t13$w_min_pio_cycle;1 unsigned short int t13$w_min_pio_iordy_cycle;( unsigned short int t13$w_reserved69;( unsigned short int t13$w_reserved70;( unsigned short int t13$w_reserved71;( unsigned short int t13$w_reserved72;( unsigned short int t13$w_reserved73;( unsiRgned short int t13$w_reserved74; __struct {+ unsigned t13$v_max_queue_depth : 5;( unsigned t13$v_reserved615 : 11; } t13$r_queue_depth75;( unsigned short int t13$w_reserved76;( unsigned short int t13$w_reserved77;( unsigned short int t13$w_reserved78;( unsigned short int t13$w_reserved79;+ unsigned short int t13$w_major_version;+ unsigned short int t13$w_minor_version; __struct {! unsigned t13$v_smart : 1;$ unsigned t13R$v_security : 1;% unsigned t13$v_removable : 1;! unsigned t13$v_power : 1;" unsigned t13$v_packet : 1;' unsigned t13$v_write_cache : 1;% unsigned t13$v_lookahead : 1;' unsigned t13$v_release_int : 1;' unsigned t13$v_service_int : 1;( unsigned t13$v_device_reset : 1;* unsigned t13$v_host_protected : 1;& unsigned t13$v_obsolete11 : 1;( unsigned t13$v_write_buffer : 1;' unsigned t13$v_read_buffer : 1; R unsigned t13$v_nop : 1;& unsigned t13$v_obsolete15 : 1;% unsigned t13$v_microcode : 1;& unsigned t13$v_dma_queued : 1; unsigned t13$v_cfa : 1;% unsigned t13$v_adv_power : 1;( unsigned t13$v_media_status : 1;) unsigned t13$v_pwrup_standby : 1;' unsigned t13$v_host_spinup : 1;* unsigned t13$v_rsvd_area_boot : 1;, unsigned t13$v_set_max_security : 1;+ unsigned t13$v_auto_accoustics : 1;* unsignRed t13$v_48b_addressing : 1;* unsigned t13$v_config_overlay : 1;' unsigned t13$v_flush_cache : 1;+ unsigned t13$v_flush_cache_ext : 1;$ unsigned t13$v_fs82_mb1 : 1;$ unsigned t13$v_fs82_mb0 : 1; } t13$r_command_sets82; __struct {) unsigned t13$v_reserved0013 : 14;$ unsigned t13$v_fs84_mb1 : 1;$ unsigned t13$v_fs84_mb0 : 1; } t13$r_feature_sets84; __struct {$ unsigned t13$v_smart_on : 1;' R unsigned t13$v_security_on : 1;( unsigned t13$v_removable_on : 1;$ unsigned t13$v_power_on : 1;% unsigned t13$v_packet_on : 1;* unsigned t13$v_write_cache_on : 1;( unsigned t13$v_lookahead_on : 1;* unsigned t13$v_release_int_on : 1;* unsigned t13$v_service_int_on : 1;+ unsigned t13$v_device_reset_on : 1;- unsigned t13$v_host_protected_on : 1;) unsigned t13$v_obsolete11_on : 1;+ unsigned t13$v_write_buffer_on R : 1;* unsigned t13$v_read_buffer_on : 1;" unsigned t13$v_nop_on : 1;) unsigned t13$v_obsolete15_on : 1;( unsigned t13$v_microcode_on : 1;) unsigned t13$v_dma_queued_on : 1;" unsigned t13$v_cfa_on : 1;( unsigned t13$v_adv_power_on : 1;+ unsigned t13$v_media_status_on : 1;, unsigned t13$v_pwrup_standby_on : 1;* unsigned t13$v_host_spinup_on : 1;- unsigned t13$v_rsvd_area_boot_on : 1;/ unsigned t13$v_set R_max_security_on : 1;. unsigned t13$v_auto_accoustics_on : 1;- unsigned t13$v_48b_addressing_on : 1;- unsigned t13$v_config_overlay_on : 1;* unsigned t13$v_flush_cache_on : 1;. unsigned t13$v_flush_cache_ext_on : 1;' unsigned t13$v_cs85_mb1_on : 1;' unsigned t13$v_cs85_mb0_on : 1;" } t13$r_command_sets_on85; __struct {) unsigned t13$v_reserved0013 : 14;$ unsigned t13$v_fs87_mb1 : 1;$ unsigned t13$v_fs8 R7_mb0 : 1;" } t13$r_feature_sets_on87; __struct {, unsigned t13$v_ul_dma_mode_0_ok : 1;, unsigned t13$v_ul_dma_mode_1_ok : 1;, unsigned t13$v_ul_dma_mode_2_ok : 1;+ unsigned t13$v_ul_reserved0307 : 5;, unsigned t13$v_ul_dma_mode_0_on : 1;, unsigned t13$v_ul_dma_mode_1_on : 1;, unsigned t13$v_ul_dma_mode_2_on : 1;+ unsigned t13$v_ul_reserved1115 : 5; } t13$r_ul_dma_mode88;( unsigned short int t13$w_erase_time; R, unsigned short int t13$w_adv_erase_time;' unsigned short int t13$w_adv_power;* unsigned short int t13$w_pwd_revision; __struct {& unsigned t13$v_hrr_d0_mb1 : 1;' unsigned t13$v_hrr_d0_unit : 2;* unsigned t13$v_hrr_d0_diag_ok : 1;+ unsigned t13$v_hrr_d0_pdiag_ok : 1;* unsigned t13$v_hrr_d0_dasp_ok : 1;+ unsigned t13$v_hrr_d0_confused : 1;& unsigned t13$v_hrr_d1_mb1 : 1;' unsigned t13$v_hrr_d1_unit : 2;+ unRsigned t13$v_hrr_d1_pdiag_ok : 1;' unsigned t13$v_hrr_d1_rsvd : 1;( unsigned t13$v_hrr_cblid_hi : 1;# unsigned t13$v_hrr_mb1 : 1;# unsigned t13$v_hrr_mb0 : 1;# unsigned t13$v_fill_4_ : 1;! } t13$r_hw_reset_results; __struct {& unsigned t13$v_al_current : 8;* unsigned t13$v_al_recommended : 8; } t13$r_accoustic_level;( unsigned short int t13$w_reserved95;( unsigned short int t13$w_reserved96;( unsigned shoRrt int t13$w_reserved97;( unsigned short int t13$w_reserved98;( unsigned short int t13$w_reserved99;* unsigned __int64 t13$q_48b_addr_limit;1 unsigned short int t13$w_reserved104126 [23]; __struct {) unsigned t13$v_rms_supported : 2;, unsigned t13$v_ul_reserved0315 : 14; } t13$r_rms_features127; __struct {, unsigned t13$v_security_support : 1;, unsigned t13$v_security_enabled : 1;+ unsigned t13$v_security_locked : 1;+ R unsigned t13$v_security_frozen : 1;, unsigned t13$v_security_expired : 1;. unsigned t13$v_security_adv_erase : 1;1 unsigned t13$v_security_reserved0607 : 2;, unsigned t13$v_security_maximum : 1;1 unsigned t13$v_security_reserved0915 : 7;# } t13$r_security_status128;. unsigned short int t13$x_vendor_data [31];1 unsigned short int t13$w_reserved160254 [95]; __struct {% unsigned t13$v_signature : 8;$ unsigned t13$v R_checksum : 8;" } t13$r_integrity_word255; } ; #if !defined(__VAXC)>#define t13$r_id_general t13$r_id_ipd_overlay.t13$r_id_general@#define t13$v_id_incomplete t13$r_id_general.t13$v_id_incomplete>#define t13$v_id_removable t13$r_id_general.t13$v_id_removable2#define t13$v_id_ata t13$r_id_general.t13$v_id_ata@#define t13$r_ipd_general t13$r_id_ipd_overlay.t13$r_ipd_generalE#define t13$v_ipd_packet_size t13$r_ipd_general.t13$v_ipd_packet_sizeC#define t13$v_ipd_incomplete t13$r R_ipd_general.t13$v_ipd_incomplete;#define t13$v_ipd_rsvd34 t13$r_ipd_general.t13$v_ipd_rsvd345#define t13$v_ipd_drq t13$r_ipd_general.t13$v_ipd_drqA#define t13$v_ipd_removable t13$r_ipd_general.t13$v_ipd_removableA#define t13$v_ipd_cmdpktset t13$r_ipd_general.t13$v_ipd_cmdpktset9#define t13$v_ipd_atapi t13$r_ipd_general.t13$v_ipd_atapiD#define t13$v_sector_transfer t13$r_multiple47.t13$v_sector_transfer0#define t13$v_hex80 t13$r_multiple47.t13$v_hex80D#define t13$v_dma_supported t13$r_caRpabilities49.t13$v_dma_supportedD#define t13$v_lba_supported t13$r_capabilities49.t13$v_lba_supportedJ#define t13$v_iordy_selectable t13$r_capabilities49.t13$v_iordy_selectableH#define t13$v_iordy_supported t13$r_capabilities49.t13$v_iordy_supported<#define t13$v_ata_reset t13$r_capabilities49.t13$v_ata_resetH#define t13$v_timer_compliant t13$r_capabilities49.t13$v_timer_compliantH#define t13$v_command_queuing t13$r_capabilities49.t13$v_command_queuingH#define t13$v_interleaved_dma t13$r_capabi Rlities49.t13$v_interleaved_dma@#define t13$v_local_timer t13$r_capabilities50.t13$v_local_timer8#define t13$v_c50_mb1 t13$r_capabilities50.t13$v_c50_mb18#define t13$v_c50_mb0 t13$r_capabilities50.t13$v_c50_mb0<#define t13$v_valid5458 t13$r_field_status53.t13$v_valid5458<#define t13$v_valid6470 t13$r_field_status53.t13$v_valid64708#define t13$v_valid88 t13$r_field_status53.t13$v_valid88Y#define t13$v_sectors_per_interrupt t13$r_interrupt_sectors59.t13$v_sectors_per_interrupt9#define t13$v_valiRd t13$r_interrupt_sectors59.t13$v_validI#define t13$v_mw_dma_mode_0_ok t13$r_mw_dma_mode63.t13$v_mw_dma_mode_0_okI#define t13$v_mw_dma_mode_1_ok t13$r_mw_dma_mode63.t13$v_mw_dma_mode_1_okI#define t13$v_mw_dma_mode_2_ok t13$r_mw_dma_mode63.t13$v_mw_dma_mode_2_okI#define t13$v_mw_dma_mode_0_on t13$r_mw_dma_mode63.t13$v_mw_dma_mode_0_onI#define t13$v_mw_dma_mode_1_on t13$r_mw_dma_mode63.t13$v_mw_dma_mode_1_onI#define t13$v_mw_dma_mode_2_on t13$r_mw_dma_mode63.t13$v_mw_dma_mode_2_onF#define Rt13$v_pio_modes_supp t13$r_adv_pio_mode64.t13$v_pio_modes_suppG#define t13$v_max_queue_depth t13$r_queue_depth75.t13$v_max_queue_depth4#define t13$v_smart t13$r_command_sets82.t13$v_smart:#define t13$v_security t13$r_command_sets82.t13$v_security<#define t13$v_removable t13$r_command_sets82.t13$v_removable4#define t13$v_power t13$r_command_sets82.t13$v_power6#define t13$v_packet t13$r_command_sets82.t13$v_packet@#define t13$v_write_cache t13$r_command_sets82.t13$v_write_cache<#define t13$v_lo Rokahead t13$r_command_sets82.t13$v_lookahead@#define t13$v_release_int t13$r_command_sets82.t13$v_release_int@#define t13$v_service_int t13$r_command_sets82.t13$v_service_intB#define t13$v_device_reset t13$r_command_sets82.t13$v_device_resetF#define t13$v_host_protected t13$r_command_sets82.t13$v_host_protectedB#define t13$v_write_buffer t13$r_command_sets82.t13$v_write_buffer@#define t13$v_read_buffer t13$r_command_sets82.t13$v_read_buffer0#define t13$v_nop t13$r_command_sets82.t13$v_nop<#defRine t13$v_microcode t13$r_command_sets82.t13$v_microcode>#define t13$v_dma_queued t13$r_command_sets82.t13$v_dma_queued0#define t13$v_cfa t13$r_command_sets82.t13$v_cfa<#define t13$v_adv_power t13$r_command_sets82.t13$v_adv_powerB#define t13$v_media_status t13$r_command_sets82.t13$v_media_statusD#define t13$v_pwrup_standby t13$r_command_sets82.t13$v_pwrup_standby@#define t13$v_host_spinup t13$r_command_sets82.t13$v_host_spinupF#define t13$v_rsvd_area_boot t13$r_command_sets82.t13$v_rsvd_area_bo RotJ#define t13$v_set_max_security t13$r_command_sets82.t13$v_set_max_securityH#define t13$v_auto_accoustics t13$r_command_sets82.t13$v_auto_accousticsF#define t13$v_48b_addressing t13$r_command_sets82.t13$v_48b_addressingF#define t13$v_config_overlay t13$r_command_sets82.t13$v_config_overlay@#define t13$v_flush_cache t13$r_command_sets82.t13$v_flush_cacheH#define t13$v_flush_cache_ext t13$r_command_sets82.t13$v_flush_cache_ext:#define t13$v_fs82_mb1 t13$r_command_sets82.t13$v_fs82_mb1:#define Rt13$v_fs82_mb0 t13$r_command_sets82.t13$v_fs82_mb0:#define t13$v_fs84_mb1 t13$r_feature_sets84.t13$v_fs84_mb1:#define t13$v_fs84_mb0 t13$r_feature_sets84.t13$v_fs84_mb0=#define t13$v_smart_on t13$r_command_sets_on85.t13$v_smart_onC#define t13$v_security_on t13$r_command_sets_on85.t13$v_security_onE#define t13$v_removable_on t13$r_command_sets_on85.t13$v_removable_on=#define t13$v_power_on t13$r_command_sets_on85.t13$v_power_on?#define t13$v_packet_on t13$r_command_sets_on85.t13$v_packet_onRI#define t13$v_write_cache_on t13$r_command_sets_on85.t13$v_write_cache_onE#define t13$v_lookahead_on t13$r_command_sets_on85.t13$v_lookahead_onI#define t13$v_release_int_on t13$r_command_sets_on85.t13$v_release_int_onI#define t13$v_service_int_on t13$r_command_sets_on85.t13$v_service_int_onK#define t13$v_device_reset_on t13$r_command_sets_on85.t13$v_device_reset_onO#define t13$v_host_protected_on t13$r_command_sets_on85.t13$v_host_protected_onK#define t13$v_write_buffer_on t13$r_command_Rsets_on85.t13$v_write_buffer_onI#define t13$v_read_buffer_on t13$r_command_sets_on85.t13$v_read_buffer_on9#define t13$v_nop_on t13$r_command_sets_on85.t13$v_nop_onE#define t13$v_microcode_on t13$r_command_sets_on85.t13$v_microcode_onG#define t13$v_dma_queued_on t13$r_command_sets_on85.t13$v_dma_queued_on9#define t13$v_cfa_on t13$r_command_sets_on85.t13$v_cfa_onE#define t13$v_adv_power_on t13$r_command_sets_on85.t13$v_adv_power_onK#define t13$v_media_status_on t13$r_command_sets_on85.t13$Rv_media_status_onM#define t13$v_pwrup_standby_on t13$r_command_sets_on85.t13$v_pwrup_standby_onI#define t13$v_host_spinup_on t13$r_command_sets_on85.t13$v_host_spinup_onO#define t13$v_rsvd_area_boot_on t13$r_command_sets_on85.t13$v_rsvd_area_boot_onS#define t13$v_set_max_security_on t13$r_command_sets_on85.t13$v_set_max_security_onQ#define t13$v_auto_accoustics_on t13$r_command_sets_on85.t13$v_auto_accoustics_onO#define t13$v_48b_addressing_on t13$r_command_sets_on85.t13$v_48b_addressing_oRnO#define t13$v_config_overlay_on t13$r_command_sets_on85.t13$v_config_overlay_onI#define t13$v_flush_cache_on t13$r_command_sets_on85.t13$v_flush_cache_onQ#define t13$v_flush_cache_ext_on t13$r_command_sets_on85.t13$v_flush_cache_ext_onC#define t13$v_cs85_mb1_on t13$r_command_sets_on85.t13$v_cs85_mb1_onC#define t13$v_cs85_mb0_on t13$r_command_sets_on85.t13$v_cs85_mb0_on=#define t13$v_fs87_mb1 t13$r_feature_sets_on87.t13$v_fs87_mb1=#define t13$v_fs87_mb0 t13$r_feature_sets_on87.t13$v_fs8R7_mb0I#define t13$v_ul_dma_mode_0_ok t13$r_ul_dma_mode88.t13$v_ul_dma_mode_0_okI#define t13$v_ul_dma_mode_1_ok t13$r_ul_dma_mode88.t13$v_ul_dma_mode_1_okI#define t13$v_ul_dma_mode_2_ok t13$r_ul_dma_mode88.t13$v_ul_dma_mode_2_okI#define t13$v_ul_dma_mode_0_on t13$r_ul_dma_mode88.t13$v_ul_dma_mode_0_onI#define t13$v_ul_dma_mode_1_on t13$r_ul_dma_mode88.t13$v_ul_dma_mode_1_onI#define t13$v_ul_dma_mode_2_on t13$r_ul_dma_mode88.t13$v_ul_dma_mode_2_on@#define t13$v_hrr_d0_mb1 t13$r_hw_reset_reRsults.t13$v_hrr_d0_mb1B#define t13$v_hrr_d0_unit t13$r_hw_reset_results.t13$v_hrr_d0_unitH#define t13$v_hrr_d0_diag_ok t13$r_hw_reset_results.t13$v_hrr_d0_diag_okJ#define t13$v_hrr_d0_pdiag_ok t13$r_hw_reset_results.t13$v_hrr_d0_pdiag_okH#define t13$v_hrr_d0_dasp_ok t13$r_hw_reset_results.t13$v_hrr_d0_dasp_okJ#define t13$v_hrr_d0_confused t13$r_hw_reset_results.t13$v_hrr_d0_confused@#define t13$v_hrr_d1_mb1 t13$r_hw_reset_results.t13$v_hrr_d1_mb1B#define t13$v_hrr_d1_unit t13$r_hw_reset_results R.t13$v_hrr_d1_unitJ#define t13$v_hrr_d1_pdiag_ok t13$r_hw_reset_results.t13$v_hrr_d1_pdiag_okB#define t13$v_hrr_d1_rsvd t13$r_hw_reset_results.t13$v_hrr_d1_rsvdD#define t13$v_hrr_cblid_hi t13$r_hw_reset_results.t13$v_hrr_cblid_hi:#define t13$v_hrr_mb1 t13$r_hw_reset_results.t13$v_hrr_mb1:#define t13$v_hrr_mb0 t13$r_hw_reset_results.t13$v_hrr_mb0?#define t13$v_al_current t13$r_accoustic_level.t13$v_al_currentG#define t13$v_al_recommended t13$r_accoustic_level.t13$v_al_recommendedE#define t13$Sv_rms_supported t13$r_rms_features127.t13$v_rms_supportedN#define t13$v_security_support t13$r_security_status128.t13$v_security_supportN#define t13$v_security_enabled t13$r_security_status128.t13$v_security_enabledL#define t13$v_security_locked t13$r_security_status128.t13$v_security_lockedL#define t13$v_security_frozen t13$r_security_status128.t13$v_security_frozenN#define t13$v_security_expired t13$r_security_status128.t13$v_security_expiredR#define t13$v_security_adv_erase t13$r_security_stSatus128.t13$v_security_adv_eraseN#define t13$v_security_maximum t13$r_security_status128.t13$v_security_maximum?#define t13$v_signature t13$r_integrity_word255.t13$v_signature=#define t13$v_checksum t13$r_integrity_word255.t13$v_checksum"#endif /* #if !defined(__VAXC) */  #define T13$S_SERIAL_NUMBER 20"#define T13$S_FIRMWARE_REVISION 20#define T13$S_MODEL_NUMBER 40 struct atapira1a {+ short int t13$w_atapira1a_sdl_pacifier; } ; struct mphdr10 {1 unsigned shoSrt int t10$w_mphdr10_data_length;, unsigned char t10$b_mphdr10_medium_type;& unsigned char t10$b_mphdr10_fill3;& unsigned char t10$b_mphdr10_fill4;& unsigned char t10$b_mphdr10_fill5;2 unsigned short int t10$w_mphdr10_block_length; } ; struct mphdr6 {+ unsigned char t10$b_mphdr6_data_length;+ unsigned char t10$b_mphdr6_medium_type;& unsigned char t10$b_mphdr6_device;, unsigned char t10$b_mphdr6_block_length; } ; struct mpbdg {& unsignedS char t10$b_mpbdg_density;) unsigned char t10$x_mpbdg_blocks [3];# unsigned char t10$b_mpbdg_rsvd;- unsigned char t10$x_mpbdg_block_size [3]; } ; struct mpbdda {% unsigned int t10$l_mpbdda_blocks;' unsigned char t10$b_mpbdda_density;. unsigned char t10$x_mpbdda_block_size [3]; } ;#define T10$K_WRT_PACKET 0#define T10$K_WRT_TAO 1#define T10$K_WRT_SAO 2#define T10$K_WRT_DAO 2#define T10$K_WRT_RAW 3#define T10$K_QTM_2AUD_PE0 2##define T10$K_SQTM_2AUD_PE0_NOCOPY 0#define T10$K_QTM_2AUD_PE5015 3&#define T10$K_QTM_2AUD_PE5015_NOCOPY 1#define T10$K_QTM_4AUD_PE0 10##define T10$K_QTM_4AUD_PE0_NOCOPY 8 #define T10$K_QTM_4AUD_PE5015 11&#define T10$K_QTM_4AUD_PE5015_NOCOPY 9#define T10$K_QTM_DATA_UNINT 6%#define T10$K_QTM_DATA_UNINT_NOCOPY 4#define T10$K_QTM_DATA_INCRE 7%#define T10$K_QTM_DATA_INCRE_NOCOPY 5#define T10$M_QTM_COPYALLOWED 2#define T10$K_MSC_NO_B0 0#define T10$K_MSC_MAX_B0 1#define T10$K_MSC_RSVD 16#dSefine T10$K_MSC_OK 17#define T10$K_BT_RAW_2352 0#define T10$K_BT_RAW_2368 1#define T10$K_BT_RAW_2448 2#define T10$K_BT_RAW_2448_RAW 3#define T10$K_BT_MODE_1 8#define T10$K_BT_MODE_2_2336 9#define T10$K_BT_MODE_2_2048 10#define T10$K_BT_MODE_2_2056 11#define T10$K_BT_MODE_2_2324 12#define T10$K_BT_MODE_2_2332 13#define T10$K_SF_CDDA_CDROM 0#define T10$K_SF_CDI 16 #define T10$K_SF_CDROMXA_DDCD 32!#define T10$K_MP05_BASE_LENGTH 50 #define T10$K_MP05_MAX_LENGTH 54S struct mp05 { __struct {+ unsigned t10$v_mp05_hdr_mpcode : 6;* unsigned t10$v_mp05_hdr_fill1 : 1;' unsigned t10$v_mp05_hdr_ps : 1; } t10$r_mp05_hdr_flags;$ unsigned char t10$b_mp05_length; __struct {+ unsigned t10$v_mp05_2_wrt_type : 4;* unsigned t10$v_mp05_2_test_wr : 1;' unsigned t10$v_mp05_2_ls_v : 1;' unsigned t10$v_mp05_2_bufe : 1;( unsigned t10$v_mp05_2_fill1 : 1; } t10$r_mp05_2_flags;S __struct {+ unsigned t10$v_mp05_3_trk_mode : 4;+ unsigned t10$v_mp05_3_copyprot : 1;+ unsigned t10$v_mp05_3_fixedpkt : 1;, unsigned t10$v_mp05_3_multisess : 2; } t10$r_mp05_3_flags; __struct {* unsigned t10$v_mp05_4_bt_type : 4;' unsigned t10$v_mp05_4_fill : 4; } t10$r_mp05_4_flags;' unsigned char t10$b_mp05_link_size;# unsigned char t10$b_mp05_fill6; __struct {' unsigned t10$v_mp05_7_code :S 6;' unsigned t10$v_mp05_7_fill : 2; } t10$r_mp05_7_flags;) unsigned char t10$b_mp05_sess_format;# unsigned char t10$b_mp05_fill9;% unsigned int t10$l_mp05_pkt_size;. unsigned short int t10$w_mp05_audio_pause;0 unsigned char t10$x_mp05_media_cat_num [16];' unsigned char t10$x_mp05_isrc [14];+ unsigned char t10$x_mp05_subheader [4];- unsigned char t10$x_mp05_vendor_data [4]; } ; #if !defined(__VAXC)H#define t10$v_mp05_hdr_mpcode t10$ Sr_mp05_hdr_flags.t10$v_mp05_hdr_mpcode@#define t10$v_mp05_hdr_ps t10$r_mp05_hdr_flags.t10$v_mp05_hdr_psF#define t10$v_mp05_2_wrt_type t10$r_mp05_2_flags.t10$v_mp05_2_wrt_typeD#define t10$v_mp05_2_test_wr t10$r_mp05_2_flags.t10$v_mp05_2_test_wr>#define t10$v_mp05_2_ls_v t10$r_mp05_2_flags.t10$v_mp05_2_ls_v>#define t10$v_mp05_2_bufe t10$r_mp05_2_flags.t10$v_mp05_2_bufeF#define t10$v_mp05_3_trk_mode t10$r_mp05_3_flags.t10$v_mp05_3_trk_modeF#define t10$v_mp05_3_copyprot t10$r_mp05_3_flags.t10$v_mp0 S5_3_copyprotF#define t10$v_mp05_3_fixedpkt t10$r_mp05_3_flags.t10$v_mp05_3_fixedpktH#define t10$v_mp05_3_multisess t10$r_mp05_3_flags.t10$v_mp05_3_multisessD#define t10$v_mp05_4_bt_type t10$r_mp05_4_flags.t10$v_mp05_4_bt_type>#define t10$v_mp05_7_code t10$r_mp05_7_flags.t10$v_mp05_7_code"#endif /* #if !defined(__VAXC) */  struct mp1d { __struct {+ unsigned t10$v_mp1d_hdr_mpcode : 6;* unsigned t10$v_mp1d_hdr_fill1 : 1;' unsigned t10$v_mp1d_hdr_ps : 1;  S } t10$r_mp1d_hdr_flags;$ unsigned char t10$b_mp1d_length;# unsigned char t10$b_mp1d_fill2;# unsigned char t10$b_mp1d_fill3; __struct {' unsigned t10$v_mp1d_4_swpp : 1;' unsigned t10$v_mp1d_4_disp : 1;' unsigned t10$v_mp1d_4_tmoe : 1;+ unsigned t10$v_mp1d_4_g3enable : 1;) unsigned t10$v_mp1d_4_fill47 : 4; } t10$r_mp1d_4_flags;# unsigned char t10$b_mp1d_fill5;, unsigned short int t10$w_mp1d_g1timeout;, unsign Sed short int t10$w_mp1d_g2timeout; } ; #if !defined(__VAXC)H#define t10$v_mp1d_hdr_mpcode t10$r_mp1d_hdr_flags.t10$v_mp1d_hdr_mpcode@#define t10$v_mp1d_hdr_ps t10$r_mp1d_hdr_flags.t10$v_mp1d_hdr_ps>#define t10$v_mp1d_4_swpp t10$r_mp1d_4_flags.t10$v_mp1d_4_swpp>#define t10$v_mp1d_4_disp t10$r_mp1d_4_flags.t10$v_mp1d_4_disp>#define t10$v_mp1d_4_tmoe t10$r_mp1d_4_flags.t10$v_mp1d_4_tmoeF#define t10$v_mp1d_4_g3enable t10$r_mp1d_4_flags.t10$v_mp1d_4_g3enable"#endif /* #if !defined(__VAXC S) */ #define T10$K_LMT_CADDY 0#define T10$K_LMT_TRAY 1#define T10$K_LMT_POPUP 2#define T10$K_LMT_RSVD011 3#define T10$K_LMT_CHANGER 4#define T10$K_LMT_MAGAZINE 5#define T10$K_LMT_RSVD110 6#define T10$K_LMT_RSVD111 7#define T10$K_SPEED_X1 1723#define T10$K_SPEED_XMAX 65535#define T10$K_MP2A_X0001 1722#define T10$K_MP2A_X0002 3445#define T10$K_MP2A_X0004 6890#define T10$K_MP2A_X0008 13781#define T10$K_MP2A_X0010 17226#define T10$K_MP2A_X0012 20671#define T1S0$K_MP2A_X0016 27562#define T10$K_MP2A_X0020 34453#define T10$K_MP2A_X0024 41343#define T10$K_MP2A_X0032 55125#define T10$K_MP2A_X0040 68906#define T10$K_MP2A_X0048 82687#define T10$K_MP2A_X0052 89578#define T10$K_MP2A_X0056 96468#define T10$K_MP2A_X0064 110250#define T10$K_MP2A_RC_CLV 0#define T10$K_MP2A_RC_CAV 1 struct mp2a { __struct {+ unsigned t10$v_mp2a_hdr_mpcode : 6;* unsigned t10$v_mp2a_hdr_fill1 : 1;' unsigned t10$v_mp2a_hdr_ps : 1S; } t10$r_mp2a_hdr_flags;$ unsigned char t10$b_mp2a_length; __struct {) unsigned t10$v_mp2a_2_cdr_rd : 1;* unsigned t10$v_mp2a_2_cdrw_rd : 1;+ unsigned t10$v_mp2a_2_method_2 : 1;, unsigned t10$v_mp2a_2_dvdrom_rd : 1;* unsigned t10$v_mp2a_2_dvdr_rd : 1;, unsigned t10$v_mp2a_2_dvdram_rd : 1;( unsigned t10$v_mp2a_2_rsvd6 : 2; } t10$r_mp2a_2_flags; __struct {) unsigned t10$v_mp2a_3_cdr_wr : 1;* S unsigned t10$v_mp2a_3_cdrw_wr : 1;* unsigned t10$v_mp2a_3_test_wr : 1;( unsigned t10$v_mp2a_3_rsvd3 : 1;* unsigned t10$v_mp2a_3_dvdr_wr : 1;, unsigned t10$v_mp2a_3_dvdram_wr : 1;( unsigned t10$v_mp2a_3_rsvd6 : 2; } t10$r_mp2a_3_flags; __struct {' unsigned t10$v_mp2a_4_play : 1;, unsigned t10$v_mp2a_4_composite : 1;, unsigned t10$v_mp2a_4_digital_1 : 1;, unsigned t10$v_mp2a_4_digital_2 : 1;. unsigned t10 S$v_mp2a_4_mode2_form1 : 1;. unsigned t10$v_mp2a_4_mode2_form2 : 1;/ unsigned t10$v_mp2a_4_multisession : 1;& unsigned t10$v_mp2a_4_buf : 1; } t10$r_mp2a_4_flags; __struct {, unsigned t10$v_mp2a_5_supported : 1;+ unsigned t10$v_mp2a_5_accurate : 1;% unsigned t10$v_mp2a_5_rw : 1;, unsigned t10$v_mp2a_5_corrected : 1;- unsigned t10$v_mp2a_5_c2pointers : 1;' unsigned t10$v_mp2a_5_isrc : 1;& unsigned t10$vS_mp2a_5_upc : 1;* unsigned t10$v_mp2a_5_barcode : 1; } t10$r_mp2a_5_flags; __struct {' unsigned t10$v_mp2a_6_lock : 1;( unsigned t10$v_mp2a_6_state : 1;* unsigned t10$v_mp2a_6_prevent : 1;( unsigned t10$v_mp2a_6_eject : 1;( unsigned t10$v_mp2a_6_rsvd4 : 1;/ unsigned t10$v_mp2a_6_loadmechtype : 3; } t10$r_mp2a_6_flags; __struct {) unsigned t10$v_mp2a_7_sepvol : 1;* unsigned t10$v_mp2a_7_sepmute S: 1;* unsigned t10$v_mp2a_7_present : 1;& unsigned t10$v_mp2a_7_sss : 1;- unsigned t10$v_mp2a_7_sidechange : 1;, unsigned t10$v_mp2a_7_rw_leadin : 1;( unsigned t10$v_mp2a_7_rsvd6 : 2; } t10$r_mp2a_7_flags;+ unsigned short int t10$w_mp2a_max_read;, unsigned short int t10$w_mp2a_vollevels;* unsigned short int t10$w_mp2a_bufsize;, unsigned short int t10$w_mp2a_curr_read;$ unsigned char t10$b_mp2a_rsvd16; __struct {) un Ssigned t10$v_mp2a_17_rsvd1 : 1;( unsigned t10$v_mp2a_17_bckf : 1;' unsigned t10$v_mp2a_17_rck : 1;( unsigned t10$v_mp2a_17_lsbf : 1;* unsigned t10$v_mp2a_17_length : 2;) unsigned t10$v_mp2a_17_rsvd6 : 2; } t10$r_mp2a_17_flags;, unsigned short int t10$w_mp2a_max_write;- unsigned short int t10$w_mp2a_curr_write;+ unsigned short int t10$w_mp2a_copymgmt;% unsigned char t10$b_mp2a_rsvd240;% unsigned char t10$b_mp2a_rsvd250;% unSsigned char t10$b_mp2a_rsvd260; __struct {* unsigned t10$v_mp2a_27_rotcon : 2;) unsigned t10$v_mp2a_27_rsvd3 : 6; } t10$r_mp2a_27_flags;2 unsigned short int t10$w_mp2a_curr_write_unit;. unsigned short int t10$w_mp2a_wrtspd_size; __struct {* unsigned char t10$b_mp2a_ws_rsvd0; __struct {. unsigned t10$v_mp2a_ws_rotcon : 3;- unsigned t10$v_mp2a_ws_rsvd3 : 5;$ } t10$r_mp2a_ws_rotctrl;2 unsigned S short int t10$w_mp2a_write_speed;" } t10$r_mp2a_wrtspd [256]; } ; #if !defined(__VAXC)H#define t10$v_mp2a_hdr_mpcode t10$r_mp2a_hdr_flags.t10$v_mp2a_hdr_mpcode@#define t10$v_mp2a_hdr_ps t10$r_mp2a_hdr_flags.t10$v_mp2a_hdr_psB#define t10$v_mp2a_2_cdr_rd t10$r_mp2a_2_flags.t10$v_mp2a_2_cdr_rdD#define t10$v_mp2a_2_cdrw_rd t10$r_mp2a_2_flags.t10$v_mp2a_2_cdrw_rdF#define t10$v_mp2a_2_method_2 t10$r_mp2a_2_flags.t10$v_mp2a_2_method_2H#define t10$v_mp2a_2_dvdrom_rd t10$r_mp2a_2_flagSs.t10$v_mp2a_2_dvdrom_rdD#define t10$v_mp2a_2_dvdr_rd t10$r_mp2a_2_flags.t10$v_mp2a_2_dvdr_rdH#define t10$v_mp2a_2_dvdram_rd t10$r_mp2a_2_flags.t10$v_mp2a_2_dvdram_rdB#define t10$v_mp2a_3_cdr_wr t10$r_mp2a_3_flags.t10$v_mp2a_3_cdr_wrD#define t10$v_mp2a_3_cdrw_wr t10$r_mp2a_3_flags.t10$v_mp2a_3_cdrw_wrD#define t10$v_mp2a_3_test_wr t10$r_mp2a_3_flags.t10$v_mp2a_3_test_wrD#define t10$v_mp2a_3_dvdr_wr t10$r_mp2a_3_flags.t10$v_mp2a_3_dvdr_wrH#define t10$v_mp2a_3_dvdram_wr t10$r_mp2a_3_flags.t10$v_mpS2a_3_dvdram_wr>#define t10$v_mp2a_4_play t10$r_mp2a_4_flags.t10$v_mp2a_4_playH#define t10$v_mp2a_4_composite t10$r_mp2a_4_flags.t10$v_mp2a_4_compositeH#define t10$v_mp2a_4_digital_1 t10$r_mp2a_4_flags.t10$v_mp2a_4_digital_1H#define t10$v_mp2a_4_digital_2 t10$r_mp2a_4_flags.t10$v_mp2a_4_digital_2L#define t10$v_mp2a_4_mode2_form1 t10$r_mp2a_4_flags.t10$v_mp2a_4_mode2_form1L#define t10$v_mp2a_4_mode2_form2 t10$r_mp2a_4_flags.t10$v_mp2a_4_mode2_form2N#define t10$v_mp2a_4_multisession t10$r_mp2a_4_fSlags.t10$v_mp2a_4_multisession<#define t10$v_mp2a_4_buf t10$r_mp2a_4_flags.t10$v_mp2a_4_bufH#define t10$v_mp2a_5_supported t10$r_mp2a_5_flags.t10$v_mp2a_5_supportedF#define t10$v_mp2a_5_accurate t10$r_mp2a_5_flags.t10$v_mp2a_5_accurate:#define t10$v_mp2a_5_rw t10$r_mp2a_5_flags.t10$v_mp2a_5_rwH#define t10$v_mp2a_5_corrected t10$r_mp2a_5_flags.t10$v_mp2a_5_correctedJ#define t10$v_mp2a_5_c2pointers t10$r_mp2a_5_flags.t10$v_mp2a_5_c2pointers>#define t10$v_mp2a_5_isrc t10$r_mp2a_5_flags.t10$v_mp2a_ S5_isrc<#define t10$v_mp2a_5_upc t10$r_mp2a_5_flags.t10$v_mp2a_5_upcD#define t10$v_mp2a_5_barcode t10$r_mp2a_5_flags.t10$v_mp2a_5_barcode>#define t10$v_mp2a_6_lock t10$r_mp2a_6_flags.t10$v_mp2a_6_lock@#define t10$v_mp2a_6_state t10$r_mp2a_6_flags.t10$v_mp2a_6_stateD#define t10$v_mp2a_6_prevent t10$r_mp2a_6_flags.t10$v_mp2a_6_prevent@#define t10$v_mp2a_6_eject t10$r_mp2a_6_flags.t10$v_mp2a_6_eject@#define t10$v_mp2a_6_rsvd4 t10$r_mp2a_6_flags.t10$v_mp2a_6_rsvd4N#define t10$v_mp2a_6_loadmechtype St10$r_mp2a_6_flags.t10$v_mp2a_6_loadmechtypeB#define t10$v_mp2a_7_sepvol t10$r_mp2a_7_flags.t10$v_mp2a_7_sepvolD#define t10$v_mp2a_7_sepmute t10$r_mp2a_7_flags.t10$v_mp2a_7_sepmuteD#define t10$v_mp2a_7_present t10$r_mp2a_7_flags.t10$v_mp2a_7_present<#define t10$v_mp2a_7_sss t10$r_mp2a_7_flags.t10$v_mp2a_7_sssJ#define t10$v_mp2a_7_sidechange t10$r_mp2a_7_flags.t10$v_mp2a_7_sidechangeH#define t10$v_mp2a_7_rw_leadin t10$r_mp2a_7_flags.t10$v_mp2a_7_rw_leadin@#define t10$v_mp2a_7_rsvd6 t10$r_mp2a_7_ Sflags.t10$v_mp2a_7_rsvd6A#define t10$v_mp2a_17_bckf t10$r_mp2a_17_flags.t10$v_mp2a_17_bckf?#define t10$v_mp2a_17_rck t10$r_mp2a_17_flags.t10$v_mp2a_17_rckA#define t10$v_mp2a_17_lsbf t10$r_mp2a_17_flags.t10$v_mp2a_17_lsbfE#define t10$v_mp2a_17_length t10$r_mp2a_17_flags.t10$v_mp2a_17_lengthC#define t10$v_mp2a_17_rsvd6 t10$r_mp2a_17_flags.t10$v_mp2a_17_rsvd6E#define t10$v_mp2a_27_rotcon t10$r_mp2a_27_flags.t10$v_mp2a_27_rotcon/#define t10$b_mp2a_ws_rsvd0 t10$b_mp2a_ws_rsvd03#define t10$r_Smp2a_ws_rotctrl t10$r_mp2a_ws_rotctrlG#define t10$v_mp2a_ws_rotcon t10$r_mp2a_ws_rotctrl.t10$v_mp2a_ws_rotcon5#define t10$w_mp2a_write_speed t10$w_mp2a_write_speed"#endif /* #if !defined(__VAXC) */  struct mp3f { __struct {+ unsigned t10$v_mp3f_hdr_mpcode : 6;* unsigned t10$v_mp3f_hdr_fill1 : 1;' unsigned t10$v_mp3f_hdr_ps : 1; } t10$r_mp3f_hdr_flags; } ; #if !defined(__VAXC)H#define t10$v_mp3f_hdr_mpcode t10$r_mp3f_hdr_flags.t10$vS_mp3f_hdr_mpcode@#define t10$v_mp3f_hdr_ps t10$r_mp3f_hdr_flags.t10$v_mp3f_hdr_ps"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __T10DEF_LOADED */ ww[UM/*****************************S**********************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Developm Sent, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/*!S* **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */G/* Source: 18-MAY-1994 16:11:43 $1$DGA8345:[LIB_H.SRC]TASTDEF.SDL;1 *//***************************************************************************** "S***************************************************//*** MODULE $TASTDEF ***/#ifndef __TASTDEF_LOADED#define __TASTDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And#S set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* $S */N/* TERMINAL AST PACKET. THIS STRUCTURE IS USED BY TERMINAL SERVICES TO */N/* DELIVER OUT OF BAND CHARACTER ASTS. */N/* */ #define TAST$M_MASK_DSBL 0x1#define TAST$M_INCLUDE 0x2#define TAST$M_ONE_SHOT 0x4#define TAST$M_BUSY 0x8#define TAST$M_LOST 0x10#define TAST$M_ABORT 0x20#define TAST$K_LENGTH 60#defin%Se TAST$C_LENGTH 60#define TAST$M_ABO 0x4000#define TAST$M_INC 0x8000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _tast {#pragma __nomember_alignmentN int tastdef$$_fill_1 [9]; /*RESERVE ACB REGION */N struct _tast *tast$l_flink; /*FORWARD LINK */N int (*tast$l_ast)( &S); /*SAVED AST ADDRESS */N unsigned int tast$l_astprm; /*SAVED AST PARAMETER */N unsigned int tast$l_pid; /*SAVED PID */N unsigned char tast$b_rmod; /*SAVED RMOD */ __union {N unsigned char tast$b_ctrl; /*CONTROL FIELD */ __struct {N unsigned tast$v_mask_dsbl : 1; /*DISABLE MASK PROCESSING */N 'S unsigned tast$v_include : 1; /*INCLUDE CHARACTER */N unsigned tast$v_one_shot : 1; /*ONE SHOT AST */N unsigned tast$v_busy : 1; /*BLOCK BUSY */N unsigned tast$v_lost : 1; /*AST LOST */N unsigned tast$v_abort : 1; /*ABORT I/O */( unsigned tast$v_fill_0_ : 2; } tast$r_ctrl_bits; } tast$r_ctrl_overlay;N unsi (Sgned short int tast$w_chan; /*CHANNEL */N unsigned int tast$l_mask; /*OUT OF BAND MASK */ __struct {N unsigned tast$v_fill : 14; /* First byte and spares */N unsigned tast$v_abo : 1; /* ABORT flag */N unsigned tast$v_inc : 1; /* INCLUDE flag */ } tast$r_status_bits; char tast$b_fill_1_ [2]; } TAST; #if !defined(__V )SAXC)3#define tast$b_ctrl tast$r_ctrl_overlay.tast$b_ctrlN#define tast$v_mask_dsbl tast$r_ctrl_overlay.tast$r_ctrl_bits.tast$v_mask_dsblJ#define tast$v_include tast$r_ctrl_overlay.tast$r_ctrl_bits.tast$v_includeL#define tast$v_one_shot tast$r_ctrl_overlay.tast$r_ctrl_bits.tast$v_one_shotD#define tast$v_busy tast$r_ctrl_overlay.tast$r_ctrl_bits.tast$v_busyD#define tast$v_lost tast$r_ctrl_overlay.tast$r_ctrl_bits.tast$v_lostF#define tast$v_abort tast$r_ctrl_overlay.tast$r_ctrl_bits.tast$v_abort2 *S#define tast$v_fill tast$r_status_bits.tast$v_fill0#define tast$v_abo tast$r_status_bits.tast$v_abo0#define tast$v_inc tast$r_status_bits.tast$v_inc"#endif /* #if !defined(__VAXC) */ T#define TAST$S_TASTDEF 64 /* Old size name, synonym for TAST$S_TAST */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#e+Sndif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TASTDEF_LOADED */ wwD[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone,S without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** th-Se prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 * .S/F/* Source: 28-JAN-2004 08:32:06 $1$DGA8345:[LIB_H.SRC]TIEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TIEDEF ***/#ifndef __TIEDEF_LOADED#define __TIEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supp/Sorted */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#e0Sndif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define TIE$K_GSMATCH 0#define TIE$K_PROC_KIND 1#define TIE$K_CALL_PROC 2$#define TIE$K_NATIVE_TO_TRANSLATED 3'#define TIE$K_NATIVE_TO_TRANSLATED_BP 4#define TIE$K_LONGJMP_RESTORE 5"#define TIE$K_GET_INVO_HANDLE_64 6 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __requ1Sired_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TIEDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development2S, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M3S/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************* 4S***********************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */H/* Source: 26-SEP-2001 15:19:04 $1$DGA8345:[LIB_H.SRC]TITANDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TITANDEF ***/#ifndef __TITANDEF_LOADED#define __TITANDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __5Snomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !d6Sefined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */J/* Version: 'X-6' */N/* */N/* 7S */N/************************************************************************* */N/* * */N/* Copyright 2000 Compaq Computer Corporation * */N/* * */N/* COMPAQ Registered in U.S. Patent and Trademark Office. * */N/* 8S * */N/* Confidential computer software. Valid license from Compaq or * */N/* authorized sublicensor required for possession, use or copying. * */N/* Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * */N/* Computer Software Documentation, and Technical Data for Commercial * */N/* Items are licensed to the U.S. Government under vendor's standard * */N/* commercial license. * */N/* 9S * */N/* Compaq shall not be liable for technical or editorial errors or * */N/* omissions contained herein. The information in this document is * */N/* subject to change without notice. * */N/* * */N/************************************************************************* */N/* :S */N/* FACILITY: OpenVMS AXP System Macro Libraries */N/* */N/* ABSTRACT: */N/* */J/* This file defines the control and status registers of the Titan Chip */O/* Set (an extemsion of Tsunami), designed for use in EV6-8 based plat;Sforms. */N/* */L/* Because of the disparities in the address spaces for the various chips */W/* in the Titan Chip Set, it structure is defined as three distinct data stuctures, */^/* C chip (TITAN_C), D chip (TITAN_D), and the P chip (TITAN_P). There is one C Chip */_/* (C4+ - up to four processors), as many as eight D Chips (D+) and as many as two P Chips, */O/* (the PA-chip [PCI + AGP] and the PP-chip [2 PCIs] = 0, single byte valid in */4/* quadword access, 16 MB accessible */F/* 801 a000 0000 256 MB C chip CSRs, addr<5:0> = 0, quadword access */J/* -------------------------------------------------------------------- */N/*>S */J/* -------------------------------------------------------------------- */I/* D chip Address Space */J/* -------------------------------------------------------------------- */I/* 801 b000 0000 256 MB D chip CSRs, addr<5:0> = 0, all eight bytes in */4/* quadword access must be identical. */J/* -------------------------------------------------------------------?S- */N/* */J/* -------------------------------------------------------------------- */I/* P chip-0 Address Space */J/* -------------------------------------------------------------------- */F/* 801 8000 0000 256 MB P chip CSRs, addr<5:0> = 0, quadword access */N/* */F/* 800 0000 0000 4 GB GPCI Memory @S */F/* 801 f800 0000 64 MB GPCI IACK/Special */F/* 801 fc00 0000 32 MB GPCI IO */F/* 801 fe00 0000 16 MB GPCI config space */N/* */I/* 804 0000 0000 4 GB APCI Memory */G/* 805 f800 0000 64 MB APCI IACK/Special */I/* 805 fc00 0000 32 MB AASPCI IO */G/* 805 fe00 0000 16 MB APCI config space */J/* -------------------------------------------------------------------- */I/* */J/* -------------------------------------------------------------------- */I/* P chip-1 Address Space */J/* -------------------------------------------------------------------- */F/* 8BS03 8000 0000 256 MB P chip CSRs, addr<5:0> = 0, quadword access */N/* */F/* 802 0000 0000 4 GB GPCI Memory */F/* 803 f800 0000 64 MB GPCI IACK/Special */F/* 803 fc00 0000 32 MB GPCI IO */F/* 803 fe00 0000 16 MB GPCI config space */N/* CS */G/* 806 0000 0000 4 MB APCI Memory */N/* 807 f800 0000 64 MB APCI IACK/Special */F/* 807 fc00 0000 32 MB APCI IO */F/* 807 fe00 0000 16 MB APCI config space */N/* */N/* */J/* -----------------------------------DS--------------------------------- */N/* */N/* AUTHOR: */N/* */'/* Walt Arbo 03-Jan-2000 */N/* */N/* MODIFIED BY: */N/* ES */-/* X-6 GBH Gary Huff 26-Sep-2001 */B/* Add AGP bit definitions to apctl. */N/* *///* X-5 TLC Tony Camuso 29-Aug-2001 */C/* Bug: without MCTL register at 801.A000.0500, as in Tsunami, */B/* displacement for for MPR3 register must be %xC0, not %x80. */N/* FS */-/* X-4 WDA W.D. Arbo 26-Apr-2001 */B/* Add overlays to the Pchip for AGPERROR, AGPERREN, */B/* AGPERRSET and AGPLASTWR. They mirror SERROR, SERREN, */B/* SERRSET and Reserved. It all depends on whether the Pchip */B/* definition maps Pchip's 0 and 1 (SERROR etc.) or 2 and 3 */B/* (AGPERROR etc). */N/* */-/* X-3 WDA W.D. Arbo 15- GSMay-2000 */B/* When I put this file into LIB, it had duplicate */B/* symbol definitions with TSUNAMIDEF.SDL for things like */B/* C_CHIP (duh!). Put TITAN into all the names (TITAN_C */B/* for C_CHIP etc.) */N/* */-/* X-2 WDA W.D. Arbo 10-May-2000 */B/* A few fixes. */N/* HS */2/* X-1 WDA W.D. Arbo 03-Jan-2000 */G/* Based on Tony Camuso's work on Tsunami support */B/* (TSUNAMIDEF.SDL). */I/* */N/*-- */N/* The maximum number of CPUs supported by the Titan chipset */N/* IS */#define TITAN$K_MAX_CPU 4#define TITAN$C_MAX_CPU 4N/* */Q/* Since SDL currently doesn't support constants greater 2**32, the high-order */N/* bits (%X80x) have their own constants defined. */N/* */N/* Titan Chip Set CSR base addresses <63:32> (High longwor JSd) */N/* =========================================================== */N/* */#define TITAN$L_C_CHIP_H 2049#define TITAN$L_D_CHIP_H 2049N/* */"#define TITAN$L_P0_CHIP_CSR_H 2049##define TITAN$L_P0_CHIP_GMEM_H 2048"#define TITAN$L_P0_CHIP_GIO_H 2049&#define TITAN$L_P0_CHIP_GCONFIG_H 2049##define TITAN$L_P0_CHIP_AMEM_H KS 2052"#define TITAN$L_P0_CHIP_AIO_H 2053&#define TITAN$L_P0_CHIP_ACONFIG_H 2053N/* */"#define TITAN$L_P1_CHIP_CSR_H 2051##define TITAN$L_P1_CHIP_GMEM_H 2050"#define TITAN$L_P1_CHIP_GIO_H 2051&#define TITAN$L_P1_CHIP_GCONFIG_H 2051##define TITAN$L_P1_CHIP_AMEM_H 2054"#define TITAN$L_P1_CHIP_AIO_H 2055&#define TITAN$L_P1_CHIP_ACONFIG_H 2055N/* */LSN/* */N/* Titan Chip Set CSR base addresses <31:0> (Low longword) */N/* ========================================================= */N/* */N#define TITAN$L_C_CHIP_L -1610612736 /* Cchip */N#define TITAN$L_D_CHIP_L -1342177280 /* Dchip */N/* MS */N/* */N/* P-Chip */N/* ------ */*#define TITAN$L_P_CHIP_CSR_0_L -2147483648*#define TITAN$L_P_CHIP_CSR_1_L -2147479552#define TITAN$L_P_CHIP_MEM_L 0%#define TITAN$L_P_CHIP_IO_L -67108864(#define TITAN$L_P_CHIP_IACK_L -134217728)#define NSTITAN$L_P_CHIP_CONFIG_L -33554432N/* */N/* */O/*************************************************************************** */N/* */N/* Titan Chip Set Structures */N/* OS */O/*************************************************************************** */N/* */O/*========================================================================== */N/* */N/* C-CHIP Structure */O/*========================================================================== */ c#if PS!defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _titan_c {N/* */N/* 801.A000.000 */N/* */N/* CSC - C-Chip System Configuration Register QS */N/* */#pragma __nomember_alignment __union {( unsigned __int64 titan_c$iq_csc;% unsigned char csc$b_pad [64]; } titan_c$r_csc_overlay;N/* */N/* 801.A000.0040 */N/* RS*/N/* MTR - C-Chip Memory Timing Register */N/* */ __union {( unsigned __int64 titan_c$iq_mtr;% unsigned char mtr$b_pad [64]; } titan_c$r_mtr_overlay;N/* */N/* 801.A000.0080 */N/* SS */N/* MISC - C-Chip Miscellaneous Register */N/* */ __union {) unsigned __int64 titan_c$iq_misc;% unsigned char csc$b_pad [64];! } titan_c$r_misc_overlay;N/* */N/* 801.A000.00C0 */N/* TS */N/* MPD - C-Chip Memory Presence Detect */N/* */ __union {( unsigned __int64 titan_c$iq_mpd;% unsigned char mpd$b_pad [64]; } titan_c$r_mpd_overlay;N/* */N/* 801.A000.0100 US */N/* */N/* AAR0 - C-Chip Array Address Register 0 */N/* */ __union {) unsigned __int64 titan_c$iq_aar0;& unsigned char aar0$b_pad [64];! } titan_c$r_aar0_overlay;N/* */N/* 801.A000.0140 VS */N/* */N/* AAR1 - C-Chip Array Address Register 1 */N/* */ __union {) unsigned __int64 titan_c$iq_aar1;& unsigned char aar1$b_pad [64];! } titan_c$r_aar1_overlay;N/* */N/* 801.A000.01 WS80 */N/* */N/* AAR2 - C-Chip Array Address Register 2 */N/* */ __union {) unsigned __int64 titan_c$iq_aar2;& unsigned char aar2$b_pad [64];! } titan_c$r_aar2_overlay;N/* XS */N/* 801.A000.01C0 */N/* */N/* AAR3 - C-Chip Array Address Register 3 */N/* */ __union {) unsigned __int64 titan_c$iq_aar3;& unsigned char aar3$b_pad [64];! } titan_c$r_aar3_overlay;N/* YS */N/* 801.A000.0200 */N/* */N/* DIM0 - C-Chip Device Interrupt Mask Register 0 */N/* */ __union {) unsigned __int64 titan_c$iq_dim0;& unsigned char dim0$b_pad [64];! } titan_c$r_dim0_overlay;N/* ZS */N/* 801.A000.0240 */N/* */N/* DIM1 - C-Chip Device Interrupt Mask Register 1 */N/* */ __union {) unsigned __int64 titan_c$iq_dim1;& unsigned char dim1$b_pad [64];! } [Stitan_c$r_dim1_overlay;N/* */N/* 801.A000.0280 */N/* */N/* DIR0 - C-Chip Device Interrupt Request Register */N/* */ __union {) unsigned __int64 titan_c$iq_dir0;& unsigned cha \Sr dir0$b_pad [64];! } titan_c$r_dir0_overlay;N/* */N/* 801.A000.02C0 */N/* */N/* DIR1 - C-Chip Device Interrupt Request Register */N/* */ __union {) unsigned __int64 titan_c$i ]Sq_dir1;& unsigned char dir1$b_pad [64];! } titan_c$r_dir1_overlay;N/* */N/* 801.A000.0300 */N/* */N/* DRIR - C-Chip Raw Interrupt Request Register */N/* */ __union {) ^S unsigned __int64 titan_c$iq_drir;& unsigned char drir$b_pad [64];! } titan_c$r_drir_overlay;N/* */N/* 801.A000.0340 */N/* */N/* PRBEN - C-Chip Probe Enable Register */N/* _S */ __union {* unsigned __int64 titan_c$iq_prben;' unsigned char prben$b_pad [64];" } titan_c$r_prben_overlay;N/* */N/* 801.A000.0380 */N/* */N/* IIC0 - C-Chip Interval Ignore Count Register 0 */N/* `S */ __union {) unsigned __int64 titan_c$iq_iic0;& unsigned char iic0$b_pad [64];! } titan_c$r_iic0_overlay;N/* */N/* 801.A000.03C0 */N/* */N/* IIC1 - C-Chip Interval Ignore Count Register 1 */N/* aS */ __union {) unsigned __int64 titan_c$iq_iic1;& unsigned char iic1$b_pad [64];! } titan_c$r_iic1_overlay;N/* */N/* 801.A000.0400 */N/* */N/* MPR0 - C-Chip Memory Programming Register 0 bS */N/* */ __union {) unsigned __int64 titan_c$iq_mpr0;& unsigned char mpr0$b_pad [64];! } titan_c$r_mpr0_overlay;N/* */N/* 801.A000.0440 */N/* */N/* MPR1 - C-Chip Memory Prog cSramming Register 1 */N/* */ __union {) unsigned __int64 titan_c$iq_mpr1;& unsigned char mpr1$b_pad [64];! } titan_c$r_mpr1_overlay;N/* */N/* 801.A000.0480 */N/* */ dSN/* MPR2 - C-Chip Memory Programming Register 2 */N/* */ __union {) unsigned __int64 titan_c$iq_mpr2;& unsigned char mpr2$b_pad [64];! } titan_c$r_mpr2_overlay;N/* */N/* 801.A000.04C0 */N/* eS */N/* MPR3 - C-Chip Memory Programming Register 3 */N/* */ __union {) unsigned __int64 titan_c$iq_mpr3;' unsigned char mpr3$b_pad [192];! } titan_c$r_mpr3_overlay;N/* */N/* 801.A000.0580 */N/* fS */N/* TTR - C-Chip TIG Bus Timing Register */N/* */ __union {( unsigned __int64 titan_c$iq_ttr;% unsigned char ttr$b_pad [64]; } titan_c$r_ttr_overlay;N/* */N/* 801.A000.05C0 gS */N/* */N/* TDR - C-Chip TIG Bus Device Timing Register */N/* */ __union {( unsigned __int64 titan_c$iq_tdr;% unsigned char tdr$b_pad [64]; } titan_c$r_tdr_overlay;N/* */N/* 801.A000.0600 hS */N/* */N/* DIM2 - C-Chip Device Interrupt Mask Register 2 */N/* */ __union {) unsigned __int64 titan_c$iq_dim2;& unsigned char dim2$b_pad [64];! } titan_c$r_dim2_overlay;N/* */N/* 801.A000.06 iS40 */N/* */N/* DIM3 - C-Chip Device Interrupt Mask Register 3 */N/* */ __union {) unsigned __int64 titan_c$iq_dim3;& unsigned char dim3$b_pad [64];! } titan_c$r_dim3_overlay;N/* jS */N/* 801.A000.0680 */N/* */N/* DIR2 - C-Chip Device Interrupt Request Register 2 */N/* */ __union {) unsigned __int64 titan_c$iq_dir2;& unsigned char dir2$b_pad [64];! } titan_c$r_dir2_overlay;N/* kS */N/* 801.A000.06C0 */N/* */N/* DIR3 - C-Chip Device Interrupt Request Register 3 */N/* */ __union {) unsigned __int64 titan_c$iq_dir3;& unsigned char dir3$b_pad [64];! } titan_c$r_dir3_overlay;N/* lS */N/* 801.A000.0700 */N/* */N/* IIC2 - C-Chip Interval Ignore Count Register 2 */N/* */ __union {) unsigned __int64 titan_c$iq_iic2;& unsigned char iic2$b_pad [64];! } mStitan_c$r_iic2_overlay;N/* */N/* 801.A000.0740 */N/* */N/* IIC3 - C-Chip Interval Ignore Count Register 3 */N/* */ __union {) unsigned __int64 titan_c$iq_iic3;& unsigned cha nSr iic3$b_pad [64];! } titan_c$r_iic3_overlay;N/* */N/* 801.A000.A780 */N/* */N/* PWR - C-Chip Power Management Control */N/* */ __union {( unsigned __int64 titan_c$i oSq_pwr;' unsigned char pwr$b_pad [1152]; } titan_c$r_pwr_overlay;N/* */N/* 801.A000.0C00 */N/* */N/* CMONCTLA - C-Chip Monitor Control A */N/* */ __union {- pS unsigned __int64 titan_c$iq_cmonctla;* unsigned char cmonctla$b_pad [64];% } titan_c$r_cmonctla_overlay;N/* */N/* 801.A000.0C40 */N/* */N/* CMONCTLB - C-Chip Monitor Control B */N/* qS */ __union {- unsigned __int64 titan_c$iq_cmonctlb;* unsigned char cmonctlb$b_pad [64];% } titan_c$r_cmonctlb_overlay;N/* */N/* 801.A000.0C80 */N/* */N/* CMONCNT01- C-Chip Monitor Counter 01 */N/* rS */ __union {. unsigned __int64 titan_c$iq_cmoncnt01;+ unsigned char cmoncnt01$b_pad [64];& } titan_c$r_cmoncnt01_overlay;N/* */N/* 801.A000.0CC0 */N/* */N/* CMONCNT23- C-Chip Monitor Counter 23 sS */N/* */ __union {. unsigned __int64 titan_c$iq_cmoncnt23;+ unsigned char cmoncnt23$b_pad [64];& } titan_c$r_cmoncnt23_overlay;N/* */N/* 801.A000.0D00 */N/* */N/* CPEN- C tS-Chip (Reserved for future use) */N/* */ __union {) unsigned __int64 titan_c$iq_cpen;( unsigned char cpen$b_pad [4864];! } titan_c$r_cpen_overlay; } TITAN_C; #if !defined(__VAXC);#define titan_c$iq_csc titan_c$r_csc_overlay.titan_c$iq_csc;#define titan_c$iq_mtr titan_c$r_mtr_overlay.titan_c$iq_mtr>#define titan_c$iq_misc titan_c$r_misc_overlay.titan uS_c$iq_misc;#define titan_c$iq_mpd titan_c$r_mpd_overlay.titan_c$iq_mpd>#define titan_c$iq_aar0 titan_c$r_aar0_overlay.titan_c$iq_aar0>#define titan_c$iq_aar1 titan_c$r_aar1_overlay.titan_c$iq_aar1>#define titan_c$iq_aar2 titan_c$r_aar2_overlay.titan_c$iq_aar2>#define titan_c$iq_aar3 titan_c$r_aar3_overlay.titan_c$iq_aar3>#define titan_c$iq_dim0 titan_c$r_dim0_overlay.titan_c$iq_dim0>#define titan_c$iq_dim1 titan_c$r_dim1_overlay.titan_c$iq_dim1>#define titan_c$iq_dir0 titan_c$r_dir0_overlay.t vSitan_c$iq_dir0>#define titan_c$iq_dir1 titan_c$r_dir1_overlay.titan_c$iq_dir1>#define titan_c$iq_drir titan_c$r_drir_overlay.titan_c$iq_drirA#define titan_c$iq_prben titan_c$r_prben_overlay.titan_c$iq_prben>#define titan_c$iq_iic0 titan_c$r_iic0_overlay.titan_c$iq_iic0>#define titan_c$iq_iic1 titan_c$r_iic1_overlay.titan_c$iq_iic1>#define titan_c$iq_mpr0 titan_c$r_mpr0_overlay.titan_c$iq_mpr0>#define titan_c$iq_mpr1 titan_c$r_mpr1_overlay.titan_c$iq_mpr1>#define titan_c$iq_mpr2 titan_c$r_mpr2 wS_overlay.titan_c$iq_mpr2>#define titan_c$iq_mpr3 titan_c$r_mpr3_overlay.titan_c$iq_mpr3;#define titan_c$iq_ttr titan_c$r_ttr_overlay.titan_c$iq_ttr;#define titan_c$iq_tdr titan_c$r_tdr_overlay.titan_c$iq_tdr>#define titan_c$iq_dim2 titan_c$r_dim2_overlay.titan_c$iq_dim2>#define titan_c$iq_dim3 titan_c$r_dim3_overlay.titan_c$iq_dim3>#define titan_c$iq_dir2 titan_c$r_dir2_overlay.titan_c$iq_dir2>#define titan_c$iq_dir3 titan_c$r_dir3_overlay.titan_c$iq_dir3>#define titan_c$iq_iic2 titan_c$r_iixSc2_overlay.titan_c$iq_iic2>#define titan_c$iq_iic3 titan_c$r_iic3_overlay.titan_c$iq_iic3;#define titan_c$iq_pwr titan_c$r_pwr_overlay.titan_c$iq_pwrJ#define titan_c$iq_cmonctla titan_c$r_cmonctla_overlay.titan_c$iq_cmonctlaJ#define titan_c$iq_cmonctlb titan_c$r_cmonctlb_overlay.titan_c$iq_cmonctlbM#define titan_c$iq_cmoncnt01 titan_c$r_cmoncnt01_overlay.titan_c$iq_cmoncnt01M#define titan_c$iq_cmoncnt23 titan_c$r_cmoncnt23_overlay.titan_c$iq_cmoncnt23>#define titan_c$iq_cpen titan_c$r_cpen_o ySverlay.titan_c$iq_cpen"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* */O/*========================================================================== */N/* */N/* D-CHIP Structure zS */N/* */S/* NOTE: All the registers in this structure are abstracted as 64-bit entities. */N/* Therefore, they MUST be accessed and manipulated as quadwords and with */I/* quadwords. */I/* */O/*================================================================== {S======== */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _titan_d {N/* */N/* 801.B000.0800 */N/* */N/* DSC - D-Chip System Configu |Sration Register */N/* */#pragma __nomember_alignment __union {( unsigned __int64 titan_d$iq_dsc;% unsigned char dsc$b_pad [64]; } titan_d$r_dsc_overlay;N/* */N/* 801.B000.0840 */N/* }S */N/* STR - D-Chip System Timing Register */N/* */ __union {( unsigned __int64 titan_d$iq_str;% unsigned char str$b_pad [64]; } titan_d$r_str_overlay;N/* */N/* 801.B000.0880 */N/* ~S */N/* DREV - D-Chip System Configuration Register */N/* */ __union {) unsigned __int64 titan_d$iq_drev;& unsigned char drev$b_pad [64];! } titan_d$r_drev_overlay;N/* */N/* */ SN/* 801.B000.08C0 */N/* */N/* DSC2 - D-Chip (Reserved for future use) */N/* */ __union {) unsigned __int64 titan_d$iq_dsc2;& unsigned char dsc2$b_pad [64];! } titan_d$r_dsc2_overlay;N/* S */ } TITAN_D; #if !defined(__VAXC);#define titan_d$iq_dsc titan_d$r_dsc_overlay.titan_d$iq_dsc;#define titan_d$iq_str titan_d$r_str_overlay.titan_d$iq_str>#define titan_d$iq_drev titan_d$r_drev_overlay.titan_d$iq_drev>#define titan_d$iq_dsc2 titan_d$r_dsc2_overlay.titan_d$iq_dsc2"#endif /* #if !defined(__VAXC) */ N/* */N/* S */N/* */O/*========================================================================== */N/* */N/* P chip Structure - These are the common registers (G and A) of the */O/* two halves of a PAchip or a PPchip. Remember that hose 2 or hose 3 could */N/* be an AGP bus. */N/*S */N/* The four PCI chips have base address as follows: */I/* PCI 0 Pchip 0 Hose 0 G-port 801.8000.0000 */N/* PCI 1 Pchip 1 Hose 1 G-port 803.8000.0000 */G/* PCI 2 Pchip 0 Hose 2 A-port 801.8000.1000 */I/* PCI 3 Pchip 1 Hose 3 A-port 803.8000.1000 */N/* S */O/*========================================================================== */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _titan_p {N/* */N/* 80x.8000.0000 */N/* S */N/* WSBA0 - P-CHip Window Space Base Address Register 0 */N/* */#pragma __nomember_alignment __union {* unsigned __int64 titan_p$iq_wsba0;' unsigned char wsba0$b_pad [64];" } titan_p$r_wsba0_overlay;N/* */N/* 80x.8000.0040 S */N/* */N/* WSBA1 - P-CHip Window Space Base Address Register 1 */N/* */ __union {* unsigned __int64 titan_p$iq_wsba1;' unsigned char wsba1$b_pad [64];" } titan_p$r_wsba1_overlay;N/* S */N/* 80x.8000.0080 */N/* */N/* WSBA2 - P-CHip Window Space Base Address Register 2 */N/* */ __union {* unsigned __int64 titan_p$iq_wsba2;' unsigned char wsba2$b_pad [64];" } titan_p$r_wsba2_overlay;N/* S */N/* 80x.8000.00C0 */N/* */N/* WSBA3 - P-CHip Window Space Base Address Register 3 */N/* */ __union {* unsigned __int64 titan_p$iq_wsba3;' unsigned char wsba3$b_pad [64];" } titan_p$r_wsba3_overlay;N/* S */N/* 80x.8000.0100 */N/* */N/* WSM0 - P-Chip Window Space Mask Register 0 */N/* */ __union {) unsigned __int64 titan_p$iq_wsm0;& unsigned char wsm0$b_pad [64];! } ti Stan_p$r_wsm0_overlay;N/* */N/* 80x.8000.0140 */N/* */N/* WSM1 - P-Chip Window Space Mask Register 1 */N/* */ __union {) unsigned __int64 titan_p$iq_wsm1;& unsigned char Swsm1$b_pad [64];! } titan_p$r_wsm1_overlay;N/* */N/* 80x.8000.0180 */N/* */N/* WSM2 - P-Chip Window Space Mask Register 2 */N/* */ __union {) unsigned __int64 titan_p$iq_ Swsm2;& unsigned char wsm2$b_pad [64];! } titan_p$r_wsm2_overlay;N/* */N/* 80x.8000.01C0 */N/* */N/* WSM3 - P-Chip Window Space Mask Register 3 */N/* */ __union {) S unsigned __int64 titan_p$iq_wsm3;& unsigned char wsm3$b_pad [64];! } titan_p$r_wsm3_overlay;N/* */N/* 80x.8000.0200 */N/* */N/* TBA0 - P-Chip Translated Base Address Register 0 */N/* S */ __union {) unsigned __int64 titan_p$iq_tba0;& unsigned char tba0$b_pad [64];! } titan_p$r_tba0_overlay;N/* */N/* 80x.8000.0240 */N/* */N/* TBA1 - P-Chip Translated Base Address Register 1 */N/* S */ __union {) unsigned __int64 titan_p$iq_tba1;& unsigned char tba1$b_pad [64];! } titan_p$r_tba1_overlay;N/* */N/* 80x.8000.0280 */N/* */N/* TBA2 - P-Chip Translated Base Address Register 2 */N/* S */ __union {) unsigned __int64 titan_p$iq_tba2;& unsigned char tba2$b_pad [64];! } titan_p$r_tba2_overlay;N/* */N/* 80x.8000.02C0 */N/* */N/* TBA3 - P-Chip Translated Base Address Register 3 S */N/* */ __union {) unsigned __int64 titan_p$iq_tba3;& unsigned char tba3$b_pad [64];! } titan_p$r_tba3_overlay;N/* */N/* 80x.8000.0300 */N/* */N/* PCTL - P-Chip Control Registe Sr */N/* */ __union {) unsigned __int64 titan_p$iq_pctl;& unsigned char pctl$b_pad [64];! } titan_p$r_pctl_overlay;N/* */N/* 80x.8000.0340 */N/* */N/* S PLAT - P-Chip Master Latency Register */N/* */ __union {) unsigned __int64 titan_p$iq_plat;' unsigned char plat$b_pad [192];! } titan_p$r_plat_overlay;N/* */N/* 80x.8000.0400 */N/* S */N/* SERROR - P-Chip System Error Register */N/* */ __union {+ unsigned __int64 titan_p$iq_serror;- unsigned __int64 titan_p$iq_agperror;( unsigned char serror$b_pad [64];# } titan_p$r_serror_overlay;N/* */N/* 80x.8000.0440 S */N/* */N/* SERREN - P-Chip System Error Enable Register */N/* */ __union {+ unsigned __int64 titan_p$iq_serren;- unsigned __int64 titan_p$iq_agperren;( unsigned char serren$b_pad [64];# } titan_p$r_serren_overlay;N/* S */N/* 80x.8000.0480 */N/* */N/* SERRSET - P-Chip System Error Set Register */N/* */ __union {, unsigned __int64 titan_p$iq_serrset;. unsigned __int64 titan_p$iq_agperrset;) unsigned char serrset$b_pad [6 S4];$ } titan_p$r_serrset_overlay;N/* */N/* 80x.8000.04C0 */N/* */N/* AGPLASTWR - P-Chip Last Write Register */N/* */ __union {. unsigned __int64 titan_p$iq_agplastwr; S+ unsigned char agplastwr$b_pad [64];& } titan_p$r_agplastwr_overlay;N/* */N/* 80x.8000.0500 */N/* */N/* PERROR - P-Chip Error Register */N/* */ __union {+ S unsigned __int64 titan_p$iq_perror;( unsigned char perror$b_pad [64];# } titan_p$r_perror_overlay;N/* */N/* 80x.8000.0540 */N/* */N/* PERREN - P-Chip Error Enable Register */N/* S */ __union {+ unsigned __int64 titan_p$iq_perren;( unsigned char perren$b_pad [64];# } titan_p$r_perren_overlay;N/* */N/* 80x.8000.0580 */N/* */N/* PERRSET - P-Chip Error Set Register */N/* S */ __union {, unsigned __int64 titan_p$iq_perrset;* unsigned char perrset$b_pad [128];$ } titan_p$r_perrset_overlay;N/* */N/* 80x.8000.0600 */N/* */N/* TLBIV - P-Chip Translation Buffer Invalidate Virtual Register S */N/* */ __union {* unsigned __int64 titan_p$iq_tlbiv;' unsigned char tlbiv$b_pad [64];" } titan_p$r_tlbiv_overlay;N/* */N/* 80x.8000.0640 */N/* */N/* TLBIA - P-Chip Translation Buffer S Invalidate all Register */N/* */ __union {* unsigned __int64 titan_p$iq_tlbia;( unsigned char tlbia$b_pad [192];" } titan_p$r_tlbia_overlay;N/* */N/* 80x.8000.0700 */N/* */N/* S SCTL - P-Chip System Control Register */N/* */ __union {) unsigned __int64 titan_p$iq_sctl;' unsigned char sctl$b_pad [256];! } titan_p$r_sctl_overlay;N/* */N/* 80x.8000.0800 */N/* S */N/* SPRST - Software PCI Reset Register */N/* */ __union {* unsigned __int64 titan_p$iq_sprst;" } titan_p$r_sprst_overlay; } TITAN_P; #if !defined(__VAXC)A#define titan_p$iq_wsba0 titan_p$r_wsba0_overlay.titan_p$iq_wsba0A#define titan_p$iq_wsba1 titan_p$r_wsba1_overlay.titan_p$iq_wsba1A#define titan_p$iq_wsba2 titan_p$r_wsba2_ove Srlay.titan_p$iq_wsba2A#define titan_p$iq_wsba3 titan_p$r_wsba3_overlay.titan_p$iq_wsba3>#define titan_p$iq_wsm0 titan_p$r_wsm0_overlay.titan_p$iq_wsm0>#define titan_p$iq_wsm1 titan_p$r_wsm1_overlay.titan_p$iq_wsm1>#define titan_p$iq_wsm2 titan_p$r_wsm2_overlay.titan_p$iq_wsm2>#define titan_p$iq_wsm3 titan_p$r_wsm3_overlay.titan_p$iq_wsm3>#define titan_p$iq_tba0 titan_p$r_tba0_overlay.titan_p$iq_tba0>#define titan_p$iq_tba1 titan_p$r_tba1_overlay.titan_p$iq_tba1>#define titan_p$iq_tba2 titan_Sp$r_tba2_overlay.titan_p$iq_tba2>#define titan_p$iq_tba3 titan_p$r_tba3_overlay.titan_p$iq_tba3>#define titan_p$iq_pctl titan_p$r_pctl_overlay.titan_p$iq_pctl>#define titan_p$iq_plat titan_p$r_plat_overlay.titan_p$iq_platD#define titan_p$iq_serror titan_p$r_serror_overlay.titan_p$iq_serrorH#define titan_p$iq_agperror titan_p$r_serror_overlay.titan_p$iq_agperrorD#define titan_p$iq_serren titan_p$r_serren_overlay.titan_p$iq_serrenH#define titan_p$iq_agperren titan_p$r_serren_overlay.titan_p$iq_agSperrenG#define titan_p$iq_serrset titan_p$r_serrset_overlay.titan_p$iq_serrsetK#define titan_p$iq_agperrset titan_p$r_serrset_overlay.titan_p$iq_agperrsetM#define titan_p$iq_agplastwr titan_p$r_agplastwr_overlay.titan_p$iq_agplastwrD#define titan_p$iq_perror titan_p$r_perror_overlay.titan_p$iq_perrorD#define titan_p$iq_perren titan_p$r_perren_overlay.titan_p$iq_perrenG#define titan_p$iq_perrset titan_p$r_perrset_overlay.titan_p$iq_perrsetA#define titan_p$iq_tlbiv titan_p$r_tlbiv_overlay.tit San_p$iq_tlbivA#define titan_p$iq_tlbia titan_p$r_tlbia_overlay.titan_p$iq_tlbia>#define titan_p$iq_sctl titan_p$r_sctl_overlay.titan_p$iq_sctlA#define titan_p$iq_sprst titan_p$r_sprst_overlay.titan_p$iq_sprst"#endif /* #if !defined(__VAXC) */ O/*************************************************************************** */N/* */X/* Bit Definitions for the Titan Chip Set Registers. Since many of these definitions */S`/* are not used, I deleted definitions for Tsunami-only registers and updated Titan ones, but */N/* did not add any new Titan ones. */N/* */O/*************************************************************************** */O/*========================================================================== */N/* */N/*S C-Chip Registers */N/* */O/*========================================================================== */N/* */N/* */N/* Titan CSC - C-Chip System Configuration Register */N/* S */#define TITAN_CSC$M_BC 0x3#define TITAN_CSC$M_C0CFP 0x4#define TITAN_CSC$M_C1CFP 0x8#define TITAN_CSC$M_SED 0x30#define TITAN_CSC$M_SFD 0x40#define TITAN_CSC$M_FW 0x80#define TITAN_CSC$M_AW 0x100#define TITAN_CSC$M_IDDR 0xE00#define TITAN_CSC$M_IDDW 0x3000#define TITAN_CSC$M_P1P 0x4000!#define TITAN_CSC$M_RSVD_0 0x8000 #define TITAN_CSC$M_DWTP 0x30000 #define TITAN_CSC$M_DWFP 0xC0000!#define TITAN_CSC$M_DRTP 0x300000##dSefine TITAN_CSC$M_RSVD_1 0xC00000!#define TITAN_CSC$M_PME 0x1000000!#define TITAN_CSC$M_QPM 0x2000000!#define TITAN_CSC$M_FET 0xC000000"#define TITAN_CSC$M_QDI 0x70000000"#define TITAN_CSC$M_EFT 0x80000000##define TITAN_CSC$M_FTI 0x100000000##define TITAN_CSC$M_B1D 0x200000000##define TITAN_CSC$M_B2D 0x400000000##define TITAN_CSC$M_B3D 0x800000000(#define TITAN_CSC$M_TPQMMAX 0xF000000000)#define TITAN_CSC$M_FPQCMAX 0xF0000000000*#define TITAN_CSC$M_FPQPMAX 0xF00000000000*#define STITAN_CSC$M_PDTMAX 0x7000000000000'#define TITAN_CSC$M_AXD 0x8000000000000+#define TITAN_CSC$M_PRQMAX 0x70000000000000,#define TITAN_CSC$M_ADD4PTP 0x80000000000000,#define TITAN_CSC$M_PBQMAX 0x700000000000000-#define TITAN_CSC$M_RSVD_7 0x3800000000000000,#define TITAN_CSC$M_NODQM 0x4000000000000000*#define TITAN_CSC$M_ISM 0x8000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#elsSe#pragma __nomember_alignment#endiftypedef union _titan_csc {#pragma __nomember_alignment' unsigned __int64 titan_csc$iq_data; __struct {$ unsigned int titan_csc$il_l;$ unsigned int titan_csc$il_h; } titan_csc$r_longwords; __struct {N unsigned titan_csc$v_bc : 2; /* 1:0 Base Configuration */N unsigned titan_csc$v_c0cfp : 1; /* 2 CPU 0 Clk Fwd Preset */N unsigned titan_csc$v_c1cfp : 1; /* 3 CPU 1 Clk FwdS Preset */N unsigned titan_csc$v_sed : 2; /* 5:4 SysDC Extract Delay */N unsigned titan_csc$v_sfd : 1; /* 6 SysDC Fill Delay */N unsigned titan_csc$v_fw : 1; /* 7 available for firmware */N unsigned titan_csc$v_aw : 1; /* 8 Array Width */N unsigned titan_csc$v_iddr : 3; /* 11:9 Issue to Data Delay on read */X unsigned titan_csc$v_iddw : 2; /* 13:12 Issue to Data Delay for all xactionSs */N unsigned titan_csc$v_p1p : 1; /* 14 P-Chip 1 present */N unsigned titan_csc$v_rsvd_0 : 1; /* 15 reserved */W unsigned titan_csc$v_dwtp : 2; /* 17:16 Min Dchip Delay from CPU to PAD bus */` unsigned titan_csc$v_dwfp : 2; /* 19:18 Min Dchip Delay from PADbus to CPU or Memory */Z unsigned titan_csc$v_drtp : 2; /* 21:20 Min Dchip Delay from Memory to PAD bus */N unsigned titan_csc$v_rsvd_1 : 2; /* 23:22 reserved S */N unsigned titan_csc$v_pme : 1; /* 24 Page Mode Enable */N unsigned titan_csc$v_qpm : 1; /* 25 Que Priority Mode */U unsigned titan_csc$v_fet : 2; /* 27:26 Fill to Extract Turnaround cycles */N unsigned titan_csc$v_qdi : 3; /* 30:28 Que Drain Interval */R unsigned titan_csc$v_eft : 1; /* 31 Extract to Fill Turnaround cycles */N/* S */N unsigned titan_csc$v_fti : 1; /* 32 Full Throttle Issue */N unsigned titan_csc$v_b1d : 1; /* 33 Bypass 1 Issue Path Disable */N unsigned titan_csc$v_b2d : 1; /* 34 Bypass 2 Issue Path Disable */N unsigned titan_csc$v_b3d : 1; /* 35 Bypass 3 Issue Path Disable */\ unsigned titan_csc$v_tpqmmax : 4; /* 39:36 Max entries in TPQM on D-Chips, mod 16 */P unsigned titan_csc$v_fpqcmax : 4; /* 43:40 Max entries in FQP, mod 16 */O S unsigned titan_csc$v_fpqpmax : 4; /* 47:44 Max entries in FPQ, mod 8 */b unsigned titan_csc$v_pdtmax : 3; /* 50:48 Max data xfers to one P-Chip until ack, mod 8 */N unsigned titan_csc$v_axd : 1; /* 51 Disable Memory Address XOR */_ unsigned titan_csc$v_prqmax : 3; /* 54:52 max reqests to one P-Chip until ack, mod 8 */N unsigned titan_csc$v_add4ptp : 1; /* 55 Additional 4 PTP */N unsigned titan_csc$v_pbqmax : 3; /* 58:56 Max CPU probe queue S */N unsigned titan_csc$v_rsvd_7 : 3; /* 61:59 reserved */_ unsigned titan_csc$v_nodqm : 1; /* 62 Set to 1, DMA partial writes to memory use DQM */N unsigned titan_csc$v_ism : 1; /* 63 Interrupt Strobe Mode bit */ } titan_csc$r_bits; } TITAN_CSC; #if !defined(__VAXC);#define titan_csc$il_l titan_csc$r_longwords.titan_csc$il_l;#define titan_csc$il_h titan_csc$r_longwords.titan_csc$il_h6#define titan_csc$v_bc titan_csc$r_bits. Stitan_csc$v_bc<#define titan_csc$v_c0cfp titan_csc$r_bits.titan_csc$v_c0cfp<#define titan_csc$v_c1cfp titan_csc$r_bits.titan_csc$v_c1cfp8#define titan_csc$v_sed titan_csc$r_bits.titan_csc$v_sed8#define titan_csc$v_sfd titan_csc$r_bits.titan_csc$v_sfd6#define titan_csc$v_fw titan_csc$r_bits.titan_csc$v_fw6#define titan_csc$v_aw titan_csc$r_bits.titan_csc$v_aw:#define titan_csc$v_iddr titan_csc$r_bits.titan_csc$v_iddr:#define titan_csc$v_iddw titan_csc$r_bits.titan_csc$v_iddw8#define titan_csc$ Sv_p1p titan_csc$r_bits.titan_csc$v_p1p>#define titan_csc$v_rsvd_0 titan_csc$r_bits.titan_csc$v_rsvd_0:#define titan_csc$v_dwtp titan_csc$r_bits.titan_csc$v_dwtp:#define titan_csc$v_dwfp titan_csc$r_bits.titan_csc$v_dwfp:#define titan_csc$v_drtp titan_csc$r_bits.titan_csc$v_drtp>#define titan_csc$v_rsvd_1 titan_csc$r_bits.titan_csc$v_rsvd_18#define titan_csc$v_pme titan_csc$r_bits.titan_csc$v_pme8#define titan_csc$v_qpm titan_csc$r_bits.titan_csc$v_qpm8#define titan_csc$v_fet titan_csc$r_bits.t Sitan_csc$v_fet8#define titan_csc$v_qdi titan_csc$r_bits.titan_csc$v_qdi8#define titan_csc$v_eft titan_csc$r_bits.titan_csc$v_eft8#define titan_csc$v_fti titan_csc$r_bits.titan_csc$v_fti8#define titan_csc$v_b1d titan_csc$r_bits.titan_csc$v_b1d8#define titan_csc$v_b2d titan_csc$r_bits.titan_csc$v_b2d8#define titan_csc$v_b3d titan_csc$r_bits.titan_csc$v_b3d@#define titan_csc$v_tpqmmax titan_csc$r_bits.titan_csc$v_tpqmmax@#define titan_csc$v_fpqcmax titan_csc$r_bits.titan_csc$v_fpqcmax@#define ti Stan_csc$v_fpqpmax titan_csc$r_bits.titan_csc$v_fpqpmax>#define titan_csc$v_pdtmax titan_csc$r_bits.titan_csc$v_pdtmax8#define titan_csc$v_axd titan_csc$r_bits.titan_csc$v_axd>#define titan_csc$v_prqmax titan_csc$r_bits.titan_csc$v_prqmax@#define titan_csc$v_add4ptp titan_csc$r_bits.titan_csc$v_add4ptp>#define titan_csc$v_pbqmax titan_csc$r_bits.titan_csc$v_pbqmax>#define titan_csc$v_rsvd_7 titan_csc$r_bits.titan_csc$v_rsvd_7<#define titan_csc$v_nodqm titan_csc$r_bits.titan_csc$v_nodqm8#define Stitan_csc$v_ism titan_csc$r_bits.titan_csc$v_ism"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan MTR - C-Chip Memory Timing Register */N/* */#define TITAN_MTR$M_RCD 0x1#define TITAN_MTR$M_RSVD_0 0x2#define TITAN_MTR$M_CAT 0x4#defSine TITAN_MTR$M_RSVD_1 0x8#define TITAN_MTR$M_IRD 0x70#define TITAN_MTR$M_RSVD_2 0x80#define TITAN_MTR$M_RPW 0x300 #define TITAN_MTR$M_RSVD_3 0xC00#define TITAN_MTR$M_RPT 0x3000!#define TITAN_MTR$M_RSVD_4 0xC000#define TITAN_MTR$M_RRD 0x10000"#define TITAN_MTR$M_RSVD_5 0xE0000 #define TITAN_MTR$M_MPD 0x100000##define TITAN_MTR$M_RSVD_6 0xE00000!#define TITAN_MTR$M_RI 0x3F000000%#define TITAN_MTR$M_RSVD_7 0xC0000000$#define TITAN_MTR$M_PHCR 0xF00000000%#define TITAN_MTR$M_PHCWS 0xF000000000&#define TITAN_MTR$M_MPH 0x3F0000000000-#define TITAN_MTR$M_RSVD_8 0xFFFFC00000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_mtr {#pragma __nomember_alignment' unsigned __int64 titan_mtr$iq_data; __struct {$ unsigned int titan_mtr$il_l;$ unsigned int titan_mtr$il_h; } titaSn_mtr$r_longwords; __struct {N unsigned titan_mtr$v_rcd : 1; /* 0 RAS to CAS Delay */N unsigned titan_mtr$v_rsvd_0 : 1; /* 1 reserved */N unsigned titan_mtr$v_cat : 1; /* 2 CAS Access Time */N unsigned titan_mtr$v_rsvd_1 : 1; /* 3 reserved */N unsigned titan_mtr$v_ird : 3; /* 6:4 Issue to RAS Delay */N unsigned titan_mtr$v_rsvd_2 : 1; /* 7 reserved S */N unsigned titan_mtr$v_rpw : 2; /* 9:8 Minimum RAS Pulse Width */N unsigned titan_mtr$v_rsvd_3 : 2; /* 11:10 reserved */N unsigned titan_mtr$v_rpt : 2; /* 13:12 Min RAS Precharge Time */N unsigned titan_mtr$v_rsvd_4 : 2; /* 15:14 reserved */Z unsigned titan_mtr$v_rrd : 1; /* 16 Min Same-Array_Diff-Bank RAS-to-RAS Delay */N unsigned titan_mtr$v_rsvd_5 : 3; /* 19:17 reserved */N S unsigned titan_mtr$v_mpd : 1; /* 20 Mask Pipeline Delay */N unsigned titan_mtr$v_rsvd_6 : 3; /* 23:21 reserved */N unsigned titan_mtr$v_ri : 6; /* 29:24 Refresh Interval */N unsigned titan_mtr$v_rsvd_7 : 2; /* 31:30 reserved */N/* */N unsigned titan_mtr$v_phcr : 4; /* 35:32 Page Hit Cycles for Reads */N unsigned titan_mtr$v S_phcw : 4; /* 39:36 Page Hit Cycles for Writes */N unsigned titan_mtr$v_mph : 6; /* 45:40 Max Page Hits */N unsigned titan_mtr$v_rsvd_8 : 18; /* 63:46 reserved */ } titan_mtr$r_bits; } TITAN_MTR; #if !defined(__VAXC);#define titan_mtr$il_l titan_mtr$r_longwords.titan_mtr$il_l;#define titan_mtr$il_h titan_mtr$r_longwords.titan_mtr$il_h8#define titan_mtr$v_rcd titan_mtr$r_bits.titan_mtr$v_rcd>#define titan_mtr$v_rsvd_0 titan_mtr$r S_bits.titan_mtr$v_rsvd_08#define titan_mtr$v_cat titan_mtr$r_bits.titan_mtr$v_cat>#define titan_mtr$v_rsvd_1 titan_mtr$r_bits.titan_mtr$v_rsvd_18#define titan_mtr$v_ird titan_mtr$r_bits.titan_mtr$v_ird>#define titan_mtr$v_rsvd_2 titan_mtr$r_bits.titan_mtr$v_rsvd_28#define titan_mtr$v_rpw titan_mtr$r_bits.titan_mtr$v_rpw>#define titan_mtr$v_rsvd_3 titan_mtr$r_bits.titan_mtr$v_rsvd_38#define titan_mtr$v_rpt titan_mtr$r_bits.titan_mtr$v_rpt>#define titan_mtr$v_rsvd_4 titan_mtr$r_bits.titan_mtr$v_ Srsvd_48#define titan_mtr$v_rrd titan_mtr$r_bits.titan_mtr$v_rrd>#define titan_mtr$v_rsvd_5 titan_mtr$r_bits.titan_mtr$v_rsvd_58#define titan_mtr$v_mpd titan_mtr$r_bits.titan_mtr$v_mpd>#define titan_mtr$v_rsvd_6 titan_mtr$r_bits.titan_mtr$v_rsvd_66#define titan_mtr$v_ri titan_mtr$r_bits.titan_mtr$v_ri>#define titan_mtr$v_rsvd_7 titan_mtr$r_bits.titan_mtr$v_rsvd_7:#define titan_mtr$v_phcr titan_mtr$r_bits.titan_mtr$v_phcr:#define titan_mtr$v_phcw titan_mtr$r_bits.titan_mtr$v_phcw8#define titan_ Smtr$v_mph titan_mtr$r_bits.titan_mtr$v_mph>#define titan_mtr$v_rsvd_8 titan_mtr$r_bits.titan_mtr$v_rsvd_8"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan MISC - C-Chip Miscellaneous Register */N/* */#define TITAN_MISC$M_CPUID 0x3#definSe TITAN_MISC$M_RSVD_0 0xC #define TITAN_MISC$M_ITINTR 0xF0!#define TITAN_MISC$M_IPINTR 0xF00!#define TITAN_MISC$M_IPREQ 0xF000 #define TITAN_MISC$M_ABW 0xF0000!#define TITAN_MISC$M_ABT 0xF00000"#define TITAN_MISC$M_ACL 0x1000000%#define TITAN_MISC$M_RSVD_6 0xE000000##define TITAN_MISC$M_NXM 0x10000000##define TITAN_MISC$M_NXS 0xE0000000%#define TITAN_MISC$M_REV 0xFF00000000)#define TITAN_MISC$M_DEVSUP 0xF0000000000.#define TITAN_MISC$M_RSVD_7 0xFFFFF00000000000 c#if !defined(_ S_NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_misc {#pragma __nomember_alignment __struct {P unsigned titan_misc$v_cpuid : 2; /* 0:1 ID of CPU performing the read */N unsigned titan_misc$v_rsvd_0 : 2; /* 3:2 reserved */T unsigned titan_misc$v_itintr : 4; /* 7:4 Interval Timer Interrupt pending */U S unsigned titan_misc$v_ipintr : 4; /* 11:8 Interprocessor Interrupt pending */U unsigned titan_misc$v_ipreq : 4; /* 15:12 Interprocessor Interrupt Request */N unsigned titan_misc$v_abw : 4; /* 19:16 Arbitration Won */N unsigned titan_misc$v_abt : 4; /* 23:20 Arbitration Try */N unsigned titan_misc$v_acl : 1; /* 24 Arbitration Clear */N unsigned titan_misc$v_rsvd_6 : 3; /* 27:25 reserved */N unsignSed titan_misc$v_nxm : 1; /* 28 Non eXistent Memory */N unsigned titan_misc$v_nxs : 3; /* 31:29 NXM Source */N/* */N unsigned titan_misc$v_rev : 8; /* 39:32 C-Chip Revision */N unsigned titan_misc$v_devsup : 4; /* 43:40 Suppress IRQ[1] */N unsigned titan_misc$v_rsvd_7 : 20; /* 63:44 reserved */ } titan_misc$r_bits; } TITA SN_MISC; #if !defined(__VAXC)?#define titan_misc$v_cpuid titan_misc$r_bits.titan_misc$v_cpuidA#define titan_misc$v_rsvd_0 titan_misc$r_bits.titan_misc$v_rsvd_0A#define titan_misc$v_itintr titan_misc$r_bits.titan_misc$v_itintrA#define titan_misc$v_ipintr titan_misc$r_bits.titan_misc$v_ipintr?#define titan_misc$v_ipreq titan_misc$r_bits.titan_misc$v_ipreq;#define titan_misc$v_abw titan_misc$r_bits.titan_misc$v_abw;#define titan_misc$v_abt titan_misc$r_bits.titan_misc$v_abt;#define ti Stan_misc$v_acl titan_misc$r_bits.titan_misc$v_aclA#define titan_misc$v_rsvd_6 titan_misc$r_bits.titan_misc$v_rsvd_6;#define titan_misc$v_nxm titan_misc$r_bits.titan_misc$v_nxm;#define titan_misc$v_nxs titan_misc$r_bits.titan_misc$v_nxs;#define titan_misc$v_rev titan_misc$r_bits.titan_misc$v_revA#define titan_misc$v_devsup titan_misc$r_bits.titan_misc$v_devsupA#define titan_misc$v_rsvd_7 titan_misc$r_bits.titan_misc$v_rsvd_7"#endif /* #if !defined(__VAXC) */ N/* S */N/* */N/* Titan MPD - C-Chip Memory Presence Detect */N/* */#define TITAN_MPD$M_CKS 0x1#define TITAN_MPD$M_DS 0x2#define TITAN_MPD$M_CKR 0x4#define TITAN_MPD$M_DR 0x8%#define TITAN_MPD$M_RSVD_0 0xFFFFFFF0-#define TITAN_MPD$M_RSVD_1 0xFFFFFFFF00000000 c#i Sf !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_mpd {#pragma __nomember_alignment __struct {N unsigned titan_mpd$v_cks : 1; /* 0 ClocK Send */N unsigned titan_mpd$v_ds : 1; /* 1 Data Send */N unsigned titan_mpd$v_ckr : 1; /* 2 ClocK Receive */N S unsigned titan_mpd$v_dr : 1; /* 3 Data Receive */N unsigned titan_mpd$v_rsvd_0 : 28; /* 31:4 reserved */N/* */N unsigned titan_mpd$v_rsvd_1 : 32; /* 63:32 reserved */ } titan_mpd$r_bits; } TITAN_MPD; #if !defined(__VAXC)8#define titan_mpd$v_cks titan_mpd$r_bits.titan_mpd$v_cks6#define titan_mpd$v_ds titan_mpd$r_bits.titan_mpd$v_ds8 S#define titan_mpd$v_ckr titan_mpd$r_bits.titan_mpd$v_ckr6#define titan_mpd$v_dr titan_mpd$r_bits.titan_mpd$v_dr>#define titan_mpd$v_rsvd_0 titan_mpd$r_bits.titan_mpd$v_rsvd_0>#define titan_mpd$v_rsvd_1 titan_mpd$r_bits.titan_mpd$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan AAR - C-Chip Array Address Register S */N/* */#define TITAN_AAR$M_BNKS 0x3#define TITAN_AAR$M_ROWS 0xC#define TITAN_AAR$M_RSVD_1 0xF0#define TITAN_AAR$M_SA 0x100#define TITAN_AAR$M_DSA 0x200 #define TITAN_AAR$M_RSVD_2 0xC00#define TITAN_AAR$M_ASIZ 0xF000#define TITAN_AAR$M_DBG 0x10000##define TITAN_AAR$M_RSVD_4 0xFE0000$#define TITAN_AAR$M_ADDR 0x7FF000000-#define TITAN_AAR$M_RSVD_5 0x7FFFFFF800000000 c#if !defined(__NOBASEALISGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_aar {#pragma __nomember_alignment' unsigned __int64 titan_aar$iq_data; __struct {$ unsigned int titan_aar$il_l;$ unsigned int titan_aar$il_h; } titan_aar$r_longwords; __struct {O unsigned titan_aar$v_bnks : 2; /* 1:0 Number of Bank bits in SDRAMs */N unsiSgned titan_aar$v_rows : 2; /* 3:2 Number of Row bits in SDRAMS */N unsigned titan_aar$v_rsvd_1 : 4; /* 7:4 reserved */N unsigned titan_aar$v_sa : 1; /* 8 Split Array */N unsigned titan_aar$v_dsa : 1; /* 9 Doubly (twice) Split Array */N unsigned titan_aar$v_rsvd_2 : 2; /* 11:10 reserved */N unsigned titan_aar$v_asiz : 4; /* 15:12 Array Size */^ unsigned titan_aar$v_dbg : 1; S /* 16 Enables this memory port as a debug interface */N unsigned titan_aar$v_rsvd_4 : 7; /* 23:17 reserved */N unsigned titan_aar$v_addr : 11; /* 34:24 Base Address */N unsigned titan_aar$v_rsvd_5 : 28; /* 63:35 reserved */) unsigned titan_aar$v_fill_0_ : 1; } titan_aar$r_bits; } TITAN_AAR; #if !defined(__VAXC);#define titan_aar$il_l titan_aar$r_longwords.titan_aar$il_l;#define titan_aar$il_h titan S_aar$r_longwords.titan_aar$il_h:#define titan_aar$v_bnks titan_aar$r_bits.titan_aar$v_bnks:#define titan_aar$v_rows titan_aar$r_bits.titan_aar$v_rows>#define titan_aar$v_rsvd_1 titan_aar$r_bits.titan_aar$v_rsvd_16#define titan_aar$v_sa titan_aar$r_bits.titan_aar$v_sa8#define titan_aar$v_dsa titan_aar$r_bits.titan_aar$v_dsa>#define titan_aar$v_rsvd_2 titan_aar$r_bits.titan_aar$v_rsvd_2:#define titan_aar$v_asiz titan_aar$r_bits.titan_aar$v_asiz8#define titan_aar$v_dbg titan_aar$r_bits.titan_aar S$v_dbg>#define titan_aar$v_rsvd_4 titan_aar$r_bits.titan_aar$v_rsvd_4:#define titan_aar$v_addr titan_aar$r_bits.titan_aar$v_addr>#define titan_aar$v_rsvd_5 titan_aar$r_bits.titan_aar$v_rsvd_5"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan DIM - C-Chip Device Interrupt Mask Registers */N/* S */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_dim {#pragma __nomember_alignment' unsigned __int64 titan_dim$iq_data; __struct {$ unsigned int titan_dim$il_l;$ unsigned int titan_dim$il_h; } titan_dim$r_longwords; } TITAN_DIM; #if !defined S(__VAXC);#define titan_dim$il_l titan_dim$r_longwords.titan_dim$il_l;#define titan_dim$il_h titan_dim$r_longwords.titan_dim$il_h"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan DIR - C-Chip Device Interrupt Request Registers */N/* */$#define TITASN_DIR$M_DEV_L 0xFFFFFFFF*#define TITAN_DIR$M_DEV_H 0xFFFFFF00000000,#define TITAN_DIR$M_RSVD_0 0x300000000000000*#define TITAN_DIR$M_ERR 0xFC00000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_dir {#pragma __nomember_alignment' unsigned __int64 titan_dir$iq_data; __struct {$ unsigned int titan_dir$il_ Sl;$ unsigned int titan_dir$il_h; } titan_dir$r_longwords; __struct {R unsigned titan_dir$v_dev_l : 32; /* 31:0 IRQ[1] PCI Interrupts Pending */R unsigned titan_dir$v_dev_h : 24; /* 55:32 IRQ[1] PCI Interrupts Pending */N unsigned titan_dir$v_rsvd_0 : 2; /* 57:56 reserved */N unsigned titan_dir$v_err : 6; /* 63:58 IRQ[0] Error Interrupts */ } titan_dir$r_bits; } TITAN_DIR; #if !defined(__VAXC);#define ti Stan_dir$il_l titan_dir$r_longwords.titan_dir$il_l;#define titan_dir$il_h titan_dir$r_longwords.titan_dir$il_h<#define titan_dir$v_dev_l titan_dir$r_bits.titan_dir$v_dev_l<#define titan_dir$v_dev_h titan_dir$r_bits.titan_dir$v_dev_h>#define titan_dir$v_rsvd_0 titan_dir$r_bits.titan_dir$v_rsvd_08#define titan_dir$v_err titan_dir$r_bits.titan_dir$v_err"#endif /* #if !defined(__VAXC) */ N/* */N/* S */N/* Titan DRIR - C-Chip Raw Interrupt Request Register */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_drir {#pragma __nomember_alignment( unsigned __int64 titan_drir$iq_datSa; __struct {% unsigned int titan_drir$il_l;% unsigned int titan_drir$il_h;! } titan_drir$r_longwords; } TITAN_DRIR; #if !defined(__VAXC)>#define titan_drir$il_l titan_drir$r_longwords.titan_drir$il_l>#define titan_drir$il_h titan_drir$r_longwords.titan_drir$il_h"#endif /* #if !defined(__VAXC) */ N/* */N/* S */N/* Titan PRBEN - C-Chip Probe Enable Register */N/* */#define TITAN_PRBEN$M_PRBEN 0x1'#define TITAN_PRBEN$M_RSVD_0 0xFFFFFFFE/#define TITAN_PRBEN$M_RSVD_1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan S_prben {#pragma __nomember_alignment) unsigned __int64 titan_prben$iq_data; __struct {& unsigned int titan_prben$il_l;& unsigned int titan_prben$il_h;" } titan_prben$r_longwords; __struct {N unsigned titan_prben$v_prben : 1; /* 0 Probe Enable bit */N unsigned titan_prben$v_rsvd_0 : 31; /* 31:1 Reserved */N unsigned titan_prben$v_rsvd_1 : 32; /* 63:32 Reserved */ } titan_prben$r_bits; S } TITAN_PRBEN; #if !defined(__VAXC)A#define titan_prben$il_l titan_prben$r_longwords.titan_prben$il_lA#define titan_prben$il_h titan_prben$r_longwords.titan_prben$il_hB#define titan_prben$v_prben titan_prben$r_bits.titan_prben$v_prbenD#define titan_prben$v_rsvd_0 titan_prben$r_bits.titan_prben$v_rsvd_0D#define titan_prben$v_rsvd_1 titan_prben$r_bits.titan_prben$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* S */N/* */N/* Titan IIC - C-Chip Interval Ignore Count Registers */N/* */!#define TITAN_IIC$M_ICNT 0xFFFFFF #define TITAN_IIC$M_OF 0x1000000%#define TITAN_IIC$M_RSVD_0 0xFE000000-#define TITAN_IIC$M_RSVD_1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ *S/'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_iic {#pragma __nomember_alignment' unsigned __int64 titan_iic$iq_data; __struct {$ unsigned int titan_iic$il_l;$ unsigned int titan_iic$il_h; } titan_iic$r_longwords; __struct {Z unsigned titan_iic$v_icnt : 24; /* 23:0 Count of remaining interrupts to ignore */N unsigned titan_iic$v_of : 1; /* 24 Overflow bit S*/N unsigned titan_iic$v_rsvd_0 : 7; /* 31:25 reserved */N unsigned titan_iic$v_rsvd_1 : 32; /* 63:32 reserved */ } titan_iic$r_bits; } TITAN_IIC; #if !defined(__VAXC);#define titan_iic$il_l titan_iic$r_longwords.titan_iic$il_l;#define titan_iic$il_h titan_iic$r_longwords.titan_iic$il_h:#define titan_iic$v_icnt titan_iic$r_bits.titan_iic$v_icnt6#define titan_iic$v_of titan_iic$r_bits.titan_iic$v_of>#define titan_iic$v_rsvd_0 t Sitan_iic$r_bits.titan_iic$v_rsvd_0>#define titan_iic$v_rsvd_1 titan_iic$r_bits.titan_iic$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan MPR - C-Chip Memory Programming Registers */N/* */!#define TITAN_MPR$M_MPRDAT 0x1FFF%#define TISTAN_MPR$M_RSVD_0 0xFFFFE000-#define TITAN_MPR$M_RSVD_1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_mpr {#pragma __nomember_alignment' unsigned __int64 titan_mpr$iq_data; __struct {$ unsigned int titan_mpr$il_l;$ unsigned int titan_mpr$il_h; } titan_mpr$r_longwords; __ Sstruct {] unsigned titan_mpr$v_mprdat : 13; /* 12:0 Data to be written on address lines 12:0 */N unsigned titan_mpr$v_rsvd_0 : 19; /* 31:13 reserved */N unsigned titan_mpr$v_rsvd_1 : 32; /* 63:32 reserved */ } titan_mpr$r_bits; } TITAN_MPR; #if !defined(__VAXC);#define titan_mpr$il_l titan_mpr$r_longwords.titan_mpr$il_l;#define titan_mpr$il_h titan_mpr$r_longwords.titan_mpr$il_h>#define titan_mpr$v_mprdat titan_mpr$r_b Sits.titan_mpr$v_mprdat>#define titan_mpr$v_rsvd_0 titan_mpr$r_bits.titan_mpr$v_rsvd_0>#define titan_mpr$v_rsvd_1 titan_mpr$r_bits.titan_mpr$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan TTR - C-Chip TIG Bus Timing Register */N/* S */#define TITAN_TTR$M_AS 0x3#define TITAN_TTR$M_AH 0xC#define TITAN_TTR$M_IS 0xF0#define TITAN_TTR$M_IRT 0xF00#define TITAN_TTR$M_ID 0x7000%#define TITAN_TTR$M_RSVD_3 0xFFFF8000-#define TITAN_TTR$M_RSVD_4 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_ttr {#pragma __nomember_alignment __struSct {^ unsigned titan_ttr$v_as : 2; /* 1:0 Address Setup to the address latch before AS */S unsigned titan_ttr$v_ah : 2; /* 3:2 Address Hold after AS before CS_L */N unsigned titan_ttr$v_is : 4; /* 7:4 Interrupt Setup time */N unsigned titan_ttr$v_irt : 4; /* 11:8 Interrupt Read Time */N unsigned titan_ttr$v_id : 3; /* 14:12 Interrupt starting Device */N unsigned titan_ttr$v_rsvd_3 : 17; /* 31:15 reserved S*/N unsigned titan_ttr$v_rsvd_4 : 32; /* 63:32 reserved */ } titan_ttr$r_bits; } TITAN_TTR; #if !defined(__VAXC)6#define titan_ttr$v_as titan_ttr$r_bits.titan_ttr$v_as6#define titan_ttr$v_ah titan_ttr$r_bits.titan_ttr$v_ah6#define titan_ttr$v_is titan_ttr$r_bits.titan_ttr$v_is8#define titan_ttr$v_irt titan_ttr$r_bits.titan_ttr$v_irt6#define titan_ttr$v_id titan_ttr$r_bits.titan_ttr$v_id>#define titan_ttr$v_rsvd_3 titan_ttr$r_bits.titan_ttr$v_rsvd_3>#d Sefine titan_ttr$v_rsvd_4 titan_ttr$r_bits.titan_ttr$v_rsvd_4"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan TDR - C-Chip TIG Bus Device Timing Register */N/* */#define TITAN_TDR$M_RA0 0x1F#define TITAN_TDR$M_RD0 0xE0#define TITAN_TDR$M_WS0 S0xF00#define TITAN_TDR$M_WP0 0x7000#define TITAN_TDR$M_WH0 0x8000 #define TITAN_TDR$M_RA1 0x1F0000 #define TITAN_TDR$M_RD1 0xE00000!#define TITAN_TDR$M_WS1 0xF000000"#define TITAN_TDR$M_WP1 0x70000000"#define TITAN_TDR$M_WH1 0x80000000$#define TITAN_TDR$M_RA2 0x1F00000000$#define TITAN_TDR$M_RD2 0xE000000000%#define TITAN_TDR$M_WS2 0xF0000000000&#define TITAN_TDR$M_WP2 0x700000000000&#define TITAN_TDR$M_WH2 0x800000000000(#define TITAN_TDR$M_RA3 0x1F000000000000(#define TITAN_TDR$M_SRD3 0xE0000000000000)#define TITAN_TDR$M_WS3 0xF00000000000000*#define TITAN_TDR$M_WP3 0x7000000000000000*#define TITAN_TDR$M_WH3 0x8000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_tdr {#pragma __nomember_alignment' unsigned __int64 titan_tdr$iq_data; __struct {$ unsigned int titan_tdr$il_l;$ S unsigned int titan_tdr$il_h; } titan_tdr$r_longwords; __struct {N unsigned titan_tdr$v_ra0 : 5; /* 4:0 Read Access time */N unsigned titan_tdr$v_rd0 : 3; /* 7:5 Read output Disable time */N unsigned titan_tdr$v_ws0 : 4; /* 11:8 Write Setup time */N unsigned titan_tdr$v_wp0 : 3; /* 14:12 Write Pulse width */N unsigned titan_tdr$v_wh0 : 1; /* 15 Write Hold time */N/* S */N unsigned titan_tdr$v_ra1 : 5; /* 20:16 Read Access time */N unsigned titan_tdr$v_rd1 : 3; /* 23:21 Read output Disable time */N unsigned titan_tdr$v_ws1 : 4; /* 27:24 Write Setup time */N unsigned titan_tdr$v_wp1 : 3; /* 30:28 Write Pulse width */N unsigned titan_tdr$v_wh1 : 1; /* 31 Write Hold time */N/* S */N unsigned titan_tdr$v_ra2 : 5; /* 36:32 Read Access time */N unsigned titan_tdr$v_rd2 : 3; /* 39:37 Read output Disable time */N unsigned titan_tdr$v_ws2 : 4; /* 43:40 Write Setup time */N unsigned titan_tdr$v_wp2 : 3; /* 46:44 Write Pulse width */N unsigned titan_tdr$v_wh2 : 1; /* 47 Write Hold time */N/* S */N unsigned titan_tdr$v_ra3 : 5; /* 52:48 Read Access time */N unsigned titan_tdr$v_rd3 : 3; /* 55:53 Read output Disable time */N unsigned titan_tdr$v_ws3 : 4; /* 59:56 Write Setup time */N unsigned titan_tdr$v_wp3 : 3; /* 62:60 Write Pulse width */N unsigned titan_tdr$v_wh3 : 1; /* 63 Write Hold time */ } titan_tdr$r_bits; } TITAN_TDR; #if !defined(__VAXC);#define titan_tdr$il_l S titan_tdr$r_longwords.titan_tdr$il_l;#define titan_tdr$il_h titan_tdr$r_longwords.titan_tdr$il_h8#define titan_tdr$v_ra0 titan_tdr$r_bits.titan_tdr$v_ra08#define titan_tdr$v_rd0 titan_tdr$r_bits.titan_tdr$v_rd08#define titan_tdr$v_ws0 titan_tdr$r_bits.titan_tdr$v_ws08#define titan_tdr$v_wp0 titan_tdr$r_bits.titan_tdr$v_wp08#define titan_tdr$v_wh0 titan_tdr$r_bits.titan_tdr$v_wh08#define titan_tdr$v_ra1 titan_tdr$r_bits.titan_tdr$v_ra18#define titan_tdr$v_rd1 titan_tdr$r_bits.titan_tdr$v_rd1 S8#define titan_tdr$v_ws1 titan_tdr$r_bits.titan_tdr$v_ws18#define titan_tdr$v_wp1 titan_tdr$r_bits.titan_tdr$v_wp18#define titan_tdr$v_wh1 titan_tdr$r_bits.titan_tdr$v_wh18#define titan_tdr$v_ra2 titan_tdr$r_bits.titan_tdr$v_ra28#define titan_tdr$v_rd2 titan_tdr$r_bits.titan_tdr$v_rd28#define titan_tdr$v_ws2 titan_tdr$r_bits.titan_tdr$v_ws28#define titan_tdr$v_wp2 titan_tdr$r_bits.titan_tdr$v_wp28#define titan_tdr$v_wh2 titan_tdr$r_bits.titan_tdr$v_wh28#define titan_tdr$v_ra3 titan_tdr$r_bits S.titan_tdr$v_ra38#define titan_tdr$v_rd3 titan_tdr$r_bits.titan_tdr$v_rd38#define titan_tdr$v_ws3 titan_tdr$r_bits.titan_tdr$v_ws38#define titan_tdr$v_wp3 titan_tdr$r_bits.titan_tdr$v_wp38#define titan_tdr$v_wh3 titan_tdr$r_bits.titan_tdr$v_wh3"#endif /* #if !defined(__VAXC) */ O/*========================================================================== */N/* */N/* D-Chip Registers S */N/* */O/*========================================================================== */N/* */N/* */N/* Titan DSC - D-Chip System Configuration Register */N/* */S#define TITAN_DSC$M_BC 0x3#define TITAN_DSC$M_C0CFP 0x4#define TITAN_DSC$M_C1CFP 0x8#define TITAN_DSC$M_C2CFP 0x10#define TITAN_DSC$M_C3CFP 0x20#define TITAN_DSC$M_P1P 0x40#define TITAN_DSC$M_RSVD_0 0x80#define TITAN_DSC$M_BC1 0x300 #define TITAN_DSC$M_C0CFP1 0x400 #define TITAN_DSC$M_C1CFP1 0x800!#define TITAN_DSC$M_C2CFP1 0x1000!#define TITAN_DSC$M_C3CFP1 0x2000#define TITAN_DSC$M_P1P1 0x4000!#define TITAN_DSC$M_RSVD_1 0x8000#define TITAN_DSC$M_BC2 0x30000"#define STITAN_DSC$M_C0CFP2 0x40000"#define TITAN_DSC$M_C1CFP2 0x80000##define TITAN_DSC$M_C2CFP2 0x100000##define TITAN_DSC$M_C3CFP2 0x200000!#define TITAN_DSC$M_P1P2 0x400000##define TITAN_DSC$M_RSVD_2 0x800000!#define TITAN_DSC$M_BC3 0x3000000$#define TITAN_DSC$M_C0CFP3 0x4000000$#define TITAN_DSC$M_C1CFP3 0x8000000%#define TITAN_DSC$M_C2CFP3 0x10000000%#define TITAN_DSC$M_C3CFP3 0x20000000##define TITAN_DSC$M_P1P3 0x40000000%#define TITAN_DSC$M_RSVD_3 0x80000000##define TITAN_DSC$M_BC S4 0x300000000&#define TITAN_DSC$M_C0CFP4 0x400000000&#define TITAN_DSC$M_C1CFP4 0x800000000'#define TITAN_DSC$M_C2CFP4 0x1000000000'#define TITAN_DSC$M_C3CFP4 0x2000000000%#define TITAN_DSC$M_P1P4 0x4000000000'#define TITAN_DSC$M_RSVD_4 0x8000000000&#define TITAN_DSC$M_BC15 0x30000000000(#define TITAN_DSC$M_C0CFP5 0x40000000000(#define TITAN_DSC$M_C1CFP5 0x80000000000)#define TITAN_DSC$M_C2CFP5 0x100000000000)#define TITAN_DSC$M_C3CFP5 0x200000000000'#define TITAN_DSC$M_P1P5 0x40000 S0000000)#define TITAN_DSC$M_RSVD_5 0x800000000000'#define TITAN_DSC$M_BC6 0x3000000000000*#define TITAN_DSC$M_C0CFP6 0x4000000000000*#define TITAN_DSC$M_C1CFP6 0x8000000000000+#define TITAN_DSC$M_C2CFP6 0x10000000000000+#define TITAN_DSC$M_C3CFP6 0x20000000000000)#define TITAN_DSC$M_P1P6 0x40000000000000+#define TITAN_DSC$M_RSVD_6 0x80000000000000)#define TITAN_DSC$M_BC7 0x300000000000000,#define TITAN_DSC$M_C0CFP7 0x400000000000000,#define TITAN_DSC$M_C1CFP7 0x800000000000000-#defSine TITAN_DSC$M_C2CFP7 0x1000000000000000-#define TITAN_DSC$M_C3CFP7 0x2000000000000000+#define TITAN_DSC$M_P1P7 0x4000000000000000-#define TITAN_DSC$M_RSVD_7 0x8000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_dsc {#pragma __nomember_alignment' unsigned __int64 titan_dsc$iq_data; __struct {$ Sunsigned int titan_dsc$il_l;$ unsigned int titan_dsc$il_h; } titan_dsc$r_longwords; __struct {N unsigned titan_dsc$v_bc : 2; /* 1:0 Base Configuration */N unsigned titan_dsc$v_c0cfp : 1; /* 2 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c1cfp : 1; /* 3 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c2cfp : 1; /* 4 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c3cfp : 1; /* 5 CPU 0 Clock Forward PSreset */N unsigned titan_dsc$v_p1p : 1; /* 6 P-Chip_1 Preset */N unsigned titan_dsc$v_rsvd_0 : 1; /* 7 reserved */N/* */N unsigned titan_dsc$v_bc1 : 2; /* 9:8 Base Configuration */N unsigned titan_dsc$v_c0cfp1 : 1; /* 10 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c1cfp1 : 1; /* 11 CPU 0 Clock Forward Preset */N unsiSgned titan_dsc$v_c2cfp1 : 1; /* 12 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c3cfp1 : 1; /* 13 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_p1p1 : 1; /* 14 P-Chip_1 Preset */N unsigned titan_dsc$v_rsvd_1 : 1; /* 15 reserved */N/* */N unsigned titan_dsc$v_bc2 : 2; /* 17:16 Base Configuration */N unsigned titan_dsc$v_c0cfp2 : S1; /* 18 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c1cfp2 : 1; /* 19 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c2cfp2 : 1; /* 20 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c3cfp2 : 1; /* 21 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_p1p2 : 1; /* 22 P-Chip_1 Preset */N unsigned titan_dsc$v_rsvd_2 : 1; /* 23 reserved */N/* S */N unsigned titan_dsc$v_bc3 : 2; /* 25:24 Base Configuration */N unsigned titan_dsc$v_c0cfp3 : 1; /* 26 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c1cfp3 : 1; /* 27 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c2cfp3 : 1; /* 28 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c3cfp3 : 1; /* 29 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_p1p3 : 1; /* 30 P-Chip_1 Preset */N unSsigned titan_dsc$v_rsvd_3 : 1; /* 31 reserved */N/* */N unsigned titan_dsc$v_bc4 : 2; /* 33:32 Base Configuration */N unsigned titan_dsc$v_c0cfp4 : 1; /* 34 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c1cfp4 : 1; /* 35 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c2cfp4 : 1; /* 36 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c3cfp4 S: 1; /* 37 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_p1p4 : 1; /* 38 P-Chip_1 Preset */N unsigned titan_dsc$v_rsvd_4 : 1; /* 39 reserved */N/* */N unsigned titan_dsc$v_bc15 : 2; /* 41:40 Base Configuration */N unsigned titan_dsc$v_c0cfp5 : 1; /* 42 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c1cfp5 : 1; /* 43 CPU 0 Clock ForSward Preset */N unsigned titan_dsc$v_c2cfp5 : 1; /* 44 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c3cfp5 : 1; /* 45 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_p1p5 : 1; /* 46 P-Chip_1 Preset */N unsigned titan_dsc$v_rsvd_5 : 1; /* 47 reserved */N/* */N unsigned titan_dsc$v_bc6 : 2; /* 49:48 Base Configuration */N Sunsigned titan_dsc$v_c0cfp6 : 1; /* 50 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c1cfp6 : 1; /* 51 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c2cfp6 : 1; /* 52 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c3cfp6 : 1; /* 53 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_p1p6 : 1; /* 54 P-Chip_1 Preset */N unsigned titan_dsc$v_rsvd_6 : 1; /* 55 reserved */N/* S */N unsigned titan_dsc$v_bc7 : 2; /* 57:56 Base Configuration */N unsigned titan_dsc$v_c0cfp7 : 1; /* 58 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c1cfp7 : 1; /* 59 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c2cfp7 : 1; /* 60 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_c3cfp7 : 1; /* 61 CPU 0 Clock Forward Preset */N unsigned titan_dsc$v_p1p7 : 1; /* 62 P-Chip_1 Prese St */N unsigned titan_dsc$v_rsvd_7 : 1; /* 63 reserved */ } titan_dsc$r_bits; } TITAN_DSC; #if !defined(__VAXC);#define titan_dsc$il_l titan_dsc$r_longwords.titan_dsc$il_l;#define titan_dsc$il_h titan_dsc$r_longwords.titan_dsc$il_h6#define titan_dsc$v_bc titan_dsc$r_bits.titan_dsc$v_bc<#define titan_dsc$v_c0cfp titan_dsc$r_bits.titan_dsc$v_c0cfp<#define titan_dsc$v_c1cfp titan_dsc$r_bits.titan_dsc$v_c1cfp<#define titan_dsc$v_c2cfp ti Stan_dsc$r_bits.titan_dsc$v_c2cfp<#define titan_dsc$v_c3cfp titan_dsc$r_bits.titan_dsc$v_c3cfp8#define titan_dsc$v_p1p titan_dsc$r_bits.titan_dsc$v_p1p>#define titan_dsc$v_rsvd_0 titan_dsc$r_bits.titan_dsc$v_rsvd_08#define titan_dsc$v_bc1 titan_dsc$r_bits.titan_dsc$v_bc1>#define titan_dsc$v_c0cfp1 titan_dsc$r_bits.titan_dsc$v_c0cfp1>#define titan_dsc$v_c1cfp1 titan_dsc$r_bits.titan_dsc$v_c1cfp1>#define titan_dsc$v_c2cfp1 titan_dsc$r_bits.titan_dsc$v_c2cfp1>#define titan_dsc$v_c3cfp1 titan_dsc$r S_bits.titan_dsc$v_c3cfp1:#define titan_dsc$v_p1p1 titan_dsc$r_bits.titan_dsc$v_p1p1>#define titan_dsc$v_rsvd_1 titan_dsc$r_bits.titan_dsc$v_rsvd_18#define titan_dsc$v_bc2 titan_dsc$r_bits.titan_dsc$v_bc2>#define titan_dsc$v_c0cfp2 titan_dsc$r_bits.titan_dsc$v_c0cfp2>#define titan_dsc$v_c1cfp2 titan_dsc$r_bits.titan_dsc$v_c1cfp2>#define titan_dsc$v_c2cfp2 titan_dsc$r_bits.titan_dsc$v_c2cfp2>#define titan_dsc$v_c3cfp2 titan_dsc$r_bits.titan_dsc$v_c3cfp2:#define titan_dsc$v_p1p2 titan_dsc$r_bits. Stitan_dsc$v_p1p2>#define titan_dsc$v_rsvd_2 titan_dsc$r_bits.titan_dsc$v_rsvd_28#define titan_dsc$v_bc3 titan_dsc$r_bits.titan_dsc$v_bc3>#define titan_dsc$v_c0cfp3 titan_dsc$r_bits.titan_dsc$v_c0cfp3>#define titan_dsc$v_c1cfp3 titan_dsc$r_bits.titan_dsc$v_c1cfp3>#define titan_dsc$v_c2cfp3 titan_dsc$r_bits.titan_dsc$v_c2cfp3>#define titan_dsc$v_c3cfp3 titan_dsc$r_bits.titan_dsc$v_c3cfp3:#define titan_dsc$v_p1p3 titan_dsc$r_bits.titan_dsc$v_p1p3>#define titan_dsc$v_rsvd_3 titan_dsc$r_bits.titan_ Sdsc$v_rsvd_38#define titan_dsc$v_bc4 titan_dsc$r_bits.titan_dsc$v_bc4>#define titan_dsc$v_c0cfp4 titan_dsc$r_bits.titan_dsc$v_c0cfp4>#define titan_dsc$v_c1cfp4 titan_dsc$r_bits.titan_dsc$v_c1cfp4>#define titan_dsc$v_c2cfp4 titan_dsc$r_bits.titan_dsc$v_c2cfp4>#define titan_dsc$v_c3cfp4 titan_dsc$r_bits.titan_dsc$v_c3cfp4:#define titan_dsc$v_p1p4 titan_dsc$r_bits.titan_dsc$v_p1p4>#define titan_dsc$v_rsvd_4 titan_dsc$r_bits.titan_dsc$v_rsvd_4:#define titan_dsc$v_bc15 titan_dsc$r_bits.titan_dsc$v_ Tbc15>#define titan_dsc$v_c0cfp5 titan_dsc$r_bits.titan_dsc$v_c0cfp5>#define titan_dsc$v_c1cfp5 titan_dsc$r_bits.titan_dsc$v_c1cfp5>#define titan_dsc$v_c2cfp5 titan_dsc$r_bits.titan_dsc$v_c2cfp5>#define titan_dsc$v_c3cfp5 titan_dsc$r_bits.titan_dsc$v_c3cfp5:#define titan_dsc$v_p1p5 titan_dsc$r_bits.titan_dsc$v_p1p5>#define titan_dsc$v_rsvd_5 titan_dsc$r_bits.titan_dsc$v_rsvd_58#define titan_dsc$v_bc6 titan_dsc$r_bits.titan_dsc$v_bc6>#define titan_dsc$v_c0cfp6 titan_dsc$r_bits.titan_dsc$v_c0cfp6 T>#define titan_dsc$v_c1cfp6 titan_dsc$r_bits.titan_dsc$v_c1cfp6>#define titan_dsc$v_c2cfp6 titan_dsc$r_bits.titan_dsc$v_c2cfp6>#define titan_dsc$v_c3cfp6 titan_dsc$r_bits.titan_dsc$v_c3cfp6:#define titan_dsc$v_p1p6 titan_dsc$r_bits.titan_dsc$v_p1p6>#define titan_dsc$v_rsvd_6 titan_dsc$r_bits.titan_dsc$v_rsvd_68#define titan_dsc$v_bc7 titan_dsc$r_bits.titan_dsc$v_bc7>#define titan_dsc$v_c0cfp7 titan_dsc$r_bits.titan_dsc$v_c0cfp7>#define titan_dsc$v_c1cfp7 titan_dsc$r_bits.titan_dsc$v_c1cfp7>#d Tefine titan_dsc$v_c2cfp7 titan_dsc$r_bits.titan_dsc$v_c2cfp7>#define titan_dsc$v_c3cfp7 titan_dsc$r_bits.titan_dsc$v_c3cfp7:#define titan_dsc$v_p1p7 titan_dsc$r_bits.titan_dsc$v_p1p7>#define titan_dsc$v_rsvd_7 titan_dsc$r_bits.titan_dsc$v_rsvd_7"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan STR - D-Chip System Timing Register T */N/* */#define TITAN_STR$M_AW 0x1#define TITAN_STR$M_IDDR 0xE#define TITAN_STR$M_IDDW 0x30#define TITAN_STR$M_RSVD_0 0xC0#define TITAN_STR$M_AW1 0x100#define TITAN_STR$M_IDDR1 0xE00 #define TITAN_STR$M_IDDW1 0x3000!#define TITAN_STR$M_RSVD_1 0xC000#define TITAN_STR$M_AW2 0x10000!#define TITAN_STR$M_IDDR2 0xE0000"#define TITAN_STR$M_IDDW2 0x300000##define TITAN_STR$M_RSVD_2 0xC00000 T!#define TITAN_STR$M_AW3 0x1000000##define TITAN_STR$M_IDDR3 0xE000000$#define TITAN_STR$M_IDDW3 0x30000000%#define TITAN_STR$M_RSVD_3 0xC0000000##define TITAN_STR$M_AW4 0x100000000%#define TITAN_STR$M_IDDR4 0xE00000000&#define TITAN_STR$M_IDDW4 0x3000000000'#define TITAN_STR$M_RSVD_4 0xC000000000%#define TITAN_STR$M_AW5 0x10000000000'#define TITAN_STR$M_IDDR5 0xE0000000000(#define TITAN_STR$M_IDDW5 0x300000000000)#define TITAN_STR$M_RSVD_5 0xC00000000000'#define TITAN_STR$M_AW6 T0x1000000000000)#define TITAN_STR$M_IDDR6 0xE000000000000*#define TITAN_STR$M_IDDW6 0x30000000000000+#define TITAN_STR$M_RSVD_6 0xC0000000000000)#define TITAN_STR$M_AW7 0x100000000000000+#define TITAN_STR$M_IDDR7 0xE00000000000000,#define TITAN_STR$M_IDDW7 0x3000000000000000-#define TITAN_STR$M_RSVD_7 0xC000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nome Tmber_alignment#endiftypedef union _titan_str {#pragma __nomember_alignment' unsigned __int64 titan_str$iq_data; __struct {$ unsigned int titan_str$il_l;$ unsigned int titan_str$il_h; } titan_str$r_longwords; __struct {N unsigned titan_str$v_aw : 1; /* 0 Array Width */V unsigned titan_str$v_iddr : 3; /* 3:1 Issue to Data Delay for memory reads */j unsigned titan_str$v_iddw : 2; /* 5:4 Issue to Data Delay fTor xactions other than memory reads */N unsigned titan_str$v_rsvd_0 : 2; /* 7:6 reserved */N/* */N unsigned titan_str$v_aw1 : 1; /* 8 Array Width */W unsigned titan_str$v_iddr1 : 3; /* 11:9 Issue to Data Delay for memory reads */l unsigned titan_str$v_iddw1 : 2; /* 13:12 Issue to Data Delay for xactions other than memory reads */N unsigned titan_strT$v_rsvd_1 : 2; /* 15:14 reserved */N/* */N unsigned titan_str$v_aw2 : 1; /* 16 Array Width */X unsigned titan_str$v_iddr2 : 3; /* 19:17 Issue to Data Delay for memory reads */l unsigned titan_str$v_iddw2 : 2; /* 21:20 Issue to Data Delay for xactions other than memory reads */N unsigned titan_str$v_rsvd_2 : 2; /* 23:22 reserved */N/*  T */N unsigned titan_str$v_aw3 : 1; /* 24 Array Width */X unsigned titan_str$v_iddr3 : 3; /* 27:25 Issue to Data Delay for memory reads */l unsigned titan_str$v_iddw3 : 2; /* 29:28 Issue to Data Delay for xactions other than memory reads */N unsigned titan_str$v_rsvd_3 : 2; /* 31:30 reserved */N/* */ TN unsigned titan_str$v_aw4 : 1; /* 32 Array Width */X unsigned titan_str$v_iddr4 : 3; /* 35:33 Issue to Data Delay for memory reads */l unsigned titan_str$v_iddw4 : 2; /* 37:36 Issue to Data Delay for xactions other than memory reads */N unsigned titan_str$v_rsvd_4 : 2; /* 39:38 reserved */N/* */N unsigned titan_str$v_aw5 : 1; /* 40 Array Width  T */X unsigned titan_str$v_iddr5 : 3; /* 43:41 Issue to Data Delay for memory reads */l unsigned titan_str$v_iddw5 : 2; /* 45:44 Issue to Data Delay for xactions other than memory reads */N unsigned titan_str$v_rsvd_5 : 2; /* 47:46 reserved */N/* */N unsigned titan_str$v_aw6 : 1; /* 48 Array Width */X unsigned titan_str$v_iddr6 : 3; /* 51:49 I Tssue to Data Delay for memory reads */l unsigned titan_str$v_iddw6 : 2; /* 53:52 Issue to Data Delay for xactions other than memory reads */N unsigned titan_str$v_rsvd_6 : 2; /* 55:54 reserved */N/* */N unsigned titan_str$v_aw7 : 1; /* 56 Array Width */X unsigned titan_str$v_iddr7 : 3; /* 59:57 Issue to Data Delay for memory reads */l unsigned titan_str T$v_iddw7 : 2; /* 61:60 Issue to Data Delay for xactions other than memory reads */N unsigned titan_str$v_rsvd_7 : 2; /* 63:62 reserved */ } titan_str$r_bits; } TITAN_STR; #if !defined(__VAXC);#define titan_str$il_l titan_str$r_longwords.titan_str$il_l;#define titan_str$il_h titan_str$r_longwords.titan_str$il_h6#define titan_str$v_aw titan_str$r_bits.titan_str$v_aw:#define titan_str$v_iddr titan_str$r_bits.titan_str$v_iddr:#define titan_str$v_iddw tit Tan_str$r_bits.titan_str$v_iddw>#define titan_str$v_rsvd_0 titan_str$r_bits.titan_str$v_rsvd_08#define titan_str$v_aw1 titan_str$r_bits.titan_str$v_aw1<#define titan_str$v_iddr1 titan_str$r_bits.titan_str$v_iddr1<#define titan_str$v_iddw1 titan_str$r_bits.titan_str$v_iddw1>#define titan_str$v_rsvd_1 titan_str$r_bits.titan_str$v_rsvd_18#define titan_str$v_aw2 titan_str$r_bits.titan_str$v_aw2<#define titan_str$v_iddr2 titan_str$r_bits.titan_str$v_iddr2<#define titan_str$v_iddw2 titan_str$r_bits.t Titan_str$v_iddw2>#define titan_str$v_rsvd_2 titan_str$r_bits.titan_str$v_rsvd_28#define titan_str$v_aw3 titan_str$r_bits.titan_str$v_aw3<#define titan_str$v_iddr3 titan_str$r_bits.titan_str$v_iddr3<#define titan_str$v_iddw3 titan_str$r_bits.titan_str$v_iddw3>#define titan_str$v_rsvd_3 titan_str$r_bits.titan_str$v_rsvd_38#define titan_str$v_aw4 titan_str$r_bits.titan_str$v_aw4<#define titan_str$v_iddr4 titan_str$r_bits.titan_str$v_iddr4<#define titan_str$v_iddw4 titan_str$r_bits.titan_str$v_idd Tw4>#define titan_str$v_rsvd_4 titan_str$r_bits.titan_str$v_rsvd_48#define titan_str$v_aw5 titan_str$r_bits.titan_str$v_aw5<#define titan_str$v_iddr5 titan_str$r_bits.titan_str$v_iddr5<#define titan_str$v_iddw5 titan_str$r_bits.titan_str$v_iddw5>#define titan_str$v_rsvd_5 titan_str$r_bits.titan_str$v_rsvd_58#define titan_str$v_aw6 titan_str$r_bits.titan_str$v_aw6<#define titan_str$v_iddr6 titan_str$r_bits.titan_str$v_iddr6<#define titan_str$v_iddw6 titan_str$r_bits.titan_str$v_iddw6>#define ti Ttan_str$v_rsvd_6 titan_str$r_bits.titan_str$v_rsvd_68#define titan_str$v_aw7 titan_str$r_bits.titan_str$v_aw7<#define titan_str$v_iddr7 titan_str$r_bits.titan_str$v_iddr7<#define titan_str$v_iddw7 titan_str$r_bits.titan_str$v_iddw7>#define titan_str$v_rsvd_7 titan_str$r_bits.titan_str$v_rsvd_7"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Tit Tan DREV - D-Chip System Configuration Register */N/* */#define TITAN_DREV$M_REV0 0xF #define TITAN_DREV$M_RSVD_0 0xF0#define TITAN_DREV$M_REV1 0xF00"#define TITAN_DREV$M_RSVD_1 0xF000!#define TITAN_DREV$M_REV2 0xF0000$#define TITAN_DREV$M_RSVD_2 0xF00000##define TITAN_DREV$M_REV3 0xF000000&#define TITAN_DREV$M_RSVD_3 0xF0000000%#define TITAN_DREV$M_REV4 0xF00000000(#define TITAN_DREV$M_RSVTD_4 0xF000000000'#define TITAN_DREV$M_REV5 0xF0000000000*#define TITAN_DREV$M_RSVD_5 0xF00000000000)#define TITAN_DREV$M_REV6 0xF000000000000,#define TITAN_DREV$M_RSVD_6 0xF0000000000000+#define TITAN_DREV$M_REV7 0xF00000000000000.#define TITAN_DREV$M_RSVD_7 0xF000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_dre Tv {#pragma __nomember_alignment( unsigned __int64 titan_drev$iq_data; __struct {% unsigned int titan_drev$il_l;% unsigned int titan_drev$il_h;! } titan_drev$r_longwords; __struct {N unsigned titan_drev$v_rev0 : 4; /* 3:0 D-Chip 0 Revision */N unsigned titan_drev$v_rsvd_0 : 4; /* 7:4 CPU 0 Clk Fwd Preset */N/* */N unsigned titan_drev$v_rev1 :T 4; /* 11:8 D-Chip 1 Revision */N unsigned titan_drev$v_rsvd_1 : 4; /* 15:12 CPU 1 Clk Fwd Preset */N/* */N unsigned titan_drev$v_rev2 : 4; /* 19:16 D-Chip 2 Revision */N unsigned titan_drev$v_rsvd_2 : 4; /* 23:20 CPU 2 Clk Fwd Preset */N/* */N unsigned titan_drev$v_rev3 : 4; /* 27:24 D-Chip 3 ReviTsion */N unsigned titan_drev$v_rsvd_3 : 4; /* 31:28 CPU 3 Clk Fwd Preset */N/* */N unsigned titan_drev$v_rev4 : 4; /* 35:32 D-Chip 4 Revision */N unsigned titan_drev$v_rsvd_4 : 4; /* 39:36 CPU 4 Clk Fwd Preset */N/* */N unsigned titan_drev$v_rev5 : 4; /* 43:40 D-Chip 5 Revision */N Tunsigned titan_drev$v_rsvd_5 : 4; /* 47:44 CPU 5 Clk Fwd Preset */N/* */N unsigned titan_drev$v_rev6 : 4; /* 51:48 D-Chip 6 Revision */N unsigned titan_drev$v_rsvd_6 : 4; /* 55:52 CPU 6 Clk Fwd Preset */N/* */N unsigned titan_drev$v_rev7 : 4; /* 59:56 D-Chip 7 Revision */N unsigned titan_drev$v_rsvd T_7 : 4; /* 63:60 CPU 7 Clk Fwd Preset */ } titan_drev$r_bits; } TITAN_DREV; #if !defined(__VAXC)>#define titan_drev$il_l titan_drev$r_longwords.titan_drev$il_l>#define titan_drev$il_h titan_drev$r_longwords.titan_drev$il_h=#define titan_drev$v_rev0 titan_drev$r_bits.titan_drev$v_rev0A#define titan_drev$v_rsvd_0 titan_drev$r_bits.titan_drev$v_rsvd_0=#define titan_drev$v_rev1 titan_drev$r_bits.titan_drev$v_rev1A#define titan_drev$v_rsvd_1 titan_drev$r_bits.titan_drev$v_r Tsvd_1=#define titan_drev$v_rev2 titan_drev$r_bits.titan_drev$v_rev2A#define titan_drev$v_rsvd_2 titan_drev$r_bits.titan_drev$v_rsvd_2=#define titan_drev$v_rev3 titan_drev$r_bits.titan_drev$v_rev3A#define titan_drev$v_rsvd_3 titan_drev$r_bits.titan_drev$v_rsvd_3=#define titan_drev$v_rev4 titan_drev$r_bits.titan_drev$v_rev4A#define titan_drev$v_rsvd_4 titan_drev$r_bits.titan_drev$v_rsvd_4=#define titan_drev$v_rev5 titan_drev$r_bits.titan_drev$v_rev5A#define titan_drev$v_rsvd_5 titan_drev T$r_bits.titan_drev$v_rsvd_5=#define titan_drev$v_rev6 titan_drev$r_bits.titan_drev$v_rev6A#define titan_drev$v_rsvd_6 titan_drev$r_bits.titan_drev$v_rsvd_6=#define titan_drev$v_rev7 titan_drev$r_bits.titan_drev$v_rev7A#define titan_drev$v_rsvd_7 titan_drev$r_bits.titan_drev$v_rsvd_7"#endif /* #if !defined(__VAXC) */ O/*========================================================================== */N/* */N/* P-Chip TRegisters */N/* */O/*========================================================================== */N/* */N/* */N/* Titan WSBA - P-Chip Window Space Base Address Registers */N/* T */#define TITAN_WSBA$M_ENA 0x1#define TITAN_WSBA$M_SG 0x2##define TITAN_WSBA$M_RSVD_0 0xFFFFC$#define TITAN_WSBA$M_ADDR 0xFFF00000.#define TITAN_WSBA$M_RSVD_1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_wsba {#pragma __nomember_alignment( unsigned __int64 t Titan_wsba$iq_data; __struct {% unsigned int titan_wsba$il_l;% unsigned int titan_wsba$il_h;! } titan_wsba$r_longwords; __struct {N unsigned titan_wsba$v_ena : 1; /* 0 Enable */N unsigned titan_wsba$v_sg : 1; /* 1 Scatter/Gather */N unsigned titan_wsba$v_rsvd_0 : 18; /* 19:2 reserved */N unsigned titan_wsba$v_addr : 12; /* 31:20 Base Address */N unsign Ted titan_wsba$v_rsvd_1 : 32; /* 63:32 Reserved */ } titan_wsba$r_bits; } TITAN_WSBA; #if !defined(__VAXC)>#define titan_wsba$il_l titan_wsba$r_longwords.titan_wsba$il_l>#define titan_wsba$il_h titan_wsba$r_longwords.titan_wsba$il_h;#define titan_wsba$v_ena titan_wsba$r_bits.titan_wsba$v_ena9#define titan_wsba$v_sg titan_wsba$r_bits.titan_wsba$v_sgA#define titan_wsba$v_rsvd_0 titan_wsba$r_bits.titan_wsba$v_rsvd_0=#define titan_wsba$v_addr titan_wsba$r_bits.ti Ttan_wsba$v_addrA#define titan_wsba$v_rsvd_1 titan_wsba$r_bits.titan_wsba$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan WSM - P-Chip Window Space Mask Registers */N/* */"#define TITAN_WSM$M_RSVD_0 0xFFFFF!#define TITAN_WSM$M_AM 0 TxFFF00000-#define TITAN_WSM$M_RSVD_1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_wsm {#pragma __nomember_alignment' unsigned __int64 titan_wsm$iq_data; __struct {$ unsigned int titan_wsm$il_l;$ unsigned int titan_wsm$il_h; } titan_wsm$r_longwords; __struct {N !T unsigned titan_wsm$v_rsvd_0 : 20; /* 19:0 reserved */N unsigned titan_wsm$v_am : 12; /* 31:20 Base Address */N unsigned titan_wsm$v_rsvd_1 : 32; /* 63:32 Reserved */ } titan_wsm$r_bits; } TITAN_WSM; #if !defined(__VAXC);#define titan_wsm$il_l titan_wsm$r_longwords.titan_wsm$il_l;#define titan_wsm$il_h titan_wsm$r_longwords.titan_wsm$il_h>#define titan_wsm$v_rsvd_0 titan_wsm$r_bits.titan_wsm$v_rsvd_06#define ti "Ttan_wsm$v_am titan_wsm$r_bits.titan_wsm$v_am>#define titan_wsm$v_rsvd_1 titan_wsm$r_bits.titan_wsm$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan TBA - P-Chip Translated Base Address Registers */N/* */ #define TITAN_TBA$M_RSVD_0 0x3FF$#d#Tefine TITAN_TBA$M_ADDR 0x7FFFFFC00-#define TITAN_TBA$M_RSVD_1 0xFFFFFFF800000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_tba {#pragma __nomember_alignment' unsigned __int64 titan_tba$iq_data; __struct {$ unsigned int titan_tba$il_l;$ unsigned int titan_tba$il_h; } titan_tba$r_longwords; $T __struct {N unsigned titan_tba$v_rsvd_0 : 10; /* 9:0 reserved */N unsigned titan_tba$v_addr : 25; /* 34:10 Translated Base Address */N unsigned titan_tba$v_rsvd_1 : 29; /* 63:35 reserved */ } titan_tba$r_bits; } TITAN_TBA; #if !defined(__VAXC);#define titan_tba$il_l titan_tba$r_longwords.titan_tba$il_l;#define titan_tba$il_h titan_tba$r_longwords.titan_tba$il_h>#define titan_tba$v_rsvd_0 titan_tba$r_bits.titan_ %Ttba$v_rsvd_0:#define titan_tba$v_addr titan_tba$r_bits.titan_tba$v_addr>#define titan_tba$v_rsvd_1 titan_tba$r_bits.titan_tba$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan PCTL - P-Chip Gport Control Register */N/* */#define &TTITAN_PCTL$M_FBTB 0x1#define TITAN_PCTL$M_THDIS 0x2!#define TITAN_PCTL$M_CHAINDIS 0x4 #define TITAN_PCTL$M_TGTLAT 0x18#define TITAN_PCTL$M_HOLE 0x20#define TITAN_PCTL$M_MWIN 0x40 #define TITAN_PCTL$M_ARBENA 0x80"#define TITAN_PCTL$M_PRIGRP 0xFF00!#define TITAN_PCTL$M_PPRI 0x10000%#define TITAN_PCTL$M_PCISPD66 0x20000%#define TITAN_PCTL$M_CNGSTLT 0x3C0000)#define TITAN_PCTL$M_PTPDESTEN 0x3FC00000%#define TITAN_PCTL$M_DPCEN 0x40000000%#define TITAN_PCTL$M_APCEN 0x80000000&#defin 'Te TITAN_PCTL$M_DCRTV 0x300000000,#define TITAN_PCTL$M_EN_STEPPING 0x400000000.#define TITAN_PCTL$M_AGP_RATE 0x300000000000004#define TITAN_PCTL$M_AGP_SBA_ENABLE 0x400000000000000#define TITAN_PCTL$M_AGP_ENABLE 0x800000000000002#define TITAN_PCTL$M_AGP_PRESENT 0x2000000000000001#define TITAN_PCTL$M_AGP_HP_RD 0x1C000000000000001#define TITAN_PCTL$M_AGP_LP_RD 0xE000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __no(Tmember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_pctl {#pragma __nomember_alignment( unsigned __int64 titan_pctl$iq_data; __struct {% unsigned int titan_pctl$il_l;% unsigned int titan_pctl$il_h;! } titan_pctl$r_longwords; __struct {N unsigned titan_pctl$v_fbtb : 1; /* 0 Fast Back-To-Back enable */V unsigned titan_pctl$v_thdis : 1; /* 1 Disable anti-Thrash mechanism for TLB */N )Tunsigned titan_pctl$v_chaindis : 1; /* 2 Disable Chaining */W unsigned titan_pctl$v_tgtlat : 2; /* 4:3 Target Latency Timers timers enable */N unsigned titan_pctl$v_hole : 1; /* 5 512K to 1M window Hole enable */N unsigned titan_pctl$v_mwin : 1; /* 6 Monster Window enable */N unsigned titan_pctl$v_arbena : 1; /* 7 internal Arbiter Enable */N unsigned titan_pctl$v_prigrp : 8; /* 15:8 arbiter Priority Group */\ unsigned titan_p*Tctl$v_ppri : 1; /* 16 arbiter Priority Group for the Pchip itself */] unsigned titan_pctl$v_pcispd66 : 1; /* 17 A '1' indicates GPCI frequency is 66 MHz */N unsigned titan_pctl$v_cngstlt : 4; /* 21:18 GPCI congestion limit */` unsigned titan_pctl$v_ptpdesten : 8; /* 29:22 Bit mask enables legal PTP transactions */f unsigned titan_pctl$v_dpcen : 1; /* 30 set to '1' enables checking parity on PCI data xfers */r unsigned titan_pctl$v_apcen : 1; /* 31 set to '1' +Tenables checking parity during address command cycles */N/* */d unsigned titan_pctl$v_dcrtv : 2; /* 33:32 contols value of delayed completion retry timer */p unsigned titan_pctl$v_en_stepping : 1; /* 34 enables address stepping on the PCI during config cycles */N unsigned titan_pctl$v_rsvd_1 : 17; /* 51:35 Reserved */N unsigned titan_pctl$v_agp_rate : 2; /* AGP RATE 1X, 2X, 4X ,T */N unsigned titan_pctl$v_agp_sba_enable : 1; /* AGP SBA ENABLE */N unsigned titan_pctl$v_agp_enable : 1; /* AGP ENABLE */N unsigned titan_pctl$v_rsvd_2 : 1; /* RESERVED FIELD */N unsigned titan_pctl$v_agp_present : 1; /* AGP PRESENT */N unsigned titan_pctl$v_agp_hp_rd : 3; /* AGP HIGH PRIORITY READ DE */N unsigned titan_pctl$v_agp_lp_rd : 3; /* AGP LOW PRIORITY READ DEP */ } titan_pc -Ttl$r_bits; } TITAN_PCTL; #if !defined(__VAXC)>#define titan_pctl$il_l titan_pctl$r_longwords.titan_pctl$il_l>#define titan_pctl$il_h titan_pctl$r_longwords.titan_pctl$il_h=#define titan_pctl$v_fbtb titan_pctl$r_bits.titan_pctl$v_fbtb?#define titan_pctl$v_thdis titan_pctl$r_bits.titan_pctl$v_thdisE#define titan_pctl$v_chaindis titan_pctl$r_bits.titan_pctl$v_chaindisA#define titan_pctl$v_tgtlat titan_pctl$r_bits.titan_pctl$v_tgtlat=#define titan_pctl$v_hole titan_pctl$r_bits.titan_ .Tpctl$v_hole=#define titan_pctl$v_mwin titan_pctl$r_bits.titan_pctl$v_mwinA#define titan_pctl$v_arbena titan_pctl$r_bits.titan_pctl$v_arbenaA#define titan_pctl$v_prigrp titan_pctl$r_bits.titan_pctl$v_prigrp=#define titan_pctl$v_ppri titan_pctl$r_bits.titan_pctl$v_ppriE#define titan_pctl$v_pcispd66 titan_pctl$r_bits.titan_pctl$v_pcispd66C#define titan_pctl$v_cngstlt titan_pctl$r_bits.titan_pctl$v_cngstltG#define titan_pctl$v_ptpdesten titan_pctl$r_bits.titan_pctl$v_ptpdesten?#define tita/Tn_pctl$v_dpcen titan_pctl$r_bits.titan_pctl$v_dpcen?#define titan_pctl$v_apcen titan_pctl$r_bits.titan_pctl$v_apcen?#define titan_pctl$v_dcrtv titan_pctl$r_bits.titan_pctl$v_dcrtvK#define titan_pctl$v_en_stepping titan_pctl$r_bits.titan_pctl$v_en_steppingA#define titan_pctl$v_rsvd_1 titan_pctl$r_bits.titan_pctl$v_rsvd_1E#define titan_pctl$v_agp_rate titan_pctl$r_bits.titan_pctl$v_agp_rateQ#define titan_pctl$v_agp_sba_enable titan_pctl$r_bits.titan_pctl$v_agp_sba_enableI#define titan_pctl 0T$v_agp_enable titan_pctl$r_bits.titan_pctl$v_agp_enableA#define titan_pctl$v_rsvd_2 titan_pctl$r_bits.titan_pctl$v_rsvd_2K#define titan_pctl$v_agp_present titan_pctl$r_bits.titan_pctl$v_agp_presentG#define titan_pctl$v_agp_hp_rd titan_pctl$r_bits.titan_pctl$v_agp_hp_rdG#define titan_pctl$v_agp_lp_rd titan_pctl$r_bits.titan_pctl$v_agp_lp_rd"#endif /* #if !defined(__VAXC) */ N/* */N/* 1T */N/* Titan PLAT - P-Chip Master Latency Register */N/* */ #define TITAN_PLAT$M_RSVD_0 0xFF#define TITAN_PLAT$M_LAT 0xFF00&#define TITAN_PLAT$M_RSVD_1 0xFFFF0000.#define TITAN_PLAT$M_RSVD_2 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadwor2Td#else#pragma __nomember_alignment#endiftypedef union _titan_plat {#pragma __nomember_alignment( unsigned __int64 titan_plat$iq_data; __struct {% unsigned int titan_plat$il_l;% unsigned int titan_plat$il_h;! } titan_plat$r_longwords; __struct {N unsigned titan_plat$v_rsvd_0 : 8; /* 7:0 reserved */N unsigned titan_plat$v_lat : 8; /* 15:8 Master Latency Timer */N unsigned titan_plat$v_rsvd_1 : 16; 3T /* 31:16 reserved */N unsigned titan_plat$v_rsvd_2 : 32; /* 63:32 reserved */ } titan_plat$r_bits; } TITAN_PLAT; #if !defined(__VAXC)>#define titan_plat$il_l titan_plat$r_longwords.titan_plat$il_l>#define titan_plat$il_h titan_plat$r_longwords.titan_plat$il_hA#define titan_plat$v_rsvd_0 titan_plat$r_bits.titan_plat$v_rsvd_0;#define titan_plat$v_lat titan_plat$r_bits.titan_plat$v_latA#define titan_plat$v_rsvd_1 titan_plat$r_bits.titan_pl 4Tat$v_rsvd_1A#define titan_plat$v_rsvd_2 titan_plat$r_bits.titan_plat$v_rsvd_2"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan PERROR - P-Chip Error Register */N/* */#define TITAN_PERROR$M_LOST 0x1#define TITAN_PERROR$M_SERR 0x5T2#define TITAN_PERROR$M_PERR 0x4 #define TITAN_PERROR$M_DCRTO 0x8#define TITAN_PERROR$M_SGE 0x10#define TITAN_PERROR$M_APE 0x20#define TITAN_PERROR$M_TA 0x40#define TITAN_PERROR$M_DPE 0x80 #define TITAN_PERROR$M_NDS 0x100"#define TITAN_PERROR$M_IPTPR 0x200"#define TITAN_PERROR$M_IPTPW 0x400$#define TITAN_PERROR$M_RSVD_0 0x3800*#define TITAN_PERROR$M_ADDR 0x3FFFFFFFC000)#define TITAN_PERROR$M_DAC 0x400000000000*#define TITAN_PERROR$M_MWIN 0x800000000000-#define TITAN_PERROR$M_R6TSVD_1 0x7000000000000+#define TITAN_PERROR$M_CMD 0x780000000000000#define TITAN_PERROR$M_RSVD_2 0x7F80000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_perror {#pragma __nomember_alignment* unsigned __int64 titan_perror$iq_data; __struct {' unsigned int titan_perror$il_l;' unsigned int titan 7T_perror$il_h;# } titan_perror$r_longwords; __struct {N unsigned titan_perror$v_lost : 1; /* 0 Lost an error */N unsigned titan_perror$v_serr : 1; /* 1 SERR# sampled asserted */V unsigned titan_perror$v_perr : 1; /* 2 PERR# sampled asserted as PCI master */a unsigned titan_perror$v_dcrto : 1; /* 3 delayed completion retry timeout as PCI target */O unsigned titan_perror$v_sge : 1; /* 4 Scatter/Gather had invalid PTE */f 8T unsigned titan_perror$v_ape : 1; /* 5 Address Parity Error detected as potential PCI target */N unsigned titan_perror$v_ta : 1; /* 6 Targed Abort as PCI master */Y unsigned titan_perror$v_dpe : 1; /* 7 PCI Read Data Parity Error as PCI master */N unsigned titan_perror$v_nds : 1; /* 8 No DevSel as PCI master */N unsigned titan_perror$v_iptpr : 1; /* 9 Invalid Peer-to-peer write */N unsigned titan_perror$v_iptpw : 1; /* 10 Invalid Peep-to-peer read9T */N unsigned titan_perror$v_rsvd_0 : 3; /* 13:11 reserved */S unsigned titan_perror$v_addr : 32; /* 46:14 contain longword PCI address */N unsigned titan_perror$v_dac : 1; /* 47 Erroneous DAC */U unsigned titan_perror$v_mwin : 1; /* 48 Erroneous access to Monster Window */N unsigned titan_perror$v_rsvd_1 : 3; /* 51:49 Rreserved */N unsigned titan_perror$v_cmd : 4; /* 55:52 PCI Command on error */N :T unsigned titan_perror$v_rsvd_2 : 8; /* 63:56 Reserved */, unsigned titan_perror$v_fill_1_ : 1; } titan_perror$r_bits; } TITAN_PERROR; #if !defined(__VAXC)D#define titan_perror$il_l titan_perror$r_longwords.titan_perror$il_lD#define titan_perror$il_h titan_perror$r_longwords.titan_perror$il_hC#define titan_perror$v_lost titan_perror$r_bits.titan_perror$v_lostC#define titan_perror$v_serr titan_perror$r_bits.titan_perror$v_serrC#define titan_perror$v_per;Tr titan_perror$r_bits.titan_perror$v_perrE#define titan_perror$v_dcrto titan_perror$r_bits.titan_perror$v_dcrtoA#define titan_perror$v_sge titan_perror$r_bits.titan_perror$v_sgeA#define titan_perror$v_ape titan_perror$r_bits.titan_perror$v_ape?#define titan_perror$v_ta titan_perror$r_bits.titan_perror$v_taA#define titan_perror$v_dpe titan_perror$r_bits.titan_perror$v_dpeA#define titan_perror$v_nds titan_perror$r_bits.titan_perror$v_ndsE#define titan_perror$v_iptpr titan_perror$r_bits.titTR 0x2#define TITAN_PERREN$M_PERR 0x4 #define TITAN_PERREN$M_DCRTO 0x8#define TITAN_PERREN$M_SGE 0x10#define TITAN_PERREN$M_APE 0x20#define TITAN_PERREN$M_TA 0x40#define TITAN_PERREN$M_DPE 0x80 #define TITAN_PERREN$M_NDS 0x100"#define TITAN_PERREN$M_IPTPR 0x200"#define TITAN_PERREN$M_IPTPW 0x400(#define TITAN_PERREN$M_RSVD_1 0xFFFFF8000#define TITAN_PERREN$M_RSVD_2 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C?T++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_perren {#pragma __nomember_alignment* unsigned __int64 titan_perren$iq_data; __struct {' unsigned int titan_perren$il_l;' unsigned int titan_perren$il_h;# } titan_perren$r_longwords; __struct {N unsigned titan_perren$v_rsvd_o : 1; /* 0 Reserved */N unsigned titan_perren$v_serr : 1; /* 1 Enable logging of S@TERR */N unsigned titan_perren$v_perr : 1; /* 2 Enable logging of PERR */N unsigned titan_perren$v_dcrto : 1; /* 3 Enable logging of DCRTO */O unsigned titan_perren$v_sge : 1; /* 4 Scatter/Gather had invalid PTE */Y unsigned titan_perren$v_ape : 1; /* 5 Enable detection of Address Parity Error */O unsigned titan_perren$v_ta : 1; /* 6 Enable logging of Targed Abort */] unsigned titan_perren$v_dpe : 1; /* 7 Enable detection of parity errATors on the PCI */] unsigned titan_perren$v_nds : 1; /* 8 Enable logging of "No DevSel as PCI master"' */Z unsigned titan_perren$v_iptpr : 1; /* 9 Enable logging of IPTPR if this bit set */[ unsigned titan_perren$v_iptpw : 1; /* 10 Enable logging of IPTPW if this bit set */N unsigned titan_perren$v_rsvd_1 : 21; /* 31:11 reserved */N unsigned titan_perren$v_rsvd_2 : 32; /* 63:32 Reserved */ } titan_perren$r_bits; } TITAN_ BTPERREN; #if !defined(__VAXC)D#define titan_perren$il_l titan_perren$r_longwords.titan_perren$il_lD#define titan_perren$il_h titan_perren$r_longwords.titan_perren$il_hG#define titan_perren$v_rsvd_o titan_perren$r_bits.titan_perren$v_rsvd_oC#define titan_perren$v_serr titan_perren$r_bits.titan_perren$v_serrC#define titan_perren$v_perr titan_perren$r_bits.titan_perren$v_perrE#define titan_perren$v_dcrto titan_perren$r_bits.titan_perren$v_dcrtoA#define titan_perren$v_sge titan_perren$r_biCTts.titan_perren$v_sgeA#define titan_perren$v_ape titan_perren$r_bits.titan_perren$v_ape?#define titan_perren$v_ta titan_perren$r_bits.titan_perren$v_taA#define titan_perren$v_dpe titan_perren$r_bits.titan_perren$v_dpeA#define titan_perren$v_nds titan_perren$r_bits.titan_perren$v_ndsE#define titan_perren$v_iptpr titan_perren$r_bits.titan_perren$v_iptprE#define titan_perren$v_iptpw titan_perren$r_bits.titan_perren$v_iptpwG#define titan_perren$v_rsvd_1 titan_perren$r_bits.titan_perren$v_rsv DTd_1G#define titan_perren$v_rsvd_2 titan_perren$r_bits.titan_perren$v_rsvd_2"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* Titan TLBIV - P-Chip Translation Buffer Invalidate Virtual Register */N/* */ #define TITAN_TLBIV$M_RSVD_0 0xF"#define TITAN_TLBIV$M_ADDR 0xFFFETF0'#define TITAN_TLBIV$M_RSVD_1 0xFFF00000/#define TITAN_TLBIV$M_RSVD_2 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_tlbiv {#pragma __nomember_alignment) unsigned __int64 titan_tlbiv$iq_data; __struct {& unsigned int titan_tlbiv$il_l;& unsigned int titan_tlbiv$il_h;" } tita FTn_tlbiv$r_longwords; __struct {N unsigned titan_tlbiv$v_rsvd_0 : 4; /* 3:0 reserved */Z unsigned titan_tlbiv$v_addr : 16; /* 19:4 invalidate if matches PCI addr<31:16> */N unsigned titan_tlbiv$v_rsvd_1 : 12; /* 31:20 reserved */N unsigned titan_tlbiv$v_rsvd_2 : 32; /* 63:32 reserved */ } titan_tlbiv$r_bits; } TITAN_TLBIV; #if !defined(__VAXC)A#define titan_tlbiv$il_l titan_tlbiv$r_longwords.titan_t GTlbiv$il_lA#define titan_tlbiv$il_h titan_tlbiv$r_longwords.titan_tlbiv$il_hD#define titan_tlbiv$v_rsvd_0 titan_tlbiv$r_bits.titan_tlbiv$v_rsvd_0@#define titan_tlbiv$v_addr titan_tlbiv$r_bits.titan_tlbiv$v_addrD#define titan_tlbiv$v_rsvd_1 titan_tlbiv$r_bits.titan_tlbiv$v_rsvd_1D#define titan_tlbiv$v_rsvd_2 titan_tlbiv$r_bits.titan_tlbiv$v_rsvd_2"#endif /* #if !defined(__VAXC) */ N/* */N/* HT */N/* Titan TLBIA - P-Chip Translation Buffer Invalidate all Register */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _titan_tlbia {#pragma __nomember_alignment) unsigned __int64 titan_tlbia$iq_data;IT __struct {& unsigned int titan_tlbia$il_l;& unsigned int titan_tlbia$il_h;" } titan_tlbia$r_longwords; } TITAN_TLBIA; #if !defined(__VAXC)A#define titan_tlbia$il_l titan_tlbia$r_longwords.titan_tlbia$il_lA#define titan_tlbia$il_h titan_tlbia$r_longwords.titan_tlbia$il_h"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_poiJTnter_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TITANDEF_LOADED */ wwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, KTand is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** auLTthorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************************************************** MT*****************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */F/* Source: 15-AUG-2002 16:10:05 $1$DGA8345:[LIB_H.SRC]TLBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TLBDEF ***/#ifndef __TLBDEF_LOADED#define __TLBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignNTmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)OT#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* Definitions for the first TLB insertion register and VHPT short format */N/* */#define TLB$M_P 0x1#define TLB$M_MBZ0 0x2#definPTe TLB$M_MA 0x1C#define TLB$M_A 0x20#define TLB$M_D 0x40#define TLB$M_PL 0x180#define TLB$M_AR 0xE00!#define TLB$M_PPN 0x3FFFFFFFFF000"#define TLB$M_MBZ1 0xC000000000000!#define TLB$M_ED 0x10000000000000%#define TLB$M_IGN0 0xFFE0000000000000#define TLB$M_ATTR 0x7F#define TLB$M_PROT 0xF80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifty QTpedef struct _tlb {#pragma __nomember_alignment __union {* unsigned __int64 tlb$q_vhpt_short;$ unsigned __int64 tlb$q_pte0; __struct {N unsigned tlb$v_p : 1; /* Present bit */N unsigned tlb$v_mbz0 : 1; /* Reserved TLB{1:1} (MBZ) */N unsigned tlb$v_ma : 3; /* Memory Attribute */N unsigned tlb$v_a : 1; /* Accessed bit */N un RTsigned tlb$v_d : 1; /* Dirty bit */N unsigned tlb$v_pl : 2; /* Privilege level */N unsigned tlb$v_ar : 3; /* Access Rights */#if defined(__VAXC)& unsigned tlb$v_ppn_1 : 32;% unsigned tlb$v_ppn_2 : 6;#elseN unsigned __int64 tlb$v_ppn : 38; /* Physical page number */#endifN unsigned tlb$v_mbz1 : 2; /* Reserved bits TLB{51:50} */N ST unsigned tlb$v_ed : 1; /* Exception deferral */N unsigned tlb$v_ign0 : 11; /* Ignored bits TLB{63:53} (MBZ) */ } tlb$r_tlbdef_bits; __struct {N unsigned tlb$v_attr : 7; /* Attribute bits */N unsigned tlb$v_prot : 5; /* Protection bits */' unsigned tlb$v_fill_0_ : 4; } tlb$r_prot_struct; } tlb$r_tlb_union; } TLB; #if !defined TT(__VAXC)9#define tlb$q_vhpt_short tlb$r_tlb_union.tlb$q_vhpt_short-#define tlb$q_pte0 tlb$r_tlb_union.tlb$q_pte09#define tlb$v_p tlb$r_tlb_union.tlb$r_tlbdef_bits.tlb$v_p?#define tlb$v_mbz0 tlb$r_tlb_union.tlb$r_tlbdef_bits.tlb$v_mbz0;#define tlb$v_ma tlb$r_tlb_union.tlb$r_tlbdef_bits.tlb$v_ma9#define tlb$v_a tlb$r_tlb_union.tlb$r_tlbdef_bits.tlb$v_a9#define tlb$v_d tlb$r_tlb_union.tlb$r_tlbdef_bits.tlb$v_d;#define tlb$v_pl tlb$r_tlb_union.tlb$r_tlbdef_bits.tlb$v_pl;#define tlb$v_ar t UTlb$r_tlb_union.tlb$r_tlbdef_bits.tlb$v_ar=#define tlb$v_ppn tlb$r_tlb_union.tlb$r_tlbdef_bits.tlb$v_ppn?#define tlb$v_mbz1 tlb$r_tlb_union.tlb$r_tlbdef_bits.tlb$v_mbz1;#define tlb$v_ed tlb$r_tlb_union.tlb$r_tlbdef_bits.tlb$v_ed?#define tlb$v_attr tlb$r_tlb_union.tlb$r_prot_struct.tlb$v_attr?#define tlb$v_prot tlb$r_tlb_union.tlb$r_prot_struct.tlb$v_prot"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointe VTr size */E#pragma __required_pointer_size __long /* Pointers are 64-bit */Dtypedef struct _tlb * TLB_PQ; /* Pointer to a TLB structure. */Qtypedef struct _tlb ** TLB_PPQ; /* Pointer to a pointer to a TLB structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 TLB_PQ;!typedef unsigned __int64 TLB_PPQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTERWT_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TLBDEF_LOADED */ wwp@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietXTary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** prYToprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************* ZT*************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */F/* Source: 16-JUL-1993 13:15:55 $1$DGA8345:[LIB_H.SRC]TLVDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TLVDEF ***/#ifndef __TLVDEF_LOADED#define __TLVDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Sta[Tndard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#d\Tefine __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif Q/* Define the layout of a general purpose type-length-value structure which is */N/* used to pass a variety of data structures around the cluster. */"#define TLV$K_MAX_ORB_LENGTH 13312N#define TLV$]TK_MAX_ARB_LENGTH 8448 /* 8360 rounded up to %x2100 */N#define TLV$K_MAX_IDENTIFIERS 1024 /* maximum number of rights IDs */N#define TLV$S_CHECKSUM 8 /* header minus checksum */N#define TLV$K_MSG_HDR_LENGTH 24 /* message header length */N#define TLV$K_VERSION_1 1 /* version number 1 */N#define TLV$K_VERSION_2 2 /* version number 2 (Blade) */N#define TLV$K_CURRENT_VERSION 2 ^T /* current protocol */N#define TLV$K_GRANULARITY 7 /* allocation granularity */ typedef struct _tlv$r_header {N unsigned int tlv$l_checksum; /* checksum (includes header) */N unsigned int tlv$l_unused_l1; /* start of checksum */N unsigned int tlv$l_msg_size; /* message size */N unsigned short int tlv$w_msg_count; /* # of packets in message */N unsigned char tlv$b_vers _Tion; /* TLV protocol version number */N unsigned char tlv$b_unused_b1; /* reserved for future use */N unsigned __int64 tlv$q_security_domain; /* security domain ($KGBDEF) */ } TLV$R_HEADER;N#define TLV$K_PKT_HDR_LENGTH 4 /* packet header length */ typedef struct _tlv$r_packet {N unsigned short int tlv$w_type; /* packet type */U unsigned short int tlv$w_length; /* packet length (including packet h`Teader) */N unsigned int tlv$r_value; /* offset to start of data */ } TLV$R_PACKET; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TLVDEF_LOADED */ ww*[UM/***************************************aT************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP bT **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** cT **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:30 by OpenVMS SDL V3.7 */F/* Source: 17-FEB-2000 16:35:45 $1$DGA8345:[LIB_H.SRC]TMCDEF.SDL;1 *//***************************************************************************************** dT***************************************//*** MODULE $TMCDEF ***/#ifndef __TMCDEF_LOADED#define __TMCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size eTdefault to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif G#define TMC$K_SYNCH 0 fT /* $SYNCH honor TM_ACTIVE */[#define TMC$K_SETEF 1 /* Set event flag ignore TM_ACTIVE */T#define TMC$K_WFL 2 /* $WFLAND and $WFLOR honor TM_ACTIVE */Q#define TMC$K_SET_CTX 3 /* Set synch context ignore TM_ACTIVE */T#define TMC$K_HIBER 4 /* $HIBER honor TM_ACTIVE */[#define TMC$K_WAKE 5 /* $WAKE ignore TM_ACTIVE */T#define TMC$K_PFW 6 gT /* Pagefault wait honor TM_ACTIVE */[#define TMC$K_PFC 7 /* Pagefault complete ignore TM_ACTIVE */[#define TMC$K_IMW 8 /* Inner mode Semaphore wait honor TM_ACTIVE */[#define TMC$K_IMF 9 /* Inner mode Semaphore free ignore TM_ACTIVE */[#define TMC$K_EXIT 10 /* $EXIT honor TM_ACTIVE */[#define TMC$K_FORCEX 11 /* $FORCEX hT ignore TM_ACTIVE */[#define TMC$K_SETAST 12 /* $SETAST honor TM_ACTIVE */[#define TMC$K_UAST 13 /* User mode AST ignore TM_ACTIVE */R#define TMC$K_SYNCH_CTX 14 /* Synch with context honor TM_ACTIVE */Y#define TMC$K_QUANTUM 15 /* Thread quantum ignore TM_ACTIVE */N#define TMC$K_NUM_TYPES 16 /* Number of callback types */#define TMC$K_HIGHEST_TYPE 15N iT#define TMC$K_WFLOR 0 /* $WFLOR callback */N#define TMC$K_WFLAND 1 /* $WFLAND callback */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _tmc {#pragma __nomember_alignmentN __int64 tmc$q_synch; /* $SYNCH */N __int64 tmc$q_jTsetef; /* Set event flag */N __int64 tmc$q_wfl; /* $WFLAND and $WFLOR */N __int64 tmc$q_set_ctx; /* Set synch context */N __int64 tmc$q_hiber; /* $HIBER */N __int64 tmc$q_wake; /* $WAKE */N __int64 tmc$q_pfw; /* Pagefault wait */N __int64 tmc$q_pfc; /* PkTagefault complete */N __int64 tmc$q_imw; /* Inner mode Semaphore wait */N __int64 tmc$q_imf; /* Inner mode Semaphore free */N __int64 tmc$q_exit; /* $EXIT */N __int64 tmc$q_forcex; /* $FORCEX */N __int64 tmc$q_setast; /* $SETAST */N __int64 tmc$q_uast; /* User mode AST lT */N __int64 tmc$q_synch_ctx; /* $SYNCH with context */N __int64 tmc$q_quantum; /* Thread quantum */ } TMC;N#define TMC$C_LENGTH 128 /* Length of TMC */N#define TMC$K_LENGTH 128 /* Length of TMC */N#define TMC$S_TMCDEF 128 /* Old size name - synonym */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* DefinemTd whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TMCDEF_LOADED */ wwx[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/nTM/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary softwareoT licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************* pT*******************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */F/* Source: 11-OCT-2001 16:19:26 $1$DGA8345:[LIB_H.SRC]TQEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TQEDEF ***/#ifndef __TQEDEF_LOADED#define __TQEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */qT!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_prTarams ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* TQE - TIME QUEUE ENTRY */N/* sT */N/* TIME QUEUE ENTRIES ARE UTILIZED TO SET TIMERS, WAKE UP PROCESSES, AND */N/* FOR INTERNAL SYSTEM SUBROUTINES. */N/*- */ #define TQE$M_TQTYPE 0x3#define TQE$M_REPEAT 0x4#define TQE$M_ABSOLUTE 0x8#define TQE$M_CHK_CPUTIM 0x10"#define TQE$M_EXTENDED_FORMAT 0x20#define TQE$M_ASTNODEL 0x40#define TQE$M_RSRVD_7 0x80N#define TQE$C_TMSNGL 0 /*TIMEtTR ENTRY SINGLE SHOT REQUEST */N#define TQE$C_SSREPT 5 /*SYSTEM SUBROUTINE REPEAT REQUEST */S#define TQE$C_SSSNGL 1 /*SYSTEM SUBROUTINE SINGLE SHOT REQUEST */N#define TQE$C_WKREPT 6 /*WAKE ENTRY REPEAT REQUEST */N#define TQE$C_WKSNGL 2 /*WAKE ENTRY SINGLE SHOT REQUEST */N#define TQE$S_TQEDEF 64 /* Old size name - synonym */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) uT /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _tqe {#pragma __nomember_alignmentN struct _tqe *tqe$l_tqfl; /*TIME QUEUE FORWARD LINK */N struct _tqe *tqe$l_tqbl; /*TIME QUEUE BACKWARD LINK */N unsigned short int tqe$w_size; /*SIZE OF TQE IN BYTES */N unsigned char tqe$b_type; /*STRUCTURE TYPE FOR TQE */ vT__union {N unsigned char tqe$b_rqtype; /*TIME QUEUE ENTRY TYPE */ __struct {P unsigned tqe$v_tqtype : 2; /* TQE type (timer, subroutine, wake) */N unsigned tqe$v_repeat : 1; /* REPEAT REQUEST (1=YES) */R unsigned tqe$v_absolute : 1; /* Absolute expiration time specified */U unsigned tqe$v_chk_cputim : 1; /* Process CPU time constrained request */Z unsigned tqe$v_extended_format : 1; /* Extende wTd AST fields included in size */_ unsigned tqe$v_astnodel : 1; /* Don't deallocate TQE/ACB after AST delivery */N unsigned tqe$v_rsrvd_7 : 1; /* Unused bit */ } tqe$r_rqtype_bits; } tqe$r_rqtype_overlay; __union {N unsigned int tqe$l_pid; /*TIMER OR WAKE REQUEST PROCESS ID */N int tqe$l_fpc; /*TIMER SUBROUTINE ADDRESS */ } tqe$r_pid_overlay; __union { xT __struct {N void (*tqe$l_ast)(); /*ADDRESS OF AST ROUTINE */N unsigned int tqe$l_astprm; /*AST PARAMETER */ } tqe$r_ast_fields;N __int64 tqe$q_fr3; /*TIMER SUBROUTINE SAVED R3 */ } tqe$r_ast_overlay;N __int64 tqe$q_fr4; /*TIMER SUBROUTINE SAVED R4 */N unsigned __int64 tqe$q_time; /*ABSOLUTE EXPIRATION TIME */N unsigned __int64 tqe yT$q_delta; /*DELTA REPEAT TIME */N unsigned int tqe$l_rmod; /*ACCESS MODE OF REQUEST */O unsigned int tqe$l_efn; /*EVENT FLAG NUMBER AND EVENT GROUP */N unsigned int tqe$l_rqpid; /*REQUESTER PROCESS ID */Y unsigned int tqe$l_cputim; /* Process CPU time at which entry becomes due */N/* TIME QUEUE ENTRY REQUEST TYPE DEFINITIONS */ } TQE; #if !defined(__VAXC)zT6#define tqe$b_rqtype tqe$r_rqtype_overlay.tqe$b_rqtypeH#define tqe$v_tqtype tqe$r_rqtype_overlay.tqe$r_rqtype_bits.tqe$v_tqtypeH#define tqe$v_repeat tqe$r_rqtype_overlay.tqe$r_rqtype_bits.tqe$v_repeatL#define tqe$v_absolute tqe$r_rqtype_overlay.tqe$r_rqtype_bits.tqe$v_absoluteP#define tqe$v_chk_cputim tqe$r_rqtype_overlay.tqe$r_rqtype_bits.tqe$v_chk_cputimZ#define tqe$v_extended_format tqe$r_rqtype_overlay.tqe$r_rqtype_bits.tqe$v_extended_formatL#define tqe$v_astnodel tqe$r_rqtype_overlay.tqe$ {Tr_rqtype_bits.tqe$v_astnodelJ#define tqe$v_rsrvd_7 tqe$r_rqtype_overlay.tqe$r_rqtype_bits.tqe$v_rsrvd_7-#define tqe$l_pid tqe$r_pid_overlay.tqe$l_pid-#define tqe$l_fpc tqe$r_pid_overlay.tqe$l_fpc>#define tqe$l_ast tqe$r_ast_overlay.tqe$r_ast_fields.tqe$l_astD#define tqe$l_astprm tqe$r_ast_overlay.tqe$r_ast_fields.tqe$l_astprm-#define tqe$q_fr3 tqe$r_ast_overlay.tqe$q_fr3"#endif /* #if !defined(__VAXC) */ N#define TQE$K_LENGTH 64 /*LENGTH OF STANDARD TQE */N#d|Tefine TQE$C_LENGTH 64 /*LENGTH OF STANDARD TQE */N/* */N/* */O/* Extended version of TQE to support a 64-bit ACB if it is embedded in this */P/* structure. Basically, the original TQE format remains the same as before, */N/* but if the EXTENDED_FORMAT bit is set in RQTYPE, the extra ACB quadwords */N/* are included in the s }Ttructure and the internal ACB is configured to look */N/* like the 64-bit extended version with a valid flags longword. */N/* */#define TQE64$M_TQTYPE 0x3#define TQE64$M_REPEAT 0x4#define TQE64$M_ABSOLUTE 0x8#define TQE64$M_CHK_CPUTIM 0x10$#define TQE64$M_EXTENDED_FORMAT 0x20#define TQE64$M_ASTNODEL 0x40N#define TQE64$C_TMSNGL 0 /*TIMER ENTRY SINGLE SHOT REQUEST */N#define TQE64$C_SSRE~TPT 5 /*SYSTEM SUBROUTINE REPEAT REQUEST */S#define TQE64$C_SSSNGL 1 /*SYSTEM SUBROUTINE SINGLE SHOT REQUEST */N#define TQE64$C_WKREPT 6 /*WAKE ENTRY REPEAT REQUEST */N#define TQE64$C_WKSNGL 2 /*WAKE ENTRY SINGLE SHOT REQUEST */N#define TQE64$S_TQEDEF 88 /*Size name - synonym */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nome Tmber_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _tqe64 {#pragma __nomember_alignmentN struct _tqe *tqe64$l_tqfl; /*TIME QUEUE FORWARD LINK */N struct _tqe *tqe64$l_tqbl; /*TIME QUEUE BACKWARD LINK */N unsigned short int tqe64$w_size; /*SIZE OF TQE IN BYTES */N unsigned char tqe64$b_type; /*STRUCTURE TYPE FOR TQE */ __union {N unsigned char tqe64$b_rqtype; T/*TIME QUEUE ENTRY TYPE */ __struct {Q unsigned tqe64$v_tqtype : 2; /* TQE type (timer, subroutine, wake) */N unsigned tqe64$v_repeat : 1; /* REPEAT REQUEST (1=YES) */T unsigned tqe64$v_absolute : 1; /* Absolute expiration time specified */W unsigned tqe64$v_chk_cputim : 1; /* Process CPU time constrained request */\ unsigned tqe64$v_extended_format : 1; /* Extended AST fields included in size */a T unsigned tqe64$v_astnodel : 1; /* Don't deallocate TQE/ACB after AST delivery */) unsigned tqe64$v_fill_0_ : 1;" } tqe64$r_rqtype_bits;! } tqe64$r_rqtype_overlay; __union {N unsigned int tqe64$l_pid; /*TIMER OR WAKE REQUEST PROCESS ID */N int tqe64$l_fpc; /*TIMER SUBROUTINE ADDRESS */ } tqe64$r_pid_overlay; __union { __struct {N unsigned int tqe64$l_acb64x; /*OFFSET TO A TCB64X STRUCTURE */N int tqe64$l_fill_2; /*Not used in ACB64 (ASTPRM in ACB) */! } tqe64$r_ast_fields;N __int64 tqe64$q_fr3; /*TIMER SUBROUTINE SAVED R3 */ } tqe64$r_ast_overlay;N __int64 tqe64$q_fr4; /*TIMER SUBROUTINE SAVED R4 */N unsigned __int64 tqe64$q_time; /*ABSOLUTE EXPIRATION TIME */N unsigned __int64 tqe64$q_delta; /*DELTA REPEAT TIME */N unsignedT int tqe64$l_rmod; /*ACCESS MODE OF REQUEST */O unsigned int tqe64$l_efn; /*EVENT FLAG NUMBER AND EVENT GROUP */N unsigned int tqe64$l_rqpid; /*REQUESTER PROCESS ID */Y unsigned int tqe64$l_cputim; /* Process CPU time at which entry becomes due */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void T (*tqe64$pq_ast)(); /*64-bit AST address */#else unsigned __int64 tqe64$pq_ast;#endifN unsigned __int64 tqe64$q_astprm; /*64-bit ASTPRM value */S unsigned __int64 tqe64$q_user_thread_id; /*Unique thread-specific identifier */N/* TIME QUEUE ENTRY REQUEST TYPE DEFINITIONS */ } TQE64; #if !defined(__VAXC)<#define tqe64$b_rqtype tqe64$r_rqtype_overlay.tqe64$b_rqtypeP#define tqe64$v_tqtype tqe64$r_rqtypTe_overlay.tqe64$r_rqtype_bits.tqe64$v_tqtypeP#define tqe64$v_repeat tqe64$r_rqtype_overlay.tqe64$r_rqtype_bits.tqe64$v_repeatT#define tqe64$v_absolute tqe64$r_rqtype_overlay.tqe64$r_rqtype_bits.tqe64$v_absoluteX#define tqe64$v_chk_cputim tqe64$r_rqtype_overlay.tqe64$r_rqtype_bits.tqe64$v_chk_cputimb#define tqe64$v_extended_format tqe64$r_rqtype_overlay.tqe64$r_rqtype_bits.tqe64$v_extended_formatT#define tqe64$v_astnodel tqe64$r_rqtype_overlay.tqe64$r_rqtype_bits.tqe64$v_astnodel3#define tqe64$l_ Tpid tqe64$r_pid_overlay.tqe64$l_pid3#define tqe64$l_fpc tqe64$r_pid_overlay.tqe64$l_fpcL#define tqe64$l_acb64x tqe64$r_ast_overlay.tqe64$r_ast_fields.tqe64$l_acb64x3#define tqe64$q_fr3 tqe64$r_ast_overlay.tqe64$q_fr3"#endif /* #if !defined(__VAXC) */ N#define TQE64$K_LENGTH 88 /*Length of 64-bit TQE */N#define TQE64$C_LENGTH 88 /*Length of 64-bit TQE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* DefiTned whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TQEDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **T/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary softwaTre licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************** T*********************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */I/* Source: 28-AUG-2001 11:37:35 $1$DGA8345:[LIB_H.SRC]TQEIDXDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TQEIDXDEF ***/#ifndef __TQEIDXDEF_LOADED#define __TQEIDXDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-StandarTd features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#definTe __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* TQEIDX - Timer queue entry index */N/* T */N/* Timer queue entries are maintained in an index structure. */N/*- */ N#define TQEIDX$K_MAP_WIDTH 6 /* Width */N#define TQEIDX$C_MAP_WIDTH 6 /* of bitmap */P#define TQEIDX$K_MAX_WIDTH 6 /* Maximum width allowed by structure */P#define TQEIDX$C_MAX_WIDTH 6 /* Maximum width allowed by structurTe */N#define TQEIDX$K_MAXIDX 64 /* Number of pointers in one */O#define TQEIDX$C_MAXIDX 64 /* index bucket (= bits in bitmap) */N#define TQEIDX$C_LENGTH 800 /* Size */N#define TQEIDX$K_LENGTH 800 /* Size */N#define TQEIDX$S_TQEDEF 800 /* Size (synonym) */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C T++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _tqeidx {#pragma __nomember_alignment[ struct _tqeidx *tqeidx$l_flink; /* Forward link to next bucket (zero terminated) */\ struct _tqeidx *tqeidx$l_blink; /* Back link to previous bucket (zero terminated) */N unsigned short int tqeidx$w_size; /* Size of this structure */N unsigned char tqeidx$b_type; /* (misc) */N unTsigned char tqeidx$b_subtype; /* (tqeidx) */N int tqeidx$l_level; /* Index level */N int tqeidx$l_freecnt; /* Number of free array entries */N struct _tqeidx *tqeidx$l_parent; /* Pointer to parent bucket */N unsigned __int64 tqeidx$q_bitmap; /* Free space bitmap; */N/* Min: 2 (1@2 - 1 = 3 entries per bucket) */N/* Max: 6 (1@6 - 1 = 63 entries Tper bucket) */N/* Cannot exceed 64 (size of bitmap = 1 quad) */N unsigned __int64 tqeidx$q_key [64]; /* Array of ordered keys */Q void *tqeidx$ps_ptr [64]; /* Array of pointers to target element */N/* or next level bucket */ } TQEIDX; #ifdef TQEIDX$C_DEBUG#undef TQEIDX$C_MAP_WIDTH;#undef TQEIDX$C_MAXIDX;#endif $#pragma __member_alignmeTnt __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TQEIDXDEF_LOADED */ ww0[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTITAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This soTftware is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/********************************************************************* T******//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */F/* Source: 28-JUL-2003 11:15:07 $1$DGA8345:[LIB_H.SRC]TRDDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TRDDEF ***/#ifndef __TRDDEF_LOADED#define __TRDDEF_LOADED 1 G#pragma __no Tstandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params T...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif #define TRD$M_VALID 0x1#define TRD$M_PL 0x6#define TRD$M_AR 0x38##define TRD$M_RESERVED_1 0xFFFFFFC0+#define TRD$M_RESERVED_2 0xFFFFFFFF00000000#define TRD$C_TLENGTH 32 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _trd {#pragma __nomember_alignment __union {% unsigned __int64 trd$q_flags; __struct {N unsigned trd$v_valid : 1; /* Valid */N unsigned trd$v_pl : 2; /* Privilege level */N T unsigned trd$v_ar : 3; /* Access Rights */N unsigned trd$v_reserved_1 : 26; /* Unused */N unsigned trd$v_reserved_2 : 32; /* Unused */ } trd$r_trddef_bits; } trd$r_trd_union;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *trd$pq_va; T /* Virtual address */#else unsigned __int64 trd$pq_va;#endifN unsigned __int64 trd$q_pa; /* Physical address */N unsigned int trd$l_ps; /* Page size bits */" unsigned int trd$l_reserved_3; } TRD; #if !defined(__VAXC)/#define trd$q_flags trd$r_trd_union.trd$q_flagsA#define trd$v_valid trd$r_trd_union.trd$r_trddef_bits.trd$v_valid;#define trd$v_pl trd$r_trd_union.trd$r_trddef_bits.trd$v_pl;#d Tefine trd$v_ar trd$r_trd_union.trd$r_trddef_bits.trd$v_ar"#endif /* #if !defined(__VAXC) */ N/* */N/* These symbols are used to define which TRs are used for what purposes. */N/* Note: there are both instruction and data translation registers. So, */N/* we distinguish which TR the constant is for by putting ITR or DTR in */N/* the symbol name. */N/* T */N#define TRD$C_DTR_VHPT1 0 /* 1st DTR used for the VHPT */N#define TRD$C_DTR_VHPT2 1 /* 2nd DTR used for the VHPT */N#define TRD$C_IVT_SWIS1 5 /* ITR used for the IVT and SWIS */^#define TRD$C_IVT_SWIS2 6 /* 2nd ITR used for the IVT and SWIS (if necessary) */S#define TRD$C_DTR_SLOT_VA 7 /* DTR used for the slot virtual address */N#define TRTD$C_ITR_PAL_CODE 7 /* ITR used for PAL code */N#define TRD$C_DTR_SWIS_DATA 8 /* DTR used for SWIS data */N/* */N/* Minimum number of TRs supported by the IA64 architecture */N/* */#define TRD$C_MIN_TRS 8N/* */N/* Page si Tze for PAL's TR */N/* */N#define TRD$C_PAL_PS 18 /* 256K */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragm Ta __standard #endif /* __TRDDEF_LOADED */ wwPc[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission oTf HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. T **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */G/* Source: 18-JAN-2002 13:52:15 $1$DGA8345:[L TIB_H.SRC]TSRVDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TSRVDEF ***/#ifndef __TSRVDEF_LOADED#define __TSRVDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __saTve /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAX TC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* TSRV ( ) Definitions */N/* */I/* This module defines the main data structure of the TMSCP */I/* server. This structure contains the values specified in */I/* the start up qualifiersT when the server was loaded, the */I/* UQB vector table, and statistics that are kept for server */I/* performance measurements. */I/* */I/* This structure is being checked in with fields aligned */I/* to the MSCP structure DSRV. This is not a requirement */I/* and may be changed in the future if necessary. */NT/* */N/* <<== !NOTICE! ==>> */N/* */I/* DO NOT change offsets of the top part of the data structure. */J/* If new fields have to be added please make them below the */I/* forward and backward links to the UQB. */N/*- T */ N/*Max number of served units */#define TSRV$M_LOG_ENABLD 0x1#define TSRV$M_LOG_PRESENT 0x2#define TSRV$M_PKT_LOGGED 0x4#define TSRV$M_PKT_LOST 0x8#define TSRV$M_LBSTEP1 0x10#define TSRV$M_LBSTEP2 0x20#define TSRV$M_LBEVENT 0x40#define TSRV$M_HULB_DEL 0x80#define TSRV$M_MON_ACTIVE 0x100#define TSRV$M_LB_REQ 0x200#define TSRV$C_LENGTH 1912#define TSRV$K_LENGTH 1912N#define TSRV$K T_AR_ADD 2 /* Action routine code */#define TSRV$K_MAX_UNITS 256  9#ifdef __cplusplus /* Define structure prototypes */ struct _uqb; #endif /* #ifdef __cplusplus */ typedef struct _tsrv$r_tsrv {N void *tsrv$l_flink; /* Field maintained for */N void *tsrv$l_blink; /* compatability */N unsigned short int tsrv$w_size; /* Structure size in bytes */N unsigned char Ttsrv$b_type; /* MSCP type structure */N unsigned char tsrv$b_subtype; /* with a TSRV subtype (1) */ __union {N unsigned short int tsrv$w_state; /* Current state of the server */ __struct {N unsigned tsrv$v_log_enabld : 1; /* Logging is enabled */N unsigned tsrv$v_log_present : 1; /* Logging code is present */N unsigned tsrv$v_pkt_logged : 1; /* A packet has been logged */N T unsigned tsrv$v_pkt_lost : 1; /* One or more packets over- */N/* written since last read */N unsigned tsrv$v_lbstep1 : 1; /* Load balancing step1 active */N unsigned tsrv$v_lbstep2 : 1; /* Load balancing step2 active */N unsigned tsrv$v_lbevent : 1; /* An event of interest to LB has */N/* occured while STEP1 was active */O unsigned tsrv$v_hulb T_del : 1; /* One or more HULBs to be deleted */S unsigned tsrv$v_mon_active : 1; /* The load monitor thread is active */R unsigned tsrv$v_lb_req : 1; /* A load balance request has been sent */( unsigned tsrv$v_fill_2_ : 6; } tsrv$r_fill_1_; } tsrv$r_fill_0_;N unsigned short int tsrv$w_bufwait; /*I/Os that had to wait */N void *tsrv$l_log_buf_start; /* Address of start of buffer */N void *tsrv$l_log_bufT_end; /* Address of end of buffer */N void *tsrv$l_next_read; /* Adrs of next packet to read */N void *tsrv$l_next_write; /* Adrs of next packet to write */N unsigned short int tsrv$w_inc_lolim; /* Low unit number to log */N unsigned short int tsrv$w_inc_hilim; /* High unit number to log */N unsigned short int tsrv$w_exc_lolim; /* Low unit number not to log */N unsigned short int tsrv$w_exc_hilim; /* High uTnit number not to log */N int tsrv$l_filler1 [5]; /* Keep compatible with DSRV */N __struct { /* Info returned in GCI cmd */N unsigned short int tsrv$w_version; /* Server software version */N unsigned short int tsrv$w_cflags; /* Controller flags */N unsigned short int tsrv$w_ctimo; /* Controller timeout */N unsigned short int tsrv$w_reserved; /* Reserved T*/ } tsrv$r_ctrl_info;N unsigned __int64 tsrv$q_ctrl_id; /* Unique MSCP device identifier */N int tsrv$l_filler2 [4]; /* Keep compatible with DSRV */N unsigned short int tsrv$w_num_host; /* Count of hosts being served */N unsigned short int tsrv$w_num_unit; /* Count of disks being served */N void *tsrv$l_hqb_fl; /* Host queue block list head */N void *tsrv$l_hqb_bl; /* T */N void *tsrv$l_uqb_fl; /* Unit queue block list head */N void *tsrv$l_uqb_bl; /* */N int tsrv$l_filler3 [24]; /* Keep compatible with DSRV */N struct _uqb *tsrv$l_units [256]; /* Table of UQB addresses */N/* */N/* new fields should be added here, after the UQB linkages */N/* T */N/* */I/* Statistics gathering fields */N/* */I/* Two tables are maintained below. The first table is made up of the */I/* frequency count for each of the opcodes received since the server */J/* was loaded. The opcode is used as an index into the tTable to its own */I/* frequency count (the zeroeth element contains a total count). The */I/* second table is made up of the frequency counters for all the */I/* different sized block transfers. For this table, the size of the */I/* transfer is the index into the table. */N/* */N __struct { /* Op-code counters */N unsigned int tTsrv$l_opcount; /* Total operations count */N unsigned int tsrv$l_abort_cnt; /* - 1 - */N unsigned int tsrv$l_get_cmd_cnt; /* - 2 - */N unsigned int tsrv$l_get_unt_cnt; /* - 3 - */N unsigned int tsrv$l_set_con_cnt; /* - 4 - */N unsigned int tsrv$l_reserved5; /* - 5 - */N unsigned int tsrv$l_reserved6; /* - 6T - */N unsigned int tsrv$l_reserved7; /* - 7 - */N unsigned int tsrv$l_avail_cnt; /* - 8 - */N unsigned int tsrv$l_onlin_cnt; /* - 9 - */N unsigned int tsrv$l_set_unt_cnt; /* - 10 - */N unsigned int tsrv$l_det_acc_cnt; /* - 11 - */N unsigned int tsrv$l_reserved12; /* - 12 - T */N unsigned int tsrv$l_reserved13; /* - 13 - */N unsigned int tsrv$l_reserved14; /* - 14 - */N unsigned int tsrv$l_reserved15; /* - 15 - */N unsigned int tsrv$l_acces_cnt; /* - 16 - */N unsigned int tsrv$l_cmp_con_cnt; /* - 17 - */N unsigned int tsrv$l_erase_cnt; /* - 18 - */N unsigned intT tsrv$l_flush_cnt; /* - 19 - */N unsigned int tsrv$l_replc_cnt; /* - 20 - */N unsigned int tsrv$l_reserved21; /* - 21 - */N unsigned int tsrv$l_reserved22; /* - 22 - */N unsigned int tsrv$l_reserved23; /* - 23 - */N unsigned int tsrv$l_reserved24; /* - 24 - */N unsigned int tsrv$l_reserved25; /* -T 25 - */N unsigned int tsrv$l_reserved26; /* - 26 - */N unsigned int tsrv$l_reserved27; /* - 27 - */N unsigned int tsrv$l_reserved28; /* - 28 - */N unsigned int tsrv$l_reserved29; /* - 29 - */N unsigned int tsrv$l_reserved30; /* - 30 - */N unsigned int tsrv$l_reserved31; /* - 31 - T */N unsigned int tsrv$l_cmp_hst_cnt; /* - 32 - */N unsigned int tsrv$l_read_cnt; /* - 33 - */N unsigned int tsrv$l_write_cnt; /* - 34 - */N unsigned int tsrv$l_reserved35; /* - 35 - */N unsigned int tsrv$l_reserved36; /* - 36 - */N unsigned int tsrv$l_reserved37; /* - 37 - */N unsigned i Tnt tsrv$l_reserved38; /* - 38 - */N unsigned int tsrv$l_reserved39; /* - 39 - */ } tsrv$r_opcode_cntrs;N unsigned int tsrv$l_vcfail_cnt; /* Count of VC failures */N unsigned int tsrv$l_blkcount [129]; /* Counters for block xfer reqs */ } TSRV$R_TSRV; #if !defined(__VAXC)0#define tsrv$w_state tsrv$r_fill_0_.tsrv$w_stateI#define tsrv$v_log_enabld tsrv$r_fill_0_.tsrv$r_fill_1_.tsrv$v_log_enabldKT#define tsrv$v_log_present tsrv$r_fill_0_.tsrv$r_fill_1_.tsrv$v_log_presentI#define tsrv$v_pkt_logged tsrv$r_fill_0_.tsrv$r_fill_1_.tsrv$v_pkt_loggedE#define tsrv$v_pkt_lost tsrv$r_fill_0_.tsrv$r_fill_1_.tsrv$v_pkt_lostC#define tsrv$v_lbstep1 tsrv$r_fill_0_.tsrv$r_fill_1_.tsrv$v_lbstep1C#define tsrv$v_lbstep2 tsrv$r_fill_0_.tsrv$r_fill_1_.tsrv$v_lbstep2C#define tsrv$v_lbevent tsrv$r_fill_0_.tsrv$r_fill_1_.tsrv$v_lbeventE#define tsrv$v_hulb_del tsrv$r_fill_0_.tsrv$r_fill_1_.tsrv$v_hulb_del TI#define tsrv$v_mon_active tsrv$r_fill_0_.tsrv$r_fill_1_.tsrv$v_mon_activeA#define tsrv$v_lb_req tsrv$r_fill_0_.tsrv$r_fill_1_.tsrv$v_lb_req6#define tsrv$w_version tsrv$r_ctrl_info.tsrv$w_version4#define tsrv$w_cflags tsrv$r_ctrl_info.tsrv$w_cflags2#define tsrv$w_ctimo tsrv$r_ctrl_info.tsrv$w_ctimo9#define tsrv$l_opcount tsrv$r_opcode_cntrs.tsrv$l_opcount=#define tsrv$l_abort_cnt tsrv$r_opcode_cntrs.tsrv$l_abort_cntA#define tsrv$l_get_cmd_cnt tsrv$r_opcode_cntrs.tsrv$l_get_cmd_cntA#definTe tsrv$l_get_unt_cnt tsrv$r_opcode_cntrs.tsrv$l_get_unt_cntA#define tsrv$l_set_con_cnt tsrv$r_opcode_cntrs.tsrv$l_set_con_cnt=#define tsrv$l_avail_cnt tsrv$r_opcode_cntrs.tsrv$l_avail_cnt=#define tsrv$l_onlin_cnt tsrv$r_opcode_cntrs.tsrv$l_onlin_cntA#define tsrv$l_set_unt_cnt tsrv$r_opcode_cntrs.tsrv$l_set_unt_cntA#define tsrv$l_det_acc_cnt tsrv$r_opcode_cntrs.tsrv$l_det_acc_cnt=#define tsrv$l_acces_cnt tsrv$r_opcode_cntrs.tsrv$l_acces_cntA#define tsrv$l_cmp_con_cnt tsrv$r_opcode_cntrs.t Tsrv$l_cmp_con_cnt=#define tsrv$l_erase_cnt tsrv$r_opcode_cntrs.tsrv$l_erase_cnt=#define tsrv$l_flush_cnt tsrv$r_opcode_cntrs.tsrv$l_flush_cnt=#define tsrv$l_replc_cnt tsrv$r_opcode_cntrs.tsrv$l_replc_cntA#define tsrv$l_cmp_hst_cnt tsrv$r_opcode_cntrs.tsrv$l_cmp_hst_cnt;#define tsrv$l_read_cnt tsrv$r_opcode_cntrs.tsrv$l_read_cnt=#define tsrv$l_write_cnt tsrv$r_opcode_cntrs.tsrv$l_write_cnt"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_PTOINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TSRVDEF_LOADED */ wwp[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential Tproprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/TM/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************** T*********************************************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */J/* Source: 16-DEC-1998 16:25:25 $1$DGA8345:[LIB_H.SRC]TSUNAMIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TSUNAMIDEF ***/#ifndef __TSUNAMIDEF_LOADED#define __TSUNAMIDEF_LOADED 1 G#pragma __nostandard /* ThiTs file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#defTine __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* */N/* FACILITY: OpenVMS AXP SyTstem Macro Libraries */N/* */N/* ABSTRACT: */N/* */L/* This file defines the control and status registers of the Tsunami Chip */I/* Set (TCS), designed for use in EV6 based platforms. */N/* T */L/* Because of the disparities in the address spaces for the various chips */K/* in the Tsunami Chip Set, and because there are one C-Chip, as many as */I/* eight D-Chips and as many as two P-Chips, the Tsunami Chip Set */L/* structure is defined as three distinct data stuctures, C_CHIP, D_CHIP, */M/* and P_CHIP. This simplifies the definition, but puts an extra burden on */K/* the programmer to use the correct base addresses for the three chips. */N/* T */L/* The following table shows the regions for the Tsunami Chip Set address */I/* space. */N/* */J/* -------------------------------------------------------------------- */I/* Cchip Address Space */J/* -------------------------------------------------------T------------- */F/* 801 0000 0000 1 GB TIG Bus, addr<5:0> = 0, single byte valid in */4/* quadword access, 16 MB accessible */F/* 801 a000 0000 256 MB Cchip CSRs, addr<5:0> = 0, quadword access */J/* -------------------------------------------------------------------- */N/* */J/* -------------------------------------------------------------------- */I/* Dchip Address Space T */J/* -------------------------------------------------------------------- */H/* 801 b000 0000 256 MB Dchip CSRs, addr<5:0> = 0, all eight bytes in */4/* quadword access must be identical. */J/* -------------------------------------------------------------------- */N/* */J/* -------------------------------------------------------------------- */I/* Pchip-0 Address Space T */J/* -------------------------------------------------------------------- */F/* 800 0000 0000 4 GB PCI Memory */F/* 801 8000 0000 256 MB CSRs, addr<5:0> = 0, quadword access */F/* 801 f800 0000 64 MB PCI IACK/Special */F/* 801 fc00 0000 32 MB PCI IO */F/* 801 fe00 0000 16 MB PCI config space */J/* -------------------------------------------T------------------------- */I/* */J/* -------------------------------------------------------------------- */I/* Pchip-1 Address Space */J/* -------------------------------------------------------------------- */F/* 802 0000 0000 4 GB PCI Memory */F/* 803 8000 0000 256 MB CSRs, addr<5:0> = 0, quadword access */F/* 803 f800 0000 64 MB PCI TIACK/Special */F/* 803 fc00 0000 32 MB PCI IO */F/* 803 fe00 0000 16 MB PCI config space */J/* -------------------------------------------------------------------- */N/* */N/* AUTHOR: */N/* */*/*T Tony Camuso 14-Jan-1997 */N/* */N/* MODIFIED BY: */N/* *///* X-3 TLC Tony Camuso 16-Dec-1998 */B/* Add constant for maximum supported CPUs */N/* */:/* X-2 PAJ1025 Paul A. JTacobi 12-Oct-1998 */B/* Rename DIR$ to CDIR$ to avoid conflict with other symbols. */N/* */4/* X-1 TLC Tony Camuso 14-Jan-1997 */B/* Initial entry. */I/* */N/*-- */N/* The maximum number of CPUs supported by the T Tsunami chipset */N/* */#define TSUNAMI$K_MAX_CPU 4#define TSUNAMI$C_MAX_CPU 4N/* */Q/* Since SDL currently doesn't support constants greater 2**32, the high-order */N/* bits (%X80x) have their own constants defined. */N/* */N/* Tsuna Tmi Chip Set CSR base addresses <63:32> (High longword) */N/* =========================================================== */N/* */#define TSUNAMI$L_C_CHIP_H 2049#define TSUNAMI$L_D_CHIP_H 2049N/* */$#define TSUNAMI$L_P0_CHIP_MEM_H 2048##define TSUNAMI$L_P0_CHIP_IO_H 2049$#define TSUNAMI$L_P0_CHIP_CSR_H 2049N/* T */$#define TSUNAMI$L_P1_CHIP_MEM_H 2050##define TSUNAMI$L_P1_CHIP_IO_H 2051$#define TSUNAMI$L_P1_CHIP_CSR_H 2051N/* */N/* */N/* Tsunami Chip Set CSR base addresses <31:0> (Low longword) */N/* ========================================================= */N/* T */N#define TSUNAMI$L_C_CHIP_L -1610612736 /* Cchip */N#define TSUNAMI$L_D_CHIP_L -1342177280 /* Dchip */N/* */N/* */N/* P-Chip */N/* ------ T */ #define TSUNAMI$L_P_CHIP_MEM_L 0'#define TSUNAMI$L_P_CHIP_IO_L -67108864*#define TSUNAMI$L_P_CHIP_CSR_L -2147483648*#define TSUNAMI$L_P_CHIP_IACK_L -134217728+#define TSUNAMI$L_P_CHIP_CONFIG_L -33554432N/* */N/* */N/* Tsunami Chip Set CSR offsets */N/* ===T============================================== */N/* */N/* ------------------------------------------------- */N/* C-Chip - base addr<63:32> = TSUNAMI$L_C_CHIP_H */N/* base addr<31:0> = TSUNAMI$L_C_CHIP_L */N/* ------------------------------------------------- */N#define TSUNAMI$L_CSC_L 0 T /* Cchip System Config */N#define TSUNAMI$L_MTR_L 64 /* */N#define TSUNAMI$L_MISC_L 128 /* */N#define TSUNAMI$L_MPD_L 192 /* */N/* */N#define TSUNAMI$L_AAR0_L 256 /* */N#define TSUNAMI$L_AAR1_L 320 /* T */N#define TSUNAMI$L_AAR2_L 384 /* */N#define TSUNAMI$L_AAR3_L 448 /* */N/* */N#define TSUNAMI$L_DIM0_L 512 /* */N#define TSUNAMI$L_DIM1_L 576 /* */N#define TSUNAMI$L_DIR0_L 640 /* */N#defTine TSUNAMI$L_DIR1_L 704 /* */N/* */N#define TSUNAMI$L_DRIR_L 768 /* */N#define TSUNAMI$L_PRBEN_L 832 /* */N#define TSUNAMI$L_IIC0_L 896 /* */N#define TSUNAMI$L_IIC1_L 960 /* */N/* T */N#define TSUNAMI$L_MPR0_L 1024 /* */N#define TSUNAMI$L_MPR1_L 1088 /* */N#define TSUNAMI$L_MPR2_L 1152 /* */N#define TSUNAMI$L_MPR3_L 1216 /* */N/* */N#define TSUNAMI$L_MCTL_L 1280 /* T */N#define TSUNAMI$L_TTR_L 1408 /* */N#define TSUNAMI$L_TDR_L 1472 /* */N/* */N#define TSUNAMI$L_DIM2_L 1536 /* */N#define TSUNAMI$L_DIM3_L 1600 /* */N#define TSUNAMI$L_DIR2_L 1664 /* */N#dTefine TSUNAMI$L_DIR3_L 1728 /* */N/* */N#define TSUNAMI$L_IIC2_L 1792 /* */N#define TSUNAMI$L_IIC3_L 1856 /* */N/* */N/* */N/* -------------------------T---------------------------- */N/* D-Chip - base addr <63:32> = TSUNAMI$L_D_CHIP_H */N/* base addr <31:0> = TSUNAMI$L_D_CHIP_L */N/* ----------------------------------------------------- */N#define TSUNAMI$L_DSC_L 2048 /* */N#define TSUNAMI$L_STR_L 2112 /* */N#define TSUNAMI$L_DREV_L 2176 /* T */N/* */N/* */N/* ----------------------------------------------------- */N/* P-Chip - P0 base addr<63:32> = TSUNAMI$L_P0_CHIP_CSR_H */N/* P0 base addr<32:0> = TSUNAMI$L_P_CHIP_CSR_L */N/* */NT/* P1 base addr<63:32> = TSUNAMI$L_P1_CHIP_CSR_H */N/* P1 base addr<32:0> = TSUNAMI$L_P_CHIP_CSR_L */N/* ----------------------------------------------------- */N#define TSUNAMI$L_WSBA0_L 0 /* */N#define TSUNAMI$L_WSBA1_L 64 /* */N#define TSUNAMI$L_WSBA2_L 128 /* */N#define TSUNAMI$L_WSBA3_L T192 /* */N/* */N#define TSUNAMI$L_WSMA0_L 256 /* */N#define TSUNAMI$L_WSMA1_L 320 /* */N#define TSUNAMI$L_WSMA2_L 384 /* */N#define TSUNAMI$L_WSMA3_L 448 /* */N/* T */N#define TSUNAMI$L_TBA0_L 512 /* */N#define TSUNAMI$L_TBA1_L 576 /* */N#define TSUNAMI$L_TBA2_L 640 /* */N#define TSUNAMI$L_TBA3_L 704 /* */N/* */N#define TSUNAMI$L_PCTL_L 768 /* */TN#define TSUNAMI$L_PLAT_L 832 /* */N/* */N#define TSUNAMI$L_P_RESERVED_1_L 896 /* */N/* */N#define TSUNAMI$L_PERROR_L 960 /* */N#define TSUNAMI$L_PERRMASK_L 1024 /* */N#define TSUNAMI$L_PERRSETT_L 1088 /* */N/* */N#define TSUNAMI$L_TLBIV_L 1152 /* */N#define TSUNAMI$L_TLBIA_L 1216 /* */N/* */N#define TSUNAMI$L_PMONCTL_L 1280 /* */N#define TSUNAMI$L_PMONCNT_L 1344 /* T */N/* */N/* */O/*************************************************************************** */N/* */N/* Tsunami Chip Set Structures */N/* T */O/*************************************************************************** */N/* */O/*========================================================================== */N/* */N/* C-CHIP Structure */O/*========================================================================== */ c#if !defin Ted(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _c_chip {N/* */N/* 801.A000.000 */N/* */N/* CSC - C-Chip System Configuration Register T */N/* */#pragma __nomember_alignment __union {' unsigned __int64 c_chip$iq_csc;% unsigned char csc$b_pad [64]; } c_chip$r_csc_overlay;N/* */N/* 801.A000.0040 */N/* */N/* M TTR - C-Chip Memory Timing Register */N/* */ __union {' unsigned __int64 c_chip$iq_mtr;% unsigned char mtr$b_pad [64]; } c_chip$r_mtr_overlay;N/* */N/* 801.A000.0080 */N/* T */N/* MISC - C-Chip Miscellaneous Register */N/* */ __union {( unsigned __int64 c_chip$iq_misc;% unsigned char csc$b_pad [64]; } c_chip$r_misc_overlay;N/* */N/* 801.A000.00C0 */N/* T */N/* MPD - C-Chip Memory Presence Detect */N/* */ __union {' unsigned __int64 c_chip$iq_mpd;% unsigned char mpd$b_pad [64]; } c_chip$r_mpd_overlay;N/* */N/* 801.A000.0100 */N/* T */N/* AAR0 - C-Chip Array Address Register 0 */N/* */ __union {( unsigned __int64 c_chip$iq_aar0;& unsigned char aar0$b_pad [64]; } c_chip$r_aar0_overlay;N/* */N/* 801.A000.0140 T */N/* */N/* AAR1 - C-Chip Array Address Register 1 */N/* */ __union {( unsigned __int64 c_chip$iq_aar1;& unsigned char aar1$b_pad [64]; } c_chip$r_aar1_overlay;N/* */N/* 801.A000.0180 T */N/* */N/* AAR2 - C-Chip Array Address Register 2 */N/* */ __union {( unsigned __int64 c_chip$iq_aar2;& unsigned char aar2$b_pad [64]; } c_chip$r_aar2_overlay;N/* */N/* 801.A T000.01C0 */N/* */N/* AAR3 - C-Chip Array Address Register 3 */N/* */ __union {( unsigned __int64 c_chip$iq_aar3;& unsigned char aar3$b_pad [64]; } c_chip$r_aar3_overlay;N/* T */N/* 801.A000.0200 */N/* */N/* DIM0 - C-Chip Device Interrupt Mask Register 0 */N/* */ __union {( unsigned __int64 c_chip$iq_dim0;& unsigned char dim0$b_pad [64]; } c_chip$r_dim0_overlay;N/* T */N/* 801.A000.0240 */N/* */N/* DIM1 - C-Chip Device Interrupt Mask Register 1 */N/* */ __union {( unsigned __int64 c_chip$iq_dim1;& unsigned char dim1$b_pad [64]; } c_chip$r_dim1_overlay;N/* T */N/* 801.A000.0280 */N/* */N/* DIR0 - C-Chip Device Interrupt Request Register */N/* */ __union {( unsigned __int64 c_chip$iq_dir0;& unsigned char dir0$b_pad [64]; } c_chip$r T_dir0_overlay;N/* */N/* 801.A000.02C0 */N/* */N/* DIR1 - C-Chip Device Interrupt Request Register */N/* */ __union {( unsigned __int64 c_chip$iq_dir1;& unsigned char dir1$b_pad T [64]; } c_chip$r_dir1_overlay;N/* */N/* 801.A000.0300 */N/* */N/* DRIR - C-Chip Raw Interrupt Request Register */N/* */ __union {( unsigned __int64 c_chip$iq_drir;& T unsigned char drir$b_pad [64]; } c_chip$r_drir_overlay;N/* */N/* 801.A000.0340 */N/* */N/* PRBEN - C-Chip Probe Enable Register */N/* */ __union {) unsigned __int T64 c_chip$iq_prben;' unsigned char prben$b_pad [64];! } c_chip$r_prben_overlay;N/* */N/* 801.A000.0380 */N/* */N/* IIC0 - C-Chip Interval Ignore Count Register 0 */N/* */ __ Tunion {( unsigned __int64 c_chip$iq_iic0;& unsigned char iic0$b_pad [64]; } c_chip$r_iic0_overlay;N/* */N/* 801.A000.03C0 */N/* */N/* IIC1 - C-Chip Interval Ignore Count Register 1 */N/* T */ __union {( unsigned __int64 c_chip$iq_iic1;& unsigned char iic1$b_pad [64]; } c_chip$r_iic1_overlay;N/* */N/* 801.A000.0400 */N/* */N/* MPR0 - C-Chip Memory Programming Register 0 */N/* T */ __union {( unsigned __int64 c_chip$iq_mpr0;& unsigned char mpr0$b_pad [64]; } c_chip$r_mpr0_overlay;N/* */N/* 801.A000.0440 */N/* */N/* MPR1 - C-Chip Memory Programming Register 1 */N/* T */ __union {( unsigned __int64 c_chip$iq_mpr1;& unsigned char mpr1$b_pad [64]; } c_chip$r_mpr1_overlay;N/* */N/* 801.A000.0480 */N/* */N/* MPR2 - C-Chip Memory Programming Register 2 T */N/* */ __union {( unsigned __int64 c_chip$iq_mpr2;& unsigned char mpr2$b_pad [64]; } c_chip$r_mpr2_overlay;N/* */N/* 801.A000.04C0 */N/* */N/* MPR3 - C-Chip Memory Programming TRegister 3 */N/* */ __union {( unsigned __int64 c_chip$iq_mpr3;& unsigned char mpr3$b_pad [64]; } c_chip$r_mpr3_overlay;N/* */N/* 801.A000.0500 */N/* */N/* MCTL - TC-Chip M-Port Control Register */N/* */ __union {( unsigned __int64 c_chip$iq_mctl;' unsigned char mctl$b_pad [128]; } c_chip$r_mctl_overlay;N/* */N/* 801.A000.0580 */N/* T */N/* TTR - C-Chip TIG Bus Timing Register */N/* */ __union {' unsigned __int64 c_chip$iq_ttr;% unsigned char ttr$b_pad [64]; } c_chip$r_ttr_overlay;N/* */N/* 801.A000.05C0 */N/* T */N/* TDR - C-Chip TIG Bus Device Timing Register */N/* */ __union {' unsigned __int64 c_chip$iq_tdr;% unsigned char tdr$b_pad [64]; } c_chip$r_tdr_overlay;N/* */N/* 801.A000.0600 */N/* T */N/* DIM2 - C-Chip Device Interrupt Mask Register 2 */N/* */ __union {( unsigned __int64 c_chip$iq_dim2;& unsigned char dim2$b_pad [64]; } c_chip$r_dim2_overlay;N/* */N/* 801.A000.0640 T */N/* */N/* DIM3 - C-Chip Device Interrupt Mask Register 3 */N/* */ __union {( unsigned __int64 c_chip$iq_dim3;& unsigned char dim3$b_pad [64]; } c_chip$r_dim3_overlay;N/* */N/* 801.A000.0680 T */N/* */N/* DIR2 - C-Chip Device Interrupt Request Register 2 */N/* */ __union {( unsigned __int64 c_chip$iq_dir2;& unsigned char dir2$b_pad [64]; } c_chip$r_dir2_overlay;N/* */N/* 801.A000. T06C0 */N/* */N/* DIR3 - C-Chip Device Interrupt Request Register 3 */N/* */ __union {( unsigned __int64 c_chip$iq_dir3;& unsigned char dir3$b_pad [64]; } c_chip$r_dir3_overlay;N/* T */N/* 801.A000.0700 */N/* */N/* IIC2 - C-Chip Interval Ignore Count Register 2 */N/* */ __union {( unsigned __int64 c_chip$iq_iic2;& unsigned char iic2$b_pad [64]; } c_chip$r_iic2_overlay;N/* U */N/* 801.A000.0740 */N/* */N/* IIC3 - C-Chip Interval Ignore Count Register 3 */N/* */ __union {( unsigned __int64 c_chip$iq_iic3;' unsigned char iic3$b_pad [192]; } c_chip$r_iic3_overlay;N/* U */ } C_CHIP; #if !defined(__VAXC)8#define c_chip$iq_csc c_chip$r_csc_overlay.c_chip$iq_csc8#define c_chip$iq_mtr c_chip$r_mtr_overlay.c_chip$iq_mtr;#define c_chip$iq_misc c_chip$r_misc_overlay.c_chip$iq_misc8#define c_chip$iq_mpd c_chip$r_mpd_overlay.c_chip$iq_mpd;#define c_chip$iq_aar0 c_chip$r_aar0_overlay.c_chip$iq_aar0;#define c_chip$iq_aar1 c_chip$r_aar1_overlay.c_chip$iq_aar1;#define c_chip$iq_aar2 c_chip$r_aar2 U_overlay.c_chip$iq_aar2;#define c_chip$iq_aar3 c_chip$r_aar3_overlay.c_chip$iq_aar3;#define c_chip$iq_dim0 c_chip$r_dim0_overlay.c_chip$iq_dim0;#define c_chip$iq_dim1 c_chip$r_dim1_overlay.c_chip$iq_dim1;#define c_chip$iq_dir0 c_chip$r_dir0_overlay.c_chip$iq_dir0;#define c_chip$iq_dir1 c_chip$r_dir1_overlay.c_chip$iq_dir1;#define c_chip$iq_drir c_chip$r_drir_overlay.c_chip$iq_drir>#define c_chip$iq_prben c_chip$r_prben_overlay.c_chip$iq_prben;#define c_chip$iq_iic0 c_chip$r_iic0_overlay U.c_chip$iq_iic0;#define c_chip$iq_iic1 c_chip$r_iic1_overlay.c_chip$iq_iic1;#define c_chip$iq_mpr0 c_chip$r_mpr0_overlay.c_chip$iq_mpr0;#define c_chip$iq_mpr1 c_chip$r_mpr1_overlay.c_chip$iq_mpr1;#define c_chip$iq_mpr2 c_chip$r_mpr2_overlay.c_chip$iq_mpr2;#define c_chip$iq_mpr3 c_chip$r_mpr3_overlay.c_chip$iq_mpr3;#define c_chip$iq_mctl c_chip$r_mctl_overlay.c_chip$iq_mctl8#define c_chip$iq_ttr c_chip$r_ttr_overlay.c_chip$iq_ttr8#define c_chip$iq_tdr c_chip$r_tdr_overlay.c_chip$iq_tdr; U#define c_chip$iq_dim2 c_chip$r_dim2_overlay.c_chip$iq_dim2;#define c_chip$iq_dim3 c_chip$r_dim3_overlay.c_chip$iq_dim3;#define c_chip$iq_dir2 c_chip$r_dir2_overlay.c_chip$iq_dir2;#define c_chip$iq_dir3 c_chip$r_dir3_overlay.c_chip$iq_dir3;#define c_chip$iq_iic2 c_chip$r_iic2_overlay.c_chip$iq_iic2;#define c_chip$iq_iic3 c_chip$r_iic3_overlay.c_chip$iq_iic3"#endif /* #if !defined(__VAXC) */ N/* */N/* U */N/* */O/*========================================================================== */N/* */N/* D-CHIP Structure */N/* */S/* NOTE: All the registers in this stUructure are abstracted as 64-bit entities. */N/* Therefore, they MUST be accessed and manipulated as quadwords and with */I/* quadwords. */I/* */O/*========================================================================== */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadwor Ud#else#pragma __nomember_alignment#endiftypedef struct _d_chip {N/* */N/* 801.B000.0800 */N/* */N/* DSC - D-Chip System Configuration Register */N/* */#pragma __nomember_alignment U __union {' unsigned __int64 d_chip$iq_dsc;% unsigned char dsc$b_pad [64]; } d_chip$r_dsc_overlay;N/* */N/* 801.B000.0840 */N/* */N/* STR - D-Chip System Timing Register */N/* U */ __union {' unsigned __int64 d_chip$iq_str;% unsigned char str$b_pad [64]; } d_chip$r_str_overlay;N/* */N/* 801.B000.0880 */N/* */N/* DREV - D-Chip System Configuration Register */N/* U */ __union {( unsigned __int64 d_chip$iq_drev;& unsigned char drev$b_pad [64]; } d_chip$r_drev_overlay;N/* */ } D_CHIP; #if !defined(__VAXC)8#define d_chip$iq_dsc d_chip$r_dsc_overlay.d_chip$iq_dsc8#define d_chip$iq_str d_chip$r_str_overlay.d_chip$iq_str;#define d_chip$iq_drev d_chip$r_drev_overlay.d_chip$iq_drev"#endif /* #if !define Ud(__VAXC) */ N/* */N/* */N/* */O/*========================================================================== */N/* */N/* P-CHIP Structure */N/* U */N/* In the addresses below, x = 1 for PChip-0 and x = 3 for PChip-1 */N/* */O/*========================================================================== */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#end Uiftypedef struct _p_chip {N/* */N/* 80x.8000.0000 */N/* */N/* WSBA0 - P-CHip Window Space Base Address Register 0 */N/* */#pragma __nomember_alignment __union {) unsigned __int64 p_chi Up$iq_wsba0;' unsigned char wsba0$b_pad [64];! } p_chip$r_wsba0_overlay;N/* */N/* 80x.8000.0040 */N/* */N/* WSBA1 - P-CHip Window Space Base Address Register 1 */N/* */ __union {U) unsigned __int64 p_chip$iq_wsba1;' unsigned char wsba1$b_pad [64];! } p_chip$r_wsba1_overlay;N/* */N/* 80x.8000.0080 */N/* */N/* WSBA2 - P-CHip Window Space Base Address Register 2 */N/* U */ __union {) unsigned __int64 p_chip$iq_wsba2;' unsigned char wsba2$b_pad [64];! } p_chip$r_wsba2_overlay;N/* */N/* 80x.8000.00C0 */N/* */N/* WSBA3 - P-CHip Window Space Base Address Register 3 */N/* U */ __union {) unsigned __int64 p_chip$iq_wsba3;' unsigned char wsba3$b_pad [64];! } p_chip$r_wsba3_overlay;N/* */N/* 80x.8000.0100 */N/* */N/* WSM0 - P-Chip Window Space Mask Register 0 */ UN/* */ __union {( unsigned __int64 p_chip$iq_wsm0;& unsigned char wsm0$b_pad [64]; } p_chip$r_wsm0_overlay;N/* */N/* 80x.8000.0140 */N/* */N/* WSM1 - P-Chip Window Space Mask Register 1 U */N/* */ __union {( unsigned __int64 p_chip$iq_wsm1;& unsigned char wsm1$b_pad [64]; } p_chip$r_wsm1_overlay;N/* */N/* 80x.8000.0180 */N/* */N/* WSM2 - P-Chip Window Sp Uace Mask Register 2 */N/* */ __union {( unsigned __int64 p_chip$iq_wsm2;& unsigned char wsm2$b_pad [64]; } p_chip$r_wsm2_overlay;N/* */N/* 80x.8000.01C0 */N/* */N U/* WSM3 - P-Chip Window Space Mask Register 3 */N/* */ __union {( unsigned __int64 p_chip$iq_wsm3;& unsigned char wsm3$b_pad [64]; } p_chip$r_wsm3_overlay;N/* */N/* 80x.8000.0200 */N/* U */N/* TBA0 - P-Chip Translated Base Address Register 0 */N/* */ __union {( unsigned __int64 p_chip$iq_tba0;& unsigned char tba0$b_pad [64]; } p_chip$r_tba0_overlay;N/* */N/* 80x.8000.0240 */N/* U */N/* TBA1 - P-Chip Translated Base Address Register 1 */N/* */ __union {( unsigned __int64 p_chip$iq_tba1;& unsigned char tba1$b_pad [64]; } p_chip$r_tba1_overlay;N/* */N/* 80x.8000.0280 */N/* U */N/* TBA2 - P-Chip Translated Base Address Register 2 */N/* */ __union {( unsigned __int64 p_chip$iq_tba2;& unsigned char tba2$b_pad [64]; } p_chip$r_tba2_overlay;N/* */N/* 80x.8000.02C0 U */N/* */N/* TBA3 - P-Chip Translated Base Address Register 3 */N/* */ __union {( unsigned __int64 p_chip$iq_tba3;& unsigned char tba3$b_pad [64]; } p_chip$r_tba3_overlay;N/* */N/* 80x.8000.0300 U */N/* */N/* PCTL - P-Chip Control Register */N/* */ __union {( unsigned __int64 p_chip$iq_pctl;& unsigned char pctl$b_pad [64]; } p_chip$r_pctl_overlay;N/* */N/* 8 U0x.8000.0340 */N/* */N/* PLAT - P-Chip Master Latency Register */N/* */ __union {( unsigned __int64 p_chip$iq_plat;& unsigned char plat$b_pad [64]; } p_chip$r_plat_overlay;N/* U */N/* 80x.8000.0380 */N/* */N/* P_RESERVED_1 - P-Chip Reserved Register 1 */N/* */ __union {0 unsigned __int64 p_chip$iq_p_reserved_1;. unsigned char p_reserved_1$b_pad [64];( } p_chip$r_p_reserved_1_overlay;N/* U */N/* 80x.8000.03C0 */N/* */N/* PERROR - P-Chip Error Register */N/* */ __union {* unsigned __int64 p_chip$iq_perror;( unsigned char perror$b_pad [64];" } p_ Uchip$r_perror_overlay;N/* */N/* 80x.8000.0400 */N/* */N/* PERRMASK - P-Chip Error Mask Register */N/* */ __union {, unsigned __int64 p_chip$iq_perrmask;* unsigned cha Ur perrmask$b_pad [64];$ } p_chip$r_perrmask_overlay;N/* */N/* 80x.8000.0440 */N/* */N/* PERRSET - P-Chip Error Set Register */N/* */ __union {+ unsigned __int64 p_c Uhip$iq_perrset;) unsigned char perrset$b_pad [64];# } p_chip$r_perrset_overlay;N/* */N/* 80x.8000.0480 */N/* */N/* TLBIV - P-Chip Translation Buffer Invalidate Virtual Register */N/* */ __ !Uunion {) unsigned __int64 p_chip$iq_tlbiv;' unsigned char tlbiv$b_pad [64];! } p_chip$r_tlbiv_overlay;N/* */N/* 80x.8000.04C0 */N/* */N/* TLBIA - P-Chip Translation Buffer Invalidate all Register */N/* "U */ __union {) unsigned __int64 p_chip$iq_tlbia;' unsigned char tlbia$b_pad [64];! } p_chip$r_tlbia_overlay;N/* */N/* 80x.8000.0500 */N/* */N/* PMONCTL - P-Chip Monitor Control Register */N/* #U */ __union {+ unsigned __int64 p_chip$iq_pmonctl;) unsigned char pmonctl$b_pad [64];# } p_chip$r_pmonctl_overlay;N/* */N/* 80x.8000.05C0 */N/* */N/* PMONCNT - P-Chip Monitor Counters Register $U */N/* */ __union {+ unsigned __int64 p_chip$iq_pmoncnt;) unsigned char pmoncnt$b_pad [64];# } p_chip$r_pmoncnt_overlay; } P_CHIP; #if !defined(__VAXC)>#define p_chip$iq_wsba0 p_chip$r_wsba0_overlay.p_chip$iq_wsba0>#define p_chip$iq_wsba1 p_chip$r_wsba1_overlay.p_chip$iq_wsba1>#define p_chip$iq_wsba2 p_chip$r_wsba2_overlay.p_chip$iq_wsba2>#define p_chip$iq_wsba3 p_chip$r %U_wsba3_overlay.p_chip$iq_wsba3;#define p_chip$iq_wsm0 p_chip$r_wsm0_overlay.p_chip$iq_wsm0;#define p_chip$iq_wsm1 p_chip$r_wsm1_overlay.p_chip$iq_wsm1;#define p_chip$iq_wsm2 p_chip$r_wsm2_overlay.p_chip$iq_wsm2;#define p_chip$iq_wsm3 p_chip$r_wsm3_overlay.p_chip$iq_wsm3;#define p_chip$iq_tba0 p_chip$r_tba0_overlay.p_chip$iq_tba0;#define p_chip$iq_tba1 p_chip$r_tba1_overlay.p_chip$iq_tba1;#define p_chip$iq_tba2 p_chip$r_tba2_overlay.p_chip$iq_tba2;#define p_chip$iq_tba3 p_chip$r_tba3_ove&Urlay.p_chip$iq_tba3;#define p_chip$iq_pctl p_chip$r_pctl_overlay.p_chip$iq_pctl;#define p_chip$iq_plat p_chip$r_plat_overlay.p_chip$iq_platS#define p_chip$iq_p_reserved_1 p_chip$r_p_reserved_1_overlay.p_chip$iq_p_reserved_1A#define p_chip$iq_perror p_chip$r_perror_overlay.p_chip$iq_perrorG#define p_chip$iq_perrmask p_chip$r_perrmask_overlay.p_chip$iq_perrmaskD#define p_chip$iq_perrset p_chip$r_perrset_overlay.p_chip$iq_perrset>#define p_chip$iq_tlbiv p_chip$r_tlbiv_overlay.p_chip$iq_tlbiv 'U>#define p_chip$iq_tlbia p_chip$r_tlbia_overlay.p_chip$iq_tlbiaD#define p_chip$iq_pmonctl p_chip$r_pmonctl_overlay.p_chip$iq_pmonctlD#define p_chip$iq_pmoncnt p_chip$r_pmoncnt_overlay.p_chip$iq_pmoncnt"#endif /* #if !defined(__VAXC) */ O/*************************************************************************** */N/* */N/* Bit Definitions for the Tsunami Chip Set Registers */N/* (U */O/*************************************************************************** */O/*========================================================================== */N/* */N/* C-Chip Registers */N/* */O/*====================================== )U==================================== */N/* */N/* */N/* CSC - C-Chip System Configuration Register */N/* */#define CSC$M_BC 0x3#define CSC$M_C0CFP 0x4#define CSC$M_C1CFP 0x8#define CSC$M_SED 0x30#define CSC$M_SFD 0x40#define CSC$M_FW 0x80*U#define CSC$M_AW 0x100#define CSC$M_IDDR 0xE00#define CSC$M_IDDW 0x3000#define CSC$M_P1P 0x4000#define CSC$M_RSVD_0 0x8000#define CSC$M_DWTP 0x30000#define CSC$M_DWFP 0xC0000#define CSC$M_DRTP 0x300000#define CSC$M_RSVD_1 0xC00000#define CSC$M_PME 0x1000000#define CSC$M_QPM 0x2000000#define CSC$M_FET 0xC000000#define CSC$M_QDI 0x70000000#define CSC$M_EFT 0x80000000#define CSC$M_FTI 0x100000000#define CSC$M_B1D 0x200000000#define CSC$M_B2D 0x400000000#defin+Ue CSC$M_B3D 0x800000000"#define CSC$M_TPQMMAX 0x7000000000!#define CSC$M_RSVD_2 0x8000000000##define CSC$M_FPQCMAX 0x70000000000"#define CSC$M_RSVD_3 0x80000000000$#define CSC$M_FPQPMAX 0x700000000000##define CSC$M_RSVD_4 0x800000000000$#define CSC$M_PDTMAX 0x7000000000000$#define CSC$M_RSVD_5 0x8000000000000%#define CSC$M_PRQMAX 0x70000000000000%#define CSC$M_RSVD_6 0x80000000000000&#define CSC$M_PBQMAX 0x700000000000000'#define CSC$M_RSVD_7 0xF800000000000000 c#if !defined(__N,UOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _csc {#pragma __nomember_alignment! unsigned __int64 csc$iq_data; __struct { unsigned int csc$il_l; unsigned int csc$il_h; } csc$r_longwords; __struct {N unsigned csc$v_bc : 2; /* 1:0 Base Configuration */N unsigned csc$v_c0cfp : 1; -U /* 2 CPU 0 Clk Fwd Preset */N unsigned csc$v_c1cfp : 1; /* 3 CPU 1 Clk Fwd Preset */N unsigned csc$v_sed : 2; /* 5:4 SysDC Extract Delay */N unsigned csc$v_sfd : 1; /* 6 SysDC Fill Delay */N unsigned csc$v_fw : 1; /* 7 available for firmware */N unsigned csc$v_aw : 1; /* 8 Array Width */N unsigned csc$v_iddr : 3; /* 11:9 Issue to Data .UDelay on read */X unsigned csc$v_iddw : 2; /* 13:12 Issue to Data Delay for all xactions */N unsigned csc$v_p1p : 1; /* 14 P-Chip 1 present */N unsigned csc$v_rsvd_0 : 1; /* 15 reserved */W unsigned csc$v_dwtp : 2; /* 17:16 Min Dchip Delay from CPU to PAD bus */` unsigned csc$v_dwfp : 2; /* 19:18 Min Dchip Delay from PADbus to CPU or Memory */Z unsigned csc$v_drtp : 2; /* 21:20 M/Uin Dchip Delay from Memory to PAD bus */N unsigned csc$v_rsvd_1 : 2; /* 23:22 reserved */N unsigned csc$v_pme : 1; /* 24 Page Mode Enable */N unsigned csc$v_qpm : 1; /* 25 Que Priority Mode */U unsigned csc$v_fet : 2; /* 27:26 Fill to Extract Turnaround cycles */N unsigned csc$v_qdi : 3; /* 30:28 Que Drain Interval */R unsigned csc$v_eft : 1; /* 31 Extract to0U Fill Turnaround cycles */N/* */N unsigned csc$v_fti : 1; /* 32 Full Throttle Issue */N unsigned csc$v_b1d : 1; /* 33 Bypass 1 Issue Path Disable */N unsigned csc$v_b2d : 1; /* 34 Bypass 2 Issue Path Disable */N unsigned csc$v_b3d : 1; /* 35 Bypass 3 Issue Path Disable */Y unsigned csc$v_tpqmmax : 3; /* 38:36 Max entries in TPQM on D-Chip1Us, mod 8 */N unsigned csc$v_rsvd_2 : 1; /* 39 reserved */N unsigned csc$v_fpqcmax : 3; /* 42:40 Max entries in FQP, mod 8 */N unsigned csc$v_rsvd_3 : 1; /* 43 reserved */N unsigned csc$v_fpqpmax : 3; /* 46:44 Max entries in FPQ, mod 8 */N unsigned csc$v_rsvd_4 : 1; /* 47 reserved */a unsigned csc$v_pdtmax : 3; /* 50:48 Max data xfers to one P-Chip until ack, mod 2U 8 */N unsigned csc$v_rsvd_5 : 1; /* 51 reserved */^ unsigned csc$v_prqmax : 3; /* 54:52 max reqests to one P-Chip until ack, mod 8 */N unsigned csc$v_rsvd_6 : 1; /* 55 reserved */N unsigned csc$v_pbqmax : 3; /* 58:56 Max CPU probe queue */N unsigned csc$v_rsvd_7 : 5; /* 63:59 reserved */ } csc$r_bits; } CSC; #if !defined(__VAXC))#define csc$il_l csc 3U$r_longwords.csc$il_l)#define csc$il_h csc$r_longwords.csc$il_h$#define csc$v_bc csc$r_bits.csc$v_bc*#define csc$v_c0cfp csc$r_bits.csc$v_c0cfp*#define csc$v_c1cfp csc$r_bits.csc$v_c1cfp&#define csc$v_sed csc$r_bits.csc$v_sed&#define csc$v_sfd csc$r_bits.csc$v_sfd$#define csc$v_fw csc$r_bits.csc$v_fw$#define csc$v_aw csc$r_bits.csc$v_aw(#define csc$v_iddr csc$r_bits.csc$v_iddr(#define csc$v_iddw csc$r_bits.csc$v_iddw&#define csc$v_p1p csc$r_bits.csc$v_p1p,#define csc$v_rsvd_0 csc$r_bits.4Ucsc$v_rsvd_0(#define csc$v_dwtp csc$r_bits.csc$v_dwtp(#define csc$v_dwfp csc$r_bits.csc$v_dwfp(#define csc$v_drtp csc$r_bits.csc$v_drtp,#define csc$v_rsvd_1 csc$r_bits.csc$v_rsvd_1&#define csc$v_pme csc$r_bits.csc$v_pme&#define csc$v_qpm csc$r_bits.csc$v_qpm&#define csc$v_fet csc$r_bits.csc$v_fet&#define csc$v_qdi csc$r_bits.csc$v_qdi&#define csc$v_eft csc$r_bits.csc$v_eft&#define csc$v_fti csc$r_bits.csc$v_fti&#define csc$v_b1d csc$r_bits.csc$v_b1d&#define csc$v_b2d csc$r_bits.csc$v_b2d& 5U#define csc$v_b3d csc$r_bits.csc$v_b3d.#define csc$v_tpqmmax csc$r_bits.csc$v_tpqmmax,#define csc$v_rsvd_2 csc$r_bits.csc$v_rsvd_2.#define csc$v_fpqcmax csc$r_bits.csc$v_fpqcmax,#define csc$v_rsvd_3 csc$r_bits.csc$v_rsvd_3.#define csc$v_fpqpmax csc$r_bits.csc$v_fpqpmax,#define csc$v_rsvd_4 csc$r_bits.csc$v_rsvd_4,#define csc$v_pdtmax csc$r_bits.csc$v_pdtmax,#define csc$v_rsvd_5 csc$r_bits.csc$v_rsvd_5,#define csc$v_prqmax csc$r_bits.csc$v_prqmax,#define csc$v_rsvd_6 csc$r_bits.csc$v_rsvd_6, 6U#define csc$v_pbqmax csc$r_bits.csc$v_pbqmax,#define csc$v_rsvd_7 csc$r_bits.csc$v_rsvd_7"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* MTR - C-Chip Memory Timing Register */N/* */#define MTR$M_RCD 0x1#define MTR$M_RSVD_0 0x2#def7Uine MTR$M_CAT 0x4#define MTR$M_RSVD_1 0x8#define MTR$M_IRD 0x70#define MTR$M_RSVD_2 0x80#define MTR$M_RPW 0x300#define MTR$M_RSVD_3 0xC00#define MTR$M_RPT 0x3000#define MTR$M_RSVD_4 0xC000#define MTR$M_RRD 0x10000#define MTR$M_RSVD_5 0xE0000#define MTR$M_MPD 0x100000#define MTR$M_RSVD_6 0xE00000#define MTR$M_RI 0x3F000000#define MTR$M_RSVD_7 0xC0000000#define MTR$M_PHCR 0xF00000000#define MTR$M_PHCW 0xF000000000 #define MTR$M_MPH 0x3F0000000000'#define MTR$M_RS8UVD_8 0xFFFFC00000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _mtr {#pragma __nomember_alignment! unsigned __int64 mtr$iq_data; __struct { unsigned int mtr$il_l; unsigned int mtr$il_h; } mtr$r_longwords; __struct {N unsigned mtr$v_rcd : 1; /* 0 RAS to CAS Delay 9U */N unsigned mtr$v_rsvd_0 : 1; /* 1 reserved */N unsigned mtr$v_cat : 1; /* 2 CAS Access Time */N unsigned mtr$v_rsvd_1 : 1; /* 3 reserved */N unsigned mtr$v_ird : 3; /* 6:4 Issue to RAS Delay */N unsigned mtr$v_rsvd_2 : 1; /* 7 reserved */N unsigned mtr$v_rpw : 2; /* 9:8 Minimum RAS Pulse Width */N unsigned:U mtr$v_rsvd_3 : 2; /* 11:10 reserved */N unsigned mtr$v_rpt : 2; /* 13:12 Min RAS Precharge Time */N unsigned mtr$v_rsvd_4 : 2; /* 15:14 reserved */Z unsigned mtr$v_rrd : 1; /* 16 Min Same-Array_Diff-Bank RAS-to-RAS Delay */N unsigned mtr$v_rsvd_5 : 3; /* 19:17 reserved */N unsigned mtr$v_mpd : 1; /* 20 Mask Pipeline Delay */N unsigned mtr$v_rsvd_6 ;U: 3; /* 23:21 reserved */N unsigned mtr$v_ri : 6; /* 29:24 Refresh Interval */N unsigned mtr$v_rsvd_7 : 2; /* 31:30 reserved */N/* */N unsigned mtr$v_phcr : 4; /* 35:32 Page Hit Cycles for Reads */N unsigned mtr$v_phcw : 4; /* 39:36 Page Hit Cycles for Writes */N unsigned mtr$v_mph : 6; /* 45:40 Max PagUmtr$v_phcw&#define mtr$v_mph mtr$r_bits.mtr$v_mph,#define mtr$v_rsvd_8 mtr$r_bits.mtr$v_rsvd_8"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* MISC - C-Chip Miscellaneous Register */N/* */#define MISC$M_CPUID 0x1#define MISC$M_RSVD_0 ?U0xE#define MISC$M_ITINTR 0x30#define MISC$M_RSVD_1 0xC0#define MISC$M_IPINTR 0x300#define MISC$M_RSVD_2 0xC00#define MISC$M_IPREQ 0x3000#define MISC$M_RSVD_3 0xC000#define MISC$M_ABW 0x30000#define MISC$M_RSVD_4 0xC0000#define MISC$M_ABT 0x300000#define MISC$M_RSVD_5 0xC00000#define MISC$M_ACL 0x1000000#define MISC$M_RSVD_6 0xE000000#define MISC$M_NXM 0x10000000#define MISC$M_NXS 0xE0000000#define MISC$M_REV 0xFF00000000##define MISC$M_DEVSUP 0x30000000000(#d @Uefine MISC$M_RSVD_7 0xFFFFFC0000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _misc {#pragma __nomember_alignment __struct {N unsigned misc$v_cpuid : 1; /* 0 ID of CPU performing the read */N unsigned misc$v_rsvd_0 : 3; /* 3:1 reserved */R unsigned misc$v_itintr : 2; AU/* 5:4 Interval Timer Interrupt pending */N unsigned misc$v_rsvd_1 : 2; /* 7:6 reserved */R unsigned misc$v_ipintr : 2; /* 9:8 Interprocessor Interrupt pending */N unsigned misc$v_rsvd_2 : 2; /* 11:10 reserved */T unsigned misc$v_ipreq : 2; /* 13:12 Interprocessor Interrupt Request */N unsigned misc$v_rsvd_3 : 2; /* 15:14 reserved */N unsigned misc$v_abw : 2; /* 17:16 ArbBUitration Won */N unsigned misc$v_rsvd_4 : 2; /* 19:18 reserved */N unsigned misc$v_abt : 2; /* 21:20 Arbitration Try */N unsigned misc$v_rsvd_5 : 2; /* 23:22 reserved */N unsigned misc$v_acl : 1; /* 24 Arbitration Clear */N unsigned misc$v_rsvd_6 : 3; /* 27:25 reserved */N unsigned misc$v_nxm : 1; /* 28 Non eXistent Memory */ CUN unsigned misc$v_nxs : 3; /* 31:29 NXM Source */N/* */N unsigned misc$v_rev : 8; /* 39:32 C-Chip Revision */N unsigned misc$v_devsup : 2; /* 41:40 Suppress IRQ[1] */N unsigned misc$v_rsvd_7 : 22; /* 63:42 reserved */ } misc$r_bits; } MISC; #if !defined(__VAXC)-#define misc$v_cpuid misc$r_bits.misc$v_ DUcpuid/#define misc$v_rsvd_0 misc$r_bits.misc$v_rsvd_0/#define misc$v_itintr misc$r_bits.misc$v_itintr/#define misc$v_rsvd_1 misc$r_bits.misc$v_rsvd_1/#define misc$v_ipintr misc$r_bits.misc$v_ipintr/#define misc$v_rsvd_2 misc$r_bits.misc$v_rsvd_2-#define misc$v_ipreq misc$r_bits.misc$v_ipreq/#define misc$v_rsvd_3 misc$r_bits.misc$v_rsvd_3)#define misc$v_abw misc$r_bits.misc$v_abw/#define misc$v_rsvd_4 misc$r_bits.misc$v_rsvd_4)#define misc$v_abt misc$r_bits.misc$v_abt/#define misc EU$v_rsvd_5 misc$r_bits.misc$v_rsvd_5)#define misc$v_acl misc$r_bits.misc$v_acl/#define misc$v_rsvd_6 misc$r_bits.misc$v_rsvd_6)#define misc$v_nxm misc$r_bits.misc$v_nxm)#define misc$v_nxs misc$r_bits.misc$v_nxs)#define misc$v_rev misc$r_bits.misc$v_rev/#define misc$v_devsup misc$r_bits.misc$v_devsup/#define misc$v_rsvd_7 misc$r_bits.misc$v_rsvd_7"#endif /* #if !defined(__VAXC) */ N/* */N/* FU */N/* MPD - C-Chip Memory Presence Detect */N/* */#define MPD$M_CKS 0x1#define MPD$M_DS 0x2#define MPD$M_CKR 0x4#define MPD$M_DR 0x8#define MPD$M_RSVD_0 0xFFFFFFF0'#define MPD$M_RSVD_1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nome GUmber_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _mpd {#pragma __nomember_alignment __struct {N unsigned mpd$v_cks : 1; /* 0 ClocK Send */N unsigned mpd$v_ds : 1; /* 1 Data Send */N unsigned mpd$v_ckr : 1; /* 2 ClocK Receive */N unsigned mpd$v_dr : 1; /* 3 Data Receive */N unsigned mpd$v_rsvd_0 : 28; /* HU 31:4 reserved */N/* */N unsigned mpd$v_rsvd_1 : 32; /* 63:32 reserved */ } mpd$r_bits; } MPD; #if !defined(__VAXC)&#define mpd$v_cks mpd$r_bits.mpd$v_cks$#define mpd$v_ds mpd$r_bits.mpd$v_ds&#define mpd$v_ckr mpd$r_bits.mpd$v_ckr$#define mpd$v_dr mpd$r_bits.mpd$v_dr,#define mpd$v_rsvd_0 mpd$r_bits.mpd$v_rsvd_0,#define mpd$v_rsvd_1 mpd$r_bits.mpd$v_rsvd_1 IU"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* AAR - C-Chip Array Address Register */N/* */#define AAR$M_BNKS 0x1#define AAR$M_RSVD_0 0x2#define AAR$M_ROWS 0xC#define AAR$M_RSVD_1 0xF0#define AAR$M_SA 0x100#define AAR$M_RSVDJU_2 0xE00#define AAR$M_ASIZ 0x7000#define AAR$M_RSVD_3 0x8000#define AAR$M_DBG 0x10000#define AAR$M_RSVD_4 0xFE0000#define AAR$M_ADDR 0xFF000000'#define AAR$M_RSVD_5 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _aar {#pragma __nomember_alignment! unsigned __int64 aar$iq_data; __struct { KU unsigned int aar$il_l; unsigned int aar$il_h; } aar$r_longwords; __struct {N unsigned aar$v_bnks : 1; /* 0 Number of Bank bits in DRAMs */N unsigned aar$v_rsvd_0 : 1; /* 1 reserved */N unsigned aar$v_rows : 2; /* 2 Number of Row bits in DRAMS */N unsigned aar$v_rsvd_1 : 4; /* 7:4 reserved */N unsigned aar$v_sa : 1; /* 8 Split Array */NLU unsigned aar$v_rsvd_2 : 3; /* 11:9 reserved */N unsigned aar$v_asiz : 3; /* 14:12 Array Size */N unsigned aar$v_rsvd_3 : 1; /* 15 reserved */^ unsigned aar$v_dbg : 1; /* 16 Enables this memory port as a debug interface */N unsigned aar$v_rsvd_4 : 7; /* 23:17 reserved */N unsigned aar$v_addr : 8; /* 31:24 Base Address */N unMUsigned aar$v_rsvd_5 : 32; /* 63:32 reserved */ } aar$r_bits; } AAR; #if !defined(__VAXC))#define aar$il_l aar$r_longwords.aar$il_l)#define aar$il_h aar$r_longwords.aar$il_h(#define aar$v_bnks aar$r_bits.aar$v_bnks,#define aar$v_rsvd_0 aar$r_bits.aar$v_rsvd_0(#define aar$v_rows aar$r_bits.aar$v_rows,#define aar$v_rsvd_1 aar$r_bits.aar$v_rsvd_1$#define aar$v_sa aar$r_bits.aar$v_sa,#define aar$v_rsvd_2 aar$r_bits.aar$v_rsvd_2(#define aar$v_asiz aar$r_b NUits.aar$v_asiz,#define aar$v_rsvd_3 aar$r_bits.aar$v_rsvd_3&#define aar$v_dbg aar$r_bits.aar$v_dbg,#define aar$v_rsvd_4 aar$r_bits.aar$v_rsvd_4(#define aar$v_addr aar$r_bits.aar$v_addr,#define aar$v_rsvd_5 aar$r_bits.aar$v_rsvd_5"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* DIM - C-Chip Device Interrupt Mask Registers OU */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _dim {#pragma __nomember_alignment! unsigned __int64 dim$iq_data; __struct { unsigned int dim$il_l; unsigned int dim$il_h; } dim$r_longwords; } DIM; #if !def PUined(__VAXC))#define dim$il_l dim$r_longwords.dim$il_l)#define dim$il_h dim$r_longwords.dim$il_h"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* DIR - C-Chip Device Interrupt Request Registers */N/* */#define CDIR$M_DEV_L 0xFFFFFFFF%#define CDQUIR$M_DEV_H 0xFFFFFF00000000'#define CDIR$M_RSVD_0 0x300000000000000%#define CDIR$M_ERR 0xFC00000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _dir {#pragma __nomember_alignment" unsigned __int64 cdir$iq_data; __struct { unsigned int cdir$il_l; unsigned int cdir$il_h; } cdir$r_longwords RU; __struct {Q unsigned cdir$v_dev_l : 32; /* 31:0 IRQ[1] PCI Interrupts Pending */Q unsigned cdir$v_dev_h : 24; /* 55:32 IRQ[1] PCI Interrupts Pending */N unsigned cdir$v_rsvd_0 : 2; /* 57:56 reserved */N unsigned cdir$v_err : 6; /* 63:58 IRQ[0] Error Interrupts */ } cdir$r_bits; } DIR; #if !defined(__VAXC),#define cdir$il_l cdir$r_longwords.cdir$il_l,#define cdir$il_h cdir$r_longwords.cdir$il_h-#d SUefine cdir$v_dev_l cdir$r_bits.cdir$v_dev_l-#define cdir$v_dev_h cdir$r_bits.cdir$v_dev_h/#define cdir$v_rsvd_0 cdir$r_bits.cdir$v_rsvd_0)#define cdir$v_err cdir$r_bits.cdir$v_err"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* DRIR - C-Chip Raw Interrupt Request Register */N/* TU */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _drir {#pragma __nomember_alignment" unsigned __int64 drir$iq_data; __struct { unsigned int drir$il_l; unsigned int drir$il_h; } drir$r_longwords; } DRIR; #if !defined(__VAXC),#define drir$il_l drir$r UU_longwords.drir$il_l,#define drir$il_h drir$r_longwords.drir$il_h"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* PRBEN - C-Chip Probe Enable Register */N/* */#define PRBEN$M_PRBEN 0x1!#define PRBEN$M_RSVD_0 0xFFFFFFFE)#define PRBEN$VUM_RSVD_1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _prben {#pragma __nomember_alignment# unsigned __int64 prben$iq_data; __struct { unsigned int prben$il_l; unsigned int prben$il_h; } prben$r_longwords; __struct {N unsigned prben$v_prben : 1; /* 0 Probe Enabl WUe bit */N unsigned prben$v_rsvd_0 : 31; /* 31:1 Reserved */N unsigned prben$v_rsvd_1 : 32; /* 63:32 Reserved */ } prben$r_bits; } PRBEN; #if !defined(__VAXC)/#define prben$il_l prben$r_longwords.prben$il_l/#define prben$il_h prben$r_longwords.prben$il_h0#define prben$v_prben prben$r_bits.prben$v_prben2#define prben$v_rsvd_0 prben$r_bits.prben$v_rsvd_02#define prben$v_rsvd_1 prben$r_bits.prben$v_rsvd_1"#e XUndif /* #if !defined(__VAXC) */ N/* */N/* */N/* IIC - C-Chip Interval Ignore Count Registers */N/* */#define IIC$M_ICNT 0xFFFFFF#define IIC$M_OF 0x1000000#define IIC$M_RSVD_0 0xFE000000'#define IIC$M_RSVD_1 0xFFFFFFFF00000000 c#if !definYUed(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _iic {#pragma __nomember_alignment! unsigned __int64 iic$iq_data; __struct { unsigned int iic$il_l; unsigned int iic$il_h; } iic$r_longwords; __struct {Z unsigned iic$v_icnt : 24; /* 23:0 Count of remaining interrupts to ignore */N unsigned i ZUic$v_of : 1; /* 24 Overflow bit */N unsigned iic$v_rsvd_0 : 7; /* 31:25 reserved */N unsigned iic$v_rsvd_1 : 32; /* 63:32 reserved */ } iic$r_bits; } IIC; #if !defined(__VAXC))#define iic$il_l iic$r_longwords.iic$il_l)#define iic$il_h iic$r_longwords.iic$il_h(#define iic$v_icnt iic$r_bits.iic$v_icnt$#define iic$v_of iic$r_bits.iic$v_of,#define iic$v_rsvd_0 iic$r_bits.iic$v_rsvd_0,#define [Uiic$v_rsvd_1 iic$r_bits.iic$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* MPR - C-Chip Memory Programming Registers */N/* */#define MPR$M_MPRDAT 0x1FFF#define MPR$M_RSVD_0 0xFFFFE000'#define MPR$M_RSVD_1 0xFFFFFFFF00000000 \Uc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _mpr {#pragma __nomember_alignment! unsigned __int64 mpr$iq_data; __struct { unsigned int mpr$il_l; unsigned int mpr$il_h; } mpr$r_longwords; __struct {[ unsigned mpr$v_mprdat : 13; /* 12:0 Data to be written on address lines 12:0 */N ]U unsigned mpr$v_rsvd_0 : 19; /* 31:13 reserved */N unsigned mpr$v_rsvd_1 : 32; /* 63:32 reserved */ } mpr$r_bits; } MPR; #if !defined(__VAXC))#define mpr$il_l mpr$r_longwords.mpr$il_l)#define mpr$il_h mpr$r_longwords.mpr$il_h,#define mpr$v_mprdat mpr$r_bits.mpr$v_mprdat,#define mpr$v_rsvd_0 mpr$r_bits.mpr$v_rsvd_0,#define mpr$v_rsvd_1 mpr$r_bits.mpr$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* ^U */N/* */N/* MCTL - C-Chip M-Port Control Register */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _U_mctl {#pragma __nomember_alignment" unsigned __int64 mctl$iq_data; __struct { unsigned int mctl$il_l; unsigned int mctl$il_h; } mctl$r_longwords; } MCTL; #if !defined(__VAXC),#define mctl$il_l mctl$r_longwords.mctl$il_l,#define mctl$il_h mctl$r_longwords.mctl$il_h"#endif /* #if !defined(__VAXC) */ N/* */N/* `U */N/* TTR - C-Chip TIG Bus Timing Register */N/* */#define TTR$M_AS 0x1#define TTR$M_AH 0x2#define TTR$M_RSVD_0 0xC#define TTR$M_IS 0x30#define TTR$M_RSVD_1 0xC0#define TTR$M_IRT 0x300#define TTR$M_RSVD_2 0xC00#define TTR$M_ID 0x7000#define TTR$M_RSVD_3 0xFFFF8000'#define TTR$M_RSVD_4 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defin aUed(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _ttr {#pragma __nomember_alignment __struct {\ unsigned ttr$v_as : 1; /* 0 Address Setup to the address latch before AS */Q unsigned ttr$v_ah : 1; /* 1 Address Hold after AS before CS_L */N unsigned ttr$v_rsvd_0 : 2; /* 3:2 reserved */N unsigned ttr$v_is : 2; bU /* 5:4 Interrupt Setup time */N unsigned ttr$v_rsvd_1 : 2; /* 7:6 reserved */N unsigned ttr$v_irt : 2; /* 9:8 Interrupt Read Time */N unsigned ttr$v_rsvd_2 : 2; /* 11:10 reserved */N unsigned ttr$v_id : 3; /* 14:12 Interrupt starting Device */N unsigned ttr$v_rsvd_3 : 17; /* 31:15 reserved */N unsigned ttr$v_rsvd_4 : 32; /* 63:32 reserved cU */ } ttr$r_bits; } TTR; #if !defined(__VAXC)$#define ttr$v_as ttr$r_bits.ttr$v_as$#define ttr$v_ah ttr$r_bits.ttr$v_ah,#define ttr$v_rsvd_0 ttr$r_bits.ttr$v_rsvd_0$#define ttr$v_is ttr$r_bits.ttr$v_is,#define ttr$v_rsvd_1 ttr$r_bits.ttr$v_rsvd_1&#define ttr$v_irt ttr$r_bits.ttr$v_irt,#define ttr$v_rsvd_2 ttr$r_bits.ttr$v_rsvd_2$#define ttr$v_id ttr$r_bits.ttr$v_id,#define ttr$v_rsvd_3 ttr$r_bits.ttr$v_rsvd_3,#define ttr$v_rsvd_4 ttr$r_bits.ttr$v_rsvd_4"#e dUndif /* #if !defined(__VAXC) */ N/* */N/* */N/* TDR - C-Chip TIG Bus Device Timing Register */N/* */#define TDR$M_RA0 0xF#define TDR$M_RD0 0x70#define TDR$M_RSVD_0 0x80#define TDR$M_WS0 0x300#define TDR$M_RSVD_1 0xC00#define TDR$M_WP0 eU0x7000#define TDR$M_WH0 0x8000#define TDR$M_RA1 0xF0000#define TDR$M_RD1 0x700000#define TDR$M_RSVD_2 0x800000#define TDR$M_WS1 0x3000000#define TDR$M_RSVD_3 0xC000000#define TDR$M_WP1 0x70000000#define TDR$M_WH1 0x80000000#define TDR$M_RA2 0xF00000000#define TDR$M_RD2 0x7000000000!#define TDR$M_RSVD_4 0x8000000000#define TDR$M_WS2 0x30000000000"#define TDR$M_RSVD_5 0xC0000000000 #define TDR$M_WP2 0x700000000000 #define TDR$M_WH2 0x800000000000!#define TDR$M_RA3 0xF000fU000000000"#define TDR$M_RD3 0x70000000000000%#define TDR$M_RSVD_6 0x80000000000000##define TDR$M_WS3 0x300000000000000&#define TDR$M_RSVD_7 0xC00000000000000$#define TDR$M_WP3 0x7000000000000000$#define TDR$M_WH3 0x8000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _tdr {#pragma __nomember_alignment! unsigned __int gU64 tdr$iq_data; __struct { unsigned int tdr$il_l; unsigned int tdr$il_h; } tdr$r_longwords; __struct {N unsigned tdr$v_ra0 : 4; /* 3:0 Read Access time */N unsigned tdr$v_rd0 : 3; /* 6:4 Read output Disable time */N unsigned tdr$v_rsvd_0 : 1; /* 7 reserved */N unsigned tdr$v_ws0 : 2; /* 9:8 Write Setup time */N unsigned tdr$v_rsvd_1 : 2; hU/* 11:10 reserved */N unsigned tdr$v_wp0 : 3; /* 14:12 Write Pulse width */N unsigned tdr$v_wh0 : 1; /* 15 Write Hold time */N/* */N unsigned tdr$v_ra1 : 4; /* 19:16 Read Access time */N unsigned tdr$v_rd1 : 3; /* 22:20 Read output Disable time */N unsigned tdr$v_rsvd_2 : 1; /* 23 reserved iU */N unsigned tdr$v_ws1 : 2; /* 25:24 Write Setup time */N unsigned tdr$v_rsvd_3 : 2; /* 27:26 reserved */N unsigned tdr$v_wp1 : 3; /* 30:28 Write Pulse width */N unsigned tdr$v_wh1 : 1; /* 31 Write Hold time */N/* */N unsigned tdr$v_ra2 : 4; /* 35:32 Read Access time */N unsijUgned tdr$v_rd2 : 3; /* 38:36 Read output Disable time */N unsigned tdr$v_rsvd_4 : 1; /* 39 reserved */N unsigned tdr$v_ws2 : 2; /* 41:40 Write Setup time */N unsigned tdr$v_rsvd_5 : 2; /* 43:42 reserved */N unsigned tdr$v_wp2 : 3; /* 46:44 Write Pulse width */N unsigned tdr$v_wh2 : 1; /* 47 Write Hold time */N/* kU */N unsigned tdr$v_ra3 : 4; /* 51:48 Read Access time */N unsigned tdr$v_rd3 : 3; /* 54:52 Read output Disable time */N unsigned tdr$v_rsvd_6 : 1; /* 55 reserved */N unsigned tdr$v_ws3 : 2; /* 57:56 Write Setup time */N unsigned tdr$v_rsvd_7 : 2; /* 59:58 reserved */N unsigned tdr$v_wp3 : 3; /* 62:60 Write Pulse widlUth */N unsigned tdr$v_wh3 : 1; /* 63 Write Hold time */ } tdr$r_bits; } TDR; #if !defined(__VAXC))#define tdr$il_l tdr$r_longwords.tdr$il_l)#define tdr$il_h tdr$r_longwords.tdr$il_h&#define tdr$v_ra0 tdr$r_bits.tdr$v_ra0&#define tdr$v_rd0 tdr$r_bits.tdr$v_rd0,#define tdr$v_rsvd_0 tdr$r_bits.tdr$v_rsvd_0&#define tdr$v_ws0 tdr$r_bits.tdr$v_ws0,#define tdr$v_rsvd_1 tdr$r_bits.tdr$v_rsvd_1&#define tdr$v_wp0 tdr$r_bits.tdr$v_wp0&#define mUtdr$v_wh0 tdr$r_bits.tdr$v_wh0&#define tdr$v_ra1 tdr$r_bits.tdr$v_ra1&#define tdr$v_rd1 tdr$r_bits.tdr$v_rd1,#define tdr$v_rsvd_2 tdr$r_bits.tdr$v_rsvd_2&#define tdr$v_ws1 tdr$r_bits.tdr$v_ws1,#define tdr$v_rsvd_3 tdr$r_bits.tdr$v_rsvd_3&#define tdr$v_wp1 tdr$r_bits.tdr$v_wp1&#define tdr$v_wh1 tdr$r_bits.tdr$v_wh1&#define tdr$v_ra2 tdr$r_bits.tdr$v_ra2&#define tdr$v_rd2 tdr$r_bits.tdr$v_rd2,#define tdr$v_rsvd_4 tdr$r_bits.tdr$v_rsvd_4&#define tdr$v_ws2 tdr$r_bits.tdr$v_ws2,#define tdr$v_rs nUvd_5 tdr$r_bits.tdr$v_rsvd_5&#define tdr$v_wp2 tdr$r_bits.tdr$v_wp2&#define tdr$v_wh2 tdr$r_bits.tdr$v_wh2&#define tdr$v_ra3 tdr$r_bits.tdr$v_ra3&#define tdr$v_rd3 tdr$r_bits.tdr$v_rd3,#define tdr$v_rsvd_6 tdr$r_bits.tdr$v_rsvd_6&#define tdr$v_ws3 tdr$r_bits.tdr$v_ws3,#define tdr$v_rsvd_7 tdr$r_bits.tdr$v_rsvd_7&#define tdr$v_wp3 tdr$r_bits.tdr$v_wp3&#define tdr$v_wh3 tdr$r_bits.tdr$v_wh3"#endif /* #if !defined(__VAXC) */ O/*==============================================================oU============ */N/* */N/* D-Chip Registers */N/* */O/*========================================================================== */N/* */N/* */N/* DSCpU - D-Chip System Configuration Register */N/* */#define DSC$M_BC 0x3#define DSC$M_C0CFP 0x4#define DSC$M_C1CFP 0x8#define DSC$M_C2CFP 0x10#define DSC$M_C3CFP 0x20#define DSC$M_P1P 0x40#define DSC$M_RSVD_0 0x80#define DSC$M_BC1 0x300#define DSC$M_C0CFP1 0x400#define DSC$M_C1CFP1 0x800#define DSC$M_C2CFP1 0x1000#define DSC$M_C3CFP1 0x2000#define DSC$M_P1P1 0x4000#defqUine DSC$M_RSVD_1 0x8000#define DSC$M_BC2 0x30000#define DSC$M_C0CFP2 0x40000#define DSC$M_C1CFP2 0x80000#define DSC$M_C2CFP2 0x100000#define DSC$M_C3CFP2 0x200000#define DSC$M_P1P2 0x400000#define DSC$M_RSVD_2 0x800000#define DSC$M_BC3 0x3000000#define DSC$M_C0CFP3 0x4000000#define DSC$M_C1CFP3 0x8000000#define DSC$M_C2CFP3 0x10000000#define DSC$M_C3CFP3 0x20000000#define DSC$M_P1P3 0x40000000#define DSC$M_RSVD_3 0x80000000#define DSC$M_BC4 0x300000000 #definrUe DSC$M_C0CFP4 0x400000000 #define DSC$M_C1CFP4 0x800000000!#define DSC$M_C2CFP4 0x1000000000!#define DSC$M_C3CFP4 0x2000000000#define DSC$M_P1P4 0x4000000000!#define DSC$M_RSVD_4 0x8000000000 #define DSC$M_BC15 0x30000000000"#define DSC$M_C0CFP5 0x40000000000"#define DSC$M_C1CFP5 0x80000000000##define DSC$M_C2CFP5 0x100000000000##define DSC$M_C3CFP5 0x200000000000!#define DSC$M_P1P5 0x400000000000##define DSC$M_RSVD_5 0x800000000000!#define DSC$M_BC6 0x3000000000000$#define DS sUC$M_C0CFP6 0x4000000000000$#define DSC$M_C1CFP6 0x8000000000000%#define DSC$M_C2CFP6 0x10000000000000%#define DSC$M_C3CFP6 0x20000000000000##define DSC$M_P1P6 0x40000000000000%#define DSC$M_RSVD_6 0x80000000000000##define DSC$M_BC7 0x300000000000000&#define DSC$M_C0CFP7 0x400000000000000&#define DSC$M_C1CFP7 0x800000000000000'#define DSC$M_C2CFP7 0x1000000000000000'#define DSC$M_C3CFP7 0x2000000000000000%#define DSC$M_P1P7 0x4000000000000000'#define DSC$M_RSVD_7 0x8000000000000000tU c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _dsc {#pragma __nomember_alignment! unsigned __int64 dsc$iq_data; __struct { unsigned int dsc$il_l; unsigned int dsc$il_h; } dsc$r_longwords; __struct {N unsigned dsc$v_bc : 2; /* 1:0 Base Configuration */N unsignuUed dsc$v_c0cfp : 1; /* 2 CPU 0 Clock Forward Preset */N unsigned dsc$v_c1cfp : 1; /* 3 CPU 0 Clock Forward Preset */N unsigned dsc$v_c2cfp : 1; /* 4 CPU 0 Clock Forward Preset */N unsigned dsc$v_c3cfp : 1; /* 5 CPU 0 Clock Forward Preset */N unsigned dsc$v_p1p : 1; /* 6 P-Chip_1 Preset */N unsigned dsc$v_rsvd_0 : 1; /* 7 reserved */N/* vU */N unsigned dsc$v_bc1 : 2; /* 9:8 Base Configuration */N unsigned dsc$v_c0cfp1 : 1; /* 10 CPU 0 Clock Forward Preset */N unsigned dsc$v_c1cfp1 : 1; /* 11 CPU 0 Clock Forward Preset */N unsigned dsc$v_c2cfp1 : 1; /* 12 CPU 0 Clock Forward Preset */N unsigned dsc$v_c3cfp1 : 1; /* 13 CPU 0 Clock Forward Preset */N unsigned dsc$v_p1p1 : 1; /* 14 P-Chip_1 Preset wU */N unsigned dsc$v_rsvd_1 : 1; /* 15 reserved */N/* */N unsigned dsc$v_bc2 : 2; /* 17:16 Base Configuration */N unsigned dsc$v_c0cfp2 : 1; /* 18 CPU 0 Clock Forward Preset */N unsigned dsc$v_c1cfp2 : 1; /* 19 CPU 0 Clock Forward Preset */N unsigned dsc$v_c2cfp2 : 1; /* 20 CPU 0 Clock Forward Preset */N unsixUgned dsc$v_c3cfp2 : 1; /* 21 CPU 0 Clock Forward Preset */N unsigned dsc$v_p1p2 : 1; /* 22 P-Chip_1 Preset */N unsigned dsc$v_rsvd_2 : 1; /* 23 reserved */N/* */N unsigned dsc$v_bc3 : 2; /* 25:24 Base Configuration */N unsigned dsc$v_c0cfp3 : 1; /* 26 CPU 0 Clock Forward Preset */N unsigned dsc$v_c1cfp3 : 1; yU /* 27 CPU 0 Clock Forward Preset */N unsigned dsc$v_c2cfp3 : 1; /* 28 CPU 0 Clock Forward Preset */N unsigned dsc$v_c3cfp3 : 1; /* 29 CPU 0 Clock Forward Preset */N unsigned dsc$v_p1p3 : 1; /* 30 P-Chip_1 Preset */N unsigned dsc$v_rsvd_3 : 1; /* 31 reserved */N/* */N unsigned dsc$v_bc4 : 2; /* 33:32 Base ConfiguratzUion */N unsigned dsc$v_c0cfp4 : 1; /* 34 CPU 0 Clock Forward Preset */N unsigned dsc$v_c1cfp4 : 1; /* 35 CPU 0 Clock Forward Preset */N unsigned dsc$v_c2cfp4 : 1; /* 36 CPU 0 Clock Forward Preset */N unsigned dsc$v_c3cfp4 : 1; /* 37 CPU 0 Clock Forward Preset */N unsigned dsc$v_p1p4 : 1; /* 38 P-Chip_1 Preset */N unsigned dsc$v_rsvd_4 : 1; /* 39 reserved */N/* {U */N unsigned dsc$v_bc15 : 2; /* 41:40 Base Configuration */N unsigned dsc$v_c0cfp5 : 1; /* 42 CPU 0 Clock Forward Preset */N unsigned dsc$v_c1cfp5 : 1; /* 43 CPU 0 Clock Forward Preset */N unsigned dsc$v_c2cfp5 : 1; /* 44 CPU 0 Clock Forward Preset */N unsigned dsc$v_c3cfp5 : 1; /* 45 CPU 0 Clock Forward Preset */N unsigned dsc$v_p1p5 : 1; |U /* 46 P-Chip_1 Preset */N unsigned dsc$v_rsvd_5 : 1; /* 47 reserved */N/* */N unsigned dsc$v_bc6 : 2; /* 49:48 Base Configuration */N unsigned dsc$v_c0cfp6 : 1; /* 50 CPU 0 Clock Forward Preset */N unsigned dsc$v_c1cfp6 : 1; /* 51 CPU 0 Clock Forward Preset */N unsigned dsc$v_c2cfp6 : 1; /* 52 CPU 0 Clock Forw}Uard Preset */N unsigned dsc$v_c3cfp6 : 1; /* 53 CPU 0 Clock Forward Preset */N unsigned dsc$v_p1p6 : 1; /* 54 P-Chip_1 Preset */N unsigned dsc$v_rsvd_6 : 1; /* 55 reserved */N/* */N unsigned dsc$v_bc7 : 2; /* 57:56 Base Configuration */N unsigned dsc$v_c0cfp7 : 1; /* 58 CPU 0 Clock Forward Preset */N ~Uunsigned dsc$v_c1cfp7 : 1; /* 59 CPU 0 Clock Forward Preset */N unsigned dsc$v_c2cfp7 : 1; /* 60 CPU 0 Clock Forward Preset */N unsigned dsc$v_c3cfp7 : 1; /* 61 CPU 0 Clock Forward Preset */N unsigned dsc$v_p1p7 : 1; /* 62 P-Chip_1 Preset */N unsigned dsc$v_rsvd_7 : 1; /* 63 reserved */ } dsc$r_bits; } DSC; #if !defined(__VAXC))#define dsc$il_l dsc$r_longwords.dsc$il_l)#define Udsc$il_h dsc$r_longwords.dsc$il_h$#define dsc$v_bc dsc$r_bits.dsc$v_bc*#define dsc$v_c0cfp dsc$r_bits.dsc$v_c0cfp*#define dsc$v_c1cfp dsc$r_bits.dsc$v_c1cfp*#define dsc$v_c2cfp dsc$r_bits.dsc$v_c2cfp*#define dsc$v_c3cfp dsc$r_bits.dsc$v_c3cfp&#define dsc$v_p1p dsc$r_bits.dsc$v_p1p,#define dsc$v_rsvd_0 dsc$r_bits.dsc$v_rsvd_0&#define dsc$v_bc1 dsc$r_bits.dsc$v_bc1,#define dsc$v_c0cfp1 dsc$r_bits.dsc$v_c0cfp1,#define dsc$v_c1cfp1 dsc$r_bits.dsc$v_c1cfp1,#define dsc$v_c2cfp1 dsc$r_bits.dsc$v_ Uc2cfp1,#define dsc$v_c3cfp1 dsc$r_bits.dsc$v_c3cfp1(#define dsc$v_p1p1 dsc$r_bits.dsc$v_p1p1,#define dsc$v_rsvd_1 dsc$r_bits.dsc$v_rsvd_1&#define dsc$v_bc2 dsc$r_bits.dsc$v_bc2,#define dsc$v_c0cfp2 dsc$r_bits.dsc$v_c0cfp2,#define dsc$v_c1cfp2 dsc$r_bits.dsc$v_c1cfp2,#define dsc$v_c2cfp2 dsc$r_bits.dsc$v_c2cfp2,#define dsc$v_c3cfp2 dsc$r_bits.dsc$v_c3cfp2(#define dsc$v_p1p2 dsc$r_bits.dsc$v_p1p2,#define dsc$v_rsvd_2 dsc$r_bits.dsc$v_rsvd_2&#define dsc$v_bc3 dsc$r_bits.dsc$v_bc3,#define dsc$ Uv_c0cfp3 dsc$r_bits.dsc$v_c0cfp3,#define dsc$v_c1cfp3 dsc$r_bits.dsc$v_c1cfp3,#define dsc$v_c2cfp3 dsc$r_bits.dsc$v_c2cfp3,#define dsc$v_c3cfp3 dsc$r_bits.dsc$v_c3cfp3(#define dsc$v_p1p3 dsc$r_bits.dsc$v_p1p3,#define dsc$v_rsvd_3 dsc$r_bits.dsc$v_rsvd_3&#define dsc$v_bc4 dsc$r_bits.dsc$v_bc4,#define dsc$v_c0cfp4 dsc$r_bits.dsc$v_c0cfp4,#define dsc$v_c1cfp4 dsc$r_bits.dsc$v_c1cfp4,#define dsc$v_c2cfp4 dsc$r_bits.dsc$v_c2cfp4,#define dsc$v_c3cfp4 dsc$r_bits.dsc$v_c3cfp4(#define dsc$v_p1p4 dsc U$r_bits.dsc$v_p1p4,#define dsc$v_rsvd_4 dsc$r_bits.dsc$v_rsvd_4(#define dsc$v_bc15 dsc$r_bits.dsc$v_bc15,#define dsc$v_c0cfp5 dsc$r_bits.dsc$v_c0cfp5,#define dsc$v_c1cfp5 dsc$r_bits.dsc$v_c1cfp5,#define dsc$v_c2cfp5 dsc$r_bits.dsc$v_c2cfp5,#define dsc$v_c3cfp5 dsc$r_bits.dsc$v_c3cfp5(#define dsc$v_p1p5 dsc$r_bits.dsc$v_p1p5,#define dsc$v_rsvd_5 dsc$r_bits.dsc$v_rsvd_5&#define dsc$v_bc6 dsc$r_bits.dsc$v_bc6,#define dsc$v_c0cfp6 dsc$r_bits.dsc$v_c0cfp6,#define dsc$v_c1cfp6 dsc$r_bits.dsc$v_c1 Ucfp6,#define dsc$v_c2cfp6 dsc$r_bits.dsc$v_c2cfp6,#define dsc$v_c3cfp6 dsc$r_bits.dsc$v_c3cfp6(#define dsc$v_p1p6 dsc$r_bits.dsc$v_p1p6,#define dsc$v_rsvd_6 dsc$r_bits.dsc$v_rsvd_6&#define dsc$v_bc7 dsc$r_bits.dsc$v_bc7,#define dsc$v_c0cfp7 dsc$r_bits.dsc$v_c0cfp7,#define dsc$v_c1cfp7 dsc$r_bits.dsc$v_c1cfp7,#define dsc$v_c2cfp7 dsc$r_bits.dsc$v_c2cfp7,#define dsc$v_c3cfp7 dsc$r_bits.dsc$v_c3cfp7(#define dsc$v_p1p7 dsc$r_bits.dsc$v_p1p7,#define dsc$v_rsvd_7 dsc$r_bits.dsc$v_rsvd_7"#endif U/* #if !defined(__VAXC) */ N/* */N/* */N/* STR - D-Chip System Timing Register */N/* */#define STR$M_AW 0x1#define STR$M_IDDR 0xE#define STR$M_IDDW 0x30#define STR$M_RSVD_0 0xC0#define STR$M_AW1 0x100#define STR$M_IDDR1 0xE00U#define STR$M_IDDW1 0x3000#define STR$M_RSVD_1 0xC000#define STR$M_AW2 0x10000#define STR$M_IDDR2 0xE0000#define STR$M_IDDW2 0x300000#define STR$M_RSVD_2 0xC00000#define STR$M_AW3 0x1000000#define STR$M_IDDR3 0xE000000#define STR$M_IDDW3 0x30000000#define STR$M_RSVD_3 0xC0000000#define STR$M_AW4 0x100000000#define STR$M_IDDR4 0xE00000000 #define STR$M_IDDW4 0x3000000000!#define STR$M_RSVD_4 0xC000000000#define STR$M_AW5 0x10000000000!#define STR$M_IDDR5 0xE0000000U000"#define STR$M_IDDW5 0x300000000000##define STR$M_RSVD_5 0xC00000000000!#define STR$M_AW6 0x1000000000000##define STR$M_IDDR6 0xE000000000000$#define STR$M_IDDW6 0x30000000000000%#define STR$M_RSVD_6 0xC0000000000000##define STR$M_AW7 0x100000000000000%#define STR$M_IDDR7 0xE00000000000000&#define STR$M_IDDW7 0x3000000000000000'#define STR$M_RSVD_7 0xC000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma U__nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _str {#pragma __nomember_alignment! unsigned __int64 str$iq_data; __struct { unsigned int str$il_l; unsigned int str$il_h; } str$r_longwords; __struct {N unsigned str$v_aw : 1; /* 0 Array Width */V unsigned str$v_iddr : 3; /* 3:1 Issue to Data Delay for memory reads */j unsigned str$v_iddw : 2; /*U 5:4 Issue to Data Delay for xactions other than memory reads */N unsigned str$v_rsvd_0 : 2; /* 7:6 reserved */N/* */N unsigned str$v_aw1 : 1; /* 8 Array Width */W unsigned str$v_iddr1 : 3; /* 11:9 Issue to Data Delay for memory reads */l unsigned str$v_iddw1 : 2; /* 13:12 Issue to Data Delay for xactions other than memory reads */NU unsigned str$v_rsvd_1 : 2; /* 15:14 reserved */N/* */N unsigned str$v_aw2 : 1; /* 16 Array Width */X unsigned str$v_iddr2 : 3; /* 19:17 Issue to Data Delay for memory reads */l unsigned str$v_iddw2 : 2; /* 21:20 Issue to Data Delay for xactions other than memory reads */N unsigned str$v_rsvd_2 : 2; /* 23:22 reserved U */N/* */N unsigned str$v_aw3 : 1; /* 24 Array Width */X unsigned str$v_iddr3 : 3; /* 27:25 Issue to Data Delay for memory reads */l unsigned str$v_iddw3 : 2; /* 29:28 Issue to Data Delay for xactions other than memory reads */N unsigned str$v_rsvd_3 : 2; /* 31:30 reserved */N/* U */N unsigned str$v_aw4 : 1; /* 32 Array Width */X unsigned str$v_iddr4 : 3; /* 35:33 Issue to Data Delay for memory reads */l unsigned str$v_iddw4 : 2; /* 37:36 Issue to Data Delay for xactions other than memory reads */N unsigned str$v_rsvd_4 : 2; /* 39:38 reserved */N/* */N unsigned str$v_aw5 : 1; U /* 40 Array Width */X unsigned str$v_iddr5 : 3; /* 43:41 Issue to Data Delay for memory reads */l unsigned str$v_iddw5 : 2; /* 45:44 Issue to Data Delay for xactions other than memory reads */N unsigned str$v_rsvd_5 : 2; /* 47:46 reserved */N/* */N unsigned str$v_aw6 : 1; /* 48 Array Width */X unsigned str$v_iUddr6 : 3; /* 51:49 Issue to Data Delay for memory reads */l unsigned str$v_iddw6 : 2; /* 53:52 Issue to Data Delay for xactions other than memory reads */N unsigned str$v_rsvd_6 : 2; /* 55:54 reserved */N/* */N unsigned str$v_aw7 : 1; /* 56 Array Width */X unsigned str$v_iddr7 : 3; /* 59:57 Issue to Data Delay for memory reads */l U unsigned str$v_iddw7 : 2; /* 61:60 Issue to Data Delay for xactions other than memory reads */N unsigned str$v_rsvd_7 : 2; /* 63:62 reserved */ } str$r_bits; } STR; #if !defined(__VAXC))#define str$il_l str$r_longwords.str$il_l)#define str$il_h str$r_longwords.str$il_h$#define str$v_aw str$r_bits.str$v_aw(#define str$v_iddr str$r_bits.str$v_iddr(#define str$v_iddw str$r_bits.str$v_iddw,#define str$v_rsvd_0 str$r_bits.str$v_rsvd_0 U&#define str$v_aw1 str$r_bits.str$v_aw1*#define str$v_iddr1 str$r_bits.str$v_iddr1*#define str$v_iddw1 str$r_bits.str$v_iddw1,#define str$v_rsvd_1 str$r_bits.str$v_rsvd_1&#define str$v_aw2 str$r_bits.str$v_aw2*#define str$v_iddr2 str$r_bits.str$v_iddr2*#define str$v_iddw2 str$r_bits.str$v_iddw2,#define str$v_rsvd_2 str$r_bits.str$v_rsvd_2&#define str$v_aw3 str$r_bits.str$v_aw3*#define str$v_iddr3 str$r_bits.str$v_iddr3*#define str$v_iddw3 str$r_bits.str$v_iddw3,#define str$v_rsvd_3 str$r_b Uits.str$v_rsvd_3&#define str$v_aw4 str$r_bits.str$v_aw4*#define str$v_iddr4 str$r_bits.str$v_iddr4*#define str$v_iddw4 str$r_bits.str$v_iddw4,#define str$v_rsvd_4 str$r_bits.str$v_rsvd_4&#define str$v_aw5 str$r_bits.str$v_aw5*#define str$v_iddr5 str$r_bits.str$v_iddr5*#define str$v_iddw5 str$r_bits.str$v_iddw5,#define str$v_rsvd_5 str$r_bits.str$v_rsvd_5&#define str$v_aw6 str$r_bits.str$v_aw6*#define str$v_iddr6 str$r_bits.str$v_iddr6*#define str$v_iddw6 str$r_bits.str$v_iddw6,#define str$ Uv_rsvd_6 str$r_bits.str$v_rsvd_6&#define str$v_aw7 str$r_bits.str$v_aw7*#define str$v_iddr7 str$r_bits.str$v_iddr7*#define str$v_iddw7 str$r_bits.str$v_iddw7,#define str$v_rsvd_7 str$r_bits.str$v_rsvd_7"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* DREV - D-Chip System Configuration Register */N/* U */#define DREV$M_REV0 0xF#define DREV$M_RSVD_0 0xF0#define DREV$M_REV1 0xF00#define DREV$M_RSVD_1 0xF000#define DREV$M_REV2 0xF0000#define DREV$M_RSVD_2 0xF00000#define DREV$M_REV3 0xF000000 #define DREV$M_RSVD_3 0xF0000000#define DREV$M_REV4 0xF00000000"#define DREV$M_RSVD_4 0xF000000000!#define DREV$M_REV5 0xF0000000000$#define DREV$M_RSVD_5 0xF00000000000##define DREV$M_REV6 0xF000000000000&#define DREV$M_RSVD_6 U0xF0000000000000%#define DREV$M_REV7 0xF00000000000000(#define DREV$M_RSVD_7 0xF000000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _drev {#pragma __nomember_alignment" unsigned __int64 drev$iq_data; __struct { unsigned int drev$il_l; unsigned int drev$il_h; } drev$r_longwords; __Ustruct {N unsigned drev$v_rev0 : 4; /* 3:0 D-Chip 0 Revision */N unsigned drev$v_rsvd_0 : 4; /* 7:4 CPU 0 Clk Fwd Preset */N/* */N unsigned drev$v_rev1 : 4; /* 11:8 D-Chip 1 Revision */N unsigned drev$v_rsvd_1 : 4; /* 15:12 CPU 1 Clk Fwd Preset */N/* */N unsignUed drev$v_rev2 : 4; /* 19:16 D-Chip 2 Revision */N unsigned drev$v_rsvd_2 : 4; /* 23:20 CPU 2 Clk Fwd Preset */N/* */N unsigned drev$v_rev3 : 4; /* 27:24 D-Chip 3 Revision */N unsigned drev$v_rsvd_3 : 4; /* 31:28 CPU 3 Clk Fwd Preset */N/* */N unsigned drev$v_rev4 : 4; U/* 35:32 D-Chip 4 Revision */N unsigned drev$v_rsvd_4 : 4; /* 39:36 CPU 4 Clk Fwd Preset */N/* */N unsigned drev$v_rev5 : 4; /* 43:40 D-Chip 5 Revision */N unsigned drev$v_rsvd_5 : 4; /* 47:44 CPU 5 Clk Fwd Preset */N/* */N unsigned drev$v_rev6 : 4; /* 51:48 D-Chip 6 Revision U */N unsigned drev$v_rsvd_6 : 4; /* 55:52 CPU 6 Clk Fwd Preset */N/* */N unsigned drev$v_rev7 : 4; /* 59:56 D-Chip 7 Revision */N unsigned drev$v_rsvd_7 : 4; /* 63:60 CPU 7 Clk Fwd Preset */ } drev$r_bits; } DREV; #if !defined(__VAXC),#define drev$il_l drev$r_longwords.drev$il_l,#define drev$il_h drev$r_longwords.drev$il_h+#define drev$v_r Uev0 drev$r_bits.drev$v_rev0/#define drev$v_rsvd_0 drev$r_bits.drev$v_rsvd_0+#define drev$v_rev1 drev$r_bits.drev$v_rev1/#define drev$v_rsvd_1 drev$r_bits.drev$v_rsvd_1+#define drev$v_rev2 drev$r_bits.drev$v_rev2/#define drev$v_rsvd_2 drev$r_bits.drev$v_rsvd_2+#define drev$v_rev3 drev$r_bits.drev$v_rev3/#define drev$v_rsvd_3 drev$r_bits.drev$v_rsvd_3+#define drev$v_rev4 drev$r_bits.drev$v_rev4/#define drev$v_rsvd_4 drev$r_bits.drev$v_rsvd_4+#define drev$v_rev5 drev$r_bits.drev$v_rev U5/#define drev$v_rsvd_5 drev$r_bits.drev$v_rsvd_5+#define drev$v_rev6 drev$r_bits.drev$v_rev6/#define drev$v_rsvd_6 drev$r_bits.drev$v_rsvd_6+#define drev$v_rev7 drev$r_bits.drev$v_rev7/#define drev$v_rsvd_7 drev$r_bits.drev$v_rsvd_7"#endif /* #if !defined(__VAXC) */ O/*========================================================================== */N/* */N/* P-Chip Registers U */N/* */O/*========================================================================== */N/* */N/* */N/* WSBA - P-Chip Window Space Base Address Registers */N/* */#dUefine WSBA$M_ENA 0x1#define WSBA$M_SG 0x2#define WSBA$M_PTP 0x4#define WSBA$M_RSVD_0 0xFFFF8#define WSBA$M_ADDR 0xFFF00000(#define WSBA$M_RSVD_1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _wsba {#pragma __nomember_alignment" unsigned __int64 wsba$iq_data; __struct { unsigned int wsba$il U_l; unsigned int wsba$il_h; } wsba$r_longwords; __struct {N unsigned wsba$v_ena : 1; /* 0 Enable */N unsigned wsba$v_sg : 1; /* 1 Scatter/Gather */N unsigned wsba$v_ptp : 1; /* 2 Peer-to-Peer */N unsigned wsba$v_rsvd_0 : 17; /* 19:3 reserved */N unsigned wsba$v_addr : 12; /* 31:20 Base Address */N unsigned wUsba$v_rsvd_1 : 32; /* 63:32 Reserved */ } wsba$r_bits; } WSBA; #if !defined(__VAXC),#define wsba$il_l wsba$r_longwords.wsba$il_l,#define wsba$il_h wsba$r_longwords.wsba$il_h)#define wsba$v_ena wsba$r_bits.wsba$v_ena'#define wsba$v_sg wsba$r_bits.wsba$v_sg)#define wsba$v_ptp wsba$r_bits.wsba$v_ptp/#define wsba$v_rsvd_0 wsba$r_bits.wsba$v_rsvd_0+#define wsba$v_addr wsba$r_bits.wsba$v_addr/#define wsba$v_rsvd_1 wsba$r_bits.wsba$v_rsvd_1"#endif /* # Uif !defined(__VAXC) */ N/* */N/* */N/* WSM - P-Chip Window Space Mask Registers */N/* */#define WSM$M_RSVD_0 0xFFFFF#define WSM$M_AM 0xFFF00000'#define WSM$M_RSVD_1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cUplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _wsm {#pragma __nomember_alignment! unsigned __int64 wsm$iq_data; __struct { unsigned int wsm$il_l; unsigned int wsm$il_h; } wsm$r_longwords; __struct {N unsigned wsm$v_rsvd_0 : 20; /* 19:0 reserved */N unsigned wsm$v_am : 12; /* 31:20 Base Address U */N unsigned wsm$v_rsvd_1 : 32; /* 63:32 Reserved */ } wsm$r_bits; } WSM; #if !defined(__VAXC))#define wsm$il_l wsm$r_longwords.wsm$il_l)#define wsm$il_h wsm$r_longwords.wsm$il_h,#define wsm$v_rsvd_0 wsm$r_bits.wsm$v_rsvd_0$#define wsm$v_am wsm$r_bits.wsm$v_am,#define wsm$v_rsvd_1 wsm$r_bits.wsm$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* U */N/* TBA - P-Chip Translated Base Address Registers */N/* */#define TBA$M_RSVD_0 0x3FF#define TBA$M_ADDR 0x7FFFFFC00'#define TBA$M_RSVD_1 0xFFFFFFF800000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignmeUnt#endiftypedef union _tba {#pragma __nomember_alignment! unsigned __int64 tba$iq_data; __struct { unsigned int tba$il_l; unsigned int tba$il_h; } tba$r_longwords; __struct {N unsigned tba$v_rsvd_0 : 10; /* 9:0 reserved */N unsigned tba$v_addr : 25; /* 34:10 Translated Base Address */N unsigned tba$v_rsvd_1 : 29; /* 63:35 reserved */ } tba$r_bits; } TBA; U#if !defined(__VAXC))#define tba$il_l tba$r_longwords.tba$il_l)#define tba$il_h tba$r_longwords.tba$il_h,#define tba$v_rsvd_0 tba$r_bits.tba$v_rsvd_0(#define tba$v_addr tba$r_bits.tba$v_addr,#define tba$v_rsvd_1 tba$r_bits.tba$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* PCTL - P-Chip Control Register U */N/* */#define PCTL$M_FDSC 0x1#define PCTL$M_FBTB 0x2#define PCTL$M_THDIS 0x4#define PCTL$M_CHAINDIS 0x8#define PCTL$M_TGTLAT 0x10#define PCTL$M_HOLE 0x20#define PCTL$M_MWIN 0x40#define PCTL$M_ARBENA 0x80#define PCTL$M_PRIGRP 0x7F00#define PCTL$M_PPRI 0x8000#define PCTL$M_RSVD_0 0x30000#define PCTL$M_ECCEN 0x40000#define PCTL$M_PADM 0x80000#define PCTL$M_CDQMAX 0xF00000#define UPCTL$M_REV 0xFF000000!#define PCTL$M_CRQMAX 0xF00000000"#define PCTL$M_PTPMAX 0xF000000000"#define PCTL$M_PCLKX 0x30000000000##define PCTL$M_FDSDIS 0x40000000000##define PCTL$M_FDWDIS 0x80000000000%#define PCTL$M_PTEVRFY 0x100000000000(#define PCTL$M_RSVD_1 0xFFFFE00000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _pctl { U#pragma __nomember_alignment" unsigned __int64 pctl$iq_data; __struct { unsigned int pctl$il_l; unsigned int pctl$il_h; } pctl$r_longwords; __struct {N unsigned pctl$v_fdsc : 1; /* 0 Fast Discard enable */N unsigned pctl$v_fbtb : 1; /* 1 Fast Back-To-Back enable */U unsigned pctl$v_thdis : 1; /* 2 Disable anti-Thrash mechanism for TLB */N unsigned pctl$v_chaindis : 1; /* 3 Disable ChaUining */S unsigned pctl$v_tgtlat : 1; /* 4 Target Latency Timers timers enable */N unsigned pctl$v_hole : 1; /* 5 512K to 1M window Hole enable */N unsigned pctl$v_mwin : 1; /* 6 Monster Window enable */N unsigned pctl$v_arbena : 1; /* 7 internal Arbiter Enable */N unsigned pctl$v_prigrp : 7; /* 14:8 arbiter Priority Group */\ unsigned pctl$v_ppri : 1; /* 15 arbiter Priority Group for theU Pchip itself */N unsigned pctl$v_rsvd_0 : 2; /* 17:16 reserved */S unsigned pctl$v_eccen : 1; /* 18 ECC Enable for DMA & SGTE accesses */N unsigned pctl$v_padm : 1; /* 19 PAD bus Mode */\ unsigned pctl$v_cdqmax : 4; /* 23:20 Max Data xfer to Dchips from both Pchips */N unsigned pctl$v_rev : 8; /* 31:24 Revision */N/* U */Z unsigned pctl$v_crqmax : 4; /* 35:32 Max requests to Cchip from both Pchips */^ unsigned pctl$v_ptpmax : 4; /* 39:36 Max PTP requests to Cchip from both Pchips */N unsigned pctl$v_pclkx : 2; /* 41:40 PCI Clock Freq Multiplier */V unsigned pctl$v_fdsdis : 1; /* 42 Fast DMA Start & SGTE request Disable */] unsigned pctl$v_fdwdis : 1; /* 43 Fast DMA read cache blk Wrap request Disable */N unsigned pctl$v_ptevrfy : 1; /* U 44 PTE Verify for DMA read */N unsigned pctl$v_rsvd_1 : 19; /* 63:45 reserved */ } pctl$r_bits; } PCTL; #if !defined(__VAXC),#define pctl$il_l pctl$r_longwords.pctl$il_l,#define pctl$il_h pctl$r_longwords.pctl$il_h+#define pctl$v_fdsc pctl$r_bits.pctl$v_fdsc+#define pctl$v_fbtb pctl$r_bits.pctl$v_fbtb-#define pctl$v_thdis pctl$r_bits.pctl$v_thdis3#define pctl$v_chaindis pctl$r_bits.pctl$v_chaindis/#define pctl$v_tgtlat pctl$r_bits.pctl U$v_tgtlat+#define pctl$v_hole pctl$r_bits.pctl$v_hole+#define pctl$v_mwin pctl$r_bits.pctl$v_mwin/#define pctl$v_arbena pctl$r_bits.pctl$v_arbena/#define pctl$v_prigrp pctl$r_bits.pctl$v_prigrp+#define pctl$v_ppri pctl$r_bits.pctl$v_ppri/#define pctl$v_rsvd_0 pctl$r_bits.pctl$v_rsvd_0-#define pctl$v_eccen pctl$r_bits.pctl$v_eccen+#define pctl$v_padm pctl$r_bits.pctl$v_padm/#define pctl$v_cdqmax pctl$r_bits.pctl$v_cdqmax)#define pctl$v_rev pctl$r_bits.pctl$v_rev/#define pctl$v_crq Umax pctl$r_bits.pctl$v_crqmax/#define pctl$v_ptpmax pctl$r_bits.pctl$v_ptpmax-#define pctl$v_pclkx pctl$r_bits.pctl$v_pclkx/#define pctl$v_fdsdis pctl$r_bits.pctl$v_fdsdis/#define pctl$v_fdwdis pctl$r_bits.pctl$v_fdwdis1#define pctl$v_ptevrfy pctl$r_bits.pctl$v_ptevrfy/#define pctl$v_rsvd_1 pctl$r_bits.pctl$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* U */N/* PLAT - P-Chip Master Latency Register */N/* */#define PLAT$M_RSVD_0 0xFF#define PLAT$M_LAT 0xFF00 #define PLAT$M_RSVD_1 0xFFFF0000(#define PLAT$M_RSVD_2 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#e Undiftypedef union _plat {#pragma __nomember_alignment" unsigned __int64 plat$iq_data; __struct { unsigned int plat$il_l; unsigned int plat$il_h; } plat$r_longwords; __struct {N unsigned plat$v_rsvd_0 : 8; /* 7:0 reserved */N unsigned plat$v_lat : 8; /* 15:8 Master Latency Timer */N unsigned plat$v_rsvd_1 : 16; /* 31:16 reserved */N unsigned plat$v_rsvd_2 : 32;U /* 63:32 reserved */ } plat$r_bits; } PLAT; #if !defined(__VAXC),#define plat$il_l plat$r_longwords.plat$il_l,#define plat$il_h plat$r_longwords.plat$il_h/#define plat$v_rsvd_0 plat$r_bits.plat$v_rsvd_0)#define plat$v_lat plat$r_bits.plat$v_lat/#define plat$v_rsvd_1 plat$r_bits.plat$v_rsvd_1/#define plat$v_rsvd_2 plat$r_bits.plat$v_rsvd_2"#endif /* #if !defined(__VAXC) */ N/* U */N/* */N/* PERROR - P-Chip Error Register */N/* */#define PERROR$M_LOST 0x1#define PERROR$M_SERR 0x2#define PERROR$M_PERR 0x4#define PERROR$M_DCRTO 0x8#define PERROR$M_SGE 0x10#define PERROR$M_APE 0x20#define PERROR$M_TA 0x40#define PERROR$M_RDPE 0x80#define PERROR$M_NDS 0x100#define UPERROR$M_RTO 0x200#define PERROR$M_UECC 0x400#define PERROR$M_CRE 0x800#define PERROR$M_RSVD_0 0xF000$#define PERROR$M_ADDR 0xFFFFFFFF0000'#define PERROR$M_ADDR_H 0x7000000000000'#define PERROR$M_RSVD_1 0x8000000000000%#define PERROR$M_CMD 0xF0000000000000'#define PERROR$M_SYN 0xFF00000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif Utypedef union _perror {#pragma __nomember_alignment$ unsigned __int64 perror$iq_data; __struct {! unsigned int perror$il_l;! unsigned int perror$il_h; } perror$r_longwords; __struct {N unsigned perror$v_lost : 1; /* 0 Lost an error */N unsigned perror$v_serr : 1; /* 1 SERR# sampled asserted */T unsigned perror$v_perr : 1; /* 2 PERR# sampled asserted as PCI master */^ unsigned perror$Uv_dcrto : 1; /* 3 delayed completion retry timeout as PCI target */N unsigned perror$v_sge : 1; /* 4 Scatter/Gather had invalid PTE */e unsigned perror$v_ape : 1; /* 5 Address Parity Error detected as potential PCI target */N unsigned perror$v_ta : 1; /* 6 Targed Abort as PCI master */X unsigned perror$v_rdpe : 1; /* 7 PCI Read Data Parity Error as PCI master */N unsigned perror$v_nds : 1; /* 8 No DevSel as PCI master */\U unsigned perror$v_rto : 1; /* 9 Retry TimeOut as PCI master after 2^24 tries */N unsigned perror$v_uecc : 1; /* 10 Uncorrectable ECC error */N unsigned perror$v_cre : 1; /* 11 Correctable ECC error */N unsigned perror$v_rsvd_0 : 4; /* 15:12 reserved */N unsigned perror$v_addr : 32; /* 48:16 Addres of CRE or UECC */N unsigned perror$v_addr_h : 3; /* 50:48 Addres of CRE or UECC */N unsi Ugned perror$v_rsvd_1 : 1; /* 51 reserved */N unsigned perror$v_cmd : 4; /* 55:52 PCI Command on error */O unsigned perror$v_syn : 8; /* 63:56 ECC Syndrome on CRE or UECC */ } perror$r_bits; } PERROR; #if !defined(__VAXC)2#define perror$il_l perror$r_longwords.perror$il_l2#define perror$il_h perror$r_longwords.perror$il_h1#define perror$v_lost perror$r_bits.perror$v_lost1#define perror$v_serr perror$r_bits.perror$v_serr1 U#define perror$v_perr perror$r_bits.perror$v_perr3#define perror$v_dcrto perror$r_bits.perror$v_dcrto/#define perror$v_sge perror$r_bits.perror$v_sge/#define perror$v_ape perror$r_bits.perror$v_ape-#define perror$v_ta perror$r_bits.perror$v_ta1#define perror$v_rdpe perror$r_bits.perror$v_rdpe/#define perror$v_nds perror$r_bits.perror$v_nds/#define perror$v_rto perror$r_bits.perror$v_rto1#define perror$v_uecc perror$r_bits.perror$v_uecc/#define perror$v_cre perror$r_bits.perror$v_cre U5#define perror$v_rsvd_0 perror$r_bits.perror$v_rsvd_01#define perror$v_addr perror$r_bits.perror$v_addr5#define perror$v_addr_h perror$r_bits.perror$v_addr_h5#define perror$v_rsvd_1 perror$r_bits.perror$v_rsvd_1/#define perror$v_cmd perror$r_bits.perror$v_cmd/#define perror$v_syn perror$r_bits.perror$v_syn"#endif /* #if !defined(__VAXC) */ N/* */N/* U */N/* PERRMASK - P-Chip Error Mask Register */N/* */#define PERRMASK$M_LOST 0x1#define PERRMASK$M_SERR 0x2#define PERRMASK$M_PERR 0x4#define PERRMASK$M_DCRTO 0x8#define PERRMASK$M_SGE 0x10#define PERRMASK$M_APE 0x20#define PERRMASK$M_TA 0x40#define PERRMASK$M_RDPE 0x80#define PERRMASK$M_NDS 0x100#define PERRMASK$M_RTO 0x200#define PERRMASK$M_UECC 0x400U#define PERRMASK$M_CRE 0x800$#define PERRMASK$M_RSVD_0 0xFFFFF000,#define PERRMASK$M_RSVD_1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _perrmask {#pragma __nomember_alignment& unsigned __int64 perrmask$iq_data; __struct {# unsigned int perrmask$il_l;# unsigned int perrmask$il_h; U } perrmask$r_longwords; __struct {N unsigned perrmask$v_lost : 1; /* 0 Lost an error */N unsigned perrmask$v_serr : 1; /* 1 SERR# sampled asserted */T unsigned perrmask$v_perr : 1; /* 2 PERR# sampled asserted as PCI master */^ unsigned perrmask$v_dcrto : 1; /* 3 delayed completion retry timeout as PCI target */N unsigned perrmask$v_sge : 1; /* 4 Scatter/Gather had invalid PTE */e unsigned perrmask$v_ape : 1; U /* 5 Address Parity Error detected as potential PCI target */N unsigned perrmask$v_ta : 1; /* 6 Targed Abort as PCI master */X unsigned perrmask$v_rdpe : 1; /* 7 PCI Read Data Parity Error as PCI master */N unsigned perrmask$v_nds : 1; /* 8 No DevSel as PCI master */\ unsigned perrmask$v_rto : 1; /* 9 Retry TimeOut as PCI master after 2^24 tries */N unsigned perrmask$v_uecc : 1; /* 10 Uncorrectable ECC error */N unsigned U perrmask$v_cre : 1; /* 11 Correctable ECC error */N unsigned perrmask$v_rsvd_0 : 20; /* 31:12 reserved */N unsigned perrmask$v_rsvd_1 : 32; /* 63:32 reserved */ } perrmask$r_bits; } PERRMASK; #if !defined(__VAXC)8#define perrmask$il_l perrmask$r_longwords.perrmask$il_l8#define perrmask$il_h perrmask$r_longwords.perrmask$il_h7#define perrmask$v_lost perrmask$r_bits.perrmask$v_lost7#define perrmask$v_serr perrmask$r_b Uits.perrmask$v_serr7#define perrmask$v_perr perrmask$r_bits.perrmask$v_perr9#define perrmask$v_dcrto perrmask$r_bits.perrmask$v_dcrto5#define perrmask$v_sge perrmask$r_bits.perrmask$v_sge5#define perrmask$v_ape perrmask$r_bits.perrmask$v_ape3#define perrmask$v_ta perrmask$r_bits.perrmask$v_ta7#define perrmask$v_rdpe perrmask$r_bits.perrmask$v_rdpe5#define perrmask$v_nds perrmask$r_bits.perrmask$v_nds5#define perrmask$v_rto perrmask$r_bits.perrmask$v_rto7#define perrmask$v_uecc perrma Usk$r_bits.perrmask$v_uecc5#define perrmask$v_cre perrmask$r_bits.perrmask$v_cre;#define perrmask$v_rsvd_0 perrmask$r_bits.perrmask$v_rsvd_0;#define perrmask$v_rsvd_1 perrmask$r_bits.perrmask$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* PERRSET - P-Chip Error Set Register */N/* U */#define PERRSET$M_LOST 0x1#define PERRSET$M_SERR 0x2#define PERRSET$M_PERR 0x4#define PERRSET$M_DCRTO 0x8#define PERRSET$M_SGE 0x10#define PERRSET$M_APE 0x20#define PERRSET$M_TA 0x40#define PERRSET$M_RDPE 0x80#define PERRSET$M_NDS 0x100#define PERRSET$M_RTO 0x200#define PERRSET$M_UECC 0x400#define PERRSET$M_CRE 0x800#define PERRSET$M_RSVD_0 0xF000%#define PERRSET$M_ADDR 0xFFFFFFFF0000(#define PERRSET$M_ADDRU_H 0x7000000000000(#define PERRSET$M_RSVD_1 0x8000000000000&#define PERRSET$M_CMD 0xF0000000000000(#define PERRSET$M_SYN 0xFF00000000000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _perrset {#pragma __nomember_alignment% unsigned __int64 perrset$iq_data; __struct {" unsigned int perrset$il_l;" unsigned i Unt perrset$il_h; } perrset$r_longwords; __struct {N unsigned perrset$v_lost : 1; /* 0 Lost an error */N unsigned perrset$v_serr : 1; /* 1 SERR# sampled asserted */T unsigned perrset$v_perr : 1; /* 2 PERR# sampled asserted as PCI master */^ unsigned perrset$v_dcrto : 1; /* 3 delayed completion retry timeout as PCI target */N unsigned perrset$v_sge : 1; /* 4 Scatter/Gather had invalid PTE */e unsignedU perrset$v_ape : 1; /* 5 Address Parity Error detected as potential PCI target */N unsigned perrset$v_ta : 1; /* 6 Targed Abort as PCI master */X unsigned perrset$v_rdpe : 1; /* 7 PCI Read Data Parity Error as PCI master */N unsigned perrset$v_nds : 1; /* 8 No DevSel as PCI master */\ unsigned perrset$v_rto : 1; /* 9 Retry TimeOut as PCI master after 2^24 tries */N unsigned perrset$v_uecc : 1; /* 10 Uncorrectable ECC error U */N unsigned perrset$v_cre : 1; /* 11 Correctable ECC error */N unsigned perrset$v_rsvd_0 : 4; /* 15:12 reserved */U unsigned perrset$v_addr : 32; /* 47:16 Lo 32 Address bits of CRE or UECC */U unsigned perrset$v_addr_h : 3; /* 50:48 Hi 3 Address bits of CRE or UECC */N unsigned perrset$v_rsvd_1 : 1; /* 51 reserved */N unsigned perrset$v_cmd : 4; /* 55:52 PCI Command on error */O U unsigned perrset$v_syn : 8; /* 63:56 ECC Syndrome on CRE or UECC */ } perrset$r_bits; } PERRSET; #if !defined(__VAXC)5#define perrset$il_l perrset$r_longwords.perrset$il_l5#define perrset$il_h perrset$r_longwords.perrset$il_h4#define perrset$v_lost perrset$r_bits.perrset$v_lost4#define perrset$v_serr perrset$r_bits.perrset$v_serr4#define perrset$v_perr perrset$r_bits.perrset$v_perr6#define perrset$v_dcrto perrset$r_bits.perrset$v_dcrto2#define perrset$v_sge perrse Ut$r_bits.perrset$v_sge2#define perrset$v_ape perrset$r_bits.perrset$v_ape0#define perrset$v_ta perrset$r_bits.perrset$v_ta4#define perrset$v_rdpe perrset$r_bits.perrset$v_rdpe2#define perrset$v_nds perrset$r_bits.perrset$v_nds2#define perrset$v_rto perrset$r_bits.perrset$v_rto4#define perrset$v_uecc perrset$r_bits.perrset$v_uecc2#define perrset$v_cre perrset$r_bits.perrset$v_cre8#define perrset$v_rsvd_0 perrset$r_bits.perrset$v_rsvd_04#define perrset$v_addr perrset$r_bits.perrset$v_addr8#def Uine perrset$v_addr_h perrset$r_bits.perrset$v_addr_h8#define perrset$v_rsvd_1 perrset$r_bits.perrset$v_rsvd_12#define perrset$v_cmd perrset$r_bits.perrset$v_cmd2#define perrset$v_syn perrset$r_bits.perrset$v_syn"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* TLBIV - P-Chip Translation Buffer Invalidate Virtual Register */N/* U */#define TLBIV$M_RSVD_0 0xF#define TLBIV$M_ADDR 0xFFFF0!#define TLBIV$M_RSVD_1 0xFFF00000)#define TLBIV$M_RSVD_2 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _tlbiv {#pragma __nomember_alignment# unsigned __int64 tlbiv$iq_data; __struct U { unsigned int tlbiv$il_l; unsigned int tlbiv$il_h; } tlbiv$r_longwords; __struct {N unsigned tlbiv$v_rsvd_0 : 4; /* 3:0 reserved */X unsigned tlbiv$v_addr : 16; /* 19:4 invalidate if matches PCI addr<31:16> */N unsigned tlbiv$v_rsvd_1 : 12; /* 31:20 reserved */N unsigned tlbiv$v_rsvd_2 : 32; /* 63:32 reserved */ } tlbiv$r_bits; } TLBIV; #if !defin Ued(__VAXC)/#define tlbiv$il_l tlbiv$r_longwords.tlbiv$il_l/#define tlbiv$il_h tlbiv$r_longwords.tlbiv$il_h2#define tlbiv$v_rsvd_0 tlbiv$r_bits.tlbiv$v_rsvd_0.#define tlbiv$v_addr tlbiv$r_bits.tlbiv$v_addr2#define tlbiv$v_rsvd_1 tlbiv$r_bits.tlbiv$v_rsvd_12#define tlbiv$v_rsvd_2 tlbiv$r_bits.tlbiv$v_rsvd_2"#endif /* #if !defined(__VAXC) */ N/* */N/* U */N/* TLBIA - P-Chip Translation Buffer Invalidate all Register */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _tlbia {#pragma __nomember_alignment# unsigned __int64 tlbia$iq_data; __struct { unsigned int tlbia$il_l; U unsigned int tlbia$il_h; } tlbia$r_longwords; } TLBIA; #if !defined(__VAXC)/#define tlbia$il_l tlbia$r_longwords.tlbia$il_l/#define tlbia$il_h tlbia$r_longwords.tlbia$il_h"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* PMONCTL - P-Chip Monitor Control Register */N/* U */#define PMONCTL$M_SLCT0 0xFF#define PMONCTL$M_SLCT1 0xFF00!#define PMONCTL$M_STKDIS0 0x10000!#define PMONCTL$M_STKDIS1 0x20000##define PMONCTL$M_RSVD_0 0xFFFC0000+#define PMONCTL$M_RSVD_1 0xFFFFFFFF00000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _pmonctl {#pragma U__nomember_alignment% unsigned __int64 pmonctl$iq_data; __struct {" unsigned int pmonctl$il_l;" unsigned int pmonctl$il_h; } pmonctl$r_longwords; __struct {N unsigned pmonctl$v_slct0 : 8; /* 7:0 Select Monitor 0 */N unsigned pmonctl$v_slct1 : 8; /* 15:8 Select Monitor 1 */N unsigned pmonctl$v_stkdis0 : 1; /* 16 Sticky Count 0 Disable */N unsigned pmonctl$v_stkdis1 : 1; /* 17 Sticky Count 1 Dis Uable */N unsigned pmonctl$v_rsvd_0 : 14; /* 31:18 reserved */N unsigned pmonctl$v_rsvd_1 : 32; /* 63:32 reserved */ } pmonctl$r_bits; } PMONCTL; #if !defined(__VAXC)5#define pmonctl$il_l pmonctl$r_longwords.pmonctl$il_l5#define pmonctl$il_h pmonctl$r_longwords.pmonctl$il_h6#define pmonctl$v_slct0 pmonctl$r_bits.pmonctl$v_slct06#define pmonctl$v_slct1 pmonctl$r_bits.pmonctl$v_slct1:#define pmonctl$v_stkdis0 pmonctl$r_ Ubits.pmonctl$v_stkdis0:#define pmonctl$v_stkdis1 pmonctl$r_bits.pmonctl$v_stkdis18#define pmonctl$v_rsvd_0 pmonctl$r_bits.pmonctl$v_rsvd_08#define pmonctl$v_rsvd_1 pmonctl$r_bits.pmonctl$v_rsvd_1"#endif /* #if !defined(__VAXC) */ N/* */N/* */N/* PMONCNT - P-Chip Monitor Counters Register */N/* U */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef union _pmoncnt {#pragma __nomember_alignment% unsigned __int64 pmoncnt$iq_data; __struct {% unsigned int pmoncnt$il_cnt0;% unsigned int pmoncnt$il_cnt1; } pmoncnt$r_longwords; } PMONCNT; #if !definedU(__VAXC);#define pmoncnt$il_cnt0 pmoncnt$r_longwords.pmoncnt$il_cnt0;#define pmoncnt$il_cnt1 pmoncnt$r_longwords.pmoncnt$il_cnt1"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TSUNAMIDEF_LOADED */  UwwP[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/*U* 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS SofUtware, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JAN-2004 07:50:02 $1$DGA8345:[LIB_H.SRC]TTYDEF.SDL;1 *//************************* U*******************************************************************************************************//*** MODULE $TTYDEF ***/#ifndef __TTYDEF_LOADED#define __TTYDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */U[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union vari Uant_union#endif#endif N/*++ */N/* */N/* Terminal driver write packet (TWP) */N/* */N/*-- */ N#define TTY$K_WB_LENGTH 56 /* LENGTH U */N#define TTY$C_WB_LENGTH 56 /* LENGTH */R#define TTY$S_TTYWBDEF 60 /* Old size name, synonym for TWP$S_TWP */  9#ifdef __cplusplus /* Define structure prototypes */ struct _irp; #endif /* #ifdef __cplusplus */ typedef struct _twp {N struct _twp *tty$l_wb_flink; /* */N struct _twp *tty$l_wb_blink; /* */N unsigned short int tty$wU_wb_size; /* */N unsigned char tty$b_wb_type; /* */N unsigned char tty$b_wb_flck; /* */N void (*tty$l_wb_fpc)(); /* */N __int64 tty$q_wb_fr3; /* */N __int64 tty$q_wb_fr4; /* */N void *tty$l_wb_map; /* U */N void *tty$l_wb_next; /* */N void *tty$l_wb_end; /* */N struct _irp *tty$l_wb_irp; /* */N unsigned short int tty$w_wb_status; /* */N unsigned short int tty$w_wb_bcnt; /* */N int (*tty$l_wb_retaddr)(); /* */NU void *tty$l_wb_data; /* */ } TWP;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TTYDEF_LOADED */ ww`[UM/*********************************************************U******************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** U **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** U **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JAN-2004 07:50:02 $1$DGA8345:[LIB_H.SRC]TTYDEF.SDL;1 *//*********************************************************************************************************** U*********************//*** MODULE $TTYDIALTYP ***/#ifndef __TTYDIALTYP_LOADED#define __TTYDIALTYP_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size defaulUt to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* U */N/* Assign meanings to bits in the TTY_DIALTYP SYSGEN parameter. */N/* */#define TTY$M_RINGWAIT 0x1#define TTY$M_FAST_SHUTDOWN 0x2#define TTY$M_NO_REFC 0x4#define TTY$M_A_SPEEDS 0x8Z#define TTY$S_DIALTYP_BITS 1 /* Old size name, synonym for TTY$S_TTY_DIALTYP */ typedef struct _tty_dialtyp {N unsigned tty$v_ringwait : 1; /*WAIT FOR RING BE UFORE SET DTR */N unsigned tty$v_fast_shutdown : 1; /*SHUTDOWN IMMED. IF LOSE CARRIER */N unsigned tty$v_no_refc : 1; /*SKIP CHECK FOR REFC */N unsigned tty$v_a_speeds : 1; /*IF SET, USE A SPEED TABLE */N/*last bit reserved for internal */N/*use */ unsigned tty$v_fill_13_ : 4; } TTY_DIALTYP; $#pragma __member_alignmentU __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TTYDIALTYP_LOADED */ wwI[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIALU. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This softUware is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*********************************************************************** U****//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JAN-2004 07:50:02 $1$DGA8345:[LIB_H.SRC]TTYDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TTYILDEF ***/#ifndef __TTYILDEF_LOADED#define __TTYILDEF_LOADED 1 G#pragma U__nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_parUams ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* Itemlist Descriptor */N/* U */N/* Description: */I/* This set of definitions defines the locations of all the fields */N/* in the terminal QIO item list. */N/*-- */N#define TTY$K_IL_LENGTH 12 /* LENGTH */[#define TTY$S_TTYILDEF 12 U /* Old size name, synonym for TTY$S_TT_ITEM_LIST */ typedef struct _tt_item_list {X unsigned short int tty$w_il_len; /* THE LENGTH OF THE BUFFER POINTED TO BY ADR */N unsigned short int tty$w_il_type; /* THE TYPE CODE OF THIS ITEM */N unsigned int tty$l_il_adr; /* THE USER SPECIFYED ADDRESS */N unsigned int tty$l_il_retadr; /* VALUE RETURNED ADDRESS */ } TT_ITEM_LIST; $#pragma __member_alignment __restoreR#ifdef __INITIAL_PUOINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TTYILDEF_LOADED */ wwp[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential Uproprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/UM/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************** U*********************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JAN-2004 07:50:02 $1$DGA8345:[LIB_H.SRC]TTYDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TTYISDEF ***/#ifndef __TTYISDEF_LOADED#define __TTYISDEF_LOADED 1 G#pragma __nostandard /* This file useUs non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknUown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* ITEM LIST STACK STRUCTURE */N/* U */ N/* WARNING: STRUCTURE MUST ALWAYS BE FORCED TO A LONGWORD BOUNDARY. */N/* */N/* DESCRIPTION: */I/* THIS STRUCTURE IS ALLOCATED OFF THE STACK WHEN AN ITEM LIST QIO IS */N/* DETECTED. */N/*-- U */N#define TTY$K_IS_LENGTH 96 /* LENGTH */Z#define TTY$S_TTYISDEF 96 /* Old size name, synonym for TTY$S_TT_ITEM_STK */ typedef struct _tt_item_stk {_ unsigned int tty$l_is_acmode; /* ACCESS MODE MAXIMIZED WITH THE MODE OF THE CALLER */N unsigned int tty$l_is_editmode; /* PLACE TO KEEP THE MODE */N void *tty$l_is_buf; /* THE USERS ADDRESS OF HIS BUFFER */N unsigned int tty$l_iUs_buflen; /* THE LENGTH OF THE USERS BUFFER */N void *tty$l_is_ini; /* USERS INITIAL STRING ADDRESS */N unsigned int tty$l_is_inilen; /* LENGTH OF THE INITIAL STRING */W unsigned int tty$l_is_inibuf; /* length of initial buffer for fallback use */P void *tty$l_is_itmlst; /* THE USERS ADDRESS OF THE ITEM LIST */N/* USED AS A POINTER TO THE NEXT ENTRY */N void *tty$l_is_lastitm; U /* USERS ADDRESS OF THE LAST ITEM */N/* CALCULATED FROM BEGINNING ADDRESS AND LENGTH */N unsigned int tty$l_is_modify; /* THE USERS MODIFIER BITS */Q void *tty$l_is_pic; /* USERS ADDRESS OF THE PICTURE STRING */N unsigned int tty$l_is_piclen; /* THE LENGTH OF THE PICTURE STRING */P void *tty$l_is_prm; /* USERS ADDRESS OF THE PROMPT STRING */N unsigned int tty$l_is_prmlen; /* THE LENGTH OF TUHE PROMPT STRING */O unsigned int tty$l_is_prmbuf; /* length of prompt for fallback use */T unsigned int tty$l_is_specifyed; /* BITMASK OF SPECIFYED ITEM LIST ENTRIES */V void *tty$l_is_term; /* THE ADDRESS OF THE USERS TERMINATOR MASK */U void *tty$l_is_termlen; /* THE LENGTH OF THE USERS TERMINATOR MASK */V void *tty$l_is_aes; /* THE ADDRESS OF THE ALTERNATE ECHO STRING */U unsigned int tty$l_is_aeslen; /* THE LENGTUH OF THE ALTERNATE ECHO STRING */N unsigned int tty$l_is_timeout; /* TIMEOUT VALUE */\ unsigned short int tty$w_is_fillchr; /* TWO BYTES SPECIFYING FILL AND CLEAR CHARACTER */T unsigned short int tty$w_is_inioff; /* OFFSET INTO INITIAL STRING FOR ECHOING */P unsigned short int tty$w_is_esctrmovr; /* ESCAPE TERMINATOR OVERFLOW SIZE */N unsigned short int tty$w_is_sparew; /* round to longword */N unsigned int tty$l_is_sparel; /* roundU to quadword boundary */ } TT_ITEM_STK;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TTYISDEF_LOADED */ ww[UM/***************************************************************************/M/** U **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** U **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** U **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JAN-2004 07:50:02 $1$DGA8345:[LIB_H.SRC]TTYDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $T UTYMDMDEF ***/#ifndef __TTYMDMDEF_LOADED#define __TTYMDMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdUef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* aka $TTYMODEM via hack in TTYMACS.MAR */NU/* */I/* Modem control state table definitions */N/* */N/* */I/* state entry definitions */N/* */ N#define MODEM$C_ST_LENGTH 8 U /* LENGTH */_#define MODEM$S_MODEM_STATE 8 /* Old size name, synonym for MODEM$S_TT_MODEM_STATE */ typedef struct _tt_modem_state {N unsigned char modem$b_st_onmask; /*output signals to activate */N unsigned char modem$b_st_offmask; /*output signals to disable */N unsigned short int modem$w_st_timer; /*timer amount to init */N int (*modem$l_st_routine)(); /*action routine ADDRESS */ U } TT_MODEM_STATE;N/* */I/* transition definitions */N/* */N#define MODEM$C_TRAN_LENGTH 8 /* LENGTH */_#define MODEM$S_MODEM_TRANS 8 /* Old size name, synonym for MODEM$S_TT_MODEM_TRANS */ typedef struct _tt_modem_trans {N unsigned char modem$b_tranV_type; /* element type */N unsigned char modem$b_tran_type2; /* unused element type */N unsigned char modem$b_tran_offmask; /* input signals test on */N unsigned char modem$b_tran_onmask; /* input signals test off */N void *modem$l_tran_nstate; /* next state ADDRESS */ } TT_MODEM_TRANS;N/* */I/* transition type codes V */N/* */N#define MODEM$C_TRAN_DATASET 0 /* dataset */N#define MODEM$C_TRAN_TIME 1 /* timer */N#define MODEM$C_TRAN_END 2 /* end of transition list */N#define MODEM$C_TRAN_DIALTYPE 3 /* test for sysgen parameter */N#define MODEM$C_TRAN_DZ11 4 /* controller = DZ11 V */N#define MODEM$C_TRAN_NOMODEM 5 /* line not enabled for modem */N/* */I/* argument type codes */N/* */N#define MODEM$C_INIT 0 /* init line */N#define MODEM$C_SHUTDWN 1 /* hangup command */S#define MODEVM$C_NULL 2 /* null, for detecting preset conditions */N#define MODEM$C_DATASET 3 /* dataset interrupt */N#define MODEM$C_TIMER 4 /* timer expiration */N#define MODEM$C_INIT_NORESET 5 /* init modem but not signals */N#define MODEM$C_SHUTDWN_NOHANGUP 6 /* stop modem but not signals */#define TIMCTRL$M_CANCEL 0x1#define TIMCTRL$M_ACTIVE 0x2`#define TIMCTRL$S_MODEM_BITS 1 /* Old size Vname, synonym for TIMCTRL$S_TT_MODEM_BITS */ typedef struct _tt_modem_bits {N unsigned timctrl$v_cancel : 1; /*CANCEL TIMER REQUEST */N unsigned timctrl$v_active : 1; /*TIMER CURRENTLY ACTIVE */$ unsigned timctrl$v_fill_12_ : 6; } TT_MODEM_BITS;N#define MODEM$M_ENABLE 32768 /*mask enable */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supporVted */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TTYMDMDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-PackVard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, IncV., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************************* V*************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JAN-2004 07:50:02 $1$DGA8345:[LIB_H.SRC]TTYDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TTYRBDEF ***/#ifndef __TTYRBDEF_LOADED#define __TTYRBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_align Vment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif  V#ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* Read buffer definitions */N/* */I/* This buffer V is allocated everytime a read is issued. The */N/* buffer contains all the information necessary to perform this read. */N/* */N/*-- */ #define TTY$M_RS_WRAP 0x1Y#define TTY$S_TTYRBDEF 84 /* Old size name; synonym for TTY$S_TT_READBUF */ typedef struct _tt_readbuf {O void *tty$l_rb_txt; /* Add Vress of the first character of */N/* the read data. */N void *tty$l_rb_uva; /* READ BUFFER - USER VIRTUAL ADDR */N unsigned short int tty$w_rb_size; /* READ BUFFER - BLOCK SIZE */N unsigned short int tty$w_rb_type; /* buffer type */N unsigned short int tty$w_rb_echlen; /* NUMBER OF CHARACTERS TO ECHO */N/* WHEN OUTPUTTING FROM ECHSTR  V */N unsigned short int tty$w_rb_nonfill; /* POSITION OF 1ST NONFILL CHAR */N unsigned __int64 tty$q_rb_echoarea; /* WORDS TO ECHO CHARACTERS FROM */N void *tty$l_rb_echstr; /* ADDRESS OF THE FIRST CHARACTER */N/* TO OUTPUT DURING EDITECHOING. */N void *tty$l_rb_pic; /* ADDRESS OF THE PICTURE STRING */N/* FOR READ VERIFY */S void *tty$l_Vrb_term; /* THE ADDRESS OF THE TERMINATOR BITMASK */N unsigned int tty$l_rb_mod; /* MODIFIER LONGWORD */N void *tty$l_rb_aes; /* ADDRESS OF THE AES STRING */N unsigned short int tty$w_rb_aeslen; /* THE LENGTH OF THE AESSTRING */ __union {N unsigned short int tty$w_rb_rdstate; /* Read state information word */ __struct {i unsigned tty$v_rs_wrap : 1; /* THE READ HAS WRAPPED EITHER IN THE VPROMPT OR INITIAL STRING */( unsigned tty$v_fill_11_ : 7;$ } tty$r_rb_rdstate_bits;# } tty$r_rb_rdstate_overlay;O void *tty$l_rb_lin; /* ADDRESS OF THE FIRST CHARACTER ON */N/* THIS LINE. */N unsigned short int tty$w_rb_linoff; /* OFFSET FROM THE BEGINNING OF THE */N/* LINE TO THE CURSOR POSITION. */P unsigned short int tty$w_rb_linrVest; /* NUMBER OF CHARACTERS TO THE RIGHT */N/* OF THE CURSOR POSITION, USED BY */N/* INPUT EDITING */R unsigned short int tty$w_rb_prmlen; /* LENGTH IN BYTES OF THE PROMPT STRING */N unsigned short int tty$w_rb_timos; /* READ BUFFER - TIMEOUT SECONDS */N unsigned short int tty$w_rb_cpzcur; /* CURRENT CURSOR POSITION */N unsigned short int tty$w_rb_cpzorg; /* READ BUFFER -V ORIGONAL HORIZON */N unsigned short int tty$w_rb_txtoff; /* OFFSET FROM THE BEGINNING OF THE */N/* DATA TO THE LOCATION OF THE NEXT CHARACTER */N unsigned short int tty$w_rb_piclen; /* the length of the picture string */N unsigned short int tty$w_rb_txtsiz; /* THE LENGTH OF THE READ. */N unsigned short int tty$w_rb_txtech; /* AMOUNT OF INITIAL STRING TO ECHO */N unsigned short int tty$w_rb_mode; /* VALUE INDICATING READ EDIT MODE */N V unsigned char tty$b_rb_rvfclr; /* CLEAR CHARACTER FOR READ VERIFY */N unsigned char tty$b_rb_rvffil; /* READ VERIFY FILL CHARACTER */N unsigned short int tty$w_rb_esctkn; /* ESCAPE TOKEN CHARACTER */O unsigned short int tty$w_rb_txtonlysiz; /* SIZE OF TEXT W/OUT TERMINATOR */ __union {P void *tty$a_rb_prm; /* ADDRESS OF BEGINNING OF THE PROMPT */N void *tty$l_rb_data; /* READ BUFFER - DATA */ V} tty$r_rb_prm_overlay; } TT_READBUF; #if !defined(__VAXC)B#define tty$w_rb_rdstate tty$r_rb_rdstate_overlay.tty$w_rb_rdstateR#define tty$v_rs_wrap tty$r_rb_rdstate_overlay.tty$r_rb_rdstate_bits.tty$v_rs_wrap6#define tty$a_rb_prm tty$r_rb_prm_overlay.tty$a_rb_prm8#define tty$l_rb_data tty$r_rb_prm_overlay.tty$l_rb_data"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Vb#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TTYRBDEF_LOADED */ ww3[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard EnteVrprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and iVs not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*************************************************************************************** V*****************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JAN-2004 07:50:02 $1$DGA8345:[LIB_H.SRC]TTYDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TTYSYMDEF ***/#ifndef __TTYSYMDEF_LOADED#define __TTYSYMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment _V_save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndeVf __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* */N/* Miscellaneous symbols used by the terminal driver. */N/* V */N/*-- */ N/* */N/* FORK DISPATCHER BIT DEFINITIONS */N/* */#define TTY$M_FD_UNSOL 0x1#define TTY$M_FD_GETAHD 0x2#define TTY$M_FD_DISCONNECT 0x4#define TTY$M_FD_PORTFORK 0x8 V#define TTY$M_FD_UNLINK 0x10#define TTY$M_FD_LINK 0x20 #define TTY$M_FD_ASIAN_CTRL 0x40#define TTY$M_FD_FONT 0x80#define TTY$M_FD_PRELOAD 0x100 #define TTY$M_FD_DEL_CACHE 0x200#define TTY$M_FD_BUSY 0x400S#define TTY$S_FORK 2 /* Old size name, synonym for TTY$S_FORK */ typedef struct _tt_fork {N unsigned tty$v_fd_unsol : 1; /* SEND UNSOLISITED INPUT MESSAGE */N unsigned tty$v_fd_getahd : 1; /* CREATE A TYPEAHEAD BUFFER */N unsignVed tty$v_fd_disconnect : 1; /* DISCONNECT AND DELIVER HANGUPAST */O unsigned tty$v_fd_portfork : 1; /* FORK DISPATCH FOR THE PORT DRIVER */N unsigned tty$v_fd_unlink : 1; /* UNLINK PUCB & LUCB (DETACH) */N unsigned tty$v_fd_link : 1; /* LINK PUCB & LUCB (CONNECT) */N unsigned tty$v_fd_asian_ctrl : 1; /* Create Asian control block */N unsigned tty$v_fd_font : 1; /* Font request delivery */N unsigned tty$v_fd_preload : 1; V /* Deliver preload request */N unsigned tty$v_fd_del_cache : 1; /* request delete Soft-ODL cache */P unsigned tty$v_fd_busy : 1; /**** MUST REMAIN AT THE END ******** */ unsigned tty$v_fill_0_ : 5; } TT_FORK;N/* */N/* POSIX FDT RETURN VALUE DEFINITIONS */N/* */#define VTTY$M_PF_GETAHD 0x1 typedef struct _posix_fdt_ret {N unsigned tty$v_pf_getahd : 1; /* CREATE A TYPEAHEAD BUFFER */ unsigned tty$v_fill_1_ : 7; } POSIX_FDT_RET;N/* */N/* POSIX PUTNXT RETURN VALUE DEFINITIONS */N/* */#define TTY$M_PP_XOFF 0x1#define TTY$M_PP_XON 0x2#define TTY$M_PPV_CTRLY 0x4#define TTY$M_PP_CTRLYFLUSH 0x8#define TTY$M_PP_GETAHD 0x10#define TTY$M_PP_START 0x20#define TTY$M_PP_STOP 0x40#define TTY$M_PP_ECHO 0x80 #define TTY$M_PP_FLUSHONLY 0x100#define TTY$M_PP_MAX 0x200 typedef struct _posix_putnxt {N unsigned tty$v_pp_xoff : 1; /* SEND XOFF */N unsigned tty$v_pp_xon : 1; /* SEND XON */N unsigned tty$v_pp_ctrly : 1; /* DELIVER CTRL-Y AST */N un Vsigned tty$v_pp_ctrlyflush : 1; /* CTRL-Y AST AND FLUSH QUEUES */N unsigned tty$v_pp_getahd : 1; /* CREATE TYPEAHEAD */N unsigned tty$v_pp_start : 1; /* CALL TTY$RESUME */N unsigned tty$v_pp_stop : 1; /* CALL TTY$STOP */N unsigned tty$v_pp_echo : 1; /* ECHO (TTY$GETNEXTCHAR) */N unsigned tty$v_pp_flushonly : 1; /* FLUSH I/O QUEUES */N unsigned tty$v_pp_max : 1; !V /*** MUST BE LAST *** */ unsigned tty$v_fill_2_ : 6; } POSIX_PUTNXT;N/* */N/* POSIX GETNXT RETURN VALUE DEFINITIONS */N/* */#define TTY$M_PG_XON 0x1#define TTY$M_PG_LOOP 0x2#define TTY$M_PG_WRITEDONE 0x4 typedef struct _posix_getnxt {N unsigned tty$v_pg_xon : 1; "V/* SEND XON */N unsigned tty$v_pg_loop : 1; /* GO BACK TO GETNXT */N unsigned tty$v_pg_writedone : 1; /* Finish current write */ unsigned tty$v_fill_3_ : 5; } POSIX_GETNXT;N/* */N/* POSIX READERROR RETURN VALUE DEFINITIONS */N/* */#define TT #VY$M_PR_PURGEAHEAD 0x1#define TTY$M_PR_FLUSH 0x2 !typedef struct _posix_readerror {N unsigned tty$v_pr_purgeahead : 1; /* PURGE TYPEAHEAD */N unsigned tty$v_pr_flush : 1; /* FLUSH I/O QUEUES */ unsigned tty$v_fill_4_ : 6; } POSIX_READERROR;N/* */N/* CHARACTER CONSTANTS */N/* $V */N#define TTY$C_CTRLA 1 /* 1 */N#define TTY$C_CTRLB 2 /* 2 */N#define TTY$C_CTRLC 3 /* 3 */N#define TTY$C_CTRLD 4 /* 4 */N#define TTY$C_CTRLE 5 /* 5 */N#define TTY$C_CTRLF 6 /* 6 %V */N#define TTY$C_BELL 7 /* 7 */N#define TTY$C_BS 8 /* 8 */N#define TTY$C_TAB 9 /* 9 */N#define TTY$C_LF 10 /* 10 */N#define TTY$C_VT 11 /* 11 */N#define TTY$C_FF 12 /* 12 */N#define &VTTY$C_CR 13 /* 13 */N#define TTY$C_CTRLN 14 /* 14 */N#define TTY$C_CTRLO 15 /* 15 */N#define TTY$C_CTRLP 16 /* 16 */N#define TTY$C_CTRLQ 17 /* 17 (XON) */N#define TTY$C_CTRLR 18 /* 18 */N#define TTY$C_CTRLS 19 'V /* 19 (XOFF) */N#define TTY$C_CTRLT 20 /* 20 */N#define TTY$C_CTRLU 21 /* 21 */N#define TTY$C_CTRLV 22 /* 22 */N#define TTY$C_CTRLW 23 /* 23 */N#define TTY$C_CTRLX 24 /* 24 */N#define TTY$C_CTRLY 25 /* 25 (V */N#define TTY$C_CTRLZ 26 /* 26 */N#define TTY$C_ESCAPE 27 /* 27 */#define TTY$C_XON 17#define TTY$C_XOFF 19#define TTY$C_BLANK 32#define TTY$C_DOLLAR 36#define TTY$C_PLUS 43#define TTY$C_ZERO 48#define TTY$C_ONE 49#define TTY$C_SCRIPT 96#define TTY$C_LOWA 97#define TTY$C_LOWZ 123#define TTY$C_LOWESC1 125#define TTY$C_LOWESC2 126#define TTY$C_DELETE 127#def )Vine TTY$C_NL 128#define TTY$C_CSI 155N/* */N/* Miscellaneous values */J/* */#define TTY$C_MAXPAGLEN 255#define TTY$C_MAXPAGWID 511#define TTY$C_HIGHIPL 22N/* */N/* EDIT READ STATES (STORED IN THE MODE FIELD OF THE READ BUFF*VER) */N/* */N#define TTY$K_ER_NORMAL 0 /* NORMAL CONTROL-R OR CONTROL-U */O#define TTY$K_ER_CLRECHO 1 /* ECHO WITH TABS EXPANDED TO SPACES */N#define TTY$K_ER_ECHLINE 2 /* ECHO FROM GIVEN STRING */R#define TTY$K_ER_UPDCURSOR 3 /* UPDATE THE CURSOR POSITION THEN EXIT */N#define TTY$K_ER_EXITING 4 /* EXIT NOW */P#d+Vefine TTY$K_ER_MOVECURSOR 5 /* MOVE THE CURSOR TO ITS FINAL PLACE */N#define TTY$K_ER_CLRREST 6 /* CLEAR THE REST OF THE LINE */N#define TTY$K_ER_PRMECHO 7 /* ECHO OUT A PROMPT */N#define TTY$K_ER_PRMECHO1 8 /* RETURN STATE FOR PROMPT ECHOING */N#define TTY$K_ER_AESECHO 9 /* ECHO AES STRING ALONE */N#define TTY$K_ER_RVECHO 10 /* ECHO READ VERIFY STRING */N#define TTY$K_ER_SIMCEOL 1,V1 /* SIMULATE CLEAR TO END OF LINE */N/* */N/* EDITING TOKENS */N/* */N#define TTY$K_ET_CTRLU 1 /* CONTROL-U */N#define TTY$K_ET_CTRLR 2 /* CONTROL-R */N#define TTY$K_ET_DELEFT 3 /* DELETE CH-VARACTER LEFT */N#define TTY$K_ET_ESCAPE 4 /* ESCAPE PREFIX CHARACTER */N/****** END OF THE NORMAL EDITING CHARACTERRSn */N#define TTY$K_ET_BACK_CHAR 5 /* BACKUP 1 CHARACTER */N#define TTY$K_ET_FORWARD_CHAR 6 /* MOVE FORWARD 1 CHARCTER */N#define TTY$K_ET_MOVE_EOL 7 /* MOVE TO THE END OF LINE */O#define TTY$K_ET_MOVE_BOL 8 /* MOVE TO THE BEGINNING OF THE LINE *.V/N#define TTY$K_ET_DELETE_WORD 9 /* DELETE WORD TO THE LEFT */N#define TTY$K_ET_QUOTING 10 /* AND THE QUOTE CHARACTER */N#define TTY$K_ET_RECALL 11 /* RECALL THE LAST Command */X#define TTY$K_ET_TOGGEL 12 /* TOGGEL BETWEEN INSERT AND OVERSTRIKE MODES */N#define TTY$K_ET_UNUSED 13 /* *** MUST REMAIN AT THE END *** */d#define TTY$K_ET_TERMINATE 14 /* INDICATES CHARACTERS NOT ALLOWED IN EDITING INPUT/V LINE */#define TTY$K_EDITNORMAL 4N/* */N/* INTERNAL FUNCTION CODES */N/* */N#define TTY$C_FC_READ 0 /* 0 READ FUNCTION */N#define TTY$C_FC_WRITE 1 /* 1 WRITE FUNCTION */N#define TTY$C_FC_SETM 2 /* 2 SET MODE 0V */N#define TTY$C_FC_SETC 3 /* 3 SET CHAR */N#define TTY$C_FC_HANGUP 4 /* 4 HANGUP */N#define TTY$C_FC_MAINT 5 /* 5 MAINTENCE FUNCTION */N#define TTY$C_FC_CTRL 6 /* 6 CONTROL ENABLE */N#define TTY$C_FC_CONNECT 7 /* 7 CONNECT TO DETACHED TERMINAL */Q#define TTY$C_FC_DISCON 8 /* 8 DISCONNECT FROM ATTACHED TERMINAL */N#define TT1VY$C_FC_POSIXREAD 9 /* 9 POSIX READ */P#define TTY$C_FC_POSIXWRITE 10 /* 10 POSIX WRITE - MAPS TO VMS WRITE */N#define TTY$C_FC_POSIXSETM 11 /* 11 POSIX SET MODE */N#define TTY$C_FC_ASSETM 12 /* 12 Asian set mode */N#define TTY$C_FC_ASSETC 13 /* 13 Asian set characteristics */N/* */N/* CHARACTER CHARACTERISTICS 2V */N/* */#define TTY$M_CH_LOWER 0x8#define TTY$M_CH_SPEC 0x10#define TTY$M_CH_CTRL 0x20#define TTY$M_CH_CTRL3 0x40#define TTY$M_CH_CTRL2 0x80[#define TTY$S_CHAR_CHAR 1 /* Old size name, synonym for TTY$S_TT_CHAR_CHAR */ typedef struct _tt_char_char { unsigned tty$v_ch_fill : 3; unsigned tty$v_ch_lower : 1; unsigned tty$v_ch_spec : 1; 3Vunsigned tty$v_ch_ctrl : 1; unsigned tty$v_ch_ctrl3 : 1; unsigned tty$v_ch_ctrl2 : 1; } TT_CHAR_CHAR; N/*++ */N/* */N/* ASDRIVER symbols */N/* */N/*-- 4V */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TTYSYMDEF_LOADED */ ww[UM/***************************************************************************/M/** 5V **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/6VM/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************7V****************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:21 by OpenVMS SDL V3.7 */F/* Source: 14-JAN-2004 07:50:02 $1$DGA8345:[LIB_H.SRC]TTYDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TTYTADEF ***/#ifndef __TTYTADEF_LOA8VDED#define __TTYTADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#def9Vine __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* TYPEAHEAD BUFFER :V */N/* */N/* DESCRIPTION: */I/* THIS BUFFER IS USED TO STORE CHARACTERS BEFORE PROCESSING AND */N/* MOVING THEM INTO THE USERS READ BUFFER. */J/* ALLOCATED ON UNSOLICITED DATA OR THE FIRST READ POSTED ON A TERMINAL */N/* LINE. ;V */N/*-- */ N#define TTY$K_TA_RCLLEN 256 /* LENGTH OF RECALL */Z#define TTY$S_TTYTADEF 284 /* Old size name, synonym for TTY$S_TT_TYPE_AHD */ typedef struct _tt_type_ahd {N/* THE LENGTH OF THE RECALL BUFFER */N int (*tty$l_ta_put)(); /* PUT POINTER */N int (*tty$l_ta_get)(); /* GETVize __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TTYTADEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is?V not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authoriz@Ved to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************* AV***********/=/* Created: 7-Oct-2024 15:23:35 by OpenVMS SDL V3.7 */I/* Source: 16-MAR-2004 09:30:01 $1$DGA8345:[LIB_H.SRC]TTYUCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TTYUCBDEF ***/#ifndef __TTYUCBDEF_LOADED#define __TTYUCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomemberBV_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(_CV_VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* $TTYUCBDEF follows here only because there is no way to get the */N/* UCB$K_LENGTH symbol into another module. TTYUCBDEF was formerly */N/* included in TTYDEF.MAR. DV */N/* */N/* TERMINAL DRIVER DEFINITIONS */N/* */N/* These definitions define the device dependent extensions of the UCB. */N/* Certain portions of the ucb are assumed to be contiguous and must not */N/* be split. These areas are documented in the following definitions. EV */N/* */  #include   9#ifdef __cplusplus /* Define structure prototypes */struct _ucb$r_fr3_overlay; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ltrm_ucb {#pragma __nomember_alignment UCFVB ucb$r_ucb;N/* */N/* Logical terminal UCB extension */N/* */N struct _acb *ucb$l_tl_ctrly; /* CONTROL Y AST BLOCK LIST HEAD */N struct _acb *ucb$l_tl_ctrlc; /* CONTROL C AST BLOCK LIST HEAD */N unsigned int ucb$l_tl_outband; /* OUT OF BAND CHARACTER MASK */N int ucb$GVl_tl_bandque; /* OUT OF BAND AST QUEUE */N struct _ucb *ucb$l_tl_phyucb; /* THE PHYSICAL UCB ADDRESS */N unsigned int ucb$l_tl_ctlpid; /* CONTROLING PID (USED WITH SPAWN) */N unsigned __int64 ucb$q_tl_brkthru; /* FACILITY BROADCAST BITMASK */N void *ucb$l_tl_posix_data; /* POSIX PTC POINTER */N void *ucb$l_tl_asian_data; /* ASIAN DATA POINTER */ __union {N unsigned char HVucb$b_tl_a_mode; /* CURRENT ASIAN MODES */N unsigned int ucb$l_tl_a_charset; /* CHARACTER SET BITMASK */" } ucb$r_tl_a_mode_overlay;N void *ucb$l_tl_a_fi_ucb; /* POINTER TO ASIAN INPUT SERVER */N/* */N/* Terminal class driver dependant region */N/* Split here between local and remote terminal UCB's, each of */N/* which hasIV it's own type. */N/* */ } LTRM_UCB; #if !defined(__VAXC)?#define ucb$b_tl_a_mode ucb$r_tl_a_mode_overlay.ucb$b_tl_a_modeE#define ucb$l_tl_a_charset ucb$r_tl_a_mode_overlay.ucb$l_tl_a_charset"#endif /* #if !defined(__VAXC) */ #define UCB$C_TL_LENGTH 544#define UCB$K_TL_LENGTH 544 #define ucb$r_ltrm_ucb ucb$r_ucb#define TTY$M_ST_POWER 0x1#define TTJVY$M_ST_CTRLS 0x2#define TTY$M_ST_LOSTCTS 0x4#define TTY$M_ST_MODEM_OFF 0x8 #define TTY$M_ST_POSIXSTALL 0x10#define TTY$M_ST_FILL 0x20#define TTY$M_ST_CURSOR 0x40#define TTY$M_ST_SENDLF 0x80 #define TTY$M_ST_BACKSPACE 0x100#define TTY$M_ST_MULTI 0x200#define TTY$M_ST_WRITE 0x400!#define TTY$M_ST_POSIXWRITE 0x800#define TTY$M_ST_EOL 0x1000 #define TTY$M_ST_EDITREAD 0x2000 #define TTY$M_ST_RDVERIFY 0x4000#define TTY$M_ST_RECALL 0x8000#define TTY$M_ST_READ 0x10000"#define TTY$KVM_ST_POSIXREAD 0x20000#define TTY$M_ST_CTRLO 0x1#define TTY$M_ST_DEL 0x2#define TTY$M_ST_PASALL 0x4#define TTY$M_ST_NOECHO 0x8#define TTY$M_ST_WRTALL 0x10#define TTY$M_ST_PROMPT 0x20#define TTY$M_ST_NOFLTR 0x40#define TTY$M_ST_ESC 0x80#define TTY$M_ST_BADESC 0x100#define TTY$M_ST_NL 0x200#define TTY$M_ST_REFRSH 0x400#define TTY$M_ST_ESCAPE 0x800#define TTY$M_ST_TYPFUL 0x1000#define TTY$M_ST_SKIPLF 0x2000#define TTY$M_ST_ESC_O 0x4000#define TTY$M_ST_WRAP 0x8000LV#define TTY$M_ST_OVRFLO 0x10000#define TTY$M_ST_AUTOP 0x20000#define TTY$M_ST_CTRLR 0x40000!#define TTY$M_ST_SKIPCRLF 0x80000!#define TTY$M_ST_EDITING 0x100000##define TTY$M_ST_TABEXPAND 0x200000!#define TTY$M_ST_QUOTING 0x400000$#define TTY$M_ST_OVERSTRIKE 0x800000##define TTY$M_ST_TERMNORM 0x1000000!#define TTY$M_ST_ECHAES 0x2000000#define TTY$M_ST_PRE 0x4000000$#define TTY$M_ST_NINTMULTI 0x8000000%#define TTY$M_ST_RECONNECT 0x10000000"#define TTY$M_ST_CTSLOW 0x20000000$#defMVine TTY$M_ST_TABRIGHT 0x40000000#define UCB$M_TT_XXPARITY 0x1#define UCB$M_TT_DISPARERR 0x2#define UCB$M_TT_USERFRAME 0x4#define UCB$M_TT_LEN 0x18#define UCB$M_TT_STOP 0x20#define UCB$M_TT_PARTY 0x40#define UCB$M_TT_ODD 0x80#define TTY$M_TANK_PREMPT 0x100#define TTY$M_TANK_STOP 0x200#define TTY$M_TANK_HOLD 0x400#define TTY$M_TANK_BURST 0x800#define TTY$M_TANK_DMA 0x1000#define TTY$M_PC_NOTIME 0x1#define TTY$M_PC_DMAENA 0x2#define TTY$M_PC_DMAAVL 0x4#define TTNVY$M_PC_PRMMAP 0x8#define TTY$M_PC_MAPAVL 0x10#define TTY$M_PC_XOFAVL 0x20#define TTY$M_PC_XOFENA 0x40#define TTY$M_PC_NOCRLF 0x80#define TTY$M_PC_BREAK 0x100#define TTY$M_PC_PORTFDT 0x200#define TTY$M_PC_NOMODEM 0x400##define TTY$M_PC_NODISCONNECT 0x800"#define TTY$M_PC_SMART_READ 0x1000!#define TTY$M_PC_ACCPORNAM 0x2000#define TTY$M_PC_FRAME 0x4000$#define TTY$M_PC_MULTISESSION 0x8000#define UCB$M_TT_DSBL 0x80  9#ifdef __cplusplus /* Define structure prototypes *OV/ struct _twp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _tty_ucb {#pragma __nomember_alignment LTRM_UCB ucb$r_ltrmucb;N/* READ TIMEOUT CONTROL */N unsigned int ucb$l_tt_rdue; /* ABSTIME WHEN READ TIMEOUT DUE */N void (*u PVcb$l_tt_rtimou)(); /* ADDRESS OF READ TIMEOUT ROUTINE */N/* TERMINAL DRIVER STATE TABLE */N/* (NOTE: Any changes made to this state table must also be made to */N/* the SX state table.) */ __union {N unsigned __int64 ucb$q_tt_state; /* CURRENT UNIT STATE VECTOR */ __struct { __union {- unsigned int ucb$l_tt_state1; QV __struct {N unsigned tty$v_st_power : 1; /* */N unsigned tty$v_st_ctrls : 1; /* */Q unsigned tty$v_st_lostcts : 1; /* Reserved for future work */N unsigned tty$v_st_modem_off : 1; /* */S unsigned tty$v_st_posixstall : 1; /* POSIX timed output wait */N unsigned tty$v_st_fill : 1; /* RV */N unsigned tty$v_st_cursor : 1; /* */N unsigned tty$v_st_sendlf : 1; /* */N unsigned tty$v_st_backspace : 1; /* */N unsigned tty$v_st_multi : 1; /* */0 unsigned tty$v_st_write : 1;T unsigned tty$v_st_posixwrite : 1; /* POSIX special case write */N unsigned tty$v_st_eol : SV1; /* */N unsigned tty$v_st_editread : 1; /* */N unsigned tty$v_st_rdverify : 1; /* */N unsigned tty$v_st_recall : 1; /* */N unsigned tty$v_st_read : 1; /* */N unsigned tty$v_st_posixread : 1; /* *// unsigned tty$v_fill_0_ : 6;- TV} ucb$r_tt_state1_fields;* } ucb$r_tt_state1_overlay; __union {- unsigned int ucb$l_tt_state2; __struct {N unsigned tty$v_st_ctrlo : 1; /* */N unsigned tty$v_st_del : 1; /* */N unsigned tty$v_st_pasall : 1; /* */N unsigned tty$v_st_noecho : 1; /* */N UV unsigned tty$v_st_wrtall : 1; /* */N unsigned tty$v_st_prompt : 1; /* */N unsigned tty$v_st_nofltr : 1; /* */N unsigned tty$v_st_esc : 1; /* */N unsigned tty$v_st_badesc : 1; /* */N unsigned tty$v_st_nl : 1; /* */N unsigned tty$v_st_VVrefrsh : 1; /* */N unsigned tty$v_st_escape : 1; /* */N unsigned tty$v_st_typful : 1; /* */N unsigned tty$v_st_skiplf : 1; /* */N unsigned tty$v_st_esc_o : 1; /* */N unsigned tty$v_st_wrap : 1; /* */N unsigned tty$v_st_ovrflo : 1; /* WV */N unsigned tty$v_st_autop : 1; /* */N unsigned tty$v_st_ctrlr : 1; /* */N unsigned tty$v_st_skipcrlf : 1; /* */N unsigned tty$v_st_editing : 1; /* */N unsigned tty$v_st_tabexpand : 1; /* */N unsigned tty$v_st_quoting : 1; /* */N XV unsigned tty$v_st_overstrike : 1; /* */N unsigned tty$v_st_termnorm : 1; /* */N unsigned tty$v_st_echaes : 1; /* */N unsigned tty$v_st_pre : 1; /* */N unsigned tty$v_st_nintmulti : 1; /* */N unsigned tty$v_st_reconnect : 1; /* */N unsigned tty$v_s YVt_ctslow : 1; /* */N unsigned tty$v_st_tabright : 1; /* *// unsigned tty$v_fill_1_ : 1;- } ucb$r_tt_state2_fields;* } ucb$r_tt_state2_overlay;% } ucb$r_tt_state_q_block;! } ucb$r_tt_state_overlay;N struct _ucb *ucb$l_tt_logucb; /* ADDRESS OF THE LOGICAL UCB */N/* DEFAULT CHARACTERISTICS */N ZVunsigned int ucb$l_tt_dechar; /* DEFAULT DEVICE CHARACTERISTICS */N unsigned int ucb$l_tt_decha1; /* DEFAULT DEVICE CHAR EXTENSIONS */N unsigned int ucb$l_tt_decha2; /* MORE DEVICE CHARACTERISTICS */N unsigned int ucb$l_tt_decha3; /* ANOTHER DEVICE CHAR EXTENSIONS */N/* WRITE QUEUE POINTERS */ char ucb$b_fill_2_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre [VDECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN struct _twp *ucb$l_tt_wflink; /* Write queue forward link. */#pragma __nomember_alignmentN struct _twp *ucb$l_tt_wblink; /* Write queue backward link. */N struct _twp *ucb$l_tt_wrtbuf; /* Current write buffer block. */N/* ADDRESS AND LENGTH OF MULTI-ECHO STRING */N void *ucb$l_tt_multi; /* CUR \VRENT MULTIECHO BUFFER ADDRESS */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned short int ucb$w_tt_multilen; /* LENGTH OF STRING TO OUTPUT */#pragma __nomember_alignment char ucb$b_fill_3_ [2];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword ]V#else#pragma __nomember_alignment#endifN unsigned short int ucb$w_tt_smltlen; /* SAVED MULTI LENGTH */#pragma __nomember_alignment char ucb$b_fill_4_ [2];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN void *ucb$l_tt_smlt; /* AND THE SAVED ADDRESS */N/*-- *******************************************^V*************************** */N/* DEFAULT SPEED, FILL ,PARITY (MUST BE CONTIGUOUS) */N/*++ ******************************************************************* */#pragma __nomember_alignmentN unsigned short int ucb$w_tt_despee; /* DEFAULT SPEED */N unsigned char ucb$b_tt_decrf; /* DEFAULT CR FILL */N unsigned char ucb$b_tt_delff; /* DEFAULT LF FILL */N unsigned char ucb$b_tt_depari; /* D_VEFAULT PARITY/CHAR SIZE */) unsigned char ucb$b_tt_defspe_spare1;. unsigned short int ucb$w_tt_defspe_spare2;N/*-- ********************************************************************** */N/* */N/* DEFAULT TERMINAL TYPE AND SIZE */N/* */P/*++ ****************************************************`V******************* */N unsigned short int ucb$w_tt_desize; /* DEFAULT LINE SIZE */N unsigned char ucb$b_tt_detype; /* DEFAULT TERMINAL TYPE */N unsigned char ucb$b_tt_spare1; /* SPARE BYTE MUST FOLLOW */N/*-- ********************************************************************** */N/* SPEED, FILL, PARITY (MUST BE CONTIGUOUS) */N/*++ ***************************************************************** */ aV __union {N unsigned short int ucb$w_tt_speed; /* SPEED CODES (SPLIT SPEED) */ __struct {N unsigned char ucb$b_tt_tspeed; /* TRANSMIT SPEED */N unsigned char ucb$b_tt_rspeed; /* RECEIVE SPEED */$ } ucb$r_tt_speed_fields;! } ucb$r_tt_speed_overlay;N unsigned char ucb$b_tt_crfill; /* NUMBER FILLS TO OUTPUT ON CR */N unsigned char ucb$b_tt_lffill; /* NUMBER FILLS TO OUTPUT ON LF bV*/ __union {S unsigned char ucb$b_tt_parity; /* PARITY AND CHARACTER SIZE DEFINITIONS */ __struct {N unsigned ucb$v_tt_xxparity : 1; /* UNUSED ?? */R unsigned ucb$v_tt_disparerr : 1; /* SPECIFY DISREGARD PARITY ERRORS */N unsigned ucb$v_tt_userframe : 1; /* SPECIFY USER FRAME SETUP */N unsigned ucb$v_tt_len : 2; /* CHARACTER LENGTH */N unsigned ucb$v_tt_stop : 1; /* STOP BITS cV */N unsigned ucb$v_tt_party : 1; /* PARITY ENABLED */N unsigned ucb$v_tt_odd : 1; /* ODD PARITY */# } ucb$r_tt_parity_bits; } ucb$r_parity_overlay;& unsigned char ucb$b_tt_par_spare1;+ unsigned short int ucb$w_tt_par_spare2;N/*-- ****************************************************************** */N/* Typeahead buffer address */N dV void *ucb$l_tt_typahd; /* TYPEAHEAD BUFFER ADDRESS */N/* CURRENT CURSOR AND LINE POSITION FOR FORMATTED OPERATIONS */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned short int ucb$w_tt_cursor; /* CURRENT CURSOR POSITION */#pragma __nomember_alignment char ucb$b_fill_5_ [2];c#if !defined(__NOBeVASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned char ucb$b_tt_line; /* CURRENT LINE ON PAGE */#pragma __nomember_alignment char ucb$b_fill_6_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN fVunsigned char ucb$b_tt_lastc; /* LAST FORMATTED OUTPUT CHARACTER */N/* Number of back spaces to output for non-ansi terminals */#pragma __nomember_alignment char ucb$b_fill_7_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned short int ucb$w_tt_bsplen; /* NUMBER OF BACKSPACES */N/* FILL HANDLING gV */#pragma __nomember_alignment char ucb$b_fill_8_ [2];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned char ucb$b_tt_fill; /* CURRENT FILL COUNT */N/* ESCAPE SYNTAX RULE STATE. */#pragma __nomember_alignment ch hVar ucb$b_fill_9_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifO unsigned char ucb$b_tt_esc; /* CURRENT READ ESCAPE SYNTAX STATE */#pragma __nomember_alignment char ucb$b_fill_10_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else iV#pragma __nomember_alignment#endifN unsigned char ucb$b_tt_esc_o; /* OUPUT ESCAPE STATE */N/* Count of characters in interrupt string */#pragma __nomember_alignment char ucb$b_fill_11_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif" unsigned char ucb$b_tt_intcnt;N/* Bit used for mode jVm control */#pragma __nomember_alignment char ucb$b_fill_12_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif\ unsigned short int ucb$w_tt_unitbit; /* BIT USED TO ENABLE AND DISABLE MODEM CONTROL. */N/* PORT SPECIFIC OUTPUT CONTROL */#pragma __nomember_ali kVgnment char ucb$b_fill_13_ [2];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentS unsigned short int ucb$w_tt_hold; /* UNIT HOLDING TANK AND PORT DISPATCH */ __struct {N unsigned char tty$b_tank_char; /* CHARACTER */N unsigned tty$v_tank_prempt : 1; lV/* SEND PREMPT CHARACTER */N unsigned tty$v_tank_stop : 1; /* STOP OUTPUT */N unsigned tty$v_tank_hold : 1; /* CHAR IN TANK */N unsigned tty$v_tank_burst : 1; /* BURST ACTIVE */\ unsigned tty$v_tank_dma : 1; /* DMA ACTIVE **** SHOULD MOVE BEFORE BURST **** */( unsigned tty$v_fill_14_ : 3;! } ucb$r_tt_hold_bits; } ucb$r_tt_hold_overlay; char ucb$b_fill_15_ mV[2];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned char ucb$b_tt_prempt; /* THE BYTE USED TO PREMPT INPUT */#pragma __nomember_alignment char ucb$b_fill_16_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember nV_alignment#endifN char ucb$b_tt_outype; /* TYPE OF OUTPUT THAT THIS CALL */N/* CLASS & PORT VECTOR POINTERS */#pragma __nomember_alignment char ucb$b_fill_17_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned char (*ucb$l_tt_getnxt)(); /* ADDRESS OF CLASS INPUT ROUTINE oV*/#pragma __nomember_alignmentN unsigned char (*ucb$l_tt_putnxt)(); /* ADDRESS OF CLASS OUTPUT ROUTINE */N int ucb$l_tt_class; /* ADDRESS OF CLASS VECTOR */N int ucb$l_tt_port; /* ADDRESS OF PORT VECTOR */O void *ucb$l_tt_outadr; /* ADDRESS OF OUTPUT CURRENT STREAM */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#elsepV#pragma __nomember_alignment#endifN unsigned short int ucb$w_tt_outlen; /* LENGTH OF OUTPUT STREAM */#pragma __nomember_alignment char ucb$b_fill_18_ [2];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment% unsigned int ucb$l_tt_prtctl;N unsigned short int ucb$w_tt_prtctl; /* THEqV PORT DRIVER CONTROL WORD */ __struct {T unsigned tty$v_pc_notime : 1; /* IF SET NO TIMEOUT WILL BE CALCULATED */N unsigned tty$v_pc_dmaena : 1; /* DMA CURRENTLY ENABLED */N unsigned tty$v_pc_dmaavl : 1; /* DMA SUPPORTED ON THIS PORT */U unsigned tty$v_pc_prmmap : 1; /* UNIT CAN HAVE PERMANENT MAP REGISTERS */P unsigned tty$v_pc_mapavl : 1; /* MAP REGISTER CURRENTLY ALLOCATED */P unsigned tty$v_pc_xofavl :rV 1; /* AUTO XOFF SUPPORTED ON THIS PORT */N unsigned tty$v_pc_xofena : 1; /* AUTO XOFF CURRENTLY ENABLED */T unsigned tty$v_pc_nocrlf : 1; /* don't do free linefeed after creturn */N unsigned tty$v_pc_break : 1; /* TURN ON OR OFF BREAK */N unsigned tty$v_pc_portfdt : 1; /* PORT CONTAINS FDT ROUTINE */U unsigned tty$v_pc_nomodem : 1; /* Port cannot support modem operations */g unsigned tty$v_pc_nodisconnect : 1; sV/* Device cannot support virtual terminal operations */^ unsigned tty$v_pc_smart_read : 1; /* Port contains additional read capabilities */Q unsigned tty$v_pc_accpornam : 1; /* Port supports access port name */N unsigned tty$v_pc_frame : 1; /* GETNXT and PUTNXT use frame */T unsigned tty$v_pc_multisession : 1; /* part of multi-session terminal */# } ucb$r_tt_prtctl_bits;" } ucb$r_tt_prtctl_overlay;N/* MODEM CONTROL DEFINITIONS tV */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned int ucb$l_tt_ds_st; /* CURRENT MODEM STATE */N unsigned char ucb$b_tt_ds_rcv; /* CURRENT RECEIVE MODEM */#pragma __nomember_alignment char ucb$b_fill_19_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defuVined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned char ucb$b_tt_ds_tx; /* CURRENT TRANSMIT MODEM */#pragma __nomember_alignment char ucb$b_fill_20_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned short int ucb$w_tvVt_ds_tim; /* CURRENT MODEM TIMEOUT */#pragma __nomember_alignment char ucb$b_fill_21_ [2];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN unsigned char ucb$b_tt_maint; /* MAINTENANCE PARAMETERS */ __struct {- unsigned ucb$v_tt_maint_fill : 7;N wV unsigned ucb$v_tt_dsbl : 1; /* LINE DISABLED */" } ucb$r_tt_maint_bits;! } ucb$r_tt_maint_overlay; char ucb$b_fill_22_ [3];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned char ucb$b_tt_oldcpzorg; /* Old cursor position */#pragma __nomember_alignment char ucb$b_fill_23_ [3];c#if xV!defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN unsigned short int ucb$w_tt_fillrup; /* FILL to align next */#pragma __nomember_alignment char ucb$b_fill_24_ [2];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignmentyV#endifN void *ucb$l_tt_fbk; /* PTR TO FALLBACK BLOCK */#pragma __nomember_alignmentN void *ucb$l_tt_rdverify; /* PTR TO READ/VERIFY TABLE */N unsigned int ucb$l_tt_class1; /* CLASS DRIVER LONGWORD */N unsigned int ucb$l_tt_class2; /* AND ANOTHER ONE */\ void *ucb$l_tt_accpornam; /* Address of counted string describing the port */N/* typicall LAT server name / and port name or numbezVr */R/****************************************************************************** */N/* */N/* Asian VMS extension */N/* */R/*++ ************************************************************************** */N void *ucb$l_tt_a_gcbadr; /* Glyph Control Block address {V */N unsigned short int ucb$w_tt_a_edsts; /* Multi-byte line edit states */N unsigned char ucb$b_tt_a_state; /* On-demand loading states */N unsigned char ucb$b_tt_a_parse; /* ODL parse states */N unsigned char ucb$b_tt_a_trans; /* JIS conversion states */N unsigned char ucb$b_tt_a_xedsts; /* Extended line edit states */N unsigned short int ucb$w_tt_a_resrv1; /* Reserved */ __union {N |V unsigned char ucb$b_tt_a_char; /* Default Asian modes */N unsigned int ucb$l_tt_a_dechset; /* Default char set bitmask */" } ucb$r_tt_a_char_overlay; } TTY_UCB; #if !defined(__VAXC)<#define ucb$q_tt_state ucb$r_tt_state_overlay.ucb$q_tt_statem#define ucb$l_tt_state1 ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$l_tt_state1#define tty$v_st_power ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.u}Vcb$r_tt_state1_fields.tty$v_st_power#define tty$v_st_ctrls ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_ctrls#define tty$v_st_lostcts ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_lost\cts#define tty$v_st_modem_off ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_mo\dem_off#define tty$v_st_posixstall ucb$r_tt_state_overlay.u~Vcb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_p\ osixstall#define tty$v_st_fill ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_fill#define tty$v_st_cursor ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_cursor#define tty$v_st_sendlf ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_sendlf#define tty$v_Vst_backspace ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_ba\ckspace#define tty$v_st_multi ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_multi#define tty$v_st_write ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_write#define tty$v_st_posixwrite ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_stateV1_fields.tty$v_st_p\ osixwrite~#define tty$v_st_eol ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_eol#define tty$v_st_editread ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_edi\tread#define tty$v_st_rdverify ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_rdv\erify#define tty$v_st_recall ucb$r_tt_state_overlay.ucb$r_tt_statVe_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_recall#define tty$v_st_read ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_read#define tty$v_st_posixread ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state1_overlay.ucb$r_tt_state1_fields.tty$v_st_po\sixreadm#define ucb$l_tt_state2 ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$l_tt_state2#define tty$v_st_ctrlo ucb$r_tt_state_overlay.Vucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_ctrlo~#define tty$v_st_del ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_del#define tty$v_st_pasall ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_pasall#define tty$v_st_noecho ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_noecho#define tty$v_st_wrtall Vucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_wrtall#define tty$v_st_prompt ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_prompt#define tty$v_st_nofltr ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_nofltr~#define tty$v_st_esc ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_escV#define tty$v_st_badesc ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_badesc|#define tty$v_st_nl ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_nl#define tty$v_st_refrsh ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_refrsh#define tty$v_st_escape ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fiVelds.tty$v_st_escape#define tty$v_st_typful ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_typful#define tty$v_st_skiplf ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_skiplf#define tty$v_st_esc_o ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_esc_o#define tty$v_st_wrap ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_Voverlay.ucb$r_tt_state2_fields.tty$v_st_wrap#define tty$v_st_ovrflo ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_ovrflo#define tty$v_st_autop ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_autop#define tty$v_st_ctrlr ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_ctrlr#define tty$v_st_skipcrlf ucb$r_tt_state_overlay.ucb$r_tt_stat Ve_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_ski\pcrlf#define tty$v_st_editing ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_edit\ing#define tty$v_st_tabexpand ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_ta\bexpand#define tty$v_st_quoting ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_quot\ing#dVefine tty$v_st_overstrike ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_o\ verstrike#define tty$v_st_termnorm ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_ter\mnorm#define tty$v_st_echaes ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_echaes~#define tty$v_st_pre ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_oveVrlay.ucb$r_tt_state2_fields.tty$v_st_pre#define tty$v_st_nintmulti ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_ni\ntmulti#define tty$v_st_reconnect ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_re\connect#define tty$v_st_ctslow ucb$r_tt_state_overlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_ctslow#define tty$v_st_tabright ucb$r_tt_state_oVverlay.ucb$r_tt_state_q_block.ucb$r_tt_state2_overlay.ucb$r_tt_state2_fields.tty$v_st_tab\right<#define ucb$w_tt_speed ucb$r_tt_speed_overlay.ucb$w_tt_speedT#define ucb$b_tt_tspeed ucb$r_tt_speed_overlay.ucb$r_tt_speed_fields.ucb$b_tt_tspeedT#define ucb$b_tt_rspeed ucb$r_tt_speed_overlay.ucb$r_tt_speed_fields.ucb$b_tt_rspeed<#define ucb$b_tt_parity ucb$r_parity_overlay.ucb$b_tt_parityU#define ucb$v_tt_xxparity ucb$r_parity_overlay.ucb$r_tt_parity_bits.ucb$v_tt_xxparityW#define ucb$v_tt_dispaVrerr ucb$r_parity_overlay.ucb$r_tt_parity_bits.ucb$v_tt_disparerrW#define ucb$v_tt_userframe ucb$r_parity_overlay.ucb$r_tt_parity_bits.ucb$v_tt_userframeK#define ucb$v_tt_len ucb$r_parity_overlay.ucb$r_tt_parity_bits.ucb$v_tt_lenM#define ucb$v_tt_stop ucb$r_parity_overlay.ucb$r_tt_parity_bits.ucb$v_tt_stopO#define ucb$v_tt_party ucb$r_parity_overlay.ucb$r_tt_parity_bits.ucb$v_tt_partyK#define ucb$v_tt_odd ucb$r_parity_overlay.ucb$r_tt_parity_bits.ucb$v_tt_odd9#define ucb$w_tt_hold ucb$r_ttV_hold_overlay.ucb$w_tt_holdP#define tty$b_tank_char ucb$r_tt_hold_overlay.ucb$r_tt_hold_bits.tty$b_tank_charT#define tty$v_tank_prempt ucb$r_tt_hold_overlay.ucb$r_tt_hold_bits.tty$v_tank_premptP#define tty$v_tank_stop ucb$r_tt_hold_overlay.ucb$r_tt_hold_bits.tty$v_tank_stopP#define tty$v_tank_hold ucb$r_tt_hold_overlay.ucb$r_tt_hold_bits.tty$v_tank_holdR#define tty$v_tank_burst ucb$r_tt_hold_overlay.ucb$r_tt_hold_bits.tty$v_tank_burstN#define tty$v_tank_dma ucb$r_tt_hold_overlay.ucb$r_tt_hold_bVits.tty$v_tank_dma?#define ucb$l_tt_prtctl ucb$r_tt_prtctl_overlay.ucb$l_tt_prtctl?#define ucb$w_tt_prtctl ucb$r_tt_prtctl_overlay.ucb$w_tt_prtctlT#define tty$v_pc_notime ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_notimeT#define tty$v_pc_dmaena ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_dmaenaT#define tty$v_pc_dmaavl ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_dmaavlT#define tty$v_pc_prmmap ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_prmmapT#define ttVy$v_pc_mapavl ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_mapavlT#define tty$v_pc_xofavl ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_xofavlT#define tty$v_pc_xofena ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_xofenaT#define tty$v_pc_nocrlf ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_nocrlfR#define tty$v_pc_break ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_breakV#define tty$v_pc_portfdt ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_portfdtVV#define tty$v_pc_nomodem ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_nomodem`#define tty$v_pc_nodisconnect ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_nodisconnect\#define tty$v_pc_smart_read ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_smart_readZ#define tty$v_pc_accpornam ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_accpornamR#define tty$v_pc_frame ucb$r_tt_prtctl_overlay.ucb$r_tt_prtctl_bits.tty$v_pc_frame`#define tty$v_pc_multisession ucb$r_tt_prtctl_over Vlay.ucb$r_tt_prtctl_bits.tty$v_pc_multisession<#define ucb$b_tt_maint ucb$r_tt_maint_overlay.ucb$b_tt_maintZ#define ucb$v_tt_maint_fill ucb$r_tt_maint_overlay.ucb$r_tt_maint_bits.ucb$v_tt_maint_fillN#define ucb$v_tt_dsbl ucb$r_tt_maint_overlay.ucb$r_tt_maint_bits.ucb$v_tt_dsbl?#define ucb$b_tt_a_char ucb$r_tt_a_char_overlay.ucb$b_tt_a_charE#define ucb$l_tt_a_dechset ucb$r_tt_a_char_overlay.ucb$l_tt_a_dechset"#endif /* #if !defined(__VAXC) */ #define UCB$C_TT_CLSLEN 776#define UCB$K_TTV_CLSLEN 776 .#define ucb$r_tty_ucb ucb$r_ltrmucb.ucb$r_ucb$#define ucb$r_tty_ltrm ucb$r_ltrmucb#define TTY$M_TP_ABORT 0x1#define TTY$M_TP_ALLOC 0x2#define TTY$M_TP_DLLOC 0x4 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _tpd_ucb {N/* */N/* V */N/* Terminal Port driver dependant extension region */N/* */N/* */#pragma __nomember_alignment TTY_UCB ucb$r_ttyucb;N int ucb$l_tp_map; /* UNIBUS MAP REGISTERS */ __union {N unsigned char ucb$b_tp_stat; /* DMA P VORT SPECIFIC STATUS */Q __struct { /* BITS DEFINED IN THE DMA STATUS WORD */O unsigned tty$v_tp_abort : 1; /* DMA ABORT REQUESTED ON THIS LINE */N unsigned tty$v_tp_alloc : 1; /* ALLOC MAP FORK IN PROGRESS */N unsigned tty$v_tp_dlloc : 1; /* DEALLOCATE MAP FORK IN PROGRESS */( unsigned tty$v_fill_25_ : 5;! } ucb$r_tp_stat_bits; } ucb$r_tp_stat_overlay;" unsigned char ucb$b_tp_spare1;' V unsigned short int ucb$w_tp_spare2; } TPD_UCB; #if !defined(__VAXC)9#define ucb$b_tp_stat ucb$r_tp_stat_overlay.ucb$b_tp_statN#define tty$v_tp_abort ucb$r_tp_stat_overlay.ucb$r_tp_stat_bits.tty$v_tp_abortN#define tty$v_tp_alloc ucb$r_tp_stat_overlay.ucb$r_tp_stat_bits.tty$v_tp_allocN#define tty$v_tp_dlloc ucb$r_tp_stat_overlay.ucb$r_tp_stat_bits.tty$v_tp_dlloc"#endif /* #if !defined(__VAXC) */ #define UCB$C_TP_LENGTH 784#define UCB$K_TP_LENGTH 784#define UCB$C_TT_LENGT VH 784#define UCB$K_TT_LENGTH 784 ;#define ucb$r_tpd_ucb ucb$r_ttyucb.ucb$r_ltrmucb.ucb$r_ucb.#define ucb$r_tpd_ltrm ucb$r_ttyucb.ucb$r_ltrm##define ucb$r_tpd_tty ucb$r_ttyucbN/* TERMINAL DRIVER SX STATE TABLE */N/* (NOTE: Any changes made to this state table must also be made to */N/* the ST state table.) */#define TTY$M_SX_LOSTCTS 0x4 #define TTY$M_SX_POSIXSTALL 0x10 c#if !def Vined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _sx_state {#pragma __nomember_alignment TPD_UCB tty$r_tpducb; __struct {I unsigned tty$v_sx_power : 1; /* */N unsigned tty$v_sx_ctrls : 1; /* */N unsigned tty$v_sx_lostcts : 1; /* Reserved for future wVork */N unsigned tty$v_sx_modem_off : 1; /* */N unsigned tty$v_sx_posixstall : 1; /* POSIX timed output wait */N unsigned tty$v_sx_fill : 1; /* */N unsigned tty$v_sx_cursor : 1; /* */N unsigned tty$v_sx_sendlf : 1; /* */R unsigned tty$v_sx_backspace : 1; /* OUTPUT BACKSPACES FOR SEVERAL LOOPS */N V unsigned tty$v_sx_multi : 1; /* */N unsigned tty$v_sx_write : 1; /* Write state */N unsigned tty$v_sx_posixwrite : 1; /* POSIX Write state */N unsigned tty$v_sx_eol : 1; /* */N unsigned tty$v_sx_editread : 1; /* */N unsigned tty$v_sx_rdverify : 1; /* */N unsigned tty$v_sx_recallV : 1; /* */N unsigned tty$v_sx_read : 1; /* */N unsigned tty$v_sx_posixread : 1; /* */N unsigned tty$v_sx_fillbits : 14; /* END OF FIRST LONGWORD */N unsigned tty$v_sx_ctrlo : 1; /* */N unsigned tty$v_sx_del : 1; /* */N unsigned tty$v_sx_pasall : 1; /* V */N unsigned tty$v_sx_noecho : 1; /* */N unsigned tty$v_sx_wrtall : 1; /* */N unsigned tty$v_sx_prompt : 1; /* */N unsigned tty$v_sx_nofltr : 1; /* */N unsigned tty$v_sx_esc : 1; /* */N unsigned tty$v_sx_badesc : 1; /* */N V unsigned tty$v_sx_nl : 1; /* New line must directly precede */N unsigned tty$v_sx_refrsh : 1; /* refresh, or all breaks. */N unsigned tty$v_sx_escape : 1; /* */N unsigned tty$v_sx_typful : 1; /* */N unsigned tty$v_sx_skiplf : 1; /* */N unsigned tty$v_sx_esc_o : 1; /* */N unsigned tty$v_sx_wrapV : 1; /* */N unsigned tty$v_sx_ovrflo : 1; /* */N unsigned tty$v_sx_autop : 1; /* */N unsigned tty$v_sx_ctrlr : 1; /* */N unsigned tty$v_sx_skipcrlf : 1; /* */N unsigned tty$v_sx_editing : 1; /* */N unsigned tty$v_sx_tabexpand : 1; /* V */N unsigned tty$v_sx_quoting : 1; /* */N unsigned tty$v_sx_overstrike : 1; /* */N unsigned tty$v_sx_termnorm : 1; /* */N unsigned tty$v_sx_echaes : 1; /* */N unsigned tty$v_sx_pre : 1; /* */N unsigned tty$v_sx_nintmulti : 1; /* */N V unsigned tty$v_sx_reconnect : 1; /* */N unsigned tty$v_sx_ctslow : 1; /* */N unsigned tty$v_sx_tabright : 1; /* */$ unsigned tty$v_fill_26_ : 1; } tty$r_tt_state_sx; } SX_STATE; #if !defined(__VAXC)7#define tty$v_sx_power tty$r_tt_state_sx.tty$v_sx_power7#define tty$v_sx_ctrls tty$r_tt_state_sx.tty$v_sx_ctrls;#define tty$v_sx_lostcts tty$r_tt_state_ Vsx.tty$v_sx_lostcts?#define tty$v_sx_modem_off tty$r_tt_state_sx.tty$v_sx_modem_offA#define tty$v_sx_posixstall tty$r_tt_state_sx.tty$v_sx_posixstall5#define tty$v_sx_fill tty$r_tt_state_sx.tty$v_sx_fill9#define tty$v_sx_cursor tty$r_tt_state_sx.tty$v_sx_cursor9#define tty$v_sx_sendlf tty$r_tt_state_sx.tty$v_sx_sendlf?#define tty$v_sx_backspace tty$r_tt_state_sx.tty$v_sx_backspace7#define tty$v_sx_multi tty$r_tt_state_sx.tty$v_sx_multi7#define tty$v_sx_write tty$r_tt_state_sx.tty$v_sx_ VwriteA#define tty$v_sx_posixwrite tty$r_tt_state_sx.tty$v_sx_posixwrite3#define tty$v_sx_eol tty$r_tt_state_sx.tty$v_sx_eol=#define tty$v_sx_editread tty$r_tt_state_sx.tty$v_sx_editread=#define tty$v_sx_rdverify tty$r_tt_state_sx.tty$v_sx_rdverify9#define tty$v_sx_recall tty$r_tt_state_sx.tty$v_sx_recall5#define tty$v_sx_read tty$r_tt_state_sx.tty$v_sx_read?#define tty$v_sx_posixread tty$r_tt_state_sx.tty$v_sx_posixread=#define tty$v_sx_fillbits tty$r_tt_state_sx.tty$v_sx_fillbits7#d Vefine tty$v_sx_ctrlo tty$r_tt_state_sx.tty$v_sx_ctrlo3#define tty$v_sx_del tty$r_tt_state_sx.tty$v_sx_del9#define tty$v_sx_pasall tty$r_tt_state_sx.tty$v_sx_pasall9#define tty$v_sx_noecho tty$r_tt_state_sx.tty$v_sx_noecho9#define tty$v_sx_wrtall tty$r_tt_state_sx.tty$v_sx_wrtall9#define tty$v_sx_prompt tty$r_tt_state_sx.tty$v_sx_prompt9#define tty$v_sx_nofltr tty$r_tt_state_sx.tty$v_sx_nofltr3#define tty$v_sx_esc tty$r_tt_state_sx.tty$v_sx_esc9#define tty$v_sx_badesc tty$r_tt_state_sx. Vtty$v_sx_badesc1#define tty$v_sx_nl tty$r_tt_state_sx.tty$v_sx_nl9#define tty$v_sx_refrsh tty$r_tt_state_sx.tty$v_sx_refrsh9#define tty$v_sx_escape tty$r_tt_state_sx.tty$v_sx_escape9#define tty$v_sx_typful tty$r_tt_state_sx.tty$v_sx_typful9#define tty$v_sx_skiplf tty$r_tt_state_sx.tty$v_sx_skiplf7#define tty$v_sx_esc_o tty$r_tt_state_sx.tty$v_sx_esc_o5#define tty$v_sx_wrap tty$r_tt_state_sx.tty$v_sx_wrap9#define tty$v_sx_ovrflo tty$r_tt_state_sx.tty$v_sx_ovrflo7#define tty$v_sx_autop V tty$r_tt_state_sx.tty$v_sx_autop7#define tty$v_sx_ctrlr tty$r_tt_state_sx.tty$v_sx_ctrlr=#define tty$v_sx_skipcrlf tty$r_tt_state_sx.tty$v_sx_skipcrlf;#define tty$v_sx_editing tty$r_tt_state_sx.tty$v_sx_editing?#define tty$v_sx_tabexpand tty$r_tt_state_sx.tty$v_sx_tabexpand;#define tty$v_sx_quoting tty$r_tt_state_sx.tty$v_sx_quotingA#define tty$v_sx_overstrike tty$r_tt_state_sx.tty$v_sx_overstrike=#define tty$v_sx_termnorm tty$r_tt_state_sx.tty$v_sx_termnorm9#define tty$v_sx_echaes tt Vy$r_tt_state_sx.tty$v_sx_echaes3#define tty$v_sx_pre tty$r_tt_state_sx.tty$v_sx_pre?#define tty$v_sx_nintmulti tty$r_tt_state_sx.tty$v_sx_nintmulti?#define tty$v_sx_reconnect tty$r_tt_state_sx.tty$v_sx_reconnect9#define tty$v_sx_ctslow tty$r_tt_state_sx.tty$v_sx_ctslow=#define tty$v_sx_tabright tty$r_tt_state_sx.tty$v_sx_tabright"#endif /* #if !defined(__VAXC) */ N#define TTY$S_TTYUCB 248 /* Old size name */N#define TTY$S_TTYRTTUCB 248 /* V Old size name */Y#define TTY$S_TTYUCBDEF 792 /* Old size name, synonym for TTYUCB$S_TTYUCB */ M#define ucb$r_sx_state_ucb ucb$r_tpducb.ucb$r_ttyucb.ucb$r_ltrmucb.ucb$r_ucb@#define ucb$r_sx_state_ltrm ucb$r_tpducb.ucb$r_ttyucb.ucb$r_ltrm5#define ucb$r_sx_state_tty ucb$r_tpducb.ucb$r_ttyucb(#define ucb$r_sx_state_tpd ucb$r_tpducb#define FLG$M_CTRLO 0x1#define FLG$M_CANCTRLO 0x2#define FLG$M_VAXTOVAX 0x4#define FLG$M_CTRLC 0x8#define FLG$M_INIT 0Vx10#define FLG$M_RESET_TIMER 0x20#define FLG$M_DECNET_BUSY 0x40#define FLG$M_OUTPUT_BUSY 0x80#define FLG$M_READ_BUSY 0x100#define FLG$M_SENSE_BUSY 0x200#define FLG$M_OOB_CHAR 0x400 #define FLG$M_FLUSH_OUTPUT 0x800!#define FLG$M_CLR_NOBRDCST 0x1000#define FLG$M_READ_ABORT 0x2000!#define FLG$M_READ_ABORTED 0x4000#define FLG$M_ISUPPORT 0x8000"#define FLG$M_PARTIAL_READ 0x10000  9#ifdef __cplusplus /* Define structure prototypes */ struct _wcb; struct _irp; struct V _dcb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _rtt_ucb {N/* */N/* remote terminal extension */N/* */#p Vragma __nomember_alignment LTRM_UCB ucb$r_ltrmucb; __struct {N struct _ucb *ucb$l_rtt_netucb; /* NET DEVICE UCB */N struct _wcb *ucb$l_rtt_netwind; /* NET DEVICE WCB */N struct _irp *ucb$l_rtt_irpfl; /* IRP QUEUE */N struct _irp *ucb$l_rtt_irpbl; /* IRP QUEUE */N struct _irp *ucb$l_rtt_netirp; /* READ NET IIRP */N int ucb$l_rtt_bandinclV; /* OUT OF BAND INCLUDES */N unsigned int ucb$l_rtt_bandinmsk; /* OUT OF BAND INCLUDE MASK */N unsigned int ucb$l_rtt_bandexcl; /* out of band exclude mask */N unsigned int ucb$l_rtt_bandexmsk; /* out of band exclude */N unsigned char ucb$b_rtt_provrs; /* PROTOCOL VERSION */N unsigned char ucb$b_rtt_proeco; /* PROTOCOL ECO */N unsigned short int ucb$w_rtt_link; /* LINK NUMBE VR (for LOGINOUT) */N unsigned char ucb$b_rtt_obj; /* OBJECT NUMBER CONNECTED */N unsigned short int ucb$w_rtt_systype; /* SYSTEM TYPE (VMS=7) */N unsigned char ucb$b_rtt_fillbyte; /* fill - use when convenient */I/* CTERM driver only */ __union {N unsigned int ucb$l_ct_flags; /* MISC FLAGS */ __struct {N unsigned flg$v_ctrlo : 1V; /* CTRLO IN PROGRESS */N unsigned flg$v_canctrlo : 1; /* CANCEL CTRLO ON WRITE */N unsigned flg$v_vaxtovax : 1; /* VAX TO VAX */N unsigned flg$v_ctrlc : 1; /* CTRL/C DELIVERED */N unsigned flg$v_init : 1; /* AWAITING FIRST WRITE */Q unsigned flg$v_reset_timer : 1; /* Restart timer due to write. */N unsigned flg$v_decnet_busy : 1; /* DECnet OutpVut task busy. */N unsigned flg$v_output_busy : 1; /* Output task busy. */N unsigned flg$v_read_busy : 1; /* Read task busy. */N unsigned flg$v_sense_busy : 1; /* Sense task busy. */O unsigned flg$v_oob_char : 1; /* Process OOB character later. */Z unsigned flg$v_flush_output : 1; /* Flush output for out-of-band abort. */_ unsigned flg$v_clr_nobrdcst : 1; /* Don't broadcast until Vafter first write. */N unsigned flg$v_read_abort : 1; /* Read abort in progress. */U unsigned flg$v_read_aborted : 1; /* Read has already been aborted. */N unsigned flg$v_isupport : 1; /* Support of ISUPPORT msg */O unsigned flg$v_partial_read : 1; /* Partial read in progress */, unsigned flg$v_fill_27_ : 7;& } ucb$r_ct_flags_bits;% } ucb$r_ct_flags_overlay;N struct _irp *ucb$lV_ct_wiirp; /* WRITE IIRP */N struct _tqe *ucb$l_ct_tqe; /* TQE ADDRESS */N struct _dcb *ucb$l_ct_netqfl; /* Queue of DCB's waiting */N struct _dcb *ucb$l_ct_netqbl; /* for write IRP */N struct _irp *ucb$l_ct_senseqfl; /* Queue for pending */N struct _irp *ucb$l_ct_senseqbl; /* IO$_SENSExxxx IRPs. */N struct _irp *ucb$l_ct_readqfl; /* Queue forV pending */N struct _irp *ucb$l_ct_readqbl; /* read IRPs. */O struct _dcb *ucb$l_ct_wrtdcb; /* First DCB in current write chain. */N struct _dcb *ucb$l_ct_curdcb; /* Last DCB added to write chain. */N unsigned short int ucb$w_ct_remsiz; /* Remaining size in message. */N short int ucb$w_ct_qdcbcnt; /* Number of queued DCBs. */N unsigned short int ucb$w_ct_maxmsg; /* MAX WRITE TO NET SIZE V*/N unsigned short int ucb$w_ct_maxread; /* MAX READ IN SERVER */N unsigned int ucb$l_ct_legalmsg; /* LEGAL MESSAGE MASK */N unsigned char ucb$b_ct_version; /* CTERM VERSION */N unsigned char ucb$b_ct_eco; /* CTERM ECO */N unsigned short int ucb$w_ct_speed; /* SPEED */N unsigned char ucb$b_ct_crfill; /* CR FILL */N unsigned char Vucb$b_ct_lffill; /* LF FILL */N unsigned short int ucb$w_ct_parity; /* CTERM PARITY */P unsigned int ucb$l_ct_include; /* INCLUDE OUT-OF-BAND CHARACTER MASK */P unsigned int ucb$l_ct_exclude; /* EXCLUDE OUT-OF-BAND CHARACTER MASK */N unsigned int ucb$l_ct_abort; /* ABORT OUT-OF-BAND CHARACTER MASK */N unsigned char ucb$b_ct_oob_char; /* Received out of band character. */N unsigned char ucb$b_ct_fill_byte [43 V]; /* fill */N unsigned short int ucb$w_ct_prtctl; /* Same as UCB$W_TT_PRTCTL */N unsigned __int64 ucb$q_ct_isupport; /* Messages supported */N unsigned int ucb$l_ct_fill_longword; /* fill */ } ucb$r_rttucb; char ucb$b_fill_28_ [6]; } RTT_UCB; #if !defined(__VAXC)6#define ucb$l_rtt_netucb ucb$r_rttucb.ucb$l_rtt_netucb8#define ucb$l_rtt_netwind ucb$r_rttucb.ucb$l_rtt_netwind4#define ucb$l_rtt_ Virpfl ucb$r_rttucb.ucb$l_rtt_irpfl4#define ucb$l_rtt_irpbl ucb$r_rttucb.ucb$l_rtt_irpbl6#define ucb$l_rtt_netirp ucb$r_rttucb.ucb$l_rtt_netirp:#define ucb$l_rtt_bandincl ucb$r_rttucb.ucb$l_rtt_bandincl<#define ucb$l_rtt_bandinmsk ucb$r_rttucb.ucb$l_rtt_bandinmsk:#define ucb$l_rtt_bandexcl ucb$r_rttucb.ucb$l_rtt_bandexcl<#define ucb$l_rtt_bandexmsk ucb$r_rttucb.ucb$l_rtt_bandexmsk6#define ucb$b_rtt_provrs ucb$r_rttucb.ucb$b_rtt_provrs6#define ucb$b_rtt_proeco ucb$r_rttucb.ucb$b_rtt_proeco2#defVine ucb$w_rtt_link ucb$r_rttucb.ucb$w_rtt_link0#define ucb$b_rtt_obj ucb$r_rttucb.ucb$b_rtt_obj8#define ucb$w_rtt_systype ucb$r_rttucb.ucb$w_rtt_systype:#define ucb$b_rtt_fillbyte ucb$r_rttucb.ucb$b_rtt_fillbyteI#define ucb$l_ct_flags ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$l_ct_flagsW#define flg$v_ctrlo ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_ctrlo]#define flg$v_canctrlo ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_canctrlo]#define flg$v_vaxtovax ucb$rV_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_vaxtovaxW#define flg$v_ctrlc ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_ctrlcU#define flg$v_init ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_initc#define flg$v_reset_timer ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_reset_timerc#define flg$v_decnet_busy ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_decnet_busyc#define flg$v_output_busy ucb$r_rttucb.ucb$r_ct_flags_ovVerlay.ucb$r_ct_flags_bits.flg$v_output_busy_#define flg$v_read_busy ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_read_busya#define flg$v_sense_busy ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_sense_busy]#define flg$v_oob_char ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_oob_chare#define flg$v_flush_output ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_flush_outpute#define flg$v_clr_nobrdcst ucb$r_rttucb.ucb$r_ct_flags_overlayV.ucb$r_ct_flags_bits.flg$v_clr_nobrdcsta#define flg$v_read_abort ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_read_aborte#define flg$v_read_aborted ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_read_aborted]#define flg$v_isupport ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_isupporte#define flg$v_partial_read ucb$r_rttucb.ucb$r_ct_flags_overlay.ucb$r_ct_flags_bits.flg$v_partial_read2#define ucb$l_ct_wiirp ucb$r_rttucb.ucb$l_ct_wiirp.#define Vucb$l_ct_tqe ucb$r_rttucb.ucb$l_ct_tqe4#define ucb$l_ct_netqfl ucb$r_rttucb.ucb$l_ct_netqfl4#define ucb$l_ct_netqbl ucb$r_rttucb.ucb$l_ct_netqbl8#define ucb$l_ct_senseqfl ucb$r_rttucb.ucb$l_ct_senseqfl8#define ucb$l_ct_senseqbl ucb$r_rttucb.ucb$l_ct_senseqbl6#define ucb$l_ct_readqfl ucb$r_rttucb.ucb$l_ct_readqfl6#define ucb$l_ct_readqbl ucb$r_rttucb.ucb$l_ct_readqbl4#define ucb$l_ct_wrtdcb ucb$r_rttucb.ucb$l_ct_wrtdcb4#define ucb$l_ct_curdcb ucb$r_rttucb.ucb$l_ct_curdcb4#define ucb$w_ct_remsi Vz ucb$r_rttucb.ucb$w_ct_remsiz6#define ucb$w_ct_qdcbcnt ucb$r_rttucb.ucb$w_ct_qdcbcnt4#define ucb$w_ct_maxmsg ucb$r_rttucb.ucb$w_ct_maxmsg6#define ucb$w_ct_maxread ucb$r_rttucb.ucb$w_ct_maxread8#define ucb$l_ct_legalmsg ucb$r_rttucb.ucb$l_ct_legalmsg6#define ucb$b_ct_version ucb$r_rttucb.ucb$b_ct_version.#define ucb$b_ct_eco ucb$r_rttucb.ucb$b_ct_eco2#define ucb$w_ct_speed ucb$r_rttucb.ucb$w_ct_speed4#define ucb$b_ct_crfill ucb$r_rttucb.ucb$b_ct_crfill4#define ucb$b_ct_lffill ucb$r_rttucb.ucb V$b_ct_lffill4#define ucb$w_ct_parity ucb$r_rttucb.ucb$w_ct_parity6#define ucb$l_ct_include ucb$r_rttucb.ucb$l_ct_include6#define ucb$l_ct_exclude ucb$r_rttucb.ucb$l_ct_exclude2#define ucb$l_ct_abort ucb$r_rttucb.ucb$l_ct_abort8#define ucb$b_ct_oob_char ucb$r_rttucb.ucb$b_ct_oob_char:#define ucb$b_ct_fill_byte ucb$r_rttucb.ucb$b_ct_fill_byte4#define ucb$w_ct_prtctl ucb$r_rttucb.ucb$w_ct_prtctl8#define ucb$q_ct_isupport ucb$r_rttucb.ucb$q_ct_isupportB#define ucb$l_ct_fill_longword ucb$r_rttucb. Vucb$l_ct_fill_longword"#endif /* #if !defined(__VAXC) */ T#define UCB$C_RTT_LENGTH 728 /* Length must be same for both RTTDRIVER */N#define UCB$K_RTT_LENGTH 728 /* and CTDRIVER. */ .#define ucb$r_rtt_ucb ucb$r_ltrmucb.ucb$r_ucb$#define ucb$r_rtt_ltrm ucb$r_ltrmucb  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore tVhe previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TTYUCBDEF_LOADED */ ww`l[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorizVed to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated Vor disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: V 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */I/* Source: 29-JUL-2002 11:28:09 $1$DGA8345:[LIB_H.SRC]TTYVECDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $TTYVECDEF ***/#ifndef __TTYVECDEF_LOADED#define __TTYVECDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIVAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct sVtruct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* */N/* */N/* V */ N#define CLASS_LENGTH 40 /* must be at end. */X#define CLASSS_CLASS_DEF 40 /* Old size name, synonym for CLASSS_TT_CLASS */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ddt; #endif /* #ifdef __cplusplus */ typedef struct _tt_class {N unsigned char (*class_getnxt)(); /* */N unsigned char (*class_putnxt)(); /* */N void (*classV_setup_ucb)(); /* */N void (*class_ds_tran)(); /* */N struct _ddt *class_ddt; /* */N unsigned char (*class_readerror)(); /* */N void (*class_disconnect)(); /* */N void (*class_fork)(); /* */N void (*class_powerfail)(); /* V */N void *class_tables; /* */ } TT_CLASS;N#define TABLES_LENGTH 100 /* must be at end. */Z#define TABLESS_TABLES_DEF 100 /* Old size name, synonym for TABLESS_TT_TABLES */ typedef struct _tt_tables {N unsigned int tables_fill1; /* */N unsigned int tables_fill2; /* */N Vunsigned int tables_fill3; /* */N unsigned int tables_fill4; /* */N unsigned int tables_fill5; /* */N unsigned int tables_fill6; /* */N unsigned int tables_fill7; /* */N unsigned int tables_fill8; /* */N unsigned int tables_fill9;V /* */N unsigned int tables_fill10; /* */N unsigned int tables_fill11; /* */N unsigned int tables_fill12; /* */N unsigned int tables_fill13; /* */N unsigned int tables_fill14; /* */N unsigned int tables_fill15; /* V */N unsigned int tables_fill16; /* */N unsigned int tables_fill17; /* */N unsigned int tables_init_mid; /* */N unsigned int tables_fill19; /* */N unsigned int tables_posix; /* */N unsigned int tables_asian; /* */N V unsigned int tables_fill22; /* */N unsigned int tables_fill23; /* */N unsigned int tables_fill24; /* */N unsigned int tables_fidriver; /* */ } TT_TABLES;N#define PORT_LENGTH 76 /* must be at end. */V#define PORTS_PORT_DEF 76 /* Old size name, synonym for PORTS_TT_PORT */ Vtypedef struct _tt_port {N void (*port_startio)(); /* */N void (*port_disconnect)(); /* */N void (*port_set_line)(); /* */N void (*port_ds_set)(); /* */N void (*port_xon)(); /* */N void (*port_xoff)(); /* V*/N void (*port_stop)(); /* */N void (*port_stop2)(); /* */N void (*port_abort)(); /* */N void (*port_resume)(); /* */N void (*port_set_modem)(); /* */N void (*port_glyphload)(); /* Glyph loading (was _DMA) */N int (*port_maint)(V); /* */N void (*port_forkret)(); /* */N int (*port_fdt)(); /* */N void (*port_start_read)(); /* Start of PSI specific extensions */N void (*port_middle_read)(); /* */N void (*port_end_read)(); /* End of PSI specific extensions */b void (*port_cancel)(); /* Port Vdriver cancel I/O routine for PORT FDT requests */ } TT_PORT;N/* */N/* Asian terminal driver vectors */N/* */N#define ASIAN_LENGTH 96 /* must be at end. */X#define ASIANS_ASIAN_DEF 96 /* Old size name, synonym for ASIANS_TT_ASIAN */ typedef struct _tt_asianV {N int (*asian_fdtsensem)(); /* FDT SENSEMODE */N int (*asian_fdtsensec)(); /* FDT SENSECHAR */N int (*asian_fdt_setm)(); /* FDT SETMODE */N int (*asian_fdt_setc)(); /* FDT SETCHAR */N int (*asian_upper)(); /* FDT upcasing */N int (*asian_jiscon)(); /* JIS conversion */N int (*asian_start_Vread)(); /* Read QIO init */N int (*asian_do_setm)(); /* Start I/O SETMODE */N int (*asian_do_setc)(); /* Start I/O SETCHAR */N int (*asian_begin_echo)(); /* Start echo if needed */N int (*asian_cursoroverf)(); /* Cursor overflow */N int (*asian_setup_ucb)(); /* Set/reset UCB */N int (*asian_fontfork)(); /* Fork VODL startup */N int (*asian_cre_control)(); /* */N int (*asian_fhpointer)(); /* Pointer to FHDRIVER */N int (*asian_delete_asc)(); /* Delete ASC */N int (*asian_abort)(); /* AS$ABORT */N int (*asian_find_bol)(); /* Find begin of line */N int (*asian_preload)(); /* Preload handling V */N int (*asian_preload_fork)(); /* Deliver preload req. */N int (*asian_del_cache_fork)(); /* Deliver del cache req. */N int (*asian_preload_cleanup)(); /* Deliver preload req. */N int (*asian_adjust_cursor)(); /* update cursor position */N int (*asian_clone_ucb)(); /* Clone UCB fixup */ } TT_ASIAN;N/* */N/*V FI driver vectors */N/* */N#define FIDRIVER_LENGTH 12 /* must be at end. */X#define FIDRIVERS_FIDRIVER_DEF 12 /* Old size name, synonym for ASIANS_TT_ASIAN */ typedef struct _tt_fidriver {N int (*fidriver_ttread)(); /* FDT READ */N int (*fidriver_ttcancelio)(); /* CANCEL IO V */N int (*fidriver_ttdisconnect)(); /* DISCONNECT */ } TT_FIDRIVER;N/* */N/* Tables pointed to by TTY$A_POSIX */N/* */N#define POSIX_TABLES_LENGTH 16 /* must be at end. */h#define POSIX_TABLESS_POSIX_TABLES_DEF 16 /* Old size name, synonym Vfor POSIX_TABLESS_TT_POSIX_TABLES */ !typedef struct _tt_posix_tables {N unsigned int posix_tables_pt_pointer; /* */N unsigned int posix_tables_pt_putnxt; /* */N unsigned int posix_tables_pt_getnxt; /* */N unsigned int posix_tables_pt_writing; /* */ } TT_POSIX_TABLES; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* DefineVd whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __TTYVECDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software V**/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary softVware licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************* V***********************************************************************************/=/* Created: 7-Oct-2024 15:22:31 by OpenVMS SDL V3.7 */F/* Source: 31-OCT-2018 15:40:26 $1$DGA8345:[LIB_H.SRC]UAFDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $UAFDEF ***/#ifndef __UAFDEF_LOADED#define __UAFDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard featuresV */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optionVal_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* User authorization file format */N/* Note: With the exception of the username and account name, V */N/* all strings are blank padded counted strings. Username and */N/* account name are uncounted, blank padded. */N/*-- */N#define UAF$C_USER_ID 1 /* main user ID record */N#define UAF$C_VERSION1 1 /* this version */N#define UAF$C_KEYED_PART 52 /* ISAM keys come this far */O#define UAF$VC_MAX_PWD_LENGTH 64 /* maximum plaintext password length */O#define UAF$K_MAX_PWD_LENGTH 64 /* maximum plaintext password length */N#define UAF$C_AD_II 0 /* AUTODIN-II 32 bit crc code */P#define UAF$C_PURDY 1 /* Purdy polynomial over salted input */Y#define UAF$C_PURDY_V 2 /* Purdy polynomial + variable length username */Q#define UAF$C_PURDY_S 3 /* PURDY_V folded into password length */N#define UAF$K_CUVRRENT_ALGORITHM 3 /* current DEC algorithm number */N#define UAF$C_CURRENT_ALGORITHM 3 /* current DEC algorithm number */$#define UAF$C_PREFERED_ALGORITHM 127$#define UAF$K_PREFERED_ALGORITHM 127T#define UAF$C_PREFERRED_ALGORITHM 127 /* preferred hash algorithm - use current */T#define UAF$K_PREFERRED_ALGORITHM 127 /* preferred hash algorithm - use current */N#define UAF$C_CUST_ALGORITHM 128 /* customer algorithm division */N#define UAF$K_CUST_ALGORITHM 128 V /* customer algorithm division */#define UAF$M_DISCTLY 0x1#define UAF$M_DEFCLI 0x2#define UAF$M_LOCKPWD 0x4#define UAF$M_RESTRICTED 0x8#define UAF$M_DISACNT 0x10#define UAF$M_DISWELCOM 0x20#define UAF$M_DISMAIL 0x40#define UAF$M_NOMAIL 0x80#define UAF$M_GENPWD 0x100#define UAF$M_PWD_EXPIRED 0x200 #define UAF$M_PWD2_EXPIRED 0x400#define UAF$M_AUDIT 0x800#define UAF$M_DISREPORT 0x1000!#define UAF$M_DISRECONNECT 0x2000#define UAF$M_AUTOLOGIN 0x4000(#define UAVF$M_DISFORCE_PWD_CHANGE 0x8000#define UAF$M_CAPTIVE 0x10000#define UAF$M_DISIMAGE 0x20000#define UAF$M_DISPWDDIC 0x40000#define UAF$M_DISPWDHIS 0x80000 #define UAF$M_DEFCLSVAL 0x100000#define UAF$M_EXTAUTH 0x200000!#define UAF$M_MIGRATEPWD 0x400000#define UAF$M_VMSAUTH 0x800000##define UAF$M_DISPWDSYNCH 0x1000000#define UAF$M_PWDMIX 0x2000000#define UAF$M_MONDAY 0x1#define UAF$M_TUESDAY 0x2#define UAF$M_WEDNESDAY 0x4#define UAF$M_THURSDAY 0x8#define UAF$M_FRIDAY 0x10 V#define UAF$M_SATURDAY 0x20#define UAF$M_SUNDAY 0x40N#define UAF$K_FIXED 644 /* length of fixed portion */N#define UAF$C_FIXED 644 /* length of fixed portion */#define UAF$K_LENGTH 1412#define UAF$C_LENGTH 1412S#define UAF$S_UAFDEF 1412 /* Old size name, synonym for UAF$S_UAF */ typedef struct _uaf {N unsigned char uaf$b_rtype; /* UAF record type */N unsigned char uaf$b_version; V /* UAF format version */S unsigned short int uaf$w_usrdatoff; /* offset of counted string of user data */ __union {N char uaf$t_username [32]; /* username */ __struct {# char uaf$t_fill_0 [31];N char uaf$t_username_tag; /* tag to differentiate records */ } uaf$r_fill_1_; } uaf$r_fill_0_; __union {N unsigned int uaf$l_uic; /* user ID code V */ __struct {N unsigned short int uaf$w_mem; /* member subfield */N unsigned short int uaf$w_grp; /* group subfield */ } uaf$r_fill_3_; } uaf$r_fill_2_;N unsigned int uaf$l_sub_id; /* user sub-identifier */Q unsigned __int64 uaf$q_parent_id; /* identifier of owner of this account */N char uaf$t_account [32]; /* account name */N char uafV$t_owner [32]; /* owner's name */N char uaf$t_defdev [32]; /* default device */N char uaf$t_defdir [64]; /* default directory */N char uaf$t_lgicmd [64]; /* login command file */N char uaf$t_defcli [32]; /* default command interpreter */N char uaf$t_clitables [32]; /* user CLI tables */ __union {N unsigned __int V64 uaf$q_pwd; /* hashed password */ __struct {N unsigned int uaf$l_pwd; /* 32 bit subfield */ } uaf$r_fill_5_; } uaf$r_fill_4_;N unsigned __int64 uaf$q_pwd2; /* second password */N unsigned short int uaf$w_logfails; /* count of login failures */N unsigned short int uaf$w_salt; /* random password salt */N unsigned char uaf$b_encrypt; /* primaryV password hash algorithm */N/* known hash algorithm indices */O unsigned char uaf$b_encrypt2; /* secondary password hash algorithm */N unsigned char uaf$b_pwd_length; /* minimum password length */ char uaf$$$_fill_1 [1];N unsigned __int64 uaf$q_expiration; /* expiration date for account */N unsigned __int64 uaf$q_pwd_lifetime; /* password lifetime */N unsigned __int64 uaf$q_pwd_date; /* dVate of password change */N unsigned __int64 uaf$q_pwd2_date; /* date of 2nd password change */N unsigned __int64 uaf$q_lastlogin_i; /* date of last interactive login */P unsigned __int64 uaf$q_lastlogin_n; /* date of last non-interactive login */N unsigned __int64 uaf$q_priv; /* process privilege vector */N unsigned __int64 uaf$q_def_priv; /* default process privileges */N __struct { /* minimum security class V */ char uaf$b_fill_2 [20]; } uaf$r_min_class;N __struct { /* maximum security class */ char uaf$b_fill_3 [20]; } uaf$r_max_class; __union {N unsigned int uaf$l_flags; /* user flags longword */ __struct {N unsigned uaf$v_disctly : 1; /* no user control-y */N unsigned uaf$v_defcli : 1; /* only allow user default CLI */N Vunsigned uaf$v_lockpwd : 1; /* disable SET PASSWORD command */V unsigned uaf$v_restricted : 1; /* restricted account (pre-V5.2 CAPTIVE) */N unsigned uaf$v_disacnt : 1; /* no interactive login */N unsigned uaf$v_diswelcom : 1; /* skip welcome message */N unsigned uaf$v_dismail : 1; /* skip new mail message */N unsigned uaf$v_nomail : 1; /* disable mail delivery */N unsigned uaf$v_genVpwd : 1; /* passwords must be generated */N unsigned uaf$v_pwd_expired : 1; /* password has expired */N unsigned uaf$v_pwd2_expired : 1; /* 2nd password has expired */N unsigned uaf$v_audit : 1; /* audit all actions */N unsigned uaf$v_disreport : 1; /* skip last login messages */N unsigned uaf$v_disreconnect : 1; /* inhibit reconnections */N unsigned uaf$v_autologin : 1; /* auto-login Vonly */X unsigned uaf$v_disforce_pwd_change : 1; /* disable forced password change */N unsigned uaf$v_captive : 1; /* captive account (no overrides) */Q unsigned uaf$v_disimage : 1; /* disable arbitrary image activation */R unsigned uaf$v_dispwddic : 1; /* disable password dictionary search */O unsigned uaf$v_dispwdhis : 1; /* disable password history search */O unsigned uaf$v_defclsval : 1; /* default classific Vation is valid */N unsigned uaf$v_extauth : 1; /* external authentication enabled */Q unsigned uaf$v_migratepwd : 1; /* migrate UAF pwd to external auth */N unsigned uaf$v_vmsauth : 1; /* VMS alternative is allowed */N unsigned uaf$v_dispwdsynch : 1; /* no ACME password sharing */N unsigned uaf$v_pwdmix : 1; /* enable mixed-case passwords */( unsigned uaf$v_fill_10_ : 6; } uaf$r_fill_7_; } Vuaf$r_fill_6_;R unsigned char uaf$b_network_access_p [3]; /* hourly network access, primary */T unsigned char uaf$b_network_access_s [3]; /* hourly network access, secondary */N unsigned char uaf$b_batch_access_p [3]; /* hourly batch access, primary */P unsigned char uaf$b_batch_access_s [3]; /* hourly batch access, secondary */N unsigned char uaf$b_local_access_p [3]; /* hourly local access, primary */P unsigned char uaf$b_local_access_s [3]; /* hourly local access, secondary V*/P unsigned char uaf$b_dialup_access_p [3]; /* hourly dialup access, primary */R unsigned char uaf$b_dialup_access_s [3]; /* hourly dialup access, secondary */P unsigned char uaf$b_remote_access_p [3]; /* hourly remote access, primary */R unsigned char uaf$b_remote_access_s [3]; /* hourly remote access, secondary */N char uaf$$$_fill_4 [12]; /* space for 2 more access types */ __union {N unsigned char uaf$b_primedays; /* bits representing primary days V */ __struct {S unsigned uaf$v_monday : 1; /* bit clear means this is a primary day */N unsigned uaf$v_tuesday : 1; /* bit set means this is an off day */) unsigned uaf$v_wednesday : 1;( unsigned uaf$v_thursday : 1;& unsigned uaf$v_friday : 1;( unsigned uaf$v_saturday : 1;& unsigned uaf$v_sunday : 1;( unsigned uaf$v_fill_11_ : 1; } uaf$r_fill_9_; } uaf$r_fill_8_; chVar uaf$$$_fill_5 [1];N unsigned char uaf$b_pri; /* base process priority */N unsigned char uaf$b_quepri; /* maximum job queuing priority */N unsigned short int uaf$w_maxjobs; /* maximum jobs for UIC allowed */N/* 0 means no limit */P unsigned short int uaf$w_maxacctjobs; /* maximum jobs for account allowed */N/* 0 means no limit */PV unsigned short int uaf$w_maxdetach; /* maximum detached processes for UIC */N/* 0 means no limit */N unsigned short int uaf$w_prccnt; /* subprocess creation limit */N unsigned short int uaf$w_biolm; /* buffered I/O limit */N unsigned short int uaf$w_diolm; /* direct I/O limit */N unsigned short int uaf$w_tqcnt; /* timer queue entry limit */N unsigned short int uVaf$w_astlm; /* AST queue limit */N unsigned short int uaf$w_enqlm; /* enqueue limit */N unsigned short int uaf$w_fillm; /* open file limit */N unsigned short int uaf$w_shrfillm; /* shared file limit */N unsigned int uaf$l_wsquota; /* working set size quota */N unsigned int uaf$l_dfwscnt; /* default working set size */N unsigned int uaf$l_wsextent; /* workingV set size limit */N unsigned int uaf$l_pgflquota; /* page file quota */N unsigned int uaf$l_cputim; /* CPU time quota */N unsigned int uaf$l_bytlm; /* buffered I/O byte count limit */O unsigned int uaf$l_pbytlm; /* paged buffer I/O byte count limit */X unsigned int uaf$l_jtquota; /* job-wide logical name table creation quota */N unsigned short int uaf$w_proxy_lim; /* number of proxies use Vr can grant */N unsigned short int uaf$w_proxies; /* number of proxies granted */N unsigned short int uaf$w_account_lim; /* number of sub-accounts allowed */N unsigned short int uaf$w_accounts; /* number of sub-accounts in use */N __struct { /* default security class */ char uaf$b_fill_6 [20]; } uaf$r_def_class;N char uaf$$$_fill_99 [44]; /* spare space */N char uaf$$$_fill_100 [76 V8]; /* user-extensible area */ } UAF; #if !defined(__VAXC)3#define uaf$t_username uaf$r_fill_0_.uaf$t_usernameI#define uaf$t_username_tag uaf$r_fill_0_.uaf$r_fill_1_.uaf$t_username_tag)#define uaf$l_uic uaf$r_fill_2_.uaf$l_uic7#define uaf$w_mem uaf$r_fill_2_.uaf$r_fill_3_.uaf$w_mem7#define uaf$w_grp uaf$r_fill_2_.uaf$r_fill_3_.uaf$w_grp)#define uaf$q_pwd uaf$r_fill_4_.uaf$q_pwd7#define uaf$l_pwd uaf$r_fill_4_.uaf$r_fill_5_.uaf$l_pwd-#define uaf$l_flags uaf$ Vr_fill_6_.uaf$l_flags?#define uaf$v_disctly uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_disctly=#define uaf$v_defcli uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_defcli?#define uaf$v_lockpwd uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_lockpwdE#define uaf$v_restricted uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_restricted?#define uaf$v_disacnt uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_disacntC#define uaf$v_diswelcom uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_diswelcom?#define uaf$v_dismail uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_dismail=#define uaf$Vv_nomail uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_nomail=#define uaf$v_genpwd uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_genpwdG#define uaf$v_pwd_expired uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_pwd_expiredI#define uaf$v_pwd2_expired uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_pwd2_expired;#define uaf$v_audit uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_auditC#define uaf$v_disreport uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_disreportI#define uaf$v_disreconnect uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_disreconnectC#define uaf$v_autologin uaf$r_fiVll_6_.uaf$r_fill_7_.uaf$v_autologinW#define uaf$v_disforce_pwd_change uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_disforce_pwd_change?#define uaf$v_captive uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_captiveA#define uaf$v_disimage uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_disimageC#define uaf$v_dispwddic uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_dispwddicC#define uaf$v_dispwdhis uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_dispwdhisC#define uaf$v_defclsval uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_defclsval?#define uaf$v_extauth uaf$r_fill_6 V_.uaf$r_fill_7_.uaf$v_extauthE#define uaf$v_migratepwd uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_migratepwd?#define uaf$v_vmsauth uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_vmsauthG#define uaf$v_dispwdsynch uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_dispwdsynch=#define uaf$v_pwdmix uaf$r_fill_6_.uaf$r_fill_7_.uaf$v_pwdmix5#define uaf$b_primedays uaf$r_fill_8_.uaf$b_primedays=#define uaf$v_monday uaf$r_fill_8_.uaf$r_fill_9_.uaf$v_monday?#define uaf$v_tuesday uaf$r_fill_8_.uaf$r_fill_9_.uaf$v_tuesdayC#define uaf$ Vv_wednesday uaf$r_fill_8_.uaf$r_fill_9_.uaf$v_wednesdayA#define uaf$v_thursday uaf$r_fill_8_.uaf$r_fill_9_.uaf$v_thursday=#define uaf$v_friday uaf$r_fill_8_.uaf$r_fill_9_.uaf$v_fridayA#define uaf$v_saturday uaf$r_fill_8_.uaf$r_fill_9_.uaf$v_saturday=#define uaf$v_sunday uaf$r_fill_8_.uaf$r_fill_9_.uaf$v_sunday"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __requiredV_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __UAFDEF_LOADED */ ww/[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LPV, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** Vauthorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//************************************************************************************************************* V*******************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Source: 19-APR-1993 14:56:58 $1$DGA8345:[LIB_H.SRC]UASDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $UASDEF ***/#ifndef __UASDEF_LOADED#define __UASDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_aliVgnmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXVC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* UNIBUS ADDRESS SPACE REGISTER DEFINITIONS FOR DW750 */J/* (SECOND UNIBUS ADAPTER ON 11/750) */N/*- V */#define UAS$M_IP_CR1_PIE 0x1000#define UAS$M_IP_CR1_PDN 0x2000#define UAS$S_UASDEF 5222 typedef struct _uas { char uasdef$$_fill_1 [5216];T __struct { /* INTER-PROCESSOR EXERCISER COMMUNICATOR */[ short int uasdef$$_fill_2 [2]; /* ADDRESS AND DATA REGISTERS NOT CURRENTLY USED */ __union {O unsigned short int uas$w_ip_cr1; /* THE THIRD IPEC REGISTER, CR1 */ __struct {N W unsigned uasdef$$_fill_3 : 12; /* SKIP BITS OF NO INTEREST */O unsigned uas$v_ip_cr1_pie : 1; /* POWERFAIL INTERRUPT ENABLE */N unsigned uas$v_ip_cr1_pdn : 1; /* POWER DOWN STATUS BIT */+ unsigned uas$v_fill_0_ : 2;! } uas$r_cr1_bits; } uas$r_cr1_overlay; } uas$r_ip; } UAS; #if !defined(__VAXC)<#define uas$w_ip_cr1 uas$r_ip.uas$r_cr1_overlay.uas$w_ip_cr1S#define uas$v_ip_cr1_pie uas$r_ip.uas$r_Wcr1_overlay.uas$r_cr1_bits.uas$v_ip_cr1_pieS#define uas$v_ip_cr1_pdn uas$r_ip.uas$r_cr1_overlay.uas$r_cr1_bits.uas$v_ip_cr1_pdn"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __UASDEF_LOADED */ wwWV[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 20W24 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software,W Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */G/* Source: 19-APR-1993 14:58:35 $1$DGA8345:[LIB_H.SRC]UBMDDEF.SDL;1 *//***************************** W***************************************************************************************************//*** MODULE $UBMDDEF ***/#ifndef __UBMDDEF_LOADED#define __UBMDDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[W#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union varian Wt_union#endif#endif N/*+ */N/* UBMD - UNIBUS Map Descriptor used to record UNIBUS map registers */N/* and datapaths allocated. */N/*- */#define UBMD$S_UBMDDEF 4 typedef struct _ubmd {N unsigned short int ubmd$w_mapreg; /* Starting map register */N unsigned char ubmdW$b_numreg; /* Number of registers in extent */N unsigned char ubmd$b_datapath; /* Associated Buffered datapath */ } UBMD; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __UBMDDEF_LOADED */ ww}[UM W/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewle Wtt-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc.  W **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:35 by OpenVMS SDL V3.7 */F/* Source: 09-JUL-2022 00:13:57 $1$DGA8345:[LIB_H.SRC]UCBDEF.SDL;1 *//************************************************* W*******************************************************************************//*** MODULE $UCBDEF ***/#ifndef __UCBDEF_LOADED#define __UCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_poi Wnter_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endWif  #include F#include /* Define the TQE type; UCB contains a pointer */#include N#define UCB$K_V8_POWERED 1 /* Build for V8 feature set. */Q#define UCB$K_50BIT_PA 1 /* 50BIT Physical addressing with V8.2 */#define UCB$M_TIM 0x1#define UCB$M_INT 0x2#define UCB$M_ERLOGIP 0x4#define UCB$M_CANCEL 0x8#define UCB$M_ONLINE 0x10#define UCB$M_POWER 0x20#define UCB$M_TIMOUT 0x40#define UCB$M_INTTYPE 0x80#dWefine UCB$M_BSY 0x100#define UCB$M_MOUNTING 0x200#define UCB$M_DEADMO 0x400#define UCB$M_VALID 0x800#define UCB$M_UNLOAD 0x1000#define UCB$M_TEMPLATE 0x2000#define UCB$M_MNTVERIP 0x4000#define UCB$M_WRONGVOL 0x8000#define UCB$M_DELETEUCB 0x10000#define UCB$M_LCL_VALID 0x20000#define UCB$M_SUPMVMSG 0x40000#define UCB$M_MNTVERPND 0x80000#define UCB$M_DISMOUNT 0x100000#define UCB$M_CLUTRAN 0x200000 #define UCB$M_WRTLOCKMV 0x400000#define UCB$M_SVPN_END 0x800000#dWefine UCB$M_ALTBSY 0x1000000 #define UCB$M_SNAPSHOT 0x2000000!#define UCB$M_NO_ASSIGN 0x4000000##define UCB$M_EXFUNC_SUPP 0x8000000"#define UCB$M_FAST_PATH 0x10000000"#define UCB$M_PATHVERIP 0x20000000!#define UCB$M_FP_HWINT 0x40000000%#define UCB$M_IOPOST_LOCAL 0x80000000#define UCB$M_JOB 0x1#define UCB$M_TEMPL_BSY 0x40#define UCB$M_PRMMBX 0x1#define UCB$M_DELMBX 0x2#define UCB$M_TT_TIMO 0x2#define UCB$M_TT_NOTIF 0x4#define UCB$M_TT_HANGUP 0x8 #define UCB$M_TT_NOLOGINS 0xW8000#define UCB$M_NT_BFROVF 0x4#define UCB$M_NT_NAME 0x10#define UCB$M_NT_BREAK 0x20#define UCB$M_ECC 0x1#define UCB$M_DIAGBUF 0x2#define UCB$M_NOCNVRT 0x4#define UCB$M_DX_WRITE 0x8#define UCB$M_DATACACHE 0x10!#define UCB$M_MSCP_MNTVERIP 0x100 #define UCB$M_MSCP_INITING 0x200 #define UCB$M_MSCP_WAITBMP 0x400#define UCB$M_MSCP_FLOVR 0x800#define UCB$M_MSCP_PKACK 0x1000#define UCB$M_MSCP_WRTP 0x2000 #define UCB$M_MSCP_IGNSRV 0x4000##define UCB$M_MSCP_MVRESTART 0x8000.W#define UCB$M_MSCP_LOCAL_DRAIN_WAITBMP 0x10000#define UCB$M_DU_SHMV_STRTD 0x8#define UCB$M_DU_0MNOTE 0x20#define UCB$M_MVFKBBSY 0x40#define UCB$M_GTUNMBSY 0x80#define UCB$M_TU_OVRSQCHK 0x1#define UCB$M_TU_TRACEACT 0x2#define UCB$M_TU_SEQNOP 0x4#define UCB$M_TU_1DENS 0x8%#define UCB$M_TU_DENS_DETERMINED 0x10"#define UCB$M_TU_MEDIA_LOADED 0x20#define UCB$M_SHD_WLG_INV 0x80##define UCB$M_SHD_SEQCMD_HERE 0x400$#define UCB$M_SHD_SEQCMD_THERE 0x800##define UCB$M_SHD_PASSIVE_MVW 0x1000%#define UCB$M_SHD_NODE_FAILURE 0x2000##define UCB$M_SHD_WLGSTA_CHA 0x4000$#define UCB$M_SHD_VCB_DEQUEUE 0x8000%#define UCB$M_SHD_SEQCMD_PEND 0x10000%#define UCB$M_SHD_ST_DRAIN_IO 0x20000&#define UCB$M_SHD_MBRSHP_EVENT 0x40000&#define UCB$M_SHD_TGR_VALIDATE 0x80000#define UCB$M_PORT_ONLINE 0x1#define UCB$M_FKLOCK 0x2#define UCB$M_MSGFKLOCK 0x4#define UCB$M_INIFKLOCK 0x8#define UCB$M_BAD_REV 0x10#define UCB$M_PA_ERLOGIP 0x20#define UCB$M_MFQEFKLOCK 0x40#define UCWB$M_MFQE_LOST 0x80 #define UCB$M_ADMIN_ONLINE 0x100#define UCB$M_ADMIN_INIT 0x200##define UCB$M_ADMIN_TEAR_DOWN 0x400!#define UCB$M_CHAN_ONLINE 0x10000#define UCB$M_CHAN_INIT 0x20000$#define UCB$M_CHAN_TEAR_DOWN 0x40000##define UCB$M_PB_TQE_BUSY 0x1000000$#define UCB$M_MBR_CALLBACK 0x2000000$#define UCB$M_SHUTDOWN_REQ 0x4000000##define UCB$M_SHUTDOWN_IP 0x8000000.#define UCB$M_PB_LAST_GASP_EMULATED 0x10000000  9#ifdef __cplusplus /* Define structure prototypes */ structW _acb; struct _spl; struct _orb; struct _cram; struct _crb; struct _ddb; struct _vcb; struct _irp; struct _cpu;struct _iocnt;struct _bufio; struct _pdt; struct _ddt; struct _adp;struct _crctx; struct _dtn; struct _sud; struct _ext; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ucb { W __union {#pragma __nomember_alignment FKB ucb$r_ucb_fkb; __struct { __union {N struct _fkb *ucb$l_fqfl; /*FORK QUEUE FORWARD LINK */ __union {N unsigned int ucb$l_unit_seed; /* Longword Unit Seed */O unsigned short int ucb$w_unit_seed; /* UNIT NUMBER SEED */c unsigned short int ucb$w_mb_seed; /* MB -- UNIT NUMBER SEED (no longer used) */) W } ucb$r_seed_overlay;N void *ucb$l_rqfl; /* NET -- RCV QUEUE FORWARD LINK */N void *ucb$l_mb_msgqfl; /* MAILBOX MESSAGE QUEUE LISTHEAD */% } ucb$r_fqfl_overlay; __union {N struct _fkb *ucb$l_fqbl; /*FORK QUEUE BACKWARD LINK */N void *ucb$l_rqbl; /* NET -- RCV QUEUE BACKWARD LINK */N void *ucb$l_mb_msgqbl; /* MAILBOX MESSAGE QUEUE LISTHEAD */% W } ucb$r_fqbl_overlay;N unsigned short int ucb$w_size; /*SIZE OF UCB IN BYTES */N unsigned char ucb$b_type; /*STRUCTURE TYPE FOR UCB */N unsigned char ucb$b_flck; /* Fork lock number index */ __union {N void (*ucb$l_fpc)(); /*FORK PC */T int ucb$l_astqfl; /* MB -- AST QUEUE LISTHEAD FORWARD LINK */N struct _acb *ucb$l_mb_w_ast; /* WMAILBOX WRITE ATTN AST LIST */N char ucb$t_partner; /* NET -- PARTNER'S NODENAME */$ } ucb$r_fpc_overlay; __union {N __int64 ucb$q_fr3; /*FORK R3 */ __struct {N int ucb$l_fr3; /*FORK R3 longword overlay */( } ucb$r_fr3_q_block;X struct _acb *ucb$l_astqbl; /* MB -- AST QUEUE LISTHEAD BACKWARD LINK */N W struct _acb *ucb$l_mb_r_ast; /* MAILBOX READ ATTN AST LIST */$ } ucb$r_fr3_overlay; __union {N __int64 ucb$q_fr4; /*FORK R4 */ __struct {Z unsigned short int ucb$w_msgmax; /* MB -- MAXIMUM MESSAGES ALLOWED */\ unsigned short int ucb$w_msgcnt; /* MB -- CURRENT NUMBER OF MESSAGES */* } ucb$r_mb_fr4_fields;T int ucb$l_first; W /* NET -- ADDR OF 1ST SEG OF CHAINED MSG */$ } ucb$r_fr4_overlay;N struct _spl *ucb$ps_spinlock; /* Pointer to a spinlock. */# } ucb$r_ucb_fkb_struct; } ucb$r_ucb_fkb_union; __union {V unsigned short int ucb$w_bufquo; /* BUFFERED I/O QUOTA CHARGED FOR THIS UCB */N unsigned short int ucb$w_dstaddr; /* NET -- REMOTE CONNECT NO. */ } ucb$r_bufquo_overlay; __union {V unsigned short int ucb$w W_iniquo; /* INITIAL BUFFERED I/O QUOTA FOR THIS UCB */N unsigned short int ucb$w_srcaddr; /* NET -- LOCAL CONNECT NO. */ } ucb$r_iniquo_overlay;N struct _orb *ucb$l_orb; /* OBJECT'S RIGHTS BLOCK ADDRESS */ __union {N unsigned int ucb$l_lockid; /*DEVICE LOCK ID */P unsigned int ucb$l_cpid; /*PID CHARGED FOR BUFQUO BY UCBCREDEL */ } ucb$r_lockid_overlay;N struct _cram *ucb$ps_cram; /*ADWDRESS OF FIRST UNIT CRAM */V struct _crb *ucb$l_crb; /*ADDRESS OF PRIMARY CHANNEL REQUEST BLOCK */N struct _spl *ucb$l_dlck; /*ADDRESS OF DEVICE IPL SPINLOCK */N struct _ddb *ucb$l_ddb; /*BACKPOINTER TO DEVICE DATA BLOCK */N unsigned int ucb$l_pid; /*PROCESS ID OF OWNER PROCESS */T struct _ucb *ucb$l_link; /*ADDRESS OF NEXT UCB FOR RESPECTIVE DDB */N struct _ucb *ucb$l_blink; /*Backwards Link W */N struct _vcb *ucb$l_vcb; /*ADDRESS OF VOLUME CONTROL BLOCK */ char ucb$b_fill_0_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __union { /*DEVICE CHARACTERISTIC BITS */#pragma __nomember_alignmentQ unsigned __int64 ucb$q_devchar; /* Device characteristic bits quWadword */ __struct {R unsigned int ucb$l_devchar; /* Original device characteristic bits */S unsigned int ucb$l_devchar2; /* Extended device characteristic bits */$ } ucb$r_devchar_q_block; } ucb$r_devchar;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN W CBB ucb$r_cbb_affinity; /* Embedded CBB block */N __struct { /* Compatability offset cells */% __int64 ucb$q_fill_1 [6]; __union {N unsigned int ucb$l_affinity; /* Device affinity */N unsigned __int64 ucb$q_affinity; /* Device affinity */2 } ucb$r_cbb_affinity_data_overlay;& __int64 ucb$q_fill_2 [15];0 } ucb$r_cbb_affinity !W_compat_overlay;% } ucb$r_cbb_affinity_overlay; __union {N unsigned int ucb$l_xtra; /*EXTRA LONGWORD (FOR SMP) */N int ucb$l_altiowq; /*ALTERNATE STARTIO WAIT */N/*QUEUE */ } ucb$r_xtra_overlay;N unsigned char ucb$b_devclass; /*DEVICE CLASS */N unsigned char ucb$b_devtype; /*DEVICE TYPE */N "W unsigned short int ucb$w_devbufsiz; /*DEVICE DEFAULT BUFFER SIZE */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN __union { /*DEVICE DEPENDENT DATA */#pragma __nomember_alignmentN unsigned __int64 ucb$q_devdepend; /*Device dependent quadword */ __struct { __union {T#W unsigned int ucb$l_devdepend; /* First device dependent longword */N __struct { /* Disk fields */J unsigned char ucb$b_sectors; /* Sectors per track */I unsigned char ucb$b_tracks; /* Track per cylinder */P unsigned short int ucb$w_cylinders; /* Cylinders per disk */+ } ucb$r_disk_devdepend;N __struct { /* Terminal field$Ws */: char ucbdef$$_term_devdepend_fill [3];Y unsigned char ucb$b_vertsz; /* Vertical page size (lines per page) */+ } ucb$r_term_devdepend;N __struct { /* Network fields */J unsigned char ucb$b_locsrv; /* Local link services */J unsigned char ucb$b_remsrv; /* Remote link services */Z unsigned short int ucb$w_bytestogo; %W/* No. of bytes left in rcv bfr */* } ucb$r_net_devdepend;* } ucb$r_devdepend_overlay; __union {W unsigned int ucb$l_devdepnd2; /* Second device dependent long word */^ unsigned int ucb$l_tt_devdp1; /* Terminal -- Device dependent long word */q unsigned short int ucb$w_tu_formenu; /* TU/TMSCP -- Supported formats (returned by GETDVI). */* } ucb$r_devdepnd2_overlay;& &W} ucb$r_devdepend_q_block;$ } ucb$r_devdepend_q_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifP __union { /*2nd QUADWORD DEVICE DEPENDENT DATA */#pragma __nomember_alignmentN unsigned __int64 ucb$q_devdepend2; /*Device dependent quadword */ __struct { __union {R 'W unsigned int ucb$l_devdepnd3; /* 3rd device dependent longword */* } ucb$r_devdepnd3_overlay; __union {T unsigned int ucb$l_devdepnd4; /* 4th device dependent long word */* } ucb$r_devdepnd4_overlay;' } ucb$r_devdepend2_q_block;Q __struct { /* Tape Mount verification byte counts */N unsigned short int ucb$w_tmv_bcnt1; /* Byte count for 1st CRC */N unsigned short int(W ucb$w_tmv_bcnt2; /* ...2nd CRC */N unsigned short int ucb$w_tmv_bcnt3; /* ...3rd CRC */N unsigned short int ucb$w_tmv_bcnt4; /* ...4th CRC */ } ucb$r_tmv_bcnt;% } ucb$r_devdepend2_q_overlay;N struct _irp *ucb$l_ioqfl; /*I/O QUEUE LISTHEAD FORWARD LINK */N struct _irp *ucb$l_ioqbl; /*I/O QUEUE LISTHEAD BACKWARD LINK */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) )W/* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN unsigned short int ucb$w_unit; /*PHYSICAL DEVICE UNIT NUMBER */ unsigned int ucb$l_unit; } ucb$r_unit_overlay; __union {N unsigned short int ucb$w_charge; /*MAILBOX BYTE COUNT QUOTA CHARGE */\ unsigned short int ucb$w_rwaitcnt; /* CLASS DRIVERS -- THREADS WAITING RESOURCES */ *W __struct {Q unsigned char ucb$b_cm1; /* LEVEL 1 CONTROLLER ALLOCATION MASK */Q unsigned char ucb$b_cm2; /* LEVEL 2 CONTROLLER ALLOCATION MASK */' } ucb$r_ctrlr_alloc_fields; } ucb$r_charge_overlay; char ucb$b_fill_1_ [2];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifP struct _irp *u +Wcb$l_irp; /*CURRENT I/O REQUEST PACKET ADDRESS */#pragma __nomember_alignmentN unsigned int ucb$l_refc; /*REFERENCE COUNT OF PROCESSES */ __union {N unsigned char ucb$b_dipl; /*DEVICE INTERRUPT PRIORITY LEVEL */X unsigned char ucb$b_state; /* NET -- LINK STATE FOR NETWORK TRANSITIONS */ } ucb$r_dipl_overlay;N unsigned char ucb$b_amod; /*ALLOCATION ACCESS MODE */ short int ucb$w_fill_0;S ,Wstruct _ucb *ucb$l_amb; /*ASSOCIATED UNIT CONTROL BLOCK POINTER */ __union {N unsigned int ucb$l_sts; /*DEVICE UNIT STATUS */ __struct {N unsigned ucb$v_tim : 1; /* TIME OUT ENABLED (1=YES) */N unsigned ucb$v_int : 1; /* INTERRUPT EXPECTED (1=YES) */T unsigned ucb$v_erlogip : 1; /* ERROR LOG IN PROGRESS ON UNIT (1=YES) */N unsigned ucb$v_cancel : 1; /* CANCEL I/O ON UNI-WT (1=YES) */N unsigned ucb$v_online : 1; /* UNIT ONLINE (1=YES) */S unsigned ucb$v_power : 1; /* POWER FAILED WHILE UNIT BUSY (1=YES) */N unsigned ucb$v_timout : 1; /* UNIT TIMED OUT (1=YES) */N unsigned ucb$v_inttype : 1; /* RECEIVER INTERRUPT IF SET */N unsigned ucb$v_bsy : 1; /* UNIT IS BUSY (1=YES) */N unsigned ucb$v_mounting : 1; /* DEVICE IS BEING MOUNTED */N.W unsigned ucb$v_deadmo : 1; /* DEALLOCATE AT DISMOUNT */N unsigned ucb$v_valid : 1; /* VOLUME IS SOFTWARE VALID */N unsigned ucb$v_unload : 1; /* UNLOAD VOLUME AT DISMOUNT */N unsigned ucb$v_template : 1; /* SET IF THIS IS TEMPLATE UCB */N unsigned ucb$v_mntverip : 1; /* MOUNT VERIFICATION IN PROGRESS */_ unsigned ucb$v_wrongvol : 1; /* WRONG VOLUME DETECTED DURING MOUNT VERIFICATION */V /W unsigned ucb$v_deleteucb : 1; /* DELETE THIS UCB WHEN REFC REACHES ZERO */Q unsigned ucb$v_lcl_valid : 1; /* VOLUME IS VALID ON THE LOCAL NODE */] unsigned ucb$v_supmvmsg : 1; /* IF SET, SUPPRESS SUCCESS TYPE MOUNT VER. MSGS. */] unsigned ucb$v_mntverpnd : 1; /* MOUNT VERIFICATION IS PENDING ON BUSY DEVICE. */N unsigned ucb$v_dismount : 1; /* DISMOUNT IN PROGRESS */U unsigned ucb$v_clutran : 1; /* VAXcluster STATE TRANSITION0W IN PROGRESS */[ unsigned ucb$v_wrtlockmv : 1; /* Write-locked mount verification in progress */V unsigned ucb$v_svpn_end : 1; /* Last byte used from page mapped by SVPN */U unsigned ucb$v_altbsy : 1; /* Unit is busy via alternate startio path */R unsigned ucb$v_snapshot : 1; /* Restart validation is in progress */Y unsigned ucb$v_no_assign : 1; /* Unit cannot have channels assigned to it. */N unsigned ucb$v_exfunc_supp : 1 1W; /* Unit supports the EXFUNC bit */O unsigned ucb$v_fast_path : 1; /* Unit supports FASTPATH affinity */] unsigned ucb$v_pathverip : 1; /* Path verification in progress for this device */_ unsigned ucb$v_fp_hwint : 1; /* Unit supports FASTPATH HW interrupt cpu affinity */g unsigned ucb$v_iopost_local : 1; /* Unit supports I/O post processing on the current CPU */ } ucb$r_sts_bits; } ucb$r_sts_overlay; __union {N 2Wunsigned int ucb$l_devsts; /*DEVICE DEPENDENT STATUS */N __struct { /* Generally used bits */N unsigned ucb$v_job : 1; /* Job Controller notified *// unsigned ucb$v_devsts_gen_fill : 5;N unsigned ucb$v_templ_bsy : 1; /* Template UCB is busy */' unsigned ucb$v_fill_2_ : 1;( } ucb$r_devsts_general_bits;N __struct { /* Mailbox status bi 3Wts */N unsigned ucb$v_prmmbx : 1; /* Permanent mailbox */N unsigned ucb$v_delmbx : 1; /* Mailbox marked for delete */' unsigned ucb$v_fill_3_ : 6;' } ucb$r_devsts_mailbx_bits;N __struct { /* Terminal status bits */. unsigned ucb$v_devsts_tt_fill : 1;R unsigned ucb$v_tt_timo : 1; /* Terminal read timeout in progress */[ unsigned ucb$v_tt_4Wnotif : 1; /* Terminal user notified of unsolicted data */N unsigned ucb$v_tt_hangup : 1; /* Process hang up */P unsigned ucb$v_tt_devsts_fill : 11; /* fill to the end the word */N unsigned ucb$v_tt_nologins : 1; /* NOLOGINS ALLOWED */% } ucb$r_devsts_term_bits;N __struct { /* Network status bits */0 unsigned ucb$v_devsts_net_fill1 : 2;N unsigned ucb$v_nt_ 5Wbfrovf : 1; /* Too many bytes rcvd */0 unsigned ucb$v_devsts_net_fill2 : 1;Q unsigned ucb$v_nt_name : 1; /* Link has declared a connect name */N unsigned ucb$v_nt_break : 1; /* Link is being broken */' unsigned ucb$v_fill_4_ : 2;$ } ucb$r_devsts_net_bits;N __struct { /* Disk (all disks) status bits */N unsigned ucb$v_ecc : 1; /* ECC correction was made */N 6W unsigned ucb$v_diagbuf : 1; /* Diagnostic buffer specified */R unsigned ucb$v_nocnvrt : 1; /* No LBN to media address conversion */O unsigned ucb$v_dx_write : 1; /* Console floppy write operation */N unsigned ucb$v_datacache : 1; /* Data blocks being cached */' unsigned ucb$v_fill_5_ : 3;! } ucb$r_devsts_disks;N __struct { /* MSCP class driver bits */+ unsigned ucb7W$v_byte_fill_1 : 8;T unsigned ucb$v_mscp_mntverip : 1; /* Mount verification in progress */N unsigned ucb$v_mscp_initing : 1; /* UCB is being initialized */N unsigned ucb$v_mscp_waitbmp : 1; /* RWAITCNT has been bumped */] unsigned ucb$v_mscp_flovr : 1; /* Bit toggled everytime a failover succeeds. */Y unsigned ucb$v_mscp_pkack : 1; /* Set when a IO$_PACKACK is in progress. */X unsigned ucb$v_mscp_wrtp : 1; /* Uni8Wt MSCP write protected in some way. */c unsigned ucb$v_mscp_ignsrv : 1; /* Ignore served paths during connection failover. */[ unsigned ucb$v_mscp_mvrestart : 1; /* Restart Mount Ver to pickup new path */o unsigned ucb$v_mscp_local_drain_waitbmp : 1; /* RWAIT bumped due to io$_local_drain processing */' unsigned ucb$v_fill_6_ : 7;+ } ucb$r_devsts_mscp_class_bits;N __struct { /* Disk class driver bits 9W */+ unsigned ucb$v_unused_fill : 3;Z unsigned ucb$v_du_shmv_strtd : 1; /* Shadowing mount verification started */. unsigned ucb$v_skip_datacache : 1;N unsigned ucb$v_du_0mnote : 1; /* Zero members message sent */R unsigned ucb$v_mvfkbbsy : 1; /* DUTU mount verify fork block busy */S unsigned ucb$v_gtunmbsy : 1; /* DUTU get unit name fork block busy */) } ucb$r_devsts_du_class_bits;N __stru:Wct { /* Tape class driver bits */N unsigned ucb$v_tu_ovrsqchk : 1; /* Override sequence checking */N unsigned ucb$v_tu_traceact : 1; /* IRP trace table active */[ unsigned ucb$v_tu_seqnop : 1; /* Sequential NOP tape operation in progress */N unsigned ucb$v_tu_1dens : 1; /* Single density device */b unsigned ucb$v_tu_dens_determined : 1; /* Density already determined. Basically a */N/* ;Wbit that says that a particular part of */N/* PACKACK processing has already been done */N/* once for this unit. */d unsigned ucb$v_tu_media_loaded : 1; /* Media loaded into drive and drive available. */- unsigned ucb$v_unused_fill_2 : 2;) } ucb$r_devsts_tu_class_bits;N __struct { /* Shadowing virtual driver bits */Wen creating membership event threads stall new I/O */ unsigned ucb$v_shd_tgr_validate : 1; /* SHLK$TRIGGER_VALIDATE when another system has finished changing VU membership\ */' unsigned ucb$v_fill_7_ : 4;$ } ucb$r_devsts_shd_bits;N __struct { /* PADRIVER bits */N unsigned ucb$v_port_online : 1; /* Port is online. */N unsigned ucb$v_fklock : 1; /* Fork block interlock bit ?W */N unsigned ucb$v_msgfklock : 1; /* Fork block interlock for */N/* printing operator msgs */N unsigned ucb$v_inifklock : 1; /* Fork block interlock for */N/* adapter errors */N unsigned ucb$v_bad_rev : 1; /* Bad Port Revision flag */N unsigned ucb$v_pa_erlogip : 1; /* Error log buffer in the */N/* extended UC@WB is in use */N unsigned ucb$v_mfqefklock : 1; /* Fork block interlock for */N/* emergency pool allocation */N unsigned ucb$v_mfqe_lost : 1; /* Lost MFQE interrupt because */N/* the fork block was in use */# } ucb$r_devsts_pa_bits;N __struct { /* Shadowing virtual driver bits */+ AW unsigned ucb$v_byte_fill_6 : 8;N unsigned ucb$v_admin_online : 1; /* Admin unit is on-line */N unsigned ucb$v_admin_init : 1; /* Admin unit init in-progress */V unsigned ucb$v_admin_tear_down : 1; /* Admin unit tear down in-progress */+ unsigned ucb$v_byte_fill_8 : 5;N unsigned ucb$v_chan_online : 1; /* Channel is on-line */N unsigned ucb$v_chan_init : 1; /* Channel init in-progress */R BW unsigned ucb$v_chan_tear_down : 1; /* Channel tear down in-progress */+ unsigned ucb$v_byte_fill_9 : 5;N unsigned ucb$v_pb_tqe_busy : 1; /* PB_TQE is busy */R unsigned ucb$v_mbr_callback : 1; /* Galaxy Membership Callback has */N/* been registered */N unsigned ucb$v_shutdown_req : 1; /* Shutdown Requsted */N unsigned ucb$v_shutdown_ip : 1; /* Shutdown In Pro CWgress */O unsigned ucb$v_pb_last_gasp_emulated : 1; /* Last gasp emulation */N/* initiated */' unsigned ucb$v_fill_8_ : 3;# } ucb$r_devsts_pb_bits; } ucb$r_devsts_overlay;N int ucb$l_qlen; /* Device queue length */N/* */N/* UCB$PS_START_AFF_QFL is used by IOC$INITIATE, DWIOC$INITIATE_NEW_IO and */N/* IOC$INITIATE_PORT_CPU as follows, and any new use of this cell must */N/* conform to this logic; also note that all reads from and writes to */N/* this cell must be performed holding IOLOCK8. */N/* */N/* 1) If the field contains the UCB's address: */N/* */EWN/* - The UCB is not on any CPU's Start I/O Affinity queue */N/* - The UCB is being processed by IOC$INITIATE_PORT_CPU */N/* */N/* 1) If the field is zero: */N/* */N/* - The UCB is not on any CPU's Start I/O Affinity queue */N/* - The UCB is noFWt being processed by IOC$INITIATE_PORT_CPU */N/* */N/* 3) The only other values this field should ever take are those which */N/* are written to it when it is used to queue the UCB to a CPU's */N/* Start I/O Affinity queue */N/* */N struct _ucb *ucb$ps_start_aff_qfl; /*CPUDB AfGWfinity queue flink */N struct _ucb *ucb$ps_start_aff_qbl; /*CPUDB Affinity queue blink */N struct _cpu *ucb$l_port_cpudb; /*Device's CPUDB addr for FastPath */N struct _iocnt *ucb$ps_io_counters; /*IOCNT debug counters */N unsigned int ucb$l_duetim; /*DUE TIME FOR I/O COMPLETION */N unsigned int ucb$l_opcnt; /*COUNT OF OPERATIONS COMPLETED */U unsigned int ucb$l_svpn; /*SYSTEM VIRTUAL PAGE/MAP REGISTER NHWUMBER */S struct _bufio *ucb$ps_bufio_pkt; /* 32-bit pointer to buffered I/O packet */N unsigned int ucb$l_bcnt; /*BYTE COUNT OF TRANSFER */N unsigned int ucb$l_boff; /*Byte offset in page */N unsigned int ucb$l_softerrcnt; /*SOFT ERROR COUNT */X unsigned int ucb$l_ertcnt; /*ERROR LOG DEVICE CURRENT ERROR RETRY COUNT */X unsigned int ucb$l_ertmax; /*ERROR LOG DEVICE MAXIMUM ERROR RETRYIW COUNT */N unsigned int ucb$l_errcnt; /*DEVICE ERROR COUNT */N struct _pdt *ucb$l_pdt; /*ADDR OF PORT DESCRIPTOR TABLE */R struct _ddt *ucb$l_ddt; /*ADDR OF DDT (OPTIONAL BUT PREFERRED) */N struct _adp *ucb$ps_adp; /*ADDR OF ADP */Q struct _crctx *ucb$ps_crctx; /*ADDR OF COUNTED RESOURCE CONTEXT BLK */ __union {N unsigned int ucb$l_media_id; /*BIT ENCODED MEDIA IDENTIFICAJWTION */ __struct {N unsigned ucb$v_media_id_nn : 7; /* MEDIA NAME NUMBER */N unsigned ucb$v_media_id_n2 : 5; /* MEDIA NAME CHAR 2 */N unsigned ucb$v_media_id_n1 : 5; /* MEDIA NAME CHAR 1 */N unsigned ucb$v_media_id_n0 : 5; /* MEDIA NAME CHAR 0 */N unsigned ucb$v_media_id_t1 : 5; /* MEDIA TYPE CHAR 1 */N unsigned ucb$v_media_id_t0 : 5; /* MEDIA TYPE CHAR 0 KW */' } ucb$r_media_id_subfields;! } ucb$r_media_id_overlay;O struct _dtn *ucb$ps_dtn; /*ADDR OF DEVICE TYPE NAME DTN STRUC */T struct _ucb *ucb$ps_dtn_link; /* ADDR OF NEXT UCB WITH THIS DEVICE TYPE */S void (*ucb$ps_toutrout)(); /*DEVICE TIMEOUT ROUTINE PROCEDURE VALUE */N struct _sud *ucb$ps_sud; /*ADDR OF SUD FOR THIS UCB */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4. LW0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif int ucb$l_spare_space [8];N/*Spare Space - Reserved for use by VSI */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_svapte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else$ unsigned __int64 ucb$pq_sva MWpte_sva;#endifN/* X-124 */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */_ struct _ext *ucb$pq_extent; /* Pointer to 1st of extents to use for buffered I/O */#else unsigned __int64 ucb$pq_extent;#endif#pragma __nomember_alignmentY int ucb$l_extent_boff; /* Byte offset NW into 1st extent of EXTENTS list */ char ucb$b_fill_9_ [4]; } UCB; #if !defined(__VAXC)7#define ucb$r_ucb_fkb ucb$r_ucb_fkb_union.ucb$r_ucb_fkbY#define ucb$l_fqfl ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fqfl_overlay.ucb$l_fqflv#define ucb$l_unit_seed ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fqfl_overlay.ucb$r_seed_overlay.ucb$l_unit_seedv#define ucb$w_unit_seed ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fqfl_overlay.ucb$r_seed_overlay.ucb$w_unit_seedr#define ucOWb$w_mb_seed ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fqfl_overlay.ucb$r_seed_overlay.ucb$w_mb_seedY#define ucb$l_rqfl ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fqfl_overlay.ucb$l_rqflc#define ucb$l_mb_msgqfl ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fqfl_overlay.ucb$l_mb_msgqflY#define ucb$l_fqbl ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fqbl_overlay.ucb$l_fqblY#define ucb$l_rqbl ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fqbl_overlay.ucb$l_rqblc#define ucb$l_mb_msgqbPWl ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fqbl_overlay.ucb$l_mb_msgqblF#define ucb$w_size ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$w_sizeF#define ucb$b_type ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$b_typeF#define ucb$b_flck ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$b_flckV#define ucb$l_fpc ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fpc_overlay.ucb$l_fpc\#define ucb$l_astqfl ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fpc_overlay.ucb$l_astqfl`#define ucb$l_mb_w_ast ucb$rQW_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fpc_overlay.ucb$l_mb_w_ast^#define ucb$t_partner ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fpc_overlay.ucb$t_partnerV#define ucb$q_fr3 ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fr3_overlay.ucb$q_fr3h#define ucb$l_fr3 ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fr3_overlay.ucb$r_fr3_q_block.ucb$l_fr3\#define ucb$l_astqbl ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fr3_overlay.ucb$l_astqbl`#define ucb$l_mb_r_ast ucb$r_ucb_fkb_union.ucb$r_ucbRW_fkb_struct.ucb$r_fr3_overlay.ucb$l_mb_r_astV#define ucb$q_fr4 ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fr4_overlay.ucb$q_fr4p#define ucb$w_msgmax ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fr4_overlay.ucb$r_mb_fr4_fields.ucb$w_msgmaxp#define ucb$w_msgcnt ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fr4_overlay.ucb$r_mb_fr4_fields.ucb$w_msgcntZ#define ucb$l_first ucb$r_ucb_fkb_union.ucb$r_ucb_fkb_struct.ucb$r_fr4_overlay.ucb$l_firstP#define ucb$ps_spinlock ucb$r_ucb_fkb_union.ucb$r_uc SWb_fkb_struct.ucb$ps_spinlock6#define ucb$w_bufquo ucb$r_bufquo_overlay.ucb$w_bufquo8#define ucb$w_dstaddr ucb$r_bufquo_overlay.ucb$w_dstaddr6#define ucb$w_iniquo ucb$r_iniquo_overlay.ucb$w_iniquo8#define ucb$w_srcaddr ucb$r_iniquo_overlay.ucb$w_srcaddr6#define ucb$l_lockid ucb$r_lockid_overlay.ucb$l_lockid2#define ucb$l_cpid ucb$r_lockid_overlay.ucb$l_cpid1#define ucb$q_devchar ucb$r_devchar.ucb$q_devcharG#define ucb$l_devchar ucb$r_devchar.ucb$r_devchar_q_block.ucb$l_devcharI#define ucb$l_TWdevchar2 ucb$r_devchar.ucb$r_devchar_q_block.ucb$l_devchar2H#define ucb$r_cbb_affinity ucb$r_cbb_affinity_overlay.ucb$r_cbb_affinity#define ucb$l_affinity ucb$r_cbb_affinity_overlay.ucb$r_cbb_affinity_compat_overlay.ucb$r_cbb_affinity_data_overlay.ucb$l_affinity#define ucb$q_affinity ucb$r_cbb_affinity_overlay.ucb$r_cbb_affinity_compat_overlay.ucb$r_cbb_affinity_data_overlay.ucb$q_affinity0#define ucb$l_xtra ucb$r_xtra_overlay.ucb$l_xtra6#define ucb$l_altiowq ucb$r_xtra_overlay.ucb$l_altiowqAUW#define ucb$q_devdepend ucb$r_devdepend_q_overlay.ucb$q_devdependQ#define ucb$r_devdepend_q_block ucb$r_devdepend_q_overlay.ucb$r_devdepend_q_blockW#define ucb$l_devdepend ucb$r_devdepend_q_block.ucb$r_devdepend_overlay.ucb$l_devdependa#define ucb$r_disk_devdepend ucb$r_devdepend_q_block.ucb$r_devdepend_overlay.ucb$r_disk_devdepend8#define ucb$b_sectors ucb$r_disk_devdepend.ucb$b_sectors6#define ucb$b_tracks ucb$r_disk_devdepend.ucb$b_tracks<#define ucb$w_cylinders ucb$r_disk_devdepend.ucb$wVW_cylindersa#define ucb$r_term_devdepend ucb$r_devdepend_q_block.ucb$r_devdepend_overlay.ucb$r_term_devdepend6#define ucb$b_vertsz ucb$r_term_devdepend.ucb$b_vertsz_#define ucb$r_net_devdepend ucb$r_devdepend_q_block.ucb$r_devdepend_overlay.ucb$r_net_devdepend5#define ucb$b_locsrv ucb$r_net_devdepend.ucb$b_locsrv5#define ucb$b_remsrv ucb$r_net_devdepend.ucb$b_remsrv;#define ucb$w_bytestogo ucb$r_net_devdepend.ucb$w_bytestogoW#define ucb$l_devdepnd2 ucb$r_devdepend_q_block.ucb$r_devdepnd2_ovWWerlay.ucb$l_devdepnd2W#define ucb$l_tt_devdp1 ucb$r_devdepend_q_block.ucb$r_devdepnd2_overlay.ucb$l_tt_devdp1Y#define ucb$w_tu_formenu ucb$r_devdepend_q_block.ucb$r_devdepnd2_overlay.ucb$w_tu_formenuD#define ucb$q_devdepend2 ucb$r_devdepend2_q_overlay.ucb$q_devdepend2T#define ucb$r_devdepend2_q_block ucb$r_devdepend2_q_overlay.ucb$r_devdepend2_q_blockX#define ucb$l_devdepnd3 ucb$r_devdepend2_q_block.ucb$r_devdepnd3_overlay.ucb$l_devdepnd3X#define ucb$l_devdepnd4 ucb$r_devdepend2_q_block.ucb$r XW_devdepnd4_overlay.ucb$l_devdepnd4@#define ucb$r_tmv_bcnt ucb$r_devdepend2_q_overlay.ucb$r_tmv_bcnt6#define ucb$w_tmv_bcnt1 ucb$r_tmv_bcnt.ucb$w_tmv_bcnt16#define ucb$w_tmv_bcnt2 ucb$r_tmv_bcnt.ucb$w_tmv_bcnt26#define ucb$w_tmv_bcnt3 ucb$r_tmv_bcnt.ucb$w_tmv_bcnt36#define ucb$w_tmv_bcnt4 ucb$r_tmv_bcnt.ucb$w_tmv_bcnt40#define ucb$w_unit ucb$r_unit_overlay.ucb$w_unit0#define ucb$l_unit ucb$r_unit_overlay.ucb$l_unit6#define ucb$w_charge ucb$r_charge_overlay.ucb$w_charge:#define ucb$w_rwaitcnt u YWcb$r_charge_overlay.ucb$w_rwaitcntI#define ucb$b_cm1 ucb$r_charge_overlay.ucb$r_ctrlr_alloc_fields.ucb$b_cm1I#define ucb$b_cm2 ucb$r_charge_overlay.ucb$r_ctrlr_alloc_fields.ucb$b_cm20#define ucb$b_dipl ucb$r_dipl_overlay.ucb$b_dipl2#define ucb$b_state ucb$r_dipl_overlay.ucb$b_state-#define ucb$l_sts ucb$r_sts_overlay.ucb$l_sts<#define ucb$v_tim ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_tim<#define ucb$v_int ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_intD#define ucb$v_erlogip ucb$r_sts_overlay.ucb$ ZWr_sts_bits.ucb$v_erlogipB#define ucb$v_cancel ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_cancelB#define ucb$v_online ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_online@#define ucb$v_power ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_powerB#define ucb$v_timout ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_timoutD#define ucb$v_inttype ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_inttype<#define ucb$v_bsy ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_bsyF#define ucb$v_mounting ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_mountingB#defin[We ucb$v_deadmo ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_deadmo@#define ucb$v_valid ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_validB#define ucb$v_unload ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_unloadF#define ucb$v_template ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_templateF#define ucb$v_mntverip ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_mntveripF#define ucb$v_wrongvol ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_wrongvolH#define ucb$v_deleteucb ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_deleteucbH#define ucb$v_lcl_va\Wlid ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_lcl_validF#define ucb$v_supmvmsg ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_supmvmsgH#define ucb$v_mntverpnd ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_mntverpndF#define ucb$v_dismount ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_dismountD#define ucb$v_clutran ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_clutranH#define ucb$v_wrtlockmv ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_wrtlockmvF#define ucb$v_svpn_end ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_svpn_endB#define ucb$v_altb]Wsy ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_altbsyF#define ucb$v_snapshot ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_snapshotH#define ucb$v_no_assign ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_no_assignL#define ucb$v_exfunc_supp ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_exfunc_suppH#define ucb$v_fast_path ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_fast_pathH#define ucb$v_pathverip ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_pathveripF#define ucb$v_fp_hwint ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_fp_hwintN#define ucb$^Wv_iopost_local ucb$r_sts_overlay.ucb$r_sts_bits.ucb$v_iopost_local6#define ucb$l_devsts ucb$r_devsts_overlay.ucb$l_devstsJ#define ucb$v_job ucb$r_devsts_overlay.ucb$r_devsts_general_bits.ucb$v_jobV#define ucb$v_templ_bsy ucb$r_devsts_overlay.ucb$r_devsts_general_bits.ucb$v_templ_bsyO#define ucb$v_prmmbx ucb$r_devsts_overlay.ucb$r_devsts_mailbx_bits.ucb$v_prmmbxO#define ucb$v_delmbx ucb$r_devsts_overlay.ucb$r_devsts_mailbx_bits.ucb$v_delmbxO#define ucb$v_tt_timo ucb$r_devsts_overlay.ucb$r_devst_Ws_term_bits.ucb$v_tt_timoQ#define ucb$v_tt_notif ucb$r_devsts_overlay.ucb$r_devsts_term_bits.ucb$v_tt_notifS#define ucb$v_tt_hangup ucb$r_devsts_overlay.ucb$r_devsts_term_bits.ucb$v_tt_hangup]#define ucb$v_tt_devsts_fill ucb$r_devsts_overlay.ucb$r_devsts_term_bits.ucb$v_tt_devsts_fillW#define ucb$v_tt_nologins ucb$r_devsts_overlay.ucb$r_devsts_term_bits.ucb$v_tt_nologinsR#define ucb$v_nt_bfrovf ucb$r_devsts_overlay.ucb$r_devsts_net_bits.ucb$v_nt_bfrovfN#define ucb$v_nt_name ucb$r_devsts_ove`Wrlay.ucb$r_devsts_net_bits.ucb$v_nt_nameP#define ucb$v_nt_break ucb$r_devsts_overlay.ucb$r_devsts_net_bits.ucb$v_nt_breakC#define ucb$v_ecc ucb$r_devsts_overlay.ucb$r_devsts_disks.ucb$v_eccK#define ucb$v_diagbuf ucb$r_devsts_overlay.ucb$r_devsts_disks.ucb$v_diagbufK#define ucb$v_nocnvrt ucb$r_devsts_overlay.ucb$r_devsts_disks.ucb$v_nocnvrtM#define ucb$v_dx_write ucb$r_devsts_overlay.ucb$r_devsts_disks.ucb$v_dx_writeO#define ucb$v_datacache ucb$r_devsts_overlay.ucb$r_devsts_disks.ucb$v_datacaaWchea#define ucb$v_mscp_mntverip ucb$r_devsts_overlay.ucb$r_devsts_mscp_class_bits.ucb$v_mscp_mntverip_#define ucb$v_mscp_initing ucb$r_devsts_overlay.ucb$r_devsts_mscp_class_bits.ucb$v_mscp_initing_#define ucb$v_mscp_waitbmp ucb$r_devsts_overlay.ucb$r_devsts_mscp_class_bits.ucb$v_mscp_waitbmp[#define ucb$v_mscp_flovr ucb$r_devsts_overlay.ucb$r_devsts_mscp_class_bits.ucb$v_mscp_flovr[#define ucb$v_mscp_pkack ucb$r_devsts_overlay.ucb$r_devsts_mscp_class_bits.ucb$v_mscp_pkackY#define ucb$v_msbWcp_wrtp ucb$r_devsts_overlay.ucb$r_devsts_mscp_class_bits.ucb$v_mscp_wrtp]#define ucb$v_mscp_ignsrv ucb$r_devsts_overlay.ucb$r_devsts_mscp_class_bits.ucb$v_mscp_ignsrvc#define ucb$v_mscp_mvrestart ucb$r_devsts_overlay.ucb$r_devsts_mscp_class_bits.ucb$v_mscp_mvrestartw#define ucb$v_mscp_local_drain_waitbmp ucb$r_devsts_overlay.ucb$r_devsts_mscp_class_bits.ucb$v_mscp_local_drain_waitbmp_#define ucb$v_du_shmv_strtd ucb$r_devsts_overlay.ucb$r_devsts_du_class_bits.ucb$v_du_shmv_strtdW#define ucb$cWv_du_0mnote ucb$r_devsts_overlay.ucb$r_devsts_du_class_bits.ucb$v_du_0mnoteU#define ucb$v_mvfkbbsy ucb$r_devsts_overlay.ucb$r_devsts_du_class_bits.ucb$v_mvfkbbsyU#define ucb$v_gtunmbsy ucb$r_devsts_overlay.ucb$r_devsts_du_class_bits.ucb$v_gtunmbsy[#define ucb$v_tu_ovrsqchk ucb$r_devsts_overlay.ucb$r_devsts_tu_class_bits.ucb$v_tu_ovrsqchk[#define ucb$v_tu_traceact ucb$r_devsts_overlay.ucb$r_devsts_tu_class_bits.ucb$v_tu_traceactW#define ucb$v_tu_seqnop ucb$r_devsts_overlay.ucb$r_devsts_tu_cladWss_bits.ucb$v_tu_seqnopU#define ucb$v_tu_1dens ucb$r_devsts_overlay.ucb$r_devsts_tu_class_bits.ucb$v_tu_1densi#define ucb$v_tu_dens_determined ucb$r_devsts_overlay.ucb$r_devsts_tu_class_bits.ucb$v_tu_dens_determinedc#define ucb$v_tu_media_loaded ucb$r_devsts_overlay.ucb$r_devsts_tu_class_bits.ucb$v_tu_media_loadedV#define ucb$v_shd_wlg_inv ucb$r_devsts_overlay.ucb$r_devsts_shd_bits.ucb$v_shd_wlg_inv^#define ucb$v_shd_seqcmd_here ucb$r_devsts_overlay.ucb$r_devsts_shd_bits.ucb$v_shd_seqcmd_hereeW`#define ucb$v_shd_seqcmd_there ucb$r_devsts_overlay.ucb$r_devsts_shd_bits.ucb$v_shd_seqcmd_there\#define ucb$v_shd_passive_mv ucb$r_devsts_overlay.ucb$r_devsts_shd_bits.ucb$v_shd_passive_mv`#define ucb$v_shd_node_failure ucb$r_devsts_overlay.ucb$r_devsts_shd_bits.ucb$v_shd_node_failure\#define ucb$v_shd_wlgsta_cha ucb$r_devsts_overlay.ucb$r_devsts_shd_bits.ucb$v_shd_wlgsta_cha^#define ucb$v_shd_vcb_dequeue ucb$r_devsts_overlay.ucb$r_devsts_shd_bits.ucb$v_shd_vcb_dequeue^#define ucb$v_shd_seqcmdfW_pend ucb$r_devsts_overlay.ucb$r_devsts_shd_bits.ucb$v_shd_seqcmd_pend^#define ucb$v_shd_st_drain_io ucb$r_devsts_overlay.ucb$r_devsts_shd_bits.ucb$v_shd_st_drain_io`#define ucb$v_shd_mbrshp_event ucb$r_devsts_overlay.ucb$r_devsts_shd_bits.ucb$v_shd_mbrshp_event`#define ucb$v_shd_tgr_validate ucb$r_devsts_overlay.ucb$r_devsts_shd_bits.ucb$v_shd_tgr_validateU#define ucb$v_port_online ucb$r_devsts_overlay.ucb$r_devsts_pa_bits.ucb$v_port_onlineK#define ucb$v_fklock ucb$r_devsts_overlay.ucb$r_devstsgW_pa_bits.ucb$v_fklockQ#define ucb$v_msgfklock ucb$r_devsts_overlay.ucb$r_devsts_pa_bits.ucb$v_msgfklockQ#define ucb$v_inifklock ucb$r_devsts_overlay.ucb$r_devsts_pa_bits.ucb$v_inifklockM#define ucb$v_bad_rev ucb$r_devsts_overlay.ucb$r_devsts_pa_bits.ucb$v_bad_revS#define ucb$v_pa_erlogip ucb$r_devsts_overlay.ucb$r_devsts_pa_bits.ucb$v_pa_erlogipS#define ucb$v_mfqefklock ucb$r_devsts_overlay.ucb$r_devsts_pa_bits.ucb$v_mfqefklockQ#define ucb$v_mfqe_lost ucb$r_devsts_overlay.ucb$r_devsts_pa_bhWits.ucb$v_mfqe_lostW#define ucb$v_admin_online ucb$r_devsts_overlay.ucb$r_devsts_pb_bits.ucb$v_admin_onlineS#define ucb$v_admin_init ucb$r_devsts_overlay.ucb$r_devsts_pb_bits.ucb$v_admin_init]#define ucb$v_admin_tear_down ucb$r_devsts_overlay.ucb$r_devsts_pb_bits.ucb$v_admin_tear_downU#define ucb$v_chan_online ucb$r_devsts_overlay.ucb$r_devsts_pb_bits.ucb$v_chan_onlineQ#define ucb$v_chan_init ucb$r_devsts_overlay.ucb$r_devsts_pb_bits.ucb$v_chan_init[#define ucb$v_chan_tear_down ucb$r_devstiWs_overlay.ucb$r_devsts_pb_bits.ucb$v_chan_tear_downU#define ucb$v_pb_tqe_busy ucb$r_devsts_overlay.ucb$r_devsts_pb_bits.ucb$v_pb_tqe_busyW#define ucb$v_mbr_callback ucb$r_devsts_overlay.ucb$r_devsts_pb_bits.ucb$v_mbr_callbackW#define ucb$v_shutdown_req ucb$r_devsts_overlay.ucb$r_devsts_pb_bits.ucb$v_shutdown_reqU#define ucb$v_shutdown_ip ucb$r_devsts_overlay.ucb$r_devsts_pb_bits.ucb$v_shutdown_ipi#define ucb$v_pb_last_gasp_emulated ucb$r_devsts_overlay.ucb$r_devsts_pb_bits.ucb$v_pb_last_gaspjW_emulated<#define ucb$l_media_id ucb$r_media_id_overlay.ucb$l_media_id[#define ucb$v_media_id_nn ucb$r_media_id_overlay.ucb$r_media_id_subfields.ucb$v_media_id_nn[#define ucb$v_media_id_n2 ucb$r_media_id_overlay.ucb$r_media_id_subfields.ucb$v_media_id_n2[#define ucb$v_media_id_n1 ucb$r_media_id_overlay.ucb$r_media_id_subfields.ucb$v_media_id_n1[#define ucb$v_media_id_n0 ucb$r_media_id_overlay.ucb$r_media_id_subfields.ucb$v_media_id_n0[#define ucb$v_media_id_t1 ucb$r_media_id_overlay.ucb$r_m kWedia_id_subfields.ucb$v_media_id_t1[#define ucb$v_media_id_t0 ucb$r_media_id_overlay.ucb$r_media_id_subfields.ucb$v_media_id_t0"#endif /* #if !defined(__VAXC) */ N#define UCB$K_LENGTH 496 /*LENGTH OF STANDARD UCB */N#define UCB$C_LENGTH 496 /*LENGTH OF STANDARD UCB */S#define UCB$S_UCBDEF 496 /*OLD UCBDEF SIZE NAME FOR COMPATIBILITY */N/* */N/* DEVIC lWE DEPENDENT UCB EXTENSIONS */N/* */N/* MAILBOX */N/* */  9#ifdef __cplusplus /* Define structure prototypes */ struct _irp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If usin mWg pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mb_ucb {#pragma __nomember_alignment UCB ucb$r_ucb;_ unsigned int ucb$l_mb_readerrefc; /*REFERENCE COUNT OF READ ENABLED CHANNELS TO DEVICE */` unsigned int ucb$l_mb_writerrefc; /*REFERENCE COUNT OF WRITE ENABLED CHANNELS TO DEVICE */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __ nWshort /* And set ptr size default to 32-bit pointers */#endifN struct _irp *ucb$l_mb_readqfl; /*MAILBOX READ IRP QUEUE LISTHEAD */" struct _irp *ucb$l_mb_readqbl;` int ucb$l_mb_writerwaitqfl; /*MAILBOX WAIT FOR WRITE CHANNEL TO BE ASSIGNED QUEUE */ int ucb$l_mb_writerwaitqbl;_ int ucb$l_mb_readerwaitqfl; /*MAILBOX WAIT FOR READ CHANNEL TO BE ASSIGNED QUEUE */ int ucb$l_mb_readerwaitqbl;g int ucb$l_mb_nowriterwaitqfl; /*MAILBOX WAIT FOR oW ALL WRITE CHANNELS TO BE DEASSIGNED QUEUE */! int ucb$l_mb_nowriterwaitqbl;f int ucb$l_mb_noreaderwaitqfl; /*MAILBOX WAIT FOR ALL READ CHANNELS TO BE DEASSIGNED QUEUE */! int ucb$l_mb_noreaderwaitqbl;N int ucb$l_mb_room_notify; /*ROOM NOTIFY AST LIST */ __union {N void *ucb$l_logadr; /*LOGICAL NAME BLOCK ADDRESS */ __struct {U void *ucb$l_mb_logadr; /* and a synonym to let SDA find the field *pW/ } ucb$r_fill_11_; } ucb$r_fill_10_;U void (*ucb$ps_mb_last_channel)(); /*Pointer to Last channel deassign routine */O char ucb$t_quad_fill1 [4]; /* Fill bytes for quadword alignment */z unsigned __int64 ucb$q_mb_context; /*64 bit context data passed back when last channel deassign rotuine is called. */N int ucb$l_mb_bufquo; /*MAILBOX Buffer Quota */N int ucb$l_mb_iniquo; /*MAILBOX Initial Buffer Quo qWta */ } MB_UCB; #if !defined(__VAXC)0#define ucb$l_logadr ucb$r_fill_10_.ucb$l_logadrE#define ucb$l_mb_logadr ucb$r_fill_10_.ucb$r_fill_11_.ucb$l_mb_logadr"#endif /* #if !defined(__VAXC) */ N#define UCB$K_MB_UCBLENGTH 576 /*SIZE OF MAILBOX UCB */N#define UCB$C_MB_UCBLENGTH 576 /*SIZE OF MAILBOX UCB */O#define UCB$C_MB_LENGTH 576 /*SIZE OF MAILBOX UCB for SDA FORMAT */T#define UCB$S_MB_EXTENSION 576 /* Old s rWtep-1 size name for compatibility */ & #define ucb$r_mb_ucb ucb$r_ucbN/* */N/* ERROR LOG DEVICES (ALL) */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment sW#endiftypedef struct _erl_ucb {#pragma __nomember_alignmentN UCB ucb$r_ucb; /*COMMON UCB */N void *ucb$l_emb; /*ADDRESS OF ERROR MESSAGE BUFFER */N unsigned int ucb$l_func; /* I/O function modifiers */S void (*ucb$l_dpc)(); /*SAVED DRIVER SUBROUTINE RETURN ADDRESS */Z unsigned short int ucb$w_mt3_density; /* Current Tape Density word. (For Tape Only) */ char ucb$b_fill_ tW12_ [2]; } ERL_UCB;N#define UCB$K_ERL_LENGTH 512 /*SIZE OF ERROR LOG UCB */N#define UCB$C_ERL_LENGTH 512 /*SIZE OF ERROR LOG UCB */T#define UCB$S_UCBDEF4 512 /* Old step-1 size name for compatibility */ ' #define ucb$r_erl_ucb ucb$r_ucbN/* */N/* DUAL PORTED DEVICES (ALL DISKS AND MOST TAPES) */N/* uW */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ddb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _dp_ucb {#pragma __nomember_alignmentN ERL_UCB ucb$r_erlucb; /* Errlog UCB */ __un vWion { __struct {N struct _ddb *ucb$l_dp_ddb; /* Pointer to alternate DDB */O struct _ucb *ucb$l_dp_link; /* Address of next UCB for this DDB */S struct _ucb *ucb$l_dp_altucb; /* Addr of alternate UCB for this unit */" } ucb$r_old_dual_path; __struct {N struct _ddb *ucb$l_2p_ddb; /* Pointer to alternate DDB */O struct _ucb *ucb$l_2p_link; /* Address of next UCB for this DDB */S wW struct _ucb *ucb$l_2p_altucb; /* Addr of alternate UCB for this unit */' } ucb$r_prefered_dual_path; } ucb$r_dual_path; char ucb$b_fill_13_ [4]; } DP_UCB; #if !defined(__VAXC)E#define ucb$l_dp_ddb ucb$r_dual_path.ucb$r_old_dual_path.ucb$l_dp_ddbG#define ucb$l_dp_link ucb$r_dual_path.ucb$r_old_dual_path.ucb$l_dp_linkK#define ucb$l_dp_altucb ucb$r_dual_path.ucb$r_old_dual_path.ucb$l_dp_altucbJ#define ucb$l_2p_ddb ucb$r_dual_path.ucb$r_prefered_dual_path. xWucb$l_2p_ddbL#define ucb$l_2p_link ucb$r_dual_path.ucb$r_prefered_dual_path.ucb$l_2p_linkP#define ucb$l_2p_altucb ucb$r_dual_path.ucb$r_prefered_dual_path.ucb$l_2p_altucb"#endif /* #if !defined(__VAXC) */ N#define UCB$K_DP_LENGTH 528 /*Size of dual path UCB */N#define UCB$C_DP_LENGTH 528 /* size of dual path UCB */N#define UCB$K_2P_LENGTH 528 /*Size of dual path UCB */N#define UCB$C_2P_LENGTH 528 /* size of d yWual path UCB */T#define UCB$S_DUALPATH_EXTENSION 528 /* Old step-1 size name for compatibility */ , #define ucb$r_dp_ucb ucb$r_erlucb.ucb$r_ucb" #define ucb$r_dp_erl ucb$r_erlucbN/* */N/* ALL DISKS AND TAPES */N/* */#define UCB$M_AST_ARMED 0x8000N#define UCB$K_LCL_DISK_LENGTH 572 zW /* Size of local disk UCB */N#define UCB$C_LCL_DISK_LENGTH 572 /* Size of local disk UCB */N#define UCB$K_LCL_TAPE_LENGTH 560 /* Size of local tape UCB */N#define UCB$C_LCL_TAPE_LENGTH 560 /* Size of local tape UCB */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _dt_ucb { {W#pragma __nomember_alignment DP_UCB ucb$r_dpucb; __union {N unsigned short int ucb$w_dirseq; /* Directory sequence number */ __struct {' unsigned ucb$v_filler : 15;N unsigned ucb$v_ast_armed : 1; /* Blocking AST armed flag */ } ucb$r_fill_15_; } ucb$r_fill_14_;N unsigned char ucb$b_onlcnt; /* Online count */ char ucb$b_fill_16_ [5];c#if !defined(__NOBASEALIGN_SUPPORT) && |W!defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment __struct { __union {N unsigned __int64 ucb$q_maxblock_64; /* 64-bit highest block */U unsigned int ucb$l_maxblock; /* Random access device highest block */) } ucb$r_maxblock_overlay;N unsigned int ucb$l_maxbcnt; /* Maximum t }Wransfer BCNT */Q int ucb$l_dccb; /* Pointer to data cache control block */N unsigned int ucb$l_qlenacc; /* Queue length accumulator */N unsigned int ucb$l_usn; /* Reserved */N void *ucb$ps_mount_list; /* Reserved */N char ucb$t_mscp_dsply_path [8]; /* Displayable path buffer. */ } ucb$r_disk_fields; __struct {T unsign~Wed int ucb$l_record; /* Current tape position or frame counter */ __union {k unsigned int ucb$l_prev_record_l; /* Tape position prior at start of last I/O (longword) */_ unsigned char ucb$b_prev_record; /* Tape position prior at start of last I/O */, } ucb$r_prev_record_overlay; int ucb$l_reserved;b unsigned int ucb$l_tmv_record; /* Position following last guaranteed successful I/O */] unsigned short W int ucb$w_tmv_crc1; /* 1st CRC for Mount Ver's media validation */N unsigned short int ucb$w_tmv_crc2; /* 2nd CRC ... */N unsigned short int ucb$w_tmv_crc3; /* 3rd CRC ... */N unsigned short int ucb$w_tmv_crc4; /* 4th CRC ... */ } ucb$r_tape_fields;! } ucb$r_disktape_overlay;N unsigned int ucb$l_alloclass; /* Device allocation class */ } DT_UCB; #if !defined(__VAXC)0#defWine ucb$w_dirseq ucb$r_fill_14_.ucb$w_dirseqE#define ucb$v_ast_armed ucb$r_fill_14_.ucb$r_fill_15_.ucb$v_ast_armedk#define ucb$q_maxblock_64 ucb$r_disktape_overlay.ucb$r_disk_fields.ucb$r_maxblock_overlay.ucb$q_maxblock_64e#define ucb$l_maxblock ucb$r_disktape_overlay.ucb$r_disk_fields.ucb$r_maxblock_overlay.ucb$l_maxblockL#define ucb$l_maxbcnt ucb$r_disktape_overlay.ucb$r_disk_fields.ucb$l_maxbcntF#define ucb$l_dccb ucb$r_disktape_overlay.ucb$r_disk_fields.ucb$l_dccbL#define ucb$l_qlenacc ucWb$r_disktape_overlay.ucb$r_disk_fields.ucb$l_qlenaccD#define ucb$l_usn ucb$r_disktape_overlay.ucb$r_disk_fields.ucb$l_usnT#define ucb$ps_mount_list ucb$r_disktape_overlay.ucb$r_disk_fields.ucb$ps_mount_list\#define ucb$t_mscp_dsply_path ucb$r_disktape_overlay.ucb$r_disk_fields.ucb$t_mscp_dsply_pathJ#define ucb$l_record ucb$r_disktape_overlay.ucb$r_tape_fields.ucb$l_recordr#define ucb$l_prev_record_l ucb$r_disktape_overlay.ucb$r_tape_fields.ucb$r_prev_record_overlay.ucb$l_prev_record_ln#define ucWb$b_prev_record ucb$r_disktape_overlay.ucb$r_tape_fields.ucb$r_prev_record_overlay.ucb$b_prev_recordR#define ucb$l_tmv_record ucb$r_disktape_overlay.ucb$r_tape_fields.ucb$l_tmv_recordN#define ucb$w_tmv_crc1 ucb$r_disktape_overlay.ucb$r_tape_fields.ucb$w_tmv_crc1N#define ucb$w_tmv_crc2 ucb$r_disktape_overlay.ucb$r_tape_fields.ucb$w_tmv_crc2N#define ucb$w_tmv_crc3 ucb$r_disktape_overlay.ucb$r_tape_fields.ucb$w_tmv_crc3N#define ucb$w_tmv_crc4 ucb$r_disktape_overlay.ucb$r_tape_fields.ucb$w_tmv_crc4" W#endif /* #if !defined(__VAXC) */ N#define UCB$K_DT_LENGTH 576 /*Size of disk/tape UCB */N#define UCB$C_DT_LENGTH 576 /* size of disk/tape UCB */(#define UCB$S_DISKTAPE_UCB_EXTENSION 576N/* Old step-1 size name for compatibility */ ? #define ucb$r_dt_ucb ucb$r_dpucb.ucb$r_erlucb.ucb$r_ucb5 #define ucb$r_dt_erl ucb$r_dpucb.ucb$r_erlucb( #define ucb$r_dt_dp ucb$r_dpucbN/* W */N/* MSCP DISKS AND TAPES UCB EXTENSION */N/* */  9#ifdef __cplusplus /* Define structure prototypes */ struct _cddb; struct _cdt; struct _shad; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment W __quadword#else#pragma __nomember_alignment#endiftypedef struct _mscp_ucb {#pragma __nomember_alignment DT_UCB ucb$r_dtucb;N struct _cddb *ucb$l_cddb; /* Pointer to active CDDB */N struct _cddb *ucb$l_2p_cddb; /* Pointer to alternate CDDB */O struct _ucb *ucb$l_cddb_link; /* Pointer to next UCB in CDDB chain */N struct _cdt *ucb$l_cdt; /* Pointer to active CDT */k struct _cddb *ucb$l_wait_cddb; W/* Address of CDDB waiting for mnt. ver. to complete on this UCB */N struct _cddb *ucb$l_pref_cddb; /* CDDB address for preferred path */N unsigned __int64 ucb$q_unit_id; /* Unique MSCP unit identifier */N unsigned short int ucb$w_mscpunit; /* Primary path MSCP unit number */N unsigned short int ucb$w_unit_flags; /* MSCP unit flags */f unsigned short int ucb$w_lcl_mscpunit; /* MSCP unit number for local (non-emulated) controllers */c unsignedW short int ucb$w_srv_mscpunit; /* MSCP unit number for served (emulated) controllers */N unsigned int ucb$l_mscpdevparam; /* MSCP device-dependent parameters */N unsigned char ucb$b_freecap; /* Free capacity */N unsigned char ucb$b_fail_mutex; /* MUTEX for device failover */N unsigned short int ucb$w_mscp_resvdw; /* Reserved for MSCP enhancements */N struct _shad *ucb$l_shad; /* Virtual Unit Pointer to HBS SHAD */N unsigned int W ucb$l_dutufkblink; /* Link to permanent fork blocks */ } MSCP_UCB;N#define UCB$K_MSCP_DISK_LENGTH 632 /*Size of MSCP disk UCB */N#define UCB$C_MSCP_DISK_LENGTH 632 /*Size of MSCP disk UCB (for SDA) */N#define UCB$K_MSCP_TAPE_LENGTH 632 /*Size of MSCP tape UCB */N#define UCB$C_MSCP_TAPE_LENGTH 632 /*Size of MSCP tape UCB (for SDA) */T#define UCB$S_MSCP_UCB_EXTENSION 632 /* Old step-1 size name for compatibility */ M #defin We ucb$r_mscp_ucb ucb$r_dtucb.ucb$r_dpucb.ucb$r_erlucb.ucb$r_ucbC #define ucb$r_mscp_erl ucb$r_dtucb.ucb$r_dpucb.ucb$r_erlucb6 #define ucb$r_mscp_dp ucb$r_dtucb.ucb$r_dpucb* #define ucb$r_mscp_dt ucb$r_dtucbN/* */N/* DISK CLASS DRIVER DEVICE DEPENDENT UNIT CONTROL BLOCK OFFSETS */N/* */ c#if !defined(__NOBASEALIGN W_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _du_ucb {#pragma __nomember_alignment MSCP_UCB ucb$r_mscpucb;N unsigned int ucb$l_du_volser; /* Serial umber as returned */N/* in ONLINE end packet. */N unsigned int ucb$l_du_usize; /* Size of user visible area of */N/* unit in logiWcal blocks */N unsigned int ucb$l_du_totsz; /* Size of unit including RCT */N/* area in logical blocks */N unsigned short int ucb$w_du_rctsize; /* Size of the RCT in blocks */N unsigned char ucb$b_du_rctcpys; /* Number of RCT copies on the unit */N unsigned char ucb$b_du_rbnptrk; /* RBNs per track */N unsigned short int ucb$w_du_lbnptrk; / W* LBNs per track */N unsigned short int ucb$w_du_trkpgrp; /* Tracks per group */N unsigned short int ucb$w_du_grppcyl; /* Groups per cylinder */N unsigned short int ucb$w_du_muntc; /* Multi-unit code */N unsigned char ucb$b_du_usvr; /* Unit software version */N unsigned char ucb$b_du_uhvr; /* Unit hardware version */ char ucb$b_fill_17_ [6]; } DU_UCB;U#define UCB$K_DU_LENGT WH 664 /* Size of DISK CLASS DRIVER dependent UCB */N/* Old step-1 size name for compatibility */$#define UCB$S_DUDRIVER_EXTENSION 664 [ #define ucb$r_du_ucb ucb$r_mscpucb.ucb$r_dtucb.ucb$r_dpucb.ucb$r_erlucb.ucb$r_ucbQ #define ucb$r_du_erl ucb$r_mscpucb.ucb$r_dtucb.ucb$r_dpucb.ucb$r_erlucbD #define ucb$r_du_dp ucb$r_mscpucb.ucb$r_dtucb.ucb$r_dpucb8 #define ucb$r_du_dt ucb$r_mscpucb.ucb$r_dtucb, #def Wine ucb$r_du_mscp ucb$r_mscpucbN/* */N/* TAPE CLASS DRIVER DEVICE DEPENDENT UNIT CONTROL BLOCK OFFSETS */N/* */#define UCB$M_TU_RPTREQ 0x1#define UCB$M_TU_RPTPND 0x2#define UCB$M_TU_DENSITY 0x4 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadw Word#else#pragma __nomember_alignment#endiftypedef struct _tu_ucb {#pragma __nomember_alignment MSCP_UCB ucb$r_mscpucb;h unsigned int ucb$l_tu_maxwrcnt; /* Largest size record likely to have reliability statistics. */N unsigned short int ucb$w_tu_format; /* Format (density). */N unsigned short int ucb$w_tu_speed; /* Current speed. */Z unsigned short int ucb$w_tu_noise; /* Size of noise records ignored by controller. */N unsignWed char ucb$b_tu_softerr; /* Media quality reporting counter. */ __union {N unsigned char ucb$b_tu_softflags; /* Media quality reporting flags. */N __struct { /* Define soft error flags. */N unsigned ucb$v_tu_rptreq : 1; /* Report request. */N unsigned ucb$v_tu_rptpnd : 1; /* Report pending. */N unsigned ucb$v_tu_density : 1; /* Density check done if set. */( unsigned W ucb$v_fill_18_ : 5;& } ucb$r_tu_softflags_bits;% } ucb$r_tu_softflags_overlay;Q int ucb$l_tracebeg; /* Pointer to beginning of trace ring. */N int ucb$l_traceptr; /* Pointer to next available slot. */N int ucb$l_tracend; /* Pointer to beyond trace ring. */O int ucb$l_trace_next_slot; /* Number of next trace slot to use. */ char ucb$b_fill_19_ [4]; } TU_UCB; #if !defined(__VAXC)H#definWe ucb$b_tu_softflags ucb$r_tu_softflags_overlay.ucb$b_tu_softflagsZ#define ucb$v_tu_rptreq ucb$r_tu_softflags_overlay.ucb$r_tu_softflags_bits.ucb$v_tu_rptreqZ#define ucb$v_tu_rptpnd ucb$r_tu_softflags_overlay.ucb$r_tu_softflags_bits.ucb$v_tu_rptpnd\#define ucb$v_tu_density ucb$r_tu_softflags_overlay.ucb$r_tu_softflags_bits.ucb$v_tu_density"#endif /* #if !defined(__VAXC) */ U#define UCB$K_TU_LENGTH 664 /* Size of TAPE CLASS DRIVER dependent UCB */N/* Old step-1 size name for comp Watibility */$#define UCB$S_TUDRIVER_EXTENSION 664 [ #define ucb$r_tu_ucb ucb$r_mscpucb.ucb$r_dtucb.ucb$r_dpucb.ucb$r_erlucb.ucb$r_ucbQ #define ucb$r_tu_erl ucb$r_mscpucb.ucb$r_dtucb.ucb$r_dpucb.ucb$r_erlucbD #define ucb$r_tu_dp ucb$r_mscpucb.ucb$r_dtucb.ucb$r_dpucb8 #define ucb$r_tu_dt ucb$r_mscpucb.ucb$r_dtucb, #define ucb$r_tu_mscp ucb$r_mscpucbN/* W */N/* SCSI Port Driver Extensions */N/* */#define UCB$M_PK_IFKB_LOCK 0x1  9#ifdef __cplusplus /* Define structure prototypes */ struct _kpb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignme Wnt#endiftypedef struct _scsi_ucb {#pragma __nomember_alignment ERL_UCB ucb$r_erlucb;N unsigned int ucb$il_pk_cur_data; /* Selection bus data snapshot */N unsigned int ucb$il_pk_resel_id; /* [RE]selection saved id */ __union {N unsigned int ucb$il_pk_exflags; /* Port extended flags */ __struct {N unsigned ucb$v_pk_ifkb_lock : 1; /* Init FKB locked */( unsigned ucb$v_fill_22_ : 7; W } ucb$r_fill_21_; } ucb$r_fill_20_; __union {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN char ucb$ib_pk_inifkblk [48]; /* Initialization fork block */#pragma __nomember_alignmentN struct _kpb *ucb$ps_pk_inikpb; /* Initializtion KPB pointer */ } ucb$r_fill_pk_init; char ucb$b_fill_23_ [4 W]; } SCSI_UCB; #if !defined(__VAXC):#define ucb$il_pk_exflags ucb$r_fill_20_.ucb$il_pk_exflagsK#define ucb$v_pk_ifkb_lock ucb$r_fill_20_.ucb$r_fill_21_.ucb$v_pk_ifkb_lock@#define ucb$ib_pk_inifkblk ucb$r_fill_pk_init.ucb$ib_pk_inifkblk<#define ucb$ps_pk_inikpb ucb$r_fill_pk_init.ucb$ps_pk_inikpb"#endif /* #if !defined(__VAXC) */ N#define UCB$K_PK_LENGTH 576 /* Size of SCSI port UCB */R#define UCB$C_PK_LENGTH 576 /* Size of SCSI port UCB for SDA W FORMAT */T#define UCB$S_SCSI_PORT_EXTENSION 576 /* Old step-1 size name for compatibility */ . #define ucb$r_scsi_ucb ucb$r_erlucb.ucb$r_ucb$ #define ucb$r_scsi_erl ucb$r_erlucbN/* */N/* NETWORK LOGICAL LINK (NETWORK MAILBOX) EXTENSION */N/* */#define UCB$M_BACKP 0x20[#define UCB$C_LOGLNK 1 /* CONNECT I WS FOR LOGICAL LINK (NOT SINGLE MSG) */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _net_ucb {#pragma __nomember_alignment UCB ucb$r_ucb;V void *ucb$l_nt_datssb; /* ADDRESS OF DATA SUBCHANNEL STATUS BLOCK */N void *ucb$l_nt_intssb; /* ADDRESS OF INT/LS SSB */N unsigned short int u Wcb$w_nt_chan; /* DDCMP CHANNEL NO. */ __union {N short int ucbdef$$_fill_3; /* DUMMY FIELD */ __struct {N unsigned ucb$v_ltype : 2; /* LINK TYPE BITS */N unsigned ucb$v_segflo : 1; /* SEGMENT REQUEST COUNTS */N unsigned ucb$v_msgflo : 1; /* MESSAGE REQUEST COUNTS */N unsigned ucb$v_msgack : 1; /* MESSAGE ACK/NAK */N Wunsigned ucb$v_backp : 1; /* BACKPRESSURE (1=> NO FLOW) */N unsigned ucb$v_lnkpri : 2; /* LINK PRIORITY (IGNORED) */ } ucb$r_fill_3_bits;N/* NETWORK CONSTANTS */ } ucb$r_fill_3_overlay; char ucb$b_fill_24_ [4]; } NET_UCB; #if !defined(__VAXC)F#define ucb$v_ltype ucb$r_fill_3_overlay.ucb$r_fill_3_bits.ucb$v_ltypeH#define ucb$v_segflo ucb$r_fill_3_overlay.ucb$r_fill_3_bits.ucb$v_ WsegfloH#define ucb$v_msgflo ucb$r_fill_3_overlay.ucb$r_fill_3_bits.ucb$v_msgfloH#define ucb$v_msgack ucb$r_fill_3_overlay.ucb$r_fill_3_bits.ucb$v_msgackF#define ucb$v_backp ucb$r_fill_3_overlay.ucb$r_fill_3_bits.ucb$v_backpH#define ucb$v_lnkpri ucb$r_fill_3_overlay.ucb$r_fill_3_bits.ucb$v_lnkpri"#endif /* #if !defined(__VAXC) */ T#define UCB$S_UCBDEF7 512 /* Old step-1 size name for compatibility */ ' #define ucb$r_net_ucb ucb$r_ucbN/* W */N/* NI DEVICE EXTENSION */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ni_ucb {#pragma __nomember_alignment UCB ucb$r_ucb;R void *ucb$l_ni_hwaptr; W /*ADDRESS OF NI DEVICE HARDWARE ADDRESS */P void *ucb$l_ni_mltptr; /*ADDRESS OF PROTOCOL MULTICAST TABLE */ } NI_UCB;N#define UCB$K_NI_LENGTH 504 /*SIZE OF NI DEVICE UCB */N#define UCB$C_NI_LENGTH 504 /*SIZE OF NI DEVICE UCB */T#define UCB$S_UCBDEF9 504 /* Old step-1 size name for compatibility */ & #define ucb$r_ni_ucb ucb$r_ucbN/* W */N/* DAP DEVICE EXTENSION (FOR DEVICES THAT USE THE DAP INTERFACE WITHOUT */N/* UNDELYING DECNET, SUCH AS CERTAIN CONSOLE DISKS). */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _dap_ucb {#pragma __nomember_alignme Wnt UCB ucb$r_ucb;N char ucb$t_dapdevnam [32]; /*EQUIVALENCE NAME STRING */ } DAP_UCB;N#define UCB$K_DAPDEV_LENGTH 528 /*SIZE OF DAP DEVICE UCB */N#define UCB$C_DAPDEV_LENGTH 528 /*SIZE OF DAP DEVICE UCB */T#define UCB$S_UCBDEF10 528 /* Old step-1 size name for compatibility */ ' #define ucb$r_dap_ucb ucb$r_ucb#define UCB$K_BGN_ADPTAB 624#define UCB$M_LBDG 0x1#define UCB$M_POLL 0x2#define UCB$M_LOWCAL 0x4#define UCB$M_SINGLE_PATH 0x8#define UCB$M_STORAGE 0x10#define UCB$K_BGN_ADPSUB 652#define UCB$K_BGN_PDTSUB 716#define UCB$K_END_ADPTAB 756#define UCB$K_TAB_LEN 132#define UCB$K_LMPKTBYTS 64#define UCB$K_ERRDGBYTS 180#define UCB$K_LMBUFSIZ 104#define UCB$K_ERRDGSIZ 220 #define UCB$M_RSP_FKB_IN_USE 0x1  9#ifdef __cplusplus /* Define structure prototypes */ struct _adp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(_ W_cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _pa_ucb {N/* */N/* Skip the common UCB */N/* */#pragma __nomember_alignment ERL_UCB ucb$r_erlucb;N/* W */N/* Define private PA fields */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN char ucb$l_inifkblk [48]; /* Error fork block for handling */N/* severe adapter errors W */N char ucb$l_mfqefkblk [48]; /* Pool allocation fork block for */N/* handling message free queue */N/* interrupts */#pragma __nomember_alignmentN unsigned short int ucb$w_incarn; /* Last BVP incarnation number */ short int ucb$w_fill1;N struct _adp *ucb$l_adp; /* Address of the ADP */N unWsigned int ucb$l_inireturn; /* Initialization thread return */N/* address */ int ucb$l_fill2;N/* */Q/* Fields used to link a port driver with the generic SCS port code. The port */T/* driver initializes these routines with pointers to hardware-dependent routines */N/* at unit initialization time. */NW/* */N unsigned int ucb$l_ndt; /* Adapter hardware code */N unsigned char ucb$b_dt; /* Adapter device type */N __union { /* Initialization flags */ __struct {N unsigned ucb$v_lbdg : 1; /* Loopback datagram */N unsigned ucb$v_poll : 1; /* Configuration polling */N W unsigned ucb$v_local : 1; /* Local MSCP port (BVP ports) */N unsigned ucb$v_single_path : 1; /* Only one path available */N unsigned ucb$v_storage : 1; /* Port is for remote storage only */( unsigned ucb$v_fill_25_ : 3;# } ucb$r_ini_flags_bits;& unsigned char ucb$b_ini_flags;" } ucb$r_ini_flags_overlay; short int ucb$w_fill3;N unsigned char ucb$b_msg_typ; /* Error log message type */N unWsigned char ucb$b_pdt_type; /* Type of PDT */N unsigned short int ucb$w_pdt_size; /* Size of PDT */N unsigned int ucb$l_ppd_size; /* Size of the PPD header */N void *ucb$l_lsindx; /* Local store dump start address */N unsigned int ucb$l_lslength; /* Dump size in longwords */N void *ucb$l_pmc; /* Address of the PMC register */N/* used to disable interrupts W */N/* on port power-up */N unsigned int ucb$l_rev_table; /* Port version table */N int (*ucb$l_power_fail)(); /* Power failure recovery routine */N int (*ucb$l_init_pdt)(); /* PDT initialization routine */N int (*ucb$l_start_ucode)(); /* Microcode load and start routine */N int (*ucb$l_enb_int)(); /* Interrupt enablWe routine */N int (*ucb$l_format_rev)(); /* Verify port version routine */N int (*ucb$l_timer)(); /* Periodic wakeup routine */N int (*ucb$l_poke_port)(); /* Poke the port's sanity timer */O int (*ucb$l_interrupt)(); /* Adapter interrupt service routine */N int (*ucb$l_stop_ucode)(); /* Microcode shutdown routine */N int (*ucb$l_unmap_pdt)(); /* Unmap register pointers routine */N W int (*ucb$l_reg_dump)(); /* Register dump routine */P int (*ucb$l_reg_disp)(); /* Error log register display routine */N int (*ucb$l_mem_dump)(); /* Memory dump routine */R int (*ucb$l_release_ps)(); /* Release port status register routine */ int ucb$l_fill4;N unsigned int ucb$l_ins_comql; /* Notify port of non-empty CMDQ0 */N unsigned int ucb$l_ins_comqh; /* Notify port of non-empty CMDQ1 */N W unsigned int ucb$l_ins_dfreq; /* Notify port of non-empty DFQ */N unsigned int ucb$l_ins_mfreq; /* Notify port of non-empty MFQ */! unsigned int ucb$l_ins_comqm;! unsigned int ucb$l_init_ablk; unsigned int ucb$l_cmpl_int;! unsigned int ucb$l_misc_int2; int ucb$l_fill5 [2]; char ucb$b_fill_26_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#els We#pragma __nomember_alignment#endifN char ucb$l_msgfkblk [48]; /* Fork block for starting */N/* error messages to operator */#pragma __nomember_alignmentN unsigned int ucb$t_opa0_temp [6]; /* Field used to store optional */N/* OPA0: error logging information */N/* (access to this field is also */N/* protected by UCB$V_MSGFKLOCK) W */N unsigned char ucb$b_lmest; /* Error subtype */N unsigned char ucb$b_lmet; /* Error type */N unsigned char ucb$b_lmertcnt; /* Error retry count */N unsigned char ucb$b_lmertmax; /* Maximum error retry count */N unsigned short int ucb$w_lmerrcnt; /* Accumulated errors */ short int ucb$w_fill6;N unsigned char ucb$n_lsaddr [W6]; /* Local station address */N unsigned char ucb$n_lsid [6]; /* Local station ID */N unsigned char ucb$n_rsaddr [6]; /* Remote station address */N unsigned char ucb$n_rsid [6]; /* Remote station ID */N unsigned int ucb$l_cicmd; /* CI packet command longword */N unsigned short int ucb$w_msgbytcnt; /* CI packet byte count */N unsigned short int ucb$w_msgppdtyp; /* CI packet PPD t Wype */N unsigned char ucb$t_msgdata [64]; /* CI packet data */ char ucb$b_fill7 [116]; int ucb$l_fill8 [2];N char ucb$b_align_1 [28]; /* QUADWORD ALIGN */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN char ucb$l_rspfkblk [48]; /* Response Q fork block for thread */ WN/* that drains response Queue. */#pragma __nomember_alignment __union {N unsigned int ucb$l_rsp_sts; /* Resp Queue status mask */N __struct { /* Bit definitions for mask */N unsigned ucb$v_rsp_fkb_in_use : 1; /* Resp Q fork block in use */( unsigned ucb$v_fill_27_ : 7;! } ucb$r_rsp_sts_bits; } ucb$r_rsp_sts_overlay;P int ucb$l_reserved2 [7 W]; /* These longwords keep fork block in */N/* it's own cache block. Place only static */N/* data in these fields if necessary as this */N/* cache block is in high demand on SMP systems. */ } PA_UCB; #if !defined(__VAXC)J#define ucb$v_lbdg ucb$r_ini_flags_overlay.ucb$r_ini_flags_bits.ucb$v_lbdgJ#define ucb$v_poll ucb$r_ini_flags_overlay.ucb$r_ini_flags_bits.ucb$v_pollL#define ucb$v_lo Wcal ucb$r_ini_flags_overlay.ucb$r_ini_flags_bits.ucb$v_localX#define ucb$v_single_path ucb$r_ini_flags_overlay.ucb$r_ini_flags_bits.ucb$v_single_pathP#define ucb$v_storage ucb$r_ini_flags_overlay.ucb$r_ini_flags_bits.ucb$v_storage?#define ucb$b_ini_flags ucb$r_ini_flags_overlay.ucb$b_ini_flags9#define ucb$l_rsp_sts ucb$r_rsp_sts_overlay.ucb$l_rsp_stsZ#define ucb$v_rsp_fkb_in_use ucb$r_rsp_sts_overlay.ucb$r_rsp_sts_bits.ucb$v_rsp_fkb_in_use"#endif /* #if !defined(__VAXC) */ #define UCB$C_ WPALENGTH 1168N#define UCB$C_PA_LENGTH 1168 /* For SDA FORMAT */W#define UCB$S_PAUCBDEF 1168 /* Old PAUCBDEF size name for compatibility */ , #define ucb$r_pa_ucb ucb$r_erlucb.ucb$r_ucb" #define ucb$r_pa_erl ucb$r_erlucb#define UCB$M_PI_ENABLE 0x1#define UCB$M_PI_FKB_BUSY 0x2#define UCB$M_PI_TQE_BUSY 0x4 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __qua Wdword#else#pragma __nomember_alignment#endiftypedef struct _pi_ucb {N/* */N/* Skip the common UCB plus the PA extension */N/* */#pragma __nomember_alignment PA_UCB ucb$r_paucb;N/* */N/* Define private PI fields W */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif$ unsigned char ucb$b_pi_fkb [48];$ unsigned char ucb$b_pi_tqe [64];#pragma __nomember_alignment __union {& unsigned __int64 ucb$q_pi_tfq; __struct {% void *ucb$Wl_pi_tfq_flink;% void *ucb$l_pi_tfq_blink; } ucb$r_fill_29_; } ucb$r_fill_28_; __union {% unsigned __int64 ucb$q_pi_tq; __struct {$ void *ucb$l_pi_tq_flink;$ void *ucb$l_pi_tq_blink; } ucb$r_fill_31_; } ucb$r_fill_30_; __union {& unsigned __int64 ucb$q_pi_ifq; __struct {% void *ucb$l_pi_ifq_flink;% void *ucb$l_pi_ifq_blink; } ucWb$r_fill_33_; } ucb$r_fill_32_; __union {% unsigned __int64 ucb$q_pi_iq; __struct {$ void *ucb$l_pi_iq_flink;$ void *ucb$l_pi_iq_blink; } ucb$r_fill_35_; } ucb$r_fill_34_; unsigned int ucb$l_pi_sva; unsigned int ucb$l_pi_svpn;! unsigned int ucb$l_pi_script;% unsigned int ucb$l_pi_tgt_script;% unsigned int ucb$l_pi_dat_script;% unsigned int ucb$l_pi_ini_script;" unsigned int ucb$l_pi_Wrl_stat;! unsigned int ucb$l_pi_wl_dsp;$ unsigned int ucb$l_pi_tgt_c710d;$ unsigned int ucb$l_pi_ini_c710d;& unsigned int ucb$l_pi_curr_script; unsigned int ucb$l_pi_dsa; unsigned int ucb$l_pi_dsps;" unsigned int ucb$l_pi_scratch;" unsigned int ucb$l_pi_exp_int; __union { __struct {) unsigned ucb$v_pi_enable : 1;+ unsigned ucb$v_pi_fkb_busy : 1;+ unsigned ucb$v_pi_tqe_busy : 1;( unsigned ucb$v_fill_ W36_ : 5;" } ucb$r_pi_flags_bits;% unsigned char ucb$b_pi_flags;! } ucb$r_pi_flags_overlay; char ucb$b_fill_37_ [3]; } PI_UCB; #if !defined(__VAXC)0#define ucb$q_pi_tfq ucb$r_fill_28_.ucb$q_pi_tfqK#define ucb$l_pi_tfq_flink ucb$r_fill_28_.ucb$r_fill_29_.ucb$l_pi_tfq_flinkK#define ucb$l_pi_tfq_blink ucb$r_fill_28_.ucb$r_fill_29_.ucb$l_pi_tfq_blink.#define ucb$q_pi_tq ucb$r_fill_30_.ucb$q_pi_tqI#define ucb$l_pi_tq_flink ucb$r_fill_30_.ucb$r_fill_31_.uc Wb$l_pi_tq_flinkI#define ucb$l_pi_tq_blink ucb$r_fill_30_.ucb$r_fill_31_.ucb$l_pi_tq_blink0#define ucb$q_pi_ifq ucb$r_fill_32_.ucb$q_pi_ifqK#define ucb$l_pi_ifq_flink ucb$r_fill_32_.ucb$r_fill_33_.ucb$l_pi_ifq_flinkK#define ucb$l_pi_ifq_blink ucb$r_fill_32_.ucb$r_fill_33_.ucb$l_pi_ifq_blink.#define ucb$q_pi_iq ucb$r_fill_34_.ucb$q_pi_iqI#define ucb$l_pi_iq_flink ucb$r_fill_34_.ucb$r_fill_35_.ucb$l_pi_iq_flinkI#define ucb$l_pi_iq_blink ucb$r_fill_34_.ucb$r_fill_35_.ucb$l_pi_iq_blinkR#defin We ucb$v_pi_enable ucb$r_pi_flags_overlay.ucb$r_pi_flags_bits.ucb$v_pi_enableV#define ucb$v_pi_fkb_busy ucb$r_pi_flags_overlay.ucb$r_pi_flags_bits.ucb$v_pi_fkb_busyV#define ucb$v_pi_tqe_busy ucb$r_pi_flags_overlay.ucb$r_pi_flags_bits.ucb$v_pi_tqe_busy<#define ucb$b_pi_flags ucb$r_pi_flags_overlay.ucb$b_pi_flags"#endif /* #if !defined(__VAXC) */ #define UCB$C_PILENGTH 1376N#define UCB$C_PI_LENGTH 1376 /* For SDA FORMAT */W#define UCB$S_PIUCBDEF 1376 W/* Old PIUCBDEF size name for compatibility */ 8 #define ucb$r_pi_ucb ucb$r_paucb.ucb$r_erlucb.ucb$r_ucb. #define ucb$r_pi_erl ucb$r_paucb.ucb$r_erlucb! #define ucb$r_pi_pa ucb$r_paucb d#include /* Define the SHM_ID type; SHM_REG contains embedded SHM_ID types */#define UCB$M_PB_OPEN 0x1#define UCB$M_PB_OPENING 0x2#define UCB$M_PB_NIP 0x4#define UCB$M_PB_START 0x8#define UCB$M_PB_ABORTED 0x1#define UCB$M_PB_TERMINATED 0x2#define UCB$M_PB_RWF 0x4#dWefine UCB$M_PB_IWF 0x8#define UCB$M_PB_SMSD 0x10N#define UCB$K_A_END 0 /* A_end node index */N#define UCB$K_B_END 1 /* B_end node index */#define UCB$C_PB_LENGTH 1668  9#ifdef __cplusplus /* Define structure prototypes */ struct _idb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword W#else#pragma __nomember_alignment#endiftypedef struct _pb_ucb {N/* */N/* Skip the common UCB plus the PA extension */N/* */#pragma __nomember_alignment PI_UCB ucb$r_piucb;N/* */N/* Define private PB fields; W */N/* */N/* */N/* The following fields are only associated with the Admin Units. */N/* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __no Wmember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */% struct _cbb *ucb$pq_pb_gnode_cbb;#else& unsigned __int64 ucb$pq_pb_gnode_cbb;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */ W#endifN void *ucb$ps_pb_gnode_ucb_list; /* */N struct _ucb *ucb$ps_pb_template_ucb; /* pointer to the template UCB */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN SHM_ID ucb$r_pb_smci_section_id; /* SMCI Section region id */#pragma __nomember_alignment! unsigned int ucb$l_pb_status; W struct _tqe *ucb$ps_pb_tqe; struct _idb *ucb$ps_pb_idb;% struct _ucb *ucb$ps_pb_admin_ucb;) struct _tqe *ucb$ps_pb_discovery_tqe;' unsigned int ucb$l_pb_remote_gnode;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif* unsigned __int64 ucb$q_pb_incarnation;#pragma __nomember_alignment __union {N unsigned int ucb$l_pb_chan Wsts; /* channel status longword */ __struct { __union {N unsigned short int ucb$w_pb_chansts; /* channel status word */ __struct {N unsigned ucb$v_pb_open : 1; /* channel local end open */R unsigned ucb$v_pb_opening : 1; /* ready to go to open state */N unsigned ucb$v_pb_nip : 1; /* negotiations in progress */N unsigned ucb$v_pb_start : 1; /* starting W, negotiations */0 unsigned ucb$v_fill_38_ : 4;* } ucb$r_chan_sts_bits;" } ucb$r_sts_flags; __union {T unsigned short int ucb$w_pb_chanerr; /* channel status error word */ __struct {N unsigned ucb$v_pb_aborted : 1; /* we were told to die */N unsigned ucb$v_pb_terminated : 1; /* we kill ourselves */N unsigned ucb$v_pb_rwf : 1; /* remque W workq failure */N unsigned ucb$v_pb_iwf : 1; /* insque workq failure */N unsigned ucb$v_pb_smsd : 1; /* sh. mem. shutting down */0 unsigned ucb$v_fill_39_ : 3;* } ucb$r_chan_err_bits;" } ucb$r_err_flags;" } ucb$r_chan_sts_word; } ucb$r_chan_sts;N unsigned int ucb$l_pb_lnode_idx; /* local end index A or B */J unsigned int ucb$l_pb_rnode_idx; /* remot We end index A or B */N void *ucb$ps_pb_fkb; /* Pointer interrupt fork block */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_pb_nb; W /* negotiation section pointer */#else unsigned __int64 ucb$pq_pb_nb;#endif#pragma __nomember_alignment int ucb$l_pb_nb_len;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *ucb$ps_pb_smh; /* channel handle pointer */N void *ucb$ps_pb_smh_self; /* channel handle pointer self */N un Wsigned int ucb$l_pb_gnode [2]; /* gNode number A,B */N unsigned int ucb$l_pb_node_block [2]; /* gNode number A,B */N unsigned int ucb$l_pb_workq [4]; /* Other end work queue pointer */N unsigned int ucb$l_pb_freeq; /* Local-end Harter free head */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN W SHM_ID ucb$r_pb_reg_id; /* Channel region id */#pragma __nomember_alignmentN unsigned int ucb$l_pb_msg_nworkq; /* Number of work queues */N unsigned int ucb$l_pb_msg_buffers; /* Number of buffers */N unsigned int ucb$l_pb_msg_dg_size; /* buffer size */N unsigned int ucb$l_pb_msg_scshdr_size; /* scs/ppd header */N unsigned int ucb$l_pb_msg_smwe_size; /* SMWE header */ WN unsigned int ucb$l_pb_msg_smch_size; /* SMCH header */N unsigned int ucb$l_pb_msg_smnd_size; /* SMND header */N unsigned int ucb$l_pb_msg_netsize; /* decnet header size */O unsigned int ucb$l_pb_channel_add; /* number of channels for expansions */ unsigned int ucb$l_dbg [30]; char ucb$b_fill_40_ [4]; } PB_UCB; #if !defined(__VAXC)8#define ucb$l_pb_chansts ucb$r_chan_sts.ucb$l_pb_chansts\#define ucb$w_pb_cWhansts ucb$r_chan_sts.ucb$r_chan_sts_word.ucb$r_sts_flags.ucb$w_pb_chanstsj#define ucb$v_pb_open ucb$r_chan_sts.ucb$r_chan_sts_word.ucb$r_sts_flags.ucb$r_chan_sts_bits.ucb$v_pb_openp#define ucb$v_pb_opening ucb$r_chan_sts.ucb$r_chan_sts_word.ucb$r_sts_flags.ucb$r_chan_sts_bits.ucb$v_pb_openingh#define ucb$v_pb_nip ucb$r_chan_sts.ucb$r_chan_sts_word.ucb$r_sts_flags.ucb$r_chan_sts_bits.ucb$v_pb_nipl#define ucb$v_pb_start ucb$r_chan_sts.ucb$r_chan_sts_word.ucb$r_sts_flags.ucb$r_chan_sts_bits.ucb$v_pbW_start\#define ucb$w_pb_chanerr ucb$r_chan_sts.ucb$r_chan_sts_word.ucb$r_err_flags.ucb$w_pb_chanerrp#define ucb$v_pb_aborted ucb$r_chan_sts.ucb$r_chan_sts_word.ucb$r_err_flags.ucb$r_chan_err_bits.ucb$v_pb_abortedv#define ucb$v_pb_terminated ucb$r_chan_sts.ucb$r_chan_sts_word.ucb$r_err_flags.ucb$r_chan_err_bits.ucb$v_pb_terminatedh#define ucb$v_pb_rwf ucb$r_chan_sts.ucb$r_chan_sts_word.ucb$r_err_flags.ucb$r_chan_err_bits.ucb$v_pb_rwfh#define ucb$v_pb_iwf ucb$r_chan_sts.ucb$r_chan_sts_word.ucb$r_er Wr_flags.ucb$r_chan_err_bits.ucb$v_pb_iwfj#define ucb$v_pb_smsd ucb$r_chan_sts.ucb$r_chan_sts_word.ucb$r_err_flags.ucb$r_chan_err_bits.ucb$v_pb_smsd"#endif /* #if !defined(__VAXC) */ N/* */N/* SNAPSHOT SERVICES (aka SnappyDisk) UCB EXTENSION */N/* */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If us Wing pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _sd_ucb {#pragma __nomember_alignment DT_UCB ucb$r_dtucb; N unsigned __int64 ucb$q_sd_export_queue; /* Device queue link */N void *ucb$ps_sd_sdcb; /* snappy disk control block */N void *ucb$ps_sd_pool_config; /* Pointer to POOL_CONFIG lock */N unsigned int ucb$l_sd_family_number; /* Family number W */N unsigned int ucb$l_sd_snap_number; /* Snap number */N unsigned int ucb$l_sd_dev_lockid; /* Device Lock Id */N unsigned int ucb$l_sd_uid_lockid; /* UID Lock Id */N unsigned int ucb$l_sd_spare1; /* Spare field */N unsigned int ucb$l_sd_spare2; /* Spare field */N unsigned int ucb$l_sd_spare3; /* Spare field */N unsi Wgned int ucb$l_sd_spare4; /* Spare field */ } SD_UCB;N#define UCB$C_SD_LENGTH 624 /* For SDA FORMAT */#define UCB$S_SDUCBDEF 624 #define ucb$ps_sdmb ucb$l_dccb N/* */I/* SCSI/FibreChannel Disk Class Driver UCB Extension */N/* */ #include #define WUCB$M_REMOVABLE 0x1!#define UCB$M_FIRST_ATTN_SEEN 0x2#define UCB$M_SPINUP_INPROG 0x4#define UCB$M_DISCONNECT 0x8#define UCB$M_SYNCHRONOUS 0x10"#define UCB$M_MODE_SENSE_PAG1 0x20##define UCB$M_MODE_SENSE_PAG10 0x40 #define UCB$M_DISABL_ERRLOG 0x80#define UCB$M_OUT_OF_REV 0x100#define UCB$M_HWL 0x200#define UCB$M_FLOPPY 0x400#define UCB$M_FORMAT 0x800#define UCB$M_NOREASSIGN 0x1000#define UCB$M_DD_BYPASS 0x2000#define UCB$M_HBS_CHECK 0x4000"#define UCB$M_FLOPPY_MEDIA 0x180W00#define UCB$M_CDROM 0x20000#define UCB$M_CD_VALID 0x40000#define UCB$M_RAID 0x80000 #define UCB$M_PORT_CMDQ 0x100000#define UCB$M_CMDQ 0x200000#define UCB$M_OPTICAL 0x400000#define UCB$M_WORM 0x800000#define UCB$M_DDR 0x1000000 #define UCB$M_PORT_AEN 0x2000000&#define UCB$M_PORT_AUTOSENSE 0x4000000#define UCB$M_TENBYTE 0x8000000#define UCB$M_CLUSQ 0x10000000 #define UCB$M_HFAILOV 0x20000000#define UCB$M_NO_FUA 0x40000000%#define UCB$M_NO_10BYTE_RW 0x80000000#define WUCB$M_CB_NOCMDQ 0x1#define UCB$M_CB_INIT 0x2 #define UCB$M_CB_BBR_IN_PROG 0x4#define UCB$M_CB_MNTVERIP 0x8 #define UCB$M_CB_KP_STARTIO 0x10%#define UCB$M_CB_CHECK_CONDITION 0x20%#define UCB$M_CB_QUEUE_FULL_EVNT 0x40#define UCB$M_CB_BUS_RESET 0x80&#define UCB$M_CB_NO_SEND_CREDITS 0x100"#define UCB$M_CB_NO_CMD_BITS 0x200 #define UCB$M_CB_SINGLE_RW 0x400 #define UCB$M_CB_SINGLE_DC 0x800"#define UCB$M_CB_SINGLE_DSE 0x1000##define UCB$M_CB_FORCE_ERROR 0x2000#define UCB$M_CB_NOP 0x4W000!#define UCB$M_CB_AVAILABLE 0x8000#define UCB$M_CB_UNLOAD 0x10000 #define UCB$M_CB_PACKACK 0x20000!#define UCB$M_CB_DIAGNOSE 0x40000#define UCB$M_CB_FORMAT 0x80000#define UCB$M_CB_AUDIO 0x100000#define UCB$M_CB_BUSY 0x200000%#define UCB$M_CB_LOCAL_DRAIN 0x400000#define UCB$M_CB_LINK 0x800000&#define UCB$M_CB_PATH_VERIFY 0x1000000)#define UCB$K_DK_NUM_LONGWORDS_DIAGNOSE 6#define UCB$M_DTESET 0x1#define UCB$M_XPLOOK 0x2#define UCB$M_MULTIBUS_CAP 0x4#define UCB$M_MULTIBWUS_ENA 0x8!#define UCB$M_SECTORS_VIA_MS 0x10!#define UCB$M_TRK_CYL_VIA_MS 0x20#define UCB$M_PR_PREEMPT 0x80#define UCB$M_NOTREADY 0x100##define UCB$M_CD_2K_BLOCKSIZE 0x200##define UCB$M_VIRTUAL_MACHINE 0x400#define UCB$M_DK_FIBRE 0x1#define UCB$M_DK_HSG 0x2#define UCB$M_DK_HSV 0x4#define UCB$M_DK_XP 0x8'#define UCB$M_DK_ASYM_ACC_STATE 0xF0000'#define UCB$M_DK_TPG_NUM_VALID 0x100000&#define UCB$M_DK_RPT_TPG_SUPP 0x200000&#define UCB$M_DK_SET_TPG_SUPP 0x400000#define UCB$M_WDK_SAS 0x1#define UCB$M_DK_SAS_DEV 0x2!#define UCB$M_DK_SAS_SATA_DEV 0x4#define UCB$M_DK_SAS_IR_VOL 0x8"#define UCB$M_DK_SAS_RAID_VOL 0x10!#define UCB$C_DK_SPARE_COUNTERS 3#define UCB$C_DK_UCBLEN 1568N#define UCB$C_DK_LENGTH 1568 /* (For SDA) */  9#ifdef __cplusplus /* Define structure prototypes */struct _scdrp; struct _kpb; struct _scdt; struct _irp;struct _dklog_header; struct _spl; struct _iobd; struct _ext; #endif /* #ifdeWf __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _dk_ucb {#pragma __nomember_alignment MSCP_UCB ucb$r_mscpucb; __union {$ unsigned int ucb$l_dk_flags; __struct {N unsigned ucb$v_removable : 1; /* Media is removeable */h unsigned ucb$v_first_attn_seen : 1; /* FWirst UNIT ATTENTION CHECK CONDITION has been seen */N unsigned ucb$v_spinup_inprog : 1; /* Disk is spinning up if set */X unsigned ucb$v_disconnect : 1; /* Device supports (bus-level) disconnects */\ unsigned ucb$v_synchronous : 1; /* Device supports synchronous data transfers */N unsigned ucb$v_mode_sense_pag1 : 1; /* */N unsigned ucb$v_mode_sense_pag10 : 1; /* */N unsigned ucb$v_dWisabl_errlog : 1; /* */N unsigned ucb$v_out_of_rev : 1; /* */N unsigned ucb$v_hwl : 1; /* Hardware Write Locked */N unsigned ucb$v_floppy : 1; /* This is a floppy disk */N unsigned ucb$v_format : 1; /* */N unsigned ucb$v_noreassign : 1; /* */N unsigned ucb$v_dd_bypass : 1; /* W */N unsigned ucb$v_hbs_check : 1; /* */N unsigned ucb$v_floppy_media : 2; /* */N unsigned ucb$v_cdrom : 1; /* */N unsigned ucb$v_cd_valid : 1; /* */N unsigned ucb$v_raid : 1; /* */N unsigned ucb$v_port_cmdq : 1; /* */PW unsigned ucb$v_cmdq : 1; /* Disk supports SCSI Command Queuing */N unsigned ucb$v_optical : 1; /* Optical disk */N unsigned ucb$v_worm : 1; /* Write-Once, Read-Many */N unsigned ucb$v_ddr : 1; /* */g unsigned ucb$v_port_aen : 1; /* Underlying port supports Asynchronous Event Notification */i unsigned ucb$v_port_autosense : 1; /* Underlying port performs REQWUEST SENSE automatically */N unsigned ucb$v_tenbyte : 1; /* */N unsigned ucb$v_clusq : 1; /* */N unsigned ucb$v_hfailov : 1; /* */N unsigned ucb$v_no_fua : 1; /* Forced Unit Access not supported */b unsigned ucb$v_no_10byte_rw : 1; /* Device does not support 10-byte Reads or Writes */ } ucb$r_fill_42_; } ucb$r_fill_41_ W; __union {g unsigned int ucb$l_dk_class_busy; /* Class Busy bits show details about why UCB$V_BSY is set */ __struct {N unsigned ucb$v_cb_nocmdq : 1; /* */N unsigned ucb$v_cb_init : 1; /* */N unsigned ucb$v_cb_bbr_in_prog : 1; /* */N unsigned ucb$v_cb_mntverip : 1; /* */N unsigned ucb$v_cb_kp_startWio : 1; /* */N unsigned ucb$v_cb_check_condition : 1; /* */N unsigned ucb$v_cb_queue_full_evnt : 1; /* */N unsigned ucb$v_cb_bus_reset : 1; /* */N unsigned ucb$v_cb_no_send_credits : 1; /* */N unsigned ucb$v_cb_no_cmd_bits : 1; /* */N unsigned ucb$v_cb_single_rw : 1; /* W */N unsigned ucb$v_cb_single_dc : 1; /* */N unsigned ucb$v_cb_single_dse : 1; /* */N unsigned ucb$v_cb_force_error : 1; /* */N unsigned ucb$v_cb_nop : 1; /* */N unsigned ucb$v_cb_available : 1; /* */N unsigned ucb$v_cb_unload : 1; /* */N W unsigned ucb$v_cb_packack : 1; /* */N unsigned ucb$v_cb_diagnose : 1; /* */N unsigned ucb$v_cb_format : 1; /* */N unsigned ucb$v_cb_audio : 1; /* */N unsigned ucb$v_cb_busy : 1; /* */N unsigned ucb$v_cb_local_drain : 1; /* */N unsigned ucb$v_cb_link : W 1; /* */N unsigned ucb$v_cb_path_verify : 1; /* */( unsigned ucb$v_fill_53_ : 7; } ucb$r_fill_44_; } ucb$r_fill_43_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN __union { /* NormalPath Active-IRP list */#pragma __ Wnomember_alignmentN unsigned __int64 ucb$q_dk_irp_list; /* */N __struct { /* */N void *ucb$ps_dk_active_irp_qfl; /* */N void *ucb$ps_dk_active_irp_qbl; /* */( } ucb$r_dk_active_irp_queue;N/* */" } ucb$r_dk_irp_list_union;N/* W */N void *ucb$l_dk_flush_ioqfl; /* */N void *ucb$l_dk_flush_ioqbl; /* */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endifN __union { /* DataCheck Wait Queue */#pra Wgma __nomember_alignmentN unsigned __int64 ucb$q_dk_dc_wait_list; /* */N __struct { /* */N void *ucb$ps_dk_dc_wait_qfl; /* */N void *ucb$ps_dk_dc_wait_qbl; /* */% } ucb$r_dk_dc_wait_queue;N/* */! } ucb$r_dk_dc_wait_union;N/* W */k __union { /* Queue of SCDRPs waiting for all I/O in front of them to drain */N unsigned __int64 ucb$q_dk_drain_list; /* */N __struct { /* */N void *ucb$ps_dk_drain_qfl; /* */N void *ucb$ps_dk_drain_qbl; /* */#W } ucb$r_dk_drain_queue;N/* */ } ucb$r_dk_drain_union;N/* */Q int ucb$is_dk_drain_count; /* Number of SCDRPs on the Drain Queue */S int ucb$l_dk_queued_io_count; /* Number of IRPs on the Active IRP list */N struct _scdrp *ucb$ps_dk_scdrp; /* */N struct _kpb *ucb$ps_ Wdk_unitinit_kpb; /* */V struct _scdt *ucb$ps_dk_scdt; /* SCSI Connection Descriptor Table address */ char ucb$b_fill_54_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignmentN unsigned __int64 ucb$q_dk_cur_lbn_64; /* Current LBN (64-bit) */N unsignedW int ucb$l_dk_cur_lbn; /* (32-bit) */# } ucb$r_dk_cur_lbn_overlay;N int ucb$l_dk_fairness_cnt; /* */N unsigned int ucb$l_dk_hw_rev; /* */N unsigned int ucb$l_dk_error_type; /* */N unsigned int ucb$l_dk_err_mask; /* */N unsigned int ucb$l_dk_vms_status; /* */& Wunsigned int ucb$l_dk_disable_ddr;N unsigned int ucb$l_dk_initmo; /* */N void *ucb$ps_dk_aucb_addr; /* */N void *ucb$ps_dk_format_param; /* */N void *ucb$ps_dk_save_conn_char; /* */' unsigned int ucb$r_dk_diagnose [6];N short int ucb$w_dk_readl_len; /* */N short int ucb$w_dk_phaseW_tmo; /* Phase-Change Timeout in seconds */N short int ucb$w_dk_disc_tmo; /* Disconnect Timeout in seconds */N short int ucb$w_dk_block_size; /* Block size in bytes */N char ucb$b_dk_lun; /* Logical Unit Number */N char ucb$b_dk_seek_dir; /* */N char ucb$b_dk_scsi_version; /* */N char ucb$b_dk_rw_retry; /* W */N char ucb$b_dk_reassign_retry; /* */N char ucb$b_dk_rewrite_retry; /* */N char ucb$b_dk_ready_retry; /* */N/* For CD-ROMS, Sub-Channel Q - Media Catalog Data (UPC) */" char ucb$b_dk_mcn_scdata [32]; char ucb$b_fill_55_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ *W/'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif" char ucb$r_dk_sense_info [10];#pragma __nomember_alignment char ucb$b_dk_sense_len [2];N/* Error Recovery parameters */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endif! char ucb$r_dk_recov_par [16];N/* Error W Recovery changeable parameters */" char ucb$r_dk_recov_cpar [16];N/* Control Mode parameters */ char ucb$r_dk_ctrl_mode [8];N/* Control Mode changeable parameters */% char ucb$r_dk_ctrl_mode_cpar [8]; #pragma __nomember_alignmentf int ucb$l_dk_qdepth; /* Current maximum queue depth for this device (NormalPath) */Y int ucb$l_dk_qdepth_tuWrns; /* How many times queue depth has been changed */N int ucb$l_dk_read_count; /* Number of NormalPath reads done */N int ucb$l_dk_write_count; /* Number of NormalPath writes done */Z int ucb$l_dk_other_count; /* Number of non-Read & non-Write I/O functions */S int ucb$l_dk_fp_rw_count; /* Number of FastPath I/Os (R/W implied) */e int ucb$l_dk_fp_err_count; /* Number of other-than SS$_CLASSUPER FastPath completions */WN int ucb$l_dk_read_xlen_hist; /* Pointer to Read histogram pool */N int ucb$l_dk_write_xlen_hist; /* Pointer to Write histogram pool */N int ucb$l_dk_xlen_hist; /* Pointer to total histogram pool */N int ucb$l_dk_xlen_hist_cycle; /* # I/Os per histogram turnover */Q struct _irp *ucb$ps_dk_busy_bit_irp; /* Also referred to as the Golden IRP */Z struct _dklog_header *ucb$l_dk_top_of_ring; /* Pointer to first byte of ring buffer */X struWct _dklog_header *ucb$l_dk_ring_pointer; /* Pointer to next ring buffer entry */l int ucb$l_dk_ring_counter; /* Number of ring buffer entries left before wrapping is required */j/* These fields count reasons for our returning SS$_MEDOFL to help us diagnose excessive Mount Verifies */N int ucb$l_dk_timeout; /* I/O Timed Out */N int ucb$l_dk_drverr; /* SS$_DRVERR returned from port */N int ucb$l_dk_ctrlerr; /* SS$W_CTRLERR ... */N int ucb$l_dk_devoffline; /* SS$_DEVOFFLINE ... */N int ucb$l_dk_unit_attention; /* Unit Attention CHECK CONDITION */N int ucb$l_dk_vendor_specific; /* */N int ucb$l_dk_copy_aborted; /* */N int ucb$l_dk_not_ready; /* */N int ucb$l_dk_reserved; /* W */N int ucb$l_dk_medofl; /* */N int ucb$l_dk_unexplained; /* */" int ucb$l_dk_inquiry_data [9];N/* Overflow from DK_FLAGS */ __union {% unsigned int ucb$l_dk_flags2; __struct {N unsigned ucb$v_dteset : 1; /* */N unsigned ucb$v_xplook : 1; /* W */N unsigned ucb$v_multibus_cap : 1; /* */N unsigned ucb$v_multibus_ena : 1; /* */N unsigned ucb$v_sectors_via_ms : 1; /* */N unsigned ucb$v_trk_cyl_via_ms : 1; /* */N unsigned ucb$v_not_used : 1; /* nothing uses this */^ unsigned ucb$v_pr_preempt : 1; /* Persistent Reservation Preemption in Progres Ws */R unsigned ucb$v_notready : 1; /* Last command returned NOT_READY key */P unsigned ucb$v_cd_2k_blocksize : 1; /* CD/DVD using 2K block mode */b unsigned ucb$v_virtual_machine : 1; /* X-128 Driver is running on a virtual machine */( unsigned ucb$v_fill_56_ : 5; } ucb$r_fill_46_; } ucb$r_fill_45_;N/* SCSIPATH structure */ char ucb$b_fill_57_ [4];c#if !defined(__NOBASEA WLIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif! char ucb$r_dk_path_info [24];N/* Obsolete (X-116) */#pragma __nomember_alignmentN char ucb$r_dk_old_dsplypath_id [28]; /* Obsolete (X-116) */N int ucb$l_dk_get_path_info_retries; /* */N/* FastPath Attention flag - set W by NormalPath code (while holding */N/* the portlock) to get the FastPath code's attention */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif& unsigned __int64 ucb$q_dk_fp_attn;N/* FibreChannel-disk boolean */ __union {#pragma __nomember_alignment( unsigned __int W64 ucb$q_dk_fibre; __struct {( unsigned ucb$v_dk_fibre : 1;& unsigned ucb$v_dk_hsg : 1;& unsigned ucb$v_dk_hsv : 1;% unsigned ucb$v_dk_xp : 1;( unsigned ucb$v_fill_58_ : 4; } ucb$r_fill_48_; } ucb$r_fill_47_;N/* Queue of active FastPath IRPs, synchronized with port spinlock */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember W_alignment __quadword#else#pragma __nomember_alignment#endifN __union { /* */#pragma __nomember_alignmentN unsigned __int64 ucb$q_dk_fp_irp_list; /* */N __struct { /* */N void *ucb$ps_dk_fp_irp_qfl; /* */N void *ucb$ps_dk_fp_irp_qbl; /* */$ W } ucb$r_dk_fp_irp_queue;N/* */% } ucb$r_dk_fp_irp_list_union;N/* */N/* Count of active FastPath IRPs, synchronized with port spinlock */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN Wunsigned __int64 ucb$q_dk_fp_irp_count; /* */t/* FastPath Start I/O flag, synchronized with fork spinlock, used to avoid excesssive stack depth and avoid FORKs */* unsigned __int64 ucb$q_dk_fp_start_io;b/* UCB$L_DISC_TMO + UCB$L_PHASE_TMO summed in this field to avoid unnecessary per-I/O operation */#pragma __nomember_alignment$ struct _spl *ucb$ps_dk_spl_fork;% unsigned int ucb$l_dk_fp_timeout;$ struct _spl *ucb$ps_dk_spl_port;N unsigned int ucb$l W_dk_log_flag; /* Logging flags/controls */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_dk_datacheck_spte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#e Wlse/ unsigned __int64 ucb$pq_dk_datacheck_spte_sva;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_dk_datacheck_sva; /* and her address */#else* unsigned __int64 ucb$pq_dk_datacheck_sva;#endifV int ucb$l_dk_irp_wait_4_kpb; /* If nonzero, IRP in "fork wait" for a KPB */R#ifdef _W_INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifd void *ucb$ps_dk_qdepth_table; /* Pointer to optional Size vs. Maximum queue depth table */N struct _irp *ucb$ps_dk_quorum_irp; /* Pointer to pending Quorum IRP */ char ucb$b_fill_59_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nome Wmber_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_dk_buffio_spte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else, unsigned __int64 ucb$pq_dk_buffio_spte_sva;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z X#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_dk_buffio_sva; /* Pointer to temp DMA Buffer */#else' unsigned __int64 ucb$pq_dk_buffio_sva;#endif __union {V unsigned int ucb$l_dk_tpg_info; /* Target port group info for Active-Active */ __struct {N short int ucb$w_dk_tpg_num; /* Target port group number */O unsigned ucb$v_dk_asym_acc_state : 4; /* Asymmetric access X state */N unsigned ucb$v_dk_tpg_num_valid : 1; /* TPG num is valid */V unsigned ucb$v_dk_rpt_tpg_supp : 1; /* RPT TARG PORT GRPS cmd supported */W unsigned ucb$v_dk_set_tpg_supp : 1; /* SET TARG PORT GRPS cmd supported */( unsigned ucb$v_fill_60_ : 1; } ucb$r_fill_50_; } ucb$r_fill_49_;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And s Xet ptr size default to 32-bit pointers */#endifN struct _dklog_header *ucb$l_dk_ua_ring_pointer; /* Used by SDA's MKLOG */N/* Display path size for DK, MK, and GK devices (X-116) */N char ucb$r_dk_dsplypath_id [292]; /* Moved here in X-116 */N/* SAS device boolean */ char ucb$b_fill_61_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pXragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {#pragma __nomember_alignment& unsigned __int64 ucb$q_dk_sas; __struct {& unsigned ucb$v_dk_sas : 1;* unsigned ucb$v_dk_sas_dev : 1;/ unsigned ucb$v_dk_sas_sata_dev : 1;- unsigned ucb$v_dk_sas_ir_vol : 1;/ unsigned ucb$v_dk_sas_raid_vol : 1;( unsigned ucb$v_fill_62_ : 3; } ucb$r_fill_52_; X } ucb$r_fill_51_;N/* NOSVAPTE_DEVEL Counters for IOBD path development, and a few spares */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif1 unsigned __int64 ucb$q_dk_extent_list_checks;#pragma __nomember_alignment+ unsigned __int64 ucb$q_dk_extent_lists;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#p Xragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */( struct _iobd *ucb$pq_dk_buffio_iobd;#else( unsigned __int64 ucb$pq_dk_buffio_iobd;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */) struct _ext *ucb$pq_dk_buffio_extent;#else* unsigned __int64 ucb$pq_dk_buffio_extent;#endifR#ifdef __INITIAL_POINTER_SIZE /* XDefined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */$ struct _iobd *ucb$pq_dk_dc_iobd;#else$ unsigned __int64 ucb$pq_dk_dc_iobd;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */% struct _ext *ucb$pq_dk_dc_extent;#else& unsigned __int64 ucb$pq_dk_dc_extent;#endif0 X unsigned __int64 ucb$q_dk_spare_counter [3]; } DK_UCB; #if !defined(__VAXC)4#define ucb$l_dk_flags ucb$r_fill_41_.ucb$l_dk_flagsE#define ucb$v_removable ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_removableQ#define ucb$v_first_attn_seen ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_first_attn_seenM#define ucb$v_spinup_inprog ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_spinup_inprogG#define ucb$v_disconnect ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_disconnectI#define ucb$v_synchronous ucb$r_fill_41_.ucb$r_fill_X42_.ucb$v_synchronousQ#define ucb$v_mode_sense_pag1 ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_mode_sense_pag1S#define ucb$v_mode_sense_pag10 ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_mode_sense_pag10M#define ucb$v_disabl_errlog ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_disabl_errlogG#define ucb$v_out_of_rev ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_out_of_rev9#define ucb$v_hwl ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_hwl?#define ucb$v_floppy ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_floppy?#define ucb$v_format ucb$r_fill_ X41_.ucb$r_fill_42_.ucb$v_formatG#define ucb$v_noreassign ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_noreassignE#define ucb$v_dd_bypass ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_dd_bypassE#define ucb$v_hbs_check ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_hbs_checkK#define ucb$v_floppy_media ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_floppy_media=#define ucb$v_cdrom ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_cdromC#define ucb$v_cd_valid ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_cd_valid;#define ucb$v_raid ucb$r_fill_41_.ucb$r_fi Xll_42_.ucb$v_raidE#define ucb$v_port_cmdq ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_port_cmdq;#define ucb$v_cmdq ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_cmdqA#define ucb$v_optical ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_optical;#define ucb$v_worm ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_worm9#define ucb$v_ddr ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_ddrC#define ucb$v_port_aen ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_port_aenO#define ucb$v_port_autosense ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_port_autosenseA#define uc Xb$v_tenbyte ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_tenbyte=#define ucb$v_clusq ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_clusqA#define ucb$v_hfailov ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_hfailov?#define ucb$v_no_fua ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_no_fuaK#define ucb$v_no_10byte_rw ucb$r_fill_41_.ucb$r_fill_42_.ucb$v_no_10byte_rw>#define ucb$l_dk_class_busy ucb$r_fill_43_.ucb$l_dk_class_busyE#define ucb$v_cb_nocmdq ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_nocmdqA#define ucb$v_cb_init ucb$r_fill_43_ X.ucb$r_fill_44_.ucb$v_cb_initO#define ucb$v_cb_bbr_in_prog ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_bbr_in_progI#define ucb$v_cb_mntverip ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_mntveripM#define ucb$v_cb_kp_startio ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_kp_startioW#define ucb$v_cb_check_condition ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_check_conditionW#define ucb$v_cb_queue_full_evnt ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_queue_full_evntK#define ucb$v_cb_bus_reset ucb$r_fill_43_.ucb$r_fill_44_ X.ucb$v_cb_bus_resetW#define ucb$v_cb_no_send_credits ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_no_send_creditsO#define ucb$v_cb_no_cmd_bits ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_no_cmd_bitsK#define ucb$v_cb_single_rw ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_single_rwK#define ucb$v_cb_single_dc ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_single_dcM#define ucb$v_cb_single_dse ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_single_dseO#define ucb$v_cb_force_error ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_force_erXror?#define ucb$v_cb_nop ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_nopK#define ucb$v_cb_available ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_availableE#define ucb$v_cb_unload ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_unloadG#define ucb$v_cb_packack ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_packackI#define ucb$v_cb_diagnose ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_diagnoseE#define ucb$v_cb_format ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_formatC#define ucb$v_cb_audio ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_XaudioA#define ucb$v_cb_busy ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_busyO#define ucb$v_cb_local_drain ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_local_drainA#define ucb$v_cb_link ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_linkO#define ucb$v_cb_path_verify ucb$r_fill_43_.ucb$r_fill_44_.ucb$v_cb_path_verifyC#define ucb$q_dk_irp_list ucb$r_dk_irp_list_union.ucb$q_dk_irp_listS#define ucb$r_dk_active_irp_queue ucb$r_dk_irp_list_union.ucb$r_dk_active_irp_queueS#define ucb$ps_dk_active_irp_qfl ucb$r_dk_Xactive_irp_queue.ucb$ps_dk_active_irp_qflS#define ucb$ps_dk_active_irp_qbl ucb$r_dk_active_irp_queue.ucb$ps_dk_active_irp_qblJ#define ucb$q_dk_dc_wait_list ucb$r_dk_dc_wait_union.ucb$q_dk_dc_wait_listL#define ucb$r_dk_dc_wait_queue ucb$r_dk_dc_wait_union.ucb$r_dk_dc_wait_queueJ#define ucb$ps_dk_dc_wait_qfl ucb$r_dk_dc_wait_queue.ucb$ps_dk_dc_wait_qflJ#define ucb$ps_dk_dc_wait_qbl ucb$r_dk_dc_wait_queue.ucb$ps_dk_dc_wait_qblD#define ucb$q_dk_drain_list ucb$r_dk_drain_union.ucb$q_dk_drain_listFX#define ucb$r_dk_drain_queue ucb$r_dk_drain_union.ucb$r_dk_drain_queueD#define ucb$ps_dk_drain_qfl ucb$r_dk_drain_queue.ucb$ps_dk_drain_qflD#define ucb$ps_dk_drain_qbl ucb$r_dk_drain_queue.ucb$ps_dk_drain_qblH#define ucb$q_dk_cur_lbn_64 ucb$r_dk_cur_lbn_overlay.ucb$q_dk_cur_lbn_64B#define ucb$l_dk_cur_lbn ucb$r_dk_cur_lbn_overlay.ucb$l_dk_cur_lbn6#define ucb$l_dk_flags2 ucb$r_fill_45_.ucb$l_dk_flags2?#define ucb$v_dteset ucb$r_fill_45_.ucb$r_fill_46_.ucb$v_dteset?#define ucb$v_xplook ucb$r_filXl_45_.ucb$r_fill_46_.ucb$v_xplookK#define ucb$v_multibus_cap ucb$r_fill_45_.ucb$r_fill_46_.ucb$v_multibus_capK#define ucb$v_multibus_ena ucb$r_fill_45_.ucb$r_fill_46_.ucb$v_multibus_enaO#define ucb$v_sectors_via_ms ucb$r_fill_45_.ucb$r_fill_46_.ucb$v_sectors_via_msO#define ucb$v_trk_cyl_via_ms ucb$r_fill_45_.ucb$r_fill_46_.ucb$v_trk_cyl_via_msG#define ucb$v_pr_preempt ucb$r_fill_45_.ucb$r_fill_46_.ucb$v_pr_preemptC#define ucb$v_notready ucb$r_fill_45_.ucb$r_fill_46_.ucb$v_notreadyQ#definXe ucb$v_cd_2k_blocksize ucb$r_fill_45_.ucb$r_fill_46_.ucb$v_cd_2k_blocksizeQ#define ucb$v_virtual_machine ucb$r_fill_45_.ucb$r_fill_46_.ucb$v_virtual_machine4#define ucb$q_dk_fibre ucb$r_fill_47_.ucb$q_dk_fibreC#define ucb$v_dk_fibre ucb$r_fill_47_.ucb$r_fill_48_.ucb$v_dk_fibre?#define ucb$v_dk_hsg ucb$r_fill_47_.ucb$r_fill_48_.ucb$v_dk_hsg?#define ucb$v_dk_hsv ucb$r_fill_47_.ucb$r_fill_48_.ucb$v_dk_hsv=#define ucb$v_dk_xp ucb$r_fill_47_.ucb$r_fill_48_.ucb$v_dk_xpL#define ucb$q_dk_fp_irp_Xlist ucb$r_dk_fp_irp_list_union.ucb$q_dk_fp_irp_listN#define ucb$r_dk_fp_irp_queue ucb$r_dk_fp_irp_list_union.ucb$r_dk_fp_irp_queueG#define ucb$ps_dk_fp_irp_qfl ucb$r_dk_fp_irp_queue.ucb$ps_dk_fp_irp_qflG#define ucb$ps_dk_fp_irp_qbl ucb$r_dk_fp_irp_queue.ucb$ps_dk_fp_irp_qbl:#define ucb$l_dk_tpg_info ucb$r_fill_49_.ucb$l_dk_tpg_infoG#define ucb$w_dk_tpg_num ucb$r_fill_49_.ucb$r_fill_50_.ucb$w_dk_tpg_numU#define ucb$v_dk_asym_acc_state ucb$r_fill_49_.ucb$r_fill_50_.ucb$v_dk_asym_acc_stateS#dXefine ucb$v_dk_tpg_num_valid ucb$r_fill_49_.ucb$r_fill_50_.ucb$v_dk_tpg_num_validQ#define ucb$v_dk_rpt_tpg_supp ucb$r_fill_49_.ucb$r_fill_50_.ucb$v_dk_rpt_tpg_suppQ#define ucb$v_dk_set_tpg_supp ucb$r_fill_49_.ucb$r_fill_50_.ucb$v_dk_set_tpg_supp0#define ucb$q_dk_sas ucb$r_fill_51_.ucb$q_dk_sas?#define ucb$v_dk_sas ucb$r_fill_51_.ucb$r_fill_52_.ucb$v_dk_sasG#define ucb$v_dk_sas_dev ucb$r_fill_51_.ucb$r_fill_52_.ucb$v_dk_sas_devQ#define ucb$v_dk_sas_sata_dev ucb$r_fill_51_.ucb$r_fill_52_.ucb$ Xv_dk_sas_sata_devM#define ucb$v_dk_sas_ir_vol ucb$r_fill_51_.ucb$r_fill_52_.ucb$v_dk_sas_ir_volQ#define ucb$v_dk_sas_raid_vol ucb$r_fill_51_.ucb$r_fill_52_.ucb$v_dk_sas_raid_vol"#endif /* #if !defined(__VAXC) */ N/* */I/* SCSI Tape Class Driver UCB Extension */N/* */  9#ifdef __cplusplus /* Define struXcture prototypes */struct _dklog_header; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _mk_ucb {#pragma __nomember_alignmentN char ucb$b_mk_lcl_tape [560]; /* Standard tape UCB fields */N int ucb$l_mk_local_fields1 [110]; /* Legacy Mkdriver extensions */N char ucb$r_mXk_old_dsplypath_id [28]; /* Obsolete (X-116) */N int ucb$l_mk_local_fields2 [2]; /* More local Mkdriver extensions */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _dklog_header *ucb$l_mk_ring_pointer; /* Used by SDA's MKLOG */N unsigned int ucb$l_mk_log_flag; /* Used by SDA's MKLOG */N struct _dklo Xg_header *ucb$l_mk_ua_ring_pointer; /* Used by SDA's MKLOG */\ char ucb$r_mk_dsplypath_id [292]; /* Pathname, used by SDA's MKLOG (moved in X-116) */ char ucb$b_fill_63_ [4]; } MK_UCB;N/* */I/* SCSI Generic Class Driver UCB Extension */N/* */  9#ifdef __cplusplus /* Define structure prototypes */ Xstruct _dklog_header; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _gk_ucb {#pragma __nomember_alignmentN MSCP_UCB ucb$r_mscpucb; /* Standard generic SCSI UCB fields */N int ucb$l_gk_local_fields1 [18]; /* Legacy Gkdriver extensions */N char ucb$r_gk_old_dsplypath_id [X28]; /* Obsolete (X-116) */N struct _dklog_header *ucb$l_gk_ring_pointer; /* Used by SDA's GKLOG */N unsigned int ucb$l_gk_log_flag; /* Used by SDA's GKLOG */\ char ucb$r_gk_dsplypath_id [292]; /* Pathname, used by SDA's GKLOG (moved in X-116) */ } GK_UCB;N/* */I/* DECram (MD) Disk Class Driver UCB Extension */N/* X */#define UCB$M_MD_MEMORY 0x1#define UCB$M_MD_UCB_FIP 0x2!#define UCB$M_MD_UPDATINGFILE 0x4#define UCB$M_MD_INTIO 0x8#define UCB$M_MD_DTREGION 0x10!#define UCB$M_MD_DTENTRY_CRE 0x20!#define UCB$M_MD_DTENTRY_MOD 0x40"#define UCB$M_MD_UPDATINGHOME 0x80"#define UCB$M_MD_UPDATINGFMT 0x100#define UCB$M_MD_RSVD1 0x200#define UCB$K_MD_LENGTH 1024#define UCB$C_MD_LENGTH 1024 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* IXf using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _md_ucb {#pragma __nomember_alignment MSCP_UCB ucb$r_mscpucb; __union { __struct {N unsigned ucb$v_md_memory : 1; /* memory region allocated */N unsigned ucb$v_md_ucb_fip : 1; /* io$_format in progress */V unsigned ucb$v_md_updatingfile : 1; /* mdrecover.dat update in progress */N Xunsigned ucb$v_md_intio : 1; /* internal IO to create new disk */N unsigned ucb$v_md_dtregion : 1; /* disktab region created */N unsigned ucb$v_md_dtentry_cre : 1; /* disktab entry created */N unsigned ucb$v_md_dtentry_mod : 1; /* disktab entry modified */R unsigned ucb$v_md_updatinghome : 1; /* homeblock update in progress */N unsigned ucb$v_md_updatingfmt : 1; /* format update in progress */N unsigned ucb$v_md_rsvd X1 : 1; /* */( unsigned ucb$v_fill_64_ : 6; } ucb$r_status_bits;% unsigned int ucb$l_md_status;" } ucb$r_md_status_overlay;N unsigned __int64 ucb$q_md_lbn; /* irp$l_media */N unsigned __int64 ucb$q_md_homelbn; /* homeblock LBN */N unsigned int ucb$l_md_ramfunction; /* irp$l_func */N unsigned int ucb$l_md_ramcontrol; /* irp$q_qio_p2 (bits 0-31) X */N unsigned int ucb$l_md_ramrad; /* irp$l_qio_p6 */N unsigned __int64 ucb$q_md_ramcapacity; /* irp$q_qio_p1 */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_md_disktab_sva; /* disktab section address */#else( unsigned __int64 ucb$pq_md_disktab_sva;#endifN __int64 ucb$q_md !X_disktab_pte_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN SHM_ID ucb$r_md_disktab_shm_reg_id; /* disktab gsection region id */#pragma __nomember_alignmentN unsigned int ucb$l_md_disktab_len; /* disktab gsection length */N unsigned int ucb$l_md_frsterr_status; /* last error status "X */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_md_disk_sva; /* disk section address */#else% unsigned __int64 ucb$pq_md_disk_sva;#endifN __int64 ucb$q_md_disk_pte_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */ #X'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN SHM_ID ucb$r_md_disk_reg_id; /* disk gsection region id */#pragma __nomember_alignmentN unsigned int ucb$l_md_disk_len; /* disk length in pages */N unsigned int ucb$l_md_lasterr_status; /* last error status */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size d $Xefault to 64-bit pointers */N void *ucb$pq_md_user_buffer_sva; /* user buffer VA */#else, unsigned __int64 ucb$pq_md_user_buffer_sva;#endifN __int64 ucb$q_md_user_buffer_pte_fill; /* NOSVAPTE_V9.0 Dave Fairbanks */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_md_gnodes_cbb; /* gnode CBB bitmap pointer */ %X#else' unsigned __int64 ucb$pq_md_gnodes_cbb;#endifN unsigned int ucb$l_md_pfns; /* number of pfns allocated */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *ucb$l_md_create_disk_link; /* link to next disk to create */N __struct { /* embebed Lock LKSB */N unsigned sho&Xrt int ucb$w_md_lock_status; /* lock status */. unsigned short int ucb$w_md_lock_rsvd;N unsigned int ucb$l_md_lock_lockid; /* lock lock ID */N char ucb$t_md_lock_valblk [12]; /* lock value block */ } ucb$r_md_lksb_lock;N char ucb$t_md_volname [12]; /* disk label */N __struct { /* embebed Perm LKSB */N unsigned short int ucb$w_md_perm_statu'Xs; /* perm status */. unsigned short int ucb$w_md_perm_rsvd;N unsigned int ucb$l_md_perm_lockid; /* perm lock ID */N char ucb$t_md_perm_valblk [12]; /* perm value block */ } ucb$r_md_lksb_perm;N unsigned char ucb$b_md_nomem_retrycnt; /* no memory retry count */N unsigned char ucb$b_md_nofork_retrycnt; /* no fork retry count */N unsigned char ucb$b_md_noastcln_retrycnt; /* no AST clean retry coun (Xt */N unsigned char ucb$b_md_rsvd_retrycnt; /* rsvd retry count */N unsigned __int64 ucb$q_md_reserved1; /* reserved quadword */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {N unsigned char ucb$r_fkb [48]; /* Embedded FKB$ */#pragma __nomember_alignment __struct {)X __union {S unsigned int ucb$l_md_dtlockfqfkb; /* FORK QUEUE FORWARD LINK lw */U struct _fkb *ucb$l_md_pdtlockfqfkb; /* FORK QUEUE FORWARD LINK ptr */) } ucb$r_md_fqfl_overlay1;N struct _fkb *ucb$l_md_pdtlockbqfkb; /*FORK QUEUE BACKWARD LINK */O unsigned short int ucb$w_md_dtlckfkbsize; /*SIZE OF UCB IN BYTES */N unsigned char ucb$b_md_dtlckfkbtype; /*STRUCTURE TYPE FOR UCB */N unsigned c *Xhar ucb$b_md_dtlckfkbflck; /* Fork lock number index */N void (*ucb$l_md_pdtlckfkbfpc)(); /*FORK PC */N __int64 ucb$q_md_dtlckfkbfr3; /*FORK R3 */N __int64 ucb$q_md_dtlckfkbfr4; /*FORK R4 */ } ucb$r_fkb_overlay; } ucb$r_md_fkb;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#els +Xe#pragma __nomember_alignment#endif __union {N unsigned char ucb$r_fkb2 [48]; /* Embedded FKB$ */#pragma __nomember_alignment __struct { __union {W unsigned int ucb$l_md_updatefilefqfkb; /* FORK QUEUE FORWARD LINK lw */Y struct _fkb *ucb$l_md_pupdatefilefqfkb; /* FORK QUEUE FORWARD LINK ptr */) } ucb$r_md_fqfl_overlay2;Q struct _fkb *ucb$l_md_pupdatefilebqfkb; /*FORK QUEUE B,XACKWARD LINK */P unsigned short int ucb$w_md_updtflfkbsize; /*SIZE OF UCB IN BYTES */N unsigned char ucb$b_md_updtflfkbtype; /*STRUCTURE TYPE FOR UCB */N unsigned char ucb$b_md_updtflfkbflck; /* Fork lock number index */N void (*ucb$l_md_pupdtflfkbfpc)(); /*FORK PC */N __int64 ucb$q_md_updtflfkbfr3; /*FORK R3 */N __int64 ucb$q_md_updtflfkbfr4; /*FORK R4 */! -X } ucb$r_fkb_overlay2; } ucb$r_md_fkb2; __union {N unsigned int ucb$l_md_dbg [10]; /* debug */N unsigned __int64 ucb$q_md_qdbg [5]; /* debug */ } ucb$r_md_dbg_overlay;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_md_src; /* debug .X */#else unsigned __int64 ucb$pq_md_src;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_md_dst; /* debug */#else unsigned __int64 ucb$pq_md_dst;#endifN unsigned int ucb$l_md_debuglevel; /* debug */N unsigned int ucb$l_md_version; /* reserved lo /Xngword */N unsigned int ucb$l_md_reserved2; /* reserved longword */ char ucb$b_fill_65_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N 0Xvoid *ucb$pq_md_disktab_pte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else, unsigned __int64 ucb$pq_md_disktab_pte_sva;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_md_disk_pte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else) unsigned __int64 ucb$pq_md_disk_pte_sva;#endifR#ifdef __INITIAL_POINT 1XER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *ucb$pq_md_user_buffer_pte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else0 unsigned __int64 ucb$pq_md_user_buffer_pte_sva;#endif } MD_UCB; #if !defined(__VAXC)Q#define ucb$v_md_memory ucb$r_md_status_overlay.ucb$r_status_bits.ucb$v_md_memoryS#define ucb$v_md_ucb_fip ucb$r_md_status_overlay.ucb$r_status_bits.ucb$v_md_ucb_2Xfip]#define ucb$v_md_updatingfile ucb$r_md_status_overlay.ucb$r_status_bits.ucb$v_md_updatingfileO#define ucb$v_md_intio ucb$r_md_status_overlay.ucb$r_status_bits.ucb$v_md_intioU#define ucb$v_md_dtregion ucb$r_md_status_overlay.ucb$r_status_bits.ucb$v_md_dtregion[#define ucb$v_md_dtentry_cre ucb$r_md_status_overlay.ucb$r_status_bits.ucb$v_md_dtentry_cre[#define ucb$v_md_dtentry_mod ucb$r_md_status_overlay.ucb$r_status_bits.ucb$v_md_dtentry_mod]#define ucb$v_md_updatinghome ucb$r_md_status_3Xoverlay.ucb$r_status_bits.ucb$v_md_updatinghome[#define ucb$v_md_updatingfmt ucb$r_md_status_overlay.ucb$r_status_bits.ucb$v_md_updatingfmtO#define ucb$v_md_rsvd1 ucb$r_md_status_overlay.ucb$r_status_bits.ucb$v_md_rsvd1?#define ucb$l_md_status ucb$r_md_status_overlay.ucb$l_md_statusD#define ucb$w_md_lock_status ucb$r_md_lksb_lock.ucb$w_md_lock_status@#define ucb$w_md_lock_rsvd ucb$r_md_lksb_lock.ucb$w_md_lock_rsvdD#define ucb$l_md_lock_lockid ucb$r_md_lksb_lock.ucb$l_md_lock_lockidD#define 4Xucb$t_md_lock_valblk ucb$r_md_lksb_lock.ucb$t_md_lock_valblkD#define ucb$w_md_perm_status ucb$r_md_lksb_perm.ucb$w_md_perm_status@#define ucb$w_md_perm_rsvd ucb$r_md_lksb_perm.ucb$w_md_perm_rsvdD#define ucb$l_md_perm_lockid ucb$r_md_lksb_perm.ucb$l_md_perm_lockidD#define ucb$t_md_perm_valblk ucb$r_md_lksb_perm.ucb$t_md_perm_valblk(#define ucb$r_fkb ucb$r_md_fkb.ucb$r_fkbg#define ucb$l_md_dtlockfqfkb ucb$r_md_fkb.ucb$r_fkb_overlay.ucb$r_md_fqfl_overlay1.ucb$l_md_dtlockfqfkbi#define ucb$l_md_pdt5Xlockfqfkb ucb$r_md_fkb.ucb$r_fkb_overlay.ucb$r_md_fqfl_overlay1.ucb$l_md_pdtlockfqfkbR#define ucb$l_md_pdtlockbqfkb ucb$r_md_fkb.ucb$r_fkb_overlay.ucb$l_md_pdtlockbqfkbR#define ucb$w_md_dtlckfkbsize ucb$r_md_fkb.ucb$r_fkb_overlay.ucb$w_md_dtlckfkbsizeR#define ucb$b_md_dtlckfkbtype ucb$r_md_fkb.ucb$r_fkb_overlay.ucb$b_md_dtlckfkbtypeR#define ucb$b_md_dtlckfkbflck ucb$r_md_fkb.ucb$r_fkb_overlay.ucb$b_md_dtlckfkbflckR#define ucb$l_md_pdtlckfkbfpc ucb$r_md_fkb.ucb$r_fkb_overlay.ucb$l_md_pdtlckfkbfpc6XP#define ucb$q_md_dtlckfkbfr3 ucb$r_md_fkb.ucb$r_fkb_overlay.ucb$q_md_dtlckfkbfr3P#define ucb$q_md_dtlckfkbfr4 ucb$r_md_fkb.ucb$r_fkb_overlay.ucb$q_md_dtlckfkbfr4+#define ucb$r_fkb2 ucb$r_md_fkb2.ucb$r_fkb2q#define ucb$l_md_updatefilefqfkb ucb$r_md_fkb2.ucb$r_fkb_overlay2.ucb$r_md_fqfl_overlay2.ucb$l_md_updatefilefqfkbs#define ucb$l_md_pupdatefilefqfkb ucb$r_md_fkb2.ucb$r_fkb_overlay2.ucb$r_md_fqfl_overlay2.ucb$l_md_pupdatefilefqfkb\#define ucb$l_md_pupdatefilebqfkb ucb$r_md_fkb2.ucb$r_fkb_ov7Xerlay2.ucb$l_md_pupdatefilebqfkbV#define ucb$w_md_updtflfkbsize ucb$r_md_fkb2.ucb$r_fkb_overlay2.ucb$w_md_updtflfkbsizeV#define ucb$b_md_updtflfkbtype ucb$r_md_fkb2.ucb$r_fkb_overlay2.ucb$b_md_updtflfkbtypeV#define ucb$b_md_updtflfkbflck ucb$r_md_fkb2.ucb$r_fkb_overlay2.ucb$b_md_updtflfkbflckV#define ucb$l_md_pupdtflfkbfpc ucb$r_md_fkb2.ucb$r_fkb_overlay2.ucb$l_md_pupdtflfkbfpcT#define ucb$q_md_updtflfkbfr3 ucb$r_md_fkb2.ucb$r_fkb_overlay2.ucb$q_md_updtflfkbfr3T#define ucb$q_md_updtflfkbfr4 ucb$ 8Xr_md_fkb2.ucb$r_fkb_overlay2.ucb$q_md_updtflfkbfr46#define ucb$l_md_dbg ucb$r_md_dbg_overlay.ucb$l_md_dbg8#define ucb$q_md_qdbg ucb$r_md_dbg_overlay.ucb$q_md_qdbg"#endif /* #if !defined(__VAXC) */  [ #define ucb$r_md_ucb ucb$r_mscpucb.ucb$r_dtucb.ucb$r_dpucb.ucb$r_erlucb.ucb$r_ucbQ #define ucb$r_md_erl ucb$r_mscpucb.ucb$r_dtucb.ucb$r_dpucb.ucb$r_erlucbD #define ucb$r_md_dp ucb$r_mscpucb.ucb$r_dtucb.ucb$r_dpucb8 #define ucb$r_md_dt ucb$r_mscpucb.ucb 9X$r_dtucb, #define ucb$r_md_mscp ucb$r_mscpucbB/* *** Add new extensions immediately before this line!!!!! *** */D/* *** All symbols in the UCB extension for device XX should *** */D/* *** have names that begin XX_, including the length symbol *** */G/* *** UCB$C_XX_LENGTH. (Note the need for "tag C" when creating *** */B/* *** this symbol, otherwise you'll get UCB$K_XX_LENGTH.) *** */F/* *** Contact the SDA maintainer so that SDA can be taught how *** */6/* *** to format the XX exte:Xnsion to the UCB. *** */N/* */N/* SUPPLEMENTAL UCB DATA definition */L/* This structure is intended to contain information which should belong */I/* in the UCB but can't because we cannot change the size of the UCB */I/* without impacting customers. */N/* */#define ;XSUD$M_AUX_SUD_ALLOC 0x1 #define SUD$M_PATH_AVAILABLE 0x1#define SUD$M_OK2UINIT 0x2#define SUD$M_PV_TRIED 0x4#define SUD$M_PACKACK_TRIED 0x8#define SUD$M_SWITCH_TRIED 0x10%#define SUD$M_PATH_USER_DISABLED 0x20"#define SUD$M_NOTCURPATH_IOIP 0x40#define SUD$M_POLL_ENABLED 0x80"#define SUD$M_NOT_RESPONDING 0x100#define SUD$M_NO_PR_SUPP 0x200%#define SUD$M_MV_MSG_SUPPRESSED 0x400#define SUD$M_CFGCBK_PND 0x800&#define SUD$M_MVSUPMSG_OVERRIDE 0x1000'#define SUD$M_SHUNNED_ON_LAST_PVXwhenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _ucb *sud$ps_ucblink; /* Pointer to UCB for this SUD */U void *sud$ps_aux_sud; /* Pointer to Driver UCB extension area. */N unsigned short int sud$w_size; /* Size of SUD, in bytes. */S unsigned char sud$b_type; /* Nonpaged pool packet type, DYN$C_MISC */V unsigned char sud$b_subtyp ?Xe; /* Nonpaged pool packet subtype, DYN$C_SUD */N/* Flag bits */ __union {! unsigned int sud$l_flags; __struct {h unsigned sud$v_aux_sud_alloc : 1; /* Area pointed to by SUD$PS_AUX_SUD has been allocated */( unsigned sud$v_fill_72_ : 7; } sud$r_fill_67_; } sud$r_fill_66_; __union { unsigned int sud$l_sts; __struct {^ un@Xsigned sud$v_path_available : 1; /* Set by driver once unit init is complete. */` unsigned sud$v_ok2uinit : 1; /* Set by driver if unit init failed. It states that */N/* this UCB can be reused. */_ unsigned sud$v_pv_tried : 1; /* Set if path verification I/O has been issued to */N/* this path while path verification is in progress */Z unsigned sud$v_packack_tried : 1; /* Set if packack I/O AXhas been issued to */N/* this path while path verification is in progress */[ unsigned sud$v_switch_tried : 1; /* Set if path switch has been switched to */N/* while path verification is in progress */^ unsigned sud$v_path_user_disabled : 1; /* Set if access denied via user request */e unsigned sud$v_notcurpath_ioip : 1; /* Set if this path is not the current path but it */N/* has I/O in progress BX */N unsigned sud$v_poll_enabled : 1; /* Poll enabled on this path */[ unsigned sud$v_not_responding : 1; /* Device is not responding via this path */R unsigned sud$v_no_pr_supp : 1; /* No Persistent Reservation Support */o unsigned sud$v_mv_msg_suppressed : 1; /* MV start msg has been automatically suppressed, for now */X unsigned sud$v_cfgcbk_pnd : 1; /* Device configuration call back pendi CXng */f unsigned sud$v_mvsupmsg_override : 1; /* Override message suppression for this MV event */v unsigned sud$v_shunned_on_last_pv : 1; /* Path was shunned on the most recent path verification attempt */( unsigned sud$v_fill_73_ : 2; } sud$r_fill_69_; } sud$r_fill_68_; __union {$ unsigned int sud$l_devchar3; __struct {N unsigned sud$v_wwid_present : 1; /* this SUD contains WWID */f unsiDXgned sud$v_fc_port_name_present : 1; /* this SUD contains a fibre channel port name */f unsigned sud$v_fc_node_name_present : 1; /* this SUD contains a fibre channel node name */V unsigned sud$v_pr_disabled : 1; /* Persistent Reservations are disabled */W unsigned sud$v_cloned_ucb : 1; /* indicates, if this UCB is a cloned UCB */j unsigned sud$v_nosynch_cancel : 1; /* driver cancel routine will be called without forklock */^ unsigned sud$v_sEXas_address_present : 1; /* this SUD contains a SAS Port Address */S unsigned sud$v_sata_end_device : 1; /* this SUD contains a SATA WWID */Y unsigned sud$v_ir_volume : 1; /* this SUD contains an Integrated RAID WWID */X unsigned sud$v_ciss_ext_lun : 1; /* this SUD contains a CISS external Lun */( unsigned sud$v_fill_74_ : 6; } sud$r_fill_71_; } sud$r_fill_70_;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* I FXf using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN unsigned __int64 sud$q_scssystemid; /* SCS system ID */#pragma __nomember_alignmentN unsigned int sud$l_spare_1; /* */N unsigned int sud$l_spare_2; /* */N unsigned int sud$l_spare_3; /* */N unsigned int sud$l_spare_4; GX /* */N unsigned int sud$l_wwid_offset; /* WWID ofset */N unsigned int sud$l_wwid_length; /* WWID length */P struct _mpdev *sud$ps_mpdev; /* Pointer to the multipath structure */Q struct _ucb *sud$ps_mpdev_primary_ucb; /* Pointer to the primary paths UCB */Y struct _ucb *sud$ps_mpdev_next_ucb; /* Pointer to the next UCB in a multipath set. */ char sud$b_fill_75_ [4];c#if !defined HX(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifZ unsigned __int64 sud$q_mpdev_switch_to_time; /* last time this path was switched to */^ unsigned __int64 sud$q_mpdev_switch_from_time; /* last time this path was switched from */#pragma __nomember_alignmentY struct _mpdev_ppb *sud$ps_mpdev_ppb; /* Pointer to Path Poller Block for this path */ __union { IX __struct {N unsigned int sud$l_fp_flags; /* Fastpath flags */! } sud$r_flags_fields; __struct {X unsigned sud$v_fp_on_port_queue : 1; /* set if port already on port queue */Y unsigned sud$v_fp_user_pref_cpu : 1; /* set if user has assigned this port */u unsigned sud$v_fp_on_hwint_port_queue : 1; /* set if port already on FASTPATH HW interrupt ports queue */s unsigned sud$v_fp_usrprf_hwint_cpuJX : 1; /* set if user has assigned this port to a HW interrupt CPU. */` unsigned sud$v_fp_init_failed : 1; /* exe$fp_port_init() failed to init this port */( unsigned sud$v_fill_76_ : 3; } sud$r_flags_bits; } sud$r_flags_overlay;N/* Fastpath preferred CPU state */P struct _cpu *sud$l_fp_usrprf_cpudb; /* CPU db addr of user-preferred port */N struct _sud *sud$l_fp_ports_link; /* single-link queue of poKXrts. */O void *sud$l_fp_asgn_ports_fl; /* queue links into per-CPU assigned */N void *sud$l_fp_asgn_ports_bl; /* ports queue. */N/* Fastpath HW interrupt CPU state */V struct _cpu *sud$l_fp_hwint_cpu; /* CPU db addr of current HW interrupt CPU. */a struct _cpu *sud$l_fp_usrprf_hwint_cpu; /* CPU db addr of user-preferred HW interrupt CPU. */^ struct _sud *sud$l_fp_hwint_ports_link; /* single-link que LXue of all HW interrupt ports. */X void *sud$l_fp_asgn_hwint_ports_fl; /* queue links into the current HW interrupt */_ void *sud$l_fp_asgn_hwint_ports_bl; /* CPU's list of HW interrupt ports assigned to it.. */N/* Fastpath contingency cells */ int sud$l_fp_spare1; int sud$l_fp_spare2; int sud$l_fp_spare3; int sud$l_fp_spare4;N unsigned int sud$l_mpdev_pv_iost1; /* Last PV I/O status on path */N unsigned int sudMX$l_mpdev_pv_abstim; /* Last PV time (abstim) */W unsigned int sud$l_mpdev_tracking_end; /* Current tracking interval end (abstim) */P unsigned int sud$l_mpdev_tracking_count; /* PV incursions during interval */N unsigned int sud$l_mpdev_pv_duration; /* Last PV I/O duration (seconds) */f struct _sud *sud$ps_mpdev_path_link; /* Pointer to next SUD on same MPDEV_PPB (null terminated) */] unsigned int sud$l_mpdev_shunned_count; /* Total number of times path has been shunnedNX */N int sud$l_mpdev_spare_6; /* Reserved for multipath */N int sud$l_mpdev_path_id; /* Path id for multipath */V struct _fc_wwid_64b *sud$ps_fc_port_name; /* Pointer to fibre channel port name */V struct _fc_wwid_64b *sud$ps_fc_node_name; /* Pointer to fibre channel node name */N struct _irp *sud$l_busy_bit_irp_p; /* Pointer to ucb$r_busy_bit_irp */N char sud$t_dev_serial_num [24]; /* serial number of device */c OXunsigned int sud$l_mvsupmsg_intvl_end; /* End of current quiet MV interval in ABSTIM seconds */k unsigned int sud$l_mvsupmsg_intvl_num; /* Count of suppressed MV messages so far in current interval */q unsigned int sud$l_mvsupmsg_total_num; /* Total count of suppressed MV messages since boot for this device */d unsigned int sud$l_mvsupmsg_intvl; /* MV msg suppression interval in seconds for this device */N/* Changed by SET DEVICE/MV_INTERVAL=n, 0 means use system-wide value */P PX unsigned int sud$l_mvsupmsg_num; /* MV msg suppression threshold count */N/* Changed by SET DEVICE/MV_NUMBER=n, 0 means use system-wide value */T unsigned __int64 sud$q_last_errrst; /* Last time the error count of was reset */d unsigned int sud$l_mpdev_path_switch_count; /* count of successful path switches to this path */ int sud$l_io_exec_spare_1; int sud$l_io_exec_spare_2; int sud$l_io_exec_spare_3; int sud$l_io_exec_spare_4; int sud$l_io_exec_spare_QX5; int sud$l_io_exec_spare_6; int sud$l_io_exec_spare_7; int sud$l_io_exec_spare_8; char sud$b_fill_77_ [4]; } SUD; #if !defined(__VAXC).#define sud$l_flags sud$r_fill_66_.sud$l_flagsM#define sud$v_aux_sud_alloc sud$r_fill_66_.sud$r_fill_67_.sud$v_aux_sud_alloc*#define sud$l_sts sud$r_fill_68_.sud$l_stsO#define sud$v_path_available sud$r_fill_68_.sud$r_fill_69_.sud$v_path_availableC#define sud$v_ok2uinit sud$r_fill_68_.sud$r_fill_69_.sud$v_ok2uinitC#define sud$v_RXpv_tried sud$r_fill_68_.sud$r_fill_69_.sud$v_pv_triedM#define sud$v_packack_tried sud$r_fill_68_.sud$r_fill_69_.sud$v_packack_triedK#define sud$v_switch_tried sud$r_fill_68_.sud$r_fill_69_.sud$v_switch_triedW#define sud$v_path_user_disabled sud$r_fill_68_.sud$r_fill_69_.sud$v_path_user_disabledQ#define sud$v_notcurpath_ioip sud$r_fill_68_.sud$r_fill_69_.sud$v_notcurpath_ioipK#define sud$v_poll_enabled sud$r_fill_68_.sud$r_fill_69_.sud$v_poll_enabledO#define sud$v_not_responding sud$r_fill_SX68_.sud$r_fill_69_.sud$v_not_respondingG#define sud$v_no_pr_supp sud$r_fill_68_.sud$r_fill_69_.sud$v_no_pr_suppU#define sud$v_mv_msg_suppressed sud$r_fill_68_.sud$r_fill_69_.sud$v_mv_msg_suppressedG#define sud$v_cfgcbk_pnd sud$r_fill_68_.sud$r_fill_69_.sud$v_cfgcbk_pndU#define sud$v_mvsupmsg_override sud$r_fill_68_.sud$r_fill_69_.sud$v_mvsupmsg_overrideW#define sud$v_shunned_on_last_pv sud$r_fill_68_.sud$r_fill_69_.sud$v_shunned_on_last_pv4#define sud$l_devchar3 sud$r_fill_70_.sud$l_devchaTXr3K#define sud$v_wwid_present sud$r_fill_70_.sud$r_fill_71_.sud$v_wwid_present[#define sud$v_fc_port_name_present sud$r_fill_70_.sud$r_fill_71_.sud$v_fc_port_name_present[#define sud$v_fc_node_name_present sud$r_fill_70_.sud$r_fill_71_.sud$v_fc_node_name_presentI#define sud$v_pr_disabled sud$r_fill_70_.sud$r_fill_71_.sud$v_pr_disabledG#define sud$v_cloned_ucb sud$r_fill_70_.sud$r_fill_71_.sud$v_cloned_ucbO#define sud$v_nosynch_cancel sud$r_fill_70_.sud$r_fill_71_.sud$v_nosynch_cancelY#defUXine sud$v_sas_address_present sud$r_fill_70_.sud$r_fill_71_.sud$v_sas_address_presentQ#define sud$v_sata_end_device sud$r_fill_70_.sud$r_fill_71_.sud$v_sata_end_deviceE#define sud$v_ir_volume sud$r_fill_70_.sud$r_fill_71_.sud$v_ir_volumeK#define sud$v_ciss_ext_lun sud$r_fill_70_.sud$r_fill_71_.sud$v_ciss_ext_lunL#define sud$l_fp_flags sud$r_flags_overlay.sud$r_flags_fields.sud$l_fp_flagsZ#define sud$v_fp_on_port_queue sud$r_flags_overlay.sud$r_flags_bits.sud$v_fp_on_port_queueZ#define sud$v_VXfp_user_pref_cpu sud$r_flags_overlay.sud$r_flags_bits.sud$v_fp_user_pref_cpuf#define sud$v_fp_on_hwint_port_queue sud$r_flags_overlay.sud$r_flags_bits.sud$v_fp_on_hwint_port_queue`#define sud$v_fp_usrprf_hwint_cpu sud$r_flags_overlay.sud$r_flags_bits.sud$v_fp_usrprf_hwint_cpuV#define sud$v_fp_init_failed sud$r_flags_overlay.sud$r_flags_bits.sud$v_fp_init_failed"#endif /* #if !defined(__VAXC) */ N#define SUD$C_LENGTH 288 /* Length of a SUD */N#define SUD$K_LENGWXTH 288 /* Length of a SUD */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __UCBDEF_LOADED */ wwp[UM/***************************************************************************/M/** XX **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** YX **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** ZX **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** [X MODULE $UCBNIDEF ***/#ifndef __UCBNIDEF_LOADED#define __UCBNIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif\X #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ ]X */N/* LAN definitions that follow the standard UCB fields */N/*-- */ N/* Extensions to the UCB for the LAN drivers */#define UCB$C_NI_NUMGSP 4O#define UCB$C_NI_ALLPRM 672 /* Start of parameters to copy/match */N/* with LSB parameters */$#define UCB$C_NI_EMBED_TABLE_SIZE 88N/* Size of the embedded mu ^Xlticast table */Q#define UCB$C_NI_QUE_START 992 /* Message and I/O request queue heads */#define UCB$C_NI_QUE_NO 2N/* Number of queue heads */#define UCB$C_NI_TR_ENTSIZE 16N#define UCB$C_NI_ACTUAL_LENGTH 1112 /* Size of a LAN driver UCB */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword _X#else#pragma __nomember_alignment#endiftypedef struct _ucbnidef {N/* Overlay the UCB structure at UCB$C_NI_LENGTH. */#pragma __nomember_alignment% char ucbdef$$_ni_ucbfill_1 [504];N/* DLL extensions to the common UCB section. */N unsigned int ucb$l_ni_pid; /* Starter's PID */N unsigned int ucb$l_ni_quota; /* Receive buffer quota charged */N unsigned int ucb$l_ni_ast; /*`X Attention AST list */R unsigned int ucb$l_ni_stopirp; /* Address of the STOPIRP for QIO users */Q unsigned int ucb$l_ni_resbuf; /* Address of automatic restart buffer */N unsigned int ucb$l_ni_vcib; /* VMS Comm Interface Block address */N unsigned int ucb$l_ni_lsb; /* Address of LSB */N unsigned int ucb$l_ni_p2param; /* Parameters set in SETMODE QIO */N unsigned int ucb$l_ni_mst; /* Maintenance stateaX */N/* The following fields are used to record information that may be */N/* relevant when examining a CLUEXIT crash dump. */P unsigned int ucb$l_ni_lstrcvtim; /* Time of last receive for this user */Q unsigned int ucb$l_ni_lstxmttim; /* Time of last transmit for this user */N unsigned int ucb$l_ni_lststratt; /* Time of last start attempt for */N/* this user */ObX unsigned int ucb$l_ni_lststrcmp; /* Time of last success user startup */N unsigned int ucb$l_ni_lststrfld; /* Time of last failed user restart */N unsigned int ucb$l_ni_lstuubtim; /* Time of last UUB for this user */N/* These are the user's parameters as written in a SETMODE request and */N/* read in a SENSEMODE request. */N unsigned int ucb$l_ni_acc; /* Access mode */N unsigned int ucb$l_ncXi_bsz; /* Device buffer size (only used to */N/* hold user's requested value) */N unsigned int ucb$l_ni_dch; /* Data chaining (only used to hold */N/* user's requested value) */( unsigned short int ucb$g_ni_des [4];N/* Destination address for shared */N/* user (6 bytes) */N unsidXgned int ucb$l_ni_fmt; /* Packet format */N unsigned int ucb$l_ni_gsp; /* 802.2 Group SAPs (4) */( unsigned short int ucb$g_ni_hwa [4];N/* Hardware address (6 bytes) */N unsigned int ucb$l_ni_mbs; /* Maximum buffer size */O unsigned int ucb$l_ni_med; /* Medium (ATM, CSMACD, FDDI, or TR) */N unsigned int ucb$l_ni_mrb; /* Minimum Receive Buffers eX */N int ucb$l_extra_l_1; /* Preserve quadword alignment */# unsigned char ucb$g_ni_pid [8];N/* 802E Protocol Id (5 bytes) */N unsigned int ucb$l_ni_prm; /* Promiscuous mode */N unsigned int ucb$l_ni_sap; /* 802.2 Service Access Point */N unsigned int ucb$l_ni_srv; /* 802.2 Service */N unsigned int ucb$l_ni_apc; /* Allow promiscuofXus client */N unsigned int ucb$l_ni_bfn; /* Number of receive buffers */N unsigned int ucb$l_ni_cca; /* Can change address */N unsigned int ucb$l_ni_mlt; /* All Multicast mode */N unsigned int ucb$l_ni_pad; /* Padding mode */N unsigned int ucb$l_ni_pty; /* Ethernet protocol type */N unsigned int ucb$l_ni_res; /* Automatic restart */ gX__union {N unsigned int ucb$l_ni_xfc; /* User supplied FC (priority only) */N unsigned int ucb$l_ni_xac; /* User supplied AC (priority only) */ } ucb$r_xmit_fc; __union {N unsigned int ucb$l_ni_rfc; /* User wants FC on recv mode */N unsigned int ucb$l_ni_rac; /* User wants AC on recv mode */ } ucb$r_recv_fc;N/* The BADPRMTBL table in the LAN module must match the parameters in this */N/* section of the UCB. hX */N unsigned int ucb$l_ni_con; /* Controller mode */N unsigned int ucb$l_ni_ilp; /* Internal loopback mode */N unsigned int ucb$l_ni_crc; /* CRC generation mode */N int ucb$l_extra_l_2; /* Preserve quadword alignment */( unsigned short int ucb$g_ni_pha [4];N/* Physical address (6 bytes) */N unsigniXed int ucb$l_ni_famode; /* Functional Address Mode */N unsigned int ucb$l_ni_srmode; /* Source Routing Mode */N/* End of the parameters that are copied into the LSB on INIT. */N/* End of parameter section */N/* We need two fields for the header size. The first one is the full */N/* header size and will be copied into the VCIB$W_DLL_HDR_SIZE field for */N/* VCI clients. The sub header fieljXd is the number of bytes in the header */N/* excluding the PDU$C_ETH_HEADER bytes for the standard Ethernet header. */N unsigned int ucb$l_ni_hdr; /* Maximum header size */O unsigned int ucb$l_ni_fc; /* Default FC for transmit (FDDI/TR) */N unsigned int ucb$l_ni_ac; /* Default AC for transmit (TR) */N/* Filtering fields. NI_MCLAST contains the last multicast filtered on */P/* behalf of this user (set to -1 when a start/change/stop ikXs done), NI_MCENA */N/* tells the disposition of the filtering (LBS if passed, LBC if rejected). */N/* NI_EMBED_MULTI gives the list of multicast addresses embedded in the */N/* UCB with a pointer to additional tables if needed. */R unsigned int ucb$l_ni_mcena; /* LBS if last mca filtered was enabled */N unsigned __int64 ucb$q_ni_mclast; /* Last user MCA filtered */, unsigned char ucb$t_ni_embed_multi [88];N/* Set up embedded table lX */N/* Source filtering fields. NI_SOURCE is the address of a list of source */N/* addresses enabled for the user (zero if there are none). NI_SACHECK */N/* indicates whether any source address checking is needed at at all. */N/* NI_SAENA tells the disposition of the filtering (LBS if passed, LBC if */N/* rejected) for the address given in NI_SALAST. NI_SALAST gives the last */N/* source address filtered on behalf of this user (set to -1mX when a start/ */N/* change/stop is done), */N int ucb$l_extra_l_3; /* Preserve quadword alignment */N unsigned int ucb$l_ni_source; /* Address of source address table */N unsigned int ucb$l_ni_sancheck; /* LBS if no SA checking is needed */Q unsigned int ucb$l_ni_saena; /* LBS if last SA filtered was enabled */O unsigned __int64 ucb$q_ni_salast; /* Last user source address filtered */NnX/* Phase V counter section. This is where we really count. */N unsigned __int64 ucb$q_lan_ocrctr; /* Octets received */N unsigned __int64 ucb$q_lan_morctr; /* Multicast octets received */N unsigned __int64 ucb$q_lan_octctr; /* Octets transmitted */N unsigned __int64 ucb$q_lan_motctr; /* Multicast octets transmitted */N unsigned __int64 ucb$q_lan_pdrctr; /* PDUs received */N unsigned __int64 ucb$qoX_lan_mprctr; /* Multicast PDUs received */N unsigned __int64 ucb$q_lan_pdtctr; /* PDUs transmitted */N unsigned __int64 ucb$q_lan_mptctr; /* Multicast PDUs transmitted */N unsigned __int64 ucb$q_lan_uubctr; /* Unavailable user buffers */O/* Non-architected counter maintained similar to the other Phase V counters. */N unsigned __int64 ucb$q_lan_mnectr; /* Multicast not enabled */N/* Phase IV clear section. This is where we storepX how much of the */N/* Phase V counters have been cleared for Phase IV. */N unsigned __int64 ucb$q_lan_uubclr; /* Unavailable user buffers */N unsigned __int64 ucb$q_lan_pdtclr; /* PDUs transmitted */N unsigned __int64 ucb$q_lan_octclr; /* Octets transmitted */N unsigned __int64 ucb$q_lan_pdrclr; /* PDUs received */N unsigned __int64 ucb$q_lan_ocrclr; /* Octets received qX*/O/* Non-architected counter maintained similar to the other Phase V counters. */N unsigned __int64 ucb$q_lan_mneclr; /* Multicast not enabled */N/* Phase IV counter section. These fields are left here so there's */N/* a place into which we can convert the Phase V counters when someone */N/* wants the Phase IV counters. */N unsigned short int ucb$w_ni_mnectr; /* Multicast address not enabled */N unsigned short irXnt ucb$w_ni_ubuctr; /* User buffer unavailable counter */N unsigned int ucb$l_ni_sblctr; /* Number of blocks sent */N unsigned int ucb$l_ni_sbyctr; /* Number of bytes sent */N unsigned int ucb$l_ni_rblctr; /* Number of blocks received */N unsigned int ucb$l_ni_rbyctr; /* Number of bytes received */N/* Miscellaneous counters. */N unsigned int ucb$l_lan_btsctr; /* NumsXber of packets discarded */N/* because user buffer was too small */N/* User queues. */N unsigned __int64 ucb$q_ni_rcvmsg; /* Receive messages completed */N unsigned __int64 ucb$q_ni_rcvreq; /* Receive IRP waiting for messages */N/* Network Management work area. */N int ucb$l_lnm_flink; /* Forward link to next UCB NM atXrea */S int ucb$l_lnm_blink; /* Backward link to previous UCB NM area */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *ucb$a_lnm_lpb; /* Pointer to the LPB for this UCB */U int ucb$l_lnm_cnm_len; /* Allocated size of client name item list */N void *ucb$a_lnm_cnm; /* Pointer to clieuXnt name item list */N/* TR only fields. There are only a few fields, so we include them in all */N/* the LAN UCBs. */O unsigned int ucb$l_ni_tr_xcuse; /* Offset to next cache entry to use */+ unsigned __int64 ucb$t_ni_tr_lstmc [4];N/* Last transmitted MC/FC cache */N unsigned __int64 ucb$q_ni_tr_xcchk; /* Times Xmit MC/FC cache checked */N unsigned __int64 ucb$q_ni_tr_xchvXit; /* Times Xmit MC/FC cache hit */N unsigned int ucb$l_ni_lsb_size; /* Port specific size of the LSB */W void *ucb$a_ni_unit_init; /* Address of port driver unit init fork rtn */N unsigned int ucb$l_ni_vlan_tag; /* VLAN tag used by this unit */N unsigned int ucb$l_ni_udpuser_pty; /* UDPDRIVER change PTY flag for TX */Z unsigned int ucb$l_ni_udpuser_len; /* UDPDRIVER length of data to add to TX packet */ char ucb$b_fill_63_ [4];c#if !definwXed(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifO unsigned __int64 ucb$q_ni_udpuser_pa; /* UDPDRIVER data physical address */ } UCBNIDEF; #if !defined(__VAXC)/#define ucb$l_ni_xfc ucb$r_xmit_fc.ucb$l_ni_xfc/#define ucb$l_ni_xac ucb$r_xmit_fc.ucb$l_ni_xac/#define ucb$l_ni_rfc ucb$r_recv_fc.ucb$l_ni_rfc/#define ucb$l_ni_rac ucb$r_recv_fc.ucb$l_ni_rac"xX#endif /* #if !defined(__VAXC) */ N/* Define device status bits for the LAN driver UCBs */ #define UCB$M_NI_START_BEGUN 0x1#define UCB$M_LAN_LENGTH 0x2#define UCB$M_LAN_UNIQID 0x4#define UCB$M_NI_SHARE 0x8#define UCB$M_NI_STARTED 0x10##define UCB$M_NI_RESTART_INUSE 0x20#define UCB$M_NI_PASS 0x40#define UCB$M_NI_SHARE_DEF 0x80 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignme yXnt __longword#else#pragma __nomember_alignment#endiftypedef struct _ucbnists {#pragma __nomember_alignment __union {" unsigned int ucb$l_ni_sts; __struct {N unsigned ucb$v_ni_start_begun : 1; /* Device is (being) started */O unsigned ucb$v_lan_length : 1; /* Length field required in frame */N unsigned ucb$v_lan_uniqid : 1; /* Unique ID has been specified */N unsigned ucb$v_ni_share : 1; /* Shared protocol type zX */N unsigned ucb$v_ni_started : 1; /* Device is STARTED */V unsigned ucb$v_ni_restart_inuse : 1; /* Automatic RESTART buffer in use */N unsigned ucb$v_ni_pass : 1; /* Pass through user */N unsigned ucb$v_ni_share_def : 1; /* Shared default user */N unsigned ucb$v_ni_filler : 24; /* force longword */ } ucb$r_fill_65_; } ucb$r_fill_64_; } UCBNISTS; #if !d{Xefined(__VAXC)0#define ucb$l_ni_sts ucb$r_fill_64_.ucb$l_ni_stsO#define ucb$v_ni_start_begun ucb$r_fill_64_.ucb$r_fill_65_.ucb$v_ni_start_begunG#define ucb$v_lan_length ucb$r_fill_64_.ucb$r_fill_65_.ucb$v_lan_lengthG#define ucb$v_lan_uniqid ucb$r_fill_64_.ucb$r_fill_65_.ucb$v_lan_uniqidC#define ucb$v_ni_share ucb$r_fill_64_.ucb$r_fill_65_.ucb$v_ni_shareG#define ucb$v_ni_started ucb$r_fill_64_.ucb$r_fill_65_.ucb$v_ni_startedS#define ucb$v_ni_restart_inuse ucb$r_fill_64_.ucb$r_fill_65_.ucb$v|X_ni_restart_inuseA#define ucb$v_ni_pass ucb$r_fill_64_.ucb$r_fill_65_.ucb$v_ni_passK#define ucb$v_ni_share_def ucb$r_fill_64_.ucb$r_fill_65_.ucb$v_ni_share_def"#endif /* #if !defined(__VAXC) */ N/* Define P2 parameter bits for the LAN drivers */#define UCB$M_NI_PRM_ACC 0x1#define UCB$M_NI_PRM_APC 0x2#define UCB$M_NI_PRM_BFN 0x4#define UCB$M_NI_PRM_BSZ 0x8#define UCB$M_NI_PRM_BUS 0x10#define UCB$M_NI_PRM_CCA 0x20#define UCB$M_NI_PRM_CNM 0x40#def}Xine UCB$M_NI_PRM_CON 0x80#define UCB$M_NI_PRM_ILP 0x100#define UCB$M_NI_PRM_CRC 0x200#define UCB$M_NI_PRM_DCH 0x400#define UCB$M_NI_PRM_DES 0x800#define UCB$M_NI_PRM_FMT 0x1000#define UCB$M_NI_PRM_GSP 0x2000#define UCB$M_NI_PRM_HWA 0x4000#define UCB$M_NI_PRM_MCA 0x8000 #define UCB$M_NI_PRM_MED 0x10000 #define UCB$M_NI_PRM_MLT 0x20000 #define UCB$M_NI_PRM_MRB 0x40000 #define UCB$M_NI_PRM_PAD 0x80000!#define UCB$M_NI_PRM_PHA 0x100000!#define UCB$M_NI_PRM_PID 0x200000!#defin~Xe UCB$M_NI_PRM_PRM 0x400000!#define UCB$M_NI_PRM_PTY 0x800000"#define UCB$M_NI_PRM_RES 0x1000000"#define UCB$M_NI_PRM_SAP 0x2000000"#define UCB$M_NI_PRM_SRV 0x4000000"#define UCB$M_NI_PRM_MBS 0x8000000##define UCB$M_NI_PRM_RFC 0x10000000##define UCB$M_NI_PRM_XFC 0x20000000##define UCB$M_NI_PRM_SRC 0x40000000 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignme Xnt#endiftypedef struct _ucbniprm {#pragma __nomember_alignment __union {& unsigned int ucb$l_ni_prm_str; __struct {N unsigned ucb$v_ni_prm_acc : 1; /* Access parameter specified */N unsigned ucb$v_ni_prm_apc : 1; /* Allow promiscuous client */N unsigned ucb$v_ni_prm_bfn : 1; /* Buffer number specified */N unsigned ucb$v_ni_prm_bsz : 1; /* Device buffer size specified */N unsigned ucb$v_ni_prm_bus X: 1; /* User buffer size specified */N unsigned ucb$v_ni_prm_cca : 1; /* Can change address */N unsigned ucb$v_ni_prm_cnm : 1; /* Client name specified */N unsigned ucb$v_ni_prm_con : 1; /* Controller mode specified */N unsigned ucb$v_ni_prm_ilp : 1; /* Internal loopback specified */N unsigned ucb$v_ni_prm_crc : 1; /* CRC mode specified */N unsigned ucb$v_ni_prm_dch : 1; /* Data chainning modXe specified */N unsigned ucb$v_ni_prm_des : 1; /* Destination Address specified */N unsigned ucb$v_ni_prm_fmt : 1; /* Format specified */N unsigned ucb$v_ni_prm_gsp : 1; /* Group SAP specified */N unsigned ucb$v_ni_prm_hwa : 1; /* Hardware address specified */N unsigned ucb$v_ni_prm_mca : 1; /* Multicast address specified */N unsigned ucb$v_ni_prm_med : 1; /* Medium */T X unsigned ucb$v_ni_prm_mlt : 1; /* Accept All Multicast mode specified */N unsigned ucb$v_ni_prm_mrb : 1; /* Minimum Receive Buffers */N unsigned ucb$v_ni_prm_pad : 1; /* PAD mode specified */N unsigned ucb$v_ni_prm_pha : 1; /* Physical Address specified */N unsigned ucb$v_ni_prm_pid : 1; /* Protocol Identifier specified */N unsigned ucb$v_ni_prm_prm : 1; /* Promiscious mode specified */N unsigned ucb$v_ni_Xprm_pty : 1; /* Protocol type specified */N unsigned ucb$v_ni_prm_res : 1; /* Automatic Restart specified */N unsigned ucb$v_ni_prm_sap : 1; /* SAP specified */N unsigned ucb$v_ni_prm_srv : 1; /* Service specified */N unsigned ucb$v_ni_prm_mbs : 1; /* Maximum buffer size */N unsigned ucb$v_ni_prm_rfc : 1; /* Receive FC requested */N unsigned ucb$v_ni_prm_xfc : 1; /* Transmit F XC will be passed */N unsigned ucb$v_ni_prm_src : 1; /* Source address specified */N unsigned ucb$v_ni_prm_filler : 1; /* force longword */ } ucb$r_fill_67_; } ucb$r_fill_66_; } UCBNIPRM; #if !defined(__VAXC)8#define ucb$l_ni_prm_str ucb$r_fill_66_.ucb$l_ni_prm_strG#define ucb$v_ni_prm_acc ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_accG#define ucb$v_ni_prm_apc ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_apcG#define ucb$Xv_ni_prm_bfn ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_bfnG#define ucb$v_ni_prm_bsz ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_bszG#define ucb$v_ni_prm_bus ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_busG#define ucb$v_ni_prm_cca ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_ccaG#define ucb$v_ni_prm_cnm ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_cnmG#define ucb$v_ni_prm_con ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_conG#define ucb$v_ni_prm_ilp ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_ilpGX#define ucb$v_ni_prm_crc ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_crcG#define ucb$v_ni_prm_dch ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_dchG#define ucb$v_ni_prm_des ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_desG#define ucb$v_ni_prm_fmt ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_fmtG#define ucb$v_ni_prm_gsp ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_gspG#define ucb$v_ni_prm_hwa ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_hwaG#define ucb$v_ni_prm_mca ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_nXi_prm_mcaG#define ucb$v_ni_prm_med ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_medG#define ucb$v_ni_prm_mlt ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_mltG#define ucb$v_ni_prm_mrb ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_mrbG#define ucb$v_ni_prm_pad ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_padG#define ucb$v_ni_prm_pha ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_phaG#define ucb$v_ni_prm_pid ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_pidG#define ucb$v_ni_prm_prm ucb$r_fill_66_.ucb$r_fillX_67_.ucb$v_ni_prm_prmG#define ucb$v_ni_prm_pty ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_ptyG#define ucb$v_ni_prm_res ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_resG#define ucb$v_ni_prm_sap ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_sapG#define ucb$v_ni_prm_srv ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_srvG#define ucb$v_ni_prm_mbs ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_mbsG#define ucb$v_ni_prm_rfc ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_rfcG#define ucb$v_ni_prm_xfc ucb$r_fill_66X_.ucb$r_fill_67_.ucb$v_ni_prm_xfcG#define ucb$v_ni_prm_src ucb$r_fill_66_.ucb$r_fill_67_.ucb$v_ni_prm_src"#endif /* #if !defined(__VAXC) */   $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __UCBNIDEF_LOADED */ wwR[UfWUCBDEFVXUCBNIDEFXUNCDEFXFUQBDEFXdUTCDEFXVCADEFXBVCBDEFJYVCCDEFY<VCIBDEFYr VCIBDLLDEFVCONS_ROUTINESY:VCRPDEFZT VCRPLANDEF:ZrVECDEFBZVL1DEFKZVL2DEFRZ VLANDATADEF[ZVLANDEFkZ`VLEDEFtZVVMS$DEFSL VMS_CONSOLE VMS_DRIVERS^ VMS_MACROSF VMS_RANDOMtZ~VSLDEF|Z.WBMDEFZFWCBDEFZWQHDEFZPWSLDEF [lX86HWDEFk[X X86MSRDEFX86_CPUID_INFO YMF262_REGXM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright HewXlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. X **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Source: 15-DEC-2000 09:43:54 $1$DGA8345:[LIB_H.SRC]UNCDEF.SDL;1 *//*********************************************** X*********************************************************************************//*** MODULE $UNCDEF ***/#ifndef __UNCDEF_LOADED#define __UNCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pXointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#e Xndif N/* */N/* UNCHDRDEF - Universal Context Segment Header Definition */N/* */N#define UNC$C_JPI 1 /* JPI context segment (not used) */N#define UNC$C_UAI 2 /* UAI context segment */N#define UNC$C_AUDIT_EVENT 3 /* AUDIT_EVENT context segment */O#define UNC$C_OBXJECT 4 /* Object management context segment */N#define UNC$C_ORB_FIXUP 5 /* Writeback ORB after boot fixup */N#define UNC$C_OBJECT_SERVICE 6 /* Object service request context */N#define UNC$C_HDR_LENGTH 16 /* size of context segment header */N#define UNC$K_HDR_LENGTH 16 /* size of context segment header */N#define UNC$C_LIST 16 /* offset to first context block */N#define UNC$K_LIST 16 X/* offset to first context block */N#define UNC$S_UNCHDRDEF 16 /* Old size name - synonym */ typedef struct _unchdr {R struct _unchdr *unc$l_flink; /* forward link to next context segment */S struct _unchdr *unc$l_blink; /* back link to previous context segment */N unsigned short int unc$w_size; /* total size of context segment */N unsigned char unc$b_type; /* VMS type of block (DYN$C_UNC) */N unsigned char unc$b_su Xbtype; /* type of context segment */Q unsigned short int unc$w_count; /* number of context blocks in segment */N unsigned short int unc$w_free_count; /* number of entries free for use */#if defined(__VAXC) char unc$r_list[];#elseQ/* Warning: empty char[] member for unc$r_list at end of structure not created */"#endif /* #if defined(__VAXC) */ } UNCHDR;N/* */N/* Universal Conte Xxt Block Definition (Go Heels!) */N/* */#define UNC$M_ENTRY_INUSE 0x1#define UNC$M_NEW_ENTRY 0x2#define UNC$M_MBX_NORSWAIT 0x4N#define UNC$C_LENGTH 84 /* size of largest context block */N#define UNC$K_LENGTH 84 /* size of largest context block */N#define UNC$C_SEGMENTS 5 /* natural number of segments/page */N#define UNC$K_SEGMENTS 5 X /* natural number of segments/page */N#define UNC$S_UNCDEF 84 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _iosb; struct _ocb; struct _orb; #endif /* #ifdef __cplusplus */ typedef struct _unc { __union {N unsigned short int unc$w_flags; /* context cell flags */ __struct {N unsigned unc$v_entry_inuse : 1; /* context entry inuse */N X unsigned unc$v_new_entry : 1; /* Newly created entry */N unsigned unc$v_mbx_norswait : 1; /* Return on resource failure */' unsigned unc$v_fill_2_ : 5; } unc$r_fill_1_; } unc$r_fill_0_;N unsigned char unc$b_access_mode; /* access mode of context cell */" unsigned char unc$b_unused_b1;O unsigned int unc$l_image_count; /* IMGCNT when context cell assigned */ __union { __struct {N unsiXgned short int unc$w_uai_ifi; /* FAB$W_IFI */N unsigned short int unc$w_uai_isi; /* RAB$W_ISI */N unsigned short int unc$w_uai_channel; /* UAF channel */ } unc$r_uai_context; __struct {N struct _iosb *unc$l_ae_iosb; /* IOSB address */N void (*unc$l_ae_astadr)(); /* AST address */N unsigned int unc$l_ae_astprm; /* AST parameter X */N unsigned short int unc$w_ae_efn; /* EFN number */N unsigned short int unc$w_ae_channel; /* reply mailbox channel */N unsigned int unc$l_ae_flags; /* $AUDIT_EVENT flags */N unsigned int unc$l_ae_reply; /* audit server reply status */N __struct { /* IOSB for $AUDIT_EVENT */n unsigned short int unc$w_ae_qio_status; /* status from $AUDIT_EVENT's $QIO t Xo reply mailbox */. short int unc$w_unused_w2 [3];$ } unc$r_ae_our_iosb;O unsigned char unc$b_ae_prvmod; /* mode to deliver completion AST */% char unc$b_unused_b2 [3];( } unc$r_audit_event_context; __struct {N unsigned int unc$l_so_context; /* Value of this context block */S struct _unc *unc$l_so_context_ptr; /* Address of user's context cell */N unsigned int unc$l_so_acl_position; X/* Position in the ACL */N unsigned int unc$l_so_lockid; /* Lock ID for write lock on ORB */O unsigned int unc$l_so_parent_id; /* Parent lock ID for SO_LOCKID */U unsigned int unc$l_so_osr_flags; /* OSR processing flags (see $OSRDEF) */N struct _ocb *unc$l_so_ocb; /* Object Class Block address */N struct _orb *unc$l_so_orb; /* Address of the ORB */N void *unc$l_so_object_handle; /* Object handle addreXss */N/* */N/* OBJNAM_LENGTH and OBJNAM */N/* must form an string */N/* descriptor */N/* */P unsigned short int unc$w_so_objnam_length; /* Size of object name */N X unsigned short int unc$w_so_reserved_1; /* Reserved (MBZ) */N void *unc$l_so_objnam; /* Object name buffer address */N/* */X unsigned short int unc$w_so_objnam_bufsiz; /* Size of objnam buffer alloc */N unsigned char unc$b_so_acmode; /* Access mode */N unsigned char unc$b_so_reserved_2; /* Reserved for digital use */N int (*unc$l_Xso_aclctx_ptr)(); /* Context return address */N unsigned int unc$l_so_reserved_3; /* Reserved for digital use */N unsigned int unc$l_so_reserved_4; /* Reserved for digital use */U char unc$t_so_osr_context [16]; /* Object Support Routine context area */# } unc$r_object_context; __struct {N void (*unc$l_of_astadr)(); /* AST address */N unsigned int unc$l_of_astprm; /* AST parameter X */N unsigned int unc$l_of_flags; /* flags (object specific) */N __struct { /* IOSB for $AUDIT_EVENT */N unsigned short int unc$w_of_status; /* completion status */1 short int unc$w_of_unused_w2 [3];$ } unc$r_of_our_iosb;O unsigned char unc$b_of_prvmod; /* mode to deliver completion AST */( char unc$b_of_unused_b2 [3];N unsigned int unc$l_of_Xobject; /* context for locating the */N unsigned int unc$l_of_object1; /* next object profile */N unsigned int unc$l_of_object2; /* (object specific) */N unsigned int unc$l_of_object3; /* */& } unc$r_orb_fixup_context; __struct {N void (*unc$l_os_astadr)(); /* AST address */N unsigned int unc$l_os_astprm; /* AST parameter */XN unsigned int unc$l_os_flags; /* flags (object specific) */R unsigned short int unc$w_os_repl_chan; /* mailbox channel for reply */T unsigned short int unc$w_os_rqst_chan; /* mailbox channel for request */N __struct { /* IOSB for $QIO */N unsigned short int unc$w_os_status; /* completion status */1 short int unc$w_os_unused_w2 [3]; } unc$r_os_iosb;O X unsigned char unc$b_os_prvmod; /* mode to deliver completion AST */( char unc$b_os_unused_b2 [3];N unsigned int unc$l_os_object; /* context for locating the */N unsigned int unc$l_os_object1; /* next object profile */N unsigned int unc$l_os_object2; /* (object specific) */N unsigned int unc$l_os_object3; /* */+ } unc$r_object_service_context; } unc$r_context_ Xoverlay; } UNC; #if !defined(__VAXC)-#define unc$w_flags unc$r_fill_0_.unc$w_flagsG#define unc$v_entry_inuse unc$r_fill_0_.unc$r_fill_1_.unc$v_entry_inuseC#define unc$v_new_entry unc$r_fill_0_.unc$r_fill_1_.unc$v_new_entryI#define unc$v_mbx_norswait unc$r_fill_0_.unc$r_fill_1_.unc$v_mbx_norswaitK#define unc$w_uai_ifi unc$r_context_overlay.unc$r_uai_context.unc$w_uai_ifiK#define unc$w_uai_isi unc$r_context_overlay.unc$r_uai_context.unc$w_uai_isiS#define unc$w_uai_channel unc$r_coXntext_overlay.unc$r_uai_context.unc$w_uai_channelS#define unc$l_ae_iosb unc$r_context_overlay.unc$r_audit_event_context.unc$l_ae_iosbW#define unc$l_ae_astadr unc$r_context_overlay.unc$r_audit_event_context.unc$l_ae_astadrW#define unc$l_ae_astprm unc$r_context_overlay.unc$r_audit_event_context.unc$l_ae_astprmQ#define unc$w_ae_efn unc$r_context_overlay.unc$r_audit_event_context.unc$w_ae_efnY#define unc$w_ae_channel unc$r_context_overlay.unc$r_audit_event_context.unc$w_ae_channelU#define unc$Xl_ae_flags unc$r_context_overlay.unc$r_audit_event_context.unc$l_ae_flagsU#define unc$l_ae_reply unc$r_context_overlay.unc$r_audit_event_context.unc$l_ae_replyq#define unc$w_ae_qio_status unc$r_context_overlay.unc$r_audit_event_context.unc$r_ae_our_iosb.unc$w_ae_qio_statusW#define unc$b_ae_prvmod unc$r_context_overlay.unc$r_audit_event_context.unc$b_ae_prvmodT#define unc$l_so_context unc$r_context_overlay.unc$r_object_context.unc$l_so_context\#define unc$l_so_context_ptr unc$r_context_overlayX.unc$r_object_context.unc$l_so_context_ptr^#define unc$l_so_acl_position unc$r_context_overlay.unc$r_object_context.unc$l_so_acl_positionR#define unc$l_so_lockid unc$r_context_overlay.unc$r_object_context.unc$l_so_lockidX#define unc$l_so_parent_id unc$r_context_overlay.unc$r_object_context.unc$l_so_parent_idX#define unc$l_so_osr_flags unc$r_context_overlay.unc$r_object_context.unc$l_so_osr_flagsL#define unc$l_so_ocb unc$r_context_overlay.unc$r_object_context.unc$l_so_ocbL#define unc$l_so_orb uncX$r_context_overlay.unc$r_object_context.unc$l_so_orb`#define unc$l_so_object_handle unc$r_context_overlay.unc$r_object_context.unc$l_so_object_handle`#define unc$w_so_objnam_length unc$r_context_overlay.unc$r_object_context.unc$w_so_objnam_lengthZ#define unc$w_so_reserved_1 unc$r_context_overlay.unc$r_object_context.unc$w_so_reserved_1R#define unc$l_so_objnam unc$r_context_overlay.unc$r_object_context.unc$l_so_objnam`#define unc$w_so_objnam_bufsiz unc$r_context_overlay.unc$r_object_context.unc$w_Xso_objnam_bufsizR#define unc$b_so_acmode unc$r_context_overlay.unc$r_object_context.unc$b_so_acmodeZ#define unc$b_so_reserved_2 unc$r_context_overlay.unc$r_object_context.unc$b_so_reserved_2Z#define unc$l_so_aclctx_ptr unc$r_context_overlay.unc$r_object_context.unc$l_so_aclctx_ptrZ#define unc$l_so_reserved_3 unc$r_context_overlay.unc$r_object_context.unc$l_so_reserved_3Z#define unc$l_so_reserved_4 unc$r_context_overlay.unc$r_object_context.unc$l_so_reserved_4\#define unc$t_so_osr_context unc$r_cXontext_overlay.unc$r_object_context.unc$t_so_osr_contextU#define unc$l_of_astadr unc$r_context_overlay.unc$r_orb_fixup_context.unc$l_of_astadrU#define unc$l_of_astprm unc$r_context_overlay.unc$r_orb_fixup_context.unc$l_of_astprmS#define unc$l_of_flags unc$r_context_overlay.unc$r_orb_fixup_context.unc$l_of_flagsg#define unc$w_of_status unc$r_context_overlay.unc$r_orb_fixup_context.unc$r_of_our_iosb.unc$w_of_statusU#define unc$b_of_prvmod unc$r_context_overlay.unc$r_orb_fixup_context.unc$b_of_pXrvmodU#define unc$l_of_object unc$r_context_overlay.unc$r_orb_fixup_context.unc$l_of_objectW#define unc$l_of_object1 unc$r_context_overlay.unc$r_orb_fixup_context.unc$l_of_object1W#define unc$l_of_object2 unc$r_context_overlay.unc$r_orb_fixup_context.unc$l_of_object2W#define unc$l_of_object3 unc$r_context_overlay.unc$r_orb_fixup_context.unc$l_of_object3Z#define unc$l_os_astadr unc$r_context_overlay.unc$r_object_service_context.unc$l_os_astadrZ#define unc$l_os_astprm unc$r_context_overlay.unXc$r_object_service_context.unc$l_os_astprmX#define unc$l_os_flags unc$r_context_overlay.unc$r_object_service_context.unc$l_os_flags`#define unc$w_os_repl_chan unc$r_context_overlay.unc$r_object_service_context.unc$w_os_repl_chan`#define unc$w_os_rqst_chan unc$r_context_overlay.unc$r_object_service_context.unc$w_os_rqst_chanV#define unc$r_os_iosb unc$r_context_overlay.unc$r_object_service_context.unc$r_os_iosb5#define unc$w_os_status unc$r_os_iosb.unc$w_os_statusZ#define unc$b_os_prvmod unc$r_coXntext_overlay.unc$r_object_service_context.unc$b_os_prvmodZ#define unc$l_os_object unc$r_context_overlay.unc$r_object_service_context.unc$l_os_object\#define unc$l_os_object1 unc$r_context_overlay.unc$r_object_service_context.unc$l_os_object1\#define unc$l_os_object2 unc$r_context_overlay.unc$r_object_service_context.unc$l_os_object2\#define unc$l_os_object3 unc$r_context_overlay.unc$r_object_service_context.unc$l_os_object3"#endif /* #if !defined(__VAXC) */ N/* X */N/* Object management Context cell layout */N/* */N#define OBJCTX$S_CTXDEF 8 /* Old size name - synonym */ typedef struct _objctx {N unsigned int objctx$l_index; /* Index in table */N unsigned int objctx$l_seq; /* Sequence number */ } OBJCTX; $#pragma X__member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __UNCDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPXE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTXIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/********************************************************* X******************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Source: 28-NOV-2016 15:12:11 $1$DGA8345:[LIB_H.SRC]UQBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $UQBDEF ***/#ifndef __UQBDEF_LOADED#define __UQBDEF_LOADED 1 G X#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optiXonal_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* UQB (Unit Queue Block) Definitions -- MSCP Server, TMSCP Server */ XN/* */I/* This data structure has all the information pertaining */I/* to a unit that is currently being served. It is most used */I/* for the list head of all requests for this unit. */N/*- */ #define UQB$M_SEQ 0x1#define UQB$M_WRTPH 0x2#define UQB$M_WRTPS 0x4#define UQB$M_ONLINE 0x8#define UQXB$M_FLUSH 0x10#define UQB$M_DUNN 0x20#define UQB$M_DSE 0x40#define UQB$M_C 0x1F#define UQB$M_D1 0x3E0#define UQB$M_D0 0x7C00N#define UQB$K_ST_ONLINE 2 /* Unit is online to some host */N#define UQB$K_ST_OFFLINE 3 /* Unit is offline */N#define UQB$K_ST_AVAILABLE 4 /* Unit is available */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb; struct _hrb; #endif /* #ifdef __cplusplus */ X c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _uqb {#pragma __nomember_alignmentN struct _uqb *uqb$l_flink; /* Used to link together all */N struct _uqb *uqb$l_blink; /* UQBs being served */N unsigned short int uqb$w_size; /* Structure size in bytes */N unsigned cha Xr uqb$b_type; /* MSCP type structure */N unsigned char uqb$b_subtype; /* with a UQB subtype (5) */N unsigned short int uqb$w_state; /* Current state of this unit */ __union {N unsigned short int uqb$w_flags; /* Unit usage */ __struct {N unsigned uqb$v_seq : 1; /* Sequential command executing */N unsigned uqb$v_wrtph : 1; /* Unit is writelocked */N X unsigned uqb$v_wrtps : 1; /* Unit was mounted /NOWRITE */N unsigned uqb$v_online : 1; /* Unit is ONLINE. */N unsigned uqb$v_flush : 1; /* Per-unit cache is being flushed */N unsigned uqb$v_dunn : 1; /* Device uses new naming */P unsigned uqb$v_dse : 1; /* Device implements IO$_DSE function */' unsigned uqb$v_fill_6_ : 1; } uqb$r_fill_1_; } uqb$r_fill_0_;N unsignXed short int uqb$w_old_unit; /* "Old Style" unit number */N unsigned short int uqb$w_current; /* Commands active on this unit */N unsigned short int uqb$w_mult_unit; /* This information is set up */N unsigned short int uqb$w_unit_flags; /* in ADDUNIT when the device */ __union {N unsigned __int64 uqb$q_unit_id; /* is set /SERVED. */ __struct {N unsigned int uqb$l_allocls; /* The unit identifier is made up */XO unsigned short int uqb$w_unit; /* of the allocation class, the */ __union {N unsigned short int uqb$w_devname; /* */ __struct {Q unsigned uqb$v_c : 5; /* UCB unit number, the controller */O unsigned uqb$v_d1 : 5; /* letter, and the D1 D0 fields */N unsigned uqb$v_d0 : 5; /* from the media ID field *// unsigned uqb$v_fill_7_ X : 1;$ } uqb$r_fill_5_; } uqb$r_fill_4_; } uqb$r_fill_3_; } uqb$r_fill_2_;N unsigned int uqb$l_reserved; /* */N struct _ucb *uqb$l_ucb; /* UCB address for this unit */N unsigned short int uqb$w_num_que; /* Host requests pending */N unsigned short int uqb$w_max_que; /* Most requests ever pending */N struct _hrb *uqb$l_blocked_fl; /* List heXad for HRBs pending */N struct _hrb *uqb$l_blocked_bl; /* sequential cmd completion */N unsigned char uqb$b_online [32]; /* Array of hosts with unit online */N unsigned int uqb$l_extra_io; /* Splinter requests */N unsigned int uqb$l_iocnt; /* Server contribution to total */N unsigned short int uqb$w_qlen; /* Server queue length for unit */N unsigned short int uqb$w_slun; /* Server local unit number X*/N/* max chars in Cluster unique */N/* device name ( dependency in */N/* PEDRIVER's PEM_DEF.SDL) */N unsigned char uqb$b_unique_dname_cnt; /* .ASCIC string with */N char uqb$t_unique_dname [15]; /* Cluster unique name for disk */N/* unit (obtained VIA GETDVI */N/* ALLDEVNAM item) X */ N/* Unit state definitions */ } UQB; #if !defined(__VAXC)-#define uqb$w_flags uqb$r_fill_0_.uqb$w_flags7#define uqb$v_seq uqb$r_fill_0_.uqb$r_fill_1_.uqb$v_seq;#define uqb$v_wrtph uqb$r_fill_0_.uqb$r_fill_1_.uqb$v_wrtph;#define uqb$v_wrtps uqb$r_fill_0_.uqb$r_fill_1_.uqb$v_wrtps=#define uqb$v_online uqb$r_fill_0_.uqb$r_fill_1_.uqb$v_online;#define uqb$v_flush uqb$r_fill_0 X_.uqb$r_fill_1_.uqb$v_flush9#define uqb$v_dunn uqb$r_fill_0_.uqb$r_fill_1_.uqb$v_dunn7#define uqb$v_dse uqb$r_fill_0_.uqb$r_fill_1_.uqb$v_dse1#define uqb$q_unit_id uqb$r_fill_2_.uqb$q_unit_id?#define uqb$l_allocls uqb$r_fill_2_.uqb$r_fill_3_.uqb$l_allocls9#define uqb$w_unit uqb$r_fill_2_.uqb$r_fill_3_.uqb$w_unitM#define uqb$w_devname uqb$r_fill_2_.uqb$r_fill_3_.uqb$r_fill_4_.uqb$w_devnameO#define uqb$v_c uqb$r_fill_2_.uqb$r_fill_3_.uqb$r_fill_4_.uqb$r_fill_5_.uqb$v_cQ#define uqb$v_d1 uXqb$r_fill_2_.uqb$r_fill_3_.uqb$r_fill_4_.uqb$r_fill_5_.uqb$v_d1Q#define uqb$v_d0 uqb$r_fill_2_.uqb$r_fill_3_.uqb$r_fill_4_.uqb$r_fill_5_.uqb$v_d0"#endif /* #if !defined(__VAXC) */ #define UQB$M_ST_BOT 0x1#define UQB$M_ST_DLS 0x2#define UQB$M_ST_EOT 0x4#define UQB$M_ST_LEOT 0x8#define UQB$M_ST_PLS 0x10#define UQB$M_ST_SEREX 0x20#define UQB$M_ST_WRTPH 0x40  9#ifdef __cplusplus /* Define structure prototypes */ struct _hqb; struct _hrb; #endif /* #ifdef __cplusp Xlus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif typedef struct _tsrv_extension {#pragma __nomember_alignment UQB uqb$r_basic_uqb;N struct _hqb *uqb$l_online_hqb; /* Unit is excl. onl. to this host. */N unsigned int uqb$l_memw_tot; /* Number of I/Os that had to wait. */N struct _hrb *uqb$l_memw_fl; /* Queue listhXead for requests */N struct _hrb *uqb$l_memw_bl; /* in memory wait state. */N unsigned short int uqb$w_memw_cnt; /* Current memory stalls. */N unsigned short int uqb$w_memw_max; /* Most requests ever in MEMWAIT */N struct _hrb *uqb$l_cache_fl; /* Queue listhead for requests */N struct _hrb *uqb$l_cache_bl; /* in server cache. */N unsigned short int uqb$w_num_cache; /* Number of requests in cache. */NX unsigned short int uqb$w_max_cache; /* Max ever cached */N void *uqb$l_freelist_fl; /* Queue listhead for available */N void *uqb$l_freelist_bl; /* local buffers */N unsigned short int uqb$w_buff_avail; /* Number of free buffers */N unsigned short int uqb$w_max_buff_avail; /* Max ever of free buffers */N unsigned short int uqb$w_buff_alloc; /* Number of allocated buffers */O unsigned short int uqbX$w_max_buff_alloc; /* Max number of buffers alloc. */N unsigned int uqb$l_serv_rspid; /* Last RSPID checked in GCS */N unsigned int uqb$l_class_rspid; /* Last class driver RSPID */N unsigned int uqb$l_old_clssts; /* Class driver command status. */N unsigned short int uqb$w_tapem_skip; /* Storage for REPOS. OBJECT */N unsigned short int uqb$w_record_skip; /* Storage for REPOS. OBJECT */N unsigned int uqb$l_startstop; /* Start/sXtop time for drive */N unsigned int uqb$l_io_time; /* Cycle time of IO to local drive */N unsigned short int uqb$w_num_io; /* Number of IOs issued to drive */N unsigned short int uqb$w_max_io; /* Max num of IOs outstanding to */N/* to drive */N unsigned int uqb$l_arr_time; /* Average time it takes the host */N/* to respond to a request and X*/N/* send the next request out. */N unsigned short int uqb$w_num_flush; /* Number of flush commands. */O unsigned short int uqb$w_max_num_flush; /* Max number of flush commands. */N unsigned int uqb$l_position; /* Unit's current position */ __union {N unsigned short int uqb$w_st_flags; /* Unit usage */ __struct {N unsigned uqb$v_st_bot : 1; /* BOT X */N unsigned uqb$v_st_dls : 1; /* Cached data lost */N unsigned uqb$v_st_eot : 1; /* End of tape */N unsigned uqb$v_st_leot : 1; /* Logical end of tape */N unsigned uqb$v_st_pls : 1; /* Position lost */N unsigned uqb$v_st_serex : 1; /* Serious exception state */N unsigned uqb$v_st_wrtph : 1; /* Write protected */( X unsigned uqb$v_fill_10_ : 1; } uqb$r_fill_9_; } uqb$r_fill_8_; char uqb$b_fill_11_ [6]; } TSRV_EXTENSION; #if !defined(__VAXC)3#define uqb$w_st_flags uqb$r_fill_8_.uqb$w_st_flags=#define uqb$v_st_bot uqb$r_fill_8_.uqb$r_fill_9_.uqb$v_st_bot=#define uqb$v_st_dls uqb$r_fill_8_.uqb$r_fill_9_.uqb$v_st_dls=#define uqb$v_st_eot uqb$r_fill_8_.uqb$r_fill_9_.uqb$v_st_eot?#define uqb$v_st_leot uqb$r_fill_8_.uqb$r_fill_9_.uqb$v_st_leot=#define uqb$v_st_pls uqb X$r_fill_8_.uqb$r_fill_9_.uqb$v_st_plsA#define uqb$v_st_serex uqb$r_fill_8_.uqb$r_fill_9_.uqb$v_st_serexA#define uqb$v_st_wrtph uqb$r_fill_8_.uqb$r_fill_9_.uqb$v_st_wrtph"#endif /* #if !defined(__VAXC) */ #define UQB$C_LENGTH 208#define UQB$K_LENGTH 208 $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdXef __cplusplus }#endif#pragma __standard #endif /* __UQBDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without theX **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior writXten permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Sourc Xe: 30-MAY-1995 14:26:02 $1$DGA8345:[LIB_H.SRC]UTCDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $UTCDEF ***/#ifndef __UTCDEF_LOADED#define __UTCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pXragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #i Xfndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* $UTCDEF defines the storage format for UTC based times. */N/* */N/*- X */#define UTC$M_TDF 0xFFF#define UTC$M_VER 0xF000N#define UTC$S_UTCDEF 16 /* Old size name - synonym */ typedef struct _utc { __union { __struct {P __int64 utc$a_whole_time [2]; /* Double quad to fetch entire time */ } utc$r_utcdef_wtim; __struct {N unsigned __int64 utc$q_abstime; /* 64 bit system time */N/* In units of 100ns ticks X */N unsigned __int64 utc$q_tdf_etc; /* Inaccuracy, TDF, and version */! } utc$r_utcdef_quad0; __struct {N unsigned int utc$l_abs0; /* Least sig 4 bytes of binary time */N unsigned int utc$l_abs1; /* Most sig 4 bytes of binary time */N unsigned int utc$l_inac; /* 4 least sig bytes of inaccuracy */N unsigned int utc$l_tdfv; /* 4 bits vers, 12 bits TDF, 2 */N/* most sig bytes of inaccuracy X */! } utc$r_utcdef_long0; __struct {N __int64 utc$q_fill_1; /* Overlay filler */N char utc$a_inaccur [6]; /* Six bytes of inaccuracy */N/* In units of 100ns ticks */ __union { __struct {Y unsigned short int utc$w_tdfwrd; /* Fetch the TDF and the version */* } ut Xc$r_utcdef_tdfwrd; __struct {V unsigned utc$v_tdf : 12; /* 12 bits of offset from UTC to local */N/* In units of minutes */N unsigned utc$v_ver : 4; /* Unsigned version number */+ } utc$r_utcdef_tdfbit1;' } utc$r_utcdef_tdfbit0; } utc$r_utcdef_fld0; } utc$r_utcdef_time; } UTC; #if !defined(__VAXC)M#define utc$a_wholXe_time utc$r_utcdef_time.utc$r_utcdef_wtim.utc$a_whole_timeH#define utc$q_abstime utc$r_utcdef_time.utc$r_utcdef_quad0.utc$q_abstimeH#define utc$q_tdf_etc utc$r_utcdef_time.utc$r_utcdef_quad0.utc$q_tdf_etcB#define utc$l_abs0 utc$r_utcdef_time.utc$r_utcdef_long0.utc$l_abs0B#define utc$l_abs1 utc$r_utcdef_time.utc$r_utcdef_long0.utc$l_abs1B#define utc$l_inac utc$r_utcdef_time.utc$r_utcdef_long0.utc$l_inacB#define utc$l_tdfv utc$r_utcdef_time.utc$r_utcdef_long0.utc$l_tdfvG#define utc$a_inaccur ut Xc$r_utcdef_time.utc$r_utcdef_fld0.utc$a_inaccurn#define utc$w_tdfwrd utc$r_utcdef_time.utc$r_utcdef_fld0.utc$r_utcdef_tdfbit0.utc$r_utcdef_tdfwrd.utc$w_tdfwrdi#define utc$v_tdf utc$r_utcdef_time.utc$r_utcdef_fld0.utc$r_utcdef_tdfbit0.utc$r_utcdef_tdfbit1.utc$v_tdfi#define utc$v_ver utc$r_utcdef_time.utc$r_utcdef_fld0.utc$r_utcdef_tdfbit0.utc$r_utcdef_tdfbit1.utc$v_ver"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whXenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __UTCDEF_LOADED */ ww<[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/*X* licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licXensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//***************************************************** X***************************************************************************/=/* Created: 7-Oct-2024 15:22:32 by OpenVMS SDL V3.7 */F/* Source: 28-JUN-1993 14:52:47 $1$DGA8345:[LIB_H.SRC]VCADEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $VCADEF ***/#ifndef __VCADEF_LOADED#define __VCADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pXragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_paramXs ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* */N/* VCA - Volume Cache Block. This block contains the specialized caches foXr */O/* a disk volume; to wit, the file ID cache, the extent cache, and the quota */O/* file cache. The file ID cache and extent cache are together in one block; */Q/* the quota cache is located separately in another block. Both are pointed to */N/* by the VCB. */N/* */N/*- */P/***********X***************************************************************** */P/* WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! * */P/**************************************************************************** */P/* If you add/remove fields *before* SER_QFL then be sure to realign SER_QFL* */P/* to be QUADWORD aligned. The danger area is between *##### * */P/* * */P/* Also, *DO NOT* insert a Xny fields between SER_QFL and SER_QBL * */P/* * */P/**************************************************************************** */P/* WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! * */P/**************************************************************************** */ #define VCA$M_FIDC_VALID 0x1#define VCA$M_EXTC_VALID 0x2#define VCA$M_FIDC_FLUSH 0x4#define VCA$M_EXTC_FLUSH 0x8XN#define VCA$C_QUEUE 16 /* Offset of queue header */N#define VCA$K_LENGTH 24 /* length of block header */N#define VCA$C_LENGTH 24 /* length of block header */N#define VCA$S_VCADEF 24 /* Old size name - synonym */N/* */ typedef struct _vca {N/* X*/N/* Be careful between here.......... */N/* ################################################## */N/* */N void *vca$l_fidcache; /* pointer to file ID cache */N void *vca$l_extcache; /* pointer to extent cache */N unsigned short int vca$w_size; /* block size */N unsigned char vca$ Xb_type; /* block type code */ __union {N char vca$b_flags; /* cache flags */ __struct {N unsigned vca$v_fidc_valid : 1; /* FID cache valid */N unsigned vca$v_extc_valid : 1; /* Extent cache valid */N unsigned vca$v_fidc_flush : 1; /* FID cache to be flushed */N unsigned vca$v_extc_flush : 1; /* Extent cache to be flushed */' X unsigned vca$v_fill_2_ : 4; } vca$r_fill_1_; } vca$r_fill_0_;P int vca$l_cache_space_used; /* Amount of space consumed/released */N void *vca$l_ser_qfl; /* Extent/FID cache */N void *vca$l_ser_qbl; /* serialization queue header */N/* */N/* .........and here */N/* ############# X##################################### */N/* */N/* The file ID cache consists of the cache header, followed by a longword */N/* vector of file numbers, densely packed. */N/* */ } VCA; #if !defined(__VAXC)-#define vca$b_flags vca$r_fill_0_.vca$b_flagsE#define vca$v_fidc_valid vca$r_fill_ X0_.vca$r_fill_1_.vca$v_fidc_validE#define vca$v_extc_valid vca$r_fill_0_.vca$r_fill_1_.vca$v_extc_validE#define vca$v_fidc_flush vca$r_fill_0_.vca$r_fill_1_.vca$v_fidc_flushE#define vca$v_extc_flush vca$r_fill_0_.vca$r_fill_1_.vca$v_extc_flush"#endif /* #if !defined(__VAXC) */ N#define VCA$S_VCADEF1 52 /* Old size name - synonym */ typedef struct _vca1 {N unsigned int vca$l_fidsize; /* number of entries allocated */N unsigned int vca$l_fidXcount; /* number of entries present */N unsigned int vca$l_fidclkid; /* FID cache lock id. */N unsigned char vca$b_fidcacb [36]; /* FID cache blocking ACB */N void *vca$l_fidlist; /* first entry in list */N/* */N/* The extent cache consists of the cache header, followed by a quadword */N/* vector of extents, densely packed. Each quadword Xcontains block count */N/* and starting LBN. */N/* */ } VCA1;N#define VCA$S_VCADEF2 64 /* Old size name - synonym */ typedef struct _vca2 {N unsigned int vca$l_extsize; /* number of entries allocated */N unsigned int vca$l_extcount; /* number of entries present */X unsigned int vca$l_exttotal; X /* total number of blocks contained in cache */Z unsigned int vca$l_extlimit; /* limit of volume to be cached, in percent/10 */N unsigned int vca$l_extclkid; /* EXT cache lock id. */N unsigned char vca$b_extcacb [36]; /* Extent cache blocking ACB. */N unsigned __int64 vca$q_extlist; /* first entry in list */ } VCA2;N#define VCA$S_VCADEF3 8 /* Old size name - synonym */ typedef struct _vca3 {XN unsigned int vca$l_extblocks; /* number of blocks */N unsigned int vca$l_extlbn; /* starting LBN */N/* */N/* The quota cache consists of the cache header, followed by the cache */N/* entries. Each cache entry is a block as defined below. */N/* */ } VCA3;#define VC XA$M_CACHEVALID 0x1#define VCA$M_CACHEFLUSH 0x2N#define VCA$S_VCADEF4 92 /* Old size name - synonym */ typedef struct _vca4 {N unsigned int vca$l_quosize; /* number of entries allocated */N unsigned int vca$l_quoclkid; /* whole cache lock ID */O char vca$$$_fill_3 [3]; /* 2nd longword & block size & type */ __union {N char vca$b_quocflags; /* cache flags */ __ Xstruct {N unsigned vca$v_cachevalid : 1; /* cache is valid */N unsigned vca$v_cacheflush : 1; /* cache is to be flushed */' unsigned vca$v_fill_5_ : 6; } vca$r_fill_4_; } vca$r_fill_3_;N unsigned int vca$l_quolru; /* current LRU counter */N unsigned char vca$b_quoacb [36]; /* ACB to deliver blocking AST */N unsigned char vca$b_quoflushacb [36]; /* ACB to deliver cache flush AST X*/N void *vca$l_quolist; /* start of entries */ } VCA4; #if !defined(__VAXC)5#define vca$b_quocflags vca$r_fill_3_.vca$b_quocflagsE#define vca$v_cachevalid vca$r_fill_3_.vca$r_fill_4_.vca$v_cachevalidE#define vca$v_cacheflush vca$r_fill_3_.vca$r_fill_4_.vca$v_cacheflush"#endif /* #if !defined(__VAXC) */ #define VCA$M_QUOVALID 0x1#define VCA$M_QUODIRTY 0x2N#define VCA$K_QUOLENGTH 28 /* length of quota cache entry */N#defin Xe VCA$C_QUOLENGTH 28 /* length of quota cache entry */N#define VCA$S_VCADEF5 28 /* Old size name - synonym */ typedef struct _vca5 {N __struct { /* lock status block */ __union {N unsigned short int vca$w_quostatus; /* $ENQ status */Q unsigned short int vca$w_quoindex; /* index in cache of this entry */& } vca$r_quostatus_overlay;N unsigned sho Xrt int vca$w_quolrux; /* LRU index for entry */N unsigned int vca$l_quolkid; /* lock ID of cache entry */N unsigned char vca$l_quorecnum [3]; /* record number */ __union {N unsigned char vca$b_quoflags; /* flags byte */ __struct {N unsigned vca$v_quovalid : 1; /* valid entry is present */N unsigned vca$v_quodirty : 1; /* dirty flag */+ X unsigned vca$v_fill_8_ : 6; } vca$r_fill_7_; } vca$r_fill_6_;N unsigned int vca$l_usage; /* current usage */N unsigned int vca$l_permquota; /* permanent quota */N unsigned int vca$l_overdraft; /* overdraft limit */ } vca$r_quolock;N unsigned int vca$l_quouic; /* UIC */ } VCA5; #if !defined(__VAXC)M#define vcXa$w_quostatus vca$r_quolock.vca$r_quostatus_overlay.vca$w_quostatusK#define vca$w_quoindex vca$r_quolock.vca$r_quostatus_overlay.vca$w_quoindex1#define vca$w_quolrux vca$r_quolock.vca$w_quolrux1#define vca$l_quolkid vca$r_quolock.vca$l_quolkid5#define vca$l_quorecnum vca$r_quolock.vca$l_quorecnumA#define vca$b_quoflags vca$r_quolock.vca$r_fill_6_.vca$b_quoflagsO#define vca$v_quovalid vca$r_quolock.vca$r_fill_6_.vca$r_fill_7_.vca$v_quovalidO#define vca$v_quodirty vca$r_quolock.vca$r_fill_X6_.vca$r_fill_7_.vca$v_quodirty-#define vca$l_usage vca$r_quolock.vca$l_usage5#define vca$l_permquota vca$r_quolock.vca$l_permquota5#define vca$l_overdraft vca$r_quolock.vca$l_overdraft"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#p Xragma __standard #endif /* __VCADEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permissiXon of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, InXc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */F/* Source: 15-JAN-2022 10:50:44 $1$DGA834 X5:[LIB_H.SRC]VCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $VCBDEF ***/#ifndef __VCBDEF_LOADED#define __VCBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __saXve /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXXC)#define __union union#else#define __union variant_union#endif#endif N#define VCB$K_MRKLEN 11 /* Old size name for Mark length */N#define VCB$C_MRKLEN 11 /* Old size name for Mark length */#define VCB$M_WRITE_IF 0x1#define VCB$M_WRITE_SM 0x2#define VCB$M_HOMBLKBAD 0x4#define VCB$M_IDXHDRBAD 0x8#define VCB$M_NOALLOC 0x10#define VCB$M_EXTFID 0x20#define VCB$M_GROUP 0x40#define VCB$M_SYSTEM 0x80#define VCB$M_HIGH_SIERRA 0x1X#define VCB$M_NOSWITCH 0x2#define VCB$M_DSI 0x4#define VCB$M_XAR 0x8#define VCB$M_UNUSED_1 0x10#define VCB$M_UNUSED_2 0x20#define VCB$M_PARTFILE 0x1#define VCB$M_LOGICEOVS 0x2#define VCB$M_WAIMOUVOL 0x4#define VCB$M_WAIREWIND 0x8#define VCB$M_WAIUSRLBL 0x10#define VCB$M_CANCELIO 0x20#define VCB$M_MUSTCLOSE 0x40#define VCB$M_NOWRITE 0x80#define VCB$M_SHADMAST 0x1#define VCB$M_FAILED 0x2#define VCB$M_REBLDNG 0x8#define VCB$M_BLKASTREC 0x10#define VCB$M_MVBEGUN X0x20#define VCB$M_ADDING 0x40#define VCB$M_PACKACKED 0x80#define VCB$M_SUBSYSTEM 0x1#define VCB$M_STRUC_ODS5 0x2#define VCB$M_ACCESSTIMES 0x4#define VCB$M_HARDLINKS 0x8 #define VCB$M_SPECIAL_FILES 0x10N#define VCB$K_COMLEN 264 /* LENGTH OF COMMON AREA */N#define VCB$C_COMLEN 264 /* LENGTH OF COMMON AREA */P#define VCB$S_VCBDEF_COMMON 264 /* OLD LENGTH NAME FOR COMPATABILITY */!#define VCB$M_FILE_ATTRIBUTES 0xF #define XVCB$M_FILE_CONTENTS 0xF0N#define VCB$C_DEFAULT 0 /* use default caching policy */N#define VCB$C_WRITETHROUGH 1 /* use writethrough caching */N#define VCB$C_WRITEBEHIND 2 /* use writebehind caching */"#define VCB$M_FLUSH_ON_CLOSE 0xF00T#define VCB$C_FLUSH 1 /* flush file from cache when file closed */S#define VCB$C_NOFLUSH 2 /* retain file in cache when file closed */,#define VCB$M_CACHING_OPTIONS_MBXZ 0xFFFFF000N#define VCB$K_LENGTH 456 /* LENGTH OF STANDARD VCB */N#define VCB$C_LENGTH 456 /* LENGTH OF STANDARD VCB */O#define VCB$S_VCBDEF_DISKS 456 /* Old length name for compatability */N#define VCB$K_F64_LEN 450 /* length of F64-extended VCB */N#define VCB$C_F64_LEN 450 /* length of F64-extended VCB */O#define VCB$S_VCBDEF_F64 450 /* old length name for compatability */N#define XVCB$K_SHAD_LEN 296 /* Shadow set member VCB length */O#define VCB$S_VCBDEF_SHADOW 296 /* Old length name for compatability */X#define VCB$S_VCBDEF_CDROM 320 /* Old size name, synonym for VCB$S_VCB_CDROM */Y#define VCB$S_VCBDEF2 301 /* Old size name, synonym for VCB$S_VCB_MTAACP */O#define VCB$S_VCBDEF3 32 /* OLD LENGTH NAME FOR COMPATABILITY */  9#ifdef __cplusplus /* Define structure prototypes */ struct _fcb; structX _ucb; struct _aqb; struct _orb; struct _mvl; struct _wcb; struct _acb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _vcb {#pragma __nomember_alignment __union {N struct _fcb *vcb$l_fcbfl; /* FCB listhead forward link */Y void *vcb$l_blockfl; /* or - B Xlocked request listhead forward link */Y struct _ucb *vcb$l_memqfl; /* or - Shadow set members queue forward link */ } vcb$r_forward_link; __union {N struct _fcb *vcb$l_fcbbl; /* FCB listhead backward link */Z void *vcb$l_blockbl; /* or - Blocked request listhead backward link */Z struct _ucb *vcb$l_memqbl; /* or - Shadow set members queue backward link */ } vcb$r_backward_link;N unsigned short int vcb$w X_size; /* Size of VCB in bytes */N unsigned char vcb$b_type; /* structure type of VCB */ __union {N/* */N/* Common fields for file and volume VCBs. Note not all fields in the */N/* common area are valid for all types. */N/* */ __struct { __unXion {N unsigned char vcb$b_status; /* Volume status: */ __struct {V unsigned vcb$v_write_if : 1; /* Index file is write accessed */W unsigned vcb$v_write_sm : 1; /* Storage map is write accessed */T unsigned vcb$v_homblkbad : 1; /* Primary home block is bad */[ unsigned vcb$v_idxhdrbad : 1; /* Primary index file header is bad */h unsigned vXcb$v_noalloc : 1; /* Allocation/deallocation inhibited (bad bitmaps) */V unsigned vcb$v_extfid : 1; /* Volume has 24 bit file numbers */O unsigned vcb$v_group : 1; /* Volume is mounted /group */Q unsigned vcb$v_system : 1; /* Volume is mounted /system */& } vcb$r_disk_bits; __struct {R unsigned vcb$v_high_sierra : 1; /* Volume is High Sierra */\ unYsigned vcb$v_noswitch : 1; /* Disable Automatic Volume Switching */S unsigned vcb$v_dsi : 1; /* Enable protection based on DSI */S unsigned vcb$v_xar : 1; /* Enable protection based on XAR */N unsigned vcb$v_unused_1 : 1; /* Available */N unsigned vcb$v_unused_2 : 1; /* Available *// unsigned vcb$v_fill_0_ : 2;' } vcb$r_cdrom_bits; Y __struct {U unsigned vcb$v_partfile : 1; /* Partial file exists on tape */b unsigned vcb$v_logiceovs : 1; /* Positioned at logical end of volume set */P unsigned vcb$v_waimouvol : 1; /* Wait for volume mount */U unsigned vcb$v_wairewind : 1; /* Wait for rewind completion */N unsigned vcb$v_waiusrlbl : 1; /* Wait for user label */N unsigned vcb$v_cancelio : 1; Y /* Cancel I/O */N unsigned vcb$v_mustclose : 1; /* Must close file */N unsigned vcb$v_nowrite : 1; /* Don't write trailers */& } vcb$r_tape_bits; __struct {[ unsigned vcb$v_shadmast : 1; /* This VCB is for shadow set master */W unsigned vcb$v_failed : 1; /* Member failed out of shadow set */2 unsigned vcb$v_unused_bit : 1;` Y unsigned vcb$v_rebldng : 1; /* Mount verfication rebuilding shadow set */_ unsigned vcb$v_blkastrec : 1; /* Shadowing lock blocking AST received */U unsigned vcb$v_mvbegun : 1; /* Mount verification initiated */S unsigned vcb$v_adding : 1; /* Adding member to shadow set */b unsigned vcb$v_packacked : 1; /* Member PACKACKed during rebuild attempt */( } vcb$r_shadow_bits; Y } vcb$r_volsts;N unsigned int vcb$l_trans; /* VOLUME TRANSACTION COUNT */V void *vcb$l_rvt; /* ADDRESS OF UCB OR RELATIVE VOLUME TABLE */N struct _aqb *vcb$l_aqb; /* ADDRESS OF AQB */N __union { /* Second status longword */+ unsigned int vcb$l_status2;, unsigned char vcb$b_status2;N __struct { /* Disk STATUSY2 usage */] unsigned vcb$v_writethru : 1; /* VOLUME IS TO BE WRITE-THROUGH CACHED */Y unsigned vcb$v_nocache : 1; /* ALL CACHEING IS DISABLED ON VOLUME */] unsigned vcb$v_mountver : 1; /* VOLUME CAN UNDERGO MOUNT VERIFICATION */\ unsigned vcb$v_erase : 1; /* ERASE DATA WHEN BLOCKS REMOVED FROM FILE */^ unsigned vcb$v_nohighwater : 1; /* TURN OFF HIGH-WATER MARKING (D = ON) */N Y unsigned vcb$v_noshare : 1; /* non-shared mount */U unsigned vcb$v_cluslock : 1; /* CLUSTER WIDE LOCKING NECESSARY */N unsigned vcb$v_subset0 : 1; /* ODS-2 SUBSET 0 VOLUME */. } vcb$r_disk_status2_bits;U unsigned char vcb$b_cd_status2; /* CD STATUS2 usage - same as disk */( } vcb$r_status2_overlay;W __union { /* Third status longword - used by disk only *Y/+ unsigned int vcb$l_status3; __struct {T unsigned vcb$v_subsystem : 1; /* PROTECTED SUBSYSTEMS ENABLED */S unsigned vcb$v_struc_ods5 : 1; /* ODS-5 STRUCTURES SUPPORTED */N unsigned vcb$v_accesstimes : 1; /* record access times */b unsigned vcb$v_hardlinks : 1; /* support POSIX hardlinks, rather than alias */b unsigned vcb$v_special_files : 1; /* support special fYiles (symlinks, etc.) */V unsigned vcb$v_noxfccache : 1; /* XFC VOLUME CACHING STATUS BIT */\ unsigned vcb$v_xfc_deposing : 1; /* XFC volume depose in progress bit *// unsigned vcb$v_fill_1_ : 1;. } vcb$r_disk_status3_bits;( } vcb$r_status3_overlay;N __union { /* Volume identifier */N char vcb$t_volname [12]; /* VOLUME LABEL BLANK FILLED */ YO char vcb$t_volidentifier [64]; /* Extended volume identifier */& } vcb$r_volid_overlay;N unsigned __int64 vcb$q_mounttime; /* VOLUME MOUNT TIME */ __union {N unsigned int vcb$l_mcount; /* MOUNT COUNT */\ unsigned int vcb$l_cd_mcount; /* Alternate name used by CDrom file system */' } vcb$r_mcount_overlay;N unsigned int vcb$l_rvn; /* RELATIVE VOLUME NUM YBER */N struct _orb *vcb$l_orb; /* Pointer to the volume's ORB */N int vcb$l_fill_00 [1]; /* Quadword alignment */N unsigned int vcb$l_reads; /* Total count of read I/Os */N unsigned int vcb$l_writes; /* Total count of write I/Os */P unsigned __int64 vcb$q_readbytes; /* Count of read bytes for I/Os */R unsigned __int64 vcb$q_writebytes; /* Count of write bytes for I/Os */N  Y unsigned int vcb$l_split_io; /* Total count of split I/Os */X unsigned int vcb$l_assist_io; /* Total count of file system assisted I/Os */R unsigned int vcb$l_serialnum; /* VOLUME SERIAL NUMBER (DISKS ONLY) */N unsigned int vcb$l_vollkid; /* VOLUME LOCK ID */N unsigned int vcb$l_cluster; /* VOLUME CLUSTER SIZE */N unsigned int vcb$l_recordsz; /* NUMBER OF BYTES IN A RECORD */R in Yt vcb$l_fill_01 [8]; /* Common space reserved for future use */N/* and align to quadword */N/* */N/* Files-11 A & B Volume Control Block Fields */I/* (ODS-I & ODS-II ) */N/* Note we are still in the common area of the VCB (also note that some */N/* of the preceding fields are also File Ys-11 related). Problem is the */N/* usage of fields is not clear-cut; some fields are also applicable to */N/* other file systems (present and future). Also, the CDrom ACP overlays */N/* a number Files-11 fields with its own equivalent, but differently named, */N/* fields. Rather than leave these fields in the file system specific VCB */N/* and trust to luck with the overlays, we have chosen to turn the overlays */N/* into proper unions. Y */N/* */N/* Note LBN and volume size related fields have been promoted to quadwords. */N/* ODS-II/V will never support volumes larger than 1TB; the promotions are */N/* in anticipation of a new file system that will use the VCB in common. */ __union {\ unsigned __int64 vcb$q_retainmin; /* MINIMUM FILE RETENTION PERIOD (DISK) */Z unsigned __int64 vcb$q_exp_date; /* DE YFAULT FILE EXPIRATION DATE (TAPE) */* } vcb$r_retainmin_overlay;R unsigned __int64 vcb$q_retainmax; /* MAXIMUM FILE RETENTION PERIOD */f/* The following fields are overlaid with equivalent but differently named fields in the CDrom VCB. */N __union { /* NUMBER OF FREE BLOCKS ON VOLUME */( unsigned int vcb$l_free;, unsigned __int64 vcb$q_free;+ unsigned int vcb$l_cd_free;/ unsign Yed __int64 vcb$q_cd_free;% } vcb$r_free_overlay; __union {] unsigned int vcb$l_maxfiles; /* MAXIMUM NUMBER OF FILES ALLOWED ON VOLUME *// unsigned int vcb$l_cd_maxfiles;) } vcb$r_maxfiles_overlay; __union {N unsigned int vcb$l_window; /* VOLUME DEFAULT WINDOW SIZE */- unsigned int vcb$l_cd_window;' } vcb$r_window_overlay; __union {R Y unsigned int vcb$l_lru_lim; /* VOLUME DIRECTORY LRU SIZE LIMIT */. unsigned int vcb$l_cd_lru_lim;( } vcb$r_lru_lim_overlay; __union {N unsigned int vcb$l_blockfact; /* VOLUME BLOCKING FACTOR */^ unsigned int vcb$l_lbblocks; /* Number of 512-byte blocks per logical block */* } vcb$r_blockfact_overlay;N __union { /* LBN OF VOLUME HOME BLOCK */+ Y unsigned int vcb$l_homelbn;/ unsigned __int64 vcb$q_homelbn;N unsigned int vcb$l_voldesc; /* LBN of CD volume descriptor *// unsigned __int64 vcb$q_voldesc;( } vcb$r_homelbn_overlay;N/* end of overlaid CDrom fields */N __union { /* SCB$L_VOLSIZ */+ unsigned int vcb$l_volsize;/ unsigned __int64 vcb$q_volsize Y;( } vcb$r_volsize_overlay;N __union { /* Expansion limit */+ unsigned int vcb$l_expsize;/ unsigned __int64 vcb$q_expsize;( } vcb$r_expsize_overlay;V __union { /* NESTED UNION CONTAINING MAJOR EXTENSIONS */ __struct {Q __union { /* LBN OF ALTERNATE VOLUME HOME BLOCK */4 unsigned int vcb Y$l_home2lbn;8 unsigned __int64 vcb$q_home2lbn;1 } vcb$r_home2lbn_overlay;Q __union { /* LBN OF ALTERNATE INDEX FILE HEADER */5 unsigned int vcb$l_ixhdr2lbn;9 unsigned __int64 vcb$q_ixhdr2lbn;2 } vcb$r_ixhdr2lbn_overlay;N __union { /* LBN OF INDEX FILE BITMAP */4 unsigned int vcb$l_ibmaplb Yn;8 unsigned __int64 vcb$q_ibmaplbn;1 } vcb$r_ibmaplbn_overlay;N __union { /* LBN OF STORAGE BITMAP */4 unsigned int vcb$l_sbmaplbn;8 unsigned __int64 vcb$q_sbmaplbn;1 } vcb$r_sbmaplbn_overlay;Q unsigned int vcb$l_ibmapsize; /* SIZE OF INDEX FILE BITMAP */X unsigned int vcb$l_ibmapvbn; /* CURRENT VBN YIN INDEX FILE BIT MAP */O unsigned int vcb$l_sbmapsize; /* SIZE OF STORAGE BITMAP */R unsigned int vcb$l_sbmapvbn; /* CURRENT VBN IN STORAGE MAP */Z unsigned int vcb$l_extend; /* VOLUME DEFAULT FILE EXTENSION LENGTH */V unsigned int vcb$l_fileprot; /* VOLUME DEFAULT FILE PROTECTION */S unsigned int vcb$l_eofdelta; /* INDEX FILE EOF UPDATE COUNT */Z unsigned int vcb$l_resfiles;Y /* NUMBER OF RESERVED FILES ON VOLUME */Y struct _fcb *vcb$l_quotafcb; /* ADDRESS OF FCB OF DISK QUOTA FILE */N void *vcb$l_cache; /* ADDRESS OF VOLUME CACHE BLOCK */N void *vcb$l_quocache; /* ADDRESS OF VOLUME QUOTA CACHE */X unsigned int vcb$l_quosize; /* LENGTH OF QUOTA CACHE TO ALLOCATE */Y unsigned int vcb$l_spl_cnt; /* NUMBER OF DEVICES SPOOLED TO VOLUME */T unsignedY int vcb$l_penderr; /* COUNT OF PENDING WRITE ERRORS */N char vcb$t_volcknam [12]; /* NAME FOR VOLUME LOCKS */X struct _vcb *vcb$l_memhdfl; /* SHADOW SET MEMBERS QUEUE HEADER FL */X struct _vcb *vcb$l_memhdbl; /* SHADOW SET MEMBERS QUEUE HEADER BL */N char vcb$b_fill_7 [3]; /* Pad out status byte */W unsigned char vcb$b_shad_sts; /* STATUS BYTE RELATIVE TO MEMHDFL */N Y unsigned int vcb$l_blockid; /* VOLUME BLOCKING LOCK. */N unsigned int vcb$l_activity; /* ACTIVITY COUNT/FLAG */N unsigned char vcb$b_acb [36]; /* ACB FOR BLOCKING AST. */N __union { /* F64 data + attribs caching */; unsigned int vcb$l_caching_options;# __struct {c unsigned vcb$v_file_attributes : 4; /* file attributes caching field */_ Y unsigned vcb$v_file_contents : 4; /* file contents caching field */^ unsigned vcb$v_flush_on_close : 4; /* flush file on close field */W unsigned vcb$v_caching_options_mbz : 20; /* must be zero */9 } vcb$r_caching_options_bits;8 } vcb$r_caching_options_overlay;c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pra Ygma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifW unsigned __int64 vcb$q_access_delta; /* access time qranularity */#pragma __nomember_alignmentW char vcb$b_dvi_volchar [16]; /* DVIVOLDEF structure for disk VCB */Q unsigned short int vcb$w_backrev; /* Copy of SCB$W_BACKREV */& } vcb$r_vcb_disks; __struct {N/* Y */N/* SHADOW SET MEMBER VOLUME CONTROL BLOCK FIELDS */N/* */S struct _ucb *vcb$l_mem_ucb; /* Shadow set member UCB address */T struct _ucb *vcb$l_mast_ucb; /* Shadow set master UCB address */T struct _vcb *vcb$l_mast_vcb; /* Shadow set master VCB address */U unsigned short int vcb$w_copy_type; /* Member'Ys MSCP copy type */Z unsigned short int vcb$w_cpyseqnum; /* IO$_COPYSHAD sequence number */N unsigned __int64 vcb$q_work; /* Per-member workspace */\ unsigned __int64 vcb$q_shdm_resv; /* Reserved for future enhancements */' } vcb$r_vcb_shadow; __struct {N/* */N/* Files-11 C & D Volume Control Block Fields Y */N/* (ISO 9660 and High Sierra) */N/* */_ struct _vcb *vcb$l_orphaned_vcb; /* Singly linked list of Orphaned VCB's */N void *vcb$l_ptvector; /* Address Path Table Vector */N void *vcb$l_lbncache; /* Address of LBN cache listhead */N unsigned int vcb$l_ptindex; /* LBN of Path Table IndexY */P unsigned int vcb$l_lbsize; /* ISO 9660 Logical Block Size */U unsigned int vcb$l_mxdirnm; /* Maximum directory record number */\ unsigned int vcb$l_minread; /* Minimum number of LBNs to read at once */_ unsigned int vcb$l_rdbytes; /* Number of bytes to read from disk at once */` unsigned int vcb$l_lastgrp; /* Highest volume number of last volume group */_ unsigned int vcb$l_p Ytrvn; /* RVN of volume containing current Path Table */P unsigned int vcb$l_fat_rfm; /* Override FAT Record Format */T unsigned int vcb$l_fat_rat; /* Override FAT Record Attributes */V unsigned int vcb$l_fat_mrs; /* Override FAT Maximum Record Size */Q unsigned int vcb$l_sectors; /* Number of sectors on volume */N/* */N/* Compare with VCBDEF_DISK !Yabove, before overlaying any other CDROM fields */N/* */& } vcb$r_vcb_cdrom; __struct {N/* */N/* MTAACP VOLUME CONTROL BLOCK FIELDS */N/* */ __union {V unsigned"Y int vcb$l_cur_fid; /* CURRENT FILE IDENTIFICATION */# __struct {` unsigned short int vcb$w_cur_num; /* CURRENT FILE SECTION NUMBER */a unsigned short int vcb$w_cur_seq; /* CURRENT FILE SEQUENCE NUMBER */3 } vcb$r_cur_fid_fields;0 } vcb$r_cur_fid_overlay; __union {c unsigned int vcb$l_start_fid; /* FILE IDENTIFICATION A#YT START OF SEARCH */# __struct {m unsigned short int vcb$w_start_num; /* FILE SECTION NUMBER AT START OF SEARCH */n unsigned short int vcb$w_start_seq; /* FILE SEQUENCE NUMBER AT START OF SEARCH */5 } vcb$r_start_fid_fields;2 } vcb$r_start_fid_overlay; __union {O unsigned short int vcb$w_mode; /* MODE OF OPERATION */$Y# __struct {Q unsigned vcb$v_ovrexp : 1; /* OVERRIDE EXPIRATION */N unsigned vcb$v_ovracc : 1; /* OVERRIDE ACCESS */N unsigned vcb$v_ovrlbl : 1; /* OVERRIDE LABELS */W unsigned vcb$v_ovrsetid : 1; /* OVERRIDE SET IDENTIFIER */N unsigned vcb$v_intchg : 1; /* INTERCHANGE TAPE */N unsigned vcb$v_ebcdic : %Y1; /* EBCDIC CODE SET */V unsigned vcb$v_novol2 : 1; /* DO NOT WRITE A VOL2 LABEL */V unsigned vcb$v_nohdr3 : 1; /* DO NOT WRITE HDR3 LABELS */g unsigned vcb$v_starfile : 1; /* CURRENT FILE IS A STARLET PRODUCED FILE */h unsigned vcb$v_enusereot : 1; /* SET WHEN USER HANDLING OF EOT IS ENABLED */h unsigned vcb$v_blank : 1; /* SET FOR AVL WHEN NO READ SHOULD H&YAPPEN FIRST */m unsigned vcb$v_init : 1; /* SET FOR AVL WHEN NEXT VOL MOUNTED SHOULD BE INITED */c unsigned vcb$v_noauto : 1; /* MTAACP NOT RUNNING IN AVL AND AVR MODE */` unsigned vcb$v_ovrvolo : 1; /* OVERRIDE THEVOL1 OWNER IDENT FIELD */} unsigned vcb$v_fil_access : 1; /* SET IF ACCESS ROUTINE ALLOWS CHECK OF VMS PROTECTION ON FILE */7 unsigned vcb$v_fill_2_'Y : 1;. } vcb$r_mode_bits;- } vcb$r_mode_overlay;N unsigned char vcb$b_tm; /* NUMBER OF TM'S INTO FILE */O unsigned char vcb$b_cur_rvn; /* CURRENT RELATIVE VOLUME */m unsigned int vcb$l_st_record; /* NUMBER OF RECORDS UP TO AND INCLUDING LAST TAPE MARK */W struct _mvl *vcb$l_mvl; /* ADDRESS OF MAGNETIC TAPE VOLUME LIST */T struct _wcb *vcb$l(Y_wcb; /* ADDRESS OF WINDOW FOR THIS VOLUME */N void *vcb$l_vpfl; /* VIRTUAL PAGE LIST HEAD */N void *vcb$l_vpbl; /* VIRTUAL PAGE LIST TAIL */` struct _acb *vcb$l_usrlblast; /* ADDRESS OF USER LABEL AST CONTROL BLOCK */\ unsigned char vcb$b_lblcnt; /* Count of HDRn labels read on file open */' } vcb$r_vcb_mtaacp;' } vcb$r_vcb_extensions;N/* End the Union of ex)Ytensions */% } vcb$r_vcb_union_member;N/* End the member (which is a union with VCB_JACP) */ __struct {N/* */N/* JOURNAL ACP VOLUME CONTROL BLOCK FIELDS */N/* */N unsigned char vcb$b_qnamecnt; /* BYTE COUNT OF QUEUE N*YAME */R char vcb$t_qname [20]; /* ASCII NAME OF QUEUE FOR THIS DEVICE */ } vcb$r_vcb_jacp; } vcb$r_vcb_union; char vcb$b_fill_3_ [6]; } VCB; #if !defined(__VAXC)2#define vcb$l_fcbfl vcb$r_forward_link.vcb$l_fcbfl6#define vcb$l_blockfl vcb$r_forward_link.vcb$l_blockfl4#define vcb$l_memqfl vcb$r_forward_link.vcb$l_memqfl3#define vcb$l_fcbbl vcb$r_backward_link.vcb$l_fcbbl7#define vcb$l_blockbl vcb$r_backward_link.vcb$l_blockbl5#defin+Ye vcb$l_memqbl vcb$r_backward_link.vcb$l_memqblU#define vcb$b_status vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$b_statusi#define vcb$v_write_if vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_disk_bits.vcb$v_write_ifi#define vcb$v_write_sm vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_disk_bits.vcb$v_write_smk#define vcb$v_homblkbad vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_disk_bits.vcb$v_homblkbadk#define vcb$v_idxhdrbad vcb$r_vcb_union.vc,Yb$r_vcb_union_member.vcb$r_volsts.vcb$r_disk_bits.vcb$v_idxhdrbadg#define vcb$v_noalloc vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_disk_bits.vcb$v_noalloce#define vcb$v_extfid vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_disk_bits.vcb$v_extfidc#define vcb$v_group vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_disk_bits.vcb$v_groupe#define vcb$v_system vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_disk_bits.vcb$v_systemp#define vcb$v_high_sie-Yrra vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_cdrom_bits.vcb$v_high_sierraj#define vcb$v_noswitch vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_cdrom_bits.vcb$v_noswitch`#define vcb$v_dsi vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_cdrom_bits.vcb$v_dsi`#define vcb$v_xar vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_cdrom_bits.vcb$v_xari#define vcb$v_partfile vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_tape_bits.vcb$v_partfilek#d.Yefine vcb$v_logiceovs vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_tape_bits.vcb$v_logiceovsk#define vcb$v_waimouvol vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_tape_bits.vcb$v_waimouvolk#define vcb$v_wairewind vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_tape_bits.vcb$v_wairewindk#define vcb$v_waiusrlbl vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_tape_bits.vcb$v_waiusrlbli#define vcb$v_cancelio vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_/Yvolsts.vcb$r_tape_bits.vcb$v_canceliok#define vcb$v_mustclose vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_tape_bits.vcb$v_mustcloseg#define vcb$v_nowrite vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_tape_bits.vcb$v_nowritek#define vcb$v_shadmast vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_shadow_bits.vcb$v_shadmastg#define vcb$v_failed vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_shadow_bits.vcb$v_failedi#define vcb$v_rebldng vcb$r_vcb_un0Yion.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_shadow_bits.vcb$v_rebldngm#define vcb$v_blkastrec vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_shadow_bits.vcb$v_blkastreci#define vcb$v_mvbegun vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_shadow_bits.vcb$v_mvbegung#define vcb$v_adding vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_shadow_bits.vcb$v_addingm#define vcb$v_packacked vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volsts.vcb$r_shadow_bits.vcb$v_packac1YkedF#define vcb$l_trans vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$l_transB#define vcb$l_rvt vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$l_rvtB#define vcb$l_aqb vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$l_aqb`#define vcb$l_status2 vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status2_overlay.vcb$l_status2`#define vcb$b_status2 vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status2_overlay.vcb$b_status2|#define vcb$v_writethru vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status2_overlay.vcb$r_disk_2Ystatus2_bits.vcb$v_writethrux#define vcb$v_nocache vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status2_overlay.vcb$r_disk_status2_bits.vcb$v_nocachez#define vcb$v_mountver vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status2_overlay.vcb$r_disk_status2_bits.vcb$v_mountvert#define vcb$v_erase vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status2_overlay.vcb$r_disk_status2_bits.vcb$v_erase#define vcb$v_nohighwater vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status2_overlay.vcb$r_disk_status2_bits.v3Ycb$v_nohighwaterx#define vcb$v_noshare vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status2_overlay.vcb$r_disk_status2_bits.vcb$v_nosharez#define vcb$v_cluslock vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status2_overlay.vcb$r_disk_status2_bits.vcb$v_cluslockx#define vcb$v_subset0 vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status2_overlay.vcb$r_disk_status2_bits.vcb$v_subset0f#define vcb$b_cd_status2 vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status2_overlay.vcb$b_cd_status2`#define vcb$l_st4Yatus3 vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status3_overlay.vcb$l_status3|#define vcb$v_subsystem vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status3_overlay.vcb$r_disk_status3_bits.vcb$v_subsystem~#define vcb$v_struc_ods5 vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status3_overlay.vcb$r_disk_status3_bits.vcb$v_struc_ods5#define vcb$v_accesstimes vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status3_overlay.vcb$r_disk_status3_bits.vcb$v_accesstimes|#define vcb$v_hardlinks vcb$r_vcb_union.5Yvcb$r_vcb_union_member.vcb$r_status3_overlay.vcb$r_disk_status3_bits.vcb$v_hardlinks#define vcb$v_special_files vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status3_overlay.vcb$r_disk_status3_bits.vcb$v_special_files~#define vcb$v_noxfccache vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status3_overlay.vcb$r_disk_status3_bits.vcb$v_noxfccache#define vcb$v_xfc_deposing vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_status3_overlay.vcb$r_disk_status3_bits.vcb$v_xfc_deposing^#define vcb$t_volname vcb$6Yr_vcb_union.vcb$r_vcb_union_member.vcb$r_volid_overlay.vcb$t_volnamej#define vcb$t_volidentifier vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_volid_overlay.vcb$t_volidentifierN#define vcb$q_mounttime vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$q_mounttime]#define vcb$l_mcount vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_mcount_overlay.vcb$l_mcountc#define vcb$l_cd_mcount vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_mcount_overlay.vcb$l_cd_mcountB#define vcb$l_rvn vcb$r_vcb_union.vcb$r_vcb_union_7Ymember.vcb$l_rvnB#define vcb$l_orb vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$l_orbF#define vcb$l_reads vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$l_readsH#define vcb$l_writes vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$l_writesN#define vcb$q_readbytes vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$q_readbytesP#define vcb$q_writebytes vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$q_writebytesL#define vcb$l_split_io vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$l_split_ioN#define vcb$l_assist_io vcb$r_vcb_8Yunion.vcb$r_vcb_union_member.vcb$l_assist_ioN#define vcb$l_serialnum vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$l_serialnumJ#define vcb$l_vollkid vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$l_vollkidJ#define vcb$l_cluster vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$l_clusterL#define vcb$l_recordsz vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$l_recordszf#define vcb$q_retainmin vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_retainmin_overlay.vcb$q_retainmind#define vcb$q_exp_date vcb$r_vcb_union.vcb$r_v9Ycb_union_member.vcb$r_retainmin_overlay.vcb$q_exp_dateN#define vcb$q_retainmax vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$q_retainmaxW#define vcb$l_free vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_free_overlay.vcb$l_freeW#define vcb$q_free vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_free_overlay.vcb$q_free]#define vcb$l_cd_free vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_free_overlay.vcb$l_cd_free]#define vcb$q_cd_free vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_free_overlay.vcb$q_cd_free:Yc#define vcb$l_maxfiles vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_maxfiles_overlay.vcb$l_maxfilesi#define vcb$l_cd_maxfiles vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_maxfiles_overlay.vcb$l_cd_maxfiles]#define vcb$l_window vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_window_overlay.vcb$l_windowc#define vcb$l_cd_window vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_window_overlay.vcb$l_cd_window`#define vcb$l_lru_lim vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_lru_lim_overlay.vcb$l_lru_lim;Yf#define vcb$l_cd_lru_lim vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_lru_lim_overlay.vcb$l_cd_lru_limf#define vcb$l_blockfact vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_blockfact_overlay.vcb$l_blockfactd#define vcb$l_lbblocks vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_blockfact_overlay.vcb$l_lbblocks`#define vcb$l_homelbn vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_homelbn_overlay.vcb$l_homelbn`#define vcb$q_homelbn vcb$r_vcb_union.vcb$r_vcb_union_member.vcb$r_homelbn_overlay.vcb$q_homelbnYb_disks.vcb$r_ixhdr2lbn_overlay.vcb$q_ixhdr2lbnL#define vcb$l_ibmaplbn vcb$r_vcb_disks.vcb$r_ibmaplbn_overlay.vcb$l_ibmaplbnL#define vcb$q_ibmaplbn vcb$r_vcb_disks.vcb$r_ibmaplbn_overlay.vcb$q_ibmaplbnL#define vcb$l_sbmaplbn vcb$r_vcb_disks.vcb$r_sbmaplbn_overlay.vcb$l_sbmaplbnL#define vcb$q_sbmaplbn vcb$r_vcb_disks.vcb$r_sbmaplbn_overlay.vcb$q_sbmaplbn7#define vcb$l_ibmapsize vcb$r_vcb_disks.vcb$l_ibmapsize5#define vcb$l_ibmapvbn vcb$r_vcb_disks.vcb$l_ibmapvbn7#define vcb$l_sbmapsize vcb$r_ ?Yvcb_disks.vcb$l_sbmapsize5#define vcb$l_sbmapvbn vcb$r_vcb_disks.vcb$l_sbmapvbn1#define vcb$l_extend vcb$r_vcb_disks.vcb$l_extend5#define vcb$l_fileprot vcb$r_vcb_disks.vcb$l_fileprot5#define vcb$l_eofdelta vcb$r_vcb_disks.vcb$l_eofdelta5#define vcb$l_resfiles vcb$r_vcb_disks.vcb$l_resfiles5#define vcb$l_quotafcb vcb$r_vcb_disks.vcb$l_quotafcb/#define vcb$l_cache vcb$r_vcb_disks.vcb$l_cache5#define vcb$l_quocache vcb$r_vcb_disks.vcb$l_quocache3#define vcb$l_quosize vcb$r_vcb_disks.vc @Yb$l_quosize3#define vcb$l_spl_cnt vcb$r_vcb_disks.vcb$l_spl_cnt3#define vcb$l_penderr vcb$r_vcb_disks.vcb$l_penderr5#define vcb$t_volcknam vcb$r_vcb_disks.vcb$t_volcknam3#define vcb$l_memhdfl vcb$r_vcb_disks.vcb$l_memhdfl3#define vcb$l_memhdbl vcb$r_vcb_disks.vcb$l_memhdbl5#define vcb$b_shad_sts vcb$r_vcb_disks.vcb$b_shad_sts3#define vcb$l_blockid vcb$r_vcb_disks.vcb$l_blockid5#define vcb$l_activity vcb$r_vcb_disks.vcb$l_activity+#define vcb$b_acb vcb$r_vcb_disks.vcb$b_acba#define AYvcb$l_caching_options vcb$r_vcb_disks.vcb$r_caching_options_overlay.vcb$l_caching_options|#define vcb$v_file_attributes vcb$r_vcb_disks.vcb$r_caching_options_overlay.vcb$r_caching_options_bits.vcb$v_file_attributesx#define vcb$v_file_contents vcb$r_vcb_disks.vcb$r_caching_options_overlay.vcb$r_caching_options_bits.vcb$v_file_contentsz#define vcb$v_flush_on_close vcb$r_vcb_disks.vcb$r_caching_options_overlay.vcb$r_caching_options_bits.vcb$v_flush_on_close#define vcb$v_caching_options_mbz vcb$r_vc BYb_disks.vcb$r_caching_options_overlay.vcb$r_caching_options_bits.vcb$v_caching_options_mbz=#define vcb$q_access_delta vcb$r_vcb_disks.vcb$q_access_delta;#define vcb$b_dvi_volchar vcb$r_vcb_disks.vcb$b_dvi_volchar3#define vcb$w_backrev vcb$r_vcb_disks.vcb$w_backrev>#define vcb$r_vcb_shadow vcb$r_vcb_extensions.vcb$r_vcb_shadow4#define vcb$l_mem_ucb vcb$r_vcb_shadow.vcb$l_mem_ucb6#define vcb$l_mast_ucb vcb$r_vcb_shadow.vcb$l_mast_ucb6#define vcb$l_mast_vcb vcb$r_vcb_shadow.vcb$l_mast_vcb8#def CYine vcb$w_copy_type vcb$r_vcb_shadow.vcb$w_copy_type8#define vcb$w_cpyseqnum vcb$r_vcb_shadow.vcb$w_cpyseqnum.#define vcb$q_work vcb$r_vcb_shadow.vcb$q_work8#define vcb$q_shdm_resv vcb$r_vcb_shadow.vcb$q_shdm_resv<#define vcb$r_vcb_cdrom vcb$r_vcb_extensions.vcb$r_vcb_cdrom=#define vcb$l_orphaned_vcb vcb$r_vcb_cdrom.vcb$l_orphaned_vcb5#define vcb$l_ptvector vcb$r_vcb_cdrom.vcb$l_ptvector5#define vcb$l_lbncache vcb$r_vcb_cdrom.vcb$l_lbncache3#define vcb$l_ptindex vcb$r_vcb_cdrom.vcb$l_ptinde DYx1#define vcb$l_lbsize vcb$r_vcb_cdrom.vcb$l_lbsize3#define vcb$l_mxdirnm vcb$r_vcb_cdrom.vcb$l_mxdirnm3#define vcb$l_minread vcb$r_vcb_cdrom.vcb$l_minread3#define vcb$l_rdbytes vcb$r_vcb_cdrom.vcb$l_rdbytes3#define vcb$l_lastgrp vcb$r_vcb_cdrom.vcb$l_lastgrp/#define vcb$l_ptrvn vcb$r_vcb_cdrom.vcb$l_ptrvn3#define vcb$l_fat_rfm vcb$r_vcb_cdrom.vcb$l_fat_rfm3#define vcb$l_fat_rat vcb$r_vcb_cdrom.vcb$l_fat_rat3#define vcb$l_fat_mrs vcb$r_vcb_cdrom.vcb$l_fat_mrs3#define vcb$l_sectors EYvcb$r_vcb_cdrom.vcb$l_sectors>#define vcb$r_vcb_mtaacp vcb$r_vcb_extensions.vcb$r_vcb_mtaacpJ#define vcb$l_cur_fid vcb$r_vcb_mtaacp.vcb$r_cur_fid_overlay.vcb$l_cur_fid_#define vcb$w_cur_num vcb$r_vcb_mtaacp.vcb$r_cur_fid_overlay.vcb$r_cur_fid_fields.vcb$w_cur_num_#define vcb$w_cur_seq vcb$r_vcb_mtaacp.vcb$r_cur_fid_overlay.vcb$r_cur_fid_fields.vcb$w_cur_seqP#define vcb$l_start_fid vcb$r_vcb_mtaacp.vcb$r_start_fid_overlay.vcb$l_start_fidg#define vcb$w_start_num vcb$r_vcb_mtaacp.vcb$r_start_fidFY_overlay.vcb$r_start_fid_fields.vcb$w_start_numg#define vcb$w_start_seq vcb$r_vcb_mtaacp.vcb$r_start_fid_overlay.vcb$r_start_fid_fields.vcb$w_start_seqA#define vcb$w_mode vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$w_modeU#define vcb$v_ovrexp vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_ovrexpU#define vcb$v_ovracc vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_ovraccU#define vcb$v_ovrlbl vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_ovrlblY#define vcb$v_ovrsGYetid vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_ovrsetidU#define vcb$v_intchg vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_intchgU#define vcb$v_ebcdic vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_ebcdicU#define vcb$v_novol2 vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_novol2U#define vcb$v_nohdr3 vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_nohdr3Y#define vcb$v_starfile vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$vHY_starfile[#define vcb$v_enusereot vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_enusereotS#define vcb$v_blank vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_blankQ#define vcb$v_init vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_initU#define vcb$v_noauto vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_noautoW#define vcb$v_ovrvolo vcb$r_vcb_mtaacp.vcb$r_mode_overlay.vcb$r_mode_bits.vcb$v_ovrvolo]#define vcb$v_fil_access vcb$r_vcb_mtaacp.vcb$r_mode IY_overlay.vcb$r_mode_bits.vcb$v_fil_access*#define vcb$b_tm vcb$r_vcb_mtaacp.vcb$b_tm4#define vcb$b_cur_rvn vcb$r_vcb_mtaacp.vcb$b_cur_rvn8#define vcb$l_st_record vcb$r_vcb_mtaacp.vcb$l_st_record,#define vcb$l_mvl vcb$r_vcb_mtaacp.vcb$l_mvl,#define vcb$l_wcb vcb$r_vcb_mtaacp.vcb$l_wcb.#define vcb$l_vpfl vcb$r_vcb_mtaacp.vcb$l_vpfl.#define vcb$l_vpbl vcb$r_vcb_mtaacp.vcb$l_vpbl8#define vcb$l_usrlblast vcb$r_vcb_mtaacp.vcb$l_usrlblast2#define vcb$b_lblcnt vcb$r_vcb_mtaacp.vcb$b_lblcnt5#define JYvcb$r_vcb_jacp vcb$r_vcb_union.vcb$r_vcb_jacp4#define vcb$b_qnamecnt vcb$r_vcb_jacp.vcb$b_qnamecnt.#define vcb$t_qname vcb$r_vcb_jacp.vcb$t_qname"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __VCBDEF_LOA KYDED */ ww@[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. LY **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 CopyrMYight VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:37 by OpenVMS SDL V3.7 */F/* Source: 22-DEC-2017 14:14:29 $1$DGA8345:[LIB_H.SRC]VCCDEF.SDL;1 *//************* NY*******************************************************************************************************************//*** MODULE $VCCDEF ***/#ifndef __VCCDEF_LOADED#define __VCCDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined requiredOY ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define PY__union variant_union#endif#endif N/* */N/* CFCB - Cache File Control Block */N/* */N/* There is one CFCB for each cacheable file. The Cache File Control */N/* Block contains the information necessary for consistent data caching */N/* in a VAXcluster. The FCB contains the address of the CFCB.QY */N/* */ #define CFCB$M_SEQ 0x1#define CFCB$M_CONFLICT 0x2#define CFCB$M_WRITE 0x4#define CFCB$M_NOLOCK 0x8#define CFCB$M_BUSY 0x10#define CFCB$M_DELAYBLKAST 0x20 #define CFCB$M_DELAYCMPLAST 0x40#define CFCB$M_DISBLKFRK 0x80#define CFCB$M_DISCMPLFRK 0x100#define CFCB$M_LIMBO 0x200#define CFCB$M_BYPASS 0x400#define CFCB$M_TRUNCATE 0x800#define CFCB$M_DELETE 0x1000 #define CFCB$M_NRYOPRESERVE 0x2000#define CFCB$K_LENGTH 168N#define CFCB$S_CFCBDEF 168 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _acb; struct _ht; struct _fcb; struct _vcb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cfcb {N/* h SYead of CFCB is an ACB which we use as a FKB */#pragma __nomember_alignment __union {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifN char cfcb$b_frk_fcb [48]; /* Embedded fork block */#pragma __nomember_alignment __struct {N struct _acb *cfcb$l_astqfl; /* AST queue FLINK TY */N struct _acb *cfcb$l_astqbl; /* AST queue BLINK */N unsigned short int cfcb$w_size; /* size of CFCB in bytes */Q unsigned char cfcb$b_type; /* type is VCC, a subtypable structure */R unsigned char cfcb$b_subtype; /* subtype for CFCB and RMODE for ACB */R unsigned int cfcb$l_ast_pid; /* either accesser/deacceser or server */N void (*cfcb$l_ast_addr)(); /* address to resume process UY*/N unsigned int cfcb$l_ast_prm; /* the parameter */N/* no KAST field needed */N/* end of ACB */ } cfcb$r_frk_struct; } cfcb$r_frk_overlay;N/* cells to control access to and type of cache mode lock */N __union { /* lock status block */N unsigned __int64 cfcb$q_lksb VY; /* whole LKSB */ __struct {N unsigned short int cfcb$w_lksb_status; /* completion status *// unsigned short int cfcb$w_reserved;N unsigned int cfcb$l_lockid; /* lockid of cache mode lock */! } cfcb$r_lksb_fields; } cfcb$r_lksb_overlay;T unsigned int cfcb$l_wait_pid; /* PID waiting for cache mode lock access */P int (*cfcb$l_wait_addr)(); /* address at which to resume procesWYs */O unsigned int cfcb$l_wait_prm; /* AST parameter for waiting process */R unsigned int cfcb$l_writers; /* number of reasons to keep write lock */R struct _ht *cfcb$l_hashtable; /* address of hash table data structure */N __union { /* */N unsigned int cfcb$l_status; /* */N __struct { /* */Q XY unsigned cfcb$v_seq : 1; /* file is being accessed sequentially */N/* these next 3 bits must be together */N/* they indicate the current cache mode */^ unsigned cfcb$v_conflict : 1; /* this node's access conflicts with another node */Q unsigned cfcb$v_write : 1; /* set for read/write, clear read only */N unsigned cfcb$v_nolock : 1; /* no cache mode lock held */N/* status biYYts for accessing the cache mode lock */O unsigned cfcb$v_busy : 1; /* cache mode lock is being modified */Q unsigned cfcb$v_delayblkast : 1; /* BLKAST arrived while CFCB busy */S unsigned cfcb$v_delaycmplast : 1; /* CMPLAST arrived while CFCB busy */N unsigned cfcb$v_disblkfrk : 1; /* disable future blocking forks */Q unsigned cfcb$v_discmplfrk : 1; /* disable future completion forks */N/* OTHER STATUS BITS ZY */N unsigned cfcb$v_limbo : 1; /* set if CFCB in LIMBO */N unsigned cfcb$v_bypass : 1; /* If set don't cache IO requests */N unsigned cfcb$v_truncate : 1; /* If set, need to truncate cache */' unsigned cfcb$v_delete : 1;R unsigned cfcb$v_nopreserve : 1; /* If set delete cache at $DEACCESS */( unsigned cfcb$v_fill_0_ : 2;! } cfcb$r_status_bits; [Y } cfcb$r_status_overlay;N/* counts of interesting things */N unsigned int cfcb$l_vread; /* virtual reads to this file */N unsigned int cfcb$l_readhit; /* read hits to this file */N unsigned int cfcb$l_vwrite; /* virtual writes to this file */N unsigned int cfcb$l_writehit; /* write hits to this file */P unsigned int cfcb$l_around; /* read or writes "around" this cach\Ye */P unsigned int cfcb$l_blockcnt; /* data blocks allocated to this file */P unsigned int cfcb$l_clcnt; /* cache lines allocated to this file */P unsigned int cfcb$l_ioerrors; /* number of I/O errors for this file */N unsigned int cfcb$l_lastvbn; /* last VBN read/written */S unsigned int cfcb$l_hivbn; /* largest VBN ever cached for this file */N struct _fcb *cfcb$l_fcb; /* FCB associated with this CFCB */Q unsi]Ygned int cfcb$l_ocnt; /* Count of Reasons not to delete CFCB */R unsigned int cfcb$l_disable; /* number of reasons to disable caching */N/* of this file even if cache mode lock */N/* will allow caching */N/* zero means caching is enabled */S unsigned int cfcb$l_lkq_status; /* status of ENQ/DEQ request (not final) */N unsigned int cfc ^Yb$l_time; /* Time put CFCB put in LIMBO */N unsigned __int64 cfcb$q_limbo; /* Queue of CFCB that are in LIMBO */N unsigned int cfcb$l_cid; /* Cache ID */N struct _vcb *cfcb$l_cvcb; /* VCB address for this file */N char cfcb$t_lockname [12]; /* XQP lockname */ } CFCB; #if !defined(__VAXC)H#define cfcb$l_astqfl cfcb$r_frk_overlay.cfcb$r_frk_struct.cfcb$l_astqflH#define cfcb_Y$l_astqbl cfcb$r_frk_overlay.cfcb$r_frk_struct.cfcb$l_astqblD#define cfcb$w_size cfcb$r_frk_overlay.cfcb$r_frk_struct.cfcb$w_sizeD#define cfcb$b_type cfcb$r_frk_overlay.cfcb$r_frk_struct.cfcb$b_typeJ#define cfcb$b_subtype cfcb$r_frk_overlay.cfcb$r_frk_struct.cfcb$b_subtypeJ#define cfcb$l_ast_pid cfcb$r_frk_overlay.cfcb$r_frk_struct.cfcb$l_ast_pidL#define cfcb$l_ast_addr cfcb$r_frk_overlay.cfcb$r_frk_struct.cfcb$l_ast_addrJ#define cfcb$l_ast_prm cfcb$r_frk_overlay.cfcb$r_frk_struct.cfcb$l_ast_prm`Y3#define cfcb$q_lksb cfcb$r_lksb_overlay.cfcb$q_lksbT#define cfcb$w_lksb_status cfcb$r_lksb_overlay.cfcb$r_lksb_fields.cfcb$w_lksb_statusN#define cfcb$w_reserved cfcb$r_lksb_overlay.cfcb$r_lksb_fields.cfcb$w_reservedJ#define cfcb$l_lockid cfcb$r_lksb_overlay.cfcb$r_lksb_fields.cfcb$l_lockid9#define cfcb$l_status cfcb$r_status_overlay.cfcb$l_statusF#define cfcb$v_seq cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_seqP#define cfcb$v_conflict cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_confaYlictJ#define cfcb$v_write cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_writeL#define cfcb$v_nolock cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_nolockH#define cfcb$v_busy cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_busyV#define cfcb$v_delayblkast cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_delayblkastX#define cfcb$v_delaycmplast cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_delaycmplastR#define cfcb$v_disblkfrk cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_disblkfrkT#define cfbYcb$v_discmplfrk cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_discmplfrkJ#define cfcb$v_limbo cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_limboL#define cfcb$v_bypass cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_bypassP#define cfcb$v_truncate cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_truncateL#define cfcb$v_delete cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_deleteT#define cfcb$v_nopreserve cfcb$r_status_overlay.cfcb$r_status_bits.cfcb$v_nopreserve"#endif /* #if !defined(__VAXC cY) */ N/* */N/* HT - Hash Table */N/* */N/* There is one hash table for each cacheable file. The Cache File Control */O/* Block contains the address of the hash table. Access requires owning the */N/* cache spin lock. */N#define HT$Q_H dYASHTABLE 24 /* start of hash table */N#define HT$S_HTDEF 24 /* Old size name - synonym */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _ht {O/* The cache line and hash table sizes are not constants. They may vary for */N/* different files. The size of each must be a power of two. TeYhe VBN is */N/* subdivided into bitfields based on the cache line size and the size of */N/* the hash table. The lowest bits, <0,CLSIZE-1> represent the offset in */N/* the cache line. Bits are the hash index. These */N/* fields are accessed via bitfield instructions and the values of CLSIZE */N/* and HASHSIZE are encoded to define bitfields NOT the actual size of the */N/* entity. */#pragma fY__nomember_alignmentQ unsigned int ht$l_clsize; /* encoded cache line size (see above) */Q unsigned int ht$l_hashsize; /* encoded hash table size (see above) */S unsigned short int ht$w_size; /* size of hash table strcuture in bytes */Q unsigned char ht$b_type; /* type is VCC, a subtypable structure */N unsigned char ht$b_subtype; /* subtype for HT */N unsigned int ht$l_entries; /* Entries in HT (if expan gYsion ne 0 */N/* then actual number is ENTRIES*2) */N unsigned int ht$l_expansion; /* Highest Hash currently being */N/* expanded */N int ht$l_ht_fill; /* fill for alignment */ } HT;N/* */N/* CL - Cache Line */N hY/* */P/* A Cache Line is used by the VAXcluster Cache to track per VBN information. */N/* The hash table in the CFCB points to cache lines. */N/* */#define CL$M_WRITE 0x10000#define CL$M_DELAYTRUNC 0x20000#define CL$K_LENGTH 64N#define CL$S_CLDEF 64 /* Old size name - synonym */ c#if !defined(_ iY_NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cl {#pragma __nomember_alignmentN void *cl$l_flink; /* Equivalence class forward link */N void *cl$l_blink; /* Equivalence class back link */N unsigned short int cl$w_size; /* size of CL in bytes */Q unsigned char cl$b_type; jY /* type is VCC, a subtypable structure */N unsigned char cl$b_subtype; /* subtype for CL */N unsigned int cl$l_entries; /* Number of Entries in Use */N unsigned int cl$l_expansion; /* Buckets being split */N unsigned int cl$l_time; /* Time CL last referenced */N unsigned int cl$l_firstvbn; /* first VBN in this cache line */N struct _cfcb *cl$l_cfcb; /* address of correskYponding CFCB */S unsigned __int64 cl$q_lruentry; /* absolute queue entry in VCC$Q_LRULINE */Q unsigned __int64 cl$q_valid; /* set if corresponding VBN data valid */N unsigned __int64 cl$q_dirty; /* set if corresponding VBN data */N/* needs to be written before block */N/* is reused */R __union { /* Cache Line lock, access VAs and d lYata */N unsigned int cl$l_lock; /* looks just like mutex */P __struct { /* but uses cache spinlock not sched */N unsigned short int cl$w_count; /* Count of current accessers */N unsigned cl$v_write : 1; /* write in progress or pending */N unsigned cl$v_delaytrunc : 1; /* delete this line during unlock */& unsigned cl$v_fill_1_ : 6; } cl$r_lock_fields; } cl$r_lock_ov mYerlay;O void *cl$l_va; /* virtual addresses for data blocks */ } CL; #if !defined(__VAXC)-#define cl$l_lock cl$r_lock_overlay.cl$l_lock@#define cl$w_count cl$r_lock_overlay.cl$r_lock_fields.cl$w_count@#define cl$v_write cl$r_lock_overlay.cl$r_lock_fields.cl$v_writeJ#define cl$v_delaytrunc cl$r_lock_overlay.cl$r_lock_fields.cl$v_delaytrunc"#endif /* #if !defined(__VAXC) */ N/* */N/*nY CPT - Cache I/O Page Table */N/* */N/* A range of sequential VBNs is not guarenteed to be virtually contiguous */N/* in the cache. Physical I/O requires the SVAPTE which maps the buffer. */N/* The cache builds a "fake" page table in this data structure and passes */N/* its virtual address as the SVAPTE. In addition some per I/O cache */N/* information is stored heroYe rather than enlarge the IRP. */N/* */Q#define CPT$L_PTE 32 /* start of PTEs(Must be QUAD Aligned) */N#define CPT$K_LENGTH 32 /* not counting size of VA array */N/* which is run time dependent */N#define CPT$S_CPTDEF 32 /* Old size name - synonym */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defin pYed(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _iocpt { __union {#pragma __nomember_alignmentN __int64 cpt$q_iova; /* Cache IO VA (64 Bits) */ __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N qYvoid *cpt$pq_iova_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else" unsigned __int64 cpt$pq_iova_sva;#endif } cpt$r_fill_3_; } cpt$r_fill_2_;N unsigned short int cpt$w_size; /* size of CPT in bytes */Q unsigned char cpt$b_type; /* type is VCC, a subtypable structure */N unsigned char cpt$b_subtype; /* subtype for CPT */N unsigned int cpt$l_ioextra; /* read ahead byte count */N unrYsigned int cpt$l_iovbn; /* cache I/O VBN */N unsigned int cpt$l_iobcnt; /* cache I/O byte count */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN struct _cfcb *cpt$l_cfcb; /* CFCB address for this I/O */N unsigned int cpt$l_rhbcnt; /* read hit byte count */N/* rea sYl length equals IRP length */ } IOCPT; #if !defined(__VAXC)+#define cpt$q_iova cpt$r_fill_2_.cpt$q_iovaC#define cpt$pq_iova_sva cpt$r_fill_2_.cpt$r_fill_3_.cpt$pq_iova_sva"#endif /* #if !defined(__VAXC) */ N/* */N/* CVCB - Cache Volume Control Block */N/* tY*/N/* There is one of these structures for each ODS2 volume currently */N/* mounted by this node. It is used to permit detection of users */N/* that perform writes to volumes around the cache, so that the */N/* file caches concerned may be flushed. */N/* */#define CVCB$M_ON 0x1#define CVCB$M_MISMTCH 0x2#define CVCB$M_DELETE 0x4#define CVCB$M_BSY 0x8uY#define CVCB$M_CONFLICT 0x10#define CVCB$M_QIRP 0x20#define CVCB$M_XFCLK 0x40#define CVCB$K_LENGTH 152N#define CVCB$S_CVCBDEF 152 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _vcb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftyvYpedef struct _cvcb {#pragma __nomember_alignment void *cvcb$l_flink; void *cvcb$l_blink;# unsigned short int cvcb$w_size; unsigned char cvcb$b_type;! unsigned char cvcb$b_subtype; char cvcb$b_fill_4_ [4];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif __union {N char cvcb$b_frk_fcb [48]; /* Embedded fork blo wYck */#pragma __nomember_alignment __struct {N struct _fkb *cvcb$l_frk1; /* Fork Block */N struct _fkb *cvcb$l_frk2; /* Fork Block */N struct _fkb *cvcb$l_frk3; /* Fork Block */N struct _fkb *cvcb$l_frk4; /* Fork Block */N struct _fkb *cvcb$l_frk5; /* Fork Block */N struct _fkb *cvcb$l_frxYk6; /* Fork Block */N struct _fkb *cvcb$l_frk7; /* Fork Block */N struct _fkb *cvcb$l_frk8; /* Fork Block */ } cvcb$r_frk_struct; } cvcb$r_frk_overlay;N struct _vcb *cvcb$l_vcb; /* VCB address */P unsigned int cvcb$l_cid; /* Cache ID (monatonicaly increasing) */N unsigned int cvcb$l_cluid; /* Cluster ID (similar to CID) yY */ __union {" unsigned int cvcb$l_state; __struct {N unsigned cvcb$v_on : 1; /* Set if cache enabled this Volume */N unsigned cvcb$v_mismtch : 1; /* Set if not CACHE SAFE Driver */N unsigned cvcb$v_delete : 1; /* Set if Deleteing this CVCB */N unsigned cvcb$v_bsy : 1; /* Set if State change in progress */O unsigned cvcb$v_conflict : 1; /* Set if MISMTCH Set somewhere in */I/* Cluster zY */N unsigned cvcb$v_qirp : 1; /* Set if IRP's Q'd waiting for */N/* Cluster Invalidate */N unsigned cvcb$v_xfclk : 1; /* Set if have Volume Interest Lock */( unsigned cvcb$v_fill_5_ : 1; } cvcb$r_state_bits; } cvcb$r_state_overlay;Q unsigned int cvcb$l_ocnt; /* Count of Reasons not to Delete CVCB */N unsigned int c{Yvcb$l_mntct; /* VCB$W_MNTCT at last State Change */N unsigned __int64 cvcb$q_irp; /* Q for IRP's */N __union { /* lock status block */N unsigned __int64 cvcb$q_lksb; /* whole LKSB */ __struct {N unsigned short int cvcb$w_lksb_status; /* completion status *// unsigned short int cvcb$w_reserved;N unsigned int cvcb$l_lockid; /* lockid of |Y Cache volume lock */! } cvcb$r_lksb_fields; } cvcb$r_lksb_overlay;N __union { /* lock status block */N unsigned __int64 cvcb$q_intlksb; /* whole LKSB */ __struct {N unsigned short int cvcb$w_intlksb_status; /* completion status */3 unsigned short int cvcb$w_int_reserved;O unsigned int cvcb$l_intlockid; /* lockid of Volume Interest lock */$ }Y} cvcb$r_intlksb_fields;! } cvcb$r_intlksb_overlay;N unsigned int cvcb$l_pool; /* Address for Pool in GET_VOL_LOCK */N unsigned int cvcb$l_seq; /* Cluster MEMSEQ for Node Bits */N unsigned int cvcb$l_bits; /* Node bits */ unsigned int cvcb$l_bits1; unsigned int cvcb$l_bits2; unsigned int cvcb$l_bits3; unsigned int cvcb$l_bits4; unsigned int cvcb$l_bits5; unsigned int cvcb$l_bits6; unsigned ~Y int cvcb$l_bits7; } CVCB; #if !defined(__VAXC)D#define cvcb$l_frk1 cvcb$r_frk_overlay.cvcb$r_frk_struct.cvcb$l_frk1D#define cvcb$l_frk2 cvcb$r_frk_overlay.cvcb$r_frk_struct.cvcb$l_frk2D#define cvcb$l_frk3 cvcb$r_frk_overlay.cvcb$r_frk_struct.cvcb$l_frk3D#define cvcb$l_frk4 cvcb$r_frk_overlay.cvcb$r_frk_struct.cvcb$l_frk4D#define cvcb$l_frk5 cvcb$r_frk_overlay.cvcb$r_frk_struct.cvcb$l_frk5D#define cvcb$l_frk6 cvcb$r_frk_overlay.cvcb$r_frk_struct.cvcb$l_frk6D#define cvcb$l_frk7 cvcb$rY_frk_overlay.cvcb$r_frk_struct.cvcb$l_frk7D#define cvcb$l_frk8 cvcb$r_frk_overlay.cvcb$r_frk_struct.cvcb$l_frk86#define cvcb$l_state cvcb$r_state_overlay.cvcb$l_stateB#define cvcb$v_on cvcb$r_state_overlay.cvcb$r_state_bits.cvcb$v_onL#define cvcb$v_mismtch cvcb$r_state_overlay.cvcb$r_state_bits.cvcb$v_mismtchJ#define cvcb$v_delete cvcb$r_state_overlay.cvcb$r_state_bits.cvcb$v_deleteD#define cvcb$v_bsy cvcb$r_state_overlay.cvcb$r_state_bits.cvcb$v_bsyN#define cvcb$v_conflict cvcb$r_state_overlayY.cvcb$r_state_bits.cvcb$v_conflictF#define cvcb$v_qirp cvcb$r_state_overlay.cvcb$r_state_bits.cvcb$v_qirpH#define cvcb$v_xfclk cvcb$r_state_overlay.cvcb$r_state_bits.cvcb$v_xfclk3#define cvcb$q_lksb cvcb$r_lksb_overlay.cvcb$q_lksbT#define cvcb$w_lksb_status cvcb$r_lksb_overlay.cvcb$r_lksb_fields.cvcb$w_lksb_statusN#define cvcb$w_reserved cvcb$r_lksb_overlay.cvcb$r_lksb_fields.cvcb$w_reservedJ#define cvcb$l_lockid cvcb$r_lksb_overlay.cvcb$r_lksb_fields.cvcb$l_lockid<#define cvcb$q_intlksb cvcb$Yr_intlksb_overlay.cvcb$q_intlksb`#define cvcb$w_intlksb_status cvcb$r_intlksb_overlay.cvcb$r_intlksb_fields.cvcb$w_intlksb_status\#define cvcb$w_int_reserved cvcb$r_intlksb_overlay.cvcb$r_intlksb_fields.cvcb$w_int_reservedV#define cvcb$l_intlockid cvcb$r_intlksb_overlay.cvcb$r_intlksb_fields.cvcb$l_intlockid"#endif /* #if !defined(__VAXC) */ N/* */N/* CACHE$GL_FLAGS is now used to select the cache type to be loaded. Y */N/* As such the previous flags definitions which only apply to VIOC */N/* should be considered obsolete. Only use the flags definition if you */N/* know what you are doing. */N/* */N/* Bits in SYSGEN parameter CACHE$GL_FLAGS */N/* This is actually 4 one byte sysgen parameters. */I/* CACHE$GB_FLAGS0Y - user "visible" static prefix CACHE_TYPE$C */I/* CACHE$GB_FLAGS1 - user "visible" static prefix CACHE_FLAGS$V */I/* CACHE$GB_FLAGS2 */I/* CACHE$GB_FLAGS3 */N/* */N#define CACHE_TYPE$C_NOCACHE 0 /* No cache is loaded */]#define CACHE_TYPE$C_VIOC 1 /* Cache type is VIOYC, Virtual I/O Cache (aka VCC) */U#define CACHE_TYPE$C_XFC 2 /* Cache type is XFC, Extended File Cache */P/* Define XFC control flag bits in CACHE$GL_FLAGS as flags and not constants. */N/* These are not present in V7.3 and below... */\/* The CACHE_TYPE$C values above remain for historical reasons. In future please use the */N/* bitfield values below... */N/* Y */#define CACHE_FLAGS$M_VIOC 0x1#define CACHE_FLAGS$M_XFC 0x2(#define CACHE_FLAGS$M_FLAG_NOT_USED 0xFC-#define CACHE_FLAGS$M_XFC_PER_RAD_CACHE 0x100 typedef struct _cacheflags1 { __struct {N unsigned cache_flags$v_vioc : 1; /* Load VIOC */N unsigned cache_flags$v_xfc : 1; /* Load XFC execlet */Y unsigned cache_flags$v_flag_not_used : 6; /* pad bit definitions into position */S unsi Ygned cache_flags$v_xfc_per_rad_cache : 1; /* Use XFC per RAD caching */+ unsigned cache_flags$v_fill_6_ : 7; } cache_flags$r_flags1; } CACHEFLAGS1; #if !defined(__VAXC)B#define cache_flags$v_vioc cache_flags$r_flags1.cache_flags$v_vioc@#define cache_flags$v_xfc cache_flags$r_flags1.cache_flags$v_xfc\#define cache_flags$v_xfc_per_rad_cache cache_flags$r_flags1.cache_flags$v_xfc_per_rad_cache"#endif /* #if !defined(__VAXC) */ #define CACHE$M_ON 0x1!#define CACHE$ YM_PROTOCOL_ONLY 0x2#define CACHE$M_READ_AHEAD 0x4"#define CACHE$M_UPDATE_ON_WRTE 0x8N#define CACHE$S_CACHEDEF 1 /* Old size name - synonym */ typedef struct _cacheflags { __struct {N unsigned cache$v_on : 1; /* Turn on caching */N unsigned cache$v_protocol_only : 1; /* Run the cache protocal, but */N/* don't cache anything. */N unsigned cache$v_read_ahead : 1; /* YAllow Read Ahead */N unsigned cache$v_update_on_wrte : 1; /* Update on Write Alogrithm */% unsigned cache$v_fill_7_ : 4; } cache$r_flags; } CACHEFLAGS; #if !defined(__VAXC)+#define cache$v_on cache$r_flags.cache$v_onA#define cache$v_protocol_only cache$r_flags.cache$v_protocol_only;#define cache$v_read_ahead cache$r_flags.cache$v_read_aheadC#define cache$v_update_on_wrte cache$r_flags.cache$v_update_on_wrte"#endif /* #if !defined(__VAXC) Y*/ N/* Define bits in CACHE$GL_STATE */N/* */#define CACHE_STATE$M_LBSY 0x1#define CACHE_STATE$M_MBSY 0x2#define CACHE_STATE$M_LOCK 0x4#define CACHE_STATE$M_PAK 0x8#define CACHE_STATE$M_ON 0x10#define CACHE_STATE$M_IMG 0x20!#define CACHE_STATE$M_HETERO 0x40 #define CACHE_STATE$M_FLUSH 0x80"#define CACHE_STATE$M_UPDWRT 0x100!#define CACHE_STATE$M_RDAHD 0x200 #def Yine CACHE_STATE$M_SAFE 0x400 #define CACHE_STATE$M_DATA 0x800%#define CACHE_STATE$M_USERSIZE 0x1000$#define CACHE_STATE$M_ENABLED 0x2000$#define CACHE_STATE$M_REDUCED 0x4000!#define CACHE_STATE$M_FULL 0x8000N#define CACHE_STATE$S_CACHESTATEDEF 2 /* Old size name - synonym */ typedef struct _cachestate { __struct {N unsigned cache_state$v_lbsy : 1; /* Cache master lock busy */N unsigned cache_state$v_mbsy : 1; /* */YN unsigned cache_state$v_lock : 1; /* Cache master lock acquired */N unsigned cache_state$v_pak : 1; /* VCC PAK enabled */N unsigned cache_state$v_on : 1; /* Cache enabled */N unsigned cache_state$v_img : 1; /* Image cache enabled */N unsigned cache_state$v_hetero : 1; /* Heterogenous cluster */N unsigned cache_state$v_flush : 1; /* Flush cache contents */N unsigned cache_sYtate$v_updwrt : 1; /* Populate on update write only */N unsigned cache_state$v_rdahd : 1; /* Read ahead enabled */N unsigned cache_state$v_safe : 1; /* Cache safe derivers present */N unsigned cache_state$v_data : 1; /* Data cache enabled */N unsigned cache_state$v_usersize : 1; /* User has sized cache */N unsigned cache_state$v_enabled : 1; /* Caching enabled */N unsigned cache_state$v_reduced : 1; /* XFC Y is using Reduced Mode */N unsigned cache_state$v_full : 1; /* XFC is using Full Mode */ } cache_state$r_state; } CACHESTATE; #if !defined(__VAXC)A#define cache_state$v_lbsy cache_state$r_state.cache_state$v_lbsyA#define cache_state$v_mbsy cache_state$r_state.cache_state$v_mbsyA#define cache_state$v_lock cache_state$r_state.cache_state$v_lock?#define cache_state$v_pak cache_state$r_state.cache_state$v_pak=#define cache_state$v_on cache_state$r_state.cac Yhe_state$v_on?#define cache_state$v_img cache_state$r_state.cache_state$v_imgE#define cache_state$v_hetero cache_state$r_state.cache_state$v_heteroC#define cache_state$v_flush cache_state$r_state.cache_state$v_flushE#define cache_state$v_updwrt cache_state$r_state.cache_state$v_updwrtC#define cache_state$v_rdahd cache_state$r_state.cache_state$v_rdahdA#define cache_state$v_safe cache_state$r_state.cache_state$v_safeA#define cache_state$v_data cache_state$r_state.cache_state$v_dataI#def Yine cache_state$v_usersize cache_state$r_state.cache_state$v_usersizeG#define cache_state$v_enabled cache_state$r_state.cache_state$v_enabledG#define cache_state$v_reduced cache_state$r_state.cache_state$v_reducedA#define cache_state$v_full cache_state$r_state.cache_state$v_full"#endif /* #if !defined(__VAXC) */ N/* Define item codes for GET_STAT */N/* */N#define CACHE_ITEMY$_LISTEND 0 /* List terminator */N#define CACHE_ITEM$_STATE 1 /* State flags */N#define CACHE_ITEM$_CACHE_MEMORY 2 /* Pages of cache memory */N#define CACHE_ITEM$_FREE_CACHE 3 /* Free page of cache memory */N#define CACHE_ITEM$_READ_HITS 4 /* Read hits */N#define CACHE_ITEM$_VIRT_READS 5 /* Virtual reads to cacheable files */O#define CACHE_ITEM$_VIRT_WRITES 6 /* VYirtual writes to cacheable files */N#define CACHE_ITEM$_R_ARND_MOD 7 /* Read arounds du to modifier bits */P#define CACHE_ITEM$_R_ARND_SIZ 8 /* Read arounds due to size too large */P#define CACHE_ITEM$_W_ARND_MOD 9 /* Write arounds due to modifier bits */Q#define CACHE_ITEM$_W_ARND_SIZ 10 /* Write arounds due to size too large */N#define CACHE_ITEM$_LIMBO_LEN 11 /* Length of limbo queue */R#define CACHE_ITEM$_MIN_CACHE_SIZE 12 /* Current lower bouYnd on size of cache */R#define CACHE_ITEM$_MAX_CACHE_SIZE 13 /* Current upper bound on size of cache */Y#define CACHE_ITEM$_MAX_CACHE_LIMIT 14 /* Upper limit set by boot-time PTE allocation */N#define CACHE_ITEM$_MAX_IO_SIZE 15 /* Largest IO XFC will cache */]#define CACHE_ITEM$_MAX_LOCKS 16 /* Maximum number of locks XFC can acquire locally */Y#define CACHE_ITEM$_READAHEAD 17 /* Current value of VCC_READAHEAD SYSGEN param */[#define CACHE_ITEM$_WRITEBEHIND 18 Y /* Current value of VCC_WRITEBEHIND SYSGEN param */[#define CACHE_ITEM$_WRITE_DELAY 19 /* Current value of VCC_WRITE_DELAY SYSGEN param */Y#define CACHE_ITEM$_VOLS_FXFC_MODE 20 /* Count of volumes currently in full XFC mode */\#define CACHE_ITEM$_VOLS_RXFC_MODE 21 /* Count of volumes currently in reduced XFC mode */[#define CACHE_ITEM$_VOLS_NC_MODE 22 /* Count of volumes currently in no-caching mode */Z#define CACHE_ITEM$_OPEN_FILES 23 /* Count of open files with valid daYta in cache */[#define CACHE_ITEM$_UNSYNCHED_IOS 24 /* Count of IO's not synchronised with XFC cache */Z#define CACHE_ITEM$_DELAYED_WRITES 25 /* Count of delayed writes since system startup */d#define CACHE_ITEM$_LOST_WRITES 26 /* Count of delayed writes discarded since system startup */c#define CACHE_ITEM$_FULL_BARRIERS 27 /* Count of outstanding full barriers currently in cache */c#define CACHE_ITEM$_PARTIAL_BARRIERS 28 /* Count of outstanding full barriers currently in cache */YP#define CACHE_ITEM$_READS_AROUND 29 /* Count of all reads bypassing cache */Q#define CACHE_ITEM$_WRITES_AROUND 30 /* Count of all writes bypassing cache */N#define CACHE_ITEM$_CURRENT_LOCKS 31 /* Count of locks held by cache */^#define CACHE_ITEM$_BARRIER_COUNT 32 /* Count of barriers inserted into cache since boot */W#define CACHE_ITEM$_SUPER_WRITES 33 /* Count of writes that supersede dirty data */c#define CACHE_ITEM$_NON_PAGED_POOL 34 /* Amount of non-paged pool cuurYrently held by the cache */[#define CACHE_ITEM$_VOLS_PNC_MODE 35 /* Count of volumes in permanent no-caching mode */N#define CACHE_ITEM$_IOSIZE_ARRAYS 36 /* Arrays of IOs by size */N#define CACHE_ITEM$_TIME_LAST_RESET 37 /* Time since last reset of stats */N#define CACHE_ITEM$_TRACE_ENTRY 38 /* to get trace buffer record(s) */O#define CACHE_ITEM$_SET_TRACE_MASK 39 /* to set trace include/exclude mask */N#define CACHE_ITEM$_TRACE_RESET 40 /* to empty trace bu Yffer */]#define CACHE_ITEM$_BLOCKS_READ 41 /* Total of blocks read from cache (hits + misses) */P#define CACHE_ITEM$_BLOCKS_FROM_CACHE 42 /* Total blocks satisfied from cache */i#define CACHE_ITEM$_BLOCKS_WRITTEN 43 /* Total blocks written (includes writethroughs + writearounds */##define CACHE_ITEM$_MAX_VCC_ITEM 11##define CACHE_ITEM$_MAX_XFC_ITEM 43#define CACHE_ITEM$_MAX_ITEM 43 N/* Values for item codes for CACHE$SET_STATVOL() and */N/* CACYHE$SET_STATFILE(). */N#define CACHE_CONTROL$_RESET_STATISTICS 1 /* Reset statistics to zero */T#define CACHE_CONTROL$_SIZE_DISABLE 2 /* Disable extended statistics collection */S#define CACHE_CONTROL$_SIZE_ENABLE 3 /* Enable extended statistics collection */N#define CACHE_CONTROL$_FORCE_DEPOSE 4 /* Force depose of volume or file */N#define CACHE_CONTROL$_FORCE_NOCACHE 5 /* Force file to no cache state */W/* Define CVS (CacheY Volume Statistics) for obtaining per volume statistics from XFC */N/* Values for CVS$L_CACHE_STATE: */N/* NOTE: coordinate changes with [XFC]XFCDEF.H */N#define CVS$C_NOCACHING 4096 /* Volume not cached */N#define CVS$C_REDUCEDXFC 4097 /* Volume in reduced XFC mode */N#define CVS$C_FULLXFC 4098 /* Volume in Full XFC mode */N#define CVS$C_PERMNOCACHING 4099 Y /* Volume permanently not cached */#define CVS$K_VOLNAM_LEN 12#define CVS$C_VOLNAM_LEN 12N#define CVS$K_HDRLEN 52 /* Length of header */N#define CVS$C_HDRLEN 52 /* */N/* NOTE: any changes or additions to the following fields or */N#define CVS$C_XFC_ARRAYSIZE 128 /* Size of array */ #define CVS$K_ORIG_ITEM_COUNT 31 #define CVS$C_ORIG_ITEM_COUNT 31#define CVS$K_YITEM_COUNT 37#define CVS$C_ITEM_COUNT 37#define CVS$K_BASE_SIZE 348#define CVS$C_BASE_SIZE 348 #define CVS$K_IO_ARRAY_SIZE 3112 #define CVS$C_IO_ARRAY_SIZE 3112  9#ifdef __cplusplus /* Define structure prototypes */ struct _vcb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cvs {Y#pragma __nomember_alignmentN unsigned __int64 cvs$q_reserved1; /* unused; aligns type to byte 11 */N unsigned short int cvs$w_mbo; /* must be one */Q unsigned char cvs$b_type; /* type is VCC, a subtypable structure */N unsigned char cvs$b_subtype; /* subtype is VCC_CVS */\ unsigned int cvs$l_version; /* version of Cache Volume Statistics used by XFC */N unsigned int cvs$l_status; /* return statusY */N unsigned int cvs$l_cache_state; /* Volume caching state */N struct _vcb *cvs$l_vcb; /* address of Volume Control Block */P unsigned int cvs$l_itm_cnt; /* Number of quadword items to return */j unsigned int cvs$l_iosize_buffer_size; /* Size (bytes) of IO size stat buffer (0 if none requested) */N int *cvs$l_iosize_buffer; /* Address of IO size stat buffer */N char cvs$t_volnam [12]; /* blank filYled volume name */O/* values MUST also be reflected in the CVB_STATS structure in [XFC]XFCDEF.H */N unsigned __int64 cvs$q_open_files; /* Open cached files */N unsigned __int64 cvs$q_closed_files; /* Closed cached files */N unsigned __int64 cvs$q_files_ever_opened; /* Files ever opened */N unsigned __int64 cvs$q_files_ever_deposed; /* Files ever deposed */_ unsigned __int64 cvs$q_pages_allocated; /* Pages of memory currently helYd for the volume */^ unsigned __int64 cvs$q_locks_acquired; /* Number of locks currently held for the volume */N unsigned __int64 cvs$q_totalqios; /* Total QIOs against this volume */N unsigned __int64 cvs$q_read_hits; /* read cache hits */N unsigned __int64 cvs$q_virtual_reads; /* virtual reads */N unsigned __int64 cvs$q_virtual_writes; /* " writes */N unsigned __int64 cvs$q_read_aheads; /* Read aheads Y */N unsigned __int64 cvs$q_read_throughs; /* Read throughs */N unsigned __int64 cvs$q_write_throughs; /* Write throughs */N unsigned __int64 cvs$q_read_around_count; /* Read arounds */N unsigned __int64 cvs$q_write_around_count; /* Write arounds */S unsigned __int64 cvs$q_read_around_mod; /* Read arounds due to modifier bits */U unsigned __int64 cvs$q_write_around_mod; /* Write arounds due to modifier bits */UY unsigned __int64 cvs$q_read_around_size; /* Read arounds due to size too large */W unsigned __int64 cvs$q_write_around_size; /* Write arounds due to size too large */N unsigned __int64 cvs$q_write_behinds; /* Write behinds */T unsigned __int64 cvs$q_full_barriers; /* Number of full barriers in dep graph */N unsigned __int64 cvs$q_lost_writes; /* Writes lost due to disk errors */N unsigned __int64 cvs$q_unsynched_io_count; /* Count of unsynced I/Os */Z Y unsigned __int64 cvs$q_partial_barriers; /* Number of partial barriers in dep graph */\ unsigned __int64 cvs$q_barrier_count; /* Number of barrier calls made since boot-time */W unsigned __int64 cvs$q_synch_response_miss; /* Count of response time I/O misses */X unsigned __int64 cvs$q_asynch_response_miss; /* Count of response time I/O misses */Z unsigned __int64 cvs$q_synch_response_tics; /* Sum of ticks for synch response time */\ unsigned __int64 cvs$q_asynch_response_tics; /Y* Sum of ticks for asynch response time */N unsigned __int64 cvs$q_response_time; /* Overall Disk I/O response time */O unsigned __int64 cvs$q_cvb_last_reset; /* Time this array was last reset */] unsigned __int64 cvs$q_blocks_read; /* Total of blocks read from cache (hits + misses) */U unsigned __int64 cvs$q_blocks_from_cache; /* Total blocks satisfied from cache */l unsigned __int64 cvs$q_blocks_written; /* Total blocks written (includes writethroughs + writearounds */N unYsigned __int64 cvs$q_files_truncated; /* Number of files truncated */N unsigned __int64 cvs$q_logical_io_count; /* Number of logical IOs */ unsigned __int64 cvs$q_vcml_blocking_asts; /* Number for volume deposes from a VCML blocking AST (logical IO in cluster) */N/* Add new individual stat fields above this line */N/* */N/* IO size array: Y */N unsigned __int64 cvs$q_read_blocksize [128]; /* Read Size stat array */N unsigned __int64 cvs$q_block_read_hits [128]; /* Read Hits stat array */N unsigned __int64 cvs$q_write_blocksize [128]; /* Write Size stat array */X unsigned __int64 cvs$q_writes128to255; /* Number of writes in 128-255 block range */V unsigned __int64 cvs$q_reads128to255; /* Number of reads in 128-255 block range */W unsigned __int64 cvs$q_large_writes; /* Number of writes greater t Yhan 255 blocks */U unsigned __int64 cvs$q_large_reads; /* Number of reads greater than 255 blocks */P unsigned __int64 cvs$q_time_last_reset; /* Time this array was last reset */ char cvs$b_fill_8_ [4]; } CVS;b/* New CVS fields should be accompanied by an increment of the value of CACHE_VERSION$C_VCC_CVS */N/* below. */N#define CACHE_VERSION$_VCC_CVS 65536 /* Version number of CVS interface */S/* Define CFS Y(Cache File Statistics) for obtaining per file statistics from XFC */ N/* Values for FILE_STATE (also on input to CACHE$GET_FIDS): */N#define CFS$K_OPEN 1 /* CFS$K_OPEN - file is open */N#define CFS$C_OPEN 1 /* CFS$C_OPEN - file is open */N#define CFS$K_CLOSED 2 /* CFS$K_CLOSED - file is closed */N#define CFS$C_CLOSED 2 /* CFS$C_CLOSED - file is closed */N/* Values for CFS$L_CACHE_STATYE: */N/* NOTE: coordinate changes with [XFC]XFCDEF.H */N#define CFS$C_DEFAULT 8192 /* No active mode specified */N#define CFS$C_WRITETHROUGH 8193 /* File in writethrough mode */N#define CFS$C_WRITEBEHIND 8194 /* File in writebehind mode */N#define CFS$C_NOCACHING 8195 /* File is not cached */N#define CFS$K_HDRLEN 56 /* Length of hea Yder */N#define CFS$C_HDRLEN 56 /* */N/* NOTE: any changes or additions to the following stats fields */N#define CFS$C_XFC_ARRAYSIZE 128 /* Size of array */#define CFS$K_ITEM_COUNT 20#define CFS$C_ITEM_COUNT 20#define CFS$K_BASE_SIZE 216#define CFS$C_BASE_SIZE 216 #define CFS$K_IO_ARRAY_SIZE 3112 #define CFS$C_IO_ARRAY_SIZE 3112  9#ifdef __cplusplus /* Define structure prYototypes */ struct _vcb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _cfs {#pragma __nomember_alignmentN unsigned __int64 cfs$q_reserved1; /* unused; aligns type to byte 11 */N unsigned short int cfs$w_mbo; /* must be one */Q unsigned char cfs$b_type; Y /* type is VCC, a subtypable structure */N unsigned char cfs$b_subtype; /* subtype is VCC_CVS */Z unsigned int cfs$l_version; /* version of Cache File Statistics used by XFC */N unsigned int cfs$l_status; /* return status */N unsigned int cfs$l_cache_state; /* File active caching state */N unsigned int cfs$l_file_state; /* Open/closed state */N unsigned int cfs$l_caching_disabled; /* BoYolean */N struct _vcb *cfs$l_vcb; /* address of Volume Control Block */N unsigned __int64 cfs$q_fid; /* FID (last word unused) */P unsigned int cfs$l_itm_cnt; /* Number of quadword items to return */j unsigned int cfs$l_iosize_buffer_size; /* Size (bytes) of IO size stat buffer (0 if none requested) */N int *cfs$l_iosize_buffer; /* Address of IO size stat buffer */N/* MUST also be reflected in the CFB_STATSY structure in [XFC]XFCDEF.H */N/* */] unsigned __int64 cfs$q_pages_allocated; /* Pages of memory currently held for the file */N unsigned __int64 cfs$q_totalqios; /* Total QIOs against this file */N unsigned __int64 cfs$q_read_hits; /* read cache hits */N unsigned __int64 cfs$q_virtual_reads; /* virtual reads */N unsigned __int64 cfs$q_virtual_writes; /* " Y writes */N unsigned __int64 cfs$q_read_aheads; /* Read aheads */N unsigned __int64 cfs$q_read_throughs; /* Read throughs */N unsigned __int64 cfs$q_write_throughs; /* Write throughs */N unsigned __int64 cfs$q_read_around_count; /* Read arounds */N unsigned __int64 cfs$q_write_around_count; /* Write arounds */S unsigned __int64 cfs$q_read_around_mod; /* Read arounds due to modifier biYts */U unsigned __int64 cfs$q_write_around_mod; /* Write arounds due to modifier bits */U unsigned __int64 cfs$q_read_around_size; /* Read arounds due to size too large */W unsigned __int64 cfs$q_write_around_size; /* Write arounds due to size too large */N unsigned __int64 cfs$q_write_behinds; /* Write behinds */N unsigned __int64 cfs$q_unsynched_io_count; /* Count of unsynced I/Os */N unsigned __int64 cfs$q_lost_writes; /* Writes lost due to disk errorYs */T unsigned __int64 cfs$q_full_barriers; /* Number of full barriers in dep graph */Z unsigned __int64 cfs$q_partial_barriers; /* Number of partial barriers in dep graph */\ unsigned __int64 cfs$q_barrier_count; /* Number of barrier calls made since boot-time */N/* Add new individual stat fields above this line */N/* */N/* IO Size array: Y */N unsigned __int64 cfs$q_read_blocksize [128]; /* Read Size stat array */N unsigned __int64 cfs$q_block_read_hits [128]; /* Read Hits stat array */N unsigned __int64 cfs$q_write_blocksize [128]; /* Write Size stat array */X unsigned __int64 cfs$q_writes128to255; /* Number of writes in 128-255 block range */V unsigned __int64 cfs$q_reads128to255; /* Number of reads in 128-255 block range */W unsigned __int64 cfs$q_large_writes; /* Number of writes greater than Y255 blocks */U unsigned __int64 cfs$q_large_reads; /* Number of reads greater than 255 blocks */P unsigned __int64 cfs$q_time_last_reset; /* Time this array was last reset */ } CFS;b/* New CFS fields should be accompanied by an increment of the value of CACHE_VERSION$C_VCC_CFS */N/* below. */N#define CACHE_VERSION$_VCC_CFS 65536 /* Version number of CFS interface */N/* Y */N/* The following values should be loaded into the global cell */N/* CACHE$GL_PROTOCOL_VER to indicate which level of locking */N/* protocol is going to be used by the cache loaded at boot */N/* time. The protocol level being used by other members of */N/* the cluster can be found in the CSB's of the respective */N/* nodes. Y */N/* */N/* Note that the default value of CACHE$GL_PROTOCOL_VER is */N/* zero so that pre-XFC aware versions of the OS 'acquire' */N/* the correct value in their remote CSB's */N/* */N#define CACHE_VERSION$_NOCACHE 0 /* No or unknown locking protocol */N#define CACHE_VERSIO YN$_VCC_V01_00 65536 /* VIOC with no XFC compatibility */O#define CACHE_VERSION$_VCC_V01_01 65537 /* VIOC with XFC compatible protocol */P#define CACHE_VERSION$_XFC_V01_00 131072 /* Fully XFC V1.0 compliant protocol */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma Y__standard #endif /* __VCCDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of YHPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. Y **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */G/* Source: 17-JAN-2000 13:10:54 $1$DGA8345:[LIB Y_H.SRC]VCIBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $VCIBDEF ***/#ifndef __VCIBDEF_LOADED#define __VCIBDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __saveY /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC) Y#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* VCIB - VAX Communication Interface Block */N/* */N/* The VCIB is the data structure used to define an instance of a VCI port */N/* between two VCMs. A single VCIB is used between only two layers. Those */N/* two layers may haYve many VCIBs between them; each one representing a */N/* different VCI port. Only the common fields within the VCIB are defined */N/* here. All layer-specific fields are defined elsewhere. Some constants */N/* used within the VCIB are defined here also. And the VCM IDs are also */N/* defined here. */N/*- */N/* VCI Registry function codes. Y */N#define VCIB$K_FC_REGISTER 0 /* Register a VCM */N#define VCIB$K_FC_UNREGISTER 1 /* Unregister a VCM */N#define VCIB$K_FC_CREATE_PORT 2 /* Create a port to a lower VCM */N#define VCIB$K_FC_DELETE_PORT 3 /* Delete a port to a lower VCM */N/* Registered users of the VCI. */N#define VCI$K_ID_MODEM 257 /* Modem Connect Y */N#define VCI$K_ID_NWM 2048 /* Network Management */N#define VCI$K_ID_CONF 2049 /* Conformance Test Tool */N#define VCI$K_ID_SCL 1280 /* Session Control */N#define VCI$K_ID_SCLSRV 1281 /* Session Control Session Services */N#define VCI$K_ID_SCLMIN 1282 /* Session Control Minimum Services */N#define VCI$K_ID_NSPTP 1024 /* Transport - NSP */N#define VCI$K_ID_OYSITP 1025 /* Transport - OSI */N#define VCI$K_ID_LCLTP 1026 /* Transport - Local */N#define VCI$K_ID_SCATP 1027 /* Transport - SCA */N#define VCI$K_ID_LAT 1028 /* Transport - LAT */N#define VCI$K_ID_LAST 1029 /* Transport - LAST */N#define VCI$K_ID_LAVC 1030 /* Transport - LAVC */N#define VCI$K_ID_MOP 1031 /* MYaintenance Operations */N#define VCI$K_ID_TCPIP 1032 /* Transport - TCPIP */N#define VCI$K_ID_IP 1032 /* Transport - IP */N#define VCI$K_ID_AMDS 1033 /* Transport - AMDS */N#define VCI$K_ID_CUSTP 1177 /* Transport - Customer */N#define VCI$K_ID_NRL 768 /* Network Routing */N#define VCI$K_ID_ALIAS 769 /* Alias (Routing portion) Y */N#define VCI$K_ID_CUSRL 921 /* Routing - Customer */N#define VCI$K_ID_LAN 513 /* Data Link - CSMACD & FDDI */N#define VCI$K_ID_DDCMP 514 /* Data Link - DDCMP Synchronous */N#define VCI$K_ID_HDLC 515 /* Data Link - HDLC Synchronous */N#define VCI$K_ID_ASY 516 /* Data Link - Asynchronous */N#define VCI$K_ID_X25 517 /* Data Link - X.25 */N#define VCI$K_IDY_ADM 518 /* Data Link - ALTSTART DDCMP */N#define VCI$K_ID_ACM 519 /* Data Link - ALTSTART CSMACD */N#define VCI$K_ID_LAPB 520 /* Data Link - LAPB */N#define VCI$K_ID_LLC2 521 /* Data Link - LLC2 */N#define VCI$K_ID_NETBEUI 528 /* Data Link - NETBEUI */N#define VCI$K_ID_IPX 529 /* Data Link - IPX */Q#define VCI$K_ID_DSP 530 /*Y Data Link - Digital stream protocol */N#define VCI$K_ID_PP 531 /* Data Link - PP */N#define VCI$K_ID_ASYN 532 /* Data Link - ASYN */N#define VCI$K_ID_CUSDL 665 /* Data Link - Customer */N#define VCI$K_ID_TST1 2304 /* Test VCM - 1st */N#define VCI$K_ID_TST2 2305 /* Test VCM - 2nd */N#define VCI$K_ID_TST3 2306 /* Test VCM - 3rd Y */N#define VCI$K_ID_TST4 2307 /* Test VCM - 4th */N#define VCI$K_ID_TST5 2308 /* Test VCM - 5th */N#define VCI$K_ID_TST6 2309 /* Test VCM - 6th */N#define VCI$K_ID_TST7 2310 /* Test VCM - 7th */N#define VCI$K_ID_TST8 2311 /* Test VCM - 8th */N#define VCI$K_ID_LANMON 2312 /* Test VCM - Lan monitor */N#define VCYI$K_ID_LANTEST 2313 /* Test VCM - Lan test */N#define VCI$K_ID_DECNET_1 2560 /* DECnet reserved VCM 0..FF */N#define VCI$K_ID_DECNET_FF 2815 /* DECnet reserved VCM 0..FF */N#define VCI$K_NUM_ID 41 /* Number of valid VCMs */N/* VCIB data structure */N/* */N/* The common fields within the VCIB Y are defined now. */N#define VCIB$K_FIXED_LENGTH 60 /* Length of fixed portion of VCIB */ struct vcibdef {N void *vcib$l_flink; /* Forward Queue link */N void *vcib$l_blink; /* Backward Queue link */N unsigned short int vcib$w_size; /* Size of structure */N unsigned char vcib$b_type; /* Type of structure - DYN$C_NET */O unsigned char vcib$b_sub_type; Y/* Subtype of structure - DYN$C_VCIB */P unsigned int vcib$l_vci_id; /* Field containing the VCI ID of the */N/* VCM (used by the lower VCM for */N/* validation of user) */N unsigned short int vcib$w_version_upper; /* VCI Version of Upper VCM */N unsigned short int vcib$w_version_lower; /* VCI Version of Lower VCM */N void *vcib$a_portmgmt_synch; /* Address of Lower VCYM's Port */N/* Management Synchronous service */N void *vcib$a_portmgmt_initiate; /* Address of Lower VCM's Port */N/* Management Initiate service */N void *vcib$a_portmgmt_complete; /* Address of Upper VCM's Port */N/* Management Complete service */N void *vcib$a_control_synch; /* Address of Lower VCM's Control */N/* SynchYronous service */N void *vcib$a_control_initiate; /* Address of Lower VCM's Control */N/* Initiate service */N void *vcib$a_control_complete; /* Address of Upper VCM's Control */N/* Complete service */N void *vcib$a_transmit_initiate; /* Address of Lower VCM's Transmit */N/* Initiate service Y */N void *vcib$a_transmit_complete; /* Address of Upper VCM's Transmit */N/* Complete service */N void *vcib$a_receive_complete; /* Address of Upper VCM's Receive */N/* Complete service */N void *vcib$a_report_event; /* Address of Upper VCM's Report */N/* Event service Y */ } ; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __VCIBDEF_LOADED */ ww[UM/***************************************************************************/M/** Y **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** Y **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*************Y**************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */G/* Source: 26-JAN-2022 23:16:38 $1$DGA8345:[LIB_H.SRC]LANUDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $VCIBDLLDEF ***/#ifndef Y__VCIBDLLDEF_LOADED#define __VCIBDLLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus Yextern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* Data Link definit Yions that follow the standard VCIB fields */N/*-- */ #define VCIB$M_DLL_RCV_DCB 0x1#define VCIB$M_DLL_RCV_MAC 0x2 #define VCIB$M_DLL_XMT_CHAIN 0x1!#define VCIB$M_DLL_XMT_RCVRSB 0x2"#define VCIB$M_DLL_PORT_STATUS 0x4N#define VCIB$K_DLL_CSMACD 1 /* CSMACD data link */N#define VCIB$K_DLL_DDCMP 2 /* DDCMP data link */N#define VCIB$K_DLL_FDDI 3 Y /* FDDI data link */N#define VCIB$K_DLL_HDLC 4 /* HDLC data link */N#define VCIB$K_DLL_LAPB 5 /* LAPB data link */N#define VCIB$K_DLL_TR 6 /* TOKEN RING data link */N#define VCIB$K_DLL_ATM 7 /* ATM data link */N#define VCIB$K_DLL_LLC2 8 /* LLC2 data link */#define VCIB$M_LAN_RCV_LIM 0x1#define VCIB$M_LAN_RCV_ICSY 0x2#define VCIB$M_LAN_FTC 0x4#define VCIB$M_LAN_SFR 0x8#define VCIB$M_LAN_SCC 0x10#define VCIB$M_LAN_FPE 0x20 #define VCIB$M_LAN_FP_RCVLL 0x40#define VCIB$M_LAN_RCV_DCB 0x1#define VCIB$M_LAN_DP_DELAY 0x2#define VCIB$M_LAN_MULSEG 0x4#define VCIB$M_LAN_FASTPATH 0x8#define VCIB$M_LAN_TSO 0x10#define VCIB$M_LAN_LRO 0x20#define VCIB$M_LAN_IP_CSUM 0x40!#define VCIB$M_LAN_IPV6_CSUM 0x80"#define VCIB$M_LAN_SCTP_CSUM 0x100"#define VCIB$M_LAN_IP_RXCSUM 0x200#define VCIB$M_L YAN_TXMBUF 0x400N#define VCIB$K_LAN_FIXED_LENGTH 160 /* Length of LAN VCIB */#define VCIB$M_SYN_UNSEQ 0x1N#define VCIB$K_SYN_FIXED_LENGTH 98 /* Length of SYN VCIB */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _vcibdlldef {N/* First get to the end of the common VCIB section. Then we can start Y */N/* the overlay. */#pragma __nomember_alignment char vcib$b_dll_filler [60];N/* DLL extensions to the VCIB. Note that the DLL extension includes */N/* some generic extensions (DLL) followed by an overlay of the LAN */N/* and SYN extensions. */N void *vcib$a_dll_input_list; /* Address of input item list */N void *vcib$a_dll_output_list; Y /* Address of output item list */ __union {S unsigned short int vcib$w_dll_client_flags; /* Flags specified by client */N unsigned int vcib$l_dll_client_flags; /* Flags specified by client */ __struct {N unsigned vcib$v_dll_rcv_dcb : 1; /* 1 = Can pass DCB on RCV */N unsigned vcib$v_dll_rcv_mac : 1; /* Determines where */N/* VCRP$A_LAN_R_HEADER points: */N/* 0 = the LHI s Ytructure */N/* 1 = MAC specific frame header */N/* FDDI: [FC] */N/* CSMACD: [DA] */N/* TR: [AC] */( unsigned vcib$v_fill_0_ : 6;! } vcib$r_dll_flags_1; } vcib$r_dll_overlay_1; __union Y {O unsigned short int vcib$w_dll_flags; /* Flags specified by data link */N unsigned int vcib$l_dll_flags; /* Flags specified by data link */ __struct {N unsigned vcib$v_dll_xmt_chain : 1; /* 1 = device can chain */O unsigned vcib$v_dll_xmt_rcvrsb : 1; /* 1 = DL can XMT on RCV RSB */U unsigned vcib$v_dll_port_status : 1; /* 1 = PORT USABLE was last event */N/* 0 = PORT UNUSABLE was last Y */N/* event, OR no USABLE/UNUSABLE */N/* event has occured yet */( unsigned vcib$v_fill_1_ : 5;! } vcib$r_dll_flags_2; } vcib$r_dll_overlay_2; __union {N unsigned short int vcib$w_dll_type; /* Type of data link */N unsigned int vcib$l_dll_type; /* Type of data link */" } vcib$r_dll_type_overlay; __unio Yn {S unsigned short int vcib$w_dll_hdr_size; /* Max data link header in bytes */N unsigned int vcib$l_dll_hdr_size; /* Max data link header in bytes */& } vcib$r_dll_hdr_size_overlay; __union {N unsigned short int vcib$w_dll_xmt_size; /* Max transmit in bytes */N unsigned int vcib$l_dll_xmt_size; /* Max transmit in bytes */& } vcib$r_dll_xmt_size_overlay; __union {V unsigned short int vcib$w_dll_chain_size; /* Min size Yof 1st chain in bytes */P unsigned int vcib$l_dll_chain_size; /* Min size of 1st chain in bytes */( } vcib$r_dll_chain_size_overlay;N/* Define the values for the field VCIB$W_DLL_TYPE. */ __union {N/* LAN extensions to the VCIB; after the DLL extensions. */ __struct {N void *vcib$a_lan_lpb; /* Address of LAN Port Block */N void *vcib$a_lan_ucb; /* Address of UCB */YQ void *vcib$a_lan_build_hdr; /* Address of LAN Build Header service */X void *vcib$a_lan_transmit_frame; /* Address of LAN Transmit Frame service */Q void *vcib$a_lan_transmit_avail; /* Address of available Transmits */N unsigned int vcib$l_lan_max_rcv; /* Max outstanding receives */Q unsigned int vcib$l_lan_out_rcv; /* Number of outstanding receives */ __union {[ unsigned short int vcib$w_lan_client_flagsY; /* Flags specified by client */U unsigned int vcib$l_lan_client_flags; /* Flags specified by client */ __struct {R unsigned vcib$v_lan_rcv_lim : 1; /* 1 = DL will limit the # */N/* of RCV VCRPs */S unsigned vcib$v_lan_rcv_ics : 1; /* 1 = DL must init context */N/* stack in RCV VCRPs */Q unYsigned vcib$v_lan_ftc : 1; /* 1 = Fast Transmit Complete */N unsigned vcib$v_lan_sfr : 1; /* 1 = Skip field restore */P unsigned vcib$v_lan_scc : 1; /* 1 = Skip completion check */N unsigned vcib$v_lan_fpe : 1; /* 1 = FastPath enabled */f unsigned vcib$v_lan_fp_rcvll : 1; /* 1 = FastPath - complete rcvs with LAN lock */0 unsigned vcib$v_fill_2_ : 1;) } vcib$r_lan_flags_1;' Y } vcib$r_lan_overlay_1; __union {N unsigned int vcib$l_lan_flags; /* Flags specified by LAN */ __struct {S unsigned vcib$v_lan_rcv_dcb : 1; /* 1 = DL supports VCRP/DCB */W unsigned vcib$v_lan_dp_delay : 1; /* 1 = Disable Port is delayed */W unsigned vcib$v_lan_mulseg : 1; /* 1 = DL can xmt chain multiple */N/* segments (DCBEs) Y */V unsigned vcib$v_lan_fastpath : 1; /* 1 = DL is FastPath enabled */N unsigned vcib$v_lan_tso : 1; /* Hw can do IP/IPV6 TSO */N unsigned vcib$v_lan_lro : 1; /* Hw can do IP/IPV6 LRO */S unsigned vcib$v_lan_ip_csum : 1; /* Hw can do CKO ip/tcp-udp */W unsigned vcib$v_lan_ipv6_csum : 1; /* Hw can do CKO ipv6/tcp-udp */O unsigned vcib$v_lan_sctp_csum : 1; /* Hw can do CK YO SCTP */\ unsigned vcib$v_lan_ip_rxcsum : 1; /* Hw can do CKO on receive frames */X unsigned vcib$v_lan_txmbuf : 1; /* Driver can handle BSD TX mbufs */0 unsigned vcib$v_fill_3_ : 5;) } vcib$r_lan_flags_2;' } vcib$r_lan_overlay_2;N void *vcib$a_lan_ldc; /* Address of the LDC structure */N int vcib$l_lan_oocnt; /* Number of operations outstanding */N voYid *vcib$a_lan_dp_vcrp; /* Address of the Disable Port VCRP */N/* being disabled. Only valid if */N/* the DP_DELAY flag is set. */N void *vcib$a_lan_hwa; /* pointer to HWA/MLA */N void *vcib$a_lan_pha; /* pointer to PHA */N void *vcib$a_lan_reset; /* Boot driver done */P int vcib$l_lan_dll_pref_cpu; Y /* Lan port preferred CPU (FastPath) */U int vcib$l_lan_client_pref_cpu; /* Lan client preferred CPU (FastPath) */ } vcib$r_lan_vcib;N/* SYN extensions to the VCIB; after the DLL extensions. */ __struct {N void *vcib$a_syn_up_port; /* Used only by the data link */ __union {[ unsigned short int vcib$w_syn_client_flags; /* Flags specified by client */ __struct {T Y unsigned vcib$v_syn_unseq : 1; /* 1 = Client wants unseq port */0 unsigned vcib$v_fill_4_ : 7;) } vcib$r_syn_flags_1;' } vcib$r_syn_overlay_1; } vcib$r_syn_vcib;$ } vcib$r_dll_vcib_additions; } VCIBDLLDEF; #if !defined(__VAXC)L#define vcib$w_dll_client_flags vcib$r_dll_overlay_1.vcib$w_dll_client_flagsL#define vcib$l_dll_client_flags vcib$r_dll_overlay_1.vcib$l_dll_client_flagsU#define vcib$v_dll_rcv_dcbY vcib$r_dll_overlay_1.vcib$r_dll_flags_1.vcib$v_dll_rcv_dcbU#define vcib$v_dll_rcv_mac vcib$r_dll_overlay_1.vcib$r_dll_flags_1.vcib$v_dll_rcv_mac>#define vcib$w_dll_flags vcib$r_dll_overlay_2.vcib$w_dll_flags>#define vcib$l_dll_flags vcib$r_dll_overlay_2.vcib$l_dll_flagsY#define vcib$v_dll_xmt_chain vcib$r_dll_overlay_2.vcib$r_dll_flags_2.vcib$v_dll_xmt_chain[#define vcib$v_dll_xmt_rcvrsb vcib$r_dll_overlay_2.vcib$r_dll_flags_2.vcib$v_dll_xmt_rcvrsb]#define vcib$v_dll_port_status vcib$r_dll_Yoverlay_2.vcib$r_dll_flags_2.vcib$v_dll_port_status?#define vcib$w_dll_type vcib$r_dll_type_overlay.vcib$w_dll_type?#define vcib$l_dll_type vcib$r_dll_type_overlay.vcib$l_dll_typeK#define vcib$w_dll_hdr_size vcib$r_dll_hdr_size_overlay.vcib$w_dll_hdr_sizeK#define vcib$l_dll_hdr_size vcib$r_dll_hdr_size_overlay.vcib$l_dll_hdr_sizeK#define vcib$w_dll_xmt_size vcib$r_dll_xmt_size_overlay.vcib$w_dll_xmt_sizeK#define vcib$l_dll_xmt_size vcib$r_dll_xmt_size_overlay.vcib$l_dll_xmt_sizeQ#define Yvcib$w_dll_chain_size vcib$r_dll_chain_size_overlay.vcib$w_dll_chain_sizeQ#define vcib$l_dll_chain_size vcib$r_dll_chain_size_overlay.vcib$l_dll_chain_sizeA#define vcib$r_lan_vcib vcib$r_dll_vcib_additions.vcib$r_lan_vcib5#define vcib$a_lan_lpb vcib$r_lan_vcib.vcib$a_lan_lpb5#define vcib$a_lan_ucb vcib$r_lan_vcib.vcib$a_lan_ucbA#define vcib$a_lan_build_hdr vcib$r_lan_vcib.vcib$a_lan_build_hdrK#define vcib$a_lan_transmit_frame vcib$r_lan_vcib.vcib$a_lan_transmit_frameK#define vcib$a_lan_tYransmit_avail vcib$r_lan_vcib.vcib$a_lan_transmit_avail=#define vcib$l_lan_max_rcv vcib$r_lan_vcib.vcib$l_lan_max_rcv=#define vcib$l_lan_out_rcv vcib$r_lan_vcib.vcib$l_lan_out_rcvA#define vcib$r_lan_overlay_1 vcib$r_lan_vcib.vcib$r_lan_overlay_1L#define vcib$w_lan_client_flags vcib$r_lan_overlay_1.vcib$w_lan_client_flagsL#define vcib$l_lan_client_flags vcib$r_lan_overlay_1.vcib$l_lan_client_flagsU#define vcib$v_lan_rcv_lim vcib$r_lan_overlay_1.vcib$r_lan_flags_1.vcib$v_lan_rcv_limU#define Yvcib$v_lan_rcv_ics vcib$r_lan_overlay_1.vcib$r_lan_flags_1.vcib$v_lan_rcv_icsM#define vcib$v_lan_ftc vcib$r_lan_overlay_1.vcib$r_lan_flags_1.vcib$v_lan_ftcM#define vcib$v_lan_sfr vcib$r_lan_overlay_1.vcib$r_lan_flags_1.vcib$v_lan_sfrM#define vcib$v_lan_scc vcib$r_lan_overlay_1.vcib$r_lan_flags_1.vcib$v_lan_sccM#define vcib$v_lan_fpe vcib$r_lan_overlay_1.vcib$r_lan_flags_1.vcib$v_lan_fpeW#define vcib$v_lan_fp_rcvll vcib$r_lan_overlay_1.vcib$r_lan_flags_1.vcib$v_lan_fp_rcvllA#define vcib$r_lYan_overlay_2 vcib$r_lan_vcib.vcib$r_lan_overlay_2>#define vcib$l_lan_flags vcib$r_lan_overlay_2.vcib$l_lan_flagsU#define vcib$v_lan_rcv_dcb vcib$r_lan_overlay_2.vcib$r_lan_flags_2.vcib$v_lan_rcv_dcbW#define vcib$v_lan_dp_delay vcib$r_lan_overlay_2.vcib$r_lan_flags_2.vcib$v_lan_dp_delayS#define vcib$v_lan_mulseg vcib$r_lan_overlay_2.vcib$r_lan_flags_2.vcib$v_lan_mulsegW#define vcib$v_lan_fastpath vcib$r_lan_overlay_2.vcib$r_lan_flags_2.vcib$v_lan_fastpathM#define vcib$v_lan_tso vcib$r_lan_ovYerlay_2.vcib$r_lan_flags_2.vcib$v_lan_tsoM#define vcib$v_lan_lro vcib$r_lan_overlay_2.vcib$r_lan_flags_2.vcib$v_lan_lroU#define vcib$v_lan_ip_csum vcib$r_lan_overlay_2.vcib$r_lan_flags_2.vcib$v_lan_ip_csumY#define vcib$v_lan_ipv6_csum vcib$r_lan_overlay_2.vcib$r_lan_flags_2.vcib$v_lan_ipv6_csumY#define vcib$v_lan_sctp_csum vcib$r_lan_overlay_2.vcib$r_lan_flags_2.vcib$v_lan_sctp_csumY#define vcib$v_lan_ip_rxcsum vcib$r_lan_overlay_2.vcib$r_lan_flags_2.vcib$v_lan_ip_rxcsumS#define vcib$v_lan Y_txmbuf vcib$r_lan_overlay_2.vcib$r_lan_flags_2.vcib$v_lan_txmbuf5#define vcib$a_lan_ldc vcib$r_lan_vcib.vcib$a_lan_ldc9#define vcib$l_lan_oocnt vcib$r_lan_vcib.vcib$l_lan_oocnt=#define vcib$a_lan_dp_vcrp vcib$r_lan_vcib.vcib$a_lan_dp_vcrp5#define vcib$a_lan_hwa vcib$r_lan_vcib.vcib$a_lan_hwa5#define vcib$a_lan_pha vcib$r_lan_vcib.vcib$a_lan_pha9#define vcib$a_lan_reset vcib$r_lan_vcib.vcib$a_lan_resetG#define vcib$l_lan_dll_pref_cpu vcib$r_lan_vcib.vcib$l_lan_dll_pref_cpuM#define vcib Y$l_lan_client_pref_cpu vcib$r_lan_vcib.vcib$l_lan_client_pref_cpuA#define vcib$r_syn_vcib vcib$r_dll_vcib_additions.vcib$r_syn_vcib=#define vcib$a_syn_up_port vcib$r_syn_vcib.vcib$a_syn_up_portA#define vcib$r_syn_overlay_1 vcib$r_syn_vcib.vcib$r_syn_overlay_1L#define vcib$w_syn_client_flags vcib$r_syn_overlay_1.vcib$w_syn_client_flagsQ#define vcib$v_syn_unseq vcib$r_syn_overlay_1.vcib$r_syn_flags_1.vcib$v_syn_unseq"#endif /* #if !defined(__VAXC) */    $#pragma __member_alignmeYnt __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __VCIBDLLDEF_LOADED */ ww8[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIYAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This soYftware is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/********************************************************************* Y******//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */G/* Source: 24-JUL-2023 11:46:16 $1$DGA8345:[LIB_H.SRC]VCRPDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $VCRPDEF ***/#ifndef __VCRPDEF_LOADED#define __VCRPDEF_LOADED 1 G#pragma Y__nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_parYams ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* VCRP - VAX Communication Request Packet */N/* Y */N/* The VCRP is the data structure used to pass requests between VCMs. A */N/* single VCRP may traverse more than two VCMs. Only the common fields */N/* within the VCRP are defined here. All layer-specific fields are defined */N/* elsewhere. The common VCRP function codes are also defined here. */N/* */N/* THE FORMAT OF A VCRP DATA REQYUEST PACKET SHOULD NOT CHANGE WITHOUT */N/* CORRESPONDING CHANGES BEING MAY TO THE DCBE. */N/*- */N/* Function codes used in the VCRP$L_FUNCTION field. The function codes */N/* are separated numerically by layer as follows: */N/* */N/* 0000-01FF Common function codes from the VCI function Yal specification */N/* 0200-02FF DLL Data Link function codes */N/* 0300-03FF NRL Network Routing function codes */N/* 0400-04FF TPL Transport function codes */N/* 0500-05FF SCL Session function codes */N/* 0600-06FF APP Application function codes */#define VCRP$K_FC_ENABLE_PORT 0 #define VCRP$K_FC_DISABLE_PORT 1#define VCRP$K_F YC_GET 2#define VCRP$K_FC_SET 3#define VCRP$K_FC_TRANSMIT 4#define VCRP$K_FC_RECEIVE 5N/* Define the fields used within the STACK area of the VCRP. */#define STACK$K_STACK_HEADER 12N/* Size of Stack Header */N#define STACK$K_STACK_SIZE 240 /* Size of Stack in bytes */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment _ Y_longword#else#pragma __nomember_alignment#endiftypedef struct _vcrpstack {#pragma __nomember_alignmentN void *stack$l_lastused; /* Stack Last Used position pointer */N void *stack$l_btm; /* Stack Bottom */N void *stack$l_top; /* Stack Top */ char stack$t_stack [240];N/* Context stack */N/* Size of entire stack area Y */ } VCRPSTACK; #define STACK$S_VCRPSTACKDEF 252 #define vcrpstackdef _vcrpstackN/* VCRP data structure */N/* */N/* The common fields within the VCRP are defined now. The VCRP is created */N/* such that it can be used as an ACB, a DCBE, or a VCRP. So the fields at */N/* the beginning of the VCRP mimic the fields in theY ACB and the DCBE. */"#define VCRP$M_ACB_FLAGS_VALID 0x4#define VCRP$M_PKAST 0x10#define VCRP$M_NODELETE 0x20#define VCRP$M_QUOTA 0x40#define VCRP$M_KAST 0x80N#define VCRP$K_ACB_LENGTH 64 /* Length of VCRP ACB Block */#define VCRP$M_CMN_LOCKED 0x1#define VCRP$M_CMN_RETBUF 0x2#define VCRP$M_CMN_CACHE 0x4#define VCRP$M_CMN_MGMT 0x8*#define VCRP$K_DATA_INFORMATION_OFFSET 196(#define VCRP$K_DATA_INFORMATION_LENGTH 7)#define VCRP$K_MGMT_INFORMATION_OFFSET 8 Y4)#define VCRP$K_MGMT_INFORMATION_LENGTH 19&#define VCRP$K_CREATOR_DATA_OFFSET 228$#define VCRP$K_CREATOR_DATA_LENGTH 8(#define VCRP$K_INTERNAL_STACK_OFFSET 248(#define VCRP$K_INTERNAL_STACK_LENGTH 252&#define VCRP$K_SCRATCH_AREA_OFFSET 500%#define VCRP$K_SCRATCH_AREA_LENGTH 64N#define VCRP$K_FIXED_LENGTH 564 /* Length of fixed part of VCRP */N/* If this VCM contains data, it will start here or after here. */N#define VCRP$C_DATA 564 /* Offset into s Ytart of data */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _vcrp {#pragma __nomember_alignmentN void *vcrp$l_flink; /* Forward Queue link */N void *vcrp$l_blink; /* Backward Queue link */N unsigned short int vcrp$w_size; /* Size of structure Y */N unsigned char vcrp$b_type; /* Type of structure - DYN$C_VCRP */ __union {N unsigned char vcrp$b_rmod; /* Request Modifier for ACB */ __struct {N unsigned vcrp$v_mode : 2; /* Mode for final delivery */X unsigned vcrp$v_acb_flags_valid : 1; /* Flags in ACB_FLAGS cell are valid */, unsigned vcrpdef$$_filler_1 : 1;N unsigned vcrp$v_pkast : 1; /* Piggy back special kernel AST */N Y unsigned vcrp$v_nodelete : 1; /* Don't delete ACB on delivery */N unsigned vcrp$v_quota : 1; /* Account for quota */N unsigned vcrp$v_kast : 1; /* Special kernel AST */ } vcrp$r_rmod_bits; } vcrp$r_rmod_overlay;N unsigned int vcrp$l_pid; /* Process Identifier */ __union {P void (*vcrp$a_astadr)(); /* Address of 32-bit user AST routine */N int vcrp$l_acb64x_ofYfset; /* Offset to ACB64X extension */ } vcrp$r_astadr_overlay;N unsigned int vcrp$l_astprm; /* User 32-bit AST input parameter */e unsigned int vcrp$l_acb_flags; /* Flags for QAST, valid iff VCRP$V_ACB_FLAGS_VALID is set */N unsigned int vcrp$l_thread_id; /* Kernel thread ID */N void (*vcrp$a_kast)(); /* Special kernel mode AST routine */N/* This longword fill is used in the DCBE as a 4 byte scratch area Z*/N int vcrp$l_filler_2; /* fill to match ACB64 */c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void (*vcrp$pq_acb64_ast)(); /* 64-bit user A ZST routine address */#else$ unsigned __int64 vcrp$pq_acb64_ast;#endifO unsigned __int64 vcrp$q_acb64_astprm; /* 64-bit user AST parameter value */O unsigned __int64 vcrp$q_user_thread_id; /* Unique user thread identifier */#pragma __nomember_alignment __union {N unsigned short int vcrp$w_common_flags; /* Common flags */ __struct {N unsigned vcrp$v_cmn_locked : 1; /* Buffer is locked down */N unsigned vcrp$v_cmn_retb Zuf : 1; /* Return buffer immediately */N unsigned vcrp$v_cmn_cache : 1; /* Owner's cache buffer */N unsigned vcrp$v_cmn_mgmt : 1; /* Mgmt VCRP; not data VCRP */( unsigned vcrp$v_fill_2_ : 4;& } vcrp$r_common_flags_bit;& } vcrp$r_common_flags_overlay;N unsigned char vcrp$b_flags; /* User controlled VCRP flags */N unsigned char vcrp$b_mode; /* */R#ifdef __INITIAL_POIZNTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifR void *vcrp$a_dealloc_rtn; /* Address of VCRP deallocation routine */N/* */N/* This part of the VCRP contains the request specific information. */N/* VCRPs can contain either a Management request or a Data request. The */N/* type of VCRP Zrequest is determined by the VCRP$W_COMMON_FLAGS field. */N/* If VCRP$V_CMN_MGMT is set, then the VCRP is using the Management */N/* request format. IF VCRP$V_CMN_MGMT is NOT set, then the VCRP is */N/* using the Data request format. */N/* */ __struct { __union {N/* */N/* D Zata Request Format. The position of these field are to be the same */N/* as the DCB fields of the same name. */N/* */ __struct {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever p Ztr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */_ void *vcrp$pq_buffer_addr64; /* 64-bit buffer address (upper-level VCM only) */#else( unsigned __int64 vcrp$pq_buffer_addr64;#endif#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif[ Z void *vcrp$l_buffer_address; /* VM Address of buffer specified in SVAPTE */N void *vcrp$a_dcb_link; /* Address of next DCB in chain */Q unsigned int vcrp$l_boff; /* Offset to start of data in buffer */N unsigned int vcrp$l_bcnt; /* Byte count of data in buffer */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */S Z void *vcrp$pq_svapte_sva; /* Address of list of extents (EXT_PQ) */#else% unsigned __int64 vcrp$pq_svapte_sva;#endifc#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endif/ __int64 vcrp$q_fill_diobm [11];N/* */S/* All fields preceeding this comment should be  Zsimilar in layout,name and size */N/* to a DCB. A programmer should verify that these fields are similar by */N/* adding the appropriate ASSUMES to his or her code. */N/* */#pragma __nomember_alignmentN unsigned int vcrp$l_total_pdu_size; /* Total PDU Size */N/* This 7 byte portion of the data request area can be used by each */N/* layer to allow its client to pass m Zore information in the request. */1 char vcrp$t_data_information [7];& } vcrp$r_data_request;N/* */N/* Management Request Format. */I/* */ __struct {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer Z_size __short /* And set ptr size default to 32-bit pointers */#endifN void *vcrp$a_input_list; /* Address of Input item list */O void *vcrp$a_template_list; /* Address of Template item list */N void *vcrp$a_output_list; /* Address of Output item list */N/* This 19 byte portion of the mgmt request area can be used by each */N/* layer to allow its client to pass more information in the request. */2 char vcrp$t_ Zmgmt_information [19];& } vcrp$r_mgmt_request;% } vcrp$r_request_overlay;N unsigned char vcrp$b_les_flags; /* LES flags */ } vcrp$r_vcrp_request;N unsigned int vcrp$l_function; /* Function for this request */' unsigned int vcrp$l_association_id;& unsigned int vcrp$l_connection_id;O __union { /* Status of request upon completion */ __struct {3 unsigned __i Znt64 vcrp$q_request_status;" } vcrp$r_quad_request; __struct {/ unsigned int vcrp$l_request_status;4 unsigned int vcrp$l_request_status_qual;" } vcrp$r_long_request; } vcrp$r_status_overlay;N void *vcrp$a_creator; /* VCIB address of creator of VCRP */N/* The creator data section is a section that is used privately by the */N/* creator of the VCRP. */ Z__union {/ char vcrp$t_creator_data_structure [8]; __struct { __union { __struct {9 unsigned __int64 vcrp$q_creator_data;/ } vcrp$r_quad_creator_data; __struct {6 unsigned int vcrp$l_creator_data1;6 unsigned int vcrp$l_creator_data2;/ } vcrp$r_long_creator_data;. } vcrp$r_creator_data_overlay; } vcrpZ$r_fill_1_; } vcrp$r_fill_0_;N unsigned __int64 vcrp$q_les; /* LES information */N/* The following fields describe the VCRP context stack, which is used by */N/* by VCM's to preserve request context. The use of the fields is as */N/* follows: */N/* */J/* STACK - contains an address which will point to a stack blocZk. The */N/* stack block will contain the last used stack pointer */N/* (LASTUSED), the address of the end of the stack (BTM), the */N/* address of the top of the stack, and the stack itself */N/* (STACK). This is layout is used to insure that if the */N/* context stack is removed from the VCRP and allocated in a */N/* buffer pointed to by VCRP$A_STACK, that no VCM's will be */N/* Z adversely affected. */I/* LASTUSED - pointer to the last used location in the stack. */E/* BTM - pointer to the bottom of the stack */E/* TOP - pointer to the top of the stack */I/* STACK - Start of context stack. */N/* */N/* Saving on and restoring from the context stack can be done by Z using the */N/* VCRP_PUSH and VCRP_POP macros. */N void *vcrp$a_stack; /* Pointer stack block */% char vcrp$t_internal_stack [252];N/* VCRP scratch area. This area is not guaranteed to be preserved across */N/* VCM's. It is intended to be used as VCM temporary data. */ char vcrp$t_scratch [64];#if defined(__VAXC) char vcrp$t_data[];#else"#define vcrp$t_data vcrp$b_fill_3_"#endif Z /* #if defined(__VAXC) */ char vcrp$b_fill_3_ [4]; } VCRP; #if !defined(__VAXC)3#define vcrp$b_rmod vcrp$r_rmod_overlay.vcrp$b_rmodD#define vcrp$v_mode vcrp$r_rmod_overlay.vcrp$r_rmod_bits.vcrp$v_modeZ#define vcrp$v_acb_flags_valid vcrp$r_rmod_overlay.vcrp$r_rmod_bits.vcrp$v_acb_flags_validF#define vcrp$v_pkast vcrp$r_rmod_overlay.vcrp$r_rmod_bits.vcrp$v_pkastL#define vcrp$v_nodelete vcrp$r_rmod_overlay.vcrp$r_rmod_bits.vcrp$v_nodeleteF#define vcrp$v_quota vcrp$r_rmod_overlayZ.vcrp$r_rmod_bits.vcrp$v_quotaD#define vcrp$v_kast vcrp$r_rmod_overlay.vcrp$r_rmod_bits.vcrp$v_kast9#define vcrp$a_astadr vcrp$r_astadr_overlay.vcrp$a_astadrG#define vcrp$l_acb64x_offset vcrp$r_astadr_overlay.vcrp$l_acb64x_offsetK#define vcrp$w_common_flags vcrp$r_common_flags_overlay.vcrp$w_common_flags_#define vcrp$v_cmn_locked vcrp$r_common_flags_overlay.vcrp$r_common_flags_bit.vcrp$v_cmn_locked_#define vcrp$v_cmn_retbuf vcrp$r_common_flags_overlay.vcrp$r_common_flags_bit.vcrp$v_cmn_retbuZf]#define vcrp$v_cmn_cache vcrp$r_common_flags_overlay.vcrp$r_common_flags_bit.vcrp$v_cmn_cache[#define vcrp$v_cmn_mgmt vcrp$r_common_flags_overlay.vcrp$r_common_flags_bit.vcrp$v_cmn_mgmtI#define vcrp$r_request_overlay vcrp$r_vcrp_request.vcrp$r_request_overlayF#define vcrp$r_data_request vcrp$r_request_overlay.vcrp$r_data_requestG#define vcrp$pq_buffer_addr64 vcrp$r_data_request.vcrp$pq_buffer_addr64G#define vcrp$l_buffer_address vcrp$r_data_request.vcrp$l_buffer_address;#define vcrp$a_dZcb_link vcrp$r_data_request.vcrp$a_dcb_link3#define vcrp$l_boff vcrp$r_data_request.vcrp$l_boff3#define vcrp$l_bcnt vcrp$r_data_request.vcrp$l_bcntA#define vcrp$pq_svapte_sva vcrp$r_data_request.vcrp$pq_svapte_svaG#define vcrp$l_total_pdu_size vcrp$r_data_request.vcrp$l_total_pdu_sizeK#define vcrp$t_data_information vcrp$r_data_request.vcrp$t_data_informationF#define vcrp$r_mgmt_request vcrp$r_request_overlay.vcrp$r_mgmt_request?#define vcrp$a_input_list vcrp$r_mgmt_request.vcrp$a_input_l ZistE#define vcrp$a_template_list vcrp$r_mgmt_request.vcrp$a_template_listA#define vcrp$a_output_list vcrp$r_mgmt_request.vcrp$a_output_listK#define vcrp$t_mgmt_information vcrp$r_mgmt_request.vcrp$t_mgmt_information=#define vcrp$b_les_flags vcrp$r_vcrp_request.vcrp$b_les_flagsE#define vcrp$r_quad_request vcrp$r_status_overlay.vcrp$r_quad_requestG#define vcrp$q_request_status vcrp$r_quad_request.vcrp$q_request_statusE#define vcrp$r_long_request vcrp$r_status_overlay.vcrp$r_long_requestGZ#define vcrp$l_request_status vcrp$r_long_request.vcrp$l_request_statusQ#define vcrp$l_request_status_qual vcrp$r_long_request.vcrp$l_request_status_qual]#define vcrp$r_creator_data_overlay vcrp$r_fill_0_.vcrp$r_fill_1_.vcrp$r_creator_data_overlayU#define vcrp$r_quad_creator_data vcrp$r_creator_data_overlay.vcrp$r_quad_creator_dataH#define vcrp$q_creator_data vcrp$r_quad_creator_data.vcrp$q_creator_dataU#define vcrp$r_long_creator_data vcrp$r_creator_data_overlay.vcrp$r_long_creator_dataJ#dZefine vcrp$l_creator_data1 vcrp$r_long_creator_data.vcrp$l_creator_data1J#define vcrp$l_creator_data2 vcrp$r_long_creator_data.vcrp$l_creator_data2"#endif /* #if !defined(__VAXC) */ #define VCRP$S_VCRPDEF 568  #define vcrpdef _vcrp $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus Z }#endif#pragma __standard #endif /* __VCRPDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prioZr written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission oZf VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:20 by OpenVMS SDL V3.7 */G/* Source: 26-JAN-2022 Z23:16:38 $1$DGA8345:[LIB_H.SRC]LANUDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $VCRPLANDEF ***/#ifndef __VCRPLANDEF_LOADED#define __VCRPLANDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#praZgma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifnZdef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*++ */N/* LAN definitions that are embedded in the standard VCRP fields */N/*-- */ #define VCRP$K_FC_DLL_BASE 512%#define VCRP$K_FC_SYN_ENTER_MAINT 512$#define VCRP$K_FC_SYN_EXIT_MAINT 513#define VCRP$K_FC_X25_RESET 514 Z##define VCRP$K_FC_X25_ACK_NOCOM 515%#define VCRP$K_FC_LAN_CHANGE_PORT 516#define VCRP$K_FC_DLL_LAST 517N/* Data Link event codes */#define VCRP$K_EC_DLL_BASE 4608&#define VCRP$K_EC_DLL_PORT_USABLE 4608(#define VCRP$K_EC_DLL_PORT_UNUSABLE 4609&#define VCRP$K_EC_LAN_NEW_ADDRESS 4610)#define VCRP$K_EC_LAN_RCV_CONGESTION 4611'#define VCRP$K_EC_LAN_RCV_PDU_LOST 4612*#define VCRP$K_EC_SYN_STATION_DELETED 4613)#define VCRP$K_EC_X25_INCOMI !ZNG_RESET 4614)#define VCRP$K_EC_X25_INCOMING_NOCOM 4615'#define VCRP$K_EC_LAN_RESTART_FAIL 4616*#define VCRP$K_EC_LAN_STATION_RENAMED 4617(#define VCRP$K_EC_LAN_RCVBUF_CHANGE 4618#define VCRP$K_EC_DLL_LAST 4619+#define VCRP$K_EC_DLL_PREF_CPU_CHANGED 4620N/* Since we need to overlay many fields, we will do each field in a */#define VCRP$M_LAN_T_MORE 0x1N#define VCRP$L_LAN_802XMT 520 /* 802.2 XMT parameters */##define VCRP$M_LAN_FLTR_STARTUP 0x1##define "ZVCRP$M_LAN_FLTR_INTXMIT 0x2#define VCRP$M_LAN_FLTR_DAT 0x4##define VCRP$M_LAN_FLTR_EXPLORE 0x8#define VCRP$M_LAN_CHAINED 0x1#define VCRP$M_LAN_SVAPTE 0x2#define VCRP$T_LAN_DATA 624 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _vcrplandef {N/* First we will define all the function codes and all the event codes */N/* use#Zd specifically by the data links. */N/* Data Link function codes */N/* separate overlay. That way, we can do them in any order. */#pragma __nomember_alignment __union {N/*======================================================================== */N/* Data Request - For receive, LAN needs a field that will point to the */N/* data link header. For transmit, we need a flag for the MORE bi $Zt. For */N/* both we need the FC field for FDDI. And AC and FC fields for TR. */ __struct {* char vcrp$b_lan_filler1 [196]; __union {Q void *vcrp$a_lan_r_header; /* Address of receive packet header */ __union {4 unsigned int vcrp$l_lan_t_flags; __struct {N/* Flags for transmit */_ unsigned vcrp$v_la %Zn_t_more : 1; /* More transmit requests are coming */4 unsigned vcrp$v_fill_7_ : 7;) } vcrp$r_fill_6_;% } vcrp$r_fill_5_;) } vcrp$r_vcrpreq_overlay; __union {N unsigned char vcrp$b_lan_fc; /* FC value for FDDI xmit/recv */N unsigned int vcrp$l_lan_fc; /* FC value for FDDI xmit/recv */ __struct {N unsigned char vcrp$b_tr_ac; /* AC &Zfor TR xmit/recv */N unsigned char vcrp$b_tr_fc; /* FC for TR xmit/recv */, } vcrp$r_lan_tr_overlay;( } vcrp$r_lan_fc_overlay;* } vcrp$r_vcrplan_data_request;N/*======================================================================== */N/* Mgmt Request - LAN needs the P2 buffer fields. */ __struct {) char vcrp$b_lan_filler2 [84];N unsigned int vcrp$l_lan_p2buff 'Z_size; /* LAN P2 buffer size */N void *vcrp$a_lan_p2buff; /* LAN P2 buffer */* } vcrp$r_vcrplan_mgmt_request;N/*======================================================================== */N/* Scratch area - LAN needs many fields here. */ __struct {* char vcrp$b_lan_filler3 [500];N/* Note: We are longword aligned now. But we are not quadword aligned. */N/* The following fields are common to (Zall VCRP requests. */O unsigned int vcrp$l_lan_function; /* S-Function for this request */N void *vcrp$a_lan_ucb; /* S-Address of UCB */N unsigned int vcrp$l_lan_port1; /* Port specific longword */N/* Note: We should be quadword aligned now. */N/* The following fields are defined for use by either the transmit code */N/* or the receive code. )Z */ __union {N/* The following fields are for transmit only. */ __struct {N/* For transmit requests, we need the following fields to be initialized */N/* by the upper VCM. These fields could not fit in the request area, so */N/* they are included here in the scratch area. */Q unsigned __int64 vcrp$q_lan_t_dest; /* Destination address */N unsigned s*Zhort int vcrp$w_lan_t_ctl; /* 802.2 ctl field */Y unsigned char vcrp$b_lan_t_ctl_size; /* 802.2 ctl field value size */N unsigned char vcrp$b_lan_t_dsap; /* 802.2 XMT dest. sap */U unsigned int vcrp$l_lan_t_resp; /* 802.2 command/response flag */N/* During the transmit request, the following fields are initialized and */N/* used by the transmit code in the LAN drivers. */ __union {] +Z unsigned int vcrp$l_lan_t_filter; /* S-Transmit filtering longword */# __struct {a unsigned vcrp$v_lan_fltr_startup : 1; /* Delete VCRP, complete IRP */` unsigned vcrp$v_lan_fltr_intxmit : 1; /* Add VCRP to Receive list */_ unsigned vcrp$v_lan_fltr_dat : 1; /* Duplicate Address Test VCRP */U unsigned vcrp$v_lan_fltr_explore : 1; /* Explorer VC ,ZRP */8 unsigned vcrp$v_fill_8_ : 4;5 } vcrp$r_fl_lan_t_filter;1 } vcrp$r_un_lan_t_filter; __union {N unsigned int vcrp$l_lan_flags; /* S-Flags */# __struct {V unsigned vcrp$v_lan_chained : 1; /* Transmit is chained */\ unsigned vcrp$v_lan_svapte : 1; /* 2nd entry uses SVAPTE/BOFF */8-Z unsigned vcrp$v_fill_9_ : 6;2 } vcrp$r_fl_lan_flags;. } vcrp$r_un_lan_flags;N/* When the CHAINED bit is set, the following fields are used to get to */N/* the second buffer in the chain. DCBBCNT has the number of bytes in */N/* the second entry. Either DCBSVA or DCBSVAPTE/DCBBOFF are used to */N/* locate the buffer. Use DCBSVA if the SVAPTE flag is clear. Use */N/* DCBSVAPTE/DCBBOFF if the .ZSVAPTE flag is set. */N unsigned int vcrp$l_lan_dcbbcnt; /* Size of 2nd entry */ __union {N unsigned int vcrp$l_lan_dcbsva; /* SVA of 2nd entry */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */b void *vcrp$pq_lan_dcbsvapte_sva; /* Address of list of extents /Z (EXT_PQ) */#else, unsigned __int64 vcrp$pq_lan_dcbsvapte_sva;#endif, } vcrp$r_lan_union1;N unsigned int vcrp$l_lan_dcbboff; /* BOFF of 2nd entry */N/* If requested, we will save the buffer descriptor fields here on a */N/* transmit request so that we can restore them when we are finished. */N unsigned int vcrp$l_lan_sboff; /* Saved BOFF value */N unsigned int vcrp$l_lan_sbcnt; /* Saved BCNT0Z value */R unsigned int vcrp$l_lan_stps; /* Saved TOTAL_PDU_SIZE value */- } vcrp$r_st_lan_transmit;N/* The following fields are for receive only. */ __struct {V unsigned int vcrp$l_lan_diag_flags; /* Diagnostic receive flags */Q unsigned int vcrp$l_lan_lenerr; /* Diagnostic receive info */T unsigned int vcrp$l_lan_pkformat; /* Packet format (prm 1Zonly) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *vcrp$a_lan_r_802hdr; /* Address of 802 header */, } vcrp$r_st_lan_receive;( } vcrp$r_un_lan_scratch;% } vcrp$r_vcrplan_scratch;N/*======================================================================== */N/* Receive PDU area - 2ZWe will define the fields that describe the */N/* fields in the received frames. Note that the DA must be QUADWORD */N/* aligned for some devices. */ __struct {N/* Align the LAN data field to be quadword aligned. */* char vcrp$b_lan_filler4 [624];N/* Now define the generic "beginning of receive data" field */$ } vcrp$r_vcrplan_rcvpdu;! } vcrp$r_vcrplan 3Z_overlay; } VCRPLANDEF; #if !defined(__VAXC)V#define vcrp$r_vcrplan_data_request vcrp$r_vcrplan_overlay.vcrp$r_vcrplan_data_requestQ#define vcrp$r_vcrpreq_overlay vcrp$r_vcrplan_data_request.vcrp$r_vcrpreq_overlayF#define vcrp$a_lan_r_header vcrp$r_vcrpreq_overlay.vcrp$a_lan_r_headerS#define vcrp$l_lan_t_flags vcrp$r_vcrpreq_overlay.vcrp$r_fill_5_.vcrp$l_lan_t_flags`#define vcrp$v_lan_t_more vcrp$r_vcrpreq_overlay.vcrp$r_fill_5_.vcrp$r_fill_6_.vcrp$v_lan_t_moreO#define vcrp$r_lan_f4Zc_overlay vcrp$r_vcrplan_data_request.vcrp$r_lan_fc_overlay9#define vcrp$b_lan_fc vcrp$r_lan_fc_overlay.vcrp$b_lan_fc9#define vcrp$l_lan_fc vcrp$r_lan_fc_overlay.vcrp$l_lan_fcI#define vcrp$r_lan_tr_overlay vcrp$r_lan_fc_overlay.vcrp$r_lan_tr_overlay7#define vcrp$b_tr_ac vcrp$r_lan_tr_overlay.vcrp$b_tr_ac7#define vcrp$b_tr_fc vcrp$r_lan_tr_overlay.vcrp$b_tr_fcV#define vcrp$r_vcrplan_mgmt_request vcrp$r_vcrplan_overlay.vcrp$r_vcrplan_mgmt_requestQ#define vcrp$l_lan_p2buff_size vcrp$r_vcrpla5Zn_mgmt_request.vcrp$l_lan_p2buff_sizeG#define vcrp$a_lan_p2buff vcrp$r_vcrplan_mgmt_request.vcrp$a_lan_p2buffL#define vcrp$r_vcrplan_scratch vcrp$r_vcrplan_overlay.vcrp$r_vcrplan_scratchF#define vcrp$l_lan_function vcrp$r_vcrplan_scratch.vcrp$l_lan_function<#define vcrp$a_lan_ucb vcrp$r_vcrplan_scratch.vcrp$a_lan_ucb@#define vcrp$l_lan_port1 vcrp$r_vcrplan_scratch.vcrp$l_lan_port1J#define vcrp$r_un_lan_scratch vcrp$r_vcrplan_scratch.vcrp$r_un_lan_scratchK#define vcrp$r_st_lan_transmit vcrp$r_6Zun_lan_scratch.vcrp$r_st_lan_transmitB#define vcrp$q_lan_t_dest vcrp$r_st_lan_transmit.vcrp$q_lan_t_dest@#define vcrp$w_lan_t_ctl vcrp$r_st_lan_transmit.vcrp$w_lan_t_ctlJ#define vcrp$b_lan_t_ctl_size vcrp$r_st_lan_transmit.vcrp$b_lan_t_ctl_sizeB#define vcrp$b_lan_t_dsap vcrp$r_st_lan_transmit.vcrp$b_lan_t_dsapB#define vcrp$l_lan_t_resp vcrp$r_st_lan_transmit.vcrp$l_lan_t_respL#define vcrp$r_un_lan_t_filter vcrp$r_st_lan_transmit.vcrp$r_un_lan_t_filterF#define vcrp$l_lan_t_filter vcrp$r_un_lan_7Zt_filter.vcrp$l_lan_t_filterL#define vcrp$r_fl_lan_t_filter vcrp$r_un_lan_t_filter.vcrp$r_fl_lan_t_filterN#define vcrp$v_lan_fltr_startup vcrp$r_fl_lan_t_filter.vcrp$v_lan_fltr_startupN#define vcrp$v_lan_fltr_intxmit vcrp$r_fl_lan_t_filter.vcrp$v_lan_fltr_intxmitF#define vcrp$v_lan_fltr_dat vcrp$r_fl_lan_t_filter.vcrp$v_lan_fltr_datN#define vcrp$v_lan_fltr_explore vcrp$r_fl_lan_t_filter.vcrp$v_lan_fltr_exploreF#define vcrp$r_un_lan_flags vcrp$r_st_lan_transmit.vcrp$r_un_lan_flags=#define vcrp$l8Z_lan_flags vcrp$r_un_lan_flags.vcrp$l_lan_flagsC#define vcrp$r_fl_lan_flags vcrp$r_un_lan_flags.vcrp$r_fl_lan_flagsA#define vcrp$v_lan_chained vcrp$r_fl_lan_flags.vcrp$v_lan_chained?#define vcrp$v_lan_svapte vcrp$r_fl_lan_flags.vcrp$v_lan_svapteD#define vcrp$l_lan_dcbbcnt vcrp$r_st_lan_transmit.vcrp$l_lan_dcbbcntB#define vcrp$r_lan_union1 vcrp$r_st_lan_transmit.vcrp$r_lan_union1=#define vcrp$l_lan_dcbsva vcrp$r_lan_union1.vcrp$l_lan_dcbsvaM#define vcrp$pq_lan_dcbsvapte_sva vcrp$r_lan_union9Z1.vcrp$pq_lan_dcbsvapte_svaD#define vcrp$l_lan_dcbboff vcrp$r_st_lan_transmit.vcrp$l_lan_dcbboff@#define vcrp$l_lan_sboff vcrp$r_st_lan_transmit.vcrp$l_lan_sboff@#define vcrp$l_lan_sbcnt vcrp$r_st_lan_transmit.vcrp$l_lan_sbcnt>#define vcrp$l_lan_stps vcrp$r_st_lan_transmit.vcrp$l_lan_stpsI#define vcrp$r_st_lan_receive vcrp$r_un_lan_scratch.vcrp$r_st_lan_receiveI#define vcrp$l_lan_diag_flags vcrp$r_st_lan_receive.vcrp$l_lan_diag_flagsA#define vcrp$l_lan_lenerr vcrp$r_st_lan_receive.vcrp$l_lan :Z_lenerrE#define vcrp$l_lan_pkformat vcrp$r_st_lan_receive.vcrp$l_lan_pkformatE#define vcrp$a_lan_r_802hdr vcrp$r_st_lan_receive.vcrp$a_lan_r_802hdrJ#define vcrp$r_vcrplan_rcvpdu vcrp$r_vcrplan_overlay.vcrp$r_vcrplan_rcvpdu"#endif /* #if !defined(__VAXC) */    $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#e;Zndif#ifdef __cplusplus }#endif#pragma __standard #endif /* __VCRPLANDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyoZ */F/* Source: 08-FEB-1994 14:02:38 $1$DGA8345:[LIB_H.SRC]VECDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $VECDEF ***/#ifndef __VECDEF_LOADED#define __VECDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas su?Zpported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif@Z#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* CRB INTERRUPT TRANSFER VECTOR STRUCTURE DEFINITIONS */N/*- */  9#ifdef __cplusplus /* Define structure prototypes */ struct _idb; struct _adp; #endif /* #ifdef __cplusplus */ AZ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _vec {N/*CRB INTERRUPT TRANSFER VECTOR */#pragma __nomember_alignment\ void *vec$ps_isr_code; /*address of Interrupt Service Routine Code entry */P void (*vec$ps_isr_pd)(); /*address of ISR Procedure Descriptor */N BZ struct _idb *vec$l_idb; /*ADDRESS OF ASSOCIATED IDB */N struct _adp *vec$ps_adp; /*ADDRESS OF ADP */ } VEC;N#define VEC$K_LENGTH 16 /*LENGTH OF STANDARD DISPATCHER */N#define VEC$C_LENGTH 16 /*LENGTH OF STANDARD DISPATCHER */P#define S_VECDEF 16 /*OLD VEC SIZE NAME FOR COMPATIBILITY */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined wheneverCZ ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __VECDEF_LOADED */ ww #[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** liceDZnsed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed EZby VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//*********************************************************** FZ*********************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */F/* Source: 21-APR-1993 09:59:04 $1$DGA8345:[LIB_H.SRC]VL1DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $VL1DEF ***/#ifndef __VL1DEF_LOADED#define __VL1DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma GZ__member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...HZ#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* VOL1 ANSI MAGNETIC TAPE LABEL */N/* THIS IS THE FIRST BLOCK ON EVERY ANSI LABELED MAGNETIC TAPE. */N IZ/* IT IDENTIFIES THE VOLUME AND ITS PROTECTION. */N/*- */#define VL1$S_VL1DEF 80 typedef struct _vl1 {P unsigned int vl1$l_vl1lid; /*LABEL IDENTIFIER AND NUMBER 'VOL1' */N char vl1$t_vollbl [6]; /*VOLUME LABEL */N unsigned char vl1$b_volaccess; /*VOLUME ACCESS */N char vl1def$$_fill_1 [13]; /*SPACES JZ */N char vl1$t_syscode [13]; /* SYSTEM CODE */ __union {N char vl1$t_owner_ident [14]; /* VOL1 OWNER ID FIELD */ __struct {N char vl1$t_volowner [13]; /*VOLUME OWNER IDENTIFICATION */N unsigned char vl1$b_decstdver; /*DEC STANDARD VERSION */! } vl1$r_old_volowner; } vl1$r_owner_union;N char vl1def$$_fill_2 [28]; /*SPACES KZ */N unsigned char vl1$b_lblstdver; /*LABEL STANDARD VERSION '3' */ } VL1; #if !defined(__VAXC)=#define vl1$t_owner_ident vl1$r_owner_union.vl1$t_owner_identJ#define vl1$t_volowner vl1$r_owner_union.vl1$r_old_volowner.vl1$t_volownerL#define vl1$b_decstdver vl1$r_owner_union.vl1$r_old_volowner.vl1$b_decstdver"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr sizLZe pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __VL1DEF_LOADED */ ww0J[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by MZHewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS SNZoftware, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//******************************************************************* OZ*************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */F/* Source: 19-APR-1993 15:00:21 $1$DGA8345:[LIB_H.SRC]VL2DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $VL2DEF ***/#ifndef __VL2DEF_LOADED#define __VL2DEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __memberPZ_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endifQZ #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* VOL2 ANSI MAGNETIC TAPE LABEL */N/* THIS IS BLOCK IS WRITTEN TO TAPES WHEN A VMS PROTECTION IS SPECIFIED */N/*- RZ */#define VL2$S_VL2DEF 19 typedef struct _vl2 {P unsigned int vl2$l_vl2lid; /*LABEL IDENTIFIER AND NUMBER 'VOL2' */N char vl2$t_volowner [15]; /*VOLUME OWNER IDENTIFICATION */ } VL2; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined reSZquired ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __VL2DEF_LOADED */ ww@q[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated ORTZ disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone withoUZut **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by Open VZVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE VLANDATADEF ***/#ifndef __VLANDATADEF_LOADED#define __VLANDATADEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* DefiWZned whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __XZstruct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif `/* SDL has a bug which causes the BLISSF file to produce invalid VLD fields (missing commas). */O/* Workaround is to not allow it to produce a BLISSF definition for the LSB. */ N/* */P/* This structure is used to send commands between LANCP and the VLAN driv YZer. */N/* */#define VLD$C_VTAG_OFFSET 16#define VLD$C_VFLAGS_OFFSET 20N#define VLD$C_BIND 256 /* BIND to a physical device */N#define VLD$C_UNBIND 257 /* UNBIND it */N#define VLD$C_DESCRIPTION 258 /* Update the description field */#define VLD$C_UNTCNT_OFFSET 24 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre ZZDECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _vdata {#pragma __nomember_alignment __union {N unsigned __int64 vld$q_physical_device [2]; /* Physical device name */N char vld$t_physdev_name [16]; /* Physical device name */ } vld$r_phydev; unsigned int vld$l_vtag; __union {N unsigned int vld$l_command; /* LANCP command to execute */N unsi [Zgned int vld$l_vflags; /* Return value from the driver */ } vld$r_cmdu;T unsigned int vld$l_untcnt; /* Unit count, how many clients connected */ char vld$b_fill_19_ [4]; } VDATA; #if !defined(__VAXC)@#define vld$q_physical_device vld$r_phydev.vld$q_physical_device:#define vld$t_physdev_name vld$r_phydev.vld$t_physdev_name.#define vld$l_command vld$r_cmdu.vld$l_command,#define vld$l_vflags vld$r_cmdu.vld$l_vflags"#endif /* #if !defined(__VAXC) */ \Z#define VLD$C_LENGTH 32#define VLD$K_LENGTH 32  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard !#endif /* __VLANDATADEF_LOADED */ ww`[UM/***************************************************************************/M/** ]Z **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** ^Z **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** _Z **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */G/* Source: 25-JAN-2024 13:59:40 $1$DGA8345:[LIB_H.SRC]LANIDEF.SDL;1 *//********************************************************************************************************************************//*** M `ZODULE $VLANDEF ***/#ifndef __VLANDEF_LOADED#define __VLANDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #iaZfdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N#define VLAN$C_DEFAULT_VTAG 0 /* Default VLAN tag */bZN#define VLAN$C_TABLE_SZ 16384 /* Size of the VLAN table in bytes */#define VLAN$M_CFI 4096#define VLAN$M_VTAG_MASK 4095N/*++ */M/* VLAN block: One LSB is created to service a single unique VLAN tag. */N/* */X/* There are 1 to 1@12 - 1 vlan tags available, so create this array of LSB per tags. */Y/* The tag number is the index into cZthe array where one can find the LSB servicing the */N/* tag as LAN virtual adapter. */N/*-- */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _vlan {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Define dZd whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *vlan$pq_flink; /* Fields maintained for */#else unsigned __int64 vlan$pq_flink;#endifR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *vlan$pq_blink; /* compatability eZ */#else unsigned __int64 vlan$pq_blink;#endifN unsigned short int vlan$w_size; /* Structure size in bytes */N unsigned char vlan$b_type; /* Structure type */N unsigned char vlan$b_subtype; /* Subtype */ __union {c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#end fZifN unsigned __int64 vlan$q_flags; /* Flags quadword */#pragma __nomember_alignment __struct { __union {N unsigned int vlan$l_flag1; /* 1st Flags longword */ __struct {N unsigned vlan$v_reserved_flag1 : 32; /* Filler */( } vlan$r_flag1_bits; } vlan$r_flag1; __union {N unsigned int vlan$l_flag2; /* 2nd Flags gZlongword */ __struct {N unsigned vlan$v_reserved_flag2 : 32; /* Filler */( } vlan$r_flag2_bits; } vlan$r_flag2; } vlan$r_flag_ints; } vlan$r_flags;N unsigned int vlan$l_default_vtag; /* Default VLAN tag */N unsigned int vlan$l_refcnt; /* Reference count */N unsigned int vlan$l_prm; /* Promiscous mode hZ*/N unsigned int vlan$l_dropped; /* Dropped receives */N unsigned int vlan$l_dropped_tag; /* Tag of last dropped receive */" unsigned int vlan$l_reserved1;" unsigned int vlan$l_reserved2;" unsigned int vlan$l_reserved3;" unsigned int vlan$l_reserved4;" unsigned int vlan$l_reserved5;" unsigned int vlan$l_reserved6;" unsigned int vlan$l_reserved7;" unsigned int vlan$l_reserved8;R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever p iZtr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void *vlan$ps_untagged_lsb; /* Untagged LSB */N void *vlan$ps_logical_lsb [4096]; /* One VLAN_LSB per VLAN tag */ char vlan$b_fill_18_ [4]; } VLAN; #if !defined(__VAXC).#define vlan$q_flags vlan$r_flags.vlan$q_flagsL#define vlan$l_flag1 vlan$r_flags.vlan$r_flag_ints.vlan$r_flag1.vlan$l_flag1L#define vlan$l_f jZlag2 vlan$r_flags.vlan$r_flag_ints.vlan$r_flag2.vlan$l_flag2"#endif /* #if !defined(__VAXC) */ #define VLAN$C_LENGTH 16472#define VLAN$K_LENGTH 16472 N#define VLAN$S_VLAN 16472 /* Constant for structure size */#ifdef __INITIAL_POINTER_SIZEG#pragma __required_pointer_size __save /* Save current pointer size */A#pragma __required_pointer_size __long /* Pointers are 64-bit */Gtypedef struct _vlan *VLAN_PQ; /* Long pointer to a VLAN structure */Htypedef stru kZct _vlan **VLAN_PPQ; /* Long pointer to a VLAN structure */O#pragma __required_pointer_size __restore /* Return to previous pointer size */#else!typedef unsigned __int64 VLAN_PQ;"typedef unsigned __int64 VLAN_PPQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __clZplusplus }#endif#pragma __standard #endif /* __VLANDEF_LOADED */ ww [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **mZ/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written nZpermission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */F/* Source: oZ25-FEB-1994 08:30:24 $1$DGA8345:[LIB_H.SRC]VLEDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $VLEDEF ***/#ifndef __VLEDEF_LOADED#define __VLEDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragmpZa __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifnde qZf __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* */N/* VLE (Vector List Extension) */N/* This structure is used to hold the list of interrupt vectors used by a */N/* particular controller when the controller requires more than one vector. */N/* If the VLE flag in an IDB is set, the field IDB$L_VECTOR points trZo this */N/* structure. */N/* */#define VLE$K_LENGTH 12#define VLE$C_LENGTH 12N#define VLE$S_VLEDEF 12 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _idb; #endif /* #ifdef __cplusplus */ typedef struct _vle {N struct _idb *vle$ps_idb; /* pointer to paresZnt IDB */Q unsigned int vle$l_numvec; /* number of vector entries in the VLE */N unsigned short int vle$w_size; /* size of this structure */N unsigned char vle$b_type; /* structure type */N unsigned char vle$b_subtype; /* structure subtype */N/* VECTOR_LIST is an array of unsigned longwords containing the appropriate */N/* byte offset into either the SCB or the ADP vector table. */N tZ/* put the constant's in front of the definition of vector list so that the */N/* header size constants stay the same. */P int vle$l_vector_list [1]; /* beginning of interrupt vector list */ } VLE; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplusuZ }#endif#pragma __standard #endif /* __VLEDEF_LOADED */ ww4[U8/* This file was created by [LIB_H]VMS$DEFS_LIB_H.COM *//* for the X86 build. *//* #define VMS$PFNBITS_32 1 */#ifndef VMS$DEFS__LOADED#define VMS$DEFS__LOADED#define VMS$PFNBITS_64 1#define NMSP$64P 1#define VMS$SVAPTE 0#define VMS$SWAP_SUPPORT 0#endifww[UM/***************************************************************************/M/** vZ **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** wZ **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/*xZ**************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:11 by OpenVMS SDL V3.7 */F/* Source: 14-NOV-2008 16:48:53 $1$DGA8345:[LIB_H.SRC]F11DEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $VSLDEF ***/#i yZfndef __VSLDEF_LOADED#define __VSLDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus exzZtern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* {Z */N/* Structure of a volume set list file entry. Record 1 contains the volume */P/* set name. Record n+1 contains the volume label of RVN n in the volume set. */N/* */N/*- */ #define VSL$K_LENGTH 64#define VSL$C_LENGTH 64N#define VSL$S_VSLDEF 64 /* Old size name - synonym |Z */ typedef struct _vsl {N char vsl$t_name [12]; /* volume name */N char vsl$$_fill_1 [52]; /* unused */ } VSL;  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard }Z#endif /* __VSLDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. ~Z **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. Z **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:23:36 by OpenVMS SDL V3.7 */F/* Source: 22-DEC-2017 10:52:46 $1$DGA8345:[LIB_H.SRC]WBMDEF. ZSDL;1 *//********************************************************************************************************************************//*** MODULE $WBMDEF ***/#ifndef __WBMDEF_LOADED#define __WBMDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the preZviously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union Zunion#else#define __union variant_union#endif#endif #define WBM$K_MAX_BITMAPS 12"#define WBM$K_MAX_BITMAPS_GROUP1 6##define WBM$K_MAX_BITMAPS_GROUP2 12#define WBM$K_MAX_NAMLEN 64V#define WBMSG$K_MAX_SET_RQSTS 9 /* based on the max msg size in cluster.sdl */V#define WBM$K_LWORDS_PER_BUFF 27 /* based on the max msg size in cluster.sdl */#define WBM$M_VERSION 15#define WBM$K_MSG_V1 1#define WBM$K_CLU_FAC_V1 127 #ifndef __NEW_STARLET#define __NEW_STARLEZT#define __NEW_STARLET_LOCALDEF#endif#include #include #ifdef __NEW_STARLET_LOCALDEF#undef __NEW_STARLET#undef __NEW_STARLET_LOCALDEF#endifN/*+ */N/* Flags argument to $START_BITMAP */N/*- */#define WBM$M_GROUP1 0x1#define WBM$M_GROUP2 0x2#define WBM$M_GROUP3 0x4#d Zefine WBM$M_MINICOPY 0x100#define WBM$M_HBMM 0x200 typedef union _startdef { __struct {N unsigned wbm$v_group1 : 1; /* Use first group of bitmap slots */N unsigned wbm$v_group2 : 1; /* Use second group of bitmap slots */N unsigned wbm$v_group3 : 1; /* Use all bitmap slots */N unsigned wbm$v_fill_3_to_7 : 5; /* unused */N unsigned wbm$v_minicopy : 1; /* This is a minicopy bitmap */N Z unsigned wbm$v_hbmm : 1; /* This is a hbmm bitmap */v unsigned wbm$v_unused : 22 /** WARNING: bitfield array has been reduced to a string **/ ; /* Reserved flags */ } wbm$r_startdef_bits;N unsigned int wbm$l_startdef_overlay; /* Longword overlay */ } STARTDEF; #if !defined(__VAXC)5#define wbm$v_group1 wbm$r_startdef_bits.wbm$v_group15#define wbm$v_group2 wbm$r_startdef_bits.wbm$v_group25#define wbm$v_group3 wbm$r_startdef_bits Z.wbm$v_group3?#define wbm$v_fill_3_to_7 wbm$r_startdef_bits.wbm$v_fill_3_to_79#define wbm$v_minicopy wbm$r_startdef_bits.wbm$v_minicopy1#define wbm$v_hbmm wbm$r_startdef_bits.wbm$v_hbmm5#define wbm$v_unused wbm$r_startdef_bits.wbm$v_unused"#endif /* #if !defined(__VAXC) */ N/*+ */N/* POLICY argument to $START_BITMAP */N/*- Z */ typedef union _policydef { __struct {N unsigned char wbm_pol$b_sub_group; /* pointer to sub_group */N unsigned char wbm_pol$b_amccnt; /* pointer to amccnt */N unsigned char wbm_pol$b_dmtcnt; /* HBMM_DMT */N unsigned char wbm_pol$b_unused; /* Spare */# } wbm_pol$r_policy_overlay;N unsigned int wbm_pol$l_policy_overlay; /* Longword overlay Z */ } POLICYDEF; #if !defined(__VAXC)H#define wbm_pol$b_sub_group wbm_pol$r_policy_overlay.wbm_pol$b_sub_groupB#define wbm_pol$b_amccnt wbm_pol$r_policy_overlay.wbm_pol$b_amccntB#define wbm_pol$b_dmtcnt wbm_pol$r_policy_overlay.wbm_pol$b_dmtcntB#define wbm_pol$b_unused wbm_pol$r_policy_overlay.wbm_pol$b_unused"#endif /* #if !defined(__VAXC) */ N/*+ */N/* Get info item codes Z */N/*- */#define WBM$_BITMAP_NAME 1#define WBM$_LOCAL_HANDLE 2#define WBM$_CREATE_SYSTIME 3#define WBM$_CLUSTER_SIZE 4#define WBM$_BITMAP_SIZE 5#define WBM$_MASTER_CSID 6#define WBM$_DELETE_RQST 7#define WBM$_STOPPED 8#define WBM$_REFCNT 9#define WBM$_MASTER_BITS_SET 10#define WBM$_LOCAL_BITS_SET 11#define WBM$_SUB_GROUP 12#define WBM$_AMCCNT 13#define WBM$_UNIT 14#define WBM$Z_INDEX 15#define WBM$_DMTCNT 16#define WBM$_BITMAP_TYPE 17#define WBM$K_MAX_BMI_ITEMS 17#define WBM$S_BITMAP_NAME 64#define WBM$S_LOCAL_HANDLE 4#define WBM$S_CREATE_SYSTIME 8#define WBM$S_CLUSTER_SIZE 2#define WBM$S_BITMAP_SIZE 4#define WBM$S_MASTER_CSID 4#define WBM$S_DELETE_RQST 1#define WBM$S_STOPPED 1#define WBM$S_REFCNT 2#define WBM$S_MASTER_BITS_SET 4#define WBM$S_LOCAL_BITS_SET 4#define WBM$S_SUB_GROUP 1#define WBM$S_AMCCNT 1#define WBM$S_UNIT 4#definZe WBM$S_INDEX 1#define WBM$S_DMTCNT 1#define WBM$S_BITMAP_TYPE 2N/*+ */N/* Msging identifiers */N/*- */#define WBM$K_INIT 1#define WBM$K_CREATE 2#define WBM$K_DELETE 3#define WBM$K_START 4#define WBM$K_STOP 5#define WBM$K_GET_INFO 6#define WBM$K_SCAN 7#define WBM$K_CHECK 8#definZe WBM$K_SET 9#define WBM$K_SET_NAME 10#define WBM$K_PACK_SET 11#define WBM$K_INFO 12#define WBM$K_WRTLCK 13#define WBM$K_UNWRTLCK 14#define WBM$K_TEST 15#define WBM$K_MSG_MODE 16N/*+ */N/* Opcom level constants */N/*- */#define WBM$K_OPCOM_LOW 0#define WBM$K_OPCOM_MED 1N/*+ Z */N/* Deletion flags */N/*- */#define WBM$K_DEL_SING 1#define WBM$K_DEL_ALL 2#define WBM$K_DEL_RQST 3N/*+ */N/* Write lock state codes */N/*- Z */#define WBM$K_CWL_NOLCK 1#define WBM$K_CWL_NL 2#define WBM$K_CWL_CR 3#define WBM$K_CWL_CW 4#define WBM$K_CWL_PR 5N/*+ */N/* WBIL - write bitmap itemlist */N/*- */#define WBIL$S_WBILDEF 142 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* Z If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _wbil {#pragma __nomember_alignmentN unsigned char wbil$b_count; /* count of items in the item list */Q unsigned char wbil$b_func_rqst [7]; /* one byte for each of the item codes */N unsigned short int wbil$w_name_len; /* storage for name length */O unsigned short int wbil$w_create_systime_len; /* storage for time length */S Z unsigned short int wbil$w_bits_set_len; /* storage for master bits set field */j unsigned short int wbil$w_master_csid_len; /* storage for master csid length */U unsigned short int wbil$w_cluster_size_len; /* storage for cluster size length */V unsigned short int wbil$w_delete_rqst_len; /* storage for delete request length */N unsigned short int wbil$w_stopped_len; /* storage for stopped length */N unsigned char wbil$b_name_buf [64]; /* buffer for bitmZap name */N unsigned __int64 wbil$q_create_systime; /* storage for timestamp */N unsigned int wbil$l_bits_set; /* storage for number of bits set */N unsigned int wbil$l_master_csid; /* storage for csid */N unsigned short int wbil$w_cluster_size; /* storage for cluster size */N unsigned char wbil$b_delete_rqst; /* storage for delete request bit */N unsigned char wbil$b_stopped; /* storage for stopped bit */N Zunsigned short int wbil$w_sub_group_len; /* storage for subgroup length */N unsigned short int wbil$w_amccnt_len; /* storage for amccnt length */N unsigned short int wbil$w_refcnt_len; /* storage for refcntlength */N unsigned short int wbil$w_unit_len; /* storage for unit length */N unsigned short int wbil$w_index_len; /* storage for index length */N unsigned short int wbil$w_dmtcnt_len; /* storage for dmtcnt length */S unsigned short int wbil$w_Zbitmap_type_len; /* storage for bitmap_type length */N unsigned char wbil$b_sub_group; /* storage for sub_group */N unsigned char wbil$b_amccnt; /* storage for amccnt */N unsigned int wbil$l_unit; /* storage for unit */N unsigned short int wbil$w_refcnt; /* storage for refcnt */N unsigned char wbil$b_index; /* storage for index */N unsigned char wbil$b_dmtcnt; /* storage Z for dmtcnt */N unsigned short int wbil$w_bitmap_type; /* storage for bitmap_type */V unsigned char wbil$b_func_rqst_ext [10]; /* one byte for each of the item codes */ char wbil$b_fill_0_ [2]; } WBIL;N/*+ */N/* BMIL - write bitmap itemlist */N/*- */#define BMIL$S_BMILDEF 3 Z60 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _bmil {#pragma __member_alignmentN ILE3 bmil$r_itemlist_entry [18]; /* array of item list entries */N unsigned short int bmil$w_retlen_entry [18]; /* Array of RETLEN values */N/* Space for item data */$ unsigned cha Zr bmil$r_data [108]; } BMIL;N/*+ */N/* WBMH -- WBM Bitmap handle */N/*- */ typedef struct _wbmh { __union {! unsigned int wbmh$l_wbmh; __struct {N unsigned short int wbmh$w_idx; /* index into WBM handle array */U unsigned short int wbmh$w_seq; /* seZquence # for bitmap identification */ } wbmh$r_overlay; } wbmh$r_handle; } WBMH; #if !defined(__VAXC)-#define wbmh$l_wbmh wbmh$r_handle.wbmh$l_wbmh3#define wbmh$r_overlay wbmh$r_handle.wbmh$r_overlay,#define wbmh$w_idx wbmh$r_overlay.wbmh$w_idx,#define wbmh$w_seq wbmh$r_overlay.wbmh$w_seq"#endif /* #if !defined(__VAXC) */ N/*+ */N/* WBM_LCK -- WBM lock context block Z */N/*- */#define WBM_LCK$S_WBM_LCKDEF 48 typedef struct _wbm_lck {\ LKSB wbm_lck$r_lksb; /* Lock status block for the LVB validation lock */R unsigned int wbm_lck$l_size; /* size of the allocated context block */Q unsigned int wbm_lck$l_lck_seq; /* sequence counter for the lock state */N WBMH wbm_lck$r_wbmh; /* handle for associated wbme Z */_ unsigned int wbm_lck$r_res_dsc [3]; /* starting address for the resource name descriptor */ } WBM_LCK;N/*+ */N/* WBMH_ENTRY -- WBM entry in the handle array */N/*- */$#define WBMH_ENTRY$S_WBMH_ENTRYDEF 8  9#ifdef __cplusplus /* Define structure prototypes */ struct _wbmb; #endif /* #ifdef __cp Zlusplus */ typedef struct _wbmh_entry {#pragma __nomember_alignment __union {N struct _wbmb *wbmh_entry$ps_wbmb; /* address of a wbmb */e unsigned short int wbmh_entry$w_next_idx; /* contains the idx of the next available entry */ } wbmh_entry$r_overlay1; __union { __union {. unsigned int wbmh_entry$l_bm_info; __struct {X unsigned short int wbmh_entry$w_seq; /* sequence number of the bitmap Z*/a unsigned char wbmh_entry$b_idx; /* index idextifying this WBME within its WBMB */N char wbmh_entry$b_fill_1; /* fill to next longword */' } wbmh_entry$r_fill_2_;# } wbmh_entry$r_fill_1_; __union {3 unsigned int wbmh_entry$l_wbmh_en_type; __struct {W unsigned short int wbmh_entry$w_size; /* Structure size in QUADWORDS */N unsigned char wbmh_entry$b_type; /* ZWBM structure type */N unsigned char wbmh_entry$b_subtype; /* WBMH_ARRAY subtype */' } wbmh_entry$r_fill_4_;# } wbmh_entry$r_fill_3_; } wbmh_entry$r_overlay2; } WBMH_ENTRY; #if !defined(__VAXC)C#define wbmh_entry$ps_wbmb wbmh_entry$r_overlay1.wbmh_entry$ps_wbmbI#define wbmh_entry$w_next_idx wbmh_entry$r_overlay1.wbmh_entry$w_next_idx\#define wbmh_entry$l_bm_info wbmh_entry$r_overlay2.wbmh_entry$r_fill_1_.wbmh_entry$l_bm_infoZi#define wbmh_entry$w_seq wbmh_entry$r_overlay2.wbmh_entry$r_fill_1_.wbmh_entry$r_fill_2_.wbmh_entry$w_seqi#define wbmh_entry$b_idx wbmh_entry$r_overlay2.wbmh_entry$r_fill_1_.wbmh_entry$r_fill_2_.wbmh_entry$b_idxo#define wbmh_entry$b_fill_1 wbmh_entry$r_overlay2.wbmh_entry$r_fill_1_.wbmh_entry$r_fill_2_.wbmh_entry$b_fill_1f#define wbmh_entry$l_wbmh_en_type wbmh_entry$r_overlay2.wbmh_entry$r_fill_3_.wbmh_entry$l_wbmh_en_typek#define wbmh_entry$w_size wbmh_entry$r_overlay2.wbmh_entry$r_fill_3_.wZbmh_entry$r_fill_4_.wbmh_entry$w_sizek#define wbmh_entry$b_type wbmh_entry$r_overlay2.wbmh_entry$r_fill_3_.wbmh_entry$r_fill_4_.wbmh_entry$b_typeq#define wbmh_entry$b_subtype wbmh_entry$r_overlay2.wbmh_entry$r_fill_3_.wbmh_entry$r_fill_4_.wbmh_entry$b_subtype"#endif /* #if !defined(__VAXC) */ N/*+ */N/* WBLVB -- Write Bitmap Lock Value Block Overlay */N/*- Z */#define WBLVB$S_WBLVBDEF 15 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _wblvb {#pragma __nomember_alignment __union {N unsigned int wblvb$l_csid; /* cluster system id */ __struct {N unsigned short int wblvb$w_csid_idx; /* slot idx Z */N unsigned short int wblvb$w_csid_seq; /* sequence number */ } wblvb$r_fill_6_; } wblvb$r_fill_5_;N WBMH wblvb$r_wbmh; /* bitmap handle */P unsigned int wblvb$l_maxblock; /* max block from the master's vu ucb */N unsigned short int wblvb$w_cluster; /* Cluster factor */Y unsigned char wblvb$b_version; /* Protocol version (note: only low four bits) */O/* MAXMSG byte uns Zigned; maximum message size in quadwords FUTURE VERISON */ char wblvb$b_fill_7_; } WBLVB; #if !defined(__VAXC)1#define wblvb$l_csid wblvb$r_fill_5_.wblvb$l_csidI#define wblvb$w_csid_idx wblvb$r_fill_5_.wblvb$r_fill_6_.wblvb$w_csid_idxI#define wblvb$w_csid_seq wblvb$r_fill_5_.wblvb$r_fill_6_.wblvb$w_csid_seq"#endif /* #if !defined(__VAXC) */ N/*+ */a/* WBM -- Actual bitmap structure and header to be a Zllocated from memory (S2 or nonpaged pool) */N/*- */#define WBM$C_LENGTH 124#define WBM$K_LENGTH 124N#define WBM$S_WBMDEF 124 /* Old size name synonym */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _wbm {#pragma __nomember_alignment ZR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */_ unsigned int *wbm$pq_bitmap; /* longword pointer to address after this structure */#else unsigned __int64 wbm$pq_bitmap;#endifN unsigned int wbm$l_size; /* Structure size in bytes */N unsigned char wbm$b_type; /* WBM Structure type */N unsigned char wbZm$b_subtype; /* Bitmap subtype */N unsigned short int wbm$w_cluster; /* cluster factor (#blocks/bit) */R unsigned char wbm$b_name [64]; /* identification string for the bitmap */[ unsigned int wbm$l_xfer_cnt; /* count of longwords transfered for this bitmap */N unsigned int wbm$l_bits_set; /* count of bis set in the bitmap */#pragma __member_alignmentN LKSB wbm$r_lksb; /* lock status block */NZ unsigned int wbm$l_name_len; /* length of name buffer */N unsigned char wbm$b_sub_group; /* Policy sub_group */N unsigned char wbm$b_amccnt; /* Policy AMCCNT */N unsigned short int wbm$w_refcnt; /* refcnt */N unsigned char wbm$b_dmtcnt; /* dmtcnt */N unsigned char wbm$b_spare_b; /* unused */N unsigned short int wbm Z$w_bitmap_type; /* bitmap_type */ char wbm$b_fill_8_ [4]; } WBM;N/*+ */N/* WBME -- Bitmap entry structure */N/*- */#define WBME$M_SLOT_INUSE 0x1#define WBME$M_EXISTS 0x2#define WBME$M_ACTIVE 0x4#define WBME$M_MASTER 0x8#define WBME$M_DELETE_RQST 0x10 #define WBME$M_INIT_ZPENDING 0x20!#define WBME$M_START_PENDING 0x40#define WBME$M_CW_PENDING 0x80#define WBME$S_WBMEDEF 110 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _wbme {#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size def Zault to 64-bit pointers */O struct _wbm *wbme$pq_wbm; /* quadword pointer to wbm structure */#else unsigned __int64 wbme$pq_wbm;#endifN unsigned int wbme$q_time [2]; /* timestamp */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *wbme$pq_vapte_sva; /* NOSVAPTE_V9.0 Dave Fairbanks */#else$ uns Zigned __int64 wbme$pq_vapte_sva;#endifZ unsigned int wbme$l_bitmap_size; /* upward bound of the bitmap array (longwords) */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifN void (*wbme$l_fpc)(); /* completion routine address */Z __union { /* context parameter for the completion routine */% unsignZed __int64 wbme$q_ctx1;! unsigned int wbme$l_ctx1; } wbme$r_ctx_overlay;N __union { /* WBME flags overlay */N unsigned int wbme$l_flags; /* flags */N __struct { /* flag bits */O unsigned wbme$v_slot_inuse : 1; /* indicates this wbme is in use */u unsigned wbme$v_exists : 1; /* indicates that a bitmap has been allocated(no gZuaranteed local caching) */{ unsigned wbme$v_active : 1; /* indicates the state of a bitmap (1 = tracking writes / 0 = no write tracking) */T unsigned wbme$v_master : 1; /* indicates this WBME masters the bitmap */q unsigned wbme$v_delete_rqst : 1; /* indicates deletion requested but could not be completed as yet */c unsigned wbme$v_init_pending : 1; /* indicates WBME in the process of initialization */` unsigned wbme$v_start_pending : 1; Z /* indicates WBME in the process of activation */U unsigned wbme$v_cw_pending : 1; /* indicates CW conversion outstanding */N unsigned wbme$v_reserved_fb1 : 24; /* Filler */ } wbme$r_flag_bits; } wbme$r_flags_overlay;#pragma __member_alignmentN char wbme$b_lck_name [32]; /* lock name */N LKSB wbme$r_lksb; /* lock status block */N unsigned int wbme$l_lck_se Zq; /* CW lock sequence counter */V unsigned int wbme$l_maxblock; /* max block count of the associated device */c unsigned short int wbme$w_wbmh_idx; /* index into the WBM handle array identifying this WBME */ char wbme$b_fill_9_ [2]; } WBME; #if !defined(__VAXC)2#define wbme$q_ctx1 wbme$r_ctx_overlay.wbme$q_ctx12#define wbme$l_ctx1 wbme$r_ctx_overlay.wbme$l_ctx16#define wbme$l_flags wbme$r_flags_overlay.wbme$l_flagsQ#define wbme$v_slot_inuse wbme$r_flaZgs_overlay.wbme$r_flag_bits.wbme$v_slot_inuseI#define wbme$v_exists wbme$r_flags_overlay.wbme$r_flag_bits.wbme$v_existsI#define wbme$v_active wbme$r_flags_overlay.wbme$r_flag_bits.wbme$v_activeI#define wbme$v_master wbme$r_flags_overlay.wbme$r_flag_bits.wbme$v_masterS#define wbme$v_delete_rqst wbme$r_flags_overlay.wbme$r_flag_bits.wbme$v_delete_rqstU#define wbme$v_init_pending wbme$r_flags_overlay.wbme$r_flag_bits.wbme$v_init_pendingW#define wbme$v_start_pending wbme$r_flags_overlay.wbme$r Z_flag_bits.wbme$v_start_pendingQ#define wbme$v_cw_pending wbme$r_flags_overlay.wbme$r_flag_bits.wbme$v_cw_pending"#endif /* #if !defined(__VAXC) */ N/*+ */N/* WBMB -- Main tracking structure for Bitmap code */N/*- */ #define WBMB$M_IGNORE_GROUP1 0x2 #define WBMB$M_IGNORE_GROUP2 0x4 #define WBMB$M_IGNORE_GROUP3 0x8#definZe WBM$K_IGNORE_LOCAL 1#define WBM$K_USE_LOCAL 2#define WBMB$S_WBMBDEF 1552  9#ifdef __cplusplus /* Define structure prototypes */struct _mscp_ucb; struct _irp; struct _fkb; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _wbmb {#pragma __nomember_alignmentN struct _wbmb *wbmb$ps_Zflink; /* Flink for master WBMB list */N struct _wbmb *wbmb$ps_blink; /* Blink */N unsigned short int wbmb$w_size; /* Structure size in bytes */N unsigned char wbmb$b_type; /* WBM structure type */N unsigned char wbmb$b_subtype; /* WBMB subtype */N struct _mscp_ucb *wbmb$ps_ucb; /* Pointer to the associated UCB */N __union { /* WBM flags Z overlay */N unsigned short int wbmb$w_flags; /* flags */N __struct { /* 8 bit flag structure currently */N unsigned wbmb$v_reserved_fb1 : 16; /* Filler */ } wbmb$r_flag_bits; } wbmb$r_flags_overlay;W unsigned char wbmb$b_init_outstanding; /* number of outstanding lock transitions */N char wbmb$b_fill_1; /* fill to next longword */N Z void (*wbmb$l_fpc)(); /* completion routine address */N unsigned int wbmb$l_ctx1; /* context parameter */N unsigned int wbmb$l_ctx2; /* context parameter */Q unsigned int wbmb$l_delete_count; /* debug delete counter ??? remove ??? */N int wbmb$l_writes_in_progress_cnt; /* Count of outstanding writes */ __union {( unsigned int wbmb$l_writelocked; __struct {g char wbmb$ Zb_sys_writelock_cnt; /* count of writelock requests by trusted system routines */U char wbmb$b_dcl_writelock_cnt; /* count of writelock requests from DCL */N unsigned short int wbmb$w_fill_16; /* extra */ } wbmb$r_fill_11_; } wbmb$r_fill_10_; __union {W unsigned __int64 wbmb$q_writelocked_irp_list; /* linked list of stalled irps */ __struct {+ struct _irp *wbmb$ps_irp_flink;+ struct _ Zirp *wbmb$ps_irp_blink; } wbmb$r_fill_13_; } wbmb$r_fill_12_; __union {z __int64 wbmb$q_writelocked_notify; /* list of fork blocks to be activated when the write lock request completes */ __struct {+ struct _fkb *wbmb$ps_fkb_flink;+ struct _fkb *wbmb$ps_fkb_blink; } wbmb$r_fill_15_; } wbmb$r_fill_14_;O LKSB wbmb$r_cwl_lksb_local; /* lock status block for CR-CW lock */N LKSB wbmb$r_cwl_lksbZ_wl; /* lock status block for PW lock */N char wbmb$b_cwl_lockname [32]; /* write lock resource name */N __struct { /* Descriptor for CWL_LOCKNAME */\ unsigned short int wbmb$w_cwl_dsc_length; /* Length in bytes of CWL name string */N unsigned char wbmb$b_cwl_dsc_dtype; /* Data type (DSC$K_DTYPE_T) */Q unsigned char wbmb$b_cwl_dsc_class; /* Storage class (DSC$K_CLASS_S) */a void *wbmb$a_cwl_dsc_poi Znter; /* Address of CWL name string (WBMB$B_CWL_LOCKNAME) */ } wbmb$r_cwl_dsc;N void (*wbmb$l_cwl_completion_rtn)(); /* completion routine address */N __union { /* completion routine context */7 unsigned __int64 wbmb$q_cwl_completion_context; __union {3 unsigned __int64 wbmb$q_two_ctx_params; __struct {< unsigned int wbmb$l_cwl_completion_context1;< unsigned int w Zbmb$l_cwl_completion_context2;" } wbmb$r_fill_17_; } wbmb$r_fill_16_; } wbmb$r_ctx_overlay;X unsigned char wbmb$b_cwl_local_state; /* DLM lock state for the CR-CW progression */N unsigned char wbmb$b_cwl_wl_state; /* DLM lock state for the PW lock */N unsigned short int wbmb$w_fill_2; /* DEBUG remove !!! */N unsigned int wbmb$l_set_cnt; /* debug counters remove !!! */N unsigned int wbmb$l_rem_set_cnt; /* dZebug counters remove !!! */N unsigned int wbmb$l_cache_hit_cnt; /* debug counters remove !!! */N __union { /* */[ unsigned int wbmb$l_ignore_bitmap_mask; /* Mask of local bitmap groups to ignore */N __struct { /* Currently only 2 groups defined */N unsigned wbmb$v_fill_0 : 1; /* unused */Q unsigned wbmb$v_ignore_group1 : 1; /* Ignore Z Group 1 local bitmaps */Q unsigned wbmb$v_ignore_group2 : 1; /* Ignore Group 2 local bitmaps */Q unsigned wbmb$v_ignore_group3 : 1; /* Ignore Group 3 local bitmaps */N unsigned wbmb$v_fill_4_to_31 : 28; /* unused */- } wbmb$r_ignore_bitmap_mask_bits;$ } wbmb$r_ignore_bitmap_mask;R unsigned int wbmb$l_fill_99 [7]; /* spare - allocate new cells from here */#pragma __member_alignmentZ WBME wbmb$r_bitmap_entry [12 Z]; /* array of WBME structures identifying bitmaps */ } WBMB; #if !defined(__VAXC)6#define wbmb$w_flags wbmb$r_flags_overlay.wbmb$w_flags=#define wbmb$l_writelocked wbmb$r_fill_10_.wbmb$l_writelockedY#define wbmb$b_sys_writelock_cnt wbmb$r_fill_10_.wbmb$r_fill_11_.wbmb$b_sys_writelock_cntY#define wbmb$b_dcl_writelock_cnt wbmb$r_fill_10_.wbmb$r_fill_11_.wbmb$b_dcl_writelock_cntO#define wbmb$q_writelocked_irp_list wbmb$r_fill_12_.wbmb$q_writelocked_irp_listK#define wbmb$ps_irp_Zflink wbmb$r_fill_12_.wbmb$r_fill_13_.wbmb$ps_irp_flinkK#define wbmb$ps_irp_blink wbmb$r_fill_12_.wbmb$r_fill_13_.wbmb$ps_irp_blinkK#define wbmb$q_writelocked_notify wbmb$r_fill_14_.wbmb$q_writelocked_notifyK#define wbmb$ps_fkb_flink wbmb$r_fill_14_.wbmb$r_fill_15_.wbmb$ps_fkb_flinkK#define wbmb$ps_fkb_blink wbmb$r_fill_14_.wbmb$r_fill_15_.wbmb$ps_fkb_blinkB#define wbmb$w_cwl_dsc_length wbmb$r_cwl_dsc.wbmb$w_cwl_dsc_length@#define wbmb$b_cwl_dsc_dtype wbmb$r_cwl_dsc.wbmb$b_cwl_dsc_dtype@#dZefine wbmb$b_cwl_dsc_class wbmb$r_cwl_dsc.wbmb$b_cwl_dsc_classD#define wbmb$a_cwl_dsc_pointer wbmb$r_cwl_dsc.wbmb$a_cwl_dsc_pointerV#define wbmb$q_cwl_completion_context wbmb$r_ctx_overlay.wbmb$q_cwl_completion_contextV#define wbmb$q_two_ctx_params wbmb$r_ctx_overlay.wbmb$r_fill_16_.wbmb$q_two_ctx_paramsx#define wbmb$l_cwl_completion_context1 wbmb$r_ctx_overlay.wbmb$r_fill_16_.wbmb$r_fill_17_.wbmb$l_cwl_completion_context1x#define wbmb$l_cwl_completion_context2 wbmb$r_ctx_overlay.wbmb$r_fill_16_.Zwbmb$r_fill_17_.wbmb$l_cwl_completion_context2U#define wbmb$l_ignore_bitmap_mask wbmb$r_ignore_bitmap_mask.wbmb$l_ignore_bitmap_mask\#define wbmb$v_fill_0 wbmb$r_ignore_bitmap_mask.wbmb$r_ignore_bitmap_mask_bits.wbmb$v_fill_0j#define wbmb$v_ignore_group1 wbmb$r_ignore_bitmap_mask.wbmb$r_ignore_bitmap_mask_bits.wbmb$v_ignore_group1j#define wbmb$v_ignore_group2 wbmb$r_ignore_bitmap_mask.wbmb$r_ignore_bitmap_mask_bits.wbmb$v_ignore_group2j#define wbmb$v_ignore_group3 wbmb$r_ignore_bitmap_mask.wbmb$ Zr_ignore_bitmap_mask_bits.wbmb$v_ignore_group3h#define wbmb$v_fill_4_to_31 wbmb$r_ignore_bitmap_mask.wbmb$r_ignore_bitmap_mask_bits.wbmb$v_fill_4_to_31"#endif /* #if !defined(__VAXC) */ N/*+ */N/* WBML -- head structure for linking WBMB's */N/*- */#define WBML$S_WBMLDEF 8 c#if !defined(__NOBASEALIGN_SUPPORT) && !d Zefined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _wbml {#pragma __nomember_alignmentN struct _wbmb *wbml$ps_flink; /* Flink for master WBMB list */N struct _wbmb *wbml$ps_blink; /* Blink */ } WBML;N/*+ */N/* WBMCD -- Write bitmap connection descriptor entZry */N/*- */#define WBMCD$M_BUFFER_MODE 0x1 #define WBMCD$M_NODE_REMOVED 0x2%#define WBMCD$M_RES_ALLOC_PENDING 0x4#define WBMCD$S_WBMCDDEF 96  9#ifdef __cplusplus /* Define structure prototypes */ struct _irp; struct _cdrp;struct _wbm_ctx; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#p Zragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _wbmcd {#pragma __nomember_alignmentN struct _wbmcd *wbmcd$ps_flink; /* Flink */N struct _wbmcd *wbmcd$ps_blink; /* Blink */ __union {N __union { /* WBM flags overlay */' unsigned int wbmcd$l_flags;N __struct { /* 32 bit flag structure c Zurrently */] unsigned wbmcd$v_buffer_mode : 1; /* indicates packaging set messages mode */R unsigned wbmcd$v_node_removed : 1; /* node removed from cluster */l unsigned wbmcd$v_res_alloc_pending : 1; /* resource allocation and intialization pending */N unsigned wbmcd$v_reserved_fb1 : 29; /* Filler */$ } wbmcd$r_flag_bits;$ } wbmcd$r_flags_overlay; __union {, unsigned int w Zbmcd$l_wbmcd_type; __struct {N unsigned short int wbmcd$w_size; /* Structure size in bytes */N unsigned char wbmcd$b_type; /* WBM */N unsigned char wbmcd$b_subtype; /* WBMCD_ARRAY */# } wbmcd$r_fill_19_; } wbmcd$r_fill_18_; } wbmcd$r_type_ovrly; __union {N unsigned int wbmcd$l_csid; /* cluster system id */ __struct {ZN unsigned short int wbmcd$w_csid_idx; /* slot idx */N unsigned short int wbmcd$w_csid_seq; /* sequence number */ } wbmcd$r_fill_21_; } wbmcd$r_fill_20_;i struct _irp *wbmcd$ps_irp_flink; /* Queue head for IRP's waiting on a resouce CDRP/RSPID/MSGBUF */N struct _irp *wbmcd$ps_irp_blink; /* Blink */g unsigned __int64 wbmcd$q_interval_end; /* end of sampling interval for dynamic message s Zwitching */N struct _cdrp *wbmcd$ps_cdrp; /* pointer to CDRP for set bitmap */m unsigned int wbmcd$l_msg_per_int; /* count of the total number of messages sent during this interval */c unsigned short int wbmcd$w_rqst_per_buf; /* count of the number of set request in the buffer */ char wbmcd$b_fill_22_ [6];c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomeZmber_alignment#endifl struct _wbm_ctx *wbmcd$ps_wbm_ctx_flink; /* Queue head for wbm_ctx's associated with this connection */#pragma __nomember_alignmentN struct _wbm_ctx *wbmcd$ps_wbm_ctx_blink; /* Blink */X unsigned __int64 wbmcd$q_setbit_per_int; /* Count of setbit per wbm_msg_interval. */Q unsigned __int64 wbmcd$q_msg_sent_single; /* Messages sent in single mode. */k unsigned __int64 wbmcd$q_msg_sent_buf_partial; /* Partially populated messages sent Zin buffered mode */d unsigned __int64 wbmcd$q_msg_sent_buf_full; /* Fully populated messages sent in buffered mode */f unsigned __int64 wbmcd$q_mode_trans_cnt; /* No. of Transitions between single and buffered mode */ } WBMCD; #if !defined(__VAXC)L#define wbmcd$l_flags wbmcd$r_type_ovrly.wbmcd$r_flags_overlay.wbmcd$l_flagsj#define wbmcd$v_buffer_mode wbmcd$r_type_ovrly.wbmcd$r_flags_overlay.wbmcd$r_flag_bits.wbmcd$v_buffer_model#define wbmcd$v_node_removed wbmcd$r_type_ovrly.wbmcZd$r_flags_overlay.wbmcd$r_flag_bits.wbmcd$v_node_removedv#define wbmcd$v_res_alloc_pending wbmcd$r_type_ovrly.wbmcd$r_flags_overlay.wbmcd$r_flag_bits.wbmcd$v_res_alloc_pendingQ#define wbmcd$l_wbmcd_type wbmcd$r_type_ovrly.wbmcd$r_fill_18_.wbmcd$l_wbmcd_typeV#define wbmcd$w_size wbmcd$r_type_ovrly.wbmcd$r_fill_18_.wbmcd$r_fill_19_.wbmcd$w_sizeV#define wbmcd$b_type wbmcd$r_type_ovrly.wbmcd$r_fill_18_.wbmcd$r_fill_19_.wbmcd$b_type\#define wbmcd$b_subtype wbmcd$r_type_ovrly.wbmcd$r_fill_18_.wbmcd$r_ Zfill_19_.wbmcd$b_subtype2#define wbmcd$l_csid wbmcd$r_fill_20_.wbmcd$l_csidK#define wbmcd$w_csid_idx wbmcd$r_fill_20_.wbmcd$r_fill_21_.wbmcd$w_csid_idxK#define wbmcd$w_csid_seq wbmcd$r_fill_20_.wbmcd$r_fill_21_.wbmcd$w_csid_seq"#endif /* #if !defined(__VAXC) */ N/*+ */N/* WBM_CTX -- Write bitmap setbit Send context */N/*- Z */ #define WBM_CTX$S_WBM_CTXDEF 130#define WBM_CTX$C_LENGTH 130#define WBM_CTX$K_LENGTH 130  9#ifdef __cplusplus /* Define structure prototypes */ struct _cdrp; struct _irp; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _wbm_ctx {#pragma __nomember_alignmentN struct _wbm_ctx Z*wbm_ctx$ps_flink; /* Flink */N struct _wbm_ctx *wbm_ctx$ps_blink; /* Blink */ __union {' unsigned int wbm_ctx$l_wbm_ctx; __struct {N unsigned short int wbm_ctx$w_size; /* Structure size in bytes */N unsigned char wbm_ctx$b_type; /* WBM */N unsigned char wbm_ctx$b_subtype; /* WBM_CTX */! } wbm_ctx$r_fill_24_; } Zwbm_ctx$r_fill_23_;N struct _cdrp *wbm_ctx$ps_cdrp; /* pointer to CDRP for set bitmap */f unsigned int wbm_ctx$l_irp_count; /* count of the number of IRPs associated with this context */b struct _irp *wbm_ctx$ps_irp_array [9]; /* Array of IRP's associated with this CDRP/wbm_ctx. */W unsigned short int wbm_ctx$w_seqio_flg; /* To store the seqio_flag for each IRP. */N unsigned int wbm_ctx$l_rem_handle_array [9]; /* Array of remote handles */N unsigned int wbm_ctx$l_lcl Z_handle_array [9]; /* Array of local handles */ char wbm_ctx$b_fill_25_ [2]; } WBM_CTX; #if !defined(__VAXC)>#define wbm_ctx$l_wbm_ctx wbm_ctx$r_fill_23_.wbm_ctx$l_wbm_ctxK#define wbm_ctx$w_size wbm_ctx$r_fill_23_.wbm_ctx$r_fill_24_.wbm_ctx$w_sizeK#define wbm_ctx$b_type wbm_ctx$r_fill_23_.wbm_ctx$r_fill_24_.wbm_ctx$b_typeQ#define wbm_ctx$b_subtype wbm_ctx$r_fill_23_.wbm_ctx$r_fill_24_.wbm_ctx$b_subtype"#endif /* #if !defined(__VAXC) */ N/*+ Z */N/* WBM_DATA -- Write bitmap global data block */N/*- */%#define WBM_DATA$M_SHADOW_CAPABLE 0x1"#define WBM_DATA$M_TQE_ENABLED 0x2!#define WBM_DATA$S_WBM_DATADEF 40#define WBM_DATA$C_LENGTH 40#define WBM_DATA$K_LENGTH 40 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignZment __quadword#else#pragma __nomember_alignment#endiftypedef struct _wbm_data {#pragma __nomember_alignment __union {p unsigned int wbm_data$l_version; /* write bitmap code version (will be accessed directly by shadowing */ __struct {N unsigned short int wbm_data$w_major_ver; /* major version */N unsigned short int wbm_data$w_minor_ver; /* minor version */" } wbm_data$r_fill_27_; } wbm_data$r_fill_26_;N Z__union { /* WBM Global status flags */( unsigned int wbm_data$gl_status;N __struct { /* 32 bit flag structure currently */p unsigned wbm_data$v_shadow_capable : 1; /* indicates node capable of performing WBM functionality */y unsigned wbm_data$v_tqe_enabled : 1; /* indicates whether a TQE was queued to process the connection list */N unsigned wbm_data$v_reserved_fb1 : 30; /* Filler Z */% } wbm_data$r_status_bits;$ } wbm_data$r_status_overlay;N unsigned short int wbm_data$w_size; /* Structure size in bytes */N unsigned char wbm_data$b_type; /* WBM structure type */N unsigned char wbm_data$b_subtype; /* WBM_DATA subtype */g struct _wbmcd *wbm_data$gl_connections; /* pointer to an array of connection descriptor entries */ __union {s unsigned int wbm_data$gq_cnxlistn [2]; /* Doubly Z linked list of connection descriptors sending N message */ __struct {1 struct _wbmcd *wbm_data$ps_cln_flink;1 struct _wbmcd *wbm_data$ps_cln_blink;" } wbm_data$r_fill_29_; } wbm_data$r_fill_28_;U struct _wbmh_entry *wbm_data$gl_wbmh_array; /* address of the WBM handle array */d unsigned int wbm_data$l_sf_msg_sent; /* total number of immediate bitmap update messages sent */h unsigned int wbm_data$l_tqe_msg_sent; /* total number of Z timer-driven bitmap update messages sent */n unsigned int wbm_data$l_cwcancel; /* counter for number of times we hit the CW lock cancellation hack */ } WBM_DATA; #if !defined(__VAXC)A#define wbm_data$l_version wbm_data$r_fill_26_.wbm_data$l_versionY#define wbm_data$w_major_ver wbm_data$r_fill_26_.wbm_data$r_fill_27_.wbm_data$w_major_verY#define wbm_data$w_minor_ver wbm_data$r_fill_26_.wbm_data$r_fill_27_.wbm_data$w_minor_verG#define wbm_data$gl_status wbm_data$r_status_overlayZ.wbm_data$gl_statusl#define wbm_data$v_shadow_capable wbm_data$r_status_overlay.wbm_data$r_status_bits.wbm_data$v_shadow_capablef#define wbm_data$v_tqe_enabled wbm_data$r_status_overlay.wbm_data$r_status_bits.wbm_data$v_tqe_enabledE#define wbm_data$gq_cnxlistn wbm_data$r_fill_28_.wbm_data$gq_cnxlistn[#define wbm_data$ps_cln_flink wbm_data$r_fill_28_.wbm_data$r_fill_29_.wbm_data$ps_cln_flink[#define wbm_data$ps_cln_blink wbm_data$r_fill_28_.wbm_data$r_fill_29_.wbm_data$ps_cln_blink"#endif /* Z #if !defined(__VAXC) */  ?#ifdef ALPHA /* Verified for x86 port - Clair Grant */# ifdef __INITIAL_POINTER_SIZEM# pragma __required_pointer_size __save /* Save current pointer size */G# pragma __required_pointer_size 64 /* Pointers are 64-bits */V typedef struct _wbm * WBM_PQ; /* Long pointer to a WBM structure. */V typedef struct _wbm ** WBM_PPQ; /* Long pointer to a WBM structure. */^ typedef struct _wblvb *WBLVB_PQ; Z /* Long pointer to a WBLVB structure. */ S# pragma __required_pointer_size __restore /* Return to previous pointer size */# elseW typedef unsigned __int64 LKSB_PQ; /* Same size as a 64-bit pointer to an LKSB */d typedef unsigned __int64 LKSB_PPQ; /* Same size as a 64-bit pointer to a pointer to an LKSB */% typedef unsigned __int64 WBM_PQ;& typedef unsigned __int64 WBM_PPQ;' typedef unsigned __int64 WBLVB_PQ; # endif#endif  $#pragma Z__member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __WBMDEF_LOADED */ wwF[UM/***************************************************************************/M/** **/M/** HPZE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTZIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/********************************************************* Z******************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:33 by OpenVMS SDL V3.7 */F/* Source: 03-JUL-2023 14:18:56 $1$DGA8345:[LIB_H.SRC]WCBDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $WCBDEF ***/#ifndef __WCBDEF_LOADED#define __WCBDEF_LOADED 1 G Z#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optiZonal_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* WCB - WINDOW CONTROL BLOCK */ZN/* */N/* THERE IS A WINDOW CONTROL BLOCK FOR EACH FILE ACCESSED BY A PROCESS. */N/* IT CONTAINS MAPPING INFORMATION SUCH THAT A LARGE PERCENTAGE OF VIRTUAL */N/* FILE I/O CAN BE MAPPED FROM VIRTUAL TO LOGICAL BLOCK NUMBERS WITHOUT */N/* HAVING TO READ THE RESPECTIVE FILE HEADER. */N/*- */ #define WCB$M_READ 0 Zx1#define WCB$M_WRITE 0x2#define WCB$M_NOTFCP 0x4#define WCB$M_SHRWCB 0x8#define WCB$M_OVERDRAWN 0x10#define WCB$M_COMPLETE 0x20#define WCB$M_CATHEDRAL 0x40#define WCB$M_EXPIRE 0x80#define WCB$M_CONTROL 0x1000!#define WCB$M_NO_READ_DATA 0x2000N#define WCB$K_MAP 112 /* MAP POINTERS START HERE */N#define WCB$C_MAP 112 /* MAP POINTERS START HERE */S#define WCB$K_LENGTH 112 /* LENGTH OF STANDARD WCB SANS POINTERS Z */S#define WCB$C_LENGTH 112 /* LENGTH OF STANDARD WCB SANS POINTERS */N/* NOTE THAT VIRTUAL MAPPING */N#define WCB$S_WCBDEF 136 /* Old size name - synonym */  9#ifdef __cplusplus /* Define structure prototypes */ struct _ucb;struct _ssio_sc; struct _fcb; struct _rvt; #endif /* #ifdef __cplusplus */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4. Z0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _wcb {#pragma __nomember_alignmentN struct _wcb *wcb$l_wlfl; /* WINDOW LIST FORWARD LINK */N struct _wcb *wcb$l_wlbl; /* WINDOW LIST BACKWARD LINK */N unsigned short int wcb$w_size; /* SIZE OF WINDOW BLOCK IN BYTES */N unsigned char wcb$b_type; /* STRUCTURE TYPE OF WCB */ __union {N unsignZed char wcb$b_access; /* ACCESS CONTROL BYTE */ __struct {N unsigned wcb$v_read : 1; /* READ ACCESS ALLOWED (1=YES) */N unsigned wcb$v_write : 1; /* WRITE ACCESS ALLOWED (1=YES) */N unsigned wcb$v_notfcp : 1; /* FILE NOT ACCESSED BY FCP IF SET */N unsigned wcb$v_shrwcb : 1; /* SHARED WINDOW */V unsigned wcb$v_overdrawn : 1; /* FILE ACCESSOR HAS OVERDRAWN HIS QUOTA */N Z unsigned wcb$v_complete : 1; /* SET WINDOW MAPS ENTIRE FILE */S unsigned wcb$v_cathedral : 1; /* LARGE, COMPLEX WINDOW (SIC) TO MAP */N/* FILE COMPLETELY */V unsigned wcb$v_expire : 1; /* FILE EXPIRATION DATE MAY NEED TO BE SET */ } wcb$r_access_bits; } wcb$r_access_overlay;N unsigned int wcb$l_pid; /* PROCESS ID OF ACCESSOR PROCESS */P unsigned int wcb$l_refcnt; Z /* REFERENCE COUNT FOR SHARED WINDOW */O struct _ucb *wcb$l_orgucb; /* ADDRESS OF ORIGINAL UCB FROM CCB */ __union {N unsigned int wcb$l_acon; /* ACCESS CONTROL INFORMATION */N/* NOTE - THESE BITS TRACK THE BITS */N/* IN FIB$L_ACCTL */ __struct {N unsigned wcb$v_nowrite : 1; /* NO OTHER WRITERS */N unsignZed wcb$v_dlock : 1; /* ENABLE DEACCESS LOCK */N unsigned wcb$$_fill_1 : 2; /* UNUSED */N unsigned wcb$v_spool : 1; /* SPOOL FILE ON CLOSE */N unsigned wcb$v_writeck : 1; /* ENABLE WRITE CHECK */N unsigned wcb$v_seqonly : 1; /* SEQUENTIAL ONLY ACCESS */N unsigned wcb$v_snapshot : 1; /* SNAPSHOT REVALIDATION PENDING */N unsigned wcb$v_writeac : 1; /* WZRITE ACCESS */N unsigned wcb$v_readck : 1; /* ENABLE READ CHECK */N unsigned wcb$v_noread : 1; /* NO OTHER READERS */N unsigned wcb$v_notrunc : 1; /* NO TRUNCATES */N unsigned wcb$v_control : 1; /* CONTROL ACCESS TO FILE */N unsigned wcb$v_no_read_data : 1; /* NO READ ACCESS TO FILE DATA */N unsigned wcb$v_fill_2 : 2; /* ALIGNMENT WITH ACON_BITS1 b Zelow */ } wcb$r_acon_bits0; __struct {& unsigned wcb$$_fill_3 : 2;N/* THE FOLLOWING FIELDS OVERLAY THE FIRST */N/* UNUSED FLAG IN WCB$W_ACON ABOVE (FILL_1). */N unsigned wcb$v_noacclock : 1; /* NO ACCESS LOCK CHECKING */N unsigned wcb$v_ssio : 1; /* File is open for SSIO access. */' unsigned wcb$$_fill_4 : 10;U unsigned wcb$v_readinit : Z1; /* A READINIT WAS DONE OVER THIS CHANNEL */N unsigned wcb$v_write_turn : 1; /* FORCE WINDOW TURN ON WRITES */ } wcb$r_acon_bits1; } wcb$r_acon_overlay;] struct _ssio_sc *wcb$ps_ssio_sc; /* Pointer to SSIO Stream Context (if SSIO access) */N unsigned int wcb$l_nmap; /* NUMBER OF MAPPING POINTERS */N struct _fcb *wcb$l_fcb; /* ADDRESS OF FCB */O struct _rvt *wcb$l_rvt; /* ADDRESS OF ZRELATIVE VOLUME TABLE */N void *wcb$l_link; /* LINK TO NEXT WINDOW SEGMENT */N unsigned __int64 wcb$q_opentime; /* Creation time of WCB */N unsigned int wcb$l_reads; /* Count of read I/Os */N unsigned int wcb$l_writes; /* Count of write I/Os */N unsigned __int64 wcb$q_readbytes; /* Count of read bytes for I/Os */N unsigned __int64 wcb$q_writebytes; /* Count of write bytes for I/Os */ZN unsigned int wcb$l_split_io; /* Count of split I/Os */P unsigned int wcb$l_assist_io; /* Count of file system assisted I/Os */N int wcb$l_fill_5 [5]; /* Longword spare space */N unsigned int wcb$l_stvbn; /* STARTING VBN MAPPED BY WINDOW */N/* NEEDS P1_COUNT IMMEDIATELY */N/* FOLLOWING STVBN */ __union { Z __struct {N unsigned short int wcb$w_p1_count; /* TMP */N char wcb$b_fill_8 [10]; /* PADDING */ } wcb$r_p1_tmp; __struct {N unsigned int wcb$l_p1_count; /* COUNT FIELD OF FIRST POINTER */N unsigned int wcb$l_p1_lbn; /* LBN FIELD OF SECOND POINTER */N unsigned int wcb$l_p1_rvn; /* RVN OF FIRST POINTER */ } wcb$r_p1_fields; Z __struct {N unsigned __int64 wcb$q_deliq; /* DELETE PENDIONG QUEUE */" char wcb$b_fill_7 [4]; } wcb$r_delq_fields; } wcb$r_p1_overlay;N unsigned int wcb$l_p2_count; /* COUNT FIELD OF SECOND POINTER */N unsigned int wcb$l_p2_lbn; /* LBN FIELD OF FIRST POINTER */N unsigned int wcb$l_p2_rvn; /* RVN OF SECOND POINTER */N/* FORMAT OF RETRIEVAL POINTER Z */ } WCB; #if !defined(__VAXC)6#define wcb$b_access wcb$r_access_overlay.wcb$b_accessD#define wcb$v_read wcb$r_access_overlay.wcb$r_access_bits.wcb$v_readF#define wcb$v_write wcb$r_access_overlay.wcb$r_access_bits.wcb$v_writeH#define wcb$v_notfcp wcb$r_access_overlay.wcb$r_access_bits.wcb$v_notfcpH#define wcb$v_shrwcb wcb$r_access_overlay.wcb$r_access_bits.wcb$v_shrwcbN#define wcb$v_overdrawn wcb$r_access_overlay.wcb$r_access_bits.wcb$v_overdrawnL#define wcb$v_complete wcb$r_accZess_overlay.wcb$r_access_bits.wcb$v_completeN#define wcb$v_cathedral wcb$r_access_overlay.wcb$r_access_bits.wcb$v_cathedralH#define wcb$v_expire wcb$r_access_overlay.wcb$r_access_bits.wcb$v_expire0#define wcb$l_acon wcb$r_acon_overlay.wcb$l_aconG#define wcb$v_nowrite wcb$r_acon_overlay.wcb$r_acon_bits0.wcb$v_nowriteC#define wcb$v_dlock wcb$r_acon_overlay.wcb$r_acon_bits0.wcb$v_dlockC#define wcb$v_spool wcb$r_acon_overlay.wcb$r_acon_bits0.wcb$v_spoolG#define wcb$v_writeck wcb$r_acon_overlay.wZcb$r_acon_bits0.wcb$v_writeckG#define wcb$v_seqonly wcb$r_acon_overlay.wcb$r_acon_bits0.wcb$v_seqonlyI#define wcb$v_snapshot wcb$r_acon_overlay.wcb$r_acon_bits0.wcb$v_snapshotG#define wcb$v_writeac wcb$r_acon_overlay.wcb$r_acon_bits0.wcb$v_writeacE#define wcb$v_readck wcb$r_acon_overlay.wcb$r_acon_bits0.wcb$v_readckE#define wcb$v_noread wcb$r_acon_overlay.wcb$r_acon_bits0.wcb$v_noreadG#define wcb$v_notrunc wcb$r_acon_overlay.wcb$r_acon_bits0.wcb$v_notruncG#define wcb$v_control wcb$r_aconZ_overlay.wcb$r_acon_bits0.wcb$v_controlQ#define wcb$v_no_read_data wcb$r_acon_overlay.wcb$r_acon_bits0.wcb$v_no_read_dataK#define wcb$v_noacclock wcb$r_acon_overlay.wcb$r_acon_bits1.wcb$v_noacclockA#define wcb$v_ssio wcb$r_acon_overlay.wcb$r_acon_bits1.wcb$v_ssioI#define wcb$v_readinit wcb$r_acon_overlay.wcb$r_acon_bits1.wcb$v_readinitM#define wcb$v_write_turn wcb$r_acon_overlay.wcb$r_acon_bits1.wcb$v_write_turnC#define wcb$w_p1_count wcb$r_p1_overlay.wcb$r_p1_tmp.wcb$w_p1_countF#define Zwcb$l_p1_count wcb$r_p1_overlay.wcb$r_p1_fields.wcb$l_p1_countB#define wcb$l_p1_lbn wcb$r_p1_overlay.wcb$r_p1_fields.wcb$l_p1_lbnB#define wcb$l_p1_rvn wcb$r_p1_overlay.wcb$r_p1_fields.wcb$l_p1_rvnB#define wcb$q_deliq wcb$r_p1_overlay.wcb$r_delq_fields.wcb$q_deliq"#endif /* #if !defined(__VAXC) */  #define WCB$K_MAP_PTR_LENGTH 12#define WCB$C_MAP_PTR_LENGTH 12N#define WCB$S_WCBDEF1 12 /* Old size name - synonym */ typedef struct _wcb1 {N unsigned int w Zcb$l_count; /* COUNT FIELD */N unsigned int wcb$l_lbn; /* LBN FIELD */N unsigned int wcb$l_rvn; /* RVN FIELD */ } WCB1;N#define WCB$S_WCBDEF2 13 /* Old size name - synonym */ Atypedef struct _wcb2 { /* WARNING: aggregate has origin of -12 */> /* WARNING: aggregate element "wcb$l_prevcount" ignored */< /* WARNING: aggregate element "wcb$l_prevlbn" ignoZred */< /* WARNING: aggregate element "wcb$l_prevrvn" ignored */N/* RETRIEVAL POINTER FORMAT */ char wcb$$_fill_6; } WCB2;  #ifdef __INITIAL_POINTER_SIZE&#pragma __required_pointer_size __save&#pragma __required_pointer_size __longtypedef WCB * WCB_PQ;typedef WCB1 * WCB1_PQ;'#pragma __required_pointer_size __shorttypedef WCB * WCB_PL;typedef WCB1 * WCB1_PL;)#pragma __required_pointer_size __restore#elsetypeZdef __int64 WCB_PQ;typedef __int64 WCB1_PQ;typedef __int32 WCB_PL;typedef __int32 WCB1_PL;,#endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __WCBDEF_LOADED */ ww [UM/*******Z********************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-PackaZrd Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. Z **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */F/* Source: 07-APR-1998 16:13:02 $1$DGA8345:[LIB_H.SRC]WQHDEF.SDL;1 *//********************************************************* Z***********************************************************************//*** MODULE $WQHDEF ***/#ifndef __WQHDEF_LOADED#define __WQHDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_sizZe __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N Z/*+ */N/* WAIT QUEUE HEADER DEFINITIONS */N/*- */ N#define WQH$K_LENGTH 16 /*LENGTH OF WAIT QUEUE HEADER */N#define WQH$C_LENGTH 16 /*LENGTH OF WAIT QUEUE HEADER */#define WQH$S_WQHDEF 16 c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If us Zing pre DECC V4.0 or C++ */'#pragma __nomember_alignment __longword#else#pragma __nomember_alignment#endiftypedef struct _wqh {#pragma __nomember_alignmentN struct _wqh *wqh$l_wqfl; /*HEAD OR FORWARD LINK */N struct _wqh *wqh$l_wqbl; /*TAIL OR BACKWARD LINK */N unsigned int wqh$l_wqcnt; /*WAIT QUEUE COUNT */N unsigned int wqh$l_wqstate; /*STATE NUMBER FOR WAIT */ } WQH; Z$#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __WQHDEF_LOADED */ ww0[UM/***************************************************************************/M/** **Z/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC.Z CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***********************************************Z****************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */F/* Source: 23-JUN-2022 15:11:28 $1$DGA8345:[LIB_H.SRC]WSLDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $WSLDEF ***/#ifndef __WSLDEF_LOADED#define __WSLDEF_LOADE[D 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#def[ine __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* WORKING SET LIST DEFINITIONS [ */N/*- */ #define WSL$M_WSLE_BITS 0x1FF#define WSL$M_VALID 0x1#define WSL$M_PAGTYP 0xE#define WSL$M_PFNLOCK 0x10#define WSL$M_WSLOCK 0x20#define WSL$M_MODIFY 0x100N#define WSL$C_LENGTH 8 /* Size of WS list entry */N/* */N#define WSL$C_PROCESS 0 /* Process page */N#d[efine WSL$C_SYSTEM 2 /* System page */N#define WSL$C_GLOBAL 4 /* Global page (read only) */N#define WSL$C_GBLWRT 6 /* Global Writable page */N#define WSL$C_PPGTBL 8 /* Process Page Table */N#define WSL$C_GPGTBL 10 /* Global Page Table */N#define WSL$C_RESERVED 12 /* reserved */g#define WSL$C_UNKNOWN 14 [ /* Uninitialized db for this PFN (should never appear in WS) */#define WSL$S_WSLDEF 8N#define WSL$C_SHIFT_SIZE 3 /* WSLE size as a power of 2 */ c#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _wsl {#pragma __nomember_alignment __union {R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr siz [e pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *wsl$pq_va; /* 64-bit address */#else unsigned __int64 wsl$pq_va;#endif __union {N unsigned wsl$v_wsle_bits : 9; /* Mask for WSLE Bits */ __struct {N unsigned wsl$v_valid : 1; /* WSL entry Valid */S unsigned wsl$v_pagtyp : 3; /* Page type (s[ee $PFNDEF for values) */N unsigned wsl$v_pfnlock : 1; /* Page frame lock */N/* THE PRECEDING 5 BITS MUST BE IN ORDER */N unsigned wsl$v_wslock : 1; /* Working set lock */N unsigned wsl$v_fill_1 : 2; /* Spare bits */N unsigned wsl$v_modify : 1; /* Saved modify bit */+ unsigned wsl$v_fill_0_ : 7;$ } wsl$r_wsldef_b[its;& } wsl$r_wsle_bits_overlay; } wsl$r_wsle_overlay;N/* PAGE TYPE VIELD DEFINITIONS */N/* */o/* These constants have been adjusted by left-shifting the constant by the offset to the field WSL$V_PAGTYP. */f/* To use these when explicitly extracting the field, the adjustment must be removed. For example: */N/* [ */C/* IF .wsle [wsl$v_pagtyp] EQL (wsl$c_system ^-wsl$v_pagtyp) */N/* */ } WSL; #if !defined(__VAXC).#define wsl$pq_va wsl$r_wsle_overlay.wsl$pq_vaR#define wsl$v_wsle_bits wsl$r_wsle_overlay.wsl$r_wsle_bits_overlay.wsl$v_wsle_bits\#define wsl$v_valid wsl$r_wsle_overlay.wsl$r_wsle_bits_overlay.wsl$r_wsldef_bits.wsl$v_valid^#define wsl$v_pagtyp wsl$r_wsle_overlay.wsl$r_wsle_bits_overla [y.wsl$r_wsldef_bits.wsl$v_pagtyp`#define wsl$v_pfnlock wsl$r_wsle_overlay.wsl$r_wsle_bits_overlay.wsl$r_wsldef_bits.wsl$v_pfnlock^#define wsl$v_wslock wsl$r_wsle_overlay.wsl$r_wsle_bits_overlay.wsl$r_wsldef_bits.wsl$v_wslock^#define wsl$v_modify wsl$r_wsle_overlay.wsl$r_wsle_bits_overlay.wsl$r_wsldef_bits.wsl$v_modify"#endif /* #if !defined(__VAXC) */  #ifdef __INITIAL_POINTER_SIZEJ#pragma __required_pointer_size __save /* Save current pointer size */E#pragma __required_pointer_siz [e __long /* Pointers are 64-bit */Dtypedef struct _wsl * WSL_PQ; /* Pointer to a WSL structure. */Q#pragma __required_pointer_size __restore /* Return to previous pointer size */#else typedef unsigned __int64 WSL_PQ;##endif /* __INITIAL_POINTER_SIZE */ $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#end [if#ifdef __cplusplus }#endif#pragma __standard #endif /* __WSLDEF_LOADED */ wwP [UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone wit [hout the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the pr [ior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */H [/* Source: 22-JAN-2024 10:40:15 $1$DGA8345:[LIB_H.SRC]X86HWDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $X86HWDEF ***/#ifndef __X86HWDEF_LOADED#define __X86HWDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas [supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif[#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* Registers: */N/* builtins.h defines EFLAGS but not RFLAGS. The 64-bit mode name for this */N/* register is RFLAGS. Define it here temporarily until builtins.h gets */N/* updated. */ #define _X86_REG_RFLAGS 3200#define RFLG$M[_CF 0x1#define RFLG$M_RES1 0x2#define RFLG$M_PF 0x4#define RFLG$M_RES3 0x8#define RFLG$M_AF 0x10#define RFLG$M_RES5 0x20#define RFLG$M_ZF 0x40#define RFLG$M_SF 0x80#define RFLG$M_TF 0x100#define RFLG$M_IF 0x200#define RFLG$M_DF 0x400#define RFLG$M_OF 0x800#define RFLG$M_IOPL 0x3000#define RFLG$M_NT 0x4000#define RFLG$M_RES15 0x8000#define RFLG$M_RF 0x10000#define RFLG$M_VM 0x20000#define RFLG$M_AC 0x40000#define RFLG$M_VIF 0x80000#define RFLG$M_VIP 0x1 [00000#define RFLG$M_ID 0x200000"#define RFLG$M_RES22_31 0xFFC00000 typedef struct _rflags { __union {N unsigned __int64 rflg$q_quadword; /* The entire quadword */ __struct {N unsigned int rflg$l_eflags; /* EFLAGS longword */N unsigned int rflg$l_rsrvd; /* Upper longword reserved */$ } rflg$r_eflags_overlay; __struct {G unsigned rflg$v_cf : 1; /* CF Carry Flag [0] [ */N unsigned rflg$v_res1 : 1; /* Reserved bit 1 (MBO) [1] */H unsigned rflg$v_pf : 1; /* PF Parity Flag [2] */N unsigned rflg$v_res3 : 1; /* Reserved bit 3 (MBZ) [3] */H unsigned rflg$v_af : 1; /* Aux Carry Flag [4] */N unsigned rflg$v_res5 : 1; /* Reserved bit 5 (MBZ) [5] */D unsigned rflg$v_zf : 1; /* Zero Flag [6] */D unsigned rflg$v_sf : 1; [/* Sign Flag [7] */D unsigned rflg$v_tf : 1; /* Trap Flag [8] */N unsigned rflg$v_if : 1; /* Interrupt Enable Flag [9] */H unsigned rflg$v_df : 1; /* Direction Flag [10] */G unsigned rflg$v_of : 1; /* Overflow Flag [11] */H unsigned rflg$v_iopl : 2; /* I/O Priv Level [12-13] */F unsigned rflg$v_nt : 1; /* Nested Task [14] */N unsigned rflg$v_res1[5 : 1; /* Reserved bit 15 (MBZ)[15] */F unsigned rflg$v_rf : 1; /* Resume Flag [16] */H unsigned rflg$v_vm : 1; /* Virt-8086 Mode [17] */N unsigned rflg$v_ac : 1; /* Align Check/Acc Ctrl [18] */M unsigned rflg$v_vif : 1; /* Virt Interrupt Flag [19] */M unsigned rflg$v_vip : 1; /* Virt Interrupt Pend [20] */B unsigned rflg$v_id : 1; /* ID Flag [21] */N [ unsigned rflg$v_res22_31 : 10; /* Reserved (MBZ) [22-31] */! } rflg$r_rflags_bits; } rflg$r_rflags_overlay; } RFLAGS; #if !defined(__VAXC)=#define rflg$q_quadword rflg$r_rflags_overlay.rflg$q_quadwordO#define rflg$l_eflags rflg$r_rflags_overlay.rflg$r_eflags_overlay.rflg$l_eflagsM#define rflg$l_rsrvd rflg$r_rflags_overlay.rflg$r_eflags_overlay.rflg$l_rsrvdD#define rflg$v_cf rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_cfH#define rflg$v_res1 rf[lg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_res1D#define rflg$v_pf rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_pfH#define rflg$v_res3 rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_res3D#define rflg$v_af rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_afH#define rflg$v_res5 rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_res5D#define rflg$v_zf rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_zfD#define rflg$v_sf rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_sfD#define rflg$v_tf rflg$r_r[flags_overlay.rflg$r_rflags_bits.rflg$v_tfD#define rflg$v_if rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_ifD#define rflg$v_df rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_dfD#define rflg$v_of rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_ofH#define rflg$v_iopl rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_ioplD#define rflg$v_nt rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_ntJ#define rflg$v_res15 rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_res15D#define rflg$v_rf rflg$r_rflags_[overlay.rflg$r_rflags_bits.rflg$v_rfD#define rflg$v_vm rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_vmD#define rflg$v_ac rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_acF#define rflg$v_vif rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_vifF#define rflg$v_vip rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_vipD#define rflg$v_id rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_idP#define rflg$v_res22_31 rflg$r_rflags_overlay.rflg$r_rflags_bits.rflg$v_res22_31"#endif /* #if !defined(__VAXC) [*/  typedef struct _gdtr {N unsigned short int gdtr$w_table_limit; /* 16-Bit Table Limit */N unsigned __int64 gdtr$q_lba; /* 64-bit Linear Base Address */ } GDTR; typedef struct _idtr {N unsigned short int idtr$w_table_limit; /* 16-Bit Table Limit */N unsigned __int64 idtr$q_lba; /* 64-bit Linear Base Address */ } IDTR;N/* */N/* Control Regsters */N/* */N/* When loading a control register, reserved bits should always be set */N/* to the values previously read. Otherwise, a General Protection */N/* Fault will occur. */N/* */#define CR0$M_PE 0x1#define CR0$M_MP 0[x2#define CR0$M_EM 0x4#define CR0$M_TS 0x8#define CR0$M_ET 0x10#define CR0$M_NE 0x20#define CR0$M_RES6_15 0xFFC0#define CR0$M_WP 0x10000#define CR0$M_RES17 0x20000#define CR0$M_AM 0x40000!#define CR0$M_RES19_28 0x1FF80000#define CR0$M_NW 0x20000000#define CR0$M_CD 0x40000000#define CR0$M_PG 0x80000000)#define CR0$M_RES32_63 0xFFFFFFFF00000000 typedef struct _cr0 { __union {N unsigned __int64 cr0$q_quadword; /* Entire quad register */ [ __struct {K unsigned cr0$v_pe : 1; /* Protection Enable [0] */M unsigned cr0$v_mp : 1; /* Monitor CoProcessor [1] */D unsigned cr0$v_em : 1; /* Emulation [2] */G unsigned cr0$v_ts : 1; /* Task Switched [3] */H unsigned cr0$v_et : 1; /* Extension Type [4] */G unsigned cr0$v_ne : 1; /* Numeric Error [5] */D unsigned cr0$v_res6_15 : 1[0; /* Reserved [6-15] */G unsigned cr0$v_wp : 1; /* Write Protect [16] */C unsigned cr0$v_res17 : 1; /* Reserved [17] */I unsigned cr0$v_am : 1; /* Alignment Mask [18] */E unsigned cr0$v_res19_28 : 10; /* Reserved [19-28] */G unsigned cr0$v_nw : 1; /* Not Wrt-Thru [29] */G unsigned cr0$v_cd : 1; /* Cache Disable [30] */A unsigned cr0$v_pg : 1; [ /* Paging [31] */E unsigned cr0$v_res32_63 : 32; /* Reserved MBZ [32-63] */ } cr0$r_cr0_bits; } cr0$r_cr0_overlay; } CR0; #if !defined(__VAXC)7#define cr0$q_quadword cr0$r_cr0_overlay.cr0$q_quadword:#define cr0$v_pe cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_pe:#define cr0$v_mp cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_mp:#define cr0$v_em cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_em:#define cr0$v_ts cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_ts:#d [efine cr0$v_et cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_et:#define cr0$v_ne cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_ne:#define cr0$v_wp cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_wp@#define cr0$v_res17 cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_res17:#define cr0$v_am cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_am:#define cr0$v_nw cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_nw:#define cr0$v_cd cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_cd:#define cr0$v_pg cr0$r_cr0_overlay.cr0$r_cr0_bits.cr0$v_pg"#endif /* #if !define ![d(__VAXC) */  typedef struct _cr2 {N __int64 cr2$q_page_fault_address; /* Virtual address that caused */N/* the fault */ } CR2;N/* */S/* An attempt to set a reserved bit in CR3 will cause a General Protection Fault */N/* */#define CR3$M_RES0_2 0x7#define CR3$M_PW "[T 0x8#define CR3$M_PCD 0x10#define CR3$M_RES5_11 0xFE0*#define CR3$M_PGDIRBASE 0xFFFFFFFFFFFFF000 typedef struct _cr3 { __union {N unsigned __int64 cr3$q_quadword; /* Entire quad register */ __struct {C unsigned cr3$v_res0_2 : 3; /* Reserved [0-2] */L unsigned cr3$v_pwt : 1; /* Pg-Lvl Write-Thru [3] */N unsigned cr3$v_pcd : 1; /* Pg-Lvl Cache Disable [4] */C unsigned cr3$v#[_res5_11 : 7; /* Reserved [5-11] */#if defined(__VAXC), unsigned cr3$v_pgdirbase_1 : 32;, unsigned cr3$v_pgdirbase_2 : 20;#elseT unsigned __int64 cr3$v_pgdirbase : 52; /* Page-Directory Base [12-63] */#endif } cr3$r_cr3_bits; } cr3$r_cr3_overlay; } CR3; #if !defined(__VAXC)7#define cr3$q_quadword cr3$r_cr3_overlay.cr3$q_quadword<#define cr3$v_pwt cr3$r_cr3_overlay.cr3$r_cr3_bits.cr3$v_pwt<#define cr3$v_pcd cr3$r_cr $[3_overlay.cr3$r_cr3_bits.cr3$v_pcdH#define cr3$v_pgdirbase cr3$r_cr3_overlay.cr3$r_cr3_bits.cr3$v_pgdirbase"#endif /* #if !defined(__VAXC) */ N/* */S/* An attempt to set a reserved bit in CR4 will cause a General Protection Fault */N/* */#define CR4$M_VME 0x1#define CR4$M_PVI 0x2#define CR4$M_TSD 0x4#define CR4$M_DE 0x8#define CR4$M_PS%[E 0x10#define CR4$M_PAE 0x20#define CR4$M_MCE 0x40#define CR4$M_PGE 0x80#define CR4$M_PCE 0x100#define CR4$M_OSFXSR 0x200#define CR4$M_OSXMMEXCPT 0x400#define CR4$M_UMIP 0x800#define CR4$M_LA57 0x1000#define CR4$M_VMXE 0x2000#define CR4$M_SMXE 0x4000#define CR4$M_RES15 0x8000#define CR4$M_FSGSBASE 0x10000#define CR4$M_PCIDE 0x20000#define CR4$M_OSXSAVE 0x40000#define CR4$M_RES19 0x80000#define CR4$M_SMEP 0x100000#define CR4$M_SMAP 0x200000#define CR4$M_PKE &[0x400000!#define CR4$M_RES23_31 0xFF800000)#define CR4$M_RES32_63 0xFFFFFFFF00000000 typedef struct _cr4 { __union {N unsigned __int64 cr4$q_quadword; /* Entire quad register */ __struct {K unsigned cr4$v_vme : 1; /* Virt-8086 Mode Extensions [0] */K unsigned cr4$v_pvi : 1; /* Prot-mode Virt Interrupts [1] */E unsigned cr4$v_tsd : 1; /* Time Stamp Disable [2] */G unsigned cr4$v_de : 1; /*'[ Debugging Extensions [3] */G unsigned cr4$v_pse : 1; /* Page Size Extensions [4] */L unsigned cr4$v_pae : 1; /* Physical Address Extension [5] */G unsigned cr4$v_mce : 1; /* Machine-Check Enable [6] */E unsigned cr4$v_pge : 1; /* Page Global Enable [7] */M unsigned cr4$v_pce : 1; /* Perf-Monitor Counter Enable [8] */M unsigned cr4$v_osfxsr : 1; /* OS Support: FXSAVE/FXRSTOR [9] */] unsi([gned cr4$v_osxmmexcpt : 1; /* OS Support: Unmasked SIMD FP Exceptions [10] */I unsigned cr4$v_umip : 1; /* U-Mode Inst Prevention [11] */O unsigned cr4$v_la57 : 1; /* 57-bit linear addresses, [12] */N/* i.e., 5-level paging enabled */? unsigned cr4$v_vmxe : 1; /* VMX-Enable [13] */? unsigned cr4$v_smxe : 1; /* SMX-Enable [14] */= unsigned cr4$v_res15 : 1; /* Reserved [1)[5] */D unsigned cr4$v_fsgsbase : 1; /* FSGSBASE-Enable [16] */@ unsigned cr4$v_pcide : 1; /* PCID-Enable [17] */Q unsigned cr4$v_osxsave : 1; /* XSAVE & Proc Ext States-Enable [18] */= unsigned cr4$v_res19 : 1; /* Reserved [19] */Z unsigned cr4$v_smep : 1; /* Enables super-mode execution prevention [20] */W unsigned cr4$v_smap : 1; /* Enables super-mode access prevention [21] */H unsigned cr4$v_pke : *[ 1; /* Protection-Key-Enable [22] */A unsigned cr4$v_res23_31 : 9; /* Reserved [23-31] */E unsigned cr4$v_res32_63 : 32; /* Reserved MBZ [32-63] */ } cr4$r_cr4_bits; } cr4$r_cr4_overlay; } CR4; #if !defined(__VAXC)7#define cr4$q_quadword cr4$r_cr4_overlay.cr4$q_quadword<#define cr4$v_vme cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_vme<#define cr4$v_pvi cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pvi<#define cr4$v_tsd cr4$r_cr4_overlay.cr4$r_ +[cr4_bits.cr4$v_tsd:#define cr4$v_de cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_de<#define cr4$v_pse cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pse<#define cr4$v_pae cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pae<#define cr4$v_mce cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_mce<#define cr4$v_pge cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pge<#define cr4$v_pce cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pceB#define cr4$v_osfxsr cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_osfxsrJ#define cr4$v_osxmmexcpt cr4$r_cr4_overlay.cr4$r ,[_cr4_bits.cr4$v_osxmmexcpt>#define cr4$v_umip cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_umip>#define cr4$v_la57 cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_la57>#define cr4$v_vmxe cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_vmxe>#define cr4$v_smxe cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_smxeF#define cr4$v_fsgsbase cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_fsgsbase@#define cr4$v_pcide cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pcideD#define cr4$v_osxsave cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_osxsave>#define cr4$v_ -[smep cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_smep>#define cr4$v_smap cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_smap<#define cr4$v_pke cr4$r_cr4_overlay.cr4$r_cr4_bits.cr4$v_pke"#endif /* #if !defined(__VAXC) */ N/* */S/* An attempt to set a reserved bit in CR8 will cause a General Protection Fault */N/* */#define CR8$M_TPL 0xF)#define CR8$M_RES_4_.[63 0xFFFFFFFFFFFFFFF0 typedef struct _cr8 { __union {N unsigned __int64 cr8$q_quadword; /* Entire quad register */ __struct {M unsigned cr8$v_tpl : 4; /* Task Priority Level [0-3] */+ unsigned cr8$v_res_4_63_1 : 32;F unsigned cr8$v_res_4_63_2 : 32; /* Reserved MBZ [3-63] */' unsigned cr8$v_fill_0_ : 4; } cr8$r_cr8_bits; } cr8$r_cr8_overlay; } CR8; #if !defined(__VAX/[C)7#define cr8$q_quadword cr8$r_cr8_overlay.cr8$q_quadword<#define cr8$v_tpl cr8$r_cr8_overlay.cr8$r_cr8_bits.cr8$v_tpl"#endif /* #if !defined(__VAXC) */ #define XCR0$M_X87_FPU_MMX 0x1#define XCR0$M_SSE 0x2#define XCR0$M_AVX 0x4#define XCR0$M_BNDREG 0x8#define XCR0$M_BNDCSR 0x10#define XCR0$M_OPMASK 0x20#define XCR0$M_ZMM_HI256 0x40#define XCR0$M_HI16_ZMM 0x80#define XCR0$M_RES8 0x100#define XCR0$M_PKRU 0x200#define XCR0$M_PASID 0x400#define XCR0$M_RES11 0x800#def0[ine XCR0$M_RES12 0x1000#define XCR0$M_RES13 0x2000#define XCR0$M_RES14 0x4000#define XCR0$M_LBR 0x8000#define XCR0$M_RES16 0x10000 #define XCR0$M_XTILE_CFG 0x20000!#define XCR0$M_XTILE_DATA 0x40000*#define XCR0$M_RES19_62 0x7FFFFFFFFFF80000'#define XCR0$M_RES63 0x8000000000000000 typedef struct _xcr0 { __union {N unsigned __int64 xcr0$q_quadword; /* Entire quad register */ __struct {L unsigned xcr0$v_x87_fpu_mmx : 1; /* x87 FPU/MMX 1[state MBO [0] */= unsigned xcr0$v_sse : 1; /* SSE state [1] */= unsigned xcr0$v_avx : 1; /* AVX state [2] */@ unsigned xcr0$v_bndreg : 1; /* BNDREG state [3] */@ unsigned xcr0$v_bndcsr : 1; /* BNDCSR state [4] */@ unsigned xcr0$v_opmask : 1; /* OPMASK state [5] */F unsigned xcr0$v_zmm_hi256 : 1; /* ZMM_Hi256 state [6] */C unsigned xcr0$v_hi16_zmm : 1; /* Hi16_ZMM state [7] */< unsigned2[ xcr0$v_res8 : 1; /* Reserved [8] */@ unsigned xcr0$v_pkru : 1; /* BNDREG state [9] */O unsigned xcr0$v_pasid : 1; /* PASID state [10] */= unsigned xcr0$v_res11 : 1; /* Reserved [11] */= unsigned xcr0$v_res12 : 1; /* Reserved [12] */= unsigned xcr0$v_res13 : 1; /* Reserved [13] */= unsigned xcr0$v_res14 : 1; /* Reserved [14] */> unsigned xcr0$v_lbr : 1; /* LBR state [15] 3[*/= unsigned xcr0$v_res16 : 1; /* Reserved [16] */J unsigned xcr0$v_xtile_cfg : 1; /* XTILE configuration [17] */C unsigned xcr0$v_xtile_data : 1; /* XTILE data [18] */, unsigned xcr0$v_res19_62_1 : 32;D unsigned xcr0$v_res19_62_2 : 12; /* Reserved [19-62] */Q unsigned xcr0$v_res63 : 1; /* Reserved for bit vec expansion [63] */ } xcr0$r_xcr0_bits; } xcr0$r_xcr0_overlay; } XCR0; #if !def4[ined(__VAXC);#define xcr0$q_quadword xcr0$r_xcr0_overlay.xcr0$q_quadwordR#define xcr0$v_x87_fpu_mmx xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_x87_fpu_mmxB#define xcr0$v_sse xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_sseB#define xcr0$v_avx xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_avxH#define xcr0$v_bndreg xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_bndregH#define xcr0$v_bndcsr xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_bndcsrH#define xcr0$v_opmask xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr5[0$v_opmaskN#define xcr0$v_zmm_hi256 xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_zmm_hi256L#define xcr0$v_hi16_zmm xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_hi16_zmmD#define xcr0$v_res8 xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_res8D#define xcr0$v_pkru xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_pkruF#define xcr0$v_pasid xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_pasidB#define xcr0$v_lbr xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_lbrN#define xcr0$v_xtile_cfg xcr0$r_xcr0_overlay.xcr0$r_xcr06[_bits.xcr0$v_xtile_cfgP#define xcr0$v_xtile_data xcr0$r_xcr0_overlay.xcr0$r_xcr0_bits.xcr0$v_xtile_data"#endif /* #if !defined(__VAXC) */ #define MXCSR$M_IE 0x1#define MXCSR$M_DE 0x2#define MXCSR$M_ZE 0x4#define MXCSR$M_OE 0x8#define MXCSR$M_UE 0x10#define MXCSR$M_PE 0x20#define MXCSR$M_DAZ 0x40#define MXCSR$M_IM 0x80#define MXCSR$M_DM 0x100#define MXCSR$M_ZM 0x200#define MXCSR$M_OM 0x400#define MXCSR$M_UM 0x800#define MXCSR$M_PM 0x1000#define MXCSR$M_RC 0x6000 7[#define MXCSR$M_FZ 0x8000##define MXCSR$M_RES16_31 0xFFFF0000+#define MXCSR$M_RES32_63 0xFFFFFFFF00000000 typedef struct _mxcsr { __union {N unsigned __int64 mxcsr$q_quadword; /* Entire register */ __struct {H unsigned mxcsr$v_ie : 1; /* Invalid operation flag [0] */@ unsigned mxcsr$v_de : 1; /* Denormal flag [1] */F unsigned mxcsr$v_ze : 1; /* Divide-by-zero flag [2] */@ unsigned mxcsr$v_oe : 8[1; /* Overflow flag [3] */A unsigned mxcsr$v_ue : 1; /* Underflow flag [4] */A unsigned mxcsr$v_pe : 1; /* Precision flag [5] */F unsigned mxcsr$v_daz : 1; /* Denormals are zeros [6] */H unsigned mxcsr$v_im : 1; /* Invalid operation mask [7] */@ unsigned mxcsr$v_dm : 1; /* Denormal mask [8] */F unsigned mxcsr$v_zm : 1; /* Divide-by-zero mask [9] */A unsigned mxcsr$v_om : 1; /* Overflow ma 9[sk [10] */B unsigned mxcsr$v_um : 1; /* Underflow mask [11] */B unsigned mxcsr$v_pm : 1; /* Precision mask [12] */G unsigned mxcsr$v_rc : 2; /* Rounding Control [13-14] */A unsigned mxcsr$v_fz : 1; /* Flush to Zero [15] */G unsigned mxcsr$v_res16_31 : 16; /* Reserved [16-31] */M unsigned mxcsr$v_res32_63 : 32; /* Fill out to 64 bits [32-63] */! } mxcsr$r_mxcsr_bits; } mxcsr$r_mxcsr_ :[overlay; } MXCSR; #if !defined(__VAXC)?#define mxcsr$q_quadword mxcsr$r_mxcsr_overlay.mxcsr$q_quadwordF#define mxcsr$v_ie mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_ieF#define mxcsr$v_de mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_deF#define mxcsr$v_ze mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_zeF#define mxcsr$v_oe mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_oeF#define mxcsr$v_ue mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_ueF#define mxcsr$v_pe mxcsr$r_mxc;[sr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_peH#define mxcsr$v_daz mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_dazF#define mxcsr$v_im mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_imF#define mxcsr$v_dm mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_dmF#define mxcsr$v_zm mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_zmF#define mxcsr$v_om mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_omF#define mxcsr$v_um mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_umF#define mxcsr$v_pm mxcsr$r_mxc <[sr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_pmF#define mxcsr$v_rc mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_rcF#define mxcsr$v_fz mxcsr$r_mxcsr_overlay.mxcsr$r_mxcsr_bits.mxcsr$v_fz"#endif /* #if !defined(__VAXC) */ N/* Model Specific Registers (MSRs): */N/* Segment Descriptors */#define SEGD$M_TYPE 0xF#define SEGD$M_S 0x10#define SEGD$M_DPL 0x60#define SEGD$M_P 0x80#define SEGD$M_LIMIT=[_HIGH 0xF00#define SEGD$M_AVL 0x1000#define SEGD$M_L 0x2000#define SEGD$M_D_B 0x4000#define SEGD$M_G 0x8000 typedef struct _segd {N unsigned short int segd$w_limit_low; /* Segment Limit 15:00 */N unsigned short int segd$w_base_addr_low; /* Base Address 15:00 */G unsigned char segd$b_base_addr_mid; /* Base Address 23:16 [0-7] */ __union {N unsigned short int segd$w_ignore; /* Overlays Bit fields below */ __struct {< >[ unsigned segd$v_type : 4; /* Type [8-11] */K unsigned segd$v_s : 1; /* Desc type (0 = system; [12] */B/* 1 = code or data) */P unsigned segd$v_dpl : 2; /* Descriptor Privilege Level [13-14] */C unsigned segd$v_p : 1; /* Segment Present [15] */N unsigned segd$v_limit_high : 4; /* Segment Limit 19:16 [16-19] */P unsigned segd$v_avl : 1; /* Available for system softwa ?[re [20] */G unsigned segd$v_l : 1; /* 64-bit code segment [21] */J unsigned segd$v_d_b : 1; /* Default operation size [22] */N/* (0 = 16-bit segment; 1 = 32-bit segment) */@ unsigned segd$v_g : 1; /* Granularity [23] */ } segd$r_tss_fields;# } segd$r_tss_fields_ovrlay;I unsigned char segd$b_base_addr_hi; /* Base Address 31:24 [24-31] */ } SEGD; #if !defined(__VAXC)J#define se@[gd$v_type segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_typeD#define segd$v_s segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_sH#define segd$v_dpl segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_dplD#define segd$v_p segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_pV#define segd$v_limit_high segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_limit_highH#define segd$v_avl segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_avlD#define segd$v_l segd$r_tss_fields_ovrlay.segd$r_tss_fields.segdA[$v_lH#define segd$v_d_b segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_d_bD#define segd$v_g segd$r_tss_fields_ovrlay.segd$r_tss_fields.segd$v_g"#endif /* #if !defined(__VAXC) */ #define IDTD$M_IST 0x7#define IDTD$M_MBZ3 0x8#define IDTD$M_MBZ4 0x10#define IDTD$M_MBZ5_7 0xE0#define IDTD$M_TYPE 0xF00#define IDTD$M_MBZ12 0x1000#define IDTD$M_DPL 0x6000#define IDTD$M_P 0x8000 typedef struct _idtd { __union {* unsigned __int64 idtd$q_quadword1; __st B[ruct {N unsigned short int idtd$w_offset_low; /* Offset 15..0 */c unsigned short int idtd$w_selector; /* Segment Selector for destination code segment */ __struct {J unsigned idtd$v_ist : 3; /* Interrupt Stack Table [0-2] */B unsigned idtd$v_mbz3 : 1; /* Must Be Zero [3] */B unsigned idtd$v_mbz4 : 1; /* Must Be Zero [4] */F unsigned idtd$v_mbz5_7 : 3; /* Must Be Zero [5-7] */> C[ unsigned idtd$v_type : 4; /* Type [8-11] */D unsigned idtd$v_mbz12 : 1; /* Must Be Zero [12] */Q unsigned idtd$v_dpl : 2; /* Descriptor Privilege Level [13-14] */H unsigned idtd$v_p : 1; /* Segment Present flag [15] */& } idtd$r_idt64_fields;N unsigned short int idtd$w_offset_mid; /* Offset 31..16 */ } idtd$r_qw1_fields; } idtd$r_qw1_overlay; __union {* unsigned D[ __int64 idtd$q_quadword2; __struct {N unsigned int idtd$l_offset_hi; /* Offset 63..32 */N unsigned int idtd$l_reserved; /* Reserved */ } idtd$r_qw2_fields; } idtd$r_qw2_overlay; } IDTD; #if !defined(__VAXC)<#define idtd$q_quadword1 idtd$r_qw1_overlay.idtd$q_quadword1P#define idtd$w_offset_low idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$w_offset_lowL#define idtd$w_selector idtd$r_qw1_overlay.idtE[d$r_qw1_fields.idtd$w_selectorV#define idtd$v_ist idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$r_idt64_fields.idtd$v_istX#define idtd$v_type idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$r_idt64_fields.idtd$v_typeV#define idtd$v_dpl idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$r_idt64_fields.idtd$v_dplR#define idtd$v_p idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$r_idt64_fields.idtd$v_pP#define idtd$w_offset_mid idtd$r_qw1_overlay.idtd$r_qw1_fields.idtd$w_offset_mid<#define idtd$q_quadword2 idtd$r_qw2_overla F[y.idtd$q_quadword2N#define idtd$l_offset_hi idtd$r_qw2_overlay.idtd$r_qw2_fields.idtd$l_offset_hi"#endif /* #if !defined(__VAXC) */ #define IDTD$C_LENGTH 16N/* X86 interrupt vectors */N#define X86_IDT$C_DE 0 /* 0 Divide error */N#define X86_IDT$C_DB 1 /* 1 Debug */N#define X86_IDT$C_NMI 2 /* 2 Non-Maskable Interrupt */N#define X86_IDT$C_BPG[ 3 /* 3 Breakpoint */N#define X86_IDT$C_OF 4 /* 4 Integer overflow */N#define X86_IDT$C_BR 5 /* 5 Bound range exceeded */N#define X86_IDT$C_UD 6 /* 6 Invalid opcode */N#define X86_IDT$C_NM 7 /* 7 No math */N#define X86_IDT$C_DF 8 /* 8 Double fault */N#define X86_IDT$C_RSV_9 9 /* 9 H[Reserved */N#define X86_IDT$C_TS 10 /* 10 Invalid TSS */N#define X86_IDT$C_NP 11 /* 11 Segment not present */N#define X86_IDT$C_SS 12 /* 12 Stack segment fault */N#define X86_IDT$C_GP 13 /* 13 General protection fault */N#define X86_IDT$C_PF 14 /* 14 Page fault */N#define X86_IDT$C_RSV_15 15 /* 15 Reserved I[ */N#define X86_IDT$C_MF 16 /* 16 Math fault */N#define X86_IDT$C_AC 17 /* 17 Alignment check */N#define X86_IDT$C_MC 18 /* 18 Machine check exception */N#define X86_IDT$C_XM 19 /* 19 SIMD Floating point exception */N#define X86_IDT$C_VE 20 /* 20 Virtualization exception */N#define X86_IDT$C_CP 21 /* 21 Control Protection Exception */N#define X86_IDT$C_J[RSV_22 22 /* 22 Reserved */N#define X86_IDT$C_RSV_23 23 /* 23 Reserved */N#define X86_IDT$C_RSV_24 24 /* 24 Reserved */N#define X86_IDT$C_RSV_25 25 /* 25 Reserved */N#define X86_IDT$C_RSV_26 26 /* 26 Reserved */N#define X86_IDT$C_RSV_27 27 /* 27 Reserved */N#define X86_IDT$C_RSV_28 28 /* 2K[8 Reserved */N#define X86_IDT$C_VC 29 /* 29 VMM Comm Exception */N#define X86_IDT$C_SX 30 /* 30 Security exception */N#define X86_IDT$C_RSV_31 31 /* 31 Reserved */N#define X86_IDT$C_BREAK 32 /* 32 */N#define X86_IDT$C_HW_START 33 /* 33 is first hardware interrupt */N/* TSS (or LDT) Descriptor. L[ */#define TSSD$M_TYPE 0xF#define TSSD$M_MBZ9 0x10#define TSSD$M_DPL 0x60#define TSSD$M_P 0x80#define TSSD$M_LIMIT_HIGH 0xF00#define TSSD$M_AVL 0x1000#define TSSD$M_MBZ21 0x2000#define TSSD$M_MBZ22 0x4000#define TSSD$M_G 0x8000#define TSSD$M_RESERVED0_7 0xFF#define TSSD$M_MBZ8_12 0x1F00'#define TSSD$M_RESERVED13_31 0xFFFFE000 typedef struct _tssd {N unsigned short int tssd$w_limit_low; /* Segment Limit 15:00 */N unsigned short int tssd$w_ M[base_addr_low; /* Base Address 15:00 */H unsigned char tssd$b_base_addr_mid1; /* Base Address 23:16 [0-7] */ __union {N unsigned short int tssd$w_ignore; /* Overlays Bit fields below */ __struct {< unsigned tssd$v_type : 4; /* Type [8-11] */9 unsigned tssd$v_mbz9 : 1; /* MBZ [12] */P unsigned tssd$v_dpl : 2; /* Descriptor Privilege Level [13-14] */C unsigned tssd$v_p : 1; /* Segment Present N[[15] */N unsigned tssd$v_limit_high : 4; /* Segment Limit 19:16 [16-19] */P unsigned tssd$v_avl : 1; /* Available for system software [20] */9 unsigned tssd$v_mbz21 : 1; /* MBZ [21] */9 unsigned tssd$v_mbz22 : 1; /* MBZ [22] */@ unsigned tssd$v_g : 1; /* Granularity [23] */ } tssd$r_tss_fields;# } tssd$r_tss_fields_ovrlay;J unsigned char tssd$b_base_addr_mid2; /* Base Address 31:24 [24-31] */N O[ unsigned int tssd$l_base_addr_hi; /* Base Address 63:32 */ __struct {? unsigned tssd$v_reserved0_7 : 8; /* Reserved [0-7] */C unsigned tssd$v_mbz8_12 : 5; /* Must Be Zero [8-12] */D unsigned tssd$v_reserved13_31 : 19; /* Reserved [13-31] */! } tssd$r_reserved_fields; } TSSD; #if !defined(__VAXC)J#define tssd$v_type tssd$r_tss_fields_ovrlay.tssd$r_tss_fields.tssd$v_typeH#define tssd$v_dpl tssd$r_tss_fields_ovrlay.tssd$rP[_tss_fields.tssd$v_dplD#define tssd$v_p tssd$r_tss_fields_ovrlay.tssd$r_tss_fields.tssd$v_pV#define tssd$v_limit_high tssd$r_tss_fields_ovrlay.tssd$r_tss_fields.tssd$v_limit_highH#define tssd$v_avl tssd$r_tss_fields_ovrlay.tssd$r_tss_fields.tssd$v_avlD#define tssd$v_g tssd$r_tss_fields_ovrlay.tssd$r_tss_fields.tssd$v_gD#define tssd$v_reserved0_7 tssd$r_reserved_fields.tssd$v_reserved0_7<#define tssd$v_mbz8_12 tssd$r_reserved_fields.tssd$v_mbz8_12H#define tssd$v_reserved13_31 tssd$r_reserved_fieQ[lds.tssd$v_reserved13_31"#endif /* #if !defined(__VAXC) */ N/* Page Fault Exception Error Code definitions */#define ERRC$M_P 0x1#define ERRC$M_RW 0x2#define ERRC$M_US 0x4#define ERRC$M_R 0x8#define ERRC$M_I 0x10 typedef struct _error_code { __union {N unsigned __int64 errc$q_quadword; /* The entire quadword */ __struct {H unsigned errc$v_p : 1; /* Present => 1 [0] */E unsign R[ed errc$v_rw : 1; /* Write => 1 [1] */D unsigned errc$v_us : 1; /* User => 1 [2] */N unsigned errc$v_r : 1; /* Reserved bit set => 1 [3] */N unsigned errc$v_i : 1; /* Instruction fetch => 1 [4] */( unsigned errc$v_fill_1_ : 3;% } errc$r_error_code_bits;$ } errc$r_error_code_overlay; } ERROR_CODE; #if !defined(__VAXC)A#define errc$q_quadword errc$r_error_code_overlay.errc$q S[_quadwordJ#define errc$v_p errc$r_error_code_overlay.errc$r_error_code_bits.errc$v_pL#define errc$v_rw errc$r_error_code_overlay.errc$r_error_code_bits.errc$v_rwL#define errc$v_us errc$r_error_code_overlay.errc$r_error_code_bits.errc$v_usJ#define errc$v_r errc$r_error_code_overlay.errc$r_error_code_bits.errc$v_rJ#define errc$v_i errc$r_error_code_overlay.errc$r_error_code_bits.errc$v_i"#endif /* #if !defined(__VAXC) */  typedef struct _xmmreg {# unsigned __int64 xmm$q_lowpart;$ T[ unsigned __int64 xmm$q_highpart; } XMMREG; typedef struct _stmreg {# unsigned __int64 stm$q_lowpart;& unsigned short int stm$w_highpart;" unsigned char stm$b_resvd [6]; } STMREG; typedef struct _xsave {N unsigned short int xsv$w_fcw; /* FPU Control Word */N unsigned short int xsv$w_fsw; /* FPU Status Word */N unsigned short int xsv$w_ftw; /* FPU Tag Word + rsvd byte */N unsigned short int x U[sv$w_fop; /* FPU Opcode */ __union { __struct {N unsigned __int64 xsv$q_rip; /* FPU Instruction Pointer */N unsigned __int64 xsv$q_rdp; /* FPU Data Pointer */ } xsv$r_rregs; __struct {N unsigned int xsv$l_fip; /* FPU IP Offset */N unsigned int xsv$l_fcs; /* FPU IP Selector */N unsigned int xsv$l_foo; /* V[ FPU Operand Offset */N unsigned int xsv$l_fos; /* FPU Operand Selector */ } xsv$r_fregs; } xsv$r_fpureg_overlay;N unsigned int xsv$l_mxcsr; /* MXCSR Register State */N unsigned int xsv$l_mxcsr_mask; /* MXCSR Mask */N STMREG xsv$r_st_regs [8]; /* 8x 10-byte STx/MMx + 6-byte rsvd */N XMMREG xsv$r_xmm_regs [16]; /* 16x 16-byte XMMx */N un W[signed __int64 xsv$q_resvd [12]; /* Part padding part reserved */ } XSAVE; #if !defined(__VAXC)<#define xsv$q_rip xsv$r_fpureg_overlay.xsv$r_rregs.xsv$q_rip<#define xsv$q_rdp xsv$r_fpureg_overlay.xsv$r_rregs.xsv$q_rdp<#define xsv$l_fip xsv$r_fpureg_overlay.xsv$r_fregs.xsv$l_fip<#define xsv$l_fcs xsv$r_fpureg_overlay.xsv$r_fregs.xsv$l_fcs<#define xsv$l_foo xsv$r_fpureg_overlay.xsv$r_fregs.xsv$l_foo<#define xsv$l_fos xsv$r_fpureg_overlay.xsv$r_fregs.xsv$l_fos"#endif /* #if !defiX[ned(__VAXC) */ #define XHD$M_X87_FPU_MMX 0x1#define XHD$M_SSE 0x2#define XHD$M_AVX 0x4#define XHD$M_BNDREG 0x8#define XHD$M_BNDCSR 0x10#define XHD$M_OPMASK 0x20#define XHD$M_ZMM_HI256 0x40#define XHD$M_HI16_ZMM 0x80#define XHD$M_RES8 0x100#define XHD$M_PKRU 0x200#define XHD$M_PASID 0x400#define XHD$M_RES11 0x800#define XHD$M_RES12 0x1000#define XHD$M_RES13 0x2000#define XHD$M_RES14 0x4000#define XHD$M_LBR 0x8000#define XHD$M_RES16 0x10000#define XHD$M_XTY[ILE_CFG 0x20000 #define XHD$M_XTILE_DATA 0x40000#define XHD$M_RES19_63 0x80000#define XHD$M_COMPACTED 0x1#define XHD$M_RES1_63 0x2 typedef struct _xsave_hdr { __union {' unsigned __int64 xhd$q_feature; __struct {K unsigned xhd$v_x87_fpu_mmx : 1; /* x87 FPU/MMX state MBO [0] */= unsigned xhd$v_sse : 1; /* SSE state [1] */= unsigned xhd$v_avx : 1; /* AVX state [2] */@ unsigned xhd$v_bndreg : 1; /* B Z[NDREG state [3] */@ unsigned xhd$v_bndcsr : 1; /* BNDCSR state [4] */@ unsigned xhd$v_opmask : 1; /* OPMASK state [5] */E unsigned xhd$v_zmm_hi256 : 1; /* ZMM_Hi256 state [6] */B unsigned xhd$v_hi16_zmm : 1; /* Hi16_ZMM state [7] */< unsigned xhd$v_res8 : 1; /* Reserved [8] */@ unsigned xhd$v_pkru : 1; /* BNDREG state [9] */O unsigned xhd$v_pasid : 1; /* PASID state [10] */= [[ unsigned xhd$v_res11 : 1; /* Reserved [11] */= unsigned xhd$v_res12 : 1; /* Reserved [12] */= unsigned xhd$v_res13 : 1; /* Reserved [13] */= unsigned xhd$v_res14 : 1; /* Reserved [14] */> unsigned xhd$v_lbr : 1; /* LBR state [15] */= unsigned xhd$v_res16 : 1; /* Reserved [16] */I unsigned xhd$v_xtile_cfg : 1; /* XTILE configuration [17] */B unsigned xhd$v_xtile_data : 1; /* XT \[ILE data [18] */+ unsigned xhd$v_res19_63_1 : 32;i unsigned xhd$v_res19_63_2 : 13 /** WARNING: bitfield array has been reduced to a string **/ ;! } xhd$r_feature_bits; } xhd$r_feature_overlay; __union {( unsigned __int64 xhd$q_xcomp_bv; __struct {) unsigned xhd$v_compacted : 1;* unsigned xhd$v_res1_63_1 : 32;h unsigned xhd$v_res1_63_2 : 31 /** WARNING: bitfield array has been reduced to a st ][ring **/ ;" } xhd$r_xcomp_bv_bits;! } xhd$r_xcomp_bv_overlay;( unsigned __int64 xhd$q_reserved [6]; } XSAVE_HDR; #if !defined(__VAXC)9#define xhd$q_feature xhd$r_feature_overlay.xhd$q_featureT#define xhd$v_x87_fpu_mmx xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_x87_fpu_mmxD#define xhd$v_sse xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_sseD#define xhd$v_avx xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_avxJ#define xhd$v_bndreg xhd$r_feature_overlay.xhd$r_f^[eature_bits.xhd$v_bndregJ#define xhd$v_bndcsr xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_bndcsrJ#define xhd$v_opmask xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_opmaskP#define xhd$v_zmm_hi256 xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_zmm_hi256N#define xhd$v_hi16_zmm xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_hi16_zmmF#define xhd$v_res8 xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_res8F#define xhd$v_pkru xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_pkruH#define xhd$v_pasid xh _[d$r_feature_overlay.xhd$r_feature_bits.xhd$v_pasidD#define xhd$v_lbr xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_lbrP#define xhd$v_xtile_cfg xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_xtile_cfgR#define xhd$v_xtile_data xhd$r_feature_overlay.xhd$r_feature_bits.xhd$v_xtile_data<#define xhd$q_xcomp_bv xhd$r_xcomp_bv_overlay.xhd$q_xcomp_bvR#define xhd$v_compacted xhd$r_xcomp_bv_overlay.xhd$r_xcomp_bv_bits.xhd$v_compacted"#endif /* #if !defined(__VAXC) */ N/* `[ */N/* XSAVE area 2 - The high 128 bits of YMM0-15 */N/* */ typedef struct _ymmh { __struct {! int ymmh$l_ymmh_long [4]; } ymmh$r_ymmh_reg [16]; } YMMH; #if !defined(__VAXC))#define ymmh$l_ymmh_long ymmh$l_ymmh_long"#endif /* #if !defined(__VAXC) */ N/* a[ */N/* XSAVE area 3 - Bound register pairs */N/* */ typedef struct _bnd {$ unsigned __int64 bnd$q_bnd_low0;% unsigned __int64 bnd$q_bnd_high0;$ unsigned __int64 bnd$q_bnd_low1;% unsigned __int64 bnd$q_bnd_high1;$ unsigned __int64 bnd$q_bnd_low2;% unsigned __int64 bnd$q_bnd_high2;$ unsigned __int64 bnd$q_bnd_low3;% unsigned __int64 bnd b[$q_bnd_high3; } BND;N/* */N/* XSAVE area 4 - Bound register control and status registers, plus pad */N/* */ typedef struct _bndcsr {& unsigned __int64 bndcsr$q_bnd_cfg;& unsigned __int64 bndcsr$q_bnd_sts; char bndcsr$b_pad [48]; } BNDCSR;N/* */N/* c[ XSAVE area 5 - Quadword opmask registers */N/* */ typedef struct _opmask {& unsigned __int64 opmask$q_opmask0;& unsigned __int64 opmask$q_opmask1;& unsigned __int64 opmask$q_opmask2;& unsigned __int64 opmask$q_opmask3;& unsigned __int64 opmask$q_opmask4;& unsigned __int64 opmask$q_opmask5;& unsigned __int64 opmask$q_opmask6;& unsigned __int64 opmask$q_opmask7;d[ } OPMASK;N/* */N/* XSAVE area 6 - The high 256 bits of ZMM0-15 */N/* */ typedef struct _zmmh { __struct {! int zmmh$l_zmmh_long [8]; } zmmh$r_zmmh_reg [16]; } ZMMH; #if !defined(__VAXC))#define zmmh$l_zmmh_long zmmh$l_zmmh_long"#endif /* #if !defined(__VAXC) */ N/* e[ */U/* XSAVE area 7 - ZMM16-31 (512-bits), YMM16-31 (256-bits) and XMM16-31 (128-bits) */N/* */ typedef struct _hi16_zmm { __struct {* int hi16_zmm$l_hi16_zmm_long [16];' } hi16_zmm$r_hi16_zmm_reg [16]; } HI16_ZMM; #if !defined(__VAXC)9#define hi16_zmm$l_hi16_zmm_long hi16_zmm$l_hi16_zmm_long"#endif /* #if !defined(__ f[VAXC) */ N/* */N/* XSAVE area 8 - Unimplemented */N/* */N/* */X/* XSAVE area 9 - PKRU registers, currently only 32-bit of reserved 64-bits are used. */N/* */ g[typedef struct _pkru { unsigned int pkru$l_pkru; char pkru$b_pad [4]; } PKRU;N/* */N/* XSAVE area 10 - PASID state */N/* */ typedef struct _pasid_state {# unsigned __int64 pasid$q_pasid; } PASID_STATE;N/* h[ */N/* XSAVE area 11, 12, 13 and 14 are not implemented. */N/* */N/* */N/* XSAVE area 15 - LBR */N/* */ typedef struct _lbr { unsigned __int64 lbr$q_ctl;! unsigned __int64 lbr$q_depth;$ i[ unsigned __int64 lbr$q_ler_from;" unsigned __int64 lbr$q_ler_to;$ unsigned __int64 lbr$q_ler_info;Z unsigned __int64 lbr$q_from; /* Start of three element array of DEPTH length */ unsigned __int64 lbr$q_to; unsigned __int64 lbr$q_info; } LBR;N/* */N/* XSAVE area 16 not implemented. */N/* j[ */N/* */N/* XSAVE area 17 - XTILE_CFG */N/* */ typedef struct _xtile_cfg {* unsigned __int64 xtile_cfg$q_tcfg [8]; } XTILE_CFG;N/* */T/* XSAVE area 18 - XTILE data registers. Each register represent 16 64-byte k[ rows */X/* of the matrix data. The number of registers depends on the actual implementation. */N/* */ typedef struct _xtile { char xtile$b_tcfg [128]; } XTILE; $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplusl[ }#endif#pragma __standard #endif /* __X86HWDEF_LOADED */ ww[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** m[prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permissin[on of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */I/* Source: 26-AUG-2 o[019 04:31:01 $1$DGA8345:[LIB_H.SRC]X86MSRDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $X86MSRDEF ***/#ifndef __X86MSRDEF_LOADED#define __X86MSRDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pp[ragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #iq[fndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/* MSR register numbers */"#define X86_MSR$_IA32_APIC_BASE 27+#define X86_MSR$_IA32_ARCH_CAPABILITIES 266%#define X86_MSR$_IA32_EFER 3221225600&#define X86_MSR$_IA32_FMASK 3221225604(#define X86_MSR$_IA32_FS_BASE 3221225728(#define X86_MSR$_IA32_GS_BASE 3221225729/#define X86_MSR$_IA32_KERNEL_GS_BASE 3221225730&#define r[X86_MSR$_IA32_LSTAR 3221225602%#define X86_MSR$_IA32_MISC_ENABLE 416N#define X86_MSR$_PLATFORM_INFO 206 /* Contents are platform specific */!#define X86_MSR$_IA32_MTRRCAP 254'#define X86_MSR$_IA32_MTRR_DEF_TYPE 767+#define X86_MSR$_IA32_MTRR_FIX16K_80000 600+#define X86_MSR$_IA32_MTRR_FIX16K_A0000 601*#define X86_MSR$_IA32_MTRR_FIX4K_C0000 616*#define X86_MSR$_IA32_MTRR_FIX4K_C8000 617*#define X86_MSR$_IA32_MTRR_FIX4K_D0000 618*#define X86_MSR$_IA32_MTRR_FIX4K_D8000 619*#define s[X86_MSR$_IA32_MTRR_FIX4K_E0000 620*#define X86_MSR$_IA32_MTRR_FIX4K_E8000 621*#define X86_MSR$_IA32_MTRR_FIX4K_F0000 622*#define X86_MSR$_IA32_MTRR_FIX4K_F8000 623+#define X86_MSR$_IA32_MTRR_FIX64K_00000 592(#define X86_MSR$_IA32_MTRR_PHYSBASE0 512(#define X86_MSR$_IA32_MTRR_PHYSMASK0 513(#define X86_MSR$_IA32_MTRR_PHYSBASE1 514(#define X86_MSR$_IA32_MTRR_PHYSMASK1 515(#define X86_MSR$_IA32_MTRR_PHYSBASE2 516(#define X86_MSR$_IA32_MTRR_PHYSMASK2 517(#define X86_MSR$_IA32_MTRR_PHYSBASE3 518 t[(#define X86_MSR$_IA32_MTRR_PHYSMASK3 519(#define X86_MSR$_IA32_MTRR_PHYSBASE4 520(#define X86_MSR$_IA32_MTRR_PHYSMASK4 521(#define X86_MSR$_IA32_MTRR_PHYSBASE5 522(#define X86_MSR$_IA32_MTRR_PHYSMASK5 523(#define X86_MSR$_IA32_MTRR_PHYSBASE6 524(#define X86_MSR$_IA32_MTRR_PHYSMASK6 525(#define X86_MSR$_IA32_MTRR_PHYSBASE7 526(#define X86_MSR$_IA32_MTRR_PHYSMASK7 527(#define X86_MSR$_IA32_MTRR_PHYSBASE8 528(#define X86_MSR$_IA32_MTRR_PHYSMASK8 529(#define X86_MSR$_IA32_MTRR_PHYSBASE9 530( u[#define X86_MSR$_IA32_MTRR_PHYSMASK9 531#define X86_MSR$_IA32_PAT 631%#define X86_MSR$_IA32_STAR 3221225601N/* Machinecheck MSRs */!#define X86_MSR$_IA32_MCG_CAP 377$#define X86_MSR$_IA32_MCG_STATUS 378!#define X86_MSR$_IA32_MCG_CTL 379N#define X86_MSR$_IA32_MC0_CTL 1024 /* IA32_MC1_CTL at 404, etc... */N#define X86_MSR$_IA32_MC0_STATUS 1025 /* IA32_MC1_CTL at 405, etc... */N#define X86_MSR$_IA32_MC0_ADDR 1026 /*v[ IA32_MC1_CTL at 406, etc... */N#define X86_MSR$_IA32_MC0_MISC 1027 /* IA32_MC1_CTL at 407, etc... */N#define X86_MSR$_IA32_MC0_CTL2 640 /* IA32_MC1_CTL2 at 281, etc... */N/* x2APIC MSRs */(#define X86_MSR$_IA32_X2APIC_APICID 2050)#define X86_MSR$_IA32_X2APIC_VERSION 2051N#define X86_MSR$_IA32_X2APIC_TPR 2056 /* Task priority */N#define X86_MSR$_IA32_X2APIC_PPR 2058 /* Processor priority w[ */N#define X86_MSR$_IA32_X2APIC_EOI 2059 /* End of interrupt */N#define X86_MSR$_IA32_X2APIC_LDR 2061 /* Logical destination */N#define X86_MSR$_IA32_X2APIC_SPURIOUS_INT 2063 /* Spurious interrupt */N#define X86_MSR$_IA32_X2APIC_ISR_31_0 2064 /* In-service 31:0 */N#define X86_MSR$_IA32_X2APIC_ISR_63_32 2065 /* In-service 64:32 */N#define X86_MSR$_IA32_X2APIC_ISR_95_64 2066 /* In-service 95:64 */N#define x[X86_MSR$_IA32_X2APIC_ISR_127_96 2067 /* In-service 127:96 */N#define X86_MSR$_IA32_X2APIC_ISR_159_128 2068 /* In-service 159:128 */N#define X86_MSR$_IA32_X2APIC_ISR_191_160 2069 /* In-service 191:160 */N#define X86_MSR$_IA32_X2APIC_ISR_223_192 2070 /* In-service 223:192 */N#define X86_MSR$_IA32_X2APIC_ISR_255_224 2071 /* In-service 255:224 */N#define X86_MSR$_IA32_X2APIC_TMR_31_0 2072 /* Trigger mode 31:0 */N#define X86_MSR$_IA32_X2APIC_TMR_6y[3_32 2073 /* Trigger mode 64:32 */N#define X86_MSR$_IA32_X2APIC_TMR_95_64 2074 /* Trigger mode 95:64 */N#define X86_MSR$_IA32_X2APIC_TMR_127_96 2075 /* Trigger mode 127:96 */N#define X86_MSR$_IA32_X2APIC_TMR_159_128 2076 /* Trigger mode 159:128 */N#define X86_MSR$_IA32_X2APIC_TMR_191_160 2077 /* Trigger mode 191:160 */N#define X86_MSR$_IA32_X2APIC_TMR_223_192 2078 /* Trigger mode 223:192 */N#define X86_MSR$_IA32_X2APIC_TMR_255_224 2079 /* Trigger modz[e 255:224 */N#define X86_MSR$_IA32_X2APIC_IRR_31_0 2080 /* Interrupt request 31:0 */N#define X86_MSR$_IA32_X2APIC_IRR_63_32 2081 /* Interrupt request 64:32 */N#define X86_MSR$_IA32_X2APIC_IRR_95_64 2082 /* Interrupt request 95:64 */N#define X86_MSR$_IA32_X2APIC_IRR_127_96 2083 /* Interrupt request 127:96 */N#define X86_MSR$_IA32_X2APIC_IRR_159_128 2084 /* Interrupt request 159:128 */N#define X86_MSR$_IA32_X2APIC_IRR_191_160 2085 /* Interrupt request 191:160 */N#defin{[e X86_MSR$_IA32_X2APIC_IRR_223_192 2086 /* Interrupt request 223:192 */N#define X86_MSR$_IA32_X2APIC_IRR_255_224 2087 /* Interrupt request 255:224 */N#define X86_MSR$_IA32_X2APIC_ERROR_STATUS 2088 /* Error status */N#define X86_MSR$_IA32_X2APIC_ICR 2096 /* Interrupt command */N#define X86_MSR$_IA32_X2APIC_LVT_TIMER 2098 /* LVT timer */N#define X86_MSR$_IA32_X2APIC_LVT_THERMAL 2099 /* LVT thermal sensor */N#define X86_MSR$_IA32_X2APIC_LVT|[_PERFMON 2100 /* LVT performance monitoring */N#define X86_MSR$_IA32_X2APIC_LVT_LINT0 2101 /* LVT LINT0 */N#define X86_MSR$_IA32_X2APIC_LVT_LINT1 2102 /* LVT LINT1 */N#define X86_MSR$_IA32_X2APIC_LVT_ERROR 2103 /* LVT Error */N#define X86_MSR$_IA32_X2APIC_LVT_INIT_COUN 2104 /* Initial timer count */N#define X86_MSR$_IA32_X2APIC_LVT_CUR_COUNT 2105 /* Current timer count */R#define X86_MSR$_IA32_X2APIC_LVT_DIV_CFG 2110 /* Divide co }[nfiguration for timer */N#define X86_MSR$_IA32_X2APIC_LVT_SELF_IPI 2111 /* Self IPI */N/* Selected register offsets in xAPIC mode. */#define X86_XAPIC$_APICID 32#define X86_XAPIC$_VERSION 48$#define X86_XAPIC$_TASK_PRIORITY 128#define X86_XAPIC$_EOI 176#define X86_XAPIC$_ICR_LO 768#define X86_XAPIC$_ICR_HI 784 #define X86_XAPIC$_LVT_TIMER 800N/* Machine-Specific Registers: */N/* In the regi ~[ster defintions, different fields can have different */N/* accessibility attributes. */E/* R/W field can be both read and written */D/* RO field can be read but not written */G/* R/WC0 field can be read, writing a zero to it clears the field */#define EFER$M_SCE 0x1#define EFER$M_RES1_7 0xFE#define EFER$M_LME 0x100#define EFER$M_RES9 0x200#define EFER$M_LMA 0x400#define EFER [$M_NXE 0x800*#define EFER$M_RES12_63 0xFFFFFFFFFFFFF000 typedef struct _ia32_efer { __union {N unsigned __int64 efer$q_quadword; /* Entire quad register */ __struct {G unsigned efer$v_sce : 1; /* SYSCALL Enable (R/W) [0] */> unsigned efer$v_res1_7 : 7; /* Reserved [1-7] */J unsigned efer$v_lme : 1; /* IA-32e Mode Enable (R/W) [8] */< unsigned efer$v_res9 : 1; /* Reserved [9] */I unsigned [ efer$v_lma : 1; /* IA-32e Mode Active (R) [10] */S unsigned efer$v_nxe : 1; /* Execute Disable Bit Enable (R/W) [11] */, unsigned efer$v_res12_63_1 : 32;D unsigned efer$v_res12_63_2 : 20; /* Reserved [12-63] */ } efer$r_efer_bits;" } efer$r_ia32_efer_ovrlay; } IA32_EFER; #if !defined(__VAXC)?#define efer$q_quadword efer$r_ia32_efer_ovrlay.efer$q_quadwordF#define efer$v_sce efer$r_ia32_efer_ovrlay.efer$r_efer_bits.efer$v_s [ceF#define efer$v_lme efer$r_ia32_efer_ovrlay.efer$r_efer_bits.efer$v_lmeH#define efer$v_res9 efer$r_ia32_efer_ovrlay.efer$r_efer_bits.efer$v_res9F#define efer$v_lma efer$r_ia32_efer_ovrlay.efer$r_efer_bits.efer$v_lmaF#define efer$v_nxe efer$r_ia32_efer_ovrlay.efer$r_efer_bits.efer$v_nxe"#endif /* #if !defined(__VAXC) */ '#define MTRRCAP$M_FIXED_SUPPORTED 0x100#define MTRRCAP$M_RES9 0x200#define MTRRCAP$M_WC 0x400#define MTRRCAP$M_SMRR 0x800-#define MTRRCAP$M_RES12_63 0xFFFFFFFFFFFFF [000 typedef struct _ia32_mtrrcap { __union {N unsigned __int64 mtrrcap$q_quadword; /* The entire quadword */ __struct {N unsigned char mtrrcap$b_vcnt; /* Number of variable MTRRs [0-7] */W unsigned mtrrcap$v_fixed_supported : 1; /* Fixed MTRRs are supported [8] */A unsigned mtrrcap$v_res9 : 1; /* Reserved bit [9] */K unsigned mtrrcap$v_wc : 1; /* WC memory type supported [10] */I unsigned mtrrcap$v[_smrr : 1; /* SMRR MTRRs supported [11] */#if defined(__VAXC)/ unsigned mtrrcap$v_res12_63_1 : 32;/ unsigned mtrrcap$v_res12_63_2 : 20;#elseR unsigned __int64 mtrrcap$v_res12_63 : 52; /* Reserved bits [12-63] */#endif! } mtrrcap$r_cap_bits;$ } mtrrcap$r_mtrrcap_overlay; } IA32_MTRRCAP; #if !defined(__VAXC)G#define mtrrcap$q_quadword mtrrcap$r_mtrrcap_overlay.mtrrcap$q_quadwordR#define mtrrcap$b_vcnt mtrrcap$r_mtrrcap_o[verlay.mtrrcap$r_cap_bits.mtrrcap$b_vcnth#define mtrrcap$v_fixed_supported mtrrcap$r_mtrrcap_overlay.mtrrcap$r_cap_bits.mtrrcap$v_fixed_supportedR#define mtrrcap$v_res9 mtrrcap$r_mtrrcap_overlay.mtrrcap$r_cap_bits.mtrrcap$v_res9N#define mtrrcap$v_wc mtrrcap$r_mtrrcap_overlay.mtrrcap$r_cap_bits.mtrrcap$v_wcR#define mtrrcap$v_smrr mtrrcap$r_mtrrcap_overlay.mtrrcap$r_cap_bits.mtrrcap$v_smrrZ#define mtrrcap$v_res12_63 mtrrcap$r_mtrrcap_overlay.mtrrcap$r_cap_bits.mtrrcap$v_res12_63"#endif /* #if !de [fined(__VAXC) */ N/* Memory type codes, as specified in IA32_PAT or the MTRRs */N#define IA32_MEMORY_TYPE$C_UC 0 /* Strong Uncacheable */N#define IA32_MEMORY_TYPE$C_WC 1 /* Write Combining */N#define IA32_MEMORY_TYPE$C_RES2 2 /* Reserved */N#define IA32_MEMORY_TYPE$C_RES3 3 /* Reserved */N#define IA32_MEMORY_TYPE$C_WT 4 /* Write Through */N#def[ine IA32_MEMORY_TYPE$C_WP 5 /* Write Protected */N#define IA32_MEMORY_TYPE$C_WB 6 /* Write Back */N#define IA32_MEMORY_TYPE$C_UCMINUS 7 /* Uncached */N/* This type can only be encoded */N/* in IA32_PAT, not the MTRRs */N/* types 8 through 255 are reserved as well */ !typedef struct _ia32_fixed [_mtrr { __union {N unsigned __int64 mtrr_fixed$q_quadword; /* The entire quadword */_ unsigned char mtrr_fixed$b_fixed_type [8]; /* 8 type fields packed into the register */* } mtrr_fixed$r_mtrr_fixed_overlay; } IA32_FIXED_MTRR; #if !defined(__VAXC)S#define mtrr_fixed$q_quadword mtrr_fixed$r_mtrr_fixed_overlay.mtrr_fixed$q_quadwordW#define mtrr_fixed$b_fixed_type mtrr_fixed$r_mtrr_fixed_overlay.mtrr_fixed$b_fixed_type"#endif /* #if !defined(__VAXC) [*/ N/* A variable MTRR range applies to a PFN if: */I/* (1) the valid bit is set for the pair in the PHYSMASK register, and */I/* (2) the PFN is greater than or equal to PHYSBASE */I/* (3) (PFN .and. PHYSMASK) = (PHYSBASE .and. PHYSMASK) */N/* */O/* Note that there are various rules to handle cases where mulitple variable */N/* ranges apply and/or where [ both a variable range and a fixed range apply. */N/* See the x86 architecture for details. */%#define MTRR_PHYSBASE$M_RES8_11 0xF000#define MTRR_PHYSBASE$M_PHYSBASE 0xFFFFFFFFFF0003#define MTRR_PHYSBASE$M_RES52_63 0xFFF0000000000000 $typedef struct _ia32_mtrr_physbase { __union {N unsigned __int64 mtrr_physbase$q_quadword; /* The entire quadword */ __struct {V unsigned char mtrr_physbase$b_type; /* Memory type for thi [s range [0-7] */M unsigned mtrr_physbase$v_res8_11 : 4; /* Reserved bits [8-11] */#if defined(__VAXC)5 unsigned mtrr_physbase$v_physbase_1 : 32;4 unsigned mtrr_physbase$v_physbase_2 : 8;#elseT unsigned __int64 mtrr_physbase$v_physbase : 40; /* Base PFN [12-51] */#endifP unsigned mtrr_physbase$v_res52_63 : 12; /* Reserved bits [52-63] */, } mtrr_physbase$r_physbase_bits;- } mtrr_physbase$r_mtrr_physbase_over;[ } IA32_MTRR_PHYSBASE; #if !defined(__VAXC)\#define mtrr_physbase$q_quadword mtrr_physbase$r_mtrr_physbase_over.mtrr_physbase$q_quadwordr#define mtrr_physbase$b_type mtrr_physbase$r_mtrr_physbase_over.mtrr_physbase$r_physbase_bits.mtrr_physbase$b_typex#define mtrr_physbase$v_res8_11 mtrr_physbase$r_mtrr_physbase_over.mtrr_physbase$r_physbase_bits.mtrr_physbase$v_res8_11z#define mtrr_physbase$v_physbase mtrr_physbase$r_mtrr_physbase_over.mtrr_physbase$r_physbase_bits.mtrr_physbase$v_phys [basez#define mtrr_physbase$v_res52_63 mtrr_physbase$r_mtrr_physbase_over.mtrr_physbase$r_physbase_bits.mtrr_physbase$v_res52_63"#endif /* #if !defined(__VAXC) */ %#define MTRR_PHYSMASK$M_RES0_10 0x7FF##define MTRR_PHYSMASK$M_VALID 0x8000#define MTRR_PHYSMASK$M_PHYSMASK 0xFFFFFFFFFF0003#define MTRR_PHYSMASK$M_RES52_63 0xFFF0000000000000 $typedef struct _ia32_mtrr_physmask { __union {N unsigned __int64 mtrr_physmask$q_quadword; /* The entire quadword */ __struct [ {N unsigned mtrr_physmask$v_res0_10 : 11; /* Reserved bits [0-10] */V unsigned mtrr_physmask$v_valid : 1; /* Enables this variable range [11] */#if defined(__VAXC)5 unsigned mtrr_physmask$v_physmask_1 : 32;4 unsigned mtrr_physmask$v_physmask_2 : 8;#elseY unsigned __int64 mtrr_physmask$v_physmask : 40; /* PFN range mask [12-51] */#endifP unsigned mtrr_physmask$v_res52_63 : 12; /* Reserved bits [52-63] */, [ } mtrr_physmask$r_physmask_bits;- } mtrr_physmask$r_mtrr_physmask_over; } IA32_MTRR_PHYSMASK; #if !defined(__VAXC)\#define mtrr_physmask$q_quadword mtrr_physmask$r_mtrr_physmask_over.mtrr_physmask$q_quadwordx#define mtrr_physmask$v_res0_10 mtrr_physmask$r_mtrr_physmask_over.mtrr_physmask$r_physmask_bits.mtrr_physmask$v_res0_10t#define mtrr_physmask$v_valid mtrr_physmask$r_mtrr_physmask_over.mtrr_physmask$r_physmask_bits.mtrr_physmask$v_validz#define mtrr_physmask$v_physmask m [trr_physmask$r_mtrr_physmask_over.mtrr_physmask$r_physmask_bits.mtrr_physmask$v_physmaskz#define mtrr_physmask$v_res52_63 mtrr_physmask$r_mtrr_physmask_over.mtrr_physmask$r_physmask_bits.mtrr_physmask$v_res52_63"#endif /* #if !defined(__VAXC) */ $#define MTRR_DEF_TYPE$M_RES8_9 0x3000#define MTRR_DEF_TYPE$M_FIXED_MTRRS_ENABLE 0x400)#define MTRR_DEF_TYPE$M_MTRR_ENABLE 0x8003#define MTRR_DEF_TYPE$M_RES12_63 0xFFFFFFFFFFFFF000 $typedef struct _ia32_mtrr_def_type { __union {N [unsigned __int64 mtrr_def_type$q_quadword; /* The entire quadword */ __struct {e unsigned char mtrr_def_type$b_dflt_memory_type; /* Memory type if no other MTRR [0-7] */N/* pertains */L unsigned mtrr_def_type$v_res8_9 : 2; /* Reserved bits [8-9] */h unsigned mtrr_def_type$v_fixed_mtrrs_enable : 1; /* Enable bit for fixed-range MTRRs [10] */Z unsigned mtrr_def_type$v_mtrr_en [able : 1; /* Enable bit for all MTRRs [11] */#if defined(__VAXC)5 unsigned mtrr_def_type$v_res12_63_1 : 32;5 unsigned mtrr_def_type$v_res12_63_2 : 20;#elseY unsigned __int64 mtrr_def_type$v_res12_63 : 52; /* Reserved bits [12-63] */#endif+ } mtrr_def_type$r_deftype_bits;- } mtrr_def_type$r_mtrr_deftype_overl; } IA32_MTRR_DEF_TYPE; #if !defined(__VAXC)\#define mtrr_def_type$q_quadword mtrr_def_type$r_mtrr_deftype_overl.[mtrr_def_type$q_quadword#define mtrr_def_type$b_dflt_memory_type mtrr_def_type$r_mtrr_deftype_overl.mtrr_def_type$r_deftype_bits.mtrr_def_type$b_dflt_memor\y_typeu#define mtrr_def_type$v_res8_9 mtrr_def_type$r_mtrr_deftype_overl.mtrr_def_type$r_deftype_bits.mtrr_def_type$v_res8_9#define mtrr_def_type$v_fixed_mtrrs_enable mtrr_def_type$r_mtrr_deftype_overl.mtrr_def_type$r_deftype_bits.mtrr_def_type$v_fixed_mt\ rrs_enable#define mtrr_def_type$v_mtrr_enable mtrr_def_type$r_mtrr_deftype_overl.m [trr_def_type$r_deftype_bits.mtrr_def_type$v_mtrr_enabley#define mtrr_def_type$v_res12_63 mtrr_def_type$r_mtrr_deftype_overl.mtrr_def_type$r_deftype_bits.mtrr_def_type$v_res12_63"#endif /* #if !defined(__VAXC) */  typedef struct _ia32_pat { __union {N unsigned __int64 ia32_pat$q_quadword; /* The entire quadword */N unsigned char ia32_pat$b_pa [8]; /* Page attribute */N/* High 5 bits are reserved and MBZ [*/& } ia32_pat$r_ia32_pat_overlay; } IA32_PAT; #if !defined(__VAXC)K#define ia32_pat$q_quadword ia32_pat$r_ia32_pat_overlay.ia32_pat$q_quadword?#define ia32_pat$b_pa ia32_pat$r_ia32_pat_overlay.ia32_pat$b_pa"#endif /* #if !defined(__VAXC) */  typedef struct _ia32_star {? int star$l_reserved0_31; /* reserved [0-31] */D unsigned short int star$w_ring0_cs; /* SYSCALL CS/SS [32-47] */D unsigned short int star$w_ring3_cs; /* SYSRET CS/SS [48-63[] */ } IA32_STAR;-#define MISC_ENABLE$M_FAST_STRINGS_ENABLE 0x1 #define MISC_ENABLE$M_RES1_2 0x6-#define MISC_ENABLE$M_AUTO_THERMAL_ENABLE 0x8!#define MISC_ENABLE$M_RES4_6 0x70-#define MISC_ENABLE$M_PERF_MON_AVAILABLE 0x80##define MISC_ENABLE$M_RES8_10 0x7000#define MISC_ENABLE$M_BRANCH_TRACE_STORE_U 0x800!#define MISC_ENABLE$M_PEBS 0x1000%#define MISC_ENABLE$M_RES13_15 0xE0002#define MISC_ENABLE$M_ENH_SPEEDSTEP_ENABLE 0x10000##define MISC_ENABLE$M_RES17 0x200000#define MISC_E [NABLE$M_ENABLE_MONITOR_FSM 0x40000'#define MISC_ENABLE$M_RES19_21 0x3800001#define MISC_ENABLE$M_LIMIT_CPUID_MAXVAL 0x4000003#define MISC_ENABLE$M_XTPR_MESSAGE_DISABLE 0x800000*#define MISC_ENABLE$M_RES24_33 0x3FF0000000#define MISC_ENABLE$M_XD_BIT_DISABLE 0x4000000001#define MISC_ENABLE$M_RES35_63 0xFFFFFFF800000000 Ntypedef struct _misc_enable { /* R/W register */ __union {N unsigned __int64 misc_enable$q_quadword; /* The entire quadword [*/ __struct {N unsigned misc_enable$v_fast_strings_enable : 1; /* */N unsigned misc_enable$v_res1_2 : 2; /* Reserved bits [1-2] */W unsigned misc_enable$v_auto_thermal_enable : 1; /* Automatic Thermal [3] */N/* Control Circuit */N/* Enable */N unsigned misc_enable$v_res4_6 : 3; /* Reserved bits [4-6] [ */[ unsigned misc_enable$v_perf_mon_available : 1; /* Performance Monitoring [7] */N/* Available/Enable */J unsigned misc_enable$v_res8_10 : 3; /* Reserved bits [8-10] */\ unsigned misc_enable$v_branch_trace_store_u : 1; /* Branch Trace Storage [11] */N/* Unavailable */N unsigned misc_enable$v_pebs : 1; /* Processor Event Based [1[2] */N/* Sampling Unavailable */L unsigned misc_enable$v_res13_15 : 3; /* Reserved bits [13-15] */` unsigned misc_enable$v_enh_speedstep_enable : 1; /* Enhanced Intel SpeedStep [16] */N/* Technology Enable (R/W) */F unsigned misc_enable$v_res17 : 1; /* Reserved bit [17] */X unsigned misc_enable$v_enable_monitor_fsm : 1; /* Enable Monitor FSM [18] */L[ unsigned misc_enable$v_res19_21 : 3; /* Reserved bits [19-21] */X unsigned misc_enable$v_limit_cpuid_maxval : 1; /* Limit CPUID Maxval [22] */\ unsigned misc_enable$v_xtpr_message_disable : 1; /* xTPR Message Disable [23] */M unsigned misc_enable$v_res24_33 : 10; /* Reserved bits [24-33] */P unsigned misc_enable$v_xd_bit_disable : 1; /* XD Bit Disable [34] */M unsigned misc_enable$v_res35_63 : 29; /* Reserved bits [35-63] */& [ } misc_enable$r_misc_bits;, } misc_enable$r_misc_enable_overlay; } MISC_ENABLE; #if !defined(__VAXC)W#define misc_enable$q_quadword misc_enable$r_misc_enable_overlay.misc_enable$q_quadword#define misc_enable$v_fast_strings_enable misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_fast_strings_enab\lek#define misc_enable$v_res1_2 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res1_2#define misc_enable$v_auto_thermal_ena[ble misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_auto_thermal_enab\lek#define misc_enable$v_res4_6 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res4_6#define misc_enable$v_perf_mon_available misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_perf_mon_availablem#define misc_enable$v_res8_10 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res8_10#define misc_enable$v_branch_trace_store_u misc_en[able$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_branch_trace_sto\re_ug#define misc_enable$v_pebs misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_pebso#define misc_enable$v_res13_15 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res13_15#define misc_enable$v_enh_speedstep_enable misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_enh_speedstep_en\ablei#define misc_enable$v_res17 misc_enable$r_misc_enable_ov[erlay.misc_enable$r_misc_bits.misc_enable$v_res17#define misc_enable$v_enable_monitor_fsm misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_enable_monitor_fsmo#define misc_enable$v_res19_21 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res19_21#define misc_enable$v_limit_cpuid_maxval misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_limit_cpuid_maxval#define misc_enable$v_xtpr_message_disable misc_enable$r_misc_enable_ove [rlay.misc_enable$r_misc_bits.misc_enable$v_xtpr_message_dis\ableo#define misc_enable$v_res24_33 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res24_33{#define misc_enable$v_xd_bit_disable misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_xd_bit_disableo#define misc_enable$v_res35_63 misc_enable$r_misc_enable_overlay.misc_enable$r_misc_bits.misc_enable$v_res35_63"#endif /* #if !defined(__VAXC) */ #define ARCH_CAP$M_RDCL_NO 0x1#define ARCH [_CAP$M_IBRS_ALL 0x2#define ARCH_CAP$M_RSBA 0x4)#define ARCH_CAP$M_SKIP_L1DFL_VMENTRY 0x8#define ARCH_CAP$M_SSB_NO 0x10#define ARCH_CAP$M_MDS_NO 0x20-#define ARCH_CAP$M_RES6_63 0xFFFFFFFFFFFFFFC0 typedef struct _arch_cap { __union {N unsigned __int64 arch_cap$q_quadword; /* Entire quadword */ __struct {a unsigned arch_cap$v_rdcl_no : 1; /* Not susceptible to Rogue Data Cache Load [0] */a unsigned arch_cap$v_ibrs_all : 1; /*[ Indirect Branch Restriction Speculation [1] */F unsigned arch_cap$v_rsba : 1; /* RSB Alternate [2] */m unsigned arch_cap$v_skip_l1dfl_vmentry : 1; /* Hypervisor need not flush L1D on VM entry [3] */c unsigned arch_cap$v_ssb_no : 1; /* Not susceptible to Speculative Store Bypass [4] */j unsigned arch_cap$v_mds_no : 1; /* Not susceptible to Microarchitectural Data Sampling [5] */#if defined(__VAXC)/ unsigned arch_cap$v_res6_6 [3_1 : 32;/ unsigned arch_cap$v_res6_63_2 : 26;#elseY unsigned __int64 arch_cap$v_res6_63 : 58; /* Reserved bits [6-63] */#endif# } arch_cap$r_arch_bits;& } arch_cap$r_arch_cap_overlay; } ARCH_CAP; #if !defined(__VAXC)K#define arch_cap$q_quadword arch_cap$r_arch_cap_overlay.arch_cap$q_quadword^#define arch_cap$v_rdcl_no arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_rdcl_no`#define arch_cap$v_ibrs_all arch_cap$r_a[rch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_ibrs_allX#define arch_cap$v_rsba arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_rsbat#define arch_cap$v_skip_l1dfl_vmentry arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_skip_l1dfl_vmentry\#define arch_cap$v_ssb_no arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_ssb_no\#define arch_cap$v_mds_no arch_cap$r_arch_cap_overlay.arch_cap$r_arch_bits.arch_cap$v_mds_no^#define arch_cap$v_res6_63 arch_cap$r_arch_cap_overl[ay.arch_cap$r_arch_bits.arch_cap$v_res6_63"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __cplusplus }#endif#pragma __standard #endif /* __X86MSRDEF_LOADED */ ww[UM/*****************************************************************[**********/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** [ **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written permission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** [ **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:19 by OpenVMS SDL V3.7 */F/* Source: 09-AUG-1995 15:12:53 $1$DGA8345:[LIB_H.SRC]XIPDEF.SDL;1 *//******************************************************************************************************************* [*************//*** MODULE $XIPDEF ***/#ifndef __XIPDEF_LOADED#define __XIPDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma __required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers[ */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef __union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ [ */N/* XIP - Extended IRP */N/* */N/*- */  Q#include /* Define the IRP type; XIP contains an embedded IRP type */#define XIP_M_IOSA 0x80000000  9#ifdef __cplusplus /* Define structure prototypes */ struct _rde; #endif /* #ifdef __cplusplus */ c [#if !defined(__NOBASEALIGN_SUPPORT) && !defined(__cplusplus) /* If using pre DECC V4.0 or C++ */'#pragma __nomember_alignment __quadword#else#pragma __nomember_alignment#endiftypedef struct _xip {#pragma __nomember_alignmentN IRP xip_r_embedded_irp; /* Starts with an IRP */R unsigned int xip_l_scancnt; /* Count - 1 of pages remaining to scan */N unsigned int xip_l_direc; /* +- page size */R#ifdef __INITIAL_P [OINTER_SIZE /* Defined whenever ptr size pragmas supported */Z#pragma __required_pointer_size __long /* And set ptr size default to 64-bit pointers */N void *xip_pq_startva; /* Starting VA to scan */#else! unsigned __int64 xip_pq_startva;#endif __union {N unsigned int xip_l_updflg; /* Section update flags */ __struct {+ unsigned xip_v_fill_flags : 31;N unsigned xip_v_iosa : 1; /* IRP conta [ins pointer to IOSA */ } xip_r_flags_bits; } xip_r_flags_overlay;V unsigned int xip_l_access_mode; /* Maximized access mode for page ownership */R#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endifQ struct _rde *xip_ps_rde; /* RDE address associated with STARTVA */ char xip_b_fill_0_ [4]; } XIP; #if !def [ined(__VAXC)5#define xip_l_updflg xip_r_flags_overlay.xip_l_updflgB#define xip_v_iosa xip_r_flags_overlay.xip_r_flags_bits.xip_v_iosa"#endif /* #if !defined(__VAXC) */ N#define XIP_C_LENGTH 888 /* LENGTH OF STRUCTURE */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef __c[plusplus }#endif#pragma __standard #endif /* __XIPDEF_LOADED */ wwh[UM/***************************************************************************/M/** **/M/** HPE CONFIDENTIAL. This software is confidential proprietary software **/M/** licensed by Hewlett-Packard Enterprise Development, LP, and is not **/M/** authorized to be used, duplicated OR disclosed to anyone without the **/tZ~VSLDEF|Z.WBMDEFZFWCBDEFZWQHDEFZPWSLDEF [lX86HWDEFk[X X86MSRDEFX86_CPUID_INFO[XIPDEF[^XMIDEF YMF262_REG[M/** prior written permission of HPE. **/M/** 2024 Copyright Hewlett-Packard Enterprise Development, LP **/M/** **/M/** VMS SOFTWARE, INC. CONFIDENTIAL. This software is confidential **/M/** proprietary software licensed by VMS Software, Inc., and is not **/M/** authorized to be used, duplicated or disclosed to anyone without **/M/** the prior written pe[rmission of VMS Software, Inc. **/M/** 2024 Copyright VMS Software, Inc. **/M/** **/M/***************************************************************************//********************************************************************************************************************************/=/* Created: 7-Oct-2024 15:22:34 by OpenVMS SDL V3.7 */F/* Source: 26 [-MAY-1993 10:46:30 $1$DGA8345:[LIB_H.SRC]XMIDEF.SDL;1 *//********************************************************************************************************************************//*** MODULE $XMIDEF ***/#ifndef __XMIDEF_LOADED#define __XMIDEF_LOADED 1 G#pragma __nostandard /* This file uses non-ANSI-Standard features */!#pragma __member_alignment __save#pragma __nomember_alignmentR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */\#pragma [__required_pointer_size __save /* Save the previously-defined required ptr size */[#pragma __required_pointer_size __short /* And set ptr size default to 32-bit pointers */#endif #ifdef __cplusplus extern "C" {#define __unknown_params ...#define __optional_params ...#else#define __unknown_params#define __optional_params ...#endif #ifndef __struct#if !defined(__VAXC)#define __struct struct#else#define __struct variant_struct#endif#endif #ifndef [__union#if !defined(__VAXC)#define __union union#else#define __union variant_union#endif#endif N/*+ */N/* XMI Required Registers */N/*- */ #define XMI$C_IO_CLASS 32#define XMI$C_MEMORY_CLASS 64#define XMI$C_CPU_CLASS 128N/* [ */#define XMI$C_READ 1#define XMI$C_IREAD 2#define XMI$C_UWMASK 6#define XMI$C_WMASK 7#define XMI$C_INTR 8#define XMI$C_IDENT 9#define XMI$C_IVINTR 15N/* XMI-2 additional commands */#define XMI$C_OREAD 3#define XMI$C_DWMASK 4#define XMI$C_TBDATA 11#define XMI$M_EMP 0x2#define XMI$M_DXTO 0x4#define XMI$M_EHWW 0x8#define XMI$M_FCMD 0xF#define XMI$M_FCID 0x3F0#define XMI$M_STF 0x400#define XMI$M_[ETF 0x800#define XMI$M_NSES 0x1000#define XMI$M_TTO 0x2000#define XMI$M_TE 0x4000#define XMI$M_CNAK 0x8000#define XMI$M_RER 0x10000#define XMI$M_RSE 0x20000#define XMI$M_NRR 0x40000#define XMI$M_CRD 0x80000#define XMI$M_WDNAK 0x100000#define XMI$M_RIDNAK 0x200000#define XMI$M_WSE 0x400000#define XMI$M_PE 0x800000#define XMI$M_IPE 0x1000000#define XMI$M_WEI 0x2000000#define XMI$M_XFAULT 0x4000000#define XMI$M_CC 0x8000000#define XMI$M_XBAD 0x10000000#def[ine XMI$M_NHALT 0x20000000#define XMI$M_NRESET 0x40000000#define XMI$M_ES 0x80000000##define XMI$M_SLEEP_MODE 0x40000000$#define XMI$M_FAEM_ENABLE 0x80000000#define XMI$M_LOCMOD 0x3#define XMI$M_XBADD 0x4#define XMI$M_CRDID 0x10000#define XMI$M_CCID 0x20000#define XMI$M_SEO 0x1#define XMI$M_OLR 0x2#define XMI$M_URR 0x4N#define XMI$S_XMIDEF 1592 /* Old size name - synonym */ typedef struct _xmi { __union {N unsigned int xmi$l_xdev; [ /* XMI Device register */ __struct { __union {N unsigned short int xmi$w_dtype; /* Device type */ __struct {N unsigned char xmi$b_dev_id; /* Device ID */N unsigned char xmi$b_class; /* Device class */) } xmi$r_dtype_fields;& } xmi$r_dtype_overlay;N unsigned short int xmi$w_drev; /* Device Revis [ion */ } xmi$r_xdev_fields; } xmi$r_xdev_overlay;N/* XMI commands */N/* */ __union {N unsigned int xmi$l_xbe; /* XMI Bus Error register */N __struct { /* Post V1.4 */N unsigned xmi$$_fill_1 : 1; /* Reserved bit */N [ unsigned xmi$v_emp : 1; /* Enable More Protocol */N unsigned xmi$v_dxto : 1; /* Disable XMI Timeout */N unsigned xmi$v_ehww : 1; /* Enable HexaWord Write */' unsigned xmi$v_fill_0_ : 4;# } xmi$r_fcmd_redefined; __struct {N unsigned xmi$v_fcmd : 4; /* Failing Command (Pre V1.4) */N unsigned xmi$v_fcid : 6; /* Failing Commander ID */N [ unsigned xmi$v_stf : 1; /* Self-test fail */N unsigned xmi$v_etf : 1; /* Extended Test fail */N unsigned xmi$v_nses : 1; /* Node-specific Err. Summary */N unsigned xmi$v_tto : 1; /* Transaction timeout */N unsigned xmi$v_te : 1; /* Transmit error */N unsigned xmi$v_cnak : 1; /* Command NoAck */N unsigned xmi$v_rer :[ 1; /* Read Error Response */N unsigned xmi$v_rse : 1; /* Read Sequence Error */N unsigned xmi$v_nrr : 1; /* No Read Response */N unsigned xmi$v_crd : 1; /* Corrected Read Data */N unsigned xmi$v_wdnak : 1; /* Write Data NoACk */N unsigned xmi$v_ridnak : 1; /* Read/IDENT Data NoAck */N unsigned xmi$v_wse : 1; /* Write Sequence [Error */N unsigned xmi$v_pe : 1; /* Parity Error */N unsigned xmi$v_ipe : 1; /* Inconsistent Parity Error */N unsigned xmi$v_wei : 1; /* Write Error Interrupt */N unsigned xmi$v_xfault : 1; /* XMI Fault */N unsigned xmi$v_cc : 1; /* Corrected Confirmation */N unsigned xmi$v_xbad : 1; /* XMI Bad */N [ unsigned xmi$v_nhalt : 1; /* Node Halt */N unsigned xmi$v_nreset : 1; /* Node Reset */N unsigned xmi$v_es : 1; /* Error Summary */ } xmi$r_xbe_bits; } xmi$r_xbe_overlay; __union {U unsigned int xmi$l_xfad; /* XMI Failing Address (physical) register */U unsigned int xmi$l_xfadr0; /* XMI Failing Address (physical) register */ __struct [ {N unsigned xmi$v_fadr : 30; /* Failing Address */N unsigned xmi$v_fln : 2; /* Failing length */ } xmi$r_xfad_fields; } xmi$r_xfad_overlay;N __union { /* XJA's version of the XFAER */N/* register. This is identical */N/* to other node's XFAER except */N/* that for the XJA it is here [ */N/* at bb+C rather than at bb+2C. */Z unsigned int xmi$l_xja_xfadrb; /* XJA Failing Address register (physical) Ext. */N/* For the field definitions, use */N/* those defined below for XFAER. */N unsigned int xmi$l_xgpr; /* XMI General Purpose register */# } xmi$r_xja_xfadrb_overlay;N __unio [n { /* XJA's General Purpose Register. */N unsigned int xmi$l_xja_xgpr; /* XJA's General Purpose Register. */N unsigned int xmi$l_xcomm; /* XMI Communication register */! } xmi$r_xja_xgpr_overlay; __union {N unsigned int xmi$l_xja_xfaemctl; /* XJA's FAEM Control Register */ __struct {N unsigned xmi$v_xbi_window_mask : 16; /* XBI Window Space Mask */' unsigned xmi$$_fill_1 : 14;N [ unsigned xmi$v_sleep_mode : 1; /* Set Sleep Mode */N unsigned xmi$v_faem_enable : 1; /* Enable FAEM */( } xmi$r_xja_xfaemctl_fields;% } xmi$r_xja_xfaemctl_overlay;T __union { /* XJA's Add On Self Test Status Register */T unsigned int xmi$l_xja_aosts; /* XJA's Add On Self Test Status Register */" } xmi$r_xja_aosts_overlay; __union {N unsigned int xmi$l_xja_sernum; [/* XJA's Serial Number Register */ __struct {N unsigned xmi$v_serial_number : 17; /* Serial Number */N unsigned xmi$v_plant : 4; /* Manufacturing Plant. */N unsigned xmi$v_rev : 4; /* Revision Level. */N unsigned xmi$v_vari : 4; /* Variation. */& unsigned xmi$$_fill_1 : 3;& } xmi$r_xja_sernum_fields; __union {N unsigned int [ xmi$l_nscsr; /* XMI-1 Node specific CSR */N unsigned int xmi$l_nscsr0; /* XMI-2 Node specific CSR */! } xmi$r_nscr_overlay;# } xmi$r_xja_sernum_overlay;N int xmi$$_fill_3 [1]; /*RESERVED REGISTERS */ __union {N unsigned int xmi$l_xbcr; /* XMI-1 Bus control register */N unsigned int xmi$l_xbcr0; /* XMI-2 Bus control register */ __struct {N unsign [ed xmi$v_locmod : 2; /* Lockout mode bits */N unsigned xmi$v_xbadd : 1; /* XMI Bad Drive */' unsigned xmi$v_fill_2 : 13;N unsigned xmi$v_crdid : 1; /* Corrected Read Int. disable */N unsigned xmi$v_ccid : 1; /* Corrected Conf. Int. disable */' unsigned xmi$v_fill_1_ : 6; } xmi$r_xbcr_fields; } xmi$r_xbcr_overlay; unsigned int xmi$l_fill_3; __union {[ [ unsigned int xmi$l_xfaer; /* XMI-1 Failing Address (physical) Ext register */[ unsigned int xmi$l_xfaer0; /* XMI-2 Failing Address (physical) Ext register */ __struct {N unsigned xmi$v_mask : 16; /* Failing Mask */U unsigned xmi$v_addrext : 10; /* Failing Address Extension bits [38:29] */N unsigned xmi$$_fill_3 : 2; /* Reserved bits */N unsigned xmi$v_fcmdx : 4; /* Failing Com [mand */! } xmi$r_xfaer_fields; } xmi$r_xfaer_overlay;N/* End of XMI-1 Register. The addition register only apply to XMI-2. */ unsigned int xmi$l_fill_4; __union {N unsigned int xmi$l_xbeer; /* XMI-1 Bus Error extension */N unsigned int xmi$l_xbeer0; /* XMI-2 Bus Error extension */ __struct {N unsigned xmi$v_seo : 1; /* Second Error Occured */N unsigned x [mi$v_olr : 1; /* Only LOC Response */N unsigned xmi$v_urr : 1; /* Unexpected Read Response */' unsigned xmi$v_fill_2_ : 5;! } xmi$r_xbeer_fields; } xmi$r_xbeer_overlay;% unsigned char xmi$b_fill_5 [460];N unsigned int xmi$l_xbe1; /* XMI-2 Bus Error register */T unsigned int xmi$l_xfad1; /* XMI-2 Failing Addr (physical) register */" unsigned int xmi$l_fill_6 [4];N unsigned int [ xmi$l_nscsr1; /* XMI-2 Node specific CSR */ unsigned int xmi$l_fill_7;N unsigned int xmi$l_xbcr1; /* XMI-2 Bus control register */ unsigned int xmi$l_fill_8;V unsigned int xmi$l_xfaer1; /* XMI-2 Failing addr. (physical) extension */ unsigned int xmi$l_fill_9;N unsigned int xmi$l_xbeer1; /* XMI-2 Bus Error extension */N/* */% unsigned char [xmi$b_fill_a [460];N unsigned int xmi$l_xbe2; /* XMI-2 Bus Error register */T unsigned int xmi$l_xfad2; /* XMI-2 Failing Addr (physical) register */" unsigned int xmi$l_fill_b [4];N unsigned int xmi$l_nscsr2; /* XMI-2 Node specific CSR */ unsigned int xmi$l_fill_c;N unsigned int xmi$l_xbcr2; /* XMI-2 Bus control register */ unsigned int xmi$l_fill_d;V unsigned int xmi$l_xfaer2; /* XMI-2 Failing a [ddr. (physical) extension */ unsigned int xmi$l_fill_e;N unsigned int xmi$l_xbeer2; /* XMI-2 Bus Error extension */N/* */% unsigned char xmi$b_fill_f [460];N unsigned int xmi$l_xbe3; /* XMI-2 Bus Error register */T unsigned int xmi$l_xfad3; /* XMI-2 Failing Addr (phsycial) register */# unsigned int xmi$l_fill_10 [4];N unsigned int xmi$l_nscsr3; [/* XMI-2 Node specific CSR */ unsigned int xmi$l_fill_11;N unsigned int xmi$l_xbcr3; /* XMI-2 Bus control register */ unsigned int xmi$l_fill_12;V unsigned int xmi$l_xfaer3; /* XMI-2 Failing addr. (physical) extension */ unsigned int xmi$l_fill_13;N unsigned int xmi$l_xbeer3; /* XMI-2 Bus Error extension */ } XMI; #if !defined(__VAXC)0#define xmi$l_xdev xmi$r_xdev_overlay.xmi$l_xdevX#define xmi$w_dtype xmi$r_xd[ev_overlay.xmi$r_xdev_fields.xmi$r_dtype_overlay.xmi$w_dtypem#define xmi$b_dev_id xmi$r_xdev_overlay.xmi$r_xdev_fields.xmi$r_dtype_overlay.xmi$r_dtype_fields.xmi$b_dev_idk#define xmi$b_class xmi$r_xdev_overlay.xmi$r_xdev_fields.xmi$r_dtype_overlay.xmi$r_dtype_fields.xmi$b_classB#define xmi$w_drev xmi$r_xdev_overlay.xmi$r_xdev_fields.xmi$w_drev-#define xmi$l_xbe xmi$r_xbe_overlay.xmi$l_xbeH#define xmi$$_fill_1 xmi$r_xbe_overlay.xmi$r_fcmd_redefined.xmi$$_fill_1B#define xmi$v_emp xmi$r_xbe_over [lay.xmi$r_fcmd_redefined.xmi$v_empD#define xmi$v_dxto xmi$r_xbe_overlay.xmi$r_fcmd_redefined.xmi$v_dxtoD#define xmi$v_ehww xmi$r_xbe_overlay.xmi$r_fcmd_redefined.xmi$v_ehww>#define xmi$v_fcmd xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_fcmd>#define xmi$v_fcid xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_fcid<#define xmi$v_stf xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_stf<#define xmi$v_etf xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_etf>#define xmi$v_nses xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_nses<#define xmi$v_ [tto xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_tto:#define xmi$v_te xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_te>#define xmi$v_cnak xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_cnak<#define xmi$v_rer xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_rer<#define xmi$v_rse xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_rse<#define xmi$v_nrr xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_nrr<#define xmi$v_crd xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_crd@#define xmi$v_wdnak xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_wdnakB#define xmi$v_ridnak [ xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_ridnak<#define xmi$v_wse xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_wse:#define xmi$v_pe xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_pe<#define xmi$v_ipe xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_ipe<#define xmi$v_wei xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_weiB#define xmi$v_xfault xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_xfault:#define xmi$v_cc xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_cc>#define xmi$v_xbad xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_xbad@#define xmi$v_nhalt [xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_nhaltB#define xmi$v_nreset xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_nreset:#define xmi$v_es xmi$r_xbe_overlay.xmi$r_xbe_bits.xmi$v_es0#define xmi$l_xfad xmi$r_xfad_overlay.xmi$l_xfad4#define xmi$l_xfadr0 xmi$r_xfad_overlay.xmi$l_xfadr0B#define xmi$v_fadr xmi$r_xfad_overlay.xmi$r_xfad_fields.xmi$v_fadr@#define xmi$v_fln xmi$r_xfad_overlay.xmi$r_xfad_fields.xmi$v_flnB#define xmi$l_xja_xfadrb xmi$r_xja_xfadrb_overlay.xmi$l_xja_xfadrb6#define xmi$l_xgpr xmi$r_x[ja_xfadrb_overlay.xmi$l_xgpr<#define xmi$l_xja_xgpr xmi$r_xja_xgpr_overlay.xmi$l_xja_xgpr6#define xmi$l_xcomm xmi$r_xja_xgpr_overlay.xmi$l_xcommH#define xmi$l_xja_xfaemctl xmi$r_xja_xfaemctl_overlay.xmi$l_xja_xfaemctlh#define xmi$v_xbi_window_mask xmi$r_xja_xfaemctl_overlay.xmi$r_xja_xfaemctl_fields.xmi$v_xbi_window_mask^#define xmi$v_sleep_mode xmi$r_xja_xfaemctl_overlay.xmi$r_xja_xfaemctl_fields.xmi$v_sleep_mode`#define xmi$v_faem_enable xmi$r_xja_xfaemctl_overlay.xmi$r_xja_xfaemctl_fields.xmi[$v_faem_enable?#define xmi$l_xja_aosts xmi$r_xja_aosts_overlay.xmi$l_xja_aostsB#define xmi$l_xja_sernum xmi$r_xja_sernum_overlay.xmi$l_xja_sernum`#define xmi$v_serial_number xmi$r_xja_sernum_overlay.xmi$r_xja_sernum_fields.xmi$v_serial_numberP#define xmi$v_plant xmi$r_xja_sernum_overlay.xmi$r_xja_sernum_fields.xmi$v_plantL#define xmi$v_rev xmi$r_xja_sernum_overlay.xmi$r_xja_sernum_fields.xmi$v_revN#define xmi$v_vari xmi$r_xja_sernum_overlay.xmi$r_xja_sernum_fields.xmi$v_variK#define xmi$l_nscs[r xmi$r_xja_sernum_overlay.xmi$r_nscr_overlay.xmi$l_nscsrM#define xmi$l_nscsr0 xmi$r_xja_sernum_overlay.xmi$r_nscr_overlay.xmi$l_nscsr00#define xmi$l_xbcr xmi$r_xbcr_overlay.xmi$l_xbcr2#define xmi$l_xbcr0 xmi$r_xbcr_overlay.xmi$l_xbcr0F#define xmi$v_locmod xmi$r_xbcr_overlay.xmi$r_xbcr_fields.xmi$v_locmodD#define xmi$v_xbadd xmi$r_xbcr_overlay.xmi$r_xbcr_fields.xmi$v_xbaddD#define xmi$v_crdid xmi$r_xbcr_overlay.xmi$r_xbcr_fields.xmi$v_crdidB#define xmi$v_ccid xmi$r_xbcr_overlay.xmi$r_xbcr_fie [lds.xmi$v_ccid3#define xmi$l_xfaer xmi$r_xfaer_overlay.xmi$l_xfaer5#define xmi$l_xfaer0 xmi$r_xfaer_overlay.xmi$l_xfaer0D#define xmi$v_mask xmi$r_xfaer_overlay.xmi$r_xfaer_fields.xmi$v_maskJ#define xmi$v_addrext xmi$r_xfaer_overlay.xmi$r_xfaer_fields.xmi$v_addrextH#define xmi$$_fill_3 xmi$r_xfaer_overlay.xmi$r_xfaer_fields.xmi$$_fill_3F#define xmi$v_fcmdx xmi$r_xfaer_overlay.xmi$r_xfaer_fields.xmi$v_fcmdx3#define xmi$l_xbeer xmi$r_xbeer_overlay.xmi$l_xbeer5#define xmi$l_xbeer0 xmi$r_xbeer_o [verlay.xmi$l_xbeer0B#define xmi$v_seo xmi$r_xbeer_overlay.xmi$r_xbeer_fields.xmi$v_seoB#define xmi$v_olr xmi$r_xbeer_overlay.xmi$r_xbeer_fields.xmi$v_olrB#define xmi$v_urr xmi$r_xbeer_overlay.xmi$r_xbeer_fields.xmi$v_urr"#endif /* #if !defined(__VAXC) */  $#pragma __member_alignment __restoreR#ifdef __INITIAL_POINTER_SIZE /* Defined whenever ptr size pragmas supported */b#pragma __required_pointer_size __restore /* Restore the previously-defined required ptr size */#endif#ifdef[ __cplusplus }#endif#pragma __standard #endif /* __XMIDEF_LOADED */ wwp[U/***********************************************************************************************************************************!! AAA_SYSTEM_CELLS.H!U! Created: 7-OCT-2024 15:21:28.63 by $1$DGA8345:[SYS.COM]MAKE_DATACELL_ALIAS.COM;1E! Source: 7-OCT-2024 15:21:28.43 $1$DGA8345:[SYS.OBJ]SYSLNK.TMP;1!**************************************************************[*********************************************************************/S#define smp$gq_configure_set SMP$GQ_CONFIGURE_SET S#define smp$gq_active_set SMP$GQ_ACTIVE_SET S#define smp$gq_override_set SMP$GQ_OVERRIDE_SET S#define smp$gq_potential_set SMP$GQ_POTENTIAL_SET S#define smp$gq_tested_set SMP$GQ_TESTED_SET S#def[ine smp$gq_present_set SMP$GQ_PRESENT_SET S#define smp$gq_powered_set SMP$GQ_POWERED_SET S#define smp$gq_autostart_set SMP$GQ_AUTOSTART_SET S#define smp$gq_deferred_set SMP$GQ_DEFERRED_SET S#define smp$gq_transition_set SMP$GQ_TRANSITION_SET S#define smp$gq_bug_done SMP$GQ_BUG_DONE [ S#define xdt$gq_benign_cpus XDT$GQ_BENIGN_CPUS S#define exe$gq_device_affinity EXE$GQ_DEVICE_AFFINITY S#define ioc$gq_interrupts IOC$GQ_INTERRUPTS S#define sch$gq_no_ktb_cpus SCH$GQ_NO_KTB_CPUS S#define smp$gq_sysptbr_ack_mask SMP$GQ_SYSPTBR_ACK_MASK S#define smp$gq_tbi_ack_mask SMP$GQ_TBI_ACK_MASK [ S#define smp$gq_tbi_ack_mask_mmg SMP$GQ_TBI_ACK_MASK_MMG S#define exe$gl_disable_dkdriver_logging EXE$GL_DISABLE_DKDRIVER_LOGGING S#define sch$aq_cpu_capabilities SCH$AQ_CPU_CAPABILITIES S#define ctl$gl_image_dump CTL$GL_IMAGE_DUMP S#define exe$gq_imgact_security EXE$GQ_IMGACT_SECURITY S#define exe$gpq_esi_table EXE$GPQ_ESI_T[ABLE S#define ctl$gq_process_pool_log CTL$GQ_PROCESS_POOL_LOG S#define ast$gq_debug AST$GQ_DEBUG S#define fil$aq_posix_root FIL$AQ_POSIX_ROOT S#define pio$aq_posix_root PIO$AQ_POSIX_ROOT S#define pio$aq_posix_cwd PIO$AQ_POSIX_CWD S#define exe$gl_shadow_psm_rdly EXE[$GL_SHADOW_PSM_RDLY S#define exe$gl_platf_spt_1 EXE$GL_PLATF_SPT_1 S#define exe$gl_platf_spt_2 EXE$GL_PLATF_SPT_2 S#define exe$gl_platf_spt_3 EXE$GL_PLATF_SPT_3 S#define exe$gl_platf_spt_4 EXE$GL_PLATF_SPT_4 S#define exe$gl_platf_spt_d1 EXE$GL_PLATF_SPT_D1 S#define exe$gl_platf_spt_d2 [ EXE$GL_PLATF_SPT_D2 S#define exe$gl_platf_spt_d3 EXE$GL_PLATF_SPT_D3 S#define exe$gl_platf_spt_d4 EXE$GL_PLATF_SPT_D4 S#define smp$gs_cbb_fastpath_set SMP$GS_CBB_FASTPATH_SET S#define smp$gq_available_port_cpus SMP$GQ_AVAILABLE_PORT_CPUS S#define lmf$gl_galaxy_lkid LMF$GL_GALAXY_LKID S#define lmf$gl_noncomp [ LMF$GL_NONCOMP S#define swis$gl_swis_log SWIS$GL_SWIS_LOG S#define iac$gq_proc_pool IAC$GQ_PROC_POOL S#define sys$gl_execstackpages SYS$GL_EXECSTACKPAGES S#define sys$gl_gb_cacheallmax SYS$GL_GB_CACHEALLMAX S#define sys$gl_gb_defpercent SYS$GL_GB_DEFPERCENT S#define sgn$gl_cpu[_threading SGN$GL_CPU_THREADING S#define sgn$gl_cpu_power_mgmt SGN$GL_CPU_POWER_MGMT S#define exe$gpq_fshwa EXE$GPQ_FSHWA S#define sgn$gl_cpu_power_thresh SGN$GL_CPU_POWER_THRESH S#define icap$gq_state ICAP$GQ_STATE S#define lck$gq_timeout_tqe LCK$GQ_TIMEOUT_TQE S#define [exe$gq_number_of_dbrs EXE$GQ_NUMBER_OF_DBRS S#define exe$gq_number_of_ibrs EXE$GQ_NUMBER_OF_IBRS S#define exe$gq_promote_p2_va EXE$GQ_PROMOTE_P2_VA S#define exe$gq_promote_p2_window EXE$GQ_PROMOTE_P2_WINDOW S#define exe$gl_pubvec_copy_sdata EXE$GL_PUBVEC_COPY_SDATA S#define exe$gl_pubvec_copy_sdata_end EXE$GL_PUBVEC_COPY_SDATA_END S[#define exe$gl_pubvec_copy_symvec EXE$GL_PUBVEC_COPY_SYMVEC S#define ldr$gl_pubvec_copy_ldrimg LDR$GL_PUBVEC_COPY_LDRIMG S#define ctl$gq_ssi_region_id CTL$GQ_SSI_REGION_ID S#define exe$gq_xqp_security EXE$GQ_XQP_SECURITY S#define ctl$gq_ssi_data CTL$GQ_SSI_DATA S#define clu$gw_lckrmwt CLU$GW_LCKRMWT [ S#define sch$gs_cbb_cothreads_idle_cpus SCH$GS_CBB_COTHREADS_IDLE_CPUS S#define sch$gq_cothreads_idle_cpus SCH$GQ_COTHREADS_IDLE_CPUS S#define sgn$gl_sas_naming SGN$GL_SAS_NAMING S#define iscsi$ar_infoblock ISCSI$AR_INFOBLOCK S#define imsem$gq_debug IMSEM$GQ_DEBUG S#define sch$gs_cbb_core_cap_cothd_cpus SCH$GS_CBB_CORE_CAP[_COTHD_CPUS S#define sch$gq_core_cap_cothd_cpus SCH$GQ_CORE_CAP_COTHD_CPUS S#define ioc$gl_mpdev_ppb_list IOC$GL_MPDEV_PPB_LIST #define exe$gq_abstim_tics EXE$GQ_ABSTIM_TICS /* Absolute time in 10ms ticks (synonym to EXE$GL_ABSTIM_TICS) */S#define pms$gq_align_kernel PMS$GQ_ALIGN_KERNEL S#define pms$gq_align_exec PMS$GQ_ALIGN_EX[EC S#define pms$gq_align_super PMS$GQ_ALIGN_SUPER S#define pms$gq_align_user PMS$GQ_ALIGN_USER S#define ctl$gq_get_vm_s CTL$GQ_GET_VM_S S#define ctl$gq_get_vm_64_s CTL$GQ_GET_VM_64_S S#define ctl$gq_get_vm_page_s CTL$GQ_GET_VM_PAGE_S S#define ctl$gq_get_vm_page_64_s CTL$G[Q_GET_VM_PAGE_64_S S#define ctl$gq_vm_malloc_s CTL$GQ_VM_MALLOC_S S#define ctl$gq_vm_malloc_64_s CTL$GQ_VM_MALLOC_64_S S#define ctl$gq_get_vm_e CTL$GQ_GET_VM_E S#define ctl$gq_get_vm_64_e CTL$GQ_GET_VM_64_E S#define ctl$gq_get_vm_page_e CTL$GQ_GET_VM_PAGE_E S#define ctl$gq_get_vm_page_64_e [ CTL$GQ_GET_VM_PAGE_64_E S#define ctl$gq_vm_malloc_e CTL$GQ_VM_MALLOC_E S#define ctl$gq_vm_malloc_64_e CTL$GQ_VM_MALLOC_64_E S#define efi$gl_cpu_thread_control EFI$GL_CPU_THREAD_CONTROL S#define smp$gq_calibrate SMP$GQ_CALIBRATE S#define ioc$gl_ssio_sync_intvl IOC$GL_SSIO_SYNC_INTVL S#define ctl$gq_get_vm_k [ CTL$GQ_GET_VM_K S#define ctl$gq_get_vm_64_k CTL$GQ_GET_VM_64_K S#define ctl$gq_get_vm_page_k CTL$GQ_GET_VM_PAGE_K S#define ctl$gq_get_vm_page_64_k CTL$GQ_GET_VM_PAGE_64_K S#define ctl$gq_vm_malloc_k CTL$GQ_VM_MALLOC_K S#define ctl$gq_vm_malloc_64_k CTL$GQ_VM_MALLOC_64_K S#define exe$gq_dst_f[lags EXE$GQ_DST_FLAGS S#define ipmi$gq_activate_status IPMI$GQ_ACTIVATE_STATUS S#define smp$gs_cbb_exclude_set SMP$GS_CBB_EXCLUDE_SET S#define smp$gq_exclude_set SMP$GQ_EXCLUDE_SET S#define sch$gs_soft_offld_bitmap SCH$GS_SOFT_OFFLD_BITMAP S#define sch$gs_hard_offld_bitmap SCH$GS_HARD_OFFLD_BITMAP S#define wp[$gq_debug WP$GQ_DEBUG S#define swis$gq_debug SWIS$GQ_DEBUG S#define exe$gl_gh_res_code_s2 EXE$GL_GH_RES_CODE_S2 S#define net$ar_mops0db NET$AR_MOPS0DB S#define mpw$gl_state MPW$GL_STATE S#define clu$gl_niscs_udp_port CLU$GL_NISCS_UDP_PORT S#d[efine sgn$gl_tcpip_load SGN$GL_TCPIP_LOAD S#define sgn$gl_gh_exec_data SGN$GL_GH_EXEC_DATA S#define sgn$gl_gh_exec_code SGN$GL_GH_EXEC_CODE S#define ctl$gl_imgdmp_data_p1 CTL$GL_IMGDMP_DATA_P1 S#define ctl$gq_imgdmp_data_p2 CTL$GQ_IMGDMP_DATA_P2 S#define clu$ar_ipci_data CLU$AR_IPCI_DATA [ S#define mmg$gl_mmg_throttle MMG$GL_MMG_THROTTLE S#define smp$gl_spinlock_array SMP$GL_SPINLOCK_ARRAY S#define mmg$gl_pkr_count MMG$GL_PKR_COUNT #define acpi$gq_root_object ACPI$GQ_ROOT_OBJECT /* Pointer to root of ACPI namespace */S#define exe$ar_paged_lal EXE$AR_PAGED_LAL [ S#define exe$gl_paged_lal_size EXE$GL_PAGED_LAL_SIZE S#define exe$gq_rad_ordering_arrays EXE$GQ_RAD_ORDERING_ARRAYS S#define pxml$gpq_database PXML$GPQ_DATABASE S#define sys$gl_rms_path_tmo SYS$GL_RMS_PATH_TMO S#define pio$gl_rms_path_tmo PIO$GL_RMS_PATH_TMO S#define exe$gq_prec_systime EXE$GQ_PREC_SYSTI[ME S#define exe$gq_prec_itm EXE$GQ_PREC_ITM S#define exe$gq_prec_checksum EXE$GQ_PREC_CHECKSUM S#define exe$gq_prec_spare1 EXE$GQ_PREC_SPARE1 S#define exe$gq_utc EXE$GQ_UTC S#define exe$gq_prec_ovflval EXE$GQ_PREC_OVFLVAL S#define exe$gq_prec_multiplier EXE$GQ_[PREC_MULTIPLIER S#define exe$gq_prec_itcbit EXE$GQ_PREC_ITCBIT S#define net$gq_rnic_vector NET$GQ_RNIC_VECTOR S#define exe$gl_power_mgmt_idle_cpu EXE$GL_POWER_MGMT_IDLE_CPU S#define exe$gl_power_threshold_idle_cpu EXE$GL_POWER_THRESHOLD_IDLE_CPU S#define exe$gq_power_state_os_control EXE$GQ_POWER_STATE_OS_CONTROL S#define exe$gq_power_state_current [ EXE$GQ_POWER_STATE_CURRENT S#define exe$gl_power_cpu_pstate EXE$GL_POWER_CPU_PSTATE S#define clu$gl_niscs_udp_pktsz CLU$GL_NISCS_UDP_PKTSZ S#define lck$gq_lckrq_pndq LCK$GQ_LCKRQ_PNDQ S#define exe$gq_abstim_100ns EXE$GQ_ABSTIM_100NS S#define exe$gt_hwname_expanded EXE$GT_HWNAME_EXPANDED S#define exe$gq_sysmd_data [ EXE$GQ_SYSMD_DATA S#define exe$gq_dump_kernel_data EXE$GQ_DUMP_KERNEL_DATA S#define exe$gl_sysmducb EXE$GL_SYSMDUCB S#define exe$gl_hwsysucb EXE$GL_HWSYSUCB S#define exe$gqp_hpet_counter_va EXE$GQP_HPET_COUNTER_VA S#define mmg$gq_syi_memory_map_64 MMG$GQ_SYI_MEMORY_MAP_64 S#define mmg$gq_phymem_[window_base_addr MMG$GQ_PHYMEM_WINDOW_BASE_ADDR S#define mmg$gq_pfn_memory_map MMG$GQ_PFN_MEMORY_MAP S#define mmg$gl_pte_levels MMG$GL_PTE_LEVELS S#define mmg$gq_pml5_base MMG$GQ_PML5_BASE S#define mmg$gq_pml4_base MMG$GQ_PML4_BASE S#define mmg$gq_pdpt_base MMG$GQ_PDPT_BASE S#define mmg$[gq_pd_base MMG$GQ_PD_BASE S#define mmg$gq_bpt_base MMG$GQ_BPT_BASE S#define mmg$gq_pml5_vrnx_base MMG$GQ_PML5_VRNX_BASE S#define mmg$gq_pml4_vrnx_base MMG$GQ_PML4_VRNX_BASE S#define mmg$gq_pdpt_vrnx_base MMG$GQ_PDPT_VRNX_BASE S#define mmg$gq_pd_vrnx_base MMG$GQ_PD_VRNX_BASE S#def[ine mmg$gq_bpt_vrnx_base MMG$GQ_BPT_VRNX_BASE S#define mmg$gq_pt_mask MMG$GQ_PT_MASK S#define mmg$gq_va_mask MMG$GQ_VA_MASK S#define exe$gq_public_vector_symvec EXE$GQ_PUBLIC_VECTOR_SYMVEC S#define exe$gq_public_vector_symvec_end EXE$GQ_PUBLIC_VECTOR_SYMVEC_END S#define exe$gq_sys_symvec EXE$GQ_SYS_SYMVEC [ S#define exe$gq_sys_symvec_end EXE$GQ_SYS_SYMVEC_END S#define mmg$gq_pte_levels MMG$GQ_PTE_LEVELS S#define mmg$gpq_npagdyn_s2 MMG$GPQ_NPAGDYN_S2 S#define exe$gpq_npagdynnxt_s2 EXE$GPQ_NPAGDYNNXT_S2 S#define mmg$gq_sysphd MMG$GQ_SYSPHD S#define swp$gq_wslpte SWP$GQ_WSLPTE [ S#define swp$gq_emptpte SWP$GQ_EMPTPTE S#define exe$gl_gh_exec_code_s2 EXE$GL_GH_EXEC_CODE_S2 S#define mmg$gq_stride MMG$GQ_STRIDE S#define exe$gl_gh_exec_data_s2 EXE$GL_GH_EXEC_DATA_S2 S#define exe$gl_gh_res_data_s2 EXE$GL_GH_RES_DATA_S2 S#define exe$gl_gh_ro_data_s0 EXE$GL_GH_RO_[DATA_S0 S#define exe$gl_gh_ro_res_data_s0 EXE$GL_GH_RO_RES_DATA_S0 S#define sgn$gl_npagedyn_s2 SGN$GL_NPAGEDYN_S2 S#define sgn$gl_boot_bitmap1_pk SGN$GL_BOOT_BITMAP1_PK S#define sgn$gl_boot_bitmap2_pk SGN$GL_BOOT_BITMAP2_PK S#define sgn$gl_boot_bitmap1_dk SGN$GL_BOOT_BITMAP1_DK S#define sgn$gl_boot_bitmap2_dk SGN[$GL_BOOT_BITMAP2_DK S#define exe$gl_disable_x86_ft EXE$GL_DISABLE_X86_FT S#define mmg$gq_pml5_end MMG$GQ_PML5_END S#define mmg$gq_pml4_end MMG$GQ_PML4_END S#define mmg$gq_pdpt_end MMG$GQ_PDPT_END S#define mmg$gq_pd_end MMG$GQ_PD_END S#define mmg$gq_bpt_end [ MMG$GQ_BPT_END S#define mmg$gq_pml5_size MMG$GQ_PML5_SIZE S#define mmg$gq_pml4_size MMG$GQ_PML4_SIZE S#define mmg$gq_pdpt_size MMG$GQ_PDPT_SIZE S#define mmg$gq_pd_size MMG$GQ_PD_SIZE S#define mmg$gq_bpt_size MMG$GQ_BPT_SIZE S#define sgn$gl_boot_bitmap1 [ SGN$GL_BOOT_BITMAP1 S#define sgn$gl_boot_bitmap2 SGN$GL_BOOT_BITMAP2 S#define exe$gl_supported_x86_features EXE$GL_SUPPORTED_X86_FEATURES S#define exe$gq_mv_sva EXE$GQ_MV_SVA S#define exe$gl_scb_lbn EXE$GL_SCB_LBN S#define sgn$gl_timer_device SGN$GL_TIMER_DEVICE #define pms$gl_npa[gdynexps_s2 PMS$GL_NPAGDYNEXPS_S2 /* Count of successful expansion attempts to */#define pms$gl_npagdynexpim_s2 PMS$GL_NPAGDYNEXPIM_S2 /* Count of unsuccessful expansion attempts to */#define pms$gl_npagdynf_s2 PMS$GL_NPAGDYNF_S2 /* Count of non-paged pool failure epochs */#define pms$gl_npagdynfpag[es_s2 PMS$GL_NPAGDYNFPAGES_S2 /* Failed PAGES accumulator */#define pms$gl_npagdynreq_s2 PMS$GL_NPAGDYNREQ_S2 /* Non-paged pool allocation requests */#define pms$gl_npagdynreqf_s2 PMS$GL_NPAGDYNREQF_S2 /* Non-paged pool allocation request fails */#define exe$gq_npagdynsz_s2 [ EXE$GQ_NPAGDYNSZ_S2 /* Size in bytes of nonpaged pool */#define mmg$gpq_npp_npool_s2 MMG$GPQ_NPP_NPOOL_S2 /* pointer to s2 npool data structure */#define mmg$gpq_npp_base_lsthds_s2 MMG$GPQ_NPP_BASE_LSTHDS_S2 /* pointer to S2 listhead */#define sgn$gl_npag_ring_size_s2 [ SGN$GL_NPAG_RING_SIZE_S2 /* S2 history buffer size */#define exe$gq_npagmaxexpsz_s2 EXE$GQ_NPAGMAXEXPSZ_S2 /* max allowed s2 npp pool expansion */#define exe$gq_npagtotalsz_s2 EXE$GQ_NPAGTOTALSZ_S2 /* total allocate S2 pool base + what we expanded */#define mmg$gpq_npagexpnxt_s2 MMG$G\PQ_NPAGEXPNXT_S2 /* Next address we can expand to */#define sgn$gl_npagexpvir_s2 SGN$GL_NPAGEXPVIR_S2 /* Max allowed S2 sysgen param */#define exe$gl_random_sources EXE$GL_RANDOM_SOURCES /* SYSGEN param RANDOM_SOURCES */#define exe$gl_active_random_sources EXE$GL_ACTIVE\_RANDOM_SOURCES /* Active source bitmask */#define pms$gl_npagdynexpst_s2 PMS$GL_NPAGDYNEXPST_S2 /* S2 Expansion State */#define pms$gl_npagdynfls_s2 PMS$GL_NPAGDYNFLS_S2 /* S2 Flush success */#define pms$gl_npagdynflim_s2 PMS$GL_NPAGDYNFLIM_S2\ /* S2 flush Insufficient Memory */#define pms$gl_npagdynflto_s2 PMS$GL_NPAGDYNFLTO_S2 /* S2 Flush timed out */#define exe$ar_procstart_trace EXE$AR_PROCSTART_TRACE /* Procstart tracing structure */#define exe$gl_image_security EXE$GL_IMAGE_SECURITY \ /* SYSGEN param IMAGE_SECURITY */S#define sys$k_version SYS$K_VERSION S#define sys$k_version_01 SYS$K_VERSION_01 S#define sys$k_version_02 SYS$K_VERSION_02 S#define sys$k_version_03 SYS$K_VERSION_03 S#define sys$k_version_04 SYS$K_VERSION_04 \ S#define sys$k_version_05 SYS$K_VERSION_05 S#define sys$k_version_06 SYS$K_VERSION_06 S#define sys$k_version_07 SYS$K_VERSION_07 S#define sys$k_version_08 SYS$K_VERSION_08 S#define sys$k_version_09 SYS$K_VERSION_09 S#define sys$k_version_10 SYS$K_VERSION_1\0 S#define sys$k_version_11 SYS$K_VERSION_11 S#define sys$k_version_12 SYS$K_VERSION_12 S#define sys$k_version_13 SYS$K_VERSION_13 S#define sys$k_version_14 SYS$K_VERSION_14 S#define sys$k_version_15 SYS$K_VERSION_15 S#define sys$k_version_16 SYS$K\_VERSION_16 S#define ctl$c_krp_count CTL$C_KRP_COUNT S#define ctl$c_krp_size CTL$C_KRP_SIZE S#define ctl$c_p1ptr_size CTL$C_P1PTR_SIZE S#define swp$c_shlp1pt SWP$C_SHLP1PT S#define swp$c_kstack SWP$C_KSTACK S#define swp$c_kstack_wsl \ SWP$C_KSTACK_WSL S#define swp$c_l2pt SWP$C_L2PT S#define swp$c_shlproc SWP$C_SHLPROC #define ctl$a_prcprm_kdata CTL$A_PRCPRM_KDATA /* K-mode Process Data Area */S#define ctl$gl_vectors CTL$GL_VECTORS S#define ctl$a_initial_pkta \ CTL$A_INITIAL_PKTA #define iac$al_imgactbuf IAC$AL_IMGACTBUF /* Image activator scratch area */#define pio$a_rms_pioend PIO$A_RMS_PIOEND /* Process IFB/IRB tables */S#define glx$gq_glcktbl_fkbq GLX$GQ_GLCKTBL_FKBQ S#define pio$a_rms_piobase  \ PIO$A_RMS_PIOBASE #define ctl$a_common CTL$A_COMMON /* DEC "core common" area */#define mmg$imghdrbuf MMG$IMGHDRBUF /* Image header buffer */#define ctl$gl_nmioch CTL$GL_NMIOCH /* Number of channels  \ */#define ctl$gl_chindx CTL$GL_CHINDX /* Maximum channel index */#define ctl$gl_lnmhash CTL$GL_LNMHASH /* Process Logical Name HASH table */#define ctl$gl_lnmdirect CTL$GL_LNMDIRECT /* Process Logical Name DIRECTory  \ */#define ctl$aq_stack CTL$AQ_STACK /* Stack pointer restart array */#define ctl$gq_lnmtblcache CTL$GQ_LNMTBLCACHE /* Queue header for logical name table */#define ctl$gl_cmsupr CTL$GL_CMSUPR /* Supervisor change mode dispatcher  \ */#define ctl$gl_cmuser CTL$GL_CMUSER /* User change mode dispatcher */#define ctl$aq_excvec CTL$AQ_EXCVEC /* Primary/secondary exception vectors */#define ctl$gl_thexec CTL$GL_THEXEC /* Executive termination handler  \ */#define ctl$gl_thsupr CTL$GL_THSUPR /* Supervisor termination handler */#define ctl$gq_common CTL$GQ_COMMON /* Core common descriptor */#define ctl$gl_getmsg CTL$GL_GETMSG /* Per-process vector to user message \ */#define ctl$aq_stacklim CTL$AQ_STACKLIM /* Stack limit array (indexed by mode) */#define ctl$gl_ctlbasva CTL$GL_CTLBASVA /* Base control region address */#define ctl$gl_imghdrbf CTL$GL_IMGHDRBF /* Address of image activator's image */#d\efine ctl$gl_imglstptr CTL$GL_IMGLSTPTR /* Address of icb list (for debugger) */#define ctl$gl_phd CTL$GL_PHD /* Address of phd window */#define ctl$gq_allocreg CTL$GQ_ALLOCREG /* Head of process allocation region pool */#define \ctl$gq_mountlst CTL$GQ_MOUNTLST /* Mounted device list */#define ctl$t_username CTL$T_USERNAME /* Username */#define ctl$t_account CTL$T_ACCOUNT /* Account name */#define ctl$gq_l\ogin CTL$GQ_LOGIN /* System time at process creation */#define ctl$gl_finalsts CTL$GL_FINALSTS /* Final exit status for process */#define ctl$gl_wspeak CTL$GL_WSPEAK /* Peak working set size */#define ctl$gl_virtpeak \ CTL$GL_VIRTPEAK /* Peak virtual size */#define ctl$gl_volumes CTL$GL_VOLUMES /* Count of volumes mounted */#define ctl$gq_istart CTL$GQ_ISTART /* Image activation time */#define ctl$gl_icputim \ CTL$GL_ICPUTIM /* Initial image cpu time */#define ctl$gl_ifaults CTL$GL_IFAULTS /* Initial image fault count */#define ctl$gl_ifaultio CTL$GL_IFAULTIO /* Initial image fault i/o count */#define ctl$gl_iwspeak \ CTL$GL_IWSPEAK /* Image working set peak */#define ctl$gl_ipagefl CTL$GL_IPAGEFL /* Image page file peak usage */#define ctl$gl_idiocnt CTL$GL_IDIOCNT /* Initial image direct i/o count */#define ctl$gl_ibiocnt CTL\$GL_IBIOCNT /* Initial image buffered i/o count */#define ctl$gl_ivolumes CTL$GL_IVOLUMES /* Initial image volume mount count */#define ctl$t_nodeaddr CTL$T_NODEADDR /* Remote node address (binary) */#define ctl$t_nodename CTL$T_NODEN\AME /* Remote node name (ascii) */#define ctl$t_remoteid CTL$T_REMOTEID /* Remote id */#define ctl$gq_procpriv CTL$GQ_PROCPRIV /* Process privilege mask */#define ctl$gl_powerast CTL$GL_POWERAST \ /* Power fail ast address */#define ctl$gb_ssfilter CTL$GB_SSFILTER /* Sys serv inhibit filter mask */#define ctl$gb_pwrmode CTL$GB_PWRMODE /* Access mode for power fail ast */#define ctl$al_finalexc CTL$AL_FINALEXC \ /* Final exception handler array */#define ctl$gl_xsig CTL$GL_XSIG /* Address of POSIX XSIG structure */#define ctl$gq_dbgarea CTL$GQ_DBGAREA /* Debug area */S#define ctl$gl_rmsbase CTL$GL_RMSBASE \ #define ctl$gl_ppmsg CTL$GL_PPMSG /* Address of process perm. msg section */#define ctl$gb_msgmask CTL$GB_MSGMASK /* Default message display flags */#define ctl$gb_deflang CTL$GB_DEFLANG /* Default message language */#def\ine ctl$gw_ppmsgchn CTL$GW_PPMSGCHN /* Channel to process perm. message */#define ctl$gl_usrundwn CTL$GL_USRUNDWN /* Per-process vector to user rundown */#define ctl$gl_pcb CTL$GL_PCB /* Address of process control block */#define ct\l$gl_ruf CTL$GL_RUF /* Pointer to recovery unit blocks */#define ctl$gl_sitespec CTL$GL_SITESPEC /* Site-specific per-process cell */#define ctl$gl_knownfil CTL$GL_KNOWNFIL /* Process known file list pointer */#define ctl$gl_iaf\lnkptr CTL$GL_IAFLNKPTR /* Address of iaf list (for debugger) */#define ctl$gl_f11bxqp CTL$GL_F11BXQP /* Address of f11b xqp queue and */#define ctl$gq_p0alloc CTL$GQ_P0ALLOC /* Header of p0 extention to process */#define ctl$gl_prcallcnt \ CTL$GL_PRCALLCNT /* Count of bytes of process allocation */#define ctl$gl_rdiptr CTL$GL_RDIPTR /* Pointer to rights database identifier (rdi) block */#define ctl$gl_lnmdirseq CTL$GL_LNMDIRSEQ /* Sequence number for cache of logical */#define ctl$gq_helpflags \ CTL$GQ_HELPFLAGS /* Help flags, one longword for use */#define ctl$gq_termchar CTL$GQ_TERMCHAR /* Home for terminal characteristics */#define ctl$gl_krpfl CTL$GL_KRPFL /* P1 pool lookaside list forward link */#define ctl$gl_krpbl \ CTL$GL_KRPBL /* P1 pool lookaside list backward link */#define ctl$gl_creprc_flags CTL$GL_CREPRC_FLAGS /* $CREPRC flags */#define ctl$gl_thcount CTL$GL_THCOUNT /* Count of termination handlers for */#define ctl$ga_les_process CTL$G \A_LES_PROCESS /* Reserved for LES use */#define ctl$gq_xcb_que CTL$GQ_XCB_QUE /* Process list of active transactions */#define ctl$gl_prcprm_kdata2 CTL$GL_PRCPRM_KDATA2 /* Address of kernel data extension area */#define ctl$gl_usrundwn_exec CTL$GL_USRUND!\WN_EXEC /* Per-process vector to user rundown */#define ctl$a_evi_kdata CTL$A_EVI_KDATA /* Kernel mode event data */#define ctl$a_evi_edata CTL$A_EVI_EDATA /* Exec mode event data */#define ctl$a_evi_sdata CTL$A_EVI_SDATA "\ /* Super mode event data */#define ctl$a_evi_udata CTL$A_EVI_UDATA /* User mode event data */#define ctl$a_kspini CTL$A_KSPINI /* Initial kernel stack pointer */#define ctl$a_dispvec CTL$A_DISPVEC #\ /* Adr of vectors for sys srv/errmsg */#define ctl$a_nsa_idt CTL$A_NSA_IDT /* Security auditing impure data table */#define ctl$a_krp CTL$A_KRP /* Address used by procstrt to find it */#define ctl$gl_catchall_extension CTL$GL_CATCHALL_EXTENSION /$\* Catch-all extensions listhead */#define ctl$gl_catchall_extension_cnt CTL$GL_CATCHALL_EXTENSION_CNT /* Catch-all extensions count */#define ctl$gl_xpcb CTL$GL_XPCB /* Address of extended process control block */#define ctl$gl_psx_argptr CTL$GL_PSX_ARGPTR /* POSIX%\ location for argument list of Exec() */#define pio$gl_fmlh PIO$GL_FMLH /* Free memory list head */#define pio$gl_iiofsplh PIO$GL_IIOFSPLH /* Free list header for image I/O seg */#define pio$gw_status PIO$GW_STATUS /* RMS overall s&\tatus */#define pio$gw_dfprot PIO$GW_DFPROT /* Default file protection */#define pio$gw_rmsextend PIO$GW_RMSEXTEND /* Extend quantity for RMS files */#define pio$gt_endstr PIO$GT_ENDSTR /* End of data string '\ */#define pio$gb_dfmbc PIO$GB_DFMBC /* Default multi-block count */#define pio$gb_dfmbfsdk PIO$GB_DFMBFSDK /* Default multi-buffer count seq. disk */#define pio$gb_dfmbfsmt PIO$GB_DFMBFSMT /* Default multi-buffer count ma(\gtape */#define pio$gb_dfmbfsur PIO$GB_DFMBFSUR /* Default multi-buffer count unit rec. */#define pio$gb_dfmbfrel PIO$GB_DFMBFREL /* Default multi-buffer count relative */#define pio$gb_dfmbfidx PIO$GB_DFMBFIDX /* Default multi-buffer count indexed )\ */#define pio$gb_rms_conpolicy PIO$GB_RMS_CONPOLICY /* Default RMS Contention Policy */#define pio$gb_dfnbc PIO$GB_DFNBC /* NETWORK BLOCK COUNT TRANSFER SIZE */#define pio$gb_rmsprolog PIO$GB_RMSPROLOG /* Structure level for RMS files *\ */#define pio$gb_ruf_flags PIO$GB_RUF_FLAGS /* RMS/DDTM RUF emulation flags */#define pio$gb_jnl_stall_cnt PIO$GB_JNL_STALL_CNT /* Count of journal stalled threads (RUF only) */#define pio$gl_dircache PIO$GL_DIRCACHE /* Directory cache list head +\ */#define pio$gq_rub_qh PIO$GQ_RUB_QH /* RMS Recovery Unit Block (RUB) queue header */#define pio$gl_rub_flink PIO$GL_RUB_FLINK /* RUB queue forward link */#define pio$gl_rub_blink PIO$GL_RUB_BLINK /* RUB queue backward link ,\ */#define pio$gl_nxtirbseq PIO$GL_NXTIRBSEQ /* Next sequence number for IRB$L_IDENT */S#define pio$gw_pioimpa PIO$GW_PIOIMPA #define pio$gw_iioimpa PIO$GW_IIOIMPA /* Image i/o impure area */#define pio$al_rmsexh PIO$AL_RMSEXH -\ /* Exit handler control block */#define pio$gq_iiodefault PIO$GQ_IIODEFAULT /* Default image i/o area */#define pio$gl_lnkcshadr PIO$GL_LNKCSHADR /* Logical link cache entry listhead */#define pio$gl_nt0_rm_id PIO$GL_NT0_RM_ID .\ /* RMS/DDTM Network resource manager ID */#define pio$gl_ru_handler_id PIO$GL_RU_HANDLER_ID /* Default recovery unit handler ID (RUF only) */#define pio$gl_ru_failure_count PIO$GL_RU_FAILURE_COUNT /* Recovery unit failure count */#define pio$gl_ru_wait_q_flink PIO$GL_RU_WAIT_Q_FLINK /* /\ Recovery unit wait queue flink */#define pio$gl_ru_wait_q_blink PIO$GL_RU_WAIT_Q_BLINK /* Recovery unit wait queue blink */#define pio$gq_free_pio_rub_qh PIO$GQ_FREE_PIO_RUB_QH /* RMS free PIO RUB queue header */#define pio$gl_free_pio_rub_flink PIO$GL_FREE_PIO_RUB_FLINK /* Free PI0\O RUB queue forward link */#define pio$gl_free_pio_rub_blink PIO$GL_FREE_PIO_RUB_BLINK /* Free PIO RUB queue backward link */#define pio$gq_free_iio_rub_qh PIO$GQ_FREE_IIO_RUB_QH /* RMS free IIO RUB queue header */#define pio$gl_free_iio_rub_flink PIO$GL_FREE_IIO_RUB_FLINK /* Free IIO RUB qu1\eue forward link */#define pio$gl_free_iio_rub_blink PIO$GL_FREE_IIO_RUB_BLINK /* Free IIO RUB queue backward link */#define pio$gq_ntrub_qh PIO$GQ_NTRUB_QH /* RMS Network Recovery Unit Block (NTRUB) queue header */#define pio$gq_ruf_tsb_qh PIO$GQ_RUF_TSB_QH /* RUF Transaction Stack B2\lock (TSB) queue header */#define pio$gl_alloc_table PIO$GL_ALLOC_TABLE /* RMS pool checker structure pointer */#define pio$gq_urew_fplh PIO$GQ_UREW_FPLH /* UREW Image I/O Data Buffer Free Page List Head */#define pio$gq_urew_iiodefault PIO$GQ_UREW_IIODEFAULT /* UREW Image I/O Data Default 3\ */#define pio$gq_urew_iio_seg PIO$GQ_UREW_IIO_SEG /* UREW Image I/O Data Segment */#define pio$gl_cur_asb PIO$GL_CUR_ASB /* Pointer to current ASB */#define pio$gl_asb_slots PIO$GL_ASB_SLOTS /* ASB lookaside list counter 4\ */#define pio$gl_asb_list PIO$GL_ASB_LIST /* ASB lookaside list head */#define pio$gl_rms_active PIO$GL_RMS_ACTIVE /* RMS active flag */#define pio$gq_reserved0 PIO$GQ_RESERVED0 /* Reserved for future use by RMS 5\ */#define pio$gq_reserved1 PIO$GQ_RESERVED1 /* Reserved for future use by RMS */#define pio$gq_reserved2 PIO$GQ_RESERVED2 /* Reserved for future use by RMS */#define pio$gl_reserved3 PIO$GL_RESERVED3 /* Reserved for future use by RMS 6\ */#define pio$gl_reserved4 PIO$GL_RESERVED4 /* Reserved for future use by RMS */#define pio$gl_reserved5 PIO$GL_RESERVED5 /* Reserved for future use by RMS */#define pio$gl_reserved6 PIO$GL_RESERVED6 /* Reserved for future use by RMS 7\ */#define pio$gt_ddstring PIO$GT_DDSTRING /* DEFAULT DIRECTORY STRING */#define fil$gt_ddstring FIL$GT_DDSTRING /* FILE READ DEFAULT DIRECTORY STRING */#define ctl$al_clicalbk CTL$AL_CLICALBK /* Call back vector for CLI 8\ */#define ctl$ag_climage CTL$AG_CLIMAGE /* VA range into which CLI is mapped */#define ctl$ag_clitable CTL$AG_CLITABLE /* VA range into which CLI table is */#define ctl$gl_uaf_flags CTL$GL_UAF_FLAGS /* Flags from authorization record */9\#define ctl$gt_cliname CTL$GT_CLINAME /* CLI name (file name only) */#define ctl$gt_tablename CTL$GT_TABLENAME /* CLI table name (full file spec) */#define ctl$gt_spawncli CTL$GT_SPAWNCLI /* spawn CLI name (file name only) */#define :\ ctl$gt_spawntable CTL$GT_SPAWNTABLE /* spawn CLI table name (full file spec) */#define ctl$ag_clidata CTL$AG_CLIDATA /* Start of data area */S#define ctl$c_clidatasz CTL$C_CLIDATASZ #define ctl$gl_dclprsown CTL$GL_DCLPRSOWN /* Address o;\f DCL wrk area created */#define ctl$gl_clintown CTL$GL_CLINTOWN /* Address of context block used by */#define ctl$gl_pstflags CTL$GL_PSTFLAGS /* Process start flags */#define ctl$gt_cli_namestring CTL$GT_CLI_NAMESTRING /* CLI imag file nam<\e string holder */#define ctl$gl_report_user_faults CTL$GL_REPORT_USER_FAULTS /* If non zero, report user faults */#define ctl$gl_report_method CTL$GL_REPORT_METHOD /* AFR$K_BUFFERED or AFR$K_EXCEPTION */#define ctl$gl_report_buffer CTL$GL_REPORT_BUFFER /* Address of alignment data=\ buffer */#define ctl$gl_buffer_items CTL$GL_BUFFER_ITEMS /* Max number of data items */#define ctl$gl_free_index CTL$GL_FREE_INDEX /* First free index */#define ctl$gl_used_index CTL$GL_USED_INDEX /* First used index >\ */#define ctl$gl_iaflink CTL$GL_IAFLINK /* Listhead of linked list of fixup vectors */#define ctl$gl_iaflast CTL$GL_IAFLAST /* Address of last fixup vector in list */#define ctl$gl_fixuplnk CTL$GL_FIXUPLNK /* Listhead of linked list of fixup ?\ */#define ctl$gl_p1merge CTL$GL_P1MERGE /* Listhead of linked list of fixup vectors */S#define ctl$gl_iafperm CTL$GL_IAFPERM S#define ctl$gl_iafexe CTL$GL_IAFEXE #define ctl$gl_bpd_ptr CTL$GL_BPD_PTR /* AUTO-JACKET BPD/PSB buffer pointer @\ */#define ctl$gl_xlated_img_cnt CTL$GL_XLATED_IMG_CNT /* Number of translated VAX shareable images */#define iac$gl_imagctx IAC$GL_IMAGCTX /* Context that exists for life of image */#define iac$gl_procctx IAC$GL_PROCCTX /* Context that exists beyond image exit A\ */#define iac$al_vecaddr IAC$AL_VECADDR /* Array of altered opcode addresses */#define iac$al_vecopcod IAC$AL_VECOPCOD /* Array of saved opcodes */S#define iac$gl_image_list IAC$GL_IMAGE_LIST S#define iac$gl_work_list IAC$GL_WORK_LB\IST S#define iac$gl_icbfl IAC$GL_ICBFL #define iac$gl_main_icb IAC$GL_MAIN_ICB /* ICB of main image */#define iac$gl_first_icb IAC$GL_FIRST_ICB /* ICB of image just merged */#define iac$gl_stack_size IAC$GL_STACK_SIC\ZE /* Amount by which to expand user stack */#define iac$gq_image_ids IAC$GQ_IMAGE_IDS /* Your basic descriptor */#define ctl$gq_orb_lockdb CTL$GQ_ORB_LOCKDB /* Header for $change_acl lock database */#define ctl$gl_license_cnt CTL$GL_LICENSE_CNT D\ /* LMF - count of licensed products */#define ctl$gq_rms_rurec_lksb CTL$GQ_RMS_RUREC_LKSB /* Recovery unit doorbell lock LKSB */#define ctl$gl_rms_ruj_count CTL$GL_RMS_RUJ_COUNT /* Active recovery unit journal count */#define ctl$gl_rms_rujlck_flink CTL$GL_RMS_RUJLCK_FLINK E\ /* RU journal lock block (RUJLCK) flink */#define ctl$gl_rms_rujlck_blink CTL$GL_RMS_RUJLCK_BLINK /* RU journal lock block (RUJLCK) blink */#define ctl$gl_uaictx CTL$GL_UAICTX /* Pointer to UAI context segment */#define ctl$gq_misc_p1_flags CTL$GQ_MISC_P1_FLAGS /* F\ Miscellaneous P1 flags. The values */#define ctl$gq_rmcb_que CTL$GQ_RMCB_QUE /* Process list of resource managers */#define ctl$gl_cur_xscb CTL$GL_CUR_XSCB /* Current default transaction pointer */#define ctl$gl_posix_1 CTL$GL_POSIX_1 /* POSIX cG\ell 1 */#define ctl$gl_posix_2 CTL$GL_POSIX_2 /* POSIX cell 2 */#define cfs$ga_dataptr CFS$GA_DATAPTR /* Posix address of CFS file system data structures */#define psx$ga_fs_dataptr PSX$GA_FS_DATAPTR /* POSIX address oH\f file system private structures */#define psx$ga_p1dataptr PSX$GA_P1DATAPTR /* POSIX address to a private structure */#define psx$gl_process_flags PSX$GL_PROCESS_FLAGS /* POSIX process flags */#define ctl$gq_lastlogin_i CTL$GQ_LASTLOGIN_I /* Last interactive login I\time */#define ctl$gq_lastlogin_n CTL$GQ_LASTLOGIN_N /* Last non-interactive login time */#define ctl$gl_logfails CTL$GL_LOGFAILS /* Login failure count at login */#define ctl$gl_login_flags CTL$GL_LOGIN_FLAGS /* Miscellaneous flags set by LOGIJ\NOUT */#define ctl$gl_subsys_rights CTL$GL_SUBSYS_RIGHTS /* Saved image rights */#define ctl$gl_pvolumes CTL$GL_PVOLUMES /* INITIAL COUNT OF VOLUMES MOUNTED */#define ctl$gq_pstart CTL$GQ_PSTART /* INITIAL START TIME K\ */#define ctl$gl_pcputim CTL$GL_PCPUTIM /* INITIAL CPU TIME */#define ctl$gl_pvpcputim CTL$GL_PVPCPUTIM /* INITIAL VECTOR CPU TIME */#define ctl$gl_pfaults CTL$GL_PFAULTS /* INITIAL FAULT COUNT L\ */#define ctl$gl_pfaultio CTL$GL_PFAULTIO /* INITIAL FAULT I/O COUNT */#define ctl$gl_pimgcnt CTL$GL_PIMGCNT /* INITIAL IMAGE COUNT */#define ctl$gl_pdiocnt CTL$GL_PDIOCNT /* INITIAL DIRECT I/O COUNT M\ */#define ctl$gl_pbiocnt CTL$GL_PBIOCNT /* INITIAL BUFFERED I/O COUNT */#define ctl$gl_dnsptr CTL$GL_DNSPTR /* DNS process context area pointer */#define qman$gq_message_list QMAN$GQ_MESSAGE_LIST /* Outstanding messages N\ */#define qman$gq_getqui_context QMAN$GQ_GETQUI_CONTEXT /* $GETQUI context */#define qman$gl_getqui_seed QMAN$GL_GETQUI_SEED /* $GETQUI context ID seed */#define qman$gl_getqui_default QMAN$GL_GETQUI_DEFAULT /* Default $GETQUI context O\ */#define qman$gl_qmgrs_used QMAN$GL_QMGRS_USED /* Bitmask of queue managers used */#define ctl$gl_native_to_tie CTL$GL_NATIVE_TO_TIE /* Addr. of native to TIE callback */S#define exe$a_sysparam EXE$A_SYSPARAM S#define exe$c_sysparsz EXE$C_SYSPARSZ P\ S#define boo$c_sysparsz BOO$C_SYSPARSZ S#define exe$gq_todcbase EXE$GQ_TODCBASE S#define exe$gq_saved_hwclock EXE$GQ_SAVED_HWCLOCK S#define exe$gq_tdf EXE$GQ_TDF S#define sgn$gw_dfpfc_pagelets SGN$GW_DFPFC_PAGELETS S#define sgn$gw_dfpfc_pages SGN$GW_DFPFC_PAGES Q\ S#define sgn$gb_pgtbpfc_pagelets SGN$GB_PGTBPFC_PAGELETS S#define sgn$gb_pgtbpfc_pages SGN$GB_PGTBPFC_PAGES S#define sgn$gb_syspfc_pagelets SGN$GB_SYSPFC_PAGELETS S#define sgn$gb_syspfc_pages SGN$GB_SYSPFC_PAGES S#define exe$gl_shadow_mbr_timeout EXE$GL_SHADOW_MBR_TIMEOUT S#define sch$gb_priority_offset SCH$GB_PRIORIR\TY_OFFSET S#define sgn$gw_gblsecnt SGN$GW_GBLSECNT S#define sgn$gl_maxgpgct_pagelets SGN$GL_MAXGPGCT_PAGELETS S#define sgn$gl_maxgpgct_pages SGN$GL_MAXGPGCT_PAGES S#define sgn$gl_gblpagfil SGN$GL_GBLPAGFIL S#define sgn$gw_maxprcct SGN$GW_MAXPRCCT S#define sgn$gw_pixscan SGNS\$GW_PIXSCAN S#define sgn$gl_smp_cpus SGN$GL_SMP_CPUS S#define sgn$gl_smp_cpush SGN$GL_SMP_CPUSH S#define sgn$gb_multiprocessing SGN$GB_MULTIPROCESSING S#define exe$gb_vp_load EXE$GB_VP_LOAD S#define sgn$gl_smp_sanity_cnt SGN$GL_SMP_SANITY_CNT S#define sgn$gl_smp_tick_cnt T\ SGN$GL_SMP_TICK_CNT S#define sgn$gl_smp_spinwait SGN$GL_SMP_SPINWAIT S#define sgn$gl_smp_lngspinwait SGN$GL_SMP_LNGSPINWAIT S#define sgn$gw_maxpstct SGN$GW_MAXPSTCT S#define sgn$gl_minwscnt SGN$GL_MINWSCNT S#define sgn$gw_pagfilct SGN$GW_PAGFILCT S#define sgn$gw_swpfiles U\ SGN$GW_SWPFILES S#define sgn$gl_sysdwsct_pagelets SGN$GL_SYSDWSCT_PAGELETS S#define sgn$gl_sysdwsct_pages SGN$GL_SYSDWSCT_PAGES S#define sgn$gl_kstackpag SGN$GL_KSTACKPAG S#define lck$gl_extrastk LCK$GL_EXTRASTK S#define sgn$gl_balsetct SGN$GL_BALSETCT S#define sgn$gl_maxV\wscnt_pagelets SGN$GL_MAXWSCNT_PAGELETS S#define sgn$gl_maxwscnt_pages SGN$GL_MAXWSCNT_PAGES S#define sgn$gl_npagedyn SGN$GL_NPAGEDYN S#define sgn$gl_npagevir SGN$GL_NPAGEVIR S#define sgn$gl_pagedyn SGN$GL_PAGEDYN S#define sgn$gl_maxvpgct_pagelets SGN$GL_MAXVPGCT_PAGELETS S#define W\sgn$gl_maxvpgct_pages SGN$GL_MAXVPGCT_PAGES S#define exe$gl_crd_control EXE$GL_CRD_CONTROL S#define sgn$gl_exusrstk SGN$GL_EXUSRSTK S#define sgn$gw_pchancnt SGN$GW_PCHANCNT S#define sgn$gw_piopagelets SGN$GW_PIOPAGELETS S#define sgn$gw_ctlpagelets SGN$GW_CTLPAGELETS SX\#define sgn$gw_ctlimglim SGN$GW_CTLIMGLIM S#define sgn$gw_imgiocnt SGN$GW_IMGIOCNT S#define mpw$aw_initval MPW$AW_INITVAL S#define mpw$gw_mpwpfc MPW$GW_MPWPFC S#define mpw$gl_hilim MPW$GL_HILIM S#define mpw$gl_lolim MPW$GL_LOLIM Y\ S#define mpw$gb_iolim MPW$GB_IOLIM S#define mpw$gb_prio MPW$GB_PRIO S#define swp$gb_prio SWP$GB_PRIO S#define mpw$gl_thresh MPW$GL_THRESH S#define mpw$gl_waitlim MPW$GL_WAITLIM S#define mpw$gl_lowaitlim MPW$GL_LOWAITLIM Z\ S#define sgn$gw_wslmxskp SGN$GW_WSLMXSKP S#define ctl$gl_fred CTL$GL_FRED S#define mmg$gl_phymem MMG$GL_PHYMEM S#define sch$gl_pfratl SCH$GL_PFRATL S#define sch$gl_pfrath SCH$GL_PFRATH S#define clu$gl_tmscp_load CLU$GL_TM[\SCP_LOAD S#define uid$gl_ieee_address UID$GL_IEEE_ADDRESS S#define uid$gw_ieee_addressh UID$GW_IEEE_ADDRESSH S#define sch$gl_wsinc_pagelets SCH$GL_WSINC_PAGELETS S#define sch$gl_wsinc_pages SCH$GL_WSINC_PAGES S#define sch$gl_wsdec_pagelets SCH$GL_WSDEC_PAGELETS S#define sch$gl_wsdec_pages \\ SCH$GL_WSDEC_PAGES S#define sch$gl_awsmin_pagelets SCH$GL_AWSMIN_PAGELETS S#define sch$gl_awsmin_pages SCH$GL_AWSMIN_PAGES S#define sch$gl_awstime SCH$GL_AWSTIME S#define sch$gl_swprate SCH$GL_SWPRATE S#define swp$gl_swppgcnt_pagelets SWP$GL_SWPPGCNT_PAGELETS S#define swp$gl_swppgcnt_pages ]\ SWP$GL_SWPPGCNT_PAGES S#define swp$gw_swpinc SWP$GW_SWPINC S#define sch$gw_quan SCH$GW_QUAN S#define sch$gw_iota SCH$GW_IOTA S#define sch$gw_longwait SCH$GW_LONGWAIT S#define sch$gw_dormantwait SCH$GW_DORMANTWAIT S#define sch$gw_swpfail ^\ SCH$GW_SWPFAIL S#define sgn$gl_lan_flags SGN$GL_LAN_FLAGS S#define sgn$gl_vmsd1 SGN$GL_VMSD1 S#define sgn$gl_vmsd2 SGN$GL_VMSD2 S#define sgn$gl_vmsd3 SGN$GL_VMSD3 S#define sgn$gl_vmsd4 SGN$GL_VMSD4 S#define sgn$gl_\_vms5 SGN$GL_VMS5 S#define sgn$gl_vms6 SGN$GL_VMS6 S#define sgn$gl_vms7 SGN$GL_VMS7 S#define sgn$gl_vms8 SGN$GL_VMS8 S#define sgn$gl_jobctld SGN$GL_JOBCTLD S#define sgn$gl_pu_options SGN$GL_PU_OPTIONS S#defin`\e sgn$gl_wptte_size SGN$GL_WPTTE_SIZE S#define sgn$gw_wpre_size SGN$GW_WPRE_SIZE S#define scs$gw_timvcfail SCS$GW_TIMVCFAIL S#define sgn$gb_qbus_mult_intr SGN$GB_QBUS_MULT_INTR S#define sgn$gw_erlbufcnt SGN$GW_ERLBUFCNT S#define sys$gl_erlbufpagelets SYS$GL_ERLBUFPAGELETS a\ S#define sgn$gl_dump_style SGN$GL_DUMP_STYLE S#define sgn$gl_userd1 SGN$GL_USERD1 S#define sgn$gl_userd2 SGN$GL_USERD2 S#define sgn$gl_user3 SGN$GL_USER3 S#define sgn$gl_user4 SGN$GL_USER4 S#define sgn$gl_extracpu SGN$GL_EXTRACPU b\ S#define exe$gl_sysuic EXE$GL_SYSUIC S#define ioc$gw_mvtimeout IOC$GW_MVTIMEOUT S#define ioc$gw_tape_mvtimeout IOC$GW_TAPE_MVTIMEOUT S#define ioc$gw_maxbuf IOC$GW_MAXBUF S#define ioc$gl_mbxbfquo IOC$GL_MBXBFQUO S#define ioc$gw_mbxmxmsg IOC$GW_MBXMXMSGc\ S#define sgn$gl_npag_ring_size SGN$GL_NPAG_RING_SIZE S#define sgn$gl_freelim SGN$GL_FREELIM S#define sgn$gl_freegoal SGN$GL_FREEGOAL S#define sch$gl_growlim SCH$GL_GROWLIM S#define sch$gl_borrowlim SCH$GL_BORROWLIM S#define exe$gl_lockrtry EXE$Gd\L_LOCKRTRY S#define ioc$gw_xfmxrate IOC$GW_XFMXRATE S#define ioc$gw_lamapreg IOC$GW_LAMAPREG #define clu$gl_niscs_max_pktsz CLU$GL_NISCS_MAX_PKTSZ /* Maximum packet size for LAN transfers (includes LAN overhead). */S#define exe$gl_clitabl EXE$GL_CLITABL S#define lck$gl_idtblsiz Le\CK$GL_IDTBLSIZ S#define lck$gl_idtblmax LCK$GL_IDTBLMAX S#define lck$gl_htblsiz LCK$GL_HTBLSIZ S#define lck$gl_waittime LCK$GL_WAITTIME S#define scs$gw_bdtcnt SCS$GW_BDTCNT S#define scs$gw_cdtcnt SCS$GW_CDTCNT S#define scs$gw_rdtcnt f\ SCS$GW_RDTCNT S#define scs$gw_maxdg SCS$GW_MAXDG S#define scs$gw_maxmsg SCS$GW_MAXMSG S#define scs$gw_flowcush SCS$GW_FLOWCUSH S#define scs$gb_systemid SCS$GB_SYSTEMID S#define scs$gb_systemidh SCS$GB_SYSTEMIDH S#define scs$gb_nodename g\ SCS$GB_NODENAME S#define scs$gw_prcpolint SCS$GW_PRCPOLINT S#define scs$gw_pastmout SCS$GW_PASTMOUT S#define scs$gw_pappddg SCS$GW_PAPPDDG S#define scs$gb_panpoll SCS$GB_PANPOLL S#define scs$gb_pamxport SCS$GB_PAMXPORT S#define scs$gw_ph\apolint SCS$GW_PAPOLINT S#define scs$gw_papoolin SCS$GW_PAPOOLIN S#define scs$gb_pasanity SCS$GB_PASANITY S#define scs$gb_panopoll SCS$GB_PANOPOLL #define clu$gl_niscs_lan_ovrhd CLU$GL_NISCS_LAN_OVRHD /* Bytes reserved in LAN transfers for other devices (eg: DESNC). */S#define sgn$i\gl_pe1 SGN$GL_PE1 S#define sgn$gl_pe2 SGN$GL_PE2 S#define sgn$gl_pe3 SGN$GL_PE3 S#define sgn$gl_pe4 SGN$GL_PE4 S#define sgn$gl_pe5 SGN$GL_PE5 S#define sgn$gl_pe6 SGN$GL_PE6 S#defj\ine sgn$gw_tpwait SGN$GW_TPWAIT S#define exe$gw_clkint EXE$GW_CLKINT S#define scs$gb_udaburst SCS$GB_UDABURST S#define lnm$gl_htblsizs LNM$GL_HTBLSIZS S#define lnm$gl_htblsizp LNM$GL_HTBLSIZP S#define exe$gl_defflags EXE$GL_DEFFLAGS k\ S#define exe$gl_time_control EXE$GL_TIME_CONTROL S#define sgn$gl_brkmsk SGN$GL_BRKMSK S#define exe$gl_dynamic_flags EXE$GL_DYNAMIC_FLAGS S#define exe$gl_static_flags EXE$GL_STATIC_FLAGS S#define exe$gl_msgflags EXE$GL_MSGFLAGS S#define sgn$gl_loadflags SGN$GL_LOADFLAGS l\ S#define tty$gl_delta TTY$GL_DELTA S#define tty$gb_dialtyp TTY$GB_DIALTYP #define tty$gb_defspeed TTY$GB_DEFSPEED /* DEFAULT SPEED FOR TERMINALS AND PARITY */#define tty$gb_rspeed TTY$GB_RSPEED /* THE RECEIVE SPEED FOR A TERMINAL m\ */#define tty$gb_parity TTY$GB_PARITY /* THE PARITY OF THE TERMINALS */#define tty$gw_defbuf TTY$GW_DEFBUF /* DEFAULT BUFFER SIZE */#define tty$gl_defchar TTY$GL_DEFCHAR /* DEFAULT CHARACTERISTICS n\ */S#define tty$gl_defchar2 TTY$GL_DEFCHAR2 S#define tty$gw_typahdsz TTY$GW_TYPAHDSZ S#define tty$gw_altypahd TTY$GW_ALTYPAHD S#define tty$gw_altalarm TTY$GW_ALTALARM S#define tty$gw_dmasize TTY$GW_DMASIZE S#define mmg$gl_res_mem_flink MMG$GL_RES_MEM_FLINK o\ S#define mmg$gl_res_mem_blink MMG$GL_RES_MEM_BLINK S#define tty$gw_classnam TTY$GW_CLASSNAM S#define tty$gb_silotime TTY$GB_SILOTIME S#define tty$gl_timeout TTY$GL_TIMEOUT S#define tty$gb_autochar TTY$GB_AUTOCHAR #define tty$gl_defport TTY$GL_DEFPORp\T /* DEFAULT PORT CHARACTERISTICS */S#define sys$gb_dfmbc SYS$GB_DFMBC S#define sys$gb_dfmbfsdk SYS$GB_DFMBFSDK S#define sys$gb_dfmbfsmt SYS$GB_DFMBFSMT S#define sys$gb_dfmbfsur SYS$GB_DFMBFSUR S#define sys$gb_dfmbfrel SYS$GB_DFq\MBFREL S#define sys$gb_dfmbfidx SYS$GB_DFMBFIDX #define sys$gb_rms_conpolicy SYS$GB_RMS_CONPOLICY /* Default RMS Contention Policy */S#define sys$gb_rmsprolog SYS$GB_RMSPROLOG S#define sys$gw_rmsextend SYS$GW_RMSEXTEND S#define sys$gw_fileprot SYS$Gr\W_FILEPROT S#define mmg$gq_ptes_per_page MMG$GQ_PTES_PER_PAGE S#define sys$gb_dfnbc SYS$GB_DFNBC S#define pql$al_default PQL$AL_DEFAULT S#define pql$al_min PQL$AL_MIN S#define pql$ab_flag PQL$AB_FLAG #define pql$gdastlm s\ PQL$GDASTLM /* AST LIMIT */#define pql$gdbiolm PQL$GDBIOLM /* BUFFERED I/O LIMIT */#define pql$gdbytlm PQL$GDBYTLM /* BUFFERED I/O BYTE COUNT LIMIT */#define pql$gdcpulm PQLt\$GDCPULM /* CPU TIME LIMIT */#define pql$gddiolm PQL$GDDIOLM /* DIRECT I/O LIMIT */#define pql$gdfillm PQL$GDFILLM /* OPEN FILE LIMIT */#define pql$gdpgflquota_pagelets PQL$GDPGFLQu\UOTA_PAGELETS /* PAGING FILE QUOTA */#define pql$gdpgflquota_pages PQL$GDPGFLQUOTA_PAGES /* PAGING FILE QUOTA */#define pql$gdprclm PQL$GDPRCLM /* SUB-PROCESS LIMIT */#define pql$gdtqelm PQL$GDTQELM v\ /* TIMER QUEUE ENTRY LIMIT */#define pql$gdwsdefault_pagelets PQL$GDWSDEFAULT_PAGELETS /* WORKING SET DEFAULT SIZE */#define pql$gdwsdefault_pages PQL$GDWSDEFAULT_PAGES /* WORKING SET DEFAULT SIZE */#define pql$gdwsquota_pagelets PQL$GDWSQUOTA_PAGELETS w\ /* WORKING SET QUOTA */#define pql$gdwsquota_pages PQL$GDWSQUOTA_PAGES /* WORKING SET QUOTA */#define pql$gdwsextent_pagelets PQL$GDWSEXTENT_PAGELETS /* WORKING SET EXTENT */#define pql$gdwsextent_pages PQL$GDWSEXTENT_PAGES x\ /* WORKING SET EXTENT */#define pql$gdenqlm PQL$GDENQLM /* ENQUEUE LIMIT */#define pql$gdjtquota PQL$GDJTQUOTA /* JOB-WIDE LOGICAL NAME TABLE QUOTA */#define pql$gmastlm PQL$GMASTLM /* ASTy\ LIMIT */#define pql$gmbiolm PQL$GMBIOLM /* BUFFERED I/O LIMIT */#define pql$gmbytlm PQL$GMBYTLM /* BUFFERED I/O BYTE COUNT LIMIT */#define pql$gmcpulm PQL$GMCPULM /* CPU TIME LIz\MIT */#define pql$gmdiolm PQL$GMDIOLM /* DIRECT I/O LIMIT */#define pql$gmfillm PQL$GMFILLM /* OPEN FILE LIMIT */#define pql$gmpgflquota_pagelets PQL$GMPGFLQUOTA_PAGELETS /* PAGING FILE QUOTA {\ */#define pql$gmpgflquota_pages PQL$GMPGFLQUOTA_PAGES /* PAGING FILE QUOTA */#define pql$gmprclm PQL$GMPRCLM /* SUB-PROCESS LIMIT */#define pql$gmtqelm PQL$GMTQELM /* TIMER QUEUE ENTRY LIMIT |\ */#define pql$gmwsdefault_pagelets PQL$GMWSDEFAULT_PAGELETS /* WORKING SET DEFAULT SIZE */#define pql$gmwsdefault_pages PQL$GMWSDEFAULT_PAGES /* WORKING SET DEFAULT SIZE */#define pql$gmwsquota_pagelets PQL$GMWSQUOTA_PAGELETS /* WORKING SET QUOTA }\ */#define pql$gmwsquota_pages PQL$GMWSQUOTA_PAGES /* WORKING SET QUOTA */#define pql$gmwsextent_pagelets PQL$GMWSEXTENT_PAGELETS /* WORKING SET EXTENT */#define pql$gmwsextent_pages PQL$GMWSEXTENT_PAGES /* WORKING SET EXTENT ~\ */#define pql$gmenqlm PQL$GMENQLM /* ENQUEUE LIMIT */#define pql$gmjtquota PQL$GMJTQUOTA /* JOB-WIDE LOGICAL NAME TABLE QUOTA */S#define acp$gw_mapcache ACP$GW_MAPCACHE S#define acp$gw_hdrcache ACP$G\W_HDRCACHE S#define acp$gw_dircache ACP$GW_DIRCACHE S#define acp$gw_dindxcache ACP$GW_DINDXCACHE S#define acp$gw_workset ACP$GW_WORKSET S#define acp$gw_fidcache ACP$GW_FIDCACHE S#define acp$gw_extcache ACP$GW_EXTCACHE S#define acp$gw_extlimit \ ACP$GW_EXTLIMIT S#define acp$gw_quocache ACP$GW_QUOCACHE S#define acp$gw_sysacc ACP$GW_SYSACC S#define acp$gb_maxread ACP$GB_MAXREAD S#define acp$gb_window ACP$GB_WINDOW S#define acp$gb_writback ACP$GB_WRITBACK S#define acp$gb_datachk \ ACP$GB_DATACHK S#define acp$gb_baseprio ACP$GB_BASEPRIO S#define acp$gb_swapflgs ACP$GB_SWAPFLGS S#define sys$gb_defpri SYS$GB_DEFPRI S#define sys$gw_ijoblim SYS$GW_IJOBLIM S#define sys$gw_bjoblim SYS$GW_BJOBLIM S#define sys$gw_njobl\im SYS$GW_NJOBLIM S#define sys$gw_rjoblim SYS$GW_RJOBLIM S#define sys$gb_defquepri SYS$GB_DEFQUEPRI S#define sys$gb_maxquepri SYS$GB_MAXQUEPRI S#define sys$gb_pwd_tmo SYS$GB_PWD_TMO S#define sys$gb_retry_lim SYS$GB_RETRY_LIM S#define sy\s$gb_retry_tmo SYS$GB_RETRY_TMO S#define sys$gb_brk_lim SYS$GB_BRK_LIM S#define sys$gl_brk_tmo SYS$GL_BRK_TMO S#define sys$gl_hid_tim SYS$GL_HID_TIM S#define clu$gb_vaxcluster CLU$GB_VAXCLUSTER S#define clu$gw_exp_votes CLU$GW_EXP_VOTES S#d\efine clu$gw_votes CLU$GW_VOTES S#define clu$gw_recnxint CLU$GW_RECNXINT S#define clu$gb_qdisk CLU$GB_QDISK S#define clu$gw_qdskvotes CLU$GW_QDSKVOTES S#define clu$gw_qdskinterval CLU$GW_QDSKINTERVAL S#define clu$gl_allocls CLU$GL_ALLOCLS \ S#define clu$gw_lckdirwt CLU$GW_LCKDIRWT S#define clu$gl_sgn_flags CLU$GL_SGN_FLAGS S#define clu$gl_niscs_port_serv CLU$GL_NISCS_PORT_SERV S#define clu$gl_mscp_load CLU$GL_MSCP_LOAD S#define clu$gl_mscp_serve_all CLU$GL_MSCP_SERVE_ALL S#define clu$gl_mscp_buffer CLU$GL_MSCP_BUFFER \ S#define clu$gl_mscp_credits CLU$GL_MSCP_CREDITS S#define sgn$gb_tailored SGN$GB_TAILORED S#define exe$gq_mbz EXE$GQ_MBZ S#define exe$gl_old_sid EXE$GL_OLD_SID S#define exe$gt_startup EXE$GT_STARTUP S#define sgn$gb_startup_p1 SGN$GB_STAR\TUP_P1 S#define sgn$gb_startup_p2 SGN$GB_STARTUP_P2 S#define sgn$gb_startup_p3 SGN$GB_STARTUP_P3 S#define sgn$gb_startup_p4 SGN$GB_STARTUP_P4 S#define sgn$gb_startup_p5 SGN$GB_STARTUP_P5 S#define sgn$gb_startup_p6 SGN$GB_STARTUP_P6 S#define sgn$gb_startup_p7 S\GN$GB_STARTUP_P7 S#define sgn$gb_startup_p8 SGN$GB_STARTUP_P8 S#define exe$gl_s0_paging EXE$GL_S0_PAGING S#define exe$gl_poolcheck EXE$GL_POOLCHECK S#define sgn$gl_pseudoloa SGN$GL_PSEUDOLOA S#define sch$gl_ctlflags SCH$GL_CTLFLAGS S#define sch$gb_minclasspri \ SCH$GB_MINCLASSPRI S#define sch$gb_maxclasspri SCH$GB_MAXCLASSPRI S#define sch$gb_minprpri SCH$GB_MINPRPRI S#define mmg$gb_ctlflags MMG$GB_CTLFLAGS S#define mmg$gl_rsrvpagcnt MMG$GL_RSRVPAGCNT S#define exe$gl_window_system EXE$GL_WINDOW_SYSTEM S#define sch$gl_affinity_sk\ip SCH$GL_AFFINITY_SKIP S#define sch$gl_affinity_time SCH$GL_AFFINITY_TIME S#define exe$gb_erlbufpagelets EXE$GB_ERLBUFPAGELETS S#define clu$gl_tape_allocls CLU$GL_TAPE_ALLOCLS S#define exe$gl_vp_margin EXE$GL_VP_MARGIN S#define exe$gl_boot_style EXE$GL_BOOT_STYLE S#define exe$gl_s\hadowing EXE$GL_SHADOWING S#define exe$gl_shadow_sys_disk EXE$GL_SHADOW_SYS_DISK S#define exe$gl_shadow_sys_unit EXE$GL_SHADOW_SYS_UNIT S#define exe$gl_shadow_max_copy EXE$GL_SHADOW_MAX_COPY S#define sys$gw_dflrl SYS$GW_DFLRL S#define sys$gb_rmsheuristic SYS$GB_RMSHEURISTIC S#define \ exe$gl_npagedyn EXE$GL_NPAGEDYN S#define exe$gl_npagevir EXE$GL_NPAGEVIR S#define cache$gl_flags CACHE$GL_FLAGS S#define exe$gl_npag_bap_max EXE$GL_NPAG_BAP_MAX S#define cache$gl_blockcntmax CACHE$GL_BLOCKCNTMAX S#define exe$gl_npag_bap_min EXE$GL_NPAG_BAP_MIN \S#define exe$gl_npag_bap_max_pa EXE$GL_NPAG_BAP_MAX_PA S#define xqp$gl_alloc_blocks XQP$GL_ALLOC_BLOCKS S#define sys$gb_callouts SYS$GB_CALLOUTS S#define sys$gb_net_callouts SYS$GB_NET_CALLOUTS S#define sgn$gl_dnvosi1 SGN$GL_DNVOSI1 #define ioc$intdisp IOC$INTDISP \ /* *MUST* be type DATA */S#define ots$div_data OTS$DIV_DATA S#define sys$c_jobctlmb SYS$C_JOBCTLMB S#define pfm$c_bufcnt PFM$C_BUFCNT #define phv$gl_pixbas PHV$GL_PIXBAS /* Base of process index vector \ */S#define mmg$gl_ptes_per_page MMG$GL_PTES_PER_PAGE S#define mmg$gl_pagswpvc MMG$GL_PAGSWPVC #define sch$gl_pcbvec SCH$GL_PCBVEC /* Pointer to pcb vector */#define sch$gl_seqvec SCH$GL_SEQVEC /* Pointer to sequence number vector \ */#define mpw$gl_badpagtotal MPW$GL_BADPAGTOTAL /* Total pages ever put on bad page list */S#define mmg$gl_maxpfidx MMG$GL_MAXPFIDX #define sgn$gw_swpfilct SGN$GW_SWPFILCT /* Count of swapfile slots */S#define mmg$gw_minpfidx MMG$GW_MINPFIDX \ S#define mb$ar_dpt MB$AR_DPT S#define mb$ar_ddt MB$AR_DDT S#define nl$ar_dpt NL$AR_DPT S#define nl$ar_ddt NL$AR_DDT #define pms$gl_faults PMS$GL_FAULTS /* Count of page faults \ */#define pms$gl_preads PMS$GL_PREADS /* Page reads */S#define pms$gl_rdflts PMS$GL_RDFLTS #define pms$gl_preadio PMS$GL_PREADIO /* I/O requests to read the pages */#define pms$gl_pwrites PMS$GL_PWRITES \ /* Modified pages written */#define pms$gl_pwritio PMS$GL_PWRITIO /* I/O requests to write the modified pages */#define pms$gl_dzroflts PMS$GL_DZROFLTS /* Demand zero page faults */#define pms$gl_dptscn PMS$GL_DPTSCN /* \Dead page table scans */#define pms$gl_gvalid PMS$GL_GVALID /* Global valid faults */#define pms$gl_fow_flts PMS$GL_FOW_FLTS /* Fault On Write faults */#define pms$gl_for_flts PMS$GL_FOR_FLTS /* Fault On\ Read faults */#define pms$gl_foe_flts PMS$GL_FOE_FLTS /* Fault On Execute faults */#define mpw$gl_iopagcnt MPW$GL_IOPAGCNT /* Modified pages in transit to disk */S#define mpw$l_count MPW$L_COUNT S#define exe$gq\_sysdisk EXE$GQ_SYSDISK #define ldr$gq_image_list LDR$GQ_IMAGE_LIST /* Loaded Image data blocks */#define ldr$gq_hpdesc LDR$GQ_HPDESC /* Loader huge page descriptors */#define mmg$gl_pfnlock_pages MMG$GL_PFNLOCK_PAGES /* Counter of PFN-lo\cked pages */#define swp$gl_swtime SWP$GL_SWTIME /* Earliest time for next exchange swap */#define swp$gw_balcnt SWP$GW_BALCNT /* Count of processes in balance set */#define sch$gw_swpfcnt SCH$GW_SWPFCNT /* Count of successive swap \ */S#define lnm$ar_system_directory LNM$AR_SYSTEM_DIRECTORY S#define lnm_ar_system_dir_lnmth LNM_AR_SYSTEM_DIR_LNMTH S#define pql$ar_syspql PQL$AR_SYSPQL S#define pql$gl_syspqllen PQL$GL_SYSPQLLEN #define erl$gb_bufflag ERL$GB_BUFFLAG /* Buffer status flags \ */#define erl$gb_buftim ERL$GB_BUFTIM /* Format process wakeup timer */#define erl$gl_erlpid ERL$GL_ERLPID /* Process id of error log process */#define erl$gl_sequence ERL$GL_SEQUENCE /* Universal error sequence numbe\r */#define exe$ar_io_routines_data EXE$AR_IO_ROUTINES_DATA /* IO_ROUTINES private data area */S#define exe$ar_fork_wait_queue EXE$AR_FORK_WAIT_QUEUE #define exe$ab_hextab EXE$AB_HEXTAB /* Hexdecimal conversion table */#define bug$l_bugchk_flags \ BUG$L_BUGCHK_FLAGS /* Flags to be used by bugcheck code */#define bug$l_fatal_spsav BUG$L_FATAL_SPSAV /* Fatal bugcheck in progress sp */#define exe$a_id_upcase EXE$A_ID_UPCASE /* Table used to translate to upper case */S#define ioc$gl_adplist \ IOC$GL_ADPLIST S#define ioc$gl_dptlist IOC$GL_DPTLIST S#define tty$gl_dpt TTY$GL_DPT S#define no$gl_dpt NO$GL_DPT S#define tty$gl_jobctlmb TTY$GL_JOBCTLMB S#define sys$gl_uis SYS$GL_UIS S#define uis$gl_usb \ UIS$GL_USB S#define sys$gl_fallback SYS$GL_FALLBACK #define exe$gl_cpunodsp EXE$GL_CPUNODSP /* Holds virtual address that maps BI */#define exe$gl_confregl EXE$GL_CONFREGL /* Holds the address of a longword array */#define exe$gl_confreg \ EXE$GL_CONFREG /* Holds the address of a byte array */#define mmg$gl_sbiconf MMG$GL_SBICONF /* Holds the address of a longword */#define exe$gl_numnexus EXE$GL_NUMNEXUS /* Number of nexuses present on system. */#define mmg$gl_rmsbase \ MMG$GL_RMSBASE /* Base of RMS image */#define mmg$gl_fpemul_base MMG$GL_FPEMUL_BASE /* Base address of folating point */#define mmg$gl_sysloa_base MMG$GL_SYSLOA_BASE /* Base address of SYSLOAzzz.EXE */#define mmg$gl_vaxemul_base MMG$GL_\VAXEMUL_BASE /* Base address of decimal/string */#define mmg$gl_gblsecfnd MMG$GL_GBLSECFND /* Last global section table entry found */#define mmg$gl_gblpagfil MMG$GL_GBLPAGFIL /* page file allowed (remaining) for global sections */#define sch$gl_maxpix SCH$GL_MAXPIX \ /* Maximum process index */#define sch$gl_pixlast SCH$GL_PIXLAST /* Last process index created, used */#define sch$gl_pixwidth SCH$GL_PIXWIDTH /* Width of process index field in */#define sch$gw_localnode SCH$GW_LOCALNODE \ /* ID for local cluster node, used */#define pms$gl_dirio PMS$GL_DIRIO /* number of direct I/O operations */#define pms$gl_bufio PMS$GL_BUFIO /* number of buffered I/O operations */#define pms$gl_split PMS$GL_SPLIT \ /* number of split transfers */#define pms$gl_hit PMS$GL_HIT /* number of transfers not requiring */#define pms$gl_lognam PMS$GL_LOGNAM /* number of logical name translations */#define pms$gl_mbreads PMS$GL_MBREADS /* \ number of mailbox read operations */#define pms$gl_mbwrites PMS$GL_MBWRITES /* number of mailbox write operations */#define pms$gl_treads PMS$GL_TREADS /* number of terminal reads */#define pms$gl_twrites PMS$GL_TWRITES /* number \of terminal writes */#define pms$gl_iopfmpdb PMS$GL_IOPFMPDB /* address of performance data block */#define pms$gl_iopfmseq PMS$GL_IOPFMSEQ /* master I/O packet sequence number */#define pms$gl_arrlocpk PMS$GL_ARRLOCPK /* arriving local \packets */#define pms$gl_deplocpk PMS$GL_DEPLOCPK /* departing local packets */#define pms$gl_arrtrapk PMS$GL_ARRTRAPK /* arriving transit packets */#define pms$gl_trcnglos PMS$GL_TRCNGLOS /* transit congestion loss\ */#define pms$gl_rcvbuffl PMS$GL_RCVBUFFL /* receiver buffer failures */#define pms$gl_enqnew_loc PMS$GL_ENQNEW_LOC /* number of local new lock requests */#define pms$gl_enqnew_in PMS$GL_ENQNEW_IN /* number of incoming new lock req\uests */#define pms$gl_enqnew_out PMS$GL_ENQNEW_OUT /* number of outgoing new lock requests */#define pms$gl_enqcvt_loc PMS$GL_ENQCVT_LOC /* number of local conversion requests */#define pms$gl_enqcvt_in PMS$GL_ENQCVT_IN /* number of incoming conversion requests \ */#define pms$gl_enqcvt_out PMS$GL_ENQCVT_OUT /* number of outgoing conversion requests */#define pms$gl_deq_loc PMS$GL_DEQ_LOC /* number of local dequeues */#define pms$gl_deq_in PMS$GL_DEQ_IN /* number of incoming dequeues \ */#define pms$gl_deq_out PMS$GL_DEQ_OUT /* number of outgoing dequeues */#define pms$gl_enqwait PMS$GL_ENQWAIT /* number of $ENQ requests that wait */#define pms$gl_enqnotqd PMS$GL_ENQNOTQD /* number of $ENQ requests not queued \ */#define pms$gl_blk_loc PMS$GL_BLK_LOC /* number of local blocking ASTs queued */#define pms$gl_blk_in PMS$GL_BLK_IN /* number of incoming blocking ASTs queued */#define pms$gl_blk_out PMS$GL_BLK_OUT /* number of outgoing blocking ASTs queued \ */#define pms$gl_dir_in PMS$GL_DIR_IN /* number of incoming directory operations */#define pms$gl_dir_out PMS$GL_DIR_OUT /* number of outgoing directory operations */#define pms$gl_dlckmsgs_in PMS$GL_DLCKMSGS_IN /* number of incoming deadlock \ */#define pms$gl_dlckmsgs_out PMS$GL_DLCKMSGS_OUT /* number of outgoing deadlock */#define pms$gl_dlcksrch PMS$GL_DLCKSRCH /* number of deadlock searches performed */#define pms$gl_dlckfnd PMS$GL_DLCKFND /* number of deadlocks found */\#define pms$gl_flags PMS$GL_FLAGS /* Flags used in disk queue length code */#define pms$gl_qlen_scans PMS$GL_QLEN_SCANS /* No. of scans of IO data base */#define pms$gl_qlen_toint PMS$GL_QLEN_TOINT /* Timeout interval */#define \ pms$gl_qlen_toctr PMS$GL_QLEN_TOCTR /* Timeout down counter */#define pms$gl_sch_0_page PMS$GL_SCH_0_PAGE /* Pages created in idle loop */#define pms$gq_idle_loop PMS$GQ_IDLE_LOOP /* Passes through idle loop */#define pms$gl\_reserved1 PMS$GL_RESERVED1 /* Reserved for use by Digital */#define pms$gl_reserved2 PMS$GL_RESERVED2 /* Reserved for use by Digital */#define pms$gl_reserved3 PMS$GL_RESERVED3 /* Reserved for use by Digital */#define pms$gl_reserve\d4 PMS$GL_RESERVED4 /* Reserved for use by Digital */#define pms$gl_reserved5 PMS$GL_RESERVED5 /* Reserved for use by Digital */#define pms$gl_reserved6 PMS$GL_RESERVED6 /* Reserved for use by Digital */#define pms$gl_reserved7 \ PMS$GL_RESERVED7 /* Reserved for use by Digital */#define pms$gl_reserved8 PMS$GL_RESERVED8 /* Reserved for use by Digital */#define pms$gl_reserved9 PMS$GL_RESERVED9 /* Reserved for use by Digital */#define pms$gl_reserved10 \ PMS$GL_RESERVED10 /* Reserved for use by Digital */#define pms$gl_reserved11 PMS$GL_RESERVED11 /* Reserved for use by Digital */#define pms$gl_reserved12 PMS$GL_RESERVED12 /* Reserved for use by Digital */#define pms$gl_reserved13 P\MS$GL_RESERVED13 /* Reserved for use by Digital */#define pms$gl_reserved14 PMS$GL_RESERVED14 /* Reserved for use by Digital */#define pms$gl_reserved15 PMS$GL_RESERVED15 /* Reserved for use by Digital */#define pms$gl_reserved16 PMS$GL_RE\SERVED16 /* Reserved for use by Digital */#define pms$gl_reserved17 PMS$GL_RESERVED17 /* Reserved for use by Digital */#define pms$gl_reserved18 PMS$GL_RESERVED18 /* Reserved for use by Digital */#define pms$gl_chmk PMS$GL_CHMK \ /* number of CHMK system services */#define pms$gl_chme PMS$GL_CHME /* number of CHME system services */#define pms$gl_pages PMS$GL_PAGES /* number of pages of memory on configuration */#define pms$gw_batch PMS$GW_BATCH \ /* number of current batch jobs */#define pms$gw_intjobs PMS$GW_INTJOBS /* number of terminal users */#define pms$gl_readcnt PMS$GL_READCNT /* # of characters read. */#define pms$gl_wrtcnt PMS$GL_WRTCNT \ /* # of characters written. */#define pms$gl_passall PMS$GL_PASSALL /* # OF READS IN PASSALL MODE */#define pms$gl_rwp PMS$GL_RWP /* # OF READ WITH PROMPT READS */#define pms$gl_lrgrwp PMS$GL_LRGRWP /* #\ OF RWP > 12 CHARACTERS */#define pms$gl_rwpsum PMS$GL_RWPSUM /* # OF RWP CHARACTERS TOTAL */#define pms$gl_nostdtrm PMS$GL_NOSTDTRM /* # OF READS NOT USING STD TERMS. */#define pms$gl_rwpnostd PMS$GL_RWPNOSTD /* # OF RWP \NOT USING STANDARD TERMS */#define pms$gl_tty_code1 PMS$GL_TTY_CODE1 /* performance code vector 1 */#define pms$gl_tty_code2 PMS$GL_TTY_CODE2 /* performance code vector 2 */#define pms$gl_ldpctx PMS$GL_LDPCTX /* number of load pr\ocess context's */#define pms$gl_switch PMS$GL_SWITCH /* number of switches from current process */S#define pms$gb_prompt PMS$GB_PROMPT #define exe$ar_ewdata EXE$AR_EWDATA /* Pointer to the exec-writable page */#define pms$gl_dostats \ PMS$GL_DOSTATS /* FLAG TO TURN ON/OFF STATISTICS CODE */S#define sch$gq_comqs SCH$GQ_COMQS S#define sch$gq_comoqs SCH$GQ_COMOQS #define sch$gl_sip SCH$GL_SIP /* Swap in progress, etc. flags */#define sch$gb_rescan \ SCH$GB_RESCAN /* Flag byte for RELPFN to notify */#define mmg$gl_frewflgs MMG$GL_FREWFLGS /* Flags to control FREWSLE action */#define sch$gw_proccnt SCH$GW_PROCCNT /* Current count of processes */#define sch$gw_proclim \ SCH$GW_PROCLIM /* Maximum number of processes */#define swp$gl_slotcnt SWP$GL_SLOTCNT /* count of available swap slots */#define sch$gq_cebhd SCH$GQ_CEBHD /* Common event block header */#define sch$gw_cebcnt \ SCH$GW_CEBCNT /* number of common event blocks */#define sch$gw_delphdct SCH$GW_DELPHDCT /* Count of headers with delete pending */#define swp$gl_shell SWP$GL_SHELL /* Shell process swap address */#define swp$gl_inpcb SWP$G\L_INPCB /* PCB address of inswap process */#define swp$gl_ispagcnt SWP$GL_ISPAGCNT /* Inswap page count */#define swp$gw_ibalsetx SWP$GW_IBALSETX /* Inswap balance set index */#define swp$gb_iswpri SWP$GB_ISWPRI\ /* Inswap process priority */#define swp$gl_iswppages SWP$GL_ISWPPAGES /* Count of inswapped pages */#define swp$gl_iswpcnt SWP$GL_ISWPCNT /* Count of inswaps performed */#define swp$gl_oswpcnt SWP$GL_OSWPCNT \ /* Count of outswaps performed */#define swp$gl_hoswpcnt SWP$GL_HOSWPCNT /* Count of header outswaps */#define swp$gl_hiswpcnt SWP$GL_HISWPCNT /* Count of header inswaps */S#define swp$gl_map SWP$GL_MAP \ #define sch$gl_resmask SCH$GL_RESMASK /* Resource wait bit vector */#define exe$gl_flags EXE$GL_FLAGS /* System control flags */#define exe$gl_state_flags EXE$GL_STATE_FLAGS /* State of the system control flags */\S#define exe$aq_erlmbx EXE$AQ_ERLMBX S#define exe$gl_vaxexcvec EXE$GL_VAXEXCVEC S#define exe$gl_fpexcvec EXE$GL_FPEXCVEC #define exe$gl_usrchmk EXE$GL_USRCHMK /* Vector to user supplied change mode */#define exe$gl_usrchme EXE$GL_USRCHME \ /* Vector to user supplied change mode */#define swi$gl_fqfl SWI$GL_FQFL /* Forward link */#define swi$gl_fqbl SWI$GL_FQBL /* Backward link */#define lnm$aq_mutex LNM$AQ_MUTEX /* Lo\gical name mutex */#define lnm$gl_sysdirseq LNM$GL_SYSDIRSEQ /* System directory modification counter */#define exe$gl_sysucb EXE$GL_SYSUCB /* Address of the system device ucb */#define fil$gt_dddev FIL$GT_DDDEV /* File read \default device string */#define fil$gt_topsys FIL$GT_TOPSYS /* ASCIC top level dir string */#define fil$gq_cache FIL$GQ_CACHE /* File read cache descriptor */#define exe$gq_bootcb_d EXE$GQ_BOOTCB_D /* Descriptor for boo\t control block */#define exe$gl_bootcb EXE$GL_BOOTCB /* Address of boot control block */#define exe$gl_savedump EXE$GL_SAVEDUMP /* Block count to release to page file */#define exe$gl_erasepb EXE$GL_ERASEPB /* Address of a page-aligned \EPB of zeros */#define exe$gl_eraseppt EXE$GL_ERASEPPT /* Address of a PPT that maps the EPB */#define net$gl_diag_buf NET$GL_DIAG_BUF /* Network diagnostic tool common buffer address */S#define exe$gq_pqbiq EXE$GQ_PQBIQ #define ioc$gl_aqblist \ IOC$GL_AQBLIST /* Single link, empty */S#define ioc$gq_mountlst IOC$GQ_MOUNTLST #define ioc$gq_brdcst IOC$GQ_BRDCST /* Empty */#define ioc$gl_crbtmout IOC$GL_CRBTMOUT /* Empty \ */S#define ioc$gl_du_cddb IOC$GL_DU_CDDB S#define ioc$gl_tu_cddb IOC$GL_TU_CDDB S#define ioc$gl_hirt IOC$GL_HIRT S#define ioc$gl_shdw_wrk IOC$GL_SHDW_WRK #define exe$gl_gsdgrpfl EXE$GL_GSDGRPFL /* Forward link \ */#define exe$gl_gsdgrpbl EXE$GL_GSDGRPBL /* Backward link */#define exe$gl_gsdsysfl EXE$GL_GSDSYSFL /* Forward link */#define exe$gl_gsdsysbl EXE$GL_GSDSYSBL /* Backward link \ */#define exe$gl_gsddelfl EXE$GL_GSDDELFL /* Forward link */#define exe$gl_gsddelbl EXE$GL_GSDDELBL /* Backward link */#define exe$gq_wcbdeliq EXE$GQ_WCBDELIQ /* Forward link \ */#define exe$gq_syswcbiq EXE$GQ_SYSWCBIQ /* Forward link */#define ioc$gq_postiq IOC$GQ_POSTIQ /* Interlocked queue */#define exe$gq_rightslist EXE$GQ_RIGHTSLIST /* Null descriptor, no flag set \ */#define pms$gl_kernel PMS$GL_KERNEL /* Time in kernel mode */#define pms$gl_exec PMS$GL_EXEC /* Time in executive move */#define pms$gl_super PMS$GL_SUPER /* Time in supervisor mode \ */#define pms$gl_user PMS$GL_USER /* Time in user mode */#define pms$gl_inter PMS$GL_INTER /* Time on interrupt stack */#define pms$gl_compat PMS$GL_COMPAT /* Time in compatibility mode \ */#define exe$gl_abstim EXE$GL_ABSTIM /* Absolute time in seconds */#define exe$gq_systime EXE$GQ_SYSTIME /* System absolute time in nanoseconds */#define exe$gq_boottime EXE$GQ_BOOTTIME /* Define EXE$GQ_TODCBASE at last boot */\#define exe$gl_systick EXE$GL_SYSTICK /* Amount to be added to EXE$GQ_SYSTIME */#define exe$gl_tickwidth EXE$GL_TICKWIDTH /* Size of tick interval in 100ns units */#define exe$gl_clock_drift EXE$GL_CLOCK_DRIFT /* Amount of drift by the local clock */#define \ exe$gl_soft_tick EXE$GL_SOFT_TICK /* Initial hw ticks = 10ms soft */#define exe$gl_time_deviation EXE$GL_TIME_DEVIATION /* Initial deviation from real 10ms */#define exe$gl_timeadjust EXE$GL_TIMEADJUST /* Number of ticks necessary to adjust */#define exe$gl\_tickadjust EXE$GL_TICKADJUST /* Tick adjustment */#define exe$gl_ticklength EXE$GL_TICKLENGTH /* Total length of a tick */#define exe$gl_dtssflags EXE$GL_DTSSFLAGS /* DTSS (Time service) flags */#define exe$gl_pfatim \ EXE$GL_PFATIM /* Duration of last power failure */#define ioc$gq_mutex IOC$GQ_MUTEX /* Mutex for IOC data base */#define exe$gl_cebmtx EXE$GL_CEBMTX /* Mutex for common event cluster list */#define smp$gq_cpu_mutex \ SMP$GQ_CPU_MUTEX /* Special mutex to freeze active CPU set */#define exe$gl_pgdynmtx EXE$GL_PGDYNMTX /* Paged dynamic memory mutex */#define exe$gl_gsdmtx EXE$GL_GSDMTX /* Global section descriptor mutex */#define exe$gl_enqmtx \ EXE$GL_ENQMTX /* ENQUEUE/DEQUEUE tables mutex */#define exe$gl_aclmtx EXE$GL_ACLMTX /* ACL modification mutex */#define exe$gl_sysid_lock EXE$GL_SYSID_LOCK /* Start with no parent lock id */#define exe$gl_known_files E\XE$GL_KNOWN_FILES /* Pointer to known file entry */#define ctl$gq_ims_counter CTL$GQ_IMS_COUNTER /* count of inner mode semaphore acquires */#define sys$gq_version SYS$GQ_VERSION /* */#define sys$gl_ijobcnt SYS$GL_IJ\OBCNT /* Current count of interactive logins */#define sys$gl_njobcnt SYS$GL_NJOBCNT /* Current count of network logins */#define sys$gl_bjobcnt SYS$GL_BJOBCNT /* Current count of batch logins */#define exe$gl_sysmsg EXE$GL_SYSMSG \ /* Obsolete address of system-wide messages */#define exe$gl_msgvec EXE$GL_MSGVEC /* New address of system-wide messages */#define exe$gl_usrundwn EXE$GL_USRUNDWN /* Vector for system-wide rundown */#define exe$gl_nonpaged EXE$GL_NONPAGED \ /* address of first free block */#define exe$gl_paged EXE$GL_PAGED /* Address of first free block */#define exe$gl_shblist EXE$GL_SHBLIST /* Shared memory control blocks */#define exe$gl_rtbitmap EXE$GL_RTBITMAP \ /* Realtime SPT bit map. */#define exe$gl_mchkerrs EXE$GL_MCHKERRS /* Count of machine checks since boot */#define exe$gl_memerrs EXE$GL_MEMERRS /* Count of memory errors since boot */#define io$gl_uba_int0 IO$GL_UBA_INT0 /* Co\unter for UBA interrups thru vector 0 */#define io$gl_unexp_xmi_intr IO$GL_UNEXP_XMI_INTR /* Counter for unexpected XMI interrupts */#define io$gl_unexp_fbus_intr IO$GL_UNEXP_FBUS_INTR /* Counter for unexpected FBUS interrupts */#define io$gl_scb_int0 IO$GL_SCB_INT0 /* Counter fo\r unexpected SCB interrupts */#define exe$gl_tenusec EXE$GL_TENUSEC /* No. of times loop executes in 10 u-sec. */#define exe$gl_ubdelay EXE$GL_UBDELAY /* # of times to loop to delay 3 usec. */#define exe$gl_mp EXE$GL_MP /* Pointer to MP code\ */#define exe$gl_sitespec EXE$GL_SITESPEC /* Site specific longword */#define lck$ar_compat_tbl LCK$AR_COMPAT_TBL /* Address of Lock mode compatibility table */#define lck$gq_idtbl LCK$GQ_IDTBL /* Address of lock id table \ */#define lck$gl_nxtid LCK$GL_NXTID /* Next lock id to use */#define lck$gl_maxid LCK$GL_MAXID /* Max. lock id */#define lck$gl_htblcnt LCK$GL_HTBLCNT /* Number of entries in hash table \ */#define lck$gl_dirvec LCK$GL_DIRVEC /* Address of directory vector */#define lck$gl_prcmap LCK$GL_PRCMAP /* Address of process bitmap */#define lck$gq_bitmap_exp LCK$GQ_BITMAP_EXP /* Process bitmap expiration timestamp \ */#define lck$gq_bitmap_explcl LCK$GQ_BITMAP_EXPLCL /* Process bitmap expiration timestamp */#define lck$gq_debug LCK$GQ_DEBUG /* Reserved quadword for lock manager debug use */#define lck$gl_maxdepth LCK$GL_MAXDEPTH /* Maximum depth of resource names \ */#define lck$gl_stallreqs LCK$GL_STALLREQS /* Stall lock requests flag */#define lck$gl_rebld_state LCK$GL_REBLD_STATE /* Lock rebuild state: */#define exe$gl_acmflags EXE$GL_ACMFLAGS /* Accounting manager control flags \ */#define exe$gl_svapte EXE$GL_SVAPTE /* SVAPTE for PTE that maps blakhole page */#define xqp$gl_sections XQP$GL_SECTIONS /* Count of global sections */#define xqp$gl_dzro XQP$GL_DZRO /* Size of dzro section \ */#define xqp$gl_fileserver XQP$GL_FILESERVER /* Pid of server process */#define xqp$gl_fileserv_entry XQP$GL_FILESERV_ENTRY /* AST entry point of process */#define sys$gq_pwd SYS$GQ_PWD /* System password \ */#define cia$gl_mutex CIA$GL_MUTEX /* Initial count of -1 */#define cia$gq_intruder CIA$GQ_INTRUDER /* Set flink, blink */#define exe$gl_badacv_t EXE$GL_BADACV_T /* Time of the last bad accvio */#d\efine exe$gl_badacv_c EXE$GL_BADACV_C /* Count of bad accvios */#define exe$exceptable EXE$EXCEPTABLE /* Pointer to exception table */#define smp$ar_spnlkvec SMP$AR_SPNLKVEC /* Address of spinlock vector */#define \smp$gw_spnlkcnt SMP$GW_SPNLKCNT /* Number of entries in spinlock vector */#define smp$gw_min_index SMP$GW_MIN_INDEX /* Value of first spinlock index */#define exe$gq_1st_time EXE$GQ_1ST_TIME /* Expiration time for first TQE */#define smp$gl_c\puconf SMP$GL_CPUCONF /* Bitmask of available CPUs */#define smp$gl_active_cpus SMP$GL_ACTIVE_CPUS /* Bitmask of members of 'active' set */#define smp$gl_override SMP$GL_OVERRIDE /* Bitmask of members of 'override' set */#define smp$gl_tbi_ack_m\ask_mmg SMP$GL_TBI_ACK_MASK_MMG /* Bitmask of CPUs to wait for TBI ACK */#define smp$gl_tbi_ack_mask SMP$GL_TBI_ACK_MASK /* Bitmask of CPUs to wait for TBI ACK */#define smp$gl_astsr_ack SMP$GL_ASTSR_ACK /* Bit to wait for ASTSR ACK */#define smp$gl_bug_done \ SMP$GL_BUG_DONE /* Bitmask of CPUs that have completed per-CPU state saving during BUGCHECK */#define smp$gq_invalid_mmg SMP$GQ_INVALID_MMG /* Address of VA to invalidate TB with */#define smp$gq_invalid SMP$GQ_INVALID /* Address of VA to invalidate TB with */#define smp$gl_flags \ SMP$GL_FLAGS /* SMP control flags */#define smp$gl_bugchkcp SMP$GL_BUGCHKCP /* ID of CPU initiating BUGCHECK (CRASH CPU) */#define smp$gl_primid SMP$GL_PRIMID /* PRIMARY CPU ID - Can be used to locate */#define smp$gl_cpu_data SMP\$GL_CPU_DATA /* per-CPU Database vector */#define smp$gq_proposed_hwclock SMP$GQ_PROPOSED_HWCLOCK /* proposed new value for TODRs */#define smp$gq_new_hwclock SMP$GQ_NEW_HWCLOCK /* most recent contents of primary */#define xdt$gl_interlock XDT$GL_INTE\RLOCK /* XDELTA entry interlock (low bit) */#define xdt$gl_owner_id XDT$GL_OWNER_ID /* CPU ID of XDELTA owner */#define xdt$gl_benign_cpus XDT$GL_BENIGN_CPUS /* Mask of CPUs in benign state */#define xdt$gl_scb XDT$GL_SCB \ /* XDELTA private SCB page */#define clu$gb_cluver CLU$GB_CLUVER /* cluster version number */#define exe$gq_bugcheck_exclude_pfn EXE$GQ_BUGCHECK_EXCLUDE_PFN /* PFN not to be written in dump */S#define mmg$gl_dzro_pte MMG$GL_DZRO_PTE \ S#define mmg$gl_dzro_va MMG$GL_DZRO_VA #define exe$gl_abstim_tics EXE$GL_ABSTIM_TICS /* Absolute time in 10 ms tics */#define pms$gl_npagdynexps PMS$GL_NPAGDYNEXPS /* Count of successful attempts to */#define pms$gl_npagdynexpf PMS$GL_NPAGDYNEXPF \ /* Count of unsuccessful attempts to */#define pms$gl_pagdynf PMS$GL_PAGDYNF /* Count of paged pool */#define pms$gl_proccntmax PMS$GL_PROCCNTMAX /* Maximum no. of concurrent processes */#define sch$al_cpu_cap SCH$AL_CPU_CAP /\* Array of capabilities held by each CPU. */#define smp$gw_affinity_count SMP$GW_AFFINITY_COUNT /* Per capability count of */#define exe$ga_les_table EXE$GA_LES_TABLE /* Address of main LES data structure */#define exe$gl_affinity EXE$GL_AFFINITY /* Defau\lt device affinity value */#define exe$gl_tmv_svapte EXE$GL_TMV_SVAPTE /* SVA of first PTE used to map */#define exe$gl_tmv_svabuf EXE$GL_TMV_SVABUF /* SVA of 1024 byte area in system */S#define exe$ga_wp_cre EXE$GA_WP_CRE S#define exe$\ga_wp_del EXE$GA_WP_DEL S#define exe$ga_wp_wpre EXE$GA_WP_WPRE S#define exe$ga_hwname EXE$GA_HWNAME S#define exe$ga_hwtype EXE$GA_HWTYPE #define exe$gl_usrundwn_exec EXE$GL_USRUNDWN_EXEC /* Vector for system-wide rundown */S#define \sys$gl_version SYS$GL_VERSION #define sys$version_begin SYS$VERSION_BEGIN /* Alternative symbol for SYSBOOT */S#define lmf$gl_reserved LMF$GL_RESERVED S#define clu$gw_quorum CLU$GW_QUORUM #define pms$gl_npagdynf PMS$GL_NPAGDYNF /* Count\ of non-paged pool failure epochs */#define pms$gl_npagdynfpages PMS$GL_NPAGDYNFPAGES /* Failed PAGES accumulator */#define pms$gl_pagdynfpages PMS$GL_PAGDYNFPAGES /* Failed PAGES accumulator */#define pms$gl_npagdynreq PMS$GL_NPAGDYNREQ /* Non-paged poo\l allocation requests */#define pms$gl_npagdynreqf PMS$GL_NPAGDYNREQF /* Non-paged pool allocation requests */#define pms$gl_pagdynreq PMS$GL_PAGDYNREQ /* Paged pool allocation requests */#define pms$gl_pagdynreqf PMS$GL_PAGDYNREQF /* Paged pool allocation\ requests */#define pms$gl_xrpfail PMS$GL_XRPFAIL /* xRP lookaside list allocation failures */S#define sys$gl_uis_flags SYS$GL_UIS_FLAGS S#define sys$gl_uisbg_epid SYS$GL_UISBG_EPID S#define uis$gl_ltrc_buf UIS$GL_LTRC_BUF S#define uis$gl_ltrc_en\d UIS$GL_LTRC_END S#define uis$gl_ltrc_ptr UIS$GL_LTRC_PTR S#define uis$gl_ltrc_spare UIS$GL_LTRC_SPARE S#define sch$aq_comh SCH$AQ_COMH S#define sch$aq_comt SCH$AQ_COMT S#define sch$aq_comoh SCH$AQ_COMOH S#define sch$\aq_comot SCH$AQ_COMOT S#define sch$aq_wqhdr SCH$AQ_WQHDR S#define sch$gq_colpgwq SCH$GQ_COLPGWQ S#define sch$gq_mwait SCH$GQ_MWAIT S#define sch$gq_pfwq SCH$GQ_PFWQ S#define sch$gq_lefwq SCH$GQ_LEFWQ S#def\ine sch$gq_lefowq SCH$GQ_LEFOWQ S#define sch$gq_hibwq SCH$GQ_HIBWQ S#define sch$gq_hibowq SCH$GQ_HIBOWQ S#define sch$gq_susp SCH$GQ_SUSP S#define sch$gq_suspo SCH$GQ_SUSPO S#define sch$gq_fpgwq SCH$GQ_FPGWQ \ #define pms$al_transflt PMS$AL_TRANSFLT /* Page faults out of transition states */S#define pms$al_crfio PMS$AL_CRFIO S#define pms$al_crf PMS$AL_CRF #define nsa$ar_alarm_vector NSA$AR_ALARM_VECTOR /* Pointer to security alarm event vector \*/#define nsa$ar_audit_vector NSA$AR_AUDIT_VECTOR /* Pointer to security audit event vector */#define nsa$ar_alarm_failure NSA$AR_ALARM_FAILURE /* Pointer to security alarm failure vector */#define nsa$ar_audit_failure NSA$AR_AUDIT_FAILURE /* Pointer to security audit failure vector */#def\ine scs$ar_localsb SCS$AR_LOCALSB /* Pointer to the local system block */#define net$ar_wcb NET$AR_WCB /* Pointer to thenetwork window control block */#define mmg$ar_nullpfl MMG$AR_NULLPFL /* Pointer to the null pagefile structure */#define sc\h$ar_nullpcb SCH$AR_NULLPCB /* Pointer to the null PCB */#define sch$ar_swppcb SCH$AR_SWPPCB /* Pointer to the swapper PCB */#define mmg$ar_syspcb MMG$AR_SYSPCB /* Pointer to the system PCB (dummy, used for system paging) */#define exe$ar_upc]ase_dat EXE$AR_UPCASE_DAT /* Pointer to the upcase table */#define ioc$gl_devlist IOC$GL_DEVLIST /* DDB list head. There is also */S#define mb$ar_ddb MB$AR_DDB S#define mb$ar_orb1 MB$AR_ORB1 S#define mb$ar_orb2 ] MB$AR_ORB2 S#define mb$ar_ucb1 MB$AR_UCB1 S#define sys$ar_jobctlmb SYS$AR_JOBCTLMB S#define mb$ar_ucb2 MB$AR_UCB2 S#define sys$ar_oprmbx SYS$AR_OPRMBX S#define mb$ar_orb0 MB$AR_ORB0 S#define mb]$ar_ucb0 MB$AR_UCB0 S#define nl$ar_ddb NL$AR_DDB S#define nl$ar_orb0 NL$AR_ORB0 S#define nl$ar_ucb0 NL$AR_UCB0 S#define opa$ar_ddb OPA$AR_DDB S#define opa$ar_orb0 OPA$AR_ORB0 S#d]efine opa$ar_ucb0 OPA$AR_UCB0 S#define opa$ar_crb OPA$AR_CRB S#define op$ar_dpt OP$AR_DPT S#define opa$ar_spl OPA$AR_SPL S#define opa$ar_idb OPA$AR_IDB S#define arch$gq_ptolemy_cell ARCH$GQ_PTOLEMY_CELL ] S#define swp$gl_shellbas SWP$GL_SHELLBAS S#define swp$gl_shellpfil SWP$GL_SHELLPFIL S#define lnm$al_hashtbl LNM$AL_HASHTBL S#define lnm$al_dirtbl LNM$AL_DIRTBL S#define sch$gl_swppid SCH$GL_SWPPID #define swp$al_swapper_stack SWP$AL_SWAPPER_STACK ] /* Pointer to the swapper's stack */#define swp$gl_swapper_stack_size SWP$GL_SWAPPER_STACK_SIZE /* Size of swapper's stack */S#define sys$ar_bootucb SYS$AR_BOOTUCB S#define sys$ar_bootorb SYS$AR_BOOTORB S#define sys$ar_bootddb SYS$AR_BOOTDDB ] #define exe$ar_uafc_hash_table EXE$AR_UAFC_HASH_TABLE /* Address of UAF record hash table */#define exe$ar_arbc_hash_table EXE$AR_ARBC_HASH_TABLE /* Address of security profile hash table */S#define exe$gl_hwname_length EXE$GL_HWNAME_LENGTH S#define exe$gl_hwtype_length EXE$GL_HWTYPE_LENGTH ] S#define smp$al_iplvec SMP$AL_IPLVEC #define exe$ar_tqenorept EXE$AR_TQENOREPT /* initialized in timeschdl.mar */S#define exe$gl_saved_embs EXE$GL_SAVED_EMBS S#define exe$gw_saved_embs_count EXE$GW_SAVED_EMBS_COUNT S#define opa$ar_vector OPA$AR_VECTOR ] S#define sys$gw_mbxucbsiz SYS$GW_MBXUCBSIZ S#define exe$al_erlbufadr EXE$AL_ERLBUFADR S#define exe$gw_erlbufhead EXE$GW_ERLBUFHEAD S#define exe$gw_erlbuftail EXE$GW_ERLBUFTAIL #define exe$gl_tqfl EXE$GL_TQFL /* Flink and Blink initialized to point  ] */#define exe$gq_kfe_lcknam EXE$GQ_KFE_LCKNAM /* install utility initialized in */#define exe$gl_brkmsk EXE$GL_BRKMSK /* executive that are allowed to */S#define clu$gb_quorum_lost CLU$GB_QUORUM_LOST S#define exe$gl_xpca EXE$GL_XPCA  ] #define sch$gl_idle_cpus SCH$GL_IDLE_CPUS /* LW bitmask of idle CPUs */#define sch$gq_idle_cpus SCH$GQ_IDLE_CPUS /* QW bitmask of idle CPUs */#define decw$gl_vector DECW$GL_VECTOR /* Longword address of a vector  ] */S#define exe$gw_clkutics EXE$GW_CLKUTICS S#define exe$gw_clkuticr EXE$GW_CLKUTICR #define exe$gl_abstim_utics EXE$GL_ABSTIM_UTICS /* Absolute time in utics */#define lmf$ar_grouptbl LMF$AR_GROUPTBL /* Address of LMF group name table  ] */#define exe$ar_dumpdev_validation_data EXE$AR_DUMPDEV_VALIDATION_DATA /* Pointer to area filled in by SYSINIT */#define exe$gl_dumpmask EXE$GL_DUMPMASK /* dumps and dumps generated directly */#define vms$gl_license_version VMS$GL_LICENSE_VERSION /* License version number */ ]#define vms$gq_license_date VMS$GQ_LICENSE_DATE /* License date */#define exe$gl_ns_flags EXE$GL_NS_FLAGS /* Misc flags longword */#define exe$gl_mmg_flags EXE$GL_MMG_FLAGS /* Misc flags longword */#defin]e net$gl_atm_rcvpkt NET$GL_ATM_RCVPKT /* ATM Receive Packet Callout Address */#define net$gl_atm_xmtpkt NET$GL_ATM_XMTPKT /* ATM Transmit Packet Callout Address */#define net$gl_atm_fwdpkt NET$GL_ATM_FWDPKT /* ATM Forward Packet Callout Address */#define smp$]gl_pfork_pool SMP$GL_PFORK_POOL /* VA of dedicated pool for high-IPL */#define smp$gb_pfork_pool_size SMP$GB_PFORK_POOL_SIZE /* size in pages of PFORK_POOL */#define sch$gl_default_process_cap SCH$GL_DEFAULT_PROCESS_CAP /* default capabilities */#define sch$gl_defau]lt_cpu_cap SCH$GL_DEFAULT_CPU_CAP /* default capabilities */#define sch$ar_cap_priv SCH$AR_CAP_PRIV /* pointer to array */S#define sch$gq_active_priority SCH$GQ_ACTIVE_PRIORITY #define sch$gl_cpu_cap_sum SCH$GL_CPU_CAP_SUM /* summary of all ] */#define ddtm$ar_performance_cells DDTM$AR_PERFORMANCE_CELLS /* Base of DDTM performance cells */#define exe$ar_powerdwn_done EXE$AR_POWERDWN_DONE /* Address of powerfail done mask */#define net$gq_ctf_wrk_q NET$GQ_CTF_WRK_Q /* Network Common Trace Facility (]CTF) */#define net$gq_ctf_reg_q NET$GQ_CTF_REG_Q /* Network Common Trace Facility (CTF) */#define pms$gl_gblsectcnt PMS$GL_GBLSECTCNT /* Current no. of mapped global sections */#define pms$gl_gblsectmax PMS$GL_GBLSECTMAX /* Maximum no. of mapped global pages ] */#define pms$gl_gblpagcnt PMS$GL_GBLPAGCNT /* Current no. of mapped global pages */#define pms$gl_gblpagmax PMS$GL_GBLPAGMAX /* Maximum no. of mapped global pages */#define sys$gl_exitret SYS$GL_EXITRET /* Return address if $EXIT service ] */#define pms$gl_cwps_msgs_in PMS$GL_CWPS_MSGS_IN /* Count of CWPS messages */#define pms$gl_cwps_msgs_out PMS$GL_CWPS_MSGS_OUT /* Count of CWPS messages */#define pms$gl_cwps_bytes_in PMS$GL_CWPS_BYTES_IN /* Count of CWPS bytes input ] */#define pms$gl_cwps_bytes_out PMS$GL_CWPS_BYTES_OUT /* Count of CWPS bytes output */#define pms$gl_cwps_getjpi_in PMS$GL_CWPS_GETJPI_IN /* Count of inbound $GETJPI */#define pms$gl_cwps_getjpi_out PMS$GL_CWPS_GETJPI_OUT /* Count of outbount $GETJPI ] */#define pms$gl_cwps_pcntrl_in PMS$GL_CWPS_PCNTRL_IN /* Count of inbound PCNTRL */#define pms$gl_cwps_pcntrl_out PMS$GL_CWPS_PCNTRL_OUT /* Count of outbount PCNTRL */#define pms$gl_cwps_rsrc_send PMS$GL_CWPS_RSRC_SEND /* Count of resource fail sent ] */#define pms$gl_cwps_rsrc_recv PMS$GL_CWPS_RSRC_RECV /* Count of resource fail rec'd */#define mb$ar_ucb3 MB$AR_UCB3 /* address of UCB for audit server mailbox */#define mb$ar_orb3 MB$AR_ORB3 /* address of ORB for audit server mailbox */]#define sys$ar_audsrvmbx SYS$AR_AUDSRVMBX /* address of UCB for audit server mailbox */#define exe$gl_xmi_nexus_array EXE$GL_XMI_NEXUS_ARRAY /* address of array containing XMI device types */#define exe$gl_xmi_csr_array EXE$GL_XMI_CSR_ARRAY /* address of array containing pointers to */#define ] exe$gl_xmi_structure_array EXE$GL_XMI_STRUCTURE_ARRAY /* address of array containing pointers to the */#define psx$gl_state PSX$GL_STATE /* POSIX state cell */#define psx$gl_posix PSX$GL_POSIX /* POSIX Pointer PXDSRR cell */#define psx$gl]_spare PSX$GL_SPARE /* POSIX spare cell */#define smp$gq_primary_workq SMP$GQ_PRIMARY_WORKQ /* Primary CPU's work queue. */#define pms$gl_rm_quota_wait PMS$GL_RM_QUOTA_WAIT /* No quota for operation */#define pms$gl_rm_unlo]ad PMS$GL_RM_UNLOAD /* Tree moved to another node */#define pms$gl_rm_acquire PMS$GL_RM_ACQUIRE /* Tree moved to this node */#define pms$gl_rm_finish PMS$GL_RM_FINISH /* Operation completed */#define pms$gl_rm_req_nak ] PMS$GL_RM_REQ_NAK /* Proposed new manager declines */#define pms$gl_rm_msg_sent PMS$GL_RM_MSG_SENT /* Remaster messages sent */#define pms$gl_rm_msg_rcv PMS$GL_RM_MSG_RCV /* Remaster messages received */#define pms$gl_rm_rbld_sent ] PMS$GL_RM_RBLD_SENT /* Remaster rebuild msgs sent */#define pms$gl_rm_rbld_rcvd PMS$GL_RM_RBLD_RCVD /* Remaster rebuild msgs received */#define lck$gl_dlck_incmplt LCK$GL_DLCK_INCMPLT /* Deadlock search incomplete */#define net$gq_ctf_tb_q N]ET$GQ_CTF_TB_Q /* Network Common Trace Facility (CTF) */#define exe$gq_basimgmtx EXE$GQ_BASIMGMTX /* Base image mutex */#define exe$gl_ldr_seq EXE$GL_LDR_SEQ /* Count of exec loaded images */#define exe$gl_ldr_cnt EXE$GL_LD]R_CNT /* Loaded image queue sequence number */#define ioc$gl_interrupts IOC$GL_INTERRUPTS /* CPUs that accept I/O interrupts */#define exe$gl_num_xmi_nexus EXE$GL_NUM_XMI_NEXUS /* Cell containing number of active */#define net$ar_debug_vector NET$AR_DEBUG_VECT ]OR /* Pointer to DEBUG's vector */#define exe$ga_les_vector EXE$GA_LES_VECTOR /* Pointer to LES' vector */#define net$ar_ctf_vector NET$AR_CTF_VECTOR /* Pointer to CTF's vector */#define net$ar_emaa_vector NET$AR_EMAA_VECTOR !] /* Pointer to EMAA's vector */#define net$ar_lan_vector NET$AR_LAN_VECTOR /* Pointer to LAN's vector */#define net$ar_nrl_vector NET$AR_NRL_VECTOR /* Pointer to NRL's vector */#define net$ar_nbi_vector NET$AR_NBI_VECTOR "] /* Pointer to the network base */#define net$gl_nsa_fwdpkt NET$GL_NSA_FWDPKT /* Address of network forwarding */#define exe$gl_ft_flags EXE$GL_FT_FLAGS /* Fault Tolerant State flags */#define exe$gl_sys_specific EXE$GL_SYS_SPECIFIC /* C#]PU support */#define exe$gl_snap_sequence EXE$GL_SNAP_SEQUENCE /* Process notification sequence */#define exe$gl_snap_state EXE$GL_SNAP_STATE /* State bits (see $SNAPSTATEDEF) */#define exe$ar_snap_vector EXE$AR_SNAP_VECTOR /* Process n$]otification vector */#define exe$gq_snap_fork_list EXE$GQ_SNAP_FORK_LIST /* Queue for fork process notification */#define exe$gl_snap_pid EXE$GL_SNAP_PID /* Owning process PID */#define exe$gl_snap_fork_vector EXE$GL_SNAP_FORK_VECTOR /* Fork process noti%]fication table */#define lck$gl_stallfl LCK$GL_STALLFL /* Stalled locks */#define exe$gl_hbs_ptr EXE$GL_HBS_PTR /* Pointer to HBS Dispatcher */#define exe$gl_hbs_cip EXE$GL_HBS_CIP /* Number of HBS copies &] */#define scs$gb_log SCS$GB_LOG /* Event log enable/disable flag */#define scs$gl_available_port SCS$GL_AVAILABLE_PORT /* 32-bit SCS Load Share Port Bit Map. */#define scs$gl_load_share_interval SCS$GL_LOAD_SHARE_INTERVAL /* Repeat interval of a timer '] */#define scs$gl_load_share_pdt_table SCS$GL_LOAD_SHARE_PDT_TABLE /* Pointer to the PDT List */#define scs$gq_reuse_cdt SCS$GQ_REUSE_CDT /* Queue of reusable CDTs whose */#define scs$gq_disconnect SCS$GQ_DISCONNECT /* The queue list of CDTs for (] */#define scs$gq_worse_path SCS$GQ_WORSE_PATH /* A queue which keeps all worse */#define scs$gl_share_enable SCS$GL_SHARE_ENABLE /* 0 disables and 1 enables equal path */#define scs$gl_init_timeout SCS$GL_INIT_TIMEOUT /* Interval of the initial connection )] */#define scs$gl_min_port_wait_interval SCS$GL_MIN_PORT_WAIT_INTERVAL /* The amount of time to wait before the port is */#define scs$gl_min_conn_wait_interval SCS$GL_MIN_CONN_WAIT_INTERVAL /* The amount of time to wait before a connection */#define scs$gb_discon_limit SCS$GB_DISCON_LIMIT /* The maximum number of connections that *] */#define scs$gw_next_index SCS$GW_NEXT_INDEX /* Next SCS local process index to be */#define scs$gq_local_names SCS$GQ_LOCAL_NAMES /* Queue of SCS Load Share Name Blocks */#define pdp$gl_status PDP$GL_STATUS /* and number of active threads +] */S#define pdp$ga_cntrlblk PDP$GA_CNTRLBLK #define scs$gl_red_threshold SCS$GL_RED_THRESHOLD /* The percentage of the port saturation */#define scs$gl_yellow_threshold SCS$GL_YELLOW_THRESHOLD /* The percentage of the port saturation */#define scs$gl_tolerance SCS$GL_TOLERANCE ,] /* The percentage of the port saturation */S#define cache$gl_state CACHE$GL_STATE #define exe$gq_limboq EXE$GQ_LIMBOQ /* Queue header for queue */S#define exe$gl_limbolen EXE$GL_LIMBOLEN S#define exe$gl_limbomax EXE$GL_LIMBOMAX -] S#define exe$gl_limbothr EXE$GL_LIMBOTHR #define ioc$gl_ens_base IOC$GL_ENS_BASE /* Pointer to generalized event */#define ioc$gl_event_database IOC$GL_EVENT_DATABASE /* Pointer to generalized event */#define exe$gl_dtssptr EXE$GL_DTSSPTR .] /* Pointer to DTSS data storage */#define sevms$ar_alarm_vector SEVMS$AR_ALARM_VECTOR /* SeVMS alarm vector */#define sevms$ar_audit_vector SEVMS$AR_AUDIT_VECTOR /* SeVMS audit vector */#define sevms$gl_flags SEVMS$GL_FLAGS /* /] SeVMS flags */S#define clu$gl_join_tblstart CLU$GL_JOIN_TBLSTART S#define clu$gl_remov_tblstart CLU$GL_REMOV_TBLSTART #define exe$gl_dnsptr EXE$GL_DNSPTR /* Pointer to DNS data storage */S#define lck$gl_act_thrsh LCK$GL_ACT_THRSH S#d0]efine lck$gl_sys_thrsh LCK$GL_SYS_THRSH S#define lck$gl_activity LCK$GL_ACTIVITY S#define pms$gl_rm_single PMS$GL_RM_SINGLE S#define pms$gl_rm_better PMS$GL_RM_BETTER S#define pms$gl_rm_more_act PMS$GL_RM_MORE_ACT S#define lck$gl_flags LCK$GL_FLAGS 1] #define sch$gw_maxpixseq SCH$GW_MAXPIXSEQ /* Maximum process index */#define mpw$ar_perfstats MPW$AR_PERFSTATS /* Address of performance */#define exe$ar_ftss_vectors EXE$AR_FTSS_VECTORS /* Pointer to the FTSS execlet */2]#define net$gq_node_param NET$GQ_NODE_PARAM /* Node parameter information */#define sch$gl_transient_capabilities SCH$GL_TRANSIENT_CAPABILITIES /* Cell to hold transient */#define qman$ar_qdbtable QMAN$AR_QDBTABLE /* Pointer to QDB table */#define 3] qman$gl_mutex QMAN$GL_MUTEX /* Mutex for Batch/Print */#define swp$gl_troll_time SWP$GL_TROLL_TIME /* Last Troll time */#define mmg$gl_reclaim_flags MMG$GL_RECLAIM_FLAGS /* Flags to control Ticker */#define net$ar4]_ssrv_vector NET$AR_SSRV_VECTOR /* Pointer to Session Service's */#define net$ar_emaa_ert NET$AR_EMAA_ERT /* Pointer to EMAA's Entity */#define net$ga_register_id NET$GA_REGISTER_ID /* Pointer to the routine used */#define exe$gl_decnet_5]version EXE$GL_DECNET_VERSION /* Version of DECnet-VAX */#define mmg$gl_page_size MMG$GL_PAGE_SIZE /* memory page size in bytes */#define mmg$gl_page_to_vbn MMG$GL_PAGE_TO_VBN /* Shift for page to VBN converts */#define mmg$gl_bwp_mask 6] MMG$GL_BWP_MASK /* mask for byte-within-page */S#define mmg$gl_va_to_vpn MMG$GL_VA_TO_VPN S#define mmg$gl_vpn_to_va MMG$GL_VPN_TO_VA S#define mmg$gl_va_to_pte_offset MMG$GL_VA_TO_PTE_OFFSET S#define mmg$gl_pte_offset_to_va MMG$GL_PTE_OFFSET_TO_VA #define mmg$gq_64p1_shift 7] MMG$GQ_64P1_SHIFT /* Memory management helper */#define mmg$gq_64sys_shift MMG$GQ_64SYS_SHIFT /* Memory management helper */#define cpu$gb_arch_type CPU$GB_ARCH_TYPE /* architecture type */#define cpu$gt_arch_name 8] CPU$GT_ARCH_NAME /* architecture name */#define clu$gl_club CLU$GL_CLUB /* address of the cluster block */#define clu$gl_clusvec CLU$GL_CLUSVEC /* address of cluster system vector */#define clu$gw_maxindex 9] CLU$GW_MAXINDEX /* maximum number of entries in system vector */S#define scs$gq_config SCS$GQ_CONFIG S#define scs$gq_direct SCS$GQ_DIRECT #define scs$gq_poll SCS$GQ_POLL /* List of SPPB's giving process names */S#define scs$gl_bdlt :] SCS$GL_BDLT S#define scs$gl_max_bdlt_index SCS$GL_MAX_BDLT_INDEX S#define scs$gl_cdl SCS$GL_CDL S#define scs$gl_rdt SCS$GL_RDT S#define scs$gl_mclen SCS$GL_MCLEN S#define scs$gl_mcadr SCS$GL_MCADR #define scs$gl_mscp ;] SCS$GL_MSCP /* Start of MSCP server process */#define scs$gl_mscp_mv SCS$GL_MSCP_MV /* MSCP server mount verification routine */#define scs$gl_mscp_newdev SCS$GL_MSCP_NEWDEV /* MSCP server new device handling */#define scs$gl_pdt <] SCS$GL_PDT /* Singly link list of PDT's */S#define scs$ga_exists SCS$GA_EXISTS S#define exe$gl_mvmslbas EXE$GL_MVMSLBAS S#define exe$ar_mchk_errcnt EXE$AR_MCHK_ERRCNT S#define exe$ar_mchk_blocks EXE$AR_MCHK_BLOCKS #define swp$gl_shellsiz =] SWP$GL_SHELLSIZ /* PAGES REQUIRED FOR SHELL */#define swp$gw_emptpte SWP$GW_EMPTPTE /* EMPTY PHDPAGES */#define swp$gw_wslpte SWP$GW_WSLPTE /* PHD PAGES FOR FIXED+WSL+PST */#define swp$gl_bslotsz S>]WP$GL_BSLOTSZ /* SIZE OF BALANCE SLOT */#define swp$gl_phdbasva SWP$GL_PHDBASVA /* BASE ADDRESS OF PHD WINDOW */#define sgn$gl_p1lwcnt SGN$GL_P1LWCNT /* COUNT OF LW TO END OF P1 PAGETABLE */#define mmg$gl_ctlbasva MMG$GL_CT?]LBASVA /* BASE ADDRESS IN CONTROL REGION */#define mmg$gl_sptbase MMG$GL_SPTBASE /* BASE ADDRESS OF SPT */#define mmg$gl_sysphd MMG$GL_SYSPHD /* VA OF SYSTEM PHD */#define swp$gl_balbase SWP$GL_BALBASE @] /* BASE VA OF BALANCE SLOTS FOR */#define swp$gl_balspt SWP$GL_BALSPT /* BASE VA IN SPT FOR MAPPING BALANCE */#define mmg$gl_sbr MMG$GL_SBR /* SYSTEM BASE REGISTER */#define mmg$gl_npagedyn MMG$GL_NPAGEDYN A] /* VA OF NON-PAGED POOL */#define mmg$gl_npagnext MMG$GL_NPAGNEXT /* NEXT VA FOR NON-PAGED POOL EXTENSION */#define mmg$gl_pagedyn MMG$GL_PAGEDYN /* VA OF PAGED POOL */#define exe$gl_scb EXE$GL_SCB B] /* VIRTUAL ADDRESS OF SCB */#define exe$gl_archflag EXE$GL_ARCHFLAG /* ARCHITECTURAL FLAGS (BITS DEFINED */#define exe$gl_state EXE$GL_STATE /* FLAGS BOOTSTRAP PROGRESS */#define exe$gl_scbpfn EXE$GL_SCBPFN /* SC]CB pfn */#define exe$gq_cputype EXE$GQ_CPUTYPE /* CPU TYPE FROM HWRPB */#define exe$gq_systype EXE$GQ_SYSTYPE /* SYSTEM TYPE FROM HWRPB */#define exe$gw_cpumodel EXE$GW_CPUMODEL /* CPU MODELD] NUMBER */S#define clu$gl_niscs_auth CLU$GL_NISCS_AUTH #define clu$gb_niscs_comm CLU$GB_NISCS_COMM /* NISCS communications region */#define clu$gq_niscs_auth CLU$GQ_NISCS_AUTH /* Authorization quadword */#define clu$gl_nE]iscs_group CLU$GL_NISCS_GROUP /* Group code */S#define clu$gs_niscs_comm CLU$GS_NISCS_COMM #define exe$gw_pgfl_fid EXE$GW_PGFL_FID /* FILE ID OF PAGEFILE.SYS */#define exe$gq_snap_bitmap EXE$GQ_SNAP_BITMAP /* Snapshot bad page bF]itmap descriptor */#define cache$gl_ptes CACHE$GL_PTES /* Number of PTES available to VBN cache */#define swp$gl_swap_image_size_max SWP$GL_SWAP_IMAGE_SIZE_MAX /* Maximum swap image size */#define exe$gl_sys_code_base EXE$GL_SYS_CODE_BASE /* SYS.EXE readonly address G] */#define exe$gl_sys_code_end EXE$GL_SYS_CODE_END /* SYS.EXE readonly end address */#define exe$gl_sys_data_base EXE$GL_SYS_DATA_BASE /* SYS.EXE read/write address */#define exe$gl_sys_data_end EXE$GL_SYS_DATA_END /* SYS.EXE read/write end address H] */#define exe$gl_sys_symvec EXE$GL_SYS_SYMVEC /* SYS.EXE's symbol vector addr. */#define exe$gl_sys_symvec_end EXE$GL_SYS_SYMVEC_END /* SYS.EXE's symbol vector end addr. */#define exe$gl_public_vector_symvec EXE$GL_PUBLIC_VECTOR_SYMVEC /* PUBLIC_VECTOR's sym vect addr. I] */#define exe$gl_public_vector_symvec_end EXE$GL_PUBLIC_VECTOR_SYMVEC_END /* PUBLIC_VECTOR's sym vect endaddr. */#define ioc$gl_cramh_flink IOC$GL_CRAMH_FLINK /* Queue header FLINK for CRAMH */#define ioc$gl_cramh_blink IOC$GL_CRAMH_BLINK /* " " BLINK " " J] */#define ioc$gl_cramh_pages IOC$GL_CRAMH_PAGES /* Total pages of CRAMHs */#define ioc$gl_cram_total IOC$GL_CRAM_TOTAL /* Total number of CRAMs */#define ioc$gl_cram_in_use IOC$GL_CRAM_IN_USE /* Total CRAMs in use K] */#define ioc$gl_cram_avail IOC$GL_CRAM_AVAIL /* Total CRAMs available */#define exe$gpl_hwrpb_l EXE$GPL_HWRPB_L /* Longword address of HWRPB */#define boo$ga_hwrpb BOO$GA_HWRPB /* Longword address of HWRPB L] */#define exe$gpq_hwrpb EXE$GPQ_HWRPB /* Quadword address of HWRPB */#define exe$gpq_swrpb EXE$GPQ_SWRPB /* Quadword address of SWRPB */#define sch$gl_astdel_k SCH$GL_ASTDEL_K /* PD address of SCH$ASTDEL_K M]*/#define ioc$gl_spi_connect IOC$GL_SPI_CONNECT /* SPI$CONNECT routine address */#define ioc$gl_spdt_list IOC$GL_SPDT_LIST /* SPDT header list */#define exe$ar_mvmslbas EXE$AR_MVMSLBAS /* MV message list base */#defN]ine exe$ar_mvwbqfl EXE$AR_MVWBQFL /* MV work buffer queue */#define exe$gl_scb_reservation EXE$GL_SCB_RESERVATION /* Pointer to reservation bitmap */#define net$ar_reserved1 NET$AR_RESERVED1 /* Reserved for DECnet */#define neO]t$ar_reserved2 NET$AR_RESERVED2 /* Reserved for DECnet */#define net$ar_reserved3 NET$AR_RESERVED3 /* Reserved for DECnet */#define net$ar_reserved4 NET$AR_RESERVED4 /* Reserved for DECnet */#define exe$gl_repP]ort_sys_faults EXE$GL_REPORT_SYS_FAULTS /* Report sys align faults boolean */#define exe$gl_report_match_table EXE$GL_REPORT_MATCH_TABLE /* Table of what faults to report */#define exe$gl_report_buffer EXE$GL_REPORT_BUFFER /* Address of report buffer */#define exe$gl_buffer_itemQ]s EXE$GL_BUFFER_ITEMS /* Max number of data items */#define exe$gl_free_index EXE$GL_FREE_INDEX /* First free data item */#define exe$gl_used_index EXE$GL_USED_INDEX /* First used data item */#define exe$ar_forge_db R] EXE$AR_FORGE_DB /* Address of language database */#define scs$gl_tmscp SCS$GL_TMSCP /* Start of TMSCP server process */#define scs$gl_tmscp_mv SCS$GL_TMSCP_MV /* TMSCP server mount verification routine */#define exe$gq_pfailtime S] EXE$GQ_PFAILTIME /* Smithsonian Time at power fail */#define exe$gq_pwrdone EXE$GQ_PWRDONE /* End time for power up interval */#define exe$gq_pwrintvl EXE$GQ_PWRINTVL /* Allowable interval in 100ns units */#define mmg$gl_color_mask MMG$GT]L_COLOR_MASK /* Page color filter mask (high bits set) */#define mmg$gq_zeroed_list_count MMG$GQ_ZEROED_LIST_COUNT /* Zeroed page list count */#define mmg$gl_zero_list_hi_lim MMG$GL_ZERO_LIST_HI_LIM /* Zeroed list high limit */#define exe$ar_npool_data_mon EXE$AR_NPOOL_U]DATA_MON /* Nonpaged pool */#define exe$ar_npool_data EXE$AR_NPOOL_DATA /* Nonpaged pool */#define pms$gl_kernel_dispatch_vector PMS$GL_KERNEL_DISPATCH_VECTOR /* Kernel dispatch vector addr */#define pms$gl_exec_dispatch_vector PMS$GL_EXEC_DISPATCH_V]VECTOR /* Exec dispatch vector addr */#define mmg$a_sysparam MMG$A_SYSPARAM /* Start of sysparam data */#define ioc$gl_tr_number IOC$GL_TR_NUMBER /* Current TR number */#define scs$gl_pingpong_num_trips SCS$GL_PINGPONG_NUM_TRIPS W] /* Trip limit */#define scs$gl_pingpong_trip_count SCS$GL_PINGPONG_TRIP_COUNT /* Trip count */#define scs$gq_pingpong_start_time SCS$GQ_PINGPONG_START_TIME /* Starting time */#define scs$gq_pingpong_stop_time SCS$GQ_PINGPONG_STOP_TIME /X]* Ending time */#define scs$gl_pingpong_test_done SCS$GL_PINGPONG_TEST_DONE /* Flag for test completion */#define scs$gl_pingpong_ping_error SCS$GL_PINGPONG_PING_ERROR /* Error status from PING SYSAP */#define scs$ar_pingpong_ping_cdt SCS$AR_PINGPONG_PING_CDT /* CDT fY]or PING */#define scs$gl_pingpong_pong_error SCS$GL_PINGPONG_PONG_ERROR /* Error status from PONG SYSAP */#define scs$ar_pingpong_pong_cdt SCS$AR_PINGPONG_PONG_CDT /* CDT for PONG */#define scs$ar_pingpong_counters SCS$AR_PINGPONG_COUNTERS /* Pointer to poZ]rt counter array */#define exe$gl_itb_entries EXE$GL_ITB_ENTRIES /* Max code huge pages to allocate */#define exe$gl_gh_rsrvpgcnt EXE$GL_GH_RSRVPGCNT /* Available memory to be left in huge page */#define exe$gq_deleted_kfe EXE$GQ_DELETED_KFE /* Deleted KFE list [] */#define mmg$ar_cvtprt_hwtov MMG$AR_CVTPRT_HWTOV /* Addr. of HW-VAX protection table */#define mmg$ar_cvtprt_vtohw MMG$AR_CVTPRT_VTOHW /* Addr. of VAX-HW protection table */#define dass$ar_control_block DASS$AR_CONTROL_BLOCK /* Addr of DECdas block \] */#define exe$ar_decps_vectors EXE$AR_DECPS_VECTORS /* Addr of DECps vectors */#define mmg$gq_window_va MMG$GQ_WINDOW_VA /* Addr of 1ST VA */#define mmg$gq_window2_va MMG$GQ_WINDOW2_VA /* Addr of 2ND VA ]] */#define mmg$gl_clone_clump MMG$GL_CLONE_CLUMP /* # of pages to clone at once */#define swp$gl_min_shellpfil SWP$GL_MIN_SHELLPFIL /* Minimal proc pagfile requirement */S#define pms$gl_2pcreq_out PMS$GL_2PCREQ_OUT S#define pms$gl_2pcreq_in ^] PMS$GL_2PCREQ_IN S#define pms$gl_2pcrdy_out PMS$GL_2PCRDY_OUT S#define pms$gl_2pcrdy_in PMS$GL_2PCRDY_IN S#define pms$gl_2pcack_out PMS$GL_2PCACK_OUT S#define pms$gl_2pcack_in PMS$GL_2PCACK_IN S#define pms$gl_2pccnc_out PMS$GL_2PCCNC_OUT S#define pms$gl_2pccnc_in _] PMS$GL_2PCCNC_IN S#define lck$al_ggmax_tbl LCK$AL_GGMAX_TBL S#define lck$al_ggred_tbl LCK$AL_GGRED_TBL S#define lck$al_valblk_tbl LCK$AL_VALBLK_TBL S#define lck$al_dwncvt_tbl LCK$AL_DWNCVT_TBL S#define lck$gl_lkb_miss LCK$GL_LKB_MISS S#define lck$gl_rsb_miss `] LCK$GL_RSB_MISS S#define lck$gl_cspin LCK$GL_CSPIN S#define lck$gl_lckcnt LCK$GL_LCKCNT S#define lck$gl_lkidcnt LCK$GL_LKIDCNT S#define lck$gl_lkidfree LCK$GL_LKIDFREE S#define lck$gl_rsbcnt LCK$GL_RSBCNT S#define lck$gqa]_lstfree LCK$GQ_LSTFREE S#define lck$gl_cache LCK$GL_CACHE S#define lck$gl_lkbcache LCK$GL_LKBCACHE S#define exe$gl_min_vms_prio EXE$GL_MIN_VMS_PRIO S#define exe$gl_max_vms_prio EXE$GL_MAX_VMS_PRIO S#define exe$gl_min_psxrt_prio EXE$GL_MIN_PSXRT_PRIO S#definb]e exe$gl_max_psxrt_prio EXE$GL_MAX_PSXRT_PRIO S#define ctl$ga_ccb_table CTL$GA_CCB_TABLE S#define exe$gl_cdsptr EXE$GL_CDSPTR S#define ctl$gl_cdsptr CTL$GL_CDSPTR S#define exe$gl_secptr EXE$GL_SECPTR #define exe$gl_psx_ctx_buffer_length EXE$GL_PSX_CTX_BUFFER_LENGTH c] /* Length of POSIX context buffer */#define ctl$gl_fcb_listhead CTL$GL_FCB_LISTHEAD /* POSIX FORK_CONTROL callbacks list-head */#define exe$gr_system_data_cells EXE$GR_SYSTEM_DATA_CELLS /* Base of SYSTEM_DATA_CELLS */#define exe$ar_ipc_data EXE$AR_IPC_DATA /* Poid]nter to IPC data cells */S#define exe$gl_transition_year EXE$GL_TRANSITION_YEAR #define exe$gt_hwname EXE$GT_HWNAME /* Recognition */#define sys$k_version_17 SYS$K_VERSION_17 /* Mask for SYS$K_POSIX */#define sye]s$k_version_18 SYS$K_VERSION_18 /* Mask for SYS$K_MULTI_PROCESSING */S#define exe$ar_file_ocb EXE$AR_FILE_OCB S#define exe$ar_object_server_ucb EXE$AR_OBJECT_SERVER_UCB S#define exe$ar_volume_ocb EXE$AR_VOLUME_OCB S#define exe$gl_volume_mutex EXE$GL_VOLUME_MUTEX S#define f] exe$gl_security_policy EXE$GL_SECURITY_POLICY S#define exe$ar_qman_ocb EXE$AR_QMAN_OCB #define sgn$gl_xqpctld1 SGN$GL_XQPCTLD1 /* Reserved for use by F11BXQP */#define sgn$gl_xqpctl2 SGN$GL_XQPCTL2 /* Reserved for use by F11BXQP */#define g]sgn$gl_xqpctld3 SGN$GL_XQPCTLD3 /* Reserved for use by F11BXQP */#define sgn$gl_xqpctl4 SGN$GL_XQPCTL4 /* Reserved for use by F11BXQP */#define sgn$gl_xqpctld5 SGN$GL_XQPCTLD5 /* Reserved for use by F11BXQP */#define sgn$gl_xh]qpctl6 SGN$GL_XQPCTL6 /* Reserved for use by F11BXQP */#define sgn$gl_xqpctld7 SGN$GL_XQPCTLD7 /* Reserved for use by F11BXQP */#define sgn$gl_xqpctl8 SGN$GL_XQPCTL8 /* Reserved for use by F11BXQP */S#define exe$gl_rsdm_mutei]x EXE$GL_RSDM_MUTEX S#define exe$gq_rsdm_list EXE$GQ_RSDM_LIST S#define nsa$gl_audit_summary NSA$GL_AUDIT_SUMMARY S#define exe$gl_objcls_mutex EXE$GL_OBJCLS_MUTEX S#define exe$gq_object_class_list EXE$GQ_OBJECT_CLASS_LIST S#define exe$gq_security_domain EXE$GQ_SECURITY_DOMAIN S#define nsa$glj]_audit_server_pid NSA$GL_AUDIT_SERVER_PID S#define nsa$gl_server_wake_addr NSA$GL_SERVER_WAKE_ADDR S#define nsa$gq_audit_queue NSA$GQ_AUDIT_QUEUE S#define ctl$gl_nsab CTL$GL_NSAB S#define nsa$gq_deaccess_audit NSA$GQ_DEACCESS_AUDIT S#define nsa$a_scratch NSA$A_SCRATCH #defink]e ctl$a_prcprm_edata CTL$A_PRCPRM_EDATA /* E-mode Process Data Area */S#define ctl$gl_oss_flags CTL$GL_OSS_FLAGS S#define ctl$gq_object_context CTL$GQ_OBJECT_CONTEXT S#define ctl$gq_security_exec_1 CTL$GQ_SECURITY_EXEC_1 S#define ctl$gl_security_exec_1 CTL$GL_SECURITY_EXEC_1 S#dl]efine ctl$gl_security_exec_2 CTL$GL_SECURITY_EXEC_2 S#define ctl$ar_forge_word CTL$AR_FORGE_WORD S#define exe$gl_lnm_ocb EXE$GL_LNM_OCB S#define ioc$gl_dtn_list IOC$GL_DTN_LIST S#define exe$gl_lntorb_lock EXE$GL_LNTORB_LOCK S#define exe$ar_system_global_ocb EXE$AR_SYSTEM_GLOBAL_OCB m] S#define exe$ar_group_global_ocb EXE$AR_GROUP_GLOBAL_OCB #define ctl$ar_gfs2 CTL$AR_GFS2 /* Was CTL$AR_FILES_64 */#define ctl$ar_vafs CTL$AR_VAFS /* Was CTL$AR_XFS_CLIENT */#define ctl$ar_vfs CTL$AR_VFS n] /* Was CTL$AR_XFS_SERVER */#define exe$ar_gfs2 EXE$AR_GFS2 /* Was EXE$AR_FILES_64 */#define exe$ar_vafs EXE$AR_VAFS /* Was EXE$AR_XFS_CLIENT */#define exe$ar_vfs EXE$AR_VFS /* Wo]as EXE$AR_XFS_SERVER */S#define ctl$gq_prcterm_listhead CTL$GQ_PRCTERM_LISTHEAD S#define xqp$ar_xqp_private XQP$AR_XQP_PRIVATE S#define xqp$gl_request_callout XQP$GL_REQUEST_CALLOUT S#define mmg$gq_p2_base_va MMG$GQ_P2_BASE_VA S#define xdt$gl_scratch_pages XDT$GL_SCRATCH_PAGES p]S#define xdt$gq_scratch_memory XDT$GQ_SCRATCH_MEMORY S#define mmg$gl_initial_bad_pages MMG$GL_INITIAL_BAD_PAGES S#define tty$gl_asian_dpt TTY$GL_ASIAN_DPT S#define exe$gl_gh_exec_code EXE$GL_GH_EXEC_CODE S#define exe$gl_gh_exec_data EXE$GL_GH_EXEC_DATA S#define exe$gl_gh_res_code EXE$GL_GH_RES_CODE q] S#define exe$gl_gh_res_data EXE$GL_GH_RES_DATA S#define sch$gl_tbsh SCH$GL_TBSH S#define sch$gl_tbswh SCH$GL_TBSWH S#define sch$gl_tbsoh SCH$GL_TBSOH S#define decc$ga___ctype DECC$GA___CTYPE S#define clu$ar_cluevt CLU$AR_CLUEVT r] S#define exe$gl_mmecb EXE$GL_MMECB S#define exe$gl_mme_flags EXE$GL_MME_FLAGS S#define exe$gl_imgreg_pages EXE$GL_IMGREG_PAGES S#define exe$gl_shadow_sys_tmo EXE$GL_SHADOW_SYS_TMO S#define exe$gl_shadow_sys_wait EXE$GL_SHADOW_SYS_WAIT S#define exe$gl_shadow_enable EXE$GL_s]SHADOW_ENABLE S#define decc$ga_randx DECC$GA_RANDX S#define xdt$al_tk_net_info XDT$AL_TK_NET_INFO S#define sgn$gl_system_check SGN$GL_SYSTEM_CHECK #define ctl$gq_ieee_fp_control CTL$GQ_IEEE_FP_CONTROL /* IEEE Floating Point Control */#define mmg$gl_color_count MMGt]$GL_COLOR_COUNT /* Number of page colors (power of 2) */S#define ctl$a_imgreg CTL$A_IMGREG S#define ctl$gl_imgreg_size CTL$GL_IMGREG_SIZE #define sgn$gl_pfn_color_count SGN$GL_PFN_COLOR_COUNT /* Page coloring parameter */S#define exe$gl_volshad_perdev_licelkid EXE$Gu]L_VOLSHAD_PERDEV_LICELKID S#define exe$gq_real_cputype EXE$GQ_REAL_CPUTYPE S#define ctl$gq_remote_address CTL$GQ_REMOTE_ADDRESS S#define ctl$gq_remote_node CTL$GQ_REMOTE_NODE S#define ctl$gq_remote_uid CTL$GQ_REMOTE_UID S#define ctl$ar_dass CTL$AR_DASS S#define ctl$ar_dce v] CTL$AR_DCE S#define ctl$gq_remote_fullname CTL$GQ_REMOTE_FULLNAME S#define img$gl_imcb_list IMG$GL_IMCB_LIST S#define sgn$gb_scsicluster_p1 SGN$GB_SCSICLUSTER_P1 S#define sgn$gb_scsicluster_p2 SGN$GB_SCSICLUSTER_P2 S#define sgn$gb_scsicluster_p3 SGN$GB_SCSICLUSTER_P3 S#define sgn$gb_scsicluster_p4 w] SGN$GB_SCSICLUSTER_P4 S#define decc$$clocale_s DECC$$CLOCALE_S S#define decc$$ga___ctypet DECC$$GA___CTYPET S#define decc$$gl___ctypea DECC$$GL___CTYPEA S#define decc$$gl___mb_cur_max DECC$$GL___MB_CUR_MAX S#define decc$$gl___isclocale DECC$$GL___ISCLOCALE S#define sgn$gl_file_x]cache SGN$GL_FILE_CACHE S#define clu$gl_tmscp_serve_all CLU$GL_TMSCP_SERVE_ALL S#define sgn$gl_dr_unit_base SGN$GL_DR_UNIT_BASE S#define sgn$gl_mc_services_p0 SGN$GL_MC_SERVICES_P0 S#define sgn$gl_mc_services_p1 SGN$GL_MC_SERVICES_P1 S#define sgn$gl_mc_services_p2 SGN$GL_MC_SERVICES_P2 S#define sgy]n$gl_mc_services_p3 SGN$GL_MC_SERVICES_P3 S#define sgn$gl_mc_services_p4 SGN$GL_MC_SERVICES_P4 S#define sgn$gl_mc_services_p5 SGN$GL_MC_SERVICES_P5 S#define sgn$gl_mc_services_p6 SGN$GL_MC_SERVICES_P6 S#define sgn$gl_mc_services_p7 SGN$GL_MC_SERVICES_P7 S#define sgn$gl_mc_services_p8 SGN$GL_MC_SERVICES_P8 S#dz]efine sgn$gl_mc_services_p9 SGN$GL_MC_SERVICES_P9 S#define exe$ar_crd_feet EXE$AR_CRD_FEET #define ctl$a_region_table CTL$A_REGION_TABLE /* Table of user defined region descriptors */#define exe$gq_bugchk_dump_remove_list EXE$GQ_BUGCHK_DUMP_REMOVE_LIST /* Points to first element in remove list */#def{]ine ldr$gq_free_s0s1_pt LDR$GQ_FREE_S0S1_PT /* Free S0/S1 PTE list head */#define ldr$gq_free_s2_pt LDR$GQ_FREE_S2_PT /* Free S2 PTE list head */#define mmg$gl_bwp_width MMG$GL_BWP_WIDTH /* VA byte within page width */#define mm|]g$gl_l1_index MMG$GL_L1_INDEX /* Index of page table space's L1PTE */#define mmg$gl_level_width MMG$GL_LEVEL_WIDTH /* VA segment field, "level" width */#define mmg$gl_maxbobmem_pages MMG$GL_MAXBOBMEM_PAGES /* Available buffer object memory (pages) */#define mmg$gl_max}]bobmem_pagelets MMG$GL_MAXBOBMEM_PAGELETS /* Available buffer object memory (constant quantity) */#define mmg$gl_system_l1pte_index MMG$GL_SYSTEM_L1PTE_INDEX /* Lowest numbered system L1PTE allocated */#define mmg$gl_va_bits MMG$GL_VA_BITS /* Number of sig. bits in 64-Bit VA */#define mmg$gq_bwp_mask ~] MMG$GQ_BWP_MASK /* 64-Bit synonym for bwp mask */#define mmg$gq_bwp_width MMG$GQ_BWP_WIDTH /* 64-Bit synonym for bwp width */#define mmg$gq_free_gpt MMG$GQ_FREE_GPT /* Free GPTE list head */#define mmg$gq_gap_lo_va ] MMG$GQ_GAP_LO_VA /* Low address end of the gap */#define mmg$gq_gap_hi_va MMG$GQ_GAP_HI_VA /* High address end of the gap */#define mmg$gq_gpt_base MMG$GQ_GPT_BASE /* Address of GPT base */#define mmg$gq_l1_base ] MMG$GQ_L1_BASE /* VA of L1PTE base in PT space */#define mmg$gq_l2_base MMG$GQ_L2_BASE /* VA of L2PTE base in PT space */#define mmg$gq_level_width MMG$GQ_LEVEL_WIDTH /* 64-Bit synonym for "level" width */#define mmg$gq_max_gpte MMG$G]Q_MAX_GPTE /* VA succeeding GPT */#define mmg$gq_next_free_s0s1_va MMG$GQ_NEXT_FREE_S0S1_VA /* Next place to expand in S0/S1 */#define mmg$gl_next_free_s0s1_va MMG$GL_NEXT_FREE_S0S1_VA /* Synonym for MMG$GQ_NEXT_FREE_S0S1_VA */#define mmg$gq_next_free_s2_va MMG$GQ_NEXT_F]REE_S2_VA /* Next place to expand in S2 space */#define mmg$gq_non_va_mask MMG$GQ_NON_VA_MASK /* Mask for bits not in 64-bit VA */#define mmg$gq_non_pt_mask MMG$GQ_NON_PT_MASK /* Mask for bits not in 64-bit VA, including BWP field */#define mmg$gq_page_size MMG$GQ_PAGE_SIZE ] /* 64-Bit synonym for page size cell */#define mmg$gq_process_space_limit MMG$GQ_PROCESS_SPACE_LIMIT /* Highest possible process space address */#define mmg$gq_pt_base MMG$GQ_PT_BASE /* VA of PT space base */#define mmg$gq_pte_offset_to_va MMG$GQ_PTE_OFFSET_TO_VA ] /* 64-Bit synonym for pte offset to va shift */#define mmg$gq_s0s1base_pte_address MMG$GQ_S0S1BASE_PTE_ADDRESS /* Address of PTE that maps the base of S0/S1 space */#define mmg$gq_shared_va_ptes MMG$GQ_SHARED_VA_PTES /* Boundary between process and system space PTEs */#define mmg$gq_sptbase MMG$GQ_SPTBASE /]* Base of "SPT Window" (synonym to MMG$GL_SPTBASE) */#define mmg$gq_system_virtual_base MMG$GQ_SYSTEM_VIRTUAL_BASE /* Base address of system space */#define mmg$gq_vpn_to_va MMG$GQ_VPN_TO_VA /* 64-Bit synonym for vpn to va shift */#define mmg$gq_va_bits MMG$GQ_VA_BITS /* 64-Bi]t synonym for "va bits" */#define mmg$gq_s0s1base_pte_offset MMG$GQ_S0S1BASE_PTE_OFFSET /* Offset to PTE address of -1.80000000 in PT_space */#define mmg$gq_system_l1pt MMG$GQ_SYSTEM_L1PT /* Contains permanent mapping of system L1PT */#define mmg$gq_svapte_pte MMG$GQ_SVAPTE_PTE /* Address of SV]APTE-reserved window PTE */#define mmg$gq_svapte_pc MMG$GQ_SVAPTE_PC /* PC of last user of SVAPTE-reserved window */#define mmg$gq_svapte_va MMG$GQ_SVAPTE_VA /* Address of SVAPTE-reserved window */#define phv$gl_refcbas_lw PHV$GL_REFCBAS_LW /* Base of PHD reference] count vector */#define pms$gl_bufobj_pages_s0s1 PMS$GL_BUFOBJ_PAGES_S0S1 /* Number of buffer object pages in S0S1 */#define pms$gl_bufobj_pages_s2 PMS$GL_BUFOBJ_PAGES_S2 /* Number of buffer object pages in S2 */#define pms$gl_bufobj_pages_s0s1_peak PMS$GL_BUFOBJ_PAGES_S0S1_PEAK /* Peak number of buffer object ]pages in S0S1 */#define pms$gl_bufobj_pages_s2_peak PMS$GL_BUFOBJ_PAGES_S2_PEAK /* Peak number of buffer object pages in S2 */#define sgn$gl_s2_size SGN$GL_S2_SIZE /* Size of S2 space */#define pfn$pq_database PFN$PQ_DATABASE /* Quadword pointer to PFN database ] */#define swp$gq_balbase SWP$GQ_BALBASE /* Base of balance slots */#define swp$gq_bal_end SWP$GQ_BAL_END /* Lowest VA that is above the balance slots */#define swp$c_l1pt SWP$C_L1PT /* SHELL L1PT count ] */#define ctl$gt_simple_tabname CTL$GT_SIMPLE_TABNAME /* simple file name of CLI command table */#define sgn$gl_cwcreprc_enable SGN$GL_CWCREPRC_ENABLE /* SYSGEN parameter to enable use by unpriv. user */#define clu$gl_csp_mbx CLU$GL_CSP_MBX /* address of CSP mailbox ] */#define clu$gl_csp_entries CLU$GL_CSP_ENTRIES /* address of CSP entry point table */#define smp$gl_last_cpu_assigned SMP$GL_LAST_CPU_ASSIGNED /* Last affinitized CPU */#define smp$gl_available_port_cpus SMP$GL_AVAILABLE_PORT_CPUS /* Mask of port CPUs ] */#define scs$gl_reserved1 SCS$GL_RESERVED1 /* Reserved SCS data cell */#define scs$gl_reserved2 SCS$GL_RESERVED2 /* Reserved SCS data cell */#define sgn$gl_fast_path SGN$GL_FAST_PATH /* Contents of SYSGEN parameter FASTPATH ] */#define sgn$gl_multithread SGN$GL_MULTITHREAD /* Multithread system parameter */#define ctl$gl_initial_ktb CTL$GL_INITIAL_KTB /* KTB address of initial thread */#define ctl$gl_initial_pid CTL$GL_INITIAL_PID /* PID of initial thread */]#define ctl$gl_initial_epid CTL$GL_INITIAL_EPID /* EPID of initial thread */#define ctl$gl_kt_count CTL$GL_KT_COUNT /* Count of active kernel threads */#define ctl$gl_kt_high CTL$GL_KT_HIGH /* Higest ktbvec entry in use */#defin]e ctl$gl_multithread CTL$GL_MULTITHREAD /* Max number of kernel threads */#define ctl$gl_kt_area_pages CTL$GL_KT_AREA_PAGES /* Size of kthread area in pages */#define ctl$ar_im_semaphore CTL$AR_IM_SEMAPHORE /* Address of inner mode semaphore */#define ctl$]gq_tm_callbacks CTL$GQ_TM_CALLBACKS /* address of thread manager */#define ctl$gq_pktavec CTL$GQ_PKTAVEC /* Vector of kthread area pointers */#define ctl$gq_kt_region_base CTL$GQ_KT_REGION_BASE /* base address of kthreads region */#define ctl$gq_kt_re]gion_id CTL$GQ_KT_REGION_ID /* max address in kthreads region */#define ctl$gq_persona_handle CTL$GQ_PERSONA_HANDLE /* per-thread persona handle */#define ctl$gq_exit_thread CTL$GQ_EXIT_THREAD /* thread id of exit in progress */#define ctl$gq_exh_mutex ] CTL$GQ_EXH_MUTEX /* Exit handler list mutex */#define ctl$gq_ssi_interlock CTL$GQ_SSI_INTERLOCK /* SSI threaded interlock */#define swp$gw_fredpte SWP$GW_FREDPTE /* # of FRED pages in a balance set slot */#define ctl$gq_virtpeak ] CTL$GQ_VIRTPEAK /* Peak virtual size */#define mmg$gq_process_va_pages MMG$GQ_PROCESS_VA_PAGES /* min (VIRTUALPAGECNT, sizeof (P0+P1+P2)) */#define ctl$gq_wsl CTL$GQ_WSL /* Pointer to process's WSL */#define mmg$gq_syswsl ] MMG$GQ_SYSWSL /* Pointer to system's WSL */#define ctl$gq_pool_mutex CTL$GQ_POOL_MUTEX /* Pool mutex for threads */#define ctl$gq_emulate_flags CTL$GQ_EMULATE_FLAGS /* For internal use by emulator; bit 0 cleared by imgact */#define ctl$gq_emulate_count CTL$GQ_]EMULATE_COUNT /* Count the number of instructions emulated */#define ctl$gq_emulate_signal_mask CTL$GQ_EMULATE_SIGNAL_MASK /* A mask of which group of extended instructions */#define ctl$gq_emulate_signal_max CTL$GQ_EMULATE_SIGNAL_MAX /* The number of times to signal an emulated instruction */#define ctl$gq_emulate_ring_index CTL$GQ_EMULATE_]RING_INDEX /* The index of the next entry in the ring buffer */#define ctl$gq_emulate_pc_ring CTL$GQ_EMULATE_PC_RING /* Ring buffer for PCs of emulated instructions */#define ctl$gq_emulate_data CTL$GQ_EMULATE_DATA /* Reserved for a place to pass data to the emulator. */#define ctl$gq_report_buffer CTL$GQ_REPORT_BUFFER ] /* Address of alignment data buffer (quadword allows for */#define sgn$gl_file_cache_min SGN$GL_FILE_CACHE_MIN /* Minimum pages in cache */#define sgn$gl_file_cache_max SGN$GL_FILE_CACHE_MAX /* Maximum pages in cache */#define sgn$gl_f64ctl1 SGN$GL_F64CTL1 ] /* Reserved for file system use */#define sgn$gl_f64ctl2 SGN$GL_F64CTL2 /* Reserved for file system use */#define sgn$gl_f64ctld3 SGN$GL_F64CTLD3 /* Reserved for file system use */#define sgn$gl_f64ctld4 SGN$GL_F64CTLD4 /* ] Reserved for file system use */#define sgn$gl_dsb_upcalls SGN$GL_DSB_UPCALLS /* Bitmask for disabling specific threads upcalls */#define scs$gq_ddma_base SCS$GQ_DDMA_BASE /* Pntr to Pool Base */#define scs$gq_ddma_len SCS$GQ_DDMA_LEN /* Pool Le]ngth */#define scs$gl_nonpaged_ddma SCS$GL_NONPAGED_DDMA /* Pntr to Pool NEXT_FREE */#define scs$gq_listhead_ddma SCS$GQ_LISTHEAD_DDMA /* Pntr to Pool Freelist */#define ioc$gl_paclist_b IOC$GL_PACLIST_B /* Pointer to Boot]-time PAC list */#define ioc$gl_paclist_f IOC$GL_PACLIST_F /* Pointer to "registry" PAC list */#define ioc$gl_pac_id_list IOC$GL_PAC_ID_LIST /* Pointer to database of who is sharing "our" SCSI buses */#define ioc$gl_naming_p IOC$GL_NAMING_P /* Spare for naming ] */#define ioc$gl_naming IOC$GL_NAMING /* DEVICE_NAMING SYSGEN parameter */#define ctl$ar_persona_array CTL$AR_PERSONA_ARRAY /* Address of persona array */#define ctl$gl_persona_freeindex CTL$GL_PERSONA_FREEINDEX /* Index of next free entry in per]sona array */#define ctl$gl_persona_maxindex CTL$GL_PERSONA_MAXINDEX /* Maximum index into persona array */#define ctl$gl_persona_usercount CTL$GL_PERSONA_USERCOUNT /* Count of user mode personae */#define ctl$gl_arb_support CTL$GL_ARB_SUPPORT /* Current working ARB_SUPPORT value for p]rocess */#define ctl$gl_def_arb_support CTL$GL_DEF_ARB_SUPPORT /* Permanent ARB_SUPPORT value for process */#define exe$ar_system_rights EXE$AR_SYSTEM_RIGHTS /* Address of system rights chain */#define exe$gq_debug_class_list EXE$GQ_DEBUG_CLASS_LIST /* Address of debug classification chain ] */#define exe$gq_debug_psb_list EXE$GQ_DEBUG_PSB_LIST /* Address of debug persona chain */#define exe$gq_debug_rights_list EXE$GQ_DEBUG_RIGHTS_LIST /* Address of debug rights chain */#define mmg$gl_pfn_memory_map MMG$GL_PFN_MEMORY_MAP /* PFN memory map used by VALID_PFN ] */#define mmg$gl_syi_pfn_memory_map MMG$GL_SYI_PFN_MEMORY_MAP /* PFN memory map returned by $GETSYI */S#define exe$gq_bugchk_process_list EXE$GQ_BUGCHK_PROCESS_LIST S#define clu$gl_mscp_cmd_tmo CLU$GL_MSCP_CMD_TMO S#define sch$gq_reserved_user_caps SCH$GQ_RESERVED_USER_CAPS #define pio$gw_dflrl PIO$GW_DFLR]L /* Default Longest Record Length */#define pio$gb_rmsheuristic PIO$GB_RMSHEURISTIC /* Default RMS heuristic */S#define sgn$gl_npag_interval SGN$GL_NPAG_INTERVAL S#define sgn$gl_npag_gentle SGN$GL_NPAG_GENTLE S#define sgn$gl_npag_aggressive SGN$GL_NPAG_A]GGRESSIVE S#define ctl$ar_registry CTL$AR_REGISTRY S#define ctl$ar_registry_extra CTL$AR_REGISTRY_EXTRA S#define exe$ar_registry EXE$AR_REGISTRY S#define exe$ar_registry_extra EXE$AR_REGISTRY_EXTRA S#define mmg$gq_bap MMG$GQ_BAP S#define exe$gq_bap_variable EXE]$GQ_BAP_VARIABLE S#define exe$gq_bap_max_request_size EXE$GQ_BAP_MAX_REQUEST_SIZE S#define exe$gq_bap_min_request_size EXE$GQ_BAP_MIN_REQUEST_SIZE S#define exe$gq_bap_max_pa_registered EXE$GQ_BAP_MAX_PA_REGISTERED S#define exe$gq_bap_min_pa_registered EXE$GQ_BAP_MIN_PA_REGISTERED S#define exe$gq_bap_num_registrations EXE$GQ_BAP_NUM_REGISTRATIONS S#define clu$gl_cluster_credits ] CLU$GL_CLUSTER_CREDITS S#define ioc$gq_min_bap_window IOC$GQ_MIN_BAP_WINDOW S#define exe$gpq_fru_table EXE$GPQ_FRU_TABLE S#define icc$gl_icc_pdb_vector ICC$GL_ICC_PDB_VECTOR S#define icc$gl_icc_trace_area ICC$GL_ICC_TRACE_AREA #define pms$gl_bufobj_pages PMS$GL_BUFOBJ_PAGES /* Number of physical pages in b]uffer objects */#define pms$gl_bufobj_pages_peak PMS$GL_BUFOBJ_PAGES_PEAK /* Peak number of physical pages in buffer object pages */#define mmg$gl_maxbobs0s1_pages MMG$GL_MAXBOBS0S1_PAGES /* Available buffer object S0S1 VA space (pages) */#define mmg$gl_maxbobs0s1_pagelets MMG$GL_MAXBOBS0S1_PAGELETS /* Available buffer object S0S1 VA space] (constant quantity) */#define mmg$gl_maxbobs2_pages MMG$GL_MAXBOBS2_PAGES /* Available buffer object S2 VA space (pages) */#define mmg$gl_maxbobs2_pagelets MMG$GL_MAXBOBS2_PAGELETS /* Available buffer object S2 VA space (constant quantity) */#define mmg$gl_prvpfn_flink MMG$GL_PRVPFN_FLINK /* List head for private lists of free PFNs (fli]nk) */#define mmg$gl_prvpfn_blink MMG$GL_PRVPFN_BLINK /* List head for private lists of free PFNs (blink) */#define mmg$gl_prvpfn_reclaimable MMG$GL_PRVPFN_RECLAIMABLE /* System-wide count of PFNs that can be reclaimed from private PFN lists */#define mmg$gl_prvpfn_reclaimed MMG$GL_PRVPFN_RECLAIMED /* System-wide count of PFNs that were reclaimed but not] yet returned */S#define vcc$gl_max_cache VCC$GL_MAX_CACHE S#define vcc$gl_max_io_size VCC$GL_MAX_IO_SIZE S#define vcc$gl_max_locks VCC$GL_MAX_LOCKS S#define vcc$gl_readahead VCC$GL_READAHEAD S#define vcc$gl_writebehind VCC$GL_WRITEBEHIND S#define vcc$gl_write_delay VCC]$GL_WRITE_DELAY S#define vcc$gl_max_cache_pages VCC$GL_MAX_CACHE_PAGES S#define exe$ar_xfc_data EXE$AR_XFC_DATA S#define exe$ar_xfc_anchor EXE$AR_XFC_ANCHOR S#define exe$ar_ntbs EXE$AR_NTBS S#define exe$ar_sd_anchor EXE$AR_SD_ANCHOR S#define clu$gl_sd_allocls ] CLU$GL_SD_ALLOCLS S#define icc$gl_icc_rand ICC$GL_ICC_RAND S#define img$gl_image_region IMG$GL_IMAGE_REGION #define sgn$gl_arb_support SGN$GL_ARB_SUPPORT /* Address of system arb_support cell */#define exe$ar_unicode_upcase_dat EXE$AR_UNICODE_UPCASE_DAT /* Pointer to the Unicode upcase table] */#define ctl$gq_sspi_root CTL$GQ_SSPI_ROOT /* Address of SSPI data structures */#define pms$gl_dellnm PMS$GL_DELLNM /* Number of logical name or table deletions */#define pms$gl_crelnm PMS$GL_CRELNM /* Number of logical name creations ] */#define pms$gl_crelnt PMS$GL_CRELNT /* Number of logical name table creations */#define pms$gl_failed_trnlnm PMS$GL_FAILED_TRNLNM /* Number of failed translations */#define lnm$ar_cluster_lnmb LNM$AR_CLUSTER_LNMB /* Pointer to LNM$CLUSTER logical name block ] */#define lnm$ar_syscluster_lnmb LNM$AR_SYSCLUSTER_LNMB /* Pointer to LNM$SYSCLUSTER logical name block */#define lnm$gq_cw_workq LNM$GQ_CW_WORKQ /* Listhead of pending messages */#define lnm$gl_cw_workq_count LNM$GL_CW_WORKQ_COUNT /* Number of messages on the queue ] */#define lnm$gl_cw_server LNM$GL_CW_SERVER /* IPID of process handling messages */#define lnm$gl_cw_buffer LNM$GL_CW_BUFFER /* SVA of preallocated buffer */#define lnm$gl_cw_last_msg LNM$GL_CW_LAST_MSG /* SVA of most recent message ] */#define exe$ar_pxrb_array EXE$AR_PXRB_ARRAY /* Pointer to registration database array */#define exe$gq_pxrb_mutex EXE$GQ_PXRB_MUTEX /* Synchronization point for writing to database */#define exe$gl_pxrb_count EXE$GL_PXRB_COUNT /* Count of registered extensions ]*/#define lnm$gq_cw_names LNM$GQ_CW_NAMES /* Listhead of clusterwide LNMBs */#define sch$gq_affinity_time_int SCH$GQ_AFFINITY_TIME_INT /* Internal value for affinity_time system parameter */#define sch$gq_io_vs_compute SCH$GQ_IO_VS_COMPUTE /* Value used to determine if process is I/O or compute */#def]ine sch$gq_cc_per_hardtick SCH$GQ_CC_PER_HARDTICK /* # of system cycles per hard tick */#define sch$gq_cc_per_quant SCH$GQ_CC_PER_QUANT /* # of system cycles per quantum */#define lck$gq_hashtbl LCK$GQ_HASHTBL /* Address of resource hash table */#define lc]k$gq_timoutq LCK$GQ_TIMOUTQ /* Lock timeout queue header */#define lck$gq_rrsfl LCK$GQ_RRSFL /* List of all Root RSBs */#define lck$gq_lkb_head LCK$GQ_LKB_HEAD /* Head of LKB cache */#define lck$gq_lkb]_tail LCK$GQ_LKB_TAIL /* Tail of LKB cache */#define lck$gq_rsb_head LCK$GQ_RSB_HEAD /* Head of RSB cache */#define lck$gq_rsb_tail LCK$GQ_RSB_TAIL /* Tail of RSB cache */#define lck$ar_poolzone_re]gion LCK$AR_POOLZONE_REGION /* Pointer to poolzone region info */#define pio$gl_dirclals PIO$GL_DIRCLALS /* RMS pathcache lookaside list ptr */#define pio$gw_dircsiz PIO$GW_DIRCSIZ /* Semi-max size of pathcache */#define pio$gw_dircalloc ] PIO$GW_DIRCALLOC /* Current pathcache allocation */#define sgn$gl_galaxy SGN$GL_GALAXY /* Galaxy participation */#define smp$gpq_ctd_listhead SMP$GPQ_CTD_LISTHEAD /* Array of CTD listheads */#define smp$gpq_failover_gnode ] SMP$GPQ_FAILOVER_GNODE /* CPU failover array */#define smp$gl_potential_set SMP$GL_POTENTIAL_SET /* Galaxy-available CPUs */#define smp$gl_cpu_auto_start SMP$GL_CPU_AUTO_START /* CPU auto-start bitmask */#define smp$gl_cpu_transition SMP$G]L_CPU_TRANSITION /* CPU transition bitmask */#define glx$gpq_gmdb_base GLX$GPQ_GMDB_BASE /* pointer to GMDB */#define glx$gl_gnode GLX$GL_GNODE /* Partition ID */#define glx$gpq_config_tree GLX$GPQ_CONFI]G_TREE /* Ptr to configuration tree */#define mmg$gl_max_mem_fragments MMG$GL_MAX_MEM_FRAGMENTS /* Max number of memory fragments for this Galaxy */#define exe$gl_unicode_upcase_version EXE$GL_UNICODE_UPCASE_VERSION /* Version number for Unicode table */S#define glx$gl_communityid_lock GLX$GL_COMMUNITYID_LO]CK S#define glx$gl_shm_reg_attached_count GLX$GL_SHM_REG_ATTACHED_COUNT S#define glx$gpq_shmem_gmdb GLX$GPQ_SHMEM_GMDB S#define glx$gl_shmem_flags GLX$GL_SHMEM_FLAGS S#define glx$gl_max_shm_cpp_count GLX$GL_MAX_SHM_CPP_COUNT S#define glx$gq_shm_cpp_size GLX$GQ_SHM_CPP_SIZE S#define glx$gpq_shm_cpp_array GLX$GPQ_SHM]_CPP_ARRAY S#define glx$gl_shm_cpp_max_frag GLX$GL_SHM_CPP_MAX_FRAG S#define glx$gpq_shmem_pmap_array GLX$GPQ_SHMEM_PMAP_ARRAY S#define glx$gl_shmem_pmap_count GLX$GL_SHMEM_PMAP_COUNT S#define glx$gpq_shm_tag_array GLX$GPQ_SHM_TAG_ARRAY S#define glx$gl_max_shm_reg_count GLX$GL_MAX_SHM_REG_COUNT S#define glx$gq_shm_reg_size G]LX$GQ_SHM_REG_SIZE S#define glx$gpq_shm_reg_array GLX$GPQ_SHM_REG_ARRAY S#define glx$gpq_shm_desc_array GLX$GPQ_SHM_DESC_ARRAY S#define glx$gq_system_features GLX$GQ_SYSTEM_FEATURES S#define glx$gl_system_features_l GLX$GL_SYSTEM_FEATURES_L S#define glx$gl_system_features_h GLX$GL_SYSTEM_FEATURES_H S#define glx$gq_lock_tables ] GLX$GQ_LOCK_TABLES S#define glx$gq_gmdb_locking GLX$GQ_GMDB_LOCKING S#define glx$gq_partition_id GLX$GQ_PARTITION_ID S#define glx$gq_partition_handle GLX$GQ_PARTITION_HANDLE S#define glx$gq_community_id GLX$GQ_COMMUNITY_ID S#define glx$gq_community_handle GLX$GQ_COMMUNITY_HANDLE S#define exe$ar_console_dis]patch EXE$AR_CONSOLE_DISPATCH #define sys$k_version_19 SYS$K_VERSION_19 /* Value for SYS$K_GALAXY */S#define exe$gl_npag_bap_min_pa EXE$GL_NPAG_BAP_MIN_PA S#define glx$go_galaxy_id GLX$GO_GALAXY_ID #define pio$gb_rmsd6 PIO$GB_RMSD6 /* Reserved to RMS develop]ment (process) */#define sys$gb_rmsd6 SYS$GB_RMSD6 /* Reserved to RMS development (system) */#define lck$gq_lckcpu_list LCK$GQ_LCKCPU_LIST /* address of lckmgr per-CPU data blocks */#define glx$gpq_gmdb_node_block GLX$GPQ_GMDB_NODE_BLOCK /* Pointer to node block in GMDB h]eader */#define ctl$gq_sspi_synch CTL$GQ_SSPI_SYNCH /* Address of SSPI synchronization lock */#define ctl$gq_acmerb_list CTL$GQ_ACMERB_LIST /* Authentication services request queue head */#define acme$gq_mutex ACME$GQ_MUTEX /* Authentication services mutex ] */#define acme$gq_request_queue ACME$GQ_REQUEST_QUEUE /* Authentication services request queue head */#define acme$gq_server ACME$GQ_SERVER /* Authentication server */#define clu$gl_smci_group CLU$GL_SMCI_GROUP /* Shared Memory CI Group Code ] */#define clu$gq_smci_auth CLU$GQ_SMCI_AUTH /* Shared Memory CI Authorization quadword */#define glx$gl_max_instances GLX$GL_MAX_INSTANCES /* max Galaxy instances in box */S#define ioc$gl_mpdev_flags IOC$GL_MPDEV_FLAGS S#define exe$ar_system_event EXE$AR_SY]STEM_EVENT #define ioc$gl_wwidtbl IOC$GL_WWIDTBL /* Pointer to World-Wide ID table */S#define exe$gl_glxsysfl EXE$GL_GLXSYSFL S#define exe$gl_glxsysbl EXE$GL_GLXSYSBL S#define exe$gl_glxgrpfl EXE$GL_GLXGRPFL S#define exe$gl_glxgrpbl EXE$G]L_GLXGRPBL #define cache$gl_protocol_ver CACHE$GL_PROTOCOL_VER /* Cache protocol version */S#define sys$gl_rmsd1 SYS$GL_RMSD1 S#define exe$ar_glxsys_global_ocb EXE$AR_GLXSYS_GLOBAL_OCB S#define exe$ar_glxgrp_global_ocb EXE$AR_GLXGRP_GLOBAL_OCB S#define ioc$gq_ddma_base_pa I]OC$GQ_DDMA_BASE_PA #define exe$ar_fastpath_block EXE$AR_FASTPATH_BLOCK /* I/O Fastpath block anchor */S#define ctl$gpq_gsd_lock_pte CTL$GPQ_GSD_LOCK_PTE S#define glx$gq_lock_regions GLX$GQ_LOCK_REGIONS S#define ctl$gq_glx_lock_regions CTL$GQ_GLX_LOCK_REGIONS S#define mmg$gl_io_memory_map ] MMG$GL_IO_MEMORY_MAP S#define glx$gl_is_member GLX$GL_IS_MEMBER S#define glx$gl_spi_available GLX$GL_SPI_AVAILABLE S#define ctl$gq_glx_lock_reg_id CTL$GQ_GLX_LOCK_REG_ID S#define glx$gq_glock_fkbq GLX$GQ_GLOCK_FKBQ S#define pio$gl_rms_local_charset PIO$GL_RMS_LOCAL_CHARSET S#define ctl$gq_glx_lock_reg_cnt ] CTL$GQ_GLX_LOCK_REG_CNT S#define glx$gq_lock_reg_cnt GLX$GQ_LOCK_REG_CNT S#define glx$gpq_gmdb_base_copy GLX$GPQ_GMDB_BASE_COPY S#define glx$gpq_gmdb_node_block_copy GLX$GPQ_GMDB_NODE_BLOCK_COPY S#define sgn$gl_glx_inst_tmo SGN$GL_GLX_INST_TMO S#define sgn$gl_smci_flags SGN$GL_SMCI_FLAGS S#define sgn$gl_smci_po]rts SGN$GL_SMCI_PORTS S#define glx$gt_community_id_name GLX$GT_COMMUNITY_ID_NAME S#define glx$gl_shm_reg_attach_fkb GLX$GL_SHM_REG_ATTACH_FKB S#define glx$gl_shm_reg_detach_fkb GLX$GL_SHM_REG_DETACH_FKB #define clu$gl_served_io CLU$GL_SERVED_IO /* SYSGEN parameter (unused as of Jan 2017) */#define net$ar_lan]2_vector NET$AR_LAN2_VECTOR /* LAN-VCI2 global data pointer */#define net$ar_drl_vector NET$AR_DRL_VECTOR /* LAN DRL global data pointer */#define mb$ar_ucb4 MB$AR_UCB4 /* Mailbox UCB (unused as of Jan 2017) */#define mb$ar_orb4 ] MB$AR_ORB4 /* Mailbox ORB (unused as of Jan 2017) */#define sys$ar_qiosrvmbx SYS$AR_QIOSRVMBX /* Global pointer to QIOserver mailbox (unused as of Jan 2017) */S#define glx$gq_smci_ipint_queue GLX$GQ_SMCI_IPINT_QUEUE S#define ctl$gq_nt_events CTL$GQ_NT_EVENTS S#define ctl$gq_clusyictx ] CTL$GQ_CLUSYICTX S#define exe$ar_perm_db_start EXE$AR_PERM_DB_START S#define exe$ar_perm_db_end EXE$AR_PERM_DB_END S#define glx$gq_init_inprog GLX$GQ_INIT_INPROG S#define ioc$gl_mpdev_lcretries IOC$GL_MPDEV_LCRETRIES S#define ioc$gl_mpdev_d1 IOC$GL_MPDEV_D1 S#define rms$gq_loc]al_charset_queue RMS$GQ_LOCAL_CHARSET_QUEUE S#define glx$gq_smlan_ipint_queue GLX$GQ_SMLAN_IPINT_QUEUE S#define smp$gl_cpus_tested SMP$GL_CPUS_TESTED S#define ctl$gl_network_protocol CTL$GL_NETWORK_PROTOCOL S#define qsrv$gl_pimgcnt QSRV$GL_PIMGCNT S#define qsrv$gl_p0_root QSRV$GL_P0_ROOT S#define ]glx$gpq_packet_dispatch GLX$GPQ_PACKET_DISPATCH S#define glx$gpq_active_set GLX$GPQ_ACTIVE_SET S#define glx$gpq_cpucom_ktb GLX$GPQ_CPUCOM_KTB S#define ctl$ar_persona_ringbuffer CTL$AR_PERSONA_RINGBUFFER S#define glx$gl_cpucom_fkb_flags GLX$GL_CPUCOM_FKB_FLAGS S#define atm$gq_request_queue ATM$GQ_REQUEST_QUEUE S]#define atm$gq_complete_queue ATM$GQ_COMPLETE_QUEUE #define cnx$gq_debug CNX$GQ_DEBUG /* reserved for cnxmgr debug use */#define lck$gl_lckmgr_flags LCK$GL_LCKMGR_FLAGS /* Lock manager flags */#define lck$gq_local_anchor LCK$GQ_LOCAL_ANCHOR /* l]ocal lckmgr data structure anchor */#define lck$gq_shared_anchor LCK$GQ_SHARED_ANCHOR /* share lckmgr data structure anchor */#define lck$gq_reserved1 LCK$GQ_RESERVED1 /* reserved for lckmgr use */#define lck$gq_reserved2 LCK$GQ_RESERVED2 /* reserved ]for lckmgr use */#define lck$gq_reserved3 LCK$GQ_RESERVED3 /* reserved for lckmgr use */#define lck$gq_reserved4 LCK$GQ_RESERVED4 /* reserved for lckmgr use */#define lck$gq_reserved5 LCK$GQ_RESERVED5 /* reserved for lckm]gr use */#define lck$gq_reserved6 LCK$GQ_RESERVED6 /* reserved for lckmgr use */#define smp$gq_debug SMP$GQ_DEBUG /* reserved for spinlock debug use */#define smp$gl_max_cpuid SMP$GL_MAX_CPUID /* holds maximum CPU Id ] */S#define glx$gl_ev_lp_count GLX$GL_EV_LP_COUNT #define sch$ar_current_quant SCH$AR_CURRENT_QUANT /* Longword array for current class quantum */#define sch$ar_original_quant SCH$AR_ORIGINAL_QUANT /* Longword array for original class quantum */#define sch$ar_class_pcblink ] SCH$AR_CLASS_PCBLINK /* Listhead for list of PCBs belonging to class */#define sch$ar_time_restrict SCH$AR_TIME_RESTRICT /* Longword array for current time restrictions */#define sch$ar_class_name SCH$AR_CLASS_NAME /* Array of scheduling class names */#define sch$gl_class_sched_mutex ] SCH$GL_CLASS_SCHED_MUTEX /* Class scheduler mutex for controlling access to PCB list */#define sch$gl_max_sched_class SCH$GL_MAX_SCHED_CLASS /* Highest scheduling class number in use */S#define mmg$gq_pagefile_allocs MMG$GQ_PAGEFILE_ALLOCS S#define mmg$gq_pagefile_refs MMG$GQ_PAGEFILE_REFS S#define mmg$gq_pagefile_pages ] MMG$GQ_PAGEFILE_PAGES S#define mmg$gq_swapfile_allocs MMG$GQ_SWAPFILE_ALLOCS S#define mmg$gq_swapfile_pages MMG$GQ_SWAPFILE_PAGES S#define sgn$gl_lckmgr_flags SGN$GL_LCKMGR_FLAGS S#define exe$gl_sched_flags EXE$GL_SCHED_FLAGS S#define sgn$gl_fast_path_ports SGN$GL_FAST_PATH_PORTS [#define glx$gpq_config_root/glx$]gpq_config_tree GLX$GPQ_CONFIG_ROOT/GLX$GPQ_CONFIG_TREE [#define glx$gpq_config_header GLX$GPQ_CONFIG_HEADER [#define rms$gl_forklock_blk_status RMS$GL_FORKLOCK_BLK_STATUS [#define mmg$gpq_page_swap_vector MMG$GPQ_PAGE_SWAP_VECTOR [#define sgn$gl_glx_shm_reg SGN$GL_GLX_SHM_REG [#define exe$gpq_rad_info_header EXE$GPQ_RAD_INFO_HE]ADER [#define sgn$gl_rad_support SGN$GL_RAD_SUPPORT [#define mmg$gl_present_color_mask MMG$GL_PRESENT_COLOR_MASK [#define mmg$gl_next_color_index MMG$GL_NEXT_COLOR_INDEX [#define sgn$gl_npagecalc SGN$GL_NPAGECALC [#define ioc$gq_dev_wwid_list IOC$GQ_DEV_WWID_LIST [#define wb]m$gl_data WBM$GL_DATA [#define wbm$gq_wbmb_queue WBM$GQ_WBMB_QUEUE [#define wbm$gl_interval WBM$GL_INTERVAL [#define wbm$gl_upper_threshold WBM$GL_UPPER_THRESHOLD [#define wbm$gl_lower_threshold WBM$GL_LOWER_THRESHOLD [#define sch$gl_no_ktb_cpus ] SCH$GL_NO_KTB_CPUS [#define wbm$gl_shadow_max_unit WBM$GL_SHADOW_MAX_UNIT [#define wbm$gl_wbm_opcom_lvl WBM$GL_WBM_OPCOM_LVL [#define sgn$gl_auto_dlight_sav SGN$GL_AUTO_DLIGHT_SAV [#define sys$gl_rms_nql SYS$GL_RMS_NQL [#define rms$gq_reserved01 RMS$GQ_RESERVED01 ] [#define rms$gq_reserved02 RMS$GQ_RESERVED02 [#define rms$gq_reserved03 RMS$GQ_RESERVED03 [#define rms$gq_reserved04 RMS$GQ_RESERVED04 [#define rms$gq_reserved05 RMS$GQ_RESERVED05 [#define rms$gq_reserved06 RMS$GQ_RESERVED06 [#define rms$gq_reserved0]7 RMS$GQ_RESERVED07 [#define rms$gq_reserved08 RMS$GQ_RESERVED08 [#define rms$gq_reserved09 RMS$GQ_RESERVED09 [#define rms$gq_reserved10 RMS$GQ_RESERVED10 [#define pio$gl_rms_nql PIO$GL_RMS_NQL [#define smp$gq_abuse_threshold SMP$GQ_ABUS]E_THRESHOLD [#define smp$gq_abuse_count SMP$GQ_ABUSE_COUNT [#define smp$gl_cpus_powered SMP$GL_CPUS_POWERED [#define smp$gl_cpus_present SMP$GL_CPUS_PRESENT [#define smp$gl_compat_level SMP$GL_COMPAT_LEVEL [#define smp$gq_ctd_wait_queue SMP$GQ_CTD_WAIT_QUEUE [#def]ine smp$gq_tree_upd_count SMP$GQ_TREE_UPD_COUNT [#define sch$gl_on_rad SCH$GL_ON_RAD [#define sch$gl_off_rad_skip SCH$GL_OFF_RAD_SKIP [#define sch$gl_off_rad_fallback SCH$GL_OFF_RAD_FALLBACK [#define sch$gl_exit_queue_rad SCH$GL_EXIT_QUEUE_RAD [#define sch$gl_def_rad_skip_cnt ] SCH$GL_DEF_RAD_SKIP_CNT [#define sch$gq_reserved00 SCH$GQ_RESERVED00 [#define sch$gq_reserved01 SCH$GQ_RESERVED01 [#define sch$gq_reserved02 SCH$GQ_RESERVED02 [#define glx$gpq_primary_cpu_array GLX$GPQ_PRIMARY_CPU_ARRAY [#define glx$gpq_part_node_flags GLX$GPQ_PART_NODE_FLAGS ] [#define exe$gs_npp_npool EXE$GS_NPP_NPOOL [#define exe$gs_bap_npool EXE$GS_BAP_NPOOL [#define exe$ga_rad_npp_lsthds EXE$GA_RAD_NPP_LSTHDS [#define sgn$gl_npagerad SGN$GL_NPAGERAD [#define ctl$gq_exception_flags CTL$GQ_EXCEPTION_FLAGS [#define sys$ar_d]cpi_mbx SYS$AR_DCPI_MBX [#define pms$gq_tqe_total PMS$GQ_TQE_TOTAL [#define pms$gq_tqe_sysub PMS$GQ_TQE_SYSUB [#define pms$gq_tqe_timer PMS$GQ_TQE_TIMER [#define pms$gq_tqe_wakeup PMS$GQ_TQE_WAKEUP [#define exe$gs_bap_base_lsthds EXE]$GS_BAP_BASE_LSTHDS [#define exe$gs_npp_base_lsthds EXE$GS_NPP_BASE_LSTHDS [#define mmg$ga_page_files MMG$GA_PAGE_FILES [#define smp$gl_cpu_upd_defer SMP$GL_CPU_UPD_DEFER [#define smp$ar_busywait_scc SMP$AR_BUSYWAIT_SCC [#define smp$ar_busywait_ticks SMP$AR_BUSYWAIT_TICKS ] [#define smp$gq_mpsynch_flags SMP$GQ_MPSYNCH_FLAGS [#define smp$ar_cpu_ring_pointer SMP$AR_CPU_RING_POINTER [#define smp$gl_dynamic_busywait SMP$GL_DYNAMIC_BUSYWAIT #define mtx$gq_debug MTX$GQ_DEBUG /* Reserved for mutex debugging */#define tr$gq_debug ] TR$GQ_DEBUG /* Reserved for general debugging */#define mpw$gq_debug MPW$GQ_DEBUG /* Reserved for modified page writer debugging */#define flt$gq_debug FLT$GQ_DEBUG /* Reserved for alignment fault debugging */#define prf$gq_debug ] PRF$GQ_DEBUG /* Reserved for performance debugging */[#define mmg$gq_pooltrace MMG$GQ_POOLTRACE #define glx$gq_hw_root_handle GLX$GQ_HW_ROOT_HANDLE /* Handle of tree's HW root node */#define lnm$gq_debug LNM$GQ_DEBUG /* ] Reserved for logical name debugging */#define exe$gl_pcb_cache EXE$GL_PCB_CACHE /* PCB Cache */#define mmg$gq_virbnd MMG$GQ_VIRBND /* Virtual boundary register value */#define smp$gl_sysptbr_ack_mask SMP$GL_SYSPTBR_ACK_MASK ] /* Ack mask for above routine */[#define swp$gl_last_rad_cpu SWP$GL_LAST_RAD_CPU [#define pms$gq_processes_created PMS$GQ_PROCESSES_CREATED [#define ioc$gl_mpdev_d2 IOC$GL_MPDEV_D2 [#define ioc$gl_mpdev_d3 IOC$GL_MPDEV_D3 [#define ioc$gl_mpdev_d4 ] IOC$GL_MPDEV_D4 [#define ioc$gl_mpdev_afb_intvl IOC$GL_MPDEV_AFB_INTVL [#define ioc$gl_mpdev_spare_1 IOC$GL_MPDEV_SPARE_1 [#define ioc$gl_mpdev_spare_2 IOC$GL_MPDEV_SPARE_2 [#define ioc$gl_mpdev_spare_3 IOC$GL_MPDEV_SPARE_3 [#define ioc$gl_mpdev_spare_4 IOC$GL_MPDEV_SPARE_]4 [#define exe$gq_hbvs_wlg EXE$GQ_HBVS_WLG [#define exe$gq_hbvs_wlg_1 EXE$GQ_HBVS_WLG_1 [#define exe$gq_hbvs_wlg_ena EXE$GQ_HBVS_WLG_ENA [#define exe$gq_hbvs_wlg_dis EXE$GQ_HBVS_WLG_DIS [#define exe$gq_hbvs_driver_cap EXE$GQ_HBVS_DRIVER_CAP [#define ex]e$gq_hbvs_scp_cap EXE$GQ_HBVS_SCP_CAP [#define exe$gq_hbvs_tbs_1 EXE$GQ_HBVS_TBS_1 [#define exe$gq_hbvs_tbs_2 EXE$GQ_HBVS_TBS_2 [#define ctl$gq_p0poolbase CTL$GQ_P0POOLBASE [#define ctl$gq_p1poolbase CTL$GQ_P1POOLBASE [#define mpw$gl_stackpages ] MPW$GL_STACKPAGES [#define exe$gq_rad_data_array EXE$GQ_RAD_DATA_ARRAY [#define exe$gl_radcnt EXE$GL_RADCNT [#define sys$gl_rmsd7 SYS$GL_RMSD7 [#define sys$gl_rms_seqfile_wbh SYS$GL_RMS_SEQFILE_WBH [#define exe$ar_usb_vector EXE$AR_USB_VECTOR ] [#define glx$gq_hard_partition_handle GLX$GQ_HARD_PARTITION_HANDLE [#define glx$gq_sw_root_handle GLX$GQ_SW_ROOT_HANDLE [#define tqe$gq_debug TQE$GQ_DEBUG [#define sgn$gl_dcl_ctlflags SGN$GL_DCL_CTLFLAGS [#define exe$gps_tqeidx_root_time EXE$GPS_TQEIDX_ROOT_TIME [#define exe$gps_tqeidx_r]oot_id EXE$GPS_TQEIDX_ROOT_ID [#define exe$gps_tqe_ovf_list_time EXE$GPS_TQE_OVF_LIST_TIME [#define exe$gps_tqe_ovf_list_id EXE$GPS_TQE_OVF_LIST_ID [#define exe$gps_tqeidx_start EXE$GPS_TQEIDX_START [#define exe$gps_tqeidx_free EXE$GPS_TQEIDX_FREE [#define exe$gl_tqeidx_free_count EXE$GL_TQEI]DX_FREE_COUNT [#define pms$gq_tqe_count PMS$GQ_TQE_COUNT [#define pms$gq_tqeins_count PMS$GQ_TQEINS_COUNT [#define pms$gq_tqermv_not_found PMS$GQ_TQERMV_NOT_FOUND [#define pms$gq_tqerem_count PMS$GQ_TQEREM_COUNT [#define pms$gq_tqerem_not_found PMS$GQ_TQEREM_NOT_FOUND [#def]ine pms$gq_tqe_ovf_insert PMS$GQ_TQE_OVF_INSERT [#define pms$gq_tqe_ovf_remove PMS$GQ_TQE_OVF_REMOVE [#define pms$gq_tqeidx_split_count PMS$GQ_TQEIDX_SPLIT_COUNT [#define pms$gq_tqeidx_contract_count PMS$GQ_TQEIDX_CONTRACT_COUNT [#define exe$gr_rad_data_cells EXE$GR_RAD_DATA_CELLS [#define exe$gr_rad_data_cells_end ] EXE$GR_RAD_DATA_CELLS_END [#define mmg$gq_sysptbr MMG$GQ_SYSPTBR [#define exe$gl_radid EXE$GL_RADID [#define exe$gq_rad_database EXE$GQ_RAD_DATABASE [#define rad$gq_reserved1 RAD$GQ_RESERVED1 [#define rad$gq_reserved2 RAD$GQ_RESERVED2 ] [#define rad$gq_reserved3 RAD$GQ_RESERVED3 [#define rad$gq_reserved4 RAD$GQ_RESERVED4 [#define rad$gq_reserved5 RAD$GQ_RESERVED5 [#define rad$gq_reserved6 RAD$GQ_RESERVED6 [#define rad$gq_reserved7 RAD$GQ_RESERVED7 [#define rad$gq_r]eserved8 RAD$GQ_RESERVED8 [#define pms$gq_rad PMS$GQ_RAD [#define sgn$gl_delprc_exit SGN$GL_DELPRC_EXIT [#define sgn$gl_phymem_config SGN$GL_PHYMEM_CONFIG [#define sgn$gl_ktk_d1 SGN$GL_KTK_D1 [#define sgn$gl_ktk_d2 SGN]$GL_KTK_D2 [#define sgn$gl_ktk_d3 SGN$GL_KTK_D3 [#define sgn$gl_ktk_d4 SGN$GL_KTK_D4 [#define sgn$gl_ktk_d5 SGN$GL_KTK_D5 [#define sgn$gl_ktk_d6 SGN$GL_KTK_D6 [#define sgn$gl_ktk_d7 SGN$GL_KTK_D7 ] [#define sgn$gl_ktk_d8 SGN$GL_KTK_D8 [#define sgn$gl_ktk_d9 SGN$GL_KTK_D9 [#define sgn$gl_ktk_d10 SGN$GL_KTK_D10 [#define sgn$gl_ktk_d11 SGN$GL_KTK_D11 [#define sgn$gl_ktk_d12 SGN$GL_KTK_D12 [#define smp$gq_min_cpu_feature]_mask SMP$GQ_MIN_CPU_FEATURE_MASK [#define smp$gl_nonprimary_console_io SMP$GL_NONPRIMARY_CONSOLE_IO [#define exe$gl_san_group EXE$GL_SAN_GROUP [#define exe$gq_san_auth EXE$GQ_SAN_AUTH [#define sgn$gl_fibre_scsi_rsv1 SGN$GL_FIBRE_SCSI_RSV1 [#define psx$ar_session_ids PSX$AR_SESSION_ID]S [#define psx$ar_leaderless PSX$AR_LEADERLESS [#define sgn$gl_defuid SGN$GL_DEFUID [#define sgn$gl_defgid SGN$GL_DEFGID [#define mmg$gq_pt_space_size MMG$GQ_PT_SPACE_SIZE [#define exe$ar_pal_proc EXE$AR_PAL_PROC [#define ]exe$gq_promote_kernel_va EXE$GQ_PROMOTE_KERNEL_VA [#define exe$gq_promote_kernel_length EXE$GQ_PROMOTE_KERNEL_LENGTH [#define exe$gq_promote_kernel_window EXE$GQ_PROMOTE_KERNEL_WINDOW [#define exe$gq_promote_kernel_next EXE$GQ_PROMOTE_KERNEL_NEXT [#define exe$gq_promote_exec_va EXE$GQ_PROMOTE_EXEC_VA [#define exe$gq_promote_exec_length ] EXE$GQ_PROMOTE_EXEC_LENGTH [#define exe$gq_promote_exec_window EXE$GQ_PROMOTE_EXEC_WINDOW [#define exe$gq_promote_exec_next EXE$GQ_PROMOTE_EXEC_NEXT [#define exe$gq_promote_super_va EXE$GQ_PROMOTE_SUPER_VA [#define exe$gq_promote_super_length EXE$GQ_PROMOTE_SUPER_LENGTH [#define exe$gq_promote_super_window EXE$GQ_PROMOTE_SUPER_WINDOW ] [#define exe$gq_promote_super_next EXE$GQ_PROMOTE_SUPER_NEXT [#define mmg$gq_memtest_active MMG$GQ_MEMTEST_ACTIVE [#define mmg$gq_pages_tested MMG$GQ_PAGES_TESTED [#define mmg$gl_gh_page_size_bits MMG$GL_GH_PAGE_SIZE_BITS [#define exe$gq_ivt_code_base EXE$GQ_IVT_CODE_BASE [#define exe$gq_ivt_dat]a_base EXE$GQ_IVT_DATA_BASE [#define exe$gpq_idt EXE$GPQ_IDT [#define swp$gq_wslbase SWP$GQ_WSLBASE [#define swp$gq_wsl_end SWP$GQ_WSL_END [#define swp$gl_wslotsz SWP$GL_WSLOTSZ [#define swp$gl_candidate SWP$GL_CA]NDIDATE [#define swp$gq_debug SWP$GQ_DEBUG [#define swp$gl_balcnt SWP$GL_BALCNT [#define sgn$gl_balsetmax SGN$GL_BALSETMAX [#define ctl$aq_regstack CTL$AQ_REGSTACK [#define ctl$aq_regstacklim CTL$AQ_REGSTACKLIM [#d]efine ctl$gq_ubsp_region_id CTL$GQ_UBSP_REGION_ID [#define ctl$gl_p2kt_area_pages CTL$GL_P2KT_AREA_PAGES [#define ctl$gq_p2kt_region_id CTL$GQ_P2KT_REGION_ID [#define ctl$gq_p2kt_region_base CTL$GQ_P2KT_REGION_BASE [#define smp$gpq_pib SMP$GPQ_PIB [#define exe$ar_fpswa ] EXE$AR_FPSWA [#define exe$ar_sal_proc EXE$AR_SAL_PROC [#define ocla$ar_pc_trace OCLA$AR_PC_TRACE [#define ocla$ar_va_trace OCLA$AR_VA_TRACE [#define exe$gpq_efi_system_table EXE$GPQ_EFI_SYSTEM_TABLE [#define exe$gpq_efi_runtime_services EXE$GPQ_EFI_RUNTIME_SER]VICES [#define exe$gq_sal_plabel EXE$GQ_SAL_PLABEL [#define exe$gpq_swis_low_va EXE$GPQ_SWIS_LOW_VA [#define exe$gpq_swis_high_va EXE$GPQ_SWIS_HIGH_VA [#define mmg$gl_itr_count MMG$GL_ITR_COUNT [#define mmg$gl_dtr_count MMG$GL_DTR_COUNT [#define mmg$ar]_min_itr_array MMG$AR_MIN_ITR_ARRAY [#define mmg$ar_min_dtr_array MMG$AR_MIN_DTR_ARRAY [#define swis$gpq_ring_buffer SWIS$GPQ_RING_BUFFER [#define swis$gpq_ring_buffer_end SWIS$GPQ_RING_BUFFER_END [#define swis$gpq_ring_buffer_next SWIS$GPQ_RING_BUFFER_NEXT [#define ioc$gl_mvsupmsg_intvl I]OC$GL_MVSUPMSG_INTVL [#define ioc$gl_mvsupmsg_num IOC$GL_MVSUPMSG_NUM [#define exe$gpq_indictment EXE$GPQ_INDICTMENT [#define exe$gpq_unwind EXE$GPQ_UNWIND [#define ctl$gpq_unwind CTL$GPQ_UNWIND [#define exe$gl_mrv_ordered_rads EXE$GL_MRV_ORDERED_RADS ^ [#define exe$gl_mrv_rad_hops EXE$GL_MRV_RAD_HOPS [#define exe$gl_shadow_site_id EXE$GL_SHADOW_SITE_ID [#define exe$gq_shadow_capabilities EXE$GQ_SHADOW_CAPABILITIES [#define pms$gl_tdcblk PMS$GL_TDCBLK [#define ctl$gq_log_bufadr CTL$GQ_LOG_BUFADR [#define ctl$gl_log_bufhead ^ CTL$GL_LOG_BUFHEAD [#define ctl$gl_log_buftail CTL$GL_LOG_BUFTAIL [#define ctl$gl_log_seqnum CTL$GL_LOG_SEQNUM [#define ctl$gl_log_bufsize CTL$GL_LOG_BUFSIZE [#define ctl$gl_log_bufcnt CTL$GL_LOG_BUFCNT [#define sys$gl_rmsd2 SYS$GL_RMSD2 ^ [#define sys$gl_rmsd3 SYS$GL_RMSD3 [#define sys$gl_rmsd4 SYS$GL_RMSD4 [#define sys$gl_rmsd5 SYS$GL_RMSD5 [#define exe$gq_testing123 EXE$GQ_TESTING123 [#define vms$gq_debug VMS$GQ_DEBUG [#define ^ du$gq_debug DU$GQ_DEBUG [#define tu$gq_debug TU$GQ_DEBUG [#define mscp$gq_debug MSCP$GQ_DEBUG [#define tmscp$gq_debug TMSCP$GQ_DEBUG [#define scs$gq_debug SCS$GQ_DEBUG [#define pe$gq_debug ^ PE$GQ_DEBUG [#define xfc$gq_debug XFC$GQ_DEBUG [#define dk$gq_debug DK$GQ_DEBUG [#define mk$gq_debug MK$GQ_DEBUG [#define io$gq_debug IO$GQ_DEBUG [#define lan$gq_debug LAN$GQ_DEBUG ^ [#define pk$gq_debug PK$GQ_DEBUG [#define pg$gq_debug PG$GQ_DEBUG [#define fg$gq_debug FG$GQ_DEBUG [#define mmg$gq_debug MMG$GQ_DEBUG [#define shad$gq_debug SHAD$GQ_DEBUG [#define rms$gq_debug^ RMS$GQ_DEBUG [#define xqp$gq_debug XQP$GQ_DEBUG [#define secur$gq_debug SECUR$GQ_DEBUG [#define wbm$gq_debug WBM$GQ_DEBUG [#define exec$gq_debug EXEC$GQ_DEBUG [#define exe$gq_spare1 EXE$GQ_^SPARE1 [#define exe$gq_spare2 EXE$GQ_SPARE2 [#define exe$gq_spare3 EXE$GQ_SPARE3 [#define exe$gq_spare4 EXE$GQ_SPARE4 [#define exe$gq_spare5 EXE$GQ_SPARE5 [#define exe$gq_rad_spare1 EXE$GQ_RAD_SPARE1 [^#define exe$gq_rad_spare2 EXE$GQ_RAD_SPARE2 [#define exe$gq_rad_spare3 EXE$GQ_RAD_SPARE3 [#define exe$gq_rad_spare4 EXE$GQ_RAD_SPARE4 [#define exe$gq_rad_spare5 EXE$GQ_RAD_SPARE5 [#define sgn$gl_testing123 SGN$GL_TESTING123 [#define sgn$gl_vcc_pagesize  ^ SGN$GL_VCC_PAGESIZE [#define sgn$gl_vcc_rsvd SGN$GL_VCC_RSVD [#define sgn$gl_rsvd_io_1 SGN$GL_RSVD_IO_1 [#define sgn$gl_rsvd_io_2 SGN$GL_RSVD_IO_2 [#define sgn$gl_rsvd_clu_1 SGN$GL_RSVD_CLU_1 [#define sgn$gl_rsvd_clu_2 SGN$GL_RSVD_CLU_2  ^ [#define sgn$gl_rsvd_exec_1 SGN$GL_RSVD_EXEC_1 [#define sgn$gl_rsvd_exec_2 SGN$GL_RSVD_EXEC_2 [#define sgn$gl_rsvd_secur_1 SGN$GL_RSVD_SECUR_1 [#define sgn$gl_rsvd_secur_2 SGN$GL_RSVD_SECUR_2 [#define sgn$gl_rsvd_lan_1 SGN$GL_RSVD_LAN_1 [#define sgn$ ^gl_rsvd_lan_2 SGN$GL_RSVD_LAN_2 [#define exe$gl_shadow_rec_dly EXE$GL_SHADOW_REC_DLY [#define exe$gl_shadow_d1 EXE$GL_SHADOW_D1 [#define exe$gl_shadow_d2 EXE$GL_SHADOW_D2 [#define exe$gl_shadow_d3 EXE$GL_SHADOW_D3 [#define exe$gl_shadow_d4  ^ EXE$GL_SHADOW_D4 [#define exe$gl_shadow_d5 EXE$GL_SHADOW_D5 [#define ctl$gq_stack_peak CTL$GQ_STACK_PEAK [#define ctl$gq_regstack_peak CTL$GQ_REGSTACK_PEAK [#define mmg$gq_stack_peak MMG$GQ_STACK_PEAK [#define mmg$gq_regstack_peak MMG$GQ_REGSTACK_PEAK  ^ [#define mmg$gq_kp_stack_peak MMG$GQ_KP_STACK_PEAK [#define mmg$gq_kp_regstack_peak MMG$GQ_KP_REGSTACK_PEAK [#define mmg$gq_kt_stack_peak MMG$GQ_KT_STACK_PEAK [#define mmg$gq_kt_regstack_peak MMG$GQ_KT_REGSTACK_PEAK [#define ioc$gl_devcfg_cbk IOC$GL_DEVCFG_CBK [#define ioc$gl_devcfg_coun^t IOC$GL_DEVCFG_COUNT [#define ioc$gl_devcfg_last_ucb IOC$GL_DEVCFG_LAST_UCB [#define ioc$gl_devcfg_full_scans IOC$GL_DEVCFG_FULL_SCANS [#define ctl$gl_brk_p0_count CTL$GL_BRK_P0_COUNT [#define ctl$gl_brk_neg_count CTL$GL_BRK_NEG_COUNT [#define wbm$gl_wbm_d1 WBM$GL_WBM_D1^ [#define pio$gl_rms_sts PIO$GL_RMS_STS [#define pio$gl_rms_stv PIO$GL_RMS_STV [#define ctl$gq_invo_context_user CTL$GQ_INVO_CONTEXT_USER [#define ctl$gq_invo_context_super CTL$GQ_INVO_CONTEXT_SUPER [#define ctl$gq_invo_context_exec CTL$GQ_INVO_CONTEXT_EXEC [#defin^e ctl$gq_invo_context_kernel CTL$GQ_INVO_CONTEXT_KERNEL [#define ctl$gq_tie_symvect CTL$GQ_TIE_SYMVECT [#define ctl$gq_iac_watch CTL$GQ_IAC_WATCH [#define tty$gl_defchar3 TTY$GL_DEFCHAR3 [#define sgn$gl_vhpt_size SGN$GL_VHPT_SIZE [#define lmf$gl_lmf_oe ^ LMF$GL_LMF_OE [#define pcs$gq_debug PCS$GQ_DEBUG [#define exe$gl_copy_merge_priority_fl EXE$GL_COPY_MERGE_PRIORITY_FL [#define exe$gl_copy_merge_priority_bl EXE$GL_COPY_MERGE_PRIORITY_BL [#define mmg$ar_gh_ps_vector MMG$AR_GH_PS_VECTOR [#define mmg$gl_gh_ps_maxidx MMG$GL_GH_PS_MAXIDX ^ #define exe$gl_hbvs_sda_trace EXE$GL_HBVS_SDA_TRACE /* Enable tracing any VU */#define exe$gl_hbvs_sda_trace_this_vu EXE$GL_HBVS_SDA_TRACE_THIS_VU /* Enable tracing this VU */#define exe$gl_hbvs_enable_trace_a EXE$GL_HBVS_ENABLE_TRACE_A /* Enable tracing for a subset of messages ^ */#define exe$gl_hbvs_enable_trace_n EXE$GL_HBVS_ENABLE_TRACE_N /* Enable tracing for a subset of messages */#define exe$gl_hbvs_enable_trace_c EXE$GL_HBVS_ENABLE_TRACE_C /* Enable tracing for a subset of messages */#define exe$gl_hbvs_enable_trace_d EXE$GL_HBVS_ENABLE_TRACE_D /* Enable tracing for a subset of ^messages */#define exe$gl_hbvs_check_shad EXE$GL_HBVS_CHECK_SHAD /* Enable sanity check for the SHAD */#define exe$gl_hbvs_check_ctxb EXE$GL_HBVS_CHECK_CTXB /* Enable sanity check for the CTXB */[#define exe$gl_shadow_hbmm_rtc_tmr EXE$GL_SHADOW_HBMM_RTC_TMR [#define exc$gq^_debug EXC$GQ_DEBUG #define boo$ga_swrpb BOO$GA_SWRPB /* Longword address of SWRPB */[#define exe$gq_vcons_plabel EXE$GQ_VCONS_PLABEL [#define exe$ar_vcons_service EXE$AR_VCONS_SERVICE #define swp$aq_swapper_regstack SWP$AQ_SWAPPER_^REGSTACK /* Pointer to the swapper's register stack */[#define efi$gq_loc_mmap EFI$GQ_LOC_MMAP [#define exe$ar_shsba_service EXE$AR_SHSBA_SERVICE [#define exe$gq_shsba_plabel EXE$GQ_SHSBA_PLABEL [#define pio$gq_free_gbsb PIO$GQ_FREE_GBSB [#define sgn$gl_fclan^_frame SGN$GL_FCLAN_FRAME [#define smp$gs_cbb_configure_set SMP$GS_CBB_CONFIGURE_SET [#define smp$gs_cbb_active_set SMP$GS_CBB_ACTIVE_SET [#define smp$gs_cbb_override_set SMP$GS_CBB_OVERRIDE_SET [#define smp$gs_cbb_potential_set SMP$GS_CBB_POTENTIAL_SET [#define smp$gs_cbb_tested_set SMP$GS_^CBB_TESTED_SET [#define smp$gs_cbb_present_set SMP$GS_CBB_PRESENT_SET [#define smp$gs_cbb_powered_set SMP$GS_CBB_POWERED_SET [#define smp$gs_cbb_autostart_set SMP$GS_CBB_AUTOSTART_SET [#define smp$gs_cbb_deferred_set SMP$GS_CBB_DEFERRED_SET [#define smp$gs_cbb_transition_set SMP$GS_CBB_TRANSITION_SET [^#define smp$gs_cbb_bug_done SMP$GS_CBB_BUG_DONE [#define xdt$gs_cbb_benign_cpus XDT$GS_CBB_BENIGN_CPUS [#define exe$gs_cbb_affinity EXE$GS_CBB_AFFINITY [#define sch$gs_cbb_idle_cpus SCH$GS_CBB_IDLE_CPUS [#define ioc$gs_cbb_interrupts IOC$GS_CBB_INTERRUPTS [#define sch$gs_cbb_no_ktb_cpus ^ SCH$GS_CBB_NO_KTB_CPUS [#define smp$gs_cbb_sysptbr_ack_mask SMP$GS_CBB_SYSPTBR_ACK_MASK [#define mmg$gs_cbb_memtest_active MMG$GS_CBB_MEMTEST_ACTIVE [#define smp$gs_cbb_tbi_ack_mask SMP$GS_CBB_TBI_ACK_MASK [#define smp$gs_cbb_ack_mask_mmg SMP$GS_CBB_ACK_MASK_MMG [#define smp$gq_max_supported_cpus SMP$GQ_MAX_SUPPORTED_^CPUS [#define pfn$ai_head PFN$AI_HEAD [#define pfn$ai_tail PFN$AI_TAIL [#define pfn$ai_color_head PFN$AI_COLOR_HEAD [#define pfn$ai_color_tail PFN$AI_COLOR_TAIL [#define mmg$gq_minpfn MMG$GQ_MINPFN [#define mmg$^gq_maxpfn MMG$GQ_MAXPFN [#define mmg$gq_maxmem MMG$GQ_MAXMEM [#define mmg$gq_min_node_pfn MMG$GQ_MIN_NODE_PFN [#define mmg$gq_max_node_pfn MMG$GQ_MAX_NODE_PFN [#define mmg$gq_min_shared_pfn MMG$GQ_MIN_SHARED_PFN [#define mmg$gq_max_shared_pfn ^ MMG$GQ_MAX_SHARED_PFN [#define boo$gq_nextpfn BOO$GQ_NEXTPFN [#define mmg$gq_window_pte MMG$GQ_WINDOW_PTE [#define mmg$gq_window2_pte MMG$GQ_WINDOW2_PTE [#define exe$gq_blakhole EXE$GQ_BLAKHOLE [#define mmg$gl_syi_pfn_memory_map_64 MMG$GL_SYI_PFN_MEMORY_MAP_64 ^ [#define pio$gl_initial_gbsb PIO$GL_INITIAL_GBSB [#define pfn$ai_count PFN$AI_COUNT [#define pfn$ai_lolimit PFN$AI_LOLIMIT [#define pfn$ai_hilimit PFN$AI_HILIMIT [#define sch$gi_mfylolim SCH$GI_MFYLOLIM [#define sch$gi_freelim ^ SCH$GI_FREELIM [#define sch$gi_freecnt SCH$GI_FREECNT [#define sch$gi_freereq SCH$GI_FREEREQ [#define sch$gi_mfycnt SCH$GI_MFYCNT [#define sch$gi_mfylim SCH$GI_MFYLIM [#define ldr$gq_public_image_list LDR$GQ_PUBLIC ^_IMAGE_LIST [#define mmg$gq_fluid_pgcnt MMG$GQ_FLUID_PGCNT [#define mmg$gq_phypgcnt MMG$GQ_PHYPGCNT [#define mmg$gq_memsize MMG$GQ_MEMSIZE [#define mmg$gq_shared_l2pt_pfn MMG$GQ_SHARED_L2PT_PFN [#define sch$gq_mfylimsv SCH$GQ_MFYLIMSV [#defin!^e sch$gq_mfylosv SCH$GQ_MFYLOSV [#define exe$gq_pshared EXE$GQ_PSHARED #define ctl$gq_ieee_wpfp_hw CTL$GQ_IEEE_WPFP_HW /* Hardware whole pgrm FP default (FPSR on Itanium) */#define ctl$gq_ieee_wpfp_sw CTL$GQ_IEEE_WPFP_SW /* Software whole pgrm FP default (IEEE struct with not al"^l bits used) */[#define exe$aq_erlbufadr_s2 EXE$AQ_ERLBUFADR_S2 [#define exe$gl_erlbufhead_s2 EXE$GL_ERLBUFHEAD_S2 [#define exe$gl_erlbuftail_s2 EXE$GL_ERLBUFTAIL_S2 [#define sys$gl_erlbufpagelets_s2 SYS$GL_ERLBUFPAGELETS_S2 [#define sys$gl_erlbufcnt_s2 SYS$GL_ERLBUFCNT_S2 [#define sys$gl_erlbufcnt SYS$GL_ERLBUFCNT [#define sgn$gl_erlbufpagelets_s2 SGN$GL_ERLBUFPAGELETS_S2 [#define sgn$gl_erlbufcnt_s2 SGN$GL_ERLBUFCNT_S2 [#define fc$ar_protocols_vector FC$AR_PROTOCOLS_VECTOR [#define fc$ar_wtid_queue FC$AR_WTID_QUEUE ww